1980_AMI_MOS_Products_Catalog 1980 AMI MOS Products Catalog

1980_AMI_MOS_Products_Catalog 1980_AMI_MOS_Products_Catalog

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Copyright© 1980

AIMIIe American Microsystems, Inc.
(All rights reserved) Trade Marks Registered®
Information furnished by AMI in this catalog is believed to be accurate and reliable. Devices sold
by AMI are covered by the warranty and patent indemnification provisions appearing in its
Terms of Sale. AMI makes no warranty, express, statutory,implied, or by description regarding
the information set forth herein or regarding the freedom of the described devices from patent
infringement. AMI reserves the right to change specifications and prices at any time and without
notice.
Advanced Product Description means that this product has not been produced in volume, the
specifications are preliminary and subject to change, and device characterization has not been
done. Therefore, prior to designing this product into a system, it is necessary to check with AMI
for current information.
Preliminary means that this product is in limited production, the specifications are preliminary
and subject to change. Therefore, prior to designing this product into a system, it is necessary to
check with AMI for current information.
This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such
as military, medical life-support or life-sustaining equipment are specifically not recommended
without additional processing by AMI for such application.

~II®

1980
MOS Products Catalog

AMII~

Introduction

American Microsystems, Inc., the first commercial producer of MOS/LSI beginning in 1966, is a major designer,
manufacturer and marketer of circuits for the consumer, EDP and communications markets.
AMI is the leading designer of custom LSI, makes and markets its proprietary S2000 family of 4-bit microcomputers,
is a major alternate source for the S6800 8-bit microprocessor family and the only alternate source for the S9900
16-bit family of microprocessors. The Company provides the market with selected 1K and 4K low power CMOS
Static RAMs, 16K and 32K ROMs.
The most experienced designer of systems-oriented MOS/LSI communication circuits, AMI provides components for
station equipment, P ABX and Central Office Switching systems, data communications and advanced signal processing applications.
AMI is pioneering in same-chip integration of digital and analog circuitry, and is a recognized leader in switched
capacitor filter technology.
Processing capability includes N-Channel, advanced silicon gate CMOS and the largest production capability
available in P-Channel.
Headquartered in Santa Clara, California, AMI has design centers in Santa Clara, Pocatello, Idaho and Swindon,
England. Wafer fabricating plants are in Santa Clara and Pocatello, and assembly facilities are in Seoul, Korea and
the Philippines.
Field sales offices are located throughout the United States, in Europe and in the Far East. Their listing, plus those of
domestic and international representatives and distributors appear on pages B.27 through B.31 of this publication.

AMII

A. Indices

o
o
o

Numerical
Functional
Cross-Reference

1. Custom Capabilities
2. Communication Products
3. Consumer Products
4. S2000 Family
5. S6800 Family
6. S9900 Family
7. Microprocessor/Microcomputer Development
Systems Products
8. Random Access Memories (RAMs)
9. Read Only Memories (ROMs)
10. UV EPROMs
11. Uncommitted Logic Arrays
12. Application Note Summary
B. General Information
MOS Handling
MOS Processes
Product Assurance
Military Products Screening Program
Packaging
Ordering Information
Terms of Sale
D AMI Sales Offices
o Domestic Representatives
[J Domestic Distributors
[J European Representatives and Distributors

D
D
D
D
IJ
D
D

Table of Contents

Indices

I

AMII~

Numerical Index
Page

Device

Page

Device

AMI Cross 8upport ...
AMI Pascal ..........
810110 ................
810111 ..............
810129 ..............
810130 ..............
810131 ..............
810377 ..............
810430 ..............
81103A ..............
81602 ................
81856 ................
82000 ................
82000A ..............
82150 ................
82150A ..............
82152 ................
82200 ................
82200A ..............
82210 ................
82350 .................
82400 ................
82400A ..............
82559A ..............
82559B ..............
82559C ..............
82559D ..............
82560A ..............
82561 ................
82561A ..............
82561C ..............
82562 ................
82567 ................
82600 ................
82601 ................
82688 ................
82709 ................
82742 ................
82743 ................
82809 ................
82811 ................
82814 ................
82859 ................
82860 ................
82861A ..............
82861B ..............
83501 ................
83501A ..............
83502 ................
83502A ..............

7.2
7.3
3.45
3.49
3.52
3.54
3.56
3.58
3.62
8.2
5.101
3.32
4.4
4.4
4.4
4.4
4.4
4.6
4.6
4.6
5.112
4.6
4.6
2.3
2.3
2.3
2.3
2.30
2.39
2.39
2.39
2.47
3.68
3.3
3.3
3.70
3.37
3.9
3.9
3.41
2.71
2.90
2.13
2.21
2.27
2.27
2.57
2.57
2.57
2.57

83503 ................
83504 ................
83525A ..............
83525B ..............
84264 ................
850240 ..............
850241 ..............
850242 ...............
850243 ..............
850244 ..............
850245 ..............
85101L ..............
85101L-1 ............
85101L-3 ............
85101L-8 ............
85101-8 ..............
85204A .............
86504 ................
86508 ................
86508A ..............
86508A-1 ............
86508-1 ..............
86514 ................
86800 ................
868AOO ..............
868BOO ..............
868HOO ..............
86801 ................
86801(E) .............
86802 ................
868A02 ..............
86803 ................
86803N/R ............
868045 ..............
868047 ..............
86805 ................
86808 ................
868A08 ..............
86809(E) . ............
868A09(E) . ..........
868B09(E) ...........
86810 ................
868A10 . .............
868B10 ..............
86810-1 ..............
86821 ................
868A21 ..............
868B21 ..............
868H21 ..............

A.2

2.70
2.70
2.92
2.92
9.8
3.85
3.85
3.85
3.2
3.2
3.2
8.3
8.3
8.3
8.3
8.3
10.2
8.8
8.9
8.9
8.9
8.9
8.14
5.3
5.3
5.3
5.7
5.10
5.10
5.46
5.46
5.2
5.2
5.135
5.156
5.50
5.73
5.73
5.74
5.74
5.74
5.190
5.190
5.190
5.2
5.120
5.120
5.120
5.126

Device
86831B ..............
868332 ..............
86834 ...............
86834-1 .............
868364 ..............
86840 ................
868A40 ..............
868B40 ..............
86846 ................
868488 ..............
86850 ................
868A50 ..............
868B50 ..............
86852 ................
868A52 ..............
S68B52 ..............
86854 ................
868A54 ..............
868B54 ..............
86894 ................
88890 ................
89260 ................
89261 ................
89262 ................
89263 ................
89264 . ...............
89265 . ...............
89266 ................
89660 ................
89900 ................
89901 ................
89902 ................
89940 ................
89980A ..............
89981 ................
8E 82000/82150 ......
TCK-100 .............

Page
9.2
9.5
10.4
10.4
8.2
5.130
5.130
5.130
5.150
5.183
5.168
5.168
5.168
5.173
5.173
5.173
5.178
5.178
5.178
5.188
3.73
3.14
3.14
3.21
3.14
3.14
3.14
3.21
3.80
6.3
6.15
6.18
6.7
6.11
6.11
7.6
3.28

Functional Index
Device

Page

Communication Products

8tation Products
82559A ..............
82559B ..............
82559C ..............
82559D ..............
82859 ................
82860 ................
82861A ..............
82861B ..............
82560A ..............
82561 ................
82561A ..............
82561C ..............
82562 ................
PCM Products
83501 ................
83501A ..............
83502 ................
83502A ..............
83503 ................
83504 ................

2.3
2.3
2.3
2.3
2.13
2.21
2.27
2.27
2.30
2.39
2.39
2.39
2047
2.57
2.57
2.57
2.57
2.70
2.70

Other Communication Products
82811 ................ 2.71
82814 ................ 2.90
83525A .............. 2.92
83525B .............. 2.92
Consumer Products

Remote Control Circuits
82600 ................
82601 ................
82742 ................
82743 ................

3.3
3.3
3.9
3.9

TouchControl Interface Circuits
89260 ................ 3.14
89261 ................ 3.14
89262 ................ 3.21
89263 ................ 3.14
89264 ................ 3.14
89265 ................ 3.14
89266 ................ 3.21
TCK-100 ............. 3.28
Consumer Circuits
81856 ................
82709 ................
82809 ................

3.32
3.37
3041

Organ Circuits
810110 ..............
810111 ..............
810129 ..............
810130 ..............
810131 ..............
810377 ..............

3045
3049
3.52
3.54
3.56
3.58

Device

Page

Device

Page

810430 ..............
82567 ................
82688 ................
88890 ................
89660 ................
850240 ..............
850241 ..............
850242 ..............
850243 ..............
850244 ..............
850245 ..............

3.62
3.68
3.70
3.73
3.80
3.85
3.85
3.85
3.2
3.2
3.2

868A50 ..............
868B50 ..............
86852 ................
868A52 ..............
868B52 ..............
86854 ................
868A54 ..............
868B54 ..............
868488 ..............
86894 ................
86810 ................
868AlO ..............
868B10 ..............
86810-1 ..............

5.168
5.168
5.173
5.173
5.173
5.178
5.178
5.178
5.183
5.188
5.190
5.190
5.190
5.2

89900 Family
89900 ................
89901 ................
89902 ................
89940 ................
89980A ..............
89981 ................

6.3
6.15
6.18
6.7
6.11
6.11

Microprocessors/
Microcomputers

82000 Family
82000 ................
82000A ..............
82150 ................
82150A ..............
82152 ................
82200 ................
82200A ..............
82210 ................
82400 ................
82400A ..............

404
404
404
404
404
4.6
4.6
4.6
4.6
4.6

86800 Family
86800 ................
868AOO ..............
868BOO ..............
868HOO ..............
86801 ................
86801E .......... ,...
86802 ................
868A02 ..............
86803 ................
86803N/R ............
86805 ................
86808 ................
868A08 ..............
86809(E) .............
868A09(E) ...........
868B09(E) ...........
81602 ................
82350 ................
86821 ................
868A21 ..............
868B21 ..............
868H21 ..............
86840 ................
868A40 ..............
868B40 ..............
868045 ..............
86846 ................
868047 ..............
86850 ................

5.3
5.3
5.3
5.7
5.10
5.10
5046
5046
5.2
5.2
5.50
5.73
5.73
5.74
5.74
5.74
5.101
5.112
5.120
5.120
5.120
5.126
5.130
5.130
5.130
5.135
5.150
5.156
5.168

A.3

Microprocessor/
Microcomputer Development
Systems Products

AMI Cross 8upport ...
AMI Pascal..........
8E82000/82150 ......

7.2
7.3
7.6

Memory Products

RAMs
86810 ................ 5.190
868A10 .............. 5.190
868B10 .............. 5.190
86810-1 .............. 8.2
85101L .............. 8.3
85101L-1 ............ 8.3
85101L-3 ............ 8.3
85101L-8 ............ 8.3
85101-8 .............. 8.3
86504 ................ 8.8
86508 ................ 8.9
86508A .............. 8.9
86508A-1 ............ 8.9
86508-1 .............. 8.9
86514 ................ 8.14
ROMs
86831B .............. 9.2
868332 .............. 9.5
84264 ................ 9.8
868364 .............. 8.2
EPROMs
85204A ............. 10.2
86834 .............. lOA
86834-1 ............. lOA

•

AMlt.

Cross Reference Guide
Communication Products

Codes

(D) - Direct Replacement

(C) - Codec Only, No Filters

General
Instruments

(F) - Functional Replacement

Intel

Mitel

Mostek

Motorola

National

-

-

-

MK-5086(D)

-

-

-

-

-

-

MK-5086(D),
MK-5087(F)

-

-

82559D

-

-

-

-

-

-

82560A

A Y-5-9151(F),
A Y-5-9152(F)

-

MT-4320(F)

MK-5098(F),
MK-5099(F)

-

MM-5393(F),
MM-53190(F)

-

AMI
82559A
82559B
82559C

82561

-

-

-

-

-

82561A

-

-

ML-8204(F)

-

-

-

-

-

MK-5170(F)

-

-

-

-

82562

TZ-2001(F)

-

-

82859

-

-

-

-

-

-

-

MK-5089(F)
MK-5087(F)

82561C

82860
82861A
82861B
83501/83502

-

-

-

-

-

-

2910/2912(F)

-

MK-5151(FC)

MC-144061

-

-

14414(F)

-

83503/83504

-

2911/2912(F)

MK-5156(FC)

MC-144071

-

14414(F)

-

83525A/B

-

-

-

MT-8865(F)

-

Memory Products
NM08ROMs

CMOS RAMs
Vendor

256X4

1KX1

IKX4

4KXl

2KX8

4KX8

8KX8

AMI

85101

86508

86514*

86504*

86831B

868332

868364*

-

-

-

-

9216
8316
3516

9232
2332

AMD
EA
FSC
FUJIT8U
GI
HARRI8
HITACHI
INTEL
INTER8IL
MARUM AN
MIT8UBI8HI
M08TEK
MOTOROLA
NATIONAL
NEC

-

8414
-

8404

-

-

9316

9332

6514
4334

6504
4315

6504
-

-

-

-

2316

2332

2364

2316

2332

2364

-

58733

-

68332
52132
2332

37000
68364
52164
2364

-

-

2316
8316
2600

8332
2632

2664

2316

-

-

2316
8316
331

2332
4732
333

-

6561
435101
5101
6551
-

6508

-

6508

-

145101
74C920
5101

146508
74C929
6508

OKI
RCA
ROCKWELL
8IEMEN8
8IGNETIC8

573
5101

574
1821

-

-

8G8
SS8
SYNERTEK
TI
T08HIBA

-

-

-

5101
5101

5102
5102

5101

5508

-

-

-

-

-

-

-

-

-

-

6514

-

-

-

-

-

58731
34000
68316
2316
2316

-

-

3870

1825

5104

-

146504
6504

444

-

-

-

5514

-

5504

*To Be Announced

A.4

-

-

-

-

-

9364

-

-

2364
4764

-

AMII~

Cross Reference Guide
86800 Family

AMI

Fairchild

General
Instruments

Hitachi

Motorola

National

Texas Instruments

81602

-

AY-3-1014

-

-

MM5303N

TM86011

82350

-

-

-

-

-

-

86800

F6800

-

HD46800

MC6800

-

-

86801

-

-

-

MC680l

86802

F6802

-

HD46802

MC6802

-

86805

-

-

HD46805

MC6805

-

-

86808

F6808

-

HD46808

MC6808

-

-

-

-

86809

-

-

MC6809

-

86810

F6810

-

HD468l0

MC6810

-

-

86821

F6821

-

HD46821

MC6821

-

-

-

86840

F6840

-

HD46840

MC6840

-

-

86846

F6846

-

HD46846

MC6846

-

-

86850

F6850

-

HD46850

MC6850

-

-

86852

F6852

-

HD46852

MC6852

-

-

-

-

86854

F6854

-

HD46854

MC6854

868488

F68488

-

HD468488

MC68488

86894

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

868045
868047

89900 Family
AMI

Texas Instruments

89900

TM89900

89901

TM89901

89902

TM89902

89903

TM89903

89940

TM89940

89980

TM89980

89981

TM89981

A.5

Custom Capabilities

I

Custom Capabilities

AMI's Six Step Program
for Success in Custom LSI.

Step One: Considering all the Factors.
There are many ways to build your product, so, why do
we believe the custom MOS/LSI approach is right for
you? For the answer let's look at the alternatives:

No other company can match AMI's track record in
developing state-of-the-art custom MOS products. With
more than 1,400 custom devices designed and manufactured since 1967, AMI has more experience than any
other integrated circuit company in building a wide variety of custom microcircuits.

Electromechanical. These assemblies suffer compared
to MOS circuits: in reliability because moving parts
wear; in convenience because of the greater space
needed; and because of their limits in handling highly
complex functions.

AMI not only has the experience but the design engineering organization and the advanced production and testing facilities to produce the highest quality MOS/LSI circuits. Because AMI also offers standard memory, microprocessor, telecommunication and consumer products
and the widest variety of custom LSI processes in the
industry, we're able to be objective in helping customers
determine their most cost effective approach.

Hardwired Logic. This is more expensive due to the high
labor and material cost involved. Much space is needed
and power is much higher than for MOS/LSI circuits.
Standard Circuits. Standard ICs perform the same jobs
as custom ICs but require more devices, higher assembly
costs, more power and space with lower reliability.

AMI can participate at any level of
the custom LSI process.
We participate at any level in the design of the custom
IC, from the classic "we'll-design-and-produce-it-for-you"
approach where we have complete responsibility, to the
"Customer Tooling" cooperative approach for customers
who do their own design but want us to do the manufacturing. We will even enter into long-term, fully-funded
joint development agreements, designing ICs for families
of end products, joining together your systems designers
with our circuit designers.
We've developed a six step program in which you, the
customer, can work with us to successfully develop the
custom IC for your product by:
1. Considering All the Factors.
2. Looking At the Custom Options.
3. Selecting the Right MOS/LSI Process.
4. Designing The Best Circuit.
5. Fabricating the Optimum Device.
6.. Testing For Reliable Performance.

Microprocessors. Using standard microprocessors requires several microcircuits, and much of the device's
capability may not be needed. A custom circuit, however,
can combine all your needed functions on one IC, conserving space and cost.

The custom MOS/LSI decision
The advantages of custom MOS/LSI circuits become
more apparent when considered in relation to IC complexity, component count, power consumption and confidentiality (it's your circuit exclusively).
Complexity. An application suitable for custom LSI is
usually one needing moderately complex circuits or functions; i.e., more than 100 to 500 gates. Fewer than this
might not justify the engineering, design, and manufacturing effort required for the custom IC.
Custom LSI may be the only way technically to achieve a
desired result, no matter what the development cost.

Component Count. An important consideration affecting
cost is the number of components in a system that are
eliminated by the substitution of a single custom LSI circuit. A reduction in component count significantly lowers
the number of electrical interconnections and increases
product reliability.

The results are a unique product designed to your complete satisfaction.

This factor often reduces troubleshooting problems at
the board, subsystem and system levels, minimizes field

1.2

Custom Capabilities

repairs and usually reduces warranty costs. The reduction in component count also decreases assembly and initial checkout costs.
Power Consumption. The amount of power required to
operate an end product is increasingly an important consideration. MOS/LSI circuits require much less power
than the electro-mechanical and hardwired logic alternatives. A custom MOS/LSI solution usually requires less
power than the multi-chip alternatives offered by standard circuits and microprocessors. For battery operated
designs, we offer custom, high performance/ultra-low
power complementary MOS (CMOS) capability.
Confidentiality. Of prime concern in any highly competitive market situation is confidentiality of design. AMI
treats each circuit assignment as a highly proprietary
project insuring complete security to, and through, the
product's manufacturing life.

Step Two: Looking at the Custom Options.
There are two basic ways AMI teams up with its
customers, although we are very flexible:

o

AMI designs and makes the circuit to meet customer
requirements; or,

o

the customer designs the IC with AMI assistance and
AMI produces it.

The total AMI approach
AMI's custom capability encompasses the entire development sequence of a product. The services we provide
start with five conceptual planning steps:

o

System Definition;

o System Design and Partitioning;
o Preliminary Logic Design/Simulation;

o
o

Final Logic Design; and
LSI Circuit Design.

First, system definition requires the customer to have
full knowledge of the system requirements for the custom IC. Working with AMI's application engineers, the
two companies form a team to develop a final system
which not only meets the needs, but optimizes performance and economics.
Second, system partitioning follows the joint development of system definition. This involves the cataloging of
functions into MOS subfunctions, and then into chip

functions. At this step the optimum MOS process for the
application is chosen. Usually, functional flow charts and
timing diagrams are generated at this time as a preliminary step in logic design.
Once partitioning is complete, preliminary logic design
and simulation can be done. The chip functions are translated into MOS logic diagrams. Traditional breadboarding techniques are quite often used to verify these logic
designs. AMI uses proprietary computerized simulation
programs for verification. These programs check the
design as well as help reduce time and cost factors for
design verification.
Final logic design is next. First, system errors discovered
through breadboarding or simulation are corrected.
Earlier partitioning may be refined if the final logic
design indicates the need. During the final logic design
step all system design objectives are analyzed again.
MOS logic diagrams are finalized, the chip sizes are
estimated, and testing procedures are generated.
And then - the chip design. The topological chip layout is
a precise science. The exact dimensions and placement
for each transistor and other components must be determined. Here again AMI uses computerized circuit analysis programs to validate chip designs and verify that
the design meets the performance objectives. The computerized analysis not only substantiates logic, it is an
integral part of the on-going quality assurance program
at AMI.

The cooperative approach
In this approach, the customer designs the circuit and
has complete control over the logic and electrical requirements, the design budget and schedule, and the design
changes prior to tooling.
Design workshops, consultation and information documentation packages are provided by us depending on the
needs of the customer. We divide our customer interfacing into four phases: Phase 1 is a feasibility study; Phase
2 is a preliminary wafer fabrication or sample run; Phase
3, pre-production yield evaluation; and Phase 4,
production.
Phase 1 begins before MOS logic is drawn. AMI
customer tooling engineers provide suggestions on MOS
design, discuss process and design rule parameters, provide a standard device, help plan ahead for testing, and
provide information on packaging and tooling interface.
Our experience has shown that the customer tooling interface works best when the customer is aware from the
1.3

Custom Capabilities
start of how we will make the device. If it's already been
designed, Phase 1 begins when AMI provides a process
and design rule questionnaire. This gives us information
about packaging requirements, testing needs and tooling
interface level. Our customer tooling experts review the
data to see if AMI can meet all the requirements. At the
end we supply at no charge a program plan, a firm quotation for the next two phases, and a budget quote for
production.
During Phase 2 we'll process one wafer lot and then map,
optically inspect, package and ship sample quantities of
untested les, and, if the customer requires them, several
untested wafers. Furthermore, AMI guarantees these
samples will be within the agreed parameters and will
meet our standards of quality and workmanship. The
customer can supply working plates for Phase 2, or AMI
will accept pattern generator tapes or lOx reticles.
After the customer approves the Phase 2 sample devices,
AMI moves to Phase 3: pre-production yield evaluation.
Here we guarantee the required manufacturing documentation, run acceptances on the test program, and build
the wafer probe cards and the program board for AMI
testers. We then make several reproducibility runs of
wafers and sort them for yield information.
From these runs AMI engineers will assemble and final
test a number of good devices. The unit cost for them will
be based on the costs of assembly, type of package and
final test. These units provide the customer with a low
volume production run for additional evaluation and
start-up production commitments.
Pre-production deliveries actually start during Phase
3. Initial production deliveries during Phase 4 usually
begin 9 to 11 weeks after approval of the pre-production
units.

.. . But there are other options
We're not biased particularly in favor of custom LSI,
especially if it becomes clear it's not the best way to solve
a customer problem. AMI is also a major microprocessor
supplier in the 4-,8-, and 16-bit categories: our own family of S2000 single chip microcomputers, the Motoroladesigned 6800, and Texas Instrument's 9900 product
line, respectively.
By having available both custom LSI and standard microprocessors, we can offer customers alternatives that
can also combine the two. For example, to test the
market for a new product, we can design a microprocessor-based system which provides a relatively quick,
though not necessarily cost effective way to get a product to market. As part of the approach, we customize
the microprocessor program or "software," and then, if

the product is successful, design and make a custom LSI
circuit dedicated to that particular application.
But if a microprocessor-ours or anyone else's-is the
best solution, custom LSI is still useful, for microprocessors can't operate alone. They need interface devices.
To achieve a system with a minimum chip count, custom
devices can be designed to allow the customer to efficiently interface standard microprocessors with the customer's system.

Step Three: Choosing the right
MOS/LSI process.
One of the most important decisions to be made in the
custom LSI approach is determining the right MOS/LSI
process.
Where many of our competitors offer one, and possibly
two MOS processes with which to build devices, AMI offers seven custom MOS process options, more than any
other company supplying custom circuits. They are:

P-channel high voltage metal gate
This is the most mature process in the industry and
because of its relative simplicity, has the lowest cost per
wafer. It provides high noise immunity, making it ideal
for applications involving mechanical equipment which
can generate RF noise and where low power dissipation is
not a prime requirement.

P-channel ion implanted metal gate
This is very similar to its high voltage P-channel process,
with two additional processing steps. An ion implantation of the gate areas reduces the device thresholds to
levels consistent with the low voltage P-channel process
while at the same time retaining the high field thresholds
of the high voltage process.
A second ion implant in selected gate regions reduces
those thresholds to the point of forcing depletion mode
transistor operation. The use of depletion mode devices
as load transistors greatly increases device speed per unit
area, can lower power, improve noise margins, makes
bipolar interfacing easier, permits the use of unregulated
power supplies, and allows generation of full amplitude
signals on chip with only one power supply. This latter
feature can be especially useful in converting certain logic
implementations to much simpler forms which thereby
reduce chip area significantly. This process has been used
in several different standard memory products as well as
many custom chip applications where speed, noise immunity and wide power supply tolerances are specified.

1.4

Custom Capabilities
P-channel silicon gate (SiGate)

other processes, but this is decreasing with advanced
CMOS techniques. CMOS chips are currently used in low
power, often battery operated applications such as electronic watches, clocks, and memories where the ability to
work at very low power is an absolute requirement, and
in automotive electronics, where low standby current and
high noise immunity are important. CMOS is also making important inroads into microprocessors and communications circuitry.

This process has two main features: (1) somewhat
smaller transistor structures due to a self-aligning fabrication technique that eliminates certain masking
tolerance problems, and (2) a partial third layer of interconnect which can sometimes significantly reduce cell
area and interconnections between cells. The self-aligning
gate structure lowers the effective gate capacitance. The
circuit response is faster than regular P-channel low
voltage devices, but slower than ion implanted circuits
with depletion mode load devices. This process has been
mostly used in memory applications and in customer
tooled circuits. AMI no longer designs products in this
process.

Present CMOS technologies include both standard metal
gate and silicon gate, as well as a high density, isoplanar
silicon gate process.

Five-Micron CMOS
AMI's major second generation 5-micron CMOS process
uses an n+ only ubiquitous Powell approach to improve
performance, simplify layout and reduce circuit size. This
process permits implanting in the field oxide region, thus
eliminating guard rings. AMI's process also reduces
Powell doping levels below alternative 5-micron processes
and consequently lowers junction capacitances and increases switching speeds.

N-channel silicon gate
This process uses ion implantation in the field areas to
achieve high field threshold without having to resort to
thick field oxides. Then the gate regions are implanted to
establish the required control of device thresholds. This
process is designed for single supply circuits that do not
have stringent performance requirements but must have
significant packing densities. This packing density
results from the following: (1) for a given device
N -channel can charge or discharge a mode faster than
P-channel, (2) the self-aligning feature of the process,
and, (3) the extra layer of interconnect inherent in silicon
gate which can be used to reduce chip interconnect area.

We use this 5-micron process to design and produce switched capacitor circuits for analog and digital functions.
Among the kinds of circuits that can benefit enormously
from mixed digital-analog approaches are low-noise,
high-gain op amps, high-speed offset-cancelled comparators and high-current line buffers. CMOS linear subsystems have appeared on AMI-designed circuits to perform A to D and D to A conversion, switched capacitor
filtering and quasi-adaptive phase lock and auto-zero
loops. System level integrated circuits have been designed and fabricated for complex filter functions, DTMF,
MF and SF receivers, low and medium speed modems,
codecs, voice compression, industrial control and voice
synthesis.

N-channel ion implanted SiGate
with depletion loads
This is a high performance process; it offers all the advantages of the N-channel, ion implanted SiGate process
plus the increased speed associated with depletion loads.
The drawback to this process lies in the increased complexity of the additional processing steps.

Complementary MOS (CMOS)
The CMOS technology has many advantages. Its biggest
asset is that CMOS draws very little power. The majority of the power is consumed when switching occurs.
Under static conditions or during power down CMOS
dissipates virtually no DC power. CMOS is also very
fast, and it has very high noise immunity, comparable to
ion implanted circuits using depletion mode transistors.
Like ion implanted depletion mode circuits, CMOS can
work over a very wide single supply power range. The
area used per logic function has been larger than with

Step Four: Designing the best circuit.
A key to AMI's success in the custom LSI business is its
Computer-Aided Design (CAD) capability. Our CAD capabilities, the most advanced in the semiconductor industry, are based on a wealth of experience in custom
MOS/LSI circuit design work. CAD software and hardware aids are employed throughout the custom IC development cycle, from the early logic design stage to creation of production tooling.
1.5

Custom Capabilities
Logic Simulation
Early in the design phase logic simulation is used to
verify that the logic is sound. The circuit is extensively
simulated to verify logical correctness as well as timing
and signal propagation characteristics. Logic simulation
is used throughout the design cycle from hierarchical
block-level logic design to test program generation.
SIMAD is an MOS oriented four-state logic simulator
which supports assignable rise and fall switching delay.
It includes such features as:

o block-oriented input notation, including macros, Boolean expressions, and array notation;
D basic logic gates, several types of MOS transmission
gates, RAMs, ROMs, shift-registers, and user specified combinational logic gates;
D four-state

(~,

1, u, z) simulation;

D multi-phase user specified clocking schemes;

region DC operation; body effect as a function of substrate bias; channel length modulation in saturation;
mobility reduction at elevated gate voltages; channel
pinchoff; short channel effects; weak inversion; as well as
full non-linear voltage-dependent modeling of the MOS
capacitors which determine device transient behavior.

Symbolic mask design using SIOS
AMI has developed an advanced symbolic mask design
system for MOS ICs. This Symbolic Interactive Design
System (SIDS) reduces the total mask design cycle time
as much as 50 percent, with half the manpower effort and
half the cost of the hand drawn approach. SIDS
eliminates hand drafting by using symbols to represent
complex multi-level circuit elements.
SIDS circuit masks are designed symbolically on an
interactive color CRT terminal. The mask design process
is supported by such checking aids as:
D Design Rule Checking (DRC) which checks for all
symbol-to-symbol layout violations;

o assignable rise and fall delay;
o race detection and inertial delay simulation;

D TRACE, which traces a circuit node and visually
highlights the node on the color CRT terminal so the
user can observe circuit continuity errors.

D versatile input, output, and simulation
control options;
D checkpoint-restart capability;
D accurate initialization algorithm;
D extensive compression and formating of simulation
results for automatic test equipment.

D CONTINUITY, which generates a net list from a
logic description file, compares it to a net list traced
from the symbolic layout, and prints out any continuity differences.
The final SIDS step is the conversion from symbols to
polygons (STP) and the generation of the pattern generation (PATGEN) tape.

Circuit simulation
At the circuit design phase, a circuit simulator containing semiconductor device models is used to identify
undesirable circuit behavior. Exact circuit behavior is
simulated and the results are used to insure the circuit
will operate within allowable tolerances.

Hardware design aids
o On-site Burroughs 7765 large scale computer with
multiprocessing capability.

The ASPEC circuit simulator can perform non-linear DC,
non-linear DC transfer function, non-linear transient and
small signal (linear) AC circuit analysis. Built-in component models include independent voltage and current
sources; linear elements such as resistance, inductance,
capacitance, transconductance, voltage controlled switches and coupled-inductors. Non-linear transistor models
for junction field effect transistors (JFETs), MOSFETs,
and bipolar junction transistors (BJT) are also available.

o Prime minicomputers in Santa Clara, Pocatello and

The MOSFET model simulates linear and saturation

D Calcomp 748 Flatbed Plotter.

1.6

Swindori, England.
D A Calma G DSII interactive graphics system for digitizing and editing of composite drawings; includes 3
digitizing surfaces and 4 CRT edit stations.
D High speed, high resolution Electromask
pattern generator.
D Versatec 42 inch high speed electrostatic plotter.

Custom Capabilities
Software design aids

Step Six: Testing for reliable performance

o
o

ASPEC Circuit Simulator

o

Tides Logic Simulator for:
Logic Validation
- Pattern Validation
- Test Word Generation

Currently more than 50% of the custom LSI circuits
designed by AMI work the first time. The key to this
impressive record is a comprehensive program of quality
assurance, rigorous testing and constant double checking
of each step.

o
o

Semiconductor device models tailored to
AMI processes

SIDS for mask design

It starts at the initial stages of logic design, with the
custom LSI chip designed to incorporate facilities for
ease of testing and ends with prototype debugging.

Geometrical Design Rule Checking (DRC) for
hand drawn circuits

Common test data base

o

Trace and continuity checking for
hand drawn circuits

o

Device test program development aids

To facilitate the processing of vast quantities of test
data, a base of parametric and functional information
with run, wafer or die resolution has been created by
AMI engineers.

Step Five: Fabricating the optimum device.
A partnership
AMI's long history of success in the custom MOS/LSI
business is the result of a close, working partnership
between AMI and each of our customers.
These customers have taken advantage of orders of magnitude increases in circuit complexity over the years,
thereby reducing even further the component count in
their systems.
The flexibility of AMI's development program allows the
customer to select the interface point best suited to his
particular needs. The most common interface points are
noted as (*) in the review of the sequence of steps involved in developing a custom MOS/LSI circuit below:
1. System Definition Design (*)

With this data analysis system, each user creates a personal data base secured by user code and information inputted from magnetic tape, cards or remote terminals.
Using an interactive command language for manipulation of data, subsets of test information can be retrieved
and listed through the use of key attributes-test group,
process, product number, test date, test time at start,
operator ID, save data, run or lot number. The retrieved
data base subset can be analyzed statistically as: histograms, scatter plots, wafer maps, trend charts, tabulations of percentiles, means, standard deviations and correlation coefficients.

Extensive test facilities
AMI maintains fourteen Fairchild Sentry II and 600
automated test systems, plus a wide range of other
testers for debugging of protypes, solving design and
testing problems and production testing.

2. Preliminary logic design and simulation(*)
3. Final logic design and system design review
4. Chip circuit design
5. Topological design
6. Artwork generation (*)
7. Mask fabrication (*)
8. Wafer fabrication and map test
9. Wafer sort test (*)
10. Final test and characterization

Quality assurance
An on-going activity that pervades the entire design and
manufacturing process is AMI's quality assurance program. This includes a special group of inspectors organizationally separate from the production group, whose
main responsibility is to examine and test the custom
LSI circuits and all the raw materials that go into them.
Some of the quality control checkpoints include:

o

11. Product assurance tests

1.7

final logic design where system objectives
are reviewed;

AMII~
o

Custom Capabilities

chip circuit design, where it is verified that
performance meets objectives;

D working plates check;

o

mask fabrication check;

o wafer fabrication check;

o

wafer sort;

D scribe and break with 100% optical inspection;

o
o
o

die attach checks;
lead bonding followed by 100% preseal
optical inspection;
seal checks;

D final tests; and,

o

final electrical/environmental tests.

At each one of these pre-production steps meticulous
checks of both design and workmanship are made. And
only after the checks at each of these steps are completed
is a device considered fully manufacturable. It is then
turned over to production with its yield history. In production a similar series of quality control checks is made.

Custom MOS/LSI from AMI
The information in this section has been presented to
show not only how and why custom can be used, but also
to explain the types of custom services available at AMI,
and the level of commitment at AMI to total custom circuit development and to customer tooling processing. If
your application can benefit from high· quality custom
MOS/LSI circuits, AMI is the place to go for design,
engineering, manufacturing, and testing capability. To
get in contact with AMI Custom, just complete the inquiry card at the back of this catalog.

1.8

Communication Products

•

Communication Products Selection Guide

STATION PRODUCTS
Part No.

Description

Process

Power Supplies

S2559A/B

Digital Tone Generator

CMOS

3.5V to 13V

16 Pin

S2559CID

Digital Tone Generator

CMOS

2.75V to 10V

16 Pin
16 Pin

Packages

S2859

Digital Tone Generator

CMOS

3.0V to 10.0V

S2860

Digital Tone Generator

CMOS

3.5V

16 Pin

S2861A/B

Digital Tone Generator

CMOS

2.5V to 10.0V

16 Pin

S2560A/B

Pulse Dialer

CMOS

1.5V to 3.5V

18 Pin

S2561, S2561C

Tone Ringer

CMOS

4.0V to 12.0V

18 Pin

S2561A

Tone Ringer

CMOS

4.0V to 12.0V

8 Pin

S2562

Repertory Dialer

CMOS

3.5V to 7.5V

40 Pin

Part No.

Description

Process

Power Supplies

Packages

S3501lS3501A

wLaw Encoder with Filter

CMOS

±5V

18 Pin

S3502/S3502A

J.I-Law Decoder with Filter

CMOS

±5V

16 Pin

S3503

A-Law Encoder with Filter

CMOS

±5V

18 Pin

S3504

A-Law Decoder with Filter

CMOS

±5V

16 Pin

S2811

Signal Processing Peripheral

VMOS

5V

28 Pin

S2814

Fast Fourier Transformer

VMOS

5V

28 Pin

S3525AIB

DTMF Bandsplit Filter

CMOS

10.0V to 13.5V

18 Pin

PCM PRODUCTS

OTHER PRODUCTS

2.2

S2559A1B/C/D

DIGITAL
TONE GENERATOR
Features

General Description

D

The S2559 Digital Tone Generator is specifically
designed to implement a dual tone telephone dialing
system. The device can interface directly to a standard
pushbutton telephone keyboard or calculator type X-Y
keyboard and operates directly from the telephone lines.
All necessary dual-tone frequencies are derived from the
widely used TV crystal standard providing very high
accuracy and stability. The required sinusoidal
waveform for the individual tones is digitally synthesized on the chip. The waveform so generated has very
low total harmonic distortion. A voltage reference is
generated on the chip which is stable over the operating
voltage and temperature range and regulates the signal
levels of the dual tones to meet the recommended
telephone industry specifications. These features permit
the 82559 to be incorporated with a slight modification
of the standard 500 type telephone basic circuitry to
form a pushbutton dual-tone telephone. Other applications of the device include radio and mobile telephones,
remote control, Point-of-8ale, and Credit Card Verification Terminals and process control.

D

D

D
D
D

o

D
D

Wide Operating Supply Voltage Range: 3.5 to
13.0 Volts (A, B) 2.75 to 10 Volts (C, D)
Low Power CMOS Circuitry Allows Device
Power to be Derived Directly from the Telephone Lines or from Small Batteries, e.g., 9V
Uses TV Crystal Standard (3.58 MHz) to Derive
all Frequencies thus Providing Very High
Accuracy and Stability
Mute Drivers On Chip
Interfaces Directly to a Standard Telephone
Push-Button or Calculator Type X-Y Keyboard
The Total Harmonic Distortion is Below
Industry Specification
On Chip Generation of a Reference Voltage to
Assure Amplitude Stability of the Dual Tones
Over the Operating Voltage and Temperature
Range
Dual Tone as Well as Single Tone Capability
Four Options Available:
A:3.5 to 13.0V Mode Select
B:3.5 to 13.0V Chip Disable
C: 2.75 to lOV Mode Select
D: 2.75 to 10V Chip Disable

Pin Configuration

Block Diagram

3.58MHI

i-~I;;w~;7vN~E;;;;-l

I
16fl

I

I

I

I

I
I
I

Vee

Rl

EN

R2
C3
Vss

R4

OSCI

I
16tH

OSCO

I
I

I

I

L ________ ..JI

2.3

C4

•

S2559A1B/C/D

Absolute Maximum Ratings
DC Supply Voltage (VDD- VSS) S2559 A, B ................................................................ + 13.5V
DC Supply Voltage (VDD- VSS) S2559 C, D ................................................................. + 1O.5V
Operating Temperature .......................................................................... -25°C to +70°C
Storage Temperature ........................................................................... -55°C to + 125°C
Power Dissipation at 25°C ................................................................................. 500rnW
Input Voltage .............................................................................. -0.6",VIN",VDD+0.6

S2559A & B Electrical Characteristics:

(Specifications apply over the operating temperature range of - 25°C to 70°C unless otherwise noted. Absolute
values of measured parameters are specified.)

Symbol

VDD

IDD

VOR
dBCR
%DIS

VOH
IOF
VOL
VOH
IOL
IOH

IOL
IOH

I(VDD- VSS) I
Volts

Parameter/Conditions
Supply Voltage
Tone Out Mode (Valid Key Depressed)
Non Tone Out Mode (No Key Depressed)
Supply Current
Standby (No Key Selected, Tone, XMIT
and MUTE Outputs Unloaded)
Operating (One Key Selected, Tone, XMIT
and MUTE Outputs Unloaded)
Tone Output
Single Tone
Row Tone, RL=390Q
Mode Output
Voltage
I Row Tone, RL=240Q
Ratio of Column to Row Tone

I
I

I
I

Min.
3.5
3.0

3.5
13.0
3.5
13.0

I

Distortion *
XMIT, MUTE Outputs
XMIT, Output Voltage, High (IOH=15rnA)
(No Key Depressed)(Pin 2)
(lOH=50rnA)
XMIT, Output Source Leakage Current,
VOF=OV
MUTE (Pin 10) Output Voltage, Low,
(No Key Depressed), No Load
MUTE, Output Voltage, High,
(One Key Depressed) No Load
MUTE, Output Sink
VOL=0.5V
Current
MUTE, Output Source
VOH=2.5V
Current
VOH=9.5V
Oscillator Input/Output
Output Sink Current
VOL=0.5V
One Key Selected
VOL=0.5V
Output Source Current
VOH=2.5V
One Key Selected
VOH=9.5V

I

Typ.

I
I

I

I
I

Max.
13.0
13.0

I

I

1

Units
V
V

0.4
1.5
0.95
11

40
130
2.9
33

IJA
IJA
rnA
rnA

789
725
3.75
10

rnVrrns
rnVrrns
dB
%

5.0
12.0
3.5-13.0
3.5-13.0

417
378
1.75

596
551
2.54

3.5
13.0

2.0
12.0

2.3
12.3

13.0
3.5
13.0
3.5
13.0
3.5
13.0
3.5
13.0

3.0
13.0
0.66
3.0
0.18
0.78

0
0
3.5
13.5
1.7
8.0
0,46
1.9

3.5
13.0
3.5
13.0

0.26
1.2
0.14
0.55

0.65
3.1
0.34
1.4

V
V
100

IJA

0.4
0.5

V
V
V
V
rnA
rnA
rnA
rnA
rnA
rnA
rnA
rnA

*Distortion measured in accordance with the specifications described in Ref. 1 as the "ratio of the total power of all extraneous frequencies in
the voiceband above 500Hz accompanying the signal to the total power of the frequency pair".
2.4

S2559A1B/C/D

S2559A & B Electrical Characteristics: (Continued)
Parameter/Conditions

IlL
IIH
IlL
tSTART
CliO

Units

Input Current
Leakage Sink Current,
One Key Selected
Leakage Source Current
One Key Selected
Sink Current
No Key Selected
Oscillator Startup Time

VIL=13.0V

13.0

1.0

Ili\

VIH=O.OV

13.0

1.0

/AA

VIL=0.5V
VIL=0.5V

3.5
13.0
3.5
13.0

24
27

3.5

7

17

/AA

13.0

150

400

/AA

3.5

90

230

/AA

13.0

370

960

/AA

3.5

1.5

3.6

/AA

13.0

23

74

/AA

3.5

4

10

/AA

13.0

90

240

Ili\

Input/Output Capacitance

93
130
3
0.8
12
10

Ili\
Ili\
rnS
rnS
pF
pF

6
1.6
16
14

Input Currents
IlL
Row &
Column Inputs
IIH

IIH

IlL

Mode Select
Input (S2559C)
Chip Disable
Input (S2559D)

Sink Current,
VIL=3.5V (Pull-down)
Sink Current
VIL= 13.0V (Pull-down)
Source Current,
VIH=3.0V (Pull-up)
Source Current,
VIH=12.5V (Pull-up)
Source Current,
VIH=O.OV (Pull-up)
Source Current
VIH=O.OV (Pull-up)
Source Current,
VIL=3.5V (Pull-down!
Sink Current.
VIL=13.0V (Pull-down)

S2559C & 0 Electrical Characteristics:

(Specifications apply over the operating temperature range of -25°C to 70°C unless otherwise noted. Absolute
values of measured parameters are specified.)
Symbol

VDD

IDD

VOR

Parameter/Conditions

Units

Supply Voltage
Tone Out Mode (Valid Key Depressed)
Non Tone Out Mode (No Key Depressed)
Supply Current
Standby (No Key Selected, Tone, XMIT
and MUTE Outputs Unloaded)
Operating (One Key Selected, Tone, XMIT
and MUTE Outputs Unloaded)
Tone Output
Single Tone
Mode Output
Row Tone, RL=390Q
Voltage
Row Tone, RL-240Q

V
V
3.0
10.0
3.0
10.0
3.5
5.0
10.0

2.5

250
367
328

0.3
1.0
1.0
8

30
100
2.0
16.0

362
546
501

474
739
675

/AA
/AA
rnA
rnA
rnVrrns

I rnVrms

I

rnVrms

I

S2559A1B/~/D

S2559C & 0 Electrical Characteristics: (Continued)
Symbol

Parameter/Conditions

dEeR

Ratio of Column to Row Tone
Distortion
XMIT, MUTE Outputs
XMIT, Output Voltage, High (lOH=15mA)
(No Key Depressed)(Pin 2)
(IOH=50rnA)
XMIT, Output Source Leakage Current,
VOF=OV
MUTE (Pin 10) Output Voltage, Low,
(No Key Depressed), No Load
MUTE, Output Voltage, High,
(One Key Depressed) No Load
MUTE, Output Sink
VOL=0.5V
Current
MUTE, Output Source
VOH=2.5V
Current
VOH=9.5V
Oscillator Input/Output
Output Sink Current
VOL=0.5V
One Key Selected
VOL=0.5V
Output Source Current
VOH=2.5V
One Key Selected
VOH=9.5V
Input Current
Leakage Sink Current,
VIL=10.0V
One Key Selected
Leakage Source Current
VIH=O.OV
One Key Selected
Sink Current
VIL=0.5V
No Key Selected
VIL=0.5V
Oscillator Startup Time

%DIS

VOH
IOF
VOL
VOH
IOL
IOH

IOL
IOH

IlL
IIH
IlL
tSTART

CliO

*

(Vnn-Vss)
Volts
3.0-10.0
3.0-10.0

Min.

Typ.

Max.

Units

1.75

2.54

3.75
10

dB
%

3.0
10.0

1.5
8.5

1.8
8.8

10.0

Input/Output Capacitance

2.75
10.0
2.75
10.0
3.0
10.0
3.0
10.0

2.5
9.5
0.53
2.0
0.17
0.57

0
0
2.75
10.0
1.3
5.3
0.41
1.5

3.0
10.0
3.0
10.0

0.21
0.80
0.13
0.42

0.52
2.1
0.31
1.1

V
V
100

,.u\

0.5
0.5

V
V
V
V
rnA
rnA
rnA
rnA

rnA
rnA
rnA
rnA

10.0

1.0

,.u\

10.0

1.0

,.u\

3.0
10.0
3.5
10.0
3.0
10.0

24
27

3.0

6.5

16

,.u\

10.0

9.2

24

,.u\

3.0

85

210

,.u\

10.0

280

740

,.u\

3.0

1.4

3.3

,.u\

10.0

18

46

,.u\

3.0

3.9

9.5

,.u\

10.0

55

143

,.u\

93
130
2
0.25
12
10

5
4
16
14

,.u\
,.u\
mS
mS
pF
pF

Input Currents
IlL

Row &
Column Inputs
IIH

IIH

IlL

Mode Select
Input (S2559C)
Chip Disable
Input (S2559D)

Sink Current,
VIL=3.0V (Pull-down)
Sink Current
VIL=10.0V (Pull-down)
Source Current,
VIH=2.5V (Pull-up)
Source Current,
VIH=9.5V (Pull-up)
Source Current,
VIH=O.OV (Pull-up)
Source Current
VIH=3.0V (Pull-up)
Source Current,
VIL = 3.0V (Pull-down)
Sink Current
VIL = 1O.0V (Pull-down)

*Distortion measured in accordance with the specifications described in Ref. 1 as the "ratio of the total power of all extraneous frequencies in the
voiceband above 500Hz accompanying the signal to the total power of the frequency pair".

2.6

JtMII.

S2559A1B/C/D
Table 2. XMIT and MUTE Output Functional Relationship

Table 1. Comparisons of Specified vs Actual Tone
Frequencies Generated by S2559

OUTPUT FREQUENCY Hz

ACTIVE
INPUT

SPECIFIED

ACTUAL

% ERROR
SEE NOTE

R1
R2
R3
R4
C1
C2
C3
C4

697
770
852
941
1,209
1,336
1,477
1,633

699.1
766.2
847.4
948.0
1,215.9
1,331.7
1,471.9
1,645.0

+0.30
-0.49
-0.54
+0.74
+0.57
-0.32
-0.35
+0.73

OUTPUT

'DIGIT' KEY
RELEASED

'DIGIT' KEY
DEPRESSED

XMIT

Voo

High Impedance

Can source at
least 50mA at
10V with 1.5V
max. drop

MUTE

Vss

VDO

Can source or
sink current

COMMENT

NOTE: % Error does not include oscillator drift.

Circuit Description
The 82559 is designed so that it can be interfaced easily
to the dual tone signaling telephone system and that it
will more than adequately meet the recommended
telephone industry specifications regarding the dual
tone signaling scheme.

Design Objectives
The specifications that are important to the design of the
Digital Tone Generator are summarized below: the dual
tone signal consists of linear addition of two voice frequency signals. One of the two signals is selected from a
group of frequencies called the "Low Group" and the
other is selected from a group of frequencies called the
"High Group". The low group consists of four frequencies 697, 770, 852 and 941 Hz. The high group consists of
four frequencies 1209, 1336, 1477 and 1633 Hz. A
keyboard arranged in a row, column format (4 rows x 3 or
4 columns) is used for number entry. When a push button
corresponding to a digit (0 thru 9) is pushed, one appropriate row (R1 thru R4) and one appropriate column (C1
thru C4) is selected. The active row input selects one of
the low group frequencies and the active column input
selects one of the high group frequencies. In standard
dual tone telephone systems, the highest high group frequency of 1633Hz (Col. 4) is not used. The frequency
tolerance must be ±1.0%. However, the 82559 provides
a better than .75 % accuracy. The total harmonic and
intermodulation distortion of the dual tone must be less
than 10% as seen at the telephone terminals. (Ref. 1.) The
high group to low group signal amplitude ratio should be
2.0 ± 2dB and the absolute amplitude of the low group
and high group tones must be within the allowed range.
(Ref. 1.) These requirements apply when the telephone is
used over a short loop or long loop and over the operating
temperature range. The design of the 82559 takes into
account these considerations.
2.7

Oscillator
The device contains an oscillator circuit with the
necessary parasitic capacitances on chip so that it is only
necessary to connect a lOMQ feedback resistor and the
standard 3.58MHz TV crystal across the OSCI and OSCO
terminals to implement the oscillator function. The
oscillator functions whenever a row input is activated. The
reference frequency is divided by 2 and then drives two
sets of programmable dividers, the high group and the low
group.
Keyboard Interface
The 82559 employs a calculator type scanning circuitry
to determine key closures. When no key is depressed, active pull-down resistors are "on" on the row inputs and
active pull-up resistors are "on" on the column inputs.
When a key is pushed a high level is seen on one of the
row inputs, the oscillator starts and the keyboard scan
logic turns on. The active pull-up or pull-down resistors
are selectively switched on and off as the keyboard scan
logic determines the row and the column inputs that are
selected. The advantage of the scanning technique is that
a keyboard arrangement of 8P8T switches are shown in
Figure 2 without the need for a common line, can be used.
Conventional telephone push button keyboards as
shown in Figure 1 or X-Y keyboards with common can
also be used. The common line of these keyboards can be
left unconnected or wired "high".
Logic Interface
The 82559 can also interface with CM08 logic outputs
directly. The 82559 requires active "High" logic levels.
8ince the active pull-up resistors present in the 82559 are
fairly low value (500Q typ), diodes can be used as shown
in Figure 3 to eliminate excessive sink current flowing into the logic outputs in their "Low" state.

AMite

S2559A1B/C/D

Tone Generation

When a valid key closure is detected, the keyboard logic
programs the high and low group dividers with appropriate divider ratios so that the output of these dividers
cycle at 16 times the desired high group and low group
frequencies. The outputs of the programmable dividers
drive two 8-stage Johnson counters. The symmetry of
the clock input to the two divide by 16 Johnson counters
allows 32 equal time segments to be generated within
each output cycle. The 32 segments are used to digitally

synthesize a stair-step waveform to approximate the
sinewave function (see Figure 3). This is done by connecting a weighted resistor ladder network between the outputs of the Johnson counter, V DD and VREF. VREF
closely tracks VDD over the operating voltage and
temperature range and therefore the peak-to-peak
amplitude Vp (VDD - VREF) of the stairstep function is
fairly constant. VREF is so chosen that Vp falls within the
allowed range of the high group and low group tones.

Figure 1. Standard Telephone Push Button Keyboard

,I
I
Al

-0-'- - -

0)--0--0
I

I

I

I

I

I

0--0)--0)---1
I

I

I

I

I

I

I

I
1

I

~A2

R3~,----0--0)--0)
I

I

0)--0)--0---1
I
I
e-o-

R4

'---_-'--I'1'---~--~'--.........- - _ COMMON
(CONNECT TO VOO 0 R
LEAVE FLOATING)
- - - MECHANICAL
LINKAGE

Ron (Contact Resistance)

1kl!

Figure 2. SPST Matrix Keyboard Arranged in the 2 of 8 Row, Column Format
RI

R2

R3

R4
SPST MATRIX KEYSORTEO:

/

)'o

CI

C2

C3

2.8

C4

(OPTIONAL COLUMN)

S2559A1B/C/D

Figure 3. logic Interface for Keyboard Inputs of the S2559

Voo
14
R1
13
12
11

Rz
R3
R4

S2559
C1
C2
C3
C4

Vss
6
Gl THRU G8 ANY TYPE CMOS GATE
01 THRU 08 DIODES TYPE IN914 (OPTIONAL)

Figure 4. Stairstep Waveform of the Digitally Synthesized Sinewave

(Vee)

1.0
0.9

0.8

>0~
N
::::;
-------,

R
1

-0--<0

,---8--8--8
I
I

I
I

I
I

0)--0--0)---,
I
I
I
~R1
~~'--

I

I

I

I

I

I

--CP--9--9

~IOTE:

%ERROR
SEE NOTE

OUTPUT FREQUENCY Hz
ACTUAL
SPECIFIED

ACTIVE
INPUT

R1

697

699.1

R2

770

766.2

- 0.49

R3

852

847.4

-0.54

+0.30

R4

941

948.0

+0.74

C1

1209

1215.9

+ 0.57

C2

1336

1331.7

-0.32

C3

1477

1471.9

- 0.35

C4

1633

1645.0

+0.73

%ERROR DOES NOT INCLUDE OSCILLATOR DRIFT

Figure 2. Logic Interface for Keyboard
Inputs of the S2859

()--~--()---,
I
I
~R4
'------"'-'1'------0c

w

!::::!

0.6

....I

0.
c
W

!:::!

0.6

..J

or:(

:2

a:

0.5

0

z
0.4
0.3
0.2
0.1
(V'el l

0
TIME SEGMENTS

Reference Voltage
The structure of the reference voltage employed in the
82860 is shown in Figure 4. It has the following
characteristics:

a) VREF is proportional to the supply voltage. Output
tone amplitude, which is a function of (VDD
- VREF), increases with supply voltage (Figure 5).

When no key is depressed the AKD outputs are open.
When a key is depressed the AKD outputs go to Vss.
The devices are large enough to sink a minimum of
lOOJ.(A with voltage drop of 0.2V at a supply voltage of
3.5V.

b) The temperature coefficient of VREF is low due to a
single VBE drop. Use of a resistive divider also provvides an accuracy of better than 1%. As a result, tone
amplitude variations over temperature and unit to
unit are held to less than ± 1.3dB over nominal.
c) Resistor values in the divider network are so chosen
that VREF is above the VBE drop of the tone output
transistor even at the low end of the supply voltage
range. The tone output clipping at low supply voltages is thus eliminated, which improves distortion
performance.
AKD (Any Key Down or Mute) Outputs

The AKD outputs (pin 15 and pin 10) are identical and consist of open drain N channel devices (see Figure 6.)
2.25

Vss

Figure 4. Structure of the Reference Voltage

AMlt.

S2860

Figure 5. Typical Tone Output Amplitude Vs Supply Voltage (RL = 10k)

800

700

t

600

i...

E
co

~
c
...z
co

500

:IE

I-

400

300

10

SUPPL Y VOLlAGE (VOL lS) ---..

Figure 6. AKD Output Structure

(Pin 15) AKD
~-----.....(")

(Pin 10) AKD

AKD

2.26

ADVANCED PRODUCT DESCRIPTION

S2861A1S2861 B

DIGITAL
TONE GENERATOR
Features
D Replaces S2559 Family with Reduced Tone
Output Distortion
D Wide Operating Supply Voltage Range: 2.5 to
10 Volts
o Low Power CMOS Circuitry Allows Device
Power to be Derived Directly from the Telephone Lines or from Small Batteries. e.g., 9V
o Uses TV Crystal Standard (3.58 MHz) to Derive
all Frequencies thus Providing Very High
Accuracy and Stability
o Oscillator Bias Resistor On Chip
o Interfaces Directly to a Standard Telephone
Pushbutton or Calculator Type X-V Keyboard
o The Total Harmonic Distortion is Below
Industry Specification
D On Chip Generation of a Reference Voltage to
Assure Amplitude Stability of the Dual Tones
Over the Operating Voltage and Temperature
Range
D Dual Tone as Well as Single Tone Capability
D Two Options Available on Pin 15:
S2861A: Mode Select (Replaces S2559A/C)
S2861B: Chip Disable (Replaces S2559BID)

General Description
The 82861A/B devices are improved versions of the
82559 family and are recommended for use in new
designs or as replacements for 82559 devices. Functionally the 82861A is identical to 82559A and 82559C.
The 82861B is functionally identical to 82559B and
82559D. An exception is the built in oscillator bias
resistor across the oscillator input/output pins of 82861
so that the external 10M n resistor is no longer
necessary.

Certain major differences in electrical performance
should be noted. Preemphasis, the ratio of the column
tone to the row tone, is changed to 2 dB ± 1 dB in the
82861 and the reference voltage circuit has been improved. These modifications substantially lower distortion in the tone output, especially at low operating
voltages, with only a small decrease in available tone
output level. Electrical specifications other than tone
amplitude and preemphasis are nearly identical to their
82559 counterparts, except for maximum operating
voltage, which is higher in the 82559A/B.

Pin Configuration

Block Diagram

I

IL ________ -.JI

2.27

•

82861 Al82861 B

S2861A & B Electrical Characteristics:

(Specifications apply over the operating temperature range of - 25°C to 70°C unless otherwise noted. Absolute
values of measured parameters are specified.)
Symbol

Vnn

Inn

VOR
dBCR
%DIS

VOH
10F
VOL
VOH
IOL
10H

10L
10H

IlL
IIH
IlL
tSTART

Parameter/Conditions

Units

Supply Voltage
Tone Out Mode (Valid Key Depressed)
Non Tone Out Mode (No Key Depressed)
Supply Current
Standby (No Key Selected, Tone, XMIT
and MUTE Outputs' Unloaded)
Operating (One Key Selected, Tone, XMIT
and MUTE Outputs Unloaded)
Tone Output
Single Tone
Mode Output
Row Tone, RL=390Q
Voltage
Row Tone, RL=240Q
Ratio of Column to Row Tone

v
v
3.0
10.0
3.0
10.0
3.5
5.0
10.0
3.5-13.0

*

Distortion
XMIT, MUTE Outputs
XMIT, Output Voltage, High (lOH=15mA)
(No Key Depressed)(Pin 2)
(lOH=50mA)
XMIT, Output Source Leakage Current,
VOF=OV
MUTE·Win 10) Output Voltage, Low,
(No Key Depressed), No Load
MUTE, Output Voltage, High,
(One Key Depressed) No Load
MUTE, Output Sink
VOL=0.5V
Current
MUTE,Output Source
VOH=2.5V
Current
VOH=9.5V
Oscillator Input/Output
Output Sink Current
VOL=0.5V
One Key Selected
VOL=0.5V
Output Source Current
VOH=2.5V
One Key Selected
VOH=9.5V
Input Current
Leakage Sink Current,
VIL=10.0V
One Key Selected
Leakage Source Current
One Key Selected
Sink Current
No Key Selected
Oscillator Startup Time

0.3
1.0
1.0
8

1.0

30
100
2.0
16.0

2.0

3.5-13.0
3.0
10.0

1.5
8.5

/AA
/AA
rnA
rnA

3.0

mVrms
mVrms
mVrms
dB

10

%

1.8
8.8

V
V

10.0
2.75
10.0
2.75
10.0
3.0
10.0
3.0
10.0

2.5
9.5
0.53
2.0
0.17
0.57

0
0
2.75
10.0
1.3
5.3
0.41
1.5

3.0
10.0
3.0
10.0

0.21
0.80
0.13
0.42

0.52
2.1
0.31
1.1

100

~

0.5
0.5

V
V
V
V

rnA
rnA
rnA
rnA

I

I

rnA
rnA
rnA
rnA

10.0

1.0

~

VIH=O.OV

10.0

1.0

~

VIL=0.5V
VIL=0.5V

3.0
10.0
3.5
10.0

24
27

93
130
2
0.25

~
~

5
4

mS
mS

• Distortion measured in accordance with the specifications described in Ref. 1 as the "ratio of the total power of all extraneous frequencies in the
voiceband above 500Hz accompanying the signal to the total power of the frequency pair".

2.28

AMlt.

S2861A1S2861B

S2861A & B Electrical Characteristics: (Continued)
Symbol

Parameter/Conditions

CliO

Input/Output Capacitance

(VDiJ-VSS)
Volts
3.0
10.0

Min.

3.0

6.5

16

~

10.0

9.2

24

~

3.0

85

210

~

10.0

280

740

~

3.0

1.4

3.3

~

10.0

18

46

~

3.0

3.9

9.5

~

10.0

55

143

~

Typ.

Max.

Units

12
10

16
14

pF
pF

Input Currents
IlL
Row &
Column Inputs

IIH

IIH

IlL

Mode Select
Input S2861A

Chip Disable
Input S2861B

Sink Current,
VIL=3.0V (Pull-down)
Sink Current
VIL=1O.0V (Pull-down)
Source Current,
VIH = 2.5V (Pull-up)
Source Current,
VIH=9.5V (Pull-up)
Source Current,
VIH=O.OV (Pull-up)
Source Current
VIH = 3.0V (Pull-up)
Source Current,
VIL=3.0V (Pull-down)
Sink Current
VIL=1O.0V (Pull-down)

2.29

•

S2560A
PULSE DIALER
o
o

Features

o

Low Voltage CMOS Process for Direct Operation From Telephone Lines

o

Inexpensive R-C Oscillator Design Provides
Better than ±5% Accuracy Over Temperature
and Unit to Unit Variations

o

Dialing Rate Can Be Varied By Changing the
Dial Rate Oscillator Frequency

o

Dial Rate Select Input Allows Changing of the
Dialing Rate by a 2:1 Factor Without Changing
Oscillator Components

o

Two Selections of Mark/Space Ratios
(33-1/3/66-2/3 or 40/60)

o

Twenty Digit Memory for Input Buffering and
for Redial With Access Pause Capability

Mute and Dial Pulse Drivers on Chip
Accepts DPCT Keypad with Common
Arranged in a 2 of 7 Format; Also Capable of
Interface to SPST Switch Matrix

General Description

The S2560A Pulse Dialer is a CMOS integrated circuit
that converts pushbutton inputs to a series of pulses
suitable for telephone dialing. It is int~nded as a replacement for the mechanical telephone dial and can operate
directly from the telephone lines with minimum interface. Storage is provided for 20 digits, therefore, the last
dialed number is available for redial until a new number
is entered. IDP is scaled to the dialing rate such as to
produce smaller IDP at higher dialing rates. Additionally, the IDP can be changed by a 2:1 factor at a given
dialing rate by means of the IDP select input.

Block Diagram

Pin Configuration

KEYBOARD
INPUTS

R4

18

R1

17

RZ

16

R3
DIAL
RATE
OSC

4

I RO

iiS

S2560A 15
5 PULSE 14

Co
RE

RE

6

I

Ol'
MUTE

DRS

IPS

MIS

2.30

DIALER 13

C3
Cz
C1
IPS
DRS

Voo

Co

1Z

MIS

RO

11

MUTE

liP

10

Vss

S2560A
Absolute Maximum Ratings:
Supply Voltage ....................................................................................................... +5.5V
Operating Temperature Range ...................................... , . . . .. . . .. . .. . . . . . .. . . . . . . . . .... . .. . . .... -25°C to +70°C
Storage Temperature Range ................................................................................ -40°C to + 125°C
Voltage at any Pin ................................................................................... VSS -0.3V to VDD +0.3V
Lead Temperature (Soldering, lOsec) .................................................................................... 300°C

Electrical Characteristics:
Specifications apply over the operating temperature and
Symbol

Parameter

1.5V~VDD

to Vss ~3.5V unless otherwise specified.

Vnn-Vss
(Volts)

Min.

3.5

125

Il A

VOUT

1.5
3.5

20
125

VO UT
VO UT

3.5

125

Il A
Il A
Il A

1.5
3.5

20
125

Il A
Il A

VOUT
VOUT

= IV
= 2.5V

1.5

20

Il A

VOUT

= O.4V

1.5

20

= IV

Max.

Units

Conditions

Output Current Levels
IOLDP
IOHDP
IOLM
IOHM

DP Output Low
Current (Sink)
DP Output High
Current (Source)
MUTE Output Low
Current (Sink)
MUTE Output High
Current (Source)

IDD

Tone Output Low
Current (Sink)
Tone Output High
Current (Source)
Quiescent Current

IIL,IIH

Input Current Average
(Keyboard Inputs)

IOLT
IOHT

1.5

750

Il A

VOUT

nA

"On Hook" HS

One row end one col. input connected to
VDD' Other keyboard inputs open.

= VDD

3.5

60

IlA

3.5

100

nA

VIN = VSS or VDD

1.5
3.5

100
500

IlA
Il A

DP, MUTE open, HS = VSS ("Off Hook")
Keyboard processing and dial pulsing at 10
pps at conditions as above

IDD

Input Current Any
Other Pin
Operating Current

fo

Oscillator Frequency

1.5

10

kHz

Molfo

Frequency Deviation

1.5 to 2.5

-3

+3

%

2.5 to 3.5

-3

+3

%

IIL,IIH

= O.4V
= IV
= 2.5V
VOUT = O.4V

Fixed R-C oscillator components
50kQ":RO": 750kQ; 100pF": Co * ..: 1000pF;
750kQ ":RE ":5MQ
*300pF most desirable value for CD

Input Voltage Levels
VIH

Logical "1"

0.8
(Vnn-Vss)

VDO
+0.3

V

VIL

Logical "0"

VSS
-0.3

0.2
(Vnn-Vss)

V

CIN

Input Capacitance Any. Pin

7.5

pF

The device power supply should always be turned on before the input signal sources, and the input signals should be turned off before the
power supply is turned off (Vss ~ VI ~ VDD as a maximum limit). This rule will prevent over-dissipation and possible damage of the inputprotection diode when the device power supply is grounded. When power is first applied to the device, the device should be in "On Hook"
condition (HS=l). This is necessary because there is no internal power or reset on chip and for proper operation all internal latches must
come up in a known state. In applications where the device is hard wired in "Off Hook " (HS) =0) condition, a momentary "On Hook" condition can be presented to the device during power up by use of a capacitor resistor network as shown in Figure 6.

2.31

I

AMII~

S2560A

Functional Description

The pin function designations are outlined in Table 1.
Oscillator
The device contains an oscillator circuit that requires
three external components: two res~stors (RD and RE)
and one capacitor (CD). All internal timing is derived
from this master time base.·· To eliminate clock interference in the talk state, the oscillator is only enabled
during key closures and during the dialing state. It is
disabled at all other times including the "on hook"
condition. For a dialing rate of 10 pps the oscillator
should be adjusted to 2400 Hz. Typical values of external components for this are RD and RE=750k{} and
CD=270 pF. It is recommended that the tolerance of
resistors to be 5% and capacitor to be 1 % to insure a
±10% tolerance of the dialing rate in the system.
Keyboard Interface (2560A)
The S2560A employs a scanning technique to determine
a key closure. This permits interface to a DPCT
keyboard with common connected to VDD (Figure 1),
logic interface (Figure 2) and interface to a SPST switch
matrix (Figure 7). A high level on the appropriate row
and column inputs constitutes a key closure for logic interface. When using a SPST switch matrix, it is
necessary to add small capacitors (30 pF) from the column inputs to VSS to insure that the oscillator is shut
off after a key is released or after the dialing is complete.

OFF Hook Operation: The device is continuously
powered through a 150k {} resistor during Off hook
operation. The DP output is normally high and sources
base drive to transistor Ql to turn ON transistor Q2'
Transistor Q2 replaces the mechanical dial contact
used in the rotary dial phones. Dial pUlsing begins
when the user enters a number through the keyboard.
The DP output goes low shutting the base drive to Ql
OFF causing Q2 to open during the pulse break. The
MUTE output also goes low during dial pulsing allowing muting of the receiver through transistors Q3 and
Q4' The relationship of dial pulse and mute outputs are
shown in Figure 3.
ON Hook Operation: The device is continuously powered through a 1O-20M Q resistor during the ON hook
operation. This resistor allows enough current from the
tip and ring lines to the device to allow the internal
memory to hold and thereby providing storage of the
last number dialed.
The dialing rate is derived by dividing down the dial
rate oscillator frequency. Table 2 shows the relation2.32

ship of the dialing rate with the oscillator frequency
and the dial rate select input. Different dialing rates
can be derived by simply changing the external resistor value. The dial rate select input allows changing of
the dialing rate by a factor of 2 without the necessity
of changing the external component values. Thus,
with the oscillator adjusted to 2400Hz, dialing rates
of 10 or 20 pps can be achieved. Dialing rates of 7
and 14 pps similarly can be achieved by changing the
oscillator frequency to 1680Hz.
The Inter-Digit Pause (IDP) time is also derived from
the oscillator frequency and can be changed by a
factor of 2 by the IDP select input. With IDP select
pin wired to VSS, an IDP of 800ms is obtained for
dial rates of 10 and 20 pps. IDP can be reduced to
400ms by wiring the IDP select pin to VDD. At dialing
rates of 7 and 14 pps, IDP's of 1143ms and 572ms
can be similarly obtained. If the IDP select pin is connected to the dial rate select pin, the IDP is scaled to the
dial rate such that at 10 pps an IDP of 800ms is obtained and at 20 pps an IDP of 400ms is obtained.
The user can enter a number up to 20 digits long from a
standard 3x4 double contact keypad with common
(Figure 1). It is also possible to use a logic interface as
shown in Figure 2 for number entry. Antibounce protection circuitry is provided on chip (min. 20ms.) to prevent
false entry.
Any key depressions during the' on-hook condition are
ignored and the oscillator is inhibited. This insures that
the current drain in the on-hook condition is very low
and used to retain the memory.
Normal Dialing

The user enters the desired numbers through the keyboard after going off hook. Dial pulsing starts as soon
as the first digit is entered. The entered digits are
stored sequentially in the internal memory. Since the
device is designed in a FIFO arrangement, digits can
be entered at a rate considerably faster than the output rate. Digits can be entered approximately once
every 50ms while the dialing rate may vary from 7 to
20 pps. The number entered is retained in the memory
for future redial. Pauses may be entered when required
in the dial sequence by pressing the "#" key, which
provides access pauses for future redial. Any number
of access pauses may be entered as long as the total
entries do not exceed twenty.

S2560A

Auto Dialing

The last number dialed is retained in the memory and
therefore can be redialed out by going off hook and
pressing the "#" key. Dial pulsing will start when
the key is depressed and finish after the entire number is dialed out unless an access pause is detected.
In such a case, the dial pUlsing will stop and will
resume again only after the user pushes the "#" key.

Table 1. S2560A Pin/Function Descriptions

Pin
Keyboard
(RIo R 2 , R 3 , R 4 , C I , C2 , C3 )

Number

Function

7

These are 4 row and 3 column inputs from the keyboard
contacts. These inputs are open when the keyboard is inactive. When a key is pushed, an appropriate row and column
input must go to VDD or connect with each other. A logic
interface is also possible as shown in Figure 3. Active pull
up and pull down networks are present on these inputs
when the device begins keyboard scan. The keyboard scan
begins when a key is pressed and starts the oscillator. Debouncing is provided to avoid false entry (typ. 20ms).

Inter-Digit Pause Select (IPS)

Dial Rate Select (DRS)

One programmable line is available that allows selection of
the pause duration that exists between dialed digits. It is
programmed according to the truth table shown in Table
3. Note that preceding the first dialed pulse is an interdigit time equal to the selected IDP. Two pauses either
400ms or 800ms are available for dialing rates of 10 and 20
pps. IDP's corresponding to other dialing rates can be
determined from Tables 2 and 3.
1

Mark/Space (MS)
Mute Out (MUTE)

A programmable line allows selection of two different output rates such as 7 or 14 pps, 10 or 20 pps, etc. See Tables 2
and 3.
This input allows selection of the mark/space ratio, as per
Table 3.

1

A pulse is available that can provide a drive to turn on an
external transistor to mute the receiver during the dial
pulsing.

2.33

S2560A

Table 1. (Continued)

Number

Function

Dial Pulse Out (DP)

1

Dial Rate Oscillator

3

Hook Switch (HS)

1

Power (VDD, Vss)

2

Output drive is provided to turn on a transistor at the
dial pulse rate. The normal output will be "low" during
"space" and "high" otherwise.
These pins are provided to connect external resistors
RD, RE and capacitor CD to form an R -C oscillator
that generates the time base for the Key Pulser. The
output dialing rate and IDP are derived from this time
base.
This input detects the state of the hook switch contact;
"off hook" corresponds to VSS condition.
These are the power supply inputs. The device is designed to operate from 1.5V to 3.5V.

Pin

18

2.34

S2560A

Figure 1. Standard Telephone Pushbutton Keyboard

fl

(io-__- - -,
,
--8--0--0
", --o--e
I

1

I

1

I

1

I

I

1

1

I

1

I

I

1

I

I

I

( (0--8--8---,
~.-o-"3

"1

r---c)--8--8

--o--e~

9-- 0 --Q--~~ ",
'--------"'-'!'-_--.o-_-'-'-1'---+.---

1_(3

:.1

)' C,

COMMON

(CONNECT TO VOO

)'

I

___ MECHANICAL
LINKAGE

RON (CONTACT RESISTANCEI <; lkn

Figure 2. Logic Interface For the S2560

----fG\1---+------l
1)

KEYBOARO
INPUTS

S2560

G 1 through G7 any CMOS type logic gates
877292

Figure 3. Timing

DIAL PULSES

LOOPCURRENT----:u-LJ~
I

I

DP
lOP

IMARK

i I

SPACE

I
I

I

I

I
lOP

I

!
I

1

I

rr--lL...-____

---i
877293

2.35

S2560A

Table 2. Table for Selecting Oscillator Component Values for Desired Dialing Rates and Inter-Digit Pauses
Dial Rate
Desired

Osc. Freq.

RD

(Hz)

(kQ)

5.5/11
6/12
6.5/13
7/14
7.5/15
8/16
8.5/17
9/18
9.5/19
10/20

1320
1440
1560
1680
1800
1920
2040
2160
2280
2400

(fd/24O)/
(fd/ 12O)

fd

RE

I

(kQ)

I

CD
(pF)

Select components in the
ranges indicated in table
of electrical specifications

750

1

I

750

270

Dial Rate (pps)
DRS=Vss
DRS = VDD
5.5
11

6
6.5
7
7.5
8
8.5
9
9.5
10

12
13
14
15
16
17
18
19
20

(fd/ 24O)

(fd/ 12O)

IDP (ms)
IPS=Vss

IPS=VDD

1454
1334
1230
1142
1066
1000
942
888
842
800

727
667
615
571
533
500
471
444
421
400

(~~20 X103)

(9~0 X10 3)

Notes:
1. IDP is dependent on the dialing rate selected. For example, for a dialing rate of 10 pps, an IDP of either 800ms or 400ms can be selected. For
a dialing rate of 14 pps, and IDP of either 1142ms or 571ms can be selected.

Table 3.

Function
Dial Pulse Rate Selection
Inter-Digit Pause Selection

Pin Designation

Input Logic Level

DRS

Vss
VnD

IPS

VDD
Vss

Mark/Space Ratio

M/S

Vss
Vnn

On Hook/Off Hook

HS

VDD
Vss

Note: f is the oscillator frequency and is determined as shown in Figure 5.

2.36

Selection
(f/240) pps
(f/120) pps
960 s
f
1920 s
f
33-1/3/66-2/3
40/60
On Hook
Off Hook

S2560A

•

Figure 4. Pulse Dialer Circuit with Redial

RO=10-20MIl, R1=150kll, R2=2kll
R3=470kll, R4, RS=10kll, R10=47kll
RS, Ra= 2kll, R7, R9= 3Okll, R11 = 2011, 2W
Z1 = 3.9V, 01- 04= IN4004, Os' 06= IN914, C1 =15"F
RE= RO=750kll, CO=270pF, C2=0.01" F
01, 04 = 2N5550 TYPE 02, 03 = 2NS401 TYPE
Z2= 1 NS379 110V ZENER OR 2X1N47Sa

NOTE. PARTS REQUIRE COMMON OF THE KEYBOARD CONNECTEDTOV OO

Figure 5. Pulse Dialer Circuit with Redial (Single Hook Switch Contact Application for PABX)

R1 = 10-20MIl, R2 = 2kll
R3=470kll, R4, RS=10kll
Rs, Ra=2kll, R7, R9=30kll
R10=47kll, R11 =2011, 2W
Z1 = 3.9V, 01 - 04 = IN4004
Os, 0s= 1N914, C1 = 1S" F
RE, RO = 750kll, Co = 270pF
C2 0.01"F, 01, 04 2NSSSO
02, 03 2NS401
Z2 150V ZENER OR VARISTOR TYPE GE MOV150

=
=
=

NOTE. PARTSREOUIRE COMMON OF THE KEYBOARD CONNECTED TOV OO

=

2.37

AMII~

S2560A

Figure 6. Circuit for Applying Momentary "On Hook" Condition During Power Up

13

""'~

VDD

S2560AiB

5

HS

lOOk!!

10
VSS

Figure 7. SPST Switch Matrix Interface

C1
C2
C3

I

S2560A

2

0,\

3-

R1

4

5

6

R2

7

8

9

R3

*

0

#

R4
30pFFT

T1

2.38

VSS

1

Q

52561/52561 A/52561 C

TONE RINGER
Features

o
o

o
o
o

o

o

CMOS Process for Low Power Operation
Operates Directly from Telephone Lines
with Simple Interface
Also Capable of Logic Interface for
Non-Telephone Applications
Provides a Tone Signal that Shifts Between
Two Predetermined Frequencies at
Approximately 16Hz to Closely Simulate
the Effects of the Telephone Bell
Push-Pull Output Stage Allows Direct Drive,
Eliminating Capacitive Coupling and
Provides Increased Power Output
25mW Output Drive Capability at IOV
Operating Voltage

Auto Mode Allows Amplitude Sequencing
such that the Tone Amplitude Increases in
Each of the First Three Rings and Thereafter
Continues at the Maximum Level
Single Frequency Tone Capability

o

General Description

The S2561 Tone Ringer is a CMOS integrated circuit
that is intended as a repJacement for the mechanical
telephone bell. It can be powered directly from the
telephone lines with minimum interface and can
drive a speaker to produce sound effects closely
simulating the telephone bell.

Data subject to change at any time without notice. These sheets transmitted for information only.

Block Diagram

Pin Configuration

AUTO

SFS

VOO

OSCR,

THC

MANUAL
OSCRm

DUll

DEl

INH

01

OSCRO

OUT H

OSCT,

OUTm

OSCTm

OUT I

OSCT,

OUT,

DUrM

m

OUTPUT
STAGE

aSCTi

DUTH

AIM

ENIRATE

Vss

EN

OSCTm
OSCTo

DUTe

OSCR 1

OSCRm
OSCRo

OSCR j

5120Hz
(NOMl

OSCRm

OUT h

OSCRO

OUT,

RATE*'

VOLTAGE
SENSING
CIRCUIT

PoR

!-*-1

VOO

*OPTIONAlDunUTFORS2561&

2.39

VSS

VSS

Voo

EN

I

82561/82561 A/82561 C

Absolute Maximum Ratings
Supply Voltage ..................................................................................................... + 12.0V*
Operating Temperature Range. . . .. . .... .. . . . . .. . . . . . . . . . ... . . . . . . ... . .. . . . . . . .. . . . . . . .. ... . . . . . . . . . . . . .. . . .. -25°C to +70°C
Storage Temperature Range ................................................................................ -40°C to + 125°C
Voltage at any Pin ................................................................................... VSS -0.3V to VDD +0.3V
Lead Temperature (Soldering. 10sec) .................................................................................... 300°C
*This device incorporates a 12V internal zener diode across the VDD to VSS pins. Do NOT connect a low impedance power supply directly
across the device unless the supply voltage can be maintained below 12V or current limited to <25mA.

Electrical Characteristics
Specifications apply over the operating temperature and 3.5V ~ VDD to Vss <12.0V unless otherwise specified.

VDS

Symbol

Parameter
Operating Voltage (VDD to VSS)

VDS

Operating Voltage

lOS

Operating Current

IOHC

Output Drive
Output Source Current
(OUTH. OUTC outputs)

IOLC

Output Sink Current
(OUTH. OUTC outputs)

IOHM

Output Source Current (OutM output)

2

rnA

VDO=lOV. VOUT=8.75V

IOLM

Output Sink Current (OUTM output)

2

rnA

VOD=10V. VO UT =0.75V

IOHL

Output Source Current (OUTL output)

1

rnA

lOLL

1

rnA

VOO=10V. VO UT =8.75V
VOO=10V. VO UT =0.75V

V IH

Output Sink Current (OUT L output)
CMOS to CMOS
Input Logic "1" Level

0.7 VOO VDO+0.3

V

All inputs

VIL

Input Logic "0" Level

VSS-0.3

V

All inputs

VOHR

Output Logic "1" Level (Rate output) 0.9 VOO

V

IO=10",A (Source)

VOLR

Output Logic "0" Level (Rate output)

VOz

Output Leakage Current
(OUTH. OUTM outputs in high
impedance state)

CIN

Input Capacitance

Afo/fo

Oscillator Frequency Deviation

Min.
8.0

Max.
12.0

Units
V
V

"Auto" mode. non-ringing

500

",A

Non-ringing. VDD=10V. THC pin open.
DI pin open or VSS

5

rnA

VDO=lOV. VOUT=8.75V

5

rnA

VDD=lOV. VOUT=0.75V

4.0

-5

0.3 VOO

Conditions
Ringing. THC pin open

0.5

V

1
1

",A
",A

IO=10",A (Sink)

7.5

pF

Any pin

+5

%

Fixed RC component values IMQ

VOO=10V. VOUT=OV
VOO=10V. VO UT =10V

~

Rri.

Rti~5MQ;

100kQ~Rrm. Rtm~750kQ; 150pF~Cro.
Cto~ 3000pF;

330pF recommended value of Cro
and Cto. supply voltage varied from 9V ± 2V
(over temperature and unit-unit variations)
RLOAO

Output Load Impedance Connected
Across OUT H and OUTc

Q

600

IIH.IL

Leakage Current. V IN = VOD or VSS

100

nA

VTH

POE Threshold Voltage

6.5

8

V

Vz

Internal Zener Voltage

11

13

V

Tone Frequency Range = 300Hz to 3400Hz
Any input. except DI pin VOO=lOV
IZ=5mA

The device power supply should always be turned on before the input signal sources, and the input signals should be turned off before the power supply is turned
off (Vss";; VI";; VDD as a maximum limit). This rule will prevent over·dissipation and possible damage of the input-protection 'diode when the device power supply
is grounded

2.40

AMII~

S2561/S2561/A/S2561 C

Functional Description

The S2561 is a CMOS device capable of simulating the
effects of the telephone bell. This is achieved by producing a tone that shifts between two predetermined frequencies (512 and 640 Hz) with a frequency ratio of 5:4
at a 16 Hz rate.
Tone Generation: The output tone is derived from a
tone oscillator that uses a 3 pin R-C oscillator design
consisting of one capacitor and two resistors. The
oscillator frequency is divided alternately by 4 or 5 at
the shift rate. Thus, with the oscillator adjusted for
5120Hz, a tone signal is produced that alternates between 512Hz and 640Hz at the shift rate. The shift
rate is derived from another 3 pin R-C oscillator
which is adjusted for a nominal frequency of 5120Hz.
It is divided down to 16Hz which is used to produce
the shift in the tone frequency. It should be noted
that in the special case where both oscillators are adjusted for 5120Hz, it is only necessary to have one
external R -C network for one oscillator with the other
oscillator driven from it. The oscillators are designed
such that for fixed R-C component values an accuracy
of ±5% can be obtained over the operating supply voltage, temperature and unit-unit variations. See Table 1
for component and frequency selections. In the single
frequency mode, activated by connecting the SFS
input to V SS only the higher frequency continuous
tone is produced by using a fixed divider ratio of 4
and by disabling the shift operation.
Ring Signal Detection: In the following description it is
assumed that both the tone and rate oscillators are adjusted for a frequency of 5120 Hz. Ringing signal
(nominally 42 to 105 VAC, 20 Hz, 2 sec on/4 sec off duty
cycle) applied by the central office between the
telephone line pair is capacitively coupled to the tone
ringer circuitry as shown in Figure 2. Power for the
device is derived from the ringing signal itself by rectification (diodes D1 thru D4) and zener diode clamping
(Z2). The signal is also applied to the EN input after
limiting and clamping by a resistor (R2) and internal
diodes to VDD and VSS supplies. Internally the signal
is first squared up and then processed thru a 2ms filter
followed by a dial pulse reject filter. The 2ms filter is a
two stage shift register clocked by a 512 Hz signal
derived from the rate oscillator by a divide by 10 circuit.
The squared ring signal (typically a square wave) is applied to the D input of the first stage and also to reset
inputs of both stages. This provides for rejection of
spurious noise spikes. Signals exceeding a duration of
2ms only can pass through the filter. The dial pulse reject filter is clocked at 8 Hz derived from the rate oscillator by a divide by 640 circuit. This circuit is designed

to pass any signal that has at least two transitions in a
given 125ms time period. This insures that signals
below 8 Hz will be rejected with certainty. Signals over
16 Hz will be passed with certainty and between 8 Hz
and 16 Hz there is a region of uncertainty. By adjusting
the rate oscillator to a different frequency the break
points in frequencies can be varied. For instance for
break points of 10 Hz and 20 Hz the rate oscillator can
be adjusted to 6400 Hz. Of course this also increases the
tone shift rate to 20 Hz. The action of the dial pulse reject filter minimizes the dial pulse interference during
dialing although it does not completely eliminate it due
to the rather large region of uncertainty associated with
this type of discrimination circuitry. The dial pulse filter
also has the characteristic that an input signal is not
detected unless its duration exceeds 125ms. This insures that the tone ringer will not respond to momentary bursts of ringing less than 125 milliseconds in
duration (Ref 1).
In logic interface applications, the 2ms filter and the
dial pulse reject filter can be inhibited by wiring the
Det. INHIBIT pin to VDD. This allows the tone ringer
to be enabled by a logic '1' level applied at the
"EN ABLE" input without the necessity of a 20Hz
ring signal.
Voltage Sensing: The S2561 contains a voltage sensing
circuit that enables the output stage and the rate and
tone oscillators, only when the supply voltage exceeds a predetermined value. Typical value of this
threshold is 7.3 volts. This produces two benefits.
First, it insures that the audible intensity of the output tone is fairly constant throughout the ringing
period; and secondly, it insures proper circuit operation during the "auto" mode operation by reducing
the power consumption to a minimum when the
supply voltage drops below 7.3 volts. This extends
the supply voltage decay time beyond 4 seconds (off
period of the ring signal) with an adequate filter capacitor and insures the proper functioning of the
"amplitude sequencing" counter. It is important to
note that the operating supply voltage should be well
above the threshold value during the ringing period
and that the filter capacitor should be large enough so
that the ripple on the supply voltage does not fall
below the threshold value. A supply voltage of 10 to
12 volts is recommended.
In applications where the tone ringer is continuously
powered and below the threshold level, the internal
threshold can be bypassed by connecting the THC pin
to VDD' The internal threshold can also be reduced

2.41

I

82561/82561 A/82561 C

Functional Description (Continued)

by connecting an external zener diode between the
THC and V DD pins.
Auto Mode: In the "auto" mode, activated by wiring
the "auto/manual" input to VSS' an amplitude sequencing of the output tone can be achiev~d. Resistors
RL and RM are inserted in series with the OutL and
OutM outputs, respectively, and paralleled with the
OutH output (Figure 1). Load is connected across
OutH and Outc pins. RL is chosen to be higher than
RM. In this manner the first ring is of the lowest amplitude, second ring is of medium amplitude and the
third and consecutive rings thereafter are at maximum
amplitude. For the proper functioning of the "amplitude sequencing" counter the device must have at
least 4.0 volts across it throughout the ring sequence.
The filter capacitor is so chosen that the supply voltake will not drop below 4.0 volts during the off period. At the end of a ring sequence when the off period
substantially exceeds the 4 second duration, the counter will be reset. This will insure that the amplitude
sequencing will start correctly beginning a new ring
sequence. The counter is held in reset during the
"manual" mode operation. This produces a maximum
ring amplitude at all times.

consisting of buffers L, M, Hand C. The load is connected across pins OutH and Outc (Figure 2). During
ringing, the OutH and Outc outputs are out of phase
with each other and pulse at the tone rate. During a
non-ringing state, all outputs are forced to a known
level such as ground which insures that there is no DC
component in the load. Thus, direct coupling can be
used for driving the load. The major benefit. of the
push-pull arrangement is increased power output.
Four times as much power can be delivered to the
load for the same operating voltage. Buffers M and H
are three-state. In the "auto" mode buffer M is active
only during the second ring and in the "high impedance" state at all other times. Buffer H is active
beginning the third ring. In the "manual" mode buffers H, Land C are active at all times while buffer M
is in a high impedance state. The output buffers are
so designed that they can source or sink 5mA at a
VDD of 10 volts without appreciable voltage drop.
Care has been taken to make them symmetrical in
both source and sink configurations. Diode clamping
is provided on all outputs to limit the voltage spikes
associated with transformer drive in both directions
VDD and VSS'

Output Stage: The output stage is of push-pull type Normal protection circuits are present on all inputs.
Table 1. 52561/52561 C Pin/Function Descriptions

Pin

Number

Function

Power (VDD*, Vss*)

2

Ring Enable (EN*, EN)

2

These are the power supply pins. The device is designed to
operate over the range of 3.5 to 12.0 volts. A range of 10 to
12 volts is recommended for the telephone application.
These pins are for the 20Hz ring enable input. They can
also be used for DC level enabling by wiring the DI pin to
VDD. EN is available for the S2561 only.

Auto/Manual (AIM)

1

"Auto" mode for amplitude sequencing is implemented by
wiring this pin to Vss. "Manual" mode results when
connected to VDD . The amplitude sequencing counter is
held in reset during the "manual" mode.

4

These are the push-pull outputs. Load is directly connected across OutH and Outc outputs. In the "auto" mode,
resistors RL and RM can be inserted in series with the Ouk
and OutM outputs for amplitude sequencing (see Figure 1).

3

These pins are provided to connect external resistors RRi,
RRm and capacitor CRo to form an R-C oscillator with a
nominal frequency of 5120Hz. See Table 2 for components
selection.

Oscilla tors
Rate Oscillator
* OSCRo)*
(OSCRi*, OSCRm

2.42

AMlt.

82561/82561 A/82561 C

Table 1 (Continued)

Pin

Number

Function

3

These pins are provided to connect external resistors RTi,
RT m and capacitor CT0 to form an R-C oscillator from
which the tone signal is derived. With the oscillator adjusted to 5120Hz, a tone signal with frequencies of 512Hz and
640Hz results. See Table 2 for components selection.

Tone Oscillator
(OSCTi, OSCTm, OSCT0)

Threshold Control (THC)

The internal threshold voltage is brought out to this pin
for modification in non-telephone applications. It should
be left open for telephone applications. For power supplies
less thim 9V connect to VDD.

Rate

1

Detector Inhibit (DI)

This is an o~nal output for the S2561C version which
replaces the EN output. This is a 16Hz output that can be
used by external logic as shown in Figure 3-A to produce a
2sec on/4sec off waveform.
When this pin is connected to VDD , the dial pulse reject
filter is disabled to allow DC level enabling of the tone
ringer. This pin should be hardwired to Vss in normal
telephone-type applications.
When this pin is connected to Vss, only a single frequency
continuous tone is produced as long as the tone ringer is
enabled. In normal applications this pin should be hardwired to VDD.

Single Frequency Select (SFS)

18
*Pinouts of 8 pin S2561A package.

Table 2. Selection Chart for Oscillator Components and Output Frequencies

Tone/Rate Oscillator
Frequency

RI

Oscillator Components
RM

Tone

(kQ)

(kQ)

Co
(pF)

Rate

(Hz)

(Hz)

(Hz)

5120

1000

200

330

16

512/640

20

640/800

10

320/400

25

800/1000

..fQ..

fo/fO
10 8

6400
3200

Select components in the ranges indicated
in the table of electrical charateristics

8000
fo

320

2.43

•

52561/52561 A/52561 C

Applications

Typical Telephone Application: Figure 2 shows the
schematic diagram of a typical telephone application
for the S2561 tone ringer circuit: Power is derived
from the telephone lines by the network formed by
capacitor C1, resistor Rl, diode bridge d1 through d4,
and filter capacitor C2. C2 is chosen to be large
enough so as to insure that the power supply ripple
during ringing does not fall below the internal threshold level (typ. 7.3 volts) and to provide large enough
decay time during the off period. A typical value of
C2 may be 47,uF. C1 and R1 are chosen to satisfy the
Ringer Equivalence Number (REN) specification
(Ref. 1). For REN = 1 the resistor should be a minimum of 8.2kQ. It must be noted that the amount of
power that can be delivered to the load depends upon
the selection of C1 and R 1.
The device is enabled by limiting the incoming ring
signal through resistors R2, R3 and diodes d5 and
d6. Zener diode Zl (typ. 9-27 volts) may be required
in certain applications where large voltage transients
may occur on the line during dial pUlsing. The internal
2ms filter and the dial pulse reject filter will suppress
any undesirable components of the signal and will
only respond to the normaJ 20Hz ring signal. Ring
signals with frequencies above 16Hz will be detected.

In applications where dial pulse rejection is not necessary, such as in DTMF telephone systems, the
ENABLE pin may be connected directly to VDD.
Det. Inh pin must be connected to VDD to allow
DC level enabling of the ringer.

Non-Telephone Applications: The configuration
shown in Figure 3 -A may be used in non -telephone
applications where it is desired to simulate the telephone bell. The internal threshold is bypassed by
wiring THC to VDD. The rate output (16Hz) is divided
down by a 7 stage divider type 4024 to produce two
signals: a 2 second on/2 second off signal and a 4
second on/4 second off signal. The first signal is connected to the EN pin and the second to the DI pin to
produce a 2 second on/4 second off telephone-type
ring signal. The ring sequence is initiated by removing
the reset on the divider. If "auto" mode is used, a
reset signal must be applied to the "amplitude sequencing" counter at the end of a ring sequence so
that the circuit will respond correctly to a new ring
sequence. This is done by temporarily connecting the
"auto/manual" input to VSS.

Figure 3 -B shows a typical application for alarms,
The configuration shown will produce a tone with buzzers, etc. Single frequency mode is used by confrequency components of 512Hz and 540 Hz with a necting the SFS input to VSS. A suitable on/off rate
shift rate of approximately 16 Hz and deliver at least can be determined by using the 7 stage divider circuit.
25m W to an 8Q speaker through a 2000Q:8Q trans- If continuous tone is not desired, the 16Hz output
former. If "manual" mode is used, a potentiometer can be used to gate the tone on and off by wiring it
may be inserted in series with the transformer primary into the ENABLE input.
to provide volume control. If "automatic" mode is
used, resistors R Land R M can be chosen to provide Many other configurations are possible depending
desired amplitude sequencing. Typically, signal power upon the user's specific application.
will be down 20 log.

RLOAD )
( RL + RLOAD

first ring, and down 20 log

~

RLOAD

dB during the
Reference 1. Bell system communications technical
reference:

)

dB during PUB 47001 of August 1976
"Electrical characteristics of Bell System Network
the second ring with maximum power delivered to the Facilities at the interface with Voiceband Ancillary
load beginning the third and consecutive rings.
and Data Equipment" - Sections 2.6.1 and 2.6.3.
RM

+ RLOAD

2.44

AMlt.

52561/52561 A/52561 C

Figure 1-A. Output Stage Connected
for Auto Mode Operation

Figure 1- B. Output Stage Connected
for Manual Mode Operation.

-------~

EN

I

~

I
IOUTH

II () ",,""

I

oUTc

_ _ _ _ _ _ _ ..lI

877276

TRANSFORMER

877277

Figure 2. Typical Telephone Application of the S2561 and S2561A

VOD

18

4

Vss
S2561A

ITO 27V Z

C,
C,

.47J.iF/200V

R,

"j

.47j.1FJ25V

ft,
ft,

Rm
Co

Ot-04 tHeQ04
IN4H2
Z,

20QKQ

"lR.

300pf

R.

t81(2
3.3KQ

S.

IRS'EAKER
2000Q/8QXFMR

9T027VZENER

12VZENER

2.45

•

82561/82561 A/82561 C

Figure 3-A. Simulation of the Telephone Bell in Non- Telephone Applications.

I
VDD

750kH

l~S

1
I

200kH

330pF

,~

L
-

THC

J

()

DUlL

DUlM

I

DUTH

1

S1561C

Ii

DUTe

2

AIM

RESET

4024

~Dl

1 STAGE DIVIDER
1

RATE

,--EN

CK

16Hz

Vss

D1

D2

D3

D,

I" I" I' I'

1

05
15

06

,

0/
3

2SECONOSON,2SECQNOSOFF
4SECONOSON4SECONDSOFF

STARTJSTOP RING SEQUENCE

"
Figure 3-B. Single Frequency Tone Application in Alarms, Buzzers, Etc.

Voo
(181

AIM
(81
(16101

};

(l1ITHC

II()

(1510UTH
SI561C

}I

(141 DUTM

(131 DUll

(12) DUTe
11

EN(1U)

SFSm

RATE
(91
Vss

2.46

52562
REPERTORY DIALER

Features

o
o

o
o
o
o
o

CMOS Process Achieves Low Power Operation
8 or 16 Digit Number Capability
(Pin Programmable)
Dial Pulse and Mute Output

o
o

Tone Outputs Obtained by Interfacing with
Standard AMI S2559 Tone Generator
Two Selections of Dial Pulse Rate

Provides Better Than ± 3% Accuracy Over Supply
Voltage, Temperature and Unit-Unit Variations
and Allows Different Dialing Rates, IDP and
Tone Drive Timing by Changing the Time Base
Power Fail Detection
BCD Output with Update for Number Display
Applications

Two Selections of Inter-Digit Pause
General Description

Memory Storage of 32 8-Digit Numbers or
16 16-Digit Numbers with Standard
AMI S5101 RAM

o

16 -Digit Memory for Input Buffering and for
Redial with Access Pause Capability

o

Accepts the Standard Telephone DPCT
Keypad or SPST Switch X -Y Matrix
Keyboards; Also Capable of Logic Interface

o
o

Ignores Multi Key Entries
Inexpensive, but Accurate R-C Oscillator Design

The S2562 Repertory Dialer is a CMOS integrated
circuit that can perfonn storing or retrieving, nonnal
dialing, redialing or auto dialing and displaying of
one of several telephone numbers. It is intended to be
used with the AMI standard S5101-256x4 RAM that
functions as telephone number storage. With one
S5101 up to 32 8-digit or 16 I6-digit numbers can
be stored. It can provide either dial pulses or DTMF
tones with the addition of the AMI S2559 tone
generator for either the dial or tone line applications.

Data subject to change at any time without notice. These sheets transferred for information only.

Block Diagram

Pin Configuration
--0 VOO
--0 VSS
Ct
RNI

OSCi
oSC m
oSC o

DRS

KEYPAD

RS
Cl
Cs

Voo
NLS

O2

TEST

0,

IPS

RiW
RAM 110 DATA
DISPLAY

TE

MODE
NLS
Rl

03

CE

IPS

HS

0,

PLA

AD
Al

A2
A3 RAM ADDRESS
A4 TONE GENERATOR
A5
AS
A7

MUTE
jjp

A6
As

R3

A,

R2

A3

R,

A2

i'T

A,

C6
Cs

Vss

iiP
877283

2.47

R6
Rs
R,

OSC I

MUTE

MOOE

A,

Ao
OSC o
OSC M

Pi'

HS
DRS

C,
C3
C2
C,

I

82562
Absolute Maximum Ratings:

Supply Voltage. . .. . . . . . . . . .. . . . . . . ... . . . . . .. . . . .. . . . . . . .. . . . . . . . . . . . . . . . . . . . .. ... . . . . . . . . . . .. 13.5V
3.5V to 7.5V
Operating Supply Voltage Range (VDD- Vss) .........................................
Operating Temperature Range ....................................................... -25°C to +70°C
Storage Temperature Range ........................................................ - 40 °C to + 125 ° C
Voltage at any Pin .......................................................... Vss -0.3V to VDD +0.3V
Lead Temperature (Soldering, 10sec) ............................................................ 200°C
Electrical Characteristics:

Specifications apply over the operating temperature range and 4.5V ~ VDD to Vss ~5.5V unless otherwise specified.
Absolute values of measured parameters are specified.
Symbol

VIL
VIH
VOL

Characteristics
Output Drive
DP Output Sink Current
DP Output Source Current
MUTE Output Sink Current
MUTE Output Source Current
PF Output Source Current
CMOS to CMOS
Logic "0" Input Voltage
Logic" 1" Input Voltage
Logic "0" Output Voltage

VO H

Logic" 1" Output Voltage

IDD
IDD

Current Levels
Quiescent Current
Operating Current

IOLDP
IOHDP
IOLM
IOHM
IOHPF

IIH
IlL, IIH
loz
fo

Oscillator Frequency
Frequency Deviation

Molfo

Input Capacitance, Any Pin
Supply Voltage at which PF
Output Goes Low

CIN
VTRIP
..

Input Current Any Pin
(keyboard inputs)
Input Current All Other Pins
Output Current in High
Impedance State

Min.

Max.

400
400
400
400
100
1.5
3.5
0.5
4.5

Conditions

/-lA
/-lA
/-lA
/-lA
/-lA

VO UT =O.4V,
Vo uT =3.6V,
VOUT=O.4V,
VOUT=3.6V,
VOUT=3.6V,

V
V
V

All inputs, VDD = 5V
All inputs, VDD = 5V
All outputs except DP, MUTE,
PF, lo=-10/-lA, VDD =5V
All outputs except DP, MUTE,
PF, lo=-10/-lA, VDD=5V

V

VDD =5V
VDD =5V
VDD=5V
VDD=5V
VDD=5V

500

/-lA
/-lA

Standby, VDD = 5V
All valid input combinations, DP,
MUTE, PF outputs open
VDD=5V

100

/-lA

VIN = VDD, VDD = 5V

100
1

/-lA
/-lA

1
10
+3

/-lA
kHz

VIN=Vss or VDD, VDD=5V
VD D =5V, VOUT=OV data
outputs (D1-D4)
VDD =5V, Vo uT =5V
VDD = 5V (min. duty cycle 30/70)
VDD-VSS from 4.5V to 5.5V.
Fixed R-C oscillator components
50kQ~ RM ~ 750kQ;
1MQ ~ RI ~ 5MQ·:
150pF ~ Co 3000pF; 330pF most
desirable value for Co, fo < 10kHz
over the operating temperature
and unit-unit variations

7.5

pF

4.5

V

25

10

Units

4
-3

2.5

"

%

The dev~ce power supply should always be turned on before the mput sIgnal sources, and the mput s~gnals should be turned off before the power
supply is turned off (Vss'" VI'" VDD as a maximum limit). This rule will prevent over-dissipation and posible damage of the input-protection diode
when the device power supply is grounded. Power should be applied to the device in "on hook" condition.

2.48

S2562
Functional Description
The S2562 is a CMOS controller designed for storing or
retrieving, normal dialing, redialing or auto dialing and
displaying of one of several telephone numbers. It is intended to be used with the AMI standard S5101 256x4
RAM that functions as a telephone number storage. A
single S5101 RAM will store up to 32 8-digit or 16
16-digit telephone numbers. The S2562 can be programmed to work with either 8-digit or 16-digit numbers by
means of the Number Length Select (NLS) input.
The S2562 uses an inexpensive, but accurate R-C oscillator as a time base from which the dialing rate and
inter-digit pause duration (lDP) are derived. Different
dialing rates and IDP durations can be implemented by
simply adjusting the oscillator frequency. The dialing
rate and IDP can be further changed by a 2:1 factor by
means of the dialing rate select (DRS) and inter-digit
pause select (IPS) inputs. Thus, for the oscillator frequency of 8kHz, dialing rates of 10 and 20 pps and
IDP's of 400 and 800ms can be achieved. The mark!
space ratio is fixed independent of the time base at
40/60. Over supply voltage (5V±10%), operating
temperature range and uhlt-unit variations, timing accuracy of ±3% can be achieved. A mute output is also
available for muting of the receiver during dial pulsing.
See Figure 5 for timing relationship.
The S2562 can be programmed by means of the MODE
input for dual tone signaling applications as well. In this
mode, it can interface directly with the AMI standard
S2559 Tone Generator to produce the required DTMF
signals. The tone on/off rate during an auto dial operation in this mode is derived from the time base. For the
oscillator frequency of 8kHz, a tone drive rate of 50ms
on, 50ms off is obtained. Different rates can be implemented by adjusting the time base as desired. See
Tables 2 and 3 for the various combinations. In the tone
mode, the mute output is used to gate the tone
generator on and off. The 8 address lines that are normally used for addressing the RAM are also used to address the tone generator row, column inputs. Figure 6
shows a typical system application.
The S2562 can perform the following functions:
Normal Dialing
The user enters the desired number digits through the
keyboard after going off hook. Dial pulsing starts as
soon as the first digit is entered. The entered digits are
stored sequentially in the internal memory. Since the
device is designed in a FIFO arrangement, digits can be
entered at a rate considerably faster than the output
rate. Digits can be entered approximately once every
50ms while the dialing rate may vary from 7 to 20 pps.
Debouncing is provided on the keyboard entries to
avoid false entries. The number entered is retained for
2.49

future redial. Pauses may be entered when required in
the dial sequence by pressing the "#" key, which provides access pauses for future redial. Any number of access pauses may be entered as long as the total entries
do not exceed the total number of digits (8 or 16).
An update pulse is generated to update the display digit
as a new entry is made.
Redialing
The last number entered is retained in the internal
memory and can be redialed by going "off hook" and
depressing the "redial" (RDL) key. The RDL key is a
unique 2 of 12 matrix location (R5, C3). The number being redialed out is displayed as it is dialed out.
In the tone mode, the redial tone drive rate depends
upon the time base as discussed before.
Storing of a Normally Dialed or Redialed Number into
the External Memory
After the normal dialing or redialing operation, the
telephone number can be stored in tha external memory
for future repertory dialing use by going on hook and
initiating the following key sequence.
1. Push "store" (ST) button.
2. Depress the single digit key corresponding to the
desired address location.

Note that the "ST" key is a unique 2 of 12 matrix location (R5 , Cl ).
Storing of a Telephone Number into the External
Memory
This operation is performed "on hook" and no outdialing occurs. A telephone number can be stored in the
desired address location by initiating the following key
sequence.
1. Push the "*" key (This instructs the device to accept
a new number for storage into the internal memory).
2. Enter the digits (including any access pauses) corresponding to the desired number. Digits will be displayed as they are entered.
3. Push the "ST" key.
4. Push the single digit key corresponding to the desired address location.

The entire sequence can be repeated to store as many
numbers as desired. However, any memory locations not
addressed with a telephone number "store" operation
must be addressed with the following sequence.
1. Push the "*" key.
2. Push the "ST" key.
3. Push the single digit key corresponding to the first
unused memory location.
4. Push the "ST" key.

S2562
5. Push the single digit key corresponding to the next
unused memory location.
8teps 4. and 5. are repeated until all remaining memory
locations have been addressed.
It should be noted that accessing all memory locations is
required only for initial system set-up. This insures that
no memory ·location will contain invalid data from
memory power-up. If a memory location were to have invalid, power-up induced data and that location was addressed by the 82562, the 82562 would enter a "Halt"
state and cease its normal program activities. To exit
from this condition it is necessary to go "on hook" and
perform a "store" operation.

Pause
Note that the out dialing in the repertory or redial
operation continues unless an access pause is detected.
The outpulsing will stop and resume only when the user
terminates the access pause by pushing the "*" key
again.
Power Fail Detection

Displaying of a Stored Telephone Number

Memory Expansion
The memory can be expanded by paralleling additional
85101 RAM's. External logic must be used to enable
the desired RAM corresponding to a desired address
location. The 82562 can drive up to 2 RAM's without
the need of buffering address and data lines.

This is an "on hook" operation Either the last dialed
number or the number stored in the external memory
can be displayed one digit at a time. The key sequence
for displaying the last dialed number is as follows:
Push the "RDL" key.

This output is normally high. When the supply voltage
falls below a predetermined value, it goes low. The output can then drive a suitable latching device that will
switch the memory to either the tip and ring or an auxiliary battery supply.

Keybounce Protection
When a key closure is detected by the 82562, an internal
timeout (4ms at fo=8kHz) is started. Any transitions
that occur during this timeout will reset the timer to
zero so that a key will only be accepted as valid after a
noise free timeout period. The key must remain closed
Note that the "R" key is a unique 2 of 12 matrix loca- for an additional 16ms before released. Thus, the total
make time of the key must be at least 20ms. The key
tion (R5 , C2 ).
The number is displayed one digit at a time at a rate must be released for at least Ims before a new key is
determined by the time base. With a time base of 8kHz activated. Any transitions occurring when the key is
the display will be on 500ms, off 500ms. The display is released are ignored as long as the make time does not
updated by producing an update pulse. The update exceed 4ms.
pulse must be decoded with external logic (one inverter Keyboard Entry Options
and one 2-input gate) as shown in Figure 6.
Figure 4 shows two options for arrangement of a
The display is blanked by outputting an illegal (non keyboard for dialing of 32, 8 digit or 16, 16 digit
BDC) code such as 1111. The 4511-type BCD to 7 seg- numbers. A single 85101 memory is sufficient for
ment decoder driver latch will blank the display when number storage in the basic scheme.
the illegal code is detected. When other driver circuits Increasing Number Capacity
are employed, external logic must be used to detect the
To increase the capacity from 16, 16 digit numbers to
illegal code. Table 4 gives a list of display codes used by
32, 16 digit numbers, an additional memory must be us82562.
ed. Since in the 16 digit mode, the 82562 decodes keys
Repertory Dialing
in locations 17 through 32 as locations 1 through 16, the
This is the most common mode of usage and allows the additional memory can be simply paralleled with the
user to dial automatically any number stored in the first memory. Note that keys 17 through 32 are in row 6
memory. This mode is initiated by the following key se- and columns 5 and 6. This permits use of a simple
decoder to separate the keys into two address fields. A
quence after going off hook.
latch then can be set or reset depending upon the loca1. Push the "*" key.
tion of the key. The outputs of the latch can then direct2. Push the single digit key corresponding to the de- ly select the appropriate memory via CE pin of each
2
sired address location.
memory. Capacity can also be increased to 64, 8 digit
The number is displayed as it is dialed out. In the tone numbers by paralleling of two 32 key keyboards and
mode, the tone driver rate is dependent on the time base two 5101 RAM's selection of appropriate memory can
as described earlier.
be done as indicated above.

The number in the external memory can be displayed as
follows:
1. Push the "R" key.
2. Push the single digit key corresponding to the desired address location.

2.50

52562
Table 1. Pin/Function Descriptions

Number

Function

Power (VDD, VSS)

2

These are the power supply inputs. The device is designed
to operate from 3.5V to 7.5V.

Keyboard (RI-R6, CI-C6)

12

These are 6 row and 6 column inputs from the keyboard
contacts. When a key is pushed, an appropriate row and
column input must go to VDD or connect to each other.
Figures 1 and 2 depict the standard telephone DPCT and
X-Y matrix keyboard arrangements that can be used. A
logic, interface is also possible as shown in Figure 3. Debouncing is provided to avoid false entry. Key pad entry
options are shown in Figure 4.

Number Length Select (NLS)

1

This input permits programming of the device to accept
either 8-digit numbers or 16-digit numbers.

Mode Select (MODE)

1

This input allows the use of the device in either dial pulsing applications or tone drive applications.

Dial Rate Select (DRS)

1

This input allows selection of two different dialing rates
such as 10 or 20 pps, 7 or 14 pps, etc. See Tables 2 and

Pin

3.
Inter-Digit Pause Select (IPS)

1

This allows selection of the pause duration that exists
between dialed digits. It is programmed according to the
truth table shown in Table 3. Note that preceeding the
first dialed digit is an inter- digit time equal to the selected
IDP. Two pause durations, either 400ms or BOOms are
available at dialing rates of 10 and 20 pps. IDP's corresponding to other dialing rates can be determined from
Tables 2 and 3.

Test Input (TEST)

1

This input is used for test purposes. For normal operation
it must be tied to VDD.

Mute Output (MUTE)

1

A pulse is available that can provide drive to turn on an
external transistor to mute the receiver during dial pulsing. See Figure 5 for mute and dial pulse output relationship. It is also used as a keyboard disable in the tone
drive applications. See Figure 6.

Dial Pulse Output (DP)

1

Output drive is provided to turn on a transistor at the
dial pulse rate. This output will be normally high and go
low during "space" or "break."

Display Memory I/O Data (DI-D4)

4

These are 4 bidirectional pins for inputting and outputting data to the external memory and display driver.
2.51

I

ltMII.

52562

Table 1. (Continued)

Pin

Number

Function

Memory Enable (CE)

1

This line controls the external memory operation.

Memory Read/Write (R/W)

1

This line controls the read or the write operation of the
external memory. This output along with the CE output
can be used to produce a pulse to update the external
display. See Figure 6.

Tone Generator/Memory Address
(AO-A7)

8

These are 8 output lines that carry the external memory
address and tone generator row/column information.

Hook Switch (HS)

1

This input conveys the state of the subset. "Off hook"
corresponds to V SS condition.

Power Fail Detect (PF)

1

This output is normally high and goes low when the
power supply falls below a certain predetermined value.

Oscillator (aSCi, OSCm , OSC o )

3

These pins are provided to connect external resistors R I,
RM and capacitor Co to form an R- C oscillator that generates the time base for the repertcry dialer. The output
dialing rate, tone drive rate and IDP are derived from
this time base.

40

Table 2. Table for Selection of Oscillator Component Values for Desired Dialing Rate, lop or Tone Drive Rate
Dial Rate Osc. Freq.
Desired
fo
(PPS)
(Hz)
5.5/11

6/12
6.5113

7/14
7.5/15

8/16
8.5117

9/18
9.5119
10/20

(fo/800/
(fo/400)

4400
4800
5200
5600
6000
6400
6800
7200
7600
8000
fo

Oscillator Components
(R 1)
RM
Co
(kQ)
(kQ)
(pF)
TBD
220
190
1000
TBD

110

300

Dial Rate (PPS)

IDP (ms)

DRS=Vss DRS=VDD IPS = Vss
11
1454
5.5
12
1334
6
13
6.5
1230
14
1142
7
15
1066
7.5
16
1000
8
17
8.5
942
18
9
888
19
842
9.5
20
10
800
fo/800
fo/400
6400 x10 3
fo

2.52

IPS=VDD
727
667
615
571
533
500
471
444
421
400
3200
x10 3
-fo

Tone Drive
OnlOff
Time (ms)
90/90
83.3/83.3
77/77

71171
66.7/66.7
62.5/62.5
59/59
55.5/55.5
52.6/52.6
50/50
3/400 x10 3
400
x10
fo
fo

52562

I

Figure 1. Standard Telephone Pushbutton Keyboard

I
I

R,

~I-

-0--0)--0)

-

I
I

I
I

I
I

0--0)--0)---1
I
I
I
e.-o-R3~'--

-

I

I

I

I

I

I

R2

-9--CP--CP
0--0)--0---,
I

,~R4

'--_----.:.I..fJ'o_ _--<"r-_--....:I.Jf'___......._ _ _ COMMON

'--

(CONNECT TO VOD OR
LEAVE FLOATING)
- - - MECHANICAL
LINKAGE

RON (CONTACT RESISTANCE)';; lkn
871290

Figure 2. SPST Matrix Keyboard Arranged in the 2 of 12 Row, Column Format

~---.----

__--------.R,

--+----.-+----~--------.R3

--+----.-+----~--------.R4

I

I

C,

C3 -

SPST MATRIX KEYBOARD:

877285

2.53

-

-

-

-

- Cs

R6

82562

Figure 3. Logic Interface For the S2562

Gl

Dl
Rl

Joo....L
V-I

KEYBOARD
INPUTS

......
..... ,

S2562
C6

D12

G12
877286

Gl through G12 any CMOS type logic gates.
Dl through D12 DIODES type IN 914. (Optional)
A valid key closure corresponds to a logic high level on one row and one column

Figure 4. Example of Keypad Entry - Options

C1

C2

C3

C4

C5

Cs

I

OPTION FOR lS,
lS DIGIT NUMBERS-

GJ
0
-.
0
c:J
0

CD 0 B

0

@] @J

Rl

IT] @] @] @]

R2

~ ~

R3

~ ~

R4

IT]

0 G
@J
0 8 r---0 B J!~
_____________
15

10

12

@] ~
0
@] @] @] ~ §] @]

877287

•

OPTION FOR 3J, 8 DIGIT NUMBERS

2.54

R5

RS

S2562

Table 3

Function

Pin Designation

Input Logic Level

Selection

Dial Rate Selection

DRS

Vss
V DD

(fo/800) pps
(fo/400) pps

Inter-Digit Pause Selection

IPS

VDD
VSS

(3200/fo) S
(6400/fo) S

TEST

Vss
VDD

Test Mode
Normal Mode

HS

VDD
Vss

On Hook
Off hook

MODE

Vss
VDD

Dial pulse
Tone Drive*

NLS

Vss
VDD

8 digits
16 digits

Test Input

Hook Switch

Mode Selection

Number Length Selection

*For tone mode also set DRS=VSS. IPS=VSS and Test=VDD.
Note: fo is the oscillator frequency and is d~termined as shown in Table 2.

Figure 5A. Mute and Dial Pulse Output Timing Relationship

I

DP

I

I

I
I

I

I

I

I

I MARK: SPACE

I

IDP

:-40-:-60-l
_I

lOP

1_

MU~~~________________________________________~r---

Mute will reset i) when the number of digits dialed out equals either the number of digits entered or the maximum
selected (8 or 16) or ii) when an access pause is detected.

Figure 58. Mute and Tone Output Timing Relationship

I

MUTEI

f- ~ +- -¥Cp- ..j

-JL,"'f~'--I.--"4f~"'d-.-~"""4f"'~d""+-""4"'Pod"'-~--i!f

I

I VALID I,NVALIDI VALID I

TONE
GEN. __~
~AJ\
OUTPUT
VVv
ull---------.-JinAII

~:~----';"I-V...:cA!-lID--';"I-IN~VA~L-'D"';'I-------

-VVvv~

~'-

__...JliIlAN\"_ _ _ _ _ _ _ _ _ __

Mute output will reset il when the number of digits dialed out equals the number of digits entered or equals the maximum selec
ted (8 or 16) or ii) when an access pause is detected. In the normal dialing mode when digits are entered one at a time the mute
output will reset between digits provided the time between entered digits exceeds
In both the normal dialing or automatic
dialing mDde tone will be output for a fixed duration of
150m,", for fo = 8kHz).

w.-

2.55

w.-.

•

AMII~

52562

Figure 6. Typical Application of the S2562

'T
2' C
22 c~
23 :

Vss

VDO

0,

U

J
[)7

C3
24
CII
25
26 CS

Il,

,
2
3

,

C,

G]00 ~@]@]
0G[6J @)@J@]
000 B@JG

o·0 0
'0

~§J@)

IT

31 All

@]@]@]~~[EJ

33 RS

"'"~""

6~P~~~ION~ Vss
UPON APPliCATION

OIGIT
DISPLAY

30 R3

32

{

SINGLE

\

R2

§]0§9@]G~

OSCILLATOR

'I

Lf

28 RI

RS

10121416
REPERTORY
DIALER

52562

RIIS
RM 18

1~

01/1 DO 1 002 003 004

:~

01 3

;19~

OSCI

'0
' -_ _---""i

OSCM

1705CO

AO

Co

A,

{

A2

CE,
RW

r::-----1---'-I'
AO
~:
J

I-"----.-t--'-I A,

2
1-"-_--,-++---'-1
A2
"

A3 13

A4

\ A3
1-"----.+H--'-I
2
12
1-"----t+H--'-1 A,

A5 II

Pi'

iiP

1-"-..--++++---'-1 A5
A6 10
r::--ff--++++---'-I' A,
A) ,
1-"-+t0

1-1-

1

01011111

-.33

31

01001111

00101111
00011111

-t:!-+-

00001111 I--- I-00000000

-1

-.66

lY

V
.Y1

-.33

-.66

-1.0

.33

.66

~~

1

~~~

1

VI

4}

00111111

KK

II

j

1/8

V

1.0

2l

I

0

g

-

0

0

0

r~ - -- §- - -

0

0

-

PCM INPUT

83502 Transfer Characteristics

83501 Transfer Characteristics

2.62

~II.

53501/53501 A, 53502153502A

53501 Absolute Maximum Ratings

DC Supply Voltage VDD ....................................................................... +6.5V
DCSupplyVoltageVss ........................................................................ -6.5V
Operating Temperature ................................................................. O°C to +70°C
Storage Temperature ...................................................... " . ... . .. -55°C to + 125°C
Power Dissipation at 25°C ..................................................................... 250mW
Digital Input ................. " . . . .. . . . . . . . . . . . . . . . . . .. .. . . . .. . . . . . . . . . . . . . . .. -0.3~VIN~VDD + 0.3
Analog Input .................................................................. - VREF~ VIN~ + VREF
-VREF ............................................................................... VSS~VREF~O
53501 Electrical Operating Characteristics (TA = 25 ° C)

Power Supply Requirements
Symbol

Parameter

Min.

Typ.

Max.

Units

5.0
-5.0
-3

6.0
-6.0
-3.25

V
V

100

VDD

Positive Supply

Vss
-VREF

Negative Suppply

4.75
-4.75

Negative Reference

-2.4

POPR

Power Dissipation (Operating)

70

PSTBY

Power Dissipation (Standby)

15

Conditions

V
mW

Vnn=5.0V,
VSS=-5.0V,
-VREF=-3.0V

mW

53501 AC Characteristics (Refer to Figures 1 and 2)

Symbol

Min.

Typ.

Max.

Units

0.056
40

1.544

3.152

MHz

50

60

%

Shift Clock Rise Time

100

ns

Shift Clock Fall Time

100

ns

trs

Strobe Rise Time

100

ns

tfs

Strobe Fall Time

100

ns

tsdOn)

Shift Clock to Strobe (On) Delay

0+

(112 CP)-

Shift
Clock
Period

tsc (Off)

Shift Clock to Strobe (Off) Delay

0+

(1/2 CP)-

Shift
Clock
Period

Parameter
Shift Clock Frequency

fsC
Dsc
trc

Shift Clock Duty Cycle

tfc

td(On)

Shift Clock to PCM Out (On) Delay

100

125

ns

td (Off)

Shift Clock to PCM Out (Off) Delay

100

125

trd

PCM Output Rise Time CL = 50pF

100

125

ns
ns

tfd

PCM Output Fall Time CL = 50pF
AlB Select to Strobe Trailing Edge
Set UpTime
Phase-Lock Loop Lock Up Time

50

70

ns

tdss
tL
t·J

ns

100
20

P-P Jitter of Strobe Rising Edge

2.63

35

ms

5

I-Is

Conditions

Resistive Pull-Up on
PCM Out selected for
desired rise time

83501/83501 A, 83502/83502A

53501 DC Characteristics (VDD =

+ 5V, Vss = -

Symbol

Parameter

RINA
C1N

Analog Input Resistance

IINL

5V, - VREF = - 3.0V unless otherwise specified)
Min.

Typ.

Max.

Units
MQ

Input Capacitance

10

pF

V1N -, VIN+ Inputs
All Logic and Analog Input

Logic Input Low Current
(Shift Clock, Strobe)

1

I1A

V1L =0.8V

1

I1A
V

VIH=2.0V

10

Conditions

IINH
V1L
VIH

Logic Input High Current

I REF -

Negative Reference Current

RREF-

Negative Reference Input
Resistance

VOL

Logic Output "Low" Voltage
(PCM Out)

0.4

V

IOL=5mA

VOL

Logic Output "Low" Voltage
(AlB Out)

0.8

V

IOL=lmA

IOH

PCM Output Off Leakage Current

100

nA

Logic Input "Low" Voltage

0.8

Logic Input "High" Voltage

2.0

V
100

nA
MQ

10

Vo=O to 5V

53502 Decoder with Filter
Functional Description

ly 20ms. During this time the AlB outputs and the
analog output stage are held in the idle state.

83502 Decoder with Filter consists of (1) a digital to
analog converter that uses a capacitor array; (2) a low
pass filter with D3 filter characteristic; (3) a phase-lock
loop that generates all internal timing signals from the
externally supplied strobe signal and (4) control logic
that performs miscellaneous logic functions.

The control logic implements the loading of the input
shift register, signaling logic and other miscellaneous
functions. A new data word is shifted into the input
register on a positive transition of the strobe signal at the
shift clock rate. The received data is decoded by the DIA
converter and applied to the sample and hold circuit. The
output sample and hold circuit is filtered by a low pass
filter. The low pass filter is a sixth order elliptic filter. The
combined response of the sample and hold and the low
pass filter is shown in Figure 5.

The digital to analog converter uses a capacitor array
based on charge redistribution technique (Ref. 1) to perform the D/A conversion with a /1"255 law transfer
characteristic (See Figure 4).
The timing signals required for the low pass filter
(1 28kHz) digital to analog converter (1.024MHz) are

generated by a phase-lock loop comprised of a VCO, a frequency divider, a loop filter and a lock detector. The loop
locks to the externally supplied 8kHz strobe pulses. In
the absence of the strobe pulses, the lock detector detects
the unlocked condition and forces the device into a
power-down mode thereby reducing power dissipation to
a minimum. Thus, power-down mode' is easily implemented by simply gating the strobe pulses "off" when
the channel is idle. During the power-down mode the output amplifier is forced to a high impedance state and the
A, B outputs are forced to inactive state. The lock-up
time, when strobe pulses are gated "on", is approximate-

Signaling information is received and latched immediately after the AlB select input makes a positive or negative transition. On the positive transition of the AlB
select input information received in the eighth bit of the
data word is routed to the AoUT pin and latched until updated again after the next positive transition of the AlB
select input. Similarly "B" signaling information is
routed and latched at the BOUT pin after each negative
transition of the AlB select input. The A and B outputs
are designed such that either relay or TTL compatibility
can be achieved (see detailed description under Pin/Function descriptions). In the CCIS compatible AlB signaling
option "A" bit is latched during the data bit 1 time and
"B" bit is latched during the data bit 8 time.

2.64

AMite

83501/83501 A, 83502/83502A

53502 Decoder with Filter
Pin/Functions Descriptions

Strobe: (Refer to Figure 1 for timing diagram. I This TTL
compatible input is typically driven by a pulse stream of
8kHz rate. Its active state is defined as a logic 1 level and
is normaly active for a duration of 8 clock cycles of the
shift clock. It initiates the following functions: (11
instructs the device to receive a PCM data word serially
on PCM IN pin at the shift clock rate; (21 supplies sync information to the phase-lock loop from which all internal
timing is generated; (31 conveys power-down mode to the
device by its absence. (See functional description of the
phase-lock loop for details.)
Shift Clock: This TTL compatible input is typically a
square wave signal at 1.544MHz. The device can operate
with clock rates from 56kHz (as in the single channel
7-bit PCM systeml to 3.152MHz (as in the TI-C carrier
systeml. Data is shifted in the PCM IN buffer on the falling edges of the clock after the strobe signal makes a
logic 0 to logic 1 transition.
PCM IN: This is a TTL compatible input on which time
multiplexed PCM data is received serially at the shift
clock rate during, the active state of the strobe signal.
AlB Select: (S3502 only) (Refer to Figure 6 for timing
diagram.) This TTL compatible input is provided in
order to select the path for the signaling information.
It is a transition sensitive input. A posi~ive transition
on this input routes the received signaling bit to the
"A" output and a negative transition routes it to the
"B"output.
A Out, B Out: These two open drain outputs are provided
to output received signaling information. These outputs
are designed in such a way that either LS TTL or relay
drive compatibility can be achieved. With a suitable pullup resistor (47KQ) connected to the LS TTL logic supply,
the output voltage will swing between digital ground and
the LS TTL logic supply when the polarity pin is connected to digital ground. (See Figure 6.) The output
polarity is the same as the received signaling bit polarity.
If the polarity pin is connected to the Vss supply, the output voltage will swing between Vss and VDn supplies
with a suitable pull-up resistor. This facilitates driving a
relay by a PNP emitter grounded transistor in - 48V
systems. The output polarities are inverted from the
received signaling bit polarity to facilitate relay driving.
Polarity: This pin is provided for testing purposes and
for controlling the AlB output polarities and TTL/relay

drive compatibilities. For TTL compatibility this pin is
connected to digital ground. The AlB output polarities
are then the same as the received signaling bit polarities.
For relay drive capability this pin is connected to the Vss
supply. The AlB output polarities then are inverted from
the received signaling bit polarities. Test mode results
when this pin is connected to VD D . In this mode the
decoder output (S&H output) is connected to the B-Out
pin while the filter input is connected to the A-Out pin.
- VREF: The input provides the conversion reference for
the digital to analog conversion circuit. and the phaselock loop. A value of - 3 volts is required. The reference
must maintain 100ppM/oC regulation over the operating
temperature range. A high input impedance buffer is provided on this input which facilitates bussing of the same
reference voltage to several devices as well as local R-C
filtering at the input of the device.
VOUTH: This is the output of the low pass filter which
represents the recreated voice signal from the received
PCM data words. This is a high impedance output which
can be used by itself or connected to the output amplifier
stage which has a low output impedance.
VOUTL, IN -: These two pins are the output and input of
the uncommitted output amplifier stage. Signal at the
VOUTH pin can be connected to this amplifier to realize a
low output impedance with the unity gain, increased gain
or reduced gain. This allows easier calibration of the
receive channel and testing of the decoder in a stand
alone situation.
Analog Ground, Digital Ground: Two separate pins are
provided for connection of analog signals referenced to
analog ground and digital signals referenced to digital
ground. This minimizes switching noise associated with
the digital signals from affecting the analog signals.
VDD , Vss: These are power supply pins. The device is
designed to operate from power supply voltages of ± 4. 75
to ± 6.0 volts.
Loop Filter: A capacitor CLOOP (nominal O.IJ.tF is required
from this pin to digital ground to provide filtering of the
phase comparator output.
AlB IN: (S3502A only) This optional TTL compatible
input is provided to implement CCIS compatible AlB
signaling scheme. Time multiplexed AlB signaling information is applied at this input and recovered by the
decoder as shown in Figure 2-b.

2.65

I

AMII.

53501/53501 A, 53502/53502A

53502 Absolute Maximum Ratings

DC Supply Voltage VDD ....................................................................... +6.5 V
DCSupplyVoltageVss ........................................................................ -6.5V
Operating Temperature ........................................... " .......... " ...... " O°C to +70°C
Storage Temperature ............................................................... -55°C to +125°C
Power Dissipation at 25°C .................................................................... 250mW
Digital Input .................................................................. -0.3~VIN~VDD + 0.3
Analog Input .................................................................. - VREF~ VIN~ + VREF
- VREF ............................................................................... VSS~VREF~O
53502 Electrical Operating Characteristics (TA = 25°C)
Power Supply Requirements

Symbol

Parameter

Min.

Typ.

Max.

Units

VDD
Vss
-VREF

Positive Supply
Negative Reference

-2.4

5.0
-5.0
-3

6.0
-6.0
-3.25

V

Negative Suppply

4.75
-4.75

V
V

POPR

Power Dissipation (Operating)

100

mW

PSTBY

Power Dissipation (Standby)

55
15

Conditions

VOO=5.0V.
VSS=-5.0V.
- VREF=-3.0V

mW

53502 AC Characteristics (Refer to Figures 1 and 6)

Symbol

Parameter

Min.

Typ.

Max.

Units

fsC

Shift Clock Frequency

0.056

1.544

3.152

MHz

Dsc
trc
tfc

Shift Clock Duty Cycle

40

50

60

%

Shift Clock Rise Time

100

ns

Shift Clock Fall Time

100

trs

Strobe Rise Time

100

ns
ns

tfs

Strobe Fall Time

100

ns

tsdOn)

Shift Clock to Strobe (On) Delay

0+

(112 CP)-

Shift
Clock
Period

tsc (Off)

Shift Clock to Strobe (Off) Delay

0+

(112 CP)-

Shift
Clock
Period

trd

PCM Input Rise Time

tfd
tL
t·J

PCM Input Fall Time

100

Phase-Lock Loop Lock Up Time

20

p-p Jitter of Strobe Rising Edge

100

ns
ns

35

ms

5

/AS

td(On)

Shift Clock to PCM Input
(On) Delay

100

ns

td (Off)

Shift Clock to PCM Input
(Off) Delay

100

ns

tAIBS

AlB Select Set Up Time to
Strobe Trailing Edge

tAO. tBO

Strobe Falling Edge to
AlB Out Delay

ns

100
200
2.66

ns

Conditions

AMII.

S3501/S3501 A, S3502lS3502A

•

Figure 5. S3502 Decoder Filter with Sample & Hold Loss Response

ldB/DIV

10dB/DIV
+1.0

+10

-2.0

-20

-3.0

-30

-4.0

-40

+0.15

-1.0

MAX

-r

RETURN

-5.0

-50

.2
FREOUENCY (kHz) -

Figure 6. Decoder AlB Output Timing

~~,~~
STROBE

I
I

I
I

I

I

iLl- - - - - Y l

~~~

AlB SELECT

. ..v

./

--~--~
AOUT

I

I

I

~~

'I

I

I

I

~~~

I
----.j

I

tAO

~
I

~----------------~~~~

i

--------

~----~I

I

I

I

______________________________,i_________
I
---.j

I

BOUT

2.67

tao

AMII~

53501/53501 A, 53502/53502A

53502 Decoder with Filter DC Characteristics
(VDD= +5V, Vss= -5V, -VREF= -3.0V unless otherwise specified)

Symbol

Parameter

Min.

RdVoUTd
RINA(IN-)

Output Load Resistance

600

Units
Q

Analog Input Resistance

10

MQ

C1NA(lN-)

Analog Input Capacitance

10

pF

I REF -

Negative Reference Current

100

nA

RREF-

Negative Reference Input
Resistance

V1L

Logic Input (Shift Clock,
Strobe, PCM In) "Low" Voltage

Vm

Logic Input "High" Voltage

IINL

Typ.

Max.

Conditions

MQ

10

0.8

V

Logic Input "Low" Current

1

/AA

VIL=0.8V

IINH

Logic Input "High" Current

1

/AA

Vm=2.0V

VOL

A, B Output "Low" Voltage

0.8

V

Polarity = Dig.
Gnd, IOL=lmA

VOL

A, B Output "Low" Voltage

Vss+1.0

V

Polarity = Vss, IOL = 1mA

2.0

V

53501153502 5ystem Characteristics
Typical Group Delay Characteristic

Abs. Gr. Delay

Relative Gr. Delay Distortion

/AS

(Over Band of 1000 Hz to

Device
f = 1000Hz

f = 2600Hz

2600Hz wrt 1000Hz) /AS

Encoder Low Pass Filter

132

220

Encoder High Pass Filter

104

22

88
-82

Encoder Filter Total

236

242

6

Decoder Low Pass Filter

153

250

97

Encoder + Decoder Filters (Total)
End to End Group Delay
(Encoder Analog Input to
Decoder Analog Output)

389

492

103

639

742

103

Parameter
Signal-to-Distortion

Gain Tracking

Idle Channel Noise
a) End to End
b) Decoder only
Transmission Level Point

Min.

Typ.

Max.

Units

Conditions

38
27
22

dB

Analog Input=O to -30dBmO
Analog Input=-30 to -40dBmO
Analog Input= -40 to -45dBmO

±.25
±.5
±1.5

dB

Analog Input= +3 to -40dBmO
Analog Input= -40 to -50dBmO
Analog Input= -50 to -55dBmO

dBmcO
17
7

20
10
dBm

+5.2
2.68

Analog Input=Analog Ground
thru 6000
PCM In to VDD
With -3V VREF and RL =6000

AMII~

53501/53501 A, 53502/53502A

Figure 7. Suggested Anti·Aliasing Filter for Encoder
. - - - - - - - - - . . - - PIN 3 (VINF)

1300pF

f " - - - + - - - P I N 5 (VIN-)

T··~'
ANALOG GROUND

2.69

I

ADVANCED PRODUCT DESCRIPTION

S3503/S3504

SINGLE CHANNEL
A·LAW PCM CODEC/FILTER SET
Features
D CMOS Process, for Low Power Dissipation and
Wide Supply Voltage Range
D Full Independent Encoder with Filter and
Decoder with Filter Chip Set
D Meets or Exceeds CCITT G. 711, G.712 and G.
733 Specifications
D On-Chip Dual Band Width Phase-Lock Loop
Derives All Timing and Provides Automatic
Power Down
D Low Absolute Group and Relative Delay Distortion
D Single Negative Polarity Voltage Reference Input
D Encoder with Filter Chip Has Built-In. Dual
Speed Auto Zero Circuit with Rapid Acquisition
During Power Up that Eliminates Long Term
Drift Errors and Need for Trimming
D Serial Data Rates from 56kb/s to 3.152Mb/s at
8kHz Nominal Sampling Rate
D Programmable Gain Input/Output Amplifier
Stage

General Description
The 83503 and 83504 form a monolithic CM08 Companding Encoder/Decoder chip set designed to implement the per channel voice frequency CODEC8 used in
PCM systems requiring an A-law transfer characteristic. Each chip contains two sections: (1) a band-limiting
filter, and (2) an analog -digital conversion circuit that
conforms to the A-law transfer characteristic. Typical
transmission and reception of 8-bit data words containing the analog information is performed at 2.048Mb/s
rate with analog sampling occurring at 8kHz rate. A
strobe input is provided for synchronizing the transmission and reception of time multiplexed PCM information of several channels over a single transmission line.
These chips are pin-for-pin replacements for the 835011
83502 chip set with the exception of the A-law transfer
characteristic conforming to CCITT G. 711 and the unused signaling capability which remains available for
special applications.

53503 Block Diagram Encoder With Filter

Pin Configuration

Vooo------..
'ssO------

:::lOBo----....
GilD

0----+PIN 10,11, 12 TO Voo FOR MORMAL OPlRATtON

53504 Block Diagram Decoder wi~!1_~i~!~~ _______________ -,

'sso---.
~~G~lAl 0 - - - .
GND

0.--..-

I

,

I

,

----------------:~~
2.70

Pin Configuration

... , TO DlGRAl8ROUND,PIN 2, 11 0PfIiI FOR NOIIMAL OfIEIIATION

ADVANCED PRODUCT DESCRIPTION

S2811
SIGNAL PROCESSING
PERIPHERAL
Features

o
o
o
o

o
o

o
o
o

General Description

High Speed VMOS Technology
Programmable for Digital Processing of
Signals in Voice-Grade Communications
Systems and Other Applications with Signal
in the Audio Frequency Range
Extremely Fast 12-Bit Parallel Multiplier
On-Chip 1300ns Max. Multiplication Time)
Built-in Program ROM 1256x17)*, 3-Port Data
Memory 1256x16) and Add/Subtract Unit IASU)
Pipeline Structure for High Speed Instruction
Execution 1300ns Max. Cycle Time)
Bus-Oriented Parallel I/O for Easy
Microprocessor Interface
Additional Double Buffered I/O for Ease of
Asynchronous Serial Interface
On-Chip Crystal Oscillator 120MHz) Circuit
Pre-Programmed Standard Parts to Be
Announced Shortly

The S2811 Signal Processing Peripheral (SPP) is a high
speed special purpose arithmetic processor with on-chip
ROM, RAM, multiplier, adder/subtractor, accumulator
and I/O organized in a pipeline structure to achieve an
effective operation of one multiply, add and store of up
to 12 bit numbers in 300 nanoseconds.
User Support

A real time in circuit emulator, the RTDS2811 is under
development. This is a fully compatible hardware
emulator with software assembler/disassembler and
editor for rapid program development and debugging.

*Out of the 256 instruction locations of the ROM, 250 are usable by the
user program. Six instruction locations are reserved for in-house
testing.

Pin Configuration

Block Diagram

ACCUMULATOR BUS

Serial

Port
16

Obu.
CONTROL
PROCESSOR
INTERFACE Fbu.

2.71

I

ltMII.

52811

Absolute Maximum Ratings

Supply Voltage .................................................................................. 7.0VDC
Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. O°C to + 70°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to + 125°C
Voltage at any Pin ............................................................... V88 - 0.3 to Vcc + 0.3V
Lead Temperature (soldering, 10 sec.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 200°C
Electrical Specifications (V cc = 5.0V ± 5%; V88 = OV, T A = O°C to + 70°C unless otherwise specified)

Symbol

CI

Parameter
Input HIGH Logic "I" Voltage
Input LOW Logic "0" Voltage
Input Logic Leakage Current
Input Capacitance

VO H

Output HIGH Voltage

VOL

Output LOW Voltage

fCLK
PD

Clock Frequency
Power Dissipation

VIR
VIL

lIN

Min.
2.0
-0.3

Typ.

1.0

Max.
Vcc +0.3
0.8
2.5
7.5

20
0.5

Conditions
Vcc= 5.0V
Vcc= 5.0V
VIN = OV to 5.25V

V

ILOAD = -lOOJ.l.A, Vcc = min,
CL=30pF

0.4

V

ILOAD = 1.6mA, Vcc = min,
CL=30pF

1.0

MHz
W

2.4

5.0

Units
V
V
pAdc
pF

VCC=5.0V
VCC= 5.0V

SPP Pin/Function Descriptions

Microprocessor Interface (16 pinsl
DO through D7

(Input/Output) Bi-directional 8-bit data bus.

FO through F3

(Input) Control Mode/Operation decode. Four microprocessor address leads are used for this purpose. See "SPP CONTROL MODES AND OPERATIONS." (Table 1)
(Input) Interface enable. A low level on this pin enables the SPP microprocessor interface.
Generated by microprocessor address decode logic.

R/W

(Input) Read/write select. When HIGH, output data from the SPP is available on the data bus.
When LOW, data can be written into SPP.
(Output) Interrupt request. This open-drain output will go LOW when the SPP needs service
from the microprocessor.
(Input) When LOW, clears all internal registers and counters, clears all modes and initiates program execution at location 00.

Serial Interface f6 pinsl
SICK, SOCK

Serial Input/Output clocks. Used to shift data int%ut of the serial port.

S1

(Input) Serial input. Serial data input port. Data is entered MSB first and is inverted.

SIEN

(Input) Serial input enable. A HIGH on this input enables the serial input port. The length of the
serial input word (16 bits maximum) is determined by the width of this strobe.

SO

(Output) Serial output. Three-state serial output port. Data is output MSB first and is inverted.

SOEN

(Input) Serial output enable. A HIGH on this input enables the serial output port. The length of
the serial output (16 bits maximum) is determined by the width of this strobe.
2.72

52811

Miscellaneous

OSCi> OSC o

An external 20MHz crystal with suitable capacitors to ground can be connected across these
pins to form the time base for the SPP. An external clock can also be applied to OSCi input if the
crystal is not used.

Vee, Vss

Power supply pins Vee = + 5V, Vss = 0 volt (ground).

Operating in a microprocessor system, the SPP can be
viewed as a "hardware subroutine" module. The microprocessor can call up a "subroutine" by giving a command to the SPP. A powerful instruction set (including
conditional branching and one level of subroutine) permits the SPP to function independently of the microprocessor once the initial command is given. The SPP
will interrupt the microprocessor upon completion of its
task. The microprocessor is free to perform other operations in the interim.

Functional Description

The main functional elements of the SPP (see Block
Diagram) are:
1. a 256x17 ROM which contains the user program,

2. a 3-port 256x16 data memory (one input and two output ports) which allows simultaneous readout of two
words,
3. a 12-bit high-speed parallel multiplier
4. an Add/Subtract unit (ASu),

The SPP contains a high-speed serial port for direct interface to an analog-to-digital (A/D) converter. In many
applications, real-time processing of sampled analog
data can be performed within the SPP without tying up
the main microprocessor. Data transfer to the microprocessor occurs upon completion of the SPP processing. The SPP interface environment is summarized in
Figure 3.

5. an accumulator register, and,
6. I/O and control circuits.
The Spp is implemented in a combination of clocked
and static logic which allows complete overlap of the
multiply operation with the read, accumulate, and
write operations. The basic instruction cycle is "Read,
Modify, Write" where the "Read" brings the operands
from the RAM to the multiplier and/or the ASU, the
"Modify" operates on those operands and/or the product of the previous operands, and the "Write" stores
the result of the "Modify." The cycle time for the instruction is 300 nanoseconds. This results in an
arithmetic throughput of about 3.3 multiply and accumulate operations per microsecond. Figure 1 illustrates the SPP Instruction Formats. The OP1 and
OP2 instructions are listed in Tables 2 and 3 and
Figure 2 illustrates the basic instuction timing.

The SPP is intended to be used as a microprocessor
peripheral. The SPP control interface is directly compatible with the 6800 microprocessor bus, but can be
adapted to other 8-bit microprocessors with the addition
of a few MSI packages.
The high-speed number crunching capability of the SPP
gives a standard microprocessor system the necessary
computational speed to implement complex digital
algorithms in real time.

Separate input and ouput registers exchange data with
the SPP data ports. Serial interface logic converts the
parallel 2's complement data to serial2's complement or
sign + magnitude format. Data format and source (serial
or parallel port) is software selectable.
Table 1 summarizes direct commands given to the SPP
from the control processor. These control modes are
specified via four address lines brought to the SPP. The
SPP is a memory-mapped peripheral, occupying 16 locations of the microprocessor memory space. Providing
the proper SPP address will activate the corresponding
control mode.
The control modes and the LIBL command enable realtime modification of the SPP programs. This permits a
single SPP program to be used in several different applications. For example, an SPP might be programmed
as a "universal" digital filter, with cutoff frequency,
filter order, and data source (serial or parallel port)
selected at execution time by the control microprocessor.

2.73

I~

82811

Figure 1. 52811 Object Code Instruction Formats.
116

SPP Instruction Format

10

18' 17

112 111

OP2

OP1

5 Bits

4 Bits

OPERAND

I~

SPP Addressing Modes

17 BITS

Offset Addressing (UV/US)

OP2

OP1

Direct Addressing (D)
Direct Transfer (DT)
Literal (L)

OP2
OP2
OP2

OP1
OP1

3 Bits
01

3 Bits

1 Bit

1 Bit

O2

O=US
1 =UV

0

Address (OH)
Transfer Address (HH)
Data Word (HHH)

1

Effective Address
Addressing Mode

U

VIS

UV

(BAS)+Ol

V = (BAS) +0 2

P= U·V

US

(BAS)+Ol

S=02
OH

P=U·S
P=A·V

0

-

Multiplier Operands

NOTE: 0 indicates an octal digit (3 bits) and H indicates a hexadecimal digit (4 bits)
Table 1. 5PP Control Modes and Operations

Input leads Fo-F3 define several control modes and operations to facilitate the interface between the SPP and a control processor, In
general, these inputs are derived from the control processor address leads, The SPP will therefore occupy 16 memory locations, being a
memory mapped peripheral.

Control Modes and Operations
F-Bus (F3-FO)
Hex Value

Operation/Function

Mnemonic

0

CLR (Clear)

Resets control modes to normal operation.

1

RST (Reset)

Software master reset. Clears all SPP registers and starts execution at location 00.

2

DUH (Data U/H)

Specifies MSByte of data word. DUH terminates data word transfer.

3
4
5

DLH (Data LlH)

Specifies LSBs of data word.

XEQ (Execute)
SRI (Ser. Inp.)

Starts execution at location specified on data lines.
Enables serial input port.

6

SRO (Ser. Out)

Enables serial output port.

7

SMI (S/M Inp.)

Converts sign-magnitude serial input data to 2' s complement form.

8

SMO (S/M Out)

Converts 2' s complement internal data to sign-magnitude serial output.

9

BLK (Block)

Enables block data transfer.

A

XRM (Ext. ROM)

Permits control of SPP using external instruction ROM. A special mode used primarily
for testing.

B

SOP

Set Overflow Protect.

C

COP

D,E,F

Clear Overflow Protect.
Not Used.

2.74

AMII~

82811

Figure 2. SPP Instruction Timing Diagram
1 - - - - - - 300ns -------1:~1
-INSTRUCTION (N -1) .....~-- INSTRUCTION N ------.........~- INSTRUCTION (N + 1) -

1:

TIME SLOT

- - -/

MULTIPLIER OPERATION

T4

I T5 I T6 I T1 I T2 I T3 I T4 I T5 I T6 I T1 I T2 I T3 I

(UN-l. VN-l/S)

I'"

.N

~---~

ACCESS ROM INSTR.
DECODE INSTR.

H

SETUP RAM ADDR.

H

I
.. ...

,-

r--

INCREMENT PC

~

~--+t

ASU OPERATION
ACCUMULATOR OPERATION

1- - -

(N+ 2)

=:\(N+1)

~

~~-~

H

SAMPLE RAM OUTPUT

LATCH MULTIPLIER
INPUT

T4

H
,..(N+1) "I

LATCH MULTIPLIER
OUTPUT

I'"

(N+1)

ACCESS RAM

CONDITIONAL PC CHANGE

I
.. -

(UN. VN/S)

t
t

(UN. VN/S)

t

(UN-2. VN-2/S)

(UN-l. VN-l/S)

(U N- 1• VN- 1/S)

H

H

H

H
,..

H

WRITE INTO RAM

,-

LOAD REGISTERS

H

~I

-I

H
EACH TIME SLOT = 50ns

Figure 3. SPP Interface Environment

2.75

•

AMII~

52811

Figure 3-A. SPP to 6800 Interface

Figure 3-B.

SI
Ao

FO

A,

F, (INPUT ONLY)

A2

F2

A'5
VMA
<1>2

S6800

S2811

F3

A3
A4

:

I

}-

I

L

7T+

j( (INPUT ONLY)

Sci

V

S2811

CCPULL-UP

IRQ

IRQ (OPEN DRAIN)

aiW

IIlW (INPUT ONLY)

m

iiff (INPUT ONLY)
Do
I
I

Do
I
I
I

I

I

SOCK

ANALOG
OUT

SOEN

(BI-IIIRECTlDNAL
TR~STATE INPUT/OUTPUT)

I

07

07

ANALOG
IN

SIEN

Add"" Decode

4K7

I
I
I
I

SICK

Note 1_plaw -linear conversion is performed by the SPP software_
*Note 2_ The input and output clocks and strobe generators may
be realized with two (2) CMOS packages_

Figure 3-C. SPP Serial Port to PCM BUS Interface

SI

INPUT
OAT A BUS

SICK

-

SIEN

-

S2811

•

STROBE *
GENERATOR
LOGIC

,
~

-

80
SOCK

SOEN

..

-

•

STROBE *
GENERATOR
LOGIC

2.76

CLO CK

•

g·LAW
DECODER
WITH FILTER
S3502

,

....Q

~

~.LAW

CODER
WITH FILTER
83501

OUTPUT
DATA BUS
CLOCK

t
---...

ANALOG
OUT

r-<>

ANALOG
IN

AMII~

82811

•

Figure 3-0. SPP Serial Interface Timing
SERIAL INPUT

SICK~JJ~
SIEN~r----'lr---------'JI-----',--_ _ _----,~

(D~rA)

-

-

- _

SIGN
1

I

I

MSB
2

I

3

I

4

LSB

I

1.

SIEN must be synchronized to the lallng edge 01 SICK such that the rise and Ian 01 SIEN follow lallng edge 01 SICK.

2.

Data may contain 1 to 16 bits defined by width 01 SIEN. SPP willert justily data words < 16 bits.

3.

Data are sampled on the trailing edge 01 SICK.

4.

Minimum 16 SICK pulses + 4!,sec. are required between SIEN rising edges.

5.

H serial Input buller is lun, SPP win ignore new input samples.

6.

The serial data is inverted and may be eHher in sign

+

magnHude or two's complement code.

SERIAL OUTPUT

SOEN ~r------------,ff----~ _ _ _ _ _ __
SIGN

MSB

LSB

(D:~A) -=~I.I JL....:l-LI...:2:.....l1....::......l1.......:...4....L~L-_ _.L...:l.::..5....l1_1:..::6...J1

HI·Z

1 . Rise and lall 01 SOEN must lollow lallng edge 01 SOCK.
2. Output data win be 1 to 16 bits defined by width 01 SOEN.
3. Data are valid from rising edge to rising edge 01 SOCK so that the receiving system can sample data on trailing
edge.
4. H the serial output buller is empty, aN ones will be output.
5. SO win be in a high impedance state when not enabled by serial output sequence.
6. The serial data is inverted and maybe e"her in sign

+ magnHude or two's complement code.

Figure 3-E. SPP Parallel Interface Timing

CONTROL MOOE SETUP

Fo·F3

~- ~
___

-:I

iE

!

VAllO CODE

'[

:

I

I

I

1'---_____1

PARAllEL WRITE

Fo·F3

RIW

0

00. ,

IE

~~

PARAllEL REAO

'C~

=~ ~__-y_-+-__

O_UH_O_R_Ol_H_-+_......

Fo·F3

~\""_+-_____-'-:__

==~P~ =J=-=x
I
I

I
I
VAllO

:

I

===~_+-__

~~

OU_H_OR_O_lH_-t_-'Y:

I
I

RIW _ _ _...I

IE

'£____=

i
yr----

I

-----.~

I~---..,...._...Jr

I~_ _ __

\'-___-'1

2.77

00. 0, -

-

-H;; -

OUTPUT -

-

-

-

-

i-v

I

VALID

IV-·-_;_I.z-_-_

-+/L

-..j. - " ' - -_ _ _
I

AMlt.

S2811

Table 2. OP1 Instructions

MNEMONIC

HEX CODE
111-18

OPERATIONS

DESCRIPTION

No Operation

NOP

0

None

No OPeration

Accumulator
Operations

ABS

C

ASS (A)-A

ABSolute value of accumulator is
placed in accumulator.

NEG

D

-(A)-A

NEGate accumulator contents (two's complement) and replace in accumulator.

(A) I 2-A

SHift Right accumulator contents 1-bit position. Equivalent to dividing contents by two.

TYPE

ADDRESS MODES

SHR

Addition

SGV

UV/US, D

(A)-A, if sign (A)=sign VIS
-(A)-A, if sign (A)*sign VIS

SiGn of RAM output V is the sign of accumulator contents. Accumulator contents are
negated (two's complement) if different sign
from V. Useful in implementing hard limiter
function.

AUZ

UV/US

(U)+O-A

Add U and Zero. Loads RAM output U into the
accumulator.

AVZ

UV/US, D

(V/S)+ O-A

Add VIS and Zero. Loads RAM output VIS
into the accumulator.

AVA

UV/US,D

(VIS) + (A)-A

Add VIS and Accumulator contents. Sum is
placed back into accumulator.

AUV

UV/US

(U)+(V/S)-A

Add RAM outputs U and VIS and place sum
in accumulator.

SVA

UV/US,D

(V/S)- (A)-A

Subtract VIS and Accumulator contents. The
difference (V - A) is placed in the
accumulator.

SVU

UVI US

(V/S)-(U)-A

Subtract RAM outputs V and U and place difference (V - U) in the accumulator.

APZ

- - - (current ins!.)
UV IUS, D (prec. instr)

(P)+O-A

Add Product and Zero. Loads multiplier product into the accumulator. The multiplier inputs
were set up in the preceding instruction by
addressing mode.

- - - (current ins!.)
UV IUS, D (prec. instr)

(P)+(A)-A

Add Product and Accumulator contents. Result
is placed in the accumulator. The mutliplier
inputs were set up in the preceding instructions by addressing mode.

APU

UV (current instr)
UV IUS, D (prec. instr)

(P)+ (U)-A

Add Product and RAM output U. Sum is placed
in accumulator. The multiplier inputs were set
up in preceding instruction by addressing mode.

SPA

- - -(current instr)
UV IUS, D (prec. instr)

(P)- (A)-A

Subtract Product and Accumulator contents.
Difference (P-A) is placed in accumulator.
The multiplier inputs were set up in preceding
instruction by addressing mode.

SPU

UV IUS (current instr)
UV IUS, D (prec. instr)

(P)- (U)-A

Subtract Product and RAM output U. Difference
(P - U) is placed in accumulator. The
multiplier inputs were set up in preceding instruction by addressing mode.

Operations

Subtraction

Multiplyl
Add Operations

APA

Multiplyl
Subtract
Operations

A

2.78

AMII~

82811

Table 3. SPP Instruction Set
OP2 Instructions

TYPE

MNEMONIC

HEX COOE
116-112

OPERATIONS

DESCRIPTION

None

NO OPeration

HHH-IR

Load LiTeral in Input register. A 12-bit (3 hex
digits) literal is transferred to the input
register. This instruction cannot be used with
an OP1 instruction or with a specified addressing mode. Literal is left justified to occupy bits 4-15 in register.

07

(IR)-BAS
(IR)-LC

02

(A)-OR

Load Input register contents to Base register
and Loop counter. Bits 11-15 are loaded to
the base register, while bits 4-8 are loaded to
preset the loop counter. Clears input flag
(LOW).

No Operation

NOOP

00

Load
Instructions

LLTI

1E

L1BL

LA CO

ADDRESS MODES

Literal

Load ACcumulator contents into the Output
Register. This is the basic data output instruction. Sets output flag (HIGH).

Data Transfer
Instructions

Accumulator
Operations
Register
Man ipu lation
Instruction

Unconditional
Branch
Instruction

LAXV

05

UV/US, 0

(A)-IX, VIS
(A)-A

LALV

04

UV/US, 0

(A)-LC, VIS

LABV

03

UV/US, 0

(A)-BAS, VIS
(A)-A

Load Accumulator to Base and RAM location
VIS. Truncate accumulator contents to most
significant 5 bits alter the operation.

TACU

OB

UV/US

(A)-U

Transfer Accumulator Contents into RAM
location U.

TACV

OC

UV/US, 0

(A)-VIS

Transfer Accumulator Contents into RAM
location VIS.

TIRV

08

UV/US, 0

(IR)-V/S

Transfer Input Register Contents to RAM
location VIS. This is the basic data input
instruction. Clears input flag (LOW).

TVPV

09

UV/US, 0

VP-V/S

Transfer contents of VP register (equals
previous value of output V) to RAM location
VIS.

TAUI

10

UV/US

(A)-U

Transfer Accumulator contents into RAM location U using Index register as base.

CLAC

01

O-A

CLear the ACcumulator. Forces SWAP mode to
normal operation and clears overflow flag.
INcrement the IndeX register.

Load Accumulator contents into IndeX register
and RAM location VIS. Accumulator is truncated to 5 most significant bits after the
operation.
Load Accumulator to Loop counter and RAM
location VIS.

INIX

00

(IX)+1-IX

DECB

DE

(BAS) -1-BAS

DECrement the Base register.

INCB

OF

(BAS) + 1-BAS

INCrement the Base register.

SWAP

06

BAS-IX

SWAP the roles of Base and Index registers.

JMUD

15

OT

HH-PC

JuMp Unconditionally Direct to location
indicated by 8-bit (two hex digits) literal HH.
Cannot be used with an OP1 instruction requiring specific addr. mode.

JMUI

11

UV/US

[(IX)]-PC

JuMp Unconditionally Indirect to location indicated by contents of RAM address pointed
to by index and displacement indicated by
VIS. [(V/S)0-7]-PC,

2.79

•

~II.

52811

Table 3. SPP Instruction Set (Continued)
OP2 Instructions
HEX CODE
TYPE
Conditional
Branch
Instruction s

Subroutine
Instruction

Complex
Instructions

116-112

ADDRESS MODES

OPERATIONS

DESCRIPTION

JMCD

16

DT

HH-PC, if LC*O
(LC) -1-LC

JuMp Conditionally Direct to location indicated
by 8-bit (two hex digits) literal HH, if loop
counter is not zero. Loop Counter is
decremented after the test.

JMPZ

19

DT

HH-PC if (A)=O

JuMP to locatioh specified if accumulator contents are Zero as result of previous instruction.

JMPN

1A

DT

HH-PC if (A) 0
E~
::>
u .....
Q)
u c..
«0

en
c::

c::
0

0:;::::;

:-e
"0

~

Q)

"0 c..
«0

.gg
U._

n:l-

.!=~

.c

Q)

.g

"0
"0

en
.......

«en
'..... c::

en
c::

>,0

>, 0

0...

~~
~
::>c..en

g-~

::>c.. "3~
eno :Eo

:Eo

cr:
UJ

::::i

OP1-..
OP2.
No Operation Instruction

NOOP

Load Instructions

LLTI

0...
i=
«
0... en c.!Jcr: > N N«
«::::l «::::l....J
S> ::::IN
o co UJ :c c.!J
::::l »
>0... 0... 0... o...o...::::l
Z« zen en « «« « en en« « « cnen:E

X X X X X X X X X X X X X X X X X

LlBL
LACO
LAXV
LALV
LABV
Data Transfer Instructions

TACU
TACV
TIRV
TVPV
TVIB
TAUI

Accumulator Instructions
Register Manipulation Instructions

CLAC

1 1 1 1 1 1

1

1 1

X X

See note 2

INIX
DECB
INCB
SWAP

Unconditional Branch Instructions

Conditional Branch Instructions

Subroutine Instructions

JMUD

X X X X X X X

X

JMUI

1 1 1 1 1 1 1

1

1 1

JMCD

X X X X X X X

X

X X

JMPZ

X X X X X X X

X

X X

JMPN

X X X X X X X

X

X X

JMPO

X X X X X X X

X

X X

JMIF

X X X X X X X

X

X X

JMOF

X X X X X X X

X

X X

JMSR

X X X X X X X

X

X X

JCDT

X X X X X X X

X

X X

JCDI

X X X X X X X

X

X X

RETN
Complex Instructions

MODE
REPT

2.82

See note 3

4

AMII~

82811

Circuit Description

loop counter can be loaded from the Input Register as
well as the Accumulator.

Instruction ROM - The SPP program is stored in a
256x17 bit ROM. The 17-bit wide instruction word (See
Figure 1) facilitates multiple operations per instruction.
Addresses 250-255 are reserved for chip testing.

Index Register - The index register is 5 bits wide and
is used to access lookup tables. This register can be incremented by a software command. Lookup table instructions cause the index contents to be used as the
data memory base. Table contents may be used either
as data or as jump addresses for computed GO-TO operations. Special instructions allow the base and the index
register to work together, providing a dual base addressing scheme. The index is also used to step through
the data memory during block transfer operations.

Data Memory - The 256x16 bit data memory is
organized to provide two operands (V, V) in a single
fetch cycle. The 256 data words are structured in a
32-'base' by 8-'displacement' word matrix. Memory is
further partitioned such that each base group contains 4
words of RAM (displacements 0 through 3) and 4 words
of ROM (displacements 4 through 7). Only the base information is fed to the RAM/ROM core. All eight displacement words associated with that base are accessed in ASU - The heart of the SPP is a 16-bit adder/subtractor
parallel. Two independent displacement multiplexers unit (ASU). The ASU operates with two's complement
select the two operands (U, V) from the eight output arithmetic, and is provided with zero, negative and
words. Within an 8-word base, therefore, the memory overflow detect circuits. The basic adder cell includes
look-ahead carry logic to improve speed. The ASU will
appears to have three ports.
deliver a 16-bit sum in 40 nanoseconds. An accumulator
Scratchpad Memory - An 8-word scratchpad memory latch follows the ASU. A shifter is available to shift the
(all RAM) is provided so that common data may be ac- accumulator contents 1 bit to the right, providing a
cessed with the full efficiency of data contained within precision divide-by-two.
an 8-word base. An additional multiplexer on the "V"
memory port accesses the scratchpad data instead of Multiplier - The SPP incorporates a parallel modified
data from the main memory core. Since this is indepen- Booth's algorithm multiplier. The multiplier inputs are
dent of the base group, the scratch pad contents may be truncated to 12 bits and the multiplier output is rounded
considered as a "floating" base group. This feature to 16 bits. These truncations produce a product with a
doubles the efficiency of equalizer tap update and resolution of > 15 bits. The 16 MSBs of the product are
similar programs.
retained. This implies that all numbers in the SPP are
represented as fractions less than one in magnitude.
VP Register - The VP register provides a one-instruc- The imaginary binary point is to the left of the MSB.
tion delay of data accessed from the memory "V" port. This fractional representation and the fixed-point
The memory read cycle precedes the write cycle (see Fig- arithmetic requires proper scaling of equations to
ure 2). The VP register consists of two portions. Data realize the full accuracy of the SPP. A benefit of fracfrom the n-th read cycle first enters the master portion. tional representation of numbers is that the multiplier
During the next cycle, data from instruction n + 1 cannot overflow. The propogation delay through the
enters the master portion while the instruction n data multiplier is 300 nanoseconds. A 300-nanosecond SPP inshifts to the slave portion. The data in the slave portion struction cycle is achieved by pipelining the multiplier.
may be returned to the memory during the instruction Data entered into the multiplier during instruction n
n + 1 write cycle by use of the commands TVPV or will result in a product available during instruction
TVIB. thus digital filter z-l delays are implemented n + 1. (See Figure 2.) The one instruction delay removes
with minimal software overhead.
the multiplier propogation delay from the overall inRAR - A return address register allows one level of struction cycle.
subroutine nesting. This facilitates repeated use of
universal subroutines such as a second order digital Multiplication is automatically set up by the address
filter routine, SIN/COS routine, etc., thus minimizing mode (see Figure 1). The multiplier is always active.
Products are utilized by specifying one of the multiplier
the program size.
OP1 operators (APZ, AP A, APU, SPA, SPU). The
multiplier latches are updated wherever the instruction
Loop Counter - A loop counter is provided to handle operand is a D or UV/S address. They are not updated if
iteration loops up to 32 iterations. Special jump instruc- the operand is a Literal or DT, and the product of the
tions conditional on this loop counter to be zero, provide previous set-up is retained until one of the multiplier
the iteration test without adding program steps. The OP1 operators is used to read it out.
2.83

•

AMII~

52811

Programming Examples

In this section two programming examples are provided
to illustrate the use of some of the instructions and the
power of the instruction set. The first example is that of
a second order digital filter section. This can be implemented as a subroutine in the SPP such that the main
program can access it repeatedly to implement higher
order filter sections. The second example is that of a
SIN COS subroutine that computes the values of sin w
and cos w using an approximation formula. This routine
was chosen as it illustrates the use of some of the complex instructions and because it is useful in applications
that require carrier generation.

1. A Second Order IIR Digital Filter Section: Figure 5
shows a block diagram, filter equations and the computational process involved in the implementation of
this filter. It is clear that storage must be provided for
the fixed coefficients aI' a2, b1 and b2 and previous two
intermediate results W n-l and W n-2' Figure 7 illustrates
the memory configuration at the beginning of the
subroutine. Fixed coefficients are conveniently stored
in the ROM portion of the data memory in displacements 4 through 7 while displacements 0 and 1 are used

for storage of past values. It is assumed that the present
input sample Xn is loaded in the accumulator by the
main program prior to accessing the subroutine. At the
end of the subroutine output Yn is left in the accumulator while Wn -1 and Wn -2 are replaced by Wnand
Wn -1 so that the next input sample Xn + 1 can be processed.
Note that only one base value is used by the filter for
the storage and main program must load this value in
the base register prior to execution.
Figure 6 illustrates the instruction sequence of the subroutine. Only five instructions are needed to completely
process the section. This corresponds to a processing
time of 1.5 microseconds. Figure 7 illustrates how the
memory map gets modified during the execution. A
higher order filter is implemented by cascading of the
second order sections. The main program can increment
the base register and decrement the loop counter after
each iteration until the required number of iterations of
this subroutine take place. Since the accumulator holds
the output of the filter after each iteration, no storage is
required in memory. Figure 8 illustrates the program
and memory allotment for implementation of a sixth
order filter.

Figure 5. Digital Filter Example

B. Computation Process

A. Second Order Recursive II R Digital Filter Section

Input Samples X(n) - - .• X(n-2). X(n-l). Xn•···

w.

I------y,

,

Intermediate
Results W(n)···. W(n·2). W(n.l). Wn••••

Output Samples Y(n) .••• Y(n.2). Y(n.l).

@ ...

Sampling Instants· ..•.• ~n.2). ~n.l). tn.····

C. Digital Filter Equations

2.84

S2811

Figure 6. Digital Filter Subroutine

LINE #

LABEL

OP1

OP2

OPERAND

COMMENTS

0

DFIL

NOP

NOOP

UV(4,0)

1

APA

NOOP

UV(5,1)

2

APA

TACV

UV(6,0)

a1, Wn-1- MULT. ACe = Xn
a2, Wn-2- MULT. Xn + a1 Wn-1-ACC
b1, Wn-1-MULT.
Wn = Xn + a1 Wn-1 + a2 Wn-2-ACC
ACC-V(O) (replace Wn-1)
Wn-1-(VP)

3

APA

TVPV

UV(7,1)

4

APA

RETN

b2, Wn-2-MULT. Wn+ b1 Wn-1-ACC
Wn-1- V(1) (replaces Wn-2)

-

Yn= Wn+ b1 Wn-1+ b2 Wn-2 -ACC
Return to main program

Figure 7. Memory Maps for the Digital Filter
DISPL

•
0

1

BASE

=N

,----

Wn

Wn

Wn-2

Wn-1

Wn-1

-

-

-

-

-

-

Wn

Wn·1

r--Wn·2
I---

2
3

r---

4

I--a1
I---

5

-

-

a1

a1

a1

a2

a2

b1

b1

b1

b2

b2

b2

End of line 3

Final

a2

a2

-

r--6

b1
I---

7

b2
~

End of line

Initial

2

Figure 8-A. Main Program Instructions for a Sixth Order Filter

LABEL

LOOP

OPERAND COMMENTS

OP1

OP2

NOP

•
•
•
LLTI

002

(IR) = 002

NOP

LlBL

-

0-BAS,2-LC
Initialize base register and loop counter

-

JMSR

DFIL

Jump to DFIL subroutine

JCDI

LOOP

Increment base, Test if LC = 0

•
•
•

If non zero go to LOOP
Decrement LC after test
Output of the filter is in accumulator at
the end of iterations.

2.85

•

AMII~

82811

o

Base~

2

DISPl

t

a

WO(n-l)

W l (n-l)

W2(n-l)

WO(n-2)

W l (n-2)

W2(n-2)

II coefficients I < 21
NOOP UV(4,O)
NOOP UV(5,l) as above

Modified Subroutine

Figure 8-B. Memory Map for the Sixth Order Filter

o

NOP

1

APA

2

APA

3

APA

TACV UV(6,O)
TVPV UV(7,1)

4

APA

TACV US(-,O)
UV(O,O)

2

-

5

AUV

TACV

3

-

6

AVZ

RETN US(-,O)

4

aOl

all

a2l

5

a02

a12

a22

6

bOl

b l1

b21

7

b 02

b12

b22

Yn = Wn + b 1 W n -1 +
b2 Wn-2- ACC-S(O)
U(O) + V(O)-ACC-V(O)
= 2W n _ 1
S(O)- ACC = Y n

2. SINCOS: SIN COS is a subroutine that provides the
sin w values for values of w satisfying the condition
- 1I"$W< 11". Since all numbers in the SPP are represented
as fractions less than 1 it is first necessary

to scale by a factor

11"

such that - 1:$ ~ < 1. The value
11"

Wi =

~ is assumed to be in the accumulator at the
11"

beginning of the subroutine. In a practical application
the control processor can enter Wi into the SPP before
the
computation begins. If the control processor does
In order to be able to implement a digital filter with
coefficients in the range of - 2 to + 2 it is necessary to not have scaled values of w available, an alternative
scale the coefficients by a factor of 2 to bring them into method can be used. In this method the control prothe permissible range of -1 and + 1. However, in order cessor can enter ~ into the SPP. ~ can be easily obtained
4
4
to restore the "loop gain" of the recursive section of the
filter it is necessary to correct for this in the signal flow by a 2-bit ,right shift operation. The SPP can then connetwork. The easiest way to do this is to double the vert ~ to ~ by first multiplying ~ by
and then
signal level at the point A in Figure 5. The modified se4
11"
4
11"
cond order filter subroutine is shown below, together adding the result to itself. In any event it is assumed
with the basic subroutine. Note that in the modified
that Wi = ~ is available in the accumulator when the
subroutine all the coefficients must be halved.
Implementation of Second Order Digital Filter with
Coefficients > 1 in the S2811

!

11"

Basic Subroutine

o

II coefficients I < 11

subroutine is accessed. When the control is returned to
the main program sin w is available in s(O) and cos w is
available is s(l) while Wi remains in the accumulator as
well as s(2). The subroutine computes the sin wand cos w
values by use of the following approximation:

NOOP UV(4,O) aI, Wn_1-MULT.
ACC=X n
1 AP A NOOP UV(5,1) a2, W n_2-MULT.
Xn + al Wn-l-ACC
2 APA TACV UV(6,O) b v Wn_1-MULT
Wn = Xn + al W n-1 + a2
W n-2- ACC
ACC- V(O) (replace Wn-1 )
Wn-1-(VP)

3

NOP

For small values of Aw:
sin Aw=:Aw
cos Aw=:l
sinw = sin (~+ Aw) = sin~ cosAw + cos~ sinAw

TVPV UV(7,1) b2, Wn_2-MULT.
W n + bl W n-l - ACC
Wn-l - V(1) (replaces Wn-2)

4 APA RETN

Yn = W n + b 1 W n-l + b 2
W n_2- ACC
Return to main program

=: sin~ + Aw cos~
COsw = cos (~+ Aw) = cos~ cosAw - sin~ sinAw
=: cos~ - Aw sin~
w represents the nearest quantized value to w. In the
subroutine the quantized value is obtained by trun-

cating
2.86

21 Wi I = (!
11"

Iwi). The truncation results in five

MlII~

82811

most significant bits including t~e sign bit. Since absolute value is truncated, sign bit is zero. The four
most significant magnitude bits provide sixteen quantized angles 21 ~I I = wq. Wq is loaded in the index
register . Use of SWAP command allows the index
register to access the appropriate block of data
memory corresponding to wq. Sin ~ and cos ~ values
corresponding to wqare stored in displacements 4 and 5
(ROM portion) of the appropriate block addressed by
wq. Figure 10-A illustrates the organization of the
lookup table.

signs are assigned by use of the SGV instruction at the
end of the subroutine. The quantized angle Wq is computed by truncation of the number 21 w' I. The truncated value (five most significant bits including sign
bit) are loaded in the index register by the LAXV instruction and allows direct access of the sin ~ and cos ~
values from the appropriate block. ~W is computed
simply as a difference between the input and the quantized angle. The sin wand cos W values are stored in s(O)
and s(l) respectively while the angle w' is retained in
the accumulator as well as s(2) when the program exits.

Figure 9 shows a detailed sequence of instructions for
the SINCOS routine. The routine is nineteen instructions long and takes 5.7 microseconds to execute. As
seen from Figure 9, the first objective of the program
is to transform the input angle to the first quadrant.
This transformation process is graphically illustrated
in Figure 10-B. The input angle w' is stored in s(O) and a
number (112-1 w'l] is stored in s(1). The signs of these
numbers are used to assign the sign to the magnitudes
of sin wand cos W computed by the approximation formulae. Table 10-C illustrates how the sign of sin W can
be taken from the sign of the angle w' and sign of cos W
can be taken from the sign ofthe number (112 -I w'I]. The

The SINCOS subroutine ilustrates the following operations:
- Scaling
- Table Lookup
- Use of SWAP command
- Use of SCRATCHPAD
- All Data Addressing Modes
- Use of SG V command
- Use of TVPV command
- Truncation of the accumulator using LAXV
command.

2.87

•
_

~

AMII.

52811

Figure 9. SINCOS Subroutine

SINCOS Routine
LINE #

0

2

LABEL

OP1

OP2

OPERAND

SINCOS

NOP

TACV

UA(-,O)

ABS

SWAP

SVA

NOOP

0(112)

COMMENTS

w' = ~- s(O), ACC
7r
I w' I-ACC, SWAP roles of base and index
1f2"lw'I-ACC, 0(Y2) refers to the address of
location containing the constant 112

3

NOP

TACV

US(-,1 )

1I2-lw'l-s(1), ACC

4

AVA

NOOP

US(-,1 )

s(1)+ACC-ACC= (1-2Iw'l)

5

ABS

NOOP

6

SVA

NOOP

D(1)

7

NOP

LAXV

US(-,2)

1(1-21 w' I) I-ACC
2Iw'I-ACC
21 w' l-s(2). w' -ACC, IX.
corresponding to w

w' = quantized value

8

SVA

TACV

US(-,2)

21 w' 1- w' = 2Aw' -ACC, s(2)

9

AVA

NOOP

US(-,2)

s(2) + ACC= -ACC (4Aw')

10

NOP

NOOP

D(7r/4)

~, 4Aw'-MULT.

11

APZ

TACV

US(-,2)

12

NOP

NOOP

US(4,2)

sinw, Aw- MULT. Index register contents w' point to
sinw in displacement 4 of the appropriate block.

13

SPU

TACV

US(5,2)

Awsinw - cosw = - cosw-ACC, s(2).
Aw, cosw-MULT.

14

APU

SWAP

US(4,2)

sinw+ Awcosw= sinw-'+ACC. Transfer control back
to base register.

15

SGV

TACV

US(-,O)

Assign the sign of w' to (sinw) and store result in
s(O). sinw-s(O), w' -(VP)

16

AVZ

TVPV

US(-,2)

- cosw-ACC. (VP) = w' - s(2). Refer to the
description of the VP register for explanation of TVPV
instruction.

17

SGV

TACV

US(-,1 )

Assign the sign of [1j2-1 w' I] to COSw and store result
in s(1). cosw-s(1)

18

AVZ

RETN

US(-,2)

w' = ~ -ACC. Return to main program.
7r

2.88

4
7rAw'-ACC, s(2) (7rAw'=Aw)

82811

•

Figure 10-A. Organization of the Lookup Table for SINCOS Routine
DISPLACEMENT

•

DATA MEMORY

0

-

1

2
3
4

sin(O)

5

cosIO)

ROM

----.

157r
sin 32

sin(-2-'U)q)
- sin~
COS(-i~wq)
- COSu.'

cos

151T

32

6

7
BASE
IX (1 tiU)q) } -

a

-".-

1

15

16wq

-2IA/I-2(1~1)
WqW
7r

16

I

I

31

15
16

1
16

= 7r2

lA,
W
I

. (1T"2 Wq) =SIn. (1T"2. 7r
2 1W I) == Slnw
.
A

Sin

A

Figure 10-B. Graphical Angle Transformation Process
11"

2"

o

o

+71"

--~------~~----~-

21w /

Wl=~

w

11"

QUANDRANTS

Figure 10-C. Table for Computing Sign ofsinw, cosw

Range of

w

0-1r12

2
1r/2-{

Range of

WI

0-V2

3

4

V2-1

-1r- -1r/2
-1--V2

-1r/2-0

V2-0

0--V2

-1/2-0

0-1/2

+
+
+
+

+
+
-

-

-

-

-

-

+
+

1

Range of [V2-1 WI I]
Sign of

WI

Sign of sinw
Sign of [1/2-1 WI I]
Sign of cos

l

w

2.89

-

-V2-0

ADVANCED PRODUCT DESCRIPTION

S2814
FAST FOURIER TRANSFORMER

Features

General Description

o

The AMI 82814 Fast Fourier Transformer calculates
FFTs using a decimation in frequency technique for
minimum distortion. The 82814 calculates a basic
32-point FFT using internal coefficients. A coefficient
rotation algorithm is provided so that larger FFT's may
be implemented (in blocks of 32-points). The 82814 includes optional conditional array scaling for maximum
range.

o

o
o

o
o
o
o

Performs 32 Complex or 64 Real Point Forward or Inverse FFT in 1.5msec Using Decimation in Frequency
Transform Expandable Either by Using Multiple S2814s for Minimum Processing Time or a
Single S2814 for Minimum Hardware
Operates with S6800 Microprocessor and 6844
DMA Controller, or S9900 Microprocessor and
AM2940 DMA Controller for Higher Speed
Block Data Transfer and 1/0 Carried Out on
Microprocessor Data Bus
Optional Conditional Array Scaling Gives
Over 70dB Dynamic Range With 57dB resolution on Transforms Up to 2048 Points.
Optional Windowing Algorithm Permits Use of
Arbitrary Weighting
Coefficient Generation On Chip, With Rotation
Algorithm for Transform Expansion
Uses AMI's VMOS Technology to Achieve
High Speed and Low Power Dissipation

The 82814 is intended for use in a microprocessor
system (see Figure 1) including a microprocessor, ROM,
RAM and a DMA controller. The microprocessor controls the flow of signal processing by selectively calling
routines in the 82814. Data points are stored in RAM,
and are block transferred into and out of the 82814 using the DMA controller. Windowing weights and setup
data are loaded into the 82814 prior to processing. A
6800-compatible source listing of a suitable control program, complete with description, will be available to the
82814 user at no charge. This control program will also
be available as a pre-programmed ROM.

Block Diagram

Pin Configuration

NOT USEO

NOT USEO

N. C.
NOT USEO
NOT USED
NOT USED
NOT USED
OSCI
OSC o

DATA
BUS

::1

F2

F3
RST

IE
DATA BUS

ADORESS BUS

4 BYTES PER
TRANSFORM POINT

PACKAGE 28 PIN D.I.l.

2.90

CONTROL
BUS

82814

Absolute Maximum Ratings:

Supply Voltage ........................................................................... +7V D.C.
Operating Temperature Range .......................................................... O°C to +70°C
Storage Temperature Range. . . . . . . . . . . . . . . .. . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -55°C to + 125°C
Voltage on any Pin .......................................................... Vss -O.3V to Vee +0.3V
Lead Temperature (Soldering, 10sec) ............................................................ 200°C
Abbreviated Electrical Specifications

Vee=5.0V +5%. Vss=OV. TA =O°C to +70°C
All Inputs and Outputs .............................................................. TTL Compatible
Clock Frequency ................................................................ 20MHz Guaranteed
Power Dissipation ........................................................ 0.5W (Typical) - lW (Max.)
FFT Performance Data

Execution Time msec
Using Single
Using N
S2814
S2814s

# Of Points (Complex) # Of 32 Point Transforms

(=N)
32

1

1.5

-

64

2
4

3.35

2.25

8.2

2.25

128
256

8

19.4

2.62

512

16

44.8

3.0

1024

32

101.6

3.35

2048

64

225.2

3.5

Note: Executions assume 2Mbyte/sec DMA transfer rate.

2.91

._-

•

ADVANCED PRODUCT DESCRIPTION

S3525A/S3525B

DTMF BANDSPLIT FILTER

Features

General Description

o

CMOS Technology for Wide Operating Single
Supply Voltage Range (10.0V to 13.5V). Dual
Supplies (±5.0V to ±6.75V) Can Also Be Used.

o

Uses Standard 3.5SMHz Crystal as Time Base.

o

Ground Reference Internally Derived and
Brought Out.

o

Programmable Gain Input Amplifier Stage

o

Limiter and Filter Outputs Separately
Available

The S3525 DTMF Bandsplit Filter is a IS-pin monolithic CMOS integrated circuit designed to implement a
high quality DTMF tone receiver system in conjunction with a suitable receiver circuit. The device includes a dial tone filter, high group and low group
separation filters and limiters for squaring of the filtered signals. An uncommitted input amplifier allows
a programmable gain stage. An overall signal gain of
6dB is provided for the low group and high group
signals in the circuit. The dial tone filter is designed to
provide a rejection of at least 52dB in the frequency
band of 300Hz to 500 Hz. The only difference between
the S3525A and the S3525B is the frequency of output
clock signal at the CKOUT pin. In the S3525B, it is a
894.89kHz square wave while in the S3525A, it is a
3.58MHz buffered oscillator signal. The S3525A can
be used with digital DTMF receiver chips that need
the TV crystal time base allowing use of only one
crystal between the filter and receiver chips.

Block Diagram

Pin Configuration

VDD
VREF
BVREF

CKOUT (3.58MHzJ895kHz) (AlB)
OSCo
OSC,

Vss

FHOUT

LOII-

FLOUT

LOIN+

FEEOBACK

IN-

aVREF
VDD

vREF
Vss

2.92

FLsa

IN'

FHSQ

IN-

HIIII+

1U1II-

S3525A1S3525B

Absolute Maximum Ratings:
DC Supply Voltage (VDD - Vss) ................................................................ +15.0V
Operating Temperature ..................................... ;........................... O°C to +70°C
Storage Temperature ............................................................... -55°C to +125°C
Analog Input ...................................................... 1/4(VDD - Vss) <;VIN <;3/4(VDD . Vss )
Operating Supply Voltage (VDD - Vss) ................................................ + 1O.0V to + 13.5V

Electrical Operating Characteristics: TA = 25°C
Parameter/Conditions

Min.

Typ.

Max.

Units

VDD

Positive Supply (Ref to Vss)

10.0

12.0

13.5

V

VOL(CKOUT)

Logic Output "Low" Voltage

VO H

Logic Output"High" Voltage

Symbol

IOH=4~A

RINA (IN-,IN+)

Analog Input Resistance

CINA(lNA-,IN+)

Analog Input Capacitance

VREF

Reference Voltage Out

VoR=\BVREF-VREF\

Offset Reference Voltage

PD

Power Dissipation
VDD =12.5V

Vss+O.4

Vss

IOL=160~A

VDD-1.0

V

10

MQ
15

0.49
0.50
0.51
(VDD-VSS) (VDD-VSS) (VDD-VSS)
50
400

VDD = 13.5V and O°C

pF
V
mV
mW

650

mW

Typical Op Amp Characteristics (On Chip)

GBW

Unity Gain Bandwidth

f3dB

3dB Point (wrt

Ao

DC Open Loop Gain

1.2

1.8

MHz

70

Hz

80

86

dB

Ao)

~

Phase Margin

60

65

deg

CMRR

Common Mode Rejection

60

70

dB

Vos

Offset Voltage

10

WN

Wideband Noise Over 3MHz

Po

Power Dissipation (VDD - Vss) = lOV

2.93

25

mV

25

50

~Vrms

5

7.5

mW

I

AMlt.

S3525A/S3525B

System Specifications

Symbol

Parameter/Conditions

Min.

Typ.

Max.

Units

Total Harmonic Distortion
THD

Total Harmonic Distortion (dB). Dual tone of 770Hz and
1336 Hz sinewave applied at the input of the filter at a level
of 3dBm each. Distortion measured at the output of each
filter over the band of 300 Hz to 10kHz (VDD = 12V)

40

dB

Idle Channel Noise
ICN

Idle Channel Noise measured at the output of each filter
with C-message weighting with input of the filter terminated to BVREF

1

mVrms

Group Delay
GDL

Low Group Filter Delay over the band of 50Hz to 3kHz

4.5

6.0

ms

GDH

High Group Filter Delay over the band of 50Hz to 3kHz

4.5

6.0

ms

Pin/Function Descriptions

OSCj,OSCo

These pins are for connection of a standard 3.579545MHz crystal and lOmQ resistor to
form the oscillator from which all timing is derived. Necessary parasitic capacitances are
built on-chip thus eliminating the need for external capacitors.

CKOUT (S3525A)

Oscillator output is buffered and brought out at this pin. This output can be used to drive
the oscillator input of a receiver chip that uses the TV crystal as time base. This allows use
of only one crystal between the filter and receiver chips.

CKOUT (S3525B)

This is a divide by 4 output from the oscillator and is provided to supply a clock to receiver
chips that use 895kHz as time base.

IN-, IN+, Feedback

These three pins provide access to the input operational amplifier on chip. The feedback pin
in conjunction with the IN - and IN + pins allow a programmable gain stage. (See Note.)

FH OUT, FL OUT

These are outputs from the high group and low group filters. These can be used as inputs to
analog receiver circuits.

HI IN-, HI IN+
LO IN-, LO IN+

These are inputs of the high group and low group limiters. These are used for squaring of
the respective filter outputs.

FHSQ,
FLSQ

These are respectively the high group and low group square wave outputs from the
limiters. These are connected to the respective inputs of digital receiver circuits.
These are the power supply voltage pins. The device can operate over a range of 10V..;
(VDD-VSS ) ..; 13.5V.
An internal ground reference is derived from the VDD and Vss supply pins and brought
out to this pin. Typically VREF is 1I2(VDD - Vss) above Vss.
Buffered VREF is brought out to this pin

Note: Because the overall signal gain is approximately 6dB, in order to maintain performance, the MAXIMUM signal voltage developed at
"feedback" (pin 13) should be 3/8 (VDD- Vss ) ..; VIN ..; 5/8 (VDD- VssJ·

2.94

S3525A1S3525B

I

Figure 1. DTMF Bandsplit Filter Loss/Delay Characteristics

10

20

30

40

50

~

60

'"'"

70
5.0
80

4.5
4.0

90

3.5

100

2.~

3.0

I

110

2.0
1.5
1.0

120

0.5
0.5

~ .0

1.5

FREQUENC"( ik~zi

2.95

2.5

3.0

!
"'"
"-

'"

'"'"'"

Consumer Products

I

Consumer Products Selection Guide

REMOTE CONTROL CIRCUITS
Part No.

Description

Process

Power Supplies

110 Bits

Packages

S2600

Remote Control Transmitter

CMOS

+7Vto+10V

11

16 Pin

S2601

Remote Control Receiver

P·I2

+lOV to+18V

5

S2742

Remote Control Decooer

PMOS

'f91l

18 Pin

S2743

Remote Control Encoder

PMOS

+9V

16 Pin

Part No.

Description

Process

Power Supplies

InputlOutput

Packages

S9260161

Seven· Switch Interface

P-I2

-13.5V to - 18V

CMOSITTL

22 Pin

S9263164165

Sixteen-Switch Interface

PI2

-13.5V to -18V

CMOSIMOSITTL

40 Pin

S9262

Fourteen-Switch Interface

PI2

-13.5V to - 18V

MOSITTL

22 Pin

S9266

Thirty-Two-Switch Interface

P-I2

- 13.5V to -18V

MOSITTL

40 Pin

TCK-100

Touch Control Evaluation Kit

22 Pin

TOUCHCONTROL™ INTERFACE CIRCUITS

CONSUMER CIRCUITS
Part No.

Description

Process

Power Supplies

Digits

Packages

S1856

Digital Clock Circuit LEDILCD Fluorescent Auto Clock

P-I2

-6V to-22V

3V2

40 Pin

S2709

Fluorescent Automotive Digital Clock

P-I2

+12V

4

22 Pin

Process

Power Supplies

Outputs

Packages

P-J2

+8V to+22V

32

40 Pin

Power Dissipation

Packages

Part No.

Description

S2809

Universal Display Driver

Part No.

Description

Process

Power Supplies

S10110

Analog Shift Register

P-I2

-24V

S10111

Analog Shift Register

P-J2

-24V

S10129

Six-Stage Frequency Divider

P-I2

-14V to-27V

350mW

14 Pin

S10130

Six-Stage Frequency Divider

P-I2

-14V to-27V

350mW

14 Pin

S10131

Six-Stage Frequency Divider

P-J2

-14V to-27V

350mW

14 Pin

S10377

Analog Shift Register

P-I2 MOS

-14V to-27V

350mW

8 Pin

S10430

Divider-Keyer

P-I2 MOS

-14V to-27V

350mW

40 Pin
14 Pin

ORGAN CIRCUITS
8 Pin
8 Pin

S2567

Rhythm Counter

HIV T

-15V to-27V

400mW

S2688

Noise Generator

P-I2

-14V to-27V

350mW

8 Pin

S8890

Rhythm Generator

P·I2

-12V

400mW

40 Pin

S9660

Rhythm Generator

P-I2

-12V

400mW

28 Pin

S50240

Top Octave Synthesizer

P-I2

-l1V to-16V

360mW

16 Pin

S50241

Top Octave Synthesizer

P-I2

-l1V to-16V

360mW

16 Pin

S50242

Top Octave Synthesizer

P-I2

-l1V to-16V

360mW

16 Pin

S50243

Top Octave Synthesizer

P-J2

-l1V to-16V

360mW

16 Pin

S50244

Top Octave Synthesizer

P-I2

-l1V to-16V

360mW

16 Pin

S50245

Top Octave Synthesizer

P-I2

-l1V to-16V

360mW

16 Pin

3.2

82600/82601
ENCODER/DECODER
REMOTE-CONTROL 2-CHIP 8ET

I

Features

o
o
o
o

o

o
o
o
o
o

Small Parts Count - No Crystals Required
Easily Used in LED, Ultrasonic, RF, or Hardwire Transmission Schemes
Very Low Reception Error
Low Power Drain CMOS Transmitter for
Portable and Battery Operation
31 Commands - 5-bit Output Bus with Data
Valid

3 Analog (LP Filterable PWM) Outputs
Muting (Analog Output Kill/Restore)
Indexing Output - 21h Hz Pulse Train
Toggle Output (On/Off)
Mask-Programmable Codes

Block Diagram
S2600 Encoder

Pin Configuration
S2600

GNO

~

Vss

OSCTEST
(16)

~~~~UT

;1
l
,

E

G

kEY
BOARD

I

J

Pin Configuration
S2601

+v=vss
'OR

.eY
BOARD

!':
~

C

~N!lFF
3
5

!BINARY

~ OUTPUTS

: J
SIGNAL INPUT

VOO=GNO

3.3

AMII~

82600/82601

Functional Description
The 82600/82601 is a set of two L8I circuits which
allows a complete system to be implemented for remote control of televisions, toys, security systems,
industrial controls, etc. The choice of transmission
medium is up to the user and can be ultrasonic, infrared radio frequency, or hardwire such as twisted pair
or telephone.
The use of a synchronizing marker technique has eliminated the need for highly accurate frequencies
generated by crystals. The 82600 Encoder typically
generates a 40kHz carrier which it amplitude-modulates with a base-band message of 12 bits, each bit
preceded by a synchronizing marker pulse.
Bits 1 and 12 denote sync and end-of-message, respectively, bits 2 thru 6 constitute a fixed preamble which
must be received correctly for the command bits to
be received, and bits 7 thru 11 contain the command
data. The 82601 Decoder produces an output only
after two complete, consecutive, identical, 12-bit
transmissions. Marker pulses, preamble bits, and
redundant transmissions, have given the 82600/
82601 system a very high immunity to noise, without a large number of discrete components.
82600 Encoder
The 82600 is a CM08 device with an on-chip oscillator, 11 keyboard inputs, a keyboard encoder, a shift
register, and some control logic. The oscillator
requires only an external resistor and capacitor, and
to conserve power, runs only during transmission.
Keyboard inputs are active-low, and have internal
pull-up resistors to VDD. When one keyboard input
from the group A thru E is activated with one from
the group F thru K, the keyboard encoder generates
a 5-bit code, as given in the table entitled ((82600/
82601 CODING," below. This code is loaded into
a shift register in parallel with the sync, preamble,
and end bits, to form the 12-bit message.
The transmitter output is a 40 kHz square wave of
50% duty factor which has been pulse-code-modulated
by (Le., ANDed with) a signal having a recurring
pattern, a bit frame of 3.2 millisecond duration. This
bit frame is comprised of three signals: the 8tart
signal which is 0.4 milliseconds of logic "1"; followed
by the Data signal which is 1.2 milliseconds of the
lowest-order shift register bit; followed by the Mark
signal which is 1.6 milliseconds of logic "0" (except
in the first bit frame where Mark = 1 to facilitate
receiver synchronization).
3.4

The shift register is clocked once per bit frame, so
that its 12-bit message is transmitted once in 38.4
milliseconds. The minimum number of tranmissions
that can occur is two, but if the keyboard inputs are
active after the first 3.6 milliseconds of any 12-bit
transmission, one more 12-bit transmission will result.
Transmissions are always complete, never truncated,
regardless of the keyboard inputs.
The Test Input is used for functional testing of the
device. A low level input will cause the oscillator
frequency to be gated to the Data Output pin. This
input has an internal pull-up resistor to VDD.
82601 Decoder
The 82601 is a PM08 L8I device with an on-chip
oscillator, five keyboard inputs, a 40 kHz signal
input, and 11 outputs. The oscillator requires only an
external Rand C. The five keyboard inputs are activelow with internal pull-up resistors to Vss; activation
of any two causes one of 10 possible 5-bit codes to
be generated and fed to the outputs of the 82601,
overriding any 40 kHz signal input.
Two counters, the signal counter and the local
counter, are clocked respectively by the signal input
and a 40 kHz signal from the local RC oscillator
timing chain. A 40 kHz input lasting 3/2 milliseconds
(Le., an initial bit frame) causes the sIgnal counter to
overrun and reset both itself and the local counter.
At specific intervals thereafter, the local counter
generates pulses used to interrogate the contents of
the signal counter. Resynchronization of the counters
occurs every bit frame so that the interrogation yields
valid data bits even if the transmitter oscillator frequency has deviated up to ± 24% with respect to the
receiver oscillator frequency.
Decoded data bits from the next five bit frames
following the initial synchronizing frame are compared
with the fixed preamble code. The next five decoded
bits, the command bits, are converted to a parallel
format and are compared against the command bits
saved from the prior transmission. If they match, and
if the preamble bits are correct, the command bits
are gated to the receiver outputs. However, a mismatch
causes the receiver outputs to be immediately disabled,
and the new command bits are saved for comparison
against the commarid bits from the next 12-bit transmission. In the case where 2 identical, proper, 12-bit
transmissions are immediately followed either by
transmissions with erroneous preamble codes or by

52600/52601

nothing, the receiver outputs will be activated during
the end-frame of the second transmission, and will be
disabled 45 milliseconds thereafter. In the rest (disabled) state the five Binary Outputs are at a "1" logic
level; when not in the rest state, one or more of the
open-sourced output transistors will conduct to VDD.
The Data Valid output is low during the rest state, and
high whenever data is present at the Binary Outputs.
The 82601 has five other outputs: Pulse Train, On/Off,
Analog A, Analog B, and Analog C. The states of these
outputs are controlled by the 10 particular Binary
Output codes which the receiver Keyboard Inputs can
cause to be generated. The Pulse Train output provides
a 2.44 Hz square wave (50% duty factor) whenever
11011 appears at the Binary Outputs, but otherwise
it remains at a logic "0". This pulse train can be used
for indexing, e.g., for stepping a TV channel selector.
The On/Off ("mains") output changes state each time
0.1111 appears at the Binary Outputs. In TV applications the On/Off output is most often used to kill and
restore the main power supply.
Analog Outputs A, B, and C are 10 kHz pulse trains
whose duty factors are independently controllable.
With a simple low-pass f~ter each of these outputs

can provide 64 distinct DC levels suitable for control
of volume, color saturation, brightness, motor speed,
etc. Each Analog Output increases its duty factor in
response to a particular Binary Output code and
decreases its duty factor in response to another code
- 6 codes in all. The entire range of 0% to 100%
duty factor can be traversed in 26 seconds or at a rate
of the oscillator frequency divided by 262,144. All
three Analog Outputs are set to 50% duty factor
whenever 01011 appears at the Binary Outputs.
Analog A is mutable; 01100 sets it to 0% duty factor.
If 01100 then disappears and reappears. the original
duty factor is restored. This of course implements the
TV "sound killer" feature.
The 82601 has an on-chip power-on reset (PaR)
circuit which sets the Pulse Train and On/Off Outputs
to "0," sets the Analog Outputs at 50% duty factor,
and insures that Analog A is muted. No external
components are required to implement paR, but a
paR input has been provided for applications where
externally controlled reset is desirable, e.g., where the
power supply voltage rise time is extremely slow. The
paR input has an internal resistor pull-up to Vss; pulling it low causes a reset.

Message Bit Format

~
*

**

START
ALWAYS
=1

DECODER DATA OUTPUT
= liN SYNC AND END BITS
= TRANSMITTED DATA
INFRAMES2THRU 11
(PREAMBLE OR COMMAND)

MARK
= liN SYNC BIT
= 0 OTHERWISE

1.2m .. c

M ••,
16 CLOCKS

1.6msec

48 CLOCKS

•

64 CLOCKS

3.2msec
TYPICAL
128 CLOCKS/BIT
(TYPICAL CARRIER = 40kHz)

"I" MEANS PRESENCE OF A 40kHz CARRIER (SQUARE WAVE); "0" MEANS ABSENCE OF A 40kHz CARRIER (SQUARE WAVE).

IF MESSAGE BIT = "I" THEN DECODER DATA OUTPUT = ENCODER DATA INPUT = "0";
IF MESSAGE BIT = "0" THEN DECODER DATA OUTPUT = ENCODER DATA INPUT = "I".

Message Format
FIRSTPREAMBLEBIT=O -'\:-----------~
'"
\.
M
D
M S 0
D
M
S D
M
S D M
S D

INPUT KEYED
STARTED HERE

-

.~

KEY INPUTS
PRESSED 0

OSC
RUN
HA LT DECODE OUTPUT DATA
TRANSMITTED MESSAGE

40 kHz
0SYNC
BIT

OUTPUT
DATA=O

~f- ~f

5 BITSOF
PREAMBLE

5 BITSDF
CDMMAND

~

= OON'TCARE
D
M

r--

OUTPUT
DATA = 1

IL
END
81T

MESSAGE ONE

L-..,~
SYNC
BIT

10 BITSOF
PREAMBLE
& CDMMAND
MESSAGE TWO

76.8msec
TYPICAL

3.5

~

M

IL
END
BIT

-----+

I--

AMII~

82600/82601

S2600/S2601 Coding
Transmitter
Keyboard
Input Pins
Tied to Vss

Receiver
Keyboard
Input Pins

Resulting
Receiver
Binary
Outputs
1
2
3
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0

4
0
0
1
1
0
0

5
0

U

U

I

u

-

0
0
0
0

0

-

0
0
0

1
1
1
1

r~:~ ~oo~Dfi
-

AB
AF
AG
AH
AI
AJ

BC

-

All.

BF
BG
BH
BI
BJ
BK
CF
CG
CH
CI
CJ
CK
DF
DG
DH
DI
DJ
DK
EF
EG
EH
EI
EJ
EK

AE

-

a

CD

\

1
1
1
1

AD
BD

1

-

1

a
0
0

a
a
0
0

-

1
1
1
1
1
1
1
1
1

-

1

1

1

1

-

AB

-

BE

AC

-

NOTES:

a

DE
CE

1
1
1

a

1
1
1
1
1
1

I

1

1

0

1

0

1

1

0
0

0

1
1
1
1

0
0

a

0
0
0
0

a

a

1
1
1

0

1

a
0
0
0

1
1
1
1

Increase Analog C pulse width

1

0
0
0

a

Receiver Dedicated
Functions
(Mask programmable
except for rest state)

Decrease Analog B pulse width

1

0

1
1

1

RESET Analog (See Note 2)
MUTE (See Note 3)

1

1
1

0

1

Toggle On/Off Output

1

0

0

1
1

a

1

Increase Analog B pulse width
Decrease Analog C pulse width

1

Increase Analog A pulse width

a
1
a

1
1

0

0
0

1

1
1

a

0
0

0

1

1

0
1

1

1

Activate Pulse Train Output
Decrease Analog A pulse width
Rest State

1. Receiver keyboard inputs override any remote signal input.
2. Sets Analog A, B, and C waveforms to 50% Duty Factor.
3. First operation sets Analog A to 0% Duty Factor; second operation restores former Analog A Duty Factor.

Electrical Specifications - 2600 Encoder
All voltages measured with respect to Vss.
Absolute Maximum Ratings

Operating ambient temperature TA ................................................ 0 to + 70° C
Storage temperature ...................................................... - 65° C to + 150° C
Positive voltage on any pin .......................................................... +14V
Negative voltage on any pin .......................................................... - 0.3V
Electrical Characteristics

Unless otherwise noted, VDD

= 8.5 ± 1.5V and TA = 0 to +70°C.

Symbol
fO
L:,fO/fO

Parameter
Oscillator frequency
Frequency deviation

IDD

Supply current
Standby
Input "1" threshold
Input "0" threshold
Input source currrent
Output source current
Output sink current

Vrn
VIL
IlL
IOH
IOL

Min.

7
-10

Typ.
640

Max.

2000
+10
2
10

25
50
1
-.2

50
50

75
200

1.5
-.5

Note: Circuit operates with VDD from 3.0V to 12.0V.

3.6

Units
kHz
%
rnA
p.A
%VDD
%VDD
p.A
rnA
rnA

Conditions
Rose = 12K, Cose = 100pF
Fixed Rose, Cose, VDD ± 10%
During transmission,
Data Output = 1mA
No transmission (25° C)
VI = OV
Vo = VDD - 3V
Vo = +0.5V

S2600/S2601

Electrical Specifications - S2601 Decoder

All voltages measured with respect to Vnn.
Absolute Maximum Ratings

Operating ambient temperature TA ............................................... 0° C to 70° C
Storage temperature ...................................................... - 65° C to + 150° C
Vss power supply voltage ........................................................... +31 V
Positive voltage on any pin ...................................................... Vss +0.3V
Negative voltage on any pin ....................................................... Vss - 22V
Electrical Characteristics

Unless otherwise noted, Vss = 14 ± 4V and TA = 0 to +70°C
Symbol

Parameter

Min.

Typ.

Max.

Units

Conditions

fO
MO/fO
Iss

Oscillator frequency
Frequency deviation
Supply current

7
-10

640

2000
+10
50

kHz
%
rnA

Rose = 71K, Cosc = 25pF
Fixed Rosc, Cosc, Vss
No loads, Vnn = 18V
Vnn = 10V

85
35

%Vss
%Vss
%Vss

Vss -5.5
300
2.2

V
V
J.l.A
msec

Signallnput:
"I" threshold
VIH
"0" threshold
VIL
VIH-VIL Voltage hysteresis
Keyboard and POR Inputs:
"1" voltage
VIH
"0" voltage
VIL
Source current
IlL
Debounce delay
(Keyboard inputs only)
Binary Outputs (open source):
Sink current
IOL
Duration
Analog Outputs (open drain):
l:::.Vstep Step Voltage change
Source current
IOH

34
28

30
5

70
48

Vss -.5 Vss - 5.5
50
1.45

-1.28
- 0.50
34.9

1.0
Analog step rate
fstep
Data ValId, Pulse Tram, and On/Off Outputs:
Source current
1
IOH
Sink current
-40
IOL
Risetime (.lVss to .9 Vss)
tr
Falltime (.9Vss to .1 Vss)
tf

150

VI = Vss -10V

- 0.60

rnA
rnA
msec

Vo=Vss - 5.2V, Vss=18V
Vo=Vss - 5.2V, Vss=10V
fO = Max = 704 kHz

Vss/64
1.04
1.15
1.2
10

V
rnA
rnA
rnA
kHz

Vo=Vss .. 0.5V, Vss=10V
Vo=Vss -0.5V, Vss=18V
Vo=Vss -IV
(fO ~ 64)

1.5
- 50

rnA
J.l.A
J.l.sec
J.l.sec

Vo = Vss - 2V
Vo = .7V
RL = 00, CL 50pF
RL =00, CL 50 pF

10
10

Note: Circuit operates with Vss from 7.0V to 30.0V

3.7

1_

52600/52601

Circuit Application

3

A
4
5 B
C

18
VDD

12K
Re
OSC

+

-E
9
10 F
G
11
H
12
I
13
J
14
K

+~

+V = 10 TO 18 VOC

Cl

-2
100pF

~D
~

9V

50pF

g

~
~

OSC
TEST

.".

15
-NC

33K

RC

BOI
B02
B03

paR

B04

.".

DATA
OUT
VSS

16

J
I

TRANSMISSION
MEDIUM

I

13

I

8

r--:I-

,+.. ., ~

~

5
4

SIG
IN
KIA
KIB

B05

g
i
«

0/0
PT

KIC
ANA

KID

ANB

KIE

ANC

12

1276172

.J.

RIPPLE ON FILTER OUTPUT <10mV p.p USING R2 = 10K, R3 = lOOK, C3 = 0.47 ~F, VSS = 14VDC
Cl, C2, AND Cp OPTIONAL

3.8

'0
14

j"'' "'

17

DATA

15

WORD

16
3

DATA VALID

DV

&l

V
DD

KEYBOARD

~

Rl

SS

Cp

___1~3_

11
KEYBOARD

i

1

11

f---

C2
+I---J.

~

r--:--

TOGGLE FOR POWER CONTROL
TO INDEXING CIRCUIT

20
} DC LEVELS
FOR ANALOG

21

22
R3
R C3
2

LOW·PASS
FILTERS

t

CONTROLS
E.G., VOLUME,

BRIGHTNESS,

COLOR SAT

827 43/S27 42
ENCODER/DECODER
REMOTE-CONTROL 2-CHIP SET
Features

Applications

o
o

o
o

o
o

o

RC Oscillator Used - No Crystal Required
Phase Locked Loop on Decoder for Reliable
Operation
512 User Selectable Address Codes
Encoder Operates on a Single Rail 9 Volt
Supply - Suitable for Inexpensive and
Convenient Battery Operation
User Can Determine the Type of
Transmission Medium to Use

o
o
o
o

I

Entry Access Systems
Remote Engine Starting for Vehicles and
Standby Generators
Security Systems
Traffic Control
Paging Systems
Remote Control of Domestic Appliances

Block Diagram 2743 Encoder

Pin Configuration 2743
, . . . . - - - - - - - - - - -.... Vss
r----------_OUTPUT

CONTROL
LOGIC

OSCILLATOR
~------e

RIC

L - - - - - - - " I M - - - - - -.... v"
r-L_-====================~------TEST

Block Diagram of 2742 Decoder

Pin Configuration 2742
OUTPUT

------'Vss
_Von

BIT
DECODE

B1

Vss

ONE-SHOT ftC

OUT

ICOINPUT

CAP

ONE
SHOT

BITS

ICOCAP

1-9

oOP
CAP
VCOI/P

• PHASE OUTPUT

AC UP
VDD

INPUT

3.9

82743/8?742

General Description -

Encoder/Decoder

This two-chip PMOS set includes a user-programmable
serial data encoder for use in a simple low-power transmitter and a serial data decoder for use in a user addressable receiver. The user can select the transmission
medium (RF, infrared ultrasonic, or hardwire). The externally selectable message allows up to 512 codes or add! esses, this is dOlle .. ith the nine binary inputs on each
device. An additional 3 bits of address can be programmed on chip as a fixed preamble.
The serial data encoder encodes by means of a frequencyshift-keyed trinary data pattern composed of 16 data
bits. Each data bit will have a length equivalent to 32
cycles of high frequency clock (20kHz typical) ...Each
trinary data pattern will be 512 cycles of 1/2 the
oscillator frequency length. The encoder frequency
oscillator reference is controlled with an external RC
network. The encoder transmitter can be powered by a
single 9 volt battery so that a single momentary push
button will activate the encoder and transmitter. In the
off position there is no current flow.
The serial data decoder in conjunction with a receiver
amplifier decodes the transmitted 16-bit coded signal.
The on-chip phase-locked-loop locks in on the 20kHz
signal even if the transmitted frequency differs from
the receiver by up to ± 15%. The coded signal input is
compared with the externally selected code. The serial
decoder looks at the transmitted signal a minimum of
three times before validating a good message. A 3-bit
"good" code counter or a 3-bit "bad" code counter accumulates the number of successive good and bad codes
being received.
The decoder has an on-chip one-shot which is user programmedby an external RC combination. Whenever
three complete good codes are received in the "good"
counter a signal enables the one-shot which controls the
signal valid output. If a series of three sequencial bad
codes enter the "bad" code counter the "bad" counter
resets the "good" code counter and one-shot period and
will not allow an active output until the end of the oneshot period. Any "good" code resets the "bad" code
counter. If the "good" counter has accumulated three
good codes and activated the output one-shot, any occasional "good" code (occurring within the one-shot period)
will maintain the output by retriggering the one-shot.
The output appears like a single switch, on when "good"
codes are received, off when not, with the minimum
total period being determined by twice the one-shot

period. The one-shot can be used to prevent the output
from switching on and off too rapidly due to system
noise. The typical RC components shown in the block
diagram give a period of about one second.
Functional Description -

Serial Data Encoder

The AMI serial data encoder is comprised of three secbons: OscillatOI, PI Ogi amnling Logie, ana Contrel
Logic. Specifically it will provide logical ones "I", logical
zeroes "0", and synchronization pulses "S" and arrange
them into a trinary data pattern composed· of 16 data
bits. Each data bit will be 32 cycles of the high frequency
(HF-1/2 Oscillator Frequency) in length. Each trinary
data pattern will be 512 cycles of 1/2 the Oscillator Frequency length.
A logical "I" is represented by 32 cycles of the high frequency.
A logical "0" is represented by 16 cycles of the high frequency followed directly by 8 cycles of the low frequency
(LF = 1/2 HF).
A synchronization pulse "S" is represented by 16 cycles
of the low frequency.
A 16-bit data pattern will be encoded in the device in
such a manner as to have three (3) bits programmed internally and nine (9) bits programmed externally.
The Oscillator Frequency equals twice that of the High
Frequency, and the High Frequency equals twice that of
the Low Frequency.
The Oscillator circuit will require a maximum of three
(3) external components (refer to Figure 2).
External programming inputs connected to the device
- VDD supply will be considered as a logical "1." The bit
programming current will not exceed 50IlA. The programming resistance should not exceed 1kO. Unconnected external bit programming inputs will be considered at a logical "D."
A "1" (- 5V ~ "1" ~ VDD) presented to the "Test" input
sets the Internal counter and maintains the output of
the device "On." The input impedance of the test input
is greater than 5MO.
For portable operation a 9V transistor battery can be
used for the DC voltage supply. Proper circuit polarity
must be observed (- VDD, + V88).

3.10

AMII~

82743/82742

S2743 Absolute Maximum Ratings

DC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 15V
Input Voltage .................................................................... Vss + .3V to Vss - 15V
Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 40°C to + 100°C
Storage Temperature Range ..................... , ....... , .. , ... , ... , . .. .. ... ..... .. ... - 65°C to + 150°C
Lead Temperature (During Soldering). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 300°C for Max. 10 sec.
S2743 Electrical Characteristics (25°C Air Temperature Unless Otherwise Specified)
Symbol

Parameter

Min.

Typ.

Max.

Units

ConditioDs

Operating Supply Voltage
Operating Power Dissipation
Operating Frequency
Programming Bits 1-9, Current
External Programming
Resistance
(DC Bits 1-9) Program Logical "1"
Input Levels Logical "0"
Bits 1-9 Current
Test and R + C Input Impedance
(DC) Test Input Levels Test ON
Test OFF (See Note 1)
R, C Resistance Logical "1"
Logical "0" (See Fig. )
Output Current (See Note 2)

-6.65

-9.5
27
40

-15
40
60
50

V
MW
kHz
",A

VDD

1

kO

Bits 1-9

VDD

V
V
",A
MO
V
V
kO
kO
rnA

Input R 9V> 1.5M @ 5V
Input Resistance 5MO
Maintains Output Device ON
Permits Normal Operation
Resistance to VDD, ± 20%
Resistance to Vss, + 20% - 30%
Output Voltage = .BV WN DD

Notes: 1. Effect noted at Pin 15 to Vss

Figure 1. Serial Data Encoder

2

-5

-6.05
-0.4
55

75

5
-5

VDD
-1

Vss
12
3
5

-7V

2. Output Voltage Pin 15 to Vss

-BV, -5mA
Oscillator
Programming Input, R:s; 1kO

All Voltages measured with respect to Vss
v"

VDD

OSCILLATOR INPUT
DIAGRAM
ALL INTERNAL RESISTANCE
+20%

10K

10K

TO CONTROL LOGIC

2K

2K

3

C2

R2

R1

C1

270K

L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

EXTERNAL OSCILLATOR COMPONENTS

3.11

~

I

AMII~

82743/82742

External Oscillator Components

The Astable Multivibrator Circuit employed here required three (3) external components.
R1 aids in keeping the operating frequency independent
of variators in supply voltage. R2 and C1 form the RC
time constant which controls the oscillator frequency. In
this case, Rl will be specified at 270kD regardless of the
gscillator operatjng frequency Typically it will be found
that R1 > 2T2. R2 should not be greater than 80kD or less
than 20kD; C1 should not be less than 100pF. A method
for determining the approximate value of R2 and C1 is:
Start with the approximate formula for oscillator frequency
1

The I6-bit trinary data pattern includes:
3 "I" bits (fixed) 32 cycles of 20kHz each
1 Sync bit 16 cycles at 10kHz
3 Mask programmable bits either "1" or "0"
9 User-selectable bits externally programmed.
The PLL locks on the "I" bits present in the data pattern. Once locked, the PLL generates a clock which controls the digital decoder section (DDS). The DDS waits
for a sync bit and then compal es the ine6ming data pat
tern bits, one by one, to make sure all the bits are correct;
fixed ones are ones; mask programmable bits match;
and finally verifies that the user-selectable 9-bit pattern
is correct.
Bit Position
Data Pattern

osc. freq;:::::-2RC
It must be noted that the oscillator frequency must be
set at twice the desired device high frequency value.
Using a set value of R or C and a known, desired
oscillator frequency:
To solve for C; w/osc. freq. = 30kHz; R = 60kD
1

1

C --;:::::
;:::::2.77x10- 10 277pF
2Rf 2(60x10 3 ) (30xl03 )
In this case, solve for R2; 2/0sc. freq. = 30kHz; C1 = 500pF
R-

1

2cf

-

1

2(500x10 - 12) (30x103 )

General Description -

"'" 3.33x104 R2 = 33kD

Serial Data Decoder

The AMI serial data decoder is comprised of four sections: Phase Locked Loop (PLL). 16-Bit Digital Decoder,
GoodlBad Code Logic and the Retriggerable Output
One-Shot.
The decoder is always on and the phase locked loop is
running. A small external capacitor determines the
center frequency while an external low pass filter
smooths out and generates the ICO control current. The
typical center frequency of the PLL is 20kHz allowing
the received signal to slightly off frequency and the PLL
will still "lock in,"

I

=

M

=

U
S

=
=

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

IIMMMUUUUUUUUUIS

Fixed "1" (32 cycles at 20kHz)
Mask Programmable Bits
User-Selectable Bits
Sync Bit (16 cycles at 10kHz)

Time for One Pattern

16 x 32 x _1_ ;::::: 25mS
20kHz
If the pattern was correct, a good count (GC) is stored in
a "Good Pattern Counter" (GPC). If the pattern match
did not occur, a bad count (BC) is stored in a "Bad Pattern Counter" (BPC). Then:
=

Any GC resets the BPC.
Three (3) BCs in a row will reset the GPC.
When the GPC reaches four (4) the one-shot is triggered and an output will occur, i.e., three (3) good
codes completed.
4. Anyone GC after an output, occurring within the
one-shot time will retrigger the one-shot and maintain the output on.
The retriggerable one-shot stabilizes the systems operation by introducing hysterisis.
1.
2.
3.

1. It takes more good pattern counts to turn the output on than to maintain it on.
2. After the output goes off, it will stay off for the oneshot period regardless of any good patterns being
received.

An external RC is used to control the one-shot period.

S2742 Absolute Maximum Ratings

DC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 20V
Input Voltage ................................................................................... .
Operating Temperature Range ............. '" .......................... '" .. .. . ... . ... - 40°C to + 100°C
Storage Temperature Range ........ '" .. .. ... . .............. . . .. ... . .... . ... .. . ... .. ... - 20°C to + 70°C
Lead Temperature (During Soldering). ............................................... 300°C for Max. 10 sec.

3.12

AMII~

82743/82742

52742 Electrical Characteristics (25°C Air Temperature Unless Otherwise Specified)

Symbol

Parameter

Min.

Operating Supply Voltage

-15V

Typ.

Conditions

Max.

Units

-20

V

200

MW

75

kHz

Oscillator

Operating Current Static

-10

p,A

No Signal, No Bit

(DC Bits 1-9) Program Logical "I"

-20

V

0

V

Operating Power Dissipation
Operating Frequency

2

20

Input Levels Logical "0"
ICO Input Voltage
Output Voltage
Output Current (VOUT =

-

V

-1

V

10

1V)

Signal Input. AC Coupled

:::::4V

0.025

Input Impedance, AC Coupled
Amplifier

0.05

VDD

At Pin 12

mA
1.0

@lVP-POutputVoltage

V/pk-pk
kQ

20

Figure 2. Typical Bench Test Setup

Vss

GNo
BIT"
2

2743
SERIAL DATA
ENCOOER

1M~'

18

'0

S2742
SERIAL
DATA
DECODER

BIT"

20 VOLTS
10
15

R.C
BIT SELECT
SWITCHES
H(MUST
MATCH DECODER)

14

R,

270k!!

033.f

PIT
13

UK

1

100K
14

OUTPUT

12
SoOK

TEST

Vss

10

TWISTED P A I R - - j

L
"

PUSH BUTIoN
ACTUATOR
SWITCH

- II

OUTPUT

9 VOLT
MALLORY MN1604
DR EQUIVALENT

3.13

SllECT
1·9
IMUST MATCH
ENCODER I

89260/89261 89263/89264/89265

TOUCHCONTROLINTERFACE
Vss
VDD
MIT

Vee

.,

0100
22

SCI

00

21

MIT

01

20
19

06

02

Ie

04

03

17

03

16

Vee

Vss

04

16
NC

10

RC
REF

05

15

02

14

01

13

00

12

VOO

L

,g:g~~

L-

"~:':-11'="" tL8f.J

iH\

PIN/PACKAGE CONFIGURA nON
S9260/S9261

Vss

40

VDO~
MIT

~ee

eUFFERS

110
III

112
113
115

01
02
03
04
05
06
07
08
09
010
011
012
013
014
015

110

MIT

38

015

37

014

36

013

35

012

34

011
010
09

10

31
30

08
07

12

29

06

13

28
27

05

Vee

113

15

26

04

114

16

25

03

NC

17
18

24
23

02
01

19
20

22
21

00

RC

REf

RC

SCI

39

33
32

112

115
SCI

."

'I
150MA~~ 0010~~-

BLOCK DIAGRAM - S9260/S9261 (7 SWITCHES)

OUTPUT

0.390 ~

BEND

I_---------RC

SCI

O

o

0020 MIN

VDO

0'0

M1N-

'60

..

020 _ _

"0

MIN

600
BEND

.. _

lS0MAX ... -

PIN/PACKAGE CONFIGURA nON
S9263/S9264/S9265

BLOCK DIAGRAM - S9263/S9264/S9265 (16 SWITCHES)

FEATURES

•
•
•

•
•
•

Interfaces with up to 16 touch switches
Eliminates contact noise
Comparator sensing permits use with wide
variety of touch switch configurations

3_14

Momentary or toggle operation electrically
selectable
Outputs are TTL/CMOS/MOS compatible
Simplifies design of touch-sensitive switches

.010

59260/59261/59263/59264/59265
GENERAL DESCRIPTION
The S9260 series ofMOS TouchControl interface circuits
permits almost any control panel containing mechanical
switches to be easily replaced by a flat-surface capacitive
control panel providing superior styling, reliability, ease of
cleaning, and safety. Connecting directly to a screened or
etched pattern on the panel's reverse side, these MOS circuits
provide outputs to drive a variety. of logic systems from household appliances to industrial controls. All system functions are
then sele~ted by merely touching the flat conductive TouchControl "switch" areas that have been deposited on the panel's
front surface in practically any configuration desired.
These circuits provide an individual output for each of
up to 16 TouchControl switches. For applications requiring
more switches or encoded outputs, refer to AMI's S9262 and
S9266, which can interface with up to 32 switches.

FUNCTIONAL DESCRIPTION
Fabricated with P-channel ion implanted MOS/LSI technology, the S9260 family* of TouchControl integrated circuits
has been designed to interface with a variety of touch panel
switches and provide a high degree of flexibility in the selection of touch panel materials, layout of touch pad configurations, and design of switching functions. These circuits can
interface directly with either seven TouchControl switches (22
lead versions) or sixteen TouchControl switches (40 lead ver-

TYPICAL APPLICATIONS

•
•
•
•
•

Appliance Control Panels
Home Entertainment Systems
Power Tool Controls
Televisions
Automotive Controls

•
•
•
•
•
•

sions). For each TouchControl switch input there is a corresponding output that may be used to.interface with various logic
families such as CMOS or TTL
Both momentary and "push on - push off' (toggle)
switching operations are available on all AMI TouchControl
circuits and are electrically selected by the logic levels of one
input pin. To ensure reliable switch action, a built-in delay is
incorporated in all circuits requiring a minimum touch time
for switch response.

Telephones
Games
Fast Food Waterproof Keyboards
Moisture Proofing
Industrial Controllers
Computer Terminals

•

•
•
•
•
•

ABSOLUTE MAXIMUM RATINGS
Voltage on any pin relative to Vss:
Operating temperature range:

+ O.3V to - 20V
O°C to + 70°C

Storage temperature (Ambient)

*FOR MULTIPLEXED TOUCHCONTROL CIRCUITS SEE AMI S9262 and S9266.

3.15

Keyboards
Instrumen ta tion
16 to 1 Multiplexers
Microproces~or Interface
Vending Machines
Cash Registers

I

59260/59261/59263/59264/59265

ELECTRICAL CHARACTERISTICS
(O°C < TA

< 70°C; Vss = OV; Voo = -

l3.5V to - l8.0V unless otherwise specified.)

SYMBOL

PARAMETER

V1L

Input logic 0 level
"I" inputs.

VIH

Input logic 1 level - all except
"I" inputs

iRe

Internal oscillator frequency
measured at RC input.

50

Ts
TRsT

Switch delay time
Time to reset all latches using
MIT input.

65

VOL
VOH

Output low voltage
Output high voftage

VOL
VOH

Output low voltage
Output high voltage

SCI

S~an clock output:
Output low voltage
Output high voltage
Supply Current

IOD

CONDITIONS

MIN

TYP

MAX

UNITS

+ 0.3

0

- 1.5

Volts

- 10.0

- 12.0

- 18.0

Volts

100

kHz

135
135

msec
msec

Frequency meaSUTed at RC Input
= 50 kHz

Vss

- 1.0
VDD

Volts

VBB = Vss; 10K
resistive load to VDD

VSS
VBB + 0.4

Vss - 0.5
VBB

Volts

VSS = +5V; VBB = OV
VDD = l2V; 2800[2
resistive load to VSS

Vss

- 1.5
VD D
15.0

all except

100

7.0

OPERATION

Nore: lVIII mpul IS
internally pulled up
to VSS

Max. capacitive
loading < 150 pF
rna

Outputs unconnected

series capacitors and is detected in the MOS circuit. When a
panel switch surface is touched, the signal level into the chip
dimishes, and the on-chip differential amplifier senses the
change and performs the appropriate switching function. For
example, if surface SI is touched, the signal at input 13
decreases, and output 03, normally open, now becomes
active and drives the SI input to the TTL circuitry toward
voltage level VBB.

Device operation can be understood by referring to
Figure 1, depicting a typical application of the S9263. Each of
the sixteen pairs of series capacitors labeled Sl - S16 is one
touch switch located on a TouchControl panel. (For details on
touch panel configuration and operation, see the TouchControl
application note included in this APD.) In each capacitor pair,
the two commotl plates represent the conductive area on the
control panel surface that is to be touched. The other two
plates are formed by two conductive surfaces parallel to the
touched surface and located directly under it on the reverse
side of the panel. Referring again to Figure 1, the S9263
generates a clock signal on output SCI that is applied to one
plate of each capacitor pair; this signal passes through the two

I INPUTS
Inputs from the touch switch pads to the TouchControl
circuit are labeled 10 through 115 (S9263, S9264, and S9265)
or 10 through 16 (S9260 and S9261). Each I input relates
directly to an 0 output of identical numeral.

3.16

AMII~

59260/59261/59263/59264/59265

I

Vss
SCI

Vss

MIT

NC
S5

015

S6

014

S7

013
14

S8

012

S9263

S16

011

16

S14

09

S12

07
110

06
VBB

112

05

113

04

114

03

RC

01

115

00

S11

SID
S9
Sl
S2

02
57614

TYPICAL VALUES:
RI = IOOKn VSS = +5 volts
R2 = 10Kn VBB = 0 volts
R3=91Kn VDD=-12volts
Cl=220pF

REF

CIRCUITS

S13

08

111

TTL

S15

010

S3
S4

VOO

Rl

NOTE. IT MAY BE NECESSARY TO
CONNECT PULLUP RESISTORS TO
TTL INPUT LINES

VOO

BB

VSS

FIGURE 1. 16 SWITCH APPLICATION USING S9263

RCINPUT

o OUTPUTS

A resistor connected to VDD and a capacitor connected
to VSS are connected to the RC input pin to establish the onchip clock frequency that controls the touch switch delay time.
Nominal values for these components are suggested in Figure 1,
but they may be varied to change clock frequency over a range
of SO kHz to 100 kHz.

Each output pin labeled "0" corresponds to an input pin
labeled "1." Whenever an input is selected, the output becomes
active and will drive an external load toward supply voltage
VBB. When outputs are not active, they are high impedance
open drain.
VBB SUPPLY
The sources of all output devices are common and
connected to pin VBB. This allows TTL compatibility as shown
in Figure 1, as well as the ability to drive higher level signals.
For instance, if VSS = 0 volts, VDD = - 16 volts, and VBB =
VSS, then active outputs would drive a load connected to VDD
towards VSS. The VBB pin can be used also to switch analog
signals; in this configuration the analog signals are applied to
the "0" pins and VBB is the output pin.

REF INPUT
In order to allow flexibility in the choice of TouchControl panel materials, switch layout, and switch size, AMI
Touch Control inputs have been designed to detect a differential change rather than an absolute change in level. To obtain a
reference level, two resistors are connected to input REF, one
to VSS and the other to VDD.

3.17

59260/59261/59263/59264/59265

VSS

0---- VSS

'-----l H!-l

10

~f---E-II
------1~L

SCI

LJ

MT

e--- NC

12

05
S9260

------1~
-------I~

13

04

14

03

------1~L

15

VSS

YH

16

02

L
NC-

01
RC

-L

TYPICAL VALUES:
Rl = 100Kn VSS = +5 volts
R2 = 30Kn VBB = 0 volts
R3=91 Kn VOO=-12volts
Cl = 220pF

00

CI
REF

VOO

R2
VSS

r----

06~

11

RI

R3

-----0

TTL

VBB

t--roVoo

VOO

CIRCUITS

NOTE: IT MAY BE
NECESSARY TO
CONNECT PUllUP
RESISTORS TO TTL
INPUT LINES

,1612

FIGURE 2. 7 SWITCH APPLICATION USING S9260

level applied to MIT causes the circuit to operate in the toggle
mode. In this condition, the brief touch of any switch will
turn on the appropriate output, which will remain latched on
until the switch is touched again. Subsequent activations of
the switch will toggle the corresponding output on and off
alternately. To reset all outputs when the toggle mode is
selected, a pulse of Vss level may be applied to the MIT input.

MIT INPUT

The MIT input pin selects the mode of switch operation,
either momentary or toggle. With no connection to the MIT
pin momentary operation is selected, and appropriate outputs
are active only for the duration of touching a switch. In this
mode, no output is active when no switch is touched. A VDD
SCI OUTPUT

The SCI output provides the clock signal for the TouchControl panel. Its frequency is determined by the RC time conMOMENTARY AND TOGGLE COMBINATION

The S9261, 89264, and S9265 contain several outputs
that are permanently in the momentary mode of operation.

stant, and it is connected in common with one of each of the
two common conductive surfaces on the reverse side of the
touch panel.
With the MIT input at Vss these parts function identically to
the 89260 and 89263. With MIT at a logic 1 level, however,
the S9261 has four momentary and three toggle inputs. Table
1 shows the combinations available on all three parts.

3.18

AMII~

59260/59261/59263/59264/59265

TABLE 1. COMPARISON OF FEATURES
Touch Switch Capacity
Touch Switch
Inputs Fixed In
Momentary Operation
(Not affected by
state of MIT input)

Part
Number

Pin
Count

Total Touch
Switch
Interface Capability

Touch Inputs
Selectable For
Either Momentary Or
Toggle Operation Through
Use of MIT Input

S9260

22

7

7

0

7

S9261

22

7

3
(14 thru 16)

4
(IO thru 13)

7

S9263

40

16

16

0

16

S9264

40

16

8
(18 thru 115)

8
(10 thru 17)

16

S9265

40

16

12
(I4 thru II 5)

4
(10 thru 13)

16

Number
of
Outputs

TOUCHCONTROL APPLICATION NOTES
PANEL CONSTRUCTION
A TouchControl switch panel consists of a single sheet
of a rigid material with conductive surfaces applied on both
sides as shown in Figure 3.
A number of materials may be used for touch panels, the
selection of the material most suited for a particular application being dependent on such things as durability, appearance,
ease of assembly, cost, and dielectric constant of the material.
Regardless of the selected panel material, a touch switch
is formed by applying a single conductive surface to its front
surface with two other conductive surfaces applied directly in
line on the reverse side of the panel. Figure 3 shows three views
of a typical touch panel containing two TouchControl switches.
On switch one, conductive surface A is applied to the front of

3.19

the panel and is the surface to be touched to effect a switch
closure. Surfaces Band C are applied directly in line with A on
the opposite side of the panel. A should cover completely and
may overlap surfaces Band C.
The application of the conductive surfaces depends on
selection of the panel materials. If glass is used, for example, it
is common to apply a coating of tin oxide, which is then fired
on for durability; rear surface conductors may be screened on
with a conductive ink. Touch panels may be made more simply
from double-sided printed circuit boards in which the conductive TouchControl surfaces are created by standard etching. For
breadboarding purposes, a number of conductive tapes and
paints are available and may be applied to a variety of touch
panel materials.

I

Mill.

59260/59261/59263/59264/59265

SURFACE C ~
"

~ SURFACE A
GURFACEB
SWITCH 1

SWITCH 1

I---t J-- 2
SWITCH

SC1
SWITCH 2

57610

SW2
SCl
VIEWED FROM
FRONT SURFACE

VIEWED FROM
REAR SURFACE

FIGURE 3. CONSTRUCTION OF A TWO SWITCH TOUCHCONTROL PANEL WITH EQUIVALENT ELECTRICAL CIRCUIT.
ELECTRICAL OPERATION

surface must cover the entire area of the two rear conductors,
it must, then, be at least 1.0 sq. inch. It is desirable to separate
the two rear-surface conductors by at least 0.125 inches, so
the touch surface would be somewhat larger than 1.0 sq. inch.
Higher capacitance, and thus smaller touch switches, can be
obtained by using epoxy printed circuit material; though the
dielectric constant is lower (around 5.0) the thickness can be
decreased substantially.

The three conductive surfaces in a TouchControl switch
combine to form two capacitors connected in series, as shown
in the schematic diagram of Figure 3. An AC signal generated
in the MOS circuit is applied to the rear conductive surface
labeled C. This signal is coupled through to surface A by the
capacitor formed by C and A. The signal is then coupled to
surface B by the capacitor formed by A and B and applied to
one of the inputs of the MOS circuit, which detects the signal's
presence. When surface A is touched, the amplitude of the
signal is significantly decreased because of body capacitance.
This is sensed by the MOS circuit, and the appropriate switching function is performed.

CIRCUIT TO PANEL CONNECTIONS
There are a number of ways to make the necessary connections between TouchControl circuits and panels. A simple
approach is to use a printed circuit board for the touch panel.
In this case, the connections to the circuit are made by the
etched copper pattern. In laying out a printed circuit, it is
important to keep the copper traces running to the individual
touch pads separated from each other as much as possible. In
most instances a minimum spacing of 0.125" between traces is
acceptable, though wider spacing might be necessary in cases
where traces will run parallel to each other for distances of
over six inches. It is also important to keep the clock output
(SCI) at least 0.75 inches away from any input trace. These
spacing requirements are guidelines to be followed regardless
of the touch panel material.
With glass touch panels, a simple method for breadboarding systems is to fasten individual wires onto the conductive surfaces with a conductive epoxy. For production situations, it is possible to locate the electronic circuitry on a separate printed circuit board. Contact to the glass touch panel
can be made through spring contacts mounted in the appropriate locations on the circuit board. An alternate approach is
to route the traces on the glass to an edge of the glass, making connection through an edge connector, keeping in mind
the spacing requirements between traces.

TOUCH SWITCH LAYOUT GUIDELINES
AMI TouchControl circuits have been designed to interface with a variety of touch switch configurations. However,
there are several guidelines that must be observed to insure a
satisfactory TouchControl system.
The size of a TouchControl switch is dependent on the
amount of capacitance needed to couple the clock signal to
the "I" inputs of the MOS circuits. Because the input capacitance associated with the circuit input is typically five picofarads, it is advisable that each of the two series capacitors
formed by the three conductive TouchControl panel surfaces
be no less than seven picofarads. Since the capacitance in picofarads can be calculated by C = 0 .22EA -:- d, where E is the
dielectric constant, A is area, and d is the material's thickness,
it is apparent that minimum switch size is dependent on the
thickness and dielectric constant of the panel material. If, for
example, the panel is made from 1/8" thick glass with a dielectric constant of 8, then the minimum area of each of the two
rear surface conductors is 0.5 sq. inches. Since the touch

3.20

59262159266

MULTIPLEXED
TOUCHCONTROLINTERFACE
Vss
Voo

""':~1:J
r~

",oo~
~

VBB

22

VSS
10

SCI

21
20

B3

19

82

0.020
0016

-=f=-

BO
16

SC2

15

VBB
01

13

00

12

VOD

NC
10

RC
REF

1130MAX

0050

11

12

~ 0365~

r- j
0335

0.390
0410

H'

15 MAX! ~

BLOCK DIAGRAM - S9262 (14 SWITCHES)

PIN/PACKAGE CONFIGURATION - S9262

VSS
10

Vss - - - - - - . .

40

SCI

39

MIT

38

AK

37

B4

36

B3

35

16

10
B2

B3

ITO

12

13
112
113

02
03
04

113
114

~

_ _ _ _ _ _ _ ENA

B2

34

Bl

33

BO

32

EXT

31

SC2

30

06

29

VBB

28

05

27

04

ENA

15

26

16

25

03

24

02

NC
RC

:~: - - - - - - - /

0.010

23

01

115

19

22

00

REf

20

21

VDD

18

S9266

PIN/PACKAGE CONFIGURATION - S9266

BLOCK DIAGRAM - S9266 (32 SWITCHES)

FEATURES

•
•
•
•

•
•
•

Simplifies design of Touch-sensitive switches
Interfaces with up to 32 touch switches
Eliminates contact noise
Comparator sensing permits use with wide
variety of touch switch configurations

3.21

Binary outputs provided
Outputs are TTL compatible
Permits design of totally isolated touch surfaces,
facilitating UL approval

~~

AMII~

89262/89266

GENERAL DESCRIPTION

switches to be easily replaced by a flat-surface capacitive
control panel providing superior styling, reliability, ease of
cleaning, and safety. Connecting directly to a screened or
etched pattern on the panel's reverse side, these MOS circuits
provide outputs to drive a variety of logic systems from household appliances to industrial controls. All system functions are
then selected by merely touching the flat conductive TouchControl "switch" areas that have been deposited on the panel's
front surface in practically any configuration desired.
These circuits can operate up to 32 Touch Control
switches, and their outputs are encoded for easy interfacing
with microprocessors. For applications requiring an individual
output for each TouchControl switch, refer to AMI's S9260,
S9261 , S9263, S9264 and S9265.

FUNCTIONAL DESCRIPTION
Fabricated with P-channel ion implanted MOS/LSI technology, AMI TouchControl integrated circuits* are designed to
interface with a variety of touch panel switches and provide a
high degree of flexibility in the selection of touch panel
materials, layout of touch pad .configurations, and design of
switching functions. These parts are designed to address an
array of TouchControl switches in either a 2 x 7 matrix
(S9262) or a 2 x 16 matrix (S9266) to interface with a total of

TYPICAL APPLICATIONS
•
•
•
•
•

Appliance Control Panels
Home Entertainment Systems
Power Tool Controls
Televisions
Automotive Controls

•
•
•

•
•
•

either 14 or 32 switches. The outputs are binary encoded for
easy interfacing with microprocessors or TTL, CMOS or MOS
logic.
Both momentary and "push on - push off' (toggle)
switching operations are available on AMI TouchControl
circuits and are electrically selected by the logic level of the
MIT input pin. To ensure reliable switch action, a built in
delay is incorporated in aU circuits requiring a minimum touch
time for switch response.

Telephones
Games
Fast Food Waterproof Keyboards
Moisture Proofing
Industrial Controllers
Computer Terminals

•
•
•
•
•
•

Keyboards
Instrumentation
16 to 1 Multiplexers
Microprocessor Interface
Vending Machines
Cash Registers

ABSOUJ fE MAXIMUM RATINGS
Voltage on any pin except EXT
relative to Vss:
Voltage on EXT pin relative to VSS:

Operating temperature range:
Storage temperature (Ambient)

+ O.3V to - 20V
+ 0.3V to - 27V

*For non-multiplexed TouchControl circuits see AMI S9260, S9261, S9263, S9264, S9265

3.22

O°C to + 70°C
- 65°C to + 150°C

.DIII~

59262159266

ELECTRICAL CHARACTERISTICS
(O°C ~ TA ..;; 70°C; Vss

=OV; VDD =- 13.5V to -

18.0V unless otherwise specified.)

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNITS

\'IL

Input logic 0 level - all except
"I" inputs.

+ 0.3

0

- 1.5

Volts

\'IH

Input logic 1 level - all except
"I" inputs.

- 10.0

- 12.0

- 18.0

Volts

fRC

Internal oscillator frequency
measured at RC input.

50

100

kHz

Ts
TRST

Switch delay time
Time to reset all latches using
MIT input.

65

135
135

msec
msec

Frequency measured at
RC Input = 50 kHz.

VOL
VOH

Output low voltage.
Output high voltage

Vss

- 1.0
VDD

Volts

VBB = Vss; 10K resistive load to VDD.

VOL
VOH

Output low voltage.
Output high voltage

VSS
VBB + 0.4

VSS - 0.5
VBB

Volts

Vss = + 5V; VBB = OV
VDD = - 12V; 2800n
resistive load to Vss.

SCI, SC2

Scan clock output.
Output low voltage
Output high voltage.
Supply Current

VSS

- 1.5
VDD
15.0

IDD

100

7.0

OPERATION

CONDITIONS
Note: MIT and
ENA inputs are
internally pulled
up to VSS'

Max. capacitive loading";; 150 pF.
rna

Outputs unconnected

conductors of 16 of the 32 touch switches; the SC2 clock
connects to the remaining 16 switches. For each touch switch
the clock signal passes through the two series capacitors and is
detected in the MOS circuit. When a panel switch surface is
touched, the signal level into the chip diminishes, and the onchip differential amplifier senses the change and performs the
appropriate switching function.

Device operation can be understood by referring to
Figure 1, depicting a typical application of the S9266. Each of
the 32 pairs of series capacitors labeled Sl - 832 is one touch
switch located on a TouchControl panel constructed of glass,
printed circuit board, epoxy, or other dielectric material. (For
details on touch panel configuration and operation, see the
TouchControl application note included in this APD.) In each
capacitor pair, the two common plates represent the conductive
area on the control panel surface that is to be touched. The
other two plates are formed by two conductive surfaces parallel
to the touched surface and located directly under it on the
reverse side of the panel. Referring again to Figure 1 , the S9266
generates a clock signal on output SCI and a similar signal on
output SC2. The SCI clock output is connected to the common

I INPUTS
Inputs from the touch switch pads to the TouchControl
circuit are labeled 10 through 115 (S9266), or 10 through 16
(S9262). The 1 inputs in conjunction with SCI and SC2 outputs form a touch switch matrix of 2 x 16 or 2 x 7, respectively.
In both these parts the outputs are binary coded and will be
described later.

3.23

AMII~

59262/59266

VSS

I~~

.

VSS

SC1J

IU

MIT f---NC

AK
B4
R'

Fll
r---12

S9

j

I

Ij r;= :

B2 f - - - B1 f - - - -

-1r=

SO f - - -

16
,17

EXT~

~

IS

SC2 f - -

C

l9

06

~::;

VSS

~~

I

Al

R3 = 47Kn VDD = -12 volts
Cl = 220pF

04

t-vss

S9266

Cl

~

031-02
f---

~AC

Olf---

115

OO~

[AEF

VOO I - -

1
H3

.1, I" I" I~ ---'I-,'""""~"
'1

I

R2 = 10Kn VBB = 0 volts

114

A2

TYPICAL VALUES:
Rl = 100Kn VSS = +5 volts

I--

rNA

113

rvsa
~

05

Ir-I---I..T-TL..J.- A...I.CU-IT...I.S
CI

57613

FIGURE 1. 32 SWITCH APPLICATION USING S9266

RCINPUT

VBB SUPPLY

A resistor connected to VDD and a capacitor connected
to Vss are connected to the RC input pin to establish the on·
chip clock frequency that controls the rate of multiplexing
and the touch switch delay time. Nominal values for these
components are suggested in Figure I, but they may be varied
to change clock frequency over a range of 50kHz to 100 kHz.

The sources of all output devices (both "0" and "B" out·
puts) are common and connected to pin VBB. This allows TTL
compatibility as shown in Figure I, as well as the ability to
drive higher level Signals. For instance, if Vss =0 volts, VDD =
- 16 volts, and VBB = Vss, then active outputs would drive a
load connected to VDD towards Vss.

REF INPUT

MIT INPUT

In order to allow flexibility in the choice of TouchControl
panel materials, switch layout, and switch size, AMI Touch·
Control inputs have been designed to detect a differential change
rather than an absolute change in level. To obtain a reference

The MIT input pin selects the mode of switch operation,
either momentary or toggle. Applying VSS to the MIT pin
selects momentary operation in which appropriate outputs are _
active only for the duration of touching a switch. In this mode,
no output is active when no switch is touched. A VDD level
applied to MIT causes the circuit to operate in the toggle mode

level, two resistors are connected to input REF, one connected
to input REF, one connected to VSS and the other to VDD.

3.24

AMII~

59262159266

SCl
VSS
~

-__ ..1 1m-

. ~,J
VSS

MIT
83

TTL

12

82

LOGIC

13

Bl

CIRCUITS

14

80

IS1IS2IS3IS4IS5ISSIS7

S9262

TTTTTTT
1..1..11..111..
IS8 IS9 IS

r -r

lOIS11ImIs

13E14

-IT~

Rl ~ lOOKn VSS"'+5vo\1s
R2'" lOKn Vas = o volts

I---

15

SC2

IS

V88 f----oV8B

NC-

01 I--NC

r - r - - - RC
_I-. Cl

OOI--NC

II ""

VOO rroVoo

R2

TYPICAL VALUES

r-- NC

ID
11

R3
Rl

R3",47KS1Voo=-12volts
C1'220pF
57611

FIGURE 2. 14 SWITCH APPLICATION USING S9262

o OUTPUTS
for "push-on, push-off' operation. Subsequent activation of
the switch will toggle the corresponding output on and off
alternately. It should be noted that each input should be cleared
to the off state before selecting a new input to obtain meaningful data from the binary outputs. To reset all outputs when
the toggle mode is selected, a pulse of Vss level may be applied
to the MIT input.

Each output pin labeled "0" corresponds to an input
pin labeled "I". Whenever an input is selected, the output becomes active and will drive an external load toward supply
voltage VBB. This is true for momentary operation only;
toggle operation is described in the section labeled "MT
input." When "0" outputs are not active, they are high
impedance open drain.

SCI and SC2 OUTPUTS

BAND AK OUTPUTS

The S9262 and S9266 have multiplexed inputs, using
2 x 7 and 2 x 16 matrices, respectively, to provide 14 and 32
input states. Clock signals SC 1 and Se2 are used along with
the "J" inputs to form these matrices as connected in the
schematic of Figure 1.

The S9262 has four and the S9266 has five outputs
labeled "B." These supply a binary code relating to the state
of the inputs. Fourteen unique states are available on S9262
and thirty-two on S9266. The output configuration is identical
to the "0" outputs. An extra ot.ttput labeled AK is available
on the S9266 and is active whenever any key is selected.

3.25

AMII~

S9262/S9266

TABLE 1. OUTPUT ENCODING
(VBB = 0 VOLTS)

ENAINPUT
Available on the S9266, the ENA input allows the outputs to be bussed and may be gated off by application of a
logic 1 level. Vss applied to the input enables all five outputs
and AK.

SCAN
OUTPUT
SCI
SCI
SCI
SCI
SCI
SCI
SCI
SCI
SCI
SCI
SCI
SCI
SCI
SCI
SCI
SCI
SC2
SC2
SC2
SC2
SC2
SC2
SC2
SC2
SC2
SC2
SC2
SC2
SC2
SC2
SC2
SC2

EXT
The EXT pin is used in the output circuitry and should
be connected to VDD.

SCAN
OUTPUT
SCI
SCI
SCI
SCI
SCI
SCI
SCI
SC2
SC2
SC2
SC2
SC2
SC2
SC2

-

TOUCHED
INPUT
10
11
12
13
14
15
16
10
11
12
13
14
15
16
None

"8" OUTPUIS
80 81 82 83
0
I
0
I
0
I
0
1
0
I
0
I
0
1
I

0
0
I
1
0
0
I
I
0
0
I
I
0
0
I

0
0
0
0
1
I
1
1
0
0
0
0
I
I
I

0
0
0
0
0
0
0
0
I
I
I
I
I
I
1

"O"OUTPUTS
00
01
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
I
0
0
0
0
0
0
0
0
0
0
0
0
0

TOUCHED
INPUT

80

"8" OUTPUTS
81 82 83 84

00 01

"0" OUTPUTS
02 03 04 05 06

AK
OUTPUT

10
II
12
13
14
15
17
18

19
110
111
112
113
114
115
10
11
12
13
14

19
110
111
112
113
114
115
None

TOUCHCONTROL APPLICATION NOTES
PANEL CONSTRUCTION
A TouchControl switch panel consists of a single sheet
of a rigid material with conductive surfaces applied on both
sides as shown in Figure 3.
A number of materials may be used for touch panels, the
selection of the material most suited for a particular application being dependent on such things as durability, appearance,
ease of assembly, cost, and dielectric constant of the material.
Regardless of the selected panel material, a touch switch
is formed by applying a single conductive surface to its front

surface with two other conductive surfaces applied directly in
line on the reverse side of the panel. Figure 3 shows three
views of a typical touch panel containing two TouchControl
switches. On switch one, conductive surface A is applied to the
front of the panel and is the surface to be touched to effect a
switch closure. Surfaces Band C are applied directly in line with
A on the opposite side of the panel. A should cover completely
and may overlap surfaces Band C.

SURFACE C ~

~ SURFACE A

~

.~ SURFACE B

fswi:i:c'H 1
~

SWITCH I

l----SWITCH 2
SCI

SWITCH 2

ELECTRICALLY EOUIVALENT SCHEMATIC
57610

VIEWED FROM
FRONT SURFACE

VIEWED FROM
REAR SURFACE

FIGURE 3. CONSTRUCTION OF A TWO SWITCH TOUCHCONTROL PANEL WITH EQUNALENT ELECTRICAL CIRCUIT.

3.26

59262/59266

dielectric constant, A is area, and d is the material's thickness,
it is apparent that minimum switch size is dependent on the
thickness and dielectric constant of the panel material. If, for
example, the panel is made from 1/8" thick glass with a dielectric constant of 8, then the minimum area of each of the two
rear surface conductors is 0.5 sq. inches. Since the touch
surface must cover the entire area of the two rear conductors,
it must, then, be at least 1.0 sq. inch. It is desirable to separate
the two rear-surface conductors by at least Q.125 inches, so
the touch surface would be somewhat larger than 1.0 sq. inch.
Higher capacitance, and thus smaller touch switches, can be
obtained by using epoxy printed circuit material; though the
dielectric constant is lower (around 5.0) the thickness can be
decreased substantially.

The application of the conductive surfaces depends on
selection of the panel materials. If glass is used, for example, it
is common to apply a coating of tin oxide, which is then fired
on for durability; rear surface conductors may be screened on
with a conductive ink. Touch panels may be made more simply
from double-sided printed circuit boards in which the conductive TouchControl surfaces are created by standard etching.
For breadboarding purposes, a number of conductive tapes
and paints are available and may be applied to a variety of
touch panel materials.
ELECTRICAL OPERATION
The three conductive surfaces in a TouchControl switch
combine to form two capacitors connected in series, as shown
in the schematic diagram of Figure 3. An AC signal generated
in the MaS circuit is applied to the rear conductive surface
labeled C. This signal is coupled through to surface A by the
capacitgr formed by C and A. The signal is then coupled to
surface B by the capacitor formed by A and B and applied to
one of the inputs of the MaS circuit, which detects the
signal's presence. When surface A is touched, the amplitude of
the signal is significantly decreased because of body capacitance.
This is sensed by the MaS circuit, and the appropriate switching function is performed.

CIRCUIT TO PANEL CONNECTIONS
There are a number of ways to make the necessary connections between TouchControl circuits and panels. A simple
approach is to use a printed circuit board for the touch panel.
In this case, the connections to the circuit are made by the
etched copper pattern. In laying out a printed circuit, it is
important to keep the copper traces running to the individual
touch pads separated from each other as much as possible. In
most instances a minimum spacing of 0.125" between traces
is acceptable, though wider spacing might be necessary in cases
where traces will run parallel to each other for distances of
over six inches. It is also important to keep the clock output
(SCI) at least 0.75 inches away from any input trace. These
spacing requirements are guidelines to be followed regardless
of the touch panel material.
With glass touch panels, a simple method for breadboarding systems is to fasten individual wires onto the conductive surfaces with a conductive epoxy. For production situations, it is possible to locate the electronic circuitry on a separate printed circuit board. Contact to the glass touch panel can
be made through spring contacts mounted in the appropriate
locations on the circuit board. An alternate approach is to
route the traces on the glass to an edge of the glass, making
connection through an edge connector, keeping in mind the
spacing requirements between traces.

TOUCH SWITCH LA YOUT GUIDELINES
AMI TouchControl circuits have been designed to interface with a variety of touch switch configuratiorls. However,
there are several gUidelines that must be observed to insure a
satisfactory TouchControl system.
The size of a TouchControl switch is dependent on the
amount of capacitance needed to couple the clock signal to
the "I" inputs of the MaS circuits. Because the input capacitance associated with the circuit input is typically five picofarads, it is advisable that each of the two series capacitors
formed by the three conductive TouchControl panel surfaces
be no less than seven picofarads. Since the capacitance in picofarads can be calculated by C = 0.22EA -:- d, where E is the

3.27

SWITCHING

The AJMll TouchControl Kit
TCK-IOO
Instructions forAssemblyand Operation
INTRODUCTION

The AMI TouchControl kit demonstrates the ease
with which this unique system of capacitive switching may be implemented. Included in the kit are a
printed circuit board and AMI's newly developed
89263 TouchControl circuit. The printed wiring
board, which has 16 touch switches etched onto its
top surface, contains on its reverse side all the interconnection necessary to interface the 89263 inputs
with the 16 touch switches and the 89263 outputs
with 16 light emitting diodes. As the touch switches

3.28

are activated, the corresponding diodes are lighted
to indicate the output states of the 89263. If
desired, external logic may be operated by connecting a cable directly to the 89263 outputs.
Additional components required for the kit are
readily available, and assembly of the kit should
take less than an hour's time. The circuit board
may be mounted either on standoffs or on a standard aluminum chassis box.

PARTS LIST FOR AMI TOUCHCONTROL KIT:
QUANTITY
REQUIRED
1
1
1
1
1
2
1
1

QUANTITY
REQUIRED

DESCRIPTION
S9263 TouchControl circuit (Included)
Printed wiring board (Included)
Transformer, 12.6 volt 300mA
Radio Shack PIN 273-1385 or equivalent
Line cord
Diode IN920 or equivalent
100KQ Resistor 1A Watt
60KQ Resistor 1A Watt
15KQ Resistor 114 Watt
10KU Resistor 114 Watt

16
1
1
1
16
1

DESCRIPTION
3.3KQ Resistor 1A Watt
Transistor 2N3569 or equivalent
500pF capacitorj20 volts
O.33pF capacitor
220 pF capacitor
Light emitting diode - MV5023
or equivalent
Aluminum chassis box -15" X 9"
Bud #AC1421 or equivalent
(optional)

ASSEMBLY

The circuit board may be assembled easily by referring to Figure 2, a view of the reverse side of the
board. For appearance, it is recommended that all
components except the LED's and the 89263 be
mounted on the reverse side of the board, with all
leads cut off flush with the board's top surface.

For convenience, a 15 volt power supply is provided
on the circuit board, so that the system may be
plugged into a standard 110 volt outlet. If desired,
an external DC supply of 15 volts may be used,
connecting the positive and negative outputs to the
corresponding holes designated for C1. If a DC
supply is used, the transformer, diode, and C1 may
be eliminated.

OPERATION

The AMI TouchControl-kit provides sixteen touch
switches that interface with the S9263 to activate
sixteen light emitting diodes. Each of the switches
numbered from one to fifteen has a light associated
with it which is labeled with the same number. The
switch labeled "T" is used to select the mode of
operation of the S9263, either momentary or toggle.
When the LED labeled "T" is off, touch pads one
through fifteen operate as momentary switches,
and any switch's corresponding LED will turn on
when the switch is touched, remaining on only for
the duration of touching the switch. If "T" is
touched, the "T" LED will turn on and stay on
even after "T" is untouched. The S9263 is now
operating in a toggle mode, and the brief touch of
any switch from one through fifteen will cause its
corresponding LED to turn on and latch. Subsequent activations of the switch will turn the LED

off and on alternately. Touching "T" once again
causes the "T" LED to turn off, and the S9263
once again operates in the momentary mode. By
removing the O.33J.LF capacitor, it is possible to use
the "T" pad as a clear switch. In this mode, all
numbered pads function as "push on, push off"
switches. Touching the ''T'' pad turns off all LED's
corresponding to the numbered switches.
To operate external logic systems with the TouchControl kit, a cable may be soldered, using a
grounded soldering iron, directly to the outputs of
the 89263. The voltage on an output that is turned
off (corresponding LED is off) is - 15 volts (or
VDD). When turned on, the output will rise towards
ground (VSS). Appropriate loading conditions are
specified in the advanced product description for
this part.

3.29

I

16 LED'S MV5023
OR EQUIV.
16 RESISTORS
3300nv..WATT

ICI
• VSS

SCI

10
11
12
13
14
15
16
17

MIT
015
014
013
012
011
010
09
08
07
06

18

S9263

19
110
111

VBB
05
04
03
02

112
113

C3 0.33
L7
L6

Rll

L5
L4

Rll
Rl0

L3
L2
L1

R9
R8
R7

L9

R15
R16

L10

-=

L11
L12
L13

~

R17
R18
R19
R20
R21

TRANSFORMER
12.5 VAC 300MA

---I-~----~------"':":":':"--+--------<'-----...-..4~""T--'2N3569

OR EQUIV.

67650

Figure 1.

Schematic Diagram of TCK·100

PARTS LIST FOR ASSEMBLING TCK - 100 KIT:

PART NUMBER
R1, R4
R2
R3
R5
R6 thru R21
C1
C2
C3

PART DESCRIPTION

PART NUMBER

100 Kn % Watt resistor
10 Kn 1,4 Watt resistor
47Kn ¥! Watt resistor
15 Kn % Watt resistor
3.3 Kn % Watt resistor
500 /J.F capacitor 20 Volts
220 pF capacitor
0.33 /J.F capacitor

Q1
D1
L1 thru L16
IC1
T1

3.30

PART DESCRIPTION
NPN transistor 2N3569 or equivalent
Diode IN920 or equivalent
Light emitting diode - MV5023 or
equivalent
AMI integrated circuit S9263
Transformer 12. 6 V AC @ 300 rnA.
Radio Shack PIN 273-1385
or equivalent

o

o

110VAe

o

o

0

Figure 2.

Rear of Circuit Board

Figure 3.

Front of Panel

3.31

~

0

S1856

MOS DIGITAL
CLOCK
Features
in a 40-pin DIP. The circuit has a separate output pin to
drive each segment of a Liquid Crystal Display directly.
However if the LED mode of operation is selected, only
the HRS X 10 and F3 through A3 outputs are used to
provide segment drive current. In this mode of operation
segment drivers F3 through A3 are multiplexed at 25%
duty cycle to provide MINUTES, 10's of MINUTES and
HOURS information.

o 262,144 External Quartz Crystal

o
o
o

Has 20 Hr. Resettable Elapsed Time Counter
Direct LCD or Tung-sol DT1704 Tube Interface
Electrically Selectable Multiplexed LED Output
Minute and Hour SET Controls
Separate Display Supply Allows Display Turn
Off for Reduced Battery Current Drain
1024Hz Outputs for Voltage Doubler
Calendar Advancing or AM/PM Output

o

o
o
o

The ELAPSED TIME COUNTER can be reset and
displayed separately without affecting the state of the
time keeper. The ELAPSED TIME COUNTER has the
added feature of displaying SECONDS, 10's of
SECONDS and MINUTES automatically during the
first 10 minutes after a reset has occurred. The counter
will then display MINUTES, 10's of MINUTES,
HOURS and 10's of HOURS for the remainder for its 20
hours capacity.

General Description
The S1856 Digital Clock provides the circuitry to
implement a 4-digit time keeper with separate
elapsed time counter. It is an MOS/LSI circuit consisting of down counters, combinational logic, BCD
to 7-segment decoder and output buffer transistors
Block Diagram

Pin Configuration

TEST
BYPASS

Voo

~::o

osc. Y
IN X

Vss

.z

.1

TEST BYPASS
VDD

Vss

CLR

LEDfLG
Voo

READ
E.T.
LED/La

Sb1
Sb2
Sb3

I~'~

VSS
VOO

Voo

~"~
-;

:

ELAPSEO
TIME
CNTR.

25DQ

Vss

500Q

RST
E.T.

I

A1~F1 1~2O~A
A2.F2

-I

5KQ
Vss

10
HRS.

BCD
TO
7·SEG.
DECODER

A3·F3

I~'~'
-I

500Q

Vss
TIME
CNTR.

ADV. MIN
ADV. HRS.

I
I

L-----------

f1 -:--

Vss

Voo Voo

Sb3

AOVAHCEHRS

Voo

CMSbZ

Al

CAL

Bl

AOVAHCEMIN.

Cl

RST ELAPSED TIME

Gl

CMSbl

01

REAOELAPSEOTIME

El

HRSX 10

Fl

F3

AZ

E3

BZ

CAL·I-l~500Q
Vss

03

CZ

G3

G2

HRS

~350A

C3

oz

B3

EZ

500Q

A3

FZ

X10

\-t

Voo

Vss

3.32

CLR

AMII~

81856

Absolute Maximum Ratings
Positive Voltage on any Pin ................................................................. Vss+0.3V
Negative Voltage on any Pin ................................................................. Vss - 28V
Storage Temperature ................................................................ - 65°C to + 150°C
Operating Temperature .............................................................. - 40°C to + 100°C
Dynamic Characteristics: TA = -40°C to +70°C, Vss=OV, VDD -6V to -16V, VOD-5V to -28V
Symbol

Min.

VldOSC X)
VIH
VIH(Control)
VIL
VOH(Outputs)

Typ.

VDD
Vss-1
Vss-0.5
VDD
Vss -1

Max.

Units

VSS -6
Vss+0.3
Vss+0.3
Vss -6

V
V
V
V

An Internal resistor of 700KQ
(typical) to VDD is provided
for all control inputs.

V

Open circuit

V
rnA

Open circuit
VDD -14V
VDD -6V

VOL
IDD

10

IDD

10

VDD
15

Conditions

rnA

Figure 1. Typical Performance Characteristics

./

~t-

/""

10

/
louT

f'

/

-

1.0

SEGMENT OUTPUT _

louT

Voo

I
II

(mA )

~i""""

Voo =-16V/

Voo =-12V"/

-i

(mA )

r= -

Vss

L
I

L

0.5

J

/

-

Voo

~'~ r:.
-

I

OUTPUT

_

Vss

I
I

-

I
8

10

12

14

16

18

12

(VOLTS) Vss - VOUT

16

20

24

28

32

36

(VOLTS) Vss - VOUT

"TOTAL AVG. CURRENT FOR
7SEGMENTS <30mA

Typical Applications
D Automotive Clock
D Household Clock With Auxiliary Battery for Accurate Time Keeping During Power Interruptions
D Appliance Timers
D Industrial Timers
D Photographic Timers
D Avionics Timers
D Portable Clock

Operational Description
The Clock circuit block diagram is shown on the previous
page. The input transistor of the circuit forms an oscillator circuit with an external quartz crystal and a few
other components (see application drawings). The resultant 262.144kHz signal is amplified and clipped in the input stage. A chain of binary down counters divides the
square wave frequency by 256 to supply two complemen-

3.33

AJMII~

81856

tary outputs, ~ 1 and ~ 2 at 1024Hz. These low impedance
outputs can drive an external voltage doubler as well as
allow an accurate frequency tuning on the oscillator.
Next a divide by four stage produces a 64Hz signal from
which the three strobes Sb1, Sb2, and Sb3 are generated.
The strobe generator also contains logic to synchronize
the display outputs with the external strobes as well as
control the segments for Liquid Crystal Display operation. The 64Hz signal also inputs to a divide by 64-stage
to produce a 1 Hz signal which inputs to both the TIME
COUNTER and the ELAPSED TIME COUNTER.
The TIME COUNTER contains the binary stages and
the decoding logic to generate the BCD code for
MINUTES, HOURS and HRS X 10. This data is strobed
into the BCD to 7-segment DECODER and loaded into
the output buffers in synchronization with the appropriate strobe, Sb1, Sb2 or Sb3.

The backplane voltage is generated by buffering the
signal which drives the timing counters. This assures
that visibility of the display will not occur through synchronizing problems or rise and fall time differences.
The phase of the segment outputs is generated from
the contents of data latches and buffer circuits. This provides an active pull-up or pull-down to both terminals
of the segments at all times, thus eliminating the effect of
capacitive coupling across the LCD segment. (See Figure
2.)

When pin 37 is connected to Vss the multiplexed mode of
operation is selected. An ON segment in this mode is driven by a pull-down to Vss which is true during its appropriate strobe time as shown in Figure 3 below.

Figure 3. Strobe Time

The ELAPSED TIME COUNTER functions similarly
to the TIME COUNTER with the additional decoding of
SECONDS and 10's of SECONDS to the display instead
of HRS and HRS X 10 during the first 10 minutes after
reset.

MIN. SEGMENT

V
SSSLJLJL
ON
Von

MIN. STROBE

VOD

VSS~
64HZ
1 1
1

25%

VSS~DUTYCYClE

An internal connection to VDD supply at pin 37 holds the
clock in the liquid crystal mode and the outputs are interfaced directly with the LCD as shown in Figure 2.

Mil. X 10 STROBE

Von

2

2

2

HRS.STROBE

A typical LED interface circuit is shown below in Figure
4. In this mode the HRS X lO-digit is a steady state DC
output and can be used at any of the 3 strobe times.

Figure 2. LCD Output Drive

/ 0·0
".""0

Figure 4. MOS/LED Interface
Vss

BACKPlANE

LCO::~:::: --u-LJLJL
OFF

--u-LJLJL

To assure longevity of the LCD display, a 64Hz signal is
applied to the individual segments. When the applied
segment signal is in-phase with the 64Hz backplane
(LCD common terminal) voltage, no visibility occurs.
When the applied signal is 180 0 out of phase with the
backplane voltage, visibility occurs. The waveforms
shown in Figure 2 represent these conditions.

3.34

.

2
MIN.
X10

s~ ~Uo-

20
_UT_t--"1.

2
MIN.

~

~1Lf3~0_UT +--r~
__

Vss

Y
OD

Mill.

S1856

Functional Description of Inputs
Positive voltage supply return line for circuit.

Vss
Y

Oscillator pull-up resistor connection. A lOKQ resistor to Vee from this pin serves as the
262.144kHz oscillator load.

x

Oscillator input pin. Provides amplification at oscillation frequency of the output from the external
crystal and RC network.

CLR

Master Clear. Resets all counters to zero when connected to Vss.

ADV. MIN.

Sets MINUTES with carry to MINUTES X 10 at a one per second rate when connected to Vss.

RSTET

Displays contents of ELAPSED TIME COUNTER when connected to Vss. otherwise time of day
displayed.

VOD

Negative power supply input for output buffers only. Allows display to be turned off while internal
clock counters continue to operate.

ADV.HRS.

Sets HRS, with carry to HRS X 10, at a one per second rate connected to Vss.

LEDILQ

Mode select pin. When connected to Vss the LED mode is selected. In this mode the three strobe
outputs are used to multiplex outputs A3 through F3 to drive MINUTES, MINUTES X 10 and
HRS X 10 digits. This occurs at 64Hz 25% duty rate. In this mode outputs Al through Fl and A2
through F2 remain off at negative supply level, VOD.

VDD
TEST BYPASS

Negative power supply input for internal logic can be connected to VOD for single supply operation.
When connected to Vss time counters advance at 1024 X normal rate. Used for automatic testing of
the clock circuitry.

Functional Description of Outputs
~l

Voltage doubler and frequency check output. This supplies a 1024Hz square wave signal which
swings between the Vss and VDD voltage levels.

~2

Same as

Sb3

Strobe signal for HRS digit. 64Hz 25% duty cycle with voltage swing from Vss to VOD. Used only
in LED mode.

CMSb2

Drives colon in Liquid Crystal mode and serves as MIN X 10 digit strobe in LED mode. Voltage
swing Vss to VOD.
Calendar advance output. This pin has internal pull-down to Vss only for stepping motor interface.
An external30kQ resistor may be connected to VOD to drive an external latch for AM-PM display.

CAL OUT
CMSbl

~1

but 180 0 out of phase.

Drives display backplane in LIQUID CRYSTAL mode and serves as MINUTES digit strobe in
LED mode. Voltage swing Vss to VoD.

Figure 5. 7-8egment Call Out

I

HRS X 10

3.35

I

AMII~

81856

Figure 6. Application Data

-12V,,(BAHERY')

10KQ

,f

~

1 Vss
3 Y

262.144kHzXTAl

~O

4

~

VOO3S

X

lEOILQ37
AOV. HR 36

15 PF E 10pF

Voo35

6 Sb3

.".

~~

7 Sb2

9 AOV. MIN
10 RSTE.T.
11Sb1

~

.03eF

r; ~;~.
600Q

IGNITIO

/ - - 12 ROE.T.

"-I

13 HRSX10

~

"'-I

14F3

",

"--l

100QY2W
(SPLS)

1KQ
(BA HERY)

51856

15E3

~~

U

110VAC===

1603

""""'-I

r

17G3

~

-

;--

-

<7---"

r--

I

:: ::

( ' _ _ _ _

20 A3
10KQ

~---t-tl

2

~

Vss
~1

+------t----13 Y
M----I-----I4 X
15pF

I

[

jI

HRSX10
L-.-

Sb3a~

-~

j[
HRS

j [~~

,

MINX10

~

~tf

:[

HEGMEHT COMMON
CATHODE LEO DISPLAY

r
MIN
51856

Sb1~~

10

TiiiTII( 111111111111111 "

AUTOMOBILE CLOCK
WITH LED DISPLAY

.1111111111111111111111111.

I B:B B
HOUSEHOLD CLOCK
WITH AUXILIARY BATTERY

3.36

52709
VACUUM FLUORESCENT
DIGITAL CLOCK FOR
AUTOMOTIVE APPLICATIONS
Features

Functional Description

o Uses Inxpensive 4MHz Crystal
o Direct Drive to Green or Blue Vacuum Fluores-

The S2709 vacuum fluorescent clock is a monolithic
MOS integrated circuit utilizing P-Channel low threshold, enhancement mode and ion-implanted depletion
mode devices. The circuit interfaces directly with 4 digit
multiplexed vacuum fluorescent displays and requires
only a single nominal 12V power supply. The timekeeping function operates from a 4MHz crystal controlled input. The display format is 12 hours with colon and
leading zero blanking. An up-converter output is provided by the circuit to generate increased display driving
voltage. A brightness control input allows variation of
the display intensity. An ignition monitor input controls
the up converter operation and inhibits time setting. The
S2709 is normally supplied in a 22-lead plastic dual-inline package.

o
o

cent Display
Low Standby Power Dissipation When Display
is Switched Off With Ignition
Variable Brightness Tracks Other Dash Lights

Applications

o

In Dash Automobile Clocks

o Tape Players, CB Radio Units

o

Automotive After Market Clocks

o Aircraft, Marine Panel Clocks
o Portable Instrumentation Clocks

Pin Configuration

Block Diagram

SEGMENT G

OSCILLATOR OUTPUT

SEGMENT F

OSCILlATOB INPUT

DIGITG.

VDD

SEGMENT 0

TEST

DIGIT GJ
SEGMENT C
DIGIT G2

Vss
IGNITION MONITOR
DAY/NIGHT

SEGMENT 8

DIMMING CONTROL

SEGMENT A

PULSE (UPCONVERTER)

COLON

3.37

TIME SET

SEGMENT E

DIGIT G,

I

52709

Operational Description

Refer to the block diagram and Figure 1, Typical
Application.
Oscillator Input (Pin 21) and Output (Pin 22)- The
crystal controlled oscillator operates at a frequency of
4.194304 MHz to increase accuracy and reduce external
component costs due to the less expensive quartz
crystal. The frequency is controlled by a quartz crystal
and fixed capacitor upconverter output (pin 13). This
method allows accurate frequency tuning of the crystal
oscillator without loading down the oscillator circuit.
The feedback and phase shift resistors are integrated to
further reduce external component costs. The internal
oscillator inverter drives a counter chain that performs
the timekeeping function.
Time Setting Input (Pin 20)- To prevent tampering,
time setting is inhibited until the ignition monitor (pin
16) is held at a logic high level (Vss).
Normal timekeeping is provided by allowing the time set
pin to float externally. (Unloaded, this pin will alternate
between VDD and Vss in phase with the unit minutes
digit strobe [pin 12] during normal timekeeping.) If the
time set pin is held at a logic high level (Vss) the minutes
counter advances at a 2Hz rate without carry to hours. If
the time set pin is held at a logic low level (VDD) the hours
counter advances at a 2Hz rate.
It is possible to reset the hours, minutes and internal

seconds counter by applying a logic low level (VDD ) to the
test input (pin 18) during the time that the ignition
monitor input is at a logic low level (Vss). This reset state
(time 1:00) is used for testing purposes.
Upconverter Pulse Output (Pin 13)-The clock circuit
and vacuum fluorescent display drive normally operate
at 25V when the ignition monitor pin is held at a logic
high level (Vss ). The automobile battery voltage (12V) is
doubled by an external upconverter circuit triggered by
an 8kHz output pulse having a 28% duty cycle. The
voltage, whether 12V or 25V, is applied to the circuit via
the Vss input (pin 17).
When the ignition monitor pin is held at a logic low level
(VDD ) the upconverter is disabled. This drops the Vsssupply to 12V allowing the clock to operate while the
display drive is decreased, lowering power dissipation.
At the battery voltage drops (due to engine starting, cold
temperature, or aging) timekeeping is maintained down
to approximately 7V with no loss of the memory down to
5V. However, below 9V the upconverter will not be inhibited by the ignition monitor input.

Note that low standby power dissipation (60mW typical
@Vss=12V, and no output loads) is accomplished by
turning off the filament voltage to the display when the
auto ignition switch is off.
Ignition Monitor (Pin 16)- Along with preventing the
already mentioned time setting function, the ignition
monitor when held at a logic low level (VDD ) inhibits the
8kHz upconverter output pulse (pin 13) as long as the
supply (Vss) is above 9V. This pin is normally connected
to the auto accessory switch.
The ignition monitor input can be protected against
power supply transients by using 47KQ external series
resistance (see Figure 1).
Day/Night Display Control Input (Pin 15)- As seen in
Figure 2, the display brightness is controlled via both pin
15 and the dimming control input (pin 14). The day/night
input is connected to the automobile parking or
headlights switch such that when these lights are off
(VIN low) the decoded segment and the digit outputs are
from Vss to VS8 - 2.0 volts. When the parking or
headlights are switched on (VIN high) the internal
day/night logic enables the dimming input to control the
segment and digit output voltage and brightness by
allowing adjustable current to flow as controlled by the
dash lights rheostat.
The day/night input can be protected from power supply transients by using 47KQ external series resistance
(See Figure 1).
Display Dimming Control Input (Pin 14)-The display
dimming input is connected to the automobile dashboard
light dimming rheostat through a series resistor. This
allows the fluorescent display to track the dimming
characteristics of the incandescent dashboard light (see
Figure 2). The display dimming control is inhibited
unless the day/night input (pin 15) is held at a logic high
level (V8S).
Display Drivers (Pins 1 through 12)-The 12 hour
display format is comprised of four digits with leading
zero blanking and a flashing colon. Each digit contains 7
segments with individual segments coded in the conventional manner (see Figure 1). The display is multiplexed
with each digit output (G 1, G2, G3 and G4) being strobed
for a time period of approximately 0.5ms. Figure 3 shows
the minimum output current as a function of output
voltage for the digit (grid) and segment outputs.
The colon output (pin 11) is designed to have an unobtrusive flash while still indicating that the clock is functioning normally. The colon flash is accomplished in a 2
second period of 1-112 seconds on the 112 second off.

3.38

82709

Electrical Characteristics
Symbol

VDD
V

Characteristics/Conditions

Vss

Operating Supply Range
VDD=O.OV (Refer to Upconverter
Pulse Output)

Iss

Supply Current
(No loads on Outputs)

O°C to 70°C
Min.

Typ.

7.0

12
25

Oscillator Frequency

Max.

Unit

28

V

12
15

rnA
rnA

4.194304

MHz

512
18.8

Hz

Display Outputs

IOH
IOL
IOH
IOL

AVo
AVo

Multiplex Rate
Duty Cycle (Each Digit Per Cycle)
Output Current (Day/Night = LOW)
Digits, VOH=24V
Vo L = 2V
Segments & Colon, VOH =24V
VOL= 2V
Output Voltage (V[Pin 14]-V(Digit or Seg)
Day/Night = High, V(Pin 14~/4V)
Digits (RL = 8.2KQ to VDD)
Segment (RL = 100KQ to VDD)

25
25
25
25

%

-6.0

rnA

-1.5

rnA

40

JAA

10

JAA

25
25

1
1

V
V

Upconverter Pulse Output

IOH
IOH
IOL

VIH
VIL

Pulse Frequency
Duty Cycle
Output Current
VOH=7V
VOH=23V
Vo L =IV
Time Set Input/Output

8192
25

Input Voltage (No Load)
High
Low

Hz
%

-1.5
-3.0

9
25
25

6.0

25
25

24
0

25

-6.0

rnA
rnA
JAA

1
1

V
V

-2.0

rnA

Output Current
IOH

VOH =18V
Output Frequency
Duty Cycle

Hz

512
25

%

Ignition Monitor Input and Day/Night Input
VIH
VIL
IIH

Input Voltage
High
Low
Input Current (Pull Down) VIH = 12V

9.0 to 25
9.0 to 25
25

3.39

6.5
0
2

Vss
2.0
20

V
V
JAA

52709

Figure 1. Typical Application

VF DISPLAY

,-,0,-,-,
I ,_
=, _,

(FUTABA 4 BT -01 OR EOUIVALENT)
CAR BATTERY
(+12V)

0
IGNI¥~'0-N-----2-~0~Or~2---'L-~~-r-'--r-~'--r~--r-;-'-~
SWITCH

1W
12
(DISPLAY DRIVERS, PINS 1-12)
47J.lF

25V

3

10K

(8kHz)
19

OSC
IN

22
4.194304
MHz

DAY/
NIGHT

21

15

1.2K

IGN
MON

DASH LIGHTS
RHEOSTAT
(son POT TO +12V)

TIME
SET

16

20

-L

o

- USE 130n, 2W FOR
FOR FUTABE 4BT -01

14

~-""""'\I"--.,

VACUUM FLUORESCENT DIGITAL CLOCK

OSC
OUT

0.1, 0.2-2N2222 OR EOUIVALENT

o1M
CONTROL

S2709

1--.N'W,,--+_ _'_-t PULSE

c>--o Vss (SET MINUTES)

47K
47K

25pF

'::

HEAD LIGHT
SWITCH
TO +12V

3.40

IGNITION
SWITCH
TO +12V

47~
0--0

Voo (SET HOURS)

S2809

UNIVERSAL
DISPLAY DRIVER
Features

General Description

o

32 Bit Data Storage Register

o

Drives· LED, LCD, or Vacuum Fluorescent
Displays

o

32 Output Buffers

o

Drives up to 4 Digits

The S2809 Universal Display Driver is a P-channel MOS
integrated circuits capable of driving LED, vacuum
fluorescent, and liquid crystal displays. Data is clocked
serially into a 32-bit master-slave static shift register.
This provides static parallel drive to the display
segments through display drive buffers. To reduce RFI
emanation, capacitors have been integrated on the circuit
for reduction of output switching speeds. Serial interconnection of circuits is made possible by the Data Out Output, allowing additional digits to be driven.

o Expansion Capability for More Digits

o

Reduced RFI Emanation

o

Wired OR Capability for Higher Current

Two or more outputs may be wired together for higher
sourcing currents; useful in applications such as triac
triggering or low voltage incandescent displays. The
S2809 can also be used as a parallel output device for
lAC'S such as AMI's S2000 series single chip microcomputer.

Pin Configuration

Block Diagram

OUTPUT
10F32
STATIC SHIFT
REGISTER ELEMENTS

OUTPUT

24
25

22

26

21

27

20

28

19

29

18

30

17

31

16

32

DATA OUT
INVERT
Vss

13

BLANK

12

CHIP SelECT

11

CLOCK

10

DATA IN
OUTPUT

!

OUTPUT

3.41

OUTPUT

5

I

82809
Absolute Maximum Ratings
Operating Ambient Temperature TA ............ " .......................................... O°C to + 70°C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65°C to + 150°C
Vss Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. + 25V
Positive Voltage on Any Pin .................................................................. Vss + 0.3V

Electrical Characteristics (Vnn = OV, BV < Vss < 22V, TA = O°C to + 70°C unless otherwise noted)
Symbol Parameter

VIH
VIL
VBH
VBL
IB
CB
IOH
IOH
IOH
IOH
los
los
IL
Inn

Min.

Logic 1 Level (Data, Clock, Vss - 0.7
Invert, Chip Select Inputs)
Logic 0 Level (Data, Clock
Invert, Chip Select Inputs)
Logic 1 Level
Vss - 4.0
(Blank Input)
Logic 0 Level
Vnn
(Blank Input)
Current Sinked or Sourced
by Blank Input
Capacitance of Blank Input
>'\ '
Output Source Current
9.0
Output Source Current
4.0
Output Source Current
Output Source Current
10.0
Sink Current Output
Load Device
Sink Current Output
10
Load Device
Output Leakage Currrent
(Output Off)
Supply Current

Maximum Total Output
Loading
Clock Frequency
fc
Clock Input LogiclLevel
ton
Duration
Clock Input Logic 0 Level
toff
Duration
tro, tfo Display Output Current
Rise and Fall Times

Typ.

Max.

Units

VSS + 0.3

V

Vss -7

V

Vss + 0.3

V

Vss - 7

V

1.0

p,A

12

pF
rnA
rnA
rnA
p,A
p,A

VOUT = Vss - 3.
VOUT = Vss-1
VOUT = Vss-O
VOUT = Vss - 50
Output voltage = Vss

p,A

Output voltage :os; + 3V

1.0
50

10M

DC
3.0

10.0

p,A

3.0

rnA

300

rnA

lOOK

Hz

Conditions

Voltage applied to Blank
Input between Vnn & Vss

Not including output
source and sink current
All outputs on

p,S

6.5

p,S

150

10

p,S

"'Measured between 10%
and 90% of output current
Vss < + nv, IOH = 9ma

*NOTE: With supp,ly voltages higher than 11 volts, delay exists before an output rise or fall. This delay will not exceed 100/-15 with a 22 volt supply.

3.42

AMII~

52809

Functional Description

Blank Input

The 32-bit static shift register stores data to be used for
driving 32 output buffers, which may be used to drive
display segments or other circuitry. Data is clocked
serially into the register by the signal applied to the
Clock Input whenever a logic 1 level is applied to the
Chip Select Input; during this time, outputs are not
driven by the shift register but will go to the logic level
of the invert input. With a logic 0 level applied to the
Chip Select Input, the 32 outputs are driven in parallel
by the 32-bit register. It is possible to connect S2809 circuits in series to drive additional displays by use of the
Data Output.

This input may be used to control display intensity by
varying the output duty cycles. With a logic 0 level at
the Blank Input, all outputs will turn off (Le., outputs
will go the the logic level of the Invert Input). With a
logic 1 level at the Blank Input, outputs are again driven
in parallel by the 32 shift register elements (assuming
the Chip Select Input is at logic 0).
The Blank Input has been designed with a high
threshold to allow the use of a simple RC time constant
to control the display intensity. This has been shown in
Figure 1.

Clock Input

The Clock Input is used to clock data serially into the
32-bit shift register. The signal at the Clock Input may
be continuous, since the shift register is clocked only
when a logic 1 level is applied to the Chip Select Input.
As indicated in Table 1, data is transferred from QN-1 to
QN on the negative transition of the Clock Input.
Data Input

Whenever a logic 1 level is applied to the Chip Select Input, data present at the Data Input is clocked into the
32-bit master-slave shift register. Data present at the input to the register is clocked into the master element
during the logic 1 clock level and thus must be valid for
the duration of the positive clock pulsewidth. This information is transferred to the slave section of each
register bit during the clock logic 0 level.

Invert Input
The Invert Input is used to invert the state of the outputs, if required. With a logic 0 level on this input, the
logic level of the outputs is the same as the data clocked
into the 32-bit shift register. A logic 1 level on the Invert
Input causes all outputs to invert.
This input may also be used when driving liquid crystal
displays, as shown in Figure 5.
Data Output
The Data Out signal is a buffered output driven by element 32 of the shift register. It is of the same polarity as
this last register bit and may be used to drive the Data
Input of another S2809. In this manner, S2809 circuits
may be cascaded to drive additional display digits.
Table 1. Logic Truth Table
~

c.:I

!:

w
.....

...ccc =
.....

Chip Select

CI)

c.:I

:c
c.:I

c.:I

el

The Chip Select Input is used to enable clocking of the
shift register. When a logic 1 level is applied to this input, the register is clocked as described above. During
this time, the output buffers are not driven by the
register outputs, but will be driven to the logic level
present at the Invert Input. With a logic 0 level at the
Chip Select Input, clocking of the register is disabled,
and the output buffers are driven by' the 32 shift
register elements.

X
X
X

Z
0
1

0
1

w

~

X
X
X
X
S
S
S
S

I!

Q.,

0
0
0
0
1
1
1
1

~

a:
W
>

a:

0
0

0

1
1

0

X
X
X
X

0
0

-

>Q.,

c

1

w=
_...
==

a:'"

z

C

el=

0
NO CHANGE

1

1
1

o
1

o
1

ON-1-0N
ON-1-0N
ON-1-0N
ON-1-0N

1
ON
ON

0
0
0
0

Figure 1. Typical Display Intensity Control

VTH-~ ~~~~I~~I~~~~~S~C)
VTH VSS-4;;,VTH;;'VSS -7

I'---.JI

f\.. - - - f\.. - - _ f\.._ - ...J
"---.J "'--

I

--.-

\ \ . SEGMENT 0 FF
LSEGMENTON

3.43

V2 (WITH SMALL RC)
30% FULL BRIGHTNESS

•.

AMII~

82809

Figure 2. LED Drive - Series

Figure 3. LED Drive - Shunt

-------,

------,

Figure 5. Liquid Crystal Drive

Figure 4. Vacuum Fluorescent Drive

-------,

------,

SEGMENT

SEGMENT

BACKPLANE

I

_______ ...l

I

______ ..J

Figure 6. Clock Input Waveform

TON

DATA~VALlD_-----I""'I..._DDN"T
IN

~

..

.J

CARE~

3.44

PRELIMINARY DATA SHEET

S10110
ANALOG
SHIFT REGISTER

Features

General Description

D 185 Stage "Bucket Brigade" Delay Line

The S10110 analog shift register is a monolithic circuit
fabricated with P-channel ion-implanted MOS
technology. The part differs from a digital shift
register, which is capable of only digital input and output information, in that an audio signal is typically
supplied as the data input to the analog register, and
the output is the same audio signal delayed in time.
The amount of signal delay is dependent on the
number of bits of delay (185) and the frequency of the
two symmetrical clock inputs. Since each negativegoing clock edge transfers data from one stage to the
next, the analog signal delay equals 185 + 2 X clock
frequency.

D Delays Audio Signals
D

Accepts Clock Inputs up to 500 kHz

D Variable Delay
D Alternate to TCA 350

Block Diagram

Pin/Package Configuration

NC
CLOCK 2 IN

2

8

NC

7

V DO

S10110
DATA
OUT

DATA IN

3

6

DATA OUT

Vss

4

5

CLOCK 1 IN

DATA
IN

277182

CL~~K 1 - - - - 1 - - - - - 1 - 0.065
0.200 MAX

°ffl040
Vss-_

I·
I

I

-+1-1

---r

0.020 MIN
0.090 MIN

V DD - -

J~~:g~~

0.100TYP

0.31 0
0.290·

-r--------1
Ir----\ I

BEND

fR~
0

15 MAXJ LJLO.012
0.008

277181

57639

3.45

•

AMII~

810110

Operation
Device
Figure
analog
typical

operation may be understood by referring to
1. This is an actual schematic diagram of the

shift register, or "bucket brigade," showing
external bias techniques.

Data In Input:

The analog signal, or audio signal, to be delayed is applied to pin 3. This input must be biased to a negative
voltage of approximately -8 volts, and two resistors
may be used as a voltage divider to provide this bias.
They must be chosen so that (R 1) ± (R2) -+- (Rl + R2) is
less than 20 KQ. The input signal applied to this input
through series capacitor CIN may be as high as 6 volts
peak to peak.
Clock 1 and Clock 2 Inputs:

Applied respectively to pins 5 and 2, Clock 1 and Clock
2 are two symmetrical non-overlaping negative-going
clocks used to transfer the analog data along the 185
bit delay line. Although these clocks may have a duty
cycle as low as 25% (Le.: each clock signal is at a
negative level for 25% of its period), better output
signals will be obtained with both clock duty cycles
closer to 50%. It is important, however, that no
overlap of the clock signals occurs at a level more
negative than Vss -0.8 volts.
Referring again to Figure 1, it can be seen that when
Clock 1 is· negative, data is transferred from the data

input to capacitor C1; likewise, data is transferred
from each even-numbered capacitor to the capacitor to
its right. When Clock 2 is negative, data is transferred
from C1 to C2 and from each other odd-numbered
capacitor to the capacitor to its right. In this manner,
data is shifted from the input to C185 after a total of
185 negative clock pulses has occurred (Le.: 93 periods
of Clock 1 and 92 periods of Clock 2).
Data Out Output:

The output of the S10110 analog shift register is a
single device, T187, with its drain at VDD and its
source connected to pin 6. If a 47K resistor to Vss is
supplied at this pin, T187 functions as a source
follower.
Referring to Figure 3, it can be seen that the output
potential during Clock 2 is a constant value near-lO
volts. When Clock 1 switches on (negative), the output
instantaneously drops to a level of approximately-30
volts; this is caused by the 20 volt swing of Clock 1 and
C185. As Clock 1 remains on, device T185 transfers
charge from C184 to C185, and the output voltage
becomes more positive, depending on the charge
previously stored on C184. It is during this part of
Clock 1 that the output reflects the analog data stored
on C1 185 bits earlier. Since the clock signal now appears on the output, it is necessary to apply the appropriate filtering to obtain the delayed analog signal.

Figure 1. Schematic Diagram and Pinouts of S10110
r - - - - - - - - - - - - - - - - - - - - - - - - - - -........- - - ( : > - - - - . 2 4 VOLTS
VDD

I--~--------------

I

I

!lV

1
----u -1 ¥1
T185

T186

'---+--0--...-

r:,,,~

-=

--~--*-----+---+-~c;__
________________ J
277183

3.46

5

DATA OUT

6---

CLOCK 1
CLOCK 2

AMII~

810110

Applications

Absolute Maximum Ratings

D Delay of Audio Signals
Rotating Speaker Simulation
Electronic Chorus
D Electronic Vibrato
o String Ensemble
D Reverberation

Voltage on any pin relative to Vss: +0.3V to -30V
Operating temperature range:
O°C to + 70°C
Storage temperature (ambient):
-65°C to + 150 °C

o
o

Electrical Characteristics
(O°C < TA < 70°C; Vnn = -24V ± 2V; Vss = OV.)

Symbol

Parameter

Min

VCLKL

a
tn

CLOCK 1 and
CLOCK 2 Inputs
Logic Level "0"
CLOCK 1 and
CLOCK 2 Inputs
Logic Level "1"
Duration of CLOCK
Logic "1" Level
CLOCK Input Frequency
Input Bias Voltage
Resistance of the Bias
Voltage Source at Input
Signal Level at
Data In Input
Analog Signal Attenuation
Signal Delay

f3dB

3dB Response Point

VCLKH
tCLKH
fCLK
VBIN
RBIN
VDIN

I

Typ

Max

Units

Conditions

Vss

Vss
-0.8

Volts

No overlap of signals more
negative than Vss - 0.8V

-18

-20

Volts

See Figure 2

0.2 X
TCLK
5
-7.5

See Figure 2
500
-8.5
20

kHz
Volts
KO

6

Volts
P-P
dB

4
185
2 X fCLK
0.1 X fCLK

3.47

See Figure 1
RBIN=(R1) X (R2) +(R1
+ R2) See Figure 1

AMII~

510110

Figure 2. Timing Diagram of Clock 1 and Clock 2 Signals

--~

~-------

\~-----J/VCLKH

CLOCK 1

V CLKL

CLOCK 2

277184

Figure 3. 510110 Output Waveform
CLOCK 2

CLOCK 1

-10V

-v

I
- 30V

ANALOG
SIGNAL

277185

3.48

510111

ANALOG
SHIFT REGISTER
Features

General Description

o

The S10111 analog shift register is a monolithic circuit
fabricated with P-channel ion-implanted MOS technology. The part differs from a digital shift register,
which is capable of only digital input and output
information, in that an analog signal is typically
supplied as the data input to the register. The register's
output is that analog signal delayed in time. Because
the two phase driver required to clock this shift
register is integrated onto this circuit, the part can be
easily driven by a single-phase low capacitance TTL
compatible clock signal. Because each level transition
of the clock input transfers data to a successive delay
element, the amount of delay is equal to the number
of delay elements (185) multiplied by half the clock
period.

o

o
o
o

185 Stage "Bucket Brigade" Delay Line
Delays Analog Signals
Single Phase TTL Compatible Clock Input
Accepts Clock Inputs up to 500KHz
Variable Delay

Typical Applications

o
o

o
o

o
o
o
o

Delay of Audio Signals
Electronic Chorus
Electronic Vibrato
Reverberation
String Ensemble
Rotating Speaker Simulation
Delay of Analog Signals
Musical Phasing Effects

Pin Configuration

Block Diagram

Vss_~

VOO_~

DATA
OUT

VBB _ _

1 OF 185
DELAY ELEMENTS

NC

Voo
DATA OUT
DATA
IN

CLOCK IN

CLOCK
IN

3.49

•

810111

Absolute Maximum Ratings

Voltage on any pin relative to Vss: ............................................. +0.3V to -30V
Operating temperature range: .................................................. O°C to +70°C
Storage temperature (ambient): ............................................. -65°C to +150°C
Electrical Characteristics

(_20°C < TA

< 60°C; Voo

= -24V ± 2V; Vss = OV; VBB = +10V ± 7V)

Symbol

Parameter

Min.

VCLKL

CLOCK Input Logic
Level "0"

VCLKH

CLOCK Input Logic
Level "1"
Duration of CLOCK
Logic "1" Level

tCLKH

Max.

Units

Vss

Vss
-0.8

Volts

-4.0

-20

Volts

48

52

%of
Clock
Period

to

CLOCK Input Frequency
5
Input Bias Voltage
-7.5
Resistance of the Bias
Voltage Source at Input
Signal Level at Data In
Input
Analog Signal
Attenuation
Signal Delay

f3dB

3dB Response Point

fCLK
VBIN
RBIN
VDlN
a

Typ.

Conditions

kHz

500
-8.5
20

Volts
Kit

6

Volts
P-P

4

dB

RBIN=(R1) x (R2)+ (R1 +R2)
See Figure 2

185
2xfcLK
0.1xfcLK

Figure 1. Schematic Diagram

V88D--

T189

DATA

____

T185

1186

r------ID

~

DATA
OUT

Voo

1187

1188

" 1rllUopCLOCK
IN

---Ovoo

91

977318

3.50

S10111

Functional Description

Device operation may be understood by referring to
Figure 1, a schematic diagram of the S10111 analog
shift register. A suggested connection diagram for the
part is shown (Figure 2) along with typical output
waveforms (Figure 3).
Data In Input: The analog signal to be delayed is
applied to pin 3. This input must be biased to a negative voltage of VBIN, which may be accomplished by
a simple resistive divider network. The input peak-topeak signal level may be as high as VDIN.
Clock Input: The Clock input, pin 5, is used to transfer the analog data from each delay element to the
subsequent stage. Because the two-phase clock divider
required to operate the delay line is integrated on the
circuit, it is not necessary to generate a two-phase
clock externally. The single-phase clock is a high
impedance input and may be driven with either MOS
or TTL voltage levels.
Referring to Figure 1, it can be seen that when the
clock input is negative (Le., 

vv\~-(j POSITION 2 1 r 500PF TEST SWITCH 1,0 POSITION 1 'fo POSITION 2 tro and t10 Tests Figure 2. Output Signal DC Loading MAX SOURCE CURRENT" 1.0 rnA -16 -15 -14 V OUT -13 -12 -11 -10 - 9 ISOURCE ~ Your SINK CURRENT TO CHIP VDD o- (Operating Areal 'ro SOURCE CURRENT FROM CHIP VSS ~ - (Current Overload Areal 3.87 -1 r-- -\ r- -16V 'to I 82000 8ingle-Chip Microcomputer Family AMII~ Product Features ROM (Bytes) RAM (Nibbles) AID Converter (8-Bit) Timer Interrupts Power Fail Detect High Voltage Outputs Crystal Clock Option TouchControl Inputs Levels of Subroutine Hof Flags Table Look-up Power-Down RAM Option D/A Converter Option Zero-Crossing Detect Cycle Time (/A sec) Instructions - Total Single Cycle & Byte Voltage (volts) User Definable 7-Segment PLA 82000 Family Comparison Chart S2000 S2000A S2150 1K 64 1K 64 1.5K 80 S2200(2) S2210(3) S2150A S2152(1) 1.5K 80 50/60Hz 1.5K 2K 2K 2K 4K 4K 128 128 128 80 128 128 YES YES YES YES YES Prog-:-N Prog 8Bit Prog 8Bit Prog 8Bit Prog 8Bit Prog 8Bit 2 2 2 2 2 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 3-5 3-5 3-5 3-5 3-5 3 262 2 262 262 262 262 Yes Yes Yes Yes Yes S2200A S2400 S2400A - - - 50/60Hz Yes 3 2 50/60Hz 50/60Hz - Yes 3 2 Yes Yes 3 2 - - - Yes Yes Yes 3 2 - - - - - - Yes Yes Yes Yes Yes Yes 4.5 51 49 9 - Yes 4.5 51 49 9 - Yes 4.5 51 49 9/32 Yes 4.5 51 49 9/35 Yes 4.5 51 49 9 Yes Yes 4.5 63 52 5 Yes Yes 4.5 63 52 5/35 Yes Yes 4.5 63 52 5 Yes Yes 4.5 63 52 5 Yes Yes 4.5 63 52 5/35 No No No No No Yes Yes Yes Yes Yes Yes SES 2150 Yes Yes SES 2150 Yes Yes SES 2150 Yes Yes SES 2400 Yes Yes SES 2400A Yes Yes SES 2400 Yes Yes SES 2400 Yes Yes SES 2400A Yes - - - Development Support Tektronix 8002A(4) In-Circuit Emulator Hardware Emulator SES 2150A SES 2150A "1. Has digital-to-frequency converter (4-bit) for enhanced sound generation. 2. Also available in an 8-bit bus-compatible version - S2220. 3. CMOS 4. Motorola Exorcisor and Intel Intellec Development System Support for the S2000 Family also available. Features AMI's 82000 Family of single-chip microcomputers brings the advantages of microprocessor control to lowcost, multi-feature keyboard/display systems. These circuits are optimized to reduce systems cost while at the same time providing the user with the ability to select from a variety of architectural features. Versatile input/output and an instruction set optimized for its intended applications make an 82000 Family member preferable to expensive multiple-chip solutions. Dramatic cost reductions are possible during product design, manufacture, testing, and maintenance. Two versions are available for the members of the 82000 Family: The standard version for direct drive of LED displays and the" A" version for direct drive of fluorescent displays. The 82000 Family members are entire computers on a chip, suitable for volume keyboard/display applications which require control in a minimum space at a minimum cost. They are ideally suited for systems with the following requirements: o Analog-to-digital and digital-to-analog conversion o Time-of-day and interval timer control o AC line synchronization o Display drive o Keyboard inputs (ohmic or TouchControl) o Arithmetic operations o 8ingle power supply o Program expandability and testability o Triac drive 4.2 AMII~ 82000 Microcomputer Overview Applications The K Lines range from a voltage comparator, Schmitttrigger, and timer inputs on the S2000, to a full bidirectional port on the S2200 supporting A/D and D/A converters, interrupts, and a programmable counter/timer. The S2000 can lower the cost and enhance the performance of control circuits in applications such as the following: D Vehicle instrumentation and systems control D Major household appliances The eight bi-directional three-state D Lines are generalD CB radios, stereo receivers, tape decks purpose data signals. The thirteen A Lines are outputs D Electronic scales for displays, keyboard strobes, control signals, or address D Toys and games lines for external ROM. D Lab instruments D Telephone equipment "A" Versions for Vacuum D Programmable calculators Fluorescent Display o Data sampling devices D Data logging devices The "A" versions of the S2000 Family provide high volD Test equipment tage fluorescent display capability but are otherwise D Keyboard devices identical to their non-"A", LED counterparts. The outD Display devices put buffer drive (Vnn ) is changed to a vacuum fluoresD Remote monitors cent drive (VFn ) and typically tied to 35 volts. The Do D Security systems through D7 and Ao through A4 are changed from LED D Set-back thermostats drivers (nominal 5 volts) to vacuum fluorescent drivers (nominal 26 to 35 volts). Functional Description The basic S2000 has an on-chip 1024-instruction ROM; other family members have ROMs ranging up to 4096 instructions (see tables). If necessary, additional program memory can be added externally up to a maximum of 8192 instructions. The Program Counter is a pointer to the next instruction to be executed. The Program Counter Stack holds return addresses during execution of subroutines or interrupts. CMOS Version-S2210 The scratchpad RAM holds the temporary values of 4-bit data words, typically numeric quantities. The BA, BU and BL registers are used to access RAM words. The E Register can be used as a general purpose register or as an index limit register for controlling RAM access. The ALU-Arithmetic Logic Unit-performs data operations, using the Accumulator and the Carry Register. Software can set reset and test Flags as temporary indicators. For those applications which require micropower, the S2210 is a CMOS version of the S2200. The S2210 is functionally identical and software compatible to the S2200. Microprocessor Bus-Compatible Version-S2220 The S2220 bus-compatible version of the S2200 can be used as a user programmable peripheral or multiprocessor systems. This processor is software compatible with all the other members of the family and is functionally identical (with the exception of some control lines and the D-line interface) to all the other members. The Control Logic includes three inputs and three outputs for interfacing external devices. The Oscillator generates all clocking signals and needs only an external RC circuit to set its rate. Optionally a crystal may be used to precisely control the oscillator frequency. Development Support Tools For information on support tools, both hardware and software, see the Development System Support section of this catalog. 4.3 S2000/S2150/AlS2152 SINGLE-CHIP MICROCOMPUTERS Features o o o o o o o o o o 1024X8 Program ROM On-Chip; Externally Expandable to 8192X8-S2000 1536X8 Program ROM On-Chip; Externally Expandable to 8192X8-S2150 64X4 Scratchpad RAM On-Chip-S2000 80X4 Scratchpad RAM On-Chip-S2150 14 Outputs, 8 Inputs, Plus 8 Bi-Directional Three-State Lines TouchControl Capacitive Touchplate Interface Seconds Timer for Both 60Hz and 50Hz Lines 7-Segment Decoder o D D o D D o LED Display Drivers-S2000/S2150 Vacuum Fluorescent Display DriversS2000/S2150A Single +9V Supply Fast 4.5fJs Execution Cycle Three-Level Subrouting Stack TTL-Compatible Outputs Reset, Test, and Single Step Modes Crystal Input for Accurate Clocking-S2150 S2152:D-To-F Converter Programmable Divide-by-N Counter/Timer Pin Configuration Block Diagram 12 1 IPCMSB)AIl 7 TOUCH CONTROL SWITCH ADDRESS/CONTROL LINES AU. IGRDIVSS DATA/SEGMENT LINES (3·STATE) KU.4.a l ',2.4,8 1." a I'1Q 9 10 36 0, 35 SYNC 34 RUN 520001 32 1(. S2150lA 31 1(1 A! 11 30 .. , A, 13 28 '."IIDTIMER A~ ,. ... ~ 15 A~ 16 25 " 23 ClM· IPClSB1A0LL::,,'--_--'-":..r STATUS· VGG - LOGIC VFO or VOO= OUTPUT BUFFERS VSS-GROUND -s2150-11 BITS 4.4 " " J1 " 32 fooT 31 Ct:1I 29 Y6G S2000/S2150/AlS2152 Functional Description The 82000/82150 are ideal for a wide range of appliance and process control designs. Versatile input/output and an instruction set optimized for its intended applications make the 82000 preferable to expensive multiple-chip solutions with dramatic cost reductions during product design, manufacture, testing, and maintenance. The 82000/82150 have an on-chip 1024/1536 instruction ROM. If necessary, additional program memory can be added externally up to a maximum of 8192 instructions. The Program Counter is a pointer to the next instruction to be executed. The 8ubroutine 8tack holds return addresses during execution of subroutines. The scratchpad RAM holds the temporary values of 64/80 4-bit data words, typically numeric quantities. The BU and BL registers are used to access RAM words. The E Register can be used as a general purpose register or as an index limit register for controlling RAM accesses. The ALU -Arithmetic Logic Unit-performs data operations, using the Accumulator and the Carry Register. 80ftware can set and test two Flags as temporary indicators. The Control Logic includes three inputs and three outputs for interfacing external devices. The Oscillator generates all clocking signals and needs only an external RC circuit to set its rate. The KREF Input is the analog reference for TouchControl and similar interfaces. 8oftware decision-making instructions sample the four K Inputs and the four I Inputs, one of which can be used as a line-frequency counter. The eight bi-directional three-state D Lines are generalpurpose data signals. The thirteen A Lines are outputs for displays, keyboard strobes, control signals, or address lines for external ROM. General Description for S2152 The 82152 is an extension of the 82000/82150 and is software compatible with them. It has the following enhanced features: o Digital-To-Frequency Converter (4-Bit) o Programmable Divide-by-N Counter/Timer o 15 Outputs, 4 Inputs, and 8 Bi-Directional Three8tate Lines o One Open Drain Output, and o High Current Outputs S2000/S2150lAlS2152 Instruction Set Summary ADCS ADD ADISX AND CMA DISB DISN ACC+RAM+CARRY, Skip if Sum~15 ACC+RAM ACC+ x, Skip if Sum~15 ACC"AND"RAM Complement ACC Display Number in Binary Format Display Number in Seven Segment Format EUR (European) SET 50/60Hz and Display Latch Polarity INP Input 8 Bits from D Lines JMPX JMSX Jump Jump to Subroutine LAB LAE LAIX LAMY Load ACC with BL Load ACC with E LOAD ACC with X LOAD ACC with RAM then BU "XOR"Y LBEY LBFY LBEPY LBZY Load Load Load Load MVS Move Master Latch to Slave Latch NOP No Operation OUT PPX PSH PSL Output 8 Bits to D Lines Prepare Page (or Bank) Preset Master Strobe High Preset Master Strobe Low BL with BL with BL with BL with E and BU with Y 15 and BU with Y E+1 and BU with Y 0 and BU with Y RF1 RF2 RSC RSMZ RT RTS Reset Flag 1 Reset Flag 2 Reset Carry Reset RAM Bit Z Return from Subroutine Return from Subroutine and Skip SAM SBE SF1 SF2 SOS STC STMZ SZC SZI SZK SZMZ Skip if ACC=RAM Skip ifBL=E Set Flag! Set Flag2 Skip if Seconds Flag Set Set Carry Set RAM Bit Z Skip if Carry = 0 Skip if 1=0 Skip if K=O Skip if RAM Bit Z = 0 TF1 TF2 Skip if Flag! = 1 Skip if Flag2 = 1 XAB XABU XAE XCV Exchange ACC with BL Exchange ACC with BU Exchange ACC with E Exchange ACC with RAM then BU "XOR"Y Exchange ACC and RAM, BU "XOR"Y, Decrement BL, and Skip if BL = 0 Before Decrementing Exchange ACC and RAM, BU "XOR"Y, Increment BL, and Skip if BL=O After Incrementing ACC "Exclusive-OR" RAM XCDY XCIV XOR 4.5 I S2200/S2400/AlS2210 SINGLE-CHIP MICROCOMPUTERS Features o o o o o o o o o o 8-Bit AID Converter with 8 Inputs 8-Bit D/A Converter 2048X8 Program ROM On-Chip and Expandable to 8192X8 (S2200/S2200A/S2210) 4096X8 Program ROM On-Chip and Expandable to 8192 X 8 (S2400/S2400A) 128 X 4 Scratchpad RAM On-Chip with Power-Down Mode Two-Level Maskable Priority Interrupt System with Provision for Software Interrupt Programmable 8-Bit Timer/Event Counter On-Chip 14 Outputs, 8 Bidirectional Three-State Lines, TTL-Compatible, Plus 8 Independently Software-Defined I/O Lines TouchControl Capacitive Switch Interface Seven-Segment Display Decoder/Drivers: o o o o o o o o o o o o S2200/S2400/S2210-LED S2200A/S2400A - Vacuum Fluorescent Single + 5V Power Supply 4.5/As Cycle Time 63 Instructions-52 Single Byte and Single Cycle 3-Level Subroutine Stack (5-Level if Interrupts Not Used) 2-Level Interrupt Stack Built-In Production Test Mode Single Step Capability Power Failure Detection and Power-On-Reset Circuitry Up to 256 General Purpose Flags (RAM Bank 1) 6 Special Flags Table Look-Up Ability S2210-CMOS Version of the S2200 S2220-Microprocessor Bus-Compatible Version of S2200 Block Diagram Pin Configuration PORIY RAM Vss ExT ClK ROMS ClK RUNS SYNC 07 VREF 03 STATUS 06 Ks 02 K, Os eLK Cli K7 0, STATUS K3 04 K6 Do m 522QOl52400 K2 POR/VUM K. Vee kO A'2 Al1 Ao A,o A, lED DRIVE S2200A/S2400A FLUDJlESCENTDRIVE 4.6 Ag A2 A. A3 A7 A4 A6 As AMII~ S2200/S2400/AlS221 0 General Description The 82200/82400 provides a quantum jump in chip features beyond the 82000. In addition to all the features the 82000 offers, the 82200 gives the added flexibility of interrupts and the sophistication of an on-chip AID and/or D/A converter capable of analog data making it suitable for a wide range of applications. The PLA which defines the 7-segment outputs of a DI8N is user definable. The Control Logic includes three inputs and three outputs for interfacing external devices. The Oscillator generates all clocking signals and needs only an external RC circuit to set its rate. Optionally a crystal may be used to precisely control the oscillator frequency. The 128 X 4 scratchpad RAM holds the temporary values of 4-bit data words, typically numeric quantities. The BA, BU and BL registers are used to access RAM words. The E Register can be used as a general purpose register or as an index limit register for controlling RAM access. The K Lines are a full bi-directional port on the 82200 supporting AID and D/A converters, interrupts, and a programmable counter/timer. The ALU -Arithmetic Logic Unit-performs data operations, using the Accumulator and the Carry Register. 80ftware can set reset and test Flags as temporary indicators. The eight bi-directional three-state D Lines are generalpurpose data signals. The EXT signal is an output data strobe for the D Lines. On the 82220, the D Lines become the data bus interface. The thirteen A Lines are outputs for displays, keyboard strobes, control signals, or address lines for external ROM. S2200/S2400/A/S2210 Instruction Set Summary Sum~ ADCS ADD ADIS X AND ACC+RAM+CARRY, Skip if ACC+RAM ACC + X, Skip if Sum ~ 15 ACC "AND" RAM CMA DEV DISB DISN Complement ACC Skip Always Display Number in Binary Format Display Number in Seven Segment Format IBLS IND INK Increment BL and Skip if BL=O after Incrementing Input 8 Bits from D Lines Input 8 Bits from K Lines JMPX JMSX JMSI Jump Jump to Subroutine Jump to Subroutine Indexed LAB LAE LAIX LAMY LAMY LANG LBEY LBZY LMOD LRAIW MVS Load ACC from BL Load ACC from E LOAD ACC with X LOAD ACC with RAM then BU "XOR"Y Load ACC from RAM then BU "XOR"Y Load Analog Reg Load BL with E and BU with Y Load BL with 0 and BU with Y Load Modules Reg Modify RAM Address NOP No Operation OUTD OUTK PPX PSH PSL Output 8 Bits to D Lines Output 8 Bits to K Lines Prepare Page (or Bank) Preset Master Strobe High Preset Master Strobe Low Move Master Latch to Slave Latch 15 RANG RAR RBIN RCTL RFLGW RSC RSMZ RSMIW RT RTI RTS Read Analog Reg Rotate ACC Right Read Binary Counter Read Control Reg Reset Flag W Reset Carry Reset RAM Bit Z Reset RAM Bit W in Bank 1 Return from Subroutine Return from Interrupt Return from Subroutine and Skip SAM SANG SBE SCTL SFLGW STA STC STMZ STMIZ SWI SZC SZK SZMIW SZMZ Skip if ACC = RAM Start AID Conversion Skip if BL=E Set Control Reg Set Flag W Store ACC in RAM Set Carry Set RAM Bit Z Set RAM Bit W in Bank 1 Software Interrupt Skip if Carry = 0 Skip if K=O Skip if RAM Bit W in Bank 1 = 0 Skip if RAM Bit Z = 0 TFLGW TLU XAB XABU XAE XAK XCY XCDY Test Flag W Table Look-Up Exchange ACC and BL Exchange ACC and BA, BU Exchange ACC and E Exchange ACC and KSR Exchange ACC and RAM, then BU "XOR"Y Exchange ACC and RAM, Decrement BL, BU "XOR"Y, and Skip if BL=O Before Decrementing ACC "Exclusive-OR" RAM XOR 4.7 AMII~ Typical Application Block Diagrams S2000/S2150 Appliance/Outlet Controller AMI S2000/2150 Vee (+9V.) lED DISPLAY VGG 0 0 .7 Voo ROMS RUN 4 AO.3 ClK Vss Kl.2.4,a KREF POR A, ~------+ ALARM .., I, AC AS.'2 :r. I, ISensitive ~a~T~c_ _ I American (60 Hz) I _ _ _ _ UP TO 8 OUTLETS S2200A Microwave Oven Controller 50Hz ..:.-. .:a-....:-...:.. flUORESCENT DISPLAY MEAT ANNUN· CIATORS OVEN TEMPERATURE SENSOR STIRRER MAGNETRON BROWN SPKR. FRED ~PKR. STATE AS A6 A1 AS Ag DOOR INTERLOCK K1 .~ AO AMI SZZOOA A4 0 0 0 D 0 D D D D D 0 0 D D 0 0 TOUCHCONTROL KEYBOARO MAGNETRON 8, VACUUM FLUORESCENT FILAMENTS 4.8 0 D D D ~ 52000 Family Mask Option Specification Form The 82000/82200 Family has several options which need to be specified before an order can be placed. The forms on the following two pages call out by part number which options are available and what must be specified, e.g., package type, operating temperature range, pin count, etc. For most options, simply circle the appropriate response. However, for the 28 pin package option, Table 1 details which pins cannot be deleted and which pins may be deleted. To assure that the customer's pin configuration can be bonded within the package, always consult with Microcomputer Product Marketing before placing an order. S2000 Family Mask Option Specification Form For the S2000/S2000A, S2150/S2150A/S2152 DATE _ _ _ _ __ COMPANY NAME CONTACT_____________ PHONE NUMBER (_ _ )_ _ _ _ _ EXT. _ _ __ P.O.# S.O.#(For Factory Use Only) FilE NAME (For Diskette Only) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ I. S2000/S2000A: A. PACKAGE (circle one): PLASTIC CERAMIC DIE B. OPERATING TEMPERATURE RANGE (circle one): T1 T3 T2 T4 C. PIN COUNT (circle one): 28 40 IF 28, SPECIFY PINS (see Table 1): _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ T1 = DoC to + 55°C; T2 = DoC to + 70°C; T3 = O°C to + 85°C; T4 = - 40°C to + 85°C II. S2150/S2150A/S2152: A. PACKAGE (circle one): PLASTIC CERAMIC DIE B. OPERATING TEMPERATURE RANGE (circle one): T1 T2 T3 T4 C. PIN COUNT (circle one): 28 40 IF 28, SPECIFY PINS (see Table 1): _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ O. Clock (circle one): Crystal R-C Table 1. Optional/Required Pin Table for 52000/52200 Families S2000/S2150 PlN# NAME REO. S2200 OPT. PIN# NAME REO. CONDmONS/REASONS OPT. 1 Vss X 1 Vss X Power supply-Ground 29 VGG X 28 Vee X Power supply-most positive: + 9V or + 5V 2,3,4, 36-40 00-0 7 X 30-37 00-0 7 X Internal ROM Test 7-11, 36-40 Ao-AI2 Program Counter Monitor, comprises skip. stack & jump test cannot reliably test if al lines deleted X 15-27 5 ROMS 6 EXT X X 39 An-All' A12 ROMS 40 EXT X X Internal ROM test X Optional if SOS, OUTO instructions not used 35 SYNC X 4 SYNC X Required 34 RUN X 38 RUN X Required 22 POR X 29 PORI X Required VRAM 23 ClK X 21 Status X 24 KREF X 12 VOO/VFD 25-28 II-Is X 30-33 K1-K s X X Mask Option Required only if crystal option is exercised 2 ClK 3 ClK X X 6 StatusIVFD X 5 7-14 VREF Ko-K7 30-33 K,-Ks X X X Cannot be internally bonded to VGG X This table shows which pins are required and optional for S2000/S2200 family devices. Those pins which are optional may be deleted in any mix to make a 28-pin package. If possible. pins should be deleted in as even a manner as possible to facilitate bonding the die to lead frame. 4.9 I S2000 Family Mask Option Specification Form 52000 Family Mask Option Specification Form For the 52200/52210/52220/52400 DATE _ _ _ _ __ COMPANY NAME CONTACT _ _ _ _ _ _ _ _ _ _ _ __ P.O.# _ _ _ _ _ _ _ _ __ PHONE NUMBER ( __ )_ _ _ _ _ EXT. _ _ __ S.O#(For Factory Use Only) FILE NAME (For Diskette Only) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ I. 52200/52210/52200/52400 A. PACKAGE (circle one): PLASTIC B. PIN COUNT (circle one): CERAMIC 28 DIE 40 IF 28, SPECIFY PINS (see Table 1): _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ C. R= F. D= G. C= D. P= _ _ _ _ _ _ _ _ __ H. W= E. 1= B. = J. VFO : K. OPERATING TEMPERATURE RANGE (circle one): T1 Yes ("A" Version) No T2 T3 T4 T1 = O°C to + 55°C; T2 = O°C to + lO°C; T3 = O°C to + 85°C; T4 = - 40°C to + 85°C NAME OF OPTION CODE RAM POWER R=1T016: R=O: RAM power is supplied from theJ50R/V RAM Pin (see S2200 PDS) RAM is supplied from Vce. POWER-FAIL DETECTION P=1: P=O: A non-maskable interrupt (jump to address 0400 HEX) occurs when Vee c; VPOR No interrupt for low Vee LOW-PRIORITY INTERRUPT -K7 HI-PRIORITY INTERRUPT -K6 1=0: K6 & K7 not connected to interrupt logic K6 only connected to interrupt logic K7 only connected to interrupt logic Both K6 & K7 connected to interrupt logic D/A OUTPUT D=I: Digital-to-analog converter output appears at K5 C=1: On-chip master oscillator configured to accept a piezoelectric crystal; can be driven by an external oscillator On-chip oscillatory uses an external resistor and capacitor; or can be driven by an external oscillator CLOCK OSCILLATOR 1=1: 1=2: 1=3: C C=O: RESETSTATE·OF.A-LINE W W=1: W=O: Whenever the chip enters power-on reset, the "A" outputs are all set to ones "A" outputs are all zeroes after POR. BUS COMPATIBILITY B B=1: B=O: Bus compatible option (S2220) Standard See Chapter 3 of PDS for S2200/S2400 et al. Choice of wide operating temperature ranges may require slight derating of some electrical parameters: please consult with the factory. 4.10 86800 Microprocessor Component Family Eight Bit 56800 Family Selection Guide MICROPROCESSORS S6800/S68AOO/S68BOO 8·Bit Microprocessor (1.0/1.5/2.0MHz XTAL) S68HOO High Speed S6800 (2MHz Clock) S6801lS6801E Single Chip Microcomputer 2K ROM, 128X8 RAM, 31 110 Lines, Enhanced Instruction Set (External IE) or Internal Clock) S6802/S68A02 Microprocessor with Clock and RAM (1.0/1.5MHz Clock) S6803/S6803N /R S6801 Without ROM (N/R Model- No ROM and/or RAM) 86805 8ingle Chip Microcomputer 1,152X8 ROM, 64X8 RAM, Clock, Pre·scaler, Bit Level Instructions. 86808/S68A08 86800 with Clock (1.0/1.5MHz Clock) 86809(E)/868A09(E)/868B09(E) Pseudo 16·Bit Microprocessor (1.0/1.5/2.0MHz Clock) (E Models - External Clock Mode) 81602 Universal Asynchronous ReceiverlTransmitter (UART) PERIPHERALS 82350 Universal Synchronous ReceiverlTransmitter (U8RT) 868211S68A211868B21 Peripheral Interface Adapter (PIA) (1.0/1.5/2.0MHz Clock) 868H21 High 8peed Peripheral Interface Adapter (PIA) (2.5MHz Clock) 86840/S68A40/S68B40 Programmable Timer (1.0/1.5/2.0MHz) 868045 CRT Controller (CRTC) 86846 2K ROM, Parallel 110, Programmable Timer 868047 Video Display Generator (VDG) 86850/S68A50/868B50 Asynchronous Communication Interface Adapter 800 Bus Compatible 86852/S68A52/S68B52 Asynchronous Communication Interface (1.0/1.5/2.0MHz Clock) (ACIA) S6854/S68A54/868B54 Advanced Data Link Controller (ADLC) (1.0/1.5/2.0MHz Clock) 868488 IEEE - 488 Bus Interface S6894 Data Encryption Unit (DEU) MEMORIES 86810/S68AI0/868BlO 128X8 Static RAM (450/360/250ns Access Time) 86810-1 Low Cost 86810 (575ns Access Time) 5.2 S6800/S68AOO/S68BOO 8-BIT MICROPROCESSOR Features o o Eight-Bit Parallel Processing OBi-Directional Data Bus o Sixteen-Bit Address Bus - 65536 Bytes of Addressing o 72 Instructions - Variable Length o Seven Addressing Modes - Direct, Relative Immediate, Indexed, Extended, Implied and Accumulator o Variable Length Stack o Vectored Restart o 2 Microsecond Instruction Execution o Maskable Interrupt Vector o o o o o Separate Non-Maskable Interrupt - Internal Registers Saved in Stack Six Internal Registers - Two Accumulators, Index Register, Program Counter, Stack Pointer and Condition Code Register Direct Memory Access (DMAI and Multiple Processor Capability Clock Rates - S6800 - 1.0MHz - S68AOO - 1.5MHz - S68BOO - 2.0MHz Simple Bus Interface Without TTL Halt and Single Instruction Execution Capability Pin Configuration Block Diagram Vee GNO GNO (S) (1) (36) OBE (21) (33) DO (32) 01 (31) 02 (30) 03 (29) 04 (2S) 05 RESET rna: NMi <1>1 <1>2 (27) 06 (40) (26) 07 (4) (6) (3) (37) BA R/W (5) (7) (34) TSC A15 A14 A13 A12 All Al0 A9 AS A7 A6 A5 A4 A3 A2 Al AO 5.3 40 1. 39 38 37 36 f11 IRQ VMA NMI BA Vee AO A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 (2) HALT VMA GNO HALT RESET TSC ;2 OBE 35 34 33 10 11 12 13 14 15 16 17 18 19 20 56800 568AOO S68800 32 31 30 29 21 R/W DO 01 02 03 04 05 06 07 A15 A14 A13 A12 GNO I AMII. S6800/S68AOO/S68BOO Absolute Maximum Ratings Supply Voltage Vcc .................................................................... - 0.3 to + 7.0V Input Voltage VIN .................................................................... - 0.3V to + 7.0V OperatingTemperatureRangeTA ........................................................ O°Cto + 70°C Storage Temperature Range Tstg .................................................... - 55°C to + 150°C Electrical Characteristics (Vcc = 5.0V, ± 5%, VSS = 0, TA unless otherwise noted.) Symbol VIH VIHe Characteristics Input High Voltage (N ormal Operating Levels) ~1, ~2 VIL VILe Input Low Voltage (N ormal Operating Levels) lIN Input Leakage Current (VIN = 0 to 5.25V, Vee = Max) (VIN = 0 to 5.25V, Vec = O.OV) ITSI VOH Logic Logic ~1, ~2 Min. Typ. Max. Unit VSS + 2.0 Vee - 0.6 - Vee Vee + 0.3 Vdc VSS + 0.8 VSS + 0.4 Vdc VSS - 0.3 Vss - 0.3 - - ~dc Three-State (Off State) Input Current VIN = 0.4 to2.4V, VCC = Max Logic'" - 1.0 ~1, ~2 - - DO - D7 AO - A15,R/W - 2.0 - 10 100 VSS + 2.4 VSS + 2.4 VSS + 2.4 - - 2.5 100 Vdc Output High VoJtage (ILOAD = 205~dc, Vcc = Min) (ILOAO = 145~dc, Vee = Min) (ILOAO = - 100~dc, Vce = Min) DO - D7 AO - A15,R/W, VMA BA VOL Output Low Voltage (ILOAO 51.6mAdc, Vee = Min) - - VSS + 0.4 Po Power Dissipation - 0.5 1.0 CIN Capacitance# (V IN = 0, T A = 25°C, f COUT f tCYC = 1.0MHz) ~1 ~2 Frequency of Operation tUT Total ~1 and ~2 - - - - 10 6.5 - 0.1 0.1 0.1 S6800 S68AOO 868BOO 1.000 0.666 0.50 - 86800 S68AOO S68BOO S6800 S68AOO S68BOO 400 230 800 900 600 440 Rise and Fall Times ~ 1, ~2 ~1, ~2 ~1, ~2 - Up Time t+r, t+f - S6800 S68AOO S68BOO Clock Timing (Figure 1) Cycle Time Clock Pulse Width Measured at Vee - 0.6V Vdc W pF DO -D7 Logic Inputs AO - A15, R/W, VMA PW+H ~dc - - - 35 70 12.5 10 12 1.0 1.5 2.0 10 10 10 pF MHz /-IS 9500 9500 9500 ns ns - - ns - - - - 5.0 - 100 ns 0 - 9100 ns Measured between VSS + 0.4 and Vee - 0.6 Delay Time or Clock Separation td Measured at VOV = Vss + 0.6V *Except IRQ and NMI, Which require KQ pullup load resistor for wire-OR capability at optimum operation. #Capacitances are periodically sampled rather than 100% tested. 5.4 AMII~ S6800/S68AOO/S68BOO Read/Write Timing Symbol tAO S68AOO 868800 Min Typ Max Min Typ Max Min Typ Max - 270 250 - - - - - 180 165 - - 150 135 - - 530 - - 360 - - 250 ns Address Delay Unit ns C C t ACC S6800 Characteristics = = 90pF 30pF Periph. Read Access Time tAC = tUT - (tAO + t oSR ) tOSR Data Setup Time (Read) 100 - - - 40 - - ns Input Data Hold Time 10 - - 60 tH 10 - - 10 - - ns tH Output Data Hold Time 10 25 - 10 25 - 10 25 - ns tAH Address Hold Time (Address, R/W, VMA) 30 50 - 10 75 - 10 75 - ns tEH Enable High Time for DBEInput 450 - - 280 - - 220 - - ns toow Date Delay Time (Write) - - 225 - 165 200 - - 160 ns 200 - - 200 - - 200 - - ns - - - 100 270 40 270 - - 100 250 270 - - - - - 100 270 40 270 ns ns ns ns 150 - - 150 - - 70 - - ns - - 25 - - 25 - - 25 ns tpcs tPCr;tPCf tBA t TSE t TSO tOBE tOBEr' tOBEf Processor Controls Proc. Control Setup Time Processor Control Rise and Fall Time Bus Available Delay Three-State Enable Three-State Delay Data Bus Enable Down Time During t1 Up Time Data Bus Enable Rise and Fall Times - - - Measurement point for ¢I and ¢2 are shown below. Oth~r measurements are the same as for MC6800. 1 - - - - - - - - - - 'eve--l /StartofCYCI. 'Of 01 \Ill Vcc - 0.6 V 0.4 V -tr Figure 1. Clock Timing Waveform Figure2.Read/WriteTimingWaveform 5.5 Please contact your local AMI Sales Office for complete data sheet ~II~ 56800/568AOO/568BOO ¢1 ------------~rl r---------------~ Vee - D.3V ¢2 f-=..-~~.;..I_------------------------....,H_~rn 2.4V RIW -----------+~~~~ ADDRESS:=====~~~~~~~~=============~~~~ FROM MPU VMA .~ DATA FROM _ _ _ _ _ _ _ _ _ _ _~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___;;~2.D~V~~~:~~1l~ MEMORY OR PERIPHERALS 0.8 V DATA NOT VALID Figure 3. Read Data From Memory or Peripherals ¢1 ______________ ~ ¢2 D.4V -r----="""4-------+----------+---- RIW ADDRESS -----------2'iiv=~~;::-_::::;,.j...--------t_----------~~:;:::_ D.4V 2.4V FROM MPU _ _ _ _ _ _ _..!!!!;;;;;~~~~~=------+__--------~~~~ D.4V -+::::.2~~~-------t------------+-~~ 2.4V VMA DATA FROM MPU DBE ~ 0 ---------t----------t~~~~t~~~~~~ ¢2 _ _ _ _ _ _ _ _--,. DATA NOT VALID Figure4. Write Data In Memory or Peripherals ,<1'" 1 _ _ _- - _2~1 Reset VMA ~------ ? 8 Clock Times --IIIt-- ------.~I V22?22d?22????????????????????????????"~ Address Out = FFFE _I_ -I- d I Address Out = Contents of FFFE + FFFF Address Out = FFFF Figure 5. Initialization of MPU After Restart 5.6 First Instruction Loaded into MPU S68HOO 8-81T HIGH SPEED MICROPROCESSOR Features o o Eight-Bit Parallel Processing OBi-Directional Data Bus o Sixteen-Bit Address Bus - 65536 Bytes of Addressing o 72 Instructions - Variable Length o Seven Addressing Modes - Direct, Relative Immediate, Indexed, Extended, Implied and Accumulator o Variable Length Stack o Vectored Restart o 400nsec Instruction Execution Maskable Interrupt Vector o Separate Non-Maskable Interrupt - Internal Registers Saved in Stack o Six Internal Registers - Two Accumulators, Index o o o o Register, Program Counter, Stack Pointer and Condition Code Register Direct Memory Access (DMA) and Multiple Processor Capability Clock Rate 2.5MHz Simple Bus Interface Without TTL Halt and Single Instruction Execution Capability Pin Configuration Block Diagram DATA Vee (361 DBE GND (331 DO 1321 01 1311 02 1301 (291 04 1281 05 RESET rna NM~I '1,1 HALT VMA 8A R/W (271 06 1401 1261 141 161 131 (371 121 (51 (71 (341 1391 TSC A15 A14 A13 A12 All AID A9 A8 A7 A6 A5 A4 A3 A2 Al AD 5.7 07 GNo HALT 1. 40 39 el ilrn VMA NMI BA Vee AO Al A2 A3 A4 A5 A6 A7 A8 A9 Al0 All 38 37 4 5 36 RESET TSC _2 oBE 35 10 11 12 13 14 15 16 17 18 19 20 S68HOO 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RIW DO 01 02 03 04 05 06 07 A15 A14 A13 A12 GNo S68HOO Absolute Maximum Ratings Supply Voltage Vcc .................................................................... -0.3 to + 7.0V Input Voltage VIN .•.•.............................................•................. -0.3V to + 7.0V Operating Temperature Range TA ........................................................ O°C to + 70°C StorageTemperatureRangeTstg ..................................................... -55°Cto+150°C Electrical Characteristics (Vcc =5.0V, ±5%, Vss =0, TA unless otherwise noted.) Symbol Characteristics VIH VIHe Input High Voltage (Normal Operating Levels) VIL VILe Input Low Voltage (Normal Operating Levels) lIN Input Leakage Current (YIN =0 to 5.25V, Vee =Max) (YIN =0 to 5.25V, Vee =O.OV) Logic ~1, ~2 Logic ~1, ~2 Min. Typ. Max. Unit VSS +2.0 Vee -0.6 - Vee Vee +0.3 Vdc VSS +0.8 Vss +0.4 Vdc VSS -0.3 Vss -0.3 - /lAde Logic· - ~1, ~2 - - DO-D7 AO-A15,R/W - 2.0 - 10 100 VSS +2.4 VSS +2.4 VSS +2.4 - - Output Low Voltage (I LOAD = 1.6mAdc, Vee = Min) - - VSS +0.4 PD Power Dissipation - 0.5 1.0 CIN Capacitance # (VIN =0, TA =25°C, f =1.0MHz) ITSI VOH VOL Three-State (Off State) Input Current VIN =0.4 to 2.4V, Vee =Max Output High Voltage (I LOAD = 205/lAdc, Vee = Min) (lLOAD = 145/lAdc, Vee =Min) (lLOAD =-100/lAdc, Vee = Min) 1.0 2.5 100 /lAdc Vdc DO-D7 AO - A15, R/W, VMA BA Vdc W pF ~1 ~2 DO-D7 Logic Inputs AO - A15, R/W, VMA - - - - - 10 6.5 - 35 70 12.5 10 12 pF 2.5 MHz COUT f Frequency of Operation S68HOO 0.1 teye Clock Timing (Figure 1) Cycle Time S68HOO 0.4 - PW,H Clock Pulse Width Measured at Vee - 0.6V - S68HOO 165 tUT Total ~1 and S68HOO 4.20 - Rise and Fall Times 5.0 - 0 - 9100 ns t,r' t,f td ~2 ~1, ~2 - Up Time Measured between Vss +0.4 and Vee -0.6 Delay Time or Clock Separation Measured at VOV = Vss + 0.6V *Except IRQ and NMI, Which require KQ pullup load resistor for wire-OR capability at optimum operation. #Capacitances are periodically sampled rather than 100% tested. 5.8 10 10 /lS 9500 9500 ns ns - ns 100 ns AMII~ Please contact your local AMI Sales Office for complete data sheet S68HOO Read/Write Timing Symbol Characteristics tAD Address Delay Min Typ Max - - Unit ns C =90pF C =30pF - - 140 125 t ACC Periph. Read Access Time tAC=tUT-(tAD+tDSR) - - 235 ns t DSR Data Setup Time (Read) 35 - - ns tH Input Data Hold Time 10 - - ns tH Output Data Hold Time 10 25 - ns - ns 155 ns tAH Address Hold Time (Address, R/W, VMA) 10 75 tEH Enable High Time for DBE Input 205 - tDDW Date Delay Time (Write) - 165 200 - - - - 100 270 40 270 t pcs tPCr;tPCf tBA trSE trSD GmE t DBEr , Processor Controls Proc. Control Setup Time Processor Control Rise and Fall Time Bus Available Delay Three-State Enable Three-State Delay Data Bus Enable Down Time During ~1 Up Time 65 - - ns ns ns ns ns ns - - 25 ns - Data Bus Enable Rise and Fall Times tDBEf ns - - Measurement point for ---1::: TO PERIPHERAL TO COUPLER CONTROL AS BITS 5. 6 ANO 7 OF PORT 2 ARE READ DNLY, THE MDDE CANNDT BE CHANGED THROUGH SOFTWARE. THE MODE SELECTIDNS ARE SHOWN IN TABLE 3. P20 REFERS TO PORT 2. BIT O. Mode Selection The mode of operation that 6801 will operate in after Reset is determined by hardware that the user must wire on pins 10,9, and 8 of the chip. These pins are the three Figure 15. Quad Analog, Switch/Multiplexer In a Typical S6801 Circuit LSB's (lI02, lI01, and lIOO respectively) of Port 2. They are latched into programmed control bits PC2, PC1, and PCO when reset goes high. lIO Port 2 Register is shown below. ~---ODUTnN MC14066B (1/4 OF DEVICE SHOWN) CONTROL 7 6 5 4 3 2 1 0 PC2 PCl PCO U04 U03 U02 UOl UOO $0003 An example of external hardware that could be used in the Expanded Non-Multiplexed Mode is given in Figure 14. In the Expanded Non-Multiplexed Mode, pins 10, 9 and 8 are programmed Hi, Lo, Hi respectively as shown. Couplers between the pins on Port 2 and the peripherals attached may be required. If the lines go to devices which require signals at power up differing from the signals needed to program the 6801' s mode, couplers are necessary. The 14066B can be used to provide this isolation between the peripheral device and the MCV during reset. Figure 15 shows the logic diagram and xxxxx? for the MC14066B. It is bidrectional and requires no external logic to determine the direction of the information flow. 5.20 7414 RESET _----t TO 14066B CONTROL INPUTS 56801/56801 E 56801 Basic Modes The S6801 is capable of operating n three basic modes, (1) Single Chip Mode, (2) Expanded Multiplexed Mode (compatible with S6800 peripheral family, (3) Expanded Non-Multiplexed Mode. Single Chip Mode Both mask options will operate in this mode. In the Single Chip Mode the parts are configured for 110. tion is shown in Figure 16. In this mode, Port 3 has two associated control lines, an input strobe and an output strobe for handshaking data. External ClockIDivide-by-One (S6801E)- This mask option is shown in Figure 16a. The Read/Write (R/W) line, Chip Select (CS), and Register Select (RS) are associated with Port 3 only. The Read/Write (R/W) line controls the direction of data on Port 3 and Chip Select (CS) enables Port 3. The Register Select (RS) allows for the access of Port 3 data register or Port 3 control register. Internal ClockIDivide-by-Four (S6801)-This mask opFigure 16. 56801 MCU Single Chip Mode Figure 16a_ 56801 E MCU Single-Chip Mode Vee ENABLE ----oiiMi _REGISTERSElECT PORT1~ S6801 MCU S6801E MCU PORT 3 BVOUNES al/ouNES~ OUTPUT STROBE PORT 2 5 110 UNES UART (SERIAL I/O) TIMER PORT 4 al/OUNES _CHIPSELECT PORT 1 a I/O UNES PORT 3 PERIPHERAL DATA BUS PDRT4 ai/DUNES PORT 2 5 PARALLEl I/O SERIAL liD TIMER Vss VSS Expanded Non-Multiplexed Mode In this mode the S6801 will directly address S6800 peripherals with no external logic. In this mode Port 3 becomes the data bus. Port 4 becomes the A 7-AO address bus or partial address and 110 (inputs only). Port 2 can be parallel 110, serial only. In this mode the S6801 is expandable to 256 locations. The eight address lines associated with Port 4 may be substituted for 110 (inputs only) if a fewer number of address lines will satisfy the application. Internal ClockIDivide-by-Four-This mask option is shown in Figure 17. The Internal Clock requires only the addition of a crystal for operation. This input will also accept an external TTL or CMOS input, but in either case, the clock frequency will be divided by four for this mask option. External ClocklDivide-by-One- This mask option is shown in Figure 17a. The External ClockiDivide-by-One allows for an external clock to be applied to the Enable Pin. This is a divide-by-one input only. Expanded Multiplexed Mode In this mode Port 4 becomes higher order address lines with an alternative of substituting some of the address lines for 110 (inputs only). Port 3 is the data bus multiplexed with the lower order address lines differentiated by an output called Address Strobe. Port 2 is 5 lines of Parallel 110, SCI, Timer, or any combination thereof. Port 1 is 8 Parallel 110 lines. In this mode it is expandable to 65K words. 5.21 86801186801 E Internal ClockIDivide-by-Four-This mask option is shown in Figure 18. Only an external crystal is required for operation. External ClocklDivide-by-One- This mask option is shown in Figure 18a. This accepts an external clock input to the enable pin. Figure 17. S6801 MCU Expanded Non-Multiplexed Mode Figure 17a_ S6801 E MCU Expanded Non-Multiplexed-Mode Vee ENABLE _mo V"STANDBY _ _ _ PORT1~ PORT 3 B DATA LINES BPARAllELIIO~ PORT2<=) 5 PARALLEL 110 SERIAL 110 TIMER PORT 4 TOBADDRESS LINES OR TO 7110 LINES (INPUTS ONLYI L...-_.----' PORT 1 B PARA~LEL UOLINES PORT 3 MUXED OATAIAODRESS PORT 2 5 PARALLEL UO SERIAL VO TIMER PORT 4 ADDRESS BUS VSS VSS Figure 18. S6801 MCU Expanded Multiplexed Mode Figure 18a. S6801 E MCU Expanded Multiplexed-Mode Vee ENABLE PORT 1 BUOLINES PORT 3 BliNES MULTIPLEXEO OATAIADDRESS PORT 2 5UOLINES SERIAL UO TIMER PORT 4 BliNES ADDJlESS BUS Vss PORT 1 B PARALLEL VOLINES PORT 3 MUXED DATA/ADDRESS PORT 2 5 PARAllEL VD SERIAL VO TIMER PORT 4 ADDRESS BUS VSS 5.22 AMII~ S6801/S6801 E Table 3. Mode Selects MODE 7 PROGRAM CONTROL Single Chip Expanded Multiplexed Expanded Non-Multiplexed Single Chip Test 64K Address I/O Ports 3 & 4 External 6 5 4 3 Hi Hi Hi Hi Lo Lo Lo Lo Test Data Outputted from ROM & ROM to I/O Port 3 0 Hi Hi Lo Lo Hi Hi Lo Lo Hi Lo Hi Lo Hi Lo Hi Lo ROM RAM I I 1(2) E E I 1(1) E INTERRUPT VECTORS BUS E E E I' Ep/M Ep I Ep/M Ep/M Ep/M Ep/M * First two addresses read from external after reset (1) Address for RAM XX80-XXFF (2) ROM disabled E-EXTERNAL all vectors are external I-INTERNAL Ep-EXPANDED MULTIPLEXED Lower Order Address Bus Latches Since the data bus is multiplexed with the lower order address bus in Port 3, latches are required to latch those address bits. The SN74LS373 Transparent octal D-type latch can be used with the S6801 to latch the least significant address byte. Figure 19 shows how to connect the latch to the S6801. The output control to the LS373 may be connected to ground. Figure 19. Latch Connection GND AS I 0, PORT 3 ADDRESS/DATA G I DC 0, ADDRESS: Ao-A7 74LS373 08 08 OAT": 00-07 FUNcnDN TABLE OUTPUT CONTROL L L L H ENABLE 0 H H L X 0 H L X X OUTPUT 0 H L 00 Z 5.23 AMII~ 56801156801 E Programmable Timer The 86801 contains an on-chip 16-bit programmable timer which may be used to perform measurements on an input waveform while independently generating an output waveform. Pulse widths for both input and output signals may vary from a few microseconds to many seconds. The timer hardware consists of • an 8-bit control and status register • a 16-bit output compare register, and • a 16-bit free running counter • a 16-bit input capture register A block diagram of the timer registers is shown in Figure 20. Figure 20. Block Diagram of Timer Registers soal 7 6 ICF OCF TIMER CONTROL/STATUS REGISTER 4 3 2 5 TOF EICI EOCI ElOl SOB* OUTPUT COMPARE HIGH BYTE COUNTER OLVL OUTPUT COMPARE LOW BYTE SOA HIGH BYTE COUNTER SOD INPUT CAPTURE IEOG SOC S09 ~21 0 LOW BYTE SOE HIGH BYTE INPUT CAPTURE LOW BYTE "THE CHARACTERS ABOVE THE REGISTERS REPRESENT THEIR ADDRESS IN HEX. Free Running Counter ($0009:000A) The key element in the programmable timer is a I6-bit free running counter which is driven to increasing values by the MPU~. The counter value may be read by the MPU software at any time. The counter is cleared to zero on RESET and may be considered a read-only register with one exception. Any MPU write to the counter's address ($09) will always result in a preset value of $FFF8 being loaded into the counter regardless of the value involved in the write. The preset feature is intended for testing operation of the part, but may be of value in some applications. Output Compare Register ($OOOB:OOOC) The Output Compare Register is a I6-bit read/write register which is used to control an output waveform. The contents of this register are constantly compared with the current value of the free running counter. When a match is found a flag is set (OCF) in the Timer Control and Status Register (TCSR) and the current value of the Output Level bit (OLVL) in the TCSR is clocked to the output level register. Providing the Data Direction Register for Port 2, Bit 1 contains a "1" (output), the output level register value will appear on the pin for Port 2 Bit 1. The values in the Output Compare Register and Output level bit may then be changed to control the output level on the next compare value. The Output Compare Register is set to $FFFF during RESET. The Compare function is inhibited for one cycle following a write to the high byte of the Output Compare Register to insure a valid 16-bit value is in the register before a compare is made. Input Capture Register ($OOOD:OOOE) The Input Capture Register is a 16-bit read-only register used to store the current value of the free running counter when the proper transition of an external input signal occurs. This input transition change required to trigger the counter transfer is controlled by the input Edge bit (EDG) in the TOSR. The Data Direction Register bit for Port 1 Bit 0 should *be clear (zero) in order to gate in the external input signal to the edge defect unit in the timer. 5.24 86801186801 E *With Port 2 Bit 0 configured as an output and set to "1". the external input will still be seen by the edge detect unit. • a match has been found between the value in the free running counter and the output compare register, and • when $0000 is in the free running counter. Timer Control and Status Register (TCSR) ($0008) Each of the flags may be enabled onto the S6801 internal bus (R02) with an individual Enable bit in the tCSR. If the I-bit in the S6801 Condition Code Register has been cleared, a priority vectored interrupt will occur corresponding to the flag bit(s) set. A description for each bit follows: The Timer Control and Status Register consists of an 8-bit register of which all 8 bits are readable but only the low order 5 bits may be written. The upper three bits contain read-only timer status information and indicate that: • a proper transition has taken place on the input pin with a subsequent transfer of the current counter value to the input capture register. I TIMER CONTROL AND STATUS. REGISTER 7 6 5 4 3 2 ICF OCF TOF EICI EOCI ETOI o IEDG OlVl 1$0008 Bit OOLVL Output Level-This value is clocked to the output level register on an output compare. If the DDR for Port 2 bit 1 is set, the value will appear on the output pin. Bit 1 IEDG Input Edge-This bit controls which transition of an input will trigger a transfer of the counter to the input capture register. The DDR for Port 2 Bit 0 must be clear for this function to operate. IEDG = 0 Transfer takes place on a negative (high-to-Iow transition). IEDG = 1 Transfer takes place on a positive edge (low-to-high transition). Bit 2 ETOI Enable Timer Overflow Interrupt- When set, this bit enables IRQ2 to occur on the internal bus for a TOF Interrupt; when clear the interrupt is inhibited. Bit 3 EOCI Enable Output Compare Interrupt- When set, this bit enables IRQ2 to appear on the internal bus for an input capture interrupt; when clear the interrupt is inhibited. Bit 4 EICI Enable Input Capture Interrupt- When set, this bit enables IRQ2 to occur on the internal bus for an input capture interrupt; when clear the interrupt is inhibited. Bit 5 TOF Timer Overflow Flag-This read-only bit is set when the counter contains $0000. It is cleared by a read of the TCSR (with TOF set) followed by an MPU read of the Counter ($09). Bit 60CF Output Compare Flag-This read-only bit is set when a match is found between the output compare register and the free running counter. It is cleared by a read of the TCSR (with ODF set) followed by an MPU write to the output compare register ($OB or $OC). Bit 7 CF Input Capture Flag-This read-only status bit is set by a proper transition on the input to the edge detect unit; it is cleared by a read of the TCSR (with ICF set) followed by an MPU read of the input Capture Register ($OD). Serial Communications Interface The S6801 contains a full-duplex asynchronous serial communications interface (SCI) on board. Two serial data formats (standard mark/space (NRZ] or Bi-phase) are provided at several different data rates. The controller comprises a transmitter and a receiver which operate independently or each other but in the same data format and at the same data rate. Both transmitter and receiver communicate with the MPU via the data bus and with the outside world via pins 2, 3, and 4 of Port 2. The hardware, software, and registers are explained in the following paragraphs. Waka-up Feature In a typical multi-processor application, the software protocol will usually contain a destination address in the initial byte(s) of the message. In order to permit non- 5.25 5680116801 E selected MPU' s to ignore the remainder of the message, a wake-up feature is included whereby all further interrupt processing may be optionally inhibited until the beginning of the next message. When the next messge appears, the hardware re-enables (or "wakes-up") for the next message. The "wake-up" is automatically triggered by a string of ten consecutive l's which indicates an idle transmit line. The software protocol must provide for the short idle period between any two consecutive messages. • interrupt requests-enabled or masked indivually for transmitter and receiver data registers • clock output-internal clock enabled or disabled to Port 2 (Bit 2) • Port 2 (bits 3 and 4)-dedicated or not dedicated to serial I/O individually for transmitter and receiver Serial Communications Hardware The serial communications hardware is controlled by 4 registers as shown in Figure 21. The registers include: Programmable Options The following features of the 86801 serial I/O section have programmable: • • • • • format-standard mark/space (NRZ) or Bi-phase • clock-external or internal • baud rate-one of 14 per given MPU~2 an 8-bit control and status register a 4-bit rate and mode control register (write only) an 8-bit read-only receive data register and an 8-bit write-only transmit data register In addition to the four registers, the serial I/O section utilizes bit 3 (serial input) and bit 4 (serial output) or Port 2. Bit 2 of Port 2 is utilized if the internal-clock-out or external-clock-in options are selected. clock fre- quency or external clock X8 input • wake-up feature-enabled or disabled Figure 21. Serial 1/0 Registers CONTROL AND STATUS REGISTER $0011, READ/WRITE EXCEPT (READ ONLY) u· . 7 RDRF 6 5 4 3 2 ORFE TORE RIE RE TIE I I I o TE WU RATE AND MODE REGISTER $0010, WRITE ONLY X X X X CC1 CCO S1 SO PORT 2 BIT 3 BRX PORT 2 BIT 2 G EXT CLK INIINT CLK OUT (NOT USER ADDRESSABLE) PORT 2 BIT 4 ~~~~--~~--~~~~--~~--~--~~--~~ 5.26 AMite 5680116801 E Transmit/Receive Control and Status (TRCS) Register The TRCS register consists of an 8-bit register of which all 8 bits may be read while only bits 0-4 may be written. The register is initialized to $20 on RESET. The bits in the TRCS register are defined as follows: 7 6 5 4 3 2 ° ___ R_DR_E--'-_O_RF_E--'-_T_DR_E........._RIE_.&....-_RE_.&....-_TI_E........_TE____ w_u---'1 ADDR. $0011 BitOWU "Wake-up on Next Message-set by S6801 software cleared by hardware on receipt of ten consecutive l' s. Bit 1 TE Transmit Enable-set by S6801 to produce preamble of nine consecutive l's and to enable gating of transmitter output to Port 2, bit 4 regardless of the DDR value corresponding to this bit; when clear, serial 110 has no effect on Port 2 bit 4. Bit 2 TIE Transmit Interrupt Enable-when set, will permit an IRQ2 interrupt to occur when bit 5 (TDRE) is set; when clear, the TDRE value is masked from the bus. Bit 3 RE Receiver Enable-when set, gates Port 2 bit 3 to input of receiver regardless of DDR value for this bit; when clear, serial 110 has no effect on Port 2 bit 3. Bit 4 RIE Receiver Interrupt Enable-when set, will permit an IRQ2 interrupt to occur when bit 7 (RDRF) or bit 6 (OR) is set; when clear, the interrupt is masked. Bit 5 TDRE Transmit Data Register Empty-set by hardware when a transfer is made from the transmit data register to the output shift register. The TDRE bit is cleared by reading the status register, then writing a new byte into the transmit data register, TDRE is initialized to 1 by RESET. Bit 6 ORFE Over-Run-Framing Error-set by hardware when an overrun or framing error occurs (receive only). An overrun is defined as a new byte received with last byte still in Data Register/Buffer. A framing error has occured when the byte boundaries in bit stream are not synchronized to bit counter. The ORFE bit is cleared by reading the status register, then reading the Receive Data Register, or by RESET. Bit 7 RDRF Receiver Data Register Full-set by hardware when a transfer from the input shift register to the receiver data register is made. The RDRF bit is cleared by reading the status register, then reading the Receive Data Register, or by RESET. Rate and Mode Control Register The Rate and Mode Control register controls the following serial 110 variables: • Baud rate • format • Clocking source, and • Port 2 bit 2 configuration The register consists of 4 bits all of which are write-only and cleared on RESET. The 4 bits in the register may be considered as a pair of 2-bit fields. The two low order bits control the bit rate for internal clocking and the remaining two bits control the format and clock select logic. The register definition is as follows: 7 6 54320 ---II ADDR. $0010 ,--_X_.L..-_X_.L..-_X_.L.-_X_.L.-C_C_1--L._C_C_0--L._8_1---,-_8_0 5.27 • AMII~ S6801 IS6801 E Bit 0 SO Bit 1 Sl Speed Select-These bits select the Baud rate for the internal clock. The four rates which may be selected are a function of the MPU ~2 clock frequency. Table 4 lists the available Baud rate. Bit 2 CCO Bit 3 CCI Clock Control and Fonnat Select- This 2-bit field controls the format and clock select logic. Table 5 defines the bit field. Table 4. SCI Internal Baud Rates Sl, SO 00 01 10 11 XTAL 4.0MHz 4.9152MHz 2.5476MHz ~2 1.0MHz 62.5K 8ITS/S 7,812.58ITS/S 976.6 8ITS/S 244.1 8ITS/S 1.2288MHz 76.8K 8ITS/S 9,600 8ITS/S 1,200 8ITS/S 300 8ITS/S 0.6144MHz 38.4K 8ITS/S 4,800 8ITS/S 600 8ITS/S 150 8ITS/S ~2 ~2 -;.-16 -;.-128 ~2-;.-1024 ~2 -;.- 4096 Table 5. Bit Field CC1, CCO FORMAT CLOCK SOURCE PORT 2 BIT 2 PORT 2 BIT 3 PORT 2 BIT 4 00 01 10 11 81-PHASE NRZ NRZ NRZ INTERNAL INTERNAL INTERNAL EXTERNAL NOT USED NOT USED OUTPUT* INPUT ** ** SERIAL INPUT SERIAL INPUT ** ** SERIAL OUTPUT SERIAL OUTPUT *CLOCK OUTPUT IS AVAILABLE REGARDLESS OF VALUES FOR BITS RE AND TE. **BIT 3 IS USED FOR SERIAL INPUT IF RE= "1" IN TRCS; BIT 4 IS USED FOR SERIAL OUTPUT IF TE= "1" IN TRCS. Serial Operations Internally Generated Clock If the user wishes for the serial 110 to furnish a clock, the following requirements are applicable: • the values of RE and TE are immaterial • CC1, CCO must be set to 10 • the maximum clock rate will be cp -:-16 • the clock will be at 1 X the bit rate and will have a rising edge at mid-bit Externally Generated Clock If the user wishes to provide an external clock for the serial 110, the following requirements are applicable: • the CC1, CCO, field in the Rate and Mode Control Register must be set to 11. • the external clock must be set to 8 times (X8) the desired baud rate and • the maximum external clock frequency is 1.2MHz. The Serial 110 hardware should be initialized by the S6801 software prior to operation. This sequence will normally consist of: • writing the desired operation control bits to the Rate and Mode Control Register and • writing the desired operational control bits in the Transmit/Receive Control and Status Register. The Transmitter Enable (TE) and Receiver Enable (RE) bits may be left set for dedicated operations. Transmit Operations The transmit operation is enabled by the TE bit in the Transmit/Receive Control and Status Register. This bit when set, gates the output of the serial transmit shift register to Port 2 Bit 4 and takes unconditional control 5.28 8680116801 E over the Data Direction Register value for Port 2, Bit 4. Following a RESET, the user should configure both the Rate and Mode Control Register and the Transmit/ Receiver Control and Status Register for desired operation. Setting the TE bit during this procedure initiates the serial output by first transmitting a ten-bit preamble of l's. Following the preamble, internal synchronization is established and the transmitter section is ready for operation. At this point one of two situations exist: a) if the Transmit Data Register is empty (TDRE = 1), a continuous string of ones will be sent indicating an idle line, or b) if data has been loaded into the Transmit Data Register (TDRE=O), the word is transferred to the output shift register and transmission of the data word will begin. During the transfer itself, the 0 start bit is first transmitted. Then the 8 data bits (beginning with bit 0) followed by the stop bit, are transmitted. When the Transmitter Data Register has been emptied, the hardware sets the TDRE flag bit. If the S6801 fails to respond to the flag within the proper time, (TDRE is still set when the next normal transfer from the parallel data register to the serial output register should occur) then a 1 will be sent (instead of a 0) at "Start" bit time, followed by morel's until more data is supplied to the data register. No O's will be sent while TDRE remains a l. The Bi-phase mode operates as described above except that the serial output toggles each bit time, and on 112 bit times when a 1 is sent. Receive Operation The receive operation is enabled by the RE bit which gates in the serial input through Port 2 Bit 3. The receiver section operation is conditioned by the contents of the Transmit/Receive Control and Status Register and the Rate and Mode Control Register. The receiver bit interval is divided into 8 sub-intervals for internal synchronization. In the standard, non-Bi-phase mode, the received bit stream is synchronized by the first o (space) encountered. The approximate center of each bit time is strobed during the next 10 bits. If the tenth bit is not a 1 (stop bit) a framing error is assumed, and bit ORFE is set. If the tenth bit is 1, the data is transferred to the Receiver Data Register, and interrupt flag RDRF is set. If RDRF is still set at the next tenth bit time, ORFE will be set, indica- ting an over-run has occurred. When the S6801 responds to either flag (RDRF or ORFE) by reading the status register followed by reading the Data Register RDRF (or oRFE) will be cleared. Ram Control Register This register, which is addressed at $0014, gives status information about the standby RAM. A 0 in the RAM enable bit (RAM E) will disable the standby RAM, thereby protecting it at power down if Vee is held greater than V SBB volts, as explained previously in the signal description for Vee Standby. I Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Not used. Not used. Not used. Not used. Not used The RAM ENABLE control bit allows the user the ability to disable the standby RAM. This bit is set to a logic "one" by reset which enables the standby RAM and can be written to or zero under program control. When the RAM is disabled, logic "zero", data is read from external memory. Bit 7 The STANDBY BIT of the control register, $0014, is cleared when the standby voltage is removed. This bit is a read/write status flag that the user can read which indicates that the standby RAM voltage has been applied, and the data in the standby RAM is valid. The S6801 provides up to 65K bytes of memory for program and/or data storage. The memory map is shown in Figure 22. Locations $0020 through $007F access external RAM or I/O Internal RAM is accessed at $0080 through $OOFF. The RAM may be alternately selected by mask programming at location $AOOO. However, if the user desires to access external RAM at those locations he may do so by clearing the RAM ENABLE cont~ol bit of the RAM Control Register. In this wayan extrp 126 bytes of external RAM are available. The first 64 bytes of the 128 bytes of on-chip RAM are provided with a separate power supply. This will maintain the 64 bytes of RAM in the power down mode as explained in the pin description for Vee Standby. 5.29 AMII~ , 56801/6801 E The first 32 bytes are for the special purpose registers as shown in Table 6. Figure 22. Memory Map Table 6. Special Registers soooo I' i ] SOO1F I I SPECIAL PURPOSE REGISTER I I : ] I EXTERNAL RAMORVD I , ....------~I S0020 S007F I S0080 , ! ! ~M"" , ] : • I I som I I I $0200 : I , I I I SF7FF I: SF800 I I SFFFF I I 00 01 02 03 04 05 06 07 08 09 OA OB OC OD OE OF 10 11 12 13 14 15-1 F RESERVED I ] I SOOFF , S0100 " • ! HEX ADDRESS I EXTERNAL RAM OR VO FOR NON·MUl TlPLEXED MODE !1 1 I I I I EXTERNAL RAM OR ROM OR VO II : I I , INTERNAL ROM OR EROM . Locations $0100 through $OlFF are available in the Expanded Non-Multiplexed Mode. The eight address lines of Port 4 make this 256 word expandability possible. Those not needed for address lines can be used as input lines instead. The full range of addresses available to the user is in the Expanded Multiplexed Mode. Locations $0200 through $F7FF can be used as external RAM, external ROM, or lIO. Any higher order bit not required for addressing can be used as lIO as in the Expanded Non-Multiplexed Mode. The internal ROM is located at $F800 through $FFFF. The decoder for the ROM may be mask programmed on A12, and A13 as zeros or one's to provide for $C800, $D800, $E800 for the ROM address. A12 and A13 may also be don't care in this decoder. The primary address for the ROM will be $F800. 5.30 REGISTER DATA DIRECTION 1 DATA DIRECTION 2 I/O PORT 1 I/O PORT 2 DATA DIRECTION 3 DATA DIRECTION 4 I/O PORT 3 I/O PORT 4 TCSR COUNTER HIGH BYTE COUNTER LOW BYTE OUTPUT COMPARE HIGH BYTE OUTPUT COMPARE LOW BYTE INPUT CAPTURE HIGH BYTE INPUT CAPTURE LOW BYTE I/O PORT 3 CIS REGISTER SERIAL RATE AND MODE REGISTER SERIAL CONTROL AND STATUS REGISTER SERIAL RECEIVER DATA REGISTER SERIAL TRANSMIT DATA REGISTER RAM/EROM CONTROL REGISTER Figure 23. Memory Map for Interrupt Vectors VECTOR Highest Priority Lowest Priority DESCRIPnON MS LS FFFE, FFFF FFFC, FFFA, FFFD FFFD FFF8, FFF9 IRQ111ntenupt Strobe S FFF6, FFF7 IRQ2JTimer Input Capture FFF4, FFF5 IRQ2JTimer Output Compare FFF2, FFF3 IRQ2ffimer Ovelflow FFFO, FFF1 IRQ2JSeriaIIlO Intenupt Restart Non-Maskable Intenupt Software Intenupt 86801/86801 E General Description of Instruction Set The 86801 is upward object code compatible with the 86800 as it implements the full 86800 instruction set. The execution times of key instructions have been reduced to increase throughput. In addition, new instructions have been added; these include 16-bit operations and a hardware multiply. Included in the instruction set section are the following: • • • • • • • • MPU Programming Model (Figure 24) Addressing modes Accumulator and memory instructions- Table 7 New instructions Index register and stack manipulations-Table 8 Jump and branch instructions-Table 9 8pecial operations- Figure 25 Condition code register manipulation instructionsTable 10 • Instruction Execution times in machine cyclesTable 11 • 8ummary of cycle by cycle operation-Table 12 MPU Programming Model The programming model for the 86801 is shown in Figure 24. The double (D) accumulator is physically the same as the A Accumulator concatenated with the B Accumulator so that any operation using accumulator D will destroy information in A and B. Figure 24. MCU Programming Model o 7 I I I 15 ACCA 7 II ACCD IX 15 PC ACCUMULATOR B ACCUMULATOR 0 I INDEX REGISTER I I PROGRAM COUNTER 0 15 I I I 0 0 15 I 0 ACCB SP STACK POINTER 0 CONDITION CODE C REGISTER CARRY (from Bit 7) OVERFLOW ZERO NEGATIVE INTERRUPT MASK HALF CARRY (from Bit 3) MPU Addressing Modes The 86801 eight-bit microcomputer unit has seven address modes that can be used by a programmer, with the addressing mode a function of both the type of instruction and the coding within the instruction. A summary of the addressing modes for a particular instruction can be found in Table 11 along with the associated instruction execution time that is given in machine cycles. With a clock frequency of 4MHz, these times would be microseconds. Accumulator (ACCX) Addressing- In accumulator only addressing, either accumulator A or accumulator B is specified. These are one-byte instructions. Immediate Addressing- In immediate addressing, the operand is contained in the second byte of the instruction except LD8 and LDX which have the operand in the second and third bytes of the instruction. The M CU addresses this location when it fetches the immediate instruction for execution. These are two or three-byte instructions. Direct Addressing- In direct addressing, the address of the operand is contained in the second byte of the instruction. Direct addressing allows the user to directly address the lowest 256 bytes in the machine Le., locations zero through 255. Enhanced execution times are achieved by storing data in these locations. In most configurations, it should be a random access memory. These are two-byte instructions. Extended Addressing- In extended addressing, the address contained in the second byte of the instruction is used as the higher eight-bits of the address of the operand. The third byte of the instruction is used as the lower eightbits of the address for the operand. This is an absolute address in memory. These are three-byte instructions. Indexed Addressing - In indexed addressing, the address contained in the second byte of the instruction is added to the index register's lowest eight bits in the MCU. The carry is then added to the higher order eight bits of the index register. This result is then used to address memory. The modified address is held in a temporary address register so there is no change to the index register. These are two-byte instructions. Implied Addressing - In the implied addressing mode the instruction gives the address (Le., stack pointer, index register, etc.). These are one-byte instructions. Relative Addressing- In relative addressing, the address contained in the second byte of the instruction is added to the program counter's lowest eight bits plus two. The carry or borrow is then added to the high eight bits. This allows the user to address data within a range of -125 to + 120 bytes of the present instruction. These are two-byte instructions. 5.31 86801186801 E Table 7. Accumulator & Memory Instructions ACCUMULATOR AND MEMORY Operations IMMED. MNEMONIC OP n.J ADDRESSING MODES DIRECT INDEX EXTEND INHERENT # OP n.J # OP n.J # OP n.J # OP n.J # 5 4 321 0 Booleanl Arithmetic Operation ADDA 8B 2 2 9B 3 2 AB 4 2 BB 4 3 A+M-A ADDB CB 2 2 DB 3 2 EB 4 2 FB 4 3 B+M-B ADD DOUBLE ADDD C3 4 3 D3 5 2 E3 6 2 F3 6 3 ADD ACCUMULATORS ABA ADD WITH CARRY ADCA 89 2 2 99 3 2 A9 4 2 B9 4 3 A+ M +C-A ADCB C9 2 2 D9 3 2 E9 4 2 F9 4 3 B+M+C-B ANDA 84 2 2 94 3 2 A4 4 2 B4 4 3 A M-A ANDB C4 2 2 D4 3 2 E4 4 2 F4 4 3 BM-B BIT A 85 2 2 95 3 2 A5 4 2 B5 4 3 AM BIT B C5 2 2 D5 3 2 E5 4 BM ADD AND BIT TEST CLEAR COMPARE COMPARE ACCUMULATORS COMPLEMENT, 1'S 2 F5 4 3 CLRA 4F 2 1 00 -A CLRB 5F 2 1 00 -B CMPA 81 2 2 91 3 2 A1 4 2 B1 4 3 A-M CMPB C1 2 2 D1 3 2 E1 4 2 F1 4 3 B- M 11 2 1 CBA 63 6 COM A-A COMB 53 2 1 B-B NEGA 60 6 OC- M-M 2 70 6 3 40 2 1 50 2 1 NEGB 19 2 1 DAA 4A 2 1 5A 2 1 DECB OO-A-A 00 - B-B A-1-A B-1-B EORA 88 2 2 98 3 2 A8 4 2 B8 4 3 AEBM-A EORB C8 2 2 D8 3 2 E8 4 2 F8 4 3 BEBM-B 2 7C 6 3 M + 1-M INC 9C 6 INCA 4C 2 1 A+1-A INCB 5C 2 1 B+1-B LDAA 86 2 2 96 3 2 A6 4 2 B6 4 3 M-A LDAB C6 2 2 D6 3 2 E6 4 M-B LOAD DOUBLE ACCUMULATOR LDAD CC 3 3 DC 4 2 EC 5 2 FC 5 3 MULTIPLY UNSIGNED MUL OR, INCLUSIVE ORAA 8A 2 2 9A 3 2 AA 4 2 BA 4 3 A+ M-A ORAB CA 2 2 DA 3 2 EA 4 2 FA 4 3 B + M-B LOAD ACCUMULATOR 2 F6 4 3 M+A M+1-B 3D 10 1 The Condition Code Register notes are listed after Table 10. 5.32 ·· · ·· · · ·· ·· ·· ·· ·· ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ Ax B-AB ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ R ~ ~ R ~ ~ R ~ ~ R · · · · R S R R ·· ·· ·· ·· ··t t t t ·· ·· ·· ·· ·· CD R S R R R S R R ·· Converts binary add of BCD characters into BCD • format M -1-M 6A 6 2 7A 6 3 DEC DECA INCREMENT M-M 2 73 6 3 43 2 1 (NEGATE) EXCLUSIVE OR A-B COMA NEG DECREMENT A+B-A 00 -M 6F 6 2 7F 6 3 CLR COMPLEMENT, 2'S DECIMAL ADJUST, A A:B+ M:M + 1-A:B 1B 2 1 H I N Z V C ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ R S ~ ~ R S ~ ~ R S ~ ~CD ~ ~ ~ ~CD ® ® ® · · · t tt Zero BGT 2E 4 2 Z+(NEllV)=O Branch If Higher BHI 22 4 2 C+Z=O Branch If.,,;Zero BlE 2F 4 2 Z + (N Ell V) = 1 Branch If lower Or Same BlS 23 4 2 C+Z=1 Branch If< Zero BLT 2D 4 2 NEllV=1 Branch If Minus BMI 28 4 2 N=1 Branch If Not Equal Zero BNE 20 4 2 Z=O Branch If Overflow Clear BVC 28 4 2 V=O Branch If Overflow Set BVS 29 4 2 V=1 2 N=O f\J f\J f\J f\J BRANCH TEST 2 Branch If Plus BPl 2A 4 Branch To Subroutine BSR 8D 8 2 Jump JMP 6E 4 2 7E 3 3 Jump To Subroutine JSR AD 8 2 8D 9 3 No Operation NOP 01 Retu rn From Interru pt RTI 3B 10 1 H I N Z V C · · · · ·· · See Special Operations 2 1 Return From Subroutine RTS 39 5 1 Software Interrupt SWI 3F 12 1 Wait For Interrupt* WAI 3E 9 1 Advances Prog. Cntr. Only ···· · ··· ·· ··· ··· ··· ··· ·· ··· ·· ·· ·· ·· · ·· ·· · ·· ·· ·· · · ·· · · ··· ·· ·· ··· ··· ·· ·· ··· ··· ·· ·· ··· ··· ··· ··· ··· ··· ··· ······ ··· ·· .·· ··· ··· ·· ---@--- See Special Operations ~ · Table 10. Condition Code Register Manipulation Instructions CONDo CODE REG. 5 4 3 2 1 0 IMPLIED OPERATIONS CONDITION CODE 1 (Bit V) 2 (Bit C) 3 (Bit C) (Bit V) (Bit V) (Bit V) MNEMONIC OP f\J BOOLEAN OPERATION # Clear Carry ClC OC 2 1 O-C Clear Interrupt Mask Cli OE 2 1 0-1 Clear Overflow ClV OA 2 1 O-V Set Carry SEC OD 2 1 1-C Set Interrupt Mask SEI OF 2 1-1 1 Set Overflow SEV OB 2 1 1-V Accumulator A-CCR TAP 06 2 1 A-CCR CCR-Accumulator A TPA 07 2 CCR-A REGISTER NOTES: (Bit set if test is true and cleared otherwise)" Test Result = 100000007 Test Result = 000000007 Test: Decimal value of most significant BCD Character greater than nine? (Not cleared if previously set.) Test: Operand = 10000000 prior to execution? Test: Operand = 01111111 prior "to execution? Test: Set equal to result of NeC after shift has occurred. 1 10 (Bit N) (Bit V) (Bit N) (All) 11 (Bit I) 12 (All) 5.35 H I N Z V C ·· · ·· ·· ·· · R R ·· ·· ·· ·· · · · ···· ·- -· @ · · - -· R S S S ·1·1·1·1·1· Test: Sign Bit of most significant (MS) byte = 17 Test: 2's complement overflow from subtraction of MS bytes7 Test: Result less than zer07 (Bit 15 = 1) load Condition Code Register from Stack. (See Special Operations) Set when interrupt occurs. If previously set, a Non-Maskable Interrupt as required to exit the wait state. Set according to the contents of Accumulator A. 86801/86801 E Figure 25. Special Operations JSR, JUMP TO SUBROUTINE: MAIN PROGRAM F AO INOXD ~ JSR K = OFFSET* n+2 NEXT MAIN INSTR. e) ~ --"SP-2 SP -1 MAIN PROGRAM F SL = SUBR. ADDR. n+3 NEXT MAIN INSTR. e) ± K = OFFSET* n+2 NEXT MAIN INSTR. 1ST. SUBR. INSTR. STACK (n + 3) H SP -1 (n + 3) l SP (S FORMED FROM ~ e) f~ STACK n+2'K ~SP-2 n + 2 FORMED FROM (n + 2)H AND (n + 2)l F n K = OFFSET EXTENDED NEXT INSTRUCTION Ie) ~ SP SP + 1 - - . . SP+2 ~ i'::~R::''' PROGRAM r PC MAIN PROGRAM RTI. RETURN FROM INTERRUPT: SUBROUTINE 1ST. SUBR. INSTR. SP 6E = JMP RTS, RETURN FROM SUBROUTINE: SUBROUTINE ~ 39 = RTS AND SL) SP -1 JMP, JUMP; X+K ~ AFTER EXECUTION *K = ].8IT SIGNEO VALUE: INOXD SUBROUTINE -= STACK POINTER BSR, BRANCH TO SUBROUTINE: MAIN PROGRAM ~ 80 = BSR n+1 ~ S SUBROUTINE (n + 2) L ~ - - - . SP-2 SH = SUBR. ADDR. 1ST. SUBR. INSTR. (n+2)H AND (n +2)l FORMn +2 BD = JSR n+2 ~ INX + K (n + 2) H SP *K = 8·BIT UNSIGNED VALUE EXTND STACK Ie) ~ SP SP + 1 SP + 2 SP +3 SP +4 SP + 5 SP + 6 ____ SP+7 STACK SUBROUTINE 7E = JMP n+l KH = NEXT AODRESS n+: Kl = NEXT ADDRESS ~ NEXT INSTRUCTION MAIN PROGRAM NEXT MAIN INSTR. I:: STACK MAIN PROGRAM NEXT MAIN INSTR. CONOITION CODE ACMLTR B ACMLTR A INDEX REGISTER (XH) INDEX REGISTER (XL! NH Nl 5.36 ~II~ 86801186801 E Table 11. Instruction Execution Times in Machine Cycle UJ l- >< Co) Co) cc ABA ABX ADC ADD ADDD AND ASL ASLD ASR BCC BCS BEQ BGE BGT BHI BIT BLE BLS BLT BMI BNE BPL BRA BSR BVC BVS CBA CLC CLI CLR CLV CMP COM CPX DAA DEC DES DEX EaR INC INS ~ UJ ~ iI ICo) = i!5 11.1 CI UJ CI Z CI UJ UJ I- >< 11.1 11.1 iii!: >< CI I- Z 11.1 iii!: cc >< Co) 11.1 Co) -' 3 4 2 3 3 5 3 4 4 6 4 6 4 4 6 4 6 6 6 • 3 3 3 3 3 3 3 3 4 4 3 3 3 3 3 3 3 6 3 3 3 4 2 5 6 6 4 6 6 4 6 6 6 6 4 6 4 6 • 3 2 UJ I- UJ > 1= = = = UJ 3 cc INX JMP JSR LDA LDD LDS LDX LSR LSRD MUL NEG Nap ORA PSH PSHX PUL PULX ROL ROR RTI RTS SBA SBC SEC SEI SEV STA STD STS STX SUB SUBD SWI TAB TAP TBA TPA TST TSX TXS WAI 5.37 ~ UJ t; iI ~ CI UJ CI Z CI IoU = 11.1 >< 11.1 is >< 11.1 iii!: 5 3 4 4 4 3 6 4 5 5 5 6 3 6 4 5 5 5 6 11.1 I- CI !Z IoU UJ > 1= = = = 11.1 iii!: cc -' UJ 3 3 3 3 3 10 2 3 6 6 4 4 3 4 4 0 2 6 6 6 6 10 6 2 3 4 4 2 2 4 4 3 4 4 4 5 4 5 5 5 6 6 4 5 6 • 6 6 12 6 6 2 3 9 AMII~ 86801/86801 E Summary of Cycle by Cycle Operation Table 12 provides a detailed description of the information present on the Address Bus, Data Bus, and the Read/Write line (R/W) during each cycle for each instruction. This information is useful in comparing actual with expected results during debug of both software and hardware as the control program is executed. The information is categorized in groups according to addressing mode and number of cycles per instruction. (In general, instructions with the same addressing mode and number of cycles execute in the same manner; exceptions are indicated in the table). Table 12. Cycle by Cycle Operation ADDRESS MODE & INSTRUCTIONS CYCLE # ADDRESS BUS DATA BUS IMMEDIATE ADC EOR ADD LDA AND ORA BIT SBC CMP SUB 2 1 2 OP CODE ADDRESS OP CODE ADDRESS + 1 1 1 OP CODE OPERAND DATA LOS LOX 3 1 2 3 OP CODE ADDRESS OP CODE ADDRESS + 1 OP CODE ADDRESS + 2 1 1 1 OP CODE OPERAND DATA (High Order Byte) OPERAND DATA (Low Order Byte) CPX SUBD ADDD 4 1 2 3 4 OP CODE ADDRESS OP CODE ADDRESS + 1 OP CODE ADDRESS + 2 ADDRESS BUS FFFF 1 1 1 1 OP CODE OPERAND DATA (High Order Byte) OPERAND DATA (Low Order Byte) LOW BYTE OF REST ART VECTOR ADC EOR ADD LOA AND ORA BIT SBC CMP SUB 3 1 2 3 OP CODE ADDRESS OP CODE ADDRESS + 1 ADDRESS OF OPERAND 1 1 1 OP CODE ADDRESS OF OPERAND OPERAND DATA STA 3 1 2 3 OP CODE ADDRESS OP CODE ADDRESS + 1 DESTINATION ADDRESS 1 1 0 OP CODE DESTINATION ADDRESS DATA FROM ACCUMULATOR LOS LOX LDD 4 1 3 4 OP CODE ADDRESS OP CODE ADDRESS + 1 ADDRESS OF OPERAND OPERAND ADDRESS + 1 1 1 1 1 OP CODE ADDRESS OF OPERAND OPERAND DATA (High Order Byte) OPERAND DATA (Low Order Byte) STS STX STD 4 1 2 3 4 OP CODE ADDRESS OP CODE ADDRESS + 1 ADDRESS OF OPERAND ADDRESS OF OPERAND + 1 1 1 0 0 OP CODE ADDRESS OF OPERAND REGISTER DATA (High Order Byte) REGISTER DATA (Low Order Byte) CPX SUBD ADDD 5 1 2 3 4 5 OP CODE ADDRESS OP CODE ADDRESS + 1 OPERAND ADDRESS OPERAND ADDRESS + 1 ADDRESS BUS FFFF 1 1 1 1 1 OP CODE ADDRESS OF OPERAND OPERAND DATA (High Order Byte) OPERAND DATA (Low Order Byte) LOW BYTE OF RESTART VECTOR JSR 5 1 2 3 4 5 OP CODE ADDRESS OP CODE ADDRESS + 1 SUBROUTINE ADDRESS STACK POINTER STACK POINTER + 1 1 1 1 0 0 OP CODE IRRELEVANT DATA FIRST SUBROUTINE OP CODE RETURN ADDRESS (High Order Byte) RETURN ADDRESS (Low Order Byte) DIRECT 2 (continued) 5.38 86801186801 E Table 12. Cycle by Cycle Operation (continued) ADDRESS MODE & INSTRUCTIONS ADDRESS BUS DATA BUS INDEXED JMP 3 1 2 3 OP CODE ADDRESS OP CODE ADDRESS + 1 ADDRESS BUS FFFF 1 1 1 OP CODE OFFSET LOW BYTE OF RESTART VECTOR ADC EOR ADD LDA AND ORA BIT SBC CMP SUB 4 1 2 3 4 OP CODE ADDRESS OP CODE ADDRESS + 1 ADDRESS BUS FFFF INDEX REGISTER PLUS OFFSET 1 1 1 1 OP CODE OFFSET LOW BYTE OF RESTART VECTOR OPERAND DATA STA 4 1 2 3 4 OP CODE ADDRESS OP CODE ADDRESS + 1 ADDRESS BUS FFFF INDEX REGISTER PLUS OFFSET 1 1 1 0 OP CODE OFFSET LOW BYTE OF RESTART VECTOR OPERAND DATA LDS LDX LDD 5 1 2 3 4 5 OP CODE ADDRESS OP CODE ADDRESS + 1 ADDRESS BUS FFFF INDEX REGISTER PLUS OFFSET INDEX REGISTER + 1 1 1 1 1 1 OP CODE OFFSET LOW BYTE OF RESTART VECTOR OPERAND DATA (High Order Byte) OPERAND DATA (Low Order Byte) STS STX STD 5 1 2 3 4 5 OP CODE ADDRESS OP CODE ADDRESS + 1 ADDRESS BUS FFFF INDEX REGISTER PLUS OFFSET INDEX REGISTER PLUS OFFSET 1 1 1 0 0 OP CODE OFFSET LOW BYTE OF RESTART VECTOR OPERAND DATA (High Order Byte) OPERAND DATA (Low Order Byte) ASL LSR ASR NEG CLR ROL COM ROR DEC TST (1) INC 6 1 2 3 4 5 6 OP CODE ADDRESS OP CODE ADDRESS + 1 ADDRESS BUS FFFF INDEX REGISTER PLUS OFFSET ADDRESS BUS FFFF INDEX REGISTER PLUS OFFSET 1 1 1 1 1 0 OP CODE OFFSET LOW BYTE OF RESTART VECTOR CURRENT OPERAND DATA CURRENT OPERAND DATA NEW OPERAND DATA CPX SUBD ADDD 6 1 2 3 4 5 6 OP CODE ADDRESS OP CODE ADDRESS + 1 ADDRESS BUS FFFF INDEX REGISTER + OFFSET INDEX REGISTER + OFFSET ADDRESS BUS FFFF 1 1 1 1 1 OP CODE OFFSET LOW BYTE OF RESTART VECTOR OPERAND DATA (High Order Byte) OPERAND DATA (Low Order Byte) LOW BYTE OF RESTART VECTOR JSR 6 1 2 3 4 5 6 OP CODE ADDRESS OP CODE ADDRESS + 1 ADDRESS BUS FFFF INDEX REGISTER + OFFSET STACK POINTER STACK POINTER + 1 1 1 1 1 0 OP CODE OFFSET LOW BYTE OF RESTART VECTOR FIRST SUBROUTINE OP CODE RETURN ADDRESS (Low Order Byte RETURN ADDRESS (High Order Byte) 1 2 3 OP CODE ADDRESS OP CODE ADDRESS + 1 OP CODE ADDRESS 1 1 1 OP CODE JUMP ADDRESS (High Order Byte) JUMP ADDRESS (Low Order Byte) 0 EXTENDED JMP 3 (continued) 5.39 56801156801 E Table 12. Cycle by Cycle Operation (continued) ADDRESS MODE" INSTRUCTIONS ADDRESS BUS DATA BUS EXTENDED ADC EOR ADD LOA AND ORA BIT SBC CMP SUB 4 1 2 3 4 OP CODE ADDRESS OP CODE ADDRESS + 1 OP CODE ADDRESS + 2 ADDRESS OF OPERAND 1 1 1 1 OP CODE ADDRESS OF OPERAND ADDRESS OF OPERAND (Low Order Byte) OPERAND DATA STA A STA B 4 1 2 3 4 OP CODE ADDRESS OP CODE ADDRESS + 1 OP CODE ADDRESS + 2 OPERAND DESTINATION ADDRESS 1 1 1 0 OP CODE DESTINATION ADDRESS (High Order Byte) DESTINATION ADDRESS (Low Order Byte) DATA FROM THE ACCUMULATOR LOS LOX LDD 5 1 2 3 4 5 OP CODE ADDRESS OP CODE ADDRESS + 1 OP CODE ADDRESS + 2 ADDRESS OF OPERAND ADDRESS OF OPERAND + 1 1 1 1 1 1 OP CODE ADDRESS ADDRESS OPERAND OPERAND OF OPERAND (High Order Byte) OF OPERAND (Low Order Byte) DATA (High Order Byte) DATA (Low Order Byte) STS STX STD 5 1 2 3 4 5 OP CODE ADDRESS OP CODE ADDRESS + 1 OP CODE ADDRESS + 2 ADDRESS OF OPERAND ADDRESS OF OPERAND 1 1 1 0 0 OP CODE ADDRESS ADDRESS OPERAND OPERAND OF OPERAND (High Order Byte) OF OPERAND (Low Order Byte) DATA (High Order Byte) DATA (Low Order Byte) ASL LSR ASR NEG CLR ROL COM ROR DEC TST (1) INC 6 1 2 3 4 5 6 OP CODE ADDRESS OP CODE ADDRESS + 1 OP CODE ADDRESS + 2 ADDRESS OF OPERAND ADDRESS BUS FFFF ADDRESS OF OPERAND 1 1 1 1 1 0 OP CODE ADDRESS OF OPERAND (High Order Byte) ADDRESS OF OPERAND (Low Order Byte) CURRENT OPERAND DATA LOW BYTE OF RESTART VECTOR NEW OPERAND DATA CPX SUBD ADDD 6 1 2 3 4 5 6 OP CODE ADDRESS OP CODE ADDRESS + 1 OP CODE ADDRESS + 2 OPERAND ADDRESS OPERAND ADDRESS + 1 ADDRESS BUS FFFF 1 1 1 1 1 OP CODE OPERAND ADDRESS OPERAND ADDRESS (Low Order Byte) OPERAND DATA (High Order Byte) OPERAND DATA (Low Order Byte) LOW BYTE OF RESTART VECTOR JSR 6 1 2 OP CODE ADDRESS OP CODE ADDRESS + 1 1 1 3 OP CODE ADDRESS + 2 1 4 5 6 SUBROUTINE STARTING ADDRESS STACK POINTER STACK POINTER - 1 1 0 0 OP CODE ADDRESS OF SUBROUTINE (High Order Byte) ADDRESS OF SUBROUTINE (High Order Byte) OP CODE OF NEXT INSTRUCTION RETURN ADDRESS (Low Order Byte ADDRESS OF OPERAND (High Order Byte) 1 2 OP CODE ADDRESS OP CODE ADDRESS + 1 1 1 OP CODE OP CODE OF NEXT INSTRUCTION INHERENT ABA DAA SEC ASL DEC SEI ASR INC SEV CBA LSR TAB CLC NEG TAP CLI NOP TBA CLR ROL TPA CLV ROR TST COM SBA 2 (continued) 5.40 AMII~ 56801156801 E Table 12. Cycle by Cycle Operation (continued) ADDRESS MODE & INSTRUCTIONS ADDRESS BUS DATA BUS INHERENT ABX 3 1 2 3 OP CODE ADDRESS OP CODE ADDRESS + 1 ADDRESS BUS FFFF 1 1 1 OP CODE IRRELEVANT DATA LOW BYTE OF RESTART VECTOR ASLD LSRD 3 1 2 3 OP CODE ADDRESS OP CODE ADDRESS + 1 ADDRESS BUS FFFF 1 1 1 OP CODE IRRELEVANT DATA LOW BYTE OF RESTART VECTOR DES INS 3 1 2 3 OP CODE ADDRESS OP CODE ADDRESS + 1 PREVIOUS REGISTER CONTENTS 1 1 1 OP CODE OP CODE OF NEXT INSTRUCTION IRRELEVANT DATA INX DEX 3 1 2 3 OP CODE ADDRESS OP CODE ADDRESS + 1 ADDRESS BUS FFFF 1 1 1 OP CODE OP CODE OF NEXT INSTRUCTION LOW BYTE OF REST ART VECTOR PSHA PSHB 3 1 2 3 OP CODE ADDRESS OP CODE ADDRESS + 1 STACK POINTER 1 1 0 OP CODE OP CODE OF NEXT INSTRUCTION ACCUMULATOR DATA ISX 3 1 2 3 OP CODE ADDRESS OP CODE ADDRESS + 1 STACK POINTER 1 1 1 OP CODE OP CODE OF NEXT INSTRUCTION IRRELEVANT DATA TXS 3 1 2 3 OP CODE ADDRESS OP CODE ADDRESS + 1 ADDRESS BUS FFFF 1 1 1 OP CODE OP CODE OF NEXT INSTRUCTION LOW BYTE OF REST ART VECTOR PULA PULB 4 1 2 3 4 OP CODE ADDRESS OP CODE ADDRESS + 1 STACK POINTER STACK POINTER 1 1 1 1 OP CODE OP CODE OF NEXT INSTRUCTION IRRELEVANT DATA PSHX 4 1 2 3 4 OP CODE ADDRESS OP CODE ADDRESS + 1 STACK POINTER STACK POINTER-1 1 1 0 0 OP CODE IRRELEVANT DATA INDEX REGISTER (Low Order Byte) INDEX REGISTER (High Order Byte) PULX 5 1 2 3 4 5 OP CODE ADDRESS OP CODE ADDRESS + 1 STACK POINTER STACK POINTER + 1 STACK POINTER + 2 1 1 1 1 1 OP CODE IRRELEVANT DATA IRRELEVANT DATA INDEX REGISTER (High Order Byte) INDEX REGISTER (Low Order Byte) BCC BCS BEQ BGE BGT 3 1 2 3 OP CODE ADDRESS OP CODE ADDRESS + 1 ADDRESS BUS FFFF 1 1 1 OP CODE BRANCH OFFSET LOW BYTE OF RESTART VECTOR 6 1 2 3 4 5 6 OP CODE ADDRESS OP CODE ADDRESS + 1 ADDRESS BUS FFFF SUBROUTINE STARTING ADDRESS STACK POINTER STACK POINTER-1 1 1 1 1 0 0 OP CODE BRANCH OFFSET LOW BYTE OF REST ART VECTOR RETURN ADDRESS (Low Order Byte) RETURN ADDRESS (Low Order Byte) RETURN ADDRESS (High Order Byte) BSR BHT BNE BLE BPL BLS BRA BLT BVC BMT BVS 5.41 AMII~ S68011S6801 E Figure 26. S6801 E MCU Single-Chip Mode EXTERNAL OSCILLATOR ENABLE MAIN MICROPROCESSOR ~~ V 16 ~ 8 V ~ V ~ PORT 4 ADDRESS BUS RANDOM ACCESS MEMORY PERIPHERAL INTERFACE ADAPTER S6801E PERIPHERAL PROCESSOR PORT 3 DATA BUS Figure 27. S6801 MCU Single-Chip Dual Processor Configuration Vee Vee ENABLE CJ ENABLE c:::J fIMI fIRl Vee STANDBY PORT 1 8 PARALLEL UO S6801 MCU PORT 1 8 PARALLEL UO PORT 3 DATA TRANSFER LINES PORT 3 HANDSHAKE LINES PORT 2 8 PARALLEL UO PORT 4 8 PARALLEL UD Vss Vss 5.42 AMII~ 86801/86801 E Figure 30. S6801 E Expanded Non-Multiplexed Mode Figure 28. S6801 MCU Expanded Non-Multiplexed Mode EXTERNAL OSCILLATOR S6801 MCU ENABLE S6801E MCU ~ ENABLE ~~ RANDOM ACCESS MEMORY 8 8 -V ~ RAM PERIPHERAL INTERFACE ADAPTER -V ~ GENERAL PURPOSE INTERFACE ADAPTER ADDRESS BUS -V ~ DATA BUS ADDRESS BUS 5.43 DATA BUS PIA GPiA 86801186801 E Figure 31. 56801 MCU Expanded I Multiplexed Mode Figure 31. 56801 E Expanded Multiplexed Mode ROM ROM RAM RAM PIA PIA GPIA GPIA PTM PTM ADDRESS BUS DATA BUS ADDRESS BUS 5.44 DATA BUS 86801/86801 E Table 13. Mode and Port Summary MCU .- = CICI MODE PORT 1 PORT 2 Eight lines Five lines SCl SC2 I/O I/O I/O I/O XTAL1(I) XTAL2(1) IS3(0) OS3(0) EXPANDED MUX I/O I/O ADDRESS BUS (AD-A?) DATA BUS (00-07) ADDRESS BUS* (A8-A15) XTAL1(1) XTAL2(1) AS(O) R/W(O) EXPANDED NON-MUX I/O I/O DATA BUS (00-07) ADDRESS BUS* (AO-A7) XTAL 1(I) XTAL2(1) 10S(0) R/W(O) SINGLE CHIP I/O I/O DATA BUS (00-07) I/O R/W(I) RSO(I) CS3(1) OS3(0) EXPANDED MUX I/O I/O ADDRESS BUS (AD-A?) DATA BUS (00-07) ADDRESS BUS* (A8-A15) HALT(I) BA(O) AS(O) R/W(O) EXPANDED NON-MUX I/O I/O DATA BUS (00-07) ADDRESS BUS* (AD-A?) HALT(I) BA(O) 10S(0) R/W(O) CI.) = CICI CD PORT 4 Eight lines SINGLE CHIP u:I w .- PORT 3 Eight lines CI.) "These lines can be substituted for I/O (Input Only) starting with the most significant address line. 1=lnput 0= Output BA = Bus Available R/W = Read/Write CC = Crystal Control IS=lnput Strobe OS = Output Strobe lOS = I/O Select CS = Chip Select AS = Address Strobe SC = Strobe Control 5.45 CCl CC2 S6802/S68A02 MICROPROCESSOR WITH CLOCK AND RAM Features General Description D On-Chip Clock Circuit The 86802/868A02 are monolithic 8 -bit microprocessors that contain all the registers and accumulators of the present 86800 plus an internal clock oscillator and driver on the same chip. In addition, the 86802/ 868A02 both have 128 bytes of RAM on board located at hex addresses 0000 to 007E. The first 32 bytes of RAM, at addresses 0000 to 001F, may be retained in a low power mode by utilizing Vee standby, thus facilitating memory retention during a power-down situation. The S6802/868A02 are completely software compatible with the 86800 as well as the entire 86800 family of parts. Hence, the S6802/868A02 are expandable to 65K words. When the 86802 is interfaced with the 86846 ROM - I/O - Timer chip, as shown in the Block Diagram below, a basic 2-chip microcomputer system is realized. D 128 x 8 Bit On-Chip RAM D 32 Bytes of RAM Are Retainable D Software-Compatible with the S6800 D Expandable to 65K Words D Standard TTL-Compatible Inputs and Outputs D 8-Bit Word 8ize D 16-Bit Memory Addressing D Interrupt Capability D Clock Rates: 86802 - 1.0MHz 868A02 - 1.5MHz Typical Microcomputer Block Diagram Pin Configuration 5.46 56802l568A02 Absolute Maximum Ratings Supply Voltage, Vee ................................................................. -0.3Vto +7.0V Input Voltage, VIN ................................................................... -0.3Vto + 7.0V Operating Temperature Range, TA ......................................................... 0° to +70°C Storage Temperature Range, Tstg ................................................... " -55°C to + 150 °C Thermal Resistance, eJA Plastic ................................................................................... 100 ° C/W Ceramic ................................................................................... 50 ° C/W This device contains circuitry to protect the inputs agains t damage due to high static voltageorelectnc fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. D.C. Electrical Characteristics (Vee = 5.0V ± 5%, Vss = 0, TA = O°C to +70°C unless otherwise noted.) Symbol Parameter Vrn Input High Voltage VIL Input Leakage Voltage Input Leakage Current (VIN = 0 to 5.25V, Vee = Max) Output High Voltage (ILOAD = - 2051lA, Vee = Min) (ILOAD = -145IlA, Vee = Min) (ILOAD = -100IlA, Vec = Min) Output Low Voltage (ILOAD = 1.6mA, Vee = Min) Power Dissipation Capacitance #= (VIN = 0, TA =25 ° C, f=1.0MHz lIN VOH VOL PD** CIN COUT Typ. Min. Logic, EXtal Reset Logic, EXtal, Reset Logic* Vss +2.0 Vss +4.0 Vss - 0.3 DO-D7 AO-AI5, R/W, VMA,E BA Vss +2.4 Vss +2A Vss +2.4 1.0 - Vce VCC Standby Standby IDD IDD RAM Standby Standby Vee Vee Vss + 0.8 2.5 - - DO-D7 Logic Inputs, EXtal AO - A15, R/W, VMA Max. - - - - Vss + 0.4 - Unit V V IlA V V V V V - 0.600 1.2 - 10 6.5 12.5 10 12 pF - W pF - - 4.0 - 5.25 V - - 8.0 rnA Clock Timing (Vec = 5.0V ± 5%, Vss = 0, TA = O°C to +70°C unless otherwise noted) Symbol Parameter Min. f fXtal tCYC PWHs PWrpL t Frequency of Operation Input Clock 74 Crystal Frequency Cycle Time Clock Pulse Width Measured at 2.4V Fall Time Measured between VSS + O.4V and VSS -2.4V 0.1 1.0 1.0 450 - - - S6802 Typ. Max. - Min. S68A02 Typ. Max. - MHz - - 25 ns - 0.1 1.0 1.0 300 - - 25 - - Unit 1.5 6.0 6.6 3000 1.0 4.0 10 4500 IlS ns *Except IRQ and NMI, which require- 3KD pull up load resistors for wire-OR capability at optimum operation. Does not include EXtal and Xtal, which are crystal inputs. **In power-down mode, maximum power dissipation is less than 40mW. tFCapacitances are periodically sampled rather than 100% tested. 5.47 AiMII. S6802lS68A02 Read/Write Timing (Figures 1 through 5; Load Circuit of Figure 3). (Vee = 5.0V ± 5%, VSS = 0, TA = O°C to +70°C unless otherwise noted.) Symbol Parameter Address Delay tAD S6802 Typ. Max. Min. C = 90pF C = 30pF Peripheral Read Access Time tACC tAC = tUT - (tAD + tDSR) Data Setup Time (Read) tDSR Input Data Hold Time tH Address Hold Time tAH (Address, R/W, VMA) Data Delay Time (Write) tDDW Processor Controls Processor Control tpcs Setup Time Processor Control tPCr;tPCf Rise and Fall Time 100 ~ 100 10 ADDRESS FROM MPU 2.4V O.4V 2.4V 20 200 ns ns 200 200 ns 100 ns '\ 2.4V .... O.4V r- -f+ ~~ c.-tAH ~ ~ _tAO_ .. ~ t ACC _tAO ......, _tH ~ Rl DATA VALID ~ ...... c* ~ DATA NOT VALID Figure 2. Write Data In Memory or Peripherals \ ~~ ~~~~C~,~ ~~ ~ ~ 2.2K ~~ R ~ 2.4V}~ ~ MM0615C OR EQUIV . ~ TEST POINT" I O.BV 4.75V . t OSR - 2.0V~ 0.4V 75 165 225 Figure 3. Bus Timing Test Load DATA FROM MPU OR PERIPHERALS E ns ns 10 165 ~ VMA ns 60 10 30 . - - - t AO '----'" RIW Unit ns 180 165 360 575 O.4V 2.4V S68A02 Typ. Max. 270 Figure 1. Read Data From Memory or Peripherals E Min. ~ _ t AO - R/W O.4V ~ -+- AOORESS FROM MPU 2.4V 0.4V ~ ~ _tAO_ 2.4V VMA ~ _tAO_ -- _toow ___1 2.4V~ DATA FROM MPU ""~~ I+-tAH DATA VALID 2.4V ~ DATA NOT VALID 5.48 ~ _t H ~ c = 130pF FOR 00 = 07. E 90pF FOR AO - AIS. RIW. 'ANO VMA 30pF FOR BA R = 11.7 KSl FOR 00 - 07. E = 16.SKSl FOR AD - A15. R/W. AND VMA = 24KSl FOR BA Please contact your local AMI Sales Office for complete data sheet AMII~ S6802lS68A02 Figure 4. Typical Data Bus Output Delay Versus Capacitive Loading Figure 5. Typical Read/Write, VMA, and Address Output Delay Versus Capacitive Loading 600 500 :!w =i= > ~ 400 600 10H = - 20S pA MAX @ 2.4V = 1.6mA MAX@0.4V -I OL -VCC= S.OV _TA = 2S'C 500 - -- 200 100 o ] :i5 - ---- -- (S6802, S68A02) 300 ~ ~ 400 10H = -145pAMAX@2.4V - i= 300 1.6mA MAX @ D.4V -.....--- > ~ 10 L = -V = S.OV CC _TA = 2S'C 200 100 ---- ......-- ~ ~ ;;....- 100 200 300 400 500 R/W -~ I JS680~, S68A02)- I I i I C INCLUDES STRAY CAPACITANCE L 600 100 200 CL • LOAD CAPACITANCE (pF) 400 300 500 CL LOAD CAPACITANCE (pF) Figure 6. S6802 Expanded Block Diagram A15 25 MEMORY READY A14 24 A13 23 A12 22 All 20 AID 19 A9 18 A8 17 3 ENABLE 37 RESET 40 NON·MASKABLE INTERRUPT 6 HALT 2 INTERRUPT REQUEST 4 EXTAL 39 XTAL 3B BUS AVAILABLE 7 VALID MEMORY ADDRESS 5 READiWRITE 34 Vee Vss = = PIN8.35 PIN 1. 21 26 07 27 06 28 05 29 04 - .... ADDRESS, VMA (S68A02) C INCLUDES STRAY CAPACITANCE L o ADDRESS, VMA ~ (S6802 ONL V) 30 03 31 02 5.49 32 01 33 00 A7 16 A6 15 A5 14 A4 13 A3 12 A2 11 Al 10 AD 9 600 PRELIMINARY DATA SHEET 56805 MICROCOMPUTER Features o Software o Hardware • • • • • • • • • • • • • • • • • • • • • • 8-Bit Architecture 64 Bytes RAM 1100 Bytes ROM 116 Bytes of Self Check ROM 28 Pin Package Memory Mapped I/O Internal8-Bit Timer with 7-Bit Prescaler Vectored Interrupts - External, Timer, Software, Reset 20 TTL/CMOS Compatible I/O Line 8 Lines LED Compatible On-Chip Clock Circuit Self-Check Capability Low Voltage Inhibit 5 Vdc Single Supply Similar to 6800 Byte Efficient Instruction Set Versatile Interrupt Handling True Bit Manipulation Bit Test and Branch Instruction Indexed Addressing for Tables Memory Usable as Registers/Flags 10 Addressing Modes Powerful Instruction Set All 6800 Arithmetic Instructions All 6800 Logical Instructions All 6800 Shift Instructions Single Instruction Memory Examine/Change Full Set of Conditional Branches Pin Configuration Block Diagram TIMER uo ACCUMU lATOR A 81 82 83 84 85 86 87 8 CPU CONTROL PORT A 110 LINES AD Al A2 A3 A4 A5 AS A7 PORT A REG DATA DIR REG INOEX REGISTER B X CONOITION CODE REGISTER CC PORT 8 110 LINES STACK POINTER 5 SP PROGRAM COUNTER HIGH 3 PCH CO Cl C2 C3 AlU PROGRAM COUNTER lOW PCl SELF CHECK ROM 5.50 PORT C 1/0 LINES Vss lImT iNT A7 Vee A6 XTl A5 EXTl A4 HUM A3 TIMER A2 CO Al Cl Ao C2 B7 C3 11& 11& B5 Bl B4 ~ B3 86805 General Description The S6805 is an 8-bit single chip microcomputer. It is the first member of the growing microcomputer family that contains a CPU, on-chip clock, ROM, RAM, 110 and timer. A basic feature of the 6805 is an instruction set very similar to the S6800 family of microprocessors. Although the 6805 is not strictly source nor object code compatible, an experienced 6800 user can easily write 6805 code. Also a 6805 user will have no trouble moving up to the 6801 or 6809 for more complex tasks. Absolute Maximum Ratings Supply Voltage, Vcc ................................................................. -0.3V to +7.0V Input Voltage, VIN .................................................................. -0.3V to +7.0V Operating Temperature Range, TA ........................................................ 0° to +70°C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +150°C Thermal Resistance, 8JA Plastic .................................................................................... 85 °C/W Ceramic ................................................................................... 50°C/W CerDIP ................................................................................... 51°C/W This device contains circuitry to protect the inputs against damage due to high static voltage or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that V IN and V OUT be constrained to the range Vss :S (V IN or V OUT) Vee Electrical Characteristics: Vcc= +5.25 Vdc±Vdc, Vss=GND, TA =00-70°C unless otherwise noted Symbol Min. Typ. Max. Unit Input High Voltage RESET 4.0 - VCC Vdc - 2.2 - Vss+2.0 Vss+2.0 - Input High Voltage Timer INT All Other Timer Mode Self-Check Mode - - 9.0 Vcc Vcc 15.0 Vdc Vdc Vdc Vdc V1L V1L V1L Input Low Voltage RESET VSS-0.3 - 0.8 Vdc - 2.0 - Vdc Vdc VH Pn CIN C1N LVR LVI INT Hysteresis Power Dissipation Input Capacitance VIR VIR VIR VIR VIR Characteristic INT All Other Vss-0.3 - Vss+0.8 - 100 350 20 10 - - EXTL All Other - Low Voltage Recover Low Voltage Inhibit - - - - 4.75 - 4.5 - mVcc mW pF pF Vdc Switching Characteristics: Vcc= +5.25 V±0.5 Vdc, Vss=GND, TA =00-70°C unless otherwise noted Symbol Min. Typ. 0.4 1.0 - tCYC Characteristic Clock Frequency Cycle Time tIWL INT Pulse Width tcyc+ 25O - tRWL tRHL RESET Pulse Width Delay Time Reset (External Cap. = 0.47f.1F) tCyc+ 25O 20 fcl 5.51 - Max. 4.0 10 Unit MHz f.1s - ns - - 50 - ns ms I AMII~ 86805 Port Electrical Characteristics: Vee = +5.25 Vdc±0.5 Vdc, Vss=GND, TA =oo-70°C unless otherwise noted Symbol Min. Characteristic Typ. Max. Unit Condition PortA VOL VOH VO H VIH Output Low Voltage - - 0.4 Vdc Output High Voltage 2.4 - - Vdc ILO AD = 1.6mAdc I LOAD = 100f-lAdc Output High Voltage 3.5 - - Vdc I LOAD = - 10f-lAdc Input High Voltage Vss+2.0 - Vee Vdc ILo AD = - 300f-lAdc (max) V1L Input Low Voltage Vs s -0.3 - Vss+0.8 Vdc ILOAD=-500/A-Adc (max) VOL Output Low Voltage - - 0.4 Vdc ILO AD = 3.2mAdc Port B VOL Output Low Voltage - - 1.0 Vdc ILO AD = 10mAdc(sink) VO H Output High Voltage 2.4 - - Vdc I LOAD = - 200/AAdc IOH Darlington Current Drive (Source) -1.0 - -10 mAdc VIH Input High Voltage Vee Vss+0.8 Vdc Input Low Voltage Vss +2.0 Vss-0.3 - V1L - Vo=1.5Vdc Vdc PortC VOL Output Low Voltage - - 0.4 Vdc VOH VIH Output High Voltage 2.4 - - Vdc Input High Voltage Vss+2.0 - V1L Input Low Voltage Vss-0.3 - Vee Vss+0.8 Vdc ILOAD = 1.6mAdc ILOAD = -100 /A-Adc Vdc Off·State Input Current IThree-State Ports B & C I 2 I 20 f-lAde Input Current I Timer at VIN=(OA to 2.4 Vdc) Figure 1. TTL Equiv. Test Load (Port B) TEST POINT mil veeR, I I Figure 2. CMOS Equiv. Test Load (Port A) _II MMD615D TEST POINT o~----'l 1 30 R .' ':' Figure 3. TTL Equiv. Test Load (Ports A and C) Vee VI e 20 ':' TEST POINT VI u" C=40pF, R=12K C :::JOpF,R:24K ADJUST Rl SO THAT II = 3.2mA ADJUST RL SO THAT II:: 1.6mA WITH VI • O.4V AND Vee' 5.2SV WITH VI" 0.4V AND Vee' S.2SV 5.52 I' 'I Rt MMD61S0 OR EQUIV. MM01000 ~ 56805 Pin Description Pin Symbol 1 and 3 Vee and Vss Power is supplied to the MCU using these two pins. Vee is 5.25V±.5V, and Vss is the ground connection. 2 INT External Interrupt provides capability to apply an external interrupt to the MCU. 4 and 5 XTL and EXTL Provide control input for the on-chip clock circuit. The use of crystal (at cut 4MHz maximum), a resistor or a wire jumper is sufficient to drive the internal oscillator with varying degrees of stability. (See Internal Oscillator Options for recommendations) An internal divide by 4 prescaler scales the frequency down to the appropriate ~2 clock rate (lMHz maximum). 6 NUM This pin is not for user application and should be connected to ground. 7 TIMER Allows an external input to be used to decrement the internal timer circuitry. See TIMER for detailed information about the timer circuitry. 8-11 12-19 20-27 CO-C3 BO-B7 AO-A7 Input/Output lines (AO-A7, BO-B7, CO-C3). The 20 lines are arranged into two 8-bit ports (A and B) and one 4-bit port (C). All lines are programmed as either inputs or outputs under software control of the data direction registers. See Inputs/Outputs for additional information. 28 RESET This pin allows resetting of the MCU. A low voltage detect feature responds to a dip in voltage by forcing a RESET condition to clear all Data Direction Registers, so that all I/O pins are set as inputs. Description Memory The MCU memory is configured as shown in Figure 4. During the processing of an interrupt, the contents of the MCU registers are pushed onto the stack in the order shown in Figure 5. Since the stack pointer decrements during pushes, the low order byte (PCL) of the program counter is stacked first, then the high order three bits Figure 4. MCU Memory Configuration 0 000 110 PORTS 255 256 959 960 (128 BYTES) PAGE ZERO ROM (128 BYTES) PORT A PORT 8 S07F S080 MAIN ROM (964 BYTES) 1923 1924 2047 INTERRUPT VECTORS ROM (8 BYTES) 1 PORTC NOT USED SOO4- :::\: S005- NOT USED IpORTCOOR S006- NOT USED S007 $lCO 9 S783 S7B4 63 64 10 S7F7 S7F8 TIMER DATA REG S008 TIMER CTRl REG S009 SODA NOT USED (54 BYTES) 12~\ RAM (64 BYTES) STACK 6 5 4 S003 PORT B DDR 5 7 S002 PORT A OOR SELF CHECK ROM (116 BYTES) 2039 2040 1 1 1 SOOO SOOl 4 SO F NOT USED ROM (704 BYTES) Figure 5. Interrupt Stacking Order 7 6 5 4 3 2 1 0 .000 TIMER RAM 127 12B (PCH) are stacked first, then the high order three bits (PCH) are stacked. This ensures that the program counter is loaded correctly as the stack pointer increments when it pulls data from the stack. A subroutine call will cause only the program counter (PCH, PCL) contents to be pushed onto the stack. .-4 1 1 2 1 I 0 PUll .+1 .-3 ACCUMULATOR .+2 .-2 INDEX REGISTER .+3 .-1 S03F $040 1 3 CONDITION CODE REGISTER 1 1 1 1 PCl- 1 I PCH- .+4 .+5 PUSH S07F *Forsubroutine calls, only PCH and pel are stacked *WRITE ONLY REGISTERS S7FF 5.53 • AMII~ 56805 to location $07F. Subroutines and interrupts may be nested down to location $061 which allows the programmer to use up to 15 levels of subroutine calls. A 16th subroutine call would save the return address correctly, but the stack pointer would not remain pointing into the stack area and there would be no way to return from any of the subroutines. Figure 6. Programming Model 0 7 A I I ACCUMULATOR 0 7 IINOEX REGISTER X I 10 I 0 PC IPROGRAM COUNTER 10 54 10 10 I 0 10 11 11 I SP Condition Code Register (CC) The condition code register is a 5-bit register in which each bit is used to indicate or flag the results of the instruction just executed. These bits can be individually tested by a program and specific action taken as a result of their state. Each individual condition code register bit is explained in the following paragraphs. I STACK POINTER I I I I I I H I N Z C CONOITION CODE REGISTER ~CARRY/BORROW ZERO HALF CARRY (H)- Used during arithmetic operations (ADD and ADC) to indicate that a carry occurred bet· ween bits 3 and 4. NEGATIVE INTERRUPT MASK HALF CARRY Registers The S6805 MCU contains two 8-bit registers (A and X), one ll·bit register (PC), two 5-bit registers (SP and CC) that are visible to the programmer (see Figure 6). Accumulator (A) The A'register is an 8·bit general purpose accumulator used for arithmetic calculations and data manipulation. Index Register (X) This 8·bit register is used for the indexed addressing mode. It provides an 8·bit address that may be added to an offset to create an effective address. The index register can also be used for limited calculations and data manipulations when using the read/modify/write instructions. In code sequences not employing the index register it can be used as a temporary storage area. Program Counter (PC) This II-bit register contains the address of the next in· struction to be executed. Stack Pointer (SP) The stack pointer is an II·bit register that contains the address of the next free location on the stack. Initially, the stack pointer is set to location $07F and is decre· mented as data is being pushed onto the stack and incremented as data is being pulled from the stack. The six most significant bits of the stack pointer are permanently set to 000011. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set INTERRUPT (I)-This bit is set to mask the timer and external interrupt (INT). If an interrupt occurs while this bit is set it is latched and will be processed as soon as the interrupt bit is reset. NEGATIVE (N)- USED TO INDICATE that the result of the last arithmetic, logical or data manipulation was negative (bit 7 in result equal to a logical one). ZERO (Z)- Used to indicate that the result of the last arithetic, logical or data manipulation was zero. CARRY/BORROW (C)- Used to indicate that a carry or borrow out of the arithmetic logic unit (ALU) occurred during the last arithmetic operation. This bit is also affected during bit test and branch instructions, shifts and rotates. Timer The MCU timer circuitry is shown in Figure 7. The 8-bit counter is loaded under program control and counts down toward zero as soon as the clock input is applied. When the timer reaches zero the timer interrupt request bit (bit 7) in the timer control register is set. The MCU redsponds to this interrupt by saving the present MCU state in the stack, fetching the timer interrupt vector from locations $7F8 and $7F9 and executing the interrupt routine. The timer interrupt can be masked by setting the timer interrupt mask bit (bit 6) in the timer control register. The interupt bit (bit 1) in the condition code register will also prevent a timer interrupt from being processed. The clock input to the timer can be from an external source applied to the TIMER input pin or it can be the internal t2 signal. Note that when ~2 signal is used as the source it can be gated by an input applied to the TIMER 5.54 AMII~ 86805 input pin allowing the user to easily perform pulse-width measurements. The source of the clock input is one of the options that has to be specified before manufacture of the MCV. A prescaler option can be applied to the clock input that extends the timing interval up to a maximum of 128 counts before being applied to the counter. This prescaling option must also be specified before manufacturing begins. The timer continues to count past zero and its present count can be monitored at any time by monitoring the timer data register. This allows a program to determine the length of time since a timer interrupt has occurred and not disturb the counting process. At power up or reset the prescaler and counter are initialized with all logical ones; the timer interrupt request bit (bit 7) is cleared and the timer request mask bit (bit 6) is set. Self Check Mode: The MCV includes a non-user mode pin that replaces the normal operating mode with one in which the internal data and address buses are available at the 110 ports. The ports are configured as follows in the test mode (some multiplexing of the address and data lines is necessary): • The internal ROM and RAM are disabled and Port A becomes the input data bus on the ~2 of the clock and can be used to supply instructions of data to the MCV. • Port B is also multiplexed. When ~ 2 is high, Port B is the output data bus, and when ~2 is low Port B is the address lines. The output data bus can be used to monitor the internal ROM or RAM. • Port C becomes the last three address lines and a read/write control line. The MCV incorporates a self test program within a 116 byte non-user accessable test program and some control logic on-chip. These 116 bytes of ROM test every addressing mode and nearly every CPV instruction (95% of the total microprocessor capability) while only adding 1% to the total overall die size. To perform the self test, the MCV output lines of Port A and B must be externally interconnected (Figure 7) and LED's are connected to Port C to provide both a pass/fail indication (3Hz square wave). The flowchart for the self test program (Figure 8) runs four tests: • 110 TEST: Tests for 110 lines that are stuck in high, low, shorted state, or are missing a connection. The 110 lines are all externally wired together so that the program can look for problems by testing for the correct operation of the lines as inputs and outputs and for shorts between two adjacent lines. • ROM ERROR: (Checksum wrong). The checksum value of the user program must be masked into the self check ROM when the microcomputer is built. The self check program then tests the user ROM by computing the checksum value, which should be equal to the masked checksum if all the bits in the ROM are properly masked. Address and data lines that are stuck high, low or to each other are also detected by this test. An inoperable ROM will (in most cases) prevent the running of the self check program. Figure 7. Timer Block Diagram r----., I I I TIMER I I I--'-'......----lf-+- INTERRUPT REO. I L ___ J 6 TIMER INTERRUPT MASK MANUFACTURING MASK OPTIONS TIMER WRITE 5.55 REAO CONT~OL REGISTER JtMII~ S6805 • RAM Bits Non-Functional: The RAM is tested by the use of a walking bit pattern that is written into memory and then verified. Every in RAM is set to one and then to zero by using 9 different patterns as shown in Figure 9. Figure 9. Flowchart of Self Test Routines Figure 8. Interconnected Ports for Self Check Mode. port C Gives GolNo Go and Diagnostic Information. 2 28 0.471lF * +9V 5 INT RESET XTAl 330S1 27 A6 26 A5 25 A4 24 A3 23 A2 22 4 EXTAl Al 21 7 TIMER AO 20 6 NUM 87 19 86 18 Vee 330S1 A7 8 CO 85 17 84 16 83 15 9 Cl 330S1 82 14 10 C2 81 13 330S1 11 C3 80 12 Vee= PIN 3 HALT PORT e~XX01 HALT PORT e~XX01 HALT PORT e~XX10 Vss= PIN 1 Self Test Routines Program performs four main tests in the major loops and provides an output signal to indicate that the part is functional. Interrupt Logic Failure: Using an 110 line the interrupt pin is toggled to create an interrupt. The main program runs long enough to allow the timer to underflow and causes the timer interrupt to be enabled. If all of these tests are successful the program, then loops back to the beginning and starts testing again. The self check program initially tries to get the MCU out of the reset state to indicate that the processor is at least working. The non-functional parts are thus immediately eliminated, and if the part fails at this first stage the program provides a means of determining the faulty section. HALT PORTC~XX11 To place the MCU in the self check mode the voltage on the timer input (Figure 7) is raised to 8 volts which causes several operations to take place: • The clocking source for the timer is shunted to the MCU internal clock to insure that the timer will run an underflow during the course of the program, no matter which clocking rate is masked. HALT • The address of the interrupt vectors (including the reset vector) are mapped into the self check ROM area. This allows the self check to test the interrupt structure. 5.56 PORTe~xxoo AMII~ 56805 The self check program is started by the reset signal instead of the normal program because the vectors (including the reset vector) have been overlaid. The self check program runs in an endless loop testing and retesting the processor as long as there are no errors. Signals on the 110 lines indicate that the test has passed, and if any test fails, the program stops by executing a branch to self instruction. The output lines then cease to toggle and two of the 110 lines will indicate the cause of failure. Figure 10. RAM Test Pattern PATIERN #1 o 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 BIT 0 o o o 0 0 0 1 o 1 1 0 0 0 0 0 0 0 0 0 1 0 o0 0 0 0 0 o1 o0 0 0 0 0 o0 1 0 0 0 0 0 o 0 o1 0 0 0 0 o0 5V OV RESET PIN INTERNAL RESET 5.57 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 o o 0 0 0 0 1 0 0 0 1 0 0 0 o 0 • • • • • 0 0 1 0 o 0 0 0 1 0 0 0 0 0 0 o 0 1 0 vee PATIERN #9 o o • • • 0 0 Figure 11. Power Up and Reset Timing 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 o 0 0 0 PATIERN #8 0 0 0 RAM ROM 0 1 • 0 0 REASON FOR FAILURE INTERRUPTS I/O PORTS A OR B 1 o • • • 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 Table 1. Cause of Chip Failure as Shown in Bits 0 and 1 of 110 Port C BIT 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 o 0 0 0 0 0 0 1 o 0 0 0 o 0 0 0 1 0 o0 1 0 • • • • RAM Test Pattern "Walking bit" patterns test sequence sets and resets every bit in memory. (See Figure 10.) Low Voltage Inhibit As soon as the voltage at pin 3 (Vee) falls to 4.5 volts, all 110 lines are put into a high impedance state. This prevents erroneous data from being given to an external device. When Vee climbs back up to 4.6 volts a vectored reset is performed. PATIERN #2 0 o o o 0 0 0 0 1 o 0 0 0 0 0 0 1 0 0 0 0 0 0 o 1 • 86805 Resets The MCU can be reset three ways; by the external reset input (RESET), by the internal low voltage detect circuit already mentioned, and during the power up time. (See Figure 11.) Figure 12. Power Up Reset Delay Circuit Upon power up, a minimum of 20 milliseconds is needed before allowing the reset input to go high. This time allows the internal oscillator to stabilize. Connecting a capacitor to the RESET input as shown in Figure 12 will provide sufficient delay. 22K 28 "* Internal Oscillator Options The internal oscillator circuit has been designed to require a minimum of external components. The use of a crystal (AT cut, 4MHz max) or a resistor is sufficient to drive the internal oscillator with varying degrees of stability. A manufacturing mask option is available to provide better matching between the external components and the internal oscillator. PART OF S6805 MCU Figure 13. Internal Oscillator Options CRYSTAL OPTIONS RESISTOR OPTIONS EXTAL 27pF (Recommended) EXTAL 0 * S6805 MCU XTAL XTAl S6805 MCU APPROXIMATEl Y 25% ACCURACY TYPICAL tCYC = 1.25!Js EXTERNAL JUMPER CRYSTAL +5V EXTAl EXTAl -= EXTERNAL CLOCK INPUT XTAl S6805 MCU NO CONNECTION EXTERNAL CLOCK XTAL S6805 MCU APPROXIMATELY 10% ACCURACY EXTERNAL RESISTOR 5.58 F NOTE: 0.47!JF = APPROXIMATEL Y 50 MILLISECOND DELAY The different connection methods are shown in Figure 13. Crystal specifications are given in Figure 14. A resistor selection graph is given in Figure 15. 4MHz MAX 0.47!J AMII~ 56805 A flowchart of the interrupt processing sequence is given in Figure 17. Figure 14. Crystal Parameters Table 1. Interrupt rriorities AT -CUT PARAllEL RESONANCE CRYSTAL Co~7pFMAX 1\ Vcc~5V TA~250C "" ~ 2.0 1.0 ~ r--..... ~ r---...... 10 15 20 25 30 35 40 AND AND AND AND $7FF $7FD $7FB $7F9 Figure 16. Typical Sinusodial Interrupt Circuits o o $7FE $7FC $7FA $7F8 There are 20 input/output pins. All pins are programmable as either inputs or outputs under software control of the data direction registers. When programmed as outputs, all 110 pins read latched output data regardless of the logic level at the output pin due to output loading (see Figure 18). When port B is programmed for outputs. it is capable of sinking 10 milliamperes on each pin (one volt maximum). All input/output lines are TTL compatible as both inputs and outputs. Port A lines are CMOS compatible as outputs while Port Band C lines are CMOS compatible as inputs. Figure 19 provides some examples of port connections. \ ~ 1 2 3 4 Vector Address Input/Output 5.0 3.0 RESET SWI TIMER Figure 15. Typical Resistor Selection Graph :IE Priority 1Nf FREQ~4.0MHz@C, ~24pF RS ~ 50 OHMS MAX 4.0 Interrupt 45 50 RESISTANCE (K OHMS) Interrupts The MCV can be interrupted three different ways; through the external interrupt (INT) input pin, the internal timer interrupt request, and a software interrupt instruction (SWI). When any interrupt occurs, processing is suspended, the present MCV state is pushed onto the stack, the interrupt bit (I) in the condition code register is set, the address ofthe interrupt routine is obtained from the appropriate interrupt vector address, and the interrupt routine is executed. The interrupt service routines normally end with a return from interrupt (RTI) instruction which allows the MCV to resume processing of the program prior to the interrupt. Table 1 provides a listing of the interrupts, their priority, and the vector address that contain the starting address of the appropriate interrupt routine. A sinusodial signal (1kHz maximum) can be used to generate an external interrupt (INT) as shown in Figure 16. 5.59 2to~ PEAK-TO-PEAK (1kHz MAX) AC INPUT (1kH' MAX) INT S6805 MCU 1f1F Y ~V~\I"---e--_--I ~ INT S6805 MCU 86805 Figure 17. Interrupt Processing Flowchart 1-1 7F-SP O-ooR's CLR INT LOGIC FF-TiMER 7F- PRESCALER 7F-TCR Figure 18. Typical Port I/O Circuitry DATA DIRECTION REGISTER BIT 5.60 OUTPUT DATA BIT OUTPUT STATE INPUT TO MCU 0 1 3-STATE PIN 56805 Figure 19. Typical Port Connections AD •• • • • ~ IC=HFE·1a •• ••• PORTA 2N6386 (TYPICAL) PORTB A7 B7 PORT A PROGRAMMED AS OUTPUT(S) DRIVING CMOS AND TIL LOAD DIRECTLY (8) PORT B PROGRAMMED AS OUTPUT(S) DRIVING DARLINGTON BASE DlRECTL Y (b) +V +v CO R • ~). PORTB ••• •• •• •• PORTC lOrnA MAX MC14049/14069 CMOS INVERTER (TYPICAL) C3 ....... - PORT C PROGRAMMED AS OUTPUT(S) DRIVIltG CMOS USING EXTERNAL PULL·UP RESISTORS (0) PORT B PROGRAMMED AS DUTPUT(S) DRIVING LED(s) DlRECTL Y (c) Bit Manipulation The MCU has the ability to set or clear any single random access memory or input/output bit (except the data direction registers) with a single instruction (BSET, BCLR). Any bit in the page zero read only memory can be tested, using the BRSET and BRCLR instructions, and the program branches as a result of its state. This capability to work with any bit in RAM, ROM or 110 allows the user to have individual flags in RAM or to handle single 110 bits as control lines. The example in Figure 20 illustrates the usefulness of the bit manipulation and test instructions. Assume that bit 0 of port A is connected to a zero crossing detector circuit and that bit 1 of port A is connected to the trigger of a TRIAC which powers the controlled hardware. Addressing Modes The MCU has ten addressing modes available for use by the programmer. They are explained and illustrated briefly in the following paragraphs. This program, which uses only seven ROM locations, provides turn-on of the TRIAC within 14 microseconds of the zero crossing. The timer could also be incorporated to provide turn-on at some later time which would permit pulse-width modulation of the controlled power. 5.61 Figure 20. Bit Manipulation Example • • • • • SELF 1 BRCLR 0, PORTA, SELF 1 BSET 1, PORTA BCLR 1, PORTA • • • • • AMII~ 56805 Immediate-Refer to Figure 21. The immediate addressing mode accesses constants which do not change during program execution. Such instructions are two bytes long. The effective address (EA) is the PC and the operand is fetched from the byte following the opcode. Direct- Refer to Figure 22 in direct addressing, the add· ress of the operand is contained in the second byte of the instruction. Direct addressing allows the user to directly address the lowest 256 bytes in memory. All RAM space, 110 registers and 128 bytes of ROM are located in page zero to take advantage of this efficient memory addressing mode. Extended-Refer to Figure 23. Extended addressing is used to reference any location in memory space. The EA is the contents of the two bytes following the opcode. Extended addressing instructions are three bytes long. Relative- Refer to Figure 24. The relative addressing mode applies only to the branch instructions. In this mode the contents of the byte following the opcode is added to the program counter when the branch is taken. EA = (PC) + 2 + ReI. ReI is the contents of the location following the instruction opcode with bit 7 being the sign bit. If the branch is not tken ReI = 0, when a branch takes place, the program goes to somewhere within the range of + 129 bytes to -127 of the present instruction. These instructions are two bytes long. Indexed (No Offset)-Refer to Figure 25. This mode of addressing accesses the lowest 256 bytes of memory. These instructions are one byte long and their EA is the contents of the index register. Indexed (8-Bit Offset)- Refer to Figure 26. The EA is calculated by adding the contents of the byte following the opcode to the contents of the index register. In this mode, 511 low memory locations are accessable. These instructions occupy two bytes. Indexed (16-Bit Offset)- Refer to Figure 27. This addressing mode calculates the EA by adding the contents of the two bytes following the opcode to the index register. Thus, the entire memory space may be accessed. Instructions which use this addressing mode are three bytes long. Bit Set/Clear- Refer to Figure 28. This mode of addressing applies to instructions which can set or clear any bit on page zero. The lower three bits in the opcode specify the bit to be set or cleared while the byte following the opcode specifies the address in page zero Bit Test and Branch-Refer to Figure 29. This mode of addressing applies to instructions which can test any bit in the first 256 locations ($OO-$FF) and branch to any location relative to the PC. The byte to be tested is addressed by the byte following the opcode. The individual bit within that byte to be tested is addressed by the lower three bits of the opcode. The third byte is the relative address to be added to the program counter if the branch condition is met. These instructions are three bytes long. The value of the bit tested is written to the carry bit in the condition code register. Inherent- Refer to Figure 30. The inherent mode of addressing has no EA. All the information necessary to execute an instruction is contained in the opcode. Direct operations on the accumulator and the index register are included in this mode of addressing. In addition, control instructions such as SWI. RTI belong to this group. All inherent addressing instructions are one byte long. Figure 21. Immediate Addressing Example lEA I I J I ~ F8 I INDEX REG STACK POINT PROG LOA N$F8 05BE It=A~6=:::Ir-_ _ _ _----.J 05BF I F8 I I J I ~ I I I I I I I I I ; 5.62 PROG COUNT 05CO CC I S6805 Figure 22. Direct Addressing Example MEMORY ~::::J@:=l------l----J!.!!.!!.L----~=~20~:;J CAT FCB 32 004B INDEX REG STACK POINT ~~!t=}----.J PROG LOA CAT 0520 om I- PROG COUNT 052F CC ~ I I I I I I I I I : Figure 23. Extended Addressing Example MEMORY I I I PROGLDACAT0409~~ J 040A 0408 06 E5 : ] Figure 24. Relative Addressing Example MEMORY PROG BEQ PROG2 04A 7 1---="------1 04A81-_ _----I ~ I , ;I I I I STACK POINT PROG COUNT 040C CC : CAT FCB 64 06E5 t : J : c = j - - - - - - - - - - - 1 I 40 INOEX REG I I 5.63 56805 Figure 25. Indexed (No Offset) Addressing Example MEMORY A TABL FCC/LII 00B8 ~~~~~--.2m!!!!!..---t----""IC::]4C£:;;:J INDEX REG .... "... ~'~.~ I I STACK POINT PROG COUNT 05F5 CC ~ I I I I I I I I I : Figure 26. Indexed (8-Bit Offset) Addressing Example MEMORY TABL FCB NBF FCB NB6 008A FCB No8 008B FCB NCF 008C CF INDEX REG 03 STACK POINT 1---':':'----1 t-::£t::::jf---+-~ !- t=:!t=j-----.J PROG LOA TABL,X 075B 075C PROG COUNT 075E CC § I I I I I I I I I ! Figure 27. Indexed (1S-Bit Offset) Addressing Example MEMORY I I ~ ! PROG LOA TABL.X 0692 0693 0694 ;~: I ~6 07 7E I I TABL DB INDEX REG 02 STACK POINT ] I I :;;:tt-::jf:::~ ::: FCB NOB 0780 PROG COUNT 0695 CC _______ FCB NCF 0781 !-""";;':""'--I 5.64 --1 Mill. 86805 Figure 28. Bit Set/Clear Addressing Example PORT 8 EQU 1 0001 I---=::""----f-' 0000 INDEX REG STACK POINT PROG BCLR 6, PORT B OS8F OS90 r:2t:::=~-------1 I- PROG COUNT OS91 CC § I I I I I! I, I I Figure 29. Bit Test and Branch Addressing Example MEMORY PORT C EQU 2 INDEX REG STACK POINT PROG BCLR 2 PORT C PROG2 OS74 OS7S t=~==tr=~ OS 76 1----:=------1 Figure 30. Inherent Addressing Example MEMORY ; I PROG TAX ~ ,y,§ I CC I § I I I I I I 5.65 AMII~ 86805 Instruction Set The MCV has a set of 59 basic instructions. They can be divided into five different types: register/memory, read/ modify/write, branch, bit manipulation, and control. The following paragraphs briefly explain each type. All the instructions within a given type are presented in individual tables. Register/Memory Instructions- Most of these instructions use two operands. One operand is either the accumulator or the index register. The other operand is obtained from memory using one of the addressing modes. The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register operand. Refer to Table 2. Read/Modify/Write Instructions- These instructions read a memory location or a register, modify or test its contents, and write the modified value back to memory or to the register. The test for negative or zero (TST) instruc- tion is an exception to the read/modify/write instructions since it does not perform the write. Refer to Table 3. Branch Instructions-The branch instructions cause a branch from the program when a certain condition is met. Refer to Table 4. Bit Manipulation Instructions- These instructions are used on any bit in the first 256 bytes of the memory. One group either sets or clears. The other group performs the bit test and branch operations. Refer to Table 5. Control Instructions-The control instructions control the MCV operations during program execution. Refer to Table 6. Alphabetical Listing-The complete instruction set is given in alphabetical order in Table 7. Opcode Map-Table 8 is an opcode map for the instructions used on the MCV. Table 2. Register/Memory Instructions ADDRESSING MODES DIRECT IMMEDIATE UP Function N N UP N INDEXED (No Offset) EXTENDED N UP N N UP N N INDEXED (8·8it Offset) INDEXED 16·81t Offset) UP UP N N N N Mnemonic Code LOAD A FROM MEMORY LOA A6 2 2 B6 2 4 C6 3 5 F6 1 4 E6 2 5 06 3 6 LOAD X FROM MEMORY LOX AE 2 2 BE 2 4 CE 3 5 FE 1 4 EE 2 5 DE 3 6 STORE A IN MEMORY STA - - - B7 2 5 C7 3 6 F7 1 5 E7 2 6 07 3 7 STORE X IN MEMORY STX - - .- BF 2 5 CF 3 6 FF 1 5 EF 2 6 OF 3 7 ADD MEMORY TO A ADD AE 2 2 BB 2. 4 CB 3 5 FB 1 4 EB 2 5 DB 3 6 ADD MEMORY AND CARRY TO A AOC A9 2 2 B9 2 4 C9 3 5 F9 1 4 E9 2 5 09 3 6 SUBTRACT MEMORY SUB AO 2 2 BO 2 4 CO 3 5 FO 1 4 EO 2 5 DO 3 6 SUBTRACT MEMORY FROM A WITH BORROW SBC A2 2 2 B2 2 4 C2 3 5 F2 1 4 E2 2 5 02 3 6 AND MEMORY TO A AND A4 2 2 B4 2 4 C4 3 5 F4 1 4 E4 2 5 04 3 6 OR MEMORY WITH A ORA AA 2 2 BA 2 4 CA 3 5 FA 1 4 EA 2 5 OA 3 6 Bytes Cycles Code Bytes Cycles Code Bytes Cycles Code Bytes Cycles Code Bytes Cycles Code Bytes Cycles EXCLUSIVE OR MEMORY WITH A EOR A8 2 2 B8 2 4 C8 3 5 F8 1 4 E8 2 5 08 3 6 ARITHMETIC COMPARE A WITH MEMORY CMP A1 2 2 B1 2 4 C1 3 5 F1 1 4 E1 2 5 01 3 6 ARITHMETIC COMPARE X WITH MEMORY CPX A3 2 2 B3 2 4 C3 3 5 F3 1 4 E3 2 5 03 3 6 BIT TEST MEMORY WITH A (Logical Compare) BIT A5 2 2 B5 2 4 C5 3 5 F5 1 4 E5 2 5 05 3 6 JUMP UNCONDITIONAL JMP - - - BC 2 3 CC 3 4 FC 1 3 EC 2 4 DC 3 5 JUMP TO SUBROUTINE JSR - - - BO 2 7 CO 3 8 FO 1 7 ED 2 8 DO 3 9 5.66 56805 Table 3. Read/Modify/Write Instructions ADDRESSING MODES INHERENT (A) OP Function Mnemonic Code II INHERENT (X) II OP Bytes Cycle. Code II INDEXED (No Offset) DIRECT II OP Bytes Cycles Code II II OP Bytes Cycles Code II INDEXED (B· Bit Offset) OP II Bytes Cycles Code II Bytes CyCles INCREMENT INC 4C 1 4 5C 1 4 3C 2 6 7C 1 6 6C 2 7 DECREMENT DEC 4A 1 4 5A 1 4 3A 2 6 7A 1 6 6A 2 7 CLEAR CLR 4F 1 4 5F 1 4 3F 2 6 7F 1 6 6F 2 7 COMPLEMENT COM 43 1 4 53 1 4 33 2 6 73 1 6 63 2 7 NEGATE (2's COMPLEMENT) NEG 40 1 4 50 1 4 30 2 6 70 1 6 60 2 7 ROTATE LEFT THRU CARRY ROL 49 1 4 59 1 4 39 2 6 79 1 6 6iJ 2 7 ROTATE RIGHT THRU CARRY ROR 46 1 4 56 1 4 36 2 6 76 1 6 66 2 7 LOGICAL SHIFT LEFT LSL 48 1 4 58 1 4 38 2 6 78 1 6 68 2 7 LOGICAL SHIFT RIGHT LSR 44 1 4 54 1 4 34 2 6 74 1 6 64 2 7 ARITHMETIC SHIFT RIGHT ASR 47 1 4 57 1 4 37 2 6 77 1 6 67 2 7 TEST FOR NEGATIVE OR ZERO TST 40 1 4 5D 1 4 3D 2 6 7D 1 6 60 2 7 Table 4. Branch Instructions RELATIVE ADDRESSING MODE OP Function * * Mnemonic Code BRANCH ALWAYS BRA 20 2 4 BRANCH NEVER BRN 21 2 4 BRANCH IFF HIGHER BHI 22 2 4 BRANCH IFF LOWER OR SAME BLS 23 2 4 BRANCH IFF CARRY CLEAR (BRANCH IFF HIGHER OR SAME) BRANCH IFF CARRY SET (BRANCH IFF LOWER) BRANCH IFF NOT EOUAL Bytes Cycles BCC 24 2 4 (BHS) 24 2 4 4 BCS 25 2 (BLO) 25 2 4 BNE 26 2 4 BEQ 27 2 4 BRANCH IFF HALF CARRY CLEAR BHCC 28 2 4 BRANCH IFF HALF CARRY SET BHCS 29 2 4 BPL 2A 2 4 BRANCH IFF MINUS BMI 2B 2 4 BRANCH IFF INTERRUPT MASK BIT IS CLEAR BMC 2C 2 4 BRANCH IFF INTERRUPT MASK BIT IS SET BMS 2D 2 4 BRANCH IFF INTERRUPT LINE IS LOW BIL 2E 2 4 BRANCH IFF INTERRUPT LINE IS HIGH BIH 2F 2 4 BRANCH TO SUBROUTINE BSR AD 2 8 BRANCH IFF EDUAL BRANCH IFF PLUS 5.67 I AMII~ 56805 Table 5. Bit Manipulation Instructions Function Mnemonic AOORESSIIG MODES OP , I OP , , Cad. Bytes Cycle. Clde ByII' c,•• 20 n 3 10 + 20 n 3 .10 BRANCH IFF BIT n IS SET BRSET n(n = 0 .. 7) - - - BRANCH IFF BIT n IS CLEAR BRCLR n(n = 0 . .. 7) - - - SET BIT n BSET n(n = 0 .. .. 7) CLEAR BIT n BCLRn(n=O. 01 10 + 20 n 2 7 - - - + 20 n 2 7 - - - . 7) 11 Table 6. Control Instructions INHERENT OP Function /I /I Cad. Bytll C,ell. Mn.monlc TRANSFER A TO X TAX 97 1 2 TRANSFER X TO A TXA 9F 1 2 SET CARRY BIT S~C 99 1 2 CLEAR CARRY BIT CLC 98 1 2 SET INTERRUPT MASK BIT SBI 9B 1 2 CLEAR INTERRUPT MASK BIT CLI 9A 1 2 SOFTWARE INTERRUPT SWI 83 1 11 RETURN FROM SUBROUTINE RIS 81 1 6 RETURN FROM INTERRUPT RT! 80 1 9 RESET STACK POINTER RSP 9C 1 2 NO OPERATION NOP 90 1 2 Table 7. Instruction Set Addressing Modes Mnemonic Inherent Indexed (8 Bils) Indexed (16 Bits) X X X X X X X X X Immediate Direct Extended ADC X X X ADD X X X AND X Condition Code Indexed Relative (No Offset) X X ASl X X X X ASR X X X X BCC X BED X BHCC X BHCS X BHI X BHS X BIH X Bil X X X X X BlO X BlS X BMC X CONDITION CODE SYMBDlS: H HALF CARRY (FROM BIT 3) I INTERRUPT MASK N NEGATIVE (SIGN BIT) ZERO CARRY BORROW X II • 5.68 X TEST AND SET IF TRUE. CLEARED OTHERWISE NOT AFFECTED H N Z II II II II II II II II • • II • • II • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • II • • • • • • • • • • II II II II I • II • • • X BCS Bit Test & Branch II X BClR BIT Bit Set! Clear C • • • • • • • • • • • • • • • • • • • • II • • • • • • • S6805 Table 7. Instruction Set (Continued) Addressing Modes Mnemonic Inherent Immediate Direct Extended Condition Code Indexed Relative (No Offset) Indexed (8 Bits) Indexed (16 Bits) Bit Sell Clear Bit Test &. Branch BPL BRA BRN BRCLR X BRSET X x BSET BSR X CLC X CLI X CLR X CMP X X X CPX X X X X X X X X X X X x x x x x x x x X X X X X X X EOR INC N Z C • • • • • • • • • • • • • • • BNE DEC I • • • • • BMS COM H • • • • • BMI X X JMP X X X X X X X X X X X X LOA X X X X X X LOX X X X X X X JSR LSL X X X X LSR X X X X NED X X X X NOP X X X X X ORA X ROL X RSP X RTI X RTS X SBC X SEI X X X X X X X X X STA X X X X X STX X X X X X X X X X X SUB X SWI X TAX X TST X TXA X CONDITION CODE SYMBOLS: H HALF CARRY (FROM BIT 3) I INTERRUPT MASK N NEGATIVE (SIGN BIT) X ZERO CARRY BORROW LOAD CC REGISTER FROM STACK X X /I • 5.69 TEST AND SET IF TRUE. CLEARED OTHERWISE NOT AFFECTED • /I /I • • • • • • • • • • • I • • • /I /I /I • • • • • • /I /I I /I /I /I • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 7 X SEC X • • • • • • • • • • • • • • • • • • • • • • • • /I 7 /I /I /I /I /I /I /I /I /I /I /I /I /I /I /I /I /I /I /I /I /I /I 7 7 7 • • • • • • • • • I • • • • • • • • I • • • • • • • • • /I /I • • /I /I • I • • • /I /I /I • /I /I /I /I • • • • • • • /I AMII~ 56805 Table 8. Opcode Map Bit Manipulation Bmch ReadlModifyiWrite Register/Memory Control Test & Branch Set/Clear Rei DlR A X .Xl .XO INH INH IMM DlR EX .X2 .Xl .XO 0 1 2 3 4 5 6 7 8 8 A B C D E F BRSETO BSETO BRA NEQ - RTI* - SUB RIS* - CMP 1 - SBC 2 1 BRCLRO BCLRO BRN - 2 BRSET1 BSm BHI - 3 BRCLR1 BCLR1 BLS COM SWI* - CMPX/CPX 3 4 BRSET2 BSET2 BCC LSR - - AND 4 5 BRCLR2 BCLR2 BCS 6 BRSET3 BSET3 BNE - - - BIT 5 ROR - - LDA 6 - ? BRCLR3 BCLR3 BEQ ASR - TAX 8 BRSET4 BSET4 BHCC LSL/ASL - CLC - STA( + 1) ? EOR 8 9 BRCLR4 BCLR4 BHCS ROL - SEC ADC 9 A BRSET5 BSET5 BPL DEC - CLI ORA A B BRCLR5 BCLR5 BMI - - SEI C BRSET6 BSET6 BMC INC - RSP D BRCLR6 BCLR6 BMS TST - NOP E BRSET? BSET7 BIL F BRCLR7 BCLR? BIH 3/10 217 2/4 - - CLR 2/6 1/4 1/4 - 217 1/6 1/* - BSR* TXA - 1/2 2/2 3/5 NOTES: UNDEFINED OPCODES ARE MARKED WITH' THE NUMBERS AT THE BOTTOM OF EACH COLUMN DENOTE THE NUMBER OF BYTES AND THE NUMBER OF CYCLES REQUIRED (BYTES/CYCLES) NMEMONICS FOLLOWED BY A .... REQUIRE A DIFFERENT NUMBER OF CYCLES AS FOLLOWS RTI 9 RTS 6 SWI 11 BSR 8 ) INDICATE THAT THE NUMBER IN PARENTHESIS MUST BE ADDED TO THE CYCLE COUNT FOR THAT INSTRUCTION 5.70 ADD B JMP(-1) C JSR( + 3) D LDX E F STX(+ 1) 2/4 3/6 HIGH 0 2/5 1/40 w AMII~ 56805 Table 9. 56805 Family of Microprocessors 86805 86805C 86805N 86805C1 TECHNOLOGY NMOS CMOS NMOS CMOS NUMBER OF PINS 28 40 40 40 ON-CHIP RAM (BYTES) 64 112 64 112 ON CHIP USER ROM (BYTES) UK NONE 2K 2.2K EXPANSION BUS NONE YES NONE NONE BIDIRECTIONAL I/O LINES 20 16 32 32 I/O OPTIONS NONE NONE A/D CONVERTER NONE SOFTWARE COMPATIBILITY YES YES YES YES TRUE BIT MANIPULATION YES YES YES YES INSTRUCTIONS 59 61 59 61 TEN ADDRESSING MODES YES YES YES YES 5.71 • AMII~ S6805 Ordering Information Option List - Select the options for your MCU from the following list. A manufacturing mask will be generated from this information. Timer Clock Source Timer Prescaler o 20 (divide by 1) o 21 (divide by 2) o 22 (divide by 4) D Internal ~ 2 clock D TIMER input, pin 7 D 23 (divide by 8) 0 24 (divide by 16) 0 25 (divide by 32) 0 26 (divide by 64) 0 27 (divide by 128) 0 Crystal o o D Disable Internal Oscillator Input Resistor Low Voltage Inhibit HOM Specifications How are the records specified? o AMI Hex D Intellec Hex Enable D BPNF o Anything else (include precise description of format) What form will the data be transmitted in? I. 9-track NRZ unlabeled magnetic tape? D If you choose mag tape, please answer the following questions: A. Which is it coded in? 0 EBCDIC B. What is the parity? 0 ODD C. What is the recording density? 0 556 BPI o 800 BPI D. Is is unblocked? (One record per block) DYES o NO If blocked, how many records per block? II. FDOS floppy disk file? 0 III. Paper tape? 0 IV. Card deck 0 V. EPROM? 0 o ASCII o EVEN o 1600 BPI No matter what physical means is chosen, try to include two machine readable forms along with a listing. If only one form of the data is available, a listing is imperative. Two blank EPROM's should be included with the ordering information. These EPROM's will be programmed from the mask tapes and returned for approval before the first silicon trial run. 5.72 Please contact your local AMI Sales Office for complete data sheet ADVANCED PRODUCT DESCRIPTION 56808 MICROPROCESSOR WITH CLOCK Features General Description o o The S6808 is a monolithic 8-bit microprocessor that contains all the registers and accumulators of the present S6800 plus an internal clock oscillator and driver on the same chip. o o o o o On-Chip Clock Software-Compatible with the S6800 Expandable to 65K Words Standard TTL-Compatible Inputs and Outputs 8-Bit Word Size I6-Bit Memory Addressing Interrupt Capability This very cost-effective MPU allows the designer to use the S6808 in consumer as well as industrial applications without sacrificing industrial specifications. Typica I Microprocessor Interface Pin Configuration RESET XTAl EXTAl 3K 3K ---+--........--HiRQ Vss '----~~MR Vee ~-----~VMA R/W DO ~-----~Rffl 01 02 DATA BUS DO - 07 03 04 27pF Xlal 1----..----1 ADDRESS BUS h D27pF AD - A15 EXtal 4MHz 05 .". ~ 06 07 A15 A14 A13 A12 Vss 5.73 PRELIMINARY DATA SHEET S6809/S68A09/S68B09 8·BIT MICROPROCESSING UNIT Features General Description o Interfaces with All S6800 Peripherals o Upward Compatible Instruction Set and Addressing Modes o The 86809 is an advanced processor within the 86800 family offering greater throughput, improved byte efficiency, and increased adaptability to various software disciplines. These include position independence, reentrancy, recursion, block structuring, and high level language generation. Upward Source Compatible Instruction Set and Addressing Modes Because the 86809 generates position-independent code, software can be written in modular form for easy user expansion as system requirements increase. The 86809 is hardware compatible with all 86800 peripherals, and any assembly language code prepared for the 86800 can be passed through the 86809 assembler to produce code which will run on the 86809. o Two 8-Bit Accumulators Can Be Concatenated Into One 16-Bit Accumulator o On-Chip Crystal Oscillator {4 Time XT AU Pin Configuration Block Diagram +-+-- Vee Vss INSTRUCTION DECODE (IR) Vssl HALT NMi XTAL iRQ EXTAL Fiiili RESET SS MROY SA Vcc 1 AO RESET NMI R/W A2 00 FIRQ A3 01 IRQ A4 02 A5 03 A6 04 A7 05 A8 06 A9 07 FWT BA BS XTAL ~ OMA/SREQ Al EXTAL MRDY E Q 5.74 Al0 A15 All A14 A12 A13 S6809/S68A09/S68B09 S6809 Hardware Features o On-Chip Oscillator o MRDY Input Extends Access Time o DMA/BREQ for DMA and Memory Refresh o Fast Interrupt Request Input: Stacks Only Program Counter and Condition Code o Interrupt Acknowledge Output Allows Vectoring by Devices o Three Vectored Priority Interrupt Levels o SYNC Acknowledge Output Allows for Synchronization to External Event o NMI Blocked after RESET until after First Load of Stack Pointer o Early Address Valid Allows Use with Slow Memories S6809E Hardware Features o Last Instruction Cycle Output ILICI for Identification Output Fetch o Busy Output Eases Multiprocessor Design Instruction Set o Extended Range Branches o Load Effective Address o 16-Bit Arithmetic o 8x8 Unsigned Multiply (Accumulator A*BI o SYNC Instruction - Provides Software Sync with an External Hardware Process o Push and Pull on 2 Stacks o Push/Pull Any or All Registers o Index Registers May Be Used as Stack Pointer o TransferlExchange All Registers Addressing Modes o All 6800 Modes Plus PC Relative, Extended Indirect, Indexed Indirect, and PC Relative Indirect o Direct Addressing Available Anywhere in Memory Map o PC Relative Addressing: Byte Relative I ± 32, 768 Bytes from PCI D Complete Indexed Addressing Including Automatic Increment and Decrement, Register Offsets, and Four Indexable Registers IX, Y, U and SI D Expanded Index Addressing - 0, 5, 8, 16-Bit Constant Offset - 8, 16-Bit Accumulator Offsets Absolute Maximum Ratings The S6809 gives the user 8 and 16-bit word capability with several hardware enhancements in the design such as the Fast Interrupt (FIRQ), Memory Ready (MRDY), and Quadrature (Qout) and System Clock Outputs (Eout). With the Fast Interrupt Request (FIRQ) the S6809 places only the Program Counter and Condition Code Register on the stack prior to accessing the FIRQ vector location. The Memory Ready (MRDY) input allows extension of the data access time for use with slow memories. The System Clock (Eout) operates at the basic processor frequency and can be as the synchronization signal for the entire system. The Quadrature Output (Qout) provides additional system timing by signifying that address and data are stable. The External Clock mode of the S6809E is particularly useful when synchronizing the processor to an externally generated signal. The Three-State Control input (TSC) places the Address and R/W line in the high impedance state for DMA or Memory Refresh. The last Instruction Cycle (LIC) is activated during the last cycle of any instruction. This signifies that the next instruction cycle is the opcode fetch. The Processor Busy signal (BUSY) facilitates multiprocessor applications by allowing the designer to insure that flags being modified by one processor are not accessed by another simultaneously. The S6809 features a family of addressing capabilities which can use any of the four index registers and stack pointers as a pointer to the operand (or the operand address). This pointer can have a fixed or variable signed offset that can be automatically incremented or decremented. The eight-bit direct page register permits a user to determine which page of memory is accessed by the instructions employing "page zero" addressing. This quick access to any page is especially useful in Multitasking Applications. The S6809 has three vectored priority-interrupt levels, each of which automatically disables the lower priority interrupt while leaving the higher priority interrupt enabled. The S6809 gives the system designer greater flexibility (through modular relocatable code) to enable the user to reduce system software costs while at the same time increasing software reliability and efficiency. Supply Voltage, Vee ................................................................. - 0.3V to + 7.0V Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3V to + 7.0V Operating Temperature Range, TA ....................................................... O°C to + 70°C Storage Temperature Range, T stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to + 150°C Thermal Resistance, ()JA Plastic .................................................................................. 100°C/W Ceramic ................................................................................. 50°C/W This device contains circuitry to protect the inputs against damage due to high static voltage or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. 5.75 AMII. S6809/S68A09/S68B09 Electrical Characteristics (Vcc = 5.0V ± 5%; Vss= 0, TA = OOC to + 70°C unless otherwise noted) Symbol Parameter Typ. Min. Input High Voltage Logic, EXtal RESET Vss + 2.0 Vss + 4.0 VIL Input Low Voltage Logic EXtal, RESET Vss-0.3 lin Input Leakage Current Logic Output High Voltage DO-D7 VIH VOH AO-AI5, R/W, Q, E BA,BS VOL Output Low Voltage PD Power Dissipation Cin Capacitance # Cout f fXTAL fXTAL ITS! Vdc 10 7 Vdc J.tAdc Yin = 0 to 5.25V, Vee = max Vdc ILoad = - 205J.tAdc, Vee = min ILoad = -145J.tAdc, Vee= min ILoad = - 100J.tAdc, Vee = min Vss + 0.5 Vdc hoad = 2.0mAdc, Vee = min 1.0 W 15 10 12 pF 4 6 8 MHz 10 100 J.tAdc S6809 S68A09 S68B09 Three-State (Off State) Input Current Do-D7 A o-A 1S,R/W Condition 2.5 Vss + 2.4 Vss + 2.4 Vss + 2.4 Do-D7 (Crystal or External Input) Unit VDD VDD Vss + 0.8 1.0 Logic Inputs, EXtal A o-A 1S,RiW Frequency of Operation Max. 2.0 Yin = 0, TA = 25°C, f = 1.0MHz Yin = 0.4 to 2.4V, Vee = max Read/Write Timing (Reference Figures 1 and 2) S68A09 S6809 Typ. Typ. S68B09 Parameter Min. tCYC Cycle Time 1000 667 500 ns tUT Total Up Time 975 640 480 ns t ACC Peripheral Read Access Time 695 440 320 ns t DSR Data Setup Time (Read) 80 60 40 ns Max. Min. Max. Typ. Symbol Min. Max. Unit Condition tDRR Input Data Hold Time 10 10 10 ns tDRw Output Data Hold Time 30 30 30 ns tAR Address Hold Time (Address. R/W) 30 30 30 ns tAD Address Delay 200 140 110 ns tDDW' Data Delay Time (Write) 225 180 145 ns t AvS E 10w to Qhigh Time 250 165 125 ns tAQ Address Valid to Qhigh 25 25 15 ns tpWEL Processor Clock Low 450 295 210 ns tpWEH Processor Clock High 450 280 220 ns tpCSR MRDY Set Up Time 60 60 60 ns tpcs Interrupts Set Up Time 200 140 110 ns tpCSH HALT Set Up Time 200 140 110 ns tpCSR RESET Set Up Time 200 140 110 ns tpCSD DMA/BREQ Set Up Time 125 125 125 ns t,.c Crystal Osc Start Time 100 100 100 ms t ER • tEF E Rise and Fall Time tpCR.tPLF Processor Control Rise/Fall t QR • tQF Q Rise and Fall Time t pWQH Q Clock High 5 25 5 5 450 25 5 100 100 25 5 280 5.76 25 5 220 20 ns 100 ns 20 ns ns tacc = tut- tAD - t DSR tut = tCYC - tEF S6809/S68A09/S68B09 Figure 1. Read Data From Memory or Peripherals Inc 2.4V 2.4V O.5V 2.4V IpWEH ....- - - - - - - - - IUT 2.4V ....- - - - - + - - - - - I U T - - - - - - - - - - - . . J ADDR DATA,-------------------c:z:zu MRDY DMA/BREQ ~NOTVALID Figure 2. Write Data to M~mory or Peripherals RM ADOR BA, BS --~~ DATA DATA VALID ~NOTVALID 5.77 O.5V AMII~ S6809/S68A09/S68B09 Programming Model Figure 3. Bus Timing Test Load As shown in Figure 4, the 86809 adds three registers to the set available in the 86800. The added registers include a direct page register, the User 8tack pointer and a second Index Register. 4.75V Accumulators lA, B, DI The A and B registers are general purpose accumulators which are used for arithmetic calculations and manipulation of data. TEST POINTo-........_~~-~ MM06150 ~ ,OR EQUIV . ...;"" Certain instructions concatenate the A and B registers to form a single 16-bit accumulator. This is referred to as the D register, and is formed with the A register as the most significant byte. ~ ~MM07000 ~ ~OR EQUIV. ~ C= 30pF FOR BA, BS 130pF FOR 00·07, E, Q 90pF FOR AO·A 15, R/W Direct Page Register IDP) R= 11.7kn FOR 00·07 16.5k{J FOR AO·A15, E, Q 24kll FOR BA, BS The Direct Page Register of the 86809 serves to enhance the Direct Addressing Mode. The content of this register appears at the higher address outputs (A 8-A 15) during direct Addressing Instruction execution. This Figure 4. Programming Model of the Microprocessing Unit 15 IM"~~~~~ x - INDEX REGISTER Y - INDEX REGISTER U - USER STACK POINTER S - HARDWARE STACK POINTER PROGRAM COUNTER PC A I ACCUMULATORS B ,'--------------.. ~----------'/ '0 OP I ElF [H 5.78 II I N I z DIRECT PAGE REGISTER I v I C CC-CONDlTIONCOOEREGISTER S6809/S68A09/S68B09 Figure 5. Condition Code Register Format IEIF rHlllNlz lvici I L CARRY ~OVERFLOW I L - -_ _ _ ZERO L -_ _ _ _ NEGATIVE L--_ _ _ _ _ _ IRQ MASK 1.-._ _ _ _ _ _ _ HALF CARRY L -_ _ _ _ _ _ _ _ _ FIRQ MASK ' - - - - - - - - - - - - - ENTIRE FLAG allows the direct mode to be used at any place in memory, under program control. To allow 6800 compatibility, all bits of this register are cleared during Processor Reset. Condition Code Register The condition code register defines the State of the Processor at any given time, see Figure 5. Index Registers fX, yt The Index Registers are used in indexed mode of addressing. The 16-bit address in this register takes part in the calculation of effective addresses. This address may be used to point to data directly or may be modified by an optional constant or register offset. During some indexed modes, the contents of the index register are incremented and decremented to point to the next item of tabular type data. All four pointer registers (X, Y, U, S) may be used as index registers. Stack Pointers lU, SI The Hardware Stack Pointer (S) is used automatically by the processor during subroutine calls and interrupts. The stack pointers of the S6809 point to the top of the stack, in contrast to the S6800 stack pointer which pointed to the next free location on the stack. The User Stack Pointer (U) is controlled exclusively by the programmer thus allowing arguments to be passed to and from subroutines with ease. Both Stack Pointers have the same indexed mode addressing capabilities as the X and Y registers, but also support Push and Pull instructions. This allows the S6809 to be used efficiently as a stack processor, greatly enhancing its ability to support higher levellanguage~ and modular programming. Bit 0 lCI Bit 0 is the Carry Flag, and is usually the carry from the binary ALU. C is also used to represent a 'borrow' from subtract like instructions (CMP, NEG, SUB, SBC). Here the carry flag is the complement of the carry from the binary ALU. Bit IIVI Bit 1 is the overflow flag, and is set to a one by an operation which causes a signed two's complement arithmetic overflow. This overflow is detected in an operation in which the carry from the MSB in the AL U does not match the carry from the MSB-l. Bit 2lZ1 Bit 2 is the zero flag, and is set to a one if the result of the previous operation was identically zero. Bit 31NI Bit 3 is the negative flag, which contains exactly the value of the MSB of the result of the preceding operation. Thus, a negative two's-complement result will leave N set to a one. Program Counter The Program Counter is used by the processor to point Bit 4111 to the address of the next instruction to be executed by Bit 4 is the IRQ mask bit. The processor will not the processor. Relative Addressing is provided allowing recognize interrupts from the IRQ line if this bit is set to the Program Counter to be used like an index register a one. NMI, FIRQ, IRQ, RESET, and SWI all set I to a one; SWI2 and SWI3 do not affect I. in some situations. 5.79 S6809/S68A09/S68B09 Bit 51Hl Bit 5 is the half-carry bit, and is used to indicate a carry from bit 3 in the AL U as a result of an 8-bit addition only (ADC or ADD). This bit is used by the DAA instruction to perform a BCD decimal add adjust operation. The state of this flag is undefined in all subtract-like instructions. Bit 61Fl Bit 6 is the FIRQ mask bit. The processor will not recognize interrupts from the FIRQ line if this bit is a one. NMI, FIRQ, SWI, and RESET all set F to a one. IRQ, SWI2 and SWI3 do not affect F. Bit 71El Bit 7 is the entire flag, and when set to a one indicates that the complete machine state (all the registers) was stacked, as opposed to the subset state (PC and CC). The E bit of the stacked CC is used on a return from interrupt (RTI) to determine the extent of the unstacking. Therefore, the current E left in the Condition Code Register represents past action. 56809 MPU Signal Description Power IV ss, Vcd Two pins are used to supply power to the part: Vss is ground or 0 volts, while Vee is + 5.0V ± 5%. Address Bus IAo-A151 Sixteen pins are used to output address information from the MPU onto the Address Bus. When the processor does not require the bus for a data transfer, it will output address FFFF16, R/W = 1, and BS = O. Addresses are valid on the rising edge of Q (see Figures 1 and 2). All address bus drivers are made high-impedance when output Bus Available (BA) is high. Each pin will drive one Schottky TTL load and typically 90pF. Data Bus IDo-D71 These eight pins provide communication with the system bi-directional data bus. Each pin will drive one Schottky TTL load and typically 130pF. RESET A low level on this Schmitt-trigger input for greater than one bus cycle will reset the MPU as shown in Figure 6. The Reset vectors are fetched from locations FFFE16 and FFFF16 (Table 1) when Interrupt Acknowledge is true, (BA!\BS = 1). During initial poweron, the Reset line should be held low until the clock oscillator is fully operational; see Figure 7. Because the S6809 Reset pin has a Schmitt-trigger input with a threshold voltage higher than that of standard peripherals, a simple RIC network may be used to reset the entire system. This higher threshold voltage insures that all peripherals are out of the reset state before the Processor. HALT A low level on this input pin will cause the MPU to stop running at the end of the present instruction and remain halted indefinitely without loss of data. When Halted, the BA output is driven high indicating the buses are high-impedance. BS is also high which indicates the processor is in the Halt or Bus Grant state. While halted, the MPU will not respond to external real-time requests (FIRQ, IRQ) although DMA/BREQ will always be accepted, and NMI or RESET will be latched for later response. During the Halt state Q and E continue to run normally. If the MPU is not running (RESET, DMAI BREQ), a halted state (BA and BS = 1) can be achieved by pulling HALT low while RESET is still low. If DMAI BREQ and HALT are both pulled low, the processor will reach the last cycle of the instruction (by reverse cycle stealing) where the machine will then become halted. See Figure 8. Bus Available, Bus Status IBA, BSI The Bus Available output is an indication of an internal control signal which makes the MOS buses of the MPU high-impedance. This signal does not imply that the bus will be available for more than one cycle. When BA goes low, an additional dead cycle will elapse before the MPU acquires the bus. The Bus Status output signal, when decoded with BA, represents the MPU state (valid with leading edge of Q): ReadlWrite IR/W) This signal indicates the direction of the data transfer on the data bus. A low indicates that the MPU is writing data onto the data bus. R/W is made high impedance when BA is high. R/W is valid on the rising edge of Q, refer to Figures 1 and 2. 5.80 MPU State BA BS 0 0 1 1 0 1 0 1 Normal (Running) Interrupt Acknowledge SYNC Acknowledge HALT or Bus Grant ~... Figure 6. RESET Timing Vou RESET'~ AD~~~SS FFFE ~c- ·NOTE: PARTS WITH DATE CODES PREFIXED BY 7F WILL COME OUT OF RESET ONE CYCLE SOONER THAN SHOWN <:l1 Cx> ...... Figure 7. Crystal Connections and Oscillator Start Up 6B09 Crystal Parameters· tl Vou -+------r.Jl-Sl-Jl-J .8V REID tRe ~ I 3.SBMHz 4.00MHz 6.0MHz B.OMHz RS 60n son 30·son 20·40n Co 3.SpF 6.SpF 4·6pF 4·6pF C1 .U1SpF .U2SpF .01·.02pF .U1-.02pF 2SpF 2SpF 2SpF 2SpF C;n·Coul Q ,,3UK ,,20K ,,20K 40K I -All Parameters Are± 10%. ·Note: nese are representative AT·cul crystal parameters only. Crystals of other types of cut that wolf( may also be used. 38 101 39 CiJ JCO o ~ 0) 86809 38rD~39 en 0) Q) ~C~ ~~~~ Co ~ o ~ 0) Q) m o CO AMII. S6809/S68A09/S68B09 Figure 8. HALT and Single Instruction Execution for System Debug 2nd TO LAST LAST CYCLE OF CYCLE OF CURRENT CURRENT INST INST I. I ~. ...I .I.. ) OEAD CYCLE HALTED HALTED ( ~--~~~-------------------~-------FETCH EXECUTE r---~'~-----------------~------- \ _________--J! r---~~r_----------------~\ I~------- r---~~-------------------~----­ INSTRUCTION OPCODE Interrupt Acknowledge is indicated during both cycles of a hardware-vector-fetch (RESET, NMI, FIRQ, IRQ, SWI, SWI2, SWI3). This signal, plus decoding of the lower 4 address lines can provide the user with an indication of which interrupt level is being serviced and allow vectoring by device (see Table 1). Sync Acknowledge is indicated while the MPU is waiting for external synchronization on an interrupt line. HaltlBus Grant is true when the S6809 is in a Halt or Bus Grant condition. Table 1. Memory Map for Interrupt Vectors Memory Map for Vector Location MS LS FFFE FFFC FFFA FFF8 FFF6 FFF4 FFF2 FFFO FFFF FFFD FFFB FFF9 FFF7 FFF5 FFF3 FFF1 Interrupt Vector Description RESET NMI SWI IRQ FIRQ SWI2 SWI3 Reserved *NOTE: NMI, FIRQ and IRQ requests are latched by the falling edge of every Qexcept during cycle stealing operations (e.g:, DMA) where only NMI is latched. From this point, a delay of at least one bus cycle will occur before the interrupt is serviced by the MPU. Non-Maskable Interrupt INMU A negative edge on this input requests that a nonmaskable interrupt sequence be generated. A nonmaskable interrupt cannot be inhibited by the program, and also has a higher priority than FIRQ, IRQ or software interrupts. During recognition of an NMI, the entire machine state is saved on the hardware stack. After reset, an NMI will not be recognized until the first program load of the Hardware Stack Pointer (S). The pulse width of NMI low must be at least one E cycle. If the NMI input does not meet the minimum set up with respect to Q, the interrupt will not be recognized until the next cycle. See Figure 9. Fast-Interrupt Request IFIRQ) A low level on this input pin will initiate a fast interrupt sequence, provided its mask bit (F) in the CC is clear. This sequence has priority over the standard Interrupt Request (IRQ), and is fast in the sense that it stacks only the contents of the condition code register and the program counter. The interrupt service routine should clear the source of the interrupt before doing an RTI. See Figure 10. 5.82 ~.... Figure 9. IRQ and NMI Interrupt Timing I ADDRESS BUS ! I INS}w~lTlON FFFF SP·1 SP·2 SP·3 SP·4 SP·5 SP·6 SP·8 SP9 SP·10 SP·11 SP·12 FFFF FFFC (NMqFFFO (NMI) FFFF NEW PC NEW PCH Ipc~ ~FETCH FFF8 (IRQ) FFF9 (IRQ) \~._=0.~8V~_________________________________________________________________________________________________ ~R DATA BUS INSTRUCTION PCLO R/W~ PCHI USLO USHI Y·REGLD Y·REGHI X·REGLD X·REG.. DP ACCB ACCA CCR NEW PCHI NEW PCLO SERVICE ROUTINE I \ VMA OF IN~~RUPT -c BA~ I §~ \'-_ _ _ __ 01 00 CI.:l Figure 10. FIRQ Interrupt Timing '-9.-' ADDRESSJ'-_.J'\._...J\_...J,____.....J'.......-.J"-__J.'-----',"--_,'-_J'-_.J\..._J'-_........_ . J ' \ ._ _ BUS NEXT FFFF SP·1 SP·2 SP·3 FFFF FFF6 FFF7 FFFF NEW PC NEW ...... - ARQ PC + 1 INSTRUCTION -FETCH ~0~.8~V-------------------~------------- ,,_...J,____ DATA BUS-.J'.~._J'.......---'''__---'''___,.......__''''-_.J'_ __..J\...'=""...J'\._ _ _ .....J'......._ _ J ' ' - - _ _ J ' _ _ INSTRUCTION PCLO pc.. CCR NEW PCLo NEW PC .. VMA OF1~\~~~1PT SERVICE ROW R/W ql?d:J \ I 'c= BA~ BS~ I \'-_ _ _ __ en 0) CO o ~ 0) ~ o ~ 0) CO to o CO AMII~ S6809/S68A09/S68B09 Interrupt Request (IRQ) integral multiples of quarter (1/4) bus cycles, thus allowing interface to slow memories as shown in Figure 12. A maximum stretch is 10 microseconds. During non-valid memory accesses (VMA cycles). MRDY has no effect on stretching E. This inhibits slowing the processor speed during "don't care" bus accesses. A low level input on this pin will initiate an Interrupt Request sequence provided the mask bit (I) in the CC is clear. Since IRQ stacks the entire machine state it provides a slower response to interrupts than FIRQ. IRQ also has a lower priority than FIRQ. Again, the interrupt service routine should clear the source of the interrupt before doing an RTI. See Figure 9. DMA/BREQ XTAL, EXTAL These input pins are used to connect the on-chip oscillator to an external parallel-resonant crystal. Alternately, the pin EXTAL may be used as a TTL level input for external timing by grounding XT AL. The crystal or external frequency is 4 times the bus frequency, see Figure 7. Proper RF layout techniques should be observed in the layout of printed circuit boards. E,Q E is similar to the S6800 bus timing signal ct>2; Q is a quadrature clock signal which leads E. Q has no parallel on the S6800. Addresses from the MPU will be valid with the leading edge of Q. Data is latched on the falling edge of E. Timing for E and Q is shown in Figure 11. MRDY This input control signal allows stretching of E to extend data-access time. When MRDY is high, E will be in normal operation. When MRDY is low, E may be stretched The DMA/BREQ input provides a method of suspending execution and acquiring the MPU bus for another use as shown in Figure 13. Typical uses include DMA and dynamic memory refresh. Transition of DMA/BREQ should occur during Q. A low level on this pin will stop instruction execution at the end of the current cycle. The MPU will acknowledge DMA/BREQ by setting BA and BS to a one. The requesting device will now have up to 15 bus cycles before the MPU retrieves the bus for self-refresh. Self-refresh requires one bus cycle with a leading and trailing dead cycle, see Figure 14. Typically. the DMA controller will request to use the bus by asserting the DMA/BREQ pin low on the leading edge of E. When the MPU replies with BA = BS = 1, that cycle will be a dead cycle used to transfer control to the DMA controller. False memory accesses should be prevented during any dead cycles. When BA is cleared {either as a result of Figure 11. E/Q Relationship START OF CYCLE END OF CYCLE (LATCH DATA) I I E~'-----_--J/ '{~ ~~,~ I ~72.~4V------------~" : '------4----- ADORESS VALID Figure 12. MRDY Timing \ / \1 n--\. r )'-----~ I I \~~/_~~~.lil~(~J-~/ _~.~ ~--p+--lpCSR (J~- MDRY 5.84 AMII~ S6809/S68A09/S68B09 Figure 13. Typical DMA Timing « 14 Cycles) MPU DEAD DEAD DMA MPU 8A,88 \~--J/ »)-------------------------«....___ ADDR(MPU) _ _ _ _ _ _ _ _ _ _ ADDR(DMAC) ----------~(I....__________________ _J)>-----NOTE: NMAYin IS A SIGNAL WHICH ISDEVELOPfDfXTEJlHAllY, BUT IS A SYSTEM REQUIREMENT FOR DMA Figure 14. Auto-Refresh DMA Timing « 14 Cycles) I I I I DEAD f - - - - - - - - - - 1 4 DMA f o. o. I l. I CYCLES--------~.I DEAD I MPU I DEAD L-- D M A _ I I I I I I I I I I I I DMAl8REQ'\ : I I I I I - Y r - - - : - - - - - - - - - - - - - - - - - - - - - -.....~r-+------ 8A,as DMAYMA ~' - - - /1----------------------------------\1~~~I~------ 5.85 S6809/S68A09/S68B09 DMA/BREQ = HIGH or MPU self-refresh), the DMA device should be taken off the bus. Another dead cycle will elapse before the MPU is allowed a memory access to transfer control without contention. MPU Operation During normal operation, the MPU fetches an instruction from memory and then executes the requested function. This sequence begins at RESET and is repeated indefinitely unless altered by a special instruction or hardware occurrence. Software instructions that alter normal MPU operation are: SWI, SWI2, SWI3, CWAI, RTI and SYNC. An interrupt, HALT or DMA/ BREQ can also alter the normal execution of instructions. Figure 15 illustrates the flowchart for the S6809. The left-half of the flowchart represents normal operation; the right-half represents the flow when an interrupt when an interrupt or special instruction occurs. Immediate Addressing In Immediate Addressing, the effective addressing of the data is the location immediately following the opcode; the data to be used in the instruction immediately follows the opcode of the instruction. The S6809 uses both 8 and 16-bit immediate values depending on the size of argument specified by the opcode. Examples of instructions with Immediate Addressing are: LDA #$20 LDX #$FOOO LDY #CAT Note: # signifies Immediate addressing, $ signifies hexadecimal value. Extended Addressing In Extended Addressing the contents of the two bytes immediately following the opcode fully specify the 16-bit effective address used by the instruction. Note that the address generated by an extended instruction defines an absolute address and is not position independent. Examples of Extended Addressing include: Addressing Modes The basic instructions of any computer are greatly enhanced by the presence of powerful addressing modes. The 86809 has the most complete set of addressing modes available on any microcomputer today. For example, the S6809 has 59 basic instructions, however it recognizes 1464 different variations of instructions and addressing modes. The new addressing modes support modern programming techniques. The following addressing modes are available on the S6809: Inherent (Includes Accumulator) Immediate Extended Extended Indirect Direct Register Indexed Zero-Offset Constant Offset Accumulator Offset Auto Increment/Decrement Indexed Indirect Relative Short/Long Relative Branching Program Counter Relative Addressing LDA CAT STX MOUSE LDD $2000 Extended Indirect As a special case of indexed addressing (discussed below), one level of indirection may be added to Extended Addressing. In Extended Indirect, the two bytes following the post byte of an Indexed instruction contains the address of the address of the data. LDA [CAT] LDX [$FFFE] STU [DOG] Direct Addressing Direct addressing is similar to extended addressing except that only one byte of address follows the opcode. This byte specifies the lower 8 bits of the address to be used. The upper 8 bits of the address are supplied by the direct page register. Since only one byte of address is required in direct addressing, this mode requires less memory and executes faster than extended addressing. Of course, only 256 locations (one page) can be accessed without redefining the contents of the DP register. Since the DP register is set to $00 on Reset, direct addressing on the S6809 is compatible with direct addressing on the S6800. Indirection is not allowed in direct addressing. Some examples of direct addressing are: Inherent Uncludes Accumulatorl In this addressing mode, the opcode of the instruction contains all the address information necessary. Examples of Inherent Addressing are: ABX, DAA, SWI, ASRA, and CLRB. LDA $30 SETDP $10 (Assembler directive) $1030 LDB LDD o ~ 00 to o CD ..~ Figure 19. Address Bus Cycle-by-Cycle Performance (Cont.) It NON-INHERENTS -----2~2------~------~------~-------+-------+------~------~~----------------------~ LEA AOCA ADCB ADDA AOOB BlTA BlTB CMPA CMPB EORA EORB LOA LOB ORA ORB STA STB SUBA SUBB LOO LOS ASL ASR CLR COM DEC INC LSL LSR NEG ROL ROR LOU LOX LOY STD STS STIl STX STY TST AODD CMPO CMPS CMPU CMPX CMPY SUBO END JSR ANDCC ORCC 01 ~ ~ VMA STACK AOOR+ 1 j' i T l en 0) CO o ~ 0) ~ o ~ 0) CO OJ o CD AMII~ S6809/S68A09/S68B09 Table 6. Index Register/Stack Pointer Instructions 56809 Instruction Set Tables Mnemonlc(s) CMPS, CMPU CMPX, CMPY EXG R1, R2 lEAS, lEAU lEAX, lEAY lOS, lOU lOX, lOY PSHS PSHU PUlS PUlU STS, STU STX, STY TFR R1, R2 ABX The instructions of the S6809 have been broken down into six different categories. They are as follows: 8-Bit Operation (Table 4) 16-Bit Operation (Table 5) Index Register/Stack Pointer Instructions (Table 6) Relative Branches (Long and Short) (Table 7) Miscellaneous Instructions (Table 8) Hexadecimal Value Instructions (Table 9) Table 4. 8-Bit Accumulator and Memory Instructions Mnemonic(s) AOCA, AOCB AOOA, AOOB ANOA, AN DB ASl, ASlA, ASlB ASR, ASRA, ASRB BITA, BITB ClR, ClRA, ClRB CMPA, CMPB COM, COMA, COMB OAA DEC, OECA, OECB EORA, EORB EXG R1, R2 INC, INCA, INCB lDA, lOB lSl, lSlA, lSlB lSR, lSRA, lSRB MUl NEG, NEGA, NEGB ORA, ORB ROl, ROlA, ROlB ROR, RORA, RORB SBCA, SBCB STA, STB SUBA, SUBB TST, TSTA, TSTB TFR, R1, R2 Operation Add memory to accumulator with carry Add memory to accumulator And memory with accumulator Arithmetic shift of accumulator or memory left Arithmetic shift of accumulator or memory right Bit test memory with accumulator Clear accumulator or memory location Compare memory from accumulator Complement accumulator or memory location Decimal adjust A-accumulator Decrement accumulator or memory location Exclusive OR memory with accumulator Exchange R1 with R2 (R1, R2 = A, B, CC, OP) Increment accumulator or memory location load accumulator from memory logical shift left accumulator or memory location logical shift right accumulator or memory location Unsigned multiply (A x B-O) Negate accumulator or memory OR memory with accumulator Rotate accumulator or memory left Rotate accumulator or memory right Subtract memory from accumulator with borrow Store accumulator to memory Subtract memory from accumulator Test accumulator or memory location Transfer R1 to R2 (R1, R2 = A, B, CC, OP) Operation Compare memory from stack pointer Compare memory from index register Exchange 0, X, Y, S, U or PC with 0, X, y, S, U or PC load effective address into stack pointer load effective address into index register load stack pOinter from memory load index register from memory Push any register(s) onto hardware stack (except S) Push any register( s) onto user stack (except U) Pull any register( s) from hardware stack (except S) Pull any register(s) from hardware stack (except U) Store stack pOinter to memory Store index register to memory Transfer 0, X, Y, S, U or PC to 0, X, Y, S, U or PC Add B accumulator to X (unsigned) Table 7. Branch Instructions Mnemonic(s) BCC, lBCC BCS, lBCS BEQ, lBEQ BGE, lBGE BGT, lBGT BHI, lBHI BHS, lBHS BlE, lBlE BlO, lBlO BlS, lBlS BlT, lBLT BMI, lBMI BNE, lBNE BPl, lBPl BRA, lBRA BRN, lBRN BSR, lBSR BVC, lBVC BVS, lBVS Branch Branch Branch Branch Branch Branch Branch Branch Branch Branch Branch Branch Branch Branch Branch Branch Branch Branch Branch Operation if carry clear if carry set is equal if greater than or equal (Signed) if greater (signed) if higher (unsigned) is higher or same (unsigned) if less than or equal (signed) if lower (unsigned) if lower or same (unsigned) if less than (Signed) if minus if not equal is plus always never to subroutine if overflow clear if overflow set NOTE: A, B, CC, or OP may be pushed to (pulled from) either stack with PSHS, PSHU, (PUlS, PUlU) instructions, Table 5. 16-Bit Accumulator and Memory Instructions Mnemonic(s) AOOO CMPO EXG 0, R lOO SEX STD SUBO TFR 0, R TFR R, 0 Table 8. Miscellaneous Instructions Mnemonlc(s) ANOCC CWAI NOP ORCC JMP JSR RTI RTS SWI, SWI2, SWI3 SYNC Operation Add memory to 0 accumulator Compare memory from 0 accumulator Exchange 0 with X, y, S, U or PC load 0 accumulator from memory Sign Extend B accumulator into A accumulator Store 0 accumulator to memory Subtract memory from 0 accumulator Transfer 0 to X, Y, S, U or PC Transfer X, y, S, U or PC to 0 5.97 Operation AN 0 condition code register AN 0 conditon code register, then wait for interrupt No operation OR condition code register Jump Jump to subroutine Return from interrupt Return from subroutine Software interrupt (absolute indirect) Synchronize with interrupt line I ~II~ 56809/568A09/568B09 Table 9. Hexadecimal Values of Machine Codes OP Mnem Mode 03 COM 6 2 05· OP Mnem Mode 31 LEAY T 33 LEAU Indexed 35 PULS , OP Mnem Mode 4+ 2+ 61 • T 4+ 2+ 63 COM I 5+ 2 65· I 6+ 2+ 07 ASR 6 2 37 PULU 5+ 2 67 ASR I 6+ 2+ 09 ROL 6 2 39 RTS 5 1 69 ROL I 6+ 2+ OB· OD TST OF CLR 10 Page 2 12 NOP Direct - Inherent Relative 6/15 1 6B· I 11 1 6D TST I 6+ 2+ 6 2 3D MUL 6 2 3F SWI Inherent 19 1 6F CLR Indexed 6+ 2+ 40 NEGA Inherent 2 1 70 NEG Extended 7 3 2 - 1 14· 16 LBRA 3B RTI 5 3 18· 42· 72· I 44 LSRA 2 1 74 LSR I 7 3 46 RORA 2 1 76 ROR I 7 3 48 ASLA/LSLA 2 1 78 ASL/LSL I 7 3 1A ORCC ImTed 3 2 4A DECA 2 1 7A DEC I 7 3 1C ANDCC Immed 3 2 4C INCA 2 1 7C INC I 7 3 ; 8 2 4E· 4 3 3 2 51 • 23 BLS 3 2 53 COMB 25 BLO/BCS 3 2 55· 27 BEQ 3 2 56 RORB 2 29 BVS 3 2 58 ASLB/LSLB 2B BMI 3 2 2D BLT 3 3 1E EXG 21 BRN 2F BLE , Relative • , 7E JMP • 81 CMPA 'I' 2 2 83 SUBD I 4 3 85 BIT A I 2 2 1 87· I 2 1 89 ADCA I 2 2 5A DECB 2 1 8B ADDA 2 2 2 5C INCB 2 1 8D BSR 7 2 2 5E· 2 1 • • Relative 8F· Legend NOTE: All unused opcodes are both undefined and illegal - Number of MPU cycles (less possible push/pull or indexed-mode cycles) # Number of program bytes • Denotes unused opcode 5.98 56809/568A09/568B09 Table 9. Hexadecimal Values of Machine Codes (Continued) OP Mnem Mode UP Mnem Mode Mode OP Mnem -# ., , 91 CMPA 4 2 C4 ANDB Yy: 2 93 SUBD 6 2 2 4 2 C8 EDRO 2 2 F9 ADCB I 5 3 FB ADDB I 5 3 I 6 3 6 3 ,', ,. 97 STA 99 ADCA 4 2 4 2 CA DRB CC LDO h 4 9B ADDA 90 JSR AO SUBA 3 .: Qll;~" 95 BITA 9F STX 5 ,:"ffitil~.jjf;;~;~;Fi!i C6 LDB 2 !~!!\INDl!i·: , I F7 STB 2 ~y <'. Direct Indexed " 2 7 2 5 2 4+ 2+ (':0Ixt·": ,.' ,. FD STD 3 3 FF STU 3 Im0ed ' 3 .. , . . ~xtehded , " ; , 01 CMPB 2 "' ; CE LDU 2 ~ ~ " ,'. " " 4 2 03 AOOD 6 2 1022 LBHI +, 5(6) 4 D5 BITB 4 2 1024 LBHS/LBCC I 5(6) 4 4 2 1026 LBNE I 5(6) 4 L 5(6) 4 5(6) 4 5(6) 4 Relative 5(6) 4 Inherent 20 2 5 4 ,: .;\; '~,> :<;::l~?~'l(;~i:l1:;i~lnln1iii0Jrtl, ::':, 7 1093 CMPO Oir~ct 3 " : A2 SBCA 4+ .. , 2+ 'n~!~~;; . " h <-Y<- " .. <\:.' '1~!,~6il(l~:::~: ' A4 ANDA 4+ 2+ D7 STB A6 LOA 4+ 2+ D9 ADCB 4 2 1028 LBVC A8 EORA 4+ 2+ DB ADOB 4 2 102A LBPL AA ORA 4+ 2+ OD S10 . 5 2 102C LBGE 6+ 2+ DF STU Direct 5 2 102E LBGT AC CMPX AE LOX 81 CMPA ., t , , \< $' EO SU8B 5+ ,Indeled 4+ 2+ 4+ 2+ 4+ 2+ '~}~~,:.. 5 3 E4 AND8 103F SWI/2 .~:; 108C CMPY < '·,·,:i~;~~~;pMR~j:; 83 SUBD 7 3 E6 LOB 4+ 2+ 109E LDY 85 BITA 5 3 E8 EORB 4+ 2+ 10A3 CMPO 87 STA 5 3 EA ORB 4+ 2+ 10AE LDY 89 AOCA 5 3 EC LDO 5+ 2+ 10B3 CMPO 8B AOOA 5 3 EE LOU 5+ 2+ 10BE LOY BO JSR 8 3 Extended 6 3 F1 CMPB CO SUBB Immed 2 2 F3 AOOO C2 SBCB Immed 2 2 F5 BITB 8F STX , ; " yY *$l1tttll~a~,,;~',::, E2 SBCB , I , , , Ind~xed Exterded j 6 3 7+ 3+ 6+ 3+ 8 4 7 4 10CE LOS Immed 4 4 6 3 5 3 100F STS Direct 7 3 10EF STS Indexed 6+ 3 5 3 10FF STS Extended 7 4 " Extended NOTE: All unused opcodes are both undefmed and Illegal 5.99 ~II~ S6809/S68A09/S68B09 Table 9. Hexadecimal Values of Machine Codes (Continued) OP Mnem Mode OP Mnem Mode OP Mnem 1183 CMPU Immed 119CCMPS Direct 11B3CMPU NOTE: All unused opcodes are both undefined and illegal 5.100 Mode Extended PRELIMINARY DATA SHEET S1602 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER Features D Full or Half Duplex Operation - Can Receive and Transmit Simultaneously at Different Baud Rates. D Completely Static Circuitry D Fully TTL Compatible. D Completely Programmable - Data Word Length, Number of Stop Bits, Parity. D Three-state Output Capability D Start Bit Generated Automatically D Single Power Supply: +5V D Data and Clock Synchronization Performed Automatically D Standard 40-Pin Dual-in-Line Package D Double Buffered - Eliminates Timing Difficulties D Plug In Compatible with Western Digital TR1602A, TR1863, Fujitsu 8868A Pin Configuration Block Diagram TR. TR J TR. " TR5 TR. TRl TRz TR, Vee r+r+r+r+r+r+.--+-...--------.-+---.R '"" r---++--TRC " SIS °N.C. mc EPE Vss WlS, RRD WlS 2 RRs SBS RR, PI RRs CRl RRs TRs RR. TR, RR J TRs 'L~ " CRL RR2 TRs RR, TR. PE TR J FE TR2 DE TR, SFD TRo RRC TRE DRR THRl DR THRE RI 5.101 MR I AMII~ 51602 General Description The AMI S1602 is a programmable Universal Asynchronous Receiver/Transmitter (UART) fabricated with N -Channel silicon gate MOS technology. All control pins, input pins and output pins are TTL compatible, and a single + 5 volt power supply is used. The U ART interfaces asynchronous serial data from terminals or other peripherals, to parallel data for a microprocessor, computer, or other terminal. Parallel data is converted by the trans- mitter section of the U ART into a serial word consisting of the data as well as start, parity, and stop bit(s). Serial data is converted by the receiver section of the UART into parallel data. The receiver section verifies correct code transmission by parity checking and receipt of a valid stop bit. The UART can be programmed to accept word lengths of 5, 6, 7, or 8 bits. Even or odd parity can be set. Parity generation checking can be inhibited. The number of stop bits can be programmed for one, two, or one and one-half when transmitting a 5-bit code. Absolute Maximum Ratings * Vee Pin Potential to VssPin ........................................................ -0.3Vto + +7.0V Input Voltage ...................................................................... -0.3V to + 7.0V Operating Temperature ................................................................ O°C to +70°C Storage Temperature .............................................................. - 55 ° C to + 150 ° C *Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheets. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Capacitance: TA =25°; f=IMHz; VIN=OV Symbol Parameter Max. Unit Input Capacitance for all Inputs pF Guaranteed Operating Conditions (Referenced to Vss) Parameter Operating Temperature Supply Voltage Vss V IH O°C to +70°C Logic Input High Voltage VIL Logic Input Low Voltage Symbol Vee Min. Typ. Max. Unit 4.75 5.0 5.25 V 0.0 0.0 0.0 V O°C to +70°C 2.2 - O°C to +70°C -0.3 - Vee +0.8 V V D.C. Characteristics (Guaranteed Operating Ranges Unless Otherwise Noted.) Symbol Min. Typ. Max. Unit IlL Parameter Input Leakage Current (VIN=O to 5.25V, Vee=5.25V) - - 1.4 rnA ILZ Output Leakage Current for 3-State (VOUT = OV to Vee, SFD=RRD=VIH) -20 - +20 /AA VOL Output Low Voltage (lOL = 1.8mA) - - 0.4 V VO H Output High Voltage (IOL = - 200/AA) 2.4 - - V 70 - rnA lee - Vee Supply Current 5.102 AMII~ 81602 A.C. Characteristics (Guaranteed Operating Ranges Unless Otherwise Noted.) Typ. Max. Unit Clock Frequency for RRC and TRC (Duty Cycle = 50%) DC - 800 kHz tpwe CRL Pulse Width, High 200 - ns Symbol fc Parameter Min. tpWT THRL Pulse Width, Low 180 - tpwR DRR Pulse Width, Low 180 - tpwM MR Pulse Width, High 150 - Coincidence Time (Figure 3 and Figure 8) 180 - tHOLD Hold Time (Figure 3 and Figure 8) 20 - - tSET Setup Time (Figure 3 and Figure 8) 0 - - ns - - 350 ns - - 350 ns te tpDo tpDl Propagation Delay Time High to Low, Output (CL = 130pF + 1TTL) Propagation Delay Time Low to High, Output (CL = 130pF + 1TTL) ns ns ns ns ns Pin Description Pin 1 2 3 4 Function Label Vee N.C. VSS RRD 5 -12 Power Supply - normally at +5V. No connection. On the S1602 this is an unconnected pin. On the TR1602A this is a -12V supply. -12V is not needed on the S1602 and thus the N.C. pin allows the S1602 to be compatible with the TR1602A. This is normally at OV or ground. Receive Register Disconnect. A high logic level, VIR, on this pin disconnects the Receiver Holding Register outputs from the data outputs RRs - RRI on pin 5 - 12. Receiver Holding Register Data. These are the parallel outputs from the Receiver Holding Register if the RRD input is low (VId. Data is (LSB) right justified for character formats of less than eight bits, with RRI being the least significant bit. Unused MSBs are forced to a low logic output level, VOL' 13 PE Parity Error. This output pin goes to a high level if the received parity does not agree with that programmed by the Even Parity Enable input (pin 39). This output is updated as each character is transferred to the Receiver Holding Register. The Status Flag Disconnect input (pin 16) allows additional PE lines to be tied together by providing an output disconnect capability. 14 FE Framing Error. This output pin goes high if the received character has no valid stop bit. Each time a character is transferred to the Receiver Holding Register, this output is updated. The Status Flag Disconnect input (pin 16) allows additional FE lines to be tied together by providing an output disconnect capability. 15 OE Overrun Error. This output pin goes high if the Data Received Flag (pin 19) did not get reset before the next character was transferred to the Receive Holding Register. The Status Flag Disconnect input (pin 16) allows additional OE lines to be tied together provip.ing an output disconnect capability. 16 SFD Status Flag Disconnect. When this input is high, PE, FE, OE, DR and THRE outputs are forced to high impedance Three State allowing bus sharing capability. 5.103 AMII~ 81602 Pin Description (Continued) Pin Label 17 RRC Receive Register Clock. This clock input is 16x the desired receiver shift rate. 18 19 DRR DR Data Received Reset. A low level input, V IL, clears the Data Received (DR) line. 20 RI Receiver Input. Serial input data enters on this line. It is transfered to the Receiver Register as determined by the character length, parity and number of stop bits. When data is not being received, this input must remain high, VIR. 21 MR Master Reset. A high level pulse, VIR, on this input clears the internal logic. The transmitter and Receive Registers, Receiver Holding Registers, FE, OE, PE, DRR are reset. In addition, the serial output line is set to a high level, Vo H . 22 THRE Transmitter Holding Register Empty. This output will go high when the Transmitter Holding Register completes transfer of its contents to the Transmitter Register. The high level indicates a new character may be loaded into the Transmitter Holding Register. 23 THRL Transmitter Holding Register Load. When a low level, V IL , is applied to this input, a character is loaded into the Transmitter Holding Register. The character is transferred to the Transmitter Register on a low to high level, VIR, transition as long as the Transmitter Register is not currently in the process of transmitting a character. If a character is being transmitted, the transfer is delayed until the transmission is completed. The new character is then transferred simultaneously with the start of the serial transmission of the new character. 24 TRE 25 TRO Transmitter Register Empty. Goes high when the Transmitter Register has completed the serial transmission of a full character including the required number of stop bits. A high will be maintained until the start of transmission of the next character. Transmitter Register Output. Transmits the Transmitter Register contents (Start bit, Data bits, Parity bit and Stop bit(s)) serially. Remains high, Vo H , when no data is being transmitted. Therefore, start of transmission is determined by transition of the Start bit from high to low level voltage, VOL' 26-33 Function Data Received. When a complete character has been received and transferred to the Receiver Holding Register, this output goes to the high level, VOH. Transmitter Register Data Inputs. The THRL strobe loads the character on these lines into the Transmitter Holding Register. If WLS 1 and WLS 2 have selected a character of less than 8 bits, the character is right justified to the least significant bit, TRI with the excess bits not used. A high input level, VIR, will cause a high output level, Vo H , to be transmitted. 34 CRL Control Register Load. The control bits, (WLS lo WLS 2 , EPE, PI, SBS), are loaded into the Control Register when the input is high. This input may be either strobed or hard wired to the high level. 35 PI Parity Inhibit. Parity generation and verification circuitry are inhibited when this input is high. The PE output will be held low as well. When in the inhibit condition the Stop bit(s) will follow the last data bit on transmission. 36 SBS Stop Bit(s) Select. A high level will select two Stop bits, and a low level selects one Stop bit. If 5-bit words are selected, a high level will generate one and one-half Stop bits. 5.104 ~IIe 81602 Pin Description (Continued) Pin Label Function Word Length Select. The state of these two (2) inputs determines the character length (exclusive of parity) as follows: 37,38 39 EPE 40 TRC WORD LENGTH WLS2 WLSI LOW LOW 5 bits LOW HIGH 6 bits HIGH LOW 7 bits HIGH HIGH 8 bits Even Parity Enable. A high voltage level, VIH, on this input will select even parity, while a low voltage level, V1L , selects odd parity. Transmitter Register Clock. The frequency of this clock input should be 16 times the desired baud rate. Figure 1. Receiver Operating Timing , START , ~-OA-TA-+-:"T"I---'I RI\ RR,- RR a, PE, OE, FE OR / " ' _ - - - - ........ SEE FIG. 2 FOR DETAil " STOP START I ',STOP i ! I I X~____ I \I tIL- I ------------+I~ I ORR I OATAJ lJ U) / \. Figure 2. Timing for Status Flags, RR1 thru RRs and DR 2 10 3 11 12 13 14 15 RRC NOMINAL RI *r---------- I I BIT CENTER STOP BIT I I -!-'i PE, FE _ _ _ _ _ _ _ _ _ _ _ I, RR,-RR S OE -----------'*: .~.~---------- 1+-_--"-'- ORR MAX 500n5 OR 5.105 MIN 500n, +1/2 CLOCK AMII~ 81602 Figure 3. Transmitter Operating Timing SEE FIG. 4 FDA DETAIL TAl ~ TAB _ _--t-__J X i DATA ~-L...... I I :UI ----+I-n" I \ 1 ) THAL i-/ X,...------D-A-TA---------- ~---, ~ I((J/r-----~'~\~I---------- 'I 1 I r-~I-FO-A-D-E-T-AI-L-------- ! U: THAF 1 TAE I SEE FIG. 6 I I ,...~I_~I~ 1 1 ----:-1---, I n I I I iI I I I ~~I--~I-----~~~I----------~ I : I I Ii TAO \ STAAT ) '-_/ 1 I I l. . I (DATA " I--D-AT-A----.---- ,/~TAAT STOP .... '--_/ STOP SEE FIG. 5 FOR DETAIL Figure 4. Data Input Load Cycle .r: ----=-----:. .---=---' -- ------ - THAL 5.106 \:.._---- AMII~ 81602 Figure 5. Transmitter Output Timing(1) INPUT TRC CRI CFI CR2 CF2 CR3 CF3 CR4 CF4 INPUT THRL OUTPUT THRE TO TRANSMITTER HOLDING REGISTER -0) - OUTPUT TRE OUTPUT TRO NOTES: 1. When the positive transition 01 THRL is 500ns or more before the falling edge of TRC (CF2 in the figure), TRE is enabled at CF2. But, when 500ns>(!»Ons, TRE-is invalid between CF2 and CF3. 2. THRE goes to low during 500ns Max. from the positive transition of THRL. 3. TRE goes to low during 500ns Max. from the first falling edge of TRC after THRE goes to low with TRE high. 4. TRO goes to low (START BIT) during 500ns Max. from the first rising edge of TRC after TRE goes to low. 5. THRE goes to high during 500ns Max. from the falling edge of TRC after START BIT is enabled. Figure 6. Transmitter Output Timing (2) INPUT TRC INPUT THRL OUTPUT THRE OUTPUT TRE OUTPUT TRO NOTES: 2·5, refer to Figure 5. 6. TRANSMITTER REGISTER EMPTY goes to high during 500ns Max. from the 15th rising edge of TRe after STOP BIT is enables. 5.107 • 51602 Figure 7 .Input After Master Reset Figure 9. Status Flag Output MR SFD PE FE THRL VIL\r --.. -------- OE DR THRE RI Figure 8. Control Register Load Cycle :~~~ VIH - SBS ___ !JI.,'- PI EPE ~tpD1 ~ ~ Figure 10. Data Output -==::-=---=-==~\ RRD I'-------------JI CRL RRa ~RR1 5.108 -------r ~VOH r VOL ~--1- t pDO S1602 Figure 11. Transmitting Sequence Flowchart (Note that the 51602 can simultaneously transmit and receive at two different bau d rates) The frequency inputto TRC should be 16 times the desired transmission frequency. For example. if transmission is to take place at 300 bps the input to TRC should be a 16 x 300 = 4,800 Hz clock This gets rid of any glitches. It is important to return Master Reset to a Low level and maintain it there throughout transmission LOAD TIlE CONlROLREGlSTER r---------, PUT THE PROPER VOlTAGES 011 1'H£ COffTIIOLREGlSTER _PINS PlNMUMIER 35 PlNMAME PI 36 SIS NoII:1f the system uses a constant data format the most economical method of programming the S1602 is to simply hard wire pins 34-39 to the appropriate voltage - Vcc or GND. If the system the S1602 will be used in could be using a variable data format, the best approach is to program the control regisler via software control signals. To do this, start out by wiring the Control Register inpul pins (pin 34-39) directly to the lower five (5) data bits (pins 26-30) as shown in Figure 11 a. By pulsing either CRL or THRL (but not althe same time!) you can control whelher the data on the Transmitter Register lines will be senllo Ihe Transmitting Register or 10 the Control Register. Notelhal CRL should be returned to Low and held there. If more than one S1602 will be used in a design, the inputs to TR,-TRs can be wire ORed together to a common 8-bit data bus (Figure 11 b). To eliminate bus contention problems. THRL (pin 23) can be used as a chip selecl A similar arrangement can be used to monitor the transmitter status outputs over a Single bus line. All Transmitter Holding Register Empty (THRE, pin 22) pins ean be wire ORed together to produce a single System THRE signal. When this common line goes High. the syslem controller can poll each S1602 separately by using the SFD (pin 16) pin as a THRE status chip select Select whether parity generation and detection is to be enabled (Low) or inhibited (High). Select the number of stop bits. If the data word length programmed on pins 37 and 38 is 6. 7. or 8 bits. the number of stop bits can be 1 (SBl low) or 2 (SBS High). If the data word length is chosen to be 5 bits, the number of stop bits can be 1 (SBS low) or 1 112 (SBS High). 37,31 WL"WL, Select the length of your data word: 5, 6, 7 or 8 bits. Pin 37 Pin 38 39 EPE 0111 Word Length LOW LOW 5 lOW HIGH 6 7 HIGH LOW HIGH HIGH 8 If PI (Pin 35) is Low. EPE will allow you to choose even (EPE High) or odd (EPE Low) parity. If PI is High. EPE is ignored The informalion on the five pins initialized above has to be loaded into the control register by a high on CRl. This input may be either strobed or hard-wired to the high level The data word should be input to the UART right-Iustified to the LSB (TR,) The Low level on THRL transfers the word on TRs- TR, tothe Transmitter HOlding Register. The low-to-High transition transfers the word from the Transmitter Holding Register to the Transmitter Register itself and starts transmission The Low level on THRL will load the previous word into the transmitter register. load the new word into the transmitter holding register, and start transmission Wait until the Transmitter Holding Register has been emptied into the Transmitter Register before another word is read Into the Transmitter Holding Register: otherwise. a word waiting in Ihe Transmitter Holding Register could be accidentally overwritten and lost. 5.109 AMII~ 51602 Figure11a. Figure 11b. 39...-------, 81602 38~--....., 331----------. 321----------. 311----------. 301--------. 291--------. 281-----....., 271------. 261-----. 371------. 36 t---- 35t-CRL 34 I- 33 ~--+-+-I-++------- ~ 311---1-+--+-~-+------- TRs TR4 TR3 TR2 TR, 30 ~--+-+-I_+-4------_ 29~-+-+-""""'------- I DATA TO BE SENT 23t-- 28 ~--+--+-<~------27~-+--4--------­ 26~~--------- 81602 CRL THRL 2 3 1 - - - - - - - - - - - - THRL 33 ~--I-+-+~--+-+-+'" 321--~1__+_+_+_+__+_+_4 31 I--~I__+_+_+_+_+...... 30 1----4-.j.-.4...~_4 291----4-.j.-.4...--1--4 281-----If--+-+..... 271-----+--..... 261----+---4 If the system uses a constant data format the most economical method of programming the S1602 is to simply hard wire pins 34-39 to the appropriate voltage - Vee or GND. 23t-- If the system the S1602 will be used in could be using a variable data format, the best approach is to program the control register via software control signals. To do this, start out by wiring the Control Register input pins (pin 34-39) directly to the lower five (5) data bits (pins 26-30) as shown above. By pulsing either CRL or THRL (but not at the same time!) you can control whether the data on the Transmitter Register lines will be sent to the Transmitting Register or to the Control Register. Note that CRL should be returned to Low and held there. 81602 33 ~+-4-+-+-+-l--+-+_+'" 321---+-1-+-+_+_+__+-+-4 311---+-I-+-+_+_l-I-.... 30...-+-+---lH-+-+...... 291--+-+-+-++1 281--+-I-+-+-..... 271---+-1--+-4 26 t--+-r--. 23 CRLc If more than one S1602 will be used in a design, the inputs to TR 1-TRs can be wire ORed together to a common 8-bit data bus to eliminate bus contention problems, THRL (pin 23) can be used as a chip select. CRLB ------TR, TRe This example illustrates how to string the inputs to several 1602' s together in a wiredOR situation, using a function enable pin as chip select. A similar arrangement can be used to monitor the transmitter status outputs over a single bus line. All Transmitter Holding Register Empty (THRE, pin 22) pins can be wire ORed together to produce a single System THRE signal. When this common line goes High, the system controller can poll each S1602 separately by using the SFD (pin 16) pin as a THRE status chip select. A lay-out much like this one can be used to string the output signals (either data or status messages) from several 1602 's together on a common bus. 5.110 51602 Figure 12. Receiving Sequence Flowchart (Note that the S1602 can simultaneously transmit and receive at two different baud rates) The frequency input to RRC should be t6 times the desired transmission frequency. For example, if transmission is to take place at 300 bps the input to RRC should be a t 6 x 300 = 4,800 Hz clock. This gets rid of any glitches. It is important to return Master Reset to a Low level and maintain it there throughout transmission. Nole: If more than one S1602 will be used in your design, the outputs from RRI-RRB can be wire ORed together to a common bus (similar to the arrangement in Fig. lIb.) To eliminate bus contention problems. RRO (pin 4) can be used as a chip select. LOAOTHE CONTROL REGISTER r---------,I PUT THE PROPER VOLTAGES ON THE CONTROL REGISTER INPUT PINS I I I I PIN NUMBER 35 Select whether parity generation and detection is to be enabled (Low) or inhibited (High) 36 I I I 37,38 , Select the number of stop bits. If the data word length programmed on pins 37 and 38 is 6, 7, or 8 bits. The number ot stop bils can be I (SBS Low) or 2 (SBS High). If the data word length is chosen as 5 bits, the number of stop bits can be 1 (SBS Low) or 1 112 (SBS High). WL2,WL, : I I I I I 39 A similar setup can be used to monitor the receiver status outputs of several S1602's using a Single set of bus lines All Parity Error pins (PE, pin 13) can be wire ORed together to produce a single System Parity Error signal. When this line goes High, the system controller can poll each S1602 separately by using the SFO (pin 16) pin as a status flag chip select. An equivalent, independent wired-OR/polling setup can be used for each of the Framing Error (PE, Pin 14). Overrun Error (DE, pin 15) and Data Received (DR, pin 19) status Signals EPE : Select the length of your data word; 5, 6, 7 or 8 bits. Pin 37 LOW LOW HIGH HIGH Pin 38 LOW HIGH LOW HIGH Data Word Length L. _ _ _ _ _ _ _ _ _ .J 5 6 7 8 If PI (Pin 35) is Low, EPE will allow you to choose even (EPE High) or odd (EPE Low) parity. If PI is High, EPE is ignored. The information on the five pins initialized above has to be loaded into the control register by a high on CRL. This input may be either strobed or hard-wired to the high level. This resets DR (pin 19) in preparation for the next incoming character. If the data word is less than 8 bits long the word is right-justified to the LSB (RR j , pin 12)_ The data on ARB-RR j is valid only if RRD (pin 4) is low; otherwise, the RRg-RA j lines are left to float. 5.111 S2350 Universal Synchronous ReceiverlTransmitter Features General Description 0 500kHz Data Rates 0 Internal Sync Detection 0 Fill Character Register 0 Double Buffered Input/Output 0 Bus Oriented Outputs 0 5-8 Bit Characters 0 0 Odd/Even or No Parity The S2350 Universal Synchronous Receiver Transmitter (USRT) is a single chip MOSILSI device that totally replaces the serial-to-parallel and parallel-to-serial conversion logic required to interface a word parallel controller or data terminal to a bit-serial, synchronous communication network. The USRT consists of separate receiver and transmitter sections with independent clocks, data lines and status. Common with the transmitter and receiver are word length and parity mode. Data is transmitted and received in a NRZ format at a rate equal to the respective input clock frequency. Error Status Flags 0 Single Power Supply I + 5VI 0 Input/Output TTL-Compatible Block Diagram IPs Pin Configuration 1381 151 CS 1391 NOB, 1401 NOB2 POE NPB Tep AR Rep 141 131 1361 1'31 GNO NOB2 Vee NOB, NPB 'fliS POE RCP cs TCP TSO iiiiE FCT SWE SCR ROD TBMT RD, RPE RD2 RDR RDJ RDA RD_ iiii RDs RESET RD6 1371 TBMTI91 171 FeT 181 1'01 RPE RORI"I 1'21 ROA 1'41 seR APE RCR RDA 5.112 Do RD7 0, RSI ~ m ~ ~ 0_ 07 05 06 AMII~ 82350 Data messages are transmitted as a contiguous character stream, bit synchronous with respect to a clock and character synchronous with respect to framing or "sync" characters initializing each message. The USRT receiver compares the contents of the internal Receiver Sync Register with the incoming data stream in a bit transparent mode. When a compare is made, the receiver becomes character synchronous formatting a 5, 6, 7, or 8-bit character for output each character time. The receiver has an output buffer register allowing a full character time to transfer the data out. The receiver status outputs indicate received data available (RDA), receiver overrun (ROR), receive parity error (RPE) and sync character received (SCR). Status bits are available on individual output lines and can also be multiplexed onto the output data lines for bus organized systems. The data lines have tri-state outputs. (TSO). The transmitter is buffered to allow a full character time to respond to a transmitter buffer empty (TBMT) request for data. Data is transmitted in a NRZ format changing on the positive transition of the transmitter clock (TCP). The character transmitter fill register is inserted into the data message if a data character is not loaded into the transmitter after a TBMT request. Typical Applications o Computer Peripherals D Communication Concentrators o o o The USRT transmitter outputs 5, 6, 7, or 8-bit characters with correct parity at the transmitter serial output Integrated Modems High Speed Terminals Time Division Multiplexing D Industrial Data Transmission Absolute Maximum Ratings Ambient Temperature Under Bias ..................................................... " O°C to + 70°C Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65°C to + 150°C Positive Voltage on any Pin with Respect to GROUND ............................................ " + 7V Negative Voltage on any Pin with Respect to GROUND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.5V Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0.75W D.C. (StatiC) Electrical Characteristics * (Vee = 5.0V ± 5%; TA = OOC to + 70°C unless otherwise noted) Symbol Parameter Min. Typ. Max. Unit Vee +0.8 10 V Condition VIR Input High Voltage 2.0 VIL Input Low Voltage -0.5 IlL Input Leakage Current VOH Output High Voltage VOL Output Low Voltage CIN Input Capacitance pF IOL= 1.6mA VIN = OV; f = 1.0MHz COUT Output Capacitance 12 pF VIN=OV; f= 1.0MHz Icc Vee Supply Current 100 rnA No Load; Vee = 5.25V 2.4 V p,A V +0.4 10 V VIN=OTO Vee V IOH= -100p,A *Electrical characteristics included in this advanced product description are objective specifications and may be subject to change. 5.113 AMII~ 82350 A.C. (Dynamic) Electrical Characteristics· (VCC = 5.0V ± 5%; TA = O°C to + 70°C unless otherwise noted) Symbol TCP,RCP Condition Parameter Clock Frequency Input Pulse Widths PTCP Transmit Clock 900 nsec CL =20pF PRCP Receive Clock 900 nsec ITTL Load PRST Reset 500 nsec PTDS Transmit Data Strobe 200 nsec PTFS Transmit Fill Strobe 200 nsec PRSS Receive Sync Strobe 200 nsec PCS Control Strobe 200 nsec PRDE Receive Data Enable 400 nsee Note 1 PSWE Status Word Enable 400 nsec Note 1 PRR Receiver Restart 500 nsee Switching Characteristics TTSO Delay, TCP Clock to Serial Data Out 700 TTBMT Delay, TCP Clock to TBMT Output 1.4 fJ-sec TTBMT Delay, TDS to TBMT 700 nsec TSTS Delay, SWE to Status Reset 700 nsec TRDO Delay, SWE, RDE to Data Outputs 400 nsec ITTL Load THRDO Hold Time SWE, RDE to Off State 400 nsec CL = 130pF TDTS Data Set Up Time TDS, TFS, RSS, CS 0 nsec TDTH Data Hold Time TDS 700 nsec TDTI Data Hold Time TFS, RSS 200 nsec TCNS Control Set Up Time NDBl, NDB2, NPB, POE 0 nsec TCNH Control Hold Time NDBl, NDB2, NPB, POE 200 nsec TRDA Delay RDE to RDA Output 700 nsec NOTE 1: Required to reset status and flags. 5.114 nsec 52350 FiguFe 1. Timing Waveform RESET NOB1 NOB. NPB POE ---------/r-- PAST ~L ~----TC_NH,'I "r ___ _ VIH '--------~ Figure 2. Timing Waveform Tep TSO \ TBMT -4 ,- ~'---RDO IVOH " 5.115 VOL ~------_./ / '- - 82350 Figure 3. Transmitter Timing Diagram ~RES=ET~ ~~NDTE1 I ______________________ ______________________________ __~n~ ~ I I _TS_D_ _...:.Iii '1ST.' FCT I , , , LIsfj: ~PAD CHAR. ~ L :' -: I J ®'T:C J : C J"TIT :': J: I:': :': DATA CHAR. ALL "1" S ;";';""--""'U DATA CHAR. ---.!--SYNC CHAR.----.l --,--- I TBMT I!r-------,I~ u u u u NOTE 1 OATA TRANSMISSION WILL START ON THE RRST LOW TO IIGH TRANSmoN OF TCP AFTER RESET IS LOW. THE IHmAL RESET PULSE SHOULO NOT OCCUR UNTIL 100 MlCROSECONOS AFTER POWER IS APPLIEO. Figure 4. Receiver Timing Diagram ~RE~SE~T____~n~ I ______________ ________________ ___________________ ~ ~ u I I ]§,:::r II . . rl :::ThTJ .; ;: .; . :-----:1:1 --~ II---~ ~RP~E_ _~I J: C I :': ,,~... I I LLAIT[\1!TI : ' : I~~~I' L J ~S!!]s[,: I ,"'00' 'I] ~ U~II--:,:II:']Aslp]: 'Toil IfI-'~ - ---:J IL..------------~:.!.; r-- ; I ~ 5.116 -+j r I~---IL- _ _ _ _ r ---.J ______ L L 52350 Pin Definitions Pin (1) (2) Label GND (14) Vee RESET (15-22) DO-D7 (38) (24) Function Ground +5 Volts ±5% MASTER RESET. A VIR initializes both the receiver and transmitter. The Transmitter Shift Register is set to output a character of all logic 1's. FCT is reset to VOL and TBMT set to VOH indicating the Transmitter Holding Register is empty. The receiver status is initialized to a VOL on RPE, SCR, and RDA. The sync character detect logic is inhibited until a RR pulse is received. DATA INPUTS. Data on the eight data lines are loaded into the Transmitter Holding Register by TDS, the Transmitter Fill Register by TFS, and the Receiver Sync Register by RSS. The character is right justified with the LSB at DO. For word lengths less than 8 bits, the unused inputs are ignored. Data transmission is LSB first. TRANSMIT DATA STROBE. A VIL loads data on DO-D7 into the Transmitter Holding Register and resets TBMT to a VOL. TFS (23) TRANSMIT FILL STROBE. A VIL loads data on DO-D7 into the Transmitter Fill Register. The character in the Transmitter Fill Register is transmitted whenever a new character is not loaded in the allotted time. RECEIVER SYNC STROBE. A VIL loads data on DO-D7 into the Receiver Sync Register. SCR is set to VOH whenever data in the Receiver Shift Register compares with the character in the Receiver Sync Register. (9) TBMT (6) TSO (36) TCP (26-33) RD7-RDO TRANSMIT BUFFER EMPTY. A VOH indicates the data in the Transmitter Holding Register has been transferred to the Transmitter Shift Register and new data may be loaded. TBMT is reset to VOL by a VIL on TDS. A VIR on RESET sets TBMT to a VOH. TBMT is also multiplexed onto the RD7 output (26) when SWE is at VIL and RDE is at VIR. TRANSMITTER SERIAL OUTPUT. Data entered on DO-D7 are transmitted serially, least significant bit first, on TSO at a rate equal to the Transmit Clock frequency, TCP. Source of the data to the transmitter shift register is the Transmitter Holding Register or Transmitter Fill Register. TRANSMIT CLOCK. Data is transmitted on TSO at the frequency of the TCP input in a NRZ format. A new data bit is started on each negative to positive transition (V IL to VIH) of TCP. RECEIVED DATA OUTPUTS RDO-RD7 contain data from the Receiver Output Register or selective status conditions depending on the state of SWE and RDE per the following table: (26) (27) (34) (35) (33) (32) (31) (30) (39) (28) RD7 RD6 SWE RDE RDO RD1 RD2 RD3 RD4 RD5 X X VIL VIL X X X X X X FCT TBMT VIL VIR RDA ROR RPE SCR VOL VOL DB7 DB6 VIR VIL DBO BD1 DB2 DB3 DB4 DB5 X X VIH VIH X X X X X X X - Output is in the OFF or Tri-State condition DBO - LSB of Receiver Output Register DB7 - MSB of Receiver Output Register The two unused outputs are held at VOL in the output status condition. 5.117 AMII~ . 82350 Pin Definitions (continued) Pin Function Label (35) RECEIVE DATA ENABLE. A VIL enables the data in the Receiver Output Register onto the, output data lines RDO - RD7. The trailing edge (V IL to VIR transition) of RDE resets RDA to the VOL condition. FCT FILL CHARACTER TRANSMITTED. A VOH on FCT indicates data from the Transmitter Fill Register has been transferred to the Transmitter Shift Register. FCT is reset to VOL when data is transferred from the Transmitter Holding Register to the Transmitter Shift Register, or on the trailing edge (VIL to VIR) of the SWE pulse, or when RESET is VIR. FCT is rilUltiplexed onto the RD6 output (27) when SWE is at VIL and RDE is at VIR· RECEIVER SERIAL INPUT. Serial data is clocked into the Receiver Shift Register, least significant bit first, on RSI at a rate equal to the Receive Clock frequency RCP. (25) RSI (37) RCP RECEIVE CLOCK. Data is transferred from RSI input to the Receiver Shift Register at the frequency of the RCP input. Each data bit is entered on the positive to negative transition (VIR to VId of RCP. (12) RDA RECEIVED DATA AVAILABLE. A VOH indicates a character has been transferred from the Receiver Shift Register to the Receiver Output Register. RDA is reset to VOL on the trailing edge (V IL to VIR transition) of RDE, by a VIL on RR or a VIR on RESET. RDA is multiplexed onto the RDO output (33) when SWE is VIL and RDE is VIR. (8) SCR SYNC CHARACTER RECEIVED. A VOH indicates the data in the Receiver Shift Register is identical to the data in the Receiver Sync Register. SCR is reset to a VOL when the character in the Receiver Shift Register does not compare to the Receiver Sync Register, on the trailing edge (V IL to VIR transition) of SWE, by a VIL on RR or a VIR on RESET. SCR is multiplexed onto the RD3 output (30) when SWE is a VIL and RDE is VIR. (34) STATUS WORD ENABLE. A VIL enables the internal status conditions onto the output data lines RDO-RD7. The trailing edge of SWE pulse resets FCT, ROR, RPE, and SCR to VOL. (11) ROR RECEIVER OVERRUN. A VOH indicates data has been transferred from the Receiver Shift Register to the Receiver Output Register when RDA was still set to VOH. The last data in the Output Register is lost. ROR is reset by the trailing edge (VIL to VIR) of SWE, a VIL on RR, a VIR on RESET or a VOL to VOH transition of RDA. ROR is multiplexed onto the RD1 output (32) when SWE is VIL and RDE is VIR. (10) RPE RECEIVER PARITY ERROR. A VOH indicates the accumulated parity on the received character transferred to the Output Register does not agree with the parity selected by POE. RPE is reset with the next received character with correct parity, the trailing edge (VIL to VIR) of SWE, a VIL on RR or a VIR on RESET. RPE is multiplexed onto the RD2 output (31) when SWE is VIL and RDE is VIR. 5.118 AMII~ 82350 Pin Definitions (continued) Pin Function Label (13) RECEIVER RESTART. A VIL resets the receiver section by clearing the status RDA, SCR, ROR, and RPE to VOL. The trailing edge of tm (V IL to VIR) also puts the receiver in a bit transparent mode to search for a comparison, each bit time, between the contents of the Receiver Shift Register and the Receiver Sync Register. The number of data bits per character for the comparison is set by NDBl and NDB2. After a compare is made SCR is set to VOH, the sync character is transferred to the Receiver Output Register, and the receiver enters a word synchronous mode framing an input character each word time. NOTE: Parity is not checked on the first sync character but is enabled for every succeeding character. (39) NDBl NUMBER DATA BITS. The number of Data Bits per character are determined by NDBl and NDB2. The number of data bits does not include the parity bit. NDB2 NDBl CHARACTER LENGTH 5 Bits 6 Bits 7 Bits 8 Bits For character length less than 8 bits, unused inputs are ignored and unused outputs are held to VOL. Data is always right justified with DO and RDO being the least significant bits. (3) NPB NO PARITY BIT. A VIR eliminates generation of a parity bit in the transmitter and checking of parity in the receiver. With parity disabled, the RPE status bit is held at VOL. (4) POE PARITY ODD/EVEN. A VIR directs both the transmitter and receiver to operate with even parity. A VIL forces parity operation. NPB must be VIL for parity to be enabled. (5) CONTROL STROBE. A VIL loads the control inputs NDBl, NDB2, POE, and NPB into the Control Register. For static operation, CS can be tied directly to ground. 5.119 56821 1568A21 1568821 PERIPHERAL INTERFACE ADAPTER (PIA) Features o 8-Bit Bidirectional Bus for Communication with the MPU o Two Bidirectional 8-Bit Buses for Interface to Peripherals o Two TTL Drive Capability on all A and B Side Buffers D TTL Compatible o Static Operation o Two Programmable Control Registers o Two Programmable Data Direction Registers General Description o Four Individually-Controlled Interrupt Input Lines: Two Usable as Peripheral Control Outputs o Handshake Control Logic for Input and Output Peripheral Operation o High-Impedance Three-State and Direct Transistor Drive Peripheral Lines The S68211S68A211S68B21 are peripheral Interface Adapters that provide the universal means of interfacing peripheral equipment to the S6800/S68AOO/S68BOO Microprocessing Units (MPU). This device is capable of interfacing the MPU to peripherals through two 8-bit bidirectional peripheral data buses and four control lines. No external logic is required for interfacing to most peripheral devices. o Program Controlled Interrupt and Interrupt The functional configuration of the PIA is programmed by the MPU during system initialization Each of the peripheral data lines can be programmed to act as an Disable Capability o CMOS Compatible Peripheral Lines Block Diagram Pin Configuration TiiliA.J8-J===========F~~~~ GNO 40 CAl PAD 39 CA2 PAl 38 lRQA PA2 37 lRIl8 PA3 36 RSD RSI 1. PA4 35 PA5 34 RESET PA6 33 00 32 01 PA7 PBD 5.120 10 56821 568A21 568821 31 02 30 03 29 04 PBl 11 pa2 12 PB3 13 28 05 PB4 14 27 06 PB5 15 26 07 PB6 16 25 PB7 17 24 CBl 18 23 CS2 CB2 19 22 CSI CSD 21 RIW .MIII~ S6821 IS68A21 IS68B21 General Description (Continued) input or output, and each of the four control/interrupt lines may be programmed for one of several control modes. This allows a high degree of flexibility in the overall operation of the interface. chip select lines, two register select lines, two interrupt request lines, read/write line, enable line and reset line. These signals, in conjunction with S6800/S68AOO/ S68BOO VMA output, permit the MPU to have complete control over the PIA. VMA may be utilized to gate the input signals to the PIA. The PIA interfaces to the S6800/S68AOO/S68BOO MPU s with an eight-bit bidirectional data bus, three Absolute Maximum Ratings: Symbol Rating Value Unit Supply Voltage -0.3 to +7.0 Vdc VIN Input Voltage -0.3 to +7.0 Vdc TA Operating Temperature Range 0° to +70° °C -55° to +150° °C 82.5 °C/W Vcc Storage Temperature Range Tstg Thermal Resistance Bja Note: This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. Electrical Characteristics Vcc = 5.0V ± Symbol 5%, Vss = 0, TA = TL to TH unless otherwise noted. Characteristic Conditions Bus Control Inputs (R/W, Enable, Reset, RSO, RSl, CSO, CSl, CS2) VIH Input High Voltage VSS +2.0 - Vee Vdc VIL Input Low Voltage VSS-0.8 - VSS+0.8 Vdc lIN Input Leakage Current 2.5 MAdc VIN=O to 5.25 Vdc pF VIN=O, TA=25°C, f=1.0MHz CIN Capacitance - 1.0 - 7.5 Interrupt Outputs (IRQA, IRQB) VOL Output Low Voltage - - VSS+O.4 Vdc ILOAD=3.2 mAdc ILOH Output Leakage Current (Off State) - 1.0 10 MAdc VOH=2.4 Vdc COUT Capacitance - - 5.0 pF VIN=O, T A =25°C, f=1.0MHz Data Bus (DO- D7) VIH Input High Voltage VSS+2.0 - Vee Vdc VIL Input Low Voltage VSS -0.3 - VSS+0.8 Vdc MAdc ITSI Three State (Off State) Input Current - 2.0 10 VOH Output High Voltage VSS +2.4 - - Vdc ILOAD= -205MAdc VOL Output Low Voltage - - VSS+O.4 Vdc I LOAD = 1.6mAdc CIN Capacitance - - 12.5 pF VIN=O, TA =25°C f=1.0MHz 5.121 VIN=O.4 to 2.4 Vdc S6821 IS68A21 IS68B21 Electrical Characteristics (Continued) Symbol Characteristic Peripheral Bus (PAO-PA7, PBO-PB7, CAl, CA2, CBl, CB2) - Input Leakage Current lIN -~- R/W. Reset. RSO. CSO. CSI. CS2. CAl. CBl. Enable 1.0 2.5 fiAdc VIN=O to 5.25 Vdc 2.0 10 fiAdc VIN=O.4 to 2.4 Vdc fiAdc V1H=2.4 Vdc ITSI Three-State (Off State I Input Current PBO-PB7. CB2 IIH Input High Current PAO-PA7. CA2 -200 -1.0 IOH Darlington Drive Current PBO-PB7. CB2 III, Input Low Current PAO-PA7. CA2 -400 -1.3 .10 mAde VO= l.5 Vdc -2.4 mAde VIL=O.4Vdc Output High Voltage VOH Vdc PAO-P7. PBO-PB7. CA2. CB2 PAO-PA7. CA2 I LOAD = - 200fiAdc ILOAD=-lOfi Adc VSS+2.4 VCC-1.0 Output Low Voltage VOL Capacitance C 1N Vdc I LOAD =3.2mAdc 10 pF VIN=O. TA =25°C. f= 1.0MHz 550 mW VSS+O.4 Power Requirements PD I Power Dissipation A.C. (Dynamic) Characteristics Loading=30pF and one TTL load for PAO-PA7, PBO-PB7, CA2, CB2 = 130pF and one TTL load for DO-D7, IRQA, IRQB (VCC = + 5.0V ± 5%, TA = O°C to + 70°C unless otherwise noted) Peripheral Timing Characteristics: Vcc-5.0V±5%, Vss=OV, TA =TL to TH unless otherwise specified S6821 S68A21 S68B21 Units Symbol Parameter Min. t pDSU Peripheral Data Setup Time 200 135 100 ns t pDH Peripheral Data Hold Time 0 0 0 ns tCA2 to CA2 Negative Transition Max. Delay Time. Enable Negative Transition t RSl tr. tf t RS2 Delay Time. Enable Negative Transition to CA2 Positive Transition Rise and Fall Times for CAl and CA2 Input Signals Delay Time from CAl Active Transition to CA2 Positive Transition Min. Max. Min. Max. 1.0 0.670 0.5 fis 1.0 0.670 0.50 fiS 1.0 1.0 1.0 fiS 2.0 1.35 1.0 fis 1.0 0.670 0.5 fis 2.0 1.35 1.0 fiS Delay Time. Enable Negative Transition tpow t CMOS to Peripheral Data Valid Delay Time. Enable Negative Transition to Peripheral CMOS Data Valid PAO-PA7. CA2 5.122 S6821/S68A21/S68B21 Peripheral Timing Characteristics (Continued) S6821 Min. S68A21 Max. Min. S68B21 Symbol Parameter Max. tCB2 Delay Time, Enable Positive Transition to CB2 Negative Transition t DC Delay Time, Peripheral Data Valid to CB2 Negative Transition t RS1 Delay Time, Enable Positive Transition to CB2 Positive Transition PWCT Peripheral Control Output Pulse Width, CA2/CB2 tr. tf Rise and Fall Times for CBI and CB2 Input Signals 1.0 1.0 1.0 j.ls t RS2 Delay Time, CB I Active Transition to CB2 Positive Transition 2.0 1.35 1.0 j.ls tIR Interrupt Release Time, IRQA and IRQB 1.60 1.1 0.85 j.ls t RS3 Interrupt Response Time PWr Interrupt Input Pulse Width 500 500 500 ns tRL Reset Low Time* 1.0 0.66 0.5 j.ls 1.0 Min. Max. Units 0.5 j.ls 0.670 2.0 20 1.0 0.670 550 0.5 1.0 1.0 *The Reset line must be high a minimum of 1.0j.lS before addressing the PIA. Figure 2. Bus Read Timing Characteristics (Read Information from PIA) RS, CS, RNi .....-- 'ODR o.av OATA BUS Figure 3. Bus Write Timing Characteristics (Write Information into PIA) Figure 4. Bus Timing Test Loads l- ;ov 100·-071 I~av -------' RS, CS, RM 5,OV I 2.0V TEST POINT 0--r--""---4 ~~~~~1~ o,av C 130pF 2,Ov o.av 5.123 MMO)OOO OREQUIV j.ls ns 550 550 1.0 Figure 1. Enable Signal Characteristics ns 20 j.ls S6821 IS68A21 IS68B21 Bus Timing Characteristics (Vcc = + 5.0V ± 5%, VSS =0, TA =TL to TH unless otherwise noted.) 86821 868A21 868B21 8ymbol Parameter Min. ,tcyc(E) Enable Cycle Time 1000 666 500 ns PWEH Enable Pulse Width, High 450 280 220 ns 430 Max. Min. Max. Min. Units Max. PWEL Enable Pulse Width, Low tEr,tEf Enable Pulse Rise and Fall Times tAS Setup Time, Address and R/W Valid to Enable Positive Transition 160 tAH Address Hold Time 10 tOOR Data Delay Time, Read tOHR Data Hold Time, Read 10 10 10 ns tosw Data Setup Time, Write 195 80 60 ns tOHW Data Hold Time, Write 10 10 10 ns Figure 5. TTL Equiv. Test Load 280 25 ns 210 25 140 ns 10 220 Figure 6. CMOS Equiv. Test Load ns 70 10 320 ns 25 ns 180 Figure 7. NMOS Equiv. Test Load (PAO·PA7,PBO PB7,CA2,CB21 rfROONlY' [PAO - PAT, PBO, PB), CA2, CB21 ~r 50V ~ Vee u'" "l' ~~ _II TEST POINT v, e;: .. 3- MM06150 OREOUIV "l' R TESTPOINT~ MMO)OOO TEST POINT fCC OR EQUIV ~, C~40pF R = 12k ADJUST RLSO THAT II = 3,21llA WITH VI = O.4V AND Vee ~ 5.25V Figure 8. Peripheral Data Setup and Hold Times (Read Mode) I PAOPA)~2'V PBO PB) Figure 9. CA2 Delay Time (Read Mode; CRA-5 _ _ _ _--J,/ =CRA-3 =1, CRA-4 = 0) O.BV J"":p;.;;.;::-u-I-----C-1~ ----J tCA2 2'V ENABLE c \r \l.w- O.BV pW CT F 2AV * Assumes part was deselected during the previous E pulse. 5.124 Please contact your local AMI Sales Office for complete data sheet AMII~ S6821/S68A21/S68B21 Figure 10. CA2 Delay Time (Read Mode; CRA-5 = 1, CRA-3 = CRA-4 = 0) ENABLE;t;;BV Figure 11. Peripheral CMOS Data Delay Times (Write Mode; CRA-5 = CRA-3 = 1, CRA-4 = 0) ! Irlf 2 OV Figure 12. Peripheral Data and CB2 Delay Times (Write Mode; CRB-5 = CRB-3 = 1, CRB-4 = 0) Figure 13. CB2 Delay Time (Write Mode; CRB-5 = CRB-3 ENABLE ENABLE =1. CRB-4 =0) r- F\ ~ ~tCB2'-------'~ ~ j.--tRS1· 24V O'V 2.4V'-- CB2 CB2 Note: CB2 goes low as a result of the positive transition af Enable. Figure 14. CB2 Delay Time (Write Mode; CRB-5 = 1, CRB-3 = CRB-4 = 0) Figure 15. Interrupt Pulse Width and IRQ Response ENABL~20V<' PW, CAI,C A2 CBI, CB2 20V CSl CB2----tC-"~~ ~ X 2.0V O.8V iRTIii tRS3' ~ *Assumes Interrupt Enable Bits are set. *Assumes part was deselected during any previous E pulse. Figure 17. Reset Low Time. Figure 16. IRQ Release Time .OV ENABLE ~ "~f.o..;."f--O;';';'8-V~_-_-_-_tR_L~~~~~~_~~V- tlR~ ~ _JI nnr _ _ _ _ _ __ 2.'V *The Reset line must be a V,H for a minimum of 1.0,us before addressing the PIA. 5.125 S68H21 PERIPHERAL INTERFACE ADAPTER (PIA) Features General Description o 8-Bit Bidirectional Bus for Communication o o o o o o o o with the MPU Two Bidirectional 8-Bit Buses for Interface to Peripherals Two Programmable Control Registers Two Programmable Data Direction Registers Four Individually-Controlled Interrupt Input Lines: Two Usable as Peripheral Control Outputs Handshake Control Logic for Input and Output Peripheral Operation High-Impedance Three-State and Direct Transistor Drive Peripheral Lines Program Controlled Interrupt and Interrupt Disable Capability CMOS Compatible Peripheral Lines The S68H21 is a peripheral Interface Adapter that provides the universal means of interfacing peripheral equipment to the S68HOO Microprocessing Unit (MPU). This device is capable of interfacing the MPU to peripherals through two 8-bit bidirectional peripheral data buses and four control lines. No external logic is required for interfacing to most peripheral devices. The functional configuration of the PIA is programmed by the MPU during system initialization. Each of the peripheral data lines can be programmed to act as an input or output, and each of the four control/interrupt lines may be programmed for one of several control modes. This allows a high degree of flexibility in the overall operation of the interface. Pin Configuration Block Diagram i1iCiA3B 40 CAl PAD 39 CA2 PAl 38 IROA PA2 31 Tifi!B PAl 36 GNO RSO PA4 35 RSI PA5 34 lfESEf PA6 33 DO PAl 32 01 PBO 5.126 1. 10 S68H21 31 02 PBl 11 30 03 PB2 12 29 04 PB3 13 28 05 PB4 14 27 06 PB5 15 26 07 PB6 16 25 PBl 17 24 CSI CBl 18 23 CSf CB2 19 22 CSO 21 RIW AM/I. S68H21 General Description (Continued) The PIA interfaces to the S68HOO with an eight-bit bidirectional data bus, three chip chip select lines, two interrupt request lines, read/write line, enable line and reset line. These signals, in conjunction with the S68HOO output, permit the MPU to have complete control over the PIA. VMA may be utilized to gate the input signals to the PIA. Absolute Maximum Ratings Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .. -0.3 to +7.0V Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 to +7.0V Operating Temperature Range ........................................................................ 0° to +70°C Storage Temperature Range ...................................................................... -55° to + 150°C Note: This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. Electrical Characteristics Vcc = 5.0V ± 5%, Vss = 0, TA = O°C to +70°C unless otherwise noted. Symbol Parameter Min. VIH Input High Voltage VIL Input Low Voltage lIN Input Leakage Current R/W, Reset, RSO, RS1, CSO, CS2, CS1, CAl, CB1, Enable I TSI Three State (Off State) Input Current DO-D7, PBO-PB7, CB2 IIH Input High Current PAO-PA7, CA2 Input Low Current PAO-PA7, CA2 IlL VO H -200 Vdc Conditions Vss+0.8 Vde 2.5 /-lAde VIN=O to 5.25 Vde 2.0 10 /JAde /JAde VIN =O,4 to 2,4 Vde VIH = 2,4Vde mAde VIL =O,4Vdc -400 -1.3 -2,4 Vss +2,4 Vss+2,4 Vde Vdc I LOAD = - 205/JAde I LOAD = - 200/JAdc Vss +O,4 Vss +O,4 Vde Vdc I LOAD = L6mAdc I LOAD = 3.2mAde -10 /JAde /JAde mAde Output Low Voltage Output High Current Sourcing DO-D7 Other Outputs PBO-PB7, CB2 hOH PD Output Leakage Current C IN Capacitance COUT Unit Vee 1.0 DO-D7 Other Outputs IOH Max. Output High Voltage DO-D7 Other Output VOL Typ. Vss +2.0 Vss -0.8 -205 -100 -1.0 IRQA,IRQB -2.5 1.0 10 /JAde 550 mW DO-D7 PAO-PA7, PBO-PB7, CA2, CB2 Enable, R/W, Reset, RSO, RS1, CSO, CS1, CS2, CAl, CB1 12.5 10 pF pF 7.5 pF IRQA,IRQB 5.0 pF Power Dissipation VOH= 2.4Vde Vo= 1.5Vde, the current for driving other than TTL, e.g., Darlington Base VoH =2.4Vde VIN=O, TA=+25°C, f=1.0MHz Note: The PAO-PA7 Peripheral Data lines and the CA2 Peripheral Control line can drive two standard TTL loads. In the input mode, the internal pullup resistor on these lines represents a maximum of 1.5 standard TTL loads. 5.127 I AMII~ S68H21 A.C. (Dynamic Characteristics Loading=30pF and one TTL load for PAO-PA7, PBO-PB7, CA2, CB2 = 130pF and one TTL load for DO-D7, IRQA, IRQB (VCC=5.0V ±5%, TA =O°C to +70°C unless otherwise noted.) Read Timing Characteristics (Figure 1) Timing Characteristics (Vcc=5.0V±5%, Vss=O, TA =O°C to +70°C unless otherwise noted.) Symbol Parameter t pDSU Peripheral Data Setup Time 90 ns t pDH Peripheral Data Hold Time 0 ns tCA2 Delay Time, Enable Negative Transition to CA2 Negative Transition 0.4 /AS t RSl Delay Time, Enable Negative Transition to CA2 Positive Transition 0.4 /AS tr, Rise and Fall Times for CAl and CA2 Input Signals 1.0 /AS t RS2 Delay Time from CAl Active Transition to CA2 Positive Transition 0.85 /AS t pDW Delay Time, Enable Negative Transition to Peripheral Data Valid 0.4 /AS t CMOS Delay Time, Enable Negative Transition to Peripheral CMOS PAO-PA7, CA2 Data Valid 0.85 /AS tCB2 Delay Time, Enable Positive Transition to CB2 Negative Transition 0.4 /AS t DC Delay Time, Peripheral Data Valid to CB2 Negative Transition t RSl Delay Time, Enable Positive Transition to CB2 Positive Transition PWCT Peripheral Control Output Pulse Width, CA2/CB2 iT, Rise and Fall Times for CBl and CB2 Input Signals 1.0 /AS Delay Time, CBl Active Transition to CB2 Positive Transition 0.85 /AS tIR Interrupt Release Time, IRQA and IRQB 0.70 /AS t RS3 Interrupt Response Time 1.0 /AS PW 1 Interrupt Input Pulse Width 500 ns tRL Reset Low Time* 0.4 /AS tf tf t RS2 Min. Max. 2.0 *The Reset line must be high a minimum of 1.0",s before addressing the PIA. 5.128 Units ns 0.4 550 /AS ns Conditions Vc c-30% Vcc; Figure 6, Load C Please contact your local AMI Sales Office for complete data sheet AMlt. S68H21 Bus Timing Characteristics (VCC=5.0V ±5%, TA =O°C to +70°C unless otherwise noted.) Read Symbol Parameter tCYC(E) Enable Cycle Time Min. 0.4 liS PWEH Enable Pulse Width, High 0.18 liS 0.18 ns PWEL Enable Pulse Width, Low tAS Setup Time, Address and RIW to Enable Positive Transition tDDR Data Delay Time tH Data Hold Time 10 tAH Address Hold Time 10 t Er, tEf Rise and Fall Time for Enable Input Max. 55 Units ns 160 ns ns ns 25 ns Max. Units write Symbol Parameter Min. tCYC(E) Enable Cycle Time 0.4 PWEH PWEL Enable Pulse Width, High 0.18 liS Enable Pulse Width, Low 0.18 ns tAS Setup Time, Address and RIW to Enable Positive Transition 55 ns ns liS t DSW Data Setup Time 50 tH Data Hold Time 10 ns tAH Address Hold Time 10 ns t Er , tEf Rise and Fall Time for Enable Input 25 Figure 1. Peripheral Data Setup Time (Read Mode) PAO PA7=1 pso PS7 Figure 2. CA2 Delay Time (Read Mode; CRA-5=CRA-351, CRA-4=O) rs; 14V ENABLE ~~0':':'8V----_t::""'; ~tpDH tposJu..- _ ~ osv 'CA2 F 24V ""'1'""4V""--- ENA8LE _ _ _ _-J ns 0.8V * Assumes part was deselected during the previous E pulse. 5.129 • S6840/S68A40/S68840 PROGRAMMABLE TIMER Features General Description o o o o The S6840 is a programmable subsystem component of the S6800 family designed to provide variable system time intervals. o o o o o o Operates from a Single 5 Volt Supply Fully TTL Compatible Single System Clock Required (Enable) Selectable Prescaler on Time 3 Capable of 4MHz for the S6840, 6MHz for the S68A40 and 8MHz for the S68B40 Programmable Interrupts (IRQ) Output to MPU Readable Down Counter Indicates Counts to Go to Time-Out Selectable Gating for Frequency or Pulse-Width Comparison RESET Input Three Asynchronous External Clock and Gatel Trigger Inputs Internally Synchronized Three Maskable Outputs The S6840 has three 16-bit binary counters, three corresponding control registers and a status register. These counters are under software control and may be used to cause system interrupts and/or generate output signals. The S6840 may be utilized for such tasks as frequency measurements, event counting, interval measuring and similar tasks. The device may be used for square wave generation, gated delay signals, single pulses of controlled duration, and pulse width modulation as well as system interrupts. Block Diagram Pin Configuration RM RSO RSI RS2 CSo ENABLE (SYSTEM¢2) CSI 2B 27 07 06 05 04 ......_~ 26 25 03 ......_~ 24 02 01 00 22 23 21 20 10 19 o a: 11 lB o 12 17 13 16 14 15 .... z ~ r1 - Vss Vee RESET ii3 C3 03 G2 C2 02 5.130 G1 Ci 01 S6840/S68A40/S68840 Absolute Maximum Ratings Supply Voltage Vcc ................................................................................ -0.3 to +7.0V Input Voltage VIN ................................................................................. -0.3 to +7.0V Operating Temperature Range TA ..................................................................... 0° to +70°C Storage Temperature Range Tstg .................................................................. -55° to + 150°C Thermal Resistance BJA ..........................................................•...........•.......... 82.5°C/W Note: This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. Electrical Characteristics Vee = 5.0V ± 5%, VSS = 0, TA = O°C to +70°C unless otherwise noted. Symbol Parameter Min. Typ. Vm Input High Voltage Vss +2.0 V IL Input Low Voltage Vss -0.3 lIN Input Leakage Current ITS I Three State (Off State) Input Current V OH Output High Voltage Unit Vcc V Conditions Vss+0.8 V 1.0 2.5 /AA VIN=O to 5.25 V 2.0 10 /AA VIN =O.4 to 2.4 V V V I LOAD = - 205/AA I LOAD = - 200/AA Vss +O.4 Vss+O.4 V V I LOAD = 1.6mA I LOAD =3.2mA 10 /AA VOH =2.4V 550 mW DO-D7 All Others 12.5 7.5 pF VIN=O, TA=+25°C, f=1.0MHz IRQ 01,02,03 5.0 10 pF VIN=O, TA=+25°C, f=1.0MHz DO-D7 DO-D7 Other Outputs VOL Max. Vss +2.4 Vss +2.4 Output Low Voltage DO-D7 01-03, IRQ lLOH Output Leakage Current (Off State) PD C IN Capacitance IRQ 1.0 Power Dissipation COUT Bus Timing Characteristics Read (See Figure 1) S6840 Symbol Characteristic tCYCE PWEH PWEL tAS S68A40 S68B40 Min. Max. Min. Max. Min. Max. Unit 1.0 10 0.666 10 0.5 10 /As Enable Pulse Width, High 0.45 4.5 0.280 4.5 0.22 4.5 /AS Enable Pulse Width, Low 0.43 0.280 0.21 /As Setup Time, Address and R/W Valid to Enable Positive Transition 160 140 70 ns Enable Cycle Time tDDR Data Delay Time tH Data Hold Time 10 10 10 Address Hold Time 10 10 10 tAH t Er, tEf 320 Rise and Fall Time for Enable Input 25 5.131 220 25 180 ns ns ns 25 ns • S6840/S68A40/S68B40 Bus Timing Characteristics (Continued) Read (See Figure 1) S6840 Symbol Characteristic S68A40 S68B40 Min. Max. Min. Max. Min. Max. Unit 1.0 10 0.666 10 0.5 10 lAs 4.5 0.280 4.5 0.22 4.5 lAS tCYCE Enable Cycle Time PWEH Enable Pulse Width, High 0.45 PWEL Enable Pulse Width, Low 0.43 0.280 0.21 lAs Setup Time, Address and RIW Valid to Enable Positive Transition 160 140 70 ns t nsw Data Setup Time 195 80 60 ns tH Data Hold Time 10 10 10 ns tAH Address Hold Time 10 10 10 t AS t Er, tEf 25 Rise and Fall Time for Enable Input 25 ns ns 25 AC Operating Characteristics (See Figures 3 and 7) S6840 Symbol tr, tf PWL PW H tsu thd PW L , PW H tco tcrn tcmos tIR Characteristic Min. S68A40 Max. Input Rise and Fall Times (Figures 4 and 5) C, G and Reset Min. 1.0 S68B40 Max. Min. Max. Unit 0.500* 0.666* lAS Input Pulse Width (Figure 4) (Asynchronous Mode) C, G and Reset tCYCE+tsu +thd tCYCE+tsu+thd tCYCE + tsu + thd ns Input Pulse Width (Figure 5) (Asynchronous Mode) C, G and Reset tCYCE+tsu+thd tCYCE+tsu+thd tCYCE+tsu+thd ns 200 120 75 ns 50 50 50 ns 125 84 62.5 ns Input Setup Time (Figure 6) (Synchronous Mode) C, G and Reset C3 (-;- 8 Prescaler Mode only) Input Hold Time (Figure 6) (Synchronous Mode) C, G and Reset C3 (-;- 8 Prescaler Mode only) Input Pulse Width (Synchronous Mode) C3 (-;- 8 Prescaler Mode only) Output Delay, 01-03 (Figure 7) TTL (VOH = 2.4V, Load B) (VOH =2.4V, Load D) MOS (V oH =0.7 VDD, Load D) CMOS 700 450 2.0 460 450 1.35 340 340 1.0 ns ns Interrupt Release Time 1.2 0.9 0.7 lAs * tr and tf~ tCYCE 5.132 lAS AMII~ S6840/S68A40/S68B40 Figure 1. Bus Read Timing Characteristics (Read Information from PTM) Figure 2. Bus Write Timing Characteristics (Write Information into PTM) ~---tcy'E------lI~ ENABLE ENABLE RS, Cs, R,w RS, Cs, RtW DATA BUS DATA BUS Figure 3. Input Pulse Width Low Figure 4. Input Pulse Width High PW,_ &i-a Gi-jj3 t, ___ _ PW _ H Figure 5. Input Setup and Hold Times Figure 6. Output Delay ENABLE ~GI-G3 -J'" 01-03 RESET 5.133 \~t co ' tan' tcmos Please contact your local AMI Sales Office for complete data sheet AMlt. S6840/S68A40/S68B40 Figure 7. I RQ Release Time ENABLE iRii T~',")'~ Figure 8. Bus Timing Test Loads LOAOA (00·07) LOAD B (01.02.03) ~ ) 5.0V RL = 1.25k RL =2.5k .... ...... TEST POINT _ MM06150 OR EnUIV. ..... ,.... TEST POINT" - lUk 40pF ;::~ ~, ~~ --:------ MMD6150 OR EQUIV. ~~ '1' 130pF ;:: Vee OF DEVICE UNDER TEST 11.7k MMD7000 OR EQUIV. ~~ ~ ~ --: ~~ MM07000 OR EQUIV. '* LOAD C (fRQONLV) () 5.0V LOAD D (CMOS LOAD) 3k ""'''~1 TEST POINT " I'"' lDOpF ;::~ ~ 5.134 PRELIMINARY DATA SHEET 868045 CRT CONTROLLER (CRTC) Features o o o o Generates Refresh Addresses and Row Selects Generates Video Monitor Inputs: Horizontal and Vertical Sync and Display Enable o Cursor and/or Display Can Be Delayed 0, 1 or 2 Clock Cycles o Four Cursor Modes: - Non-Blink - Slow Blink - FastBlink - Reverse Video With Addition of a Single TTL Gate o Three Interlace Modes - Normal Sync - Interlace Sync - Interlace Sync and Video o o o Full Hardware Scrolling Low Cost; MC6845/SY6545 Pin Compatible Text Can Be Scrolled on a Character, Line or Page Basis o o Addresses 16K Bytes of Memory o Character Font Can Be 32 Lines High With Any Width o Two Complete ROM Programs Screen Can Be Up to 128 Characters Tall By 256 Wide NMOS Silicon Gate Technology TTL-Compatible, Single + 5 Volt Supply Pin Configuration Block Diagram 00-07 TO REFRESH MEMORY v" VSYNC iiffif PR06RAMSELECT RAO} HAl ROW ADDRESSES RA2 FOR CHARACTER GENERATORS RA3 HA< PROG PROCESSOR INTEftFACE TO CRT VCC Vss DISPLAY ENABLE CURSOR ClK W CS RESET ENABLE CONTROL lOGIC 00-07 ADDRESS REGISTER 5.135 AMII~ 868045 General Description The S68045 CRT Controller performs the complex interface between an S6800 Family microprocessor and a raster scan display CRT system. The S68045 is designed to be flexible yet low cost. I t is configured to both simplify the development and reduce the cost of equipment such as intelligent terminals, word processing, and information display devices. The CRT Controller consists of both horizontal and vertical counting circuits, a linear address counter, and control registers. The horizontal and vertical counting circuits generate the Display Enable, HSYNC, VSYNC, and RAO-RA4 signals. The RAO-RA4lines are scan line count signals to the external character generator ROM. The number of characters per character row, scan lines per character row, character rows per screen, and the horizontal and vertical SYNC position and width are all mask programmable. The S68045 is capable of addressing 16K of memory for display. The CRT may be scrolled or paged through the entire display memory under MPU control. The cursor control register determines the cursor location on the screen, and the cursor format can be programmed for fast blink, slow-blink, or non-blink appearance, with programmable size. By adding a single TTL gate, the cursor can even be reversed video. The device features two complete, independent programs implemented in user-specified ROM. Either set of programmable variables (50/60Hz refresh rate, screen format, etc.) is available to the user at any time. The S68045 is pin compatible with theMC6845, operates from a single 5-volt supply, and is designed using the latest in minimum-geometry NMOS technology. Absolute Maximum Ratings Supply Voltage Vee ............ , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3°C to +7.0°C Input Voltage VIN .................................................................... -0.3V to +7.0V Operating Temperature Range TA ......................................................... O°C to +70°C Storage Temperature Range Tstg ..................................................... - 55°C to + 150°C Bus Timing Characteristics Symbol Parameter tcycE PWEH Enable Cycle Time 1.0 Enable Pulse Width, High 0.45 PWEL Enable Pulse Width, Low 0.43 I-'S tAS Setup Time, CS and RS Valid to Enable Positive Transition 160 ns tH Data Hold Time 10 ns tAH Address Hold Time 10 tEr. tEf Rise and Fall for Enable Input tnsw Data Setup Time Min. Typ. Max. I-'s 25 5.136 I-'s ns 25 195 Unit ns ns Condition 868045 Electrical Characteristics Ve e=5.0V±5%; Vss=O, TA=O°C to +70°C unless otherwise noted Typ. Symbol Parameter Min. Input High Voltage 2.0 VIR -0.3 Input Low Voltage VIL Input Leakage Current 1.0 lIN Output High Voltage 2.4 VOH VOL PD Ouput Low Voltage Power Dissipation CIN Input Capacitance COUT Output Capacitance Minimum Clock Pulse Width, Low Clock Pulse Width, High PWCL PWCH fc Max. Vec 0.8 2.5 0.4 600 DO-D7 All Others All Outputs 12.5 10 10 160 200 10,000 tcr, tcf Clock Frequency Rise and Fall Time for Clock Input 2.5 20 tMAD tRAD tDTD Memory Address Delay Time Raster Address Delay Time Display Timing Delay Time tHSD Horizontal Sync Delay Time Vertical Sync Delay Time Cursor Display Timing Delay Time 160 160 300 300 tVSD tCDD 300 300 Systems Operation The S68045 CRTC generates all of the signals needed for the proper operation of a CRT system including HSYNC, VSYNC, Display Enable, Cursor control signals (refer to Figure 1), the refresh memory addresses (MAO-MA13) and row addresses (RAO-RA4). The CRTC's timing is derived from the CLK input, which is divided down from the dot rate counter. The CRTC, which is compatible with the 6800 family, communicates with the MPU by means of the standard 8-bit data bus. This primary data bus uses a buffered interface for writing information to the display refresh RAM by means of a separate secondary data bus. This arrangement allows the MPU to forget about the display except for those time periods when data is actually being changed on the screen. The address bus for the refresh RAM is continuously multiplexed between the MPU and the CRTC. Unit Vdc Vdc !JAdc Vdc Vdc mW pF pF pF Condition ILOAD= -lOO!JA ILOAD = 1.6mA ns ns MHz ns ns ns ns ns ns ns Since the MPU is allowed transparent read/write access to the display memory, the refresh RAM appears as just another RAM to the processor. This means that the refresh memory can also be used for program storage. Care should be taken by the system designer, however, to insure that the portion of memory being used for program storage is not actively displayed. Displayed Data Control Display Refresh Memory Addresses (MAO-MAl3) - 14 bits of address provide the CRTC with access of up to 16K of memory for use in refreshing the screen. Row Addresses (RAO-RA4) - 5 bits of data that provide the output from the CRTC to the character generator ROM. They allow up to 32 scan lines to be included in a character. Cursor - This TTL compatible, active high output indicates to external logic that the cursor is being displayed. 5.137 568045 Figure 1. Typical CRT Controller System MAIN PROCESSOR HORIZONTAL SYNC HIGH REFRESH RAM SPEED TIMING CRT CDHlROLLER VERllCAL SYNC CLOCK CURSOR. DISPLAY ENABLE. DOT RATE COUNTER The character address of the cursor is held in a register, so the cursor's position is not lost even when scrolled off the screen. CRT Control All three CRT control signals are TTL compatible, active high outputs. Display Enable - Indicates that valid data is being clocked to the CRT for the active display area. Vertical Sync (VSYNC) - Makes certain the CRTC and the CRT's vertical timing are synchronized so the picture is vertically stable. Horizontal Sync (HSYNC) - Makes certain the CRTC and the CRT's horizontal timing are synchronized so the picture is horizontally stable. Processorlnteriace All processor interface lines are three state, TTL/MOS compatible inputs. Chip Select (CS)-The CS line selects the CRTC when low to write to the internal Register File. This signal should only be active when there is a valid stable address being decoded from the processor. Register Select - The RS line selects either the Address Register (RS= "0") or one of the Data Registers (RS = "1") of the internal Register File. To address one of the software programmable registers (R12, R13, R14 or R15 in Table 2) first access the Address Register (CS=O, RS=O) and write the number of the desired register. Then write into the actual register by addressing the data register section (CS=O, RS=l) and enter the appropriate data. Write (W) - The W line allows a write to the internal Register File. Data Bus (DO-D7) - The data bus lines (DO-D7) are write-only and allow data transfers to the CRTC internal register file. Enable (E) - The Enable signal enables the data bus input buffers and clocks data to the CRTC. This signal is usually derived from the processor clock, and the high to low transition is the active edge. 868045 Control Clock (CLK) - The clock signal is a high impedance, TTL/MOS compatible input which assures the CRTC is synchronized with the CRT itself. The CLK signal is divided down by external circuitry from the dot rate counter. The CLK frequency is equal to 5.138 868045 the dot rate frequency divided by the width of a single character block (including framing) expressed in dots, CLK is equal to the character rate. Program (PROG) - The voltage on this pin determines whether the screen format in ROM 0 (PROG LOW) or ROM 1 (PROG HIGH) is being used. Reset (RES) - The RES input resets the CRTC. An (active) low input on this line forces these actions: control registers in the 68045, most of which are mask programmed. The exceptions are the Address Register, the two Start Address Registers (R12 & R13) and the Cursor Location Registers (R14 & R15). All software programmable registers are write only. The Address Register is 5 bits long. The software programmable registers are made available to the data lines whenever the chip select (CS) goes low. When CS goes high, the data lines show a high impedance to the microprocessor. a) MAO-MA13 are loaded with the contents of R12/R13 (the start address register). b) The horizontal, vertical, and raster address counter are reset to the first raster line of the first displayed character in the first row. c) All other outputs go low. Horizontal Total Register (RO) - The full horizontal period, expressed in character times, is masked in RO. (See Figure 2a.) Note that none of the internal registers are affected by RES. RES on the CRTC differs from the reset for the rest of the 6800 family in the following aspects: Horizontal SYNC Position Register (R2)- The contents of R2 (also in character times) should be slightly larger than the value in R1 to allow for a non-displayed right border. (See Figure 2a.) a) MAO-MA13 and RAO-RA4 go to the start addresses, instead of FFFF. b) Display recommences immediately after RES goes high. Sync Width Register (R3) - The width of the HSYNC pulse expressed in character times is masked into the lower four bits of R3. The width of the HSYNC pulse has to be non-zero. Internal Register Description - The width of the VSYNC pulse is masked into the upper There is a bank of 15 Horizontal Displayed Register (Rl) - This register contains the number of characters to be actually displayed in a row. (See Figure 2a.) Figure 2a. Approximate Timing Diagram I I I I I......c--------IHORIZONTAL TOTAL RO ---------;----------~.I !. . . ,----------HORIZONTAL DISPLAY R1 _ _ _ _ _ _ HORIZ DISPLAY ------~ ENABLE -'.~I RIGHT MARGIN I II I I I r-I I I LEFT c-----••I MARGIN f o. o l. : I I I 1 I......c---------HORIZONTAL SYNC POSITION R2-------~ HSYNC II I I I HSYNC WIDTH R3 I I --------'-1------------------------' FOR MORE EXACT DIAGRAMS REFER TO THE BACK OF THE OATA SHEET. THE HORIZONTAL DISPLAY ENABLE IS ANDED WITH THE VERTICAL DISPLAY ENABLE TO PROOUCE THE DISPLAY ENABLE AT PIN 18. NOTE THE (a) AGURE IS TIMED IN TERMS OF INDIVIDUAL CHARACTERS, WHEREAS THE (b) AGURE IS TIMED IN TERMS OF CHARACTER ROWS. 5.139 I 868045 four bits of R3 without any modification, with the exception that all zeroes will make VSYNC 16 characters wide. Vertical Total Register (R4) - This register contains the total number of character rows - both displayed and non-displayed - per screen. This number is just the total number of scan lines used divided by the number of scan lines in a character row. If there is a remainder, it is placed in R5. (See Figure 2b). Vertical Total Adjust Register (R5) - See description of R4. A fractional number of character row times is used to obtain a refresh rate which is exactly 50HZ, 60HZ, or some other desired frequency. (See Figure 2b). Enable signal is delayed. This feature allows the system designer to account for memory address propagation delay through the RAM, ROM, etc. Maximum Scan Line Register (R9) - Determines the number of scan lines per character row including top and bottom spacing. Cursor Start Register (RIO) - Contains the raster line where the cursor start (see Figure 4). The cursor start line can be anywhere from line 0 to line 31. The cursor can be in one of the following formats. Non-blinking Slow blinking (1/16) the vertical refresh rate) Vertical Displayed Register (R6) - This register contains the total number of character rows that are actually displayed on the CRT screen. (See Figure 2b). Vertical SYNC Position (R7) - R7 contains the position of the vertical SYNC pulse in character row times with respect to the top character row. Increasing the value shifts the data up. (See Figure 2b). Interlace Mode Register (R8) - R8 controls which of the three available raster scan modes will be used (See Figure 3). - Non-interlace or Normal sync mode Interlaced sync mode Interlaced sync and Video mode The Cursor and Display Enable outputs can be delayed (skewed) 0, 1 or 2 clock cycles with respect to the refresh memory address outputs (MAO-MAI3). The amount the cursor is delayed is independent of how much the Display Fast blinking (1/32 the vertical refresh rate) Reverse video (non-blinking, slow blinking, or fast blinking) The reverse video cursor needs an external TTL XOR gate to be placed in the video circuit. To implement the reverse video cursor, the cursor start line (RlO) should be set to line 0 and the cursor end line (Rll) should be set to whatever is in R9 so that the cursor covers the entire block. On the circuit level, the output from the Cursor pin (pin 19) should be taken through the XOR gate along with the output from the shift register. (See Figure 5.) With this setup the character whose memory address is in the cursor register (RI4/ R15) will have it's background high (because Cursor along is high) but the character itself will be off (because both cursor and the character are both high. Figure 2b. Approximate Timing Diagram II II ......I - - - - - - - - - - V E R T I C A L TOTAL R 4 - - - - - - - - - - - - . 1 - - - -____ I 1 I I I I f - - - - - - - - - - V E R T I C A L DISPLAYED R6 - - - - - - - - - - ' 1 I 11 . . . . . . VERTICAL DISPLAY I i_ __I II I I VERTICAL ADJUST R5 I - r---- I ~I-:I--.,----~I ENABLE I I I I ~~TRTG~~ -----..J I....-- I I TOP I I I~MARGIN I VSYNC I 1 - - - - - - VERTICAL SYNC POSITION R7-----------l~ 5.140 I ! VERTICAL SYNC WIDTH R3 AMII~ 868045 Figure 3. Interface Control SCAN LINE ADDRESS SCAN LINE ADDRESS SCAN LINE ADDRESS o - o o o o o --0 -1 -1 -3 -2 -5 -3 -7 -4 --1 00000 o 0 o o - -5 o o - -6 -- - -7 ODD fiELD EVEN fiELD NORMAL SYNC MODE 1 -----3 - - - --5 ---7 ODD FIELD EVEN FIELD INTERLACE SYNC AND VIDEO MODE 3 INTERLACE SYNC MODE 2 Figure 4. Cursor Control MODE CURSOR DISPLAY MODE 1 Non-Blink 2 Cursor Non-Display 3 Blink, 1/16 Field Rale 4 Blink, 1/32 Field Rale I 1 I I ~----4-----4------~---.. ON OFF ON I --+i I I ~ I BLINK PERIOD = 16 OR 32 TIMES fiELD PERIOD + 10 -+-+-+--+---+-+-+11-+-+-+--+---+-+-+CURSOR START ADR. = 9 CURSOR END ADR. = 9 Memory Start Address Register (R12/R13) - These two software programmable, write-only registers taken together contain the memory address of the first character displayed on the screen. Register R12 contains the upper six bits of the fourteen refresh memory address bits, while R13 contains the lower eight bits. The Linear Address Generator begins counting from the address in RI2!R13. By changing the starting address, the display 10 --eMK8-ffi.f9-~87-- 10 11 -+-+--+-+-+-+-+- 11 CURSOR START ADR. = 9 CURSOR END ADR. = 10 -+-+-+-+-4-+-+--+-+-+-+-4-+-+-CURSOR START ADR. = 1 CURSOR END ADR. = 5 can be scrolled up or down through the 16K memory block by character, line or page. If the value in R12/R13 is near the end of the 16K block the display will wrap around to the front. Cursor Address Register (Rl41R15) - These two software programmable, write-only registers, taken together, contain the address in memory of the cursor character. 5.141 868045 Figure 5. Implementation of a Reversed Video Cursor MAO· MA13 r--'--- _ RAM S68045 / - - - - - - - - - - , , ~ f-----..........,~l RAO·RA4 t ASCII CHARACTER ----"'~~-~~ CHARACTER GENERATOR ROM CURSOR \} I I SHIFT h ~~~ TO VIDEO '-_ _ _ _ _ _ _ _ _ _ RE_GI_ST_ER_ _ Register R14 contains the upper six bits and register R15 contains the lower eight bits of the character. Cursor position is associated with an address in memory rather than with a position on the screen. This way cursor position is not lost when the display is scrolled. Address Register - The five bit address register is uni· que in that it does not store any CRT-related information, but is used as the address storage register in an in· direct access of the other registers. When the Register Select pin (RS) is low, the address register is accessed by DO-D4. When RS is high, the register whose address is in the address register is accessed. CRTC Internal Description There are four counters which determine what the CRTC's output will be (see Block Diagram): 1) 2) 3) 4) Horizontal Counter Vertical Counter Row Address Counter Linear Address Counter The first two counters, and to some extent the third, take care of the physical operation ofthe monitor. The Linear Address Counter, on the other hand, is responsible for the data that is displayed on the screen. Surrounding these counters are the registers RO-R15. Coincidence logic continuously compares the contents of each counter with the contents of the register(s) associated with it. When a match is found, appropriate action is taken; the counter is reset to a fixed or dynamic value, or a flag (such as VSYNC) is set, or both. Twosetsofregisters - ThestartAddressRegister(Rl21 R13) and the Cursor Position Register (RI4/RI5) - are programmable via the Data lines (DO-D7). The other registers are all mask programmed. There are two ROM programs available on each chip. Selection of which ROM program will be accessed is performed by the PROG pin. Horizontal Counter The Horizontal Counter produces four output flags: HSYNC, Horizontal Display Enable, Horizontal Reset to the Linear Address Counter, and the horizontal clock. The Horizontal Counter is driven by the character rate clock, which was derived from the dot rate clock (see Table 1). Immediately after the valid display area is entered the Horizontal Counter is reset to zero but continues incrementing. HSYNC is the only one of the four signals which is fed to an external device (the CRT). The Horizontal Counter is compared to registers RO, R2 and R3 to give an HSYNC of the desired frequency (RO), position (R2) and width (R3). (See Figure 2a.) Horizontal Display Enable is an internal flag which, when ANDed with Vertical DE, is output at the Display Enable pin. The Horizontal Counter determines the proper frequency (RO), and width (Rl). The Horizontal Reset and the horizontal clock are actually identical signals: the only difference is the way they are used. Both are pulsed once for each scan line, so their frequency is equal to the character rate clock frequency divided by the entire horizontal period (display, non-display and retrace) expressed in character times 5.142 AMII~ 868045 Table 1. Comparison of all CRTC Clocks LOCATION OF CLOCK NAME DOT RATE CLOCK CHARACTER RATE CLOCK CONTROLLING REGISTER DIVIDED BY: EXTERNAL TOTAL WIDTH OF A CHARACTER BLOCK IN DOTS EXTERNAL INPUT HORIZONTAL CLOCK ROW ADDRESS CLOCK PRODUCES EXTERNAL CHARACTER RATE CLOCK TOTAL NUMBER OF CHARACTERS IN A ROW RO HORIZONTAL CLOCK INTERNAL TOTAL NUMBER OF SCAN LINES IN A CHARACTER ROW R9 ROW ADDRESS CLOCK INTERNAL TOTAL NUMBER OF CHARACTER ROWS PER SCREEN R4, R5 VERTICAL CLOCK Table 2. CRTC Internal Register Assignment ADDRESS REGISTER CS RS REGISTER # 4 3 2 1 MASK PROGRAMMABLE 0 a a a a 1 1 1 1 a a a a a X 1 1 1 1 X 1 1 1 1 X a a 1 1 X REGISTER FILE 0 a 1 0 1 X RO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 HORIZONTAL TOTAL HORIZONTAL DISPLAYED HORIZONTAL SYNC POSITION HORIZONTAL SYNC WIDTH VERTICAL TOTAL VERTICAL TOTAL ADJUST VERTICAL DISPLAYED VERTICAL SYNC POSITION INTERLACE MODE MAX SCAN LINE ADDRESS CURSOR START CURSOR END R12 R13 R14 R15 X START ADDRESS (H) START ADDRESS (L) CURSOR (H) CURSOR (L) ADDRESS REGISTER X DON'T CARE (which is stored in RO). The horizontal clock drives the Vertical and Row address Counters. The horizontal reset is discussed with the Linear Address Counter. is compared to registers R3, R4, R5 and R7 to give a VSYNC of the desired frequency (R4, R5), position (R7) and width (R3). (See Figure 2b.) Vertical Counter Vertical Display Enable is an internal flag which, when ANDed with Horizontal DE, is output at the Display Enable pin. The Vertical Counter determines the proper frequency (R4, R5) and width (R6). The Vertical Counter produces three output flags: VSYNC, Vertical Display Enable, and Vertical Reset to the Linear Address Counter. The Vertical Counter is driven by the horizontal clock. Immediately after vertical retrace the Vertical Counter is reset to zero but continues incrementing. VSYNC is the only one of the three signals which is fed to an external device (the CRT). The Vertical Counter Vertical Reset is pulsed once for each screen. The frequency of Vertical Reset is equal to the horizontal clock frequency divided by the total number of scan lines in a screen (which is equal to (R4XR9)+R5). It will be discussed with the Linear Address Counter. 5.143 AMite 868045 Figure 6. Bus Write Timing ~------Ic"E-----~ PWEL ENABLE RS.~ DATA BUS Row Address Counter The Row Address Counter produces three sets of output: the five Row Address lines (RAO-RA4), the Row Address Cursor Enable flag and the Row Address Reset flag. The Row Address Counter is driven by the horizontal clock. Immediately after a full character row has been completed by the Row Address Counter is reset to zero but continues incrementing. Note that the Row Address Counter actually counts scan lines, which are different from character rows. A full character row consists of however many scan lines are in register R9. The Row Address Lines, RAO-RA4, are the only data lines from the Row Address Counter that are fed to an external device (the character generator ROM). The Row Address lines just carry the count that is currently in the Row Address Counter. The counter is reset whenever the count equals the contents of the Maximum Scan Line Register (R9.) Row Address Cursor Enable is a flag going to the Cursor output AND gate. The Row Address Cursor Enable flag goes high whenever the count in' the Row Address Counter is greater than or equal to the Cursor Start Register (RIO) but less than or equal to the Cursor End Register (Rll). The other input to the Cursor output AND gate goes high whenever the address in the Linear Address Counter is equal to the address in the Cursor Position Reister (R14/R15). Row Address Reset is pulsed whenever the Row Address Counter is reset. It will be discussed with the Linear Address Counter. Linear Address Counter The Linear Address Counter (LAC) produces only one set of outputs: The Refresh Memory Address lines (MAOMA13). These fourteen bits are fed externally to the Refresh RAM and internally to the Cursor Position coincidence circuit. The LAC is driven by the character rate clock and continuously increments during the display, non-display and retrace portions of the screen. It contains an internal read/write register which stores the memory address of the first displayed character in the current row. When any of the three Reset flags already mentioned (Horizontal, Row Address and Vertical) is pulsed, the value.in the internal register is loaded into the counter. If the reset is a Horizontal Reset the value in the internal register is not modified before the load. If the reset is a Row Address Reset, the value in the internal "first character" register is first increased by the number of characters displayed on a single character row (register 5.144 S68045 R1). The new contents of the internal register are then loaded into the Linear Address Counter. If the reset is a Vertical Reset, the value in Start Address Register (R12/R13) is first loaded into the internal register, and then into the Linear Address Counter. The fourteen output lines allow 16K of memory to be accessed. By incrementing or decrementing the number in the Start Address Register, the screen can be scrolled forward or backward through Display Refresh RAM on a character, line, or page basis. Figure 7. Bus Timing Character MAO·MA13 RAO·RA4 5.145 AMII~ 868045 Figure 8. Refresh Memory Addressing (MAO-MA13) State Chart ~ } ~ Ua: Horizontal Retrace (Non-Displayl Horizontal Display ~I tX~ Ch."c!.' JI NhO IN~' 1 2 I~ l N:l I~ N,d 1 \ ~I ( N:I N Vd N" I? l N~l N" N" ' 1 II ~ I Na~J 1 ! I I I : I N hd Nhd + 1 2XNhd 2XNhd + 1 I I I II 2XNhd 2XN hd t 1 1))( N hd tNl/d tN Vd 1) x 1) !x .. : 1 2XNhd 3XNhd 1 3X~hd 3XNhd i- 1 1))( Nhd (NI/d 1 N vd )( Nhd N vd )( N hd 1 I I Nhd -+ 1 I N vd x Nhd Nvdx Nhd' 1 x (NI/d + 1) N hd 1 N vd )( Nhd N vd x N hd + 1 i i N vd )( Nhd N vd x Nhd -+ 1 (N vd + 1) x N hd - 1 N vt x Nhd N vt x Nhd -+ 1 (N vt + 1).X Nhd I I II I 1 I N vt x N~d + Nht I I (N vt + 1) x Nhd + 1 (N vt + 2) x Nhd 1 (N vt + 2) x Nhd I I I I I 1 I I N yt x Nhd + Nht I 5.146 I I I I The initial MA is determined by the contents of start address register, R12lR13. Timing is shown for R12/R13 = O. Only Non·lnterlace and Interlace Sync Modes are shown. x Nhd + Nht i (N vt t 1))( Nhd x Nhd (Nvd' 1) (N vt + 1))( Nhd (N yt + 1) x Nhd IN"t + 2) x Nhd + Nht N vd x Nhd + Nht 1 (N vt -+ 1) x Nhd t 1 (Nvd' 1) tNvd + 1) x Nhd (N vt + 1) x Nhd 1) x Nhd ... 2Nhd + Nht N vd x N~d + Nht x i N vt x Nhd t 1 t .. + Nht i Nhd (NI/d + 1) N vt x Nhd CN vt : Nhd + Nht 2Nhd I I I I Nhd ~ Nht .. 3XNhd I. I Nh! .. : I I (N vd , : 2XNhd N7t .. . 2XNhd i Nhd .. Nhd 2XNhd·1 Nhd t 1 NhO I I~ I: Nhd NhO I l N:I , ; I (N vt + 1) Nhd + Nht i I I (N vt + 2) x Nhd (N vt -+ 1) Nhd + Nht AMII~ 868045 Figure 9. CRTC Horizontal Timing ----.--Tsl~ (Nht b=F ___ Tc elk ] I II 0 1 + 1) x Tc ,~_Horizontal Di~play ~-------1I~----------Horizontal NhdxTc ~ :I 2 )I :I : I I :I Retrace I I I I t I I I 'Nhd- 1 ' Nhd I I ! : l : , : ,Nhsp·l, Nhsp I , I ; ~ ~ : ~ MAO.MA13'~ ~ ~~ I I I : : I I I : :: : : :Nhd-1: Nhd : :Nhsp-1: NhSP: : I I I I I I I ! Character # I I I I : I I I , I I I I P I I HSYNC ':__________________________________+,____________________ I I ~ I I I I I I : : Nht : ~ I I J : : Nht : I I ! I ~;__NhSWX~~~1________________~ I :~-"-~--Nhd Oispen I x Tc -----------j I __________________________________________________ ~ ~ -Timing is shown for first displayed scan row only. See Chart in Figure 16 for other rows. The initial MA is determined by the contents of Start Address Register, R12/R13. Timing is shown for R12/R13 = O. Figure 10. CRTC Vertical Timing RAO-RA4 ~ TI = (Nvt ( ) T Verticat Display = Nvd x Trc-=~ IS INTtRLACE rc~ ~ I I ~~::DE~~~ ODD FIELD MAO·MA13" CHARACTER ROW. I I I (Nsl . 1): I : I tr ~ ~ ::xt::::: 1-" t' "If- fi' I a Nht' I I I I ~ r-------t- 0 I VSYNC I (HOH·IHTERLACE) I , , I I :: ~ 10,1 (Nsl ·1) I I I I I N 1 I I ~ Vertical Retrace c~~~=NadjXTSI~ ' I I I I I I I I I L-.. LJ" I I I I I I I : NySp . 1 ! I Nysp !\ I I I I :: I I: I I Nhl I yd· II I + : I ~L..Jf---, ---.JL DISPLAY ENABLE' I (Nvd: 1) x Nh,d I I ~ RELO TIME 1) x Trc + Nadi x Tsl ,_ I r- Tsl--. I I (N51 . 1) r RELO ADJUST TIME I !/ I I I I ADDRiss CONTINUES TO :NCREMENT " . . : I ~ -vt--< ~ :x;Wff~#/qWy;WmZ;w4@/!///'l!?!!!!4W//ff&?Z///V!/Zd///ffiZWA (Nvd . 1) x Nhd I '0 "ht' I Ns1 I (Nse . 1)1 + I I I I I I I I I I I : I Nvl Nvl + 1 I 16XTSI-----1 : I ~LJL.. ........JI'-----------------____________________________________ I ---' ~ , Nht . Ihere must be an even number of characler limes for both inlerlace modes . .. Initial MA is delermined by R12/R13 (Start Address Register), which is zero in Ihistiming example. '" Nhl must be an even number 01 scan lines lor Interlace Sync and Video Mode. 5.147 • 868045 Figure 11. Cursor Timing _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _A -_ _ _ _ _ _ _ _ _ _~--------~----------~--------~x RAO·RM· I I I I I I I I I ~~ ~~ + + + ! + + I + I I + + I I + I MAO·MA13·· I CHARACTER ROW' CHARACTER' Nhd I Nhd 1 Nhd 2I I I I I I I I I I I I I I I : Nhd Nht Nhd Nhd I I I I I I 1 I Nhd I Nhd Nht I I I::::: I I I I I I I I 2 I I : I \ I:: I I Nhd I Nhd 1 I Nhd I I I I I : I 2 I Nhd Nht I I I I ! Nht I CURSOR I I ----------~~ I Nht I I I I I ~~I____________________~~I~__________ • Timing is shown lor non·interlace and interlace sync modes. Example shown has cursor programmed as: Cursor Register = Nhd + 2 Cursor Start =1 Cursor End 3 = .. The initial MA is determined by the contents 01 Start Address Register. R12/R13. Timin~ is shown for R12/R13 = O. 5.148 868045 868045 ROM Program Worksheet The value in each register of the MC6845 or SY6545 should be entered without any modifications. AMI will take care of translating into the appropriate format. o o All numbers are in decimal. ROM Program Zero All numbers are in hex. ROM Program One RO Rl R2 R3 R4 R5 R6 R7 R8 R9 RIO Rll Which controller was used to develop the system? Synertek or Rockwell 6545 0 Motorola MC6845 Original 0 R Version 0 S Version 0 5.149 ADVANCED PRODUCT DESCRIPTION 86846 ROM-l/o-TIMER Features General Description o o The 86846 combination chip provides the means, in conjunction with the 86802, to develop a basic 2-chip microcomputer system. The 86846 consists of 2048 bytes of mask-programmable ROM, an 8-bit bidirectional data port with control lines, and a 16-bit programmable timer -counter. This device is capable of interfacing with the 86802 (basic 86800, clock and 128 bytes of RAM) as well as the 86800 if desired. No external logic is required to interface with most peripheral devices. The 86846 combination chip may be partitioned into three functional operating sections: programmed storage, timer-counter functions, and a parallel I/O port. o o o o o 2048x8-Bit Bytes of Mask-Programmable ROM 8·Bit Bidirectional Data Port for Parallel Interface Plus Two Control Lines Programmable Interval Timer-Counter Functions Programmable I/O Peripheral Data, Control and Direction Registers Compatible with the Complete S6800 Microcomputer Product Family TTL-Compatible Data and Peripheral Lines Single 5 Volt Power Supply Pin Configuration Block Diagram 40 39 00 01 38 02 03 04 37 BIDIRECTIONAL DATA BrU.;:,..S_ _ _ _- , 36 05 35 06 07 34 COMPOSITE STATUS REGISTER CSO' CSI' 33 32 AO AI 10 31 II 30 A3 12 29 A3 A5 13 28 14 21 A2 1\6 CPl 1\7 A8 15 26 16 25 17 24 CP2 A9 AIO All Vss_ VCC _ PPO PPI 18 23 PP2 19 22 20 21 PP3 2048 BYTE ROM PP4 PP5 PP6 PP7 'MASK PROGRAMMABLE 5.150 86846 General Description (Continued) Programmed 8torage The mask-programmable ROM section is similar to other AMI ROM products. The ROM is organized in a 2048 by 8 -bit array to provide read only storage for a minimum microcomputer system. Two maskprogrammable chip selects are available for user definition. Address inputs AD-AID allow any of the 2048 bytes of ROM to be uniquely addressed. Internal registers associated with the I/O functions may be selected with AD, Al and A2. Bidirectional data lines (DO-D7) allow the transfer of data between the MPU and the 86846. Timer-Counter Functions Under software control this 16 -bit binary counter may be programmed to count events, measure frequencies and time intervals, or similar tasks. It may also be used for square wave generation, single pulses of controlled duration, and gated delayed signals. Interrupts may be generated from a number of conditions selectable by software programming. The timer-counter control register allows control of the interrupt enables, output enables, and selection of an internal or external clock source. Input pin CTC (counter-timer clock) will accept an asynchronous pulse to be used as a clock to decrement the internal register for the counter-timer. If the divide-by-8 prescaler is used, the maximum clock rate can be four times the master clock frequency with a maximum of 4 MHz. Gate input (CTG) accepts an asynchronous TTL-compatible signal which may be used as a trigger or gating function to the counter-timer. A countertimer output (CTO) is also available and is under software control via selected bits in the timer-counter control register. This mode of operation is dependent on the control register, the gate input, and the external clock. Parallel I/O Port The parallel bidirectional I/O port has functional operational characteristics similar to the B port on the 86821 PIA. This includes 8 bidirectional data lines and two handshake control signals. The control and operation of these lines are completely software programmable. The interrupt input (CPl) will set the interrupt flags of the peripheral control register. The peripheral control (CP2) may be programmed to act as an interrupt input or as a peripheral control output. Figure 1. Typical Microcomputer STANDBY Vce 56846 ROM,IIO, TIMER COUNTERI \ TIMER 110 Vee Vee iRli MR RESET eso VMA 2K BYTES ROM 10110 LINES 3 LINES TIMER VMA S6B02 MPU 128 BYTE RAM 00-07 CLOCK RIW PARALLEL 110 VCC RES HALT RE NMl SA XTAL 0 CONTROL I CP2 AO-A15 _CPl L-_----._ _...... SYSTEM EXPANSID N IF REQUIRED Figure 1 ;sablockdiagramofa typical costeffectllle microcomputer The MPU is the center of the microcomputer system and is shown in a minimum system interfacing with a ROM combination chip. It is not intended that this system be limited to this function but that it be expandable with other parts in the S6800 Microcomputer family if 5.151 XTAL S6846 Absolute Maximum Ratings Supply Voltage ........................................................ -0.3Vdc to +7.0Vdc Input Voltage ......................................................... -0.3Vdc to +7.0Vdc Operating Temperature Range ...................... . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0° C to +70° C Storage Temperature R?nge ................................................ -55°C to +150°C Thermal Resistance .............................................................. 70° C/W This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields: however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this highimpedance circuit. Electrical Characteristics (Vee Symbol = 5.0V ± 5%, Vss ::: 0, TA::: O°C to +70°C unless otherwise noted.) Parameter All Inputs VIL Input Low Voltage All Inputs Vos Clock Overshoot/Undershoot - Input High Level - Input Low Level lin Input Leakage Current ITSI Three-State (Off State) Input Current VOH Output High Voltage Unit Vdc VSS -0.3 Vee Vss + 0.8 Vee -0.5 VSS -0.5 Vee + 0.5 VSS + 0.5 Vdc 1.0 2.5 100 j.lAdc 2.0 10 100 ,uAdc DO-D7 PPO-PP7, CR2 IOL VSS + 2.4 VSS + 2.4 VSS + 2.4 Power Dissipation Cjn Capacitance ILoad = 1.6mAdc ILoad = 3.2mAdc j.lAdc 00-07 Other Outputs CP2, PPO-PP7 -205 -200 -1.0 DO-D7 Other Outputs 1.6 3.2 VOH = 2.4Vdc -10 mADC IRQ VOL = OAVdc 10 /lAdc 1000 mW 20 12.5 pF 10 7.5 PPO-PP7, CP2, CTO 5.0 10 pF 1.0 MHz f Frequency of Operation 0.1 tcycE Clock Timing Cycle Time 1.0 Reset Low Time tIR Interrupt Release j.lS j.lS 2 1.6 5.152 VOH = 2.4Vdc Vin = 0, TA = 25°C, f= 1.0MHz PPO-PP7, CP2 AO·A10, R/W, Reset, CSO, CS1, CP1, CTC, CTG IRQ tRL Vo = 1.5Vdc, the current for driving other than TTL, e.g., Darlington Base mAdc 00-07 Cout ILoad = -205,uAdc, ILoad = -145.uAdc, ILoad = -100,uAdc Vdc Output Low Current (Sinking) Output Leakage Current (Off State) Yin = 0 to 5.25Vdc Yin 0.4 to 2.4Vdc VSS + 0.4 VSS + 0.4 Output High Current (Sourcing) Po Vdc Vdc Output Low Voltage ILOH Conditions Vdc DO·D7 Other Outputs IOH Typ. VSS + 2.0 R/W, Reset, CSO, CS1 CP1, CTG, CTC, E, AO-All DO-D7 CP2, PPO-PP7 Other Outputs VOL Max. Min. Input High Voltage VIH j.lS 56846 Read/Write Timing Symbol Parameter Min. PWEL Enable Pulse Width, Low 430 Typ. Max. Unit PWEH Enable Pulse Width, High 430 ns tAS Set Up Time (Address CSO, CS1, R/W) 160 ns tDDR Data Delay Time tH Data Hold Time 10 ns tAH Address Hold Time 10 ns tEf, tEr Rise and Fall Time tDSW Data Set Up Time Conditions ns 320 25 ns ns ns 195 Bus Timing Peripheral I/O Lines Symbol Parameter Min. tpDSU Peripheral Data Setup 200 tPr, tpc Typ. Max. Unit Rise and Fall Times CP1, CP2 1.0 fJ.S tCP2 Delay Time E to CP2 Fall 1.0 fJ.S tDC Delay Time I/O Data. CP2 Fall tRSl Delay Time E to CP2 Rise ns 20 JlS 1.0 JlS tRS2 Delay Time CP1 to CP2 Rise 2.0 JlS tpDW Peripheral Data Delay 1.0 JlS 100 ns Timer-Counter Lines tCR, tCF Input Rise and Fall Time CTC and CTG tPWH Input Pulse Width High (Asynchronous Mode) tcyc + 250 ns tpwL Input Pulse Width Low (Asynchronous Mode) tcyc + 250 ns tsu Input Setup Time (Synchronous Mode) 200 ns thd Input Hold Time (Synchronous Mode) 50 ns tCTO Output Delay 1.0 5.153 fJ.S Conditions AMII~ 86846 Figure 2. Bus Read Timing (Read Information from S6846) Figure 3. Bus Write Timing (Write Information from MPU) /..----''''.---.-.1 Rm. A,CS R/W,A,CS DATA BUS DATA BUS Figure 4. Peripheral Data and CP2 Delay (Control Mode PCR5 = 1, PCR4 = 0, PCR3 2,DV Figure 5. IRQ Release Time = 1) 2.0V ,. ~_t=."J,- O.8V PPO·PP7 tRS' ENABLE 2.0V CP2 Z.4V Figure 6. Peripheral Port Setup Time Figure 7. CP2 Delay Time (PCR5 = 1, PCR4 = 0, PCR3 = 0) 2.0V PPO·PP7 ENABLE ~Z.OV ~..:.;.;...O'BV_t=--tPDSU--CPl ENABLE T2.0V \..._____ ~ CBZ CP2 5.154 O.4V tRSZF 2.4V j-j_ _ _...J Please contact your local AMI Sales Office for complete data sheet S6846 Figure 9. Input Setup and Hold Times Figure 8. Input Pulse Widths rnor eTG 0.8V 1'------'1 eTC ill NOTE: This made is valid anJy for synchronous operation. Figure 10. Output Delay Figure 11. Bus Timing Test Loads LOAD A (00·07, CTO, CP2, PPO·PP7) 5.0V LOAO B ENABLE f'" L.. CTO \ Ie TO (1M ONLY) R, =2.5k TEST POINT i,,, 56150 OR EOUIV. ~'" .'I TEST POINT 57000 OR EOUIV. 0.4V -=C = 1JOpF for 00,07 = JOpF for CTO, CP2, PPO·PP7 R = 11.7kllfor 00·07 = 24kll for CTO, CP2, PPO·PP7 5.155 -=- Jk 568047 VIDEO DISPLAY GENERATOR Features General Description o The S68047 Video Display Generator (VDG) is designed to produce composite video suitable for display on a standard American NTSC compatible black/white television or color televison or monitor. o o o o o o o 32 x 16 (512 total) Alphanumeric Two Color Display on Black Background with Internal or External Character Generator ROM. Two Semigraphics Modes with Display Densities Ranging from 64 x 32 to 64 x 48 in 8 and 4 Color Sets Respectively, plus Black. Full Graphics Modes with Display Densities Ranging from 64 x 64 to 256 x 192 in 2 and 4 Colors. Full NTSC Compatible Composite Video with Choice of Interlaced and Non -interlaced Display Versions. Provides Microprocessor Compatible Interface Signals. Generates Display Refresh RAM Addresses. NMOS Device, Single 5V Supply, TTL Compatible Logic Levels. Color Set Select Pin Can Give 8 Color Displays in Full Graphics Mode. There are three major types of display which the S68047 can generate. These include an alphanumerics mode of which there are two types, each with normal or inverted video; a semigraphics mode of which there are also two types; and full graphics mode of which there are eight types. Alphanumeric Modes The alphanumeric modes, internal and external, enable the S68047 to display a matrix of 32 x 16 (512 total) characters. The internal mode utilizes an on-chip 64 ASCII character ROM to display each character in a 5 x 7 dot matrix font. In the external alphanumeric Block Diagram Pin Configuration MPU ADDRESS BUS MPU DAl A BUS Vee CC GM4 GM2 3K 6-12 AtS 5·50 pF A6 GMI A7 A/G AB INV Vss jjji RP A9 AID HS B-V All GM2 R-V A4 GMI CHROMA BIAS AJ CSS A2 AtG GM4 CSS INfIEXT 68 AIS 5.156 VIljEO CLOCK (VCI Al 07 AD 06 MS 05 DO 04 Dl OJ 02 AMII~ 568047 General Description (Continued) mode, an external memory is required, either ROM or RAM, which is used to display the 32 x 16 character matrix with each character located within an 8 x 12 dot matrix of customized font. Switching between internal and external alphanumerics modes and normal and inverted video can be accomplished on a character by character basis. Semigraphic Modes The two semigraphic modes, semigraphic 4 (SG4) and semigraphic 6 (SG6), subdivide each of the 512 (32 x 16) character blocks of 8 x 12 dots each into 2 x 2 and 2 x 3 smaller blocks respectively. In SG4 each block is created from 4 x 6 dots and in SG6 each block consists of 4 x 4 dots. In addition the SG4 and SG6 modes can each be displayed in 8 and 4 colors plus black. Display switching from alphanumerics to semigraphics modes or vice versa during a raster display is called minor mode switching and can take place on a character basis. Graphics Modes The eight full graphics modes are divided into two major groups, 4 color and 2 color. The 4 color graphics provide 4 display densities ranging from 64 x 64 for Graphics 0 through to 128 x 192 elements for Graphics 6. The 2 color graphics also provide 4 display densities ranging from 128 x 64 for Graphics 1 through to 256 x 192 elements for Graphics 7. The latter display has the highest density of the eight graphics modes. The amount of display memory increases proportionately with increasing density of display to a maximum of 6K bytes for Graphics 7. Switching between either the alphanumeric modes or semigraphics modes and any o"f the full graphics modes is called major mode switch ing. Major mode switching can only occur at the end of every twelfth raster line scan. Applications Anywhere data can be more usefully presented graphically on a CRT and for a minimum cost, the VDG in conjunction with a microprocessor based controller can utilize a standard American NTSC compatible TV or monitor for such a purpose. ApplIcations are extremely broad ranging from educational systems, video games, small low cost business/home computers to process control monitors and medical diagnostic displays. The different modes of operation permit various cost/ display presentation tradeoffs. The alphanumerics modes allow use of the TV screen as a video teletype at the most limited level of operation. Only 512 bytes, one for each character, need to be stored, each byte being a minimum of six bits wide per the ASCII code. If video inversion switching or alpha to semigraphics switching is required per character then two extra bits are required in the display RAM as shown in Fig. 5. The semigtaphics modes each offer an intermediate range of graphics densities with tradeoffs in density versus color. Typical semigraphics display capabilities are bar graphs, charts, mini displays, etc. which with minor mode switching to alphanumerics modes allow annotation or captioning of the resultant display. The various graphics modes provide greater density displays with greater freedom of display presentations. The tradeoffs in increasing density are with increasing display memory size and color versus density. A minimum Graphics 0 provides a display density of 64 x 64 (4096) elements, each element being composed of a matrix of 12 (4 x 3) dots with a selection of four colors per element. Since each of the even numbered 4 color graphics modes map two bits of the data word to one picture element. each data word of memory provides four picture elements. Thus Graphics 0 requires 4096/4 = 1024 bytes of display RAM, Graphics 2 requires 8192/4 = 2048 and so on. Graphics 1. like all the odd numbered 2 color graphics modes. maps one hit of data word to one picture element. Each data word therefore maps eight elements. Graphics 1 density of 128 x 8 (8192) elements therefore requires 8192/8 = 1024 bytes of display RAM and Graphics 7. the densest display. requires 49. 152/8 == 6144 bytes of RAM. At the higher density graphics displays, the rate of change of elements approaches the maximum dot frequency of 6MHz. This video rate taxes the capabilities of most commercially available television sets and thus the quality of the display system (television or monitor) should be commensurate with the highest video rate to be used. Electrical Specifications Absolute Maximum Ratings Supply Voltage .................................................................... 7.0V Input Voltage ...................................... , ...................... - O.3V to +7.0V Operating Temperature ........................................................ O°C to 70°C Storage Temperature ....................................................... - 65°C to 150°C 5.157 868047 DC (Static) Characteristics (Vee = 5.0V ± 5% ; TA = 25°C, unless otherwise specified). Symbol Parameter Min. Typ. Max. Unit VIH Input Voltage High 2.0 Vee V VIH Input Voltage High (Color Clock only) 4.0 Vee V VIL Input Voltage Low - 0.3 +0.6 V lIN Input Leakage Current (all inputs) 2.5 JlA 1.0 Conditions VIN = 0 - 5.25V; Vee = OV IL(TS) Tri-State Output Leakage Current (AO - All) 10 JlA Vee = 5.25V; MS VIN = 0.4 -2.4V = OV; ILO Output.Leakage Current (HS, FS, RP) 1.0 JlA VIN = 2.4V; Vee = OV VOH Output Voltage High (AO - All, HS, FS, RP) VOL Output Voltage Low (AO - All, HS, FS, RP) Icc Vee Supply Current rnA Vee CIN Input Capacitance 10 pF VIN = 0, TA = 25°C; f = 1.0MHz COUT Output Capacitance 12 pF VIN = 0, TA f = 1.0MHz 2.4 0.4 45 AC Electrical Characteristics (Vee = 5.0V ± 5%; TA = V IOH = -100pA (HS, FS, RP); OpA (Ao - All); CL = 30pF V IOL = 1.6mA (HS, FS, RP); OmA (Ao - All); CL = 30pF = 5V; TA = 25°C ~ 25°C; 0 - 70°C except where noted). Alpha Internal Mode (Figure 1) Symbol fvc tch tAec tdot Parameter Min. Typ. Max. Unit Video Clock Frequency Character Time Access-Time of External Refresh RAM Dot Time 5.6 1.43 6.0 1.33 6.4 1.25 MHz 178 166 0.7 156 ps JlS ns Alpha External Mode (Figure 1) NOTE: All parameters are the same as in Alpha Internal Mode except tACC tAec Access-time of Refresh RAM + Access-time of External ROM 0.7 Semigraphics Mode (Figure 1) tpic Picture Element Duration NOTE: All other parameters are the same as in Alpha Internal Mode. 5.158 JlS Conditions AMII~ 868047 Color Sub-carrier Input Symbol Parameter fcc Frequency tr tf PWcc VIL VIH DR Rise Time Fall Time Pulse Width Zero Level One Level Duty Ratio Typ. Min. Max. 10 10 140 0.6 50% Conditions MHz 3.579545 ±10 Hz 4.0 40% Units ns ns ns V V 60% Figure 1. Refresh RAM Interface Timing VIDEO CLOCK (¢l) AD - All 00 - 07, CSS A/S, INV, INT /EXT LATCH DATA (Internal to the chip) Y, R-Y, B-Y DOT BEING DISPLAYED (FULL ALPHA) PICTURE ELEMENT BEING DISPLAYED (SEMIG RAPHICS) Composite Video Timing (Figure 2 ) Symbol Parameter tSYNC Sync duration 4.888889 Il S tfp Front Porch duration 1.536508 Il S tBLANK t rs • tfs trv, tfv Typ. Min. Max. Units Horizontal Blank Duration 11.44 Il S Rise time and Fall time of Horizontal Sync 250 ns Rise time and Fall time of Horizontal Blank 340 ns 5.159 Conditions AMlt. 868047 Figure 2. Composite Video Timing on Y Pin V _ _ _ __ WH1TE Chroma R and Chroma B Output Timing; CL = 10pF; 1K Load (Figure 3.)' Symbol Parameter trB, tfB trR, tfR tscB tBURST tfeB, treB Color Signals rise and fall time Color Burst to Sync lag Color Burst Duration Color Burst rise and fall times Video to color signals lag teLl, teL2 Typ. Min. Max. Units 50 410 2.45 ns ns 175 75 ns ns Conditions Load = R-Y, B-Y input of LM1889 /lS V oltage Levels Video (Y) and Chroma (R-Y, B-Y) Output Levels (Figure 3.) CL = 10pF; Video Clock = 5.6MHz; TA= 25°C; Vee = 5V ± 5% Symbol VSYNC Parameter Sync Voltage Min. Typ. Max. Units 0 0.1 0.5 V VBLANK Blanking Level 1.5 VBLACK Black Level 1.7 VWHITE VBl, VRl White level V V 2.4 4.0 Vee V 2.4 4.0 Vee V 0 0.5 VBURST 0.1 0.4 V V VeHROMA BIAS 2.0 2.0 VBO, VRO VB3, VR3 5.160 V V Conditions AM/I. 868047 Figure 3. Chroma Timing ': :" ::~:;:~===? i '~"'""':~~r VWHITE - -Il-tfB Bl---;: I tCLl-J I I I I- IsCB-+! BO ______ 1 10% 90% BUR::~ -------~ RO- U U II"';-"::":':'---/'\[' II I:I~ I 90% 10% I I : W: 'IB-: I:J I I !-tBuRST -J/-t Rl~: ~ ~ !-1CL2 I ~ trCB tfCB-YI-+jf- CHROMA B B IB-YI : fR I-trB n - CHROMA R I IA - YI R3 -l:... I t rR Video Display Format Timing (Figure 4.) Symbol Parameter H V F Horizontal Scan Time Field Time Frame Time Field Rate Active Display Duration Active Display + Border Duration Row Preset Period (12 Horizontal Scans) ltv tACTIVE tVIDEO tRP Typ. Units 63.55557 16.683337 33.366674 59.94004 41 J.l.S ms ms sec 1 J.l.S 52.8 762.66684 J.l.s J.l.S Figure 4. Video Display Format --I BORDER -II ACTIVE ~ OISPLAY AREA L...-_ _ _ _ _ _~ -II START - - - OF VERT. BLANK 1 1-'ACTI~vl I - - - 'VIDEO - - - I------H 5.161 ~ 2: Conditions AMII~ 868047 Pin Description (Figure 2.) Vee +5V Vss DV cc (Color Burst Clock 3.579545 MHz) VC (Video Clock Oscillator == 6MHz) AD -All (Address Lines to Display Memory; high-impedance during MS low) DD-D5 (Data from Display Memory RAM or ROM; D4 - D6 - Color Data in Semigraphics) D6,D7 (Data from Display Memory in GRAPHIC Mode; Data also in ALPHANUMERIC Mode; Color Data in ALPHA SEMIGRAPHIC - 6) R-Y, B-Y, Y (Color and Composite Video) CHB (Chroma Bias; References R - Y and B - Y Levels) RP (Row Preset in any ALPHA Mode; goes low in all modes every 12 lines) HS (Horizontal Sync) A~PHA INV (Inverts Video in all FULL EXT/INT (Switches to External ROM in ALPHA Mode; between SEMIG - 4 and SEMIG - 6 in Semigraphics; no effect in all Graphics Modes) A/S (Alpha/Semigraphics: Selects between FULL ALPHA and SEMIGRAPHICS in ALPHA Modes; no effect in all Graphics Modes) Modes; no effect in Semigraphics or Graphics Mode) (Memory Select; forces VDG Address Buffers to high-impedance state; also used as a strobe in TEST and RESET functions). The TV screen is forced black when MS = low A/G FS (Switches between ALPHA and GRAPHIC Modes) CSS (Color Set Select: Selects between two ALPHA Display Colors; between two Color Sets in SEMIGRAPHICS - 6 and FULL GRAPHICS: selects Border Color in 8 Graphic Modes) GM1, GM2 GM4 (Graphics Mode Select; select one of eight Graphic Modes; no affect in Alpha and Semigraphic Modes; GM1, GM2 select TEST and RESET mode when A/G = D and MS pin is strobed low) (Field Synchronization; LOW during vertical blanking time) Internal Description Internally the VDG is the combination of four integrated subsystems (timing and control, MUX, address buffers and shift registers to form the VDG function. A block diagram of the VDG is shown on Page 1. Each subsystem is described below. ternal RC and generates addresses AD - All to address the external refresh RAM. Timing and Control The EXT /INT input has two functions. In the full alphanumeric mode, it is used to select either internal ROM or external ROM. It is also used to select between semigraphic 4 and semigraphic 6 mode in semigraphic modes (A/S = 1). The timing and control subsystem of the VDG uses the 3.58MHz color frequency to generate timing information. It accepts the color clock (generated off-chip) (CC) input and generates timing for the horizontal sync, horizontal blank, field sync, vertical blank and row preset signal (RP) for external character generator ROM. The video clock is generated on-chip by ex- The color-set-select (CSS) input to the Timing and Control subsystem of the VDG is used to determine the color-set of the display. The INV input is utilized by the timing and control subsystem to invert the display while in full alpha mode. 5.162 AMII~ 568047 Internal Description (Continued) A/G, A/S, GM1, GM2, GM4 inputs to the timing and control subsystenl determine which of the fourteen VDG modes is to be used (Table 1). on the TV screen. The shift registers output also goes to the chroma encoder circuitry to determine the color of each individual dot. Each shift register has 4-bits. VDG The VDG has fourteen modes, grouped in three sets. They are: MUX The MUX provides the function of selecting the data source to be displayed. The source can be either internal ROM or external ROM or RAM. For the internal alphanumeric mode, the data source is the internal ROM. For all other modes (semigraphic and graphics) the data source is external ROM/RAM. 4 Alphanumerics Modes 2 Semigraphics Modes o o o o o o Normal internal alpha Inverted internal alpha Normal external alpha Inverted external alpha Semigraphics 4 Semigraphics 6 8 Full- graphics Modes Address Buffers The address buffers provide the buffering required for external drive (ROM/RAM). The buffers are tristated when the MS pin goes low and tri-states the buffers so that VDG does not interfere with the MPU operation. The FS pin (output) from the VDG signals to the MPU that the TV is in the vertical retrace mode and the MPU can directly change the data in the display memory during that time with no interruption to displayed data. Shift Registers The two shift registers serialize bytes coming from internal/external ROM/RAM for conversion to data o o 4 Graphics four-color modes 4 Graphics two -color modes The six alphanumeric modes can be switched among themselves on a character -by -character basis. Switching within the six alphanumeric modes is referred to as minor-mode switching. All other mode switching is referred to as major-mode switching. The display can be major-mode switched on after any multiple of twelve rows have been completed. This is signalled to the MPU by RP output going low. Switching among the full-graphics modes is permitted .at the end of every twelfth row just as in majormode switching. Table 1 tabulates the modes of the VDG. The data structures for each mode are listed in Table 7. Table 2 and Table 3 show the Alpha Select Mode and Graphic Select Mode configurations respectively. Table 4 gives the Two-color Graphics and Full-alpha Color Specification. Table 5 shows the semigraphics and Four-color Graphics Color Specification. Table 1. VDG Modes Descri~tion Mode II. III. IV. V. ALPHA ALPHA ALPHA ALPHA ALPHA VI. ALPHA SEMIGRAPHICS 6 VII. VIII. IX. X. XI. XII. XIII. XIV. GRAPHICS 0 CiRAPHICS 1 GRAPHICS2 GRAPHICS 3 GRAPHICS 4 GRAPHICS 5 GRAPHICS 6 GRAPHICS 7 I. INTERNAL INTERNAL INVERTED EXTERNAL EXTERNAL INVERTED SEMIGRAPHICS 4 32 x 16 BOXES: 5 x 7 CHARACTER IN8x12BOX 32 x 16 BOXES: 5 x 7 OR 7 x 9 CHARACTERS IN 8 x 12 BOX OR FULL 8 x 12 LIMITED GRAPHICS 32 x 16 BOXES: 2 x 2 ELEMENTS PER BOX; EIGHT COLORS PLUS BLACK 32 x 16 BOXES 2 x 3 ELEMENTS PER BOX; FOUR COLORS PLUS BLACK 64 x 64 ELEMENTS: FOUR COLORS PER ELEMENT 128 x 64 ELEMENTS: TWO COLORS PER ELEMENT 128 x 64 ELEMENTS: FOUR COLORS PER ELEMENT 128 x 96 ELEMENTS: TWO COLORS PER ELEMENT 128 x 96 ELEMENTS: FOUR COLORS PER ELEMENT 256 x 96 ELEMENTS: TWO COLORS PER ELEMENT 128 x 192 ELEMENTS: FOUR COLORS PER ELEMENT 256 x 192 ELEMENTS: TWO COLORS PER ELEMENT 5.163 Memor)! 512x7-8 .512x7-8 512x4-7 512x6-8 1K x 8 1K x 8 2K x 8 1.5K x 8 3K x 8 3K x 8 6K x 8 6K x 8 868047 Table 7. Detailed Description of VDG Model VDG PINS COLOR A/G A/S INT/EXT GM4 GM2 GM1 CSS INV CHARACTER BACKCOLOR GROUND + + a -+ a - -+-+ a a a a x a Green a Black ~ Blue 1 1 Black Black Green Black Blue Green Black Green 1 Black Black Green Blacl< Green - 1 X X a 0 0 x x DISPLAY MODE OETAIL Black 32 Characters in columns 16 Characters In rows 1200Tt[j 32 Characters In columns 16 Characters In rows @] Blacl< Black Black Lx C2 C, Co Color a x x X Black a a a Green a a 1 Yellow Black 0 1 0 Cyan Red a 1 1 1 0 Blue 1 1 a Cyan! Blue 1 1 1 0 Magenta 1 1 1 1 Orange Lx C, Co 0 a D 0 a a t t t a t 1 0 0 1 a TV SCREEN BORDER t t 1 a 1 1 Black Green Yellow Cyan Red Black Blue Cyan! Blue Magenta Orange C, Co a a Green 1 Yellow 1 a Cyan Green Red Blue Cyan! Cyan! Blue Blue 1 0 Magenta 1 1 Orange a ooo.!.X t o a r- Color Black x Same color as Graphics 0 + Cyan! Blue Green Same color as Graphics 1 tcyan; ,Green rCyan! Blue a x >+-T; 1., 64 Display elements In columns tlliili UL2 32 Display elements in rows 64 Display elements in columns Ll LD UL2 L5L4 48 Display elements in rows 64 Display elements in columns 64 Display elements in rows Same color as Graphics 0 T Green -Cyan! Blue Same color as Graphics 1 'v-'~--v-----' HOT USED ASCI INPUT mTJTTD ONE ROW OF 1 1 ..2.... 1 X Same color as Graphics 0 -------,- Cyan! Blue X Same color as Graphics 1 ALPHANUMERIC EXTERNAL mode uses external ROM or RAM to display 512 characters in custom fonts each in 8x12 dot matrix [JCililftO[UJll[llflO] ~, HOT COLOR USED I LUMlHEHCE c***41 L**1/Lol '--y---J~ COLOR SEMIGRAPHICS 4 mode subdivides each of the 512 (32x16) character blocks of 8x12 dots into four equal parts. The dominance of each block is determined by the corresponding bit (LO-L3) on the VDG data bus. Color of each block is determined by 3 bits (CO-C2) SEMIGRAPHICS 6 mode subdivides each of the 512 (32x16) character blocks of 8x12 dots into six equal parts. The luminance of each part is determined by the corresponding bits (LO-L5) on the VDG bus. Color of each block is determined by 2 bits (CO. Cl). LUMlHEHCE GRAPHICS a mode uses a maximum of 1024 bytes of display RAM in which one pair of bits (CO. C1) specifies on picture element. (Ex.) 1E3lu\E1\ EOI WHEREEX = CICO GRAPHICS 1 mode uses a maximum of 1024 bytes of display RAM in which one bit (Lx) specifies one picture element elements in rows 128 Display elements in columns 64 Display elements in rows GRAPHICS 2 mode uses a maximum of 2048 bytes of display RAM in which one pair of bits (CO. Cl) specifies one picture element (Ex.) 128 Display elemen1s in columns 96 Display elements in rows GRAPHICS 3 mode uses a maximum of 1536 bytes of display RAM in which one bit (Lx) specifies one picture element 128 Display elements in columns 96 Display elements In rows GRAPHICS 4 mode uses a maximum of 3072 bytes of display RAM in which one pair of bits (CO. Cl specifies one picture element (Ex.) 256 Display Green elements in -columns Cyan! 96 Display Blue elements in rows Green acter ROM to display each character in 5x7 dot matrix font CUSTOM CHARACTERS 1L7IL61L5IL4IL31 L21 Lll LDI ~~~~~~s GRAPHICS 5 mode uses a maximum of 3072 bytes of display RAM in which one bit (Lx) specifies one picture element GRAPHICS 6 mode uses a maximum of 6144 bytes of display RAM in which one pair of bits (CO. Cl) specifies one picture element (Ex.). 128 Display O..ll COMMENTS I I I I I I I I I ~;:r~~t~~~eEn~lr~t~~~i~~~~_~~~e6~s:~~~lte;~:;_ 128 Display elements in Blue X +i 8O'T! ~ -~--- ----~~~-~ ~~luD~Snp~ay Cyan! Blue 1 VDG DATA BUS in 192 Display elements in rows ;~~~~~~I~~ Green -columns Cyan! 192 Display Blue elements in rows 1L7IL61L5lul ulL2IL1ILOI 5.164 GRAPHICS 7 mode uses a maximum of 6144 bytes of display RAM in which one bit (Lx) specifies one picture element AMII~ 568047 Table 2. Alpha Mode Select GM2 GM1 A/G A/S INT /EXT INV X 0 0 0 0 0 X 0 0 0 0 X 0 0 0 X 0 0 0 X 0 0 X 0 0 0 NOTES: MODE INTERNAL ALPHANUMERICS INTERNAL INV. ALPHA 0 EXTERNAL ALPHA EXTERNALINV.ALPHA 0 SEMIGRAPHICS - 4 X X SEMIGRAPHICS - 6 0 X X X STROBED LOW TEST ROM 0 X X X STROBED LOW RESET 1) GM4 pin has no effect when A/G = o. 2) Invert pin has no effect except in Internal Alpha or External Alpha. 3) Under normal operation, care should be taken not to take GM 1pin HIG H, when A/G pin is LOW. If this happens, any of the following conditions will occur depending on the status of MS and GM2 pin: a) The VDG might go to TEST mode. b) The VDG might be reset. The VD G will not return to normal operation unless A,/G and GM 1 pins are returned to LOW level and MS pin is strobed. 4) X = Don't care. Table 3. Graphic Mode Select A/G GM4 GRAPHICS 0 0 GRAPHICS 1 0 GRAPHICS 2 0 GRAPHICS 3 0 GM2 GM1 MODE 64 x 64 4 - CO LO R 0 128x642-COLOR 0 128x644-COLOR 128 x 96 2 - COLOR GRAPHICS 4 0 GRAPHICS 5 0 0 128 x 96 4 - COLOR 0 128 x 192 4 - COLOR 256 x 96 2 - COLOR GRAPHICS 6 GRAPHICS 7 NOTE: 256 x 192 2 - COLOR A/S, INT /EXT, INV pins have no effect when A/G = 1. Table 4. Two-Color Graphics and Full-Alpha Color Specification CSS PIN COLOR OF 'ON' DOTS o GREEN 1 CYAN-BLUE 5.165 ~II~ 568047 Table 5. Semigraphics and Four-Color Graphics Color Specification 4·COLOR GRAPHICS SEMIGRAPHICS - 6 SEMIGRAPHICS-4 EVEN BIT 000 BIT CSS 06 07 04 05 css css .1 COLOR SET 000 0 o o o COLOR SET GREEN YELLOW CYAN RED BLUE CYAN/BLUE MAGENTA ORANGE 1 o 1 o NOTE: In Semigraphics-6. if any bit 00-05 is '0', then the picture element corresponding to that bit would be black. In Semigraphics-4, if any bit 00-03 is zero, then the picture element corresponding to that dot will be black. Table 6. Two-Color Graphics and Four-Color Graphics Border Color Specification CSS PIN BORDER COLOR o GREEN CYAN-BLUE Typical System: A typical 86800 microprocessor based 868047 system is shown on Figure 6. This system has the capability of displaying internally and externally generated characters, semigraphics 4 and 6 modes with mode switching control from the microcomputer input! output ports. A full graphics system configuration would be similar in complexity with possibly additional display RAM for the denser graphics modes. The National 8emiconductor LM1889RF modulator shown, has an on-chip 3.58MHz oscillator which can provide the microcomputer system clock as well as the color burst reference for the 868047. Other RF modulators are available through various commercial channels. Only 512 bytes are needed to display the 512 character blocks on a TV screen. However, because of current static RAM configurations (Le., 1Kx1 & 1Kx4) the extra 512 bytes available in the 1Kx9 RAM shown can be used as scratchpad by the host microcomputer system. Figure 5. - - - -_ _- - - - - - - -_ _~MS 741173 S68047 GRAPHICS 6 AND GRAPHICS 7 REQUIRE CK OF DISPLAY RAM. THUS THIRTEEN ADDRESS LINES THE VDG PROVIDES Ao-A" HOWEVER A'2 MUST BE GENERATED EXTER· NALLY AS SHOWN IN FIGURE 5 '-----1------1 fS All - - - - - - - - Ordering Information Ordering Number 868047 868047P 868047Y 868047YP Number Pins 40 40 40 40 Package Ceramic Plastic Ceramic Plastic 5.166 Temp. Range Description VDG non-interlaced VDG non-interlaced VDG interlaced VDG interlaced AMII~ 868047 Figure 6. Typical System (Alphanumeric Internal/External & Semigraphics 4 and 6 Modes.) r--:l--_----Jr-,~ ":: : i-'';---r :~~o";:: ~-----r---------_ _ _ I"--lM"""--------'-"''''' SELECT I.......--- M" I t )~ ~v 1 "," I '"'''' """ If----- I -b - CE ,:':. t~ '" DATA ,l " "c+-- 7~'"'"" ""~---~~""", I I ' I RV 8 y I lM1U9 I I L ___ -' Physical Dimensions 40-Pin SLAM 40- Pin Plastic 5.167 TO TV ANTENNA S6850/S68A50/S68B50 ASYNCHRONOUS COMMUNICATION INTERFACE ADAPTER (ACIA) Features General Description • 8 Bit Bidirectional Data Bus for Communication with MPU The S6850/S68A50/S68B50 Asynchronous Communications Interface Adapater (ACIA) provices the data formatting and control to interface serial asynchronous data communications to bus organized systems such as the S6800/S68AOO/S68BOO Microprocessing Units. • • False Start Bit Deletion Peripheral/Modem Control Functions • Double Buffered Receiver and Transmitter • One or Two Stop Bit Operation • Eight and Nine-Bit Transmission with Optional Even and Odd Parity • Parity, Overrun and Framing Error Checking • Programmable Control Register • Optional -:- 1, -:- 16, and -:- 64 Clock Modes • Up to 500,000 bps Transmission The S6850/S68A50/S68B50 includes select enable, read! write, interrupt and bus interface logic to allow data transfer over an eight-bit bidirectional data bus. The parallel data of the bus system is serially transmitted and received by the asynchronous data interface, with proper formatting and error checking. The functional configuration of the ACIA is programmed via the data bus during system initialization. Word lengths, clock division ratios and transmit control through the Requestto-Send output may be programmed. For modem operation three control lines are provided. Block Diagram Pin Configuration CTX.;..14.,1- - - - - - - - - - - - - - - - l EI141 CSo CS1 1-_ _ _ _~161 TXO 1--_ _ _ _+'1""'241 m l81 1101 rn 191 Rslll1 SELECT & RIW CONTROL RIW 1131 171iifii 00 01 02 03 04 05 06 07 1221 1-_ _ _ _ _~12~3Imrn 1211 1--_ _ _ _ _~(~51~ 1201 1191 1181 1171 DATA BUS BUFFERS 1161 1151 1--_----<~-..j..:.!!.121 RXO 877253 131 CRX.::1 -----------~ VCC =PIN 12 GROUND = PIN 1 5.168 AMII~ S6850/S68A50/S68B50 Absolute Maximum Ratings Supply Voltage ........................................................... -0.3V to +7.0V Input Voltage ............................................................ - 0.3V to +7.0V Operating Temperature Range .................................................. O°C to +70°C Storage Temperature Range ................................................ -55°C to +150°C Note: This device contains circuitry to protect the inputs against damage due to high static voltages or electrical fields, however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. Electrical Characteristics (Vee = +5.0V ± 5%, VSS = 0, T A = 0° C to +70 0 C unless otherwise noted.) Symbol VIH VIL lIN ITSI VOH Typ. Max. Units Min. Parameter Vdc Input High Voltage (normal operating level) VSS+2.0 VCC Input Low Voltage (normal operating level) VSS+0.8 Vdc VSS-0.3 Input Leakage Current 1.0 2.5 J.lAdc R/W, ES, CSO, CS1, CS2, Enable Three-State (Off State) Input Current 2.0 10 J.lAdc DO-D7 Output High Voltage (all outputs except IRQ) Vdc DO-D7 VSS+2.4 Vdc Tx Data, RTS VSS+2.4 VOL Output Low Voltage (Enable pulse width < 25J.1s) ILOH PD CIN Output Leakage Current (Off State) Power Dissipation Input Capacitance Vdc IRQ 1.0 300 10 525 J.lAdc mW DO-D7 E,Tx,CLK,Rx Clk,R/W,RS,Rx Data, CSO,CS1,CS2,RXD,CTS,DCD,CTX,CRX 10 12.5 pF 7.0 7.5 10 5.0 pF pF pF ns ns kHz kHz J.lS ns ns J.lS J.lS J.ls COUT Output Capacitance PWCL PWCH fC Minimum Clock Pulse Width, Low Minimum Clock Pulse Width, High Clock Frequency ~DD Clock-to-Data Delay for Transmitter Receive Data Setup Time Receive Data Hold Time Interrupt Request Release Time Request-to-Senct Delay Time Input Transition Times (Except Enable) tRDSU tRDH tIR tRTS tr,tf VSS+O.4 RTS,Tx Data IRQ +16, +64 Modes +16, +64 Modes +1 Mode +16, +64 Modes 600 600 +1 Mode +1 Mode 500 500 500 800 1.0 1.2 1.0 1.0* *1.0J.l or 10% of the pulse width, whichever is smaller. 5.169 Conditions VIN = OVdc to 5.25Vdc VIN = O.4Vdc to 2.4Vdc ILOAD = - 205J.1Adc, Enable Pulse Width < 25J.1s ILOAD = -100J.lAdc, Enable Pulse Width <25J.1s ILOAD = 1.6mAdc, Enable Pulse Width <25J.1s VOH = 2.4Vdc VIN = 0, TA = 25°C, f = 1.0MHz S6850/S68A50/S68B50 Bus Timing Characteristics (Vee = +5.0V ±5%, Vss=O, TA =O°C to +70°C unless otherwise noted.) Read S6850 Symbol Characteristic Min. S68A50 Max. Min. Max. S68B50 Min. Max. Unit tCYCF Enable Cycle Time 1.0 0.666 0.50 PWEH Enable Pulse Width, High 0.45 0.28 0.22 PWEL Enable Pulse Width, Low 0.43 0.28 0.21 J.ls Setup Time, Address and RIW Valid to Enable Positive Transition 160 140 70 ns tAS 320 J.ls 25 180 220 J.ls tDDR Data Delay Time tH Data Hold Time 10 10 10 ns tAH Address Hold Time 10 10 10 ns t Er, tEf 25 Rise and Fall Time for Enable Input 25 25 ns ns Write S6850 Symbol Min. Characteristic S68A50 Max. Min. Max. S68B50 Min. Max. Unit tCYCE Enable Cycle Time 1.0 0.666 0.50 PWEH Enable Pulse Width, High 0.45 0.28 0.22 PWEL Enable Pulse Width, Low 0.43 0.28 0.21 J.ls Setup Time, Address and RIW Valid to Enable Positive Transition 160 140 70 ns Data Setup Time 195 80 60 ns 10 10 ns tAS t DSW tH tAH t Er, tEf Data Hold Time 10 Address Hold Time 10 5.170 10 10 25 Rise and Fall Time for Enable Input J.ls 25 25 J.ls ns 25 ns S6850/S68A50/S68850 Figure 2. Clock Pulse Width, High State Figure 1. Clock Pulse Width, Low State PWCl Tx ClK or Rx ClK TxClK RxClK PWCH Figure 4. Receive Data Setup Time (71 Mode) Figure 3. Transmit Data Output Delay Tx ClK RxDATA O.BV trDD TxDATA --------'>t Figure 5. Receive Data Hold Time (71 Mode) ~ 2'OV ...:O.:.;;..8V:...-_ _ _ _ _ _ _ _ _ __ Rx CLOCK f- ----- tRDSU O.8V Figure 6. Request-to Send Delay and Interrupt- Request Release Times ENABLE _1~_tRDH_~_ tRTS _r .:::_:: Figure 7. Bus Read Timing Characteristics (Read Information from ACIA) Figure 8. Bus Write Timing Characteristics (Write Information into ACtA) i-.---tcycE'----- t..----tcycE----.! ENABLE ENABLE RS,CS,R/W RS,CS,R/W DATA BUS DATA BUS 5.171 Please contact your local AMI Sales Office for complete data sheet S6850/S68A50/S68B50 Bus Timing Test Loads (00·07. LOAD A RTS. Tx DATA) LOAO B (iRQ ONLY) 5.0V 5.0V RL,2.5k 3k TEST POINT C' 130pF FOR 00·07 , 30pF FOR ill ANO Tx DATA 871251 0-----. R' 11.71<1"lFOR 00·07 AND Tx DATA , 24Hl FOR m Expanded Block Diagram TRANSMIT CLOCK 4 -------------------~ ENABLE 14 - - - - , REAO/WRITE 13 CHIPSELECTO 8 TRANSMIT DATA REGISTER CHIPSELECT I 10 CHIPSELECT 1 9 ~-----__ 6 TRANSMIT DATA REGISTER SELECT 11 24CLEAR·TO·SEND DO 22 STATUS REGISTER 01 21 02 20 03 19 04 lB 7 INTERRUPT REQUEST DATA BUS BUFFERS 23 DATA CARRIER DETEcT 05 17 5 REQUEST·TO·SEND 06 16 07 15 CONTROL REGISTER VOD =PIN 12 VSS 'PIN I RECEIVE DATA REGISTER RECEIVE SHIFT REGISTER RECEIVE CLOCK 3 -------------------~L..-_ _---' 877252 5.172 14----+---2 RECEIVE DATA S6852/S68A52/S68B52 SYNCHRONOUS SERIAL DATA ADAPTER (SSDA) Features General Description o Programmable Interrupts from Transmitter, Receiver, and Error Detection Logic o Character Synchronization on One or Two Sync Codes o External Synchronization Available for Parallel- Serial Operation o o o o The S6852 Synchronous Serial Data Adapter provides a bi-directional serial interface for synchronous data information interchange. It contains interface logic for simultaneously transmitting and receiving standard synchronous communications characters in bus organized systems such as the S6800 Microprocessor systems. Programmable Sync Code Register o o o o Up to 600kbps Transmission Peripheral/Modem Control Functions Three Bytes of FIFO Buffering on Both Transmit and Receive Seven, Eight, or Nine Bit Transmission Optional Even and Odd Parity Parity, Overrun, and Underflow Status Clock Rates: 1.0MHz 1.5MHz 2.0MHz The bus interface of the S6852 includes select, enable, read/write, interrupt, and bus interface logic to allow data transfer over an 8 -bit bi -directional data bus. The parallel data of the bus system is serially transmitted and received by the synchronous data interface with synchronization, fill character insertion/deletion, and error checking. The functional configuration of the SSDA is programmed via the data bus during system initialization. Programmable control registers provide control for variable word lengths, transmit control, receive control, synchronization control, and interrupt control. Status, timing and control lines provide peripheral or modem control. Typical applications include floppy disk controllers, cassette or cartridge tape controllers, data communications terminals, and numerical control systems. Block Diagram Pin Configuration ADDRESS/CDNTROL AND INTERRUPT PERIPHERALI MOOEM CONTROL RECEIVE OATA DATA BUS 1/0 TRANSMIT OATA 5.173 AMII~ S6852/S68A521S68B52 Absolute Maximum Ratings: Supply Voltage. . .. . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .......... . . . . . . . .. . .. .. . . . . . .. . .. . . . . . . . . . . . .. . . . .. -0.3 to +7.0 Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .. . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . . . . . . . . .. -0.3 to +7.0V Operating Temperature Range ............. , ....................................................................... 0° to +70°C Storage Temperature Range ................................................................................... -55° to +150°C Thermal Resistance .................................................................................................. +70°C/W Note: This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. Electrical Characteristics (Vcc Symbol = 5.0V ± 5%, VSS = 0, TA = Characteristic Min. Typ. Max. Unit Vdc TxClk, Rx Clk, Rx Data, Enable Reset, RS, R/W, CS, DCD, CTS 1.0 VSS+0.8 2.5 f'Adc DO-D7 2.0 10 /AAdc VIH Input High Voltage VIL Input Low Voltage lIN Input Leakage Current (VIN=O to 5.25Vdc) ITSI Three State (Off State) Input Current (VIN=OA to 2AVdc, VCC=5.25Vdc) VOH Output High Voltage ILOAD= -205/AAdc, Enable Pulse Width < 25/As ILOAD= -100/AAdc, Enable Pulse Width < 25/As VOL Output Low Voltage ILOAD= 1.6mAdc, Enable Pulse Width < 25/As ILOH Output Leakage Current (Off State) VOH=2AVdc Power Dissipation PD COUT DO-D7 VSS+2A VSS+OA Vdc 1.0 10 /AAdc 300 525 mW pF Output Capacitance (VIN=O, TA=25°C, f= 1.0MHz) = 5.0V ± Vdc Vdc VSS+2A IRQ Input Capacitance (VIN=0,TA =25°C. f=1.0MHz) Electrical Characteristics (Vcc Vdc VSS+2.0 Tx Data, DTR, TUF CIN O°C to 70°C unless otherwise noted.) DO-D7 All Other Inputs 12.5 7.5 Tx Data, SMIDTR, TUF IRQ 10 5.0 5%, TA pF = TL to TH unless otherwise noted.) S68A52 S6852 S68B52 Symbol Characteristic Min. PWCL Minimum Clock Pulse Width, Low (Figure 1) 700 400 280 ns PWCH Minimum Clock Pulse Width, High (Figure 2) 700 400 280 ns fC Max. Clock Frequency Min. Max. 600 Min. Max. 1500 1000 Unit kHz tRDSU Receive Data Setup Time (Figure 3, 7) 350 200 160 tRDH Receive Data Hold Time (Figure 3) 350 200 160 tSM Sync Match Delay Time (Figure 3) 1.0 0.666 0.500 /AS Clock-to-Data Delay for Transmitter (Figure 4) 1.0 0.666 0.500 /AS tTDD *lOl's or 10% of the pulse width, whichever is smf'lier. Figure 1. Clock Pulse Width, Low-State Figure 2. Clock Pulse Width, High-State Ix Clk OA Ax Clk 2.0V Tx Clk OA Ax Clk _ P W CH 5.174 ns ns S6852/S68A52/S68B52 Electrical Characteristics-Continued (Vcc 8ymbol = 5.0V ± 5%, TA Characteristic Transmitter Underflow (Figure 4, 6) tTUF tDTR tIR tRes tcTS tDCD t r , tf = TL to TH unless otherwise noted.) 86852 Min. Max. DTR Delay Time (Figure 5) 1.0 1.0 Interrupt Request Release Time (Figure 5) 1.2 Reset Minimum Pulse Width CTS Setup Time (Figure 6) 1.0 200 DCD Setup Time (Figure 7) 500 Input Rise and Fall Times (except Enable) (0.8V to 2.0V) 868A52 Min. Max. 0.666 868B52 Min. Max. 0.666 0.800 0.666 150 /AS 0.600 /AS /As 0.500 120 350 1.0 Unit 0.500 0.500 /As ns 250 1.0 ns 1.0 /AS Bus Timing Characteristics Symbol S68A52 Min. Max. Min. Max. 0.5 0.22 0.21 25 0.43 0.666 0.28 0.28 Setup Time, Address and RIW Valid to Enable Positive Transition 160 140 Data Delay Time Data Hold Time 10 10 10 10 10 10 Characteristic Min. Enable Cycle Time 1.0 0.45 86852 Max. 868B52 Unit Read tCYCE PWEH Enable Pulse Width, High Enable Pulse Width, Low PWEL tAS tDDR tH 320 Address Hold Time Rise and Fall Time for Enable Input tAH tEr, tEf Write 25 25 tCYCE PWEH Enable Cycle Time Enable Pulse Width, High 1.0 0.45 PWEL Enable Pulse Width, Low 0.43 0.28 160 195 10 10 Setup Time, Address and RIW Valid to Enable Positive Transition Setup Time Data Hold Time tAs tDsw tH Address Hold Time Rise and Fall Time for Enable Input tAH tEr, tEf 0.666 . 0.28 /As /As /As 70 220 25 25 25 0.5 0.22 25 ns 180 ns 25 ns ns ns /As 25 /As 0.21 /AS 140 70 ns 80 60 10 10 10 ns ns 10 25 25 ns ns 25 Figure 3. Receive Data Setup and Hold Times and Sync Delay Time On -I -,.... z.ov I ...,i'o.sv - 'RDSU_ RxDATA DO On Rx Clk \\\\\\~ .... Z.OV r- O.SV <- 'RDH _ _ 1\\\\\\\\\\~ =~\\\\\"\ \\~ ~\\\\\\\\\"\ l- ISM_ n = NUMBER OF SITS IN CHARACTER [SSJ = OON'T CARE / SYNC MATCH Z.4V • 5.175 \- 0.4V RxClk PERIOD ~I AMII~ S6852/S68A52/S68852 Figure 4. Transmit Data Output Delay and Transmitter Underflow Delay Time Figure 5. Data Terminal Ready and Interrupt Request Release Times Tx Clk 2.0V ENABLE t TOO Tx DATA t,R-j----i )2.4V TUF -----------------~ n = NUMBER OF BITS IN CHARACTER Figure 6. Clear·To-Send Setup Time Figure 7. Data Carrier Detect Setup Time ~j O.BV toeD Rx Clk TxDATA --------------J>f Figure 8. Bus Read Timing Characteristics (Read Information from SSDA) Rx DATA DO ~ _ _ _ _ _ _ _ _ _ _ _ _ _- J 2'OV DO O.BV Figure 9. Bus Write Timing Characteristics (Write Information into SSDA) ~----tCY'E-------.l ENABLE ENABLE RS; RS, Cs, RNI CS, RNI DATA BUS DATA BUS 5.176 Please contact your local AMI Sales Office for complete data sheet S68521S68A52/S68852 Figure 10. Bus Timing Test Loads LOAD 8 (iJiQONLY) LOAOA (00·07, iifR, Tx OATA, TUF) 5.0V RL = 2.5k TEST POINT ..... o-_-_-~- MM06150 OR EQUIV. TEST POINT MMD7000 OR EQUIV. ~ 5.0V 3k 1'"°" C = 130pF FOR 00·07 = 30pF FOR iffR, Tx DATA, AND TUF R = 1107hZ FOR 00·07 = 24kfl FOR iifR, Tx DATA, AND TUF Expanded Block Diagram ENA8LE 14 READIWRITE 13 CHIP SELEG i 10 REGISTER SELECT 11 DO 22 01 21 02 20 03 19 ~-------_ 6 8 1-+_ _ _ _ _ 04 18 05 17 06 16 07 15 1+_------- 24 br=tt:t:==:::r.===;-- 23 L~$!LI-~--r-r---- V DD =PIN 12 TRANSMITIER UNDERFLOW CLEAR·TO·SEND DATA CARRIER 7 UD..D~====.s-L..L--fRe~iER-,..~~==+-jjL--- TRANSMIT DATA 2 DETECl INTERRUPT REQUEST ~!~~IVE 3 ~~g~~VE 5 SYNC MATCHi DATA TERMINAL iITAifY Vss =PIN I 5.177 S6854/S68A54/S68854 ADVANCED DATA LINK CONTROLLER o o Features o o o o o o S6800 Compatible Protocol Features o Automatic Flag Detection and Synchronization o Zero Insertion and Deletion o Extendable Address, Control and Logical Control Fields (Optional) o Variable Word Length Info Field - 5, 6,7, or 8-bits o Automatic Frame Check Sequence Generation and Check o Abort Detection and Transmission o Idle Detection and Transmission Loop Mode Operation Loop Back Self-Test Mode NRZjNRZI Modes Quad Data Buffers for Each Rx and Tx Prioritized Status Register (Optional) MODEMjDMA/Loop Interface General Description The S6854 ADLC performs the complex MPUjdata communication link function for the "Advanced Data Communication Control Procedure" (ADCCP). High Level Data Link Control (HDLC) and Synchronous Data Link Control (SDLC) standards. The ADLC provides key interface requirements with improved software efficiency. The ADLC is designed to provide the data communications interface for both primary and secondary stations in stand-alone, polling, and loop configurations. Block Diagram Pin Configuration ~DCO RxC Vss 2s_m RfS 27_DCO TxO FLAG iiffiff fiITI RESET- cs- ~~ t• J..--===::;:-;::;;"LO~OP~O:N::;:-L"'I:':NE;;:;C;;;O:NT;;ROn7L~~~R L_-,...._..,..._-r----,J----~RfS VssPIN 1 Vee PIN 14 '-------« RESET 5.178 26 LOOP ON-LINE CONTROL/iITii 25 FLAG OET 24 TOSR ROSR 23 S6854 7 S68A54 22 _ 0 0 S S68854 21 _01 9 20-02 RS o- 1 0 19_03 RS,-11 18-04 RIW-12 17-05 E-13 16-06 14 15-07 Vee AMII~ S6854/S68A54/S68B54 Absolute Maximum Ratings· Supply Voltage ................................................................................... -0.3 to +7.0V Input Voltage ..................................................................................... -0.3 to +7.0V Operating Temperature Range ........................................................................ 0° to +70°C Storage Temperature Range... ... ..... ......... ............ ... ........ ........... . ........... .... -55° to + 150°C Thermal Resistance ...................................................................................... 70°C/W *This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. Electrical Characteristics (Vee Symbol Vm V1L = 5.0V ± 5%, VSS Parameter = 0, TA = O°C to +70°C unless otherwise noted.) Min. Input High Voltage Typ. Input Low Voltage lIN Input Leakage Current All Inputs Except DO-D7 ITsI Three State (Off State) Input Current DO-D7 V OH Output High Voltage DO-D7 All Others Max. Unit Vss+0.8 Vdc 1.0 2.5 IAAdc VIN=O to 5.25 Vdc 2.0 10 IAAdc VIN=OA to 2AVdc Vcc=5.25Vdc Vdc Vdc hOAD= -205,uAdc hOAD= - lOO IAAdc VSS + 2,4 Vs s+2,4 VOL Output Low Voltage hOH PD CIN Output Leakage Current (Off State) IRQ DO-D7 All Other Inputs COUT IRQ All Others 5.0 10 pF pF 1.0 Power Dissipation Capacitance S6854 Symbol Conditions Vdc Vs s+2.0 VSS + 0,4 Vdc hOAD = 1.6mAdc 10 VOH=2AVdc 850 IAAdc mW 12.5 7.5 pF pF S68A54 VIN=O, TA=+25°C, f=1.0MHz S68B54 Characteristic Min. PWCL Minimum Clock Pulse Width, Low 700 450 280 PWCH Minimum Clock Pulse Width, High 700 450 280 fc Clock Frequency Max. Min. 0.66 Max. Min. 1.0 Max. Unit ns ns 1.5 MHz t RDSU Receive Data Setup Time 250 200 120 tRDH t RTS Receive Data Hold Time 120 100 60 tTDD Clock-to-Data Delay for Transmitter 460 320 250 ns Flag Detect Delay Time 680 460 340 ns ns tFD Request-to-Send Delay Time 680 ns ns 340 460 ns tDTR D'l'R Delay Time 680 460 340 tLOC Loop On-Line Control Delay Time 680 460 340 ns t RDSR RDSR Delay Time 540 400 340 ns t TDSR TDSR Delay Time 540 400 340 ns Interrupt Request Release Time 1.2 0.9 0.7 lAS tIR t RES Reset Minimum Pulse Width tr, tf Input Rise and Fall Times except Enable (0.8V to 2.0V) 1.0* *1.0fis or 10% of the pulse width, whichever is smaller. 5.179 0040 0.65 1.0 1.0* lAs 1.0* lAS S6854/S68A54/S68B54 Bus Timing Characteristics (Vee = +5.0V ±5%, Vss=O, TA =O°C to +70°C unless otherwise noted.) Read S6854 Symbol tCYC PWEH PWEL tAS Characteristic Min. S68A54 Max. Min. Max. S68B54 Min. Max. Unit 25 /As Enable Cycle Time 1.0 0.666 0.50 Enable Pulse Width, High 0.45 0.28 0.22 Enable Pulse Width, Low 0.43 0.28 0.21 /As Setup Time, Address and RfW Valid to Enable Positive Transition 160 140 70 ns 320 220 /AS 180 tDDR Data Delay Time tH Data Hold Time lO 10 lO ns tAH Address Hold Time 10 10 lO ns t Er, tEf 25 Rise and Fall Time for Enable Input 25 25 ns ns Write S6850 Symbol Characteristic Min. S68A50 Max. Min. Max. S68B50 Min. Max. Unit t CYCE PWEH Enable Cycle Time 1.0 0.666 0.50 /AS Enable Pulse Width, High 0.45 0.28 0.22 /As PWEL Enable Pulse Width, Low 0.43 0.28 0.21 /As Setup Time, Address and RfW Valid to Enable Positive Transition 160 140 70 ns t Dsw Data Setup Time 195 80 60 ns tH Data Hold Time lO 10 lO ns tAH Address Hold Time lO tAS t Er, tEf 10 25 Rise and Fall Time for Enable Input 5.180 ns lO 25 25 ns S6854/S68A54/S68B54 Figure 1. Bus Timing Test loads LOADA (00-07 TxD, RDSR, TOSR FLAG DET, LOOP ON· LINE CONTROL/iiTii) m. LOAD B (iM ONLY) 5.0V 3k TEST POINT()--_~_--M""-"" ~~i~~~v. TEST POINT 0,,----'" MMD7000 OR EUUIV. =- C = 130pF FOR 00-07 =30pF FOR OTHERS ':' R = 11.7krl FOR 00-07 = 24kn FOR OTHERS Figure 2. Receiver Data Setup/Hold, Flag Detect and Loop On-Line Control Delay Timing '. . .- - - - - P W C H - - - - - -.. ·~'i RxC '1--_ _ _ _ _-------(1/ 2.0V 1~•._------PWCl~,I--------------~-~~~------------0.-8V~2.0~VI RxD 1----------tRDHI--""2;-;.4T."V---'°::j··L""VI _t FLAG DET. -----------------+t~:...:...-----_---_-tF-DI::_:-.;.;,_----..J~ ~ CONTROL ___________________-++-____ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-++-_____ _la.4V Loc 5.181 0.4V ~}2~.4~V------------ -4~~----------- Please contact your local AMI Sales Office for complete data sheet S6854/S68A54/S68B54 Figure 3. Transmit Data Output Delay and Request to Send Delay Timing I-PWCH-I TxC 2.0V 1\ O.BV ~~------------~ -PW Cl ---:-}!21d. ~:..."~l 4"""V!.. -_ _ ______________ TxD JO.4V -tTOD-I}! 12;::.4V=--_ _ _ _ _ _ _ _ _ _ __ RTS Figure 4. TDSR/RDSR Delays, IRQ Release Delay, RTS and DTR Delay Timing 2.0V E ---.I \ O.BV R'fS .. \ ) iffii .. iRQ .. O.4V " 2.4V tATS " tOTR ttR O.4V 2.4V 2.4V " TDSR RDSR t RDSR t TDSR O.4V Figure 5. Bus Read/Write Timing Characteristics READ ES. RSO RW/RSI DATA BUS 11111111111111~:====j~}IIIIIIII~ WRITE ES. RSO RIW. RSI DATA BUS 5.182 ADVANCED PRODUCT DESCRIPTION 568488 GENERAL PURPOSE INTERFACE ADAPTER Features General Description o o o o The S68488 GPIA provides the means to interface between the IEEE488 standard instrument bus and the S6800. The 488 instrument bus provides a means for controlling and moving data from complex systems of multiple instruments. o o o o o o o Single or Dual Primary Address Recognition Secondary Address Capability Complete Source and Acceptor Handshakes Programmable Interrupts RFD Holdoff to Prevent Data Overrun Operates with DMA Controller Serial and Parallel Polling Capability Talk-Only or Listen-Only Capability Selectable Automatic Features to Minimize Software Synchronization Trigger Output S6800 Bus Compatible The S68488 will automatically handle all handshake protocol needed on the instrument bus. Block Diagram Pin Configuration "HANDSHAKE S6BOO DATA BUS MGMT. BUS{ / ... DATA 10 0101·0108 NOTE 1: TYP 16 PLACES *The 3-wire handshake described is the subject of patents owned by Hewlett-Packard Co. 5.183 AMII~ 868488 Functional Description The IEEE 488 instrument bus standard is a bit-parallel, byte-serial bus structure designed for communiation to and from intelligent instruments. Using this standard, many instruments may be interconnected and remotely and automatically controlled or programmed. Data may be taken from, sent to, or transferred between instruments. A bus controller dictates the role of each device by making the attention line true and sending talk or listen addresses on the instrument bus data lines; those devices which have matching addresses are activated. Device addresses are set into each GPIA from switches or jumpers on a PC board by a microprocessor as a part of the initialization sequence. When the controller makes the attention line true, instrument bus commands may also be sent to single or multiple GPIAs. Information is transmitted on the instrument bus data lines under sequential control of the three handshake lines. No step in the sequence can be initiated Figure 1. DATA BUS ES (8I ) until the previous step is completed. Information transfer can proceed as fast as the devices can respond, but no faster than the slowest device presently addressed as active. This permits several devices of different speeds to receive the same data concurrently. The GPIA is designed to work with standard 488 bus driver Ics (83448As) to meet the complete electrical specifications of the IEEE488 bus. Additionally, a powered-off instrument may be powered-on without disturbing the 488 bus. With some additional logic, the GPIA could be used with other microprocessors. The 868488 GPIA has been designed to interface between the 86800 microprocessor. and the complex protocol of the IEEE488 instrument bus. Many instrument bus protocol functions are handled automatically by the GPIA and require no additional MPU action. Other functions require minimum MPU response due to a large number of internal registers conveying information on the state of the GPIA and the instrument bus. GENERAL INTERFACE MANAGEMENT DATA BYTE TRANSFER CONTROL iiAV oAC fFc RFo A <;= v .- I -- \ .- ........, ill Imi EOi SRii otJ v J 1\ ~i 1 1 DEVICE A ABLE TO TALK, LISTEN, AND CONTROL •.g., CALCULATOR 1 '" ~ 11 DEVICE B ABLE TO TALK AND LISTEN •.g., DIGITAL MULTIMETER 1 '" 7T 1 1 ..., 711 DEVICE C ONLY ABLE TO LISTEN e.g.,SIGNAL GENERATOR S68488 S6802 5.184 >- DEVICE 0 ABLE TO TALK AND LISTEN ~II. S68488 Maximum Ratings Supply Voltage ........................................................ -0.3Vdc to +7.0Vdc Input Voltage ......................................................... -0.3Vdc to +7.0Vdc Operating Temperature Range .................................................. O°C to +70°C Storage Temperature Range ................................................ - 55°C to +150°C Thennal Resistance ............................................................ +82.5° CjW This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields, however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this highimpedance circuit. Electrical Characteristics (Vee == 5.0V ±5%, Vss Symbol Parameter == 0, TA == o°c to +70°C unless otherwise noted) Min. VIH Input High Voltage VIL Input Low Voltage Typ. VSS + 2.0 VSS - 0.3 Max. Unit Vdc ,uAdc VIN ,uAdc VIN == 0.4 to 2.4V lIN Input Leakage Current 1.0 Vee VSS + 0.8 2.5 ITSI Three -State (Off State) Input Current DO-D7 2.0 10 VOH Output High Voltage VOL Output Low Voltage DO-D7 ILOH PD CIN Output Leakage Current (Off State) IRQ Power Dissipation 1.0 600 Input Capacitance DO-D7 All Others VSS + 0.4 VSS + 0.4 Vdc Iload == 1.6mA Iload == 3.2mA 10 ,uAdc mW pF VOH == 2.4Vdc 12.5 7.5 =X~ _____--,X,,--___ SOURCE DAV _ _ _- - , I SOURCE VALID R_DY_~I----, RFD _ _ AL_L I I I NONE ISOM:C~DY DAC : II I SOME RDY ALL nTiACCEPTOR AL~ ACe rrmL.--_ACCEPTOR I I DATA TRANSFER BEGIN DATA TRANSFER END 5.185 0 to 5.25V Iload == - 205,u A Figure 2. Source and Acceptor Handshake D101. 0108 = Vdc VSS + 2.4 DO-D7 IRQ Conditions VIN = 0, TA == 25°C, f == 1.0MHz 568488 Bus Timing Characteristics Read (See Figure 3) Symbol Parameter Min. Typ. Max. Unit tcycE Enable Cycle Time 1.0 jJ.s PWEH Enable Pulse Width, High 0.45 jJ.s PWEL Enable Pulse Width, Low 0.43 jJ.s tAS Setup Time, Address and R/W valid to enable positive transition 160 ns Conditions See Figure 3 ns tDDR tH Data Delay Time Data Hold Time 10 ns tAH Address Hold Time 10 ns tEr, tEf Rise and Fall Time for Enable input 320 25 ns Write (See Figure 4) tcycE Enable Cycle Time 1.0 J.l.s PWEH Enable Pulse Width, High 0.45 jJ.s PWEL Enable Pulse Width, Low 0.43 jJ.s tAS Setup Time, Address and R/W valid to enable positive transition 160 ns tDSW Data Setup Time 195 ns tH Data Hold Time 10 ns tAH Address Hold Time 10 tEr, tEf Rise and Fall Time for Enable input See Figure 4 ns 25 ns 400 ns DA V, DAC, RFD, EOl, ATN valid 400 ns T/R1, T/R2 valid Output (See Figure 5) tHD Output Delay Time tT{Rl,2D Figure 3. Bus Read Timing Characteristics (Read Information from GPIA) Figure 4. Bus Write Timing Characteristics (Write Information into GPIA) ~ ENABLE ENABLE RS, CS, R/Vi RS, CS, R/W DATA BUS DATA BUS 5.186 _ _ _ t",cE _ _~ Please contact your local AMI Sales Office for complete data sheet 568488 Figure 5. Output Bus Timing ENABLE -- ----' OAV, OAC, RFO, EOi, ill V:SV i---- tHD :x 2,OV O.BV ~tT/Rt,2D_ X T/R1, T/R2 A.C. Time Values Symbol* * ** Parameter Min. T1 Settling Time for Multiple Message t2 Response to A TN T3 Interface Message Accept Time t4 Response to IFC or REN False t5 Response to ATN • EOI Typ. Max. Unit #2 ps** ,,;;;200 ns >0 ~ T,TE, L, LE <100 fJ.S PP ,,;;;200 ns SH SH, AH, T, L t AH Conditions Time values specified by a lower case t indicate the maximum time allowed to make a state transition. Time values specified by an upper case T indicate the minimum time that a function must remain in a state before exiting. If three-state drivers are used on the DIO - DAV and EOI lines, Tl may be: (1) #1l00ns (2) Or #700ns if it is known that within the controller ATN is driven by a three-state driver. (3) Or #500ns for all subsequent bytes following the first sent after each false transition of ATN [the first byte must be sent in accordance with (1) or (2)]. t Time required for interface functions to accept, not necessarily respond to interface messages. ~ Implementation dependent. MPU bus clock rate - The current 6800 bus clock is";;; IMHz but part should operate at 1.5MHz (design goal), with appropriate settling times (T1). 5.187 • ADVANCED PRODUCT DESCRIPTION 56894 DATA ENCRYPTION UNIT Features o o o o Full Implementation of the NBS DES Algorithm A Complete Set of Operations, Including Encrypt Data, Decrypt Data, Enter New Key, Return Status, and Partial and Full Resets High-Speed Operation - Full Encryption or Decryption of a 64-Bit Data Block, Including All Command and Data Transfers, in 14.0ms. o 64~Bit Key Entry and Processing in 11.0ms, Including Odd Parity Checking of 8-Bit Key Data Bytes Simple Interface Through a General Purpose 8-Bit Paralled Digital I/O Port General Description In addition, the AMI S6894 DEU offers an on-chip clock circuit, TTL-compatible I/O, single + 5V power supply, in a two-chip set. The 14.0ms data encryption/decryption time provided by the AMI DEU corresponds to a data rate in excess of 4600 bits-per-second in sustained operation. Allowing only 5% overhead for communications protocol control and checksum bits, this data rate is adequate to support a 4800 baud synchronous data link operated at 100% utilization. For start-stop asynchronous communications, the S6894 data rate is adequate to support lines with an aggregate transmission capacity in excess of 5700 baud. Two or more S6894 DEUs can be operated in parallel where higher data rates are required. The encryption key is processed separately at the time it is entered. Once entered into S6894 DEU, an encryption key cannot be accessed by external means in either its original or processed form. Thus, security of the encryption key is fully protected. Each encryption key is entered only once - following a DEU reset, at DEU initialization, or when the key is to be changed. The entered key is then used for all subsequent data encryption and decryption operations. Interface to the S6894 DEU is through a conventional general purpose 8-bit parallel I/O port. This allows the unit to be used with a wide range of host processors having different bus structures. Other DEU Products Although the S6894 DEU is the primary AMI NBS DES hardware product, other versions can be supplied at customer request. These include: S6894-2 - Features and performance are identical to the S6894 DEU except that two encryption keys are accommodated. DEU encrypt and decrypt commands explicitly designate which key is to be used. Thus, the DEU-2 can serve two data paths having different encryption keys, can be used in the Master Key/Session Key mode, and so forth. Two new commands - Enter and Decrypt New Key, and Process New Key - are provided. These allow a new encrypted key to be decrypted under control of either existing key and then to replace either key, while prohitibing external access to the intermediate decrypted key value. The S6894-2 is implemented as a three-chip set that includes an S6810 RAM. 5.188 AMII~ 56894 86894-3 - Features and performances are identical to the S6894-2 DEU except that three encryption keys are accommodated. The S6894-3 consists of a four-chip set that includes two S5101 CMOS RAMs. An added feature is low power key data retention. During powerdown conditions, all three encryption key values can be preserved using battery backup with only O.lm W power drain. Preserved encryption keys are restored during power-on reset processing. 86894-3A - Features are identical to the S6894-3 DEU in a two-chip set implementation. Data encryption and decryption times are 22.5ms, corresponding to a data rate in excess of 2800 bits-per-second in sustained operation. Low power data retention power requirements are less than 40m W. DEU can be modified, and commands can be added or modified. For example, commands can be modified and added to facilitate Master/Session Key and/or Cypher Feedback (CFB) modes of operation. Further, the hardware interface can be modified or customized to meet specific application requirements. For example, the general purpose 8-bit parallel I/O port interface can be replaced - e.g., by a DMA interface or a custom LSI circuit - to precisely match the bus interface requirements of a particular host processor, to simplify DEU control and minimize host processor overhead, and/or to achieve maximum efficiency and speed in data and command word transfers. Customized Data Encryption Units AMI can also make available high-speed versions of any of the above DEUs. Because the object of such an implementation of the NBS DES is high performance, AMI plans at this time to offer high speed DEU products only in versions specifically customized to individual user requirements. AMI DEU products can be customized to specific customer requirements in a number of ways. Protocols and conventions for .transfer of data and command words between the controlling host processor and the AMI will be pleased to work with interested customers in specifying and implementing customized versions of DEU products that meet requirements of specific applications. Prices and delivery for all of the above DEUs will be quoted on request. 5.189 • S681 0/S68A 1 0/S6881 0 128X8 STATIC READ/WRITE MEMORY Features General Description o o o o The S681O/S68A10 and S68B10 are static 128x8 Read/Write Memories designed and organized to be compatible with the S6800/S68AOO and S68BOO Microprocessors. Interfacing to the S6810/S68A10 and S68B10 consists of an 8-bit bidirectional data bus, seven address lines, a single Read/Write control line, and six chip enable lines, four negative and two positive. Organized as 128 Bytes of 8 Bits Static Operation Bidirectional Three-State Data Input/Output Six Chip Enable Inputs (Four Active Low, Two Active High o Single 5 Volt Power Supply o TTL Compatible o Maximum Access Time 450ns for S6810 360ns for S68AlO 250ns for S68B10 For ease of use, the S681O/S68A10 and S68BlO are a totally static memory requiring no clocks or cell refresh. The S6810/S68A10 and S68B10 are fabricated with N-channel silicon gate depletion load technology to be fully DTLlTTL compatible with only a single + 5 volt power supply required. Pin Configuration Block Diagram 12100 AD 1231 13101 AI 1221 14102 GNO Vee 00 M 01 AI A21211 15103 A31201 16104 A41191 17105 02 A1 A51181 18106 03 A3 A61171 19107 04 A4 05 A5 06 A6 REAO/ 1161 WRITE E31131 07 RIW EOIIOI EO E5 t"S1151 [41141 E21121 fj fa E2 E3 ff 1111 III 1241 GND Vee 1+5VI 5.190 AMII~ S681 0/S68A 10/S6881 0 Absolute Maximum Ratings Supply Voltage ..................................................................... - 0.3V to + 7.0V Input Voltage ...................................................................... -0.3V to +7.0V Operating Temperature Range .......................................................... O°C to + 70°C Storage Temperature Range ........................................................ -55°C to + 150°C D.C. Characteristics: (Vee = +5.0V ± 5%, Vss = 0, TA=O°C to 70°C unless otherwise noted.) Min. Symbol Parameter lIN Input Current (An, R/W, CSn , CSn ) VOH Output High Voltage VOL Output Low Voltage ho lee Typ. Max. Units Conditions 2.5 I-lAdc VIN = OV to 5.25V 2.4 Vdc IOH = -2051-l A 0.4 Vdc IOL = 1.0rnA Output Leakage Current (Three State) 10 I-lAdc CS = O.BV or CS = 2.0V, VOUT = OAV to 2.4V Supply Current S6810 S68AI0/S68B10 80 100 mAdc mAdc Vec = 5.25V, all other pins grounded,TA = O°C A.C. Characteristics: Read Cycle (Vec = +5.0V ± 5%, Vss = O,TA=O°C to 70°C unless otherwise noted.) S6810 Symbol Parameter tCYC(R) Read Cycle Time Min. S68AIO Max. 450 Min. 868B1O Max. 360 Min. Max. 250 Units ns tacc Access Time tAS Address Setup Time 20 tAH Address Hold Time 0 tDDR Data Delay Time (Read) tRcs Read to Select Delay Time 0 0 0 ns tDHA Data Hold from Address 10 10 10 ns tH tDHW tRH 450 360 10 Data Hold from Write 10 Read Hold from Chip Select 0 20 20 0 10 60 10 0 5.191 ns 180 10 0 ns ns 10 60 ns ns 0 220 230 Output Hold Time 250 60 ns ns AMII~ 8681 0/868A 10/868810 Write Cycle (Vee = + 5.0V ± 5%, VSS = O,TA =O°C to 70°C unless otherwise noted.) S6810 Symbol Parameter tcyC(W) tAS Min. S68A10 Min. Max. S68B10 Max. Min. Max. Units Write Cycle Time 450 360 250 ns Address Setup Time 20 20 20 ns tAH Address Hold Time tes Chip Select Pulse Width 0 0 0 ns 300 250 210 ns twes Write to Chip Select Delay Time 0 0 0 ns tnsw Data Setup Time (Write) 100 80 60 ns Input Hold Time 10 10 10 ns Write Hold Time from Chip Select 0 0 0 ns tH tWH 1 - - - - - - - ICYCIRI Read Cycle Timing ----------+1 - - - - - lace - - - - · 1 ADDRESS CS CS RM DATA OUT O.BV 2.0V 2.0V O.BV ~~~r,l~.OVV----------------~------~~~~~~~~~ J ---------«========== _ a¥3 "-IDHA~ --tOHW----... .-.--IH DATA VALID ------ DDN·T CARE NOTE: CS AND CS CAN BE ENABLED FOR CONSECUTIVE READ CYCLES PROVIDED R W REMAINS AT VIH Write Cycle Timing . . DDWT CARE NOTE' CS AND CS CAN BE ENABLED FOR CONSECUTIVE WRITE CYCLES PROVIDED RMIS STROBED TO V BEFORE OR CDINCIDENTWITH THE ADDRESS IH CHANGE. AND REMAINS HIGH FOR TIME lAS' 5.192 AMII~ 5681 0/S68A 10/568810 AC Test Load 130 pF* MMD7000 OR EQUIV * Includes Jig Capacitance 5.193 • I I I t tt 89900 High Performance Microprocessor Family Sixteen Sit S9900 Fami MICROPROCESSORS 89900 16-Bit Microprocessor 89940 8ingle Chip Microcomputer 2K ROM, 128X8 RAM 89980A/S9981 16-Bit Microprocessor 8-Bit Data Bus (89981 has Internal Clock) S9901 Programmable Systems Interface IPSI) 89902 UART/Asynchronous Communications Controller (USRT/ACC) PERIPHERALS 6.2 Selection Guide PRELIMINARY DATA SHEET S9900 16-81T MICROPROCESSOR Features General Description o o The S9900 microprocessor is a single-chip 16-bit central processing unit (CPU) produced using N-channel silicon-gate MOS technology. The instruction set of the S9900 includes the capabilities offered by full minicomputers. The unique memory-to-memory architecture features multiple register files, resident in memory, which allow faster response to interrupts and increased programming flexibility. The separate bus structure simplifies the system design effort. AMI provides a compatible set of MOS memory and support circuits to be used with an 89900 system. The system is fully supported by software and complete prototyping systems. 16-Bit Instruction Word Full Minicomputer Instruction Set Capability including Multiply and Divide o Up to 65,536 Bytes of Memory o 3.3MHz Speed o Advanced Memory-to-Memory Architecture o Separate Memory, 1/0 and Interrupt-Bus Structures o 16 General Registers o 16 Prioritized Interrupts o Programmed and DMA 1/0 Capability ON-Channel Silicon-Gate Technology Pin Configuration Block Diagram v.. INTERRUPT ADDRESS READY WE CRUCLK 01 57 NC ¢2 56 D15 A14 10 55 D14 Atl 11 54 013 53 012 16 A8 18 AS 19 89900 23 . 24 VSS 26 25 V,, 21 .3 28 OBIN 29 CRUOUT 30 CRUIN 31 lNTREQ 32 NC=IIO_L_ 6.3 62 61 Vee AD DATA MEMEN 59 ClOCK-----' CRU HOLD 63 &0 A8 CONTROL 64 52 011 51 010 50 09 49 08 48 01 46 05 45 04 59900 S9900 Electrical and Mechanical Specifications Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless otherwise noted)* Supply Voltage, VCC (See Note 1) .......................................................... -O.3V to +20V Supply Voltage, VDD (See Note 1) .......................................................... - O.3V to + 20V Supply Voltage, Vss (See Note 1) ............................ '" ........................... -O.3V to +20V All Input Voltages (See Note 1) ............................................................ -O.3V to +20V Output Voltage (with Respect to Vss) ......................................................... - 2V to + 7V Continuous Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2W Operating Free-Air Temperature Range ..................................................... O°C to + 70°C Storage Temperature Range ............................................................ - 55°C to + 150°C ·Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Under absolute maximum ratings voltage values are with respect to the most negative supply, VBB (substrate), unless otherwise noted. Throughout the remainder of this section, voltage values are with respect to Vss. Recommended Operating Conditions Parameter Min. Nom. Max. Unit VBB Supply voltage -5.25 -5 -4.75 V Vce VDD Supply voltage Supply voltage 4.75 5 12 5.25 12.6 V 11.4 VSS VIH Supply voltage High-level input voltage (all inputs except clocks) 2.2 0 2.4 Vee+ 1 VIH(cp) High-level clock input voltage VIL VDD-2 -1 0.4 VDD 0.8 VIL(CP) Low-level input voltage (all inputs except clocks) Low-level clock input voltage -0.3 0.3 0.6 V V TA Operating free-air temperature 70 DC Symbol 0 Conditions V V V V Timing Requirements Over Full Range of Recommended Operating Conditions (See Figures 1 and 2) Min. Nom. Max. Unit 0.3 10 0.333 0.5 j.LS Clock fall time Pulse width, any clock high Delay time, clock 1 low to clock 2 low (time between clock pulses) 10 40 12 45 100 ns ns ns 0 5 ns tcl>2L. ~3L t~3L, ~4L Delay time, clock 2 low to clock 3 low (time between clock pulses) 0 5 ns Delay time, clock 3 low to clock 4 low (time between clock pulses) 0 5 ns t~4L. ~lL Delay time, clock 4 low to clock 1 low (time between clock pulses) Delay time, clock 1 high to clock 2 high (time between leading edges) 0 5 73 83 ns ns 73 73 83 ns 83 8 ns Symbol tc(cp ) tr(cp ) tr( ) tw(lH, cp2H tcp2H, cp3H t3H, 4H tcp4H, lH tsu th Parameter Clock cycle time Clock rise time Delay time, clock 2 high to clock 3 high (time between leading edges) Delay time, clock 3 high to clock 4 high (time between leading edges) Delay time, clock 4 high to clock 1 high (time between leading edges) Data or control setup time before clock 1 73 30 Data hold time after clock 1 10 6,4 12 ns ns ns Conditions AMII~ 89900 Electrical Characteristics Over Full Range of Recommended Operating Conditions (unless otherwise noted) Symbol Min. Parameter Unit Typ·t Max. ±50 ±100 ±50 ±100 ±25 ±1 ±75 110 mA mA mA VOH VOL Low-level output voltage IBB lee InD Supply current from VBB Supply current from Vee Supply current from Vnn Input capacitance (any inputs except clock and data bus) 0.1 50 25 Vee 0.65 0.50 1 75 45 10 15 pF Ci(ct>l) Clock-1 input capacitance 100 150 pF Ci(ct> 2) Clock-2 input capacitance 150 200 pF Cj(ct>3) Clock-3 input capacitance 100 150 pF Ci(ct>4) Clock-4 input capacitance 100 150 pF CnB Data bus capacitance 15 25 pF Co Output capacitance (any output except data bus) 10 15 pF II Cj t All typical values are at T A = 204 Conditions VI = VSS to Vee Data Bus during DBIN WE, MEMEN, DBIN, Address Input current bus, Data bus during HOLDA Clock* Any other inputs High -level output voltage J.lA VI = VSS to Vee VI = -0.3 to 12.6V VI = VSS to Vee V 10 = -OAmA V 10 = 32.mA 10 = 2mA VBB = -5, f = 1MHz, unmeasured pins at Vss VBB = -5, f = 1MHz, unmeasured pins at Vss VBB = -5, f = 1MHz unmeasured pins at Vss VBB = -5, f = 1MHz, unmeasured pins at Vss VBB = -5, f = 1MHz, unmeasured pins at Vss VBB = -5, f = IMHz, unmeasured pins at VSS VBB = -5, f = 1MHz, unmeasured pins at Vss 0 25 C and nominal voltages. *D.C. Component of Operating Clock. Switching Characteristics Over Full Range of Recommended Operating Conditions (See Figure 2) Symbol tpLH or tpHL Parameter Min. Propagation delay time. clocks to outputs CRUCLK, WE. MEMEN. WAIT. DBIN All other outputs 6.5 Typ. Max. Unit Conditions CL=200pF ~~0 20 40 ns ns Please contact your local AMI Sales Office for complete data sheet 59900 Figure 1. Clock Timing I- .1 1,1" .f+--"- 'd¢1H.2H---+j I 9.4V r - - - - . I 9.4V CLOCK¢1 0.7V I 10.7v: : II I,I¢I-II-- -11---'11,,1 I'-'.I¢I--II !--'<>20.¢30_1 ClOCK>!>2 II ___'+l_"\2L_h~n : I 2L CLOCK¢3 :: : /I II I I !-,.,O'''0-j I_-~n: ______ 'I ·_'3l I I CLOCK" II I t-,..o.<10----"jl ___________________'+3_L.\._L~~~~~-'+-4l.\-"--- Note: All timing and voltage levels shown on ~1 apply to ~2, ~3, and ~4 in the same manner. Figure 2. Signal Timing ~ ~~ _I'ru~ -J1h~ ~~L________~9.vf\~ : CLOCK (13 CLOCK.,A 9 . V n ' - - - -_ _ : : '''n n I I I -I ~IPlO 1 ' 1 0) r\1 1 _-----,--_---1 I .I -I I f"'V _I 1-4--'PlH \- I 1 --+-----.Jn~_ '''0- v 9 I -1=f- ______ I _1__________ __ 1.....-. tPHL 0 V '_' I 1 I --!...-I- ; - - - - - - ' - 1- - - -j 1_,PlO 1 tl::-='··V,..----------'-I- IPOL~~:~ ~ r l !~'= ..V--------------~~ lPOL -1 ~tPlHORtPHL I tThe number of cycles over which input/output data must/will remain valid can be determined from the number of wait states required for memory access. Note that in all cases data should not change during 1. 6.6 PRELIMINARY DATA SHEET S9940 MICROPROCESSOR Features General Description o o o o o o The 89940 is a single-chip, 16-bit microcomputer containing a CPU, memory (RAM and ROM), and extensive I/O. The instruction set of the 89940 is a subset of the 89900 instruction set and includes capabilities offered by minicomputers. The unique memory-to-memory architecture features multiple register files, resident in the RAM, which allow faster response to interrupts, and increased programming flexibility. The memory consists of 128 bytes of RAM and 2048 bytes of ROM. The 89940 implements four levels of interrupts, including an internal decrementer which can be programmed as a timer or an event counter. All members of the 89900 family of peripheral circuits are compatible with the 89940. 16-Bit Instruction Word Minicomputer Instruction Set Including Multiply and Divide 2048 Bytes of ROM on Chip 128 Bytes of RAM on Chip 16 General Purpose Registers 4 Prioritized Interrupts o On Chip Timer/Event Counter o 32 Bits General Purpose I/O o 256 Bits I/O Expansion o Multiprocessor System Interface o Single 5 Volt Power Supply o Power Down Capability for Low Stand-by Power ON-Channel Silicon Gate MOS Block Diagram Pin Configuration (16) (21) (22)(15) (37) (19) (10) (20) (8) (9) I I H N N R 0 T T S L 1 2 T 0 CONTROL C R U MEMORY (ROM/RAM) I/O PORTS o U T (17) /7l (14) /11) /18) (1·11) (14·18) (23·36) (38,39) 6.7 AMII~ 89940 S9940 Electrical Specifications Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless otherwise noted)* Supply Voltage, VCCI(l) ................................................................. -0.3V to +20V Supply Voltage, Vcc2(1) ................................................................. -0.3V to +20V Programming Voltage, PE (1) ............................................................ -0.3V to +35V All Input Voltages (1) ................................................................... -0.3V to +20V Output Voltage (1) ........................................................................ -2V to +7V Continuous Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... .. 1.5W Operating Free-Air Temperature Range ....................................................... O°C to 70°C Storage Temperature Range ........................................................... -55°C to + 150°C *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specification is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. (1) All voltage values are with respect to vss Recommended Operating Conditions Symbol Parameter VCCI Supply Voltage 5 VCC2 Supply Voltage 5 V Vss VIR VIL Supply Voltage 0 V VIP Test Input Voltage TA Operating Free-Air Temperature Min. High-Level Input Voltage Nom. Max. Unit Condition V 2.0 V Low-Level Input Voltage 0.8 +70 0 V V 26 °C Electrical Characteristics Symbol Parameter II VOH VOL High-Level Output Voltage, All Inputs Low-Level Output Voltage, All Outputs ICCI Supply Current from ICCI ICC2 CI Supply Current from ICC2 Co Output Capacitance, All Outputs Min. Nom. ±1O 2.4 0.4 10 150 15 Input Current, All Inputs Input Capacitance, All Inputs 15 Clock Characteristics The 89940 has an internal oscillator and 2-phase clock generator controlled by an external crystal. The user may also disable the oscillator and directly inject a frequency source into the XT AL2 input. The crystal frequency and the external frequency source must be 2 times the desired system frequency. 6.8 Max. Unit Condition JAA V VI=VSS to VCC Io=-O.4mA V Io=2mA mA mA pF pF f= IMHz unmeasured pins at Vss f= IMHz unmeasured pins at Vss Internal Clock Option The internal oscillator is enabled by connecting a crystal across XTAL1 and XT AL2. The system frequency is one-half the crystal frequency. AMII~ Symbol 89940 Parameter Condition Crystal Frequency Ext~rnal Clock Options An external frequency source can be used by injecting the frequency directly into XTAL2 with XTAL1left unconnected. The external frequency must conform to the following specifications: Symbol Parameter fext COUT VH External Source Frequency Min. Typ. Max. Unit 5 MHz Output capacitance of External Source 15 pF External Source High-Level 4.5 V VL External Source Low-Level OA V tw(H) External Source High-Level Pulse Width 90 ns tw(L) External Source Low-Level Pulse Width 90 ns Condition Switching Characteristics Over Full Range of Recommended Operating Conditions All external signal timings are with reference to cP (see Figure 1). Symbol Parameter tR,p Rise Time of cP tf,p Min. Typ. Max. Unit 20 ns Fall Time of cP 20 ns tw,p Pulse Width of cP 350 ns tDl Output Delay Time 100 ns tD2 Output Delay Time 400 ns tsu Input Set Up Time 10 ns tH Input Hold Time 0 ns Condition CL=100pF Programming Characteristics (see Figure 2). Typ. Symbol Parameter tRPE Rise Time of PE 50 ns Min. Max. Unit tFPE Fall Time of PE 50 ns tSUDA Data Set Up Time 0 ns tHDA Data Hold Time 0 ns tRPR t FPR tWPR Data Time of PROG 50 ns Fall Time of PROG 50 ns PROG Pulse Width 100 ms tHPE PE Hold Time 30 tp* tsupR t rst PROG Set Up Time 30 tp* Reset Time 800 ns *tp = System Clock Time Period 6.9 Condition Please contact your local AMI Sales Office for complete data sheet AMII~ 89940 Figure 1. External Signal Timing Diagram OSC INPUT If PO·PI6 P17·P31 All INPUTS CRU ADDRESS x x CRU IN CRU OUT CRU CLK x_____I x \'---- Figure 2. Programming Signal Timing Diagram "n~4~'" P E _ l i - - , , - . , - - ,- ~"'~ ~ DATA- ~'""'~ r X I~" l X I PROG _ _ w", l X J\""~ ~ '·'l ------J!~ --}'----,".1~ ~~~ 6.10 PRELIMINARY DATA SHEET S9980A/S9981 16·811 MICROPROCESSOR Features D 16-Bit Instruction Word D Full Minicomputer Instruction Set Capability Including Multiply and Divide D Up to 16,384 Bytes of Memory D 8-Bit Memory Data Bus D Advanced Memory-to-Memory Architecture D Separate Memory, 1/0, and Interrupt-Bus Structures D 16 General Registers D 4 Prioritized Interrupts D Programmed and DMA 1/0 Capability DOn-Chip 4-Phase Clock Generator D 40-Pin Package D N-Channel Silicon-Gate Technology The 89981 has an optional on-chip crystal oscillator in addition to the external clock mode of the 89980A. 3. The pin-outs are not compatible for DO-D7, INTOINT2, and ¢3. . Description· The S9980A and the S9981 although very similar, have several differences which are: 1. 2. The S9980A requires a VBB supply (pin 21) while the S9981 has an internal charge pump to generate V BB from Vee and V DD· The 89980A/S9981 is a software-compatible member of AMI's 9900 family of microprocessors. Designed to minimize the system cost for smaller systems, the 89980A/89981 is a single-chip 16-bit central processing unit (CPU) which has an 8-bit data bus, on-chip clock, and is packaged in a 40-pin package (see Figure 1). The instruction set of the 89980A/89981 includes the capabilities offered by full minicomputers and is exactly the same as the 9900's. The unique memory-to-memory architecture features multiple register files, resident in memory, which allow faster response to interrupts and increased programming flexibility. The separate bus structure simplifies the system design effort. Block Diagram Pin Configuration 9980 9981 HOLD MEMEN MEMEN HOLDA READY READY WE WE ADDRESS INTERRUPT lAO A131CRUOUT CONTROL CLOCK------l CRU CRUCLK A12 Villi All Vss Vss AID CKIN CKIN Villi A9 07 OSCOUT A8 D6 D7 A7 D5 DB A6 D4 D5 A5 D3 D4 A4 D2 D3 A3 D1 D2 Dl A2 DO A1 INT D DO AD INT 1 IHT D 0811 CRUll INT 2 INTI ~ INT 2 V.. ~3 DATA Vee 6.11 S9980A/S9981 S9980AlS9981 Electrical and Mechanical Specifications Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless otherwise noted)· Supply voltage, V cc (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3V to 15V Supply voltage, Vnn (see Note 1) ............................................................ - 0.3V to 15V Supply voltage, VBB (see Note 1) (9980A only) . .. .. .. .. .. .. .. .. .. .. .. . .. .. . .. .. . .. . . .. .. . .. ... - 5.25V to OV All input voltages (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - O.3V to 15V Output voltage (see Note 1) ................................................................... - 2V to 7V Continuous power dissipation...... .... ... .. .......... ...... ....... ..... .. ... .. . . ..... .... ....... 1.4W Operating free-air temperature range ......................................................... O°C to 70°C Storage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 150°C ·Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Under absolute maximum ratings voltage values are with respect to Vss. Recommended Operating Conditions Symbol Parameter Min. Nom. Max. Unit VBB Supply voltage (9980A only) -5.25 -5 -4.75 V VCC Supply voltage 4.75 5 5.25 V Vnn Supply voltage 11.4 12 12.6 V Vss Supply voltage VIR High-level input voltage 2.2 2.4 VIL Low-level input voltage -1 TA Operating free-air temperature 0 Conditions V 0 V 0.4 VCC+ 1 0.8 V 20 70 °C Electrical Characteristics Over full Range of Recommended Operating Conditions (unless otherwise noted) Symbol II VOH Typ.· Conditions Max. Unit Data bus during DBIN WE, MEMEN, DBIN ±75 J-lA VI = V ss to V cc during HOLDA Any other inputs ±75 ± 10 p.A /AA VI= Vss to Vee VI = Vss to Vce Parameter Min. Input current High-level output voltage V Io=-O.4mA 0.5 0.65 V Io=2mA I o =3.2mA 1 rnA 2.4 VOL Low-level output voltage IBB Supply current from V BB (9980A only) Icc Supply current from V cc 50 40 60 50 rnA O°C 70°C Inn Supply current from Vnn 70 65 80 75 rnA O°C 70°C CI Input capacitance (any inputs except data bus) 15 pF f = 1MHz, unmeasured pins at V ss CnB Data bus capacitance 25 pF f = 1MHz, unmeasured pins at V SS CO Output capacitance (any output except data bus) 15 pF f = 1MHz, unmeasured pins at V SS ·All typical values are at TA = 25°C and nominal voltages. 6.12 AMII~ S9980A/S9981 Clock Characteristics Figure 1. Crystal Oscillator Circuit The 89980A and 89981 have an internal 4-phase clock generator/driver. This is driven by an external TTL compatible signal to control the phase generation. In addition, the 89981 provides an output (08COUT) that in conjunction with CKIN forms an on-chip crystal oscillator. This oscillator requires an external crystal and two capacitors as shown in Figure 1. The external signal or crystal must be 4 times the desired system frequency. 59981 CKIN OSCOUT D CRYSTAL Internal Crystal Oscillator (9981 Only) The internal crystal oscillator is used as shown in Figure 1. The crystal should be a fundamental series 8ymbol Parameter resonant type. C1 and C2 represent the total capacitance on these pins including strays and parasitics. Min. Crystal frequency 6 C1,C2 10 Typ. Max. Unit Conditions 10 MHz 0°C-70°C 15 25 pF 0°C-70°C External Clock The external clock on the 89980A and optional on the 89981, uses the CKIN pin. In this mode the 08COUT pin of the 89981 must be left floating. The external clock source must conform to the following specifications. 8ymbol Parameter fext External source frequency· 6 VH External source high level 2.2 VL External source low level Min. Typ. Max. Unit 10 MHz Conditions V 0.8 10 V ns Tr/Tf External source rise/fall time TWH External source high level pulse width 40 ns TWL External source low level pulse width 40 ns *This allows a system speed of 1.5MHz to 2.5MHz Switching Characteristics Over Full Range of Recommended Operating Conditions The timing of all the inputs and outputs is controlled by the internal 4 phase clock; thus all timings are based on the width of one phase of the internal clock. This is 1/f(CKIN) (whether driven or from a crystal). This is'also 1/4 fsystem. In the following table this phase time is denoted two All external signals are with reference to cP3 (see Figure 2). 6.13 • Please contact your local AMI Sales Office for complete data sheet AMII~ S9980AlS9981 Symbol Parameter tr(cpa) Rise time of cpa Min. Typ. Max. Unit 3 5 10 ns 5 7.5 15 ns t~cpa) Fall time of cpa tw(cpa) Pulse width of cpa tw-15 tw-10 tw+ 10 ns tsu Data or control setup time· tw-30 ns th tpHL (WE) Data hold time· 21tw+ 1O ns Propagation delay time WE high to low tw-10 tw+20 tw tw+ 10 tw+30 tpLH (WE) Propagation delay time WE low to high tw Propagation delay time, CRUCLK high to low -20 -10 + 10 ns tpLH (CRUCLK) Propagation delay time, CRUCLK low to high 2tw-10 2tw 2tw+20 ns toy cPS low Delay time from output invalid to cPS low tox tw = l/f(CKIN) = 1/4 fsystem ns tpHL (CRUCLK) Delay time from output valid to Conditions ns CL = 200pf ns tw-50 tw-30 tw-20 tw ns ·All inputs except ICO-IC2 must be synchronized to meet these requirements. ICO-IC2 may change asynchronously. Figure 2. External Signal Timing Diagram w,.----- ~I.)~__t_f_(¢_)- - - - - - -..... I I I CRUClK r- -I l.... ,....-_..:.....-.....:...." - -...... ' ------~--------' --l OTHER OUTPUTS I t PlH I - t OV,¢3l tox,¢3l I 1 r==1 I ~ I VALID ~ ~~_ _ _ _ _ _ _ _ _ _ _~ 6.14 t PHl -\-""----- ADVANCED PRODUCT DESCRIPTION S9901 PROGRAMMABLE SYSTEMS INTERFACE CIRCUIT Features General Description • N -Channel Silicon -Gate Process The S9901 Programmable Systems Interface is a multifunctioned component designed to provide low cost interrupts and I/O ports in a 9900/9980 microprocessor system. It is fabricated with N -channel silicon-gate technology and is completely TTL compatible on all inputs including the power supply (+5V) and single-phase clock. Figure 1 is a block diagram of the S9901. The Programmable Systems Interface provides a 9900/9980 system with interrupt control, I/O ports, and a real-time clock as shown in Figure 2. • 9900 Series CRU Peripheral • Performs Interrupt and I/O Interface Functions - 6 Dedicated Interrupt Input Lines - 7 Dedicated I/O Ports - 9 Ports Programmable as Interrupts or I/O • Easily Stacked for Interrupt and I/O Expansion • Interval and Event Timer • Single 5V Supply Figure 1. Block Diagram S9901 Pin Configuration RSTl VCC so CRUOUT po CRUCLK CRUIN P1 TI Sl S2 INT7/P15 INTB/P14 INT9/P13 INT10/P12 INT11/P11 IC3 INTl2/P10 IC2 ffIm7I'9 IC1 INTl4/PB ICO P2 VSS S3 INTl 54 INTl5/P7 INT2 P6 P3 P5 P4 Figure 2. 9900/9980 System AODRESS BUS ,---------------------, ,-------------------, PROGRAMMABLE SYSTEMS INTERFACE MEMORY S9900/S99BO CPU OATA BUS 6.15 AMII~ S9901 S9901 Electrical Specifications Absolute Maximum Ratings Over Operating Free Air Temperature Range (Unless Otherwise Noted)* Supply Voltages, Vcc and VSS ................................................ -0.3V to +10V All Input and Output Voltages ................................................ -0.3V to +10V Continuous Power Dissipation ........................................................ 0.75W Operating Free-Air Temperature Range .......................................... O°C to +70°C Storage Temperature Range ................................................ -65°C to +150°C *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specification is not implied. Exposure to absolute maximum rated conditions for extended period may affect device reliability. Recommended Operating Conditions Parameter Supply Voltage, V cc Min. Nom. Max. Unit 4.75 5 5.25 V Supply Voltage, V ss 0 V High-Level Input Voltage, VIH 2 V Low-Level Input Voltage, VIL 0.8 V °C 70 0 Operating Free-Air Temperature, TA Electrical Characteristics Over Full Range of Recommended Operating Conditions (Unless Otherwise Noted) Symbol II VOH Parameter Min. Input Current (Any Input) Typ. Max. ±10 High Level Output Voltage Unit Conditions fJ.A V VI= OV to Vcc 2.4 2 V IOH = -400fJ.A IOL = 3.2mA VOL Low Level Output Voltage 0.4 V Icc Supply Current from V cc 100 rnA Iss Supply Current from V ss 200 rnA ICC(av) Average Supply Current from V cc 60 Ci Co Capacitance, Any Input Capacitance, Any Output 10 20 rnA pF pF IoH = 100fJ.A tc(¢) = 333ns, TA = 25°C f = 1MHz, All Other Pins at OV Timing Requirements Over Full Range of Operating Conditions Symbol Parameter Min. Nom. Max. Unit tc(cf» bock Cycle Time 333 ns tr(cf» Clock Rise Time 10 ns tf(cf» Clock Fall Time 10 ns tW(cf>L) tw(cf>H) Clock Pulse Low Width 55 ns Clock Pulse High Width 240 ns tsu Setup Time for SO-S4, CE, or CRUOUT before CRUCLK 200 ns tsu Setup Time, Input Before Valid CRUIN 200 ns tsu Setup Time, Interrupt Before ¢ Low 40 ns 100 80 ns ns tw(CRUCLK) CRU Clock Pulse Width Address Hold Time th 6.16 Please contact your local AMI Sales Office for complete data sheet AMII~ S9901 Switching Characteristics Over Full Range of Recommended Operating Conditions Symbol tpD tpD Parameter Typ. Min. Propagation Delay, ¢ Low to Valid INTREQ, Ico -IC3 Propagation Delay, SO-S4 or CE to Valid CRUIN Max. Unit Test Conditions 80 ns CL = 100pF, 2 TTL Loads 400 ns CL = 100pF Figure 3. Switching Characteristics ~ 'wl.L)...J ----------~I U I 'su~ ',I.) --.II.- I~------~I U I _ I ______________:~______ __ I r-------~I U __ 'wl.H)_ I -----..j .....f - - - - - ' c l . ) - - - - - - . J U I I ~ -INT-E-RR-UP-T----~I\~ ~ 'H.) t-- _JI 1 I I "'-'su : I IpD IpD - - , I /4- -IN-TR-EQ------------------------~~~___________________________J/~-----------I---'su I -.j ~IPD----i~~1 I ~~~1_______~/~--~\~____________~:----------------I ~ C_R_uC_LK________ I ---.j I II 1: II ISU I I I ~ IwlcRUCLK) ~~~-------------------------------I--------------------I I \.-Ih-..j f-- f + - - - - I p D -----l.~1 VALID ADDRESS VALID ADDRESS SO·S4 I I I I I I I I I I I r------X I '--'su--1 • VALID INPUT DATA . INTl·INTl5,PO·P15 r-------VA-L-ID-CR-UI-N-------X CRUIN I "fI/II.II#.. 1'TTTT'T"T'T"1t-- 'su CRUDUT I I I I I I I-- Ih ~ 1M!"7t"1rlr"1M!"7t"1rlr"!nMI:"'II"1I'"!nMI:"'II"1I'"1!""I\""Pnnr1!""l\""Pnnr"1\"1\"1nnr"1\"1\"1~"1\"1\"1~"1\"1\"1~T1r1iX"T --.j I VALID DATA ! NDTE1: ALL TIMING MEASUREMENTS ARE FRDM 10%.nd 90% POINTS 6.17 ADVANCED PRODUCT DESCRIPTION S9902 ASYNCHRONOUS COMMUNICATIONS CONTROLLER (ACC) Features General Description • • • • • The S9902 Asynchronous Communication Controller (ACC) is a peripheral device for the S9900 family of microprocessors. The ACC provides an interface between the microprocessor and a serial asynchronous communication channel, performing the timing and data serialization and deserialization, thus facilitating the control of the asynchronous channel by the microprocessor. 5 - to 8 -Bit Character Length 1, 1 1/2, or 2 Stop Bits Even, Odd, or No Parity Fully Programmable Data Rate Generation Interval Timer with Resolution from 64 to 16,320 j.1.S • Fully TTL Compatible, Including Single Power Supply. Figure 2. Pin Configuration Figure 1. Block Diagram iNT DSR XOUT CE CE RIN SO-S4 CRUIN CRUOUT CRUCLK CRUIN Vcc CPU IfF RIN INT CTS RTS XOUT 6.18 CRUCLK R'fS so rn SI liSA S2 CRUOUT S3 VS5 54 59902 S9902 Electrical Specifications Absolute Maximum Ratings Over Operating Free Air Temperature Range (Unless Otherwise Noted)* Supply Voltage, Vcc ........................................................ -0.3V to +10V All Inputs and Output Voltages ................................................ - 0.3V to +10V Continuous Power Dissipation .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0.7W Operating Free-Air Temperature Range .......................................... O°C to +70°C Storage Temperature Range ................................................ - 65°C to +150°C *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specification is not implied. Exposure to Absolute Maximum Rated conditions for extended periods may affect device'reliability. Recommended Operating Conditions Parameter Supply Voltage, V cc Min. Nom. Max. 4.75 5 5.25 Supply Voltage, V SS Unit 0 High-Level Input Voltage, VIH 2.2 2.4 Low-Level Input Voltage, VIL VCC 0.8 0.4 Operating Free-Air Temperature, TA V V 0 70 V V °c Electrical Characteristics Over Full Range of Recommended Operating Conditions (Unless Otherwise Noted) Symbol Parameter Min. Typ. Max. Unit f,J.A II Input Current (Any Input) VOH High-Level Output Voltage VOL Low-Level Output Voltage 0.4 0.85 V ICC(AV) Average Supply Current from Vee 2.5 100 rnA Ci Capacitance, Any Input 10 Co Capacitance, Any Output 20 ±10 2.2 3.0 2.0 2.5 V pF Conditions VI = OV to Vcc IOH = -100f,J.A IOH = -400f,J.A IOL = 3.2mA tc(+-00, '----1>+-00, 20 17 ill 19 R/W-----; '------;>+-00, Oo---------t 877302 Truth Table Pin Names CEI CE2 OD R/W DIN Output Mode H X L X X X X X H H H X X X X X X HighZ HighZ HighZ HighZ HighZ Dout Not selected Not Selected Output Disabled Write Write Read X X L L L H H H 877301 L L L L H AO- A7 DII- DI4 DOI-D04 OD 8.3 Address Inputs Data Inputs Data Outputs Output Disable CEI CE2 R/W VCC Chip Enable Chip Enable Read/Write Input +5 Volt Power Supply AMII~ 85101 General Description (Continued) The stored data is read out nondestructively and is the same polarity as the original input data. The S5101 is totally static, making clocks unnecessary for a new address to be accepted. The device has two chip enable inputs (GEl and CE2) allowing easy system expansion. CE2 disables the entire device but CE1 does not disable the address buffers and decoders. Thus, minimum power dissipation is achieved when CE2 is low. The L version of the S5101 has the additional feature of guaranteed data retention with the power supply as low as 2 volts. This makes the device an ideal choice when battery augmented non-volatile RAM storage is mandatory. The S5101 is fabricated using a silicon gate CMOS process suitable for high volume production of ultra low power, high performance memories. Absolute Maximum Ratings· Ambient Temperature Under Bias ...................................................... -lOoC to 80°C Storage Temperature. . . .. . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . .. -65°C to 150°C Voltage on Any Pin with Respect to Ground ........................................ -0.3V to Vee +O.3V Maximum Power Supply Voltage .................................................................. 8V Power Dissipation ............................................................................... 1W *eOMMENT: Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. D.C. Characteristics: TA = O°C to 70°C, Vee = 5V ± 5% (Unless otherwise specified) Symbol Limits Min. Max. 1 Units Conditions tJ.A VIN = OV to Vee CE1 = Vrn VOUT = OV to Vee Outputs = Open, VIN = VIL to Vee VIN = OV to Vee except CE2 ~0.2V ILl Parameter Input Leakage Current ILO Output Leakage Current 1 tJ.A lee Operating Supply Current 22 rnA IeeL Standby Supply Current VIL VIH VOL VOH Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 10 140 500 0.65 Vee 0.4 tJ.A tJ.A tJ.A V V V V S5101L1,S5101L S5101L3 S5101L8, S5101-8 -0.3 2.2 2.4 IOL - 2 rnA IOH = -1 rnA Capacitance Symbol CIN Co Limits Min. Max. Parameter Input Capacitance Output Capacitance 8 12 8.4 Units pF pF Conditions VIN = OV, on all Input Pins Vo =OV AMlt. 85101 A.C. Characteristics for Read Cycle: TA Symbol Parameter TRC TACC TC01 TC02 TOD Read Cycle Time Access Time CE1 to Output Delay CE2 to Output Delay Output Disable to Enabled Output Delay TDP Output Disable to Output H· Z State Delay TOH1 Output Data Valid Into Next Cycle with respect to Address Output Data Valid Into Next Cycle with respect to Chip Enable TOH2 = O°C to 70°C, Vcc 5V ± 5% (Unless otherwise specified) S5101L S5101L3 Limits Min. Max. 650 S5101L1 Limits Min. Max. 450 450 650 400 600 500 700 250 350 130 0 = 0 S5101L8 S5101·8 Limits Min. Max. 800 800 800 850 150 0 Units Conditions ns ns ns ns 450 ns 200 ns 0 0 0 ns 0 0 0 ns See A.C. Conditions of Test and A.C. Test Load Read Cycle ADDRESS 'I '\V }r\ --'~ \l j\ eE2 - / - TOH1 - TCOI l.t Too- -~---------------, T V "~ TC02 ~ K DATA au I I-- TOH2- \J DO I TRC TRC -t---------------TACC J OF FT - K DATA OUT VALID ---""\1 ___ .J\ ----T ACC ---- DATA OUT VALID \- j H-Z STATE 1016145 Note: 1. OD may be tied low for seaprate I/O information. 2. The output will go into a high impedance state if either CE1 is high, CE2 is low, OD is high or R/W is low. 8.5 AMII~ 55101 A.C. Characteristics for Write Cycle - Separate or Common Data I/O Using Output Disable TA :::: O°C to 70°C, VCC :::: 5V ± 5% (Unless otherwise specified) Symbol TWC TAW TCW1 TCW2 TDW TDH TWp TWR TDS S5101L S5101L3 Limits Max. Min. 650 150 550 550 S5101L8 S5101·8 Limits Min. Max. 800 200 650 650 250 400 450 ns 50 250 100 400 100 450 ns ns 50 50 100 ns 130 150 200 ns S5101L1 Limits Parameter Min. 450 130 350 350 Write Cycle Time Address To Write Delay CE1 to Write Delay CE2 to Write Delay Data Set·Up to End of Write Time Data Hold After End of Write Time Write Pulse Width End of Write to New Address Recovery Time Output Disable to Data·In Set-Up Time Max. Units ns ns ns ns Write Cycle - For Separate or Common Data I/O ADDRESS 'V ..J1\ \V II\- Tewl i\ V GE2 TCW2 - t-t1 V 00 - !I_-Tos-- ,IIIr\-- TOH- \V 11\ DATA IN DATA IN STABLE Tow R/W ~ _-TAW 1\ I TWR - - - 1-,"'-jJ--_ _ _~C ~ DATA OUT V Twp HIZSTATE 1076147 8.6 • Conditions See A.C. Conditions of Test and A.C. Test Load 55101 Low VCC Data Retention Characteristics for S5101 L, S5101 L 1, S5101 L3 and S5101 L8 [11 TA = O°C to 70°C Symbol VDR ICCDR TCRD TR Min. 2.0 Parameter Vcc for Data Retention Limits Max. 10 140 500 S5101L1, S5101L Data Retention S5101L3 Supply Current S5101L8 Chip Deselect to Data Retention Time Operation Recovery Time 0 TRd21 Units V /LA /LA p.A ns ns Conditions CE2~0.2V Vcc = VDR TR = TF = 20ns CE2~0.2V Nota;; [1] For guaranteed low Vee Data Retention @ 2.0V, order must specify S5101L, S5101L1, S5101L3 or S5101L8. [2] THe = Read Cycle TIme. Low Vee Data Retention Wave Form DATA RETENTION MODE Vee °01- ', " eE2 1. 2 3. 4. -.tCD - GJ; (] IL ----- TR (] -r0(i) 4.75V VDR VIH O.2V 477215 A.C. Test Load 1.73V f-- 0 I--- .> 85101 D.U.T. :~ 660n f-- A.C. Conditions of Test O.65V to 2.2V Input Levels 20ns Input Rise and Fall Time 1.5V Timing Measurement Reference Level 11O"F -= 1076146 8.7 ADVANCED PRODUCT DESCRIPTION S6504 4096 BIT (4096X1) STATIC CMOS RAM Features General Description o o o The AMI S6504 is a 4096 X 1 bit low power CMOS RAM offering static operation with a single + 5V power supply. All inputs and outputs are fully TTL compatible. The addresses are buffered by on-chip address latches. These internal registers are latched by the HIGH to LOW transition of the CE. The write enable and chip enable functions are designed such that either separate or common data 110 operat ms can be easily implemented for maximum design flexibility. o o o o Low Standby Power-lO!JW Typ. Low Operating Power-20m W Typ. Low Voltage Data Retention - 2.0V High Density Standard 18 Pin Package Fast Access Time 300ns On Chip Address Latches SiGate CMOS Technology Logic Symbol Block Diagram o ADDRESS LATCHES ROW DECODERS 32X128 ARRAY Vi Pin Configuration CE AD Al AD 17 VCC A6 16 A7 15 A8 A9 A2 A3 Al A4 A5 A3 A4 14 A6 A5 13 Al0 A7 0 12 All A8 W 11 A9 GND 10 A2 A1D All 5 6 7 8 9 10 11 Pin Names Truth Table Mode w AD-All ................ Address Inputs Data In Data Out Q ............................... Output D .............................. Data In CE ............ Chip Enable (Active LOW) W ............ Write Enable (Active LOW) VCC ................. +5V Power Supply Read H L x Data In Write L L x Hi-Z Not Selected x H x Hi·Z 8.8 CE S6508/S6508A 1024 BIT (1024X1) STATIC CMOS RAM Features General Description D Ultra Low Standby Power The AMI S6508 family of 1024x1 bit static CMOS RAMs offers ultra low power dissipation with a single power supply. The device is available in two versions. The basic part (S6508) operates on 5V and is directly TTL compatible on all inputs and the three-state output. The S6508 "A" operates from 4V to 11V and is fully CMOS compatible. The data is stored in ultra low power CMOS static RAM cells (six transistor). The stored data is read out nondestructively and is the same polarity as the original input data. The address is buffered by on-chip address registers. These internal registers are latched by the HIGH to LOW transition of chip enable (CE). The write enable and chip enable functions are designed such that either separate or common data I/O operations can be easily implemented for maximum design flexibility. D S6508 Completely TTL Compatible D S6508A Completely CMOS Compatible D 4V to 11 V Operation (S6508A) D Data Retention at 2V D Three-State Output D Low Operating Power: 10mW D @ 1MHz (5V) Fast Access Time: 115ns @ 10V Pin Configuration Logic Symbol Block Diagram CE DIN WE 1 15 14 AD A1 Ao------l A1--A2 A3 ROW ~~~~~~ A2 32,32 ARRAY A3 DECODER A4 A4--A5 AS 10 A7 11 A S - - + - i COLUMN AS 12 ~~~~~~ A9 13 A5--+--1 A7 AS DECODER A9,---+--l DOUT '--1>-- DDUT OINI----f--+-l~ Pin Names AO-A9 Address Inputs CE DIN Data Input WE Write Enable VCC Power Supply DOUT 8.9 Data Output Chip Enable S6508/S6508A General Description (Continued) The S6508 is. fabricated using a silicon gate CMOS process suitable for high volume production of high performance, ultra low power memories. When deselected (CE = HIGH), the S6508-1 draws less than 10 microamps from the 5V supply. In addition, it offers guaranteed data retention with the power supply as low as 2 volts. This process makes the device an ideal choice where battery augmented nonvolatile RAM storage is mandatory. CMOS to TTL - 56508/56508-1 Absolute Maximum Ratings 8upply Voltage .................................................................... 8.0 V Input or Output Voltage Supplied .................................... GND - 0.5V to VCC + 0.5V 8torage Temperature Range ................................................. -65°C to 150°C Operating Temperature Range, Commercial ........................................ O°C to 70°C D.C. Characteristics (VCC = 5.0V ± 10%, TA = O°C to 70°C) 8ymbol VIH VIL IlL VOH2 VOH1 VOL2 VOL1 10 ICCL ICC CIN Co Parameter Logical "1" Input Voltage Logical "0" Input Voltage Input Leakage Logical "1" Output Voltage Logical "1" Output Voltage Logical "0" Output Voltage Logical "0" Output Voltage Output Leakage IS6508 Standby Supply Current, S6508-1 Min. Units Max. VCC- 2.0 -1.0 VCC- 0.01 2.4 -1.0 0.8 1.0 GND+O.Ol 0.45 1.0 100 10 2.5 7.0 10.0 Supply Current S6508/86508-1 Input Capacitance Output Capacitance V V MA V V V V MA MA MA mA pF pF Conditions OV< VIN< VCC lOUT:;: 0 IOH = -0.2mA lOUT:;: 0 IOL = 2.0mA OV< VO< VCC,CE=VIH VIN = VCC f= 1MHz A.C. Characteristics (VCC = 5.0V ± 10%, CL = 50pF (One TTL Load), TA = O°C to 70°C) 8ymbol Parameter tACC tEN tDIS tCEH tCEL twp tA8 tAH tD8 tDH tMOD Access Time from CE Output Enable Time Output Disable Time CE HIGH CELOW Write Pulse Width (LOW) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Data Modify Time 86508-1 Min. Max. 86508 Min. Max. 300 180 180 460 285 285 200 300 200 7 90 200 0 0 300 460 300 15 130 300 0 0 8.10 Units ns ns ns ns ns ns ns ns ns ns ns Conditions See A.C. conditions of test and A.C. test load. AMII~ S650S/S650SA CMOS to CMOS - S6508A/S6508A-1 Absolute Maximum Ratings Supply Voltage ................................................................... 12.0V Input or Output Voltage Applied ......................................... -0.5V to VCC + 0.5V Storage Temperature Range ................................................. _65°C to 150°C Operating Temperature Range, Commercial ........................................ 0° C to 70° C D.C. Characteristics (VCC == 4V to 11V, TA == O°C to 70°C) Symbol VIH VIL IlL VOH VOL 10 ICCL ICC CIN Co Max. Min. Parameter Logical "1" Input Voltage 70% VCC Logical "0" Input Voltage 20% VCC -1.0 1.0 Input Leakage Logical "1" Output Voltage VCC- 0.01 GND+0.01 Logical "0" Output Voltage -1.0 1.0 Output Leakage 500 S6508A Standby Supply Current 100 S6508A-1 Supply Current 2.5 VCC==5V (S6508A/S6508A-1) VCC==10V 5.0 7.0 Input Capacitance 10.0 Output Capacitance Units V V f.lA Conditions f.lA OV < VIN< VCC lOUT == 0 IOUT== 0 OV-t-sJ-J;;:1''---<>---H DATA I/O CONTROL D/03-----C)-¥--¥-<'I----"'.....Jot'---<>---t--i AO-A9 D/QI-D /Q4 CE WE Address Inputs Data Inputs/Outputs Chip Enable Write Enable Truth Table w Data Out Read L H Data In Write L H L X HI-Z Mode Disable 8.14 HI-Z 56514 Absolute Maximum Ratings Supply Voltage - VCC ..................................................... '" -0.3V to +7.0V Input/Output Voltage Applied ............................................. -0.3V to VCC +0.3V Storage Temperature-Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -65°C to + 150 °C DC Electrical Characteristics: TA= O°C to 70°C, VCC = +5V±100/0 Symbol Parameter ILl ILO ISB ICC VIL VIH VOL VOH Input Leakage Current Output Leakage Current Standby Supply Current Operating Supply Current Input Voltage LOW Input Voltage HIGH Output Voltage LOW Output Voltage HIGH Capacitance: Symbol Cin Cout Min. -1 -0.3 2.4 2.4 Typ. I: 1 Max. 1 1 50 7 0.8 VCC+0.3 0.4 Units /LA /LA /LA rnA V V V V Conditions Vin=GND Vin=GND Vin=GND Vin=GND to VCC to VCC orVCC orVCC,f=lMHz IUL-1.6mA IOH=O.4mA TA=25°C, t=lMHz. Capacitance is sampled and guaranteed. Min. Parameter Input Capacitance Output Capacitance Low vce Data Retention Characteristics: Symbol Parameter Min. ICCDR ICC For Data Retention VCCDR VCC for Data Retention 2.0 tCDR Chip Deselect to Data 0 Retention Time tR Operation Recovery Time TELEL Typ. Max. 8 10 Typ .. Max. 25 Units pF pF Units p.A V ns Conditions Conditions Vin=GND or vce Low VCC Data Retention Wave Form _ V G) CC DATA RETENTION MODE cr~TCOR-K ® ® 1. 4.7SV 2. VOR 3. VIH 4.0.2V AC Test Conditions t rise/t fall ................................................................................ 20ns Output Load .............................................................................. 50pF All Timing ................................................................................ 1.5V 8.15 86514 AC Electrical Characteristics: Symbol TELQV TAVQV TWLQZ TEHQZ TELEH TEHEL TAVEL TELAX TWLWH TWLEH TELWH TDVWH TWHDZ TWHEL TQVWL TWLDV TELWL TWHEH TELEL TA=O°C to 70°C, VCC=5V± 10% Parameter , Min. Chip Enable Access Time Address Access Time Write Enable Output Disable Time Chip Enable Output Disable Time Chip Enable Pulse Negative Width 300 Chip Enable Pulse Positive Width 120 Address Setup Time 20 Address Hold Time 50 Write Enable Pulse Width 300 Write Enable Pulse Setup Time 300 Write Enable Pulse Hold Time 300 Data Setup Time 200 Data Hold Time 0 Write Enable Read Setup Time 0 Output Data Valid to Write Time 0 Write Data Delay Time 100 Early Output High-Z Time Late Output High-Z Time Read or Write Cycle Time 420 I Typ. , Max. 300 320 100 100 0 0 Read Modify Write Cycle Note 1: TElEl & TElEH are longer than the minimum given for Read or Write cycle. 8.16 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions AMII. 86514 Read Cycle: WE = HIGH Write Cycle DO V HIGH-Z f\~_ _----,-, f---TDVWH~ 1......---- TELWH 8.17 -l !--TWHDZ Read Only Memories (ROMs) S6831B 16,384 BIT (2048x8) STATIC NMOS ROM General Description Features +5V Power Supply o Single o Directly TTL Compatible Inputs o Three-State TTL Compatible Outputs o Three Programmable Enables The AMI S6831B is a 16,384 bit mask programmable Read-Only-Memory offering fully static operation with a single + 5V power supply. The device is fully TTL compatible on all inputs and three-state outputs. The three enables are mask programmable, the active level is specified by the user. The S6813B is pin compatible with the 2708 and 2716 EPROMs. Software developed in EPROMs can be put in low cost ROM for high volume production. o Access Time: 450ns Maximum o 2716 EPROM Pin Compatible o The device is organized as 2048 words by 8 bits, a configuration particularly suitable for microprocessors. The 86831B is manufactured with an N-channel silicon gate depletion load technology. Low Power: Supply Current is SOmA Maximum Block Diagram Logic Symbol CSl CS2 Pin Configuration CS3 An An A1 A, Aa A. On A7 ADDRESS DECODER DRIVER 01 As Vee A6 As As Ag A6 A. CS3 Aa CSl A, A1n A1 CS2 An 07 06 ADDRESS DECODER DRIVER CSl CS2 CS3 CHIP SELECT DECODER" Pin Names 'PROGRAMMABLE CHIP SELECTS Ao-AIO Address Inputs QO-Q7 CSI-CS3 Data Outputs Chip Select Inputs Vee +5V Power Supply 9.2 00 06 01 as a, 0, GND 03 868318 Absolute Maximum Ratings Ambient Temperature Under Bias ....................................................... -O°C to 70°C Storage Temperature ......... , ....... , .... ... .. . . .. . . .. . . . . . . . . . . .. . . . . . . . . . . . . . .. . .. -65°C to 150°C Output or Supply Voltages ............................................................... -0.5V to 7V Input Voltages .......................................................................... -0.5V to 7V Power Dissipation ............................................................................... 1W *COMMENT: Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may effect device reliability. D.C. Characteristics: Vee = +5V ± 5%, TA =O°C to 70°C Symbol VIR ILl Parameter Output LOW Voltage Output HIGH Voltage Input LOW Voltage Input HIGH Voltage Input Leakage Current ho Output Leakage Current 10 t-t A VIN=OV to 5.25V Vo = OAV to 5.25V Chip Deselected Icc Power Supply Current 70 rnA Vce=5.25V, TA =O°C Max. 7 10 Units pF pF Max. 450 Units ns ns 200 150 ns ns VOL VOH V1L Min. Typ. 2.4 -0.5 2.0 Max. 0.4 0.8 Vee 10 Units V V V V J1A Conditions IOL=3.2mA IOH=- 22Ot-t A Capacitance: TA =25°C, f= 1.0MHz Symbol CIN CO UT Parameter Input Capacitance Output Capacitance Min. Typ. Conditions VIN=OV VOUT=OV A.C. Characteristics: Vcc = + 5V ± 5%, TA =O°C to 70°C Symbol /;eyC tAA tAE toFF Parameter Read Cycle Time Address Access Time Enable Access Time Output Disable Time Min. 450 Typ. 10 Propagation Delay from Address Inputs Propagation Delay From Chip Enable 9.3 Conditions See Test Circuit and Waveforms AMII~ S68318 A.C. Test Conditions Input Pulse Levels ......................................................................... O.4V to 2.4V Input Rise and Fall Times ........................................................................ <;20ns Input Timing Level ...................................................................... , ......... 1.5V Output Timing Levels ............................................ ;....................... O.BV and 2.0V Output Load .................................................. ~ . . . . . . . . . . . .. 1 TTL Gate and CL = lOOpF Custom Programming The preferred method of pattern submission is the AMI Hex format as described below, with its built-in address space mapping and error checking. This is the format produced by the AMI Assembler. The format is as follows and may be on paper tape, punched cards or other media readable by AMI. Position 1 2 3,4 5,6,7,8 9, ... ,N N+l, N+2 Example: Description Start of record (Letter S) Type of record 0- Header record (comments) 1 - Data record 9 - End of file record Byte Count Since each data byte is represented as two hex characters, the byte count must be multiplied by two to get the number of characters to the end of the record. (This includes checksum and address data.) Records may be of any length defined in each record by the byte count. Address Value The memory location where the first data byte of this record is to be stored. Addresses should be in ascending order. Data Each data byte is represented by two hex characters. Most significant character first. Checksum The one's complement of the additive summation (without carry) of the data bytes, the address, and the byte count. Sl13000049E9FI0320F0493139F72000F5EOF00126 S9030000FC ~ 'E'E 00 ~~ _ ~ U)~ £ U) ~~ § ~ "'''' 8 ~ i~ ~ ~ ~ 0 llA~, 1 ~ ~~ 6 \~ S113000049E9FI0320F0493139F72000F5EOF00126 NOTES: 1. Only positive logic formats for EO, El, E2 are accepted. 1 = VHIGH; 0 = VLOW 2. A "0" indicates the chip is enabled by a logic O. A" 1" indicates the chip is enabled by a logic 1. 3. Paper tape format is the same as the card format above except: a. The record should be a maximum of 80 characters. b. Carriage return and line feed after each record followed by another record. c. There should NOT be any extra line feed between records at all. d. After the last record, four (4) $$$$ (dollar) signs should be p1,lnched with carriage return and line feed indicating end of file. 9.4 S68332/S68A332 32,768 BIT (4096x8) STATIC NMOS ROM Features General Description 0 Fast Access Time: S68332: 450ns Maximum S68A332: 350ns Maximum 0 Fully Static Operation The AMI S68332 is a 32,768 bit static mask programmable NMOS ROM organized as 4096 words by 8 bits. The device is fully TTL compatible on all inputs and outputs and has a single + 5V power supply. The three state outputs facilitate memory expansion by allowing the outputs to be OR-tied to other devices. 0 Single +5V ±5% Power Supply 0 Directly TTL Compatible Inputs 0 Three-State TTL Compatible Outputs 0 Two Programmable Chip Selects 0 EPROM Pin Compatible Block Diagram A. A5 A6 A, A, The S68332 is pin compatible with UV EPROMs making system development much easier and more cost effective. It is fully static, requiring no clocks for operation. The two chip selects are mask programmable, the active level for each being specified by the user. The S68332 is fabricated using AMI's N-Channel MOS technology. This permits the manufacture of very high density, high performance mask programmable ROMs. Pin Configuration Logic Symbol A, AD A, ADDRESS DECODER DRIVER 00 Aa 0, Ag 02 A,. AD A, A2 Aa ADDRESS DECODER DRIVER Al1 CS1 CS2 CHIP SELECT DECODER" As A. A3 03 A2 D. A, 05 AD 0, 00 0, 0, 0, 05 0, D. GND 03 BUFFERS Pin Names "PROGRAMMABLE CHIP SELECTS 9.5 A,. Ao-All Address Inputs QO-Q7 Data Outputs CSI - CS2 Chip Select Inputs Vee + 5V Power Supply AMII~ S68332/S68A332 Absolute Maximum Ratings * Ambient Temperature Under Bias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .. -O°C to 70°C Storage Temperature ............... ~ ............................................... , -65°C to 150°C Output or Supply Voltages ............................................................... -0.5V to 7V Input Voltages ......................................................................... -0.5V to 7V Power Dissipation ............................................................................... 1W *COMMENT: Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these orat any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may effect device reliability. D.C. Characteristics: Vee = +5V ± 5%, TA =O°C to 70°C Symbol Parameter Output LOW Voltage VOL Output HIGH Voltage VOH VIL Input LOW Voltage Input HIGH Voltage VIR Input Leakage Current ILl Min. Typ. Max. 0.4 2.4 -0.5 2.0 0.8 Vee 10 Units V V V V Conditions IOL=3.2mA IOH= -220JAA ILO Output Leakage Current 10 JAA VIN = OV to 5.25V VO=O.4V to 5.25V Chip Deselected lee Power Supply Current 70 mA Vee=5.25V, TA =O°C Max. 7 10 Units pF pF JAA Capacitance: TA =25°C, f= 1.0MHz Symbol Parameter Input Capacitance CIN Output Capacitance COUT Min. Typ. Conditions VIN=OV VOUT=OV A.C. Characteristics: Vee = +5V ± 5%, TA =O°C to 70°C Symbol Parameter tAA Address Access Time t Aes Chip 8elect Access Time tOFF Chip Deselect Time Min. Typ. S68332 S68A332 868332 Max. 450 Units ns 350 150 ns ns 868A332 868332 0 150 150 ns ns 868A332 0 150 ns Waveforms AU-All See. A.C. Test Conditions and Waveform ______ ~....._ _ _ _ _ _ _ _ _ _ __ ~ ~_. ~tAA~ ~~* _ ____ 00-07 Conditions __ __ --------------- VALID DATA Propagation From Address Propagation From Chip Select 9.6 S68332/S68A332 A.C. Test Conditions InputPulseLevels ....................................................................... O.4Vto2.4V Input Rise and Fall Times ...................................................................... ~ 20ns Input Timing Level .............................................................................. 1.5V Output Timing Levels .................................................................. O.8V and 2.0V Output Load ................................................................... 1 TTLLoadandlOOpF Custom Programming The preferred method of pattern submission is the AMI Hex format as described below, with its built-in address space mapping and error checking. This is the format produced by the AMI Assembler. The format is as follows and may be on paper tape, punched cards or other media readable by AMI. Position 1 2 3,4 5,6,7,8 9, ... ,N N+l, N+2 Example: Description Start of record (Letter S) Type of record o - Header record (comments) 1 - Data record 9 - End of file record Byte Count Since each data byte is represented as two hex characters, the byte count must be multiplied by two to get the number of characters to the end of the record. (This includes checksum and address data.) Records may be of any length defined in each record by the byte count. Address Value The memory location where the first data byte of this record is to be stored. Addresses should be in ascending order. Data Each data byte is represented by two hex characters. Most significant character first. Checksum The one's complement of the additive summation (without carry) of the data bytes, the address, and the byte count. Sl13000049E9FI0320F0493139F72000F5EOF00126 S9030000FC ~ 'E'E 00 ~~ _ U U ~~ § ~ CIl a CIl ~~ 0 ~ ~o...p ~ ;;~ ~ :3 ~ ~ 1iS 0 £ r15 JJA~/ rj)~ 00 ~ ;A. 'oJ ,1, \~ S113000049E9FI0320F0493139F72000F5EOF00126 NOTES: 1. Only positive logic fonnats for CS1 and CS2 are accepted. 1 '" VHIGH; 0 = VLOW 2. A "0" indicates the chip is enabled bya logic O. A "1" indicates the chip is enabled by a logic 1. 3. Paper tape fonnat is the same as the card fonnat above except: a. The record should be a maximum of 80 characters. b. Carriage return and line feed after each record followed by another record. c. There should NOT be any extra line feed between records at all. d. After the last record, four (4) $$$$ (dollar) signs should be punched with carriage return and line feed indicating end of file. 9.7 ADVANCED PRODUCT DESCRIPTION 84264 65,536 BIT (8192x8) STATIC NMOS ROM Features General Description o Single +5V ± 10% Power Supply o High Performance: Maximum Access Time: 450ns The AMI S4264 is a 65,536 bit fully static NMOS mask programmable ROM organized as 8192 words by 8 bits. The device is fully TTL compatible on all inputs and outputs and has a single + 5V power supply. The three-state outputs facilitate memory expansion by allowing the outputs to be OR-tied to other devices. o EPROM Compatible for Cost Effective System Development o Completely Static Operation o Directly TTL Compatible Inputs o Three-State TTL Compatible Outputs o Industry Standard 24 Pin Package Block Diagram The S4264 is fully static requiring no clocks for operation. Data access is simple as no address setup times are required. The byte organization of the S4264 makes it ideal for microprocessor applications. The S4264 is fabricated using AMI's proprietary NMOS technology. This process permits the manufacture of very high density, high performance mask programmable ROMs. Pin Configuration Logic Symbol cs A7 Vee As As As Ag 00 AO Al A2 A3 A, 01 0, Os 06 07 Al0 All Au A12 cs 03 As A6 A7 As Ag A, A3 02 ADDRESS DECODER DRIVER ADDRESS DECODER DRIVER A2 Al0 Al Au AD 07 00 Os 01 05 02 0, 03 Pin Names Ao-A12 ......................... Address Inputs Qo -Q7 ............................ Data Outputs CS ............................ Chip Select Inputs Vee ............. ;............ + 5V Power Supply 9.8 AMII~ 84264 Absolute Maximum Ratings· Ambient Temperature Under Bias ...................................................... O°C to 70°C Storage Temperature ................................................................ , -65°C to 150°C Output or Supply Voltages ................ :.............................................. -0.5V to 7V Input Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .. . . .. -0.5V to 7V Power Dissipation ............................................................................... 1W *COMMENT: Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. D.C. Characteristics: T A=0 °C Symbol to 70 °C, Vee = +5V ± 10% VOL VOH VIL VIH ILl Parameter Output LOW Voltage Output HIGH Voltage Input LOW Voltage Input HIGH Voltage Input Leakage Current Min. Typ. ho Output Leakage Current 10 IlA Icc Power Supply Current 100 rnA Max. 7 10 Units pF pF Max. 450 Units ns Conditions See Test Circuit 150 150 ns ns and Waveforms Max. 0.4 2.4 -0.5 2.0 Units V V V V 0.8 Vee 10 IlA Conditions IOL=3.2mA IoH =- 22OIlA VIN=OV to 5.5V CS;;;;'2.4V, VO=O.4V to 5.5V Vee=5.5V, TA =O°C Capacitance: TA =25°C, f=l.OMHz Symbol CIN Parameter Input Capacitance Output Capacitance COUT A.C. Characteristics: TA=O°C Symbol Min. Min. Chip Select Access Time Chip Deselect Time toFF Conditions VIN=OV VOUT=OV to 70°C, Vee = +5V ± 10% Parameter Address Access Time tAA tAes Typ. Typ. 0 Wave Forms Propagation Delay From Address Propagation Delay From Chip Select AO'A12~_~_t_ 00-07 cs ------z::....-~j~-V-A-lI-DO-A-TA-- 00-07 9.9 1. ~ V 1\ fI ~ VALlO DATA tOFF I AMII~ 54264 A.C. Test Conditions Input Pulse Levels ..................................................................... OAV to 2AV Input Rise and Fall Times ..................................................................... ~20ns Input Timing Levels ............................................................................ 1.5V Output Timing Levels ................................................................. O.SV to 2.0V Output Load ................................................................. 1 TTL Load and 100pF Custom Programming The preferred method of pattern submission is the AMI Hex format as described below, with its built-in address space mapping and error checking. This is the format produced by the AMI Assembler. The format is as follows and may be on paper tape, punched cards or other media readable by AMI (see NOTES at bottom of page). Position 1 2 3,4 5,6,7,S 9, ... ,N N+l, N+2 Example: Description Start of record (Letter S) Type of record 0- Header record (comments) 1 - Data record 9 - End of file record Byte Count Since each data byte is represented as two hex characters, the byte count must be multiplied by two to get the number of characters to the end of the record. (This includes checksum and address data.) Records may be of any length defined in each record by the byte count. Address Value The memory location where the first data byte of this record is to be stored. Addresses should be in ascending order. Data Each data byte is represented by two hex characters. Most significant character first. Checksum The one's complement of the additive summation (without carry) of the data bytes, the address, and the byte count. Sl13000049E9FI0320F0493139F72000F5EOF00126 S9030000FC >< 'E'E ~ 00 ~~ ~ ~~ ;j 'H'H 0 00 U ~~ £ ~~.& ! !A ~ ]v §... ~ ~ ~ ~ ,r-_________ 00. ~ ~ 0 1 --J ~ \ u ~ Sl13000049E9FI0320F0493139F72000F5EOF00126 NOTES: 1. Paper tape format is the same as the card format above except: a. The record should be a maximum of 80 characters. b. Carriage return and line feed after each record followed by another record. c. There should NOT be any extra line feed between records at all. d. After the last record, four (4) $$$$ (dollar) signs should be punched with carriage return and line feed indicating end of file. 9.10 UV EPROMs S5204A 512 X 8 BIT ERASABLE AND ELECTRICALLY REPROGRAMMABLE READ ONLY MEMORY Features General Description o o o The S5204A is a high speed, static, 512x8 bit, erasable and electrically programmable read only memory designed for use in bus-organized systems. Both input and output are TTL compatible during both read and write modes. Packaged in a 24-pin hermetically sealed dual in -line package, the bit pattern can be erased by exposing the chip to an ultraviolet light source through the transparent lid, after which a new pattern can be written. o o o o o o o On-Board Programmability Fast Access Time - 750ns Max. High Speed Programming - Less than 1 Minute for all 4096 Bits Programmed with R/W, CS and VpROG Pins Completely TTL Compatible - Excluding the VPROG Pin during Read or Write Ultraviolet Light Erasable - Less than 10 Minutes Static Operation - No Clocks Required Three-State Data I/O Standard Power Supplies - +5V and -12V Mature P-Channel Process Block Diagram AO AI A2 A3 Pin Configuration 64x64 BIT PROM ARRAY '"A5 AS A7 AS Y·GATING SENSE AMPLIFIERS 3·STATE INPUT/OUTPUT BUFFERS GSO RWOR CSI VPROG -+------' Typical Applications 00 0 I 02 0304050607 o o o o o o o o 77675 10.2 ROM Program Debugging Code Translation Microprogramming Look-up Tables Random Logic Replacement Programmable Waveforms Character Generation Electronic Keyboards Please contact your local AMI Sales Office for complete data sheet AMII. S5204A ABSOLUTE MAXIMUM RATINGS +0.3 to -20V +0.3 to -60V O°C to +70°C -55°C to +85°C _55°C to 150°C Voltage on any pin relative to VSS except the VPROG pin Voltage on the VPROG pin relative to VSS ... . . Operating Temperature Storage Temperature (programmed) Storage Temperature (unprogrammed) NOTE: This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields, however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. DC (STATIC) CHARACTERISTICS (VCC = +5.0V ± 5%, VGG = -12 .OV ± 5% T A = 0 - 70u C unless otherwise noted). MIN MAX UNIT INPUT VOLTAGE LOW 0.8 V VIH INPUT VOLTAGE HIGH VCC -2.25 VCC t.3 V VOL OUTPUT VOLTAGE LOW IOL::: 1.6 rna 0.4 V VOH OUTPUT VOLTAGE HIGH ILl INPUT LEAKAGE CURRENT 10 JJa ILO OUTPUT LEAKAGE CURRENT CS=5V VGG SUPPLY CURRENT 20 JJa 45 rna VCC SUPPLY CURRENT 50 rna 750 mw SYMBOL VIL CHARACTERISTIC V 2.4 IOH = 200tlA IGG ICC PD POWER DISSIPATION NOTE: Program input VpROG may be tied to VCC during the Read. AC (DYNAMIC) CHARACTERISTICS (Loading is as shown in Figure 1 unless otherwise noted). SYMBOL MIN CHARACTERISTIC MAX UNIT TACC ACCESS TIME 750 ns TCO CHIP SELECT TO OUTPUT DELAY CHIP DESELECT TO OUTPUT DELAY 400 ns TDD ns 10.3 • S6834 ERASABLE AND ELECTRICALLY PROGRAMMABLE READ ONLY MEMORY Features General Description o o The S6834 is a high speed, static, 512 x 8 bit, erasable and electrically programmable read only memory designed for use in bus-organized systems. Both input and output are TTL compatible during both read and write modes. Packaged in a 24 pin hennetically sealed dual in-line package the bit pattern can be erased by exposing the chip to an ultra-violet light source through the transparent lid, after which a new pattern can be written. o o o o o o o o o On-Board Programmability Fast Access Time - 57 5ns Typ. Pin Configuration Similar to the S6830 1K x 8 Bit ROM High Speed Programming - Less than 1 Minute for All 4096 Bits Programmed with R/W, CS and VPROG Pins Completely TIL Compatible - Excluding the VPROG Pin Ultraviolet Light Erasable - Less than 10 Minutes Static Operation - No Clocks Required Three-State Data I/O Standard Power Supplies +5V and -12V Mature P-Channel Process Block Diagram Pin Configuration GNO AO A1 A2 A3 64,64 BIT PROM ARRAY A4 A5 A6 A7 GSO RWOR CS1 A1 01 A2 02 A3 03 A4 04 A5 05 A6 06 A, 0, As VGG cs Y-GATING A8 Ao Do SENSE AMPLIFIERS 3-STATE INPUT 10UTPUT BUFFERS VPROG RJW Vee Vee 0001020304050607 Typical Applications VPROG o o o o o o o o lOA ROM Program Debugging Code Translation Microprogramming Look-up Tables Random Logic Replacement Programmable Waveforms Character Generation Electronic Keyboards Please contact your local AMI Sales Office for complete data sheet AMII~ 56834 ABSOLUTE MAXIMUM RATINGS +0.3 to -20V +0.3 to -60V O°C to +70°C -55°C to +85°C -55°C to 150°C Voltage on any pin relative to VSS except the VpROG pin Voltage on the VPROG pin relative to VSS Operating Temperature .. . . . Storage Temperature (programmed) Storage Temperature (unprogrammed) NOTE: This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields, however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. DC (STATIC) CHA~CTER[STICS (VCC = +5.0V ± 5%, VGG = -12.0V ± 5% TA = 0 -70 C unless otherwise noted). fJ SYMBOL MIN MAX UNIT 0.8 V VCC -2.25 Vce +.3 V 0.4 V CHARACTERISTIC VIL INPUT VOLTAGE LOW VIH INPUT VOLTAGE HIGH VOL OUTPUT VOLTAGE LOW 10L::: 1.6 rna VOH OUTPUT VOLTAGE HIGH V 2.4 IOH =200J.(A INPUT LEAKAGE CURRENT 10 Jla Jla IGG OUTPUT LEAKAGE CURRENT CS =5V V GG SUPPLY CURRENT 20 45 rna ICC V CC SUPPLY CURRENT 50 rna PD POWER DISSIPATION 750 mw ILl ILO NOTE: Program input VPROG may be tied to VCC during the Read. AC (DYNAMIC) CHARACTERISTICS (Loading is as shown in Figure 1 unless otherwise noted). SYMBOL TACC TCO TDD MIN CHARACTERISTIC (6834) CHIP SELECT TO OUTPUT DELAY CHIP DESELECT TO OUTPUT DELAY 10.5 UNIT 750 ns 300 400 ns 250 325 ns 575 ACCESS TIME MAX (6834-1) Uncommitted Logic Arrays ADVANCED PRODUCT DESCRIPTION UNCOMMITTED LOGIC ARRAYS Features Description o Arrays of uncommitted G-MOS devices "programmed" by metal layer interconnect to implement arbitrary digital logic functions. o Six array configurations-from 300 to 1260 gates. AMI's Uncommitted Logic Array (ULA) products consist of arrays of C-MOS devices whose interconnections are initially unspecified. By "programming" interconnect at the metal layer mask level, virtually arbitrary configurations of digital logic can be realized in an LSI implementation. o Quick Turn Prototypes. o Advanced oxide-isolated C-MOS technology. o High Performance-5 to 10 ns typical gate delay. o Broad Power Supply Range-2.5V to 12V. o TTL Compatible 1/0. o Up to 76 110 connections. o Numerous package options. o Full Military temperature range (-55°C to 125°C). AMI ULA designs are based on topological cells-Le., groups of uncommitted silicon-gate N-channel and P-channel transistors-that are placed at regular intervals along the X and Y axes of the chip with intervening poly silicon underpasses. Pads, input protection circuitry, and uncommitted output drivers are placed around the periphery. A family of C-MOS ULA products is offered in six configurations, summarized in Table I, with circuit complexities equivalent to 300, 400, 540, 770, 1000, and 1260 two-input gates, respectively. All pads (except the two pre-assigned power supply connections) can be individually configured as inputs, outputs, pr I/O's. Input switching characteristics can be programmed for either C-MOS or TTL compatibility. LS Buffer output drivers will support C-MOS levels or two low power schottky TTL loads. TTL Buffer outputs will also provide C-MOS levels and are capable of driving TABLE I Circuit Equivalent Two-Input Gates Pads LS Output Drivers TTL Output Drivers Low Drive 110 UA-1 UA-2 UA-3 UA-4 UA-5 UA-6 300 400 540 770 1000 1260 40 46 52 62 70 78 17 23 25 31 35 39 20 20 24 28 32 36 1 1 1 11.2 1 1 1 AMII~ two standard TTL loads. One low drive (C-MOS level) output driver is provided. All output drivers can be programmed for tri-state or open drain (open collector) operation as required. Pinout or lead count varies with die size and array complexity as shown in Table I. The arrays are offered in standard 40-pin, 48-pin, and 64-pin DIPs (plastic, ceramic or cerdip). Lower lead count DIPs can be provided on request, as can JEDEC-Standard Leadless Chip Carrier (LCC) packages. AMI ULA products are also offered in wafer or unpackaged die form where required. The C-MOS technology used for these products is AMI's state-of-the-art 5-micron, oxide-isolated, silicongate C-MOSprocess. This process offers all the conventional advantages of C-MOS-i.e., very low power consumption, broad power supply voltage range (2.5V to 12V), and high noise immunity-as well as dense circuits with high performance. Gate propagation delays are in the five to ten ns range for room temperature operation. AMI ULA products operate over the full military temperature range (-55°C to 125°C). gate equivalents they utilize are shown in Table II. AMI will convert customer designed logic to metal interconnect patterns using functional overlays and its proprietary Symbolic Interactive Design System (SIDS). SIDS is a computer aided design tool for layout using on-line color graphics terminals. Interested customers should submit logic diagrams for evaluation and a quotation. For programs involving multiple ULA patterns from customers with suitable MaS design and layout experience, AMI will also support arrangements in which the customer designs the ULA metal interconnect patterns and furnishes AMI with corresponding metal mask PG tapes to AMI specifications. TABLE II In conjunction with these arrays, AMI has developed a set of "functional overlays." These are basic logic element building blocks-e.g. two input and larger gates of various types, flip-flops, and so forth-from which complete logic designs can be developed. Each functional overlay corresponds to a metal interconnect pattern that is superimposed on a set of uncommitted transistors (and polysilicon underpasses) in the array to implement the logic element. Typical functional overlay logic elements and the number of two-input Logic Element 2-Input Gate Equivalent 2-Input NOR 2-Input NAND 3-lnput NOR 3-Input NAND INVERTER D FLIP-FLOP D FLIP-FLOP W/RESET D FLIP-FLOP W/SET-RESET J-K FLIP-FLOP CLOCKED LATCH EXCLUSIVE OR SCHMITT TRIGGER 4-BIT BCD CNTR W/RESET 1 1 1.5 1.5 .5 4 5 6 6.5 2 2.5 5.5 27 DC Characteristics-TTL Interface Specified @ VDD = +5V ±5% Temperature = -55°C to + 125 °C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage VOH Output High Voltage (LS Buffer IOH = -700 J.'a) (T-Buffer IOH = -1.5 rna) IOL Ioz Min. Typ. Max. V 2.0 0.8 -10 11.3 V V V 2.7 2.4 Output Low Voltage (T Buffer IOL = 3.2 rna) (LS Buffer IOL = 0.8 rna) 3-State Output Leakage Vo = 0 or VDD Unit 0.001 0.4 0.4 V V 10 J.'a AMII~ D.C. Characteristics - Sym. Parameter Inn Quiescent Device Current CMOS Interface VDD (Vdc) Condition Limits *TLow Min Max 5V VIN = VnD lOV Max 0.1 .005 0.1 1 p,A/gate 0.2 .01 0.2 2 p,A/gate 0.05 0.05 V VOL Low Level Output Voltage VOR High Level Output Voltage 5V lo=ltJA 10V VIL Input Low Voltage 5V 10V VIR Input High Voltage 5V lOV 3.5 7.0 3.5 7.0 IOL Output Low (Sink) Current T Buffer 5V Vo=0.4V lOV Vo=0.5V 4 7 4 7 5V. Vo=OAV 10V Vo=0.5V 1.0 1.8 1.0 1.8 LS Buffer lOR 0.05 lo=ltJA Units * THigh Min Max' 25°C Typ Min 4.95 9.95 4.95 9.95 4.95 9.95 1.5 3.0 1.5 3.0 V V 1.5 3.0 V V 3.5 7.0 V V 6.5 12.5 3.2 4.0 rnA rnA 1.6 3.1 0.8 1.0 rnA rnA Output High (Source) Current T Buffer 5V Vo=4.6V lOV I Vo=9.5V -400 -750 -400 -750 -400 tJ A -750 tJ A LS Buffer 5V Vo=4.6V lOV Vo=9.5V -200 -375 -200 -375 -200 tJ A -375 t-tA lIN Input Current VIN=O or VDD 1 1 1 tJ A loz 3 State Output Leakage Current Vo=O or VDD ±1 ±1 ±lO t-tA Input Capacitance Any Input 5 * Military Temperature Range is -55°C to + 125 °C. Commercial Temperature Range is -40°C to +85°C. 11.4 pF Application Note Summary Application Note Summary Communications Products 82559 Digital Tone Generator ..................................................................... 79T01 Describes design considerations, test methods, and results obtained using the 82559 Tone Generator family in DTMF pushbutton telephones. Interface with type 500 and 2500 networks are discussed. Use in ancillary equipment is also covered. Consumer Products Useful Noise .................................................................................... 79COI The 82688 Noise Generator is useful in many applications where digital noise is required for audio effects. Programming the 88890 Rhythm Generator ........................................................ 79C02 Explains the program format and how to submit data for ROM programming. Touch M08 for Capacitive 8witching .............................................................. 79C03 Explains the circuit operation and the design formulas needed to determine system parameters of pad areas, scan clock frequency and reference level adjustments. 18 Touchy Questions ............................................................................. 79C04 Answers many of the common questions which may arise when using TouchControl. This note should provide assistance for the successful design of a TouchControl system. M08 Music ..................................................................................... 79C05 M08 Music is a primer on the application of standard M08/L8I circuits in creating electronic music. This note discusses the key elements of music production in an electronic organ. Real Remote Control ............................................................................. 79C06 A remote control system using the 82742 and 82743 with infrared transmission is shown. A simple but effective alignment technique is demonstrated which will ensure successful operation. S2000 Family Extended Memory ............................................................................. 792KOI This note describes the necessary circuitry needed to extend the program memory (ROM) beyond an 82000/82150's normal amount. Musical Application for an 82000 Microcomputer ................................................... 792K02 This note describes some theory and the application of a microcomputer to generate musical notes. Applications might include electronic games, alarm clock, door bells and telephones. Repertory Dialers/Feature Phones Using 82000/82150 ............................................... 792K05 This note describes how an 82000/82150 can be used in a repertory dialer circuit and how to communicate with external RAM. 12.2 Application Note Summary S2000 Software TouchControl Keyboard Scan and Display Output ................................... 792K06 This note describes programs for typical display output with delay and a keyboard scan and debounce. This program will handle eight digits and up to 32 keys. S2000 Software Seconds Timing and Display ...................................................... 792K07 This note describes several useful software timing/display routines and the associated hardware. Analog-to-Digital Conversion Using the S2000 Family .............................................. 792KI0 This note describes several A/D schemes using the S2000 family, e.g., from a simple single slope integration method with an S2000 to a complex scheme using the S2200's on-chip A/D converter. S2000 Family Technical Articles ................................................................. 792Kl1 This brochure contains several reprints of articles on S2000 family members. Programmable Appliance/Outlet Controller Using the S2000/S2150 ................................... 792K14 This note describes an intelligent programmable appliance/outlet controller. 56800 Family S68047 Video Display Generator ..................... " ................................ /........... 796801 Describes a low cost link between an MPU and a standard black and white or color television set. A Minimal S6802/S6846 System Design ............................................................ 796802 Details how to make an S6802/S6846 version of the EVK in a minimal systems application. Microprocessor Crystal Specification .............................................................. 796803 Aids the MPU system designer in specifying and ordering the crystal required for the S6802 microprocessor. 59900 Family S9900 Simplifies Design of Bi-Directional 1/0 Module ................................................ 799901 Illustrates use of the CPU. The design can be used for simple TTL logic testers. (Reprint form Electronics) Minimum System Design with the S9900 16-Bit Microprocessor ....................................... 799902 This design uses just the CPU, a 1K ROM, a 2K RAM, a clock and six smaller IC's. Controlled Dot Matrix Printer - S9900 ............................................................ 799903 Shows how to control a 7040 series dot matrix printer. S9900 Technical Article Reprints .................................................................. 799904 A compilation of 6 technical articles covering: a comparison of the 9900, Z8000 and 8086; an 8-page description of the 9900; a real-time control software design using the 9900; a multiprocessor system design using the 9900; the bidirectional I/O module identical to the above application note; using the 9940 to implement the NBS data encryption standard. • 12.3 General Infonnation AMII~ Guide to MOS Handling At AMI we are continually searching for more effective methods of providing protection for MOS devices. Present configurations of protective devices are the result of years of research and review of field problems. 6. Humidity is controlled at a minimum of 35% to help reduce generation of static voltages. 7. All parts are transported in conductive trays. Use of plastic containers is forbidden. Axial leaded parts are stored in conductive foam, such as Velofoam#7611. In the normal course of producing integrated circuits however, there occasionally occur variations in oxide thickness which may allow a condition where gate oxide breakdown voltage is less than the protective device breakdown. Although the oxide breakdown voltage may still be far beyond normal voltage levels encountered in operation, excessive voltages may cause permanent damage. Even though AMI has evolved the best designed protective device possible, we recognize that it is not 100% effective. A large number of failed returns have been due to misapplication of biases. In particular, forward bias conditions cause excessive current through the protective devices, which in turn will vaporize metal lines to the inputs. Careful inspection of the device data sheets and proper pin designation should help reduce this failure mode. Gate ruptures caused by static discharge also account for a large percentage of device failures in customers' manufacturing areas. Precautions should be taken to minimize the possibility of static charges occurring during handling and assembly of MOS circuits. To assist our customers in reducing the hazards which may be detrimental to MOS circuits, the following guidelines for handling MOS are offered. The precautions listed here are used at AMI. 1. All benches used for assembly or test of MOS circuits are covered with conductive sheets. WARNING: Never expose an operator directly to a hard electrical ground. For safety reasons, the operator must have a resistance of at least lOOK Ohms between himself and hard electrical ground. 2. All entrances to work areas have grounding plates on door and/or floor, which must be contacted by people entering the area. 3. Conductive straps are worn inside and outside of employees' shoes so that body charges are grounded when entering work area. 4. Anti-static neutralized smocks are worn to eliminate the possibility of static charges being generated by friction of normal wear. Two types are available; Dupont anti-static nylon and Dupont neutralized 65% polyester/35% cotton. 8. All equipment used in the assembly area must be thoroughly grounded. Attention should be given to equipment that may be inductively coupled and generate stray voltages. Soldering irons must have grounded tips. Grounding must also be provided for solder posts, reflow soldering equipment, etc. 9. During assembly of I.C.'s to printed circuit boards, it is advisable to place a grounding clip across the fingers of the board to ground all leads and lines on the board. 10. Use of carpets should be discouraged in work areas, but in other areas may be treated with anit-static solution to reduce static generation. 11. MOS parts should be handled on conductive surfaces and the handler must touch the conductive surface before touching the parts. 12. In addition, no power should be applied to the socket or board while the MOS device is being inserted. This permits any static charge accumulated on the MOS device to be safely removed before power is applied. 13. MOS devices should not be handled by their leads unless absolutely necessary. If possible, MOS devices should be handled by their packages as opposed to their leads. 14. In general, materials prone to static charge accumulation should not come in contact with MOS devices. These precautions should be observed even when an MOS device is suspected of being defective. The true cause of failure cannot be accurately determined if the device is damaged due to static charge build-up. It should be remembered that even the most elaborate physical prevention techniques will not eliminate device failure if personnel are not fully trained in the proper handling of MOS. This is a most important point and should not be overlooked. More information can be obtained by contacting the Product Assurance Department. 5. Cotton gloves are worn while handling parts. Nylon gloves and rubber finger cots are not allowed. B.2 American Microsystems, Inc. 3800 Homestead Road Santa Clara, California 95051 Telephone (408) 246-0330 TWX 910-338-0024 or 910-338-0018 AMII~ MOS Processes PROCESS DESCRIPTIONS served as the foundation for the MOS/LSI industry and still finds use today in some devices. Several versions of this process have evolved since its earliest days. A thin slice (8 to 10 mils) of lightly doped N-type silicon wafer serves as the substrate or body of the MOS transistor. Two closely spaced, heavily doped P-type regions, the source and drain, are formed within the substrate by selective diffusion of an impurity that provides holes as majority electrical carriers. A thin deposited layer of aluminum metal, the gate, covers the area between the source and drain regions, but is electrically insulated from the substrate by a thin layer (1000-15000..\.) of silicon dioxide. The P-Channel transistor is turned on by a negative gate voltage and conducts current between Each of the major MOS processes is described on the following pages. First, the established production proven processes are described, followed by those advanced processes, which are starting to go into volume production now. In each case, the basic processes is described first, followed by an explanation of its advantages, applications, etc. P-CHANNEL METAL GATE PROCESS Of all the basic MOS processes, P-Channel Metal Gate is the oldest and the most completely developed. It has Figure B.1. Summary of MOS Process Characteristics P·CHANNEL METAL GATE VARIA liONS: 1. High Threshold (HiVT) 2. Low Threshold (LoVT) I I MATERIALS: N·SILICON SUBSTRATE - (111) FOR HIGH VT, (100) FOR LOW VT. ALUMINUM GATE, SOURCE, AND DRAIN CONTACTS. PERFORMANCE: POOR SPEED-POWER PRODUCT: VT/VTF TRADEOFF. COMPLEXITY: TYPICALLY 15 DR LESS PROCESS STEPS. I·ATE~LS : SAME AS ABOVE, ALWAYS (111) SILICON. PERFORM ANCE: LOWER VT BY ALTERING TERM; HIGH VTF OF [111) SILICON; ENHANCEMENT AND DEPLETION MODE TRAN· SISTORS POSSIBLE COMPLEX IT Y: OVER 15, lESS THAN 20 PROCESS STEPS. ION IMPLANTED P·CHANNEL METAL GATE VARIATIONS: 1. With enhancement and depletion mode devices on same chip a8 P.CHANNEL SILICON GATE (Usually with Ion Implantation) VARIATIONS: 1. With buried interconnect layer 2. With enhancement and depletion mode devices on same chip 3. Selective Fox (Field Oxidation) 4. Four VT Process CMOS VARIATIONS: 1. Planar, N+/P+ Poly 2. Selective Fox, N+Poly 3. Selective Fox, N+ Poly, isolated P·Well / N.CHANNEL I ~FOR.' NCE: I MATERIALS: (111) SUBSTRATE, DOPED POLYCRYSTALLINE SILICON GATE PERFORMANCE: LOWER VT THROUGH ~MS TERM, BUT HIGH VTF OF (111) SILICON COMPLEXITY: 15·20 PROCESS STEPS, BUT OVER 25 WITH COMBINED ENHANCEMENT AND DEPLETION MODE DEVICES MATERIALS: [1 ~O) P·S/LICON SUBSTRATE, DOPING POLY· SILICON. GATE, ION IMPLANTED FIELD PERFORMANCE: FAST CIRCUITS, THROUGH HIGH MOBILITY (J..<) OF ELECTRONS COMPLEXITY: SAME AS P-CHANNEL SiGATE FOR OLDER PROCESSES. 20·25 PROCESS STEPS FOR NEWER PROCESSES. LOW POWER, HIGH SPEED MATERIALS : (100) N·SILICON SUBSTRATE, ION IMPLANTED P·WELL COMPLEXIT Y: OVER 25 PROCESS STEPS SPECIAL PR OCESS: LINEAR CAPACITORS FOR SWITCHED CAPCITOR LINEAR INTEGRATED CIRCUITS B.3 I MOS Processes the source and the drain by means of holes as the majority carriers. The basic P-Channel metal gate prOCElSS can be subdivided into two general categories: High-threshold and low-threshold. Various manufacturers use different techniques (particularly so with the low threshold process) to achieve similar results, but the difference between them always rests in the threshold voltage VT required to turn a transistor on. The high threshold VT is typically - 3 to - 5 volts and the low threshold VT is typically - 1.5 to - 2.5 volts. The original technique used to achieve the difference in threshold voltages was by the use of substrates with different crystalline structures. The high VT process used [111] silicon whereas, the low VT process used [100] silicon. The difference in the silicon structure causes the surface charge between the substrate and the silicon dioxide to change in such a manner that it lowers the threshold voltages. One of the main advantages of lowering VT is the ability to interface the device with TTL circuitry. However, the use of [100] silicon carries with it a distinct disadvantage also. Just as the surface layer of the [100] silicon can be inverted by a lower VT, so it also can be inverted at other random locations-through the thick oxide layers-by large voltages that may appear in the metal interconnections between circuit components. This is undesirable because it creates parasitic transistors, which interfere with circuit operation. The maximum voltage that can be carried in the interconnections is called the parasitic field oxide threshold voltage VTF , and generally limits the overall voltage at which a circuit can operate. This, then, is the main factor that limits the use of the [100] low VT process. A drop in VTF between a high VT and low VT process may, for example, be from - 28V to -17V. The low VT process, because of its lower operating voltages, usually produces circuits with a lower operating speed than the high VT process, but is easier to interface with other circuits, consumes less power, and therefore is more suitable for clocked circuits. Both P-Channel metal gate processes yield devices slower in speed than those made by other MOS processes, and have a relatively poor speed/power product. Both processes require two power supplies in most circuit designs, but the high VT process, because it operates at a high threshold voltage, has excellent noise immunity. Ion Implanted P-Channel Metal Gate Process The P-Channel Ion Implanted process uses essentially the same geometrical structure and the same materials as the high VT P-Channel process, but includes the ion implantation step. The purpose of ion implantation is to introduce P-type impurity ions into the substrate in the limited area under the gate electrode. By changing the characteristics of the substrate in the gate area, it is possible to lower the thr~shold voltage VT of the transistor, without influencing any other of its properties. Figure B.2. shows the ion implantation step in a diagrammatic manner. It is performed after the gate oxide is grown, but before the source, gate, and drain metallization deposition. The wafer is exposed to an ion beam which penetrates through the thin gate oxide layer and implants ions into the silicon substrate. Other areas of the substrate are protected both by the thicker oxide layer and sometimes also by other masking means. Ion implantation can be used with any process and, therefore could, except for the custom of the industry, be considered a special technique, rather than a process in itself. Figure B.2. Diagram of Ion Implantation Step BORON (P-TYPE) IONS FROM IMPLANTER ACCELERATOR IMPLANTED HERE The implantation of P-type ions into the substrate, in effect, reduces the effective concentration of N-type ions in the channel area and thus lowers the VT required to turn the transistor on. At the same time, it does not alter the N-type ion concentration elsewhere in the substrate and therefore, does not reduce the parasitic field oxide threshold voltage VTF (a problem with the low VT P-Channel Metal Gate process, described above). The [111] silicon usually is used in ion-implanted transistors. In fact, if the channel area is exposed to the ion beam long enough, the substrate in the area can be turned into P-type silicon (while the body of the substrate still re- BA MOS Processes mains N-type) and the transistor becomes a depletion mode device. In any circuit some transistors can be made enhancement type, while others are depletion type, and the combination is a very useful circuit design tool. of the processes described so far, in that the source, drain, and channel all are N-type silicon, whereas the body of the substrate is P-type. Conduction in the N-Channel is by means of electrons, rather than holes. The Ion-implanted P-Channel Metal Gate process is very much in use toady. Among all the processes, it represents a good optimization between cost and performance and thus is the logical choice for many common circuits, such as memory devices, data handling (communication) circuits, and others. The main advantage of the N-Channel process is that the mobility of electrons is about three times greater than that of holes and, therefore, N-Channel transistors are faster than P-Channel . In addition, the increased mobility allows more current flow in a channel of any given size, and therefore N-Channel transistors can be made smaller. The positive gate voltage allows an N-Channel transistor to be completely compatible with TIL. Because of its low VT , it offers the designer a choice of using low power supply voltages to ,conserve power or increase supply voltages to get more driving power and thus increase speed. At low power levels it is more feasible to implement ciock generating and gating circuits on the chip. In most circuit designs only a single power supply voltage is required. N-CHANNEL PROCESS Historically, N-Channel process and its advantages were known well at the time when the first P-Channel devices were successfully manufactured; however, it was much more difficult to produce N-Channel. One of the main reasons was that the polarity of intrinsic charges in the materials combined in such a way that a transistor was on at OV and had a VT of only a few tenths of a volt (positive). Thus, the transistor operated as a marginal depletion mode device without a well-defined on/off biasing range. Attempts to raise VT by varying gate oxide thickness, increasing the substrate doping, and back biasing the substrate, created other objectionable results and it was not until research into materials, along with ion implantation, silicon gates, and other improvements came about that N-Channel became practical for high density circuits. The N-Channel process gained its strength only after the P-Channel process, ion implantation, and silicon gate all were already well developed. N-Channel went into volume productions with advent of the 4K dynamic RAM and the microprocessor, both of which required speed and high density. Because P-Channel processes were nearing their limits in both of these respects, N-Channel became the logical answer. The N-Channel process is structurally different from any Although metal gate N-Channel processes have been used, the predominant N-Channel process is a silicon gate process. Among the advantages of silicon gate is the possibility of a buried layer of interconnect lines, in addition to the normal aluminum interconnections deposited on the surface of the chip. This gives the circuit designer more latitude in layout and often allows the reduction of the total chip size. Because the poly silicon gate electrode is deposited in a separate step, after the thick oxide layer is in place, the simultaneous deposition of additional poly silicon interconnect lines is only a matter of masking. These interconnect lines are buried by later steps, as shown in Figure B.3. Figure B.3. Crosssection of an N-Channel Silicon Gate MOS Transistor (a) TRANSISTOR READY FOR SOURCE AND DRAIN DIFFUSIONS P SUBSTRATE (b) FINISHED TRANSISTOR One minor limitation associated with the buried interconnect lines is their location. Because the source and drain diffusions are done after the polysilicon is deposited [see (a) of Figure B.3] the interconnect lines cannot be located over these diffusion regions. B.5 I MOS Processes A second advantage of a silicon gate is associated with the reduction of overlap between the gate and both the source and drain. This reduces the parasitic capacitance at each location and improves speed, as well as power consumption characteristics. Whereas in the metal gate process, the P region source and drain diffusion must be done prior to deposition of the gate electrode, in silicon gate process, the electrode is in place during diffusion, see (a) of Figure B.3. Therefore, no planned overlap for manufacturing tolerance purposes need exist and the gate is said to be self-aligned. The only overlap that occurs is due to the normal lateral extension of the source and drain regions during the diffusion process. The silicon-gate process produces devices that are more compact than metal gate, and are slightly faster because of the reduced gate' overlap capacitance. Because the basic silicon gate process is relatively simple, it is also economical. It is a versatile process that is used in memory devices and most any other circuit. N-Channel development continues at a vigorous pace, resulting in all kinds of process variations, production techniques and applications. The combination of high speed, TTL compatibility, low power requirements, and compactness have already made N-Chaimel the most widely used process. The cost of N-Channel has been coming down also. In addition to its use in large memory chips and microprocessors, N-Channel has become a good general purpose process for circuits in which compactness and high speed are important. transistor is biased on, the P-Channel is off, and the output is near ground potential. Conversely, when the input is at a logic 0 level, its negative voltage biases only the P-Channel transistor on and the output is near the drain voltage + VDD . In either case, only one of the two transistors is on at a time and thus, there is virtually no current flow and no power consumption. Only during the transition from one logic level to the other are both transistors on and current flow increases momentarily. Silicon Gate CMOS is also fast, approaching speeds of bipolar TTL circuits. On the other hand, the use of two transistors in every gate makes CMOS slightly more complex and costly, and requires more chip size. For these reasons, the original popularity of CMOS was in SSI logic elements and MSI circuits-logic gates, inverters, small shift registers, counters, etc. These CMOS devices consititute a logic family in the same way as TTL, ECL, and other bipolar circuits do; and in the areas of very low power consumption, high noise immunity, and simplicity of operation, are still widely accepted by discrete logic circuit designers. Low power CMOS circuits made the watch circuit possible and also have been used in space exploration, battery operated consumer products, and automotive control devices. As experience was gained with CMOS, tighter design rules and reduced device sizes have been implemented and now LSI circuits, such as 1K RAM memories and microprocessors, are being manufactured in volume. CMOS circuits can be operated on a single power supply voltage, which can be varied from + 2.5 to about + 15 volts, with a higher voltage giving more speed and higher noise immunity. CMOS The basic CMOS circuit is an inverter, which consists of two adjacent transistors-one an N-Channel, the other a P-Channel, as shown in Figure BA. The two are fabricated on the same substrate, which can be either N or P type. The first implementation of an inverting gate is a process that uses both n+ and p+ polysilicon. The basic structure is a first-generation approach to which a selective field-oxidation process has been added. (At American Microsystems, Inc., the selective field-oxidation process is used only to shrink existing designs down to 5-micrometer rules; it is not applied to new designs.) The CMOS inverter in Figure BA is fabricated on an N-type silicon substrate in which a P "tub" is diffused to form the body for the N-Channel transistor. All other steps, including the use of silicon gates and ion implantation, are much the same as for other processes. Figure B.5 shows the plan and section views of the threedevice gate portion. Because the PoWell in the top view spans both N-Channel devices, it is referred to as ubiquitous, and the process is called Ubiquitous PoWell. The main advantage of CMOS is extremely low power consumption. When the common input to both gate electrodes is at a logic 1 (a positive voltage) the N-Channel In this planar process, p+ guard rings are used to reduce surface leakage. Poly silicon cannot cross the rings, however, so that bridges must be built. Note the use of B.6 AMII~ MOS Processes p+ polysilicon in the P·Channel areas. The plan view shows the construction of the bridges linking p + to metal to n +. (Were the process to be used for a lowvoltage, first-generation application like a watch circuit, the guard rings would not be necessary and poly silicon could directly connect N -Channel and P-Channel devices; however, to ensure good ohmic contact from one type of polysilicon to another, polysilicon-diode contacts must be capped with metal.) This process provides a buried contact (n + polysilicon to n + diffusion) that can yield a circuit-density advantage. However, neither of the other two second-generation approaches provides buried contacts. Therefore, if a layout in this process is to be compatible with the others, the buried contact must be eliminated. Though there will be a penalty in real estate, the gain for custom applications is a, great increase in the number of available CMOS vendors. The n+-Only Polysilicon Aproach follow are variants of the n+-only, selective-field-oxide approach. One closely resembles the p+ n+ UbiquitousP-Well process, since it, too, has a Ubiquitous P-Well that is implanted before the field oxidation and thus runs under the field oxide. The other, called isolated PoWell, has separate wells for each N -Channel device that are implanted after field oxidation. Figure B.6 shows the section and plan views of the n+-only Ubiquitous-poWell approach used to build the gate of Figure B.4. This is the 5iJm process recommended by AMI and others for new, high-performance CMOS designs. The layout is simpler than with the n+/p+ poly silicon Ubiquitous-Well approach (there are no buried contacts and no polysilicon-diode contacts), and it occupies less area for the same line widths. Also, since the process permits implanting in the field region, no guard rings are required. Polysilicon can thus cross directly from P- to N-Channel device areas without the need for bridges or polysilicon-dioxide contacts. Both of the second-generation CMOS processes that Figure 8.4. Crossection and Schematic Diagram of a CMOS Inverter INPUT --(»o--- OUTPUT VDD OUTPUT B.7 AMII~ MOS Processes Figure B.S. n+/p+ Polysilicon Approach P·CHANNEl N·CHANNEl p+·POl YSILlCON·TO· P+ DIFFUSION BURIED CONTACT GUARD·RING JUMPER (n+ POLYSILICON L-_ _...... ( n+ I--~- p+ DFFUSION THE FIIST HlGH·PERFORMANCE COMPLEMENTARY ·MOS PLANAR PROCESS. ITS DRAWBACKS: TWO TYPES OF POLYSILICON ARE USED. AND THE UNAVAILABILITY OF fIELD IMPLANT DOPIIIIIllES FIELD THRESHOLD TO DEVICE THRESHOLOS. B.8 DIFFUSION MOS Processes Figure B.6. n+-Only Polysilicon Approach P·CHANNEL N·CHANNEL IMPLANTED FIELD ALUMINUM) n- .+ METAL PO"."'.. \ /'+ ~--~---------+--~~------------~ ALL NEW HIGH·PERFORMANCE CMDS CIRCUITS WILL USE ONE TYPE OF POL YSILICON. THIS VERSION HAS A UBIQUITOUS P·WELL: THAT IS, SERIES N·CHANNEL DEVICES sir IN A COMMON P·WELL, WHICH, IMPLANTED BEFORE FIELD OXIDATION, RUNS UNDER THE FIELD OXIDE. THIS IS AMI'S PREFERRED CMOS PRO· CESS FORMAT FOR ALL NEW DESIGNS. B.9 POLYS. ." AMII~ MOS Processes Figure B.7. Isolated Wells. P·CHANNEL N·CHANNEL ALUMINUM~ "+ "".",,, \ P·WELL CONNECTION n+ POL YSILICON r---~--------~----1-~--------~ ~n+ p+",,,.., ) DIFFUSION THE THIRD CMOS APPROACH ISOLATES ALL N·CHANNEL DEVICES IN SEPARATE P·WELLS. SINCE THE ISOLATED WELLS MUST BE DOPED MUCH MORE HEAVILY THAN THOSE OF THE UBIQUITOUS· WELL APPROACH, n+·TO P·WELL CAPACITANCE IS GREATER AND SWITCHING SPEEDS LOWER. THIS IS AN n+·ONL Y POL YSILICON PROCESS. B.IO MOS Processes A variant of the all n + (See Figure B. 7) poly silicon process just discussed uses basically the selective field-oxide approach except that the PoWells are not continuous under the field-oxide areas; they are instead bounded by field-oxide edges. Since the PoWells are naturally isolated from one another, the process is called n+ poly-isolated P-Well. The isolated wells must all be connected to ground; if they are left floating, circuit malfunctions are bound to occur. The grounding is done either with p+ diffusions or with top-side metalization that covers a p+-toP-Well contact diffusion. Although currently available from AMI and other manufacturers, the Isolated-Well process is in fact not recommended for new designs by AMI. Its layout takes up more area than does one using the Ubiquitous-Well approach, even though its PoWell to p+-area spacing is slightly less. Table 1. Layout Compatibility Concerns for CMOS Processes LA YOUT FEATURE In the Isolated-Well process, the PoWells must be doped much more heavily than in the Ubiquitos-Well process. One result is a higher junction capacitance between the n + areas and the wells that both slows switching speeds and raises the power dissipation of a device. Even though the speed loss could be compensated for by slightly shorter channel lengths, the operating power still remains high. BURIED CONTACT n+/p+ POLY·SILICON UBIQUITOUS P·WELL n+·ONLY POLYSILICON UBIQUITOUS P·WELL n+·ONLY POLY SILICON ISOLATED P·WELL X NO NO POLYSILICON DIODE CONTACT YES X X P·WELL ISOLATION WITH DIFFUSION MASK NO NO YES TIGHT P·WELL·TO· p+ SPACING NO NO YES LAYOUT CARE REQUIRED FOR P'WELL ELECTRICAL CONTACTS NO NO YES x = DOES NOT MATTER Figure B.8. Comparative Data on Major MOS Processes MASKS REQUIRED I - PMETAL GATE HI V, 1000- I - P METAL GATE HI V, 1000- 1000 - f- f- P METAL GATE HI V, I-PSi·GATE t-PSi·GATE I-NSi·GATE t- NSi·GATE LO V, t:~ ~iEmEGATE LO v, , - N Si·GATE LO V, f- PION IMPLANT 100- t- PSi·GATE f- PION IMPLANT I- 100- CMOS LINEAR PROCESS CMOS, N·CHANNEL 4 V, PROCESS - f- N·CHANNEL SI·GATE (DEPLETION LOAD) - I- ~·CHANNEL SI·GATE LO V, - f- N·CHANNEL Si·GATE - t- P·CHANNEL METAL GATE LO V, -I- P·CHANNEL METAL GATE HI V, P METAL GATELO V, I - P METAL GATE LO V, I - P ION IMPLANT - f- f- f- N Si·GATE LO V, t-N Si·GATE t-N Si·GATEOEP LO t-N Si·GATE OEP LD, VMOS 10010- 1- 10- t-CMOS t - CMOS (PLANAR) 1- I-CMOS I-N Si·GATE OEP LO 0RELATIVE SPEED POWER PRODUCT (NS·MW) 0RELATIVE POWER (AT FIXED SPEED) 10- t- CMOS (SELECTIVE FOX) RELATIVE PROPAGATION DELAY B.ll RELATIVE COST PER LOGIC FUNCTION I Product Assurance Program INTRODUCTION Quality is one of the most used, least understood, and variously defined assets of the semiconductor industry. At AMI we have always known just how important effective quality assurance, quality control, and reliability monitoring are in the ability to deliver a repeatably reliable product. Particularly, through the manufacture of custom MOS!LSI, experience has proved that one of the most important tasks of quality assurance is the effective control and monitoring of manufacturing processes. Such control and monitoring has a twofold purpose: to assure a consistently good product, and to assure that the product can be manufactured at a later date with the same degree of reliability. To effectively achieve these objectives, AMI has developed a Product Assurance Program consisting of three major functions: o Quality Control o Quality Assurance o Reliability Each function has a different area of concern, but all share the responsibility for a reliable product. The AMI Product Assurance Program The program is based on MIL-STD-883, MIL-M-3851O, and MIL-Q-9858A methods. Under this program, AMI manufactures highest quality MOS devices for all segments of the commercial and industrial market and, under special adaptations of the basic program, also manufactures high reliability devices to full military specifications for specific customers. The three aspects of the AMI Product Assurance Program -Quality Control, Quality Assurance, and Reliability- have been developed as a result of many years of experience in MOS device design and manufacture. Quality Control establishes that every method meets or fails to meet, processing or production standards - QC checks methods. AMI circuits, and AMI circuits have also been utilized in the Viking and Vinson programs, as well as many other military airborne and reconnaissance hardware programs. QUALITY CONTROL The Quality Control function in AMI's Product Assurance Program involves constant monitoring of all aspects of materials and production, starting with the raw materials purchased, through all processing steps, to device shipment. There are three major areas of Quality Control: o o o Incoming Materials Control All purchased materials, including raw silicon, are checked carefully to various test and sampling plans. The purpose of incoming materials inspection is to ensure that all items required for the production of AMI MOS circuits meet such standards as are required for the production of high quality, high reliability devices. Incoming inspection is performed to specifications agreed to by suppliers of all materials. The Quality Control group continuously analyzes supplier performance, performs comparative analysis of different suppliers, and qualifies the suppliers. Tests are performed on all direct material, including packages, wire, lids, eutectics, and lead frames. These tests are performed using a basic sampling plan in accordance with MIL-S-19500, generally to a Lot Tolerance Percent Defective (LTPD) level of 10%. The AQL must be below 1 % overall. Two incoming material inspection sequences illustrate the thoroughness of AMI Quality Control: o Purchased packages are first inspected visually. Then, dimensional inspections are performed, followed by a full functional inspection, which subjects the packages to an entire production run simulation. Finally, a full electrical evaluation is made, including checks of the insulation, resistance, and lead-to-lead isolation. A package lot which passes these tests to an acceptable LTPD level is accepted. Quality Assurance establishes that every method meets, or fails to meet, product parameters-QA checks results. Reliability establishes that QA and QC are effective-Reliability checks device performance. One indication that the AMI Product Assurance Program has been effective is that NASA has endorsed AMI products for flight quality hardware since 1967. The Lunar Landers and Mars Landers all have incorporated Incoming Materials Control Microlithography Control Process!Assembly Control o Raw silicon must also pass visual and dimensional B.12 checks. In addition, a preferential etch quality inspection is performed. For this inspection, the underlayers AMII~ Product Assurance Program of bulk silicon are examined for potential anomalies such as dislocation, slippage or etch pits. Resistivity of the silicon is also tested. Microlithography Control Microlithography involves the processes which result in finished working plates, used for the fabrication of wafers. These processes are pattern or artwork generation, photo-reduction, and the actual printing of the working plates. Pattern generation now is the most common practice at AMI. The circuit layout is digitized and stored on a tape, which then is read into an automated pattern generator which prints a highly accurate lOx reticle directly. In cases where the more traditional method of artwork generation is used whether Rubylith, Gerber Plots, AMI generated or customer generated-the artwork is throughly inspected. It is checked for level-to-Ievel registration and dimensional tolerances. Also, a close visual inspection of the workmanship is made. AMI artwork is usually produced at 200x magnification and must conform to stringent design rules, which have been developed over a period of years as part of the process control requirements. Acceptable artwork is photographically reduced to a 20x magnification, and then further to a lOx magnification. The resulting lOx reticles are then used for producing Ix masters. The masters undergo severe registration comparisons to a registration master and all dimensions are checked to insure that reductions have been precise. During this step, image and geometry are scrutinized for missing or faded portions and other possible photographic omissions. For a typical N-Channel silicon gate device, master sets are checked at all six geometry levels in various combinations against each other and against a proven master set. Allowable deviations within the die are limited to 0.5 micron, deviations within a plate are limited to 1 micron, and all plate deviations are considered cumulatively~ Upon successful completion of a device master set, it is released to manufacturing where the Ix plates are printed. A sample inspection is performed by manufacturing on each 30-plate lot and the entire lot is returned to Quality Control for final acceptance. Quality Control performs audits on each manufacturing inspector daily, by sample inspection techniques. The plates can be rejected first by manufacturing, when the 30-plate lots are inspected, or by Quality Control when the lots are submitted for final acceptance. If either group rejects the plates, they are rescreened and then undergo the same inspection sequence. In the rescreening process, the plates undergo registration checks; visual checks for pin holes, protrusions, and faded or missing images, as well as all critical dimension checks. Process Control Once device production has started in manufacturing, AMI Quality Control becomes involved in one of the most important aspects of the Product Assurance Program - the analysis and monitoring of virtually all production processes, equipment, and devices. Process controls are performed in the fabrication area, by the Quality Control Fabrication Group, to assure adherence to specifications. This involves checks on operators, equipment and environment. Operators are tested for familiarity with equipment and adherence to procedure. Equipment is closely checked both through calibration and maintenance audits. Environmental control involves close monitoring of temperature, relative humidity, water resistivity and bacteria content, as well as particle content in ambient air. All parameters are accurately controlled to minimize the possiblity of contamination or adverse effects due to temperature or humidity excesses. Experience has proven that such close control of the operators, equipment, and environment is highly effective towards improved quality and increased yields. In addition to the specification adherence activities of the QC Fabrication Group, a QC Laboratory performs constant process monitoring of virtually .every step of all processes. Specimens are taken from all production steps and critically evaluated. Sampling frequency varies, depending on the process, but generally, oxidation, diffusion, masking, and evaporization are the most closely monitored steps. Results are supplied both to manufacturing and engineering. When evidence of a problem occurs, QC provides recommendations for corrections and follows up the corrective action taken. Optical Inspections are performed at several steps; quality control limits are based on a 10% LTPD. The chart in Figure 1 shows process steps and process control points. B.13 AMII~ Product Assurance Program mance with customer specifications or other AMI specifications. Figure 1. Flowchart of Product Assurance Program Implementation After devices undergo 100% testing in manufacturing, they are sent to Quality Assurance for acceptance. Lots are defined, and using the product specifications, sample sizes are determined, along with the types of tests to be performed and the test equipment to be used. Lots must pass QA testing either with an LTPD of 10%, or less, if the specification requires tighter limits. Lots with quantities greater than 2000 are checked to a 1% AQL. ......- - OC INSPECTION PHOTO SUPPORT OC INSPECT10N OC FAB INSPECTlON ......- - O C LAB MONITORS 1 + - - - OC INSPECTION ASSEMBLY SCRIBE/BREAK 1ST OPTICAL DIE ATTACH BOND 2ND ......_ _ _SEAL ---1 OPTICAL Three types of tests are performed on the samples: visuaUmechanical, parametric, and functional. All tests are performed both at room temperature and at elevated temperature. In addition, a number of other special temperature tests may be performed if required by the specification. Generally, high temperature tests are at 125°C. l~K."'-' ......- - OC INSPECTION To perform the tests, QA uses AMI PAFT test systems, ROM test systems, Macrodata testers, Fairchild Sentry, Sentinel, XINCOM systems, Teradyne test systems,and various bench test units. In special instances a part may also be tested in a real life environment in the equipment which is to finally utilize it. 1 + - - - MANUFACTURING OA ACCEPTANCE PROGRAM VERIFICATION VISUAL/MECHANICAL TESTING FUNCTIONAL TESTING PARAMETRIC TESTING TEMPERATURE TESTING If a lot is rejected during QA testing, it is returned to the production source for an electrical rescreening. It is then returned to QA for acceptance but is identified as a resubmitted lot. If it fails again, corrective action in engineering is initiated. As evidence of the problem is detected, the parts may also be traced all the way back to the wafer run to analyze the cause. When a lot is acceptable, it is sent to packaging and then to finished goods. When parts leave finished goods, they are again checked by the QA group to a 10% LTPD with visuaUmechanical tests. Also, all supporting documentation for the parts is verified, including QA acceptance, special customer specifications, certificates of compliance, etc. Only after this last check are devices considered ready for plant clearance. ......- - O A INSPECTlON I - . . - - O A INSPECTION Sill' QUALITY ASSURANCE The Quality Assurance function in the Product Assurance Program involves checking the ability of manufactured parts to meet specifications. In addition, the QA group also is responsible for calibration of all equipment, and for the maintenance of AMI internal product specifications, to assure that they are always in confor- If there are customer returns, they are first sample tested by QA to determine the cause of the return. (Many times an invalid customer test will incorrectly cause returns.) Selected return samples are sent to Reliability for failure analysis. RELIABILITY The Reliability function in the Product Assurance Program involves process qualification, device qualification, B.14 Product Assurance Program o A large P-N junction area (identical to the junction area above, but without the MOS capacitor) o A large area MOS capacitor over substrate o Several long contact strings with different contact geometries D Several long conductor geometries, which cross a series of eight deeply etched areas package qualification, reliability program qualification and failure analysis. To perform these functions AMI Reliability group is organized into two major areas: o Reliability Laboratory D Failure Analysis Reliability Laboratory AMI Reliability Laboratory is responsible for the following functions. o New Process Qualification o Process Change Qualification o Process Monitoring o o New Device Qualification Device Change Qualification D New Package Qualification o Device Monitoring D Package Change Qualification o Package Monitoring o High Reliability Programs There are various closely interrelated and interactive phases involved in the development of a new process, device, package or reliability program. A process change may affect device performance, a device change may affect process repeatability, and a package change may affect both device performance and process repeatability. To be effective. the Reliability Laboratory must monitor and analyze all aspects of new or changed processes, devices, and packages. It must be determined what the final effect is on product reliability, and then evaluate the merits of the innovation or change. Process Qualification For example, AMI Research and Development group recommends a new process or process alteration when it feels that the change can result in product improvement. The Reliability Laboratory then performs appropriate environmental and electrical evaluations of a new process. Typically, a special test vehicle, or "reI chip", generated by R&D during process development, is used to qualify the recommended new process or process change. Each circuit element of a reI chip allows a specific test to be performed. As an example, the discrete inverter and MOS load device accommodate power life tests. As a consequence, any type of parameter drift can be observed. The MOS capacitor, covering the large P-N junction, can serve to indicate the presence of contamination in the oxide, under the oxide, or in the bulk silicon. If unusual drift is evidenced, the location of contamination can be determined through analysis of the additional MOS capacitor and the large P-N junction area. The metal conductor interconnecting contacts is useful for life testing under relatively high current conditions. It facilitates the detection of metal separation when moisture or other contaminants are present. The conductors crossing deeply etched areas allow the checking of process control. Rather than depending upon optical inspection of metal quality, burned out areas caused by high currents are readily identified and provide a quantitative measure of metal quality. If the Reliability Laboratory determines that a recommended new process or process change is viable for manufacturing purposes, further analysis is necessary to determine that production devices can be manufactured in high volume, in a repeatable and reliable manner. Process Monitoring In addition to process qualification, the Reliability group also conducts ongoing process monitoring programs. Once every 90 days each major production process is evaluated using reI chips as test vehicles. The resulting test data is analyzed for parameter limits and process stability. In this manner AMI can help assure repeatability and high product quality. The reI chip is composed of circuit elements similar to Package Qualification those that may be required under worst-case circuit design conditions. The reI chip elements are standard for New packages are also qualified before they are adopted. any given process, and thus allow precise comparisons To analyze packages, a qualification matrix is designed, between diffusion runs. The following is an example of according to which the new package and an established what is included on a typical reI chip: package (used for control) are tested concurrently. The o A discrete inverter and an MOS capacitor test matrix consists of a full spectrum of electrical and o A large P-N junction covered by an MOS environmental stress tests, in accordance with MILSTD-883. capacitor. B.15 Product Assurance Program Failure Analysis results of the analysis are returned in the form of a written report. Another important function of the Reliability group is failure analysis. Scanning electron microscopes, high power optical microscopes, diagnostic probe stations, and other equipment is used in failure analysis of devices submitted from various sources. It is the function of the Reliability group to determine the cause of failure and recommend corrective action. The Reliability group provides a failure analysis service for the previously mentioned in-house programs and for the evaluation of customer returns. All AMI customers are provided a failure analysis service for any part that fails within one year from date of purchase and the SUMMARY The Product Assurance Program at AMI is oriented towards process control and monitoring, and the evaluation of devices. The Program consists of three maj or functions: Quality Control, Quality Assurance, and Reliability. Constant monitoring of all phases of production, with information feedback at all levels, allows fast and efficient detection of problems, evaluation and analysis, correction, and verification of the correction. The overall result is a line of products which are highly repeatable and reliabile, with a very low reject level. B.16 AMII. AMI Military Products Screening Program Aerospace and defense equipments generally require LSI microcircuits capable of superior product reliability and performance. To meet these needs, AMI offers three standard screening options patterned after MIL-STD-883, Method 5004. Please note that two Class B flows are available: o o One per Method 5004.5, the current official revision. This Class B level requires temperature extreme electrical testing on both a 100% and on a Group A sampling basis. A more economical Class B flow patterned after a much earlier and officially obsolete revision ... Method "5004.0". Temperature extreme electrical testing is performed only on a Group A sampling basis. Operation/M~L-STD-883 Test Method Internal Visuall2010 Final Seal Stabilization Bakell008 Temperature Cycle/1010, 10 Cycles Constant Accelerationl2001 (1) Seal Testll014 -Fine Leak -Gross Leak Pre-bum-in Electrical Test Burn-inlI015(3) Final Electrical Test/5004(4) -Static Tests, 25°C - Static Tests, Maximum Rated Operating Temperature - Static Tests, Minimum Rated Operating Temperature -Switching Tests, 25°C -Functional Tests, 25°C Group A Electricals/5005 -55°C, 25°C, 125°C Class B Method 5004.5 MIL-STD-883 Class B Method 5004.0 MIL-STD-883 Class C Method 5004.5 MIL-STD-883 Cond.B 100% Condo C, 24 Hrs Cond.B 100% Condo C, 24 Hrs Cond.B Cond.C Cond.C Cond.C Y1 Axis Y1 Axis 100% Condo C, 24 Hrs Y1 Axis Condo A or B Condo C @AMI Option(2) Condo A or B Cond.C @AMI Option(2) Condo A or B Cond.C / - 125°C Min, 160 Hrs. 125°C Min, 160 Hrs. - 100% 100% 100% 100% - - 100% - - 100% 100% Sample(5) Table I 100% 100% Sample(5) Table I 100% Sample(5) Table I - Notes: (1) Stress level (g) applied is dependent on package size/lead count. (2) Per paragraph 3.5.1 of MIL-STD-883, Method 5004. (3) Per MIL-STD-883, Method 1015 and Method 5004, paragraph 3.4.2, accelerated testing (Test Condition F of Method 1015) may be used at AMI's option. (4) Final test electrical measurements per the applicable AMI data sheet. (5) Group A is performed on each lot. B.17 AMII~ Packaging PLASTIC PACKAGE The AMI plastic dual-in-line package is the equivalent of the widely accepted industry standard, refined by AMI for MOS/LSI applications. The package consists of a plastic body, transfer-molded directly onto the assembled lead frame and die. The lead frame is Kovar or Alloy 42, with external pins tin plated. Internally, there is a 50JAin. gold spot on the die attach pad and on each bonding fingertip. Gold bonding wire is attached with the thermocompression gold ball bonding technique. Materials of the lead frame, the package body, and the die attach are all closely matched in thermal expansion coefficients, to provide optimum response to various thermal conditions. During manufacture every step of the process is rigorously monitored to assure maximum quality of the AMI plastic package. Available in: 8, 14, 16, 18, 22, 24, 28, 40 and 64 pin configurations. Cerdip PACKAGE The Cerdip dual-in-line package has the same high performance characteristics as the standard three-layer ceramic package yet is a cost-effective alternative. It is a military approved type package with excellent reliability characteristics. The package consists of an Alumina (AI2 0 3 ) base and the same material lid, hermetically fused onto the base with low temperature solder glass. Inert gasses are sealed inside the die cavity. Available in 14,16,18,22,24,28 and 40 pin configurations. B.18 AMII~ Packaging CERAMIC PACKAGE Industry standard high performance, high reliability package, made of three layers of Al2 0 s ceramic and nickel-plated refractory metal. Either a low temperature glass sealed ceramic lid or a gold tin eutectic sealer Kovar lid is used to form the hermetic cavity of this package. Package leads are available with gold over nickel or tin plating for socket insertion or soldering. N, PLATING REFRACTORY METALLIZATION Available in 14,16,18,22,24,28,40 and 64 pin configurations. 14-Pin Plastic 8-Pin Plastic PIN 1 IDENTIFIER PIN 1 IDENTIFIER)] '065 ~ 0.100 TYP -: 0.020 0.Q15~ .---- o .090 MINJ~-=lo 0020MIN . ~ 1 0.040 I_ I- 14 I 0.400 MAX I I : '--------1 4 0.020 0.015 t=JlJ . 200 MAX UO.2BO 0.220 0.310---r---1BEND 0.290 11\1 0.090 MIN ~R~ b W MAX-J L JI 0020 MIN . I I ~ 7 0.200 MAX U 8 0.2BO 0.220 BENDDo.310 Q~ \ ,R'11\ 0.012 '---0.008 /1 15°MAX 0.012 '-/ I--- -ll--O.OOB TYP 16-Pin Plastic 14-Pin Ceramic _f-°. 280 1 9Q']"'"r 0.795 MAX 0.070 0.030 16 1 PIN 1 IDENTIFIER -..I- 0.310 ,I 0.290 B.19 AMII~ Packaging 16-Pin Ceramic 16-Pin Cerdip PIN 1 IDENTIFIER PIN 1 IDENTIFIER ! :ff' ::;: m 1 16 ~,,~jFo~." 0' ·LJ- :ll: 0000 I 0.015MIN 0.310 0. 290 I--- -UO.295 0.275 BEND BEND 'A 15°MAX ~ ~ t t 0.310 II 11 0.290 ,~\ t /1 MARKINGS ON LID SURFACE ONLY 16 JL 0.012 O.OOB 15° 18-Pin Plastic MAX~'~" Jl' 0.012 0.008 18-Pin Ceramic PIN 1 IDENTIFIER PIN 1 IDENTIFIER- 18 lB MARKINGS ON LID SURFACE ONLY ~.~~~ TYP ~ 0.090 ~IN 10 U ~~~~ JJE:0.200 MAX II-- 0020 . MIN BEND 1-l r--l I +---1- 0,.310 I I 0.290 ,R, '"OM',}L--1111\ I A, 15' MAX 0.'" 0.008 18-Pin Cerdip PIN 1 IDENTIFIER 18 0.020 0.D15 9 10 l 11 0 . 0 9 0 : - J J H o .200 MAX I/-- 0020 MIN ' I 0.295 ~~~ BENDO'O'310 0.290 ~ 150MA~:l , / I I JLo.012 0.008 B.20 I 7 I-- -II- 22-Pin Plastic PIN 1 IDENTIFIER L_ 0 310 . 0,290 0.012 OOOB Packaging 22-Pin Cerdip 22-Pin Ceramic PIN 1 IDENTIFIER PIN 1 IDENTIFIER ~:IH·::::1"JJ 'F MARKINGS .~ sS~FL~gE ONLY 0.020 0,015 t~J-JJI 11 0.090 MIN 0.200 MAX O.015MIN 'IJ I-- g:~;~ , r BENDf,o.4tO---1 I-- I 0.390 r-=:J ~ I AE3~~ I 15"MAX / "i JL r--- I /~ "I g~~ 15"MAX. JLo.012 0.008 24-Pin Cerdip 24-Pin Plastic I~ 24 Ii 1.270 MAX 0.06. 51 0.040 g~~1~310MAX 0020 0015 0.090 MIN-I ~ U 0090:-JJ}~~0200MAX 0.200 MAX --11--00020 MIN 0015MIN I I-- 12 13 LO.590J 0.480 BENDio.61Oi 0 590 11 -,1 . AE3~~ 150MAX~ [ I- 28-Pin Plastic 24-Pin Ceramic PIN 1 IDENTIFIER 24 MARKINGS ON LID SURFACE ONLY f--0.61O Ir --j 0.590 - , I ,.."!~F9L'J~ 0.012 0.008 B.21 JLO.012 O.OOB Packaging 28~Pin 28-Pin Cerdip PIN 1 IDENTIFIER Ceramic PIN 1 100NTIAER 28 iO.61O·iBEND Ii I 0.590 --, jiE3~, 150MA~ I-I ILo.012 0.008 --j 40-Pin Plastic 40-Pin Ceramic PIN 1 IDENTIFIER PIN 1 IDENTIFIER , \ 40 40 I I 0.065 , 0.040 MARKINGS ON LID D 2.060.MAX i ~ SURFACE ONLY I _-.1 , 0.020-, : 0.015~ ~--....- '-II 21 0.090 MI N J -, I I +-.~ iL-L0.200 MAX ~-~.~~~ J 1-I 0020MINJL . 21 - ~.610~ 0.590 1r==J 0 15 MAX ..., B.22 ~ ~ ! 0.012 1--0.008 L J: AMII~ Packaging 64-Pin Ceramic 40-Pin Cerdip 1~90MIN. 1 --I .020 MIN. PIN SPACING 0.100 T.P (SeeNo'eAlL 3.400 MAX _.200 MAX NOHA EacllpincenterhneisiocatellWlIhm0010cfltsirueiongl1udinaiPO$ltUln 64-Pin Plastic 3.300 MAX MOMIN. _I ~ Ill- ."oMAx·_1 1 ..... 1 1-·770-.830~1 I 020MlN 1_ 1_·890-.910_IBENOLINE F=1 L ~I ~\\_.008_.012 15° MAX B.23 r·82o .. 88o ----I AMII~ Ordering Information Standard Products: Any product in this MOS Products Catalog can be ordered using the simple system described below. With this system it is possible to completely specify any standard device in this catalog in a manner that is compatible with AMI's order processing methods. The example below shows how this ordering system works and will help you to order your parts in a manner that can be expedited rapidly and accurately. All orders (except those in sample quantities) are normally shipped in plastic carriers or aluminum tube containers, which protect the devices from static elec- tricity damage under all normal handling conditions. Either container is compatible with standard automatic IC handling equipment. Any device described in this catalog is an AMI Standard Product. However, ROM devices that require mask preparation or programming to the requirements of a particular user, devices that must be tested to other than AMI Quality Assurance standard procedures, or other devices requiring special masks are sold on a negotiated price basis. ~?2@@® =~ ~?2@@®~ =~ ~@®@@ =[Q) ~@®[}{]©© =[Q) ~@~©~D® =~ ~~@~~© =~ ~--------~--------~/~ ~ Device Number - prefix S, followed by four (or five*) numeric digits that define the basic device type. Versions to the basic device are indicated by an additional alpha or numeric digit as shown in the above examples. Package Type - a single letter designation which identifies the basic package type. The letters are coded as follows: P - Plastic package *Organ Circuits D - Cerdip package C - Ceramic (three-layer) package Microprocessor/Microcomputer Development Support: Custom Circuits: Consult your local sales office. Consult your local sales office. B.24 Ordering Information Military Products: Examples Parts Numbering Format x X X MBC 6802 MEC 5101L-l LBC 68AOO MBLUA·3 L NNNNN Four to seven alpha numerics specifying the basic part number (die type) and including a power/speed selection as applicable. For example, 6802 indicates an 8-bit microprocessor with clock and RAM; 5101L-l specifies a CMOS 256X4 static RAM with 0.055mW maximum standby power and 450ns maximum access time; and UA-3, a 540 gate CMOS uncommitted logic array. Designates the package and utilizes one of the following letters regardless of the number of leads: C - Ceramic dual in-line D - Cerdip L - Leadless chip carrier, ceramic, 50 mil pin spacing Designates the screening level: B - Class B, MIL-STD-883, Method 5004.5 C - Class C, MIL-STD-883, Method 5004.5 E - Class B, patterned after MIL-STD-883, Method "5004.0" Designates the operating temperature range and utilizes one of the letters M or L. Definitions: M-Full military temperature range, -55°C to + 125°C L -Limited military temperature range, -55°C to +85°C Ordering Information Please specify part numbers in accordance with the parts numbering format above. B.25 AMII~ 1. 2. 3. ACCEPTANCE: THE TERMS OF SALE CONTAINED HEREIN APPLY TO ALL QUOTATIONS MADE AND PURCHASE ORDERS ENTERED INTO BY THE SELLER. SOME OF THE TERMS SET OUT HERE MAY DIFFER FROM THOSE IN BUYER'S PURCHASE ORDER AND SOME MAY BE NEW. THIS ACCEPTANCE IS CONDITIONAL ON BUYER'S ASSENT TO THE TERMS SET OUT HERE IN LIEU OF THOSE IN BUYER'S PURCHASE ORDER. SELLER'S FAILURE TO OBJECT TO PROVISIONS CONTAINED IN ANY COMMUNICATION FROM BUYER SHALL NOT BE DEEMED A WAIVER OF THE PROVISIONS OF THIS ACCEPTANCE. ANY CHANGES IN THE TERMS CONTAINED HEREIN MUST SPECIFICALLY BE AGREED TO IN WRITING BY AN OFFICER OF THE SELLER BEFORE BECOMING BIND· ING ON EITHER THE SELLER OR THE BUYER. All orders or contracts must be approved and accepted by the Seller at its home office. These terms shall be applicable whether or not they are attached to or enclosed with the products to be sold or sold hereunder. Prices for the items described above and acknowledged hereby are firm and not subject to audit, price revision, or price redetermination. PAYMENT: (a) Unless otherwise agreed, all invoices are due and payable thirty (30) days from date of invoice. No discounts are authorized. Shipments, deliveries, and performance of work shall at all times be subject to the approval of the Seller's credit department and the Seller may at any time decline to make any shipments or deliveries or perform any work except upon receipt of payment or upon terms and conditions or security satisfactory to such department. (b) If, in the judgment of the Seller, the financial condition of the Buyer at any time does not justify continuation of production or shipment on the terms of payment originally specified, the Seller may require full or partial payment in advance and, in the event of the bankruptcy or insolvency of the Buyer or in the event any proceeding is brought by or against the Buyer under the bankruptcy or insolvency laws, the Seller shall be entitled to cancel any order then outstanding and shall receive reimbursement for its cancellation charges. (c) Each sh ipment shall be considered a separate and independent transaction, and payment therefor shall be made accordingly_ If shipments are delayed by the Buyer, payments shall become due on the date when the Seller is prepared to make shipment. If the work covered by the purchase order is delayed by the Buyer, payments shall be made based on the purchase price and the percentage of completion. Products held for the Buyer shall be at the risk and expense of the Buyer. TAXES: Unless otherwise provided herein, the amount of any present or future sales, revenue, excise or other taxes, fees, or other charges of any nature, imposed by any public authority, (national, state, local or other) applicable to the products covered by this order, or the manufacturer or sale thereof, shall be added to the purchase price and shall be paid by the Buyer, or in lieu thereof, the Buyer shall provide the Seller with a tax exemption certificate acceptable to the taxing authority. 4. F.O.B. POINT: All sales are made F.O.B. point of shipment. Seller's title passes to Buyer, and Seller's liability as to delivery ceases upon making delivery of material purchased hereunder to carrier at shipping point, the carrier acting as Buyer's agent. All claims for damages must be filed with the carrier. Shipments will normally be made by Parcel Post, Railway Express, Air Express, or Air Freight. Unless specific instructions from Buyer specify which of the foregoing methods of shipment is to be used, the Seller will exercise his own discretion. 5. DELIVERY: Shipping dates are approximate and are based upon prompt receipt from Buyer of all necessarv information. In no event will Seller be liable for anv re-procurement costs, nor for delay or non-delivery, due to causes beyond its reasonable control including, but not limited to, ~cts of God, acts of civil or military authority, priorities, fires, strikes, lock-outs, slow-downs, shortages, factory or labor conditions, errors in manufacture, and inability due to causes beyond the Seller's reasonable control to obtain necessary labor, materials, or manufacturing facilities_ In the event of any such delay, the date of delivery shall, at the request of the Seller, be deferred for a period equal to the time lost by reason of the delay. In the event Seller's production is curtailed for any of the above reasons so that Seller cannot deliver the full amount released hereunder, Seller may allocate production deliveries among its various customers then under contract for similar goods. The allocation will be made in a commercially fair and reasonable manner. When allocation has been made, Buyer will be notified of the estimated quota made available. 6. Terms of Sale PROVISION IS STATED IN LIEU OF ANY OTHER EXPRESSED, IMPLIED, OR STATUTORY WARRANTY AGAINST INFRINGEMENT AND SHALL BE THE SOLE AND EXCLUSIVE REMEDY FOR PATENT INFRINGEMENT OF ANY KIND. 7. INSPECTION: Unless otherwise specified and agreed upon, the material to be furnished under this order shall be subject to the Seller's standard inspection at the place of manufacture. If it has been agreed upon and specified in this order that Buyer is to inspect or provide for inspection at place of manufacture such inspection shall be so conducted as to not interfere unreasonably with Seller's operations and consequent approval or rejection shall be made before shipment of the material. Notwithstanding the foregoing, if, upon receipt of such material by Buyer, the same shall appear not to conform to the contract, the Buyer shall immediately notify the Seller of such conditions and afford the Seller a reasonable opportunity to inspect the material. No material shall be returned without Seller's consent. Seller's Return Material Authorization form must accompany such returned material. 8. WARRANTY: The Seller warrants that the products to be delivered under this purchase order will be free from defects in material and workmanship under normal use and service. Seller's obligations under this Warranty are limited to replacing or repairing or giving credit for, at its option, at its factory, any of said products which shall, within one (1) year after shipment, be returned to the Seller'S factory of origin, transportation charges prepaid, and which are, after examination, disclosed to the Seller's satisfaction to ~e thus defective. THIS WARRANTY IS EXPRESSED IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, STATUTORY, OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, AND OF ALL OTHER OBLIGATIONS OR LIABILITIES ON THE SELLER'S PART, AND IT NEITHER ASSUMES NOR AUTHORIZES ANY OTHER PERSON TO ASSUME FOR THE SELLER ANY OTHER LIABILITIES IN CONNECTION WITH THE SALE OF THE SAID ARTICLES_ This Warranty shall not apply to any of such products which shall have been repaired or altered, except by the Seller, or which shall have been subjected to misuse, negligence, or accident. The aforementioned provisions do not extend the original warranty period of any product which has either been repaired or replaced by Seller. It is understood that if this order calls for the delivery of semiconductor devices which are not finished and fully encapsulated, that no warranty, statutory, expressed or implied, including the implied warranty of merchantability and fitness for a particular purpose, shall apply. All such devices are sold as is where is. 9. GENERAL: The validity, performance and construction of these terms and all sales (a) hereunder shall be governed by the laws of the State of California. (b) The Seller represent~ that with respect to the production of articles andl or performance of the services covered by this order it will fully comply with all requirements of the Fair Labor Standards Act of 1938, as amended, WilliamsSteiger Occupational Safety and Health Act of 1970, Executive Orders 11375 and 11246, Section 202 and 204. (c) In no event shall Seller be liable for consequential or special damages_ (d) The Buyer may not unilaterally make changes in the drawings, designs or specifications for the items to be furnished hereunder without Seller's prior consent. (e) Except to the extent provided in Paragraph 10, below, this order is not subject to cancellation or termination for convenience. (f) Buyer acknowledges that all or part of the products purchased hereunder may be manufactured andlor assembled at any of Seller's facilities, domestic or foreign. (g) In the __ event that the cost of the products are increased as a result of increases in materials, labor costs, or duties, Seller may raise the price of the products to cover the cost increases. If Buyer is in breach of its obligations under this order, Buyer shall (h) remain liable for all unpaid charges and sums due to Seller and will reimburse Seller for all damages suffered or incurred by Seller as a result of Buyer's breach. The remedies provided herein shall be in addition to all other legal means and remedies available to Seller. 10. GOVERNMENT CONTRACT PROVISIONS: If Buyer's original purchase order indicates by contract number, that it is placed under a government contract, only the following provisions of the current Armed Services Procurement Regulation are applicable in accordance with the terms thereof, with an appropriate substitution of parties, as the case may be - i.e., "Contracting Officer" shall mean "Buyer", "Contractor" shall mean "Seller", and the term "Contract" shall mean th is order: PATENTS: The Buyer shall hold the Seller harmless against any expense or loss resulting from infringement of patents, trademarks, or unfair competition arising from compliance with Buyer's designs, specifications, or instructions. The sale of products by the Seller does not convey any license, by implication, estoppel or otherwise, under patent claims covering combinations of said products with other devices or elements .• 7-103_1, Definitions; 7-103.3, Extras; 7-103.4, Variation in Quantity; 7-103.8, Assignment of Claims; 7-103.9, Additional Bond Security; 7-103.13, Renegotiation; 7-103.15, Rhodesia and Certain Communist Areas; 7-103.16, Contract Work Hours and Safety Standards Act - Overtime Compensation; 7-103.17, Walsh-Healey Public Contracts Act; 7-103.18, Equal Opportunity Clause; 7-103.19, Officials Not to Benefit; 7-103.20, Covenant Against Contingent Fees; 7-103.21, Termination for Convenience of the Government (only to the extent that Buyer's contract is terminated for the convenience of the government); 7-103.22, Authorization and Consent; 7-103_23, Notice and Assistance Regarding Patent Infringement; 7-103.24, Responsibility for Inspection; 7-103.25, Commercial Bills of Lading Covering Shipments Under FOB Origin Contracts; 7-103.27, Listing of Employment Openings; 7-104.4, Notice to the Government of Labor Disputes; 7-104.11, Excess Profit; 7-104.15, Examination of Records by Comptroller General; 7-104.20, Utilization of Labor Surplus Area Concerns. Except as otherwise provided in the preceding paragraph, the Seller shall defend any suit or proceeding brought against the Buyer, so far as based on a claim that anv product, or any part thereof, furnished under this contract constitutes an infringement of any patent of the United States, if notified promptly in writing and given authority, information, and assistance (at the Seller'S expense) for defense of same, and the Seller shall pay all damages and costs awarded therein against the Buyer. In case said product, or any part thereof, is, in such suit, held to constitute infringement of patent, and the use of said product is enjoined, the Seller shall, at its own expense, either procure for the Buyer the right to continue using said product or part, replace same with non-infringing product, modify it so it becomes non-infringing, or remove said product .and refund the purchase price and the transportation and installation costs thereof. In no event shall Seller's total liability to the Buyer under or as a result of compliance with the provisions of this paragraph exceed the aggregate sum paid by the Buyer for the allegedly infringing product. The foregoing states the entire liability of the Seller for patent infringement by the said products or any part thereof. TH IS B.26 AMII~ Worldwide Sales Offices DOMESTIC WESTERN AREA 100 East Wardlow Rd., Suite 203 Long Beach, California 90807 Tel: (213) 595-4768 TWX: 910-341-7668 2960 Gordon A venue Santa Clara, California 95051 Tel: (408) 738-4151 TWX: 910-338-2022 20709 N.E. 232nd Avenue Battle Ground, Washington 98604 Tel: (216) 687-3101 CENTRAL AREA 500 Higgins Road, Suite 210 Elk Grove Village, Illinois 60007 Tel: (312) 437-6496 TWX: 910-222-2853 408 South 9th Street Suite Number 201 Noblesville, Indiana 46060 Tel: (317) 773-6330 TWX: 810-260-1753 3850 Second Street Suite Number 110 Wayne, Michigan 48184 Tel: (313) 7.29-1520 TWX: 810-242-2919 725 So. Central Expressway, Suite A-9, Richardson, Texas 75080 Tel: (214) 231-5721 (214) 231-5285 TWX: 910-867-4766 France EASTERN AREA 237 Whooping Loop Altamonte Springs, Florida 32701 Tel: (305) 830-8889 TWX: 810-853-0269 24 Muzzey St. Lexington, Massachusetts 02173 Tel: (617) 861-6530 20F Robert Pitt Drive, Suite 208 Monsey, New York 10952 Tel: (914) 352-5333 TWX: 710-577-2827 Axe Wood East Butler & Skippack Pikes, Suite 230 Ambler Pennsylvania 19002 Tel: (215) 643-0217 TWX: 510-661-3878 AMI Microsystems, S.A.R.L. 124 Avenue de Paris 94300 Vincennes, France Tel: (01) 374 00 90 TLX: 842-670500 Holland AMI Microsystems, Ltd. Calandstraat 62 Rotterdam, Holland Tel: 010-36 14 83 TLX: 844-27402 Italy AMI Microsystems, S.p.A. Via Pascoli 60 20133 Milano Tel: 29 37 45 or 2360154 TLX: 843 32644 Japan INTERNA TIONAl England AMI Microsystems, Ltd. Princes House, Princes St. Swindon, SN1 2HU Tel: (793) 37852 TLX: 851-449349 AMI Japan Ltd. 502 Nikko Sanno Building 2-5-3, Akasaka Minato-ku, Tokyo 107 Tel: Tokyo 586-8131 TLX: 781-242-2180 AMI J West Germany AMI Microsystems, GmbH Rosenheimer Strasse 30/32, Suite 237 8000 Munich 80, West Germany Tel: (89) 483081 TLX: 841-522743 Rapifax: (89) 486591 Domestic Representatives ALABAMA CANADA ILLINOIS Huntsville Rep, Inc. Tel: (205) 881-9270 TWX: 810-726-2101 Quebec Vitel Electronics Tel: 514-331-7393 TWX: 610-421-3124 Elk Grove Village Oasis Sales Tel: (312) 640-1850 TWX: 910-222-2170 ARIZONA COLORADO IOWA Phoenix Hecht, Henschen & Assoc., Inc. Tel: (602) 275-4411 TWX: 910-951-0635 Englewood R2Marketing Tel: (303) 771-7580 Parker R2Marketing Tel: (303) 841-5822 Cedar Rapids Comstrand, Inc. Tel: (319) 377-1575 CALIFORNIA Los Angeles Ed Landa Co. Tel: (213) 879-0770 TWX: 910-342·6343 Mt. View (,c,,), Thresum Associates, Inc .. G\ 0 Ir(f, \{.'5 \ Tel: (415)965-9180 /-h;,~ \ \,,) .I, TWX: 910-379-6617 - n; v San Diego Hadden Associates Tel: (714) 565-9445 TWX: 910-335-2057 CONNECTICUT Essex Eastern Technology Tel: (203)767-8505 GEORGIA Tucker Rep, Inc. Tel: (404) 938-4358 B.27 MASSACHUSETTS Lexington, Circuit Sales Company Tel: (617) 861-0567 MINNESOTA Minneapolis Comstrand, Inc. Tel: (612) 788-9234 TWX: 910-576-0924 MISSOURI Grandview Beneke & McCaul Tel: (816) 765-2998 Domestic Representatives (continued) NEW YORK Clinton Advanced Components Tel: (315) 853-6438 Endicott Advanced Components Tel: (607) 785-3191 North Syracuse Advanced Components Tel: (315) 699-2671 TWX: 710-541-0439 Rochester Advanced Components Tel: (716) 554-7017 Scottsville Advanced Components Tel: (716) 889-1429 W_ Babylon Astrorep Tel: (516) 422-2500; (201) 624-4408; (203) 324-4208 TWX: 510-227-8114 NORTH CAROLINA Raleigh Rep, Inc. Tel: (919) 851-3007 OHIO Centerville S.A.I. Marketing Tel:(513) 435-3181 TWX: 8lO-459-1647 Shaker Heights S.A.I. Marketing Tel: (216) 751-3633 TWX: 810-421-8289 Zanesville S.A.I. Marketing Tel: (614) 454-8942 OKLAHOMA Oklahoma City Ammon & Rizos Tel: (405) 942-2552 Tel: (919) 851-300" OREGON VIRGINIA Portland SD-R2 Products & Sales Tel: (503) 246-9305 Charlottesville Coulbourn DeGreif, Inc. Tel: (804) 977-0031 PENNSYLVANIA WASHINGTON Monroeville S.A.I. Marketing Tel: (412) 856-6210 Bellevue SD-R2 Products & Sales Tel: (206) 747-9424 or (206) 624-2621 TWX: 810-443-2483 SOUTH CAROLINA Greenville Rep., Inc. Tel: (803) 233-8595 TEXAS Austin Ammon & Rizos Tel: (512) 454-5131 TWX: 910-374-1369 Dallas Ammon & Rizos Tel: (214) 233-5591 TWX: 910-860-5137 Houston Ammon & Rizos Tel: (713) 781-6240 TWX: 910-881-6382 TENNESSEE Jefferson City Rep, Inc. Tel: (615) 475-4105 TWX: 810-570-4203 UTAH North Salt Lake R2Marketing Tel: (801) 298-2631 TWX: 910-925-5607 Parker R2Marketing Tel: (303) 841-5822 Salt Lake City R2 Marketing Tel: (801) 290-2631 TWX: 910-925-5607 WISCONSIN Menomonee Falls Oasis Sales Tel: (414) 251-9431 CANADA Ottowa, Ontario Vitel Electronics Tel: 613-236-0396 TWX: 053-3198 Can tee Reps, Inc. Tel: (613) 725-3704 TWX: 610-562-8967 Rexdale, Ontario Vi tel Electronics Tel: 416-245-8528 TWX: 610-491-3728 Ste_ Genevieve, Quebec Can tee Reps, Inc. Tel: (514) 626-3856 TWX: 610-422-3985 St. Laurent, Quebec Vitel Electronics Tel: 514-331-7393 TWX: 610-421-3124 Toronto, Ontario Tel: (416)d 675-2460 or 2461 TWX: 610-492-2655 Domestic Distributors ARIZONA Phoenix Kierulff (602) 243-4101 Sterling Electronics (602) 258-4531 CALIFORNIA Cupertino Western Microtechnology (408) 725-1660 Irvine Schweber Electronics (213) 537-4320 or (714) 556-3880 Los Angeles Kierulff Electronics (213) 725-0325 Los Gatos ROW Int'l, Inc. (408) 354-7698 Palo Alto Kierulff Electronics (415) 968-6292 San Diego Anthem Electronics (714) 279-5200 Kierulff Electronics (714) 278-2112 Sunnyvale Anthem Electronics (408) 738-1111 Tustin Anthem Electronics (714) 730-8000 or (213) 582-2122 Kierulff (714) 731-5711 COLORADO Denver Kierulff Electronics (303) 371-6500 Wheatridge Bell Electronics (303) 424-1985 B.28 CONNECTICUT Danbury Schweber Electronics (203) 792-3500 Hamden Arrow Electronics (203) 248-3801 Wallingford Arrow Electronics (203) 265-7741 FLORIDA Ft. Lauderdale Arrow Electronics (305) 776-7790 Hollywood Schweber Electronics (305) 927-0511 Palm Bay Arrow Electronics (305) 725-1480 St. Petersburg Kierulff Electronics (813) 576-1966 AMII~ Domestic Distributors (continued) GEORGIA Atlanta Schweber Electronics (404) 449-9170 Norcross Arrow Electronics (404) 449-8252 ILLINOIS Elk Grove Village Kierulff (312) 640-0200 Schweber Electronics (312) 593-2740 Lombard RIM Electronics (312) 932-5150 Schaumburg Arrow Electronics (312) 893-9420 INDIANA Indianapolis RIM Electronics (317) 247-9701 MARYLAND Baltimore Arrow Electronics (301) 247-5200 Gaithersburg Schweber Electronics (301) 247-5200 MASSACHUSETTS Bedford Schweber Electronics (617) 275-5100 Billerica Kierulff (617) 667-8331 or (617) 935-5134 Woburn Arrow Electronics (617) 933-8130 MICHIGAN Ann Arbor Arrow Electronics (313) 971-8220 Livonia Schweber Electronics (313) 525-8100 Wyoming RIM Electronics (616) 531-9300 MINNESOTA Bloomington Arrow Electronics (612) 830-1800 Edina Arrow Electronics (612) 830-1800 Eden Prairie Schweber Electronics (612) 941-5280 NEW JERSEY TEXAS Fairfield Kierulff (201) 575-6750 Schweber Electronics (201) 227-7880 Moorestown Arrow Electronics (215) 928-1800 or (609)235-1900 Saddlebrook Arrow Electronics (201) 797-5800 Dallas Arrow Electronics (214) 386-7500 R.M. Dallas, Inc. (214) 263-8361 Schweber Electronics (214) 661-5010 Houston Schweber Electronics (713) 784-3600 UTAH Albuquerque Bell Electronics (505) 292-2700 Salt Lake City Bell Electronics (801) 972-6969 Kierulff Electronics (801) 973-6913 NEW YORK WASHINGTON NEW MEXICO Farmingdale Arrow Electronics (516) Fishkill Arrow Electronics (914) Hauppauge Arrow Electronics (516) Liverpool Arrow Electronics (315) Rochester Arrow Electronics (716) Schweber Electronics (716) 424-2222 Westbury Schweber Electronics (516) 334-7474 694-6800 896-7530 WISCONSIN 231-1000 652-1000 275-0300 NORTH CAROLINA Winston Salem Arrow Electronics (919) 725-8711 OHIO Beechwood Schweber Electronics (216) 464-2970 Kettering Arrow Electronics (513) 435-5563 Reading Arrow Electronics (513) 761-5432 Solon Arrow Electronics (216) 248-3990 OREGON Portland Kierulff Electronics (503) 641-9150 PENNSYLVANIA Horsham Schweber Electronics (215) 441-0600 Pittsburgh Arrow Electronics (412) 351-4000 NEW HAMPSHIRE Manchester Arrow Electronics (603) 668-6968 B.29 Seattle Kierulff Electronics (206) 575-4420 Tukwila Arrow Electronics (206) 575-0907 Oak Creek Arrow Electronics (414) 764-6600 Waukesha Kierulff Electronics (414) 784-8160 CANADA Alberta Edmonton Bowtek Electric Co. (403) 452-9050 British Columbia Vancouver Bowtek Electric Co. (604) 736-1141 Future Electronics, Inc. (604) 438-5545 Manitoba Winnepeg Bowtek Electric Co. (204) 633-9525 Ontario Downsview Cesco Electronics, Ltd. (416) 661-0220 Future Electronics, Inc. (416) 663-5563 Ottawa Cesco Electronics, Ltd. (613) 729-5118 Future Electronics, Inc. (613) 820-8313 Quebec Montreal Cesco Electronics, Ltd. (514) 735-5511 Future Electronics, Inc. (514) 731-7441 Quebec Cesco Electronics, Ltd. (418) 524-4641 International Representatives and Distributors ARGENTINA FRANCE ROW, Inc. 3421 Lariat Drive Shingle Springs, Calif. 95682 Tel: (916) 677-2827 TLX: 171373 ROW INCSHS9 Bernard Marchal 16 Avenue du General De Gaulle 67000 Strasbourg, France Produits Electronique Professionals S.A.R.L. (P.E.P.) 2 - 4 Rue Barthelemy 92120 Montrouge Tel: (01) 7353320 TLX: 204534 Tekelec Airtronic B.P. No.2 Cite des Bruyeres Rue Carle Vernet 93210 Sevres, France Tel: (01) 027 75 35 TLX: 204552 Logic Systems International, Inc. Ltd. Moriden Bldg. 5th Floor 3-9-9 Mita, Minato-Ku Tokyo, Japan 108 Tel: (03) 454-3261 Matsushita Electric Trading Company, Ltd. 71, 5-Chome, Kawaramachi Higashi-ku Osaka Tel: (06) 204-5510 TLX: 781-63417 Taiyo Electric Co. Nakazawa Bldg. Shibuya-ku. Tokyo Tel: (03) 379-2926 TLX: 24904 HOLLAND MEXICO Techmation Electronics NV Nieuve Meerdijk 31 P.O. Box 31 1170 AA Badhoevedorp Schipol, Holland SC 421 Tel: 02968-6451 TLX: 13427 ROW, Inc. 3421 Lariat Drive Shingle Springs. Calif. 95682 Tel: (916) 677-2827 TLX: 171373 ROW INCSHSG Dicopel S.A. Augusto Rodin No. 20 Col Napoles Mexico 18 D.F. AUSTRALIA Rifa Pty. Ltd. 202 Bell Street Preston, Victoria 3072 Tel: (03)480 1211 TLX: AA31001 AUSTRIA Triagonal Handelsgesellschaft GmbH Kaerntner Str. 21 - 23 A-1015 Wein, Vienna Tel: (0222) 52 82 92 TLX: 13862 BELGIUM Betea Automation S.A.lN.V. Avenue Geo Bernier 15 1050 Brussels, Belgium Tel: 6499900 TLX: 23188 BRAZIL Datatronix Electronica Ltda. Av. Pacaembu, 746 - Conj. 11 Sao Paulo, CEP 01234 Tel: 209-0134 TLX: 391-1131889 DAEL BR ENGLAND Distronic, Ltd. 50-51 Burnt Mill, Elizabeth Way Harlow, Essex, England Tel: (0279) 39701 TLX: 851-81387 Quarndon Electronics Ltd. Slack Lane Derby DE 3 3ED, England Tel: (0332) 32651 TLX: 37163 Semiconductor Specialists U.K., Ltd. Premier House Fairfield Road, Yiewsley West Drayton Mtddx Tel: (08954) 46415 TLX: 21958 Ritro Electronics (U.K.) Grefell Place Maidenhead Berkshire, England Tel: (0628) 36227 Vako Electronics Ltd. Pass Street Werneth, Oldham Greater Manchester Tel: (061) 652-6316 TWX: 668250 FINLAND OY Atomica AB P.O. Box 22, 02171 Espoo 17 Tel: 80 42 35 33 TLX: 12-1080 HONGKONG Electrocon Products Limited 1020 Star House Kowloon Tel: 3-679557 or 3-679269 TLX: 84996 TGRAF HX INDIA ROW International, Inc. 22 West Central Ave Los Gatos, Calif. 94030 Tel: (408) 354-7698 TLX: 352042 ROW INTL LSGTS ISRAEL R.N. Electronics, Ltd. Hagolan 103 Ramat-Hachayal Tel Aviv ITALY C.LD. s.r.l. Viale Degli Ammiragli 67, 00136 Roma Tel: (06) 63-81-981 TWX: 680474 Cefra s.r.l. Via Giovanni Pascoli 60 20133 Milano Tel: (02) 23 52 64 or (02) 23 60 154 TLX: 311644 Mesa Spa Viale Monterosa 13 20135 Milano Tel: 434333 TLX: 334022 JAPAN Kyokuto Boeki Kaisha, Ltd. (KBK) 7th Floor, New Otemachi Bldg. 2-1, 2-Chome, Otemachi Chiyoda-ku, Tokyo, 100-91 Logic House, Inc. 7-2-8 Nishishinjuku, Shinjuku-ku Tokyo 160 NETHERLANDS Techmation Electronics BV Nieuwe Meerdikj 31 P.O. Box 31 1170AA Badhoevedorp Schipol. Holland SC 421 Tel: (02968) 6451 TLX: 13427 NEW ZEALAND David P. Reid (NZ) Ltd. Box 2630. Auckland 1 Tel: 492-189 TLX: 791 2612 SINGAPORE Dynamar International Ltd. Cuppage Center, Suite 526 55 Cuppage Road Singapore 9 Tel: 235-1139 TLX: RS 26283 DYNAMA SOUTH AFRICA Radiokom Pty, Ltd. P.O. Box 56310 Pinegowrie 2123. Transvaal Johannesburg Tel: 48-5712 TLX: 960-80838 Tecnetics P.O. Box 56310 Pinegowrie 2123. Transvaal Johannesburg Tel: 48-5712 TLX: 960-80838 SPAIN Interface S.A. Ronda San Pedro 22. 3-3 Barcelona 10, Spain Tel: (03) 3017851 TLX: 51508 (continued) B.30 AMII~ International Representatives and Distributors (continued) SWEDEN A.B. Rifa Fack, S-16300 Spanga Tel: (08) 751 00 20 TLX: 13690 SWITZERLAND W. Moor AG 8105 Regensdorf ZH Bahnstrasse 58 Zurich Tel: (01) 8406644 TLX: 52042 TAIWAN Promotor Co., Ltd. 2nd Fir., 33 Lane 395 Fu-Yuan Street Taipei, Taiwan ROC Tel: Taipei 7689743 TLX: TAIPEI 27271 COMMOTEK Ditronic, GmbH 1M Asemwald 48 D-7000 Stuttgart 70 Tel: (0711) 724 844 TLX: 725-5638 Gustav Beck KG Eltersdorfer Strasse 7 8500 Nurnberg 15 Tel: (0911) 34966 TLX: 622334 Microscan GmbH Uberseering 31 Postfach 60 17 05 2000 Hamburg 60 Tel: (040) 6305 067 TLX: 213288 WEST GERMANY Aktiv Elektronik GmbH Ballinstrasse 12-14 D-lOOO Berlin 47 Tel: (030) 684 50 88 TLX: 185327 B.31 Mikrotec, GmbH Johannesstr. 91 D-7000 Stuttgart 1 Tel: (0711) 22 80 27 TLX: 722818 Onmi-Ray GmbH Ritzbruch 41 Postfach 3175 D-4054 Nettetal 1 Tel: 0215317961 TLX: 854245 YUGOSLAVIA Iskra Standard/Iskra IEZE Stegne 15D PP 312 61000 Ljubljana Tel: (051) 551-353 TLX: 31351 YU-ISELEM


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