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Copyright© 1980 by Intersil, Inc.
Printed in the United States of America. All rights reserved.
This book, or parts 0/ it, may nol be reproduced in any form
without written permissionjrom the publisher.
Information furnished herein is believed to be accurate and
reliable; however, no responsibility is assumed for any errors.
Circuit diagram!J illustrate typical applications and do not
necessarily contain complete instructional information.
Intersil does not assume any responsibility for circuits shown or
represent that they do n01 in/ringe on existing or future patent
rights. Descriptions herein do not imply the granting of licenses
to make, use, or sell equipment constructed in accordance
herewith.
Additional copies may be ordered for $5.00 from:

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Attn: Marketing Services, MS 38
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Data Acquisition
and Conversion
Handbook
A Technical Guide to
AID and 01 A Converters
and Their Applications

U~UlL
U.S.A. - 10710 N. Tantau Avenue, Cupertino, California 95014, Tel: (4081 996-5000
France - 217 Bureaux de la Colline, de St. Cloud, Batiment D, 92213 Saint-Cloud Cedex, Tel: 111 602.57.11
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United Kingdom - 9th Floor, Snamprogetti House, Basing View, Basingstoke RG21 2YS Hampshire,
England, Tel: 0256-57361
Intersil cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in an Intersil product. No other circuit
patent licenses are implied. Intersit reserves the right to change the circuitry and specifications without notice at any time.
Printed," USA. C Copyright 1980. Intersil, Inc., All Rights Reserved.

Contents
1. Principles of Data Acquisition and Conversion ....................................... 1
2. AID and DIA Converters ........................................................... 27
\":
Selecting AID Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 29
Where and When to Use Which Data Converter ...................................... 35
The Integrating AID Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 40
Applying the 7109 A/D.Converter ................................................... 44
Understanding the Auto-Zero and Common Mode
Performance of the 71061710717109 Family .......................................... 48
Know Your Converter Codes ................. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 56
The ICL7104: A Binary Output AID Converter for ",Processors ....................... 62
Power DIA Converters Using the ICH8510 .......................................... 76
Quad Current Switches for AID Conversion ......................................... 80
Digital Panel Meter Experiments for the Hobbyist .................................... 86
Low Cost Digital Panel Meter Designs . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 92
Building an Auto Ranging DMM with the ICL8052A17103A
AID Converter Pair ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 98
4-1/2 Digit Panel Meter Demonstrationllnstrumentation Boards ....................• 104
Hybrid and Monolithic Data Conversion Circuits .................................... 112
Hybrid 12-bit AID Converter ....................................................... 121
Video Analog-to-Digital Conversion ................................................ 127
Compensate for Temperature Drift in Data Conversion Circuits ..................... 133
Interpretation of Data Converter Accuracy Specs ................................... 139
Graphs Give Aperture Time Required for AID Conversion ........................... 148
Do's and Dont's of Applying AID Converters ....................................... 152
3. Data Conversion Systems ......................................................... 155
Single Hybrid Package Houses 12-bit Data Acquisition System ...................... 157
Put Video AID Converters to Work ................................................. 163
Microcomputers in an Analog World ............................................... 169
Interfacing Data Converters and Microprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 173
Straight Talk on AID Converter Boards . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . .. 182
Application of Analog Conversion Prodllcts in Microcomputers ..................... 186
Remote Data Acquisition System Needs Just One Twisted Pair
to Link Analog Sensors to Host Computer •......................................•. 194
Dual Word Length Serial Protocol Improves Data Acquisition Network ............... 200
4. Sample-Holds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 209
Designing with a Sample-Hold Won't be a Problem
if You Use the Right Circuit ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 211
Keep Track of a Sample-Hold from Mode to Mode to Locate Error Sources .......... 217
Pick Sample-Holds by Accuracy and Speed and Keep HOLD Capacitors in Mind ..... 225
Analyzing the Dynamic Accuracy of Simultaneous Sample and Hold Circuits . . . . . . .. 232
Test Your Sample-Hold IQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 236

ii

5. High Speed Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 243
High Speed Op Amps - They're in a Class by Themselves .. . . . . . . . . . . . . . . . . . . . . . .. 245

Using the ICH8500 Ultra Low Bias Current Op Amp ................................ 251
The ICL8007 - A High Performance FET Input Op Amp ............................ 254
Using the ICL8043 Dual FET Input Op Amp ........................................ 258
Using the 8048/8049 Log/Antilog Amp ............................................. 262
The ICL8013 Four Quadrant Analog Multiplier ...................................... 268
A Precision Waveform Generator and Voltage Controlled Oscillator . . . . . . . . . . . . . . . .. 273
Everything You Always Wanted to Know About the 8038 ........•................... 280
Power Supply Design Using the ICL8211/8212 ..................................... 284
Unity Gain Buffer Amplifier is Ultra Fast ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 292
Commutating Design for IC Amplifier Virtually Eliminates Offset Errors .............. 293
......... , . . . . . . . .. . . . . . . . . . .. .. . . . . . . . . ..
Switching Signals with Semiconductors ............................................
Understanding and Applying the Analog Switch ....................................
The IH5009 Analog Switch Series ..................................................
A New CMOS Analog Gate Technology ............................................

297
299
302
318
326

Reduce CMOS Multiplexer Troubles Through Proper Device Selection ..............
...................................................................
Voltage to Frequency Converters ..................................... . . • . . . . . . . . ..
Voltage to Frequency Converters: Versatility Now at Low Cost ........... . . . . . . . . . ..
Consider VlF Converters for Data Acquisition Systems , . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Sending Transducer Signals Over 100 Feet? ........................................

328
333
335
339
344
351

Frequency Converter is a Dual Operator ................. . . . . . . . . . . . . . . . . . . . . . . . . ..
Test Your VlF Converter IQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8. Glossary of Data Acquisition Terms ................................................
9. Component Selector Guides .......................................................
VMOS ............................................................................

356
359
365
375
376

6. Analog Gates, Switches and Multiplexers

7. V/F Converters

Discrete ...............................................................•.......... 378
Analog Gates, Switches, Multiplexers .............................................. 382
Data Acquisition .................................................................. 386
Linear ............................................................................ 388
Timers, Counters, Display Drivers . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 392
RAMs, ROMs, PROMs, EPROMs ................................................... 393

iii

PREFACE
In recent years Intersil and Datel have published
many technical articles on the subject of data
acquisition and conversion in the industry trade
journals. Since many engineers have requested
reprints of these articles, it was decided to compile
them into a useful, coherent reference handbook on
data conversion and make it available at moderate
cost. This handbook is the result of that effort.
The book also contains a 23 page basic introduction
to data conversion entitled "Principles of Data
Acquisition and Conversion" and a useful "Glossary
of Data Conversion Terms" which defines the 200
most common terms used in data conversion
technology today.
The following authors have contributed to this work:

DB
PB
GB
LC
MD
LE
DF
LG
RH
RJ
JK
PM
WM
JM
GM
BO
SO
JP
ES
DW
RW
GZ

Dave Bingham
Peter Bradshaw
George F. Bryant
Larry Copeland
Mike Dufort
Lee Evans
Dave Fullagar
Larry Goff
Ray Hendry
Ralph Johnston
Jim Knitter
Paresh Maniar
Wayne E. Marshall
John M. Mills
Gene Murphy
Bill O'Neill
Skip Osgood
Jan Prak
Ed Sliger
Dave Watson
Dick Willenken
Eugene L. Zuch

iv

1. Principles of

Data Acquisition
and Conversion

2

Principles of
Data Acquisition and Conversion
Data Acquisition Systems
Introduction

by means of a transducer; once in electrical form,
all further processing is done by electronic circuits.

Data acquisition and conversion systems interface
between the real world of physical parameters,
which are analog, and the artificial world of digital
computation and control. With current emphasis on
digital systems, the interfacing function has become
an important one; digital systems are used widely
because complex circuits are low cost, accurate,
and relatively simple to implement. In addition,
there is rapid-growth in use of minicomputers and
microcomputers to perform difficult digital control
and measurement functions.
Computerized feedback control systems are used in
many different industries today in order to achieve
greater productivity in our modern industrial
society. Industries which presently employ such
automatic systems include steel making, food processing, paper production, oil refining, chemical
manufacturing, textile production, and cement
manufacturing.
The devices which perform the interfacing function
between analog and digital worlds are analog-todigital (A/D) and digital-to-analog (D/A) converters,
which together are known as data converters. Some
of the specific applications in which data converters
are used include data telemetry systems, pulse
code modulated communications, automatic test
systems, computer display systems, video signal
processing systems, data logging systems, and
sampled-data control systems. In addition, every
laboratory digital multimeter or digital panel meter
contains an A/D converter.
Besides A/D and D/A converters, data acquisition
and distribution systems may employ one or more
of the following circuit functions:

PHYSICAL

PARAMETfR

OTHER
ANALOG

CHANNElS

Figure 1. Data Acquisition System

Next, an amplifier boosts the amplitude of the
transducer output signal to a useful level for further
processing. Transducer outputs may be microvolt
or millivolt level signals which are then amplified
to 1 to 10 volt levels. Furthermore, the transducer
output may be a high impedance signal, a differential signal with common-mode noise, a current output, a signal superimposed on a high voltage, or a
combination of these. The amplifier, in order to
convert such signals into a high level voltage, may
be one of several specialized types.
The amplifier is frequently followed by a low pass
active filter which reduces high frequency signal
components, unwanted electrical interference noise,
or electronic noise from the signal. The amplifier
is sometimes also followed by a special nonlinear
analog function circuit which performs a nonlinear
operation on the high level signal. Such operations
include squaring, multiplication, division, RMS
conversion, log conversion, or linearization.
The processed analog signal next goes to an analog
multiplexer which sequentially switches between a
number of different analog input channels. Each
input is in turn connected to the output of the multiplexer for a specified period of time by the multiplexer switch. During this connection time a samplehold circuit acquires the signal voltage and then
holds its value while an analog-to-digital converter
converts the value into digital form. The resultant
digital word goes to a computer data bus or to the
input of a digital circuit.
Thus the analog multiplexer, together with the
sample-hold, time shares the ND converter with a
number of analog input channels. The timing and
control of the complete data acquisition system is
done by a digital circuit called a programmersequencer, which in turn is under control of the

Basic Data Distribution Systems

Transducers
Amplifiers
Filters
Nonlinear Analog .Functions
Analog Multiplexers
Sample-Holds
The interconnection of these components is shown
in the diagram of the data acquisition portion of a
computerized feedback control system in Figure 1.
The input to the system is a physical parameter
such as temperature, pressure, flow, acceleration,
and position, which are analog quantities. The
parameter is first converted into an electrical signal

3

DATA ACQUISITION & CONVERSION HANDBOOK

Quantizing Theory

computer. In some cases the computeritself may
control the entire data acquisition system.
While this is perhaps the most commonly used data
acquisition system configuration, there are alternative ones. Instead of multiplexing high-level signals, low-level multiplexing is sometimes used with
the amplifier following the multiplexer. In such
cases just one amplifier is required, but its gain
may have to be changed from one channel to the
next during multiplexing. Another method is to
amplify and convert the signal into digital form
at the transducer location and send the digital
information in serial form to the computer. Here
the digital data must be converted to parallel form
and then multiplexed onto the computer data bus.

Introduction
Analog-to-digital conversion in its basic conceptual
form is a two-step process: quantizing and coding.
Quantizing is the proce/ls of transforming a continuous analog signal into a set of discrete output
states. Coding is the process of assigning a digital
code word to eaCh of the output states. Some of the
early AID converters were appropriately called
quantizing encoders.
Quantizer Transfer Function
The nonlinear transfer function shown in Figure 3
is that of an ideal quantizer with 8 output states;
with output code words assigned, it is also that of

,,
,,

PROCESS
PARAMETER

111

i

i

~

110
PROCESS
PARAMETER

101

ill

§

~....

~

w

Q

Q

• 8....
~::>

100
011

0

010
001

Figure 2_ Data Distribution System
000

+1.26 +2.50 +3.75 +5.00+6.26 +7.50+8.75 +10.00

INPUT VOLTAGE

Basic Data Acquisition System
Tqe data distribution portion of a feedback control
system, illustrated in Figure 2, is the reverse of the
data IIoCquisition system. The computer, based on the
inputs of the data acquisition system, must close
the 109P on a process and control it by means of
output control functions. These control outputs are
in digital form and must therefore be converted into
analog form in order to drive the process. The
conversion is accomplished by a series of digitalto-analog converters as shown. Each DIA converter
is coupled to the computer data bus by means of a
register which stores the digital word until the next
update. The registers are activated sequentially by
a decoder and control circuit which is under computer control.
.
The DIA converter outputs then drive actuators
which directly control the '{arious process parameters such as temperature, pressure, and flow.
Thus the loop is closed on the process and the result
is a complete automatic process control system
under computer control.

Q~21f' I\. I\. I\. I\. I\. I\. I\.

QUANTIZER +
ERROR
'\.1
-Q/2......

'OJ

--L
Q

\J'J \J'J. \J , "T

Figure 3. Transfer Function 01 Ideal 3-BII Quantizer

a 3-bit AID converter. The 8 output states are
assigned the sequence of binary numbers from 000
through 111. The analog input range for this quantizer is 0 to + lOY.
There are several important points concerning the
transfer function of Figure 3. First, the resolution
of the quantizer is defined as the number of output
states expressed in bits; in this case it is a 3-bit
quantizer. The number of output states for a binary
coded quantizer is 2n, where n is the number of
bits. Thus, an 8-bit quantizer has 256 output states
and a l2-bit quantizer has 4096 output states.
As shown in the diagram, there are 2n-l analog
decision points (or threshold levels) in the transfer
function. These points are at voltages of +0.625,

4

noise has a peak-to-peak value of Q but. as with
other types of noise. the average value is zero. Its
RMS value. however. is useful in analysis and can
be computed from the triangular waveshape to be
Q/2J3.

+ 1.875. + 3.125. + 4.375. + 5.625. + 6.875. and
+8.125. The decision points must be precisely set
in a quantizer in order to divide the analog voltage
range into the correct quantized values.
The voltages + 1.25. + 2.50. + 3.75. + 5.00. + 6.25.
+7.50. and +8.75 are the center points of each
output code word. The analog decision point voltages
are precisely halfway between the code word center
points. The quantizer staircase function is the best
approximation which can be made to a straight line
drawn through the origin and full scale point; notice
that the line passes through all of the code word
center points.

Sampling Theory
Introduction
An analog-to-digital converter requires a small. but
significant. amount of time to perform the quantizing
and coding operations. The time required to make
the conversion depends on several factors: the converter resolution. the conversion technique. and the
speed of the components employed in the converter.
The conversion speed required for a particular
application depends on the time variation of the
signal to be converted and on the accuracy desired.

Quantizer Resolution and Error
At any part of the input range of the quantizer. there
is a small range of analog values within which the
same output code word is producer:!. This small range
is the voltage differenctl between any two adjacent
decision points and is known as the analog quantization size. or quantum. Q. In Figure 3. the quantum is 1.25V and is found in general by dividing the
full scale analog range by the number of output
states. Thus

Aperture Time
Conversion time is frequently referred to as aperture time. In general. aperture time refers to the
time uncertainty (or time window) in making a
measurement and results in an amplitude uncertainty (or error) in the measurement if the signal
is changing during this time.

where FSR is the full scale range. or 10V in this
case. Q is the smallest analog difference which can
be resolved. or distinguished. by the quantizer. In
the case of a 12-bit quantizer. the quantum is much
smaller and is found to be

Q = FSR
2°

= lOY =

boV-

.~\tl

•ttl

2.44 mV

4096

Figure 4. Aperture Time and Amplitude Uncertainly

If the quantizer input is moved through its entire
range of analog values and the difference between
output and input is taken. a sawtooth error function
results. as shown in Figure 3. Thiti function is called
the quantizing error and is the irreducible error
which results from the quantizi'ng process. It can
be reduced only by increasing the number of output
states (or the resolution) of the quantizer. thereby
making the quantization finer.
For a given analog input value to the quantizer,
the output error will vary anywhere from 0 to
±Q/2; the error is zero only at analog values
corresponding to the code center points. This error
is also frequently called quantization uncertainty
or quantization noise.
The quantizer output can be thought of as the analog input with quantization noise added to it. The

As shown in Figure 4. the input signal to the AID
converter changes by AV during the aperture time
ta in which the conversion is performed. The error
can be considered an amplitude error or a time
error; the two are related as follows
AV

=t

a

dV(t)
dt

where dV(t)/dt is the rate of change with time of
the input signal.
It should be noted that AV represents the maximum
error due to signal change. since the actual error
depends on howihe conversion is done. At some
point in time within tao the signal amplitude corresponds exactly with the output code word produced.

5

DATA ACQUISITION & CONVERSION HANDBOOK

then stores it on a capacitor fQr the time required
to perform the AID conversion. The aperture time
of the AID converter is therefore greatly reduced
by the much shorter aperture time of the samplehold circuit. In turn, the aperture time of the
sample-hold is a function of its bandwidth and
switching time.
Figure 5 is a useful graph of Equation 5. It gives
the aperture time required for converting sinusoidal
signals to a maximum error less than one part in
2D where n is the resolution Qf the converter in bits.
The peak to peak value of the sinusoid is assumed
to be the full scale range of the AID converter.
The graph is most useful in selecting a samplehold by aperture time or an AID converter by
conversion time.

For the specific case of a sinusoidal input signal, the
maximum rate of change occurs at the zero crossing
of the waveform, and the amplitude error is

AV

= ta ~

(A sin wt)t=o = taAw

The resultant error as a fraction of the peak to peak
full scale value is

• = AV = "ft.

2A

From this result the aperture time required to
digitize a 1 kilohertz signal to 10 bits resolution
can be found. The resolution required is one part
in 2'0 or 0.001.
ta

•

0.001

= -;;t = 3.14 X 103 = 320 x 10

-9

Sampled-Data Systems and the Sampling Theorem
In data acquisition and distribution systems, and
other sampled-data systems, analog signals are
sampled on a periodic basis as illustrated in Figure
6. The train of sampling pulses in 6(b) represents a
fast-acting switch which connects to the analog
signal for a very short time and then disconnects for
the remainder of the sampling period.

The result is a required aperture time of just 320
nanoseconds!
One should appreciate the fact that 1 KHz is not a
particularly fast signal, yet it is difficult to find a
10 bit AID converter to perform this conversion at
any price! Fortunately, there is a relatively simple
and inexpensive way around this dilemma by using
a sample-hold circuit.

I"'

~,~

]\

100,..

.4?{

]\

10,._

'!I

~

-Nt'

'0

IV,_

I

''1\

'"

~;8,

,

~~

'OOM

fc, then the two spectra are separated and the original signal can be recovered without distortion. This demonstrates the result of the
Sampling Theorem that fs>2fc.Frequency folding
can be eliminated in two ways: first by using a high
enough sampling rate, and second by filtering the
signal before sampling to limit its bandwidth to
f./2.
One must appreciate the fact that in practice there
is always some frequency folding present due to
high frequency signal components, noise, and nonideal pre-sample filtering. The effect must be reduced to negligible amounts for the particular application by using a sufficiently high sampling rate.
The required rate, in fact, may be much higher than
the. minimum indicated by the Sampling Theorem.
The effect of aIf inadequate sampling rate on a
sinusoid is illustrated in Figure 8; an alias frequency
in the recovered signal results. In this case, sampling
at a rate slightly less than twice per cycle gives
the low frequency sinusoid shown by the dotted line
in the recovered signal. This alias frequency can be
significantly different from the original frequency.
From the figure it is easy to see that if the sinusoid is sampled at least twice per cycle, as required
by the Sampling Theorem, the original frequency
is preserved.

In)
SIGNAL

(b)
SAMPLING
PULSES

(e)
SAMPLED
SIGNAL

(d)
SAMPLED AND ,
HELD SIGNAL

r'-------'''f-----:la--

Figure 6. Signa' Sampling

The answer to the question is contained in the wellknown Sampling Theorem which may be stated as
follows: If a continuous, bandwidth-limited signal
contains no frequency components higher than fe,
then the original signal can be recovered without
distortion if it is sampled at a rate of at least 2fe
samples per second.
Frequency Folding and Aliasing
The Sampling Theorem can be demonstrated by the
frequency spectra illustrated in Figure 7. Figure
7(a) shows the frequency spectrum of a continuous
bandwidth-limited analog signal with frequency
components out to fc. When this signal is sampled
at a rate fs, the modulation process shifts the original
spectrum out to fs, 2f., 3fs, etc. in addition to the
one at the origin. A portion of this resultant spectrum is shown in Figure 7(b).

(n) CONTINUOUS

Rgure 8. Alias Frequency Caused by Inadequate Sampling Rate

v~

Coding for Data Converters

SIGNAL SPECTRUM·

ko----~,tc--------·,-

(b) SAMPLED
SIGNAL SPECTRUM

V~QUENCYFOLOING
o

fs-fc \ Ie

f.

fs+fc

fs/2

Figure 7. Frequency Spectra Demonstrating the Sampling
Theorem

Natural Binary Code
AID and D/A converters interface with digital
systems by means of an appropriate digital code.
While there are many possible codes to select, a
few standard ones are almost exclusively used with
data converters. The most popular code is natural
binary, or straight binary, which is used in its fractional form to represent a number
N = a12 -1

7

+ a22 -2 + 1132-3 + .... + an2 ·n

DATA ACQUISITION 81 CONVERSION HANDBOOK

where each coefficient "an assumes a value of zero
or one. N has a value between zero and one.
A binary fraction is normally written as 0.110101,
but with data converter codes the decimal point is
omitted and the code word is written 110101. This
code word represents a fraction of the full scale
value of the converter and has no other numerical
significance.
The binary code word 110101·therefore represents
the decimal fraction (1 x 0.5) + (1 x 0.25) + (1 x 0.125)
+ (1 x 0.0625) + (0 x 0.03125) + (1 x 0.015625)
= 0.828125 or 82.8125% of full scale for the converter.
If full scale is + 10V, then the code word represents
+8.28125V. The natural binary code belongs to a
class of codes known as positive weighted codes
since each coefficient has a specific weight, none
of which is negative.
The leftmost bit has the most weight, 0.5 of full
scale, and is called the nwst significant bit, or MSB;
the rightmost bit has the least Weight, 2- D of full
scale, and is therefore called the least significant
bit, or LSB. The bits in a code word are numbered
from left to right from 1 to n.
The LSB has the same analog equivalent value as
Q discussed previously, namely
LSB (Analog Value) = F~~
Table 1 is a useful summary of the resolution, num·
ber of states, LSB weights, and dynamic range for
data converters from one to twenty bits resolution.
RESOLUTION NUMBER
OF STATES
BITS
2"
n
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

1
2
4
8
16
32
64
128
256
512
1024
2048
4096
8192
16384
32768
65536
131072
262144
52428B
1048576

LSBWEIGHT

2-"
1
0.5
0.25
0.125
0.0625
0.03125
0.015625
0.0078125
0.00390625
0.001953125
0.0009765625
0.00048828125
0.000244140625
0.0001220703125
0.00006103515625
0.000030517578125
0.0000152587890625
0.00000762939453125
0.000003814697265625
0.0000019073486328125
0.00000095367431640625

DYNAMIC
RANGE
dB
0
6
12
18.1
24.1
30.1
36.1
42.1
48.2
54.2
60.2
66.2
72,2
78.3
84.3
90.3
96.3
102.3
108.4
114.4
120.4

and 2" the number of states of the converter.
Since 6.02 dB corresponds to a factor of two, it is
simply necessary to multiply the resolution of a
converter in bits by 6.02. A 12-bit converter, for
example, has a dynamic range of 72.2 dB.
An important point to notice is that the maximum
value of the digital code, namely all 1's, does not
correspond with analog full scale, but rather with
one LSB less than full scale, or FS (1-2-"). Therefore a 12 bit converter with a 0 to + lOV analog
range has a maximum code of 111111111111 and
a maximum analog value of +20V (1-2 -12) =
+9.99756V. In other words, the maximum analog
value of the converter, corresponding'to all one's
in the code, never quite reaches the point defined
as analog full scale.
Other Binary Codes
Several other binary codes are used with ND and
D/A converters in addition to straight binary. These
codes are offset binary, two's complement, binary
coded decimal (BCD), and their complemented
versions. Each code has a specific advantage in
certain applications. BCD coding for example is used
where digital displays must be interfaced such as
in digital panel meters and digital multimeters.
Two's complement coding is used for computer
arithmetic logic operations, and offset binary coding
is used with bipolar analog measurements.
Not only are the digital codes standardized with data
converters, but so are the analog voltage ranges.
Most converters use unipolar voltage ranges of 0
to + 5V and 0 to + 10V although some devices use
the negative ranges 0 to -5V and 0 to -lOY. The
standard bipolar voltage ranges are ±2.5V, ±5V
and ± 10V. Many converters today are pin-programmable between these various ranges.
FRACTION
OFFS
+FS·l LSB
+'" FS
+~FS

+~ FS
+iOFS
+1 LSB
0

+10VFS
+9.961
+7.500
+5.000
+2.500
+1.250
+0.039
0.000

STRAIGHT COMPLEMENTARY
BINARY
BINARY
1111 1111
11000000
10000000
0100 0000
00100000
00000001
00000000

00000000
00111111
01111111
10111111
11011111
11111110
1111 1111

Table 2. Binary Coding for 8 Bit Unipolar Converters

Table 2 shows straight binary and complementary
binary codes for a unipolar 8 bit converter with a
o to + lOV analog FS range. The maximum analog
value of the converter is +9.96lV, or one LSB less
than + lOY. Note that the LSB size is 0.039V as
shown near the bottom of the table. The complementary binary coding used in some converters is
simply the logic complement of straight binary.
When AID and DfA converters are used in bioolar
operation, the analog range is offset by half scale,

Table 1. Resolution, Number of States, LSB Weight, and
Dynamic Range for Data Converters

The dynamic rang-e of a data converter in dB is
found as follows:
DR (dB) = 20 log 2"= 20nlog2
= 20n (0.301) = 6.02n
where DR is dynamic range, n is the number of bits,

8

complementing of the MSB. In bipolar coding, the
MSB becomes the sign bit.
The sign·magnitude binary code, infrequently used,
has identical code words for equal magnitude analog
values except that the sign bit is different. As
shown in Table 3 this code has two possible code
words for zero: 1000 0000 or 0000 0000. The two
are usually distinguished as 0+ and 0-, respectively. Because of this characteristic, the code has
maximum analog values of ± (FS-1 LSB) and
reaches neither analog + FS or - FS.

or by the MSB value. The result is an analog shift
of the converter transfer function as shown in
Figure 9. Notice for this 3·bit AID converter transfer function that the code 000 corresponds with
-5V, 100 with OV, and 111 with +3.75V. Since the
output coding is the same as before the analog
shift, it is now appropriately called offset binary
coding.
/
/

/

/

w 111

o

o

u
.... 110

BCD Codes
Table 4 shows BCD and complementary BCD coding
for a 3 decimal digit data converter. These are the
codes used with integrating type ND converters
employed in digital panel meters, digital multimeters, and other decimal display applications. Here
four bits are used to represent each decimal digit.
BCD is a positive weighted code but is relatively
inefficient since in each group of four bits, only 10
out of a possible 16 states are utilized.

:J

~

5

-I

Q

I /

101

~:/

010

I
I

001

I

I

/,000

o

FRACTION
OF FS

+ 1.25 +2.50 +3.75 +5.00

INPUT VOLTAGE

+FS·l LSB
FS

+*

Figure 9. Transfer Function lor Bipolar 3-BII AID Converter

+}} FS
+)4" FS
+)1; FS

Table 3 shows the offset binary code together with
complementary offset binary, two's complement,
and sign·magnitude binary codes. These are the
most popular codes employed in bipolar data
converters.

+1 LSB

FRACTION

OFFS

OFFSET

±5V FS

BINARY

+4.9976 11111111
+3.7500 11100000
+2.5000 11000000
+1.2500 10100000
+~ FS
0
0.0000 10000000
-)4 FS
--1.2500 01 to 0000
-Y, FS
--2.5000 0100 0000
-3.7500 00100000
-~ FS
-FS +llSB -4.9976 0000 0001
-FS
- 5,0000 00000000
+FS-' LSB
+~ FS
+11 FS

o

11100000

0100 0000
00.10 0000
00000000
11100000

1100 0000
10100000
10000000·
00100000

1011 1111

1100 0000

0100 0000

11011111
11111110
11111111

10100000
1000 0001
10000000

0110 0000

00011111
0011 1111
0101 1111
01111111
10011111

100110011001
011101010000
010100000000
0010 0101 0000
000100100101
00000000 0001
0000 0000 0000

011001100110
100010101111
101011111111
110110101111
111011Qll0l0
111111111110
111111111111

~~~

where FSR is the full scale range and d is the
number of decimal digits. For example if there are
3 digits and the full scale range is lOV, the LSB
value is
LSB (Analog Value) = 10V = .01V = lOmV
103

01111111

BCD coding is frequently used with an additional
overrange bit which has a weight egual to full scale
and produces a 100% increase in range for the AID
converter. Thus for a converter with a decimal
full scale of 999, an overrange bit provides a new
full scale of 1999, twice that of the previous one.
In this case, the maximum output code is 11001
10011001. The additional range is commonly reo
ferred to aslh digit, and the resolution of the ND
converter in this case is 3lhdigits.
Likewise, if this range is again expanded by 100%,
a new full scale of 3999 results and is called 3%
digits resolution. Here two overrange bits have been
added and the full scale output code is 11 1001

SIGN-MAG BINARY

0+

+9.99
+7.50
+5.00
+2.50
+1.25
+0.01
0.00

LSB(AnalogValue)=Q=

·NOTE: Sign Magnitude Brnary has two code words for zero as shown here.

o-

COMPLEMENTARY
BCD

The LSB analog value (or quantum, Q) for BCD is

t1111111

011111"
0110 0000

BINARY CODED
DECIMAL

Table 4. BCD and Complementary BCD Coding.

COMP.OFF.
TWO'S
SIGN-MAG
BINARY COMPLEMENT BINARY
00000000

+10VFS

1000 0000 0000
0000 0000 0000

Table 3. Popular Bipolar Codes Used with Data Converters.

The two's complement code has the characteristic
that the sum of the positive and negative codes
for the same analog magnitude always produces
all zero's and a carry. This characteristic makes
the two's complement code useful in arithmetic
computations. Notice that the only difference
between two's complement and offset binary is the

9

DATA ACQUISITION & CONVERSION HANDBOOK

10011001. When BCD coding is used for bipolar
measurements another bit, a sign bit, is added to the
code and the result is sign-magnitude BCD coding.

mentation amplifier circuit is shown in Figure 11.
Notice that no gain-setting resistors are connected to
either of the input terminals. Instrumentation ampli-

Amplifiers and Filters
Operational and Instrumentioil Amplifiers
The front end of a data acquisition system extracts
the desired analog signal from a physical parameter
by means of a transducer and then amplifies and
filters it. An amplifier and filter are critical compo·
nents in this initial signal processing.
The amplifier must perform one or more of the
following functions: boost the signal amplitude,
buffer the signal, convert a signal current into a
voltage, or extract a differential signal from com·
mon mode noise.

Eo

~EZ'-~E'
R
~
"

Rz

E,

_

-=

1__

+

Figure 11. Simplified Instrumentation Amplifier Circuit

+

fiers
1.
2.
3.
4.

have the following important characteristics.
High impedance differential inputs.
Low input offset voltage drift.
Low input bias currents.
Gain easily set by means of one or two
external resistors.
5. High common-mode rejection ratio.

1

'N\IERT1NG IIOLTlIGE GAIN

E =-IR

CURp_ro~,
__ , ~,.. "
E,

~

-

+ Rz

Ez=

(, R)
~+~

Common Mode Rejection
Common-mode rejection ratio is an important parameter of differential amplifiers. An ideal differential
input amplifier responds only to the voltage difference between its input terminals and does not
respond at all to any voltage that is common to both
input terminals (common-mode voltage). In nonideal
amplifiers, however, the common-mode input signal
causes some output response even though small
compared to the response to a differential
input signal.
The ratio of differential and common-mode responses is defined as the common-mode rejection
ratio. Common-mode rejection ratio of an amplifier
is the ratio (jf differential voltage gain to commonmode voltage gain and is generally expressed in dB.

UNITY GAIN BUFFER

E,

R,

NON-INIIERT1NG VOLTAGE GAIN

Figure 10. Operational Amplifier Configurations

To accomplish these functions requires a variety of
different amplifier types. The most popular type of
amplifier is an operational amplifier which is a
general purpose gain block with differential inputs.
The op amp may be connected in many different
closed loop confignrations, of which a few are shown
in Fignre 10. The gain and bandwidth of the circuits
shown depend on the external resistors connected
around the amplifier. An operational amplifier is a
good choice in general where a single-ended signal
is to be amplified, buffered, or converted from
current to voltage.
In the case of differential signal processing, the
instrumentation amplifier is a better choice since it
maintains high impedance at both of its differenti8I
inputs and the gain is set by a resistor located elsewhere in the amplifier circuit. One type of instru-

CMRR = 2010g l0 AAD

CM

where AD is differential voltage gain and ACM is
common-mode voltage gain. CMRR is a function of
frequency and therefore also a function of the
impedance balance between the two amplifier input
terminals. At even moderate frequencies CMRR can
be significantly degraded by small unbalances in
the source series resistance and shunt capacitance.

10

Other Amplifier Types
There are several other special amplifiers which
are useful in conditioning the input signal in a data
acquisition system. An isolation amplifier is used to
amplify a differential signal which is superimposed
on a very high common-mode voltage. perhaps
several hundred or even several thousand volts.
The isolation amplifier has the characteristics of an
instrumentation amplifier with a very high commonmode input voltage capability.
Another special amplifier. the chopper stabilized
amplifier, is used to accurately amplify microvolt
level signals to the required amplitude. This ampli·
fier employs a special switching stabilizer which
gives extremely low input offset voltage drift.
Another useful device. the electrometer amplifier,
has ultra-low input bias currents. generally less than
one picoampere and is used to convert extremely
small signal currents into a high level voltage.

other undesirable frequency components, and
therefore the choice of a filter is always a compromise. Ideal filters. frequently used as analysis examples, have flat passband response with infinite
attenuation at the cutoff frequency. but are mathematical filters only and not physically realizable.
In practice. the systems engineer has a choice of
cutoff frequency and attenuation rate. The attenuation rate and resultant phase response depend on
the particular filter characteristic and the number
of poles in the filter function. Some of the more
popular filter characteristics include Butterworth.
Chebychev, Bessel. and elliptic. In making this
choice. the effect of overshoot and nonuniform phase
delay must be carefully considered. Figure 12
illusrtates some practical low pass filter response
characteristics.
Passive RLC filters are seldom used in signal processing applications today due chiefly to the undesirable characteristics of inductors. Active filters are
generally used now since they permit the filter
characteristics to be accurately set by precision,
stable resistors and capacitors. Inductors. with their
undesirable saturation and temperature drift characteristics, are thereby eliminated. Also, because
active filters use operational amplifiers, the problems of insertion loss and output loading are also
eliminated.

Filters
A low pass filter frequently follows the signal processing amplifier to reduce signal noise. Low pass
filters are used for the following reasons: to reduce
man-made electrical interference noise. to reduce
electronic noise, and to limit the bandwidth of the
analog signal to less than half the sampling frequency in order to eliminate frequency folding.
When used for the last reason. the filter is called a
pre-sampling filter or anti-aliasing filter.
Man-made electrical noise is generally periodic, as
for example in power line interference, and is sometimes reduced by means of a special filter such as
a notch filter. Electronic noise, on the other hand.
is random noise with noise power proportional to
bandwidth and is present in transducer resistances,
circuit resistances, and in amplifiers themselves.
It is reduced by limiting the bandwidth of the system
to the minimum required to pass desired signal
components.
No filter does a perfect job of eliminating noise or

Settling Time
Definition
A parameter that is specified frequently in data
acquisition and distribution systems is settling time.
The term settling time originates in control theory
but is now commonly applied to amplifiers. multiplexers. and D/A converters.
OVERSHOOT

FINAL VALUE
ERROR BAND

__________ 1__ _
+F.S.

FUlL

SCALE -+--+1
INPUT
STEP

0

~

FINAL ENTRY INlO
SPECIFIED

ERROR BAND

" . 30B

5

o·L---~L----------L--------

I \ ' ( ' '·POLE iESSiL
0

\~
~
\\

5

20
25

0.1

0.2

0.3

0.4 0.5 0.6

O.B 1

'·POLE J
BUTTEiWOiTH

Figure 13. Amplifier Settling Time

f\,"POLE..I.
CHjBVCiEV

\J

•

Settling time is defined as the time elapsed from
the application of a full scale step input to a circuit
to the time when the output has entered and rerMined within a specified error band around its
final value. The method of application of the input
step may vary depending on the type of circuit, but
the definition still holds. In the case of aD/A con-

5

NORMALIZED FREQUENCY

Figure 12. Some Practical Low Pass Filter Characteristics

11

DATA ACQUISITION & CONVERSION HANDBOOK

verter, for example, the step is applied by changing
the digital input code whereas in the case of an
amplifier the input signal itself is a step change.
The importance of settling time in a data acquisition
system is that certain analog operations must be
performed in sequence, and one operation may have
to be accurately settled before the next operation
can be initiated. Thus a buffer amplifier preceding
an AID converter must have accurately settled
before the conversion can be initiated.
Settling time for an amplifier is illustrated in Figure
13. After application of a full scale step input there
is a small delay time following which the amplifier
output slews, or changes at its maximum rate. Slew
rate is determined by internal amplifier currents
which must charge internal capacitances.
As the amplifier output approaches final value, it
may first overshoot and then reverse and under·
shoot this value before finally entering and remaining within the specified error band. Note that
settling time is measured to the point at which
the amplifier output enters and remains within the
error band. This error band in most devices is
specified to either ±0.1% or ±0.01% of the full
scale transition.

It is important to note that an amplifier with a
single-pole response can never settle faster than the
time indicated by the number of closed loop time
constants to the given accuracy. Figure 15 shows
output error as a function of the number of time
constants T where

Amplifier Characteristics
Settling time, unfortunately, is not readily predictable from other amplifier parameters such as bandwidth, slew rate, or overload recovery time, although it depends on all of these. It is also dependent
on the shape of the amplifier open loop gain characteristic, its input and output capacitance, and the
dielectric absorption of any internal capacitances.
An amplifier must be specifically designed for
optimized settling time, and settling time is a parameter that must be determined by testing.

Figure 15. Output Set1l1ng Error as a Function 01 Number

T= ~ =..l....
'"

lM

and f is the closed loop 3 dB bandwidth of the
amplifier.

30

20

10

NUMBER OF TIME CONSTANTS!TI

of Time Constants

Actual settling time for a good quality amplifier rna,)'
be significantly longer than that indicated by the
number of closed loop time constants due to slew
rate limitation and overload recovery time. For
example, an amplifier with a closed loop bandwidth
of 1 MHz has a time constant of 160 nsec. which
indicates a settling time of 1.44 Ilsec. (9 time con·
stants) to 0.01 % of final value. If the slew rate of
this amplifier is 1VII,sec., it will take more than 10
Ilsec. to settle to 0.01 % for a 10V change.

AMPLIFIER OPEN LOOP
RESPONSE (SOB/OCTAVE ROLLOFF)
AMPLIFIER CLOSED LOOP
-RESPONSE

Al

r---------------~

Figure 14. Amplifier Single-Pole Open Loop Gain Characlerlsllc
Figure 16. Ultra-Fast Setlling Hybrid Oparational Ampliller

One of the important requirements of a fast settling
amplifier is that it have a single-pole open loop gain
characteristic. i.e .• one that has a smooth 6 dB per
octave gain roll-off characteristic to beyond the unity
gain crossover frequency. Such a desirable characteristic is shown in Figure 14.

If the amplifier has a nonuniform gain roll-off char·
acteristic. then its settling time may have one of
two undesirable qualities. First. the output may
reach the vicinity of the error band quickly but then

12

take a long time to actually enter it; second. it may
overshoot the error band and then oscillate back
and forth through it before finally entering and
remaining inside it.
Modern fast settling operational amplifiers come in
many different types including modular. hybrid. and
monolithic amplifiers. Such amplifiers have settling
times to 0.1 % or 0.01 % of 2 "sec. down to 100 nsec.
ana are useful in many data acquisition and conversion applications. An example of an ultra-fast
settling operational amplifier of the hybrid type
is shown in Figure 16.

ones are widely used today. Virtually all D/A converters in use are of the parallel type where all
bits change simultaneously upon application of an
input code word; serial type D/A converters. on the
other hand. produce an analog output only after
receiving all digital input data in sequential form.
Weighted Current Source DfA Converter
The most popular D/A converter design in use
today is the weighted current source circuit illustrated in Figure 18. An array of switched transistor
current sources is used with binary weighted currents. The binary weighting is achieved by using
emitter resistors with binary related values of R.
2R. 4R. 8R. ..... 2nR. The resulting collector currents are then added together at the current
summing line.

Digital-To-Analog Converters
Introduction
Digital-to-analog converters are the devices by
which computers communicate with the outside
world. They are employed in a variety of applications from CRT display systems and voice synthesizers to automatic test systems. digitally controlled
attenuators. and process control actuators. In
addition. they are key components inside most AID
converters. D/A converters are also referred to as
DAC's and are termed decoders by communications
engineers.

TTL INPUT DATA

+vs

R,
+1.2V

The transfer function of an ideal3-bit D/A converter is shown in Figure 17. Each input code word
produces a single. discrete analog output value.
generally a voltage. Over the output range of the
converter 2 n different values are produced including
zero; and the output has a one-to-one correspondence
with input. which is not true for A/D converters.
There are many different circuit techniques used
to implement D/A converters. but a few popular
FS
/

, /"
'4FS
I::J
Q.

!

I::J

a

t!l

%FS

9
«

,
,/

Q

z

,,

;-

;-

,

,,

/

/

/

Figure 18. Weighted Current Source D/A Converter

/

"

The current sources are switched on or off from
standard TTL inputs by means of the control diodes
connected to each emitter. When the TTL input is
high the current source is on; when the input is
low it is off. with the current flowing through the
control diode. Fast switching speed is achieved
because there is direct control of the transistor
current. and the current sources never go into
saturation.
To interface with standard TTL levels. the current
sources are biased to a base voltage of + 1.2V. The
emitter currents are regulated to constant values
by means of the control amplifier and a precision
voltage reference circuit together with a bipolar
transistor.
The summed output currents from all current
sources that are on go to an operational amplifier
summing junction; the amplifier converts this output current into an output voltage. In some D/A

/

/

17

<:
%FS

/f

000

001

,,

010

011

100

101

110

",

INPUT CODE

Figure 17. Transfer Function ofldeal3-Bit D/A Converter

13

DATA ACQUISITION & CONVERSION HANDBOOK

converters the output current is used to directly
drive a resistor load for maximum speed. but the
positive output voltage in this case is limited
to about + 1 volt.
The weighted current source design has the advan·
tages of simplicity and high speed. Both PNP and
NPN transistor current sources can be used with
this technique !ilthough the TTL interfacing is more
difficult with NPN sources. This technique is used
in most monolithic. hybrid. and modular D/A converters in use today.
A difficulty in implementing higher resolution D/A
converter designs is that a wide range of emitter
resistors is required. and very high value resistors
cause problems with both temperature stability
and switching speed. To overcome these problems.
weighted current sources are used in identical
groups. with the output of each group divided down
by a resistor divider as shown in Figure 19.

The operation of the R-2R ladder network is based
on the binary division of current as it flows down
the ladder. Examination of the ladder configuration
reveals that at point A looking to the right. one
measures a resistance of 2R; therefore the reference
input to the ladder has a resistance of R. At the
reference input the current splits into two equal
parts since it sees equal resistances in either direction. Likewise. the current flowing down the ladder
to the right continues to divide into two equal parts
at each resistor junction.
The result is binary weighted currents flowing
down each shunt resistor in the ladder. The digitally
controlled switches direct the currents to either
the summing line or ground. Assuming all bits are
on as shown in the diagram. the output current is

1·

·2

·3

V OUT

Figure 20. R-2R Ladder D/A Converter
Figure 19. Current Dividing the Outputs of Weighted Current
Source Groups

lOUT

The resistor network. RI through R40 divides the
output of Group 3 down by a factor of 256 and the
output of Group 2 down by a factor of 16 with
respect to the output of Group 1. Each group is
identical. with four current sources of the type
shown in Figure 18. having binary current weights
of 1. 2. 4. 8. Figure 19 also illustrates the method
of achieving a bipolar output by deriving an offset
current from the reference circuit which is then
subtracted from the output current line through
resistor Ro. This current is set to exactly one half
the full scale output current.

=

V~F

[V2 + 14 + VB + ..... +

in]

which is a binary series. The sum of all currents
is then

where the 2- n term physically represents the portion
of the input current flowing through the 2R terminating resistor to ground at the far right.
As in the previous circuit. the output current summing line goes to an operational amplifier which
converts current to voltage.
The advantage of the R-2R ladder technique is that
only two values of resistors are required. with the
resultant ease of matching or trimming and excellent1emperature tracking. In addition. for high
speed applications relatively low resistor values
can be used. Excellent results can be obtained for
high resolution D/A converters by using lasertrimmed thin film resistor networks.

R-2R D/A Converter
A second popular technique for D/A conversion is
the R-2R ladder method. As shown in Figure 20. the
network consists of series resistors of value Rand
shunt resistors of value 2R. The bottom of each
shunt resistor has a single-pole double-throw
electronic switch which connects the resistor to
either ground or the output current summing line.

14

Multiplying and Deglitched D/A Converters
The R-2R ladder method is specifically used for
multiplying type D/A converters. With these
converters. the reference voltage can be varied over
the full range of ± Vmax with the output the product
of the reference voltage and the digital input word.
Multiplication can be performed in 1. 2. or 4 algebraic quadrants.

nique. This circuit, shown in Figure 22, uses equal
value switched current sources to drive the junctions of the R-2R ladder network. The advantage of
the equal value current sources is obvious since all
emitter resistors are identical and switching speeds
are also identical. This technique is used in many
ultra-high speed D/A converters.
One other specialized type D/A converter used
primarily in CRT display systems is the deglitched
D/A converter_ AIl D/A converters pt"oduce output
spikes. or glitches, which are most serious at the
major output transitions of \-it FS, 1/2 FS, and 3A FS
as illustrated in Figure 23(a).
Glitches"are caused by small time differences between some current sources turning off and others
turning on. Take. for example, the major code
transition at half scale from 0111 .... 1111 to 1000
.... 0000. Here the MSB current source turns on
while all other current sources turn off. The small
difference in switching times results in a narrow
half scale glitch. Such a glitch produces distorted
characters on CRT displays.

Figure 21. CMOS 14-Blt Multiplying D/A Converters

If the reference voltage is unipolar. the circuit is
a one-quadrant multiplying DAC; if it is bipolar. the
circuit is a two-quadrant multiplying DAC. For fourquadrant operation the two current summing lines
shown in Figure 20 must be subtracted from each
other by operational amplifiers.
In multiplying D/A converters. the electronic
switches are usually implemented with CMOS d"evices. Multiplying DAC's are commonly used in
automatic gain controls. CRT character generation,
complex function generators, digital attenuators.
and divider circuits. Figure 21 shows two 14-bit
multiplying CMOS D/A converters.

01

Glitches can be virtually eliminated by the circuit
shown in Figure 23(b). The digital input to a D/A
converter is controlled by an input register while
the converter output goes to a specially designed
sample·hold circuit. When the digital input is up·
dated by the register, the sample· hold is switched
into the hold mode. After the D/A has changed to
its new output value and all glitches have settled
out, the sample·hold is then switched back into the
tracking mode. When this happens, the output
changes smoothly from its previous value to the new
value with no glitches present.
Figure 24 shows a modular deglitched D/A converterwhich contains the circuitry just described.

+Vs

2"

VOUT

2"

2"

2"

(bl

Figure 23. Output Glitches (a) and Deglltched D/A Converter (b)

2"

Voltage Reference Circuits
Figure 22. D/A Converter Employing R-2R Ladder with Equal

An important circuit required in both AID and
D/A converters is the voltage reference. The accuracy and stability of a data converter ultimately
depends upon the reference; it must therefore produce a constant output voltage over both time
and temperature.

Value Switched Current Sources

Another important D/A converter design takes
advantage of the best features of both the weighted
current source technique and the R-2R ladder tech-

15

DATA ACQUISITION & CONVERSION HANDBOOK

higher than the 'reference voltage. It also generates
a constant, regulated current through the reference which is detemined by the three resistors.
Some monolithic AID and D/A converters use
another type of reference device known as the
bandgap reference. This circuit is based on the
principle of using the known, predictable base-toemitter voltage of a transistor to generate a constant voltage equal to the extrapolated bandgap
voltage of silicon. This reference gives excellent
results for the lower reference voltages of 1.2 or
2.5 volts.

Analog-To-Digital Converters
Counter Type AID Converter
Analog-to-digital converters, also called ADC's or
encoders, employ a variety of different circuit
techniques to implement the conversion function.
As with DIA converters, however, relatively few of
these circuits are widely used today. Of the various
techniques available, the choice depends on the
resolution and speed required.
One of the simplest AID converters is the coumer,
or servo, type. This circuit employs a digital
counter to control the input of a DIA converter.
Clock pulses are applied to the counter and the
output of the D/A is stepped up one LSB at a time.
A comparator compares the DIA output with the
analog input and stops the clock pulses when they
are equal. The counter output is then the converted
digital word.

Figure'24. Modular Deglitchad D/A Converter

The compensated zener reference diode with a
buffer-stabilizer circuit is commonly used in most
data converters today. Although the compensated
zener may be one of several types, the compensated
subsurface, or buried, zener is probably the best
choice. These new devices produce an avalanche
breakdown which occurs beneath the surface of the
silicon, I;esulting in better long-term stability and
noise characteristics than with earlier surface
breakdown zeners.
These reference devices have reverse breakdown
voltages of about 6.4 volts and consist of a forward
biased diode in series with the reversed biased
zener. Becausethe diodes have approximately equal
and opposite voltage changes with temperature, the
result is a temperature stable voltage. Available
devices have temperature coefficients from 100
ppm/°C to less than 1 ppm/°C.
Some of the new IC voltage references incorporate
active circuitry to buffer the device and reduce
its dynamic impedance; in addition, some contain
temperature regulation circuitry on the chip to
achieve ultra~low tempcos.

DIGITAl
OUTPUT
~-I--I-l-l-~-oDATA

TRACKI<>---~'=='==~=r)

HOLO

Figure 26. Tracking Type AID Converter

While this converter is simple, it is also relatively
slow. An improvement on this technique is shown in
Figure 26 and is known asa tracking AID converter, a device commonly used in control systems.
Here an up-down counter controls the DAC, and the
clock pulses are directed to the pertinent counter input depending on whether the D/A output must increase or decrease'to reach the analog input voltage.
The obvious advantage of the tracking AID converter is that it can continuously follow the input

Figure 25. A Precision, Bullerad Voltage Reference Circuit

A popular buffered reference circuit is shown in
Figure 25; this circuit produces an output voltage

16

signal and give updated digital output data if the
signal does not change too rapidly. Also, for small
input changes, the conversion can be quite fast. The
converter can be operated in either the track or
hold modes by a digital input control.

comparisons tlie digital outtmt of the SAR indicates
all those bits which remain on and produces the
desired digital code. The clock circuit controls the
timing of the SAR. Figure 28 shows the D/A converter output during a typical conversion.
The conversion efficiency of this technique means
that high resolution conversions can be made in very
short times. For example, it is possible to perform

Sucessive-Approximation AID Converte~
By far, the most popular AID conversion technique
in general use for moderate to high speed applications is the successive-approximation'type A/D.
This met)Jod falls into a class of techniques known
as/eedback type AID converters, to which the
counter type also belongs. In both cases a D/A
converter is in the feedback loop of a digital control
circuit which changes its ouput until it equals the
analog input. In the case of the successive-approximation converter, the DAC is controlled in an optimum manner to complete a conversion in just
n-steps, where n is the resolution of the converter
in bits.
The operation of this converter is analogous to
weighing an unknown on a laboratory balance scale
using standard weights in-a binary sequence such
as 1, Ih, v.t, Ih, ..... Yn kilograms. The correct procedure is to begin with the largest standard weight
and proceed in order down to the smallest one.
The largest weight is'placed on the balance pan
first;.if it does not tip, the weight is left on and the
next largest weight is added. If the balance does
tip, the weight is removed and the next one added.
The same procedure is used for the next largest
weight and so on down to the smallest. After the
nth standard weight has been tried and a decision
made, the weighing is finished. The total of the
standard weights remaining on the balance is the
closest possible approximation to the unknown.

OUTPUT CODE: 10110111

%FS

CLOCK PERIOD:

1

Figure 2B. DIA Output for B-Bit Successlva Approximation
Conversion

a 10 bit conversion in 1 jlSec. or less and a 12 bit
conversion in 2 jlSec. or less. Of course the speed
of the internal circuitry, in particular the D/A and
comparator, are critical for high speed performance.
The Parallel (Flash) AID Converter
For ultra-fast conversions required in video signal
processing and radar applications where up to 8 bits
resolution is required, a different technique is
employed; it is known as the parallel (a1so/lash, or
simultaneous) method and is illustrated in Figure 29.

ANAlOG
INPUT
.......--,----oOIGITA.L
OUTPUT
~~~~_ _~~DMA

311/2
R

Rgure 27. Successive Approximation AID Converter

R

In the successive-approximation A/D converter
illustrated in Fignre 27, a successive-approximation
register (SAR) controls the D/A converter by implementing the weighing logic just described. The
SAR first turns on the MSB of the DAC and the
comparator- tests this output against the analog
input. A decision is made by the comparator to
leave the bit on or turn it off after which bit 2 is
turned on and a second comparison made. After n-

R

BINARY
OUTPUT

RI2

Figure 29. 4-Bit Parallel AID Converter

17

DATA ACQUISITION & CONVERSION HANDBOOK

This circuit employs 2"-1 analog comparators to
directly implement the quantizer transfer function
of an AID converter.
The comparator trip-points are spaced 1 LSB apart
by the series resistor chain and voltage reference.
For a given analog input voltage all comparators
biased below the voltage turn on and all those biased
above it remain off. Since all comparators change
state simultaneously. the quantization process is
a one-step operation.
A second step is required. however. since the logic
output of the comparators is not in binary form.
Therefore an ultra-fast decoder circuit is employed
to make the logic conversion to binary. The parallel
technique reaches the ultimate in high speed because only two sequential operations are required
to make the conversion.
The limitation of the method. however. is in. the
large number of comparators required for even moderate resolutions. A 4-bit converter. for example.
requires only 15 comparators. but an 8-bit converter
needs 255. For this reason it is common practice
to implement an 8-bit AID with two 4-bit stages
as shown in Figure 30.

clock and counter. A number of variations exist
on the basic principle such as single-slope.
dual-slope. and triple-slope methods. In addition
there is another technique -completely differentwhich is known as the charge-balancing or quantized
feedback method.
The most popular of these methods are dual-slope
and charge-balancing; although both are slow. they
have excellent linearity characteristics with the
capability of rejecting input noise. B.ecause of these
characteristics. integrating type ND converters
are almost exclusively used in digital panel meters.
digital multimeters. and other slow measurement
applications.
C
INPUT

SWITCH

R

DIGITAL OUTPUT

Figure 31. Dual Slope AID Converter

Dual-Slope AID Conversion
BIT

The dual-slope technique. shown in Figure 31. is
perhaps best known. Conversion begins when the
unknown input voltage is switched to the integrator
input; at the same time the counter begins to count
clock pulses and counts up to overflow. At this
point the control circuit switches the integrator to
the negative reference voltage which is integrated
until the output is back to zero. Clock pulses are
counted during this time until the comparator
detects the zero crossing and turns them off.

1

OUTPUT DATA

Figure 30. Two-Stage Parallel S-Bil AID Converter

The result of the first 4-bit conversion is converted
back to analog by means of an ultra-fast 4-bit DIA
and then subtracted from the analog input. The
resulting residue is then converted by the second
4-bit AID. and the two sets of data are accumulated
in the 8-bit output register.
Converters of this type achieve 8-bit conversions
at rates of 20 MHz and higher. while single stage
4-bit conversions can reach 50 to 100 MHz rates.

FULL-SCALE
CONVERSION

Integrating :TYpe AID
Converters
Indirect AID Conversion
Another class of AID converters known as integrating type operates by an indirect conversion
method. The unknown input voltage is converted
into a time period which is then measured by a

Figure 32. Integrator Output Waveform for Dual Slope AID
Converter

18

The counter output is then the converted digital
word. Figure 32 shows the integrator output waveform where TI is a fixed time and T2 is a time
proportional to the input voltage. The times are
related as follows:
T2 = TI EIN

V,N Q--'\/VV-+---j

VREF

The digital output word therefore represents the
ratio of the input voltage to the reference.
Dual-slope conversion has several important features. First, conversion accuracy is independent of
the stability of the clock and integrating capacitor
so long as they are constant during the conversion
period. Accuracy depends only on the reference
accuracy and the integrator circuit linearity. Second,
the noise- rejection of the converter can be infinite
if T} is set to equal the period of the noise. To
reject 00 Hz power noise therefore requires that
TI be 1ll.007 msec. Figure 33 shows digital panel
meters which employ dual slope AID converters.

DIGITAL
OUTPUT

Figure 34. Charge-Balancing AID Converter

The pulse output controls switch 81 which connects
R2 to the negative reference for the duration of the
pulse. During this time a pulse of current flows out
of the integrator summing junction, producing a fast,
positive ramp at the integrator output. This process
is repeated, generating a train of current pulses
which exactly balances the input current-hence
the name charge balancing. This balance has the
following relationship:
~
f =

1

-

T

V IN
-_.
VREF

R2
R}

where T is the pulse width and f the frequency.
A higher input voltage therefore causes the integrator to ramp up and down faster, producing
higher frequency output pulses. The timer circuit
sets a fixed time period for counting. Like the dualslope converter, the circuit also integrates input
noise, and if the timer is synchronized with the
noise frequency, infinite rejection results. Figure
35 shows the noise rejection characteristic of all
integrating type AID converters with rejection
plotted against the ratio of integration period to
noise period.

Figure 33. Digital Panel Meters Which Employ Dual Slope
AID Converters

Charge-Balancing AID Conversion
The charge-balancing, or quantized feedback,
method of conversion is based on the principle of
generating a pulse train with frequency proportional to the input voltage and then counting the
pulses for a fixed period of time. This circuit is
shown in Figure 34. Except for the counter and
timer, the circuit is a voltage-to-frequency (V/F)
converter which generates an output pulse rate
proportional to input voltage.
The circuit operates as follows. A positive input
voltage causes a current to flow into the operational
integrator through RI. This current is integrated,
producing a negative going ramp at the output.
Each time the ramp crosses zero the comparator
output triggers a precision pulse generator which
puts out a constant width pulse.

19

.,
0

z·

20

...

Q

1rl
;;J
a:
w

If)

0
z

10

TIT n

Figure 35. Noise Rejection for Integrating Type AID
Converters

DATA ACQUISITION & CONVERSION HANDBOOK

Analog Multiplexers

with standard TTL inputs and drives the multiplexer switches with the proper control voltages.
For the 8-channel analog multiplexer shown, a oneof-eight decoder circuit is used.
Most analog multiplexers today employ the CMOS
switch circuit shown in Figure 37. A CMOS driver
controls the gates of parallel-connected P-channel
and N-channel MOSFET's. Both switches turn on
together with the parallel connection giving relatively uniform on-resistance over the required analog input voltage range. The resulting on-resistance
may vary from about 50 ohms to 2K ohms depending
on the multiplexer; this resistance increases with
temperature. A representative group of monolithic
CMOS analog multiplexers is shown in Figure 38.

Analog Multiplexer Operation
Analog multiplexers are the circuits that time-share
an AID converter among a number of different
analog channels. Since the AID converter in many
cases is the most expensive component in a data
acquisition system, multiplexing analog inputs to
the AID is an economical approach. Usually the
analog multiplexer operates into a sample-hold
circuit which holds the required analog voltage long
enough for AID conversion.

A,

A2

A3

iii) n.,.

EN. ON-CHAN

..

"-""

,r

I

XXXONONE

o
o

0

0

#

0

'$

$ f f! if

$",,.:

A1 A2'A3
CHANNEL ADDRESS

Figure 36. Analog Multiplexer Circuit
Figure 38. A Group of Monolithic CMOS Analog Multiplexers

As shown in Figure 36, an analog multiplexer consists of an array of parallel electronic switches
connected to a common output line. Only one switch
is turned on at a time. Popular switch configurations
include 4, 8, and 16 channels which are connected
in single (single-ended) or dual (differential)
configurations.
.
The multiplexer also contains a decoder-driver circuit which decodes a binary input word and turns
on the appropriate switch. This circuit interfaces

Analog Multiplexer Characteristics
Because of the series resistance, it is common practice to operate an analog multiplexer into a very
high load resistance such as the input of a unity
gain buffer amplifier shown in the diagram. The
load impedance must be large compared with the
switch on-resistance and any series source resistance in order to maintain high transfer accuracy.
Transfer error is the input to output error of the
multiplexer with the source and load connected;
error is expressed as a percent of input voltage.
Transfer errors of 0.1 % to 0.01% or less are required
in most data acquisition systems. This is readily
achieved by using operational amplifier buffers
with typical input impedances from 10 8 to 10 12
ohms. Many sample-hold circuits also have very
high input impedances.
Another important characteristic of analog mul tiplexers is break-before-make switching. There is
a small time delay between disconnection from the
previous channel and connection to the next channel
which assures that two adjacent input channels are

r--------<>IN

'--__+ __--<: OUT

Figure 37. CMOS Analog Switch Circuit

20

the effects of noise on the signal during the remaining analog processing. In low-level multiplexing
the signal is amplified after multiplexing; therefore
great care must be exercised in handling the lowlevel signal up to the multiplexer. Low-level multiplexers generally use two-wire differential switches
in order to minimize noise pick-up. Reed relays,
because of essentially zero series resistance and
absence of switching spikes. are frequently employed in low-level multiplexing systems. They are
also useful for high common-mode voltages.
A useful specialized analog multiplexer is the/lyingcapacitor type, This circuit. shown as a single channel in Figure 40 has differential inputs and is particularly useful with high common-mode voltages.
The capacitor connects first to the differential
analog input, charging up to the input voltage. and
is then switched to the differential output which
goes to a high input impedance instrumentation
amplifier. The differential signal is therefore transferred to the amplifier input without the common
mode voltage and is then further processed up to
AID conversion.
In order to realize large numbers of multiplexed
channels. you can connect analog multiplexers in
parallel using the enable input to control each device.
This is called single-level multiplexing. You can
also connect the output of several multiplexers to
the inputs of another to expand the number of
channels; this method is double-level multiplexing.

never instantaneously connected together.
Settling time is another important specification for
analog multiplexers; it is the same definition
previously given for amplifiers except that it is
measured from the time the channel is switched on.
Throughput rate is the highest rate at which a
multiplexer can switch from channel to channel
with the output settling to its specified accuracy.
Crpsstalk is the ratio of output voltage to input
voltage with all channels connected in parallel and
off; it is generally expressed as an input to O)ltput
attenuation ratio in dB.
As shown in the representative equivalent circuit of
Figure 39. analog multiplexer switches have a

Figure 39. Equivalent Circuit 01 Analog Multiplexer Switch

number of leakage currents and capacitances as·
sociated with their operation. These parameters
are specified on data sheets and must be considered
in the operation of the devices. Leakage currents.
generally in picoamperes at room temperature.
become trou~lesome only at high temperatures.
Capacitances affect crosstalk and settling time
of the multiplexer.

Sample-Hold Circuits
Operation of Sample-Holds
Sample-hold circuits. discussed earlier, are the
devices which store analog information and reduce
the aperture time of an AID converter. A samplehold is simply a voltage-memory device in which
an input voltage is acquired and then stored on a
high quality capacitor. A popular circuit is shown
in Figure 41.

Analog Multiplexer Applications
Analog multiplexers are employed in two basic types
of operation: high-level and low-level. In high-lel'el
multiplexing, the most popular type, the analog
signal is amplified to the 1 to 10V range ahead of
the multiplexer. This has the advantage of reducing

~F-:
Ti

INPUT

aUT

±
C

SWITCH
DRIVER

a

OUTPUT

0

SAMPLE
CONTROL

Figure 41. Popular Sample-Hold Circuit

Al is an input buffer amplifier with a high input
impedance so that the source, which may be an

Figure 40. Flying Capacitor Multiplexer Switch

21

DATA ACQUISITION & CONVERSION HANDBOOK

analog multiplexer, is not loaded. The output of AJ
must be capable of driving the hold capacitor with
stability and enough drive current to charge it
rapidly. S) Is an electronic switch, generally an
FET, which is rapidly switched on or off by a driver
circuit which interfaces with TTL inputs.
C is a capacitor with low leakage and low dielectric
absorption characteristics; it is a polystyrene,
polycarbonate, polypropylene, or teflon type. In the
case of hybrid sample· holds, the MOS type capacitor
is frequently used.
At is the output amplifier which buffers the voltage
on the hold capacitor. It must therefore have ex·
tremely low input bias current, al\d for this reason
an FET input amplifier is required.
There are two modes of operation for a samplehold: sample (or tracking) mode, when the switch
is closed; and hold mode, when the switch is open.
Sample-holds are usually operated in one of two
basic ways. The device can continuously track the
input signal and be switched into the hold mode
only at certain specified times, spending most of
the time in tracking mode. This is the case for a
sample-hold employed as a deglitcher at the output
of a DIA converter, for example.
Alternatively, the device can stay in the hold mode
most of the time and go to the sample mode just
to acquire a new input signal level. This is the case
for a sample-hold used in a data acquisition system
following the multiplexer.

between samples, providing data smoothing.
As with other filter circuits, the gain and phase
components of the transfer function are of interest.
By an analysis based on the impulse response of a
sample-hold and use of the Laplace transform, the
transfer fu nction is found to be

G.IO

~t

rinrrlL~

l;- (::rJ"'''.

where fs is the sampling frequency. This function
contains the familiar (sin x) Ix term plus a phase
term, both of which are plotted in Figure 42.
The sample-hold is therefore a low pass filter with
a cut-off frequency slightly less than fs/2 and a
linear phase response which results in a constant
delay time of T/2, where T is the time between
samples. Notice that the gain function also has significant response lobes beyond fs. For this reason a
sample-hold reconstruction filter is frequently followed by another conventional low pass filter.
Other Sample-Hold Circuits
In addition to the basic circuit of Fignre 41, there
are several other sample-hold circuit configurations
which are frequently used. Figure 43 shows two
such circuits which are closed loop circuits as contrasted with the open loop circuit of Figure 41.
Figure 43(a) uses an operational integrator and
another amplifier to make a fast, accurate inverting
sample-hold. A buffer amplifier is sometimes added
in front of this circuit to give high input impedance.
Figure 43(b) shows a high input impedance noninverting sample-hold circuit.

The Sample-Hold as a Data Recovery Filter
.a common application for sample-hold circuits is
data recovery, or signal reconstruction./ilters. The
problem is to reconstruct a train of analog samples
into the original signal; when used as a recovery
filter, the sample-hold is known as a zero-order hold.
It is a useful filter because it fills in the space

.
1

INPUT

OUTPUT

,.,

OUTPUT

i
~

I
_________ 1
I _______ _

-1.

-3.

I

I

Figure 43. Two Closed Loop Sample-Hold Circuits

_________ lI __________1I _______ _

The circuit in Figure 41, although generally not as
accurate as those in Figure 43, can be used with a

Figure 42. Gain and Phase Components 01 Zero-Order
Hold Transfer Function

22

diode-bridge switch to realize ultra-fast acquisition
sample-holds, such as those shown in Figure 44.

mode to the hold mode, with a constant input voltage. It is caused by the switch transferring charge
onto the hold capacitor as it turns off.
Aperture delay is the time elapsed from the hold
command to when the switch actually opens; it is
generally much less than a microsecond. Aperture
uncertainty (or aperture jitter) is the time variation,
from sample to sample, of the aperture delay. It is
the limit on how precise is the point in time of
opening the switch. Aperture uncertainty is the
time used to determine the aperture error due to
rate of change of the input signal. Several of the
above specifications are illustrated in the diagram
of Figure 45.
Sample-hold circuits are simple in concept, but
generally difficult to fully understand and apply.
Their operation is full of subtleties, and they must
therefore be carefully selected and then tested in a
gi ven application.

Figure 44. Ultra-Fast Sample-Hold Modules Which Employ
Diode-Bridge Switches

Specification of Data
Converters

Sample-Hold Characteristics

A number of parameters are important in characterizing sample-hold performance. Probably most
important of these is acquisition time. The definition
is similar to that of settling time for an amplifier.
It is the time required, after the sample-command
is given, for the hold capacitor to charge to a fullscale voltage change and remain within a specified
error band around final value.
Several hold-mode specifications are also important.
Hold-mode droop is the output voltage change per
unit time when the sample switch is open. This
droop is caused by the leakage currents of the capacitor and switch, and the output amplifier bias current. Hold-mode feed through is the percentage of
input signal transferred to the output when the
sample switch is open. It is measured with a sinusoidal input signal and caused by capacitive coupling.
The most critical phase of sample-hold operation is
the transition from the sample mode to the hold
mode. Several important parameters characterize
this transition. Sample-to-hold offset (or step) error
is the change in output voltage from the sample

/

/

,
1\

/

Ideal vs. Real Data Converters

Real AID and 0/A converters do not have the ideal
transfer functions discussed earlier. There are
three basic departures from the ideal: offset, gain,
and linearity errors. These errors are all present
at the same time in a converter; in addition they
change with both time and temperature.
1111

1111

1000

1000

0000 I!....<<--_-'-_ _- '

o

'hFS

lal

0000L-____

~

______

IIFS
Ibl

/

SAMPlE-lO-HOLD

HOLD·MODE
DROOP

t'FFSET
-----------

t

--

II
I I

----l

:-APERTURE

\ I

DELAY

I
I

SAMPlE~+---_ _-i'
CONTROL

TRACK---!-----HOLD-----

Figure 46. OHset (al, Gain (bl, and Linearity (cl Errors for
an AID Converter

Figure 45. Some Sample-Hold Characteristics

23

~

FS

DATA ACQUISITION & CONVERSION HANDBOOK

Figure 46 shows AID converter transfer functions
which illustrate the three error types. Figure 46(a)
shows offset error. the analog error by which the
transfer function fails to pass through zero. Next.
in Figure 46(b) is gain error. also called scale factor
error; it is the difference in slope between the actual
transfer function and the ideal. expressed as a
percent of analog magnitude.
In Figure 46(c) linearity error. or nonlinearity. is
shown; this is defined as the maximum deviation of
the actual transfer function from the ideal straight
line at any point along the function. It is expressed
as a percent of full scale or in LSB size. such as
±lhLSB. and assumes that offset and gain errors
have been adjusted to zero.
Most AID and DIA converters available today have
provision for external trimming of offset and gain
errors. By careful adjustment these two errors can
be reduced to zero. at least at ambient temperature.
Linearity error. on the other hand. is the remaining
error that cannot be adjusted out and is an inherent
characteristic of the converter.

entiallinearities can be thought of as macro and
micro-linearities. respectively.
FS

110

':;
I!:

1001

~

1000

:l

I-

101

~'00

.FS

::0

5

0011
010
001

000
000

100

lHS

111

INPUT
I.,

FS

INPUT

'b,

Figure 48. Nonmonolonic DIA .Converter (a) and AID
Converter wllh Missing Code (b)

Two other important data converter characteristics
are closely related to the differential linearity
specification. The first is mono tonicity. which applies to DIA converters. Monotonicity is the characteristic whereby the output of a circuit is a continuously increasing function of the input. Figure
48(a) shows a nonmonotonic DIA converter output
where. ·at one point. the output decreases as the
input" increases. A DIA converter may go non monotonic if its differential linearity error exceeds 1
LSB; if it is always less than 1 LSB. it assures that
the device will be monotonic.
The term missing code. or skipped code. applies to
AID converters. If the differential linearity error
of an AID converter exceeds 1 LSB. its output can
miss a code as shown in Figure 48(b). On the other
hand. if the differential linearity error is always
less than 1 LSB. this assures that the converter
will not miss any codes. Missing codes are the result
of the AID converter's internal DIA converter
becoming nonmonotonic.
For AID converters the character of the linearity
error depends on the technique of conversion.
Figure 49(a). for example. shows the linearity

10'1

...

,/
111

Data Converter Error Characteristics
Basically there are only two ways to reduce linearity
error in a IPven application. First. a better quality
higher cost converter with smaller linearity error
can be procured. Second. a computer or microprocessor can be programmed to perform error
correction on the converter. Both alternatives may
be expensive in terms of hardware or software cost.

~
0
u

/

0

0111

Figure 47. Defining DiHerenllal Linearity Error
1111

1111

The linearity error discussed above is actually more
precisely termed integraiiinean·ty error. Another
important type of linearity error is known as differentiallinearity error. This is defined as the
maximum amount of deviation·of any quantum (or
LSB change) in the entire transfer function from its
ideal size of FSR/2". Figure 47 shows that the
actual quantum size may be larger or smaller than
the ideal; for example. a converter with a maximum
differential linearity error of ± '2 LSB can have a
quantum size between '·2LSB and 1'2LSB anywhere
in its tranfer function. In other words. any given
analog step size is (l±' 2) LSB. Integraland differ-

':;

~ 1000

5
0000 L-____

~L-

Y2F5
INPUT

(0,

____

~

FS

0000 "'-______L-____
YrF5
INPUT

,b,

Figure 49. Linearily Characlerlsllcs of Inlegrallng (a) and
Successive Approximalion (b) AID Converters

24

~

FS

characteristic of an integrating type AID converter.
The transfer function exhibits a smooth curvature
between zero and full scale. The predominant type
of error is integral linearity error, while differential
linearity error is virtually nonexistent.
Figure 49(b), on the other hand, shows the linearity
characteristic of a successive approximation AID
converter; in this case differential linearity error
is the predominant type, and the largest errors
occur at the specific transitions at 1/2, Y4, and ¥t scale.
This result is caused by the internal DIA converter
nonlinearity; the weight of the MSB and bit 2 current sources is critical in relation to all the other
weighted current sources in' order to achieve ±Ih
LSB maximum differential linearity error.
Temperature Effects
Ambient temperature change influences the offset,
gain, and linearity errors of a data converter. These
changes over temperature are normally specified
in ppm of full scale range per degree Celsius. When
operating a converter over significant temperature
change, the effect on accuracy must be carefully
determined. Of key importance is whether the
device remains monotonic, or has no missing codes,
over the temperatures of concern. In many cases
the total error change must be computed, i.e., the
sum of offset, gain, and linearity errors due to
temperature.
The characteristic of monotonicity, or no missing
codes, over a .given temperature change can be
readily computed from the differential linearity
tempco specified for a data converter. Assuming the
converter initially has 1. 2 LSB of differential
linearity error, the change in temperature for an
increase to 1 LSB is therefore
2- n x 10"
~T= 2DLT
where n is the converter resolution in bits and DLT
is the specified differential linearity tempco in ppm
of FSR/oC. aT is the maximum change in amhient
temperature which assures that the converter will
remain monotonic, or have no missing codes.

Selection of Data Converters
One must keep in mind a number of important
considerations in selecting AID or DIA converters.

An organized approach to selection suggests
drawing up a checklist of required characteristics.
An initial checklist should include the following
key items:
1. Converter type
2. Resolution
3. Speed
4. Temperature coefficient
After the choice has been narrowed by these considerations, a number of other parameters must be
considered. Among these are analog signal range,
type of coding, input impedance, power supply
requirements, digital interface required, linearity
error, output current drive, type of start and status
signals for an AID, power supply rejection, size,
and weight. One should list these parameters in
order of importance to efficiently organize the
selection process.

,
I
I

I
I
I

:I

I
I

-25Cto +85CI-13Fto + 18SFI

\r--~------------TLl,
MILITARY

I

V

_!5C

I

I

;,

L

to +- 125C r - 67F 10 + 2S:7Fl :

~3~UMATION f\,r---r----.,.:--------------;--r------,
WATER

*

POINT lORY ICEI I
!

-75

:,

-so

-25

WATER

I

FRE;ZES

:.
25

50

I

~

I
I

BOILS

t

1

100

125

TEMPERATURE, OEGReES CelSIUS

Figure 50. Standard Operating Temperature Ranges for
Qals Converler.

In addition, the required operating temperature
range msut be determined; data converters are
normally specified for one of three basic ranges
known in the industry as commercial, industrial,
or military. These temperature ranges are illustrated in Figure 50. Further, the level of reliability must be determined in terms of a standard
device, a specially screened device, or a military
standard 883 device.
And finally, not to be forgotten are those important
specifications, price and delivery, to which the
reputation of the manufacturer must be added.
GZ

25

26

2. AID and

D/A Converters

27

28

DATA ACQUISITION lit CONVERSION HANDBOOK

SELECTING AID CONVERTERS

One of the popular pastimes of the nineteen sixties was to
predict the explosive growth of digital data processing,
fed by the newly-developed semiconductor MSI circuits,
and the subsequent demise of analog circuitry. The first
part of this prediction has certainly come true- the advent
of the microprocessor has caused, and will continue to
cause, a revolution in digital processing which was
unthinkable 10 years ago. Butlar from causing the demise
of analog systems, the reverse has occurred. Nearly all the
data being processed (with the notable exception of
financial data) consists of physical parameters of an
analog nature - pressure, temperature, velocity, light
intensity and acceleration to name but a few. In every
instance this analog information must be converted into
its digital equivalent, using some form of AID converter.
Converter products are thus assuming a key role in the
realization of data acquisition systems.
I ncreased use of microprocessors has also causea
dramatic cost reductions in the digital components of a
typical system. The $8000 mini-computer of a few years
ago is being replaced by a $475 dedicated microprocessor board. This trend is also being reflected in the analog
components. No longer is it possible to justify buying a
$400 data acquisition module when a dedicated sy.stem,
adequate for the task under consideration, can be put
together for $50.
Thus many engineers, who in the past have had limited
exposure to analog circuitry, are having to come to grips
with the characteristics of AID converters, sample &
holds, multiplexers and operational amplifiers. Contrary
to the propaganda put out by many of the specialty
module houses, there is nothing mysterious about these
components or the way they interface with one another.
Now that many of them are available as one or two chip
MSI circuits, a block diagram may be turned into a
working piece of hardware with relative ease.
The purpose of this note is to compare and contrast the
more popular AID designs, and provide the reader with
sufficient information to select the most appropriate
converter for his or her needs.

THE IMPORTANT PARAMETERS

be a high speed successive approximation
design.
Ca•• 2: A semiconductor engineer is measuring the
'thermal profile' of a furnace. It is necessary to
make measurements accurate to a few tenths of
a degree Centigrade, which is equivalent to a
few microvolts of thermocouple output.
Sampling rates of a few readings per second are
adequate and costs should be kept low. The
integrating ('dual slope', 'triphasic', 'quad
slope', depending on which manufacturer you
go to) AID is the only type capable of the
required precisionlcost combination. It has the
added advantage of maintaining accuracy in a
noisy environment.
Cas. 3: A businessman is talking to his sales office in
Rome. Assuming the phone company is not on
strike, his voice will be sampled ata 10KHz rate,
or thereabouts, in order not to lose information
in the audio frequency range up to 5KHz. This
requires a medium accuracy (8 bit) AID with a
cycle time of 100 microseconds or less. In this
application the integrating type is not fast
enough, so it is necessary to use a slow (forthis
approach) successive approximation design.
These examples serve to introduce both the two most
popular conversion techniques (successive approximation and integrating) and the three key parameters of a
converter, i.e. speed, accuracy and cost. In fact the first
choice in selecting an AID is between successive
approximation and integrating, since greater than 95% of
all converters fall into one of these two categories.
If we look at the whole gamut of available converters, with
conversion speeds ranging from 100 ms to less than IllS,
we see that these two design approaches diliide the speed
spectrum into two groups with almost no overlap. (Table
1) However, before making a selection solely on the basis
of speed, it is important to have an understanding of how
the converters work, and how the data sheet specifications relate to the circuit operation.
TABLE 1

Let's begin by taking a look at some actual systems, since
this will illustrate the diversity of performance required of
A-to-D converters.
Ca•• 1: A seismic recording truck is situated over a
potential natural gas site. Some 32 recording
devices are laid out over the surrounding area.
An explosive charge is detonated and in a
matter of seconds it is all over. During that time
it is necessary to scan each recorder every 100
microseconds. Speed is clearly the most important requirement. In this instance, 12 bit
accuracy is not required; and, since the truck
contains many thousands of dollars of electronics, cost is not a critical parameter. The AID will

Type of
converter

Relative

speed

Conversion time
10 bltl 12 bHl 18 bill

40 ms 250 ms

20 ms

30 ms

, ms
0.3 ms

5 ms
, ms

20 ms
5 ms

-

general
purpose
successive high per-

3O.s

40",5

50.s

-

formance

10lls

15,u5

20.s

400,"5

5.s
2.s
0.8.s

10",s

12,u5

4.s
'.s

6.s
2.s

slow
integrating medium

fast

approximation

fast

high speed
ultra-fast

29

8 bR,

--

THE INTEGRATING CONVERTER
Summary 01 Characteristics
As the name implies, the output of an integrating
converter represents the integral or average value of an
input voltage over a fixed period of time. A sample-andhold circui\, therefore, is not required to freeze the input
during the measurement period, and noise rejection is
excellent. Equally important, the linearity error of integrating converters is small since they use time to quantize
the answer - it is relatively easy to hold short-term clock
jilter to better than 1 in 10'.
The most popular integrating converter uses the dualslope principle, a detailed description of which is given in
Ref.1.
lis advanlages and disadvanlages may be summarized as
follows:
Advantages:
Inherent accuracy
Non-critical components
Excellent noise rejection
No sample & hold required
low cost
No missing codes

PHASE

,--t-- PHASE II~_- PHASE 111---

AUTO ZERO

II

SIGNAL
INTEGRATE

I
I
I
I

II

TG.
REFERENCE IN E RAT

I
I
I

I
I
I
hnnn --~-----iLnUrL
.. ___ f~"::
I
y
10,000 CLOCK

10,000 CLOCK

UP TO 20,000

PULSES

PULSES

CLOCK PULSES

Figure 1: 4'1\ Digit AID Converter Timing Diagram (8052A/7103A)

THE SUCCESSIVE APPROXIMATION CONVERTER
How il works,
The heart of the successive approximation AID is a
digital-to-analog converter (DAC) in a feedback loop with
a comparator and some clever logic referred to as a'successive approximation register' (SAR). Fig 2 shows a
typical system. The DAC output is compared with the
analog input, progressing from the most significant bit
(MSB) to the least significant bit (lSB) one bit at a time.
The bit in question is set to one. II the DAC output is less
than the input, the bit in question is left at one. II the DAC
output is greater than the input, the bit is set to zero. The
register then moves on to the next bit. At the completion of
the conversion, those bits left in the one state cause a
current to flow at the output of the DAC which should
match liN within ± 'h lSB. Performing an 'n' bit conversion requires only 'n' trials, making the technique capable
of high ·speed conversion.

Disadvantages:
low speed (typically 3 to 100
readings/sec)
In a practical circuit, the primary errors (other than
reference drift) are caused by the non-ideal characteristics of analog switches and capacitors. I n the former,
leakage and charge injection are the main culprits; in the
lalter, dielectric absorption is a source of error. All these
factors are discussed at length in Ref. 1.
A well-designed dual slope circuit such as Intersil's
8052A/7103A is capable of 4'h digit performance (± 1 in
:!: 20,000) with no critical tweaks or close tolerance
components other Ihan a stable reference.
Timing Considerations
In a typical circuit, such as the 8052A17103A referred to
above, the conversilin takes place in three phases as
shown in Fig 1. Note that the input is actually integrated or
averaged over a period of 10,000 clock pulses (or83.3 ms
with a 120 KHz clock) within a conversion cycle of 40,000
clock pulses in toto. Also note that the actual business of
looking althe input signal does not begin for 10,000 clock
pulses, since the circuit first goes into an auto-zero mode.
For a 3V, digit product, such as the 7101 or 7103, the
measurement period is 1000 clock pulses (or 8.33 ms with
a 120 KHz clock).
These timing characteristics give the dual slope circuit
both its strengths and its weaknesses. By making the
signal integrate period an integral number of line
frequency periods, excellent 60Hz noise rejection can be
obtained. And of course .integrating the input Signal for
several milliseconds smoothes out the ellect of high
frequency noise.
But in many applications such as transient analysis or
sampling high frequency waveforms, averaging the input
over several milliseconds is totally unacceptable. It is of
course feaSible to use a sample & hold at the input, but the
majority of systems that demand a short measurement
window also require nigh speed conversions.

=j.w
Figure 2: Successive Approximation NO Converter
The advantages and disadvantages of successive approximation converters may be summarized as follows:
Advantages:
Hi Speed
(Typically 100,000 conversions/sec)

30

DATA ACQUISITION & CONVERSION HANDBOOK

never deviates by more than ± 'h LSB from where it
should be. That's a good spec., but note that gain and
offset errors have been adjusted prior to making the
measurement. Over a finite temperature range, the
temperature coefficients of gain and offset must be taken
into account.
The differential non-linearity of ± 'h LSB maximum is also
guaranteed over temperature: this ensures that there are
no missing codes.
The gain temperature coefficient is 10 ppm of FSR per 'C,
or 0.001 % per' C. Now 1 LSB in a 10 bit system is 1 part in
1024, or approximately 0.1%. So a 50'C temperature
change from the temperature at which the gain was
adjusted (i.e. from +25'C to +75'C) could give rise to ±'h
LSB error. This error is separate from, and in the limit
could add to, the relative accuracy spec.
The offset temperature coefficient of 20 ppm per 'C give
rise to ± 1 LSB error (over a +25'Cto+75'C range) by the
same reasoning applied to the gain tempco. The
reference contributes an error in direct proportion to its
percentage change over the operating temperature
range.
We can summarize the effect of the major error sources:
Relative Accuracy
± 'h LSB or ± .05%
Gain Temp. Coefficient
± 'h LSB or ± .05%
OffsetTemp.Coefficient
± 1 LSB or ± 0.1%
A straight forward RMS summation shows that the AID is
10 bits ± 1 v. LSB over aO'C to +75'C temperature range.
However it is over-optimistic to RMS errors with such a
small number of variables, and yet we do know that the
error cannot exceed ± 2 LSB. A realistic estimate might
place the accuracy at 10 bits ± 1'h LSB.
Timing Considerations
The 2502/2503/2504 successive approximation register is
now used in the majority of high speed AID converters
and the timing diagram shown in Fig. 3 is taken from the

Disadvantages:
Several critical components
Can have missing codes
Requires sample and hold
Difficult to auto-zero
High cost
Error Sources
The error source in the successive approximation converter are more numerous than in the integrating type,
with contributions from both the DAC and the comparator. The DAC generally relies on a resistor ladder and
current or voltage switches to achieve quantization. Maintaining the correct impedance ratios over the operating
temperature range is much more difficult than maintaining clock pulse uniformity in an integrating converter.
The data sheet for a hypothetical AID might contain the
following accuracy related specifications:

Resolution
Quantization Uncertainty:
Relative Accuracy
Differential Non Linearity:
Gain Error
Gain Temp. Coeff.
Offset Error
Offset Temp. Coeff.

10 Bits
± 'h LSB
± 'h LSB
± 'h LSB
Adjustable to zero at 25' C
± 10 ppm of Full Scale
Reading I'C
Adjustable to zero at 25'C
± 20 ppm of Full Scale
Reading I'C

Now, referring to the definition of terms on page 6, what
does this tell us about the product? First of all, being told
that the quantization uncertainty is ± 'h LSB is like being
told that binary numbers are comprised of ones and zeros
- it's part of the system. The relative accuracy of ± 'h LSB,
guaranteed over the temperature range, tells us that after
removing gain and offset errors, the transfer fun~tion

.

"

.

"

"

"

.

"

"

It

CLOCK

DATA - ' - _ - - - " ' - _ - '

OUTPUTS

Q.=::J
Q,=::J
Q.=::J
Q,=::J
Q,=::J
Q,=::J
Q.=::J
CO~ci~:~~~~ =::J
SERIAL DATA

OUT·

I

TRY B6

E

BIT 6 DECISION

I TRY 85 I.. BIT 5 DECISION
I TRY 84 I... BIT 4 DECISION

I TRY 83 I... BIT 3 DECISION
I TRY 82 I... BIT 2 DECI!ION

I TRY 81 I... liT 1 DECISION
I TAY Lsa!"'LSB DECISION

.l-._ _'-_--I__...J

'FOR PURPOSES OF ILLUSTRATION. SERIAL DATA OUT WAVEFORM SHOWN FOR 01010101.

Figure 3: Typical Timing Diagram for Successive Approximation Converter

31

2502 data sheet. However all successive approximation
converters have essentially similar timing characteristics.
Holding the start input Low for at least a clock period
initiates the conversion. The MSB is set low and all the
other bits high for the first trial. Each trial takes one clock
period, proceeding from the MSB to theLSB. Note that, i'n
contrast to the integrating converter, a serial output arises
naturally from this conversion technique.
Although the successive approximation AID is capable of
very high conversion speeds, there is an important limitation on the slew rate of the input signal. Unlike integrating designs, no averaging of the input signal takes
place. To maintain accuracy to 10 bits, for example, the
input should not change by morethan ± 'h LSB during the
conversion period. Fig 4(a) shows maximum allowable
dV/dt as a function of sampling (or aperture) time for
various conversion resolutions. Now for a sinusoidal
waveform represented by Esin wt, the maximum rate of
change of voltage':'el.:.t is 2"fE.The amplitude of one 'h
LSB is E/2 n , since the pk-pk amplitude is 2E. So the
change in input amplitude.:.e is given by:
':'e = E/2 n = 2" fE':'T ,where':' T = conversion time

PERCENT ERROR

38.8 13.5 5.0
100

..

~

.
..
..

.03 .012 .0045

I

I.
JL

50

IZ

40

U
a;

30

'"

-

'~~~~T:

VILsa IN_
10 BITS

I

I

t--

'12 LSB IN

BBITS

!

20

l

10

I
3
NUMBER OF TIME CONSTANTS

~

Figure 5: Voltage across a capacitor (as % of final value) as a
function of time (# of time constants)

CONVERTER CHECKLIST
I n selecting a converter for a specific application, it will be
helpful to go through the following checklist, matching
required performance against data sheet guarantees:
a) How many bits?
b) What is total error budget over the temperature
range?
c) What is full scale reading and magnitude of LSB?
Make sure that the 95% noise is substantially less than
the magnitude of the LSB. If no noise specifications
are given, assume that the omission is intentional!
d) What input characteristics are required?
With most successive approximation converters, the
input resistance is low (= 5K II) since one is looking
into the comparator summing junction. In a well
designed dual slope circuit, there should be a high
input resistance buffer (R in = 10"!!) included within
the auto-zero loop. However in some designs
(Teledyne 8700, Analog Devices AD7550) the input
looks directly into the integrating resistor (1 Mil).
e) What. aperture time (or measurement window) is
required?
If an 'averaged value of the input signal (over some
milliseconds) is acceptable, use an integrating
converter. Refer to Fig. 4 for systems where an
averaged value of the input is not acceptable.
Remember most successive approximation systems
rely on a sample & hold to 'freeze' the input while the
conversion is taking place. Thus the sample & hold
characteristics should be matched to the input signal
slew rate, and the AID converter characteristics
matched to the required conversion rate.
f) What measurement frequency is required?
This will determine the maximum allowable
conversion time (including auto-zero time for integrating types).
g) Is microprocessor compatibility important?
Some AID's interface easily with microprocessors;
others do not. Ref. 2 explores the microprocessor
interface in considerable depth.

t

~ 100 AS

10ns

n.

-"

I.)

II

70

0

~

0.1 O~V!::'~:::-"""";;;.V"';=~:--""Vf,."'.
1V/ms
D.lV/.. _
10Y/...
RATE OF CHANGE (aYfdll

.09

I

80

~ 60

~

;

1

.25

~

:>

I

~

.67

90

fmax = 2,,':'T2n

~

1..

, , , , "

SINUSOIDAL FREQUENCY (Hzl_
Ib)

Figure 4: Maximum input signal rate change (a) and sinewave
frequency (b) as a function of sampling or aperture time for
::!:: V:! LSB accuracy in 'n' bits.

This is the highest frequency that can be applied to the
converter input without using a sample and hold. For n =
10 bits, ':'T=IO I'S, jmax=15.5Hz.Frequenciesthislow
often come as a surprise to first time users of so-called
high speed AID converters, and explain why the majority
of non-integrating converters are preceded by a sample &
hold. Fig. 4(b) plots equation (1) for a range of .:. T values.
Note that when a sample & hold is used, .:. T is the
aperture time of the S & H. With the help of a $5 sample &
hold such as Intersil's IH5110 (worst case aperture time =
200 ns), fmax in the ab~ve example becomes 780 Hz.
Consideration must also be given to the input stage time
constant of both the sample & hold, if there is one, and the
converter. The number of time constants taken to charge
a capacitor within a given percentage of full scale is
shown in Fig 5. For example, consider a product with a 10
pF input capacitance driven by a signal source impedance
of lOOK!!. For12 bit accuracy, at least9 time constants, or
9 I' s, should be allowed for charging.

32

DATA ACQUISITION &. CONVERSION HANDBOOK

h)

i)

Does the converter form part of a multiplexed data
acquisition system?
Note that some integrating converters (Motorola
MC14433) assess polarity based on the input voltage
during the previous conversion cycle. Such designs
are clearly unsuitable for multiplexed inputs where
the signal polarity bears no relationship to the
previously measured value. They can also give
trouble with inputs hovering around zero.
Is 60Hz rejection important?
If the line frequency rejection capabilities of the integrating converter are important, make sure that the
duration of the measurement (input integrate) period
is a fixed number of clock pulses. In some designs,
the input integration time is programmed by the autozero information, making rejection of specific
frequencies impossible.

CONTROL SIGNALS

Figure 6(b): Data Acquisition using several local AIDs
Another approach, which becomes attractive with the
availability of low cost IC converters, is to use localized
AID conversion with digital transmission back to a central
console. In the limit one could use a converter per transducer, but it is often more economical to have a local
conversion station servicing several transducers (Fig 6b).
S~veral advantages result from this approach. Firstly,
digital transmission is more satisfactory in a noisy
environment, and lends itself to optical isolation
techniques better than analog transmission. Secondly,
using local conversion stations significantly reduces the
number of interconnects back to the central processor.
When one considers that the instrumentation for a typical
power plant uses 4.5 million feet of cable, this can result in
real cost savings. Finally, by sharing the conversion
workload among several AIDs, it is frequently possible to
switch from a successive approximation to a dual Slope
design.
An example of a local conversion station featuring an
8052/7103 dual slope AID, a CMOS multiplexer, and an
UART for serial data transmission is discussed in Ref 2.
The local conversion station concept can be taker a stage
further by the addition of a microprocessor. This may be
used to reduce the data prior to transmission to the
central computer, andlor to look for dangerous
conditions, for example.

MULTIPLEXED DATA SYSTEMS
The foregoing discussion has summarized the characteristics of A/D converters as stand-alone components.
However, one of the most important applications for A/Os
is as part of a multiplexed data acquisition system. Traditionally, systems of this type have used analog signal
transmission between the transducer and a central multiplexer/converter console. (Fig 6a) To sample 100 data
poin!s 25 times per second requires a 100 input analog
multiplexer and an AID capable of 2500 conversions per
second. A successive approximation converter would be
the obvious choice.

OF

Figure 6(8): Data Acquisition usjng one central AID.

33

DEFINITION OF TERMS

Quantization Error. This is the fundamental error
associated with dividing a continuous (analog)
signal into a finite number of digital bits. A 10 bit
converter. for example, can only identify the input
voltage to 1 part in 2", and there is an unavoidable
output uncertainty of ± ~ LSB (Least Significant
Bit). See Fig. 7.
Linearity. The maximum deviation from a straight
line drawn between the end paints of the converter
transfer function. Linearity is usually expressed as a
fractio,.] of LSB ~ize. The linearity of a good
converter is ± ~ LSB. See Fig. B.
Oillerenlial Non-Linearity. This describes the
variation in the analog value between adjacent pairs
of digital numbers, over the full range of the digital
output. If each transition is equal to 1 LSB, the
differential non-linearity is clearly zero. If the
transition is 1 LSB ± 'h LSB, then there is a
differential linearity error of ± ~ LSB, but no
possibility of missing codes. If the transition is 1
LSB ± 1 LSB, then there is the possibility of misSing
codes. This means that the output may jump from,
say 011 .... 111 to 100 .... 001, misSing out 100
. . . . 000. See Fig. 9.

Relallve Accuracy. The input to output error as a
fraction of full scale, with gain and offset errors
adjusted to zero. Relative accuracy is a function of
linearity, and is usually specified at less than ± ~
LSB.
Gain Error. The difference in slope between the
actual transfer function and the ideal transfer
function, expressed as a percentage. This error is
generally adjustable to zero by adjusting the input
resistor in a current-comparing successive
approximation AID. See Fig. 10.
Gain Temperature Coellicient. The deviation from
zero gain error on a 'zeroed' part which occurs as
the temperature moves away from 25°C. See Fig. 10.
Offset Error. The mean value of input voltage
required to set zero code out. This error can
generally be trimmed to zero at any given temperature, or is automatically zeroed in the case of a good
integrating design.
Ollset Temperature Coellicient. The change in
offset error as a function of temperature .

/
/

".

".
t ,.,1--+-+--+-+.....,1"-'-+-+--1

~ lOt

~

~ 100

~ 100

5

o
~ 011

~ 011
~

o

6

o
is

01 0

F.5.
,/, LSB

NORMALIZED ANALOG INPUT

Figure 7: Ideal AID conversion
/
/

".
,.,

~

~

100

~ 011

§
o

010 1--~-r-::01'-"::,--

..' h.....u---,..-F.S.
NORMALIZED ANALOG INPUT

Figure 9: Differential Non-linearity

34

010

1---1f-r.~-+--+

Where and when to use
which data converter
A broad shopping list of monolithic, hybrid, and discrete-component
devices is available
odically at a rate that is relatively fast when compared
with any change in the process.
After receiving data from the process, the computer

With the commercial availability of data-converter
products-the result of both hybrid (multichip) and
monolithic (single-chip) technologies-users of analogto-digital (AID) and digital-to-analog (D/Al converters
now have an impressive array of designs from which to
choose. In addition, the older discrete-component designs
still remain a viable choice for many high-performance
applications, particularly those where broad operating
characteristics and specialized features are important.
Unfortunately, rather than helping the users to match the
proper products to their needs, data-converter manufacturers confuse the issue by arguments over the relative
merits of the different technologies. A closer look at the

calculates the existing "state" of the process and compares it with the "desired state" stored in its memory.

From this comparison, corrections are determined for the
process variables. This information is fed to D/A converters that convert. the digital data into analog form, and
are then used to supply inputs to the process to bring it
to the liesired state.

Types of data converters
Of the many different techniques that have been employed to perform data conversion, only a few are in wide
use. Most D/A converter designs utilize a parallel-input
circuit. In this scheme, the converter accepts a parallel
binary input code and delivers an analog output voltage
by means of binary weighted switches that act simultaneously upon application of the digital input. In the
opening illustration, a representative parallel-input
O/A-converter circuit is presented (A) in which binary
weighted pnp-transistor current sources are controlled
by emitter-connected diodes. For simplicity, a 4-bit
converter is shown. The inputs operate from transistor-transistor logic (TTL) levels. The output current
changes rapidly with a change in the digital input code.
Since a voltage output is desired in most cases, the current
from the pnp transistors is fed to an operational amplifier
current-to-voltage converter. An internal voltage reference, which may be a Zener-diode or band-gap reference

various types of data converters may help to clear up

some of this confusion.

How data converters are used
Data converters are the basic interfaces between the
physical world of analog parameters and the computational world of digital data processing. They are used in
many industries in a wide variety of applications, in-

cluding data telemetry, automatic process control, test
and measurement, computer display, digital panel meters
and multimeters, and voice communications, as well as

in remote data recording and video signal processing.
As a typical example of the use of AID and D/A converters, Fig. I illustrates how an entire industrial process
can be controlled by a single digital computer, which may
be located at a considerable distance from the process
site. To communicate with the process, data inputs to the
computer must be converted into digital form and the
outputs reconverted into analog form.
Physical parameters of temperature, pressure, and flow
are sensed by appropriate transducers and amplified to
higher voltage levels by operational or instrumentation
amplifiers. The various amplifier outputs are then red
into an analog multiplexer for sequential switching to the
next stage-a sample-hold circuit that "freezes!' the input
voltage of a sequentially switched input for a fixed period
of time, long enough for the following AID converter to
make a complete. conversion cycle. In this manner, a
single AID converter is time-shared over a large number
of analog input channels. Each channel is sampled peri-

circuit, completes the circuit.

The most common AID-conversion technique is the
successive-approximation method, used in 70-80 percent
of all present-day applications. As shown in the opening
illustration, this circuit (B) incorporates the parallelinput 0/A converter circuit previously described along
with a successive-approximation register a comparator,
and a clock. The D/A converter's output, controlled by
the successive-approximation register, is compared, one
bit at a time, against the input signal, starting with the
largest or most significant bit. A complete conversion is
always accomplished in n steps for an n-bit converter,
regardless of the input signal value. Successive-approximation AID converters have the desirable characteristics
of high conversion speed as well as excellent accuracy and
stability, provided the circuit is well designed.
The next most popular AID-conversion method is the
dual-slope technique found in most digital panel meters
and digital multimeters and commonly used in measurement and numeric display systems, also shown in the
opening illustration (C). This converter circuit operates
on an indirect principle, whereby the input voltage is
I

35

DATA ACQUISITION & CONVERSION HANDBOOK

+Vs

Bitl

D/Aconverter

Comparator
Successive
approximation
register

Reference

circuit
2" Iline

Binary-

tonM

coded
output

decoder

R/2

Output data

36

Transducers

12-bit current-output 0/A converters are available with
settling times as low as 50 ns, with voltage-output units
achieving settling times down to 600 ns. Resolution can
be as high as 16 bits. Excellent stabilities are also possible;
ultralow drifts of 1 ppm/·C are achievable.
Equally impressive performance is also obtainable from
discrete-component AID converters. The fastest are the
parallel types with resolutions of 8 bits at a 17-MHz

Amplifiers

conversion rate. Successive-approximation AID converters offer rapid conversion times at various resolutions.

As can be seen in Table II, conversion times of 0.80, 1.0,
2.0, and 10 ,"S at re.".ctive resolutions of8, 10, 12, and 14
bits are possible. Slower but higher-resolution 14-bit
dual-slope and 16-bit successive-approximation AID
converters with excellent stabilities are also available.

Hybrid converters

111 AID

Although hybrid-converter design is almost as flexible
as that of discrete-component converters, it does have two
limitations: Not all of the semiconductor components
used in a hybrid converter are readily available in chip
form. Moreover, the number of chips used in a hybrid

converted to a time period measured by means of a ref-

converter must be kept to a minimum for the converter

erence and a counter. Firsi, the input voltage is integrated
for a fixed period of time, determined by the circuit's
clock and counter. The integrator is then switched to the
reference, causing integration in the opposite direction,
until the output is back to zero, as determined by the
comparator. The resultant digital-word output of the
counter is proportional to the input voltage. The dualslope method is very accurate, as its accuracy and stability
depend only on the accuracy and stability of the circuit's

to be economically producible. Minimizing the chip count
minimizes the number of honds required, which in turn
minimizes labor content and maximizes both end-product
yield and reliability.
Three factors have played a role in the emergence of
new low-cost high-performance hybrid converters. The
first is'the availability of low-cost quad-current switches
in chip form, which has simplified the circuitry required
for the binary weighted current sources used. Second, new

reference. Its disadvantage is a much slower conversion
time than with successive-approximation converters.

monolithic successive-approximation registers have

and DI A conversion products are a process-control
system's basic Interface elements between Hs physical .arlables
and dlglta' controlling computers.

minimized the logic circuitry required. And third, stable
thin-film resistors with tight temperature tracking
characteristics, and trimmable with fast laser trimming

A third AID-conversion method is the less frequently
used ultrahigh-speed parallel, or flash, technique. As
shown in the opening illustration, this circuit (D) employs
2 n - 1 comparators to make an n-bit conversion. The
comparators are biased by a tapped resistor connected
to the reference voltage. The input signal is fed to the
other comparator inputs all tied together. The result is
a circuit that acts as a quantizer witb 2 n levels, where n
is the number of bits. For a given input-voltage level, all
comparators biased below that level trip ON, and those
biased above it remain OFF. The 2" - 1 digital outputs
from the comparator must then be decoded into binary
outputs. Since the complete conversion cycle occurs in
only two steps, very-high-speed conversions are possible.
The limitation of this technique is that it is difficult to
realize high resolution, because of the large number of

techniques, have made it possible to achieve economical

12-bit, and higher, resolutions. In fact, the excellent
tracking characteristics of thin-film resistors (tracking
within 1-2 ppm/·C is considered routine) provides hybrid
converters with an advantage over modular discretecomponent units.
As can be seen in Table I, hybrid devices include 8-, 10-,

12-, and 16-bit D/A converters with excellent performance characteristics. The 12-bit D/A converters have

temperature coefficients as low as 10 ppm/·C, and some
certain input registers. Most bybrid 0/A converters do
not require external output amplifiers.
Hybrid AID converters with resolutions of 8, 10, and
12 bits are available, with respective conversion times of

0.9, 6.0, and 8.0

comparators required.

,"S.

An attractive feature of such A/D

converters is their low price; for example, 12-bit models

A comparison of technologies

are now selling for under $100. Such units are complete

Traditionally, data converters have been of the discrete-component type, first becoming available in instrument cases and later in compact, encapsulated
modules. The advantage of this approach is that optimum
components of all types can be combined. For example,
for very high levels of speed and precision, a high-speed
comparator may be combined with precision, high-speed
current switches utilizing very-Iow-temperature-coefficient resistors and a very-Iow-temperature-coefficient
reference. The result of such flexible component selection
has been the development of some very impressive
high-performance discrete-component converters over
the past several years. For example, Table I shows that

converters and, except for calibration adjustments, require no external circuitry.

Monolithic converters
Monolithic data converters are generally a step below
discrete and hybrid units in performance. In addition,
various external components are usually required for
proper operation, although this may not be viewed as a
serious limitation since the attractive low prices of mo-

nolithic converters may more than compensate for the
cost of the added components.
One of the obvious fabrication difficulties is making
stable monolithic resistors for 10- and 12-bit monolithic

37

DATA ACQUISITION i CONVERSION HANDBOOK

II. Representative AID converter.

I. Representative 0/ A converters

Gain

Gain
Resolu- Settling

tion

Time

(bits)

b..)

Output
Type

TC
(ppml
'C)

Discrete-component converters
Current·
10
0.025
Voltage
10
0.26
Current
12
0.05
12
Voltage
2

12
12
14
16

5
0.60
2
25

Voltage
Voltage
Voltage
Voltage

Aesolu- Conversion
Comments

2
3
3
3
50

15
60

20
20
7
35
10
1

Voltage
Voltage
Voltage
Voltage
Current

Time

Conversion

(bits)

(~.)

Type

TC
(ppm I
'C)

Comments

Discreta-component converters

5

Ultrafast
Ultrafast

10
20
7

0,01

Parallel

Ultrafast;
, OO-MHz rate

8

Ultrafast

Fast; contains input
register
Low drift
Ultrafast; deglitched
Fast; low drift

8

0.80

Successive

0.06

approximation
Parallel

10

Ultralow drift

Hybrid converters

8
10
12
12
16

tion

Contains input register
Fast
Fast
Contains input register
High resolution; requires
external output
amplifier

Suc:c8ssive
approximation

12

2

14

10

16

400

14

230 000

Successive
approximation
Succe$Sive
approximation
Successive
approximation
Dual slope

20 Very fast; 1.2MHz rate
100 Ultrafast;
17·MHz rate
20 Very fast;
1·MHz rate

30

Very fast;
500·kHz rate

6

8

Fast
High resolution;
very low drift
High resolution; low
drift; Ratiometric
with front-end
isolation

Hybrid converters
Monolithic converters
Current
8
0.085

8
10

0.50
1.5

Current

Voltage

10

0.50

Current

10

0.25

Current

12

0.50

Current

12

0.30

8

Current

60

60

Fast; requires external
reference
Companding type for
communication
applications
Complete unit; includes
reference and output
amplifier
Multiplying type made
from CMOS technology; requires external reference and
output amplifier
Uses thin·film resistors;
has internal reference.
but requires e)(ternal
output amplifier
Multiplying type made
from CMOS tech·
nology; does nQt have
12-bit linearit't'; reo
quires external reference and output
amplifier
Bipolar type with true
12·bit linearity; reqllires e)(ternai reference and output
amplifier

0.9

10

6

12

8

Successive
approximation
SucceSSive
approximation
Successive
approximation

Fast

30

Fast

20

Fast

Monolithic converters

8

40

8

1800

10

40

Successive
approximation

10

6000

Charge balanCing

12

24 000

Charge balancing

13

40000

Dual slope

3%-digit 40 000

Dual slope

BCD

Successive
approximation
Charge balancing

Requires external reference and clock
CMOS; requires external reference and
other components
CMOS; requires external comparator,
reference, and other
components
CMOS; requires external reference and
other components
CMOS; requires external reference and
other components
CMOS; has auto·zero
circuit; requires external reference and
other components
CMOS; has auto·zero
circuit; requires external reference and
other components

or charge-balancing technique.
Charge balancing involves switching, in discrete time
intervals, the output of a current source fed into the
summing junction of an operational integrator. The
switching is controlled by a comparator, which is controlled, in turn, by the output of the operational integrator. The input signal, which is also fed into the operational integrator's summing junction, determines the
switching current's pulse rate. As the input signal increases in magnitude, the switched current's pulse rate
(controlled by the comparator) increases in proportion
to the input signal, until a current balance is achieved at
the operational integrator's summing junction.
Whereas earlier monolithic devices used a two-chip
approach to separate the analog and digital portions of
the circuit, newer converters are one-chip units. Never~

converters. It is possible to use diffused resistors for 8-bit,
and sometimes lO-bit, converters, but tracking requirements at the 12·bit level are severe, necessitating the use
of thin-film resistors and the additional step of depositing the thin·film resistors onto the monolithic chip.
Monolithic-converter designers have been quite successful in employing ingenious circuit techniques to
achieve what would have been difficult to do in a
straightforward manner. This is one of the challenging
aspects of monolithic circuitry. For example, although
monolithic 12-bit successive-approximation AID converters are quite difficult to make, equivalent accuracy
can be readily achieved by use of the slower dual·slope
conversion technique. A number of low-cost 12-bit monolithic unita are on the market that offer good performance characteristics. They utilize either the dual-slope

38

A brief look backwards
High~performance

data converters first became available
in 1955. when the Epsco Corp. unveiled its Datrac 8-611
AID converter (one of the historical exhibits of last year's
ELECTRO in Boston). This vacuum-tube-based instrument,
together with its companion power supply, weighed 150
pounds (68 kg) and cost $8500. Yet it offered impressive
performance, even by today's standards: 11-bit resolution
at a 44-kHz.conversion rate.
The development of early converters was spurred in part
by the then infant U.S. space program, which used them

Monolithic data converters were also being developed
in the late '60s. in 1968, Fairchild Semiconductor was able
to build a monolithic 10-bit D/A converter based on its
model JJ.A722, although this unit was a basic building block
requiring an external reference, resistor network, and
ou\put amplifier. By 1970, Analog Devices had manufac¥
tured the industry's first monolithic quad¥current switches,
to be used as building bloCks for hybrid AID and 01 A converters up to 16 bits in resolution. It was also in 1970 that
PreCision Monolithics produced the first complete 01 A
converter in monolithic forrn-a 6-bit unit that included a
reference and an output amplifier, and required no additional components for operation (model DAC-Ol).
Meanwhile, discrete-component converters continued
to be improved in performance characteristics. By 1971,
conversion times for 12-bit AID units had dropped to just
4 I-LS, though prices still hovered around the $600-$700
mark. Hybrid-converter prices continued to drop, with an
11-bit D/A converter (Beckman Instruments' model 848)
selling for $155 in 1971 and a 12-bit unit (Micro Networks'
model MN312) dropping to $100 by the next year.
MonOlithic units also continued to be improved. In 1972,
Motorola announced an B-bit monolithic 01 A converter
(model MC140B), and PreCision Monolithics produced a
10-bit unit (model OAC-02) the next year.
By 1975, the price of hybrid data converters such as
Oatel Systems' 12-bit model AOC-HY128 AID converter
had dropped below $100. At the same time, 10·bit monolithic 01 A converters were selling tor as low as $20. And
performance of discrete-component AID converters such
as Datel's AOC-EH1283-a 12-bit 2-lJ.s unit-has reached
a new high at a record low price of $300, half the former
price.
Monolithic-converter prices have continued to drop (now
down to about $10 for a 10·bit 01 A unit requiring external
components) while performance is up (300-ns for a 12-bit
01 A converter from Precision Monolithics requiring only
an external reference and an op amp).

for high-speed pulse-code-modulation (PCM) data-telemetry
and computer data-reduction applications, and also for
digitizing radar signals.
By 1958-1959. packaged transistors replaced vacuum
tubes to produce 12-bit AID converters that were substantially smaller in size than their predecessors. At least
three such converters were introduced at that time-by
Adage, Epsco, and Packard-Bell; they ranged in conversion
times from 13 to 48 I-Ls. Selling price was still quite high
(about $5000) and by 1960, only about 2000 of these
converters were in use.
A breakthrough occurred in 1966 when Epsco introduced
its Datrac 3, a small hand-held 12-bit discrete-component
AID converter constructed on just two circuit boards in a
metal-case module. The unit had 24-Ms conversion and sold
for $1200. Similar devices soon followed and, by 1968, the
Redcor Corp. had introduced the first encapsulated discrete-component 12-bit A/O converter with 50-.us conversion at a price of $600.
The next year saw rapid improvement in discretecomponent-converter performance, with 12-bit AID-converter conversion times dropping down to 12 .us. During that
same period, the Beckman Instrument Co. unveiled a
new-generation data converter-the first hybrid converter,
an 8-bit 01 A unit made from multiple monolithic IC chips
and a thick-film resistor network. An 8-bit D/A with a
thin-film resistor network was produced in 1970 by Micro
Networks.

converters are also available, one of which can be obtained
with a reference and an output amplifier. And one
multiplying-type lO-bit unit can have a variable reference
applied to it, The CMOS 12-bit monlithic D/A converter
model available at this time is a multiplying type, and
does not provide full 12-bit linearity. Another bipolar
12-bit D/A converter has been introduced that has true
12-bit linearity, and requires an external reference and
output amplifier.

theless, external components, such as an integrating capacitor, a reference, and some compensation parts, are
needed for proper operation.
CMOS drcuitry has been used to fabricate monolithic
converters with BCD coding, for digital panel meters and
small instruments. Among the other popular monolitbic
AID converter types is an 8· bit design that employs a
variation of the successive-approximation technique.
This device is made with an ion-implanted ,p-channel
MOS technology. Instead of the conventional eight
switches, it uses 255 switches connected to a 256·seriesresistor chain. In hybrid or discrete form, this would be
a gross waste of components, but not so in monoHthic
form. This approach results in a monotonic 8-bit AID
converter.
Another successful monolithic approach has been to
use bipolar technology to make an 8-bit D/A converter
with a companding characteristic for use in voice'PCM
systems, A typical device has eight inputs, which select
eight chords (straight-line approximations to a curve),
each with 16 equal steps. As part of an AID converter, this
device compresses a signal (provides high gain at low
signal levels and vice versa), When used as a D/A converter, it expands the signal according to a standardized
logarithmic curve.
Tables I and II list some representative monolithic D/A
and AID converters, A large number of 8-bit devices are
on the market, chiefly because of their low prices and
satisfactory performance levels, Several lO-bit D/A

GZ

39

THE INTEGRATING AID CONVERTER

Integrating AID converters have two characteristics in
common. First, as the name implies, their output represents the integral or average of an input voltage over a
fixed period of time. Compared with techniques which
require that the input is "frozen" with a sample-and-hold,
the integrating converter will give repeatable results in the
presence of high frequency· noise. A second and equally
important characteristic is that they use time to quantise
the answer, resulting in extremely small nonlinearity
errors and no possibility of missing output codes.
Furthermore, the integrating converter has very good
rejection of frequencies whose periods are an integral
multiple of the measurement period. This feature can be
used to advantage in reducing line frequency nOise, for
example, in laboratory instruments. (Fig. 1).

useage of integrating converters exceeds the combined
total of all other conversion methods. Furthermore, the
availability of Jow cost one and two chip converters will
encourage digitizing at the sensor in applications such as
process control. This represents a radical departure from
traditional data logging techniques which in the past have
relied heavily on the transmission of analog signals. The
availability of one chip microprocessor system (with ROM
and RAM on chip) will give a further boost to the
'conversion at the sensor' concept by faCilitating local
data processing. The advantage of local processing is that
only essential data, such as significant changes or danger
Signals, will be transmitted to the central processor.

THE DUAL SLOPE TECHNIQUE - THEORY &
PRACTICE
The most popular integrating converter is the "dualslope" type, the basic operating principles of which will be
described briefly. However, most of the comments
relating to linearity, noise rejection, auto-zero capability,
etc., apply to the whole family of integrating designs
including charge balancing, triple ramps, and the 101
other techniques that have appeared in the literature. A
simplified dual slope converter is shown in Figure 2.

NMO
(dB)

INTEGRATION CAP.

Figure 1: Normal Mode Rejection of dual-slope converter as a function of
freqyency

In addition, a competitive instrument-quality product
should have the following features:
1. Single Reference Voltage. This is strictly a
convenience to the user, but since many designs are
available with single references that contribute
negligible error, products requiring dual references
are rapidly becoming obsolete.
2. Auto Zero. This eliminates one trim-pot and a troublesome calibration step. Furthermore, it allows the
manufacturer to use op-amps with up to 10mV offset
while still achieving system offsets of only a few
microvolts.
3. High Input Impedance. Recently developed monolithic
FET technology allows input impedances of 1000
Mohm and leakages of a few pico amps to be achieved
fairly readily.
The unique characteristics of the integrating converter
have made it the natural choice for panel meters and
digital voltmeter applications. For this reason, overall

Figure 2: Simplified dual-slope converter,

• relative to the measurement period.

Figure 3: The three phases of a dual-slope conversion.

The conversion takes place in three distinct phases
(Fig. 3).

-PHASE I _ _ I_PHASI;'
AUTO ZERO

II

II-I--~PHASE

SIGNAl.
INTEGRATE

I
I

I

I

I

I

I

I

til--

REFERENCE INTEGRATE

I

I
I
I
I
--IU1.I1I1.
___ .I1.I1..fUlIl. ______ _

I~I------------

40

liud number

Number 01 clock puis.,

01 clock pulse.

proporllona' 10 VIN

DATA ACQUISITION & CONVERSION HANDBOOK

300f'F

sw,

"03

DIGITAL PROCESSOR

ANALOG
GNO

'5V

Figure 4: the 7103/8052 AID Converter pair.

Phase 1, Auto Zero: During auto zero, the errors in the
analog components (buffer offset voltages, etc.) will be
automatically nulled out by grounding the input and
closing a feedback loop such that error information is
stored on an "auto-zero" capacitor.
Phase 2, Signal Integrate: The input signal is integrated
for a fixed number of clock pulses. For a 3'h-digit
converter, 1,000 pulses is the usual count; for a4 'h-digit
converter, 10,000 is typical. On completion of the
integration period, the voltage V in Fig. 3 is directly
proportional to the input signal.
Phase 3, Reference Integrate: At the beginning of this
phase, the integrator input is switched from VIN to
VREF. The polarity of the reference is determined
during Phase 2 such that the integrator discharges back
towards zero. The number of clock pulses counted
between the beginning of this cycle and the time when
the integrator output passes through zero is a digital
measure of the magnitude of VIN.
The beauty of the dual slope technique is that the
theoretical accuracy depends only on the absolute value
of the reference and the equality of the individual clock
pulses within a given conversion cycle. The latter can
easily be held to 1 part in 10·, so in practical terms the only
critical component is the reference. Changes in the value
of other components such as the integration capacitor or
the comparator input offset voltage have no effect,
provided they don't change during an individual
conversion cycle. This is in contrast to Successive
Approximation converters which rely on matching a
whole string of resistor values for quantisation.
I n a very real sense the designer is presented with a near
perfect system; his job is to avoid introducing additional
error sources in turning this text-book circuit into a real
piece of hardware.
From the foregoing discussion, it might be assumed that
designing a high performance dual-slope converter is as
easy as falling off the proverbial log. This is not true,
however, because in a practical circuit a host of pitfalls
must be avoided. These include the non-ideal character-

istics of FET switches and capacitors, and the switching
delay in the zero crossing detector.

ANALYZING THE ERRORS
At this pOint it is instructive to perform a detailed error
analysis of a representative dual slope circuit, Intersil's
8052An103A pair. This is a 4'h-digit design, where the
analog circuitry is on a JFET/bipolar chip (the 8052) and
the digital logic and switches on a MOS chip (7103A); the
partitioning is shown in Fig. 4. The error analysis which
follows relates to this specific pair - however, the
principles behind the analysis apply to most integrating
converters.
The analog section of the converter is shown in Fig. 5.
Typical values are shown for 120KHz clock and 3
measurements/second. Each measurement is divided
into three parts. In part 1, the auto-zero FET switches 1,2
and 3 are closed for 10,000 clock pulses. The reference
capacitor is charged toVREF and the auto-zero capacitor
is charged to the voltage that makes dVIdt of the
integrator equal to zero. In each instance the capacitors
are charged for 20 or more time-constants such that the
voltage across them is only limited by noise.

"N
Figure 5: Analog section of a dual slope converter.

I n the second phase, signal integrate, switches 1, 2 and 3
are opened and switch 4 is closed for 10,000 clock pulses.
The integrator capacitor will ramp up at a rate that is proportional to VIN. I n the final phase, de-integrate, switch 4
is opened and, depending on the polarity of the input
signal, switch 5 or 6 is closed. In either case the integrator
will ramp down at a rate that is proportional to VREF. The

41

amount of time, or number of clock pulses, required to
bring the integrator back to its auto-zero value is 10,000
(V~~F)' Of course, this is a description of the "ideal" cycle.
Errors from this ideal cycle are caused by:

3. Non-linearity 01 buffer and Integrator.
In this converter, since the signal and reference are injected
at the same point, the gain of the buffer and integrator are
not of first-order importance in determining accuracy. This
means that the buffer can have a very poor CMRR over the
input range and still contribute zero error as long as it is constant, i.e., offset changes linearly with common mode voltage. The first error term is the non-linear component of
CMRR. Careful measurement of CMRR on 30 buffers indicated roll-over errors from 5 to 30 !,V. The contribution of integrator non-linearity is less than I!'V in each case.

1. Capacitor droop due to leakage.
2. Capacitor voltage change due to charge "suck-out"
(the reverse of charge injection) when the switches
turn off.
3. Non-linearity of buffer and integrator.
4. High-frequency limitations of buffer, integrator and
comparator.
5. Integrating capacitor
absorption).

4. High frequency limitations of amplifiers.

non-linearity (dielectric

For a zero input signal, the buffer output will switch from
zero to VREF (1.0 volt) in 0.5 !,seconds with an
approximately linear response. The net result is to lose .25
!' seconds of de-integrate period. For a 120KHz clock, this
is 3% of a clock pulse or 3 !,V. This is not an offset error
since the delay is equal for both positive and negative
references. The net result is the converter would switch
from a to 1 at 97 !'V instead of 100 !'V in the ideal case.

6. Charge lost by C REF in charging Cstray.
Each of these errors will be analyzed for its error
contribution to the converter.
1. Capacitor droop due to leakage.
Typical leakage (IDoff) of the switches at normal
operating voltage is 1 pA each and 2pA at each input afthe
buffer and integrator op amps. I n terms of offset voltage
caused by capacitor droop, the effect of the auto-zero and
reference capacitors is differential, Le., there is no offset if
they droop an equal amount. A conservative typical effect
of droop on offset would be 2pA discharging I!,F for 83
milliseconds (10,000 clock periods), which amounts to an
averaged equivalent of .083!, V referred to the input. The
effect of the droop on roll-over error (difference between
equal positive and negative voltages near full scale) is
slightly different. For a negative input voltage, switch 5 is
closed for the de-integrate cycle. Thus the reference
capacitor and auto-zero capacitor operate differentially
for the entire measurement cycle. For a positive voltage,
switch 6 is closed and the differential compensation of the
reference capacitor is lost during de-integrate. A typical
contribution to roll-over error is 3 pA discharging I!'F
capacitor for 166 milliseconds, equivalent to .249!,V when
averaged. These numbers are certainly insignificant for
room temperature leakages but even at 100°C the contributions should be only 15!'V and 45!'V respectively. A
roll-over error of 45 !'V is less than 0.5 counts on this
20,000 count instrument.

A much larger source of delay is the comparator which
contributes 3 I'seconds. At first glance, this sounds
absolutely ridiculous compared to the few tens of nanoseconds delay of modern IC comparators. However, they
are specified with 2 to 10 mV of overdrive. By the time the
8052A comparator gets 10 mV of overdrive, the integrator
will have been through zero-crOSSing for 20 clock pulses l
Actually, the comparator has a 300M Hz gain-bandwidth
product which is comparable to the best IC's. The
problem is that it must operate on 30/-tV of overdrive
instead of 10 mV. Again, this delay causes no offset error
but means the converter switches from 0 to 1 at 60 !'V,
from 1 to 2 at 160 !'V, etc. Most users consider this
switching at approximately V, LSB more desirable than
the "so-called ideal" case of switching at 100 !,V. If it is
important that switching occur at 100 !'V, the comparator
delay may be compensated by including a small value
resistor (oe2011) in series with the integration capacitor.
(Further details of this technique are given on page 4
under the heading "Maximum Clock Frequency".)
The integrator time delay is less than 200 nsecond and
contributes no measureable error.

2, Charge "suck-out" when the switches turn-off,
There is no problem in charging the capacitors to the
correct value when the switches are on. The problem is
getting the switches off without changing this value. As
the gate is driven off, the gate-to-drain capacitance of the
switch injects a charge on the reference or auto-zero
capacitor, changing its value. The net charge injection of
switch 3 turning-off can be measured indirectly by noting
the offset resulting by using a .01!,F auto-zero cap~citor
instead of 1.0!, F. For this condition the offset is typically
250!'V, and since the signal ramp is a straight line instead
of a parabola the main error is due to charge injection
rather than leakage. This gives a net injected charge of 2.5
picocouloumbs or an equivalent Cgd ofO.16pF. The effect
of switches 1, 2, 4, 5 and 6 are more complicated since
they depend on timing and some switches are going on
while others are going off. A substitution of an .01 !' F
capacitor for reference capacitor gives less than 100!'V
offset error. Thus, a conservative typical offset error for a
1.0!'F capacitor is 2.5I'V. There is no contribution to rollover error (independent of offset). Also this value does not
change significantly with temperature.

5. I ntegrating capacitor dielectric absorption.
Any integrating AID assumes that the voltage change
across the capaCitor is exactly proportional to the integral
of the current into it. Actually, a very small percentage of
this charge is "used up" in rearranging charges within the
capaCitor and does not appear as a voltage across the
capacitor. This is dielectric absorption. Probably the most
accurate means of measuring dielectric absorption is to
use it in a dual-slope AID converter with V,N =VREF' In
this mode, the instrument should read 1.0000
independent of other component values. In very careful
measurements where zero-crossings were observed in
order to extrapolate a fifth digit and all delay errors were
calculated out, polypropylene capacitors gave the best
results. Their equivalent readings were 0.99998. In the
same test polycarbonate capacitors typically read 0.9992,
polystrene 0.9997. Thus, polypropylene is an excellent
choice since they are not expensive and their increased
temperature coefficient is of no consequence in this
circuit. The dielectric absorption of the reference and
auto-zero capaCitors are only important at power-on or

42

DATA ACQUISITION & CONVERSION HANDBOOK

when the circuit is recovering from an overload. Thus,
smaller or cheaper capacitors can be used if very accurate
readings are not required for the first few seconds of
recovery.

6, Charge lost by CREF In charging Cstray'
In addition to leakage and switching charge injection, the
reference capacitor has a third method of losing charge
and, therefore, voltage. It must charge Cst ray as it swings
from 0 to VIN to VREF, (Figure 5). However, Cstray only
causes an error for positive inputs. To see why, let's look
firstly at the sequence of events which occurs for negative
inputs. During auto-zero CREF and Cstray are both
charged through the switches. When the negative signal
is applied, CREF and Cstray are in series and act as a
capacitance divider. For Cstray =15 pf, the divider ratio is
0.999985. When the positive reference is applied through
switch #5, the same divider operates. As mentioned
previously, a constant gain network contributes no error
and, thus, negative inputs are measured exactly.
For positive inputs, the divider operates as before when
switching from auto-zero to VIN, but the negative
reference is applied by closing switch #6. The reference
capacitor is not used, and therefore the equivalent divider
network is 1.0000 instead of .999985. At full scale, this 15
I'V/v error gives a 301' V rollover error with the negative
reading being.30l'V too low. Of course forsmalierCstray'
the error is proportionally less.
Summary,
Error analysis of the circuit using typical values shows
four types of errors. They are (1) an offset error of 2.5p.V
due to charge injection, (2) a full scale rollover error of 30
p.V due to Cstray' (3) a full scale rollover error of5 t030p.V
due to buffer non-linearity and (4) a delay error of 40l'V
for the first count. These numbers are in good agreement
with actual results observed for the 80S2A/71 03A. Due to
peak-to-peak noise of 20 p.V around zero, it is possible
only to say that any offsets are less than 10p.V. Also, the
observed rollover error is typically v, count (SO p. V) with
the negative reading larger than the positive. Finally, the
transition from a reading of 0000 to 0001 occurs at SOp.V.
These figures illustrate the very high performance which
can be expected from a well designed dual-slope circuitperformance figures which can be achieved with no tricky
'tweaking' of component values. Furthermore, the circuit
includes desirable convenience features such as autozero, auto-polarity and a single reference.

SO"V IN

(a, UNCOMPENSATED

SO"V IN
(bl COMPENSATED

Flgure6: Integrator and comparator outputs for uncompensated (8) and
compensated (b) system.

resistor and th'e integrating resistor (a few tens of ohms in
the re.cgmmended circuit), the comparator delay can be
compensated and the maximum clock frequency
extended by approximately a factor of 3. At higher
frequencies, ringing and second order breaks will cause
significant non-linearities in the first few counts of the
instrument.

NOISE
The peak-to-peak noise around zero is approximately 20
I'V (pk-to-pk value not exceeded 9S% of the time). Near
full scale, this value increases to approximately 40I'V,
Since much of the noise originates in the auto-zero loop,
some improvement in noise can be achieved by putting
gain in the buffer. Pin 10 of the 80S2 brings out the
inverting input, so this is easily done. A gain of about5X is
optimum. Too much gain will cause the auto-zero switch
to misbehave, because the amplified Vos of the buffer will
exceed the switch operating range.
A low-noise version of the analog chip (80S2-LN), using
Bifet technology, should reduce the noise to about 31'V
pk-to-pk and even less with some gain in the buffer.

MAXIMUM CLOCK FREQUENCY
Because of the 3p. S delay in the 8052 comparator, the
maximum recommended clock frequency is 160KHz. In
the error analysis it was shown that under these
conditions half of the first reference integrate period is
lost in delay. This means that the meter reading will
change from 0 to 1 at SO p.V, from 1 to 2 at IS0p.V, etc. As
was noted earlier, most users consider this transition at
midpoint to be desirable. However, if the clock frequency
is increased appreciably above 160KHz, the instrument
will flash 1 on noise peaks even when the input is shorted.
The clock frequency may be extended above 160KHz,
however, by using a low value resistor in series with the
integration capacitor. The effect of the resistor is to
introduce a small pedestal voltage on to the integrator
output at the beginning of the reference integrate·phase
(Fig. 6). By careful selection of the ratio between this

LE

43

Applying the 7109
AID converter

can be reduced to less than the recommended 4V full scale with some loss of
accuracy. The integrator output can swing
within 0·3V of either supply without loss of
linearity.
The ICL 7109 has, however, been
optimised for operation with analogue common near digital ground. With power supplies of +5V and -5V, this allows a 4V full
scale integrator swing positive or negative,
maximising the performance of the analogue section.

This article examines the operation and applications of the
leL 7709 monolithic, c.m.o.s., 12 bit, integrating analogue to
digital converter which was introduced to the market early Differential reference
The reference voltage can be generated
in 1979.
anywhere within the power supply voltage
Figure I shows the equivalent circuit of the
ICt 71011. When the RUNI1R51]) input is
left open or connected to V+. the circuit
will perform conversions at a rate determined by the clock frequency (S192 clock
periods per cycle). Each measurement
cycle is divided into three phases as shown
ill Fig. 2. They are Auto-Zero (AZ), Signal
Integrate (INT) and Deintegrate (DE).
Auto-zero phase. During auto-zero three
things happen. First, input high and low are
disconnected from their pins and internally
shorted to analogue common. Second, the
reference capacitor is charged to the reference voltage. Third, a feedbark loop is
closed around the system to charge the
auto-zero capacitor C AZ to compensate for
offset voltages in the buffer amplifier,
integrator, and comparator. Since the
l'Omparator is included in the loop, the AZ
accuraC\l is limited onlv by the noise of the
system. 'In any case, the offset referred to
the input is less than 111", V.
Signal integrate pha.ff. During signal integrate the auto-zero loop is opened, the
internal short is removed: and the internal
input hij!h and low are connected to the
external pins. The converter then inte~rates the differential voltage between
IIIpUt high and input low for a fixed time of
~1I4R clock periods. At the end of this
phase. the polarity of the integrated signal
i, determined.

Deintegrate phase. The final phase is
deinte$rate, or reference integrate. Input
low is mternally connected to analog common and input high is connected across the'
previously charged (during auto-zero)
reference capacitor. Circuitry within the
chip ensures that the capacitor will be
connected with the correct polarity to
cause the integrator output to. return to the
zero crossing (established in Auto Zero)
with a fixed slope. Thus the time for the
output to return to zero (represented by
the number of clock periods counted) is
proportional to the input signal.

Differential input
The input can accept differential voltages
anywhere within the common mode range
of the input amplifier, or specifically from
0·5V below the positive supply to IV
above the negative supply. In thl~ range the
system has a C.m.r.r. of 86dB tYPIcal. However, since the integrator also swings with
the common mode voltage, care must be
exercised to ensure that integrator output
does not saturate. A worst case condition
would be a large positive common mode
voltage with a near fullscale negative differential input voltage. The negative input
signal drives the integrator positive when
most of its swing has been used up by the
positive common mode voltage. For these
critical applications the integrator swing

of the converter. The ICL 7109 provides a
reference output (pin 29) which may be
used with a resistive divider to generate a
reference voltage. This output will sink up
to about 20mA without significant variation in output voltage, and is provided with
a pullup bias device which sources about
1O",A. The output voltage is nominally
2.SV below V+, and has a temperature
coefficient of ± SOppml"C typo The stability
of the reference voltage is a major factor in
the overall absolute accuracy of the converter. The resolution of the ICL 7109 at
12 bits is one part in 4096, or 244ppm.
Thus if the reference has a temperature
coefficient of SOppml"C (onboard reference) a temperature difference of 3°C will
introduce a one-bit abSl)lute error. For this
reason, an external high-quality reference
should be used where the ambient tem~r­
ature is not controlled or where hl$haccuracy absolute measurements are bemg
made. The internal reference may then be
used as a pre-regulator for an external
reference, such as the ICLS069 bandgap
refer~n~e diode.

Digital section
The digital section includes the clock
oscillator and scaling circuit, a 12-bit
binary counter with output latches and
t.t.I.-compatible three-state output drivers,
polarity, over-range and control logic, and
u.a.r.t. handshake logic.

Fig. I.

f ----U~·.!.- --t

Ref cop + Ref In'
)
In"u'

AZtX

h'9ht01- . --- -- 135

0

I )'0
I
emt emt +)

U¥R'",
c..
fAZ

Ref cap -

~-'--4I

. .........

-,

r"1+

I

InpII'

tNT

AZ

v/
"----_

'

common~-l~-

j2' -

Test POL OR 121110:

I: ~ 6 5 4

3 .2 1 _ _ _ _ •

-17j-3 ~7TsT9Iopi'fl2113f~sr6!

,~n.e9r••or I ~omp.r•• or

II\Z~ _

1

flntegr ••or

> ..J -r-'~''+

- ~ffer

t~:::~B~:-:+::-~;:::ts~-;1

--Jo c,.,

38" - s..ii'r 30 3'- _ ..

Q tJ
t5QAZ

liNT

Ref IN-

t£ -- - -'ilf

137

,

'>_
"

14 Three·..... outputs

18

CE Load

..--

I

14 Latches

___

.
'

I

10.A
-Oe,ntl·)

_~~Int ttl

LO~-~==_-=

III

___

---.J

~ef

6.2V!

:

:

I

Int o;in;(+)

29_ _ _
out

I_

l .....-.-+:20~HBEN
LB~N

2~Jo~'~I_ _2
v-

V+

44

Statu.

--1 ~
Run/ Osc Osc Osc Buf Mode
hold in out ., Ole
out

Send

GNO

The MODE input is used to contro! the output mode of the converter.

Direct mode. When the MODE pin is left at
a low level, the data outputs (bits I to Slow
order byte, bits 9 to 12, polarity and overrange high order byte) are accessible under
control of the byte and chip enable terminals as inputs. These three inputs are all
active low, and are provided with pull up
resistors to ensure an inactive high level
when left open. When the chip enable
input is low, taking a byte enable input low
will allow the outputs of that byte to
become active (three-stated on). This
allows a variety of parallel data accessing
techniques to be used, and enables the
converter to be interfaced directly, either
as 110 or bv memory mapping, to any
microprocessor system with an 8-bit,
12-bit or 16-bit word length.
Handshake mode. The handshake output
mode is provided as an alternative means
of interfacing the ICL 7109 to digital systems. where the NO converter becomes
active in controlling the flow of data
instead of passively responding to chip and
byte enable inputs. This mode is designed
to allow a direct interface between the ICL
710<) and industry-standard u.a.r.t.s (such
as the Intersil C.m.o.S. u.a.r.t.s. 1M 64(2/3)
with no external logic required. When triggered into the handshake mode. the ICL
710<) provides all the control and flag
signals necessary to sequence the two bytes
of data into the u.a.r.t. and initiate their
transmission in serial form. This greatly
eases the task and reduces the cost of
designing remote data acquisition stations
using serial data transmission to minimise
the number of lines to the central controlling processor.
Entrl" into the handshake mode is controlled'bl" the MODE input. When the MODE
terminal' is held high. the ICL 7109 will
enter the handshake mode after new data
has been stored in the output latches at the
end of every conversion performed. The
MODE terminal may also be used to trigger
entrl" into the handshake mode on
demand.
In this mode. the SEND input is connected to the CART TBRE output so that the
ICL 7 J()I} can detect when the u.a.r.t. is
ready for more data. The CE/LOAD pin
hecomes an output strobe and' is connected
to the u.a.r.t. TBRL input to clock data into
the u.a.r.t. HBEN and LBEN also become
outputs which identify the high and low
bytes respectively. Figure 3 shows the output sequence.
A"uming th~ u.a.r.t. transmitter buffer
r~gi"~r is ~mpt\". the SEl"D input will be
high when the handshake mode is entered
aft~r new data is stored. The ('E'LOAD amI
HBES terminals w ill go low after SEND is
sensed. and the high order bl"te outputs
become active. When CE/wAo goes high at
the ~nd of one dllCk period. the high order
bvt~ data is clocked into the u.a.r.t. transniitter buffer register. The u.a.r.t. TBRE output will now go low. which halts the output
Cl"cle with the HBP;; output low. and the
high order byte outputs acti¥l .~ :

L- __....1.......... . . - - -

Integrator
output

I AZ phase 1

Zero crossing
detected

;"'" _ ...I"'Ji,.--,'c-_ _ _....J._ _

I I nt phase II I

I

AZ

[1I" "UU1..fL J1.nIlfL Jl.flIlI1-f "l..n..n..f111J
Internal latch :
I
I
n
I
I
I
I
I

I

I

I

I

I

I

I
I

II
I

I

I
I

4

~

Internal clock

I

Status output I

I

I
2048
I
Fixed
foo--counts~ 2048

I

min.

I

counts

"I_

t-...----I
Number of counts to zero crossing/"
proportional to Vln

.

I
I
4096 counts~
max

After zero crossing,
analog section will
be in autoz~ro
configuration

Fig. 2.
Zero crossing

Integrator
output
Internal
clock
Internal
latch
Status
output
Mode
input
I riternal
mode
Send input

UAAT
norm

:~~::::~~~~~

(UAAT TBAEI----J
CE/LDAD output-----+--{
(UAAT TBALl

~,~~~~::-------------------+.i._-1-{

Data valid

t __________ _-i

LBEN
I
Low ~~::---------+- _~

=

= Dont care

-1------- -

---:--1---

Data valid

~-~---

Three state high Impedance

Fig 3

mitter buffer register. the TBRE returns
high. On the next ICL 71 (II} internal clock
high to low edge. the high order byte
outputs are disabled. and one-half internal
clock later. the HBEN output returns high.
At the same time. the CE/l.OAD and LBEN
outputs go low. and the low order hyte
outputs become active. Similarly, when the
CE/l.OAD returns high at the end of one
clock period. the low order data is clocked
into the u.a.r.t. transmitter buffer register.
and TBRE again goes low. When TBRE
returns to a high it will be sensed on the
next ICL 710lJ internal clock high to low
edge. disabling the data outputs. One-half
internal clock later. the handshake mode
will be cleared, the the CE/LOAD. HBE·N. and
LBEN terminals return high and stay active
(as long as MODE stays high).

Status output
During a conversion cycle. the STATUS
output goes high at the beginning of Signal

45

Integrate (Phas" II). and

!!"" I""

one-half

clock period after nev" data from the ,.'on-

version has been stored in the output
latches (Sec Fig. ~ for detail, of this timing). This signal n"" be used a' a "data
valid" flag (data nevcr changes while
STATUS is low) to drive interrupts. '" for
monitoring the ~tilfU~ of the l'Ollverter,

When RUl"IHOl.ll i, held hi~h or left
open (it has an internal pull-up resistor)
the 71 (II} converts continuousl\". taking
III I}~ clock cvcles for each l"
~

~

.. ..
-'"
..
'g g.
~

'-

.;?=>

I
I
I
I

IM6402/3
CMOS UART
TSRL
DRR

Therefore:- R

RBR
1-8

D,

I

.- 0
'0-

D2

cx>i!

T8R
1-8

(

.. 0

go.

'~l

DR
I

AQ.
SBb1.2

eS

RBR
1-3

u..

=

't, where AI = 4ps.

By this means. the zero offset is cancelled (the system works for both input
polarities). One error is being offset with
another. and the two may not track with
temperature. so this method is not to be
relied on for· wide temperature range
applications.
The ICL 7109 has shown itself to be one
of the most versatile and cost effective AID
converters on the market, replacing existing 12-bit converters, as well as creating new applications which previously had
been the domain of V to F converters and
other devices.
ow

47

Understanding the Auto-Zero
and Common Mode Performance
of the ICL7106/7107 /7109 Family
1. INTRODUCTION

2. Signal Integrate Phase
During signal INTegrate, the auto-zero loop is opened, the
internal short is removed, and the internal input high and low
are" connected to the external pins. The converter then
integrates the differential voltage between INHI and INLO for
a fixed time. This differential voltage can be within a wide
common mode range - within one volt of either supply. If, on
the other hand, the input signal has no return with respect to
the converter power supply, INLO can be tied to analog
COMMON to establish the correct common-mode voltage.
At the end of this phase the polarity of the integrated signal is
determined.

Most of Intersil's one chip AID converters offer differential
input, differential reference and separable analog and digital
ground references. The price of all this freedom, of course, is
technical vigilance, and this note is intended as a defense
manual against the potholes and landmines it makes
accessible. The discussion is based on the ICL710617, but
applies in largu part to the ICL711617, the ICL7126, the
ICL7109, and to a lesser extent to the ICL7135.

2. GENERAL DESCRIPTION
Figure 1 shows the Block Diagram of the Analog Section for
the ICL7106 and 7107. Each measurement cycle is divided
into three phases. They are (1) auto-zero (A-Z), (2) signal
integrate. (I~T\ and (3) deintegrate (DE).

3. De-Integrate Phase
The final phase is DE-integrate, or reference integrate. Input
low is internally connected to analog COMMON and input
high is connected across the previously charged reference
capacitor. Circuitry within the chip ensures that the capacitor
will be connected with the correct polarity to cause the
integrator output to return to zero. The time required for the
output to return to zero is proportional to the input Signal.
Specifically the digital reading displayed is

1. Auto-Zero Phase
During Auto-Zero three things happen. First, input high and
low are disconnected from the pins and internally shorted to
analog COMMON. Second, the reference capacitor is
charged to the reference voltage. Third, a feedback loop is
closed around the system to charge the auto-zero capacitor
CAZ to compensate for offset voltages in the buffer amplifier,
integrator, and comparator. Since the comparator is
included in the loop, the A-Z accuracy is limited only by the
noise of the system. In any case, the offset referred to the
input is less than 10 ,.V.

1000 ( Vin )
Vrel.

CAEF

RINT
CAEF

r------

REF HI

REFLO

CREF

y+

BUFFER

1
:

y+

1
I

1
I

10J.l_

1

_ll~~'t~~-r--- TO DIGITAL SECTION

I
'31

INHI~~-{~~--~--~~--~----~
I

tNT

1
1
1
1
'32

COMMON~~----~--~---4----~

1

INLO~'~30~~~____~______________~________________~
I _________________________
.NT
L

'!! ____________________________________ _
y-

Figure 1. Analog Section of 710617107

48

3. CMRR AND COMMON MODE VOLTAGE
EFFECTS

2000 (VREFLO CS1 + VREFHI CS2) '"
VREF CREF

There are three basic voltages applied to the ICL710617, etc.
which can give "common mode voltage" consequences.
These are indicated in Figures 2, 3, and 4 which show the
analog section in the phases described above. The choices
are 1 \ of reference voltage source to COMMON, 2) of input
voltage source to COMMON, and 3) of COMMON to (digital)
supply voltage.

2000 VCM ICS1 + CS21 (counts)
VREF CREF
For CREF = 0.1 pF, Cs = 15pF, VCMIVREF = 10, this can give
two counts of error, but ifVREFLO =0, and CS2 is 5 pF, the error
is 0.1 counts, lost in the nOise level. In the latter case (a very
common application condition) CS1 does not contribute any
errors, so putting the "outside foil" of the reference capacitor
to this side will minimize roll-over. Also increasing CREF
(without corresponding increases in Cs) will reduce rollover. Note that stray capacitance to the buffer output is also
unimportant if either REFHI or REFLO is at COMMON.

During Auto-Zero, the outputs of the buffer, integrator, and
comparator are all within various offset voltages of analog
COMMON. These are marked on Figure 2, which shows the
Auto-Zero phase. For the remainder of the discussion, these
offset voltages will be ignored, since they are merely added to
other voltage changes described. The non-inverting inputs of
the buffer and integrator are also tied to analog COMMON,
so it is convenient to describe all these voltages with respect
to COMMON.

2. Input Voltage to COMMON
First, the direct CMRR of the buffer and integrator op amps
will themselves lead to a scale factor error and an offset if
INLO is not at analog COMMON. Higher order CMRR terms
are generally negligible, and this first order term is very small
for most devices. It can be adjusted out in most applications
with a reference voltage adjustment. More serious is the
effect of stray capacitance to ground of the integrating and
auto-zero capacitors, and the AZ pin, CS4 and CS3 in Figure 2.
The AZ pin will swing from COMMON to INLO (Figure3) and
CS3 will have to be charged through CAZ, giving an error
voltage on CAZ, during the integrate phase, of:

1. Reference Common Mode Voltage to COMMON
The reference capacitor is recharged during the Auto-Zero
time; the stray capacitance shown in Figure 2 as CS1 and CS2
will also be charged. During DE-integrate (Figure 4) the
reference capacitor is switched so that one or the other of
its terminals is at analog COMMON. This will cause chargesharing with the stray capacitances on the other terminal. In
particular, a common mode voltage on the reference input
(with respect to COMMON) will give a roll-over error, since
the effective DE-integrate reference will be higher in one
polarity than the other. The ideal here is for (VREFHI + VREFLO)
= 2 VANCOM, at least for equal stray capacitances, but this is
inconvenient in most applications. The roll-over error
contribution at full scale (ignoring a second order term) is

CS3

6. VAZ = VINLO CAZ

This acts as an offset voltage referred to the input, and is most
serious for small ratios of full-scale input voltage to common
mode voltage: For CAZ = 0.47 pF, CS3 = 10pF, VINLO =2V, the
offset will be 40 pV, or 0.4 counts for 200 mV full scale input.
This charge is recovered in the transition back to COMMON

r--l :!.!!,EFH;.;;.I_ _ _ _III-_ _ _vR~~~1 ~-..,
-J-_-

CS1

CREF

REF HI

CREF+

r-----I

i

3.

CS2

REFLO

CREF -

-J:.BUFFER

36

y+

I

I

I
I

10~a

.>t::-- TO DIGITAL SECTION

I
I
131
IN HI ~+__(~_-__t-_ pol is 0.6 counts. A
small increase in stray capacitance or reduction of integrator
swing will give a significant "gap" in the readings, as shown in
Figure 5. This effect, the only one causing significant nonlinearity, can be reduced by guarding the integrating and
auto-zero capacitors and resistor with either BUFFer out or
INTegrator out pins in so far dS possible. This can readily
be done on a PC board by simple extension of the traces
leading from those pins to the three components, as
suggested in Figure 6. Note that excessive capacitance
across RINT will increase the width of the zero reading (see

3. Analog COMMON to digital supply voltages
The COMMON line on the ICL710617 family of devices
provides a convenient ground-return point in many
applications; particularly with floating (battery) supplies.
However, in a fixed supply environment, improved integrator
swing (improving many system parameters) can be achieved
.if COMMON is pulled more negative, and the circuit has been
set up to allow this. The effects described above are all
independent of the actual level of COMMON, but the next
one is not!
The DE-integrate phase should ideally terminate when the
output of the comparator returns to the value it had during
Auto-Zero (analog COMMON), but will act.ually terminate
when the output passes through the logiC threshold of the
zero-crossing gate and flip-flop combination. The "free"
analog COMMON voltage is very close to the logic threshold,
giving a negligible error, but if analog COMMON is pulled
negative, zero crossing will be detected late for positive
inputs, (reading high) and early for negative inputs (reading
low), this leads to a (pOSitive) offset. The polarity detection
sees the same influence, so no nonlinearity results. The
magnitude of this offset depends on comparator gain
(typically 7-8K, but as low as 3K in some devices) and F.S.
integrator swing;

+,

+,
+1
ACTUAL

10

I-I
r--.J

+1

+2

+3

+4

OFFSET (COMMON) = 2000 (VCOMMON - VTH)
VINTFS AVCOMP

~1

I

I

.... __ J

I "IDEAL"
I
_J

-2

With a 2V swing and 3K gain, this will contribute 1/3count per
COMMON negative volt. This can be used to measure
comparator gain, at least with moderate accuracy, which is
otherwise hard to do. Obviously, the offset can be minimized
by maximizing the integrator swing. The comparator gain
varies from device to device, and is limited also by the need to
keep the comparator fast. Various improvements in this gain
have been made, and will probably continue to be made in the
future, but this offset should be considered carefully if
COMMON is to be moved away from its "free" location, or if
the logic supplies are altered.

-3

·4

DIGITAL READING

Figure 5. "GAP" in readings due to VINLO # COMMON
(a bad case shown)

51

4. The Auto-Zero Loop Residual
During the Auto-Zero phase, the converter self-corrects for
all the offset voltages in the buffer, integrator, and
comparator.

Note; however, that we have assumed a zero-crossing
actually occurred. lithe input is overloaded (past full scale),
DE-integrate will terminate with a substantial residual
voltage remaining on the integrator capacitor. The maximum
value of this residual depends on the total possible swings of
buffer and integrator, as compared to the "full scale" values
used. In general, we may treat this case as corresponding to a
large negative value of cx.

This section covers a normally undetectable, but under some
circumstances significant, error generated in the auto-zero
system. A similar effi'lci which occurs in the 2-chip systems
has been discussed previously (see A030, Appendix A), but
the details and remedies are sufficiently different to warrant a
separate discussion.

The immediate effect of closing the auto-zero loop may be
seen by examining Figure 7. We may consider the
comparator as acting as an op-amp. Under these conditions:
the voltage across the auto-zero impedance is high, and the
(nonlinear) impedance is low; on the other hand, the initial
voltage across the integrating resistor is zero.

The relevant circuit to be discussed is shown in Figure 7 and
the major cycle waveforms in Figure 8. Let us first assume
that the prior auto-zero cycle has been indefinitely long, or is
otherwise ideal, so that the conversion starts with no residual
error on the auto-z.ero capacitor. The integrate and DEintegrate cycles will be classically perfect to the point at
which a zero-crossing actually occurs (at the output of the
integrator). However, from this point two delays occur; first
the comparator output is delayed (due to comparator delay)
and secondly the zero-crossing is not registered until the
next appropriate clock edge. (For further discussion of this,
see Application Note A017). Atthis point, the circuit is returned to the auto-zero connection (logic and switch delays may
be absorbed in comparator delay as far as our discussion is
concerned). The net result is that the integrator output
voltage will have passed the zero-crossing point by an
amount given by

Thus, the auto-zero capacitor will be charged rapidly to
exactly cancel the residual voltage, as shown in Figure 9. The
output of the integrator is now at the correct position, butthe
auto-zero and integrator capacitors have shared the original
error. The junction point of the two capacitors and resistor
has been moved by a portion of the original residual voltage,
given by:
VAZI

= Vires

CINT
)
( CAZ
CINT

+

(4.1)

CAZy
~l~
'NTICD.JI-'

+

Vires = ±VIFS (CD
cx)
.
CFS

INTEGRATOR
OUTPUT

where 0'5 cx '5 1 is the variable delay, CD is the fixed delay,
is the full scale count in units of ~Iock pulse periods, and
VIFS is the full scale integrator swing in volts.

CFS

AUTO·
ZERO
F.8./2
COUNTS

Note: In all subsequent discussions, "C" indicates a
capacitor, while "c" denotes a number (not necessarily an
integer) of counts.

I

SIGNAL
INT.
F.8.12
COUNTS

REFEREN~E

INTEGRATE
FULL SCALE
COUNTS MAX.

:---1

FULL MEASUREMENT CYCLE
2 F.S. COUNTS

The range of this residual voltage corresponds to the
integrator swing per count, and is independent of inputvalue,
except for polarity.

Figure 8. Major Cycle Waveforms

HINT

CAl
BUFFER

INTEGRATOR

ZERO
CROSS

Q

DET.
ZERO
CROSSING
FF

CL

L..----CL

AZ

POL.

Figure 7. The Analog System (simplified to show only Auto-Zero connectionsl

52

This voltage will decay with a tim'e constant controlled by the
integrating resistor and the two capacitors, while the autozero capacitor is easily kept in step owing to the high
comparator gain, Thus, at the end of the auto-zero time,
tAl = CAl tcp, the residual will be reduced to:
V

This residual voltage on the auto-zero capacitor effectively
increases the magnitude of the input voltage as seen on the
output of the buffer. Thus, converting this voltage to countequivalents,
c

( - ICAll Itcpl )
- V
Alras - AZI exp RINT I CINT + CAl I

=

V

(4.4)

CINT + COE)
CINres = CAZres (
CINT
so that

(cx + CD)
CINT
- V
Alres - IFS ~ (CAl + CINTI

(4.2)

c

-CAl tcp
)
exp ( RINT (CINT + CAli

VAl res

= Vires

0

(4.3)

-----.:'?-i----i-=_-.....,._------_

I
I

I
I

1
I
,
1
I ~
COMPOIP -----i'-""*'!~=
1 _ _;;::",_ _ _ _ _ _ _ __

....
n
,
-K:''-ciI

vit
H-

CL

DETECTED ZERO-CROSSING

IT

ZCFF

I

1

AlZ _ _ _

(1 + 0)

(4.5)

C
CAl • VIFS • _1_)
\ CINT VBFS
1+

CAli

1

I

-!'-I~J

= CAlres +

VIFS ICX+CDi
VBFS ~

(4.6)

By combining equations !4.41 and (4.61 we find, for the
equilibrium· condition,

IIC---"

------ioI!4~-+':/

VBFS

For the normal in-range condition, two things should be
noted here. First, this residual acts to increase the input
voltage magnitude, and secondly, a small increase in input
voltage tends to decrease the magnitude of the residual (until
the result count changes). These effects lead to "stickyness"
in the readings; suppose, in a noise-free system, that the
input voltage is at a level where the residual is a minimum; the
detected zero-crossing follows the true one as closely as
possible. A minute increase in input voltage will cause the
zero-crossing to be detected one pulse later, and the residual
to jump to its maximum value. The effect of this is a small
increase in the apparent input voltage; thus if we now remove
the minute increase, the residual voltage effect will maintain
the new higher reading; in fact we will have to reduce the
input voltage by an amount commensurate with the effective
residual voltage to force the reading to drop back to the lower
value. In more detail, we should consider the equilibrium
conditions on the auto-zero capacitor. Clearly, the voltage
added at the end of reference integrate must just balance that
which decays away during the auto-zero interval. So far the
relationships we have developed have assumed a zero
residual before the conversion, but in the equilibrium
condition the residual given byequation (4.41 remains, and at
the end of conversion, the new amount, given by equation
(4.1), is added to this, so we start the "auto-zero decay"
interval with

"TRUE" ZERQ-CROSSING

I
I

CINT

Note that CDE is equal to the displayed result, except for overrange conditions, when it is equal to CFS and the first
bracket becomes 3. Also, CAl = CINT; and this expression, so
substituted, determines the overrange residual performance.

CINT, for convenience, and will

( -+1
1) exp (-CAl
V VIFS
1+ )
o
CINT BFS I
01

= (1 + COE) (VIFS ) (cx + CD)

1J/

Now RINT CINT is controlled by the buffer swing, VBFS, the
integrator swing, VIFS, and the integration time tiNT = CINT tcp,
so that
VBFS
VBFS/RINT • tiNT = CINT VIFS, or RINT CINT = CINT VIFS tcp
Also we may write CAl =
then obtain

INres

exp

For the overrange case, we may again assume a large
negative cx value.

C.,

VAl res CFS _ VIFS ,CX + CD'
VBFS·
- VBFS ~

Since this voltage also subtracts from the reference, its effect
at the input is magnified in the ratio

For the residual left after a zero-crossing, we may further
refine this to:

"ZERO"

=

(CAl
VIFS
1)
exp ,- CINT • VBFS • 1 + Q

(
CINT)
((-CAli (tcpl
)
Ires CAl + CINT exp RINT (CINT + CAli

V

Alres

----

CAlres = ± VIFS I cx + CD'

VBFS~

ALL ANALOG VOLTAGES ARE WITH RESPECT TO THEIR "AUTO-ZEROED" VALUE

VIFS
[ exp { + CINT CAl
VBFS 11 +
Figure g. Waveforms at Beginning of Auto-Zero Interval

53

}
Q'

-1

J.1

Once again, the effect of this at the input is multiplied by the
ratio of total input integrate times, so that, under equilibrium
conditions,
CINr.s = ± VIFS (1
VBFS

+COE)
CINT

(cx + Col
(1 + <>1

I.• I--+---Io--.....,~........,Jc--.+-----+---I
(4.7)

[ ex

P

{

CAZ VIFS
} 1l-'
CINT VBFS (1 + <>1 - ~

•. II--t--I--''''''''cf'''<:--l',<:--~~+---I

Those expert at skipping to the end of the difficult bit will
recognize that as the final equation, in terms of complexity.
So let us now see what it means. Clearly, the error term is
greater, the larger cOE/clNT, and the smaller cAz/clNT. Forthe
devices considered here (except some applications of the
ICL71091 these are both worst case near full scale input,
where cOE/clNT ~ 2 and cAz/clNT ~ 1.

1."J-+--t--+--4\-\---f--lI----t--\---l
1O"J-+--J--+--4----lt-!\I--\---t---\--l

Substituting these, we find the worst case
(cx + col
VBFS (31 (1 + <>1

_ + VIFS

CINre. - -

..m(,)
VBFs
1+0

(4.8)
} 1J"'
[ exp { VBFSVIFS
(1 + <>1 -

Figure 11. Auto-Zero Loop Residual vs. Integrator/
Buffer Swing for Overload and Capacitor Ratio

Recall that CD is fixed; and cx must be between 0 and 1. The
expression is now a function purely of the ratio of integrator
and buffer full scale swings, and the ratio of auto-zero and
integrator capacitors, <>. The effect of the latter ratio is mixed;
a larger value reduces the initial error, but increases the time
- constant for its decay. The relationship is plotted in Figure
10 and shows the desirability of keeping the integrator swing
higher than the buffer swing. Note also that a lower
capacitance ratio a always improves the residual. However,
both noise and the .common-mode effects discussed in
Section 3 above require a large auto-zero capacitor, and a
compromise must be reached. In general, if the full scale
input is small, a large CAZ is needed, but for larger full scale
inputs, a smaller value is best. Note also that the comparator
delay (CD in equation (4.8)) is also effectively enhanced. This
has the effect of shrinking the zero somewhat more than

3.

D~

2. 5

The effects of noise should be mentioned here. The worst
case value of residual shown in Figure 10 assumes a very
gradual approach to equilibrium, and any noise spike
causing the reading to flash to the next value will destroy this
carefully established residual value! Thus, for any system
with noise of 1/3 count or more, the effect is greatly reduced,
and even 1/10 count of noise will restrict the actual hysteresis
value found in practice. The detailed analysis of the autozero residual problem in the presence of appreciable noise is
left as an exercise for the masochist.
For overrange conditions, the controlling equation is (4.5)
with the appropriate substitutions for the count ratios.
Specifically, putting COR forthe count-equivalent value olthe
overrange above full scale, and ignoring CD, we obtain:

~ ~ r---.
" ,

, ,,'"
,\

r-.,,"

•

2.

(VIFS) (COR)
[VIFS
1 ]
C INres -- 3 \VBFS
1 + a exp - VBFS • 1 + a

~~3

\

(a~.I'

c~:.

normally occurs. Since this term changes sign with polarity,
the converter will have a tendency to keep the current sign at
zero input.

,,

1.5

'c'

This is plotted in Figure 11, and shows the very strong
dependence on the integrator to buffer swing ratio. The
direction is the opposite of that for the post-zero-crossing
residual, as well as being normally much larger. A positive
overrange on one reading will tend to make the next
reading(s) too negative, and vice versa. The influence on
second and even subsequent readings after an overrange
can also be appreciable in some cases. The miss-charge
trapped on the auto-zero capaCitor during the first
conversion after an overrange will still be there at the end. If
this conversion is in-range, we may ignore cx and CD and just
consider the continuation of the exponential decay during
the following Auto-Zero phase. Thus, at the beginning of the
second conversion, the residual will have been reduced to:

\

\ \

\

I.D

~,

,

D.5

D

o

0.1

O.S

1.0

,, 1\ 1\\
- I- .....\ ~
..
2.0

4 ••

.

(4.9)

11.0

CAZ
VIFS
1 ]
CAZres 2 = CAZre. exp [ - - c • - V • -1-INT
BFS
+a

Figure 10. Auto-Zero Loop Residual vS. Integrator/Buffer
Swing and Capacitor Ratios (worst easel

54

+5V
OR

OR

+5V

OR

lOOK!!

30

5TTS

ICM7555
ICL7109

30

ICL7109

BUF

RINT

31

100KJl

r-

-5V

CO:p~g~~LR :;:

5

1V-

••

+5V

3.
31
3.

AZ

10Kll

INT

O.22/-1 F

OV

5rr5
1000 pF

Figure 12. Circuits to Reduce Gverrange Residual on ICL7109

where CAZres is given by equation (4.4). This will be similar for
subsequent in-range conversions. The effect at the input is
again increased by the time ratio of DE-integrate and
INTegrate, and so we may write, for the effective error at the
input on the nth conversion after the overrange:

ICL7106/7 which do not provide the necessary signals.
Generally, however, these devices are not used in
multiplexing applications.

CINresn =
(1

+ ~I~~)

SUMMARY

(~;~) (1c~Aa) [ex p (- ~I~~ . ~;~ . 1 1a)J n

This note has described the most common behavior patterns
that cause concern and/or confusion among users of the
ICL710617 and similar products, and their origins. Hopefully,
it will help alleviate or eliminate any consequent applications
problems with this family of devices. Naturally, some parts
will not show all of the effects; for instance, the ICL711617
and ICL7135 cannot suffer from large common-mode
voltages between reference and COMMON, because no such
voltage can be applied, and the ICL7135hasa modified autozero sequence that alters the residual effects of Section 4.

(4.10)
This also is plotted in Figure 11, for various values of n
against VIFS
1 ,for worst case conditions (an overload
VBFS 1 + a
followed by several full scale conversions).
The residual can be reduced for devices, such as the
ICL7109, which provide indications of overrange conversions and auto-zero phase (OR and STATUS in the ICL7109)
by reducing the integrator time constant during all or part of
the Auto-Zero phase after an overrange conversion. This can
be done by shorting out all or part of the integrating resistor
RINT by a suitable analog switch. A circuit to do this is shown
in Figure 12 for the ICL7109. Care should be taken to ensure
that the switch does not cause errors due to charge injection
into the capacitors when going OFF. Alternatively the clock
can be slowed down or stopped, or Run/Hold used to extend
the Auto-Zero phase under the same conditions. These
techniques are much harder to apply to devices such as the

PB

55

DATA ACQUISITION & CONVERSION HANDBOOK

Know your converter codes. When you work
with aid and d/a converters, there are many input and output
codes to choose from. Here are some characteristics of each.
The right digital code can help simplify system
design when analog-ta-digital and digital-to-analog converters are used in the system.
While some custom aid and d/a converters use
special codes, off-the-shelf units employ one of
a few common codes adopted by the industry as
"standard" (Table 1). Understanding which code
to use, and where, is the key to a simpler system
design. And the added benefits with a standard
code include lower cost of the converter and a
wider choice of vendors.
Many designers are perplexed about application. There are unipolar codes-straight binary,
complementary binary and binary coded decimal
(BCD). There are bipolar codes-sign-magnitude binary,. sign-magnitude BCD, offset binary,
one's complement and two's complement. Other
decimal codes include excess-three, 2421, 5421,
5311 and 74-2-1. And there are also reflective
codes-such as the Grey code; and error-detecting codes-like the Hamming.
All codes used in converters are based on the
binary numbering system. Any number can be
represented in binary by the following
N == an2n + an_12n-, + .... +a:!22 + a 121 + au2°,
where each coefficient a assumes a value of one
or zero. A fractional binary number can be
represented as
N = a,2-' + a,2-' + a,2-' + .... + a,,2- n •
A specific binary fraction is then written, for
example, as 0.101101. In most converters it is
this fractional binary number that is used for
the basic converter code. Conventionally the fractional notation is assumed and the decimal point
dropped.
The left-most digit has the most weight, 0.5,
and is commonly known as the most-significantbit (MSB). Thus the right-most digit would have
the least weight, 1/2 n , and is. called the leastsignificant-bit (LSB).
This coding scheme is convenient for converters, since the full-scale range used is simply
interpreted in terms of a fraction of full scale.
For instance, the fractional code word 101101
has a value of (1 x 0.5) + (0 x 0.25) + (1 x

Table 1. Summary of coding for aid
and dla converters
co
-0
a.

-c

:::>

~

co
-0

D I a converters
Straight binary
BCD
Complementary binary
Complementary BCD
Offset binary
Complementary off.
binary
Two's complement

iii

A I d converters
Straight binary
BCD
Straight bin, invert.
analog
BCD, inverted analog
Offset binary
Two's complement
Offset bin, invert.
analog
Two's compl, invert.
analog
Sign + mag. binary
Sign + mag. BCD

0.125) + (1 x 0.0625) + (0 x 0.03125) + (1
x 0.015625), or 0.703125 of full-scale value. If
all the bits are ONEs, the result is not full scale
but rather (1 - 2-") x full scale. Thus a 10-bit
d/a converter with all bits ON has an input code
of 1111111111. If the unit has a +10-V full-scale
output range, the actual analog output value is
(1 - 2-") x 10 V = +9.990235 V.
The quantization size, or LSB size, is full scale
divided by 2 n-which in this case is 9.77 mY.
Analyzing digital codes

The four most common unipolar codes are
straight binary, complementary binary, binarycoded decimal (BCD) and complementary BCD.
Of these four, the most popular is straightbinary,. positive-true. Positive-true coding means
that a logic ONE is defined as the more positive
of the two voltage levels for the logic family.
Negative-true logic defines things the other
way-the more negative logic level is called ONE
and the other level ZERO. Thus, for standard
TTL, positive true logic makes the +5-V output
logic ONE and 0 V a ZERO. In negative true
logic the +5 V is ZERO and 0 V is ONE.
All four of the codes are defined (Table 2) in
terms of the fraction of their full-scale values.
Full-scale ranges of +5 and +10 V are shown_
with 12-bit codes.

56

Table 2. Unipolar codes-12 bit converter
Straight binary and complementary binary
Scale

+ 10 V FS

+5 V FS

Straight binary

+ FS -1 LSB
+ 718 FS
+3/4 FS
+ 5/8 FS
+1/2 FS
+3/8 FS
+1/4 FS
+1/8 FS
0+1 LSB
0

+9.9976
+8.7500
+ 7.5000
+6.2500
+5.0000
+3.7500
+2.5000
+1.2500
+0.0024
0.0000

+4.9988
+4.3750
+3.7500
+3.1250
+2.5000
+ 1.8750
+ 1.2500
+0.6250
+0.0012
0.0000

111111111111
III 0 0000 0000
11 00 0000 0000
1010 OJOO 0000
1000 0000 0000
0110 0000 0000
0100 0000 0000
0010 0000 0000
0000 0000 0001
0000 0000 0000

+ lOV FS

+5V FS

Binary coded decimal

+9.99
+8.75
+7.50
+6.25
+5.00
+3.75
+2.50
+ 1.25
+0.01
0.00

+4.95
+4.37
+3.75
+3.12
+2.50
+ 1.87
+1.25
+0.62
+0.00
0.00

I

Complementary binary
0000
0001
0011
0101
0111
1001
1011
1101
1111
1111

I

0000
1111
1111
1111
1111
1111
1111
1111
1111
1111

0000
1111
1111
1111
1111
1111
1111
1111
1110
1111

BCD and complementary BCD
Scale
+FS-1 LSB
+ 718 FS
+3/4 FS
+5/8FS
+1/2 FS
+3/8 FS
+1/4 FS
+ 1/8 FS
0+1 LSB
0

II
I

i

1001
1000
0111
0110
0101
0011
0010
0001
0000
0000

Dla and aId converters: The
operating basics

Complementary BCD

I

1001
0101
0000
0101
0000
0101
0000
0101
0001
0000

0110
0111
1000
1001
1010
1100
1101
1110
1111
1111

0110
1000
1010
1101
1111
1000
1010
1101
1111
1111

0110
1010
1111
1010
1111
1010
1111
1010
1110
1111

For the ideal dla ton\"ertel', there is a aneta-one tOl'respondente between i npu t and all tput. but for the aid there is not. beeauseany
analog input within a range of Q will giw the
same output ('ode word, Thus, fol' a goh'en code
w01'd, the tOl'l'csponding input analog yt.thH-'
could ha,'e errors of from U to ±Q/2. This
quantization errol' can be I'eduted only by an
intl'ease in l'on\"cl'tel' resolution.
Although the analog input 01' output l'ang-l'S
arc arbitrary, some of the standardized l'angl's
indude 0 to +5. 0 to + 10. 0 to
5 and U to
10 V fo1' unipola.r converters, and
2.5 to
5 to 5 and
HI to + 10 \. for bipo!;,,·
+ 2.5.
units. Many units on the market are programmahIE:> types in which external pin conm'ctions
dl,t('}"minc the range of operation.

The basic transfer characteristic of an ideal

d/a com'erter forms the plot shown in Fig. A.
The d/a takes an input digital <.:ode and <.:onY(,l't:-;
it to an analog output voltage or current.

1001
0111
0101
0010
0000
0111
0101
0010
0000
0000

Thi~

form of discrete input and di:-:<:I'l'te output
(quantized) gives the tram-liel' fUllction a
straight line through the tops of th,· \'('rtieal
bars. In general the analog \"ailies an' l'ompl(.>tl'I~·
arbitrary and a large number of binary dig-ital
codes tan be used. Analog full-:;tale tan bl' dl'fined as
25.2 to 85.7 \' as easily as 0 to 10 \'.
In practice. though. the industry has se!tied
on sen~l'al codes and very simple ranges for most
major appiitations. For instance. the transfer
ehal'atiel'h;tits in Fig. A are for a dla tonn.'~l'tel'
that uses a :l-bit unipolar binary ('ode and an
output defined only in terms of its full-seal"
\·aluE>.

The ideal aid converter (Fig. B I has a staircase transfer characteristic. Here an analog input voltage or current is convertcd into a digital
word. The analog input is quantized into n
levels for a converter with n hits I'e:-;olution.
For the ideal converter. the true analog "alu"
corresponding to a given output code word i:->
centered between two decision leve!!;. Thcl"P are
2' 1 analog decision levels. The quantitization
size. Q. is equal to the full-scale range of the
converter divided by 2 n ,

Illl~EClS10N
':

~

110

8

101

LEVEL

I

e:~

100
011
:::) 010

o

001
000

a

'

I

:

:

:

l, :,

J

:

:

,

,
I

I
I

"

I~Q:-::
'

:
FS

0.2:5

I

,

FS

05

,

I

0.75

INPUT VOLTA.GE

57

,

l :

I '
FS

I

F'S

DATA ACQUISITION 81 CONVERSION HANDBOOK

___ LOGIC IN----..

ISV

......--LOGIC IN--.............

0---1--+----.--1---

ISVo--____~-~----._-~-~

2.

1.2 VO - - - - - i l - - - - - - - f - - - - - -lOUT

1.2 Vo---t--------f--------

--+-----

-4.4 Vo---il---I----....
IOUT-

-ISVo---~-

_ _ _ _ _~-----_

ate output current in different directions. The resistor

1. Weighted current·source configurations for straight
binary (a) and complementary binary (b) coding gener·

weighting determines the output code.

Complementary-binary, positive-true coding is
also used in d/ a converters. This scheme is used
because of the weighted current source configuration employed in many converter designs.
Fig. 1 shows two commonly used weightedcurrent-source designs. The pnp version (Fig.
1a) delivers a positive output current with
straight binary positive-true coding. When the
logic input is ONE, or +5 V, the current source
is on, since the input diode is back-biased. Thus
the current from each ON weighted current
source is summed at the common-collector connection and flows to the output. A ZERO input
holds the cathode of the input diode at ground
and steals the emitter current from the transistor, keeping it off.
The use of an npn current source (Fig. 1b)
produces a negative output current with complementary binary positive-true coding. The pnp
transistors operate in the same way as before,
but each collector is connected to the emitter of
an npn weighted current source, which is turned
on or off by the pnp transistor. This basic

method finds common use in IC quad currentsource circuits.
Complementary binary, positive-true, coding is
identical to straight binary negative true; these
are just two definitions of the same code.
Straight-binary, negative-true, coding is commonly used to interface equipment with many
minicomputer input/output busses. Unipolar aid
converters most frequently use the straight
binary positive-true coding. They also use
straight-binary inverted-analog where the fullscale code word corresponds to the negative full
scale analog value.
Another popular code used in many converters
is BCD. Table 2 shows three-decade BCD and
complementary BCD codes used with converters
that have full-scale ranges of +5 or +10 V. BCD
is an 8421 weighted code, with four bits used to
code each decimal digit. This code is relatively
inefficient, since only 10 of the 16 code states
for each decade are used. It is, however, a very
useful code for interfacing decimal displays and
switches with digital systems.

IMS8

1

160-"""",V\o-+-"",,-,
32

64
128

DATA OUT'

2. Binary (a) and BCD (b) ladder networks in d I a con·
verters use the same weighting in the resistor quads but
different divider ratios.

3. MOst aId converters for bipolar operation are offset
by a current equal to the ,value of the MSB. The half·
scale then becomes 100 ... o.

58

With dla converters, it is especially convenient
to have input decimal codes for use with such
equipment as digitally programmed power supplies. And, with aid converters, BCD is particularly popular for the dual-slope type for direct
connection to numeric displays.
BCD coding in converters can be achieved in
two ways: binary-tD-BCD code conversion or
direct weighting of internal resistor ladders and
current sources. Today it is almost aiways done
by resistor weighting schemes (Fig. 2). Each of
the weighted resistors gets switched to a voltage
source and thus generates the weighted current
for the amplifier. Fig. 2a shows an 8-bit binary
ladder network. Due to temperature-tracking
constraints, groups of four resistors are used.
Then the total resistance variation won't exceed
8-to-1.
In between the groups of four resistors is a
current divider composed of two resistors that
give a division ratio of 16 to 1 between resistor
quads. The BCD ladder configuration is similar,
with the same values in each of the groups of
four resistors. In this case, however, the current
divider has a ratio of lO to 1 between resistor
quads. Thus, because of the difference in internal
weighting, BCD-coded converters cannot be pinstrapped for another code; they must be ordered
only for BCD use.

derived from the internal voltage reference, so
it will track the other weighted current sources
with temperature.
For bipolar operation, this current source fs
connected to the converter's comparator input.
Since the current flows in a direction opposite
from that of the other weighted sources, its value
is subtracted from the input range. With the
weighted currents flowing away from the comparator input, the normal input voltage range is
positive. Thus the offsetting can $!hange a 0 to
+lO-V input range into a -5 to +5-V bipolar
range.
If the analog range is offset for a converter
with straight binary coding, the new coding becomes offset binary. This is the simplest code for
a converter to implement, since no change in the
coding .is required. Table 3 shows offset binary
coding for a bipolar converter with a ± 5-V input
range. All ZEROs in the code correspond to
minus full scale. The code word that was originally half-scale becomes the analog zero, lOOO
0000 0000. And all ONEs correspond to +5 V
less one LSB. Successive-approximation aid converters also have a serial, straight-binary output.
This serial output is the result of the sequential
conversion process, and it also becomes offset
binary when the converter is connected for bipolar operation.
Three other types of binary codes are shown in
Table 3, along with the offset binary. Of all
four, the two most commonly used are offset
binary and two's complement. Some converters
use the sign-magnitude binary, but the one's
complement is rarely used.
The two's complement code is the most popular because most digital arithmetic is performed
in it; thus most interfacing problems are elim-

Codes can be made bipolar

Most conve'rters have provision for both unipolar and bipolar operation by external pin connection. The unipolar analog range is offset by
one-half of full scale, or by the value of MSB
current source, to get bipolar operation (Fig. 3).
The current source, equal to the MSB current, is

Table 3. Bipolar codes-12 bit converter
Scale

±5 V FS

+FS-1 LSB
+3/4 FS
+ 1/2 FS
+ 1/4 FS
0
-1/4 FS
-1/2 FS
-3/4 FS
-FS+1 LSB
-FS

+4.9976
+3.7500
+2.5000
+1.2500
0.0000
-1.2500
-2.5000
-3.7500
-4.9976
-5.0000

Offset binary

Two's complement One's complement

111111111111 0111 1111
1110 0000 0000 0110 0000
1100 0000 0000 0100 0000
10 10 0000 0000 0010 0000
1000 0000 0000 0000 0000
0110 0000 0000 III 0 0000
0100 0000 0000 11 00 0000
0010 0000 0000 10 10 0000
0000 0000 0001 1000 0000
000000000000110000000

1111
0000
0000
0000
0000
0000
0000
0000
0001
0000

0111
0110
0100
0010
0000
1101
1011
1001
1000

1111
0000
0000
0000
0000
1111
1111
1111
0000

Sign· mag binary

1111
1111
0000
III 0
0000 11 00
0000 1010
0000' 1000
1111
0010
1111
0100
1111 '0110
0000 I 0111

-

,

1111
0000
0000
0000
0000
0000
0000
0000
1111

1111
0000
0000
0000
0000'
0000
0000
0000
1111

-

-Note: One's complement and sign magnitude binary
have two code words for zero as given below;
these are deSignated zero plus and zero minus:

One's complement
0+
0-

59

0000 0000 0000
1111 1111 1111

I

i

Sign·mag binary
1000 0000 0000
0000 0000 0000

I

DATA ACQUISITION,. CONVERSION HANDBOOK

Table 4. Inverted analog offset binary coding comparison
Scale

Normal analog
offset binary

Inverted analog
offset binary

+FS

Normal analog
compo offset binary

0000.00000000
1111 1111 1111

0000 0000 0001

1100 0000 0000

0100 0000 0000

0011 1111 1111

1000 0000 0000

1000 0000 0000

0111 1111 1111

-1/2 FS

0100 0000 0000

11 00 0000 0000

1011 1111 1111

-FS +1 LSB

0000 0000 0001

1111 1111 1111

1111 1111 1110

+FS - 1 LSB
+1/2 FS
0

-FS

0000 0000 0000

0000 0000 0000

1111 1111 1111

o

0

DIGITAL OUTPUT

4. For two's complement coding in a dla, the MSB
current·source must go to the oPPosite terminal from
the other weighted sources to avoid output glitches.

5. The inverted-analog dla converter (a) and the invert·
ed·analog aid converter (b) have negative·going analog
output and input values, respectively.

inated. The easiest way to characterize the two'scomplement code 'is to look at the sum of a positive and negative number of the same magnitude;
the result is all ZEROs plus a carry.
'Visually the only difference between two's
complement and offset binary is the left-most
bit. In two's complement code it is the complement of the left-most bit in offset binary.
This left-most bit is normally called the MSB;
in offset binary it is, in effect, the sign bit, and
is so called in the other codes. Thus two's-complement coding is derived froIl! offset binary
when the sign bit is complemented and brought
out as an additional output.

code words for zero, as shown in Table 3. Because of the extra code word used for zero, the
range of these codes is one LSB less than for
offset-binary and two's-complement 'Coding.
For positive numbers, one's-complement is the
same as two's-complement. The negative number
in one's-complement is obtained when the positive number is complemented. Signcmagnitude
coding is identical to offset binary for positive
numbers; negative numbers are obtained by use.of
the positive number with a complemented sign bit.
D a converters don't usually use two's complement coding. This is because it's hard to invert
the MSB weighted current source. If the logic
input is inverted, there is an extra digital delay
in switching the current source, and this causes
large output· transients when the current is
switched on arid off.
The other alternative is to change the direction
of the MSB current instead of inverting the
digital input. This is also difficult to do and
can introduce switching delays.
One satisfactory way of inverting the MSB is
shown in Fig. 4. Here a voltage output d /a converter that uses two's-complement coding has the
MSB current switched into the negative ampli-

Codinljl has its limitations

Both two's-complement and offset-binary codes
have magnitudes (if we temporarily forget about
the sign bit) that increase from minus full scale
to zero, and, with a sign change, from zero to
plus full scale. Both codes have Ii single definition
of zero. On the other hand, one's-complement and
sign-magnitude codes have magnitudes that increase from zero to plus full scale and from zero
to minus full scale. Both of these codes have two

60

output current. However, if a current-to-voltage
converter is used at the output, an inversion
takes place, and a normal analog output voltage
results.
In Fig. 6b, a d/a converter with positive output
current is used in an aid converter. Since the
dia output current is summed with the offset
and input current at the comparator input, a
negative input voltage is needed to balance these
currents. The analog input thus goes from plus
full scale to minus full scale for an increasing
output code. Normal analog coding is achieved
by use of an inverting amplifier ahead of the
analog input terminal.
Inverted analog coding is compared with the
normal offset binary coding in Table 4. This comparison shows that if the inverted analog offset
binary code is rotated around the zero of the
analog voltage, a normal analog offset binary
output results. If inverted analog offset binary
is compared with normal analog complementary
offset binary, the two codes will appear identical
except for an offset of one LSB. The relationship between these two codes can be expressed
as:
Normal analog complementary binary + 1 LSB
= Inverted analog offset binary.
Therefore a converter that uses one of these
codes can also be used for the other with an external offset adjustment of 1 LSB.

fier input terminal, while the other weighted
currents are switched into the load resistor and
positive input terminal. Thus opposite-polarity
output voltages are produced, and there are no
additional switching delays in the MSB.
One other code in Table 1 is the sign-magnitude BCD. This code, used mostly in dual-slope
aid converters, usually requires 13 bits for a
three-decade digital display. Of the 13 bits, 12
are for the BCD code and one for the sign bit.
An additional output bit for an overrange indication is generally supplied.
Another scheme in Table 1 is inverted analog
code. This is also called negative reference coding. While most converters use zero to plus full
scale as analog values; the inverted configuration uses zero to minus full scale values. The
coding then increases in magnitude when the
analog level .increases in magnitudll from zero to
minus full scale. For bipolar coding, normal
analog has an increasing code as the analog value
goes from minus full scale to plus full scale; inverted analog coding does the opposite-the code
increases as the analog value goes from plus full
scale to minus.
Why the need for this code? Fig. 5a shows a
dla converter that delivers a negative output
current. With bipolar operation and use of the
offset current source, the converter provides a
code ZERO that corresponds to plus full scale

GZ

61

DATA ACQUISITION lit CONVERSION HANDBOOK

The ICL71 04
A Binary Output AID
Converter for J.LProcessors
1. INTRODUCTION

The chip pair operates as a dual-slope integrating converter.
The conversion takes place in three stages, each with their
own configuration. In thelirst, or auto-zero phase (this is also
the "idle" condition), the converter self-corrects for all the
ollset voltages in the buller, integrator, and comparator.
During the second, or input integrate phase, the converter
integrates the input signal lor a lixed time (2'5 clock pulses
lor the -16 part, 213 for -14, 2" lor -12), The converter then
determines the (average) polarity 01 the input, and during the
third, or deintegrate (alias reference integratel phase,
integrates the relerence voltage in the opposite polarity, until
the circuit returns to the initial condition. This pOint is known
as the zero-crossing, and terminates the conversion process.
The time (number 01 clock pulsesl required to reach zerocrossing is proportional to the ratio 01 the input signal to the
reference. A more detailed discussion 01 the operation of the
dual-slope converter, including the ICL8052-ICL-710X
family, is given in Application Note A017 "The Integrating
AID Converter." Figure 2 shows the basic waveforms of the
Integrator.

The ICL7104, combined with the ICL8052 or ICL8068,
forms a memberollntersil's high performance AID converter
family. The 16-bit version, the ICL7104-16, performs the
analog switching and digital function lor a 16-bit binary AID
converter, with lull three state output, UART handshake
capability, and other outputs lor a wide range of output
interfacing. The ICL7104-14 and ICL7104-12 are 14 and 12bit versions. The analog section, as with all Intersil's
integrating converters, provides fully precise Auto-zero,
Auto-polarity (including ± 0 null indication), Single reference
operation, very high input impedance, true input integration
over a constant period lor maximum EMI rejection, lully
ratio metric operation, over-range indication, and a medium
quality built-in relerence. The chip pair also offers optional
input buffer gain lor high sensitivity applications, a built-in
clock oscillator, and output signals lor providing an external
auto-zero capability in preconditioning circuitry, synchronizing external multiplexers, etc., etc. The basic schematic
connections are shown in Figure 1.

O/RPOl161514 13 12 1110 9

a

7 6 5 4

3 2 1

--l
21
r-~~~~~~~~~~

I

I

VAEF

ANALOG

,NPUT

REF.
CAP

(2)

OPTION
16 BIT
PINS 23. 12, 13 NOT CONN.
14 BIT
PINS 23.10.11.13.12 NOT CONN. 12 BIT

1 AZ 1 INTEO, 1 DEINTEG.
MIN.

321<
8K
2K

321<
8K
21<

o· 64k
o· 16K
D' 41<

Figure 1: 8052A (8068A117104 16114112 Bit AID Converter.
INTEGRATION CAP.

PHASE 1--++ PHASE I I - t - - PHASE
AUTO ZERO I
SIGNAL
I
I INTEGRATE I
I

I
I

'11-

REFERENCE
INTEGRATE

~,~

0"-

i~

~

___ h.nnnn.. _______ _

I~I-~-~--

Find number
of clock

pu'.'

Number of ctoc:k pulses
proporUoMiI 10 YIN

Figure 2: Simplified Dual-Slope Converter and the Three Phases of a Dual-Slope Conversion.

62

CONVERT
CONTROL

This application note will first cover the digital interface of
the ICL8052!1CL8068)-ICL71 04 chip pair to digital systems of
various kinds, including microprocessors, using the three
state output capabilities (covered in Section 2) and the
handshake' system built into the 7104 (Section 3). Finally,
some (mainly) analog techniques to enhance the system
performance in certain applications are covered in Section 4.
An Appendix covers a normally undetectable 'but under
some circumstances significant error generated in the autozero system.

".
8052AI

7104
-16

....A

2. DIGITAL INTERFACE
(Without Internal Handshake)
The output format of the ICL7104 is extremely versatile, and
includes a full internal handshake capability, which is discussed in the next section. Here we will be concerned only
with the "normal" three state output lines. To disable the
handshake circuitry, the MODE pin (pin 27) should be tied
low Ito digital gndl.
In this mode, the most useful output-timing signal is the
STaTuS (STTS) line (pin 3), which goes high at the beginning
of the signal integrate phase. When zero crossing occurs (or
overload detection), new data is latched on the next clock
pulse, and 1/2 clock pulse later, the STTS line goes low.
Thus, the new data is stable on this transition. The Run/Hold
pin (R/H) (pin 28) is also useful for controlling conversions. A
more detailed description olthe operation olthis pin is given
in Section 4.8, but it will suffice to say here that if it is high,
conversions will be performed continuously, while if it is low,
the current conversion will be completed, but no others will
start until it goes high again. There are 18 data output lines
(16 and 14 on the 14-bit and 12-bit versions), including the
polarity and over-range lines. These lines are grouped in sets
of no more than 8 for three stated enable purposes, in the
format shown in Figure 3, under the control of the byte and
chip disable lines shown. To enable any byte, both the chip
disable and the corresponding byte disable lines must be
low. If all fourlthreefor7104-14 and -12) disable lines are tied
low, all the data output lines will be asserted full time, thus
giving a latched parallel output. For a three state parallel output, the three (two) byte disable lines should be tied low, and
the chip disable line will act as a normal three state control
line, as shown in Figure 4. This technique assumes the use of
an 18 (16, 14) bit wide bus, fairly common among minicomputers and larger computers, but still rare among microprocessors (note that "extra" bits can sometimes be sensed as
condition flags, etc.!. For small words, the bit groups can be
enabled individually or in pairs, by tying the chip disable line
low, and using the byte disable lines either individually or in
any combination as three state control lines, as shown in
Figure 5. Several devices can be three stated to one bus by
the technique suggested in Figure 6, comparable to row and
column selection in memory arrays.

71"",

Figure 4: Full 18 Bit Three State Output

CONVERT

....AI

....

7104

....A

......

""AI

7104

....
LB.

LSB

CONTROL

CONTROL

CONVERT

OR

POL

....AI

7104

USIA

....
LSI

CONTROL

Figure 5: Various Combinations of Byte Disables

..

.7

..

I.

..

83

12

.1

~_~W~Hn~"UMnn~

POL 0ItI

OR

OR
POL

POL OIR .1• •11 .'4 ., • •12 111 11' . .

~u

71 ....12

r-=.t,: or CHIP SELECT 2

L-+--+---'-_

'12 111 .1' ..

..

.7

..

II

Figure 3: Three State Formats via Disable Pins

63

..

1:1

12

.1

DATA ACQUISITION & CONVERSION HANDBOOK

CONVERTER

CONVERTER
IELECT

lOUCT

(

-fl

MODE ettD)

-

i

-

71IM

... =:J

MIl

8052A1
8068A

]
LI.

fl

MODE CII[D

POL
71IM

L. .

iiiIfri iiiiDi LBEN

~

80S2Af

71IM

8068A

-

-

.... P
L. .

0r---

HiIN iiiDi LSEN

HIIN MaEN La!N

L

J

RIft

0111--

]

-

--)

+j -

ORI--

POI.

8068A

-

Rlii

MODE CE/Lfii

OR-

8052A1

lOUCT

-

+j

-fl

fl/N

CON¥lRTER

j

TO OTHER CONVERTERS

1

BYTE SELECT

Figure 6: Three Stating Several 7104'. to a Small Bus.

Some practical interface circuits utilizing the parallel and
three state output capabilities of the ICL7104 are shown in
Figures 7 through 13. Figure 7 shows a straightforward
application to the Intel MCS-48, 80, and 85 systems via an
8255 PPI, using full-time parallel output. The 1/0 ports of an
8155 can be used in the same way. This interface can be used
in a read-anytime mode, although there can be timing
problems here, since a read performed as new data is being
latched in the ICL7104 may lead to scrambled data. (Note
that this will occur only very rarely, in proportion to the ratio

of setup-skew to conversion times). One way to overcome
this problem is to read back the STTS line as wall, and if it is
high, read the data again after a delay exceeding 1/2
(converter) clock cycle. If STTS is now low, the second
reading is correct, if it is still high, the first reading was
corract (note that data never changes when STTS is low, and
it goes low 1/2 clock cycle after data update occurs).
Alternatively, the problem is completely avoided by using a
read-alter-update mode, as shown in Figure 8. Here the high
to low transition of STTS triggers a "read data" operation
ADDRESS_US

:0

CONTROL.US

I

DATA BUS

I

Figure 7: Full Time Parallel/Interface
8052(8068)-7104 to MCS-48, 80/85

]

RiER iii6i iliEii
O/R,POL

Families
80521
8.68

..,-

71IM

IIODE

AI"

1- +.r

~
...J\.

"o-AI

U G II

co

,....

.........

PA1-PAo

~

U

D7-Do

AD WR

--'\.

~
Li. ~

STTS ClfLD

,,

D

U

j?

8015, I0I0,
104I, ....,IItc.

(ModI! 0)

P81-PaO
PC>;

!

.1
ADDRESS BUS

0

t

CONTAOLBUS
DATA 8US

Figure 8: Full Time Parallel Interface
8052(8068)-7104 to MCS-48, 80/85

I

I

HBEN

iiiiiii

J

U

-

LaEN

8002
8068

07-Do

~

PC 0,1

I

)

(MODEl)

Lia I

)

(MODE 0)

Families With Interrupt
71IM

M!.

STTS CElLO

....Ucs ,

U

AD WR

A
O/A,POL

.....

....,no.,

PA7-PAo

u n
1015.I0I0,
1041........Ie.

PI7-PBo
MODE

-l-

R/H

I

1-1

Pc.

..

'.{
SEE TEXT

64

1".',..

PCt

"""

IINTRA

+·1

INTR

I

11

through the MCS-8 Interrupt system. This application also
shows the R/R" pin being used to initiate conversions under
software control. If continuous conversions are desired, R/R"
may be held high, and if the maximum possible conversion
rate is desired, R/R" may be tied to clock out (see Section 4.B
belowl.

Figure 10 shows an interface to the Intersil IMS100 microprocessor family through the IMS101 PIE device. Here the
data is read back in a 10-bit and an 8-bit word, directly from
the 7104 onto the 12-bit data bus. Again, the high to low
transition of the STTS line triggers an interrupt. This leads to
a software routine which controls the two read operations.
As before, the R/R" pin is shown as being under software
control, though the options mentioned above are equally
acceptable, depending on system needs.
These Interrupt-fed systems essentially use an external
handshake operation, under software control. An interesting
variation, using the Simultaneous Direct Memory Access
(SOMAl capability of the IMS100 family, is shown in Figure
11. The IMS102 MEDIC allows DMA during bus-idle
processor cycles, so the transfer takes no extra time. The
current address and extended current address registers of
the IMS102 control the memory location to which the data
will be sent, and the STTS output of the ICL7104 allows data
transfer only when the converter is not updating information.
The ECA register is used to drive the byte select lines (CA
should be set to 7777, and WC to 21 and the User Pulse
controls Chip disable CE/Li5. A more fully loaded system
can use address latches for CA. A DMA system can also be
set up on the MCS-8 system using the DMA controller, 8257,
and the three state outputs of the ICL7104.

A similar interface to the Motorola MC6800 system is shown
in Figure g. Since the maximum input-port count here is only
1S, while the 1S-bit ICL7104 has 18 outputs, control register
A is used to inputthe two extra bits. The high to low transition
of the STTS pin enables the two high bits, clocking the two
interrupt flags in Control Register A if they are negative. A
pull up resistor is needed on CAl, though CA2 has one
internally. The same transition causes an interrupt via
Control Register B's CBl line. It is important to ensure that
the software interrupt routine reads control register A before
reading data port A, since the latter operation will clear the
interrupt flags. Note that CB2 controls the R/R" pin through
control register B, allowing software initiation of
conversions· in this system also. Naturally, the 14 and 12 bit
versions of the ICL7104 avoid this problem since lS or fewer
bits need to be read back. Since the MOS Technology
MCSS50X microprocessors are bus-compatible with the
MCS800's the same circuit can be used with them also.

Figure 9: Paraliel Interface from 7104 to MC 6800 Family (also MCS650X Familyl
12 BIT DATA

aus

Figure 10: 8052180681/7104 Paraliel Interface With 6100"P

65

DATA ACQUISITION & CONVERSION HANDBOOK

12 BIT DATA BUS

·5.

UP
OR

8052A1

80'"

71~

LSB

6102

6100

MEDIC

"p

EM"

13 BIT CONTROL BUS

Figure 11: 8052180681/7104 Parallel Interface With 6100"P Using DMA

It is possible using the three state output capability, to
connect the ICL7104 directly onto many microprocessor
busses. Examples of this are shown in Figures 12and 13. It is
necessary to consider the system timing in this kind of
application, and careful study should be made of the
required set-up times from the microprocessor data sheets.

Note also the drive limitations on long busses. Generally this
type of circuit is only favored if the memory peripheral
address density is low, so that simple redundant address
decoding can be used. Interrupt handling can require multiple
external components also, and use of an interface device is
normally advisable if this is needed.

BUS CONTROL

ADDRESS BUS

DATA BUS

Figure 12: Direct 805218068117104 to MC6800 Microprocessor Interface
ADDRESS BUS

A13-A,5

(')0

t

CONTROL 8U8
RD

<-

DATA 8US

U

HHIi
MIEN

O/A,POL

Ui!N

....

80521

Mfl

7104

MODE

AIM

J: .t

CilUi

1

LiB

J
::J
::J

-

r-

U H II

,....

lOIS, I0I0,

Figure 13: Direct Connection of 8052180681/7104 to MCS-80/85 System

66

3. HANDSHAKE MODE INTERFACE

low. When receipt of the last byte has been acknowledged by
a high SEN, the handshake mode will be cleared, re-enabling
data latching from conversions, and recognizing the
condition of the MODE pin again. The byte and chip disables
will be three stated off, if the MODE pin is low, but held high
by their (weak) pullups. These timing relationships are
illustrated in Figure 14.
This configuration allows ready interface with a wide variety
of external devices. For instance, external latches can be
clocked on the rising edge of CE/i]), and the byte disables
can be used to drive either load enables, or provide data
identification flags, as shown in Figure 15. More usefully, the
handshake mode can be used to interface with an 8-bit
microprocessor of the MCS-8 group (eg. 8048, 8080, 8085,
etc.) as shown in Figure 16. The handshake operation with
the 8255 Programmable Peripheral Interface (PPII is
controlled by inverting its Input Buffer Full IIBF) flag to drive
the Send ENable pin, and driving its strobe with' the (;Eli])
line. The internal control register of the PPI should be set in
mode 1 for the port used. If the 7104 is in handshake mode,
and the 8255 IBF fla9 is low, the next word will be presented
to the chosen port, and strobed. The strobe will cause IBFto
rise, locking the three stated byte on. The PPI will cause a
program interrupt in the MCS-8 system, which will result
(after the appropriate program steps have been executed) in
a "read" operation. The byte will be read, and the IBF reset
low. This will cause the current byte disable to be dropped,
and the next (if any) selected, strobed, etc., as before. The
interface circuit as shown has the MODE pin tied to a control
line on the PPI. If this bit is set always high (or mode is tied
high separately), every conversion will be fed into the system
(provided that the three interrupt sequences take less time
than one conversion) as three 8-bit bytes; if this bit is
normally left low, setting it high will cnse a data
transmission on demand. The interrupt routine clln be used

Entry into the handshake mode will occur if either of two
conditions are fulfilled; first. if new data is latched Ii.e. a
conversion is completed) while MODE pin (27) is high, in
which case entry occurs at the end of the latch cycle; or
secondly, if the MODE pin goes from low to high, when entry
will occur immediately Iif new data is being latched, entry is
delayed to the end of the latch cycle!. While in the handshake
mode, data latching is inhibited, and the MODE pin is
ignored. (Note that conversion cycles will continue in the
normal manner). This allows versatile initiation of handshake
operation without danger of false data generation; if the
MODE pin is held high, every conversion (other than those
completed during handshake operations) will start a new
handshake operation, while if the MODE pin is pulsed high,
handshake operations can be obtained "on demand."
During handshake operations, the various "disable" pins
become output pins, generating Signals used for the
handshake operation. The Send ENable pin (SEN) (pin 29) is
used as an indication of the ability 'of the external device to
receive data. The condition of the line is sensed once every
clock pulse, and if it is high, the next (or first) byte is enabled
on the next riSing CL 1 (pin 25) clock edge, the corresponding
byte disable line goes low, and the Chip DisablE/LoaD line
(pin 301 «;Eli])) goes low for one full clock pulse only,
returning high.
On the next falling CL 1 clock pulse edge, if SEN remains
high, or after it goes high again, the byte output lines will be
put in the high impedance state (or three-stated off). One half
pulse later, the byte disable pin will be cleared high, and
(unless finished) the CEli]) and the next byte disable pin will
go low. This will continue until all three (2 in the case of 12
and 14 bit devices) bytes have been sent. The bytes are
individually put into the low impedance state i.e.: threestated on during most of thetimethattheir byte disable pin is

.. - 7104-16 REPEAT SEQUENCE FOR MBEN

-I

Cll(PIN25}
EITHER:MODE PIN

OR:-

INTERNAL LATCH
PULSE IF MODE "HI".
UAAT
INTERNAL MODE

\'----

NORM _ _-L_ _",--_....J

SEN

(EXTERNAL SIGNAL)

DIA,POL.BI-1"
17104-12: 89-12)

.~«==~D.~T~.~V~.L~ID~.~ST~.~.L~E:: ~>---------

BITS 1-8

I -_ _ _
HANDSHAKE MODE TRIGGERED By········· OR - - -

THREE STATE H I Z _

-14, -12 BIT VERSION SHOWN

Figurs 14: Timing Relationships in Handshake Mode

67

.....L... THREE STATE W PULLUP.

-18 HAS EXTRA (1I8EN) PHASE

DATA ACQUISITION 8. CONVERSION HANDBOOK

to reset the bit, if desired. Note also that the R/R' pin is also
shown tied to a control bit so that conversions can be
performed· either continuously or on demand under software
control. Note that one port is not used here, and can service
another peripheral device. The same arrangement can again
be used with an 8155 I/O port and control lines.

17, and the Intel MCS4/40 family, as shown in Figure 18.
These both operate almost identically to the method
described above, except that in the former both R/R and
MODE are shown tied high, to avoid using a full port for only
two lines. Any 8-bit or wider microprocessor lor minicomputer), or narrower devices with 8-bit wide ports (most 4bit devices have 8-bit wide ports available) can be interfaced
in a handshake mode with a minimum 01 additional
hardware, frequently none at all.

Similar methods can be used with other microprocessors,
such as the MC6800 or MCS650X family, as shown in Figure
1+'
2

I

I

I

MODE

S.N

Aitt
OA2
POL
MS.

8052A1

7104

8068'

~
a

~
icl/[i5

HiIJii MiEN

LS·l
L81!N
L-

a

I

r:=:::>

74C'.,

I
•
[
•
[
•
[
•
r

----l
)I

L-..

74C181

)\

[

L-..

----l

I--

14C161

~

..)

'---

-------'

r:

74C181

)

L-..

,----J

~ LO~C1~LK

I=

..)

'---

f---J

a

PARALLEL

TO

I

SERIAL
CONVERTER

"LOAD

-

SERIAL
DATA

W'TH
BYTE
FLAGS

Figure 15: Use of Byte Disable Lines as Flags or for Loading
ADDRESS IUS

r

c

CONTROL BUS
DATA BUS

O/A,POL

to.2'

M~B

7104

8.68

MODE

R/R

SEN

Cilili

I

1

1

LSB

~
~
...
A

U

{}

U

lAD iii!

Ao-At

01-00

U G II

co

,....

Intltl

PC.

101S.IOIO.
IIMI. I00I, etc.

82&&

PA7'PAo

(Mochl1)

PC,

PC,

PC.

PC,

INTA

!

!INTRA.

liTO'I'·"1

Figure 16: 8052A18068AI-7104 to MCS-48. -80. or -85 Handshake Interface

fE/a; S'N

O'A

CA1

POL

CA2
CRA

I

n

100-01

I

MS.
Po4O·1
10521

8.68

MC ....
OA

MC6820

7104
P80·7

MCSI50J(

C81

C.2
ADDRESS BUS

BUS CONTROL

Figure 17: 805218068117104 to MC6800 or MCS650X Microprocessor With Handshake

68

CONTfiOlBUS

u {)

ADDfiESS I DATA BUS

u {)

80521
1068

7'04

OIR'::.:§
~

p~~~'" ':

L-...L::M~OD~E"';A;;;'[;"_"';S"'~1;"~;;;;\;';;~'--_-~-'·__ ~;}j
k

INTEL
4004 OR

4040

(MODE 1 OA 2)

"

ONLY:
ELSE_
'5V)
_ _ _ _ _(MODE
_ _2_
__
_____ _

Figure 18: 8052A-7104 to MCS4/40 Microprocessor With Handshake
The handshake mode can also be used to interface with
industry-standard UARTs, such as the Intersil IM6402/3 and
the Western Digital TR1602. One method is shown in Figure
19. The arrangement here is such that il the UART receives
any word serially down the Receiver Register Input line (RRD
the Data Received flag (DR) will be set. Since this is tied to the
MODE pin, the current result will be loaded, lull handshake
style as belore, into the transmitter buffer register, via the
Transmitter Buller Register Empty flag (TBRE) and the
TBR]"oad lines. The UART will thus transmit the lull 18 (16,
14) bit result in 3 (2, 2) 8-bit words, together with the requisite
start, stop and parity bits, serially down the Transmitter
Register Output (TRO) line. The DR Ilag is reset via DRReset,
here driven by a byte disable line. II we use DR to drive R/R'
instead, and use the received data word to drive a
multiplexer, as shown in Figure 20, the multiplexer address
sent to the UART will be selected, and a conversion initiated
01 the corresponding analog input. The result will be
returned serially il the MODE pin is tied high. Thus a
complete remote data logging station lor up to 256 separate
input lines can be controlled and read back through a three
line interface. By adding a duplex or modem, telephone or
radio link control is possible. (For a luller discussion 01 this
technique, see Application Note A025, Building A Remote
Data Logging Station).

o

'5.
SEN
CElLO
lBEN

8052A1
oo68A

alA

7104

TBA 1
RA1 _ _ _ SERIAL liP

LS.
OA

MODE

Figure 19: 805218068117104 Serial Inferface Using UART
unselected A/Os all have three stated disable lines as well as
data lines, so provided only one device is selected at a time,
no conllicts will occur. (Note that byte disable lines are
internally pulled-up when not active, so CE/[5 has no effect
on unselected converters). Naturally, care must be taken to
avoid double selection errors in the data word, or an address
decoder used. This technique could also be used to poll
many stations on a single set 01 lines, provided that the TRO
outputs are either three state or open collector/drain
connections, since only that UART receiving an address that
will trigger an attached converter will transmit anything.

o

-5V

ANALOG
INPUTS

MULTIPLEXER

6403
UART

POL

MODE

IH ....

SERIAL DIP

TBAl

1-----1 O.A

MS.

Alternatively, the data word could be used to select one 01
several A/D converters, as shown in Figure 21. The

8052AI
oo68A

TAO

TBRE

TAO

O/A

SEAIAL O/P

6403
UART

7'04
POL

AB.A1

MS.

ABR4

AN lIP
AR1

• SEAIAL liP

LS.
OA

Figure 20: 805218068117104 Serial Interface Using UART and Analog Multiplexer

69

DATA ACQUISITION & CONVERSION HANDBOOK

SERIAL DIP

SERIAL liP

j

1

TOO

001

DO

8403

C

UART
TIRE HRl

RBRl ••• RIM TaRl ••• TaAI

DO.

~

II

~

I

(

t-'''\
MODE CEli:D

SEN

SE.

ORr
POL
MS.

8052A1
8068A

710.

RIH

~

MS.

8052AI
8068A

7104

-

LS.

I

SEN

P

0

I

I

I

RIH
00

POL
MS.

8052AI
SO..A

710.

I--

HfiN iiiHN LaEN

HIEN MBEN LBEN

I

MODE CIlLO

ORr
POL

J
LS.

r-·' "\

1-' "\
MODE i'!!ILD

R'"

I

LS.

i--'

P

0

I--

HBiN MIEN LIEN

I

I

I

Figure 21: Multiplexing Converters Through the Mode Pin

4. MISCELLANEOUS TECHNIQUES FOR

is shown in Figure 22. With careful layout, the circuit shown
can achieve effective input noise voltages on the order of 12".V, allowing full 16-bit use with full scale inputs of as low as
150mV. Note thatatthis level, thermoelectric EMFs between
PC boards, IC pins, etc., due to local temperature changes
can be very troublesome. ConSiderable care has been taken
with the internal design of the ICL7104 and the ICL8068
to minimize the internal thermoelectric effects, but device
dissipation should be minimized, and the effects of heatfrom
adjacent land not-so adjacent) components must be
considered to achieve full performance at this sensitivity
level.

PERFORMANCE ENHANCEMENT

This section covers a few techniques. primarily analog, that
can be used to enhance the performance of the ICL8052
IICL8068)/ICL7104 chip pair for certain applications. Section
4.A. deals with buffer gain. for sensitivity increases of up to
about 5 or 10 to 1, Section 4.B. with a special interconnection to allow the maximum rate of conversion with
lower-valued inputs, and Section 4.C. external auto-zero for
extending the benefits of auto-zero operation to preamplifiers, etc., to cover specialized signal processing or
sensitivity enhancement by 10-100 to 1.

4. A. Buffer Gain

4. B. Minimal Auto-Zero Time Operation

One of the significant contributions to the effective input
noise voltage of a dual slope integrator is the so called autozero noise. At the end of the auto-zero interval, the instantaneous noise voltage on the auto-zero capacitor is stored,
and subtracts from the input voltage while adding to the
reference voltage during the next cycle. Although the open
loop band width of the auto-zero loop is not wide, the gain
from the input is very high, and the resulting closed loop
band width to buffer noise is fairly wide. The result is thalthis
noise voltage effectively is somewhat greater than the input
noise voltage of the buffer . itself during integration. By
introducing some voltage gain into the buffer, the effect of
the auto-zero noise (referred to the input> can be reduced to
the level of the inherent buffer noise. This generally occurs
with a buffer gain of between 3 and 10. Further increase in
buffer gain merely increases the total offset to be handled by
the auto-zero loop, and reduces the available buffer and
integrator swings, without improving the noise performance
of the system (see also the appendix). The circuit
recommended for doing this with the ICL806811CL7104

The R/H pin (pin 28) can be used in two basic modes. If it is
held high, the ICL7104-16 will perform a complete
conversion cycle in 131K clock counts (strictly 217),
regardless of the result value Ifor the -14, 215 counts, -12, 2'3
counts!.
If, however, the R/H pin lever) goes low between the time of
the zero-crossing and the end of a full 216/14/12 count
reference integrate phase, that phase is immediately
terminated. If it is then held low, the 7104 will ensure a
minimum auto-zero count (of 2 15/13/11 counts) and then wait
in auto-zero until the R/R pin goes high. On the other hand, if
it goes high immediately subsequent to this minimal autozero count, the 7104 will start the'next conversion after the
least permissible time in auto-zero; i.e., at the maximum
possible rate. The necessary "activity" oflthe R/R pin can be
readily provided by tying it to the clock out pin (pin 26).
Obviously under these conditions, the conversion cycle time
depends on the result. Also note the scale factor and autozero effects covered in the Appendix.

70

·15V

15V

roJ
168

7

1

VRF.~

ANALOG
INPUT

Figure 22: 806817104 Converter With Buffer Gain

4. C. External Auto-Zero

5. SUMMARY

In many systems, signal conditioning is required in front of
the converter for preamplification, filtering, etc., etc. With the
exception of buffer gain, discussed in Section 4.A. above, it is
generally not possible to include these conditioning circuits
in the auto-zero loop. However, a sample-and-difference
circuit keyed to the auto-zero phase can be used to eliminate
offset and similar errors in preamplifiers, multiplexers, etc. A
suitable circuit for a simple system is shown in Figure 23. The
ICL8053 is used as a switch here primarily because of its
extremely low charge injection (typically well below 10pC),
even though it does limittheanalog swing to±4V. The use of
an IH191 or IH5043 avoids this restriction, but increases the
charge injection. The circuit of Figure 24 includes some
balancing, but still injects typically 60pC lor 150pC for a
DG191). Note that all these circuits have some sensitivity to
stray capacitance at the converter input node. The
amplifying or conditioning stages indicated in both these
circuits must be capable of passing the chopping frequency
with small enough delay, rise time, and overshoot to lead to
insignificant error. Filtering should be done before or after
the switching devices. Note also that although the input
signal is still integrated over the normal time period, the input
reference level is not. The time constant of the hold capacitor
charging circuit should take noise and interference effects
into consideration.

The list of applications presented here is not intended to be,
nor can it be, exhaustive, but is intended to suggest the wide
range of possible applications of the ICL805211CL806811
ICL7104 chip pair in AID conversion in a digital environment.
Many of the ideas suggested here may be used in combination; in particular, all the digital concepts discussed in
Sections 2 and 3 can be used with any of the analog
techniques outlined in Section 4, and many of the uses of the
R/R and MODE pins can be mixed.

PB

For a multiplexed input system, an arrangement similar to
that of Figure 25 may be needed with individual preconditioning amplifiers, and Figure 26 with a common preconditioning amplifer. Note that in both of these cases, the
capacitor may be charged to different voltages on each
channel. By putting a capacitor in each line of Figure 25, the
capacitor charging transients are eliminated, but the multiplexer capacitance becomes an important source of stray
capacitance.

71

DATA ACQUISITION & CONVERSION HANDBOOK

ANAL.OG
INPUT

I

I

ANA~~~ MII"-'---......I--+...........J

rc~o-;-­

I
I
I
I

I
I

PREAIIP ITC.

SIGNAL IN

Flgu.. 23: External Auto-Zero System Using 8053 Switches

72

"15V

·15V

rbJ
IS

L

8

7

O/RPOL 1615 l' 13 12 11 10 9

8 7 6 5 4 3 2 1

--l

1

f-~~~~~~~~~~~~'" :

32

Figure 24: External Auto-Zero System for Large Signals Using IH5043 or Equivalent

PREAMPS

AN

AN

IN

IN

80521

BOSS

....

80521

7104
SlIP

7104

r---I
AN
I

GND

I

I
I

,,
I

I

L____ ___C~~T~~

STTS

STTS

:

_____ ,-'_ _ _ _ _ _ _ _- '

figure 25: Multiplexed Auto-Zero System With Individual Preamps

Figure 28: Multiplexed Auto-Zero System With Common Preamp

73

96

~

DATA ACQUISITION 8. CONVERSION HANDBOOK

APPENDIX A!

The Auto-zero Loop Residual; A Relatively
Complete Discussion for those with Strong
Heads
The relevant circuit to be discussed is shown in Figure Aland
the major cycle waveforms in Figure A2. Let us first assume that
the prior auto-zero cycle has been indefinitely long, or is
otherwise ideal, so that the conversion starts with no residual
error on tha auto-zero capacitor. The integrate and deintegrate
cycles will be classically perfect to the point at which a zero
crossing actually occurs (at the output of the integrator).
However, from this pOint two delays occur; first the
comparator output is delayed (due to comparator delay) and
secondly the zero crossing is not registered until the next
appropriate clock edge. (For further discussion of this, see
Application Note A017l. At this point, the circuit is returned
to the auto-zero connection (logic and switch delays may be
absorbed in comparator delay as far as our discussion is
concernedl. The net result is that the integrator output
voltage will have passed the zero-crossing point by an
amount given by
Vires

~ :±:VIFS (COc;Scx)

where O,;S cx,;S 1

The range of this residual voltage corresponds to the
integrator swing per count, and in independent of input
value, except for polarity. The immediate effect of closing the
auto-zero loop may be seen by examining Figure A3. We may
consider the comparator as acting as an op-amp underthese
conditions: the voltage across the auto-zero impedance is
high, and the (nonlinear) impedance is low; on the other
hand, the initial voltage across the integrating resistor is
zero. Thus the auto-zero capacitor will be charged rapidly to
exactly cancel the residual voltage, as shown in Figure A4.
The output of the integrator is now at the correct position,
but the two inputs are not. The residual voltage will decay
away with a time constant controlled by the integrating
resistor and capacitor, while the auto-zero capacitor is easily
kept in step owing to the high comparator gain. Thus at the
end of the auto-zero time, tAl ~ CAl !cp, the residual will be
reduced to:
VAlres

(All

is the variable delay, where co is the fixed delay, CFS is the full
scale count in units of clock pulse periods, and VIFS is the full
scale integrator swing in volts.

~ Vires

~ VIFS

exp(

R~AZC!cP
)
INT INT

(CX + CD)

c!s

exp

(~~C~~Tj

(A21

Q

ZERO

CROIIING
FF

CL

ow.

CL

POL.

Figure Al: The Analog System

"TRUE" ZERO CROSSING

"Z.RO·· ---~'l--1--t=_-.,,_------_

,

::~

COMPO/P

FIgure A2: Major Cycle Waveforms

..:---"'---------

----Z.;.:-to""7~~~=

'Of""

I
I
I i-1....\
CL _ _ _ _ _ _~~I ,

t---+

0-

ZOFF

I

AlZ _ _

c"

DETECTED ZERO CROSSING

I

~i~t

c---

:0----

------\i"'--"1"'V

ALL ANALOG VOLTAGES ARE WITH RESPECT TO THEIR "AUTO-ZEROED" VALUE

FIgure A4: Waveforms at Beginning of Auto-Zero Interval

Fl,ure A3: Analog System During Auto-Zero

74

Those expert at skipping to the end of the difficult bit will
recognize that as the final equation. in terms of complexity.
So let us now see what it means. Clearly. the error term is
CDE
CAl
greater. the larger CINT • and the smaller CINT For the

Now RINTCINT is controlled by the buffer swing. VBFS. the
integrator swing. VIFS. and the integration time tiNT = CINT !cp.
so that
VBFS/RINT' tiNT = CINT VIFS. or RINT CINT = CINT VBFS tcp
VIFS
CAlVIFS)
and VAl'e. = Vl,e, ( exp - --V-CINT BFS

ICL7104 combinations. land also the ICL7103. and the data
sheet systems for the ICL8053 pairs). these are both worst
CDE
CAZ
.
case near full scale Input. where CiNr ~2 and CINT ~1. INote

(A3)

This residual voltage on the auto-zero capacitor effectively
increases the magnitude of the input voltage as seen on the
output of the buffer. Thus. converting this voltage to countequivalents.
VAl,.,
VIFS (
)
(CAl VIFS )
CAl,., = VBFS • CFS = VBFS cx + CD exp - CINT • VBFS

that the minimum auto-zero time technique of section 4B will
make CAZ =1 for all input values). Substituting these. wefind
CINT
the worst case
CIN,.,

(A4)

Since this voltage also subtracts from the reference. its effect
at the input is magnified in the ratio
CINres

::::

CIN,e. = (1

+ coe )
CINT

CAZres (CINT

so that

+ CDE )( VVIFS ) (cx + CD ) exp (_ CAZ • VVIFS)

CINT
BFS
\ CINT BFS
Note that CDE is equal to the displayed result.
(A5)
Two things should be noted here. First. this residual acts to
increase the input voltage magnitude. and secondly. a small
increase in input voltage tends to decrease the magnitude of
the residual luntil the result count changesl. These effects
lead to "sticky ness" in the readings; suppose. in a noise-free
system. that the input voltage is at a level where the residual
is a minimum; the detected zero crossing follows the true one
as closely as possible. A minute increase in input voltage will
cause the zero crossing to be detected one pulse later. and
the residual to jump to it's maximum value. The effect of this
is a small increase in the apparent input voltage; thus if we
now remove the minute increase. the residual voltage effect
will maintain the new higher reading; in fact we will have to
reduce the input voltage by an amount commensurate with
the effective residual voltage to force the reading to drop
back again to the lower value. In more detail. we should
consider the equilibrium conditions on the auto-zero
capacitor. Clearly. the voltage added at the end of reference
integrate must just balance that which decays away during
the auto-zero interval. So far the relationships we have
developed have assumed a zero residual before the
conversion. but clearly in the equilibrium condition the
residual given by equation IA4) remains. and at the end of
conversion. the new amount. given by equation IA 1). is
added to this. so we start the "auto-zero decay" interval with
VIFS (cx + CD )
CI,e. = CAl,e. + VBFS
(AB)

[exp (

::;~) -1J -1

(A8)

C,

.........

~

2.5

~

"'"

2.0

I

1.5

""\

\

.-

\
f- 1\

1.0

0.5

o

0.1

0.25

0.5

-

\

"--..

1.0

Figure A5: Auto-Zero Loop Residual v•.
Integrator/Buffer Swing Aado

The effects of noise should be mentioned here. The worst
case value of residual shown in Figure A5 assumes a very
gradual approach to equilibrium. and any noise spike
causing the reading to flash to the next value will destroy all
this carefully established residual value! Thus for any system
with noise of - 1/3 count or more. the effect is greatly
reduced. and even 1/10 count of noise will restrict the actual
hysteresis value found in practice. The detailed analysis of
the auto-zero residual problem in the presence of
appreciable noise is left as an exercise for the masochist.

+ CD ) [ exp {CAlVIFS}
+ CINTVBFS -1]-1

Once again. the effect of this at the input is multiplied by the
ratio of total input integrate times. so that. under equilibrium
conditions.
CINres ::::

+ CD)

(3)(CX

! c...."
3.0

By combining equations IA4) and IA6) we find. for the
equilibrium condition.
VIFS (
CAl,., = ± VBFS Cx

~ ± ::;~

Recall the CD is fixed; and ex must be between 0 and 1. The
expression is now a function purely of the ratio of integrator
and buffer full scale swings; the relationship is plotted in
Figure A5. and shows the desirability of keeping the
integrator swing higher than the buffer swing. Note also that
the comparator delay ICD in equation IA811 is also effectively
enhanced. This has the effect of shrinking the zero
somewhat more than normally occurs. Since this term
changes sign with polarity. the converter will have a
tendency to keep the current sign at zero input.

VIFS
±- ( 1 + CDE ) (CX + cDlex p { CAl VIFS} _11-1
VBFS
CINT
~
CINTVBFS

J

(A7)

PB

75

DATA ACQUISITION III CONVERSION HANDBOOK

POWER O/A CONVERTERS USING THE IH8510

THE POWER D/A CONVERTER

DESIGN DETAILS

Intersil has introduced a family of power amplifiers - the IH
8510 family. These power amplifiers have been speCifically
designed to drive D.C. servo motors, D.C. linear and rotary
actuators, electronic orifice valves and X·Y printer motors.
There are three versions presently offered - the IH851 0 is
specified at 1 amp continuous output with up to ±35V power
supplies; the IH8520 is specified at 2 amps continuous out·
put at up to ±35V; finally the IH8530 is a 3 amp version
with the same power supply range.

A typical power DAC designed for 8 bit accuracy and 10 bit
resolution is shown in Figure 1. The IH8510 power amplifier
described in the introduction is driven by the Intersil 7520
monolithic D/A converter.
The 7520 contains the R/2R ladder network and the feed·
back resistor for proper scaling of the reference input volt·
age (±10V) and also the SPDT switches (CMOS) for each
bit. Figure 2 shows a part of the system (first 4 bits). Note
that a permanently biased "on" switch is in series with the
10Kn feedback resistor. The RDS(on) of this "on" FET is
0.5 x RDS(onl of the Most Significant Bit (MSB) switch to
maintain MSB accuracy (gain accuracy) at 25°C and over the
temperature range. Since the F ET switches are on the same
I.C. chip, the temperature tracking is excellent. Actually,
the 7520 specifies the temperature coefficient at 2ppm/"C
maximum.

The amplifiers are linear mode types and are basically a
po'wer version of the popular 741 differential op amp. The
parts are available in 8'pin TO·3 packages. Using ±30V power
supplies, the amplifiers are capable of delivering up to ±26V
swings into a 10n load. The parts are biased Class AB, and
have typical no·load quiescent current of 20mA. Frequency
response, input offset voltage, input offset, and bias currents
are the same as the 741 op amp. All three models can with·
stand indefinite shorts to ground on the output. When driv·
ing a D.C. motor, the amplifiers can also withstand the
surges caused by motor lock·up and motor reversal (i.e.,
while running in one direction, the voltage is suddenly
reversed) .

The circuit configuration is such that the SPDT switches in
series with each 20Kn resistor never see more than ±25mV;
this minimizes DAC errors caused by ID(off) and ID(on) leak·
ages. It also allows the DAC switch to handle ±1OV references
with only a single +15V power supply. The size of each DAC
switch is scaled so that it does not distort the gain for each
bit, i.e., the MSB switch RDS(on) is 25n; the next switch
RDS(on) is 50n; the next is lOOn, etc.

The linear nature of these power amplifiers allows them to
fit in very well with another Intersil product family - the
D/A converter. Intersil has two low cost DAC's available the 7520 series, and the 7105. When a DAC and a power
amplifier are combined, one has a very useful building block
for control functions, i.e., a digitally programmable power
driver. This power DAC can interface directly with micro·
processors, UARTS, computers, etc.

A summing amplifier is shown between the 7520 and the
IH8510 in Figure 1. This apparently redundant amplifier is
used to separate the gain block containing the 7520 on·chip
resistors from the power amplifier gain stage whose gain is
set only by external resistors. This approach minimizes drift
since the resistor pairs will track properly.

16

15

BIT-

SWITCHES

{

VREF j'lOVI

3OK::

+15V

4 INTERSll 13
7520
5

,."
11

L~}

BIT

O.68!l
'OK~;

SWITCHES
lOOp'

9

.,

D.SS!!

1.51(::

10K:;

Figure 1:
The Basic Power DAC

76

-------------------,

10K!!

)

1520

"II

I
20K~~

20K!!

20K!!

I

20K!!

I

I
I

I:v .,

I

L------+------~------~----~------_T--h
IL~
__________ _
LSB

10K!!

+15VT

I

_-1

OUTPUT
TOPQWER

.,

AMP

Figure 2:
D/A Converter Details
26mV, and the voltage drift (worst case) is 2.5mV. The
latter number is an estimate since the 741 data sheet does
not guarantee drift. It can be seen from these numbers that
the 741 is margi~al fdr this application. However a more

One of the decisions the user will have to make is the choice
of summing amplifier. For 8 bit accuracy with 25 volt out·
put swings, a " LSB is equivalent to approximately 50mV.
The worst case errors introduced by the op·amp (i.e., the
cummulative effects of IB, and lOS, and ~VOS/~T) should
therefore be significantly less th.an 50mV.

detailed analysis, taking into account a non-zero value for

R 1 (say 10K!?), would show the 741 in a better light.

In Figure 1 a lOlA isshown. This amplifier meets the require·
ments outlined abo~e. Over the military temperature range.
the input bias current (average of the two input currents) is
specified at 100nA maximum. The input offset current is
given as 20nA maximum. Thus, in the worst case, one input
bias current could be 11 DnA, the other one 90nA. Again,
making the pessimistic simplification that R 1 = zero, that
all the DAC switches are off, and that the higher of the two
bias currents flows through the feedback resistor, the error
due to input current equals 110 x Rf x 1D- 6 mV. Figure 3
shows this situation. The maximum value of Rf is not given
in the 7520 data sheet, but in practice is around 15K!?. The
input current error (absolute worst case) therefore calculates
out at 1.65mV. To this, one must add the effect of offset
voltage drift. This amounts to a worst case of 1.5mV over
the temperature range. The summation of these two errors
is still an order of magnitude less than "LSB in 8 bits, a com·
fortable safety margin. In fact, the lOlA would be adequate
for a 10 bit power DAC.

The initial offset voltage of the buffer amplifier adds to that
of the IH8510, and is multiplied by three before appearing
at the output. Depending on the application, it may be de·
sirable to null out this offset. The nulling should be done at
the buffer in the manner recommended for the amplifier be·
ing used.
In the majority of DAC applications, a full scale output ad·
justment is necessary. For example, set point controllers in
servo systems are typically required to have an error no great·
er than 0.3% of full scale reading. This can be achieved by
either adjusting the reference voltage up or down from a
nominal 10.DDOV, or by using a potentiometer in the ampli·
fier feedback network, as shown in Figure 4. The potentiometer should be a low temperature coefficient type.
A final important note on the 7520/101 A interface concerns
the connection between Pin 1 of the DAC and Pin 2 of the
op amp. Remember this point is the summing junction of
an amplifier with an AC gain of 50,ODD or better, so stray
capacitance should be minimized otherwise instabilities and

Performing the same calculations on a 741 over the military
temperature range, the input current (worst case) error is

--

Rf= ISKH MAX

.L.

IlOW T.C. POTENTIOMETERI

.,

ASSUMED

ZEAO

Figure 4:
Full Scale. Gain Adjustment

Figure 3:
Worst Case Error Due to Input Current

77

DATA ACQUISITION & CONVERSION HANDBOOK

The IH8510 family design is shown in Figure 7. It consists
of a 741 op amp driving a custom chip (called the IH8063),
The 8063 is a 60V circuit which boosts the ooltago and cur·
rent outputs of the 741 to drive internal power transistors.
It also contains plus and minus regulators \0 lower the ±30V
input voltages to ±15V for safe 741 operation.

Figure 5:
Non·inverting Gain Connection

poor noise performance will result. Notice also that an in·
verting gain stage follows the lOlA output; this is to boost
the power DAC output to ±30V; thus a gain of -3 is used.
If a non·inverting gain of +3 is desired, then the configuration
of Figure 5 should be used.
6

~----_-o VOUT

The 0.68\1 resistors from Pins 5 and 7 to Pin 6 are used to
set current limits for the power amp. These are safe area limiting structures which follow a definite VOUT/IOUT profile
This is shown in Figure 6.

::r~~-""""""''''5

R-SC

lOUT lAMPS!

t
r"
+"

Vee

Figure 7:
IH8510 Schematic

COST OF THE POWER OAC SYSTEM

..-..-- VOUT 1- REl

VOUT !TREI

The complete, operational system is shown in Figure 4. At
the time of writing, the 7520 sells for $10 in small quantities,
and the 301A is in the 50¢ area. The IH8510 sells for $15
each in small quantities, so the system cost is as follows:

--+

Figur.6:
Output Current Limiting

$10.00
2.00
.50
.20
1.10

7520 DAC (Intersi!)
5Kn 50ppm pot (full scale trim)
301 A op amp (lntersi!)
100pF capacitors
Miscellaneous resistors
0.68n 5 watt resistors
IH8510 power amplifier (lntersil)

Notice that maximum output current is obtained when
VOUT = +25V.30V, for either polarity of VOUT; current
falls off as VOUT decreases to limit the internal power dissipation. When driving 24V to 28V DC motors or actuators,
the power amp delivers full power. Since lOUT is a max·
imum for this range, the internal power limiting does not
affect normal performance. For example, consider driving a
24V DC motor at 1.5 amps delivered current. The internal
power dissipation is (30V - 24V) x 1.5 amps = 9 watts.

.50
15.00
$29.30

To obtain a D.C. referenoe for the DAC, one can buy a 10V
reference or use a circuit such as that shown in Figure 8.

Now the load is also taking 1.5 amps x 24 V = 36 watts. The
amplifier efficiency = ~ = 80%. Now, if the output
is mistakenly shorted to wg'}05nd (through motor failure)
then IOUT(max) goes to 0.5 amps and the power dissipation
equals 30V x 0.5 amps = 15 watts. As long as the amplifier
is heat-sin ked to dissipate t~is 15 watts, no damage will r,esult
and proper performance will return when the fault is corrected. A significant advantage of the IH8510 family is that the
case is electrically isolated and is not tied to any pin. This
means that multiple IH8510's can be mounted on the same
heat sink.

(LOW T.C. POTENTIOMETERI
lK!!

1.5mA

>:-4.-T_OOVREF
lN827
16.2VI
10K!!

300pF

Figure 8:
Buffered OAC Reference

78

STROBE

2 POLE LO PASS BUTTERWORTH FILTER
GAIN AT DC - +13dB.

Figure 9:
Power DAC Design Using 7105 D/A

ANOTHER WAY TO BUILD
A POWERFUL D/A CONVERTER

APPLICATIONS
Motor Control
An important application for power D/A converters is in pre·
cision motor control systems (position controllers). Digitally
controlled constant torque is best facilitated using the power
DAC circuit shown in Figure 10. The desired torque is set
by closing the appropriate DAC switches; this sets the DC
output of the DAC. Torque is directly proportional to motor
current, and the motor current is directly proportional to
the voltage across RS, i.e.,

Intersil will shortly introduce a D/A converter which operates
on a new concept (no R/2R ladders or weighted resistors,
etc.l. Instead of dividing current or voltage into many small
steps, the 7105 DAC divides time. The output configuration
consists of a SPDT switch. A clock oscillator is prbvided, and
data latches for the digital input. For a n·bit converter, in any
2 n consecutive clock pulses, the switch is thrown one way
for a number of pulses corresponding to the input data and
the other way for the remainder. Thus, if the switch is used
to connect a reference voltage or current to an appropriate
filter, the average output corresponds to the digital input as
a ratio of the reference. The switching cycle is arranged so
as to minimize the filtering required on the output; and hence
optimize the settling time. By its very nature, this technique
insures monotonicity and (except for two short sections
near zero and full scale I excellent linearity. Other than the
reference, no critical value components are needed, and the
tolerance and temperature coefficients of the filter components affect only the settling time and ripple content. The
main limitation of the converter is the relatively slow conversion rate. The technique does for D-to·A conversion what
the dual·slope technique does for A/D conversion, that is it
provides a slow but very accurate and stable conversion tech·
nique that avoids the use of high tolerance components.

Torque

= Kim = - KVl

RS
By setting the DAC input switches 20, 2 1 ,22, etc., any de·
sired torque can be obtained and a torque versus time profile
can be established. Torque versus time profiles are important
in controlling the acceleration and deceleration of motors
and may be used to provide dynamic breaking for different
load conditions. The digital control could be performed by
a microprocessor or a programmahle logic array such as Intersil's,IM5200 (Ref. 11.
Programmable Power Supply
Another big application for power DACs is the digitally can·
trolled power supply. It is probably that the coarse and fine
control adjustment knobs on power supplies will be replaced
in the future by digit switches. With this, the user does not
need to use a 3)1, digit DVM just to set a power supply. An
8·bit power DAC allows the supply to be set instantly and
provided remote control automatically_The practical problem one runs into here is the maximum load capacity the
power DAC can drive without oscillating. Power supplies
often use O.lI1F to 100llF decoupling capacitors to ground;
this will cause most op amps to oscillate, including the 8510.
The only answer for this application is to reduce the bandwith to gain CL drive capability. Of course, the lower the
bandwith, the bigger the value of CL to keep the output
impedance to a certain minimum value; thus there is a compromise involved here. This compromise is not unique to the
8510; the amplifiers in typical series pass regulators must
also be designed to handle capacitance loads without misbe·
having. Another possible solution is to isolate the amplifier
output from the load by using a series inductor. Thus, when
large decoupling capacitors to ground are used, the amplifier
still sees at least the inductance as a load.

A suitable interconnection between a 7105 D·toA converter
and the 8510 power amplifier is shown in Figure 9. Note
that two pole filtering is adequate for 8 through 12 bit can·
verters, but three pole is required for optimum settling time
on 14 and 16 bit devices.

BUFFERED
OUTPUT
FROM 7520

GAIN - 1 5

>--"""",.....-~-!.I

RS

RW
Figur. 10:
Power DAC Driving DC Motor

79

Quad Current Switches For D/ A Conversion
BASIC D/A THEORY

10.0 volts the maximum output would be

The majority of digital to analog converters contain the
elements shown in Figure 1. The heart of the 01A converter is
the logic controlled switching network, whose output is an
analog current or voltage proportional to the digital number
on the logic inputs. The magnitude of the analog output is
determined by the reference supply and the array of
precision resistors, see fig. 2. If the switching network has a
current output, often a transconductal1ce amplifier is used to
provide a voltage output.
LOGIC INPUTS

REFERENCE

SWITCHING NETWORK

RESISTOR ARRAY

Figure 1: Elements of a D/A Converter

Nominal
Output
Current (mA)
1.875
1.750
1.625
1.500
1.375
1.250
1.125
1.000
0.825
0.750
0.625
0.500
0.375
0.2.50
0.125
0.000

Logic Input
0000
000 1
001 0
001 1
o1 0 0
o1 0 1
o1 1 0
o1 1 1
1 000
1 0 0 1
101 0
101 1
1 1 00
1 10 1
1 1 1 0
1 1 1 1

:g~~ X 10V. Since

the numbers are extremely close for high resolution systems,
the terms are often used interchangeably.
The accuracy of a O/A converter is generally taken to mean
the largest error of any output level from its nominal value.
The accuracy or absolute error is often expressed as a
percentage of the full scale output.
Linearity relates the maximum error in terms of the deviation
from the best straight line drawn through all the possible
output levels. Linearity is related to accuracy by the scale
factor and output offset. If the scale factor is exactly the
nominal value and offset is adjusted to zero, then accuracy
and linearity are identical. Linearity is usually specified as
being within ±1/2 LSB of the best straight line.
Another desirable property of O/A converter is that it be
monotonic. This simply implies that each successive output
level is greater than the preceding one. A possible worst case
condition would be when the output changes from most
significant bit (MSB) OFF, all other bits ON to the next level
which has the MSB ON and all other bits OFF, e.g., 10000 ...
to 01111.
In applications where a quad current switch drives a
transconductance amplifier (current to voltage converter),
transient response is almost exclusively determined by the
output amplifier itself. Where the quad output current drives
a resistor to ground, switching time and settling time are
useful parameters.
Switching time is the familiar 10% to 90% rise time type of
measurement. Low capacitance scope probes must be used
to avoid masking the high speeds that current source
switching affordS. The settling time is the elapsed time
between the application of a fast input pulse and the time at
which the output voltage has settled to or approached its
final value within a specified limit of accuracy. This limit of
accuracy should be commensurate with the resolution of the
OAC to be used.
Typically, the settling time specification describes how soon
after an input pulse the output can be relied upon as accurate
to within ±1/2 LSB of an N bit converter. Since the 8018A
family has been desiged with all the collectors·of the current
switching transistors tied together, the output capaCitance is
constant. The transient response is, therefore, a simple
exponential relationship, and from this the settling time can
be calculated and related to the measured rise time as shown
in Figure 3.

Figure 2: Truth Table

DEFINITION OF TERMS
±1/2 LSB Error
Number of
Number of
Bits of
Resolution % Full Scale Time Constants Rise Times
6.2
2.8
.2 %
8
3.4
.05%
7.6
10
9.2
4.2
12
.01%
Rise Time (10%-90%) = 2.2 RL Ceff

The resolution of a 01 A converter refers to the number of
logic inputs used to control the analog output. For example,
a 01 A converter using two quad current sources would be an
8 bit converter. If three quads were used, a 12 bit converter
would be formed. Resolution is often stated in terms of one
part in. e.g .. 256 since the number of controlling bits is
related to total number of identifil!ble levels by the power of
2. The four bit quad has sixteen different levels (see Truth
Table) each output corresponding to a particular logic input
word.
Note that maximum output of the quad switch is 1 + 1/2+ 1/4
+ 1/8 = 1-7/8= 1.875 mAo Ifthis series of bits were continued
as 1/16 + 1/32 + 1/64 ..... 112 n-1, the maximum output limit
would approach 2.0 mAo This limiting value is called full scale
output. The maximum output is always less than the full
scale output by one least significant bit, LSB. For a twelve bit
system (resolution 1 part in 4096) with a full scale output of

Figure 3: Settling Time vs. Rise Time ReSistor Load

CIRCUIT OPERATION
An example of a practical circuit for the ICL8018A quad
current switch is shown in Figure 4. The circuit can be
analyzed in two sections; the first generates very accurate
currents and the second causes these currents to be
switched according to input logiC signals. A reference
current of 125pA is generated by a stable reference supply
and a precision resistor. An op-amp with low offset voltage
80

LOGIC INPUTS
, ,_ _~A~_ _- - - . ,

i-I

BIT 4
5

BIT 3
4

BIT 2
3

BIT 1
2

I

v+

I
I
I

Rs

L

IREF

VOUT

IN914
Rs

BOk

10

11

12

13

80k

40k

20k

10k

14

Figure 4: Typical Circuit

and low input bias current, such as the ICLBOOB, is used in
conjunction with the internal reference transistor, 06, to
force the voltage on the common base line, so that the
collector current of 06 is equal to the reference current. The
emitter current of 06 will be the sum of the reference current
and a small base current causing a drop of slightly greater
than 10 volts across the BOk resistor in the emitter of 06.
Since this resistor is connected to -15V, this puts the emitter
of 06 at nearly -5V and the common base line at one VSE
more positive at -4.35V typically.
Also connected to the common base line are the switched
current source transistors 07 through 010. The emitters of
these transistors are also connected through weighted
precision resistors to -15V and their collector currents
summed at pin B. Since all these transistors, 06 through 010,
are designed to have equal emitter-base voltages, it follows
that all the emitter resistors will have equal voltage drops
across them. It is this constant voltage and the precision
resistors at the emitter that determine the exact value of
switched output current. The emitter resistor of 07 is equal to
that of 06, therefore, Ois collector current will be IREF or
125,uA. Oa has 40k in the emitter so that its collector current
will be twice IREF or 250,uA. In the same way, the 20k and 10k
in the emitters ofOg and 010 contribute .5 mAand 1 mA to the
total collector current.
The reference transistor and four current switching
transistors are designed for equal emitter current density by
making the number of emitters proportional to the current
switched.
The remaining circuitry provides switching signals from the
logic inputs. In the switch ON mode, zener diodes Ds
through Da, connected to the emitter of each current switch
transistor 07 thru 010, are reverse biased allowing the
transistors to operate, producing precision currents
summed in the collectors. The transistors are turned off by

raising the voltage on the zeners high enough to turn on the
zeners and raise the emitters olthe switching transistor. This
reverse biases the emitter base diode thereby shutting off
that transistor's collector current.
The analog output current can be used to drive one load
directly, (1 kfl to ground for FS = 1.B75V for example) or can
be used to drive a transconductance amplifier to give larger
output voltages.

EXPANDING THE QUAD SWITCH
While there are few requirements for only 4 bit D to A
converters, the 801BA is readily expanded to Band 12 bits
with the addition of other quads and resistor dividers as
shown in Figure 5.
To maintain the progression of binary weighted bit currents,
the current output of the first quad drives the input of the
transconductance amplifier directly, while a resistor divider
network divides the output current of the second quad by 16
and the output current of the third by 256.
e.g., ITotal= 1 x(1 +1/2+1/4+1/B)+1/16(1+1/2+1I4+1/B)
+ 11256 (1 + 1/2 + 1/4+ 1/B)= 1 + 1/2+ 1/4+ 1/8+
1/16 + 1/32 + 1/64 + 1/128 + 1/256 + 1/512 +
1/1024 + 1/204B.
Note that each current switch is operating at the same high
speed current levels so that standard 10k, 20k, 40k and BOk
resistor networks can be used. Another advantage of this
technique is that since the current outputs of the second and
third quad are attenuated, so are the errors they contribute.
This allows the use of less accurate switches and resistor
networks in these positions; hence, the three accuracy
grades of .01%, 0.1%, and 1% for the B018A, B019A and
B020A, respectively. It should be noted that only the
reference transistor on the most significant quad is
required to set up the voltage on the common base line
joining the three sets of switching transistors (Pin 9).
81

ANALOG
VOLTAGE OUT

VREF

LOGIC INPUTS
,---A------,

LIRE,

B018A
(0.01%)

B019A
(0.1%)

8020A
(1.0'1.)

Figure 5: Expanding the Quad Switch

the external zener will dominate the temperature
dependence of this scheme, however using a temperature
compensated zener minimizes this problem. Since 06 is
operating at a higher current density than the other
switching transistors, the temperature matching of VeE'S is
not optimum, but should be adequate for a simple 8 or 10 bit
converter.
The 8018A series is tested for accuracy with 10V reference
Yoltage across -the preciSion resistors, implying use of a 10
volt zener. Using a different external zener voltage will only
slightly degrade accuracy if the zener Yoltage is above 5 or 6
volts.
When using other than 10 volt reference, the effects on logic
thresholds should also be noted (see logic levels below). Full
scale adjustment can be made at the output amplifier.

GENERATING REFERENCE CURRENTS ZENER REFERENCE
As mentioned above, the 8018A switches currents
determined by a constant voltage across the external
precision resistors. in the emitter of each switch. There are
several ways of generating this constant voltage. One of the
simplest is shown in Figure 6. Here an external zener diode is
driven by the same current source line used to bias internal
Zener Dll.
v+
BIT 4
BIT 3
BIT 2
BIT 1
5

4

3

1
012

PNP REFERENCE
Another simple reference scheme is shown in Figure 7. Here
an external PNP transistor is used to buffer a resistor divider.
In this case, the -15 volt supply is used as a reference.
Holding the V- supply constant is not too difficult since the
8018A is essentially a constant current load. In this scheme,
the internal compensation transistor is not necessary, since
the VeE matching is provided by the emitter-base junction of
the external transistor. A small pot in series with the divider
facilitates full scale output adjustment. A capaCitor from
base to collector of the external PNP will lower output
impedance and minimize transient effects.

8

r--+_-+-_-+_>---+---+--t--<> lOUT
L....c........f-,-=-=--F-=:.:......++-=-t+-=--+-lr--=.:=....r----'- - - - TO
OTHER
QUADS
Q12

FULL COMPENSATION REFERENCE
10

11

12

+

10V

20k

13

14

For high accuracy, low drift applications, the reference
scheme of Figure 4, offers excellent performance. In this circuit, a high gain op-amp compares two currents. The first is a
reference current generated in Rs by the temperature compensated zener and the virtual ground at the non-inverting opamp input. The second is the collector current of the
reference transistor 06, provided on the quad switch. The
output of the op-amp drives the base of 06 keeping its
collector current exactly equal to the reference current.
Since the switching transistor's emitter current densities are
equal and since the preCision resistors are proportional, all
of the switched collector currents will have the proper value.

10k

-15V

Figure 6: Simple Zener Reference

The zener current will be typically 1 mA per quad. The
compensation transistor 06 is connected as a diode in series
with the external zener. The VeE of this transistor will
approximately match the VeE'S of the current switching
transistors, thereby forcing the external zener voltage across
each of the external resistors. The temperature coefficient of
82

BIT 4
5

BIT 3
4

BIT 2
3

V+
1

BIT 1
2

012

--TO
OTHER
QUADS
Q12

10k

10

11

12

&Ok

40k

20k

13

14

10k

-15Y

Figure 7: PNP Reference

+15Y
2k

360

OUTPUT OFFSET
ADJUST
10M

-1

+15V
3.9k

5k

Eour
10k

-15V

J

3.9k

30PF

R,.~

':'

14.0625k

14.0625k
RlS

R"
lk

937.5

IN914

51k

l000pF

R.

Rl3

A,2

All

10k

&Ok

40k

20k

-15Y
NOTE: ALL RESISTORS RATIO TO R,
UNLESS OTHERWISE NOTED.

R,
R2

As
R.
Rs

TOLERANCE TABLE
10k
0.1'10 ABS
20k
0.0122'10
40k
0.0244'10
&Ok
0.0488'10
10k
0.0H0J0

R.
R7

R.
R.
R,a
R"

20k
40k
10k
&Ok
10k
20k

Figure 8

83

0.195'10
0.391'10
0.781'10
0.1'10
0.5'10 ABS
RATIO TO R,a ''''

R'2
R'3

40k
&Ok
lk

R,s
R,.
R17

137.50

l'1oABS
l'1oABS

14.082Sk
14.082Sk

RATIO TO R,s 1'10
RATIO TO R,. 0.1'10

R,.

RATIO TO R,a ''''
RATIO TO R,a 1'10

The op-amp feedback loop using the internal reference
transistor will maintain proper currents in spite of VeE drift,
beta drift, resistor drift and changes in V-. Using this circuit,
temperature drifts of 2 ppm/· C are typical. A discrete diode
connected as shown will keep Qs from saturating and
prevent latch up if V- is disconnected.
In any reference scheme, it is advisable to capacitively
decouple the common base line to minimize transient
effects. A capacitor, .001/LF to .1/LF from Pin 9 to analog
ground is usually sufficient.

MULTIPLYING DAC
The circuit of Figure 9 is also convenient to use as a one
quadrant multiplying D/A converter. In a multiplying OAC,
the analog output is proportional to the product of a digital
number and an analog signal. The digital number drives the
logic inputs, while the analog signal replaces the constant
reference voltage, and produces a current to set up the
regulating SOOS op-amp. To vary the magnitude of currents
being switched, the voltage across all the 10k, 20k, 40k and
SOk resistors must be modulated according to the analog
input. An analog input ofOto+l0 volts and an SOk resistor at
the input to the SOOS will fulfill this requirement.

IMPROVED ACCURACY

CALIBRATING THE 12 BIT D/A CONVERTER

As a final note on the subject of setting up reference levels, it
should be pointed out that the largest contributor of error is
the mismatch of VeE's of the current switching transistors.
That is, if all the VeE's were identical, then all precision
resistors would have exactly the same reference voltage
across them. A one millivolt mismatch compared with ten
volt reference across the precision resistors will cause a .01 %
error. While decreasing the reference voltage will decrease
the accuracy, the voltage can be increased to achieve. better
than .01% accuracies. The voltage across the emitter
resistors can be doubled or tripled with a proportional
increase in resistor values resulting in improved absolute
accuracy as well as improved temperature drift performance.
This technique has been used successfully to implement up
to 16 bit 01 A converters.

1. With all logic inputs high (ones) adjust the outputamplifier
offset for zero volts out.
2. Put in the word 0000 11111111 (Quad 1 maximum output
Quad 2 and 3 off) and adjust full scale pot for Vo of 15/16
(10V) where full scale output is to be 10 volts.
3. Put in the word 1111 00001111 and trim the Quad 2 divider
for Vo of 15/256 (10V), This adjustment compensates for
VeE mismatches between quads although matched sets
are available (see data sheet).
4. Put in the word 11111111 0000 and trim the Quad 3 divider
for Vo of 15/4096 (10V),
5. Finally, with all bits ON (all O's) readjust the full scale
factor pot for
Vo = 4095/4096 (10V)

SYSTEM INTERFACE REQUIREMENTS

PRACTICAL DIA CONVERTERS

Using the S01SA series in practical circuits requires
consideration of the following interface requirements.
Logic Levels: The S01SA is designed to be compatible with
TTL, DTL and RTL logic drive systems. The one constraint
imposed on the external voltage levels is that the emitters of
the conducting current switch transistors be in the vicinity of
--5V; this will be the same as the voltage on Pin 6 if the
reference transistor is used. When using other than --5V at
Pin 6, the direct bearing on logic threshold should be
considered.
Power Supplies: One advantage of the ICLS01SA is its
tolerance of a wide range of supply voltage. The positive
supply voltage need only be large enough (greater than
+4.5V) to keep Qll out ofsaturation, and the negative supply
needs to be more negative than -10V to ensure constant
current operation of Q12. The maximum supply voltage of
±20V is dictated by transistor breakdown voltages. It is often
convenient to use ±15V supplies in systems with op-amps
and other I.C,'s. These supplies tend to be better regulated
and free from high current transients found on supplies used
to power TTL Logic. As with any high speed circuit, attention
to layout and adequate power supply decoupling will
minimize switching effects.
Ground: High resolution DIA, e.g., 12 bits require fairly large
logic drive currents. The change from all bits ON to all bits
OFF is a considerable change in supply current being
returned to ground. Because of this, it is usually advisable to
maintain separate ground points for the analog and digital
sections.
Resistors: Each quad current $witch requires a set of
matched resistors scaled proportional to their binary
currents as R, 2R, 4R and SA. For a 10V resistor voltage drop
and "2 mA" full scale output current, resistor values of 10k,
20k, 40k and SOk are convenient. Other resistor values can be
. used, for example, to increase total output current. The

The complete circuit for a high performance 12 bit O/A
converter is shown in Figure S. This circuit uses the "full
compensation reference" described above to set the base
line drive at the proper level, the temperature compensated
zener is stabilized using an op-amp as a regulated supply,
and the circuit provides a very stable, precise voltage
reference for the D/A converter. The 16:1 and 256:1 resistor
divider values are shown for a straight binary system; for a
binary coded decimal system the dividers would be 10:1 and
100:1 (BCD is frequently encountered in building programmable voltage sources).
The analog output current of the S01SA current switches is
converted to an output voltage using the S017 as shown. The
output amplifier must have low input bias current (small
compared with the LSB current),low offset voltage and offset
voltage drift, high slew rate and fast settling time. The input
compensation shown helps improve pulse response by
providing a finite impedance at high frequencies for a point
that is virtual ground at DC.
An alternative bias scheme is shown in Figure 9.ln this case,
the bias at the common base line is fixed by inverting op-amp
A4, the gain of which is adjusted to give --5.0 volts at the
emitter of the reference transistor. With the bias at the common base line fixed, the regular circuit of A1 uses the internal
reference transistor and drives the bus connecting all the
precision resistors. This isolates the precision resistors from
V- fluctuations. Zener D3 and constant current source Q1
keep the regulation SOOS op-amp in mid-range. There are
several alternative bias schemes depending on power
supplies available. If -20 volts is used for V-, the bottom of
the precision resistor will be at -15 and operation will be the
same as the standard circuit. If only -15V is available for Vthe gain of the output transconductance amplifier can be
increased by 30% to allow use of a smaller switching currents
with 7 volts across the precision resistors.

84

individual switched currents can be increased up to 100% of
their nominal values. The overall accuracy of the complete
DI A converter depends on the accuracy of the reference, the
accuracy of the quad current switch and tolerance of resistor
matching. Because of the binary progression of switched
currents, the tolerance of 80k/10k match can be twice that of
the 40k/10k which. in turn. can be twice the tolerance of the
20k/10k ratio and still have equal output current errors. The
current dividers between quads allows use of less well
matched sets of resistors further along in the D/A just as it
allows use of .01%. 0.1%, and 1% accurate quad current
switches. There are several manufacturers producing the
complete precision resistor networks required to implement
up to 12 bit D/A converters. Contact Intersil for additional
information .•
+15Y

2k

360

'Resistor Ladder Networks are manufactured by the
following companies:
Micro Networks Corporation
5 Barbara Lane
Worcester, Massachusetts 01604
Tel. (617) 756-4635
Allen-Bradley Company
1201 S. Second Street
Milwaukee, Wisconsin 53204
Tel. (414) 671-2000
Hycomp, Inc.
146 Main Street
Maynard, Massachusetts 01754
Tel. (617) 897-4578

-15V

20k

~.....,J\iO",UI\TPr"U_T

f

ADJUST
..O_F_F_S_E..
T _ _"""--f
10M

5k

EOUT

10k
·15V

:r
MULTIPLYING
o TO 10V

3.9k
30PF

14.0625k

13k

14.0625k
lk

4.35V

MULTIPLY
DAC
1000pF

I

Figure 9

85

-20Y

937.5

DIGITAL PANEL METER EXPERIMENTS FOR THE HOBBYIST
Digital displays have many advantages over their analog counter parts. They are more accurate, and more
rugged since there are no moving parts. Equally important, unskilled operators can record accurate data
due to the unambiguous nature of the readout. But
ready-built digital panel meters (DPMs) are costly
and, until recently, designing one's own from scratch
was an ambitious undertaking.

the voltage being measured. Since the maximum value
that can be displayed on the digital readout is 1999,
voltmeters with full-scale readings of 199.9mV,
1.999V, 19.99V, etc., are easily made. The user must
determine the full-scale reading that is most appropriate for his application. Then a reference voltage,
and in some instances an input attenuator, must be
selected.

Intersil's 7106 and 7107 one chip panel meter ICs
have changed all that. By adding only a display and
less than 10 passive components, anyone can build a
high performance DPM for less than the cost of a
good moving-coil meter. All that is needed is Ohm's
Law and a soldering iron! The hobbyist can have digital display of his aquarium temperature or the speed
of his saiiboat, the serviceman can build his own test
equipment, and the student of physics can measure
his plasma potential.

The relationship between the full-scale input voltage
and the reference voltage is very simple:
VIN (full-scale) = 1.999 x VREF
There is, however, a restriction on the magnitude of
VREF. It is not possible, for example, to measure a
199.9 volt signal by using a 100 volt reference - the
integrated circuit chip would be damaged by voltages
of this magnitude. The reference voltage should be
between +1 OOmVand +1 volt, and to achieve the oneto-one relationship between VIN and the displayed
value, it should be exactly +100.0mV or +1.000V.
The evaluation kits are supplied with the components
necessary to build a 200mV (or, to be precise, a
199.9mV) full-scale panel meter. The kit application
note (A023) explains how to change the sensitivity
from 200mV to 2V full scale.

The starting point for designs such as these is one of
Intersil's digital panel meter kits. Two kits are offered.
One uses a liquid crystal display (LCD), and is intended to be powered by a 9V 'transistor radio'
battery. The other uses light emitting diode (LED)
displays, and will usually be driven by an external
power supply. The kits include all the components
necessary to build a 200mV full scale panel meter,
including the IC, circuit board, display, passive components and miscellaneous hardware. They are available from Intersil's distributors; the LCD kit (part
#ICL7106 EV/KIT) sells for $29.95, the LED kit
(part #ICL7107 EV/KIT) sells for $24.95. Figure 1
shows what the kits look like after assembly. Included
in the kit is a detailed application note (#A023) entitled Low Cost Digital Panel Meter Designs, which
includes assembly instructions and schematics. For
reference, the circuit diagram of each kit is repeated
in Appendix I.

To measure voltages greater than 2 volts, an input attenuator is needed as shown in Figure 2.
Now the full-scale sensitivity is given by:
VIN (full-scale) = 1.999 VREF x

(~~ + R2)

For a panel meter which is to be used on a single fixed
range, it is not necessary to buy .05% (1 in 2000) or
better resistors. Any small variations in the ratio
R2/( R 1 + R2) can be compensated by tweaking the
reference voltage. It is important, however, that the
ratio remains fixed for the calibration period of the
instrument. Metal film resistors with good long-term
drift characteristics should be used. It is also important to use low temperature coefficient types, otherwise small temperat!,lre changes will effect the full
.scale accuracy to an undesirable extent.

The following discussion uses the assembled panel
meter as a basic building block and explains how it
can be used to make fundamental electrical measurements of voltage, current, and resistance. Very little
circuit deSign knowledge is assumed; the discussion
is primarily directed towards engineers, technicians,
students and hobbyists from fields other than electronics.

The input attenuator obviously reduces the input resistance ofthecircuitfrom > 1012 ohms to (R, + R2)'
This places an upper limit of about 10Mn on the input resistance that can readily be achieved when using
an attenuator before the A/D input current causes offset errors_

A. DC VOLTAGE MEASUREMENTS
The most frequently measured electrical parameter is
voltage. I n the majority of applications, it is desirable
to have the displayed reading correspond directly to

86

B. MULTI·RANGE DVM's

(20Hz to 5kHz) and introduces no DC errors since
the CA 3140 is capacitively coupled to the 7106/7107.
It should be realized, however, that this circuit is responding to the average value of the applied waveform.
The majority of AC voltmeters, on the other hand, are
required to read RMS values. For a sinusoidal waveform, the relationship between the average value and
the RMS value is fixed. Thus by altering the gain of
the AC to DC converter (the 2kn potentiometer Figure 51, the output can be adjusted to read RMS. But
the more the measured waveform deviates from a sinewave, the greater will be the error. Other waveforms
with fixed form -factors can be measured in a similar
manner, provided the relationship between the average and the RMS value is known.
In applications where the AC waveforms being measured have widely varying form-factors, a true RMS
converter should be used. National's LH0022 and
Analog Devices' Model 536 are suitable. In any event,
the subject of AC and DC converters is a complex
one. The reader wishing to pursue the subject in greater
depth is referred to Reference 1.
D. RESISTANCE MEASUREMENTS
The best way to measure resistance is to use the socalled ratiometric technique. The unknown resistance
is put in series with a known standard and a current
passed through the pair. The voltage developed across
the unknown is applied to the input (between IN HI
and IN LO), and the voltage across the known resistor
applied to the reference input (between REF H I and
REF LO). If the unknown equals the standard, the
integrate and de -integrate ramps will be of equal
slope and the display will read 1000. In general the
displayed reading can be determined from the following expression:

Multiple range voltmeters are frequently required and
are easy to implement using the 7106 or 7107. The
full-scale voltage is selected via a rotary or push -button
switch, or possibly an analog gate. Two schemes are
commonly used, as shown in Figure 3a and 3b.
The circuit of Figure 3a has the advantage that any
switch contact resistance appears in series with the
7106/7107 input. Since the input resistance is> 10 12n,
errors due to the switch are negligible. Another advantage is that precision voltage attenuators (R 1
through R5) are available from a number of manufacturers. Allen Bradley, for example, makes a thin film
network which contains 1 K, 9K, 90K, 900K and 9Mn
resistors in one package (FN207) - ideal for a fiverange voltmeter. Most hobbyists, however, will find
that it is less expensive to use medium precision resistors in series with potentiometers for the attenuator. Then the schematic of Figure 3b has some advantages because the resistors in the attenuator are
non -interactive. Setting up the 10: 1 attenuator, for
example, has no influence on the 100: 1, the 1000: 1,
etc., The circuit of Figure 3b is also more amenable
to solid state range switching. An analog switch or
FETs may be used in place of the mechanical switch.
Then, by adding a couple of zener diodes (or ordinary
silicon diodes in the case of a 200mV F.S. panel
meter) the solid state switch is totally protected
against overvoltages. By contrast, the configuration
of Figure 3a exposes the switch to the full-input
voltage, which may be several hundred volts. However, in 3b the switch resistance forms part of the
attenuator and could contribute an error.
So far we have only discussed full-scale voltages of
200mV or greater. On the 200mV scale, the least
significant digit represents 100llV steps. To resolve
smaller signals, it is necessary to use an operational
amplifier prior to the 7106/7107 inputs. It is quite
feasible to do this, provided one realizes that the
autozeroing circuitry within the panel meter cannot
take care of the op-amp offset or voltage drift. In
a 741 the drift may amount to as much as 151lVrC,
while a 308A will have no more than 5IlVrC.
The initial offset can of course be zeroed in the usual
way. Figure 4 shows a circuit with ±20mV full-scale
and an input resistance greater than 1OMn.

Displayed reading =

~ :A~NDOA~~

x 1000

Figure 6 shown a typical resistance measurement circuit. Note that due to its ratiometric nature, the technique does not require an accurately defined reference
voltage. The display will overrange for R UNKNOWN
;> 2 x R STANDARD.
E. CURRENT MEASUREMENTS
Current must be converted into voltage through the
use of a shunt resistor. The relationship between the
current and the displayed reading for the circuit of
Figure 7 is given by the following expression:

C. AC VOLTAGE MEASUREMENTS
The 7106 and 7107 will not measure AC voltages directly; an AC to DC converter is needed. The least expensive way to build such a converter is to use an opamp and some diodes in a half or full wave rectifying
circuit. The type of circuit shown in Figure 5 has been
used extensively in commercial 3% digit DVM's. It
has high input impedence (10Mnl, good bandwidth

lin x Rs
Displayed reading = -V-- x 1000
REF
In most current measurement applications, it is preferable to use a reference voltage of 1OOmV. This minimizes the shunt resistance and, therefore, the voltage
dropped across the shunt. A multirange current meter

87

is shown in Figure 8. Note that although the input
current passes through the selector switch, I R drops
across the switch do not contribute to the measured
voltage.
F. ARBITRARY SCALE FACTORS
We have already noted that one of the advantages of a
digital display is the unambiguous nature of the readout. When measuring other physical parameters, such
as temperature, it is equally desirable to display
78.0°C, for example, as 78.0. With the 7106 or 7107
this can readily be achieved, even though the temperature sensing element may be a diode which changes
-2.1mVrC.
For scale factors between 100mV and 1mV per least
significant digit (LSD), simply determine the reference
voltage required from the following equation:
VREF = (Voltage change represented by 1 LSD) x 103

consider a 0 to 2000 lb. weighing machine with a transducer that puts out 3. 7m V per pound. An input attenuation network that reduces the input signal to
1mV/lb will give the desired scale factor.
G. TEMPERATURE MEASUREMENT
Many of the points discussed in the foregoing sections
can be illustrated by considering the design of a digital
thermometer. We have already seen how a diode-connected transistor can be used as the sensing element,
since VBE has a temperature coefficient of about
- 2.1mVrC. Setting the reference at around 210mV
will give the desired scale factor of 0.1°C per count.
The other problem that must be considered is the zero
adjustment. At O°C and 1OOIlA bias current, the diode
will have a forward voltage of about 550mV. In order
for the meter to read zero at O°C, we must set up a
fixed 550mV (approx.) source that can be used to
offset the diode drop. Since the voltage between V+
and common is internallv reaulated at about 2.8 volts
in the 7106 and 7107, this is easily achieved. In the
circuit of Figure 9, R5 should be adjusted to give
000.0 output reading with Q1 at O°C. Then R4
should be adjusted to give 100.0 reading with Q1 at
100°C.

For example, in the temperature-sensing diode discussed aoove, we may want the ieast significant digit
to represent 0.1°C, which would correspond to a
voltage change across the diode of 210/lV. To
achieve this sensitivity, the reference should be set at
210llV x 1000= 210mV.
For scale factors greater than 1mV/LSD, the most
straight forward approach is to use an input attenuator in conjunction with a 1 volt reference. For example,

FIGURE 1: DIGITAL PANEL METER KITS FOR THE EXPERIMENTER.

88

r---------------,
I

EVALUATION KIT

I

",

I

L _______________ JI

FIGURE 2: INPUT ATTENUATOR FOR VIN;;;' 2.0V.
200mV F.S.

2VF.S.

900K
20V F.S.

200V F.S.

OK
2000V F.S,'

lK
INLO

L ______ _

FIGURE 3(a): MUL TIRANGE VOLTMETER
'CAUTION: High voltages can be lethal. Proper operating precaution. must be observed
by the user. Intersi! assumes no liabilitY for unsafe operation.

r---

I

10Mu

'111M" {

~o,.u{ ~oo,.!{

2V ~

F.S/

~ ""f'

I

I

I

I

**1
I

I

~~~ [ - 2~~V ( - 2~~V ( -

1

• 200mV F.S. for all switch. open.

EVALUAT ION KIT

(VREF- 1oOrnV)

I
I

I
I

:=

I
I
I

I

L _____ .

FIGURE 3(b): MULTI RANGE VOLTMETER, ALTERNATIVE SCHEME.
SkI!

....

I
I

v-

--------EVALUATION KIT
(VREF ·100mV)

~

GNO*. IN THE ABSENCE OF SPLIT SUPPLY OPERATION,
''TEST'' (PIN 37) CAN BE USED AS GROUND.

FIGURE 4: 20mV FULL SCALE.

89

,-----

t

I
I

AC VOLTS

IN

470k!!

I

EVALUATION KIT
(V REF = 100mVl

IN HI

~.

I
I
I

2K

t~wl

3K

":"

L _____ _

GNO· = IN THE ABSENCE OF SPLIT SUPPLY OPERATION,
"TEST" (PIN 371 CAN BE USED AS GROUND.

FIGURE 5: AC TO DC CONVERTER
SELECT FOR CORRECT
VOLTAGE DROP

+-----,,----1 REF HI
R STANDARD

+--_--'L-_-I REF LO

DISPLAY

Q - - 4 - - - - , - - - - I I N HI
7106/7107

6--.---...L--4

IN LO

' - - - - - - - - 1 COMMON

FIGURE .6: RESISTANCE MEASUREMENT*.
(* REQUIRES SOME MODIFICATION TO THE KIT)

-

I

"N

Rs

I
I
I

11061
7107

=r=

I
I
I

T
I
IL _ _ _ _ _ _ _ _ _ _

FIGURE 7: CURRENT MEASUREMENT

r-----------

1

200j,jA F.S.

EVALUATION KIT
VREF = 100mV

T

900!l
2mA F.S.

~

~

90u

I

20mA

9u
200mA

.gu
2A

,11l

I
I
I
I
I
I
I
I
I
I
I
I
I
I

-

7108/
7107

I

1
TL __________ _

FIGURE 8: MULTIRANGE CURRENT METER.

90

22kll

1M!!

220kn

V+
IN LO

TEMP. SENSOR

TO
DISPLAY

IN HI

100kn
(20 turn)

REF HI
REF LO
COMMON
SCALE FACTOR
ADJUST

ZERO
ADJUST

FIGURE 9: DIGITAL THERMOMETER*
(* REQUIRES SOME MODIFICATION TO THE KIT)

APPENDIX 1 - EVALUATION KIT SCHEMATICS

ON

ON

+ -

+ -

ICL7106 WITH
LIQUID CRYSTAL DISPLAY

ICL7107 WITH
LED DISPLAY

91

Low Cost Digital
Panel Meter Designs
Including Complete Instruction.
for Intersil'. LCD and LED Kits

Intersil's 7106 and 7107 are the first ICs to contain all the
active circuitry for a 3 1/2 digit panel meter on a Single
chip. The 7106 is designed to interface with a liquid crystal
display (LCD) while the 7107 is intended for light-emitting
diode (LED) displays. In addition to a precision dual slope
converter, both circuits contain BCD to seven segment
decoders, display drivers, a clock and a reference. To
build a high performance panel meter (with auto zero and
auto polarity features) it is only necessary to add a display,
4 resistors, 4 capacitors, and an input filter if required
(Figures 1 and 2),

chip panel meter functions (lntersil's 7106 and 7107) has
reduced the design effort on the part of the user to zero.
The make or buy decision becomes a simple question of
dollars and cents.
At the time of writing, a 3112 digit LED display panel meter
can be built for $18 in production (5,000) quantities. This
figure includes labor at $3 per hour with 300% overhead.
The cost breakdown is as follows:
ICL71 07 (@5000pcs)
$ 5.95
LEOs (4)
3.00
Capacitors (5)
.58
Resistors (4)
.12

+'N-

Potentiometer

.50

Circuit Board
1.00
Misc. Hardware
---:Z§.
TOTAL COMPONENTS
$12.00
Labor
~
(1/2 hour at $3/hour, 300% overhead)
TOTAL COST
$18.00
including assembly and test
A 3 112 digit LCD panel meter, using the 7106, is $3 to $4
more expensive. This is due to the greater cost of the
display.
These cost figures are considerably lower than the
least expensive of the ready-built panel meters. However,
the cost is not the only advantage; the do-it-yourself
approach allows greater flexibility. Off-the-shelf panel
meters have form factors which are frequently
inconvenient, whereas a single IC design takes up a
minimum of circuit board real estate. Consider the
advantages for field servicing a military radar, for
example, if each complex circuit card had its own built-in
voltmeter and miniature switch. Fault finding would be
greatly simplified by making critical voltages throughout
the system instantly accessible.

Figure 1: LCD Digital Panel Meter Using ICl7106
'0

DECIMAL
POINT

THE EVALUATION KITS
After purchasing a sample of the 7106 or the 7107, the
majority of users will want to build a simple voltmeter. The
parts can then be evaluated against the data sheet
specifications, and tried out in the intended application.
However, locating and purchasing even the small number
of· additional components required, then wiring a
breadboard, can often cause delays of days or sometimes
weeks. To avoid this problem and facilitate evaluation of
these unique circuits, Intersil is offering a kit which
contains all the necessary components to build a 3 1/2
digit panel meter. With the help of this kit, an engineer or
technician can have the system "up and running" in about
half an hour.
Two kits are offered, the ICL7106EV/KIT and the
ICL 71 07EVlKIT. Both contain the appropriate IC, a circuit
board, a display (LCD for 7106EV/KIT, LEOs for
7107EV/KITl, passive components, and miscellaneous
hardware.

Figure 2: lED Digital Panel Meter Using ICl7107

COST ADVANTAGES OF 7106 AND 7107
Until recently, the make or buy decision for any A-to-D
system was dominated by the engineering costs. Even a
simple panel meter, built from off-the-shelf digital and
linear ICs, required at least six months of engineering
effort for completion. However, the advent of truly single
92

(a) Assembly Instructions
The circuit board layouts and assembly drawings for both
kits are given in the Appendices. The boards are singlesided to minimize cost and simplify assembly. Jumpers
are used to allow maximum flexibility. For example,
provision has been made for connecting an external clock
(Test Point #5). Provision has also been made for
separating REF Lo from COMMON when using an
external reference zener. In a production instrument, the
board area could be reduced dramatically. Asidefrom the
display, all the components can easily be placed in less
than 4 square inches of board space.
Molex® pins are used to provide a low cost IC socket; one
circuit board can thus be used to evaluate several ICs.
(Strips of 20 pins should be soldered onto the P.C. boards;
the top of the strip holding the pins together can then be
broken off by bending it back and forth using needle-nose
pliers). Solder terminals are provided for the five test
pOints, and for the ±5V input on the 7107 kit.

simple MOS inverter can be used (Fig. 3>' For instruments
where the decimal point must be shifted, a quad exclusive
OR gate is recommended (Fig. 4>. Note that in both
instances, TEST (pin 37, TP1) is used as V- for the
inverters. This pin is capable of sinking about 1 mA, and
is approximately 5 volts below V+. The B.P. outputipin 21)
oscillates between V+ & TEST.
y+

< 1Mn

Figure 3: Simple Inverter for Fixed Decimal Point

(b) Full Scale Reading - 200mV or 2.000V?
The component values supplied with the kit are those
specified in the schematics of Fig. 1 or Fig. 2. They have
been optimized for 200.OmV full scale reading. The
complete absence of last digit jitter on this range
illustrates the exceptional noise performance of the 7106
and 7107. In fact, the noise level (not exceeded 95% of
time) is about 15"V, a factor of 10 less than some
competitive one chip panel meters.
To modify the sensitivity to 2.000 volts full scale, the
integrator time constant and the reference should be
changed by substituting the component values given in
the Table below. The auto-zero capacitor (C2) should also
be changed. These additional components are not
supplied in the kits. In addition, the decimal pOint jumper
should be changed so the display reads 2.000.

y•

7106

200.0mV
Full Scale

2.000V
Full Scale

C2 (mylar)

0.47"F
24Kn
47KO

.047"F
1.5KO*
470KO

Rl
R2

DECIMAL

-

POINT
SELECT

_

H-I]'D+
H=J
: D+I

I

I

o

TEST

I

I

TO LCD
DECIMAL
POINTS

0

CD4030

I

L--T'-~

' - - - - - - - - - - ' \GND

Figure 4: Exclusive 'OR' Gate for Decimal Point Drive

Before soldering the display onto the circuit board, make
sure that it is inserted correctly. Many LCD packages do
not have pin #1 marked, but the segments of an
unenergized display can be seen by viewing with reflected
light. The package orientation should correspond with
that shown in Appendix I.

TABLE 1: Component Values for Full Scale Options

COMPONENT
(type)

.P~-.-H-J~:.
Dt}
r---t---\D-+,. - __!.v~_,

(d) Light Emitting Diode Display (7107)
The 7107 pull-down FETs will sink about 8mA per
segment. Using standard common anode .3" or .43" red
LEOs, this drive level produces a bright display suitable
for almost any indoor application. However, additional
brightness can be achieved through the use of Hewlett
Packard high-efficiency LEOs. Note that the display
contrast can be increased substantially by using a red
filter. Ref. 4 discusses filter techniques and lists
manufacturers of suitable materials.
A fixed decimal point can be turned on by tying the
appropriate cathode to ground through a 1500 resistor.
The circuit boards supplied with the kit will accomodate
either H.P. 0.3" displays or the popular MAN 3700 types.
The difference between the two is that the H.P. has the
decimal pOint cathode on pin 6, whereas the MAN 3700
uses pin 9. Due to the limited space on the circuit board,
not all decimal points are brought to jumper pads; it may
be necessary to wire directly from the 1500 resistor to the
display. For multiple range instruments, a 7400 series
CMOS quad gate or buffer should be used. The majority
of them are capable of sinking about 8mA.

*Changing Rl to 1.SKO will reduce the battery life of the 7106 kit.
As an alternative, the potentiometer can be changed to 2SKO.

(c) Liquid Crystal Display (7106)
Liquid crystal displays are generally driven by applying a
symmetrical square wave to the back-plane (B.p.>. To turn
on a segment, a waveform 1800 outof phase with B.P. (but
of equal amplitude) is applied to that segment. Note that
excessive D.C. voltages (>50mV) will permanently
damage the display if applied for more than a few minutes.
The 7106 generates the segment drive waveform
internally, but the user should generate the decimal point
front plane drive by inverting the B.P. (pin 21> output.** In
applications where the decimal pOint remains fixed, a
**In some displays, a satisfactory decimal point can be achieved
by tying the decimal front pldne to COMMON (pin 32). This pin
is internally regulated at about 2.8 volts below V+. Prolonged
use of this technique, however, may permanently burn-in the
decimal, because COMMON is not exactly midway between
B.P. high and B.P. low.
93

(e) Capacitors
The integration capacitor should be a low dielectric-loss
type. Long term stability and temperature coefficient are
unimportant since the dual slope technique cancels the
effect of these variations. Polypropylene capacitors have
been found to work well; they have low dielectric loss
characteristics and are inexpensive. However, that is not
to say that they are the only suitable types. Mylar
capacitors are satisfactory for Cl (reference ) and C2
(auto-zerol.
For a more detailed discussion of recommended
capacitor types, the reader is referred to page 3 of
Reference 2.

(9) The Reference
For 200.0mV full scale, the voltage applied between REF
Hi and REF Lo should be set at 100.0mV. For 2.000V full
scale, set the reference voltage at 1.000V. The reference
inputs are floating, and the only restriction on the applied
voltage is that it should lie in the range V- to V+.
The voltage between V+ and COMMON is internally
regulated at about 2.8 volts. This reference is adequate for
many applications and is used in the evaluation kits. It has
a typical temperature coefficient of 100ppm/oC.
The limitations of the on-Chip reference should also be
recognized, however. With the 7107, the internal heating
which results from the LED drivers can cause some
degradation in performance. Due to its higher thermal
resistance, plastic parts are poorer in this respect than
ceramic. The user is cautioned against extrapolating from
the performance of the kit, which is supplied with a
ceramic 7107, to a system using the plastic part. The
combination of reference TC. internal chip dissipation,
and package thermal resistance can increase noise near
full scale from 25 I'V to 80 I'V pk-pk.
The linearity in going from a high dissipation count such
as 1000 (19 segments on) to a low dissipation count such
as 1111 (8 segments on) can also suffer by a count or
more. Devices with a positive TC reference may require
several counts to pull out of an overload condition. This is
because overload is a low dissipation mode, with the three
least significant digits blanked. Similarly, units with a
negative TC may cycle between overload and a nonoverload count .as the die alternately heats and cools.
These problems are of course eliminated if an external
reference is used.
The 7106, with its negligible dissipation, suffers from
none of these problems. In either case, an external
reference can easily be added as shown in figures 7(a) or
7(b).
.

(f) The Clock
A simple RC oscillator is used in the kit. It runs at about
48kHz and is divided by 4 prior to being used as the
system clock (Fig. 5). The internal clock period is thus
83.3I'S, and the signal integration period (1000 clock
pulses) is 83.3mS. This gives a measurement frequency of
3 readings per second since each conversion sequence
requires 4000 clock pulses. Setting the clock oscillator at
precisely 48kHz will result in optimum line frequency
(60Hz) noise rejection, since the integration period is an
integral number of line frequency period (see Ref. 2 for
dlscussionl. Countries with 50Hz line frequencies should
set the clock at 50kHz.
710617107

-------------,
I

100pF

+----+.;,--o

--I

Y+

Y+
Y+

Figure 5: 710617107 Internal Oscillator/Clock

7106/71071
7106/7107
REF HI

An external clock can also be used. In the 7106, the
internal logic is referenced to TEST. External clock
waveforms should therefore swing between TEST and V+
(Fig. 6al. In the 7107, the internal logic is referenced to
GND so any generator whose output swings from ground
to +5V will work well (Fig. 6bl.

1.2 VOLT

IREFERENCE
IUNTEASIL

'CLI"',

y.

(a,

osc 1

40

7106

OSC 1 40

7107

(h) Power Supplies
The 7106 kit is intended to be operated from a 9 volt dry
cell. INPUT Lo is shorted to COMMON, causing V+ to sit
2.8 volts positive with respect to INPUT Lo, and V- 6.2
volts negative with respect to INPUT Lo.
The 7107 kit should be operated from ±5 volts. Noisy
supplies should be bypassed with 6.81'F capacitors to
ground at the pOint where the supplies enter the board.
INPUT Lo has an effective common mode range with
respect to GND of a couple of volts.
The precise value is determined by the po;"nt at which the
integrator output ramps within -.3V of one or other of the
supply rails. This is governed by the integrator time

5,

-o-J"L

TEST 37

a) 7106

(b'

Figure 7: Using an External Reference

+5,

b) 7107

Figure 6: External Clock Options

94

constant, the magnitude and polarity of the input, the
common mode voltage, and the clock frequency: for
further details, consult the data sheet. Where the voltage
being measured is floating with respect to the supplies,
INPUT Lo should be tied to some voltage within the
common mode range such as GROUND or COMMON.
If a -5 volt supply is unavailable, a suitable negative rail
can be generated locally using the circuit shown in Fig. 8.

Further evaluation should be performed with the help of a
precision DC voltage calibrator such as Fluke Model
343A. Alternatively a high quality 4 1/2 digit DVM can be
used, provided its performance has been measured
against that of a reliable standard.

DPM COMPONENTS: SOURCES OF SUPPLY
It has already been shown that the 7106 and 7107 require
an absolute minimum of additional components. The only
critical ones are the display and the integration capacitor.
The following list of possible suppliers is intended to be of
assistance in putting a converter design into production.
It should not be interpreted as a comprehensive list of
suppliers, nor does it constitute an endorsement by
Intersi!.
Liquid Crystal Displays
a) LXD Inc., Cleveland, Ohio, 216/831-8100
b) Hamlin Inc., Lake Mills, Wisconsin, 414/648-2361
c) lEE Inc., Van Nuys, California, 2131787-0311
d) Shelley Associates, Irvine, California, 714/549-3414
e) Crystaloid Electronics, Stow, Ohio, 216/688-1180

Figure 8: Generating Negative Supply from +5v

(I) Input Filters
One of the attractive features of the 7106 and 7107 is the
extremely low input leakage current, typically 1pA at
25°C. This minimizes the errors caused by high
impedance passive filters on the input. For example, the
simple RC (1 MO/.01!,F) combination used in the
evaluation kits introduces a negligible 1!'V error.

LED Displays (Common Anode)
a) Hewlett Packard Components, Palo Alto, California,
415/493-1212
b) Itac Inc., Santa Clara, California, 408/985-2290
c) Litronix Inc., Cupertino, California, 408/257-7910
d) Monsanto Inc., Palo Alto, California, 415/493-3300

PRELIMINARY TESTS

Polypropylene Capacitors
a) Plessey Capacitors, West Lake Village, California,
213/889-4120
b) 1MB Electronics Products, Santa Fe Springs,
California, 213/921-3407
c) Elcap Components, Santa Ana, California, 7141
979-4440
d) TRW Capacitors, Ogallala, Nebraska, 308/284-3611

(a) Auto Zero
With power on and the inputs shorted, the display should
read zero. The negative sign should be displayed about
50% of the time, an indication of the effectiveness of the
auto-zero system used in the 7106 and 7107. Note that
some competitive circuits flash negative on every
alternate conversion for inputs near zero. While this may
look good to the uninitiated, it is not a true auto zero
system!
(b) Over-range
Inputs greater than full scale will cause suppression olthe
three least significant digits; i.e. only 1 or -1 will be
displayed.
(c) Polarity
The absence of a polarity signal indicates a positive
reading. A negative reading is indicated by a negative
sign.

CA~TION: Potential trouble areas when constructing the evaluation kits.

1. Certain LCD displays have a protective plastic sheet
covering the plastic top. This sheet may be removed
after installing the display to maximize display
viewing.
2. Solder flux or other impurities on PC board may
cause leakage paths between IC pins and board
traces reducing performance and should be
removed with rubbing alcohol or some other
suitable cleaning agent. Displays should be
removed when cleaning as damage could result to
them.

3. Blue PC board material (PC75) has been treated
with a chemical which may cause surface leakage
between the input traces. It is suggested that the
board be scribed between the input traces and
adjacent traces to eliminate this surface leakage.
4. I n order to ensure that unused segments on the LCD
displays do not turn on, tie them to the backplane
pin (pin 21).

95

APPENDIX I:

7106 Printed Circuit Board Layout and Component I Placement

~ __________~____5_.5_0_0_±._OO_5______~___________ ~

r

...,

..J
t Jumper to dlspta), decimal lor temporary decimal point. See texl.

96

APPENDIX II:

7107 Printed Circuit Board Layout and Component' P1acement

_________
5.5_oo~_.OO_5_ _ _ _ _ _ _ _ _ ~

INTERSll 7107 LED DPM

• Jumpers can be inserted here 10 short IN LO 10 GND or COMMON.
t Jumper to decimal point II required

DF

97

MD

Building an Auto-ranging
DMM with the
ICL7103A/S052A
A/D Converter Pair
VIN = 200mV. Third, a300K potentiometer should replace the
300K!1 fixed resistor in the comparator translation network.
With VIN = 0 volts, this pot should be adjusted until the
display reads equal intervals of positive and negative signs.
This network brings the comparator output up to the threshold of the 7103A logic during auto-zero. The two JFET's
connected across the integrator cap maintain the integrity of
the integrator and auto-zero cap during a gross over range
condition.

INTRODUCTION
The development of LSI AID converters has carved the
pathway for a new category of low cost, accurate digital
panel meters (DPM) and digital multimeters (DMM)' The
7103A18052A AID pair represents an excellent example of
this new breed of converter products available today. The
outstanding attributes of this pair include:
• Accuracy guaranteed to ± 1 count over the entire
conversion range.
• Guaranteed zero reading for 0 volts input.
• Single reference voltage.
• Over-range and under-range signals available for autoranging.
• TTL compatible outputs.
• Six auxilliary outputs for enhanced interfacing capability.
In effect, the user has available a near perfect system. The
key to a successful design depends, almost exclusively, on
the individual's ability to prevent adding errors to the system.
The purpose of this applications bulletin is to describe the
operation and potential pitfalls of a 10/-,V resolution (VREF =
100mV) 4-1/2 digit auto-ranging scheme using the 7103A1
8052A pair. Two auto-ranging circuits are included within
the text. Each is discussed in terms ·of its advantages and
disadvantages. Section One is intended to familiarize the
reader with the circuitry common to both deSigns.

Input Divider
All auto-ranging systems use a resistive divider network of
some kind. The particular type of network used is important
and requires some thought. Shown below are two
conventionai divider networks.

R

~
I

DISPLAY

I

Type A

Ii

ANALOG

R LADDER

~

-"-

7103A

---".

14-

ANALOG'" 11
GROUND

13 ......

7

18

8OS2A

"V

'("

27

--

I'REFERENCE
INPUT

OVERRANGE\
UNDERRANGE \

"-----IlJ'.r.g.~LNrJ~?cl_

I

~

STROBE

"

.0101R

.OO1001R

(10.1.)

(1.001.)

REED RELA VS
ONLY

Type B

Each of these dividers has advantages and disadvantages.
For example, type B can be implemented with analog gating,
whereas, type A cannot. However, type B requires some form
of input protection to prevent destructive breakdown
when high voltage is applied.
The designer must also consider the potential hazards of
four additional sources of leakage current (3 switches plus
input protection). For 10/-,V resolution, these leakage
currents must be less than 1OpA forthe resistor values shown
above.
A major advantage to type A is its versatility. It can easily be
used to measure current and resistance as well as voltage.
Type A was chosen for this application primarily for this
reason. The absence of potential leakage current problems
was also an important factor in favor of type A.
Ohm's Converter (See main schematics)
Measuring an unknown resistance relies on the basic
fundamentals of ohm's law. The ohm's converter produces a
constant voltage (adjustable) which is applied to the ladder
network. A constant current is generated and the voltage
developed across the resistor in question is measured. Four
decades of resistance can be measured by connecting the
ohm's converter to the four pOints on the resistor ladder. The
op amp used should be a FET input device to eliminate
constant current source errors.

-

INPUT ... 10

0--

TO AID

.001VIN

BLOCK DIAGRAM

INHI

(1Mtl)

R
(90Ok)

DIGIT DRIVE 1

SECTION 1
7103A/8052A VARIATIONS FROM DATA BOOK SCHEMATIC
The basic circuitforthe 7103A/8052AA/D converter remains
unchanged. However, a few modifications are necessary to
accommodate a 100mV reference. First, the reference
voltage divider network (5.1 K, 1K) is modified for greater
resolution. Second, the integrator resistor is reduced to
1OK!1 to facilitate an approximate 8 volt integrator swing with

98

on. Auto-ranging is accomplished by shifting the active bit
either left or right until a non-over range (or under-range)
condition exists. The digital section associated with the
74195 varies between the two designs and will be discussed
later.

AC Converter
With the addition of a precision rectifier and a low pass filter,
AC measurements can be made. The precision rectifier
shown below is a conventional circuit used for this application. Tolerances can be reduced below± 1% by adjusting a
single potentiometer. The user can expect dependable
accuracy over a frequency range of 40Hz to 40kHz.

SECTION 2
This section is intended to familiarize the reader with
individual characteristics of each design.

10kJl

Schematic #1
The basic idea behind circuit #1 is to extend the auto-zero
time whenever an over range or under range condition
exists. If the auto-zero time is not long enough, it is possible
for the auto-ranging circuitry to continuously rock between
two adjacent scales. Basically, this phenomenon is due to a
residual deintegrate charge stored on the auto-zero cap
after an over range condition has occurred. The scale will
increment up one decade but an under-range may result on
the next conversion (VIN NET = VIN ACTUAL - Vresiduall. The
74121 extends auto-zero to 250ms whenever an under range
or over range occurs. This time extension should enable the
auto-zero loop to behave properly.

Precision Rectifier and Low Pass Filter.
Clock Circuit
The actual clock frequency is not of first order importance
assuminc it does not varv durin.c a conversion cvcle and is
within the limits dictated by the integrating resistor and
capacitor. However, some problems can result if the clock
wave form contains severe ringing or spikes. The 311 clock
generator shown in each schematic proved to be excellent
for this application. It did not generate current spikes on the
5 volt supply line and it remained stable during supply fluctuations due to variations in LED current.

When an under range or over range occurs, several things
happen. First, the true output of the 74121 goes high
enabling a shift pulse. At the same time the Q output goes
low causing the 7103A to hold in auto-zero. Nine hundred
clock pulses after the beginning of auto-zero, the
coincidence between 01 and strobe generates the clock
pulse that shifts the active bit in the register. Approximately
250ms after the beginning of Auto-zero, the single shot will
clear and another integrate/deintegrate cycle begins. The
process will repeat on subsequent under range/over range
conversions. One auto-range cycle requires approximately
450ms (200ms of integrate/deintegrate and 250ms of autozerol.

Decimal Point Logic
The anode of each decimal point used, (OP5, OP4, OP3) is
connected to the common anode pin of its respective 7
segment display. The position of the zero bit in the shift
register and the operating mode (KO or Volts) of the autoranging system determines which decimal point will be on.
The table below defines when each decimal point should be
on.

Dr" I-I

0.P.4

kO

D.P. = DECIMAL POINT

0.P.3

OPERATING MODE
Dev, Aev

Circuit #2 utilizes the 3'h-4'h digit mode of the 7103A to
auto-range in approximately one tenth the normal
conversion time. The system is designed to operate in a
normal 41/2 digit mode until auto-ranging is necessary. The
7474 0 flip-flop controls the 3'h-4'h .digit mode of the
7103A, but it has a rather interesting twist to insure
.
sufficient auto-zero time.
The integrator and comparator time constants are each
reduced by a factor of 10 at the beginning of auto-zero if
auto-ranging is required. However, the 7103A doesn't enter
the 3 'h digit mode until the input data tothe 7474 is clocked
intO the register. This occurs 900 counts after auto-zero
begins (01 strobel. The system completes the remainder of
auto-zero and the subsequent conversion in the 3 'h digit
mode at 10 times the normal conversion rate (approximately
33msl. The 1474 is then cleared 100 counts after the next
auto-zero begins (05. strobe) and a 4'12 digit mode is
resumed. If subsequent auto-scaling is not necessary, the
system continues to operate in the 4-1/2 digit mode, and if it
is necessary, the integrator and comparator time constants
remain in a 3-1/2 digit mode but the 7103A returns to a 4-1/2
digit mode when the 7474 is cleared. 800 counts later the data
is strobed into the register and the 7103A once again enters
the 3-1/2 digit mode and another3-1/2 digit conversion cycle
begins. The integrator and comparator will remain in the 3-1/
digit mode and the 7103A will switch to the 4-1/2 digit mOde
for only 800 counts of auto-zero (900 counts for the fi rst auto-

DIGIT 1

I-I I , I I
I.U.I 1.0 '_I
0.P.5

Schematic #2

D.P.S

D.P.4

D.P.3

2V Scale 20V Scale 200mV Scale
(8)
Ie)
IA)
200V Scale
101

2kO

(D)

20k!l Ie)

200k!l (8)

2Mn IA)

The letter in parenthesis indicates the location of the zero bit in the
shift register.
The two SPST switches (SW1, SW2) and the two transistors
(01, 02) provide the necessary switching. The only addition
to this circuitry is a single LED and a 1800 resistor. Connect
the anode to 5 volts and the cathode (through 1800 resistor)
to register A, and the LED will differentiate between the
200mV and 200 volt scales or the 2kO and 2MO scales.
SN74195 shift register
The 74195 shift left/shift right shift register is the heart of the
auto-ranging logic. The location of a single zero bit
determines which relay is closed and which decimal pOint is
99

Content. of Decade Counter.
Operating
Mode

1st AZ
after
invalid
conversion
Int.
Deint.
Subsequent
Auto-zero's

Most
Significant
Decade

Decade
4

Decade
3

Decade
2

Least
Significant
Decade

0

0

9

0

0

31/2

0

9

1

0

X

{ 31/2
31/2

1
2
0
0
0

0
0
1
0
8

0
0
0
8
2

0
0
0
0
0

X
X
X

4112 Digit

1
{

31/2
41/2
31/2

Gomments

900 counts after auto-zero begins, data is
strobed into 7474.
total clock periods needed to fill counters
with 1,000 equals 1810
next integrate cycle
max counts for deintegrate
7474 cleared
total counts of 4 1/2 digit auto-zero
remaining auto-zero counts

0
X

Counts required for first auto-zero = 1810 (~15ms)
Counts required for next conversion = 3000 max (~25ms)
Counts required for second, third or fourth auto-zero = 1720 (~14.3ms)
Total time required to auto-range through four decades" 300 ms (170 ms are required for the initial integrateldeintegrate
cycle)

logic 1, the shift clock is enabled; if D is a logic 0 and a shift
right condition exists the ciock is disabied. AND gate #iA
insures the active bit will not shift out otthe register when VIN
:;; lS.00mV.

zero after over-range or under-range) extends the effective
auto-zero time to 1720 counts instead of 1000 (1810 for the
first auto-zero after over-range or under-range>. The faster
time constants of the integrator and comparator, in addition
to the extended auto-zero, ensures proper operation of the
auto-zero loop and eliminates the possibility of oscillating
between adjacent ranges.

The 3 'h digit mode is disabled when register A is a logic 0
and a shift left occurs, or if register D is a logic 0 and a shift
right occurs. Basically, this means the 7103A/S052A will
convert small inputs (VIN:;; lS.00mV) and signals greater than
200 volts in a 4'h digit mode. This is accomplished with
AND gates #2B and #3B and OR gate #3.

The status of the 7103A/S052A is determined by 5 decade
counters in the 7103A. The least significant counter is
cleared and bypassed in the 3 'h digit mode. A closer look at
these counters, with respect to the auto-ranging Circuitry,
will clearly show the time available for auto-zero and
individual conversion periods.

The integrator and Comparator time constants are controled
by OR gate #4. Short time constants are enabled as soon as
an over range or under range occurs and they remain
enaf>led until a non-over-range/under range condition exists
and the 7474 is cleared.

The shift pulse to the 74195 is enabled by AND gate#2A.lfan
over range or under range occurs and register D contains a

4 1/2 DIGIT INVALID CONVERSION
INTEGRATOR

OUTPUT

FAST CONVERSION

I
I

I

I

II

OYERRANGE OR
UNDERRANGE

--I
7474 CLEAR
PULSE
(05 • STROBE)

I

U

I

7103A
OPERATING

I
I

41/2

MODe
INTEGRATOR
OR COMPARATOR
TIME CONSTANT
CONTROL
(0+0)

1

r100COUNTS

I

I

I

I
1

I

I
I

I

1-1
7474 CLOCK
(01 • STROBE)

~~

1%1

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I

••

#1

1
1

I

r--

U1

U

I

I
I

800 COUNTS

n

n
!

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I
I

31/2

~

I
I
I

31/2

r.
I
I

. NORMAL TIME CONSTANT

1110 NORMAL TIME CONST'ANT

Timing diagram for circuli #2

100

I
...

200mV
2M!l

I

0.0.5

LED

150U

.lET

_~

I

I

1 ~ IIII

.

t
0.0.4

DIGOT.
DECIMAL
POINT

0.0.3

DIGIT.
DECIMAL
POINT

DIGIT 3

DECIMAL
POINT

150Jl

C

}l'
I

ANODES CONNECTED to
OIGIT DRIVE TRANSISTORS
OF RESPECTIVE DIGITS

Dev

I

MsoD5

S'fR5iE

'''N~~
;

i

i

r=
114-7"02

STROBE
(PIN 18)

~

...
""",

Auto-Ranging Schematic #1

...

0.0.5

-yt~

LED

2MU

15011

A
ANODES CONNECTED
TO COMMON ANODE
OF 1 SEG. DISPLAY

;:;

'"

RESISTOR LADDER

Aulo-Ranglng Schemallc #2

t

0.0.3

0.0.4

DIGIT
5
DECIMAL
POINT

DIGIT.
DECIMAL
POINT

1500

C

SW2

~

CAUTION

• Unusually large rollover error.
a) Rollover is a result of the voltage drop on the auto-zero
capacitor during the reference integrate phase, and
stray capacitance present while charging CREF to the
reference voltage. For a1 volt reference, the 7103A1
8052A pai r is guaranteed to have less than one count of
rollover. With a 100mV reference, the rollover should
be less than 2 counts. If larger rollover errors are
present, clean the PC board, as any leakage current
path must be removed. Also be sure the auto-zero and
reference capacitors are high quality, low leakage
capacitors.
• Unusually large amount of count instaDility.
a) Check noise on the power supplies. If large current
spikes or 60 cycle noise are present, the converter will
appear noisy. Also, if the comparator translation
network (36k, 300k) is way out of adjustment, the
comparator will not respond conSistently to a zero
crossing.

Using the 7103A/8052A solves a great number of conventional AID design problems, however the user must pay
special attention to the components and the board layout for
the specific application. Listed below are some application
notes. If the user spends some time reviewing these bulletins, fewer headaches will result.

SYMPTOMS/SOLUTIONS
It is very easy to build a system containing several error
terms and if the user is unfamiliar with integrating AID
converters, a specific trouble shooting sequence may not be
apparent. This section is intended to, a, identify specific
errors, and b, suggest solutions.
• With VIN = OV, the display flashes zeros indicating an overrange.
a) Check power supplies. If the ±15V supply is not working
properly the 7103A/8052A may over-range.
b) Check all component connections corresponding to
the integrator, comparator, and analog switch network.
• With VIN = OV, display reads something other than zero
(offset error).
a) This symptom is typically a result of grounding
problems or digital signals coupled to analog lines.
Connect pin 11 (analog. ground) to the 100kO reSistor
at signal input. If the offset disappears, the problem is a
result of IR drops in the ground line. Reconnect ground
lines similar to Figure 3.
I/P
HI

ANALOG
SECTION

GENERALLY SPEAKING
• Minimize stray capacitance.
• Keep analog lines short.
• Build system around a stable analog ground.
LG

DIGITAL
SECTION

Figure 3

If the offset remains the same, check the proximity of
digital lines (digit drive. busy, under-range) to analog
lines. They should be separated as far as possible.
If the offset reduces but is not completely eliminated.
The problem is most likely due to both types of errors.

103

4 Y2 Digit Panel Meter

Demonstrator/
Instrumentation Boards
DEMONSTRATOR BOARD

Intersil's 8052A/7103A precision AID converter pair with its
multiplexed BCD outputs and digit drivers combines dualslope conversion reliability with ±1 count in 20,000 accuracy.
The two chip system features performance characteristics
such as 5pA input leakage, 0.002% linearity, auto-zero to
10/LV with drift less than 1/LV/o C, and scale factor
temperature coefficients of 3ppm/o C (with external
reference). With these outstanding features, the 8052AI
7103A two chip system is ideally suited for LED display
Digital Panel Meter (DPM) and Digital Multimeter (DMM)
applications.

Two versions of the complete circuit for a 4'h digit DPM with
±2.0000 volt full scale and LED readout will be discussed.
The first version, the Demonstrator Board, is shown in
schematic form in Figure 1. This circuit uses the internal
reference of the 8052A for conversion reference and a
buffered 2-inverter CMOS RC oscillator for the clock source.
The Demonstrator Board contains all the components and
displays for a 4'h DPM on one, double-sided PC board. In
addition, the BCD outputs, digit drivers, overrange,
underrange, run/hold and busy lines from the 7103 are
brought out to the edge connector making it possible to
interface the DPM to a microprocessor or UART. The PC
board layout diagram and component placement diagrams
are shown in figures 2, 3 and 4.

A2

l~

H~~_ _ :N~sJ
u & - - - - - - - - -.......-t---!!]. ICL'f,'03A
I
AI
I

I INPUT

~[!~~~y~I!~~~~~iJ
t
A13

.,y

I

I
I

I
I
I
I

EDGE CONNECTOR NUMBER ............ D

w

T

Figure 1: Demonstrator Board Schematic

104

------------------------~
ICL80152A17103A 41ft DIGIT
DPM DEMONSTRATOR BOARD

•

~:•
.0

..\

BACK

FRONT
Figure 2: Demonstrator Board Component Side

Figure 3: Demonstrator Board Back

Figure 4: Demonstrator Board Component Placement

105

.I

INSTRUMENTATION BOARDS

out to the edge connector. Both boards use single-sided
construction to simplify assembly and reduce fabrication
costs. Figure 6 shows the main board PC layout with the
component placement diagram in Figure 7. The display
board artwork is shown in Figure 8 with component
placement shown in Figures 9 and 10. Note that the displays
are mounted on the trace side of the display board while the
digit driver transistors, current-limiting resistors and the
decoder/driver IC are mounted on the opposite side of the
board.
-rcL80siAi71oaA -~:PLA-YBOARD1

The schematic diagram in Figure 5 is for the 4'h Digit
Instrumentation Boards which feature a lower component
count, a separate front panel display board and a compact
main board. The display board uses 5 similar LED Displays
for the full digits and the polarity/'h digit, with the 7-segment
decoder/driver on the reverse side of the board. The main
board uses the 8052 reference, a CMOS clock circuit with
variable frequency adjustment and has the BCD lines, digit
driver lines, supply and ground lines, and input lines brought

r--R; -.. . ----- -------------------- -------,.

SN7447AN

I

17
16

I
I

I
I
I

I

IL ______ _

_ _ _ _ _ _ _ _ _ _ _ ....t

12

13

11

15

"

1110 9 8 7 8 5 412

r----------------------------------I

- -- - - -- - - -- -- -- --- - -----------,iiios2AniiiiAl

IC2

MAIN BOARD

~~~

I

15~----......

24'IJDIQ/3 IhDIG

~----mPOLARITV
4 RUN/HOLD
COMPo IN

3~=:::::::;V\r:;.=;:=~~:-t,::;;;~B6 -15V
REF CAP2
~_________t:::...-.;:==tt:t::;'0 ANA IN

17~

8

18 E-

11 ANA GND

r-~vv~~~--I~~~~~~CLKIN

UNDRNG
'" OYRNG

1:1

CD4001A

I
I

012
02
03
04 24

I

ICI

I

ICL8052A
, -15Y

B8gl===~J

REF
REF CAP1

I

I

14~'--------------~~JL----~TI,r.~5V~~~~B~U;.SY~"

84 22
82

r----~r--;;=:::;;:u:~COMPOUT
REF CAP

I
I

INTOUT

+BUFIN
+lNT IN

I
2

REFIYPA" -INTINIil,~--~

DslP'B=====:J
i·

OND

B1

-aUF IN

REF OUT aUF OUTm..~o.N"-'
RlF SUPPLY
+15
R15

STROBE 1

AZINfi"~=====:tj-r1

AZ OUT II.
OIG GND 15

13

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ....1

~----------------------------------13

1

Figure 5: Instrumentation Board Schematic (Numerals refer to edge connector pin numbers)

18

BACK

Figure 7: Main Instrumentation Board Component Placement

Figure 6: Main Instrumentation Board Back
106

I.
FRONT

Figure 8: Display Instrumentation Board Artwork

T~A-=t

Figure 9: Display Instrumentation Board (Non-Conductor Sidel Component Placement

,.
fRONT

Figure

10: Display

Instrumentation

Board (Conductor Side) Component Placement

COMPONENT SELECTION

EVALUATION

The only critical components for the 4'h digit DPM circuits
are the reference, auto-zero and integrating capacitors, (C"
C2, and C3 respectively for the Instrumentation Boards and
C4, C12, and C'4 respectively for the Demonstrator Board!.
The reference and auto-zero capacitor should have low
dielectric absorption ID.A.l for quick start-up and recovery
from overload while the integrating capacitor requires low
DA for minimum rollover error and optimum ratiometric
measurement performance. A complete list of components
and suggested sources for each board may be found in
tables 1 and 2.

The Demonstrator and Instrumentation Boards both reflect
design considerations regarding the separation of digital
and analog ground lines, and grounding priorities to
minimize the effects of IR drops on the grounds of various
IC's. For instance, the analog ground of the 8052A (pin 5) is
not only kept separate from digital ground, but is in close
proximity to the edge connector to minimize the IR drop
along the conductor and, hence, minimize ground line
variations.
MD
107

Table I
ICL8052A17103A 4'12 DIGIT DIGITAL PANEL METER
Electrical Parts List for Demonstrator Board
Reference Designation
IC1
IC2
IC3
IC4
IC5
C1
C2,C3,C6,C7,C9C11,C13,C16,C17
C4,C12
C5
C8
C14
R1,R19,R22
R2,R14,R15,R21
R3,R4
R5
R6-R12,R23
R13
R16
R17
R18
CR1,CR2
DS1-DS4
DS5

Description
Analog AID Converter
Digital AID Converter
7-Seg ment. DecoderIDriver
Quad CMOS Nand Gate, 2-lnput
7-Transistor Array, Common Emitter
0.1ILF Ceramic Capacitor
10ILF Tantalum Capacitor

Recommended Manufacturer & Part Number
Intersil ICL8052A
Intersil ICL7103A
RCA CD4511BE
RCA CD4011AE
RCA CA3081
Sprague 7CZ5U104X0050D1
Kemet T39-C106-025AS

1.0ILF Polypropylene Capacitor
20%, 200V dc
100pF Mica Capacitor
300pF Mica Capacitor
0.22ILF Polypropylene Capacitor
100K!! V.W Resistor
39K!! V.W Resistor
330!! V.W Resistor
2.2K!! V.W Resistor
120!! V.W Resistor
82K!! V.W Resistor
300K!! V.W Resistor
510!! V.W Resistor
1K!! Trimmer
Small Signal Diode
7-Segment LED Display
±1 Polarity Display

TRW X363UW
Arco CM4FD101J03
Arco CM4FD301J03
1MB GA2A224

Beckman 76PR1K
1N914
HP 5082-7653
HP 5082-7656

Table II
ICL8052A17103A 4'12 DIGIT DIGITAL PANEL METER
Electrical Parts List for Instrumentation Board
Reference Designation
IC1
IC2
IC3
IC4
C1, C2
C3
C4 thru C7
C8
C9
C10
R1
R2 thru R9
R10
R11
R12
R13
R14, R15
R16
R17
R18
01,02
Q1 thru Q7
DS1 thru DS5

Description
Analog AID Converter
Digital AID Converter
7 Segment DecoderlDriver
Quad CMOS Nor Gate, 2 input
1.0 ILF Polypropylene Capacitor
0.22ILF Polypropylene Capacitor
10 ILF Tantalum Capacitor
100pF Mica Capacitor
300pF Mica Capacitor
0.1 ILF Polyester Capacitor
1kn Cermet Trimpot
120n V.W Resistor
510nv.W Resistor
200kH V.W Resistor
100kn Trimmer
47kn V.W Resistor
100KU V.W Resistor
4.7KH V.W Resistor
300kO V.W Resistor
36kn v. W Resistor
Small Signal Diodes
NPN Transistor
7 Segment LED Display
108

Recommended Manufacturer & Part Number
Intersi! ICL8052A
Intersi! ICL7103A
Texas Instruments SN7447AN
RCA CD4001AD
Plessey 171L105K160
1MB GA2A224
Kemet T39-C106-025AS
Arco CM4FD101J03
Arco CM4FD301J03
Siemens B325600.1/10/100
Bourns 3299P

Spectrol 62-3

IN914
Motorola MPS 3704
Fairchild FND507

One problem that exists on both PC boards regarding supply
line variations is that of the CMOS clock source. Since the
supply for the RC oscillator is shared with the LED display,
any variation in supply voltage due to the display reading will
also vary the supply voltage to the oscillator. The point at
which this variation becomes critical is when the display
changes from a fuil scale reading to overrange; i.e., 19999 to
0000. When in overrange, the display alternates between a
blank display (all segments off) and the 0000 over range
indication. The supply voltage to the CMOS oscillator varies
enough to cause a shift in the clock frequency. This shift
occurs during the signal integrate/reference integrate phase
of conversion causing a low display reading just after
overrange recovery. For instance, if the signal voltage is
1.99995 volts, the display reading should toggle between
1.9999 and overrange. However, the clock frequency shift
causes the display to read 1.9992 just after the 0000
overrange display before returning to the 1.9999 reading.
The severity of the reading variation after overrange
recovery depends on the magnitude of the clock variation
which gets back to the stability of the supply voltage line to
the RC oscillator.
The clock supply voltage modulation has been minimized on
both boards by separating the display supply lines from the
clock supply line. To eliminate any clock frequency shift
completely, a clock source using Intersil's LM311 voltage
comparator in positive feedback mode (Figure 11) could be
substituted.
Another problem encountered with the 8052A/71 03A DPM is
that of gross over-voltage applied to the input. Any voltage in
excess of ±2.0000 volts may cause the display to give an
erroneous voltage indication. The reason this occurs is the
integrator continues to ramp towards the supply (positive for
negative input voltages, negative for positive inputs) until the

+15V

integrator output saturates. When this occurs, the integrator
can no longer source (or sink) current required to hold the
summing junction (Pin 11) at the voltage stored on the auto
ze.ro capacitor. As a result, the voltage across the integrator
capacitor decreases sufficiently to give a false voltage
reading.
+5V

56kll

16kll

Figure 11: LM311 Clock Source
A simple solution to this problem is to use junction FET
transistors across the integrator capacitor to source (or sink)
current into the summing junction and prevent the integrator
amplifier from saturating. USing an N channel and a P
channel JFET, connect drains to pin 11 of the 8052A, sources
to pin 14, the gate of the P channel to +15V, and the gate of
the N channel to -15V (Figure 12). With the JFET's in this
configuration, input voltages ranging from 2 to 6 volts
positive and 2 to 10 volts negative will cause the correct
overrange indication to occur.

-15Y

lOOK

-BUF.IN.

8

7

1

1kH

16k!!

10---

aUF. OUT

.--

BUFFER

O.22.u.F

-INT. IN

INT. OUT

1 ' - - - 1.---1
INTEGRATOR

I
I
I

8052A

300pF

I
I

I

•

'---!--

I

!~FTN.----- ~+.rTTN--------'

~----------~~v~------------~
To 7103A

Figure 12: Gross Overvoltage Protection Circuit

109

!Zo

a::
u..

r:-:

Demonstrator Board Component Side

"-- ~

I ~. -. ~ "-/ t:."~
I . : .(0,,_0
~Ol

.
_

0

0 0

.0':::'

•

~

~

:f/IJ))V,.--..

--

.....

:.::
u
.v,

The first "quad current switches" were introduced two years
after the MA722 and were an excellent conceptual and technical approach to a practical data converter building block
circuit in monolithic form. These devices are now available

I"

in several circuit variations from different manufacturers

and are used extensively in hybrid data converters. The
basic circuit concept is illustrated in Figure 1.

DIGITAL

INPUT

0---1<1--1---1

~
--------+--..---f--'=--o

lour

G,

_ _ _ _ _ _ _ _ _ _-1-_ _ _ _- - 0 -v.

FIGURE 2. Detail Circuit of Quad Current Switching Cell

This particular circuit configuration gives standard TTL input voltage levels and results in a 40 nsec. switching time
with a current output settling time of about 200 nsec. to
0.01%.

'"

HYBRID D/A CONVERTERS

8R

High performance 12 bit D/A converters are made possible
by combining quad current switches with a precision zener
reference, reference control amplifier, a thin-film resistor
network, and a fast output operational amplifier as shown
in Figure 3.

-v,
FIGURE 1. Basic Quad Current Switch Circuit

Three quad current switches are used with a current dividing resistor network at the outputs of two of the quads.
With respect to QCS no. 1 output, QCS no. 2 output is
divided down by a factor of 16 and QC:; output no. 3 is divided down by a factor of 256. Due to the excellent accuracy
characteristics of the quad current switches, resolutions of
12 bits and higher may be realized in this manner.

There are four NPN current source transistors and a reference transistor as shown in the diagram. The bases are all
connected to a common line, and the reference transistor
together with an operational amplifier form a reference con-

trol circuit which biases all of the current sources. A precision, trimmed resistor network is used to set the currp.nts
in the sources in the binary ratiOS ot I, 21, 41, and 81. To

The output amplifier is a fast monolithic op amp which
operates as a current to voltage converter from the current

112

DATA ACQUISITIOIII & CONVERSION HANDBOOK

important factor in determining the converter absolute
temperature stability, tracking stability, and long term stability. When properly fabricated, these resistors result in
excellent stability, surpassing that achievable in all but the
most expensive discrete component converters.

CONNECTION
FOR BIPOLAR
OFFSET

L<>--t-----'--f:'--.
>----oVOUT

The fabrication of good quality thin film resistors iSa'process
involving many important operations. The following manufacturing steps are based Datel Systems' electron beam
evaporation technique of making nickel-chromium thin-film
resistor networks:
1. Oxidation of silicon substrate to form dielectric layer.
2. Deposition of nichrome thin film « 100.0\) by electron
beam evaporation.
3. Evaporation of barrier layer of nickel onto nichrome
film.
4. Photolithographic definition and gold plating of conductor pattern.
5. Photolithographic definition and etching of resistor
pattern.
6. Stabilization bake.
7. Photolithographic definition and etching of scribing
grid pattern.
8. Chemical vapor deposition of silicon dioxide paSSivation layer.
9. Photolithographic definition and etching of bond pad
openings over conductors.
10. Scribing and dicing wafer.
11. Test, inspection, and sorting of networks.

FIGURE 3. 12 Bit Hybrid 01 A Converter Circuit

outputs of the Quad switches. The reference control amplifier is connected differently from the one shown in Figure
1. By having the control amplifier drive the negative rail of
the current sources, better immunity against negative supply voltage variations is achieved while not affecting the TIL
input logic levels.
The circuit of Figure 3 is the basic design for Datel Systems' DAC-HZI2B series of high performance 12 bit D/A
converters. Because of the quad current switch circuit configuration the input coding for this device is complementary
binary, Le., all zero's on the inputs produce a full scale
output voltage and all one's produce zero output voltage.
This coding can be changed to straight binary by using external digital inverters. In the case of the DAC-HKI2B
series D/A converters an internal level-controlled storage
register is provided for storing a digital input word, and an
inversion is done in the register to give straight binary
coding.

:-====
:.

NICKEL

NICHROME

OXIDE

L __________.J----S'LiCON

.------NICKEL
~----GOLD

By adding a fourth Quad current switch to the circuit shown
in Figure 3, additional resolutions of 13 to 16 bits can be
attained. True 16 bit linearity is generally not possible,
however, but a more practical specification of 16 bit resolution with 14 bit linearity is achievable over a reasonable
temperature range. This performance is realized by Datel
Systems model DAC-HPI6B which has a companion model
DAC-HPI6D for 4 digit BCD applications.

I ____ SILICON

'111 a:;;~E====OX'OE
I
-'~---OXIDE
GOLD

NICKEL

L __________

-.l-----SILICON

An important feature designed into 12 bit hybrid D/A converters is the useful pin-programmable voltage output ranging. This is done, as shown in Figure 3, by providinga tapped
feedback resistor for use with the output amplifier. The
feedback resistor can thus be connected as R, 2R, or R/2
to give three possible voltage ranges. Another resistor is
provided in series with the reference to permit offsetting
the analog output by one half scale for bipolar operation.
The final result of this is five useful output voltage ranges:
o to +5V, 0 to +IOV, ±2.5V, ±5V, and ± IOV, all by simple
pin connection.

FIGURE 4. SummarY 01 Steps in Making A Nichrome
Thin-Film Resistor

Figure 4 summarizes some of the steps described above
in processing a thin film resistor network. A starting three
inch silicon wafer is shown together with a completely processed wafer in Figure 5; approximately 70 resistor networks are contained on this wafer. Each finished, tested
resistor network is then bonded to the converter substrate.

Two of the primary advantages of the new hybrid D/A converters are their completeness (requiring no extra components for operation) and their operating flexibility, both at
relatively low cost.

THIN FILM RESISTOR NETWORKS
Modern, low cost hybrid D/A converter designs are based
on two premises: a standard circuit design with relatively
few circuit components, and high volume production. The
quad current switches significantly reduce the number of
active circuit components required. In a similar manner
thin-film resistor networks greatly reduce the number of
passive circuit elements. The thin-film resistors are also an

FIGURE 5. Blank Silicon Wafer and Finished Resistor N~

113

The substrate is made Of alumina (AIO,) and is itself a thin
film component which is photolithographically defined and
then electro-chemically plated with gold. Datel Systems uses
thin film substrates in its hybrid products while some other
companies use thick film. The main advantage of the thin
film substrates is in the fine line widths which can be
attained, resulting in more complex circuits. Figure 6 shows
a magnified substrate mask for a 12-bit D/A converter;
this conductor pattern has line widths down to 4 mils.

PULSED
-XENON
LASER BEAM

Fllll1l!ll1lll!l1ll1ltt:.::Jlizm!l1l 1l",Sim'O",'"'I"..J.",·m7·ooo.l~imm!l1l1.!~'_"aoA
5;02

1=12,--f-~ OUTPUT
Vo>Vz

I

[vo," (1

+

~~) Vz J

The comparison process is continued one bit at a time from

1..- __ .J

the MSB down to the LSB (least significant bit). After the
last clock period, theoutputofthe successive approximation
register contains the digital word representing the analog

R,

input. The converter also puts out an end of conversion,

or status, pulse indicating that conversion is complete. In
addition to the parallel data output on n digital lines, there is

FIGURE 10. Temperature Compensated Reference Circuit

also a useful serial output from most converters derived

from the comparison process.

Datel Systems' DAC-HZ12BMR-1 uses such a low tempco,
compensated, buried zener reference to achieve a low 10
ppm/oC gain stability over a -25°C to +B5°C operating
temperature range.

The successive aproximation

AID

converter with up to 12

bits resolution is made possible in hybrid form by three
recent developments:
1. availability of low cost monolithic Quad current switches in chip form

Another reference circuit now used in many devices, par-

ticularly monolithic data converters, IS the "bandgap reference." This circuit is based on the predictable base emitter
voltage change of a transistor with temperature. By using
two matched transistors operating at different current densities, a stable reference voltage numerically equal to the
extrapolated bandgap voltage of silicon at 0° K is achieved.
This voltage is 1.205V, but in some reference circuits it is
multiplied up to about 2.5V. The bandgap reference in general has not achieved the stability of the new buried Zener
references, however.

2. availability of low cost monolithic successive approximation registers in chip form

3. availability of fast laser trimming systems for trimming
thin film resistors
The first two developments drastically reduced the number
of individual monolithic chips necessary to fabricate a com-

plete hybrid AID converter. The third development made
rapid and inexpensive trimming of the complete converter

possible.

115

The development of the monolithic SAR (successive approx-

Datel Systems' models ADC-HX12B, ADC-HZ12B, ADCHS12B, and ADC-HF12B are all high performance hybrid
12 bit AID converters which use the successive approximation conversion technique. Conver.sion times vary with these
devices from 20 ~sec. down to only 2 ~sec.

imation register) was particularly significant since it elimi-

nated a large number of digital chips. The SAR is really a
special purpose digital register that contains all the storage
and control logic to perform the successive approximation
operation. In hybrid data converters the low parts count is
extremely important for several reasons. First it rilduces
parts cost and labor, thus allowing the device to be produced economically in large quantities. Secondly it results
in high reliability by reducing the number of total interconnections in the device. Compared to a modular converter, for example, the hybrid has less than half the total
number of connections. A module, in addition to the bonds
in each circuit component, has at least the same number
of soldered connections.

FAST AND ULTRA-FAST HYBRID
DATA CONVERTERS
A typical hybrid 12 bit AID converter, for example the low
cost ADC-HX12B, has a conversion time in the area of 20
to 25 psec. There are some limitations in trying to achieve
shorter conversion times with the circuitry just described.
The limitations are in the comparator sWitching time and in
the output settling time of the quad current switches. For
accurate conversion to 12 bits, each bit output current must
settle to within 0.01% of full scale before the next.comparison takes place.

An important advantage in the new hybrid AID converters,
in addition to low cost and small size, are the "universal operating features." Some of the operating features which result
in application flexibility are:
1. Pin programmable input voltage ranges of 0 to + 5V,
o to + lUV, ± 2.5V, ± 5V, and ± lOV.
2. Buffered (100 megohm) or unbuffered input.
3. Parallel and serial output data.
4. Short cycled operation (for less resolution at higher
speed) by external pin connection.
5. Voltage reference and clock circuit outputs.

One of the factors that inhibits the comparator switching
time and the D/A converter output settling time is the stray
capacitance from the th~n film resistors to the substrate
conductor. Since'the resistors are fabricated on a silicon
wafer, this capacitance is significant because of the rather
high (12) dielectric constant of silicon. Thetotal straycapacitance seen at the QCS emitters and collectors, and also
at the comparator input, Significantly increases the time

required for settling and switching.
One way to achieve higher conversion speed is to reduce
this unwanted capacitance by fabricating the resistor network on glass instead of silicon. Glass has a dielectric constant of 4, much less than that of silicon. A nichrome thin
film resistor on glass is shown in Figure 13. This nichromeoR-glass resistor network is used in Datel Systems' ADCHZ12B 12 bit hybrid AID converter to achieve a 12 bit
conversion in 8 p,sec. maximum.

BUFFER

8UFF~: :~_ _ _ _ _ _ _...J
OUT

~NGE O---~V~~~~A-~~~
~~NGE 0 - - - - - - '
COMPARATOR

IN

.BIPOLAR

o---------"----{

6.4K

OFFSET

~~

0--------'

FIGURE 12. Hybrid AID Converter Input Circu~

Some of .these features are illustrated in the input circuit
diagram of Figure 12. The comparator input has a tapped
resistor which can be connected for input resistance values
of 2.5K, 5K, or 10K, giving three different voltage ranges.
If the bipolar offset pin is connected to the comparator summing junction, then the input is offset by one half scale
to give bipolar operation with each of the previous voltage
.ranges. If high input impedance is required, the auxiliary
buffer amplifier can be connected ahead of the input resistors. It should be noted, however, that the settling time
of the amplifier must then be added to the conversion time
of the AID converter. The buffer output must have settled
to within ±y, LSB (0.012% for 12 bits) of final value before
the AID conversion cycle can be initiated.

FIGURE 13. Nichrome Thin Film Resistor on Glass

For faster 12 bit conversions another circuit technique must
be used. There are basic limitations in the switching speed

of quad current switches which cannot be further reduced.
A faster technique is to use individual PNP switched current
sources as shown in Figure 14. Here all the current sources
are Of equal value and drive a low impedance R-2R ladder
network; the impedance at every junction in the ladder is
identical. The key to very fast settling time is to use higher
currents driving low impedances. In addition, since each
current source is switched by a single diode connected to
the emitter, the switching delays are very small.

Another way to use the buffer amplifier, if it is not used in
the input circuit, is to buffer the reference output for use
with external circuitry. In this way the reference can drive
up to ±5 rnA externally without affecting the temperature
coefficient of the zener reference. External circuitry can,
therefore, be made to track with the AID converter over
time and temperature.

The result of the circuit of Figure 14, when used as a

116

DATA ACQUISITION & CONVERSION HANDBOOK

form an input quantizer with trip paints set one LSB apart
by the resistor biasing network and reference. For a given
analog voltage applied to the input of the converter, all
comparators biased below the input voltage will turn on
and all biased above the input voltage will remain off. The
logic output from the comparators is not very useful since
it is a 2" -1 line "thermometer" type scale as shown in Table
1 for a 3 bit parallel converter with an overrange bit. Therefore, a fast decoder circuit is used to convert this logic
output into binary code.

D/A converter. is a current output settling time of less than
50 nsec. for 12 bit resolution. This circuit is used in Datel
Systems' ultra-fast D/A converters, the DAC-HF series. As
,

81TIN

The advantage of the parallel type AID converter is that the
complete conversion takes place in just two steps: the comparators switch state and the decoder switches state. With
new high speed logic circuits this can be done in typically
15 nsec. The limitation is in the resolution that can be
achieved with a reasonable number of comparators. The
practical limit is a 4'bit converter which requires 2"-1, or
15 comparators. The number of comparators is limited by
physical placement, power consumption, and the total bias
current which cumulatively flows through the resistor biasing network.

FIGURE 14. Ultra-Fast Current Output DIA Converter

with the other circuits, here the R-2R ladder network is also
laser trimmed for optimum linearity. For ultra-fast 12 bit
AID conversion this DI A converter circuit can be used with
a fast comparator and monolithic SAR to achieve a 2 ~sec.
conversion time (Datel model ADC-HFI2B).
Although in lower resolution AID converters such as 8 bit
units it is possible to achieve sub-microsecond conversion
times, for the ultimate in conversion speed it is necessary to
employ a technique other than successive approximation.
This other technique is known as the parallel, or flash,
method and is illustrated in Figure 15.
12345678
OUTPUT DATA

FIGURE 16. Eight-Bit, .Two Step Parallef AID Converter

,

.

2 ~~t,!0~
3 DATA

To achieve 8 bit resolution, two 4 bit converters are used in a

two-step approach shown in Figure 16. The first 4 bits are
converted and the digital output goes to an ultra-fast 4
bit DI A converter which converts the result back to analog.
The resultant analog voltage is then subtracted from the
input voltage and this difference is converted into digital
form by a second 4 bit parallel converter. The complete
8 bit digital word is held in an output register. Since the
two steps occur at different times, the next first step can be
performed while the result of the previous first step is held
in the register and the second step is being done. This
overlap mode of operation gives a 1aster conversion rate
than would otherwise be possible.

DECODER

FIGURE 15. Para".' (Fla.h) Type AID Converter

The parallel technique basically eliminates the n clock steps
required for a complete converSion by the successive approximation conyerter. A bank of 2" -1 analog comparators
8 LINE OUTPUT

J......L-L...L-Ll...L.l..

o
o
o

1 1 1 1 1 1 1
0 1 1 1 1 1 1
0 0 1 1 1 1 1
o 0 0 0 1 1 1 1
00000111
00000011
00000001
o 0 0 0 0 0 0 0

The advantage of this two stage conversion is that just 30
comparators are required by the two 4 bit parallel converters as compared with 255 if a single stage 8 bit converter were used. The disadvantage is that some speed is
sacrificed in the process; nevertheiess, speeds as high as
20 MHz are achieved for an 8 bit conversion.

BINARY OUTPUT
1

0

0

0

o

1
1
1
0
0
0
0

1
0
0
1
1
0
0

0
1
0
1
0
1
0

011'1'-

o
o
o
o
o
o

OVER RANGE

Datel Systems' HU series devices are hybrid building blocks
for ultra-fast parallel type AID converters. This is a new and
very useful approach to ultra-high speed conversion since
building block series may be connected in different ways to
achieve a desired purpose. The ADC-HU3B is a 3-bit parallel AID converter which is expandable. Two of these connected together make a 4-bit AID and four connected to-

TABLE I Digital Outputs for 3 Bit Para"el Converter

117

get her make a 5-bit AID. Used as a single stage, they have
a 50 MHz conversion rate.

Figure 17 illustrates two basic monolithic techniques used
in data conversion circuits. The first device (Figure 16a)
is a standard diffused planar NPN transistor which is the key
component in monolithic bipolar circuit design. It is fabricated in the following basic steps, starting with a P type
silicon wafer:
1. Photolithographic definition and diffusion of N+ buried
layer. This is required to create a low collector resistance.
2. Growth of N type silicon epitaxial layer.
3. Isolation masking and diffusion (P+ type).
4. Photolithographic definition and diffusion of base region (P type).
5. Photolithographic definition and diffusion of emitter
region (N+ typ~).
6. Photolithographic definition and evaporation of metallization layer (Aluminum).
7. Testing, dicing, and sorting of devices.

For a two stage converter, the DAC-HU4B is an ultra-fast
4 bit D/A converter which operates directly from a 15 line
input from a 4 bit AID. Another device in this series is the
SHM-HU, which is an ultra-fast sample hold for use with the
ADC-HU3B.

MONOLITHIC CIRCUIT FABRICATION
Monolithic techniques have made outstanding progress in
the past few years. Monolithic technology, rather than relying on a variety of different components, must rely on devices that can be readily made monolithically. The circuit
design rules, therefore, have been to minimize resistors.
capacitors, etc. and rely on transistors, making use of the
inherent advantages of close matching, excellent thermal
coupling, and the economy of using large numbers of active
devices with various device geometries. The engineering
Ingenuity used in maximizing the use of "active components
has rp.!=i.I.Jlted in monolithic circuits 'Nhich schematically look
quite different from their discrete equivalents. For example,
the monolithic design for an operational amplifier is quite
different from a discrete-design op amp.

The second device is a CMOS transistor pair. These devices are formed by successive diffusions in the same manner as the NPN transistor described above. The basic differences are that the initial wafer is N type silicon and the
devices themselves are unipolar transistors. One device is
a P-channel MOS transistor and the other is an N-channel
MOS transistor. The insulation underneath each of the two
metalized gates IS a stable field-oxide layer.

Monolithic circuits which are available at the present time
use one or more of the following technologies: bipolar,
CMOS, ion implantation, TTL, I'L, and thin film deposition.
Recent progress has permitted the combination of two or
more of these technologies in a single circuit, for example,
bipolar and CMOS, bipolar and ion Implanted FErs, and
bipolar and I'L. The difficulty in making monolithic data
conversion circuits has been in combining linear circuitry
with digital circuitry and including precision, stable resistors.

An important element in monolithic data converters is the
resistor. Stable resistor networks are the basis for accurate and stable data conversion. For lower resolution converters, namely up to 8 bits, diffused resistors are commonly used. The diffused resistor is the most economical type to
use since it requires no additional processing steps beyond
those already required for a monolithic circuit. A typical
diffused resistor is shown in Figure 18; it is formed by the
bulk resistance of a P-type base diffusion. The value of this
resistor is determined by the sheet reSistivity of the diffusion and the length and width of the resistor:
R = Rs L/W
where Rs is the sheet resistivity.

Monolithic techniques achieved notable and rapid success
with operational amplifiers, but with data conversion circuits the progress has been slower due to the above mentioned problems. Therefore, the first monolithic converters
were simple 8 bit D/A converters without a reference or
output amplifier. Recent progress, however, has permitted
10 and 12 bit D/A converters to be fabricated. AID converters made with monolithic technology have been largely
restricted to dual slope and charge balancing types, but
some successive approximation devices are now becoming
available. At the present time most monolithic data converters require a number of external parts, for example
references, op amps, comparators, clock circuits, capacitors,
and resistors. In spite of these limitations, monolithic circuits generally offer the lowest cost solution to a data conversion problem, and many of the earlier limitations are now
being overcome.

ISOlAllOH

DIFFUSION

S,QzPASSIVATION

,.

MET ALllZA TION

ISOLAnON

:j~~~~~_~~~~~~~S.02PASSIVATION

p. ISOLATION
OIFFUSION

NTVPE
EPITAXIAL LAVER

N. BURIED
LAYER

PTYPe
SUBSTRATE

DIFFUSION

FIGURE 18, DetaIl of Diffused Resi$tor
The temperature coefficient of these resistors is large, apprOXimately 1500 ppm/oC from OOC to 125°C. Fortunately
converter performance depends more critically upon the
matching and temperature tracking of resistors than on the
absolute temperature coefficient. The matching of diffused
resistors to 0.5% or 'better and temperature tracking to
100 ppm/oC or better can be achieved in monolithic circuits.

SOURCEl

b

CMOS

MeTAlliZATION

PCHANNEl-,-,--==--,--=:.J

FIGURE 17. Bipolar and CMOS Monolithic Devices

118

DATA ACQUISITION & CONVERSION HANDBOOK

The limit on using diffused resistors is generally B bits, although 10 bit resolution has been achieved by use of resistors with laser trimmed aluminum links. Diffused resistors, however, are no match for thin film resistors which
can give less than 30 ppm/oC absolute tempco and 1 to
2 ppm/oC tracking tempco. Therefore, most 10 bit and higher resolution monolithic converters have the additional
operations of depositing, photolithographic etching, and
laser trimming of a thin film resistor network on part of
the monOlithic chip.

2.

'----t--'----:--"-+--+-----<> OUT 1

."

BIT 1
INPUTS

MONOLITHIC CONVERTER DESIGNS
A common design used in 8 bit monolithic D/A converters
is shown in Figure 19. A series of collector switched NPN
current sources is used with a diffused R-2R ladder network. The ladder network is connected to the emitters as

FIGURE 20. A CMOS Multiplying D/A Converter

depends on the tracking tempco rather than the absolute
resistor tempeo.

shown, in order to minimize the total number of resistors;

A detailed circuit of the CMOS switch is shown in Figure 21.
It is composed of two N channel MOSFET's which are driven
out of phase with each other so that one switch is on while
the other is off. The switches are driven by two CMOS
inverters as shown.

in this way only two resistors per bit are required and they
have just two different values, Rand 2R. Matching and
tracking of the resistors is thereby simplified.

FIGURE 19. Bipolar D/A Converter with Diffused Resistor

Network

DUT2

Vs

OUT 1

FIGURE 21. Single Pole, Double Throw CMOS Switch

A reference amplifier and reference control resistor are used
to bias the current sources from an external reference

This technique is used to make both monolithic and hybrid
multiplying D/A converters. The advantage of a 2 or 3 chip
hybrid design is that higher accuracy can be attained,
with resolutions up to 14 bits. Such devices are Datel
Systems' DAC-HA series, composed of 10, 12 and 14 bit
multiplying D/A converters.

voltage. Some circuits steer the collector outputs to two

separate output lines which are analog logic complements
of one another and are useful in a number of ways, including
driving an output amplifier in push-pull.
The circuit of Figure 19 is used in Datel Systems' DAC-OBB
B bit D/A converters; these have 85 nsec. output settling
time and high voltage compliance outputs (-10to +1BV).ln
another Datel Systems model, the DAC-ICBB, the complemented collector output is not brought out but is internally
tied to the positive supply voltage. Resolution is B bits, and
output current settling time is typically 300 nsec. An extension of this device to 10 bits resolution is model DAC-IC1QBC which uses identical circuitry but Uses laser link resistor trimming of the higher order bits.
.

Monolithic AID converters have been much more difficult
to make than D/A converters, especially for resolutions
higher than B bits. This has been particularly true for
successive approximation type AID converters where two
semiconductor technologies must be combined with thin
film resistor technology. The combination that looks particularly promiSing in the near future is the combination of
bipolar linear circuitry with I'L digital circuitry and the use
of nichrome thin-film resistors on the same chip.

Another.popular D/A conversion method uses CMOS circuitry with a precision R-2R thin-film ladder network. This
circuit, illustrated in Figure 20, is particularly well suited to
multiplying applications where a variable reference voltage
is used. The key to multiplying operation with high precision is the low resistance CMOS switches which are in
series with high resistance 2R resistors. A feedback resistor
is also provided for use with an external operational amplifier. This resistor is also provided for use with an external
operational amplifier. This resistor has an identical tempco
with the ladder resistors since they are fabricated in the
same network and, therefore, the output voltage tempco

Given the greater difficulty of making a high resolution
successive approximation AID converter in monolithic form,
it is not surprising that another technique was used first.
This technique is the dual slope method, which has been
popular for many years in discrete component form. It is
illustrated in Figure 22 and operates on an indirect conversion prinCiple whereby the unknown input voltage is
converted into a time period which is then measured by
a counter.
The conversion cycle begins by switching the operational integrator to the input voltage, which is then integrated for a

119

v~
/

~IXEO LEASUR~D
COUNT

A state of equilibrium exists when the average current
developed by the pulses just equals the input current.
Since each current pulse is a fixed amount of charge, the
name "charge-balancing" is appropriate.

TIME

COUNT

If a counter is used to count the output pulses from this
circuit for a fixed period of time, the circuit is then a complete AID converter. This technique, implemented by bipolar
and CMOS circuitry, is used in Datel Systems' ADC-EK
series AID converters which consist of 8, 10, and 12 bit
binary devices and a 3)1, digit BCD unit. If a counter is not
used with the circuit then the device· is the well known V/F
(voltage to frequency) converter. Model VFQ-1 is a low cost
monolithic V/F converter which also uses bipolar and CMOS
circuitry on the same chip.

OUTPUT DATA

FIGURE 22. Monolithic Dual Slope AID Converter

OTHER DATA ACQUISITION CIRCUITS
The devices described so far have been ND and D/A con-

fixed time period. After this time, the integrator is switched
to a reference voltage of opposite polarity and the integratui output integrates bdGk to L.tHU lur a period of iime which
is measured by the counter. The resultant count is then the
digital value of the input voltage. The important thing about
the dual slope technique is that the accuracy and stability
are dependent only on the reference, and not on other components in the circuit. This assumes, of course, that the operational integrator is linear. The technique is both simple
and effective and is readily implemented with CMOS circuitry. Some devices also incorporate automatic zeroing
circuitry to reduce the effect of offset drift with time and
temperature.

verters. In addition to these, there are a number of other
circuits which are commonly used in data acquisition applications. These circuits include sample-holds, analog multiplexers, operational and instrumentation amplifiers, and
filters. All of these devices are also available in either monolithic or hybrid form; many of these products are described
in the pages of this brochure.
Frequently, these various devices are combined together
to make a complete "data acquisition system." Such a system
has an input analog multiplexer, an instrumentation amplifier (sometimes), a sample-hold, an ND converter, and the
required control logic circuitry. These systems take care of
the entire signal processing function from multiple analog
inputs to the digital output which connects to a computer
datil"bus line.

The advantages of dual slope conversion are simplicity,
accuracy, and noise immunity due to integration of the input
signal. The chief drawback is relatively slow conversion time.
Dual slope AID converters are most commonly used in digital panel meters, digital multimeters, and other digital measuring instruments.

Such a system is also now available in a single hybrid
package. This device is Datel Systems' model HDAS-16 and
a companion device, model HDAS-8. The HDAS-16 provides
16 channels of analog multiplexing, an instrumentation
amplifier with programmable gain from 1 to 1000, a samplehold, a 12 bit ND converter, three state output bus drivers,
and all the required control logic. The HDAS-8 is identical
except that it contains an 8 channel differential multiplexer. This complex hybrid circuit is fabricated on two
interconnected substrates and is shown in the photograph
of Figure 24.

Another integrating conversion technique which has gained
in popularity recently is thecharge-balancingNDconverter.
As illustrated in Figure 23, an operational integrator is
enclosed in a digital feedback loop consisting of a comparator, pulse timer circuit, and a switched reference. A positive
input voltage causes the integrator output voltage to cross
zero volts, which is detected by the comparator and triggers
the pulse timer circuit. The output pulse from the timer
switches a negative reference current to the integrator
input, and this current pulse is then integrated, causing the
integratoroutputto increase in the positive direction. Therefore, every time the integrator output crosses zero another
pulse is generated and integrated.

GZ

'"
RIIEF
-VAEf

1-------------

o--""'v--oC

FIGURE 24. Photocraph 01 Hybrid 12 Bit, 16 Channel
Data Acquisition System

OUTPUT DATA

FIGURE 23. Charge ealaneing AID Converter

120

DATA ACQUISITION & CONVERSION HANDBOOK

an industry standard
Hybrid 12-Bit
AID Converters
Analog to digital converters interface analog signals to digital computers and other digital control circuits_ In the world
of data converters the moderate speed, low cost 12-bit AID
converter is a real workhorse, serving in a broad range of applications from data acquisition systems and pulse code
telemetry systems to computer-based process control systems, automatic test systems and other sampled-data systems_
System designers often require that an AID converter provide 12-bit conversion with conversion times between 8 and
SO microseconds_ Along with these basic specifications go a
few other accepted parameters such as ±l:>least significant

bit linearity and temperature coefficient between about 20
and 40 parts per million per degree Celsius. Twelve-bit resolution yields what most designers consider precision measurement: relative accuracy of 0.012% with 0.012% linearity.
The 0.012% accuracy figure, equal to ±l:> bit accuracy,
results from quantization uncertainty. Other factors such as
nonlinearity, gain and offset temperature coefficients and
long term drift degrade the 0.012% ideal accuracy figure.
Also, the overall error budget for the complete analog portion of the external circuit may include an amplifier, analog
multiplexer or sample-hold. Hence the use of a 12-bit AID

+15V

-15V

Ref

Power

Povo.er
31

Out
18

28

+5V
Power

16

6.3K

~--------i 27 Gain
Adj.

~~~~~t

29

f-----4~------.J

23

1--------------'

~;rar

22

f------.---.----------i

:~:"t

24

f------o

15 DigCom.

12 Bit DAC

14 Short
Cycle
Successive

~~:"t

Approximation
Register

25

f--------'

Analog 26

Com.

Block Diagram

elK
Rate

19 21
12 11 10
elK Start
LSB
Out Conn.

8 7
Bit No.

4

Parallel Data Out

3

1 T
MSB

32
Serial
Data

Out

Fig 1 Block diagram shows the internal structure of a typical 12·bit hybrid analoltto-digital converte,. Pin connection••hown .,. in • standard
configuration.

121

converter commonly results in an overall system accuracy
of 0.1%.
The development of monolithic and hybrid Ie technology produced dramatic changes in data conversion device
technology. In the past, 12·bit AID converters of the suc·
cessive approximation type came in a standard 2"x4"x0.4"
encapsulated modular package. Manufactured by a number
of companies and costing between $120 and $200 each,
these units still enjoy wide use.
The first moderate cost, hybrid 12·bit AID converters,
introduced in 1974, were followed by a number of devices
made by different manufacturers, all housed in a -standard
32'pin package with two basic pin configurations. Such
standardization has been rare in the industry. Three factors
weigh heavily in making these devices popular industry
standards: low price (many cost less than $100), small size
(about 1.1 "xI.7"xO.2") and universal operating features
L'1at allow ta'iem to serve in a wide vailtty uf appliciiliuHs.
These converters are quite a contrast with earlier units
of eqUivalent performance; such units sold for $5000 in
1959 and $600 in 1968 and were considerably larger. Hy·
brid data converters in themselves are not really new de·
vices since they first appeared on the market in the late
1960s, but until recently they were not produced as stan·
dard products in large volume. Early hybrid converters
served in military and aerospace application where small
size and high reliability were overriding considerations,
and low price was not. The circuitry at that time, much more
complex than today's circuitry, gave very high chip counts
and relatively low production yields.

ii> t::JATEL
uN-ll i' 1 \ ,
\\1 \2Ht '

A!1
f\{H

'frrrrl",)1

i ' rf

Fig 2 Thil AID converter, manufactured by Datel Systems, employs
thin·film hybrid technology to provide 12-bit conversion.

TABLE I
HYBRID 12 BIT AID CONVERTER
SPECIFICATION SUMMARY
Resolution
Nonlinearity

12 Bits
± 1/2 LSB (0.012%)

Gain Tempco

±2OppmrC max.

Analog Input Ranges

Oto +5V, Oto +10V

Coding, unipolar

±2.SV. ±5V•• 10V
Compo Binary

Coding, bipolar

Comp. Offset Binary
20 "sec. max.
±15VDC & +5VDC

Conversion Time
Power Supply

'Out
Current Dividers

I

Digital
Control

9101112

aCS2

aCS3

-,
I
I

I

I

_______________ 1I
~-------------------

Fig 3 Quad current switches play an important rol. in the operation of the converter. In this circuit diagram, teh QCSs and the current divider
resistors form a network providing proper current source binary weighting.

122

DATA ACQUISITION & CONVERSION HANDBOOK

register until initiation of the next conversion cycle. The
conversion is thus completed in 12 clock periods.

Note: Clock is sped up bV connecting
clock rate adjust pin to ±SV.

Construction and Technology
Short
Cvcle
SAR

14

Output Data

Fig 4 External pin connections allow faster AID conversion with
lower resolution. The connection shown gives lO-bit conversion.
Connecting the short cvcle to ground gives full resolution (12·bit)
conversion.

Design and Operation
Several recent developments have allowed a significant reo
duction in number of chips required to implement a suc·
cessive approximation register, and these technological ad·
vances have brought on the low cost hybrid converter. These
developments include: the availability oflow cost, quad
current switches used to implement the converter portion
of the circuit; the development of the monolithic successive
approximation register; and the rapid laser trimming systems
for actively trimming thin·film resistor networks.
The resulting low component count makes high yield
production of a standard converter design a reality; since
parts count and labor are reduced, production costs drop.
In addition, reducing the parts count also reduces the num·
ber of wire bonds, thereby increasing reliability.
Fig I shows the block diagram of a complete 12'bit hy·
brid device and Fig 2 shows one such device. The circuit
basically consists of a 12·bit D/A converter inside an ana·
log/digital feedback loop. The successive approximation reg·
ister (SAR) controls the converter and in turn takes inputs
from the clock circuit and analog comparator. A precision
low drift voltage reference circuit stabilizes the converter.
Operation of the A/D converter is straightforward. The
analog input voltage connects to one of the input resistors
(either directly or through the buffer amplifier at, for ex·
ample, pin 25). The analog comparator compares the current flowing through the input resistor with the D/ A converter's output current. A start pulse to the SAR initiates
the conversion cycle, turning on the first bit (most significant bit) of the converter. This current is compared with the
input current. If the MSB current is less than the input current, the MSB current is left on and in the next clock period
the second bit is turned on. If the MSB current is greater
than the input, it is turned off, and the second bit turned
on in the next clock period.
This comparison sequence continues through all twelve
bits until the cumulative total of all bit currents left on has
been compared with the input current. The digital output
of the SAR (which is also the input to the D/A converter)
is then the digital output word equivalent to the analog input voltage. This output word is held in the SAR's output

The quad current switches (QCS) play an important role in
the implementation of the converter (see Fig 3). Three QCSs
connect to give 12 weighted currents that are summed together at the output of the circuit. The first QCS with its
four weighted current sources and reference current source
is shown in detail in Fig 3. The other two QCSs are identical
except that their reference current sources are not used.
The voltage reference circuit se.ts up a constant current
in the reference transistor which is controlled by amplifier
A" By means of the reference current source, all 12 current
sources are biased by maintaining a constant voltage from
the transistor bases at the negative voltage rail. The biasing
is independent of supply voltage variations. The voltage
reference circuit consists of a low tempco compensated zener
reference and an op amp circuit that maintains constant current through the zener reference.
Weighting the emitter resistors R, 2R, 4R and 8R weights
the currents in the NPN transistor current sources in binary
ratios of 8, 4, 2 and I. In order that the currents track each
other closely over a wide temperature range, the NPN transistors are diffused with emitter areas in binary ratios of 1,2,
4 and 8, giving the same current density in each transistor.
This identical current characteristic gives closely matched
base-to-emitter voltage drops that track each other with
temperature.
To get exact binary weighting of the current sources out
to 12 bits, QCS2 and QCS3 both operate into precision current dividers that divide the QCS current outputs by factors
of 16 and 256 respectively (compared with QCS I).
Thin-film technology. To ensure the stability of the A/D
converter, the emitter, reference and current divider resistors
are all fabricated in a single thin-film resistor network and
then laser trimmed to the required accuracy. The resulting
resistors have absolute temperature coefficients between zero
and thirty parts per million/"C. Trimming the resistors while

30
16
Channel

MUX

Z,N---+

'" 10'n

29+-......1..----'

17

Fig 5 This circuit mUltiplexes stowly changing signals without sample-hold. A throughput rate of 77 KHz can be achieved with ± 1
least significant bit accuracy_ This circuit multiplexes up to 16 channels. The converter's buffer amp provides it with a high-Z load.

123

L

Ref

Out

rl------------------B-u-ff-e-'----------~-----------------,

30

Amp.

Buffer
In
Buffer

+r6._4_V____________~O~u~t___

6.3K

29+_--~~----------~
23~--------------------~

I nstrum.

22

I

f-------,.------,----------------i

'"
Bridge
Transducer

17

[IIll

~

Fig 6 This circuit will provide accurate and stable measurements for computer uSlge. Because AID converte,'s internal buffer amplifier i, not
used, the amplifier can drive the transducer bridge from the converte", ref.rence.

the converter is powered and running allows you to achieve
a linearity specification of ±!6 least significant bit.

Universal Operating Features
Certain features appear in hybrid D/A converters that make
them industry standards. These features became an important 'design goal after their appearance in some of the modular converters on the market a few years ago.
Pin-programmable input ranges. Hybrid A/D converters provide six usable input ranges: 0 to +5V. 0 to + I OV. 0 to
+20V, ±2.SV, ±SV and ±IOV. You can obtain the first three
of these ranges by various connections of the two SKU input
resistors: in addition. if pin ~2 is connected to pin 23, an offset current derived from the internal reference is applied to
the comparator input, offsetting the converter's range by
exactly half-scale to give bipolar (positive/negative input)
operation.

Internal buffer amplifier. This operational amplifier is connected as a unity gain follower and has an input impedance
of typically 10· to 109 U. Externally pin-connecting the
amplifier ahead of the input resistors increases the converter's
input impedance from the normal range (2.5KU to 10KU
depending on how the range-setting resistors are connected)
to over 10" U.
This high input impedance does not come without strings
attached - the 0 to +20V input range cannot be used since
the amplifier's maximum input and output voltage ranges

are ±IOV. Also, the conversion time of the AID converter
is increased by the settling time of the buffer amplifier. A
little thought about the operation of the successive approximation converter reveals that the output of the buffer ampli-

124

fier must have settled to within ±~ least significant bit of
final value before the A/D conversion cycle can be initiated.
In some applications the settling time may not alter the conversion rate since the input amplifier can be settling to a
new value during the time that the output of the AID converter is being transferred out.

Short cycling capability. You can terminate the conversion
cycle at less than 12 bits via external pin connection, resulting in a faster conversion time with less resolution. Speeding
up the conversion time is also helped by speeding up the
clock rate through an external connection. This method worle
because lower resolution requires less settling time at the
output of the D/A converter.
Fig 4 shows how to effect short cycling. The short cycle
terminal (pin 14) of the SAR is externally connected to the
N+ I output bit for an N-bit conversion. The figure shows
the connection for a IO-bit conversion. For a full resolution
12-bit conversion the short cycle pin is connected to the +5
volt logic supply.
To speed up the clock rate, connect the clock rate input
(pin 17) to an adjustable positive voltage. This voltage should
be +SV for lO-bit conversion and + ISV for 8-bit conversion.
These changes result in reductions in conversion time of
25% for IO bits and 50% for 8 bits (compared to 12-bit conversion time).
Choice of output codes. You can choose complementary
binary. complementary offset binary or complementary
two's complement. Use of unipolar operation requires the
first code; for bipolar operation, you can select either
complementary offset binary or complementary two's complement codes by using either the most significant bit out-

DATA ACQUISITION & CONVERSION HANDBOOK

put or the complemented most significant bit output from
the converter.
Precision reference voltage output (pin 18). This output permits referencing external circuitry to the internal voltage
reference in order to give identical tracking of the AID converter and external circuits with both time and temperature.
This results in stable raliometric operation of the measurement, but the reference output must be buffered by a high
impedance amplifier and hence cannot drive other circuits
directly. 10 microamps can be drawn from the reference
itself. One way you can buffer the reference uses the internal
buffer amplifier, if your application does not require the
amplifier at the AID converter input.
Clocked serial output (pin 32). This serial output occurs during the conversion cycle and is synchronized with the clock
(pin 19). The serial output format is most significant bit
first, nonteturn to zero with either complementary binary
or complementary offset binary coding. The serial output
can aid in digital data transmission over long distances and
in pulse code telemetry. Together with the clock output, the
serial output can help align the converters since the codes
are readily observed on an oscilloscope.

Applications
Fig 5 shows an application that requires multiplexing of
slowly changing signals without sample-hold. The circuit
shown will multiplex up to 16 channels. Since the multiplexer may have a channel resistance between 250n and 2Kn,
the multiplexer must see a very high impedance at its output. The converter's buffer amplifier can provide this high
impedance load.
If you use a hybrid AID converter with an 8 microsecond conversion time and allow multiplexer buffer amplifier

settling time of 5 microseconds, you can realize a throughput as high as 77 KHz. The system will be accurate to ±I
least significant bit for up to 5 Hz input signal frequency.
Fig 6 shows a typical measurement application where
the measured value must be fed to a digital computer. The
differential output of a transducer bridge is amplified by
the instrumentation amplifier before being fed to the AID
converter input. Since the instrumentation amplifier buffers
the bridge output with its high input impedance, you don't
need the internal amplifier for input buffering. The amplifier can then drive the transducer bridge from the converter's
internal reference. The buffer amplifier typically draws 125
nA bias current from the reference and provides up to 5 mA
output current to the bridge.
This circuit arrangement achieves the most stable measurement results over time and temperature. In the circuit,
as the internal reference changes, the magnitude of the input signal changes. The converter operates ratiometrically,
providing error cancellation for reference changes.
Figure 7 shows the circuit conneclion for a sampling 10bit AID converter. A l2-bit hybrid AID with 8 !-,sec conversion time is short cycled to 10-bit operation. This is done by
connecting the short cycle terminal, pin 14, to pin 2, the bit
II output. Pins 3 through 12 then serve as data outputs with
complementary offset binary coding. The input to the AID
converter is connected for ±5V bipolar operation.
Ahead of pin 24 is a sample-hold circuit (which is a monolithic device) that samples the analog input and provides high
impedance buffering. This sample-hold requires a 1000 pF
holding capacitor, and with this value acquires a 10 volt input change in 4 !-,sec. The sample control pulse is therefore
set to 4 !-,sec width.
After the sample control pulse returns to zero, putting

23
[

[

1~~;
'""'"'
1::r-:;---t-c~~

Short
Cycle

14

0--2
Analog
In

1IpF
14

Sampl.

Control

-8

11

-L

100

~
-=
•

25

26

Figure 7 shows the circuit connection for a sampling 10 bit AID converter. A 12 bit hybrid AID with 8 jJS8C conversion time is short cycled to
10 bit operation. This is done by connecting the short cycl. terminal, pin 14. to pin 2. the bit 11 output. Pins 3 through 12 then serve as data
outputs with complementary offset binary coding. The input to the AID converter is connected for ±5V bipolar operation.

125

GLOSSARY
OF TERMS
Trigger ------+
Absolute Accuracy: The output error, as a percent of full
scale, referenced to the NBS standard volt.

r - 1 - - +15V

Charge Balancing AID Converter: A type of AID Converter
that uses a closed loop integrator with a switched current at
its input to exactly balance the current produced by the input signal.

Analog

Conversion Time: The lime from when a conversion is initiated until the output digital data. representing the analog
input value, is ready.

~~------~~--r--o

Differential Unearity: The maximum deviation of the analog transition between any two adjacent codes in an AID
converter from the ideal value. This quantity is generally
expressed as a fraction of a least significant bit.

O-+=-......'M.-+..~ 100K

In
10to +10VI

Gain
Adj.

Dual Slope AID Converter: A type of AID converter that
operates by the indirect method of converting a voltage input to a time period, using an integrator, and then measuring the time period by a clock and counter.

o-t-,r:-------<~-+-

I----------t=--.:!~

Error Budget: A detailed list of all sources of error in a sys-

tem or

d~:::1!it

to detenrJne

Unearity (or Integral Unearity): The maximum deviation
of the AID converter's transfer function from an ideal
straight line between its end points. It is generally given in
percent of full scale or fraction of a least significant bit.
Missing Code: The phenomenon of skipping one or more of
the sequence of output codes over the total analog input
range.
Offset Error: The amount by which the AID converter
transfer function fails to pass through the origin. generally
given in millivolts or percent of full scale.
Parallel AID Conllel'ter (or Flash Converter): A type of AID
converter that uses a bank of 2n_1 comparators and a decoder circuit to perform ultra-fast conversions.
Quad Current Switch (QCS): A monolithic circuit which
employs four matched. switched current sources and a reference current source to achieve 4 bit DIA conversion.
Quantizing Error (or Quantization Uncertainty): The inherent uncerlainty associated with digitizing an analog signal
by a finite number of digital output states. The ideal AID
converter has a maximum quantizing error of ±1/2least Significant bit. .
Reference: A circuit providing an accurate, stable voltage
used as the standard for comparison in an AID converter.
Relative Accuncy: The output error of an
as a percent of its full scale value.

AID converter

Resolution: The smallest analog input change an AID converter can distinguish. This is a function of the number of
output states, 2n , where n is the number of bits and is generally expressed in number of bits or in percent.
Successive Approximation Register (SAR): A digital circuit
that controls the operation of a successive approximation
AID converter and accumulates the output digital word in
its register.
Settling Time: In a DIA converter or an amplifier. the time
elapsed from the application of a full scale input step to
when the output has entered into and remained within a
specified error band around its final value.

Short Cycling: Termination of the conversion sequence of
an AID converter to less than the total number of clock peiods required for a full resolution conversion.
Status Output: An output logic state indicating when the
AID COnverter is busy ana when output data is ready.
Successift Approximation AID Converter: A popular type
of AID converter in which conversion is accomplished by a
sequence of n comparisons where n is the number of resolution bits.
Temperature CoeffICient: The stability with temperature of
the scale factor of the AID converter, generally expressed in
parts per million per degree CelSius.

·15V

_+

Vert.

Ax::;

over~!! ~CC1!~:l.cy.

Gain Error (or Scale Factor Error): The difference in slope
between the actual transfer function and the ideal transfer
function, generally given in percent.

___________

Figure 8 illustrates simple celibretion of the hybrid AID converter.
Two external 100K npotentiometen adjust zero and fulllC". for
the converter.

the sample·hold circuit into the hold mode, a 100 nsec start
convert pulse is applied to the AID converter after a I j.lSeC
delay. The I/,sec delay allows the sample-hold output to
settle from its tum-off transient so that this does not cause a
conversion error. The IO-bit AID conversion -then takes
place and is completed in just 6/,sec. The clock rate is increased by 20% by connecting the clock rate, pin 17, to
±5V. This, in addition to short cycling, reduces the conver·
sion time from 8/,sec at 12 bits to 6 jlSec for 10 bits.
The time required for sampling, delay, and conversion
is therefore about ll/,sec, giving a maximum throughput
Illte of 90 KHz. Such a circuit is commonly used in fast
data acquisition systems.
The sample.hold circuit reduces the aperture, or
measurement uncertainty, time of the circuit. With the
AID converter alone the measurement time is 6 jlSec, but
with the sample.hold this time is reduced to about 5 nsec.
This sampling AID converter can thus accurately sample
signals as fast as 70 kHz.
Figure 8 illustrates simple calibration of the hybrid
AID converter. Two external 100Kn potentiometers
adjust zero and full scale for the converier. A pulsed
start convert pulse is applied to the start convert input
and also externally triggers an oscilloscope. The converter output code is simply monitored by displaying
the serial output together with the clock output on the
vertical axis of the scope. There are 13 clock pulses and
12 intervals that show up as HI's or LO's on the scope.
Assuming 0 to ±IOV input range, the input pin 24
should first be connected to a precision voltage source
set to +1.2 mV (zero + 1/2 LSB). The zero adjust potentiometer is adjusted to give an output code that just
flickers between II1l... .. 1110 and 1111.. .. .1111. Next,
set the precision voltage source to +9.9963V (+FS·
1 1/2 LSB) and adjust the gain potentiometer to give an
output code that just flickers between 0000 .....0000 and
0000 .....0001.
The converter is now precisely aligned and gives a
quantization error of ±1/2 LSB maximum.

GZ

126

DATA ACQUISITION & CONVERSION HANDBOOK

Video analog-Io-cligital conversion
calls for virtuoso performances. And the plot
really thickens when you have to produce high resolution.
Table 1. Comparator thresholds for a

Accurately digitizing analog signals containing high
frequencies, demands ultrahigh-speed, or video, aid
converters. Such a converter is essentiai to diverse
uses like radar-signature or transient analysis, highspeed digital-data transmission, video densitometry,
and digital television. In television alone, a speedy
converter can help enhance images, correct time-base
errors, convert standards, synchronize or store
frames, reduce noise, and record TV.
Most video aid converters work in the I-to-20 MHz
range. But at these speeds, resolution can be a problem. Fortunately, 8 bits and fewer most often suffice
in ultrafast aid applications.
Higher resolutions are hard (and expensive) to come
by, particularly at 10 to 20 MHz. In this ultrahighspeed range, 4 bits is about the practical limit for a
single-stage converter. However, you can cascade aid
stages for more than 4 bits.
Below 5 MHz, you can retain the "one bit at a time"
concept of the familiar successive-approximation converter, while reducing the time delays inherent in
converting each bit. The "propagation" (or variablereference-cascade) converter of Fig. 1 does just this.

4-bit propagation-type aid converter
Scale

Comparator Number
2

J
FS-J LSB

3
+8.750

3/4 FS

4
+9.375
+8.125

+7.500
+6.875
+6.250

1/2 FS

+5.625

+5.000
+3.750

+4.375
+3.125

1/4 FS

+2.500
+1.875
+ 1.250

1 LSB

Comparators star in propagation a/d's

+0.625

ANALOG INPUT
(OlOIOV)

The critical parts of the circuit are the comparators,
which must be very fast, and the switches, which must
be not only very fast but also capable of withstanding
the reference voltage. A propagation aid converter
uses one comparator per bit. Furthermore, each bit
is converted in sequence, beginning with the most
significant. With a -5 V reference, the circuit of Fig.
1 handles inputs from 0 to +10 V.
Comparator AI makes its decision at a +5 V input:
when the analog-input voltage exceeds +5 V, the
output is true. The threshold of comparator A, is set
for an i'lPut of either +2.5 or +7.5 V, depending on
the output of comparator AI. If the analog input
voltage exceeds +7.5 V, comparator· A, also goes true.
If, however, the analog input voltage is between +5
and +7.5 V, the output becomes ZERO; an input

-!:IV

REF.

BIT I (MSB)

BIT 2

"'Y

\..~_ _ _ _ _

BIT 3

BIT 4 (LSB)
I

OUTPUT DATA

1. A propagatlon·type aid converter uses one comparator
per bit, with each bit converted in sequence. At best. this
type of aid runs at 5 MHz for up to four bits.

127

CODE

between +2.5 and +5 V produces a ONE. And for less
than 2.5-V input, the output becomes ZERO.
As you can see, then, the output of comparator AI
sets the threshold of comparator A2 via electronic
switch SI. SI switches one end of the resistive divider
at comparator A2 to ground when the output of
comparator AI is ZERO, and to the -5 V reference
when it is ONE. Therefore, the threshold of the second
comparator is set for either of two analog-inputvoltage levels: +2.5 or +7.5 V.
This process continues for comparators A, and A,.
Each succeeding threshold is set by the result of all
previous comparator decisions. Thus, comparator A,
has four possible threshold levels, + 1.25, +3.75, +6.25,
or +8.75 V. Similarly. comparator A, has eight possible threshold levels (for a summary of each
comparator's threshold levels. see Table 1).
Obviousiy. a propagation-type converter becomes
more complex as its resolution increases beyond 4 bits.
Higher resolution requires not only more resistorsto set the new threshold levels-but also higher-value
resistors. The resistor values go up in a 1. 2. 4.
8.... binary sequence. So as the number of bits increases. the resistors soon take on values so large as
to affect the conversion time for the less-significant
bits. The fault lies with slow settling of the currents
switch.1i through the resistors. The time constants.
caused by switch plus stray capacitances and the highvalue resistors. cause the delays.
Still. you can achieve 50-ns per bit conversions with
a propagation-type converter. After a new input is
applied to the converter. the resulting digital output
word propagates rapidly down the converter-output
lines. as each comparator and switch change states.
Instead of simply allowing the circuit to propagate
naturally. you can also operate it in a clocked mode
by using sampling (gated) comparators. rather than
the usual ungated kind.
But 5-MHz and higher conversion rates. together
with the complexity required for higher than 4-bit
resolution. severely limit the video uses of propagation-type analog-to-digital converters.

LEVEL

1111

J5

1110
1101
1100

14
13
12

1011

II

1010
1001

10

1000
01 t I
0110

,;

'

I

I

I

I

I

I

I

I

I

I

I

I

I

0100

0011
0010

0001
0000

I ......

Q

l+-

I
I

0101

~

:

ANALOG

C[Cf>-TR~~l!~ON
I
I
I

2.5

, ,
3.75

'
5.0

ANALOG INPUT VOLTAGE

2. The quantlzer transfer function for a 4-bit parallel-type
ShOW5 how thl? E'n!.t1og !nput is broken into 15
different levels. Each word of digitally coded output
signals represents a range. Q. of input voltage.
converter

is more popular because it is faster than propagation.
A parallel-type aid converter is simply a quantizer
circuit followed by a decoder circuit. As a matter of
fact these two functions are fundamental to all aid
converters. The difference is that these functions are
clearly separate in a parallel ald.
The quantizer section of a parallel converter is
defined by its transfer function. which is shown for
a 4-bit quantizer. in Fig. 2. The quantizer breaks up
the continuous-analog input (horizontal axis) into
discrete-output levels (vertical axis).
In Fig. 2. the output is divided into 16 different
states, or 2" levels, where n is the number of bits. Along
the horizontal axis of the transfer function are 2"-1
or 15 analog-transition points which represent the
voltage levels that define the edges between adjacent
output states or codes.
There is no one-to-one correspondence between
input and output for the quantizer, which assigns one
output code word to a small range. or band. of analoginput values. The size of this band is the quantum.
Q. and is equal to the full-scale-analog range divided
by the number of output states:

Quantizer plays the lead

Q = FSR

Fortunately, a much faster technique is available.
Parallel conversion (also called flash. or simultaneous)

2"

128

DATA ACQUISITION & CONVERSION HANDBOOK

REf
IN

r-

ANALOG
IN

Table 2. Parallel 3-bit a,ld coding

EXPANSION

-

I V2

R

I
I
I
I
I

R

I
I

R

7·Llne equally weighted Binary
code with over range
code

Scale
(fraction of full
scale)

I

+9/8
BIT 3
(lSB)

+3/4

BIT 2

+112
+114
1

I
I

R

a

I
I

I

11111111

1000

01111111

0111

00111111

0110

00011111

0101

00001111

0100

00000111

0011

00000011

0010

00000001

0001

00000000

0000

1

: 1/2 R

iL

COMPARATORS 1

The binary coaes are assigned by a circuit that
decodes the quantizer-output logic. Though you can
select any code, the code shown, natural binary, is
most used. Notice that the analog center of each code
word-the exact analog value-is depicted by a dot
on the transfer-function graph.
The transfer function in Fig. 2 depicts an ideal
quantizer or aid converter. A real device, of course,
has errors in offset, scale-factor (gain) and linearity.
Fig. 3 shows a circuit implementation of a 3-bit
parallel aid converter. Usually, the quantizer portion
of such a circuit consists of a bank of zn -1 high-speed
comparators. But, in Fig. 3, zn or 8, comparators are
used, because this circuit also provides an overrange
output that can be used for expansion.
The bank of comparators has zn analog-transition
points. These are directly set by biasing one side of
the comparator inputs from a reference with a series
string of equal-value resistors, R. The Q for this circuit
depends on the value of R, the reference voltage, and
the total resistance:
Q = (VREFR)/RTOTAL

:

________ 1_ _ _ _ _ _ _ _ _ _ _ _ 1I

3. The circuit for a parallel 3·bit aid converter (a) has
just two basic sections: the quantizer and the decoder.
The transition paints in the quantizer are set by biasing
each comparator. through a resistive divider and reference. The complete 3·bit analog·to·digital converter
comes packaged as a thin·film hybrid (b).

The bottom and top resistors in the string have
values of R/2, which correspond to the values of the
first and last analog-transition points. These transitions are at Q/2 and FS -(Q/2), respectively.
Without the overrange output, the last analog
transition point would be at FS - (3Q/2). The value
of the top resistor would then be 3R/2.

In Fig. 2, where the full-seale-input range is 10 V,

Q = !Q
2'

!Q
16
= 0.625 V.

Enter the decoder

Fig. 2 snows levels of 0 through 15 at the output.
When binary-code words are assigned to these output
states, as shown in the leftmost column, the transfer
function becomes that of a complete aid converter
rather than just a quantizer alone.

The parallel converter's decoder section is a rather
straightforward logic circuit. It translates the logic
outputs from the comparators into the most commonly used code, natural binary.

129

START

EOC

CONvERT

ANAL.OG

IN

@~'IV-<~.

1

8-BIT
DATA REGISTER

r

8IT~~-~r--r-~-'-~-b'--5-,-~-~.---.-'~
OUTPUT OATA

4.

Two-stage parallel aid converters can develop S-bit
resolutions at 20 MHz. Though conversion 1 begins at the

Start-Convert pulse and ends 65 nanoseconds later, subsequent conversions take only 50 nanoseconds.

Table 2 shows the coding for quantizer and decoder
outputs. In this quantizer-output code, the seven
comparator-output lines (eight, counting the overrange comparator) are equally weighted. This equally
weighted code is simple and unambiguous, but inefficient-only one output line changes at a time from
all-ZERO to all-ONE outputs. Except for not being
cyclical, the quantizer code is like the Johnson code
used in shift counters. Like the quantizer code, Johnson code proceeds from all-ZEROs to all-ONEs, but
then cycles back to all ZEROs.
In the decoder, simple NOR and OR gates perform
the logic according to the following equations:
A.
Bit 1
Bit 2 = As + A,.A.
Bit 3 = A, + (As'As) + (A,.A.) + (A,.A.),
where the A;s are the numbered-comparator outputs
in Fig. 3, Bit 1 is the MSB and Bit 3 is the LSB. The
AND function in the equations is replaced by a NOR
in the actual circuit. The OR function can be implemented by tying together the appropriate outputs
of wire-ORed ECL logic.
With ultrafast analog comparators, parallel conversion offers the ultimate conversion speed. Since the
comparators all change state simultaneously, the
quantizer output is available after just one propagation time. Of course, the decoder adds more delay, but
high-speed Schottky-TTL or ECL circuits can minimize the decoding time.
In 3-bit form with an additional comparator, for
·overrange, the parallel converter in Fig. 3 can be
expanded for higher resolution. You can connect two
converters, combine into one flash converter to get
often-needed 4-bit resolution. Likewise you can connect four such circuits for 5-bit resolution-and so
forth. In this way, these circuits can be used as
"building blocks" for ultrafast aId converters. Conversion rates of 50 MHz, for 3, 4, or 5-bit aId's, are

possible using the commercial hybrid version of these
expandable parallel converters.
Comparator plays a complex role

The most critical component in a parallel aId
converter-as in a propagation converter-is the comparator. It not only determines the speed of the
converter but also the accuracy. Ultrafast sampling
comparators like the 685, 686 and the dual 687 are
excellent for this function.
A sampling comparator has two Latch-Enable inputs that switch it into either a Compare or Latched
mode. In the latter, the comparator's digital output
is locked until the next comparison is made.
Whether or not you use a sampling comparator, you
must consider the propagation delay for small overdrive. This is important because the analog full-scalesignal range is generally small for ultrafast aId
converters-commonly between 1 and 4 V. The comparator must change state rapidly for a Q/2 analoginput change. For a 4-bit converter with a I-V input
range, this represents an overdrive of 31 mV; for an
8-bit converter with the same input range, the overdrive is just 2 m V.
The analog-input characteristics of a comparator
are important because they affect conversion accuracy. Input-offset voltage and input-bias current are
usually the most significant of these parameters. The
offset voltage directly affects the accuracy of the
quantizer's analog-transition points; the input-bias
current also affects the accuracy through the effective
input resistance of the comparator.
Since an ultrafast comparator generally has bias
currents as high as 10 iJ.A, its inputs must look into
low resistances. Fortunately, for small-signal ranges
like I to 4 V, each resistance in the series network
can be kept low. In an actual 3-bit parallel hybrid
130

DATA ACQUISITION & CONVERSION HANDBOOK

ANALOG
INPUT

f---50ns~c -----{

f2l

STAR&0

CONVERT

I

rl

f3l

G~ 2 n

G '2"

I

r,,
SAMPLE
HOLD

lO

--1

,,
I

.~nsec---l

l---65nsec
EDC I
(STATUS) :

Jzl

Gl

--,X

~l~~T _____

DATA VALID I

X

R..
DATA VALID 2

91011 12
I 2 34
5 678
OUTPUT
\. DATA
)
~-------~y---------~
m STAGES

~

5. Timing for the B·bit two·stage aid converter allows for
two modes in the sample·and·hold circuit-Hold and
Track. These occur between successive Start·Converts.
The second and succeeding conversions take 50 ns.

6. A generalized n·blt, m·stage aid converter develops an

converter, laser-trimmed, thin-film-resistor networks
make the transition points stable and accurate.
One comparator parameter that greatly affects
speed is input capacitance. For example, the analoginput line to a 4-bit aid with overrange feeds 15
parallel-comparator inputs. It must be driven from
a low-impedance source to retain high speed. Therefore, either a high-speed input-buffer amplifier or a
sample-and-hold circuit drives the input.
Parallel aid conversion suffers from one significant
drawback; more resolution than four bits requires
many comparators. The number (N,) increases exponentially with n, the number of bits:

nates the analog input with the proper impedance and
scales the signal for the sample-and-hold circuit,
During its conversion to digital form, the ultrafast
sample-and-hold acquires and holds the an;ilog-input.
The sample-and-hold output goes into two unitygain buffer amplifiers, one of which buffers the input
to parallel 4-bit aid converter 1. This aid converts the
input level, then stores the digital result in half of
the output-data register. In addition, 15 undecoded
comparator-output lines drive a I5-line, equallyweighted digital-to-analog converter. This dla, in
turn, generates an analog voltage that is subtracted
from the other buffered-input signal.
The subtraction result, a residual signal, goes to the
input of the second parallel 4-bit aid, the output of
which goes to the other half of the output-data
register. The input signal is therefore sampled and
converted to digital form in two 4-bit steps.
Four digital delays time the converter as shown in
Fig. 5. A pulse at the Start-Convert input begins the
timing sequence. The Start-Convert pulse puts the
sample-and-hold into the Hold mode for 30 ns. During
this time, the first 4-bit conversion is made and the
second 4-bit converter quantizes the residual signal.
While the second aid conversion is decoded and
transferred to the data register, the sample-and-hold
goes into the Track mode to acquire the next value.
When the conversion is done and the 8-bit word is
ready in the output register, the delay circuit generates and End of Conversion (or Status) pulse. In the
timing diagram, numbers 1, 2, 3 and 4 indicate the
relationship of the signals for the first, second, third

N, = 2" -1

An 8-bit converter, for example, requires 255 comparators. That many comparators vastly complicates
bias-current and input-capacitance problems-to say
nothing of the high power dissipation they produce.
Another problem, of course, is how to position so many
comparators while minimizing lead lengths.

Coming onstage-the two-stage aid
As a result, the practical limit of parallel aid
converters is usually 4 bits. Higher-resolution designs
use a two-stage parallel technique that is really a
combination of the parallel and propagation techniques. It cascades two 4-bit conversions.
This two-stage method is illustrated in Fig. 4, which
shows the block diagram of a complete 8-bit, 20-MHz
converter, including buffer amplifiers and a sampleand-hold. Starting at the input, amplifier A termi-

131

output with n X m bits of resolution. In each stage, except
the first, the analog result of the subtraction is amplified
by a circuit whose gain is 2".

Slower aid converters are alive and well
second to several ~s. Each clock period must allow
time for comparator switching, changing successiveapproximation-register states and dla converter
switching plus settling. Settling time for the dla
converter takes a large part of the clock period because
the output must settle to within half the leastsignificant bit before the comparison starts.

The two most popular techniques for aid conversion
are dual-slope (a) and successive-approximation (b).
Together these methods probably account for over
98% of all analog-to-digital converters in use.
Dual-slope conversion, an indirect method, converts
the analog-input voltage into a time period. Then a
digital clock and counter measure the interval. For
only serial-output data, a simple gate replaces the
counter. The method is simple, accurate, and inexpensive, but suffers one major drawback: Conversion
is usually slow~often taking milliseconds.
Successive approximation aid converters, on the
other hand, can be much faster. They can convert to 12
bits in 2 to 50 ~s and to·8 bits in 400 ns to 20 ~s. Also,
every conversion is completed in a fixed number (n) of
ciock periods, where n is the resoiution in bItS.

Successive-approximation, a direct method, puts a
dla converter inside a feedback loop containing both
analog and digital elements. The successive-approximation register controls the dla converter, and the
comparator and clock, in turn, control the register.
A conversion consists of turning on, in sequence,
each bit of the dla converter, starting with the most
significant. During each clock period, the analog input
and the dla output are compared. The comparison
determines whether to leave each bit on or turn it off.
So, after n clock periods, each bit has been turned
on, a comparison has been made, each bit's logic state
has been decided and the conversion is complete. Clock
periods usually last from just fractions of a micro-

able decoded aid's. Also, the I5-line dla converter, the
sample-and-hold and the input-buffer amplifier can
be readily hybridized. The remaining noncritical
circuit elements can be made from standard
monolithic devices and passive components.
The hybrid circuits' stable thin-film resistors can
be laser-trimmed for optimum linearity. The entire
circuit of Fig. 4 fits on a single circuit card, so laying
out critical components is less formidable.
Propagation and parallel two-stage are specific
examples of a more general conversion method by
which m stages of n bits each, make an aid converter
with m x n bits of resolution (see Fig. 6). In each case,
the residual analog signal from the subtraction is
boosted for the next stage by an amplifier with gain
of 2". This technique can produce a I2-bit aid converter
using three parallel 4-bit aid stages.

and fourth conversions. The delay from the leading
edge of the Start-Convert pulse to the falling edge of
the Status pulse is 65 ns-the delay for the first
conversion. After the first conversion, new output
data arrive every 50 ns-a rate of 20 MHz.
A two-stage parallel aid converter is practically the
only device used for ultrafast conversion at 8-bit
resolution. Moreover, just about all new 8-bit converters have built-in sample-and-holds to shorten the
effective aperture time of the conversion from the 50
ns of the converter in Fig. 4, to a fraction of an ns.
While the 8-bit aid in Fig. 4 is functionally simple,
it's actually difficult to develop. In fact, it usually
takes longer to develop than today's Qther types of
aid's. More engineering time can go into just determining circuit and ground-plane layout than into
any other part of the development.
Behind the scenes-a hybrid

GZ

At least one commercial 8-bit converter uses thinfilm hybrid components as building blocks, which
organize the critical-circuit functions into miniature
packages. For example, each 4-bit aid shown in Fig.
4 can be implemented with two hybrid 3-bit expand-

132

Compensate for temperature drift
in data-converter circuits
Data-converter circuits must operate in a nonideal world in which
temperature drift can reduce the effica.cy of their design. Beating
the problem requires an understanding of drift components.

requires an undel'standing of the sources of
data-converter temperature drift.
Compensating for data-converter temperature
drift can be a complicated process. involving
(depending upon system needs and designer
expertise) one or more of the following;
Properly calibrating the chosen converter
Choosing a converter that best suits the
system's stability needs
Mounting the chosen converter in n
temperature-regulated environment
Using a converter with provision for an
external reference
Controlling drift by means of external error
correction.
Whatever technique (or combination of techniques) you use, though, its effective applicatioh

r------~I
I

I

I

~------~

Although all data-conversion devices can operate over a defined range of ambient temperature,
as temperature varies within that range, the
elements of a device's accuracy-its offset, gain
and linearity-will change.
To compensate for this temperature drift, as
well as for drift occurring over time, most data
converters come with provisions for external
adjustment of offset and gain errors. In nearconstant temperature environments, though,
and for moderate-resolution devices, the drift
remains small. Thus, in such environments,
calibrating a converter for offset and gain at the

Ir-------------------------~I

I~---..J

CLOCK

Where does the drift come from?

SUCCESSIVE APPROXIMATION REGISTER

I

~--

~----------------.

I

----------

-----------~

:
I
I

I
I
I
RE

R£

RE

Re

:

I
I
I
I
I
I

+1.2V o-----Hf:-+--~F_+-_+F+_+F_I

I
I

'R

_______ JI

'R

'R

,

L
......

~ BIPOLAR OFFSET CONNECTION

Fig l-A popular data-converter configuration uses equal·value current sources to form either a DAC or (by connecting the
dotted lines) a successive-approximation AOC.

133

DATA ACQUISITION & CONVERSION HANDBOOK

Matching analog components
improves temperature tracking
ambient operating temperature usually suffices.
For a 12-bit ADC or DAC with 20-ppm/'C maximum gain drift, for example, the maximum gain
drift over ±5'C is only ±0.42 bit. (Converters with
14-bit (or greater) resolution, however, show
significant drift even for small temperature
changes.)
Consider a popular data-converter configuration (Fig 1), using a D/A converter employing
equal-value, switched pnp current sources. An
R/2R resistor ladder provides binary weighting,
and the servo loop of Al maintains constant
current through the transistors. In conjunction
with feedback resistor R .. the output amplifier
(A z) converts the output current into a voltage.

- lOV

GAIN

DRIFT~./
/

>-

~
::>
0

5V
/
/
/

/

/

/. /

/

/

/

/

/

/

/

/

/

/

/
/

/

/

/

/

/
/

/

/

/
/

/
/

/
/

/

/

5V

/

/\
/

/

/

Ro and the reference voltage provide a one-half
full-scale offset current for connection in the
bipolar mode.
Connecting the circuitry represented by the
dotted lines converts this circuit into a
successive-approximation AID converter, in
which
a
clock-controlled
successiveapproximation register (SAR) in turn controls
the D/A converter, and A, is a comparator rather
than an op amp.
In both the D/A- and AiD-circuit versions, this
circuitry's analog portion determines its temperature drift. Modern data-converter designs
match discrete components in such a circuit to
cancel the drift errors and furnish stable operation over temperature. In hybrid-type D/A converters, for example, identical RES fabricated on
the same thin-film chip track each other closely.
Similary, the Rand 2R ladder resistors don't
influence temperature drift so long as they track

/

/

GAIN
DRIFT ............. /

>-

ir

>-

::>

/

0

/

/./

/

/
/

/
/

//\
/

/

/

'V
1111

0000

INPUT

/.,/
OFFSET

"

DRIFT

'5V

~

1,1

1111

1000

INPUT

Ibl

Fig 2-011 ••1 and gain drift

In

both unipolar (a) and bipolar (b) converters are finaar.

1,1

Ibl

1111

/ /

70'C,

~::>

,""
"
/

>-

1000

,

0

/

/

""

.

1111

T

>-

25 C

~::>

1000

0

/
/.
~

0000
5V

0000

10V

5V

INPUT

10V

INPUT

Fig 3-Llnearlty drift in an integrating AID converter (a) produces a change in the shape of the transfer function; in a
successive-approximation AID converter (b), it produces larger steps at adjacent code transitions.

134

each other. The current sources vary in proportion to the reference resistor R H , but R .. compensates for this effect, tracking RH over changes in
temperature by altering the gain of A,. In bipolar
operation, R" must track R" for stable operation.
Other possible temperature-drift errors result
from the change in transistor beta and V,,>:, but
the transistors, too, are matched for tracking.
Ideally, then, with perfect component temperature tracking, the circuit exhibits only three
sources of drift:
Offset-voltage drift caused by A,'s input
drifts
Leakage-current change in the current

TABLE 1-S0URCES OF TEMPERATURE DRIFT FOR CIRCUIT OF FIG 1
SYMBOL

do

SOURCE OF DRIFT

~::~;6~~~~i g~:RTEON~6~TF~F6~~Tu~~~ ~~t;ptl~~ER
A2 AND LEAKAGE-CURRENT DRIFT OF TRANSISTOR
CURRENT SOURCES

d,.
d,

d,

d"
d,

OFFSET DRIFT Due TO DIFFERENTIAL TEMPERATURE
TRACKING OF Ro AND RR
CIRCUIT GAIN DRIFT DUE TO DIFFERENTIAL TEMPERATURE TRACKING Of RE s, TRANSISTOR V.Es.
TRANSISTOR BETAS AND INPUT OFFSET VOLTAGE
AND CURRENT DRIFT OF SERVO AMPLIFIER Al
GAIN DRIFT OF VOL rAGE REFERENCE CIRCUIT
GAIN DRIFT DUE TO DIFFERENTIAL TEMPERATURE
TRACKING OF RF AND Rft
GAIN DRIFT DUE TO DIFFERENTIAL TEMPERATURE
TRACKING Of RAND 2R RESISTORS IN LADDER
NETWORK

sources

Gain drift caused by the temperature coefficient of the voltage-reference source.
In practice, of course, component tracking is
not perfect, thereby adding to the drift problem;
in well-designed circuits, the resulting drift

DIFFERENTIAL
LINEARITY IN
FRACTIONS LSB
Tran 1 =
- 0.3
Tran 2 =
- 0.1
Tran 3=
-0.1
Tran 4=
-0.1
Tran 5=
-0.0
Tran 6 =
- 0.0
Tran 7 =
-0.0
Tran 8=
-0.0
Tran 9 =
0.0
Tranl0=
0.0
Tran 11 =
-0.0

Ag 4-A te.t performed on I 12-blt D/A converter at
ambient temperature shows its differential-linearity error.

TEMPERATURE COEFFICIENT, PPM/"C

Fig 5-U.. Ihl. graph to datarmina tha range 01ltH' which a
particular conWlrte, remains monotonic. The method as.uma. an initiallinaarily arror of ± 112 LSB.

remains small but must nonetheless be accounted for. Component tracking is best when the
reRistors have equal values (and identical geometries) or are held to small resistance ratios.
Analyzing the drift
Table 1 describes the sources of temperature
drift for the circuit in Fig I, as well as delineating
the symbols referring to 'each drift component.
Table 2 groups these drift components according
to their contribution to + FS, - FS or zero
operating points.
Analyzing the circuit's unipolar operation is
simple. With an input code of 0000, all bits are
OFF, and the DAC output is zero. The only offset
drift, d", comprises the input-offset voltage, the
current drifts of A, and the leakage current of
the current sources. This last factor remains
negligible at room temperature but doubles with
each 10°C increase; it becomes significant at
approximately 100°C. The offset temperature
drift arising from do, shown in Fig 2a, shifts the
converter's entire transfer function up or down
with temperature. It affects all points on the
transfer function equally.
An input code of 1111 sets the DAC's output
bits ON, producing -FS output (-IOV in this
case). (For simylicity's sake, Fig 2a shows the
output inverted.) At this output level, several
sources of gain drift come into play. Although d.
furnishes the most significant contribution, dc,
d H.. and d L , resulting from differential component
tracking errors, must also be dealt with. The gain
drift by itself rotates the transfer function
around the origin, as shown in Fig 2a_
To summarize: The unipolar mode has the least
drift at zero; it has the greatest drift at - FS.
Bipolar operation introduces additional drift
sources. With an input code of 1000, the converter
output is zero. Adjusting the current through Ro
during calibration precisely balances the offset
current and MSB source current to provide zero
output. Three sources of drift--d., dc, and d Rocombine here to move the transfer function up or

135

DATA ACQUISITION & CONVERSION HANDBOOK

Linearity drift changes
transfer-function shape
down with temperature.
An input code of 1111 produces -FS (-5V)
output. Three new drift sources-d", d"F and
d,-add to the three present at zero. Finally, an
input code of 0000 turns all bits OFF; the output
is then +5V or + FS. The only current into the
output-amplifier summing junction comes from
the reference through R". Now all drift sources
except d, and dl. are present-all current sources
are OFF.
To summarize: In the bipolar mode, the least
drift occurs at zero output; the worst, when all
inlJut Lit~ afe ON. "Vhen all bits are OFF, drift
lies between these extremes.
A c()mpal'isoll of the two modes of operation
shows that unipolar exhibits fewer drift sources
and that 111 either mode the least drift occurs at
zero output. Realil.e also that the largest source
of temperature drift in either mode comes from
the converter's reference.
Maintaining linearity can be difficult

Linearity drift (which changes the shape of the
converter's transfer function) is the most difficult drift component to handle. Fig 3a illustrates
the effect of this component on an integrating
AID converter: Integral linearity-the maximum
deviatiun from an ideal straight line-is the

16
CHANNEL

12-BIT

ANALOG

AID CONVERTER

MULTI

ADC-HZ12B

predominant type of linearity error here. A
change in temperature increases the transfer
function's curvature.
In a successive-approximation AlP converter,
on the other hand, the predominant linearityerror form is differential-linearity error. Illustrated in Fig 3b, this error is the analog size
difference between ·actual adjacent code transitions and the ideal LSB size. Differentiallinearity drift occurs primarily at major code
transitions (one-half, one-quarter and threequarter scale), as shown in exaggerated form in
Fig 3b. This deviation increases with temperature change.
Determining an n-bit converter's worst-case
differential-linearity errors requires measuring
n- 1 differences. The first measurement is the
difference between the most significant bit and
all other bits; the second measures the difference
between the MSB plus the second bit with all
other bits, and so on. Ideally, each measurement
produces a 1-LSB difference. The results of such
a test, performed at room temperature on II
high-performance 12-bit D/A converter, appear
in Fig 4. Repeating the measurements at the
operating-temperature extremes determines the
con verter's differential-linearity temperature
coefficient (DLTC):
DLTC=.lDL/·H
where .lDL is the worst-case change in differential linearity between the two temperatures and
.lT is the temperature difference.
The combination of DLTC and temperature

PLEXER
MV 1606

MICROCOMPUTER

ADDRESS

DECODER
AND
CONTROL

FIg 8-A •• H-caHbretlng data-converter circuit requires two channels for the calibration process. The '" C stores the
correct output codes in its memory and compares them with the actuS! output codes.

136

TABLE 2-ERROR ANALYSIS OF TEMPERATURE·DRIFT SOURCES

TABLE 3 DIFFERENTIAL·LlNEARITY TEMPERATURE COEFFICIENTS
REQUIRED TO GUARANTEE MONOTON1ClTY OVER STANDARD RANGES

OUTPUT
OPERATING MODE
UNIPOLAR
BIPOLAR

'F'

0
00

da + dRO+d R
+d RF

do + de
+d RO

F'

RESOLUTION

00+ 0R+ ae
+ dRf + dt
do + dc + dRo
+ d R + dRF + d t

'"'~"
10

"
14
16

NOTE:
A CONVERTER WITH PNPCURRENT SOURCES (FIG 1) IS
A MODEL FOR A CONVERTER WITH NPNCURRENT SOURCES,
+FS ANO - FS ARE INTERCHANGED

, -.,

OT070 C
43.4
10.8
2.7
0.68
017

25 TO +85 C
or 60
32.6
81
2.0
0.51
0.13

55 TO +125 C
..IT'' 100

19.5
4.9
1.2
0.31
0076

•..IT REPRESENTS THE CHANGE FROM +25 C

change can, if large enough, cause a D/A converter's output to be nonmonotonic; an A/D converter
ct~ a choice between three competing technolog:ie~:
monolithic, hybrid, and modular, each with its own
specific advantages. Since A·D and D·A converters are
hasically analog circuits that have digital inputs or out·
puts, the computer systems engineer who may be mostly
familiar with digital techniques must become familiar

plication of data converters has increased enormously
as the use of minicomputers and microcomputers has
grown. Typical applications of data converters involve the
areas of process control and measurement where the
inputs and outputs of the system must be in analog form,
yet the computation and control functions are performed
digitally. In such a system, input variables such as
temperature, flow, pressure, and velocity must be con.
veTted into electrical form by a transducer, then ampli·
fied and converted into digital form by an al1alo,,·lo.
digital converter for the computer to process.
Since the computer nol only measures and determine~
the state of a process, but also controls it, its computations must be employed to close the loop around the
sy:stem. This is done hy causing the computer to actuate
inputs to the process itself, thus controlling its state.
Because the actuation is done hy analo,x control parameters, the output of the digital computf'!r mu~t he con·
verted into analog form by a di!l:ilal·to·analog COllverter.
Such a closed loop feedback rontrol system is shown in
Fig l.
Interfacing by analog.to.digital I A·D·I and digital.to.
analog I D.A) converters performs a vital role. At the

139

ANALOG

PROCESS

ANALOG

Fig 1 Computer controlled feedback control
system .. Computer closes loop around process
to control Its stale. However I two Interfaces
are required: A-D converter and O-A converter

D1G1TAL
COMPUTER

fS

wilh the many analog specifications describing data
converter performance in order to choose the correct can ..
verter for a specific requirement.

:

---------------------"
FS '" FULL SCALE
,/'
Q '" QUANTUM

I

I
I

I

~,/

I
I

Data Converter Transfer Functions

I

I
I

~FS

I

Fig 2 .hows the transfer function of an ideal 3-bit D-A
converter (DAC). This converter is assumed to be of the
parallel type, as are virtually all DACs in use today. A
parallel DAC responds simultaneously to all digital input
lines whereas a serial DAC responds sequentially to each
digital input. The transfer function representing a 3-bit
DAC is a discontinuous function; its analog output voltage
or current changes only in discrete analog steps, or
quanta, rather than continuously. However, a one-to-one
correspondence exist~ between the binary input code and
the analog output value. For each input code there is
one, and only one, possible output value. Analog step
magnitude, or quantum, is shown as Q.
The horizontal axis is the input binary code, in this
case a 3-bit code, increasing from 000 to Ill. The number of output states, or quanta, is 211 , where n is the
number of bits in the code. For a 3-bit DAC, the number
of states is 2 3 or 8; for a 12-bit DAC, the number of states
is 212 or 4096.
Fig 3 illustrates the transfer function for an ideal 3-bit
ADC. This transfer function is also discontinuous but
without the one-to-one correspondence between input and
output. An ADC produces a quantized output from a continuously variable analog· input. Therefore, each output
code word corresponds to a small range (Q) of analog
input values. The ADC also has 2" output states and
2" - 1 transition points between states; Q is the analog
difference between these transition points.
For both ADCs, Q represents the smallest analog difference that the converter 'can resolve. Thus, it is the
resolution of the converter expressed in analog units.
Resolution for an A·D or D·A converter, however, is commonly expressed in bits, since this define. the number of

I
I
I

I
I
I

:
I
I

B1NARY 1NPUT CODE

Fig 2 Ideal DAC Iransfer funclion.
This I/O graph Is shown for 3-bit DAC
which has one~to~one correspondence
between input and outpul

-----------..
F~:~~~T~~LE

---------~

,/ :

ANALOG IN;>LiT lVOL TSI

Fig 3 Ideai ADC Iransfer funclion.
I/O graph iIIuslrales 3-bil ADC which
has quantized characteristic

140

DATA ACQUISITION & CONVERSION HANDBOOK

TABLE 1
Summary of Data COnverter CharacterilticI
Resolution
(n)

8
10
12
14
16

States

Binary Weight

Ofor

(2")

.-~

10VFS

16
64
256
1024
4096
16384
65536

0.0625
0.0156
0.00391
0.000977
0.000244
0.0000610
0.0000153

0.625 V
0.156 V
39.1 mV
9.76 mV
2.44 mV
610 ~V
153~V

states of the converter. A converter with a resolution of

Dynamic
Range (dB)

Max Output for

34.9
46.9
58.9
71.0
83.0
95.1
107.1

24.1
36.1
48.2
60.2
72.2
84.3
96.3

9.3750
9.8440
9.9609
9.9902
9.9976
9.9994
9.9998

10V FS (V)

9uanfization Noise and
Dynamic: Range

12 bits, then, ideally resolves 1 part in 4Q96 of its
analog range.
For an ideal ADC or DAC, Q has the same value any.
where along the transfer function. This value is Q =

Even an ideal A-D or D-A converter has an irreducible
error, which is quantization uncertainty or quantization
noise. Since a data converter cannot distinguish an

FSR/2 11 , where FSR is the converter's full~scale range-the

difference between the maximum and minimum analog
values. For example, if a converter has a unipolar range
of 0 to 10 V or a bipolar range of -5 to 5 V, FSR in
both cases is 10 V. Q is also referred to as one least
significant bit (LSB", since it represents the smallest code
change the converter can produce, with the last bit in
the code changing from 0 to 1 or 1 to O.

analog difference less than Q, its output at any point
may be in error by as much as ±Q/2.
Fig 4( a) shows an ideal ADC and an ideal DAC that
digitize and then reconstruct an analog slow-voltage ramp
signal. The ADC and output register are both triggered
together so that the DAC is updated in synchronism with
the A-D conversiohs. The DAC output ramp is identical
with the analog input ramp except for the discrete steps
in its output (not counting time delay). If the output
ramp is subtracted from the input ramp as shown, the
difference is the quantization noise-a natural result of
the conversion process. This noise [Fig 4(b) 1 is simply
the difference between the transfer function and the
straight line shown in Fig 3. Quantization noise from
an ideal conversion is therefore a triangular waveform
with a peak·to-peak value of Q.

Notice in the transfer functions of both A·D and D·A
converters that the output never reaches full scale. This
results because full scale is a nominal value that remains
the same regardless of the resolution of the converter.
For example, assume that a DAC has an output range of

o to

SIN Ratio
(dB)

10 V; then 10 V is nominal full scale. If the con-

verter has an 8-bit resolution, its maximum output is

255/256 x 10 V = 9.961 V. If the converter has 12·bit
resolution, its maximum output voltage is 4095/4096 x
10 V = 9.9976 V.

As with most noise sources, the average value is zero,
but the rms value is determined from the triangular
shape to be En (rms) = Q/yI12. Thus, a data conversion
system can be thought of as a simple signal processor
that adds noise to the original signal by vittue of the
quantization process. Since this noise is an inherent part
of the conversion process, it cannot be eliminated ex·
cept with a converter of infinite resolution. The best
that can be done, even with ideal converters, is to reduce
it to a level consistent with desired system accuracy.
This is done by using a converter with sufficiently high
resolution.

In both cases, maximum output is one bit less than

indicated by the nominal full·scale voltage. This is true
because analog zero is one of the 2 n converter states;
therefore, there are only 211 - I steps above zero for

either an A-D or D·A converter. To actually reach full scale
would require 211 + 1 states, necessitating an additional
coding hit. For simplicity and convenience then, data
converters always have the analog range defined as
nominal full scale rather than actual full scale for the
particular resolution implemented.
In the transfer functions of Figs 2 and 3, a straight
line is passed through the output values in the case of the
DAC and through the code center points in the case of
the ADC. For the ideal converter, this line passes pre·
cisely through zero and full scale. Table 1 summarizes
the characteristics of the ideal A·D or D·A converter for
the most commonly applied resolutions.

In many computerized signal processing applications,
it is necessary to determine the signal.to·noise (S/N)
ratio, which is a power ratio expressed in decibels. It can
be found from the ratio of peak·to·peak signal to rms
noise as follows.

141

I"

+
Fig 4

Signal digitization and reconstriJc-

tion (a) and quantization noise (b). Quan-

ERROR SIGNAL

tization noise is shown as difference be-

'"

"o~V /1V /1V /1V /1V /1V /1V /

. ',0

tween Input and output for Ideal data conversion system

-;-

J'

2'Q
siN Ratio (dB) = 10 log [ QIy'12

= 6,02.

_

= 20 log 2' + 20 log v'12

+ 10.8

(l)

The sIN ratio increases by a factor of about 6 dB for
each additional bit of resolution.
Dynamic range of a data converter, another useful
term, is found from the ratio of FSR to Q, This ratio is
the same as the number of converter states.

1,1

Dynamic Range (dB) == 20 log 211 == 20n log 2 ;;::: 6.02n

(2)

Therefore, simply multiplying the number of bits of
resolution by 6 dB gives the dynamic range, siN ratio
and dynamic range are summarized for the most popular
resolutions in Table 1.

Ib'

Nonideal Data Converters
Real A·D and D·A ,converters exhibit a number of de·
partures from the ideal transfer functions just described.
These departures include offset, gain, and linearity errors
(Fig 5), all of whicb appear simultaneously in any
given data converter. In addition, the errors change with
both time and temperature. In Fig 5(a), the ADC transfer function is shifted to the right from the ideal func.
tion, This offset error is defined as the analog value by
which the transfer function fails to pass through zero;
it IS generally specified in millivolts or in percent of
full scale,
In Fig 5 (b), the converter transfer function bas a
slope difference from the ideal function. This gain, or
scale factor, error is defined as the difference in full·
scale values between the ideal and actual transfer func·
tions when the offset error is zero; gain error is expressed in percent.
An ADC transfer function in Fig 5 (c) exhibits linearity
errOf, a curvature from the ideal straight line. Linearity
error, or nonlinearity, is the maximum deviation of the
transfer function from a straight line drawn between zero
and full scale; it is expressed in percent or in LSDS (such
as ± V2 LSD), Fig 5 (d) shows the total error of a nonideal

I"

Fig 5

Errors in nonldeal A-O converters.

Transfer functions are shown for. ADCs
with offset error (a), gain firror (b), and
linearity error (c). ADC with all three
errors present will have quantization er-

ror as shown in (d)

142

DATA ACQUISITION & CONVERSION HANDBOOK

Nonlinearity
Linearity error is the most difficult error to deal with
since it cannot be eliminated by adj ustment. Like quantization error, it is an irreducible error. Basically, there
are just two methods to reduce linearity error, hath of
which are expensive: either use a higher quality converter with better linearity, or perform a digital error
correction routine on the data using a computer. The
latter, of course, may not be feasible in many applications. Ther~ is some merit in using a more expensive
converter, however. For example, suppose that an ultralinear 8-bit ADC is required. Most good quality cortverters
have iinearity 'errors specified to less than ± % LSD. If
a more expensive 12·bit ADC is employed with only 8
output bits used, then its linearity error of ±1j2 LSD out of
12 bits is the same as ±%:! LSB out of 8 bits. This converter, therefore, becomes an ultralinear a-bit ADC and
probably at not too great an additional cost.
Actually, two types of linearity errors existing in
A-D and D·A converters are integral linearity error and
differential linearity errOf. Integral linearity error in
Fig Sfcl is due to the curvature of the transfer function,
resulting in departure from the ideal straight line. The
definition given for integral linearity error as the maximum deviation of the transfer function from a straight
line between zero and full scale is a conservative one
used by most data converter manufacturers. It is an
"end-point" definition, as contrasted with the normal
definition of linearity error as the maximum deviation
from the "best. fit" straight line.
Since determining the best· fit straight line for data
converters can be a tedious process when calibrating
the device, most manufacturers have opted for the more
conservative definition. This means that the converter
must be aligned accurately at zero and at full scale to
realize the specified linearity. The end-point definition
can mean a linearity that is twice as good as a best·fit
definition, as illustrated in Fig 6. Notice that the curva·
ture may be twice as great with the best·fit straight line
definition.
Differential linearity error is the amount of deviation
of any quantum from its ideal value. In other words, it
is the deviation in the analog difference between two
adjacent codes from the ideal value of FSR/2 n. If a data
converter has ± V2 LSB maximum differential' linearity
error, then the actual size of any quantum in its transfer
function is between lj2 LSB and 1% LSB; each analog
step is 1 ± % LSB. Fig 7 illustrates the definition. The
first two steps shown are the ideal value Q = FSR/2 n •
The next step is only %Q, and above this is I%Q. These
two steps are at the limit of the specification of ± 1h LSB
maximum differential linearity error. Most data converters today are specified in terms of both integral and
differential linearity errOf. In production testing of data
converters, quanta sizes are measured over the converter's
full·scale range.
Two other important terms are commonly used in
conj unction with the differential linearity error specification. The first is monotonicity, which applies to DACs.
A monotonic DAC has an analog output that is a continuously increasing function of the input. The DAC transfer
function shown in Fig 8(a) is monotonic even though
it has a large differential linearity error. The transfer

;/
END-POINT
/"
DEFINITION - - - - ; / /

no

/

/

////

',FS
ANALOG INPUT (VOLTS)

Fig 6 Comparison of linearity error definitions. Curves illustrate end-point and
best-fit definitions of linearity error in an

ADC

---------------------~

'I

/'

'"
'"
100

on
010

FSR

'"

',FS

FS

ANALOG INPUT (VOLTS)

Fig 7 Definition of differential linearity error. This transfer function illustrates ±Y2 LSB differential linearity
errors. Differential linearity error of
zero means that every step in transfer
function has size of precisely Q

which contains offset, gain, nonlinearity, and quantization errors. Compare this curve with that of Fig 4(b).
Fortunately, most A-D and D-A converters on the market
today have provision for trimming out the initial offset
and gain errors. By means of two simple external potentiometer adj ustments, the offset and gain errors can
be virtually reduced to zero or within the limits of
measurement accuracy. Then, only the linearity error
remains.
ADC,

143

FS

'~"
~

~

:Y,FS

~

'f.,F5

-----------------/

§
g

~

Y.FS

BINARY INPUT CODe
("

(,(

~ ----------------A--

I

111

~

~

§
'l;FS

§
g

",FS

~

NON MONOTONIC

,

I
i

llU

~ 101

\

§ 100
~ 011

~ 010

y'FS

]l,FS

'Y.FS

FS

ANALOG INPUT (VOLTS)
(b(

(b(

Fig 8

Monotonic

(a)

Fig 9 No missing code (a)
and missing code (b) in ADC
output. Differential linearity
error of less than ±1 LSB assures that there are no mjss~
ing codes in transfer function

and

non monotonic (b) DAC outputs. Monotonicity means output is continuously increasing
fUnction of input

function of Fig 8(b), on the other hand, is nonmono-

weighted current sources. The worst differential linearity
errors occur at the maj or code transitions, such as 114 ,
V2, and % scale. If these differential linearity errors are
smail, then the integral linearity error will also he small.

tonic since the output actually decreases at one point.
In terms of differential linearity error, a DAC may go
nonmonotonic if the differential linearity error is greater than ± 1 LSB at some point; if the differential linearity
error is less than ± 1 LSB, it assures that the output is
monotonic.
The term missing, or skipped, code applies to ADCs.
When the difIetential linearity error of an ADC is greater
than ± 1 LSB, the output may have a missing code j if
the differential linearity error is less than ± I LSB, it
assures that there are no missing codes. Fig 9 (a) shows
the transfer function of an ADC with a large differential
linearity error hut with no missing codes. In Fig 9(h),
however, the differential linearity error causes a code to
he skipped in the output.
For ADCs, the linearity characteristic depends on the
technique of A-D conversion used; each converter type
exhibits its own specific nonlinearity characteristic. Fig
10 illustrates the nonlinearity characteristics of the two
most popular types of ADCs: successive approximation
and dual-slope integrating. With the successive approxi.
mation ADC, and also with other feedhack type ADCs that
use a parallel input DAC in the feedhack loop, differential
linearity error is the dominant type of nonlinearity. This
is due to the parallel input DAC, which is made up of

The difficulty at the major transition points is that, for
example, the most significant bit current source is turning on while all other current sources are turning off.
This subtraction of currents must be accurate to ±V2 LSB
and is a severe constraint in high resolution DACs. This
means that the weighted current sources must be precisely
trimmed in manufacturing. The most difficult transition
is at Y2 scale, where all hits change state (eg, for an
8·hit converter, 01111111 to 10000000), and the worst
differential linearity error generally occurs here.
The next most difficult transitions occur at

1~

scale and

% scale, where all hut one of the hits change state (eg,
for an 8-hit converter, 00111111 to 01000000 and
10111111 to 11000000, respectively). Relatively smaller
differential linearity errors may also occur at the 1f8, %,
%, and % scale transitions, and so on. Fig 10(a) shows
a successive approximation ADC transfer function, illustrating exaggerated differential linearity errors at 114 ,
Yz, and % scale. If these errors are properly trimmed
out in manufacturing, then 'both differential and integral
linearity errors will he less than ± Y2 LSB.

144

DATA ACQUISITION & CONVERSION HANDBOOK

ANALOG INPUT(VOLTS)

,.,

Fig 10

Linearity characteristic of successive

approximation (a) and dual slope Integrating
(b) ADes. Transfer function of successive
approximation converter exhibits mostly differential linearity error while that of integrating converter shows mostly integral linearity
error

Ibl

sius, and linearity error change with temperature is expressed in parts per million of full scale per degree
Celsius.
Effective aproaches to minimizing gain and offset
changes with temperature are available. If a converter
operates most of the time at a given temperature, then
its offset and gain should be zeroed at that temperature.
If, however, the ambient temperature varies between two
temperatures, the converter should be calibrated midway
between those two temperatures. Another approach to
minimizing changes with temperature is to use a converter with a low temperature coefficient to meet the
desired specification. Data converters with low temperature coefficients are, of course, more expensive, but this
may be the most economical solution to the problem
when all design factors are considered. Another method
of minimizing gain error is based on the fact that many
data converters with internal references have provision
for connecting an external reference. In such a case, it is
possible to connect a lower temperature coefficient external reference to the converter. This can be particularly
effective where a number of converters are used together
and one reference is used for all of them.
Linearity error temperature coefficient is the most
troublesome specification, since it resists correction. In
many applications, it is desired that the converter be

Fig. lO(b) shows a dual-slope integrating ADC transfer
function. In this case, the predominant nonlinearity is
the integral linearity error; differential linearity error
is almost nonexistent in integrating type ADCS, which
also includes charge balancing ADCS. The curvature of
the transfer function is caused by a nonideal integrator
circuit. Differential linearity is determined by the time
between clock pulses in the converter, and this is constant
within any conversion cycle.

Temperature Induced
Errors
Ambient temperature changes cause variations in offset,
gain, and linearity errors. If a converter is operated at a
constant temperature within its specified operating temperature range, offset and gain errors can be zeroed by
external adjustment at that temperature. But if the CODverter must operate with changing ambient temperature,
then the problem becomes acute.
Offset change with temperature is generally specified
in microvolts per degree Celsius, or in parts per million
of full scale per degree Celsius. Gain temperature coefficient is specified in parts per million per degree Cel-

145

I--------~ -55 TO 125°C

1------

-25T085°C

4QPPM,ac
1 LSB

-~---

-----

lLSB

---------------

24PPM/ Q C
ACTUALA-O
CHARACTERISTIC

Fig 11

Butterfly gain tempco

characteristic

for

12-bit

ADC

with ±1 LSB maximum gain error. Converter is calibrated for
l"~rl) g~in error ;=It 25°C limits
shown are for ±1 LSB error
out of 12 bits over designated
temperature range

monotonic, or have no mIssmg codes, over the desired
operating temperature range. From the converter differential linearity temperature coefficient, it is useful to
determine the temperature range over which the con·
verter will have guaranteed monotonicity or no missing
codes. Using a conservative approach, it is assumed that
the converter has a maximum initial differential linearity
error of ±Y2 LSB. Then, if the differential linearity error
changes by not more than an additional V:! LSB, a DAC
will remain monotonic and an ADC will have no missing
codes.
With a 12·bit ADC for example, % LSB is equal to 120
ppm. If the operating temperature range is 0 to 70 'C and
the converter is calibrated at 25 oC, the maximum temperature change is 70°C - 25 DC, or 45°C To guar·
antee no missing codes, the differential linearity temperature coeffioient must be 120 ppm/45°C = 2.7 ppm/,C
oJ full scale, maximum. An even lower differential linearity temperature coefficient is required to assure no missing
codes if the operating temperature range is the full -55
°C to 125°C military range. Performing a similar computation gives 120 ppm/lOO °C = 1.2 ppmj'C of full
scale, maximum, for the difJerentiallinearity temperature
coefficient.
Gain temperature coefficient is commonly specified by
the butterfly limits shown in Fig 11. All the lines pass
through zero at 25 ° C, where it is assumed that the
initial measun ment is made. The graph of Fig 11 shows
the maximum gain temperature coefficient required for a
± 1 LSB gain error for a 12-bit A-D or D-A converter
over three different temperature ranges. Observe that the

146

gain deviation curve must be within the bounds shown to
meet the specification of 2: 1 LSB maximum change. The
dotted curve shows an actual converter gain deviation
that would qualify as a gain temperature coefficient of
±2.4 ppmj'C over the -55 to 125°C operating tempera·
ture range. This represents a very low temperature coefficient for an actual converter since most available devices fall in the range of 5 to 50 ppmj'C

Error Budget Summary
A common mistake in specifying data converters is to
assume that the relative accuracy of a converter is determined only by the number of resolution bits. In fact,
achievable relative accuracy is likely to be far different
from the implied resolution, depending on the converter
specifications and operating conditions. This simply
means that the last few resolution bits may be meaningless in terms of realizable accuracy.
The best way to attack this design problem is with a
systematic error budget. An error budget partitions all
possible errors by source to arrive at a total error. In a
given system, this must be done not only for the A-D or
D-A converter, but also for the other circuits, such as
transducer, amplifier, analog multiplexer, and sample
and hold.
As an example, using the accuracy specifications for a
typical 12·bit ADC (Table 2), an error budget can be
determined based on the following assumptions: operating temperature range of 0 0 C to 50 0 C, maximum

DATA ACQUISITION 8r CONVERSION HANDBOOK

TABLE 2
Accuracy SpaelftcaUan. lor 12·BII ADC
Characteristic

Value

Resolution
Dillerentlal Linearity Error
Differenllal Linearity T empco
Gain Ternpco
Ollset Tampeo
Power Supply Sensitivity

12 Bits
±Yz LSB max
±2 ppm/'C of FSR max
±20 ppm/'C max
±5 ppm/'C 01 FSR max

0.002%/%

TABLE 3
Error Budget lor 12·BII ADC
Specification

Error (%)

Quantization Error (±V. LSB)
Dillerential Linearity Error (±Yz LSB)
Differential Linearity Error over Temp (2 ppm/'C x 25)
Gain Change over Temp (20 ppm/'C x 25)
Zero Change over Temp (5 ppm/'C x 25)
Change with Power Supply (1 x 0.002%)
Long Term Change

0.012
0.012
0.005
0.05
0.0125
0.002
0.02

Total Error. Worst Case
Total Statistical (rms) Error

0.1135
0.0581

power supply voltage change of 1 % with time and tem.
perature, and maximum converter change of 0.027<.
with time. Table 3 shows the resulting error budget with
a total worst case error of 0.1135%. It is improbable
that the errors will all add in one direction. Statistical
(rms) addition of the errors yields a lower value of
0.0581 %; this, on the other hand, may be too opti.
mistic since the number of error sources is small. At

any rate, the maximum error will be somewhere be·
tween 0.0581 % and 0.1135%, a significant difference
from what might be assumed as a 12·bit or 0.024%
converter. The ideal relative accuracy has been de·
graded by one to two resolution bits.
In applying data converters, best results are achieved
by reading the data sheet carefully for accuracy specifica.
tions, computing total error by the error budget method,
and then carefully aligning and testing the converter in

its actual application.
GZ

147

DATA ACQUISITION III CONVERSION HANDBOOK

Graphs give aperture time
required for a-d conversion

The time required for an analog-to-digital converter to
make a conversion is known as "aperture time," and depends on both the resolution and the particular conversion method employed. For commercially available a-d
converters that use the successive approximation

method, the aperture time may be 40 microseconds for
a relatively low-cost l2-bit converter, or as little as 4 1'5
for a more expensive high-speed l2-bit converter. In
many cases a sample-hold circuit is used ahead of an ad converter to effectively reduce the aperture times; the
sample-hold can take a very fast sample of the analog
signal and then hold the value while the a-d operation is
performed. (The time interval during which the signalhold circuit turns off is then the aperture time, and determines the conversion accuracy. The time for actual
a-d conversion can be longer.)
It is important for the designer to know what aperture ,
time is required to keep the system error to a tolerable
value in terms of the resolution of his a-d coverter. The

1. Sampling time. Aperture time lor 1-lllt accuracy at various resolutiOns in a-d conversion are shown here, Graph (a) gives aperture time
as a functiOn 01 signal rate of change for signals that are 10 volts full scale or 10 volts peak to peak, Graph (b) gives aperture time as a function of frequency for sinusoidal signals, Aperture times for larger allowed error can be found by reading on line for lower resolution, e,g" a 2bit error and B-blt resolution requires the same time as a 1-bit error and 7-bit resolution. Equations for these graphs are found in text.

148

If flV is held to I bit, and VFS is resolved into n bits,
then e = 11(2'), and
tA = V Fs I2 n (dVldt)

This is the equation for the family oflines in Fig. I(a),
with VFS = 10 volts and n - 4,6, . . . 16.
For a sinusoidal signal, which has a maximum rate of
change at its zero crossing,

/lV = AMPLITUPE UNCERTAINTY

flV= tA[d/dt(%)(Vsin.,t))._o = .,VtAI2

where V is peak-to-peak signal value. This gives

2. Error. Possibility of error in a-d conversion depends upon aperture time. The greater tA is. the greater the uncertainty in value of an
analog voltage that has been converted to digital level.

maximum aperture time that allows I-bit accuracy in
conversion of an analog signal to 4 bits, 6 bits,. . . ?r
16 bits is given here in two useful graphs. The graph m
Fig. I(a) shows this aperture time as a function of signal
rate of change, for signals that are 10 volts full scale or
peak to peak. Fig. I(b) gives the aperture time as a
function of the frequency of a sinusoidal signal.
The two graphs are derived with reference to Fig. 2,
which shows a time-varying signal and the amplitude
uncertainty flV associated with an aperture time tA
tA = fl V/(dV/dt)

If the fractional error e is the ratio of fl V to full-scale
voltage VFS,
tA = (e VFS)I(dVldt)

tA

= (2flV)/("V) = elfTf=

l/(2''TTj)

for a I-bit error and n-bit resolution. This is the equa.
tion for the family of lines in Fig. I(~). .
If the allowed error is to be 2 bits mstead of I bit,
then e = 2/(2'), so aperture times are doubled. An ~r:or
of 3 bits gives E = 4/(2'), and so o.n; thus a I.-bit mcrease in error is equivalent to a I-bit decrease m resolution on the graphs.
As an example of the ~seflll:ness ?f th~e graphs,. ~s­
sume that a I-kilohertz smusOidal signal IS to be digitized to a resolution of 10 bits. What aperture time must
be used to give less than I bit of error? The answer,
readily found from Fig..I(b), is 320 nanoseconds. For ~
bit error the aperture Ilme would have to be 160 ns.
This is surprising, because a I-kHZ signal ~s really not
very fast, and a IO-bit/320-ns converter IS not to be
found commercially available as a module. Therefore, a
sample-hold circuit would be required ahead of a
slower a-d converter.

GZ
NOTE: Pages ISO and lSI show large, detailed versions of Figure I.

149

DATA ACQUISITION & CONVERSION HANDBOOK

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DATA ACQUISITION & CONVERSION HANDBOOK

DO'S AND DO NT'S OF APPLYING AID CONVERTERS

In many applications, the limitation in the performance of
any system lies in how the individual components are
used. The Analog-to-Digital Converter (AID) can also be
considered as a component and, therefore, proper design
procedures are necessary in order to obtain the optimum
accuracy. Intersi( IC AID converters are inherently
extremely accurate devices. To obtain the optimum performance from them, care should be taken in the hook-up
and external components used. Test equipment used in
system evaluation should be substantially more accurate
and stable than the system needs to be. The following
sections illustrate DO's and DON'Ts to obtain the besl
results from any system.

1, DONT INTRODUCE GROUND LOOP ERRORS
Plan your grounding carefully. 'Probably the most
common source of error in any Analog-Digital system is
improper grounding. Let's look at Fig ,1. All the grounds
are tied together, so everything should be alright, right?
WRONG! Almost everything is wrong with this
connection.
liP
HI

ANALOG

SECTION

DIGITAL
SECTION

change as the converter goes from one phase of conversion to another. (Currents of this type injected into an
autozero loop are particularly obstinate). Another serious
source Qf variation is the change in digital and display
section currents with the result value. This frequently
shows up as an oscillating result, andlor missing results;
one value being displayed displaces the effective input to
a new value, which is converted and displayed, leading to
a different displacement, a new value and so on. This sequence usually closes after two or three values, which are
displayed in sequence.
A more subt!e source of eiiOiS in ttris ci(cuii Gumes from

the clock oscillator frequency. For an integrating converter, variations in clock frequency during a single conversion cycle due to varying digital supply. voltage or
supply currents, or ground loops to a timing capacitor,
will lead to incorrect results.
Fig 2 shows a much beller arrangement. The digital and
analog grounds are connected by a line carrying only the
interface currents between sections, and the input section
is also tied back by a low-current line. The display-current
loop will not affect the analog section and the clock
section is isolated by a decoupling capacitor. Note that
external reference return currents and any other analog
system currents must also be returned carefully to analog
ground.
liP

HI

ANALOG

SECTION

DIGITAL
SECTIOPII

liP
lO

:;;------j

~:;

CLOCK

AN

AN

P.S. GND.

DIG. DIG.
IGND. P.S.

csc.

FIGURE 1 Don't hook it up like this!

The power supply currents for the analog and digital
sections, together with the output or display currents, all
flow through a lead common to the input. Let us analyze
some of the errors we have introduced. The average
currents flowing in the resistance of the common lead will
generate a D.C. offset voltage. Even the autozero circuit of
an integrating AID converter cannot remove this error.
But, in addition, this current will have several varying
components. The clock oscillator, and the various digital
circuits driven from it, will show supply current variation
at the clock frequency, and usually at submultiple also.
For a successive approximation converter, these will
cause an additional effective offset. For an integrating
converter, at least the higher frequency components
should average out. In some converters, the analog
supply currents will also vary with the clock (or a submuUiple) frequency. If the display is multiplexed, that
current will vary with the multiplex frequency, usually
some fraction of the clock frequency. For an integrating
converter, both digital and analog section currents will

ANALOG
POWER
SUPPLY

FIGURE 2 Do hook it up like this.

2. DON'T COUPLE DIGITAL SIGNALS INTO
ANALOG LINES
Although Intersil's AID converter circuits have been
designed to minimize the internal coupling of digital
signals into analog lines, the external capacitive coupling
is controlled by the user. For the best results, it is advisable to keep analog and digital sections separatE1d on
PC boards. A few examples of the results of capacitive
coupling follow.
On dual slope converters, the "busy" lineswings from one
state to the other at the end and beginning of the autozero cycle. Capacitive coupling from this line to the autozero or integrating capaCitors will induce an effective
input offset voltage. A similar effect occurs with the

152

6. DO USE THE MAXIMUM INPUT SCALE

"Measure/Zero" line on charge-balancing converters and
for a successive approximation converter with coupling
between "End of Conversion" and a sample-and-hold
capacitor. For a multiplexed display device, coupling
between the multiplex or "digit" lines and these capacitors can lead to non-linearity of the converter. And
coupling from any digital line into a high-impedance input
line can lead to errors in any system.

3. DO USE ADEQUATE QUALITY COMPONENTS
For successive approximation converters, the resistors
used must have excellent time and temperature stability
to maintain accuracy. Any adjustment potentiometers,
etc. must be of compatible quality (note that in some
trimpots, the slider position moves with temperature!)
For dual slope converters, the component selection is less
critical. Long term drifts in the integrating resistor and the
capacitors are not important. However, any resistive
divider used on the reference, especially if it is adjustable,
must be of sufficient stability not to degrade system
accuracy. Dielectric absorption in the integrating capacitor is important (see reference 1) and the integrating
resistor must have a negligible voltage coefficient to
ensure linearity. Noisy components will lead to noisy
performance. whether in the integrator, autozero or clock
circuits.

4. DO USE A GOOD REFERENCE
Good references are like good wines; nobody is quite sure
how to make them but generally the older the technology
used, the better the result, and the proof lies in the tasting
(or testing). Thus, it is hard to beat the old temperature
compensated zener with the current flow adjusted to the
optimum for each diode. If you aren't into Zinfandel
Superior Premier Cru (1972), the Intersil8052 has a fairly
good reference built in. In either case, the division down
from what you get to the required reference voltage
requires care also (see above). And it is a fundamental fact
that no converter can be better than its reference voltage.

To minimize all other sources of error, it is advisable to
use the highest possible full scale input voltage. This is
particularly important with successive approximation
converters, where offset voltage errors can quickly get
above 1LSB, but even for integrating-type converters,
noise and the various other errors discussed above will
increase in importance for lower-than-maximum full
scale ranges. Pre-converter gain is usually preferable for
small original Signals. All Intersil's integrating converters
have a digital output line that can be used to extend autozero to preconditioning circuits (being careful not to
couple the digital signal into the analog system, of
course).

Also, DO CHECK THESE AREAS
Tie digital inputs down (or up) if you are not using them.
This will avoid stray input spikes from affecting operation.
Bypass all supplies with a large and a small capacitor
close to the package. Limit input currents intoany I.C. pin
to values within the maximum rating of the device (or a
few mA if not specified) to avoid damaging the device.
Ensure that power supplies do not reverse polarity or
spike to high values when turned on or off. Remember that
many digital gates take higher-than-normal supply
currents for inputs between defined logic levels. And
remember also that gates can look like amplifiers under
these circumstances. An example is shown in Fig 3, where
stray and internal input-to-output capacitance is
multiplied by the gain of the gate just at the threshold
causing a large effective load capacitance on the 8052
comparator (see reference 1 for the effects of this.) A noninverting gate here could lead to oscillations.

r-----H----i

:

'

COMPARATOR

5. DO WATCH OUT FOR THERMAL EFFECTS
All integrated circuits have thermal time constants of a
few milliseconds to dissipation changes in the die. These
can cause changes in such parameters as offset voltages
and V be matching. For example, the power dissipation in
an 8018 quad current switch depends on the digital value.
Although the die is carefully designed to minimize the
effects of this, the resultant temperature changes will
affect the matching between current switch values to a
small degree. Inappropriate choice of supply voltages and
current levels can enhance these differences. leading to
errors. Similarly, the power dissipated in a dual-slope
converter circuit depends on the comparator polarity and
hence varies during the conversion cycle. Offset voltage
variations due to this cannot beautozero'd out, and so can
lead to errors. Again a poor choice of comparator loading
or swing will enhance this (normally) minor effect. The
power dissipation in an output display could be coupled
into the sensitive analog sections of a converter, leading
to similar problems. And thermal gradients between IC
packages and PC boards can lead to thermo-electric
voltage errors in very sensitive systems.

8052

FIGURE 3

External Adjustment Procedure
Most of the A/D converters now offered by Intersil do not
require an offset adjustment. They have internal autozero circuits which typically give less than 10 I-' V of offset.
Therefore. the only optional adjustment required to
obtain optimum accuracy in a given application is the full
scale or gain reading.
With the AID converter in a continuous mode of conversion, the following procedure is recommended: The full
scale adjustment is made by setting the input voltage to
preciselV 'n LSB less than full scale or 'n LSB down from
nominal full scale. (Note that the nominal full scale is
actually never reached but is always one LSB short).
Adjust the full scale control until the converter output just
barely switches from full output to one count less than full
output.

PB SO

153

154

3. Data

Conversion
Systems

155

156

DATA ACQUISITION 8. CONVERSION HANDBOOK

Single hybrid package houses
12-bit data-acquisition system
Handling either 8 differential or 16 single-ended inputs,
device acquires data at 50 kHz or faster from many sources

o The shift from minicomputers to microcomputers in
data processing has been paralleled by the shift from
boards and modules to microcircuits in data conversion.
By now, complete microprocessor-compatible dataacquisition systems are available as single plug-in hybrid
or monolithic components. Eight-bit performance has
been the limit, though, with the hybrid devices being
much faster though less economical than the monolithic
converters. For 12-bit performance, users have had to
turn back to bulky modules or else interconnect two or
more hybrid circuits.
Getting down to one package

But a new 12-bit hybrid data-acquisition system is
offering users the convenience and cost savings of a
single integrated-circuit-compatible package, together
with the high performance and reliability of a hybrid
circuit. Besides multichannel capability, the device
includes address decoding logic, an adjustable-gain

instrumentation amplifier, a sample-and-hold circuit, a
12-bit successive-approximation analog-to-digital converter, control logic, and three-state output buffers for
interfacing with a microprocessor data bus. It is manufactured in two versions, the HDAS-8 handling eight
differential inputs and the HDAS-16 handling 16
single-ended inputs.
Housed in a hermetic 62-pin ceramic package, the
device meets all the requirements of MIL-STD-883A,
class B. To shrink its overall size, as well as optimize the
internal layout and make external access easy, the pins
are arranged around all four sides of the package,
instead of in two parallel rows. The use of ceramic
instead of metal keeps cost and especially weight down.
With such a complex hybrid, internal power consumption, of course, must be minimized. An equivalent
modular unit uses about 4.5 watts, which in the hybrid's
62-pin ceramic package would push the temperature at
the chip-mounting surface 50°C above ambient. Since

157

"" ::"

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49

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48

47

"'"'"

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::

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'"u"

45

46

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~

~

e=>

g
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0

>

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39

O!'
~

a

:s '"
~ "
;;;

40

38

~

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36 37

35 } IMSBI
34
81TS 1-4

4
3
2
1

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33

32
31

61

16

12-BIT
ANALDG-TDDIGITAL
CONVERTER

60

SINGLE-ENDED
DR
8 DIFFERENTIAL
INPUTS

58
57

ANALOG
MULTIPLEXER

I----'---i

30} 81TS 5-8
29
28

17

26

53
52

25
24

~;

l"

21

7

1211

10

9

10

41

MUX
ADDRESS OUT

4442

I~~
ADDRESS IN

I~

"8

>

'"u;

'I

16

~

'"

la)

1. The device. Hybrid

+5 V

EN 15-8)

1
J

RIT~~-11

(LSB)

EN 19-12)
EDC

fl fl r f

l!i 1413

19

EN 11-4)

43

B 
~

"'"'"

1817

.. '" '"Bc
~

>

data~acquisition

system (a) delivers 12-bit

data for 8 differential or 16 single-ended input channels. A few simple
connections (b). and the hybrid wilt automatically address the input
channels sequentially for a system throughput rate of 50 kHz.

fl-'""r
SIGNAL

4

BIT 1

CHoHI

35

Finally, in a move that reduces device complexity as
well as temperature rise, as many of the internal thinfilm resistors as possible are placed directly on the
ceramic substrate, and not on separate chips of glass,
silicon, or ceramic. With either technique, there will
always be a resistor-to-conductor interface. But making
a resistor part of the substrate eliminates the two wirebond interfaces at its terminations, making wjre~bond
weakness a less likely cause of failure.

O!'

"
58

w

CH, HI

g

I"IOAS-8

~
~

CHo LO
I

CH, LO

BIT 12

"I

How the device operates

"
43
Ib)

+15

v

the unit must be able to operate at 125°C ambient, and
silicon semiconductors deteriorate at junction temperatures above 150°C, the internal temperature rise must be
limited to 25°C. Considerations of power therefore override those of space so that, wherever possible, the device
employs bulky tantalum chip capacitors and low-power
transconductance-mode amplifiers, while the digital
control circuitry uses low-power Schottky transistortransistor logic only.

The circuit configuration (Fig. I a) for the device is a
fairly common one for a data-acquisition system. At the
front end is an analog multiplexer having either 8 differential or 16 single-ended channels, which may be
addressed randomly or scanned sequentially. Following
the multiplexer is an instrumentation amplifier that
extracts the input signal from common-mode noise. The
gain of this amplifier is adjustable (through an external
resistor) from I to 1,000, so that the maximum expected
range of the input signal becomes ± 10 volts at the
amplifier output for optimum dynamic range.
A precision sample-and-hold circuit then buffers the
selected signal, holding its level constant during the
actual conversion. The output of the sample-and-hold

158

DATA ACQUISITION & CONVERSION HANDBOOK

serves as the input to a 12-bit a-d converter, which
produces a binary number that is the digital representation of the selected analog input. For flexibility in databus organization, three-state logic elements, which are
configured in 4-bit bytes, buffer the digital data output
from the a-d converter.
The hybrid is very easy to use, as is evident from the
simplicity of the circuit (Fig. I b) needed to acquire eight
differential inputs. A few straightforward connections,
and the HDAS-8 deliv~rs 12-bit binary data at a rate of
50 kilohertz from eight sequentially addressed channels,
each having a ± 10-v signal range. Since no gain resistor
is used, the amplifier's gain is unity. A single strap
selects bipolar operation (+ 10 v), and another strap
from R delay to the + 5-v supply selects the internally
allotted delay time for the multiplexer and the amplifier
to settle.
To obtain continuous scanning of the input channels.
the user need do nothing at all to the address control
inputs. With its end-of-conversion flag tied to the strobe
input, the device will acquire data continuously at the
maximum rate. For self-strobe operation, though, the
rise time (from 10% to 90%) of the + 5-v supply (when
power is first applied or interrupted and then reapplied)
must be less than 10 microseconds, or else a latchup may
occur. For reliable operation, the user should examine
the EOC flag and apply a STROBE signal when it is
required. Even supply-bypass components are included
in the package.

Protection
A good ·part of the device's ruggedness is due to
overvoltage protection circuitry for the multiplexer. A
I-kilohm resistor on each channel input limits the
current flowing through protection diodes and, in combination with stray nodal capacitance, limits the rise time
of large spikes so that the diode can clip them before
they do any damage. Even without using any external
components, protection is assured to 20 v beyond the
± 15-v supply voltages.
Adding a series resistance to each input can increase
protection up to a diode current limit of ± 10 milliamperes. But large values of input resistance are not altogether desirable. Besides raising the input noise, they
increase the settling time of the instrumentation amplifier for changing input signals, as well as the multiplexer's recovery time from switching transients.
Expanding the channel capacity of the hybrid requires
just one external component, connected as shown in Fig.
2a. This hookup converts the HDAS-16 from a 16channel single-ended unit into a 16-channel differential
part. In fact, channels may be added almost without
limit at very little cost, as Fig. 2b illustrates. Here, with
the addition of just 15 multiplexers and one logic device
(a one-of-16 decoder), the H DAS-16 acquires 256 channels of low-level analog signals. In this application, the
unit compares the outputs from 256 temperature-sensing
2. Easy channel expansion. One external component converts the
HOAS-16 into a 16-channel differential part (a). Adding 15 multiplexers and a single logic decoder accommodates 256 input channels

(b). For throughput faster than 50 kHz. more hybrids are needed (c)

159

16

ANALOG
INPUTS
ILOW}

INHIBIT

'5 V

MULTI·

} MULTIPLEXER
ADDRESS
OUTPUT

PLEXER

I,}
RGAIN

diodes with the output of a single reference diode.
Indeed, the hybrid is built to be expanded - it can
handle up to 65,536 channels with the addition of only
17 logic circuits. The unit's multiplexer-enable line is
what makes this possible. Left alone, it is high, and the
internal multiplexer is enabled. But when pulled low, it
disables the internal multiplexer and frees the amplifier
input lines for external multiplexer control.
Although the circuit of Fig. 2b is an economical way
to handle 256 channels at a 50-kHZ rate, that throughput
may not be fast enough for some applications. A faster
throughput of 800 kHZ is easily achieved by interleaving
16 hybrids into 256 channels (Fig. 2c). This circuit is
actually just as simple as the slower one, for it still
requires only one external decoder device. Because the
hybrid uses three-state data outputs, all 16 units can be
tied to one data bus and enabled one at a time during the
delay period preceding the next conversion while the

STROBE

SAMPLE

AND
HOLD

data from the last conversion is still valin

Both the HDAS-8 and the HDAS-16 are ideally
suited to acquiring data quickly from many sources, with
two provisos: the sources should all have similar maximum signal levels, and the highest frequency components of the signal sources must be in the low audio
range. When the signal sources have dissimilar ranges,
the dynamic range of some signals will be less than
optimum because the gain of the differential amplifier
will be set to accommodate the largest signal range. This
limitation is normally overcome by using prescaling
amplifiers, which also serve as convenient low-imped-

1,1
SYNC IN

ance signal line drivers and as filter points to reduce

unwanted power-line signals and the like.
Acquiring high-frequency signals

SIGNAL

INPUT
SYNC
TAPa

~------------------

--R________________
fL

TAP'5 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

Ibl
3. Handling high-frequency input•. To acquire signals beyond the
mid-audio range requires a sample-and-hold circuit for each channel
(a). For a nonrepetitive high-frequency signal, a delay line and a
string of sample-and-holds slice the input into 16 pieces (b).

When the signal sources are to contain high-frequency
components that the data-acquisition system must recognize and acquire accurately, a very fast track-and-hold
circuit or, better yet, a true sample-and-hold should
intercept the signal and hold it for a precisely controlled
time. Once the signal has been processed by the multiplexer, the amplifier, and so on, its bandwidth and phase
delay are no longer precisely known. Figure 3a shows
one way to do real-time analysis of input signals having
frequencies up to 25 kHZ. With this circuit, to retain
precise information as to the time of sample, 16 fast
sample-and-holds simultaneously sample the input
signals, and the data-acquisition system digitizes the
held analog value on each input channel.
Beyond 25 kHZ, the inability of the hybrid to generate
two data points per cycle of the input .signal violates the
Nyquist criteria of signal sampling. When repetitive
events need not be analyzed in real time-for example,
when synchronized sampling heads provide sample
snatches with varying delays - the frequency limit
extends to the bandwidth of the sample-and-hold
circuits. But for real-time analysis of nonrepetitive
signals, another approach is needed.
Radar pulses are a common example of nonrecurring
pulses that contain critical target data that must be
analyzed in exceedingly fine detail in real time. To
handle them, the HDAS-16 data-acquisition system
requires just a tapped delay line and a string of fast

160

DATA ACQUISITION & CONVERSION HANDBOOK

1.333!1IG -16)

4. PuHing amplifier gein to work. It is even possible to turn the
HDAS-16 into a 16-bit a-d converter by applying the input signal to
the internal amplifier's inverting input. Here, the amplifier-input-Iow
line is being viewed as a high-impedance, transient-free signal input.

m

-A.-

A\M;---,
- c- - - -- - -1_-- - ---- - - -

~~'~2~OO~'-4~O~O~'~60~O~'~8=~O~M~1~,~~OO~'~l~~'O~O~'~l~.~O=O~-L­
sample-and-holds, as noted in Fig. 3b. In effect, the
sample-and-holds slice the radar pulse into 16 easyWAVELENGTH (nm)
to-digest pieces, while the delay line causes each
sample-and-hold to retain the analog information at 5. High gain. In this fast spectrophotometer application for monitorincremental times following the synchronization pulse. ing industrial waste, the hybrid's high-gain capability and adjustable
Meanwhile, the hybrid can address and digitize each settling time are exploited. Careful tailoring of delay time versus gain
input slice at a comparatively leisurely pace, producing a provides best system resolution in terms of data rate needs.
12-bit binary word for each of the 16 slices at a word
rate of 50 kHZ. Clearly, there is a limit to the number of between the input signal and the selected channel voltsample-and-hold circuits that may be addressed and age. (With R gain at 1,333 ohms, amplifier gain is 16.)
Only one channel address will be associated with an
digitized before hold-capacitor droop problems destroy
analog signal accuracy. This limit may be circumvented in-range 12-bit data word, and all other channels will
by adding more hybrids to the circuit, at any rate until yield all zeros or all ones. When the address of the
system cost reaches that of a real-time video converter. -oOielected channel is used as the top 4 bits and the resulting conversion data as the bottom 12 bits, the HDAS-16
To increa.. resolution up to 16 bits
generates a 16-bit complementary binary data word. For
Besides being useful as a video a-d converter, the input signals in the audio-frequency range, the channel
HDAS-16 may be operated as a 16-bit a-d converter. address will change by no more than one count from one
Unlike the HDAS-8, in which the two mUltiplexer conversion to the next, so that no more than two converoutputs are both committed to the amplifier's inputs, the sions are ever necessary to obtain valid data. This means
HDAS-16 has only one multiplexer output so commit- that the HDAS-16 will typically deliver 16 bits in 20
ted. It is tied internally to the amplifier's noninverting microseconds, or 40 itS maximum.
(high) input, leaving the inverting (low) amplifier input
for the user to connect, for example, to the signal source When high gain is n. .ded
common. (In-any event, the user must of necessity return
Some applications require both high gain and multieventually the signal source common to the hybrid's channel capability. However, when the gain exceeds 20,
the hybrid's amplifier needs more than the internally
signal or power common.)
Another way of looking at the HDAS-16's amplifier- allotted 9 itS for settling to within l2-bit accuracy. Even
input-low line is as a high-impedance transient-free though the signal inputs may change slowly, the amplisignal input, as illustrated in Fig. 4. Wired in this way, fier sees the mUltiplexer output as a fast-changing step
the HDAS-16 operates as a 16-bit a-d converter. Fifteen function, with changes occurring whenever the multiresistors, precisely matched and equal in value, divide plexer address changes.
the internal IO-v ref,erence into 16 equally spaced voltThe amplifier, then, must have enough time to settle
ages, so as to bias the input channels into 16 contiguous fully in response to these abrupt changes before a
windows. The amplifier will only amplify the difference conversion takes place. Suppose, for example, the appli-

161

photon-induced diode voltage is small, amplifier gain
must be large for a reasonable dynamic range. Instead of
strapping the hybrid's R delay pin directly to the + 5-v
supply, as is usually done, the user may add a series
resistor to increase the delay time between an address
change and the start of a conversion. By carefully tailoring the delay time to the gain, the user can optimize
system resolution versus data-rate needs. Even at a gain
of 1,000, throughput rate will be at least 3.3 kHZ, with
root-mean-square system noise held to less than '/2 least
significant bit.
Dealing with accuracy errors

Many users of data-conversion devices are puzzled by
the seeming inconsistency of specifications for relative
accuracy and absolute accuracy. But distinguishing
between the two is not all that difficult. In brief, relative
accuracy is a measure of a device's differential linearity
and monotonicity, while absolute accuracy ieflects the
unit's gain and offset stability. Furthermore, relative
accuracy requires that similar components do the same
thing with time and temperature, whereas absolute accuracy requires that a component does not change with
time and temperature-a requirement that flies in the
face of reality.
As it advances, process technology will continue to
reduce accuracy errors, but it will always come closer to
optimizing relative than absolute accuracy. Certain
circuit techniques, however, permit doing away with
absolute-accuracy errors altogether. For example, the
la)
simple one shown in Fig. 6. cancels offset errors, and a
twin circuit could be used to cancel gain errors as well.
This technique uses a charge-pump loop to hold absolute
errors below measurable levels for all time and all
temperatures. When data (offset voltage) appears on
channel zero, the transconductance amplifier receives a
bias-set pulse for 5 "s. If the data is zero, this amplifier
sinks (or sources in the case of non-zero data) a current
pulse to the integrator that minutely adjusts the hybrid's
zero. At null, there is an imperceptible ± I-pulse hunt
traded off against capture time.
In a microprocessor-based system the time needed to
ANALOG
INPUTS
digitize analog data can become very long with respect
to the processor's cycle time, particularly if the dataconversion device is a reasonably priced unit. This time
difference causes all sorts of software problems that
require complex interrupt schemes to solve. But, in fact,
the delay is totally unrelated to the need for fully
updated signal data, and the data-conversion device is
Ib)
usually quite capable of generating digital data at a fast
8, Odd. and and., Charge-pump loop (a) cancels troublesome enough rate to satisfy most signal-analysis requirements.
One simple way to work around the delay is to insert a
offset errors for aU time and temperature. A twin circuit could be used
multiple-port register file between the data-conversion
to cancel gain errors also. Register file (b) creates memory location
device and the digital processor, as shown in Fig. 6b.
for HDAS-1S, so data access is independent of the hybrid's status.
Essentially, the register file creates a memory location
cation calls for a fast spectrophotometer for monitoring for a continuously scanning H DAS-16. Data access is
industrial waste or a similar cost-sensitiv·e task. Figure 5 fast, free, and independent of the hybrid's status. Thus,
shows one solution utilizing the hybrid's high-gain capa- the hybrid generates new data words at 50 kHZ and
bility and its user-adjustable settling delay time. Here, updates a 16-word file at a rate of over 3 kHZ. Meanthe outputs of 16 photodiodes, each of which has a while, the digital processor can request and retrieve data
different narrow-band filter, are compared to the output at normal memory-access speeds without disturbing or
of an unfiltered white-light reference diode. Since the waiting for the data-acquisition system.
0

I

WM

162

DATA ACQUISITION & CbNVERSION HANDBOOK

Put video aid converiers to work.
These small, inexpensive show-stoppers can digitize the
analog signals required for a variety of applications.
Video-speed, 8-bit, aid converters-particularly
those that use two, 4-bit, hybrid, flash stages'-are
now small enough and inexpensive enough to work
ih a variety of applications, including digital television, transient recording, radar-signature analysis
and distortion analyzers.
Probably the most extensive use of ultra-high-speed
aid converters will be broadcast TV; where digital
picture processing has started a revolution that is
perhaps even profounder than the transition from
tubes to semiconductors.
Though the potential advantages of digital television were obvious for some time, its potentiality
didn't become reality until compact, ultra-high-speed,
reasonably priced, aid converters and high-density
LSI memory chips appeared.
Basically, digital television-picture processing requires three major steps:
1. Digitizing the analog signal from the camera (or
other video source) using very fast aid converters.

FROM

~~~~ 0---,------1
RECORDER

8·811
AID
CONVERTER

2. Processing the converted data digitally.
3. Reconverting the processed picture data into
analog form for transmission via dla converters.
Right now, digital TV extends only to processing
video signals in studios. Digital data aren't transmitted to home receivers-yet. But the digitized video
signals do have the following advantages:
• They're immune to noise.
• They can be stored in digital form and read out
at selectable rates.
• They can be simply converted to different TV
standards.
• They can be delayed, compressed and stretched.
Video

aid stars in digital TV

From the performance viewpoint, a digital-TV
system's aid converter is the most important block.
The converter limits the system's two crucial characteristics-resolution and sampling rate. Fortunately,
8-bit resolution faithfully reproduces a TV picture. At
'iideo speed, higher resolution gets prohibitively expensive. An 8-bit converter quantizes the luminance,
or video-signal amplitude, into 2', or 256, discrete

2K' 8 BIT
RAM

8-81T
DEGLITCHEO
DIA
CONVERTER

ANALOG
VIDEO

OUT

to.74 MHz

l. Digital time-base correction systems synchronize data
converted by this video-speed. B-bit aid converter to the

local-station color subcarrier. The RAM stores up to three
lines of digitized video data.

163

levels. These 0.4% amplitude steps produce a grey
scale that appears continuous.
Today's high-speed aid converters sample at the
rates required by digital TV. The well-known Nyquist
criterion of the sampling theorem spells out the
required theoretical sampling rate (to recover a bandlimited signal without distortion, it must be sampled
at least twice as fast as its highest-frequency component). In the U.S., the National Television System
Committee (NTSC) standard is in force. The TV signal
has a 4.2-MHz bandwidth, which requires a minimum
S.4-MHz sampling rate.
In practice the sampling frequency is higher than
the required minimum, and usually an integral multiple (three or four) of the 3.58-MHz color subcarrier.
Thus, the most common sampling rates are 10.74 and
14.32 million per second.
There is another standard to consider: the widerbandwidth, European, phase-alternating line (PAL)
standard. The video bandwidth is 5.5 MHz and the
color-subcarrier frequency is 4.43 MHz. Sampling
three and four times the color-subcarrier rate means
13.29 and 17.72-MHz conversion rates, respectively. To
compare data for both U.S. and European systems,

3. Digital noise reducers store the converted frame  channel, so almost all converter manufacturers offer multiplexers that provide from 8 to 128 channels on one or
two boards. The boards can usually in terface directly
with a variety of popular mini and microcomputers.
Prices vary from vendor to vendor. Table 2 shows Datel
Systems' prices for several 8080-based A/I> converter

erage is simple. After you've summed the inputs, sim-

ply shift the sum to the right and you'll have the average. If you're averaging two points, shift right one bit;
for four points, shift the su.m two bits; for 8 points, shift
right 3. This method works because computers operate
on binary arithmetic, and each one bit shift to the right
represents a divide b) 2 operation.
Of course, if you decide to average 27 samples, the
arithmetic is no longer easy. Also. if you haw a severe

Table

2: AID converter board costs 1

Number of
channels

I

Module. required

Tolat
price

Costl
channel

16

ST -800-168 ($595)
16-channel master board
with AID

$ 595

$37.20

32

5T -800-328 ($650)
32-channel master board
With AID

$ 650

$20.30

64

8T -800-328 ($650)
32-channel master

$1065

$16.62

$1125

$14.08

$1600

$12.50

.-/

13511

LSB value

if full scale

noise problem-such as periodic high frequency noise
that prndllP.es s~verf' aliasing in the data-you may
have to write a numerical analysis program in I'ORTHA~ or BASIC to average out the beat notes. In this
case, it's better to filter with hardware.

cllstomf!rs. If YOll haVf\ or f>XPf>C't to have, a noise proh-

Total $1650
5Utf.:S~lem 1500

Best accuracy in
parts per million
(ppm)

V

1200
1050
goo

l

7511
600
4511
300
SI511

Y

8T-800ADX32S ($415)
32 channels, slave mux
expander board, no AID

/
/'
80

/

o

5T-800-328 ($650)
32-channel master

16

32

48

64

so

~

112

128

5T -800ADX48S ($4751

Number of smgle-efliled analog Input cIIanAels

48 channels, slave mux
expander board. no AID

Fig. 1: The cost per channel lor AID converter
subsystems in.creases linearly after the initial master board is purchased. If major components, such
as a printed circuit board or chassis, have to be
added, the costs can go up dramatically. Although
this figure illustrates Datel Systems components,
other manufacturers generally are within 10% of
these prices (assuming identical configurations).

128

8T -800-328 ($650)
32-channel master
(2) ST -800ADX48S ($950)
48 channel expander boards

For smgle-ended 12-M. 808D-based A/O peripherals

184

DATA ACQUISITION & CONVERSION HANDBOOK

sidering to see what their next increment is. For example, if you need 30 channels and are conSidering a
32-channel A/O from Manufacturer X, is his next increment 48 or 64 channels? Will you have to buy an entire chassis or just an expansion board if you need more
channels?
By selecting your multichannel A/0 components
carefully, you may spend a little more now, but you can
also save a great deal if you have to expand in the fu-

Cornered by success
One of our customers decided to expand an existing control system by installing a microprocessorbased data acquisition and control system at a remote site. The existing control system, a large minicomputer ac;ting as a central hos~ already had
many input channels installed with direct cables.
From past experience, we felt the customer
would probably want to add many more channels,
01 A outputs and additional remote site controllers
later on. More Importantly, we felt he should stick
with a microcomputer version of his central minicomputer. This would enable him to use common
programming languages, peripheral drivers and
communications protocols. But the customer persisted with a low-cost Brand X microprocessor,
home-brew chassis, power supply and custom programming. Ultimately, the system got working-sort

Multichannel A/n converters that offer speed, accuracy and direct interfacing to your computer are expensive, to be sure. Although we certainly appreciate
your need for economy, let me point out one rule of the
data acquisition business: Don't paint yourself into a

of.

corner!

ture.

GeHing out of the corner

The remote micro had communication difficulties
with the host mini, but the advantages of being able
to locally control the process on site had the predictable result: The plant manager was impressed
enough to authorize funding for six more remote
systems. Now the scramble began. The design engineers had to untangle th" software problems and
hand-build six more custom units.
We finally convinced the customer to switch to a
microcomputer version of his central mini. The offthe-shelf software supplied with the micro solved
his communications problems. Then we convinced
him to use "packaged" AID and 01 A systems that
come complete with power supplies and allow for
future expansion. The' happy ending was a system
that works smoothly, has room for future expansion, and can be duplicated easily for additional
applications.

Stand back from your project for a few minutes and
consider a few things. You are not simply buying a
processor, data acquisition hardware, transducers and
an output terminal. You are buying a system that will
provide useful data for a measurement or control application over a long period of time. Don't let the details
blind you into not seeing your system's function.
It is false economy to specify an 8-bit micro and an
8-bit A/D converter only to find out six months from
now that your system isn't big enough or fast enough to
handle the data. Anticipate that others may want to apply your system-or one just like it-to applications
you haven't considered. If more people begin using
your system, design limitations may beJ(in to cripple it
Something as simple as the number of wires in the
cable or the hardware/software methods for multiplexing data can come back to haunt your later on.
And there's always the unexpected. After you've had
your system running for awhile, don't be amazed if the
plant manager asks you to provide additional inputs
from a processing site half a mile away. The half mile
may seem insignificant to the plant manager, but you
have to solve tlie communications problem-perhaps
with modems, coaxial cable or a microwave unit If
your processor can't handle the additional data acquisition and communications work, you've got a problem.
This is exactly the place not to be painted into a comer
with a modest processor struggling to handle everything and no simple way to expand
Anticipate that you may not see all the ramifications
of your system design. Try to draw on the experiences
of others who have installed systems. Select manufacturers who offer a variety of systems with expandability
features. and don't buy a processor or an A/D input system on price alone. If you plan for future problems.
maybe they won't be problems. •

modules. Figure 1 is a graph of cost vs. channel capacity, so you can get a general idea of how much the A/D
peripherals will cost for your particular application.
Some companies offer a variety of channel expansion
methods, but the variety is not infinite. For example, if
your system has reached capacity and you want to add
a few more input channels, the manufacturer will have
to charge you for the next increment of channel expansion-which may be many more channels than you
need. Channel expansion is usually in increments of 16,
32 or 48 channels.
Many customers are concerned about the additional
cost of A/O channels and want to specify only the capacity that they need. While this is a good idea, be sure
you don't limit yourself. Keep in mind that you will
probably think of some other parameter that needs to
be measured (if you don't think of it, someone else
will~

If your calculations say that you need a certain number of channels, check the manufacturers you are con-

LC

185

Application of Analog Conversion
Products in Micro-computers
Introduction
A great many of the applications employing microcomputers also require some form of analog input
or analog output.' It is estimated that 37% of all
computer aPl)lications require some form of analog
I/O. The majority of these application areas can be
classified as Data Measurement/Collection or Process Monitoring/Control.
Since most sensors ami control elements are analog
in nature, it is obvious that in areas where measurement and control are required, analog signals are
most likely to be present and, therefore, must be
generated (D-A's) or measured (A-D's).
The actual application determines both the type
and number of analog signals involved. In some
process control or process monitoring applications,
hundreds of control points are being continuously
measured. In these applications, the Data Acquisition System is more likely to be a rack mounted
system separate from the computer. In other less
complex systems, the number of analog signals
would be in the area of 4-100 points. Micro-computer
systems tend to be smaller in scope; and it is these
type applications that are being. considered here.
Fewer analog channels allow having the analog
circuitry located directly on the same P.C. board
as the I/O interface logic. This resulting unit is
treated as a standard I/O peripheral and is offered
hy several manufacturers in many different versions
with each version capable of providing many different options.
These peripherals are offered in the following
versions;
a. Analog-in IA-D only) with 8-64 channel input
capability.
h. Multiplexer expander units for applications
requiring additional analog channels.
c. Analog-out ID-A onlyl with from 4-8 channel
output capability.
d. Analog-out expander boards for multi-channel
analog out capability.

e. Combination A-D/D-A units with 8-32 analog
input and 1-4 analog output channels.
Of applications having some form of analog in/out,
45% have analog-in only, 15% have analog-out only
and 40% require both analog input and analog output
peripherals. The number of analog output channels
may be superficially inflated, as in some applications,
they are merely used for self-testing or calibrating
the A-D section. At other times, th" D-A's are used
only to reproduce selected analog input channels
on a strip chart recorder or CRT.
Typical optional features are listed below:
a. Single ended or differential analog inputs.
b. Current loop (i.e. 4-20mA) inputs.
c. High level analog inputs (0 to +5V, 0 to + lOV,
±5V, ±lOV).
d. Low Level (l0-100mV full scale) analog inputs
requiring instrumentation amplifiers with
gains of 100-1000.
e. Amplifier with software programmable gains
of 1, 2, 4, and 8.
f. Operation under program control, program
interrupt or DMA.
g. With or without DC to DC converter to generate ±15 volts power (from +5V supply) for
analog circuitry.
h. Simultaneous sample and hold circuits on
analog input channels.
i. Different full scale voltage ranges on analog
outputs.
j. Current loop (4-20mA) on analog output
channels.
The actual applications described in this paper were
selected as typical of those peculiar to microcomputers. These applications may not have been
feasible, economically or otherwise, to have been
accomplished using a mini-computer. Additionally,
the applications were selected depicting different
versions and options of the analog I/O peripherals
and their employment in different application areas.

186

DATA ACQUISITION & CONVERSION HANDBOOK

Energy
Monitoring Operating Status of
Reactor During Power Station Start-Up
Putting a reactor on-line at a nuclear power station
requires a precise procedure with detailed information on the operating condition of many devices.
This information must be available at all steps of
the start-up procedure.

NUCLEAR
REACTOR

!

TEMPERATURE. PRESSURE.
WATER FLOW. ETC.

!

SIGNAL CONDITIONING

J

150 ANALOG INPUT CHANNELS

1.

DATEL SINETRAC ANALOG INPUT
MICRO-COMPUTER PERIPHERAL

t

I

DMA CONTROLLER

I

MICRO-COMPUTER

t
t

I

I

L DIGITAL 1/0 CONTROLLERS I

l

The measurement system operated in t\\'o modes:
H. A slow sean mode to sense long ttlI'm trt-'nds
\\-'here eC:leh sensor was measul"(.'d four timl's
per hour.
h. A fast scan modl' to look at primary impor'
tant sensors during start-up 01' wlll'n taking
the reador off-line.
The reactor vt'ndor desil'l'd to opl'rall' till' unit in
a DlVIA mode to poll all units quickl>' and tlll'n
release the machinl' to perform othl'r control fune·
tions. The Datel analog I/O boards I ST·HOO-:l2S I
were capable of being operated in DlVIA and the
ST-800-ADX boards allowed for expansion to 150
channels in increments of 4H channels pt'r hoard.
This application was as a monitoring station for
operator information only and was not used as a ('ontrol system as there was no fel'dbaek to til<' system.
While the primary function of this systt'm was for
monitoring purposes when putting the reador on
or off line, it is now being evaluated as a monitoring
system during power station operation. It is t'xtremely important that equipment repair or replacement be performed during scheduled maintenance
periods.
If the system is monitoring a group of pumps. and
detects excessive wobble on one pump shaft. maintenance personnel can be alerted to replace or repair
the pump during the next scheduled maintenance
period. If it failed, causing an unscheduled shutdown, the power plant would have to decrease the
amount of power it could be depended upon to
supply the grid.
By using micro-computers, these monitoring stations can be dedicated to specific groups of equipment and could be spread out over the power station.
Employing the monitoring system in this manner,
can be proven to be extremely cost effective.

"MONITORING STATION"

Aviation

CRT TERMINALS, HARD COPY
PRINTERS, ALARM SIGNALS

ENERGY

In this application, it was necessary to monitor the
status of 150 points. The physical parameters being
measured were temperature, pressure, and water
flow. The Reactor Vendor chose to use a microcomputer for cost reasons and because the power
of a mini was not warranted. The outputs of the
transducers were connected to a Signal Conditioning
Unit which generated analog voltages in the 0 to
+10V range for inputting to the measurement
syswm.

Digital Flight Controlled Simulator
This system was developed by the Redundancy
Management Laboratory of BlVIAD (Boeing Military
Airplane Development!. The application illustrates
a system that employs both mini and microcomputers. The Data General NOVA mini-computer
was used for central processing and an Intel
SBC-80/1O was used for distributed I/O.
This research effort was to investigate system
problems associated with r"dulldollt high reliability
digital flight control. As a result of using redundant
controls for higher reliability operation, two sets
each of NOVA's mini-computers, SBC-80's microcomputers and Datel SineTrac analog I/O peripherals. were employed.

187

The analog I/O peripherals were connected to an
airframe simulator consisting of an analog computer,
actuators, and a two axis platform on which sensors
were mounted. The system contained 6 analog outputs (D-A's) and 18 analog inputs. The outputs
entered an analog computer which drove aircraft
actuators connected to the 2 axis platform. The
actuators were dual with selection clutches for
operation under control of one redundant system
or the other.
An operator station is associated with each minicomputer, whereby the operator may input commands to the system to have the system simulate
an abrupt altitude change from one position to
another. The system would simulate this, via programs in the mini-computer, and measure changes
from the sensors mounted on the simulator and
generate commands (analog signals) to the simulator
to stabilize the airirame.
The data acquisition system samples analog inputs
from the simulator which are representative of the
following:
a. Roll information from vertical gyros.
b. Pitch information from vertical gyros.
c. Roll rate from rate gyros.
d. Pitch rate from rate gyros.
e. Altitude information simulated from the
analog computer.
f. Engine speed information simulated from the
analog computer.
The micro-computer does some prescaling and limit
checking on the data and sends the results to the
mini-computer for processing. The mini-computer
contains a full set of flight control equations and
after processing the data transmits information back
to the micro-computer for stabilizing the simulated
airplane.

The micro-computer does some error checking on
the data received and outputs to the micro-computer analog output peripheral (D-A). The output of
the D-A's contain pitch, roll and throttle information which enter a small analog computer which
drives the dual actuators controlling the 2 axis
platform.

Manufacturing
Automatic Production Test Equipment
This system monitors the status of 64 products
under life test. It can scan 64 similar products at
preset time intervals outputting to the operator
a hardcopy printout and a visual display of each
product's status as it is scanned. Alarm levels are
set to flag an item that is out of tolerance.
The parameters being measured are from photoceils
and pressure and temperature sensors. The signal
conditioning section performs two functions:
a. Amplifies the low level (20mV full scale) input
to high level (lOV full scale).
b. Isolates and ground references the signals that
had high common mode voltages (up to lKV)
or contained noise spikes of up to 150 volts.
The sequencing logic allows the data logger to
make multi readings as each product is individually
scanned. At each dual point the sequencer allows
several conditions to be read and outputted to the
logger. Timing and data channel number information
is provided by the microprocessor to the sequencing

PITCH, ROLL,
ROLL RATE, PITCH

RATE, ALTITUDE,
ENGINE SPEED

ANALOG COMPUTER
DUAL ACTUATORS, TWO AXIS PLATFORM
VERTICAL GYRO'S, RATE GYRO'S, POSITION POTS.

MICRO-COMPUTER CONTROLLED PRODUCT LIFE TEST SYSTEM

MANUFACTURING

AIRPLANE SIMULATOR

188

DATA ACQUISITION & CONVERSION HANDBOOK

logic. The sequencer allows the data to he moni·
tored as various loadin~ and stress effects are
chan~ed on the product under life test. In actuality,
64xN readin~s can be taken, where N represents
the number of indexin~ steps of the load sequencer.
The microprocessor multiplexin~ technique was
utilized because of the off-the-shelf availability of
compatible products, namely, the Intel SBC-80/l0
Sin~le Board Micro-computer and the Datel SineTrac 800 Series Analo~ I/O System. The in-house
availability of a micro-computer software development system and a PLIM hi~h levellan~a'g-e
compiler allowed us to turn around software for
this system. rather rapidly.
The block dia!-,'Tam at the upper ri~ht hand corner
of this pa~e depicts the component parts of the
system.

PROCESS UNDER CONTROL

MICRO-COMPUTER

PROCESS CONTROL SYSTEM

Process Control
Local Microcontrollers Return
Control to Process Site
This is a process control application for a materials
manufacturer who is measurin~ 53 channels of temperature, pressure, line speed and other types of
process data. Low level analo~ si~nals from the
sensors are si~nal conditioned by external instrumentation amplifiers to present hi~h level analog
signals to the Datel SineTrac Data Acquisition analog input peripheral unit (ST-800-32S). Additional
high level analog channels (channels 33-53), are
entered through a Datel analog channel expander
board (ST-800-ADX). Low level signal input ranges
were up to 50m V full scale and each had a bandwidth of less than 20Hz.
The analog channels are selected and digitized under
control of the Intel Micro-computer (SBC-80/l0).
The micro-computer performs some computation
and processing operations on the digitized analog
data and some switch position inputs. The microcomputer outputs in two ways:
a. It generates 20 analog signals via D-A converters located on Datel analog output peripheral boards (ST-800-DA8). These analog
outputs drive actuators in the manufacturing
process to complete the real time, computer
aided process control loops.
b. Additionally, the ('omputer outputs data to a
local monitoring station. Process status is displayed in the form of bar graphs on a color CRT
as well as to some di~ital meters displaying
several process variables in engineering units.
By using local micro-controllers at different sta~es
of the process (versus a large remote main frame
controlling the whole process), several a-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--'

MUX AOOR
CHECKSUM
STOP BIT

!;.ONTROL

OB = 0 OON-T PROGRAM OUTPUTS WITH 012-015.
DB = 1 DO PROGRAM OUTPUTS WITH 012-015.

ADDRESS
00·07 ADDRESSES ONE OF 256 REMOTES

1/0
IF 08 = 1. BITS 012-015 WILL BE
REMOTE-S DIGITAL OUTPUTS
PROGRAMMEO AT THE
TO ADDRESS THE MULTlPLH

Fig 5 Remote receive structure, 24-bit command format. Format contains address, control, and 110
data. Anyone of 256 remote stations can be addressed with one of four valid control words plus four
bits of 110 information

will respond with such data as status, I/O, and transducer information, the type of response being determined by the command message. Data integrity is
maintained by the use of a 4-bit checksum in the 24-bit
message format and an 8-bit eRC r_emainder in the
44-bit message format. Both remote station and receivertransmitter append the error checking bits to the end

of the message before transmitting. Upon reception of
a message, the same error checking bits are used to
detect transmission errors. In the event of a command
message error, the receiver-transmitter is alerted immediately by completion of a receive data time-out.
The addressed remote station receiving the command
message in error does not return a status or data

205

DO Dl D2 D3 D4 D5 D6 D7 D8 D9 Dl0DllD12D13D14D15

ADC READING
DO-Dll REPRESENT 12-BIT DUAL SLOPE ANALOG TO DIGITAL CONVERTER
BINARY OUTPUTS RETURNED AS REQUESTED IN COMMAND MESSAGE SENT
BY RECEIVER-TRANSMITIER

BITS LABELED "T" ARE TRANSPARENT
TO USER'S SOFTWARE.

110
D12-D15 REPRESENT STATE OF FOUR liD LINES USED IN MULTIPLEXER
ADDRESS INFORMATION IN EXAMPLE OF FIG. 5

Fig 6 Remote transmit structure, 24-bit data format. Format contains ADC and 1/0 information. This message format is used by addressed analog remote station as response to send ADC and 1/0 data

DO Dl D2 D3 D4 D5 D6 D7 D8 D9Dl0DllD12D13D14D15

STARTBIT
BIT
24144
TXIRC BIT

~~.
~

I

"

I '

~jli!AADDR ~>----_-----'
ECHOED
CHECKSUM
STOP BIT

)

ADDRESS
BITS DO-D7 REPRESENT REMOTE'S ADDRESS.

.

09

D10

011

1/0

o

FUNCTION
STATUS OK

BITS D12-D15 REPRESENT STATE OF FOUR liD
LINES PREVIOUSLY PROGRAMMED.

LAST WORD RECEIVED BEFORE STA lUS ReQUEST RECOGNIZED HAD AN ILLEGAL
24/44 BIT SETTING OR LAST WORD WAS FROM ANOTHER REMOTE
LAST WOAD WAS NOT RIGHT ADDRESS tDO·071.

POWER FAIL
IF D8·· "1;' POWER FAILURE HAS OCCURRED
AT REMOTE SINCE LAST STATUS REQUEST.

LAST WOAO RECEIVED HAD CHECKSUM OR FRAMING ERROR

Fig 7 Remote transmit structure, 24-bit status format. Contains address, status, and 1/0 information.
This message format is used by analog remote station in response to status request

message, thus allowing the receiver-transmitter to timeout and alert the host computer.
Figs 5 to 7 show three unique structures within the
24-bit message format that allow efficient communication between host computer and remote station, remote
station hardware consisting of a 12-bit ADC buffered
by a 16-channel analog multiplexer. The three formats are remote receive command (Fig 5), remote
transmit data (Fig 6), and remote transmit status (Fig
7). The remote receive command format, when sent
to the selected remote, produces one of two responses:
data or status. Purpose of the command message is to

select the remote station, tell it how to respond, and
then to program its digital I/O. This type of communication between host computer and remote is half
duplex. After the command message is received by the
addressed remote and no transmission errors are detected, the command message is executed, and the
appropriate response is transmitted back to the host
computer.
The first eight bits of nontransparent data in the
command message (Fig 5) are address bits used to
select the remote station in question and allow for
addressing up to 256 remotes. Next are four control

206

bits which dictate the remote response, followed by
four bits of digital I/O used to program the analog
multiplexer. The remaining eight bits are user·transparent control bits that are common to all three
structures, and required to support the protocol framework. These are the start, stop, 24/44, TX/RC, and error
checking bits. Transparency is important in maintaining
low software overhead on the part of the user, to assure
greatest possible throughput and ease of implementation. The remote data response (Fig 6) is the most
often used of the two remote transmit formats; it contains the latest conversion and I/O information. Status
response (Fig 7), on the other hand, is used primarily
for system diagnostics; however, it may also be used
as a means to obtain additional data integrity when
programming the remote I/O lines. When a remote's
digital I/O is programmed with a request status command, the resulting remote response contains address
conformation, digital I/O echoing, transmission line history, and power-fail indication; an excellent way to
obtain high security communication.
The party line concept allows for configuration of a
data acquisition and control system, in which the
efficiency of the message format for each station is
maximized, resulting in a minimum of hardware and
software support while providing a viable system
capable of high data throughput.

task of the host computer is to collect and process
thousands of temperature readings in order to efficiently
control the building's air conditioning and heating
systems at reduced cost. In a data acquisition system
of this magnitude, where several thousand points must
be continually monitored, it is important to maximize
the throughput rate while keeping the cost per data
point low. Implementation of the 24-bit message format
with a single-chip microcomputer and a dual-slope
AOC (OSAOC) makes this possible. The microcomputer
is programmed to control the OSADC and to communicate with the party line system by means of the 24-bit
message format. Use of an IM80C48 microcomputer and
an ICL 7109 DSADC allow for protocol emulation at a
rate up to 4800 baud, resulting in a sampling throughput of approximately 100 points/s; the only speed
limitation results from the microcomputer's inability to
execute software any faster.
A receiver-transmitter completes the serial communication link by supporting the 24/44·bit protocol
and providing the host computer with the proper interface. Its primary function is to support the protocol
and provide all necessary handshaking signals for
proper interfacing. Required signals include transmitter buffer load, data received, transmitter register ready,
receiver error, overrun error, and time-out error. Since
this block resembles a standard UART, it interfaces
easily to most computers. All that is necessary is a
simple parallel interface to the host computer data
bus. It would also be relatively easy to use yet another microcomputer along with the receiver-transmitter to allow the party line system to connect
directly to a standard Rs-232 interface. This would
greatly simplify interfacing requirements of the 24/44bit serial protocol to the host computer. Fig 9 shows

Fig 8 s!.ows an energy management application for
a serial party line data acquisition and control system,
where the primary design goal is to monitor and control temperature conditions within a large building. Major

1·256 REMOTE ANALOG STATIONS
24-BIT FORMAT

1-16 CHANNELS OF
TEMPERATURE DATA
1-4 DIGITAL 1/0 LINES

RECEIVER
TRANSM IHER

HOST
COMPUTER

PARALLEL
INTERFACE

J

'-----S-E-R-IA-'L PARTY LINE
TWISTED PAIR

J
1·256 REMOTE DIGITAL STATIONS
44·BIT FORMAT
UP TO 32 BITS DIGITAL 1/0
FOR CONTROL OF AIR
CONDITIONERS/HEATERS
HIGH DATA INTEGRITY

Fig 8 Energy management application. Host computer requests temperature data from analog remote
stations. Receiver/transmitter sets up protocol handling and data integrity. Computer analyzes temperature data and supplies control information to both analog and digital remote stations

207

SERIAL
PARTY LINE
TWISTED PAIR
TO HOST
COMPUTER

UART
IM6402

MICROPROCESSOR

1

1085

MICROCOMPUTER
2
IMIOC41

Fig 9 RS-232 serial interface for party line receiver/transmitter. Microprocessor 1 controls local bus
and processes data to and from host computer using UART. 'RAM is used to store up to 512 command
messages. These are transferred sequentially to microcomputer 2 which controls serial party line. Data
returned by microcomputer 2 are stored in RAM for transmission to host upon request

a possible configuration. The microcomputers are used
to split the required processing duties in order to
maintain high efficiency and maximum data rate. This
particular system would be able to accept up to 512
commands, store each one in memory, and execute the
commands sequentially over the 241M-bit party line.
After execution, remote data and status information
received by ~icrocomputer two would be stored in
the memory of microcomputer one for transfer back
to the host computer. This would allow the host computer to dump a series of commands, at high baud
rates, to each of many unique party line systems. When
ready, the host could retrieve the packed data for
processing or storage and download the next series
of commands (distributed multilevel processing).

applications involving serial data acquisition. Versatility and modularity, along with CRC error checking
capabilities, make a serial protocol an attractive and
inexpensive approach to party line data acquisition and
control.

1. F. M. Ingels, In/ormation and Coding Theory. Haddon Craftsmen, Pa. 1971
2. Hewlett·Packard. Guidebook to Data Communications. Hewlett-'Packard Co. Santa Clara. Calif. 1977
3. A. J. Wei.sberger. Data Communications Handbook. Signetics.
Sunnyvale. Calif. 1977

ES JP

Need for a serial digital data link between transducer
and host computer in a data acquisition system has been
demonstrated as a solution to many of the problems
inherent in the classical system. The serial link provides ease of implementation, substantial reduction in
cost per data point, and increased length of transmission
line. However, inefficiencies exist in bit- and byteoriented protocols for data acquisition and control.
'CRC catches all 1-, 2-, and 3-bit errors, random bit
errors, and burst errors. It can be implemented in software to run efficiently in a microcomputer based communication protocol requiring a sophisticated error detection scheme. Comparisons of efficiency vs throughput
for several existing protocols-Bisync, SDLC, HDLC, and
packed ASCII-show varying values. Packed ASCII, even
though moderately inefficient, is the best suited for

208

4. Sample-Holds

209

210

Designing with a sample-hold won't be
a problem if you use the right circuit

S

ample-hold circuits are widely used in analog
signal-processing and data-conversion systems to
store an analog voltage accurately over periods
ranging from less than a microsecond up to several
minutes. This capability suits them to numerous
applications including data-distribution systems,
data-acquisition systems, simultaneous sample-hold
systems, aid converter front ends, sampling oscilloscopes and DVMs, signal reconstruction filters,
and analog computation circuits.
Although sample-holds are conceptually simple,
their application is full of subtleties. In general,
applications that need only slow to moderate speed
and moderate accuracy generate few problems, but
high-speed, high-accuracy applications are the ones
that need careful design. An example of the latter is
taking a 10-V sample in one microsecond or less with
0.01% accuracy.
To select the right sample-hold for a particular job,
and apply it properly as well, requires understanding
the intricacies of its design and operation.

the capacitor retains this charge and thus holds the
desired voltage for a specified period.
There are three important sets of terminals in a
sample-hold circuit: the analog input, the analog
~

5

~

c\

SAMPLE

CONTROL

A2

~:'+l

~

t::\

~

'" ~

SAMPLE

CONTROL

fb\
\.V

1. In a basic sample-hold circuit (a), the switch closes to
sample the input Voltage. When the switch opens, the
capacitor holds the voltage. A practical circuit (b) has
unity-gain buffers to charge the capacitor without loading
the source and to drive normal loads without changing
the voltage stored by the capaCitor.

Basically speaking

A sample-hold circuit is fundamentally a "voltage
memory" device that stores a given voltage on a highquality capacitor. The circuit can take a voltage
sample and then "freeze" it for some specified period,
while some other circuit or system uses the voltage.
Fig. la shows a sample-hold circuit in conceptual
form. An electronic switch is connected to a hold
capacitor so that when the switch closes, the capacitor
charges to the input voltage. When the switch opens,

2. A sample-hold can operate In two different way•. It can
take a quick sample of the input and return right back
to hold mode (a), or it can track the input for part of the
time and hold it for the rest (b).

211

DATA ACQUISITION & CONVERSION HANDBOOK

output, and the sample control terminals. Fig. 1b
shows a practical circuit that includes input and
output buffer amplifiers and a switch-driver circuit.
The sample control input closes the switch for sample
mode, or opens it for hold mode.
The sample-hold input terminals are usually the
input of a high-impedance buffer amplifier since in
most applications, such as operating at the output of
an analog multiplexer, the source shouldn't be loaded.
Likewise, the output has a low impedance so that the
sample-hold can drive a load such as an aid converter
input. The output buffer amplifier must also present
a very high input impedance, and very low bias
current, to the hold capacitor so that its charge doesn't
leak off too rapidly. In virtually all sample-hold
designs, therefore, this amplifier has a junction-FET
input stage. Similarly, the switch must be fast and
have very low off-state .leakage.

circuited inductor is hard pressed to give a selfdischarge time constant (L/R) as high as 10 seconds,
while a capacitor can give a time constant (Re) of 10·
seconds. (The only exception, a superconducting induc-

o

2T

4T

6T

8T

lOT

1~~l~ER~D D~UT

J:''\

~,

AVERAGED OUTPUT (IDEAL)

,....

Sample-hold: An energy storage circuit

All sample-holds are basically accurate energy
storage circuits. Since the hold capacitor is a key
component in an accurate sample-hold, a fundamental
question to be answered is: Why use a capacitor to
store the energy?
It turns out that certain types of capacitors very
nearly approach the ideal. They have extremely low
leakage, and therefore very high equivalent parallel
resistance. This resistance, commonly specified in
megohm-microfarads and known as insulation resistance, is the parallel resistance of a one-microfarad
capacitor and is numerically equal to the self-discharge time constant of the capacitor in seconds.
To find the parallel resistance for other capacitor
values, divide the insulation resistance in megohmmicrofarads by the capacitance in microfarads. Since
the parallel resistance. can be quite high for smaller
value capacitors, most manufacturers specify a maximum "need not exceed" value, generally twice the
insulation resistance. This means only that the parallel resistance is not measured or guaranteed by the
manufacturer. It may well be as high as calculated.
The self-discharge time constant is the length of
time required for an open-circuited capacitor to discharge to 36.8% {)f its charged voltage. High-quality
capacitors used in sample-holds have insulation resistance as high as 10" megohm-microfarads,
equivalent to a self-discharge time constant of one
million seconds, or 11-1/2 days. In other words, this
is only 1% droop in almost three hours.
To get back to why capacitors are used for the energy
storage, they approach the ideal much more closely
than the alternative, which is an inductor. The figure
of merit for an energy-storage element is its selfdischarge time constant. A high quality short-

2T

2T

ORIGINAL SIGNAL

4T

4T

6T

8T

6T

8T

lOT

lOT

3. A zero-order hold reconstructs an analog signal that's
been transmitted as a series of pulse samples (a). It does
so by holding the amplitude of each pulse to fill in the
spaces between them (b). Practical averaging uses a lowpass filter (c) that has more delay than the ideal averaging
shown in (b).

IGol f II
GAIN

4. The lain response of a zero-order hold (a) in terms
of the sampling frequency f, takes the form of the absolute
value of (sin xl/x. The phase response (b) is linear because
of the constant time delay.

212

I
I

~

r- ~

r-

r:::-

\

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f'\.

F-

2T

:I

t-

4T

ZERO - ORDER HOLD

6T

~

8T

o

CD

/ k r-

'~

~

\

2T

4T

6T

FtRST -ORDER HOLD

5. Three types of holds reconstruct an original signal
(dashed curve) differently. The output of a zero-order hold
(a) is steady between samples. A first-order hold (b)
extrapolates a new slope that's proportional to the dif-

8T

o

(c)

i
2T

I I
4T

6T

8T

POLYGONAL HOLD

ference between the two most-recent samples. Its output
error is zero during constant-slope portions of the signal.
The polygonal hold (c) interpolates between the two most
recent samples.

in the term "sample-hold," as just about all sampleholds can also track and hold. The few circuits that
can only sample for a short time, and cannot track
the input, are clearly labeled this way.
To appreciate the difference between true samplehold operation and track-and-hold operation, see Fig.
2. In Fig. 2a, a sample-hold periodically takes a sample
of the input, a sinusoid in this case, and holds it for
the rest of the time. In Fig. 2b, a track-and-hold tracks
the input for part of the time and holds it for the rest.
Here, the track time and hold time are equal.

tor, would, of course, be better than a high quality
capacitor, but it would be difficult to package in an
ordinary sample-hold circuit!)
Capacitors of certain types are therefore clearly
superior to inductors when it comes to approaching
the ideal. Acceptable types of capacitors include
polystyrene, polycarbonate, polypropylene, and
Teflon. In addition, MOS capacitors are excellent for
hybrid circuit sample-holds.
Two other storage elements useful in specialized
sample-holds are an electrochemical cell such as the
Plessey Electro-Products E-Cell, and a register that
holds the voltage digitally.
Sample-hold circuits are variously called zero-orderholds, track-and-holds, or sample-and-hold amplifiers. Although these terms are generally used interchangeably today, some technical distinctions
should be pointed out.
Strictly speaking, a sample-hold takes a very fast
sample and then goes into the hold mode. This means
that the switch closes for only a very short period of
time, usually because a pulse transformer drives the
switch. A track and hold circuit, on the other hand,
can track the input with the switch closed indefinitely
and then go into the hold mode upon command.
A zero-order hold may be either a sample-hold or
track-and-hold. When a device is called a zero-order
hold, that means it's used as a signal recovery filter.
There are various types of sample-hold recovery filters
such as zero-order holds, first-order holds, fractionalorder holds, and polygonal holds.
The term "sample-and-hold amplifier" can refer to
either a sample-hold or a track-and-hold, and originates from the fact that operational amplifiers are
used to make sample-hold circuits.
Although there's a technical distinction between the
terms sample-hold and track-and-hold, it's automatically assumed that both functions are included

Zero-order hold

An important sample-hold application is reconstructing, or recovering, an analog signal that has
been transmitted as a train of pulse samples, like those
in Fig. 3a. To reconstruct the original signal waveform, a sample-hold, or zero-order hold, retains the
peak value of a sample until the next one arrives, thus
filling in the spaces between them, as in Fig. 3b. The
result is a reasonable reconstruction of the original
signal before it was converted to a pulse train. Ideally,
the average of the reconstructed waveform, shown
dashed in Fig. 3b, is a near-replica of the original
waveform, delayed by half the sampling period, T.
If the staircase waveform of the output is objectionable, a low-pass filter following the zero-order hold
will smooth the waveform further. This filter will add
further phase delay, but the resulting reconstruction
of the original signal is much better, as Fig. 3c shows.
The cutoff frequency of this filter must be determined
from the sampling rate and the bandwidth of the
signal to be recovered. The lower the cutoff frequency,
the better the smoothing.
The zero-order hold is a type of filter. As with other
types of filters, its gain-phase characteristics are
important to know. These gain and phase terms are

213

DATA ACQUISITION & CONVERSION HANDBOOK

plotted in Fig. 4. The zero-order hold is obviously not
an ideal filter with its (sinx)/x amplitude response.
Nevertheless, it reconstructs signals respectably. Its
gain is slightly more than 3 dB down at a frequency
of f,/2, and it again goes to zero at integral multiples
of the sampling frequency, f. There are some undesirable gain peaks at frequencies of 3/2 f" 5/2 f .. etc.
These peaks are frequently attenuated by a low-pass
filter following the zero-order hold. A zero-order hold
as a filter has a perfectly linear phase response (Fig.
4b), which results in the constant phase delay of T/2
for the output signal.
There are also more-sophisticated recovery filters
than the zero-order hold circuit. These higher-order
hold circuits, known as first-order holds, second-order
holds, etc., reconstruct a signal more accurately than
a zero-order hold (Fig. 5). A first-order hold does this
by retaining the value of the previous sample as well
as the present one. It then extrapolates from existing
data to predict the slope to the next sample, which
hasn't arrived yet (Fig. 5b). When a new sample comes
in, it generates a slope proportional to the difference
between this sample and the previous one. If the slope
of the original signal hasn't changed much, the resulting error is small; for a constant slope, the error is
zero. When the original signal reverses its slope
quickly, the output "goes the wrong way," causing a
fairly large error for one sample period.
An interpolative first-order hold, also called a
polygonal hold, reconstructs the original signal much
more accurately. This circuit also generates a line
segment with a slope proportional to the difference
between consecutive samples, but rather than extrapolate into the future, it interpolates between
samples already received. Its accuracy is achieved at
the expense of a delay of one sample period, which
is necessary because a new sample must arrive before
the line segment can be generated by starting from
the previous sample.

INPUT

,.., BUFFER

INPUT

I

"

~+I/:'

RI

2'

1/

OUTPUT

(0
C,

INPUT

"I

0----1

1

' .....

RI

,/

5k

+1

c'

OUTPUT

G
6. This type of inverting, closed· loop circuit is both
accurate and simple.The charge time constant. R,C H • of
the basic circuit (a) is much too long for some applications. The current booster in (b) speeds up charging
considerably. The input resistance, R" may be too low for
some sources; the buffer raises it a great deal.

constant is 4 /lS. To reach a value within 0.01% of the
input requires about nine time constants, or in this
case, 36 /lS.
Speed can be improved considerably, as shown in
Fig. 6b, by adding an amplifier with current gain,
inside the feedback loop. The operational amplifier
must also be able to supply this current to the
capacitor. Since these amplifiers have low output
resistance, the circuit's time constant is much lower.
For example, with the same valued capacitor and an
amplifier output resistance of 20 fI, the time constant
is only 40 ns rather than 4 /lS. Now, only the amplifiers'
output current capability limits charging.
With a maximum output current of 20 rnA from
this amplifier to charge the capacitor and a 40-ns time
constant, the capacitor takes just 1.2 /lS to charge to
within 0.01 % of final value. This is much faster than
the 36 /lS for the previous circuit. Note that in the
latter case, Fig. 6b, R, and R. can be larger since R.
no longer determines the charging time constant.
An input buffer amplifier improves this circuit
further by boosting the input resistance to a much
higher value than that of the input resistor R,. In fact,
the input resistance can be as high as 10' to 1012 ohms.
Such high resistances are required when a samplehold follows an analog multiplexer. In this case the
buffer amplifier must be fast, since its settling time
becomes part of the time required to charge the
holding capacitor. The buffer can also be added to the
circuit of Fig. 6a. Both sample-holds in Fig. 6 are
referred to as closed loop, since the capacitor charging
takes place within a closed loop circuit.
Fig. 7 shows a noninverting closed-loop sample-hold
in which A" that is serving as both an input buffer
amplifier and an error-correCting amplifier, compares
the output voltage to the input voltage, then charges
the holding capacitor until this error is reduced to zero.

Lots of circuit variety

Sample-holds come in many different circuit configurations, each suited to different speed and accuracy requirements. It's important to know the
common configurations and how they operate to
choose the proper type and apply it properly.
One configuration is popular because it's accurate
and simple. This circuit, shown in Fig. 6a, has a gain
of -1 since R, = R,;'however, making R,larger than
R, gives inverting gains larger than one. When the
switch closes, hold capacitor CH charges to the negative of the input voltage. The switch opens after the
capacitor has acquired' this voltage to the desired
accuracy.
Although potentially very accurate, this circuit is
not a fast sample-hold. The capacitor charges slowly
since it has a time constant of R.C H; with practical
values such as R. = 2k and CH = 2 nF, the time

214

Amplifier Al also gives this circuit a high input
resistance.
Thanks to the error-correcting feedback in this
sample-hold, A. need not be very accurate so long as
its gain is roughly unity. Resistor R isolates the output
of A, from the input of Al during hold mode.
This circuit is both fast and accurate; how fast it
charges the capacitor depends on the speed of Al and
its output current capability. Two back-to-back diodes
clamp AI's output to its negative input so that Al
remains closed-loop stable when the switch is opened.
Note that in this circuit the switch must float up and
down with the input voltage, whereas in the circuits
of Fig. 6 the switch always operates at virtual ground.
Operational transconductance amplifiers
Fig. 8 shows another type of sample-hold circuit,
which is versatile and can be operated in a number
of closed loop configurations. This circuit is an operational integrator that can be enclosed in the feedback
loop of AI. In this case, however, Al is an operational
transconductance amplifier; that is, one that produces
an output current proportional to its input voltage.
The current charges the holding capacitor while the
integrator's input remains at virtual ground.
In this circuit, the two switches operate out of phase.
Switch S, closes to sample, then S, closes to reduce
hold-mode feedthrough when S, opens again.
This circuit can be connected in different ways as
a closed-loop sample-hold: Fig. 9a shows the most
commonly used connection, a non inverting samplehold with a gain of +1; Fig. 9b shows the non inverting
connection with gain, and Fig. 9c shows the inverting
connection with gain.
Both of the switches in these circuits operate at
virtual ground, an advantage in driving the switch and
producing an accurate output voltage. This circuit has
been successfully used in monolithic, hybrid, and
modular sample-hold devices.
Another popular noninverting, unity-gain circuit is
shown in Fig. 10. It's basically the same as the one
shown in Fig. 1b, with two unity-gain buffer
amplifiers. This type of open-loop sample-hold is
commonly used in ultra-fast designs. In this case, a
pulse transformer drives a fast diode bridge switch.
Normally, the supply voltage back-biases the diodes.
Sampling is done by a fast-rise command pulse that
turns on the diodes to charge the hold capacitor from
the input buffer. Using ultra-fast buffer amplifiers
and an appropriate diode-gate switch, such sampleholds can charge the hold capacitor to a full-scale
change in as little as 30 nanoseconds. Because of the
open-loop configuration, there is no problem with
phase delays from output to input caused by a feedback loop. This means that the circuit is both fast and
stable.

7. Closed-loop sample-holds can also be non inverting. In
this configuration. Al is both an input buffer and an errorcorrecting amplifier. When the switch closes. current from
A, charges the hold capacitor until the output equals the
input. The pair of diodes clamps A,'s output to keep it
stable when the switch is open.

5'

8. Several closed-loop sample-hold configurations can be
built around this circuit, shown without its feedback
connections. Basically. it's an operational integrator driven by an operational transconductance amplifier, A,.

The input buffer in this circuit is difficult to design,
for it must be both fast and stable while driving the
hold capacitor load. Sampling switches, however,
cause no such problems.
The basic sampling switch circuits commonly use
junction FETs, MOSFETs, D-MOS FETs, and diodegate switches. All of these can be both fast and
accurate. The FET-type switches have the advantage
of zero offset since they are purely resistive in the
closed state. The diode-gate switch does have an offset
voltage, however, which is minimized by properly
matching the diode forward-voltage drops.
The infinite-hold circuit
All sample-hold circuits have the problem that once
they are in the hold mode, the charge will gradually
leak off the hold capacitor due to switch leakage,
capacitor leakage, and output amplifier bias current.
It was mentioned previously that a digital register can
store a number equivalent to a voltage value as long
as necessary.
The "infinite hold" circuit uses this principle to store
a voltage value for any required time without any drift
due to leakage. The circuit, shown in Fig. 11, is
basically a tracking aid converter, with its output

215

DATA ACQUISITION & CONVERSION HANDBOOK

Know your circuit
Sample-hold: The generic term used for track-andhold, zero-order hold, or sample-and-hold amplifier, it
describes basically a circuit that acquires an analog
input voltage and accurately stores it for a specified
period of time.
Track-and-hold: A sample-hold circuit that can
continuously follow the input signal until switched
into the hold mode.
Signal-reeovery filter: A circuit that reconstructs
an analog signal from a train of analog samples.
Zero-order hold: A sample-hold circuit used as a
signal recovery filter. So called because its output
represents the first term of a power-series approximation to the input.
First-order hold, or extrapolative hold: A complex signal-recovery filter that predicts the next
sample value by generating an output slope equal to
the slope of a line segment connecting previous and

present samples. In a sense, it works toward the
future.
Polygonal hold, or interpolative hold: A complex
signal-recovery filter that generates a straight-line
segment output that joins the previous sample value
to the present sample. It uses available data to
reconstruct the signal more accurately than other hold
circuits, but with a one-sample-period delay.
Infinite hold: An analog/digital sample-hold that
digitally holds an analog voltage indefinitely without
the decay of capacitor storage.
Cloaed-loop sample-hold: A sample-hold circuit
that charges the hold capacitor within a negative
feedback loop during sampling to achieve high accuracy.
Open-loop sample-hold: A sample-hold circuit that
does not enclose the hold capacitor within a feedback
loop.

11. Sometimes called an "infinite hold," this circuit can
hold a sample indefinitely without the droop that happens
with capacitor storage. It's an aid converter with its output
taken from the analog feedback line. A high on the sample
command line lets the output follow the input. A low
freezes the count inputs. so the count doesn·t change.
9. Here are three different waYI to connect the Input and
feedback to the partial circuit in Fig. 8. The circuit in
(c) has unity gain if the input (R,) and feedback (R2) resistors have equal values.

10. Ultra·f.st umple·holdl often use a circuit like thll.
It has a diode-bridge switch and operates open-loop. The
diodes are biased off until a sample command arrives;
then the pulse transformer's output turns on the diodes,
which connect the input buffer amplifier to the hold
capacitor. A 3O-ns full-scale change is possible.

from the analog feedback line rather than from the
counter. It consists of a d/a converter, up-down
counter, clock, and analog comparator. The circuit
operates by directing clock pulses into the up or down
count inputs of the bidirectional binary counter that
controls a d/a converter.
An analog comparator tests the output voltage of
the d/a converter against the input voltage and directs
the clock pulses to the counter so that the converter's
output voltage changes toward the input. When the
input voltage is reached, the circuit oscillates within
one count of the input value. When the sample
command goes low, the counter retains its contents
indefinitely until the next sample is taken.
This circuit is not particularly fast since it must
go to each new value one count at a time until the
input voltage is reached. Different counting tech·
niques will speed it up, however. Its accuracy depends
on the resolution of the d/a converter; ±O.01 % accuracy requires at least 12 bits.

GZ

216

Keep track of a sample-hold from mode
to mode to locate error sources

A

complicated process begins when a sample-hold
takes a sample. The complications increase
when it switches into the hold mode. To this
bumper crop of complications, add the actual sampleto-hold transition itself, which, as a complex and
important event, must not be overlooked. Understanding the intricate workings of this process is the
basis for understanding the sources of error in the
system and how to minimize them.
In the sample mode, the sampling switch closes and
the circuit charges the hold capacitor to the input
voltage. With the capacitor charged, the circuit tracks
the input signal as it changes. However, tracking is
possible only if the signal doesn't exceed the
bandwidth or slew rate limit of the sample-hold. The
term "sample mode" applies regardless of how long
tracking continues.
The operating parameters that apply to the samplehold in the sampling mode are specified in the same
way as an operational amplifier's. Offset voltage,
expressed in mi11ivolts, may be referred to either the
input or output, and is usually adjustable to zero with
an external potentiometer. Dc gain, the ratio of output
to input voltage at dc, is commonly either +1 or -l.
With some sample-holds, adding external feedback
resistors provides other gains, and some allow trimming external gain to precisely +1 or -l.
Bandwidth, the sinusoidal frequency at which gain
is down by 3 dB from its de value, is measured with
a small-signal sine wave below the slew rate limit.
The slew rate is the fastest rate at which the sample-

FINAL VALUE
VOLTAGE

CAPACI TOR CHARGING

ACQUISITION
TIME
SAMPLE COMMAND

TIME

1. Acquisition time of a sample-hold starts with the
sample command and ends when the voltage on the hold
capacitor enters and stays in the error band. Acquisition
time ;s defined for a full-scale voltage change. measured
at the hold capacitor.

°0

INPUT

o

o -~
10V

[>-=i -X-;-lRE~vc
+1

+1

RO

I
/)

--

O.OO:~FTC
T H

OUTPUT
0

~

_1 __ --~~----"t""-----

-r0.4V

ANAL VALUE

EXPONENTIAL SETTLING
TIME

2. This equivalent circuit for determining acquisition time


l-~---_'''';:-'-I~--Iv>-----O

221

DATA ACQUISITION & CONVERSION HANDBOOK

~RATE

O' CHANGE'

\J1L----A1:t

:~

u

8. Timing uncertainty in the switch and driver circuit
produces uncertainty in the held voltage, which for a given
period of time, increases with the rate of change of the
signal voltage.

SIGNAL RATE

rF CHANGE (dV/dt)

9. To obtain the error due to aperture uncertainty time
for a given signal rate of change, a full-log plot is helpful.
This plot assumes a lO-V full-scale signal.

.~
T

therefore occurs after the signal has been acquired,
when the switch rapidly opens.
Aperture time is frequently, but mistakenly, defined as the turn-off time of the switch. If this were
true, aperture times would be extremely small since
the switch opens very quickly. The confusion stems
from the fact that the switch follows a band-limited
input amplifier which, even if the switch opening were
instantaneous, averages the result over a small period
of time.
To interpret aperture time, as in Fig. 6, assume the
sample-hold receives a I-mV input step (Fig. 6a). The
hold command transition (Fig. 6b) can be adjusted to
occur before, with or after the input step. The timing
difference between the two, designated t,., can be
positive, zero, or negative. (For simplicity, assume no
delay between the hold command and the opening of
the sampling switch.) To make the measurement, feed
the sample-hold with repeated input steps and hold
commands while slowly varying t,.. As the hold
command transition effectively scans across the input
step, the sample-hold's output in hold mode changes.
Ideally, when hold-mode output is plotted against
t., it should look like Fig. 6c. Such an output, a perfect
sample with no averaging, requires an infinitebandwidth input amplifier in addition to an infinitelyfast switch.
Since this is not possible, the input step is averaged,
or filtered, by both the switch with a non-zero opening
time, and by the input amplifier, which has limited
bandwidth. The actual waveform therefore looks like
Fig. 6d. The filtering action of the switch and input
amplifier slows the rise-time of the step to tA, which
is the aperture time or aperture window of the samplehold as shown in Fig. 6e. Mathematically convolving
the input step (Fig. 6a) with the aperture window (Fig.
6e) gives the actual output (Fig. 6d).
In practice, because of amplifier and switch speed
limitations, it is extremely difficult to achieve true
aperture times less than a few nanoseconds .

.~
T

10. Draln-to-gate capacitance, Cd.. transfers some
charge. q. when a FET sampling switch opens. The resulting voltage step on the hold capacitor. CH• is small if
CH is large. The switch in the first circuit (a) operates at
virtual gr'ound,

Ideally, a sample-hold takes a point sample of the
input signal, that is, an accurate sample in zero time.
Since this is impossible,' the sample is actually taken
in the short period of time when the switch opens,
during which the signal is averaged. The aperture time

Delayed window

Aperture delay time, another frequently used term
concerning the sample-to-hold transition, is generally
defined as the elapsed time between the hold command
and the opening of the switch. Aperture delay time,
a pure time delay, can be compensated out by advancing or delaying the hold command. Furthermore, this
specification is difficult to measure, if not impossible,
since the precise time when the switch turns off cannot
be determined directly.
A more useful specification might be called effective
aperture delay, and defil1ed as the time difference
between the hold command and the time at which the

222

input signal and the held voltage were equal. In other
words, effective aperture delay relates the hold command to the point on the input signal which was held
(see Fig. 7).
Effective aperture delay really points out the difference between the two delay times snown in Fig.
7. The first is the analog delay through the input
amplifier, while the second is the digital delay to the
switch opening (Fig. 7a). Effective aperture delay
(EAD) is then equal to (t., - t.).
Notice that either a positive, negative, or zero value
may be obtained depending on which delay is larger.
Fig. 7b illustrates negative effective aperture delay.
In this instance, time lag in the input amplifier has
resulted in holding an input voltage which occurred
before the hold command. Knowing effective aperture
delay time then is more useful than knowing aperture
delay time.
A related specification, aperture uncertainty time,
or aperture jitter, is the uncertainty in the time at
which the switch opens. Actually, it's the time variation in aperture delay time. If the sampling switch
receives the hold command for a series of samples at
the same point on a waveform, it will hold slightly
different values each time.
Aperture uncertainty time originates in the digital
driver circuit and switch. The hold command has a
finite risetime and must pass through one or more
logic thresholds that have voltage noise. These transitions therefore generate time uncertainties. The significance of aperture uncertainty time is that it causes
an amplitude uncertainty in the held output of the
sample-hold. This amplitude error, aA, shown in Fig.
8, equals the product of the rate of change of the input
signal dV / dt, and the aperture uncertainty t,.
This product is the basis of a graph (Fig. 9) that
gives aperture uncertainty vs. signal rate of change
for various accuracies. The accuracy is based on 10volt full scale signals. The surprising fact is that
moderate speed signals produce relatively large errors
even with small aperture uncertainties. For example,
if the aperture uncertainty is 10 ns and the input signal
rate of change is 1V/ I'S, the amplitude error is 0.1%
for 10 V full scale. Reducing this error to 0.01 % means
that the aperture uncertainty time has to be reduced
to just 1 ns.
Aperture uncertainty time is generally quite small
in well-designed sample-holds since it's possible to
achieve values of a few nanoseconds down to tens of
picoseconds. As a rough rule of thumb, the aperture
uncertainty tends to be 10% or less of the aperture
delay time; in some designs it can be as low as 0.1%.
Sample-to-hold offset error develops when the
switch opens, as a direct result of a phenomenon called
charge dumping or charge transfer.

223

lOY

-IOV

11. Sample-to·hold offset error varies with input signal
voltage if the sampling switch floats with the signal. but
is unaffected by variations in signal voltage if the switch
operates at virtual ground.

SPECIFIED
ERROR BAND

1

SAMPLE-TO-HOLD
TRANSIENT
'\.

..,,1 ______ ---_

-------r- ---

OUTPUT

HOLD-MODE
SETTUNG TIME

START

c~~W

1------' L._ _ _ _ __

12. When an aid converter follows a sample-hold, the
start·conversion pulse must be delayed until the output
of the sample-hold has had enough time to settle within
the error band and stay there.

There r.re two types of sample-hold switches; one
operates at virtual ground (Fig. lOa), while the other
operates at the signal voltage (Fig. lOb). Every electronic switch has a capacitance associated with it. In
this case it is Cda , the drain-to-gate capacitance of the
junction FET switches shown. This capacitance
couples the switch-control voltage on the gate to the
hold capacitor.
Since the switch-control voltage must generally be
rather large, a significant charge transfers from the
hold capacitor to the gate-drive circuit when the
switch is turned off. This charge is
q = Cd.

av.

(6)

where a Vg is the change in gate voltage. The error
this .produces on the hold capacitor is then
V

=-q-

=~ av.

(7)

,
CH
CH
•
This error typically might be 10 mV assuming 2 pF
for C. g , a 10-V ~V., and a 0.002 /tF hold capacitor.
Sample-to-hold offset error is one of the un-

DATA ACQUISITION & CONVERSION HANDBOOK

desirable, inherent characteristics of sample-hold
circuits. It should be looked for and recognized. The
charge transfer that causes this error is expressed in
picocoulombs and in practical circuits it may vary
from 50 pC down to 0.1 pC. Since monolithic samplehold circuits require external hold capacitors, their
voltage error must be determined by equation 7.
Sample-holds with internal capacitors have a specified
sample-to-hold offset voltage. This offset, of course,
can be decreased by adding an external capacitor to
increase the total hold capacitance.
Note that the two switch configurations in Fig. 10
have somewhat different charge transfer characteristics. In the virtual ground switch the charge transfer
is constant regardless of the signal voltage, since the
gate voltage change is always the same. In the other
switch, however, the gate voltage change varies with
the signal voltage. This causes the charge transfer to
vary with signal level. Furthermore, the drain-to-gate
capacitance also varies with the signal voltage, so that
the charge transfer itself is nonlinear and even has
a "gain error."
Some have curved errors

The output error caused by charge transfer differs
for the two types of switches (Fig. 11). The virtual
ground switch produces a constant offset error vs.
signal voltage, while the floating switch produces a
nonlinear error vs. signal voltage. Charge transfer is

obviously a limiting factor in a high-accuracy, highspeed sample-hold. It works against attaining both
these characteristics. simultaneously. Some sampleholds have unique switch designs that minimize or
compensate for this charge transfer. In some of them,
an externally-adjustable compensation circuit minimizes the charge transfer. If the sample-to-hold offset
error is constant with signal voltage, then the error
is relatively easy to handle since it can be zeroed with
a simple offset adjustment.
Another effect of the sample-to-hold transition is
a small transient in the output just after going into
the hold mode-the hold mode settling time (Fig. 12b).
This is the time it takes the output of the samplehold to settle within the specified error band after the
hold command transition. Notice that the hold mode
settling time includes aperture delay time. Fig. 12
shows the small output transient caused by the rapid
switch turn-off at the input to the buffer amplifier.
This transient occurs after the output settles to a
new value that includes the sample-to-hold offset.
Hold mode settling time may be a few nanoseconds
to a microsecond or so, depending on the particular
sample-hold. It is an important specification because
an aid conversion that follows sampling and holding
cannot begin until hold-mode settling is complete
without causing a conversion error. As Fig. 12 shows,
the pulse that starts the converter is generated after
the sample-hold output has settled within the specified
error band.

GZ

224

Pick sample-holds by accuracy and speed
and keep hold capacitors in mind

W

hen it comes to selecting a sample-hold
device, fortunately there's a fine assortment
available: monolithic, hybrid and modular
types can all give good performance. There are different degrees of good performance, of course, and for
the most part the sample-hold that's finally selected
will depend on the degree of speed and accuracy
needed. Depending on the type of sample-hold and its
application, it may need an external hold capacitor.
This capacitor should be chosen with as much care
as the sample-hold itself, for its quality directly
affects the performance of the sample-hold. There will
be more about selecting hold capacitors, but first, it's
a good idea to consider error analysis, which is vital
in appraising the total error contribution of a samplehold to a system.
In a given system, of course, the sample-hold is but
one of the many sources of error that may also include
an amplifier, filter, mUltiplexer, and aid converter.
Achieving total system accuracy on the order of 0.01 %
is by no means a trivial task, but quite the opposite.
It pays to take a somewhat pessimistic approach in
adding up the errors, and follow this by thorough
testing of the sample-hold's accuracy in the system.
In many cases the results will be a pleasant surprise,
because a conservatively-specified device has been
chosen. In other cases, it won't be a shock to discover
that the analysis is about right because the samplehold that was selected has been specified right at the
edge of its performance.
The best way to handle error analysis is with a

225

systematic listing like the one in Table 1, which gives
errors for a fast, accurate system with 0.01% error
as a design goal. The errors are computed for an
assumed operating temperature range of 0 to 50 C and
take into account all of the specifications discussed
in this series.
What seems to be a large total error in Table 1
shouldn't be alarming. The sample-hold evaluated,
designed for use in 12-bit systems, has been conservatively specified. If all the errors add in the same
direction, the total error is ±0.036%, but this is an
unlikely possibility. Adding the errors statistically
(RMS) gives a better figure of ±0.017%, which is a
good bit closer to the goal. Since most of the errors
are specified as maximums, the typical statistical
error is actually close to 0.01%.
Speed and accuracy are the two foremost considerations in choosing a sample-hold, and the key to proper
selection is an error analysis that takes the desired
sampling rate into account. The circuit configuration,
a subject discussed in Part 1 of this series, affects
performance in certain applications, so it should be
kept in mind as well.
Consider monolithics first

In general, a monolithic device should be considered
first, since it will result in the lowest-cost design if
moderate performance is acceptable. Moderate performance implies about 4 !,s acquisition time to 0.1 %
and 5 to 25!,s to 0.01 %. Monolithic devices use external
hold capacitors, so one will need to be selected.
Hybrid microcircuit sample-holds offer a step up
in performance without a major increase in size.
Acquisition times of 5 !,S down to 1 !'s, to 0.01 %
accuracy are available, and even faster acquisition
times for 0.1 % can be obtained. Most hybrid sampleholds include an internal hold capacitor, so there's no
need to select one unless additional capacitance is
needed. Many hybrids use MOS-type hold capacitors
which offer exceptionally good performance.
Both the newer monolithic as well as hybrid devices
equal or surpass the performance of many of the early
low-cost modular sample-holds, but they can't match
the newer, high-performance modular types. These
new modules offer some difficult-to-achieve speed and
accuracy specifications such as 350-ns maximum ac-

DATA ACQUISITION 8. CONVERSION HANDBOOK

Table 1. Error analysis of an
accurate, high speed sample-hold
Source of
error
Acquisition
error

---1- - -

SAMPLE
MODE

I

Error
contribution

Comments

0.01%

Maximum error specified

h-

I

+ 5V

MODE

I

rd

~

Cd

~

i
I

R,

-1"'
I

I
I

for rated acquisition time.

I

Gain error

0.00

Externally adjustable to
zero.

Offset error

0.00

Nonlinearity

0.005%

Droop error

0.01%

Gain change

0.004%

Offset change 0.008%

Dielectric
absorption

1-_ _ _ _ _+
Total
RMS Total

0.003%

ACQUISITION

Externally adjustable to
zero.

- 5V

I

Maximum specified.
For 10 p.s hold time. Using
25 C droop of 20 p.Vlp.s
max. and multiplying by
10 to give droop 01 1 mY
at 50 C. This is 0.01 % for
10 V full scale.
Using specified 15
ppm/oC max., x maximum temperature
change of 25 C.
Using specified 30

0)
1. In this example of dielectric absorption error, the hold
capacitor has been sitting at

+ 5 V for some timE. Although

given enough time to settle completely during sampling.
in hold mode. the capacitor·s voltage creeps back toward
+5 V (a). An Imperfect capacitor with dlelectric.absorption
can be modeled (b) by a perfect capacitor. C. the insulation
resistance. RI, and the long-time-constant components
rd and Cd. which simulate dielectric absorption.

p'vrc

max .. x
max. temperature change of 25 C.

Estimated error voltage
during hold time using
of Fig. 2.

__---1curve
0.036%
0.017%

quisition time to 0.01%, or 50 ns to 0.1 %.
Once a sample-hold has been selected, it may need
a hold capacitor. These capacitors have somewhat
unusual requirements. Some parameters, such as
tempco of capacitance, matter very little, while others,
such as dielectric absorption, are very important.
Dielectric absorption affects the accuracy of the held
voltage, although insulation resistance is quite important as well, for the same reason.
When high accuracy is needed, the range of satisfactory capacitor dielectrics narrows down to those in
Table 2, which gives the important specs for them.
Note that insulation resistance, which is quite high
at 25 C, drops drastically at higher temperatures, such
as 125 C. That's because insulation resistance decreases exponentially with temperature.
It won't stay put

If a capacitor is charged to a given voltage, discharged by shorting it, and then open-circuited again,
its voltage will begin to creep up from zero toward
the original voltage. The capacitor exhibits a "voltage
memory" characteristic known as dielectric absorption, which occurs because the dielectric material

doesn't polarize instantaneously-molecular dipoles
need time to align themselves in an electric field. As
a result, not all the energy stored in a charged
capacitor can be quickly recovered upon discharge.
One way to measure dielectric absorption is to
charge the capacitor to some voltage for 5 minutes,
discharge it through a 5-1/ resistor for 5 seconds, then
disconnect it. Measure the capacitor voltage five
minutes later. The ratio of the measured voltage to
the charging voltage, expressed in percent, is the
dielectric absorption.
Even though the time scale in a sample-hold is
usually far shorter than 5 min, dielectric absorption
is still a source of error and should be taken into
account. Assume the hold capacitor has been resting
at a given voltage Vo when a different voltage is
sampled and held. Once hold mode begins, the voltage
on the capacitor will begin to creep back toward
Yo. Thus, the dielectric absorption causes an error as
illustrated in Fig. 1a.
Fig. 1b shows a first-order approximation model of
an imperfect capacitor, emphasizing dielectric absorption. Resistor R, represents the insulation resistance
and rd and Cd represent the source of the dielectric
absorption. (Actually, to model the absorption accurately, there should be a number of additional,
parallel rdC d circuits with different values.)
After capacitor C in the model has been rapidly
discharged from a previous voltage and then opencircuited, the long time constant of r"c d causes some
of the charge on Cd to transfer slowly to C, which
develops a small voltage.
An accurate approximation to this "creep" voltage

226

4 6v

30V

26V

I,

"!,fo

6 V

l

fDa: DIELECTRIC
ABSORPTION ("to)

'S = SAMPLE TIME
'h = HOLD TIME

-2

-I

I
I

I

"

10

14

12

16

MULTIPLES OF ts -

2. A natural log function of time is an accurate approximation to the voltage creep caused by dielectric absorption. Before sampling, the capacitor has been holding a
voltage Vo. A new sample charges the capacitor to a new

voltage (zero, in this case, for simplicity), for period t,.
Once in hold mode, the capacitor reaches a voltage :;'V
at time 2t, and continues to creep toward Vo according
to the logarithmic expression.

ANALOG
CHANNEL

CHANNELl

r:
,------------

~

I

I

n'
~ ,+:----------..sf.~;}.~" :
:

START

I

"""'*'1

I

~

n

HOLD-MODE SETTLING TIME

CONVERT:

: 1-_ _ _ _ _ _ _ _ __

I
I
STATUS:

l:1.------'1

"
"

BUSY

~T~
G

3. A data-acquisition system scans a number of analog

converter until its conversion is complete, When it's
finished, the STATUS line goes low to permit the next input
in sequence to be converted (b).

inputs and converts them, one at a time, to digital form
(a). The sample-hold provides an unchanging input to the

caused by dielectric absorption is shown in Fig. 2. The
curve is a natural log function of the shorting time,
or sampling time (t,). If the output creep voltage is
measured at time 2t.. the voltage will be !1 V. If it is
measured at 4t.. it will be 2 !1 V and at St.. 3 !1 V. The
equation for the curve is

First, determine the value of !1 V from the measured
dielectric absorption. The standard tests for dielectric
absorption normally specify th » t.. which is the
correct way to make them. Since the equation is
logarithmic, there is no asymptote to the curve, which
continues to rise. For all practical purposes, however,
a hold time much longer than the sample time will
give a value for dielectric absorption that's far out
on the curve.
Assume that the dielectric absorption is measured
as 0.02% for a point at which th = 15t, or t =
16t". Then
2 X 10-' V.
!1V =
In 16
= 7.21 X 10-' V.
where the dielectric absorption is defined as Ve/Vo at
t = 16t". 'l'he resulting equation for creep voltage is

Ve = !1Vln

t"
where t" is the sample time and t is the total time,
or sample time plus hold time (t, + th)'
This equation is a good model, providing Ve«V•. It
does not hold for extremely long time periods, however, since Ve goes to infinity for infinite time. As
shown, Vd represents the voltage measured to determine dielectric absorption at a specific time, which
is a large multiple of t".
Capacitors can be measured and fitted to this curve.

227

DATA ACQUISITION & CONVERSION HANDBOOK

Table 2. Sample-hold capacitor characteristics
Insulation
resistance
at 25 C
(Megohmmicrofarads)

Type

Operating
temperature
range (OC)

Polycarbonate

-55 to +125

5

Metallized
polycarbonate

-55 to +125

Polypropylene

-55 to +105

Metallized
polypropylene

-55 to +105

x

0.05%

3 X 10'

4X 103

0.05%

7 X 10'

5 X 103 (1)

0.03%

5 X 103 (1)

0.03%

7 X 10' (2)

0.02%

1 X 10'

0.01%

-55 to +85

Teflon

-55 to +200

1 X 1()6

c:c: .......

l

')nn

x

Dielectric
absorption

1()4

Polystyrene

T .... '-I .......

~

v

1.5

10'

7 X 10'
1 X 1Q6

Metallized

Insulation
resistance
at 125 C
(Megohmmicrofarads)

1nfi

.,

~

v

, f\4

n(\')OI..

(1) At 105 C
(2) At 85 C

error to the sample-hold, as the curve in Fig. 2 shows.
At this point, there may be reason to wonder if all
the care and time needed to select a sample-hold is
worth it. It certainly is. There's an abundance of
applications for these devices.

IN

OUTPUT
DATA

Take a sample
I

Undoubtedly one of the most common applications
for a sample-hold is in data acquisition systems. A
representative system would have an B-channel multiplexer followed by a sample-hold and a 12-bit aid
converter (see Fig. 3a).
A logic-control circuit steps an address counter to
sequence the analog multiplexer through the eight
channels of analog data. For each channel the samplehold acquires the input signal and switches into the
hold mode.
After allowing for the hold-mode settling time, a
start-convert pulse initiates the aid conversion, which
is performed by successive approximation. After the
conversion, the aid converter's status output goes low.
When the conversion of this channel is finished, the
analog multiplexer switches to the next channel while
the output register of the aid converter holds the
digital word from the completed conversion. This word
is then transferred out to a computer data bus. The
sampling and conversion process is repeated for each
analog channel in sequence.
From Fig. 3b, T is the time required for the
multiplexer and sample-hold to acquire the signal and
for the aid to convert it. Then liT gives the throughput rate, or the fastest rate at which the analog
channels can be scanned. The rates for practical 12bit data acquisition systems may vary from about 20
kHz up to 250 kHz corresponding to values of T that
range from 50 I's down to 41's.

...
2
"'3

~4

~ 6
7

•

OUTPUT
DATA

4. In a single-channel system, the settling time of the
input buffer amplifier, A,. isn·t critical because the
amplifier can follow changes in the signal (a). With
multiplexed inputs (b). however. the input buffer may take
additional time to settle to the new value at the
multiplexer's output when it switches channels.

v,

= 7.21

X

10- 5 Vo In..!.
t,

Two factors reduce considerably the error due to
dielectric absorption in typical applications of a
sample-hold. First, the dielectric absorption measurement assumes a long initial charging time, say 5
minutes, whereas in a sample-hold a new voltage is
held for a relatively short time. Second, the dielectric
absorption is specified for a long open-circuit time
compared with the shorting time, whereas in a samplehold the hold time may be only slightly longer than
the sample time.
The amount of creep voltage can also be reduced
by remaining in the sample mode as long as possible
relative to the hold time. The result of these factors
is that a capacitor with a dielectric absorption of
0.02%, for instance, may contribute 0.005% or less

228

OUTPUT
OATA

INPUT

CONTROL

5. A simultaneous sample-hold system such as this
samples all analog inputs at the same time and holds the
samples for conversion. While one of the held voltages
is being converted. the others mustn·t droop too much.

7. In an ultrafast aid conversion system, acquisition time
in a sample-hold takes up a sIZable part of the cycle.
Interleaving two sample-holds like this lets one of them
acquire while the other one's output is being converted.

~
,I
I

ANALOG

-.It-

OUTPUTS

I

~
I
:
v.

I

I

I

I

I

~
I
I

I
I
tb

SAMPLE
COMMAND

6. Multiplexed digital data destined for a number of
analog channels are reconstructed and distributed by a
system like this one. Once the data for a channel have
been converted. the sample-hold for that channel samples
the d/a's output and retains it until the next data word
for that channel comes in for conversion.

8. Sample-holds can serve as temporary analog signalstorage devices. The first sample-hold retains Signal
VAs peak value so the converter can divide it by the peak
value of input VB. which comes by later.

Indeed, considering the many applications for
sample-holds, a good number are used in conjunction
with aid converters. This is because the sample-hold
greatly reduces the converter's aperture time.
There are two important ways to use a sample-hold
with an aid converter, and each imposes a different
requirement for the acquisition time. Fig. 4a shows
a fast inverting sample-hold used ahead of an aid
converter, which converts just one input signal. The
sample-hold continuously tracks the input signal until
is goes into the hold mode.
Even while in the hold mode, input-buffer amplifier
Al continues to track the input signal and only A, and
A, affect the acquisition time. Acquisition is very fast
because Al doesn't have to settle to a new voltage for
every sample.
The same sample-hold can also follow an analog
multiplexer, as in Fig. 4b. The required acquisition

time will be longer here since A, must settle to a new
voltage every time the multiplexer switches to a new
channel. This means that the settling time of A, is
now part of the acquisition time.
These two situations are significant because A,'s
settling time may be larger than the acquisition time
of the rest of the circuit. If it is, there'll be a great
difference between the acquisition times of singlechannel and multichannel acquisition systems.
Another important consideration in a data-acquisition system is interfacing the sample-hold to the aid
converter. A successive-approximation aid converter,
without an input buffer amplifier (which adds to the
conversion time), has a resistor input that goes to an
analog comparator's input terminal. Since the comparator is changing state during the successive-approximation conversion, the input impedance to the
aid changes. Since this happens at high speed, there

to

229

DATA ACQUISITION & CONVERSION HANDBOOK

Table 3. Sample-hold comparison
, OUTPUT

Acquisition
time

Accuracy

®:-{"

Monolithic

0.1%
0.01%

41020~s

Hybrid

0.1%
0.01%

25 ns
1101O~s

0.1%
0.01%

30 to 200 ns
0.25 10 5 ~s

D/A CONVERTER
OUTPUT

Modular

GLITCH
DATA IN

9. An output developed' by many d/a converters for
certain input-code transitio!,!s temporarily goes the wrong
way. This transient. or "glitch." is undesirable in some
applications and can be removed by sampling the
converter's output after the glitch has gone by.

may be errors if the sample-hold's high-frequency
output impedance isn't low enough. Furthermore,
most sample-holds have higher output impedance in
the hold mode than in the sample mode.
Sample all at once

Another way to use sample-holds in a data-acquisition system is illustrated in the simultaneous samplehold system of Fig. 5. Here, data must be taken from
all analog inputs at precisely the same time. To do
this, the system requires a sample-hold per channel
ahead of the analog multiplexer.
All the sample-holds are given the hold command
.simultaneously; then the multiplexer sequentially
switches to each sample-hold output while the aid
converter converts it into digital form. Notice that a
high-impedance buffer amplifier is required between
the multiplexer and the aid converter.
For this application, select sample-hold devices that
are identical and have very small aperture-uncertain. ty times. In addition, the aperture delay times should
be adjusted so that they' all go into hold mode
simultaneously. Another important criterion is that
the droop rate be relatively low, since the last samplehold in the system must hold its voltage until all the
other outputs have been converted.
In an application which is the reverse of data
acquisition, sample-holds can .send signals from a
channel to many destinations in a data-distribution
system. Such a system (see Fig. 6) uses a single dl a
converter and storage register together with a number
of sample-holdsto distribute data to a series of analog
channels. As digital data are transferred into the dla
converter and its output changes, the appropriate
sample-hold samples the new output voltage and then,
once the converter's output has settled, switches into
hold mode.
Each sample-hold circuit is updated in sequence as

5 10 25

Price

$5 to $21

~s

$35 10 $135
$4310 $208

new data arrive, and holds its voltage until all the
other sample-holds have been updated and the sequence returns to the first one. The sample-holds used
must be chosen for the required acquisition time,
which depends on the rate of updating each output,
and fur the

dt!sin~u uruup

error ueLween upuates.

Back on the other side of the coin, ultrafast aid
converters can benefit from working with sampleholds. Interleaving two of them, as in Fig. 7, will
eliminate acquisition time delay in many applications.
In such systems, the sample-hold's acquisition time
can be a significant portion of the system's cycle time.
With interleaved sample-holds, however, system cycle
time depends only on the time required for aid
conversion.
Acquisition-time delay is eliminated by having one
sample-hold acquire the next sample while the aid
is converting the output of the other sample-hold. The
aid converter, therefore, is simply switched from the
output of one sample-hold to the other. The only dead
time between conversions is the small delay in the
analog switch.
Conversion time can be decreased further, but doing
it requires a second aid converter, with one aid
operating off each sample-hold. The sample-holds then
are operated sequentially, and the outputs of the aid's
have to be digitally multiplexed. In this way the
throughput time is reduced to half the conversion time
of either aid converter.
In yet another aid application, a sample-hold can
delay or "freeze" analog data that exist only briefly;
this information can then he combined with later data.
This circuit (see Fig. 8) computes the ratio of two peaks
that occur at different times, t. and tb'
The first sample-hold stores the peak of signal
VA so that its value will still be :wailable to the
ratio metric aid converter when the peak of signal VB comes by. The second sample-hold stores the
peak while the ratio is being converted to digital form.
Sample-holds deglitch

The list of conversion applications for saml,\e-holds
seems almost endless. Even big problems can be
solved. For example, major code tran~itions in a dla
converter can cause unwanted voltage spikes as large
as half the full-scale output voltage. These spikes,

230

OUTPUTS

~
2

~

~
SYNC

---=ft:..sl' '

~

~m!l

10. When analog signals are encoded by pulse-amplitude
modulation and then multiplexed. they can be sorted out
and reconstructed by a set of sample-holds with properly
timed sample commands. The time scale of the Input is
shorter than that of the outputs.

11. Cascaded sample-holds acquire a signal quickly and
hold it for a long time with little droop. The first one needs
to hold a signal only longenough for the second to acquire
it. Typical acquiSition would be 51's to 0.1 %. with a droop
rate of 30 I'V/s.

commonly called glitches, are caused by switches in
the converter that take longer to turn off than to turn
on, or vice versa. The point is, in many d/a converter
applications such as CRT displays and automatic
testing, the converter output voltage should make a
smooth, monotonic transition when it goes from one
output voltage to the next.
This can be done by processing the d/a converter
output with a sample-hold as shown in Fig. 9. First,
a digital control circuit transfers the digital data from
the register to the d/a converter. With this information at its input, the d/a converter generates a new
output containing glitches. Once the glitches have
settled, the sample-hold takes a sample of the new
analog data and returns to hold mode before the d/a
output changes again. The output of the sample-hold
now has a smooth, monotonic transition between the
old and the new levels.
Keeping up with high-speed analog d/a outputs
generally requires ultrafast sample-holds for
deglitching. Usually an inverting, current-input
sample-hold follows the d/a converter to permit the
highest possible operating speed. In fact, some specially designed d/a converters have self-contained
sample-holds for deglitching, and not surprisingly, are
called deglitched d/a converters.

To demodulate this pulse train, the control circuit
synchronously switches on each sample-hold in sequence as the pulse arrives, then returns it to hold
mode until the next pulse from that channel arrives.
Pulse by pulse, the output of each sample-hold becomes the reconstructed analog signal of the appropriate channel. A low-pass filter can also be added
to each sample-hold output to smooth the reconstructed signals further.
In some analog-circuit applications, sampling
sholiid be quick, yet the sampled value should hold
steady for a long time. Such conflicting needs produce
conflicting requirements on the sample-hold. The best
solution to the problem is to use two cascaded samplehold devices, as in Fig. 11. The first sample-hold is
a fast unit that acquires the input rapidly and accurately, ·while the second unit is a slow device with
a very long hold time (low droop rate), perhaps on
the order of minutes.
Basically, the first sample-hold must acquire the
signal quickly and then hold the result long enough
for the second sample-hold to acquire it. The errors
need to be calculated carefully to be sure of meeting
the accuracy requirements. In many cases two
monolithic sample-holds in cascade might do the trick.
External hold capacitors can then be chosen to give
the desired performance.
For example, a O.OOl-I'F polystyrene capacitor
would be a good choice for the first sample-hold to
give an acquisition time of 51'S to 0.1 %. For the second
one, a 1.0-I'F capacitor would give an acquisition time
of 10 ms but a hold time of 300 s to 0.1% accuracy.
The resulting droop rate would be only 30 I' VIs, which
is quite low, indeed.

Putting it all together
Data conversions aren't the only applications to
benefit from sample-holds. As Part 1 of this series
pointed out, a zero-order hold makes an excellent datareconstruction filter and is commonly used in pulseamplitude modulated (PAM) systems such as the one
in Fig. 10. Here, time-division mUltiplexing is used
to send a train of amplitude-modulated pulses over
a transmission system, each pulse in sequence being
the sample from one analog channel.

GZ

231

DATA ACQUISITION & CONVERSION HANDBOOK

Analyzing the dynamic accuracy

of simultaneous
sample-and-hold circuits is straightforward. A wideband
scope and a simple mathematical model supply the answers.

·:rm,. y

In most simultaneous data-acquisition systems
a large number of analog input channels are
strobed at precise time intervals and then sequentially digitized by an analog-to-digital converter. To check the multichannel sample-andhold circuits there are some simple tests the user
can perform to verify correct circuit operation.
To start the error analysis, several assump·
tions can safely be made: All static errors have
been eliminated• The offset error.
• The gain error.
• The hold step error.
Input voltage. Vin' to the sample·and·hold equals
the output voltage, Vouto from the sample·and·hold.
Vin is any dc voltage between ±10 V. The offset
error is Vout when Vin = 0, while the gain error is
the maximum value of the offset error divided by
V in maximum (10 V).

OliO'

:~:QUENC;O:.
In\
\:J

10°

~Ol

I

I /I

~

I

iV I I I
00\0_

105

"'"

d

FREQUENCY Hz

1. Plots of a sin'gle pole transfer function (a) and of the
gain·error (b) are shown with a i·MHz cutoff frequency,

• A change in the gain during the sample
mode as a function of frequency.
• A nonzero hold step as a function of fre·
quency (hold-step error).
• A shift in the effective beginning of the hold·
step as a function of Vout , dVoutldt, or frequency
(aperture·shift error).
The aperture-shift error can be caused by a slowly
opening switch or by a pole at the unity-gain -3
dB point (fco) of the unity-gain sample amplifier.
The error advances the effective time of the switch
opening to a time prior to its actually reaching open
circuit. For applications of simultaneous sample-andhold circuits both the fco's and the switch opening
times, must be matched.

Looking at the dynamic errors

Normally, one sample-and-hold circuit is used
for each a d converter with any multiplexing between input channels done previously. However,
for a large number of channels this leads to
errors due to the different conversion times of
the various channels. In a simultaneous sampleand-hold configuration, a number of input analog
channels are strobed at' a precise time and the
held voltages are sequentially converted to digital form.

The transfer function during sample

Gain in the sample stage can be represented
bv a linear transfer function-at least for amplit~des small enough that the amplifier slew-rate
doesn't affect the results. Thus, a simple low-pass
function with a pole at f co, say 1 MHz, can be represented by the following:

At this point the most basic test that can be
performed is to simultaneously apply the same
voltage waveform to all inputs. Now, if we look
at the output for each channel, the digital words
representing each voltage should be identical. If
the system fails this basic test, the user must
search the specification sheets and the circuits
themselves for the error sources.
The three major sources of dynamic errors can
be traced to the following:

1
--.-f
1 + J 106

The graph of this typical low-pass filter is shown
in Fig. la. It has unity-gain transmission and a

232

width of 1 MHz, an input of 10 V at a frequency
of 1 kHz results in an error of 0.001 or 10 mY.
By now finding the response of the circuit to
a ramp of K V Isec, we can try to match transfer
functions of all the channels of the sample-andhold stages. The gain-error transfer function is
put into the s domain using LaPlace transforms
and becomes

I-MHz -3 dB point.
Usually, though, it proves more useful to plot
small deviations from unity gain as shown in
Fig. lb. The formula used for this gain-error
plot is
.

Gain error = _V-",~ - 1 =
V"'

f

-J1O"
~-.-f-

+ J 10'
While not usually seen in this form, this type of
frequency-response plot is quite valid. From the
equation we see, for example, that a circuit band-

Gain error =

s + ._
27T X 10"
The ramp is also transformed, and becomes K/s'.

The sample·and·hold: What is it and where is it used?
A sample-and-hold (S/H) circllit holds or
"freezes" a changing analog input signal voltage. lTslially. the ,'oltage thll~ frozen is then
con\'erted into another form. either by a voltage-controlled o~cillator. an analog-ta-digital
(aid) converter or some other device.
The simplified block diagram of a lossipss
(ideal) S/H circuit is shown in Fig. I. Here the
amplifiers are assumed to be ideal-with infinite
input impedances and bandwidths, zero output
impedances and unity gain::.. The electronic
switch is also considered ideal~with infinite
speed, zero impedance in thE" sample position
and infinite impedance in the hold position. Also,
the sampling capacitor, r. is assumed to have
no leakage or dielectric ahsorption.
D('pending upon cost, tht' ust'r has three basic
methods to choosl:' from when setting up a multiple-signal data-acquisition system. The most
basic but also thl' most llXPl'tlsiYl' schl'me is the

one shown in Fisc 2a. This circuit u.c;es an individual S/H and aid convrrter for each sensor
line. Fig. 2b is a low cost alternatiw' in which
all the sensor lines are first multiplexed and
then fed into a single Sill and aid com·erter.
Another method. fallin, between those of Figs.
2a and 2b in cost and performance.' is shown in
Fig. Zc. Here, the sensor signals ar(' first
sampled and then multiplexed and sent to a
single aid converter.
If the S/H circuits were ideal. the only significant errors wouId OCClIr in the multiplexer
or the aid converters. In a real world situation.
of course, the S/H circuits introduce some
serious errors into the con\'ersion circuit.
The circuits of Figs. 2a and 2c require actditional qualities from the S/H circuits that
are not needed for the system of Fig. 2b. Precise matching of the aperture delays and bandwidths is required.

SENSOR
LINES

BUFFER

"P'

>---+-0

VOUT

NON-1NVERTING SAMPLE MD HO_D

2

n-LiNES

MULTIPLExER

n 1m-LINES

TOTAL

2

a

233

b

DATA ACQUISITION & CONVERSION HANDBOOK

TIME
IDEAL

1'
I

,

1

,

,

HOLD STEP

,
1
1
1

APERTURE SHIFT

,

1
1

I

:-ACTtJAl.

EF;-:'E~TIVE~

SAMPLE

~HOLO

1

,I

I

I

SAMPLE--:-'- -....-

HOLD

TIME

4. If you use a different scope input, the effective
point of hold initiation can be found by extrapolating
back to the zero point.

2. Dynamic errors caused by the hold step and the
aperture shift are hard to distinguish.

c(f\.---;v
z

>
I

I

I

SAMPLE

-r--- HOl::)

,,
,

TIME

EFFECTIVE --+t

I

I
j4-ACTUAL

SAMPLE-L,_-......
, -

3. By extrapolating the two straight·line segments to
meet each other, you can find the effective time at
which the hold period starts.

5. The effective start time for hold is not affected by
the slope of the input ramp--for a first·order analysis.

The hold-step error appears as a sudden change
in the sample capacitor voltage at the time of
hold. If such an error exists only for a fast ramp
input, a probable cause is dielectric absorption
in the capacitor.
The aperture shift is a variation, in either
direction, of the point in time at which hold
occurs. It is also known as aperture uncertainty.
As a function of input rate it is somewhat difficult to measure.
To measure aperture uncertainty, use an
oscilloscope with a sampling amplifier or with a
sensitive, wideband input having good recovery.
Then observe the sample-and-hold output for an
input slope of 0.5 or 1 V / /Ls. The reSulting
straight lines can then be extrapolated to a point
where they meet, and the effective hold instant
can be fflund. as shown in Fig. 3. A change of
this point with the input waveform, or randomly, is called aperture jitter.
A similar type of measurement uses a scope's
differential input. All static and dynamic errors,
including linear ones, due to the transfer function can be measured by observing Vo ", - V,,, as
shown in Fig. 4. The slope during the hold period
can be extrapolated back to zero to find the effec-

Taking the inverse transform of the product
we get
K

27T X

10" [1 + e-(2'I" x

10')

HOLD

t]

as the output error for a ramp input.
The two terms in the result represent a gain
error. This error is due to the ramp as a constant
K/27Tf,,, and a delay of 1l21Tf,.". seconds. The delay in the output can be considered as an advance
in the transition time of sample-to-hold statesbut this is not usually done. The inverse transfer
function can always be applied after the data has
been digitized. However. for multichannel simultaneous sample-and-hold applications it is unnecessarily complicated to keep track of, say. 32
different transfer functions. The solution to this
problem is to match all the transfer functions so
that the units will deliver identical outputs for
the same input waveform.
Other error sources exist

Examination of the output voltage near the
time of the sample-to-hold transition shows the
errors caused by both a hold step and an aperture shift (Fig. 2).

234

~. "II-------ll.------~n--.-E--

,
/

K(I-llel

TIME

~~!~;:cr I---~~~W---~,f_---~--~TI~
..=E~~
T I --L..&.-- T 2 _ _,

,

,"

EFFECTIVE TIME

,,

aF HOLD

,,

,.....-- T 3----t
T3

6. A typical analog switch introduces a delay in the
sample·to·hold transition.

0>---+---"1':''''___2::"a

~"'---I~--OO

,.

0
0

,

.=1
-

-

I

IN

+

5/H CONTROL

o

A,:

:

.

~

•

IC...

1 - . , - - - - 5/H OUT

A2

H '"

100 pF

Fig 2-ln this open-loop-follower S/H, determine sampling
output settling time and output acquisition time. (See
questions 2 and 3)

sampling switch equals 1000 and that the
hold capacitor has a value of 100 pF, determine, to a first approximation, both the
sampling output settling time to 0.1% for a
10V step input and the output acquisition
time to 0.1% for a continuous 10V p-p 20 Hz
sine wave on the input.
a. 870 nsec, 470 nsec
b. 470 nsec, 870 nsec
c. 570 nsec, 406 nsec
d. 405 nsec, 337 nsec.
3. Suppose that the sample/hold circuit of Fig 2
is an IC type in which you connect the hold
capacitor externally. With C Il =100 pF, the
manufacturer specs the following: sampleto-hold offset error of 100 mV and hold-mode
voltage droop of 250 mY/sec.
A. If you change C H to 2000 pF, what new
values do the sample-to-hold offset error
and hold-mode voltage droop assume?
a. 2V, 12.5 mY/sec
b. 100 mY, 12.5 mY/sec
c.5 mY, 5V/sec
d. 5 mY, 12.5 mY/sec.
B. Find the input acquisition time to 0.1%
FS for a 10V step input with C,,=100 pF
and C H =2000 pF.
a. 570 nsec, 11.47 fLsec
b. 406 nsec, 1.46 fLsec
c. 570 nsec, 878 fLsec
d. 406 nsec, 1.21 fLsec.
4. A sample/hold operates in front of a 12-bit
A/D converter that has a 10V FS range and
20-fLsec conversion time. This S/H uses FET
switches and has a droop rate of 59.5 mY/sec
at 25'C. What maximum operating temperature can you choose so that the A/D sees less
than 1/2 LSB change on its input?
a. 60'C
b.85'C
c. 100'C
d. 125'C.
5. When working with a track-and-hold circuit
with a finite sampling time of 50 nsec in an
environment with an operating range of - 55
to +125'C, what type of holding capacitor

I---+-- 5tH OUT

t---+--

5tH CONTROL

5tH OUT

0--------'

Fig 3-Simultaneous S/H's present special problems of their
own. Do you know what they are? (See question 7)

gives best performance?
a. Ceramic
b. Teflon
c. Polystyrene
d. Polypropylene.
6. Suppose you're designing a system in which
the maximum error introduced by the sample/hold must not eKceed 0.01% and you
apply a 20V p-p sinusoidal signal to the input.
If the only error source consists of a 32-nsec
aperture time, what maximum allowable
input frequency can you use and remain
within error budget?
a. 1 kHz
b. 2 kHz
c. 4 kHz
d. 7.5 kHz.
7. Fig 3 shows a simultaneous sample/hold
circuit. If you sample a 20V p-p sinusoidal
signal with a frequency of 30 kHz, a 10-nsec
aperture uncertainty in the S/H causes errors
of near what percentage fu II-scale range
between units?
a.1%
b. 0.05%
c. 0.09%
d.0.009%.
8. The sample/hold circuit of Fig 4 consists of a
closed-loop type with an operationalamplifier integrator in the feedback path of

237

DATA ACQUISITION & CONVERSION HANDBOOK

a. Fair accuracy, last acquisition time, high
droop rate
b. Extremely good accuracy, last acquisition
time, high droop rate
c. Extremely good accuracy, slow acquisition
time, low droop rate
d. Fair accuracy, slow acquisition time, low
droop rate.

o

10.

S!H CONTROL

Fig 4-By examining this

closed~loop

S/H with opwamp

feedback, can you describe its general operating characteris-

tics? (See questions 8 and 9)

A samplefhold with unity gain has specilied
accuracy of 12 bits (ie, gain error in sampling
mode=O.Ol% of' reading). In sampling mode
this simple SfH exhibits a single-pole transfer function and a 20V pop -3 dB bandwidth
of 500 kHz. If you want to sample a 20V pop
sine wave to 12-bit accuracy, what approximate maximum frequency can you input and
still maintain that accuracy?

the input buffer amplifier. \Vhat fe:atiofiship

9.

exists between (I) the output settling time and
(II) the input acquisition time (dependent on
C H ) lor a 10V step input?
a.I<11
b.I=11
c. I> II
d. Insullicient data.
Reier again to the closed-loop integrating SfH
conliguration 01 Fig 4. What best describes
the general charact'eristics 01 this type 01

b. 100 Hz

c. 7.1 kHz
11.

circuit?

d. 14.14 kHz.
Here's a quickie question to complete the
quiz: Of the four SfH specs listed below,
what is (are) the most commonly omitted
parameter(s) on manufacturers' data sheets?
a. Sample-to-hold ollset error
b. Hold-mode settling time
c. Output noise, hold mode
d. Output ollset voltage drift.
JM GM

238

Presentin p the answers
to our qUIz on sample/holds
Confused? If not, you're an industry expert. Take this opportunity to
learn some important facts about these deceivingly complicated devices.

a spike; however, the closed-loop transconductance integrator of Fig 1d won't exhibit large
hold-to-sample spikes.
2. The sampling output settling time (ie, keeping the unit in sample mode and observing the
output for a 10V step input) depends on the signal
going through three separate single-pole stages:
the input buffer, the RC network composed of
ON switch resistance and hold capacitor, and the
output follower. On the other hand, when
coming out of a hold state back into sample
mode, the acquisition time required for the
output to track the slow (20 Hz) sine wave
diminishes because the input buffer already
tracks the sine wave on its output. You can use
the square root of the sum of squares formula as a
first approximation for calculating the settling
time of such cascaded single-pole circuits. The
RC time constant of the switch-and-hold capacitor equals 10 nsec, and its settling time takes
seven time constants-70 nsec-to reach 0.1% of
its final value.
Thus, sampling output settling time is

ANSWERS
1. a, d
2. c
3A. d
3B. b

4. d
5. b
6. a
7. C

8. b

9. c
10. c
11. b, c

This quiz should have given your knowledge of
5tH's a real workout. In fact, it should have been
difficult-you learn much more from tough
exams. Here's how to score yourself (count lA
and l8 separately):
11-12
9-10
7-8
5-6
3-4
1-2

Send your resume to the authors
Take over your design department
Collect one "attaboy!"
Average
Read up before doing any S/H designs
Don't let your boss see this.

Now for a more detailed discussion of the
answers.
1. Generally, a and d work best. Although all
sample/hold circuits contribute slight errors,
open-loop-follower types don't exhibit large
hold-to-sample transients (spikes) that generally
occur on closed-loop types. And although spiking
might not matter for large changes, it becomes
extremely important in D/A deglitcher applications where you sequentially increase D/A digital
inputs to generate an analog ramp. In this
application, the sample/hold samples only 1-LSB
changes from input to output, and even in this
case the closed-loop types of band c generate
large hold-to-sample spikes (as high as 7V),
possibly worse than the D/A glitches that the S/H
tries to eliminate. Because it keeps its loop open
during hold, a closed-loop circuit must entirely
reacquire the input in sample mode, even with
unchanged inputs. Usually this process results in

v'400' + 70' + 400' = 570 nsec,
and the output acquisition time is
v'70' + 400' = 406 nseC.
lA. With C H=2000 pF, the sample-to-hold offset
error=5 mV and the droop rate=12.5 mY/sec,
because both specs vary inversely with CH. Droop
dV/dt equals itCH where i represents the current
leakage through the hold capacitor (the sum of
output-amplifier bias current and switch leakage
current). The sample-to-hold offset error consists
of the step error that occurs at the initialization of
the hold mode generated by dumping charge into
the hold capacitor. Because droop dV/dt= itCH

239

DATA ACQUISITION 8. CONVERSION HANDBOOK

and sample/hold offset error=Q/C, if you increase CH.by a factor of 20, both droop and offset
decrease by 20.
3B. This question is slightly deceptive. The true
definition of input acquisition time is the time
necessary, in sample mode, for the hold capacitor
to acquire a step voltage. If C H=100 pF as in the
initial problem circuit, the time constant RC=10
nsec and 7RC=70 nsec. The input amplifier settles
in 400 nsec, and, as before, input acquisition time
is

v' 400' + 70' = 406 nsec.
For CH=2000 pF, 7RC=1400 nsec, and
acquisition time is
'\/400 2 + 14002

=

CAPACITOR BREAKDOWN CHARACTERISTICS

TYPE

TEMPERATURE RANGE DIELECTRIC ABSORPTION

CERAMIC
POLYSTYRENE
POLYPROPYLENE

UNACCEPTABLE
TO 85~C
TO 100°C

TEFLON

TO 12SoC

The maximum allowable signal change on the
input of the A/D is

4.

10V) = 1.22 mV,
(0.5) ( 2i2

E=(~~)T
Wheie [~voltage enOf or change, dVidt=signai
slew rate and T=aperture time. During time T,
the maximum allowable change on the input
of the sample/hold equals (0.010/0X20V)=2 mV.
Also note that for sinusoidal waveforms, the
maximum slew rate occurs at zero crossings.
Any sinusoidal input signal follows the form

Vin = Vsin(21Tit),

and maximum allowable slew rate equals
1.22 mV = 61VI
20 p.sec
sec.
This value also represents the maximum allowable droop rate for the sample/hold. Because the
S/H uses FET switches, the droop rate doubles
every '10 0 e. Taking this into consideration, apply
the following formula:

and in this case E=10V for a 20V p-p signal. Taking
the first derivative, which represents slew rate,
find
dV
dt
=

= 59.5

mV x 2' ATII.·C)
sec

And because llT=100°C,Tmax=125°e.
5. A major error source in sample/holds with
finite sample time periods comes from the
storage capacitor's dielectric-absorption characteristic. Teflon exhibits the lowest dielectricabsorption property at 125°C and thus makes the
best choice. This characteristic, also called dielec~
tric hysteresis, determines the length of time a
capacitor requires to discharge; a high
dielectric-absorption value means that the capacitor won't react to sudden step changes in storage
charge and also that high temperatures can cause
extremely high sampling errors. The nearby table
lists breakdown characteristics of commonly used
capacitor types.
6. A sample/hold aniplifier, actually a form of
analog memory, ideally stores (in hold mode) an

(21T/)V cos(21Tft).

Then you know that zero crossings occur at

DRmax = DR. •• c x 2' >TII.·C)
61 V/sec

0.01%

instantaneous voltage (sample value) at a desired
instant in time. The constraint on this time is
aperture uncertainty. To compute the error (for
sinusoidal waveforms), you must observe the
following formula:

input

1 .16 ;,Lsec.

0.01·0.02%
0.01-0.02%
0.03-0.09%

t =

2fn (n = 1,

2, 3 ... ).

Thus,
dV = (21TiV)dt.
To find the maximum allowable input frequency,
use this equation and solve for f:
2mV = 21Ti(10V)(32 nsec)
f = 0.995 kHz.

Find the answer in the same manner as in the
previous question, but here the key lies in
knowing how to use the 10-nsec value in relation
to this circuit.
You know that

7.

E=(~~)T

240

where

~~

Generally, the p-p output noise in hold mode
runs well below the specified linearity of the
particular sample/hold, and its omission usually
causes few problems. But this noise could cause
slight linearity problems if you input its signal into
an AID. A more important missing sample/hold
specification, hold-mode settling time, is defined
as the time for the output to settle to the
sample/hold accuracy after being given the logic
command to switch into hold mode. This holdmode settling time could cause annoyances in
D/A deglitcher (display) applications, but bigger
headaches can result if you use the sample/hold
with an A/D converter. Here, if you begin the
conversion process (A/D clocking) before the
sample-to-hold transient has settled to the L5B
level, you run the risk of getting bad codes,
especially noticeable at the half-scale level for
successive-approximation-type A/D's and at
lower voltages for counter-comparator types. The
hold-mode settling time can run as high as 1 ILsec
for the slower closed-loop-type 5/H's, while it
usually runs only tens of nanoseconds for highspeed 5/H's.

= (27r)(30 x 103 )(10)

= 1.8 x 10'V/sec.
But because T=10x10" sec, E=18 mY; converting
the value, you find that
Error =

1.8 mV
20\1
=

0.9

X

10-3 = 0.09% FS range.

Aperture uncertainty is the variance of the
aperture time, the uncertainty in the time interval. This parameter varies from unit to unit and
typically ranges from 0.5 to 10 nsec. In this
question, you see that aperture uncertainty
becomes very important to consider in simultaneous 5/H applications. This approach gives you a
better grasp of worst-case errors. To conclude,
aperture time· is an important parameter to
consider when sampling one channel with a
fast-changing signal, and aperture uncertainty
becomes important when performing simultaneous sample-holds.
8. 5.ettling time and acquisition time tend to
assume the same value because the output as well
as the input controls the charge on the hold
capacitor for closed-loop circuits.
9. Extremely good accuracy, slow acquisition
time and low droop rate best describe the
characteristics of closed loop integrating-type 5/H
circuits. High tracking accuracy results from a
configuration that acts like one amplifier during
the sampling time. Also, because an integrator is
used, the sample/hold switch operates at ground
potential, eliminating leakage problems through
the feedback hold capacitor and thus reducing
the droop rate i/C.
10. A single-pole transfer function with gain=1
and a -3 dB BW=500 kHz has the input/output
relationship
V(out)
V(jn) =

+.(J 5

X

f

JM

)

10'

To maintain 12-bit (0.01%) accuracy, V(out)/
V(in), or gain, should not degrade more than
(1-0.01%) =0.9999. Thus,
1

+

;(5 xf 10')

,;; 0.9999,

or f, the maximum sampling frequency, should
not exceed 7071.6 Hz.
11. Data sheets will most likely omit band c.

241

GM

242

5. High Speed

Operational
Amplifiers

243

244

High-speed op ampsthey're in a class by themselves
The same special characteristics that make fast op amps useful in
difficult applications can also create problems for unwary designers.

Fast operational amplifiers are not like other op
amps. In addition to good dc characteristics such
as high open-loop dc gain, low bias currents and
low input offset drift, fast op amps have specially
designed ac characteristics that come into play at
high frequencies. Proper application of these
amplifiers involves the selection of gainbandwidth product, slew rate, settling time and
output current. In addition, you must pay particular attention to many small circuit details like
power-supply bypassing, proper routing of
grounds, short lead lengths and minimization of
stray capacitance. Poor design practice invariably
produces an oscillator instead of a high-speed
amplifier.
You can't ignore op-amp characteristics
Operational amplifiers offer designers one
fundamental attraction: The characteristics of the
closed-loop feedback circuit are determined
almost exclusively by external circuit elements
rather than by the op amp itself. Precise control of
gain, offset, linearity, temperature stability, etc.,
in amplifier design itself thus reduces the user's
task to the proper selection of the passive circuit
components used around the op amp. Unfortunately, this simple relationship in general doesn't
hold true for high-speed op amps: They're more
difficult to handle than their low-frequency
counterparts, and a detailed knowledge of their
characteristics becomes essential:
Open-loop gain and IMndwidth-Refer to Fig.
t's gain-frequency (Bode) plot. The open-loop

1M+--_~
lOOk
_10k
~
~
Z 1k

~

100
10

10

00

lk

10k

100k

1M

FREQUENCY (Hz)
BREAK DUE TO
HIGH FREQUENCY
POLE

Fig. 1-Well desillned hillh-speed op amps have a smooth 20
dB/decade roll-off. Additional amplifier poles should not
occur until well beyond fT'

gain must be very high in a fast operational
amplifier to reduce errors at the device's summing junction. Open-loop gain typically runs
between 10' and 10" V/V in a good quality,
high-speed op amp. As illustrated, the gain is flat
from dc out to a corner frequency (100 Hz in this
case); then it decreases with increasing frequency. For well-designed amplifiers, gain decreases
at a fixed rate of 20 dB/decade of frequency, a
roll-off rate that assures stable closed-loop operation and also produces the best settling-time

245

DATA ACQUISITION & CONVERSION HANDBOOK

performance.
The gain-frequency plot crosses the gain-ofone axis at unity gain frequency, fT' This frequency should be as large as possible for a wide-bandwidth amplifier; 100 MHz is common. Along the
20 dB/decade slope of the gain roll-off, the
product of gain and frequency remains constant
and equal to h. Therefore, the value of fT is
frequently referred to as the gain-bandwidth
product of the amplifier.
Smooth roll-off is generally maintained out
beyond fT for most fast amplifiers. Another
op-amp pole usually occurs at a higher frequency
as a result of a non ideal amplifier circuit, but if
this frequency is considerably greater than the
circuit's closed-loop bandwidth, the extraneous
pole will have very little effect on high-frequency
performance.

OVERSHOOT

Fig. 2-Slewing time must be induded in

Slew rate-The ability of a high-speed op amp
to reproduce fast, large signal outputs depends
primarily on its specified slew rate, the maximum
rate at which the output can change, expressed in

V/(J-sec. When the output must respond to a
step-input change, slew-rate limitation causes a
longer large-signal settling time than you might
expect from the bandwidth characteristics alone.
Slew rates of modern high-speed op amps equal
or exceed 1000 V/(J-sec.
Settling time-In servo theory this term specifies the maximum time required to achieve an
accuracy of 5% or so after a step input is applied
to the servo. With regard to op amps, it refers to
the time required for much greater accuracies,
typically 0.1% to 0.01% of F.S., and is best
defined as follows:
"Settling time is the elapsed time from the
application of a step input to an amplifier to the
instant when the output has entered into and
remained within a specified error band around its
final value." Note that settling time must be
specified with both the error band and the
magnitude of the step change given. Almost all
cases specify a F.S. output change of 10V.
Fig. 2 illustrates a typical settling response for a
high-speed op amp. Usually the amplifier's output first goes into slew-rate limit, overshoots its
final value, then enters the specified error band
and remains there until it reaches the final
steady-state level. (One word of caution: Measure settling time from t=O, the instant that the
input step was applied. Some manufacturers play
"specmanship" games and fail to include the
amplifier slewing time in their measurements.)
You can't predict amplifier settling time from
bandwidth and slew-rate specifications alone: It's
a measured, as well as designed-in, parameter.
You can usually tell an op am p specifically
designed for fast settling time from one that's
not: The former's settling-time spec will be fairly
predictable from bandwidth and slew-rate considerations; the latter's won't.

Today's fast op amps ARE fast
Modular op amps introduced in the late
1960's featured settling times as low as 1
fJ.sec to 0.01%, and they quickly became
popular in 12-bit data-acquisition systems.
Early in the 1970's, ultrafast modules became
available, boasting even faster settling times,
100 MHz gain-bandwidth products and 1000
V/fJ.sec slew rates. More recently, hybrid
units have achieved such performance levels, as shown below.

BASIC CHARACTERISTICS OF A TYPICAL HIGH·
SPEED OP AMP (AM-500)
DC OPEN·LOOP GAIN ......... 106 V/V
GAIN-BANDWIDTH PRODUCT .... 130 MHz
SLEW RATE . . . . . . . . . . . . . . . . 1000 V/I1SEC
FULL POWER FREQUENCY
(20V pop) . . . • . . . . . . . . • . 16 MHz
SETTLING TIME. 10V TO 1% .... 70 nSEC
SETTLING TIME. 10V TO 0.1 % ... 100 nSEC
SETTLING TIME. 10V TO 0.01% .. 200 nSEC
INPUT OFFSET DRIFT .•....... llJVtC
OUTPUT VOLTAGE

settling~time

measurements.

.

.........• ±10V

OUTPUT CURRENT ........•.. ±50 rnA

246

2R

v,.o---_--.....--f'o..
(10Vp-p

AT 10MHzJ

....

>~

V,.o---'IW~"""----l

4.92V'l.

OVOUT
(20V p-pAT

10MHz)

fig. 3-The summing junction is NOT a virtual ground in high
speed op·amp applications. Thus the amplifier must be

fig. 4-Slaying within an amplifier's lOR avoids slew-rate
limitation problems and produces a smooth output response.

designed with a large input dynamic range (lOR), or distortion,
limiting or clipping will result.

step appears at the summing junction divided by
a factor of two by the two equal-value resistors.)
To further appreciate the significance of input
dynamic range, you must understand that within
this input range the op amp's output rate of
change is in direct proportion 10 the input
voltage. Therefore, the output can make a large
voltage transition in the time required to make a
small voltage transition. Fig. 5 illustrates three

Low output impedance and high output
current-High-speed operational amplifiers almost always are designed to give low output
impedance and relatively high output current.
low output impedance proves critical to stability
for driving capacitive loads, while high output
current (20 to 100 mAl is required for both driving
capacitive loads at high speed (I=Cdv/dt) and for
driving relatively low-value feedback and load
resistors. (Good high-frequency design practice
keeps all impedances as low as possible to cut
phase shifts from parasitic capacitances.)
Why is input dynamic range importanlf
Fig. 3 shows a simple, high speed op-amp
circuit with an inverting gain of 2 to illustrate an
important device characteristic. The signal input
is a 10V pop sine wave at 10 MHz; the output, an
inverted 20V pop sinusoid. If we assume that the
amplifier has the Bode plot shown in Fig. 1, then
its open-loop gain at 10 MHz is 10. So for a 20V
pop output, the voltage at the op amp's summing
junction must be 2V pop. This is a rather large
signal; in fact, most general-purpose op amps
couldn't handle such a high level without distorting, limiting and/or clipping. Therefore, highspeed op amps must possess a large input
dynamic range; i.e., significant peak-to-peak
voltages applied directly across the device'S input
terminals must not cause the output to slew-rate
limit or distort. Calculation of a high-speed op
amp's input dynamic range is straightforward (see
box at right).
Knowing the input dynamic range of an operational amplifier can help you determine how to
best utilize the device while carefully avoiding
slew-rate limitation problems. For instance, Fig. 4
shows an op amp connected as a unity-gain
inverter. If we assume that this device has an
input dynamic range of ±1.23V (as calculated in
the box), then the circuit can reproduce a 4.92V
input step as a -4.92V output step without
slew-rate limiting. (Observe that the 4.92V input

lOR is a function of SR and GB
The input dynamic range (lOR) of a highspeed op amp is related to the unit's slew
rate (or full-power frequency) and its gainbandwidth product. To compute lOR, assume that the output is at its full power
frequency and amplitude (i.e., it's producing the largest and fastest output possible
without distortion), then calculate the
open-loop gain at this frequency, and finally
plug these values in the following formula:
IDR= (V•• x FPF)/GB
where Vpp=peak-Io-peak full-power voltage, FPF=full-power frequency and
GB=gain-bandwidth product.
If the full-power frequency is not known,
you can use an alternate equation:
IDR= V•• xSR/(201rGB)
where SR=slew rate.
EXAMPLE
What is the input dynamic range of the
amplifier described in the previous box (the
AM-SOO)?
IDR=(20X16 MHz)/130 MHz = 2.46V pop
(or ±1.23Vl.
Thus,withinan input range of ±1.23V, the op
amp won't go into slew-rate limitation.

._---_._-_..._------------'

247

DATA ACQUISITION & CONVERSION HANDBOOK

SLEW RATE LIMITING

gain-bandwidth product and its noise gain in the
application. "Noise gain" is defined as the gain of
the closed-loop amplifier to voltage noise or to
any other signal inserted in series with one of the
amplifier inputs (Fig. 7).
.R

v,.
VOLTAGE NOISE
OR OTHER
VOLTAGE SOURCE

TIME

Fig. 5-Rise times for pulses of varying heights remain
constant as long as you observe lOR limits.

values of output steps for a fast op amp. Output
steps 1 and 2 have identical rise times; since they
lie within the IDR, they aren't slew-rate limited.
Because Output 3 is generated outside the IDR,
however, slew-rate limiting occurs, and the
output takes considerably longer to reach its final
value. Further, the waveform exhibits some
overshoot, a common problem under slew-rate
limit conditions.
It's no trivial task to design an op-amp input
circuit that has good dc characteristics, plus good
input dynamic range, plus the response needed
to avoid slew-rate limiting. One approach combines the low-drift characteristics of a bipolar
input op amp with the excellent IDR of an FET in a
fast-feedforward design (Fig. 6). This circuit
produces very wide bandwidth, high slew rate
and fast settling time. It also provides extremely
high open-loop gain and very low input offsetvoltage drift (typically 1 /J.V/"C).

.R

NOISE GAIN = 1 +Fr'= 1 + a

Fig. 7-Noise gain and signal gain differ. In an inverting circuit
the noise gain equals the Signal gain plus one.

The noise gain drawn on the Bode plot of an op
amp determines the -3 dB closed-loop bandwidth. In Fig. 8, for example, closed-loop gain
equals 99, giving a noise gain of (1 +a) or 100.
When plotted on the diagram, this noise gain
gives a closed-loop 3 dB bandwidth of 1 MHz for
the 100 MHz gain-bandwidth amplifier illustrated.
(Note that for the common unity-gain inverting
amplifier, the noise gain is 2; therefore the
closed-loop bandwidth of such a circuit built with
a 100 MHz op amp would equal 50 MHz, not 100
MHz.)

A single pole simplifies response calculations •••
If an op amp has a true single-pole response (as
many do), you can calculate its step response for
the closed-loop circuit by the expression:
EOl..,.=aE" (l-e -hf.,./(Ha»
and the output error is then
E = e -2ntrl(1+a)

-'N
99R

l M t - - -........
lOOk
"N
10k

z

~

lk

100

Fig. &-Fast...feedforward amplifier design combines a lowdrift,. bipolar Ie op amp with an FET feedforward stage to
produce excellent de and ac characteristics.

10

,

1~--~~---+---r--~--~--~~----­
10
10n
lk
10k
tOOk
1M
10M 100M

Your choice should start with bandwidth
When you select a high-speed operational
amplifier, first determine your application's bandwidth requirement. The minimum closed-loop
bandwidth is a function of both the op amp's

FREaUENCV (Hz)

Fig. 8-1f the op amp exhibits a single-pole response, you can
compute its settling time from frequency and noise-gain data.

This approach works best at high noise gains.

248

35

r _____ -I~:l:.F.?~~E~~~~I~~~PACITOR

30

,I

aR

I

v,.

,.
o.OOl~

O.QI)45"
10

l'

0.D0081%
12

Fig. 10-Three sources of extraneous poles appear in this
diagram: input capacitance, load capacitance and the op amp
itself. C z compensates for output ringing and is best chosen
via experiments with the actual circuit components and

Fig. 9-0utput error decreases predictably as a function of the
number of time constants when the opMamp circuit exhibits a
singJeMpoJe response.

layout.

From the latter equation you can readily
compute the settling time to various accuracies.
For greatest convenience, perform this computation in terms of the time constant T = (a+1)/2"11"f,.,
where a is the closed-loop gain. The amplifier
configuration of Fig. 8, for instance, has a time
constant (T) of 159 nsee.
Fig. 9 shows the number of time constants
necessary to reach a given error, assuming a
single-pole response. Thus, the amplifier configuration of Fig. 8 would take nine time constants or
1.44 f.Lsec to settle to 0.01 % . If the same amplifier
(GB=100 MHz) were connected as a unity-gain
inverter, its closed-loop bandwidth would equal
50 MHz, giving T =3.2 nsec and a settling time to
0.01% of 28.8 nsee.
Using the ideal single-pole response with no
slew-rate limiting to determine settling is a valid
approach. At worst it gives a first approximation
of the settling time, and this approximation gets
closer at high noise gains. Given an op amp
designed and specified for fast settling, you can
obtain an even closer approximation by adding to
the computed settling time that estimated extra
time required to slew to the final voltage.

... but multiple poles often occur
In some cases the op-amp circuit is not really a
single-pole system. Fig. 10 shows three typical
situations that add a second pole to the circuit. C,
represents the input capacitance of the amplifier
plus any stray capacitance from the summing
junction to ground, as well as (where applicable)
the output capacitance of the device driving the
op amp. C, combines with resistances Rand aR to
produce a pole located at -aRC,/(a+1) on the real
axis of the s-plane. The finite output resistance of
the amplifier, Ro, and load resistance RL com-

249

bined with output capacitance CL can add another
pole located at -RoRI.CL/(Ro+Rd. And the op amp
itself can add a third extraneous pole if it has an
extraneous high-frequency pole in its response as
noted.
In general, one of these "extra" poles will be
dominant; i.e., closer in frequency to the amplifier's unity-gain frequency than the others. This
dominant pole, of course, converts our firstorder system into a second-order one and brings
up the pOSSibility of complex conjugate poles that
produce ringing.
When ringing occurs, the amplifier must be
compensated by a feedback capacitor (Fig. 10).
You can determine experimentally the optimum
value for this compensation capacitor by observing the step response and adjusting a trimmer to
eliminate the ringing. Normally you want a
damping ratio of one, but in some applications
you may actually prefer a small amount of
overshoot.
Calculations reveal that if the frequency of the
second pole is at least 4x the op amp's closedloop bandwidth, the damping ratio will equal or
exceed one, and overshoot won't occur. Since
often you can quickly approximate the frequency
of the extraneous pole, you can use this relationship to predict ringing in the circuit.
In the common situation where input capacitance C, causes the second pole, a good starting
value for compensation capacitor C, is C,=C,/a.
Increase C, as necessary above this value to
achieve a damping ratio of one. (The other two
possible extraneous poles, even when they don't
dominate, may still add some phase lag to the
amplifier. This possibility explains the somewhat
higher value of C, often needed to give the
required compensation.)

DATA ACQUISITION 81 CONVERSION HANDBOOK

Success is just a design tip away
We conclude our discussion by offering six
brief, but important, hints on applying highspeed op amps:
•

•

•

•

•

Keep all component leads as short as
possible, particularly at the summing junction. Also, diligently strive to keep stray
capacitance at the summing junction to an
absolute minimum.
Separate signal grounds from power
grounds, connecting them only at one
common physical point.
If you must locate the source or load some
distance from the op amp, use properly
terminated coaxial cable for best response.
If you mount the op amp on a pc board,
incorporate a ground piane into the board's
design for best performance.
Make the input and feedback resistors as
small as possible consistent with inputsource drive capability and amplifier-output
drive capability. A value in the range of 500
to lO00n is commonly used for the input
resistor.
Use good power-supply bypass capacitors
and connect them right at the amplifier
power-supply pins. We recommend tantalum capacitors in parallel with ceramics.
GZ JK

250

Using The ICH8500 Ultra
Low Bias Current Op Amp
The Pico Ammeter
A very sensitive pico ammeter can be constructed with
the ICH8500. The basic circuit (illustrated in Figure 1)
employs the amplifier in the inverting or current
summing mode.

circuit is approximately the product of the feedback
capacitance Cfb times the feedback resistor Rfb. For
instance, the time constant of the circuit in Figure 1 is 1
sec if Cfb = 1 pF. Thus, it takes approximately 5 sec (5
time constants) for the circuit to stabilize to within 1%
of its final output voltage after a step function of input
current has been applied. Cfb of less than 0.2 to 0.3 pF
can be achieved with proper circuit layout. A practical
pico ammeter circuit is illustrated in Fig.ure 2.

Care must be taken to eliminate any stray currents
from flowing into the current summing node. This can
be accomplished by forcing all points surrounding the
input to the same potential as the input. I n this case the
potential of the input is at virtual ground, or OV,
therefore, the case of the device is grounded to
intercept any stray leakage currents that may
otherwise exist between the ±15V input terminals and
the inverting input summing junctions. Feedback
capacitance' should be kept to a minimum in order to
maximize the response time of the circuit to step
function input currents. The time constant of the

The internal diodes CR1 and CR2 together with
external resistor R1 protect the input stage of the
amplifier from voltage transients. The two diodes
contribute no error currents, since under normal
operating conditions there is no voltage across them.
'Feedback capacitance is the capacitance between the output and
the inverting input terminal of the amplifier.

Cfb

Rfb=1012 n

......o::---------<~-- OUTPUT

CURRENT

SOURCE

Vo '" -liN Afb

"-1 VOL TJpA

CURRENT/
SUMMING
NODE

Figure 1. Basic Pica Ammeter Circuit
+15V

R,
INPUT

--

1M!)

r-------"Y......- - - - -.....- -.......>-----! .....~---__- - - -......- - - - O U T P U T
Vo '" -liN

I,"

It

1012n

=-1 VOlT/pA

CRl

CR'

INTERNAL

DIODES
2Ck!l

-15V

Figure 2. Pica Ammeter Circuit

251

Sample and Hold Circuit (Figure 3)

The basic principle of this circuit is to rapidly charge a
capacitor CSTO to a voltage equal to an input signal.
The input signal is then electrically disconnected from
the capacitor with the charge still remaining on CSTO.
Since CSTO is in the negative feedback loop of the
operational amplifier, the output voltage of the
amplifier is equal to the voltage across the capacitor.
Ideally, the voltage across CSTO will remain constant,
thus the output of the amplifier will also be constant,
however, the voltage across CSTO will decay at a rate
proportional to the current being injected or taken out
of the current summing node of the amplifier. This
current can come from four sources: leakage
resistance of CSTO, leakage current due to the solid
state switch SW2, currents"due to high resistance paths
on the circuit fixture, and most important, bias current
of ttie operational amplifier. If the ICH8500A operational amplifier is employed, this bias current is almost
non-existent «0.01 pAl. The voltage on the source,
drain and gate of switch SW2 being zero or near zero
when the circuit is in the hold mode, results in a negligible switch leakage current. Careful construction will
eliminate stray resistance paths and capacitor resistance can be eliminated if a quality capacitor is
selected. The net result is a quality sample and hold
circuit.

As an example, suppose the leakage current due to all
sources flowing into the current summing node of the
sample and hold ci rcuit is 100pA. The rate of change of
the voltage across theO.01 p.F storage capacitor is then
10mV/sec. In contrast, if an operational amplifier
which exhibited an input bias current of 1 nA were
employed, the rate of change of the voltage across
CSTO would be 0.1 V/sec. An error build up such as this
could not be tolerated in most applications.
Wave forms illustrating the operation of the sample and
hold circuit are shown in Figure 4.

The Gated Integrator
The circuit in Figure 3 can double as an integrator. In
this application the inpui voiiage is appiied to the
integrator input terminal. The time constant of the
circuit is the product of R1 and CSTO. Because of the
low leakage current associated with the ICH8500 and
ICH8500A, very large values of R1 (Up to 1012 ohms)
can be employed; this permits the use of small values of
integrating capacitor (CSTO) in applications that
require long time delays. Waveforms for the integrator
circuit are illustrated in Figure 5.

R,b CAN BE REDUCED TD 10K
IF CIRCUIT IS EMPLOYED AS
AN INTEGRATOR

R'b
'OOk{l
0.01')6
INPUT TERMINAL
IF CIRCUIT

AS AN

:~i~~~~ig~

CHARGE
STORAGE
CAPACITOR

>--NY-+-----------,

VIN",OTO:l:10V

Coro

/

O.01~F

SW2
1T1700
INPUT TERMINAL
IF CIRCUIT
IS EMPLOYED
AS A SAMPLE AND
HOLD CIRCUIT
VIN = OTO ±10V

l00kO
0.01%

........:----o---<~- OUTPUT

•

IT1700

+15V
10pF

V2

15kO

-15V

V,

'0""

CNULl;;:' lpF

-15V

'Mil
-::"

V,

V'N>---C
SAMPLE

ITI700

PULSE OR
CAPACITOR
OISCHARGE
PULSE
-::"

t-----------------'

ADJUST CNULl TO ELIMINATE
ANY OUTPUT OFFSET VOLTAGE
DUE TO CHARGE INJECTION
FROMSW2

15kO

":"

-t5V

Figure 3. Sample and Hold Circuit or Integrator Circuit

252

WAVEFORMS

VIN

+5:

-.J

bl

"15V---1
V,
dl

V3

,I

STATE OF
SW'

bl

~

v,
-15V

,I

I ----'I

II

dl

91

hi

I

V3

I

I

I,

II

II

II~SED

='---

STATE OF

CLO~

II

~OPEN

__

i~SED

SW'
i--CLOSED-j

OPEN

~SAMPLE

STATE OF
SW2

~I

WINDOW

INPUT TO +16V - - - - - - - - " " ' \
SOH
0 _______
....._ _ _ __

OUTPUT

I

-15V

~-OPEN---,"'
OPEN

f'L-

t15V~1

I--CLOSEO--\

STATE OF
SW2

TIME_

V2 -15: ~

t

CLOSED ,:

SAMPLE PULSE

I

'15V~1
:
I
-15V

~

+15V

0-,II.
-15V

'SV

VIN

TlME _ _

1\

V,·'SV

,I

L1_ _S;..A_M_P;..LE_P..;U_L_SE_

g)

0,,= --------

INTEGRATOR
CIRCUIT
INPUT

0

I~

~SAMPLE

WINDOW

_ _ _ _ _ _ _ _ _ _ _ __

-lOY - - - - - - - - - - - - -

OP. AMP.

+6V - -

o

Figure 4. Sample and Hold Circuit Waveforms

= ______ _

_ L -_ _ _

Figure 5. Gated Integrator Waveforms

253

The ICL8007 A High Performance FET Input Operational Amplifier
INTRODUCTION

Another feature of the input design which deserves comment
is the method of offset adjustment. To minimize the
temperature coefficient of the input offset voltage, it is
imperative that the current through the two FET's be closely
matched. Any attempt to compensate for initial offset by
mismatching the FET drain currents will result in excessive
temperature drift. The best place to implement the offset
nulling is in the PNP stage, provided that 03 and 04 are fed
from a low temperature coefficient current source; zeroing
the offset will have no detrimental effect on the drift.
Input Current
The input current of the ICL800? is typically less than 3 pA; it
is selected for an input current of 1 pA maximum at 25° C. As
with any junction FET input amplifier, this current approximately doubles for every 10°C increase in temperature, as
shown in Figure 2.

During the last 10 years the Field Effect Transistor has
become the accepted device for amplifying low level
currents. Until recently, however, high performance FET
amplifiers have been available in only relatively expensive
module or discrete form. With the introduction of the
ICL800?, the first inexpensive high performance FET input
OPAMP, Intersil has provided a device for use in those
applications previously considered impossible due to cost
factors. It is extremely easy to use, is a pin for pin
replacement for the popular ?41 (Ref 1), has internal
compensation, and is short circuit protected. The ICL800? is
available in a hermetic T05 type package and is ideally
suited to both military and commercial applications.

C)RCUIT DESCRIPTION
Input Stage DeSign
Figure 1 shows a simplified schematic of the ICL800? Itisa
two stage-circuit with a class AB complementary output and
internal phase compensation.
The input stage consists of two bootstrapped FET source
followers driving a lateral PNPemittercoupled pair. By using
the FET's in the source follower mode, run to run variations
of gm have no influence on the stability. The bootstrap serves
a dual purpose: itensures excellent common mode rejection,
and also prevents excessive gate currents. The latter
problem is frequently seen in FET amplifiers, where at one
end of the common mode range the FET sees large drain to
source voltages.

Summary of Characteristics (Typ. at 25° CI

ICL8007M

ICL8007C

10
2.0
106
90
±12
6.0
1.0

20
3.0
106
90
±12

Input Offset Voltage
Input Bias Current
Input Resistance
Common Mode Rejection
Input Voltage Range
Slew Rate
Unity Gain Bandwidth

<
S:

6.0
1.0

ICL8007AM a
ICL8007AC UNITS
15
mV
0.5
pA
106
Mil
95
dB
±12
V
6.0
VI!'s
1.0
MHz

1 nA

!z

w
::il00pA

i3
5
~

10pA

1 pA
20

40 60 80 100 120 140
TEMPERATURE ('C)

Figure 2: Input Bias Current as a Function
of Temperature

Figura 1: ICLa007 Simplified Schematic

254

Input Offset Voltage Drift
The input offset voltage drift of an FET amplifier is inherently
worse than that of a well-designed bipolar circuit The
ICL8007M and ICL8007C are guaranteed to have
temperature coefficients of less than 75J.1V/oC, while the
ICL8007AM and ICL8007AC are specified at 50J.lV/oC
maximum. Practically the whole of the manufacturing
distribution falls within these limits, and it is straightforward
to screen for tighter limits on a custom basis.
Noise Performance
The total mean square noise of an operational amplifier for a
bandwidth j.f = f2 - 1, is given by
e2T =

J ~(en)2 df +
f1

RS2

J ~(jn)2 df + 4kTRs
f1

. -_ _
1/",2..;;OF IT,,1"-20'--_ _

6

2 kll

>"-4-.JV'<./\r-+--QVOUT

Figure 4: Basic Log Amplifier

Ilf (1)

where Rs is the source resistance, en is the input-referred
noise voltage generator, and in is the input-referred noise
current generator. Typical values for en and in are compared
with the 741 in the table below.
en (at 10 Hz)
200 nV/\/Hz
25 nV/vHz

8007
741

§ 10DO
>
..=,
w 100

VOUT

in (at 10 Hz)
< 0.1 pA/VHz
0.7 pA/VHz

==

BANDWIDTH
~ 10 Hz TO 100 kHz-:

Figure 5: Basic Antilog Amplifier
It can be seen from equation 4 that each factor of ten change
in collector current produces a 60mV change in VBE. For a
low leakage silicon transistor such as the IT120, this
relationship holds true over a surprisingly wide dynamic
range: 10 decades (0.1 pA to 1 mAl is quite common. Ref (3)
contains an excellent discussion of the principles and
limitations of this type of log amplifier.
At the low current end of the range, the accuracy of the
circuit in Figure 4 is primarily dependent on the amplifier
input current, making the FET input type an obvious choice.
At high currents, accuracy is finally limited by base
resistance and current crowding effects in the "log"
transistor. Figure 6 shows the inputloutputcharacteristics of
such an amplifier.
In the majority of applications where the logarithm function
is used, the antilogarithm is subsequently derived. In such
applications, the temperature dependence of equation 3 is
usually unimportant, provided the log and antilog transistors
are in good thermal contact. A monolithic transistor pair
such as the IT120 will ensure the required thermal tracking.
However there are occasions when direct readout of a log
function is called for, and unless compensated, the
temperature dependence of equation 3 becomes a serious
limitation. Ref 4 contains a more detailed discussion of this
problem, and outlines some temperature compensation
techniques. One of these is used in the photo cell amplifier
which follows.

~

 1M!ll where in
dominates, the FET input is superior to a general purpose
bipolar design such as the 741. The input-referred current
noise in the ICL8007 is so low that accurate measurement is
difficult. For source impedances between 1M!l and 50M!l,
the total noise shown in equation 1 is dominated by the third
term, the thermal noise of the feedback and source resistors.
This is of course independent of the amplifier itself.
The total input-referred noise is shown as a function of
source resistance in Figure 3.

APPLICATIONS
1) Log and Antilog Amplifiers
An application which illustrates the advantages of low input
current is the log circuit of Figure 4 and its antilog counterpart, Figure 5.
These circuits make use of the well known logarithmic
relationship between the base-emitter voltage and the
collector current in a transistor (equation 2):
VBE = (mkT lin!£
q
Is

)Qn IC2
IC1

Hence

/lVBE ={ mkT
\ q

at 25°C

/lVBE = 60 10glO I'C1 mV
C2

10- 2

~ ~~: 4
!z 10- 5
3

1/

TA~25°C

/

V

~ 10-6
/
~ lO- 7
u 10-8
1/
!:; 10-9
/
~10-1 0
-10-1
10- 1
100 200 300 400 SOD 600 700 8DO
OUTPUT VOLTAGE (mV)

(2)

;r ...

(3)

(4)

Figure 6: Transfer Characteristic of a Log Amplifier
255

discharge rate is a function of the amplifier input current.
Two long time constant peak detectors are shown. Figure a
shows a circuit having an input resistance of around 40Mn
and provides an output in phase with the input; figure .9
shows an inverting version of the same circuit. Although the
input resistance is reduced to 10Kn, there are no common
mode errors due to the 741 since it is operating as a virtual
ground amplifier. Note that in both cases the initial offset of
the ICLa007 is automatically nulled out. The typical output
voltage decay rate for either circuit is less than 1mVlmin.

2) Photocell Amplifier
Figure 7 shows a light meter which directly displays the log
of the light intensity as an Exposure Value.' The silicon cell is
operated at zero voltage to minimize leakage errors. Rl and
R2 form a temperature sensitive gainblock, thus
compensating the kT/q term in equation 3. The output reads
EV -3 to EV +18 (@ ASA 100) on a SOOILA meter.
3) Peak Detector
Both peak detectors and sample & hold circuits benefit from
the use of an FET input amplifier since the capacitor

'Th is is a photographic term. Each unit change of EV corresponds to
a factor of two change in light intensity.

lSOk!!
J.=..!.......o\"",-o+15V

SHARP
SBC

10k!!

2020

Your
R2
TEMP. COMPENSATED
lkl! RESISTOR
'TEL LABS TYPE 081

150k!!

1

1
Figure 7: Sensitive Photometer

Figure 8: Non-Invertin\! Peak Detector

A sample and hold with input multiplexing can also be
designed using low cost Intersil analog switches. In Figure
11, one channel of the IHS009 (Ref 6) is used to control the
sample and hold, whilethe other 3 channels control the input
multiplexing. Output voltage decay rates of about SmV/sec
can be achieved with this circuit.

4) Sample & Hold Circuits
A straightforward sample & hold circuit using the DG139A
analog switch (Ref S) is shown in Figure 10. During the hold
mode, the input amplifier is connected in unity gain to avoid
output saturation.
lOkI!

VOUT

5kl!
*IA

=

Your

I

10 pA max.
@ VR ~ 10V.

Figure 9: Inverting Peak Detector

Figure 10: Sample and Hold Circuit

lOkI!

ANALOG
INPUTS

O.Ol.F POLYSTYRENE

lOkI!

lOkI!

lOkI!

12

-

7

/

8

I.-",...-'

SAMPLE/HOLD CHANNEL
SELECT
SELECT

14

CHARACTERISTICS: TYPICAL OUTPUT
VOLTAGE DRIFT
<5mV/SEC

Figure 11: Sample and Hold With Input Multiplexing

256

5) High Impedance Buffer
Figure 12 shows a high impedance follower in which the
output of the amplifier is used to drive a shielded cable. This
circuit is used by Intersil to measure the performance of
MOSFET's at wafer sort. Since the amplifiers are situated
some distance from the probe tips, shielded cable is used.
The reduction in test speed normally associated with high
capacitance coax is eliminated by driving the shield in phase
with the input.

frequency is substantially less than the 1MHz small signal
bandwidth. It can easily be shown that for a sinusoidal
waveform described by equation 5 the maximum rate of
change of voltage is given by equation 6.

v=

Vo sin",t

(5)

~~

(max) = 2rrfVo

(6)

If the amplifier siew rate is less than dv/dt (max), distortion
will occur. An amplifier with 0.6V1lls slew rate will not handle
20V p-p signals above about 10kHz.
The ICL8007 has a typical slew rate of 6V1IlS, thus extending
the large signal operating frequency range by a factor of 10
compared with the 741. The undistorted output voltage
swing as a function of frequency is shown in Figure 13.
Figure 14 illustrates the large signal pulse response
characteristics.
The Wein Bridge Oscillator of Figure 15 makes use of the
high slew rate to provide a 20V peak to peakoutputat40kHz.
The amplitude may be controlled by R4; for smaller output
swings correspondingly higher frequencies can be obtained.

Your

V,N o--H----I-"t

Figure 12: Buffer with Screen Drive

6) Weln Bridge Oscillator
In many oscillator and other large signal applications, the
high slew rate of the ICL8007 may be used to advantage.
When using general purpose amplifiers, such as the 741, to
process signals with amplitudes greater than about 100mV,
the slew rate determines the upper operating frequency. This

:>

;;4
0
z
~

....

32

OF
Vsupp - ±15V

TA = +25°C

~ 8

RL

w

~

10k!!

~~

K24
5
o

~
o

~

....

16

4
0

Vsupp== ±15V
TA"" +2S0C

~

I

11

ll~Ul~~T

~-4

8

1
INPUT

-I-

JJJ.

0-8

0
lk

10k lOOk
1M
FREQUENCY (Hz)

o

10M

1 234 5 6 789
TIME (ps)

Figure 13: Output Voltage Swing as a Function of Frequency

Figure 14: Voltage Follower Large-Signal Pulse Response

Figure 15: Wein Bridge Oscillator

257

Using The ICL8043
Dual FET Input Op Amp

information stored on Cl can be "refreshed" relatively
infrequently. The measured offset voltage of Al during the
amplification mode was 11!'V; offset voltage drift with
temperature was less'than 0.1!,V/oC.

APPLICATIONS
Applications for any dual amplifier fall into two categories.
There are those which use the two-in-one package concept
simply to save circuit-board space and cost, but more
interesting are those circuits where the two sides of the dual
are used to complement one another in a subsystem
application. The circuits which follow have been selected on
this basis.

STAIRCASE GENERATOR
The circuit shown in Figure 2 is a high input impedance
version of the so-called "diode pump" or staircase generator.
Note that charge transfer takes place at the negative-going
edge of the input-signal.

AUTOMATIC OFFSET SUPPRESSION
CIRCUIT

The most common application for staircase generators is in
low cost counters. By resetting the capacitor when the
output reaches a predetermined level, the circuit may be
made to count reliably up to a maximum of about 10. A
straightforward circuit using a LM311 for the level detector,
and a CMOS analog gate to discharge the capacitor, is
shown in Figure 3. An important property of this type of
counter is the ease with which the count can be changed; it is
only necessary to change the voltage at which the
comparator trips. A low cost A-O converter can also be
designed using the same principle since the digital count
between reset periods is directly proportional to the analog
voltage used as a reference for the comparator.
A considerable amount of hysteresis is used in the
comparator shown in Figure 3. This ensures that the ."
capacitor is completely discharged during the reset period.
In a more sophisticated circuit, a dual comparator "window
detector" could be used, the lower trip point set close to
ground to assure complete discharge. The upper trip pOint
could then be adjusted independently to determinethepulse
count.

The circuit shown in Figure 1 uses one amplifier (Al) as a
normai gain stage, whiie the other (A2) torms part of an offset
voltage zeroing loop. There are two modes of operation
which occur sequentially; first, an offset null correction
mode during which the offset voltage of Al is nulled out.
Following this nulling operation, Al is used as a normal
amplifier while the voltage necessary to zero its offset
voltage is stored on the integrator comprised of A2 and Cl.
The advantage of this circuit is that it allows chopper
amplifier performance to be achieved at one-tenth the cost.
The only limitation is that during the offset nulling mode, Al
is disconnected from the input. However, in most data
acquisition systems, many inputs are scanned sequentially.
It is fairly simple to synchronize the offset nulling operation
so that it does not occur when that particular amplifier is
being "looked at". For the component values shown in Figure
1, and assuming a total leakage of 50pA at the inverting input
of A2, the offset voltage referred to the input of Al will drift
away from zero at only 40!,Visec. Thus, the offset nulling

+5V

130kll

+15V
11

16

1k!!

130k!!

c,
SW1*

8

1kll

/

/

~/----------~~----------~/

LOGIC
INPUT

10k!!

*SW" SW2,Il SW3 ARE ALL PART OF
A SINGLE IH5043 CMOS ANALOG
SWITCH CONNECTED AS SHOWN
IN FIGURE 38

/

Figure 1A

258

Figure 18

~

100kll

.01 F

.r. J"

~~~~-1r-~~~1

Ir-

V-

'oJ

-"" ---"

10100
LOW LEAKAGE
DIODE PAIR

~

I-

to-- r
VOUT

;..J

}

- - - - HORIZONTAL

~

(2V/DIV)

VIN
}

(5V1DIV)

50mS/DIV

Figure 2

IH5042

lkfl

~

1"'-~

lOOkll

10100
LOW LEAKAGE
DIODE PAIR

--- ""-- ~--

",

~

,,;-

'..,rl ~

VOUT VREF

Figure 3

259

~

~

-- --- ~-- --- -- ,..--""--HORIZONTAL

10kfl

VOUT

~

200mS/DIV

}

(5V/DIV)

VIN
}

(5V/DIV)

Actual sample and hold waveforms are shown in Figure 58.
The center waveform is the analog input, a ramp moving at
about 67V/ms, the lower waveform is the logic input to the
sample & hold; a logic "1" initiates the sample mode. The
upper waveform is the output, displaced by about 1 scope
division (2V) from the input to avoid superimposing traces.
The hold mode, during which the output remains constant, is
clearly visible. At the beginning of a sample period, the
output takes about 81J,sec to catch up with the input, after
which it tracks until the next hold period.

SAMPLE & HOLD CIRCUIT
Two important properties of the 8043 are used to advantage
in this circuit. The low input bias currents give rise to slow
output decay rates ("droop") in the hold mode, while the high
slew rate (6V/IJ,S) improves the tracking speed and the
response time of the circuit. See Figure 4.
The ability of the circuit to track fast moving inputs is shown
in Figure SA. The upper waveform is the input (10V/div), the
lower waveform the output (SV/divl. The logic input is high.

-15V

10
OUTPUT
ANALOG
INPUT

~511l

r

110,000 pF
POLYSTYRENE

13

12 +5V

11 +15V

10

+3V

IH5043

OV

~

~ >

SAMPLE MODE

> HOLD MODE

Figure 4

'"

1"'--0.,.

,

I

A

\

1\

\

..........

I"'- ho!...

k

i"""'- :---...

~

~

~

TOP: INPUT (10VlDIV)
BOTTOM: OUTPUT (5V/DIV)
HORIZONTAL: 10~O/DIV

TOP: 2V1DIV
CENTER: 2VIDIV
BOTTOM: 10VlDIV
HORIZONTAL: 10~O/DIV

Figure 5A

Figure 58
260

............

r--..... i"'o!!..

INSTRUMENTATION AMPLIFIER
A dual FET input operational amplifier is an attractive
component around which to build an instrumentation
amplifier because of the high input resistance. The circuit
shown in Figure 6 uses the popular triple op-amp approach.
The output amplifier is a High Speed 741 (741 HS, slew rate
guaranteed ?f).7V/p.s) 50 as to utilize the high slew rate of the
8043 to the maximum extent. Input resistance of the circuit
(either input, regardless of gain configuration) is in excess of
1012 ohms.
For the component values shown, the overall amplifier gain
is 200 (front end gain = 2Rl

+ R2,

Common mode rejection is largely determined by the
matching between R4 and Rs, and R6 and R7. In applications
where offset nulling is required, a single potentiometer can
be connected as shown in Figure 7.
Another popular circuit is given in Figure 8. In this case the
gain is 1 + Rl/R2, and the CMRR determined by the match
between Rl and R4, R2 and R3.

back end gain, = R6/R4).

R2

R.
10k

9.5k

Rl

lk

R2

lOOk

YOUT

9.5k

R3
Rs
10k

lOOk

Figure 6
+v
lOOk

lk

lk

lOOk

ALL RESISTORS .1%

-v

Figure 7

Figure 8
261

Using The 8048/8049
Log/ Antilog Amplifier
the current through the input resistor R1. The collector
current for 02 is set by R2 and the reference voltage, and
since the collector current of 02 remains constant, the
emitter base voltage also remains constant. Therefore, only
the emitter base voltage of 01 varies with a change of input
current. However, the output voltage is a function of the
difference in emitter-base voltages of 01 and 02.

GENERAL DESCRIPTION
A common problem in instrumentation and data
transmission is the processing of signals over a wide
dynamic range. The ICL8048 is designed to provide the
solution.
The 8048 is a complete DC logarithmic amplifier, consisting
of two FET input op amps and utilizing the fundamental
logarithmic properties of a transistor junction. It will handle
six decades of input current or three decades of voltage
input, is temperature compensated from O°C to 70°C, and
features adjustable scale factor, reference current and offset
voltage.
The 8049 is the anti-log counterpart of the 8048 and is
designed to supply one full decade of output voltage for each
1 volt change at the input. And like the 8048, the refere'nce
current scale factor and offset voltage are externally
adjustable.

(1 )

For matched transistors operating at different collector
currents, the emitter base differential is given by
kt
AVSE= q

J

...

IC1
IC2

-

(2)

Combining Equation 1 and 2 and writing the expression for
the output voltage gives

THEORY OF OPERATION (Figure 1 )
The logarithmic gain of the 8048 is derived from the inherent
exponential characteristics of a transistor junction.
Transistor 01 is used as the non-linear feedback element
around op amp A1 which has a FET-input stage to provide
low input current noise and very low input bias current.
Negative feedback is applied to the emitter of 01 through R4.
This forces the collector current of 01 to be exactly equal to

Va = R5

+ R3 (~);',.
R3

q

IC1 '
IC2

(3)

This shows that the output is proportional to the logarithm of
the input current, and hence voltage. The temperature
dependence is minimized by control of the temperature
coefficient of R5.

VREF ">---~v..i\,----o

I
200pF

-- --

I
I

R,

V,N
10

>---.._-+----<>

RS

15

Figure 1: 8048 A Complete Monolithic Log Amp

262

I
~

Vour

The basic schematic of the 8049 is shown in Figure 2. A3
forces 03 to operate at IREF, shifting down the emitter voltage
of 04 by the voltage applied to pin 2. The division ratio is
controlled by Rs and R7, thus the VBE of 04 will force a
collector current given by:
h
=gRs
IaUT -- IC(Q4) -- (I REF II> VIN ,were
I> -- kT(Rs
+ R71,

therefore giving the desired antilog dependence.
.A4, together with Re, acts as a current to voltage converter:
VaUT = Re(lREFI antilog (I> VINI
Again the temperature coefficient of R7 corrects for the
temperature dependence of 1>.

R,
VREF>-------~~~------~--------_,

200pF

----------,

I
16

14

I

V,N o-+~W'\r-__t--+------------+_----~

R9

RlO
VOUT

10

Ra

15

Figure 2: ICL8049 A Complete Monolithic Antilog Amp

SOURCES OF ERROR
Log Conformity Error: Log conformity error is the difference

the output voltage is seen on pin 16. Thisdoes not constitute
an appreciable error, provided VREF is much greater than this
voltage; a 10V or 15V reference satisfies this condition.
Alternatively, IREF can be provided from a true current
source. See Figure 3.
Bandwidth: The gain bandwidth product of the logging
element is relatively constant, and a change in gain will vary
the bandwidth. Gain changes occur when input current to
the logging elements varies with signal level. Consequently,
slew rate and frequency response are specified as a function
of input signal level and will vary accordingly.
It should be noted that zero collector current in the logging
element for zero signal current is not the preferred condition,
particularly if the input terminal is to be multiplexed and a
rapid rise to the end value of output voltage is important. The
rise time, in decades of collector current per second, is
approximately proportional to collector current;
accordingly, if the collector current had to start up from zero,
the rise to the output voltage would take an undue length of
time. This can be prevented by injecting a collector rest
current equal to 1% of the lowest current to be measured.

between actual output voltage and the output voltage
predicted by the log transfer equation. A plot of input versus
output should be a straight line (when plotted on semi log
paper), with a slope kT/q(60mV/decadel. Any deviation from
this straight line is log conformity error.
Offset Voltage (Vas): The offset voltage of the internal FET

amplifier. This voltage appears as a small DC voltage in
series with the input terminals. For current logging
applications, its error contribution is negligible, however for
log voltage applications, best performance is obtained /)y
nulling Vas.
Reference Current (IREF): IREF is the current generated by R2

and VREF (Fig. 1) to which all input currents are compared.
IREF tolerance errors appear as a DC offset at the output; a
±1% IREF error, referred to the input, corresponds to a DC
offset of ±4.3mV at the output. This offset is independent of
input signal.
When a resistor is used to generate IREF, as shown in Fig. 1,
pin 16 is not a true virtual ground. For the 8048, a fraction of
263

ONE QUADRANT DIVIDER
Computing the ratio of two analog voltages can be done with
general-purpose analog multipliers, but the accuracy
decreases if the denominator varies over a wide range. With
log-amps, a one-quadrant divider with a better full-scale
accuracy over a dynamic range of 100:1 can be designed,
and with the flexibility of external adjustments, the scale
factors are readily adjustable and the circuit can easily be
optimized for other ranges.
The circuit in Figure 1 may be used as divider or reciprocal
generator. The output of the 8048 is actually the ratio of the
input current and the reference current through R2, when
used as a log generator, the reference current is held
constant by connecting R2 to a fixed voltage. If R2 is driven
by an input voltage, rather than the 15V reference, the output
of the 8048 is the log ratio of the input current to the current
through R2. The antilog of this output voltage is the ratio of
the inputs.

~~:)~

A·complete one quadrant divider is shown in Figure 3.lt is the
log amplifier (8048) shown in Figure 1 driving the antilog
amplifier (8049) shown in Figure 2. The log amplifier output
drives the base of 03 with a voltage proportional to the log of
E1/E2. Transistor 03 adds a voltage proportional to the log of
E3 and drives the anti-log transistor, 04. The .collector
current of 04 is converted to an output voltage by A4 and Rs,
with the scale factor set by Rs.

E1
VOUT = 10E2

(4)

Note that the current corresponding to E2 is derived from a
true current source to avoid the errors discussed above
under "reference current".

10k
______-4____~~~
__~~________________________-,

2k

16

I

-- --

I

200pF

I

Rl
V,N
10k

~--~~-------Q10

200pF

Rs

-----

1---__-o-__'....S"M"I,..l__--'EJ""( ~~i~

I

-

-_-_-=--+~_~-

1.-

.-----------~--------------;---~14

16o----+~VV~~----+-------------~----~

R6
10k

~----t---O 10 Vour

I
L
1S

FlguIV 3: Complete One Quadrant Divider Using an 8048 Log Amp and an 8049 Antilog Amp

264

VOUT=~

ARBITRARY POWER LAW CIRCUIT
Log amplifiers are an excellent means of computing Y = xO'
relationships. Powers or roots may be computed precisely
by cascading a log amp (8048) and antilog amp (8049) with
appropriate scale factors. General-purpose multipliers are
good for squaring (0' = 2), but non-integer·exponents, such as
1.3 or 1.5: are sometimes needed. The circuit for this is
shown in Figure 4.
The output of the 8048 log amplifier with a DC voltage input X
that ranges from 1V to 10V is:

X
VOUT = -K 1 10glO (10K IREF)

The output of the antilog circuit (8049) is:

X
VOUT = ROUT IREF2 antiloglO ( K11091O )
K2
or in other words,
VOUT

=. ROUT IREF2 (X) K1/K2

ROUT Output resistor connected between pins 10 and 14 of
the 8049.
IREF2 Reference current for the 8049.

(5)

X - Input (+1V::; X ::; +10VI.
K1 - Scale factor of 8048.
K2 - Scale factor of 8049.
The exponent is set by the ratio of the scale factors K 1 and K2,
and the coefficient is set by the product RoIREF2·

(6)

16

200pF

(8)

where

where K1 is the scale factor of the 8048 and IREF is the
reference current. Setting IREF to 100ilA will make:
VOUT = -K1 10glO X

(7)

9----1"5"oklr-----<.

rr--

VREF

+15V

----8~

I

I

x
10k

10

L_
~----~Ar----~15

200pF

R5

VREF

i---Q----.J--f----+--------
I-

"a.
"0
"a.w
I-

II

i
t

.
C

•.8

w
~

..

- 1-

:;I

i

II:

0

z

TO+V

••••

8

I. 12 14 1•

LOAD CURRENT-mA

."
w

~
>

1.'

III

1.1

!

0

I-

"a.
"c0

...

~

•.8

l-

w

..

i i I

i

:;I

II:

0
Z

V

I

I .•

•.7

...

I

-r-

10Hz

I

I

100Hz

1kHz

I I
i I

10kHz 100kHz 1MHz

FREQUENCY

I.

I

I

!
I

~

a
!
...

1
,

..

,

...

I

1

,

I

1
10Hz 100Hz

II

I

I,

j

I
1kHz

10kHz 100kHz 1UHz

FREQUENCY

FIGURE 4. PERFORMANCE OF TRIANGLE-WAVE OUTPUT.

275

w

~
~

~

101--f-f-f-f-f-f-f-f-1I--l
1.01-i--i--i--.L=>,.--I

I

o
Q

~

o

0.9

i
oz

10Hz

100Hz

1kHz

10kHz 100kHz 1MHz

10Hz

100Hz

FREQUENCY

1kHz

10kHz 100kHz 1MHz

FREQUENCY

FIGURE 5. PERFORMANCE OF SINE-WAVE OUTPUT.

The performance of the sine-wave output is shown in
Figure 5. Figure 6 shows additional general information
concerning current consumption and frequency stability
and Figure 7 shows the phase relationship between the
three waveforms .

20

z

0

~

..
:E
:::>

15

z

0

u

...z

w
a:
a:
:::>
u

10

10

15

20

25

30

SUPPLY VOLTAGE

f

1.03r--r---------~

TO

>- 1.02

.- -

1

1.01

II.

1.00

~

0.89

~

10V

p.p'

-.l.
f
TO

HV

I

p.p'

~ 0.98

.-l

~~
10

15

20

25

30

• MINIMUM LEVELl WITH Vee' IOV

ALL OUTPUTS MAY IE TTL COMPATIBLE

SUPPLY VOLTAGe

FIGURE 7. PHASE RELATIONSHIP OF WAVEFORMS.

1.03 r--r------.._-.,.....,

li
!

EXTERNAL ADJUSTMENTS

1.02

The symmetry of all waveforms can be adjusted with the
external timing resistors. Two possible ways to
accomplish this are shown in Figure 8. By far the best
result Is obtained by keeping the timing resistors separate
(al. RA controls the riSing portion of the triangle and
sinewave and the 1 state of the square-wave. As
previously discussed, the reference voltage for the two
current sources is 0.2 X Vee. The current therefore is
simply

51.01

~

CII 1.00

~
lo.n
o

,

+- •

Z D."

-.0 -25 0

25

75

125

TEMPERATURE' C

FIGURE 6. CURRENT CONSUMPTION AND FREQUENCY
STABILITY.

IA =

276

0.2 x Vee

The magnitude of the triangle-waveform is set at 1/3 Vee;
therefore

CxV

(a)

5

C x 1/3 x Vee x RA

3

1/5 x Vee

RA

X

C
r---.----.---~--

-y or OND

(b)

Also. netice that the square wave eutput is net cemmitted.
The lead resister can be cennected to. a different pewer
supply, as leng as the applied veltage remains within the
breakdewn capability ef the waveferm generater (30 Vl. In
this way, fer example, can the square-wave eutput be
made TTL cempatible (lead resister cennected to. ±5
Volts) while the waveferm generater itself is pewered frem
a much higher veltage.

+Ycc

i

RL

V~~::;Er-~----~----~--,
!

nn
Vv

8038

'"
12k
L-_---<~----<~---<>

FREQUENCY MODULATION AND
SWEEPING
As explained earlier, the frequency ef the waveferm
generater is a direct functien ef the DC veltage at terminal
8 (measured frem +Veel. Thus by altering this veltage,
frequency medulatien is achieved.

-YorGND

FIGURE 10. CONNECTIONS FOR FREQUENCY
MODULATION la)
AND SWEEP Ibl.

278

USE IN PHASE-LOCKED LOOPS

pin 9 of the waveform generator and the VCO input of the
phase-detector.
Second, the dc output level of the amplifier must be made
compatible to the dc level required at the FM input of the
waveform generator (pin 8, 0.8 x Vee'> The simplest
solution here is to provide a voltage divider to Vee (R1, R2
as shown) if the amplifier has a lower output level or to
ground if its level is higher. The divider can be made part
of the low-pass filter.
This application not only provides for a free-running
frequency with very low temperature drift, but it also has
the unique feature of producing a large reconstituted
sinewave signal with a frequency identical to that at the
input.

Its high frequency stability makes the waveform
generator an ideal building block for a phase-locked loop.
In this application the remaining functional blocks, the
phase-detector and the amplifier, can be formed by a
number of available IC's (e.g. MC 4344, NE 562, HA 2800,
HA 2820>.
In order to match these building blocks to each other, two
steps must be taken. First, if necessary, two different
supply voltages are used and the square wave output is
returned to the supply of the phase detector. This assures
that the VCO input voltage will not exceed the capabilities
of the phase detector. If a smaller VCO signal is required,
a simple resistive voltage divider is connected between

PHASE DETECTOR

INPUT
~

OEM;!DULATED
FM

-

AMPLIFIER

t--

+v,

VCOIN

+Vcc

V

,A~
SQU ARE
WAVE
OUT

DUTV CYCLE
FREQUENCY
ADJUST

"

V

R:

I

\

FM
SWEEP

•

5

4

R,

•

INPUT

TRIANGLE

lOW·PASS

OUT

FM .,AS_

7

FILTER

,~~

8038

J

SINE WAVE

2
10
TIMINQ
CAP.

11

1

12
-Yee/OND

SINE
WAVE

ADJ.

V

=

I

f--o r\A,
=~

-

SINEWAVf.

ADJ.

"

FIGURE 11. WAVEFORM GENERATOR USED AS STABLE VCO IN A PHASE-LOCKED LOOP.

279

Everything You Always
Wanted to Know about
the 8038
The 8038 is a function generator capable of producing
sine, square, triangular, sawtooth and pulse waveforms
(some at the same time>. Since its introduction, marketing
and application engineers have been manning the phones
explaining the care and feeding of the 8038 to customers
worldwide. This experience has enabled us to form articulate responses to the most frequently asked questions.
So, with data sheet and breadboard in hand, read on and
be enlightened.
Q1.

A.

Q2.

A.

Q3.

A.

r-~----t-------r-o +15Y

::571N457

15K
4.7K

RA

·-~nn

I want to sweep the frequency externally but can
only get a range of 100 to 1. (or 50 to 1)[or 10 to 11.
Your data sheet says 1000 to 1. How much sweep
range can I expect?
Let's look at what determines the output frequency.
Start by examining the circuit schematic at pin 8 in
the upper left hand corner. From pin 8 to pin 5 we
have the emitter-base of NPN 0, and the emitterbase of PNP 02. Since these two diode drops cancel
each other (approximately) the potential at pins 8, 5
and 4 are the same. This means that the voltage from
V+ to pin 8 is the same as the voltage across external
resistors RA and RB. This is a textbook example of a
voltage across two resistors which produce two
currents to charge and discharge a capacitor
between two fixed voltages. This is also a linear
system. If the voltage across the resistors is dropped
from 10V to 1V the frequency will drop by 10:1.
Changing from 1 volt to 0.1V will also change the
frequency by 10:1. Therefore, by causing the
voltage across the external resistors to change from
say 10V to 10 mV, the frequency can be made to vary
at least 1000:1. There are, however, several factors
which make this large sweep range less than ideal.

lOOK
FREQUENCY

--4\

r~+1L'"1.7

8038

3

-

A A _
V

v

LOG POT ' - -

10M

/1

r

2

'---<:l " "

'---....:'0;-_-.:.;"_ _....;' 2_='
.0047

~F

DISTORTION

lOOK

' - - -.......- -......- -......- - - - 0 -15Y

FIGURE 1. VARIABLE AUDIO OSCILLATOR, 20 Hz to 20 KHz

Q4.

A.

You say I can vary the voltage on pin 8 (FM sweep
input) to get this large range, yet when I short pin 8
to V+ (pin 6) the ratio is only around 100:1.
This is often true. With pin 8 shorted to V+, a check
onthe potentials across the external RA and RB will
show 100 mV or more. This is due to the VBE mismatch between 0, and 02 (also 0, and 03) because
of the geometries and current levels involved.
Therefore, to get smaller voltages across these R's,
pin 8 must be raised above V+.
How can I raise pin 8 above V+ without a separate
power supply?
First of all, the voltage difference need only be a few
hundred millivolts so there is no danger of
damaging the 8038. One way to get this higher
potential is to lower the supply voltage on the 8038
and external resistors. The simplest way to do this is
to include a diode in series with pin 6 and resistors
RA and RB.
See Figure 1. This technique should increase the
sweep range to 1000 to 1.

QS.

A.

280

O.K., now I can get a large frequency range but I
notice that the duty cycle and hence my distortion
changes at the lowest frequencies.
This is caused partly by a slight difference in the
VBE's of 02 and 03. In trying to manufacture two
identical transistors, it is not uncommon to get VBE
differences of several millivolts or more. In the
standard 8038 connection with pins 7 and 8
connected together, there are several volts across
RA and RB and this small mismatch is negligible.
However, in a swept mode with the voltage at pin 8
near V+ and only tens of millivolts across RA and
RB, the VBE mismatch causes a larger mismatch in
charging currents, hence the duty cycle changes.
For lowest distortion then, it is advisable to keep the
minimum voltage across RA and RB around 100
millivolts. This would, of course, limit the frequency
sweep range to around 100 to 1.
I have a similar duty cycle problem when I use high
values of RA and RB. What causes this?
There is another error term which becomes
important at very low charge and discharge
currents. This error current is the emitter current of
07. The application note on the 8038 gives a
complete circuit description but it is sufficient to
know that the current charging the capacitor is the
current in RA which flows down through diode 09
and into the external C. The discharge current is the
current in RB which flows down through diode Os.
Adding to the 08 current is the current of 07 which is
only a few microamperes. Normally, this 07 current
is negligible, but with a small current in RB, this
current will cause a faster discharge than would be
expected. This problem will also appear in sweep
circuits when the voltage across the external
resistors is small.

06.
A.

07.

How can I get the lowest distortion over the largest
frequency sweep range?
First of all, use the largest supply voltage available
(±15V or +30V is convenient), This will minimize
VBE mismatch problems and allow a wide variation
of voltage on pin 8. The potential on pin 8 may be
swept from Vee (and slightly higher) to (2/3 Vee +2V)
where Vee is the total voltage across the 8038.
Specifically for ±15V supplies (+30V) , the voltage
across the external resistors can be varied from zero
to nearly 8 volts before clipping of the triangle
waveform occurs.
Second, keep the maximum currents relatively large
(1 or 2 mAl to minimize the error due to 07. Higher
currents could be used, but the small geometry
transistors used in the 8038 could give problems
due to VeE(sat) and bulk resistance, etc.
Third, and this is important, use two separate
resistors for RA and RB rather than one resistor with
pins 4 and 5 connected together. This is because
transistors 02 and 03 form a differential amplifier
whose gain is determined by the impedance
between pins 4 and 5 as well as the quiescent
current. There are a number of implications in the
differential amplifier connection (pin 4 and 5
shorted), The most obvious is that the gain
determines the way the currents split between 02
and 03. Therefore, any small offset or differential
voltage will cause a marked imbalance in the charge
and discharge currents and hence the duty cycle. A
more subtle result of this connection is the effective
capacitance at pin 10. With pins 4 and 5 connected
together, the "Miller effect" as well as the compound
transistor connection of 03 and 05 can produce
several hundred picofarads at pin 10 seriously
limiting the highest frequency of oscillation. The
effective capacitance would have to be considered
important in determining what value of external C
would result in a particular frequency of oscillation.
The single resistor connection is fine for very simple
circuits, but where performance is critical, the two
separate resistors for RA and RB are recommended.
Finally, trimming the various pins for lowest distortion deserves some attention. With pins 7 and 8
connected together and the pot at pin 7 and 8
externally set at its maximum, adjust the ratio of RA
and RB for 50% duty cycle. Then adjust a pot on pin
12 or both pins 1 and 12 depending on minimum
distortion desired. After these trims have been
made, set the voltage on pin 8 for the lowest
frequency of interest. The principle error here is due
to the excess current of 07 causing a shift in the
duty cycle. This can be partially compensated for by
bleeding a small current away from pin 5. The
simplest way to do this is to connect a high value of
resistance (10 to 20 mf1l from pin 5 to V-to bring the
duty cycle back to 50%. This should result in a
reasonable compromise between low distortion and
large sweep range.

A.

as.
A.

09.

You're probably having trouble keeping the
constant voltage across RA and RB really constant.
The pulse output on pin 9 puts a moderate load on
both supplies as it switches current on and off.
Changes in the supply reflect as variations in
charging current, hence non-linearity. Decoupling
both power supply pins to ground rightat the device
pins is a good idea. Also, pins 7 and 8 are
susceptible to picking up switching transients (this
is especially true on printed circuit boards where
pins 8 and 9 run side by sidel. Therefore, a capacitor
L 1 J-lF or morel from V+ to pin 8 is often advisable. In
the case when the pulse output is not required, leave
pin 9 open to be sure of minimizing transients.
What is the best supply voltage to use for lowest
frequency drift with temperature?
The 8038AM, 8038AC, 8038BM and 8038BC are all
temperature drift tested at Vee = +20 V (or ±1 OV). A
curve in the lower right hand corner of Page 4 of the
data sheet indicates frequency versus temperature
at other supply voltages. It is important to connect
pin 7 and 8 together.

Why does connecting pin 7 to pin 8 give the best
temperature performance?
A.
There is a small temperature drift of the comparator
thresholds in the 8038. To compensate for this, the
voltage divider at pin 7 uses thin film resistors plus
diffused resistors. The different temperature coefficients of these resistors causes the voltage at pins 7
and 8 to vary 0.5 mV/oC to maintain overall low
frequency drift at Vee = 20V. At higher supply
voltages e.g., ±15V (+30VI, the threshold drifts are
smaller compared with the total supply voltage. In
this case, an externally applied constant voltage at
pin 8 will give reasonably low frequency drift with
temperature.
010. Your data sheet is very confusing about the phase
relationship of the various waveforms.
A.
Sorry about that! The thing to remember is that the
triangle and sine wave must be in phase since one is
derived from the other. A check on the way the
circuit works shows that the pulse waveform on pin
9 will be high as the capaCitor charges (positive
slope on the triangle wave) and will be low during
discharge (negative slope on the triangle wave).
The latest data sheet corrects the photograph
Figure 7 on Page 5 of the data sheet. The 20% duty
cycle square wave was inverted, i.e., should be 80%
duty cycle. Also, on that page under "Waveform
Timing" the related sentences should read "RA
controls the rising portion of the triangle and sinewave and the 1 state of the square wave." Also, "the
falling portion of the triangle and sine wave and the
Q state of the square wave is:"
all. Under Parameter Test Conditions on Page 3 of your
8038 data sheet, the suggested value for min. and
max. duty cycle adjust don't seem to work.
A.
The positive charging current is determined by RA
alone since the current from RB is switched off. (See
8038 Application Note A012 for complete circuit
description,) The negative discharge current is the
difference between the RA current and twice the AB

This waveform generator is a piece of junk. The
triangle wave is non-linear and has large glitches
when it changes slope.

281

v+

current. Therefore, changing RB will effect only the
discharge time, while changing RA will effect both
charge and discharge times. For short negative
going pulses (greater than SO% duty cycle) we can
lower the value of RB (e.g., RA = SOKO and RB =
1.6KOl. For short positive going pulses (duty cycles
less than SO%) the limiting values are reached when
the current in RA is twice that in RB(e.g., RB=SOKO
and RA = 2SKOl. This has been corrected on the
latest data sheet.

80.8

11

10

Q12. I need to switch the waveforms off and on. What's a
good way to strobe the 8038?
A. With a dual supply voltage (e.g., ±1SV) the external
capacitor (pin 10) can be shorted to ground so that
the sine wave and triangle wave always begin at a
zero crossing point. Random switching has a SO/SO
chance of starting on a positive or negative slope. A
simple AND gate using pin 9 will allow the strobe to
act only on one slope or the other, see Figure 2.
Using only a single supply, the capacitor (pin 10) can
be switched either to V I or ground to force the
comparator to set in either the charge or discharge
mode. The disadvantage of this technique is that the
beginning cycle of the next burst will be 30% longer
than the normal cycle.

c

(AI

I

r...-------tRAi-RB~--+15V

c

15K

~-----+-----~~----oV-

(BI

8038

FIGURE 3. SINE WAVE OUTPUT BUFFER AMPLIFIERS
IN914

11

10

IN914

Q14. Your 8038 data sheet implies all waveforms can
operate up to 1 Megahertz. Is this true?
A.
Unfortunately, only the square wave output is useful
at that frequency as can be seen from the curves on
page 4 of the data sheet, distortion on the sine wave
and linearity of the triangle wave fall off rapidly
above two hundred kilohertz.
Q15. Is it normal for this device to run hot to the touch?
A.
Yes. The 8038 is essentially resistive. The power
dissipation is then Wand at ±1S volts the device
does run hot. Extensive life testing under this
operating condition and maximum ambient
temperature has verified the reliability of this
product. Copies of the reliability report are available
from Intersil.
Q16. My data sheet shows a device with only 12 pins. The
8038 I received has 14 pins. How can I hook it up?
A.
Our artist got lazy and decided to draw only the
twelve pins that are used and omitted pins 13and 14
which are not connected. The pin numbers and their
functions are correct. This drawing has been
corrected on the latest data sheet.

I+-......-+.--{>I--o STROBE
OFF

-, r
W

ON

+15V (> OVI
-15V

« -10V)

FIGURE 2. STROBE - TONE BURST GENERATOR

Q13. How can I buffer the sine wave output without
loading it down?
A.
The simplest circuit is a simple op amp follower as
shown in Figure 3A. Anothercircuit shown in Figure
3B allows amplitude and offset controls without
disturbing the 8038. Either circuit can be DC or AC
coupled. For AC coupling the op amp non-inverting
input must be returned to ground with a 100KO
resistor.

282

Q17. How stable are the output amplitudes versus
temperature?
A.
The amplitude of the triangle waveform decreases
slightly with temperature. The typical amplitude
coefficient is -.01 %/0 C giving a drop of about 1% at
125°C. The sine output is less sensitive and

decreases only about 0.6% at 125°C. For the square
wave output the VCE(sat) goes from 0.12V at room to
0.17 at 125° C. Leakage current in the "1" state is less
than a few nanoamperes even at 125°C and is
usually negligible.

BO

DETAILED SCHEMATIC

at,
R46

40k

-~,6
I

i

!

r+-.
R,
30k

a"
a"
a"
a"
a"

010

a'~l---<

, 1;J'a"
, ~"
~R4 ~R5 R6
~100

roo

100

+ "'" +

FLIP-FLOP

SINE·CONVERTER

283

Power Supply Design Using
The ICL8211 and 8212
INTRODUCTION

For a detailed circuit description of the ICL 8211/ 12 refer
to the data sheet pages 4 and 5. For large volume applications the ICL 8211/12 may be customized by the use of
metal mask options to include setting resistors or to vary the
output options, or even to adapt the circuit as a temperature sensing element.

The Intersil ICL 8211/12 are micropower bipolar monolithic integrated circuits intended primarily for precise
voltage detection and generation. These circuits consist of
an accurate voltage reference, a comparator and a pair of
output buffer/drivers.

Applications for the ICL 8211/12 include a variety of voltage detection circuits, power supply malfunction detectors,
regulators, programmable zeners, and constant current
sources. In this discussion we will explore the uses of the
ICL 8211/12 in power supply circuits of various types. Their
attractiveness to the power supply designer lies largely in
their ability to operate at low voltage and current levels
where standard power supply regulator devices cannot be
used. In addition, the unique features of the ICL 8211/12
make them useful in many ancillary circuits such as current
sources, overvoltage crowbars, programmable zeners and
power failure protection.

Specifically, the ICL 8211 provides a 7mA current limited
output sink when the voltage applied to the THRESHOLD
input is less than 1.15 volts. Figure 1 shows a simplified
block diagram of the ICL 8211.

1,15V
VOLTAGE

3
'l--+------oTHAESHOlD

REFERENCE

5

v-o----~

POSITIVE VOLTAGE REGULATORS

_____ __
~

Using the ICL 8211/12 it is possible to design a series of
power supply regulators having low minimum input voltage
and small input/output differential. These are particularly
useful for local regulation in electronic systems as their
small input/ output differential results in low power loss.

~_~

Figure 1:
ICL 8211 Block Diagram
The ICL 8212 provides a saturated transistor output (no
current limit) whenever the input THRESHOLD voltage
exceeds 1.15 volts. Both circuits have a low current HYSTERESIS output which is turned on when the THRESHOLD voltage exceeds 1.15 volts, enabling the user to add
controlled hysteresis to his design. Figure 2 shows a simplified block diagram of the ICL 8212.

INPUT
2.2V·30V

1.15V

R2

v5

v.o----~---~-~--~-__,

VOLTAGE
REFERENCE

ICL 8211

TH.

C2

OUTPUT

10,uF

1.15V·29.5V
SOmA

R3

Figure 3:
Positive Regulator - PNP Boost
The ICL 8211 in Figure 3 provides the voltage reference
and regulator amplifier while Q1 is the series pass transistor.
R 1 defines the output current ofthe ICL 8211 while C1 and
C2 provide loop stability and also act to suppress feedthrough of input transients to the output supply. R2 and
R3 determine the output voltage as follows:

3
l--+-----QTHRESHOLO

V_C5>--_ _-4_ _ _ _ _~-_ _ _ ___'

Figure 2:
ICL 8212 Block Diagram

In addition, the values of R2 and R3 are chosen to provide
a small amount of standing current in Q1, which gives ad-

284

ditional stability margin to the circuit_ Where accurate setting of the output voltage is required, either R2 or R3 can
be made adjustable. If R2 is made adjustable the output voltage will vary linearly with shaft angle; however, if the potentiometer wiper were to open circuit, the output voltage would
rise. In general, therefore, it is better to make R3 adjustable
as this gives failsafe operation.

put voltage in order for the ICL 8212 to be able to pull the
gate down far enough to turn the device off at no load.
The predominant loop time constant is provided by R2 and
C1. This time constant should be chosen as small as possible
commensurate with loop stability as it also affects load tran·
sient response. After an abrupt change in load current C1
must be charged to a new voltage level by R2 to regulate the
current in 01 to the new load level and therefore the small·
er the R2 x C1 product the better the load transient response.
The value of C2 should be chosen to maintain the output
within desired limits during the recovery period of the main
loop. Note, however, that because of the wide bandwidth of
the IC L 8212 and the absence of charge storage effects in
the F ET, these considerations are not particularly restrictive.

The choice of 01 depends upon the output requirements.
The ICL 8211 has a worst case maximum output current of
4mA, so with any reasonable device for 01 the circuit should
be capable of 50mA output current with an input to output
drop of 0.5V. If larger output currents are required 01 could
be made into a complementary quasi-darlington, but the input/output differential will then increase.
Note also that 01 provides an inversion within the loop so
the non·inverting ICL 8211 must be used to give overall neg·
ative feedback.

For higher current outputs the system could be further boost·
ed using a bipolar transistor. One attraction of using a FET
only output, however, is that the IDSS of the FET gives a
measure of output short circuit protection. Should both the
low input/output differential of the circuit of Figure 3 plus
the extended input voltage capability of Figure 4 be required,
the circuit of Figure 5 may be used.

One limitation of the above circuit is that input voltages
must be restricted to 30 volts due to the voltage rating ofthe
ICL 8211. The circuit of Figure 4 avoids this problem.

+

r'f f"

+

I.

R1

R1

t

v+

r

A3

A2
4 DIP

~~C2

TH~

INPUT

OUTPUT

INPUT

ICL 8212

V-

.l "

5

1

_:R5 ..

1
I

Figure 4:
Positive Regulator - J - F ET Boost

I

'"

:fJ,

Q2

----f(~----

· J*-

,-

v+

DIP

I

R'

D2

+

,

A3

ICL 8211

~D1

TH

~C2

OUTPUT

3

VA'

15

-

Figure 5:
Positive Regulator - NPN + PNP Boost

In this circuit the input voltage is limited only by the voltage
rating of 01. The input/output differential is now dependent on the RDS(ON) of the J-FET boost transistor. For in·
stance, if 01 were a 2N4391 the maximum output current
would be equal to IDSS(MIN) which is 50mAandtheinput/
output differential would be:

This circuit is similar to that of Figure 3 except that 01 has
been added as a common base stage to buffer the output of
the ICL 8211 from the input supply and R1 and D1 to protect the input. Unfortunately, the ICL 8211 ca'nnot be sup·
plied from the regulated output as this would result in the
power supply being non self·starting. The choice of values
for R2, R3, R4, C1 and C2 is identical to that of Figure 3,
while D 1 must be a voltage equal to or larger than the output
voltage, R 1 must be chosen to provide the relatively low
supply current requirement of the ICL 8211, An alternative
arrangement for starting the circuit is to replace D1 with R5
and add D2. In this case the choice of R1 and R5 is such
that once the output supply is established the ICL 8211 is
supplied through D2,

RDS(ON) x I LOAD = 30n x 50mA = 1.5 Volts

However, at lower load currents the input/output differen·
tial will be proportionately lower.
A further consideration when choosing the F ET boost tran·
sistor is that its pinch-off voltage must be less than the out·

285

+

In this circuit the current threshold is set by the base-emitter
voltage of 01 so that when the voltage drop in R2, due to
load current, is sufficient to turn on 01 base drive is removed
from 02 by 01 collector. Note that this circuit works only
because the output current of the ICl 8211 is current limited
so that there is no danger of 01 and the ICl 8211 blowing
each other up with unlimited current.

~, Q1

'\

R1

+

I.

R3~ OlC1

v+

4

O/P

R3

INPUT

! ~ C2

ICL 8211

~~D1

TH.

OUTPUT

NEGATIVE VOLTAGE REGULATORS

3

vR4

I"

Because the reference voltage ofthe ICl 8211/12 is connected to the negative supply rail, and their output consists of
the open collector of an NPN transistor, it is not possible to
construct a negative equivalent of the circuit of Figure 3.
However, a negative equivalent of Figure 4 is easily constructed.

Figure 6:
Positive Regulator - Thyristor Boost
In the circuit of Figure 5, 01 and 02 are connected in the
classic S.C.R. or Thyristor configuration. Where higher input
voltages or minimum component count are required the circuit of Figure 6 can be used. The thyristor is running in a linear mode with its cathode as the control terminal and its gate
as the output terminal. This is known as the remote base
configuration.

+0

I

~"' I

J

4 O/P

INPUT

R2

d. I
0+

I·

v+

ICL8211

TH

~C2

!....

OUTPUT

R4

A word of warning, however. Thyristor data sheets do not
generally specify individually the gain of the PNP portion of
the thyristor, on which the circuit relies. It must therefore
either be very conservatively designed or some screening or
guarantee of the PNP gain be provid~d.
Note that, with the exception of the lOSS limit of Figure 4,
none of the circuits so far described provide output current
limiting. In general they are intended for applications in
which the extra voltage drop of a current sensing resistor
would be unacceptable. Where the circuits are used as local
regulators and the output supplies are only connected to local circuitry the chance of output short circuits is relatively
low and overcurrent protection is considered unnecessary.
Where protection is required it can be added by any of the
standard techniques. Figure 7 shows the simplest possible
constant current protection added to the circuit of Figure 3

Figure 8:
Negative Regulator - J -F ET Boost

Of course the J-F ET must now be a P-channel device but
otherwise the design considerations are identical to those for
Figure 4. Should further boost of the output current level be
required, an NPN boost transistor, 02, (shown dotted) can
be added. However, the charge storage effects of the NPN
transistor will reduce the loop bandwidth so that R2 or C1
should be increased to maintain stability. Note also that in
the circuit of Figure 8 an ICl 8211 is used instead of an
ICl 8212 in order to maintain correct feedback polarity.

+O-----~----~r-~--1_~

R2
R1

•
v+

This is the closest negative equivalent to the circuits of Figures 5 and 6.ln this case R1. R2 and 01 ensure that the circuit is self starting. The divider R 1/R2 must be chosen to
ensure that sufficient voltage (say -1 volt) is present at the
base of Q1 to start the circuit under minirr,1Um output voltage
conditions, but once the circuit is running 01 must remain
forward biased even at maximum input voltage, otherwise
the output of the ICl 8212 will be unable to pull the emitter of 01 low enough to turn it off under no load conditions.
Thus for a 3 volt output supply which runs from a minimum
4 volt input the ratio of R1 to (R1 + R2) must be one quarter. In order that the base of 01 is not taken below -3V
once the circuit is running the maximum input voltage would
therefore be -12V. An alternative arrangement which avoids
this restriction is to replace R1 with a zener diode, reduce
the value of R2 and delete 01.

C1
Q1

O/P

4

~
",02

INPUT

+

2.2V·30V
ICL8211

v-

"

TH

3

"'l l°o'~
Ol C2

1.15V·29V
SOmA

R4

Figure 7:
Positive Regulator - PNP Boost
Current Limited

286

0

,,

"/

I

f

,*.I,'

"

v'

HI

v'

IU

Il!)

IU

I

4

"

~ 01'

L..- _._

~;! '"

fH-

Hli

~~'"

I

()UIPI!l

4

~I)I

IM']J]

INPUT

I"

till

0-.

-K'"

V

'1

"

I

' 'r'r

",,02

a~~H4

1)\

Figure 10:
Current Limited Negative Regulator
- NPN + PNP Boost

Figure 9:
Negative Regulator - NPN + PNP Boost

ANCILLARY POWER SUPPLY CIRCUITS

In this case the only restriction is that the zener voltage shall
be less than or equal to the output voltage of the regulator.

Figure 11 shows the ICL 8212 connected as a programmable
zener diode. Zener voltages from 2 volts up to 30 volts may
be programmed by suitable selection of R2, the zener voltage
being:

In the circuit of Figure 9, R3 must be chosen to provide sufficient base drive for 02 via 01 under maximum load conditions. The maximum value of the current in R3 which may
be tolerated is 12mA, the worst case sink current of the ICL
8212 output transistor.

Vz=1.15x R1 + R2
R1
Because of the absence of internal compensation in the ICL
8212, C1 is necessary to ensure stability. Two points worthy
of note are the extremely low knee current (less than 300j.lA)
and the low dynamic impedance (typically 4 to 7 ohms) over
the operating current range of 300llA to 12mA.

Current limit can be applied to the circuits of Figure 9 in an
analogous manner to Figure 7 _ In this case R3 is the current
source for the base of 02, ensuring that the current limit transistor 03 has a defined maximum collector current.

IZ

(JlnpUT

HI

IHi

J",

1<4

~~C2

ICl Hl12

V

~,.

1\:1

'H~

(II'

lei Hi'11

I.
v+

J

DIP 4

~:m

ICL 8212

Vz

THL-

~
" 3
N 2

>

R1
150K

1

o
0.01

0.1

1.0
Iz(mA)

Figure 11:
Programmable Zener

287

10

100

The standard method of overcurrent protection in simple
series regulated supplies is shown in Figure 14.
v·

,:

leL 8211
OR

ICl8212

---1r----.

UNREGULATED INPUT

leL 8212
ICL8211

I = 25,uA
I'" 130,uA

BASE DRIVE

----,----1:
~

POWER DEVICE

R1
R3

R2

Figure 12:
Constant Current Sources

......------~_- REGULATED OUTPUT

Figure 14:
Standard Current limit

The circuit of Figure 12 shows how the ICl 8211/12 may be
used as constant current circuits. At the current levels obtained with the ICl 8211 or 12 on their own, the principal application will be in providing the "tail" currents of differential
amplifiers which may be used in power supply design. A more
useful application in power supplies is the programmable
current source shown in Figure 13.

The current limit value is simply:
•

ICl =

VRI= (03)
~R-2

The disadvantages of this circuits are the poor temperature
coefficient of the emitter base voltage of 03, the large variation of VBE between different devices and the badly defined transition between constant voltage and constant
current states due to the low gain of the current reglliation
loop.

ICla211

In this case the current limit value is:
I

_ 1.15V

Cl-~

THF------~

R2

One advantage of the circuit is the much improved temperature coefficient of the limit current. In Figure 14 the typical
coefficient is O.3%tC, while in Figure 15 the typical coefficient is O.02%tC. In addition, the higher gain of the ICl
8212 gives a much sharper transition between voltage limit
and current limit conditions. The spread of threshold voltages will also be lower in this circuit, but if precise adjustment
of the threshold is required R3 and R4 may be added as
shown in Figure 15.

Figure 13:
Programmable Current Source
In this case the output current is given by:
_

~

10 - 25/lA + R1

1.15

+!'i2 (1 + (3)
BASE DRIVE --Io-r------,------Ir

where {3 is the forward current gain of 01 and VBE is its
emitter-base voltage. The principal causes of departure
from a true current source for this circuit will be the variations in {3 with collector voltage of 01. With the current
settable anywhere in the range of about 300/lA to 50mA
and an operating voltage range from 2 to 30V, this circuit is
particularly suitable as the current source driving the base of
an output transistor in conventional series regulator power
supplies. Another useful application is as the current source
feeding a reference zener in highly stable reference supplies.
Again, because of the absence of internal compensation in
the ICl 8212, C1 is provided to ensure loop stability.ltalso
helps to keep output current constant during voltage changes
or transients.

R1

O/P
leL 8212

R4

R2

REGULATED OUTPUT

Figure 15:
Improved Current Limit

288

The major penalty of the system is the extra 500mV which
must be dropped in R2 to effect current limiting. Note again
that the low operating voltage and power supply current al·
low the ICL 8212 to be powered directly from the base drive
voltage of the power supply.

feedback, which is overcome by the large positive feedback
from pin 2. Resistor R3 limits the output current ofthe ICL
8212 to a safe value of, say, 20mA. To operate properly the
thyristor should have a gate trigger current not greater than
about 10mA. Where higher gate currents are necessary the
circuit of Figure 18 may be used .

·O-~.-2--------l~:---4~~~4Q'
o/pr

R2

U

..2PROTECTED

SUPPLY

LOAD

I

I.

HVST.

v'

R4

.3

o/p

fLLKm
U~

ICL 8211

SUPPLY

ICL 8211

+-___..:3'-1 TH,

.2-

v'

TH

-

Figure 16:
High Voltage Dump Circuit

LOAD

v-

r

.,

r

Rl

.

.

R5

Figure 18:
Overvoltage Crowbar

This circuit protects sensitive loads against high voltage transients on the power supply rail. Should the input voltage
e'xceed the threshold set by R2 and R1, the ICl 8211 will
turn off 01 and hence protect the load from the transient.
R3 provides optional voltage hysteresis if so desired.

In this case the ICL 8211 holds down the base of 01 until
the circuit is triggered. The current in R3 should not exceed
4mA as this is the worst case current the ICl 8211 can sink
at its output. With this circuit thyristors requiring gate drives
in the 50 to 100mA region are easily tolerated.

I.

Notice that in both the above circuits no extra supplies are
needed to make the crowbars work down to voltages as low
as 3V. In particular, this makes the circuits most suitable for
use on 5V logic supplies where no other rails may be available to power a crowbar circuit or where, for reasons of safety, one does not wish to rely on auxiliary supplies.

v'

R2

R3

~

HYST.

f-----2.

TH

DIP
SUPPLY

~

In some systems it is undesirable to allow the supply rail to
be partially established. For instance, in a logic system logical
malfunctions may occur. Another example is the lM199/
299/399 temperature stabilized reference. If the heater supply falls below about 9V the unit tends to "run away" and
destroy itself.

LOAD

ICL 8212

v5

R'

)~

R4

I.
'~~"r'
R2

Figure 17:
Overvoltage Crowbar

v'

The most popular form of overvoltage protection is the Thyristor crowbar, which short circuits the supply in the event
of an overvoltage condition. The circuit of Figure 17 triggers
a thyristor when the supply voltage reaches a threshold defined by R1 and R2. The very low quiescent current of the
ICl 8212 means that there is negligible voltage drop in R4
during sensing so that accuracy is unimpaired and there is
no danger of triggering the thyristor. The connection from
pin 2 provides hysteresis which is necessary in this case because the reference will rise on the top of R4 as soon as the
threshold is reached and otherwise would provide negative

O/P

4

R'

P'N'r---J..----l

ICL8212

R3
SUPPLY

2

HVST.

1-_ _ _""3 TH
Rl

r
Figure 19:
low Voltage Disconnect

289

I

PROTECTED

LOAD

I

\

Should the power supply voltage fall below the level deter·
mined by R1 and R2, 01 is turned off, disconnecting the
load entirely so that it cannot operate at partial. voltage.
Note that the removal of the load may cause the supply
voltage to rise and the possibility of an oscillatory condition
exists. Resistor R3 therefore provides a small hysteresis,
which should be calculated to exceed the full load regulation
drop of the supply.

the supply is already out of regulation and unless it falls very
slowly there will not be sufficient time to shut the system
down properly.
LINE
TRANSFORMER

SERIES OR SWITCHED

REGULATOR
R1

R3
R4

REGULATED

C1

SUPPL V

DIP 4

LOGIC
OUTPUT

3
t - - -"fTH
R2

Figure 20:
Power Suppiy 'ltlindovv Detector

The circuits of Figures 16 and 19 can be combined so that a
load is only connected to the supply when the supply voltage
is within a specified range. In this case IC1 senses the over·
voltage condition while IC2 senses the undervoltage condi·
tion. Again, hystere~is may be added as necessary by the addition of R3 and R5.
In many systems, particularly those using microprocessors,
it is necessary to provide a logic signal which gives advance
warning of an impeding power failure so that the system can
execute a shutdown routine before power is lost. A simple
undervoltage detector on the regulated supply is generally
insufficient as by the time an undervoltage signal is generated,

Figure 21:
Simple Power Fail System
In the circuit of Figure 21, an inCipient power failure is de·
tected at the unregulated input of the regulator. Note that
the value of main reservoir capacitor Cl must be large enough
so that the shutdown routine can take place before the reg·
ulator drops out of regulation. Waveforms for a typical power
failure are shown in Figure 22.
The threshold detector should be an ICL 8212 if a logic '1'
is required to initiate shutdown, or an ICL 8211 if a logic '0'
is required. Note that the ICL 8212 will drive 7 T.T.L.loads
and the ICL 8211 2 T.T.L. loads.

FULL WAVE

RECTIFIED
A.C.

-+ -----UNREGULATED INPUT

VOLTAGES
OF REGULATOR

-~PEAKOFRIPPLE

REGULATED OUTPUT

TIME FOR

-I

LOGIC

I

I

I_SHUTDOWN

I

ROUTINE

.J.[I=
__

OUTPUT-If-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

..J..:- -

Figure 22:
Simple Power Fail System Waveforms

290

LINE
TRANSFORMER

R1
R3

LOGIC
OUTPUT

C1

o/p

REGULATED
SUPPLY

Figure 23:
Improved Power Fail System

through R2 to the threshold voltage of 1.15 volts, at which
point the power fail signal is activated.

Notice that, because of the ripple always present on the unregulated supply, power failure was not actually detected until some time after the removal of input power. This waste
of time means that larger voltage margins must be built into
the system, reducing the regulator efficiency under normal
operating conditions. In some instances, however, this circuit
may be adequate.

In this case, the worst point at which a power failure can occur is just before C1 begins to charge on the rising side ofthe
input A.C. signal. However, because of the fast warning given
by the system, it is still superior than that of Figure 21 in
the time allowed for a shutdown routine.

In Figure 24, the power is monitored at a point isolated from
the main capacitor C1 so that failure can be detected without having to wait for C1 to discharge below the minimum
voltage of the normal ripple. Waveforms for this circuit are
shown in Figure 24.

CONCLUSIONS
Just a few of the many possible applications of the ICL 8211
and ICL 8212 in power supply systems have been described.
Both in power supply systems and elsewhere, the features
of the ICL 8211 and ICL 8212 make them very useful general purpose circuits. Once aware of the useful features of
these low power, low voltage circuits the designer will rapidly discover a large number of applications for himself.

In this case R 1 tops up C2 to the zener voltage each cycle,
while C2 holds the input of the ICL 8211 or ICL 8212 (depending on the polarity of the required output signal) above
its threshold during the zero crossings of the A.C. waveform.
However, in the event of a power failure, C2 discharges

DW

'""''''~
RECTIFIED
A,C,

I
REGULATOR
VOLTAGES

w~u
ATC2

:I

~
I

-

'/

_ _ _ '\

I
O~~~~T_~

1_

_ _\

1 _

\.
.. . ' ,
\ ..

_

I

I
-1J______
-, _
I
I

I

TIME FOR

I

~SHUTDOWN_I

________________________

~IL-

___

Figure 24:
Improved Power Fail System Waveforms

291

I __

R_O_UT_'_NE______

ZENER VOLTAGE
DETECTOR THRESHOLD

stability of the circuit. Also, using two matched npn-pnp
transistor pairs ensures close tracking between input and
output voltages (a task normally addressed by suitable
feedback circuitry) as well as low offset-voltage drift
(20 microvolts/°C).
The complementary-transistor pairs are 2N4854s
wired for active current sourcing and sinking so that
bipolar input signals can be processed. Each transistor
has a typical {j of 100. With the npn and pnp input-bias
currents tending to cancel each other, the resultant
input-bias current of the amplifier is ± 5 microamperes.
Layout is critical to the stability of the circuit. The
buffer should be constructed as shown in (b). The two
transistor pairs are mounted close together, in holes
drilled in a copper-clad circuit board as shown. The
flanges on the TO-99 cases encapsulating the 2N485s
should be soldered to the copper, which serves as a
ground plane. The collector of each transistor must be
bypassed by a O.l-microfarad ceramic-chip capacitor
mounted close to the transistor. This is done by standing
the capacitors on end, with the bottom contact lead
soldered to the ground plane and the top contact lead
soldered to the collector.
All leads must be less than '/' inch in length and be as

Unily-galn buffer amplifier
is uHrafast

Applications where transmission-line drivers, active
voltage probes, or buffers for ultrahigh-speed analog-todigital converters are needed can use a stable buffer
amplifier capable of driving a relatively low-resistance,
moderate-capacitance load over a wide range of frequencies. The circuit shown in (a) fulfills these requirements.
With a bandwidth of 300 megahertz, it exhibits no
peaking of its response curve, having a gain of virtually I
(0.995) under no-load conditions and 0., under a
maximum load of 90 ohms.
The circuit is a variation on a basic emitter-follower
network, which is inherently capable of wide band
performance. However, no feedback loops are needed
anywhere within the circuit to boost the gain at the high
frequencies, and dispensing with them contributes to the
+15 V

MINIATURE CERAMIC
CAPACITORS

+5 V

r-..;;;.....?'....~---....,
COPPER
GROUNO
PLANE

IOkil

'INPUT
~=>o.."I""'---~

OUTPUT

IOil

(bl
OUTPUT
( h \f1 A[n RISllCS or UNll Y (,AI N Bur FE. R

IOil

IOkil

Input impedance

500 kilohms (de)

Input bias current

±5pA

Input capacitance

16 pF

Input/output voltage range

±3 V

max

Output offset-voltage drift

Output impedance

100hms

Load resistance

90 ohms max

Gain, no loatt

+0.995

Wideband buffer. Emitter-follower configuration yields unity gain

Bandwidth, -3 dB

300 MHz

from dc to 300 megahertz. Absence of feedback in circuit
contributes to buffer stability. Use of ma!ched npn-pnp transistor
pairs ensures almost parfect inputloUfput signal tracking (a).
Component layoUf is critical for circuit stabll~y (b).

Power supply. quiescent

±15 V de at 1.5 rnA

Power consumptiQn

90mW

-15V

-5V
0,. 0" 2N4854

directly wired as possible. One-eighth-watt resistors are
used throughout and are soldered to the transistor leads
as close as possible to the case. For clarity, not all
components are shown. For coupling to or from the

±

5Vdcat4.5mA

amplifier, subminiature radio-frequency connectors can
be mounted at the input and output ports of the buffer.
Typical characteristics of the unity-gain buffer circuit
are listed in the table.
GZ JK

292

Commutating design for IC amplifiers
virtually eliminates offset errors
auto zero, a new design concept
Cforommutating
monolithic operational and instrumentation

to cancel both the input offset and the instantenous
low-frequency noise voltage.
The CAZ principle is perhaps best understood by
examining the way it is implemented in the 760017601
op amps. These devices contain all the necessary
analog and digital circuitry on-chip, including two op
amps, an oscillator counter, level translators and
analog switches. The only external components required are two auto-zero capacitors.

amplifiers, dramatically reduces initial input offset
voltage and offset drift with changes in temperature
and time. Dubbed CAZ, the new approach combines
digital and linear techniques to bring down initial
offset to a low 1 to 5 p. V and hold offset drift to a
mere 0.005 p. V/oe and only 0.2 p. V/year. Moreover,
the CAZ design permits high-performance monolithic
amplifiers to be fabricated with standard low-cost
complementary-MaS processing.
The first CMOS chips to employ the CAZ technique
include: a pair of operational amplifiers (the compensated ICL7600 for applications requiring voltage
gains from unity to about 20, and the uncompensated
ICL7601 for voltage gains greater than 20); and two
instrumentation amplifiers, the ICL7605 and the
ICL7606.
For the CAZ op amps, input offset voltage is three
orders of magnitude lower than that of traditional
monolithic bipolar op amps, like the 741. Similarly,
compared to conventional instrumentation amplifiers,
which require highly accurate resistor matching and
tracking for their popular three-amplifier design, the
CAZ instrumentation amplifiers eliminate the need
for on-chip resistor trimming. The CAZ instrumentation amplifiers are intended for low-frequency applications that require voltage gains from 1 to 1000
and bandwidths from dc to 10 Hz.

All about the CAZ op amp

Fig. la shows the CAZ op amp as it sequences
through its two internal states. In addition to the
regular inverting and noninverting inputs, the CAZ
op amp has a third auto-zero input, designated AZ.
In most applications, this auto-zero input will be
connected to system ground, although it may be
connected to the noninverting input for improving
common-mode rejection ratio.
Because capacitors C. and C2 must have high values
between 0.01 and 1 p.F to minimize offset errors due
to charge injection they are not suitable for monolithic
integration. On the other hand, since resistors R. and
R2 have values of about 100 kn each, they can easily
be fabricated on-chip.
As long as the commutation frequency is high
compared to the leakage discharge times of C. and
C2 for the signal-processing mode, an input signal will
be processed as though the CAZ op amp were a single
amplifier. The discharge time constants of C. and C2,
when each has a value of 0.2 p.F, are in the tens to
hundreds of seconds.
During the auto-zero mode, with a suitable choice
of values for the resistors and the capacitors, each
internal op amp is connected, in turn, into a unitygain mode for frequencies approximately equal to or
less than the commutation frequency. As a result,
besides the dc offset voltage, each capacitor acquires
a voltage equal to the instantaneous low-frequency
noise below the commutation range of the internal op
amps. In addition, the low-pass filter networks formed
by R. and C" as well as by R2 and C2, attenuate highfrequency noise above the commutation frequency at
6 dB/octave.
This unique characteristic of the CAZ op amp to
reduce, not only the dc offset voltage, but also the low-

How CAl works

With the CAZ approach, on-chip analog switches
connect two internal op amps between two modes of
operation-when one amplifier is processing the input
signal, the other is in an auto-zero mode. The commutation frequency is the rate at which the two
internal op amps are switched between the two modes.
In the auto-zero mode, an external capacitor stores
a voltage equal to the input offset voltage plus the
low-frequency instantaneous noise voltage. In the
signal-processing mode, this capacitor is connected in
series with the overall amplifier's noninverting input

293

MODE A: A I PROCESSING ..PUT SfGNAL

In the switching section, six analog gates switch
each internal op amp between the signal-processing
mode and the auto-zero mode. The RC oscillator in
the digital section operates from a low-voltage internally regulated supply. The oscillator output may
be directed, by means of the DR terminal, either
through a 5-bit(divide-by-32) counter or a single-bit
(divide-by-2) counter. The level translators provide
full-supply voltage swings and break-before-make
signals to the input and output analog switches. This
arrangement gives the user considerable flexibility in
controlling the commutation frequency.
With the OSC terminal open-circuited and the DR
terminal connected to V+, the commutation frequency is about 160 Hz. To lower it, the designer can add
capacitance to the OSC terminal or use an external
clock to drive this terminal with a signal of -5 V peakto-peak, referenced to V+. The oscillator may be
stopped by connecting the OSC terminal to ground.
To increase the commutation frequency above 160 Hz,
the designer should connect the DR'terminal to the
GND supply. For an open-circuited OSC terminal, this
connection gives a commutation frequency of 3.2 kHz.
In the analog section, the CMOS op amps each h:rve
two gain stages. By varying the biasing of these
internal op amps, the user can select slew rate and
unity-gain bandwidth. For example, at maximum
bias, the slew rate is about 2 V/ /lS, unity-gain
bandwidth is 1 MHz, and the minimum guaranteed
stable closed-loop gain with any capacitive load is 10.

MODE B: A2 PROCESSING NVT SIGNAL

CI
+INPUT
AZ

-INPU1

INPUT

ANALOG

SWITOt
SECTION

01

02

OSC

1. In the CAZ op amp, analog gates switch two internal
op amps between signal-processing and auto-zero modes
to cancel offset errors and instantaneous low-frequency
noise (a). In addition to this analog circuitry, the CMOS
chip has digital circuitry, which includes an RC
oscillator,for controlling the commutation frequency(b).

The CAl instrumentation amps
Delivering equally impressive performance the
760517606 CAZ instrumentation amplifiers, are true
differential amplifiers, capable of amplifying a differential input signal (within the power-supply range)
in the presence of large common-mode voltages and
referencing the output signal to system ground or
some other voltage. An important advantage of these
CAZ instrumentation amplifiers over traditional
bipolar devices is the automatic self-compensation for
offset error voltages, whether they be· steady-state,
temperature, supply voltage, or long-term variable in
nature.
Both CAZ instrumentation amplifiers are low-frequency devices, useful to perhaps as high as 20 Hz,
although more commonly used in applications requiring less than 10 Hz. Unlike conventional differential
instrumentation amplifiers, the CAZ devices have
approximately constant input equivalent noise voltage, input offset voltage and drift values, as well as
100-dB common-mode and power-supply rejection
ratios-independent of gain.
As Fig. 2 shows, the CAZ instrumentation amplifier
has four functional blocks, three of which are identical
to those of the CAZ op amp. The fourth functional
block is a differential-to-single-ended unity-gain voltage converter, which consists of a group of eight analog
switches plus two external capacitors.

frequency noise below the commutation frequency has
at least two very important implications:
• The CAZ op amp can approach a near-zero noise
figure for frequencies from dc to about one-tenth the
commutation frequency. For good noise performance
below 10 Hz, the commutation frequency for the
760017601 should be between 30 and 200 Hz .
• The low-frequency or flicker noise of the input
transistors of the internal op amps is less critical than
that for a conventional op amp. This is very convenient, because the input transistors for the CAZ op
amp are MOSFETs, and their flicker noise is about
five times worse than that of bipolar transistors or
junction FETs.
As Fig. Ib illustrates, the 7600/7601 op amps
actually consist of three main functional blocks: a full
complementary set of input and output analog
switches for connecting the internal op amps into their
two modes of operation; a digital section containing
an RC oscillator, a divider chain and the necessary
drivers for the analog switches; and an analog section
comprising two internally-compensated CMOS op
amps plus their feedback resistors (R, and R.).
294

2. The CAl instrumentation amplifier works well at
bandwidths up to 10 Hz. It has four functional blocksthe analog, digital and switching sections of the CAZ op
amp, plus a differential voltage converter.

When one of these capacitors' is connected to the
differential signal source, the other is connected to
system ground, or a reference voltage, and to the input
of one of the internal op amps. A short time later,
the connections of the two capacitors are reversed.
Thus, at all times, the differential input source is being
sensed and applied to one of the internal op amps.
The only external circuitry required are two resistors,
to set the gain, and four capacitors-two for the
internal amps and two for the voltage converter.
Of the eight analog switches in the voltage converter, only four are conducting at anyone time. These
are the four that connect one of the capacitors to the
differential input and the other to ground, or a
reference, and to the input of an internal op amp. This
aliasing scheme preserves frequency information up
to the commutation frequency. Above it, an input
signal is transformed to a lower frequency at the
output. Because of charge-injection phenomena at the
switches and at the output to the voltage converter,
the values of capacitors C3 and C. must be about l/LF
to preserve signal accuracies to within 0.01%.

3. Because of its sensitivity to low-level Signals, the CAZ
op amp makes an excellent high-gain preamplifier (a). The
device is also well-suited for use with dual-slope analogto-digital converters (b).

interfacing with microprocessors. The 7600/7601 and
the 7109 use the same power supply of ±5 V, and the
entire system typically consumes just 2.5 rnA of
current.
The input signal is applied through a low-pass (150
Hz) filter to the CAZ op amp, which is connected in
a noninverting-gain configuration of either 20 or 100.
The internal oscillator of the 760017601 runs at about
5.2 kHz, resulting in a commutation frequency of 160
Hz, with the DR terminal connected to V+. The errorstorage capacitors, C, and C2, are 1 /LF each, for a good
compromise between the minimum equivalent input
dc offset voltage and the smallest value of lowfrequency noise.'
The output signal also passes through a low-pass
filter (1 Mil and 0.1 /LF), having a bandwidth of 1.5
Hz. This results in an equivalent dc offset voltage of
1 to 2 /LV and a pk-pk noise voltage of 1.7 /LV, referred
to the input of the 7600. The output of the low-pass
f:lter directly feeds the input of the converter.
The values of the converter's integrator resistor and
the reference voltage must be chosen to suit the overall
sensitivity of the system. For example, for a full-scale
reading of 2.048 V (0.005 V/count times 4096 counts),
the reference should be 1.024 V, and the integrator
resistor 100 kr!. With an amplifier gain of 100, the
system sensitivity will be 5/L V/count (0.005 V/count
divided by 100).
Alternatively, the gain of the 7600/7601 can be
reduced and different values used for the reference

Applying the CAZ op amp

The principal application for the CAZ op amp is
expected to be amplification of low-level signals from
dc to 50 Hz, such as those produced by thermocouples.
The CAZ op amp also is well-suited for use with dualslope analog-to-digital converters. The device's low
noise permits sensing signal levels as low as 10 /LV.
Fig. 3a shows a typical application-a preamplifier
having a fixed gain of 100. Here, the 100-kll series
input resistor and the O.Ol-/LF capacitor protect the
CAZ amp from damage even with overload voltages
as high as ±l kV.
In Fig. 3b, the CAZ op amp teams with the ICL 7109
12-bit dual-slope aid converter, which is designed for
295

4. In low-frequency applications,

the CAZ instrumentation amplifier can replace its more costly hybrid or

monolithic counterparts. It easily senses bridge voltages
(a) for building a digital-readout torque wrench (b).

voltage and the converter's integrator capacitor. With
a 190-kfl feedback resistor, a 0.2-V reference and a
20-k!l integrator resistor, the gain of the CAZ amp
reduces to 20, and the converter sensitivity increases
fivefold-for the same output sensitivity.

amplifier, converting the differential voltage output
from the bridge to a single-ended voltage reference
to ground. The 760517606 then applies the signal to
the input of a panel-meter chip-in this case, the
ICL7106 dual-slop aid converter for a 3-'I2-digit liquidcrystal display. This system employs the internal
voltage reference of the converter, instead of an
external reference source.
Setting a full-scale reading requires knowing the
voltage sensitivity of the strain-guage bridge and then
choosing both an appropriate gain for the CAZ
amplifier and an appropriate value for the reference
voltage. The proper amplifier gain should produce an
output swing of about 0.5 V at full scale. The reference
voltage required is one-half the maximum output
swing, or 0.25 V. Once designed, this type of system
requires only one full-scale adjustment-either the
amplifier gain or the reference voltage. Total current
consumption of the system, less the current drain of
the strain-gauge bridge, is about 2 rnA.

Ideal for low-frequency tasks

In low-frequency applications with bandwidths
from dc up to 10 Hz, 7605/7606 CAZ instrumentation
amplifiers can replace almost any of today's more
expensive hybrid or monolithic instrumentation
amplifiers. Since the CAZ devices do not require
periodic adjustment and have extremely low offset
drift, they perform particularly well in adverse environments where it is difficult to service equipp!ent.
One application for the 7605 is measuring the
voltage across a bridge network, as illustrated in Fig.
4a. The input common range for the amplifier's
+ DIFF and - DIFF inputs cannot exceed the supplyvoltage range, which might be, say, ±5 V. No adjustments are necessary, except for the gain resistors. In
such a circuit, common-mode rejection ratio is typically 100 dB, and the commutation frequency about
50 Hz.
A more specific application for the 760517606 CAZ
instrumentation amplifier is in a strain-gauge system,
like the digital-readout torque wrench of Fig. 4b. In
this application, the CAZ amp serves as a pre-

DB

296

6.

297

Analog Gates,
Switches, and
Multiplexers

298

Switching signals with semiconductors
Analog switches are fast, low cost, and work
well with the high impedance of most
signal circuits. Often they can replace reed relays
Until recently, signal routing and
switching were controlled almost exclusively by electromechanical relays and
mechanical switches. Now the electronic
switch. also known as the analog switch,
is being used for many such applications.
Initially the electronic switch replaced relays in many applications. But design
engineers soon realized that analog
switches have unique characteristics that
allow them to do things mechanical
switches could never attempt. In particular. an ordinary electronic switch is about
one thousand times as fast as a conventional rela\'.
Further: the electronic switch is smaller,
lighter, longer lived, more reliable and
often lower in cost than an equivalent
relay. These characteristics have allowed
the development of such things as low cost,
high speed, analog-to-digital and digitalto-analog converters, fast sample-andholds, video switching and many other
circuits. Usage continues to grow and a
numher of different types of electronic
'" itches ha\'e heen de\'e1oped for specific
t\'pes of aprlications.
Transistors have been used as switches
ever since they first appeared, but usually
as on-off devices for controlling lights,
rdays, and other loads, as indicated in Fig
tV

'cont~
""" 0

tV

=

A - Transistor power switch

~

I A. A diode is added to the equivalent
circuit to show that current can flow in
only one direction. Fig I B shows the
nature of electronic switching. The signals,
voltage V I, V2 and V), are usually low level
and often have high impedance; they represent the flow of information rather than
power. Further, the signals may be combined to produce new signals.
Analog switch vs reed relay. The
reed relay is closest to the analog switch
in size, speed, cost and usage; therefore it
can serve as a basis for comparison. Current through the coil (Fig 2A) of the reed
relay, opens or closes the associated contacts through which the signal passes.
The control input to the analog switch
usually comes from TTL or CMOS logic,
which the driver translates to the voltage
needed to turn on or turn off the channel.
The channel is a field effect transistor
(tTTl. with the signal to be switched fed
to the source while the drain is the output
terminal. Depending on the voltage the
driver imposes on the gate, the channel is
either a very high impedance-many
megohms-or well below 100 ohms.
Advantages of the reed relay include the
ability to handle much larger signals and
a much lower resistance when on.
Some analog switches are severly limited
in the magnitude and polarity of the signals
they can handle. Because of the nature of
semiconductors, the voltages applied to
source and drain cannot be allowed to vary
indiscriminately but must be held within
a range established by the characteristics
of the device as well as by the voltage
applied to the gate by the driver. If the

Signal

RI

Source

O > - - - - ,...
r

V,

Signal

------t-I

Drain

0>----

On off
control

R2

=

R3

V,

V3

On·off
contml

range is exceeded, either the channel goes
to the wrong state, or some intermediate
state, or the device may be destroyed.
With respect to "on" resistance, it will
be a long time (if ever) before analog
switches with the low "on" resistances of
relays are manufactured. However, the
applications that require extremely low
"on" resistance are few and most signal
switching is done into high impedance
loads.
Since electronic components are much
smaller than their mechanical counterparts, many more switches can be put
into one package, greatly reducing parts
count as well as space and volume. In
addition, electronic switches have no moving parts and consequently no contact
bounce. They are, however, sensitive to
static electricity and thus good handling
procedures should be used during assembly. The life of a solid switch is orders
of magnitude greater than a relay and no
maintenance is required. Driving the
switch is easy since it can interface directly
with TTL or CMOS logic without requiring
diode protection, as a reed relay normally
does. Pricing on a per channel basis is often
lower for the analog switch than the reed
relay, although some high speed switches
are priced higher. But the most significant
advantage of the electronic switch remains
its extremely fast switching speed. Its ability to switch in less than 1 microsecond has
opened up possibilities that are inconceivable with a reed relay.
Switch functions duplicate those commonly found in reed relays: form A (normally closed), form B (normally open) and

~r

Ro

B - Electronic signal switching

1. Bipolar transistor for power
switching. FETS for signal

I
I

A - Reed relay

B - Electronic switch

2. Reed relay performs the same function as an electronic switch

299

Switch se.ection guide

Virtual ground .wltch

Po.ltl... signal Iwltch

10K

v,

10K

-V out

;;-_-0

=lv,

Signal
inputs

XV

2

translator driver

is used.
No quiescent

No quiescent

o--"'V'VV-"""'1r--1"--O"""

Log;c

positive signals
only unless a

current.

10K
D4

inputs

Can switch

Output of switch
must go into the
virtual ground
point of an Op
Amp (unless
signal is below
0.2).

+ V2 )

Does not need

current.

t

driver. can be

~O----+-----'

Low cost.

Lowest cost.

channel doped with "positive" impurities
-the PJFET. The PJFET channel is on (low

conductor technologies typically used in·

resistance) in ilIt: abst:m.:t: of any controi

elude

signal. When the voltage at the gate terminal is made more positive than either the
drain or the source terminal (by a minimum amount). the switch is turned off
(high resistance). This phenomenon is
known as the pinching-off of the channel
through which the signal is flowing, and
the vol~age required to do this is called the
pinch-off voltage. This voltage can be
obtained directly from an open collector
TTL or CMOS logic operating at + 5 or + 15
v. The PJFETS have no quiescent current

bipolar, PJFET. NJFET; MOSFET.
VARAFET and CMOS.
The p-channel JFETS. The simplest
switch to understand and operate is a
Junction Field Effect Transistor having a

driven directly
by TTL

Does not need

3. Output olthe op-amp is determined by boih the signal inputs and the logic inputs

form C (double throw). Both single pole
and Illulti-rolc circuits arc available. Semi-

driver, can be

driven directly
by TTL

and do not require external power.
PJFETS make excellent special function
switches. An example is switching signals
into the virtual ground (inverting) terminal
of an op amp. (Note: Although the inverting input of an op amp is often part of
a more complex circuit, the circuit feeding
this input of the op amp is tricked into
believing the inverting input is at signal
ground: hence virtual ground.) The
PJFETS in the two-input circuit of Fig 3
(Note: the arrowhead orientation signifies

+V

Hybrid
circuit

?ignal

on

----------~

r - - - - - - - -1_ - - - - - - - -,

I
I

--tool

I
I

Sample

anci hold

Gain select

output

4. Programmable gain op-amp has 16
levels of gain. from 1 to 1.000
S;gnol

;n

TTL

>-....---0---,

Logic

1'---<>---+

Load

input

L----------- I -

On-off

resistor

control input

A - Sample·and-hold circuit

5. Analog switch handles only
positive voltage signals

Varactor
d;Ode\
Logic
input

6. Use of NJFETplus varactor diode for
sample-and-holds

Vln

~
+

_

Sample
output

100

Vo

I

n

0.01 ~F

B - Sample

I

7. Sample-and-hold circuit, A, uses three VARAFETS. Circuit configuration when
sampling is shown at B, and hold mode at C

Low••t qul.lcent current

Monolithic CMOS
driver gate
combination (low
cost).

HIghest .peed

Monolithic CMOS
driver gate
combination (low
leakage).

Lowest charge
injection. CMOS
driver and VERAFET
gate.

Low••t 'OSeOn)

Bipolar/MOS driver
with NJF ET gate

Bipolar driver with
NJFET gate (low
cost).

Lowest rDS(on)
Lowest rDS(on)

Low quiescent

Highest speed switch.

Lowest charge

Moderate leakage.

Lowest qu iescent
current.

Lowest leakage

Verv low quiescent

Good speed with
moderate rDS(on)
and leakage.

resulting in lowest
error.

current.

Can switch up to
!13v signals with
:!:15v supplies.

Can switch signals
almost to the supplV
rails.

p-charinel) can switch signals in the hundreds of volts as long as the op amp can
handle such voltages. The only thing to
keep in mind is that the current through
each PJFET must be kept within its specified
value. The solid line diodes DI and D2
at the inputs limit the voltage at the source
of the PJFET to about 0.7 volt and also
shunts positive inputs to ground when the
switch is off. With diodes D3 and D4 in
place. the circuit can switch ± 100 volts.
The diodes limit the input to the PJFET to
±0.6 volt. but this is adequate since the
op amp is actually forcing this point-the
drains of the PJFETS-to ground.
In Fig 4. PJFETS are used to switch
feedback resistors to provide an amplifier
with 16 different programmable gains.
Another special function switch built
using PJFETS handles only positive signals.
This switch requires an external referral
resistor. Fig 5. for proper operation. but
is ideal for switching into the positive
terminal of an op amp.
The N-channel JFET. An N-channel
JFET-a JFET with the channel doped with
"negative" impurities-is also turned on
with no control signal applied. and is
driven off by making the gate terminal
more negative than source and drain. Since
+15V--r-----

-1~~:::::J

-I

+5V---..f

I
I

I

I

± IOV

I
I

Logic in

I

High quiescent
current:

Low cost.
Moderate leakage

Highest cost.

quiescent current.

Switches :!:lOv
signals with :!:15v
supplies.

Average speed.

Ultra low leakage.

Lower cost.
Overvoltage
protection to :!:25v.

OnlV switch with
true chip enable.

Verv fast.

Lowest cost (for
this categorv).

Signal in

Fast.

injection.

current.

I
I

L ______ ....J

8. CMOS' switches have extremely low
drive and quiescent currents

the outputs of TTL and CMOS logic gates
are either a positive voltage level or near
zero. a driver is required to do level shifting
and generate a negative control signal.
Most NJFET switches come with the drivers
built in. Drivers for NJFETgates are usually
bipolar. or combined bipolar / MOS; they
require significant quiescent currents and
therefore consume power.
The negative impurities used in NJFET
channels have extra electrons. which are
far more mobile than the "holes" of
PJFETS channels. As a result. the NJFETS
have the lowest on resistance.
VARAFET switches. In some applications. such as sample-and-hold circuits.
low charge injection is critical. For these
applications the VARAFET gate. Fig 6. was
developed. The gate consists of an NJH,T
with a varactor diode in series with the gate
terminal. An NJFET by itself is not satisfactory because it will inject charge into the
signal path when it is turned on and will
thereby distort the output.
Varactor diodes can store charge and
thus they prevent most of the injected
charge from entering the channel. The
varactor diode also eliminates the referral
components otherwise required for
switching NJFET transistors. Fig 7A shows
a sample-and-hold using VARAFET gates.
When a sample of the analog input is
wanted. the logic signal applied to the
driver causes output / to go low and 2 to
go high. This puts the circuit into the
configuration shown at 7B. When this
sample period is over. / goes low. 2 goes
high. and the circuit is put in the hold
mode. Fig. 7C.
MOSFET switches. MOSFETS (Metal Oxide Silicon FET). unlik JFETS. are off when
no control voltage is applied to the switch.
They are turned on when the appropriate
signal is applied to the gate terminal.
MOSFET devices were among the first
switches on the market but are now used
301

Switches :!:1 Ov
signals with :!:15v
supplies, or :!:12v
and :!:1 Bv supplies.

in very few applications. Their only outstanding feature is more switches per packag:e-up to :-.i\-than other tCl:hllolog.ics
(ll\!..'ft..~d in this artil'k.
CMOS switches. Complimentary
MOSFFT (CMOS) switches are now heginning to dominate. In applications where
the special function switches-the PJFETS.
'HI·Frs. VARAFETS-are not needed or cannot he used. CMOS switches are the preferred devices.
CMOS switches consist of drivers and
gates made from CMOS. usually on a single
chip. A simplified circuit is shown in Fig.
H. The on-off input signal can be ohtained
from a CMOS logic gate or TTL. either
regular or open collector pulled to 15 volts.
Switching speed is higher for 15 volt logic.
When the logic input is low. both the P
and N transistor are off. When the logic
input is high. both transistors are on and
signals up to ± 10 volts can now either way
through the circuits.
A summary selection guide to analog
s\\ itches is gIven in the tahle which annears
at the top of these facing pages.

PM

Understanding and Applying
the Analog Switch
INTRODUCTION
Historically the analog switch has been thought of as a solid
state relay, and many of its common applications are areas
where the relay dominated the scene a few years ago.
Routing signals in telephone exchanges is the most obvious
example. More recently, however, as creative designers are
becoming aware of the unique properties of the analog
switch, a new generation of applications is emerging which
were simply not possible using relays. The ability to change
the gain of an amplifier, or the time constant of an inte·
grator, in less than a microsecond has far-reaching implications in real-time analog signal processing.

which follows is confined to this type of device. Reed
relays have three advantages; they are easy to apply (current
through a coil opens or closes isolated contacts), they will
handle signals of the order of hundreds of volts, and their
ON-resistance is low. So what does the solid-state analog
switch have to offer? It outperforms the mechanical relay
in almost every other specification. It is much faster, does
not suffer from contact bounce problems, is more rugged
since there are no moving parts, has several times the
number of switches per package, and is easier to drive since
the switch can interface directly with TTL without requiring back-EMF diode protection, etc. The salient features
of the two switch types are given in Table 1.

The purpose of this note is twofold. Firstly, to act as an
introduction to analog switches to those who have hitherto
only used relays. Secondly, to compare and contrast the
features of the different switch families and to illustrate
their use with practical applications.

Analog switches can be thought of in terms of form A, B,
and C relays; it is only necessary to add some external connections as shown in Table 2. The table shows devices from
the IH5040 series, with the switch states for a logic "1 "
input. In the normal state (logic "0" input) the contact
closures drawn as closed would be open and vice versa.

RELAYS AND THE ANALOG SWITCH
Since the class of relay closest to the analog switch in terms
of cost and packaging is the reed relay, the comparison

TABLE 1

AMILY
~
PARAMETER

SIGNAL HANDLING
(VS = i 15V WHERE
APPLICABLE)
~N RE~ISTANCE

TYPICAL
REED RELAY

HYBRID FET &
BIPOLAR SWITCH
(lH5001)

C-MOS SWITCH
(IH5040)

VIRTUAL GROUND
SWITCH (lH5009)

POSITIVE SIGNAL
SWITCH (IH5025)

!300V

±8V

±14V

±15V
(NOTE 1)

OV TO +10V
(NOTE 2)

O.H?

30n

75n

lOOn

loon

I

_S_P~E~E~D__(~to~n~h~o~ff~)_~~~1~00~0~/~50~0~M~S-+_~0~.5~/l~.~OM_S_ _r-_l~.0~ro~.5~M_S_-r_ _0_.5~/~0.~5~M.S___~ ___
0._2_/0_.2_M_S_ _~
LOGIC COMPATIBILITY
STEADY STATE
QUIESCENT CURRENT

NO
10mA @ 15V

YES _ __+_---Y-E-S--+-3.5mA

10MA

YES
NONE

~H--E-N-O-N-)------~-----_+---------~.-----_+_-----COST PER CHANNEL
<$1.00
$2.50
<$1.00
< $1.00
@

1000 PCS

YES

1

.-_

NONE

---~;;.~o - -

NOTE 1: When used as recommended et the virtual ground point of an operational amplifier.
NOTE 2: A method of switching +20V signals is explained in the data sheet.

A. COMBINATION FET AND BIPOLAR
HYBRID DESIGNS

THE AVAILABLE SWITCH TYPES

These may be described as first generation single package
analog switches. In many respects they are equivalent to the
p.A709 in the op-amp world; both deserve credit for pioneering the concept of a complete building block in a single
package, and yet both have been outdated by advancing
technologies and design concepts.

There are basically four different switch types on the
market at the present time. They may be summarized as
follows:
a. Combination FET (MOS or Junction) and bipolar hybrid
designs.
b. Monolithic C-MOS Designs.
c. Simple low-cost J-FET "virtual ground" designs.
d. Simple low-cost "positive signal" designs.

This family is of hybrid construction and consists of a
Bipolar, monolithic driver chip and MOSFETs or junction

302

NOTE 1: Switch states are for logic "1 " input
NOTE 2: Pin Connections are for DIP package

TABLE 2. Relay Equivalent Contact Forms
FORMA

OUALA

FORMC

"

SPST
IH5040 IROS ION) <75n

DUAL SPST
IH5041 IR DS ION) <75n

SPDT
IH5050 IRDSION) < 30n)
IH5042IRDSION) < 75H)

VL

v,

5,

D,

53

D3

'N,
1"2

OPST
IH5044 IRos ION) <75H)

5,

0,

54

0,

DUAL DPST
IH5049 IRos ION) <30n)

DPDT
IH5046 IR DS ION) <75!11

IH5045 IRos ION) <75n)

DUAL C

DUAL B

5,

4PST
IH5047 IRos IONI <75n)

DUAL SPST
IH5048 IR DS ION) <30n)

O-,+-----<,....-...,f-C-o "J
e-o+------_-oVOL;1

SIGNAL
INPUTS

10

K!~

B. MONOLITHIC C·MOS ANALOG GATE.

C. VIRTUAL GROUND SWITCH FAMILY
FIGURE 5. SWITCHING AT VIRTUAL GROUND OF AN
OP-AMP (2 CHANNELS SHOWN)

The Combination FET and Bipolar Hybrid Designs and
Monolithic C·MOS Designs are families which feature great
versatility; while there are differences in signal handling
capability, speed, power consumption, etc., between the
two groups, there is little doubt that both families will
handle most switching needs. The disadvantage of this added
versatility is the price one pays for it. If you need the
flexibility to switch A.C. signals into any load, and up to
±10V amplitude, then you need either of the a) or b)
groups. On the other hand, if you are switching into the
inverting input of an operational amplifier, or are switching
low level signals, the IH5009 through IH5024 provides the
best cost performance tradeoff.
The IH5009 family came into being at Intersil to fill the
need for a $1 per channel switch function. It was found
that 40% of all switching applications encountered could be
satisfied by a simpler switch than the driver/gate combina·
tion designs. Since the switch could be simpler, the costs
were less and customer objectives could be met. This
"designing for need" concept led to the P·channel J-FET
analog switch (lH5009 family). A P-channel was chosen as
the gating element since it could be driven directly from
positive going logic (TTL); thus the TTL gate acted as a
driver for the FET and resulted in an immediate cost
saving to end users, since previous designs had required a
separate driver.

The diodes from the source to ground limit the swing at
the J-FET to +0.7V typically so the circuit operates
correctly regardless of the signal voltage.
While the intent of the 5009 family was to reduce cost,
some unique advantages accompany this reduction:
1. Since the TTL logic element is the driver, the switch is
very fast; this implies that most analog switches are
speed limited by the driver or translator and this is true.
If the driver takes 1 J,lS to switch from +15V to -15V
then toff time of driver-gate combination (N-channel)
will be approximately 1 J,lS. Only in the 5009 and the
5025 family is the FET speed capability fully utilized;
this then turns out to be inherent in the design. Typical
ton times are 50 nS and typical toff times are 150 nS.
2. The method of switching is current switching and the
output/input relationship follows the well known inverting feedback amplifier gain equation. If the op amp has
high open loop gain, the signal present at summing
junction will be J,lV or mV and therefore, the output is
just the input current times the total feedback resistance.
Thus, for 0.1% or 0.01% switching accuracy, a feedback
J-FET is used in series with the feedback resistor (R f );

305

this feedback F ET compensates for the error due to Iin X
Ros loss at the input (Ros = "on" resistance of P-JFET).
In the 5009 family, a "compensating FET" is included in
the package specifically for this purpose (Fig. 6). The
two FETs track so the gain tracks through temperature
and system accuracy can be maintained.

by using a +30V supply at open collector terminal point.
There is no restriction on the load, as in the 5009 family,
and load resistances from 50n to infinity are easily handled.
A typical switching circuit is shown in Fig. 8 below:

AlOA,U

+15V

-

ANI~~~~ o---,\'O"K","...,---,

10 Kfl

fAOM

At

TTL OUTPUT

lin

FIGURE 8. TYPICAL SWITCHING CIRCUIT (ONE CHANNEL)

Notice that no op amp is required to be part of the switching
circuit, as is the case in the 5009 family. The disadvantage
of this series is that negative signals cannot be switched
unless external parts are added as in Fig. 9.

FIGURE 6. USE OF "COMPENSATING FET" TO
REDUCE RDS(ONI ERROR

The 5009 series is broken up into two 'different groups.
All the odd-numbered parts (5009, 5011, etc.) are designed to be used with TTL open collector logic (+15V
power supply) while the even-numbered one. are designed to be used with +5V TTL logic. For odd-numbered
parts, the J-FETs have a pinch-off voltage of 4V to 10V
and a maximum ROS(on) of lOOn (65n typical) and
the even numbers have a pinch-off range of 2V to 3.9V
and a maximum ROS(on) of 150n (90n typical).

."W"'%;::~'"

I
.w

f~"
~

"

I>':Pl'l

For both even and odd numbers, the match between
any two channels is beUer than 50n and versions at 25n,
lOn, 5n are available at increased cost over the basic
50n match. Additional information on the 5009 series
is given in Intersil Application Note A004 "The IH5009
Series of Low Cost Analog Switches."

FIGURE 9. SWITCHING BIPOLAR SIGNALS
USING THE IH5025

Thus, by adding a PNP (2N3638 or 2N2907, etc.) and two
resistors, the 5025 family becomes just as versatile as any
other analog switch. Of course, open collector logic must
still be used. When switching only positive signals, so that
the circuit is driven directly from logic, speed is very fast;
in fact, t(on) "" 50 nS and t(off) "" 200 nS up to R L = 1 K
loads (C L ~ 10 pF). When driving through PNPstageshown,
speed is considerably reduced (to 300 nS, 1 j.l.S for t(on) ,
t(off) respectively).

D. POSITIVE SIGNAL SWITCH FAMILY
Just as the 5009 series fits a particular need for virtual
ground switching applications, the IH5025 through IH5038
fits into a certain niche when only positive signals are
switched. The 5025 series has been designed to switch any
signal from OV to +10V using TIL open collector logic
(+15V power supply). Signals up to +25V can be switched

The 5025 fami Iy is broken up into 2 distinct groups, all of
which have a pinch-off range of 2V to 3.9V. The oddnumbered parts have a maximum ROS(on) of lOOn and the
even numbers have a maximum of 150n; the difference
between the two groups is that a larger geometry FET is
used for odd-numbered parts. This larger geometry, while
producing a lower on resistance, also inherently has about
twice the charge injection when compared with the evennumbered parts. This is specified at 20 mV maximum into
10,000 pF for all parts. Typical charge injections are 7 mV
for even-numbered parts and 14 mV for odd-numbered parts.
As with the 5009 family, the 5025 series has a channel to
channel ROS(on) match of 50n or less, with typicals running
in the 25n area.
While the 5025 family has been targeted for use with TTL
open collector logic, it can be used with 5V logic under the
restraint that a maximum of 1 V signal is switched. While
this is rather restrictive, there are a few applications where
this 1 V maximum would be no problem; i.e., when switching
transducer signals directly.

FIGURE 7. IH5025 SCHEMATIC

306

COMPARING THE PARAMETERS

'OS(ON) AS A FUNCTION OF THE
ANALOG SIGNAL VOLTAGE

Table 1 compares the key features of different switch types.
A more detailed description of specific parameters follows:

A. SIGNAL HANDLING
It has already been pointed out that one of the primary
differences between relays and semiconductor switches is
the degree of isolation between the control signal and the
signal being switched. In the case of the semiconductor
switch, the maximum analog signal that can be handled is
related to the characteristics of the FETs or MOSFETs, and
the supply voltages. When the switch itself is an N channel
J-FET, which in the absence of any gate bias is in the ON
state, the device is held off by driving the gate towards the
negative supply. Clearly, if the potential on the drain or
source comes within Vp (the pinch-off voltage) of the gate,
the device will turn on. With MOSFETs an analogous
situation exists: The analog signal modulates the gate bias
and can give rise to incorrect switch states if the recommended signal amplitudes are exceeded.

FIGURE 10. J-FET SWITCH

~OS(ON) AS A FUNCTION OF THE

mmm

ANALOG SIGNAL VOLTAGE
10

'~

-+ I--~::f$

-.

~

For virtual ground family (IH5009, etc.) the situation is
somewhat different. The maximum signal which can be
handled at the switch itself is only +700 mV; however, when
used as recommended at the virtual ground point of an
op-amp, signals at Vin and Vout may be much larger, as
previously stated (i.e., ±100V). It is worth noting that low
level signals, such as those from a thermocouple, may be
switched using an IH5009 without the need for an op-amp
provided the amplitudes are less than 700 mV.

.~
~

-j--

p...J-+--+.1.0

~

......... r - i

=~ _.. _.
-I---.

0

Z
I

Z

f-+---+--

t-I---+--+-!

i

+.-

--I-----I---+'-+~_+-!~

Q

9

I

I

o. 1 '--..J---'----J._i.-..J---'-~'__'
-10
-5
a
5
10
VANALOG-V

FIGURE 11. P-MOS SWITCH

B. ON RESISTANCE
'OS(ON) AS A FUNCTION OF THE
ANALOG SIGNAL VOLTAGE

The ON-resistance of a good reed relay is substantially less
than that of a typical analog switch. However, the widespread use of high input-impedance op-amp buffers has
tended to decrease the importance of ON-resistance as a
key parameter. It is almost always possible to design the
circuitry interfacing with the switch so that an ON-resistance
of 30n to lOOn does not contribute a substantial error.
Some of these techniques are illustrated in the applications
given on pages 10 through 16.

2.0 r--'--'--'--,--r~-,--,

- - - --r-

u

ekl

1.51---+--I--~--+,---j-+--I---l

53

N

::;

t--+--t...-l-+--I--d-t---I

«

1.0

~
Z

V
'"
0.5 t--+-+-i--+-+-+-f--l

~"..

~

In the case of the IH5009 series, the effective ON-resistance
of the switches may be further reduced by use of the "compensating FET" as described earlier.

.........

~~10~--~5~-~0~-~5-~'0
VANALOG-V

FIGURE 12. C-MOS SWITCH

The linearity of ON-resistance as a function of the analog
signal is dependent on the switch type. For junction F ET
switches, which are normally on, ROS(on) is independent of
the analog signal (Fig. 10). For P-MOS switches, a negative
gate bias is required to turn the device on. The analog signal
thus modulates the bias Voltage, giving rise to the characteristics seen in Fig. 11. In the case of the C-MOS switch, the
ROS(on) of the "p" and the "n" channel in parallel tend to
compensate, as shown in Fig. 12.

C. SPEED
Table 1 shows the maximum switching times for various
switch families. The waveform photos which follow illustrate the typical performance that can be expected under
normal operating conditions. When the 5009 and the 5025
series are used in conjunction with an op-amp, the switching
characteristics are usually limited by the slew rate and
settling time of the op-amp. At the present time, for
example, there are no monolithic op-amps capable of
swinging 10 volts and settling to .01% in less than 500 nS,
even though the IH5009 is capable of such performance.

The temperature characteristics of the different switch types
are shown in Fig. 13 through 15.
307

roS(ON) AS A FUNCTION OF
TEMPERATURE

roS(ON) AS A FUNCTION OF
TEMPERATURE

roS(ON) AS A FUNCTION OF
TEMPERATURE
2.0

2. 0

"

~g
"

1.5

I----t--+--t

«

"ii'
"

~
o

-.......

1.0

Z

Z

I

Z

0.5

o

~

0.5

~

1.5

0

....

i

I
I

~

~

1!l"

I

1.5

N

N

I

~

"w

W

Z

1!l"

~~

1.0

"ii'

i

V

0

Z

I

Z

0.5

~

o
-25

75

o

125

-75

TEMPERATURE-OC

TEMPERATURE-OC

FIGURE 13. J·FET SWITCH

25

.,...,

0

--75

.....V

-25

25

75

125

TEMPEAATURE-OC

FIGURE 14. P-MOS SWITCH

FIGURE 15. C-MOS SWITCH

TYPICAL SWITCHING WAVEFORMS

..

LOGIC
INPUT

ovfL
LOGIC
INPUT

VOUT

+10V
_OUTPUT
OV

HORIZONTAL = 1 p.s/div·
VERTICAL = 5V/div
FIGURE 16. OG118 (Note "Make-Belore-Break"' Action)

4

-lOV

VOUT

.ov

ovJ"1.
LOGIC

INPUT

HORIZONTAL = 1 p.s/div
VERTICAL = 5V/div

FIGURE 17. IH5010

308

10kll

..

LOGIC
INPUT

+10V
_OUTPUT

I ~) \..

uv.fL

OV

LOGIC
INPUT

HORIZONTAL = 1 ,"sid;v
VERTICAL (TOP) = 10V/d;v
VERTICAL (BOTTOM) = 5V/d;v

FIGURE 18. IH5025

..

LOGIC
INPUT

+10V
-OUTPUT
OV

HORIZONTAL = 1 ,"s/d;v
VERTICAL = 5V/d;v

FIGURE 19. IH5041 (Note ··Break·Belare·Make'" Action)

FIGURE 21.

FIGURE 20.
INTERFACING 5009 FAMILY WITH 5V ANO 15V TTL

,-

-----~

I
I

FIGURE 23

FIGURE 22
INTERFACING 5025 FAMILY WITH 5V AND 15V TTL

FIGURE 25

FIGURE 24
INTERFACING 5040 FAMILY WITH 5V AND 15V TTL

309

D. LOGIC COMPATIBILITY

ryl
":"
I

All the popular solid state switches are compatible with
TTL output swings; some require a pull-up resistor to
guarantee correct operation however. Schematics showing
how to interface with both standard (5V) TTL and high
level open collector (15V) are given in Fig. 20 through 25.

vo';OSCOPE
PROBE il0X)
lQ.OOOpF

'15V

E. POWER SUPPLIES

ovn.

The I H5009 and IH5025 require no external supplies; the
only power used is gate leakage current drawn from the
logic. The I H5040 C-MOS circuits require ±15 volts and
+5 volts, but again the only steady state power drain is a
leakage current of 1 J.lA typical. The hybrid switches
utilizing bipolar drivers require ±15 volt supplies, and
typically use 2 mA in the ON condition. In the OFF state
this current is much reduced and may only consist of a few
microamps.

FIGURE 26. CHARGE INJECTION TEST CIRCUIT

F. CHARGE INJECTION
Most analog switches exhibit some degree of charge injection, due to capacitive coupling between the FET gate and
the channel. This is a difficult parameter to riefine in
quantitative terms since it depends on the rate of change of
the gate drive signal.
However, it turns out that all the analog gates under discussion in this note exhibit similar charge injection characteristics. Using the I H5025, for example, in the test circuit
of Fig. 26, the waveform at the output is as shown in
Fig. 27. Note that the equivalent circuit of Fig. 26 is simply
a capacitance divider between the gate·channel capacitance
and the load capacitance. For other operating conditions,
the amplitude of the charge injection spike can be scaled
proportionately. For example, doubling the size of the load
capacitance will halve the spike amplitude.

UPPER WAVEFORM = LOGIC INPUT (10V/div)
LOWER WAVEFORM = OUTPUT (5 mV/div)
HORIZONTAL = 1.0 I's/div

FIGURE 27. IH5025 CHARGE INJECTION

SUMMARY
As a guide to users trying to decide which of Intersil's family of analog gates is most appropriate for their system needs, the
following summary may help to narrow the choice:
Use

Intersil Family & Key Features

Any portable equipment

IH5040 CMOS family. Lowest power dissipation (25 J.lW typ.). Compatible
with CMOS logic levels.

Telephone switching

IH5009 or IH5025 family. Very fast switching to allow multiplexing many
signals over the same line; lowest cost part.

Computer interfacing equipment
(Disc readouts. Read and write circuits
from memory drums, etc.)

IH5009 or IH5025 family for low cost.

Video or radar switching

IH5025 family for fastest speed.

Military Avionics
a. Ground support material

DGl16 thru DG164 familY or IH5040 family when versatility is more
important than cost.

b. Airborne equipment

IH5040 family for minimum waste of power and versatility to perform
many different switching functions with the same part.

Any switching done in conjunction with
operational amplifiers (i.e., switched
integrators, switched gain, integrating
sample and hold, etc.)

IH5009 family can be switched directly from logic in virtual ground
applications.

Any system requiring switch to be off
when power is off

DGl16 thru DG125 family or IH5050 family. MOSFET and CMOS devices
require power to be turned on.

310

APPLICATIONS -

DG120 SERIES

0<1120

"

'Ill

l ~OUN~-lOO; J
AiJ\j 51:

L~C

,

FIGURE 29. GAIN PROGRAMMABLE AMPLIFIER

FIGURE 30. PROGRAMMABLE INTEGRATOR WITH RESET

311

APPLICATIONS -

IH5009 SERIES (Cant.>

10

10: F

K~!

ANALuG
INPuTS

TOO;!
>--~"'VII'v-""-O OUTPUT

1 SO

'3

"

p~

CHARACTERISTICS SLEW RATE

lOY liS

GAIN ALCURACY
5", IIH50091 TO 05"'0
1IT$73/2) Sf'! Tahle 1

'----v------'
CHANNEL
SELECT

FIGURE 31. LOW COST 4 CHANNEL MULTIPLEXER
01IJF

r- -

-IH5009IHSoiO - - --,

I
I
10

I
I

K~!

I
I

\0

A"lALQG
li'IIPUTS

8001

"

K~!

10 K!!

10 K!!

"
-= !

7

8

'----v----'
CHANNEL

SAMPLE HOLD
SELECT

CHARACTERISTICS TYPICAL OUTPUT
VOLTAGE DRIFT

, 5mV'sec

SELECT

FIGURE 32. 3 CHANNEL MULTIPLEXER WITH SAMPLE & HOLD

1 MU

r - - - - - iHsOO9.iHrFlo- - - - - ---,

1 M!!

t--"'--'V'r-<>-~~
15pF

110 KH

"
2041(H
10 K1:

E.... '\...

101 KH

~

"
'":

,
CH4

CHARACTERISTICS GAIN" 1 fOR CHANNEL 1 ON, CHANNELS 2,3,4 OFF
GAIN" 2 FDA CHANNEL 2 ON. CHANNELS 1. 3, 4 OFF
GAIN ~ 10 FOft CHANNEL JON. CHANNELS 1. 2.4 OFf
GAIN:
FOR CHANNEl40N. CHANNelS 1, 2. 3 OFF
GAIN: 100 FOR ALL CHANNELS OFF
SLEW RATE' lOV>AS

so

eH3

CH2

CHI

FIGURE 32. GAIN RANGING CIRCUIT

312

APPLICATIONS -

IH5009 SERIES (CanU

10

NOTE

THE ANALOG SWITCH BETWEEN THE QP AMP AND THE
161NPLJT SWITCHES REDUCES THE ERRORS DUE TO LEAKAGE

CHARACTERISTICS ERROR ~ 0 4iJV TYPICAL@ 25 C
10).lV TYPICAL @ 70··C

FIGURE 33. 16 CHANNEL MULTIPLEXER

313

APPLICATIONS -IH5025 SERIES

r--------,·]!'>v
I

fJ 'lOV

SIGNAL
I~PUT

()V TO ':lOV

I

I
I
I
.J\,

OV.rL.,

I
I

L!"~:"::.\':":'"

FIGURE 36. SWITCHING UP TO +20V
SIGNALS WITH T2L LOGIC

FIGURE 35. SAMPLE AND
HOLD SWITCH

FIGURE 34. MULTIPLEXER
FROM POSITIVE
OUTPUT
TRANSDUCERS

r---------,

-:
-: I
____ J

'15V

I

I

IRe.,

I
I

f 1 Kl1
ITO

"OKW

I

QSt.,G,' IJR

'~I(,Il,All'"PUT~

SI\lILAR TO FIGURES 10IJR 11

~HOULD8[

A

<;CHE~H

uSfD

FROMCQNTROL

lOGIC

FIGURE 39. HIGH INPUT IMPEDANCE GAIN CONTROL FOR POSITIVE INPUT SIGNALS USING IH5025.

315

APPLICATIONS -

IH5040 SERIES

.,.,5V
+-lSV

>"---'0

APPLICATIONS - IH5040 SERIES (CanU

lOOk!!

10,OOOpF

l00k!1

10,OOOpF

100k~1

SII~~C~ D---'IM..-.........

6Sk!!

Constant Gain, Constant Q,
Variable Frequency Filter
which provides simultaneous
Lopass, Bandpass, & Hipass
outputs
i. e. with components shown
Q = 100, Gain = 100
fn

= Center

6aOk!! I

1
Frequency = - 2"RC

C = 10,OOOpF & R = 6Bkn or 6BOkn
(depending upon Logic Statel.
System Quiescent Current <300J,lA

FIGURE 42. DIGITALLY TUNED LOW POWER ACTIVE FILTER.

DF

317

ThelH5009
Analog Switch Series

INTRODUCTION

The Compensating FET

The IH5009 series of analog switches described in this note
were designed by Intersil to fill the need for an easy-to-use,
inexpensive switch for both industrial and military applications. Although low cost was one of the primary design
objectives (less than $1/switch in volume), performance and
versatility have not been sacrificed. Up to four channels per
package are available, no external power supplies are
required, and switching speeds are guaranteed to be less
than 500 ns.

Those devices which feature common drains (IH5009, 5010,
5013,5014, etc') have another FET in addition to the channel
switches (Figure 2>' This FET, which has gate and source
connected such that VGS = 0, is intended to compensate for
the on-resistance of the switch. When placed in series with
the feedback resistor (Figure 3) the gain is given by
GAIN =
10 kO + Tos (compensator)
10 kO + Ros (switch)
Clearly, the gain error caused by the switch is dependent on
the Hlaich between the FETs nather than the absoiuie vaiue oi

CIRCUIT OPERATION
Switching Virtual Ground Signals
The signals seen at the drain of a junction FET type analog
switch can be arbitrarily divided into two categories: Those
which are less than ±200 mV, and those which are greater
than ±200 mY. The former category includes all those circuits where switching is performed at the virtual ground
point of an op-amp, and it is primarily towards these applications that the IH5009 family of circuits is directed. In
applications where the signal amplitude at the switch is
greater than ±200 mV, the simple design of the IH5009 is no
longer appropriate and a more complex switch design is
called for. See REF. 1 for a complete discussion of this type
of switch.

the FET on-resistance. For the standard product, all the FETs
in a given package are guaranteed to match within 500.
Selections down to 50 are available however. The part
numbers are shown in Table I. Since the absolute value of
ROS(ON) is only guaranteed to be less than 1000 or 1500, it is
clear that a substantial improvement in gain accuracy can be
obtained by using the compensating FET. This is only true
however when the input resistor and the feedback resistor
are similar in value: for dissimilar values, the benefits of the
compensating FET are less pronounced.
COMPENSATING FET
S

0

0

~

S

It is important to realize that the ±200 mV limitation applies
only to the signal at the drain of the FET switch; signals of
±10V or greater can becommutated by the IH5009 in acircuit
of the type shown in Figure 1. For a high gain inverting
amplifier the signal level at the virtual ground point will only
be a few microvolts for +10V input and output swings.

FIGURE 2: SCHEMATIC OF IH5009 & IH5010

COMPENSATION
FET

10KSl

10 K~l
>----.l_oQ ±10V

1

ANALOG
INPUT

10 K~2

>-_~_~

=
FIGURE 1: SWITCHING AT VIRTUAL GROUND POINT

FIGURE 3: USE OF COMPENSATION FET

ANALOG
OUTPUT

TABLE I
EFFECTIVE
PART
NUMBER

INPUT
LOGIC DRIVE

rOS(ON)

rOS(ON)

(OHMS)
MAX.
100

DESCRIPTION

(OHMS)
MAX.

IH5009

High Level

4-Channel, 15V Logic

50

IH5010

DTL, TTL, RTL

4-Channel, 5V Logic

50

150

IT87318

High Level

4-Channel, 15V Logic

25

100

IT87319

DTL, TTL, RTL

4-Channel, 5V Logic

25

150

IT87320

High Level

4-Channel, 15V Logic

10

100

IT87321

DTL, TTL, RTL

4-Channel, 5V Logic

10

150

IT87322

High Level

4-Channel, 15V Logic

5

100

IT87323

DTL, TTL,RTL

4-Channel, 5V Logic

5

150

IH5013

High Level

3-Channel, 15V Logic

50

100

IH5014

DTL, TTL, RTL

3-Channel, 5V Logic

50

150

IT87324

High Level

3-Channel, 15V Logic

25

100

IT87325

DTL, TTL, RTL

3-Channel, 5V Logic

25

150

IT87326

High Level

3-Channel, 15V Logic

10

100

IT87327

DTL, TTL, RTL

3-Channel, 5V Logic

10

150

IT87328

High Level

3-Channel, 15V Logic

5

100

IT87329

DTL, TTL, RTL

3-Channel, 5V Logic

5

150

IH5017

High Level

2-Channel, 15V Logic

50

100

IH5018

DTL, TTL,RTL

2-Channel, 5V Logic

50

150

IT87330

High Level

2-Channel, 15V Logic

25

100

IT87331

DTL, TTL, RTL

2-Channel, 5V Logic

25

150

IT87332

High Level

2-Channel, 15V Logic

10

100

IT87333

DTL, TTL, RTL

2-Channel, 5V Logic

10

150

IT87334

High Level

2-Channel, 15V Logic

5

100

IT87335

DTL, TTL, RTL

2-Channel, 5V Logic

5

150

IH5021

High Level

1-Channel, 15V Logic

50

100

IH5022

DTL, TTL, RTL

1-Channel, 5V Logic

50

150

IT87336

High Level

1-Channel, 15V Logic

25

100

IT87337

DTL, TTL, RTL

1-Channel, 5V Logic

25

150

IT87338

High Level

1-Channel, 15V Logic

10

100

IT87339

DTL, TTL, RTL

1-Channel, 5V Logic

10

150

IT87340

High Level

1-Channel, 15V Logic

5

100

IT87341

DTL, TTL, RTL

1-Channel, 5V Logic

5

150

Logic Compatibility
off of the FETs is selected to be less than 3.7V (Vp @ 10 = 1
nA); therefore, a positive logic level +4.5V will supply
adequate safety margin for proper gating action. To
guarantee this +4.5V from series 54174 TTL logic requires the
use of a pull-up resistor: Values from 2 kO to 10 kO are
suitable depending upon the speed requirements (Figure 4),
Alternatively the TTL may be operated from +6V supplies.
The "1" level will then be greater than +4.5V without the need
for a pull-up resistor. The maximum on-resistance is guaranteed for +0.5V on the gate of the FET. 8ince the maximum
low level outut voltage from TTL is O.4V, the ON-resistances
specified are conservative. With OV applied to the FET gate,
typical ON-resistances of 900 will be Obtained.

The 5009 through 5024 series parts are primarily intended for
constant - impedance multiplexing. The diode connected to
the J-FET source acts like a shunt switch, while the FET itself
acts as a series switch. The advantage of this configuration is
its high noise immunity when the series element is off. The
diode then clamps the source to +0.7 TYP. with a low AC
impedance to ground and prevents false triggering of the
FET for positive inputs. Negative inputs present no problems
since they further increase the OFF voltage beyond pinchoff.
The even-numbered devices in the family (5010 through
5024) are designed for interfacing with 5V logic. The pinch319

The odd-numbered devices in the family (5009 through 50231
are designed for interfacing with 15V logic. The pinch-off of
these parts is selected to be less than 10V, so that a +llV
positive logic level provides adequate safety margin. To
obtain this level from open collector TTL logic also requires a

pull-up resistor; 1 kO to 10 kO is suitable depending on the
speed and fan-out requirements (Figure 5), The ONresistance is measured with +1.5V applied to the gate and is
guaranteed to be less than 1000 at 25°C. ForOVon the gate,
the typical RON is 600.

ANALOG
INPUT

r---- -------,
I
I

I
I

10KS2

I
IREXT
I (2KQ
I TO
110KQI

I
I
I

+5V

fIT
l

r--4~-,")ANALOG
OUTPUT

----L-~

I
I
I
I
I
I

I

10KQ

LOGIC
INPUT

I

15VTTLGATE=
=1
L ___________
..J

FIGURE 4: INTERFACING WITH +5V LOGIC

:: '·i

ANALOG
INPUT

r - - - - - - -- - - -

'+15V

i,~f{~,_
I

10K~1

ANALOG
OUTPUT

-

I
I
I

10K~1

INPUT

=

I
I
I
I

I

1
TTL GATE =
=
L15V
___________

..JI

FIGURE 5: INTERFACING WITH +15V OPEN COLLECTOR LOGIC

320

Switching Speed and Crosstalk

In applications where low ON-resistance is critical, special
selections can be made. Since high pinch-off FETs have
lower ON-resistances than low pinch-off types (for a given
geometry) it is advantageous to make such selections from
the odd-numbered devices and use high level TTL for the
control logic.

The switching speed is guaranteed to be less than 500 ns at
25° C. Typical turn-on and turn-off times are 150 ns and 300
ns, respectively.
When analog switches are used in conjunction with operational amplifiers, settling time is often an important
parameter. In a typical fast amplifier, settling times of 1 /-'s to
0.1% are seen. This time is primarily caused by non-linear
modes of operation within the amplifier, and the inclusion of
an analog switch at the virtual ground point will not cause
significant degradation of the settling time.
Crosstalk can be measured using the circuit of Figure 6. At
low frequencies, it is very difficult to obtain accurate values
since the separation is better than 120 dB. Typical crosstalk
as a function of frequency is shown in Figure 7.

Maximum Switch Current
The maximum current through the switch is dictated
primarily by leakage considerations rather than power
dissipation problems. When the drain of the FET is held at
virtual ground, current through the channel tends to bias the
source positive. Eventually, the source-gate junction will
forward bias, giving rise to large leakage currents. This is
most likely to occur at high temperature when the junction
turn-on potential is at its lowest. The data sheet guarantees
maximum leakage for Is = 1 mA and 2 mA, with VIN =OV. The
substantial increase seen in the leakage in changing Is from
1mA to 2mA (at 70°C) indicates that the turn-on potential is
being approached rapidly under these conditions.
Specifying the leakage for VIN (the gate potential) = OV is a
worst case condition; under most circumstances VIN = +200
mV would be a more typical value. Thus 200 mV additional
signal would be required at the source to give the same
leakage current.

PRODUCT SUMMARY
Table 2 shows the different product numbers, their schematics, and their equivalent circuits. The even numbers are
designed to be driven from 5V TTL, while odd numbers are
designed to be driven from TTL open collector logic (15VI.

10KIl

10KIl

1..

VOUT
10KIl

VIN

~
20V
~Pk-"k
.. 5V 15010 ETCI
+15V 15009 ETCI

FIGURE 6: CROSSTALK MEASUREMENT CIRCUIT

CROSSTALK AS A FUNCTION OF FREOUENCY
-130
-120
-110

'~

,,
"\

-100

iii

~

'"----+-0 EOUT

CHARACTERISTICS: ERROR

EIN16~

NOTE:

= O.4I'V TYPICAL

@ 25'C
lOIN TYPICAL @ 70°C

THE ANALOG SWITCH BETWEEN THE OP-AMP AND THE
16 INPUT SWITCHES REDUCES THE ERRORS DUE TO LEAKAGE.

16 CHANNEL MULTIPLEXER

325

A New CMOS
Analog Gate
Technology
INTRODUCTION

HIGH
CURRENT
PATH

A new C-MOS process has been developed by Intersil which
is destined to have a significant impact on the future of this
technology in the fabrication of analog gates and
multiplexers.
Up to the present time, all the analog gates and multiplexers
manufactured with standard C-MOS technology have
suffered from a serious limitation: under certain conditions,
these circuits "latch-up", i.e., go into a non-operative state.
They will only recover if both the power supplies and the
input are removed and reapplied in a specific sequence.
Under some circumstances the latch-up is destructive and
the only cure is replacement of the I.C.
This new process, developed and patented by Intersil, totally
eliminates these problems. As well as preventing the latchup condition, this process provides effective overvoltage
protection (to ±25V) without degradation of ON-resistance.

V,N

T
0

N-CHANNEL

However, the diode is not sufficient in itself to give rise to the
latch-up phenomena. but careful inspection of the cross
section shown in Figure 3 will reveal that this diode forms
part of an SCA. The drain and body of the N-channel FET
form the emitter and base of the NPN transistor part of the
SCR (Figure 4), the body of the P-channel FET (the substrate)
acts as the collector; the source and body of the P-channel
FET form the emitter and base ofthe PNP part ofthe SCR and
the body of the N-channel device forms the collector for this
PNP. If the beta product of these two transistors exceeds 1,
an excellent SCR is formed. It is clear from Figure 4 that
grounding the body of the N-channel FET (the gate of the
SCR) and applying a negative potential to the analog input
(the cathode of the SCR) will turn on the SCR and cause it to
latch.

UNDERSTANDING THE LATCH-UP PROBLEM

ANALOG
SIGNAL
INPUT

ANALOG
SIGNAL
OUTPUT

PCHANNEL

N CHANNEL
LOGIC
INPUT

RL
1

Figure 2: Dangerous Condition

A simplified schematic of one channel of a typical C-MOS
analog switch (or multiplexer) is shown in Figure 1.

v

~ ~~';.~~~~ 0 - - - - - - - - . : : ,

RL
GATE

GATE

N CHANNEL BODY
(P- TUB)

P CHANNEL BODY
(N- SUBSTRATE)

Figure 1: Typical C-MOS Analog Switch or Multiplexer
Figure 3: C-MOS Cross Section

The latch-up condition occurs when a negative analog signal
is applied to either the drain or source of the MOS transistors
while V- is at av. Since analog switches are frequently used
to interface between different systems and sub-systems,
these conditions occur surprisingly often, especially if the
different parts of the system or sub-system have
independent power supplies. It should also be noted that
these conditions have only to occur briefly (as transients) for
latch-up to take place.
With V- at av, and a negative potential on the analog inputor
output, a high current path exists through the forward biased
body to drain junction of the N-channel device. Permanent
damage or complete destruction of the I.C. can result from
this current. This is shown in Figure 2.

NPN EMITTER

PNP EMITTER

LATERAL
PNP

N-

PPNP COLLECTOR
NPN BASE

PNP BASE
NPN COLLECTOR
GATE
SCR
CATHODE

Figure 4: The SCA Structure

326

INTERSIL'S FLOATING BODY PROCESS

CONCLUSION

Intersil's improved C-MOS process incorporates an
additional diode in the connection to the body of the Nchannel FET (Figure 5), The cathode of this diode is then tied
to V+, thus effectively floating the body. The inclusion of this
diode not only blocks the excessive current path described
earlier, but also prevents the SCR from turning on. As an
additional precaution, processing changes have been
incorporated which reduce the beta product of the NPN-PNP
combination to less than one. Thus in the unlikely event of
excessive over-voltages being applied to the circuit (which
could break down the blocking diode) the SCR action will
still not occur.

Prior to "Floating Body" technology, solutions to the latchup problem have involved either using expensive and exotic
manufacturing processes, such as dielectric isolation, orthe
addition of external components. Apart from being
inconvenient, adding external components such as current
limiting resistors always compromises the electrical
performance.
The new "Floating Body" C-MOS technology overcomes
these problems and has resulted in a reliable, low cost
monolithic analog gate function. For the first time it is
possible to realize a inonolithic gate capable of approaching
$1.00 per channel without compromising performance or
rei iabi Iity.

+15V

ANALOG
SIGNAL
INPUT

0

i:Rl

-------JtG
OUTPUT
-------(0)--------,

jQ1
Figure 5: Protective Circuitry for N-channel FET.

327

DF

Reduce CMOS-Multiplexer Troubles
Through Proper Device Selection
CMOS analog multiplexers exhibit problems with output leakage
currents and overvoltage-protection circuitry. Here's how
to deal with them.

.A. Cr,fOS analog' nlultiplcxcr (~.1UX) is basiea!!~p a
whieh ean intel'faee signal ~en~ol'~ and eomputel'R. It provides a number
of input channel~, which are time-Rhared onto a
common output terminal. A central computer or
milToprocl'ssol' digitally sequenees the MUX to
"sel'" 0lH' l'hannel at a time. The goal of designers is to pass the sl'nsed signal through this
muitiplexl'l' with vil'tuall~' no elTOI' tel'ms present. PI'oviding adequate ovel'voltage proteetion
also pn'sents a l'halll'nge. Both objectives ean
tax dl'sigl1l'l's' ing'enuity unless they are familial'
with muitipll'xl'l' anatom~·.
:\lan~' dl'sig'IH'l's dl'visl' unnl'l'essal'ily complex
ehannel-~eleetol' ~witeh

circuits in their efforts to avoid the substantial
level of error terms that can be encountered
during the multiplexing operat.ion and to provide
overvoltage protection for the CMOS circuitry.
But you can save pc-board space, reduce component count and cost, and avoid the possibility of
introducing new errors through proper identification of error sources. And adequate circuit
self-protection is the result of the proper choice
of multiplexing devices.
Output leakage-the major error source
A typical data-acquisition system, extending
from sensors to computer, is shown in Fi~ 1. Here
the sensors feed directly into the multiplexer
input lines, but this is an idealized case, because

DIGITAL COMMANDS

Fig 1-Although the multiplexer diagrammed here is a "01-4 device. multiplexers in data-acquisition systems can switch as
lew as two or as many as 1000 channels to a common output.

328

Identification of error sources
reduces component count and cost
most users insert operational amplifiers between
the sensors and the MUX inputs. You can
eliminate these op amps, however, if you utillze
an Ie MUX with very low output leakage currents.
CMOS MUL TlPLEXER

SENSOR

INPUT

v.

,,.(ON)

+

~

100., --

I

~

j

100•• -

t

100.,-

Most popular CMOS analog multiplexers have
finite ON resistance and leakage currents. Typical of these lCs are the DG506 to DG509 (Siliconix), Hl506 to Hl509 (Harris) and the lH6116/6208
Series (lntersii).
As noted, the design goal for the system in Fig
1 is to transfer the sensed signal into the
sample-and-hold circuit with as little error as
possible. Some potential error sources are labeled
in Fig 2. One such error source arises from a
voltage-divider action between r,lS"'~' of a multiplexer ON channel (a consequence of finite
channel resistance) and the input impedance of
the follower op amp (Rill)' The signal level at the
positive input of the op amp is equal to the sensor
voltage times Rin/Rin+rlls""" And the error produced is equal to the ratio of R in to Rill+r,lS"".
Because R in (at low frequencies to dc
level)= 100MH and r,lS""'= 1 kO, the error equals
10"/10"+ 10"= III + 10-'. This set of conditions yields
an accuracy of 0.001 %; rIl S" ' ' ' can range as high as
10 k!l and still provide 0.01% accuracy. The
obvious conclusion to be drawn is that the r'M,\I

100•• -

'ON V,n/rOSCONI
'TOTAC -".'UT .OA" 'ON' 'O""~
R.
TOSiH

~I
BUFFER OP AMP

Fig 2-Wilh aU bul one channel OFF, this equivalent clfcuit
for the MUXlbuffer portion of Fig 1 shows potential error
terms.

1.,

l

Fig 3-800sllng sensor oulpullevels can overcome leakage
and r,,,,,,,, errors, but you must pay for the added op amps
and the resistors.

NORMAL OPERATION

Ibl

MUL TIPLEXER POWER OFF

'15V FROM INTERNAL
TRANSLATOR

G
N·CHANNEL TRANSISTOR

COMMON
OUTPUT

SENSOR
INPUT

COMMON
OUTPUT

,NPUT

P·CHANNEL TRANS'STOR

P·CHANNEL TRANSISTOR

1

'15V FROM 'NTERNAL TRANSLATOR

Fig 4-The diagram in -i_C_O_N_~_r_RT_E_R_~

~--~

y'MtH

COUNTER

I I I I I

TWISTED
PAIR LINE

Fig. 3. Using VIF converters
for remote data transmission.

make a VIF converter is shown in
Fig. 6. This is a unique method of
realizing voltage to pulse rate
conversion with a very high degree
of linearity. The circuit consists of
an operational integrator with a
pulse generating feedback loop
around it.

ANALOG SECTION

The circuit operates as follows. A
positive input voltage causes a
current to flow into the operational
integrator through R I . This current
is integrated by the amplifier and
capacitor to produce a negativegoing ramp at the output. When the
ramp crosses the comparator
DIGITAL SECTION

j' - - - - - - - - - - - - - - - - - 1- - - - - - - - - - - - - - - - - - - - - - - -

I

1

I

lllllllllil'1

1
I
ANALOG
INPUT

0----<>--;

VIF
CONVERTER

+FS

VOLTAGE IN

-1
I

11111
--11ll.I.--

I
I
I
I
I

1
DIGITAL
COUNTER

I

1
1
I
1

JL

I
I

I
I
I

I
I

I
I

~L~~~o-~r---------------------------t--4~

TIMER

PARALLEL
DIGITAL
OUTPUT

1
1
1
1
I

I1.. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ L
I ________________________ I
Fig. 4. The VIF converter used as an AID converter.

336

threshold voltage at ground, the device requires a bias resistor, compensating capacitors. It has
comparator output changes state output pull-up resistor, and two provision for both an external zero
and causes a pulse timing circuit to
generate a narrow voltage pulse.
Fig. 5. Nonlinearity 01 charge-balancing AID converter.
This pulse controls switch S"
which switches from ground to a
111 ... 111 - - - - - - - - - - - - - - - - - - - - ,
negative reference voltage for the
,,
duration of the pulse. During this
,,
/
time a narrow pulse of current flows
w
out of the integrator through R•.
,
o()
,
,
This current pulse is also integrated
,/
5a.
by the operational integrator, and
/.' NONLINEARITY
5 100 ... 000
causes a rapid ramp up in the output
o
voltage for the duration of the pulse.
,
...J
,
This process is then repeated,
/
,/
a2i
creating a sequence of pulses that
/
are also buffered as the output of
,/
/
the VIF converter.
/
,/
A higher input voltage to the
000 ... 000,J:....~--'--~~L--'---'---~-!.­
charge-balancing circuit causes the
o
+%FS
+FS
integrator to ramp down faster,
INPUT VOLTAGE
thereby generatil)g pulses at a higher
rate from the pulse timer circuit.
Fig. 6. Charge-balancing VIF converter circuit.
Likewise, a lower input voltage
causes the integrator to ramp down
slower and generates pulses at a
A,
lower rate than before.
Y'N O---"JWv--+---i
The term "charge-balancing" is
I,
appropriate since the feedback loop,
which is closed around the integrator, causes an average of the current
pulses (through R.). Each current
pulse through R. is a fixed charge of
VREF
value:
Q=-,r,- x 7' = T I,
where 7' is the width