1980 MCS 48 Users Manual
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MCS-48™ FAMILY OF SINGLE
CHIP MICROCOMPUTERS USER'S MANUAL
September 1980
Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which
may appear in this document nor does it make a commitment to update the information contained herein.
Intel software products are copyrighted by and shall remain the property of Intel Corporation. Use, duplication or
disclosure is subject to restrictions stated in Intel's software license, or as defined in ASPR 7·104.9 (a) (9). Intel Cor·
poration assumes no responsibility for the use of any circuitry other than circuitry embodied. in an Intel product. No
other circuit patent licenses are implied.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent
of Intel Corporation.
The following are trademarks of Intel Corporation and may only be used to identify Intel products:
BXP
CREDIT
i
ICE
ICS
im
Insite
Intel
Intelevision
Intellec
iSBC
iSBX
Library Manager
MCS
Megachassis
Micromap
MULTIBUS*
MULTIMODULE
PROMPT
Promware
RMX
UPI
flScope
and the combinations of ICE, iCS, iSBC, MCS or RMX and a numerical suffix.
MDS is an ordering code only and is not used as a product name or trademark. MDS® is a registered trademark of
Mohawk Data Sciences Corporation.
*MULTIBUS is a patented Intel bus.
Additional copies of this manual or other Intel literature may be obtained from:
Literature Department
Intel Corporation
3065 Bowers Avenue
Santa Clara, CA 95051
© INTEL CORPORATION, 1980
AFN·01300A-1
Table of Contents
CHAPTER 1
Introduction
1.0 Introduction to MCS-48™ ................................................................... 1-1
1.1 The Functions of a Computer ............................................................... 1-5
1.2 Programming a Microcomputer ............................................................ 1-10
1.3 Developing an MCS-48™ Based Product .................................................... 1-13
CHAPTER 2
The Single Component MCS-48™ System
8048/8748/8035 and 8049/8039
2.0 Summary ....................................................'............................ 2-1
2.1 Architecture ............................................................................. 2-1
2.2 Pin Description ......................................................................... 2-14
2.3 Programming, Verifying and Erasing EPROM .............................................. 2-16
2.4 Test and Debug ......................................................................... 2-18
8021
2.5 Program Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.6 Data Memory ...........................................................................
2.7 Oscillator and Clock .....................................................................
2.8 Timer/Event Counter ....................................................................
2.9 Input/Output Capabilities ................................................................
2.10 CPU ...................................................................................
2.11 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2-20
2-20
2-21
2-21
2-22
2-24
2-24
8022
2.12 Program Memory ......................................................................
2.13 Data Memory ..........................................................................
2.14 Oscillator and Clock ....................................................................
2.15 Timer/Event Counter ...................................................................
2.16 Input/Output ...........................................................................
2.17 Test and Interrupt Inputs ................................................................
2.18 Analog to Digital Converter ................................................. ; ...........
2.19 CPU ...................................................................................
2.208022 Testing .............................................. '.............................
2-25
2-25
2-26
2-26
2-26
2-27
2-28
2-29
2-29
CHAPTER 3
The Expanded MCS-48™ System
3.0 Summary .................................................................................. 3-1
3.1 Expansion of Program Memory .............................................................. 3-1
3.2 Expansion of Data Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-4
3.3 Expansion of Input/Output .................................................................. 3-5
3.4 Multi-Chip MCS-48™ Systems ............................................................... 3-9
3.5 Bank Switching ........................................................................... 3-10
3.6 Control Signal Summary ................................................................... 3-11
3.7 Port Characteristics ....................................................................... 3-11
CHAPTER 4
Instruction Set
4.0 Introduction ............................................................................... 4-1
4.1 Instruction Set Description ....................... ." .......................................... 4-4
CHAPTER 5
Application Examples
5.0 Introduction ............................................................................... 5-1
5.1 Hardware Examples ........................................................................ 5-1
5.2 Software Examples ................................................ '............. : . . . . . . . . .. 5-22
iii
CHAPTER 6
MCS-48™ Component Specifications
8048H/8048H-1/8035HU8035HL-1 HMOS Single Component 8-Bit Microcomputer .................. 6-1
8048L Special Low Power Comsumption Single Component 8-Bit Microcomputer .................. 6-8
8048/8035U8748/8748-6/8035 Single Component 8-Bit Microcomputer ............................. 6-9
108048/8748/8035L Industrial Temperature Range Single Component 8-Bit Microcomputer ......... 6-18
M8048/M8748/M8035L Single Component 8-Bit Microcomputer .................................. 6-27
New High Performance 8049/8039/8039-6 Single Component 8-Bit Microcomputer ................ 6-36
New High Performance 18049/8039 Single Component 8-Bit Microcomputer ...................... 6-41
8021 Single Component 8-Bit Microcomputer ................................................... 6-48
8022 Single Component 8-Bit Microcomputer With On-Chip NO Converter ....................... 6-51
8243 MCS-48™ Input/Output Expander ......................................................... 6-57
108243 MCS-48™ Input/Output Expander ....................................................... 6-63
8355/8355-2 16,384-Bit ROM With I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-69
8755A 16,384-Bit EPROM With I/O ............................................................. 6-74
8155/8156/8155-2/8156-22048 Bit Static MOS RAM With I/O Ports and Time ....................... 6-82
8185/8185-21024 x 8-Bit Static RAM for MCS-85™ .............................................. 6-96
CHAPTER 7
MCS-S1TM Component Specification
8051/8751/8031 Microcomputer ................................. " .............................. 7-1
CHAPTERS
Compatible MCS-48™ Components
2114A 1024 x 4-Bit Static RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-1
2316E 16K (2K x 8) ROM ........................................................ " .............. 8-5
2708 8K (1 K x 8) UV Erasable PROM ............................................................. 8-8
2716 16K (2K x 8) UV Erasable PROM .......................................................... 8-12
2732A 32K (4K x 8) UV Erasable PROM ......................................................... 8-17
8205 High Speed 1 out of 8 Binary Decoder ..................................................... 8-18
8212 8-Bit Input/Output Port .................................... '" ............................ 8-24
8214/3214 Priority Interrupt Control Unit ........................................................ 8-34
8216/8266 4-Bit Parallel Bidirectional Bus Driver ................................. " ............. 8-38
8282/8283 Octal Latch ........................................................................ 8-43
8286/8287 Octal Bus Transeiver ................................................................ 8-48
CHAPTER 9
Peripherals
8251A/S2657 Programmable Communication Interface ........................................... 9-1
8253/8253-5 Programmable Interval Timer ....................................................... 9-6
8255A/8255A-5 Programmable Peripheral Interface .............................................. 9-17
8259A Programmable Interrupt Controller ...................................................... 9-38
8272 Single/Double Density Floppy Disk Controller .............................................. 9-51
8273,8273-4,8273-8 Programmable HDLC/SDLC Protocal Controller ............................. 9-67
8279/8279-5 Programmable Keyboard/Display Interface .......................................... 9-70
8291 GPIB Talker/Listener ..................................................................... 9-82
8292 GPIB Controller .......................................................... '" ........... 9-106
8293 GPIB Transceiver ................................................................. , ..... 9-108
8294 Data Encryption Unit ....................... '" ............................ " .........•.. 9-121
8041 N8641N8741 A Universal Peripheral Interface 8-Bit Microcomputer ......................... 9-123
iv
CHAPTER 10
Support Products
Model 22SIntellec Series II .................................................................... 10-1
Intellec Prompt 48 MCS-48™ Microcomputer Design Aid ......................................... 10-6
ICE-49 MCS-48™ In-Circuit Emulator .......................................................... 10-12
EM1 8021 Emulation Board .................................................................. 10-16
EM2 8022 emulation Board ................................................................... 10-19
UPP-103 Universal PROM Programmer ........................................................ 10-22
SP-49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-24
Insite User's Library ......................................................................... 10-26
APPENDICES
Packing Information .......................................................................... A1-1
Ordering Information ......................................................................... A2-1
v
I.n troduction
INTRODUCTION
microcomputer. A single 5V supply requirement for all MCS-48 components
assures that "low cost" also applies to
the power supply in your system.
1.0 Introduction to MCS-48™
Recent advances in NMOS technology
have allowed Intel for the first time to place
enough .capability on a single silicon die to
create a true single-chip microcomputer
containing all the functions required in a
digital processing system. A set of such
microcomputers on single chips, their
variations, and optional peripherals are
collectively called the MCS-48 microcomputer family. These products are fully
described in this manual.
New Family Members
The MCS-48 family of microcomputers
which began with the 8048 and 8748 has
now been expanded with new members
which provide either more capability or
lower cost than the original family members. While broadening the applications
possible with a single chip microcomputer,
these new microcomputers share both the
instruction set and development support of
the 8048.
The head of the family is the 8048
microcomputer which contains the following
functions in a single 40 pin package:
8-Bit CPU
1K x 8 ROM Program Memory
64 x 8 RAM Data Memory
27 I/O Lines
8-Bit Timer/Event Counter
The 8049 is a single-chip microcomputer
which is completely interchangeable with
the 8048, but contains twice the program
memory and twice the data memory of the
8048.
A 2.5 or 5.0 microsecond cycle time and a
repertoire of over 90 instructions, each
consisting of either one or two cycles,
makes the single chip 8048 the equal in
performance of most presently available
multi-chip NMOS microprocessors. The
8048 is, however, a true "low-cost"
8049
The 8022 is an 8021-based microcomputer
with additional memory, 1/0, and an AID
converter.
The 8021 is a new very low cost MCS-48
family member which contains a subset of
8048
8021
8022
FEATURES
8·BIT CPU
PROGRAM MEMORY
DATA RAM
1/0 LINES
TIMER COUNTER
OSCILLATOR AND CLOCK
RESET CIRCUIT
INTERRUPT
~
~
~
~
2Kx8
128x 8
27
1Kx8
64x8
27
1Kx 8
64x8
21
2Kx8
64x 8
28
~
~
~
~
~
~
~
~
~
~
~
~
~
~
ON CHIP FEATURES
1-1
~
INTRODUCTION
the 8048's instruction set and incorporates
several new features critical in low cost
applications.
Even with low component costs, however, a
project may be jeopardized by high development and rework costs resulting from an
inflexible production design. Intel has solved
this problem by creating two pin-compatible
versions of the 8048 microcomputer: the
8048 with mask Programmable ROM program memory for low cost production and
the 8748 with user programmable and
erasable EPROM program memory for
prototype development. The 8748 is essentially a single chip microcomputer "breadboard" which can be modified over and over
again during development and pre-production then replaced by the low cost 8021 *,
8048, or 8049 ROM for volume production.
The 8748 provides a very easy transition
from development to production and also
provides an easy vehicle for temporary field
updates while new ROMs are being made.
SPECIAL FEATURES
•
•
•
•
•
•
•
•
•
SINGLE 5V SUPPLY
40 PIN DIP OR 28 PIN DIP
PIN COMPATIBLE ROM AND EPROM
2.5,5.0 AND 10.0 J,Lsec CYCLE VERSIONS
ALL INSTRUCTIONS 1 OR 2 CYCLES
SINGLE STEP
8 LEVEL STACK
2 WORKING REGISTER BANKS
LC, XTAL, OR EXTERNAL
FREQUENCY SOURCE
• OPTIONAL CLOCK OUTPUT
• POWER DOWN STANDBY MODE
To allow the MCS-48 to solve a wide range
of problems and to provide for future
expansion, all 8048 and 8049 functions
have been made externally expandable
using either special expanders or standard
memories and peripherals. An efficient low
cost means of I/O expansion is provided by
either the 8243 I/O Expander or standard
TTL or CMOS circuits. The 8243 provides
16 1/0 lines in a 24 pin package. For systems with large 1/0 requirements, multiple
8243s can be used.
For such applications as Keyboards, Displays, Serial communication lin~s, etc.
standard MCS-80/85 peripheral circuits
may be added. Program and data memory
may be expanded using standard memories
or the 8355 and 8155 memories that also
include programmable I/O lines and timing
functions.
For applications which require a more
custom tailored interface, the 8041 or 8741
Universal Peripheral Interface (UPI-41)
devices can be used. The UPI-41 devices
are available in both ROM and EPROM
versions and are essentially slave versions
of the 8048/8748 which are designed to
interface directly with expandable MCS-48
processors and provide flexible intelligent
I/O capability. The 8041/8741 share the
instruction set of the MCS-48 family of
processors.
The 8035 and 8039 are an 8048 or 8049
respectively without internal program
memory that allows the user to match his
program memory requirements exactly by
using a wide variety of external
memories. The 8035 and 8039 allow the
user to select a minimum cost system no
matter what his program memory reo
quirements. The 8035L is an 8035 with the
powerdown mode of the 8048.
The MCS-48 processors are designed to be
efficient control processors as well as
arithmetic processors. They provide an
instruction set which allows the user to
directly set and reset individual lines within
its 1/0 ports as well as test individual bits
within the accumulator. A large variety of
branch and table look-up instructions
l11ake these processors very efficient in
implementing standard logic functions.
Also, special attention has been given to
code efficiency. Over 70% of the instructions are a single byte long and all others
are only two bytes long. This means many
functions requiring 1.5K to 2.0K bytes in
other computers may very well be compressed into the 1K words resident in the
8048 or up to 3K to 4K equivalent bytes may
be compressed into the 8049.
*The 8021 is code compatible but not pin compatible with the 8748.
1·2
INTRODUCTION
FUNCTION
Microcomputers
PART
NUMBER
DESCRIPTION
COMMENTS
~~ :g~ :~~~~:~ ~:~~~ with AID } 10 I'sec Cycle
Compatible versions of the
single chip microcomputers pro·
vide mask programmed, light
erasable, or no internal program
memory.
8021
8022
8048
8035
8035L
8049
8039
8748-8
8035-8
8748-6
1K ROM Program Memory
No Program Memory 64 x 8 RAM
2.5 I'sec Cycle
8035 with Power Down Mode
2K ROM Program Memory
} 1.36 I'sec Cycle
No Program Memory 128 x 8 RAM
1K EPROM Program Memory
} 5.0 I'sec Cycle
No Program Memory
1K EPROM 0°C-55°C, 6 MHz
Memory and I/O
Expanders
8355
8755A
8155/56
8185
2K x 8 ROM with 16 I/O Lines
2K x 8 EPROM with 16 110 Lines
256 x 8 RAM with 22 I/O Lines and Timer
1Kx 8HAM
Compatible devices allow direct
expansion of MCS-48 functions
with no additional external com·
ponents.
::Ii
I-
'"til
~
0
:::Ii
f
I/O Expander
8243
16 Line I/O Expander
Low cost I/O expander.
Standard ROMs
2308
2316E
2332
1Kx8
2Kx8
4Kx8
450 ns
450 ns
450 ns
Allows low cost external expan·
sion of Program Memory. Each
ROM is interchangeable with an
EPROM.
Standard EPROMs
2708
2716
2732
1Kx8
2Kx8
4Kx8
450 ns Light Erasable
450 ns Light Erasable
450 ns Light Erasable
User programmable and eras·
able.
Standard RAMs
2111A-4
2101A-4
256x4
256x4
450 ns Common I/O
450 ns Separate I/O
Data memory can be easily ex·
panded using standard NMOS
RAMs .
Standard I/O
8212
8-B it I/O Port
8255A
Programmable Peripheral Interface
8251A
Programmable Communication Interface
!II
....z
w
Z
0
II..
:::Ii
0
0
::Ii
I-
'"ill
'"
til
0
:::Ii
w
....I
III
Standard Peripherals
i=
et
II..
:;;
0
0
·Universal Peripheral
Interface
Serves as Address Latch or I/O
port.
Three 8-bit programmable 110
ports.
Serial Communications Receiv·
er/Transmitters.
8273
Programmable HDLC/SDLC Controller
8205
8214
8216
8226
8253
8279/78
MCS-80 peripheral devices are
compatible with the MCS-48, al·
lowing easy addition of such
specialized interfaces as the
8279 Keyboard/Display Interface.
Future MCS-80/85 devices will
also be compatible.
8291
8294
8295
1·of-8 Binary Decoder
Priority Interrupt Controller
Bidirectional Bus Driver
Bidirectional Bus Driver (Inverting)
Programmable Interval Timer
Programmable Keyboard/Display Interface
(64 Keys/128 Keys)
GPIB Talker/Listener
Data Encryption Unit
Dot Matrix Printer Controller
8041A
8741A
ROM Program Memory
EPROM Program Memory
User programmable to perform
any custom I/O and control func·
tions.
MCS·48™ MICROCOMPUTER COMPONENTS
1-3
INTRODUCTION
384
8049
8155
8049
8155
835&
320
8048
8355
8155
8048
8155
(38)
(38)
(S3)
(53)
128
8049
8049
8355
64
8048
8048
8355
(24)
(24)
1K
(28)
2K
3K
(28)
4K
PROGRAM MEMORY (ROM)
( ) NUMBER OF AVAILABLE
1/0 LINES
THE EXPANDED MCS-48™ SYSTEM
The chart above shows the expansion
possibilities using the 8048 and 8049 in
various combinations with the Intel® 8355/
8755 Program Memory and I/O Expander
and the 8155 Data Memory and I/O
Expander. Data Memory can be expanded
beyond the resident words in blocks of 256
by adding 8155's. Program Memory can be
expanded beyond the resident 1K or 2K in
blocks of 2K by using the 8355/8755 in combination with the 8048 or 8049. If all external
memory is desired, the 8035 or 8039 can be
substituted for the 8048 and 8049.
1-4
INTRODUCTION
1.1 The Function of a Computer
printer, to a peripheral storage device, such
as a floppy disk· unit, or the output may
constitute process control signals that direct
the operations of another system, such as an
automated assembly line. Like input ports,
output ports are addressable. The input and
output ports together permit the processor to
communicate with the outside world.
This chapter introduces certain basic computer concepts. It provides background
information and definitions which will be
useful in later chapters of this manual. Those
already familiar with computers may skip this
material, at their option.
1.1.1 A Typical Computer System
The CPU unifies the system. It controls the
functions performed by the other components. The CPU must be able to fetch
instructions from memory, decode their
binary contents and execute them. It must
also be able to reference memory and I/O
ports as necessary in the execution of
instructions. In addition, the CPU should be
able to recognize and respond to certain
external control signals, such as INTERRUPT requests. The functional units within a
CPU that enabl~ it to perform these functions
are described below.
A typical digital computer consists of:
A central processor unit (CPU)
Program Memory
Data Memory
Input/output (I/O) ports
The processor memory serves as a place to
store Instructions, the coded pieces of
information that direct the activities of the
CPU, while Memory stores the Data, the
coded pieces of information that are
processed by the CPU. A group of logically
related instructions stored in memory is
referred to as a Program. The CPU "reads"
each instruction from memory in a logically
determined sequence, and uses it to initiate
processing actions. If the program sequence
is coherent and logical, processing the
program will produce intelligible and useful
results. The program must be organized such
that the CPU does not read a non-instruction
word when it expects to see an instruction.
1.1.2 The Architecture of a CPU
A typical central processor unit (CPU)
consists of the following interconnected
functional units:
Registers
Arithmetic/Logic Unit (ALU)
Control Circuitry
Registers are temporary storage units within
the CPU. Some registers, such as the
program counter and instruction register,
have dedicated uses. Other registers, such as
the accumulator, are for more general
purpose use.
The CPU can rapidly access any data stored
in memory; but often the memory is not large
enough to store the entire data bank required
for a particular application. The problem can
be resolved by providing the computer with
one or more Input Ports. The CPU can
address these ports and input the data
contained there. The addition of input ports
enables the computer to receive information
from external equipment (such as a paper
tape reader or floppy disk) at high rates of
speed and in large volumes.
Accumulator
The accumulator usually stores one of the
operands to be manipulated by the ALU. A
typical instruction might direct the ALU to
add the contents ofsome other reg ister to the
contents of the accumulator and store the
result in. the accumulator itself. In general,
the accumulator is both a source (operand)
and
destination (result) register. Often a
CPU will include a number of additional
general purpose registers that can be used to
store operands or intermediate data. The
availability of general purpose registers
A computer also requires one or more Output
Ports that permit the CPU to communicate
the result of its processing to the outside
world. The output may go to a display, for use
by a human operator, to a peripheral device
that produces "hard-copy", such as a line-
a
1·5
INTRODUCTION
eliminates the need to "shuffle" intermediate
results back and forth between memory and
the accumulator, thus improving processing
speed and efficiency.
this kind of jump, the pJOcessor is required to
"remember" the contents of the program
counter at the time that the jump occurs. This
enables the processor to resume execution
of the main program when it is finished with
the last instruction of the subroutine.
Program Counter (Jumps, Subroutines and
the Stack):
A Subroutine is a program within a program.
Usually it is a general-purpose set of
instructions that must be executed repeatedly in the course of a main program.
Routines which calculate the square, the
sine, or the logarithm of a program variable
are good examples of functions often written
as subroutines. Other examples might be
programs designed for inputting data to a
particular peripheral device.
The instructions that make up a program are
stored in the system's memory. The central
processor references the contents of memory in order to determine what action is
appropriate. This means that the processor
must know which location contains the next
instruction.
Each of the locations in memory is
numbered, to distinguish it from all other
locations in memory. The number which
identifies a memory location is called its
Address. The processor maintains a counter
which contains the address of the next
program instruction. This register is called
the Program Counter. The processor updates the program counter by adding "1" to
the counter each time it fetches an
instruction, so that the program counter is
always current (pointing to the next instruction).
The processor has a special way of handling
subroutines, in order to insure an orderly
return to the main program. When the
processor receives a Call instruction, it
increments the Program Counter and stores
the counter's contents in a reserved memory
area known as the Stack. The Stack thus
saves the address of the instruction to be
executed after the subroutine is completed.
Then the processor loads the address
specified in the Call into its Program Counter.
The next instruction fetched will therefore be
the first step of the subroutine.
The programmer therefore stores his instructions in numerically adjacent addresses, so
that the lower addresses contain the first
instructions to be executed and the higher
addresses contain later instructions. The
only time the progrl:immer may violate this
sequential rule is when an instruction in one
section of memory is a Jump instruction to
another section of memory.
The last instruction in any subroutine is a
Return. Such an instruction need specify no
address. When the processor fetches a
Return instruction, it simply replaces the
current contents of the Program Counter
with the address on the top of the stack. This
causes the processor to resume execution of
the calling program at the point immediately
following the original Call instruction.
A jump instruction contains the address of
the instruction which is to follow it. The next
instruction may be stored in any memory
location, as long as the programmed jump
specifies the correct address. During the
execution of a jump instruction, the processor replaces the contents of its program
counter with the address embodied in the
Jump. Thus, the logical continuity of the
program is maintained.
Subroutines are often Nested; that is, one
subroutine will sometimes call a second
subroutine. The second may call a third, and
so on. This is perfectly acceptable, as long as
the processor has enough capacity to store
the necessary return addresses, and the
logical provision for doing so. In other words,
the maximum depth of nesting is determined
by the depth of the stack itself. If the stack has
space for storing three return addresses, then
A special kind of program jump occurs when
the stored program "Calls" a subroutine. In
1·6
INTRODUCTION
signals that can then be used to initiate
specific actions. This translation of code into
action is performed by the Instruction
Decoder and by the associated control
circuitry.
three levels of subroutines may be accommodated.
Instruction Register and Decoder
Every computer has a Word Length that is
characteristic of that machine. A computer's
word length is usually determined by the size
of its internal storage elements and interconnecting paths (referred to as Buses); for
example, a computer whose registers and
buses can store and transfer 8-bits of
information has a characteristic word length
of 8-bits and is referreq to as an 8-bit parallel
processor. An 8-bit parallel processor generally finds it most efficient to deal with 8-bit
binary fields, and the memory associated
with such a processor is therefore organized
to store 8-bits in each addressable memory
location. Data and instructions are stored in
memory as 8-bit binary numbers, or as
numbers that are integral multiples of 8-bits:
16-bits, 24-bits, and so on. This characteristic
8-bit field is often referred to as
Byte. If
however, efficient handling of 4 or even 1-bit
data is necessary special processor instructions can provide this capability.
An 8-bit instruction code is often sufficient to
specify a particular processing action. There
are times, however, when execution of the
instruction requires more information than 8bits can convey.
One example of this is when the instruction
references a memory location. The basic
instruction code identifies the operation to be
performed, but cannot specify the object
address as well. In a case like this, a two byte
instruction must be used. Successive instruction bytes are stored in sequentially adjacent
memory locations, and the processor performs two fetches in succession to obtain the
full instruction. The first byte retrieved from
memory is placed in the prbcessor's instruction register, and subseq!Jent byte is placed
in temporary storage; t~e processor then
proceeds with the executio l1 phase.
a
Address Register(s)
Each operation that the processor can
perform is identified by a unique byte of data
known as an Instruction Code or Operation
Code. An 8-bit word used as an instruction
code can distinguish between 256 alternative
actions, more than' adequate for most
processors.
A CPU may use a register to hold the address
of a memory location that is to be accessed
for data. If the address register is Programmable, (Le., if there are instructions that allow
the programmer to alter the contents of the
register) the program can "build" an address
in the address register prior to executing a
Memory Reference instruction (Le., an
instruction that reads data from memory,
writes data to memory or operates on data
stored in memory).
The processor fetches an instruction in two
distinct operations. First, the processor
transmits the address in its Program Counter
to the program memory. Then the program
memory returns the addressed byte to the
processor. The CPU stores this instruction
byte in a register known as the Instruction
Register, and uses it to direct activities during
the remainder of the instruction execution.
Arithmetic/Logic Unit (ALU)
All processors contain an arithmetic/logic
unit, which is often referred to simply as the
ALU. The ALU, as its name implies, is that
portion of the CPU hardware which performs
the arithmetic and logical operations on the
binary data.
The 8-bits stored in the instruction register
can be decoded and used to selectively
activate one of a number of output lines. Each
line represents a set of activities associated
with execution of a particular instruction
code. The enabled line can be combined with
selected timing pulses, to develop 'el'ectrical
The ALU must contain an Adder which is
capable of combining the contents of two
registers in accordance with the logic of
binary arithmetic. This provision permits the
1·7
INTRODUCTION
fetches the next instruction, and so on. This
orderly sequence of events requires precise
timing, and the CPU therefore requires a free
running oscillator clock which furnishes the
reference for all processor actions. The
combined fetch and execution of a single
instruction is referred to as an Instruction
Cycle. The portion of a cycle identified with a
clearly defined activity is called a State. And
the interval between pulses of the timing
oscillator is referred to as a Clock Period. As
a general rule, one or more clock periods are
necessary for the completion of a state, and
there are several states in a cycle.
processor to perform arithmetic manipulations on the data it obtains from memory
and from its other inputs.
Using only the basic adder a capable
programmer can write routines which will
subtract, multiply and divide, giving. the
machine complete arithmetic capabilities.
In practice, however, most ALUs provide
other built-in functions, including boolean
logic operations, and shift capabilities.
The ALU contains Flag Bits which specify
certain conditions that arise in the course of
arithmetic and logical manipulations. It is
possible to program jumps which are
conditionally dependent on the status of one
or more flags. Thus, for example, the
program may be designed to jump to a
special routine if the carry bit is set following
an addition instruction.
Instruction Fetch
The first state(s) of any instruction cycle will
be dedicated to fetching the next instruction.
The CPU issues a read signal and the
contents of the program counter are sent to
program memory, which responds by
returning the next instruction word. The first
byte of the instruction is placed in the
instruction register. If the instruction consists of more than one byte, additional states
are required to fetch the second byte of the
instruction. When the entire instruction is
present in the CPU, the program counter is
incremented (in preparation for the next
instruction fetch) and the instruction is
decoded. The operation specified in the
instruction will be executed ih the remaining
states of the instruction cycle. The instruction may call for a data memory read or write,
an input or output and/or an internal CPU
operation, such as a register-to-register
transfer or an add operation.
Control Circuitry
The control circuitry is the primary functional
unit within a CPU. Using clock inputs, the
control circuitry maintains the proper sequence of events required for any processing
task. After an instruction is fetched and
decoded, the control circuitry issues the
appropriate signals (to units both internal
and external to the CPU) for initiating the
proper processing action. Often the control
circuitry will be capable of responding to
external signals, such as an interrupt. An
Interrupt request will cause the control
circuitry to temporarily interrupt main program execution, jump to a special routine to
service the interrupting device, then automatically return to the main program.
Memory Read
An instruction fetch is merely a special
program memory read operation that brings
the instruction to the CPU's instruction
register. The instruction fetched may then
call for data to be read from data memory
into the CPU. The CPU again issues a read
signal and sends the proper memory
address; memory responds by returning the
requested word. The data received is placed
in the accumulator or one of the other
geheral purpose registers (not the instruction register).
1.1.3 Computer Operations
There are certain operations that are basic to
almost any computer. A sound understanding of these basic operations is a necessary
prerequisite to examining the specific
operations of a particular computer.
Timing
The activities of the central processor are
cyclical. The processor fetches an instruction, performs the operations required,
1-8
INTRODUCTION
the processor's efficiency. Consider the case
of a computer that is processing a large
volume of data, portions of which are to be
output to a printer. The CPU can output a
byte of data within asingle machine cycle but
it may take the printer the equivalent of many
machine cycles to actually print the character specified by the data byte. The CPU
could then remain idle waiting until the
printer can accept the next data byte. If an
interrupt capability is implemented on the
computer, the CPU can output a data byte
then return to data processing. When the
printer is ready to accept the next data byte, it
can request an interrupt. When the CPU
acknowledges the interrupt, it suspends
main program execution and automatically
branches to a routine that will output the next
data byte. After the byte is output, the CPU
continues with main program execution.
Note that this is, in principle, quitesimilarto a
subroutine call, except that the jump is
initiated externally rather than by the
program.
Memory Write
A memory write operation is similar to a read
except for the direction of data flow. The
CPU issues a write signal, sends the proper
memory address, then sends the data word
to be written into the addressed data memory
location.
Input/Output
Input and Output operations are similar to
memory read and write operations with the
exception that an I/O port is addressed
instead of a memory location. The CPU
issues the appropriate input or output
control signal, sends the proper address and
either receives the data being input or sends
the data to be output.
Data can be input/output in either parallel or
serial form. All data within a digital computer
is represented in binary coded form. A binary
data word consists of a group of bits; each bit
is either a one or Ii zero. Parallel I/O consists
of transferring all bits in the word at the same
time, one bit per line. Serial I/O consists of
transferring one bit at a time on a single line.
Naturally serial I/O is much slower, but it
requires considerable less hardware than
does parallel I/O.
More complex interrupt structures are
possible, in which several interrupting
devices share the same processor but have
different priority levels. Interruptive processing is an important feature that enables
maximum utilization of a processor's capacity for high system throughput.
Interrupts
Interrupt provisions are included on many
central processors, asa means of improving
1·9
INTRODUCTION
1.2 Programming a Microcomputer
1.2.1 Machine Language Programming
counts the number of words to be stored.
When finished the processor continues on
to the next instructions.
A microprocessor is instructed what to do by
programming it with a series of instructions
stored in Program Memory. The processor
fetches these instructions one at a time and
performs the operation indicated. These
instructions must be stored in a form that the
processor can understand. This format is
referred to as Machine Language. For most
microprocessors this instruction is a group
of a binary bits (1's and O's) called a word
(also called a byte if the word is a-bits). Some
instructions require more than one location
in Program Memory. To execute a multi-byte
instruction, the processor must execute
multiple fetches of program memory before
performing the instruction. Because mUltibyte instructions take more Program Memory and take longer to execute than single
byte instructions their use is usually kept to a
minimum.
A processor may be programmed by
writing a sequence of instructions in the
binary code (ones and zeros) which the
machine can interpret directly. This is
machine language programming and it is
very useful where the program to be written
is small and the application requires that
the designer have an intimate knowledge of
the microprocessor. Machine language programming allows the user, because of his
detailed knowledge, to use many programming "tricks" to produce the most compact
and efficient code possible.
The following is an example of a machine
language program: This program reads 5
sequential 8-bit words in from an I/O port
and stores them sequentially in data
memory. The program starts by initializing
two registers, one which determines where
the data is to be stored and another which
Step
Number
Machine
Code
0
1
3
4
1011 1000
00100000
1011 1010
00000101
00001001
5
10100000
6
7
8
0001 1000
11101010
0000 0100
2
Explanation
Load decimal 32 in
register RO
Load decimal 5 in
register R2
Load Port 1 to accumulator
Transfer contents of
accumulator to register addressed by
register 0
Increment RO by 1
Decrement register 2
by 1, if result is zero
continue to step 9, if
not go to step 4
9
10
As you can see, writing machine instructions in ones and zeros can be very
laborious and subject to error. It is almost
always more efficient to represent each
a-bits of machine language code in a
shorthand format called Hexadecimal.
The term hexadecimal results from the
character set used in hexadecimal notation.
Hexadecimal is merely an extension of the
normal decimal numbers by the addition of
the first six letters of the alphabet. This
gives a total of 16 different characters. Each
hexadecimal "digit" can represent 16
values or the equivalent of four binary bits;
therefore, each a-bit machine language
word can be represented by 2 hexadecimal
(hex for short) digits. The correspondence
among the decimal, binary, and hex
number systems is given below:
1-10
INTRODUCTION
Decimal
Hex
Binary
0
1
2
3
4
5
0
1
2
3
4
5
6
7
6
7
8
8
9
9
A
B
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
10
11
12
13
14
15
C
0
E
F
step 8 would have to be changed to refer to
the new address of step 4.
1.2.2 Assembly Language Programming
Assembly language overcomes the disadvantages of machine language by allowing
the use of alphanumeric symbols to represent machine operation codes, branch
addresses, and other operands. For example,
the instruction to increment the contents of
register 0 becomes INC RO instead of the hex
18, giving the user at a glance the meaning of
the instruction. Our example program can be
written in assembly language as follows:
Step No. Hex Code
Our machine language program then
becomes:
Step
Hex Code
o
B8
20
BA
05
09
FO
18
EA
04
1
2
3
4
5
6
7
8
o
88
1
2
20
8A
05
09
AO
18
EA
04
3
4
5
6
7
Assembly Code
MOV RO, #32
MOV R2, #05
INP:
IN A, P1
MOV @RO, A
INC RO
DJNZ R2, INP
8
The first statement can be verbalized as
follows: Move to Register 0 the decimal
number 32. Move instructions are always
structured such that the destination is first
and the source is second. The pound sign "#"
indicates that the source is "immediate" data
(data contained in the following byte of
program memory). In this case data was
specified as a decimal 32, however, this could
have been written as a hex 20H or a binary
0010 00008 since the assembler will accept
either form. Notice also that in this instance
two lines of hex code are represented by one
line of assemlJly code.
The input instruction IN A, P1 has the same
form as a MOV instruction indicating that the
contents of Port 1 are to be transferred to the
accumulator. In front of the input instruction
is an address label which is delineated by a
colon. This label allows the program to be
written in a form independent of its final
location in program memory since the
branch instruction at the end of the program
can refer to this label rather than a specific
address. This is a very important advantage
of assembly language programs since it
This coding is now quite efficient to write
and read and coding errors are much easier
to detect. Hex coding is usually very
efficient for small programs (a few hundred
lines of code). However, it does have two
major limitations in larger programs:
1. Hex coding is not self-documenting, that
is, the code itself does not give any indication
in human terms of the operation to be
performed. The user must learn each code or
constantly use a Program Reference Card to
convert.
2. Hex coding is absolute, that is, the
program will work only when stored in a
specific location in program memory. This is
because the branch or jump instructions in
the program reference specific addresses
elsewhere in the program. In the example
above steps 7 and 8 reference step (or
address) 4. If the program were to be moved,
1·11
INTRODUCTION
allows instructions to be added or deleted
throughout the program during debugging
without requiring that any jump addresses be
changed.
2. Conditional Assembly - Conditional assembly allows the programmer to select only
certain portions of his assembly language
(source) program for conversion to machine
(object) code at assembly time. This allows
for instance, the inclusion of various "debug"
routines to be included in the program during
development. Using conditional assembly,
they can then be left out when the final
assembly is done.
The next instruction MOV @RO, A can be
verbalized as, Move to the data memory
location addressed by RO, the contents of the
accumulator. The @ sign indicates an
indirect operation whereby the contents of
either register 0 or register 1 acts as a pointer
to the data memory location to be operated
on.
The last instruction is a Decrement and Jump
if Not Zero instruction which acts in
combination with the specified register as a
loop counter. In this case register 2 is loaded
with 5 initially and then decremented by one
each time the loop is executed. If the result of
the decrement is not zero, the program jumps
to INP and executes another input operation.
The fifth time thru the loop the result is zero
and execution falls through to whatever
routine follows the DJNZ instruction.
Conditional assembly also allows several
versions of one basic program to be
generated by selecting various portions of a
larger program at assembly time.
3. Macro's - A macro instruction is essentially a symbol which is recognized by the
assembler to represent a specific sequence
of several standard instructions. A macro is
shorthand way of generating the same
sequence of instructions at several locations
in a program without having to rewrite the
sequence each time it is used. For example, a
typical macro instruction might beonewhich
performs a subtract operation. The 8048 does
not have a subtract instruction as such but
the operation can be performed easily with
three instructions:
CPLA
ADD A, REG
CPLA
This routine subtracts a register from the
accumulator and leaves the result in the
accumulator. This sequence can be defined
as a macro with the name SUB and an
operand which can be RO to R7. To subtract
R7 from the accumulator then, the programmer merely has to write:
SUB R7
and the assembler will automatically insert
the three instructions above with R7 substituted for REG.
a
In addition to the normal features provided
by assemblel'3, more advanced assemblers
such as that for the MCS-48 offer such things
as evaluation of expressions at assembly
time, conditional assembly, and macro
capability.
1. Evaluation of Expressions - Certain
assemblers allow the use of arithmetic
expressions and multiple symbols in the
operand portion of instructions. For instance
the MCS-48 assembler accepts instructions
such as:
ADD A, # ALFA*BETA/2
ALFA and BETA are two previously defined
symbols. At assembly time the expression
ALFA*BETA/2 will be evaluated and the
resulting number (which is the average of
ALFA and BETA) will be treated as
immediate data and .designated as the
second byte of the ADD immediate instruction. This expression has allowed the
immediate data of this instruction to be
defined in a single statement and eliminated
the need for a third symbol .equal to
ALFA*BETA/2.
Once the assembly language source code is
written it can be converted to machine
executable object code by passing it through
an assembler program. The MCS-48 assembler is a program which runs on the 8080based Intellec MDS system explained in the
next section.
1-12
INTRODUCTION
microprocessor is achieved, the functions to
be implemented can be defined using a
flowchart method to describe each basic
system function and the sequence in which
the processor executes these functions.
Once the system is flowcharted, critical timerelated functions can be identified and
sample programs written to verify that
performance requirements can be met.
1.3 Developing An MCS-48™ Based
Product
Although the development of a microcomputer based product may differ in detail from
the development cycle of a product based on
TTL logic or relays, the basic procedures are
the same - only the tools are different.
1.3.1 Education
1.3.3 Hardware Configuration
The first step of course is to become familiar
with what the microcomputer is and what it
can do. The first step in this education is this
document, the MCS-48™ User's Manual. The
user's manual gives a detailed description of
the MCS-48 family of components and how
they may be used in various system configurations. Also included is a description of the
8048 instruction set and examples of
how the instructions may be used. For a more
complete discussion of the instruction set
and programming techniques the MCS-48
Assembly Language Manual is also available.
The next step involves the definition of the
microcomputer hardware required to implement the function. Input/Output capability
must be defined in terms of number of inputs,
number of outputs, bi-directional lines,
latching or non-latching I/O, output drive
capability, and input impedance. The number of words of RAM storage required for
intermediate results and data storage must
then be determined. The type of system will
dictate whether battery backup is needed to
maintain data RAM during power failure.
If time is critical
in getting started in
microcomputers, individuals can attend one
of many Intel sponsored 5-day training
courses which give basic instruction in the
MCS-48 as well as hands-on experience with
MCS-48 development systems. These
courses are a convenient means of getting
started with the MCS-48, particularly for
those not familiar with microprocessors.
Probably the most difficult parameter to
define initially is the amount of program
memory needed to store the applications
program. Although previously written exercise programs will make this estimate more
accurate, a generous amount of "breathing
room" should be allowed in program memory
until coding is complete and the exact
requirements are known. Many special
functions such as serial communications
(TTY) or keyboard/display interfaces may be
implemented in software (programs); however, in cases where these functions place a
severe load on the processor in terms of time
or program memory, special peripheral
interface circuits such as the 8251, Universal
Synchronous or Asychronous Receiver/
Transmitter (USART) or 8279 Keyboard/
Display interface may be used.
After general familiarization is complete,
either through self-instruction or a training
course, the next step is to gain a better "feel"
for what a microprocessor can do in your
own applications by writing several exercise
programs which perform basic functions.
You may require such things as I/O routines,
delays, counting functions, look-up tables,
arithmetic functions, and logical operations
which can serve as a set of building blocks for
future applications programs. Several basic
programming examples are included in the
MCS-48 Assembly Language Manual while
the Intel User's Library is a source of more
specific applications routines.
1.3.4 Code Generation
The writing of the final program code for the
application can begin once the system
function and hardware have been defined
and can be generated in parallel with the
detailed hardware design (PC card layout,
power supply, etc.)
1.3.2 Function Definition
After a thorough understanding of the
1-13
INTRODUCTION
At this point, there are two paths available to
the designer/programmer and two types of
design development aids provided by Intel to
simplify the procedures. One system, called
PROMPT 48, is a low cost development
system which supports machine language
programming and the second is the Intellec
Microcomputer Development System which
supports both machine and assembly languages. For those of you unfamiliar with the
advantages and disadvantages of machine
and assembly languages see Section 1.2.
which a programmed .8748 executes its
program while under control of the monitor
routine.
Use of PROMPT 48 involves .the following
steps:
1. Loading an application program into the
PROMPT RAM memory via Hex keyboard or
external terminal (TTY and RS232 interface
provided).
2. Inserting an erased 8748 in the programming socket and transferring the application
program to its internal EPROM.
1.3.5 PROMPT 48
PROMPT 48 is a low cost design aid
consisting of: an 8748 processor to execute
programs, control circuitry to provide debug
functions such as single step and break
points, a monitor program stored in ROM,
an EPROM programmer, and ahexadecimal keyboard and display, There are two
processor sockets on the front ofF>ROMPT
48, one for programming the 8748 and one in
LOCKED
3. Transferring programmed 8748 to execution socket where program is executed and
debugged under control of the monitor.
The monitor routine allows the user to single
step this processor, examine or modify all
internal registers and data memory; or to run
at full speed and stop the processor at
predetermined breakpoints. PROMPT 48
LOCKED
49
40
40
lEt
50
H
I/O PORTS CONNECTOR
2
prompt 48
20
21
PROGRAMMING
SOCKET
20
21
EXECUTION
SOCKET
, _ _ - - - ' - COMMAND/FUNCTION GROUp· - - - - . . .
~FIFIBI11~IBIFIF~
I
I
FUNC1'ION
©
AODf!ESS
COMMANDS
POWER ON
EXAMINE/
MODIFY
REGISTER
GO
G~R~~:
POINTS
NEXT
DO
DO S~~~~E
DO
mI [c:JI EXi~~TEI
in~----------~--------------
1-14
DATA
HEX DATA/FUNCTIONS
DISPLAYI
MODIFY
'MEMORY
PREVIOUS/
ClEAR.ENTRY
________________________- 4
INTRODUCTION
macro-assembler and text editor programs
provided allow the designer to write and edit
his programs in assembly language and then
generate the machine language output
necessary to program the 8748 EPROM. The
availability of a high speed CRT and a
diskette operating system eliminates the
laborious input and output of paper tape files
normally required during the assembly
process. Finally, ICE 48 allows the user to
extend the resources of his entire Intellec
system into the 8048 socket of his own
system and use all its emulation, debug, and
display facilities directly.
also provides 1K of writeable program
memory which may be used to debug user
programs. A multiple single step feature
is also provided in which the processor steps
through its program dumping all internal
contents to external RAM where it may be
later displayed or typed out on an external
terminal. Paper tape input and output in
Intel's hexadecimal format is also available
through the TTY.
1.3.6 Intellec Development System
The Intellec Microcomputer Development
System is a modular development system
which can be expanded as necessary to meet
the requirements of your design cycle. The
system consists of the processor unit which
is based on Intel's 8080A microprocessor,
and several optional units such as the UPP
Universal PROM Programmer, the PTR High
Speed Paper tape reader, the DOS Disk
Operating System, and the Intellec CRT
terminal.
1.3.7 Production
Once a working program has been achieved,
a preproduction phase usually follows where
several prototype systems are evaluated in
simulated situations or in actual operation in
the field. During this period the use of the
8748 EPROM allows quick alteration of the
application program when problems or
suggested changes arise. Depending on the
magnitude and number of future changes
anticipated, the first production units may
also be shipped with EPROM processor.
However, to achieve the maximum cost
reduction potential in high volume applications, a conversion to the 8048 ROM is
usually necessary. This is an easy transition
since the 8048 and 8748 are pin and machine
code compatible equivalents. The user
merely develops a hexadecimal tape of his
8748 program memory contents using his
Intellec System or PROMPT 48 development
aid and sends it to Intel along with his 8048
order. As the 8048 ROM's arrive they can
immediately replace the 8748 EPROMs.
To support the development of MCS-48
systems a macro-assembler ASM 48 is
available for the Intellec System as well as a
personality module for the UPP which will
program the EPROM of the 8748. Also
available is in-circuit emulation capability
with ICE·49 which will allow emulation and
debug of user's 8048 application programs
on the 8080A-based Intellec Development
System.
The Intellec system is a flexible high
performance development system which can
support Intel's various microcomputer families with various optional modules. The
1-15
The Single Component
MCS-4S™ S~stem
.
2"
THE SINGLE COMPONENT MCS-48™ SYSTEM
2.0 Summary
Arithmetic Logic Unit
Sections 2.1 through 2.4 describe in detail
the functional characteristics of the 8748
EPROM, 8048/8049 ROM and 8035/8039
single component microcomputers. Unless
otherwise noted, details within these sections apply to all .versions. Sections 2.5
through 2.11 describe the operation of the
8021, while Sections 2.12 through 2.21 describe the 8022. This chapter is limited to
those functions useful in single-chip implementations of the MCS-48. Chapter 3 discusses functions which allow expansion of
program memory, data memory, and inputoutput capability.
The ALU accepts 8-bit data words from one
or two sources and generates an 8-bit result
under control of the Instruction Decoder.
The ALU can perform the following functions:
Add With or Without Carry
AND, OR, Exclusive OR
I ncrementiDecrement
Bit Complement
Rotate Left, Right
Swap Nibbles
BCD Decimal Adjust
2.1 Architecture
If the operation performed by the ALU results
in a value represented by more than 8 bits
(overflow of most significant bit) a Carry Flag
is set in the Program Status Word.
The following sections break the 8048 into
functional blocks and describe each in detail.
2.1.1 Arithmetic Section
The arithmetic section of the processor contains the basic data manipulation functions of
the 8048 and can be divided into the following
blocks:
Arithmetic Logic Unit (ALU)
Accumulator
Carry Flag
Instruction Decoder
Accumulator
The accumulator is the single most important data register in the processor, being
one of the sources of input to the ALU and
often the destination of the result of operations performed in the ALU. Data to and
from 1/0 ports and memory also normally
passes through the accumulator.
In a typical operation data stored in the
accumulator is combined in the ALU with data
from another source on the internal bus (such
as a register or I/O port) and the result is
stored in the accumulator or another register.
The following is a more detailed description of
the function of each block:
2.1.2 Program Memory
Resident program memory consists of 1024
or 2048 words eight bits wide which are
addressed by the program counter. In the
8748 this memory is user programmable
and erasable EPROM; in the 8048/8049 the
memory is ROM which is mask programmable at the factory. The 8035/8039 has no
internal program memory and is used with
external devices. Program code is completely interchangeable among the various
versions. See Section 2.3 for EPROM programming techniques.
Instruction Decoder
The operation code (op code) portion of each
program instruction is stored in the Instruction
Decoder and converted to outputs which
control the function of each of the blocks of
the Arithmetic Section. These lines control
the source of data and the destination register
as well as the function performed in the ALU.
2-1
Q)
o
~
Q)
......
Q)
o
~
CO
OJ
RESIDENT
EPROM/ROM
r-
1K x8
(2K x 8''''
o
o
c
");
C)
:D
»
s::
~
Z
C)
r---
V
'\/
V
A
A
V
(B)
V
PORTl
~BUS
V
7,
A
BUFFER
AND
LATCH
I\)
'"
MUL TIPlEXERI
REGISTER
REGISTER
REGISTER
REGISTER
TEST 0
REGISTER
REGISTER
TEST 1
1
FLAG
Vee
.........- PROGRAM SUPPLY
POWER
SUPPLY
a
FLAG 1
Voo
--:--- +5V {LOW POWER STANDBYI
REGISTER
REGISTER
INT
8 lEVEL STACK
(VARIABLE LENGTH)
OPTIONAL SECOND
REGISTER BANK
TIMER FLAG
CARRY
DATA STORE
~GND
ACC
ACCSIT TEST
XTALl
XTAL2
RESIDENT
RAM ARRAY
64x 8
OSCILLATOR
XTAL
ADDRESS
LATCH
STROBE
CYCLE
CLOCK
PROGRAM
MEMORY
ENABLE
SINGLE READ WRITE
STEP
STROBES
(128 x 8)-<-
*8049 only
r-
m
o
o
s::
"0
o
Z
m
Z
-I
tn
-<
tn
-I
m
s::
SINGLE COMPONENT SYSTEM
-0
There are three locations in Program Memory
of special importance:
LOCATION 0
Activating the Reset line of the processor
causes the first instruction to be fetched
from location O.
2048~
,
SELMai
2047~ TSELMBO
LOCATION 3
Activating the Interrupt input line of the
processor (if interrupt is enabled) causes a
jump to subroutine at location 3.
LOCATION 7
A timer/counter interrupt resulting from
timer/counter overflow (if enabled) causes
a jump to subroutine at location 7.
1024
1023
--""""""
..
Therefore, the first instruction to be executed
after initialization is stored in location 0, the
first word of an external interrupt service
subroutine is stored in location 3, and the first
word of a timer/counter service routine is
stored in location 7. Program memory can be
used to store constants as well as program
instructions. Instructions such as MOVP and
MOVP3 allow easy access to data "lookup"
tables.
LDCATION 7 - TIMER
r-- INTERRUPT
VECTORS
PROGRAM HERE
.. r--o
716151413121110
LOCATION 3 - EXTERNAL
INTERRUPT VECTORS
PROGRAM HERE
RESET VECTORS
I-- PROGRAM
HERE
ADDRESS
MCS-48™ PROGRAM MEMORY MAP
Data Memory
Resident data memory is organized as 64 or
128 words 8-bits wide. All locations are
indirectly addressable through either of
two RAM Pointer Registers which reside at
address 0 and 1 of the register array. In
addition, the first 8 locations (0-7) of the
array are designated as working registers
and are directly addressable by several
instructions. Since these registers are more
easily addressed, they are usually used to
store frequently accessed intermediate
results. The DJNZ instruction makes very
efficient use of the working registers as program loop counters by allowing the
programmer to decrement and test the
register in a single instruction.
63
(128 )
USER RAM
3h8
(96.8)
32
31
I
BANK I
WORKING
REGISTERS
ax8
2.
-
-
-
-RT' -ROo -
-
-
-
23
DIRECTLY
ADDRESSABLE
WHEN BANK 1
IS SELECTED
-.J
B LEVEL STACK
OR
USER RAM
ADDRESSED
INDIRECTLY
THROUGH
Rl OR RO
(RO' OR Rl')
16 x 8
BANKO
WORKING
REGISTERS
ax8
r-------------~- ----
By executing a Register Bank Switch instruction (SEL RB) RAM locations 24-31 are
designated as the working registers in place
of locations 0-7 and are then directly addressable. This second bank of working registers
may be used as an extension of the first bank
or reserved for use during interrupt service
I
DIRECTLY
ADDRESSABLE
WHEN BANK 0
IS SELECTED
IN ADDITION RO OR Rl (RO' OR Rl') MAY
BE USED TO ADDRESS 268 WORDS OF
EXTERNAL RAM.
(
DATA MEMORY MAP
2-3
)8049 only
SINGLE COMPONENT SYSTEM
subroutines allowing the registers of Bank 0
used in the main program to be instantly
"saved" by a Bank Switch. Note that if this
second bank is not used. locations 24-31 are
still addressable as general purpose RAM.
Since the two RAM pOinter Registers RO and
R1 are a part of the working register array.
bank switching effectively creates two more
pointer registers (RO' and R1') which can be
used with RO and R1 to easily access up to
four separate working areas in Ram at one
time. RAM locations (8-23) also serve a dual
role in that they contain the program counter
stack as explained in Sec. 2.1.6. These locations are addressed by the Stack Pointer
during subroutine calls as well as by RAM
Pointer Registers RO and R1. If the level of
subroutine nesting is less than 8, all stack
registers are not required and can be used as
general purpose RAM locations. Each level of
subroutine nesting not used provides the user
with two additional RAM locations.
ports and 3 "test" inputs which can. alter
program sequences when tested by conditional
jump instructions.
Ports 1 and 2
Ports 1 and 2 are each 8 bits wide and have
identical characteristics. Data written to these
ports is statically latched and remains unchanged until rewritten. As input ports these
lines are non latching, i.e., inputs must be
present until read by an input instruction.
Inputs are fully TTL compatible and outputs
will drive one standard TTL load.
The lines of ports 1 and 2 are called quasibidirectional because of a special output
circuit structure which allows each line to
serve as an input, an output, or both even
though outputs are statically latched. The
figure shows the circuit configuration in detail.
Each line is continuously pulled up to +5v
through a resistive device of relatively high
impedance (-50KO). This pullup is sufficient
to provide the source current for a TTL high
level yet can be pulled low by a standard TTL
gate thus allowing the same pin to be used for
both input and output. To provide fast switching
times in a "0" to "1" transition a relatively low
2.1.4 Input/Output
The 8048 has 27 lines which can be used for
input or output functions. These lines are
grouped as 3 ports of 8 lines each which
serve as either inputs, outputs or bidirectional
ORL. ANL
+5V
+5V
01---41-1
INTERNAL
BUS
-+---1D
"'5DK
I/O
PIN
PORT 1
AND2
D
FLIP
FLOP
eLK a
WRITE_t-_ _....._ _----'
PULSE
IN
"QUASI BI DIRECTIONAL" PORT STRUCTURE
2·4
SINGLE COMPONENT SYSTEM
impedance device (- 5KO) is switched in
momentarily (- 500ns) whenever a "1" is
written to the line. When a "0" is written to the
line a low impedance (-3000) device overcomes the light pullup and provides TTL
current sinking capability. Since the pulldown
transistor is a low impedance device a "1"
must first be written to any line which is to be
used as an input. Reset initializes all lines to
the high impedance "1" state. This structure
allows input and output on the same pin and
also allows a mix of input lines and output
lines on the same port. The quasi-bidirectional
port in combination with the ANL and ORL
logical instructions provide an efficient means
for handling single line inputs and outputs
within an 8-bit processor. See also Section
3.7.
Bus
to cause program branches without the necessity to load an input port into the accumulator.
The TO, T1, and INTpins have other possible
functions as well. See the pin description in
Sec. 2.2.
2.1.6 Program Counter and Stack
The Program Counter is an independent
counter while the Program Counter Stack is
implemented using pairs of registers in the
Data Memory Array. Only 10 (or 11) bits of
the Program Counter are used to address
the 1024 (2048) words of on-board program
memory while the most significant bits are
used for external Program Memory fetches.
The Program Counter is initialized to zero
by activating the Reset line.
An interrupt or CALL to a subroutine causes
the contents of the program counter to be
stored in one of the 8 register pairs of the
Program Counter Stack. The pair to be used
is determined by a 3-bit Stack Pointer which
is part of the Program Status Word (PSW).
Data RAM locations 8 thru 23 are available as
stack registers and are used to store the
Program Counter and 4 bits of PSW as
shown in the figure. The Stack Pointer when
initialized to 000 points to RAM locations
8 and 9. The first subroutine jump or interrupt
results in the program counter contents being
transferred to locations 8 and 9 of the RAM
array. The stack pointer is then incremented
by one to pOint to locations 10 and 11 in
anticipation of another CALL. Nesting of subroutines within subroutines can continue up to
8 times without overflowing the stack. If
overflow does occur the deepest address
stored (location 8 and 9) will be overwritten
and lost since the stack pointer overflows
from 111 to 000. It also underflows from 000
to 111.
,.
Bus is also an 8-bit port ~hich is a true bidirectional port with associated input and
output strobes. If the bidirectional feature is
not needed, Bus can serve
either a statically
latched output port or non-latching input port.
Input and output lines on this port cannot be
mixed however.
as
As a static port, data is written and latched
using the OUTL instruction and inputted using
the INS instruction. The INS and OUTL instructions generate pulses on the corresponding
RD and WR output strobe lines; however, in
the static port mode they are generally not
used. As a bidirectional port the MOVX instructions are used to read and write the port. A
write to the port generates a pulse on the WR
output line and output data is valid at the
trailing edge of WR. A read of the port
generates a pulse on the RD output line and
input data must be valid at the trailing edge of
RD. When not being written or read, the BUS
lines are in a high impedance state. See also
Sections 3.6 and 3.7.
The end of a subroutine, which is Signalled by
a return instruction (RET or RETR). causes
the Stack Pointer to be decremented and the
contents of the resulting register pair to be
transferred to the Program Counter.
2.1.5 Test and INT Inputs
Three pins serve as inputs and are testable
with the conditional jump instruction. These
are TO, T1, and INT. These pins allow inputs
2-5
SINGLE COMPONENT SYSTEM
I I I I I I
A"
A,O
Ag
As
A7
A61 A51 A41 Aal A21 A,
,
2.1.7 Program Status Word
I I
An 8-bit status word which can be loaded to
and from the accumulator exists called the
Program Status Word (PSW). The accompanying figure shows the information available
in the word. The Program Status Word is
actually a collection of flip-flops throughout
the machine which can be read or written as a
whole. The ability to write to PSW allows for
easy restoration of machine status after a
power down sequence.
AO
i
!
Conventional Program Counter
• Counts OOOH to 7FFH
• Overflows 7FFH to OOOH
PROGRAM COUNTER
I
CY
SAVED IN STACK
STACK POINTER
I
I
I I I I
AC
FO
BS
The upper four bits of PSW are stored in the
Program Counter Stack with every call to
subroutine or interrupt vector and are optionally
restored upon return with the RETR instruction.
The RET return instruction does not update
PSw.
1
MSB
LSB
CY
AC
CARRY
AUXILLARY CARRY
FO
FLAG 0
BS
REGISTER BANK SELECT
The PSW bit definitions are as follows:
Stack Pointer bits (So,
Bit 3:
Not used ("1" level when
read)
Bit 4:
Working Register Bank Switch
Bit (BS)
a = Bank a
1 = Bank 1
Bit 5:
Flag a bit (Fa) user controlled
flag which can be complemented or cleared, and tested
with the conditional jump instruction JFa.
Bit 6:
Auxiliary Carry (AC) carry bit
generated by an ADD instruction and used by the decimal
adjust instruction DA A.
Carry (CY) carry flag which
indicates that the previous
operation has resulted in overflow of the accumulator.
PROGRAM STATUS WORD (PSW)
·
POINTER
111
R23
··
110
22
21
20
···
·•
101
100
19
18
17
·•
16
15
I
011
·
010
Bit 7:
14
13
12
:•
001
PSW
PC4-7
000
MSB
S2)
11
2.1.8 Conditional Branch Logic
10
The conditional branch logic within the processor enables several conditions internal
and external to the processor to be tested by
the users program. By using the conditional
jump instruction the following conditions can
effect a change in the sequence of the
program execution.
9
pc s _"
PCo;J
s"
Bits a - 2:
R8
LSB
PROGRAM COUNTER STACK
2-6
SINGLE COMPONENT SYSTEM
2.1.9 Interrupt
An interrupt sequence is initiated by applying
a low "0" level input to the INT pin. Interrupt is
level triggered and active low to allow "WIRE
DRing" of several interrupt sources at the
input pin. The Interrupt line is sampled every
machine cycle during ALE and when detected
causes a "jump to subroutine" at location 3 in
program memory as soon as all cycles of the
current instruction are complete. INT must
be held low for at least T Cy to ensure proper
Jump Conditions
(Jump On)
Device Testable
Accumulator
Accumulator Bit
Carry Flag
User Flags (FO, F1)
Timer Overflow Flag
Test Inputs (TO, T1)
.Interrupt Input (INT)
not all
zeros
1
1
1
1
1
All zeros
°
°°
CONDITIONAL
JUMP LOGIC
TIMER
FLAG
JTF
EX ECUTEO--.:r--.
RESET
INTERRUPT
CALL
EXECUTED
>--+--1 R
CLR
r-------I
S
TIMER INT ___
RECOGNIZED
EXECUTED
D
EXTERNAL
INTERRUPT
RECOGNIZED
Q
TIMER
INTERRUPT
RECOGNIZED
Q
TIMER
OVERFLOW
FF
....- .
Q
R
S
INTERRUPT
IN
PROGRESS
FF
Q
R
TIMER
INT
ENABLE
Q
R
mT~
PIN
_ _ _ _ _ _~ 0
RESET
INT
FF
RETR
EXECUTED
Q
CLK
ALE---I-'"
} -_ _ _ _....l
LAST CYCLE
OF INST.
EN I
S
EXECUTED
NOTE:
1. INT INPUT IS SAMPLED BY ALE EVERY MACHINE CYCLE
EXCEPT FIRST CYCLE OF DOUBLE CYCLE INSTRUCTION.
2. WHEN INTERRUPT IN PROGRESSf/f ISSET ALL FURTHER
INTERRUPTS ARE LOCKED OUT INDEPENDENT OF STATE
OF EITHER INTERRUPT ENABLE f/f.
3. WHILE TIMER INTERRUPTS ARE DISABLED TIMER OVERFLOW
f/f WILL NOT STORE ANY OVERFLOW THAT OCCURS. TIMER
FLAG WILL BE SET, HOWEVER.
Q
INT
ENABLE
DISI
EXECUTED
RESET---:&..._
R
INTERRUPT LOGIC
2-7
."
't
t
SINGLE COMPONENT SYSTEM
interrupt operations. As in any CALL to subroutine, the Program Counter and Program
Status word are saved in the stack. For a
description of this operation see the previous
section, Program Counter and Stack. Program Memory location 3 usually contains an
unconditional jump to an interrupt service
subroutine elsewhere in program memory.
The end of an interrupt service subroutine is
signalled by the execution of a Return and
Restore Status instruction RETR. The interrupt system is single level in that once an interrupt is detected all further interrupt requests
are ignored until execution of an RETR reenables the interrupt input logic. This occurs
at the beginning of the second cycle of the
RETR instruction. This sequence holds true
also for an internal interrupt generated by
timer overflow. If an internal timer/counter
generated interrupt and an external interrupt
are detected at the same time, the external
source will be nicognized. See the following
Timer/Counter section for a description of
timer interrupt. If heeded, a second external
interrupt can b,e cr~ated by enabling the
timer/counter i'1terrupt, loading FFH in the
Counter (one less than terminal count), and
enabling the event counter mode. A "1" to "0"
transition on the T1 input will then cause an
interrupt vector to location 7.
also be tested using the conditional jump
instruction JNI. This instruction may be used
to detect the presence of a pending interrupt
before interrupts are enabled. If interrupt is
left disabled, iNT may be used as another test
input like TO and T1.
2.1.10 Timer/Counter
The 8048 contains a counter to aid the user In
counting external events and generating accurate time delays without placing a burden
on the processor for these functions. In both
modes the counter operation is the same, the
only difference being the source of the input
to the counter.
Counter
The 8-bit up binary counter is presettable and
readable with two MOV instructions which
transfer the contents of the accumulator to the
cou nter and vice versa. The cou nter content is
not affected by Reset and is initialized solely
by the MOV T,A instruction. The counter is
stopped by a Reset or STOP TCNT instruction
and rer;nains stopped until started as a timer
by a START T instruction or as an event
counter' by a START CNT instruction. Once
started the counter will increment to its maximum count (FF) and overflow to zero continuing its count until stopped by a STOP TCNT
instruction or Reset.
Interrupt Timing
The increment from maximum count to zero
(overflow) results in the setting of an overflow
flag flip-flop and in the .generation of an
interrupt request. The state of the overflow
flag is testable with the conditional jump
instruction JTF. The flag is reset by executing
a JTF or by Reset. The interrupt request is
stored in a latch and then ORed with the
external interrupt input iNT. The timer interrupt
may be enabled or di$at:>ledindependently of
external interrupt by the EN TCNTI and DIS
TCNTI instructions. If enabled, the counter
overflow will cause a subroutine call to location
7 where the timer or counter service routine
may be stored. If timer and external interrupts
occur simultaneously, the external source will
be recognized and the Call will be to location
3. Since the timer interrupt is latched it will
remain pending until the external device. is
The interrupt input may be enabled or disabled
under Program Control using the EN I and
DIS I instructions. Interrupts are disabled by
Reset and remain so until enabled by the
users program. An.interrupt request must be
removed before the RETR instruction is executed upon return from the service routine
otherwise the processor will re-enter the service routine immediately. Many peripheral
devices prevent this situation by resetting
their interrupt request line whenever the processor accesses (Reads or Writes) the peripherals data buffer register. If the interrupting
device does not require access by the processor, one output line of the 8048 may be
designated as an "interrupt acknowledge"
which is activated by the service subroutine to
reset the interrupt request. The INT pin may
2·8
SINGLE COMPONENT SYSTEM
PRESCALER
XTAL-c 15
LOAD OR READ
CLEARED ON START TIMER
1
.....- - - - . . . , START
COUNTER
EDGE
DETECTOR
JUMP ON
TIMER FLAG
8 BIT TIMER/
EVENT COUNTER
o
NOT CLEARED ON RESET
STOP T
ENABLE ----a_~
INT
TIMER/EVENT COUNTER
serviced and immediately be recognized upon
return from the service routine. The
pending timer interrupt is reset by the Call
to location 7 or may be removed by
executing a DIS TCNTI instruction.
msec may be achieved by accumulating mUltiple overflows in a register under software
control. For time resolution less than 80 /-tsec
an external clock can be applied to the T1
input and the counter operated in the event
counter mode. ALE divided by 3 or more can
serve as this external clock. Very small delays
or "fine tuning" of larger delays can be easily
accomplished by software delay loops.
As an Event Counter
Execution of a START CNT instruction connects the T1 input pin to the counter input and
enables the counter. Subsequent high to low
transitions on T1 will cause the counter to
increment. The maximum rate at which the
counter may be incremented is once per
three instruction cycles (every 7.5/-tsec when
using a 6MHz crystal)-there is no minimum
frequency. T1 input must remain high for at
least 500ns (at 6MHz) after each transition.
2.1.11 Clock and Timing Circuits
liming generation for the 8048 is completely
self-contained with the exception of a frequency reference which can be XTAL,
inductor, or external clock source. The
Clock and Timing circuitry can be divided
into the following functional blocks:
As a Timer
Oscillator
Execution of a START T instruction connects
an internal clock to the counter input and
enables the counter. The internal clock is
derived by passing the basic 400 KHz machine
cycle clock ALE through a -7- 32 prescaler.
The prescaler is reset during the START T
instruction. The resulting 12.5 KHz clock
increments the counter every 80 /-tsec
(assuming 6 MHz XTAL). Various delays
between 80 /-tsec and 20 msec (256 counts)
can be obtained by presetting the counter and
detecting overflow. limes longer than 20
The on-board oscillator is a high gain parallel
resonant circuit with a frequency range of 1 to
6MHz. The X1 external pin is the input to the
amplifier stage while X2 is the output. A
crystal or inductor connected between X1
and X2 provides the feedback and phase
shift required for oscillation. A 5.9904 MHz
crystal provides for easy derivation of all
standard communications frequencies. If an
accurate frequency reference and maximum
processor speed are not required, an induc2-9
SINGLE COMPONENT SYSTEM
Cycle Counter
tor may be used in place of the crystal. With
an inductor the oscillator frequency can be
approximately 3 to 5 MHz. For higher speed
operation a crystal should be used. An
externally generated clock may also be
applied to X1-X2 as the frequency source.
See the data sheet for more information.
ClK is then divided by 5 in the Cycle Counter
to provide a clock which defines a machine
cycle conSisting of 5 machine states. This
clock is called Address latch Enable (ALE)
because of its function in MCS-48 systems
with external memory. It is provided continuously on the ALE output pin.
State Counter
2.1.12 Reset
The output of the oscillator is divided by 3 in
the State Counter to create a clock which
defines the state times of the machine (ClK).
ClK can be made available on the external
pin TO by executing an ENTO ClK instruction.
The output of ClK on TO is disabled by Reset
of the processor.
The reset input provides a means for initialization for the processor. This Schmitt-trigger
input has an internal pullup resistor which in
combination with an external 1 ~fd capacitor
provides an internal reset pulse of sufficient
length to guarantee all circuitry is reset. If the
DIAGRAM OF 8048 CLOCK UTILITIES
INSTRUCTION CYCLE
.
1
S2
INPUT
INST.
DECODE
OUTPUT ADDRESS
INC. PC
I
I
.
2.5 .usee CYCLE
SI
S5
53
1
54
1
52
sa
54
55
51
I
CLOCK OUT
ON TO
ALE
--"f---+--+-'
~~f--~--+--~--~-,
~
~~----.,----~
PROG
2-10
53
INPUT
OUTPUT ADDRE55
i
52
SI
EXECUTION
I
MCS-48™ CYCLE TIMING
51
S5
54
55
~
CYCLE 1
INSTRUCTION
54
S5
S1
S2
READ PORT
FETCH
IMMEDIATE DATA
--
·
·
·
READ PORT
FETCH
IMMEDIATE DATA
--
·
INA,P
INCREMENT
PROGRAM COUNTER
·
--
INCREMENT
TIMER
QUTL P,A
FETCH
INSTRUCTION
INCREMENT
PROGRAM COUNTER
--
INCREMENT
TIMER
FETCH
INSTRUCTION
INCREMENT
PROGRAM COUNTER
--
INCREMENT
TIMER
FETCH
INCREMENT
PROGRAM COUNTER
--
INCREMENT
TIMER
INSTRUCTION
INCREMENT
PROGRAM COUNTER
--
INCREMENT
TIMER
--
--
READ PORT
OUTLBUS.A
FETCH
INSTRUCTION
INCREMENT
PROGRAM COUNTER
--
INCREMENT
TIMER
OUTPUT
TOPQRT
--
--
ANL BUS, :rDATA
FETCH
INSTRUCTION
--
INCREMENT
TIMER
READ PORT
FETCH
IMMEDIATE DATA
--
ORL BUS, 4JATA
FETCH
INSTRUCTION
·
·
INCREMENT
PROGRAM COUNTER
--
INCREMENT
TIMER
READ PORT
FETCH
IMMEDIATE DATA
--
MOVX@lR.A
FETCH
INSTRUCTION
INCREMENT
PROGRAM COUNTER
OUl'PUTRAM
ADDRESS
INCREMENT
TIMER
OUTPUT
DATA TO RAM
--
--
MOVXA,OR
FETCH
INSTRUCTION
INCREMENT
PROGRAM COUNTER
OUTPUT RAM
ADDRESS
INCREMENT
TIMER
--
--
READ DATA
MOVDA,Pi
FETCH
INSTRUCTION
INCREMENT
PROGRAM COUNTER
OUTPUT
OPCODE/ADDRESS
INCREMENT
TIMER
--
--
READ
P2 LOWER
MOVDPj,A
FETCH
INSTRUCTION
INCREMENT
PROGRAM COUNTER
OUTPUT
OPCODE/ADDRESS
INCREMENT
TIMER
OUTPUT DATA
TOP2LOWER
--
--
ANLDP,A
FETCH
INSTRUCTION
INCREMENT
PROGRAM COUNTER
OUTPUT
QPCODE/ADDRESS
INCREMENT
TIMER
OUTPUT
DATA
--
--
ORLD P,A
FETCH
INSTRUCTION
INCREMENT
PROGRAM COUNTER
OUTPUT
OPCODE/ADDRESS
INCREMENT
TIMER
OUTPUT
DATA
--
--
J ICONDITIONAL)
FETCH
INSTRUCTION
INCREMENT
PROGRAM COUNTER
SAMPLE
CONDITION
INCREMENT
TIMER
--
STRT T
STRT CNT
FETCH
INSTRUCTION
INCREMENT
PROGRAM COUNTER
--
START
COUNTER
STOP TCNT
FETCH
INSTRUCTION
STOP
COUNTER
EN.
·
·
--
FETCH
INSTRUCTION
QRL P, ::DATA
INS A. BUS
-
S3
FETCH
INSTRUCTION
ANLP.=OATA
'l'
52
S1
CYCLE 2
INSTRUCTION
FETCH
INCREMENT
PROGRAM COUNTER
--
INCREMENT
PROGRAM COUNTER
--
INCREMENT
PROGRAM COUNTER
DIS I
FETCH
INSTRUCTION
INCREMENT
PROGRAM COUNTER
ENTOCLK
FETCH
INSTRUCTION
·
-
INCREMENT
PROGRAM COUNTER
-----------
INSTRUCTION TIMING DIAGRAM
-OUTPUT
TO PORT
--
ENABLE
INTERRUPT
--
--
DISABLE
INTERRUPT
--
--
ENABLE
CLOCK
--
--
READ PORT
--
--
FETCH
IMMEDIATE DATA
--
53
54
55
--
--
--
--
--
INCREMENT
PROGRAM COUNTER
--
OUTPUT
TO PORT
--
INCREMENT
PROGRAM COUNTER
OIffi'UT
TO PORT
--
--
--
--
!!
--
--
--
Ci)
IHCREMENT
PROGRAM COUNTER
OUTPUT
TO PORT
--
INCREMENT
PROGRAM COUNTER
OllTl'UT
TO PORT
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
en
-<
en
--
--
--
3:
--
--
·
·
·
·
·
·
·
·
·
·
·
UPDATE
PROGRAM COUNTER
·VALID INSTRUCTION ADDRESSES ARE OUTPUT AT THIS TIME
IF EXTERNAL PROGRAM MEMORY IS BEING ACCESSED.
z
r-
m
n
o
3:
'111
o
Z
m
Z
-t
-t
m
SINGLE COMPONENT SYSTEM
reset pulse is generated externally the
RESET pin must be held at ground LSV) for
at least 10 milliseconds after the power
supply is within tolerance. Only S machine
cycles (12.SJls @ 6 MHz) are required if
power is already on and the oscillator has
stabilized.
Timing
The 8048 operates in a single-step mode as
follows:
1. The processor is requested to stop by
applying a low level on SS.
2. The processor responds by stopping
during the instruction fetch portion of the
next instruction. If a double cycle instruction is in progress when the single step command is received, both cycles will be completed before stopping.
EXTERNAL RESET
+5V
"=200
Ku
ACTIVE
PUlLUP
3. The processor acknowledges it has
entered the stopped state by raising ALE
high. In this state (which can be maintained
indefinitely) the address of the next instruction to be fetched is present on BUS and
the lower half of port 2.
POWE R ON RESET
+5V
--D..-
f
'K
""200
K!J
",
lOVI
4. SS is then raised high to bring the processor out of the stopped mode allowing it
to fetch the next instruction. The exit from
stop is indicated by the processor bringing
ALE low.
Reset performs the following functions:
1.
2.
3.
4.
S.
6.
7.
8.
9.
10.
11.
Sets program counter to zero.
Sets stack painter to zero.
Selects register bank O.
Selects memory bank O.
Sets BUS to high impedance state.
(except when EA = SV)
Sets Ports 1 and 2 to input mode.
Disables interrupts (timer and external)
Stops timer.
Clears timer flag.
Clears FO and F1.
Disables clock output from TO.
S. To stop the processor at the next instruction SS must be brought low again as soon
as ALE goes low. If SS is left high the processor remains in a "Run" mode.
A diagram for implementing the single step
function of the 8748 is shown. A D-type flipflop with preset and clear is used to generate
SS. In the run mode SS is held high by
keeping the flip-flop preset (preset has precedence over the clear input). To enter single
step, preset is removed allowing ALE to bring
SS low via the clear input. ALE should be
buffered since the clear input of an SN7474 is
the equivalent of 3 TTL loads. The processor
is now in the stopped state. The next instruction is initiated by clocking a "1" into the flipflop. This "1" will not appear on SS unless
ALE is high removing clear from the flip-flop.
In response to SS going high the processor
begins an instruction fetch which brings ALE
low resetting SS through the clear input and
causing the processor to again enter the
stopped state.
2.1.13 Single-Step
This feature provides the user with a debug
capability in that the processor can be stepped
through the program one instruction at a time.
While stopped, the address of the next instruction to be fetched is available concurrently on
BUS and the lower half of Port 2. The user
can therefore follow the program through
each of the instruction steps. A timing diagram,
showing the interaction between output ALE
and input SS is shown. The BUS buffer
contents are lost during single step; however, a latch may be added to re-establish
the lost I/O capability if needed. (See 2.4.1).
2·12
SINGLE COMPONENT SYSTEM
SINGLE STEP CIRCUIT
+6V
SINGLE
STEP
+BV
MOMENTARY
10K
PUSHBUTTON
10K
r,UN
+6V
'---:P=RE~SE=T- - ,
D
o
+BV
,------1> CLOCK
10K
DEBOUNCE
LATCH
'----<1-
ALE
1/27400
SINGLE STEP TIMING
,
I
ALE
S3
84
I
S5
I
S1
-.J
S2
S3
S4
S5
I
I
ss
<
BUS
P20·23
1/0
RUN
X
PCO·7
)
PC8·11
X
STOP
2.1.14 Power Down Mode
1/0
RUN
I
STOP
Vee serves as the 5V supply pin for the bulk
of 8048 circuitry while the Voo pin supplies
only the RAM array. Ih normal operation both
pins are at 5V while in standby Vee is at
ground and only Vob is maintained at 5V.
Applying Reset to the processor through
the RESET pin inhibits any access to the
RAM by the processor and guarantees that
RAM cannot be inadvertently altered as
power is removed from Vee.
(8048, 8049, 8039,8035L)
Extra circuitry has been added to the 8048
ROM version. to allow Rower to be removed
from aU but the 64/128 x 8 data RAM array
for low power standby operation. In the
power down mode the contents of data
RAM can be maintained while drawing
typically 10% to 15% of normal operating
power requirements.
2·13
SINGLE COMPONENT SYSTEM
effectively disable internal program memory by forcing all program memory fetches
to reference external memory. The following chapter explains how access to external
program memory is accomplished.
1"""
POWER SUPPLY
PROCESSOR
INTERRUPTED
1
I.
~I--
I
POWER SUPPlY---{
1
1
NORMAL
FAil SIGNAL
~ _ _ I____ POWERON
1
I
I
RESET
I
1
The External Access mode is very useful in
system test and debug because it allows the
user to disable his internal applications program and substitute an external program of
his choice-a diagnostic routine for instance.
In addition, the section on Test and Debug
explains how internal program memory can
be read externally, independent of the
processor.
SEQUENCE
FOllOWS
U ___ _
i
I
I
DATA SAVE
ROUTINE
EXECUTED
DATA RAM
ACCESS TO
INHIBITED
POWER DOWN SEQUENCE
A "1" level on EA initiates the external access
mode. For proper operation, Reset should be
applied while the EA input is changed.
A typical power down sequence occurs as
follows:
1. Imminent power supply failure is detected
by user defined circuitry. Signal must be
early enough to allow 8048 to save all necessary data before Vee falls below normal
operating limits.
2.2 Pin Description
The MCS-48 processors (except 8021) are
packaged in 40 pin Dual In-Line Packages
(DIP's). The following is a summary of the
functions of each pin. Where it exists, the
second paragraph describes each pin's
function in an expanded MCS-48 system.
Unless otherwise specified, each input is
TTL compatible and each output will drive
one standard TTL load.
2. Power fail signal is used to interrupt
processor and vector it to a power fail
service routine.
3. Power fail routine saves all important
data and machine status in the internal data
RAM array. Routine may also initiate transfer of backup supply to the Voo pin and
indicate to external circuitry that power fail
routine is complete.
4. Reset is applied to guarantee data will
not be altered as the power supply falls out
of limits. Reset must be held low until Vee
is at ground level.
XTAL{
8
PORT
#1.
RESET
SINGLE STEP
Recovery from the Power Down mode can
occur as any other power-on sequence with
an external capacitor on the Reset input
providing the necessary delay. See the previous section on Reset.
8
PORT
. #2
EXTERNAL
MEM.
READ
TEST {
WRITE
INTERRUPT
2.1.15 External Access Mode
BUS
Normally the first 1K (8048) or 2K (8049)
words of program memory are automatically fetched from internal ROM or EPROM.
The EA input pin however allows the userto
8
8048 LOGIC SYMBOL
2-14
PROGRAM
STORE ENABLE
ADDRESS
LATCH eNABLE
SINGLE COMPONENT SYSTEM
Pin*
Designation Number Function
Vss
20
Circuit GND potential
Voo
26
Programming power supply; + 25V during program,
+ 5V during operation for both ROM and PROM. low
power standby pin in 8048 ROM version
Vee
40
Main power supply; + 5V during operation and
8748 programming.
PROG
25
Program pulse (+23V) input pin during 8748
programming.
Output strobe for 8243 I/O expander.
P10-P17
(Port 1)
27-34
8-bit quasi-bidirectional port. (Internal Pullup "" 50KOJ
P20-P27
(Port 2)
21-24
35-38
8-bit quasi-bidirectional port. (Internal Pullup "" 50KOJ
P20-P23 contain the four high order program counter
bits during an external program memory fetch and serve
as a 4-bit I/O expander bus for 8243.
00-07
12-19
True bidirectional port which can be written or read synchronously using the RO, WR strobes. The port can also
be statically latched.
Contains the 8 low order program counter bits during an
external program memory fetch, and receives the addressed instruction under the control of PSEN. Also con"
tains the address and data during an external RAM data
store instruction, under control of ALE, RD, and WR.
TO
1
Input pin testable using the conditional transfer instructions JTO and JNTO. TO can be designated as a clock
output using ENTO ClK instruction. TO is also used during programming.
T1
39
Input pin testable using the JT1, and JNT1 instructions.
Can be designated the event counter input using the
STRT CNT instruction.
6
Interrupt input. Initiates an interrupt if interrupt is enabled.
Interrupt is disabled after a reset. (Active low)
8
Output strobe activated during a BUS read. Can be
used to enable data onto the BUS from an external
device. (Active low)
Used as a Read Strobe to External Data Memory.
(BUS)
*8048,8748,8049
2·15
SINGLE COMPONENT SYSTEM
Pin
Designation Number
Function
RESET
4
Input which is used to initialize the processor. Also used
during PROM programming and verification. (Active low)
(Internal pullup "'" 200KO)
WR
10
Output strobe during a BUS write. (Active low)
Used as write strobe to external data memory.
ALE
11
Address Latch Enable. This signal occurs once during
each cycle and is useful as a clock output.
The negative edge of ALE strobes address into external
data and program memory.
9
Program Store Enable. This output occurs only during a
fetch to external program memory. (Active Low)
5
Single step input can be used in conjunction with ALE
to "single step" the processor through each instruction.
(Internal pullup '" 300KOl
(Active Low)
EA
7
External Access input which forces all program memory
fetches to reference external memory. Useful for emulation and debug, and essential for testing and program
verification. (Active High)
(Internal pullup '" 10MO
on 8048/8049, 8035L, 8039 only)
XTAL1
2
One side of crystal input for internal oscillator. Also input
for external source.
XTAL2
3
Other side of crystal/external source input.
Unless otherwise stated inputs do not have internal pullup resistors.
2.3 Programming, Verifying and
Erasing EPROM
The internal Program Memory of the 8748
may be erased and reprogrammed by the user
as explained in the following sections. See
also the 8748 data sheet.
Pin
Function
XTAL 1
Clock Input (1 to 6MHz)
Reset
Initialization and Address
Latching
Test 0
Selection of Program (OV) or
Verify (5V) Mode
EA
Activation of Program/Verify
Modes
BUS
Address and Data Input
Data Output During Verify
P2D-1
Address Input
Voo
Programming Power Supply
PROG
Program Pulse Input
2.3.1 ProgramminglVerification
In brief, the programmin'g process consists
of: activating the program mode, applying an
address, latching the address, applying data,
and applying a programming pulse. Each
word is programmed completely before moving
on to the next and is followed .by a verification step. The following is a list of the pins
used for programming and a description of
their functions:
2-16
SINGLE COMPONENT SYSTEM
+5V
RESET
O------------~--~
- - - BUS AND PROG CAN BE DRIVEN ONLY DURING THIS T I M E - I
1--------
+5V---....,
TEST 0
o
+23V
EA
+5V _ _ _ _---I
BUS
PREVIOUS
ADDRESS
P20·21
(
ADDRESS AO-A7
X
ADDRESS A8-A9
X
DATA
>
<
DATA OUT
+25V
VDD
+5V-----------------------------------------I
+23V
PROG +OV -
I
FLOAT
- - , ' - -____________________________---1
'--__--i' - - -- - - FLOAT
SEE 8048/8748 DATA SHEET (CHAPTER 6) FOR DETAIL TIMING SPECIFICATIONS.
WARNING: An attempt to program a mis-socketed 8748 will result in severe damage to the part. An indication of a properly socketed part
is the appearance of the ALE clock output. The lack of this clock may be used to disable the programmer.
PROGRAMMINGIVERIFY. SEQUENCE
8748 Erasure Characteristics
When erased, bits of the 8748 Program
Memory are in the logic "0" state.
The erasure characteristics of the 8748 are
such that erasure begins to occur when
exposed to light with wavelengths sh<6rter
than approximately 4000 Angstroms (Al. It
should be noted that sunlight and certain
types of fluorescent lamRs have wavelengths in the 3000-4000A range. Data
show that constant exposure to room level
fluorescent lighting could erase the typical
8748 in approximately 3 years while it
would take approximately 1 week to cause
erasure when exposed to direct sunlight. If
the 8748 is to be exposed to these types of
lighting conditions for extended periods of
time, opaque labels are available from Intel
which should be placed over the 8748 window to prevent unintentional erasure.
The recommended erasure procedure for
the 8748 is exposure to shortwave ultraviolet light which has a wavelength of 2537
Angstroms tAl. The integrated dose (i.e., UV
intensity X exposure time) for erasure
should be a minimum of 15W-sec/cm2. The
erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet
lamp with a 12000jlW/cm 2 power rating.
The 8748 should be placed within one inch
from the lamp tubes during erasure. Some
lamps have a filter on their tubes and this
filter should be removed before erasure.
2-17
SINGLE COMPONENT SYSTEM
The ProgramlVerify sequence is:
P23
1. Voo = 5v, Clock applied or internal
oscillator operating, Reset = Ov Test 0 =
5v, EA = 5v, BUS and PROG floating
P22
P2l
P20
DB7
2. Insert 8748 in programming socket
3. Test 0
DB6
DB5
= Ov (Select Program Mode)
DB4
= 23V (Activate Program Mode)
DB3
5. Address applied to BUS and P20-1
DBl
4. EA
DB2
DBO
6. Reset = 5v (Latch Address)
7. Data applied to BUS
8. Voo = 25v (Programming Power)
ADDRESS OUTPUT DURING SINGLE STEP
9. PROG = Ov followed by one 50ms pulse
to 23V
This allows the user to step through his
program and note the sequence of instructions being executed.
10. Voo = 5v
11. TEST 0 = 5v (Verify Mode)
While the processor is stopped, the I/O
information on BUS and the 4-bits of port 2 is,
of course, not available. I/O information is,
however, valid at the leading edge of ALE and
can be latched externally using this signal if
necessary.
12. Read and Verify Data on BUS
13. TEST 0 = Ov
14. Reset
= Ov and
repeat from Step 5
15. Programmer should be at conditions of
Step 1 when 8748 is removed from socket.
2.4 Test and Debug
Several MCS-48 features described in the
previous sections are discussed here to
emphasize their use in testing MCS-48
components and in debugging MCS-48
based systems.
2.4.1 Single Step
Single step circuitry within the microcomputer in combination with the external
circuitry described in Section 2.1.13 allows
the user to execute one instruction at a time
whether the instruction is one or two cycles
in length. After completion of the instruction
the processor halts with the address of the
next instruction to be fetched available on the
eight lines of BUS and the lower 4-bits of port
2.
2.4.2 Disabling Internal Program Memory
Applying +5V to the EA (external access) pin
of the MCS-48 microcomputers allows the
user to effectively disable internal program
memory by forcing all instruction fetches to
occur from an external memory. This
external memory can be connected as
explained in the section on program memory
expansion and can contain a diagnostic
routine to exercise the processor, the internal
RAM, the timer, and the I/O lines. EA should
be switched only when the processor is in
RESET.
2.4.3 Reading Internal Prograin Memory
Just as the processor may be isolated from
internal program memory using EA, program
memory can be read independent of the
processor using the verification mode described in the previous section, Programming/
Verification.
2-18
SINGLE COMPONENT SYSTEM
The processor is placed in the READ mode
by applying a high voltage (+23V for the
8748, +12V for the 8048/8049) to the EA pin
and +5V to the TO (8748 only) input pin.
RESET must. be at OV when voltage is applied to EA. The address of the location to
be read is then applied to the same lines
(TTL levels) of BUS and Port 2 which output
the address during single step (see below).
The address is latched by a "0" to "1"
transition on RESET and a high level on
RESET causes the contents of the program
memory location addressed to appear on
the eight lines of BUS. RESET must be
brought back to OV before leaving the
READ mode.
P22
A1D (8049) only)
P21
A,
P20
Aa
I.
DB7
liD.
DB8
1/0,
DBS
110,
DB4
1100
6218
804B
B748
i5iE'N
DB3
I---- A7
I ' i - - Aa
I, i - - A s
10 I---- A4
D . r - D,
0, 1----00
0,1---- 0•
00 r - D,
-
a-
f ~
DB2
r- DATA OUT
OBI
O , r - D•
DBO
1/0,
O ' r - Do
0,1---- 0 ,
001---- 00
I . i - - A•
I , t - - - A,
1/00
I'I----A,
lot---Ao
1/0.
1/0,
8218
RESET
ALE
EA
I---
TO
l-
i5iEN Ci
t ~
I
Q
-[+23V 8748
+12V 8048
{+5V 8748
NC
8048
TO
8748 ONLY
I
1/2
7474 0
CK
J
L-
5V
RESET
I
+12V (+23V)
i
EA
5V
BUS
5V
P2[J.21
-
<
<
I
I
ADDRESS
><
ADDRESS
READING INTERNAL PROGRAM MEMORY
2-19
DATA
RESET'
SINGLE COMPONENT SYSTEM
8021 Functional. Specifications
The following is a functional description of
the major elements of the 8021.
return address generated. The SP to this
pushdown stack is incremented by one
after a return address is stored, and decremented by one before an address is fetched
during a RET. The unincremented program
counter address is stored in the address
stack. The stack contents is incremented
before being loaded into the program counter during a return from subroutine. A total
of 8 levels of nesting is possible. The SP is
initialized to location 8 upon RESET. Since
each address is 10-bits long, two bytes must
be used to store a single address. The SP is
incremented and decremented by one, but
each increment or decrement moves the
address pointed to by two. Therefore, only
even numbered addresses are pointed to.
2.5 Program Memory
The 8021 contains 1K x 8 of mask
programmable ROM. No external ROM
expansion capability is provided.
2.6 Data Memory
A 64 x 8 dynamic RAM is located on chip for
data storage. All locations are indirectly
addressable and eight designated locations
are directly addressable. Also, included in
the memory is the address stack, addressed
by a 3-bit stack pointer.
Memory is organized as shown in Figure 1.
The least significant 8 addresses, 0-7, are
directly addressable by any of the 11 direct
register instructions. The locations are
readily accessible for a variety of operations with the least number of instruction
bytes required for their manipulation.
Registers 0 and 1 have another function, in
that they can be used to indirectly address
all locations in memory, using the indirect
register instructions. These indirect RAM
address registers, IRAR's, are especially
useful for repetitive-type operations on
adjacent memory locations. The indirect
register instruction specifies which IRAR to
use, and the contents of the I RAR is used to
address a location in RAM. The contents of
the addressed location is used during the
execution of the instruction and may be
modified. A value larger than 63should not
be preset in the IRAR when selected by an
indirect register instruction. IRAR's may
point to address 0-7, if desired.
If a particular application does not require 8
levels of nesting, the unused portion of the
stack may be used as any other indirectly
addressable scratch pad location. For example, if only 3 levels of subroutine nesting
are used, then only locations 8-13 need be
reserved for the address stack, and locations 14-63 can be used for data storage.
LOC 24·63
INDIRECTLY
ADDRESSABLE
BY
IRARO OR 1
LOC 8-23
7
6
5
4
3
2
Locations 8-23 may be used as the address
stack. The address stack enables the processor to keep track ofthe return addresses
generated from CALL instructions. A 3-bit
stack pointer (SP) supplies the address of
the locations to be loaded with the next
IRAR 1
IRAR 0
CAN BE USED
} FOR ADDRESS
STACK
I
DIRECTLY
ADDRESSABLE
FIGURE 1. INTERNAL RAM ORGANIZATION
2-20
SINGLE COMPONENT SYSTEM
The 8021 utilizes dynamic RAM and certain
other dynamic logic. Due to the clocking
required with dynamic circuits, the oscillator frequency must be equal to or greater
than 600K Hz, or improper operation may
occur.
2.7 Oscillator and Clock
The 8021 contains its own onboard oscillator and clock circuit, requiring only an
external timing control element. This control element can be a crystal, inductor, or
clock in. The capacitor normally required in
inductor timing control operation is integrated onto the 8021. All internal time slots
are derived from the external element, and
all outputs are a function of the oscillator
frequency. Pins XT AL 1 and XTAL2 are used
to input the particular control element. An
instruction cycle consists of 10 states, and
each state is a time slot of 3 oscillator
periods. (See Figure 2) Therefore, to obtain
a 10 Msec instruction cycle, a 3M Hz crystal
should be used. An oscillator frequency of
approximately 3MHz may also be obtained
by connecting a 470 MH inductor between
XTAL 1 and XTAL2. Note that the required
inductance may vary and should be adjusted as necessary.
CYCLE
TIMES
ALE
r-----I
1
I
2
I
3
I
4
I
5
The 8021 has internal timer/event counter
circuits that can monitor elapsed time or
count external events that occur during
program execution. The circuit has an 8-bit
binary up-counter that is presettable and
readable with two MOV instructions. These
instructions transfer the contents of the
accumulator to the counter and vice-versa.
The counter content is not affected by
Reset, and is initialized solely by the MOV
r,A instruction. The counter is stopped by a
RESET or STOP TCNT instruction and
remains stopped until started as a timer by a
STRT T instruction or as an event counter
by a STRT CNT instruction. Once started,
C1 •
I
n
------~
2.8 Timer/Event Counter
6
I
7
I
8
I
9
I
10
'I'I
C2
5
1
I
1
6
n
~------------~
DATA
IN
X'-___
PO,P1,P2_ _ _ _ _ _ _- - J
I
7
I
8
I
9
I 10
~------
>C
DA_T_AO_U_T_ _ _ _ _ _ _ _ _ _ _ _ __
All PORTS FOR IN AND OUTl INSTRUCTIONS
FIGURE 2. 8021 TIMING DIAGRAM
2·21
I
SINGLE COMPONENT SYSTEM
the . counter increments to its maximum
count (FF), and overflows to zero. The count
continues until stopped by a STOP TCNT
instruction or RESET. The increment from
maxini"um . count to zero (overflow) sets an
overflow flag. The state of the overflow flag
is testable with the conditional jump instruction JTF. The flag is reset byJTF but
not by executing a RESET, unlike the 8748.
Bya MOV T,A instruction, the contents of
the accumulator are loaded to the timer. At
the STRT T command an internal prescaler
is zeroed and thereafter increments once
each 30 input clocks (once each single
cycle instruction, twice each double cycle
instruction>. The prescaler is a divide by 32.
At the (11111) to (00000> transition the timer
is incremented. The timer is 8-bits and an
overflow (FFH) to (OOH) timer flag is set. A
conditional branch instruction (JTF) is
available for testing this flag, the flag being
reset each test. Total count capacity forthe
timer is 28 x 25 = 8192 or 81.9 msec at a 10
Msec cycle time. Contents of the. timer are
moved to the accumulator by the MOV A,T
instruction without disturbing the counting
process. The timer stops upon the STOP
TCNT instruction.
matic of the quasi-bidirectional interface is shown in Figure 3. This configuration allows buffered output~, and
also allows external input. Data written to
these ports is statically latched and remains
unchanged until rewritten. As input ports
these lines are non-latching, i.e., inputs
must be present until read by an input
instruction. When writing a "0" or low value
to these ports, the large pulldown device
sinks an external TTL load. When writing a
"1", a large current is supplied through the
large pullup device to allow a fast data
transfer. After a short time (less than one
instruction cycle), the large device is shut
off and the small pullup maintains the "1"
level indefinitely. However, in this situation,
an input device capable of overriding the
small amount of sustaining current supplied by the pullup device can be read,
(Alternatively, the data written ca"n be read>'
So, by writing a "1" to any particular pin,
that pin can serve either as a true high:-Ievel
latched output pin, or as just a pullup
resistor on an input. This allows maximum
user flexibility in selecting his input or
latched output pins, with a minimum of
external components.
The STRT CNT instruction connects the T1
input pin to the event counter input and
enables the counter. Subsequent high-tolow transitions on T1 increment the
counter. The maximum rate at which the
counter can increment is once per three
instruction cycles (30MS for a 3 MHz
oscillator>. There is no minimum frequency.
T1 input must remain high for at least 500ns
after each transition. The event counter is
stopped by a STOP TCNT instruction.
Port 00-07 is also quasi-bidirectional,
except there is no large pullup device. As
outputs, this port is essentially open drain.
By mask option the small pullup devices on
POO-P07 may be deleted on any pin
providing a true open drain output. This is
useful in driving analog circuits and certain
loads, such as keyboards.
2.9 Input/Output Capabilities
The 8021 I/O configurations are highly
flexible. A number of different configurations are possible, tailoring an 8021 to a
given task. Other than the power supply
and dedicated pins, all other pins (20) can
be used for input, output, or both,
depending on the configuration.
All ports are quasi-bidirectional to facilitate stand-alone use. A simplified sche-
INPUT BUFFER
FIGURE 3. QUASI-BIDIRECTIONAL
PORT STRUCTURE
2-22
SINGLE COMPONENT SYSTEM
2.9.1 T1 Input
minimizing external parts required to do
high power control. P10 and P11 have been
designated high drive outputs capable of
sinking 7mA at Vss + 2.5 volts. (For clarity,
this is 7mA to Vss with a 2.5 volt drop across
the buffer.) These pins may, of course, be
paralleled for 14mA drive if the output logic
states are always the same.
The 8021 T1 input line can be used as an
input for the following functions:
• Event Counter (external input)
• Test input for branch instructions
• Zero voltage crossing detection
The operation of T1 as an input to the Event
Counter is described in the Timer/Event
Counter section. When used as a test input,
the JT1 and JNT1 instructions test for 1 and
o levels, respectively.
The T1 pin can also be used to detect the
zero crossing of slowly moving AC signals
(60 Hz)' The self-biasing circuit shown in
Figure 4 permits the Test 1 input to detect
when the input voltage crosses zero within
±5%; the voltage is then coupled through
a 1.01-lf capacitor. Maximum input voltage is
3V peak-to-peak. The zero cross detection
is especially useful in SCR control of 60 Hz
power and in developing time-of~day and
other timing routines. As a ROM mask
option there is a pullup resistor that is
useful for switch contact input or standard
TTL.
2.9.3 Expanded I/O
The 8021 can be used with the 8243 I/O
expander chip, which provides additional
I/O capability with a limited number of
overhead pins. This chip has 4 directly
addressable 4-bit ports. It connects to the
PROG pin, which provides a clock, and pins
P20-P23, which provide address and data.
These ports can be written with a MOVD
P,A; ANLD P,A; and ORlD P,A forPorts4-7.
A high to low transition on PROG signifies
that address and control are available on
P20-P23. The previous data on P20-P23
before an output expander instruction is
lost. Therefore, when using an output
expander P20-P23 are not useful for
general input/output. Reading is via the
MOVD A,P. This circuit configuration is
shown in Figure 5. The timing diagram is
shown in Figure 6.
2.9.2 High Current Outputs
hig~ current drive is desirable for
Very
(0)
The 8021 can also use standard low cost
TTL to expand the number of I/O lines. An
example is shown in the Applications
section.
ZERO CROSS OETECT
EXTERNAL
Ibl OPTIONAL PULLUP RESISTOR
EXTERNAL
SWITCH ~
FIGURE 4. TEST 1 PIN
FIGURE 5. I/O EXPANDER INTERFACE
2-23
SINGLE COMPONENT SYSTEM
PROG
V ADDRESSJ
DATA IN
~
-----DATA OUT
(P20·P23)
)Cf)C
FLOAT
14 BITS)
(4 BITS)
~
DATA
~
OUT
-----....
(4 BITS)
'---~(4~BIT=S)~--------------BITS 0,1
01
OO} PORT
10 ADDRESS
11
BITS 2,3
OO}READ
01 WRITE
10 OR
11 AND
PORT 2 FOR EXPANDED 1/0 WITH 8243
FIGURE 6. EXPANDED I/O TIMING DIAGRAM
2.10 CPU
The 8021 CPU has arithmetic and logical
capability. A wide variety of arithmetic and
logic instructions may be exercised, which
affect the contents of the accumulator,
and/or direct or indirect scratch pad locations. Provisions have been made for
simplified BCD arithmetic capability using
the DAA, SWAP A, and XCHD instructions.
In addition, MOVP A,@A allows table
lookup for display formating and constants.
The conditional branch logic within the
processor enables several conditions internal and external to the processor to be
tested by the users program. Use the
conditional jump instructions with the tests
listed below to effect a change in the
program execution sequence.
Test
Accumulator
Carry Flag
Timer Overflow Flag
Test Input-T1
Jump
Condition
Jump
Instructions
A=O A"'O
o 1
JZ JNZ
,JC
JTF
JNT1, JT1
o
1
1
2.11 Reset
A positive-going signal to the RESET input
resets the necessary miscellaneous flipflops and sets "the program counter and
stack pOinter to zero.
2-24
SINGLE COMPONENT SYSTEM
8022 Functional Specifications
2.13 Data Memory
The 8022's architecture is based upon the 8021,
and many functions of the two parts are identical.
On-chip data memory is organized as 64 words
eight bits wide. All locations are indirectly addressable and eight designated locations are directly
addressable. Also included in the data memory is
the program counter stack, addressed by a 3-bit
stack pointer.
2.12 Program Memory
The 8022 program memory consists of 2048
words 8 bits wide which are addressed by the
program counter. The memory is ROM which is
mask programmable at the factory. No external
ROM expansion capability is provided. There are
three locations in program memory of special importance.
The first eight locations (0-7) of the array are
designated as working registers and are directly
addressable by any of the 11 direct register
instructions. These locations are readily accessible for a variety of operations with a minimum number of instruction bytes required for their
manipulation. Thus, they are usually used to store
frequently accessed intermediate results. The
DJNZ instruction makes very efficient use of the
working registers as program loop counters by allowing the programmer to decrement and test the
register in a single instruction.
Location 0: Activating the RESET line of the processor causes the first instruction to
be fetched from location O.
Location 3: Activating the interrupt input line
(TO) of the processor (if interrupt is
enabled) causes a jump to subroutine.
Registers a and 1 have yet another function in that
they can be used to indirectly address all locations in the data memory using the indirect register
instructions. These two RAM pointer registers are
especially useful for repetitive type operations on
adjacent memory locations. The indirect register
instruction specifies which register is used to address a location in RAM. The contents of the addressed location are used during the execution of
the instruction and may be modified. The pointer
registers may also point to registers 0-7, if desired.
Location 7: A timer / event counter interrupt resulting from a timer / counter overflow causes a jump to subroutine (if
timer / counter interrupt is enabled).
Therefore, the first instruction to be executed
after initialization is stored in location 0, the first
word of an external interrupt service routine is
stored in location 3, and the first word of a timer/ event counter interrupt service routine is stored
in location 7.
Locations 8-23 serve a dual role in that they contain the 8-level program counter stack, two RAM
locations per level. The program counter stack enables the processor to keep track of the return
addresses generated by interrupts or CALL
instructions by storing the contents of the program
counter prior to servicing the subroutine. A 3-bit
stack pointer determines which of the program
counter stack's eight register pairs will be loaded
with the next return address generated. The stack
pointer, when initialized to 000 by RESET, points
to RAM locations 8 and 9. The first subroutine
CALL or interrupt results in the program counter
contents being transferred to locations 8 and 9.
The stack pointer is then incremented by one and
pOints to locations 10 and 11 in anticipation of another CALL The end of a subroutine, which is signaled by a return instruction (RET or RETI),
causes the stack pointer to be decremented and
the contents of the resulting register pair to be
transferred to the program counter.
2047
8
7
LOCATION 7 - TIMER/COUNTER INTERRUPT
VECTORS PROGRAM HERE
6
5
LOCATION 3-EXTERNAL INTERRUPT
VECTORS PROGRAM HERE
76543210
RESEr VECTORS PROGRAM HERE
PROGRAM MEMORY MAP
Program memory can be used to store constants
as well as program instructions. The MOVP instruction allows easy table lookup for constants
and display formatting.
2-25
SINGLE COMPONENT SYSTEM
Unlike the 8048, in the 8022 the unincremented
program counter address is stored in the address
stack. The stack contents are then incremented
before being loaded Into the program counter during a return (RET) from subroutine. However, during a return (RETI) from interrupt, the stack
contents are loaded directly into the program
counter. This difference makes it imperative to
use only RETI's to return from interrupts, and
RET's to return from subroutines.
Since the program counter's addresses are 11
bits long, two bytes or registers must be used to
store a single address. Thus, the 16-byte program
counter stack permits up to a total of 8 levels of
subroutine nesting without overflowing the stack.
If overflow does occur, the deepest address
stored (locations 8 and 9) will be overwritten and
lost since the stack pointer overflows from 111 to
000. It also underflows from 000 to 111. If a particular application does not require 8 levels of
nesting, the unused portion of the progam counter
stack may be used as any other indirectly addressable RAM location. For example, if only 3 levels
of subroutine nesting are used, then only locations
8-13 need be reserved for the program counter
stack, and locations 14-23 can be used for data
storage.
'2.15 Timer/Event Counter
Like the other MCS-48 microcomputers, the 8022
has an internal timer I event counter. This circuit
can monitor elapsed time or count external events
that occur during program execution.
See the 8021 description, Section 2.8, for a complete explanation.
The 8022 has 26 lines which can be used for digital input or output functions. These lines are organized as 3 ports of 8 lines, each of which serve as
either inputs, outputs, or bidirectional ports, and 2
test inputs which can alter program sequences
when tested by conditional jump instructions.
Ports 1 and 2 have identical operating characteristics and are both quasi-bidirectional. That is,
each line may serve as an input, an output, or
both. Data written to these ports is statically
latched and remains unchanged until rewritten. As
inputs, these lines are non-latching; i.e., inputs
must be present until read by an input instruction.
Inputs are fully TTL compatible and all outputs will
drive at least one standard TTL load. See Section
2.1.4 for a more complete description of the quasi-bidirectional structure.
2.16.1 Port 0 Comparator Inputs
18
24
23 8 LEVEL aTACK
OR
USER RAM
18.8
Rl~l\r:.
1
ADDRJ.
EIIED
IN DIRECTLV
THROUQH
RGORR1
DIRECTlv
ADDR~8LE
DATA MEMORY MAP
2. 14 Oscillator and Clock
The 8022 contains its own on-board oscillator and
clock circuit, requiring only an external timing control element. This control element can be a crystal, inductor, or clock. All Internal time slots are
derived from the external element, and all outputs
are a function of the oscillator frequency.· An instruction cycle consists of 10 states, and each
state is a time slot of 3 oscillator periods. Therefore, to obtain a 10 fJ,s instruction cycle, a 3 MHz
crystal should be used. The minimum instruction
cycle time of 8.4 fJ,sec corresponds to a 3.58 mHz
crystal.
Port 0 has been modified from the standard quasibidirectional structure to allow an optional open
drain configuration with comparator inputs. The
low impedance pullup device has been eliminated
and the high impedance pullup is optional. Thus,
the user can choose via a mask programmable
selection each line of port a to be either quasi-bidirectional with a high impedance or true opendrain. The open drain configuration allows the line
to sink current through the low impedance pulldown device or to float in the high output state.
More importantly, the open drain configuration
makes port 0 very easy to drive when it is used as
inputs. The input circuitry for each line of port 0
includes a voltage comparator which amplifies the
voltage difference between the input port line and
the port 0 threshold reference pin (VTH). The voltage gain of the comparator is sufficient to sense a
100 mV input differential within the range VSS to
VCC /2. ·
.
If VTH is allowed to float, it will bias itself to the
digital switch point of the other ports, and port a
behaves as a set of normal digital inputs. However, by biasing VTH, the switch point can be both
tightly controlled and adjusted. Common uses for
2·26
SINGLE COMPONENT SYSTEM
this would include high noise margin inputs
(Vee 12), unusual logic level inputs as from a diode
isolated keyboard, analog channel expansion, and
direct capacitive touchpanel interface. The comparator action is automatic and the port is read
just as any other port.
to the TO pin when external interrupt is enabled.
Interrupt is level triggered and active low to allow
"WIRE ORING" of several interrupt sources at the
input pin. When an interrupt is detected, it causes
a "jump to subroutine" at location 3 in program
memory as soon as all other cycles of the current
instruction are complete. At this time, the program
counter contents are saved in the program
counter stack, but the remaining status of the processor is not. Unlike the 8048, the 8022 does not
contain a program status word. Thus, when appropriate, the carry and auxiliary carry flags are
saved in software, as is the accumulator. The routine shown below saves the accumulator and the
carry flags in only four bytes.
2.16.2 High Current Outputs
Very high current drive is desirable for minimizing
external parts required to do high power control.
P 1a and P 11 have been designated high drive outputs capable of sinking 7mA at VSS + 2.5 volts.
(For clarity, this is 7mA to VSS with a 2.5 volt drop
across the buffer.) These pins may, of course, be
paralleled for 14mA drive if the output logic states
are always the same.
Instructions
2.16.3 Expanded 1/0
MeV R6.A
CLR A
DAA
MeV R7.A
In addition to the 26 digital I I 0 lines contained onboard the 8022, a user can obtain additional 1/0
lines by utilizing the Intel(!) 8243 I 10 expander chip
or standard TTL. The 8243 interfaces to 4 port
lines of the 8022 (lower half of port 2) and is
strobed by the PROG line of the 8022.
Bytes Comments
1
;aave accumulator
;clear accumulator
;convert carry flags into sixes
;save status of carry flags
The end of an interrupt service subroutine is
marked by the execution of a Return from Interrupt
instruction (RETI). Prior to returning from the interrupt subroutine, however, the status of the accumulator and the carry flags are restored in
software. The following routine restores the status of the accumulator and the carry flags, which
was previously saved, in five bytes.
The interface procedure is exactly the same as
with the 8021-see Section 2.9.3.
2.17 Test and Interrupt Inputs
In addition to the 24 general purpose I I 0 lines
which comprise ports 0, 1, and 2, the 8022 has
two inputs which are testable via conditional jump
instructions, TO and T 1. These pins allow inputs to
cause program branches without the necessity to
load an input port into the accumulator. TO and T1
have other functions as well.
Instructions
MeV A,R7
Add A,#OAAH
MeV A,RS
RETI
The Test a pin serves as an external interrupt input as well as a testable input. An interrupt sequence is initiated by applying a low "0" level input
Bytes Comments
1
2
;restore carry flaga status to
;accumulator and set/clear carry flags
;reatore accumulator
;return
The interrupt system is single level in that once an
interrupt is detected, all further interrupt requests
are ignored until execution of a RETI re-enables
+5V
r--_--~ XTAL 1
r - - -.......- - - i XTAL 1
1K
J<>--_ _
... _ 1 _
OPTIONAL
C=20-5OpF
by'LC
L..-_--...
XTAL2
INDUCTOR
D
--~XTAL
1
1 MEGQ
' - - - -.......- - - - . XTAL 2
.6-3.6 MHz
CRYSTAL
FREQUENCY REFERENCE OPTIONS
2-27
NC
EXTERNAL
XTAL2
SINGLE COMPONENT SYSTEM
+5V
Q
_KQ.--------,
D
FLIp·
I/O PIN
PORTO
FLOP
ClK
VYH
PORT 0
I/O STRUCTURE
the interrupt input logic. This sequence holds true
also for an internal interrupt generated by timer
overflow. If an external interrupt and an internal timer / counter generated interrupt are detected at
the same time, the external source will be recognized. If needed, a second external interrupt can
be created by enabling the timer / counter interrupt, loading FFH inthe counter (one less than terminal count) and enabling the event counter mode.
A low-to-high transition on the T 1 input will then
cause an interrupt vector to location 7.
T
-*---*'-1----1-- 1-3 VAC
X
P
ZERO-CROSS DETECTION
The Test 1 pin, in addition to being a testable input, serves two other important functions. It can
be used as an input pin to the external event
counter, as previously mentioned, and it can be
used to detect the zero crossing pOint of slow
moving AC signals. Execution of the STRT CNT
instruction puts the T1 pin in the counter input
mode by connecting T1 to the counter and enabling the counter. Subsequent low-to-high transi-
tions on T1 will cause the counter to increment.
Note that this operation differs from the rest of the
MCS-48 devices, which increment the counter on
high-to-Iow transitions. This change was made on
the 8022 to take advantage of the accuracy of the
rising edge detection on the zero cross circuitry.
The maximum rate at which the counter may be
incremented is once per three instruction cycles
(every 30 f./,S when using a 3 MHz crystaJ)-there
is no minimum frequency.
In addition to serving as a testable input and as the
counter input, the T1 pin has special circuitry to
detect when an AC signal crosses its average DC
level. When driven directly, this pin responds as a
normal digital input. To utilize the zero cross detection mode, an AC signal of approximately 1-3
VAC pop magnitude and a maximum frequency of
1 kHz is coupled through an external capacitor (1
f./,F) to the T1 pin.
.
The internal digital state is sensed as a zero until
the rising edge crosses the DC average level,
when it becomes a one. This is accomplished by
the self-biasing high gain amplifier which is included in the T 1 input. This circuit biases the T 1 input
exactly at its switching point, such that a small
change will cause a digital transition to occur. This
digital transition takes place within 5 degrees of
the zero point. The digital value of T1 remains a
one until the falling edge of the AC input drops approximately 100 mV below the switching point of
the rising edge (100 mV below the zero pOint, if
the digital transition occurred exactly at the zero
point). The 100 mV offset is created by hysteresis
and eliminates chattering of the internal Signal
caused by the external noise.
2-28
SINGLE COMPONENT SYSTEM
The zero cross detection capability allows the
user to make the 60 Hz power signal the basis for
this system timing. All timing routines, including
time-of-day, can be implemented using the zero
cross detection capability of T 1 and its conditional
jump instructions. In addition, the zero cross detection feature can be used in conjunction with the
timer interrupt to interrupt processing at the zero
voltage point. This enables the user to control voltage phase sensitive devices such as triacs and
SCRs, and to use the 8022 in applications such as
shaft speed and angle measurement.
2.18 Analog to Digital Converter
The 8022 contains on-chip a complete hardware
implementation of an 8-bit analog to digital (AID)
converter with two multiplexed analog inputs. The
A I D converter utilizes a successive approximation technique to provide an updated conversion
once every four instruction cycles with a minimum
of required software.
The AID converter consists of four main parts,
the input circuitry, a series string of resistors, a
voltage comparator, and the successive approximation logic. The two analog inputs are mUltiplexed on-Chip and selected via software by the
SEL ANO and SEL AN 1 instructions. Besides selecting one of the analog inputs, these instructions
restart the conversion sequence which operates
continuously. Restarting a conversion sequence
deletes the conversion in progress but does not
affect the result of the previous conversion which
is stored in the conversion result register. The
continuous operation of the A I D converter saves
program space and time by allowing the user obtain multiple readings from a given input with only
one select instruction. To obtain a valid conversion
reading, the user must provide the analog input
signal no later than the beginning of the select instruction cycle. The analog input is then sampled
by the A I D converter and maintained internally.
This voltage becomes one input to the voltage
comparator which amplifies the difference between the analog input and the voltage tap on the
series resistor string.
'
The series resistor string is connected between
the A I D reference pin (V ARE F) and ground
(AVSS). It is comprised of 256 identical resistors
which divide the voltage between these two pins
into 256 identical voltage steps. This configuration
gives the converter its iflherent monotonicity. The
range of VAREF in which full 8-bit resolution can be
provided is between Vee/2 and Vee.
Thus, the user is given a minimum voltage range
from ground to VCC 12 and a maximum range from
ground to Vee over which 8-bit resolution is insured.
The voltage tap on the series resistor string is selected by the resistor ladder decoder. This decoder is driven by the 8-bit successive approximation
register (SAR). Each bit of the SAR is set in succeSSion, MSB to LSB, and a voltage comparison
between the selected resistor ladder voltage and
the analog input voltage is performed after the setting of each bit. The result of each comparison determines whether the particular bit will remain set
or be reset. All comparisons are performed automatically by the on-Chip AID hardware. At the end
of 8 comparisons the SAR contains a valid digital
result which is then latched into the conversion result register (CRR). The RAD instruction (read
AID) loads the conversion result from the CRR to
the accumulator of the 8022.
ANALOG MULTIPLEXER
r---~
I
I
I
RESISTIVE
LADDER
-
-"--~-----,
RI2
I :'
I!
8-W
R
RI2
I
I
,
I
I Ill'
'''';!~.. I
I" I
I I
L __ L.J
8-
INTERNAL BUS
AID CONVERTER BLOCK DIAGRAM
As mentioned previously, the software and time
required to perform an A I D conversion is optimized by the 8022's on-chip AID converter configuration. Typical software for reading two
sequential A I D conversions and storing them in
data memory is shown below:
2-29
SINGLE COMPONENT SYSTEM
First
Conversion
50/Ls
4 bytes
SEL ANO
MOVRO.#24
RAD
;Starts conversion of ANO input
;Set up ~emory pointer
;First conversi.on value to
accumulator
Second
Conversion
40/Ls
3 bytes
MOV@RO.A
INCRO
RAD
;Store first conversion value
;Increment memory location
:Second conv8.rsion value to
accumulator
Note that the second conversion occurs without a
second select instruction being used. Rather, the
continuous operation of the A I D converter provides an updated digital value 4 instruction cycles
after the first.
To insure maximum accuracy from the AID converter, separate power supply pins (AVCC and
AVSS) and a substrate pin (SUBST) have been
provided. Supplying the power supply pins with a
well filtered and regulated voltage supply minimizes the effect of power supply variance and
system noise. The substrate pin should be bypassed to ground through a 500 pF to 0.001 f,LF
capacitor.
user's program. Use the conditional jump instructions with the tests listed below to effect a change
in the program execution sequence.
A=O k'l'O
0 1
-1
0 1
0 1
Accumulator
Carry Flag
Timer Overflow Flag
Test Input·Tl
Test Input·TO
Jump
Instructions
JZ JNZ
JNC. JC
JTF
JNT1. JTl
JNTO. JTO
2.20 8022 Testing and Debug
To facilitate testing and debug, certain test modes
may be activated in the 8022 by raiSing combinations of RESET, TEST 1 and PROG to 15 volts.
Internal ROM is dumped out sequentially for verification. External memory operation is used for
CPU checkout.
2.19 CPU
The 8022 CPU has arithmetic and logical capability. There is a wide variety of arithmetic and logic
instructions which affect the contents of the accumulator, and lor direct or indirect scratchpad locations. Provisions have been made for simplified
BCD arithmetic capability using the DAA, SWAP
A, and XCHD instructions. In addition, MOVP
A, @A allows table lookup for display formating
and constants. The conditional branch logic within
the processor enables several conditions internal
and external to the processor to be tested by the
Jump
Condition
Test
Reset
Prog
Te.t 1
5V
OV
15V
X
X
15V
X
X
15V
Mode la
15V
15V
JL..
Mode lb.
OV
15V
X
Mode 2
15V
X
X
Mode 3
Calie
Function
Power On Clear
Normal Operation
On each cycle internal ROM is
dumped to Port O-sequentially
after ALE leading edge .. '
On every TEST· 1 failing edge
the program counter incre·
ments. dumps internal ROM to
Port 0
Chip will operate from external
memory (one page) via Port O.
ALE strobes Address out. memo
ory in.
Chip accepts op codes into
Port 1. Allows Port 0 and 8243
testing.
NOTE
X = Normal mode - between OV and Vee
2-30
The Expanded
" MC~48TMS~stem
THE EXPANDED MCS-4S™SYSTEM
3.0 Summary
3.1 Expansion of Program Memory
If the capabilities resident on the singlechip 8048/8049,8748, or 8035/8039 are not
sufficient for your system requirements,
special on-board circuitry allows the
addition of a wide variety external memory,
I/O, or special peripherals you may require.
The processors can be directly and simply
expanded in the following areas:
Program Memory is expanded beyond the
resident 1K or 2K words by using the 8085
BUS feature of the MCS-48. All program
memory fetches from addresses less than
1024 (2048) occur internally with no
external signals being generated (except
ALE which is always present). At address
1024 the 8048 automatically initiates external program memory fetches.
• Program Memory to 4K words
3.1.1 Instruction Fetch Cycle (External)
• Data Memory to 320 words (384 words
with 8049)
For all instruction fetches from addresses
of 1024 (2048) or greater the following will
occur:
1. The contents of the 12 bit program
counter will be output on BUS and the lower
half of port 2.
• I/O by unlimited amount
• Special Functions using 8080/8085
peripherals
By using bank switching techniques maximum capability is essentially unlimited. Bank
switching is discussed later in the chapter.
Expansion is accomplished in two ways:
2. Address Latch Enable (ALE) will indicate the time at which address is valid. The
trailing edge of ALE is used to latch the
address externally.
1. Expander I/O-A special I/O Expander
circuit the 8243 provides for the addition of
four 4-bit Input/Output ports with the sacrifice of only the lower half (4 bits) of port 2
for inter-device communication. Multiple
8243's may be added to this 4-bit bus by
generating the required "chip select" lines.
3. Program Store Enable (PSEN) indicates
that an external instruction fetch is in progress and serves to enable the external
memory device.
4. BUS reverts to input (floating) mode
and the processor accepts its 8 bit
contents as an instruction word.
2. Standard 8085 Bus-One port of the
8048 is like the 8 bit bidirectional data bus
of the 8085 microcomputer system allowing interface to the numerous standard
memories and peripherals of the MCS80/85 microcomputer family.
All instruction fetches including internal
addresses can be forced to be external by
activating the EA pin of the 8048/8049. The
8035/8039 processors without program
memory always operate in the external
program memory mode (EA=5Vl.
MCS-48 systems can be configured using
either or both of these expansion features to
optimize system capabilities to the application.
Both expander devices and standard memories and peripherals can be added in virtually
any number and combination required.
3.1.2 Extended Program Memory
Addressing (Beyond 2K)
For programs of 2K words or less, the
8048/8049 addresses program memory in
3·1
EXPANDED MCS-48 SYSTEM
ALE
BUS
J
L
~
FLOATING
ADDRESS
0:
Conventional Program Counter
• Counts DDDH to 7FFH
• Overflow. 7FFH to DDDH
JMP or CALL Instructions trans'er oontenta 0'
Internal IIIpfiop to A11
• Fflpflop set by SEL MBl
• Flipflop ....t by SEL MBD
or by RESET
FLOATING
INSTRUCTION
During Interrupt I.rvlce routln.
A11 Is 'orced to "0"
All 12 bits are lav.d In atack
INSTRUCTION FETCH FROM
EXTERNAL PROGRAM MEMORY
PROGRAM COUNTER
the conventional manner. Addresses beyond 2047 can be reached by executing a
program memory bank switch instruction
(SEL MBO, SEL MB1) followed by a branch
instruction (JMP or CALL). The bank switch
feature extends the range of branch
instructions beyond their normal 2K range
and at the same time prevents the user from
inadvertently crossing the 2K boundary.
entirely in the lower 2K words of program
memory. The execution of a SEL MBO or SEL
MB1 instruction within an interrupt routine is
not recommended since it will not alter PC11
while in the routine, but will change the
internal flip flop.
3.1.3 Restoring I/O Port Information
Program Memory Bank Switch
Although the lower half of Port 2 is used to
output the four most significant bits of address
during an external program memory fetch,
the I/O information is still outputed during
certain portions of each machine cycle. I/O
information is always present on Port 2 lower
at the rising edge of ALE and can be sampled
or latched at this time.
The switching of 2K program memory banks
is accomplished by directly setting or resetting
the most significant bit of the program counter
(bit 11). Bit 11 is not altered by normal incrementing of the program counter but is loaded
with the contents of a special flip-flop each
time a JMP or CALL instruction is executed.
This special flip-flop is set by executing an
SEL MB1 instruction and reset by SEL MBO.
Therefore, the SEL MB instruction may be
executed at any time prior to the actual bank
switch which occurs during the next branch
instruction encountered. Since all twelve bits
of the program counter including bit (11) are
stored in the stack when a Call is executed,
the user may jump to subroutines across the
2K boundary and the proper bank will be
restored upon return. However, the bank
switch flipflop will not be altered on return.
3.1.4 Expansion Examples
The accompanying figure shows the addition
of three 27081K X 8 EPROMs or three 2308
pin-compatible ROM replacements for a total
of 4K words of program memory. The BUS
port of the 8048 is connected directly to the
data output lines of the memories. The lower
8 bits of address are latched in an 8212 8-bit
latch using ALE as the strobe. The lower half
of Port 2 provides the upper 4 bits of address
and since these address bits are stable for
the duration of the program memory fetch,
they do not have to be latched. Two of the
upper address bits are connected directly to
the address inputs of the memories while the
two most significant bits are decoded to
provide the three chip selects needed. The
PSEN output of the 8048/8748 is used to
enable the chip select lines and therefore the
memories.
Interrupt Routines
Interrupts always vector the program counter
to location 3 or 7 in the first 2K bank and bit
11 of the program counter is held at "0"
during the interrupt service routine. The end
of the service routine is signalled by the
execution of an RETR instruction. Interrupt
service routines should therefore be contained
3·2
EXPANDED MCS-48 SYSTEM
PROGRAM MEMORY
J:=4=======::;-;:=~DECODER
1 OF 4
PORT 20·3
ALE
1-----+1
r---...,
0,
27081
2308
1K·2K
10
8212
LATCH
8048
i----ICS
cs 27081
2308
2K·3K
cs 27081
2308
3K ·4K
PSEN~----------------------~
USING lK x 8 PROM/ROM
DATA
OUT
EXPANDING MCS-48 ™ PROGRAM MEMORY USING STANDARD MEMORY PRODUCTS
Also shown is the addition of 2K words of
program memory using an 2316A 2K x 8
ROM to give a total of 3K words of program
memory. In this case no chip select decoding
is required and PSEN enables the memory
directly through the chip select input. If the
system requires only 2K of program the same
configuration can be used with an 8035
substituted for the 8048. The 8049 would
provide 4K with the same configuration.
The next figure shows how the new 8755/8355
EPROM/ROM with I/O interfaces directly to
the 8048 without the need for an address
latch. The 8755/8355 contains an internal 8-bit
address latch eliminating the need for an
8212 latch. In addition to a 2K X 8 program
memory the 8755/8355 also contains 16 I/O
lines addressable as two 8-bit ports. These
ports are addressed as external RAM; there-
3
PORT 20·22
8048
ALE
A
BUS
B
I?>
8212
"'
7
'"
11)
ADDRESS
2316
LATCH
ROM
DATA
OUT
CS
PSEN
USING 2K x 8 ROM
EXPANDING MCS-48™ PROGRAM MEMORY USING STANDARD MEMORY PRODUCTS
3·3
EXPANDED MCS-48 SYSTEM
3.2 Expansion of Data Memory
fore, the RD and WR outputs of the 8048 are
required. See the following section on data
memory expansion for more detail. The subsequent section on I/O expansion explains
the operation of the 16 I/O lines.
Data Memory is expanded beyond the resi
dent 64 words by using the 8085 type bus
feature of the MCS-48.
3.2.1 Read/Write Cycle
ALE
ALE
Pmii
WR
iUS
iOW
8048 iUS
lOR
All address and data is transferred over the 8
lines of BUS. A read or write cycle occurs as
follows:
2K X8
1. The contents of register RO or R1 is outputed on BUS.
ROM/
PROM
WITH
A/DO-7 I/O
8355/
8755
BUS
I/O
2. Address Latch Enable (ALE) indicates
address is valid. The trailing edge of ALE is
used to latch the address externally.
A s -A 10 ·CS
3. A read (RD) or write (WR) pulse on the
corresponding output pins of the 8048 indicates the type of data memory access in
progress. Output data is valid at the trailing
edge of WR and input data must be valid at
the trailing edge of RD.
3
TEsT
INPUTS
I/O
4. Data (8-bits) is transferred in or out over
BUS.
EXTERNAL PROGRAM MEMORY INTERFACE
READ FROM EXTERNAL DATA MEMORY
ALE
BUS
J
L
FLOATINcXADDRESSX
7' >8<~
__
F_LO_A_T_IN_G_ _
FLOATING
WRITE TO EXTERNAL DATA MEMORY
ALE
J
L
BUS
FLOATING
3·4
EXPAND!!D MCS-48 SYSTEM
3.2.2 Addressing
~Xt~rnal Data Memory
tional 4-bit data bus of the memories. The WR
output of the processor controls the Read/
Write input of the memories while the data
bus output drivers of the memories are controlled by RD. The chip select lines of the
memories are continuously enabled unless
additional pages of RAM are required. Also
shown is the expansion of data memory using
the 8155 memory and I/O expanding device.
Since the 8155 has an internal 8-bit address
latch it can interface directly to the 8048 without the use of an external 8212 latch. The
8155 provides an additional 256 words of static data memory and also includes 22 I/O
lines and a 14 bit timer. See the following section on I/O expansion and the 8155 data sheet
for more details on these additional features.
External Data Memor~ Is ~~cessed with its
own two-cycle move instructions MOVX A
@R and MOVX @R, A which transfer 8 bits of
data between the accumulator and the external memory location addressed by the
contents of one of the RAM Pointer Registers
RO or R1. This allows 256 locations to be
addressed in addition to the resident
locations. Additional pages may be added
by "bank switching" with extra output lines of
the 8048.
3.2.3 Examples of Data Memory
Expansion
The accompanying figure shows how the
8048 can be expanded using standard 256 X
4 static RAMs such as the 2101-2 or its low
power CMOS equivalent, the 5101. An 8212
serves as an address latch while each 4-bit
half of BUS is connected directly to a bidirec-
3.3 Expansion of Input/Output
There are four possible modes of I/O
expansion with the 8048: one using a
special low cost expander, the 8243;
BUS ~------------~s----------------------------~
I/O 1·4
ALE
8048
0S2
1m 8212 gg~
A
MO
~
CS1
I/O 1-4
.~2111/2101 eI2
o
5101
00
CS1
2111/2101C'S2
o 7 5101
A .A
R/W
00
R/W
ROt--------------------4----~------------~
____~m~----------------------~----------------~
sus K
ALE
8048
8
ADo·7
"
8155
ALE
WR
iii)
WR
RD
PORT
268X8
RAM
101M
3
18
~
TEST
INPUTS
} 1/0
8048 INTERFACE TO 256 X 8 STANDARD MEMORIES
3·5
22
"
-y
110
TIMER IN
TIMER OUT
EXPANDED MCS-48 SYSTEM
bits to zero. All communication between the
8048 and the 8243 occurs over Port 2 lower
(P20-P23) withtimiilg provided by an output
pulse on the PROG. pin of the processor~ Each
transfer consists of two 4-bit nibbles:
another using standar.d MCS-80/85 I/O
devices; and a third "using the combination
memory/I/O expander devices the 8155,
8355, and 8755. It is also possible to expand
using standard TTL devices as shown in
Chapter 5.
The first containing the "op code" and port
address and the second containing the actual
4 bits of data.
3.3.1 I/O Expander Device
The most efficient means of I/O expansion for
small systems is the 8243 I/O Expander Device which requires only 4 port lines (lower
half of Port 2) for communication with the
8048. The 8243 contains four 4-bit I/O ports
which serve as extension of· the on chip I/O
and are addressed as ports #4-7. The following operations may be performed on these
ports:
1.
2.
3.
4.
Nibble 2
Nibble 1
3
2
1
0
3
I
2
1
II I A I A
Id Id Id Id
Instruction
data
Port
Code
Address
II
AA
OO-Port #4
01-Port #5
10-Port #6
11-Port #7
00 Read
01 Write
10 OR
11 AND
Transfer Accumulator to Port.
Transfer Port to Accumulator.
AND Accumulator to Port.
OR Accumulator to Port.
A 4-bit transfer from a port to the lower half of
the Accumulator sets the most significant four
EXPANDER INTERFACE
fl
-=-
PROG
20
"
2
"
CS
I/O
...
CHIP SELECT CONNECTIO N IF MORE
THAN ONE EXPANDER IS USED
P4
P5
] TEST
INPUTS
4
"
4
v
.
v
v
I/O
I/O
.
8243
A
P20-P23
4
"
PROG
A
8048
>
~
A-
('
P6
4
P7
4
DATA IN
P2
v
"
v
I/O
I/O
OUTPUT EXPANDER TIMING
\ ___-----..11
PROG
P20·P23
___ _____
~
~X
ADDRESS (4-BITS)
ANDOPCODE
0
~)~·~-
DATA (4-BITS)
3·6
BITSD.l
DO}
01
PORT
10
ADDRESS
11
BITS 2.3
DO} READ
01
10
WRITE
OR
11
AND
I
EXPANDED MCS-48 SYSTEM
A high to low transition of the PROG line indicates that address is present while a low to
high transition indicates the presence of data.
Additional 8243's may be added to the four bit
bus and chip selected using additional output
lines from the 8048/8748.
3.3.3 Combination Memory and I/O
Expanders
As mentioned in the sections on program and
data memory expansion the 8355/8755 and
8155 expanders also contain I/O capability.
8355/8755: These two parts are ROM and
EPROM equivalents and therefore contain
the same I/O structure. I/O consists of two
8-bit ports which normally reside in the external data memory address space and are accessed with MOVX instructions. Associated
with each port is an 8-bit Data Direction Register which defines each bit in the port as
either an input or an output. The data direction
registers are directly addressable thereby allowing the user to define under software control each individual bit of the ports as either
input or output. All outputs are statically
latched and double buffered. Inputs are not
latched.
I/O Port Characteristics
Each of the four 4-bit ports of the 8243 can
serve as either input or output and can provide high drive capability in both the high and
low state.
3.3.2 I/O Expansion with Standard
Peripherals
Standard MCS-80/85 type I/O devices may
be added to the MCS-48 using the same bus
and timing used for Data Memory expansion. I/O devices reside on the Data
Memory bus and in the data memory
address space and are accessed with the
same MOVX instructions. See the previous
section on data memory expansion for a
description of timing. The following are a
few of the Standard MCS-80 devices which
are very useful in MCS-48 systems.
8214
8251
8255
8279
8253
8155/8156: I/O on the 8155/8156 isconfigured as two 8-bit programmable I/O ports
and one 6-bit programmable port. These
three registers and a Control/Status register are accessible as external data memory
with the MOVX instructions. The contents
of the control register determines the mode
of the three ports. The ports can be
programmed as input or output with or
without associated handshake communication lines. In the handshake mode, lines
of the six,..bit port become input and output strobes for the two 8-bit ports. See the
Priority Interrupt Encoder
Serial Communications Interface
General Purpose Programmable I/O
Keyboard/Display Interface
Intervallimer
See Chapter 7 for detailed data sheets on
these and other components.
8
INT
INT
P20
CfD
RD
KEYBOARD
RD DISPLAY
WR
WR
8279
8048
CS
3-7
SCAN
OUTPUTS
(A) DISPLAY
OUTPUT
BUS
KEYBOARD/DISPLAY INTERFACE
KEYBOARD
INPUTS
(B)DISPLAY
OUTPUT
EXPANDED MCS-48 SYSTEM
data sheet in Chapter 6 for details. Also
included in the 8155 is a 14-bit programmable timer. The clock input to the timer
and the timer overflow output are available
on external pins. The timer can be programmed to stop on terminal count or to
continuously reload itself. A square wave or
pulse output on terminal count can also be
specified.
(chip select) input used to enable the Read/
Write control logic and the address inputs
used to select various internal registers.
A.,
8048
A,
8255
PROGRAMMABLE
PERIPHERAL
INTERFACE
ALE
PORT
A
PORT
B
Fi15
1/0 Expansion Examples
(See Also Chapter 5)
PORT
C
The accompanying figure shows the
expansion of 1/0 using multiple 8243's. The
only difference from a single 8243 system is
the addition of chip selects provided by
additional 8048 OLitput lines. Two output
lines and a decoder could also be used to
address the four chips. Large numbers of
8243's would require achip select decoder
chip such as the 8205 to save 1/0 pins.
OPTION
P20
P21
8048
AD
ViR
Also shown is the 8048 interface to a standard MCS-80 peripheral; in this case, the
8255 Programmable Peripheral Interface, a
40 pin part which provides three 8-bit programmable I/O ports. The 8255 bus interface
is typical of programmable MCS-80 peripherals with an 8-bit bidirectional data bus, a RD
and WR input for Read/Write control, a CS
#,
Ao
A,
8255
PROGRAMMABLE
PERIPHERAL
INTERFACE
AD
FA
PORT
A
PORT
B
PORT
C
BUS
00·7
cs
OPTION #2
-=-
INTERFACE TO MCS-SO PERIPHERALS
PORT 1
8048
PROGI------~-----__+------~---_ _ ____'
LOW COST 1/0 EXPANSION
3-8
EXPANDED MCS-48 SYSTEM
Interconnection to the_8048 lL very
straightforward with BUS, RD, and WR connecting directly to the corresponding pins on
the 8255. The only design consideration is the
way in which the internal registers of the 8255
are to be addressed. If the registers are to be
addressed as external data memory using the
MOVX instructions, the appropriate number of
address bits (in this case, 2) must be latched
on BUS using ALE as described in the section
on external data memories. If only a single
device is connected to BUS, the 8255 may be
continuously selected by grounding CS. If
multiple 8255's are used, additional address
bits can be latched and used as chip selects.
3.4 Multi-Chip MCS-48 Systems
The accompanying figure shows the addition
of two memory expanders to the 8048, one
8355/8755 ROM and one 8156 RAM. The
main consideration in designing such a system is the addressing of the various memories
and I/O ports. Note that in this configuration
address lines A,o and A" have been ORed to
chip select the 8355. This ensures that the
chip is active for all external program memory
fetches in the 1K to 3K range and is disabled
for all other addresses. This gating has been
added to allow the I/O port of the 8355 to be
used. If the chip was left selected all the time
there would be conflict between these ports
and the RAM and I/O of the 8156. The NOR
gate could be eliminated and~" connected
directly to the CE (instead of CE) input of the
8355; however, this would create a 1K word
"hole" in the program memory by causing the
8355 to be active in the 2K to 4K range instead of the normal 1K to 3K range.
A second addressing method eliminates external latches and chip select decoders by
using output port lines as address and chip
select lines directly. This method, of course,
requires the setting of an output port with address information prior to executing a MOVX
instruction.
8156/8355
8048
PORT
A
PORT
B
PORT
C
---TIMER
OUT
THE THREE COMPONENT MCS-48 SYSTEM
3-9
EXPANDED MCS-48 SYSTEM
PROGRAM MEMORY
SPACE
BFFH
MB1
8355
(2K)
EXTERNAL DATA
MEMORY SPACE
MBO
400H
- - - - - - - - 300H
RESIDENT
- - - - - - - 200H
(1K)
- - - - - - - - 100H
F=====ll 8~~5
8155
1-::====11
,...
I 10
RESIDENT DATA
MEMORY
1________ 1I
(64)
' - - - - - - " OOOH
SECTION
ADDRESS
DESIGNATION
PROG. MEM
DATA MEM
8155 PORTS
OOO-BFF
100-IFF
300
301
302
303
304
305
400
401
402
403
CMD/STATUS
PORTA
PORT B
PORTC
TIMER LOW
TIMER HI
PORT A
PORTB
8355 PORTS
DORA
DOR B
locations directly addressable by the pointer
registers RO and R1. These systems can be
achieved using "bank switching" techniques.
Bank switching is merely the selection of
various blocks or "banks" of memory using
dedicated output port lines from the processor.
In the case of the 8048 program memory is
selected in blocks of 4K words at a time
while data memory and I/O are enabled 256
words at a time.
In this system the various locations are addressed as follows:
Data RAM-Addresses 0 to 255 when Port
2 Bit 0 has been previously set = 1 and Bit 1
set = 0
RAM I/O-Addresses 0 to 3 when Port 2
Bit 0 = 1 and Bit 1 = 1
ROM I/O-Addresses 0 to 3 when Port 2
Bit 2 or Bit 3 = 1
The most important consideration in implementing two or more banks is the software
required to cross the bank boundaries. Each
crossing of the boundary requires that the
processor first write a control bit to an output
port before accessing memory or 1/0 in the
new bank. If program memory is being
switched, programs should be organized to
See the above memory map.
3.5 Memory Bank Switching
Certain systems may require more than the
4K words of program memory which are
directly addressable by the program counter
or more than the 256 data memory and I/O
3·10
EXPANDED MCS-48 SYSTEM
keep boundary crossings to a minimum.
Jumping to subroutines across the boundary
should be avoided when possible since the
programmer must keep track of which bank
to return to after completion of the subroutine. If these subroutines are to be nested and
accessed from either bank, a software "stack"
should be implemented to save the bank
switch bit just as if it were another bit of the
program counter.
used. The BUS port lines are either active
high, active low, or high impedance (floating).
The latched mode (INS, OUTU is intended
for use in the single chip configuration
where BUS is not being used as an expander port. OUTL and MOVX instructions can
be mixed if necessary. However, a previously latched output will be destroyed by executing a MOVX instruction and BUS will be
left in the high impedance state. INS does
not put the BUS in a high impedance state.
Therefore, the use of MOVX after OUTL to
put the BUS in a high impedance state is
necessary before an INS instruction intended to read an external word (as opposed to the previously latched value).
From a hardware standpoint bank switching
is very straight-forward and involves only the
connection of an I/O liile or lines as bank
enable signals. These enables are ANDed
with normal memory and I/O chip select
signals to activate the proper bank.
3.6 Control Signal Summary
OUTL should never be used in a system
with external program memory, since latching BUS can cause the next instruction, if
external, to be fetched improperly.
The following table summarizes the instructions which activate the various
control outputs of the MCS-48 processors.
Port 2 Operations
CONTROL
SIGNAL
WHEN ACTIVE
RD
DURING MOVX A,@R OR INS BUS
WR
DURING MOVX @R,A OR OUTL BUS
ALE
EVERY MACHINE CYCLE
PSEN
DURING FETCH OF EXTERNAL
PROGRAM MEMORY(INSTRUCTION
OR IMMEDIATE DATA)
PROG
The lower half of Port 2 can be used in three
different ways: as a quasi, bi-directional
static port, as an 8243 expander port, and to
address external program memory. In all
cases outputs are driven low by an active
device and driven high momentarily by an
active device and held high by a 50Kfl
resistor to +5V.
The port may contain latched 1/0 data prior
to its use in another mode without affecting
operation of either. If lower Port 2 (P20-3) is
used to output address for an external
program memory fetch the 1/0 information
previously latched will be automatically
removed temporarily while address is
present then restored when the fetch is
complete. However, if lower Port 2 is used
to communicate with an 8243, previously
latched 1/0 information will be removed
and not restored. After an input from the
8243 P20-3 will be left in the input mode
(floating). After an output to the 8243 P20-3
will contain the value written, ANDed, or
ORed to the 8243 port.
DURING MOVD A,P ANLD P,A
MOVD P,A ORLD P,A
During all other instructions these outputs
are driven to the inactive state.
3.7 Port Characteristics
BUS Port Operations
The BUS port can operate in three different
modes: as a latched 1/0 port, as a bidirectional bus port, or as a program memory address output when external memory is
3·11
EXPANDED MCS-48 SYSTEM
MCS-48 EXPANSION CAPABILITY
I/O
I/O
8355/8755
STANDARD
RAM
ROM I/O
2K)( 8
8049
8048
8748
8035
8039
. -_ _ _----' 000
8255
8251
8279
PPI
USART
KEYBOARD/DISPLAY
I/O
SERIAL
OUTPUT
I/O
I/O
CJ
CJ
3-12
SERIAL
INPUT
INSTRUCTION SET
4.0 INTRODUCTION
The MCS-48 microcomputers have been
designed to efficiently handle arithmetic
operations in both binary and BCD as well
as to efficiently handle the single bit
operations required in control applications.
Special instructions have also been included to simplify loop counters, table
lookup routines, and N-way branch routines.
The. MCS-48 instruction set is extensive for
a machine of its size and has been tailored
to be straightforward and very efficient in
its use of program memory. All instructions
are either one or two bytes in length and
over 70% are only one byte long. Also, all
instructions execute in either one or two
cycles (2.5J.Lsec or 5.0J.Lsec when using a 6
MHz XTAL) and over 50% of all instructions
execute in a single cycle. Double cycle
instructions include all immediate instructions, and all I/O instructions.
Data Transfers
As can be seen in the accompanying
diagram, the 8-bit accumulator is the central
i-----------l
I
I
EXPANDER
I/O PORTS
4-7
PROGRAM
MEMORY
(!tdata)
I
I
DATA
MEMORY
MOV
I
ADD
MOV
MOVP
I
MOVP3
I
I
EXTERNAL
MEMORY
AND
PERIPHERALS
,W_---=:..:,:,::-=--J.....J
ANL
ORL
8048
8049
8748
8035*
8039*
~
DATA TRANSFER INSTRUCTIONS
4-1
I
I
_ _ _ _ _ _ _ _ ---.J
*NO PROGRAM
MEMORY
INSTRUCTION SET
point for all data transfers within the 8048.
Data can be transferred between the 8
registers of each working register bank and
the accumulator directly, i.e. the source or
destination register is specified by the
instruction. The remaining locations of the
internal RAM array are referred to as Data
Memory and are addressed indirectly via an
address stored in either RO or R1 ofthe active
working register bank. RO and R1 are also
used to indirectly address external data
memory when it is present. Transfers to and
from internal RAM require one cycle while
transfers to external RAM require two.
Constants stored in Program Memory can be
loaded directly to the accumulator and to the
8 working registers. Data can also be
transfered directly between the accumulator
and the on-board timer/counter or the
accumulator and the Program Status word
(PSW). Writing to the PSW alters machine
status accordingly and provides a means of
restoring status after an interrupt or of
altering the stack pointer if necessary.
Finally, the accumulator can be: incremented. decremented, cleared, or complemented and can be rotated left or right 1-bit at
a time with or without carry.
Although there is no subtract instruction in
the 8048, this operation can be easily
implemented with three single-byte singlecycle instructions.
A value may be subtracted from the
accumulator with the result in the accumulator by:
Complementing the accumulator
Adding the value to the accumulator
Complementing the accumulator.
Register Operations
The working registers can be accessed via
the accumulator as explained above, or can
be loaded immediate with constants from
program memory. In addition, they can be
incremented or decremented or used as
loop counters using the decrement and
jump, if not zero instruction, as explained
under branch instructions.
Accumulator Operations
All Data Memory including working registers
can be accessed with indirect instructions via
RO and R1 and can be incremented.
Immediate data, data memory, or the
working registers can be added with or
without carry to the accumulator. These
sources can also be ANDed, ORed, or
Exclusive ORed to the accumulator. Data
may be moved to or from the accumulator
and working registers or data memory. The
two values can also be exchanged in a single
operation.
Flags
There are four user accessible flags in the
8048: Carry, Auxiliary Carry, FO, and F1.
Carry indicates overflow of the accumulator,
and Auxiliary Carry is used to indicate
overflow between BCD digits and is used
during decimal adjust operation. Both Carry
and Auxiliary Carry are accessible as part of
the program status word and are stored on
the stack during subroutines. FO and F1 are
undedicated general purpose flags to be
used as the programmer desires. Both flags
can be cleared or complemented and tested
by conditional jump instructions. FO is also
accessible via the Program Status word and
is stored on the stack with the carry flags.
In addition, the lower 4 bits of the
accumulator can be exchanged with the
lower 4-bits of any of the internal RAM
locations. This instruction, along with an
instruction which swaps the upper and lower
4-bit halves of the accumulator, provides for
easy handling of 4-bit quantities, including
BCD numbers. To facilitate BCD arithmetic,
a Decimal Adjust instruction is included. This
instruction is used to correct the result of the
binary addition of two tWO-digit BCD
numbers. Performing a decimal adjust on the
result in the accumulator produces the
required BCD result.
Branch Instructions
The unconditional jump instruction is two
bytes and allows jumps anywhere in the first
4-2
INSTRUCTION SET
2K words of program memory. Jumps to the
second 2K of memory (4K words are directly
addressible) are made by first executing a
select memory bank instruction then executing the jump instruction. The 2K boundary
can only be crossed via a jump or subroutine
call instruction i.e. the bank switch does not
occur until a jump is executed. Once a
memory bank has been selected all subsequent jumps will be to the selected bank until
another select memory bank instruction is
executed. A subroutine in the opposite bank
can be accessed by a select memory bank
instruction followed by a call instruction.
Upon completion of the subroutine execution will automatically return to the original
bank; however, unless the original bank is
reselected, the next jump instruction encountered will again transfer execution to the
opposite bank.
several different locations based on the
contents of the accumulator. The contents of
the accumulator points to a location in
program memory which contains the jump
address. The 8-bit jump address refers to the
current page of execution. This instruction
could be used, for instance, to vector to any
one of several routines based on an ASCII
character which has been loaded in the
accumulator. In this way ASCII key inputs
can be used to initiate various routines.
Subroutines
Subroutines are entered by executing a call
instruction. Calls can be made like unconditional jumps to any address in a 2K word
bank and jumps across the 2K boundary are
executed in the same manner. Two separate
return instructions determine whether or not
status (upper 4-bits of PSW) is restored upon
return from the subroutine.
Conditional jumps can test the following
inputs and machine status:
The return and restore status instruction also
signals the end of an interrupt service routine
if one has been in progress.
TO Input pin
T1 Input pin
INT Input pin
Accumulator Zero
Any bit of Accumulator
Carry Flag
FO Flag
F1 Flag
Timer Instructions
The 8-bit on board timer/counter can be
loaded or read via the accumulator while the
counter is stopped or while counting. The
counter can be started as a timer with an
internal clock source or as an event counter
or timer with an external clock applied to the
T1 input pin. The instruction executed
determines which clock source is used. A
single instruction stops the counter whether
it is operating with an internal or an external
clock source. In addition, two instructions
allow the timer interrupt to be enabled or
disabled.
Conditional jumps allow a branch to any
address within the current page (256 words)
of execution. The conditions tested are the
instantaneous values at the time the conditional jump is executed. For instance, the
jump on accumulator zero instruction tests
the accumulator itself not an intermediate
zero flag.
The decrement register and jump if not zero
instruction combines a decrement and a
branch instruction to create an instruction
very useful in implementing a loop counter.
This instruction can designate anyone of
the 8 working registers as a counter and can
effect a branch to any address within the
current page of execution.
Control Instructions
Two instructions allow the external interrupt
source to be enabled or disabled. Interrupts
are initially disabled and are automatically
disabled while an interrupt service routine is
in progress and re-enabled afterward.
There are four memory bank select instructions, two to designate the active working
register bank and two to control program
A single byte indirect jump instruction allows
the program to be vectored to anyone of
4-3
INSTRUCTION SE;T
responding READ or WRITE pulse is
generated and data is valid only at that time.
When data is not being transferred BUS is in
a high impedance state.
memory banks. The operation of the program
memory bank switch is explained in section
3.1.2. The working register bank switch
instructions allow the programmer to immediately substitute a second 8 register working
register bank for the one in use. This
effectively provides 16 working registers or it
can be used as a means of quickly saving the
contents of the registers in response to an
interrupt. The user has the option to switch or
not to switch banks on interrupt. However, if
the banks are switched, the original bank will
be automatically restored upon execution of
a return and restore status instruction at the
end of the. interrupt service routine.
The basic three on board I/O ports can be
expanded via a 4-bit expander bus using half
of port 2. I/O expander devices on this bus
consist of four 4-bit ports which are
addressed as ports 4 through 7. These ports
have their own AND and OR instructions like
the on board ports as well as move
instructions to transfer data in or out. The
expander AND and OR instructions, however, combine the contents of accumulator with the selected port rather than
immediate data as is done with the on board
ports.
A special instruction enables an internal
clock, which is the XTAL frequency divided
by three, to be output on pin TO. This clock
can be used as a general purpose clock in the
users system. This instruction should be
used only to initialize the system since the
clock output can be disabled only by
application of system reset.
I/O devices can also be added externally
using the BUS port as the expansion bus. In
this case the I/O ports become "memory
mapped", i.e. they are addressed in the same
way as external data memory and exist in the
external data memory address space addressed by pointer register RO or R1.
Input/Output Instructions
4.1 Instruction Set Description
Ports 1 and 2 are 8-bit static I/O ports which
can be loaded to and from the accumulator.
Outputs are statically latched but inputs are
not latched and must be read while inputs are
present. In addition, immediate data from
program memory can be ANDed or ORed
directly to Port 1 and Port 2 with the result
remaining on the port. This allows "masks"
stored in program memory to selectively set
or reset individual bits of the I/O ports. Ports 1
and 2 are configured to allow input on a given
pin by first writing a "1" out to the pin.
The following pages describe the MCS-48
instruction set in detail. The instruction set is
first summarized with instructions grouped
functionally. This summary page is followed
by a detailed description listed alphabetically
by mnemonic opcode.
The alphabetical listing includes the following information:
Mnemonic
Machine Code
Verbal Description
Symbolic Description
Assembly Language Example
An 8-bit port called BUS can also be
accessed via the accumulator and can have
statically latched outputs as well. It too can
have immediate data ANDed or ORed
directly to its outputs, however, unlike ports 1
and 2, all eight lines of BUS must be treated
as either input or output at anyone time. In
addition to being a static port, BUS can be
used as a true synchronous bi-directional
port using the Move External instructions
used to access external data memory. When
these instructions are executed a cor-
The machine code is represented with the
most significant bit (7) to the left and two byte
instructions are represented with the first
byte on the left. The assembly language
examples are formulated as follows:
Arbitrary
Label: Mnemonic, Operand;
Descriptive Comment
See section 1.2.2 for a description and
example of an assembly language program.
4·4
8048/8049
INSTRUCTION SET SUMMARY
Mnemonic
Bytes
Description
Cycle
Mnemonic
Description
Bytes
Cycles
~
ADD A, R
ADD A,@R
ADD A, #data
ADDC A, R
ADDC A,@R
ADDC A, #data
ANL A, R
ANL A, @R
ANL A, "data
O<1LA, R
g ORL A, @R
.!!
ORL A, #data
~
E XRLA, R
~
u
u XRL A, @R
XRLA, #data
INCA
DECA
CLR A
CPLA
DAA
SWAP A
RLA
RLCA
RR A
RRCA
«
;;Q.
;;
~
Q.
.:
~
Ii
1;;
'~
a:
~
u
c
=
ell
Add reg ister to A
Add data memory to A
Add
Add
Add
Add
immediate to A
register with carry
2
data memory with carry
immediate with carry
1
e
..c
~
2
CLR C
CPLC
CLR FO
.!!
u. CPL FO
CLR F1
CPL F1
2
1
And data memory to A
1
And immediate to A
Or register to A
Or data memory to A
Or immediate to A
Exclusive Or register to A
Exclusive or data memory to A
2
Exclusive or immediate to A
2
Increment A
Decrement A
1
~
'"
2
1
2
1
1
2
Complement A
Decimal Adjust A
Swap nibbles of A
Rotate A left
Rotate A left through carry
Rotate A right
Rotate A right through carry
INCR
INC@R
DEC R
Increment register
I ncrement data memory
Decrement register
Input port to A
Output A to port
And immediate to port
Or immediate to port
2
2
I nput BUS to A
Output A to BUS
1
Jump unconditional
Jump indi~ect
Decrement register and jump
Jump 0" Carry = 1
Jump on Carry = 0
Jump on A Zero
Jump on A not Zero
Jump
Jump
Jump
Jump
Jump
Jump
on
on
on
on
on
on
TO
TO
T1
Tl
FO
Fl
~
~
~
~
~
~
1
0
1
0
1
1
Jump on timer flag =1
Jump on INT
~
0
Jump on Accumulator Bit
2
Return and restore status
2
2
2
2
2
Complement Flag 1
2
2
2
2
2
2
2
2
2
2
2
2
Move
Move
Move
Move
Move
Move
Move
MOV A, T
MOV T, A
STRTT
~
0
~ STRT CNT
Ii STOP TCNT
E
i= EN TCNTI
DISTCNTI
Read Timer/Counter
Load Timer/Counter
~
0
u
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Complement Carry
Clear Flag 0
Complement Flag 0
Clear Flag 1
MOV A, R
MOV A,@R
MOV A, #data
MOV R, A
MOV@R,A
MOV R, #data
i;'! MOV@R,#data
>
0
:;: MOV A, PSW
MOV PSW, A
~
C XCH A, R
XCHA,@R
XCHD A,@R
MOVX A,@R
MOVX@R,A
MOVPA,@A
MOVP3 A,@A
e1:
2
Clear Carry
2
Clear A
And immediate to BUS
Or immediate to BUS
Input Expander port to A
Output A to Expander port
And A to Expander port
Or A to Expander port
Jump to subroutine
Return
V>
And register to A
IN A, P
OUTL P, A
ANL P, #data
ORL P, #data
INS A, BUS
OUTL BUS, A
ANL BUS, #data
OR L BUS, #data
MOVD A, P
MOVD P, A
ANLD P, A
ORLD P, A
JMP addr
JMPP@A
DJNZ R, addr
JC addr
JNC addr
J Z addr
JNZ addr
JTO addr
JNTO addr
JT1 addr
JNT1 addr
JFO addr
JF 1 addr
JTF addr
JNI addr
JBb addr
c CALL addr
RET
RETR
'§
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
EN I
DIS I
SEL RBO
SEL RBl
SEL MBO
SEL MBl
ENTO CLK
NOP
Mnemonics copyright Intel Corporation 1976,
4·5
register to A
data memory to A
immediate to A
A to register
A to data memory
immediate to register
immed late to data memory
1
2
2
2
2
2
2
Move PSW to A
Move A to PSW
Exchange A and register
Exchange A and data memory
Exchange nibble of A and register
Move external data memory to A
Move A to external data memory
Move to A from cu rrent page
Move to A from Page 3
Start Timer
Start Counter
Stop Timer/Counter
Enable Timer/Counter Interrupt
Disable Timer/Counter Interrupt
Enable external interrupt
Disable external interrupt
Select register bank 0
Select register bank 1
Select memory bank 0
Select memory bank 1
Enable Clock output on TO
No Operation
2
2
2
2
8021
INSTRUCTION SET SUMMARY
Mnemonic
~
:;
E
~
u
u
«
',;
.'l~
..,
0
~
Co
!;
A,R
ADD
A,@R
ADD
ADD
A.#data
ADDC A,R
ADDC A,@R
ADDC A,#data
ANL
A,R
A,@R
ANL
ANL
A, #data
ORL
A,R
A,@R
ORL
ORL
A,#data
XRL
A,R
A,@R
XRL
XRL
A,#dat8
INC
A
DEC
A
CLR
A
CPL
A
A
DA
SWAP A
RL
A
A
RLC
RR
A
RRC
A
Description
Bytes
Add register to A
Add data memory to A
Add immediate to A
Add
Add
Add
And
Cycle
.<:
u
c
E
2
2
1
And data memory to A
1
1
'"
And immediate to A
2
Or register to A
Or data memory to A
Or immediate to A
1
1
1
.g
~
2
~
e
Exclusive Or register to A
.c
Exclusive or data memory to A
Exclusive or immediate to A
Increment A
Decrement A
Clear A
Complement A
Decimal Adjust A
Swap nibbles of A
Rotate A left
Rotate A left through carry
Rotate A right
Rotate A right through carry
IN
OUTL
MOVD
MOVD
ANLD
ORLD
A,P
P,A
A,P
P,A
P,A
P,A
I nput port to A
Output A to port
Input Expander port to A
Output A to Expander port
And A to Expander port
Or A to Expander port
INC
INC
R
@R
Increment register
Increment data memory
~
~
Decrement register and Jump
2
2
2
2
addr
addr
addr
on R
Jump
Jump
Jump
Jump
Jump
Jump
Jump
CALL
RET
addr
CLR
CPL
C
C
Clear Carry
Complement Carry
MOV
MOV
MOV
MOV
MOV
MOV
MOV
XCH
XCH
XCHD
MOVP
A,R
A,@R
R,A
@R,A
R,#data
@R,#data
A,R
A,@R
A,@R
A,@A
Move register to A
Move data memory to A
Move immediate to A
Move A to register
Move A to data memory
Move immediate to register
Move immediate to data memory
Exchange A and register
Exchange A and data memory
Exchange nibble of A and register 1
Move to A from cu rrent page
1
MOV
MOV
STRT
STRT
STOP
A,T
T,A
T
CNT
TCNT
Read Timer/Counter
Load Timer/Counter
Start Timer
Start Counter
Stop Timer/Counter
addr
addr
addr
addr
not zero
on Carry = 1
on Carry""
on A Zero
on A not Zero
on Tl '" 1
on Tl =- 0
on timer flag
ri'
ii:
~
>
0
:;
!!
0
2
2
2
2
~
c
~
0
~
~
E
;:
a:
A,#data
NOP
2
2
2
2
2
2
2
2
2
Jump to subroutine
2
Return
1
2
2
No Operation
Instruction Set - The following instructions, which are
found in the 8748, have been deleted from the 8021
instruction set.
Data Moves
A,PSW
PSW,A
MOVX A,@R
MOVX @R,A
MOVP3 A,@A
MOV
MOV
1
a
2
2
2
2
2
en
~
....~
Cycle
2
JC
JNC
JZ
JNZ
JT1
JNT1
JTF
2
1
1
Bytes
Jump unconditional
Jump indirect
addr
@A
R,addr
1
1
with carry
with carry
with carry
register to A
Description
Mnemonic
JMP
JMPP
DJNZ
Registers
DEC R
I--Flags
~
CPl FO
CLR Fl
CPL Fl
Branch
JTO
addr
JNTO addr
JFO addr
JFl
addr
JNI
addr
JBb addr
Timer
TCNTI
DIS TCNTI
EN
Subroutine
RETR
Control
EN
DIS
SEL
SEL
SEL
SEL
I
I
RBO
RBl
MBa
MBl
Input/Output
P,#data
P,#data
A,BUS *
OUTl BUS,A *
ANL BUS,#data
ORL BUS,#data
ANL
ORL
INS
ENTO ClK
"These Instructions have been replaced in the 8021 by
IN A,PO and OUTL PO,A respectively.
4-6
2
1
1
2
2
,
2
1
2
8022
INSTRUCTION SET SUMMARY
Mnemonic
Description
ADD A,R r
ADD A,@R
ADD A,#dala
AD DC A,R r
ADDC A,@R
Add register to A
Bytes
Cycle
Hexadecimal
Opcode
68,6F
60-61
03
78-7F
70-71
Add data memory to A
Add immediate 10 A
Add register with carry
Add data 'memory with
JTO
JNTO
JTl addr
JNTl addr
JTF addr
carry
ADDC A,#data Add immediate with
carry
ANL A,R r
And register to A
And data memory to A
ANL A,@R
ANL A,#data
And immediate to A
ORL A,R r
Or register to A
ORL A,@R
Or data memory to A
ORL A,#data Or immediate to A
XRL A,R r
Exclusive Or register
~
to A
E
~
XRL
A,@R
Exclusive Or data
u
58-SF
50-51
53
4B-4F
40-41
43
DB-OF
'"
03
XRL A,#data
c
RR A
RRC A
Clear A
Complement A
Decimal adjust A
Swap nibbles of A
Rotate A left
Rotate A left through
carry
Rotate A right
CALL addr
Jump to subroutine
RET
Return
14,34,54,74
94,B4,D4,F4
83
III
0
01 CLR C
.!! CPL C
"-
Clear carry
Complement carry
MOV A,R r
MOV A,@R
MOV A,#data
MOV Rr,A
MOV@R,A
MOV R r . # data
lk
97
A7
Move register to A
Move data memory to A
Move immediate to A
Move A to register
Move A to data memory
Move immediate to
register
Move immediate to
data memory
Exchange A and
register
F8-FF
FO-Fl
23
A8-AF
AQ-Al
BS-SF
XCH A,@R
Exchange A and data
20-21
XCHD a,@R
memory
Exchange nibble of A
and register
30-31
0
~
~ MOV@R,#data
:I
~
'iii XCH A, Rr
Q
MOVPA,@A
BO-Bl
28-2F
Move to A from current
page
A3
MOV A,T
MOV T,A
T
!:: STRT
~ STRT CNT
STOP TCNT
Read timer I counter
Load timer I counter
Start timer
42
62
55
45
65
~ RAD
80
SEL ANl
Move conversion result
register to A
Select analog input
zero
Select analog input one
EN I
Enable external
05
DIS I
RET I
Disable external
interrupt
Enable timer / counter
interrupt
Disable timer / counter
interrupt
Return from interrupt
93
NOP
No operation
00
77
67
Rotate A right through
Ope ode
36
26
56
46
16
~
17
07
27
37
57
47
E7
F7
Increment A
Decrement A
Cycle
Jump on T1 =0
Jump on timer flag
.g
to A
INC A
DEC A
CLR A
CPL A
DA A
SWAP A
RL A
RLC A
Bytes
Jump on TO=l
Jump on TO=O
Jump on Tl=l
:;
00-01
memory to A
Exclusive Or immediate
Description
~
13
~
u
Hexadecimal
Mnemonic
carry
;;
~
IN A, Pp
OUTL PpA
MOVD A,P p
~ MOVD Pp.A
;;
.
= ANLD Pp.A
ORLD Pp,A
Input port to A
S
c
08,09,OA
90,39,3A
OC-OF
Output A to port
Input expander port
~
0
3C-3F
~
9C-9F
BC-SF
1:
~
>
c
to A
Output A to expander
port
And A to expander port
Or A to expander port
0
SEL ANO
U
~
Q
INC Rr
';;, INC@R
~
a:
.c
u
c
~
85
95
interrupt
JMP addr
Jump unconditional
JMPP@ A
DJNZ R,addr
Jump indirect
Decrement register and
jump on R not zero
Jump on carry= 1
Jump on carry=O
Jump on A zero
Jump on A not zero
JC addr
JNC addr
JZ addr
JNZ addr
;,
lB-1F
10-11
Increment register
Increment data memory
Start counter
Stop timer / counter
04,24,44,64,
84,A4,C4,E4
B3
ES-EF
a
j
=
F6
E6
C6
96
EN TCNTI
DIS TCNTI
Mnemonics copyright Intel Corporation, 1978_
Instruction Set - The following instructions, which are
found in the 8748, have been deleted from the 8022
instruction set.
Data Moves
MOV
MOV
MOVX
MOVX
MOVP3
A,PSW
PSW,A
A,@A
@R,A
A,@A
Ragisters
Control
Branch
DEC R
r-Flags
~
CPl FO
CLR F1
CPL F1
JFO
JF1
JNI
JBb
addr
addr
addr
addr
Subroutine
RETR
SEL
SEL
SEL
SEL
ENTO
ABO
RBl
MBO
MBl
ClK
Input/Output
ANL
ORL
INS
OUTL
ANL
ORL
P,#data
P,#data
A,BUS *
BUS,A *
BUS,#data
BUS,#data
-These Instructions have been replaced in the 8022 by
IN A,PO and OUTL PO,A respectively,
4-7
15
25
35
MCS-48™ INSTRUCTION SET
SYMBOLS AND ABBREVIATIONS USED
A
Accumulator
AC
addr
Auxiliary Carry
12-Bit Program Memory Address
Bb
Bit Designator (b=0-7)
BS
Bank Switch
BUS
C
BUS Port
Carry
ClK
Clock
CNT
Event Counter
CRR
D
Conversion Result Register
Mnemonic for 4-Bit Digit (Nibble)
data
8-Bit Number or Expression
DBF
Memory Bank Flip-Flop
FO, F1
Flag 0, Flag 1
Interrupt
I
Mnemonic for "in-page" Operation
P
PC
Pp
PSW
Rr
Register Designator (r=O, 1 or 0-7)
SP
Stack Pointer
T
Timer
TF
Timer Flag
TO, T1
Test 0, Test 1
X
Mnemonic for External RAM
#
Immediate Data Prefix
Program Counter
Port Designator (p=1, 2 or 4-7)
Program Status Word
@
Indirect Address Prefix
$
Current Value of Program Counter
(X)
Contents of X
((X))
Contents of location Addressed by X
Is Replaced by
Mnemonics copyright Intel Corporation 1976.
4-8
INSTRUCTION SET
ADD A,R r Add Register Contents to Accumulator
1011011rrri
The contents of register 'r' are added to the
accumulator. Carry is affected.
Example:
(A) .... (A) + (Rr)
r=0-7
ADDREG: ADD A,R6
;ADD REG 6 CONTENTS
;TO ACC
ADD A,@R r Add Data Memory Contents to Accumulator
101101000ri
The contents of the resident data memory location
addressed by register 'r' bits 0-5*are added to
the accumulator. Carry is affected.
Example:
(A) ..... (A) + ((Rr))
r=0-1
ADDM: MOV RO, #01 FH
ADD A, @RO
;MOVE '1 F' HEX TO REG 0
;ADD VALUE OF LOCATION
;31 TO ACC
ADD A,#data
Add Immediate Data to Accumulator
100 0 0 10 0 1 11
Id7 d6 ds d4 I d3 d2 d1 do I
This is a 2-cycle instruction. The specified data
is added to the accumulator. Carry is affected
(A) .... (A) + data
Example:
ADDID: ADD A,#ADDER: ;ADD VALUE OF SYMBOL
;'ADDER' TO ACC
ADDC A,R r Add Carry and Register Contents to Accumulator
1011111rrri
The content of the carry bit is added to accumulator
location 0 and the carry bit cleared. The contents
of register 'r' are then added to the accumulator.
Carry is affected.
Example:
(A) .... (A)+(Rr)+(C)
r=0-7
ADDRGC: AD DC A,R4
;ADD CARRY AND REG 4
;CONTENTS TO ACC
Mnemonics copyright Intel Corporation 1976.
'0-6 for 8039/8049
4-9
INSTRUCTION SET
ADDC A,@R r Add Carry and Data Memory Contents to Accumulator
101111 0 0 0r i
The content of the carry bit is added to accumulator
location 0 and the carry bit c;:leared. Then the contents
of the resident data memory location aqdressed by
register Or' bits 0-5*are added to the accumulator.
Carry is affected.
Example:
(A) ... (A)+«Rr))+(C)
r=0-1
ADDMC: MOV R1,#40
AD DC A,@R1
;MOVE '40' DEC TO REG 1
;ADD CARRY AND LOCATION 40
;CONTENTS TO ACC
AD DC A,#data
Add Carry and Immediate Data to Accumulator
I0 0 0 1 I 0 0 1 1 I Id7 de d5 d4 I d3 d2 d1 do I
This is a 2-cycle instruction. The content of the
carry bit is added to accumulator location 0 and
the carry bit cleared. Then the specified data is
addec;l to the accumulator. Carry is affected.
(A)-- (A)+data+(C)
Example:
ANL A,R r
ADDC A,#225
;ADD CARRY AND '225' DEC
;TO ACC
Logical AND Accumulator With Register Mask
1010111rrri
Data in the accumulator is logically ANDed with the
mask contained in working register or'.
Example:
ANL A,@R r
(A) -- (A) AND (Rr)
r=0-7
ANDREG: ANL A,R3
;'AND' ACC CONTENTS WITH MASK
;IN REG 3
Logical AND Accumulator With Memory Mask
101011 000r
i
Data in the accumulator is logically ANDed with the
mask contained in the data memory location referenced
by register or', bits 0-5~
(A)-- (A) AND «Rr))
Example:
r=0-1
ANDDM: MOV RO,#03FH ;MOVE '3F' HEX TO REG 0
ANL A, @RO
;'AND' ACC CONTENTS WITH
;MASK IN LOCATION 63
. '0-6 for 8039/8049
Mnemonics copyright Intel Corporation 1976.
4-10
INSTRUCTION SET
ANL A,#data
Logical AND Accumulator With Immediate Mask
I0 1 0 1 I 0 0 1 1 I
1d7 d6 ds d4 1 d3 d2 d1 do 1
This is a 2-cycle instruction. Data in the accumulator
is logically ANDed with an immediately-specified mask.
(A)-- (A) AND data
Examples: ANDID: ANL A,#OAFH
;'AND' ACC CONTENTS
;WITH MASK 10101111
;'AND' ACC CONTENTS
;WITH VALUE OF EXP
;'3+X/Y'
ANL A,#3+X/Y
ANL BUS,#data
Logical AND BUS With Immediate Mask (Not in 8021, 8022)
11 0 0 1 11 0 0 0 1
1d7 d6 ds d4 1 d3 d2 d1 do
I
This is a 2-cycle instruction. Data on' the BUS port is
logically ANDed with an immediately-specified mask. This
instruction assumes prior specification of an 'OUTL
BUS, A' instruction.
(BUS) -- (BUS) AND data
Example:
ANDBUS: ANL BUS, #MASK ;'AND' BUS CONTENTS
;WITH MASK EQUAL VALUE
;OF SYMBOL 'MASK'
ANL Pp,#data
Logical AND Port 1-2 With Immediate Mask (Not in 8021,8022)
11 00 1 11 0 P P
I Id7 d6 ds d4 I d3 d2 d1 do I
This is a 2-cycle instruction. Data on port 'p' is
logically ANDed with an immediately-specified mask.
Example:
ANLD Pp,A
(Pp)-- (Pp) AND data
p=1-2
ANDP2: ANL P2,#OFOH
;'AND' PORT 2 CONTENTS
;WITH MASK 'FO' HEX
; (CLEAR P20-23)
Logical AND Port 4-7 With Accumulator Mask
11001111ppl
This is a 2-cycle instruction. Data on port 'p' is
logically ANDed with the digit mask contained in
accumulator bits 0-3.
\
(Pp)-- (Pp) AND (AO-3) p=4-7
Mnemonics copyright Intel Corporation 1976.
4-11
INSTRUCTION SET
Note: The mapping of port 'p' to opcode bits 0-1
is as follows:
1 0
Port
o0
4
015
1 0
6
1 1
7
Example:
ANDP4: ANLD P4,A
CALL address
;'AND' PORT 4 CONTENTS
;WITH ACC BITS 0-3
Subroutine Call
la10a9as1101001
la7asa5a41a3a2a1aol
This is a 2-cycle instruction. The program counter and
PSW bits 4-7 are saved in the stack. The stack pOinter
(pSW bits 0-2) is updated. Program control is then
passed to the location specified by 'address'. PC
bit 11 is determined by the most recent SEL MB instruction.
A CALL cannot begin in locations 2046-2047 or 4094-4095.
Execution continues at the instruction following the
CALL upon return from the subroutine.
((SP)) .... (PC), (PSW 4-7)
(SP) .... (SP)+1
(PCS-10) .... (addrS-10)
(PCO-7) .... addrO-7
(PC 11 ) .... DBF
Example:
Add three groups of two numbers. Put subtotals in
locations 50, 51 and total in location 52.
MOV RO,#50
;MOVE '50' DEC TO ADDRESS
;REG 0
BEGADD: MOV A,R1
;MOVE CONTENTS OF REG 1
;TO ACC
ADD A,R2
;ADD REG 2 TO ACC
CALL SUBTOT;CALL SUBROUTINE 'SUBTOT'
ADD A R3
;ADD REG 3 TO ACC
ADD A,R4
;ADD REG 4 TO ACC
CALL SUBTOT ;CALL SUBROUTINE 'SUBTOT'
ADD A,R5
;ADD REG 5 TO ACC
ADD A,R6
;ADD REG 6 TO ACC
CALL SUBTOT ;CALL SUBROUTINE 'SUBTOT'
SUBTOT: MOV @RO,A
INC RO
RET
;MOVE CONTENTS OF ACC TO
;LOCATION ADDRESSED BY
;REG 0
;INCREMENT REG 0
;RETURN TO MAIN PROGRAM
Mnemonics copyright Intel Corporation 1976.
4-12
INSTRUCTION SET
CLR A Clear Accumulator
10010101111
The contents of the accumulator are cleared to zero.
A.-O
CLR C
Clear Carry Bit
11001101111
During normal program execution, the carry bit can
be set to one by the ADD, ADDC, RLC, CPL C, RRC, and
DAA instructions. This instruction resets the carry bit to zero.
C.-O
CLR F1
Clear Flag 1 (Not in 8021,8022)
1 1010 101011
Flag 1 is cleared to zero.
(F1)'- 0
CLR FO
Clear Flag 0
(Not in 8021, 8022)
11 00 0 101011
Flag 0 is cleared to zero.
(FO).- 0
CPL A Complement Accumulator
10011101111
The contents of the accumulator are complemented.
This is strictly a one's complement. Each one is
changed to zero and vice-versa.
(A).- NOT (A)
Example:
CPL C
Assume accumulator contains 01101010.
CPLA: CPL A
;ACC CONTENTS ARE COMPLE;MENTED TO 10010101
Complement Carry Bit
11010 101111
The setting of the carry bit is complemented; one is
changed to zero, and zero is changed to one.
(C).- NOT (C)
Example:
Set C to one; current setting is unknown.
CT01: CLR C
;C IS CLEARED TO ZERO
CPL C
;C IS SET TO ONE
Mnemonics copyright Intel Corporation 1976.
4-13
INSTRUCTION SET
CPL FO
Complement Flag 0
(Not in 8021,8022)
11001101011
The setting of flag 0 is complemented; one is
changed to zero, and zero is changed to one.
FO.... NOT (FO)
CPL F1
Complement Flag 1
(Not in 8021,8022)
11011101011
The setting of flag 1 is complemented; one is
changed to zero, and zero is changed to one.
(F1)-- NOT (F1)
DA A
Decimal Adjust Accumulator
10101 101111
The 8-bit accumulator value is adjusted to form two
4-bit Binary Coded Decimal (BCD) digits following
the binary addition of BCD numbers. The carry bit
C is affected. If the contents of bits 0-3 are
greater than nine, or if AC is one, the accumulator
is incremented by six.
The four high-order bits are then checked. If bits
4-7 exceed nine, or if C is one, these bits are
increased by six. If an overflow occurs, C is
set to one.
I
Example:
DEC A
Assume accumulator contains 10011011.
DA A
;ACC ADJUSTED TO 00000001
;WITH C SET
C AC 7
4 3
0
o 010011011
o1 10
ADD SIX TO BITS 0-7
o 010100001
o1 1 0
ADD SIX TO BITS 4-7
0 0 0 0 0 0 0 0 1
OVERFLOW TO C
1
Decrement Accumulator
10000101111
The contents of the accumulator are decremented by one.
(A) __ (A)-1
Mnemonics copyright Intel Corporation 1976.
4·14
INSTRUCTION SET
Example:
DEC Rr
Decrement contents of external data memory location 63.
MOV RO,#3FH
;MOVE '3F' HEX TO REG 0
MOVX A,@RO
;MOVE CONTENTS OF LOCATION 63
;TO ACC
DEC A
;DECREMENT ACC
;MOVE CONTENTS OF ACC TO
MOVX @RO,A
;LOCATION 63 IN EXPANDED
;MEMORY
Decrement Register
(Not in 8021, 8022)
1110011rrri
The contents of working register 'r' are decremented
by one.
Example:
DIS I
(Rr)-- (Rr)-1
r=0-7
DECR1: DEC R1
;DECREMENT CONTENTS OF REG 1
Disable External Interrupt
(Not in 8021)
10001101011
External interrupts are disabled. A low signal on
the interrupt input pin has no effect.
DIS TCNTI
Disable Timer/Counter Interrupt
(Not in 8021)
10011101011
Timer/counter interrupts are disabled. Any pending
timer interrupt request is cleared. The interrupt
sequence is not initiated by an overflow, but the
timer flag is set and time accumulation continues.
DJNZ Rrl address
Decrement Register and Test
11 1 1 0 11 r r r 1
1a7 a6 a5 a4 1a3 a2 a1 ao 1
This is a 2-cycle instruction. Register 'r' is
decremented and tested for zero. If the register
contains all zeros, program control falls through
to the next instruction. If the register contents
are not zero, control jumps to the specified 'address'.
The address in this case must evaluate to 8-bits, that
is, the jump must be to a location within the current
256-location page.
(Rr)-- (Rr)-1
If Rr not 0
(PCO-7)-- addr
r=0-7
Mnemonics copyright Intel Corporation 1976.
4·15
INSTRUCTION SET
Note: A 12-bit address specification does not cause an
error if the DJNZ instruction and the jump target are
on the same page. If the DJNZ instruction begins in
location 255 of a page, it must jump to a target
address on the following page.
Example:
EN I
Increment values in data memory locations 50-54.
MOV RO,#50
;MOVE '50' DEC TO ADDRESS
;REG 0
MOV R3,#5
;MOVE '5' DEC TO COUNTER
;REG 3
INCRT: INC @RO
;INCREMENT CONTENTS OF
;lOCATION ADDRESSED BY
;REG 0
INC RO
;INCREMENT ADDRESS IN REG 0
DJNZ R3, INCRT ;DECREMENT REG 3 - JUMP TO
;'INCRT' IF REG 3 NONZERO
NEXT ;'NEXT' ROUTINE EXECUTED
;IF R3 IS ZERO
Enable External Interrupt
(Not in 8021)
10000101011
External interrupts are enabled. A low signal on
the interrupt input pin initiates the interrupt
sequence.
EN TCNTI
Enable Timer/Counter Interrupt
(Not in 8021)
10010101011
Timer/counter interrupts are enabled. An overflow
of the timer/counter initiates the interrupt sequence.
ENTO ClK
Enable Clock Output
(Not in 8021,8022)
10111101011
The test 0 pin is enabled to act as the clock output.
This function is disabled by a system reset.
Example:
IN A,Pp
EMTSTO: ENTO ClK
;ENABlE TO AS CLOCK OUTPUT
Input Port or Data to Accumulator
10000110ppi
This is a 2-cycle instruction. Data present on port 'p'
is transferred (read) to the accumulator. In the 8021
IN A,P2 inputs P20-P23 to AO-A3 while A4-A7 is set
to zero.
(A).-. (Pp)
p=1-2
Mnemonics copyright Intel Corporation 1976.
4-16
INSTRUCTION SET
Example:
INP12: IN A,P1
;INPUT PORT 1 CONTENTS
;TO ACC
;MOVE ACC CONTENTS TO
;REG 6
;INPUT PORT 2 CONTENTS
;TO ACC
;MOVE ACC CONTENTS TO REG 7
MOV R6,A
IN A,P2
MOV R7,A
INC A
Increment Accumulator
10001101111
The contents of the accumulator are incremented
by one.
(A)-- (A)+1
Example:
INC Rr
Increment contents of location 100 in external
data memory.
INCA: MOV RO,#100
;MOVE '100' DEC TO ADDRESS
;REG 0
MOVX A,@RO
;MOVE CONTENTS OF LOCATION
;100 TO ACC
INC A
;INCREMENT A
MOVX @RO,A
;MOVE ACC CONTENTS TO
;LOCATION 100
Increment Register
1000111rrri
The contents of working register Or' are incremented
by one.
Example:
INC @R r
(Rr)-- (Rr)+1
r=0-7
INCRO: INC RO
;INCREMENT ADDRESS REG 0
Increment Data Memory Location
100011000ri
The contents of the resident data memory location
addressed by register Or' bits 0-5*are incremented
by one.
Example:
((Rr))-- ((Rr))+1
r=0-1
INCDM: MOV R1,#03FH
INC @R1
;MOVE ONES TO REG 1
;INCREMENT LOCATION 63
'0-6 .Ior 8039/8049
Mnemonics copyright Intel Corporation 1976.
4-17
INSTRUCTION SET
IN A,PO
I"puto' Port 0 Data to Accumulator
Same as INS A,BUS except no
INS A,BUS
(8021, 8022 Only)
RD pulse generated.
Strobed I"put of BUS Data to Accumulator
10000110001
This is a 2-cycle instruction. Data present on the
BUS port is transferred (read) to the accumulator
when the RD pulse is dropped. (Refer to section on
programming memory expansion for details).
(A) __ (BUS)
Example:
INPBUS: INS A,BUS
JBb address
;INPUT BUS CONTENTS
;TO ACC
Jump If Accumulator Bit is Set (Not in 8021, 8022)
I b2 b1 bo 1 I 0 0 1 0 I 1a7 a6 as a4 Ia3 a2 a1 aO I
This is a 2-cycle instruction. Control passes to the
specified address if accumulator bit 'b' is set
to one.
b=0-7
Example:
(PCO-7)-- addr
(PC) = (PC)+2
If Bb=1
If Bb=O
JB4IS1: JB4 NEXT
;JUMP TO 'NEXT' ROUTINE
;IF ACC BIT 4=1
JC address
Jump If Carry Is Set
11 1 1 1 1 0 1 1 0 1
I a7 a6 as a4 Ia3 a2 a1 aO I
This is a 2-cycle instruction. Control passes to the
specified address if the carry bit is set to one.
Example:
(PCO-7)-- addr
(PC) = (PC)+2
If C=1
If C=O
JC1: JC OVFLOW
;JUMP TO 'OVFLOW' ROUTINE
;IF C=1
JFO address
Jump If Flag Ols Set (Not in 8021, 8022)
11 0 1 1 1 0 1 1 0 1
~
a6 as a4 I a3 a2 a1 ao
I
This is a 2-cycle instruction. Control passes to the
specified address if flag 0 is set to one.
Example:
(PCO-7)-- addr
(PC) = (PC)+2
If FO=1
If FO=O
JFOIS1: JFO TOTAL
;JUMP TO 'TOTAL' ROUTINE
;IF FO=1
Mnemonics copyright Intel Corporation 1976.
4·18
INSTRUCTION SET
JF1 address
Jump If Flag 1 Is Set
10 1 1 1 1 0 1 1 0 1
(Not in 8021, 8022)
1 a7 a6 as a4 1a3 a2 a1 ao 1
This is a 2-cycle instruction. Control passes to the
specified address if flag 1 is set to one.
Example:
(PCO-7)"- addr
(PC) = (PC)+2
If F1 =1
IF F1=0
JF1IS1: JF1 FILBUF
;JUMP TO 'FILBUF'
;ROUTINE IF F1=1
JMP address
Direct Jump Within 2K Block
I a10 ag as 0 I 0 1 0 0 1 I a7 a6 as a4 1a3 a2 a1 ao 1
This is a 2-cycle instruction. Bits 0-10 of the program
counter are replaced with the directly-specified
address. The setting of PC bit 11 is determined by
the most recent SELECT MB instruction.
(PCS-10)-- addr 8-10
(PCO-7)"- addr 0-7
(PC 11 )-- DBF
Example:
JMP SUBTOT
JMP $-6
JMP 2FH
JMPP @A
;JUMP TO SUBROUTINE 'SUBTOT
;JUMP TO INSTRUCTION SIX LOCATIONS
;BEFORE CURRENT LOCATION
;JUMP TO ADDRESS '2F' HEX
Indirect Jump Within Page
11011100111
This is a 2-cycle instruction. The contents of the
program memory location pointed to by the accumulator
are substituted for the 'page' portion of the program
counter (PC bits 0-7).
(PCO-7)"- ((A))
Example:
Assume accumulator contains OFH.
JMPPAG: JMPP @A
;JUMP TO ADDRESS STORED IN
;LOCATION 15 IN CURRENT PAGE
JNC address
Jump If Carry Is Not Set
11 1 1 0 1 0 1 1 0 1
I a7 a6 as a4 1a3 a2 a1 ao I·
This is a 2-cycle instruction. Control passes to the
specified address if the carry bit is not set, that
is, equals zero.
Mnemonics copyright Intel Corporation 1976.
4-19
INSTRUCTION SET
Example:
(PCO-7)~ addr
(PC) = (PC)+2
If C=O
IF C=1
JCO: JNC NOVFLO
;JUMP TO 'NOVFLO' ROUTINE
;If C=O
Jump If Interrupt Input is Low (Not in 8021, 8022)
JNI address
11 0 0 0 1 0 1 1 0
I
I
1a7 a6 as a4 a3 a2 a1 ao
I
This is a 2-cycle instruction. Control passes to the
specified address if the interrupt input signal is
low (=0), that is, an external interrupt has
been signaled. (This signal initiates an interrupt
service sequence if the external interrupt is enabled.)
Example:
(PCO-7)~
addr
(PC) = (PC)+2
If 1=0
If 1=1
LOC 3: JNI EXTINT
;JUMP TO 'EXTINT' ROUTINE
;If 1=0
JNTO address
Jump If Test 0 Is Low (Not in 8021)
10 0 1 0 1 0 1 1 0 1 1a7 a6 as a4 1a3 a2 a1 ao
I
This is a 2-cycle instruction. Control passes to the
specified address, if the test 0 signal is low
Example:
(PCO-7)~ addr
(PC) = (PC)+2
If TO=O
If TO=1
JTOLOW: JNTO 60
;JUMP TO LOCATION 60 DEC
;IF TO=O
JNT1 address
Jump If Test 1 Is Low
This is a 2-cycle instruction. Control passes to the
specified address, if the test 1 signal is low.
(PCO-7)~ addr
(PC) = (PC)+2
JNZ address
If T1=0
If T1=1
Jump If Accumulator Is Not Zero
11 0 0 1 1 0 1 1 0 1 1a7 a6 as a4 1a3 a2 a1 ao
I
This is a 2-cycle instruction. Control pases to the
specified address if the accumulator contents are
nonzero at the time this instruction is executed.
Example:
(PCO-7)~ addr
(PC) = (PC)+2
If A"tO
If A=O
JACCNO: JNZ OABH
;JUMP TO LOCATION 'AB' HEX
;IF ACC VALUE IS NONZERO
Mnemonics copyright Intel Corporation 1976.
4-20
INSTRUCTION SET
JTF address
Jump If Timer Flag Is Set
I0 0 0 1 I 0 1 1 0 I Ia7 a6 as a4 Ia3 a2 a1 ao I
This is a 2-cycle instruction. Control passes to the
specified address if the timer flag is set to one,
that is, the timer/counter register has overflowed.
Testing the timer flag resets it to zero. (This
overflow initiates an interrupt service sequence
if the timer-overflow interrupt is enabled.)
Example:
(PC O- 7)-- addr
(PC) = (PC)+2
If TF=1
If TF=O
JTF1: JTF TIMER
;JUMP TO 'TIMER' ROUTINE
;IFTF=1
JTO address
Jump If Test 0 Is High (Not in 8021)
I 0 0 1 1 I 0 1 1 0 I Ia7 a6 as a4 Ia3 a2 a1 ao I
This is a 2-cycle instruction. Control passes to the
specified address if the test 0 signal is high (=1).
Example:
(PCO-7)-- addr
(PC) = (PC)+2
If TO=1
If TO=O
JTOHI: JTO 53
;JUMP TO LOCATION 53 DEC
;IF TO=1
JT1 address
Jump If Test 1 Is High
I 0 1 0 1 I 0 1 1 0 I Ia7 a6 as a4 Ia3 a2 a1 ao I
This is a 2-cycle instruction. Control passes to the
specified address if the test 1 signal is high (=1).
Example:
JZ address
(PCO-7)-- addr
(PC) = (PC)+2
If T1=1
If T1=O
JT1HI: JT1 COUNT
;JUMP TO 'COUNT' ROUTINE
;IF T1=1
Jump If Accumulator Is Zero
This is a 2-cycle instruction. Control passes to the
specified address if the accumulator contains all
zeros at the time this instruction is executed.
Example:
(PCO-7) -- addr
(PC) = (PC)+2
If A=O
If At-O
JACCO: JZ OA3H
;JUMP TO LOCATION 'A3' HEX
;IF ACC VALUE IS ZERO
Mnemonics copyright Intel Corporation 1976.
4·21
INSTRUCTION SET
Mev A, #data
Move Immediate Data to Accumulator
1 001 0 1 0 0 1 1 1 1d7 d6 ds d4 J d3 d2 d1 do 1
This is a 2-cycle instruction. The 8-bit value
specified by 'data' is loaded in the accumulator.
(A)-- data
Example:
MOV A,#OA3H
MaV A,PSW
;MOVE 'A3' HEX TO ACC
Move PSW Contents to Accumulator (Not in 8021, 8022)
11100101111
The contents of the program status word are moved
to the accumulator.
(A)-- (PSW)
Example:
Jump to 'RB1SET' routine if PSW bank switch, bit 4,
is set.
;MOVE PSW CONTENTS TO ACC
BSCHK: MOV A,PSW
JB4 RB1SET
;JUMP TO 'RB1SET' IF ACC
;BIT 4=1
MaV A,R r
Move Register Contents to Accumulator
11111J1rrri
8-bits of data are moved from working register 'r'
into the accumulator.
Example:
(A)-- (Rr)
r=0-7
MAR: MOV A,R3
;MOVE CONTENTS OF REG 3
;TO ACC
MaV A,@R r
Move Data Memory Contents to Accumulator
111111000rl
The contents ot the resident data memory location
addressed by bits 0-5*ot register 'r' are moved to
the accumulator. Register 'r' contents are unaffected.
(A) __ ((Rr))
Example:
r=0-1
Assume R1 contains 00110110.
;MOVE CONTENTS OF DATA MEM
MADM: MOV A,@R1
;LOCATION 54 TO ACC
Mnemonics copyright Intel Corporation 1976.
'0-6 for 8039/8049
4-22
INSTRUCTION SET
Mev A,T
Move Timer/Counter Contents to Accumulator
10100100101
The contents of the timer/event-counter register
are moved to the accumulator.
(A)--- (T)
Example:
Jump to "EXIT" routine when timer reaches '64',
that is, when bit 6 set - assuming initialization 64,
TIMCHK: MOV A,T
;MOVE TIMER CONTENTS TO
;ACC
JB6 EXIT
;JUMP TO 'EXIT' IF ACC BIT
;6=1
MeV PSW,A
Move Accumulator Contents to PSW (Not in 8021, 8022)
11101101111
The contents of the accumulator are moved into the
program status word. All condition bits and the
stack pointer are affected by this move.
(PSW)--- (A)
Example:
MOV Rr,A
Move up stack pointer by two memory locations,
that is, increment the pointer by one.
INCPTR: MOV A,PSW
;MOVE PSW CONTENTS TO ACC
INC A
;INCREMENT ACC BY ONE
MOV PSW,A
;MOVE ACC CONTENTS TO PSW
Move Accumulator Contents to Register
1101011rrri
The contents of the accumulator are moved to
register 'r'.
Example:
(Rr)--- (A)
r=0-7
MRA: MOV RO,A
;MOVE CONTENTS OF ACC TO
;REG 0
MOV Rr,#data
Move Immediate Data to Register
This is a 2-cycle instruction. The 8-bit value
specified by 'data' is moved to register 'r'.
(Rr).- data
r=0-7
Mnemonics copyright Intel Corporation 1976.
4-23
INSTRUCTION SET
Examples: MIR4: MOV R4,#HEXTEN ;THE VALUE OF THE SYMBOL
;'HEXTEN' IS MOVED INTO
;REG 4
MIR 5: MOV R5,#PI*(R*R) ;THE VALUE OF THE
;EXPRESSION 'PI*(R*R)
;IS MOVED INTO REG 5
MIR 6: MOV R6, #OADH ;'AD' HEX IS MOVED INTO
;REG .6
MaV @Rr,A
Move Accumulator Contents to Data Memory
1 1 0 1 01000 r
l
This is a 2-cycle instruction. The contents of the
accumulator are moved to the resident data
memory location whose address is specified by bits
0-5* of register 'r'. Register 'r' contents are
unaffected.
((Rr))-- (A)
Example:
r=0-1
Assume RO contains 00000111.
MDMA: MOV @RO,A
;MOVE CONTENTS OF ACC TO
;LOCATION 7 (REG 7)
MaV @Rr,#data
Move Immediate Data to Data Memory
11 0 1 1 1 0 0 0 r 1
1d7 d6 ds d4 1 d3 d2 d1 do 1
This is a 2-cycle instruction. The 8-bit value
specified by 'data' is moved to the resident data
memory location addressed by register 'r', bits 0-5~
((Rr)) __ data
r=0-1
Examples: Move the hexadecimal value AC3F to locations 62-63.
MIDM: MOV RO,#62
;MOVE '62' DEC TO ADDR REG 0
MOV @RO,#OACH ;MOVE 'AC' HEX TO LOCATION 62
INC RO
;INCREMENT REGO TO '63'
MOV @RO,#3FH
;MOVE '3F' HEX TO LOCATION 63
MaV T,A
Move Accumulator Contents to Timer/Counter
10110100101
The contents of the accumulator are moved to the
timer/event-counter register.
(T)-- (A)
Example:
Initialize and start event counter.
INITEC: CLR A
;CLEAR ACC TO ZEROS
MOV T,A
;MOVE ZEROS TO EVENT COUNTER
STRT CNT
;ST ART COUNTER
Mnemonics copyright Intel Corporation 1976,
4-24
'0-6 for 8039/8049
INSTRUCTION SET
MOVO A,Pp
Move Port 4-7 Data to Accumulator
10000111ppi
This is a 2-cycle instruction. Data on 8243 port
'p' is moved (read) to accumulator bits 0-3.
Accumulator bits 4-7 are zeroed.
(0-3) ..... (Pp)
p=4-7
(4-7) ..... 0
Note: Bits 0-1 of the opcode are used to represent ports
4-7. If you are coding in binary rather than assembly
language, the mapping is as follows:
Bits 1 0
Port
00
4
015
106
1 1
7
Example:
INPPT5: MOVD A,P5
MOVO Pp,A
;MOVE PORT 5 DATA TO ACC
;BITS 0-3, ZERO ACe BITS 4-7
Move Accumulator Data to Port 4-7
10011111ppl
This is a 2-cycle instruction. Data in accumulator
bits 0-3 is moved (written) to 8243 port 'p'.
Accumulator bits 4-7 are unaffected. (See NOTE
above regarding port mapping.)
(Pp) ... (A o-3)
Example:
p=4-7
Move data in accumulator to ports 4 and 5.
OUTP45: MOVD P4,A
;MOVE ACC BITS 0-3 TO PORT 4
SWAP A
;EXCHANGE ACC BITS 0-3 AND 4-7
MOVD P5,A
;MOVE ACC BITS 0-3 TO PORT 5
MOVP A,@A
Move Current Page Data to Accumulator
11010100111
The contents of the program memory location addressed
by the accumulator are moved to the accumulator. Only
bits 0-7 of the program counter are' affected, limiting
the program memory reference to the current page. The
program counter is restored following this operation
(PC O- 7) ..... (A)
(A) ..... ((PC»
Note: This is a 1-byte, 2-cycle instruction. If it appears
in location 255 of a program memory page, @A addresses
a location in the following page.
Mnemonics copyright Intel Corporation 1976.
4·25
INSTRUCTION SET
Example:
MOV128: MOV A,#128
MOVPA,@A
MOVP3 A,@A
;MOVE '128' DEC TO ACC
;CONTENTS OF 129th LOCATION
;IN CURRENT PAGE ARE MOVED TO
;ACC
Move Page 3 Data to Accumulator
(Not in 8021,8022)
11110100111
This is a 2-cycle instruction. The contents of the
program memory location (within page 3) addressed by
the accumulator are moved to the accumulator. The
program counter is restored following this operation.
(PCo-7)+(A)
(PCS_11)+0011
(A)+«PC))
Example:
Look up ASCII equivalent of hexadecimal code in table
contained at the beginning of page 3. Note that ASCII
characters are designated by a 7-bit code; the eighth
bit is always reset.
TABSCH: MOV A,#OB8H ;MOVE 'B8' HEX TO ACC (10111000)
ANL A,#7FH
;LOGICAL AND ACC TO MASK BIT
;7 (00111000)
MOVP3 A,@A ;MOVE CONTENTS OF LOCATION
;'38' HEX IN PAGE 3 TO ACC
;(ASCII '8')
Access contents of location in page 3 labelled TAB1.
Assume current program location is not in page 3.
TABSCH: MOV A,#LOW TAB1 ;ISOLATE BITS 0-7 OF LABEL
;ADDRESS VALUE
MOVP3 A,@A
;MOVE CONTENTS OF PAGE 3
;LOCATION LABELED 'TAB1'
;TO ACC
MOVX A,@R r
Move External-Data-Memory Contents to Accumulator
11 000
I 000 r I
(Not in 8021, 8022)
This is a 2-cycle instruction. The contents of the
external data memory location addressed by register
'r' are moved to the accumulator. Register 'r' contents
are unaffected.
(A)..- «Rr))
Example:
r=0-1
Assume R1 contains 01110110.
MAXDM: MOVX A,@R1
;MOVE CONTENTS OF LOCATION
;118 TO ACC
Mnemonics copyright Intel Corporation 1976.
4-26
INSTRUCTION SET
MOVX @Rr,A
Move Accumulator Contents to External Data Memory
(Not in 8021, 8022)
11 00 1 1 00 0 r 1
This is a 2-cycle instruction. The contents of the
accumulator are moved to the external data memory
location addressed by register 'r'. Register 'r'
contents are unaffected.
r=0-1
((Rr))-- A
Example:
NOP
Assume RO contains 11000111.
MXDMA: MOVX @RO,A
;MOVE CONTENTS OF ACC TO
;LOCATION 199 IN EXPANDED
;DATA MEMORY
The NOP Instruction
1000010000
I
No operation is performed. Execution continues with
the following instruction.
ORL A,R r
Logical OR Accumulator With Register Mask
101001 1rrr
i
Data in the accumulator is logically ORed with the
mask contained in working register 'r'.
Example:
(A)-- (A) OR (Rr)
r=Q-7
ORREG: ORL A,R4
;'OR' ACC CONTENTS WITH
;MASK IN REG 4
ORL A,@R r Logical OR Accumulator With Memory Mask
10 100 1000rl
Data in the accumulator is logically ORed with the mask
contained in the resident data memory location referenced by
register 'r', bits 0-5*
Example:
(A) -- (A) OR ((Rr))
r=0-1
ORDM: MOV RO,#3FH
ORL A,@RO
;MOVE '3F' HEX TO REG 0
;'OR' ACC CONTENTS WITH MASK
;IN LOCATION 63
ORL A,#data
Logical OFJ Accumulator With Immediate Mask
10 1 0 0 1 0 0 1 1 1
I d7 dB ds d4 I d3 d2 d1 do I
This is a 2-cycle instruction. Data in the accumulator
is logically ORed with an immediately-specified mask.
(A)-- (A) OR data
Example:
;'OR' ACC CONTENTS WITH MASK
;01011000 (ASCII VALUE OF 'X')
ORID: ORL A,#'X'
Mnemonics copyright Intel Corporation 1976.
'0-6 for 8039/8049
4-27
INSTRUCTION SET
ORl BUS,#data
logical OR BUS With Immediate Mask (Not in 8021,8022)
11 0 0 0 11 0 0 0 1 1d7 d6 ds d4 1 d3 d2 d1 do 1
Example:
This is a 2-cycle instruction. Data on the BUS port is
logically ORed with an immediately-specified mask. This
instruction assumes prior specification of an 'OUTL BUS,A'
instruction.
(BUS)-- (BUS) OR data
ORB US: ORL BUS,#HEXMSK ;'OR' BUS CONTENTS WITH
;MASK EQUAL VALUE OF SYMBOL
;'HEXMSK'
ORl Pp, #data
logical OR Port 1 or 2 With Immediate Mask (Not in
11 00 0 11 0 P p 1 1d7 d6 ds d4 1 d3 d2 d1 dO 1
8021, 8022)
This is a 2-cycle instruction. Data on port 'p'
is logically ORed with an immediately-specified mask.
(Pp)-- (Pp) OR data
p=1-2
Example: ORP1: ORL P1, #OFFH
;'OR' PORT 1 CONTENTS WITH
;MASK 'FF' HEX ( SET PORT 1
;TO ALL ONES)
ORlD Pp,A
logical OR Port 4-7 With Accumulator Mask
11000111ppl
This is a 2-cycle instruction. Data on port'p' is
logically ORed with the digit mask contained in
accumu lator bits 0-3.
p=4-7
(Pp) ... (Pp) OR (AO-3)
Example:
ORPT: ORLD P7,A
;'OR' PORT 7 CONTENTS
;WITH ACC BITS 0-3
OUTl PO, A Output Accumulator Data to Port 0 (8021, 8022 Only)
11001100001
OUTl BUS,A
Output Accumulator Data to BUS (Not in 8021,8022)
100001·00101
This is a 2-cycle instruction. Data residing in the
accumulator is transferred (written) to the BUS port and
latched. The latched data remains valid until altered by
anotherOUTL instruction. Any other instruction
requiring use of the BUS port (except INS) destroys the
contents of the BUS latch. This includes expanded
memory operations (such as the MOVX instruction).
Logical operations on BUS data (AND, OR) assume the
OUTL BUS,A instruction has been issued previously .
. (BUS) -- (A)
Example: OUTLB!?: OUTL BUS,A
Does not
apply for
OUTL
PO,A
of 8021, 8022
;OUTPUT ACC CONTENTS TO BUS
Mnemonics copyright Intel Corporation 1976.
4-28
INSTRUCTION SET
OUTL Pp,A
Output Accumulator Data to Port 1 or 2
10011110ppl
This is a 2-cycle instruction. Data residing in the
accumulator is transferred (written) to port 'p' and
latched.
Example:
RAD
(Pp) .... (A)
p=1-2
OUTLP: MOV A,R7
OUTL P2,A
MOV A,R6
OUTL P1,A
;MOVE REG 7 CONTENTS TO ACC
;OUTPUT ACC CONTENTS TO PORT 2
;MOVE REG 6 CONTENTS TO ACC
;OUTPUT ACC CONTENTS TO PORT 1
Move Conversion Result Register to Accumlator
(8022 Only)
11000100001
This is a two cycle instruction. The contents of the AID conversion
result register are moved to the accumulator.
(A) .... (CRR)
RET
Return Without PSW Restore
11000100111
This is a 2-cycle instruction. The stack pointer
(PSW bits 0-2) is decremented. The program counter
is then restored from the stack. PSW bits 4-7 are
not restored.
(SP) .... (SP)-1
(PC) .... «SP»
RETI
Return From Interrupt (8022 Only)
11001100111
This is a two cycle instruction. The stack pointer is decremented and
the program counter is restored from the stack. Interrupt input logic is
re-enabled.
(SP)-- (SP)-1
(PC) .... «SP) +1
·Mnemonics copyright Intel Corporation 1976.
4-29
INSTRUCTION SET
RETR
Return With PSW Restore (Not in 8021, 8022)
11001100111
This is a 2-cycle instruction. The stack pointer is
decremented. The program counter and bits 4-7 of the
PSW are then restored from the stack. Note that RETR
should be used to return from an interrupt, but
should not be used within the interrupt service
routine as it signals the end of an interrupt routine by
resetting the Interrupt in Progress flipflop.
(SP)..- (SP)-1
(PC)..- ((SP))
(pSW 4-7)"- ((SP))
RL A
Rotate Left Without Carry
1 1 110101111
The contents of the accumulator are rotated left one
bit. Bit 7 is rotated into the bit 0 position.
(An+1)"- (An)
(AO)..- (A7)
Example:
RLC A
n=0-6
Assume accumulator contains 10110001 ..
RLNC: RL A
;NEW ACC CONTENTS ARE 01100011.
Rotate Left Through Carry
11111101111
The contents of the accumulator are rotated left one
bit. Bit 7 replaces the carry bit; the carry bit is
rotated into the bit 0 position.
(An +1)..- (An)
n=o-S
(AO)-- (C)
(C)-- (A7)
Example: . Assume accumulator conta,ins a 'signed' number;
isolate sign without changing value.
;CLEAR CARRY TO ZERO
RL TC: CLR C
RLC A
;ROTATE ACC LEFT, SIGN
;BIT (7) IS PLACED IN CARRY
RR A
;ROTATE ACC RIGHT - VALUE
(BITS 0-6) IS RESTORED,
;CARRY UNCHANGED, BIT 7
;IS ZERO
Mnemonics copyright Intel Corporation 1976.
4·30
INSTRUCTION SET
RR A
Rotate Right Without Carry
10111\011 1 1
The contents of the accumulator are rotated right
one bit. Bit 0 is rotated into .the bit 7 position
(An)-- (An +1)
(A7)-- (AO)
Example:
RRC A
n=0-6
Assume accumulator contains 10110001.
RRNC: RR A
;NEW ACC CONTENTS ARE 11011000
Rotate Right Through Carry
10110\01111
The contents of the accumulator are rotated right one
bit. Bit 0 replaces the carry bit; the carry bit is
rotated into the bit 7 position.
n=0-6
(An)-- (An+1)
(A7)-- (C)
(C)-- (Ao)
Example:
SEL ANO
Assume carry is not set and accumulator contains
10110001.
RRTC: RRC A
;CARRY IS SET AND ACC
;CONTAINS 01011000
Select Analog Input Zero (8022 Only)
11001101011
SEL AN1
Select Analog Input One (8022 Only)
11000101011
One of the two analog inputs to the AID converter is selected. The
conversion process is started. Restarting a sequence deletes the
sequence in progress.
4-31
INSTRUCTION SET
SEL MBO
(Not in 8021, 8022)
Select Memory Bank 0
11110101011
PC bit 11 is set to zero on next JMP or CALL instruction.
All references to program memory addresses fall within
the range 0-2047.
(DBF) .... 0
Example: Assume program counter contains 834 Hex.
;SELECT MEMORY BANK 0
;JUMP TO LOCATION
;48 HEX
SEL MBO
JMP $+20
SEL MB1
Select Memory Bank 1
(Not in 8021, 8022)
11111101011
PC bit 11 is set to one on next JMP or CALL instruction.
All references to program memory addresses fall
within the range 2048-4095.
(DBF) .... 1
SEL RBO
Select Register Bank 0
(Not in 8021, 8022)
11100101011
PSW bit 4 is set to zero. References to working
registers 0-7 address data memory locations 0-7.
This is the recommended setting for normal program
execution.
(BS) .... 0
SEL RB1
Select Register Bank 1
(Not in 8021, 8022)
11101101011
PSW bit 4 is set to one. References to working registers
0-7 address data memory locations 24-31. This is the
recommended setting for interrupt service routines,
since locations 0-7 are left intact. The setting of
PSW bit 4 in effect at the time of an interrupt is
restored by the RETR instruction when the interrupt
service routine is completed.
(BS) .... 1
Example:
Assume an external interrupt has occurred, control
has passed to program memory location 3, and PSW bit
4 was zero before the interrupt.
LOC3: JNI INIT
;JUMP TO ROUTINE 'INIT' IF
;INTERRUPT INPUT IS ZERO
Mnemonics copyright Intel Corporation 1976.
4·32
INSTRUCTION SET
INIT: MOV R7,A
STOP TCNT
SEL RB1
MOV R7,#OFAH
;MOVE ACC CONTENTS TO
;LOCATION 7
;SELECT REG BANK 1
;MOVE 'FA' HEX TO LOCATION 31
SEL RBO
MOV A,R7
RETR
;SELECT REG BANK 0
;RESTORE ACC FROM LOCATION 7
;RETURN - RESTORE PC AND PSW
Stop Timer/Event-Counter
10110101011
This instruction is used to stop both time accumulation
and event counting.
Example:
Disable interrupt, but jump to interrupt routine after
eight overflows and stop timer. Count overflows in
register 7.
START: DIS TCNTI
CLR A
MOV T,A
MOV R7,A
STRT T
MAIN:
JTF COUNT
JMP MAIN
COUNT: INC R7
MOV A,R7
JB31NT
JMP MAIN
INT:
STOP TCNT
JMP 7H
;DISABLE TIMER INTERRUPT
;CLEAR ACC TO ZEROS
;MOVE ZEROS TO TIMER
;MOVE ZEROS TO REG 7
;START TIMER
;JUMP TO ROUTINE 'COUNT'
;IF TF=1 AND CLEAR TIMER FLAG
;CLOSE LOOP
;INCREMENT REG 7
;MOVE REG 7 CONTENTS TO ACC
;JUMP TO ROUTINE 'INT' IF ACe
;BIT 3 IS SET (REG 7=8)
;OTHERWISE RETURN TO ROUTINE
;MAIN
;STOP TIMER
;JUMP TO LOCATION 7 (TIMER)
;INTERRUPT ROUTINE
Mnemonics copyright Intel Corporation 1976.
4-33
INSTRUCTION SET
STRT CNT
Start Event Counter
10100101011
The test 1 (T1) pin is enabled as the event-counter
input and the counter is started. The event-counter
register is incremented with each high-to-Iow transition
on the T1 pin.
Initialize and start event counter. Assume overflow
is desired with first T1 input.
STARTC: EN TCNTI
;ENABLE COUNTER INTERRUPT
MOV A,#OFFH ;MOVE 'FF' HEX (ONES) TO
;ACC
;MOVE ONES TO COUNTER
MOV T,A
;ENABLE T1 AS COUNTER
STRT CNT
;INPUT AND START
Example:
STRT T
Start Timer
10101101011
Timer accumulation is initiated in the timer register.
The register is incremented every 32 instruction cycles.
The prescaler which counts the 32 cycles is cleared
but the timer register is not.
Example:
SWAP A
Initialize and start timer.
STARTT: CLR A
;CLEAR ACC TO ZEROS
MOV T,A
;MOVE ZEROS TO TIMER
EN TCNTI
;ENABLE TIMER INTERRUPT
STRT T
;START TIMER
Swap Nibbles Within Accumulator
10 100101111
Bits 0-3 of the accumulator are swapped with bits
4-7 of the accumulator.
(A 4- 7) ~ (A o-3 )
Example:
Pack bits 0-3 of locations
PCKDIG: MOV RO, #50
MOV R1, #51
XCHD A,@RO
SWAP A
XCHD A,@R1
MOV @RO,A
50-51 into location 50.
;MOVE '50' DEC TO REG 0
;MOVE '51' DEC TO REG 1
;EXCHANGE BITS 0-3 OF ACC
;AND LOCATION 50
;SWAP BITS 0-3 AND 4-7 OF ACC
;EXCHANGE BITS 0-3 OF ACC AND
;LOCATION 51
;MOVE CONTENTS OF ACC TO
;LOCATION 50
Mnemonics copyright Intel Corporation 1976.
4-34
INSTRUCTION SET
XCH A,R r
Exchange Accumulator-Register Contents
1001011rrri
The contents of the accumulator and the contents of
working register 'r' are exchanged.
(A)~ (Rr)
r=0-7
Example:
Move PSW contents to Reg 7 without losing
accumulator contents.
;EXCHANGE CONTENTS OF REG 7
XCHAR7: XCH A,R7
;AND ACC
MOV A, PSW ;MOVE PSW CONTENTS TO ACC
;EXCHANGE CONTENTS OF REG 7
XCH A,R7
;AND ACC AGAIN
XCH A,@R r
Exchange Accumulator and Data Memory Contents
100101000ri
The contents of the accumulator and the contents of
the resident data memory location addressed by bits
0-5*of register 'r' are exchanged. Register 'r'
contents are unaffected.
(A)~
Example:
r=0-1
((Rr))
Decrement contents of location 52.
DEC52: MOV RO,#52
;MOVE '52' DEC TO ADDRESS
;REG 0
XCH A,@RO
;EXCHANGE CONTENTS OF ACC
;AND LOCATION 52
DEC A
;DECREMENT ACC CONTENTS
XCH A,@RO
;EXCHANGE CONTENTS OF ACC
;AND LOCATION 52 AGAIN
XCHD A,@R r
Exchange Accumulator and Data Memory 4-Bit Data
100111 000r
l
This instruction exchanges bits 0-3 of the accumulator
with bits 0-3 of the data memory location addressed by
bits 0-5*of register 'r'. Bits 4-7 of the accumulator,
bits 4-7 of the data memory location, and the contents
of register 'r' -are unaffected.
(A O- 3) ~ ((RrO-3))
r=0-1
Mnemonics copyright Intel Corporation 1976.
'0-6 for 8039/8049
4-35
INSTRUCTION SET
Example:
XRL A,R r
Assume program counter
locations 22-23.
XCHNIB: MOV RO,#23
CLR A
XCHD A,@RO
contents have been stacked in
;MOVE '23' DEC TO REG 0
;CLEAR ACC TO ZEROS
;EXCHANGE BITS 0-3 OF ACC
;AND LOCATION 23 (BITS 8-11
;OF PC ARE ZEROED, ADDRESS
;REFERS TO PAGE 0)
Logical XOR Accumulator With Register Mask
1110111rrri
Data in the accumulator in EXCLUSIVE ORed with the mask
contained in working register 'r'.
Example:
(A) .... (A) XOR (Rr)
r=0-7
XORREG: XRL A,R5
;'XOR' ACC CONTENTS WITH
;MASK IN REG 5
XRL A,@R r
Logical XOR Accumulator With Memory Mask
111011000rl
Data in the accumulator is EXCLUSIVE ORed with the mask
contained in the data memory location addressed by
register 'r', bits 0-5~
Example:
(A) .... (A) XOR ((Rr))
r=0-1
XORDM: MOV R1, #20H
XRL A,@R1
;MOVE '20' HEX TO REG 1
;'XOR' ACC CONTENTS WITH MASK
;IN LOCATION 32
XRL A,#data
Logical XOR Accumulator With Immediate Mask
11 1 0 1 1 0 0 1 1 1 1d7 de ds d4
I d3 d2 d1 do I
This is a 2-cycle instruction. Data in the accumulator
is EXCLUSIVE ORed with an immediately'-specified mask.
(A) .... (A) XOR data
Example:
XORID: XOR A,#HEXTEN ;XOR CONTENTS OF ACC WITH
;MASK EQUAL VALUE OF SYMBOL
;'HEXTEN'
Mnemonics copyright Intel Corporation 1976.
·0-6 for 8039/8049
4-36
Appli~ation
Examples
APPLICATION EXAMPLES
5.0 Introduction
The following chapter is organized in two
sections, Hardware and Software. The
hardware section gives examples of some
typical configurations of MCS-48 components while software section gives assembly
language listings of some common applications routines.
5.1 Hardware Examples
DRIVING FROM EXTERNAL SOURCE
CRYSTAL OSCILLATOR MODE
+5V
r-----
47012
XTAll
..
I
Jo-4------'"2~ XTAll
I
< 15 pF
(INCLUDES XTAL,
SOC~ET, STRAY)
I
..L
+5V
I
I
IL ____ _
15-25pF
(INCLUDES SOCKET,
STRAY)
47012
I
L---'--~XTAL2
":'
BOTH XTAll AND XTAl2 SHOULD BE DRIVEN.
RESISTORS TO Vee ARE NEEDED TO ENSURE V,H = 3.8V
IF TTL CIRCUITRY IS USED.
CRYSTAL SERIES RESISTANCE SHOULD BE <7512 AT 6 MHz; <1601l AT 3.6 MHz.
LC OSCILLATOR MODE
NOTE:
A STANDARD SERIES RESONANT XTAL SUCH
AS CTS KNIGHTS MP060 OR CRYSTEK CY6B
WILL PROVIDE BETTER THAN .1% FRE·
QUENCY ACCURACY.
--"-
J;..
45 .H
20 pF
12O.H
20pF
NOMINAL'
5.2 MHz
3.2 MHZ..--_..-_-42 XTAll
C'- C+3Cpp
-
EACH C SHOULD BE APPROXIMATELY 20pF,
INCLUDING STRAY CAPACITANCE. FOR
MORE INFORMATION ON XTALS SEE INTElAPPLICATION NOTE AP.35.
L---_~_~3 XTAl2
2
Cpp " 5 - 10 pF PlN·TO·PIN
CAPACITANCE
EACH C SHOULD BE APPROXIMATELY 20 pF. INCLUDING STRAY CAPACITANCE.
NOTE: SEE PAGE 5·3 FOR 6021
FREQUENCY REFERENCES.
FREQUENCY REFERENCE OPTIONS
5·1
APPLICATION EXAMPLES
+5V
GND
b~L
Vee
VDD Vss
P10
P11
P12
P13
P14
P15
P16
P17
2
~
~
XTAL 1
3
XTAL 2
15-25pf
f-----!
RESET
1ufd
EA
-=-
8049
8048
8748
5
55
NC
P20
P21
P22
P23
P24
P25
P26
P27
1
{-
TO
DBO
DB1
DB2
DB3
DB4
DB5
DB6
DB7
39
INPUT
- - : T1
INT
NC
27
28
29
30
31
32
33
34
21
22
23
24
35
36
37
38
12
13
14
15
16
17
18
19
}~'"
[ INPUT
AND
OUTPUT
}~'"
[ INPUT]
AND
OUTPUT
}
['''~]
BUS PORT
1
AND
OUTPUT
NC
• All inputs and outputs (except RESET, X1, X2)
standard TTL compatible
• P1 and P2 outputs drive 5V CMOS directly others
require 10 to 50KO, pullup for CMOS compatibility
crs Knights MP060
XTAL: Series Resonant
1 to 6 MHz
or
Parallel Resonant
for higher
accuracy
Crystek CY6B
or equivalent
or standard 3.58 MHz
TV Color Burst XT AL
THE STAND ALONE 8048/8049
5-2
APPLICATION EXAMPLES
+5V
GND
LL
Vee
Vss
15
~ 1~
~
XTAL 1
XTAL2
+5V
4
POO
5
POI
6
P02
7
P03
8
P04
9
P05
10
P06
11
P07
l~fd .J...
10V
RESET
8021
Pl0
Pll
P12
P13
P14
P15
P16
P17
18
19
20
21
22
23
24
25
}
}
~~'J
PORTO AND
OUTPUT
~~'J
PORT 1 AND
OUTPUT
13
INPUT-- T1
26
P20
27
P21
1
P22
P23 2
~NPUT
J
} . PORT2 AND
OUTPUT
3
+5V
2
XTAL 1
TTL
GATE
XTAL2
NC'
I
LC
CRYSTAL
ALTERNATE FREOUENCY REFERENCE OPTIONS
(COMPONENT VALUES TO BE DETERMINED)
THE STAND ALONE 8021
5·3
EXTERNAL
APPLICATION EXAMPLES
+5V
40
Vee
4
Pl0
Pll
P12
VAAEF
P13
P14
AVec
PIS
P16
P17
AVss
20
100pF
Vss
1,HF
8022
SUBST
P24
P25
ANO
P26
P27
VTH
A D INPUTS (
ANI
23
. XTAL 1
POO
POI
P02
P03
XTAL2
P04
P05
T1
P06
P07
1M
22
rvv-i
P20
P21
P22
P23
19
lpF
25
26
27
28
29
30
31
32
33
34
35
36
38
39
10
11
12
13
14
15
16
}.~,
[ INPUT]
AND
OUTPUT
}~,
[ INPUT]
AND
OUTPUT
}.~.
[ INPUT]
AND
OUTPUT
17
NC
+5V
lK
Optional
2
r - - -.....--~Xl
r - - -.....- - . - , XI
c=
20-50pF
1 MEG
L
XTAL 1
TTL
GATE
' - - - -....--~ X2
XTAL2
NC
.6-3.6mHZ
L
EXTERNAL
CRYSTAL
ALTERNATE FREQUENCY REFERENCE OPTIONS
(COMPONENT VALUES TO BE DETERMINED)
THE STAND ALONE 8022
5-4
APPLICATION EXAMPLES
OPEN
COLLECTOR
INVERTERS
OEVICE
1
+5V
-".
10K
6
DEVICE
2
iNT
.....
8049
8048
8748
8035
8039
Z1
P10
26
Pll
29
P12
DEVICE
3
DEVICE
4
ANY
UNDEDICATED
PORT LINES
CAN BE USED
30
P13
.....
• All devices equal priority
• Processor polls Port 1 to determine interrupting device
MULTIPLE INTERRUPT SOURCES
5-5
APPLICATION EXAMPLES
12
13
14
15
10
1
2
3
4
DBO
OBI
OB2
DB3
WR
23
Bo Bl B2 SGS ECS
8049
8048
8748
8035
8039
I~ Rii
1-* ii2iii
17
INTERRUPT
INPUTS
I~ R3
ii4
I~
20
!-f,- fi5
'--=0.
7
8214
ii6
ii7
8
AO
9
Al
10
AZ
INT 5
El TG INTE ElR ClK
,-tf ~r
+5V
27
S
L-.(: R
Q
28
29
Pl0
Pll
P12
~
INT
Or--
9
RS FLIP FLOP
_
ALE
J
• Processor polls Port 1 to determine interrupting device
• Processor sets priority level by writing 4-bits to 8214
MULTIPLE INTERRUPTS WITH PRIORITY LEVELS
5·6
APPLICATION EXAMPLES
+5V
GND
L
+5V
+5V
b26
Vee Voo Vss
rll
124
Pl0
Pll
P12
P13
P14
P15
P16
P17
2
:::t::
~
•
HI ::r
f------l r--!
XTAL1
3
• XTAL 2
RESET
-:....
5
NC-
---
8049
8048
8748
8035*
8039*
ss
124
112
GNO
Vee
~
8212
~
~
3
5
7
9
16
##-#dL.
01,
01,
013
01,
01,
~ 01.
~ 01,
14 01.
CLR
-#
OS,
-5V
DO,
DO,
003
DO,
DO,
DO.
DO,
DO.
119
121
Voo
V••
A9
~ A8
LATCH
24
36
4
1
tt-2
~
~
~
'17&"
~
~
f"'---"-
A7
A6
A5
A4
A3
A2
Al
AO
8708
1K X 8
EPROM
MO OS,
13 12-:!;
+5V
1
------
~
#--
21
P20 ~IP21
~~
P22
P23
~
P24
P25
~
P26
~
P27 =-
7
EA
Vee
+12V
OBO
OBl
OB2
OB3
OB4
OB5
OB6
OB7
TO
39
T1
6
INT
ALE !'SEN PROG WR
11
19
125
110
12
13
14
15
16
17
18
19
9
10
11
13
14
15
16
17
01
02
03
04
05
06
07
08
Ali
CSIWE
18
20
*EA = 5V FOR 8035/8039
1
• 8212 serves as address latch
• Address is valid while ALE is high and is latched
when ALE goes low
EXTERNAL PROGRAM MEMORY
5-7
GNO
GNO
112
Vss
APPLICATION EXAMPLES
+5V
GND
I:l~ L
Vee
Voo Vss
~)
Pl0
Pll
P12 ~
30
P13
P14
PIS
P16 ~
P17 ~
2
.-e~
rll
=r
fllL
XTALI
~
3
• XTAL 2
:~ RESET
21
P20
22
P21
23
P22
P23
P24 ~
P25 ~
P26
P27
7
EA
8049
SS
8748
8035'
8039'
8048
-==
5
NC-
rRr1lL
1
{-
TO
~ T1
INT
iffi
ALE PSEN PROG WR
11
9
125
+5V
~}
39
INPUT
I/O
&-
110
DBO
DBI
DB2
DB3
DB4
DB5
DB6
DB7
40
I/O
A8
~
22
A9
23 A10
12
13
14
15
16
17
18
19
12
13
14
15
16
17
18
19
8
18
10
9
11
15
20
Vee Voo vss
11
EE
PAO ~
PAl ~
PA2 ~
27
PA3
PA4
PAS
PA6 'jfPA7
2B
29
30-
ADO
ADI
AD2
AD3
AD4
=-
8355
8755A
2K x 8
ADS
AD6
AD7
ROM
lOR
lOW
PBO
PBl
PB2
PB3
PB4
PBS
PB6
PB7
&--
I/O
~
~
~
~
&~
~
RD
ALE
2
+ 5 V _ CE
*EA = 5V FOR 8035/8039
,
GND
CAN BE SUPPLIED BY SYSTEM
RESET OR PORT LINE OF 8048
---!
RESET
.E
-=-
13
NC
16
NC
• External I/O ports are addressed as data memory PA=OO PB=01
• If the 8048's internal Program Memory is used this configuration will result in
the upper 1K of external memory being addressed before the lower 1K.
Inverting A10 will correct this if necessary. This inversion is not necessary if
the 8049 is used.
ADDING A PROGRAM MEMORY AND 1/0 EXPANDER
5-8
APPLICATION EXAMPLES
+5V
Cl" I"
Vee
2
~
~
1
VDD
Vss
P10
P11
P12
P13
P14
P15
P16
P17
XTAL 1
3
• XTAL 2
f----!
RESET
EA
-=
GND
5
NC-
P20
P21
P22
P23
P24
P25
3LP26
38
P27
1
{-::=!
TO
39
INPUTS
T1
INT
ALE PSEN PROG
11
I/O
21
22
23
24
35
36
8049
8048
8748
8035'
8039'
ss
27
28
29
30
31
32
33
34
WR RD
DBO
DB1
DB2
DB3
DB4
DB5
DB6
DB7
+5V
12
13
14
15
16
12
13
14
15
16
17
18
19
17
18
19
ADO
AD1
AD2
AD3
AD4
AD5
AD6
AD7
GND
21
PAO
22
PA1
23
PA2
24
PA3
25
PA4
26
PA5
27
PA6
28
PA7
PCO
PC1
PC2
PC3
PC4
PC5
8155
256 x 8
RAM
10/M
8
9
.
10
11
r
'EA = 5V FOR 8035/8039
CAN BE SUPPLIED BY SYSTEM RESET OR PORT LINE OF 8048
RD
WR
ALE
ce
4 RESET TIMER
OUT
TIMER
IN
PBO
PB1
PB2
PB3
PB4
PB5
PB6
PBl
3
TIMER
• Both 1/0 and RAM are addressed as data memory
• Writing a bit to P27 determines whether RAM or 1/0 is
to be accessed
ADDING A DATA MEMORY AND I/O EXPANDER
5-9
37
38
39
1
2
5
29
30
31
32
33
34
35
36
I/O
APPLICATION EXAMPLES
+5V +5V GND GND
140
21
A8
22
A9
23
Al0
12
13
14
15
16
17
18
19
8
~
9
+5V
GND
tl26
Vee
OPTIONAL GATE
TO PREVENT
"HOLE" IN
PROGRAM
MEMORY
VOD
L
Vss
Pl0
P11
P12
P13
P14
P15
P16
P17
XTAL 1
3
XTAL2
4
RESET
EA
-
8049
8048
8748
Sri
-----
~
~
~
~
ADO
AD1
AD2
AD3
AD4
AD5
AD6
AD7
~
8355
8755A
2Kx 8
lOW
2
T1
6
INT
ALE PSEN PROG WR
11
9
125
10
12
13
14
15
16
17
18
19
7
18
9
~
Vss
PAO
PAl
PA2
PA3
PA4
PA5
PA6
PA7
ADO
ADl
AD2
AD3
AD4
AD5
AD6
AD7
PCO
PCl
PC2
PC3
PC4
PC5
8156
256 X 8
RAM
101M
AD
ALE
8 CE
~
RESET TIMER
OUT
TIMER
IN
t
l6
3
i
TIMER
• This configuration is explained in section 3.4
THE THREE CHIP SYSTEM
5-10
~
1/0
~
~
~
~
~
~
F-
Gr
20
10 _
WR
CAN BE SUPPLI ED BY SYSTEM
RESET OR PORT LINE OF 8048
~
F-'-
JX J:
110
AD
~
~
~
~
RESET
40
DBO 12
DBl 13
DB214
DB3 15
DB4 16
DB5 17
DB6 18
DB7 19
TO
~
CE
f1L
39
g...
RD
Vee
1
PAO
PAl
PA2
PA3
PA4
PA5
PA6
PA7
PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7
lOR
T
}
11
CE
ROM
l·
rllf#rE-
P20 ~
P21 ~
23
P22
24
P23
P24 ~
P25 ~
P26 ~
P27
7
5
-1..)
bo
15
VOD Vss
,--2l. ALE
---!
2
NC
~
Vee
PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7
#-
~
~
~
~
~
~
~
~
~
~
~
~
~
~
S~
~
IJ4
tJt~
F-
1/0
APPLICATION EXAMPLES
1/0 Expansion Techniques
The following are several examples of how
the basic 1/0 capability of the MCS-48™
microcomputers can be easily expanded
externally using either the 8243 1/0
GND
+5V
b~
Vee
VDD
+5V
Pl0
Pll
P12
P13
P14
P15
P16
P17
2
1
3
• XTAL 2
f----!
RESET
EA
-=
5
Ne-
27
28
29
30
31
32
33
34
P40
P41
P42
P43
2
3
4
5
~50 1
) ,m
8243
I/O
EXPANDER
21
1
P20 E _ _ _ _ _--:'1'::1
22
P21 E _ _ _ _ _--'l~O
23_ _ _ _ _ _,9
j.!;::
P22
24
P23 ~_ _ _ _ _ _=t8
35
P24
7
36
r---I
P25
37
P26
38
P27
8049
8048
8748
8035
8039
ss
GND
20
Vss
---.r::-- XTAL 1
~
expander device or standard logic circuits.
These techniques can be used whenever
the combination memoryllO expanders
illustrated on the preceeding pages are not
required.
P20
P21
P22
P23
PROG
P51 23
P52 22
P53 21
110
P60
P61
P62
P63
20
19
18
17
13
P70 14
P71
P72 15
~~C_S_________________P_7_3 16
1
{-
TO
39
INPUT
~
Tl
INT
ALE PSEN PROG WR
1m
DBO
DBl
DB2
DB3
DB4
DBS
DB6
DB7
12
13
14
15
16
17
18
19
1/0
9
ADDING AN 1/0 EXPANDER
5-11
-=
APPLICATION EXAMPLES
+5V
GND
j~ J,.
Vee
Vss
XTALI
G
XTAL2
+5V
l~fd...L
IOV
17
RESET
DIODE
OPTIONAL
4
5
6
7
8
9
10
POe
11
P07
POO
POI
P02
P03
P04
P05
15
8021
8022'
-=
PIa
Pll
P12
P13
P14
P15
P16
P17
+5V
GND
1/0
18
19
20
21
22
23
24
25
P40
P41
P42
P43
8243
I/O
13
INPUT_ T1
EXPANDER
26
P20
27
P21
1
P22
P23 2
11
10
9
8
P20
P21
P22
P23
7 PROG
3
6
-=
'PIN NUMBERS ARE DIFFERENT FOR 8022
ADDING AN I/O EXPANDER TO THE 8021,8022
5-12
CS
2
3
4
5
1
P50
23
P51
22
P52
21
P53
20
P60
19
P61
18
P62
P63 17
13
P70
14
P71
15
P72
16
P73
1/0
APPLICATION EXAMPLES
+5V
GND
bl
40
Vee
26
VOD
+5V
Vss
~1
P10
P11
P12 ~
30
P13
P14
P15 ~
P16 ~
P17 ~.
XTAL1
~
XTAL2
RESET
NC---
P20
P21
P22
P23
P24
P25
P26
P27
8049
8048
8748
8035
8039
8021·
55
8022·
{--1
TO
39
INPUT
~ T1
INT
ALE PSEN PROG WR
I"
9
1
112
25
GND
Vee
20
2
EA
GND
124
110
AD
DBO
DB1
DB2
DB3
DB4
DBS
DB6
DB7
P40
P41
P42
P43
~
1
P50
P51
P52 F P53 ~
~
liD
~
8243
I/O
EXPANDER
11
P20
10
P21
9
P22
8
P23
21
22
23
24
35
36
37
38
~J
~
eLeL
r---l
I
6
P60
P61
P62
P63
P70
P71
P72
P73
PROG
CS
~
1/0
~
~
~
~
~~
~
~
elL
flL
1/0
~
r!!!flL·
+y
24
GjD
12
Vee
GND
P40
P41
P42
P43
18
P50
8243
I/O
EXPANDER
.... ~
P20
10
P21
9
P22
8
P23
7
6
'PIN NUM BERS ARE DIFFERENT FOR 8021, 8022
I I
I
I
ADDING MULTIPLE 1/0 EXPANDERS
5-13
I
I
PROG
CS
L
1~
L
~
P51 F P52 ~
PS3 ~
P60
P61
P62
P63
P70
P71
P72
P73
~
~
~
~
~
~~
~
1/0
APPLICATION EXAMPLES
The bus is normally used as an output port. To
use it as an input port the bus is put in the high
impedance state using the MOVX instruction
and then read using the INS instruction. The
resistor value chosen is a function of the
output loading and the characteristics of the
input signals.
ADDING 8 INPUT LINES
GND
+5V
-
C-l. L
Vee
Vss
2
XTAL 1
3
XTAL 2
Pl0
Pl1
P12
P13
P14
P15
Individual bits of the 74LS259 eight-bit
addressable latch can be set or reset using the
OUTL instruction. During the OUTL operation
bit zero of the accumulator is written into the
bit of the latch specified by bits 1 through 3 of
the accumulator. In this configuration DSoDS7 will be momentarily disturbed while the
external latch is loaded.
27
28
29
30
31
32
P16 33
4
P17 34
RESET
P20 21
P21 22
7
EA
-ss
1
_TO
39
_Tl
-
VOD
6
iNT
8049
8048
8748
P22 23
P23
P24
P25
P26
P27
24
35
36
37
38
CLR
74LS259
DBO 12
0
081 13
A
D82 14
DB3 15
DB4 16
08
07
06
1161
G
05
04
03
02
01
DB5 17
DB6 18
DB? 19
ADDING 8 OUTPUT LINES
5·14
APPLICATION EXAMPLES
+5V
GNo
b26
Vee VOD Vss
-
Normal 1/0 port is used to select an address
for the 16-to-1 multiplexer. The output of the
multiplexer is brought into a test input. Eight
inputs could be added with a 74LS151 8-to-1
multiplexer using the same structure.
L
2
XTAL 1
PlO 27
Pl1 28
P12 29
W
PT3 30
3
.14 31
XTAl2
P15 32
PT6 33
4
.17 34
RESET
8049
8048
8748
8021"
8035
8039
8022·
7
EA
-ss
1
_TO
6
74150
(24)
P23 ~-+='-----Io
24
P24
P25
P26
P27
Tl
DB2'4
iNT
DB3
DB4
DBS
DBB
Nota: If external program memory Is being
addressed, use P24-P27 instead of P20-P23.
E8
E9
El0
Ell
E12
E13
E14
E15
35
36
37
38
DBO 12
DBT 13
39
-
P20 ~-+---IA
21
P21 22
P22 17:--+---1
23
C
EO
El
E2
E3
E4
E5
E6
E7
15
16
11
18
DB7 19
'PIN NUMBERS ARE DIFFERENT FOR 8021. 8022
ADDING 16 INPUT LINES
+5V
GNo
L
-
b26
Vee VOD Vss
2
XTAlT
The latch can be loaded with the OUTL
instruction. After the latch is loaded the BUS
output state can be modified with the ANL
BUS, # DATA and the ORL BUS, # DATA. The
OUTL generates a WR strobe; ANL and ORL
do not. In this configuration DBo-DB7 will be
momentarily disturbed while the external latch
is loaded.
PTO 27
Pl1 28
P12 29
PT3 30
3
XTAl2
P14 31
P15 32
RESET
P17 34
P16 33
4
7
EA
ss
8049
8048
8748
PlO
P21
P22
.23
21
22
23
24
P24 35
P25 36
P26 37
P27 38
1
-TO
39
-Tl
6
-
iNf
DBD 12
DBT 13
oB2 14
0B3 15
oB4 16
DBS 17
DBB 18
14
13
11
6
60
60
40
3D
20
10
74LS174
(16)
ClK
6a
sa
4a
3a
2a
la
DB7 19
ADDING 6 OUTPUT LINES
5·15
APPLICATION EXAMPLES
+5V
GND
Vee
VSS
15
_
XTAll
16
XTAl2
17 _ _
-
RESET
8049
8049
8748
8021"
8035
8039
8022*
P10
Pl1
P12
Pt3
P14
P15
P16
P17
18
19
20
21
22
23
24
25
This is most useful when the outputs of the
74LS164 eight-bit shift register will be used to
scan a display and/or keyboard. In this case an
ANLD P7, A with A = OFFH can be used to load
the initial "1" and an ANLD P6, Awith A =OFEH
can be used to move it down the shift register.
DISPLAY
AND/OR
KEYBOARD
ARRAY
.20...,2;::-6- - - I A
P21 27
14LSl64
P22 1
1141
P23 ,2
>
CLR
'-t---+1
POQ 12
13
_T1
POt
P02
POl
P04
13
14
15
16
P05 17
POG 18
P07 19
'PIN NUMBERS ARE DIFFERENT FOR 8021, 8022
ADDING OUTPUT FOR KEYBOARD/DISPLAY SCANNING
5-16
APPLICATION EXAMPLES
ALE
Vee
I
J
EA
ALE PSEN
'"
'" r-r-- '"
'" r
'" r '"
-
'"
'"
'"
'"
'"
'"
iNT r - iNT
T ' r - T,
OE AIO AS AS
A7 As
T O r - To
I I
As A4 A3
AZ
A,
v~ rr +5V
VCC~
2716
00
PO/POR
{-
~
a,
00
NC-~
b
.. -
07 Os Os 04 03 02 0,
~~~~~-T~~~~
____V_S~"~
02'
03
"lS'5
0;
.- ~
Do 0,
D2 03
::JfL :::
00
0, 02 03
03
~
'4lS75
58r-- 58
TO ALL
Vee
vee~ Vee
r"}
E
N.C.
Dro_D,..,-rD,'-TD,____......, .
.....
VS$~VSS
'039
VDD
P 17
Ii'"
VDO
J:
t--=----
p 11
L-I-,.....---_+-+--t--t-----------t--+-++------j os,
P,st-- P,s
L....-+-+-~----t-l-I_l_----------+-+++-----., DS2
PISt--- P,s
L---+-++.....---t,..-I-+-+-----------+-+-+-+------i DB]
P'4
L....---++_+_+--t--t_++---~------~-t_+_i-----_1DB,
P'J
L....----+++_+--l_t-+_+_---_+~-----+-t_+_+-----_1DB,
L-------+-+-+--t--+-+-++-----tl-I-,.....----+-+~~r_----~DB.
PItt----
P'Or--
L-------+-t_+--t~~~e-t_+_++---__t-I_t--,.....--+_+-i_i~----_lDB,
Vee
r
1:r:r1::1l---
I
5K
I~ 00 D, ::L::7:' D, CK
T T T T T- --
00 0
.1/lF DECOUPLING CAPACITORS
DISTRIBUTED EVENl V ON BOARO
1
a2' a 3
0
DIDDI, DI,DI3
3216
DBO DB, DBl DBl
AD.,
PROG
00 0, 0, 03 n.
n.
4 ~
r--
......,..I-~-_-'fI""
F-,"""
n.~
~~ ~
{r _
...... ~
~ NC
~·U
~
22.' -::-
01001, D"DI~Jt-
DOD 00, DO, 00,
DCE
'"o:~
3216
DBo DB, DSzDB3
P14
'"
'"
PROG
X,RST
I~ 00 D, ::L::':' D. CK
W
DOo DO, DO, 00,
WA
r-----
r---- '"
P'2r--- '"
RSr
XTAll
N.C. L- XTAl2
-: - . .
- - - - - - - - - 1 WR
t----~IF~R:::,B~B~D:::N-=-CA~B::-lE:-I Ro
L-____+++-t-I----+-~·l..~(.}<1
-""J3*
~~~~Ei't. K6~'~P
~---------------__;DB7
L . . . . . - - - - - - - - - - - - - - - - - - 1 DB.
0B,
'-------------------1
'-___________________
-;DB,
L....--------------------------------i DB,
L.....________________________________
L.....------------__________________________--;QB,
~DB,
L-----------------------------------------------------------------------;OBo
'---
8049 EMULATOR CIRCUIT
5·17
APPLICATION EXAMPLES
8049 EMULATOR CIRCUIT DESCRIPTION-6 MHZ
The following is an explanation of a circuit which
emulates the operation of an IntelC!> 8049 using a standard EPROM for program storage.
With the 8049, software may be developed by running
external program memory, but dOing so requires the use
of the bus and P23-P20 to access this memory.
The circuit shown may be used to restore the normal
functioning of these twelve 1/0 pins. The circuit consists of an 8039 CPU, 2716 EPROM, two 8216 bidirectional bus drivers, and eight other 7400 Series LowPower Schottky TTL packages. The whole assembly can
be built on a 2-3/4" x 4" board.
A cable coming off the board can be terminated by a
forty-pin plug which may be inserted directly into the
CPU socket intended for the 8049 In a system undergoing design or testing. Alternatively, a pattern of forty
pins extending below the board can be used to plug the
board directly into the system undergoing testing,
"piggy-back" fashion. The emulator board may be configu~ed in various ways so that the 40 pin plug is the
logical equivalent of an. 8049 in every legal operating
mode. (In the following explanation of the operation of
the circuit, an asterisk appearing before a signal or pin
number - as in *PSEN - refers to that pin on the "virtual 8049" represented by the forty-pin plug).
Since the CPU is Identical with the 8049 in all respects
other than its lack of program memory, most of the pins
of the 8039 are simply connected directly to the corresponding pins of the forty-pin plug. These include all
of Port 1, the high order bits of Port 2, the test pins, etc.
Signals which are emulated with additional !.Qgi£...!!!.·
clude the rest of Port 2, DBrDBo, *PSEN, etc. RD, WR,
ALE, and PSEN are obtained from the 8039, but are also
used by the emulation circuitry.
The EA input of the 8039 Is hard-wired high so all instruction fetches are made from the 2716. Two 74LS75
four-bit latches gated by the buffered ALE signal are
used to hold the lower eight bits of address from the
time-multiplexed data bus. Since the Bus is being used
for fetching Instructions, data latched to the Bus will be
lost on the next instruction fetch. Two 74LS174 latches
are used to retain the output data when a bus write is
executed. These latches are triggered by the trailing
edge of the WR pulse, so their outputs are glitch free.
Since logical operations to the bus do not generate a
WR strobe, the "ANL BUS,#" and "ORL BUS,#" instructions may not be used, though they do function properly
with the other ports.
The two 8216 bi-directional bus drivers normally buffer
the latched bus contents to the DB pins of the virtual
8049. When an "INS A,BUS" Instruction is executed,
they buffer the input signals on to the emulator data
bus. Thus, the circuit is designed to use the B1Js for both
.Iatched output and strobed Input. If DB79DBo of the
8049 are to be used solely for input data, J2 and J3 may
be changed from what is shown in the Figure, so that
DBrDBo act as high impedance inputs and the 8216s
are enabled only when the read operation Is performed.
If the bus is to be used only for latched output, the
8216s can be omitted entirely..
Bi-directional data transfers which require the transfer
of address information as well as data, such as to and
from external data memory, require removal of the
8216s and replacement with 16-pin jumper blocks on
which the DBx pins are connected with the respective
DOxpins.
The lower four bits of Port 2 are also used in fetching instructions from the 2716, in addition to their use as input or output pins in the user's system. In configuring
the emulator for a particular application, the user must
dedicate each of these as either an input or output pin
and connect jumper set J1 accordingly. Any mix of input
and output pins is allowed. At the beginning of each instruction fetch, the last data written to P2 will be present on P23-P20 at the rising edge of ALE and will be
latched by a 74LS174. The latched data may be connected through the jumpers to those pins whictl will be
used as outputs on the 8049. Emulator pins used as inputs should be pulled above 2.0V for a logic "one". If
this is not the case, i.e., if switches to Ground are to be
read, 50K pull up resistors should be added to the circuit·
on each input. They were omitted from the diagram to
minimize input loading.
Pins which will be used as inputs may be connected to
the input of an OR gate formed of inverters and opencollector NAND gates. The input signals will be relayed
directly to the 8039 and will be read by an "IN A,P2" Instruction.But when PSEN is low, the NAND outputs are
forced off, allowing the 8039 pins to be used for highorder program adressing. Open-collector 0stputs are
needed to prevent line contention when P EN is not
low.
If 8243s will be be used in the final system, the low order
pins of Port 2 must be connected directly to the plug.
This may be done by replacing the Port 2 latch with four
jumpers connecting the inputs to the outputs. The
NANOs should be removed or disabled by grounding the
common NAND inputs.
The cluster of three OR gates Is used to enable the onboard 2716 and generate the *PSEN Signal, each of
which is a function of PSEN, *EA, and the high order bit
of the program counter. Thus *PSEN is generated, forcing an off-board read, only when a jump has been made
to Memory Bank 1 or when *EA is brought high. If this
feature is to be used to address off-board memory, DBr
DBo may not be used for normal 1/0. The 8216s and
74LS174 must be replaced with jumper blocks and the
open collector NAND gates disabled, as explained
above. The same changes are required to operate the
board in single step mode.
NOTE: FOR EMULATION AT"11 MHZ:
1. Substitute a 2716-1;
2. Delete 74LS03 package (leave lines open). Elimination
of 74LS03 precludes use of P20-P23 as inputs.
5-18
APPLICATION EXAMPLES
DRUM PRINTER'
PRINTER POS.
LINE FEED
RIB SHIFT
SOLENOIDS
8048
BUS
8 DATA IN OR 8080 INTERNAL BUS
RDY/BSY
'SEIKO =101
8048 INTERFACE TO DRUM PRINTER
1000 PULSE/GAL
CS
CS
8251
USART
8243
CS/CD
TO CENTRAL
TERMINAL
NON
SCANNED
3 SCANNED
FUEL
VALVES
9. 9
PRICE
SCAN LINES
MOTOR
MCS-48™ GAS PUMP
5·19
APPLICATION EXAMPLES
CASH DRAW
KEY SWITCH
TOTALS
AUDIO INDICATOR
[J=~"
8748/8048
PROM/ROM
RAM
I/O TIMER
\
INTERRUPT
I
~
DATA & STROBE
STEPPER MOTOR
CONTROL
PAPER ADVANCE
STATUS
-II'
~
TO OPTIONAL
• COMMUNICATIONS
INTERFACE
• READER
• STORE AND FORWA RD
"'i }
},
8279
KEYBOARD DISPLAY
I I
SCAN LINES
,
,
CASH REGISTER KEYBOARD
MATRIX PRINTER'
WITH PAPER
ADVANCE
•
•
•
•
•
NUMERIC
DEPT.
ITEM
TAX
ETC.
'DRUM PRINTER MAY BE USED.
DRUM PRINTER REOUIRES
MORE OUTPUTS WHICH CAN BE
OBTAINED FROM AN EXPANDER
DEVICE.
LOW COST POINT OF SALE TERMINAL
5-20
,
818181 E""
SEGM~NT
FRONT AND
REAR DUAL
DISPLAY
18~
I
INDICATOR LAMP MATRIX FOR
ILLUMINATED KEY TOPS
APPLICATION EXAMPLES
OXYGEN
SENSOR
-t>--
XTAL1
DARLINGTON
DRIVERS
(lOROI
IGNITION
PULSE
~ENGINE SPEED)
•
Tl
8021
OPEN LOOP MODES
WIDE OPEN
COLD ENGINE
DECELERATE
POWER TRAIN
TYPE IDENTIFICATION
ENGINE CRANKING
VEHICLE TYPE
IDENTIFICATION
SIMPLE FEEDBACK CARBURETOR CONTROLLER
FRONT PANEL
4x4
KEYBOARD
STATUS
INDICATORS
, - - - - - - - - - - - > - 1 Vee
~---,/I
120V.60Hz
'-11-"'-"-'
(J (J, DC'
~------->~ITl
60Hz
DISPLAY
TIMING
REFERENCE
8021
Pl0-11
MICROWAVE OVEN CONTROLLER
5-21
APPLICATION EXAMPLES
5.2 Software Examples
The following routines are written as subroutines. RO and R1 are
used as data pointers, R2 is used as an extension of the accumulator
and R3 is used as a loop counter.
RXO
AEX
= RO
= R2
DOUBLE ADD
DADO:
DEC
ADD
INC
XCH
ADDC
XCH
RET
RXO
A,@RXO
RXO
A,AEX
A,@RXO
A,AEX
;GET LOW BYTE AND ADD TO A
;GET HI BYTE AND ADD TO AEX
;RETURN
DOUBLE SUBTRACT
DMIN:
DEC
CPL
ADD
CPL
INC
XCH
CPL
AD DC
CPL
XCH
RET
RXO
A
A,@RXO
A
RXO
A,AEX
A
A,@RXO
A
A,AEX
;GET LOW BYTE AND SUB FROM A
;GET HI BYTEANDSUB FROM AEX
;RETURN
DOUBLE LOAD
OLD:
DEC
MOV
INC
XCH
MOV
XCH
RET
RXO
A,@RXO
RXO
A,AEX
A,@RXO
A,AEX
;GET LOW BYTE AND PLACE IN A
;GET HI BYTE AND PLACE IN AEX
;RETURN
DOUBLE STORE
DST:
DEC
MOV
INC
XCH
MOV
XCH
RET
RXO
@RXO,A
RXO
A,AEX
@RXO,A
A,AEX
;MOVE A INTO LOW BYTE
;MOVE AEX INTO HIGH BYTE
;RETURN
5-22
APPLICATION EXAMPLES
DOUBLE EXCHANGE
DEX:
DEC
XCH
INC
XCH
XCH
XCH
RET
RXO
A,@RXO
RXO
A,AEX
A,@RXO
A,AEX
;EXCHANGE A AND LOW BYTE
;EXCHANGE AEX AND HIGH BYTE
;RETURN
DOUBLE LEFT LOGICAL SHIFT
LLSH:
RLC
XCH
RLC
XCH
RET
A
A,AEX
A
A,AEX
;SHIFT A
;SHIFT AEX
;RETURN
DOUBLE RIGHT LOGICAL SHIFT
RLSH:
XCH
RRC
XCH
RRC
RET
A,AEX
A
A,AEX
A
;SHIFT AEX
;SHIFT A
;RETURN
DOUBLE RIGHT ARITHMETIC SHIFT
RASH:
CLR
CPL
C
C
;SET CARRY
XCH
JB7
CLR
RRC
XCH
RRC
RET
A,AEX
$+3
C
A
A,AEX
A
;IF AEX[7]<>1 THEN
;CLEAR CARRY
;SHIFT C INTO AEX
;SHIFT A
;RETURN
SINGLE PRECISION BINARY MULTIPLY
This routine assumes a one-byte multiplier
and a one-byte multiplicand. The product,
therefore, is two-bytes long.
2. The Accumulator and R1 are shifted
right one place, thus the LSB of the
multiplier goes into the carry.
3. The multiplicand. is added to the
accumulator if the carry bit is a 'one'. No
action if the carry is a 'zero'.
The algorithm follows these steps:
1. The registers are arranged as follows:
ACC-O
R1 - Multiplier
R2 - Multiplicand
R3 - Loop Counter (=8)
The Accumulator and register R1 are
treated as a register pair when they are
shifted right (see Step 2)
4. Decrement the loop counter and loop
(return to Step 2) until it reaches zero.
5. Shift the result right one last time just
before exiting the routine
*The result will be found in the Accumulator
(MS Byte) and R1 (LS Byte).
5-23
APPLICATION EXAMPLES
BINARY MUL TIPL Y
BMPY:
MOV
CLR
CLR
R3,#08H
A
C
;SET COUNTER TO 8
;CLEAR A
;CLEAR CARRY BIT
BMPI:
RRC
XCH
RRC
XCH
JNC
ADD
A
A,R1
A
A,R1
BMP3
A,R2
;DOUBLE SHIFT RIGHT ACC & R1
;INTO CARRY
DJNZ
RRC
XCH
RRC
XCH
R3,BMPI
A
A,R1
A
A,R1
;DECREMENT COUNTER AND LOOP IF 0
;DO A FINAL RIGHT SHIFT AT THE
;END OF THE ROUTINE
BMP3:
;IF CARRY=1 ADD, OTHERWISE DON'T
;ADD MULTIPLICAND TO ACCUMULATOR
INTERRUPT HANDLING
This interrupt routine assumes single level
interrupt. The purpose is to store the status of
the machine at the time the interrupt occurs
by storing contents of all registers, accumulator, and the status word. At the end of the
interrupt the state of the machine is restored
and interrupts are enabled again.
INTRPT: SEL
MOV
RB1
@RO,A
;SAVE WORKING REGISTERS
;RO IN ALTERNATE REGISTER
;BANK CONTAINS SACC
;POINTER FOR SAVING
;ACCUMULATOR
flNTERRUPT SERVICE
lROUTINE
MOV
MOV
RETR
RO,SACC ;RESTORE SACC
A,@RO
;RESTORE ACCUMULATOR
;RESTORE WORKING REGISTERS
;RESTORE PSW AND
;RE-ENABLE INTERRUPTS
5-24
APPLICATION EXAMPLES
2 BYTE PROCESSING SYSTEM
A suggested model of a processing routine
takes two single byte inputs from different
ports, compares them, and performs the
following, depending on the result of the
comparison:
(If Equal) Sets Flag and Exits
(If Not Equal) and Outputs the Larger to a
Third Port
INPUT FIRST OPERAND
INPUT SECOND OPERAND
NOT EQUAL
PROCESS: CLR
IN
MOV
IN
MOV
CPL
INC
ADD
JZ
JNC
MOV
OUTL
JMP
SECOND: MOV
OUTL
JMP
EQUL: CPL
JMP
FO
A,P1
RO,A
A,P2
R1,A
;CLEAR FO BIT (INITIALIZE)
;READ FIRST INPUT, STORE IN
A
A
;SUBTRACT SECOND FROM FIRST
;(2's COMPLEMENT AND ADD)
A,RO
EQUL
SECOND
A,RO
BUS,A
DONE
A,R1
BUS,A
DONE
FO
DONE
RO
;READ SECOND INPUT, STORE IN R1
;BRANCH IF THEY ARE EQUAL
;IF NEGATIVE, SECOND WAS LARGER
;ELSE, OUTPUT FIRST
;EXIT
;OUTPUT SECOND
;EXIT
;SET FO
;EXIT
5·25
APPLICATION EXAMPLES
8 x 8 MULTIPLY-ASSEMBLED BY MCS-48 MACRO ASSEMBLER
SEE AP-49
ISIS-II "CS-48/UPI-41 "ACRO ASSE"8LER, Y3.B
LOC
08J
SOURCE STATEMENT
LI NE
.
III
I ' 112
2' 113
2- 114
2' 115
2- 116
2' 117
2- 118
2· I "
2' 128
2· 121
2' 122
2- 123
2- 124
2- 125
2- 126
2- 127
2- 128
2- 12'
2- 131
2' 131
2- 132
2- 133
2- 134
2- 135
2- 136
2- 137
2- 138
2- 139
2- 141
2- 141
2- 142
2- 143
2- 144
2- 145
1- 146
1- 147
1- 148
SItICLUDE('FI'"PYS)
SI NClUDE(: FI: "PYS. PDl)
.
; •••••••••••••• ** •••••••••• ** •••••••• *******.** •••• ** ••••••••••••••••••••••••••
;.
"PYSXS
I.
I.
j*============================================================================*
I.
"
)'
THIS UTiliTY PROVIDES AN S 8Y e UNSIGNED "UlTIPLY
AT ENTRY'
A • LOWER EIGHT SITS OF DESTINATION OPERAND
KA- ~ON'T CARE
RI' POINTER TO SOURCE OPERAHO <"ULTIPLIER) IN IHTERNAL "E"EORY
"
"
".
I
AT EKIT'
A • LOWER EIGHT 81TS OF RESULT
XA- UPPER EIGHT 81TS OF RESULT
C • SET IF OVERFlOW elSE CLEARED
I.
I.
I.
,.
•
•
" .........................................................•.......•.........•..
;
II "PY8Ke:
1I
II
II
12
13
12
13
13
12
12
11
II
"ULTIPLICAHO[15-SI:=8
COUNT:-9
REPEAT
IF "ULTIPlICAHO[8l-. THEH BEGIH
"UlTIPlICANO""ULTIPLICAHD/2
ELSE
"UlTIPLlCAHO[ 15-9l:'"UlTIPLlCAHO[ 15-9l+"ULTIPLlER
"UlTIPLICAHO'="ULTIPlICAHO/2
ENDIF
COUHT:-COUNT-I
UHTI l COUHT-.
EHO "PYaK9
fEJECT
5-26
APPLICATION EXAMPLES
8 x 8 MULTIPLY-ASSEMBLED BY MCS-48 MACRO ASSEMBLER
SEE AP-49
I SIS-II "CS-48/UPI-41
LOC
OBJ
1835 BAl8
8137 BBIB
8139 1243
813B
813C
8130
Bl3E
Bl3F
Bl48
Bl42
2A
'7
i7
2A
i7
EBl'
83
8843
8844
8845
884'
8847
884B
884A
2A
01
i7
2A
67
EBl'
83
"ACRO ASSE"BLER, Y3 .•
LI NE
I'
11I1=
I'
1=
II1=
IIIIIII'
I1=
I'
II'
I'
II1=
II'
IIII1=
I'
SOURCE STATE"ENT
I n ;·1 "PY8X8:
lSI "PY8X8:
151 ;1 "ULTIPLICAHOI15-8]:'8
XA,188
152
"oy
153 ;1 COUNT: -8
COUNT. 18
154
"oy
155 ;1 REPEAT
15i "PYBLP:
157 ; 2
IF "UlTIPLICANOII]-B THEN BEGIN
158
J8B
"PY8A
15, : 3
"UlTIPlICANO:'"UlTIPlICAHO/2
A, XA
XCH
Iii
Iii
ClR
C
li2
RRC
A
A, XA
XCN
li3
li4
RRC
A
165
OJ HZ
COUNT. "PULP
Ih
RET
167 : 2
ELSE
168 "PY8A:
nUL T I PLI CANOl 15-8] : -nUL T IPLI CANDI 15- 81+"ULT I PLIER
I " :3
A, XA
178
XCH
A, IRI
t 71
AOO
172
RRC
A
A, XA
173
XCN
174
RRC
A
175
OJ NZ
COUNT, "PULP
176
RE T
177 : 3
nUlTIPllCAHO:="ULTIPLICAHD/2
178 ;2
ENOIF
COUNT: 'COUNT-l
17' : 2
188 :1 UNTIL COUNT=8
181 :1 END npY8X8
182 $EJECT
5-27
APP\,JCATION EXAMPLES
16 x 8 DIVIDE-{ASSEMBLED BY MCS-48 MACRO ASS.E.MBLERSEE AP-49)
ISIS-II "CS-48/UPI-41 UCRO ASSE"8LER, Y3.B
LO C
08 J
LI NE
SOURCE STATE"ENT
•
183 UNCLUOE(' Fl' DIYI6)
1= 184 i.*****.************.*******************.****.***·*··· •••••••••••••••••••••••••
*
1=
11=
1=
186 I t
187 ,.
1=
1=
1=
1=
1=
18'
1 ~B
191
192
193
185
l
188
He
,.
,.
'ill
;.
1- 194 ,.
1- 195 ;.,
1 = 19' ;.
1= 197 ,.
1= 19B ,.
2A
BB4C
88B8
BB4E 37
B04F 61
8050 37
USI F65.
BU53 A7
B054 BHF
aD56 61
1= 2BB
1= 2Bl
1- 282
1- 283
1= 284
1= 285
1= 286
1= 207
I- 28B
1= 2B~
1- 21B
1= 211
1= 212
1= 213
1= 214
1= 215
1- 216
I- 217
1= 218
1= 219
1 = 22 B
1= 221
1= 222
1 = 223
B057 ~7
USB 2A
Be" F7
USA 2A
USB F7
BOSC EH3
USE 37
885F 61
BUB 37
DB.l
BHB
1= 224
1= 225
1= 226
I- 227
1= 22B
1= 229
1- 23B
1= 231
1= 232
1= 233
.
THIS UTILITY PROVIDES AN 16 BY 8 UNSIGNED ~IVIDE
AT ENTRY'
A = LOWER EIGHT BITS OF DESTINATION OPERAND
XA= UPPER EIGHT BITS OF DIVIDEND
RI- POINTER TO DIVISOR IN IHTERNAL "EHORY
AT EXIT'
A = LOWER EIGHT BITS OF RESULT
XA= RE"A INDER
C = SET IF OYERFLOW ELSE CLEARED
,*......................................•..•••.•••••••..•.•.•.••...••••••.•••.••
1 = 199 ;
BB 48
;
'1 OIY16'
DIVI6, XCH
;1 COUNT'=S
U64 61
) ROUTINE WORKS "OSTLY WITH 81TS 15-8
nov
COUNT,IS
'1 DIYIDENDI IS-BI'=DIVIDENDI 15-BI-DIVISOR
CPL
A
ADD
A, IIRI
CPL
A
'1 IF BORROW=B THEN /. IT FITS.I
JC
DIVIA
,2
SET OYERFL~W FLAG
CPL
C·
J"P
DIYIB
) 1 ELSE
OIYIA'
'2
RESTORE DIVIDEND
A, @R I
ADO
'2
REPEAT
OIYILP'
)4
DIV!DEND'=DIYIDENO.2
)4
QUOTIEHT,-gUOTIEHT*2
CLR
C
A,XA
XCH
RLC
A
A, XA
XCH
RLC
A
DIYIE
JNC
CPL
A
A, fRl
ADD
cn
1- 234
JHP
1=
1= 236 DIYIE'
1= 237
CPL
ADD
235 ,4
U.3 37
•
0lV16
A
DIVIC
o IV IDEND[ 15-8]' -01 VI DEND[ IS-81-01V1S0R
A
A,9Rl
5-28
APPLICATION EXAMPLES
16 x 8 DIVIDE-{ASSEMBLED BY MCS-48 MACRO ASSEMBLER SEE AP-49)
lSlS-1 I "CS-48/UPI-41 "ACRO ASSEULER. Y3. I
LOC
OBJ
1865 37
1166 E668
IU8 61
II" IHC
1868 IA
886C EB57
886£ 97
Bl6F 2A
1178 83
LINE
I1=
II'
II1=
1=
1=
III1=
1=
1=
1=
1=
1=
II-
SOURCE STATE"ENT
238
CPL
A
2H
IF BORROW-I THEN
24.
JNC
DIYIC
RESTORE DIYIDEND
241
242
A.IRI
ADD
243
DIYID
J"P
244
ELSE
245 DIYIC,
246
QUOTlENTlll"1
247
XA
INC
248
ENDIF
249
COUNT' -COUNT-I
251
UNTIL COUNT=I
251 DIVID, DJNZ
COUNT.DIYILP
252
CLEAR OVERFLOW FLAG
253
C
CLR
254
ENDIF
255
ENDDIVIDE
A.XA
256 DIVIB, XCH
257
RET
5-29
MCS-4STM Component .
Speeific·a llons ·
8048H/8048H-1/8035HLl8035HL-1
HMOS SINGLE COMPONENT 8-BIT MICROCOMPUTER
• 8048H/8048H-1 Mask Programmable ROM
• 803SHL/8035HL-1 CPU Only with Power Down Mode
ROM
• 641K xx 88 RAM
CPU, ROM, RAM, I/O In Single
• 8-BIT
Package
• High Performance HMOS
• Reduced Power Consumption
1.4 usec and 1.9 usec Cycle Versions
• All
Instructions 1 or 2 Cycles.
• Over 90 Instructions: 70% Single Byte
271/0 Lines
• Interval Timer/Event Counter
• Easily Expandable Memory and I/O
with 8080/8085 Series
• Compatible
Peripherals
• Two Single Level Interrupts
The IntelG!! S04SH/S04SH-1/S035HL/S035HL-1 are totally self-sufficient, 8-bit parallel computers fabricated
on single silicon chips using Intel's advanced N-channel silicon gate HMOS process.
The S04SH contains a 1K X S program memory, a 64 X S RAM data memory, 27 I/O lines, and an S-bit
timer/counter in addition to on-board oscillator and clock circuits. For systems that require extra capability
the S04SH can be expanded using standard memories and MCS-SO™/MCS-85''' peripherals. The S035HL is
the equivalent of the S04SH without program memory and can be used with external ROM AND RAM.
To reduce development problems to a minimum and provide maximum flexibility, a logically and functionally
pin compatible version of the S04SH with UV-erasable user-programmable EPROM program memory is available. The S74S will emulate the S04SH up to 6 MHz clock frequency with minor differences.
The S04SH is fully compatible with the S04S when operated at 6 MHz.
These microcomputers are designed to be efficient controllers as well as arithmetic processors. They have
extensive bit handling capability as well as facilities for both binary and BCD arithmetic. Efficient use of
progra'm memory results from an instruction set consisting mostly of single bit instructions and no in.
structions over 2 bytes in length.
PIN CONFIGURATION
PORT
=1
XTALI
XTALI
IIH!T
III
BLOCK DIAGRAM
LOGIC SYMBOL
4
&
EA
iii!
Pm!
Wi!
ALE
DBO
DBI
DB2
DB3
DB4
DBS
DBa
PH
PORT
=I
PI5
PI4
P17
P1S
P15
8048H
8035HL
8048H-1
8035HL-1
P14
P13
P12
Pl1
Pl0
VDD
PROG
P23
DB7
P22
P21
Vss
P20
BUS
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied.
AFN-OI491A-Ol
Olntel Corporation 1980
6-1
intel"
S04SH/S04SH-1/S035HL/S035HL-1
~!ru~[!"o!MlOOO~OOW
PIN DESCRIPTION
Designation
Pin =
Function
VSS
VDD
20
Circuit GND potential
26
low power standby pin
VCC
40
Main power supply; +5V
during operation.
PROG
25
Output strobe for 8243 I/O
expander.
P10-P17
Port 1
P20-27
Port 2
27-34 . 8-bit quasi-bidirectional
port.
21-24 8-bit quasi~bidirectional
port.
35-38 P20-P23 contain the four
high order program counter
bits during an external program memory fetch and
serve as a 4-bit I/O expander
bus for 8243.
DBO-DB7
BUS
12-19
Designation
RD
Input pin testable using the
JT1, and JNT1 instructions.
Can be designated the
timer/counter input using
the STRT CNT instruction.
INT
6
Interrupt input. Initiates an
interrupt if interrupt is
enabled. Interrupt is disabled after a reset. Also
Output strobe activated
during a BUS read. Can be
used to enable data onto the
bus from an external device.
RESET
4
Input which is used to
initialize the processor.
(Active low)
(Non TTL VI H)
WR
10
Output strobe during a bus
write. (Active low)
Used as write strobe to
external data memory.
ALE
11
Address latch enable. This
signal occurs once during
each cycle and is useful as a
clock output.
The negative edge of ALE
strobes address into external data and program
memory.
Input pin testable using the
conditional transfer instructions JTO and JNTO. TO
can be designated as a clock
output using ENTO ClK
instruction.
39
8
Used as a read strobe to
external data memory.
(Active low)
True bidirectional port
which can be written or read
synchronously using the
RD, WR strobes. The port
can also be statically
latched.
T1
Function
testable. with conditional
jump instruction.
(Active low)
Contains the 8 low order
program counter bits during
an external program
memory fetch, and receives
the addressed instruction
under the control of PSEN.
Also contains the address
and data during an external
RAM data store instruction,
under control of ALE, RD,
and WR.
TO
Pin =
PSEN
9
Program store enable. This
output occurs only during a
fetch to external program
memory. (Active low)
SS
5
Single step input can be
used in conjunction with
ALE to "single step" the
processor through each
instruction. (Active low)
EA
7
External access input which
forces all program memory
fetches to reference external
memory. Useful for emulation and debug, and
essential for testi ng arid
program verification.
(Active high)
XTAl1
2
One side of crystal input for
internal oscillator. Also
input for external source.
(Non TTL VI H)
XTAl2
3
Other side of crystal input.
AFN~01491A-02
6-2
S04SH/S04SH-1 /S035HL-1/S035H L-1
INSTRUCTION SET
Accumulator
Subroutine
Description
Add register to A
ADD A, R
ADD A,@R
Add data memory to A
ADD A, # data
Add immediate to A
Add register with carry
ADDCA, R
ADDCA,@R
Add data memory with carry
ADDC A, # data Add immediate with carry
And register to A
ANL A, R
And data memory to A
ANL A,@R
ANL A, # data
And immediate to A
ORL A, R
Or register to A
Or data memory to A
ORL A@R
ORL A, # data
Or immediate to A
XRL A, R
Exclusive or register to A
XRLA,@R
Exclusive or data memory to A
XRL, A, # data
Exclusive or immediate to A
INC A
Increment A
DEC A
Decrement A
Clear A
CLR A
CPL A
Complement A
Decimal adjust A
DA A
Swap nibbles of A
SWAP A
Mnemonic
RL A
RLC A
RR A
RRCA
Rotate A left
Rotate A left through carry
Rotate A right
Rotate A right through carry
Bytes Cycles
I
I
I
I
Mnemonic
CALL addr
RETR
RETR
2
2
I
I
I
I
2
2
Flags
I
I
I
I
Mnemonic
2
2
I
I
I
I
2
2
I
I
I
I
2
2
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
CLR
CPL
CLR
CPL
CLR
CPL
IN A, P
OUTL P, A
ANL p, # data
ORL P, # data
INS A, BUS
OUTL BUS, A
ANL BUS, # data
ORL BUS, # data
MOVD A,P
MOVD p, A
ANLD P, A
ORLO p, A
Description
Input port to A
Output A to port
And immediate to port
Or immediate to port
Mnemonic
MOVA, R
MOVA,@R
MOV A, # data
MOV R. A
MOV@R.A
MOV R. # data
MOV @R, #data
MOVA, PSW
MOV PSW, A
XCH A, R
XCH A,@R
XCHDA,@R
Bytes Cycles
I
2
2
I
2
2
Input BUS to A
Output A to BUS
And immediate to BUS
Or immediate to BUS
2
2
I
I
Input expander port to A
Output A to expander port
And A to expander port
Or A to expander port
I
I
I
I
MOVX A,@R
MOVX@R,A
MOVPA,@A
MOVP3A, @
2
2
2
2
2
2
2
2
2
2
INC R
INC@R
DEC R
Description
Increment register
Increment data memory
Decrement register
Bytes Cycles
I
I
1
I
I
I
Description
Jump unconditional
Jump indirect
Decrement register and skip
Jump on carry = 1
Jump on carry = 0
Jump on A zero
Jump on A not zero
Jump on TO = I
Jump on TO =
Jump on T1 = 1
Jump on TI =
Jump on FO = 1
Jump on FI = I
Jump on timer flag
Jump on INT = 0
Jump on accumulator bit
a
a
Bytes Cycles
2
I
2
2
2
2
2
2
2
2
2
2
2
2
2
2
CLear flag 0
Complement flag 0
Clear flag I
Complement flag 1
2
Bytes Cycles
Description
Move register to A
I
1
I
I
Move data memory to A
Move immediate to A
2
2
Move A to register
I
I
I
Move A to data memory
I
Move immediate to register
2
2
Move immediate to data memory
2
2
Move PSW to A
Move A to PSW
Exchange A and register
Exchange A and data memory
Exchange nibble of A and
register
Move external data memory to A
Move A to external data memory
Move to A from current page
Move to A from page
3
I
I
I
I
I
I
I
I
I
I
I
I
I
2
2
2
2
Description
MOVA, T
MOVT, A
STRT T
STRT CNT
STOP TCNT
EN TCNTI
DIS TCNTI
Read timer/counter
Load timer/counter
Start timer
Start counter
Stop timer/counter
Enable timer/counter interrupt
Disable timer/counter interrupt
Bytes Cycles
I
I
I
I
I
I
I
I
I
I
I
I
I
1
EN I
DIS I
SEL RBO
SEL RBI
SEL MBO
SEL MBI
ENT a CLK
Description
Enable external interrupt
Disable external interrupt
Select register bank a
Select register bank 1
Select memory bank a
Select memory bank 1
Enable clock output on TO
Byles, Cycles
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Mnemonic
Description
NOP
No operation
Byles Cycles
I
I
Control
Branch
JMP addr
JMPP@A
DJNZ R, addr
JC addr
JNC addr
JZ addr
JNZ addr
JTO addr
JNTO addr
JTI addr
JNTI addr
JFO addr
JFI addr
JTF addr
JNI addr
JBb addr
Bytes Cycles
I
I
I
I
I
I
I
I
I
I
I
I
2
Mnemonic
Mnemonic
Mnemonic
Description
Clear carry
Complement carry
2
Timer/Counter
Registers
Mnemonic
Bytes Cycles
Data Moves
Input/Output
Mnemonic
C
C
FO
Fa
FI
FI
Description
Jump to subroutine
Return
Return and restore status
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
6-3
AFN-01491A-03
inter
8048H/8048H-1/8035HL/8035HL;.1
• COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device. This. is a stress rating only and functional
operation of device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied.
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias ....... o·e to 70·e
Storage Temperature ............... -65· e to + 125· e
Voltage On Any Pin With Respect
to Ground ............................ -O.5V to +7V
Power Dissipation ......................... 1.5 Watt
D.C. AND OPERATING CHARACTERISTICS TA =0·Cto70°C, VCC =VDD = 5V± 10%, VSS =OV
Limits
Symbol
Test Conditions
Unit
Parameter
Typ.
Min.
Max.
V IL
Input Low Voltage
(All Except RESET, X1, X2)
-.5
.a
V
VIL1
Input Low Voltage
(RESET, X1, X2)
-.5
.6
V
VIH
Input High Voltage
(All Except XTAL 1, XTAL2, RESET)
2.0
VCC
V
VIH1
Input High Voltage (X1, X2, RESET)
3.8
Output Low Voltage (BUS)
VCC
.45
V
VOL
VOL1
V
VOL = 2.0 mA
OutP~ow
Voltage
(RD, WR, PSEN, ALE)
.45
V
IOL = 1.a mA
VOL2
VOL3
Output Low Voltage (PROG)
.45
V
IOL = 1.0 mA
Output Low Voltage
(All Other Outputs)
.45
V
IOL = 1.6 mA
VOH
VOH1
Output High Voltage (BUS)
2.4
V
IOH = -400 f.1A
Outp~igh
Voltage
(RD, WR, PSEN, ALE)
2.4
V
IOH = -100 f.1A
VOH2
Output High Voltage
(All Other Outputs)
2.4
V
IOH=-40f.1 A
1L1
Input Leakage Current (T1, INT)
±10
f.1A
VSS
IU1
Input Leakage Current
(P10-P17, P20-P27, EA, SS)
-500
f.1A
VSS + .45~VIN~VCC
ILO
Output Leakage Current (BUS, TO)
(High Impedance State)
± 10
f.1A
VSS + .45~VIN~VCC
100
100+
ICC
VOO Supply Current
Total Supply Current
4
40
a
mA
ao
mA
BUS. Pl. P2
Pl, P2
BUS
-500
50 mA
~A
930 mA
:t -300 ~
:t
9
9
10mA
w10D JiA
4V
OV
OV
VOH
6-4
< VIN < VCC
~
~
2V
4V
VOL
AFN-01491A-04
inter
8048H/8048H-1/8035HL/8035HL-1
A.C. CHARACTERISTICS (PORT 2 TIMING) TA
=O°C to 70°C, VCC =5V± 10%, VSS =OV
8048H-1
8035HL-1
8048H
8035HL
Symbol
Parameter
6 MHz
Min.
Max.
8 MHz
Min.
11 MHz
Max.
Min.
Unit
Max.
tcp
Port control Setup Before Falling
Edge of PAOG.
110
105
ns
tpc
Port Control Hold After Falling
Edge of PAOG.
100
90
ns
tpA
PAOG to Time P2 Input Must Be Valid
tpF
Input Data Hold Time
top
Output Data Setup Time
250
210
200
ns
tpo
Output Data Hold Time
65
35
20
ns
tpp
PAOG Pulse Width
1200
970
700
ns
tpL
Port 2 1/0 Data Setup
350
300
250
ns
tLP
Port 2 1/0 Data Hold
150
65
20
ns
810
0
150
700
0
150
0
650
ns
150
ns
PORT 2 TIMING
ALE
J
\'-------~
\'---------r~1
-+CA~
EXPANDER
PORT
OUTPUT
rIOp---tIPD
PCH
I
PORT CONTROL
OUTPUT DATA
EXPANDER
PORT
INPUT
PCH
r
PROG
lPp
BUS TIMING AS A FUNCTION OF TCY *
SYMBOL FUNCTION OF TCY
SYMBOL FUNCTION OF TCY
7/30
MIN
MAX TAD (1): AD
TLL
TAD (1) 11/30
TCY
TCY
1/10
MIN
MAX TAD (2) : PSEN
TAL
TAD (2) 3/10
TCY
TCY
1/15
MIN
3/10
MIN
TLA
TCY
TAW
TCY
MIN T CC (1) : AolWA TAD (1) 1/2
TCC (1) 1/2
MAX
TCY
TCY
MIN T CC (2) : PSEN
TCC (2) 2/5
MAX TAD (1): AD
TAD (2) 1/3
TCY
TCY
2/15
MIN
TOW
1/30
TCY
TAFC
TCY MIN TAD (2) : PSEN
1/15
MIN
1/15
MIN
TWO
TCY
TCY
TCA
0
MIN
ToA
• APPROXIMATE VALUES NOT INCLUDING GATE DELAYS.
6-5
AFN-01491A-05
S04SH/S04SH-1/S035HL/S035HL-1
WAVEFORMS
~~~----tCY-----
~tLL-1
ALE
J
---!
!-I_ _ _ _ _
L
ALE
J
~tcc--I
I
Rii
-------1\
tAFCj
BUS
L
I
fIFLOATING
tCA
1-
I
-I ttDR
_ _ _ __
~
FLOATING
~tAD~1
Read From External Data Memory
ALE
J
_I tCA 1--
L
--'x::: ~
r----
2.4V - - - . . . . . . .
O.45V _ _ _
TEST POINTS
~~::X'--___
BUS
Input and Output for A.C.Tests.
Write to External Data Memory
A.C. CHARACTERISTICS TA = O°C to 70°C VCC = VDD = 5V ± 10%. VSS = OV
8048H
8035HL
Symbol
8048H-1
8035HL-1
Parameter
6 MHz
11 MHz
8 MHz
Conditions
Min. Max. Min. Max. Min. Max. Unit (Note 1)
tLL
ALE Pulse Width
400
270
150
ns
tAL
Address Setup to ALE
75
75
70
ns
tLA
Address Hold from ALE
65
65
50
ns
tcc
Control Pulse Width (PSEN, RD, WR) 700
490
300
ns
tow
Data Setup before WR
370
370
280
ns
two
Data Hold after WR
80
80
40
ns
ICY
Cycle Time
2.5
tOR
Data Hold
0
tRD
~,
tAW
Address Setup to WR
tAD
Address Setup to Data In
tAFC
Address Float to RD, PSEN
teA
Control Pulse to ALE
I!il5 to Data In
NOTE 1: Control outputl
BUS outputl
1.875
200
0
500
230
1.36
150
0
340
210
950
/ls
100
ns
200
ns
ns
200
400
650
CL =20pF
(NOTE 2)
ns
0
0
-1
ns
10
10
0
ns
NOTE 2: BUS High Impedance Load: 20 pF
CL=80pF
CL,; 150 pF
6-6
AFN·OI491A·06
8048H/8048H·1/8035HL/8035HL·1
CRYSTAL OSCILLATOR MODE
l
~ L. T--
Cf-1_-"r--_~"'-_~Z XTAL 1
cz ••
--T--
-
I
1-_-'-_ _....._ _....:j3 XTAL Z
C;
<
C1 = 5pF ± 1/2pF + STRAY 5pF
C2 = CRYSTAL + STRAY 8pF
C3 = 20pF ± 1pF + STRAY 5pF
<
<
CRYSTAL SERIES RESISTANCE SHOULD BE LESS THAN 75D AT 6 MHz LESS THAN 180D AT 3.6MHz
LC OSCILLATOR MODE
L
45pH
120pH
C
ZOpF
ZllpF
NOMINAL 1
5.2 MHz
3.2 MHz
F~
1
'"2iiiJLc'
2 XTAL1
C~~
d
_
Z
C
L
'"[C
3 XTALZ
Cpp ~ 1>010 pF PIN TO PIN
CAPACITANCE
EACH C SHOULD BE APPROXIAMTELY 2OpF.INCLUDING STRAY CAPACITANCE
DRIVING FROM EXTERNAL SOURCE
+IV
470D
....+-_ _ _....;2'"1 XTALI
+5V
470D
L--+--=-tXTAL2
XTAL 1 MUST BE HIGH 35-65% OF THE PERIOD AND XTAL 2 MUST BE HIGH 35-65'10 OF THE
PERIOD. RISE AND FALL TIMES MUST NOT EXCEED 20nl.
6-7
AFN-01491A-07
8048L
SPECIAL LOW POWER CONSUMPTION SINGLE
COMPONENT 8-BIT MICROCOMPUTER
• Typical Power Consumption 100mW
Standby Power 10mW
• Typical
Voo minimum of 2.2V
1K x 8 ROM
• 64x8RAM
271/0 Lines
• Interval Timer/Event Counter
• Easily Expandable Memory and I/O
• Compatible with 8080/8085 Series
CPU, ROM, RAM, I/O in Single
• 8-Bit
Package
Instruction Cycle.
• 4.17
All Instructions 1 or 2 Cycles.
~sec
Peripherals
• Two Single Level Interrupts
• Over 90 Instructions: 70% Single Byte
The Intel® 8048L is a totally self-sufficient 8-bit parallel computer fabricated on a single silicon chip using Intel's
advanced N-channel silicon gate HMOS process, using special techniques to reduce operating and standby
power consumption. The 8048L contains a 1K X 8 program memory, a 64 X 8 RAM data memory, 271/0 lines, and
an 8-bit timer/counter in addition to on-board oscillator and clock circuits. For systems that require extra
capability the 8048L can be expanded using standard memories and MCS-80™/MCS-8S'" peripherals. The 8048L
can be used with external ROM AND RAM.
To reduce development problems to a minimum and provide maximum flexibility, a logically and functionally pin
compatible version of the 8048L with UV-erasable user-programmable EPROM program memory is available. The
8748 will emulate the 8048L with greater power and other minor differences.
This microcontroller is designed to be an efficient controller as well as an arithmetic processor. The 8048L has
extensive bit handling capability as well as facilities for both binary and BCD arithmetic. Efficient use of program
memory results from an instruction set consisting mostly of single byte instructions and no instructions over two
bytes in length.
PIN CONFIGURATION
TO
XTAL 1
Vee
T1
XTAL 2
P27
RESET
P2S
ss
P25
INT
P2'
EA
P17
Rll
P1S
PSEN
P15
WR
P1'
ALE
P13
DBo
P12
DB,
P11
DB2
P10
DB3
VDD
DB.
PROG
DB5
P23
DBS
P22
DB7
P21
VSS
P20
BLOCK DIAGRAM
LOGIC SYMBOL
PORT
01
PORT
e 2
8048L
BUS
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied
©Intel Corporation 1980
AFN-01591A-01
6-8
8048/8035L/87 48/87 48·6/8035
SINGLE COMPONENT 8·BIT MICROCOMPUTER
•
•
•
•
•
8048 Mask Programmable ROM
8035L CPU Only with Power Down Mode
8748 User Programmable EPROM
8748·6 Up to 55C 8748
8035 CPU Only (No Power Down Mode)
• 8·BIT CPU, ROM, RAM, 1/0 in Single
Package
• 1K x 8 ROMIEPROM
64x 8 RAM
27110 Lines
• Interchangeable ROM and EPROM
Versions
• Interval TimerlEvent Counter
• Single 5V Supply
• Easily Expandable Memory and 1/0
• 2.5 fJsec and 5.0 fJsec Cycle Versions
All Instructions 1 or 2 Cycles.
• Compatible with 808018085 Series,
Peripherals
• Over 90 Instructions: 70% Single Byte
• Single Level Interrupt
The Intel 8048/8748/8743-6/8748-B/8035/B035-8 are totally self-sufficient, 8-blt parallel computers fabricated on single
silicon chips using Intel's N-channel silicon gate MOS process.
The B048 contains a 1K x B program memory, a 64 x B RAM data memory, 27 I/O lines, and an 8-blt timer/counter in addition to on-board oscillator and clock circuits. For systems that require extra capability, the 8048 can be expanded using
standard memories and MeS-BO /MeS-B5 peripherals. The 8035 Is the equivalent of an 8048 without program memory
and can be used with external ROM and RAM. The B035L has the RAM power-down mode of the 804B while the 8035 does
not. The 8748-6 is a 6 MHz B74B up to 55e. To reduce development problems to a minimum and provide maximum flexibility, three interchangeable pin-compatible versions of this single component microcomputer exist: the 8748 with userprogrammable and erasable EPROM program memory for prototype and preproduction systems, the B04B with factoryprogrammed mask ROM program memory for low cost, high VOlume production, and the B035 without program memory
for use with external program memories.
These microcomputers are designed to be efficient controllers as weil as arithmetic processors. They have extensive bit
handling capability as weli as facilities for both binary and BeD arithmetic. Efficient use of program memory results from
an instruction set consisting mostly of single bit instructions and no instructions over 2 bytes in length.
PIN CONFIGURATION
LOGIC SYMBOL
BLOCK DIAGRAM
8048
8035L
8748
8748·6
8035
ADDRESS
L.ATCH
ENABLE
PORT
EXPANDER
STROBE
INTEL CORPORATION ASSUMES NO RESPONSIBILITY FOR THE USE OF ANY CIRCUITRY OTHER THAN CIRCUITRY EMBOOIEO IN AN INTEL PROOUCT. NO OTHER CIRCUIT PATENT LICENSES ARE IMPLIEO.
6-9
AFN.Q1354A.Ql
8048/8035L/8748/8748-6/8748-8/8035/8035-8
PIN DESCRIPTION
Designation
Pin #
Function
Designation
Vss
20
Circuit GND potential
RD
Voo
26
Programming power supply; +25V
during program, +5V during operation for both ROM and PROM.
low power standby pin in 8048
and 8035l.
Vee
40
Main power supply; +5V during
operation and programming.
PROG
25
Program pulse (+23V) input pin
during 8748 programming.
Output strobe for 8243 1/0
expander.
P10-P17
Port 1
P20-P27
Port 2
DBa-DB7
BUS
Pin #
8
Function
Output strobe activated during a
BUS read. Can be used to enable
data onto the bus from an external
device.
Used as a read strobe to external
data memory. (Active low)
RESET
4
Input which is used to initialize the
processor. Also used during PROM
programming verification, and
power down. (Active low)
(Non TTL VIH )
WR
10
27-34
8-bit quasi-bidirectional port.
Output strobe during abus write.
(Active low)
21-24
35-38
8-bit quasi-bidirectional port.
Used as write strobe to external
data memory.
12-19
P20-P23 contain the four high
order program counter bits during
an external program memory fetch
and serve as a 4-bit I/O expander
bus for 8243.
True bidirectional port which can
be written or read synchronously
using the RD, WR strobes. The
port can also be statically latched.
Contains the 8 low order program
counter bits during an external
program memory fetch, and receives
the addressed instruction under the
control of PSEN. Also contains the
address and data during an external
RAM data store instruction, under
control of ALE, RD, and WR.
TO
Input pin testable using the conditional tranSfer instructions JTO
and JNTO. TO ca n be designated as
a clock output using ENTO ClK
instruction. TO is also used during
programming.
Tl
39
Input pin testable using the JTl,
and JNTl instructions. Can be designated the timer/counter input using
the STRT CNT instruction.
INT
6
Interrupt input. Initiates an interrupt if interrupt is enabled. Interrupt is disabled after a reset. Also
testable with conditional jump
instruction. (Active low)
ALE
11
Address latch enable. This signal
occurs once during each cycle and
is useful as a clock output.
The negative edge of ALE strobes
address into external data and program memory.
PSEN
9
Program store enable. This output
occurs only during a fetch to external program memory. (Active low)
SS
5
Single step input can be used in conjunction with ALE to "single step"
the processor through each instruction. (Active low)
EA
7
External access input which forces
all program memory fetches to reference external memory. Useful
for emulation and debug, and
essential for testing and program
verification. (Active high)
XTAL1
2
One side of crystal input for internal oscillator. Also input for external source. (Non TTL VIH)
XTAl2
3
Other side of crystal input.
6-10
AFN-01354A-02
6-11
AFN-Q1354A-03
8048i8035L/8748/8748-6/8748-8/8035/8035-8
ABSOLUTE MAXIMUM RATINGS·
'COMMENT: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those Indicated in the operational sections of this
specification Is not Implied.
Ambient Temperature Under Bias ........... ooe to "70 0 e
Storage Temperature ........................... -65°e to +125°e
Voltage On Any Pin With Respect
to Ground .................................................. -o.5V to·+7V
Power Dissipation ............................................... 1.5 Watt
D.C.AND OPERATING CHARACTERISTICS
TA
(TA
= O'Ct070'C,Vcc = Voo = +5V
=O'C to 55'C for 8748-6)
%
10%,Vss
= OV
Limits
Symbol
Test Conditions
Unit
Parameter
Min.
Typ.
Max.
V IL
Input Low Voltage
(All Except RESET, X1, X2)
-.5
.8
V
VIL1
Input Low Voltage
(RESET, X1, X2)
-.5
.6
V
V IH
Input High Voltage
(All Except XTAL1, XTAL2, RESET)
2.0
VCC
V
VIH1
Input High Voltage (X1, X2, RESEi')
3.8
VOL
VOL1
VCC
.45
V
Output Low Voltage (BUS)
V
VOL
.45
V
10L = 1.8 mA
VOL2
VOL3
Output Low Voltage (PROG)
.45
V
10L = 1.0 mA
Output Low Voltage
(All Other Outputs)
.45
V
10L = 1.6 mA
VOH
VOH1
VOH2
Output Low Voltage
(RO, WR, PSEN, ALE)
=2.0 mA
Output High Voltage (BUS)
2.4
V
10H = -400 /1 A
Output High Voltage
(RO, WR, PSEN, ALE)
2.4
V
10H = -100 /1 A
Output High Voltage
(All Other Outputs)
2.4
V
10H = -40 /1A
< VIN < VCC
IL1
Input Leakage Current (T1, INT)
± 10
/1A
VSS
IU1
Input Leakage Current
(P10-P17, P20-P27. EA, SS)
-500
/1A
VSS + .45~VIN~VCC
I LO
Output Leakage Current (BUS. TO)
(High Impedance State)
± 10
/1A
VSS + .45~VIN~.vCC
100
100+
ICC
VOO Supply Current
5
15
rnA
Total Supply Current
60
135
rnA.
SOmA
-500 /JA
% 0300
/J
9 30mA
9
10mA
·100/JA
OV
VOH
BUS,Pt, P2
Pt, P2
BUS
OV
VOH
6-12
e
2V
VOL
4V
8048/8035L/8748/8748-6/8748-8/8035/8035-8
WAVEFORMS
Instruction Fetch From External Program Memory
I===i---
J
ALE
Read From External Data MemorY
·1
h
IL--_ _ _~I---'L
J
ALE
L
1-- 'ee --I
----II
RD
I---
'eA
.1
i,'OR
'm ~I I~FLOATlNG~1
~
BUS
BUS
--FL-O-AT-'N-G--
1.'Ro-1
1
- tAD - -
Write to External Data Memory
Input and Output Waveforms for A.C. Tests
J
ALE
L
WR
2.4----"'"\
2.2-...
..,2.2V
_ _ _ _ _J) ( O,S-- TEST POINTS ........ O.
sA
0.45
'-----
BUS
A.C. CHARACTERISTICS
T A = O·C to WC', Vee = VDD
= + 5V ;: 10% ,Vss = OV
8048
Symbol
.1
8748-6
Parameter
874818035/8035L
Min.
Max.
18748-8**
8035·8
Min. Max.
Unit I
tLL
ALE Pulse Width
400
600
ns
tAL
Address Setup to ALE
120
150
ns
tLA
Address Hold from ALE
80
80
ns
tcc
Control Pulse Width (PSEN, RO, WR)
700
1500
ns
tow
Data Setup before WR
500
640
ns
two
Data Hold After WR
120
tCY
Cycle Time
2.5
tOR
Data Hold
tRO
PSEN, RO to Data In
tAW
Address Setup to WR
tAO
Address Setup to Data In
tAFC
Address Float to RD, PSEN
tCA
Control Pulse to ALE
Note t: Control outputs'
BUS Outputs:
U
CL = SO pF
CL= tSO pF
15,0
200
ns
CL
IJS
6 MHz XTAL=2.5
(3.6 MHz XTAL for - 8
0
200
750
950
ns
ns
ns
260
1450
ns
0
0
ns
10
20
ns
ICV = 2.5 ~s lor standard parts
=4.17 ~s lor-8 parts
6-13
= 20pF
120
4.17 15.0
500
230
Conditions (Note 1)
*T A = O·Cto55-Cfor8748-8
uVCCand VOO for 8748-8 and 8035-6 are ±5'1.
AFN'()I354A-05,
8048/8035L/8748/8748-8/i748-8/8035/8035~8
A.C. CHARACTERISTICS (PORT 2 TIMING)
TA = O°C to 70°C, VCC= SV~ 10%, \(ss= OV
(TA = O°C to 55°C for 8748-6)
TA= -40'Cto +8S'C, VCC=5V ::1:10%, VSS=OV
Symbol
Parameter
Min.
tcp
Port Control Setup Before Failing Edge of PROG
115
tpc
Port Control Hold After Falling Edge of PROG
65
tpR
PROG to Time P2 Input Must Be Valid
tpF
Input Data Hole! Time
top
Output Data Setup Time
0
Max.
Unit
rest Conditions
ns
ns
860
ns
160
ns
230
ns
tpo
Output Data Hold Time
25
ns
tpp
PROG Pulse Width
920
ns
tpL
Port 2 110 Data Setup
300
ns
tLP
Port 2110 Data Hold
120
ns
PORT 2 TIMING
ALE
EXPANDER
PORT
OUTPUT
PC"
EXPANDER
PORT
INPUT
PC"
PROG
6-14
AFN-OI354MJ8
8048/8035L/8748/8748-6/8748-8/8035/8035-8
LC OSCILLATOR MODE
CRYSTAL OSCILLATOR MODE
C1
~
.....
f--""T--...,.---=-t2
I
C
XTAL 1
~
.l.
.£.
. 45"H
20 pF
5.2 MHz
120"H
20pF
3.2 MHZ.....-_.__-"'l2 XTAL1
HIMHz
_-1___ .---.
2 .... -i-...
'---I
I
I
r--~--~--~
XTAL2
L - _....._~3 XTAL2
C3
C2. 5pF + 1f2pF + STRAY 6pF
C2 • CRYSTAL + STRAY 8pF
C3. 20pF + 1pF + STRAY 6pF
c•• = 5 -10 pF PIN·TO·PIN
CAPACITANCE
EACH C SHOULD BE APPROXIMATELY 20 pF, INCLUDING STRAY CAPACITANCE.
CRYSTALSERIES RESISTANCE SHOULO BE LESS THAN 7& AT 8MHz: LESS THAN
180 AT S.BMHz.
DRIVING FROM EXTERNAL SOURCE
+SV
47012
10-+-_ _ _ _2=-1 XTAL1
+5V
470Q
L - _....._....:3"'XTAL2
FOR XTAL 1 ANDXTAL2DEFINE"HIGH" ASVOLTAGESABOVE 1.8VAND "LOW"
AS VOLTAGES BELOW 1.8V. THE DUTY CYCLE REQUIREMENTS FOR EXTERNALLY DRIVING XTAL 1 AND XTAL 2 USING THE CIRCUIT SHOWN ABOVE ARE AS
FOLLOWS:
FOR THE 8046, XTAL 1 MUST BE HIGH 35-85'110 OF THE PERIOD AND XTAL 2
MUST BE HIGH 36-85'110 OF THE PERIOD.
. FOR THE 8748. XTAL MUST BE HIGH 48-t10'II0 OFTHE PERIOD AND XTAL 2 MUST
BE HIGH 50-65'110 OF THE PERIOD.
RISE AND FALL TIMES MUST NOT EXCEED IOn••
PROGRAMMING, VERIFYING, AND
ERASING THE 8748 EPROM
WARNING:
An attempt to program a mis-socketed 8748 wlil result In
severe damage to the part. An indication of a properly
socketed part is the appearance of the ALE clock output. The lack of this clock may be used to disable the
programmer.
The ProgramlVerify Sequence Is:
Programming Verification
1. Voo = SV, clock applied or internal oscillator operating, AESET=OV, TEST O=SV, EA=SV, BUS and
PAOG fioating.
In brief, the programming process consists of: activat·
ing the program mode, applying an address, latching the
address, applying data, and applying a programming
pulse. Each word is programmed compietely before
moving on to the next and is followed by a verification
step. The following is a list of the pins used for programming and a description of their functions:
2. Insert 8748 in programming socket.
3. TEST 0 = OV (select program mode).
4. EA = 23V (activate program mode),
S. Address applied to BUS and P20-1.
6. AESET = SV (latch address).
Pin
XTAL1
Function
AESET
Initialization and Address Latching
TEST 0
Selection of Program or Verify Mode
EA
Activation of ProgramlVerify Modes
BUS
Address and Data Input
Data Output during Verify
P20-1
Address Input
Voo
PAOG
7. Data applied to BUS.
Clock Input (1 to 6 MHz)
8. Voo = 2SV (programming power).
9. PAOG = OV followed by one SO ms pulse to 23 V.
10. Voo=SV.
11. TEST 0 = SV (verify mode).
12. Read and verify data on BUS.
13. TEST O=OV.
14.
Programming Power Supply
FiES'E'f = OV and repeat from step S.
1S. Programmer should be at conditions of step 1 when
8748 is removed from socket.
Program Puise Input
6-1S
AFN..Q1364A..Q7
8048/8035L/8748/8748~6/8748-8/8035/8035-8
AC TIMING SPECIFICATION FOR PROGRAMMING
TA
= 2SOC ± SoC, Vee = SV ± S%, Voo = 2SV ± 1V
Min.
Parameter
Symbol
tAW
Address Setup Time to RESET t
4tcy
tWA
Address Hold Time After RESET I
4tcy
tow
Data in Setup Time to PROG I
4tcy
two
Data in Hold Time After PROG !
4tcy
tPH
RESET Hold Time to Verify
4tcy
tvoow
Voo
4tcy
tVOOH
Voo Hold Time After PROG !
0
tpw
Program Pulse Width
50
tTW
Test 0 Setup Time for Program Mode
4tcy
tWT
Test 0 Hold Time After Program Mode
4tcy
too
Test 0 to Data Out Delay
tww
RESET Pulse Width to Latch Address
4tcy
tr. tf
- tcv
-tRE
Mix.
Unit
60
ms
Telt Condition.
4tcy
Voo and PROG Rise and Fall Times
0.5
CPU Operation Cycle Time
5.0
RESET Setup Time Before EA 1,
4tcy
2.0
",s
",s
Note: If Test 0 is high too can be triggered by RESET I
DC SPECIFICATION FOR PROGRAMMING
TA = 25°C ± 5°C. Vee = 5V ± 5%, VDD = 25V ± 1V
Symbol
Parameter
Min.
Max.
Unit
24.0
26.0
V
Voo Voltage Low Level
4.75
5.25
V
VPH
PROG Program Voltage High Level
21.5
24.5
V
VPL
PROG Voltage Low Level
0.2
V
VEAH
EA Program or Verify Voltage High Level
21.5
24.5
V
8748
V EAH1
EA1 Verify Voltage High Level
11.4
12.6
V
8048
VOOH
Voo Program Voltage High Level
VOOL
VEAL
EA Voltage Low Level
5.25
V
100
Voo High Voltage Supply Current
30.0
mA
IPROG
PROG High Voltage Supply Current
16.0
mA
lEA
EA High Voltage Supply Current
1.0
mA
6-16
Test Conditions
b048/8035L/8748/8748-6/8748-8/803S/803S-8
WAVEFORMS FOR PROGRAMMING
COMBINATION PROGRAMIVERIFY MODE (EPROM'S ONLY)
23V
EA
5V
_----II
__
. - - - - - - - - - i - - - VERIFY
.I'"'.~---
PROGRAM - - - - -
,.----.......
TO
'AW +-----<+--f-'WA
DBa-DB,
J--
---<
DATA TO BE
PROGRAMMED VAllO
NEXT ADDR
VALID
x==
NEXT
ADDRESS
LAST
ADDRESS
~::
_______________________
'~~-mt_~W_T
+23
PROG +5 _ _ _ _ _ _ _
+0
==rr--TI
0W
_
_
_
_
_
'wo
,._ _ _ _ __
___
J
- - -,'-------
VERIFY MODE (ROM/EPROM)
TO,mrr
DBa-DB,
P,,-P,
\I.._______--J/
==>-__
\_--~/
ADDRESS
\'-----
NEXT
ADDRESS
10-71 VALID
XI.._____
--'X. .______
A_D_DR_E_S_S_IB_-9_I_V_A_L_'D_ _ _ _
N_EX_T_A_D_D_R_E_SS_V_A_L_'D
_ _ _ _ _ _ __
NOTES:
1, PROG MUST FLOAT IF EA IS LOW (i.e., ,,23V), OR IF TO = 5V FOR THE 8748, FOR THE
8048 PROG MUST ALWAYS FLOAT,
2. Xl AND X2 DRIVEN BY 3 MHz CLOCK WILL GIVE 5",ec 'CY, THIS IS ACCEPTABLE FOR
·8 PARTS AS WELL AS STANDARD PARTS,
The 8748 EPROM can be programmed by either of two
Intel products:
1, PROMPT-48 Microcomputer Design Aid, or
2. Universal PROM Programmer (UPP series) peripheral
of the Intellec$ Development System with a UPP·848
Personal ity Card.
Note: See the ROM/PROM section for 8048 ROM ordering procedures.
To minimize turnaround time on the first 25 pieces 8648 may be
specified on the ROM order.
6-17
AFN-013S4A-09
108048/8748/8035 L
INDUSTRIAL TEMPERATURE RANGE
SINGLE COMPONENT 8·BIT MICROCOMPUTER
•
•
•
•
•
8048 Mask Programmable ROM
8648 One·Time Factory Programmable EPROM
8748 User Programmable/Erasable EPROM
8035/8035L External ROM or EPROM
- 40°C to + 85°C Operation
• 8·Bit CPU, ROM, RAM, 1/0 in Single
Package
• Interchangeable ROM and EPROM
Versions
• 1K x 8 ROMIEPROM
64 x 8 RAM
271/0 LINES
• Single 5V Supply
• 2.5 fJsec and 5.0 fJsec Cycle Versions:
All instructions 1 or 2 Cycles
• Interval TimerlEvent Counter
• Easily Expandable Memory and 1/0
• Compatible with 808018085 Series
Peripherals
• Over 90 Instructions: 70% Single Byte
• Single Level Interrupt
The Intel® 8048/8648/8748/8035 is a totally self·sufficient 8·bit parallel computer fabricated on a single silicon chip
using Intel's N·channel silicon gate MOS process.
The 8048 contains a 1K x 8 program memory, a 64 x 8 RAM data memory, 271/0 lines, and an 8·bit timerlcounter in addi·
tion to on·board oscillator and clock circuits. For systems that require extra capability, the 8048 can be expanded
using standard memories and MCS·80™IMCS·85TM peripherals. The 8035 is the equivalent of an 8048 without program
memory. The 8035L has the RAM power·down mode of the 8048 while the 8035 does not. The 8648 is a one·time pro·
grammable (at the factory) 8748 which can be ordered as the first 25 pieces of a new 8048 ROM order. The substitution
of 8648's for 8048's allows for very fast turnaround for initial code verification and evaluation units.
To reduce development problems to a minimum and provide
ble versions of this single component microcomputer exist:
program memory for prototype and preproduction systems,
memory for low cost, high volume production, and the 8035
memories.
maximum flexibility, three interchangeable pin·compati·
the 8748 with user·programmable and erasable EPROM
the 8048 with factory·programmed mask ROM program
without program memory for use with external program
This microprocessor is designed to be an efficient controller as well as an arithmetic processor. The 8048 has exten·
sive bit handling capability as well as facilities for both binary and BCD arithmetic. Efficient use of program memory
results from an instruction set consisting mostly of single byte instructions and no instructions over 2 bytes in length.
PIN CONFIGURATION
LOGIC SYMBOL
BLOCK DIAGRAM
8048
PlO
ADDRESS
LATCH
ENABLE
PORT
EXPANDER
STROBE
INTEL CORPORATION ASSUMES NO RESPONSIBILITY FOR THE USE OF ANY CIRCUITRY OTHER THAN CIRCUITRY EMBODIED IN AN INTEL PROOUCT. NO OTHER CIRCUIT PATENT LlCENS(S ARE IMPlU
© INTEL CORPORATION. 1979
6-18
AFN-OOBBOA-01
108048/8748/8035L
PIN DESCRIPTION
Designation
Pin #
Function
Designation
VSS
20
Circuit GND potential
RD
Voo
26
Programming power supply; +25V
during program, +5V during oper·
ation for both ROM and PROM.
low power standby pin in 8048
and 8035l.
Vee
40
Main power supply; +5V during
operation and programming.
PROG
25
Program pulse (+23V) input pin
during 8748 programming.
DBo-DB7
BUS
8
Function
Output strobe activated during a
BUS read. Can be used to enable
data onto the bus from an external
device.
Used as a read strobe to external
data memory. (Active low)
Output strobe for 8243 I/O
expander.
P10·P17
Port 1
P20-P27
Port 2
Pin #
RESET
4
Input which is used to initialize the
processor. Also used during PROM
programming verification, and
power down. (Active low)
(Non TTL VIH )
WR
10
27·34
8-bit quasi-bidirectional port.
Output strobe during a bus write.
(Active low)
21-24
35-38
8-bit quasi-bidirectional port.
Used as write ·strobe to external
data memory.
12-19
P20-P23 contain the four high
order program counter bits during
an external program memory fetch
and serve as a 4-bit I/O expander
bus for 8243.
ALE
Address latch enable. This signal
occurs once during each cycle and
is useful as a clock output.
The negative edge of ALE strobes
address into external data and program memory.
True bidirectional port which can
be written or read synchronously
using the RD, WR strobes. The
port can also be statically latched.
Contains the 8 low order program
counter bits during an external
program memory fetch, and receives
the addressed instruction under the
control of P5EN. Also contains the
address and data during an external
RAM data store instruction, under
control of ALE, RD, and WR.
TO
11
Input pin testable using the conditional transfer instructions JTO
and JNTO. TO can be designated as
a clock output using ENTO ClK
instruction. TO is also used during
programming.
T1
39
Input pin testable using the JT1,
and JNT1 instructions. Can be designated the timer/counter input using
the STRT CNT instruction.
INT
6
Interrupt input. Initiates an interrupt if interrupt is enabled. Interrupt is disabled after a reset. Also
testable with conditional jump
instruction. (Active low)
6-19
PSEN
9
Program store enable. This output
occurs only during a fetch to external program memory. (Active low)
55
5
Single step input can be used in conjunction with ALE to "single step"
the processor through each instruction. (Active low)
EA
7
External access input which forces
all program memory fetches to reference external memory, Useful
for emulation and debug, and
essential for testing and program
verification. (Active high)
XTAL1
2
One side of crystal input for internal oscillator. Also input for external source. (Non TTL VIH)
XTAl2
3
Other side of crystal input.
108048/8748/8035 L
INSTRUCTION SET
Mnemonic
ADD A, R'
ADD A,@R
ADD A, #data
ADDCA, R
ADDCA,@R
ADDC A, TEST POINTS:::::~:~X\"_____
BUS
A.C. CHARACTERISTICS
T A = -40·Cto +85·C, Vcc=Voo= +5V ±10%, Vss=OV
Symbol
8048/8035L
Parameter
Min.
Max.
8748/8035
Min.
Unit
tLL
ALE Pulse Width
200
300
ns
tAL
Address Setup to ALE
120
120
ns
tLA
Address Hold from ALE
80
80
ns
tcc
Control Pulse Width (PSEN, RD, WR)
400
600
ns
tow
Data Setup Before WR
420
600
ns
two
Data Hold After WR
80
120
tCY
Cycle Time
2.5
15.0
4.17
tOR
Data Hold
0
200
0
t RO
PSEN, RD to Data In
tAW
Address Setup to WR
tAD
Address Setup to Data In
400
230
t AFC
Address Float to RD, PSEN
tCA
Control Pulse to ALE
Note 1: Control Outputs: CL: 80 pF
BUS Outputs:
CL: 150 pF
ns
C L =20 pF
15.0
fJs
(3.6 MHzXTAL8748/8035)
200
ns
600
ns
900
ns
ns
260
600
Conditions (Note 1)
Max.
-40
- 60
ns
10
10
ns
for804818035L
4.17 ~ for 874818035
tCy:2.5~s
6-22
AFr>HlO860A·05
108048/8748/8035L
A.C. CHARACTERISTICS
TA= -40·Cto +85·C, Vcc=5V ±10%, Vss=OV
Symbol
Parameter
Min.
top
Port Control Setup Before Failing Edge of PROG
115
tpc
Port Control Hold After Failing Edge of PROG
65
tPA
PROG to Time P2 Input Must Be Valid
tpF
Input Data Hold Time
top
Output Data Setup Time
230
ns
tpo
Output Data Hold Time
25
ns
tpp
PROG Pulse Width
920
ns
tpL
Port 2 I/O Data Setup
300
ns
tLP
Port 2 I/O Data Hold
120
ns
0
Max.
Unit
Test Condilions
ns
ns
860
ns
160
ns
PORT 2 TIMING
ALE
EXPANDER
PORT
OUTPUT
PCH
EXPANDER
PORT
INPUT
PCH
PROG
6-23
AFN-00860A-tl8
108048/8748/8035L
CRYSTAL OSCILLATOR MODE
DRIVING FROM EXTERNAL SOURCE
+5V
,---r----'-1
XTALl
4701'1
1·6 mHz
0-15 pF
(INCLUDES XTAL
SOCKET, STRAy)
}>--+----"-t XTALl
+5V
'-----t------"l3 XTAL2
4701'1
I-=-
15-25 pF
(INCLUDES SOCKET,
STRAY)
L-_--+-_-"-j XT AL2
CRYSTAL SERIES RESISTANCE SHOULD BE <751'1 AT 6 MHz; <180Q AT 3.8 MHz.
BOTH Xl AND X2 SHOULD BE DRIVEN.
RESISTORS TO Vee ARE NEEDED TO ENSURE V,H 3.BV IF TTL CIRCUITRY IS
USED. THE MINIMUM HIGH AND THE MINIMUM LOW TIMES ARE 45%.
=
LC OSCILLATOR MODE
-"45 flH
120 J.lH
~
20 pF
20 pF
NOMINALf
5.2 MHz
3.2 MHz
...--..--"'1XTALl
'----+--"'1XTAL2
C,=C+3Cpp
2
Cpp::::: 5-10 pF PIN·TO·PIN
CAPACITANCE
EACH C SHOULD BE APPROXIMATELY 20 pF,lNCLUDING STRAY CAPACITANCE.
WARNING:
PROGRAMMING, VERIFYING, AND
ERASING THE 8748 EPROM
An attempt to program a mis-socketed 8748 will result in
severe damage to the part. An indication of a properly
socketed part is the appearance of the ALE clock output. The lack of this clock may be used to disable the
programmer.
Programming Verification
The ProgramlVerify Sequence is:
1. Voo=5V, clock applied or internal oscillator operating, RESET=OV, TEST 0=5V, EA=5V, BUS and
PROG floating:
In brief, the programming process consists of: activating the program mode, applying an address, latching the
address, applying data, and applying a programming
pulse. Each word is programmed completely before
moving on to the next and is followed by a verification
step. The following is a list of the pins used for programming and a description of their functions:
2. Insert 8748 in programming socket.
3. TEST 0 = OV (select program mode).
4. EA = 23V (activate program mode).
5. Address applied to BUS and P20-1.
6. RESET = 5V (latch address).
Pin
Function
XTAL1
Clock Input (1 to 6 MHz)
RESET
Initialization and Address Latching
TEST 0
Selection of Program or Verify Mode
EA
Activation of ProgramlVerify Modes
BUS
Address and Data Input
Data Output during Verify
P20-1
Address Input
Voo
PROG
Programming Power Supply
7. Data applied to BUS.
8. Voo = 25V (programming power).
9. PROG = OV followed by one 50 ms pulse to 23 V.
10. Voo=5V.
11. TEST 0 = 5V (verify mode).
12. Read and verify data on BUS.
13. TEST 0 = OV.
14. RESET = OV and repeat from step 5.
15. Programmer should be at conditions of step 1 when
8748 is removed from socket.
Program Pulse Input
6-24
AFN-008eOA-Q7
ID8048/8748/8035L
AC TIMING SPECIFICATION FOR PROGRAMMING
TA
=25°C ± 5°C, Vee =5V ± 5%, Vee =25V ± 1V
Sy,mbol
tAW
Paramet.r
Address Setup Time to
Min.
m!'I'1
tWA
Address Hold Time After RESETt
4tcy
tow
pata In Setup Time to PROG'
4tcy
Data In Hold Time After PROG L
4tcy
two
t pH
tvoow
tVOOH
tpw
. AmT Hold Time to Verify
4tcy
Voo
VooHold Time After PROGl
4tcy
Unit
60
ms
T..t Condition.
0
Program Pulse Width
50
tr,w
Test 0 Setup Time for Program Mode
4tcy
tWT
Test 0 Hold Time After Program Mode
4tcy
too
Test 0 to Data Out Delay
. tww
Max.
4tcy
4tcy
~ Pulse Width to Latch Address
4tcy
t" tf
tCY
Vooand PROG Rise and Fall Times
0.5
CPU Operation Cycle Time
5.0
tRE
RE§ET'Setup Time Before EA 1
2.0
,us
JAS
4tcy
Note: "Test 0 is high too can be triggered by RESET'
DC SPECIFICATION FOR PROGRAMMING
TA = 25°C ± 5°C, Vee = 5V ± 5%, Vee = 25V ± 1V
Symbol
Parameter
Min.
Max.
Unit
V
V
Voo'!
VOOL
VooProgram Voltage High Level
24.0
26.0
Voo Voltage Low Level
4.75
5.25
21.5
24.5
V
0.2
V
T••t Condition.
VPH
PROG Program Voltage High Level
VPL
PROG Voltage Low Level
VEAH
EA Program or Verify Voltage High Level
21.5
24.5
V
8746
VEAH1
EA1 Verify Voltage High Level
11.4
12.6
V
8046
VEAL
EA Voltage Low Level
5.25
V
100
VooHlgh Voltage Supply Current
30.0
mA
I PROG
PROG High Voltage Supply Current
16.0
mA
lEA
EA High Voltage Supply Current
1.0
mA
6-25
AFN-00880A-08
108048/8748/8035L
WAVEFORMS FOR PROGRAMMING
COMBINATION PROGRAMIVERIFY MODE (EPROM'S ONLY)
23V
EA
5V
_--J/
1 - - - - - - - - - - PROGRAM - - - - - - - - - - t - - - VERIFY--'~I.'---- PROGRAM - - - - -
,.----'"'""
TO
DBo- DB7
==>---
DATA TO BE
PROGRAMMED VAL 10
_ _ - { N. EXT ADDR
VALID
L
NEXT
ADDRESS
LAST
ADDRESS
voo+:
~-::-T----------------------------------------------
t.T
... I - - U :
+23-----------PROG +5 _______ _ _ _ _ _ _ _ _
+0
,.-___________
___
_
_ _ , ' -_______________
. . f _
VERIFY MODE (ROM/EPROM)
TO,RESET
DBo-DB7
1
\ \ , .________________1
\\.--__--JI
J-__________
__'~\,.
\\.----
- - -<\,.____A_~_~_~E_TS_S __'X\,._~_~_~_TV_~_~T_I~..J)_
__
__________
A_DD_R_E_S_S_(8_-9_I_V_A_LI_D________
__I~\,.
-
-
-- -
-
-
-
____________
NE_X_T_A_D_D_R_E_SS_V_A_L_ID
_______________
NOTES:
1. PROG MUST FLOAT IF EA IS LOW (Le., *23VI, OR IF TO = 5V FOR THE 8748. FOR THE
8048 PROG MUST ALWAYS FLOAT.
2. X1 AND X2 DRIVEN BY 3 MHz CLOCK Will GIVE
5~sec
tCY. THIS IS ACCEPTABLE FOR
·8 PARTS AS WELL AS STANDARD PARTS.
The 8748 EPROM can be programmed by either of two
Intel products:
1. PROMPT -48 Microcomputer Design Aid. or
2. Universal PROM Programmer (UPP series) peripheral
of the Intellec® Development System with a UPP·848
Personality Card.
Note: See the ROM/PROM section for 8048 ROM ordering procedures.
To minimize turnaround time on the first 25 pieces 8648 may be
specified on the ROM order.
6-26
AFN-00880A-09
inter
M8048/M8748/M8035L
SINGLE COMPONENT &81T MICROCOMPUTER
* 8048 Mask Programmable ROM
* 8748 User Programmable/Erasable EPROM
* 8035L Requires External ROM or EPROM
• ·55°C to + 125°C 6 MHz Operation
(M80481M8035L)
• Over 90 Instructions: 70% Single Byte
• 1K x 8 ROMIEPROM
64 x 8 RAM
27110 Lines
• ·55°C to + 100°C 3.6 MHz Operation
(M8748)
• 8-Bit CPU, ROM, RAM, 1/0 in
Single Package
• Interval TimerlEvent Counter
• Interchangeable ROM and EPROM
Versions
• Easily Expandable Memory and 1/0
• Single 5V Supply
• Compatible with 808018085 Series
Peripherals
• 2.5 IJsec and 5.0 IJsec Cycle Versions
All Instructions 1 or 2 Cycles.
• Single Level Interrupt
The Intel M80481M8748JM8035L are totally self-sufficient 8-bit parallel computers fabricated on single silicon chips using
Intel's N-Channel silicon gate MOS process_
The M8048 contains an 8-bit CPU, a 1K x 8 program memory, a 64 x 8 RAM data memory, 27 1/0 lines, and an 8-bit timerl
counter in addition to on-board oscillator and clock clrcuits_ F.ro systems that require extra capability, the M8048 can be
expanded using standard memories and MCS-80™IMCS-85TM peripherals_ The M8035L is the equivalent of an M8048
without program memory, and has the RAM power. down mode of the M8048_ To reduce development problems to a minImum and provide maximum flexibility, three Interchangeable pin-compatible' versions of this single component microcomputer exist: the M8748 with user-programmable and erasable EPROM program memory for prototype and preproduction systems, the M8048 with factory-programmed mask ROM program memory for low cost, high volume production,
and the M8035L without program memory for use with external program memories_
This microprocessor is designed to be an efficient controller as well as an arithmetic processor. The M8048 has extensive
bit handling capability as well as facilities for both binary and BCD arithmetic. Efficient use of program memory results
from an instruction set consisting mostly of single byte instructions and no Instructions over 2 bytes in length.
'Vee is used to program the M8748 and used for low power standby on the M8048I8035L.
PIN CONFIGURATION
BLOCK DIAGRAM
LOGIC SYMBOL
PORT
"
PORT
"
M8048
INTEl CORPORATION ASSUMES NO RESPONSIBILITY FOR THE USE OF ANY CIRCUITRY OTHER THAN CIRCUITRY EMBOmED IN AN INTEl PRODUCT. NO OTHER CIRCUIT PATENT LICENSES ARE IMPLIED.
©INTEL CORP.. 1980
6-27
AFN-G0780A-ol
M80481 M87481 M8035L
LCOSCILLATOR MODE
CRYSTAL OSCILLATOR MODE
Cl
1-_~_ _ _""'___2'-i XTAL 1
~ ,,::~: =
-=I
+-__...;31
<
.£.
20 pF
20 pF
~
5.2 MHz
3.2 MHz
, - - - r - - - j XTAU
c'=
C + 3Cpp
2
1-_---'1_ _ _
C3
Cl ; SpF ± 12pF + STRAY
C2 ; CRYSTAL + STRAY
C3 = 20pF ± 1pF + STRAY
..h.
45 "H
120 "H
XTAL2
'----4-_--j XTAL2
<
SpF
8pF
SpF
Cpp ::::: 5 - 10 pF PIN·TO·PIN
CAPAC IT ANCE
<
CRYSTAL SERIES RESISTANCE SHOULD BE LESS THAN 1SQ
THAN 180Q AT 3.8MHz.
AT 8MHz; LESS
EACH C SHOULD BE APPROXIMATEl Y 20 pF, INCLUDING STRAY CAPACITANCE.
DRIVING FROM EXTERNAL SOURCE
+ SV
470Q
»---+-----'-1 XTAL1
+ SV
470Q
'---~--'-i XTAL2
FOR XTAL 1 AND XTAL 2 DEFINE "HIGH" AS VOLTAGES ABOVE 1.8V AND "LOW"
AS VOLTAGES BELOW 1.6V. THE DUTY CYCLE REQUIREMENTS FOR EXTERNALLY
DRIVING XTAL 1 AND XTAL 2 USING THE CIRCUIT SHOWN ABOVE ARE AS
FOLLOWS:
FOR THE 8048. XTAL 1 MUST BE HIGH 35-6S% OF THE PERIOD AND XTAL 2 MUST
PROGRAMMING, VERIFYING, AND
ERASING THE 8748 EPROM
Programming Verification
In brief, the programming process consists of: activating
the program mode, applying an address, latching the
address, applying data, and appiying a programming pulse.
Each word is programmed completely before moving on to
the next and is followed by a verification step. The following is a list of the pins used for programming and a description of their functions:
Pin
XTALl
Reset
Test 0
EA
BUS
BE HIGH 3S-65% OF THE PERIOD.
FOR THE 8748. XTAL MUST BE HIGH 45·50% OF THE PERIOD AND XTAL 2 MUST
BE HIGH SO·SS% OF THE PERIOD.
RISE AND FALL TIMES MUST NOT EXCEED 20 ns.
WARNING:
An attempt to program a missocketed 8748 will reSUlt in severe
damage to the part. An indication of a properly socketed part is the
appearance of the ALE clock output. The lack of this clock may
be used to disable the prQgrammer.
The ProgramNerify sequence is:
Function
Clock Input (1 to 6MHz)
Initialization and Address Latching
Selection of Program or Verify Mode
Activation of ProgramNerify Modes
1.
~ 5v, Clock applied or internal oscillator operating,
RESET = OIl, TEST 0 = 5v, EA = 5v, 8US and PROG
floating.
2.
Insert 8748 in programming socket
3.
TEST 0
4.
EA = 23V (activate program mode)
5.
Address applied to BUS and P2()'1
6.
RESET = 5v (latch address)
= Ov (select program
mode)
7.
Oata appl ied to BUS
8.
VOO= 25v (programming power)
9.
PROG = 011 followed by one SOms pulse to 23V
10.
VOO = 5v
11.
TEST 0 = 5v (verify mode)
P20-1
Address and Data Input
Data Output During Verify
Address. Input
Voo
Programming Power Supply
14.
RESET = 011 and repeat from step 5
Program Pulse Input
15.
Programmer should be at conditions of step 1 when 8748
is removed from socket.
PROG
6-28
12.
Read and verify data on BUS
13.
TEST 0= 011
AFN-D076OAo02
M8048/M87481 M8035L
AC TIMING SPECIFICATION FOR PROGRAMMING
TA = 25°C ± 5°C, Vee = 5V ± 5%, Voo = 25V ± 1V
Min.
Parameter
Symbol
tAW
Address Setup Time to RESET ,
41CY
tWA
Address Hold Time After RESET'
41cy
tow
Data in Setup Time to PROG ,
41cy
Iwo
Dala in Hold Time After PROG
IPH
RESET Hold Time to Verify
tvoow
Voo
tVOOH
Voo Hold Time After PROG
Ipw
Program Pulse Width
trw
Test 0 Setup Time for Program Mode
4tcy
twr
Test 0 Hold Time After Program Mode
4tcy
too
Test 0 to Data Out Delay
tww
RESET Pulse Width to Latch Address
4tcy
Ir. It
Voo and PROG Rise and Fall Times
0.5
tCY
CPU Operation Cycle Time
5.0
tRE
Nole:
Ma••
Unit
SO
mS
Test Conditions
41cy
j
4tcy
4tcy
0
j
50
4tcy
t.
If Test 0 is high too can be triggered by RESEi' t.
RESET Setup TIme Before EA
2.0
liS
liS
4tcy
DC SPECIFICATION FOR PROGRAMMING
TA = 2SOC ± SoC, Vee = SV ± 5%, Voo = 2SV ± 1V
Symbol
Min.
Max.
Unit
24.0
2S.0
V
Voo Voltage Low Level
4.75
5.25
V
VPH
PROG Program Voltage High Level
21.5
24.5
V
VPL
PROG Voltage Low Level
VEAH
EA Program or Verify Voltage High Level
V EAH1
EA1 Verify Voltage High Level
Parameler
VOOH
Voo Program Voltage High Level
VOOL
0.2
V
21.5
24.5
V
8748
11.4
12.6
V
8048
V
VEAL
EA Voltage Low Level
5.25
100
Voo High Voltage Supply Current
30.0
mA
IPROG
PROG High Voltage Supply Current
16.0
mA
lEA
EA High Voltage Supply Current
1.0
mA
6-29
Test Conditions
AFN-Q0780A-(l3
M8048/M8748/M8035L
WAVEFORMS FOR PROGRAMMING
COMBINATION PROGRAMNERIFY MODE (EPROM'S ONLY)
EA
23'
/
5' _____.1
1 + - - - - - - - - - PROGRAM - - - - - - - - - - t - - - VERIFV---I.I~'---- PROGRAM - - - - tTw_
,.------,.
TO
tww-
DBo-DB,
J--
---<
DATA TO BE
PROGRAMMED VALID
NEXT ADDR
. VALID
LAST
ADDRESS
Voo
C
NEXT
ADDRESS
J-TI~·~n.-':w-.'----------------------
+:
+23----------~
+5------------
PROG +0
___
J ~----------'"'\....________
VERIFY MODE (ROM/EPROM)
TO. RESET
DBO-OS7
\
..J/
....._ _ _ _ _ _ _
=>---
\'--__-.J/
\'"----
---<. .__A_~_~_~_:S_S X. ._~_~_;_TV_~_~_i~...J>-
ADDRESS
10-71 VALID
__
-
-
-
-
-
-
-
_ _ _ _ _...J)<:..._ _ _ _ _
A_DD_R_E_S_S_18_-9_'_V_A_L_'D_ _ _ _ _)<:
..._ _ _ _ _ _
N_EX_T_A_D_D_R_E_SS_V_A_L_'_D_ _ _ _ _ _ _ __
NOTES:
1. PROG MUST FLOAT IF EA IS LOW (;.e" *l3V!, OR IF TO = 5V FOR THE 8748. FOR THE
8048 PROG MUST ALWAVS FLOAT.
2. X, AND X2 DRIVEN BV 3 MHz CLOCK WILL GIVE 5"sec Icv. THIS IS ACCEPTABLE FOR ALL PARTS.
The 8748 EPROM can be programmed by either of two
Intel products:
1. PROMPT -48 Microcomputer Design Aid, or
2. Universal PROM Programmer (UPP Series)
peripheral of the Intellec® Development System with a
UPP-848 Personality Card.
6-30
AFN-Q0780A-04
M8048/M8748/M8035L
INSTRUCTION SET
Mnemonic
~
::J
E
::J
~
ADD A, R
ADD A,@R
ADD A, #data
ADDC A, R
ADDC A,@R
ADDC A, #data
ANL A, R
ANLA,@R
ANL A, #data
ORL A, R
ORL A, @R
ORL A, 'data
XRL A, R
XRL A, @R
XRL A, #data
INC A
DECA
CLR A
CPL A
DAA
SWAP A
RL A
RLC A
RR A
RRC A
.,%
0
::J
".5
i'.."
"ce!
CD
JMPP@A
DJNZ R, addr
JC addr
JNC addr
JZ addr
JNZ addr
JTO addr
JNTO addr
JT1 addr
JNT1 addr
JFO addr
JF1 addr
JTF addr
JNI addr
JBb addr
:;
e
'"
Add immediate to A
Add register with carry
::J
TEST POINTS
<
2.0
0.8
0.45
x=
A.C. CHARACTERISTICS
TA = -55·C to (100·C M8748/125·C M8048/M8035L), Vcc = Voo = +5V ± 10%, Vss =OV
Symbol
Parameter
M8048
M8035L
Min. Max.
Min. Max.
M8748
Unit
Conditions (Note 1)
ns
tLL
ALE Pulse Width
200
300
tAL
Address Setup to ALE
120
120
ns
80
80
ns
tLA
Address Hold from ALE
tcc
Control Pulse Width (PSEN, RD, WR)
400
600
ns
tow
Data Setup before WR
420
600
ns
two
Data Hold After WR
80
120
ns
CL
tCY
Cycle Time
4.17 15.0
!lS
(3.6 MHz
XTAL 8748)
tOR
Data Hold
tRo
PSEN, RD to Data In
tAW
Address Setup to WR
tAD
Address Setup to Data In
tAFC
Address Float to RD, PSEN
tCA
Control Pulse to ALE
Note 1: Control outputs: CL = 80 pF
BUS Outputs:
CL = 150 pF
2.5
15.0
0
200
0 200
400
600
230
ns
ns
ns
260
900
600
= 20pF
ns
-40
-60
ns
10
10
ns
tCY = 2.5J.(5 for 8048/8035 L
4.17115 for 8748
6-34
AFN-00780A-08
M80481 M8748/M8035L
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias
8748.......... ................... -SsoC to +100°C
8048/803SL ...................... -SsoC to +12SoC
Storage Temperature .............. -6SoC to +12SoC
Voltage On Any Pin With Respect
to Ground ............................. -O.S to +7V
Power Dissipation ........................
1.S Watt
'COMMENT:
Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device, This is a stress fating
only and functional operation of the device at these or jiny other
conditions above those indicated in the operational sections of this
specification is not implied.
D.C.AN D OPERATI NG CHARACTERISTICS
TA = -55·C to (100·C MB74B/125·C MB04B/MB035L), Vee = VDD = +5V ± 10%, Vss =OV
Limits
Parameter
Symbol
Min.
Typ.
Unit
Test Conditions
Max.
V 1L
Input Low Voltage
(All Except RESET, X1, X2)
-.5
.7
V
V1L1
Input Low Voltage
(RESET, X1, X2)
-.5
.S
V
V 1H
Input High Voltage
(All Except XTAL 1, XTAL 2, RESET)
2.3
Vee
V
V1H1
Input High Voltage (RESET, X1, X2)
3.B
Vee
V
VOL
Output Low Voltage
(BUS, RD, WR, PSEN, ALE)
.45
V
IOL = 1.2mA
VOLI
Output Low Voltage
(All Other Outputs)
.45
V
iOL = O.BmA
VOH
Output High Voltage (BUS)
2.4
V
IOH= - 24OI'A
VOH1
Output High Voltage
(RD, WR, PSEN, ALE)
2.4
V
IOH = -SOI'A
VOH2
Output High Voltage
(All Other Outputs)
2.4
V
IOH = -3OI'A
III
Input Leakage Current (T1, INT)
±10
i-
I ncrement data- memory
Decrement reg ister
Jump on Carry = 1
Jump on Carry = a
Jump on A Zero
Jump on A not Zero
Jump on TO = 1
Jump on TO = a
Jump on Tl = 1
Jump on T1 = a
Jump on FO = 1
Jump on Fl = 1
Jump on timer flag
Jump on INT = a
Jump on Accumulator Bit
CALL
~ RET
f
0
Increment registel'
Jump unconditional
Jump indirect
Mnemonic
c
Increment A
Decrement A
Clear A
Complement A
Decimal Adjust A
Swap nibbles of A
Rotate A left
Rotate A left through carry
Rotate A right
Rotate A right through carry
I nput port to A
Output A to port
And immediate to port
.
register to A
memory to A
immediate to A
A to register
A to data memory
immediate to register
immediate to data memory
~ata
2
1
1
2
2
2
2
2
Move PSW to A
Move A to PSW
Exchange A and register
Exchange A and data memory
Exchange nibble of A and register
Move external data memory to A
Move A to external data memory
Move to A from current page
Move to A from Page 3
MOVA, T
MOVT, A
STRTT
STRT CNT
STOP TCNT
EN TCNTI
DIS TCNTI
Read Timer/Counter
Load Timer/Counter
Start Timer
EN I
DISI
SEL RBO
SEL RB1
SEL MBa
SEL MB1
ENTO ClK
Enable external interrupt
Disable external interrupt
Select register bank a
Select register bank 1
Select memory ba n k a
NOP
No Operatior.
2
2
2
2
Start Counter
Stop Timer/Counter
Enable Timer/Counter Interrupt
Disable Timer/Counter Interrupt
Select memory bank 1
Enable Clock output on TO
Mnemonics copyright Intel Corporation 1976, 1977, 1978
6·38
AFN·00191A·03
8049/8039
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device.
This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
Exposure to absolute
specification Is not implied.
maximum rating conditions for extended periods may
affect device reliability.
ABSOLUTE MAXIMUM RATINGS·
AmbientTemperatureUnderBias ........ 0°Cto70°C
Storage Temperature ............... -65° C to +150° C
Voltage on Any Pin With
Respectto Ground ...................... -0.5V to +7V
Power Dissipation .......................... 1.5 Watt
D.C. AND OPERATING CHARACTERISTICS
TA = o°c to 70"C, Vee = Voo = +5V ±10%, Vss = ov
Limits
Symbol
Parameter
Typ.
Min.
Max.
Unit
-0.5
0.8
V
Test Conditions
Vil
Input Low Voltage
VIH
Input High Voltage
(All Except XTAL1, XTAL2, RESET)
2.0
Vee
V
VIH1
Input High Voltage (RESET, Xl, X2)
3.8
Vee
V
VOL
Output Low Vo Itage
(BUS, RD, WR, PSEN, ALE)
0.45
V
IOl = 2.0mA
VOLl
Output Low Voltage
(All Other Outputs Except PROG)
0.45
V
IOl = 1.6mA
VO L2
Output low Voltage (PROG)
0.45
V
IOl = 1.0mA
VOH
Output High Voltage
(BUS, RD, WR, PSEN, ALE)
2.4
V
IOH = -100/.LA
VOH1
Output High Voltage
(All Other Outputs)
2.4
V
IOH = -50/.LA
IlL
In put Lea kage Current
(Tl, INT)
IOl
Output Leakage Current (Bus, TO)
(High Impedance State)
100
Power Down Supply Current
±10
loo+lee Tota I Su pply Current
A.C. CHARACTERISTICS
Symbol
/.LA
±10
/.LA
Vss + 0.45';; VIN .;; Ve e
25
50
mA
TA = 25°C
100
170
mA
TA = 25°C
TA = o°c to 70°C, Vee = Voo = +5V ±10%, Vss = ov
Max.
Unit
Conditions (Note 2)
Parameter
Min.
ALE Pulse Width
200
tAL
Address Setup to ALE
120
ns
tLA
Address Hold from ALE
80
ns
tcc
Control Pulse Width (PSEN, RD, WR)
400
ns
420
ns
ns
C L =20pF
llMHz XTAL
tll
VSS';;VIN';;Vee
ns
tow
Data Set·Up Before WR
two
Data Hold After WR
80
tey
Cycle Time
2.5
15.0
I's
tOR
Data Hold
0
200
ns
t RO
PSEN, RD to Data In
400
ns
tAW
Address Setup to WR
tAO
Address Setup to Data In
tAFC
Address Float to RD, PSEN
2~0
ns
600
-40
ns
ns
Noles: 1. 8039·6 specifications are also valid for 8049/8039 operating at 6MHz.
2. Control Outputs: C L = 80pF
BUS Outputs:
C L = 150pF
6-39
AFN-00191A-04
.8049/8039
WAVEFORMS
INSTRUCTION FETCH FROM EXTERNAL PROGRAM MEMORY
-tcv-----·I
11---~-tLL----1
ALE
------..1:.--1----'L
JI
L - -_ _
-
tAFCI---Icc----1
----------~-+~
.~------------
BUS
INSTRUCTION
READ FROM EXTERNAL DATA MEMORY
ALE
J
L
RD
BUS
WRITE TO EXTERNAL DATA MEMORY
ALE
J
L
BUS
FLOATING
6-40
AFN-00191A-05
NEW HIGH PERFORMANCE
18049/8039
SINGLE COMPONENT 8·BIT MICROCOMPUTER
*8049 Mask Programmable ROM
*8039 External ROM or EPROM
*6 MHz Operation
• 8·BIt CPU, ROM, RAM, 110 In
Single Package
• Single 5V::t 10% Supply
• 2.5 ILsec Cycle; All Instructions
1 or 2 Cycles
• Over 90 Instructions: 70% Single Byte
• Pin Compatible with 804818748
• 2K)( 8 ROM
128)( 8 RAM
27110 LInes
•
•
•
•
Interval Timer/Event Counter
Easily Expandable Memory and I/O
Compatible with MCS Memory and I/O
Single Level Interrupt
The Intel@> 18049/8039 is totally self-sufficient 8-bit parallel computer fabricated on a single silicon chip using Intel's
N-channel silicon gate MOS process.
The 8049 contains a 2K x 8 program memory, a 128 x 8 RAM data memory, 27 110 lines, and an 8-blt timer/counter In
addition to on-board oscillator and clock circuits. For systems that require extra capability, the 8049 can be expanded
using standard memories and MeS-80 TM/MeS-85™peripherals. The 8039 is the equivalent of an 8049 without program
memory.
To reduce development problems to a minimum and provide maximum flexibility, two Interchangeable pin-compatible
versions of this single component microcomputer exist: the 8049 with factory-programmed mask ROM program
memory for low-cost high volume production, and the 8039 without program memory for use with external program
.
memories In prototype and preproduction systems.
This microprocessor is designed to be an efficient controller as well as an arithmetic processor. The 8049 has extensive bit handling capability as well as facilities for both binary and BeD arithmetic. Efficient use of program memory
results from an instruction set consisting mostly of single byte instructions and no instructions over two bytes in
length.
PIN CONFIGURATION
LOGIC SYMBOL
BLOCK DIAGRAM
18039
18049
INTeL CORPORATION ASSUMES NO RESPONSIBILITY FOR THE USE OF ANY CIRCUITRY OTHER THAN CIRCUITRY EMBODIED IN AN INTeL PRODUCT. NO OTHER CIRCUIT PATENT LICENSES ARE IMPLIED.
olNTEL CORPORATION, 1979
AFN-00737-01
6-41
inter
18049/8039
PIN DESCRIPTION
Designation
Pin #
Function
Designation
Vss
20
Circuit GND pOtential
RD
Vee
26
+5V during operation. low power
standby pin.
Vee
40
Main power supply; +5V during
operation.
MaG
25
Output strobe for 8243 1/0
expander.
P1Q.P17
Port 1
P2O-P27
Port 2
00-07
BUS
27·34
B-bit quasi-bidirectional port.
21-24
35-38
B-bit quasi-bidirectional port_
12-19
Tl
P20-P23 contain the four high
order program counter bits during
an external program memory fetch
and serve as a 4-bit 1/0 expander
bus for 8243
iNr
6
Function
Output strobe activated during a
BUS read. Can be used to enable
data onto the BUS from an external
device.
RESET
4
Input which is used to initialize the
processor. Also used during verification, and power down. (Active
low) (Non TTL VIH)
WR
10
Output strobe during a B US write.
(Active low)
Used as write strobe to External
Data Memory.
ALE
11
True bidirectional port which can
be written or read synchronously
using the RD, WR strobes. The
port can also be statically latched.
Input pin testable using the conditional transfer instructions JTO
and JNTO. TO can be designated as
a clock output using ENTO ClK
instruction.
39
8
Used as a Read Strobe to External
Data Memory. (Active low)
Contains the 8 low order program
counter bits during an external
program memory fetch, and receives
the addressed instruction under the
controlof PSEN. Also contains the
address and data during an external
RAM data store instruction, under
control of ALE, RD, and WR.
TO
Pin #
Input pin testable using the JT1,
and JNT1 instructions. Can be designated the timer lcounter input using
the STRT CNT instruction.
Interrupt input. Initiates an interrupt if interrupt is enabled. Interrupt is disabled after a reset. Also
testable with conditional jump
instruction. (Active low)
6-42
Address latch Enable. This signal
occurs once dur ing each cycle and
is useful as a clock output.
The negative edge of ALE strobes
address into external data and program memory.
PSEN
9
Program Store Enable. This output
occurs only during a fetch to external program memory. (Active low)
SS
5
Single step input can be used in conjunction with ALE to "single step"
the processor through each instruction. (Active low)
EA
7
External Access input which forces
all program memory fetches to reference external memory. Useful
for emulation and debug, and
essential for testing and program
verification. (Active high)
XTAL1
2
One side of crystal input for internal oscillator. Also input for external source. (Not TTL Compatible)
XTAl2
3
Other side of crystal input.
AFN-00737-02
intJ
18049/8039
INSTRUCTION SET
Mne .... nic
ADDA.R
ADD A.@IR
ADD A. #data
ADDCA.R
ADDCA.@R
ADDC A, #data
ANL A, R
ANLA,@R
ANL A, #data
ORL A, R
~ ORLA,@R
ORL A, #data
E XRLA, R
XRLA,@R
C XRLA, #data
INCA
DEC A
CLR A
CPLA
DAA
SWAP A
RLA
RLCA
RRA
RRCA
."
ii
i;
!2
;
Q.
.5
INA,P
OUTLP,A
ANL P, #data
ORL P, #data
INSA, BUS
OUTL BUS, A
ANL BUS, #data
ORL BUS,#data
MOVDA, P
MOVDP,A
ANLD P,A
ORLD P, A
•
••r
~
.t:
.
u
til"
Dnc:rlption
Add register to A
Add data memory to A
Add immediate to A
Add register with carry
Add data memory with carry
Add immediate with carry
And register to A
And data memory to A
And immediate to A
Or register to A
Or data memory to A
Or immediate to A
Exclusive Or ragister to A
Exclusive or data memory to A
Exclusive or immediate to A
Increment A
Decrement A
Clear A
Complement A
Decimal Adjust A
Swap nibbles of A
Rotate A left
Rotate A left through carry
Rotate A right
Rotate A .right through carry
Bytes
I
I
2
And immediate to port
INCR
INC@R
DECR
Increment register
Increment data memory
Decrement reg ister
JMP addr
JMPP@A
DJNZ R, addr
JCaddr
JNC addr
J Z addr
JNZ addr
JTOaddr
JNTO addr
JTl addr
JNTI addr
JFOaddr
JFl addr
JTF addr
JNladdr
JBbaddr
Jump unconditional
Jump indirect
Decrement register and skip
Jump on Carry = I
Jump on Carry = 0
Jump on A Zero
Jump on A not Zero
Jump on TO = 1
Jump on TO= 0
Jump on T1 = 1
Jump on T1 = 0
Jump on FO= 1
Jump on Fl = 1
Jump on timer flag
Jump on INT = 0
Jump on Accumulator Bit
Mn..... nic
.~
CALL
!i RET
I
2
2
1
I
2
1
2
I
2
2
2
I
2
2
e RETR
i
III
j
II.
CLR C
CPL'C
CLR FO
CPL FO
CLR Fl
CPL FI
D-.iptlon
ByleS Cycle.
Jump to subroutine
Return
2
Return and restore status
2
Clear Carry
Complement Car'y
Clear Flag 0
Complement Flag 0
Clear Flag 1
Complement Flag I
MOVA,R
Move register to A
MOVA,@R
Move Jata memory to A
MOV A, #data Move immediate to A
MOVR,A
Move A to register
MOV@R,A
Move A to data memory
MOV R, #data Move immediate to register
MOV @R, #data Move immediate to data memory
~ Move A,PSW Move PSW to A
MOV PSW, A
Move A to PSW
';;
Exchange A a nd register
C XCH A, R
XCHA,@R
Exchange A and data memory
XCHD A,@R
Exchange nibble of A and register
MOVXA,@R
Move external data memory to A
MOVX@R,A Move A to external data memory
MOVPA,@A
Move to A from current page
MOVP3 A,@A Move to A from Page 3
!
I
2
1
1
2
I
2
2
1
2
2
.
Input port to A
Output A to port
Or immediate to port
Input BUS to A
Output A to BUS
And immediate to BUS
Or immediate to BUS
Input Expander port to A
Output A to Expander port
A nd A to Expander port
Or A to Expander port
Cycl.
2
2
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
MOVA, T
MOVT,A
STRTT
STRT CNT
STOP TCNT
.~ EN TCNTI
DIS TCNTI
...
Read Timer/Counter
Load Timer/Counter
Start Timer
Start Counter
Stop Timer/Counter
Enable Timer/Counter Interrupt
Disable Timer/Counter Interrupt
EN I
DISI
SEL RBO
SEL RBI
~ SEL MBO
SELMB1
ENTOCLK
Disable external interrupt
Select register bank 0
Select register bank I
Select memory ban k 0
Select memory bank I
Enable Clock output O~ iO
I
§"
•
~
2
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
NOP
1
1
2
2
2
2
,I
Enable external interrupt
No Operatior.
Mnemonics copyright Intel Corporation 1976, 1977, 1978
643
AFN-00737-03
18049/8039
AmbientTemperatureUnderBias ..... -40'C to +SS'C
Storage Temperature ............... -6S'C to +lS0'C
Voltage on Any Pin With
Respectto Ground ...................... -O.SV to +7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . .. 1.S Watt
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated iri th{} operational sections of this
specification is not implied. Exposure to absolute
maximum rating conGitions for extended periods may
affect device reliability.
D.C. AND OPERATING CHARACTERISTICS
TA = -40°C to +8SoC, Vee = voo = +5V ± 10%, Vss= OV
ABSOLUTE MAXIMUM RATINGS·
Limits
Symbol
Parameter
Min.
Vil
Input Low Voltage
VIH
Input High Voltage
(All Except XTALl, XTAL2,
VIH1
Input High Voltage (RESET, Xl, X2)
VOL
Typ.
-0.5
ffESEf)
Max.
Uhit
0.6
V
Test Conditions
2.2
Vee
V
3.S
Vee
V
Output Low Voltage
(BUS, RD, WR, PSEN, ALE)
0.45
V
IOl = 1.6 ma
VOl1
Output Low Voltage
(All Other Outputs Except PROG)
0.45
V
IOl = 1.2 ma
VOL2
Output Low Voltage (PROG)
0.45
V
IOl = 0.8 rna
VOH
Output High Voltage
(BUS, RD, WR, PSEN, ALE)
2.4
V
IOH = -80
j.la
VOH1
Output High Voltage
(All Other Outputs)
2.4
V
IOH = -30
j.la
III
Input Leakage Current
(n, INT)
±10
IOl
Output Leakage Current (Bus, TO)
(High Impedance State)
±10
J.l.A
Vss + 0.45";; VIN ";;Ve e
100
Power Down Supply Current
50
mA
TA = 25°C
170
mA
TA = 2SoC
loo+lee Total Supply Current
A.C. CHARACTERISTICS
Symbol
ILL
TA
= -40
0
C to +8S o C, Vee
J.l.A
VSS";;VIN";;Vee
= Voo = +SV ±10%, Vss = OV
Parameter
Min.
ALE Pulse Width
200
ns
120
ns
SO
ns
ns
Max.
Unit
Conditions (Note 2)
t~L
Address Setup to ALE
tLA
Address Hold from ALE
tee
Control Pulse Width (PSEN, RD, WR)
400
tow
Data Set·Up Before WR
420
ns
two
Data Hold After WR
80
ns
C L =20pF
tCY
Cycle Time
2.5
15.0
,..s
(6 MHz XTAL for
IDS049)
tOR
Data Hold
200
ns
tRO
PSEN, RD to Data In
400
ns
tAW
Address Setup to WR
tAD
Address Setup to Data In
tAFe
Address Float to RD, PSEN
0
2:)0
600
-40
Not••: 1. 8039·6 specifications are also valid for 8049/8039 operating at SMHz.
2. Control Outputs: CL = 80pF
6-44
BUS Outputs:
eL 150pF
=
ns
ns
ns
AFN~00737~04
18049/8039
WAVEFORMS
INSTRUCTION FETCH FROM EXTERNAL PROGRAM MEMORY
-I--'cv-------~!
1_-·
-t-ll___
ALE
JI
I.....-_ _ _
~Ir-------,L
- tAFCI---'cc---1
----------~-+--,
~------------
BUS
INSTRUCTION
READ FROM EXTERNAL DATA MEMORY
ALE
J
L
r--tCC---I
RD
------------~I
------------
~I
tAFC--1 I~OATING-I t=t
BUS
FLOATING
~
II.
l.tRO
OR
--F-LO-A-T-I-N-G---
-!
tAD~
WRITE TO EXTERNAL DATA MEMORY
ALE
J
L
BUS
FLOATING
6-45
AFN-00737-05
inter
18049/8039
A.C. CHARACTERISTICS
TA = -40 C to +85 C, Vee = Voo = +5V ±10%, Vss = OV
0
0
Symbol
tcp
tpc
tpA
top
tpo
tpF
tpp
tpL
tLp
Parameter
Port Control Siltup Before Failing
Edge of PROG
Port Control Hold After Failing Edge
of PROG
PROG to Time P2 Input Must Be Valid
Output Data Setup Time
Output Data Hold Time
Input Data Hold Time
PROG Pulse Width
Port 2 1/0 Data Setup
Port 2 1/0 Data Hold
Min.
Max.
115
Unit
ns
65
860
ns
ns
230
ns
25
160
ns
ns
0
920
300
120
Conditions (Note 2)
ns
ns
ns
WAVEFORMS
PORT 2 TIMING
ALEJ
EXPANDER
PORT
OUTPUT
~I
\
I
I
I
PCH
I
EXPANDER
PORT
fNIJUT
I
PCH
PROG
6-46
AFN-00737-06
18049/8039
CRYSTAL OSCILLATOR MODE
LC OSCILLATOR MODE
C1
~
~
2
I
__ J.
__
C2 _-,-_~
XTAL1
J:...
.£.
~
45 .. H
20 pF
5,2 MHz
120 ... H
20 pF
3.2 MHz
1·6MH,
I
~____~:______~______~
XTAL2
' -__-.+____..,,3 XT AL2
C3
C1
C2
C3
,.-.,.---''1 XT AL1
c:=:::J
= SpF ± 'hpF + STRAY < 5pF
= CRYSTAL + STRAY < 8pF
= 20pF ± 1pF + STRAY < 5pF
CRYSTAL SERIES RESISTANCE SHOULD BE LESS THAN 75\1
THAN 18011 AT 3.8MHz.
AT 8MHz; LESS
Cpp ::: 5 - 10 pF PIN·TO·PIN
CAPACITANCE
EACH C SHOULD BE APPROXIMATELY 20 pF, INCLUOING STRAY CAPACITANCE
DRIVING FROM EXTERNAL SOURCE
+ 5V
470Q
}>--i-----------=-j xTAL 1
+ 5V
470~,
'----'>----"-1
FOR XTAL 1 AND XTAL 2 DEFINE "HIGH" AS VOLTAGES ABOVE 1.6V AND "LOW"
AS VOLTAGES BELOW 1.8V. THE DUTY CYCLE REQUIREMENTS FOR EXTERNAL LV
DRIVING XTAL 1 AND XTAL 2 USING THE CIRCUIT SHOWN ABOVE ARE AS
FOLLOWS:
FOR THE 8048, XTAL 1 MUST BE HIGH 35·65% OF THE PERIOD AND XTAL 2 MUST
XTAL2
BE HIGH 35·65% OF THE PERIOD.
FOR THE 8748, XTAL MUST
BE HIGH 45·50% OF THE PERIOD AND XTAL 2 MUST
BE HIGH 51).65% OF THE PERIOD.
RISE AND FALL TIMES MUST NOT EXCEED 20
6-41
ns.
AFN·00737·07
'8021
SINGLE COMPONENT a-BIT MICROCOMPUTER
CPU, ROM, RAM, 1/0 in Single
• 8-Bit
28-Pin Package
1K x 8 ROM
• 64
x 8 RAM
21110 Lines
• Single 5V Supply (+4.5V to 6.5V)
p'sec Cycle With 3.58 MHz XTAL;
• 8.38
All Instructions 1 or 2 Cycles
• Interval Timer I Event Counter
• Clock Generated With Single Inductor
or Crystal
• Instructions- 8048 Subset
• High Current Drive Capability-2 Pins
• Zero-Cross Detection Capability
• Easily Expandable 1/0
The Intel I!> 8021 is a totally self·sufficlent a-bit parallel computer fabricated on a single silicon chip using Intel's 1')1channel silicon gate MOS process. The features of the 8021 include a subset of the 8048 optimized for low cost,
high volume applications, plus additional 1/0 flexibility and power.
The 8021 contains 1K X 8 program memory, a 64 X 8 data memory, 21 110 lines, and an 8-bit timer I event counter, in
addition to on-board oscillator and clock circuits. For systems that require extra 1/0 capability, the 8021 can be
expanded using the 8243 or discrete logic.
This microprocessor is designed to be an efficient controller as well as an arithmetic processor. The 8021 has bit
handling capability as well as facilities for both binary and BCD arithmetic. Efficient use of program memory results
from an instru.ction set consisting mostly of single byte instructions and no instructions over two bytes in length.
To minimize the development problems and maximize flexibility, an 8021 system can be easily designed using the
8021 emulation board, the EM·1. The EM-1 contains a 40-pin socket which can accommodate either the 8748
shipped with the board or an ICE-49 plug. Also, the necessary discrete logic to reproduce the 8021 's additional 1/0
features Is Included.
PIN CONFIGURATION
LOGIC SYMBOL
BLOCK DIAGRAM
P22
PORT
#fl
P23
PAOG
PO,
P02
P03
P04
POe
P06
P07
P'6
P'5
P,4
T'
PORT
#2
P'3
P'2
ALE
Vss
PORT
#,
ADDRESS
LATCH
ENABLE
PORT
XTAL2
XTAL 1
EXPANDER
STROBE
6-48
AFN-o'587A-ol
8021
ABSOLUTE MAXIMUM RATINGS'
Ambient Temperature Under Bias ..... , .O°C to 70°C
'COMMENT: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sec·
tions of this specification is not implied. Exposure to absolute maxi·
mum rating conditions for extended periods may affect device
reliability.
Storage Temperature ........... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground ............... -0.5V to + 7V
Power Dissipation
........................... 1 W
D.C. AND OPERATING CHARACTERISTICS
TA
= ooe to 7o oe, Vee = 5.5V
± lV, Vss = OV
Limits
Symbol
Parameter
Typ.
Min.
Max.
Unit
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage (All except XTAL 1& 2, T1
RESET)
3.0
Vee
V
V1Hl
Input High Voltage (XTAL 1 & 2, T1
RESET)
3.8
Vee
V
VIH(10%)
Input high voltage (all except XTAL 1 & 2,
T1, RESEl)
2.0
Vee
V
3.5
Vee
V1H1(10%) Input high voltage (XTAL 1 & 2, T1, RESEl)
VOL
Output Low Voltage
VOLl
Output Low Voltage (P 10, P 11)
VOH
Output High Voltage (All unless Open Drain)
ILO
Output Leakage Current
(Open Drain Option-Port 0)
lee
Vee Supply Current
Test Conditions
Vee
= 5.0V
V
Vee
= 5.0V :t 10%
0,45
V
IOL
2.5
V
2.4
V
±10
J.l.A
75
mA
40
± 10%
= 1.6 mA
IOL = 7 mA
IOH = 40 J.l.A
Vss+0,45.:5VIN.:5Vee
T1 ZERO CROSS CHARACTERISTICS
TA
=O°C to 70°C, Vee =5.5V :t W, Vss =OV, CL =80pF
Symbol
Parameter
Vzx
Zero·Cross Detection Input (T 1)
Azx
Zero· Cross Accuracy
Fzx
Zero· Cross Detection Input Frequency (T 1)
Min.
Max.
1
3
0.05
6-49
Unit
Vpp
± 135
mV
1
kHZ
Test Conditions
AC Coupled, C = .2j.1F
60 Hz Sine Wave
AFNo01567A·02
~!m[§!!"U~UOO~!mW
8021
PIN DESCRIPTION
Designation
Pin #
Function
Designation
Vss
14
Circuit GND potential
Vee
PROG
28
+5V power supply
3
Output strobe for 8243 1/0
Expander
POO-P07
port 0
4-11
P10-P17
Port 1
18-25 8-bit quasi-bidirectional port
P20-P23
26-27
Pin #
Function
CNT instruction. Also allows
zero-crossover sensing of
slowly moving inputs.
Input used to initialize the processor by clearing status flipflops and setting program
counters to zero.
RESET
17
ALE
12
Address Latch, Enable. Signal
occurring once every 30 input
clocks, used as an output
clock.
8-bit quasi-bidirectional port
4-bit quasi-bidirectional port
Port 2
1-2
P20-P23 also serve as a 4-bit
110 expander bus for 8243
XTAL1
15
T1
13
Input pin testable using the JT 1
and JNT1 instructions. Can be
designated the timer I event
counter input using the STRT
One side of crystal or inductor
input for internal oscillator. Also
input for external source. (Not
TTL compatible.)
XTAL2
16
Other side of timing control
element.
INSTRUCTION SET
Mnemonic
Description
Add register to A
Add data memory to A
Add immediate to A
Add register with carry
Add data memory with
carry
ADDC A,#data Add immediate with
carry
ANL A,R r
And register to A
ANL A,@R
And data memory to A
ANL A,#data And immediate to A
Or register to A
ORL A,R r
Or data memory to A
ORL A,@R
ORL A,#data Or immediate to A
Exclusive Or register
E XRL A,R r
to A
c XRL A,@R
Exclusive Or data
memory to A
XRL A,#data Exclusive Or immediate
to A
INC A
Increment A
Decrement A
DEC A
CLR A
Clear A
Complement A
CPL A
OAA
O~cimal adjust A
SWAP A
Swap nibbles of A
RL A
Rotate A left
RLC A
Flotate A left through
carry
RR A
Rotate A right
RRC A
Rotate A right through
carry
ADD A,R r
ADD A,@R
ADD A,#data
ADDC A,R r
ADDCA,@R
j
"
"
""
IN A, Pp
'5 OUTLP A
MOVO x.P p
0
MOVO Pp,A
f
:s
!
j
ANLO Pp,A
ORLO Pp,A
INCR r
IINC@R
!
Input port to A
Output A to port
Input expander port
to A
Output A to expander
port
And A to expander port
Or A to expander port
Increment register
Increment data memory
Byte.
Cycle
1
2
1
2
2
2
2
1
2
2
Hexadecimal
Opcode
6S'6F
60-61
03
7S·7F
70-71
JMP addr
...
"c
~
13
5S-5F
50·51
53
4S·4F
40·41
43
DS·OF
:Ii•
g
..g
00·01
i
03
2
··•
:i
67
2
2
2
3C·3F
2
2
9C·9F
SC·SF
RET
Return
CLRC
Clear carry
Complement carry
Move register to A
Move data memory to A
Move iJ1lrnediate to A
Move A to register
Move A to 'dahl memory
Movf! im"!'edtate ~o
register
MOV@R,#data Move immediate to
data memory
Exchange A and
XCHA,R,
register
XCHA,@R
Exchange A and data
memory
Exchange nibble of A
XCHOA,@R
and register
MOVPA,@A
Move to A from current
page
MOVA,R r
MOVA,@R
MOV A,#data
MOV Rr,A
MOV@R,A
MOV Rr,#data
t
MOVA,T
MOVT,A
~ STRTT
~ STRT CNT
STOP TCNT
0
IS-IF
10·11
~
NOP
6'50
2
2
2
2
Cycl.
Hexadecimal
Opcode
2
04,24.44,64,
2
2
B3
ES-EF
2
2
2
2
2
F6
E6
C6
96
56
46
16
14,34,54,74
Jump to subroutine
•"
77
OS,09.0A
90,39,3A
OC-OF
CALL addr
Byte.
Jump unconditional
JMPP@A
Jump indirect
DJNZ R,o addr Decrement register and
jump oo'R nof zero
Jump on carry= 1
JC addr
JNC addr
Jump o"n carry=O
Jump on A zero
JZ addr
Jump on A not zero
JNZ addr
Jump on Tl=1
JT1 addr
JNTI addr
Jump on Tl=O
JTF addr
Jump on timer flag
it CPL C
17
07
27
37·
57
47
E7
F7
-I
Description
Mnemonic
2
S3
97
A7
1
2
1
2
1
2
2
2
FS·FF
FO·Fl
23
AS·AF
AO-Al
BS·BF
BO·Bl
2S·2F
20·21
30-31
2
A3
Read timer I counter
Load timer J counter
Start timer
Start counter
Stop timer I counter
42
62
55
45
65
No operation
00
AFN-D1S87A-Il3
8022
SINGLE COMPONENT a-BIT MICROCOMPUTER
WITH ON-CHIP AID CONVERTER
• 2K x 8 ROM, 64 x 8 RAM, 28 1/0 Lines
8.38 ,usec Cycle; All Instructions 1 or 2
• Cycles
• 8-Bit CPU, ROM, RAM, 1/0 in Single 40-Pin
Package
8-Bit AID Converter; Two Input
• On-Chip
Channels
• Instructions-8048 Subset
• Interval Timer IEvent Counter
Clock Generated with Single Inductor or
• Crystal
• 8 Comparator Inputs (Port 0)
• Zero-Cross Detection Capability
• Single SV Supply (4.SV to 6.SV)
• High Current Drive Capability-2 Pins
• Two Interrupts-External and Timer
• Easily Expanded 1/0
The Intel@) 8022 is the newest member of the MCS-48™ family of single chip 8-bit microcomputers_ It is designed to
satisfy the requirements of low cost, high volume applications which involve analog signals, capacitive touchpanel
keyboards, and I or large ROM space. The 8022 addresses these applications by integrating many new functions onchip, such as AID conversion, comparator inputs and zero-cross detection.
The features of the 8022 include 2K bytes of program memory (ROM), 64 bytes of data memory (RAM), 28 110 lines,
an on-chip AID converter with two input channels, an 8-bit port with comparator inputs for interfacing to low voltage
capacitive touchpanels or other non-TIL interfaces, external and timer interrupts, and zero-cross detection capability. In addition, it contains the 8-bit interval timer I event counter, on-board oscillator and clock circuitry, single 5V
power supply requirement, and easily expandable 1/0 structure common to all members of the MCS.-48 family.
The 8022 is designed to bean efficient controller as well as an arithmetic processor. It has bit handling capability
plus facilities for both binary and BCD arithmetic. Efficient use of program memory results from using the MCS-48
instruction set which consists mostly of single byte instructions and has extensive conditional jump and direct table
lookup capability. Program memory usage is further reduced via the 8022's hardware implementation of the AID
converter which simplifies interfacing to analog signals.
Vee
P26
Vee
P21
P2S
AVec
VAREF
ANl
P2'
PROG
BLOCK DIAGRAM
LOGIC SYMBOL
PIN CONFIGURATION
XTAL
Vss
r
PORTO
THRESHOLD
REFERENCE , -_ _ _----,
REseT ....
P23
P22
AVSS
P21
TO
P20
P11
TEST 0..
8022
TEST 1
Pl.
P1S
P02
Pl'
P03
P13
P04
P12
POS
P11
PO.
Pl.
P01
RESET
ALE
XTAL 2
T1
XTAL 1
Vss
SUBST
AlD
REFERENCE
ADDRESS
LATCH
AND ...
ENABLE
PORT
--EXPANDER
ANl
STROBE
AID
Vee
I
AID SUBSTRATE
Vas
6-51
AFN-00187A-o1
~rru[§I!..OIMlOIM~rruw
8022
PIN DESCRIPTION
Designation
Pin #
Function.
Designation
Vss
20
Circuit GND p6tential.
RESET
Vee
PROG
40
+ 5V circuit power supply.
37
Output strobe for Intel@ 8243
I I 0 expander.
POO-P07
Port 0
10-17 8-bit open-drain port with qoinparator inputs. The switching
threshold is set externally by
VTH. Optional pull-up resistors
may be added via ROM mask
selection.
9
25-32 8-bit quasi-bidirectional port.
P20-P27
33-36 8-bit quasi-bidirectional port.
Port 2
38-39 P20-23 also serve as a 4-bit
1-2
1/0 expander for Intel@ 8243.
T1
8
19
Interrupt input and input pin
testable using the conditional
transfer instructions JTO and
JNTO. Initiates an interrupt following a low level input if interrupt is enabled. Interrupt is
disabled after a reset.
Input pin testable using the JT1
and JNT 1 conditional transfer
instructions. Can be designated the timer I event counter input using the STRT CNT
instruction. Also serves as the
zero-cross detection input to
allow zero-crossover sensing
of slowly moving AC inputs. Optional pull-up resistor may be
added via ROM mask selection.
Function
24
Input used to initialize the processor by clearing status flipflops and setting the program
counter to zero.
AVSS
7
AID converter GND Potential.
Also establishes the lower limit
of the conversion range.
AVee
SUeST
3
AID
21
Substrate pin used with a bypass capacitor to stabilize the
substrate voltage and improve
AID accuracy.
VAREF
4
A I D converter reference voltage. Establishes the upper limit
of the conversion range.
ANO,AN1
6,5
Analog inputs to AID converter.
Software selectable on-chip
via SEL ANO and SEL AN 1
instructions.
ALE
18
Address Latch Enable. Signal
occurring once every 30 input
clocks (once every cycle),
used as an output clock.
XTAL 1
22
One side of crystal or inductor
input for internal oscillator. Also
input for external frequency
source. (Not TTL compatible.)
XTAL 2
23
Other side of timing control element. This pin is not connected
when an external frequency
source is used.
Port 0 threshold reference pin.
VTH
P10-P17
Port 1
TO
Pin #
+ 5V power supply.
THE STAND ALONE 8022
PI.
P11
P12
V.,..,
PI'
AVec
2.
25
.
27
28
10-2oo,u.F
AV. .
2.
l00pF
SILVER MICA
Vaa
I,F
8 . .2
P2'
P••
P••
P26
P27
VTN
SUBST
AND
AID INPUTS {
ANI
PDO
POI
XTAL1
PO>
1M
P03
PDO
XTAL2
PO!
T1
.8
••
I.
11
12
,.,.
13
}-,
}-.
}-.
[ INPUT ]
AND
OUTPUT
[ WPUT ]
' AND
OUTPUT
[ INPUT
AND ]
. OUTPUT
NC
6-52
AFN.(J()187A-QZ
8022
ABSOLUTE MAXIMUM RATINGS'
'COMMENT: Stresses above those listed under "Absolute Maximum
Ratings" may cuase permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sec·
tions of this specification is not implied. Exposure to absolute maxi·
mum rating conditions for extended periods may affect device
reliability.
Ambient Temperature Under Bias ....... O°C to 70°C
Storage Temperature ........... -S5°C to +180°C
Voltage on Any Pin with
Respect to Ground ................. -0.5V to +7V
Power Dissipation ......................... 1 Watt
D.C. AND OPERATING CHARACTERISTICS
TA=O°C to 70°C, Vee=5.5V ± 1V, VSS=OV
Limits
Parameter
Symbol
Min.
Typ.
Unit
Max.
Test Conditions
VIL
Input Low Voltage
-0.5
0.8
V
VILI
Input Low Voltage (Port 0)
-0.5
VTH-O.l
V
VIH
High Voltage
(All except XTAL 1, RESET)
2.0
Vee
V
Vee = 5.0V ± 10%
VTH Floating
VIHI
Input High Voltage
(All except XTAL 1, RESET)
3.0
Vee
V
Vee = 5.5V ± 1V
VTH Floating
VIH2
Input High Voltage (Port 0)
VTH+O.l
Vee
V
VIH3
Input High Voltage (RESET, XTAL 1)
3.0
Vee
V
VTH
Port 0 Threshold Reference Voltage
0
.4Vee
V
VOL
Output Low Voltage
VOlt
Output Low Voltage (Pl0, Pll)
VOH
Output High Voltage (All unless Open Drain
Option-Port 0)
III
Input Current (T 1)
±200
/LA
VCC~VIN~VSs+.45V
ILO
Output Leakage Current (Open Drain
Option-Port 0)
±10
/LA
VCC~VIN~VSS+O.45V
lee
Vee Supply Current
100
rnA
VTH Floating
Vee
= 5.0V ±
0.45
V
IOL = 1.S mA
2.5
V
IOL = 7 mA
V
IOH
2.4
50
10%
= 50 /LA
A.C. CHARACTERISTICS
Symbol
Parameter
tey
Cycle Time
Vzx
Zero-Cross Detection Input (T 1)
Azx
Zero-Cross Accuracy
Fzx
Zero-Cross Detection Input Frequency (Tl)
Min.
Max.
8.38
1
0.05
6-53
Unit
Test Conditions
50.0
/Ls
3 MHz XTAL= 10 /LS tey
3
VACpp
± 135
rnV
1
kHz
AC Coupled
SO Hz Sine Wave
AFN.oo187A-03
8022
A.C. CHARACTERISTICS
TA=O·C to 70·C, Vcc=5.5V ± 1V, vss=ov
Parameter
Min.
tcp
Port Control Setup Before Falling Edge of PROG
0.5
tpc
Port Control Hold After Falling Edge of PROG
0.8
tPR
PROG to Time P2 Input Must Be Valid
Symbol
Expander
Operation
Normal
Operation
Test Conditions: Cl =80 pF
Max.
top
Output Data Setup Time
7.0
Output Data Hold Time
8.3
tpF
Input Data Hold Time
tpp
PROG Pulse Width
tpRl
ALE to Time P2 Input Must Be Valid
0
j.ls
j.ls
j.lS
j.lS
.150
8.3
j.ls
j.ls
3.6
j.ls
tpl
Output Data Setup Time
0.8
j.lS
tlP
Output Data Hold Time
1.6
j.lS
tpFl
Input Data Hold Time
tll
ALE Pulse Width
j.lS
0
3.9
Notes
j.lS
1.0
tpo
Unit
tCy=8.38 j.ls
23.0
j.lS
tCy=8.38 j.lS for min
PORT 2 TIMING
NORMAL OPERATION
~
~
ALEr\
PORT
OUTPUT
______________________
~n~
______ _______________
~
===x------------------------------~----------------------------------~
~
ALE/\
PORT
INPUT
______________________~r_\~________________________
------------------~(~_ _ _ _ _D_AT_A_ _ _ _~)(~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _
---ooj·1
I·
H
IpAL
tpFL
EXPANDER OPERATION
ALE
n
~
______________________
~r_\~
________________________
\~------------------~/
PAOG
J!Cd-------------'''------------f
..
1
PORT ___________________________________~~_______________~)(
OUTPUT
x=====
DATA
L,,,...L.J
,. .--r;;;-l
~
______________________~r_\~_________________________
ALEF\
PROG
PORT
INPUT
\~------------------~I
F
~~--------------~~
DATA
----------------------------~
~"c-.j
'"
r--'''---1
6-54
AFN-Q0187A-04
8022
AID CONVERTER CHARACTERISTICS
TA= O'C to 70'C, Vcc= 5.5V:!:: 1V, Vss= OV, AVcc= 5.5V:!:: W, AVss= OV, AVccl2 .. VAREF" AVCC
Parameter
Min.
Typ.
Max.
8
Resolution
Unit
.8% FSR:!:: 112 LSB
Absolute Accuracy
LSB
Sample Setup Before Falling Edge of ALE (tsal
0.20
tCY
Sample Hold After Failing Edge of ALE (ts H)
0.10
tCY
Input Capacitance (ANO, AN1)
1
Conversion Time
Comments
Bits
(Note 1)
pF
4
4
tCY
ANALOG INPUT TIMING
ALE
ISH
ANALOG
INPUT
. NOTE:
1. The analog Input must be maintained at a conslsnt voltage during the sample time (tss+ tSH)'
6-55
AFN-«I187A~
~1Rl[gI!..O~OOO~IRlW
8022
INSTRUCTION SET
Mnemonic
ADD A,R,
ADD A,@R
ADD A,#data
ADDC A_R,
ADDCA,@R
Description
Add
Add
Add
Add
Add
,egiste, to A
data memo,y to A
immediate to A
register with carry
data memory with
Byte.
Cycle
Hexadecimal
Opcode
Hexadecimal
Mnemonic
S8-6F
60-61
03
78-7F
70-71
2
2
2
1
1
2
2
2
2
i
IN A, Pp
OUTL Pp.A
;; MOVD A,P
p
S
~
~ MOVD Pp,A
;;
D.
= ANlD Pp,A
ORlD Pp,A
13
58-5F
50-51
53
48-4F
40-41
43
D8-DF
DO-Dl
2
2
D3
17
07
27
37
57
47
E7
F7
1
1
77
67
Input po,t to A
Output A to po,t
Input expander port
to A
Output A to expander
port
And A to expande, port
Or A to expander port
2
2
2
2
08,09,OA
90,39,3A
OC-OF
•
ZINC R,
INC@R
-ij.
•
Increment register
Increment data memory
CALL add,
Jump to subroutine
RET
Return
CLR C
CPL C
Complement carry
!!
~
'"
f!.'"
.
JMPP@A
.c
u DJNZ R,add,
c
£ JC add,
JNC add,
JZ add,
JNZ add,
Jump indirect
Decrement register and
jump on R not zero
Jump on carry= 1
Jump on carry=O
Jump on A zero
Jump on A not zero
2
~
XCHDa,@R
,
MOVPA,@A
2
2
2
2
2
2
F6
E6
C6
96
Exchange A and
register
Exchange A and data
memory
Exchange nibble of A
and register
Move to A from current
page
i RAD
Move conversion result
register to A
Select analog input
zero
Select analog input one
1::
c>
•
SEl AND
u
~ SEL AN1
c
EN I
.
RET I
Enable external
interrupt
Disable external
interrupt
Enable timer I counter
interrupt
Disable timer I counter
interrupt
Return from interrupt
NOP
No operation
DIS I
a
E EN TCNTI
i
DIS TCNTI
2
2
2
2
2
2
2
2
2
2
36
26
56
46
16
2
14,34,54,74
94,B4,D4,F4
83
.1
2
Opcode
97
A7
2
2
2
2
F8-FF
FO-Fl
23
A8-AF
AO-Al
B8-BF
2
2
BO-Bl
Move data memory to A
Read timer I counter
Load timer I counter
Start timer
Start counter
Stop timer I counter
9C-9F
8C-8F
Cycle
Move register to A
MOVA,T
MOVT,A
~ STRTT
i STRTCNT
STOP TCNT
~
0
~
2
2
XCHA,R,
XCH A,@R
3C-3F
04,24,44,64,
84,A4,C4,E4
B3
ES-EF
MOVA,R,
MOVA,@R
MOV A,#data
MOV R"A
MOV@R,A
MOV R,,#data
•
Q
Bytes
Clear carry
Move immediate to A
Move A to register
Move A to data memory
Move immediate to
register
is MOII@R,#data Move immediate to
:I
data memory
18-1F
10-11
Jump unconditional
TO=1
TO=O
Tl= 1
Tl=O
time' flag
Z>
II:
JMP add,
on
on
on
on
on
~
0
I!
Jump
Jump
Jump
Jump
Jump
JTOadd,
JNTOadd,
JT1 add,
JNT1 add,
JTF add,
carty
ADDC A,#data Add immediate with
carry
And ,egiste, to A
ANL A,R,
ANL A,@R
And data memory to A
ANL A,#data And immediate to A
ORL A,R,
Or register to A
ORLA,@R
Or data memory to A
ORl A,#data Or immediate to A
Exclusive Or register
XRl A,R,
to A
E
~
XRL
A,@R
Exclusive Or data
u
u
memory to A
c
XRL A,#data Exclusive Or immediate
to A
INC A
Increment A
DEC A
Decrement A
CLR A
Clea' A
CPL A
Complement A
DAA
Decimal adjust A
SWAP A
Swap nibbles of A
RL A
Rotate A left
RLCA
Rotate A left th,ough
carry
Rotate A ,ight
RR A
RRCA
Rotate A ,ight th,ough
carry
Description
28-2F
20-21
30-31
2
A3
42
62
65
46
66
2
80
85
95
05
15
25
35
2
93
00
SYMBOLS AND ABBREVIATIONS USED
A
addr
ANO,AN1
CNT
data
I
Accumulator
11-Bit Program Memory Address
Analog Input 0, Analog Input 1
Event Counter
8-Bit Number or Expression
Interrupt
P
Pp
Rr
T
TO, T1
#
@
6-56
Mnemonic for "in-page" Operation
Port Designator (P=O, 1,2 or 4-7)
Register Designator (r=0-7)
Timer
Test 0, Test 1
Immediate Data Prefix
Indirect Address Prefix
AFN-ocJ187A-08
inter
8243
MCS-48™ INPUT/OUTPUT EXPANDER
•
•
•
•
• Low Cost
• Simple Interface to MCS-48T1' Microcomputers
• Four 4-Bit I/O Ports
• AND and OR Directly to Ports
24-Pln DIP
Single 5V Supply
High Output Drive
Direct Extension of Resident 8048 I/O
Ports
The Inele 8243 is an input/output expander designed specifically to provide a low cost means of 1/0 expansion for the
M£S-48" family of single chip microcomputers. Fabricated in 5 volts NMOS, the 8243 combines low cost, single supply
voltage and high drive current capability.
The 8243 consists of four 4-bit bidirectional static 110 ports and one 4-bit port which serves as an interface to the MCS-48
microcomputers. The 4-bit interface requires that only 4 1/0 lines of the 8048 be used for 1/0 expansion, and also allows
multiple 8243's to be added to the same bus.
The 1/0 ports of the 8243 serve as a direct extension of the resident ilO facilities of the MCS-48 microcomputers and are
accessed by their own MOV, ANL, and ORL instructions.
BLOCK DIAGRAM
PIN CONFIGURATION
PORT4
P60
vee
P40
HI
P51
P52
N2
P63
1'43
P60
~
P51
MOG
P52
P23
P53
P73
P72
P71
P70
P22
P21
P20
GND
PORT 5
PORT 2
PORTa
PORT7
6-57
AFN-00214A~1
8243
PIN DESCRIPTION
Symbol
Pin No.
Function
PROG
7
Clock Input. A high to low
transistion on PROG signi.fies
that address and control are
available on P20-P23, and a low
to high transition signifies that
data is available on P20-23.
P20-P23
GND
P40-P43
P50-P53
P60-P63
P70-P73
Vee
6
Chip Select Input. A high on CS
inhil;lits any change of output or
internal status.
11-8
Four (4) bit bi-directional port
contains the address and control bits on a high to' low
transition of PROG. During a
low to high transition contains
the data for a selected output
port if a write operation, or the
data from a selected port before
the low to high transition if a
read operation.
12
2-5
1,23-21
20-17
13-16
24
o volt supply.
Four (4) bit bi-directional 110
ports. May be programmed
to be input (during read),
low impedance latched output
(after write) or a tri-state (after
read). Data on pins P20-23 may
be directly written, ANDed or
ORed with previous data.
+5 volt supply.
FUNCTIONAL DESCRIPTION
General Operation
The 8243 contains four 4-bit 1/0 ports which serve as an
extension of the on-chip 1/0 and are addressed as ports 47. The following operations may be performed on these
ports:
•
•
•
•
Transfer Accumulator to Port.
Transfer Port to Accumulator.
AND Accumulator to Port,
OR Accumulator to Port.
All communication between the 8048 and the 8243 occurs
over Port 2 (P20-P23) with timing provided by an output
pulse on the PROG pi'n of the processor. Each transfer
consists of two 4-bit nibbles:
The first containing the "op code" and port address and
the second containing the actual 4-bits of data.
A high to low transition of the PROG line indicates that
address is present while a low to high transition indicates
the presence of data. Additional 8243's may be added to
the 4-bit bus and chip selected using additional output
lines from the 8048/8748/8035.
Power On Initialization
Initial application of power to the device forces
input/output ports 4, 5, 6, and 7 to the tri-state and port 2 to
the input mode. The PROG pin may be either:high or low
when power is applied. The first high to low transition of
PROG causes device to exit power on mode. The power on
sequence is initiated if Vee drops below 1V.
P21
P20
0
0
1
1
0
1
0
Address Code
Port
Port
Port
Port
4
5
6
7
P23 P22 Instruction Code
0
0
1
0
0
Read
Write
ORlD
ANlD
Write Modes
The device has three write modes. MOVD Pi, A directly
writes new data into the selected port and old data is lost.
ORlD Pi,A takes new data, OR's it with the old data and
then writes it to the port. ANlD Pi,A takes new data AND's
it with the old data and then writes it to the port. Operation
code and port address are latched from the input port 2 on
the high to low transition of the PROG pin. On the low to
high transition of PROG data on port 2 is transferred to the
logic block of the specified output port.
After the logic manipulation is performed, the data is
latched and outputed. The old data remains latched until
new valid outputs are entered.
Read Mode
The device has one read mode. The operation code and
port address are latched from the input port 2 on the high
to low transition of the PROG pin. As soon as the read
operation and port address are decoded, the appropriate
outputs are tri-stated, and the input buffers switched on.
The read operation is terminated by a low to high
transition of the PROG pin. The port (4, 5, 6 or 7) that was
selected Is switched to the tri-stated mode while port 2 is
returned to the input mode.
Normally, a port will be in an'output (write mode) orinput
(read mode). If modes are changed during operation, the
first read following a write should be ignored; all following reads are valid. This is to allow the external driver on
the port to settle after the first read instruction removes
the low impedance drive from the 8243 output. A read of
any port will leave that port in a high impedance state.
&-58
AFN-00214A-Q2
8243
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" mav cause permanent damage to the
device. This is a stress rating on IV and functional opera·
tion of the device at these or anv other conditions above
those indicated in the operational sections of this specifi·
cation is not implied. Exposure to absolute maximum
rating conditions for extended periods mav affect device
reliabilitv.
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias ............... O·C to.70·C
Storage Temperature ............................. -65·C to +150·C
Voltage On Any Pin
With Respect to Ground ............................ -0.5 V to +7V
Power Dissipation ......................................................1 Watt
D.C. AND OPERATING CHARACTERISTICS
TA = O·C to 70·C, Vee= 5V
10%
TYP.
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
Vee+0.5
V
0.45
V
IOL = 4.5 mA*
1
V
IOL = 20 mA
20
MA
V in = Vee to OV
V in = Vee to OV
.--~
VOL1
Output Low Voltage Ports 4-7
VO L2
Output Low Voltage Port 7
VO H1
Output High Voltage Ports 4-7
2.4
11L1
Input Leakage Ports 4-7
-10
IIL2
Input Leakage Port 2, CS, PROG
-10
VO L3
Output Low Voltage Port 2
lee
Vee Supply Current
VOH2
Output Voltage Port 2
IOL
-
V
10
10
MA
.45
V
20
mA
72
mA
IOH= 240MA
IOL= 0.6 mA
IOH= 100MA
2.4
Sum of all IOL from 16 Outputs
4.5 mA Each Pin
*See following graph for additional sink current capability
A.C. CHARACTERISTICS
TA = o·c to 70·C, Vee= 5V
10%
SYMBOL
PARAMETER
tA
Code Valid Before PROG
100
ns
t8
Code Valid After PROG
60
ns
20 pF Load
ns
80 pF Load
ns
20 pF Load
ns
20 pF Load
MIN.
MAX.
UNITS
te
Data Valid Before PROG
200
to
Data Valid After PROG
20
tH
Floating After PROG
0
tK
PROG Negative Pulse Width
700
ns
tes
CS Valid Before/After PROG
50
ns
tpo
Ports 4-7 Valid After PROG
tLPl
Ports 4-7 Valid Before/After PROG
tAee
Port 2 Valid After PROG
150
700
ns
TEST CONDITIONS
80 pF Load
-- - - - - _ .
100 pF Load
ns
100
650
ns
80 pF Load
2.4---"",X >
_
_'0'.0
8
TEST POINTS
0.45 _ _ _oJ
6-59
AFN-00214A-03
8243
WAVEFORMS
PROG
~-----------------IK----------------~
FLOAT
PORT 2
..
"~;1
PORT 2
FLOAT
'"'~'~'"x
VALID
_ I PO
OUTPUT
VALID
PREVIOUS OUTPUT VALID
PORTS 4·7
--10>
l,P
PORTS 4-7
l,P
INPUT VALID
les
6-60
AFN--0O214A-04
8243
125
«
E
~ 100
o
~
~
zw
75
a:
a:
a
GUARANTEED WORST CASE
CURRENT SINKING
CAPABiliTIES OF ANY I/O
PORT PIN vs. TOTAL SINK
CURRENT OF All PINS
50
~
z
en
-I
«
~
25
o~
o L - - L_ _
o
~~~-L
2
3
4
__~~__- L__~~__- L__~~__~
5
6
7
8
9
10
11
12
13
MAXIMUM SINK CURRENT ON ANY PIN@.45V
MAXIMUM 10L WORST CASE PIN (mA)
Sink Capability
Example: This example shows how the use of the 20
mA sink capability of Port 7 affects the sinking capability of the other I/O lines.
The 8243 can sink 5 mA@.45Von each of its 16 I/O lines
simultaneously. If, however, all lines are not sinking
simultaneously or all lines are not fully loaded, the drive
capability of any individual line increases as is shown by
the accompanying curve.
An 8243 will drive the following loads simultaneously.
For example, if only 5 of the 16 lines are to sink current
at one time, the curve shows that each of those 5 lines is
capable of sinking 9 mA@.45V (if any lines are to sink
9 mA the total 10l must not exceed 45 mA or five 9 mA
loads).
2 loads - 20 mA@ 1V (port 7 only)
8 loads - 4 mA@.45V
6 loads - 3.2 mA@ .45V
Is this within the specified limits?
Example: How many pins can drive 5 TTL loads (1.6 mAl
assuming remaining pins are unloaded?
dOL =
d Ol =( 2 x 20)+(8 x 4)+(6 x 3.2)=91.2 mAo
From the curve: for 10l = 4 mA, dOL:: 93 mA
since 91.2 mA < 93 mA the loads are within
specified limits.
In this case, 7 lines can sink 8 mA for a total
of 56 mAo This leaves 4 mA sink current capability which can be divided in any way among
the remaining 8 I/O lines of the 8243.
Although the 20 mA@1V loads are used in
calculating dOL, it is the largest current required@.45Vwhich determines the maximum
allowable dOL'
10l = 5 x 1.6 mA = 8 mA
60 mA from curve
# pins=60 mA ... 8 mA/pin=7.5=7
Note: A 10 to 50Kn pullup resistor to +5V should be added to 8243 outputs when driving to 5V CMOS directly.
6-61
AFN-00214A-Q5
8243
EXPANDER INTERFACE
-=-
cs
I/O
P'
I/O
P5
I/O
P6
I/O
P7
I/O
PROG
8048
TEST
INPUTS
P20-P23
8243
DATA IN
P2
OUTPUT EXPANDER TIMING
BITS 1,0
BITS 3,2
OO}
P20-P23
_--'X. . .___...J)r---
01
10
11_
- - (.....
ADDRESS 14-BITS)
REAO
WRITE
OR
AND
O1J
OO~
Hl
PORT
ADDRESS
"
DATA (4-8IT8)
BUS
PORT 1
804B
PORT 2
PROG.-----------------~------------------+_----------------~~
________________~
USING MULTIPLE 8243'5
6-62
AFN-oQ214A-08
inter
108243
MCS-48™ INPUT/OUTPUT EXPANDER
• 24-Pin DIP
• Single 5V Supply
• High Output Drive
Direct Extension of Resident 8048 1/0
• Ports
- 40°C to + 85°C Operation
• Low
• SimpleCostInterface to MCS-48™ Micro• computers
Four 4-Bit 1/0 Ports
• AND
• and OR Directly to Ports
The Intel!!> 8243 is an input/output expander desigrjed specifically to provide a low cost means of I/O expansion for the
MCS-48'· family of single chip microcomputers. Fabricated in 5 volts NMOS, the 8243 combines low cost, single supply
voltage and high drive current capability.
The 8243 consists of four 4-bit bidirectional static I/O ports and one 4-bit port which serves as an interface to the MCS-48
microcomputers. The 4-bit interface requires that only 4 I/O lines of the 8048 be used for I/O expansion, and also allows
multi pie 8243's to be added to the same bus.
The 1/0 ports of the 8243 serve as a direct extension of the resident 1/0 facilities of the MCS-48 microcomputers and are
accessed by their own MOV, ANL, and ORL instructions.
BLOCK DIAGRAM
PIN CONFIGURATION
PORT 4
PSO
vee
P40
PS'
1'4'
P52
1'42
P53
1'43
PSO
cs
P6,
PROG
P62
P23
P63
P22
P73
P2,
P72
PORT 5
PORT 2
P20
P7'
GNO
P70
PORT 6
PORT 7
6-63
AFN-Q0861A-01
18243
PIN DESCRIPTION
Symbol
Pin No.
Function
PROG
7
Clock Input. A high to low
transistion on PROG signifies
that address and control are
available on P20-P23, and a low
to high transition signifies that
data is available on P20-23.
P20-P23
GND
P40-P43
P50-P53
P60-P63
P70-P73
Vee
6
Chip Select Input. A high on CS
inhibits any change of output or
internal status.
11-8
Four (4) bit bi-directional port
contains the address and control bits on a high to low
transition of PROG. During a
low to high transition contains
the data for a selected output
port if a write operation, or the
data from a selected port before
the low to high transition if a
read operation.
12
2-5
1,23-21
20-17
13-16
24
o volt supply.
Four (4) bit bi-directional I/O
ports. May be programmed
to be input (during read),
low impedance latched output
(after write) or a tri-state (after
read). Data on pins P20-23 may
be directly written, ANDed or
ORed with previous data.
+5 volt supply.
FUNCTIONAL DESCRIPTION
General Operation
The 8243 contains four 4-bit I/O ports which serve as an
extension of the on-chip I/O and are addressed as ports 47. The following operations may be performed on these
ports;
•
•
•
•
Transfer Accumulator to Port.
Transfer Port to Accumulator.
AND Accumulator to Port.
OR Accumulator to Port.
A high to low transition of the PROG line indicates that
address is present while a low to high transition indicates
the presence of data. Additional 8243's may be added to
the 4-bit bus and chip selected using additional output
lines from the 8048/8748/8035.
Power On Initialization
Initial application of power to the device forces
input/output ports 4, 5, 6, and 7 to thetri-state and port 2to
the input mode. The PROG pin may be either high or low
when power is applied. The first high to low transition of
PROG causes device to exit power on mode. The power on
sequence is initiated if Vee drops below 1V.
P21
P20
0
0
0
1
0
Address Code
Port
Port
Port
Port
4
5
6
7
P23 P22 Instruction Code
0
0
0
1
0
Read
Write
ORlD
ANlD
Write Modes
The device has three write modes. MOVD Pi, A directly
writes new data into the selected port and old data is lost.
ORlD Pi,A takes new data, OR's it with the old data and
then writes it to the port. ANlD PiA takes new data AND's
it with the old data and then writes it to the port. Operation
code and port address are latched from the input port 2 on
the high to low transition of the PROG pin. On the low to
high transition of PROG data on port 2 is transferred to the
logic block of the specified output port.
After the logic manipulation is performed, the data is
latched and outputed. The old data remains latched until
new valid outputs are entered.
Read Mode
The device has one read mode. The operation code and
port address are latched from the input port 2 on the high
to low transition of the PROG pin. As soon as the read
operation and port address are decoded, the appropriate
outputs are tri-stated, and the input buffers switched on.
The read operation is terminated by a low to high
transition of the PROG pin. The port (4, 5, 6 or 7) that was
selected is switched to the tri-stated mode while port 2 is
returned to the input mode.
Normally, a port will be in an output (write mode) orinput
(read mode). If modes are changed during operation, the
first read following a write should be ignored; all following reads are valid. This is to allow the external driver on
the port to settle after the first read instruction removes
the low impedance drive from the 8243 output. A read of
any port will leave that port in a high impedance state.
All communication between the 8048 and the 8243 occurs
over Port 2 (P20-P23) with timing provided by an output
pulse on the PROG pin of the processor. Each transfer
consists of two 4-bit nibbles;
The first containing the "op code" and port address and
the second containing the actual 4-bits of data.
6-64
AFN-00861A-02
18243
ABSOLUTE MAXIMUM RATINGS·
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause, permanent damage to the
device. This is a stress rating only and functional opera·
tion of the device at these or any other conditions above
those indicated in the operational sections of this specifi·
cation is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Ambl.nt T.mp.ratur. Und.r Bias .......... ,-40·C to +85·C
Storage T.mperature ............................. -65·C to +1S0·C
Voltag. On Any Pin
With Respect to Ground ............................ -o.S V to +7V
Pow.r Dissipation ...................................................., '1 Watt
D.C. AND OPERATING CHARACTERISTICS
TA = -4O·C to +8S·C, Vee= SV
1Q11b
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
VIL
Input Low Voltage
-0.5
TYP.
0.8
V
VIH
Input High Voltage
2.0
Vee+0.5
V
VO LI
Output Low Voltage Ports 4-7
0.45
V
IOL =4.5mA*
VOL2
Output Low Voltage Port 7
1
V
IOL = 20 mA
VOHI
Output High Voltage Ports 4-7
2.4
IILl
Input Leakage Ports 4-7
-10
20
IlA
Vin = Vee to OV
IIL2
Input Leakage Port 2, CS. PROG
-10
10
IlA
Vin = Vee to OV
VOL3
Output Low Voltage Port 2
lee
Vee Supply Current
VOH2
Output Voltage Port 2
IOL
Sum of all IOL from 16 Outputs
V
10
.45
V
20
mA
80
mA
2.4
TEST CONDITIONS
IOH= 240llA
IOL= 0.6 mA
IOH= lOOILA
4.5 mAEach Pin
·See following graph for additional sink current capability
A.C. CHARACTERISTICS
TA =-40·C to +8S·C, Vee= SV
10%
SYMBOL
PARAMETER
tA
Code Valid Before PROG
100
ns
te
Code Valid After PROG
60
ns
20 pF Load
te
Data Valid Before PROG
200
ns
80 pF Load
to
Data Valid After PROG
20
ns
20 pF Load
tH
Floating After PROG
0
ns
20 pF Load
tK
PROG Negative Pulse Width
700
ns
tcs
CS Valid Before/Afte(PROG
50
ns
tpo
Ports 4·7 Valid After PROG
tLPl
Ports 4-7 Valid Before/After PROG
tAee
Port 2 Valid After PROG
2.4
MIN.
MAX.
UNITS
150
ns
700
100
TEST CONDITIONS
80 pF Load
100 pF Load
ns
650
ns
80 pF Load
--....,.X:: >Tm~INTS <::X. ___
0.45 - - - - '
-
6·65
AFN-00881A·03
18243
WAVEFORMS
PROG
~-----------------tK----------------~
FLOAT
PORT 2
.~~
PORT 2
DATA
FLOAT
'"'~ ~'"x
VALID
_ t po
OUTPUT
VALID
PREVIOUS OUTPUT VALID
PORTS 4-7
--
tiP
PORTS 4-7
tiP
INPUT VALID
tes
AFN-00861A-()4
18243
125
«E
'"":J 100
e
IN
I-
z
75
w
a:
a:
a
GUARANTEED WORST CASE
CURRENT SINKING
CAPABiliTIES OF ANY 1/0
PORT PIN vs. TOTAL SINK
CURRENT OF All PINS
50
~
z
en
...J
«
l-
25
eIo
o
1
2
3
4
5
6
7
8
9
10
11
12
13
MAXIMUM SINK CURRENT ON ANY PIN@.45V
MAXIMUM IOL WORST CASE PIN (rnA)
Sink Capability
Example: This example shows how the use of the 20
mA sink capability of Port 7 affects the sinking capability of the other 110 lines.
The 8243 can sink 5 mA@.45V on each of its 16110 lines
simultaneously. If, however, all lines are not sinking
simultaneously or all lines are not fully loaded, the drive
capability of any individual line increases as is shown by
the accompanying curve:
An 8243 will drive the following loads simultaneously.
For example, if only 5 of the 16 lines are to sink current
at one time, the curve shows that each of those 51ines is
capable of sinking 9 mA@.45V (if any lines are to sink
9 mA the total IOl must not exceed 45 mA or five 9 mA
loads).
2 loads - 20 mA@1V (port 7 only)
8 loads - 4 mA@.45V
6 loads - 3.2 mA@.45V
Is this within the specified limits?
Example: How many pins can drive 5 TTL loads (1.6 mAl
assuming remaining pins are unloaded?
d Ol =( 2 x 20)+(8 x 4)+(6 x 3.2)=91.2 mAo
From the curve: for IOl = 4 mA, dOL::: 93 mA
since 91.2 mA < 93 mA the loads are within
specified limits.
IOl = 5 x 1.6 mA = 8 mA
dOL = 60 mA from curve
# pins= 60 mA-+- 8 mA/pin = 7.5= 7
Although the 20 mA@ 1V loads are used in
calculating dOL, it is the largest current required@.45V which determines the maximum
allowable dOL.
In this case, 7 lines can sink 8 mA for a total
of 56 mAo This leaves 4 mA sink current capa·
bility which can be divided in any way among
the remaining 8 110 lines of the 8243.
Note: A 10 to 50Kn pullup resistor to +5V should be added to 8243 outputs when driving to 5V CMOS directly.
6-67
AFN-00s81A-05
18243
EXPANDER INTERFACE
":"
cs
I/O
P4
I/O
P5
I/O
P5
I/O
P7
I/O
PROG
8048
TEST
INPUTS
8243
DATA IN
P2
P20·P23
OUTPUT EXPANDER TIMING
PROG
P20·P23
..J/
-----
~""_ _ _ _ _
ADDRESS (4·8ITSI
BITS 1,0
BITS 3,2
OO}
01
10
11_
READ
WRITE
OR
ANO
OO}
01
10
PORT
AODRESS
"
DATA (4-BITSI
BUS
PORT 1
B04B
PORT 2
PROG~----------------~------------------~-----------------4------------------~
USING MULTIPLE 8243'5
6-68
AFN-OOBB1A-OS
8355* /8355-2**
16,384·8IT ROM WITH 110
*Directly Compatible with 8085A CPU
**Directly Compatible with 8085A-2
• Each \/0 Port Line Individually
Programmable as Input or Output
• 2048 Words x 8 Bits
• Single + 5V Power Supply
• Multiplexed Address and Data Bus
• Internal Address Latch
• 2 General Purpose 8·Bit \/0 Ports
• 40·Pin DIP
The Intel® 8355 is a ROM and I/O chip to be used in the MCS-85'· microcomputer system. The ROM portion is organized as
2048 words by 8 bits. It has a maximum access time of 400 ns to permit use with no wait states in the 8085A CPU.
The 1/0 portion consists of 2 general purpose 1/0 ports. Each 1/0 port has 8 port lines, and each 1/0 port line is indivdu
ally programmable as input or output.
The 8355-2 has a 300ns access time for compatibility with the 8085A-2 microprocessor.
PIN CONFIGURATION
BLOCK DIAGRAM
Vee
PB,
elK
PB,
RESET
N.C. (NOT CONNECTED)
PB,
5
READY
PB,
PB,
AD o_ 7
PB,
PB,
RD
lOW
A B- 10
PB.
PA,
PA,
AD.
PAs
AD,
PA,
AD,
PA,
AD,
PA,
AD,
PAD
eE,
CE,
101M
ALE
RD
lOW
RESET
~
~
G
ROM
PAO- 7
PBO- 1
iDA
AD,
Vee (+5VI
AD,
Vss fOV)
VSS
INT£l CORPORATION ASSlHS NO RESPONSIBIlITY FOR THE USE OF ANY CIRCUITRY OTHER THAN CIICUITRY EMBOOIEO IN AN IIITEl PROOOCT. NO OTItER CIRCIIIT PATENT LICENSES ARE IMPLIED.
"INTEL CORPORATION. 1979
6-69
o
8355/8355-2
Symbol
Function
Symbol
Function
ALE
( Inputl
When ALE (Address latch Enable is
high, ADo-7, 101M, AS-1o, CE, and CE
enter address latched. The signals
I AD, 101M, AS-1o, CE, CE I are latched
in at the trailing edge of ALE.
ClK
(lnputl
The
into
has
high
ADo-7
( Inputl
Bidirectional AddresslData bus. The
lower 8-bits of the ROM or 1/0 address
are applied to the bus lines when ALE
is high.
READY
(Outputl
Ready is a 3-state output controlled by
CEL CE2, ALE and ClK. READY is
forced low when the Chip Enables are
active during the time ALE is high, and
remains low until the rising edge of the
next ClK (see Figure 61.
PAO-7
(I nput!
Output I
These are general purpose 1/0 pins.
Their input!output direction is determined by the contents of Data Direction
Register (DDRI. Port A is selected for
write operations when the Chip Enables
are active and iOW is low and a 0 was
previously latched from ADo.
During an 1/0 cycle, Port A or Bare
selected based on the latched value of
ADo. It RD or lOR is low when the latched
chip enables are active, the output
buffers present data on the bus.
AS-1o
Iinputl
These are the high order bits of the ROM
address. They do not affect 1/0 operations.
CE1
CE2
( Inputl
Chip Enable Inputs: CE1 is active low
and CE2 is active~. The 8355 can be
accessed only when BOTH Ghip Enables are active at the time the ALE
signal latches them up. It either Chip
Enab!e input is not active, the ADo-7
and READY outputs will be in a high
impedance state.
10iM
( Inputl
It the latched 10/M is high when RD is
low, the output data comes from an
1/0 port. It it is low the output data
comes from the ROM.
RD
(Inputl
It the latched Chip Enables are active
when RD goes low, the ADo-7 output
buffers are enabled and output either
the selected ROM location or 1/0 port.
When both RD and lOR are high, the
ADo-7 output buffers are 3-state.
lOW
( Input I
ClK is used to force the READY
its high impedance state after it
been forced low by CE low, CE
and ALE high.
Read operation is selected by either
lOR low and active Chip Enables and
ADo low, Q[ 101M high, RD low, active
chip enables, and ADo low.
PBO-7
(Input!
Outputl
This general purpose 1/0 port is
identical to Port A except that it is
selected by a 1 latched from ADo.
RESET
( Input)
An input high on RESET causes all pins
in Port A and B to assume input mode.
lOR
(Input)
When the Chip Enables are active, a low
on lOR will output the selected 1/0 port
onto the AD bus. lOR low performs the
same function as the combination 101M
high and RD low. When lOR is not used
in a system, lOR should be tied to Vee
Vee
+5 volt supply.
Vss
Ground Reference.
("1").
It the latched Chip Enables are active,
a low on lOW causes the output port
pointed to by the latched value of ADo
to be written with the data on ADo-7.
The state of 101M is ignored.
6-70
8355/8355-2
ABSOLUTE MAXIMUM RATINGS*
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional opera·
tion of the device at these or any other conditions above
those indicated in the operational sections of this specifi·
cation is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Temperature Under Bias ...... .
O°Cto +70°C
Storage Temperature
...... -65'Cto+1S0°C
Voltage on Any Pin
With Respect to Ground ... . ....... " -o.sv to +7V
Power Dissipation ............................. 1.SW
D.C. CHARACTERISTICS
(TA = o°c to 70°C; Vee = 5V ± 5%)
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
Vil
Input Low Voltage
-0.5
0.8
V
Vee +O· 5
V
TEST CONDITIONS
III
Input Leakage
10
j.LA
= 5.0V
Vee = 5.0V
IOl = 2mA
IOH = -400j.LA
V IN = Vee to OV
ILO
Output Leakage Current
±10
j.LA
0.45V ';;;;VOUT ';;;;Vee
Icc
Vee Supply Current
180
mA
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
A.C. CHARACTERISTICS
2.0
V
0.45
V
2.4
(TA = o°c to 70°C; Vee = 5V ± 5%)
8~55-2
8355
Symbol
Vee
Parameter
Min.
(Prel mlnary)
Max.
Min.
Max.
Units
teye
Clock Cycle Time
320
320
T1
CLK Pulse Width
80
80
ns
T2
CLK Pulse Width
120
120
ns
tf,t,
CLK Rise and Fall Time
tAL
Address to Latch Set Up Time
30
ns
30
ns
SO
30
ns
ns
tlA
Address Hold Time after Latch
80
30
tle
Latch to READ/WRITE Control
100
40
tAD
Valid Data Out Delay from READ Control
ns
140
170
ns
tAD
Address Stable to Data Out Valid
tLl
Latch Enable Width
tAOF
Data Bus Float after READ
0
tel
READ/WRITE Control to Latch Enable
20
tee
READ/WRITE Control Width
tow
Data In to Write Set Up Time
two
Data In Hold Time After WRITE
twp
WRITE to Port Output
tpA
Port Input Set Up Time
50
50
ns
tRP
Port Input Hold Time
50
50
ns
tRYH
READY HOLD Time
0
tARY
ADDRESS (CE) to READY
tRv
Recovery Time Between Controls
300
200
ns
READ Control to Data Bus Enable
10
10
ns
tROE
Note:
CLOAD =
400
ns
100
330
70
100
a
ns
ns
250
200
ns
150
150
ns
10
10
160
ns
400
0
160
6-71
85
10
400
150pF
ns
ns
160
ns
160
ns
8355/8355-2
O,8V
Figure 1. Clock Specification for 8355
A8-10
IDiM
~
ADDRESS
~
ADDRESS
tAO
·eE,=')
~
)
DATA
~
'll-
~'lA~
II
ALE
I+- 'Al ~
1+ 'RDF •
!--'RDE~
I---'RD-
l----'lC~
'ow
I---'cc
I I+---r--
'RV
'WD ~
I------ 'Cl ~
Figure 2. ROM Read and 110 Read and Write
6-72
8355/8355·2
I. Input Mode
ROOR
iOR
PORT
INPUT
=xtJ~
DATA' BUS
-
-
-
-
-
-
)(
- - - - - - - ------------.
b. Output Mode
'wp
GLITCH FREE
/OUTPUT
PORT
OUTPUT
...I\_______JX_____
DATA'----- ~
BUS
_____
'DATA BUS TIMING IS SHOWN IN FIGURE 4.
Figure 3. 1/0 Port Timing
ClK
ALE
,
....
Figure 4. Wilt Stlta Timing (READY
=0)
6-73
_-----
inter
8755A
16,384-BIT EPROM WITH 1/0
•
Directly Compatible with SOS5A CPU
• 2048 Words )( 8 Bits
• Single
• 2 General Purpose 8·Bit 1/0 Ports
+ 5V Power Supply (Vcd
• Each 1/0 Port Line Individually
Programmable as Input or Output
• U.V. Erasable and Electrically
Reprogrammable
• Multiplexed Address and Data Bus
• Internal Address Latch
• 40·Pin DIP
The Intel@ 8755A is an erasable and electrically reprogram mabie ROM (EPROM I and liD chip to be used in the MCS-85'·
microcomputer system. The EPROM portion is organized as 2048 words l:>y 8 bits. It has a maximum access time of 450 ns
to permit use with no wait states in an 8085A CPU.
The 1/0 portion consists of 2 general purpose 1/0 ports. Each 1/0 port has 8 port lines, and each 1/0 port line is individually programmable as input or output.
PIN CONFIGURATION
BLOCK DIAGRAM
vee
ClK
ClK
RESET
Voo
READY
PB.
A"o_,
READY
101M
i5R
As-lO
PB,
CE,
lOW
PAs
ALE
AD,
PA.
RD
PA,
RESET
lOW
AD,
AD,
2K)( 8
EPROM
101M
ALE
AD,
AD.
PA O- 7
G
~
PBO- 7
iDA
ADs
PA,
AD.
AlO
AD,
A.
PROG/CE,
Voo
~VCCI+5V1
Vss (OV)
Vss
INTEL CORPORATION ASstJMES NO RESPONSIBIlITY FOR THE USE OF ANY CIRCUITRY OTHER THAN CIRCUITRY EMBOOIEO IN AN INTEL PROOUCT. NO OTHER CIftCUIT PRlENT LICENSES ARE IMPLIED.
© INTEl CORPORATION. 1979
6-74
8755A
8755AFUNCTIONAL PIN DEFINITION
Symbol
Function
Symbol
Function
ALE
(input)
When Address latch Enable goes
high, ADo-7, 10/M, AS-1o, CE2, and
CE1 enter the address latches. The
signals (AD, 10/M, AB-10, CEI are
latched in at the trailing edge of ALE.
READY
(output I
ADo-7
(input/output)
Bidirectional Address/Data bus. The
lower 8-bits of the PROM or I/O
address are applied to the bus lines
when ALE is high.
READY is a 3-state output controlled
by CE2, CEl,AlE and ClK. READY
is forced low when the Chip Enables
are active during the time ALE is high,
and remains low until the rising edge
of the next ClK. (See Figure 6. I
PAO-7
(input/output 1
These are general purpose 110 pins.
Their input/output direction is determined by the contents of Data Direction Register (DDR I. PortA is selected
for write operations when the Chip
Enables are active and lOW is low
and a 0 was previously latched from
ADo, AD,.
During an I/O cycle, Port A or Bare
selected based on the latched value of
ADo. If RD or lOR is low when the
latched Chip Enables are active, the
output buffers present data on the
bus.
AS-1o
(input)
These are the high order bits of the
PROM address. They do not affect
I/O operations.
PROG/CE1
CE2
(input)
Chip Enable Inputs: CE 1 is active low
and CE2 is active high. The 8755A
can be accessed only when BOTH
Chip Enables are active at the time
the ALE signal latches them up. If
either Chip Enable input is not active,
the ADo-7 and READY outputs will
be in a high impedance state. CE, is
also used asa programming pin. (See
section on programming. I
10/M
(input)
If the latched 10/M is high when RD
is low, the output data comes from
an I/O port. If it is low the output data
comes from the PROM.
RD
(input)
If the latched Chip Enables are active
when RD goes low, the ADo-7 output
buffers are enabled and output either
the selected PROM location or I/O
port. When both RDand lOR are high,
the ADo-7 output buffers are 3-stated.
lOW
(input)
If the latched Chip Enables are active,
a low on lOW causes the output port
pOinted to by the latched value of
ADo to be written with the data on
ADo-7. The state of 10/M is ignored.
ClK
(input)
The ClK is used to force the READY
into its high impedance state after it
has been forced low by CE, low, CE2
high, and ALE high.
Read operation is selected by either
lOR low and active Chip Enables and
ADo and AD, low, or 10iM high, RD
low, active Chip Enables, and ADo
and AD, low.
PBO-7
(input/output 1
This general purpose I/O port is
identical to Port A except that it is
selected by a 1 latched from ADo and
a 0 from AD1.
RESET
(inputl
In normal operation, an input high on
RESET causes all pins in Ports A and
B to assume input mode (clear DDR
register!.
lOR
(input)
When the Chip Enables are active, a
low on lOR will output the selected
I/O port onto the AD bus. lOR low
performs the same function as the
combination of 10/M high and RD
low. When lOR is not used inasystem,
lOR should be tied to Vce ("1"1.
Vee
+5 volt supply.
Vss
Ground Reference.
Voo
Voo is a programming voltage, and
must be tied to +5V when the 8755A
is being read.
For programming, a high voltage is
supplied with Voo= 25V, typical. (See
section on programming.)
6-75
8755A
ERASURE CHARACTERISTICS
SYSTEM APPLICATIONS
System Interface with SOSSA
The erasure characteristics of the 8755A are such that
erasure begins to occur when exposed to light with
wavelengths shorter than approximately 4000 Angstroms
(AI. It should be noted that sunlight and certain types of
fluorescent lamps have wavelengths in the 3000-4000A
range. Data show that constant exposure to room level
fluorescent lighting could erase the typical 8755A in
approximately 3 years while it would take approxill1ately 1
week to cause erasure when exposed to direct sunlight.
If the 8755A is to be exposed to these types of lighting
conditions for extended periods of time, opaque labels
are available from Intel which should be placed over the
8755 window to prevent unintentional erasure.
A system using the 8755A can use either one of the two I/O
Interface techniques:
• Standard I/O
• Memory Mapped I/O
If a standard I/O technique is used, the system can use the
feature of both GE2 and CE1. By using a combination of
unused address lines A11-15 and the Chip Enable inputs, the
8085A system can use up to 5 each 8755A's without requiring
a CE decoder.
If a memory mapped I/O approach is used the 8755A will be
selected by the combination of both the Chip Enables and
10/M using the AD8-15 address lines. See Figure 1.
The recommended erasure procedure for the 8755A is
exposure to shortwave ultraviolet light which has a wavelength of 2537 Angstroms (AI. The integrated dose Ii.e.,
UV intensity X exposure time) for erasure should be a
minimum of 15W-sec/cm2. The erasure time with this
dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000",W/cm2 power rating. The
8755A should be placed within one inch from the lamp
tubes during erasure. Some lamps have a filter on their
tubes and this filter should be removed before erasure.
PROGRAMMING
Initially, and after each erasure, all bits of the EPROM
portions of the 8755A are in the "1" state. Information is
introduced by selectively programming "0" into the
desired bit locations. A programmed "0" can only be
changed to a "1" by UV erasure.
The 8755A can be programmed on the Intel® Universal
PROM Programmer (UPPI, and the PROMPT'" 80/85 and
PROMPT-48'" design aids. The appropriate programming
modules and adapters for use in programming both
8755A's and 8755's are shown in Table 1.
BOB5A
1,
2.
3.
4.
UPPI41
UPP 855
PROMPT 80/85131
PROMPT 48( 11
V
;---
WR
elK 102)
REAOY
101M
Vee
r-r-r-;---
rV '\.. 7
AID,.,
iifR
A'_10
*1
I
RD elK
101M
ALE ilii'i READY CE
B755A
TABLE 1. 875SA PROGRAMMING MODULE CROSS
REFERENCE
UPP 955
UPP UP2121
PROMPT 975
PROMPT 475
o.7
RO
Preliminary timing diagrams and parameter values per·
taining to the 8755A programming operation are con·
tained in Figure 6.
USE WITH
~
MO
"ALE
The program mode itself consists of programming a
single address at a time, giving a Single 50 msec pulse
for every address. Generally, it is desirable to have a
verify cycle after a program cycle for the same address
as shown in the attached timing diagram. In the verify
cycle (i.e., normal memory read cycle I 'Voo' should
be at +5V.
MODULE NAME
"
/1
1~8-15
'NOTE: Optional connection.
NOTES:
Described on p. 11·9 of 1978 System Data Catalog.
Special adaptor socket.
Described on p. 11·3 of 1978 System Data Catalog.
Described on p. 10·85 of 1978 System Data Catalog.
Figure 1. 8755A in 808SA System (Memory-Mapped 1/0)
6-76
8755A
ABSOLUTE MAXIMUM RATINGS·
TemperatureUnderBias .............. -10 o e to +70 o e
Storage Temperature ............... -65°eto +150 o e
Voltage on Any Pin
With Respect to Ground ............... -0.5 to +7V·
Power Dissipation ............................. 1.5W
'COMMENT
Stresses above those listed under "Absolute Maximum Ratings" maycause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those
Indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
·Except for programming voltage.
D.C. CHARACTERISTICS
(TA = o°c to 70°C; VCC = 5V ± 5%)
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
VIL
Input Low Voltage
VIH
Input High Voltage
-0.5
0.8
V
2.0
Veet-
1/
ALE
(PROG)/CE 1
ADDRESS
\.
~
-
t--tRDE
\
tROF
I---
J
I---tLC~
tow
I - - - tRO
1"-
I--- f-two
ILtce
I---tCL-
Please note that CE1 must remain low tor the entire eyele.
tRV
Figure 3. PROM Read, 1/0 Read and Write Timing
6-78
8755A
A. INPUT MODE
ROOR
lOR
PORT
INPUT
'PR
~
DATA> BUS
'+-rF---~!
=x__________
c-
-
-
-
-
-
-
~x~
____
)(
-------
----------------------
B. OUTPUT MODE
lOW
\
-J.
_ _ _ _ _ _ _ _ _ _ ' : : ~_
PORT
OUTPUT
x
.;
~
\.
------------
/
GLITCH FREE
OUTPUT
-----
_
X. ._____
DATA> """\/
BUS
_____
-A________
'",,,,,,m "'~,
Note also that the output latch is cleared when the port
enters the input mode. The output latch cannot be loaded
by writing to the port if the port is in the input mode. The
result is that each time a port mode is changed from input
to output, the output pins will go low. When the 8155/56
is RESET, the output latches are all cleared and al13 ports
enter the input mode.
I
PORT C
A srB (ACKNOWL DATA RECEIVED)
B SF (SIGNALS BUFFER IS FULL)
B INTR (SIGNALS BUFFER
READY FOR READINGI
PORT B
When in the AL T 1 or AL T 2 modes, the bits of PORT C
are structured like the diagram above in the simple input
or output mode, respectively.
TO/FROM
B STS (LOADS PORT B LATCH)
INPUT
1
}
PERIPHERAL
INTERFACE
r
TO 8085 INPUT PORT (OPTIONAL)
TO 8085 RST INPUT
Reading from an input port with nothing connected to the
pins will provide unpredictable results.
Figure 7 shows how the 8155/8156 1/0 ports might be
configured in a typical MCS-85 system.
Figure 7. Example: Command Register
6-87
= 00111001
8155/8156/8155-2/8156-2
TIMER SECTION
The timer is a 14-bit down-counter that counts the TIMER
IN pulses and provides either a square wave or pulse
when terminal count (TC) is reached.
Note that while the counter is counting, you may load a
new count and mode into the count length registers.
Before the new count and mode will be used by the
counter, you must issue a START command to the
counter. This applies even though you may only want to
change the cOllnt and use the previous mode.
The timer has the I/O address XXXXX100forthe low order
byte of the register and the I/O address XXXXX101 for
the high order byte of the register. (See Figure 5).
To program the timer, the COUNT LENGTH REG is
loaded first, one byte at a time, by selecting the timer
addresses. Bits 0-13 of the high order count register will
specify the length of the next count and bits 14-15 of the
high order register will specify the timer output mode
(see Figure 8). The value loaded into the count length
register can have any value from 2H through 3FFH in
Bits 0-13.
I
I
6
M21
Ml
I
I
4
5
3
T131 T121 Tll
II
0
2
I I
Tl0
In case of an odd-numbered count, the first half-cycle
of the squarewave output, which is high, is one count
longer than the second (low) half-cycle, as shown in
Figure 10.
T91
Tal
I
I
MSB OF CNT LENGTH
TIMER MODE
65432
o
NOTE; 5 AND 4 REFER TO THE NUMBER OF CLOCKS IN THAT TIME PERIOD
Figure 10; Asymmetrical Square-Wave Output Resulting
from Count of 9
I
LSB OF CNT LENGTH
The counter in the 8155 is not initialized to any particular
mode or count when hardware RESET occurs, but RESET
does stop the counting. Therefore, counting cannot begin
following RESET until a START command is issued via
the CIS register.
Figure 8. Timer Format
There are four modes to choose from: M2 and M1 define
the timer mode, as shown in Figure 9.
TIMER OUT WAVEFORMS:
START
COUNT
MOOE
BITS
M2
M1
o
0
TERMINAL
COUNT
~
Please note that tlie timer circuit on the 8155/8156 chip
is designed to be a square-wave timer, not an event
counter. To achieve this, it counts down by twos twice
in completing one cycle. Thus, its registers do not contain values directly representing the number of TIMER IN
pulses received. You cannot load an initial value of 1 into
the count register and cause the timer to operate, as its
terminal count value is 10 (binary) or 2 (decimal). (For
the detection of single pulses, it is suggested that one
of the hardware interrupt pins on the 8085A be used.)
After the timer has started counting down, the values
residing in the count registers can be used to calculate
the actual number of TIMER IN pulses required to complete the timer cycle if desired. To obtain the remaining
count, perform the following operations in order:
(TERMINAL)
COUNT
_____ 1____ _
1. SINGLE
SQUARE WAVE
2. CONTINUOUS
SQUARE WAVE
3. SINGLE
---~---------PULSE ON
TERMINAL COUNT
4. CONTINUOUS
PULSES
-------ur------~
Figure 9. Timer Modes
Bits 6-7 (TM2 and TM1) of command register contents
are used to start and stop the counter. There are four
commands to choose from:
TM2
o
o
1. Stop the count
2. Read in the 16-bit value from the count length registers
TMl
0
o
NOP - Do not affect counter operation.
3. Reset the upper two mode bits
STOP - NOP if timer has not started;
stop counting if the timer is running.
4. Reset the carry and rotate right one position all 16 bits
through carry
STOP AFTER TC - Stop immediately
after present TC is reached (NOP if timer
has not started)
5. If carry is set, add 1/2 of the full original count (112 full
count - 1 if full count is odd).
START - Load mode and CNT length
and start immediately after loading (if
timer is not presently running). If timer
is running, start the new mode and CNT
length immediately after present TC is
reached.
Note: If you started with an odd count and you read the
count length register before the third count pulse occurs,
you will not be able to discern whether one or two counts
has occurred. Regardless of this, the 8155/56 always
counts out the right number of pulses in generating the
TIMER OUT waveforms.
6-88
8155/8156/8155-2/8156-2
EXAMPLE PROGRAM
Following is an actual sequence of program steps that adjusts the 8155/56 count register
contents to obtain the count, extracted from Intel@ Application Note AP38. "Application
Techniques for the Intel8085A Bus." First store the value of the full original count in register
HL of the 8085A. Then stop the count to avoid getting an incorrect count value. Then sample
the timer-counter, storing the lower-order byte of the current count register in register C and
the higher-order count byte in register B. Then, call the following 8080A/8085A subroutine:
ADJUST,78
MOV A,B
;Load accumulator with upper half
; of count.
E63F
ANI3F
;Reset upper 2 bits and clear carry.
1F
RAR
;Rotate right through carry.
47
MOV B,A
;Store shifted value back in B.
79
MOV A,C
;Load accumulator with lower half.
1F
RAR
;Rotate right through carry.
4F
MOV C,A
;Store lower byte in C.
00
RNC
;If in 2nd half of count, return.
;If in 1st lialf, go on.
3F
CMC
;Clear carry.
7C
MOV A,H
;Divide full count by 2. (If HL
;is odd, disregard remainder.)
1F
RAR
67
MOV H,A
70
MOV A,L
1F
RAR
6F
MOV L,A
09
DAD B
;Double-precision add HL and BC.
44
MOV B,H
;Store results back in BC.
40
MOV C,L
C9
RET
;Return.
After executing the subroutine, BC will contain the remaining count in the current count cycle.
6-89
8155/'156/8155-2/8156-2
8085A MINIMUM
SYSTEM CONFIGURATION
Figure 11 shows a minimum system using three chips,
containing:
• 256 Bytes RAM'
• 2K Bytes ROM
• 381/0 Pins
• 1 Interval Timer
• 4 Interrupt Levels
"
A8-1S
"ADO-7
RD
-
WR
ClK
RESET DUTt
READY
,
,,
,,I TIMER
RESET
I
WR AD
IN
G
8156
VCC
-
101M
T~~~R_
v
---.!. ;..
ALE
B085A
ALE
7
CE"
101M
~
'-l
'--'--
LATCHES
"
-
7~~
_101
CE M ALE
256 x 8
RAM
l
I
I
8355 J ROM ... I/O I
OR
8755 I PROM + lID I
~~cp$
- NOTE, OPTIONAL CONNECTIONS
B. BB
Figure 11. 808SA Minimum System Conllguratlon. (Memory Mapped 1/0)
6-90
1,,
iIDiOvi elK RS~RDY
I
~
CONTROL
7:~~<;
vv~
BB
-
Vee
8155/8156/8155·2/8156·2
ABSOLUTE MAXIMUM RATINGS·
,'COMMENT: Stresses above those'listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional opera·
tion of the device at these or any other conditions above
those indicated in the operationfjl sections of thisspecifi·
cation is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Temperature Under Bias ................ O°C to +70°C
Storage Temperature ...... : ........ -65°Cto+150°C
Voltage on Any Pin
With Respect to Ground ............... -O.5V to +7V
Power Dissipation ............................. 1.5W
D.C. CHARACTERISTICS
(TA
= o°c to 70°C; Vee = 5V ± 5%)
MAX.
UNITS
-0.5
0.8
V
2.0
Veet{)·5
V
TEST CONDITIONS
PARAMETER
MIN.
VIL
Input Low Voltage
VIH
Input High Voltage
VoL
Output Low Voltage
VoH
Output High Voltage
IlL
Input Leakage
±10
IlA
VIN = Vee to OV
ILO
Output Leakage Current
±10
IlA
0.45V .;;; VOUT .;;; Vee
Icc
Vee Supply Current
180
mA
IldCE)
Chip Enable Leakage
8155
8156
+100
-100
p.A
p.A
SYMBOL
0.45
2.4
6-91
V
IoL = 2mA
V
IOH = -4001lA
VIN = Vee to OV
8155/8156/8155~218156-2
A.C. CHARACTERISTICS
ITA
=o°c to 70°C; VCC = 5V ± 5%)
8155/8156
SYMBOL
PARAMETER
tAL
Address to Latch Set Up Time
tLA
Address Hold Time after Latch
tlC
Latch to R EAD/WR ITE Control
MIN.
'.'
MAX.
50
8155·2/8156-2
(Preliminary)
MIN.
MAX.
30
UNITS
ns
80
30
ns
100
40
ns'
tRO
Valid Data Out Delay from READ Control
170
140
tAO
Address Stable to Data Out Valid
400
330
tll
Latch Enable Width
tROF
Data Bus Float After READ
0
tCl
READ/WRITE Control to Latch Enable
20
10
ns
tcc
READ/WRITE Control Width
250
200
ns
tow
Data In to WR ITE Set Up Time
150
100
ns
two
Data In Hold Time After WR ITE
0
0
ns
tRV
Recovery Time Between Controls
300
twp
WR ITE to Port Output
tPR
Port Input Setup Time
70
50
ns
tRP
Port Input Hold Time
50
10
ns
tSBF
Strobe to Buffer Full
tss
strobe Width
tRBE
READ to Buffer Empty
400
300
ns
tSI
Strobe to INTR On
400
300
ns
tROI
READ to INTR Off
400
300
ns
tPSS
Port Setup Time to Strobe Strobe
50
0
ns
tPHS
Port Hold Time After Strobe
120
100
ns
tSBE
Strobe to Buffer Empty
400
300
ns
tWBF
WR ITE to Buffer Full
400
300
ns
tWI
WR ITE to INTR Off
400
300
ns
tTL
TIMER·IN to TIMER·OUT Low
400
300
ns
tTH
TIMER·IN to TIMER·OUT High
400
300
ns
tROE
Data Bus Enable from READ Control
10
10
ns
tl
TIMER·IN Low Time
80
40
ns
t2
TIMER·IN High Time
120
70
ns
100
0
ns
ns
300
400
200
6·92
80
200
400
ns
ns
70
100
ns
300
ns
ns
ns
150
8155/8156/8155-2/8156-2
WAVEFORMS
a. Read Cycle
CE
\-
(8155 I
\
OR
\
101M
~
AL E
-'
I
CE 18156I
.
'\
/
/
\
tA:D
~
ADDRESS
-+-- t
AL
If-
______
~
DATA VALID
- - - t LA - - - - -
(
l\
f----tLL~
I--
I... t RDE ..
~I'-l
~tRD_
tRDF -
I\-
V
- - - - tLc -
t eL -------
-
!----------
tee
~
---------- tRY ~
b. Write Cycle
CE
\
18155 I
\
OR
CE 18156I
IO/i>n
I
-'[\
/
\
,V
~
~
ADO_7
ADDRESS
l
--
)
-"K
DATA VALID
-tow---------+-
I---tLA -
I - - - t AL - -
ALE
K
-tel-
1\
V
\-
t lL -
- - - - t Le
---:1
-
two ------.
-,1
I~
Figure 12. 8155/8156 Read/Write Timing Diagrams
6-93
tcc~
- - - - - - - - - tRY
-----------
"--
8155/8156/8155-2/8156-2
a. Strobed Input Mode
\
/
BF
tSBF
~r-../
~~~
I - t 5S -
t RBE -
7\
INTR
\.
\
......--tpss
INPUT DATA
FROM PORT
t pHS
~
\"7 /
-----/
L
~
b. Strobed Output Mode
J
BF
\ ~~-)' I_~
tWBF
INTR
'WI
\
)
J
j
/
/
I------- t--twp
OUTPUT DATA
TO PORT
~
Figure 13. Strobed 1/0 Timing
6-94
/
8155/8156/8155-2/8156-2
a. Basic Input Mode
DATA BUS'
~
===::::J
____________
b. Basic Output Mode
DATA BUS·
OUTPUT
·DATA BUS TIMING IS SHOWN IN FIGURE 7.
Figure 14. Basic 1/0 Timing Waveform
LOAD COUNTER FROM CLR
I
2
I
1
--I
I
RELOAD COUNTER FROM CLR
I
TIMER IN
TIMER OUT
(PULSE)
~
\
TIMER OUT
(SQUARE WAVE)
\\
(NOTE 1(
(NOTE
1)
___
J"
'--------_..1
II
NOTE 1: THE TIMER OUTPUT IS PERIODIC IF IN AN AUTOMATIC
RELOAD MODE ,!M1 MODE BIT'" ')
Figure 15. Timer Output Waveform Countdown from 5 to 1
6·95
2
I
1
-I
inter
8185/8185-2
1024 x 8-BIT STATIC RAM FOR MCS_85™
• Multiplexed Address and Data Bus
• Low Standby Power Dissipation
• Directly Compatible with 8085A
and 8088 Microprocessors
• Single +5V Supply
• Low Operating Power Dissipation
• High Density 18-Pin Package
The Intel'" 8185 is an 8192-bit static random access memory (RAM) organized as 1024 words by 8-bits using
N-channel Silicon-Gate MOS technology. The multiplexed address and data bus allows the 8185 to interface directly
to the 8085A and 8088 microprocessors to provide a maximum level of system integration.
The low standby power dissipation minimizes system power requirements when the 8185 is disabled.
The 8185·2 is a high-speed selected version of the 8185 that is compatible with the 5 MHz 8085A-2 and the full speed
5 MHz 8088.
BLOCK DIAGRAM
PIN CONFIGURATION
ADo
Vee
AD,
RD
AD,
WR
AD,
ALE
AD,
CS
AD5
CE,
AD,
CE,
AD,
A,
Vss
As
cs
CE,
CE,
.
R!W
LOGIC
RO
WALE
I
~
---v
DATA
BUS
BUFFER
1K x 8
RAM
MEM0RY
ARRAY
X-V DECODE
PIN NAMES
AD O·AD 7
As. A9
CS
ADDRESS/DATA LINES
ADDRESS LINES
CHIP SELECT
CE,
CHIP ENABLE (101M)
CE,
ALE
CHIP ENABLE
WJj
WRITE ENABLE
RO
~
Aa. Ag
ALE
v:'
ADDRESS
LATCH
U
;:..
ADDRESS LATCH ENABLE
READ ENABLE
6-96
AFN-Q0201A-01
8185/8185-2
OPERATIONAL DESCRIPTION
The 8185 has been designed to provide for direct interface
to the multiplexed bus structure and bus timing of the
8085A microprocessor.
--
At the beginning of an 8185 memory access cycle, the 8bit address on ADo-7, As and Ag, and the status of CEI and
CE2 are all latched internally in the 8185 by the falling edge
of ALE. If the latched status of both CEI and CE2 are
active, the 8185 powers itself up, but no action occurs until
the CS line goes low and the appropriate RD or WR control
signal input is activated.
--
Vss Vee
r1D~
TRAP
X,
III
X,
RESET IN
HOLD
RST7,5
HLDA
AST6,S
SOD
8085A
RST5,5
SID
INTR
1NTA
ADDR
9,
ADDRi
DATA ALE Ali
,81
WIi
--'--
r--
RESET
90 OUT
101M
ROY eLK
~ POR~~
H-
The CS input is not latched by the 8185 in order to allow
the maximum amount of time for address decoding in
selecting the 8185 chip. Maximum power consumption
savings will occur, however, only when CEI and CE2 are
activated selectively to power down the 8185 when it is not
in use. A possible connection would be to wirethe 8085A's
101M line to the 8185's CEI input, thereby keeping the
8185 powered down during 1/0 and interrupt cycles.
WR
_
PORT
R0 8156 B
CE 2
CS
{CS*)[2]
1
X
X
0
X
0
X
0
ALE
'ORTP(>
DATAl
c
(6)
"
101M
IN
TIMER
RESET
OUT
Ali
ALE
Il-r-
~~
Power Down and
Function Disablell]
PORT
CE
"-
A
8355/
8755A
V
DATAl
ADDR
101M
PORT
8
RESET
1
0
Powered Up and
Function Disable[l]
0
1
0
1
Powered Up and
Enabled
~
eLK
vs! v!c V~D
RO
CE, 8185
ALE
H--
es,
H--
As, Ag
X
X Hi-Impedance
1
0
1
Data from Memory Read
1
1
0
Data to Memory
Write
1
1
1
Hi-Impedance
Reading, but not
Driving Data Bus
CE 2
ADQ.7
vL vL
Vee
ADo_7 During Data
WR Portion of Cycle
8185 Function
0
tROG
WR
TABLE 2.
TRUTH TABLE FOR
CONTROL AND DATA BUS PIN STATUS
RD
p(>
ROV
Notes:
X: Don't Care.
1: Function Disable implies Data Bus in high impedance state
and not writing.
2: CS' = (CEI = 0) • (CE2 = 1) • (CS = 0)
CS· = 1 signifies all chip enables and chip select active
(CS*)
p(>
A s.10
Power Down and
Function Disable[l]
1
~
lOW
8185 Status
0
~
(8)
ADDR
TABLE 1.
TRUTH TABLE FOR
POWER DOWN AND FUNCTION ENABLE
CE1
T
VI'
,81
Vee
No Function
Figure 1. 8185 in an MCS-85 System.
4 Chips:
2K Bytes ROM
1 .25K Bytes RAM
38 I/O Lines
1 Counter/Timer
2 Serial I/O Lines
5 Interrupt Inputs
Note:
X: Don't Care.
6-97
AFN-00201 A-02
818~~8185-2
ABSOLUTE MAXIMUM RATINGS*
'COMMENT
Temperature Under Bias .............. o·c to +70·C
Storage Temperature .........•.... -65·C to +150·C
Voltage on Any Pin.
.
.
with Respect to Ground .......•...... -o.5V to +7V
Power Dissipation .............. . . . . .. .. . . . . . .. 1.5W
D.C. CHARACTERISTICS
(TA =
Stresses above thos'e listed under"Absolute Maximum-Ratings" may cause
p~rmanent damage to the device. This is a s~ress rating only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of thts specification is not implied.
Exposure to absolute maximum rating conditions for extended periods
may, affect device reliability.
o·c to 70·C; Vee = 5V± 5%)
Min.
Max.
Units
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
Vcc+0.5
V
VOL
Output Low Voltage
0.45
V
VOH
Output High Voltage
hL
Input Leakage
±10
,uA
VIN = Vee to OV
ILO
Output Leakage Current
±10
,uA
0.45V ::; VOUT ::; Vce
lec
Vce Supply Current
Powered Up
Powered Down
100
35
mA
mA
Symbol
VIL
Parameter
A.C. CHARACTERISTICS
IOL =2mA
2.4
(TA =
IOH = - 400,uA
o·c t070·C; Vee = 5V ± 5%)
Parameter [11
Symbol
Test Conditions
8185
8185-2
Preliminary
Preliminary
Min.
Max.
Min.
Max.
Units
tAL
Address to Latch Set Up Time
50
30
ns
tLA
Address Hold Time After Latch
80
30
ns
tLC
Latch to READ/WRITE Control
100
40
tRO
Valid Data Out Delay from READ Control
170
140
ns
tLO
ALE to Data Out Valid
~OO
200
ns
tLL
Latch Enable Width
tROF
Data Bus Float
tCL
READ/WRITE Contrpl to Latch Enable
20
10
ns
tcc
READ/WRITE Control Width.
250
200
ns
tow
Data In to WRITE Set Up Time
150
150
ns
two
Data In Hold Time After WRITE
20
20
ns
tse
Chip Select Set Up to Control Line
10
10
ns
tes
Chip Select Hold Time After Control
10
.10
ns
tALCE
Chip Enable Set Up to ALE Falling
30
10
ns
tLACE
Chip Enable Hold Time After ALE
50
30
ns
Afte~
70
100
READ
0
ns
100
"
0
ns
80
ns
Notes:
1. All AC parameters are referenceq at
a) 2.4V and .45V for inputs .
b) 2.0V and .8V for outputs.
Input Waveform for A.C. Tests:
6-98
AFN-00201 A.()3
8185/8185-2
ALE
tEE, =0)(CE2'" 1)
WR,Ro
ADO·AD7
(Aa, Ag)
(READ CYCLE)
(WRITE CYCLE)
(DESELECTED)
(SELECTED)
Figure 3.8185 Timing.
6-99
AFN'00201A-tl4
8031/8051/8751
SINGLE-COMPONENT 8-BIT MICROCOMPUTER
• S031 - Control Oriented CPU With RAM and I/O
• S051 - An S031 With Factory Mask-Programmable ROM
• S751 - An S031 With User Programmable/Erasable EPROM
•
•
•
•
•
4K x S ROM/EPROM
128 x S RAM
Four S-Bit Ports, 32 I/O Lines
Two 16-Bit Timer/Event Counters
High-Performance Full-Duplex
Serial Channel
• External Memory Expandable to 12SK
• Compatible with MCS-SOTM /MCS-S5™
Peripherals
• Boolean Processor
• MCS-4STM Architecture Enhanced with:
• Non-Paged Jumps
• Direct Addressing
• Four S-Register Banks
• Stack Depth Up to 12S-Bytes
• Multiply, Divide, Subtract, Compare
• Most Instructions Execute in 1ps
• 4ps Multiply and Divide
The Intel® 8031/8051/8751 is a stand-alone, high-performance single-chip computer fabricated with Intel's
highly-reliable +5 Volt, depletion-load, N-Channel, silicon-gate HMOS technology and packaged in a 40-pin
DIP. It provides the hardware features, architectural enhancements and new instructions that are necessary to
make it a powerful and cost effective controller for applications requiring up to 64K bytes of program memory
and/or up to 64K bytes of data storage.
The 8051/8751 contains a non-volatile 4K x 8 read only program memory; a volatile 128 x 8 read/write data
memory; 32 I/O lines; two 16-bit timer/counters; a five-source, two-priority-Ievel, nested interrupt structure; a
serial I/O port for either multi-processor communications, I/O expansion, or full duplex UART; and on-chip
oscillator and clock circuits. The 8031 is identical, except that it lacks the program memory. For systems that
require extra capability, the 8051 can be expanded using standard TTL compatible memories and the byte
oriented MCS-80 and MCS-85 peripherals.
The 8051 microcomputer, like its 8048 predecessor, is efficient both as a controller and as an arithmetic
processor. The 8051 has extensive facilities for binary and BCD arithmetic and excels in bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41%
two-byte, and 15% three-byte instructions. With a 12 MHz crystal, 58% of the instructions execute in 1,us, 40%
in 2,us and multiply and divide require only 4,us. Among the many instructions added to the standard 8048
instruction set are multiply, divide, subtract and compare.
FREQUENCY
REFERENCE
-1
1
L-""..-....J
1
1
1
TXD4RXO __
~-+(
INT1 ....
TO . . . .
Tl ......
1
I
r---""'----,
1
...........-...,.-11
...
~
L
:!i
A-
m .....
CONTROL
Rb ......
Figure 1. Pin
Configuration
1
1
PARALLEL PORTS,
ADDRESS/DATA 8US,
SERIAL
IN
SERIAL
OUT
AND 110 PINS
Figure 3. Block Diagram
Figure 2. Logic Symbol
AFN-01462A-01
7-1
inter
1.0
8031/8051/8751
INTRODUCTION
modified and updated in the field.
This data sheet provides an introduction to the 8051
family. A detailed description of the hardware required to expand the 8051 with more program memory, data memory, I/O, specialized peripherals and
into multiprocessor configurations is described in
the 8051 Family User's Manual.
2.0 MACRO-VIEW OF THE 8051
ARCHITECTURE
On a single die the 8051 microcomputer combines
CPU; non-volatile 4K x 8 read-only program me·mory;
volatile 128 x 8 read/write data memory; 321/0 lines;
two 16-bit timer/event counters; a five-source, twopriority-level, nested interrupt structure; serial I/O
port for either multi-processor communciations, I/O
expansion, or full duplex UART; and on-Chip oscillator and clock circuits. This section will provide an
overview of the 8051 by providing a high-level description of its major elements: the CPU architecture
and the on-chip functions peripheral to the CPU.
The generic term ".8051" is used to refer collectively
to the 8031,8051, and 8751.
1.1 THE 8051 FAMILY
The 8051 is a stand-alone high-performance singlechip computer intended for use in sophisticated
real-time applications such as instrumentation,
industrial control and intelligent computer peripherals. It provides the hardware features, architectural
enhancements and new instructions that make it a
powerful and cost effective controller for applications
requiring up to 64K-bytes of program memory and/or
up to 64K-bytes of data storage. A Block Diagram is
shown in Figure 3.
The 8031 is a control-oriented CPU without on-chip
program memory. It can address 64K-bytes of
external Program Memory in addition to 64K-bytes
of External Data Memory. For systems requiring extra
capability, each member of the 8051 family can be
expanded using standard memories and the byte
oriented MCS-80 and MCS-85 peripherals. The 8051
is an 8031 with the lower 4K-bytes of Program
Memory filled with on-chip mask programmable
ROM while the 8751 has 4K-bytes of UV-lighterasable/electrically-program mabie ROM.
The three pin-compatible versions of this component reduce development problems to a minimum
and provide maximum flexibility. The 8751 is well
suited for development, prototyping, low-volume
production and applications requiring field updates;
the 8051 for low-cost, high volume production; and
the 8031 for applications desiring the flexibility of
external Program Memory which can be easily
!
2.1 8051 CPU ARCHITECTURE
The 8051 CPU manipulates operands in four memory
spaces. These are the 64K-byte Program Memory,
64K-byte External Data Memory, 384-byte Internal
Data Memory and 16-bit Program Counter spaces.
The Internal Data Memory address space is further
divided into the 256-byte Internal Data RAM and
128-byte Special Function Register (SFR) address
spaces shown in Figure 2.1. Four Register Banks
(each with eight registers), 128 addressable bits,
and the stack reside in the Internal Data RAM. The
stack depth is limited only by the available Internal
Data RAM and its location is determined by the 8-bit
stack pointer. All registers except the Program
Counter and the four 8-Register Banks reside in the
Special Function Register address space. These
memory mapped registers include arithmetic registers, pointers, I/O ports, interrupt system registers,
timers and serial port. 128 bit locations in the SFR
address space are addressable as bits. The 8051 contains 128 bytes of Internal Data RAM and 20 SFRs.
64K
64K
EXTERNAL
OVERLAPPED SPACE
I
4095
-------
~r-----A
I
I
I
255 I
INTERNAL
I I
I
PROGRAM
COUNTER
12:
0
255
128
~
'----...------'
PROGRAM
MEMORY
INTERNAL
DATA RAM
Il
'----...------'
SPECIAL
FUNCTION
REGISTERS
,
,
EXTERNAL
DATA
MEMORY
INTERNAL DATA MEMORY
Figure 2.1. 8051 Family Memory Organization
AFN-01462A-Q2
inter
8031/8051/8751
2.2 ON-CHIP PERIPHERAL FUNCTIONS
The 8051 provides a non-paged Program Memory
address space to accommodate relocatable code.
Conditional branches are performed relative to the
Program Counter. The register-indirect jump permits
branching relative to a 16-bit base register with an
offset provided by an 8-bit index register. Sixteen-bit
jumps and calls permit branching to any location
in the contiguous 64K Program Memory address
space.
The 8051 has five methods for addressing source
operands: Register, Direct, Register-Indirect, Immediate and Base-Register- plus Index-RegisterIndirect Addressing. The first three methods can be
used for addressing destination operands. Most
instructions have a "destination, source" field that
specifies the data type, addressing methods and
operands involved. For operations other than
moves, the destination operand is also a source
operand.
Registers in the four 8-Register Banks can be
accessed through Register, Direct, or RegisterIndirect Addressing; the 128 bytes of Internal Data
RAM through Direct or Register-Indirect Addressing;
and the Special Function Registers through Direct
Addressing. External Data Memory is accessed
through Register-Indirect Addressing. Look-UpTables resident in Program Memory can be accessed
through Base-Register- plus Index-Register- Indirect
Addressing.
The 8051 is classified as an 8-bit machine since the
internal ROM, RAM, Special Function Registers,
Arithmetic/Logic Unit and external data bus are each
8-bits wide. The 8051 performs operations on bit,
nibble, byte and double-byte data types.
The 8051 has extensive facilities for byte transfer,
logic, and integer arithmetic operations. It excels at
bit handling since data transfer, logic and conditional branch operations can be performed directly
on Boolean variables.
The 8051's instruction set is an enhancement of
the instruction set familiar to MCS-48 users. It is
enhanced to allow expansion of on-Chip CPU
peripherals and to optimize byte efficiency and
execution speed. Op codes were reassigned to add
new high-power operations and to permit new
addressing modes which make the old operations
more orthogonal. Efficient use of program memory
results from an instruction set consisting of 49
single-byte, 45 tWO-byte and 17 three-byte instructions. When using a 12 MHz oscillator, 64 instructions
execute in 1/.1s and 45 instructions execute in '2/.Js.
The remainin,g instructions (multiply and divide)
require only 4/.1s. The number of bytes in each instruction and the number of oscillator periods required
for execution are listed in the appended 8051 Instruction Set Summary.
Thus far only the CPU and memory spaces of the
8051 have been described. In addition to the CPU
and memories, an interrupt system, extensive I/O
facilities, and several peripheral functions are integrated on-Chip to relieve the CPU of repetitious,
complicated or time-critical tasks and to permit
stringent real-time control of external system interfaces. The extensive I/O facilities include the I/O
pins, parallel I/O ports, bidirectional address/data
bus and the serial port for I/O expansion. The CPU
peripheral functions integrated on-chip are the two
16-bit counters and the serial port. All of these work
together to greatly boost system performance.
2.2.1
Interrupt System
External events and the real-time-driven on-phip
peripherals require service by the CPU asynchronous
to the execution of any particular section of code.
To tie the asynchronous activities of these functions
to normal program execution, a sophisticated multiple-source, two-priority~level, nested interrupt system is provided. Interrupt response latency ranges
from 3ps to 711S when using a 12 MHz crystal.
The 8051 acknowledges interrupt requests from
five sources: Two from external sources via the INTO
and iN'R pins, one from each of the two internal
counters and one from the serial I/O port. Each
interrupt vectors to a separate location in Program
Memory for its service program. Each of the five
sources can be assigned to either of two priority
levels and can be independently enabled and disabled. Additionally all enabled sources can be globally
disabled or enabled. Each external interrupt is programmable as either level- or transition-activated
and is active-low to allow the "wire or-ing" of several
interrupt sources to the input pin. The interrupt
system is shown diagrammatically in Figure 2.2
2.2.2
1/0 Facilities
The 8051 has instructions that treat its 32 I/O lines
as 32 individually addressable bits and as four
parallel 8-bit ports addressable as Ports 0,1,2 and 3.
Ports 0, 2 and 3 can also assume other functions.
Port 0 provides the multiplexed low-order address
ahd data bus used for expanding the 8051 with
standard memories and peripherals. Port 2 provides
the high-order address bus when expanding the
8051 with external Program Memory or more than
256 bytes of External Data Memory. The pins of
Port 3 can be configured individually to provide external interrupt request inputs, counter inputs, the
serial port's receiver input and transmitter output,
and to generate the control signals used for reading
and writing External Data Memory. The generation
or use of an alternate function on a Port 3 pin is
done automatically by the 8051 as long as the pin
AFN-ol482A-03
7-3
8031/8051/8751
POLLING
HAROWARE
INPUT LEVEL AND
INTERRUPT REQUEST
FLAG REGISTERS:
INTO
INT1
-
EXTERNAL
tNT ROST 0
INTERNAL
INTERRUPT ENABLE
REGISTER:
SOURCE
GLOBAL
ENABLE
ENABLE
INTERRUPT
PRIORITY
REGISTER:
V
0 -I -
V
-
EXTERNAL
~
----
TIMER 0
SOURCE
I.D.
V
HIGH
PRIORITY
f----.. INTERRUPT
REOUEST
~
VECTOR
INT R08T'1
INTERNAL
TIMER 1
INTERNAL~
SERIAL
PORT
•
•
•
•
•
•
•
V
V
~l
"Ft
FIVE INTERRUPT SOURCES
EACH INTERRUPT CAN BE INDIVIDUALLY ENABLED/DISABLED
ENABLED INTERRUPTS CAN BE GLOBALLY ENABLED/DISABLED
EACH INTERRUPT CAN BE ASSIGNED TO EITHER OF TWO PRIORITY LEVELS
EACH INTERRUPT VECTORS TO A SEPARATE LOCATION IN PROGRAM MEMORY
INTERRUPT NESTING TO TWO LEVELS
EXTERNAL INTERRUPT REQUESTS CAN BE PROGRAMMED TO BE LEVEL~ OR
TRANSITION-ACTIVATED
~
~
LOW
PRIORITY
INTERRUPT
REQUEST
Figure 2.2. 8051 Interrupt System
pullup resistor of approximately 20K- to 40K-ohms
is provided to hold the external driver's loading at a
TTL high level. Ports 1, 2 and 3 can sink/source one
TTL load.
is configured as an input. The configuration of the
ports is shown on the 8051 Family Logic Symbol
of Figure 2.
2.2.2.1 OPEN DRAIN I/O PINS
Each pin of Port 0 can be configured as an open
drain output or as a high impedance input. Resetting
the microcomputer programs each pin as an input by
writing a one (1) to the pin. If a zero (0) is later written
to the pin it becomes configured as an output and
will continuously sink current. Re-writing the pin
to a one (1) will place its output driver in a highimpedance state and configure the pin as an input.
Each I/O pin of Port 0 can sink two TTL loads.
2.2.2:3 MICROPROCESSOR BUS
A microprocessor bus is provided to permit the 8051
to solve a wide range of problems and to allow the
upward growth of user products. This multiplexed
address and data bus provides an interface compatible with standard memories, MCS-80 peripherals
and the MCS-85 memories that include on-chip
programmable I/O ports and timing functions. These
are summarized in the 8051 Microcomputer Expansion Cdmponents chart of Figure 2.3.
When accessing external memory the high-order
address is emitted on Port 2 and the low-order
address on Port O. The ALE signal is provided for
strobing the address into an external latch. The
program store enable (PSEN) signal is provided for
enabling an external memory device to Port 0 during
a read from the Program Memory address space.
When the MOVX instruction is executed Port 3 automatically generates the read (RD) Signal for enabling
an External. Data Memory device to Port 0 or generates the write (WR) signal for strobing the external
memory device with the data emitted by Port O. Port
o emits the address and data to the external memory
through a push/pull driver that can sink/source two
TTL loads. At the end of the read/write bus cycle
Port 0 is automatically reprogrammed to its high
2.2:2.2 QUASI-BIDIRECTIONAL I/O PINS
Ports 1, 2 and 3 are quasi-bidirectional buffers.
Resetting the microcomputer programs each pin as
an input by writing a one (1) to the pin. If a zero (0)
is later written to the pin it becomes configured as
an output and will continuously sink current. Any
pin that is configured as an output will be reconfigured as an input when a one (1) is written to the
pin. Simultaneous to this reconfiguration the output
driver of the quasi-bidirectional port will source
current for two. oscillator periods. Since current is
sourced bnly when a bit previously written to a zero
(0) is updated to a one (1), a pin programmed as an
input will not source current into the TTL gate that
is driving it if the pin is later written with.anoth.er one
(1). Since the quasi-bidirectional output driver sources
current for only two oscillator periods, an internal
AFN-01462A-04
7-4
8031/8051/8751
Category
1.0.
I/O Expander
Standard EPROMs
2758
2716-1
2732
2732A
Description
Comments
8 Line I/O Expander
(Shift Register)
Low Cost I/O Expander
1 K x 8 450
Erasable
2K x 8 350
Erasable
4K x 8 450
Erasable
4K x 8 250
Erasable
User programmable and
erasable.
ns Light
9
ns Light
P
11
ns Light
P
9
ns Light
P
12
D
D
D
12
12
12
D
12
D
D
D
D
12
12
12
12
D
12
D
D
D
12
12
12
D
12
D
12
D
D
12
11.7
D/P
D/P
12/11.7
12/11.7
D
P
P
12
11.6
11.6
2114A
2148
2142-2
1Kx4100nsRAM
1K x 4 70 ns RAM
1K x 4 200 ns RAM
Multiplexed Address/
Data RAMs
8185A
1K x 8 300 ns RAM
c
a.
E
Standard I/O
8212
8282
8283
8255A
8-Bit I/O Port
8-Bit I/O Port
8-Bit I/O Port
Programmable
Peripheral Interface
Programmable Communications Interface
Serves as Address Latch
or I/O port.
1 of 8 Binary Decoder
Bi-directional Bus Driver
Bi-directional Bus Driver
(Inverting)
Programmable Interval
Timer
Programmable
Keyboard/Display
Interface (128 Keys)
GPIB Talker/Listener
GPIB Controller
MCS-80 and MCS-85
peripheral devices are
compatible with the 8051
allowing easy addition of
specialized interfaces.
Future MCS-80/85
devices will also be
compatible.
User programmable to
perform custom I/O and
control functions.
2114A is a 4096-bit static Random Access Memory organized as 1024 words by 4-bits using HMOS, a high performance MOS technology. It uses fully DC stable (static) circuitry throughout, in both the array and the decoding, therefore it .
requires no clocks or refreshing to operate. Data access is particularly simple since address setup times are not required. The
data is read out non destructively and has the same polarity as the input data. Common input/output pins are provided.
The 2114A is designed for memory applications where the high performance and high reliability of HMOS, low cost, large bit
storage, and simple interfacing are important design objectives. The 2ll4A is placed in an la-pin package for the highest
possible density.
It is directly TTL compatible in all respects: inputs, outputs, and a single +5V supply. A separate Chip Select (CS) lead allows
easy selection of an individual package when outputs are or-tied.
PIN CONFIGURATION
Ao
vee
Ao
II,;
A,
A,
Ao
Ao
1/°1
A,
1/°1
A,
110,
A,
1/°3
~ Vee
A, ®
A, ®
®
As
-ill-GND
ROW
(i')
SELECT
As '-'
A,
110,
A,
Ao
BLOCK DIAGRAM
LOGIC SYMBOL
A,
A,
As
MEMORY ARRAY
64 ROWS
64 COLUMNS
@
@
1/°3
A.
IIO,@
A,
1/°4
A,
WE
A.
1/°4
WE
es
IIO,@
110,@
PIN NAMES
AO-Ag
ADDRESS INPUTS
WE
WRITE ENABLE
C!
CHIP SELECT
o=
Vee POWER 1+5VI
GND GROUND
PIN NUMBERS
1/01 -1/04 OATA INPUT/OUTPUT
INTEL CORPORATION ASSUMES NO RESPONSIBILITY FOR THE USE OF ANY CIRCUITRY OTHER THAN CIRCUITRY EMBODIED IN AN INTEL PRODUCT. NO OTHER CIRCUIT PATENT LICENSES ARE IMPLIED.
·.INTEL CORPORATION, 1977. 1979
DECEMBER. 1979
8-1
in1:ef
2114A FAMILY
ABSOLUTE MAXIMUM RATINGS·
·COMMENT: Stresses. above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation ofthe device
at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure is not implied. Exposure to absolute maximum rating
conditions for extended· periods may affect device reliability.
Temperature Under Bias .................. -lOoC to 80°C
Storage Temperature .................... -6SoC to 1S0°C
Voltage on any Pin
With Respect to Ground .................. -3.SV to +7V
Power Dissipation ...............................•. 1.0W
D.C. Output Current ................................ SmA
D.C. AND OPERATING CHARACTERISTICS
TA = O°C to 70°C, Vee = sv ± 10%, unless otherwise noted.
SYMBOL
PARAMETER
2114AL-1/L-2/L-3/L-4
Min. Typ.111 Max.
Min.
2114A-4/-S
Typ.lll Max.
CONDITIONS
UNIT
III
Input Load Current
(All Input Pins)
10
10
/lA
V ,N
IILOI
1/0 Leakage Current
10
10
/lA
CS ~ V'H
VI/O = GND to VCC
IcC
Power Supply Current
70
mA
Vee = max, 11/0 = 0 mA,
TA = DoC
VIL
Input Low Voltage
-3.0
O.B
-3.0
O.B
V
VIH
Input High Voltage
2.0
6.0
2.0
6.0
V
10L
Output Low Current
2.1
9.0
10H
Output High Current
-1.0
-2.5
IOsI2)
Output Short Circuit
Current
40
25
50
2.1
9.0
-1.0
-2.5
40
40
VOL = O.4V
mA
VOH
mA
= 250 C and Vee = 5.0V.
2. Duration not to exceed 30 seconds.
CAPACITANCE
=2SoC, f =1.0 MHz
SYMBOL
TEST
CliO
Input/Output Capacitance
CIN
Input Capacitance
NOTE:
MAX
UNIT
5
pF
V'/O ~ OV
5
pF
VIN
CONDITIONS
=
OV
This parameter is periodically sampled·and not 100% tested.
A.C. CONDITIONS OF TEST
Input Pulse Levels ................................................... 0.8 Volt to 2.0 Volt
Input Rise and Fall Times ...................................................... 10 nsec
Input and Output Timing Levels ................................................ 1.5 Volts
Output Load ............................................... 1 TTL Gate and C L = 100 pF
8-2
0 to 5.SV
mA
NOTE: 1. Typical values are for T A
TA
~
~
2.4V
inter
2114A FAMILY
A.C. CHARACTERISTICS
± 10%.
TA = O'C to 70'C. Vee" 5V
unless otherwise noted.
READ CYCLE (1)
2114AL-1
PARAMETER
SYMBOL
Min.
Max.
2114AL-2
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
UNIT
ns
250
200
150
120
100
2114A-4/L-4 2114A-5
2114AL-3
tRC
Read Cycle Time
tA
Access Time
100
120
150
200
250
ns
tco
Chip Selection to Output Valid
70
70
70
70
85
ns
tcx
Chip Selection to Output Active
toro
Output 3-state from Deselection
tOHA
Output Hold from
Address Change
10
10
30
15
10
35
50
40
ns
60
15
15
15
15
ns
10
10
ns
WRITE CYCLE [2)
2114AL-1
PARAMETER
SYMBOL
Min.
2114AL-2
Max.
Min.
2114AL-3.
Max.
Min.
2114A-4/L-4 2114A-S
Max.
Min.
Max.
Min.
Max.
UNIT
twc
Write Cycle Time
100
120
150
200
250
ns
tw
Write Time
75
75
90
120
135
ns
tWR
Write Release Time
0
0
0
0
0
torw
Output 3-state from Write
tow
Data to Write Time Overlap
70
70
90
120
135
ns
tOH
Data Hold from Write Time
0
0
0
0
0
ns
30
35
ns
50
40
60
ns
NOTES:
1. A Read occurs during the overlap of a low Cs and a high WE.
2. A Write occurs during the overlap of a low CS and a low WE.t w is measured from the latter of ~ or WE going low to the earlier of CS or WE going high.
WAVEFORMS
WRITE CYCLE
READ CYCLE@
I------toc-------I
twe
i------tA--------i
ADDRESS
ADDRESS
-..II'-------------i--'l'---
~tw"-
0c~
f/I I I IIII III II,
l""""
tw
® ~\\'\
-tor=!
NOTES:
DOUT
3. WE is high for a Read Cycle.
4. If the CS low transition occurs simultaneously with the WE low
transition, the output buffers remain in a high impedance state.
5. WE must be high during all address transitions.
[tow
D,N
8-3
_I
tDH
inter
2114A FAMILY
TYPICAL D.C. AND .A.C. CHARACTERISTICS
NORMAUZED ACCESS TIME VS.
SUPPLY VOLTAGE
NORMALIZED ACCESS TIME VS.
AMBIENT TEMPERATURE
1.2
1.2
1. 1
1. 1
1.0
1.0
$.
c·
i
---
,:$
o
I
0.9
w
0.6
0.9
:.---
08
o. 7
o. 7
o. 6
0.6
~
o. 5
o. 5
4.50
4.75
5.00
5.50
5.25
20
40
60
60
Vcc(V)
NORMALIZED ACCESS TIME VS.
OUTPUT LOAD CAPACITANCE
NORMALIZED POWER SUPPLY CURRENT
VS. AMJlIENT TEMPERATURE
1.4
1.2
1.3
/
1.2
$
Q
w
!:lI
./'
1.1
-i
/
1. 1
~
,,/
0.9
~ 1.0 ,,-/
--
1.0
o
I---
0.8
~
0.7
0.9
r-
0.6
0.8
0.7
0.5
100
150
200
250
300
350
o
OUTPUT SOURCE CURRENT
VS. OUTPUT VOLTAGE
OUTPUT SINK CURRENT
VS. OUTPUT VOLTAGE
40
0
30
60
20
~
10
40
K
60
40
20
20
~
o
o
0
VOH (V)
/
/
V
/
/
1
VOL (V)
8-4
80
2316E
16K (2K )( 8) ROM
• EPROM/ROM Pin Compatible for
Cost-Effective System
Development
• Fast Access Time-450 ns Max.
• Single +5V.:!:. 10% Power Supply
• Completly Static Operation
• Intel MCS 80 and 85 Compatible
• Inputs and Outputs TTL
Compatible
• Three Programmable Chip
Selects for Simple Memory
Expansion and Sy·stem Interface
• Three-State Output for Direct
Bus Interface
The Intel® 2316E is a 16,384-bit static, N-channel MaS read only memory (ROM) organized as 2048 words by 8 bits. Its
high bit density is ideal for large, non-volatile data storage applications such as program storage. The three-state outputs and
TTL input/output levels allow for direct interface with common system bus structures. The 2316E single +5V power supply
and 450 ns access time are both ideal for usage with high performance microcomputers such as the Intel MCSTM-80 and
MCSTM-85 devices.
A cost-effective system development program may be implemented by using the pin compatible Intel 2716 16K UV
EPROM for prototyping and the lower cost 2616 PROM and 2316E ROM for production. The three 2316E programmable
chip selects may be defined by the user and are fixed during the masking process. To simplify the conversion from
2716 prototyping to 2316E production, it is recommended that the 2316E programmable chip select logic levels be
defined the same as that shown in the below data sheet pin configuration. This pin configuration and these chip select
logic levels are the same as the 2716.
BLOCK DIAGRAM
PIN CONFIGURATION
A,
Vee
As
A8
..
AS
A.
A3
es,
CSl
A,
AlO
A,
CS2
A.
0,
D.
Os
0,
Os
0,
04
03
A, •
Ag
A8
A,
AS
..
A,
A,
A,
PIN NAMES
A,
A.
8-5
AFN-00684A-Gl
2316E
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias .......•_10°C to BOoC
Storage Temperature .............. _65°C to +150°C
Voltage On Any Pin With Respect
to Ground . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
Power Dissipation ..............' ........ 1.0 Watt
·COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This Is a
stress rating only and functional operation of the devica at these or
at any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device
reliability .
D.C. AND OPERATING CHARACTERISTICS
T A = O°C to +70°C. Vee = 5V ±10%. unless otherwise specified.
SYMBOL
PARAMETER
LIMITS
MIN.
TYP.(11
MAX.
Input Load Current
(All Input Pins)
ILl
UNIT
TEST CONDITIONS
10
IlA
VIN = 0 to 5.25V
ILOH
Output Leakage Current
10
IlA
Chip Deselected. VOUT = 4.0V
ILOL
Output Leakage Current
-20
IlA
Chip Deselected. VOUT = O.4V
ICC
Power Supply Current
120
mA
All Inputs 5.25V Data Out Open
VIL
Input "Low" Voltage
-0.5
0.8
V
VIH
Input "High" Voltage
2.4
Vee+1.OV
V
VOL
Output "Low" Voltage
0.4
V
IOL = 2.1 mA
VOH
Output "High" Voltage
V
IOH =- 400 IlA
7D
2.4
NOTE: 1. TYPIcal values for T A = 2Soe and nominal supply voltage.
A.C. CHARACTERISTICS
T A = O°C to +70°C. Vee = +5V ±10%. unless otherwise specified.
SYMBOL
LIMITS
PARAMETER
MIN.
UNIT
MAX.
tA
Address to Output Delay Time
450
ns
teo
Chip Select to Output Enable Delay Time
120
ns
tOF
Chip Deselect to Output Data Float Delay Time
100
ns
CONDITIONS OF TEST FOR
A.C. CHARACTERISTICS
10
CAPACITANCE121
SYMBOL
Output Load ........... 1 TTL Gate and CL = 1bo pF
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . 0.8 to 2.4V
Input Pulse Rise and Fall Times (10% to 90%) ..... 20 ns
Timing Measurement Reference Level
Input . . . . . . . . . . . . . . . . . . . . . . . . . 1V and 2.2V
Output . . . . . . . . . . . . . . . . . . . . . . . 0.8V and 2.0V
TA = 25°C. f = 1 MHz
TEST
LIMITS
TYP.
MAX.
CIN
All Pins Except Pin Under
Test Tied to AC Ground
5pF
10 pF
COUT
All Pins Except Pin Under
Test Tied to AC Ground
10 pF
15 pF
NOTE: 2. This parameter is periodically sampled and is not 100%
tested.
8-6
AFN-00684A-02
A.C. Waveforms
ADDRESS
1------ tco ------"'I
PROGRAMMABLE
CHIP SELECTS
~----------IA------------~
DATA
OUTPUT
----=HIGHZ~--~~~~~~~~~~-OU-T~TV-ALIO~~~JlJJI
Typical System Application (8K )( 8 ROM Memory)
\
~
ADDRESS BUS
I I
\
J
CONTROL BUS
_Ll
\
I
I
DA.TA BUS
,
At2
An
liNTEL
82051
~
eli
Fll
'3
t---
C!2
1
es,
+5V
'---
~
C!2
eS3
+5V
~
+SV
fl
ROM
..v - eS3
t-
-
Mes-so
SYSTEM
BUS
f"07-00
An-Al0
CHIP
SELECT
DECODER
MEMR
I
~
es,
~~
Ircs,l
.,
ROM
V
os.
es,
eS3
• 0
ROM
2316E
8-7
AFN-006B4A-03
intel~
2708
8K (1 K x 8) UV ERASABLE PROM
•
•
•
Low Power Dissipation Max. (270SL)
Max. Power
Max. Access
2708
800mW
450ns
2708L
425mW
450ns
2708·1
800mW
350ns
2708·6
800mW
425 mW
Fast Access Time - 350 ns Max.
(270S·1)
Static - No Clocks Required
550ns
•
Data Inputs and Outputs TTL
Compatible during both Read and
Program Modes
•
Three·State Outputs - OR·Tie
Capability
The Intel@ 2708 is an 8192-bit ultraviolet light erasable and electrically reprogrammable EPROM, Ideally suited where
fast turnaround and pattern experimentation are Important requirements. All data Inputs and outputs are TTL compatible during both the read and program modes. The outputs are three-state, allowing direct interface with common
system bus structures.
The 2708L at 425mW is available for systems requiring lower power dissipation than from the 2708. A power dissipation
savings of over 50% without any sacrifice in speed is obtained with the 2708L. The 2708L has high input noise Immunity
and is specified at 10% power supply tolerance. A high-speed 2708-1 is also available at 350ns for microprocessors
requiring fast access times.
The 2708 family is fabricated with the N-channel silicon gate FAMOS technology and is available in a 24-pln dual in-line
package.
PIN CONFIGURATION
BLOCK DIAGRAM
DATA OUTPUT
A,
~e
A.
A.
As
A9
A.
~.
A,
CSNIE
A2
lobo
A,
PROGRAM
00-07
I
t t
CHIP SELECT
lOGIC
OUTPUT BUFFERS
v
(UB) Ao
071MSBI
ILSBIOo
00
0,
Os
02
0,
~
03
V GATING
DECODER
ADDRESS
INPUTS
A._
A,A._
A.
As -
64 X 128
X
ROM ARRAY
DECODER
~-
PIN CONNECTION DURING READ OR PROGRAM
PIN NAMES
Ao·Ag
PIN NUMBER
ADDRESS
ADDRESS INPUTS
01..()a
DATA OUTPUTS/INPUTS
C /WE
CHIPSELECT/WRITE ENABLE INPUT
DATA I/O
9-11.
INPUTS
1-8.
13·17
22.23
HIGH IMPEDANCE
AIN
DON'TeARE
D,N
A'N
MODE
READ
DESELECT
DOUT
PROGRAM
V,.
12
GND
GND
GND
PROGRAM
18
GND
GND
PULSED
Voo
19
+12
+12
+12
CStwE
20
VIL
V,H
VIHW
Va.
Vee
21
-s
2'
+5
+s
+s
-5
-5
NY
INTEL CORPORATION ASSUMES NO RESPONSIBllITV FOR THE USE OF ~NV CIRCUITRV OTHER THAN CIRCUITRV EMBODIED IN AN INTEL PRODUCT. NO OTHER CIRCUIT PATENT LICENSES ARE IMPLIED.
@INTELCORPORATION 1980
January 1980
.
8-8
AFN-ol104A-ol
2708 FAMILY
PROGRAMMING
The programming specifications are described in the Data Catalog PROM/ROM Programming Instructions Section.
Absolute Maximum Ratings*
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . _25°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . _65°C to +125°C
Voo With Respect to VBB . . . . . . . . . . . . . . . . . . . . . . . +20V to -0.3V
VCC and Vss With Respect to VBB . . . . . . . . . . . . . . . . . +15V to -0.3V
All Input or'Output Voltages With Respect
to VBB During Read. . . . . . . . . . . . . . . . . . . . . . . .. +15V to -0.3V
CSIWE Input With Respect to VBB
During Programming . . . . . . . . . . . . . . . . . . . . . . . . +20V to -0.3V
Program I nput With Respect to VBB .............. "
+35V to -0 3V
Power Dissipation ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.5W
'COMMENT
Stresses above those listed under" Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation
of the device at these·or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
nco AND A.C.OPERATING CONDITIONS DURING READ
Temperature Range
Vcc Power Supply
Voo Power Supply
VBB Power Supply
2708
2708·1
2708·6
2708L
0·C-70·C
0·C-70·C
0·C-70·C
0·C-70·C
5V±5%
12V±5%
-5V±5%
5V±5%
12V±5%
-5V:t.5%
5V±5%
12V±5%
-5V±5%
5V±10%
12V ± 10%
-5V±10%
READ OPERATION
D.C. AND OPERATING CHARACTERISTICS
2708.2708·1.2708,8 Limit.
Symbol
2708L Limits
Unit.
Parameter
Min.
Typ.12I
Max.
1
10
Min.
Typ.l2l
Max.
1
10
~A
Te.t Conditions
VIN = 5.25V or VIN = VIL
ILl
Address and Chip Select Input Sink
Current
ILO
Output Leakage Current
1
10
1
10
~A
VOUT = 5.5V, CSJWE = 5V
100[31
Voo Supply Current
50
65
21
28
mA
Worst Case Supply Currents[4]
IcC[3]
Vcc Supply Current
6
10
2
4
mA
All Inputs High;
IBB[3]
VBB Supply Current
30
45
10
14
mA
CSWE=5V;TA =0'C
VIL
Input Low Voltage
Vss
0.65
Vss
0.65
V
VIH
Input High Voltage
3.0
VCC +1
2.2
Vcc+ 1
V
VOL
Output Low Voltage
0.4
V
VOH1
Output High Voltage
3.7
VOH2
Output High Voltage
2.4
0.45
10L = 1.6mA (2706. 2708-1, 2708-6)
10L = 2mA (2706L)
PO
NOTES:
Power Dissipation
3.7
V
2.4
600
V
10H= -100~A
10H= -lmA
325
mW
TA =70'C
425
mW
TA=O'C
1. VBB must be applied prior to Vcc and Voo. VBB must also be the last power supply switched ofl.
2. Typical values are for TA = 25'C and nominal supply voltages.
3. The total power dissipation Is not calculated by summing the various currents (1 00 • Icc, and IBB) multiplied by their respective vol·
tages since current paths exist between the various power supplies and Vss. The 100. Icc. and IBB currents should be used to deter·
mine power supply capacity only.
4. IBB for the 2708L Is specified in the programmed state and is lSmA maximum In the unprogrammed state.
8-9
AFN-Qll04A-Q2
2708 FAMILY
2708L
RANGE OF SUPPLY CURRENTS
VS. TEMPERATURE
2708,2708·1, AND 2708·6
RANGE OF SUPPLY CURRENTS
VS. TEMPERATURE
ACCESS TIME VS. TEMPERATURE
~
80
1
i
ALL POSSIBLE OPERATING
CONDITIONS:
1 TTL LOAD + l00pF
V CC " 5.25V
\fOO ~ 12.6V
400
Vea = -5.25V
300
'DD
20D
-
,..--
----
--
'00
40
60
80
TAf'C)
.~~~~~hH~cJ
o
'00
20
40
80
80
100
~20
20
TA,r e)
4.
8.
80
TA 1°C)
A.C. CHARACTERISTICS
Symbol
t ACC
2708, 2708L Limits
Min.
Max.
Parameter
450
Address to Output Delay
Chip Select to Output Delay
tOF
Chip Deselect to Output Float
0
tOH
Address to Output Hold
0
120
120
0
0
CAPACITANCE [1] TA = 25°C, f = 1 MHz
2708·6 Limits
Min.
Max.
350
120
tco
120
0
0
Units
550
ns
160
ns
160
ns
ns
A.C. TEST CONDITIONS:
Parameter
Typ.
Max.
Unit.
Conditions
CIN
I nput Capacitance
4
6
pF
VIN = OV
COUT
Output Capacitance
8
12
pF
VOUT =OV
Symbol
2708·1 limits
Min.
Max.
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: ";;;20 ns
Timing Measurement Reference Levels: 0.8V and
2.8V for inputs; 0.8V and.2.4V for outputs.
Input Pulse Levels: 0.65V to 3.0V
NOTE: 1. This parameter is periodically sampled and is not 100% tested.
8-10
AFN-O"04A-03
2708 FAMILY
A.C. WAVEFORMS 121
K
ADDRESSES
ADDRESSES
VALID
V
CS/WE
~---
teo
I'II---~
tOF (4)
I----+--
tACC ( 3 1 - - - - - - - 1
OUTPUT _ _ _ _ _...:.:.HI:;;:G:.:.H,:,Z_ _ _ _-f+~H~+_~H++_t_<
toH
(a)
VALID OUTPUT
~
HIGH Z
~//
NOTES:
2. ALL TIMES SHOWN IN PARENTHESES ARE MINIMUM AND ARE NSEC
UNLESS OTHERWISE SPECIFIED.
3.
CS MAY BE DELAYED UP TO tACC·tCO
AFTER ADDRESSES ARE VALID
4.~1;7~~~~~I~~iri ~R'6::~'OR ADDRESS CHANGE, WHICHEVER OCCURS
FIRST.
ERASURE CHARACTERISTICS
The erasure characteristics of the 2708 family are such that
erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (A). It
should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000-4000A range.
Data show that constant exposure to room level fluorescent lighting could erase the typical device in approximately 3 years, while it would take approximately 1 week
to cause erasure when exposed to direct sunlight. If the
2708 is to be exposed to these types of lighting conditions
for extended periods of time, opaque labels are available
from Intel which should be placed over the 2708 window
to prevent unintentional erasure.
The recommended erasure procedure (see Data Catalog
PROM/ROM Programming Instructions Section) for the
2708 family is exposure to shortwave ultraviolet light
which has a wavelength of 2537 Angstroms (A). The integrated dose (j,e" UV intensity X exposure time) for erasure
should be a minimum of 15 W-sec/cm 2 . The erasure time
with this dosage is approximately 15 to 20 minutes using an
ultraviolet lamp with a 12000 /J.W/cm 2 power rating, The
device should be placed within 1 inch of the lamp tubes
during erasure, Some lamps have a filter on their tubes
which should be removed before erasure,
8-11
AFN-01104A-04
2716
16K (2K )( 8) UV ERASABLE PROM
• Fast Access Time
- 350 ns Max. 2716·1
- 390 ns Max. 2716·2
- 450 ns Max. 2716
490 ns Max. 2716·5
- 650 ns Max. 2716·6
• Single
• Pin Compatible to Intel® 2732 EPROM
• Simple Programming Requirements
Single Location Programming
- Programs with One 50 ms Pulse
+ 5V Power Supply
• Inputs and Outputs TTL Compatible
during Read and Program
• Low Power Dissipation
525 mW Max. Active Power
- 132 mW Max. Standby Power
• Completely Static
The intei® 2716 is a 16,384·bit ultraviolet erasable and electrically programmable read-only memory (EPROM). The 2716
operates from a single 5·volt power supply, has a static standby mode, and features fast single address location programming. It makes designing with EPROMs faster, easier and more economical.
The 2716, with its single 5-volt supply and with an access time up to 350 ns, is ideal for use with the newer high performance
+5V microprocessors such as Intel's 8085 and 8086. A selected 2716-5 and 2716-6 is available for slower speed applications.
The 2716 is also the first EPROM with a static standby mode which reduces the power dissipation without increasing access
time. The maximum active power dissipation is 525 mW while the maximum standby power dissipation is only 132 mW, a
75% savings.
The 2716 has the simplest and fastest method yet devised for programming EPROMs - single pulse TTL level programming.
No neeo for high voltage pulsing because all programming controls are handled by TTL signals. Program any location at any
time-either individuallY, sequentially or at random, with the 2716's single address location programming. Total programming
time for all 16,384 bits is only 100 seconds.
PIN CONFIGURATION
MODE SELECTION
2732 t
2716
I~
A,
A6
A,
0,
AO
0,
0,
GNO
I,a,
OE
120'
v"
,2',
Read
V'L
V'L
'5
Standby
V,"
Don't Care
+5
Program
Pulled VIL to V1H
Program Verify
o.
o.
CE/PGM
Vee
OUTPUTS
1241
19·11,13.171
MODE
0,
Program Inhibit
GNO
VIH
.2.
V'L
V'L
'25
V'C
V,H
+25
+6
DOUT
••
High Z
DIN
'5
'5
DOUT
••
HiWt Z
BLOCK DIAGRAM
tRefer to 2732
data sheet for
specifications
Yccc>--.-
-UATAOllTPlITS
00 ·01
PIN NAMES
"o-A,O
C IPGM
ADDRESSES
CHIP ENABI.E/PROGRAM
DE
OUTPUT ENABLE
0-0
OUTPUTS
AO-Al0
ADDRESS
INPUTS
8-12
AFN-008' 1A-01
2716
PROGRAMMING
The programming specifications are described in the Data Catalog PROM/ROM Programming Instructions Section.
Absolute Maximum Ratings*
Temperature Under Bias . . . . . . . . . . . . . _10°C to +80°C
Storage Temperature . . . . . . . . . . . . . . -65°C to +125°C
All Input or Output Voltages with
Respect to Ground . . . . . . . .
. .... +6V to -0.3V
Vpp Supply Voltage with Respect
to Ground During Program ........ +26.5V to -0.3V
'COMMENT: Stresses above those listed under "Absolute Max;·
mum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device
reliability.
DC and AC Operating Conditions During Read
Temperature Range
2716
2716-1
2716-2
2716-5
2716-6
O°C _ 70°C
O°C _ 70°C
O°C _ 70°C
O°C _ 70°C
OoC _ 70°C
5V ±5%
5V ±10%
5V ±5%
5V ±5%
5V ±5%
Vcc
Vcc
Vcc
VCC
VCC
Vcc Power Supply[1.2]
Vpp Power Supply[2]
READ OPERATION
D.C. and Operating Characteristics
Limits
Parameter
Symbol
Typ.[3]
Min.
Max.
Unit
Conditions
III
Input Load Current
10
f.lA
VIN = 5.25V
ILO
Output Leakage Current
10
f.lA
VOUT = 5.25V
Vpp = 5.25V
IpPl [2]
Vpp Current
5
mA
ICCl [2]
Vcc Current (Standby)
10
25
mA
CE = VIH. OE = VIL
ICC2 12 ]
V cc Current (Active)
57
100
mA
O"E=cr=VIL
VIL
I nput Low Voltage
-0.1
0.8
V
VIH
Input High Voltage
2.0
V c c+ 1
V
VOL
Output Low Voltage
VOH
Output High Voltage
NOTES:
0.45
2.4
V
IOL = 2.1 mA
V
IOH = -400f.lA
1. Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
2. Vpp may be connected directly to Vee except during programming. The supply current would then be the sum of ICC and IPP1.
3. Typical values are for T A
= 25° C and
nominal supply voltages.
4. This parameter is only sampled and is not 100% tested.
Typical Characteristics
ICC CURRENT
ACCESS TIME
vs.
vs.
vs.
TEMPERATURE
CAPACITANCE
TEMPERATURE
70
60
--
r-- r-
50
ICC2 ACTIVE CURRENT
Cl:=Vll
I
~ 40
--
vccrv--
!
" 30
!:}
20
ICCl STANDBY CURRENT
CE=VIH
VCC=5V _
10
o
T
o
10
W
~
40
~
TEMPERATURE ( CI
M
ro
M
700
700
600
600
500
500
-
]" 400
~
.-
ACCESS TIME
Vcc = 5V
400
f--
300
300
~
200
200
100
o
r--
100
o
o
100
200
300
400
CL (pF)
8-13
500
600
700
MO
o
10
W
~
~
~
~
ro
~
TEMPERATURE ('C)
AFN-00811A'()2
2716
A.C. Characteristics
Limits (ns)
2716
Symbol
Parameter
Min.
2716-1
Max.
Min.
2716-2
Min.
Max.
Max.
2716-5
Min.
Max.
Test
2716-6
Min.
Conditions
Max.
tACC
Address to Output Delay
450
350
390
450
450
tCE
CE to Output Delay
450
350
390
490
650
OE = VIL
tOE
Output Enable to Output Delay
120
120
120
160
200
CE=VIL
tOF
Output Eneble High to Output Float
0
100
CE=VIL
tOH
Output Hold from Addresses, CE or
DE Wh iehever Oeeu rred First
0
0
Max.
Unit Conditions
100
0
100
Capacitance [4] TA = 2SoC, f = 1 MHz
Symbol
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
0
100
0
0
0
CE
= OE = VIL
A.C. Test Conditions:
Typ.
4
pF
6
8
I
100
0
0
CE=OE=VIL
pF
12
I
I
VIN
I
=
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: ';;;20 ns
Input Pulse Levels: 0.8V to 2.2V
OV
VOlJT = OV
Timing Measurement Rp.fp.renr.e Leve!:
I
Inputs
Outputs
1V and 2V
0.8V and 2V
A. C. Waveforms [1]
ADDRESSES
VALID
ADDRESSES
CE--------------~--~
5E--------------~----------~
1''------+-. . . . . . . . . .
[6J
'OF
,...~....,....,,...,,...,t--.
••••••
HIGH Z
OUTPUT----------------------------i-~~_+~<
HIGH Z
'-a..................'t-- •••••••
NOTE:
1.
2.
3.
4.
5.
6.
VCC must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
Vpp may be connected directly to VCC except during programming. The supply current would then be the sum of ICC and IpP1.
Typical values are for TA = 25' C and nominal supply voltages.
This parameter is only sampled and is not 100% tested.
OE may be delayed up to tACC - tOE after the falling edge of CE without impact on tACC.
tDF is specified from OE or CE, whichever occurs first.
8-14
AFN-00811 A-03
2716
TYPICAL 16K EPROM SYSTEM
A8-15
1-_--+--------------.
ADO-7
~""--"-"'I
8212
ADDRESS
ALE ~t------., LATCH
RD~t------~~--------~
8085
101M
o
This scheme accomplished by using CE (PO) as the primary decode. OE (CS) is now controlled by previously unused
signal. RO now controls data on and off the bus by way of OE.
o
A selected 2716 is available for systems which require CE access of less than 450 ns for decode network operation.
o
The use of a PROM as a decoder allows for:
a) Compatibility with upward (and downward) memory expansion.
b) Easy assignment of ROM memory modules, compatible with PUM modular software concepts.
SK, 16K, 32K, 64K 5V EPROM/ROM FAMILY
PRINTED CIRCUIT BOARD LAYOUT
o
o
a
o
0
o c,
8-15
2716
ERASURE CHARACTERISTICS
OUTPUT OR-TIEING
The erasure characteristics of the 2716 are such that erasure
begins to occur when exposed to light with wavelengths
shorter than approximately 4000 Angstroms (A). It should
be noted that sunlight and certain "types of fluorescent
lamps have wavelengths in the 3000-4000A range. Data
show that constant exposure to room level fluorescent
lighting could erase the typical 2716 in approximately 3
years, while it would take approximatley 1 week to cause
erasure when exposed to direct sunlight. If the 2716 is to
be exposed to these types of lighting conditions for ex·
tended periods of time, opaque labels are available from
Intel which should be placed over the 2716 window to
prevent unintentional erasure.
Because 2716's are usually used in larger memory arrays,
Intel has provided a 2 line control function that accomodates this use of multiple memory connections. The two
line control function allows for:
a) the lowest possible memory power dissipation, and
b) complete assurance that output bus contention will
not occur.
To most efficiently use these two control lines, it is recommended that CE (pin 18) be decoded and used as the
primary device selecting function, while OE (pin 20) be
made a common connection to all devices in the array and
connected to the READ line from the system control bus.
This assures that all deselected memory devices are in their
low power standby mode and that the output pins are only
active when data is desired from a particular memory
device.
PROGRAMMING
The recommended erasure procedure (see Data Catalog
PROM/ROM Programming Instruction Section) for the
2716 is exposure to shortwave ultraviolet light which has
a wavelength of 2537 Angstroms (A). The integrated dose
(i.e., UV intensity X exposure time) for erasure should be
a minimum of 15 W-sec/cm 2 . The erasure time with this
dosage is approxirnatdy i 5 to 20 minutes using an uitraviolet lamp with a 12000 pW/cm 2 power rating. The 2716
should be placed within 1 inch of the lamp tubes during
erasure. Some lamps have a filter on their tubes which
should be removed before erasure.
Initia;Jy, cmu oTter each erasure, aii bits of the 2/10 are in
the "1" state. Data is introduced by selectively programming "O's" into the desired bit locations. Although only
"O's" will be programmed, both "l's" and "O's" can be
presented in the data word. The only way to change a "0"
to a "1" is by ultraviolet light erasure.
DEVICE OPERATION
The 2716 is in the programming mode when the Vpp power
supply is at 25V and OE is at V IH. The data to be programmed is applied 8 bits in parallel to the data output
pins. The levels required for the address and data inputs are
The five modes of operation of the 2716 are listed in Table
I. It should be noted that all inputs for thefive modes are at
TTL levels. The power supplies required are a +5V V cc and
a Vpp. The Vpp power supply must be at 25V during the
three programming modes, and must be at 5V in the other
two modes.
TTl.
When the address and data are stable, a 50 msec, active
high, TTL program pulse is applied to the CE/PGM input.
A program pulse must be applied at each address location
to be programmed. You can program any location at any
time - either individually, sequentially, or at random.
The program pulse has a maximum width of 55 msec. The
2716 must not be programmed with a DC signal applied to
the CE/PGM input.
TABLE I. MODE SELECTION
~
CE/PGM
(181
DE
(201
Read
V'L
Standby
V'H
V'L
Don't Care
Vpp
Vee
(211
(24)
+,
+,
DOUT
+,
+,
High Z
OUTPUTS
(9.11,13-17)
MODE
Program
Program Verify
Program Innibit
Pulsed VIL to VIH
V'H
+25
+,
V'L
V'L
+2'
+,
DOUT
+2'
+,
High Z
V'L
V'H
D'N
Programming of multiple 2716s in parallel with the same
data can be easily accomplished due to the simplicity of
the programming requirements. like inputs of the paralleled 2716s may be connected together when they are programmed with the same data. A high level TTL pulse
applied to the CE/PGM input programs the paralleled
2716s.
PROGRAM INHIBIT
READ MODE
The 2716 has two control functions, both of which must be
logically satisfied in order to obtain data at the outputs.
Chip Enable (CE) is the power control and should be used
for device selection. OUtput Enable (OE) is the output
control and should be used to gate data to the output
pins, independent of device selection. Assuming that
addresses are stable, address access time (tACC) is equal to
the delay from CE to output (tCE). Data is available at
the outputs 120 ns (tOE) after the falling edge of OE,
assuming that CE has been low and addresses have been
stable for at least tACC - tOE,
STANDBY MODE
Programming of multiple 2716s in parallel with different
data is also easily accomplished. Except for CE/PGM, all
like inputs (including OE) of the parallel 2716s may be
common. A TTL level program pulse applied to a 2716's
CE/PGM input with Vpp at 25V will program that 2716.
A low level CE/PGM input inhibits the other 2716 from
being programmed.
PROGRAM VERIFY
The 2716 has a standby mode which reduces the active
power dissipation by 75%, from 525 mW to 132 mW. The
2716 is placed in the standby mode by applying a TTL high
signal to the CE input. When in standby mode, the outputs
are in a high impedence state, independent of the DE input.
A verify should be performed on the programmed bits to
determine that they were correctly programmed. The verify
may be performed wth V pp at 25V. Except during programming and program verify, Vpp must be at 5V.
8-16
AFN-00911 A-oS
2732A
32K (4K x 8) UV ERASABLE PROM
• Pin Compatible to 2764 EPROM
• 200ns (2732A·2) Maximum Access
Time ... HMOS*·E Technology
• Compatible to High Speed 8mHz
8086·2 MPU .. .Zero WAIT State
• Industry Standard Pinout . .. JEDEC
Approved
• Two Line Control
• Low Standby Current . .. 35mA Max.
The Intel 2732A Is a 5Vonly, 32,384 bit ultraviolet erasable and electrically programmable read-only memory (EPROM). It
Is pin compatl~le to Intel's 450ns 2732. The standard 2732A's access time is 250ns with speed selection (2732A-2)
available at 200ns. The access time is compatible to high performance microprocessors, such as the 8mHz 8086-2. In
these systems, the 2732A allows the microprocessor to operate without the addition of WAIT states.
An Important 2732A feature is the separate output control, Output Enable (OE), from the Chip Enable control (CE). The OE
control eliminates bus contention in multiple bus microprocessor systems. Intel's Application Note AP-72 describes the
microprocessor system implementation of the OE and CEcontrols on Intel's EPROMs. AP-72 Is available from Intel's
Literature Department.
The 2732A has a standby mode which reduces the power dissipation without increasing access time. The maximum
active current Is 150mA, while the maximum standby current is only 35mA, a 75% saving. The standby mode Is achieved
by applying a TTL-high signal to the CE input.
The 2732A Is fabricated with HMOS*-E technology, Intel's high speed N-channel MOS Silicon Gate Technology.
2764
MODE SELECTION
PIN CONFIGURATION
2732A
PIN CONFIGURATION
v,,
'Vee
An
POM
~
MODE
CE
(18)
OENpp
(20)
OUTPUTS
Vcc
(24)
(9·11,13·17)
A1
N.CJ11
Read
VIL
VIL
-+;5
DOUT
As
A8
Standby
VIH
Don't Care
+5
High Z
A,
Ag
A,
Program
VIL
Vpp
A11
+5
DIN
A3
OE
Program Veri Iy
VIL
VIL
+5
DOUT
A.
A,O
Program Inhibit
VIH
Vpp
+5
High Z
A,
CE
AO
00
0,
0,
o.
0,
GND
03
BLOCK DIAGRAM
DATA OUTPUTS
00-07
VCC~
('(For total compatibility from
2732A provide a trace to pin 26
GNDO----
PIN NAMES
AO-Al1
ADDRESSES
CE
CHIP ENABLE
~
OUTPUT ENABLE
°o-Or
OUTPUTS
Y·GATING
AQ-A"
ADDRESS
INPUTS
·HMOS Is a patented process of Intel Corporation.
8-17
-
X
DECODER
32.788·8IT
CELL MATRIX
8205
HIGH SPEED 1 OUT OF8 BINARY DECODER
• 1/0 Port or Memory Selector
• Simple Expansion -
• Low Input Load. Current - 0.25 mA
Max, 1/6 Standard TTL Input Load
Enable Inputs
• Hig"h Speed Schottky Bipolar
Technology - 18 ns Max Delay
• Directly Compatible with TTL Logic
Circuits
• Minimum Line Reflection - Low
Voltage Diode Input Clamp
• Outputs Sink 10 mA Min
• 16·Pin Dualln·Line Ceramic or Plastic
Package
The Intel'" 8205 decoder can be used for expansion of systems which utilize input ports, output ports, and memory
components with active low chip select input. When the 8205 is enabled, one of its 8 outputs goes "low", thus a single
row of a memory system is selected. The 3·chip enable inputs on the 8205 allow easy system expansion. For very large
systems, 8205 decoders can be cascaded such that each decoder can drive 8 other decoders for arbitrary memory
expansions.
The 8205 is packaged in a standard 16-pin dual in-line package, and its performance is specified over the temperature
range of oDe to +75°e, ambient. The use of Schottky barrierdlode clamped transistors to obtain fast switching speeds
results in higher performance than equivalent devices made with a gold diffussion process.
PIN CONFIGURATION
LOGIC SYMBOL
Ao
16
V.cc
Ao
A,
15
00
A,
14
0,
A2
A2
3
E,
4
13
°2
E2
5
12
03
E3
6
11
0.
E,
10
°5
E2
06
EJ
8205
0,
GRD
8205
8
ADDRESS
PIN NAMES
ADDRESS INPUTS
ENABLE INPUTS
00· 0,
DECODED OUTPUTS
A,
E,
E,
E3
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
l
H
X
X
X
X
X
X
X
8-18
OUTPUTS
A,
L
L
H
AO· A2
E ,. E3
ENABLE
Ao
Ii
H
L
L
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
H
L
L
H
H
L
H
H
H
H
L
H
0
1
2
3
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
L
•
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
0
6
)
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
AFN-00204B-ol
8205
FUNCTIONAL DESCRIPTION
Decoder
The 8205 contains a one out of eight binary decoder. It ac·
cepts a three bit binary code and by gating this input, creates
an exclusive output that represents the value of the input
code.
Ao
0.
A,
0;
A.z
0,
0,
For example, if a binary code of 101 was present on the AO,
A 1 and A2 address input lines, and the device was enabled,
an active low signal would appear on the 05 outputJine.
Note that all of the other output pins are sitting at a logic
high, thus the decoded output is said to be exclusive. The
decoders outputs will follow the truth table shown below in
the same manner for all other input variations.
DECODER
0.
0;;
0;;
0,
Enable Gate
.Ei:==~:)
ENABLE GATE
When using a decoder it is often necessary to gate the out·
puts with timing or enabling signals so that the exclusive
output of the decoded value is synchronous with the overall
system.
fEH2·E3)
E3
Figure 1. Enable Gate
The 8205 has a built-in function for such gating. The three
enable inputs (~, ~, E3) are ANDed together and create.
a single enable signal for the decoder. The combination of
both active "high" and active "low" device enable inputs
provides the designer with a powerfully flexible gating function to help reduce package count in his system.
ADDRESS
OUTPUTS
A,
A2
E,
E2
E3
0
1
2
3
4
5
6
7
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
H
8-19
ENABLE
Ao
H
H
L
L
L
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
X
X
X
X
X
X
X
H
L
H
H
L
H
H
H
L
H
H
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
AFN-D0204B-02
8205
ray of 8205s can be used to create Ii simple interface to a
24K memory system.
APPLICATIONS OF THE 8205
The 8206 can be used in a wide variety of applications in
microcomputer systems. I/O ports can be decoded from the
address bus, chip select signals can be generated to select
memory devices and the type of machine state such as in
8008 systems can ~ derived from a simple decoding of the
state lines (SO, S1, S2) of the 8008 CPU.
1/0 Port Decoder
Shown in the figure below is a typical application of the
8206. Address input lines are decoded by a group of 8206s
(3). Each input has a binary weight. For example, AO is as·
signed a value of 1 and is the LSB; A4 is assigned a value of
16 and is: the MSB. By connecting them to the decoders as
shown, an active low signal that is exclusive in nature and
represents the value of the input address lines, is available at
the outputs of the 8206s.
This circuit can be used to generate enable signals for I/O
ports or any other decoder related application.
Note that no external gating is required to decode up to 24
exclusive devices and that a simple addition of an inverter
or two will allow expansion to even larger decoder net·
works.
The memory devices used can be either ROM or RAM and
are 1K in storage capacity. 8308s and 81 02s are the devices
typically used for this application. This type of memory device has ten (10) address inputs and an active "low" chip
select (CS). The lower order address bits AO·A9 which come
from the microprocessor are "bussed" to all memory elements and the chip select to enable a specific device or group
of devices comes from the array of ~206s. The output of
the 8206 is active low so it is directly compatible with the
memory components.
Basic operation is that the CPU issues an address to identify
a specific memory location in which it wishes to "write" or
"read" data. The most significant address bits A 10·A 14 are
decoded by the array of 8206s and an exclusive, active low,
chip select is generated that enables a specific memory de·
vice. The least significant address bits AO.A9 irt.!I1tify !!
specific location within the selected device. Thus, all ad'
dresses th roughout the entire memory array are exclusive
in nature and are non·redundant.
This technique can be expanded almost indefinitely to sup·
port even larger systems with the addition of a few inverters
and an extra decoder (8205).
Chip Select Decoder
Using a very similar circuit to the I/O port decoder, an ar·
..... ,1.._ _ _ _ _ _ __
A",----~_I
"---~-I A,
...,---~+-I A,
A,---..,-r--t A,
A,,--~-+-+--t
..
>~~MORIES
A,,---.-1--+--1 A,
A,
8206
8205
E1
A13 --..,-H+-q E,
A14 -_-t-H-+-q E,
'N -+-t-t--t-t---t '3
Vee --+--+-H-+--1 '3
A.
A,
A,
A,
CIj
A,
OS;;
A, -T"1-t--t-1t--ClI
..
OS;
..
ili
f1
8205
12
E1
Eii-+-IH-+t-<:t r,
f3
'3
i5
8206
PORT
NUMBERS
E,
ONO ~>-+-t--Ht-t-q
~
..
is
A,
fi
is
A,
CIj
E,
Cfi4
OS;;
A,
A,
A,
!!Iii
CI1a
es;;
2ij
Figure 2. 1/0 Port Decoder
'3
23
CHIP
SELECTS
an
8206
8206
Ii
es;;
es;;
"
11
E1
r,
cr,;
22
ill;;;
E,
~
E,
csu
'3
CliO
Figure 3. 32K Memory Interface
8-20
AFN-0020411-03
8205
Logic Element Example
Probably the most overlooked application of the 8205 is
that of a general purpose logic element. Using the "on-chip"
enabling gate, the 8205 can be configured to gate its decoded outputs with system timing signals and generate
strobes that can be directly connected to latches, flip-flops
and one-shots that are used throughout the system.
and T2 decoded strobes can connect directly to devices like
8212s for latching the address information. The other decoded strobes can be used to generate signals to control the
system data bus, memory timing functions and interrupt
structure. RESET is connected to the enable gate so that
strobes are not generated during system reset, eliminating
accidental loading.
An excellent example of such an application is the "state
decoder" in an 8008 CPU based system. The 8008 CPU issues three bits of information (SO, S1, S2) that indicate the
nature of the data on the Data Bus during each machine
state. Decoding of these signals is vital to generate strobes
that can load the address latches, control bus discipline and
general machine functions.
The power of such a circuit becomes evident when a single
decoded strobe is logically broken down. Consider fi output, the boolean equation for it would be:
T1 ~ (SO'S1'S2)-(SYNC'Phase 2'Reset)
A six input NAND gate plus a few inverters would be needed to implement this function. The seven remaining outputs
would need a similar circuit to duplicate their function,
obviously a substantial savings in components can be
achieved when using such a technique .
In the figure below a circuit is shown using the 8205 as the
"state decoder" for an 8008 CPU that not only decodes the
SO, S1, S2 outputs but gates these signals with the clock
(phase 2) and the SYNC output of the 8008 CPU. The T1
..,
,
'3
1'1
11
1'2
-, "
T3
2
..
.
0
E,
3"
.-
S,
10
10
12
I
I
I
T1
T1I
1'4
7
82O!)
So
I
I
TO
Sill
-
WAIT
..0
I
I
I
2-..u
STOP
OUTPUTS
FROM
ru
8200
,-
7
.
T3
WAIT
T2
I
I
I
ill
I
I
I
I
ill
STOP
I
I
I
I
I
I
W
TO
T'
I
I
I
I
1
I
I
I
I
I
W
I
I
I
I
I
I
I
I
I
w---r
Iff
SYSTEM RESET
., "
State Control Coding
So
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
0
1
1
STATE
T1
T1I
T2
WAIT
T3
STOP
T'
T5
Figure 4. 8205 State Decoder Circuit
8-21
AFN-002048-04
8205
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias:
'COMMENT
-65°C to +125°C
-65°C to +75°C
Ceramic
Plastic
Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or at
any other condition above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
-65°C to +160o C
Storage Temperature
-0.5 to +7 Volts
All Output or Supply Voltages
-1.0 to +5.5 Volts
All I nput Voltages
125 mA
Output Currents
D.C. CHARACTERISTICS
= O·C to + 75·C, Vee = 5V ± 5%
TA
8205
PARAMETER
SYiviBOL
INPUT LOAD CURRENT
IF
-
MIN.
LIMIT
MAX.
-0.25
IR
INPUT LEAKAGE CURRENT
10
Ve
INPUT FORWARD CLAMP VOLTAGE
-1.0
Val
OUTPUT "LOW" VOLTAGE
VOH
OUTPUT HIGH VOLTAGE
V 1L
INPUT "LOW" VOLTAGE
UilJiT
0.45
2.4
0.85
2.0
V 1H
INPUT "HIGH" VOLTAGE
Ise
OUTPUT HIGH SHORT
CIRCUIT CURRENT
Vox
OUTPUT "LOW" VOLTAGE
@ HIGH CURRENT
Icc
POWER SUPPLY CURRENT
-40
TEST CONDiTiONS
mA
-120
0.8
70
Vee - 5.25V, V F - 0.45V
~A
Vee = 5.25V, VR = 5.25V
V
Vee = 4.75V, Ie = -5.0 mA
V
Vee - 4.75V, IOl - 10.0 mA
V
Vee = 4.75V, IOH = -1.5 mA
V
Vee = 5.0V
V
Vee = 5.0V
mA
Vee = 5.0V, VOUT = OV
V
Vee = 5.0V, lox = 40 mA
mA
Vee = 5.25V
TYPICAL CHARACTERISTICS
OUTPUT CURRENT VS.
OUTPUT "LOW" VOLTAGE
100
80
Vee'" 5.0V
I
60
J
40
TA
~
/, ~
~ 75"C~
20
o
'"
.,M r-o
.2
.4
i#
~
~ TA '" DOC
-.,
I
-10
-20
i
i
TA. '" DOC
,
b
I
-50
.6
.8
OUTPUT "lOW" VOL TAGE (V)
1.0
~
,/I
1.0
I
I _I.
vee'" s.ov f- -
4.0
TA - DOC
3.0
1\ I\'<
'I
I
If
-30
TA.= 25"C
flV
t. ~
HI- TA~-~
25"C
TA=O°C-
-40
DATA TRANSFER FUNCTION
5.0
r-- ~cc J50~
Y
TA '" 75°C ___
TA~25"C~
OUTPUT CURRENT VS.
OUTPUT "HIGH" VOLTAGE
TA " 25"C
2.0
TA "" 75"C
Mf..\
f--I
!
J
1.0
I
\
\
,\
\.. ~ ~
2.0
3.0
4.0
OUTPUT "HIGH' VOLTAGE (V)
8-22
5.0
.2
.4
,6
.8
1.0
1.2 1.4 1.6
1.B 2.0
INPUT VOL TAGE (V)
AFN-00204B-05
8205
SWITCHING CHARACTERISTICS
Conditions of Test:
Test Load
Input pulse amplitudes:
390n
2.5V
Input rise and fall times: 5 nsee
between 1V and 2V
Measurements are made at 1.5V
CL = 30 pF
All Transistors 2N2369 or Equivalent.
Test Waveforms
ADDRESS OR ENABLE
INPUT PULSE
OUTPUT
A.C. CHARACTRISTICS
TA
= DOG to
+ 75°G, Vee
= 5V
± 5% unless otherwise specified.
PARAMETER
SYMBOL
MAX. LIMIT
t++
ADDRESS OR ENABLE TO
OUTPUT DELAY
t -+
t+_
UNIT
18
ns
18
ns
18
ns
INPUT CAPACITANCE
1. This parameter
IS
periodically sampled and
IS
_.-
._._ ... _.
pF
pF
4(typ.)
5(typ.)
P8205
C8205
----.-~-.--.-
---"-----
--_ .. _-----"-_._- ..-
ns
18
t -CIN (1l
-TEST CONDITIONS
------- ._---------,-. .... ---.- ..
__._-----. -
f = , MHz. Vee = ov
VSIAS = 2.0V. TA
<
250 e
not 100 Yo tested.
TYPICAL CHARACTERISTICS
ADDRESS OR ENABLE TO OUTPUT
DELAY VS. AMBIENT TEMPERATURE
ADDRESS OR ENABLE TO OUTPUT
DELAY VS. LOAD CAPACITANCE
20r---r---r---'---~
20
Vee'" 5.0V
TA " 25"C
~
15
Vee
I---------+-
0
'"w-'
"'"
iii
0'"
w
-'
""'
iii
'"o
'01------1-
~
I
'"
I,
'0--·-I"
---
"
50
L-_~
'50
'00
LOAD CAPACITANCE {pFl
_I
0
0
200
I
• I_
I
'"
51
..
------ I ------
0
0
o
30 pF
'5
~
o
oL-_ _L -_ _L -_ _
" I.,ov
CL
25
50
75
AMBIENT TEMPERATURE. {"Cl
8-23
AFN-00204B-06
inter
8212
8-BIT INPUT/OUTPUT PORT
• Fully Parallel8-Bit Data Register and Buffer
• Service Request Flip-Flop for
Interrupt Generation
• 3.6SV Output High Voltage for
Direct Interface to 8008, 8080A, or
808SA CPU
• Low Input Load Current -
• Asynchronous Register Clear
.2SmA Max.
• Replaces Buffers, Latches and
Multiplexers in Microcomputer Systems
• Three State Outputs
• Outputs Sink 1SmA
• Reduces System Package Count
The 8212 input/output port consists of an 8-bit latch with 3-state output buffers along with control and device selection
logic. Also included is a service request flip-flop for the generation and control of interrupts to the microprocessor.
The device is multi mode in nature. It can be used to implement latches, gated buffers or multiplexers. Thus, all of the
principal peripheral and input/output functions of a microcomputer system can be implemented with this device.
PIN CONFIGURATION
LOGIC DIAGRAM
SERVICE A~UEST FF
os,
vee
MO
INT
01,
01.
DO,
DO.
01 2
01 7
00 2
00 7
01 3
DI.
00 3
DO.
01.
01 5
DO.
00 5
STe
CLR
GNO
OS2
IT> os,
[i]>
oS2
[[> Mo
-----t- STB ----+--;_J
OUTPUT
BUFFER
IT> 0', - - - - - - - - - + + t
OATA LATCH
[B>o', - - - - - - - = - + t
Vo'3 - - - - - - - - - - t - + t
[E> D '. - - - - - - - - I - + t
PIN NAMES
GD ~'s - - - - - - - + - H
IT> D '6 - - - - - - - - - 7 - - H
~
D', - - - - - - - - + + 1
0> D'B ----------'--+i
DOsIE>
IE> Cl R - - - - - 4
8-24
AFN-00731 A-o,
8212
FUNCTIONAL DESCRIPTION
Service Request Flip-Flop
Data Latch
The (SR) flip-flop is used to generate and control
interrupts in microcomputer systems. It is asynchronously set by the CLR Input (active low). When the (SR) flipflop is set it Is In the non-Interruptl!lg state.
The 8 flip-flops that make up the data latch are of a "0"
type design. The output (0) of the flip-flop will follow the
data Input (0) while the clock Input (C) Is high. Latching
will occur when the clock (C) returns low.
The output of the (SR) flip-flop (0) is connected to an
inverting input of a "NOR" gate. The other Input to the
"NOR" gate is non-inverting and Is connected to the
device selection logic (OS1 • OS2). The output of the
"NOR" gate (00) Is active low (interrupting state) for
connection to active low Input priority generating circuits.
The latched data Is cleared by an asynchronous reset
Input (CIA). (Note: Clock (C) Overrides Reset (CLR).)
Output Buffer
The outputs of the data latch (0) are connected to 3-state,
non-Inverting output buffers. These buffers have a
common control line (EN); this control line either enables
the buffer to transmit the data from the outputs of the data
latch (0) or disables the buffer, forcing the output Into a
high Impedance state. (3-state)
SERVICE REQUEST FF
\
The high-impedance state allows the designer to connect
the 8212 directly onto the microprocessor bl-directional
data bus.
[i> MD
----+H~rt'
[j) STa -..-----i_~
Control Logic
Il> D" --------++1
The 8212 has control inputs OS1, OS2, MO and STB.
These inputs are used to control device selection, data
latching, output buffer state and service request flip-flop.
DATA LATCH
[Z> D '3 --------r-+1
DS1, DS2 (Device Select)
These 2 inputs are used for device selection. When OS1 Is
low and OS2 is high (OS1 • OS2) the device is selected. In
the selected state the output buffer is enabled and the
service request flip-flop (SR) is asynchronously set.
IE> D '. --------+-+1
I)]> D 's --------++1
MD (Mode)
I)]> D '6 --------;--+1
This input is used to control the state of the output buffer
and to determine the source of the clock input (C) to the
data latch.
[lg> D '7 --------+-+1
When MO is high (output mode) the output buffers are
enabled and the source of clock (C) to the data latch is
from the device selection logic (OS1 • OS2).
§>D'8-------~+1
When MO is low (input mode) the output buffer state is
determined by the device selection logic (OS1 • OS2) and
the source of clock (C) to the data latch.ls the STB
(Strobe) input.
STa . MO
o
,,
, 0
o
o
STB (Strobe)
This input is used as the ciock (C) to the data latch for the
input mode MO = 0) and to synchronously reset the
service request flip-flop (SR).
·1
(08,-0821
3·STATE
DATA LATCH
0,
,o,
,,
r
(151;-0121 STa
DATA
DUTEClJAJLS elR
3·STATE
o •
• 0
o
o
DATA LATCH
DATA LATCH
DATA IN
DATA IN
DATA IN
.
o
~
,
,
·SR: INT
,
1
, 0 • , I 0
·;-·~tg
. 0
•
':""'\-.
"
1
I 0'
-INTERNAL SR FLIP· FLOP
CLR - RESETS DATA LATCH
SETS SR FLlp·FLOP
INO EFFECT ON OUTPUT BUFFERI
Note that the SR flip-flop is negative edge triggered.
8-25
AFN-00731 Ao02
8212
Applications of the 8212 ..... For
Microcomputer Systems
I
II
III
IV
Basic Schematic Symbol
Gated Buffer
BI-Directlonal Bus Driver
Interrupting Input Port
V
Interrupt Instruction Port
VI
Output Port
'
VII '8080A,$,tatus Latch
VIII 8085A'-Address Latch
1. Basic Schematic Symbols
showing the system input or output as a system bus (bus
containing 8 parallel lines). The output to the data bus is
symbolic In referencing 8 parallel lines.
Two examples of ways to draw the 8212 on system
schematics - (1) the top being, the detailed view showing
pin numbers, and (2) the bottom being the symbolicview
BASIC SCHEMATIC SYMBOLS
OUTPUT DEVICE
INPUT DEVICE
11
11
01
9
16
18
STB
DO
8212
~
4
6
8
10
15
01 STB DO
:
(DETAILED)
17
19
Vee
GND
INPUT
STROBE----;:=L...,
FLAG
.._..c:::;~-- OUTPUT,
SYSTEM
INPUT
SYSTEM
OUTPUT
(SYMBOLIC)
GND
DATA BUS
II. Gated Butter (3-State)
GATED BUFFER
The simplest use of the 82121s that of a gated butter. By
tying the mode signal low and the strobe input high, the
data latch is acting as a straight through gate. The output
buffers are then enabled from the device selection logic
DS1 and DS2.
'
vcc--~-----.---~
STB
INPUT
DATA,
When the device selection logic is false, the outputs are 3state.
'
8212
(250.AI
OUTPUT
DATA
(15mA)
(3.65V MIN)
~----
i3
~!
60
a:
"
I-
~
-200
40
0
~
-250
-300
-3
-2
+1
-1
+2
°o~--~~~-----L-------L------J
+3
INPUT VOLTAGE (VI
OUTPUT "LOW" VOLTAGE (V)
OUTPUT CURRENT VS.
OUTPUT "HIGH" VOLTAGE
DATA TO OUTPUT DELAY
VS. LOAD CAPACITANCE
50
Vee
~ ~5.0V
TA'= 25 C
U
40
~-t
30
r-----:.-
c
>-
~
0
i
I-
!
~
i
:>
0
0
..
20
I-
~
0
--
~--
\~"'-_-_1.~ f...-
-r--r--
!
~
10 - . ,
i
I
00
DATA TO OUTPUT DELAY
VS. TEMPERATURE
WRITE ENABLE TO OUTPUT DELAY
VS. TEMPERATURE
Vee = +S.OV
!
~0
18
I-
I
30
i
I
!
~
~
I-
:>
0
0
Iw
-'
16
....
ffi
t-_
0
0
I-
35
>-
!
...
14
I-
0
ST~<
os,
ii:
i:
25
50
75
r-=:.-
os;<~
-
--
.
t+_
t __
t----
15
10
-25
100
f----
!
l-
12
~'\ .. %
25
20
--,.., ---"
~!..
I
w
10
-25
300
40
~~----+-----+-----+------+-----~
~
250
LOAD CAPACITANCE (pFJ
Vee =+5.0V
>-
~o
150
100
OUTPUT "HIGH" VOLTAGE (V)
22r-----r-----r-----~----~----,
:5
i
50
i
25
50
75
100
TEMPERATURE reI
TEMPERATURE (OCI
8-31
AFN-00731A-oB
8212
A.C. CHARACTERISTICS
Symbol
o·c to HO·C. Vee = +5V ± 5%
TA =
Limits
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
ns
30
tpw
Pulse Width
tPD
Data to Output Delay
30
ns
Note 1
tWE
Write Enable to Output Delay
40
ns
Note 1
ns
tSET
Data Set Up Time
15
tH
Data Hold Time
20
tR
Reset to Output Delay
40
ns
Note 1
ts
Set to Output Delay
30
ns
Note 1
tE
Output Enable/Disable Time
45
ns
Note 1
te
Clear to Output Delay
55
ns
Note 1
CAPACITANCE*
Symbol
F = 1MHz. VBIAS
ns
= 2.5V. Vee = +5V. TA = 25·C
Limits
Test
Typ. Max.
CIN
051 MD Input Capacitance
9pF 12pF
CIN
052. CK. ACK. DI1-Dls
Input Capacitance
5pF 9pF
COUT
001-DOs Output Capacitance
8pF 12pF
'This parameter is sampled and not 100% tested.
SWITCHING CHARACTERISTICS
Conditions of Test
Input Pulse Amplitude = 2.5V
Input Rise and Fall Times 5ns
Between 1V and 2V Measurements made at 1.5V
with 15mA and 30pF Test Load
Test Load
l5mA &30pF
Vee
Note 1:
Test
CL*
R1
R2
tPD. tWE. tA. ts. tc
30pF
3000
6000
tEo ENABLE!
30pF
10KO
1KO
tEo ENABLE I
30pF
3000
6000
tEo DISABLE!
5pF
3000
6000
tEo DISABLEI
5pF
10KO
1KO
TO
D.U.T.
"INCLUDING JIG & PROBE CAPACITANCE
'Includes probe and jig capacitance.
8-32
AFN-00731A-09
8212
TIMING DIAGRAM
DATA
1.5V'J:'"- -
-
-
-
-
-
-
~tpw
------'.
"I"
1,-STa or l5S1 • DS2
1.5vl
- - -....'
_______
l-_tw_E::J
OUTPUT
____________
tH
OUTPUT
../1'---~
....
1._5V_ _ _ _ _.,...-_ _
r _____ - - -
.....IX. .
1_.5_V_ _ _ _ _ _ _ __
1.5V!
-------' l
-Y,.5V
\1.5V
tE -1 r _
-------~
~E~~~WL _ ~-t-D-+----
;::::::::::;::~
.
Itpw~
1.5V\
11.5V
tC"I, ____ _
I.
DO
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _) (....
1.5_V_ _ _ _ __
OATA
15VX----------y1.5V
r~aorOO1.-D-S-2---.,...-----~~--------1-.5~V~~
_ _ _ _ _ J~
__
tSET - - -
'I~
tH
__ _
--I
_ _ _ _ _ _ _ _ _ _ _ _ _ ___
_______~_t_PD_j r
'OUTPUT
STa
_ _ _ _ _ _ _ _ _ --'\
______
___________ _
....
1._5V_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
-J~
Ltpw
------.--
....
1._5V______________________________
--~-----""\
NOTE: ALTERNATIVE TEST LOAD
-=ci
vec'OK
OUT
eL
"::" ·'K
8-33
AFN-ClO731A-10
inter
8214/3214*
PRIORITY INTERRUPT CONTROL UNIT
• 8 Priority Levels
• Fully Expandable
• Current Status Register
• High Performance (50 ns)
• Priority Comparator
• 24·Pin Dual In·Llne Package
The Intel~ 8214 is an 8·level priority Interrupt control unit (PICU) designed to simplify interrupt·driven microcomputer
systems.
The PICU can accept 8 requesting levels; determine the highest priority. compare this priority to a software controlled
current status register and issue an interrupt to the system along with vector information to identify the service
routine.
The 8214 is fully expandable by the use of open collector interrupt output vector information. Control signals are also
provided to simplify this function.
The PICU is designed to support a wide variety of vectored interrupt structures and reduce package count in Interrupt·
driven microcomputer systems.
'Note: The specifications for the 3214 are Identical with those for the 8214.
PIN CONFIGURATION
LOGIC DIAGRAM
IE>
·0.,
I1!>ETlG--
Ees
~
Ra
[!D
R,
A.[D
I!!> R,
I!!> ;;:;
iI,[D
.,
A;
SGS
A,
'NT
R,
elK
A,
8214
ElR
Vee
REQUEST ACTIVITY
I!!> R;
~
~
~
R;
'NTE
R,
A;;
A,
A,
A,
R,
II> B,
ElA
ENLG
l?D
GNO
ETLG
A,
PIN NAMES
A,11!>
"-As
I:!> B,
ID s:;
[D SGS
PRIOR lTV
COMPARATOR
EcS
CC>'NTE-----------------~
OC>
~--------------------------~
INPUTS
RO-A?
REQUEST LEVELS IR7 HIGHEST PRIORITY)
80-82
CURRENT STATUS
iGi
STATUS GROUP SELECT
ECi
ENABLE CURRENT STA'JUS
INTE
INTERRUPT ENABLE
ill
CLOCK UNT F·FI
ENABLE lEVEL READ
ENABLE THIS LEVEL GROUP
ELA
ETLG
.....,
OUTPUTS:
M
REQUEST LEvl:LS
}-OPEN
INTEARUPT(ACT. LOW)
COLLECTOR
ENLO
ENABLE NEXT LEVEL GROUP
8-34
AFN·00210A-ol
821413214
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias. . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . • . . . . . .. O°C to 75°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _65°C to +160°C
All Output and Supply Voltages. . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . .. -0.5V to +7V
All Input Voltages .......•... '. . . . . . . . . . . . . . . . . • . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . -1.0V to +5.5V
Output Currents . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . ." 100 mA
'COMMENT: Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specifi·
cations is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliabilitY.
D.C. AND OPERATING CHARACTERISTICS
TA = o°c to +70°C, VCC = 5V ±5%.
Symbol
Parameter
Vc
Input Clamp Voltage (all inputs)
IF
Input Forward Current:
ETLG input
all other inputs
IR
Input Reverse Current:
ETLG input
all other inputs
Vil
Input LOW Voltage:
all inputs
VIH
Input HIGH Voltage:
all inputs
Icc
Power Supply Current
VOL
Output LOW Voltage:
all outputs
VOH
Output HIGH Voltage:
ENLG output
los
Short Circuit Output Current: EN LG output
ICEX
Output Leakage Current: INT and A o ·A2
Min.
Limits
Typ.[l]
-.15
-.08
Max.
Unit
Conditions
-1.0
V
Ic=-5mA
-0.5
-0.25
mA
mA
VF=0.45V
80
40
p.A
p.A
VR=5.25V
0.8
V
VCC=5.0V
V
VCC=5.0V
2.0
90
130
mA
See Note 2.
.3
.45
V
10l =15mA
-55
mA
VOs=OV, Vcc=5.0V
100
p.A
VCEx=5.25V
2.4
3.0
-20
-35
V
10H=-lmA
NOTES:
1. Typical values are for T A = 25° C, VCC = 5.0V.
2. 80.82, SGS, ClK, RO·R4 grounded, all other inputs and all outputs open.
8-35
AFN·OO210A-02
8214/3214
A.C. CHARACTERISTICS
TA = o°c to +70°C, VCC = +5V ±5%
Min.
limits
Typ.(1)
tCY
ClK Cycle Time
80
50
ns
tpw
ClK, ECS, I NT Pulse Width
25
15
ns
tlSS
INTE Setup Time to ClK
16
12
ns
tlSH
INTE Hold Time after ClK
20
10
ns
tETCS[21
ETlG Setup Time to ClK
25
12
ns
tETCH[21
ETlG Hold Time After ClK
20
10
ns
tECCS[21
ECS Setup Time to ClK
80
25
ns
tECCH[31
ECS Hold Time After ClK
tECRS[31
ECS Setup Time to ClK
tECRH[31
ECS Hold Time After ClK
0
tECSS[21
ECS Setup Time to ClK
75
tECSH[21
ECS Hold Time After ClK
Symbol
---
Parameter
Max.
0
110
Unit
ns
70
ns
70
n.
ns
0
tocs[21
SGS and Bo·B2 Setup Time to ClK
70
tOCH[21
SGS and Bo ·B 2 Hold Time After ClK
0
tRCS[31
Ro·R 7 Setup Time to ClK
90
tRCH[31
RO·R7 Hold Time After ClK
0
tiCS
INT Setup Time to ClK
55
tCI
ClK to INT Propagation Delay
tRIS[41
RO·R7 Setup Time to INT
10
0
tRIH[41
Ro ·R7 Hold Time After INT
35
20
tRA
Ro ·R7 to AO·A 2 Propagation Delay
80
100
ns
tELA
E lR to Ao ·A 2 Propagation Delay
40
55
ns
tECA
ECS to Ao ·A 2 Propagation Delay
100
120
ns
tETA
ETlG to Ao·A2 Propagation Delay
35
70
ns
tOECS[41
SGS and Bo·B2 Setup Time to ECS
15
10
tOECH[41
SGS and Bo ·B2 Hold Time After ECS
15
10
tREN
Ro ·R 7 to EN lG Propagation Delay
45
70
ns
tETEN
ETlG to ENlG Propagation Delay
20
25
ns
tECRN
ECS to ENlG Propagation Delay
85
90
ns
tECSN
ECS to ENlG Propagation Delay
35
55
ns
50
ns
ns
55
ns
35
ns
ns
15
25
ns
ns
ns
ns
ns
CAPACITANCE[S)
Symbol
Min.
limits
Typ.l11
Max
Unit
CIN
Input Capacitance
5
10
pF
COUT
Output Capacitance
7
12
pF
Parameter
Test Conditions:
VSIAS = 2.5V, vcc
=5V, TA =25°C, f = 1 MHz
NOTE 5. This parameter is periodically sampled and not 100% tested.
8-36
"FN·00210"-o3
821413214
WAVEFORMS
x-------
)(-----------------)(
._-----,
ETlG
INTE
-------
tRCH
tRCS
;---- ---1..-------
--"'\
_JX
1(.... _--------1
tETes
tETCH
-------1--- --------y -X----- ----------'I~
r---- "\
----------.
.
__
J
-------JF PII
'oes
tecss
ECRS
'ECCS
~
--1----- ------- ----- --- -----~--
'RA
tecA
'ECRH
teecH
'<:V
j
~
r-----"'\
__________ J
'<:1
'PW
'1"---
----------t--___ X- ---------1-------"\
~
--- f-.
tecsN
'I
tecsH
\
'lj
'ECRN
~---
tlSH
'oCH
1:;i
--
-.II
'ISS
'~
~'oECS _~CH
ENLG
:I~-----~j
tRIS
tRIH
tELA
...
-"'\
'--------
tETEN
tREN
_____....Jx____________________ _
-----------------"\
NOTES:
(1) Typical values are for T A
~ 25'e ,Vee ~ 5,QV,
(2) Required for proper operation if ISE is enabled during next clock pulse.
(3) These times are not required for proper opera'tion but for desired change in interrupt flip-flop.
(4) Required for new request or status to be properly loaded.
Test Load Circuit
Test Conditions
VCC
Input pulse amplitude: 2.5 volts.
Input rise and fall times: 5 ns between 1 and 2 volts.
300"
Output loading of 15 mA and 30 pf.
OUTo---~--------------+
Speed measurements taken at the 1.5V levels.
30 pf
8-37
..on
AFN-00210A-04
inter
8216/8226
4·BIT PARALLEL BIDIRECTIONAL BUS DRIVER
• 3.65V Output High Voltage for Direct
Interface to 8080 CPU
• Data Bus Buffer Driver for 8080 CPU
• ..ow Input Load Current - 0.25 mA
Maximum
• 3·State Outputs
• High Output Drive Capability for
Driving System Bus
• Reduces System Package Count
The 821618226 Is a 4-blt bidirectional bus driver/receiver_ All Inputs are low power TIL compatible. For driving MOS. the
DO outputs provide a high 3.65V "OH, and for high capacitance terminated bus structures, the DB outputs provide a
high 50 mA 10L capability. A non-Inverting (8216) and an inverting (8226) are available to meet a wide variety of applications for buffering In microcomputer systems.
·Nole: The speclflcatlone for Ihe 321613226 are identical with those for the 821618226,
PIN CONFIGURATION
cs
LOGIC DIAGRAM
LOGIC DIAGRAM
8216
8226
Vee
00.
DiiN
os.
00,
0'0
0'.
0'0
01,
00.
00,
0',
0',
08,
00,
08,
GNO
0',
01, •
.----001,
DB,
00,
0',
0',
.----008,
08,
00,
PIN NAMES
D0,
01,
0',
.---0
08,
DIo.otl,
DATA BUS
II·DIRECTIONAL
0'0"'0,
DATA INPUT
00.,00
DATA OUTPUT
O'EN
DATA IN ENAILE
DIRECTION CONTROL
i!I
CHIP SELECT
oo'~---+--~.t-~--~
~
'-------+......- - - - - - 0 a
OlEN
__"""______..J
8-38
DB,
00,
~-----+~------~a
OlEN
DB,
DO,
DO,
O~
.----0
DB.
o-__......_ _ _....J
AFN-Q0733A-Ol
821818226
FUNCTIONAL DESCRIPTION
Microprocessors like the 8080 are MOS devices and are
generally capable of driving a single TTL load. The same is
true for MOS memory devices. While this type of drive is
sufficient in small systems with few componenu, quite often
it is necessary to buffer the microprocessor and memories
when adding components or expanding to a multi·board
system.
01. ()O------p_-+-.,
08.
DO. <>---t--G--+--'
01, o---t--t>--+---,
08,
DO,o---t--G--+--'
The 8216/8226 is a four bit bi-directional bus driver specif·
ically designed to buffer microcomputer system components.
01, o---t--t>--+---,
Bidirectional Driver
DO,o---t--G--+--'
08,
Each buffered line of the four bit driver consists of two
separate buffers that are tri-state in nature to achieve direct
bus Interface and bi-directional capability. On one side of
the driver the output of one buffer and the input of another
are tied together (DB), this side is used to interface to the
system side components such as memories, 1/0, etc., because its interface is direct TTL compatible and it has high
drive (50mA). On the other side of the driver the inputs
and outputs are separated to provide maximum flexibility.
Of course, they can be tied together so that the driver can
be used to buffer a true bi-directional bus such as the 8080
Data Bus. The DO outputs on this !ide of the driver have a
special high voltage output drive capability (3.65V) so that
direct interface to the 8080 and 8008 CPUs is achieved with
an adequate amount of noise immunity (350mV worst case).
01,
o---t---t~-+---..,
DB,
DO, C>---t--c.I--+----'
' - - - - - t.....- - - - o cs
OlEN
(a) 8216
01.
DO.
01,
Control aatlng OlEN, CS
DO,
The CS input is actually a device select. When it is "high"
the output drivers are all forced to their high-impedance
state. When it is at "zero" the device is selected (enabled)
and the direction of the data flow is determined by the
OlEN input.
01,
DO,
The OlEN input controls the direction of data flow (see
Figure 1) for complete truth table. This direction control
is accomplished by forcing one of the pair of buffers into its
high impedance state and allowing the other to transmit its
data. A simple two gate circuit is used for this function.
The 8216/8226 is a device that will reduce component count
in microcomputer systems and at the same time enhance
noise immunity to assure reliable, high performance operation.
01,
DO,
(b) 8226
OlEN CS
0
0
0
,
, t+,
t-+
01 . DB
DB· 00
} HIGH IMPEDANCE
Figure 1. 821818228 Logic Diagrams
8-39
AFN-00733A-Q2
821618226
WAVEFORMS
A.C. CHARACTERISTICS
Limits
Typ.ll)
Max.
U"nit
TpOl
Input to Output Delay DO Outputs
15
25
ns
CL=30pF,R,=300n
R2=600n
Tp02
Input to Output Delay DB Outputs
8216
" C L=300pF, R 1=90n
Symbol
Parameter
Min.
Conditions
19
30
ns
8226
16
25
ns
R2 = 180n
8216
42
65
ns
(Note 2)
8226
36
54
ns
(Note 3)
16
35
ns
(Note 4)
Output Enable Time
Te
Output Disable Time
TO
Test Load Circuit
T.st Conditions:
Input pulse amplitude of 2.5V.
Input rise and fall times of 5 ns between 1 and 2 volts.
Output loading is 5 mA and 10 pF.
Speed measurements are made at 1.5 volt levels.
",
OUT
O---T------+
",
CAPACITANCEIII
Symbol
Min.
Parameter
Limits
Typ.(1)
Max.
Unit
pF
6
8
10
13
18
pF
CIN
Input Capacitance
4
COUT!
Output Capacitance
CoUT2
Output Capacitance
Test Conditions
NOTes:
1.
2.
3.
4.
S.
pF
VBIAS = 2.5V, Vee = 5.0V, TA = 25°C, f = 1 MHz.
Typical values are for TA • 25°C, VCC = 6.0V.
00 Outputs. CL· 3OpF, R, ·300110 K.!l, R2· 180/1K.!l; 08 Outputs. CL = 300pF, R, = 90110 KO. R2 = 180/1 KO.
00 Outputs, CL = 3OpF, R, • 3OO/10K.!l, R2 = 6OOI1K; DB Outputs, CL =300pF, R, =90/l0KO, R2= 180/1 KO.
00 Outputs. CL· 6pF, R, = 3OO/10KO, R2· 60011 KO; DB Outputs, CL = 6pF, R, = 90/10 KO, R2 = 180/1 KO.
This parameter i. periodically sampled and not 100% tested.
8-40
AFN-«l733A-03
8216/8226
ABSOLUTE MAXIMUM RATINGS·
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent dam~ge to the
device. This is a stress rating only and functional opera·
tion of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Temperature Under Bias . . . . . . . . . . . . . O°C to 70°C
Storage Temperature .. . . . . . . . . .. -65°C to +150°C
All Output and Supply Voltages. . . . . ..
-0.5V to +7V
All Input Voltages . . . . . . . . . . . . . . . -1.0V to +5.5V
Output Currents . . . . . . . . . . . . . . . . . . . .. 125 mA
D.C. AND OPERATING CHARACTERISTICS
Symbol
Parameter
Min.
Limits
Typ.
Max.
Unit
Conditions
IFI
Input Load Current OlEN, CS
-0.15
-.5
mA
VF =0.45
IF2
Input Load Current All Other Inputs
-0.08
-.25
mA
VF=0.45
IRI
Input Leakage Current OlEN, CS
80
JJ.A
VR =5.25V
IR2
Input Leakage Current 01 Inputs
40
JJ.A
VR =5.25V
Ve
Input Forward Voltage Clamp
-1
V
Ie = -5mA
VIL
Input "Low" Voltage
.95
V
20
100
JJ.A
95
130
mA
V
VIH
Input "High" Voltage
1101
Output Leakage Current
(3-State)
2.0
lee
Power Supply Current
VOLI
Output "Low" Voltage
VOL2
Output "Low" Voltage
VOHI
Output "High" Voltage
3.65
VOH2
Output "High" Voltage
2.4
lOS
Output Short Circuit Current
-15
-30
-35
-75
DO
DB
8216
85
120
mA
0.3
.45
V
8216
0.5
.6
V
DB Outputs IOL=55mA
8226
0.5
.6
V
DB Outputs 10L =50mA
4.0
V
DO Outputs 10H = -lmA
3.0
V
DB Outputs 10H = -10mA
8226
NOTE: Tvpical values are for TA
=
Vo = 0.45V /5.25V
-65
-120
mA
mA
DO Outputs IOL=15mA
DB Outputs 10L =25mA
-
DO Outputs Vo == OV,
DB Outputs Vec=5.0V
25°e, Vee = 5.0V.
8-41
AFN.O()733A-04
821618226
APPLICATIONS OF THE 8216/8226
8080 Data Bus Buffer
The 8080 CPU Data 8us is capable of driving a single TTL
load and is more than adequate for small, single board sys·
tems. When expanding such a system to more than one board
to increase 1/0 or Memory size, it is necessary to provide a
buffer. The 8216/8226 is a device that is exactly fitted to
th is appl ication.
The 8216/8226 can be used in a wide variety of other buf·
fering functions in microcomputer systems such as Address
Bus Drivers, Drivers to peripheral devices such as printers,
and as Drivers for long length cables to other peripherals or
systems.
Shown in Figure 2 are a pair of 8216/8226 connected di·
rectly to the 8080 Data Bus and associated control signals.
The buffer is bi·directional in nature and serves to isolate the
CPU data bus.
BUSEN
15
On the system side, the DB lines interface with standard
semiconductor liD and Memory components and are com·
pletely TTL compatible. The DB lines also provide a high
drive capability (SOmA) so that an extremely large system
can be dirven along with possible bus termination networks.
~l
Do
0,
0,
12
",
On the 8080 side the 01 and DO lines are tied together and
are directly connected to the 8080 Data Bus for bi·directional
operation. The DO outputs of the 8216/8226 have a high
voltage output capability of 3.65 volts which allows direct
connection to the 8080 whose minimum input voltage is
3.3 volts. It also gives a very adequate noise margin of
350mV (worst case).
DB,
,.
8216
8226
11
DB,
13
DB,
1.
CS
SYSTEM
DATA
8080
BUS
15
01 OlEN
0,
DB
DO
DB,
DB,
0,
8216
8226
The OlEN inputs to 8216/8226 is connected directly to the
8080. DIEN is tied to DBIN so that proper bus flow is
maintained, and CS is tied to BUSEN so that the system
side Data Bus will be 3-stated when a Hold request has been
acknowledged during a DMA activity.
0,
11
10
DB,
12
0,
1.
13
DB,
cs
Memory and 1/0 Interface to a Bidirectional Bus
In large microcomputer systems it is often necessary to provide Memory and liD with their own buffers and at the same
time maintain a direct, common interface to a bi·directional
Data Bus. The 8216/8226 has separated data in and data
out lines on one side and a common bi·directional set on the
other to accomodate such a function.
FIgure 2. 8080 Data BUI Buffer
Shown in Figure 3 is an example of how the 8216/8226 is
used in this type of application.
MEMORY
I/O
The interface to Memory is simple and direct. The memories
used are typically Intel® 8102,81 02A, 8101 or 8107B·4 and
have separate data inputs and outputs. The 0 I and DO lines
of the 8216/8226 tie to them directly and under control of
the MEMR signal, which is connected to the OlEN input,
an interface to the bi·directional Data Bus is maintained.
The interface to liD is similar to Memory. The 110 devices
used are typically Intel® 8255s, and can be used for both
input and output ports. The 110 R signal is connected di·
rectly to the 01 EN input so that proper data flow from the
110 device to the Data Bus is maintained.
FIgure 3. Memory and 110 Intertace
to a BIdIrectional BUI
8-42
AFN-00733A-05
8282/8283
OCTAL LATCH
•
Address Latch for iAPX 86,88,
MCS·80™, MCS·85™, MCS·48™ Families
•
3·State Outputs
•
High Output Drive Capability for
Driving System Data Bus
•
20·Pin Package with 0.3" Center
•
Fully Parallel 8·Bit Data Register and
Buffer
•
•
Transparent during Active Strobe
No Output Low Noise when Entering
or Leaving High Impedance State
The 8282 and 8283 are 8-bit bipolar latches with 3-state output buffers. They can be used to implement latches, buffers,
or multiplexers. The 8283 inverts the input data at its outputs while the 8282 does not. Thus, all of the principal peripheral and input/output functions of a microcomputer system can be implemented with these devices.
01 0
VCC
01 1
01 2
01 0
VCC
000
01 1
000
001
01 2
001
01 3
002
01 3
002
01 4
003
01 4
003
01 5
004
01 5
004
01 6
005
01 6
005
01 7
006
01 7
006
OE
007
OE
007
GNO
STS
GNO
STS
Figure 1. 8282 Pin Configuration
Figure 2_ 8283 Pin Configuration
8-43
intJ
828218283
r-------,
8282
&-__
IOQ
:
I
I
I
I
I
L ______ _
L______ _
Figure 3. Logic Diagrams
PIN DEFINITIONS
Pin
OPERATIONAL DESCRIPTION
D.scrlptlon
STB
STROBE (Input). STB Is an Input control
pulse used to strobe data at the data Input
pins (Ao-A7) Into the data latches. This
signal Is active HIGH to admit Input data.
The data Is latched at the HIGH to LOW
transition of STB.
OE
OUTPUT ENABLE (Input). C5"E Is an Input
control signal which when active LOW
enables the contents of the data latches
onto the data output pin (Bo-B7). OE being
Inactive HIGH forces the output buffers to
their high Impedance state.
DATA INPUT PINS (Input). Data presented
at these pins satisfying setup time requirements when STB Is strobed and
latched Into the data Input latches.
01 0- 01 7
000-00 7
(8282)
000-1)(57
(8283)
The 8282 and 8283 octal latches are 8·bit latches with
3·state output buffers. Data having satisfied the setup
time requirements is I.atched Into the data latches by
strobing the STe line HIGH to LOW. Holding the STB
line In its active HIGH state makes the latches appear
transparent. Data Is presented to the data output pins by
activating the ~ Input line. When OE Is Inactive HIGH·
the output buffers are In their high Impedance state.
Enabling or disabling the output buffers will not cause
negatlve·golng transients to appear on the data output
bus.
DATA OUTPUT PINS (Output). When OE Is
true, the data In the data latches Is presented as Inverted (8283) or non·lnverted
(8282) data onto the data output pins.
8-44
AFN oo727B
828218283
ABSOLUTE MAXIMUM RATINGS·
'NOTICE: Stresses above those listed under"AbsoluteMaxlmum Ratings"
may cause permanent damage to the device. This is astress rating only and
Temperature Under Bias ................. O·C to 70·C
Storage Temperature .••..•....... -65·C to + 150·C
All Output and Supply Voltages ........ - 0.5V to + 7V
All Input Voltages .................. - 1.0V to + 5.5V
Power Dissipation .........•................ 1 Watt
D.C. CHARACTERISTICS
= 5V ± 10%, TA = ooe to
Conditions: Vee
Symbol
Vc
e
Parameter
Min
Max
Units
-1
V
Input Clamp Voltage
Test Conditions
Ic = -5 rnA
Icc
Power Supply Current
160
rnA
IF
Forward Input Current
-0.2
rnA
VF = 0.45V
50
,..A
VR = 5.25V
V
10L = 32 rnA
IR
Reverse Input Current
VOL
Output Low Voltage
VOH
Output High Voltage
10FF
Output Off Current
VIL
Input Low Voltage
V IH
Input High Voltage
C IN
NOTE:
70 0
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
1.
.45
2.4
V
10H = -5 rnA
± 50
,..A
VOFF = 0.45 to 5.25V
0.8
V
.Vcc= 5.0V
See Note 1
V
Vcc=5.0V
See Note 1
2.0
Input Capacitance
12
F= 1 MHz
V BIAS = 2.5V, Vcc= 5V
TA =25·C
pF
Output Loading IOL=32mA,loH =-5mA, C L=300pF.
A.C. CHARACTERISTICS
= 5V ± 10%, TA = ooe to
Conditions: Vee
Loading: Outputs Symbol
TIVOV
TSHOV
70 0
e
10L = 32 rnA, IOH = - 5 rnA, CL = 300 pF
Parameter
Input to Output Delay
-Inverting
-Non-Inverting
STB to Output Delay
-Inverting
- Non·lnverting
Min
Max
Units
5
5
22
30
ns
ns
10
10
40
45
ns
ns
Test Conditions
(See Note 1)
TEHOZ
Output Disable Time
5
18
ns
TELOV
Output Enable Time
10
30
ns
TIVSL
Input to STB Setup Time
0
ns
TSLIX
Input to STB Hold Time
25
ns
TSHSL
STB High Time
15
ns
NOTE: 1. See waveforms and test load circuit on following page.
8-45
AFN 00727B
828218283
WAVEFORMS
INPUTS
\1 _______J/~~
\V _____________________________
______-JJ\~
-TIVSL-!-TSLIX.
V
STa
\
/
~
--J!----+TSHSL~ ' - - - - - - - - - - - - - - - - - - - - - - -
V
\
/
-TIVOV-
_
\
TEHOZ ~
--+----'"""\/r-------------'
OUTPUTS
~
NOTE: 1.8283 ONLY -
I.(\
TSHOV
~
TELOV- }
>- _____ _
VOH-.W
_ _ _ _ __
1\_ _ _ __
AVOL+.W
SEE NOTE 1
OUTPUT MAY BE MOMENTARILY INVALID FOLLOWING THE HIGH GOING STe TRANSITION.
2. ALL TIMING MEASUREMENTS ARE MADE AT 1.5V UNLESS OTHERWISE NOTED,
Figure 4. Timing Diagram
1.5V
1.5V
52.71l
1801l
331l
OUT 0---<
2.14V
OUTe>--
1300PF
1300 pF
3·STATE TO VOL
3·STATE TO VOH
OUT~
1300 pF
SWITCHING
Figure 5. Output Test Load Circuits
8·46
AFN 007278
inter
8282/8283
50
8283
40
&l
I/)
z
...>-c
III
CI
20
pF LOAD
50
8282
10
pF LOAD
Figure 6. Output Delay vs. Capacitance
8-47
AFN 00727B
intel'
8286/8287
OCTAL BUS TRANSCEIVER
•
Data Bus Buffer Driver for iAPX 86,88,
MCS·80™, MCS·85™, and MCS·48™
Families
•
High Output Drive Capability for
Driving System Data Bus
•
Fully Parallel 8·Bit Transceivers
•
3·State Outputs
•
20·Pin Package with 0.3" Center
•
No Output Low Noise when Entering
or Leaving High Impedance State
The 8286 and 8287 are 8-bit bipolar transceivers with 3-state outputs. The 8287 inverts the input data at its outputs
while the 8286 does not. Thus, a wide variety of applications for buffering in microcomputer systems can be met.
AO
Vee
AO
A1
BO
A1
A2
B1
A2
Vee
So
B1
A3
B2
A3
B2
A4
B3
A4
B3
AS
B4
AS
B4
A6
Bs
A6
BS
A7
B6
A7
B6
OE
B7
OE
B7
GND
T
GND
Figure 1. 8286 Pin Configuration
T
Figure 2_ 8287 Pin Configuration
Intel Corporation Assumes No Responsibilty for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenses afa Implied.
@INTELCORPORATION, 1980
8-48
8286/8287
r-------,I
I
r-------,I
I
8286
I
8287
~
L-_~~ ........ !I L
I
I
Figure 3. Logic Diagrams
Table 1. Pin Description
~e~crlpllon
Pin
T
TRANSMIT (Input). T is an input control signal ul!ed to control the direction of the transceivers.
When HIGH, it configures the transceiver's Bo-B7 as outputs with ArrA7 as inputs. T LOW con·
figures Ao-A7 as the outputs with Bo-B7 serVing as the Inputs.
OE
OUTPUT ENABLE (Input). OE Is an input control signal used to enable the appropriate output
driver (as selected by T) onto its respective bus. This signal Is active LOW.
Ao-A7
LOCAL BUS DATA PINS (Input/Output). These pins serve to either present data to or accept data
from the processor's local bus depending upon the state of the T pin.
~-!!z (8286)
SYSTEM BUS DATA PINS (Input/Output). These pins serve to either present data to or accept
data from the system bus depending upon the state of the T pin.
Bo- B7 (8287)
FUNCTIONAL DESCRIPTION
The 8286 and 8287 transceivers are 8·bit transceivers with high impedance outputs. With T active HIGH and OE active
LOW, data at ~he Ao-A7 pins is driven onto the Bo-B7 pins. With T inactive LOW and OE active LOW, data at the Bo-B7
pins is driven onto the Ao-A7 pins. No output low glitchlng will occur whenever the transceivers are entering or leaving
the high impedance state.
8-49
AFN 01506A
8286/8287
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias ................. O°C to 70°C
Storage Temperature ............. - 65°C to + 150°C
All Output and Supply Voltages .... , ... - 0.5V to + 7V
All Input Voltages .................. - 1.0V to + 5.5V
Power Dissipation .......................... 1 Watt
*NOTICE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any -other conditions above
those indicated in the operational sections 01 this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
D.C. CHARACTERISTICS FOR 8286/8287
Conditions: Vee = 5V ±10% T A = 0° C to 70° C
Max
Units
Vc
Input Clamp Voltage
-1
V
Icc
Power Supply Current-8287
-8286
130
;60
mA
mA
IF
Forward Input Current
-0.2
mA
V F=0.45V
IR
Reverse Input Current
50
J.'A
V R= 5.25V
VOL
Output Low Voltage
.45
.45
V
V
IOL = 32 mA
IOL = 16 mA
VOH
Outpu1 High Voltage -B Outputs
-A Outputs
V
V
IOH=-5 mA
IOH=-1mA
IOFF
IOFF
Output Off Current
Output Off Current
V IL
Input Low Voltage
V IH
Input High Voltage
CIN
Input Capacitance
Symbol
NOTE: 1. B Outputs -
Min
Parameter
-B Outputs
-A Outputs
2.4
2.4
Test Conditions
le=-5mA
VOFF = 0.45V
VOFF = 5.25V
IF
IR
-A Side
-B Side
0.8
0.9
2.0
12
V
V
Vee = 5.0V, See Note 1
Vcc = 5.0V, See Note 1
V
Vce = 5.0V, See Note 1
pF
F= 1 MHz
V SIAS =2.5V, Vcc=5V
T A = 25°C
IOL = 32 mA, IOH = -5 mA, c L= 300 pF; A Outputs - IOL = 16 mA, IOH = -1 mA, c L= 100 pF.
A.C. CHARACTERISTICS FOR 8286/8287
Conditions: Vee = 5V ±10%, TA = O°C to 70°C
Loading: B Outputs A Outputs -
IOL = 32 mA, IOH = -5 mA, CL = 300 pF
IOL = 16 mA, IOH = -1 mA, CL = 100 pF
Symbol
Parameter
TIVOV
Input to Output Delay
Inverting
Non·lnverting
Min
Max
Units
Test Conditions
5
5
22
30
ns
ns
(See Note 1)
TEHTV
Transmit/Receive Hold Time
5
ns
TTVEL
Transmit/Receive Setup
10
ns
TEHOZ
Output Disable Time
5
18
ns
TELOV
Output Enable Time
10
30
ns
NOTE: 1. See waveforms and test load circuit on following page.
8-50
AFN 01506A
8286/8287
WAVEFORMS
t_________
INPUTS _ _
t~
1
0E _ _ _-
-
-
{
I, mm:1 ,
';
TEHOZ :. VOH _ .W TELOV-,
-<
~__________+I--}V:~~--+ . '. ._____
OUTPUTS
I~
TEHTV -
-!
~
TTVEL
______________________________________________-J)k~_______________
NOTE: 1. All timing measurements are made at 1.5V unless otherwise noted.
Figure 4. 8286/8287 Timing
'50
50
8287
40
.
[;!
z
S
..
"
10
200
400
800
800
1000
pF LOAD
pF LOAD
Figure 5. Output Delay vs. Capacitance
8-51
AFN 01506A
inter
8286/8287
1.SV
OUT
2.14V
1.5V
1 !-"
r
OUT
OOPF
1
l~
l
oUT
r
t·"
r
300PF
100PF
3·STATE TO VOL
3·STATE TO VOL
B OUTPUT
A OUTPUT
B OUTPUT
1.5V
1.SV
2.2BV
180\1
r
OUT 0 - - -
SWITCHING
8002
OUT
11411
OUT
300 pF
3·STATE TO VOH
3·STATE TO VOH
B OUTPUT
A OUTPUT
SWITCHING
A OUTPUT
Figure S. Test Load Circuits
8-52
AFN 01506A
8251 A/S2657
PROGRAMMABLE COMMUNICATION INTERFACE
• Synchronous and Asynchronous
Operation
• Asynchronous Baud Rate 19.2K Baud
• Synchronous 5·8 Bit Characters;
• Full Duplex, Double Buffered, Trans·
mitter and Receiver
Internal or External Character Synchro·
nization; Automatic Sync Insertion
• Error Detection Framing
• Asynchronous 5·8 Bit Characters;
Clock Rate-1, 16 or 64 Times Baud
Rate; Break Character Generation; 1,
1 Y2, or 2 Stop Bits; False Start Bit
Detection; Automatic Break Detect
and Handling.
• Synchronous Baud Rate Baud
DC to
Parity, Overrun and
• Ful!y Compatible with 808018085 CPU
• 28·Pin DIP Package
• All Inputs and Outputs are TTL
Compatible
• Single + 5V Supply
DC to 64K
• Single iTL Clock
The Intel'" 8251A is the enhanced version of the industry standard, Intel'" 8251 Universal Synchronous/Asynchronous
Receiver/Transmitter (USART), designed for data communications with Intel's new high performance family of
microprocessors such as the 8085. The 8251A is used as a peripheral device and is programmed by the CPU to operate
using virtually any serial data transmission technique presently in use (including IBM "bi-sync"). The USART accepts
data characters from the CPU in parallel format and then converts them into a continuous serial data stream for
transmission. Simultaneously, it can receive serial data streams and convert them into parallel data characters for the
CPU. The USART will signal the CPU whenever it can accept a new character for transmission or whenever it has
received a character for the CPU. The CPU can read the complete status of the USART at any time. These include data
transmission errors and control signals such as SYNDET, TxEMPTY. The chip is constructed using N·channel silicon
gate technology.
PIN CONFIGURATION
BLOCK DIAGRAM
D,
D,
D]
D"
R,D
vcc.:
GND
R.e
°
D,
DTR
Ds
RTS
D"
DSR
D,
RESET
r;c
eLK
ViR
hD
cs
7 ,00
TlCEMPTY
eTS
CIO
AD
SYNDn/BO
TlCRDY
RIIRDV
PIN NAMES
0,-00
AD
Data Bus (8 blts~
Control or Data 15 to be Wntten
Read Data CO'1lmand
ViR
Write Data or Control Command
e/D
Of
Re
~
...0
<20n
:>
~
1N914
:>
..,
0
8251A
1----,--+---0 OUT
-'0
-20 '---'--:':----'-----='=----'
-'00
CL "'160pF.
~
CAPACITANCE (pFI
Figure 17. Typical 4 Output Delay vs. 4
Capacitance (pF)
Figure 16. Test Load Circuit
9-3
00216A
8251A/S2657
A.C. CHARACTERISTICS
Bus Parameters !(Note 1)
Read Cycle:
MIN.
PARAMETER
SYMBOL
MAX.
TEST CONDITIONS
UNIT
tAR
Address Stable Before READ (CS, C/O)
50
ns
Note 2
tRA
Address Hold Time for READ (CS, C/O)
50
ns
Note 2
tRR
READ Pulse Width
250
ns
tRD
Data Delay from READ
tDF
READ to Data Floating
10
250
ns
100
ns
MAX.
UNIT
3, CL = 150 pF
Write Cycle:
PARAMETER
SYMBOL
tAW
MIN.
Address Stable Before WR ITE
50
ns
tWA
Address Hold Time for WR ITE
50
ns
tww
WRITE Pulse Width
250
ns
tow
Data Set Up Time for WRITE
150
ns
two
Data Hold Time for WRITE
tRV
Recovery Time Between WRITES
50
ns
6
tCY
TEST CONDITIONS
Note 4
NOTES: 1. AC timings measured VOH = 2.0, VOL = 0.8, and with load circuit of Figure 1.
2. Chip Select (CS) and Command/Oata (C/O) are considered as Addresses.
3. Assumes that Address is valid before RD"
4. This recovery time is for Mode InitialiZ!'tion only. Write Data is allowed only when TxRDY = 1.
Recovery Time between Writas for Asynchronous Mode is 8 tCY and for Synchronous Mode is 16 tCY'
Input Waveforms for AC Tests
X~::
2.4---0.45
_ _ _ _oJ
TEST
POINTS
9-4
:::x'-____
00216A
8251A/S2657
Other Timings:
MIN.
MAX.
UNIT
TEST CONDITIONS
tCY
SYMBOL
Clock Period
PARAMETER
320
1350
ns
Notes 5, 6
tq,
1:$
Clock High Pulse Width
140
90
tCY-90
(IS
tR, tF
Clock Rise and Fall Time
tDTx
TxD Delay from Falling Edge of TxC
fTx
Transmitter Input Clock Frequency
Clock Low Pulse Width
lx Baud Rate
16x Baud Rate
64x Baud Rate
DC
DC
DC
ns
20
ns
1
J.Ls
64
310
615
kHz
kHz
kHz
Transmitter I nput Clock Pulse Width
tTPW
1 x Baud Rate
16x and64x Baud Rate
12
1
tCY
tCY
15
3
tCY
tCY
Transmitter Input Clock Pulse Delay
tTPD
1 x Baud Rate
16x and 64x Baud Rate
Receiver Input Clock Frequency
fRx
lx Baud Rate
16x Baud Rate
64x Baud Rate
DC
DC
DC
64
310
615
kHz
kHz
kHz
Receiver Input Clock Pulse Width
tRPW
lx Baud Rate
16x and 64x Baud Rate
12
1
tCY
tCY
15
3
tCY
tCY
Receiver Input Clock Pulse Delay
tRPD
lx Baud Rate
l6x and 64x Baud Rate
tTxRDY
TxRDY Pin Delay from Center of last Bit
8
tCY
Note 7
tTxRDY CLEAR
TxRDY ~ from Leading Edge of WR
6
tCY
Note 7
tRxRDY
RxRDY Pin Delay from Center of last Bit
24
tCY
Note 7
tRxRDY CLEAR
RxRDY ~ from Leading Edge of RD
6
tCY
Note 7
tiS
Internal SYNDET Delay from Rising
Edge of RxC
24
tCY
Note 7
tES
External SYNDET Set· Up Time Before
Falling Edge of RxC
16
tCY
Note 7
tTxEMPTY
TxEMPTY Delay from Center of Last Bit
20
tCY
Note 7
twc
Control Delay from Rising Edge of
WRITE (TxEn,DTR, RTS)
8
tCY
Note 7
tCR
Control to READ Set-Up Time (DSR, CTS)
20
tCY
Note 7
5. The TxC and RxC frequencies have the following limitations with respect to elK.
For 1x Baud Rate, fTx or fRx < 11(30 tCY)
For 16x and 64x Baud Rate. fTx or fRx < 1/(4.5 tCyl
6. Reset Pulse Width
~
6 tCY minimum; System Clock must be running during Reset.
7. Status update can have a maximum delay of 28 clock periods from the event affecting the status.
9-5
00216A
inter
8253/8253·5
PROGRAMMABLE INTERVAL TIMER
• MCS-85™ Compatible 8253·5
• Count Binary or BCD
• 3 Independent 16·Blt Counters
• Single
+ 5V Supply
• DC to 2 MHz
• Programmable Counter Modes
• 24·Pin Dual In·Line Package
The IntelC!> 8253 is a programmable counter/timer chip designed for use as an Intel microcornputer peripheral. It uses
nMOS technology with a single +5V supply and is packaged in a 24·pin plastic DiP.
It is organized as 3 independent 16·bit counters, each with a count rate of up to 2 MHz. All modes of operation are soft·
ware programmable.
PIN CONFIGURATION
0,
Vee
o.
ViR
BLOCK DIAGRAM
elK 0
DATA
Ali
0,
~
oJ
A,
0,
Ao
0,
eLK 2
GATE 0
BUS
BUFFER
our 0
OUT 2
Do
eLK 0
GATE 2
OUT 0
eLK 1
GATE 0
GATE 1
GNO
OUT 1
RD --~-CI
elK 1
GATE 1
AO---~
OUT 1
Al~-
CS--------'
PIN NAMES
°7,0
elK N
GATE N
OUT N
RD
WR
CS
A~A
eLK 2
DATABUS(8BtTf
COUNTER
COUNTER CLOCK INPUTS
"2
COUNTER GATE INPUTS
GATE 2
OUT 2
COUNTER OUTPUTS
READ COUNTER
WRITE COMMAND OR OAT A
CHIP SELECT
COUNnR SELECT
Vee
+5 VOL T5
GND
GROUND
INTERNAL BUS /
INTEL CORPORATION ASSUMES NO RESPONSIBILITY FOR THE USE OF ANY CIRCUITRY OTHER THAN CIRCUITRY EMBODIED IN AN INTEL PRODUCT. NO OTHER CIRCUIT PATENT LICENSES ARE IMPlIEO.
>.t·
Other counterltimer functions that are non-delay in
nature but also common to most microcomputers can be
implemented with the 8253.
• Programmable Rate Generator
• Event Counter
• Binary Rate Multiplier
• Real Time Clock
• Digital One-Shot
• Complex Motor Controller
.-t!. :.-..;.,..;.;o.q
VIIi -.,--".,q
..
.~,.","-'-~"'1
..;Ai.'..· .•
Data Bus Buffer
This 3-state, bi-directional, 8-bit buffer is used to interface
the 8253 to the system data bus. Data is transmitted or
received by the buffer upon execution of INput or OUTput
CPU instructions. The Data Bus Buffer has three basic
functions.
1. Programming the MODES of the 8253.
2. Loading the count registers.
3. Reading the count values.
ReadIWrite Logic
The ReadlWrite Logic accepts inputs from the system bus
and in turn generates control signals for overall device
operation. It is enabled or disabled by CS so that no
operation can occur to change the function unless the
device has been selected by the system logic.
Figure 1. Block Diagram Showing Data Bus Buffar and
RaadIWrita Logic Functions
RD (Read)
CS
RD
WR
A,
Ao
A "low" on this input informs the 8253 that the CPU is
inputting data in the form of a counters value.
0
1
0
0
0
Load Counter No. 0
0
1
0
1
Load Counter No.1
WR (Write)
A "low" on this input informs the 8253 that the CPU is
outputting data in the form of mode information or loading
counters.
9-7
0
1
0
0
1
0
Load Counter No.2
0
1
0
1
1
Write Mode Word
0
0
1
0
0
Read Counter No. 0
0
0
1
0
1
Read Counter No.1
0
0
1
1
0
Read Counter No.2
0
0
1
1
1
No-O peration 3-State
1
X
X
1
1
X
X
Disable 3-State
0
X
X
No-Operation 3-State
AFN-00745A-{)2
8253/8253·5
Control Word Register
The Control Word Register is selected when AD, A 1 are 11.
It then accepts information from the data bus buffer and
stores it in a register. The information stored in this
register controls the operational ~~ODE of each counter,
selection of binary or BCD counting and the loading of
each count register.
The Control Word Register can only be written into; no
read operation of its contents is available.
Counter #0, Counter #1, Counter #2
These three functional blocks are identical in operation so
only a single Counter will be described. Each Counter
consists of a single, 16-bit, pre-settable, DOWN counter.
The counter can operate in either binary or BCD and its
input, gate and output are configured by the selection of
MODES stored in the Control Word Register.
The counters are fully independent and each can have
separate Mode configuration and counting operation,
binary or BCD. Also, there are special features in the
control word that handle the loading of the count value so
that software overhead can be minimized for these
functions.
The reading of the contents of each counter is available to
the programmer with simple READ operations for event
counting applications and special commands and logic
are included in the 8253 so that the contents of each
counter can be read "on the fly" without having to inhibit
the clock input.
Figure 2. Block Diagram Showing Control Word
Register and Counter Functions
8253 SYSTEM INTERFACE
The 8253 is a component of the Intel'· Microcomputer
Systems and interfaces in the same manner as all other
peripherals of the family. It is treated by the systems
software as an array of peripheral I/O ports; three are
counters and the fourth is a control register for MODE
programming.
Basically, the select inputs AD, A 1 connect to the AD, A 1
address bus signals of the CPU. The CS can be derived
directly from the address bus using a linear select method.
Or it can be connected to the output of a decoder, such as
an Intel® 82D5 for larger systems.
\
\
ADDRESS BUS (16)
A,
Ao
l
~
CONTROL BUS
liOR
l
I/OW
~
DATA BUS (8)
A,
Ao
CS
:·1
0 0 .0 7
RD
WR
8253
COUNTER
0
,
COUNTER
I
lOUT GATE elK I lOUT GATE
j
II
1I
COUNTER
2
1
elK'
I
lOUT GATE elK I
I j I)
Figure 3. 8253 System Interface
9-8
AFN-00745A-03
8253/8253·5
M -
OPERATIONAL DESCRIPTION
MODE:
M2
Ml
MO
General
0
0
0
Mode 0
The complete functional definition of the 8253 is
programmed by the systems software. A set of control
words must be sent out by the CPU to initialize each
counter of the 8253 with the desired MODE and quantity
information. These control words program the MODE,
Loading sequence and selection of binary or BCD
counting.
0
0
1
Mode 1
X
1
0
Mode 2
X
1
1
Mode 3
1
0
0
Mode 4
1
0
1
Mode 5
Once programmed, the 8253 is ready to perform whatever
timing tasks it is assigned to accomplish.
BCD:
The actual counting operation of each counter is
completely independent and additional logic is provided
on-chip so that the usual problems associated with
efficient monitoring and management of external,
asynchronous events or rates to the microcomputer
system have been eliminated.
o
Binary Counter 1&bits
Binary Coded Decimal (BCD) Counter
(4 Decades)
Programming the 8253
Counter Loading
All of the MODES for each counter are programmed by the
systems software by simple I/O operations.
The count register is not loaded until the count value is
written (one or two bytes, depending on the mode
selected by the RL bits), followed by a rising edge and a
falling edge of the clock. Any read of the counter prior to
that falling clock edge may yield invalid data.
Each counter of the 8253 is individually programmed by
writing a control word into the Control Word Register.
(AD, Al = 11)
Control Word Format
SC1
SCO
RL1
MODE Definition
0,
DO
MO
BCD
MODE 0: Interrupt on Terminal Count. The output will
be initially low after the mode set operation. After the
count is loaded into the selected count register, the out·
put will remain low and the counter will count. When ter·
minal count is reached the output will go high and remain high until the selected count register is reloaded
with the mode or a new count is loaded. The counter
continues to decrement after terminal count has been
reached.
Definition of Control
SC -
RL -
Select Counter:
SCl
SCO
0
0
Select Counter 0
0
1
Select Counter 1
1
0
Select Counter 2
1
1
Illegal
Rewriting a counter register during counting results in
the following:
(1) Write 1st byte stops the current counting.
(2) Write 2nd byte starts the new count.
MODE 1: Programmable One·Shot. The output will go
low on the count following the rising edge of the gate input.
Read/Load:
RLl
RLO
0
0
1
0
Read/Load most significant byte only.
0
1
Read/Load least significant byte only.
1
1
Read/Load least significant byte first,
then most significant byte.
Counter Latching operation (see
R EADIWR ITE Procedure Section)
The output will go high on the terminal count. If a new
count value is loaded while the output is 10\\1 it will not
affect the duration of the one-shot pulse until the succeeding trigger. The current count can be read at any
time without affecting the one-shot pulse.
The one-shot is retriggerable, hence the output will remain low for the full count after any rising edge of the
gate input.
9-9
AFN-00745A-Q4
825318253·5
MODE 2: Rate Generator. Divide by N counter. The out·
put will be low for one period of the input clock. The
period from one output pulse to the next equals the
number of input counts in the count register. If the
count register is reloaded between output pulses the
present period will not be affected, but the subsequent
period will reflect the new value.
If the count register is reloaded between output pulses
the present period will not be affected, but the subsequent period will reflect the new value. The count will be
inhibited while the gate input is low. Reloading the
counter register will restart counting beginning with the
new number.
The gate input, when low, will force the output high.
When the gate input goes high, the counter will start
from the initial count. Thus, the gate input can be used
to synchronize the counter.
MODE 5: Hardware Triggered Strobe. The counter will
start counting after the rising edge of the trigger input
and will go low for one clock period when the terminal
count is reached. The counter is retriggerable. The out·
put will not go low until the full count after the rising
edge of any trigger.
When this mode is set, the output will remain high until
after the count register is loaded. The output then can
also be synchronized by software.
MODE 3: Square Wave Rate Generator.Simi lar to MODE
2 except that the output will remain high until one half
the count has been completed (for even numbers) and
go low for the other half of the count. This is accom·
plished by decrementing the counter by two on the fall·
ing edge oi each ciock puise. Wilen the counter reaches
terminal count, the state of the output is changed and
the counter is reloaded with the full count and the whole
process is repeated.
Status
~I
Modes
Low
0
1
Disables
counting
~~
Rising
~~
High
Fn;:!htp<:;
counting
1) Initiates
~~
counting
2) Resets output
after next clock
If the count is odd and the output is high, the first clock
pulse (after the count is loaded) decrements the count
by 1. Subsequent clock pulses decrement the clock by
2. After timeout, the output goes low and the full count
is reloaded. The first clock pulse (following the reload)
decrements the counter by 3. Subsequent clock pulses
decrement the count by 2 until timeout. Then the whole
process is repeated. In this way, if the count is odd, the
output will be high for (N + 1)/2 counts and low for
(N -1)/2 counts.
MODE 4: Software Triggered Strobe. After the mode is
set, the output will be high. When the count is loaded,
the counter will begin counting. On terminal count, the
output will go low for one input clock period, then will
go high again.
Low
Or Going
2
3
4
5
1) Disables
counting
2) Sets output
immediately
high
1) Disables
counting
2) Sets output
Immediately
high
Disables
counting
~~
Initiates
counting
Enables
counting
Initiates
Enables
counting
counting
~~
Initiates
Enables
counting
~~
counting
Figure 4. Gate Pin Operations Summary
9-10
AFN-00745A-05
825318253·5
MODE 3: Square Wave Generator
MODE 0: Interrupt on Terminal Count
CLOCK
CLOCK
i
I
WRn~
I
I
4
3
OUTPUT (INTERRUPT)
2
1
OUTPUT (n = 4)
0
OUTPUT (n = 51
I
l '
I---t--n --+]
In =41
I
I
I
I
WRm~
I
I
GATE------------~:L___Jr~I-------5
OUTPUT (INTERRUPTI
(m
"'51
4
2
1
'--'
A
A+B=-m
MODE 1: Programmable One·Shot
MODE 4: Software Triggered Strobe
CLOCK
TRIGGER
4
OUTPUT
________~~~2__'~~
~
3
2
OUTPUT
1
~i~~~~-f-----------
TRIGGER~
OUTPUT
GATE
4i_~3__:2~4__3~~2__'~j---------
MODE 2: Rate Generator
_ ______ _______
-------~~~--------__2__
~4
----,.
4~_3
~1__;0
u-
OUTPUT
MODE 5: Hardware Triggered Strobe
CLOCK
GATE
------Ir - - - - 4
OUTPUT (n • 41
3
2
1
0
L.J
GATE~
4343210
OUTPUT In • 41
W
Figure 5. 8253 Timing Diagrams
9-11
AFN-00745A-06
8253/8253-5
8253 READIWRITE PROCEDURE
Write Operations
MODE Control Word
The systems software must program each counter of the
8253 with the mode and quantity desired. The programmer must write out to the 8253 a MODE contrel word and
the programmed number of count register bytes (1 or 2)
prior to actually using the selected counter.
Counter· n·
LSB
Col,lnt Register byte
Counter n
MSB
Cou nt Register byte
Counter n
The actual order of the programming is quite flexible.
Writing out of the MODE control word can be in any
sequence of counter selection, e.g., counter #0 does not
have to be first or counter #2 last. Each counter's MODE
control word register has a separate address so that its
loading is completely sequence independent. (SCO, SC1)
Note: Format shown is a simple example of loading the 8253 and
does not imply that it is the only format that can be used.
The loading of the Count Register with the actual count
value, however, must be done in exactly the sequence
programmed in the MODE control word (RLO, RL 1). This
loading of the counter's count register is still sequence
independent like the MODE control word loading, but
when a selected count register is to be loaded it !!!..!!§! be
loaded with the number of bytes programmed in the
MODE control word (RLO, RL 1). The one or two bytes to
be loaded in the count register do not have to follow the
associated MODE control word. They can be programmed
at any time following the MODE control word loading as
long as the correct number of bytes is loaded in order.
No.1
MODE Control Word
Counter 0
I
I
No.2
MODE Control Word
Counter 1
1
1
No.3
MODE Control Word
Counter 2
1
1
Count Register Byte
Counter 1
0
1
Count Register Byte
Counter 1
0
1
Figure 6. Programming Format
All counters are down counters. Thus, the value loaded
into the count register will actually be decremented.
Loading all zeroes into a count register will result in the
maximum count (2 '6 for Binary or 10'for BCD). In MODE 0
the new count will not restart until the load has been
completed. It will accept one of two bytes depending on
how the MODE control words (RLO, HL 1) are programmed. Then proceed with the restart operation.
No.4
LSB
No.5
MSB
No.6
LSB
Count Register Byte
Counter 2
1
0
7
MSB
Count Register Byte
Counter 2
1
0
No.8
LSB
0
0
No.9
MSB
0
0
No.
Count Regist~r Byte
Counter 0
Count Register Byte
Counter 0
Note: The exclusive addresses of each counter's count register make
the task of programming the 8253 a very simple matter. and
maximum effective use of the device will result if this feature
is fully utilized.
Figure 7. Alternate Programming Formats
9-12
AFN-00745A-G7
8253/8253·5
Read Operation Chart
Read Operations
In most counter applications it becomes necessary to read
the value of the count in progress and make a
computational decision based on this quantity. Event
counters are probably the most common application that
uses this function. The 8253 contains logic that will allow
the programmer to easily read the contents of any of the
three counters without disturbing the actual count in
progress.
There are two methods that the programmer can use to
read the value of the counters. The first method involves
the use of Simple 1/0 read operations of the selected
counter. By controlling the AO, A I inputs to the 8253 the
programmer can select the counter to be read (remember
that no read operation of the mode register is allowed AO,
AI-II). The only requirement with this method is that in
order to assure a stable count reading the actual operation
of the selected counter must !:!f inhibited either by
controlling the Gate Input or by external logic that Inhibits
the clock Input. The corotents of the counter selected will
be available as follows:
Al
AD
RD
a
a
a
Read Counter No,
1
a
a
a
a
1
1
0
Illegal
1
a
Read Counter No. I
Read Counter No.2
Reading While Counting
first I/O Read contains the least significant byte (lSB).
I n order for the programmer to read the contents of any
counter without effecting or disturbing the counting
operation the 8253 has speCial internal logiC that can be
accessed uSing simple WR commands to the MODE
register. BaSically. when the programmer wishes to read
the contents of a selected counter "on the fly" he loads the
MODE register with a special code which latches the
present count value Into a storage register so that Its
contents contain an accurate, stable quantity. The
programmer then Issues a normal read command to the
selected counter and the contents of the latched register IS
available
second 1/0 Read contains the most significant byte
(MSB).
MODE Register for Latching Count
Due to the internal logic of the 8253 it is absolutely
necessary to complete the entire reading procedure. If two
bytes are programmed to be read then two bytes must be
read before any loading WR command can be sent to the
same counter.
AD, A1
11
SCI,SCO- speCify counter to be latched.
05,04
00 designates counter latching operation.
X
don't care.
The same limitation applies to this mode of reading the
counter as the previous method. That is, it is mandatory
to complete the entire read operation as programmed,
This command has no effect on the counter's mode.
ClK
3MHz
• 1,5MHz
2
8085
ClK
8253-5
"If an 8085 clock output is to drive an 8253·5 clock input, it must be reduced to 2 MHz or less,
Figure 8. MCS-8S™ Clock Interface"
9-13
AFN-00745A-08
8253/8253·5
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
ABSOLUTE MAXIMUM RATINGS·
O"e to 700 e
-65°e to +150o e
Ambient Temperature Under Bias
Storage Temperature
Voltage On Any Pin
With Respect to Ground
Power Dissipation
D.C. CHARACTERISTICS
-0.5Vto+7V
1 Watt
(TA
= O°Cto
70°C; Vee
= 5V ±5%)
SYMBOL
PARAMETER
MIN_
MAX.
UNITS
V,L
Input Low Voltage
-0_5
0_8
V
V,H
Input High Voltage
2_2
Vee+- 5V
V
VOL
Output Low Voltage
0.45
V
Note 1
VOH
Output High Voltage
V
Note 2
2.4
TEST CONDITIONS
= Vee to OV
= Vee to OV
I,L
Input Load Current
±10
/lA
V,N
IOFL
Output Float Leakage
±10
/lA
VOUT
140
mA
Vee Supply Current
lee
Note 1: 8253, IOL = 1.6 mA; 8253-5, IOL = 2.2 mA_
Note 2: 8253, IOH = -150 /lA; 8253-5, IOH = -400/lA.
CAPACITANCE
TA
= 25°C;
Vee
= GND = ov
Min_
Symbol
Parameter
Max.
Unit
C'N
Input Capacitance
Typ_
10
pF
Ic = 1 MHz
CliO
I/O Capacitance
20
pF
Unmeasured pins returned to VSS
9-14
Test Conditions
AFN-00745A-09
8253/8253·5
A.C. CHARACTERISTICS
TA = o°c to 70°C; Vcc = 5.0V ±5%; GND = OV
Bus Parameters (Note 1)
Re.dCycle:
8253
SYMBOL
PARAMETER
MIN.
8253-5
MAX.
MIN.
MAX.
UNIT
tAR
Address Stable Before READ
50
30
ns
tRA
Address Hold Time for READ
5
5
ns
400
tRR
READ Pulse Width
tRO
Data Delay From READI21
tOF
READ to Data Floating
25
tRV
Recovery Time Between READ
and Any Other Control Signal
1
PARAMETER
MIN.
300
ns
300
125
25
200
ns
100
ns
1
/-IS
Write Cycle:
8253-5
8253
SYMBOL
MAX.
MIN.
MAX,
UNIT
tAW
Address Stable Before WR ITE
50
30
tWA
Address Hold Time for WR ITE
30
30
ns
tww
WR ITE Pulse Width
400
300
ns
tow
Data Set Up Time for WR ITE
ns
Data Hold Time for WR ITE
300
40
250
two
30
ns
1
1
IlS
tRv
Recovery Time Between WRITE
and Any Other Control Signal
ns
Notes: 1. AC timings measured at VOH = 2.2. VOL = 0.8
2. Test Conditions: 8253. CL = 1OOpF; 8253-5: CL = 150pF.
Write Timing:
Read Timing:
Ao-t. CS_ _"1'__________t--f"'-_ _ __
DATA BUS
Input Waveforms for A.C. Tests:
2.4--.....,.X
_
0.45
2,.28
_0
>
TEST POINTS
---..I
9-15
<::X___
AFN-0074SA-tO
825318253·5
Clock and Gate Timing:
8253-5
8253
MIN.
MAX.
MIN.
MAX.
UNIT
tCLK
Clock Per iod
380
de
380
de
ns
tPWH
High Pulse Width
230
230
ns
tPWL
Low Pulse Width
150
150
ns
tGW
Gate Width High
150
150
ns
tGL
Gate Width Low
100
100
ns
tGS
Gate Set Up Time to CLKt
100
100
ns
tGH
Gate Hold Time After CLKt
50
50
too
Output Delay From CLK~111
400
400
ns
tOOG
Output Delay From Gate~111
300
300
ns
SYMBOL
Note 1:
PARAMETER
ns
Test Conditions: 8253: CL = 1 OOpF; 8253·5: CL = 150pF.
elK
9-16
AFN-007~A-ll
8255A/8255A·5
PROGRAMMABLE PERIPHERAL INTERFACE
• MCS.85 ™ Compatible 8255A·5
• 24 Programmable 1/0 Pins
• Direct Bit SetlReset Capability Easing
Control Application Interface
• Completely TTL Compatible
• 40·Pin Dual In·Line Package
• Fully Compatible with Intel® Micro·
processor Families
• Reduces System Package Count
• Improved Timing Characteristics
• Improved DC Driving Capability
The Intel@ 8255A is a general purpose programmable I/O device designed for use with Intel@ microprocessors. It has
24110 pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation. In the first
mode (MODE 0), each group of 12 1/0 pins may be programmed in sets of 4 to be input or output. In MODE 1, the second
mode, each group may be programmed to have 8 lines of input or output. Of the remaining 4 pins, 3 are used for handshaking and interrupt control signals. The third mode of operation (MODE 2) is a bidirectional bus mode which uses 8
lines for a bidirectional bus, and 5 lines, borrowing one from the other group, for handshaking.
PIN CONFIGURATION
8255A BLOCK DIAGRAM
S~~;l~;S { - - m
-_GND
10
PA,-PAO
PIN NAMES
0,-°0
RESET
WR
AD,A,
PA7·PM
OAT A BUS (BI·DIRECTIONAl)
RESET INPUT
CHIP SELECT
READ INPUT
WAITE INPUT
PORT AODRESS
ps,._
PORT A IBITI
PORTB IBITI
~,-'CO
Vee
PORT C (BIT)
tAW
-I
twA
-
CS. A1, AD
OUTPUT
MODE 0 (Basic Output)
9-21
AFN-00744A-05
8255A18255A·5
MODE 0 Port Definition
A
GROUPB
GROUPA
B
PORTC
(UPPERI
04
03
0,
DO
PORTA
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
0
1
0
1
0
1
INPUT
OUTPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
I
1
1
0
0
1
1
OUTPUT
OUTPUT
OUTPUT
INPUT
OUTPUT
INPUT
OUTPUT
INPUT
OUTPUT
INPUT
INPUT
OUTPUT
INPUT
OUTPUT
INPUT
OUTPUT
PORTC
#
PORTB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
OUTPUT
(LOWERI
OUTPUT
OUTPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
--
OUTPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
MODE 0 Configurations
CONTROL WORD #2
CONTROL WORD #0
0,
D.
D,
D,
D,
D,
D,
D.
I,!o!o!o!o!o! o 1 0
0,
I
I
•
A
,
D.
D.
D,
D,
D,
°7'°0
A
4
0,
o.
c{
4
B
°,,°
Pe3 ·peO
0
c{
8
PII,-P80
PA,.PAo
•
8
pc,.pee
pc3,peO
PII,-P8o
CONTROL WORD #3
0,
0,
0,
Do
0,
I' 1 0 1 o 1 0 1 0 1 0 1 o 1 ' I
0,
0,
D.
0,
0,
0,
Do
I, I
1,10101010101,
8
A
PA,-PAc
A
8255A
8255A
4
0,.00
•
4
Pe,·pee
CONTROL WORD #1
o.
I
8255A
B
0,
Do
PA,-PAc
8255A
.
D,
0 0 0 0 0 , 0
1 1 1 1 1 1 1
c{
. /.
I
8
•
PC 7 -PC 4
°7'°0
PC3,PCO
I
.
c{
8
•
•
PA,-PAc
Pe"pee
Pc.-pco
8~-PII,.P8o
PII,.P80
9-22
AFN-Q07.4A-06
8255AJ8255A·5
CONTROL WORD #4
0,
I
,
0,
0,
CONTROL WORD ::8
0,
0,
0,
0,
,
0
0
I I I I
0
0
0
1
0,
DO
I,
1 0 1
1
A
8
0,
0,
1 0 1
o
0,
1
1
o
1
o
DO
0
1 0 1
·pAo
A
I
/8
PA 7 ,PAa
8255A
c{
.
•
1
PA7
8255A
°7,00
0,
0,
0,
,
B
4
°7-0 0
4
8
4
c{
PC,.PC 4
pel,pcn
PB 7 ,PSo
4
8
B
PC 7 ·PC 4
pel,pcO
PB 7 ,PSo
CONTROL WORD #9
CONTROL WORD #5
0,
,
1
0,
0,
0,
0
0
0
I
1
1
0,
,
1
0,
0,
DO
0
0
1,1
1
1
A
0,
0,
I,
8
0,
0,
1 0 1 0
1
0,
0,
,
1
o
1
o
8
I
0,
,
0,
1
0,
0
,
1
0,
0
1
1
0,
4
°,,0
4
8
0
•
PC 3 ,PCO
1
,1
0,
I'
0 1
B
8
1
0,
0,
0,
o
0
,
1
0,
1
1
0,
I
,
0,
0
0
0
1
1
1
/4
8
PC 7,PC 4
pel,pc a
PB 7 ,PSa
0,
,
o 1 o 1
1 0 1
8
A
4
PC7 ,PC4
°
7 ,0 0
4
8
•
4
c{
.
pe 3 ,pca
4
/8
8
PB 7 ,PSa
PA 7 ,PAo
I
PC 7 ,PC4
pel,pcO
P87 ,P80
CONTROL WORD #11
0,
,
1
0,
I
0,
0,
0,
I,
,
0
1
1'1
A
8
0,
0,
1 0 1 0
0,
,
1
0,
1
0,
0,
Do
, ,
o 1 o 1
1
A
PArPAo
1
8
PA,.PA,
8255A
8255A
°7,00
0,
PA 7,PAo
CONTROL WORD #7
D.
PA 7 ,PAa
8255A
c{
0 •
D.
I
B
PBrPBo
8255A
0,
/8
I
4
c{
PC 7 ,PC4
0,
A
°7,0
.
CONTROL WORD .::10
0,
0
0
1
I, 1
A
CONTROL WORD #6
0,
o
8255A
c{
.
0,
PA 7 ,PAa
8255A
OrO!) •
1
0,
c{
8
4
PC 7 ,PC 4
DrDa
4
8
PCl,PC o
PB7 ,PSa
c{
8
9-23
4
4
8
PC 7·PC 4
pel,PCO
..,·p80
AFN-00144A-01
8255A18255A·5
CONTROL WORD #12
0,
06
05
04
CONTROL WORD =14
D3
02
0,
DO
0
0
0
0,
I' I I I I, I I I I
A
0
06
05
04
03
02
0
,8
I
0
0
0
I
"
PA,·PAO
PC,.PC 4
,
1
8
B
0,.°0
pe 3 ,pea
D.
Da
D4
0
I
c{
0
I
B
',
PA,·pAo
PC,·PC 4
Pe3 ,peO
,8
I
PB,·PBo
CONTROL WORD #15
D3
02
0,
0,
DO
8
A
B25SA
c{
B
05
0
0
0
06
D4
03
02
0,
DO
I' I I I' I' I I ' I I
I I I I I I I I' I
0
,8
A
PB,.PBo
CONTROL WORD ... is
0,.
0
8211A
c
0
00
I' I I I' I' I I ' I I
B2SSA
0
D,
I
0
0
A
PA,·pAo
8
8211A
',
0
4
8
.
c{
8
4
4
8
Pe,.pc;,
P..,.P8,
Operating Modes
Mode 1 Basic Functional Definitions:
MODE 1 (Strobed Input/Output). This functional configuration provides a means for transferring 1/0 data to
or from s specified port In conjunction with strobes or
"handshsklng" signals. In mode 1, port A and Port B use
the lines on port C to generate or accept these "handshaking" signals.
• Two Groups (Group A and Group B)
• Each group contains one a-bit data port and one 4-bit
control/data port.
• The a-bit data port can be either input or output.
Both inputs and outputs are latched.
• The 4-bit port is used for control and status of the
a-bit data port.
9-24
AFN-00744A-08
8255A18255A·5
Input Control Signal Definition
MODE 1 (PORT Al
STB (Strobe Input). A "low" on this input loads data into
the input latch.
CONTROL WORO
07 06 05 0. 0 3 02 0, Do
IBF (Input Buffer Full F/F)
I, I I, I, 11IoMXW
0
A "high" on this output indicates that the data has been
loaded into the input latch; in essence, an acknowledgement
IBF is set by STB input being low and is reset by the rising
edge of the RD input.
L~"~PUT
oa
OUTPUT
Ro_
INTR (Interrupt Request)
A "high" on this output can be used to interrupt the CPU
when an input device is requesting service. INTR is set by
the STB is a "one", IBF is a "one" and INTE is a "one".
It is reset by the falling edge of RD. This procedure allows
an input device to request service from the CPU by simply
strobi ng its data into the port.
MODE 1 (PORT BI
CONTROL WORD
07 06 0 5 D4 03 02 0, Do
1'~'I'w
INTE A
Controlled by bit set/reset of PC 4 .
INTE B
Controlled by bit set/reset of PC2.
Figure 6. MODE 1 Input
---"T~
V
1\
""',,8-11
1
IBF
INTR
tSIT
\
1_'.,8-
~J
1' )
i/
_tPH_!
INPUT FROM
PERIPHERAL
---
.
...
.
JL
1
J
---------------------
Figure 7. MODE 1 (Strobed Input)
9-25
AFN-oG744A..Q9
8255A18255A·5
Output Control Signal Definition
MODE. (PORT AI
OBF (Output Buffer Full F/F). The OBF output will go
"low" to Indicate that the CPU has written data out to
the specified port. The OBF F/F will be set by the rising
edge of the WR Input and reset by ACK Input being low.
PA,.p....
8
CONTROL WORD
D7 D.
Os
04 03 02 0, Do
/. 10 I. 1°1·IOMXlXl
L~
ACK (Acknowledge Input). A "low" on this Input informs
the 8255A that the data from port A or port B has been ac·
cepted. In essence, a response from the peripheral
device indicating that it has received the data output by
the CPU.
r-- ,
I INTE I
I __
A JI
O-OUTPUT
WR-
MODE 1 (PORT BI
INTR (Interrupt Reque,t). A "high" on this output can be
used to interrupt the CPU when an output device has accepted data transmitted by the CPU. INTR is set when
ACK is a "one", OBF IS a "one" and INTE is a "one". It is
reset by the falling edge of WR.
CONTROL WORD
PB1.P~~
PC,
ODs
INTEA
INTRa
Controlled by bit set/reset of PC6.
INTE B
Controlled by bit set/reset of PC2.
Figure 8. MODE 1 Output
r
INTR
...t----tAK
OUTPUT
Figure 9. Mode 1 (Strobed Output)
AFN.Q0744A-'O
8255A18255A·5
Combinations of MODE 1
Port A and Port B can be individually defined as input or
output in Mode 1 to support a wide variety of strobed I/O
applications.
PA7 ,PAn
PC,
STBA
PC,
IBFA
PC,
INTRA
2
Pe 6. 7
-+--
pe PDO
"
I/O
I/O
8
PC,
pe2 -ACKB
PC,
INTRB
PC.
PORT A - (STROBED INPUT)
PORT A - (STROBED OUTPUT)
PORT B - (STROBED OUTPUT)
PORT B - (STROBED INPUT)
INTRa
Figure 10. Combinations 01 MODE 1
Operating Modes
Output Operations
MODE 2 (Strobed Bidirectional Bus 1/0). This functional
configuration provides a means for communicating with
a peripheral device or structure on a single S·bit bus for
both transmitting and receiving data (bidirectional bus
1/0). "Handshaking" signals are provided to maintain
proper bus flow discipline in a similar manner to MODE
1. Interrupt generation and enableldisable functions are
also available.
OBF (Output Buffer Ful). The OBF output will go "low"
to indicate that the CPU has written data out to port A.
MODE 2 Basic Functional Definitions:
• Used in Group A only.
• One S-bit, bi-directional bus Port (Port A) and a 5-bit
control Port (Port C).
• Both inputs and outputs are latched.
• The 5-bit control port (Port C) is used for control
and status for the B-bit, bi-directional bus port (Port
A).
INTE 1 (The INTE Flip-Flop Associated with OBF)_ Controlled by bit setlreset of PCs.
ACK (Acknowledge). A "low" on this input enables the
tri-state output buffer of port A to send out the data.
Otherwise, the output buffer will be In the high impedance state.
Input Operations
STB (Strobe Input)
STB (Strobe Input)_ A "low" on this input loads data into
the Input latch.
Bidirectional Bus 1/0 Control Signal Definition
IBF (Input Buffer Full F/F)_ A "high" on this output indicates that data has been loaded into the input latch.
INTR (Interrupt Request). A high on this output can be
used to Interrupt the CPU for both input or output operations.
INTE 2 (The INTE Flip-Flop Associated with IBF)_ Controlled by bit setlreset of PC 4 •
9-27
AFN-00744A-11
8255.Al8255A·5
CONTROL WORD
PC2~
1'" INPUT
o "'OUTPUT
' - - - - - PORT B
1'" INPUT
0= OUTPUT
' - - - - - - - GROUP 8 MODE
0" MODE ,0
1'" MODE 1
Figure 11. MODE Control Word
Figure 12. MODE 2
DATA FROM
/ ; CPU TO 8255A
/
INTR
IBF
1----""----PERIPHERAL _ _ _ _ _ _ _ _ _ _
I
--ltAOi-
r - - - -.....
BUS
------t---
DATA FROM
PERIPHERAL TO 8255A
DATA FROM
8255A TO 8080
Figure 13. MODE.2 (Bidirectional)
NOTE:
Any sequence where WR occurs before ACK and STB occurs before RD is permissible.
(lNTR = IBF· MASK· STB 'RD+ OBF • MASK· ACK· WR)
9-28
AFN·OO744A·12
8255A18255A·5
MODE 2 AND MODE 0 (INPUT)
MODE 2 AND MODE 0 (OUTPUT)
\ - - - - I N T RA
PC,
PC, 1 - - - _ OBF A
07
PC 6 - - A C KA
CONTROL WORD
']0\
0 6 05 04 03 02 0,
INTRA
PC,
CONTROL WORD
I, I, e><1
Reading Port C Status
In Mode 0, Port C transfers data to or from the peripheral
device. When the 8255 is programmed to function in Modes
1 or 2, Port C generates or accepts "hand-shaking" signals
with the peripheral device. Reading the contents of Port C
"
i
GRQUPA
,
i
GROUP A
"
'
GROUP 8
(DEFINED BY MODe 0 OR MODE 1 SELECTION)
Figura 18. MODE 2 Statu. Word Format
9-30
AFN-00744A-14
8255A18255A·5
INTERRUPT
REQU
EST
APPLICATIONS OF THE 8255A
I
-
PC,
The 8255A is a very powerful tool for interfacing
peripheral equipment to the microcomputer system. It
represents the optimum use of available pins and is flexible enough to interface almost any 110 device without
the need for additional external logic.
8255A
MODE1
(INPUT)
Each peripheral device in a microcomputer system
usually has a "service routine" associated with it. The
routine manages the software interface' between the
device and the CPU. The functional definition of the
8255A is programmed by the 110 service routine and
becomes an extension of the system software. By ex·
amining the 110 devices interface characteristics for
both data transfer and timing, and matching this infor·
mation to the examples and tables in the detailed opera·
tional description, a control word can easily be devel·
oped to initialize the 8255A to exactly "fit" the application. Figures 17 through 23 present a few examples of
typical applications of the 8255A.
-
PAa
PA,
R.
R,
PA,
R,
PA,
R,
PA,
R,
PAs
PAs
R,
PA,
CONTROL
PC,
STROBE
PC,
ACK
PB.
B.
PB,
B,
SHIFT
-
MODE 1
(OUTPUT)
PB,
B,
PB,
B,
PB,
B,
PB,
B,
---.j
, PB,
BACKSPACE
CLEAR
I PC,
DATA READY
i PCs
BLANKING
ACK
PC,
REQUEST
PC.
PAc
PA,
INTERR
HIGH-SPEED
PA,
PRINTER
CANCEL WORD
UPT~
Figure 18. Keyboard and Display Interface
PAs
PA,
PA,
INTERRUPT
REOU
HAMMER
EST
RELAYS
PC,
I
pc,
PC,
PAc
PC,
PA,
--!C4
MODE 1
(INPUT)
PB.
PB,
--
R.
R,
PA,
R,
PA,
R,
PA,
R,
8255A
FULLY
DECODED
KEYBOARD
PB,
PAs
R,
PB,
PA,
SHIFT
PA,
CONTROL
PC,
STROBE
8255A
PB,
MODEl
~C7
REQUEST
PA,
PA,
(OUTPUT)
BURROUGHS
SELF-SCAN
DISPLAY
: PB7
INTERRUPT
MODE 1
(OUTPUT)
FULLY
DECODED
KEYBOARO
PB,
PB,
PB,
PC,
ACKNOWLEDGE
PC,
BUSY LT
I PC,
TEST L T
PC,
PC,
ACK
---- ,--
PC.
PB.
CONTROL LOGIC ANO DRIVERS
PB,
INTERAUPT
REQUEST
PB,
Figure 11. Printer Interface
MODE 0
PB,
(INPUT)
PB,
l
PB,
PB.
PB,
- - "'0- '1>-- '1>- --- "'0- -
--
---
--
'1>t>-0-
--0-.-
TERMINAL
ADDRESS
-
-
-
Figure 19. Keyboard and Terminal Address Interface
9-31
AFN-00744A-15
8255A18255A·5
INTERRUPT
REaUE S T ' ,
PA,
LSB
PC,
PA.
PA,
PA,
PA,
PA,
PA,
PA.
PA,
MODE 0
IOUTPUTI
PA,
PA,
--
PA.
D·A
CONVERTER
PC.
PC,
PA,
12·BIT
PA,
MODE 2
t-- ANALOG OUTPUT
PAs
PA,
IDACI
r------
PC,
1 - - - - MSB
PC.
r-----
SrB DATA
BIT
SET/RESET
PC,
PC,
I PB.
PB,
PB,
MODE 0
PB,
(I NPUTI
PB.
PB,
·
···
0,
FLOPPY DISK
CONTROLLER
AND DRIVE
0,
D.
0,
0,
0,
DATA STS
PC,
ACK (IN)
PC,
DATA READY
PC,
ACK (OUT)
8255A
OUTPUT EN
PC,
·
··
·
PC.
PC,
8255A
D.
0,
SAMPLE EN
PC,
TRACK "0" SENSOR
PC.
SYNC READY
PC,
INDEX
STB
LSB
--
ENG,A.GE
8-BIT
A·D
CONVERTER
-
ANALOG INPUT
IADCI
MODe a
(OUTPUT)
PB,
MSB
PB,
Figure 20. Digital to Analog, Analog to Digital
~EA!)
FORWARD/REV.
r
PB,
READ ENABLE
PB3
PB4
DISC SELECT
WRITE ENABLE
PB,
ENABLE CRe
PB,
TEST
PB,
BUSY IT
Figure 22. Basic Floppy Disc interface
INTERRUPT
REaUES
INTERRUPT
REaU
EST_:l
Tj
PC,
PA.
PC,
---
PA,
R.
R,
CRT CONTROLLER
PA,
PA,
R,
• CHARACTER GEN.
PA,
-- R,
8 lEVEL
PA,
• REFRESH BUFFER
PA,
R,
PA.
R,
R.
PA.
PA,
MODE 1
PA,
PA,
R.
R,
TAPE
READER
SHIFT
IOUTPUT!
PA,
CONTROL
PAs
PA,
R,
R,
DATA READY
PC,
STB
ACK
PC,
ACK
BLANKED
PC,
STOP/GO
PC,
PC,
R,
-
PC,
PC.
8255A
COLUMN SrB
MODE 0
(INPUT)
MACHINE TOOL
rca
START/STOP
PC,
LIMIT SENSOR (HIV)
PC,
OUT OF FLUID
CURSOR HIV STB
1-
PB,
PB,
i PB,
I PB4
PAPER
8255A
ROW STB
I
I
MODe 1
(INPUT)
R.
R,
BLACKIWHtTE
PC,
PB.
IOUTPUTI
f---
PC,
pc.
MODE 0
• CURSOR CONTROL
PA.
CURSOR/ROW/COLUMN
ADDRESS
MODE 0
(OUTPUT)
H&V
PB.
CHANGE TOOL
PB,
lEFT/RIGHT
PB,
UP/DOWN
PB,
PB.
HOR. STEP STROBE
VERT. STEP STROBE
PB,
PB,
SLEW/STEP
PB,
PB,
PB,
FlUID ENABLE
PB,
Figure 21. Basic CRT Controller Interface
1----
EMERGENCY STOP
Figure 23. Machine Tool Controller Interface
9-32
AFN-00744A-16
8255A18255A·5
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional opera·
tion of the device at these or any other conditions above
those indicated in the operational sections of this specifi·
cation is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias ......... o°c to 70°C
Storage Temperature . . . . . . . . . . . . . . _65°C to +150°C
Voltage on Any Pin
..... -0.5V to +7V
With Respect to Ground .
. . . . . . . . . . . . . . . . 1 Watt
Power Dissipation.
D.C. CHARACTERISTICS
TA = o°c to 70°C. Vee = +5V ±5%; GND = ov
PARAMETER
SYMBOL
MIN.
MAX. UNIT
TEST CONDITIONS
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
Vee
V
VOL (DB) Output Low Voltage (Data Bus)
0.45
V
IOL = 2.5mA
VOL (PER) Output Low Voltage (Peripheral Port)
0.45
V
IOL =1.7mA
VOH(DB)
Output High Voltage (Data Bus)
VOH(PER) Output High Voltage (Peripheral Port)
2.4
V
IOH = -400!-LA
2.4
V
IOH = -200!-LA
IDAR[11
Darlington Drive Current
-4.0
mA
lee
Power Supply Current
120
mA
IlL
Input Load Current
±10
!-LA
VIN = Vee to OV
IOFL
Output Float Leakage
±10
!-LA
VOUT = Vee to OV
Note 1:
-1.0
REXT = 750n; VEXT= 1.5V
Available on any 8 pins from Port Band e.
CAPACITANCE
TA =25°C;Vee=GND=OV
SYMBOL
PARAMETER
MAX.
UNIT
CIN
Input Capacitance
MIN.
TYP.
10
pF
fc = 1MHz
CliO
I/O Capacitance
20
pF
Unmeasured pins returned to GN
~:O~'~
LJ
l
:
I
~_~
y y--------.,..
TEST CONDITIONS
VEXT"
100pF
'VEXT Is set at various voltages during testing to guarantee the specification.
Figure 24. Test Load Circuit (for dB)
9-33
AFN·00744A·'7
o
8255A18255A·5
A.C. CHARACTERISTICS
TA = O°C to 70°C; Vcc = +5V ±5%; GND = OV
Bus Parameters
Read:
Write:
I
I
SYMBOL
PARAMETER
8255A
MIN.
tAW
Address Stable Before WR ITE
0
twA
Address Stable After WR ITE
20
tww
WRITE Pulse Width
400
tow
Data Valid to WR ITE (T.E.)
100
two
Data Valid After WR ITE
30
MAX.
•••
"~,100;i:"'~~"
"J:~",
;:
:.".
""' . ,
..
'
ns
ns
ns
ns
ns
~"i:.:J:,';:';;).:'\:;:,',:"':::.:,i'i·'•..
Other Timings:
PARAMETER
tws
WR = 1 to Output l1 ]
tlR
Peripheral Data Before RD
MIN.
MAX.
350
tHR
Peripheral Data After RD
ACK Pulse Width
300
tST
STB Pulse Width
500
tps
Per. Data Before T.E. of STB
tpH
Per. Data After T.E. of STB
'~,'
.....
....'
,"
;'e) i;'. ............... ,
0
tAK
.MIN.
Ft:r··
.....
8255A
SYMBOL
:~'
UNIT
..
f6>:'. ....
0
"'
,"
,c·
0
,
..
180
.
~.'
UNIT
ns
ns
ns
ns
ns
ns
ns
tAO
ACK = 0 to Output l1 ]
tKO
ACK = 1 to Output Float
twos
WR = 1 to OBF = 011]
650
tAOS
ACK = 0 to OBF = 1111
350
350
ns
tSIB
STB=OtoIBF=1[1]
300
300
ns
tRIB
RD = 1 to IBF = 0[1]
300
300
ns
tRIT
RD = Oto INTR = 0[1]
400
ns
tSIT
STB = 1 to INTR = 1[1]
300
tAIT
ACK = 1 to INTR = 1[1]
350
400
.300
. . 3S0 .
tWIT
WR = Oto INTR = 0 11 ]
850
300
20
250
'20-
'
ns
25(}
ns
650
ns
.......
ns
ns
ns
Not,.: 1. Test Conditions: 8255A: CL = loopF;8255A·5: CL = 150pF.
2. Period of Reset pulse must be at leest SOl'S during or after power on.
Subsequent Reset pulse can be 500 ns min.
9-34
AFN-00744A-18
8255A18255A·5
X:::;;;
2.4 - - - -.......
0.46
------I
TEST POINTS : : : :::
X._._____
Figure 25. Input Waveforms for A.C. Tasts
.
.
tRR
""',
CIR-
RO
--, ~
~tHR-1
INPUT
j - - - tAR _
. . . - - tAA-----+1
B.A'.AD
----------- -(
tRO
.
to.
. ---
Figure 28. MODE 0 (Basic Input)
'w0
twA
B. A•• AD
OUTPUT
Figure 27. MODE 0 (Basic Output)
9-35
AFN-D0744A·18
8255A18255A·5.
-tsT-
j
~
- t SI8 _____
IBF
1/
1
tSIT
INTR
~}
"1
l_tR1B_j
l--tRIT
_ t PH
INPUT FROM
PERIPHERAL
\
)
---
.
tpi
~/
"_!
/
II
/
---------------------
.
Figure 28. MODE 1 (Strobed Inut)
_ t AOB - -
OUTPUT
--1-twB
Figure 29. MODE 1 (Strobed Output)
9-36
AFN-00744A-20
8255A18255A·5
A
DATA FROM
8080 TO 8255
\
INTR
_ t AOB
\
_
i
j
~'WOB-~
/
~
\
\
- tAK
,
-
/~
k:'
1
, _ tsT - _
V
\
'SIB-Ii
rBF
...
PERIPHERAL
BUS
---------/
_
1-"01---
' •.1-_ - - - -
/
tpHI---
OATA~OM
OATAInOM
PERIPHERAL TO 8255
-
8255 TO PERIPHERAL
i---
_ _ tRIB
/
DATA FROM
8255 TO 8OBO
Figure 30. MODE 2 (Bidirectional)
NOTE:
Any sequence where WR occurs before ACK and STB occurs before RD is permissible.
(lNTR = IBF • MASK· STB • RD + OBF • MASK' ACK • WR )
9-37
AFN-00744A-21
8259A
PROGRAMMABLE INTERRUPT CONTROLLER
• MCS·86™ Compatible
• MCS·80185™ Compatible
• Elght·Level Priority Controller
• Expandable to 64 Levels
• Programmable Interrupt Modes
• Individual Request Mask Capability
• Single
+ 5V Supply (No Clocks)
• 28·Pin Dual·ln·Line Package
The Intell!l 8259A Programmable Interrupt Controller handles up to eight vectored priority interrupts for the CPU. It is
cas cad able for up to 64 vectored priority interrupts without additional circuitry. It is packaged in a 28-pin DIP, uses
NMOS technology and requires a single + 5V supp!y_ Circuitry is static, requiring no clock input.
The 8259A is designed to minimize the software and real time overhead in handling mUlti-level priority interrupts_ It has
several modes, permitting optimization for a variety of system requirements.
The 8259A is fully upward compatible with the Intel 8259. Software originally written for the 8259 will operate the
8259A in all 8259 equivalent modes (MCS-80/85, Non-Buffered, Edge Triggered).
BLOCK DIAGRAM
PIN CONFIGURATION
INTA
CS
iVA
vee
AD
INTA
Au
IR7
0,
0,
IRG
Os
IR5
0,
IR4
0,
IR3
0,
IR2
D,
IRI
0,
IRO
CASO
INT
CASI
SP/EN
GND
CAS2
PIN NAMES
D7·~.~L
DATA BUS IBI-DIRECTIONALI
AD
iVA
READ INPUT
._".
WRITE INPUT
COMMAND SELECT ADDRESS
cs
CAS2-CASO
INT
IRO-IR7
DATA
BUS
BUFFER
-IRO
-IR1
WR-
cs -
--.~-----
Ao
!lI'/£I'J
INT
CHIP SELECT
CASCADE LINES
_________ _
SLAVE PROGRAM INPUT/ENABLE
CAS1 _
CAS2 ... --
'INTERNAL BUS
__ 'NT~!l.uPT OU!!.l!!. ___ _
INTERRUPT ACKNOWLEDGE INPUT
INTERRUPT REaUEST INPUTS
INTEL CORPORAmlN ASSUMES NO RESPONSIBILITY FOR THE US[ Of ANY CIRCUITRY OTHER THAN CIRCUITRY EIIIIOOlEO IN AN INTEL PRODUCT. NO OTHER CIRCUIT PATENT LICENSES ARE IMPlIEO.
" INTEL CORPORATION. 1979
9-38
8259A
INTERRUPTS IN MICROCOMPUTER
SYSTEMS
Microcomputer system design requires that 1/0 devices
such as keyboards, displays, sensors and other components receive servicing in an efficient manner so that
large amounts of the total system tasks can be assumed
by the microcomputer with little or no effect on throughput.
The most common method of servicing such devices is
the Polled approach. This is where the processor must
test each device in sequence and in effect "ask" each
one if it needs servicing. It is easy to see that a large portion of the main program is looping through this continuous polling cycle and that such a method would
have a serious, detrimental effect on system throughput, thus limiting the tasks that could be assumed by
the microcomputer and reducing the cost effectiveness
of using such devices.
match his system requirements. The priority modes can
be changed or reconfigured dynamically at any time during the main program. This means that the complete
interrupt structure can be defined as required, based on
the total system environment.
CPU·DRIVEN
MULTIPLEXOR
CPU
RAM
A more desirable method would be one that would allow
the microprocessor to be executing its main program
and only stop to service peripheral devices when it is
told to do so by the device itself. In effect, the method
would provide an external asynchronous input that
would inform the processor that it should complete
whatever instruction that is currently being executed
and fetch a new routine that will service the requesting
device. Once this servicing is complete, however, the
processor would resume exactly where it left off.
This method is called Interrupt. It is easy to see that
system throughput would drastically increase, and thus
more tasks could be assumed by the microcomputer to
further enhance its cost effectiveness.
ROM
Polled Method
The Programmable Interrupt Controller (PIC) functions
as an overall manager in an Interrupt-Driven system
environment. It accepts requests from the peripheral
equipment, determines which of the incoming requests
is of· the highest importance (priority), ascertains
whether the incoming request has a higher priority value
than the level currently being serviced, and issues an
interrupt to the CPU based on this determination.
Each peripheral device or structure usually has a special
program or "routine" that Is associated with its specific
functional or operational requirements; this Is referred
to as a "service routine". The PIC, after issuing an Interrupt to the CPU, must somehow input information into
the CPU that can "point" the Program Counter to the
service routine associated with the requesting device.
This "pointer" is an address In a vectoring table and will
often be referred to, In this document, as vectoring data.
CPU
RAM
ROM
8259A BASIC FUNCTIONAL DESCRIPTION
GENERAL
The 8259A Is a device specifically designed for use in
real time, Interrupt driven microcomputer systems. It
Manages eight levels or requests and has built-In features for expandabillty to other 8259A's (up to 64 levels).
It is programmed by the system's ·software as an 1/0
peripheral. A selection of priority modes Is available to
the programmer so that the manner In which the requests are processed by the 8259A can be configured to
Interrupt Method
9-39
INT
8259A
INTERRUPT REQUEST REGISTER (IRR) AND
IN·SERVICE REGISTER (ISR)
The interrupts at the IR input lines are handled by two
registers in cascade, the Interrupt Request Register
(IRR) and the In·Service Register (ISR). The IRR is used
to store all the interrupt leveis which are requesting ser·
vice; and the ISR is used to store all the interrupt levels
which are being serviced.
PRIORITY RESOLVER
This logic block determines the priorities of the bits set
in the IRR. The highest priority is selected and strobed
into the corresponding bit of the ISR during INTA pulse.
INTERRUPT MASK REGISTER (IMR)
The IMR stores the bits which mask the interrupt lines
to be masked. The IMR operates on the IRR. Masking of
a higher priority input will not affect the interrupt
request lines of lower priority.
INT (INTERRUPT)
This output goes directly to the CPU interrupt input. The
VOH level on this line is designed to be fully compatible
with the 8080A, 8085A and 8086 input levels.
8259A Block Diagram
iNTi (INTERRUPT ACKNOWLEDGE)
INTA pulses will cause the 8259A to release vectoring
information onto the data bus. The format of this data
• depends on the system mode ("PM) of the 8259A.
DATA BUS BUFFER
This 3-state, bidirectional 8·bit buffer Is used to inter·
face the 8259A to the system Data Bus. Control words
and status information are transferred through the Data
Bus Buffer.
READIWRITE CONTROL LOGIC
The function of this block is to accept OUTput com·
mands from the CPU. It contains the Initialization Com·
mand Word (ICW) registers and Operation Command
Word (OCW) registers which store the various control
formats for device operation. This function block also
allows the status of the 8259A to be transferred onto the
Data Bus.
CS (CHIP SELECT)
A LOW on this Input enables the 8259A. No reading or
writing of the chip will occur unless the device is
selected.
WR(WRITE)·
8259A Block Diagram
A LOW on this input enables the CPU to write control
words (ICWs and OCWs) to the 8259A.
Fffi (READ)
A LOW on this Input enables the 8259A to send the
status of the Interrupt Request Register (IRR), In Service
Register (lSR), the Interrupt Mask Register (IMR), or the
.
Interrupt level onto the Data Bus.·
9-40
Ao
This input signal is used in conjunction with WR and RD
signals to write commands into the various command
registers, as well as reading the various status registers
of the chip. This line can be tied directly to one of the ad·
dress lines.
8259A
THE CASCADE BUFFER/COMPARATOR
This function block stores and compares the IDs of all
8259A's used in the system. The associated three I/O
pins (CASO-2) are outputs when the 8259A is used as a
master and are inputs when the 8259A is used as a
slave. As a master, the 8259A sends the 10 of the interrupting slave device onto the CASO-2 lines. The slave
thus selected will send Its preprogrammed subroutine
address onto the Data Bus during the next one or two
consecutive INTA pulses. (See section "Cascading the
8259A".)
If no interrupt request is present at step 4 of either
sequence (i.e., the request was too short in duration) the
8259A will issue an interrupt level 7. Both the vectoring
bytes and the CAS lines will look like an interrupt level 7
was requested.
INTERRUPT SEQUENCE
The powerful features of the 8259A in a microcomputer
system are its programmability and the interrupt routine
addressing capability. The latter allows direct or indirect
jumping to the specific interrupt routine requested
without any polling of the interrupting devices. The normal sequence of events during an interrupt depends on
the type of CPU being used.
The events occur as follows in an MCS-80/85 system:
1. One or more of the INTERRUPT REQUEST lines
(IR7-0) are raised high, setting the corresponding IRR
bit(s).
2. The 8259A evaluates these requests, and sends an
INT to the CPU, if appropriate.
3. The CPU acknowledges the INT and responds with an
INTA pulse.
4. Upon receiving an INTA from the CPU group, the
highest priority ISR bit is set, and the corresponding
IRR bit is reset. The 8259A will also release a CALL instruction code (11001101) onto the 8-bit Data Bus
through its 07-0 pins.
5. This CALL instruction will initiate two more INTA
pulses to be sent to the 8259A from the CPU group.
6. These two INTA pulses allow the 8259A to release its
preprogrammed subroutine address onto the Data
Bus. The lower 8-bit address is released at the first
INTA pulse and and the higher 8-bit address is released at the second INTA pulse.
7. This completes the 3-byte CALL instruction released
by the 8259A. In the AEOI mode the ISR bit is reset at
the end of the third INTA pulse. Otherwise, the ISR bit
remains set until an appropriate EOI command is
issued at the end of the interrupt sequence.
8259A Block Diagram
The events occurring in an MCS-86 system are the same
until step 4.
4. Upon receiving an INTA from the CPU group, the highest priority ISR bit is set and the corresponding IRR
bit is reset. The 8259A does not drive the Data Bus
during this cycle.
CASCADE {
LINES
5. The MCS-86 CPU will initiate a second INTA pulse.
During this pulse, the 8259A releases an 8-bit pointer
onto the Data Bus where it is read by the CPU.
,
INTERRUPT
REQuESTS
6. This completes the interrupt cycle. In the AEOI mode
the ISR bit is reset at the end of the second INTA
pulse. Otherwise, the ISR bit remains set until an
appropriate EOI command is issued at the end of the
interrupt subroutine.
8259A Interface to Standard System Bus
9-41
I,
8259A
During the third INTApuise the higher address of the
appropriate service routine, which was programmed as
byte 2 of the initialization sequence (As - A 1sl, is
enabled onto the bus.
INTERRUPT SEQUENCE OUTPUTS
MCS·80/85 SYSTEM
This sequence is timed by three INTA pulses. During the
first iiifi'A pulse the CALL opcode is enabled onto the
data bus.
-
Content of Third Interrupt
Vector Byte
Content of First Interrupt
Vector Byte
D7
CALLCODE
D8
D5
D4
D3
D2
Dl
07
A15
DO
06
A14
05
A13
D4
A12
03
All
02
Al0
01
DO
A9
AS
~1_l_________0 ____0____________0____l~1
MCS·8S SYSTEM
MCS·86 mode is similar to MCS·80 mode except that
only two Interrupt Acknowledge cycles are issued by
the processor and no CALL opcode is sent to the proc·
essor. The first interrupt acknowledge cycle is similar to
that of MCS-80/85 systems in that the 8259A uses it to
internally freeze the state of the interrupts for priority
resoiuiion ana as a master it issues the interrupt code
on the cascade lines at the end of the INTA pulse. On
this first cycle it does not issue any data to the processor and leaves its data bus buffers disabled. On the
second interrupt acknowledge cycle in MCS·86 mode
the master (or slave if so programmed) will send a byte
of data to the processor with the acknowledged inter·
rupt code composed as follows (note the state of the
ADI mode control is ignored and A5-All are unused in
MCS-86 mode):
During the second INTA pulse the lower address of the
appropriate service routine is enabled onto the data bus.
When Interval 4 bits A5-A7 are programmed, while AoA4 are automatically inserted by the 8259A. When Inter·
val 8 only A6 and A7 are programmed, while Ao-A5 are
automatically inserted.
=
=
Content of Second Interrupt
Vector Byte
IR
7
6
5
4
3
2
1
0
D7
A7
A7
A7
A7
A7
A7
A7
A7
D8
A6
A6
A6
A6
A6
A6
A6
A6
D5
A5
A5
A5
A5
A5
A5
A5
A5
Intervll-4
04
D3
1
1
1
1
1
0
1
0
0
1
0
1
0
0
0
0
02
1
0
1
0
1
0
1
0
Dl
0
0
0
0
0
0
0
0
DO
0
0
0
0
0
0
0
0
Content of Interrupt Vector Byte
for MCS·86 System Mode
IA
Interval =8
o7 ____o_6_____D_5____o_4____o_3 ____D_2_~_0_1__ ~0~~_
7 ~~____A~6~ ____~ ___~__~___ ~O~__~O____O~
6
A7 __A~6_____~__~__~O__~O:____~O____ ~
IR7
IR6
IR5
IR4
IR3
IR2
IRI
IRO
~~~A-7----A~6--------0~----~--~O----O~--~O~
4
0
0
0
c
-A7
- -A6- - - - - -0- -3
A7
A6
0
1
0
0
o.~
2
A7
A6
0
1
0
0
0
0
- - - -------------~--~-.-
1--1__ ~7_ _ ~6___ ~ _ _ Cl... ___ ~ ____O" ____ ~
o
A7
A6
0
0
0
0
0
__~
0
9-42
07
A15
A15
A15
A15
'115
A15
A15
A15
08
A14
A14
A14
A14
A14
A14
A14
A14
05
A13
A13
A13
A13
A13
A13
A13
A13
04
A12
A12
A12
A12
A12
A12
A12
A12
~
03
All
All
All
All
02
1
1
1
1
Al_~
'Ill
All
All
___
0
0
0
L....--
01
1
1
0
0
1
1
0
0
__
00
1
0
1
0
1
0
1
0
~_
8259A
PROGRAMMING THE 8259A
INITIALIZATION
The 8259A accepts two types 01 command words gener·
ated by the CPU:
GENERAL
1. Initialization Command Words (lCWs): Belore normal
operation can begin. each 8259A in the system must
be brought to a starting point - by a sequence 01 2 to
4 bytes timed by imi pulses. This sequence is
described in Figure 1.
Whenever a command is issued with AO =0 and D4 =1,
this is interpreted as Initialization Command Word 1
(ICW1). ICW1 starts the initialization sequence during
which the following automatically occur.
a. The Interrupt Mask Register is cleared.
b. IR 7 input is assigned priority 7.
c. The slave mode address is set to 7.
2. Operation Command Words (OCWs): These are the
command words which command the 8259A to oper·
ate in various interrupt modes. These modes are:
a. Fully nested mode
b. Rotating priority mode
c. Special mask mode
d. Polled mode
d. Special Mask Mode is cleared and Status Read is set to
IRR.
e. If IC4 = O. then all functions selected in ICW4 are set to
zero. (Non-Buffered mode'. no Auto-EOI. MCS-80/85
system. non SFNM).
The OCWs can be written into the 8259A anytime alter
initialization.
Ao
D4
D3
0
1
RD
WR
CS
0
0
1
1
0
0
'Nol.: Master/Slave In ICW4 Is only used in the buffered mode.
INPUT OPERATION (READ)
IRR. ISR or Interrupting Level-+-DATA BUS (Note 1)
IMR .--DATA BUS
OUTPUT OPERATION (WRITE)
0
0
0
1
0
0
0
1
X
X
1
X
1
1
1
1
0
0
0
0
0
DATA
DATA
DATA
DATA
0
0
0
BUS --OCW2
BUS --OCW3
BUS .... ICW1
BUS .... OCW1.ICW2.ICW3.ICW4 (Note 2)
DISABLE FUNCTION
X
X
X
X
X
X
1
X
1
X
DATA BUS - 3-STATE (NO OPERATION)
DATA BUS - 3-STATE (NO OPERATION)
0
1
Nol." t. Selection of IRR. ISR or Interrupting Level Is based on the content of OCW3 written before the READ operation.
2. On-chip sequencer logic queues these commands into proper sequence.
8259A Ba.le Operation
9-43
8259A
INITIALIZATION COMMAND WORDS 1 AND 2
(ICW1,ICW2)
INITIALIZATION COMMAND WORD 3 (ICW3)
This word is read only when there is more than one
8259A in the system and cascading is used, in which
case SNGL = O. It will load the 8-bit slave register. The
functions of this register are:
As-A1S: Page starting address of service routines. In an
MCS 80/85 system, the 8 request levels will generate
CALls to 8 locations equally spaced in memory. These
can be programmed to be spaced at intervals of 4 or 8
memory locations, thus the 8 routines will occupy a
page of 32 or 64 bytes, respectively.
a. In the master mode (either when SP = 1, OJ in buttered
mode when MIS = 1 in ICW4) a "1" is set for each
slave in the system. The master then will release byte
1 of the call sequence (for MCS-SO/S5 system) and
will enable the corresponding slave to release bytes 2
and 3 (for MCS-S6 only byte 2) through the cascade
lines.
b. In the slave mode (either when SP = 0, or if BUF = 1
and MIS = 0 in ICW4) bits 2-0 identify the slave. The
slave compares its cascade Input with these bits and,
if they are equal, bytes 2 and 3 of the call sequence (or
just byte 2 for MCS-86) are released by it on the Data
Bus.
INITIALIZATION COMMAND WORD 4 (lCW4)
The address format is 2 bytes long (Ao-A1S)' When the
routine interval is 4, Ao-A4 are automatically inserted by
the 8259A, while As-A l s are programmed externally.
When the routine interval Is 8, Ao-As are automatically
inserted by the 8259A, while A6-A 1S are programmed
externally.
The a·byte interval will maintain compatibility with current software, while the 4-byte interval is best for a compact jump table.
In an MeS-86 system A 1S-A ll are inserted in the five
most significant bits of the vectoring byte and the
8259A seis ilie iI""" illasi signiiicant bits accorolng to
the interrupt level. Al0-As are ignored and ADI (Address
Interval) has no effect.
SFNM: If SFNM = 1 the special fully nested mode Is
programmed.
BUF: If BUF = 1 the buffered mode is programmed. In
buffered mode SP/EN becomes an enable output
and the masterlslave determination Is by MIS.
MIS: If buffered mode Is selected: MIS = 1 means the
8259A is programmed to be a master, MIS = 0
means the 8259A is programmed to be a siave. If
BUF = 0, MIS has no function.
AEOI: If AEOI = 1 the automatic end of Interrupt mode
Is programmed.
,",PM: Microprocessor mode: ,",PM 0 sets the 8259A
for MCS-80/85 system operation, ,",PM = 1 sets
the 8259A for MCS-86 system operation.
If LTIM = 1, then the 8259A will operate in the
level Interrupt mode. Edge detect logic on the
Interrupt Inputs will be disabled.
ADI:
CALL address Interval. ADI = 1 then Interval = 4;
ADI = 0 then Interval = 8.
SNGL: Single. Means that this Is the only 8259A In the
system. If SNGL= 1 no ICW3 will be Issued.
IC4:
If this bit Is set - ICW4 has to be read. If ICW4
Is not needed, set IC4 = O.
LTIM:
AO
D7
De
D5
I
0
A7
Ae
A5
I
1
A15
1114
A13
=
D4
D2
Dl
ADI
SNGl
IC4j ICWI
All
Al0
AI
AljlCW2
52
SI
so j'CW3
MIS
AEO'
DO
I
A12
r----------(-~~.~~
I
D3
lTIM
1
S7
se
SS
54
....
S3
~--------------------r-t------------------~
,.------------~~~~."
I
SFNM
1
aUF
t
I
READY TO ACCEPT REQUESTS
IN THE FUllY NESTED MODE
Figure 1_ Initialization Sequence
9-44
I
8259A
ICW'
1· lew. NEEOED
0 .. NO ICW4NEEDEO
1" SINGLE
0'"' NOT SINGLE
CALL ADDRESS INTERVAL
1'" INTERVAL OF 4
O· INTERVAL OF 8
1 .. LEVel TRIGGERED INPUT
0'" EDGE TRIGGERED INPUT
A7 - AS OF LOWER
ROUTINE ADDRESS
(MC8-80/95 MODE ONl YI
ICW2
UPPER ROUTINE
ADDRESS
ICW3 (MASTER DEVICE)
1 ~ IR INPUT HAS A SLAVE
0" IR INPUT DOES NOT HAVE
A SLAVE
ICW31SLAVE DEVICE)
~
~
~
~
~
~
0
0
0
0
0
1, j I I I I
~
~
~
lID, liD, lIDo
I
·•• •• .•, ..., .,, ,,,
SLAVE 10111
o ,
,
2 3 •
,
,
5
•
7
o , ,
1 '" MCS 86 MODE
0'" MCS·80/85 MODE
1 ~ AUTO £01
0'" NORMAL EOI
EH!j
X--' - NON BUFFERED MODE
1
0
1
,.... BUFFERED MODE/MASTER
- BUFFERED MODE/SLAVE
NOTE 1: SLAVED 10 IS EQUAL TO THE CORRESPONDING MASTER IR INPUT.
NOTE 2: X INDICATED "DON'T CARE".
Initialization Command Word Format
9-45
8259A
OPERATION COMMAND WORDS (OCWs)
OPERATION CONTROL WORD 1 (OCW1)
After the Initialization Command Words (ICWs) are programmed Into the 8259A, the chip Is ready to accept
Interrupt requests at Its Input lines. However, during the
8259A operation, a selection of algorithms can command the 8259A to operate In various modes through
the Operation Command Words (OCWs).
OCW1 sets and clears the mask bits In the Interrupt
Mask Register (IMR). M:'- Mo represent the eight mask
bits. M = 1 Indicates the channel is masked
(Inhibited), M = 0 indicates the channel is enabled.
OPERATION CONTROL WORD 2 (OCW2)
R, SEOI, EOI - These three bits control the Rotate and
End of Interrupt modes and combinations of the two. A
chart of these combinations can be found on the Opera·
tlon Command Word Format.
OPERATION CONTROL WORDS (OCWI)
OCW1
AO
[i]
D7
I M7
De
D5
D4
D3
D2
D1
DO
Me
M5
M4
M3
M2
M1
MO
L2, L1, La - These bits determine the Interrupt level
acted upon when the SEOI bit Is active.
I
OPERATION CONTROL WORD 3 (OCW3)
0
0
IR
I0
OCW2
SEOI
EOI
0
0
L2
Ll
0
=
=
=
ocwa
SSMM SMM
ESMM - Enable Special Mask Mode. When this bit Is
set to 1 It enables the SMM bit to set or reset the Special
Mask Mode. When ESMM 0 the SMM bit becomes a
"don't care".
LOI
P
SRIS
RIS
SMM - Special Mask Mode. If ESMM = 1 and SMM 1
the 8259A will enter Special Mask Mode. If ESMM 1
and SM M = 0 the 8259A will revert to normal mask mode.
When ESMM = 0, SMM has no effect.
I
9-46
8259A
ocw,
I
~
07
0
R
~
~
~
~
I I I i
SEor
o
EOI
0
~
0,
~
1 c, 1 c, 1 c, I
. •,
BCD LEVel TO BE RESET
,
OR PUT INTO LOWEST PRIORITV
I
1
J-
0
,
,
0
0
, ,
0
0
0
0
2
,
0
0
6
7
,
, ,
, , , ,
0
0
0
0
r
r+
~-'i-r+
r,-o~
I-i-r,-r-;I-i-Io'o
r,-r,-r,-
f7r-;-~
tttttt
NON-$I'ECIFrCEO.
SPECIFIC
eol. lO-L2 CODE OF IS Ff TO BE RESET
ROTATE AT Eor AUTOMATICALLY (MODE A)
ROTATE AT EOIIMOOE BI, (LG-U OEFINES NEW LOWESTPRIORITV)
SET ROTATE A FF
CLEAR ROTATE A fF
AOTATE PRIORITY (MODE B) INDEPENDENTLY OF EOI (LO-U CODE OF LINE)
NOOPERATLON
ocw,
I
0
1-
I"M"I SMM 1
OJN'T
CAR~
0
1 ' 1
p
1ERIS 1 R'S I
l_
READ IN SERVICE REGISTER
0
0
I ,
I
0
NO ACTION
0
,
,
,
READ
REAO
IR REG
ISREG
ON NE'(T
ON NEXT
RD PULSE
AD PULSE
POLLING
A HIGH ENABLES THE NEXT Fib PULSE
TO READ THE BCD CODe OF THE HIGH
EST LEVEL REQUESTING INTERRUPT
SPECIAL MASK MODe
0
0
1 ,
I
0
0
,
RESET
NO ACTION
Operation Command Word Format
9-47
SPECIAL
MA""
,
,
SET
SPECIAL
MASK
8259A
INTERRUPT MASKS
Each Interrupt Request Input can be masked Indlvldu,ally by the Interrupt Mask Register (IMR) programmed
through OCW1. Each bit In the IMR masks one Interrupt
channel If It Is set (1). Bit 0 masks IRO, Bit 1 masks IR1
and so forth. Masking an IR channel does not affect the
other channels operation.
SPECIAL MASK MODE
Some applications may require an interrupt service
routine to dynamically alter the system priority structure during its execution under software control. For
example, the routine may wish to inhibit lower priority
requests for a portion of its execution but enable some
of them for another portion.
The difficulty here Is that if an Interrupt Request is
acknowledged and an End of Interrupt command did not
reset its IS bit (i.e., while executing a service routine),
the 8259A would have inhibited all lower priority
requests with no easy way for the routine to enable
them
That is where the Special Mask Mode comes In. In the
special Mask Mode, when a mask bit is set in OCW1, it
inhibits further interrupts at that level and enables Interrupts from all other levels (lower as well as higher) that
are not masked.
Thus, any interrupts may be selectively enabled by
loading the mask register.
The special Mask Mode is set by OCW3 where:
SSMM = 1, SMM = 1, and cleared where SSMM = 1,
SMM=O.
BUFFERED MODE
When the 8259A Is used in a large system where bus
driving buffers are required on the data bus and the cascading mode is used, there exists the problem of enablIng buffers.
The buffered mode will structure the 8259A to send an
enable Signal on Sfi/EN to enable the buffers. In this
mode, whenever the 8259A's data bus outputs are enabled, the SP/EN output becomes active.
This modification forces the use of software programming to determine whether the 8259Ais a master or a
slave. Bit 3 in ICW4 programs the buffered mode, and bit
2 in ICW4 determines whether it is a master or a slave.
9-48
FULLY NESTED MODE
This mode is entered after Initialization unless another
mode is programmed. The interrupt requests are
ordered in priority form 0 through 7 (0 highest). When an
interrupt is acknowledged the highest priority request is
determined and its vector placed on the bus. Additionally, a bit of the Interrupt Service register (ISO-7) is set.
This bit remains set until the microprocessor issues an
End of Interrupt (EOI) command immediately before
returning from the service routine, or if AEOI (Automatic
End of Interrupt) bit is set, until the trailing edge of the
last INTA. While the IS bit is set, all further interrupts of
the same or lower priority are inhibited, while higher
levels will generate an interrupt (which will be
acknowledged only If the microprocessor internal Interrupt enable flip-flop has been re-enabled through software).
After the Initialization sequence, IRO has the highest
priority and IR7 the lowest. Priorities can be changed, as
will be explained, In the rotating priority mode.
THE SPECIAL FULLY NESTED MODE
This mode will be used In the case of a big system
where cascading Is used, and the priority has to be conserved within each slave. In this case the fully nested
mode will be programmed to the master (using ICW4).
This mode Is similar to the normal nested mode with the
following exceptions:
a. When an Interrupt request from a certain slave is in
service this slave Is not locked out from the master's
priority logic and further interrupt requests from
higher priority IR's within the slave will be recognized
by the master and will initiate Interrupts to the processor. (In the normal nested mode a slave is masked
out when Its request is in service and no higher
requests from the same slave can be serviced.)
b. When exiting the Interrupt Service routine the software has to check whether the interrupt servlced was
the only one from that slave. This is done by sending
a non-specific End of Interrupt (EOI) command to the
slave and then reading Its In-Service register and
checking for zero. If it is empty, a non-specific EOI
. can be sent to the master too. If not, no EOI should be
sent.
8259A
POLL
In this mode the microprocessor internal Interrupt
Enable flip-flop Is reset, disabling its interrupt input.
Service to devices is achieved by programmer Initiative
using a Poll command.
The Poll command Is Issued by setting P= "1" in OCW3.
The 8259A treats the next AD pulse to the 8259A (i.e.,
RD = 0, ~ = 0) as an interrupt acknowledge, sets the
appropriate IS bit If there is a request, and reads the
priority level. Interrupt is frozen from WR to RD.
The word enabled onto the data bus during
07
De
05
o.
I
1
03
m5 is:
02
01
00
W2
WI
wol
WO-W2: Binary code of the highest priority level
requesting service.
I: Equal to a "1" if there is an interrupt.
second in MCS·86). Note that from a system standpoint,
this mode should be used only when a nested multilevel
interrupt structure is not required within a single 8259A.
To achieve automatic rotation (Rotate Mode A) within
AEOI, there is a special rotate flip-flop. It is set by OCW2
with R = 1, SEOI = 0, EOI = 0, and cleared with R = 0,
SEOI = 0, EOI = O.
ROTATING PRIORITY MODE A (AUTOMATIC
ROTATION) FOR EQUAL PRIORITY DEVICES
In some applications there are a number of interrupting
devices of equal priority. In this mode a device, after
being serviced, receives the lowest priority, so a device
requesting an interrupt will have to wait, in the worst
case until each of 7 other devices are serviced at most
once. For example, if the priority and "in service" status
is:
Before Rotate (IR4 the highest priority requiring service)
This mode Is useful if there is a routine command com·
mon to several levels so that the fNTA sequence is not
needed (saves ROM space). Another application is to
use the poll mode to expand the number of priority
levels to more than 64.
IS7 lSI ISS IS. IS3 152 IS1
"IS" Status
Low•• 1 Priority
Priority Status
END OF INTERRUPT (EOI)
The In Service (IS) bit can be reset either automatically
following the trailing edge of the last in sequence INTA
pulse (when AEOI bit in ICW1 is set) or by a command
word that must be issued to the 8259A before returning
from a service routine (EOI command). An EOI command
must be issued twice, once for the master and once for
the corresponding slave if slaves are in use.
There are two forms of EOI command: Specific and Non·
Specific. When the 8259A Is operated in modes which
preserve the fully nested structure, it can determine
which IS bit to reset on EOL When a Non-Specific EOI
command is issued the 8259A will automatically reset
the highest IS bit of those that are set, since in the
nested mode the highest IS level was necessarily the
last level acknowledged and serviced.
However, when a mode is used which may disturb the
fully nested structure, the 8259A may no longer be able
to determine the last level acknowledged. In this case a
Specific End of Interrupt (SEOI) must be issued which
Includes as part of the command the IS level to be reset.
EOI is issued whenever EOI = 1, in OCW2, where LO-L2 is
the binary level of the IS bit to be reset. Note that although
the Rotate command can be issued together with an EOI
where EOI = 1, it is not necessarily tied to it.
It should be noted that an IS bit that is masked by an
IMR bit will not be cleared by a non·specific EOI if the
8259A Is in the Special Mask Mode.
ISO
10111011101010101
Hlgh •• 1 Prlorlly
1716 15 I • I 3 12 I ho I
After Rotate (IR4 was serviced, all other priorities
rotated correspondingly)
IS7 lSI ISS
"IS" Slatus
Hlgh.1I Prlorlly
Priority Status
IS. IS3 IS2 151
ISO
10111010101010101
1 2 1
11
0
Low•• t Prlorlly
7E04131
The Rotate command mode A is issued in OCW2 where:
R = 1. EOI = 1. SEOI = O. Internal status is updated by an
End of Interrupt I EOI or AEOII command. If R = 1, EOI = 0,
SEOI = 0, a "Rotate-A" flip-flop is set. This is useful in
AEOI, and described under Automatic End of Interrupt.
ROTATING PRIORITY MODE B (ROTATION BY
SOFTWARE)
The programmer can change priorities by programming
the bottom priority and thus fixing all other priorities;
i.e., if IR5 is programmed as the bottom priority device,
then IR6 will have the highest one.
AUTOMATIC END OF INTERRUPT (AEOI) MODE
The Rotate command is issued in OCW2 where: R = 1,
SEOI = 1; LO- L2 is the binary priority level code of the
bottom priority device.
If AEOI = 1 In ICW4, then the 8259A will operate in AEOI
mode continuously until reprogrammed by ICW4. In this
mode the 8259A will automatically perform a non·
specific EOI operation at the trailing edge of the last
interrupt acknowledge pulse (third pulse in MCS·80/85,
Observe that In this mode internal status is updated by
software control during OCW2. However, it is independent of the End of Interrupt (EOI) command (also exe·
cuted by OCW2). Priority changes can be executed duro
ing an EOI command or independently.
9-49
8259A
LTIM liT
TO OTHER 'AIORTY CULS
.=EOGE
1 "",LEVEL
itT
·""ORITY
REIOLVER
CONTRDL
LOGIC
REOUEST
LATCH
,R
o
-+-11>>----'1..
c
.:~
I
I
a~~-+---,~uo.~-+~--4~
NON·
LATCH
REO
a
MASKED
oH-++-+
o
I
'1:1
Ii
NOTES
1. MAlTER CLEAR ACTIVE ONLY DURING
2. FIIEEZE/II ACTIVE DURING iJiITJ AND POLL SEQUENCES ONLY
3. TRUTH TAiLE FOR D·LATCH
rcw,
OPEPIATION
fOLLOW
HOLD
Priority Cell - Simplified Logic Diagram
LEVEL TRIGGERED MODE
This mode is programmed using bit 3 in ICW1.
If LTIM ='1', an interrupt request wilrbe recognized by a
'high' level on IA Input, and there is no need for an edge
detection. The interrupt request must be removed
before the EOI command Is Issued or the CPU Interrupt
is enabled to prevent a second interrupt from occurring.
The above figure shows a conce~::Jal circuit to give the
reader an understanding of the level sensitive and edge
sensitive input circuitry of the 8259A. Be sure to note
that the request latch is a transparent D type latch.
READING THE 8258A STATUS
The Input status of several internal registers can be read
to update the user Information on the system. The
following registers can be read by Issuing a suitable
OCW3 and reading with AD.
Interrupt Mask Register: 8-blt register whose content
specifies the Interrupt request lines being masked.
acknowledged. The highest request leyel is reset from
the IAA when an Interrupt Is acknowledged. (Not
affected by IMA.)
In-Service Register (ISR): 8-bit register which contains
the priority levels that are being serviced. The .ISA is
updated when an End of Interrupt command is Issued.
Interrupt Mask Register: 8-bit register which. contains
the interrupt request lines which are masked.
The IAA can be read when, prior to the AD pulse, a WR
pulse is Issued with OCW3 (EAIS= 1, RIS=O.)
The ISA can be read in a similar mode when EAIS= 1,
AIS = 1 in the OCW3.
There is no need to write an OCW3 before every status
read operation, as long as the status read corresponds
with the previous one; I.e., the 8259A "remembers"
whether the IRA or ISA has been previously selected by
the OCW3. This is not true when poll is used.
After Initialization the 8259A is set to IAA.
For reading the IMA, no OCW3 is needed. The output
data bus will contain the IMA whenever AD is actiYe and
AO= 1.
Polling overrides status read when P= 1, EAIS= 1 in
OCW3.
9-50
inter
8272
SINGLE/DOUBLE DENSITY
FLOPPY DISK CONTROLLER
Compatible in Both Single and
• IBM
Double Density Recording Formats
Programmable Data Record Lengths:
• 128,256,512,
or 1024 Bytes/Sector
Multi·Sector and Multi·Track Transfer
• Capability
Transfers in DMA or Non·DMA
• Data
Mode
Seek Operations on Up to
• Parallel
Four Drives
Compatible with Most
• Microprocessors
Including 8080A,
• Drive Up to 4 Floppy Disks
Data Scan Capability - Will Scan a
• Single
Sector or an Entire Cylinder's
8085A, 8086 and 8088
• Slngle·Phase 8 MHz Clock
• Single +5 Volt Power Supply
Worth of Data Fields, Comparing on a
Byte by Byte Basis, Data in the
Processor's Memory with Data Read
from the Diskette
in 40·Pln Plastic Dual·ln·Llne
• Available
Package
The 8272 is an LSI Floppy Disk Controller (FDG) Chip, which contains the circuitry and control functions for Interfacing
a processor to 4. Floppy Disk Drives. It is capable of supporting either IBM 3740 single density format (FM), or IBM
System 34 Double Density format (MFM) including double sided recording. The 8272 provides control signals which
simplify the design of an external phase locked loop, and write precompensation circuitry. The FDC simplifies and
handles most of the burdens associated with implementing a Floppy Disk Drive Interface.
8272 INTERNAL BLOCK DIAGRAM
PIN CONFIGURATION
RESET
liD
Vee
RWISEEK
DATA BUS
BUFFER
0 8 0.7
REGISTERS
AO
WPITS
SERIAL
INTERFACE
CONTROLLER
TERMINAL
COUNT - .
DRQ
.....-.-READY
mK_
WRITE PROTECTITWO SIDE
INT
liD_
WR ~
Ao
~
RESET
~
INDEX
FAULTITRACK 0
CONTROL
LOGIC
DRIVE
INTERFACE
L-.,..-....I
CONTROLLER
elK
DRIVE SELECT 0
DRIVE SELECT 1
MFM MODE
l'iW/SEEK
HEAD LOAD
HEAD SELECT
LOW CURRENT/DIRECTION
FAULT RESET/STEP
~
Vee - . . .
GND ---+-
Intel Corporation Assumes No Responsibllty for the Use of Any Circuitry Other Than Circuitry Embodied in 8n Intel Product. No Other Circuit Patent Licenses are Implied.
© INTEL CORPORATION. 1980
9-51
8272
8272 REGISTERS
8272 SYSTEM BLOCK DIAGRAM
CPU INTERFACE
The 8272 contains two registers which may be accessed
by the main system processor; a Status Register and a
Data Register, The 8-bit Main Status Register contains
the status information of the FDC, and may be accessed
at any time. The 8-bit Data Register (actually consists of
several registers in a stack with only one register presented to the data· bus at a time), stores data, commands, parameters, and FDD status information. Data
bytes are read out of, or written into, the Data Register
in order to program or obtain the results after execution
of a command. The Status Register may only be read
and is used to facilitate the transfer of data between the
processor and 8272.
8237
DMA
i5ACK
CONTROLLER
The relationship between the Status/Data registers and
the signals RD, WR, and Ao is shown below.
8272
FDC
TC
L -_ _--I TERMINAL L...._ _.J
COUNT
DESCRIPTION
Hand-shaking signals are provided in the 8272 which
make DMA operation easy to incorporate with the aid of
an external DMA Controller chip, such as the 8237. The
FDC will operate in either DMA or Non-DMA mode. In
the Non-DMA mode, the FDC generates interrupts to the
processor for every transfer of a data byte between the
CPU and the 8272. In the DMA mode, the processor need
only load a command into the FDC and all data transfers
occur under control of the 8272 and DMA controller.
RD
WR
0
0
i
Head Main l::itatus
Register
FUNCTION
0
1
0
Illegal
0
0
0
Illegal
1
0
0
Illegal
1
0
1
Read from Data Register
1
1
0
Write into Data Register
The bits in the Main Status Register are defined as
follows:
SYMBOL
DESCRIPTION
08 0
FOO 0 Busy
008
FOO numberO is in the Seek
mode.
08,
FDD 1 Busy
0,8
FOO number 1 is in the Seek
mode.
082
FDD 2 Busy
028
FOD number2 is in the Seek
mode.
08 3
FOD 3 Busy
038
FDO number3 is in the Seek
mode.
08 4
FOC Busy
C8
A read or write command is
in process.
08 5
Non·DMA mode
NOM
The FOe is in the non·DMA
mode. This bit is set only
during the execution phase
in non·DMA mode. Tran-
BIT NUMBER
There are 15 separate commands which the 8272 will
execute. Each of these commands require multiple 8-bit
bytes to fully specify the operation which the processor
wishes the FDC to perform. The following commands
are available.
Read Data
Read ID
Read Deleted Data
Read a Track
Scan Equal
Scan High or Equal
Scan Low or Equal
Specify
Ao
Write Data
Format a Track
Write Deleted Data
Seek
Recalibrate (Restore to
Track 0)
Sense Interrupt Status
Sense Drive Status
NAME
sition to "0" state indicates
execution phase has ended.
086
Data Input/Output
010
Indicates direction of data
transfer between FOe and
Data Register. If 010="1"
then transfer Is from Data
Register to the Processor.
If 010 = "0", then_ transfer
is -from the Processor to
Data Register.
087
Request for
Master
ROM
Indicates Data Register is
ready to send or receive
data to or from the Proc·
essor. Both bits 010 and
ROM should be used to
perform the handshaking
functions of "ready" and
"direction" to the
processor.
FEATURES
Address mark detection circuitry is internal to the FDC
which simplifies the phase locked loop and read electronics. The track stepping rate, head load time, and
head unload time may be programmed by the user. The
8272 offers many additional features such as multiple
sector transfers in both read and write modes with a
single command, and full IBM compatibility in both
single (FM) and double density (MFM) modes.
9-52
8272
PIN DESCRIPTION
PIN
NO.
PIN
UO
CONNECTION
TO
RST
I
"p
Reset: Places FOe in idle
state. Resets output lines to
FOD to "0" (low)
2
1m
l'
"p
Read: Control signal for
transfer of data from FOC to
Data Bus. when "0" (low)
3
WR
l'
"p
NO.
SYMBOL
1
DESCRIPTION
SYMBOL
UO
CONNECTION
TO
D.C. POWER
VCC
RWISEEK
0
FOO
Read Write/SEEK: When "1"
(high) Seek mode selected and
when "0" (low) ReadlWrite
mode selected
38
LCTIOIR
0
FOO
Low Current/Direction: Lowers
Write current on inner tracks
In ReadlWrlte mode, deter·
mines direction head will step
in Seek mode
37
FAlSTP
0
FOO
Fault Reset/Step: Resets fault
FF in FOD in ReadlWrite
mode, provides step puises to
move head to another cylinder
in Seek mode
Bus, when "0" (low)
4
CS
5
Ao
I
"p
Chip Select: Ie selected
when "0" (low), allowing
Ffi) and
to be enabled
"p
Data/Status Reg Select
Selects Data Reg (AO = 1) or
Stalus Reg (AO = 0)
36
HOL
0
FOO
Head Load: Command which
causes read/write head in FDD
to contact diskette
content
35
ROY
I
FOO
Ready: Indicates FDD Is ready
to send or receive data
34
WPITS
I
FOO
Write ProtectlTwo-Slde:
Senses Write Protect status In
ReadIWrlte mode, and Two
Side Media In Seek mode
33
FLTITRKO
I
FOO
Faultrrrack 0: Senses FDD
fault condition In ReadlWrlte
mode and Track 0 condition
in Seek mode.
31,32
PS"PSO
0
FOO
Precompensatlon (pre-shift):
Write precompensation status
during MFM mode. Deter·
mines early, late, and normal
times.
30
WR DATA
0
FOO
Write Data: Serial clock and
data bits to FDD
28,29
OS"OSO
0
FOO
Drive Select: Selects FOD unit
27
HOSEL
0
FOO
Head Select: Head 1 selected
when "1" (high) Head 0
selected when "0" (low)
26
MFM
0
PLL
MFM Mode: MFM mode when
"1", FM mode when "0"
25
WE
0
FOO
Write Enable: Enables write
data Into FOD
24
VCO
0
PLL
VCO Sync: Inhibits VCO in
PLL when "0" (low), enables
VCO when "1"
23
RO DATA
I
FOO
Read Data: Read data from
FOD, containing clock and
data bits
22
OW
I
PLL
Data Window: Generated by
PLL, and used to sample data
from FDD
21
WRCLK
I
m
I
be sent to Data Bus
Data Bus: Bidirectional
a-Sit Data Bus
6-13
OBo-OB7
I/O
"p
14
ORO
0
OMA
Data DMA Request; DMA
Request is being made by
FOC when ORO "1"
15
OACK
I
OMA
DMA Acknowledge: DMA
cycle Is active when "0"
(low) 'and Controller Is
performing DMA transfer
16
TC
I
OMA
Terminal Count: Indicates
the termination of a DMA
transfer when "1" (high)
17
lOX
I
FOO
Index: Indicates the beginning
of a disk track
18
INT
0
"p
19
CLK
I
20
GNO
Note 1: Disabled when
+ 5V
40
39
Write: Control signal for
transfer of data to FOe via Data
DESCRIPTION
Interrupt: 'Interrupt Request
Generated by FOC
Clock: Single Phase 8 MHz
Squarewave Clock
Ground: D.C. Power Return
CS: 1.
9-53
Write Clock: Write data rate to
FDD FM = 500 kHz, MFM = 1
MHz, with a pulse width of
250 ns for both FM and MFM
8272
The 010 and ROM bits in the Status Register indicate
when Data is ready and In which direction data will be
transferred on the Data Bus.
04TAI,.·OUT
=
1010)
OUT OF PROCEnaR AND INTO FDC
• I
I·
NOTES:
the reset to the Interrupt signal.
If the 8272 Is in the DMA Mode, no Interrupts are generated during the Execution Phase. The 8272 generates
ORa's (DMA Requests) when each byte of data Is
available. The DMA Controller responds to this request
'with both a DACK = 0 (DMA Acknowledge) and a RD 0
(Read signal). When the DMA Acknowledge signal goes
low (DACK = 0) then the DMA Req uest Is reset (ORO = 0).
If a Write COmmand has been programmed- then a WR
Signal will appear Instead of RD. After the EXf!cution
Phase has been completed (Terminal Count has
occurred) then an Interrupt will occur (INT = 1). This
signifies the beginning of the Result Phase. When the
first byte of data Is read during the Result Phase, the Interrupt Is automatically reset (INT 0).
@ _ DATA REOISTER READY to IE WRITTEN INTO BV PROCE8$OR
I!l -
DATA REGiStER HOT READY TO liE WRITTEN INTO IY PAOCUSOR
@ - OATA REGISTER READY FDA NEXT DATA BYTE TO IE READ IV THE
=
PROCESSOR
[QJ _ DATA REGISTER NOT READY FDA NEXT DATA BYTE TO III! READ BY
PROCESSOR
STATUS REGISTER TIMING
The 8272 Is capable of executing 15 different commands. Each command is initiated by a multi-byte
transfer from the processor, and the result after execution of the command may also be a multi-byte transfer
back to the processor. Because of this multi-byte Interchange of information between the 8272 and the processor, It is convenient to consider each command as
consisting of three phases:
Command Phase: The FDC receives all Information
required to perform a particular
operation from the processor.
Execution Phase: The FDC performs the operation It
was Instructed to do.
Resuft Phase:
After completion of the operation,
status and other housekeeping Information are made available to
the processor.
During Command or Result Phases the Main Status
Register (described earlier) must be read by the processor before each byte of information Is written into or
read from the Data Register. Bits 06 and 07 in the Main
Status Register must be In a 0 and _1 state, respectively,
before each byte of the command word may be written
Into the 8272. Many of the commands require multiple
bytes, and as a result the Main Status Register must be
read prior to each byte transfer to the 8272. On the other
hand, during the Result Phase, 06 and 07 In the Main
Status Register must both be 1's (06= 1 and 07= 1)
before reading each byte from the Data Register. Note,
this reading of- the Main Status Register before each
byte transfer to the 8272 is required in only the Command and Result Phases, and NOT during the Execution
Phase.
During the Execution Phase, the Main Status Register
need not be read. If the 8272 Is in the Non-DMA Mode,
then the receipt of each data byte (If 8272 Is reading data
from FDD) is indicated by an Interrupt signal on pin 18
(lNT = 1). The generation of a Read signal (im 0) will
reset the Interrupt as well as output the Data onto the
Data Bus. For example, If the processor cannot handle
Interrupts fast enough (every 13/o1s for MFM mode) then
It may poll the Main Status Register and then bit 07
(ROM) functions just like the Interrupt signal. If a Write
Command Is In process then the WFf Signal performs
=
It is important to note that during the Result Phase all
bytes shown In the Command Table must be read. The
Read Data Command, for example, has seven bytes of
data in the Result Phase. All seven bytes must be read In
order to successfully complete the Read Data Command. The 8272 will not accept a new command until all
seven bytes have been read. Other commands may require fewer bytes to be read during the Result Phase.
The 8272 contains five Status Registers. The Main
Status Register mentioned above may be read by the
processor at any time. The other four Status Registers
(STO, ST1, ST2, and ST3) are only available during the
Result Phase, and may be read only after successfully
completing a command. The particular command which
has been executed determines how many of the Status
_Registers will be read.
The bytes of data which are sent to the 8272 to form the
Command Phase, and are read out of the 8272 in the
Result Phase, must occur In the order, shown In the
Command Table. That Is, the Command Code must be
sent first and the other bytes sent In the prescribed sequence. No foreshortening of the Command or Result
Phases are allowed. After the last byte of data In the
Command Phase is sent to the 8272 the Execution
Phase automatically starts. In a similar fashion, when
the last byte of data is read out In the Result Phase;the
command Is automatically ended and the 8272 Is ready
for a new command. A command may be aborted by
simply sending a Terminal Count signal to pin 16
(TC 1). This Is a convenient means of ensuring that the
processor may always get the 8272's attention even If
the disk system hangs up In an abnormal manner.
=
POLLING FEATURE OF THE 8272
After the Specify command has been sent to the 8272,
the Drive Select Lines DSO and DS1 will automatically
go into a polling mode. In between commands (and between step pulses in the SEEK command) the 8272 polls
all four FDDs looking for a change In the Ready line from
any of the drives. If the Ready line changes state (usually due to a door opening or closing) then the 8272 will
generate an Interrupt. When Status Register 0 (STO) Is
read (after Sense Interrupt Status is Issued), Not Ready
(NR) will be indicated. The polling of the Ready line by
the 8272 occurs continuously between instructions,
thus notifying the processor which drives are on or off
line.
9-54
intJ
8272
TABLE 1. 8272 COMMAND SET
I
PHASE
AIW
DATA BUS
Dr De
D6
D4
Da
DATA BUS
DZ
D,
, ,
DO
REMARKS
PHASE
AIW
Dr
D,
D6
READ DATA
Command
W
W
W
W
W
W
W
W
W
MT MFM SK
0
0
0
0
0
0
0
0
Command
Command Codes
HDS OS, DSO
Sector 10 information
prior to Command
execution
C
H
R
N
EDT
GPL
DTL
\
Execution
Result
Data transfer
between the FOD
and main-system
R
R
R
R
R
R
R
W
W
MT MFM SK
0
0
0
0
0
sector 10 Information
after command
execution
•
1
0
0
0 HDS OS, 050
Result
Command Codes
Sector 10 information
prior to Command
execution
C
H
R
N
EC.
GPL
DTL
W
W
W
W
W
W
W
W
W
0 MFM SK
0
0
0
R
R
R
R
R
R
R
Result
Status Information
after Command
execution
STO
ST1
ST2
C
H
R
N
Sector 10 information
after Command
execution
W
W
MT MFM
0
0
0
0
0
0
0
0
Command
Command Codes
Sector 10 information
prior to Command
execution
R
R
R
R
R
R
R
STO
STI
ST2
C
H _____
W
0 MFM 0
0
0
0
0
0
STO
ST.
ST2
C
H
R
N
R
R
R
Result
Status information
after Command
execution
Sector 10 information
after Command
execution
W
W
W
W
W
W
W
MT MFM
0
0
0
0
0
0
•
1
0
0
0 HDS OS. DSO
C
H
R
N
EDT
GPL
DTL
Execution
STO
ST.
5T2
C
H
R
N
execution
Sector 10 Information
execution
1
0
,
0
0
HDS OS. DSO
Commands
The first correct 10
Information on the
Cylinder Is stored In
Data Register
R
R
R
R
R
R
R
Status Information
after Command
execution
STO
STI
ST2
C
H
R
Seotor 10 Information
during Execution
Ph...
N
W
0 MFM 0
0
W
W
W
W
W
0
0
0
0
•
0
1
1
0
HDS OS. DSO
Command Codes
BytellSector
SectorsfTrack
Gap 3
Fllt.r Byt.
N
SC
GPL
0
FDC formats an
entire cylinder
R
R
R
R
R
R
R
W
W
W
W
W
W
W
W
W
Command Codes
Septar 10 Information
prior to Command
execution
Status Information
after Command
execution
STO
ST.
ST2
C
H
R
N
MT MFM SK
0
0
0
In this case, the 10
information has no
meaning
1
0
0
0
C
H
R
Result
Status information
after Command
execution
Sector 10 information
after Command
execution
Note: 1. Symbols used In this table are described at the end of this section.
2. AO'" 1 for all operations.
3. X ... Don't care, usually made to equal binary O.
9-55
0
0
1
HOS OS. DSO
Command Codes
Sector 10 information
prior to Command
execution
N
EDT
GPL
STP
Execution
Data transfer
between the FOO
and main-system
R
R
R
R
R
R
R
after Command
SCAN EQUAL
Command
WRITE DELETED DATA
W
W
Statu8 Information
after Command
R
N
Execution
Data transfer
between the mainsystem and FOO
R
Aesult
execution
N
FORMAT A TRACK
•
·1
0
HOS 051 050
C
H
R
N
EDT
GPL
DTL
R
R
R
Command Codes
EDT
GPL
DTL
READ 10
Command
REMARKS
Sector 10 Information
prior to Command
Execution
Execution
Command
,
0
0
0
0 HOS 051 DSO
Data transfer
between the FOO
and main-system
W
W
W
W
W
W
W
Result
DO
C
H
R
WRITE DATA
Command
0
0
D,
Data transfer
between the FDD
and maln-Iystem.
FCC road. all of
cylinders contents
from Index hole to
EDT
W
Execution
Result
Dz
Status Information
after Command
execution
STO
ST'
ST2
C
H
R
N
W
W
W
W
W
W
W
Da
Execution
READ DELETED DATA
Command
D4
READ A TRACK
Data compared
between the FDO
and main-system
R
R
R
R
R
R
R
STO
STI
ST2
C
H
R
N
Status Information
after Command
execution
Sector 10 Information
after Command
execution
8272
TABLE 1. COMMAND SET (Continued)
I
PHASE
RIW
I
DATA BUS
I D7
De
D5
D4
D3
D2
Dl
DO
I
REMARKS
PHASE
RIW
DATA BUS
07
D6
D5
SCAN LOW OR EQUAL
Command
W
W
W
W
W
W
W
MT MFM SK
0
0
0
1
0
1
0
0
0
1
HDS DSl DSO
Command
W
STO
STl
ST2
C
H
R
N
R
W
W
W
W
MT MFM SK
0
0
0
1
1
0
0
C
H
W
R
W
W
N
EOT
GPL
STP
W
W
Execution
Result
R
R
R
STO
ST 1
5T2
C
H
R
N
DO
REMARKS
0
0
0
0
0
0
0
0
0
0
1
0
1
1
DSl DSO
Command Codes
Head retracted to
Track 0
Command
Result
W
Command
W
W
W
0
0
0
0
1
ST 0
PCN
0
0
0
0
R
R
Sector 10 Information
after Command
execution
0
1
1
HDS DSl DSO
0
0
0
Command Codes
Status Information at
the end of each seek
operation about the
FDC
0
1
1
Command Codes
SPECIFY
Status Information
after Command
execution
0
_SPT _ _ _.......---HUT HLT
• NO
SENSE DRIVE STATUS
Command
W
w
Result
R
Command
W
W
W
0
0
0
0
0
0
0
0
0
ST 3
0
0
1
0
HDS DSl DSO
Sector 10 information
prior Command
execution
Command Codes
Status Information
about FoD
Command Codes
SEEK
0
0
0
0
0
0
0
0
1
0
1
1
1
HDS DSl DSO
Command Codes
NCN
Head Is positioned
over proper Cylinder
on Diskette
Execution
Data compared
between the FDD
and main-system
R
R
R
R
Dl
Execution
SCAN HIGH OR EQUAL
Command
W
W
Data compared
between the FOD
and main-system
R
D2
SENSE INTERRUPT STATUS
Execution
R
R
R
R
R
D3
prior Command
execution
EOT
GPL
STP
W
Result
Command Codes
Sector lD information
C
H
R
_____ N
D4
RECALIBRATE
INVALID
Command
W
_ _ _ _ Invalid Codes _ _ _ _
Result
R
5TO
Status Information
after Command
execution
Sector 10 Information
after Command
execution
9-56
Invalid Command
Code. (NoOp- FDC
goes Into Standby
Stale)
STO=80
(16)
inter
8272
TABLE 2. COMMAND MNEMONICS
NAME
SYMBOL
Ao
Address Line 0
DESCRIPTION
AO controls selection of Main Status
Register (AO= 0) or Data Register (AO
NAME
DESCRIPTION
NCN
New Cylinder Number
NCN stands for a new Cylinder number,
which Is going to be reached as a result
of the Seek operation, Desired position of
Head.
SYMBOL
=1).
C
Cylinder Number
C stands for the current selected Cylinder
track number 0 through 76 of the medium.
0
Data
o stands for the data pattern which Is
going to be written Into a Sector.
NO
Non·DMA Mode
NO stands for operation In the Non·DMA
Mode,
orOo
Data Bus
B-blt Data Bus where 07 is the most
significant bit, and 00 Is the least signlfl'
cant bit.
PCN
Present Cylinder
Number
OSO,OS1
Drive Select
OS stands tor a selected drive number 0
or 1.
PCN stands for the Cylinder number at
the completion of SENSE INTERRUPT
STATUS Command. Position of Head at
present time.
R
Record
oTl
Data length
When N is defined as OQ, DTl stands for
the data length which users are going to
read out or write into the Sector.
R stands for the Sector number, which
will be read or written.
R/W
Read/Write
R/W stands for either Read (R) or Write
(IN) aignal.
EOT
End of Track
EOT stands for the final Sector number of
a Cylinder.
SC
Sector
SC Indicates the number of Sectors per
Cylinder.
GPl
Gap Length
GPL stands for the length of Gap 3
(spacing between Sectors excluding VCO
Sync Field).
SK
Skip
SK stands for Skip Deleted Data Address
Mark.
H
Head Address
H stands for head number 0 or 1, as
specified in 10 field.
SRT
Step Rate Time
HOS
Head Select
HOS stands for a selected Mad number 0
or 1 (H = HOS in all command words).
SRT stands for the Stepping Rate for the
FDD (1 to 16ms In 1 ms Increments).
Stepping Rate applies to a1\ drives
(F = 1 ms, E = 2 ms, etc.).
HLT
Head Load Time
HLT stands for the head load time in the
FOO (2 to 254 ms in 2 ms increments).
Status
Status
Status
Status
HUT
Head Unload Time
HUT stands for the head unload time after
a read or write operation has occurred (16
to 240ms in 16ms Increments).
STO
ST 1
ST 2
ST 3
MFM
FM or MFM Mode
If MF is low, FM mode is selected and If
It Is high, MFM mode Is selected,
ST 0-3 stand for one of four registers
which store the status information after
a command has been executed. This
information 15 available during the result
phase after command execution. These
registers should not be confused with the
main status register (selected by AO = 0).
ST 0-3 may be read only after a command
has been executed and contain information
relevant to that particular command.
MT
Multi·Track
If MT is high, a multi·track operation is to
be performed (a cylinder under both HDO
and HD1 will be read or written).
N
Number
N stands for the number of data bytes
written in a Sector.
0
1
2
3
STP
During a Scan operation, If STP= 1, the
data in contiguous sectors Is compared
byte by byte with data sent from the
processor (or DMA), and if STP= 2, then
alternate sectors are read and compared.
COMMAND DESCRIPTIONS
compares with the sector number read off the diskette,
then the FOC outputs data (from the data field) byte-bYbyte to the main system via the data bus.
During the Command Phase, the Main Status Register
must be polled by the CPU before each byte is written
into the Data Register. The 010 (OB6) and ROM (OB7)
bits in the Main Status Register must be in the "0" and
"1" states respectively, before each byte of the command may be written into.the 8272. The beginning of the
execution phase for any of these commands will cause
010 and ROM to switch to "1" and "0" states respectively.
After completion of the read operation from the current
sector, the Sector Number is incremented by one, and
the data from the next sector is read and output on the
data bus. This continuous read function is called a
"Multi·Sector Read Operation." The Read Data Command may be terminated by the receipt of a Terminal
Count signal. Upon receipt of this signal, the FOC stops
outputting data to the processor, but will continue to
read data from the current sector, check CRC (Cyclic
Redundancy Count) bytes, and then at the end of the
sector terminate the Read Data Command.
READ DATA
A set of nine (9) byte words are required to place the
FOC into the Read Data Mode. After the Read Data com·
mand has been issued the FOC loads the head (if it is in
the unloaded state), waits the specified head settling
time (defined in the Specify Command), and begins
reading 10 Address Marks and 10 fields. When the cur·
rent sector number ("R") stored in the 10 Register (lOR)
The amount of data which can be handled with a Single
command to the FOC depends upon MT (multi·track),
MFM (MFM/FM), and N (Number of Bytes/Sector). Table
3 below shows the Transfer Capacity.
TABLE 3. TRANSFER CAPACITY
Multl·Track
MT
MFM/FM
MFM
Bytes/Sector
N
Maximum Transfer Capacity
(BytesJSector)(Number of Sectors)
Final Sector Read
from Diskette
0
0
0
1
00
01
(128) (26) = 3.328
(256)(26) = 8,656
26 at Side 0
or 26 at Side 1
1
1
0
1
00
01
(128) (52)= 6,656
(256) (52) = 13,312
26 at Side 1
0
0
0
1
01
02
(256)(15)= 3,840
(512)(15)= 7,680
15 at Side 0
or 15 at Side 1
1
1
0
1
01
02
(256) (30)= 7,680
(512) (30)= 15,360
15 at Side 1
0
0
0
1
02
03
(512) (8) = 4.096
(1024) (8) = 8,192
8 at Side 0
or 8 at Side 1
1
1
0
02
03
(512)(16)= 8,192
(1024)(16)= 16,384
8 at Side 1
1
9-57
8272
The "multi·track" function (MT) allows the FDC to read
data from both sides of the diskette. For a particular
cylinder, data will be transferred starting at Sector 0,
Side 0 and completing at Sector L, Side 1 (Sector L last
sector on the side). Note, this function pertains to only
one cylinder (the same track) on each side of the
diskette.
TABLE 4. 10 INFORMATION WHEN PROCESSOR TERMINATES
COMMAND'
=
MT
When N = 0, then DTL de.fines the data length which the
FDC must treat as a sector. If DTL is smaller than the ac·
tual data length in a Sector, the data beyond DTL in the
Sector, is not sent to the Data Bus. The FDC reads (inter·
nally) the complete Sector performing the CRC check,
and depending upon the manner of command termina·
tion, may perform a Multi,·Sector Read Operation. When
N is non·zero, then DTL has no meaning and should be
set to OFFH.
At the completion of the Read Data Command, the head
is not unloaded until after Head Unload Time Interval
(specified in the Specify Command) has elapsed. If the
processor Issues another command before the head
unloads then the head settling time may be saved be·
tween subsequent reads. This time out is particularly
valuable when a diskette is copied from one drive to
another.
If the FOC detects the Index Hole twice without finding
the right sector, (indicated in "R"), then the FDC sets
the NO (No Data) flag in Status Register 1 to a 1 (high),
and terminates the Read Data Command. (Status
Register 0 also has bits 7 and 6 set to 0 and 1 respective·
Iy.)
After reading the 10 and Data Fields in each sector, the
FDC checks the CRC bytes. If a read error is detected
(incorrect CRC in ID field), the FDC sets the DE (Data Error) flag in Status Register 1 to a 1 (high), and if a CRC error occurs in the Data Field the FOG also sets the DO
(Data Error in Data Field) flag in Status Register 2 to a 1
(high), and terminates the Read Data Command. (Status
Register 0 also has bits 7 and 6 set to 0 and 1 respectively.)
If the FOC reads a Deleted Data Address Mark off the
diskette, and the SK bit (bit 05 in the first Command
Word) is not set (SK 0), then the FDC sets the CM (Control Mark) flag in Status Register 2 to a 1 (high), and terminates the Read Data Command, after reading all the
data in the Sector. If SK 1, the FDC skips the sector
with the Deleted Data Address Mark and reads the next
sector.
=
=
During disk data transfers between the FDC and the
processor, via the data bus, the FDC must be serviced
by the processor every 27 fls in the FM Mode, and every
13 fls in the MFM Mode, or the FDC sets the OR (Over
Run) flag in Status Register 1 to a 1 (high), and terminates the Read Data Command.
If the processor terminates a read (or write) operation in
the FDC, then the 10 Information in the Result Phase is
dependent upon the state of the MT bit and ,EOT byte.
Table 4 shows the values for C, H, R, and N, when the
processor terminates the Command.
0
1
EOT
Final Sector Transferred to
Proce.sor
10 Intormatlon at Relult Ph.l.
C
H
R
N
NC
NC
R+1
NC
C+l
NC
R=Ol
NC
NC
NC
R+l
NC
C+l
NC
R=Ol
NC
Sector 1 to 25 at Side 0
Sector 1 to 14 at Side 0
Sector 1 to 7 at Side 0
NC
NC
R+l
NC
lA
OF
08
Sector 26 at Side 0
Sector 15 at Side 0
Sector 8 at Side 0
NC
LSB
R=Ol
NC
lA
OF
08
Sector 1 to 25 at Side 1
Sector 1 to 14 at Side 1
Sector 1 to 7 at Side 1
NC
NC
R+l
NC
lA
OF
08
Sector 26 at Side 1
Sector 15 at Side 1
Sector 8 at Side 1
C+l
LSB
R=Ol
NC
lA
OF
08
Sector 1 to 25 at Side 0
Sector 1 to 14 at Side 0
Sector 1 to 7 at Side 0
lA
OF
08
Sector 26 at Side 0
Sector 15 at Side 0
Sector 8 at Side 0
lA
OF
08
Sector 1 to 25 at Side 1
Sector 1 to 14 at Side 1
Sector 1 to 7 at Side 1
lA
OF
08
Sector 26 at Side 1
Sector 15 at Side 1
Sector 8 at Side 1
lA
OF
08
Notes; 1. NC (No Change): The same value as the one at the beginning of command
execution.
2. LSB (Least Significant Bit): The least significant bit of H Is
complemented.
WRITE DATA
A set of nine (9) bytes are required to set the FOG into
the Write Data mode. After the Write Data command has
been issued the FDC loads the head (if it is in the
unloaded state), waits the specified head settling time
(defined in the Specify Command), and begins reading
10 Fields. When the current sector number (UR"), stored
in the 10 Register (lOR) compares with the sector
number read off the diskette, then the FDC takes data
from the processor byte-by-byte via the data bus, and
outputs it to the FDD.
After writing data into the current sector, the Sector
Number stored in "R" is incremented by one, and the
next data field is written into. The FDC continues this
"Multi-Sector Write Operation" until the issuance of a
Terminal Count signal. If a Terminal Count signal is sent
to the FDC it continues writing into the current sector to
complete the data field. If the Terminal Count signal is
received while a data field is being written then the remainder of the data field is filled with 00 (zeros).
The FDC reads the 10 field of each sector and checks
the CRC bytes. If the FDC detects a read error (incorrect
CRC) in one of the 10 Fields, it sets the DE (Data Error)
flag of Status Register 1 to a 1 (high), and terminates the
Write Data Command. (Status Register 0 also has bits 7
and 6 set to 0 and 1 respectively.)
The Write Command operates in much the same manner
as the Read Command. The following items are the
same; refer to the Read Data Command for details:
• Transfer Capacity
• EN (End of Cylinder) Flag
• NO (No Data) Flag
9-58
inter
8272
• Head Unload Time Interval
• 10 Information when the processor terminates command (see Table 2)
• Definition of DTL when N 0 and when N#-O
READID
The READ 10 Command is used to give the present position of the recording head. The FDC stores the values
from the first 10 Field it is able to read. If no proper 10
Address Mark is found on the diskette, before the INDEX HOLE is encountered for the second time then the
MA (Missing Address Mark) flag in Status Register 1 Is
set to a 1 (high), and if no data Is found then the NO (No
Data) flag Is also set in Status Register 1 to a 1 (high)
and the command is terminated.
=
I n the Write Data mode, data transfers between the processor and FDC must occur every 31 I's in the FM mode,
and every 15 I's in the MFM mode. If the time interval
between data transfers Is longer than this then the FDC
sets the OR (Over Run) flag In Status Register 1 to a 1
(high), and terminates the Write Data Command.
WRITE DELETED DATA
FORMAT A TRACK
This command is the same as the Write Data Command
except a Deleted Data Address Mark is written at the
beginning of the Data Field instead of the normal Data
Address Mark.
The Format Command allows an entire track to be formatted. After the INDEX HOLE Is detected, Data is written on the Diskette: Gaps, Address Marks, 10 Fields and
Data Fields, all per the IBM System 34 (Double Density)
or System 3740 (Single Density) Format are recorded.
The particular format which will be written Is controlled
by the values programmed into N (number of bytes/sector), SC (sectors/cylinder), GPL (Gap Length), and 0
(Data Pattern) which are supplied by the processor during the Command Phase. The Data Field Is filled with
the Byte of data stored in D. The 10 Field for each sector
is supplied by the processor; that is, four data requests
per sector are made by the FDC for C (Cylinder Number),
H (Head Number), R (Sector Number) and N (Number of
Bytes/Sector). This allows the diskette to be formatted
with nonsequential sector numbers, if desired.
READ DELETED DATA
This command is the same as the Read Data Command
except that when the FDC detects a Data Address Mark
at the beginning of a Data Field (and SK 0 (low)), It will
read all the data in the sector and set the CM flag in
Status Register 2 to a 1 (high), and then terminate the
command. If SK 1, then the FDC skips the sector with
the Data Address Mark and reads the next sector.
=
=
READ A TRACK
This command is similar to READ DATA Command
except that the entire data field is read continuously
from each of the sectors of a track. Immediately after
encountering the INDEX HOLE, the FDC starts reading
all data fields on the track as continuous blocks of data.
If the FDC finds an error in the 10 or DATA CRC check
bytes, it continues to read data from the track. The FDC
compares the 10 information read from each sector with
the value stored In the lOR, and sets the NO flag of
Status Register 1 to a 1 (high) If there is no comparison.
Multi-track or skip operations are not allowed with this
command.
After formatting each sector, the processor must send
new values for C, H, R, and N to the 8272 for each sector
on the track. The contents of the R register is Incremented by one after each sector is formatted, thus,
the R register contains a value of R + 1 when It Is read
during the Result Phase. This incrementing and formatting continues for the whole track until the FDC encounters the INDEX HOLE for the second time, whereupon it terminates the command.
If a FAULT signal is received from the FDD at the end of
a write operation, then the FDC sets the EC flag of
Status Register 0 to a 1 (high), and terminates the command after setting bits 7 and 6 of Status Register 0 to 0
and 1 respectively. Also the loss of a READY signal at
the beginning of a command execution phase causes
command termination.
This command terminates when EOT number of sectors
have been read. If the FDC does not find an 10 Address
Mark on the diskette after it encounters the INDEX
HOLE for the second time, then it sets the MA (missing
address mark) flag in Status Register 1 to a 1 (high), and
terminates the command. (Status Register 0 has bits 7
and 6 set to 0 and 1 respectively.)
Table 5 shows the relationship between N, SC, and GPL
for various sector sizes:
TABLE 5. SECTOR SIZE RELATIONSHIPS
FORMAT
FM Mode
SECTOR SIZE
N
SC
GPL '
GPL2
REMARKS
128 bytes/Sector
00
01
02
1,,-{16)
OF(16)
07(16)
OE(16)
1B(16)
18(16)
2A(16)
3,,-{16)
IBM Diskette 1
2046
4096
03
04
05
04
02
01
-
-
-
256
512
1024
2048
4096
8192
01
02
03
04
05
08
1A(16)
OF(16)
06
O~16)
1B(16)
35(16)
36(16)
54(16)
74(16)
04
02
01
-
256
512
1024 bytes/Sector
FM Mode
MFM Mode
06
-
IBM Diskette 2
-
-
IBM Diskette 20
IBM Diskette 20
Note: 1. Suggested val~es of GPL in Read or Write Commands to avoid splice point
between data field and 10 field of contiguous sections.
2. Suggested values of GPL in format command,
9-59
intel'
8272
When either the STP (contiguous sectors STP = 01, or
alternate sectors STP = 02 sectors are read) or the MT
(Multi-Track) are programmed, it is necessary to
remember that the last sector on the track must be read.
For example, if STP = 02, MT = 0, the sectors are
numbered sequentially 1 through 26, and we start the
Scan Command at sector 21; the following will happen.
Sectors 21, 23, and 25 will be read, then.the next sector
(26) will be skipped and the Index Hole will be en·
countered before the EOT value of 26 can be read. This
will result in an abnormal termination of the command.
If the EOT had been set at 25 or the scanning started at
sector 20, then the Scan Command would be completed
in a normal manner.
SCAN COMMANDS
The SCAN Commands allow data which is being read
from the diskette to be compared against data which is
being supplied from the main system (Processor in
NON-DMA mode, and DMA Controller in DMA mOde).
The FDC compares the data on a byte-by-byte basis, and
looks for a sector of data which meets the conditions of
DFDD = Dprocessor, DFDD';; Dprocessor, or DFDD;;' Dprocessor·
Ones complement arithmetic is used for comparison
(FF = largest number, 00 = smallest number). After a
whole sector of data is compared, if the conditions are
not met, the sector number is incremented (R + STP -+
R), and the scan operation is continued. The scan opera·
tion continues until one of the following conditions oc·
cur; the conditions for scan are met (equal, low, or high),
the last sector on the track is reached (EOT), or the terminal count signal is received.
During the Scan Command data is supplied by either the
processor or DMA Controller for comparison against the
data read from the diskette. In order to avoid having the
OR (Over Run) flag set in Status Register 1, it is necessary to have the data available in less than 27 JJs (FM
Mode) or 13 JJS (MFM Mode). If an Overrun occurs the
FDC terminates the command.
If the conditions for scan are met then the FDC sets the
SH (Scan Hit) flag of Status Register 2 to a 1 (high), and
terminates the Scan Command. If the conditions for
scan are not met between the starting sector (as
specified by R) and the last sector on the cylinder (EOT),
then the FDC sets the SN (Scan Not Satisfied) flag of
Status Register 2 to a 1 (high), and terminates the Scan
Command. The receipt of a TERMINAL COUNT signal
from the Processor or DMA Controller during the scan
operation will cause the FDC to complete the com·
parison of the particular byte which is in process, and
then to terminate the command. Table 6 shows the
status of bits SH and SN under various conditions of
SCAN.
SEEK
The read/write head within the FDD is moved from
cylinder to cylinder under control of the Seek Command.
The FDC compares the PCN (Present Cylinder Number)
which is the current head position with the NCN (New
Cylinder Number), and performs the following operation
if there is a difference:
PCN < NCN: Direction signal to FDD set to a 1 (high),
and Step Pulses are issued. (Step In.)
PCN > NCN: Direction signal to FDD set to a 0 (low),
and Step Pulses are issued. (Step Out.)
TABLE 6. SCAN STATUS CODES
STATUS REGISTER 2
COMMAND
COMMENTS
BIT2=SN
BIT3=SH
Scan Equal
0
1
1
0
OF DO = OProcessor
OF DO =t= 0processor
Scan low or Equal
0
0
1
1
0
0
DFDD = Dprocessor
DFDD < Dprocessor
DFOD 1: Dprocessor
Scan Hlghor Equal
0
0
1
1
0
0
DFDD = Dprocessor
DFDD > Dprocessor
DFDD ~ Dprocessor
The rate at which Step Pulses are issued is controlled by
SRT (Stepping Rate Time) in the SPECIFY Command.
After each Step Pulse is issued NCN is compared
against PCN, and when NCN = PCN, then the SE (Seek
End) flag is set in Status Register 0 to a 1 (high), and the
command is terminated.
During the Command Phase of the Seek operation the
FDC is in the FDC BUSY state, but during the Execution
Phase it is in the NON BUSY state. While the FDC is in
the NON BUSY state, another Seek Command may be
issued, and in this manner parallel seek operations may
be done on up to 4 Drives at once.
If the FDC encounters a Deleted Data Address Mark on
one of the sectors (and SK = 0), then it regards the sec·
tor as the last sector on the cylinder, sets CM (Control
Mark) flag of Status Register 2 to a 1 (high) and ter·
minates the command. If SK= 1, the FDC skips the sec·
tor with the Deleted Address Mark, and reads the next
sector. In the second case (SK = 1), the FDC sets the CM
(Control Mark) flag of Status Register 2 to a 1 (high) in
order to show that a Deleted Sector had been en·
countered.
If an FDD is in a NOT READY state at the beginning of
the command execution phase or during the seek operation, then the NR (NOT READY) flag is set in Status
Register 0 to a 1 (high), and the command is terminated.
9-60
8272
Neither the Seek or Recalibrate Command have a Result
Phase. Therefore, it is mandatory to use the Sense Inter·
rupt Status Command after these commands to effec,
tively terminate them and to provide verification of the
head position (PCN).
RECALIBRATE
This command causes the read/write head within the
FDD to retract to the Track 0 position. The FDC clears
the contents of the PCN counter, and checks the status
of the Track 0 signal from the FDD. As long as the Track
signal is low, the Direction signal remains 1 (high) and
Step Pulses are issued. When the Track 0 signal goes
high, the SE (SEEK END) flag in Status Register 0 is set
to a 1 (high) and the command is terminated. If the Track
o signal is still low after 77 Step Pulses have been·
issued, the FDC sets the SE (SEEK END) and EC (EQUIP·
MENT CHECK) flags of Status Register 0 to both 1s
(highs), and terminates the command.
o
SPECIFY
The Specify Command sets the initial values for each of
the three internal timers. The HUT (Head Unload Time)
defines the time from the end of the Execution Phase of
one of the Read/Write Commands to the head unload
state. This timer is programmable from 16 to 240 ms in
increments of 16 ms (01 = 16 ms, 02 = 32 ms .... OF =
240 ms). The SRT (Step Rate Time) defines the time in·
terval between adjacent step pulses. This timer is pro·
grammable from 1 to 16 ms in increments of 1 ms (F = 1
ms, E = 2 ms, 0 = 3 ms, etc.). The HLT (Head Load Time)
defines the time between when the Head load signal
goes high and when the Read/Write operation starts.
This timer is programmable from 2 to 254 ms in in·
crements of 2 ms (01 = 2 ms, 02 = 4 ms, 03 = 6 ms ....
FE=254 ms).
The ability to overlap RECALIBRATE Commands to
multiple FDDs, and the loss of the READY signal, as
described in the SEEK Command, also applies to the
RECALIBRATE Command.
SENSE INTERRUPT STATUS
An Interrupt signal is generated by the FOC for one of
the following reasons:
1. Upon entering the Result Phase of:
a. Read Data Command
b. Read a Track Command
c. Read 10 Command
d. Read Deleted Oata Command
e. Write Data Command
f. Format a Cylinder Command
g. Write Deleted Data Command
h. Scan Commands
2. Ready Line of FOO changes state
3. End of Seek or Recalibrate Command
4. During Execution Phase in the NON·OMA Mode
The time intervals mentioned above are a direct function
of the clock (ClK on pin 19). Times indicated above are
for an 8 MHz clock, if the clock was reduced to 4 MHz
(mini·floppy application) then all time intervals are in·
creased by a factor of 2.
Interrupts caused by reasons 1 and 4 above occur during
normal command operations and are easily discernible
by the processor. However, interrupts caused by
reasons 2 and 3 above may be uniquely identified with
the aid of the Sense Interrupt Status Command. This
command when issued resets the interrupt signal and
via bits 5, 6, and 7 of Status Register 0 identifies the
cause of the interrupt.
This command may be used by the processor whenever
it wishes to obtain the status of the FDOs. Status
Register 3 contains the Drive Status information.
The choice of OMA or NON·DMA operation is made by
the NO (NON·OMA) bit. When this bit is high (NO = 1) the
NON·OMA mode is selected, and when NO = 0 the DMA
mode is selected.
SENSE DRIVE STATUS
INVALID
BIT6
BIT7
0
1
1
Ready Line changed
state, either polarity
If an invalid command is sent to the FOC (a command
not defined above), then the FDC will terminate the com·
mand. No interrupt is generated by the 8272 during this
condition. Bit 6 and bit 7 (010 and RQM) in the Main
Status Register are both high ("1") indicating to the
processor that the 8272 is in the Result Phase and the
contents of Status Register 0 (STO) must be read. When
the processor reads Status Register 0 it will find a 80H
indicating an invalid command was received.
1
0
0
Normal Termination
of Seek or Recalibrate
Command
A Sense Interrupt Status Command must be sent after a
Seek or Recalibrate interrupt, otherwise the FDC will
consider the next command to be an Invalid Command.
1
1
0
Abnormal Termination of
Seek or Recalibrate
Command
TABLE 7. SEEK, INTERRUPT CODES
SEEK END
BIT 5
INTERRUPT CODE
CAUSE
In some applications the user may wish to use this com·
mand as a No·Op command, to place the FOC in a stand·
by or no operation state.
9-61
inter
8272
TABLE 8. STATUS REGISTERS
BIT
NO.
NAME
BIT
DESCRIPTION
SYMBOL
NO.
NAME
STATUS REGISTER 0
07
Interrupt
Code
IC
STAtUS RE.GISTER , (CO NT.)
D7~Oand Ds~O
0,
Not
Writable
NW
During execution of WRITE DATA,
WRITE DELETED DATA or Format A
Cylinder Command, If the FDC
detects a write protect signal from
the FDD, then this flag Is set.
Do
MISSing
Address
Mark
MA
If tlie FDC cannot detect the 10
Normal Termination of Command,
(NT). Command was completed and
properly executed.
Os
07=0 and Ds='
Abnormal Termination of Com·
mand, (AT). Execution of Command
was started, but was not
successfully completed.
Address Mark after encountering the
Index hole twice, then this flag is set.
If the FOC cannot detect the Data
Address Mark or Deleted Data
Address Mark, this flag Is set. Also
at the sam.e time, the MD (Missing
Address Mark in Data Field) of
Status Register 2 is set.
0 7=' and Ds=O
Invalid Command issue, (I C).
Command which was issued was
never started.
0 7=' and Ds='
Abnormal Termination because
during command execution the
ready signal from FDD changed
STATUS REGISTER 2
CM
During executing the READ DATA or
SCAN Command, if the FOC
encounters a Sector which contains
a Deleted Data Address Mark, this
flag is set.
05
Data Error in
Data Field
00
If the FOC detects a CRC error In
the data field then this flag is set.
04
Wrong
Cylinder
WC
This bit is related with the NO bit,
and when the contents of C on the
medium is different from that stored
In the lOR, this flag is set.
03
Scan Equal
Hit
SH
During execution, the SCAN
Command, if the condition of
"equal" is satiSfied, this flag is set.
O2
Scan Not
Satisfied
SN
During executing the SCAN
Command, If the FDC cannot find a
Sector on the cylinder which meets
the condition, then this flag is set.
0,
Bad
Cylinder
BC
This bit is related with the NO bit,
and when the content of C on the
medium is different from that stored
In the lOR and the content of C is
FF, then this flag is set.
Do
Missing
Address
Mark In Data
Field
MD
When data Is read from the medium,
If the FOC cannot find a Data
Address Mark or Deleted Data
Address Mark, then this flag Is set.
07
Fault
FT
This bit Is used I" indicate the
status of the Fault signal from the
FDO.
Os
Write
Protected
WP
This bit Is used to indicate the
status of the Write Protected Signal
from the FDO.
05
Ready
ROY
This bit is used to indicate the status
of the Ready signal from the FDD.
During executing the READ 10 Com·
mand, if the FDC cannot read the
10 field without an error, then this
flag is set.
04
Track 0
TO
This bit is used to indicate the status
of the Track 0 signal from the FOO.
03
Two Side
TS
This bit is used to indicate the status
of the Two Side signal from the FDD.
During the execution of the READ A
Cylinder Command, if the starting
sector cannot be found, then this
flag is set.
02
Head
Address
HO
This bit is used to indicate the status
of Side Select signal to the FDD.
0,
Unit Select'
US,
This bit is used to Indicate the status
of the Unit Select' signal tothe FDD.
Do
Unit Select 0
usa
This bit is used to indicate the status
of the Unit Select 0 signal tothe FDD.
SE
When the FDC completes the
SEEK Command, this flag Is set to ,
(high).
04
Equipment
Check
EC
If a fault Signal is received from the
FDD, or If the Track 0 Signal fails to
occur after 77 Step Pulses (Recali·
brate Command) then this flag Is set.
Not Ready
NR
HD
0,
Unit Select'
US,
Do
Unit SelectO
usa
When the FDD is in the not· ready
state and a read or write command is
issued, this flag Is set. If a read or
write command is issued to Side 1
of a single sided drive, then this flag
is set.
This flag is used to Indicate the
state of the head at Interrupt.
These flags are used to indicate a
Drive Unit Number at Interrupt
STATUS REGISTER'
End of
Cylinder
EN
When the FDC tries to access a
Sector beyond the final Sector of a
Cylinder, this flag Is set.
05
Data Erwr
DE
When the FDC detects a CRC error
In either the 10 field or the data field,
this flag Is set.
04
Over Run
OR
If the FDC Is not serviced by the
main-systems during data transfers,
within a certain time Interval, this
flag Is set.
07
Not used. This bit is always 0 (low).
Os
03
O2
STATUS REGISTER 3
Not used. This bit always 0 (low).
No Data
NO
--~
Control
Mark
Seek End
Head
Address
----
06
05
O2
Not used. This bit is always 0 (low).
07
state.
03
DESCRIPTION
SYMBOL
During execution of READ DATA,
WRITE DELETED DATA or SCAN
Command, If the FDC cannot find
the Sector specified in the lOR
Register, this flag is set.
9-62
inter
8272
ABSOLUTE MAXIMUM RATINGS·
COMMENT: Stress above those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maxi·
mum rating conditions for extended periods may affect
device reliability.
Operating Temperature ............ -10·C to + 70·C
Storage Temperature ............. -40·C to + 125·C
All Output Voltages ............... -0.5 to + 7 Volts
All Input Voltages ................. -0.5 to + 7 Volts
Supply Voltage Vee ............... -0.5 to + 7 Volts
Power Dissipation .......................... 1 Watt
DC CHARACTERISTICS
TA=O·Cto +70·C;Vee= +5V±5%
LIMITS
SYMBOL
PARAMETER
MIN
MAX
UNIT
TEST
CONDITIONS
VIL
Input Low Voltage
-0.5
0.8
V
V IH
Input High Voltage
2.0
Vee+ 0.5
V
VIL
(CLK & WR CLK)
-0.5
0.65
V
VIH
(CLK & WR CLK)
2.4
Vee+ 0.5
V
VOL
Output Low Voltage
0.45
V
IOL=2.0 mA
VOH
Output High Voltage
Vee
V
IOH= -200,.A
Icc
Vee Supply Current
150
mA
IlL
Input Load Current
(All Input Pins)
10
-10
,.A
,.A
VIN = Vee
VIN=OV
ILOH
High Level Output
Leakage Current
10
,.A
Vour= Vee
ILOL
Low Level Output
Leakage Current
-10
,.A
VOUT = + 0.45V
MAX
UNIT
TEST
CONDITIONS
2.4
CAPACITANCE
TA=25·C; le= 1 MHz; Vee=OV
LIMITS
SYMBOL
PARAMETER
CIN(8
INT
SHIFT CNTL
INT
"0_7
voo
v..
DATA BUS
8-81T
MICRODATA
PROCESSOR
BUS
SYSTEM
~
iijj
CONTROLS {
WR
RESET
CS
ADDRESS {
BUS
CLOCK
c/o
ClK
DO_7
lOR
lOW
8 0 _3
8279
3
3-8 DECODER
Jv
~
3lsa
4/
SCAN LINES
RESET
(:'
4--16 DECODER
CS
c/o
CLK SO _
3
A O_ 3
BD
BLANK
I ~'~lAY
4
r;6
ADDRESSES
(DECODED)
DISPLAY
4
/
CHARACTERS
DATA
DISPLAY
FIGURE 2. GENERAL BLOCK DIAGRAM
9-77
AFN-00742A-08
8279, 8279-5
ABSOLUTE MAXIMUM RATINGS*
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functiona/operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Ambient Temperature ............... O°C to 70°C
Storage Temperature ........ , .... _65°C to 125°C
Voltage on any Pin with
Respect to Ground . . . . . . . • . . . . . . -0.5V to +7V
Power Dissipation . . . . . . . . . . . . . . . • . . . . . . 1 Watt
D.C. CHARACTERISTICS
Symbol
TA = o·e to 70·e, Vss = OV, Note 1
Parameter
Min.
Max.
Unit
V
VIL1
Input Low Voltage for Shift Control
and Return Lines
-0.5
1.4
VIL2
Input Low Voltage for All Others
-0.5
0.8
V 11-1 1
Input High Voltage for Shift, Control
and Return Lines
2.2
2.0
Test Cond itions
V
V
VIH2
Input High Voltage for All Others
VOL
Output Low Voltage
V
VOH
Output High Voltage on Interrupt
Line
IIL1
Input Current on Shift, Control and
Return Li nes
+10
-100
J.1A
fJ.A
VIN = Vee
VIN = OV
IIL2
Input Leakage Current on All Others
±10
fJ.A
VIN = Vee to OV
IOFL
Output Float Leakage
±10
fJ.A
VOUT = Vee to OV
Icc
Power Supply Current
120
mA
0.45
3.5
V
Note 2
V
Note 3
Notes:
1. 8279, Vee = +5V ±5%; 8279-5. Vee = +5V ±10%.
2. 8279, IOL = 1.6mA; 8279-5, IOL = 2.2mA.
3. 8279, IOH = -100,uA; 8279-5. IOH = -400,uA.
CAPACITANCE
SYMBOL
TEST
TYP.
MAX.
UNIT
Cin
Input Capacitance
5
10
pF
Vin = Vee
Cout
Output Capacitance
10
20
pF
Vout=Vee
9-78
TEST CONDITIONS
AFN-00742A-09
8279, 8279-5
A.C. CHARACTERISTICS
TA = O°C to 70°C, VSS = OV, (Note 1)
BUS PARAMETERS
READ CYCLE:
8279
Symbol
Parameter
Min.
8279·5
Max.
Min.
Max.
Unit
Address Stable Before READ
50
0
ns
tRA
Address Hold Time for READ
5
0
ns
tAR
ns
250
tRR
READ Pulse Width
tRol21
Data Delay from READ
420
300
150
ns
tAO[21
Address to Data Valid
450
250
ns
tOF
READ to Data Floating
100
ns
tRCY
Read Cycle Ti me
100
10
10
1
1
IlS
WRITE CYCLE:
8279·5
8279
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
tAW
Address Stable Before WR ITE
50
0
ns
tWA
Address Hold Time for WR ITE
20
0
ns
tww
WR ITE Pulse Width
400
250
ns
tow
Data Set Up Time for WR ITE
300
150
ns
two
Data Hold Time for WR ITE
40
0
ns
Notes:
1. 8279, VCC = +5V ±5%; 8279·5, VCC = +5V ±10%.
2. 8279, CL = 100pF; 8279-5, CL = 150pF.
OTHER TIMINGS:
8279
8279·5
Max.
Min.
Max.
Symbol
Parameter
Min.
t¢w
Clock Pu Ise Width
230
120
nsec
tCY
Clock Period
500
320
nsec
Keyboard Scan Time:
Keyboard Debounce Time:
Key Scan Time:
Display Scan Time:
Digit·on Time:
Blanking Time:
Internal Clock Cycle:
5.1 msec
10.3 msec
80llsec
10.3 msec
Unit
480llsec
160llsec
10 11 sec
INPUT WAVEFORMS FOR A.C. TESTS:
u=x
2.0
?
TEST POINTS
O.B
tI.4ti
9-79
<
2.0
O.B
x=
AFN-00742A-10
8279, 8279-5
WAVEFORMS
1. Read Operation
'--------------------
ISYSTEM'S
ADDR ESS BUS)
IREAD CONTROL)
DATA BUS
(OUTPUT)
~~~w.w.~~~w.W.;W~~----------_I~W.;W~~~W.;W~~~w.~
2. Write Operation
Y
J.M\. . ------------------
AO.a
'ww
tAw-II.
\
DATA
MAY CHANGE
-twA
~
. . . - - - tDw -
DATA BUS
(INPUT)
,
)(
(SYSTEM'S
ADDRESS BUS)
IWRITE CONTROL)
- - 'wD
-DATAVALID----.
X
DATA
MAY CHANGE
3. Clock Input
9-80
AFN-00742A-11
8279 SCAN TIMING
SCAN WAVEFORMS
L
S,
ENCODED
SCAN
L
L
S,
DECODED
SCAN
u
S,
S,
u
u
u
u
u
S'-U
u
u
u
u
u
u
Lf
DISPLAY WAVEFORMS
f-------640~s=84tCy·------·
ASSUME INTERNAL FREQUENCV = 100 kHz
SOtCy=10~s
So
S,
Ao- A3
ACTIVE HIGH
BLANK
CODE'
A(O)
BLANK
CODE·
A(1)
·BLANK CODe IS EITHER ALL
a's OR ALL 1', OR 20 HEX
80- 8 3
ACTIVE HIGH
RLo- RL7
NOTE: SHOWN IS ENCODED SCAN LEFT ENTRY
~·S3
ARE NOT SHOWN BUT THEY ARE SIMPLY 81 DIVIDED BY 2 AND 4
9-81
AFN-Q0742A-12
8291
GPIB TALKER/LISTENER
• Designed to Interface Microprocessors
(e.g., 8080, 8085, 8086, 8048) to an
IEEE Standard 488 Digital Interface
Bus
• 1-8 MHz Clock Range
• Programmable Data Transfer Rate
• Directly Interfaces to External NonInverting Transceivers for Connection
to the GPIB
• 16 Registers (8 Read, 8 Write), 2 for
Data Transfer, the Rest for Interface
Function Control, Status, etc.
• Complete Source and Acceptor
Handshake
• Provides Three Addressing Modes,
Allowing the Chip to be Addressed
Either as a Major or a Minor Talkerl
Listener with Primary or Secondary
Addressing
• Complete Talker and Listener
Functions with Extended Addressing
• Service Request; Paralle! Poll, Device
Clear, Device Trigger, Remote/Local
Functions
• DMA Handshake Provision Allows for
Bus Transfers without CPU Intervention
• Selectable Interrupts
• On-Chip Primary and Secondary
Address Recognition
• Trigger Output Pin
• On-Chip EOS (End of Sequence)
Message Recognition Facilitates
Handling of Multi-Byte Transfers
• Automatic Handling of Addressing and
Handshake Protocol
• Provision for Software Implementation
of Additional Features
The 8291 GPIB Talker/Listener is a microprocessor-controlled chip designed to interface microprocessors (e.g., 8048;
8080,8085,8086) to an IEEE Standard 488 Instrumentation Interface Bus. It implements all of the Standard's interface
functions except for the. controller.
PIN CONFIGURATION
BLOCK DIAGRAM
GPIB DATA
INTERFACE
FUNCTIONS ~===-=".
SH
GPIB CONTROL
AH
TE
LE
I
T/RCONTROL
9-82
TO NON-INVERTING
BUS TRANSCEIVERS
8291
PIN DESCRIPTION
Symbol
I/O
Pin No.
Do-D7
I/O
12-19
Data bus port, to be connected
to microprocessor data bus.
21-23
Register select inputs, to be connected to three non-multiplexed
microprocessor
address bus
lines. Select which of the 8 internal read (write) registers will
be read from (written into) with
the execution of RD (WR).
RSo-RS2
8
9
o
DREQ
o
DACK
Function
Symbol
I/O
Pin No.
NRFD
I/O
37
Not ready for data; GPIB handshake control line. Indicates the
condition of readiness of devicels) connected to the bus to
accept data.
I/O
38
Chip select. When low, enables
reading from or writing into the
register selected by RSo-RS2.
Not data accepted; GPIB handshake control line. Indicates the
condition of acceptance of data
by the device(s) connected to
the bus.
26
Read strobe. When low, selected
register contents are read by the
CPU.
Attention; GPIB command line.
Specifies how data on DIO lines
are to be interpreted.
24
Interface clear; GPIB command
line. Places the interface functions in a known quiescent state.
27
Service request; GPIB command
line. Indicates the need for
attention and requests an interruption of the current sequence
of events on the GPIB.
25
Remote enable; GPIB command
line. Selects (in conjunction with
other messages I remote or local
control of the device.
39
End or identify; GPIB command
line. Indicates the end of a
multiple byte transfer sequence
or, in conjunction with ATN,
addresses the device during a
polling sequence.
10
Write strobe. When low, data is
written into the selected register.
11
Interrupt request to the microprocessor, set high for request
and cleared when the appropriate register is accessed by the
CPU. May be software configured to be active low.
6
7
DMA request, normally low, set
high to indicate byte output or
byte input, in DMA mode; reset
by DACK.
DMA acknowledge. When low,
resets DREQ and selects data
in/data out register for DMA
data transfer (actual transfer
done by RD/WR pulse).
Must be high if DMA is not used.
5
Trigger output, normally low;
generates a triggering pulse with
1!,sec min. width in response to
the GET bus command or
Trigger auxiliary command.
CLOCK
3
External clock input, used only
for T 1 delay generator. May be
any speed in 1-8 MHz range.
RESET
4
Reset input. When high, forces
the device into an "Idle" (initialization) mode. The device will remain at "Idle" until released by
the microprocessor.
TRIG
0
8-bit GPIB data port, used for
bidirectional data byte transfer
between 8291 and GPIB via noninverting external line transceivers.
I/O
36
o
I/O
Function
T/R1
o
T/R2
o
2
External
transceivers control
line. Set high to indicate output
signals on the EOI line. Set low
to indicate expected input signal
on the EOI line during parallel
poll.
Vee
P.S.
40
Positive power supply (5V ±
10%).
GND
P.S.
20
Potential ground circuit.
External transceivers control
line. Set high to indicate output
data/signals on the D101-D108
and DAV lines and input signals
on the NRFD and NDAC lines
(active source handshake I. Set
low to indicate input data/
signals on the D101·D108 and
DAV lines and output signals on
the NRFD and NDAC lines (active acceptor handshake I.
Data valid; GPIB handshake
control line. Indicates the availability and validity of information on the DIO lines.
Note: All signals on the 8291 pins are specified with positive logic.
However, IEEE 488 specifies negative l~ on its 16 signal lines. Thus, the
data is inverted once from 00-07 to 0101-0108 and non-inverting bus
transceivers should be used.
9-83
8291
8291 SYSTEM DIAGRAM
r - I
- -,
OREO
DMA
c(g~il~~~LLE)R ..II~__D_AC_K_~L""::~~:::':'..J
L_____
I
THE GENERAL PURPOSE INTERFACE
BUS (GPIB)
The General Purpose Interface Bus (GPIB) is defined in
the IEEE Standard 488-1978 "Digital Interface for
Programmable Instrumentation." Although a knowledge
of this standard is assumed, Figure 1 provides the bus
structure for quick reference. Also, Tables 1 and 2
reference the interface state mnemonics and the interface
messages respectively. Modified state diagrams for the
8291 are presented in Appendix A.
rrr rr rr1
DEVICE A
ABLE TO
TALK, LISTEN,
AND
I
t-
I
r--
f
DATA BUS
CONTROL
(e.g. calculator)
DEVICE B
ABLE TO
TALK AND
LISTEN
GENERAL DESCRIPTION
The 8291 is a microprocessor controlled device designed to interface microprocessors e.g., 8048, 8080,
8085,8086 to the GPIB. It implements all of the interface
functions defined in the IEEE 488 Standard. If an implementation of the Standard's Controller function is
desired, it can be connected with an Intel® 8292 to form
a complete interface.
(e.g. digital
multimeterl
(I-t--
DATA BYTE
TRANSFER
CONTROL
DEVICE C
ONLY ABLE
TO LISTEN
I
t-
(e.g. signal
generator)
The 8291 handles communication between a microprocessor controlled device and the GPIB. Its capabilities include data transfer, handshake protOCOl, talkerllistener
addressing procedures, device clearing and triggering,
service request, and both serial and parallel polling
schemes. In most procedures, it does not disturb the
microprocessor unless a byte is waiting on input or a
byte sent on output (output buffer empty).
GENERAL
INTERFACE
MANAGEMENT
(
DEVICE 0
ONLY ABLE
TO TALK
I
t-
(e.g. counter)
~}DIOl . .. 8
The 8291 architecture includes 16 registers. Eight of these
registers may be written into by the microprocessor. The
other eight registers may be read by the microprocessor.
One each of these read and write registers is for direct data
transfers. The rest of the write registers control the various
features of the chip, while the rest of the read registers
provide the microprocessor with a monitor of GPIB states,
various bus conditions, and device conditions.
DAV
NRFD
NDAC
IFC
ATN
SRO
REN
EOI
Figure 1_ Interface Capabilities and Bus Structure_
9-84
8291
GPIB Addressing
second mode allows the user to implement a single
talker/listener with a two byte address (primary address +
secondary address). The third mode again allows for two
distinct addresses but in this instance, they can each have
a two-byte address. However, this mode requires that the
secondary addresses be passed to the microprocessor for
verification. These three addressing schemes are described in more detail in the discussion of the Address
registers.
Each device connected to the GPIB must have at least one
address whereby the controller device in charge of the bus
can configure it to talk, listen, or send status. An 8291
implementation of the GPIB offers the user three
addressing modes from which the device can be initialized
for each application. The first of these modes allows for
the device to have two separate primary addresses. The
TABLE 1.
IEEE 488 INTERFACE STATE MNEMONICS
Mnemonic
State Represented
Mnemonic
State Represented
ACDS
ACRS
AIDS
ANRS
APRS
AWNS
Accept Data State
Acceptor Ready State
Acceptor Idle State
Acceptor Not Ready State
Affirmative Poll Response State
Acceptor Wait for New Cycle State
PACS
PPAS
PPIS
PPSS
PUCS
Parallel
Parallel
Parallel
Parallel
Parallel
REMS
RWLS
Remote State
Remote With Lockout State
CADS
CAWS
CIDS
CPPS
CPWS
CSBS
CSNS
CSRS
CSWS
Controller
Controller
Controller
Controller
Controller
Controller
Controller
Controller
Controller
SACS
SDYS
SGNS
SIAS
SIDS
SIIS
SINS
SIWS
SNAS
SPAS
SPIS
SPMS
SRAS
SRIS
SRNS
SRQS
STRS
SWNS
System Control Active State
Source Delay State
Source Generate State
System Control Interface Clear Active State
Source Idle State
System Control Interface Clear Idle State
System Control Interface Clear Not Active State
Source Idle Wait State
System Control Not Active State
Serial Poll Active State
Serial Poll Idle State
Serial Poll Mode State
System Control Remote Enable Active State
System Control Remote Enable Idle State
System Control Remote Enable Not Active State
Service Request State
Source Transfer State
Source Wait for New Cycle State
TACS
TAOS
TIDS
TPIS
Talker
Talker
Talker
Talker
------------------------,
CACS
Controller Active State
I
I
:
I
I
I
I
:
I
I
I
L~T~~ _
Addressed State
Active Wait State
Idle State
Parallel Poll State
Parallel Poll Wait State
Standby State
Service Not Requested State
Service Requested State
Synchronous Wait State
~~t.':?~~TI:a~s!:.r~t~t~ ______
DCAS
DCIS
DTAS
OTIS
Device
Device
Device
Device
LACS
LADS
LIDS
LOCS
LPAS
LPIS
LWLS
Listener Active State
Listener Addressed State
Listener Idle State
Local State
Listener Primary Addressed State
Listener Primary Idle State
Local With Lockout State
NPRS
Negative Poll Response State
I
I
I
I
I
:
I
I
I
J
Clear Active State
Clear Idle State
Trigger Active State
Trigger Idle State
- - - - - - The Controller function is implemented on the Intel® 8292.
9-85
Poll
Poll
Poll
Poll
Poll
Addressed to Configure State
Active State
Idle State
Standby State
Unaddressed to Configure State
Active State
Addressed State
Idle State
Primary Idle State
8291
TABLE 2.
IEEE 488 INTERFACE MESSAGE REFERENCE LIST
Mnemonic
Message
Interlace Functlon(s)
LOCAL MESSAGES RECEIVED (By Interlace Functions)
·gts
ist
Ion
Ipe
nba
go to standby
individual status
listen only
local poll enable
new byte available
C
PP
L, LE
PP
SH
pon
rdy
• rpp
• rsc
rsv
power on
ready
request parallel poll
request system control
request service
SH,AH,T,TE,L,LE,SR,RL,PP,C
AH
C
C
SR
rtl
'sic
'sre
*tca
·tcs
ton
return to local
send interface clear
send remote enable
take control asynchronously
take control synchronously
talk only
RL
C
C
C
AH,C
T, TE
REMOTE MESSAGES RECEIVED
ATN
DAB
DAC
DAV
DCL
Attention
Data Byte
Data Accepted
Data Valid
Device Clear
SH,AH,T,TE,L,LE,PP,C
(Via L, LE)
SH
AH
DC
END
GET
GTL
lOY
IFC
End
Group Execute Trigger
Go to Local
Identify
Interface Clear
(via L, LE)
DT
RL
L,LE,PP
T,TE,L,LE,C
LLO
MLA
MSA
MTA
OSA
Local Lockout
My Listen Address
My Secondary Address
My Talk Address
Other Secondary Address
RL
L,LE,RL,T,TE
TE,LE,RL
T,TE,L,LE
TE
OTA
PCG
tPPc
t [PPD)
t [PPE]
Other Talk Address
Primary Command Group
Parallel Poll Configure
Parallel Poll Disable
Parallel Poll Enable
T, TE
TE,LE,PP
PP
PP
PP
• PPRN
tPPu
REN
RFD
RaS
Parallel Poll Response N
Parallel Poll Unconfigure
Remote Enable
Ready for Data
Request Service
(via C)
PP
RL
SH
(via L, LE)
[SOC]
SPD
SPE
'SaR
STB
Select Device Clear
Serial Poll Disable
Serial Poll Enable
Service Request
Status Byte
DC
T, TE
T, TE
(via C)
(via L, LE)
'TCT or [TCT]
UNL
Take Control
Un listen
C
L, LE
'These' messages are handled only by Intel's 8292.
tUndefined commands which may be passed to the microprocessor.
9-86
8291
TABLE 2. (Cont'd)
IEEE 488 INTERFACE MESSAGE REFERENCE LIST
Mnemonic
•• Interlace Functlon(s)
Message
REMOTE MESSAGES SENT
ATN
DAB
DAC
DAV
DCl
Attention
Data Byte
Data Accepted
Data Valid
Device Clear
END
GET
GTl
IDY
IFC
End
Group Execute Trigger
Go to local
Identify
Interface Clear
(via T)
(via C)
(via C)
C
llO
MlA or [MlA[
MSA or [MSA[
MTA or [MTA[
OSA
local lockout
My Listen Address
My Secondary Address
My Talk Address
Other Secondary Address
(via
(via
(via
(via
(via
C)
C)
C)
C)
C)
OTA
PCG
PPC
[PPD[
[PPE[
Other Talk Address
Primary Command Group
Parallel Poll Configure
Parallel Poll Disable
Parallel Poll Enable
(via
(via
(via
(via
(via
C)
C)
C)
C)
C)
PPRN
PPU
REN
RFD
ROS
Parallel Poll Response N
Parallel Poll Unconfigure
Remote Enable
Ready for Data
Request Service
PP
(via C)
T, TE
[SDC[
SPD
SPE
SRO
STB
Selected Device Clear
Serial Poll Disable
Serial Poll Enable
Service Request
Status Byte
(via
(via
(via
SR
(via
TCT
UNl
Take Control
Unlisten
(via C)
(via C)
C
(via T, TE)
AH
SH
(via C)
•• All Controller messages must be sent via Intel's 8292.
9-87
C
C
AH
C)
C)
C)
T, TE)
8291
8291 Registers
A bit-by-bit map of the 16 registers on the 8291 is
presented in Table 3. A more detailed explanation of each
of these registers and their functions follows. The access
of these registers by the microprocessor is accomplished
by using the es. RD, WR, and RSo-RS2 pins.
CS RD WR
Register
All Read Registers
0
All Write Registers
o
RSo-RS2
o
eee
eee
X
XXX
0
x
Don't Care
TABLE 3. 8291 REGISTERS
READ REGISTERS
REGISTER SELECT
CODE
RS2
I 017 I 016
015
014
013
012
RSl
Oil! 010
WRITE REGISTERS
RSO
o
! 007 ! 006
o05! 004
DATA IN
I CPT I APT
GET I END I DEC! ERR!
80
! 81
1
I CPT ! APT ! GET I ENO I DEC I ERR
o
I 0 I0
INTERRUPT STATUS 2
SROS I 56
I
S5
I 54
I
INTERRUPT ENABLE 2
! 53
S2
! 51
1
I 58
[rsv
56
TA
I MJMNI
o
I TO
I LO
I 0
ADDRESS STATUS
S2
JSYJ
I 0
I 0
I 0
AOMll AoMOI
ADDRESS MODE
[CPT71 CPT61 CPTS! CPT41 CPT3! CPT21 cpnl CPTO I
1
I CNT2l CNTll CNTOI COM41 COM31 COM21 COMll COMol
COMMAND PASS THROUGH
oTO
! S5 I S4 I S3
SERIAL POLL MODE
EOI I LPAS I TPAS I LA
Ion
I 81
oMAOloMAl1 SPAScl LLOC! REMC! AoSC I
SERIAL POLL STATUS
1 ton
80
INTERRUPT ENABLE 1
INT ! SPAS! LLO! REM! SPASC!LLOC I REMC! Aosci
S8
001 I 000
DATA OUT
INTERRUPT STATUS 1
I
003 I 002
AUX MODE
oLO I A05.01 A04.0! A03.0! A02.01 AOl.01
o
I
ARS
I oT
oL
I AD5 I A04 I A03
A02 I Aol
ADDRESS 0/1
ADDRESS 0
Ix
1
ADDRESS 1
I Ee7 ! EC6
EC5 I Ee4
I Ee3 I Ee2
Eel
I ECO
EOS
Data Registers
017
! 016
016
I 014
013
012
011
addressed to listen. Incoming information is separately
latched by this register, and its contents are not destroyed
by a write to the data-out register. The RFD (Ready for
Datal message is held false until the byte is removed from
the data In register, either by the microprocessor or by
DMA. The 8291 then completes the handshake automatically. In RFD/DAV holdoff mode (see Auxiliary Register
AI, the handshake is not finished until a command is sent
telling the 8291 to release the holdoff. In this way, the same
byte may be read several times, or an over anxious talker
may be held off until all available data has been processed.
I 010 I
DATA·IN REGISTER IORI
007 I 006 I 005 I 004 I 003 I 002 I 001 I 000 I
DATA·OUT REGISTER IOWI
The data-In register is used to move data from the GPIB to
the microprocessor or to memory when the 8291 is
9-88
8291
When the 8291 is addressed to talk, it uses the data-out
register to move data onto the GPIB. Upon a write to this
register, the 8291 initiates and completes the handshake
while sending the byte out over the bus. When the
RFO/OAV holdoff mode is in effect, data is held until the
release command is issued. Also, a read of the data-in
register does not destroy the information in the data-out
register.
I nterrupt Registers
I CPT I APT I GET I ENO
OEC I ERR
BO
I
BI
CPT I APT I GET I END I DEC I ERR
BI I
INTERRUPT ENABLE 1 I1W)
INTERRUPT STATUS 1 II R)
liNT I SPAS I LLO I REM I SPAscl LLOC
BO
IREMCI ADSC I
I 0
INTERRUPT STATUS 2 12R)
I 0
I DMAOI DMAI I SPAscl LLOC I REMCI ADscl
INTERRUPT ENABLE 2 (2W)
The 8291 can be configured to generate an interrupt to the
microprocessor upon the occurrence of any of 12
conditions or events on the GPIB. Upon receipt of an
interrupt, the microprocessor must read the Interrupt
Status registers to determine which event has occurred,
and then execute the appropriate service routine (if
necessary). Each of the 12 interrupt status bits has a
matching enable bit in the interrupt enable registers.
These enable bits are used to select the events that will
cause the INT pin to be asserted. Writing a logic "1" into
any of these bits enables the corresponding interrupt
status bits to generate an interrupt. Bits in the Interrupt
Status registers are set regardless of the states of the
enable bits. The Interrupt Status registers are then
cleared upon being read or when a local pon (power·on)
message is executed. If an event occurs while one of the
Interrupt Status registers is being read, the event is
typically held until after its register is cleared and then
placed in the register.
The mnemonics for each of the bits in these registers and a
brief description of their respective functions appears in
Table 4. This table also indicates how each of the interrupt
bits is set.
TABLE 4. Interrupt Bits
Indicates Undefined Commands
CPT
An undefined command has been received.
Set by (TPAS + LPAS)oSCGoACOSoMODE 3
APT
A secondary address must be ""assed through
to the microprocessor for recognition.
Set by DTAS
GET
A group execute trigger has occurred.
Set by (EOS + EOI)oLACS
END
An EOS or EOI message has been received.
Set by OCAS
DEC
Device Clear Active State has occurred.
Set by TACS.nbaoOAC.RFO
ERR
Interface error has occurred; no listeners
are active.
TACSo(SWNS + SGNS)
BO
A byte should be output. t
Set by LACS.ACOS
BI
A byte has been input.
Shows status of the INT pin
The device has been enabled for a serial poll
The device is in local lock out state.
(LWLS+RWLS)
The device is in a remote state.
(REMS+RWLS)
---
'----
INT
SPAS
LLO
~
These are status only. They will not generate
I- interrupts, nor do they have corresponding
mask bits.
SPAS-SPAS SPASC Serial Poll Active State change interrupt.t
LLCNO LLO
LLOC
Local lock out change interrupt.
Remoti:~Jocal
REMC
Remote/Local change interrupt.
AddressedUnaddressed
AOSC
Address status change interrupt:
--
tSee section on 8291A compatibility.
'In ton (talk-only) and Ion (listen·only) modes, no ADSC interrupt Is generated.
9-89
8291
The BO and BI interrupts enable the user to perform data
transfer cycles. BO indicates that a byte has been sent to
the GPIB or the 8291 has been addressed to talk. A new
data byte may be written into the Data Out register. It is set
by the occurrence of TACS. (SWNS + SGNS). Hence, it is
reset when a data byte is written into the Data Out register,
when ATN is asserted on the GPIB, or when the device
stops being addressed to talk. Similarly, BI is set when an
input byte is accepted into the 8291 and reset when the
microprocessor reads the Data In register. BO and BI are
also reset by pon (power-on local message) and by a read
of the Interrupt Status 1 register. However, if it is so
desired, data transfer cycles may be performed without
reading the Interrupt Status 1 register if all interrupts
except for 80 or BI are enabled; BO and BI will
automatically reset after each byte is transferred.
The CPT interrupt bit flags the occurrence of an undefined command and of all secondary commands following an undefined command. The Command pass
through feature is enabled by the BO bit of Auxiliary
register B.
UDC = [UCG + ACG(TADSoPPC
+ LADSoTCT)]oundefinedoBO
where:
ACG - Addressed Command Group
UCG - Universal Command Group
SCG - Secondary Command Group
Any message not decoded by the 8291 (not included in the
state diagrams in Appendix B) becomes an undefined
command. Note from the logic equation that any
addressed command is automatically ignored when the
8291 is not addressed.
If the 8291 is used without DMA, the BO and BI interrupts
may be enabled through the DREQ pin. The DMAO and
DMAI bits in the Interrupt Enable 2 register would be the
corresponding enable bits for this feature. Thus, implementing this feature, with 80 and Bi enabied from the
INT pin, allows for servicing of these interrupts without
reading the Interrupt Status registers.
Undefined commands are read by the CPU from the
Command Pass Through Register of the 8291. Until this
register is read, the 8291 will hold off the handshake (only
ii the CP I teatu re is enabled).
An especially useful feature of the 8291 is its ability to
generate interrupts from state transitions in the interface
functions. In particular, the lower 4 bits of the Interrupt
Status 2 register, if enabled by the corresponding enable
bits, will cause an interrupt upon changes in the following states as defined in IEEE 488:
The ERR bit is set to indicate the bus error condition where
the 8291 is an active talker, tries sending a byte to the
GPIB, but there are no active listeners (e.g., all devices on
the GPIB are in AIDS). The logical equivalent of (nba •
TACS • DAC • RFD) will set this bit.
Bit
Bit
Bit
Bit
The DEC bit is set whenever DCAS has occurred. The user
must define a known state to which all device functions
will return in DCAS. Typically this state will be a power-on
state. However, the state of the device functions at DCAS
is at the designer's discretion. It should be noted that
DCAS has no effect on the interface functions which are
returned to a known state by the IFC (interface clear)
message or the pon local message.
0
1
2
3
ADSC
RLC
LLOC
SPASC
change
change
change
change
in
in
in
in
LIDS or TIDS or MJMN
LOCS or REMS
LWLS or RWLS
SPAS
The upper 4 bits of the I nterrupt Status 2 register are
available to the processor as status bits. Thus, if one of the
bits 1-3 generates an interrupt indicating a state change
has taken place, the corresponding status bit (bits 5-7)
may be read to determine what the new state is. To
determine the nature of a change in addressed status (bit
0) the Address Status Register is available to be read. And
finally, bit 7 monitors the state of the 8291 INT pin.
Logically, it is an OR of all enabled interrupt status bits.
One should note that bits 4-7 of the Interrupt Status 2
Register do not generate interrupts, but are available
only to be read as status bits by the processor.
The END Interrupt bit may be used by the microprocessor
to detect that a mUlti-byte transfer has been completed.
The bit will be set when the 8291 is an active listener
(LACS) and either EOS or EOI is received. EOS will
generate an interrupt when the byte in the Data In register matches the byte in the EOS register. Otherwise the
interrupt will be generated when a true input is detected at
the EOI pin of the 8291.
Bits 4 and 5 (DMAI, DMAO) of the Interrupt Enable 2
Register are available to enable direct data transfers
between memory and the GPIB, DMAI (DMA in) enables
the DREQ (DMA request) pin of the 8291 to be asserted
upon the occurrence of 81. Similarly, DMAO (DMA out)
enables the DREQ pin to be asserted upon the occurrence
of BO. One might note that the DREQ pin may be used as
a second interrupt output pin, monitoring BI and/or BO
and enabled by DMAI and DMAO. One should note that
the DREQ pin is not affected by a read of the Interrupt
Status 1 Register. It is reset whenever a byte is written to
the Data Out Register or read from the Data In Register.
The GET interrupt bit is used by the microprocessor to
detect that DTAS has occurred. It is set by the 8291 when
the GET message is received while it is addressed to listen. The TRIG output pin of the 8291 is also asserted
when the GET message is received. Thus, the basic
operation of the device may be started without involving
the microprocessor.
The APT interrupt bit indicates to the processor that a
secondary address is available in the CPT register for
validation. This interrupt will only occur if Mode 3
addressing is in effect. (Refer to the section on
addressing.) In Mode 2, secondary addresses will be
recognized on the 8291. They will be ignored in Mode 1.
To ensure that an interrupt status bit will not be cleared
without being read, and will not remain uncleared after
being read, the 8291 Irnplem~Jnts a special Interrupt
9-90
8291
handling procedures. When an enabled interrupt bit is
set in either of the Interrupt Status Registers, the Input
of the registers are blocked until the set bit is read and
reset by the microprocessor. Thus, potential problems
arise when interrupt status changes while the register is
being blocked. However, the 8291 stores all new Interrupts in a temporary register and transfers them to the
appropriate interrupt Status Register after the interrupt
has been reset. In the Interrupt Status 1 Register and in
AOSC bit, this transfer takes place only if the corresponding bits were read as zeroes. For the other status
change bits In the Interrupt Status 2 Register, the
transfer will always take place. However, even number
of changes In these status bits during blocking time will
cause no Interrupt.
Serial Poll Registers
S8
5Ras
! 56
55
54
53
52
58
51
rsv
56
55
54
53
52
51
SERIAL POLL MODE 13W)
SERIAL POLL STATUS 13R)
The Serial Poll Mode Register is used to establish the
status byte that the 8291 sends out on the GPIB data lines
when it receives the SPE I Serial Poll Enable I message. Bit
6 of this register is reserved for the rsv I request service}
local message. Setting this bit to 1 causes the 8291 to
assert its SRO line, indicating its need for attention from
the controller-in-charge of the GPIB. When service has
been granted, the bit should be cleared by the
microprocessor. The other bits of this register are
available for sending status information over the GPIB.
Sometime after the microprocessor initiates a request for
service by setting bit 6, the controller of the GPIB
sends the SPE message and then addresses the 8291 to
talk. At this point, one byte of status is returned by the 8291
via the Serial Poll Mode Register.
The Serial Poll Status Register is available for reading the
status byte in the Serial Poll Mode Register. The processor
may check the status of a request for service by polling bit
6 of this register, which corresponds to SROS IService
Request State I. When a Serial Poll is conducted and the
controller-in-charge reads the status byte, the SROS bit is
cleared. The SRO line is tied to this bit, so that a request for
service is terminated when the 8291 's status byte is read.
The rsv bit of the Serial Poll Mode Register must then be
cleared by the microprocessor.
Address Registers
I ton
Ion
EOI
I TO
!LPAS ! TPAS !LA '[ TA !MJMN!
ILO I 0 I 0 I 0 I 0
ADDRESS STATUS 14R)
IX
OTO! OLO! AOS.O! A04.0! AD3.0! AD2.0! AD,.O !
! ARS ! DT
ADDRESS 0 16R)
IX
on
ADM'I AOMOI
ADDRESS MODE 14WI
DL
I ADS I AD41
AD3! AD2! AD1
ADDRESS Oil 16WI
DL1! ADS"! AD4.1! AD3.'! AD2.1! AD,., !
ADDRESS 1 17R)
The Address Mode Register is used to select one of the five
modes of addressing available on the 8291. It determines
the way in which the 8291 uses the information in the
Address 0 and Address 1 registers:
To use Mode 2 addressing the primary address must be
loaded into the Address 0 Register, and the Secondary
address is placed in the Address 1 Register. With both
primary and secondary addresses residing on chip, the
8291 can handle all addressing sequences without
processor intervention.
-In Mode 1, the contents of the Address 0 Register
constitute the "Major" talkerllistener address while tne
Address 1 Register represents the "Minor" talker/listener
address. In applications where only one address is
needed, the major talker/listener is used, and the minor
talker/listener should be disabled. Loading an addres via
the Address 0/1 Register into Address Registers 0 and 1
enables the major and minor talker/listener functions
respectively.
-In Mode 3, the 8291 handles addressing just as it does in
Mode 1, except that each Major or Minor primary address
must be followed by a secondary address. All secondary
addresses must be verified by the microprocessor when
Mode 3 is used., When the 8291 is in TPAS or LPAS
(talker/listener primary addresses statel, and it does not
recognize the byte on the 010 lines, an APT interrupt is
generated (see section on Interrupt Registers) and the
byte is available in the CPT (Command Pass-Through)
Register. As part of its interrupt service routine, the
microprocessor must read the CPT Register and write one
of the following responses to the Auxiliary Mode Register:
-In Mode 2 the 8291 recognizes two sequential address
bytes: a primary followed by a secondary. Both address
bytes must be received in order to enable the device to talk
or listen. In this manner, Mode 2 addressing implements
the extended talker and listener functions as defined in
IEEE 488.
1. 07H implies a non-valid secondary address
2. OFH implies a valid secondary address
9-91
8291
Setting the "ton" bit generates the local ton (talk-only)
. message and sets the 8291 to a talk-only mode. This mode
allows the device to operate as a talker in an interface
system without a controller.
Setting the "Ion" bit generates the local Ion (listen-only)
message and sets the 8291 to a listen-only mode. This
mode allows the device to operate as a listener in an
interface system without a controller.
Data
RSZ-RSO
1.. Select addressing Mode 1 0
Operation
1
0
00000001
100
2. Load major address into 0
Address 0 Register with
listener function disabled.
1
0
001AAAAA
110
3. Load minor address into
Address 1 Register with
talker function disabled.
1
0
110BBBBB
110
The mode of addressing implemented by the 8291 may be
selected by writing one of the following bytes to the
Address Mode Register:
Register Contents
10000000
01000000
11000000
00000001
00000010
00000011
Mode
The Address 0/1 Register is used for specifying the
device's addresses according to the format selected in
the Address Mode Register. Five bit addresses may be
loaded into the Address 0 and Address 1 registers by
writing into the Address 0/1 Register. The ARS bit is used
to select which of these registers the other seven bits will
be loaded into. The DT 'and DL brts may be used to disable
the talker or lis.tener function at the address Signified by
the other five bits. When Mode.l addressing is used and
only one primary address is desired, both the talker and
the listener should be disabled at the Minor address.
0
At this point, the addresses AAAAA and BBBBB are stored
in the Address 0 and Address 1 registers respectively, and
are available to be read by the microprocessor. Thus, it is
not necessary to store any address information elsewhere.
Also, with the information stored in the Address 0 and
Address 1 registers, processor intervention is not required
to recognize addressing by the controller. Only in Mode3,
where secondary addresses are passed through, must the
processor intervene in the addressing sequence.
Enable talk only mode (ton)
Enable listen only mode (Ion)
The 8291 may talk to itself
Mode 1, (Primary-Primary)
Mode 2 (primary-Secondary)
Mode 3 (primary/APT-Primary/APT)
The Address Status Registercontains information used by
the microprocessor to handle its own addressing. This
information includes status bits that monitor the address
state of each talker/listener, "ton" and "Ion" flags which
indicate the talk only and listen only states, and an EOI bit
which, when set, signifies that the END message came
with the last data byte. LPAS and TPAS indicate that the
listener or talker primary address has been received. The
microprocessor can then use these bits when the
secondary address is passed through to determine
whether the 8291 is addressed to talk or listen. The LA
(listener addressed) bit will be set when the 8291 is in
LACS (Listener Active State) or in LADS (Listener
Addressed State). Similarly, the TA (Talker Addressed bit
will be set to indicate TACS or TAOS, but also to indicate
SPAS (Serial Poll Active State). The MJMN bit is used to
determine whether the information in the other bits
applies to the Major or Minor talker/listener. It is set to "1"
when the Minor talker/listener is addressed. It should be
noted that only one talker/listener may be active at any
one time. Thus, the MJMN bit will indicate which, if either,
of the talker/listeners is addressed or active.
CS RD WR
Command Pass Through Register
I~I~I-I~I~I~I~I~I
COMMAND PASS THROUGH (5RI
The Command Pass Through Register is used to transfer
undefined 8-bit remote message codes from the GPIB to
the microprocessor. When the CPT feature is enabled
(bit BO in Auxiliary Register B), any message not decoded by the 8291 becomes an undefined command.
When Mode 3 addressing is used secondary addresses
are also passed through the CPT Register. In either
case, the 8291 will holdoff the handshake until the
microprocessor reads this register and issues the
VSCMD auxiliary command.
The CPT and APT interrupts flag the availability of
undefined commands and secondary addresses in the
CPT Register. The details of these interrupts are explained
in the section on Interrupt Registers.
An added feature of the 8291 is its ability to handle
undefined secondary commands following undefined
primaries: Thus, the number of available commands for
future IEEE 488 definition is increased; one undefined
primary command followed by a sequence of as many as
32 secondary commands can be processed. The IEEE-488
Standard does. not permit users to define their own
commands, but upgrades of the standard are thus
.provided for.
The recommended use o.f the 8291 's undefined command
capabilities is for a controller-configured Parallel Poll.
The PPC message is an undefined primary command
typically followed by PPE, an undefined secondary
command. For details on this procedure, refer to the
.
section on Parallel Poll Protocol.
As an example of how the Address 0/1 Register might be
used, consider an example where t.wo primarY'addresses
are .needed in the device. The Major primary address will
be selectable only ass lalker and the Minor primary
address will be selectable only· as a listener. This
configuration of the 8291 is fo.rmed by the following
sequence of writes by. the microprocessor:
9-92
8291
Auxiliary Mode Register
I
CNT21 CNT1
4-Blt Code
I I
I I
CNTO COM41 COM31 COM21 COM' COMO
AUX MODE (5W)
CNTO-2:CONTROL BITS
COMO-4:COMMAND BITS
The "0000" pon is an immediate execute
command (a pon pulse). It is also used to
release the "initialize" state generated by
either an external reset pulse or the "0010"
Chip Reset.command.
The Auxiliary Mode Register contains a three-bit control
field and a five-bit command field. It is used for several
purposes on the 8291:
1. To load "hidden" auxiliary registers on the 8291.
2. To issue commands from the microprocessor to the
8291.
3. To preset an internal counter used to generate T1,
delay in the Source Handshake function, as defined in
IEEE 488.
Table 5 summarizes how these tasks are performed with
the Auxiliary Mode Register. Note that the three control
bits determine how the five command bits are interpreted.
0010
Chip Reset (Initialize) - This command has
the same effect as a pulse applied to the Reset
pin. (Refer to the section on Reset Procedure.)
0011
Finish Handshake - This command finishes a
handshake that was stopped because of a
holdoff on RFD or DAV. (Refer to Auxiliary
Register A.)
0100
Trigger - A "Group Execute Trigger" is
forced by this command. It has the same effect
as a GET command issued by the controllerin-charge of the GPIB, but does not cause a
GET interrupt.
rtl t - This command corresponds to the local
rtl message as defined in IEEE 488. The 8291
will go to a local state if local lockout is not in
effect.
TABLE 5
CODE
COMMAND
CONTROL COMMAND
BITS
BITS
000
OCCCC
Execute auxiliary command
ccee
001
OFFFF
Preset internal counter to
match external clock
frequency of FFFF MHz
(FFFF - binary representation
of 1 to 8 MHz)
100
DDDDD Write DDDDD into auxiliary
register A
101
ODDDD
Write DDDD into auxiliary
register B
011
USP3P2Pi Enable/disable parallel poll
either in response to remote
messages (PPC followed by
PPE or PPD) or as a local
Ipe message. (Enable if U 0,
disable if U = 1.)
0101
0110
The valid (1111) command is also used to tell
the 8291 to continue from the command-passthrough state (immediate execute command).
AUXILIARY COMMANDS
Auxiliary commands are executed by the 8291 whenever
OOOOCCCC is written into the Auxiliary' Mode Register,
where ecce is the 4-bit command code.
0000
Send EOI - The EOI line of the 8291 may be
asserted with this command. The command
causes EOI to go true with the next byte transmitted. The EOlline is then cleared upon completion of the handshake for that byte.
0111, 1111 Non-Valid/Valid Secondary Address or
Command (VSCMD) - This command informs the 8291 that the secondary address received by the microprocessor was valid or
invalid (0111 - invalid, 1111 - valid). If Mode3
addressing is used, the processor must field
each extended address and respond to it, or
the GPIB will hang up. Note that the COM3 bit
is the invalid/valid flag.
=
4-Blt Code
Description
The 8291 is designed to power up in certain
states as spec,ified in the IEEE 488 state diagrams. Thus, the following states are in effect
in the power upstate: SIDS, AIDS, TIDS, LIDS,
NPRS, LOeS, and PPIS.
Descri tion
Immediate Execute pon - This command re. sets the 8291 to a power up state (local pon
.' message as defined in IEEE 488).
The following conditions constitute the power
up state:
1. All talkers and listeners are disabled.
2. No interrupt status bits are set.
0001, 1001 Parallel Poll Flag (local "ist" message) - This
command sets (1001) or clears (0001) the
parallel poll flag. A "1" is sent over the
assigned data line (PPR-Parallel Poll Response true) only if the parallel poll flag
matches the sense bit from the'lpe local
message (or indirectly from the PPE message). For a more complete description of the
Parallel Poll features and procedures refer to
the section on ParaHel Poll Protocol.
ISee section on 8291A compatibility.
9-93
8291
INTERNAL COUNTER
A2 - End on EOS Received: Whenever the byte in the Data
In Register matches the byte in the EOS Register, the End
interrupt bit will be set inthe Interrupt Status 1 Register.
The Internal counter determines the delay time allowed
for the settling of data on the DIO lines. This delay time
is defined as T1 In IEEE 488 and appears in the Source
Handshake state diagram between SDYS and STRS. As
such, DAV is asserted T1 after the DIO lines are driven.
Consequently, T1 is a major factor In determining the
data transfer rate of the 8291 over the GPIB
(T1 = TWRDV2-TWRD15).
A3 - Output EOI on EOS ~ent: Any occurrence of data in
the Data Out Register matching the EOS Register causes
the EOI line to be sent true along with the data.
A4 - EOS 8inary Compare: Setting this bit causes the
EOS Register to function as a full8·bit word. When it is not
set, the EOS Register is a 7·bit word Ifor ASCII
characters I.
When open-collector transceivers are used for connection
to the GPIB, T1 is defined by IEEE 488 to be 2!,sec. 8y
writing 0010FFFF into the Auxiliary Mode Register, the
counter is preset to match a fc MHz clock input, where
FFFF is the binary representation of NF 11 SNFS8,
NF=I FFFFI2J.· When NF = fc, a 2!,sec T1 delay will be
generated before each DAV asserted.
If Ao = A, = 1, a special "continuous Acceptor Handshake
cycling" mode is enabled. This mode should be used only
in a controller system configuration, where both the 8291
and the 8292 are used. It provides a continuous cycling
through the Acceptor Handshake state diagram, requiring
no local messages from the microprocessor; the rdy local
message is automatically generated when in ANRS. As
such, the 8291 Acceptor Handshake serves as the
controller Acceptor Handshake. Thus, the controller
cycles through the Acceptor Handshake, without delaying
the data transfer in progress. When the tcs local message
is executed, the 8291 is taken out of the "continuous AH
cycling" mode, the GPI8 hangs up in ANRS, and a 81
interrupt is generated to indicate that control may be
taken. A simpler procedure may be used when a "tcs on
end of block" is executed; the 8291 may stay in
"continuous AH cycling". Upon the end of a block (EOI or
EOS received" a holdott is generated, the GPI8 hangs up
in ANRS, and control maybe taken.
2NF
-- + t SYNC ' 1"NF,,8
fc
tSYNC is a synchronization error, greater than zero and
smaller than the larger of T clock high and T clock low.
I For a 50% duty cycle clock, tSYNC is less than half the
clock cyclel.
If it is necessary that T1 be different from 2!,sec, NF may
be set to a value other than fc.ln this manner, data transfer
rates may be prpgrammed for a given system. In small
systems, for example, where transfer rates exceeding
GPIB specifications are required, one may set NF < fc and
decrease T1.
When tri·state transceivers are used, IEEE 488 allows a
higher transfer rate dower T11. Use of the 8291 with such
transceivers is enabled by setting B2 in Auxiliary Register
B.ln this case, setting NF = fc causes a T 1delay of 2!,sec to
be generated for the first byte transmitted - all
subsequent bytes will have a delay of 500 nsec.
T11 High Speed I !,sec
= ~~ + tSYNC
Bo - Enable Undefined Command Pass Through: This
feature allows any commands not recognized by the 8291
to be handled in software. If enabled, this feature will
cause the 8291 to holdott the handshake when an
undefined command is received. The microprocessor
must then read the command from the Command Pass
Through Register and send the VSCMD auxiliary
command. Until the VSCMD command is sent, the
handshake holdoff will be in effect.
Thus, setting N'F = 1 using a8 MHz clock will generate for a
50% duty cycle clock (tSYNc<63 nsec):
T1(HS)
AUXILIARY REGISTER B
Auxiliary Register 8 is a "hidden" 4·bit register which is
used to enable some of the features of the 8291. Whenever
a 101083B28180 is written into the Auxiliary Mode
Register, it is loaded with the data 83828,60. Setting the
respective bits to "1" enables the following features:
=2~8 + 0.063 = 125 nsec max.
AUXILIARY REGISTER A
B1 - Send EOI in SPAS: This bit enables EOI to be sent
with the status byte; EOI is sent true in Serial Poll Active
State. Otherwise, EOI is sent false in SPAS.
Auxiliary Register A is a "hidden" 5-bit register which is
used to enable some of the 8291 features. Whenever a
100 A4A3A2A 1Ao byte is written into the Auxil iary Register,
it Is loaded with the data A4A3A2A1Ao. Setting the
respective bits to "1" enables the following features:
82 - Enable High Speed Data Transfer: This feature may
be enabled when tri-state external transceivers are used.
The data transfer rate is limited by T1 (delay time
generated in the Source Handshake function', which is
defined according to the type of transceivers used. When
the "High Speed" feature is enabled, T 1 = 2 microseconds
is generated for the first byte transmitter! after each true to
false transition of ATN. For all subsequent bytes, T1 =500
nanoseconds. Refer to the I nternal Counter section for an
explanation of T 1 duration as a function of B2 and of clock
frequency.
Ao - RFD/DAV Holdoff on all Data: Ifthe8291 is listening,
RFD will not be sent true until the "finish handshake"
auxiliary command is issued by the microprocessor. If the
8291 is talking, DAV is not sent true until the "finish
handshake" command is given. In both cases, the holdoff
will be in effect for each data byte.
A1 - RFD/DAV Holdoff on End: This feature enables the
holdott on EOI or EOS (if enabled). However, no holdoft
will be in effect on any other data bytes.
9-94
8291
End of Sequence (EaS) Register
B3 - Enable Active Low Interrupt: Setting this bit causes
the polarity of the I NT pin to be reversed, providing an
output signal compatible with Intel's MCS-48'". Interrupt
registers are not affected by this bit.
I
I
EC6
I
EC5
I
EC4
I
EC3
I
EC2
ECl
ECO
I
EOS REGISTER
The EOS Register and its features offer an alternative to
the "Send EOI" auxiliary command. A seven or eight bit
byte (ASCII or binary) may be placed in the register to flag
the end of a block or read. The type of EOS byte to be used
is selected in Auxiliary Register bit A4.
PARALLEL POLL PROTOCOL
Writing a 011USP3P2P, into the Auxiliary Mode Register
will enable (U 0) or disable (U 1) the 8291 for a parallel
poll. When U = 0, this command is the "Ipe" (local poll
enable) local message as defined in IEEE 488. The "S" bit
is the sense in which the 8291 is enabled; only if the
Parallel Poll Flag ("ist" local message) matches this bit
will the Parallel Poll Response, PPR N , be sent true
(Response = S~ ist). The bits P3P2P, specify which of
the eight data lines PPR N will be sent over. Thus, once
the 8291 has been configured for Parallel Poll, whenever
it senses both EOI and ATN true, it will automatically
compare its PP flag with the sense bit and send PPR N
true or false according to the comparison.
=
EC7
=
If the 8291 is a listener, and the "End on EOS Received" is
enabled at bit A2, then an End interrupt is generated in the
Interrupt Status 1 Register whenever the byte in the DataIn Register matches the byte in the EOS Register.
If the 8291 is a talker, and the "Output EOI on EOS Sent" is
enabled at bit A3, then the EOI line is sent true with the
next data byte whenever the contents of the Data Out
Register match the EOS register.
Reset Procedure
If a PP2' implementation is desired, the "Ipe" and "ist"
local messages are all that are needed. Typically, the user
will configure the 8291 for Parallel Poll immediately after
initialization. During normal operation the microprocessor will set or clear the Parallel Poll Flag (ist)
according to the device's need for service. Consequently
the 8291 will be set up to give the proper response to I DY
(EOI • ATN) without directly involving tne microprocessor.
The 8291 is reset to an initialization state either by a
pulse applied to its Reset pin, or by a reset auxiliary
command (02H written into the Auxiliary Command
Register). The following conditions are caused by a
reset pulse (or local reset command):
1. A "pon" local message as defined by IEEE 488 is held
true until the initialization state is released.
2_ The Interrupt Status Registers are cleared (not
Interrupt Enable Registers).
3. Auxiliary Registers A and B are cleared.
4. The Serial Poll Mode Register is cleared.
5. The Parallel Poll Flag is cleared.
6. The EOI bit in the Address Status Register is cleared.
7. NF in the Internal Counter is set to 8 MHz. This setting causes the longest possible t, delay to be
generated in the Source Handshake (16 I'sec for 1
MHz clock).
8. The rdy local message is sent.
If a PP1' implementation is desired, the undefined
command features of the 8291 must be used. In PP1, the
8291 is indirectly configured for Parallel Poll by the active
controller on the GPIB. The sequence at the 8291 being
enabled or disabled remotely is as follows:
1. The PPC message is received and is loaded into the
Command Pass Through Register as an undefined
command. A CPT interrupt is sent to the microprocessor, the handshake is automatically held off.
2. The microprocessor reads the CPT Register and sends
VSCMD to the 8291, releaSing the handshake.
The initialization state is released by an "immediate execute pon" command (OOH written into the Auxiliary
Command Register).
The suggested initialization sequence is:
3. Having received an undefined primary command, the
8291 is set up to receive an undefined secondary command (the PPE or PPD message). This message is also
received into the CPT Register, the handshake is held
off, and the CPT interrupt is generated.
1. Apply a reset pulse or send the reset auxiliary
command.
2. Set the desired initial conditions by writing into the Interrupt Enable, Serial Poll Mode, Address Mode,
Address 0/1, and EOS Registers. Auxiliary Registers A
and B, and the internal counter should also be
initialized.
3. Send the "immediate execute pon" auxiliary command
to release the initialization state.
4. If a PP2 Parallel Poll implementation is to be used the
"Ipe" local message may be sent, enabling the 8291
for a Parallel Poll Response on an assigned line. (Refer
to the section on Parallel Poll Protocol.)
4. The microprocessor reads the PPE or PPD message
and writes the command into the Auxiliary Mode
Register (bit 7 should be cleared first). Finally, the
microprocessor sends VSCMD and the handshake is
released.
'As defined in IEEE Standard 488.
9·95
8291
Using DMA
8291 to 8291A Software Compatibility
The 8291 may be connected to the Intel 8237 or 8257
DMA Controllers for DMA operation. The DREO pin of
the 8291 requests a DMA byte transfer from the 8237. It
Is set by BO or BI flip flops, enabled by the DMAO and
DMAI bits In the Interrupt Enable 2 Register. (After read·
ing, the INT1 register BO and BI interrupts will be
cleared but not BO and BI In DREO equation.)
Intel will be improving the 8291 by manufacturing an
8291A. To maintain software compatibility between the
8291 and the 8291A, the following precautions should
be taken In the 8291 software:
1. BO interrupt indicates that the 8291 is ready to talk
and needs a byte to output via the source handshake.
The software should ensure that BO is true before
writing a byte to the Data Out Register (even for the
first byte after being addressed to talk).
The DACK pin Is driven by the 8237 in response to the
DMA request. When DACK is true (active low) it sets CS =
RSO= RS1 = RS2=0 such that the m; and WR signals
sent by the 8237 refer to the Data In and Data Out Regis·
ters. Also, the DMA request line is reset by DACK.
2. SPASC interrupt should not be used during a Serial
Poll sequence to determine when the Status Byte has
been issued after a Service Request.
DMA input sequence:
1.
2.
3.
4.
A data byte is accepted from the GPIB by the 8291.
A BI interrupt is generated and DREO is set.
DACK is asserted by the 8237 and DREO is reset.
RD is driven bv the 8237 and the contents of the Data
In Register are transferred to MCS™ bus.
5. The 8291 sends RFD true on the GPIB and proceeds
with the Acceptor Handshake protocol.
Before setting rsv, SPAS in.register 2 should be zero.
After setting rsv, the processor should poll the SROS
bit in register 3, and when it is clear the Status Byte
has been Issued. The processor should then write an
rsv local message clearing rsv.
The definition of the SPASC interrupt will change in
the 8291 A. SPASC (Serial Poll Active State Change) in
the 8291 is set by a transition into or out of SPAS.
SPASC (Serial Poll Active State Complete) in the
8291A will be set only by the actual transfer of a
Status Byte (APRSxSTRSxSPAS).
DMA output sequence:
1. A BO interrupt is generated (indicating that th.e Data
Out Register is empty) and DREO is asserted.
2. DACK Is asserted by the 8237 and DREO is reset.
3. ii'm Is driven by the 8237 and a byte Is transferred from
the MCS bus Into the Data Out Register.
4. The 8291 sends DAV true on the GPIB and proceeds with
the Source Handshake protocol.
3. The 8291 rtl local message is set by the rtl Auxiliary
Command and is cleared automatically by the 8291.
The 8291A will have a Set rtl Auxiliary Command
(1101) and a Clear rtl Auxiliary Command (0101). Thus,
the 8291 programmer should write a Set rtl Auxiliary
Command followed by a Clear rtl Auxiliary Command
which will have the effect of writing two consecutive
rtl commands.
It should be noted that each time the device is addressed,
the Address Status Register should be read, and the 8237
should be initialized accordingly. (Refer to the 8237 or
8257 Data Sheets.)
System Configuration
4. User's software can distinguish between the 8291
and the 8291A as follows:
a) pon (OOH to register 5)
b) RESET (02H to register 5)
c) Read Interrupt Status Register 1. If BO interrupt is
set, the device is the 8291. If BO is clear, It is the
8291A.
Microprocessor Bus Connection
The 8291 is 8080, 8048, 8085, 8088, and 8086 compatible.
The three address pins (RSo. RS1, RS2) should be
connected to the non-mUltiplexed address bus (for
example: As. Ag, A10). In case of 8080, any address lines
may be used.
This can be used to set a.11ag in the user's software
which will permit special routines to be executed for
each device. It could be Included as part of a normal
initialization procedure as the first step after a chip
reset.
External Transceivers Connection
The 8293 GPIB Transceiver interfaces the 8291 directly to
the IEEE·488 bus. The 8291 and two 8293's can be con·
figured as a talker/listener (see Figure 2) or as with the
8292 as a talker/listener/controller (see Figure 3). Ab·
solutely no active or passive external components are required to comply with the complete IEEE·488 electrical
specification.
The 8291A will be a significant improvement over the
8291. Users should plan to convert to this product when
It is available.
9-96
8291
DEVICE ELECTRICAL CHARACTERISTICS
D.C. CHARACTERISTICS
TA = O°C to 70°C; Vee = 5V ± 10%
Symbol
Parameter
Min.
Max.
Unit
VIL
Input Low Voltage
-0,5
0,8
V
VIH
Input High Voltage
2
Vee+0,5
V
VOL
Output Low Voltage
0.45
V
VOH
Output High Voltage
2.4
V
IOH = -400f.lA 1-150f.lA for SRQ pin I
VOH-INT
Interrupt Output High Voltage
2.4
V
IOH=-4OOf.lA
IlL
I nput Leakage
10
f.lA
VIN=OV to Vee
ILOL
Output Leakage Current
-10
f.lA
VOUT=0.45V
ILOH
Output Leakage Current
10
f.lA
Vour=Vee
lee
Vee Supply Current
180
mA
TA=O°C
3,5
V
A.C. CHARACTERISTICS
Vee = 5V
± 10%,
Commercial: TA = O°C to 70°C
Symbol
Parameter
tAR
Address Stable Before READ
tRA
Address Hold After
tRR
READ width
tAD
Address Stable to Data Valid
250
nsec l11
tRD
READ to Data Valid
100
nse(;1 21
tRDF
Data Float After ~
0
tAW
Address Stable Before WRITE
0
Min.
R8\5
Max.
Unit
nsecl 11
0
0
nsec l11
140
nsec l21
60 121
nsec
nsecl 11
tWA
Address Hold After WRITE
tww
WRITE Width
170
tDW
Data Set Up Time to the Trailing
Edge of WRITE
150
nsec l1 1
tWD
Data Hold Time After~
0
nsecl 11
0
nsec l11
tAKRQ
DACKI to DREQI
130
nsec
tDKDA6
~I to Up Data Valid
200
nsec
Notes:
1, 8080 System CLm"x = 100pF: CLmin = 15pF; 3 MHz clock,
2, 8085 System CL = 150pF; 4 MHz clock,
9-97
Test Conditione
IOL=2mA (4mA for TR1 pin)
IOH=-5Of.lA
8291
TIMING WAVEFORMS
~/RSj
~
K
I'
IRR
!-IRA-
lAD
~
1iEAD:
I--IAR-
./
DATA BUS
(DATA OUT)
CS/RSj
"
I-IRO-
)(
"-
-J
-0
VALID DATA
.
IWW
I---IROF
"lot'
J(
[twA~
I--Iow --
]two~
~
I--IAW-+
DATA BUS
(DATA IN)
DREQ
).
DATA MAY CHANGE
K
DATA MAY CHANGE
~-------
----/
_ _ _ _ _ _-""""1
DACK
VALID DATA
\
9-98
" ..
8291
GPIB TIMINGSI'I
Symbol
Max.
Unit
TEOT13
~I to TRll
135
nsec
PPSS, ATN=0.45V
TEODI6
EOII to 010 Valid
155
nsec
PPSS, ATN=0.45V
TEOT12
EOI! to TR11
155
nsec
PPSS, ATN=0.45V
TATND4
ATNI to NDACI
155
nsec
TACS, AIDS
TATT14
ATNI to TRll
155
nsec
TACS, AIDS
TATT24
A"'i'N1 to TR21
155
nsec
TACS, AIDS
TDVND3-C
DAVI to NDACI
650
nsec
AH,CACS
TNDDV1
NDACI to DAVI
350
nsec
SH, STRS
TNRDV2
NRFDI to DAVI
350
nsec
SH, T1 True
TNDDR1
NDACI to DREQI
400
nsec
SH
AH, LACS, ATN=2.4V
Parameter
Test Conditions
TDVDR3
DAVI to DREQI
600
nsec
TDVND2-C
DAVI to NDACI
350
nsec
AH,LACS
TDVNR1-C
DAVlto~1
350
nsec
AH, LACS, rdy=True
TRDNR3
RD~
TWRDI5
\iV'Fi to
TWRDV2
WRt to i5'A\7~
to NRFDt
DIO Valid
830
Notes:
,. All GPIB timings are at the pins of the 829'.
9-99
500
nsec
AH, LACS
250
nsec
SH, TACS, RS=0.4V
+ tSYNC
nsec
High Speed Transfers Enabled,
NF = fc, tSYNC = 1/Nc
8291
Appendix A
MODIFIED STATE DIAGRAMS
ically true at 1001's
T9
C
Delay for EOI"
<:: 1.5l'stt
t
> 06
Time values specified by a lower case t indicate the maximum time allowed to make a state transition. Time values specified by an
upper case T indicate the minimum time that a function must remain in a state before exiting.
If three-state drivers are used on the 010, DAV, and EOI lines, T1 may be:
1. 2: 1100ns
2. Or 2: 700ns if it is known that within the controller ATN is driven by a three-state driver.
3. Or 2: 500ns for 'all subsequent bytes following the first sent after each false transition of ATN (the first byte must be sent in
accordance with, (1) or (2).
4. Or 2: 350ns for all subsequent bytes following the first sent 'after each false transition of ATN under conditions specified in
Section 5.2.3 and warning note. See IEEE Standard 488.
t Time required for interface functions to accept, not necessarily respond to interface messages.
{j Implementation independent.
•• Delay required for EOI, NDAC, and NRFD signal lines to indic,ate valid slates.
tt
2: 600ns for three-state drivers.
9-102
8291
Appendix C
THE THREE WIRE HANDSHAKE
-TWRD'5,
I
I
VALID
nL
NOT VALID
--
TDVNR1
f4-- TNDDV,-
J
-TRDNR3-
-
i--TDVND2
'I
I---TNDDR'l
DREOISH)
--TDVDR3
DREOIAH)
\
"-.J'
'0
Figure C-l. 3-Wire Handshake Timing at 8291.
9-103
VALID
I----
T,
-TWRDV2-
'---TNRDV2--"
}
-TDVND3-
I
8291
SOURCE
ACCEPTOR
YES
YES
OATA IS VALID AND MAY
NOW BE ACCEPTED
NDAC SIGNAL LINE STAYS LOW UNTIL
ALL ACCEPTORS HAVE ACCEPTED IT
DATA IS NOT TO BE CONSIDERED
VALID AFTER THIS TIME
NO
FLOW DIAGRAM OUTLINES SEaUENCE OF EVENTS DURING TRANSFER OF
DATA BYTE. MORE THAN ONE LISTENER AT A TIME CAN ACCEPT DATA
BECAUSE OF LOGICAL AND CONNECTION OF NRFD AND NDAC LINES.
Figure C.2. Handshake Flowchart.
8291
Appendix D
FUNCTIONAL PARTITIONS
A
I
1
I
~I
DEVICE (APPARATUS)
I
INTERFACE
FUNCTIONS
=~ -
:::(6):
DEVICE
FUNCTIONS
C
(8292 ONLY)
--
LL
DT
C
DC
/E
\
~
IT
\
\
\
\
~
MESSAGE
CODING
DRIVERS
AND
RECEIVERS
~
~INTERFACE
¢0):::: ------------K~~S
/
SR
/
/
\
:~
3
~
\
RL
-- ---------
3
\.
\
-----y
\
--
PP
~~C
\
\
I
L
OR ---LE-----
/
T
OR TE
I
I
i
AH
SH
i
-IIIL-_ _ _ _ _ _--,_ _ _ _ _ _ _--11 ,--I_--,--_-'
L -_ _---,-_ _ _
MCS'·
SYSTEM
8291
8293
A - CAPABILITY DEFINED BY THE 488-1978 STANDARD.
B - CAPABILITY DEFINED BY THE DESIGNER.
1 - INTERFACE BUS SIGNAL LINES.
2 - REMOTE INTERFACE MESSAGES TO AND FROM INTERFACE FUNCTIONS.
3 - DEVICE DEPENDENT MESSAGES TO AND FROM DEVICE FUNCTIONS.
4 - STATE LINKAGES BETWEEN INTERFACE FUNCTIONS.
5 - LOCAL MESSAGES BETWEEN DEVICE FUNCTIONS AND INTERFACE
FUNCTIONS (MESSAGES TO INTERFACE FUNCTIONS ARE DEFINED,
MESSAGES FROM INTERFACE fUNCTIONS EXIST ACCORDING TO THE
DESIGNER'S CHOICE).
6 - CONTROL MESSAGES (8292 ONLY).
Figure 0.1. Functional Partition Within a Device.
9-105
8292
GPIB CONTROLLER
• Complete IEEE Standard 488 Controller
Function
• Interface Clear (IFC) Sending Capability
Allows Seizure of Bus Control and/or
Initialization of the Bus
• Responds to Service Requests (SRQ)
• Sends Remote Enable (REN), Allowing
Instruments to Switch to Remote
Control
• Complete Implementation of Transfer
Control Protocol
• Synchronous Control Seizure Prevents
the Destruction of Any Data
Transmission in Progress
• Connects with the 8291 to Form a
Complete IEEE Standard 488 Interface
Talker/Listener/Controller
The 8292 GPIB Controller is a microprocessor-controlled chip designed to function with the 8291 GPIB Talker/Listener
to implement the full IEEE Standard 488 controller function, including transfer control protocol. The 8292 is a preprogrammed Intel® 8041A.
PIN CONFIGURATION
IFCL
X1
vcc
COUNT
X2
REN
RESET
DAV
VCC
Cs
IBFI
OBFI
GND
EOI
Rli
SPI
AO
TCI
WR
CIC
SYNC
8291,8292 SYSTEM DIAGRAM
:__IT_, ~.~"'''=.
I
I
I
I
"'no 00'
DACK
DMA
CONTROLLER
(OPTIONAL)
I
I
DREQ
L______ I
8291
GPIB
TALKER!
LISTENER
8292
GPIB
CONTROLLER
TiRl!
NC
DO
ATNO
D1
NC
D2
CLTH
D3
VCC
D4
NC
DS
SYC
D6
IFC
D7
/lTNI
VSS
SRQ
T!Ri
GENERAL PURPOSE INTERFACE BUS
9-106
00741C
8292
PIN DESCRIPTION
Symbol I/O Pin No.
IFCL
I
1
X1, X2
I
2, 3
Inputs for a crystal, LC or an exter·
nal timing signal to determine the
internal oscillator frequency.
RESET
I
4
Used to initialize the chip to a
known state during power on.
CS
I
6
Chip Select Input - Used to select
the 8292 from other devices on the
common data bus.
RD
I
8
I/O write input which allows the
master CPU to read from the 8292.
Ao
I
9
Address Line - Used to select between the data bus and the status
register during read operations
and to distinguish between data
and commands written into the
8292 during write operations.
WR
I
10
I/O read input which allows the
master CPU to write to the 8292.
SYNC
0
11
8041 A instruction cycle synchronization signal; it is an output
clock with a frequency of
XTAL ... 15.
Do-D7
I/O
12-19
8 bidirectional lines used for communication between the central
processor and the 8292's data bus
buffers and status register.
Vss
P.S.
7, 20
Circuit ground potential.
SRO
I
21
I
22
Attention In - Used by the 8292 to
monitor the GPIB ATN control
line. It is used during the transfer
control procedure.
IFC
I/O
23
Interface Clear - One of the GPIB
management lines, as defined by
IEEE Std. 488-1978, places all devices in a known quiescent state.
SYC
I
24
System Controller - Monitors the
system controller switch.
CLTH
0
27
CLEAR LATCH Output - Used to
clear the I FCR latch after being
recognized by the 8292. Usually
low (except after hardware Reset),
it will be pulsed high when IFCR is
recognized by the 8292.
0
29
Vee
39
Count Input - When enabled by
the proper command the internal
counter will count external events
through this pin. High to low transition will increment the internal
counter by one. The pin is sampled
once per three internal instruction
cycles (7.5I'sec sample period
when using 6 MHz XTAL). It can be
used for byte counting when con'
nected to NDAC, or for block
counting when connected to the
EOL
REN
0
38
The Remote Enable bus signal
selects remote. or local control of
the device on the bus. A GPIB bus
management line, as defined by
IEEE Std. 488-1978.
DAV
I/O
37
DAV Handshake Line - Used during parallel poll to force the 8291
to accept the parallel poll status
bits. It is also used during the tcs
procedure .
IBFI
0
36
Input Buffer Not Full - Used to
interrupt the central processor
while the input buffer of the 8292
is empty. This feature is enabled
and disabled by the interrupt
mask register.
OBFI
0
35
Output Buffer Full - Used as an
interrupt to the central processor
while the output buffer of the 8292
is full. The feature can be enabled
and disabled by the interrupt
mask register.
EOl2
I/O
34
End Or Identify - One of the GPIB
management lines, as defined by
IEEE Std. 488-1978. Used with ATN
as Identify Message during parallel poll.
SPI
0
33
Special Interrupt - Used as an
interrupt on events not initiated by
the central processor.
TCI
0
32
Task Complete Interrupt - Interrupt to the control processor used
to indicate that the task requested
was completed by the 8292 and
the information requested is ready
in the data bus buffer.
CIC
0
31
Controller In Charge - Controls
the SIR input of the SRO bus
transceiver. It can also be used to
indicate that the 8292 is in charge
of the GPIB bus.
...
Attention Out - Controls the ATN
control line of the bus through external logic for tcs and tca procedures. (ATN is a GPIB control
line, as defined by IEEE Std.
488-1978.)
9-107
Function
P.S. 5,26,40 +5V supply input. ± 10%.
I
COUNT
Service Request - One of the
IEEE control lines. Sampled by the
8292 when it is controller in
charge. If true, SPI interrupt to the
master will be generated.
ATNI
Ai1W
Symbol 1/0 Pin No_
Function
IFC Received (latched) - The 8292
monitors the IFC Line (when not
system controller) throOgh this
pin.
00741C
8293
GPIB TRANSCEIVER
.- Nine Open-coUector or Three-state
Line Drivers
• On-chip Decoder .for Mode
Configuration
• 48 mA Sink Current Capability on
Each Line Driver
• Power Up/Power Down Protection to
Prevent Disrupting the IEEE Bus
• Nine Schmitt-type Line R~ceivers
• Connects with the 8291 and 8292 to
Form an IEEE Standard 488 Interface
Talker/Listener/Controller with no
Additiona! Components
• High Capacitance Load Drive
Capability
• Single 5V Power Supply
• 28-Pin Package
• Only Two 8293'sRequired per GPIB
Interface
• Low Power HMOS Design
• On-Chip IEEE-488 Bus Terminations
The Intel'" 8293 GPIB Transceiver is a high current, non-inverting buffer chip designed to interface the. 8291 GPIB
Talker/Listener or the 6292 GPIB Controller with the 8291 to the I.EEE Standard 488-1978 Instrumentation Interface
Bus. Each GPIB interface would contain two 8293 Bus Transceivers. In addition, the 8293 can also be used as a general
purpose bus driver.
PIN CONFIGURATION
8291,8292,8293 SYSTEM DIAGRAM
Tllll
8292
EOI
3
GPIB
CONTROLLER
I,m
DATAl
TIRl
GENERAL PURPOSE INTERFACE BUS
9-108
8293
~[Q)W~OO©I§ OOOIF@rrulMl~lf'O@OO
PIN DESCRIPTION
Symbol
110 Pin No.
BUS1BUS9
I/O
12,13,
1S·19,
21,22
These are the IEEE-488 bus
interface driver/rece!vers.
Using the mode select pins,
they can be configured .dlffer·
ently to allow direct connec·
tions between the 8291 GPIB
Talker/Listener and the 8292
GPIB Controller.
OATA1OATA10
I/O
5·11,
23-2S
These are the pins to be con·
nected to the 8291 and 8292 to
interface with the GPIB bus.
Their use is programmed by
the two mode select pins,
OPTA and OPTB. All these
pins are TTL compatible.
Function
Transmit receive 1; this pin
controls the direction for
NOAC, NAFO, OAV, and 01010108. Input is TTL compatible.
T/R1
T/R2
2
Transmit receive 2; this pin
controls the direction for EOL
Input is TTL compatible.
Symbo.
110 Pin No;
EOI
I/O 3
ATN
0
4
Attention; this pin is used by
the 8291 to monitor the GPIB'
ATN control line. It specifies
how data on the 010 lines is to
be interpreted. This output is
TTL compatible.
o PTA
OPTB
I
27
26
These two pins are to control
the function of the 8293. A
truth table of how this programs the various modes is in
Table 1.
Vee
P.S. 28
Positive power supply (SV
± 10%).
GNO
P.S. 14,20
Circuit ground potential.
Function
End or Identify; this pin indio
cates the end of a multiple
byte .transfer or, In conjunc·
tion with ATN, addresses the
device during a polling se·
quence. It connects to the
8291 and is switched between
transmit and receive by T/R2.
. This pin is TTL compatible.
Table 1. 8293 Mode Selection Pin Mapping
IEEE Implementation Name
Pin No.
Mode 0
Mode 1
Mode 2
Mode 3
OPTA
OPTB
27
26
0
0
1
0
0
1
1
1
OATA1
BUS1
OATA2
BUS2
OATA3
BUS3
OATA4
BUS4
OATAS
BUSS
OATA6
BUS6
OATA7
OATA8
BUS7
OATA9
BUS8 .
OATA10
BUS9
S
12
6
13
7
1S
8
16
9
17
10
18
11
23
19
24
21
2S
22
IFC
IFC'
AEN
AEN'
NC
EOI'
SAO
SAO'
NAFO
NAFO'
0108
0108'
0107
0107'
0106
0106'
OIOS
OIOS'
0104
0104'
~
~
NOAC'
T/R101
T/R102
ATN'
0103'
NC
0102
0102'
OAV
OAV'
0101
0101'
Pin Name
T/R1
T/R2
EOI
ATN
1
2
3
4
G101
G101'
GI02
G102'
T/R1
T/R2
EOI
ATN
T/R1
NC
EOI
Aiiil
n=c
IFC'
AEN
AEN'
EOl2
EOI'
SAO
SAO'
NAFO
NAFO'
NOAC
NOAC'
ATNI
ATNO
ATN'
CIC
CLTH
IFCL
SYC
TfR1
T/R2
mr
Am'
0108
OIOS'
0107
0107'
0106
0106'
0105
OIOS'
0104
0104'
0103
0103'
ATNO
0102
0102'
OAV
OAV'
0101
0101'
TlFh
IFCL
EOI
ATN
'Note: These pins are the IEEE-488 bus non·lnvertlng driver/receivers. They Include all the bus terminations required by the Standard and may be
connected directly to the GPIB bus connector.
9-109
8293
~[Q)\Yl~OO©[§
000 [F©~ ~~'iJ'O©OO
MODEO
GENERAL DESCRIPTION
The 8293 is a bidirectional transceiver. It was designed
to interface the Intel 8291 GPIB Talker/Listener and the
Intel® 8292 GPIB Controller to the IEEE Standard
488-1978. Instrumentation Bus (also referred to as the
GPIBBus). The Intel GPIB Bus Transceiver meets or exceeds all of the electrical specifications defined in the
IEEE Standard 488-1978, Seytion 3.3-3.5, including the
required bus termination specifications.
OPTA
OPTB
THREE
STATE ONLY
GIO,
TfRIOl
THREE
STATE ONLY
G.IO,
GIO,·
GI02*
TlRIO,
The 8293 can be hardware programmed to one of four
modes of operation. These modes allow the 8293 to be
configured to support both a Talker/Listener/Controller
environment and Talker/Listener environment. In addition, the 8293 can be used as a general purpose threestate (push-pull) or open-collector bus transceiver with
nine receiver/drivers. Two modes are used to support a
Talker/Listener environment (s.ee Figure 1), and to support a Talker/Listener/Controller environment (see
Figure 2). Mo.de 1 is the general purpose mode.
iFc
INPUT ONLY
REN
INPUT ONLY
INPUT ONLY
ATN
OPEN COL
OUTPUT ONLY
SRO
THREE
STATE ONLY
WI
IFC'
REN'
ATN'
SRO'
EOI'
T/~2
GPIB
N"RFi5
NDAC
T/Rl
TO
PROCESSOR
BUS
---.I
TIC
14
8291
18
SIR
1 = THREE STATE
= +5V
0= OPEN COLLECTOR
1 = SEND TO GPIB
=OV
0= RECEIVE FROM GPIB
, = IEEE·488 BUS NON·INVERTING DRIVERIRECEIVER
-&
Figure 3. Talker/Listener Control Configuration
MODE 0 PIN DESCRIPTION
Symbol
GPIB
1/0
Pin No_
Figure 1. Talker/Listener Configuration
GPIB
I/O
10
Not Data Accepted; processor
GPIB bus handshake control
line; used to indicate the condition of acceptance of data
by device(s). It is TTL compatible.
I/O
18
Not Data Accepted; IEEE
GPIB bus handshake control
line. When an input, it is a TTL
compatible Schmitt~trigger.
When an output, ilisan opencollector driver with 48 mA
sinking capability.
I/O
9
Not Ready For Data; processor GPIB handshake control
line; used to indicate the condition of readiness of device(s) to accept data. This pin
is TTL compatible.
TO
PROCESSOR
BUS
NDAC*
TO
PROCESSOR
BUS
GPIB
Figure 2. Talker/Listener/Controller Configuration
Function
Transmit receive 1; direction
control for NDAC and NRFD. If
TfRl is high, then NDAC* and
NRFD* are receiving. Input is
TTL compatible.
T/Rl
8293
Symbol
1/0
Pin No.
NRFO"
1/0
17
Not Ready For Data; IEEE
GPIB bus handshake control
line. When an input, it is a TTL
compatible Schmitt·trigger.
When an output, it is an open·
collector driver with a 48 mA
current sinking capability.
2
Transmit receive 2; direction
control for EOL If T/R2 is high,
EOI" is sending. Input Is TIL
compatible.
End or Identify; processor
GPIB bus control line; is used
by a talker by indicate the end
of a multiple byte transfer.
This pin is TIL compatible.
T/R2
1/0
EOI"
1/0
3
15
8
SRO"
o
o
REN"
6
13
o
ATN"
16
4
19
Function
End or Identify; IEEE GPIB bus
control line; is used by a talker
to indicate the end of a multiple byte transfer. This pin is a
three-state (push-pull) driver
capable of sinking 48 mA and
a TIL compatible receiver
with hysteresiS.
Symbol
o
Pin No.
Function
5
Interface Clear; processor
GPIB bus control line; used by
a controller to place the interface system into a known
quiescent state. It is a TIL
compatible output.
IFC"
12
Interface Clear; IEEE GPIB
bus control line. This input is
a TIL compatible Schmitttrigger.
T/Ffl01
T/RI02
11
23
Transmit receive General 10;
direction control for the two
spare transceivers. Input is
TIL compatible.
G101"
G102"
Service Request; processor
GPIB bus control line; used by
a device to indicate the need
for service and to request an
interruption of the current sequence of events on the GPIB.
It is a TIL compatible input
1/0
1/0
24
1/0
1/0
21
22
25
General 10; this is the TIL
side of the two spare transceivers. These pins are TTL
compatible.
General 10; these are spare
three-state (push-pull) driversl
Schmitt-trigger receivers. The
drivers can sink 48 mAo
MODEl
OPTA
OPT"
DAV
Service Request; IEEE GPIB
bus control line; it is an oPen
collector driver capable of
sinking 48 mAo
1-------1
T/ih
Remote Enable; processor
GPIB bus control line; used by
a controller (in conjunction
with other messages) to
select between two alternate
sources of device programming data (remote ·or local
control). This output is TIL
compatible.
010,
/------H
010,
/------H
010,
/------H
I!i!l4 I - - - - - - H
rno,
Remote Enable; IEEE GPIB
bus control line. This input is
a TIL compatible Schmitttrigger.
/------H
iiiOs I - - - - - - H
Dill, I - - - - - - H
Attention; processor GPIB
bus control line; used by the
8291 to determine how data
on the 010 signal lines are to
be interpreted. This Is a TIL
compatible output.
Attention; IEEE GPIB bus control line; this input is a TIL
compatible Schmitt·trlgger.
1/0
~
1------+-1
Afiij
EOi
Figura 4. TalkerlListener Data Configuration
9-111
8293
MODE 1 PIN DESCRIPTION
Symbol
I/O
Pin No.
MOOE2
OPTA
Function
OPTB
Transmit receive 1; controls
the direction for DAV and the
DIO lines. If T/R1 is high, then
all these lines are sending in·
formation to the IEEE GPIB
lines. This input is TTL com·
patible.
T/R1
NDAi:
1--------/
1------/ NOAC'
fIm'lj
1-----+-1.
H---/NRFO'
T/ft1
~I------/.
SYC
3
End of Sequence and Atten·
tion; processor GPIB control
lines. These two control
signals are ANDed together to
determine whether all the
transceivers in the 8293 are
three·state (push·pull) or
open·collector. When both
4
I/O
DAV'
I/O
I/O
24
Data Valid; processor GPIB
bus handshake control line;
used to indicate the condition
(availability and validity) of in·
formation on the DIO signals.
It is TTL compatible.
21
Data Valid; IEEE GPIB bus
handshake control line. When
an input, it is a TTL compati·
ble Schmitt·trigger. When
DAV' is an output, it can sink
48 mAo
25,23,
10,9,
8,7,
6, 5
D101'
D108'
I/O
22,
18,
16,
13,
19,
17,
15,
12
Data Input/Output; processor
GPIB bus data lines; used to
carry message and data bytes
in a bit·parallel byte·serial
form controlled by the three
handshake signals. These
lines are TTL compatible.
Data Input/Output; IEEE GPIB
bus data lines. They are TTL
compatible Schmitt·triggers
when used for input and can
sink 48 mA when used for out·
put. See ATN and EOI descrip·
tion for output mode.
9-112
iIEliiH-+----H
H---/REN'
1_+------1
I_---/SRQ·
SRQ
~ ~t~=+=~====~~~dl-I ATN'
signals are low (true), then the
controller is performing a
parallel poll and the tran·
sceivers are all open·
collector. These inputs are
TTL compatible.
I_---/IFC·
1-1--+---......-'
EOl2
i-+--+----t-!
~---IEOI·
Jrnm 1_+-......' 1 ,
E1jj I_+--==-:J-H
T/ft2
1_+----1+-'
iFCI
I--~_
c~~~ I=~~~...L")
Figure 5. Talker/Listener/Controller Control
Configuration
MODE 2 PIN DESCRIPTION
Symbol
I/O
Pin No.
T/R1
Function
Transmit receive 1; direction
control for NDAC and NRFD.
If T/R1 is high, then NDAC and
NRFD are receiving. Input is
TTL compatible.
NDAC
I/O
10
Not Data Accepted; processor
GPIB bus handshake control
line; used to indicate the condition of acceptance of data
by device(s). This pin is TTL
compatible.
NDAC'
I/O
18
Not Data Accepted; IEEE
GPIB bus handshake control
line. It is a TTL compatible
Schmitt-trigger when used for
input and an open-collector
driver with a 48 mA current
sink capability when used for
output.
8293
Symbol
I/O Pin No.
NRFD
1/0
NRFD'
1/0
SYC
REN
1/0
9
17
Not Ready For Data; IEEE
GPIB bus handshake control
line. It is a TTL compatible
Schmitt·trigger when used for
input and an open'collector
driver with a 48 mA current
sink capability when used for
output.
22
System Controller; used to
monitor the system controller
switch and control the direc·
tion for IFC and REN. This pin
is a TTL compatible input.
6
Remote Enable; processor
GPIB control line; used by the
active controller (in conjunc·
tion with other messages) to
select between two alternate
sources of device program·
ming data (remote or local con·
trol). This pin is TTL compa·
tible.
1/0
13
Remote Enable; IEEE GPIB
bus control line. When used as
an input, this is a TTL compati·
ble Schmitt·trigger. When an
output, it is a three·state driver
with a 48 mA current sinking
capability.
IFC
I/O
5
Interface Clear; processor
GPIB bus control line; used by
the active controller to place
the interface system into a
known quiescent state. This
pin is TTL compatible.
I/O
12
SRO'
24
Controller in Charge; used to
control the direction of the
SRO and to indicate that the
8292 is in charge of the bus.
CiC is a TTL compatible input.
CLTH
21
Clear Latch; used to clear the
IFC Received latch after it has
been recognized by the 8292.
Normally low (except after
a hardware reset), it will be
pulsed low when IFC Received
Pin No.
Function
o
25
IFC Received Latched; the
8292 monitors the IFC line
when it is not the active con·
troller through this pin.
1/0
8
Service Request; processor
GPIB control line; indicates
the need for attention and reo
quests the active controller to
interrupt the current sequence
of events on the GPIB bus.
This pin is TTL compatible.
I/O
16
Service Request; IEEE GPIB
bus control line. When used
as an input, this pin is a TTL
compatible Schmitt·trigger.
When used as an output, it is
an open·collector driver with a
48 mA current sinking capa·
bility.
Transmit receive 2; controls
the direction for EOL This in·
put is TTL compatible.
T/R2
Interface Clear; IEEEGPIB bus
control line. This is a TTL com·
patible Schmitt·trigger when
used for input and a three·
state driver capable of sinking
48 mA current when used for
output.
CIC
I/O
is recognized by the 8292.
This input is TTL compatible.
Not Ready For Data; processor
GPIB bus handshake control
line; used to indicate the con·
dition of readiness of device(s)
to accept data. This pin is TTL
compatible.
REN'
IFC'
Symbol
Function
ATN'
9-113
2
23
Attention Out; processor
GPIB bus control line; used by
the 8292 for ATN control of
the IEEE bus during "take
control synchronously" opera·
tions. A low on this input
causes ATN to be asserted if
CIC indicates that this 8292 is
in charge. ATNO is a TTL com·
patible input.
o
11
Attention In; processor GPIB
bus control line; used by the
8292 to monitor the ATN line.
This output is TTL compatible.
o
4
Attention; processor GPIB
bus control live; used by the
8292 to monitor the ATN line.
This output is TTL compatible.
1/0
19
Attention; IEEE GPIB bus con·
trol line; used by a controller
to specify how data on the
010 signal lines are to be in·
terpreted and which devices
must respond to data. When
used as an output, this pin is a
three·state driver capable of
sinking 48 mA current. As an
input, it is a TTL compatible
Schmitt·trigger.
I/O
7
End or Identify 2; processor
GPIB bus control line; used in
conjunction with ATN by the
active controller (the 8292) to
execute a polling sequence.
This pin is TTL compatible.
8293
Symbol
I/O
Pin No.
I/O
3
I/O
EOI'
15
MODE 3 PIN DESCRIPTION
Function
End or Identify; processor
GPIB bus control line; used by
a talker to indicate the end of
a multiple byte transfer se·
quence. This pin is TTL com·
patible.
End or Identify; IEEE GPIB bus
control line; used by a talker
to indicate the end of a multi·
pie byte transfer sequence or,
by a controller in conjunction
with ATN, to execute a polling
sequence. Whel1 an output,
this pin can sink 48 mA cur·
rent. When an input, it is a TTL
compatible Schmitt·trigger.
Symbol
I/O
Pin No.
T/R1
EOI
ATN
3
4
End of Sequence and Atten·
tion; processor GPIB control
lines. These two control lines
are ANDed together to deter·
mine whether all the tran·
sceivers in the 8293 are push·
pull or open·collector. When
both signals are low (true),
then the controller is performing a paiallei poli and the
transceivers are all opencollector. These inputs are
TTL compatible.
23
Attention Out; processor
GPIB control line; used by the
8292 during "take control synchronously" operations. This
pin is TTL compatible.
2
Interface Clean Latched; used
to make DAV received after the
system controller asserts IFC.
This input is TTL compatible.
I/O
24
Data Valid; processor GPIB
handshake control line; used
to indicate the condition
(availability and validity) of information on the 010 signals.
This pin is TTL compatible.
I/O
21
Data Valid; IEEE GPIB handshake control line. When an
input, this pin is a TTL compatible Schmitt-trigger. When
DAV' is an output, it can sink
48 mA.
I/O
25,23,
10,9,
8,7,
Data Input/Output; processor
GPIB bus data lines; used to
carry message and data bytes
in a bit-parallel byte-serial
form controlled by the three
handshake signals. These
lines are TTL compatible.
MOoE3
OPTA
OPTB
oAV
I--Y>-4-+-I
T/l!1 1--i>O-+-{>O~...J
DID, 1 - - - - - + - 1
010,1-----+-1
010, 1 - - - - - + - 1
DAV'
010, 1 - - - - - + - 1
010,1-----+1
010.1-----+-1
6, 5
010,1-----+1
ATN
0101'0108'
Figure 6. Talker/Listener/Controller Data
Configuration
9-114
Function
Transmit receive 1; controls
the direction for DAV and the
010 lines. If T/R1 is high, then
all these lines are sending
information to the IEEE GPIB
lines. This input is TTL com·
patible.
I/O
22,19,
18,17,
16,15,
13,12
Data Input/Output; IEEE GPIB
bus data lines. They are TTL
compatible Schmitt-triggers
when used for input and can
sink 48 mA when used for output.
8293
25
23
10
9
8
TO
MICROPROCESSOR
INTERFACE
8291
..E..
DO
Di01
..!!
01
0102
~ 02
0103
~
D!
0104
04
0105
-.!!.
...!!.
-.!!.
05
0106
06
0107
...!!.
07
0'108
2- CS
---.! Rii
....!.!!. WR
....!.!.
.2.
--..!.
2.....!..
INT
OAV
Tlih
ATN
EOI
CLOCK
TiR2
r1L
6
~
30
5
31
24
32
1
33
~
34
--.!.
0101'
Di02
DiOO
0102'
0104
0104'
0105
0105'
0103'
TO
IEEE·488
SUS
OAV'
E-
TIRl
OPTA
~ Vee
ATN
OPTS
~ GNO
!iIl5i
EOI
35
MODEl
36
1
26
39
3
6293
ATN'
..!!..
...!!!...
NOAC
NOAC'
r!!-
NRFO
NRFO'
EOI
EOI'
~ ATN
2
1
SRQ
27
10
lIEN
iFC
25
9
24
8
SlIQ
SRQ'
6
lIEN
REN'
IFC
IFC'
OACK
-17
..!!...
0108'
0106'
0107'
2
NRFO
..!!...
DAY
Dii56
6Im
38
NOAC
~
r!!-
~
~
~
37
RESET
OREQ
GPIS TRIGGER OUTPU T 2 TRIG
7
8293
0101
5
TIRl
TIR2
OPTA
OPTS
MOOEO
, = GPIS SUS TRANSCEIVER
Figure 7. 8291 and 8293 System Configuration
9-115
r!!...
r1L
TO
IEEE·488
SUS
r!!r1L
r!!- GNO
~
GNO
8293
TO MICROPROCESSOR
rE~
r2!
~
16
17
18
19
21
22
J
23
9
10
4
&
MICROPROCESSOR
7
8
3
11
DO
0101
01
-
0102
02
0103
03
0104
04
05
0105
06
0106
07
RSO
0107
8291
0108
RS1
T/R1
RS2
Rii
OAV
WR
EOI
RESET
ATN
OREO
SRO
OACK
IFC
~
NOAC
CLOCK
NRFO
INT
T/R2
GPIB
TRIGGER
OUTPUT
5
----.!i.
16
17
18
19
9
8
10
OSCILLATOR
OUTPUT
23
30
10
31
9
0101
0101·
0102
0102·
0103
0103·
0104
0104·
0105
0105·
0106
0106·
32
8
33
7
34
6
35
5
iiiOa
1
1
TiFh
36
24
39
3
26
4
0107
8293
OAV
~
~
~
r!Z-
~
~
0107· ~
0108·
~
DAV·
~
TO
IEEE·488
BUS
EOI
ATN
21
24
36
37
,---!!..
2
,2
ATNO
OPTA
IFCL
OPTB
rE-vee
~V ee
MODE 3
cE..
I
25
29
REN ~
TRIG
DO
OAV
~ 01
~ 02
MICROPROCESSOR
TO
28
"....
4
6
32
33
35
36
11
Vee
r
~3
15'25PF±
r-""!-4
10
03
9
04
2
05
SRO
06
07
AO
Rii
WR
RESET
~
TCI
REN
-
8292
IFC
ATNO
21
8
38
6
23
5
29
23
39
3
34
7
--
22
11
-
1
25
31
24
COUNT
EOl2
ATNI
TiR1
ATN
~
NOAC
NOAC
Nl'Rii
NRFO
r!!.-
SRO
SRO·
t-'!-
REN
REN*
T/R2
8293
IFC
~
IFC· ~
ATN·
ATNO
EOI·
EOI
TO
IEEE·488
BUS
~
~
EOl2
,ATNI
SPI
OBFI
IBFI
SYNC
------2..
~
2!..
IFCL
X,
X2
CIC
CLTH
SYC
27
21
24
22
IFCL
CIC
OPTA E....G NO
CLTH
SYC
OPTB
~V cc
MOOE2
l ) eON
SYSTEM
CONTROLLER
SWITCH
0FF
.i
Figure 8. 8291,8292, and 8293 System Configuration
9-116
• = GPIB BUS TRANSCEIVER
8293
Absolute Maximum Ratings*
Ambient Temperature Under Bias ......... O·C to 70·C
Storage Temperature ............. - 65·C to + 150·C
Voltage 011 any Pin with
Respect to Ground ................. - 1.0V to + 7V
Power Dissipation .......................... 1 Watt
'COMMENT: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those Indicated In the operational sections of this
specification Is not Implied. Exposure to absolute maximum rating can·
ditions 10', extended periods may affect device reliability.
D.C. and Operating Characteristics
TA=O·C to 70·C; V cc =5.0V ±10%; GND=OV
SYMBOL
LIMITS
PARAMETER
MIN.
VILl
Input Low Voltage (GPIB Bus Pins)
VIL2
Input Low Voltage (Option Pins)
TYP.
-0.1
V IL3
Input Low Voltage (All Others)
V IH1
Input High Voltage (GpIB Bus Pins)
2.0
V IH2
Input High Voltage (Option Pins)
4.5
VIH3
Input High Voltage (All Others)
2.0
VOLl
UNIT
TEST CONDITIONS
MAX.
0.8
V
0.1
V
0.8
V
V
5.5
V
Output Low Voltage (GPIB Bus Pins)
0.5
V
IOL=48 mA
VOL2
Output Low Voltage (All Others)
0.5
V
IOL= 16 mA
VOH1
Output High Voltage (GPIB Bus Pins)
2.4
V
IOH= -5.2 mA
VOH2
Output High Voltage (All Others)
2.4
V
IOH= -400~
V IH4
Receiver Input Hysteresis
400
600
VIT
.
High to Low
Receiver Input Threshold Low to High
0.8
1.0
1.6
-3.2
V
mV
2.0
V
ILI1
Low Input Load Current (GPIB Bus Pins)
0.0
mA
VIL= 0.8V
IU2
Low Input Load Current (All Others)
10
JJA
V IL = 0.8V
Ipo
Bus Power Down Leakage Current
10
JJA
Vcc=OV
Icc
Power Supply Current
100
mA
MAX.
UNIT
5
10
pF
VIN=VCC
10
20
pF
VOUT=VCC
Capacitance
SYMBOL
PARAMETER
CIN
Input CapaCitance
COUT
Output Capacitance
MIN.
9-117
TYP.
TEST CONDITIONS
8293
A.C. Characteristics
TA = O·C to 70·C; Vee= 5.0V ± 10%; GND = OV
TYP.·
PARAMETER
SYMBOL
MAX.
UNITS
ns
tpLH1
Driver Propagation Delay (Low to High)
20
35
t pH L1
Driver Propagation Delay (High to Low)
17
30
ns
t pLH2
Receiver Propagation Delay (Low to High)
22
35
ns
t pHL2
Receiver Propagation Delay (High to Low)
18
30
ns
t pHZ1
Driver Enable Delay (High to 3·State)
20
35
ns
tpZH1
Driver Enable Delay (3-State to High)
15
30
ns
t pLZ1
Driver Enable Delay (Low to 3-State)
20
35
ns
tpzL1
Driver Enable Delay (3-State to Low)
15
30
ns
t pHZ2 .
Receiver Enable Delay (High to 3-State)
25
40
ns
tPZH2
Receiver Enable Delay (3-State to High)
20
35
ns
t pLZ2
Receiver Enable Delay (Low to 3-State)
25
40
ns
tpZL2
Receiver Enable Delay (3-State to Low)
20
35
ns
6.0
5.0
I
4.0
2.0
g
I
,.,.
-2.0
.-'"
"
~
I
4.0 f - - _~cc= S.OV
TA=2S'C
w
~ 3.0
~
-4.0
g
-6.0
!;
NON·SHADED AREA
CONFORMS TO
PARAGRAPH 3.5.3 OF
IEEE STANDARD
488 ·1978
Vcc=5.0V
-8.0
-10
-12
-14
-4.0
-2.0
-0
2.0
4.0
2.0
i!:::>
o
~ 1.0
o
6.0
VBU •• BUS VOLTAGE (VOLTSi
Figure 9. Typical Bus Load Line
o
0.5
1.0
1.5
V,. INPUT VOLTAGE (VOLTSi
2.0
Figure 10. Typical Receiver Hysteresis Characteristics
9·118
8293
OUTPUT LOADING TEST CIRCUITS
TO SCOPE
(OUTPUT)
TO SCOPE
(OUTPUT)
+2.3V
+5.0V
24011
38.311
DATA
BUS
1"1
~z INlll
~~
OREQUIV.
;~
-FCL INCLUDES JIG AND PROBE CAPACITANCE
Figure 11. Data Input to BUI Output (Driver)
TO SCOPE
(OUTPUT)
CL INCLUDEI JIG AND PROBE CAPACITANCE
Figure 12. BUI Input to Data Output (Receiver)
TO SCOPE
(OUTPUT)
1.W
5.oV
13.52
BUS
./
(I.LZI. I.ZL1)
DATA
1
o--.......--~:r
./
o--t---- 8294 Data Encryption Unit (DEU) is a microprocessor peripheral device designed to encrypt and decrypt
64·bit blocks of data using the algorithm specified in the Federal Information Processing Data Encryption Standard.
The DEU operates on 64·bit text words using a 56·bit user·specifled key to produce 64·blt cipher words. The operation
is reversible: if the cipher word Is operated upon, the original text word is produced. The algorithm itself is perma·
nently contained in the 8294; however, the 56·blt key is user·defined and may be changed at any time.
The 56·bit key and 64·blt message data are transferred to and from the 8294 in 8·bit bytes by way of the system data
bus. A DMA interface and three interrupt outputs are available to minimize software overhead associated with data
transfer. Also, by using the DMA interface two or more DEUs may be operated In parallel to achieve effective system
conversion rates which are virtually any multiple of 80 bytes/second. The 8294 also has a 7·bit TTL compatible output
port for user·specified functions.
Because the 8294 implements the NBS encryption algorithm it can be used in a variety of Electronic Funds Transfer
applications as well as other electronic banking and data handling applications where data must be encrypted.
PIN
CONFIGURATION
Vee
Ne
BLOCK DIAGRAM
DATA
BUS
!lACK
01
02
03
D4
OS
06
07
GND
ORO
SRO
DAV
Ne
P6
PS
P'
P3
P2
PI
PO
VDD
Ne
CCMP
Ne
Ne
Ac
SRQ
DAV
teMP
po'p,
RESET
SYNC
X,
x,
NC
+5VPOWER-OND--
9-121
INTERNAL
BUS
oo230B
8295
DOT MATRIX PRINTER CONTROLLER
• Programmable Print Intensity
• Interfaces Dot Matrix Printers to
MCS·4S™, MCS.SO/SS™, MCS·S6™
Systems
• Single or Double Width Printing
• 40 Character Buffer On Chip
• Serial or Paranel Communication with
Host
• Programmable Multiple Line Feeds
• DMA Transfer Capability
• 3 Tabulations
• Programmable Character Density (10 or
12 Chararcters/lnch)
• 2 General Purpose Outputs
The Intel'" 8295 Dot Matrix Printer Controller provides an interface for microprocessors to the LRC 7040 Series dot
matrix impact printers. It may also be used as an interface to other similar printers.
The chip may be used in a serial or parallel communication mode with the host processor. In parallel mode, data
transfers are based on polling, interrupts, or DMA. Furthermore, it provides internal buffering of up to 40 characters
and contains a 7 x 7 matrix character generator accommodating 64 ASCII characters.
PIN
CONFIGURATION
BLOCK DIAGRAM
INTERNAL
'OO
9·122
002318
inter
8041 AJ8641 AJ8741 A
UNIVERSAL PERIPHERAL INTERFACE
8·BIT MICROCOMPUTER
• 8·Blt CPU plus ROM, RAM, 1/0, Timer
and Clock in a Single Package
• One 8·Bit Status and Two Data Regis·
ters for Asynchronous Slave·to·Master
Interface
• DMA, Interrupt, or Polled Operation
Supported
• 1024)( 8 ROMIEPROM, 64)( 8 RAM,
8·Blt TimerlCounter, 18 Programmable
1/0 Pins
• Fully Compatible with MCS·48™,
MCS.80™, MCS·85™, and MCS·86™
Microprocessor Families
• Interchangeable ROM and EPROM
Versions
• 3.6 MHz 8741A·8 Available
• Expandable 1/0
• RAM Power· Down Capability
• Over 90 Instructions: 70% Single Byte
• Single 5V Supply
The Intell!) 8041A18741A is a general purpose, programmable interface device designed for use with a variety of 8-bit
microprocessor systems. It contains a low cost microcomputer with program memory, data memory, 8-bit CPU, I/O
ports, timer/counter, and clock in a single 40-pin package. Interface registers are included to enable the UPI device to
function as a peripheral controller in MCS-48™, MCS-80™, MCS-85™, MCS-86™, and other 8-bit systems.
The UPI-41ATM has 1K words of program memory and 64 words of data memory on-chip. To allow full user flexibility the
program memory is available as ROM in the 8041A version or as UV-erasable EPROM in the 8741A version. The 8741A
and the 8041 A are fully pin compatible for easy transition from prototype to production level designs. The 8641A is a
one-time programmable (at the factory) 8741A which can be ordered as the first 25 pieces of a new.8041A order. The
substitution of 8641A's for 8041A's allows for very fast turnaround for initial code verification and evaluation results.
The device has two 8-bit, TTL compatible I/O ports and two test inputs. Individual port lines can function as either inputs or outputs under software control. I/O can be expanded with the 8243 device which is directly .compatlble and has
16 I/O lines. An 8-bit programmable timer/counter is included in the UPI device for generating timing sequences or
counting external inputs. Additional UPI features include: single 5V supply, low power standby mode (in the 8041A),
single-step mode for debug (in the 8741A), and dual working register banks.
Because ifs a complete microcomputer, the UPI provides more flexibility for the designer than conventional LSI interface devices. It is· designed to be an efficient controller as well as an arithmetic processor. Applications include keyboard scanning, printer control, display multiplexing and similar functions which involve interfacing peripheral
devices to microprocessor systems.
PIN CONFIGURATION
BLOCK DIAGRAM
INTERNAL
BUS
'0)
::·¢:E::::;~~=~===~
1.........
MAITIR
,.,
SVSTEM
0lI-_
01--
..-
k;====:::J
PERIPHERAL
INTERFACE
SYNC
1Ii--
'"00
omT--
CR~~T~~{XTAL1
CLOCK
_ _1
XTAL2--
,,1..
I
9-123
00188A
8041A/8641 Al8741A
UPI·41A™ FEATURES AND
ENHANCEMENTS
1. Two Data Bus Buffers, one for input and one for out·
put. This allows a much cleaner Master/Slave pro·
tocol.
If "EN FLAGS" has been executed, P25 becomes the
IBF (Input Buffer Full) pin. A "1" written to P25
enables the IBF pin (the pin outputs the inverse of the
IBF Status Bit). A "0" written to P25 disables the iBF
pin (the pin remains low). iThis pin can be used to
indicate that the UPI·41A is ready for data.
INTERNAL
DATA BUS
INPUT
DATA
BUS
BUFFER
~
DO-D7
(8)
'---------'
OBF (INTERRUPT REQUESn
OUTPUT
DATA
BUS
BUFFER
fiiF (INTERRUPT REQUESn
(8)
DATA BUS BUFFER INTERRUPT CAPABILITY
2. 8 Bits of Status
FO
I
IBF
OBF
EN FLAGS
I
ST 4-ST 7 are user definable status bits. These bits are
defined by the "MOV STS, A" Single byte, Single
cycle instruction. Bits 4-7 of the accumulator are
moved to bits 4-7 of the status register. Bits 0-3 of
the status register are not affected.
MOV STS. A
Op Cod.: OF5H
5. P26 and P27 are port pins or DMA handshake pins for
use with a DMA controller. These pins default to port
pins on Reset.
Op Code: 90H
If the "EN DMA" instruction has been executed, P26
becomes the DRQ (DMA ReQuest) pin. A "1" written
to P26 causes a DMA request (ORO is activated). DRQ
is deactivated by DACK'RD, DACK·WR, or execution
of the "EN OM A" instruction.
3. RD and WR are edge triggered. IBF, OBF, F1 and INT
change internally after the trailing edge of RD or WR.
If "EN DMA" has been executed, P27 becomes the
DACK (DMA ACKnowledge) pin. This pin acts as a
chip select input for the Data Bus Buffer registers
during DMA transfers.
FLAGS AFFECTED
RO orW'R
4. P24 and P25 are port pins or Buffer Flag pins which
can be used to interrupt a master processor. These
pins default to port pins on Reset.
If the "EN FLAGS" instruction has been executed,
P24 becomes the OBF (Output Buffer Full) pin. A "1"
written to P24 enables the OBF pin (the pin outputs
the OBF Status Bit). A "0" written to P24 disables the
OBF pin (the pin remains low). This pin can be used
to indicate that valid data is available from the UPI·
41A (in Output Data Bus Buffer).
9-124
8041A!
8741A
DRQ~
OROn
DACK~
DACK
8257
OMA HANDSHAKE CAPABILITY
EN DMA
Op Code: OESH
D,
00188A
8041 AJ8641AJ8741 A
PIN DESCRIPTION
UPITM INSTRUCTION SET
Description
Mnemonic
Bytes Cycles
ACCUMULATOR
Signal
Description
0 0- 0 7
(BUS)
Three·state, bidirectional DATA BUS BUFFER lines
used to interface the UPI·41A to an 8·bit master
system data bus.
P 10 -P 17
8·bit, PORT 1 quasi·bidirectionall/O lines.
P20-P27
8·bit, PORT 2 quasi·bidirectionall/O lines. The lower
4 bits (P 20 -P23) interface directly to the 8243 I/O ex·
pander device and contain address and data infor·
mation during PORT 4-7 access. The upper 4 bits
(P24-P27 ) can be programmed to provide Interrupt
Request and DMA Handshake capability. Software
control can configure P24 as OBF (Output Buffer
Full), P25 as IBF (Input Buffer Full~as DRQ
(DMA Request), and P 27 as DACK (DMA
ACKnowledge).
WR
I/O write input which enables the master CPU to
write data and command words to the UPI·41A IN·
PUT DATA BUS BUFFER.
RD
110 read input which enables the master CPU to
read data and status words from the OUTPUT DATA
BUS BUFFER or status register.
CS
Chip select input used to select one UPI·41A out of
several connected to a common data bus.
Ao
Address input used by the master processor to in·
dicate whether byte transfer is data or command.
TEST 0,
TEST 1
Input pins which can be directly tested using condi·
tional branch instructions.
T1 also functions as the event timer input (under
software control). To is used during PROM program·
ming and verification in the 8741A.
XTAL 1,
XTAL2
Inputs for a crystal, LC or an external timing signal
to determine the internal oscillator frequency.
SYNC
Output signal which occurs once per UPI·41A in·
struction cycle. SYNC can be used as a strobe for
external circuitry; it is also used to synchronize
single step operation.
EA
PROG
External access input which allows emulation,
testing and PROM/ROM verification.
Multifunction pin used as the program pulse input
during PROM programming.
During I/O expander access the PROG pin acts as
an address/data strobe to the 8243.
RESET
Input used to reset status flip·flops and to set the
program counter to zero.
RESET is also used during PROM programming and
verification.
SS
Single step input used in the 8741A in conjunction
with the SYNC output to step the program through
each instruction.
Vee
+ 5V main power supply pin.
Voo
+ 5V during normal operation. + 25V during pro·
gramming operation. Low power standby pin in
ROM version.
Vss
Circuit ground potential.
ADD A.Rr
ADD A.@Rr
ADD A.#data
ADDC A.Rr
ADDC A.@Rr
ADDC Mdata
ANL A.Rr
ANL A.@Rr
ANL A.#data
ORl A.Rr
ORL A.@Rr
ORL A.#data
XRl A.Rr
XRL A.@Rr
XRL A.#data
INC A
DEC A
CLR A
CPL A
DA A
SWAP A
RL A
RlC A
RR A
RRC A
Add register to A
Add data memory to A
Add immediate to A
Add register to A with carry
Add data memory to A with carry
Add immed. to A with carry
AND register to A
AND data memory to A
AND immediate to A
OR register to A
OR data memory to A
OR immediate to A
Exclusive OR register to A
Exclusive OR data memory to A
Exclusive OR immediate to A
Increment A
Decrement A
Clear A
Complement A
Decimal Adjust A
Swap nibbles of A
Rotate A left
Rotate A left through carry
Rotate A right
Rotate A right through carry
2
1
1
2
1
1
1
1
2
2
1
1
1
1
2
2
1
1
1
1
2
1
2
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
INPUT /OUTPUT
IN A.Pp
OUTL Pp.A
ANl Pp.#data
ORl Pp.#data
IN A.DBB
OUT DBB.A
MOV STS,A
MOVD A.Pp
MOVD Pp.A
ANlD Pp.A
ORlD Pp.A
DATA
2
2
Input port to A
Output A to port
AND Immediate to port
OR immediate to port
Input DBB to A. clear IBF
Output A to DBB. set OBF
A4-A7 to Bits 4-7 of Status
Input Expander port to A
Output A to Expander port
AND A to Expander port
OR A to Expander port
2
2
1
1
1
2
2
2
2
MOVES
MOV A.Rr
MOV A.@Rr
MOV A.#data
MOV Rr.A
MOV @Rr.A
MOV Rr.#data
MOV @Rr.#data
MOV A.PSW
MOV PSW.A
XCH A.Rr
XCH A.@Rr
XCHD A.@Rr
MOVP A.@A
MOVP3. A.@A
Move register to A
Move data memory to A
Move Immediate to A
Move A to register
Move A to data memory
Move immediate to register
Move Immediate to data memory
Move PSW to A
Move A to PSW
Exchange A and register
Exchange A and data memory
Exchange digit of A and register
Move to A from current page
Move to A from page 3
1
1
2
1
1
2
2
1
1
1
1
1
1
1
1
1
2
1
1
2
2
1
1
1
1
1
2
2
TIMER/COUNTER
MOV A.T
MOV T.A
STRT T
STRT CNT
STOP TCNT
EN TCNTI
DIS TCNTI
9-125
Read Timer/Counter
Load Timer /Counter
Start Timer
Start Counter
Stop Timer /Counter
Enable Timer /Counter Interrupt
Disable Timer /Counter Interrupt
00188A
8041 Al8641 Al8741 A
Mnemonic
BYt••
Deecrlpllon
CONTROL
EN DMA
EN I
DIS I
EN FLAGS
SEL RBO
SEL RBI
NOP
Enable DMA Handshake Lines
Enable IBF Interrupt
Disable IBF Interrupt
Enable Master Interrupts
Select register bank 0
Select register bank,1
No Operation
REGISTERS
INC Rr
INC@Rr
DEC Rr
Increment register
Increment data memory
Decrement register
Cycl..
SUBROUTINE
2
2
2
Jump to subroutine
Return
Return and restore status
CALL addr
RET
RETR
FLAGS
Clear Carry
Complement Carry
Clear Flag 0
CLRC
CPLC
CLR FO
Mnemonic
D••crlpllon
CPL FO
CLR Fl
CPL Fl
Complement Flag 0
Clear Fl Flag
Complement Fl Flag
BRANCH
JMP addr
JMPP@A
OJ NZ Rr, addr
JC addr
JNC addr
JZ addr
JNZ addr
JTO addr
JNTO addr
JT1 addr
JNT1 addr
JFO addr
JFl addr
JTF addr
JNIBF addr
JOBF addr
JBb addr
Jump unconditional
Jump Indirect
Decrement register and jump
Jump on Carry = 1
Jump on Carry = 0
Jump on A Zero
Jump on A not Zero
Jump on TO= 1
Jump on TO=O
Jump on Tl = 1
Jump on Tl =0
Jump on FO Flag = 1
Jump on Fl Flag = 1
Jump on Timer Flag = 1, Clear Flag
Jump on IBF Flag = 0
Jump on OBF Flag = 1
Jump on Accumulator Bit
Byte.
CyCle.
2
1
2
2
2
2
,2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
APPLICATIONS
DATAK===J[==~~~
aoaSA
TO
PERIPHERAL
DEVICES
ADDR
8048
CONTROL~==::11S,.J
Figure 1, 808SA-8041A Interface
iiii
WR
WR
~
AO
I+-To
DBB
-Tl
8041A1
cs 8741A
PORT
CONTROL
2
BUS
DATA BUS
8
TO
PERIPHERAL
DEVICES
Figure 2. 8048,..8041A Interface
KEYBOARD
MATRiX
8243
EXPANDER
~
iiii
z
:I
..~
It
>=
a:
0.
II.
Z
0-
iii:
0-
PORT,2
z
0
0
0
e
.~
0.
Cl
W
W
II.
'"Z
::;
PORT 2
8041 Al8741 A
8041A18741A
DATA BUS
CONTROL BUS
CONTROL BUS
Figure 3, 8041A-8243 Keyboad Scanner
Figure 4. 8041A Matrix Printer Interface
9-126
00l88A
8041 AJ8641 AJ8741 A
'COMMENT: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This Is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated In the operational sections of this
specification is not implied. Exposure to absolute maximum rating con·
ditlons for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias ......... O·C to 70·C
Storage Temperature ............. - 65·C to + 150·C
Voltage on Any Pin With Respect
to Ground .......................... 0.5V to + 7V
Power Dissipation ......................... 1.5 Watt
D.C. AND OPERATING CHARACTERISTICS
T A = O·C to 70·C, Vss=OV, 8041 A: Vee= Voo= +5V± 10%, 8741A: Vee = Voo= +5V± 5%
Parameter
Min.
Max.
Unit
V IL
Symbol
Input Low Voltage (Except XTAL 1, XTAL2, RESET)
-0.5
0.8
V
V IU
V IH
Input Low Voltage (XTAL1, XTAL2, RESET)
V
-0.5
0.6
Input High Voltage (Except XTAL 1, XTAL2, RESET)
2.2
Vee
3.8
Test Conditions
V IH1
Input High Voltage (XTAL1, XTAL2, RESET)
VOL
Output Low Voltage (0 0-0 7)
Vee
0.45
V
IOL=2.0 mA
Vou
V OL2
Output Low Voltage (P1QP 17 , P20 P27 , Sync)
0.45
V
10L = 1.6 mA
Output Low Voltage (Prog)
0.45
V
IOL = 1.0 mA
V OH
V
10H= - 4OO I'A
V OH1
Output High Voltage (0 0-0 7)
Output High Voltage (All Other Outputs)
IlL
Input Leakage Current (To, T 1, RD, WR, CS, A o, EA)
±10
I'A
Vss :S VIN :S Vee
loz
Output Leakage Current (0 0-0 7, High Z State)
± 10
Low Input Load Current (P1QP 17 , P20 P27 )
0.5
I'A
mA
V ss +0.45 :S VIN:s Vee
lu
IU1
Low Input Load Current (RESET, SS)
0.2
mA
100
Voo Supply Current
15
mA
VIL =0.8V
Typical = 5 mA
lee+ 100
Total Supply Current
125
mA
Typical = 60 mA
2.4
2.4
V
V
10H= -50 I'A
V IL = 0.8V
A.C. CHARACTERISTICS
TA =
o·c to 70·C, Vss=OV, 8041A: Vee= Voo=
+ 5V ± 10%, 8741A: Vee= Voo= + 5V ± 5%
DBB READ
Parameter
Symbol
Min.
Max.
Unit
0
ns
0
n5
Test Conditions
tAR
CS, Ao Setup to RDi
tRA
CS, Ao Hold After m51
tRR
RD Pulse Width
tAD
CS, Ao to Data Out Delay
225
ns
C L =150pF
t RO
RDi to Data Out Delay
225
ns
CL =
tOF
ROI
100
ns
tey
Cycle Time (Except 8741A·8)
2.5
15
1'5
6.0 MHz XTAL
tey
Cycle Time (8741A·8)
4.17
15
I's
3.6 MHz XTAL
Min.
Max.
Unit
ns
250
to Data Float Delay
150 pF
DBB WRITE
Parameter
Symbol
tAW
0
CS, Ao Setup to WRi
tWA
CS, Ao Hold After WAt
0
ns
tww
iiVA Pulse Width
250
ns
tow
Data Setup to WRt
150
ns
two
Data Hold After'i}J'R t
0
ns
9-127
Test Conditions
ns
00188A
8041A18641 Al8741 A
INPUT AND OUTPUT WAVEFORMS FOR A.C. TESTS
2.4
----""'X~::>TEST POINTS,:::::~·.:XL
O.4S----...J
-
____
WAVEFORMS
1. READ OPERATION-DATA BUS BUFFER REGISTER.
BOA Ao
'1----------------"'" '\;,___________
(SYSTEM'S
ADDREsseuS}
_t"~1
-+----il--
---- 1RR - - - -
~IAA-'
(READ CONTROL)
2. WRITE OPERATION-DATA BUS BUFFER REGISTER.
r
-v
e!OR AO - - - ' ) -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~
1.._ _ _ _ _ _ _ _ _ _ _
(SYSTEM'S
ADDRESS BUS)
:. "·i r-"·-.~Hc,..--tWA-____
'\
_
------------- t ow -
DATA SUS
DATA
UNPUTl _ _ _ _M_A_y..:"CH..:"A..:"NG..:..'_ _
~
-..Jj'
-
(WRITE CONTROLI
- - - two
--DATAVAlIO-_V
~'-
DATA
_ _ _ _M_A_y_CH_AN_G_E_ _ __
TYPICAL 8041/8741A CURRENT
80 rnA
60 rnA
40mA
20 mA
TEMP ,·C)
9-128
00188A
8041 AJ8641AJ8741 A
A.C. CHARACTERISTICS-PORT 2
TA=O·C to 70·C, 8041A: vcc= +5V : 10%, 8741A: Vcc= +5V :5%
Symbol
P.arameter
Min.
tcp
Port Control Setup Before Failing
Edge of PROG
110
tpc
Port Control Hold After Falling
Edge of PROG
100
tPR
PROG to Time P2 Input Must Be Valid
tpF
top
Output Data Setup Time
tpo
Output Data Hold Time
tpp
PROG Pulse Width
Input Data Hold Time
Max.
Unit
Telt Condition.
ns
ns
0
810
ns
150
ns
250
ns
65
ns
1200
ns
PORT 2 TIMING
SYNC
EXPANDER
PORT
PORT 20-3 DATA
EXPANDER
PORT
PORT
INPUT
20-3 DATA
PROG
A.C. CHARACTERISTICS-DMA
Symbol
Parameter
Min.
Max.
Unit
tACC
DACK to WR or"RD
0
ns
tCAC
~orWAto~
0
ns
tAco
DACK to Data Valid
225
ns
tCRO
RD or WR to ORO Cleared
200
ns
Test Conditions
C L = 150 pF
WAVEFORMS-DMA
IIIi
-
'ACC . : - - i C A C l
DATA BUS
)I(
Ii
tAce
-
-ICAe
-
-
,..---,.
-
VALID
~I-
ORa
-
.1,...----,.
VALID
_.CRJ-
9-129
Da,88A
8041 AJ8641AJ8741 A
DRIVING FROM EXTERNAL SOURCE
CRYSTAL OSCILLATOR MODE
+5V
r-----
< 16 pF
(INCLUDES XTAL,
SOC~ET, STRAY)
XTALI
I
I
I
~
4702
,..
Jo--+------=-l XTALI
I
I
I ____ _
L
+5V
3
16-26 pF
(INCLUDES SOCKET,
STRAY)
XTAL2
470Q
I
':"
'---~---=-j
XTAL2
CRYSTAL SERIES RESISTANCE SHOULD BE <75Q AT 6 MHz; <180Q AT 3.6 MHz.
BOTH XTALI AND XTAL2 SHOULD BE DRIVEN.
RESISTORS TO Vee ARE NEEDED TO ENSURE V,H = 3.8V
IF TTL CIRCUITRY IS USED.
LC OSCILLATOR MODE
J,.
..Q.
45.H
120.H
20 pF
20 pF
NOMINAL I
5.2 MHz
3.2 MHz
.....---.----"-1 XTAL 1
CPP" 5-10 pF PIN·TO·PIN
CAPACITANCE
' - -......-~XTAL2
EACH C SHOULD BE APPROXIMATELY 20 pF.INCLUDING STRAY CAPACITANCE.
PROGRAMMING, VERIFYING, AND
ERASING THE 8741A EPROM
Programming Verification
In brief, the programming process consists of: activating
the program mode, applying an address, latching the
address, applying data, and applying a programming pulse.
Each word is programmed completely before moving on to
the next and is followed by a verification step. The following is a list of the pins used for programming and a description of their functions:
Pin
Function
XTAL 1
Clock Input (1 to 6MHz)
Reset
Initialization and Address Latching
Test 0
Selection of Program or Verify Mode
EA
Activation of Program/Verify Modes
BUS
Addre~s
and Data Input
Data Output During Verify
WARNING:
An attempt to program a missocketed 8741 A will result in severe
damage to the part. An indication of a properly socketed part is the
appearance of the SYNC clock output. The lack of this clock may
be used to disable the programmer.
The Program/Verify seqUef1ce fs:
1.
Aa = av, CS = SV, EA = SV, RESET = av, TESTa = SV,
Voo = 5V, clock applied or internal oscillator operating,
BUS and PROG floating.
2.
Insert 8741A in programming socket
3.
TEST a = Ov (select program mode)
4.
EA = 23V (activate program mode)
S.
Address applied to BUS and P2Q..1
6.
RESET
7.
Data applied to BUS
= Sv
(latch address)
=2Sv (programm ing power)
8.
V DO
9.
PROG
10_
VOO = 5v
= Ov followed by
= Sv
one sOms pulse to 23V
11.
TEST 0
12.
Read and verify data on BUS
(verify mode)
P20-1
Address Input
13.
TEST 0 = Ov
VOO
PROG
Programming Power Supply
14.
RESET = Ov and repeat from step S
Program Pulse Input
16.
Programmer should be at conditions of step 1 when
8741A is removed from socket.
9·130
00188A
8041 AJ8641 AJ8741 A
8741A Erasure Characteristics
The erasure characteristics of the 8741A are such that
erasure begins to occur when exposed to light with
wavelengths shorter than approximately 4000 Ang·
stroms (A). It should be noted that sunlight and certain
types of fluorescent lamps have wavelengths In the
3000-4000A range. Data show that constant exposure to
room level fluorescent lighting could erase the typical
8741A in approximately 3 years while it would take ap·
proximately one week to cause erasure when exposed
to direct sunlight. If the 8741A is to be exposed to these
types of lighting conditions for extended periods of
time, opaque labels are available from Intel which
should be placed over the 8741A window to prevent
unintentional erasure.
The recommended erasure procedure for the 8741A is
exposure to shortwave ultraviolet light which has a
wavelength of 2537 A. The integrated dose (i.e., UV inten·
sity x exposure time) for erasure should be a minimum
of 15 w·sec/cm 2. The erasure time with this dosage is
approximately 15 to 20 minutes using an ultraviolet
lamp with a 12,000 ,..W/cm 2 power rating. The 8741A
should be placed within one inch of the lamp tubes duro
ing erasure. Some lamps have a filter on their tubes
which should be removed before erasure.
A.C. TIMING SPECIFICATION FOR PROGRAMMING
TA
= 25°C
= 5V
±5°C, Vcc
Symbol
±5%, Voo
= 25V ±1V
Min.
Parameter
tAW
Address Setup Time to RESET t
4tcy
tWA
Address Hold Time After RESET t
4tcy
tow
Data in Setup Time to PROG I
4tcy
two
Data in Hold Time After PROG I
4tcy
tPH
RESET Hold Time to Verify
4tcy
tvoow
Voo Setup Time to PROG t
4tcy
tVOOH
tpw
Voo Hold Time After PROG I
0
Program Pulse Width
50
trw
Test 0 Setup Time for Program Mode
4tcy
tWT
Test 0 Hold Time After Program Mode
4tcy
too
Test 0 to Data Out Delay
tww
RESET Pulse Width to Latch Address
4tcy
tr, tf
Voo and PROG Rise and Fall Times
0.5
tCY
CPU Operation Cycle Time
5.0
tRE
RESET Setup Time Before EA t.
4tcy
Note:
If
TEST 0 is high, too
can
be triggered
by
Max.
Unit
60
mS
Test Conditions
4tcy
2.0
I-'S
I-'S
RESET t.
D.C. SPECIFICATION FOR PROGRAMMING
TA
= 25°C
Symbol
±5°C, Vcc
= 5V
±5%, Voo
= 25V
±1V
Parameter
Min.
Max.
Unit
24.0
26.0
V
VOD Voltage Low Level
4.75
5.25
V
PROG Program Voltage High Level
21.5
24.5
V
0.2
V
24.5
V
VOOH
Voo Program Voltage High
VDOL
VPH
VpL
PROG Voltage Low Level
VEAH
EA Program or Verify Voltage High Level
VEAL
EA Voltage Low Level
5.25
V
100
VDD High Voltage Supply Current
30.0
mA
IPROG
PROG High Voltage Supply Current
16.0
mA
lEA
EA High Voltage Supply Current
1.0
mA
~evel
9-131
21.5
Test Conditions
0018BA
804'1 Al8641 Al8741A
WAVEFORMS FOR PROGRAMMING
COMBINATION PROGRAMiVERIFY MODE (EPROM'S ONLY)
23Y'
/
5V _ _ _ _ _.J
f-----~---'--
PROGRAM
-------~~--VER'FY
':.....t-I'>-----
PROGRAM - - - -
r-~--~
TESTO
DBO-DB,
J--
---<
DATA TO BE
PROGRAMMED VALID
NEXT ADDR
VALID
C
---L-A-ST-~\/r----------------+-----------~\/r---N-,E-~-,T---ADDRESS (8-9) VALID
ADDRESS
ADDRESS
t_V_DD_W_-~-~W-T---'-------..;..----..;..------
Voo +25 _ _ _ _ _ _ _ _ _ _ _ _
+:: ________ ---=fY-TIDW
tpw
PROG +
5----------~
two
' ___ J
r------
- --""\~-----
VERIFY MODE (ROM/EPROM)
RESET
DBO-OB7
~\'1.-._ _- - - J/
==>---
\~--
\'------'/
---<. .__AD_N~_~_~_SS_-JX _~_~_~T_:_AA_L~_~.J>-
ADDRESS
10-71 VALID
...
_____.J)(. ._____
-
-
-
-
-
-
-
-J)("--_____
A_D_D_R_ES_S_'B_-9_I_V_A_Ll_D_ _ _ _
N_EX_T_A_D_D_R_ES_S_V_A_L_'D_ _ _ _ _ _ _ __
'NOTES:
1. PROG MUST FLOAT IF EA IS LOW (I•••• ,,2311), OR IF TO.5V FOR THE 8741A. FOR THE
8041A PROG MUST ALWAYS FLOAT.
2. XTAL 1 AND XTAL 2 DRIVEN BY 3.8 MHz CLOCK WILL GIVE 4.17 ,He ICY' THIS IS ACCEPT·
ABLE FOR 8741A·8 PARTS AS WELL AS STANDARD PARTS.
3. AO MUST BE HELD LOW (I••••• OV) DURING PROGRAMIVERIFY MODES.
The .s741 A EPROM can be programmed by either of two
Intel products:
1. PROMPT-48 Microcomputer Design Aid, or
2. Universal PROM Programmer (UPP series) peripheral
of the Intellec/!) Development System with a UPP-848
Personality Card;
9-132
00188A
,10
Support Products
,~
--'-
~
'Ii
I"
I
I
Ii
iI!
I"'
~
"
I
,
I
I'
I
,
t"
I
.
'i'!
H:
"
~
:Y
.-..:::.
.
"
"'
, ';'.
~::
.:::.."..i
inter
MODEL 225
INTELLEC @SERIES 11/85
MICROCOMPUTER DEVELOPMENT SYSTEM
• Complete microcomputer development
system for MCS®-S6, MCS®-S5,
MCS®-SO, and MCS®-4S
microprocessor families
• Integral 250K byte floppy disk drive
with total storage capacity expandable
to over 2M bytes of floppy disk storage
and 7.3M bytes of hard disk storage
• High performance SOS5A-2 CPU,
64K bytes RAM memory, and
4K bytes ROM memory
• Powerful ISIS-II Disk Operating System
with relocating macroassembler,
linker, locater, and CRT based editor
CREDIT
• Supports PL/M, FORTRAN, BASIC,
PASCAL and COBOL high level
languages
• Self-test diagnostic capability
• Built-in interfaces for high speed paper
tape reader Ipunch, printer, and universal PROM programmer
• Software compatible with previous
Intellec ' systems
The Intellec Series 11/85 Model 225 Microcomputer Development System is a performance enhanced , com plete microcomputer development system integrated into one co mpact package . The Model 225 includes
a CPU with 64K bytes of RAM , 4K bytes of ROM , a 2\JOO-character CRT , detachable full ASCII keyboard wi th
cursor controls and upperllower case capability, and a 250K-byte floppy disk drive. Powerful ISIS·II Disk
Operating System software allows the Model 225 to be used quickly and efficiently for assembling and
debugging programs for Intel ' s MCS-86, MCS-85 , MCS-80 , or MCS-48 mi croprocessor familie s. ISIS-II performs all file handling operations for the user, leaving him free to concentrate o n the details of his own
application . When used with an optional in-circuit emulator (lCE TM ) module , the Model 225 provides all of
the hardware and software development tools necessary for the rapid development of a mi crocom puterbased product. Optional storage peripherals provide over 2 million bytes of floppy disk , and 7.3 million of
hard disk storage capacity .
exp o
The foll owing are trademarks of Intel Corporation and may be used only to identify Intel products :
Inlellec. Mult ib us . i. iS BC . Multimodule . ICE. iSBX . PROMPT. ieS . Library
Manager : Promware . Ins it e. MeS . RMX. Int el. Megachassi s, UP!. Intelevisio n. Microm ap . ~Scope and 'he combina tion of ICE . ieS. iS BC. iS BX. MeS. or RMX and a numerical
suffix.
© Intel Co rp oration 1980
121599-001 Rev . A
10-1
MODEL225
FUNCTIONAL DESCRIPTION
high technology LSI components. Known as the
integrated processor card (IPC), it occupies the
first slot in the cardcage. A second slave CPU card
is responsible for all remaining I/O control
including the CRT and keyboard interface. This
card, mounted on the rear panel, also contains its
own microprocessor, RAM and ROM memory, and
1/0 interface logic, thus, in effect, creating a dual
processor envi"ronment. Known as the 1/0 controller (IOC), the slave CPU card communicates
with the ~PC over an 8-bit bidirectional data bus.
Hardware Components
The Intellec Series 11/85 Model 225 is a highlyintegrated microcomputer development system
consisting of a CRT chassis with a 6-slot cardcage,
power supply, fans, cables, single floppy disk
drive, and two printed circuit cards. A separate,
full ASCII keyboard is connected with a cable.
A block diagram of the Model 225 is shown in
Figure1.
Expansion - Five remaining slots in the cardcage
are available for system expansion. Additional
expansion of 4 slots can be achieved through the
addition of an Intellec Series II expansion chassis.
CPU Cards -
The master CPU card contains its
own microprocessor, memory, I/O, interrupt and
bus interface circuitry implemented with Intel's
LOCAL
INTERRUPT
CONTROL
8259A
64K BYTES
RAM
4K BYTES
ROM
8·LEVEL
PRIORITY
INTERRUPT
8259A
?
•
t
I
I
SERIAL
CHANNELO
8251A
SERIAL
CHANNEL1
8251A
I
I
I
I
8085A·2
CPU
BIDIRECTIONAL
DRIVER
~
BAUD RATE
GENERATOR &
REAL·TIME CLOCK
8253A
;J
INTELLEC BUS
BUS
CONTROLLER
8219
PRIORITY
RESOLUTION
SYSTEM
CLOCKS
8080A·2
CPU
cp 9
DMA
~
K?
PANEL
CONTROL
I
...
,..
1
8228
SYSTEM
CONTROLLER
8K RAM
t
...
...
,..
IOC BUS
f
?
....
"..
8271
FLOPPY
CONTROLLER
.... "..
8275
CRT
CONTROLLER
KEYBOARD
I
I
-.:.II
CABLE BUS
~
8253
INTERVAL
TIMER
8041A
CPU
t
....
,..
,J
PIO BUS
8
!
PRINTER
Y
?
!
TAPE
PUNCH
t
?
f
TAPE
READER
Figure 1. Intellec Series 11/85 Model 225 Microcomputer Development System Block Diagram
10-2
AFN-014248
inter
MODEL225
System Components
troller. The master processor on the IPC transfers
a character for display to the 10C, where it is
stored in RAM. The CRT controller reads a line at a
time into its line buffer through an Intel 8257 DMA
controller and then feeds one character at a time
to the character generator to produce the video
signal. Timing for the CRT control is provided by
an Intel 8253 interval timer. The screen display is
formatted as 25 rows of 80 characters. The full set
of ASCII characters is displayed, including lower
case alphas.
The heart of the IPC is an Intel NMOS 8-bit microprocessor, the 8085A-2, running at 4.0 MHz. 64K
bytes of RAM memory are provided on the board
using 16K RAMs. 4K of ROM is provided, preprogrammed with system bootstrap "self-test"
diagnostics and the Intellec Series 11/85 System
Monitor. The eight-level vectored priority interrupt system allows interrupts to be individually
masked. Using Intel's versatile 8259A interrupt
controller, the interrupt system may be user programmed to respond to individual needs.
Keyboard - The keyboard interfaces directly to
the 10C processor via an 8-bit data bus. The
keyboard contains an Intel UPI_41TM Universal
Peripheral Interface, which scans the keyboard,
encodes the characters, and buffers the
characters to provide N-key rollover. The
keyboard itself is a high quality typewriter style
keyboard containing the full ASCII character set.
An upperllower case switch allows the system to
be used for document preparation. Cursor control
keys are also provided.
Input/Output
IPC Serial Channels - The I/O subsystem in the
Model 225 consists of two parts: the 10C card and
two serial channels on the IPC itself. Each serial
channel is RS232 compatible and is capable of running asynchronously from 110 to 9600 baud or synchronously from 150 to 56K baud. Both may be
connected to a user defined data set or terminal.
One channel contains current loop adapters. Both
channels are implemented using Intel's 8251 A
USART. They can be programmed to perform a
variety of I/O functions. Baud rate selection is
accomplished through an Intel 8253 interval timer.
The 8253 also serves as a real-time clock for the
entire system. I/O activity through both serial
channels is signaled to the system through a
second 8259A interrupt controller, operating in a
polled mode nested to the primary 8259A.
Peripheral Interface
A IJPI-41 Universal Peripheral Interface on the 10C
board provides interface for other standard
Intellec peripherals including a printer, high
speed paper tape reader, high speed paper tape
punch, and universal PROM programmer. Communication between the IPC and 10C is maintained
over a separate 8-bit bidirectional data bus. Connectors for the four devices named above, as weli
as the two serial channels, are mounted directly
on the 10C itself.
IOC Interface - The remainder of system I/O
activity takes place in the 10C. The 10C provides
interface for the CRT, keyboard, and standard
Intellec peripherals including printer, high speed
paper tape reader/punch, and universal PROM
programmer. The 10C contains its own independent microprocessor, an 8080A-2. The CPU controls
all I/O operations as well as supervising
communications with the IPC, 8K bytes of ROM
contain all I/O control firmware. 8K bytes of RAM
are used for CRT screen refresh storage. These
do not occupy space in Intellec Series II main
memory since the 10C is a totally independent
microcomputer subsystem.
Control
User control is maintained through a front panel,
conSisting of a power switch and indicator,
reset/boot switch, run/halt light, and eight interrupt switches and indicators. The front panel circuit board is attached directly to the IPC, allowing
the eight interrupt switches to connect to the
primary 8259A, as well as to the Intellec Series II
bus.
Integral Floppy Disk Drive
Integral CRT
The integral floppy disk is controlled by an Intel
8271 single chip, programmable floppy disk controller. It transfers data via an Intel 8257 DMA controller between an 10C RAM buffer and the
diskette. The 8271 handles reading and writing of
data, formatting diskettes, and reading status, all
upon appropriate commands from the 10C
microprocessor.
Display - The CRT is a 12-inch raster scan type
monitor with a 50/60 Hz vertical scan rate and
15.5kHz horizontal scan rate. Controls are provided for brightness and contrast adjustments.
The interface to the CRT is provided through an
Intel 8275 single-chip programmable CRT con10-3
AFN-014248
inter
MODEL225
MULTIBUS™ Interface Capability
All Intellec Series 11/85 models implement the
industry standard MUL TIBUS protocol. The
MULTIBUS protocol enables several bus masters,
such as CPU and DMA devices, to share the bus
and memory by operating at different priority
levels. Resolution of bus exchanges is synchronized by a bus clock signal derived
independently from processor clocks. Read/write
transfers may take place at rates up to 5 MHz. The
bus structure is suitable for use with any Intel
microcomputer family.
SPECIFICATIONS
Memory Access Time
Host Processor (lPC)
RAM - 470 ns max
PROM - 540 ns max
8085A-2 based, operating at 4.0 MHz.
RAM - 64K on the CPU card
ROM - 4K (2K in monitor, 2K in boot/diagnostic)
Bus - MULTIBUS™ bus, maximum transfer rate
of 5 MHz
Clocks - Host processor, crystal controlled at
4.0 MHz, bus clock, crystal controlled at 9.8304
MHz
Illtegral Floppy Disk Drive
Floppy Disk System Capacity 250K bytes (formatted)
Floppy Disk System Transfer Rate 160K bits/sec
Floppy Disk System Access Time Track to Track: 10 ms max
Average Random Positioning: 260 ms
Rotational Speed: 360 rpm
Average Rotational Latency: 83 ms
Recording Mode: FM
I/O Interfaces
Two Serial I/O Channels, RS232C, at 110-9600 baud
(asynchronous) or 150-56K baud (synchronous).
Baud rates and serial format fully programmable
using Intel 8251A USARTs. Serial Channel 1 additionally provided with 20 mA current loop. Parallel
I/O interfaces provided for paper tape punch,
paper tape reader, printer, and UPP-103 Universal
PROM Programmer.
Physical Characteristics
Interrupts
CHASSIS
8-level, maskable, nested priority interrupt network initiated from front panel or user selected
devices.
Width -17.37 in. (44.12 cm)
Height -15.81 in. (40.16 cm)
Depth -19.13 in. (48.59 cm)
Weight - 731b. (33 kg)
Direct Memory Access (DMA)
KEYBOARD
Standard capability on MULTIBUS interface;
implemented for user selected DMA devices
through optional DMA module-maximum transfer
rate ot5 MHz.
Width -17.37 in. (44.12 cm)
Height - 3.0 in. (7.62 cm)
Depth - 9.0 in. (22.86 cm)
Weight - 6 lb. (3 kg)
10-4
AFN-014248
MODEL225
Electrical Characteristics
Equipment Supplied
DC POWER SUPPLY
Volts
Supplied
Amps
Supplied
Typical
System
Requirements
+ 5± 5%
+12 ± 5%
-12±5%
-10 ± 5%
+ 15 ± 5%'
+24±5%'
30.0
2.5
0.3
1.0
1.5
1.7
17.0
1.1
0.1
0.08
1.5
1.7
Model 225 Chassis including:
Integrated Processor Card (IPC)
1/0 Controller Board (laC)
CRT
ROM-Resident System Monitor
Detachable keyboard
ISIS-II System Diskette with MCS-80 I MCS-85
Macroassembler
ISIS-II CREDIT Diskette CRT-Based Text Editor
Documentation Supplied
A Guide to Microcomputer Development Systems,
9800558
'Not available on bus.
Intellec® Series 1/ Model 22X/23X Instal/ation
Manual, 9800559
ISIS-I/ System User's Guide, 9800306
Intellec(~
AC REQUIREMENTS FOR MAINFRAME
110V, 60 Hz - 5.9 Amp
220V, 50 Hz - 3.0 Amp
Series 1/ Hardware Reference Manual,
9800556
8080/8085 Assembly
Manual, 9800301
Language
Programming
ISIS-II 8080/8085 Assembler Operator's Manual,
9800292
Intel/ec'~ Series
Listing, 9800605
1/ Systems
Monitor Source
Intel/ec'" Series II Schematic Drawings, 9800554
ISIS-I/ CREDIT (CRT-Based Text Editor) User's
Guide, 9800902
Environmental Characteristics
Additional manuals may be ordered from any Intel
sales representative or distributor office, or from
Intel Literature Department, 3065 Bowers Avenue,
Santa Clara, California 95051.
Operating Temperature -16°C to 32°C
(61 ° F to 90°F)
Humidity - 20% to 80%
ORDERING INFORMATION
Part
Number
Description
MDS-225' Intellec' Series 11/85 Model 225
Microcomputer
Development System (11 OV 160 Hz)
MDS-226' Intellec' Series 11/85 Model 226
Microcomputer
Development System (220V 150 Hz)
"'MDS" is an ordering code only, a~d is not used as a product
name or trademark. MDS") is a registered trademark of
Mohawk Data Sciences Corp.
10-5
AFN-014248
INTELLEC PROMPT 48
MCS·48 MICROCOMPUTER DESIGN AID
1
Complete low cost design aid and
EPROM programmer for revolutionary
MCS·48 single component computers
.
256 bytes expandable RAM data memory
in PROMPT system
Simplifies microcomputing, allowing user
to enter, run, debug, and save machine
language programs with calculator·like
ease
Utilizes two removable 8·bit MCS·48
CPUs
8748 CPU with erasable, reprogram·
mabie on·chip program memory
8035 CPU with off·chip program
memory
27 on·chip TTL compatible expandable
110 lines
On·chip clock, internal timer/event
counter, two vectored interrupts, eight
level stack control
Single + 5V DC system power
requirement
Integral keyboard and displays (no tele·
typewriter or CRT terminal required)
1K·byte erasable, reprogram mabie on·
chip (8748), expandable program memo
ory, 1K·byte RAM in PROMPT system
Extensive PROMPT 48 monitor, allowing
system 110, bus, and memory expansion
64 bytes RAM on·chip, expandable
register memory
Includes comprehensive design library
The Intellec Prompt 48 MCS-48 Microcomputer Design Aid is a low cost , fully-assembled design aid for the revolutionary 8748 single component microcomputer. PROMPT 48 simplifies the programming of MCS-48 systems - programs may be entered and debugged with calculator-like ease on the large, informative display and keyboard panel.
The comprehensive design library with tutorial manual is ideal for newcomers to microcomputing. PROMPT 48's
panel connector allows easy access to 1/0 ports and system bus. Thus users can expand program memory beyond the
1K bytes provided internally.
INlIl COIIPORATMlN ASSIIoIES NO RESPONSllmy fOR THE US[ Of ANY CmCIJITRY OTHER THAN CIRCUITRY EIoflOO[O IN AN INTEL PllOOUCT. NO OTHER CIRCUIT PATENT LICENSES ARE IMPI.[O.
" INTEl COIIPORATlON, )979
10-7
AFN-00352A ~01
INTELLEC PROMPT 48
FEATURES
Single Component Compu.ter
The 8748 is the first microcomputer fully integrated on
one component . All elements of a computing system are
provided, including CPU, RAM, I/O, timer, interrupts, and
erasable, reprogram mabie nonvolatile program memory.
Programming Socket
PROMPT's programming socket programs this revolu·
tionary " smart PROM"-the 8748-in a highly reliable,
convenient manner. A fail·safe interlock ensures the
device is properly inserted before applying programming pulses. Each location may be individually programmed, one byte at a time. A read-before-write
programming algorithm prevents device damage by
inadvertently programming unerased memory.
real time - after each instruction the MCS-48 program
counter is compared against pending breakpoint!\. If no
break is encountered, execution resumes. The go single
step (GO SINGLE STEP) mode exercises one instruction
at a time. Commands are like sentences, with parameters separated by [i] NEXT. Eadh command ends with
[i] EXECUTE/END. In addition to the PROMPT basic
commands, thirteen functions simplify programming.
Each is started merely by pressing a hex datalfunction
key and entering parameters as required, as shown in
Table 1.
MCS·48 Processors
The execution socket accepts either an 8035 or an 8748
MCS-48 processor. Both are supplied with each
PROMPT 48, and either can serve as heart of the
PROMPT system. There are no processors within the
PROMPT 48 mainframe, which instead contains monitor
ROM and RAM, user RAM, peripherals, drivers, and
sophisticated control circuitry. Once a processor is
seated in the execution socket and power is applied, the
PROMPT system comes to life. Various access modes
may be selected such as program execution from
PROMPT system RAM , or from on-chip PROM. Thus programs may first be executed from PROMPT RAM with
the 8035 processor. When debugging is complete, the
8035 (execution socket) processor can program the 8748
(programming socket) processor. Finally, a programmed
8748 processor .may be exercised by itself from the
execution socket. The execution socket processor runs
either monitor or user programs.
System Monitor
The system reset command initializes the PROMPT
system and enters the monitor. The monitor interrupt
command exits a user program gracefully, preserving
system status and entering the monitor. The user interrupt command causes an interrupt only if the PROMPT
system is running a user program. A comprehensive
system monitor resides in four 1K-byte read only
memories. It drives the PROMPT keyboard and displays
and responds to commands and functions. fhe top 16
bytes of on-Chip program memory must be used by the
PROMPT system to switch between monitor and user
programs. It requires one level of the MCS-48 eight-level
stack.
Commands
PROMPT 48's commands are grouped and color-coded
to simplify access to the 8748's separate program and
data memory. Registers , data memory, or program memory, may be examined and modified with the examine
and modify commands. Then either the next or previous
register and memory locations may be accessed with
one keystroke. Programs may be exercised in three
modes. The go no break (GO NO BREAK) runs in real
time. The go with break (GO WITH BREAK) mode is not
10-8
AFN-00352A-02
INTELLEC PROMPT 48
Cable Interface
Key
An optional cable, PROMPT-SER, directly connects the
PROMPT system to virtually any terminal via a rear
access slot.
Funcllon
Operallon
I}]
Port 2 map
Allows specification of direction of each pin
on port 2. Port 2 is multiplexed to address
external program memory and expand 110.
Thus it must\be buffered; the P2 map command establishes the direction of buffering.
[}]
Program EPROM
Byte search
(with optional
mask)
Programs 8748 EPROMs.
Sweeps through register, data, or program
memory searching for byte matches. Start·
ing and ending memory addresses are specified.
~
Word search
(with optional
mask)
Sweeps through register, data, or program
memory searching for word matches. Starting and ending memory addresses are specified.
[!]
He x calculator
Computes hexadeci mal sums and differ-
I2l
8748 program
lor debug
Sim ilar to program EPROM, but ensures that
the top of program memory co ntains monitor re-entry code for debugging .
[!]
Compare
Verifies any portions of EPROM program
memory against PROMPT memory.
[!]
Move memory
Allows blocks of regi ster, data, or program
memory to be moved.
~
Access
Specifies one of six access modes for PROMPT 48. For example EPROM, PROMPT
RAM, or external program memory, and a
variety of input/output options may be
selected.
[ID
Breakp oint
Allows any or all of the eight breakpoints to
be set and cleared.
[9
Clear
Clears portions of regi ster, data, or program
memory.
@I
Dump
Dumps register, data, or program memory to
PROMPT's serial chan nel : for example, a
teletypewri t er paper tape punch .
[]]
Enter
Enters (reads) register, data, or program
memory from PROMPT's serial channel.
IIJ
Fetch
Fetches programs from EPROM to PROMPT
RAM .
~
ences.
Table 1_ PROMPT 48 Commands and Functions
Access
Easy access to the pins of the executing processor is
provided via the 110 ports and bus connector. Only the
EA external access, SS single step, and X1, X2 clock
inputs are reserved for the PROMPT system.
Expansion
Program or data memory may be expanded beyond that
provided on-chip or in the PROMPT system. 1/0 ports
may be expanded, as with the 8243, or peripheral controllers may be memory-mapped. The 1/0 ports and Bus
connector allows the execution socket processor to be
directly interfaced to prototype systems, yet be controlled from the PROMPT panel.
Control
The commandlfunction group panel keyboard and displays completely con trol PROMPT 48-a teletypewriter
or CRT terminal is not needed. A hyphen prompting
character appears whenever a command or function can
be entered. Addresses and data are shown whenever
examining registers and memory. Parameters for commands and functions are also shown .
10-9
AFN~OO352A-03
INTELLEC PROMPT 48
FUNCTIONAL DESCRIPTION
"PROMPT" stands for PROgraMming Tool. It Is a programmer for 8748 EPROMs, and a versatile aid for
debugging MCS-48 programs. Programs can be entered
via its Integral panel keyboard, programming socket, or
serial channel. Almost any terminal can be Interfaced to
the serial channel, Including a teletypewriter, CRT, or an
Intellec microcomputer development system. Intellec
PROMPT 48 simplifies the programming of MCS-48
systems. Like the 8748 It Is radically new, highly Integrated, and expandable. Like the MCS·48 family, it Is
low cost, and Ideal for small applications and programs.
It Is a design aid, not a development system with
sophisticated software and peripherals.
MCS-48 Processors
PROMPT 48 comes complete with two of Intel's revolutionary MCS-48 processors: an 8748-4 Single Component 8-Blt Microcomputer and and 8035-4 Single Component 8-Blt Microcomputer. Advances In n-channel MOS
technology allow Intal, for the first tima to integrate Into
one 40-pin component all computer functions:
8-blt CPU
1K x 8-blt EPROM/ROM program memory
64 x 8-bit RAM data memory
27 Input/output lines
8-blt timer/event counter
Performance - More than 90 instructions - each one
or two cycles - make the single chip MCS-48 equal in
performance to most multi-chip microprocessors. The
MCS-48 Is an efficient controller and arithmetic processor, with extensive bit handling, binary, and BCD
arithmetic instructions. These are encoded for
minimum program length; 70% are single byte operation codes, and none Is more than two bytes.
Flexibility - Three interchangeable, pin-compatible
devices offer flexibility and low cost in development and
production, as follows:
8748 - with user-programmable and erasable EPROM
program memory for prototype and pre-productions
systems.
8048 - with factory-programmed mask ROM memory
for low-cost, high volume production.
8035 - without program memory, for use with external
program memories.
Circuitry - Each MCS-48 processor operates on a
single + 5V supply, with internal oscillator and clock
driver, and circuitry for Interrupts and resets. Extra circuitry is inthe 8048 ROM processor to allow low power
standby operation. The 64 x 8 RAM data memory can be
independently powered.
Compatibility - For systems requiring additional compatibility, the MCS-48 can be expanded with the new
8243 110 expander, 8155 I/O and 256-byte RAM, 8755 110
and 2K-byte EPROM, or 8355 110 and 2K ROM devices.
MCS-48 processors readily Interface to MCS-80/85
peripherals and standard memories.
Memory Capacity
PROMPT 48 is a complefe, fully assembled and powered
microcomputer system including program memory, data
memory, 110, and system monitor beyond that available
on MCS-48 single component computers. 1K bytes of
PROMPT system RAM serve as "writable program memory" - a ROM simulator for the program memory on
each MCS-48 computer. 256 bytes of PROMPT system
RAM serve as "external data memory," beyond the 64
register bytes on each MCS-48 computer. Users may further expand program or data memory via the panel 110
ports and bus connector.
Programming
Programs written first In assembly language, are
entered In machine language and debugged with
calculator-like ease on the large, Informative display
and keyboard panel. Most MCS-48 operations can be
specified with only two keystrokes. Once entered,
routines can be exercised one Instruction (single step)
or many Instructions at a time. The principal MCS-48
register - the accumulator - Is displayed while single
stepping. Programs can be executed in real time (GO
NO BREAK) or with as many as eight different breakpoints (GO WITH BREAK).
Control
PROMPT 48 can be fully controlled either by the panel
keyboard and displays, or remotely by a serial channel.
Thus a teletypewriter or CRT can be used but neither Is
required.
Access
The PROMPT panel 110 ports and bus connector allow
easy access to all MCS-48 pins except those reserved
for control by the PROMPT system, namely EA external
access, SS Single step, and X1, X2 clock inputs.
Optional Expansion
PROMPT 48 may be expanded beyond the resources on
both the MCS-48 single component computer and the
PROMPT system. External program and data memory
may be Interfaced and input/out ports added with the
8243 110 expander.
10-10
AFN-00352A-04
INTELLEC PROMPT 48
Documentation
The PROMPT 48 manual Includes chapters for the
reader with little or no programming experience. Topics
treated range from number systems to microcomputer
hardware design. A novel, unifying set of tutorial
diagrams - MICROMAPS - simplify microcomputer
User Interrupt - causes an Interrupt only If the
PROMPT system Is running a user program.
SPECIFICATIONS
Timing
The processor traps to location 316. The MCS-48 timer/event counter is not used by the PROMPT system and is
available to the user. Either timer flag or interrupt will
signal when overflow has occurred. The timer interrupt
can be used only in the go-no-break (real time) mode.
Basic Instruction - 2.5 ,..s
Cycle Time - tCY
2.5,..s
Clock - 6 MHz ± 0.1%
=
Memory Bytes
The 8748 contains 64 bytes of register memory, no external data memory, and 1024 bytes of RAM program
memory. The PROMPT system provides 256 bytes of external data memory, and 1024 bytes of RAM program
memory. PROMPT RAM program memory can be used
in place of the on-chip EPROM program memory; thus
programs less than 1024 bytes may be designed. For
larger programs additional memory can be directly Interfaced to the MCS-48 bus via the PROMPT panel I/O
ports and bus connector.
Memory Configuration
Memory
Reglsler
Dala
Program
concepts. PROMPT's handy, pocket-sized reference
card let can be affixed to the mainframe. Programming
pads aid in the organization and documentation of programs. These features, plus a comprehensive design
library of manuals, articles, and application notes,
make the Intellec PROMPT 48 ideal for the newcomer to
mlcrocomputlng.
Maximum
On Chip
In PROMPT 48
64
3328
4006
64
0
1024 EPROM
0
256
1024 RAM
EPROM Programming
PROMPT 48 provides a programming socket to directly
program 8748s. Programs are loaded Into the PROMPT
RAM program memory via keyboard. EPROM, teletypewriter, or other serial interface. A fail-safe interlock
ensures programming pulses are applied only if the
device is properly inserted. Inadvertant reprogramming
is prevented by a read-before-write programming algorithm. Each location may be individually programmed,
one byte at a time.
Panel 1/0 Ports and Bus Connectors
1/0 Ports
All MCS-48 I/O ports are accessible on the PROMPT
panel connector.
Bus - A true bidirectional 8-bit port with associated
strobes. If the bidirectional feature is not needed, bus
can serve as either a statically latched output port or a
non-latching Input port. Input and output lines cannot
be mixed.
Ports 1 and 2 - Data written to these 8-bit ports is
latched and remains unchanged until written. As Inputs
these lines are not latching. The lines of ports 1 and 2
are called quasi bidirectional. A special output structure
allows each line of port 1 and half of port 2 to serve as an
input, an output, or both. Any mix of input, output, and
both lines is allowed.
TO, n, and INT - Three pins that can serve as Inputs. TO
can be designated as a clock output. Input/output can
be expanded via the PROMPT panel connector with a
special I/O expander (8243) or standard peripherals.
Reset and Interrupts
Relit - Initializes the PROMPT system and enters the
monitor.
Monitor Interrupt - exits a user program gracefully,
preserving system status and entering the monitor.
10-11
All MCS-48 pins, except five, are accessible on the I/O
ports and bus connector. The five reserved for PROMPT
system control are EA external access, SS single step,
X1, X2 crystal Inputs, and 5V. Due to internal buffering
of the MCS-48 bus, access times will be negligibly
degraded by the PROMPT system. Since MCS-48 processors do not communicate internal address gate
status, bus data must be driven out If neither PSEN nor
RD is asserted.
System Devices'
Both user programs and the PROMPT monitor enjoy access to system devices: serial I/O, panel displays, and
keyboard. These are memory-mapped to program
memory addresses beyond 2K.
Serial I/O - The serial I/O port (data 820 16 , control 821 16)
Is defined by software and jumpers for 110 baud, 20 mA
current loop, but can easily be jumpered for other baud
rates and RS232C levels. Asynchronous or synchronous
transmission, data format, control characters, and parity can be programmed.
Panel Displays - Eight display ports (data 810-817 1sl
allow each of the panel displays to be written from user
programs. Data written on a display device will time out
after a fixed interval. Displays must be refreshed on a
polled or interrupt-driven basis. User programs can call
software drivers which provide this capability.
AFN-00352A-05
INTELLEC PROMPT 48
Keyboard -. Software Is used to debounce the panel
keyboard (data 810 16 ). The monitor's Input routines (see
Software Drivers) provide this debouncing and can be
called from user programs.
Equipment Supplied
Commands
Single step}
With break
No break
Panel 110 Ports and Bus Connector - 3M 3425 Flat
Crimp. A complete cable set Including wlrewrap header
for prototyplng Is included with each PROMPT.
Go
Register}
{ Data
Memory
Program
Open previous/clear/Emtry [!] Next 0 Execute/End
Examine/modify
Functions
iii Port 2 map
lil Program EPROM (8748)
I!l Search (R, 0 or P)' memory for 1 byte, optional
mask
IL Search (R, 0 or P) memory for 2 bytes, optional
PROMPT 48 mainframe with two MCS-48 processors
(8748, 8035), display/keyboard, EPROM programmer,
power supply, cabinet, and ROM-based monitor.
110 V AC power cable
110 or 220 V AC
Fuse
Panel 110 ports
Bus connector cable set
Physical Characteristics
Height - 5.3 in. (13.5 cm) max
Width - 17 in. (43.2 cm)
Depth - 17 in. (43.2 cm) max
Weight - 21 lb. (9.6 kg)
mask
Ii] Hexadecimal calculator
+,-
[] 8748 program EPROM for debug
IiJ Compare EPROM with memory
Ii] Move memory (R, 0 or P)
-00 Access
Ii] Breakpoint
~ Clear memory (R, 0 or P)
Ii!] Dump memory (R, 0 or P)
IEJ Enter (read) memory (R, 0 or P)
If] Fetch EPROM program memory
Nole
*R, D, or P is register, data, or program.
Software Drivers
Panel Keyboard In - KBIN, KDBIN
Panel Display Out - DGS6, DGOUT, HXOUT, BLK,
REFS, ENREF
Serial Channel - CI, CO, RI, PO, CSTS
Connectors
Serial 110 - 3M 3462·0001 Flat Crimp/AMP 88106·1 Flat
Crimp/ TI H312113 Solder/AMP 1·583485-5 Solder.
Electrical Characteristics
Po' 'er Requirements - either 115 or 230V AC (± 10%)
may be switch selected on the mainframe. 1.8 amps
max current (at 125 V AC).
Frequency - 47-63 Hz
Environmental Characteristics
Operating Temperature - O·C to + 40·C
Non·Operatlng Temperature - 20·C to + 65·C
Reference Manuals
9800402 Intellec PROMPT 48 User's Manual
(SUPPLIED)
9800270 - MCS·48 User's Manual (SUPPLIED)
9800255 - MCS-48 and UPI-41 Assembly Language
Programming M~nual (SUPPLIED)
Reference manuals are shipped with each product only
if deSignated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Bowers
Avenue, Santa Ciara, California 95051.
ORDERING INFORMATION
Part Number Description
PROMPT-48 or
Intellec PROMPT 48 MCS-48 microPROMPT-48-220V computer design aid. Complete with
two MCS·48 processors (8748 and
8305), EPROM programmer, integral
keyboard; displays, and system
monitor in ROM.
PROMPT-SER
Serial cable for connecting PROMPT
to TTY, CRT
10-12
AFN-00352A-Q6
ICE·49
MCS·48 IN·CIRCUIT EMULATOR
Emu/etes 8049, 8048, 8748, 8039, 8035, end 8021* MIcrocomputers
Extends Intellec microcomputer development system debug power to user configured system via external cable and
40-pln plug, replacing system MCS-48
device
Emulates user system MCS-48 device in
real time
Eliminates need for extraneous debugging tools residing in user system
Collects bus, register, and MCS-48
status information on instructions
emulated
Shares static RAM memory with user
system for program debug
Provides capability to examine and alter
MCS-48 registers, memory, and flag
values, and to examine pin and port
values
Provides hardware comparators for user
designated break conditions
Integrates hardware and software efforts
early to save development time
The ICE-49 MCS-48 In-Circuit Emulator module is an Intellec-resident module that interfaces with any MCS-48 system_
The MCS-48 family consists of the 8049, 8048, 8748, 8039, 8035, and 8021 microcomputers_ The ICE-49 module interfaces with an MCS-48 system through a cable terminating in an MCS-48 pin-compatible plug which replaces the
MCS-48 device in the sytem_ With the ICE-49 plug in place, the designer has the capability to execute the system In.
real time while collecting up to 255 instruction cycles of real-time trace data. In addition, he can single step the system
program to monitor more closely the program logic during execution. Static RAM memory is available through the
ICE-49 module to emulate MCS-48 program and data memory_ The designer can display and alter the contents of data
and replacement RAM control memory, internal MCS-48 registers and flags and I/O ports. Powerful debug capability is
extended into the MCS-48 system while ICE-49 debug hardware and software remain inside the Intellec system. Symbolic reference capability allows the designer to use meaningful symbols rather than absolute values when examining
and modifying memory, registers, flags, and I/O ports in this system.
'*EM1 emulator board is also required.
10-13
AFN-01103A-01
ICE·49
FUNCTIONAL DESCRIPTION
Integrated Hardware/Software Development
The user prototype need consist of no more than an
MCS-48 socket and timing logic to begin integration of
software and hardware development efforts. Through
the ICE-49 module mapping capabilities, Intellec system
resources can be accessed to replace prototype memo
ory. Hardware designs can be tested using the system
software to drive the final product. Thus, the system in·
tegration phase, which can be costly when attemptin.g
to mesh completed hardware and software products,
becomes a convenient two·way debug tool when begun
early in the design cycle.
Debug Capability Inside User System
The ICE-49 module provides the user with the ability to
debug a full prototype or production system wi.thout
introduCing extraneous hardware or software test tools.
The module connects to the user system through the
socket provided for the MCS-48 device in the user
system. Intellec memory is used for the execution of the
ICE-49 software. The Intellec console and file handling
capabilities provide the designer with the ability to com·
municate with the ICE-49 module and display informa·
tion on the operation of the prototype system. The
ICE-49 module block diagram is shown in Figure 1.
Real· Time Trace
The ICE-49 module captures trace information while the
designer is executing programs in real time. The instruc·
tions executed, program counter, port values for bus 0,
port 1 and port 2, and the values of selected MCS-48
status lines are stored for the last 255 instruction cycles
executed. When reirieved for dispiay, code is disassem·
bled for user convenience. This provides data for deter·
mining how the user system was reacting prior to emu·
lation break, and is available whether the break was user
initiated or the result of an error condition. For more
detailed information on the actions of internal registers,
flags, or other system operations, the user may operate
in single or multiple step sequences tailored to system
debug needs.
Batch Testing
In conjunction with the ISIS·II diskette operating
system, the ICE-49 module can run extensive system
diagnostics without operator intervention. The designer
or test engineer can define a comp!ete diagnostic eX6icise, which is stored in a file on the diskette. When actio
vated with an ISIS·II submit command, this file can
instruct the ICE-49 module to execute the diagnostic
routine and store the results in another file on the
diskette. Results are available to the designer at his con·
venience. In this way, routine diagnostics and long term
testing may be done without tying up valuable man·
power.
EMULATOR BOARD
SYNC 0
SYNC 1
CONTROL PROCESSOR BOARD
-------11------------1
I
II
I
r....l.....I....I-JI-------I
II
I
I
II
USER SOCKET
I
CABLE
BUFFER
INTERNAL
TIMER
II
II
II
I-
I
I
I
I
I
I
I
f-----,--=-::::.:-:..:.,
UJ
~ !
~ I
8080
CONTROL
PROCESSOR
P1
P2A
8049 OR 8048
WIINTERNAL
MONITOR P~~I-
_ _ _ _ _ _=,:;:-:-_---"
I
CONTROL
SCRATCH
PAD
I
I
I
CONTROL
PROG R AM
I
I
I
L __ _
_ ______
II
~
z
~ I
~ I
~
!2
1
I
I
I
I
L__ ·__________ ~
Figure 1. ICE-49 Module Block Diagram
10-14
AFN-01103A-02
ICE·49
Memory Mapping
The 8049, 8748 and 8048 contain internal program and
data memory. Both program and data memory can be
expanded using external memory devices.
Internal Memory - When the MCS-48 microcomputer is
replaced by the ICE-49 socKet in a system, the ICE-49
module supplies static RAM memory as a replacement
for the internal microcomputer memory. The ICE-49
module has enough RAM memory available to emulate
up to the total 4K control memory capability of the system_ The ICE-49 module also provides for up to 384
bytes of data memory.
External Memory The ICE-49 module separates
replacement control memory into sixteen 256-byte
blocKs. Replacement external data memory consists of
one 256-byte block. Each block of memory can be defined separately as supplied by the user system or supplied by the ICE-49 module. The user may assign ICE-49
equivalent memory to take the place of external memory
not yet supplied in his system.
Symbolic Debugging
ICE-49 software provides symbolic definition of all
MCS-48 registers, flags, and selected MCS-48 pins.
Symbolically defined pseudo registers provide access
to the sense of MCS-48 flip flops which enable time,
counter, interrupt, and flag-01lIag-1 options. In addition,
the user may reference locations in program and data
memory, or their contents, symbolically. The user symbol table generated along with the object file during a
program assembly may be loaded to Intellec memory for
access during emulation. The user is encouraged to add
to this symbol table any additional symbolic values for
memory addresses, constants, or variables he may find
useful during system debugging. Symbols may be substituted for numeric values in any of the ICE-49 commands. Symbolic reference is a great advantage to the
system designer. He is no longer burdened with the
need to recall or look up those addresses of key locations in his program that can change with each assembly. Meaningful symbols from his source program may
be used instead. For example, the command:
GO FROM .START TILL XDATA. RSLT WRITTEN
begins execution of the program at the address referenced by the label START in the designers assembly
program. A breakpoint is set to occur the first time the
microprocessor writes to the external data memory
location referenced by RSLT. The designer does not
have to be concerned with the physical locations of
START and RSLT. The ICE-49 software driver supplies
them automatically from information stored in the
symbol table.
Intel 8080 to communicate with the Intellec host processor via a common memory space. The 8080 also controls an internallCE-49 bus for intramodule communication. ICE-49 hardware consists of two PC boards, the
controller board, and the emulator board, all of which
reside in the Intellec chassis. A cable interfaces the
ICE-49 boards to the MCS-48 system. The cable terminates in a MCS-48 pin compatible plug which
replaces any MCS-48 device in the user system. The
ICE-49 module block diagram is shown in Figure 1.
Real-Time Trace
Trace Buffer - While the ICE-49 module is executing
the user program, it is monitoring port, program
counter, data, and status lines. Values for each instruction cycle executed are stored in a 255 x 44 real-time
RAM trace buffer. A resetable timer resident on the controller board counts instruction cycles.
Controller Board
The ICE-49 module talks to the Intellec system as a
peripheral device. The controller board receives commands from the Intellec system and responds through
the parameter block. Three 15-bit hardware breakpoint
registers are available for loading by the user. While in
emUlation mode, a hardware comparator is constantly
monitoring address and status lines for a match to terminate an emulation. The breakpoint registers provide a
signal when a match is detected. The user may disable
the emulation break capability and use the signal to synchronize other debug tools. The controller board returns
real-time trace data, MCS-48 register, flag, and pin
values, and ICE-49 status information, to a control block
in the Intellec system when emulation is terminated.
This information is available to the user through the
ICE-49 interrogation commands. Error conditions, when
present, are automatically displayed on the Intellec
system console. The controller board also contains
static RAM memory, which can be used to emulate
MCS-48 program and data memory in real time. 4K of
memory is available in sixteen 256-byte pages to emulate MCS-48 PROM or PROM program memory. A 256byte page of data memory is available to access in place
of MCS-48 external data memory. The controller board
address map directs the ICE-49 module to access either
replacement ICE-49 memory or actual user system external memory in 256-byte segments based on information provided by the user.
Emulator Board
The emulator board contains the 8049* and peripheral
logiC required to emulate the MCS-48 device in the user
system. A software selectable 6 MHz or 3 MHz clock
drives the emulated MCS-48 device. This clock can be
disabled and replaced with a user supplied TTL clock in
the user system.
Hardware
The ICE-49 module is a microcomputer system utilizing
Intel's 8049 or 804818748 microcomputer as its nucleus.
The 8049 provides the 8049, 8039 emulation characteristics. The 804818748 provides the 8748180481803518021
emulation characteristics. The ICE-49 module uses an
10-15
·Use 8048 with internal monitor program when emulating 8748/80481
803518021.
AFN-01103A-03
ICE·49
Cable Card
The cable card is included for cable driving. It transmits
address and data bus information to the user system
through a 40·pin connector which plugs into the user
system in the socket designed for the MCS·48 device.
Command
Operation
Display
Prints contents of memory, MCS·48
device registers, 1/0 ports, flags, pins,
real·time trace data, symbol table, or
other diagnostic data on list device.
Alters contents of memory, register,
output port, or flag. Sets or alters break·
pOints and display registers.
Defines memory status.
Establishes mode of display for output
data.
Establishes mode of display input data.
Change
Software
The ICE·49 software driver Is a RAM·based program
which provides the user with an easy to use command
language (see Table 1, Table 2, and Table 3) for defining
breakpoints, initiating real·time emulation or single step
operation, and interrogating and altering user system
status recorded during emulation. The ICE·49 command
language contains a broad range of modifiers to provide
the user with maximum flexibility in defining the opera·
tion to be performed. The ICE·49 software driver is
available on diskette and operates in 32K of Intellec
RAM memory.
Go
Step
Interrupt
Suffix
Table 2. ICE·49 Interrogation Commands
Command
Load
Save
Operation
Command
Enable
Map
Base
Activates breakpOint and display regis·
ters for use with go and step com·
mands.
Initiates real·time emulation and allows
user to specify breakpoints and data
retrieval.
Initiates emulation in single instruction
Increments. Each step is followed by
register dump. User may optionally
tailor other diagnostic activity to his
needs.
Emulates user system interrupt.
Table 1. ICE·49 Emulation Commands
Define
Move
list
Exit
Evaluate
Remove
Reset
Operation
Fetches user symbol table and object
code from input device.
Sends user symbol table and object
code to output device.
Enters symbol name and value to user
symbol table.
Moves block of memory data to another
area of memory.
Defines list device.
Returns program control to ISIS·II.
Converts expression to equivalent
values in binary, octal, decimal, and
hex.
Deletes symbols from symbol table.
Reinltiallzes ICE·49 hardware.
Table 3. ICE·49 Utility Commands
SPECIFICATIONS
System Clock
ICE·49 Operating Environment
Crystal controlled 6.0 MHz internal, 3.0 MHz internal or
user supplied TTL external: software selectable.
Required Hardware
Intellec microcomputer development system
System console
Intellec diskette operating system
ICE·49 Module
Required Software
System monitor
ISIS·II
Equipment Supplied
Printed circuit boards (control board, emulator board)
Interface cables and buffer module
ICE·49 software, diskette·based version (single density
or double density)
8048 with internal monitor program
Physical Characteristics
Width Height Depth Weight -
12.00 In. (30.48 cm)
6.75 in. (17.15 cm)
0.50 in. (1.27 cm)
8.00 lb. (3.64 kg)
Electrical Characteristics
DC Power Requirements
Vee = +5V ±5%
lee = 10A mal(; 7.0A typ
Voo = + 12V ±5%
100
79 mA max; 45 mA typ
Vss = -10V ±5%
Iss = 20 mA max
=
10-16
AFN·01103A·04
inter
EM1
8021 EMULATION BOARD
EPROM functional equivalent of 8021 single component 8·bit microcomputer
Based on 8748 - user programmablel
erasable EPROM 8·bit computer
Operates with ICE·49™ module to provide
full in·circuit debugging of 8021 prototype
system
Connects to prototype system through
8021 pin compatible plug
On·card 3.0 M Hz or external TTL driven
clock
Portable 4" x 7" microcomputer circuit
assembly
The EM1 emulator board is a ready-to-use 4" x 7" microcomputer circuit assembly that emulates the Intel 8021
microcomputer. A 12-inch flat-cable assembly connects the board to the 8021 socket in a prototype system. The board
is designed so that it can be mounted either as a stand-alone unit, or within the prototype assembly.
The 8021 microcomputer has 1K x 8 mask-programmable ROM program memory and 64 by 8 RAM data memory. The
EM1 is controlled by an Intel 8748, with 1K of EPROM program memory and a 64 byte data memory. The EPROM can be
programmed and erased repeatedly during hardware and software development. The EM1 has several ancillary circuits
that perform the following functions which are specific to ttie 8021:
Zero crossing detector
Crystal controlled clock/buffer
Port 0 simulator
For prototype debugging, the 8748 can be removed from its socket and replaced with a cable to an ICE-49 module.
When used with the EM1, ICE-49 module emulates the 8021 in real-time, or single-steps the 8021 program at the user's
command. A full range of capabilities for examining and modifying 8021 memory and status are supplied through
ICE-49 module.
10-17
AFN-00801 A-01
EM1
HARDWARE
Zero Cross Detection Simulator
The zero cross detection simulator enables the 8748's
T1 Input to detect zero-crossings. The circuitry provides
a high level signal on a positive crossing and a low level
signal on a negative crossing of zero to the T1 Input of
the 8748.
The EM1 emulation board uses the 8748 to perform the
emulation.
PO Simulator
Port 0 of the 8021 Is a quasi"-bldlrectlonal port. The PO
simulator converts the data bus of the 8748 Into a quasibidirectional port.
Reset Buffer
Crystal Control Clock Buffer
The 8021 resets on a logic HIGH level signal. However,
the 8748 resets on a logic LOW level, thus an Inverter Is
provided on the EM1 to make the two chips compatible.
The EM 1 allows user to select an on-board oscillator or a
TTL clock driven from the 8021 user's prototype system
via a Camblon Suitcase jumper.
Optional Pull·Ups
Jumper
W1
Poaltlon
State
A- B
On-Board
External
TIL Clock
C-D
Resistors are provided to simulate the optional pull-up
resistors on T1 input and Port 0 of the 8021. A removable
resistor pack is used on Port O. The T1 input pull up can
be Installed by soldering In a 50K resistor.
Software
"A bidirectional port which serves as an Input port. output port, or both even though outputs are statically
latched.
When emulating the 8021 with EM1, the user must
observe the 8021 Instruction set.
DB0- DB7
P10 - P17
P20- P28
r-______________
8748
OR
4()'PIN
PLUG
40
LINES
~A~LE~
__________________
~
8021
CABLE
PLUG
PROG
r-1
CABLE TO
ICE-49
MODULE
CRYSTAL
CONTROL
CLOCK
.......----~
RESET
r-----------~--~Tl
t--.-----------------------o<
1------1---1 RESET
. I
RE~ET BUFFER
CLOCK
L2!!!I~
I
r- - -..,
'-oiiiCIAFiD . ,
I
12 INCHES
FLAT CABLE
r-__________.......__-""XTAL 1
Tlr-~-----
28
LINES
I OPTIONAL I
I
28·PIN
SOCKET
LP~L~ ...J
.J
10-18
AFN-00801A-02
EM1
SPECIFICATIONS
Operating Environment
Stand·Alone
Required Hardware:
EM1 emulation board
In·Circuit Emulation
Required Hardware:
EM1 emulation board
Intellec Microcomputer Development System con·
figurated with ICE·49 module
Equipment Supplied
System Clock
Crystal controlled 3.0 MHz on board or user supplied
TIL external clock: hardware jumper selectable.
Physical Characteristics
Width: 7.0 in (17.78 cm)
Height: 4.0 in. (10.16 cm)
Depth: 0.75 in. (1.91 cm)
Weight: < 1.0 Ibs. (0.45 kg)
Electrical Characteristics
DC Power:
Vcc5V ±5%
Icc 300 mA (max.)
EM1 printed circuit board
Environmental Characteristics
12" long flat cable terminating in 28·pin plug, pin com·
patible with 8021
Operating Temperature: 0 - 55°C
EM1 Operator's Manual
Operating Humidity: up to 95%
without condensation
relative humidity
ORDERING INFORMATION
PART NUMBER
Description
MDS·EM1
8021 Emulation Board
10-19
AFN·00801 A·03
EM2
8022 EMULATION BOARD
Portable 4.25" x 2.75" microcomputer
circuit assembly
Provides Intel® 8755A -
2K x 8 EPROM
Connects directly into prototype system
through Intel® 8022* pin compatible
socket
EPROM functional and electrical
equivalent of Intel® 8022 - single
component 8·bit computer
The EM2 emulator board is a ready·te-use 4.25" x 2.75" microcomputer circuit assembly that emulates the Intell!> 8022
single chip microcomputer. The emulator board is designed to plug directly into the 8022 socket. No Interfacing and
interconnection cables are necessary. Power is obtained from the user's system.
The EM2 emulator board provides the user a full EPROM functional and electrical equivalent of the 8022 single compo·
nent 8·bit microcomputer.
The EM2 emulator board consists of an Intell!> 8022 emulator chip and an Intell!> 8755A, providing the EM2 emulator
board with a 2K x 8 EPROM program memory which can be programmed and erased repeatedly during hardware and
software development.
The 8022E emulator chip is a modified version of the 8022 intended for use in design support systems. Instead of
using resident ROM memory as the 8022, the 8022E uses an external 2K EPROM 8755A memory for program storage,
allowing easy program modification.
·See Intell!! 8022 Data Sheet.
1()"20
AFN-ooaooA-ol
EM2
EM2 BLOCK DIAGRAM
40·PIN SOCKET CONFIGURATION
P28
Vee
P27
P25
P24
AVec
PROD
VAREF
P23
ANI
ANO
P22
AVss
P21
TO
P20
VTH
P17
POO
P18
POI
P15
P02
P14
P03
P13
P04
P12
P05
Pll
P08
Pl0
P07
RESET
ALE
XTAL2
Tl
XTALI
Vss
SUBST
o
.----r-l
4(J.PIN
SOCKET
8755A
8022 EMULATOR CHIP
o PIN 1
SQUARE SOLDER PAD
PIN DESCRIPTION
Deslg·
nation
Pin II
Deslg·
nation
Function
Vss
20
Circuit GND potential.
Vcc
40
+ 5V circuit power supply.
PROG
37
Output strobe for Intell!> 8243 I/O expander.
POO-P07 10-17 8·bit open-drain port with comparator
Port 0
Inputs. The switching threshold is set
externally by VTH . Optional pull-up reo
slstors may be added via ROM mask
selection. (The emulator board has
switch selection of this option.)
VTH
9
2048
EPROM
MEMORY
Pin II
Function
RESET
24
Input used to Initialize the processor
by clearing status flip-flops and setting
the program counter to zero.
AVss
7
A/D converter GND potential. Also
establishes the lower limit of the conversion range.
AVcc
3
AID
SUBST
21
Substrate pin used with a bypass capacitor to stabilize the substrate voltage
and improve AID accuracy.
VAREF
4
AID converter reference voltage. Establishes the upper limit of the conversion
range.
ANO,
AN1
6,5
Analog inputs to AID converter. Software selectable on-chip via SEL ANO
and SEL AN1 instructions.
ALE
18
Address Latch Enable. Signal occurring once every 30 input input clocks
(once every single cycle instruction),
used as an output clock.
XTAL1
22
One side of crystal, inductor, or resistor input for internal oscillator. Also
Input for external frequency source.
(Not TTL compatible.)
XTAL2
23
Other side of timing control element.
This pin Is not connected when an external frequency source is used.
+ 5V power supply.
Port 0 threshold reference pin.
P10-P17 25-32 8-bit quasi·bidirectlonal port.
Port 1
P20-P27 33-36 8-bit quasi-bidirectional port.
Port 2
TO
T1
38-39 P20-P23 also serve as a 4-bit I/O ex1-2 pander for Intell!> 8243.
8
19
Interrupt input and input pin testable
using the conditional transfer Instructions JTO and JNTO. Initiates an interrupt following a low level input if interrupt is enabled. Interrupt Is disabled
after a reset.
Input pin testable using the JT1 and
JNT1 conditional transfer instructions.
Can be designated the timer/event
counter input using the STRT CNT instruction. Also serves as the zero-cross
detection input to allow zero-crossover
sensing of slowly moving AC Inputs.
Optional pull-up resistor may be added
via ROM mask selection.
10-21
AFN-OOBOOA-02
EM2
On the EM2 Board:
the Intel® 8755A EPROM can be programmed using any
o/the modules listed in Table 1.
Module
UPP-1P3
. PROMPT-48 .
PI'lOMPT-80/85
Description
Universal PROM Programmer.
Requires UPP-955, which includes 8755A Personality Card
with 40-pin adapter socket.
Intellec® MCS-48 Microcomputer Design Aid. Requires
PROMPT-475 Programming
Adapter.
Intellec® 8080/8085 Microcomputer Design Aid. Requires
PROMPT-975 Programming
Adapter.
Table 1_ 8755A Proramming Module
SPECIFICATIONS
Operating Environment
.Intef" 8755A EPROM Programming
UPp:103
"'ROMPT-48
PI'IOMPT-80/85
The 8755A EPROM is erased when exposed to light with
wavelengths shorter than approximately 4000 Angstroms (A). Sunlight and certain fluorescent lamps have
wavelengths in the 3000A to 4000A range. If the 8755A is
to be exposed to sunlight or room fluorescent lighting
for extended periods, then opaque labels should be
placed over the window to prevent unintentional
erasure.
The recommended erasure procedure is exposure to
ultraviolet light which has a wavelength of 2537 A. The
integrated dose (UV intensity multiplied by exposure
time) for erasure should be a minimum of 15W-sec/cm.
The erasure time with this dosage is approximately 15 to
20 minutes using an ultraviolet lamp with a 12,000"
W/em 2 power rating. Place the 8755A within one inch of
the lamp during erasure. Some lamps include a filter
which should be removed before erasure.
Physical Characteristics
Width: 2.75 in. (6.98 cm)
Height: 4.25 in. (10.79 cm)
Depth: 1.5 in. (3.81 cm)
Weight: 0.5 Ib (0.23 kg)
Electrical Characteristics
lntellec Microcomputer Development System
DC Power
Vcc=5V ±5%
Icc = 300 mA (maximum)
Software
8048 Assembler
ISIS-II Diskette Operating System
Environmental Characteristics
Equipment Supplied
Operating Temperature - 0 to 55°C
EM2 Printed Circuit Board
EM2 Reference Manual
Operating Humidity without condensation
Up to 95% relative humidity
ORDERING INFORMATION
Part Number
Description
MDS-EM2
8022 Emulation Board
10-22
AFN-00800A-03
intJ
3065 Bowers Avenue
Santa Clara, California 95051
Tel: (408) 987-8080
"TWX: 910·338-0026
TELEX: 34-8372
u.S. AND CANADIAN SALES OFFICES
September 1980
ALABAMA
FLORIDA (cont.)
MISSOURI
OREGON
Intel Corp.
Intel Corp.
5151 Adanson Street, Suite 203
Orlando 32804
Tel: (305) 628-2393
TWX: 810-853-9219
Intel Corp.
502 Earth City Plaza
Suite 121
Earth City 63045
Tel: (314) 291-1990
Intel Corp_
10700 S.W. Beaverton
Hillsdale Highway
Suite 324
Bea. . erton 97005
Tel: (503) 641-8086
TWX: 910-467·8741
303 Williams Avenue, S.W.
Suite 1422
Huntsville 35801
Tel: (205) 533·9353
ARIZONA
GEORGIA
Intel Corp.
10210 N. 25th Avenue, Suite 11
Phoenix 85021
Tel: (602) 997-9695
Intel Corp.
3300 Holcomb Bridge Rd.
Norcross 30092
BFA
4426 North Saddle Bag Trail
Scottsdale 85251
Tel: (602) 994-5400
CALIFORNIA
ILLINOIS
Intel Corp.*
2550 Golf Road, Suite 815
Rolling Meadows 60008
Tel: (312) 981-7200
TWX: 910-651-5881
Intel Corp.
7670 Opportunity Rd.
Suite 135
San Diego 92111
Tel: (714) 268-3563
Technical Representatives
1502 North Linde Street
Bloomington 61701
Tel: (309) 829-8080
Intel Corp."
2000 East 4th Street
Suite 100
Santa Ana 92705
Tel: (714) 835·9642
TWX: 910-595-1114
INDIANA
Intel Corp,5530 Corbin Avenue
Suite 120
Tarzana 91356
Tel. (213) 986·9510
TWX: 910-495-2045
Intel Corp,'
3375 Scott Blvd.
Santa Clara 95051
Tel: (408) 987·8086
TWX: 910-339·927~
910-338·0255
Earle Associates, Inc.
4617 Ruffner Street
Suite 202
San Diego 92111
Tel: (714) 278-5441
Mac-I
P.O. Box 1420
Cupertino 95014
Tel: (408) 257-9880
Mac-I
558 Valley Way
Calaveras Business Park
Milpitas 95035
Tel: (408) 946-8885
Mac-I
P.O. Box 8763
Fountain Valley 92708
Tel: (714) 839-3341
Mac-I
1321 Centinela Avenue
Suite 1
Santa Monica 90404
Tel: (213) 829-4797
Mac-I
20121 Ventura Blvd., Suite 240E
Woodland Hills 91364
Tel: (213) 347-5900
COLORADO
Intel Corp.
9101 Wesleyan Road
Suite 204
Indianapolis 46268
Tel: (317) 299-0623
IOWA
Technical Representatives, Inc.
St. Andrews Building
1930 St. Andrews Drive N.E.
Cedar Rapids 52405
Tel: (319) 393-5510
KANSAS
Intel Corp.
9393 W. 110th St., Ste. 265
Overland Park 66210
Tel: (913) 642-8080
Technical Representatives, Inc.
8245 Nieman Road, Suite 100
Lenexa 66214
Tel: (913) 888-0212, 3, & 4
TWX: 910-749-6412
Technical Representatives, Inc.
360 N. Rock Road
Suite 4
Wichita 67206
Tel: (316) 681-0242
MARYLAND
Intel Corp."
7257 Parkway Drive
Hanover 21076
Tel: (301) 796-7500
TWX: 710-862·1944
Mesa Inc.
16021 Industrial Dr.
Gaithersburg 20760
Tel: (301) 948·4350
Intel Corp.
7401 Metro Blvd.
Suite 355
Edina 55435
Tel: (612) 835-6722
TWX: 910-576-2867
Intel Corp."
201 Penn Center Boulevard
Suite 301W
Pittsburgh 15235
Tel: (412) 823-4970
Q.E.D. Electronics
300 N. York Road
Hatboro 19040
Tel: (215) 674-9600
TEXAS
Intel Corp.'
2925 L.B.J. Freeway
Suite 175
Dallas 75234
Tel: (214) 241-9521
TWX: 910-860-5617
BFA Corporation
3705 Westerfield, N.E.
Albuquerque 87111
Tel: (505) 292-1212
TWX: 910-989-1157
NEW YORK
Intel Corp."
6420 Richmond Ave.
Suite 280
Houston 77057
Tel: (713) 784-3400
TWX: 910-881·2490
Intel Corp"
300 Motor Pkwy.
Hauppauge 11787
Tel: (516) 231-3300'
TWX: 510-227-6236
Industrial Digital Systems Corp.
5925· Sovereign
Suite 101
Houston 77036
Tel: (713) 988-9421
Intel Corp.
80 Washington SI.
Poughkeepsie 12601
Tel: (914) 473-2303
TWX: 510-248-0060
Inlel Corp.
313 E. Anderson Lane
Suite 314
Austin 78752
Tel: (512) 454-3628
Intel Corp."
2255 Lyell Avenue
Lower Floor East Suite
Rochester 14606
Tel: (716) 254-6120
TWX: 510-253-7391
Measurement Technology, Inc.
59 Northern Boulevard
Great Neck 11021
Tel: (516) 482-3500
NORTH CAROLINA
Intel Corp.
154 Huffman Mill Rd.
Burlington 27215
Tel: (919) 584-3631
MICHIGAN
MINNESOTA
Intel Corp.'
275 Commerce Or.
200 Office Center
Suite 300
Fort WaShington 19034
Tel: (215) 542-9444
TWX: 510-661·2077
BFA Corporation
1704 Moon N.E., Suite 7
Las Cruces 87112
Tel: (505) 523-0601
TWX: 910-983-0543
T-Squared
2 E. Main
Victor 14564
Tel: (716) 924-9101
TWX: 510·254-8542
Intel Corp.'
26500 Northwestern Hwy.
Suite 401
Southfield 48075
Tel: (313) 353-0920
TWX: 810-244-4915
PENNSYLVANIA
NEW MEXICO
Intel Corp. *
27 Industrial Ave.
Chelmsford 01824
Tel: (617) 667·8126
TWX: 710-343-6333
CONNECTICUT
Intel Corp.
1001 N.W. 62nd Street, Suite 406
Ft. Lauderdale 33309
Tel: (305) 771-0600
TWX: 51Q..956-9407
NEW JERSEY
Intel Corp.'
Raritan Plaza
2nd Floor
Raritan Center
Edison 08817
Tel: (201) 225-3000
TWX: 710-480-6238
MASSACHUSETTS
EMC Corp.
381 Elliot Street
Newton 02164
Tel: (617) 244-4740
TWX: 922531
FLORIDA
Technical Representatives, Inc.'
VSW Bldg. Suite 560
406 W. 31st Street
Kansas City 64111
Tel: (816) 756-3575
TWX: 910-771-0025
T-Squared
4054 Newcourt Avenue
Syracuse 13206
Tel: (315) 463-8592
TWX: 710-541-0554
Intel Corp. *
650 S. Cherry Street
Suite 720
Denver 80222
Tel: (303) 321-8086
TWX: 910-931-2289
Intel Corp.
Peacock Alley
36 Padanaram Road
Danbury 06810
Tel: (203) 792-8366
TWX: 710-456-1199
Technical Representatives, Inc."
502 Earth City Plaza
Suite 201
Earth City 63045
Tel: (314) 291-0001
OHIO
Intet Corp.'
6500 Poe Avenue
Dayton 45415
Tel: (513) 890-5350
TWX: 810-450-2528
Intel Corp.*
Chagrin-Brainard Bldg., No. 300
28001 Chagrin Blvd.
Cleveland 44122
Tel: (216) 464·2736
TWX: 810-427-9298
WASHINGTON
Intel Corp.
Suite 114, Bldg. 3
1603116th Ave. N.E.
Bellevue 98005
Tel: (206) 453-8086
TWX: 910-443-3002
WISCONSIN
Intel Corp.
150 S_ Sunnyslope Rd.
Brookfield 53005
Tel: (414) 784-9060
CANADA
Intel Semiconductor Corp."
Suite 233, Bell Mews
39 Highway 7, Bells Corners
Ottawa, Ontario K2H 8R2
Tel: (613) 829-9714
TELEX: 053-4115
Intel Semiconductor Corp.
50 Galaxy Blvd.
Unit 12
Rexdale, Ontario
M9W 4Y5
Tel: (416) 675-2105
TELEX: 06983574
Multilek, Inc. *
15 Grenfell Crescent
Ottawa, Ontario K2G OG3
Tel: (613) 226-2365
TELEX: 053-4585
Multilek, Inc.
Toronto
Tel: (416) 245-4622
Multilek, Inc.
Montreal
Tel: (514) 481·1350
• Field Application Location
inter
3065 Bowers Avenue
Santa Clara, California 95051
Tel: (408) 987-11080
TWX: 91().338·0026
TELEX: 34-8372
u.s. AND CANADIAN
DISTRIBUTORS
September 1980
ALABAMA
COLORADO (cont.)
INDIANA
MISSOURI
tHamllton/Avnet Electronics
Wyle Distribution Group
451 E. 124th Avenue
Thornton 80241
Tel: (303) 457·WYLE
TWX: 910·931·0510
tHamllton/Avnet Electronics
485 Gradle Drive
Carmel 46032
Tel: (317) 844·9333
tHamllto~/Avnet Electronics
13743 Shoreline Ct.
Earth City, 63045
Tel: (314) 344·1200
TWX: 91()'762-O608
4812 Commercial Drive N.W.
Huntsville 35805
Tel: (205) 837·7210
tPloneer/Huntsvllle
1207 Putman Drive NW
Huntsville 35605
Tel: (205) 837·9033
TWX: 810·726·2197
ARIZONA
tHamllton/Avnst Electronics
s. 21st Street
Phoenix 85034
Tel: (602) 275·7851
261~
tWyle Distribution Group
8155 N. 24th Avenue
Phoenix 85021
Tel: (602) 995·9165
TWX: 91()'951-4282
CALIFORNIA
Arrow Electronics, Inc.
9511 Ridge Haven Court
Ser! Diego 92123
Tel: (714) 56!5-48oo
Arrow Electronics, Inc.
720 Palomar Avenue
Sunnyvale, California 94086
Tel: (408) 739·3011
TWX: 91().339·9371
tAvnet Electronics
350 McCormick Avenue
Costa Mesa 92626
Tel: (714) 754-6051
TWX: 91()'59!5-1926
Hamllton/Avnet Electronics
1175 Bordeaux Dr.
Sunnyvale 94086
Tel: (408) 743·3300
TWX: 910-339·9332
tHamllton/Avnet Electronics
8917 Complex Drive
San Diego 92123
Tel: (714) 571-7923
TWX: 910·335·1218
CONNECTICUT
t Arrow Electronics
12 Beaumont Road
Wallingford 08512
Tel: (203) 285·7741
TWX: 710-476-0162
tHamllton/Avnet Electronics
Commerce Industrial Park
Commerce Drive
Danbury 08810
Tel: (203) 797·2800
TWX: 71().456-9974
tHarvey ElectroniCS
112 Main Street
Norwalk 06851
Tel: (203) 853-1515
TWX: 71().468·3373
TWX: 71()'393-8770
FLORIDA
tArrow Electronics
1001 N.W. 62nd Street
Suite 108
Ft. lauderdale 33309
Tel: (305) 776-7790
TWX: 510·955·9458
tArrow ElectroniCS
115 Palm Bay Road, NW
Suite 10, Bldg. 200
Palm Bay 32905
Tel: (305) 725·1480
TWX: 51().959-8337
t Hamilton Electro Sales
3170 Pullman Street
Costa Me.a 92626
Tel: (714) 641-4100
TWX: 910·595·2638
tWyle Distribution Group
124 Maryland Street
EI Segundo 90245
Tel: (213) 322·3826
TWX: 910-348-7140 or 7111
tWyle Distribution Group
9525 Chesapeake Dr.
San Diego 92123
Tel: (714) 565·9171
TWX: 910-335·1590
tWyle Distribution Group
3000 Bowers Avenue
Santa Clara 95052
Tel: (408) 727·2500
TWX: 910·338-0451 or 0298
Wyle Distribution Group
17872 Cowan Avenue
Irvine 92714
Tel: (714) 641·1611
COLORADO
tWyle Distribution Group
6777 E. 50th Avenue
Commerce City 80022
Tel: (303) 287·9811
TWX: 91()'931·0510
tHamliton/Avnet Electronics
8785 E. Orchard Road
Suite 708
Englewood 80111
Tel: (303) 534·t212
TWX: 91()'931·0510
KANSAS
tHamlltonfAvnet ElectroniCS
9219 Quivira Road
Overland Park 66215
Tel: (913) 888·8900
tComponent Specialties, Inc.
8369 Nieman Road
Lenexa 66214
Tel: (913) 492·3555
MARYLAND
Arrow Electronics, Inc.
4801 Benson Avenue
Baltimore 21227
Tal: (301,247·S200
MASSACHUSETTS
tPloneeriOrlando
6220 S. Orange Blossom Trail
Suite 412
Orlando 32809
Tel: (305) 859·3600
TWX: 81().85().0177
Harvey/Boston
44 Hartwell Ave.
Lexington 02173
Tel: (617) 861·9200
TWX: 710·326·6617
Arrow Electronics
492 Lunt Avenue
P.O. Box 94248
Schaumburg 60172
Tel: (312) 893·9420
TWX: 910·222·1607
tHamiltonfAvnet Electronics
3901 No. 25th Avenue
Schiller Park 60176
Tel: (312) 678·6310
TWX: 910·227.()()60
Pioneer/Chicago
1551 Carmen Drive
Elk Grove 60007
Tel: (312) 437·9860
TWX: 910·222·1834
HamlltonfAvnet ElectroniCS
10 Industrial Road
Fairfield 07006
Tel: (201) 575·3390
TWX: 710·734·4438
NEW MEXICO
tAlilance Electronics Inc.
11030 Cochiti S.E.
Albuquerque 67123
Tel: (505) 292·3360
TWX: 91()'989·1151
tHamiltonfAvnet Electronics
2524 Baylor Drive, S.E.
Albuquerque 87119
Tel: (505) 765·1500
NEW YORK
·MICHIGAN
ILLINOIS
t Arrow Electronics
285 Midland Avenue
Saddle Brook 07662
Tel: (201) 797·5800
TWX: 71()'998·2206
tHarvey Electronics
45 Route 46
Pinebrook 07058
Tel: (201) 227·1282
TWX: 71().734-4382
tArrow Electronics
960 Commerce Way
Woburn 01601
Tel: (617) 933·8130
TWX: 71()'393·6770
tHamiltonfAvnet Electronics
6700 1-85 Access Road, No. 11
Suite 1E
Norcross 30071
Tel: (404) 448·0800
NEW JERSEY
tArrow ElectroniCS
Pleasant VaHey Avenue
Moorestown 08057
Tel: (215) 928·1600
TWX: 710·897·0829
tPioneer/Washington
9100 Gaither Road
Gaithersburg 20760
Tel: (301) 948·0710
TWX: 710·828'()545
Hamllton/Avnet Electronics
3197 Tech. Drive North
St. Petersburg 33702
Tel: (813) 578·3930
TWX: 810·863-0374
Arrow Electronics
2979 Pacific Drive
Norcross 30071
Tel: (404) 449-8252
TWX: 810·757·4213
tArrow Electronics
1 Perimeter Drive
Manchester 03103
Tel: (603) 868·6968
TWX: 710·220·1564
tHamiitoniAvnel Eiectronics
1 Keystone Ave.
Bldg. 36
Cherry Hili 08003
Tel: (609) 424·0100
TWX: 710-897·1405
tHamilton/Avnet Electronics
50 Tower Office Park
Woburn 01601
Tel: (617) 273·7500
TWX: 710·393-0382
GEORGIA
NEW HAMPSHIRE
tHamiiton/Avnet Electronics
7235 Standard Drive
Hanover 21076
Tel: (301) 796·5684
TWX: 71()'862·1881
tHamliton/Avnet Electronics
6800 Northwest 20th Ave.
Ft. Lauderdale 33309
Tel: (305) 971·2900
TWX: 51()'955-3097
tHamliton/Avnet Electronics
10912 W. Washington Blvd.
Culver City 90230
Tel: (213) 558·2193
TWX: 910·340-6364 or 7073
Pioneer/Indiana
6408 Castleplace Drive
Indianapolis 46250
Tel: (317) 649·7300
TWX: 810·260·1794
tArrow Electronics
3000 South Winton Road
Rochester 14623
Tel: (716) 275·0300
TWX: 510·253·4766
tArrow ElectroniCS
3810 Varsity Drive
Ann Arbor 48104
Tel: (313) 971·8220
TWX: 810·223-6020
tArrow Electronics
7705 Maltlage Drive
Liverpool 13068
Tel: (315) 652·1000
TWX: 710·545-0230
tPloneer/Michigan
13485 Stamford
Livonia 48150
Tel: (313) 525·1800
TWX: 810·242·3271
tHamilton/Avnet ElectroniCS
32487 Schoolcraft Road
Livonia 48150
Tel: (313) 522-4700
TWX: 810·242-8775
MINNESOTA
t Arrow Electronics
5230 W. 73rd Street
Edina 55435
Tel: (612) 830-1800
TWX: 910·756·2726
tlndustrial Components
5229 Edina Industrial Blvd.
Minneapolis 55435
Tel: (612) 831·2885
TWX: 910·756-3153
tHamllton/Avnet Electronics
7449 Cahill Road
Edina 55435
Tel: (612) 941·3801
TWX: 910·576·2720
Arrow Electronics
20 Oser Avenue
Hauppauge 11787
Tel: (516)231·1000
TWX: 51().227-6623
tHamilton/Avnet Electronics
333 Metro Park
Rochester 14623
Tel: (716) 475·9130
TWX: 51().253·5470
tHamiltonlAvnet Electronics
16 Corporate Circle
E. Syracuse 13057
Tel: (315) 437·2641
tHamiltonlAvnet ElectroniCS
5 Hub Drive
Melville, Long Island 11746
Tel: (516) 454·6000
TWX: 51().252-O893
tMicrocomputer System Technical Demonstrator Centers
intJ
3065 Bowers Avenue
Santa Clara, California 95051
Tel: (408) 987-8080
lWX: 910-338-0028
TELEX: 34-8372
NEW YORK (contJ
Harvey Electronics
P.O. Box 1208
u.s. AND CANADIAN DISTRIBUTORS
Saptamber 1980
PENNSYLVANIA
WASHINGTON (cant.)
QUEBEC
tArrow ElectronicS
4297 Greenlburg Pike
tWyle Dlltrlbutlon Group
1750 132nd Avenue NE
Bellevue 98006
Tel: (208) 453-8300
lWX: 91(1.443.2526
tHlmliton/Avnet Eleotronlcl
2870 Sabourin Stre.t
St. Laurent H4S 1M2
Tel: (514) 331-8443
lWX: 610-421-3731
Blnghampton 13902
Sult83114
Tel: (80n 748-82t 1
lWX: 510.252.0893
tHarvey Electronics
60 Crossways Park WIst
Woodbury 11797
Tel: (518) 921·8700
lWX: 510·221-2184
Harvey/Rocheetar
Pittsburgh 15221
Tel: (412) 351-4000
Pioneer/Pittsburgh
259 Kappa Drive
Plttlburgh 15238
Tel: (412) 782·2300
TWX: 710.795-3122
Pioneer/Delaware Valley
UO Fairport Park
281 Gibraltar Road
Fairport 14450
Tel: (718) 381-7070
TWX: 510.253-7001
Horaham 19044
Tel: (215) 674-4000
lWX: 510-885-8718
NORTH CAROLINA
Arrow Electronic.
938 Burke Street
Wlnston·Salam 27102
Tel: (919) 725-8711
lWX: 51MI22-4785
TEXAS
Arrow Electronics
13715 Gamma Road
Dallal 75234
Tel: (214) 388-7500
TWX: 91Q.66105495
PloneeriCarollna
Arrow Electronics, Inc.
10700 Corporate Drive, Suite 100
Stafford 71471
Tel: (713) 491-4100
108 Industrial Ave.
Greensboro 27406
Tel: (919) 273-4441
lWX: 51Q.925-1114
tHamllton/Avnel Electronics
2803 Industrial Drive
Raleigh 27809
Tol: (919) 829-8030
OHIO
Arrow Electronics
7820 McEwen Road
Centorville 45459
Tel: (513) 435-5583
lWX: 810.459·1811
Arrow Electronics
Component Specialties Inc.
8222 Jamestown Drive
Suite 115
AuoUn 78758
Tol: (512) 637·8922
lWX: 910.674·1320
tComponent Splelaltle., Inc.
10807 Shady Trail, Suite 101
Dallal 75220
Tel: (214) 357-8511
lWX: 910-881-4999
tComponent Specialties, Inc.
8585 Commerce Park Drive, lulte 590
8238 Cochran Rd.
Houston 77038
Solon 44139
Tel: (216) 248-3990
lWX: 810·427-9409
Arrow Electronics
10 Knollerslt Dr.
Cincinnati 45237
Tel: (513) 761·5432
TWX: 81Q.481·2870
Tel: (713) 771-7237
TWX: 91Q.981·2422
Hamllton/Avnet Electronics
2401 Rulland
AUltln 78758
Tel: (612) 837·8911
tHamliton/Avnet Electronics
954 Senate Drive
Dayton 45459
Tel: (513) 433.Q610
lWX: 910.340·2531
tHamliton/Avnll Electronics
4588 Emery Indultrl_1 Parkway
Warrensville Helghtl 44128
Tel: (216) 831·3500
lWX: 610·427-9452
tPloneer/Daylon
1900 Troy Sireet
Dayton 454().i
Tel: (513) 236-9900
TWX: 810.458-1622
tPloneer/Cleveland
4800 E. 1310t Street
Cloveland 44105
Tel: (216) 587·3500
lWX: 810·422·2210
OKLAHOMA
tComponents SpeCialties, Inc.
7920 E. 40th Street
TulIa 74145
Tel: (918) 684-2820
lWX: 910-845·2215
OREGON
tAlmaclStroum Electronics
8022 S.W. Nimbus, Bldg. 7
Beaverton 97005
Tol: (503) 641-9070
tHamllton/Avnet Electronics
8024 SW Jean Rd.
Bldg. C, Suite 10
Lake Oswego 97034
Tel: (503) 835-7848
tHamilton/Avnet ElectroniCS
2111 W. Walnut Hili Lane
Irving 78062
Tel: (214) 661-4111
TWX: 910·880-&371
tHamllton/Avnet Electronics
3939 Ann Arbor Drive
Houston 17083
Tel: (713) 780·1711
UTAH
tHamllton/Avnet ElectroniCS
1585 We.t 2100 South
Salt Lake City 841.19
Tel: (601) 972·2800
WASHINGTON
tAlmacJStroum ElectroniCS
5811 Sixth Ave. South
Se.ttle 89108
Tel: (208) 763-2300
TWX: 910·444·2087
Arrow Electronics, Inc,
Electronics Distribution Division
1058 Andover Park East
Tukwila 98189
Tel: (208) 575.Q907
tHamllton/Avnet ElectronlCB
14212 N.E. 21st Street
Bellevue 88005
Tel: (208) 453-5844
WI8CONSIN
tArrow Electronics
430 W, Rawlon AvenUI
Oak Creek 53154
T.I: (414) 764-eeoo
TWX: 91Q.338.Q028
Zantronlo.
5010 Plre Stre.t
Montrell H4P 1P3
Tel: (614) 735-8381
lWX: 05-827·535
tHamlltonJAvnlt ElectronlCI
2975 Moorland Road
New Berlin 83151
Tel: (414) 764-4510
lWX: 910·282·1162
CA~ADA
ALBERTA
tL.A. V.rah Ltd.
4742 14th Street N.E.
Calgary T2D 8L7
Tel: (403) 230·1235
lWX: 018-258-97
ZantroniC8
9224 27th Avenue
Edmonton ,'aN 1B2
Tel: (403) 483·3014
Zintronlc8
3851 210t N.E.
Calgary T2E 6T5
Tel: (403) 230·1422
BRITISH COLUMBIA
tL.A. V.rah Ltd.
2077 Alberta Strael
Vancouver V5V 1C4
Tel: (804) 873-3211
TWX: 61Q.929·1086
Zenironici
550 Comble St.
Vancouver VeB 2N7
Tol: (804) 889·2533
lWX: 04-5077-89
MANITOBA
L.A. Varah
1·1832 King Edward Street
Winnipeg R2R ON1
Tel: (204) 633-6190
TWX: 07·55-385
Zentronlcl
590 Berry St.
Winnipeg R3H OS1
Tel: (204) 775-8881
ONTARIO
tHamUton/Avnet Electronlos
3889 Rexwood Road, Unll. G & H
MIIsl••auga L4V 1M6
Tel: (416) 671·7432
TWX: 610.492_
tHamliton/Avnel Electronics
1735 Courtwood Cre808nt
Ott.wa K2C 3J2
rei: (613) 226·1700
lWX: 053-4971
tL.A. Varah, Ltd.
505 Kenora Avenue
Hamilton L8E 3P2
TIl: (416) 661-9311
TWX: 081·8349
tZentronl08
141 Catharine Street
Ottawa K2P 1C3
Tel: (613) 238-8411
TWX: 083-3636
tZlntronlol
1355 Meveralde Drive
Mlllleeluga, OntariO LOT 1C9
Tel: (416) 678-9000
Telex: 08-983-857
tMlcrocomputer System Technical eemonstrator Cantara
inter
3085 Bowers Avenue
Santa Clara, California 95051
Tol: (408)987-8080
TWX: 910·338-0026
INTERNATIONAL SALES AND MARKETING OFFICES
September 1980
TELEX: 34-6372
INTERNATIONAL DISTRIBUTORS/REPRESENTATIVES
ARGENTINA
FINLAND
JAPAN
SOUTH AFRICA
Micro Sistemas S,A
9 De Julio 561
Cordoba
Oy Finlronic AS
Melkonkalu 24 A
SF·002'0
Helsinki 21
Tel: 0·6926022
TELEX: 124 224 Flron SF
Asahl Electronics Co, Ltd.
KMM Bldg. Room 407
2·14·1 Asano. Kokura
Klta·Ku, KitokyuShu Cily 802
Tel: (093) 511·6471
TELEX: AECKY 7126·16
Electronic Building Elements
Pine Square
18th Street
Hazelwood. Pretoria 0001
Tel: 789221
TELEX: 30181SA
Tel: 54·51·32·880
TELEX: 51837 Blcea
AUSTRALIA
A.J.F. Systems & Components Ply, Ltd.
310 Queen Street
Melbourne
Victoria 3000
Tel:
TELEX:
Warburton Franki
Corporale Headquarters
372 Eastern Valley Way
Chatswood, New South Wales 2067
Tel: 407·3261
TELEX: AA 21299
AUSTRIA
Bacher Elektrontsche Geraele GmbH
Rolenmulgasse 26
A 1120 Vienna
Tel: 10222) 83 63 96
TELEX: 10')'532
Reklrsch Eleklronik Garaele GmbH
Lichtensteinstrasse 97
A1COO Vienna
Tel: \222) 347646
TELEX: 74759
FRANCE
Celdis SA'
53, Rue Charles Frerot
F·94250 Gentilly
Tel: (1) 581 0020
TELEX: 200 485
Feutrier
Rue des Trois Glorieuses
F·42270 SI. Priest·en·Jarez
Tel: (77) 74 67 33
TELEX: 3000 21
MetrologleO
La Tour d'Asnleres
4, Avenue Laurent Cely
92606·Asnieres
Tel: 791 44 44
TELEX: 611448
Tekelec Airtronlc'
Cite des Bruyeres
Rue Carle Vernet
F·92310 Sevres
Tel: (1) 534 75 35
TELEX: 204552
GERMANY
BELGIUM
Inalco Belgium SA
Ave. des Croix de Guerre 94
81120 Brussels
Tel: (02) 216 01 60
TELEX: 25441
BRAZIL
Icotron SA
0511·Av, Mutlnga3650
6 Andar
Pirltuba·Sao Paulo
Tel: 261·0211
TELEX: 1011) 222 ICO BA
CHILE
DIN
Av. Vic, Mc kenna 204
Casilla 6055
Santiago
Tel: 227564
TELEX: 3520003
CHINA
Electronic 2000 Vertriebs GmbH
Neumarkter Sirasse 75
0·8000 Munich 80
Tel: (089) 434061
TELEX: 522561
Jermyn GmbH
Postfach 1180
0·6077 Cam berg
Tel: (06434) 231
TELEX: 484426
Kontron Elektronik GmbH
Breslauerstrasse 2
8057 Echlng B
0·8000 Munich
Tel: (89) 319,011
TELEX: 522122
Neye Enatechnlk GmbH
Schillerstrasse 14
D·2085 Quickborn·Hamburg
Tel: 104'06) 6'2'
TELEX: 02,'3590
GREECE
C.M. Technologies
525 UniverSIty Avenue
Suite A·40
Palo Alto, CA 94301
American Technical Enterprises
P.O, Box 156
Athens
Tel: 30·1·8811271
30·1·8219470
COLOMBIA
HONG KONG
International Computer Machines
Carrera 7 No. 72·34
Apdo·Aereo 19403
Bogota 1
Tel: 211·7282
TELEX: 7'3'4INCO
Schmidt & Co.
281F Wing on Center
Conn aught Road
Hong Kong
Tel: 5·455·644
TELEX: 74766 Schmc Hx
CYPRUS
INDIA
Cyprus Eltrom Electronics
P,O. Box 5393
Nicosia
Tel: 21·27982
Mlcronic Devices
1041109C, Nlrmal Industrial Estate
Sian (E)
Bombay 400022, India
Tel: 486·170
TELEX: 011·5947 MDEV IN
DENMARK
STL·Lyngso Komponent AIS
Ostmarken 4
OK·2860 Soborg
Tel: 10') 67 00 77
TELEX: 22990
Scandinavian Semiconductor
Supply AIS
Nannasgade 18
OK·2200 Copenhagen
Tel: (01) 83 50 90
TELEX' 19037
ISRAEL
Eastronics Ltd.'
11 Rozanis Street
P.O, Box 39300
Tel Aviv 61390
Tel: 475151
TELEX: 33638
ITALY
Eledra 3S S,P.A,·
Vlale Elvezia, 18
120154 Milan
Tel: (02) 34.93.041·31.85.441
TELEX: 332332
Hamitton·Avnet Electronics Japan Ltd.
YU and YOU Bldg. 1·4 Horidome·Cho
Nihonbashi
Tel: (03) 662·991 I
TELEX: 2523774
Ayoyo Electric Corp.
Konwa Bldg.
1·12·22, Tsukiji, 1·Chome
Chuo·Ku, Tokyo 104
Tel: (03) 543·7711
Tokyo Electron Ltd.
No.1 Higashikata·Machi
M idori·Ku, Yokohama 226
Tel: (045) 471·8811
TELEX: 781·4473
KOREA
K0,aiT, Dig::a:
Room 909 Woonam Bldg.
7, '·KA Bongre·Dong
Chung·Ku Seoul
Tel: 23·8123
TELEX: K23542 HANSINT
Leewood International, Inc.
C.P.O. Box 4046
112-25, Sokong·Oong
Chung·Ku, Seoul 100
Tel: 28·5927
CABLE: "LEEWOOD" Seoul
MEXICO
Proveedora Electronlca, SA (Proesal
Prol. Moctezuma Ole. 24
Col. Romero de Terreros
Apdo. Postal 21-139
Mexico 21. D.F.
TELEX: 017·72402 SAuLME
NETHERLANDS
Inelco Nether. Camp. Sys. BV
Turfstekerstraat 63
Aalsmeer 14310
Tel: (2977) 28855
TELEX: 14693
Koning & Hartman
Koperwerf 30
2544 EN Den Haag
Tel: (70) 210.101
TELEX: 31528
NEW ZEALAND
W. K. McLean Ltd.
P.O. Box 18·065
Glenn Innes, Auckland, 6
Tel: 587·037
TELEX: NZ2763 KOSFY
NORWAY
Nordlsk Elektronlk (Norge) AIS
Postoffice Box 122
Smedsvlngen 4
1364 Hvalstad
Tel: 02786210
TELEX: 17546
PORTUGAL
Ditram
Componentes E Electronica LDA
Av. Miguel Bombarda, 133
Lisboa 1
Tel: (19) 545313
TELEX: 14347 GESPIC
SINGAPORE
Genera! Engineers Associates
Blk 3, 1003·1008, 10th Floor
P.S.A. Multi·Storey Complex
Telok BlangahlPasir Panjang
Singapore 5
Tel: 271·3163
TELEX: AS23987 GENERCO
SPAIN
Interface SA
Ronda San Pedro 22, 3 0
Barcelona 10
Tel: 301 7851
TWX: 51508
ITT SESA
Miguel Angel 16
Madrid 10
Tel: (1l4190957
TELEX: 27707127461
SWEDEN
AB Gosta Backstrom
Box 12009
10221 Stockholm
Tel: (08) 541 080
TELEX: 10135
Nordisk Electronlk AB
Box 27301
S-10254 Stockholm
Tel: (08) 635040
TELEX: 10547
SWITZERLAND
Induslrade AG
Gemsenstrasse 2
Postcheck 80 . 21190
CH·8021 ZUrich
Tel: (01) 60 22 30
TELEX: 56788
TAIWAN
Taiwan Automation Co.'
3d Floor #75, Section 4
Nanking East Road
Talpel
Tel: 771·0940
TELEX: 11942 TAIAUTO
TURKEY
Turkelek Electronics
Apapurk Boulevard 169
Ankara
Tel: 189483
UNITED KINGDOM
Comway Microsystems Ltd.
Market Street
68·Bracknell, BerkshIre
Tel: (344) 51654
TELEX: 847201
G.E.C. Semiconductors Ltd.
East Lane
North Wembley
Middlesex HA9 7PP
Tel: (01)904·9303/908·4111
TELEX: 28817
Jermyn industries
Vestry Estate
Sevenoaks, Kent
Tel: (0732) 501.44
TELEX: 95142
Rapid Recall, Ltd.
6 Soho Mills Ind. Park
Wooburn Green
Bucks, England
Tel: (6285) 24961
TELEX: 849439
Sintrom Electronics Ltd:
Arkwright Road 2
Reading, Berkshire RG2 OLS
Tel: (0734) 85464
TELEX: 847395
VENEZUELA
Componentes y Clrcuitos
Eleclronicos TTlCA C.A.
Apartado 3223
Caracas 101
Tel: 718·100
TELEX: 21795 TElETIPOS
• Field Appllcatton locatton
inter
3065 Bowers Avenue
Santa Clara, California 95051
Tel: (408) 98N!080
"TWX: 910·338·0026
TELEX: 34-6372
INTERNATIONAL SALES AND MARKETING OFFICES
September 1980
INTEL$ MARKETING OFFICES
AUSTRALIA
GERMANY
ITALY
SWEDEN
Intel Semiconductor Ply., Ltd.
Intel Semiconductor GmbH·
Suite 2, Level 15, North Point
100 Miller Street
North Sydney, NSW, 2060
Tel: 450-847
TELEX: AA 20097
Seldlstrasse 27
8000 M uenchen 2
Tel: (089) 53 691
TELEX: 523 177
Intel Corporation Italla, S.p.A.
Corso Semplone 39
1·20145 Milano
Tel: 2134.93267
TELEX: 311271
Intel Sweden A.e."
Box 20092
Alpvagen 17
$·16120 Bromma
Tel: (08) 96 53 90
TELEX: 12261
BELGIUM
Intel Corporation S.A.
Rue du Moulin a Papler 51
Bolte 1
8·1160 Brussels
Tel: (02) 660 30 10
TELEX: 24814
DENMARK
Intel Denmark AlS·
Lyngbyvej 32 2nd Floor
DK·21oo Copenhagen East
Tel: (01) 182000
TELEX: 195e7
FINLAND
Intel Finland OY
Sentnerlkuja 3
SF • 00400 Helsinki 40
Tel: (0) 558531
TELEX: 123332
FRANCE
Intel Corporation, S.A.R.L.·
5 Place de 18 Balance
Sllie 223
94528 Rungis Cedex
Tel: (01) 687 22 21
TELEX: 270475
lritel Semiconductor GmbH
Mainzer Strasse 75
6200 Wiesbaden 1
Tel: (06121) 700874
TELEX; 04186183
Intel Semiconductor GmbH
Wernerstrasse 67
P.O. Box 1460
7012 Fellbach
Tel: (0711) 580082
TELEX: 7254626
Intel Semiconductor GmbH
Hohenzollern Strasse 5
3000 Hannover 1
Tel: (0511) 327081
TELEX: 923625
Intel Semiconductor GmbH
Oberrathstrasse 2
4000 Duesseldorf 30
Tel: (0211) 651054·6
TELEX: 8586977
HONG KONG
Intel Semiconductor Ltd.
99·105 Des Voeux Rd., Central
16F, Unit B
Hong Kong
Tel: 5·450·847
TELEX: 63869
JAPAN
Intel Japan K.K. *
Flower Hitl·Shlnmachi East Bldg.
1·23·9, Shinmachl, Setagaya·ku
Tokyo 154
Tel: (03) 426·9261
TELEX: 781·28426
SWITZERLAND
Intel Semiconductor A.G.
Forchstrasse 95
CH 8032 Zurich
Tel: 1·554502
TELEX: 55789 ich ch
NETHERLANDS
UNITED KINGDOM
Intel Semiconductor B.V.
Cometongebouw
Westblaak 106
3012 Km Rotterdam
Tel: (10) 149122
TELEX: 22283
Intel Corporation (U.K.) Ltd. *
5 Hospital Street
Nantwich, Cheshire CW5 5RE
Tel: (0270) 62 65 60
TELEX: 36620
NORWAY
Intel Norway AIS
FI.O. Box 92
Hvamveien 4
N·2013
Skjetten
Tel: (2) 742 420
TELEX: 18018
Intel Corporation (U.K.) Ltd.
Dorcan House
Eldlne Drive
Swlndon, Wiltshire SN3 3TU
Tel: (0793) 26101
TELEX: 444447 INT SWN
ISRAEL
Intel Semiconductor Ltd.·
FI.O. Box 2404
Haifa
Tol: 9721452 4261
TELEX: 92246511
.. Field Application Location
inter
3065 Bowers Avenue
Santa Clara, California 95051
Tel: (408)987-8080
TWX: 91().338'()()26
TELEX: 34-6372
u.s. AND CANADIAN SERVICE OFFICES
September 1980
CALIFORNIA
MASSACHUSETIS
TEXAS
Intel Corp.
1601 Old Bayshore Hwy.
Suite 345
Burlingame 94010
Tel: (415)892-4782
TWX: 910·375-3310
Intel Corp.
27 Industrial Avenue
Chelmsford 01824
Tel: (617) 667-8126
TWX: 710·343·6333
Intel Corp.
313 E. Anderson Lane
Suite 314
Austin 78752
MICHIGAN
Intel Corp.
2000 E. 4th Street
Suite 100
Santa Ana 92705
Tel: (714)835-9842
TWX: 91()'595·1114
Intel Corp.
26500 Northwestern Hwy.
Suite 401
Southfield 48075
Intel Corp.
7670 Opportunity Road
San Diego 92111
Tel: (714)268·3563
MINNESOTA
Intel Corp.
3375 Scott Blvd.
Santa Clara 95051
Tel: (408)987-8086
Intel Corp.
5630 Corbin Avenue
Sulle 120
Tarzana 91356
Tel: (213)98,6-9510
COLORADO
Intel Corp.
650 South Cherry
Suite 720
. Denver, 80222
Tel: (303)321-8086
TWX: 91()'931·2289
FLORIDA
Intel Corp.
1001 N.W. 62nd Street
Suite 406
Ft. Lauderdale 33309
Tel: (305)77Hl600
TWX: 51().956·9407
ILLINOIS
Intel Corp.
2550 Golf Road
Suite 815
Roiling Meadows 60008
Tel: (312)981-7230
TWX: 910·253-1825 '
KANSAS
Intel Corp.
9393 W. 110th Street
Suite 265
Overland Park 66210
Tel: (913)642-8080
MARYLAND
Intel Corp.
7257 Parkway Drive
Hanover 21076
Tel: (301) 79t1-7500
TWX: 710-862·1944
Tel: (313)353.()92O
TWX: 81()'244-4915
Intel Corp.
7401 Metro Blvd.
Suite 355
Edina 55435
Tel: (612)835-6722
TWX: 91 ()'576·2867
Tel: (512)454-3628
TWX: 91()'874·1347
Intel Corp.
2925 L.B.J. Freeway
Suite 175
Dallas 75234
Tel: (214)241·2820
TWX: 91()'860·5617
Intel Corp.
6420 Richmond Avenue
Suite 280
Houston 77057
Tel: (713)784·1300
TWX: 910·881·2490
VIRGINIA
Intel Corp.
502 Earth City Plaza
Suite 121
Intel Corp.
7700 Leesburg Pike
Suite 412
Falls Church 22043
Tel: (703) 734-9707
TWX: 710·931·0625
Earth City 63045
Tel: (314)291,1990
WASHINGTON
MISSOURI
NEW JERSEY
Intel Corp.
2450 Lemoine Avenue
FI. Lee 07024
Tel: (201)947·6267
TWX: 71().991·6593
Intel Corp.
1603 116th Ave. N.E.
Suite 114
Bellevue 98005
Tel: (206)232·7823
TWX: 910-443-3002
WISCONSIN
OHIO
Intel Corp.
Chagrin-Brainard Bldg. #210
28001 Chagrin Blvd.
Cleveland 44122
Intel Corp.
150 S. Sunnyslope Road
Suite 148
Brookfield 53005
Tel: (414) 784·9060
Tel: (216)464·2736
TWX: 81().427·9298
CANADA
Intel Corp.
6500 Poe Avenue
Dayton 45414
Tel: (513)690-5350
TWX: 810·450·2528
Intel Corp.
50 Galaxy Blvd.
Unit 12
Rexdale, Ontario
M9W4Y5
Tel: (416)675·2105
OREGON
Telex: 069-83574
Intel Corp.
10700 S.W. Beaverton-Hillsdale Hwy.
Intel Corp.
39 Hwy. 7, Bells Corners
Ottawa, Ontario
Bldg, 2, Suite 324
Beaverton 97005
Tel: (503)641-8086
TWX: 910·467-8741
K2H 8R2
Tel: (613)829·9714
Telex: 053-4115
PENNSYLVANIA
Intel Corp.
275 Commerce Drive
200 Office Center
Suite 300
Fort Washington 19034
Tel: (215)542·9444
TWX: 510-651·2077
*Fleld Application Location
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