1980_Mostek_Micro_Systems_Data_Book 1980 Mostek Micro Systems Data Book

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1980
Micro Systems
Data Book

Copyright © 1980 Mostek Corporation (All rights reserved)
Trade Marks Registered ®
Mostek reserves the right to make changes in specifications at any time and without notice. The information furnished by
Mostek in this publication is believed to be accurate and reliable. However, no responsibility is assumed by Mostek for its use;
nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted under any
patents or patent rights of Mostek.
The "PRELIMINARY" designation on a Mostek data sheet indicates that the product is not characterized. The specifications
are subject to change, are based on design goals or preli'minary part evaluation, and are not guaranteed. Mostek Corporation
or an authorized sales representative should be consulted for current information before using this product. No responsibility
is assumed by Mostek for its use; norfor any infringements of patents and trademarks or other rights ofthird parties resulting
from its use. No license is granted under any patents, patent rights, or trademarks of Mostek. Mostek reserves the right to
make changes in specifications at any time and without notice.
PRINTED IN USA September 1980

MOSTEK 1980 MICRO SYSTEMS DATA BOOK

Table of Contents
General Information
STD-Z80 BUS
IV

MDX Series Data

Proc~ssing

MD Series'lnput/Output
MD Series Memory
.MD Series Special Functions
M D Series Accessories
MD Series Data Processing
SDE Series Data Processing

S
SO 'Series Memory
SDE Series Accessories

Development
.~.......,~~

Emulation Boards
Peripherals

MICRO SYSTEMS DATA BOOK

Table of Contents

TABLE OF CONTENTS'
I-

Table of Contents . ......... '" .................................................... '" I-i
Numerical Listing of Products by Part Number (MK #) ........................................ I-iii

II -

General Information
Mostek - Technology for Today and Tomorrow .............................................. II-i
U.S. and Canadian Sales Offices ......................................................... II-iii
U.S. and Canadian Representatives ...................................................... II-iv
U.S. and Canadian Distributors ......................... : ................................. II-v
International Marketing Offices .......................................................... II-vii
International Sales Representatives/Distributors ........................................... II-vii

III -

STD-ZaO Bus
STD-Z80 Bus Systems ................................................................. 111-1

IV -

MDX Series Data Processing
MDX-CPU1 ...............................................•........................... IV-1
MDX-CPU2 ........................................................................... IV-5
MDX-Math ........................................................................... IV-9

V -

MD Series Input/Output
MDX Series System Interrupt Units (SIU) Table ............................................ V-1
MDX-A/D8 ........................................................................... V-3
MDX-AIO ............................................................................ V-7
MDX-A/D12 ......................................................................... V-11
MDX-D/A8 .......................................................................... V-15
MDX-D/A12 ......................................................................... V-19
MDX-FLP ............................................................................ V-23
MDX-PIO ............................................................................ V-27
MDX-SIO ............................................................................ V-31

VI -

MD Series Memory
MDX-DRAM .......................................................................... VI-1
MDX-EPROM ......................................................................... VI-5
MDX-EPROM/UART ................................................................... VI-9
MDX-SRAM ......................................................................... VI-13
MDX-UMC .......................................................................... VI-17

VII - MD Series Special Functions
MDX Series System Interrupt Units (SIU) Table ........................................... VII-1
MDX-DEBUG ........................................................................ VII-3
MDX-INT ........................................................................... VII-11
MDX-SC/D ......................................................................... VII-15
MDX-SST .......................................................................... VII-19

VIII - M D Series Accessories
MD-ACC ............................................................................ \/111-1
MD-PWR1 ........................................................................... VIII-7
MD-RMC12 ......................................................................... VIII-9
RMDFSS ........................................................................... VIII-13

IX -

M D Series Data Processing
MD-SBC1 ............................................................................ IX-1

X-

SDE Series Data Processing
OEM-80E ............................................................................ X-1

I-i

XI -

SDE Series Input/Output
AlD-SOE .........................•.......................•.. '.' .c•••••• ; . ·••••••.••••••••. XI-1
DCC-SOE ............................................................................. XI-5
FLP-SOE ......•...................................................... , ... '.; .. '.•..... , . XI-9

XII - .SDE Series Memory
RAM-SOE ............................................................................. XII-1

XIII - .SDE Series Accessories
SOE-ACC, ......................•..........•............................. '.' .......... XIII-1
SDE-RMC6 ..............................................•...•.......•............... XIII-5

XIV - Software Disk Based
FLP-SODOS •..........•...............................................•.............. XIV-1
MITE-SO/BIOS ............•..................•...........•............. ; ...........•..• XIV-5
ANSI BASIC Software Interpreter .......................................................... XIV-9
Mostek FORTRAN IV Compiler ......................................................•. XIV-13
MACRO-70 ...•.......................•.................................•.......... XIV-15
MACRO-SO ................•.............................................. ; ........ XIV-17
MEDEX-SO ...........................•..........................................•.. XIV-19
LlB-SO-VI ............................................. , ... '............................ XIV-23

XV - Development Systems
MATRIXTM-SO/SDS ..................................................................... XV-1
MATRIX-SO/SDT .......................•................................•........•... XV7 9
MDX-PROTO ........................................................................ XV-11

XVI - Systems Emulation Boards
AIM* -SOE ..•..........•...•................................. , ....................... XVI-1
Application Interface Module AIM*-ZSOAE •.............................................. XVI-5

XVII - Peripherals

,

CRT .•......................•........•...........•.......•...•..................... XVII-1
'Line Printer .......................•....................... ~ ................ "c' .', . . . . : . XVII-5
PPG S/16-PROM Programmer ......•..•............... , .......................... ',' ... XVIl-9
RMDFSS ........................................................................... XVII-13

I-ii

NUMERICAL LISTING OF PRODUCTS BY PART NUMBER (MK #)

PART #
MK77650-O
MK77650-4
MK77651-0
MK77651-4
MK77652-0
MK77654
MK77655-0
MK77665-O
MK77666-O
MK77669-O
MK77669-4
MK77750-O
MK77752-0
MK77752-4
MK77753-0
MK77753-4
MK77754-0
MK77754-4
MK77755
MK77756
MK77758
MK77759
MK77850-0
MK77850-4
MK77851-0
MK77852-0
MK77853-0
MK77853-4
MK77950-0
MK77950-4.
MK77951-0
MK77951-4
MK77952
MK77953
MK77955
MK77956
MK77957
MK77958
MK77959
MK77962
MK77963-O
MK77963-4
MK77964
MK77966
MK77967
MK77968

PAGE #

DESIGNATOR

MDX-PIO ...................................................................... V-27
MDX-PIO-4 .................................................................... V-27
MDX-SIO .............................................. .' ....................... V-31
MDX-SIO-4 ............ .' ....................................................... V-31
MDX-FLP ...................................................................... V-23
MDX-AIO ....................................................................... V-7
MDX-A/D12 ..................................... .' ............................. V-11
MDX-DI A 12 .................................................. ; ................ V-19
MDX-D/A8 •.•........•.••••.........• .' .......•..........•..•........••...•.... V-15
MDX-A/D8 ..................................................................... V-3
MDX-A/08-4 ..................................................... ; .............. V-3
MDX-DRAMB ................................................................... VI-1
MDX-DRAM32 .................................................................. VI-1
MDX-DRAM32-4 ................................................................ VI-1
MDX-EPROM/UART ............................................................. VI-9
. MDX-EPROM/UART-4 ........................................................... VI-9
MDX-DRAM16 .................................................................. VI-1
MDX-DRAM16-4 ................................................................. VI-1
MDX-SRAM4 ......................... .' .......................................... VI-13
MDX-SRAM8 ................................................................... VI-13
MDX-EPROM16 ............ .' .................................................... VI-5
MDX-UMC ................................................................. ; ... VI-17
MDX-CPU1 .................... .' ..................... .' ......... .' ................ IV-1
MDX-CPUl-4.' ................................................................... IV-1
MD-SBC1 ....................................................................... IX-.1
MDX-MATH ..................................................................... IV-9
MDX-CPU2 ........................................................... , .......... IV-5
MDX-CPU2-4 .................................................................... IV-5
MDX-DEBUG ................................................................... VII-3
MDX-DEBUG-4 ...................................... .' .......................... VII-3
MDX-PROTO .................................................................. XV-11
MDX-PROTO-4 .......................................................•........ XV-11
MDX-WW2 .' ................................................................... VIII-l
MD-EXT ...........................................................;............. VIII-l
MD-232DCE-C ................................................................... VIII-1
MD-TfY-C ........... .' ......................................................... VIII-1
MD-PPG-C ..................................................................... VIII-1
MDX-SST ..................................................................... VII-19
MDX-WW1 ......................................................... ; .......... VIII-1
FLP-80DOS (MD PROMs) ........................................................ XIV-l
MDX-SC/D .....................•.•........•......•......•.......•...•......• .' •. VII-15
MDX-SC/D-4 .......•.....•................•...........•....•......•.......•.. VII-15
MD-PWRl .........................•........................................... VIII-7
MD-RMC12 .................................................................... VIII-9
MDX-INT ...................................................................... VII-l1
MEDEX-80 ................................................................... XIV-19
. I-iii

MK77969
MK77970
MK77972
MK77973
MK77975
MK78106
MK78109
MK78110
MK78122
MK78124-3
MK78142
MK78146
MK78152
MK78157
MK78158
MK78164
MK78165
MK78172-42
MK78172-56
MK78175-40
MK78177-26
MK78181-1
MK78181-2.
MK78182-1
MK78182-2
MK78183
MK78185
MK78188
MK78189
MK78190-1
MK78190-2
MK78191-1
MK78191-2
MK78192
MK78197
MK79062
MK79081-1
MK79085
MK79088
MK79089
MK79090

MD-CC12 ...................................................................... VIII-1
MD232DTE-C .................................................................. VIII-1
MITE80/BIOS .................................................................. XIV-5
MD-CC6 .............................. , ..................................... ; .. VIII-1
MD-RMC12-50 ................................................................. VIII-9
AIM80E ....................................................................... XVI-1
RAM-80AE ..................................................................... XII-1
RAM-80BE ..................................................................... XII-1
OEM-80E/4 ..................................................................... X-1
OEM-80E/16 ................................................................... X-1
FLP-80DOS (SO PROMs) ......................................................... XIV-1
FLP-80E ........................................................................ XI-9
SDE-RMC 6 to CRT .............................................................. XIII-1
ANSI BASIC ................................................................•... XIV-9
Mostek FORTRAN IV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. XIV -1 3
Library ...................................................................... , XIV-23
MACR080 ................................................................... XIV-17
AlD-80E/1791 .................................................................. XI-1
A/D-80E/1791 .................................................................. XI-1
A/D-80E/1795 .................................................................. XI-1
A/D-80E/1798 .................................................................. XI-1
AIMZ80AE/16 .................................................................. XVI-5
AIMZ80AE/32 ..............................................•................... XVI-5
SD-RMC6 ...................................................................... XIII-3
SD-RMC6-50 ................................................................... XIII-3
RMDFSS ........................................................... VIII-13 and XVIl-13
RMDFSS-50 ........................................................ VIII-13 andXVII-13
MATRIX-80/SDS ............................................................... XV-1
MATRIX-80/SDS-50.................... , ........................................ XV-1
CRT .......................................................................... XVII-1
CRT-50 .... ,................................................................... XVII-1
LP .............. , ......... , ........................... , ...................... XVII-5
LP-50 ........................................................................ XVII-5
DCC-80E ........................................................................ XI-5
MATRIX-80/SDT ............................................................... XV-9
SDE-EXT ....................................................................... XIII-1
PPG-8/16 .................................................................... XVII-9
MACRO 70 ................................................................... XIV-15
RMS-DFE Cable 50 Pin ................................................ .x1l1-1 and XVII-7
MATRIX System or MDX-PIO To Cent CAB .......................................... VIII-1
MATRIX To PPG-8/16 CAB EXT .................................................. XVII-9

I-iv

MICRO SYSTEMS DATA BOOK

Mostek - Technology For Today And Tomorrow ,

TECHNOLOGY
From the beginning. Mostek has been
recognized as an innovator. In 1970. Mostek
developed the MK4006 1 K dynamic RAM
and the world's first single-chip calculator
circuit. the MK601 O. These technical breakthroughs proved the benefits of ionimplantation and cost-effectiveness of MOS.
Now. Mostek represents one of the industry's
most productive bases of MOS/LSI technology. Each innovation - in memories.
microcomputers and telecommunications adds to that technological capability.

duction capability has made us the world's
largest manufacturer of dynamic RAMs. In
1979 we shipped 25 million 4K and 16K
dynamic RAMs. We built our first telecommunication tone dialer in 1974; since then.
we've shipped over 5 million telecom circuits.
The MK3870 single-chip microprocessor is
also a large volume product with over two
million in application around the world. To
meet the demand for our products. production capability must be constantly increased.
To accomplish this. Mostek has been in a
constant process of expanding and refining
our production capabilities.

QUALITY

THE PRODUCTS

The worth of a Mostek product is measured
by its quality; how well it's designed. manufactured and tested; how well it works in your
system.
In design. production and testing. our goal
is meeting the spec every time. This goal
requires a strict discipline. both from the
company and from the individual. This discipline. coupled with a very personal pride. has
driven Mostek to build in quality at every level.
until every product we take to the market is as
well-engineered as can befound in the industry.

Telecommunications and Industrial Products
Mostek has made a solid commitment to
telecommunications with a new generation
of products. such as Integrated Pulse Dialers.
Tone Dialers. CODECs. monolithic filters.
tone receivers. A/D converters and counter
time-base circuits.
Since 1974 over five million telecom circuits have been shipped. making Mostek the
leading supplier of tone/pulse dialers and
CODECs.

Memory Products

PRODUCTION CAPABILITY

Through innovations in both circuit design.
wafer processing and production. Mostek

Mostek's commitment to increasing proII-i

has become the industry's leading supplier of
memory products.
An example of Mostek leadership is our
new BYTEWYDETM family of static RAMs,
ROMs, and EPROMs. All provide high performance, N words x 8-bit organization and
common pin configurations to allow easy
system upgrades in density and performance.
Another important product area is fast static
RAMs. With major advances in technology,
Mostek static RAMs nowfeature access times
as low as 55 nanoseconds. With high density
ROMs and PROMs, static RAMs, dynamic
RAMs and pseudostatic RAMs, Mostek now
offers one of industry's broadest and most
versatile memory families.

dual floppy-disk system that is used to develop and debug software and hardware for all
Mostek microcomputers.
Asoftware operating system. FLP-80DOS,
speeds and eases the design cycle with
powerful commands. BASIC and FORTRAN
are also available for use on the MATRIX.
Mostek's MD Series™ features both standalone microcomputer boards and expandable microcomputer boards. The expandable
boards are modularized by function. reducing system cost because the designer buys
only the specific functional modules his
system requires. All MDX boards are STDZ80 BUS compatible.
The STD-Z80 BUS is a multi-sourced
motherboard interconnect system designed
to handle any MDX card in any card slot.

Microcomputer Components

Mostek's microcomputer components are
designed for a wide range of applications.
Our Z80 family is the highest performance
8-bit microcomputer available today. The
MK3870 family is one of the industry's most
popular 8-bit single-chip microcomputers,
offering upgrade options in ROM, RAM, and
I/O, all in the same socket. The MK3874
EPROM version supports and prototypes the
entire family.

Memory Systems

Taking full advantage of our leadership in
memory components technology, Mostek
Memory Systems offers a broad line of products, all with the performance and reliability
to match our industry-standard circuits.
Mostek Memory Systems offers add-in memory boards for popular DEC and Data General
minicomputers.
Mostek also offers special purpose and
custom memory boards for special applications.

Microcomputer Systems

Supporting the entire component product
line is the powerful MATRIXTM microcom puter development system, a Z80-based,
II-ii

U.S. AND CANADIAN SALES OFFICES

CORPORATE HEADQUARTERS
Mostek Corporation
, 215 W. Crosby Rd.
P. O. Box 169
Carrollton, Texas 75006

REGIONAL OFFICES

Eastern U.S.lCanada
Mostek
34 W. Putnam. 2nd Floor
Greenwich, Conn. 06830

203/622-0955
TWX 710-579-2928
Northeast U.S.
Mostek
29 Cummings Park, Suite #426
Woburn. Mass. 01801

617/935-0635
TWX 710-348-0459

Mid-Atlantic U.S.

North Central U.S.

Southwest U.S.

Mostek
East Gate Business Center
125 Gaither Drive. Suite 0
Mt. Laurel, New JerseV 08054
6091235-4112
TWX 710-897·0723

Mostek
6125 Blue Circle Drive. Suite A

Mostek

Rocky Mountains
Mostek

4100 McEwen Road

8686 N. Central Ave.

Southeast U.S.

Mostek
3400 S. Dixie Ave.
SUite 101
Kettering. Ohio 45342

Mostek
Exchange Bank Bldg.
1111 N. Westshore Blvd.
Suite 414
Tampa. Flonda 33607

813/876-1304
TWX 810-876-4611
Central U.S.

Mostek
701 E. Irving Park Road
Suite 206
Roselle, III. 60172
312/529-3993

Minnetonka, Mn. 55343

612/935-4020
TWX 910-576-2802
South Central U.S.

Suite 237
Dallas, Texas 75234

214/386·9141
TWX 910·860·5437
Northern California
Mostek

Suite 126
Phoenix, Ariz. 85020

602/997·7573
TWX 910-957-4581

Northwest
Mostek

5131299·3405

1762 Technology Drive
Suite 126
San Jose, Calif. 95011

TWX 810-473-2976

408/287-5081

1107 North East 45th Street
Suite411
Seattle. Wa. 98105
206/632-0245

TWX 910-338-7338

TWX 910-444-4030

Michigan
Mostek
Livonia PaVillion East
29200 Vassar. Suite 520
Livonia, Mich. 48152
313/478·1470
TWX 810-242-2978

Southern California
Mostek
18004 Skypark Circle
Suite 140
Irvine, Calif. 92714

714/549-0397
TWX 910-595-2513

TWX 910-291-1207

II-iii

U.S. AND CANADIAN REPRESENTATIVES

ALABAMA
Beacon Elect. Assoc., Inc.
11309 S. Memorial Pkwy.
Suite G
Huntsville, AL 35803

205/881-5031
TWX 810-726-2136
ARIZONA
Summit Sales
7336 E. Shoeman Lane
Suite 116E
Scottsdale, AZ 85251

6021994·4587
TWX 910-950-1283
ARKANSAS
Beacon Elect. Assoc., Inc.

P.O. Box 5382, Brady Station
Little Rock. AK 72215

501/224·5449
TWX 910-722-7310
CALIFORNIA
Harvey King, Inc.
8124 Miramar Road
San Diego, CA 921 26

714/566-5252
TWX 910-335-1231
COLORAOO
Waugaman Associates
4800 Van Gordon
Wheat Ridge, CO 80033

303/423·1020
TWX 910-938·0750
CONNECTICUT
New England Technical Sales

240 Pomeroy Ave.
Meriden. CT 06450

203/237·8827
FLORIDA
Beacon Elect. Assoc .• Inc.

6842 N.W. 20th Ave.
Ft. Lauderdale, FL 33309

305/971·7320
TWX 510-955-9834
Beacon Elect. Assoc., Inc.
235 Maitland Ave.
P. O. Box 1278
Maitland, FL 32751
305/647-3498
TWX 810-853-5038

Beacon Elect. Assoc., Inc.
316 Laurie
Melbourne, FL 32935
3051259-0648
TWX 510-950-7251
Beacon Elect. Assoc., Inc.
2280 U.S. Hwy 19 North
Suite 163
Clearwater, FL 33515
813/725-4714
TWX 810-866~9739

GEORGIA
Beacon Elect. Assoc., Inc."
6135 Barfield Rd.
SUite 112
Atlanta, GA 30328
404/256-9640
TWX 810-751-3165
ILLINOIS
Carlson Electronic Sales·
600 East Higgins Road
Elk Grove Village. Il60007
312/956-8240
TWX 910-222-1819

INDIANA
Rich Electronic Marketing"
599 Industnal Drive
Carmel, IN 46032
317/844-8462
TWX 810-260-2631
Rich Electronic Marketing
3448 West Taylor St.
Fort Wayne, IN 46804.

219/432-5553
TWX 81 0-332~ 1404

IOWA
Cahill, Schmitz & Cahill, Inc.
208 Collins Rd. N.E. Suite K
Cedar Rapids, IA 52402
319/377-8219
TWX 910-525-1363
Carlson Electronic Sales
204 Collins Rd. N.E.
Cedar Rapids. IA 52402
319/377-6341

KANSAS
Rush & West Associates"
107 N. Chester Street
Olathe, KN 66061
913/764-2700
TWX 910-749-6404
KENTUCKY
Rich Electronic Marketing
5910 Bardstown Road
P. O. Box 91147
lOUisville, KY 40291
5021239-2747
TWX 810-535·3757

MARYLANO
Arbotek Associates
3600 St. Johns Lane
Ellicott City, MD 21043

301/461-1323
TWX 710-862-1874

MASSACHUSETTS
New England Technical Sales"
135 Cambridge Street
Burlington, MA 01803
617/272·0434
TWX 710-332-0435
MICHIGAN
APJ Associates, Inc.
9880 E. Grand River Ave.
Brighton. MI48116
313/229-6550
TWX 810-242-1510
MINNESOTA
Cahill, Schmitz & Cahill, Inc.
315 N. Pierce
St. PaUl, MN 55104
612/646-7217
TWX 910-563-3737
MISSOURI
Rush & West Associates
481 Melanie Meadows lane
BallWin, MO 63011
314/394-7271
NEW JERSEY
Tritek Sales, Inc.
21 E Euclid Ave.
Haddonfield. NJ 08033
609/429-1551
215/627-0149 (Philadelphia line)
TWX 710-896-0881

NEW MEXICO
Waugaman Associates
9004 Menaul N.E.
Suite 7
P. O. 80x 14894
Albuquerque, NM 87112
505/294-1437
NORTH CAROLINA
Beacon Elect. Assoc., Inc.
1207 West Bessemer Ave.
Suite 112
Greensboro, NC 27408
919/275-9997
TWX 510-925-1119
Beacon Elect. Assoc., Inc.
3901 Barrett Dr. 3rd Floor
Raleigh, NC 27611
919/787-0330
NEW YORK
ERA (Engrg. Rep. Assoc.)
One DuPont Street
Plainview, NY 11803
516/349-1190
TWX 510-221-1849
Precision Sales Corp.
5 Arbustus Ln., MR-97
Binghamton, NY 13901
607/648·3686
Precision Sales Corp."
1 Commerce Blvd.
liverpool, NY 13088

315/451·3480
TWX 710·545-0250
Precision Sales Corp.
3594 Monroe Avenue
Rochester, NY 14534
716/381 -2820

OHIO
Rich Electronic Marketing
7221 Taylorsville Road
Dayton, Ohio 45424
5131237·9422
TWX 810-459-1767
Rich Electronic Marketing
141 E. Aurora Road
Northfield. Ohio 44067

216/468-0583
TWX 810-427·9210

"Home Office

II-iv

OREGON
Northwest Marketing Assoc.
9999 S.W. Wilshire St.
Suite 124
Portland OR 97225
503/297-2581
TELEX 36-0465 (AMAPORT PTLI
PENNSYLVANIA
CMS Marketing
121A lorraine Avenue
P.O. Box 300
Oreland. PA 19075
215/885-5106
TWX 510-665-0161

TENNESSEE
Beacon Elect. Assoc" Inc.
103 Sequoyan Or.
Suite #2
Johnson City, TN 37681
615/282-2421
TWX 810-575-8555
Rich Electronic Marketing
1128 Tusculum Blvd.
SuiteD
Greenville, TN 37743
615/639·3139
TWX 810·576·4597
TEXAS
Southern States Marketing, Inc.
14330 Midway Road, Suite 226
Dallas, Texas 75234

214/387-2489
TWX 910-860-5732
Southern States Marketing. Inc
9730 Town Park Drive. Suite 104
Houston, Texas 77036
713/988-0991
TWX 910-881-1630

UTAH
Waugaman Associates
2520 S. State Street
#224
Salt lake City, UT 8411 5

801/467-4263
TWX 910-925-4026
WASHINGTON
Northwest Marketing Assoc.
12835 Bellevue-Redmond Rd.
Suite 203E
Bellevue, WA 98005
206/455-5846
TWX 910-443-2445
WISCONSIN
Carlson Electronic Sales
Northbrook Executive Clr.
10701 West North Ave.
Suite 209
Milwaukee, WI 53226
414/476-2790
TWX 910·222-1 819
CANADA
Cantec Representatives Inc.·
1573 Laperriere Ave.
Ottawa, Ontario
Canada K1Z 7T3
6131725·3704
TWX 610-562·8967
Cantec Representatives Inc.
83 Galaxy Blvd., Unit 1 A
(Rexdale)
Toronto, Canada M9W 5X6
416/675-2460
TWX 610-492-2655

U.S. AND CANADIAN DISTRIBUTORS

ARIZONA
Kierulff Electronics

4134 E. Wood St.
Phoenix, AZ 85040
6021243-4101
TWX 910/951-1550
Wyle Distribution Group
8155 North 24th Avenue
Phoenix, Arizona 85021
602/249-2232
TWX 910/951-4282
CALIFORNIA
Arrow Electronics
720 Palomar Avenue
Sunnyvale, CA 94086
408/739-3011
TWX 910/339-9371
Bell Industries
1161 N. Fair Oaks Avenue
Sunnyvale, CA 94086
4081734-8570
TWX 910/339-9378
Kierulff Electronics
2585 Commerce Way
Los Angeles, CA 90040
213/725-0325
TWX 910/580-3106
Kierulff Electronics
8797 8alboa Avenue
San Diego, CA 92123
714/278-2112
TWX 910/335-1182
Kierulff Electronics
14101 Franklin Avenue
Orange County, CA 92680
7141731-5711
TWX 910/595-2599
Schweber Electronics
17811 Gillette Avenue
Irvine, CA 92714
714/556-3880
TWX 910/595-1720
Wyle Distribution Group
124 Maryland Street
EI Segundo, CA 90245
213/322-8100
TWX 910/348-711 I
Wyle Distribution Group
9525 Chesapeake Drive
San Diego, CA 92123
714/565-9171
TWX 910/335- 1590
Wyle Distribution Group
17872 Cowan Ave.
Irvine, CA 92714
714/641-1600
TWX 910/348-71 I 1
Wyle Distribution Group
3000 Bowers Ave.
Santa Clara, CA 95051
4081727-2500
TWX 910/338-0296

FLORIDA
Arrow Electronics
1001 N.W. 62nd St.
Suite 108
Ft. Lauderdale, FL 33309

305/776-7790
TWX 510/955-9456
Arrow Electronics
115 Palm Bay Road, N.W.
Suite 10 Bldg. 200
Palm Bay, FL 32905
305/725- I 480
TWX 510/959-6337
Diplomat Southland
2120 Calumet
Clearwater, FL 335 15
813/443-4514
-rNX 810/866-0436
Kierulff Electronics
324 7 Tech Drive
St. Petersburg, FL 33702
813/576-1966
TWX 810/863-5625
GEORGIA
Arrow Electronics
2979 Pacific Ave.
Norcross, GA 30071
404/449-8252
TWX 8101766-0439
Schweber Electronics
4126 Pleasantdale Road
Atlanta, GA 30340
404/449-9170
ILLINOIS
Arrow Electronics
492 Lunt Avenue
P. O. Box 94248
Schaumburg, IL 60193
312/893-9420
TWX 9101291-3544
Bell Industries
3422 W. Touhy Avenue
Chicago, IL 60645
312/982-9210
TWX 9101223-4519
Kierulff Electronics
1536 Lanmeier
Elk Grove Village, IL 60007

INDIANA
Advent Electronics
8446 Moller
Indianapolis, IN 46268
317/297-4910
TWX 810/341 -3228
Ft. Wayne Electronics
3606 E. Maumee
Ft. Wayne, IN 46803
219/423-3422
TWX 810/332-1562
Pioneer /Indianapol is
6408 Castle place Drive
Indianapolis, IN 46250
317/849-7300
TWX 810/260-1794

IOWA
Advent Electronics
682 58th Avenue
Court South West
Cedar Rapids, IA 52404
319/363-0221
TWX 910/525-1337
MASSACHUSETIES
Arrow Electronics
960 Commerce Way
Woburn, MA 01801
617/933-8130
TWX 710/393-6770
Kierulff Electronics
13 Fortune Drive
Billerica, MA 01821
617/935-5134
TWX 710/390-1449
Lionex Corporation
1 North Avenue
Burlington, MA 01803
617/272-9400
TWX 710/332-1387
Schweber Electronics
25 Wiggins Avenue
Bedford, MA 01730
617/275-5100
TWX 710/326-0268

312/640-0200
TWX 910/222-0351

COLORADO
Kierulff Electronics
10890 E. 47th Avenue
Denver, CO 80239
303/371-6500
TWX 910/932-0169
Wyle Distribution Group
6777 East 50th Avenue
Commerce City, CO 80022
303/287-961 I
CONNECTICUT
Arrow Electronics
12 Beaumont Rd.
Wallingford, CT 06492

2031265-7741
TWX 710/476-0162
Schweber Electronics
Finance Drive
Commerce Industrial Park
Danbury. CT06810
2031792-3500
TWX 71 0/456-9405

II-v

MARYLAND
Arrow Electronics
4801 Benson Avenue
Baltimore, MD 21227
3011247 ·5200
TWX 7101236-9005
Schweber Electronics
9218 Gaither Rd.
Gaithersburg, MD 20760
301/840-5900
TWX 710/828-9749

MISSOURI
Olive Electronics
9910 Page Blvd.
St. Louis, MO 63132
314/426*4500
TWX 910/763-0720
Semiconductor Spec
3805 N. Oak Trafficway
Kansas City, MO 64116
816/452-3900
TWX 9101771-2114

MICHIGAN
Arrow Electronics
3810 Varsity Drive
Ann Arbor, MJ 48104
313/971-8220
TWX 8101223-6020
Schweber Electronics
33540 Schoolcraft Road
Livonia, MI 48150

NEW HAMPSHIRE
Arrow Electronics
1 Perimeter Rd.
Manchester, NH 03103

313/525-8100
TWX 810/242-2983

MINNESOTA
Arrow Electronics
5251 W. 73rd Street
Edina, MN 55435
612/830-1800
TWX 910/576-3125
Industrial Components
5229 Edina Industrial Blvd.
Minneapolis, MN 55435
612/831-2666
TWX 910/576-3153

603/668-6968
TWX 710/220-1684
NEW JERSEY
Arrow Electronics
Pleasant Valley Avenue
Morrestown, NJ 08057

609/235-1900
TWX 710/897-0829
Arrow Electronics
285 Midland Avenue
Saddlebrook, NJ 07662
2011797-5800
TWX 710/988-2206
Kierulff Electronics
3 Edison Place
Fairfield, NJ 07006

201/575-6750
TWX 71 0/734-4372
Schweber Electronics
18 Madison Road
Fairfield, NJ 07006

201/227-7880
TWX 71 0/734-4305

U.S. AND CANADIAN DISTRIBUTORS

NEW MEXICO
Bell/Century
11728 Unn N.E.
Albuquerque, NM 87123

5051292·2700
TWX 910/989·0625
Arrow Electronics
2460 Alamo Ave. S.E.
Albuquerque, NM 87106

505/243·4566
TWX 910/989·1679
NEW YORK
Arrow electronics
20 Oser Ave.
Hauppauge, NY 11787

5161231·1000
TWX 510/227·6623
Arrow Electronics
3000 S. Winton Road
Rochester, NY 14623

7161275·0300
TWX 510/253·4766
Arrow Electronics
7705 Mattage Drive
P. O. Box 370
Liverpool, NY 13088

315/652-1000
TWX 710/545·0230
Lionex Corporation
415 Crossway Park Drive
Woodbury. L.I., NY 11797

516/921·4414
T\lVX 510/221-2196
Schwaber Electronics
2 Twin line Circle
Rochester, NY 14623

716/424-2222
Schweber Electronics
Jericho Turnpike
Westbury. NY 11590

516/334·7474
TWX 510/222-3660
NORTH CAROLINA
Arrow Electronics
938 Burke 5t.
Winston Salem, NC 27102

919/725·8711
TWX 510/931·3169
Hammond Electronics
2923 Pacific Avenue
Greensboro, NC 27406

9191275·6391
TWX 5101925·1094

OHIO
Arrow Electronics
7620 McEwen Road
Centerville, OH 45459

513/453·5563
TWX 810/459·1611
Arrow Electronics
10 Knoll Crest Drive
Reading, OH 45237
513/761·5432
TWX 810/461·2670
Arrow Electronics
6238 Cochran Road
Solon, OH 44139

216/248·3990
TWX 810/427·9409
Pioneer/Cleveland
4800 East 131st Street
Cleveland, OH 44105

216/587·3600
TWX 810/422·221 1
Schweber Electronics
23880 Commerce Park Road
Beachwood, OH 44122

216/464·2970

TEXAS
Arrow Electronics
13715 Gamma Road
Dallas, TX 75240

UTAH
Bell/Century
3639 W. 2150 South
Salt Lake City, UT 84120

214/386·7500

801/972·6969
TWX 910/925·5686

TWX 910/860·5377
Quality Components
10201 McKalia
Suite D
Austin, TX 78758

512/835·0220
TWX 910/874·1377
Quality Components
4303 Alpha Road
Dallas, TX 75240

214/387·4949
TWX 910/860·5459
Quality Components
6126 Westline
Houston, TX 77036
713/772·7100
Schweber Electronics
7420 Harwin Drive
Houston, TX 77036

TWX 810/427·9441

713/784·3600
TWX910/881·1109

OKLAHOMA
Quality Components
9934 E. 21st
Tulsa, OK 74129

Wyle Distribution Group
1750 132nd Avenue, N.E.
Bellevue, WA 98005
206/453·8300
TWX 910/433·2526

918/664·8812

Kierulff Electronics
3695 W. 1987 South St.
Salt Lake City, UT 84104
801/973·6913
WASHINGTON
Kierulff Electronics
1005 Andover Park East
Tukwila, WA 98188

206/575·4420
TWX 910/444·2034
Wyle Distribution Group
1750 132nd Avenue N.E.
Bellevue, Washington 98005

206/453·8300
TWX 910/443·2526
WISCONSIN
Arrow Electronics
434 Rawson Avenue
Oak Creek, WI 53154
4141764·6600
TWX 9101262·1193
Kierulff Electronics
2212 E. Moreland Blvd.
Waukesha, WI53186

414/784·8160
TWX 9101262·3653

OREGON
Kierulff Electronics
4273 NW Science Park
Portland, OR 97227

503/641 ·9150
TWX 910/467·8753
PENNSYLVANIA
Arrow Electronics
4297 Greensl1urg Pike
Suite 3114
Pittsburg, PA 15221

4121351·4000
Schweber Electronics
101 Rock Road
Horsham, PA 19044

215/441·0600

CANAOA
Prelco Electronics
2767 Thames Gate Drive
Mississauga, Ontario
Toronto L4T 1 G5
416/678·0401
TWX 610/492·8974
Pre leo Electronics
480 Port Royal St. W.
Montreal 357 P.Q. H3L 2B9
514/389·8051
TWX 610/421·3616
Pre leo Electronics
1770 Woodward Drive
Ottowa, Ontario K2C CP8
613/226·3491
Telex 05·34301
RAE. Industrial
3455 Gardner Court
Burnaby, B.C. V5G 4J7

6041291·8866
TWX 610/929·3065
Zentronics
141 Catherine Street
Ottawa, Ontario
K2P lC3
613/238·6411
Telex 05·33636
Zentronics
1355 Meyerside Drive
Mississauga, Ontario
(Toronto) L5T 1 C9
416/676·9000
Telex 06·983657
Zentronics
5010 Rue Pare
Montreal, Quebec
M4P 1P3
5141735·5361
Telex 05·827535
Zentronics
590 Berry Street
SI. James, Manitoba
(Winnipeg) R2H OR4
204/775·8661
Zentronics
480A Dutton Drive
Waterloo, Ontario
N2L 4C6

519/884·5700

Pioneer/Pittsburgh
560 Alpha Orive
Pittsburgh, PA 15328
4121782·2300
TWX 710/795·3122
SOUTH CAROLINA
Hammond Electronics
1035 Lown Des Hill Rd.
Greenville, SC 29602
803/233·4121
TWX 8101281·2233

II-vi

INTERNATIONAL MARKETING OFFICES
EUROPEAN HEAD OFFICE
Mostek International
150 Chaussee de la Hulpe
B·1170 Brussels
Belgium
(32) 2 6606924
Telex· 846 6201 1 MKBRU B
FRANCE
Mostek France SAR.L.
30. Rue de Morvan
Silic 505
94623 Rungis Cedex
(33) 1 6873414
Telex· 842 204049 MKFRANF F

GERMANY
Mostek GmbH
Talstrasse 172
Schurwaldstrasse 15
0·7303 Neuhausen/Filder

Mostek GmbH
Zaunkoenlgstrasse 18
0-8021 Ottobrunn
(49) 89 6091017-19
Telex· 8415216516 MKMU D

7158/66.45
Telex - 72.38.86
Mostek GmbH
Friedlandstrasse 1
2085 Quickborn/Hamburg
(491404106207712078
Telex·841 1213685 MKHA 0

)TALY
Mostek Italia S.P.A.
Via G. da Procida. 10
1·20149 Milano
(39) 23185337 or
3492696
Telex· 843 333601 MOSTEK I

JAPAN
Sanyo Bldg 3F
'-2·7 Kita·Aoyama
Minato-Ku. Tokyo 107
(81) 3 4047261
"Telex 781 23686 J23686 MOSJAOV
SWEDEN
Mostek Scandinavia AB
Magnusvagen 1
S·175 31 Jarfalla
(46) 75B-343-38
Telex - 854 12997 MOSTEK S

UNITED KINGDOM
Mostek U.K. Ltd.
Masons House.
1 ·3 Valley Drive.
Kingsbury Road.
London. NW9
(44) 1 2049322
Telex· 851 25940 MOSTEK G

INTERNATIONAL SALES REPRESENTATIVES/DISTRIBUTORS
ARGENTINA
Rayo Electronics S R.L.
Belgrano 990, Pisos 6y2
1092 Buenos Aires
(38)-1779.37-9476
Telex· 122153

FRANCE
P.E.P.
4. Rue Barthelemy
F·92120 Montrouge
(33) 1-735.33.20
Telex· 204534

AUSTRALIA
Amtron Tyree Pty.ltd.
176 Botany Street
Waterloo, N.S.W. 2017
(61) 69·89.666
Telex·25643

SCAIS
80, rue d'Arcueil
SILIe 137
F·94150 Rungis Cedex
(3311-687.23.12
Telex· 204674

AUSTRIA
TranSlstor-Vertriebs GmbH
Auhofstrasse 41 A
A·1130 Vienna
(431222-829.45.12
Telex - 13738

Societe COPEL
Rue Fourny . Z.I.
B.P.22
F-7B530 BUe

BRAZIL
Cosele, Ltd.
Rua da Consolacao, 867
Conj.31
01301 Sao Paulo
(55) 11-257.35.351258.43.25
Telex· 1130869
BELGIUM
Sotronic
14, Rue Pere de Oeken
8·1040 Brussels
(32) 2-736.10.07
Telex· 25141
DENMARK
Semicap APS
Gammel Kongevej 184.5
OK· 1850 Copenhagen
(45) 1-22.15.10
Telex - 15987
FINLAND
S.W. Instruments
Karstulantie 4 B
SF·00550 Helsinki 55
(358)-0-73.82.65
Telex· 122411

1/956.10.18
Telex· 69.63.79
SORHODIS
150.152, rue Anatole France
F·69100 VILLEURBANNE

78/85.00.44
Telex 38.01.81

HONG KONG
Cet Limited
1402 Tung Wah Mansion
199·203 Hennessy Road
Wanchai, Hong Kong
(5)-72.93.76
Telex· 85148
ISRAEL
Telsys, LTD.
12 Kehilat Venetsia St
Tel Aviv
48.21.26·28
Telex· 32.392

ITALY
Comprel S.r.L.
Viale Romagna, 1
1·20092 Cinisello Balsamo
(39) 2-928.08.09/928.03.45
Telex·332484
EMESA S.PA
Via L. da Via dana, 9
1·20122 MILANO

2/869.06.16
GERMANY
Neye Enatechnik GmbH
Schillerstrasse 14
0·2085 Quickborn
(49) 4106-61 .21 .95
Telex· 213.590
Dr Dohrenberg
Bayreuther Strasse 3
0·1 Bertin 30
(49) 30-213.80.43
Telex· 184860
Raffel-Electronic GmbH
Lochnerstrasse 1
0·4030 Ratingen
(4912102-28024
Telex - 8585180
Siegfried Ecker
Koenigsberger Strasse 2
0·6120 Michelstadt
(49) 6061-2233
Telex·4191630
Matronic GmbH
Lichtenberger Weg 3
0·7400 Tuebingen
(49) 7071 124.331
Telex· 726.28.79

THE NETHERLANDS
Nijkerk Elektronika BV
orentestraat 7
1083 HK Amsterdam
1020.1428.933
Telex· 11625
NEW ZEALAND
E.C.S. oiv. of Airspares
P.O. Box 1048
Airport Palmerston North
(771-047
Telex· 3766
NORWAY
Hetro Tekniska A/S
Postboks 6596
Rodelkka
Oslo 5
(47) 2-38.02.86
Telex· 16205
SINGAPORE
Oynamar International. LTD.
Suite 526, Cuppage Center
55 Cuppage Road
Singapore 0922

Telex· 33.50.66
JAPAN
Systems Marketing. Inc.
4th Floor. Shindo Bldg.
3·12·5 Uchikanda.
Chiyoda·Ku,
Tokyo, 100
(81) 3-254.27.51
Telex· 25761
Teijin Advanced Products Corp.
'·1 Uchisaiwai·Cho
2·Chome Chiyoda·Ku
Tokyo, 100
(81) 3-506.46.73
Telex· 23548
KOREA
Vine Overseas Trading Corp.
Room 303·Tae Sung Bldg.
199·1 Jangsa·Dong
Jongro-Ku
Seoul
(26)-1663, 25·9875
Telex· 24154

Dema·Electronic GmbH
Bluetenstrasse 21
0·8 Muenchen 40
(49) 89-288018
Telex· 28345

II-vii

SOUTH AFRICA
Radiokom
P.O. Box 56310
Pinegowrie
2123.
Transvaal
789·1400
Telex· 8·0838 SA

SWITZERLAND
Memotec AG
CH-4932 Lotlwil
(41) 63-2B. 11.22
Telex - 68636
TAIWAN
Dynamar Taiwan Limited
P.O. Box 67·445
2nd Floor. No. 14, Lane 164
Sung·Chiang Road
Taipei
5418251
Telex· 11064
UNITED KINGDOM
Celdis Limited
37·39 Loverock Road
Reading
Berks RG 31 ED
(44) 734-58.51.71
Telex· 848370
Distronic Limited
50-51 Burnt Mill
Elizabeth Way,
Harlow
Essex CM 202 HU

(44) 279-32.497/39.701
Telex - 81387
A.M. Lock Co., Ltd.
Neville Street,
Chadderton,
Oldham, Lancashire
(44) 61 -652.04.31
Telex· 669971

SPAIN
Comelta SA
Cia Electronica Tecnicas Aplicadas
Consejo de Cjento, 204
Entlo 3A.
Barcelona 11
(34) 3-254.66.07/08
Telex· 51934

Pronto Electronic Systems Ltd.
645 High Road.
Seven Kings,
liford,
Essex IG 38 RA
(44) 1-599.30.41
Telex' 24507

COMELTA S.A.
Cia Electronica Tecnicas Aplicadas
Emilio Munoz 41,
Esc. 1, Planta 1, Nave 2
Madrid 17

Pronto Electronic Systems Ltd.
466·478 Cranbrook Road,
Gants Hill
IIlford
Essex 1G3 8RA

11754·4530/4621/3077/3001

1/599.30.41

Telex·42.007

Telex - 24.507

SWEDEN
Interelko AB
Strandbergsg.47
5·11251 Stockholm
(46) 8- 13.21.60
Telex· 10689

YUGOSLAVIA
Chemcolor
Inozemma Zastupstva
Prolelerskih brigada 37·a
41001 Zagreb
(411-513.911
Telex· 21236

MICRO SYSTEMS DATA BOOK

MOSTEI(

MICRO SYSTEMS

STO-Z80 Bus Systems
INTRODUCTION
The STD BUS concept is a jOint design between Mostek and
Pro-Log to satisfy the need for cost-effective OEM
Microcomputer Systems. The definition of the STD BUS and
the MD Series™ of OEM microcomputer modules is a result
of years of microcomputer component and module
manufacturing experience. The STD BUS uses a
motherboard interconnect system concept and is designed
to handle any MD Series™ card in any card slot. Modules for
the STD BUS range from CPU, RAM and EPROM Modules
to Input, Output, AID and TRIAC control modules.
Printed circuit modules for the STD BUS are a compact 4.5 x
6.5 inches providing for system partitioning by function
(RAM, PROM, 1/0). This smaller module size makes system
packaging easier while increasing MOS-LSI densities
provide high functionality per module. Mostek has defined
the STD-Z80 BUS which is a subset of the general-purpose
STD BUS. This bus is defined extensively for the Z80

microprocessor and its supporting peripherals. By
specifying the STD-Z80 BUS, exact functional pin
descriptions and bus timing can be given. A STD-Z80
system will be guaranteed to work with all STD-Z80designed boards. The STD-Z80 BUS fully supports the
powerful Mode 2 interrupt capability of the Z80
microprocessor.
The MD Series™ provides both STD-Z80 BUS expandable
modules, designated as MDX, and single-board stand-alone
modules, designated as MD. For those applications
requiring bus expandability, the MDX~CPU series provides
that capability; if a single-board microcomputer is sufficient,
the MD-SBC1 provides the system designer with a powerful Z80-based microcomputer solution.
The MD Series™ of OEM microcomputer boards and the
STD-Z80 BUS offer the most cost-effective system
configuration available to the OEM system designer.

11\-1

MD-STO-Z80 BUS DESCRIPTION
MNEMONIC

DESCRIPTION

1
2

+5V
+5V

+5Vdc system power
+5Vdc system power

3
4
5

GNO
GNO
-5V
-5V

Ground-System signal ground and OC return
Ground-System signal ground and OC return
-5Vdc system power
-5Vdc system power

7
8
9
10
11
12
13
14

03
07
02
06
01
05
00
04

Oata Bus (Tri-state. input/output. active high). 00-07 constitute an
8-bit bidirectional data bus. The data bus is used for data exchange
with memory and I/O devices.

15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

A7
A15
. A6
A14
A5
A13
A4
A12
A3
All
A2
Al0
Al
A9
AO
A8

BUS PIN

t>

Address Bus (tri-state. output. active high). AO-A 15 make up a 16bit address bus. The address bus provides the address for memory
(up to 65K bytes) data exchanges and for I/O device data
exchanges. I/O addressing uses the lower 8 address bits to allow
the user to directly select up to 256 input or 256 output ports. AO is
the least significant address bit. Ouring refresh time. the lower 7
bits contain a valid refresh address for dynamic memories.

31

/WR

Write (Tri-state. active low). /WR indicates that the CPU data bus
holds valid data to be stored in the addressed memory or I/O device.

32

IRO

Read (Tri-state. output. active low). /RO indicates that the CPU
wants to read data from memory or an liD device. The addressed
liD device or memory should use this signal to gate data onto the
CPU data bus.

33

IIORQ

Input/Output Request (Tri-state. output. active low). The IIORQ
signal indicates that the lower half of the address bus holds a valid
I/O address for an liD read or write operation. An IIORQ signal
is also generated with an /Ml signal when an interrupt is being
acknowledged to indicate that an interrupt response vector can be
placed on the data bus. Interrupt Acknowledge operations occur
during IMl time. while I/O operations never occur during /Ml
time.

34

/MEMRQ

Memory Request (Tri-state. output. active low). The /MEMRQ signal
indicates that the address bus holds a valid address for a memory
read or memory write operation.

111-2

MNEMONIC

DESCRIPTION

35

IIOEXP

I/O Expansion, not used on Mostek MD cards. (Normally
strapped to ground on the Mostek motherboard)

36

IMEMEX

Memory Expansion, not used on Mostek MD cards. (Normally
strapped to ground on the Mostek motherboard)

37

IREFRESH

REFRESH (Tri-state, output, active low). IREFRESH indicates that the
lower 7 bits of the address bus contain a refresh address for
dynamic memories and the IMEMRQ signal should be used to
perform a refresh cycle for all dynamic RAMs in the system. During
the refresh cycle, A7 is a logic 0 and the upper 8 bits of the address
bus contain the I register.

38

IMCSYNC

Not generated by the Mostek CPU cards. IMCSYNC can be
generated by gating the following signals: IRD + IWR + IINTAK. By
connecting a jumper on the MDX-CPU, this line becomes IDEBUG
(Input). IDEBUG is used in conjunction with the DDT-80 operating
system on the MD-DEBUG card and the MD-SST card for
implementing a hardware single step function. When pulled low,
the IDEBUG line will set an address modification latch which will
force the upper three address lines A 15, A 14, and A 13 to a logic 1.
These address lines will remain at a logic 1 until reset by performing
any liD operation.

39

ISTATUS 1 (M1)

Machine Cycle One. (Tri-state, output, active low). IM1 indicates that
the current machine cycle is in the op code fetch cycle of an
instruction. Note that during the execution of two byte opcodes,
IM1 will be generated as each op code is fetched. These two byte
opcodes always begin with a CBh, DDh, or FDh. IM1 also occurs
with IIORQ to indicate an interrupt acknowledge cycle.

40

ISTATUS 0

Not used on Mostek MD cards.

41

IBUSAK

Bus Acknowledge (Output, active low). Bus acknowledge is used to
indicate to the requesting device that the CPU address bus, data bus,
and control bus signals have been set to their high impedance state
and the external device can now control the bus.

42

IBUSRQ

Bus Request (Input,active low). The IBUSRQ signal is used to
request the CPU address bus, data bus, and control signal bus to go
to a high impedance state so that other devices can control those
buses. When IBUSRQ is activated, the CPU will set these buse~ to
a high impedance state as soon as the current CPU machine cycle
is terminated and the IBUSAK signal is activated.

43

IINTAI<

Interrupt Acknowledge (Tri-state, output, active low). The IINTAK
signal indicates that an interrupt acknowledge cycle is in progress,
and the interrupting device should place its response vector on the
data bus. The IINTAK signal is equivalent to an IIORQ during
an IM1.

BUS PIN

111-3

BUS PIN

MNEMONIC

DESCRIPTION

44

IINTRO

Interrupt Request (Input, active low). The Interrupt Request signal is
generated by 1/0 devices. A request will be honored at the end of
the current instruction if the internal software controlled interrupt
enable flip flop (IFF) is enabled and if the IBUSRO signal is not
active. When the CPU accepts the interrupt, an interrupt
acknowledge signal IINTAK (fIORO during an IM1) is sent out at
the beginning of the next instruction.

45

IWAITRO

Wait Request (Input, active low). Wait Request indicates to the CPU
that the addressed memory or 1/0 device is not ready for a data
transfer. The CPU continues to enter wait states for as long as this
signal is active. This signal allows memory or 1/0 devices of any
speed to be synchronized to the CPU. Use of this signal postpones
refresh as long as it is held active.

46

INMIRO

Non Maskable Interrupt Request (Input, negative edge triggered). The
Non Maskable Interrupt Request line has a higher priority than the
IINTRO line and is always recognized at the end of the current
instruction, independent of the status of the interrupt enable flip-flop.
INMIRO automatically forces the CPU to restart to location D066h.
The program counter is automatically saved in the external stack so
that the user can return to the program that was interrupted. Note
that continuous WAIT cycles can prevent the current instruction
from ending, and that a IBUSRO will override a INMIRO.

47

ISYSRESET

System Reset (Output, active low). The System Reset line indicates
that a reset has been generated either from an external reset or the
power on reset circuit. The system reset will occur only once per
reset request and will be approximately 2/J.s in duration. A system
reset will also force the CPU program counter to zero, disable
interrupts, set the I register to DOh, set the R register to DOh, and
set Interrupt Mode O.

48

IPBRESET

Push Button Reset (Input, active low). The Push Button Reset will
generate a debounced system reset.

49

ICLOCK

Processor Clock (Output, active low). Single phase system clock.

50

ICNTRL

Not used on Mostek MD cards.

51

PCO

Priority Chain Output (Output, active high). This signal is used to
for a priority interrupt daisy chain when more than one interrupt
driven device is being used. A high level on this pin indicates that
no other devices of higher priority are being serviced by a CPU
interrupt service routine.

52

PCI

Priority Chain In (Input, active high). This signal is used to form a
priority interrupt daisy chain when more than one interrupt driven
device is being used. A high level on this pin indicates that no other
devices of higher priority are being serviced by a CPU interrupt
service routine.

53

AUX GND

Auxiliary Ground (Bussed)

54

AUX GND

Auxiliary Ground (Bussed)

111-4

DESCRIPTION

BUS PIN

MNEMONIC

55

+12V

+12Vdc system power

56

-12V

-12Vdc system power

NOTES
1. Input/Output references of each signal are made with respect to MDX-CPU
module.

2. The following signals have pull-up resistors: IWR, IRD, IIORO, IMEMRO,
IREFRESH, IDEBUG, IM1, IBUSRO, IINTAK, IINTRO, IWAITRO,
INMIRO, ISYSRESET, IPBRESET and ICLOCK.

111·5

MICRO SYSTEMS DATA BOOK

MOSTEI(@

'MDX SERIES DATA PROCESSING

MDX-CPU1
MK77850-0, MK77850-4
FEATURES

MDX-CPU 1 BOARD

o STD-Z80 BUS-compatible

o

4K x 8 EPROM (two 2716's, customer-provided)

o

256 x 8 Static RAM (compatible with DDT -80 debugger)

o

Flexible Memory decoding for EPROM and RAM

o

Four counter/timer channels

o

Restart to OOOOH or EOOOOH (strapping option)

o

Debug-compatible for single step in DDT-80

o

2.5MHz version (-0)

o

4MHz version (-4)

o

+5Vonly

o

Fully-buffered signals for system expandability

o

Z80 CPU

MDX-CPU1 DESCRIPTION
The Mostek MDX-CPU1 is the heart of an MD Series Z80
system. Based on the powerful Z80 microprocessor, the
MDX-CPU1 can be used with great versatility in an OEM
microcomputer system application. This is done simply by
inserting custom ROM or EPROM memories into the
sockets provided on the board and configuring them
virtually anywhere within the Z80 memory map.
On-board memory is provided in the form of sockets for 4K
of EPROM (2-2716's) and 256 bytes of scratchpad RAM as
pictured in the block diagram. Either 2716 EPROM can be
located at any 2K boundary within any given 16K block in
the Z80 memory map via a jumper arrangement. In

addition, an MK3882 Counter Timer Circuit is included on
the MDX-CPU1 to provide counting and timing functions for
the Z80.
The MDX-CPU1 can be used in conjunction with the MDXDEBUG and MDX-DRAM modules to utilize DDT-80 and
ASMB-80 in system development. This is accomplished by
strapping the scratchpad RAM to reside at location FFOOH
sothat it will act as the Operating System RAM for DDT-80.
The MDX-CPU1 is also available in a 4MHz version (MDXCPU1-4). In this version, one wait state is automatically
inserted each time that the on-board memory is accessed by
a read or write cycle. This is necessary to make the access
times of the .2716 PROMs and the 3539 scratchpad RAM
compatible with the MK3880 4MHz Z80-CPU.

IV-1

M DX-CPU1 BLOCK DIAGRAM

CTC

...

II" CE

MK3BB2

~

PORT
SELECT

~}

I

DATA

I L.'.0",

CPU
MK3BBO

~

L

CRYSTAL

CONTROLLED

'--------'

a

~

~

a

;r

;, ~~

CLOCK
GENERATOR

~ONTROL7
BUFFER

O

STRAPPING
OPTINS

DECODE
lOGIC

16

Y A~t?F~~~SJ6

Lt--

'--'--

DlR

A15-A10

Instruction:
Data:

DATA BUS
DIRECTION

07 - DO

DATA

.v

~

J

A15 - AO

DECODE
OPTIONS

CPU MAD

EXTERNAL TRIGGER

.,D """"'"

• _. CONTROL

CASCADEJ
STRAPPING

LOGIC

CONTROL
SYSTEM
RESET

lh ,":
:>'

~

~ORTSElECT

I

\

p

rr-

t

TI

~
~

, -,

7

CHO-~

Il

030

400 ns @ 2.5 MHz
250 ns @ 4.0 MHz
Min; 4 T states
Max. 23 T states

Off-board expansion to a total of 65,536 bytes is
possible with the use of various MDX memory modules.

IV-6

I

MEMORY REFRESH
The MDX-CPU2 generates all address and control
signals necessary to refresh dynamic RAM (such as
MDX-DRAM) modules. Refresh occurs automatically
during each OP code fetch cycle and is therefore
transparent to system throughput.

The on-board 4-channel programmable timer is hardwired to the following addresses:

o
1

2
3

The MDX-CPU2 will also accept nonmaskable interrupts
which force a restart at location 0066H.
SYSTEM INTERRUPT UNITS (SIU)

I/O ADDRESSING

MK3882 Channel

Multi-level interrupt processing is also possible with the
CPU. The level of stacking is limited only by
available memory space.

zao

Port Address (Hex)
7C
7D
7E
7F

SYSTEM CLOCK
MDX-CPU2
MDX-CPU2-4

2.5 MHz ± 0.05%
4.0 MHz ± 0.05%

STD BUS INTERFACE
Inputs:
Outputs:

I/O CAPACITY

One 74LS load max.
10L = 24 mA min. @ VOL 0.5 Volts
10H = -3 mA min. @ VOH 2.4 Volts

The Z80 CPU utilizes the lower 8 bits of its address bus
for I/O addressing to yield a total of 256 possible port
addresses.

OPERATING TEMPERATURE

INTERRUPTS

POWER SUPPLY REQUIREMENTS

The Z80-CPU may be programmed to process interrupts
in any of three different modes (mode 0, 1 or 2 as
described in the MK3880 Technical Manual). Mode 2
operation (vectored interrupts) is by far the most
powerful and is compatible with Mostek MDX Series
cards.

O°C to 60°C

5V ± 5% at 1.2 A (excluding memory power requirements)

CARD DIMENSIONS
4.50 in. (11.43 cm.) wide by 6.50 in. (16.51 cm.) long
0.48 in. (1.22 cm.) maximum height
0.062 in. (0.16 cm.) printed circuit board thickness

CONNECTORS

Function

Configuration

Mating
Connectors

STD-Z80 BUS

56-Pin
0.125 in. centers

PRINTED CIRCUIT
Viking 3VH28/1 CE5
WIRE-WRAP
Viking 3VH28/
1CND5
SOLDER LUG
Viking 3VH28/
1CN5

CTC I/O

26-Pin
0.100 in. centers

=1

FLAT RIBBON
Ansley 609-2600M
DISCRETE WIRES
Winchester PGB26A
(Housing)
Winchester 10070020 (Contacts)

IV-7

ORDERING INFORMATION
DESIGNATOR

DESCRIPTION

PART NO.

MDX-CPU2.

2.5 MHz CPU2 module with Operations Manual
(less memory and mating connectors)

MK77853-0

MDX-CPU2-4

4.0 MHz CPU2 module with Operations Manual
(less memory and mating connectors)

MK77853-4

MDX-CPU2 and MDX-CPU2-4 Operations Manual Only

MK79711

IV-8

MOSTEI(.
MDX SERIES DATA PROCESSING

MDX-MATH
MK77852-0
FEATURES

MDX-MATH BOARD PHOTO

o STD-Z80 BUS compatible
o Fixed-point 16 and 32-bit operations
o Floating point 32-bit operations
o Binary data formats
o Add, Subtract, Multiply and Divide
o Trigonometric and inverse trigonometric functions
o Square roots, logarithms, exponentials
o Float-to-fixed and fixed-to-float conversions
o Stack-oriented operand storage
o On-board wait-state insertion circuitry

DESCRIPTION
The MDX-MATH board is offered as one of Mostek's
complete line of STD-Z80 BUS-compatible microcomputer
modules. The MDX-MATH board, based on the AM9511
Arithmetic Processing Unit (APU), provides high performance fixed and floating point trigonometric and
mathematical operations. It can be used to enhance the
computational capability of a wide variety of STD-Z80 BUS
systems.
Figure 1 is a block diagram which illustrates the functional
elements of the MDX-MATH board.
The Arithmetic Processing Unit is a monolithic MOS/LSI
device that performs all of the mathematical operations. All
transfers to and from the APU take place over the 8-bit,
bi-directional data bus. Operands are pushed onto an

IV-9

internal stack within the APU and a command is issued to
perform operations on the data in the stack. Results are
then available to be retrieved from the stack, or additional
commands may be entered.
Side A ofthe MK3881 PIO can be utilized to provide a Z80
Mode 2 interrupt response when the APU completes the
execution of a command and pulls its END line low. If the
PIO has been programmed to interrupt on the high-to-Iow
transition of port bit A7, it will provide a vectored interrupt
and maintain the daisy-chain-priority interrupt logic
compatible with the STD-Z80 BUS.
Each MDX-MATH board has a total of five registers; three
WRITE only and two READ only. These registers appear as
three I/O port addresses and are defined in Table 1.

MDX-MATH BLOCK DIAGRAM
2M Hz
CRYSTAlCONTROllED
CLOCK
GENERATOR

AM9511
APU
ClK

6
END

ADDRESS
DECODE
AND
BUS
INTERFACE
lOGIC

ZBO
PIO
MK3BB

A7

B A
SELECT

MDX-MATH REGISTERS

16-BIT FIXED POINT FORMAT

Table 1
S _VALUE

.

il

11111111 II111
Port
Address

Read

'15
(MSBI

Write

x X X X X X 0 0 APU Status

APU Command

XXXXXXO 1 Undefined

PIO.Side A Control

X X X X X X 1 0 APU Stack

APU Stack

0

32-BIT FIXED POINT FORMAT

Ii

14111111 I1I11

ttlElllllllllll1 L'

31
(MSB)

FLOATING POINT FORMAT
The "X" symbols are "don't cares" and are jumperselectable, These port addresses are fully decoded:
The MDX-MATH board operates from an independent 2
MHz, crystal-controlled, clock generator circuit. The time
required by the AM9511 to execute some of its commands
can exceed 4 milliseconds. Because ofthis, there is circuitry
designed to block any access to the APU which would cause
wait states to be inserted for such lor;g periods of time
during the execution of a command. This action prevents
any interference with dynamic memory refresh as well as
any sacrifice of Z80 processing time.
The Arithmetic Processing Unit handles operands in both
fixed point and floating point formats. Fixed point operands
may be represented in either single (16-bit operands) or
double precision (32-bit operands) and are always
represented as binary, two's complement values.

The format forfloating point values is given. The mantissa is
expressed as a 24-bit (fractional) value; the exponent is
expressed as an unbiased two's complement 7-bit value
having a range of -64 to +63. The most significant bit is the
sign of the mantissa (0 = positive, 1 =. negative), for a total of
32 bits. The binary point is assumed to be to the left of the
most significant mantissa bit (bit 23). All floating point data
values must be normalized, Bit 23 must be equal to 1,
except for the valUe zero, which is represented by all zeros.

I~W\:t3130

EXPON ENT ..

'4

MANTlSSA_,

11111 L 1II111111111111111 J
2423

0

The range of values that can be represented in this format is
± (2.7 x 10-20 to 9.2 x 10 18) and zero.

lV-tO

STACK CONTROL

format is specified. Bit 6 selects the precision of the data to
be operated on by fixed point commands (if bit 5 = O. bit 6
must be 0). If bit 6 is a 1. single-precision (16-bit) operands
are indicated; if bit 6 is a O. double-precision (32-bit)
operands are indicated. Results are undefined for all illegal
combinations of bits in the command byte.

The user interface includes access to an 8-level. 16-bitwide data stack. Since single-precision. fixed-point
operands are 16 bits in length. eight such values may be
maintained in the stack. When using double-precision. fixed
point or floating point formats. four values may be stored.
The stack in these two configurations can be visualized as
shown.
TOS
NOS

--

B6 B5

84

B3

TOS_ BB B7

B2

B1

NOS_ B4 B3 ,B2

1

B1

1

!

1

COMMAND STRUCTURE
Figure 2 lists the commands and their mnemonics,
Each command consists of a single 8-bit byte having the
format illustrated.

IIOPERATIONIl

ISINGLE' F I X E D ' CODE'
5

4

I BUSY , SIGN , ZEROI

, ,

ERROR CODE

o

7

Data is written onto the stack. eight bits at a time. in the
order shown (B 1. B2. B3 •... ). Data is removed from the stack
in reverse byte order (B8. B7. B6 •... ). Data should be
transferred into or out of the stack in multiples of the
number ,of bytes appropriate to the chosen data format.

6

Device status is provided by means of an internal status
register whose format is shown.

4

8

7

DEVICE STATUS

3

2

o

BUSY:

Indicates, that the MDX-MATH board is
currently executing a command (1 =Busy).
SIGN:
Indicates that the value on the top of stack
is negative (1 Negative).
ZERO:
Indicates that the value on the top of stack
is zero (1 =Value is zero).
ERROR CODE: This field contains an indication of the
validity of the result of the last operation.
The error codes are:
0000 - No error
1000 - Divide by zero
0100 - Square root or log of negative
number
1100 - Argument of inverse sine. cosine.
or eX too large
XX10 - Underflow
XX01 - Overflow
CARRY:
Previous operation resulted in carry or
borrow from most significant bit. (1 =
Carry/Borrow. 0 No Carry/No Borrow)

=

=

Bits 0-4 select the operation to be performed. Bits 5-6 select
the data format for the operation. If bit 5 is a 1. a fixed point
data format is specified. If bit 5 is a O. the floating point

The BUSY bit in the status register can be read by the Z80
CPU at any time whether an operation is in progress or not.

IV-11

COMMAND SUMMARY
Figure 2

ACOS
ASIN
ATAN
CHSD .
CHSF
CHSS
COS
DADD
DDIV
DMUL
DMUU
DSUB
EXP
FADD
FDIV
FIXD
FIXS
FLTD
FLTS
FMUL
FSUB

ARCCOSINE
ARCSINE
ARCTANGENT
CHANGE SIGN DOUBLE
CHANGE SIGN FLOATING
CHANGE SIGN SINGLE
COSINE
DOUBLE ADD
DOUBLE DIVIDE
DOUBLE MULTIPLY LOWER
DOUBLE MULTIPLY UPPER
DOUBLE SUBTRACT
EXPONENTIATION (eX)
FLOATING ADD
FLOATING DIVIDE
FIX DOUBLE
FIX SINGLE
FLOAT DOUBLE
FLOAT SINGLE
FLOATING MULTIPLY
FLOATING SUBTRACT

LOG
LN
NOP
POPD
POPF
POPS
PTOD
PTOF
PTOS
PUPI

COMMON LOGARITHM
NATURAL LOGARITHM
NO OPERATION
POP STACK DOUBLE
POP STACK FLOATING
POP STACK SINGLE·
PUSH STACK DOUBLE
PUSH STACK FLOATING
PUSH STACK SINGLE
PUSH
POWER (xY)
SINGLE ADD
SINGLE DIVIDE
SINE
SINGLE MULTIPLY LOWER
SINGLE MULTIPLY UPPER
SQUARE ROOT
SINGLE SUBTRACT
TANGENT
EXCHANGE OPERANDS DOUBLE
EXCHANGE OPERANDS FLOATING
EXCHANGE OPERANDS SINGLE

PWR
SADD
SDIV
SIN
SMUL
SMUU
SQRT
SSUB
TAN
XCHD
XCHF
XCHS

WORD SIZE

The MDX-MATH board operates from an independent
2M Hz clock.

Data:

8 bits
8 bits

1/0 Addressing:

OPERATING TEMPERATURE RANGE

1/0 ADDRESSING

O°C to 60°C

On-board programmable - See Table 1

POWER SUPPLY REQUIREMENTS
1/0 CAPACITY

+12V ± 5% at 120 rnA max
+5V ± 5% at 0.9 A max

Five parallel 8-bit ports. Three WRITE Only and two READ
only. (See Table 1)

STD BUS INTERFACE
INTERRUPTS
Vectored interrupt generated. Daisy-chained interrupt
priority. Interrupt vector programmable upon initialization.

SYSTEM INTERRUPT UNITS (SIU)

One 74LS Load max
10H = -3mA min at 2.4 Volts
10L 24mA min at 0.5 Volts

=

=1

SYSTEM CLOCK
MDX-MATH

Inputs:
Outputs:

CARD DIMENSIONS
MIN

MAX

250kHz

2.5 MHz

4.5 in. (11.43cm) high by 6.50 in. (16.51 cm) long
0.48 in. (1.22cm) maximum profile thickness
0.062 in. (0.16cm) printed-circuit-board thickness

IV-12

CONNECTORS

Function

Configuration

Mating
Connector

STD-Z80 BUS

56-pin dual readout
0.125 in. centers

PRINTED CIRCUIT
Viking 3VH28/1 CE5
WIRE WRAP
Viking 3VH281
1CND5
SOLDER LUG
Viking 3VH281
1CN5

ORDERING INFORMATION
DESIGNATOR

DESCRIPTION

PART NO.

MDX-MATH

Module with Operations Manual; 2.5 MHz version.

MK77852-0

MDX-MATH Operations Manual Only

MK79141

IV-13

MICRO SYSTEMS DATA BOOK

0=-'

_ _ -Ta~'le ~f Contents

11

~I)

General Information

II

~10
IV

____' __

STD-Z80 BUS

il

M OX Series Data Processi

M D Series Accessories
MD Series Data Processing

SDE Series
Input/Outpu
--

~I~

_SDE Series Memory !I

~I~

SDE Series Accessories

II

~'0

Software Disk Based

II

,elc~plT.ent

Systems

Peripherals

II

MD SERIES

System Interrupt Units

CARD

SIU's

MDX-CPU1
MDX-CPU2
MDX-DRAMS/16/32
MDX-EPROM/UART
MDX-DEBUG
MDX-PIO
MDX-SIO
MDX-SST
MDX-FLP
MDX-MATH
MDX-AiDS
MDX-AIO
MDX-AlD12
MDX-D/AS
MDX-D/A12
MDX-UMC
MDX-SRAM4/S/16
MDX-EPROM
MDX-INT
MDX-SC/D

I!

V-1

1
1

0
0
0
2
1

0
1
1
1

0
1

0
0
0
0
0
1
1

V-2

MOSTEI{.
MD SERIES I/O CARDS

M OX-AI OS
MK77669-0, MK77669-4
FEATURES

MDX-A/DB BOARD PHOTO

o STD-Z80 BUS compatible
o 8-Bit AID converter with 16 single-ended analog inputs
o 0 to +5 Volts Full Scale Input Range
o Total unadjusted error < ± V2 LSB
o Linearity error < ± Y2 LSB
o No missing codes
o Guaranteed monotonicity
o No zero-adjust required
o No full-scale adjust required
o Provisions for additional channel expansion
o Single +5 Volt supply
o Address programmable

The Analog to Digital Converter Module, MDX-AlD8, is
designed to be a 16-channel single-ended AID module for
the STD-Z80 BUS. The module is designed around the
Mostek MK50816 8-bit AID converter/16 channel analog
multiplexer. Additional provisions have been included to
allow further analog expansion if desired. Figure 1 is a block
diagram of the MDX-A/D8 showing the major elements of
the module.

The other half of the MK50816 is the AID converter. The
8-bit AID consists of 256 series resistors with an analog
switch tree, a chopper-stabilized comparator and a
successive approximation register. The series resistor
approach guarantees monotonicity and no missing codes.
The need for external zero and full-scale adjustments has
been eliminated and an absolute accuracy of :::; 1 LSB
including quantizing error is provided. A start convert signal
initiates the conversion process and can be jumper-selected
from either an external source or under program control.
Upon completion, a DONE signal is generated to indicate
end of conversion. This signal is used to flag the program as
well as any external device.

The first element of this board is the multiplexer. This 16channel multiplexer can directly access anyone of 16
single-ended analog channels and provides logic for
additional channel expansion. All analog input lines contain
a diodelresistor protection circuit to reduce potential
damage from overvoltage and transient inputs.

The Data Bus Buffer and Interface Logic allows the MDXAIDS module to interface with the STD-ZSO BUS. It
provides buffering for all signals as well as address
decoding and AID port control. A total of four port address
locations are required and can start on any four-word
boundary.

o 4M Hz option
DESCRIPTION

V-3

MDX-A/DS BLOCK DIAGRAM
Figure 1
DONE

CONVERT
MK50a16

ADDITIONAL
ANALOG
CHANNEL
EXPANSION

MUX
OUT

----,

DATA BUS
BUFFER
AND
INTERFACE
LOGIC

STD-

zao

BUS

IN

CONTROL
16 S.E. ANALOG
INPUTS

AID
DATA

WORD SIZE

INTERRUPTS

Data: 8 bits
I/O Addressing: 8 bits

Vectored interrupts generated. Interrupt vector
programmable upon initialization. Daisy-chained interrupt
priority. Interrupts are controlled by a Mostek MK3881
Parallel I/O controller chip.

I/O CAPACITY
Eight-bit analog-to-digital converter with up to sixteen
single-ended analog input channels. Channel expansion
available. Start"conversion and done-handshake signals
available at the edge connector.

SYSTEM INTERRUPT UNITS (SIU) = 1
SYSTEM CLOCK

I/O ADDRESSING

MDX-A/D
MDX-AlD-4

On-board programmable on 4-word boundaries
X X X X X X 0 0 AID Port Configuration Data
X X X X X X 0 1 A/D Port Configuration Control
X X X X X X 1 0 AID Data Input/Output Port
X X X X X X 1 1 Data Control Port

MIN.
250kHz
250kHz

MAX.
2.5 MHz
4.0 MHz

STD BUS INTERFACES
Inputs:
Outputs:

X = don't care

CONVERSION TIME

One 75LS Load
10H = -3mA min. at 2.4 Volts
10L = 24mA max. at 0.5 Volts

OPERATING TEMPERATURE RANGE

138 microseconds max.

V-4

POWER SUPPLY REQUIREMENTS

CONNECTORS

+S Volts ±S% at 0.6 A max.
CARD DIMENSIONS

Function

Configuration

STO-ZSO BUS

S6-pin
0.12S-in. centers

4.S in. (11.43cm) high by 6.S0 in. (16.S1 cm) long
O.4S in. (1.22cm) maximum profile thickness
0.062 in. (0.16cm) printed-circuit-board thickness

Mating
Connector
PRINTED CIRCUIT
Viking
3VH2S/1CES
WIRE WRAP
Viking
3VH2S/1 CNDS
SOLDER LUG
Viking
3VH2S/1CNS

Analog 1/0

40-pin
0.100 in. centers

Ansley 609-4000

ORDERING INFORMATION
DESIGNATOR

DESCRIPTION

PART NO.

MDX-A/DS

Module with Operation Manual less mating connector
2.S MHz version

MK77669-0

MDX-A/DS-4

Module with Operation Manual less mating connector
4.0 MHz version

MK77669-4

MDX-A/DS Operations Manual Only

MK79632

V-5

'1.-6

MOSTEl(.
MD SERIES liD CARDS

MDX-AIO
MK77654
FEATURES

MDX-AIO BOARD PHOTO

o STD and STD-Z80 BUS compatible
o Memory-mapped 1/0
o Combination Analog Input and Output
o 8 Differential Analog Inputs or 16 Single-Ended Analog
Inputs
o Two channels of 8-bit Analog Output
o Input overvoltage protection to

± 35 volts

o Sample-and-Hold Amplifier On-Board
o Monolithic 10-Bit AID Converter
o Single On-Board Precision Reference Circuit
o Single +5-Volt Supply

DESCRIPTION
The MDX-AIO Analog Data Acquisition and Control Board
comprises a complete analog 1/0 subsystem which
simplifies the interface of real-time analog signals to MD
Series microcomputer systems.
The analog signals are connected to the board through a pin
connector mounted at the opposite board edge from the
digital bus. The MDX-AIO comes complete with its own
DCIDC converter so that the board can operate directly
from the +5 volt supply.

The MDX-AIO has eight differential or 16 single-ended
input capability while also providing for two channels of
analog output with 8-bit resolution. The board also features
input overvoltage protection to ± 35 volts. A Sample-andHold Amplifier is contained on the board along with a 10-bit
AID converter.
The MDX-AIO operates as a memory-mapped 1/0 system.
Each board can be configured as a block of five contiguous
memory locations, as shown in Table 1.

V-7

MDX-AIO BLOCK DIAGRAM
ANALOG INPUTS

STD
DR
STDZSO
BUS

DATA
BUS

DACO
OUTPUT

DAC1
OUTPUT

B

TO
REGISTER
AND
OUTPUT r-----L.L-~
STROBES

CONTROL
BUS

-15V +5V

RESET
EDC/BUSY

ENABLE

ADDRESS1_6~==A=D=D=R=E=S=S==B=U=S==~~::::~
BUS
...,

+15V

+5V

MEMORY MAP OF MDX-AIO
Table 1
BYTE FORMAT
BYTE
ADDRESS

~
X F X B

~---------------~---------------~

~SB

BO

~~

B1

B2

B3

B4

B5

B6

BYTE FUNCTION

,...

87
/

" " " "
" " " " "
MO

M1

06

07

X F X C

O2

X F X 0

BUSY

X F X E

MSB

DACO DATA

X F X F

MSB

DAC 1 DATA

03

04

05

M2

M3

MUX AD DR & CONV. CMD

,

OPERATION

~
WRITE

Os

LSB

LOWER ADC DATA BYTE

READ

MSB

01

STATUS & UPPER ADC
DATA BYTE

READ

'"

LSB

DAC 0 DATA BYTE

WRITE

DAC 1 DATA BYTE

WRITE

LSB

NOTES:
1. "X" HEX address digits are user-selectable.
2. " bits are ignored on write and indeterminate on read.

3. Busy bit is "1" during conversions and "0" when done.
4. Writing the MUX number to location XFXB sets the input
channel and initiates a conversion.

v-a

ANALOG INPUT SECTION
(All accuracy specifications typical at +25°C with ± 10V
FSR unless otherwise noted)
Input Channels
Input Protection
Input Range
Input Impedance
Instrument Amplifier
Gain
Input Bias Current
CMV Range
CMRR@60Hz
ADC Resolution
Conversion Time
Monotonicity
Overall System Error
Offset Error
Gain Error
Noise Error RTI
Nonlinearity
Offset Drift
Gain Drift

STD BUS INTERFACE
Inputs:
Outputs:

16 Single-Ended or 8 Differential
±35V
OV to 10V. ± 5V. ±10V
100M 11 min.

OPERATING TEMPERATURE RANGE
O°C to +60°C
5% to 95% R.H. without Condensation
25 to 32 inches of Mercury

1VIV
50nA
±10V
60dB min.
10 Bits
40 microseconds
Guaranteed 0 to 50°C
±0.15% F.S.R.
Adjustable to Zero
Adjustable to Zero
±%LSB
± 1LSB max.
50ppm/oC
100ppm/oC

STORAGE TEMPERATURE RANGE

POWER SUPPLY REQUIREMENTS
+5 volts ±5% at 750 rnA max.

CARD DIMENSIONS
4.5 in (11.43 cm) high by 6.50 in. (16.51 cm) long
0.48 in. (1.22 cm) max. profile thickness
0.062 in. (0.16 cm) printed-circuit-board thickness

ANALOG OUTPUT SECTION
(All accuracy specifications typical at +25°C with ± 10V
FSR unless otherwise noted)
Output Channels
Resolution
Output Ranges
Output Current
Settling Time (20V Step)
Monotonicity
Nonlinearity
Offset Error
Gain Error
Offset Drift
Gain Drift

CONNECTORS

2
8 Bits
OVt010V.±5V.±10V
5mA@±10V
30 microseconds to ±%LSB
Guaranteed 0 to +50°C
±%LSB max.
Adjustable to Zero
Adjustable to Zero
30 microseconds V/oC
50ppm/oC

SYSTEM INTERRUPT UNITS (SIO)

Function

Configuration

STD-Z80 BUS

56 pin
0.125 in. centers

PRINTED CIRCUIT
Viking
3VH28/1CE5

SOLDER LUG
Viking
3VH28/1CN5

=0
A nalog 1/0

MAX

MIN
250kHz

Mating
Connector

WIRE WRAP
Viking
3VH28/1 CND5

SYSTEM CLOCK

MDX-AIO

One 74LS Load
10H = -3 rnA min. at 2.4 volts
10L = 24 rnA min. at 0.5 volts

34-pin

3M Type Ribbon
Cable Connector
ADI PIN AC1562

4.0MHz

ORDERING INFORMATION
DESIGNATOR

DESCRIPTION

PART NO.

MDX-AIO

Module with Operation Manual less
mating connectors.

MK77654

MDX-AIO Operations Manual only

MK79775

V-9

V-10

MOSIEI{.
MD SERIES liD CARDS

MDX-A/D12
MK77655-0
FEATURES

MDX-A/D 12 BOARD PHOTO

o STD-Z80 BUS compatible
o 12-bit AID Converter
o 16 Single-Ended.or Eight Differential Input Channels
o Sample and Hold
o Two Analog Input Ranges
± 5 Volts, 0 to 5 Volts
o Provisions for input channel expansion
o Address programmable

DESCRIPTION
The Analog-to-Digital Converter Family, MDX-AlD12,
encompasses five different modules, each of which has
different input ranges. The boards allow for high-level, wide
range, and wide range isolated inputs.
The MDX-AlD12 board provides 16 single-ended or eight
differential input channels. It also has the capability for
expansion up to 64 single-ended or 32 differential input

channels. The full-scale input ranges are ± 5 volts or 0 to 5
volts. These are jumper-selectable. Throughput for this
module is 33 microseconds.

V-11"

MDX-A/D12 BLOCK DIAGRAM

EN

READ AID DATA

ADR BUS

ANALOG
INPUTS

EN
GAIN
SELECT
STD

zao

CONTROL
LINES

zao

DATA
ACQUISITION
MODULE

PIO

BUS
INT.

} EXPANSION
CONTROL

DATA
DRIVER

DATA

110 ADDRESSING

ANALOG INPUT PARAMETERS
Number of Channels: 16 single-ended or eight differential
ijurnper selectable)

On board, upper five bits programmable
INTERRUPTS

Input Impedance: 100 megohm
Sample-and-Hold APerature Uncertainty: 10 nanoseconds
Conversion Resolution: 12 bits
Inherent Quantizing Error: ± 1/2 LSB

Vectored interrupts generated. Interrupt vector programmable upon initialization. Daisy-chained interrupt
priority. Selected bit channels can be masked out under
program control.
SYSTEM INTERRUPT UNITS (SIU)

=1

Stability: ± 25ppm/oC FSR
SYSTEM CLOCK
Linearity:

± 112 LSB

Analog-Input-System Accuracy:

± 0.03% FSR

MDX-A/D12 Family

MIN

MAX

250 kHz

2.5 MHz

Throughput: 33 microseconds
DIGITAL PARAMETERS

STD BUS INTERFACE

WORD SIZE

Inputs:
Outputs:

Data: 8 bits
1/0 Addressing: 8 bits

V-12

One 74LS Load max.
10H = -3 rnA min. at 2.4 Volts
10L = 24 mA min. at 0.5 volts

OPERATING TEMPERATURE RANGE

CONNECTORS

O°C to 60°C
POWER SUPPLY REQUIREMENTS

Function

+5V ± 5% at 500mA
+ 12V ± 5% at 75mA

Configuration

STD-Z80 BUS 56-pin
0.125 in. centers

CARD DIMENSIONS

Mating
Connector
PRINTED CIRCUIT
Viking
3VH28/1CE5
WIRE WRAP
Viking
3VH28/1 CND5

4.5 in. (11.43cm) high by 6.50 in. (16.51cm) long
0.48 in (1.22cm) maximum profile thickness
0.062 in (0.16cm) printed-circuit-board thickness

SOLDER LUG
Viking
3VH28/1CN5
*ANALOG
CONN

20-pin

3M type 3421

*MDX-A/D12 may have up to two 20-pin 3M-type
connectors. Connector J1 is used for connection of analog
input signals and EXT TRIG INPUTS. Connector J2 is used
for multiplexer channel expansion.

ORDERING INFORMATION

DESIGNATOR

DESCRIPTION

PART NO.

MDX-AlD12

High-Level 12-bit. 16-channel SE (8 channel DI)
AID. Less mating connector with Operations Manual.

MK77655-0

MDX-AlD12 Operations Manual Only

MK79774

V-13

V-14

MOSTEl{.
MD SERIES liD CARDS

MDX-D/AS
MK77666-0
FEATURES

DESCRIPTION

o STO-Z80 and STO BUS compatible

Designed as a part ofthe MO Series Analog 1/0 systems,
the MOX-OIA8 features four completely independent
analog output channels. Each channel has user-selectable
output ranges of ± 5V and 0 to 5V.

o 8 Bit 01A Converter
o Four independent channels
o Output voltage ranges of ± 5V, 0 to 5V, ± 10V, 0 to 10V
o Output current range of 4 to 20 mA
o 15V optional models available
o Programmable address

The MOX-OIA8 can be used as either a memory-mapped
peripheral or as an liD port through a user-selectable
jumper option. When used in the memory-mapped
environment, the device base address can be assigned any
value in the 8000H to FFF8H memory address space. When
used as an liD port, the base port address can be assigned
any address in the OOOOH to 00F8H liD port address space.

o 2.5 and 4.0MHz Operation

V-15

MDX-D/A 8 BLOCK DIAGRAM.
D/A1
BUFFER'
REG

DATA 1

~4-20mA

>-----'-_ D/A OUT 1

DATA 2
LDDAC1

4-20mA

ADDR~

STD·
BUS

SELECT,
JMPRS

4-20mA

WR

4-20mA

LDDAC4

+v

0

>

Wi t>

.---+------.... EXT REFIN.
~R~E~F_ _L__~]
~ REF OUT

-

ANALOG OUTPUT PARAMETERS

WORD SIZE

Resolution: 8 bits

Data: 8 bits
1/0 Addressing: 8 bits

No. of Channels: 4
Linearity:

± Y2 LSB

110 ADDRESSING OR MEMORY ADDRESSING

±0.2% FSR
On-board programmable
Differential Linearity:

±

112 LSB
SYSTEM CLOCK

Gain and Offset Error: Adjustable to Zero
Gain Drift:

± 60 PPM/oC
MDX- D/A8

Offset Drift:

MIN.

MAX.

250kHz

2.5 MHz

± 10 PPM;oC unipolar
± 30 PPM/oC bipolar
SYSTEM INTERRUPT UNITS (SIU)

=0

Settling Time: 35 microseconds to 0.01 % FSR (1 O-volt step)
Slew Rate: 0.33V/microsecond
Output Voltage Range:

.

± 5V. 0 to 5V (MDX-DIA 8)

STD BUS INTERFACE
Inputs:
Outputs:

DC Output Impedance: < 0.1 ohm
V-16

One 74LS load max.
10H = -3 rnA min. at 2.4 volts
10L = 24 rnA max. at 0.5 volts

OPERATING TEMPERATURE RANGE

CONNECTORS

O°C to 60°C
Mating
Connector

POWER SUPPLY REQUIREMENTS

Function

Configuration

+5V ± 5% at 550 mA
± 15V or ± 12V ± 5% at 50 mA and load current

STD-Z80 BUS

56-pin

PRINTED CIRCUIT

0.125 in. centers

Viking 3VH281

CARD DIMENSIONS

1CE5

4.5 in. (11.43 cm) high by 6.50 in. (16.51 cm) long
0.48 in. (1.22 cm) maximum profile thickness
0.062 in. (0.16 cm) printed-circuit-board thickness

Viking 3VH281

WIRE WRAP
1CND5
SOLDER LUG
Viking 3VH281
1CN5
ANALOG
CONN

20-Pin

3M type 3421

ORDERING INFORMATION

DESIGNATOR

DESCRIPTION

PART NO.

MDX-D/A8

4-Channel 8-bit DI A converter with manual less mating
connector

MK77666

MDX-DI A8 Operation Manual Only

MK79824

V-17

V-18

MOSTEI{.
MD SERIES I/O CARDS

MDX-D/A 12
MK77665-0
FEATURES

DESCRIPTION

o

STO-Z80 BUS compatible

o

12-bit 01 A converter

Designed as a part of the MO Series Analog liD systems,
the MOX-OI A 12 features four completely independent
analog output channels. Each channel has users-selectable
output ranges of±5VandOto 5V. The MOX-OI A 12 can be
used as either a memory-mapped peripheral or as an liD
port through a user-selectable jumper option. When used in
the memory-mapped environment, the device base address
can be assigned any value in the 8000H to FFF8H memory
address space. When used as an I/O port, the base port
address can be assigned any address in the OOOOH to
OOF8H liD port address space.

o Four independent channels

o

Output voltage ranges of ±5V, 0 to 5V, ±10V, 0 to 10V

o

Programmable address

o

Both 2.5MHz and 4.0MHz

V-19

MDX-DI A 12 BLOCK DIAGRAM
D/A 1
BUFFER
REF

DATA 1

~--------~D/AOUT1

DATA 2
LDDAC1

ADDRESS
ADDRESS LINES DECODER

~0~ S~~~~~

OR
STD
Z80
BUS

JMPERS

~+-------.

LDDAC 1

DI A OUT 2

LDDAC2
LDDAC3
ADDRESS
LDDAC 4
SELECT LDBUF 4 BIT
BUFFER REG

>-+-------. DI A OUT 3

WR

DATA

>--t------. DI A OUT 4
LDDAC4

~

>V-

r----+---- EXT REF IN.

[>

r

....;R..:;:E:;"F_L_--l-

.

>-

ANALOG OUTPUT PARAMETERS

DIGITAL PARAMETERS

Resolution: 12 bits

WORD SIZE

No. of channels: 4

Data: 8 bits
1/0 Addressing: 8 bits

..

REF OUT

Output Voltage Range: ±5V. 0 to 5V
1/0 ADDRESSING OR MEMORY ADDRESSING
Linearity: ±112 LSB
±0.02% FSR

On-board programmable

Differential Linearity: ±112 LSB

INTERRUPTS

D.C. Output Impedance: < 0.1 ohm

No interrupts are generated

Gain and Offset Error: Adjustable to zero

SYSTEM INTERRUPT UNITS (SIU) = 0

Gain Drift: ±30 ppm/oC
SYSTEM CLOCK

Offset Drift: ±3 ppm/oC unipolar
±18 ppm/oC bipolar
Settling Time: 35 microseconds to 0.Q1 % FSR (1 0 volt step)
Slew Rate: 0.33 VI microsecond

MDX-D/A 12

V-20

MIN

MAX

250kHz

2.5MHz

CONNECTORS

STD BUS INTERFACE
Inputs:
Outputs:

One 741-S load max.
IOH = -3mA min. at 2.4 Volts
IOL = 24mA min. at 0.5 Volts

OPERATING TEMPERATURE RANGE

Function

Configuration

STD-Z80 BUS 56-pin
0.125 in. centers

Mating
Connector
PRINTED CIRCUIT
Viking 3VH281
1CE5
WIRE WRAP
Viking 3VH281
1CND5

O°C to 60°C
POWER SUPPLY REQUIREMENTS

SOLDER LUG
Viking 3VH281
1CN5

+5V ±5% at 550mA
CARD DIMENSIONS
4.5 in (11.43cm) high by 6.50 in. (16.51cm) long
0.48 in (1.22cm) maximum profile thickness
0.062 in (0.16cm) printed-circuit-board thickness

ANALOG
CONN

20-pin

3M type 3421

ORDERING INFORMATION
DESIGNATOR

DESCRIPTION

PART NO.

MDX-D/A 12

4-channel 12-bit DI A converter with manual
less mating connector.

MK77665-O

MDX-DI A 12 Operation Manual Only

MK79824

V-21

V-2~

MOSlEI{.
MD SERIES liD CARDS

MDX-FLP
MK77652-0
FEATURES

MDX-FLP BOARD PHOTO

o STD-ZSO BUS compatible
o One to four drives; four software-controlled select lines
.D 5-inch or S-inch drives, single-or dual"sided, jumperselectable. All drives connected to one MDX-FLP board
must be the same type

o Single-density operation
o Soft-sector operation including variable-length sectors
o Compatibility with IBM 3740 or ot~er formats
o Single-sector, multi-sector or full-track data transfers
o Automatic track seek with verification capability
o Diskette initialization/formatting capability
o Software-programmable step rate, head settling and
engage times
o DMA or programmed data transfer
o Interrupt-driven or polled operation
o Automatic CRC checking and generation on read and
write operations.
oS-inch drives supported under FLP-SODOS and MITE-SO
software; 5-inch drives under MITE-SO

DESCRIPTION
The single MDX-FLP board provides all required
controlling/formatting/interfacing logic between the STDtso BUS and one to folir floppy disk drives. The board is
based upon an LSI controller chip andMK3SS3 DMA
controller.

The MDX-FLP module is compatible with the'following
floppy disk drives.
Siemens FDb 1OO-S, 200~S, 100C, 200C.
Shugart Associates SASOO, SASSO, SA400, SA450.
Pertec FD600, FD650, FD200; FD250.
"
Memorex 550, 552.

o ,Port addresses jumper-selectable to ,a block of eight
anywhere in, the address space
o 2.5 MHz operation (system clock)
o Provision for DMA daisy chain operation (simultaneous
operation of multiple DMA devices requires on-board
jumper and backplane modification)

,"

and with any equivalent drive which utilizes the signals
shown hi' Table 1. (All signals are TTL; directions are
referenced to the board.)

V-23

BLOCK DIAGRAM
DRIVE/SIDE
SELECT
LATCHES

STD-.
Z80
BUS

BUS
INTERFACE
AND
COMMAND
DECODE

...

.....

DRIVE
INTERFACE

MK3883DMA
CONTROLLER

....

.

...,.

flOPPY
DRIVE(S)

LSI FLOPPY
DISK
CONTROLLER

PORT UTILIZATION
Table 2

FLOPPY DISC INTERFACE SIGNALS
Table 1
Signal

Direction

MDX-FLP Pin

Drive Select
1,2,3,4
Side Select
Step
Write Data
Write Gate
Direction
Head Load
Read Data
Index
Track 0
Write Protect
Drive Ready

Out

26,28,30,32

Out
Out
Out
Out
Out
Out
In
In
In
In
In

.14 and 16
36
38
40
34
18
46
24(5") or 20 (8")
42

A2

A1

AO

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

DMA Controller
Unused
Board Status
Drive Selection
Controller CommandlStatus
Track Register
Sector Register
Data Register

WORD SIZE

44

Data: 8 bits
1/0 Addressing: 8 bits

22

The MDX-FLP boardwill work with 5-inch or 8-inch singleor dual-sided, single-density drives; however, 5- and 8-inch
drives may not be driven by the same board.

1/0 ADDRESSING
On-board programmable - See Table 2.

MICROPROCESSOR INTERFACE
Connector, signals, and pinouts are STD-Z80 BUS
compatible. With the addition of jumper E16, the Bus
Acknowledge Out Signal is presented at pin 40 (STATUS 0)
for DMA daisy-chain operation.

INTERRUPTS
Vectored interrupts generated. Interrupt vector programmable upon initialization. Daisy chained interrupt
priority.

PORT MAP
Jumpers E9 through E13 select the high-order port address
on A7-A3 to which the board will respond. Thus the board
uses a block of eight contiguous port addresses, which are
arranged for maximum compatibility with FLP-80DOS. Port
utilization is as shown in Table 2.

SYSTEM INTERRUPT UNITS (SIU) = 1

SYSTEM CLOCK

MDX-FLP

V-24

MIN
250kHz

MAX
2.5MHz

STD BUS INTERFACE
Inputs
Outputs

CONNECTORS

One 74LS Load Max.
IOH = 3 mA min. at 2.4 volts
IOH = 24 mA min. at 0.5 volts
Configuration

POWER SUPPLY REQUIREMENTS

Function

+5 volts ± 5% at 1.2A max.
+12 volts ± 5% at 1OmA max.
-12 volts ± 5% at 4mA max.

STD-Z80 BUS 56-pin

Mating
Connectors
PRINTED CIRCUIT
Viking 3VH281
lCE5

OPERATING TEMPERATURE RANGE
0.125 in. centers

O°C to 60°C
CARD DIMENSIONS
4.5 in. (11.43cm) high by 6.50 in. (16.51 cm) long
0.48 in. (1.22cm) maximum profile thickness
0.062 in. (0.16cm) printed-circuit-board thickness

WIRE WRAP
Viking 3VH281
lCND5
SOLDER LUG
Viking 3VH281
lCN5

Drive Interface 50-pin
0.100 in. centers

Ansley 6095000M
w/o strain relief
Ansley 6095001M
with strain relief

ORDERING INFORMATION

DESIGNATOR

DESCRIPTION

PART NO.

MDX-FLP

Module with Operation Manual less mating
connectors. 2.5MHz version

MK77652-0

MDX-FLP Operations Manual Only

MK79639

V-25

V·26

MOSTEl{.
MD SERIES 1/0 CARDS

MDX-PIO
MK77650-0, MK77650-4
FEATURES
o STO-l80 BUS compatible
o Four 8-bit I/O ports with two handshake lines per port
o All I/O lines fully buffered
o 110 lines TIL-compatible with provision for termination
resistor networks
o Jumper options for inverted or non-inverted handshake
o Two 8-bit ports capable of true bidirectional I/O
o Programmable In oQly, Out only, or Bidirectional
o Output data buffers selectable to provide inverted or
non-inverted drive capability
o Interrupt-driven programmability
o Address strap-selectable
o 4 MHz option
PIO, and address decode and data bus buffers. Input and
output from the ports are provided through J1, a 26-pin
connector. This connector provides data paths for the two
ports and their respective handshake signals.

o Fully buffered for MO Series expandability
DESCRIPTION
The parallel I/O controller (MOX-PIO) is a highly versatile
unit designed to provide a variety of methods for inputting
and outputting data from the MO Series microcomputer
system. The system is designed around two Mostek
MK3881 l80-P10 parallel I/O controllers which give four
independent 8-bit I/O ports with two handshake (data
transfer) control lines per port. The l80-PI0's are
designated PI01 and P102. Each has an 110 port pair
designated A and B. Each port pair of each PIO have similar
output circuitry.
All 110 lines are buffered and have provisions for
termination resistors on board. All port lines are brought to
two 26-pin connectors, two ports per connector.
Figure 1 illustrates in block diagram form the major
functional elements of port pair A and B of P101. These
elements can be defined as the resistor termination
networks, data buffers, port configuration control, MK3881

One 14-pin socket is provided per port for resistor dual
inline packages so that terminations may be placed on the
data lines. A parallel termination is provided for each 8-bit
port data line plus the input strobe (STB) handshake line.
The MOX-PIO is normally shipped with 1 K pullup
terminators. In addition to the parallel termination resistors,
the ready (ROY) handshake output line is series-terminated
with a 470 resistor. This is used to damp and reduce
reflections on this output line.
Port A and B data bus lines are buffered using quadruple
non-inverting transceivers. The buffers can be configured
using port configuration jumpers to provide fixed Input, fixed
Output or Bidirectional (Port A only) signals. Further, the
transceivers are configured such that port direction can be
selected in 4-bit sections. The transceivers are mounted in
sockets so that they can be easily replaced with their
complements in order to achieve a polarity change if
desired.

V-27

MDX-PIO BLOCK DIAGRAM FOR PIOl (PI02 IS IDENTICAL)
Figure 1
4711

ROY

PORTA

AOORESS
OECOOE
AND
DATA BUS
BUFFERS

MK3aa1
PI01

CONTROL (9)

PORTa

4711

The handshake lines are also fully buffered. The port
configuration control provides jumper options to
independently control the polarity or "sense" of each
handshake line so as to further ease the interfacing
between the MDX-PIO and peripheral devices.

MDX-PIO ADDRESSES
Table 1

The MK38a1 PIO is the heart of the module. This circuit is a
fully-programmable two-port device which provides a wide
range of configuration options. Anyone of four distinct
modes of operation can be selected for a port. They are byte
output, byte input, byte bidirectional (Port A only), and bit
control mode. The PIO also automatically generates all
handshaking signals in all the above modes.

Data
Control

The PIO permits total interrupt control so that full usage of
the zao interrupt capabilities can be utilized during I/O
transfers. Also, the PIO can be programmed to interrupt the
CPU on the occurrence of a specified status condition in a
specific peripheral device. The PIO circuit will provide
vectored interrupts and maintain the daisy chain priority
interrupt logic compatible with the STD-ZaO BUS.
The address decoding, interface and bus management for
the board are performed by the address decode and data
bus circuit. Each MDX-PIO port has two addresses, one for
Control and one for Data. A total of eight addresses are
utilized per board. These addresses are defined in Table 1.

PORT A

Pial
PORT B

XXOa
XX1a

XX2a
XX3a

PI02
PORT A PORT B
XX4a
XX5a

XX6a
XX7a

The XX symbols stand for the upper five bits of the I/O
channel address. These bits are jumper-selectable on the
MDX-PIO board in orderto provide address-selectable fullydecoded ports.
The circuitry for the other two ports provided by PI02 is
identical to P101. The port configuration logic, buffers,
termination and pin out on connector J2 is duplicated for
P102. These two ports share the address-decode and databus-buffer circuitry with P101. The only differences are in
the address decoding as given in the port address table, and
PI02 is lower priority in the daisy-chain interrupt structure.
WORD SIZE
Data: a bits
I/O Addressing: a bits

V-28

1/0 ADDRESSING

INTERRUPTS

On-board programmable - See Table 1

Vectored interrupts generated. Interrupt vector
programmable upon initialization. Daisy-chained interrupt
priority. Selected bit channels can be masked out under
program control.

I/O CAPACITY
Four parallel 8-bit ports. On-board jumper, selectable in
4-bit bytes as either In only, Out only, or Bidirectional (Port
lA or 2A only). Automatic handshake provided with each
port.

SYSTEM INTERRUPT UNITS (SIU)
SYSTEM CLOCK

1/0 DRIVERS
Table 2 lists the pin-compatible 110 drivers which can be
used in the MDX-PIO.

Type

Output

Sink
Current (rnA)
24

250kHz
250kHz

2.5 MHz
4.0 MHz

OPERATING TEMPERATURE RANGE
O°C to 60°C

24

Inverting
Tri-State
Bidirectional

POWER SUPPLY REQUIREMENTS
+5 volts

1/0 Ports 1 B *74LS243 Non-Inverting
and 2B
Tri-State
Bidirectional

24

74LS242 Non-Inverting
Tri-State
Bidirectional

24

74LS86

8

Handshake:
RDY

MAX.

One 74LS Load max.
10H = -3mA min. at 2.4 Volts
10L = 24mA min. at 0.5 Volts

Inputs:
Outputs:

1/0 Ports lA *74LS244 Non-Inverting
and 2A
Tri-State
Bidirectional
74LS241

MDX-PIO
MDX-PI0-4

MIN.

STD BUS INTERFACE

1/0 DRIVERS
Table 2
Signals

± 5% at 1.1 A

max.

CARD DIMENSIONS
4.5 in. (11.43cm) high by 6.50 in. (16.51 cm) long
0.48 in. (1.22cm) maximum profile thickness
0.062 in. (0.16cm) printed-circuit-board thickness
CONNECTORS

Inverting/NonInverting (strap
selectable)

Configuration

STD-Z80 BUS

56-pin

PRINTED CIRCUIT
Viking 3VH281
lCE5

0.125 in. centers

WIRE WRAP
Viking 3VH281
lCND5

TERMINATORS

SOLDER LUG
Viking 3VH281
lCN5

1k ohm resistors on all 1/0 port lines.

+5

Parallel 1/0
1kfl
'\IV\;

=JD

•

26-pin
0.100 in. centers

FLAT RIBBON
Ansley 6092600M
DISCRETE WIRES
Winchester
PGB26A
(housing)
Winchester 10070020S (contacts)

0

74LS86
47fl
'\IV\;

Mating
Connector

Function

*These devices are supplied with the board. They may be
exchanged with the other unit listed to provide the alternate
signal polarity.

I

=2

ARDY
orGRDY

V-29

ORDERING INFORMATION
DESiGNATOR DESCRIPTION

PART NO.

MDX-PIO

Module with Operation Manual less mating connectors
(2.5MHz verslqn).

MK77650-0

MDX-PIO-4

Module with Operation Manual less mating connectors
(4.0 MHz version).

MK77650-4

MDX-PIO Operations Manual only

MK79606

V-30

MOSTEI(.
MD SERIES I/O CARDS

MDX-SIO
MK77651-0, MK77651-4
FEATURES

o

STO-Z80 BUS compatible

o

Two independent full-duplex channels

o

Independent programmable Baud-rate clocks

o

Asynchronous data rates-11 0 to 19.2k bits per second

o

Receiver data registers quadruply-buffered

MDX-SIO BOARD PHOTO

o Transmitter data registers double-buffered
o Asynchronous operation
o Binary synchronous operation
o HOLC or SOLC operation
o Both CRC-16 and CRC-CCITT (-0 and -1) hardware
implemented
o Modem control
o Operates as OTE or OCE
o Serial input and output as either RS-232 or 20mA
current loop
o Current loop optically isolated
o Current loop selectable for either active or passive mode
o Address programmable
o 4 MHz option
DESCRIPTION

virtually any other serial protocol. It can generate CRC codes
in any synchronous mode and can be programmed by the
CPU for any traditional asynchronous format. The serial
input and output data are fully buffered and are provided at
the connector as either 20mA current loop or RS-232-C
levels. A modem control section is also provided for
handshaking and status. The MOX-SIO module can be
jumper-configured as a data terminal (OTE) or as a modem
(OCE) in order to facilitate a variety of interface
configurations.
Figure 1 is a block diagram of the MOX-SIO module. It
consists of five main elements. They are the channel
configuration headers. line drivers and receivers. MK3884
Z80-SI0. programmable baud-rate generators. and address
decode and data bus buffers. Input and output to the board
is provided via two 26-pin connectors. One connector is
dedicated for each channel.

The Seriallnput/Output Module. MOX-SIO. is designed to
be a multiprotocol asynchronous or synchronous 1/0
module for the STO-Z80 BUS. The module is designed
around the Mostek MK3884 Z80-S10 which provides two
full duplex. serial data channels. Each channel has an
Several features are available as options that are selected
via the channel configuration headers. which are used to
independent programmable baud-rate clock generator to
increase module flexibility. The MOX-SIO is capable of
select the orientation of the data communication interface
handling asynchronous. synchronous. and synchronous
and the mode of the 20mA current loop. The MOX-SIO can
bit-oriented protocols such as Bi-SYNC. SOLC. HOLC and
be selected to act as either a terminal or processor (Oata
V-31

Terminal Equipment-DTE) or as the modem (Data
Communications Equipment-DCE). The header allows
reconfiguration of both data interchange and modem
control signals. This allows increased flexibility necessary to
link different hardware elements in OEM data-link systems
and networks. The module is shipped from the factory wi red
as a DTE interface.
The MDX-SIO has different selectable options forthe 20mA
current loop. Receiver and transmitter functions can be
reconfigured on the module to allow reorientation of these
signals. Also, the receive and transmit circuits can be
selected to function in either an active or passive mode. In
the active mode, the MDX-SIO module provides the 20mA
current source. In the passive mode, the module requires
that the loop current be provided. The latter is the same
mode as that of a Teletype.
An RS-232-C and 20mA current loop interface circuit is
used to provide the necessary level shifting and signal
conditioning between the MK3884 Z80-S10 and the
connector. These line drivers and receivers provide the
correct electrical signal levels, slew rate, and impedance for
interfacing RS-232-C and 20mA current loop
peripherals. Additionally, optical isolation is provided for
both transmit and receive circuits in the 20mAcurrent loop
mode.
The Mostek MK3884 Z80-S10 is the central element of this
module. It is a multifunction component designed to satisfy
a wide variety of serial data communications requirements
in microcomputer systems. Its basic role is that of a serialto-parallel, parallel-to-serial converter/controller, but

within that role it is configured by software programming so
that its function can be optimized for a given serial data
communications application. The MK3884 provides two
independent full duplex channels, A and B.
Asynchronous operation (Channel A and B)
- 5, 6, 7, or 8 bits/character
- 1, 1V2 or 2 stop bits
- Even, odd or no parity
- xl , x16, x32 and x64 clock modes
- Break generation and detection
- Parity. Overrun and Framing error detection
Binary Synchronous operation (Channel A only)
- One or two Sync characters in separate registers
- Automatic Sync character insertion
- CRC generation and checking
HDLC or SDLC operation (Channel A only)
- Automatic Zero Insertion and Deletion
- Automatic Flag Insertion
- Address Field Recognition
- I-Field Residue Handling
- Valid receive messages protected from overrun
- CRC Generation and Checking
The MK3884 also provides modem control inputs and
outputs as well as daisy chain priority interrupt logic. Eight
different interrupt vectors are generated by the SIO in
response to various conditions affecting the data
communications channel transmission and reception.

MDX-SIO BLOCK DIAGRAM
CHANNEL A

RS·232 DATA
AND
MODEM CONTROL

20mA SERIAL
INPUT/OUTPUT

STD·Z80
BUS

ADDRESS
DECODE
AND
DATA BUS
BUFFERS

CHANNEL B
20mASERIAl
INPUT/OUTPUT

RS-232 DATA
AND
MODEM CONTROL

V-32

Address decoding, STD-Z80 BUS interface and bus
management for the module are performed by the Address
Decode and Data Bus circuit. The MDX-SIO contains
command registers that are programmed to select the
desired operational mode. The addressing scheme is as
follows:
XXXXXX 00 Channel A Data
XXXXXX 01 Channel A Control Status

On board upper six bits programmable

SERIAL COMMUNICATION INTERFACE

Signal

XXXXXX 10 Channel B Data
XXXXXX 11 Channel B Control Status
XXXXXX indicates the binary code necessary to represent
which one of the 64 port addresses is selected by on-board
strapping.
Each channel has an individual programmable baud-rate
generator. The x1 multiplier on theZ80-S10 must be used in
the synchronous modes. The x16, x32 or x64 Z80-S10 clock
rate can be specified for asynchronous mode. Table 1
indicates the possible Baud rates available for both
operation modes with the Z80-S10 Data Rate Multipliers.

Transmitted data
Received data
Data Terminal
Ready (DTR)
Request to Send
(RTS)
Clear to Send (CTS)
Carrier Detect

20mA
Loop

RS-232-C

Output
Input

Output
Input
Input/Output
Input/Output
Output/Input
Output/Input

(CDET)

INTERRUPTS
Generates vectored interrupts to eight different locations
corresponding to conditions within both channels. Interrupt
vector location programmable. Daisy-chained priority
hardware interrupt circuitry.

Table 1

SYNCHRONOUS

I/O ADDRESSING

BAUD RATE (HZ)
ASYNCHRONOUS

X1

X16

X32

X64

800
1200
1760
2152
2400
4800
9600
19200
28800
32000
38400
57600
76800
115200
153600
307200

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200

25
37.5
55
67.25
75
150
300
600
900
1000
1200
1800
2400
3600
4800
9600

12.5
18.75
27.50
33.63
37.50
75
150
300
450
500
600
900
1200
1800
2400
4800

SYSTEM INTERRUPT UNITS (SIU) = 1
SYSTEM CLOCK

MDX-SIO-O
MDX-SIO-4

MIN.

MAX.

250kHz
250kHz

2.5 MHz
4.0 MHz

STD BUS INTERFACE
Inputs:
Outputs:

One 74LS load max.
IOH = -3mA min. at 2.4 Volts
IOL = 24mA min. at 0.5 Volts

WORD SIZE
Data: 8 bits
I/O addressing: 8 bits

OPERATING TEMPERATURE
O°C to 60°C

I/O CAPACITY
POWER SUPPLY REQUIREMENTS
Serial- Two full duplex serial ports. Channel A iscapable of
synchronous and asynchronous operation. Channel B is
+12 volts ± 5% at 72mA max.
asynchronous only. Special control registers and circuitry to
-12 volts ± 5% at 46mA max.
permit implementation of SDLC, BiSync, MonoSync, HDLC.
+5 volts ± 5% at 650mA max.
Other formats can be programmed on Channel A only.
V-33

CARD DIMENSIONS
4.5 in. (11.43cm) high by 6.50 in. (16.51 cm) long
0.48 in. (1.22cm) maximum profile thickness
0.062 in. (0.16cm) printed-circuit-board thickness
CONNECTORS
Function

Configuration

STO-Z80 BUS

56-pin

Mating
Connector
PRINTED CIRCUIT
Viking 3VH281
lCE5

0.125 in. centers

WIRE WRAP
Viking 3VH281
lCND5
SOLDER LUG
Viking 3VH281
lCN5

Serial 1/0

26-pin
0.100 in. center

FLAT RIBBON
Ansley 6092600M
DISCRETE WIRES
Winchester
PGB26A
(housing)
Winchester
loo-70020S
(contacts)

ORDERING INFORMATION
DESIGNATOR

DESCRIPTION

PART NO.

MDX-SIO

Module less mating connectors with Operations Manual
(2.5MHz version).

MK77651-0

MDX-SIO-4

Module with Operations Manual less mating connectors
(4.0MHz version).

MK77651-4

MDX-SIO Operations Manual Only

MK79608

V-34

MICRO SYSTEMS DATA BOOK

MOSTEI(.
MD SERIES MEMORY CARDS

MDX-DRAM
MK77750-0, MK77754-0, MK77754-4,
MK77752-0, MK77752-4
MDX-DRAM BOARD PHOTO

FEATURES
D STD-Z80 BUS compatible
D Three memory sizes:
8K x 8 (MDX-DRAM8)
16K x 8 (MDX-DRAM16)
32K x 8 (MDX-DRAM32)
D Selectable addressing on 4K boundaries
D 4MHz version available (MDX-DRAM-4)

DESCRIPTION
The MDX-DRAM is designed to be a RAM memory
expansion board for the Mostek MD Series™ of Z80-based
microcomputers. It is available in three memory capacities:
8K bytes (MDX-DRAM8), 16K bytes (MDX-DRAM16), and
32K bytes (MDX-DRAM32). Additionally, the MDXDRAM16 and the MDX-DRAM32 are available in a 4MHz
version. Thus, the designer can choose from the various
options to tailor his add-on dynamic RAM directly to his
system requirements.
any ofthe RAM cards. Memory refresh signals are provided
on the Z80 based MDX-CPU boards.
Address selection is provided on all MDX-DRAM cards for
positioning the 8K, 16K, or 32K of memory to start on any
4K boundary.

The MDX-DRAM8 is designed using Mostek's MK4108,
8, 192-bit dynamic RAM. The MDX-DRAM16 and MDXDRAM32 utilize high-performance MK4116, 16,384-bit
dynamic RAMs which allow4MHz versions ofthese boards
to be offered. No wait-state insertion circuitry is required on

VI-1

MDX-DRAM BLOCK DIAGRAM
MEMORY ARRAY
2.5 MHz
8-MK4108
8Kx8
16Kx 8 16-MK4108
32Kx8 16-MK4116

.~

./ RAS

MEMORY DECODE
&
BUFFER CONTROL

--...

I~

4

CAS

po

......

WRITE

BUFFER

16Kx 8
32Kx8

4.0MHz
8-MK4116
16-MK4116

A

DIN

f~

f

It--

£~~

....

~

MUX

DOUT

87

BUFFER

f~

/\

ADDRESS
CO NTROL
DATA
BUFFER

t

/

llle~

5V

REGULATOR

.....

~,

CONTROL
LINES

~

......

~

I I II
GND+5 +12-12

ADDRESS
BUS

STD-Z80 BUS

WORD SIZE

DATA
BUS

ACCESS TIMES

8 Bits
MEMORY SIZE
MDX-DRAM8 - 8,192 bytes
MDX-DRAM16 - 16,384 bytes
MDX-DRAM32 - 32,768 bytes

System Clock

Memory
Access
Times

MDX-DRAM
2.5MHz
MDX-DRAM-4 4.0MHz

350ns max. 465ns min.
200ns max. 325ns min.

SYSTEM INTERRUPT UNITS (SIU)

Memory
Cycle
Times

=0

ADDRESS SELECTION
SYSTEM CLOCK
Selection of 8K, 16K, or 32K contiguous memory blocks to
reside at any 4K boundary.
MDX-DRAM
MDX-DRAM-4

VI-2

MIN

MAX

1.25MHz
1.25MHz

2.5MHz
4.0MHz

STD BUS INTERFACE

CARD DIMENSIONS

Inputs:
Outputs:

4.5 in. (11.43 cm) high by 6.50 in. (16.51 cm) long
0.48 in. (1.22 cm) maximum profile thickness
0.062 in. (0.16 cm) printed-circuit-board thickness

One 74LS load max.
IOH = -3mA min. at 2.4 volts
IOL = 24mA min. at 0.5 volts

CONNECTORS

OPERATING TEMPERATURE

Function

O°C to 60°C

Configuration

STD-Z80 BUS 56-pin

PRINTED CIRCUIT
Viking 3VH281
ICE5

0.125 in centers
POWER SUPPLY REQUIREMENTS
+5V ± 5% at 0.6A max.
+ 12V ± 5% at 0.25A max.
-12V ± 5% at 0.03A max.

Mating
Connector

WIRE WRAP
Viking 3VH281
1CND5
SOLDER LUG
Viking 3VH281
1CN5

ORDERING INFORMATION

DESIGNATOR
MDX-DRAM8

DESCRIPTION

PART NO.

Module with Operation Manual less mating connectors

MK77750-0

8K Bytes (4108's)

2.5MHz

MDX-DRAM16

16K Bytes (4116's)

2.5 MHz

MK77754-0

MDX-DRAM32

32K Bytes (4116's)

2.5MHz

MK77752-0

MDX-DRAM 16-4

16K Bytes (4116's)

4.0MHz

MK77754-4

MDX-DRAM32-4

32K Bytes (4116's)

4.0MHz

MK77752-4

MDX-DRAM Operations Manual Only

VI-3

MK79624

VI-4

MOSTEI{.
MD SERIES MEMORY CARDS

MDX-EPROM
MK77758
FEATURES

MDX-EPROM BOARD PHOTO

o STD and STD-Z80 BUS compatible

o

Accepts the following industry standard EPROMS:
2758 (1K x 8)
2716 (2K x 8)
2732 (4K x 8)

o

Eight EPROM sockets for maximum storage of:
8K x 8 using 2758's
16K x 8 using 2716's
32K x 8 using 2732's

o

Wait-state generator for 4MHz operation

o

Selectable addressing on 4K boundaries

o

Operates at 2.5MHz or 4.0MHz system speed

o

Single +5 Volt supply

o

8-2716 EPROM's supplied

DESCRIPTION

which gives a maximum storage capacity of 8K, 16K, or 32K
bytes respectively.

The MDX-EPROM is designed to be an EPROM memory
expansion board for the Mostek MD Series™ of Z80-based
microcomputers. The MDX-EPROM accepts the following
EPROMs: 2758 (1 K x 8), 2716 (2K x 8) and 2732 (4K x 8)

VI-5

Starting address selection is provided for positioning the
MDX-EPROM on any 4K boundary. A wait-state generator
is also provided for optional 4MHz operation.

MDX-EPROM BLOCK DIAGRAM

8
MEMORY
DECODE
&
CONTROL
LOGIC

/\

MEMORY ARRAY

~
OE

8-2758
8-2716
8-2732

8Kx8
16Kx8
32Kx8

/\

f\

OE

10

4

8

6

V
CONTROL BUS
BUFFER

ADDRESS BUS
BUFFER

/\

/\

-M
- - RD
EMRQ,

WR. CLciCK

4

iiVAi'i'RQ

~

+5V

GND

t t

16

DATA BUS
BUFFER

8

V

STD-Z80 OR STD-BUS

WORD SIZE

~

REQUIRED ACCESS TIME

8 Bits

MEMORY SIZE

Memory
Time

Min Access
Time

Cycle Time

2758,2716,
2732

450ns*

450ns

8K x 8 using eight 2758's
16K x 8 using eight 2716's*
32K x 8 using eight 2732's

*Onewait state must be added for 4MHz operation.

*Shipped configuration

SYSTEM INTERRUPT UNITS (SIU) = 0
STD BUS INTERFACE

ADDRESS SELECTION

Inputs:
Outputs:

4K boundaries

VI-6

One 74LS load max.
IOH = -3mA min. at 2.4 Volts
IOL = 24mA min. at 0.5 Volts

CONNECTORS

OPERATING TEMPERATURE

Function

POWER SUPPLY REQUIREMENTS

Configuration

STD-Z80 BUS 56-Pin
0.125 in. centers

+ 5 Volts ± 5% at 0.45A*
*Does not include EPROMs. Add 100 mA for each EPROM.

Mating
Connector

PRINTED CIRCUIT
Viking 3VH281
1CE5
WIRE WRAP
Viking 3VH281
1CND5

CARD DIMENSIONS

SOLDER LUG
Viking 3VH281
1CN5

4.5 in. (11.43 cm) high by 6.50 in. (16.51 cm) long
0.48 in. (1.22 cm) maximum profile thickness
0.062 in. (0.16 cm) printed-circuit-board thickness

ORDERING INFORMATION
DESIGNATOR

DESCRIPTION

PART NO.

MDX-EPROM

Module with Operation Manual less mating connectors
Includes eiQht 2716 EPROMs.

MK77758

MDX-EPROM Operations Manual only

MK79671

VI-'

VI-8

MOSIEI(.
MD SERIES MEMORY CARDS

MDX-EPROM/UART
MK77753-0, MK77753-4
FEATURES

MDX-EPROM/UART BOARD PHOTO

D STD and STD-Z80 BUS compatible
D 10K x 8 EPROM/ROM (2716's not included)
D Selectable addressing on 2K boundaries
D Serial I/O channel:

RS - 232 and 20 mA interface
Reader-step control for Teletypes
Baud-rate generator (110-19200 Baud)
D 4MHz version available (MDX-EPROM/UART-4)
D Strap-selectable address

DESCRIPTION
The MDX-EPROM/UART is one of Mostek's complete line
of STD-Z80 BUS-compatible Z80 microcomputer modules.
Designed as a universal EPROM add-on module for the
STD-Z80 BUS, the MDX-EPROM/UART provides the
system designer with sockets to contain up to 10K x 8 of
EPROM memory(5-2716's) as shown in the Block Diagram.

are necessary unless there is a modification of the serial
data format. Features of the UART include:
Full-duplex operation
Start-bit verification
Data word size variable from 5 to 8 bits
One or two stop-bit selection
Odd, even, or no parity option
One-word buffering on both transmit and receive

The EPROM memories can be positioned to start on any 2K
boundary within a 16K block of memory via a strapping
option provided on the MDX-EPROM/UART.
Included on-board the MDX-EPROM/UART is a fully
buffered asynchronous I/O port with a Teletype reader-step
control. The address of the serial port is strap-selectable to
one of 64 locations via six jumpers. A full duplex UART is
used to receive and transmit data at. the serial port.
Operation and UART options are under software control.
Once the unit has been programmed, no further changes

The MDX-EPROM/UART is also available in a 4MHz
version. Circuitry is provided to force one wait-state each
time on-board EPROMs or the UART are accessed.

VI-9

MDX-EPROM/UART BLOCK DIAGRAM

-

ADDRESS AND CONTROL BUS

-

V
(I)

::l
III

Ca: O

~
C

liio~

BUS
INTERFACE
LOGIC

7

MEMORY
SELECTION
LOGIC

V

~

V

7

PORT
SELECTION
LOGIC

EPROM/ROM
SOCKETS (6)

I-

(I)

.

UART

c::>

RS-232
AND
20mA
BUFFERS

-

K

-

.

<::>

20 mA INPUT
OUTPUT AND
READER STEP

P

RS-232
INPUT. OUTPUT
AND.
MODEM CONTROL

DATA BUS

WORD SIZE

1/0 TRANSFER RATE

8 Bits for PROM
5 to 8 Bits for Serial 1/0

110, 300,600,1200, 2400,4800.• 9600, 19200 Baud

MEMORY SIZE

SERIAL COMMUNICATIONS INTERFACE

10K bytes of 2716 memory
(2716's not included)

Buffered For
20mA Current
Loop
RS-232

Signal
MEMORY ADDRESSING
ROM/EPROM
2K blocks jumper-selectable for any 2K boundary within a
given 16K block of the Z80 memory map.
MEMORY SPEED REQUIRED
Memory

Access Time

Cycle TIme

2716*

450ns

450ns

* Single 5-Volt type required

Transmitted data
,
Received data
Reader Step Relay (RSR)

Output
Input
Output
(40mA)

Output
Input

Data Terminal Ready(DTR)
Request to Send (RTS)
Carrier Detect (CDET)
Clear to Send (CTS)
Data Set Ready (DSR)

SYSTEM INTERRUPT UNITS (SIU)

Input
Input
Output
Output
Output

=0

1/0 ADDRESSING
SYSTEM CLOCK
On-board Serial 110 Port
Control Port XXXXXX01
Data Port XXXXXXOO
Modem and Reader Step Control XXXXXX10
XXXXXX represents six strap-selectable address bits

MDX-EPROM/UART
MDX-EPROM/UART-4
VI-10

MIN.

MAX.

250kHz
250kHz

2.5 MHz
4.0 MHz

CONNECTORS

STD BUS INTERFACE
Inputs:
Outputs:

One 74LS Load max.
IOH =-3mA min. at 2.4 Volts
IOL = 24mA min. at 0.5 Volts

Function

Configuration

STO-Z80 BUS 56-pin
0.125 in. centers

OPERATING TEMPERATURE RANGE
O°C to +60°C

Mating
Connector
PRINTED CIRCUIT
Viking 3VH281
1CE5
WIRE WRAP
Viking 3VH281
1CND5

POWER SUPPLY REQUIREMENTS

SOLDER LUG
Viking 3VH281
1CN5

+12 Volts ± 5% at 50 rnA max.
-12 Volts ± 5% at 35 rnA max.
+ 5 Volts ± 5% at 1.2 A max.
Serial 1/0

CARD DIMENSIONS

26-pin
0.100 in. grid

4.5 in. (11.43cm) high by 6.50 in. (16.51 cm) long
0.48 in. (1.22cm) maximum profile thickness
0.062 in. (0.16cm) printed-circuit-board thickness

FLAT RIBBON
Ansley 609
2600M
DISCRETE WIRES
Winchester
PGB26A
(housing)
Winchester
1OO-7OO20S
(contacts)

ORDERING INFORMATION
DESIGNATOR

DESCRIPTION

PART NO.

MDX-EPROM/UART

Module with Operation Manual less EPROMs and mating
connectors (2.5MHz version).

MK77753-O

MDX-EPROM/UART-4

Module with Operation Manual less EPROMs and mating
connectors (4.0 MHz version).

MK77753-4

MDX-EPROM/UART Operations Manual Only

MK79604

VI·"

VI-12

MOSTEI<.

MD SERIES MEMORY CARDS

MDX-SRAM
MK77755, MK77756
MDX-SRAM BOARD PHOTO

FEATURES

o

STD and STD-ZSO BUS compatible

o

Three memory sizes:
4K x S (MDX-SRAM4)
SK x S (MDX-SRAMS)

o

Selectable starting address on 4K boundaries

o 2.5 MHz and 4.0 MHz compatible

o

Single +5 Volt supply

DESCRIPTION
The MDX-SRAM is designed to be a static RAM Memory
expansion board for the Mostek MD Series™ of ZSO-based
microcomputers. It is available in two memory capacities:
4K bytes (MDX-SRAM4) and SK bytes (MDX-SRAMS).
Additionally, all MDX-SRAM boards are 2.5MHz and
4.0MHz compatible. Thus, the designer can choose from
two options available and tailor the add-on static RAM
directly to the system requirements.
The MDX-SRAM is designed using the state-of-art
MK411S (1 K x S) static RAM memory devices. No wait

states are necessary for operating the MDX-SRAM at
2.5MHz or 4.0MHz. Address selection is provided on all
MDX-SRAM cards for positioning the 4K or SK of memory
to start on any 4K boundary.

VI-13

MDX-s'RAM BLOCK DIAGRAM

8
MEMORY
DECODE
&
CONTROL
LOGIC

.)

MEMORY ARRAY

CS

4Kx8
8Kx8

OE

4-MK4118
8-MK4118

~
.......

WRi'i'E
t---

/\

(,~

(t

4

8

6

I

I

:r

~

I
CONTROL
BUS
BUFFER

ADDRESS
BUS
BUFFER

--j\~
MEMRQ
iID

,/\r-

/\

, 1/

4

+51

WAi'i'Ril

WR
·CLOCR

DATA
BUS
BUFFER

OE

~

!t

8

'7
~

~

i

STD BUS OR STD-Z80 BUS

SYSTEM INTERRUPT UNITS. (S.IU) = 0

WORD SIZE
S Bits

STD BUS INTERFACE

MEMORY SIZE

Inputs:
Outputs:

MDX-SRAM4 - 4,096 Bytes
MDX-SRAMS - S,192 Bytes

ADDRESS SELECTION

One 74LS load max.
IOH =-3mA min. at 2.4 Volts
IOL = 24mA min. at 0.5 Volts

OPERATING TEMPERATURE

Selection of 4K or SK contiguous memory blocks to begin on
any 4K boundary.
TIMING
POWER SUPPLY REQUIREMENTS

MDX-SRAM

Memory
Access

Memory
Cycle

250ns max.

250ns min.

VI-14

Boards

Current at +5V

MDX-SRAM4
MDX-SRAMS

O.SAmax
1.2A max

± 5%

CONNECTORS

CARD DIMENSIONS
4.5 in. (11.43 cm) high by 6.50 in. (16.51 cm) long
0.48 in. (1.22 cm) maximum profile thickness
0.062 in. (0.16 cm) printed-circuit-board thickness

Function

Configuration

Mating
Connector
PRINTED CIRCUIT
Viking 3VH281
1CE5

STD-Z80 BUS 56-pin

0.125 in. centers

WIRE WRAP
Viking 3VH281
1CND5
SOLDER LUG
Viking 3VH281
1CN5

ORDERING INFORMATION
DESIGNATOR

DESCRIPTION

PART NO.

MDX-SRAM4

4K Bytes (4118's) module with operation manual less
mating connectors

MK77755

MDX-SRAM8

8K Bytes (4118's) module with operation manual less
mating connectors

MK77756

MDX-SRAM Operations Manual Only

MK79673

VI-15

VI-16

MOSTEI(.

MD SERIES MEMORY CARDS

MDX-UMC
MK77759
MDX-UMC BOARD PHOTO

FEATURES
o STD and STD-Z80 BUS compatible
o Can be strapped to accept the following industrystandard memory devices:

EPROM

STATIC RAM

ROM

2758 (lK x 8)
2716 (2K x 8)
2732(4Kx8)

MK4118 (1 K x 8)
MK4802 (2K x 8)

MK34000 (2K x 8)

o Memories can be mixed to form a combination memory
board
o Operates at 2.5MHz and 4.0MHz system clocks speeds
o Wait-state generator provided
o Single +5 Volt supply

DESCRIPTION
The MDX-UMC is one of Mostek's complete line of STD-Z80
BUS-compatible microcomputer modules.
Designed as a universal memory card for the STD-Z80 BUS,
the MDX-UMC provides the user with the capability of
configuring the board to meet the system requirement of
ROM/EPROM and/or RAM. By the use of strapping
options, the user is able to configure pairs of sockets for

ROM/EPROM/RAM toform a combination memoryboard.
Other MDX-UMCfeatures include4K boundary addressing
and an optional wait-state generator to accomodate slower
memories for 4MHz system clock operations.

VI-17

MDX-UMC BLOCK DIAGRAM

:>

8
MEMORY
DECODE
&
CONTROL
LOGIC

MEMORY ARRAY
DEVICES*

CS
EPROM

---

-

2758
2716
2732

OE

WRITE

RAM

ROM

MK4118
MK4802

MK34000

---

A

<

*MEMORY DEVICES CAN BE MIXED TO
FORM A COMBINATION MEMORY. BOARD

/\

j\

/\
10

OE
8

6

V
CONTROL BUS
BUFFER

/\

-

M EMRO. RD

-W R. CLOCK

4

..

DATA BUS
BUFFER

ADDRESS BUS
BUFFER

/\

/\

.

+5V

--WAITRO

GND

I I

16

8

~V

STD BUS OR STD-Z80 BUS

OPERATING TEMPERATURES

WORD SIZE
8 Bits

MEMORY SIZE

POWER REQUIREMENTS

8 sockets
+5V ± 5% at 0.450 A max.
Does not include power for memories

Sockets are strapped in pairs to accomodate the following
memories.

EPROM
2758
2716
2732

STATIC RAM
MK4118
MK4802

ROM
MK34000

CARD DIMENSIONS
4.5 in. (11.43cm) high by 6.50 in. (16.51cm) long
0.48 in. (1.22cm) maximum profile thickness
0.062 in. (0.16cm) printed-circuit-board thickness

MEMORY ADDRESSING
4K boundaries

SYSTEM INTERRUPT UNITS (SIU) = 0
STD-BUS INTERFACE
Inputs:
Outputs:

One 74LS load max.
IOH = -3mA min. at 2.4 Volts
IOL = 24mA min. at 0.5 Volts

VI-18

~

CONNECTORS
Mating
Connector

Function

Configuration

STD-Z80 BUS

56-pin

PRINTED CIRCUIT
Viking 3VH281
lCE5

0.125 in. centers

WIRE WRAP
Viking 3VH281
lCND5
SOLDER LUG
Viking 3VH281
lCN5

ORDERING INFORMATION
DESIGNATOR

DESCRIPTION

PART NO.

MDX-UMC

Module with operation manual less mating connectors

MK77759

MDX-UMC Operation Manual Only

MK79667

VI-19

MICRO SYSTEMS DATA BOOK

MOSTEI(.
MDXSERIES

System Interrupt Units

CARD

SIU's

MDX-CPUl
MDX-CPU2
MDX-DRAMS/16/32
MDX-EPROM/UART
MDX-DEBUG
MDX-PIO
MDX-SIO
MDX-SST
MDX-FLP
MDX-MATH
MDX-AiDS
MDX-AIO
MDX-AlD12
MDX-D/AS
MDX-D/A12
MDX-UMC
MDX-SRAM4/S/16
MDX-EPROM
MDX-INT
MDX-SC/D

VII-1

1
1

0
0
0
2
1
0
1
1
1

0
1
0
0
0
0
0
1
1

VII-2

MOSTEI(.

MD SERIES SPECIAL FUNCTIONS

MDX-DEBUG
MK77950-0, MK77950-4
HARDWARE FEATURES
o
o
o
o

MDX-DEBUG BOARD PHOTO

STD-Z80 BUS compatible
4 MHz version available
Serial 1/0 Channel '
10K bytes of ROM contain the following firmware:
DDT-80, ASMB-80

DEBUGGER FEATURES
o
o
o
o

Z80 Operating System with debug capability
Channelized 1/0 for versatility
I/O peripheral drivers supplied
ROM-based

TEXT EDITOR FEATURES
o Input and modification of ASCII Text
o Line and character editing
o Alternate command buffers for pseudo- macro command
capability
o ROM-based
ASSEMBLER FEATURES
o Assembles all Z80 mnemonics
o Object output in industry-standard hexadecimal format
extended for Relocatable and Linkable Programs
o Over fifteen pseudo-ops
o Two-pass assembly
o ROM-based
LINKING LOADER FEATURES
o 'Loads into memory both relocatable and non-relocatable
'object output of the assembler
o Loads Relocatable modules anywhere in memory
o Automatically provides linkage of global symbols
between object modules as they are loaded
o Prints system load map
o ROM-based
HARDWARE DESCRIPTION
The MDX-DEBUG module has sockets for 10K bytes of
masked ROM that are filled with a Z80 firmware packa"ge

(DDT-80/ASMB-80). This module has a STD-Z80 BUS
interface and is available in both 2.5 MHz and 4.0 MHz
version.ln~luded on-board is a fully buffered asynchronous
1/0 port capable of 110-19200 Baud rates. Serial data
interfaces are available for 20 mAcurrent loop (with readerstep control) and RS-232. The on-board Baud Rate
Generator is selectable to all common Baud rates from 110
to 19,200 Baud. The address of the serial port is selectable
via 6 on-board jumpers.
DEBUGGER DESCRIPTION
DDT-80 is the Operating System for the MDX-DEBUG
Module, residing in a 2K ROM (MK34000 Series) on the
module itself. It provides the necessary tools and
techniques to operate the system, i.e., to efficiently and
conveniently perform the tasks necessary to develop
microcomputer software. DDT-80 is designed to support
the user from initial design through production testing. It
allows the user to display and update memory, registers,
,and ports, load and dump object files, set breakpoints, copy
blocks of memory, and execute programs.

VII-3

MDX-DEBUG BLOCK DIAGRAM

ADDRESS AND CONTROL BUS

20 mA INPUT
OUTPUT AND
READER STEP
BUS
INTERFACE
LOGIC

MEMORY
SELECTION
LOGIC

ROM FIRMWARE
DDT·80 AND ASMB·80
RS·232
INPUT, OUTPUT
AND
MODEM CONTROL

DATA BUS

DDT-SO COMMAND SUMMARY
M

S

-

M s, f

-

Ps

-

D s, f

-

L

-

Es

-

H

-

C s, f, d

-

Bs

-

Rx

-

MEMORY. PORT ANDREGISTE~ COMMANDS
1M. p. R)

Display and/or update the contents of
memory location s.
Tabulate the contents to memory locations s
through f.
Display and/or update the content of I/O
ports.
Dump the contents of memory locations s
throughf in a format suitable to be read by the
Lcommand.
.
Load, into memory, data which is in the
appropriate format.
Transfer control from DDT-SO toa user's
program starting at location s.
Perform 16-bit hexadecimal addition and/or
subtraction.
Copy the contents of memory locations s
through f to another location in memory
starting at location d.
Insert a breakpoint in a user's program (must
be in RAM) at location s which transfers
control back to DDT-SO. This allows the user
to intercept his program at a specific point
. (location s) and examine memory and CPU
registers to determine if this program is
working correctly.
Display the contents of the user registers.

The s, f, and d represent start, finish, and destination
operands required for each command.

The M, P, and R commands provide the means for
displaying the contents of specified memory locations, port
addresses, or CPU registers. The M and P commands
sequentially access memory locations or ports and display
their contents. The user has the option of updating the
content of the memory location or port. (Note some ports are
output only and their contents cannot be displayed). The M
command aiso gives the user acces.s to the CPU registers
through an area in RAM called the Register Map (discussed
in the Execute and Breakpoint section below).
The M and R commands are used to tabulate blocks of
memory locations 1M) or the CPU registers (R). The M
commandwill accept two operands, the starting and ending
address of the block to be tabulated. The R command will
accept either no operand or one. If no operand is specified,
the CPU registers will be displayed without a heading. If an
operand is specified, then a heading vithi.ch labels the
registers' contents will be displayed as well.

EXECUTE AND BREAKPOINT IE. B)
The E command is used to execute all programs, including
aids such as the Assembler. The B command is used to set a
breakpoint to exit from a program at some predetermined
location for debugging purposes. At the instant of a
breakpoint exit, the contents of all CPU registers are saved
in a designated area of RAM called the Register Map. In the

VII-4

Register Map. the register contents may be examined or
mapped using the M command and a predefined mnemonic
(or absolute address) ofthe storage location for that register
(example :PC. :A, ...• :SP). The Register Map is also used to
initialize the CPU registers whenever execution is initiated
or resumed. Thus the E and B commands can be used
together to initialize. execute. and examine the results of
individual program segments.
The B command gives the user the option of having all CPU
registers displayed when the breakpoint is encountered.
This is done by entering a second operand to the B
comma nd. Otherwise. DDT-SO defaults to displayi ng the PC
and AF registers. When all CPU registers are displayed. the
format is the same as for the R command previously
discussed.
LOAD. DUMP. AND COpy (L. D. C)
The Land 0 commands load and dump object files through
the object 110 channel in standard Hex format. Checksums
are used for error detection. and the addresses of
questionable blocks are typed automatically while loading.

The C command will copy the contents ofthe memory block
specified to another block of memory. There are no
restrictions on the direction of the copy or on whether the
blocks overlap.
HEXADECIMAL ARITHMETIC (H)
The H command is a dummy command used to allow
hexadecimal addition and subtraction for expression
evaluation without performing any other operation.
DDT-SO 1/0 CAPABILITIES
DDT-SO specifies 110 channels. designated ·Console·.
·Object·. and ·Source·. to which any suitable devices may be
assigned. The Channel Assignment Table is located in RAM
where it may be examined or modified using the M
command. The table addresses correspond to the 110
channels and the table contents correspond to the
addresses of the peripheral driver routines. A channel
which has a device assignment may have that device
assignment changed using the M command. This is
accomplished by merely modifying the table contents of that
channel's table address to correspond to the new peripheral
driver routine. A set of peripheral driver routines is supplied
and listed below. This scheme also allows the user to write
a driver routine for his own peripheral. load it into memory.
and easily configure that peripheral into the system.
DDT-SO I/O PERIPHERAL DRIVERS
1. A serial input driver (usually a keyboard).
2. A serial output driver (usually a CRT or teletype
typehead).

3. A serial input driver which sends out a reader-step signal
(usually a teletype reader).
4. A serial output driver which forces a delay after a
carriage return (usually a Silent 700 type head).
5. A parallel input driver (usually for high-speed paper tape
input).
6. A parallel output driver (usually for high-speed paper
tape output).
7. A parallel output driver (usually for a line printer).
TEXT EDITOR DESCRIPTION
The Text Editor permits random-access editing of ASCII
character strings. It can be used as a line or characteroriented editor. Individual characters may be located by
position or context. The Editor works on blocks of characters
which are typically. read into memory from magnetic tape or
paper tape. Each edited block can be output to magnetic
tape or paper tape after editing .is completed. While the
primary application for the Text Editor is in editing assembly
language source statements. it may be applied to any ASCII
text delimited by "carriage returns".
The Editor has a macro command processing option. Up to
two sets of commands may be stored and processed at any
time during the editing process.
All 110 is done via the DDT-SO channels. The Editor can be
used with the ASMB-SO Assembler and Loader to edit.
assemble. and load programs in memory without the need
for external media for intermediate storage.
The following commands are recognized by the Text Editor:
AnBn Cn dS1dS2dOn E-

ILn MnNPn RSn dS1d-

Advance record pointer n records
Backup record pointer n records
Change string S1 to string S2 for n
occurrences
Delete next n records
Exchange current record with records to
be inserted
Insert records
Go to line number n
Enter command buffers (pseudo-macro)
Print top. bottom. and current line number
Punch n records from buffer
Read source records into buffer
Search for nth occurrence of string S1

ASSEMBLER DESCRIPTION
The Assembler reads zao source mnemonics and psuedoops and outputs an assembly listing and object code. The
assembly listing shows address. machine code. statement
number. and source statement. The object code is in
industry-standard hexadecimal format modified for relocatable. linkable assemblies.

VII-5

The Assembler supports conditional assemblies, global
symbols, relocatable programs, and a printed symbol table.
It can assemble any length program limited only by a symbol
table size which is user-selectable. Expressions involving
addition and subtraction are allowed. A global symbol ,is
categorized as "internal" if it appears as a label in the
program; otherwise it is an "external" symbol. The printed
symbol table shows which symbols are internal and which
are external. The Assembler allows the user to select
relocatable or non-relocatable assembly via the "PSECT"
pseudo-op. Relocation records are placed in the object
output for relocatable assemblies (the Mostek object format
is defined below). The Assembler can be run as a single-pass
assembler or as a learning tool. (In this mode, global
symbols and forward references are not allowed.)
The following pseudo-ops are recognized by the Assembler:
ORG program origin·
EQU equate label
DEFL define label'
DEFM -.
define message
DEFB define byte.
DEFW define word
DEFS define storage
END. end statement
NAME program name definition
PSECT program section definition
GLOBAL global symbol definition
Supports the following assembler
pseudo-ops
eject a page of listing.
EJECT TITLE place heading at top of each page
LIST c
turn listing on
NLiST turn listing off

RELOCATING LINKING LOADER DESCRIPTION
The Relocating Linking Loader provides state-of-the-art
capability for: loading programs. into memory by allowing
loading and linking of any number of relocatable and nonrelocatable object modules. Non-relocatable modules are
always loaded at their starting address'as defined by the
ORG pseudo-op during assembly. Relocatable object
modules can be positioned anywhere in memory at an
offset address.
The loader automatically links any relocator global symbols
which are used to provide communication or linkage
between program modules. As object programs are loaded,

a table containing global symbol references and definitions
is built up. At the end of each module, the loader resolves all
references to global symbols which are defined by either the
current or a previously loaded module. It also prints on the
console device the number of defined global symbols that
have been referenced. The symbol table can be printed to
list all global symbols and their load addresses. The number
of object modules which can be loaded by the Loader is
limited only by the amount of RAM available for the
modules and the symbol table. Space for the symbol table is
allocated dynamically downward in memory from either the
top of memory or from a specified address entered' as an
operand of the load command.
All 1/0 is done via the DDT-80 channels. Assemblies can be
done from source statements stored in memory (by the
Editor). The object output can be directed to a memory buffer
rather than to an external device. Thus, assembly and
loading can be done without external storage media.
The. Loader prints the beginning and ending address of each
module as it is loaded. The transfer address as defined by
the END psuedo-ops is printed for the first module loaded.
The Loader execute command (E) can be used to
automatically start execution at the transfer address.
The Loader Commands are the following:
L offset load object module at address "off-set"
plus program origin address
Eexecute loaded program at transfer
address of first module
Tprint global symbol table
MOSTEK OBJECT OUTPUT DEFINITION
Each record of an object module begins with a delimiter
(colon or dollar sign) and ends with carriage return and line
feed. A colon (:) is used for data records and the end-of-file
record. A dollar sign ($) is used for records containing
relocation information and linking information. All information is in ASCII. Each record is identified by "type". The type
is determined by the 8th and 9th bytes of the record which
can take the following values:
00
01
02
03
04
05

VII-6

-

data
end-of-file
internal symbol
external symbol
relocation information
module definition

OBJECT MODULE TYPES

rD'UMIT"
1

•
•
•

•

2

RECORD TYPE

~

3

CD

#OF
BINARY
DATA BYTES

0

4

. . . I
5

6

7

B

START ADDRESS
OF DATA

0

TRANSFER ADDRESS
OF MODULE

0

.

CHEC~ G)

1

SUM

.

2

0

I

EXTERNAL SYMBOL NAME

$

#OF
BINARY
BYTES

CD

$

I

LINK
ADDRESS

3

0

CHECKG)
SUM
1

ADDRESS

--'$

CHECK G)
SUM
1

DATA

--'-

INTERNAL
SYMBOL NAME

$

.

0

0

.

110

9

~

I

.

I

CD

CHECKG)
SUM
1
•
I

0

0

0

0

MODULE NAME

0

4

0

5

ADDRESSES WHICH
••. REQUIRE RELOCATION .••

CHECKG)
SUM
1

FLAG~ CD

I

I

.G)

NOTES:
1. Check Sum is negative of the binary sum of all bytes except delimiter and carriage return/line feed.

r

Th

2.

Link Address points to last address in the data which uses the external symbol. This stans a backward link list through the data records for that external symbol.
terminates at OFFFFH.
3,' The flags are one binary byte. Bit 0 is defined as:
absolute module
1 - relocatable module
4. Maximum of 64 ASCII bytes.

e

o.

WORD SIZE

SERIAL COMMUNICATIONS INTERFACE

8 bits for PROM
5 to 8 bits for serial I/O
SIGNAL
MEMORY SIZE
10K bytes of firmware
MEMORY ADDRESSING

Transmitted data
Received data
Data Terminal Ready (DTR)
Request to Send (RTS)
Carrier Detect (CDET)
Clear to Send (CTS)
Data Set Ready (DSR)
Reader Step relay (RS)

2K blocks jumper-selectable for any 2K boundary within a
given 16KbiockoftheZ80 memory map. MDX-DEBUG has
ROMS strapped every 2K beginning at COOOOH.
I/O ADDRESSING
On board Serial I/O Port
Control Port: XXXXXX01
Data Port: XXXXXXOO
Module and Reader Step Control Port: XXXXXX10
XXXXXX represents 6 strap-selectable address bits.

Output
Input

RS-232
Output
Input
Input
Input
Output
Output
Output

Output
(4OmA)

SYSTEM CLOCK
MDX-DEBUG
MDX-DEBUG-4

I/O TRANSFER RATE
110, 300, 600, 1200, 2400, 4800, 9600, 19200 BAUD

BUFFERED FOR
20 rnA
Current
Loop

MIN
1.25 MHz
1.25 MHz

SYSTEM INTERRUPT UNITS (SIU)

VII-7

=0

MAX
2.5 MHz
4.0 MHz

1St

STD BUS INTERFACE
Inputs:
Outputs:

CONNECTORS

One 74LS load max.
10H = -3 mA min. at 2.4 Volts
10L = 24 mA min. at 0.5 Volts

Function

OPERATING TEMPERATURE

Configuration

STD-Z80 BUS 56-pin

Mating
Connector
. PRINTED CIRCUIT
Viking.~VH281

1CE5

O°Cto +60°C
POWER SUPPLY REQUIREMENT

0.125 in. centers

+12 Volts ± 5% at 50 mA max.
-12 Volts ± 5% at 35 rnA max.
+5 Volts ± 5% at 1.2 A max.

WIRE WRAP
Viking 3VH281
1CND5
SOLDER LUG
Viking 3VH281
1CN5

CARD DIMENSIONS
Serial 1/0
4.5 in. (11.43 em) high by 6.50 in. (16.51 em) long
0.48 in. (1,22 em) maximum profile thickness
0.062 in.;(O.16 em) printed-circuit-board thickness

26-pin
0.1 in. grid

FLAT RIBBON
Ansley 609-2600M
DISCRETE WIRES
Winchester
PGB26A
(housing)
Winchester
100-700205
(contacts)

ORDERING INFORMATION
DESIGNATOR

DESCRIPTION

PART NO.

MDX-DEBUG

Module with 10K bytes of firmware and Operations
Manual. No mating connectors. 2.5 MHz version.

MK77950-0

MDX-DEBUG4

Module with 10K bytes of firmware and Operations
Manual. No mating connectors. 4.0 MHz version

MK77950-4

MDX-OEBUG Operations Manual only.

MK79611

Program Source Listing of 10K byte firmware package
(DDTI ASMB-80) including comments and flow charts.
(Available free with purchase of either MDX-DEBUG
Module.)

MK78536
and
MK78534

* The 00T-80 and ASMB-80 listings are available directly from Mostek by filling out a copy of the Software Licensing
Agreement and returning it with the appropriate payment of Customer Purchase Order to:
Mostek Corporation
Microcomputer Systems Div.
1215 West Crosby Road
Carrollton, Texas 75006

VII-8

STANDARD SOFTWARE LICENSING AGREEMENT
All Mostek Corporation products are sold
on condition that the Purchaser agrees to
the following terms:
1.

2.
3.

4.

5.

6.

The Purchaser agrees not to sell, provide, give away, or otherwise make available to any unauthorized persons, all or
any part of, the Mostek software products listed below; including, but not restricted to: object code, source code and
program listings.
The Purchaser may at any time demonstrate the normal operation of the Mostek software product to any person.
All software designed, developed and generated independently of, and not based on, Mostek's software by
purchaser shall become the sole property of purchaser and shall be excluded from the provisions of this Agreement.
Mostek's software which is modified with the written permission of Mostek and which is modified to such an extent
that Mostek agrees that it is not recognizable as Mostek's software shall become the sole property of purchaser.
Purchaser shall be notified by Mostek of all updates and modifications made by Mostek for a one-year period after
purchase of said Mostek software product. Updated and/or modified software and manuals will be supplied at the
current cataloged prices.
In no event will Mostek be held liable for any loss, expense or damage, of any kind whatsoever, direct or indirect,
regardless of whether such arises out of the law of torts or contracts, or Mostek's negligence, including incidental
damages, consequential damages and lost profits, arising out of or connected in any manner with any of Mostek's
software products described below.
MOSTEK MAKES NO WARRANTIES OF ANY KIND, WHETHER STATUTORY, WRITIEN, ORAL, EXPRESSED OR
IMPLIED (INCLUDING WARRANTIES OF FITNESS FOR A PARTICULAR PURPOSE AND MERCHANTABILITY AND
WARRANTIES ARISING FROM COURSE OF DEALING OR USAGE OF TRADE) WITH RESPECT TO THE
SOFTWARE DESCRIBED BELOW.

The Following Software Products Subject to this Agreement:
Order Number
Description

Price*

Ship To: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Bill To: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Method of Shipment:

Customer P.O. Number

Agreed To:
PURCHASER
MOSTEK CORPORATION
By: ___________________________________ By: __________________________________
Title: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Title: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Date: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Date: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

* Prices Subject to Change Without Notice

VII-9

VII-10

MOSI 'EI(.
MD SERIES SPECIAL FUNCTIONS

MDX-INT
MK77967
FEATURES

MDX-INT BOARD PHOTO

o STD-Z80 BUS compatible

o

User-programmable CTC provides:
• Four external vectored interrupts
or
• Four cascadable counter/timer channels
or
• any combination of the above

o Z80 Daisy Chain Interrupt Expansion
• Allows up to 40 interrupt devices
• User selectable expansion of System Interrupt Units
(SIU)
• Required for systems over five SIU's
o Nonmaskable Interrupt Input
o All input/output signals buffered
o 4MHz compatible (14,24,34, SIU)
o +5 Volt operation only
another active edge. Therefore, once initialized, a channel
will automatically provide external interrupt capability.

DESCRIPTION
The Interrupt-Timer Expansion Module, MDX-INT, is
designed to be a versatile multimode unit. It provides
external interrupt expansion of up to four lines, a nonmaskable interrupt input, up to four cascadable timer
channels, and internal interrupt expansion capability of up
to 40 System Interrupt Units. All interrupts are Z80
compatible with full Mode 2 interrupt capability.
The MDX-INT permits up to four e)(ternal interrupt inputs.
This is possible by programming the MK3882 Counter
Timer to function as an interrupt controller. When
programming the CTC, the selected input channel is
programmed to be in the counter mode with count set to
one. The active edge as well as the interrupt vector locations
are also specified by the user's program. When an active
input occurs, a Mode 2 interrupt is generated by the CTC
and the MDX-CPU can vector directly to a service routine.
After the interrupt, the CTC down counter is automatically
reloaded with a count of one and the CTC begins looking for

Up to four channels can be used to provide external
interrupts. Input is providedthroughtheTRGOtoTRG31ines
for channels zero thru three. When multiple channels are
used, priorities are resolved within the CTC if more than one
interrupt request is made simultaneously. Each channel
has a unique vector address and each channel can be
independently "masked" by disabling that channel's local
interrupt.
The nonmaskable interrupt is also provided as an input
through this board. This line is tested by the MDX-CPU at
the end of each instruction. It has priority over the normal
interrupt and cannot be disabled under software control. Its
usual function is to provide response to signals requiring
immediate response, such as an impending power failure.
Each of the four CTC channels has an 8-bit Prescaler and
8-bit Down Counter that allows the circuit to be used as a
counter or a timer as well as an interrupt generator. In the
counter mode, a Zero Count output is provided that allows
cascading of successive counters. In the counter mode,

VII-11

MDX-INT BLOCK DIAGRAM

.-_________________<

1-_ _ _ _ _ _ _-< NON MASKABLE
INTERRUPT
TRGO}
CHANNEL
ZCO

°

TRG'} CHANNEL ,
ZC,
TRG2}

CHANNEL2

ZC 2
TRG 3

DATA BUS
BUFFER
AND
INTERFACE
LOGIC

CHANNEL 3

CASCADE
JUMPER

external inputs can be counted automatically by the CTC
and interrupt the processor after a predefined number of
counts. In the timer mode, the CTC can generate timing
intervals that are integer multiples of the system clock
period. TheZero Count output can generate a uniform pulse
train of the precise period. Therefore, precise time
measurements can be made that are a function of a crystal
clock's accuracy and stability.

SYSTEM CLOCK

MDX-INT

MIN.

MAX.

250 kHz

4.0 MHz

STD BUS INTERFACE
The MDX-INT also provides internal interrupt expansion
through a concept of System Interrupt Units (SIU). The
interrupt system of STD-Z80 compatible CPU'swili allow up
to five System Interrupt Units without need of expansion.
The MDX-INT has circuitry to allow expansion of board with
up to 40 SIU's.lt must bethe last card(the lowest priority) in
the interrupt daisy chain. An SIU is defined as an interval of
time equivalent to the worst-case propagation delay of the
the priority daisy chain through an MD board. A board with
one interrupting peripheral component, such as an MDXSIO,hasone SIU. A board with two interrupting peripheral
components, such as an MDX-PIO, has two SIU's. A board
with no interrupt capability has zero SIU's.
The SIU expansion circuitry on the MDX-INT card monitors
the data bus and PCllines. Wait states are added during the
RETI opcodeto allow the PCI and PCO linesto stabilize. The
Wait state generator on the MDX-INT is enabled when an
interrupt is pending or under service and will insert a
predetermined number wait states for 15, 25, or 40 SIU's.
The number of SIU's that the system can handle is
hardware-selectable on-board.

Inputs:
Outputs:

One 74LS Load max.
10H = -3mA min. at 2.4 Volts
10L = 24mA min. at 0.5 Volts

SYSTEM INTERRUPT UNITS (SIU) = 1
POWER SUPPLY REQUIREMENTS
+5 Volts

± 5% at 1.2 A Max.

WORD SIZE
Data:
Address:

8 Bits 1/0
8 Bits using 4 Ports with 6-Bits
Jumper Option

OPERATING.TEMPERATURE RANGE
oeCto 60 eC

VII- 12

INTERRUPTS

CONNECTORS

External Interrupts are handled to provide prioritized,
maskable, Mode 2 interrupts compatible with the STD-Z80
Bus requirements. The external interrupts are edgetriggered with the active edge software-programmable.

Function

Up to four external interrupt inputs can be handled. These
are prioritized with channel 0 being highest priority.

Configuration

STD-Z80 BUS 56-pin
0.1 25 in. centers

The nonmaskable interrupt is provided as an input. It has
priority over any maskable interrupt and forces the MDXCPU to a restart location of 066H.

Mating
Connectors
PRINTED CIRCUIT
Viking 3VH28/1 CE5
WIRE-WRAP
Viking
3VH28/1CND5

TIMER

SOLDER LUG
Viking
3VH28/1CN5

Up to four counter/timer channels are available. The
outputs can be cascaded for long word counts. Zero
CountlTimeout outputs are provided on three channels.
CTC I/O

CARD DIMENSIONS

26-pin
0.100 in. centers

FLAT RIBBON
Ansley 609-2600M
DISCRETE WIRES
Winchester
PGB26A
(housing)

4.5 in. (114.3 mm) wide by 6.5 in. (165.1 mm) long
0.48 in. (12.2 mm) maximum profile thickness
0.062 in. (01.6 mm) printed-circuit-board thickness

Winchester
100-70020S
(contacts)

ORDERING INFORMATION
DESIGNATOR

DESCRIPTION

PART NO.

MDX-INT

2.5 MHz or 4.0 MHz board with Operations Manual
less Mating Connector

MK77967

MDX-INT Operations Manual only

MK79780

VII-13

VII-14

MOSTEI<.

MD SERIES SPECIAL FUNCTIONS

MDX-SC/D
MK77963-0, MK77963-4
FEATURES

MDX-SC/D BOARD PHOTO

o STD-Z80 BUS compatible
o Provides an operator interface; switches and lamps
o 10K x 8 EPROM (2716's not included)
o Dual-purpose card, memory and/or diagnostic interface
o Interrupt-driven programmability
o Strap-selectable address
o 4 MHz Option
o Fully-buffered for MD Series expandability
o Diagnostic software package

DESCRIPTION
Designed as a system cOr;ltroller/diagnostics board, the
MDX-SC/D provides the system designer with a tool to
verify that various other MD Series modules are
operational. The board is equipped with sockets to contain
up to 1OK x 8 of EPROM memory(5-2716's) as shown in the
Block Diagram. The EPROM's can contain the diagnostic
programs necessary for testing the modules or can contain
user application programs.
The EPROM memories can be positioned to start on any 2K
boundary within a 16K block of memory via II strapping
option provided on the board.
For the4MHZ version, circuitry is provided to force one wait
state each time on-board EPROM's are accessed.
A three-position switch is provided at the top of the board.

The switch is springloaded to the OFF position. The RESET
position initializes the hardware and software diagnostics
elements. The START position begins the diagnostic test
which had been pres!!t by the thumbwheel switches, also
on the top of the board. At the conclusion of the test, the
results are displayed by the LED Readouts. Data transfers
from the switches to the bus and from the bus to the
readouts are accomplished by the MK3881 PIO.
The PIO also permits total interrupt control so that full usage
of the CPU interrupt capabilities can be utilized during data
transfers. The PIO provides vectored interrupts and
maintains the daisy-chain, priority interrupt logic
compatible with the STD-Z80 BUS.

VII-15

MDX-SC/D BLOCK DIAGRAM
ADDRESS AND CONTROL
BO- B6

BUS

B7
A6
3BB1
PIO

BUS
INTER
FACE
LOGIC

SEL
B
AO·A3

TW1

f0

TW2'

If]

MUX

DATA BUS

The address decoding, interface and bus management for
the board are performed by th!l address decode and data
bus circuit. The PIO ports have two addresses each; these
are summarized below.

MEMORY ADDRESSING
EPROM - 2K blocks jumper-selectable for any 2K boundary
within a given 16K boundary of Z80 memory map.
MEMORY SPEED REQUIRED

PORTA

PORTB

DATA

XXXXXOOO

XXXX X010

CONTROL

XXXXXOO1

XXXXX011

Access Time
Memory
* 2716
450ns
* Single 5-Volt type required
INPUT/OUTPUT

The XX symbols stand for the upper five bits of the I/O
channel address. These bits are jumper-selectable on the
board in order to provide address~selectable, fully decoded
ports.
MEDEX-SO
MEDEX-80 is a diagnostic software package designed to
operate with the MDX-SC/D card's thumbwheels, switch
and display. The package consists of a control monitor,
MDX-SC/D card interface handler, and numerous
diagnostic tests. The package can operate as a stand-alone
program or can be integrated with a user program. MEDEX. 80 is designed to allow user-developed diagnostics to be
adapted as extensions to the package.
WORD SIZE

Cycle Time
450 ns

Controlled by spring-loaded RESET/START switch with
center off.
Test selected by two thumbwheel switches.
Test results indicated by two 7-segment.LEDs.
INTERRUPTS
Vectored interrupts generated. Interrupt vector programmable upon initialization. Daisy-chained interrupt
priority. Selected bit channels can be masked out under
program control.
SYSTEM INTERRUPT UNITS (SIU)

=1

SYSTEM CLOCK

MDX-SC/D
MDX-SC/D-4

MIN.
250kHZ
250 kHZ

MAX.
2.5 MHZ
4.0 MHZ

8 bits

STD BUS INTERFACE

MEMORY SIZE

Inputs: One 74LS Load max.
Outputs: 10H = -3mA min. at 2.4 Volts
10L = 24mA min. at 0.5 Volts

10K bytes of 2716 memory (2716's not included)

VII-16

OPERATING TEMPERATURE RANGE
O°C to 60°C
POWER SUPPLY REQUIREMENTS
+5 Volts ± 5% at 1.2 A max.
CARD DIMENSIONS
4.5 in. (11.43cm) high by 6.50 in. (16.51 cm) long
0.48 in. (1.22cm) maximum profile thickness
0.062 in. (0.16cm) printed-circuit-board thickness
CONNECTORS
Function

Configuration

STD-Z80 BUS 56-pin
0.125 in. centers

Mating Connector

PRINTED CIRCUIT
Viking 3VH28/1 CE5
WIRE WRAP
Viking
3VH28/1CND5
SOLDER LUG
Viking
3VH28/1CN5

ORDERING INFORMATION
DESIGNATOR

DESCRIPTION

PART NO.

MDX-SC/D

Module with Operation Manual, 2.5 MHZ version

MK77963-0

MDX-SC/D-4

Module with Operation Manual, 4.0 MHZ version

MK77963-4

MDX-SC/D Operation Manual Only

MK79678

Diagnostic software for various MDX Series cards,
distributed on diskette in Z80 Assembly source form

MK77968

MEDEX-80

VII-17

VII-18

MOSTEI(.

MD SERIES SPECIAL FUNCTIONS

MDX-SST
MK77958
FEATURES

o

MDX-SST BOARD PHOTO

STD-ZSO BUS compatible

o Hardware single-step capability
o Compatible with DDT-SO Operating System
o +5 Volt only
o Both 2.5MHz and 4.0MHz
DESCRIPTION
The Mostek MDX-SST was designed to enhance the
hardware and software debug capability for MD Series
systems. The use of the MDX-SST with the MDX-CPU',
MDX-CPU2 and MDX-DEBUG boards allows the user to
single-step instructions through RAM and/or
EPROM/ROM with the capability of displaying all of the
CPU registers on each instruction execution.
The MDX-SST board is implemented using the CPU's
nonmaskable interrupt and is controlled by firmware from
the keyboard. When the command to single step an
instruction is given, the sequence of events is the same as
executing a program except that a "'" is output to the single
step control port (DFH) instead of a "0". The circuit decodes
the double M' instructions (CBH, DDH, EDH, or FDH) and
M' is used to clock a shift register circuit which (if a "'" is
output to port DFH) generates a nonmaskable interrupt at
the start of the instruction to be single stepped. The
nonmaskable interrupt saves the address of execution on
the stack and causes the next instruction to be fetched from
address E066H. The shift register is clocked twice after the

nonmaskable interrupt, causing the signal DEBUG to go
low, forcing "E" on the most significant address lines, and
causing the instruction to be fetched from E066H in the
operating system RAM. The operating system then jumps to
E069H, clears the debug flip-flop by reading PORT DFH,
saves the CPU registers in the scratch RAM, and waits for
the next command.
The single-step command is implemented in DDT-SO,
which resides on the MDX-DEBUG board and has the
following format.

VII-19

MDX-SST BLOCK DIAGRAM

-

DATA BUS
DO-D7

STD
Z80
BUS

CONTROL BUS
IORO, WR, RD, MI

ADDRESS BUS
AO-A7

"'"

./

PORT
DECODE

~

:>
:>

iiiiiiiiFiO.

Pin 46

I

INSTRUCTION
DETECTOR

i

DOUBLE
OP-CODE
DETECT

I

DEBUG Pin38

'-----

S COMMAND (Single-step)

OPERATING TEMPERATURE

This command allows the user to start single-stepping from
a given location for a given number of instructions and to
display the CPU registers after each step.

O°Cto 60°C
POWER SUPPLY REQUIREMENTS
+5VDC at 85mA

Format:
.S aaaa,nn,b(cr)

.S aaaa,nn(cr)
.S aaaalcr)
.S (cr)

start single-stepping at location aaaa
for nn steps or instructions. If b=O,
display only the PC and AF registers; if
biO, display all the CPU registers.
the same as above with b=O
assumed.
the same as above with nn=1 and b=O
assumed.
b=O assumed; aaaa is set equal to the
contents of the user's PC.

The use of the MDX-SST board requires the MDX-CPU1 or
MDX-CPU2 and the MDX-DEBUG. Also, system RAM must
be present from FFOO to FFFF.

CARD DIMENSIONS
4.5 in (11.43cm) high by 6.50 in. (16.51 cm) long
0.48 in (1.22cm) maximum profile thickness
0.062 in. (0.16cm) printed-circuit-board thickness

CONNECTORS
Function

STD-Z80 BUS 56-pin
0.125 in. centers

PORT ADDRESS (HEX)
DF

MAX.
4.0MHz

PRINTED CIRCUIT
Viking
3VH28/1CE5

SOLDER LUG
Viking
3VH281
1CN5

SYSTEM INTERRUPT UNITS (SIU) = 0
STD BUS INTERFACE
Inputs:
Outputs:

Mating
Connector

WIRE WRAP
Viking
.3VH281
1CND5

SYSTEM CLOCK
MIN.
500kHz

Configuration

One 74LS load max.
IOH = -3mA min. at 2.4 volts
IOL = 24mA min. at 0.5 volts

VII-20

ORDERING INFORMATION
DESIGNATOR

DESCRIPTION

PART NO.

MDX-SST

Single-Step Module, includes Operations Manual

MK77958

MDX-SST Operations Manual Only

MK79638

VII-21

MICRO SYSTEMS DATA BOOK

MOSTEl(.

MD SERIES ACCESSORIES

MO-ACC
MK77952, MK77953, MK77955,
MK77956, MK77957, MK77959,
MK77969, MK77970, MK77973, MK79089
INTRODUCTION
The following items are available as accessories to support
design, development, and production of products designed
around the Mostek MD SeriesZ80* microcomputer modules:
MDX-WW1
MDX-WW2
MD-EXT
MD-232DCE-C
MD-232DTE-C
MD-TIY-C
MD-PPG-C
MD-CPRT-C
MD-CC6
MD-CC12

Wire-wrap card with bussed power and
ground
Wire-wrap card without bussed power
and ground
Extender card
25-pin 0 female MDcable
25-pin D male MD cable
Molex-TIY cable
PROM Programmer (PPG-8/16) interface
cable
MDX-PIO to Centronics Line Printer
Interface Cable
6-slot card cage
12-slot card cage

The MDX-WW2 (MK77952) is a wire-wrap card with all
plated-through holes on a 0.100-inch grid. This allows
mounting of both DIP sockets and discrete components for
circuit fabrication. The plated-through holes accept 0.025inch square posts.

WW2 PHOTO MK77952
Figura 2

WIRE-WRAP CARDS
The MDX-WW1 (MK77959) is a wire-wrap card with bussed
power and ground lines on the board to facilitate fabrication of
circuits using wire-wrap sockets. A series of plated-through
holes are available on the top of the card for mounting
connectors.

WW1 PHOTO MK77959
Figura 1

EXTENDER CARD
The MD-EXT (MK77953) is a card that allows extending cards
for ready access. The card has a ground trace in between
each signal line to minimize stray coupling of the bus signals.

MD-EXT PHOTO MK77953
Figura 3

"280 is a register Trademark of Z1LOG

VIII-1

CABLES

MD-CPRT-C MK79089
Figure 8

The MD-232DCE-C (MK77955) is a cable designed to
interface with either the MDX-SIO or MDX-EPROM/UART.
One end has a 26-pin socket to connect to the board. The
other end has a 25-pin female "D"-type connector. This
allows the board to provide a Data Communication
Equipment interface.

EJ

CENTRONICS
PRINTER

CARD CAGES

MD-232DCE-C MK77955
Figure 4

Two card cage versions. MO-CC6 (MK77973) and MO-CC12
(MK77969). are available from Mostek. Both models have
connectors on O.75-inch centers and the cards are inserted
horizontally.

MDX·SIO
MDX·DEBUG
MDX·EPROMI
UART

MD-CC6 DRAWING WITH DIMENSIONS
The MD-232DTE-C (MK77970) is a cable designed to
interface with either the MDX-SIO or MOX-EPROM/UART.
One end has a 26-pin socket to connect to the board. The
other end has a 25-pin male "0" -type connector. This allows
the board to provide a Data Terminal Equipment interface.

Figure 9

MD-232DTE-C MK77970
Figure 5.
MDX-SIO
MDX-EPROMI
UART
MDX-DEBUG

The MO-TTY-C (MK77956) is a cable designed to interface
with either the MOX-SIO or MOX-EPROM/UART. One end
has a 26-pin socket to connect to the board. The other end has
a Molex connector that allows connection to the terminal
block in a teletype.
MD-TIY-C MK77956 .

The motherboard has eight plated-thru holes in which to
insert 16-gauge wire (max.) for the power and ground
connections. These are designated below:

Figure 6
MOX-SIO
MDX-EPROMI
UART
MDX-DEBUG

2345678

\/ I \/ I I I

The MO-PPG-C (MK77957) is a cable designed to interface
the MOX-PIO with the PPG-8/16 PROM Programmer.

GNO -12V

+5V +12V-5V AUX. GNO.

MD-PPG-C MK77957
Figure 7

The pins are denoted from left to right on the fab side of the
motherboard.
Table 1 shows the interconnection of the power plane to the
STD BUS.
The MO-CPRT-C(MK79089) is a cable designed to interface
the MATRIX System or the MOX-PIO with the Centronics
Line Printer.

VIII-2

Table 1

Connection
Pins (Left to Right)

Designator

STD Bus
PinNo.

1,2
3
4,5
6
7
8

GND
-12V
+5V
+12V
-5V
AUX.GND

3,4
56
1,2
55
5,6
53,54

A connector is available on the lower-right edge of the
motherboard for remoting +12V for a lamp and PB RESET if
the user desires a remote reset switch. The configuration is
shown below.
5
4
3
2
1

+12V
GND
PB RESET
GND
KEY

The diagram shows the relative location ofthe connectors on
the fab side of the motherboard.

Wire is not supplied with the card cage modules.
MD-CC12 DRAWING WITH DIMENSIONS'
Figure 10

t

. . :.1
BOlTOM

FRONT EDGE

MD-CC6/MD-CC12 MOTHERBOARD (FAB SIDE)
NOTE: Two stake pins are provided which are connected to
bus pins 35 (IOEXP) and 36 (MEMEX). These signals are not
used on Mostek MK cards and, if desired, can be wirewrapped to the ground stake pins provided at the bottom of
the motherboard (as shown).

The priority interrupt for the twelve-slot card cage(MD-CC12)
is from bottom to top on the right side, then from bottom to top
on the left side when viewed from the front with the
components facing upward. Thus the bottom-most righthand board is the highest priority board and the top-most
left-hand board is the lowest priority board.

PRIORITY INTERRUPT CHAIN
If a card slot is not used, the user can maintain the priority
interrupt chain by strapping across the unused connector to
the stake pins provided on the assembly side of the
motherboard opposite phlS 51 and 52.

CARD DIMENSIONS

The priority interrupt is from bottom to top on the six-slot card
cage (MD-CC6) when viewed from the front with the
components facing upward.

4.5 in. (11.43 em) high by 6.50 in. (16.51 em) long
0.680 in. (1.71 em) maximum profile thickness
0.062 in. (0.16 em) printed-circuit-board thickness

VIII-3

MD-CC6/MD-CC12 MOTHERBOARD
Figure 11

•
•
-.----------.-

+
•
-.----------.-

1???1
~

=UNUSABLE AREA

MOTHERBOARD LAYOUT
MDX CARD CAGE

«> 1m

_NTIlIOAID

RESISTOR SIPS 3:10/390
I

~

MDX DAUGHTER BOARD

CONNECTORS

Function

Configuration

STD-Z80 BUS 56-pin

0.125 in. centers

Mating
Connector
PRINTED CIRCUIT
Viking 3VH28/1CE5
WIRE WRAP
Viking 3VH28/1CND5
SOLDER LUG
Viking 3VH28/1CN5

Remote

5-pin SIP
0.100 in.. centers

h b b b ~.

~AB. SIDE

U=SPACER FEET (2 PL.I

CONN. HOUSING
AMP 87499-9
CONTACT PINS
AMP87046-1

VIII-4

•

I

ORDERING INFORMATION

DESIGNATOR

DESCRIPTION

PART NO.

MDX-WW1

MD Series wire-wrap card with bussed power and ground

MK77959

MDX-WW2

MD Series wire-wrap card without bussed power and ground

MK77952

MD-EXT

MD Series extender card

MK77953

MD-CC6

MD Series 6-slot card cage with STD BUS motherboard

MK77973

MD-CC12

MD Series 12-slot card cage with STD BUS motherboard

MK77969

MD-232DCE-C

26-pin to 25-pin D -RS232 cable

MK77955

MD-232DTE-C

MD Cable 25-pin D plug to 26-pin socket

MK77970

MD-TIY-C

26-pin to Molex-TIY connector

MK77956

MD-PPG-C

PROM Programmer (PPG-8/16) Interface Cable to MDX-PIO

MK77957

MD-CPRT-C

Centronics Line Printer Interface Cable to MDX-PIO

MK79089

VIII-5

VIII-6

MOSTEl(.
MD SERIES ACCESSORIES

MD-PWR1
. MK77964
FEATURES

o

Triple output supply: +5 volts and

o

115/230 vac ± 10%.47-440 Hz

MD-PWR1 PHOTO

± 12 volts

o Remote sensing on 5V output
o Overvoltage protection on 5V output (standard); optional
on ± 12V outputs
o

± 0.05% regulation

o Foldback current limit
o I.C. regulated design
o UL recognized
o CSA certified

DESCRIPTION
The MD-PWR 1 is an open-frame power supply. Designed to
furnish power for the MDX-PROTO kit. the MD-PWR1
operates from 115/230 vac ± 10% at a frequency range of

47 to 440 Hz. This input power is then transformed and
regulated into the three output voltages. +5 VDC and ± 12
VDC. The open-frame design allows for adequate cooling.

VIII-7

MD-PWR1 BLOCK DIAGRAM

+6V
REGULATOR

+5VDC

117/230VAC

XFMR
+12 VDC
±12V
REGULATORS

ACINPUT
115/230 vac, 47-440 Hz

-12VDC

REMOTE SENSING
Provided on 5V output, open-sense-Iead protection built-in

DC OUTPUT
+5V@6.0A
±12V@1.7A
(Derate output current 10% for 50 Hz operation)

STABILITY
± 0.3% for 24 hours after warm up
TEMPERATURE RATING

.ooe to 50°C full rated

LINE REGULATION
±.05% for a 10% line change

(derate linearly to 40% at 70°C)

LOAD REGULATION
± .05% for a 50"A> load change

TEMPERATURE COEFFICIENT
± .03%/O max.

e

OUTPUT RIPPLE
3.0 mVPk-Pk max.

EFFICIENCY
5V output: 45%, ± 12V output: 55%

TRANSIENT RESPONSE
30 microseconds for 50% load change

VIBRA'lION AND SHOCK
Per MIL-STD-S10B

SHORT CIRCUIT AND OVERVOLTAGE PROTECTION
Automatic current limit/foldback
REVERSE VOLTAGE PROTECTION
Provided on output and pass element.

SIZE
4.75 in (12.07 cm) wide x 11.0 in (27.94 cm) long x
2.75 in (6.99 cm) high

OVERVOLTAGE PROTECTION
Optional on ± 12V outputs

WEIGHT
Sibs (3.6 kg)

ORDERING INFORMATION

DESIGNATOR

DESCRIPTION

PART NO.

MD-PWR1

Power Supply Module with prestripped and tinned wires

MK77964

VIII-S

MOSTEI(.

MD SERIES ACCESSORIES

MO-RMC12
MK77966, MK77975
FEATURES

MD-RMC12 - Frontview

o Standard 19-inch rack-mountable chassis
o Removable structural-foam front panel for internal
access
o Front panel RESET switch and POWER indicator
o 12-slot card cage
o Cards mounted horizontally for ease of cooling and
cable routing
o Self-contained power supply and 115 CFM fan
o 100/1151230 Volt 50/60 Hz operation

DESCRIPTION

MD-RMC 12 - Rearview

The Mostek MO SERIES Rack-Mounted System (MORMC12) provides rack mounting for theMO Series
Microcomputer modules. The system features a selfcontained power supply designed to work on voltages
and frequencies available world wide. A structural foam
front panel is provided with system RESET and POWER
indicator. Thefront panel is designed with quick-release
ball studs so that it can bequickly removed for access to
internal components. Card cage and power supply may
be removed individually from front or top for improved
access. The cards are mounted in a horizontal plane
with provisions for cabli ng over the card cage to the rear
1/0 panel. The back panel has an 1/0 panel prepunched for twelve 25-pin "0" type connectors, one
50-pin "0" connector and one BNC connector. AC
components on the back panel include: OnlOff switch,
voltage selection switch, fuse holder (3AG or 5 x 20
mm), and AC input receptaclelline filter.

VIII-9

MD-RMC 12 - Sideview

MD-RMC 12 - Topview. inside

INPUT POWER: 100/115/230VoltsAC ± 10%
50/60Hz

LINE CORD SUPPLIED:

DC POWER AVAILABLE: +5 VDC at 12A max.
+12 VDC at 1.7A max.
-12 VDC at 1.7A max.

MK77966
Similar to Belden model
17205B

LOAD REGULATION: ± .05% for a 50% load change

MK77975
Similar to Feller model
1100

FRONT PANEL CONTROLS: RESET switch
POWER ON Indicator

OUTPUT RIPPLE: 3.0 mV Pk-Pk max.
TRANSIENT RESPONSE: 30 microseconds for a 50%
load change
SHORT CIRCUIT AND
OVERLOAD PROTECTION: Automatic current
limit/foldback

REAR PANEL CONTROLS: AC
AC
AC
AC

Power On/Off
fuse holder
line receptacle/filter
line volta.ge selector

WEIGHT: 25 Ibs (11.3 kg)
OVERVOLTAGE PROTECTION: +5 Volt output. set to
6.2 ± 0.4 Volts
STABILITY: ± 0.3% for 24 hours after warmup
THERMAL PROTECTION: Bi-metal thermostat on
primary AC line set to cut
out at 180°F (82°C)
CARD CAGE: Twelve-slot for MD series module
11.4cm x 16.5 cm (4.5 x 6.5 in). No PC
modules are supplied.
FUSING:
Line
Voltage
110/115V
230V

CHASSIS: a) 19" rack-mountable using thetwo rails
supplied
b) Slide mounting available with optional slide
mounting kit. Requires two inches of panel
space below the unit.
OPERATING TEMPERATURE RANGE: O°C to 60°C
HEIGHT: 7.0 in. (17.8cm) panel space
7.3 in. (18.5cm) overall, including feet
WIDTH: 19.0 in. (48.3cm) at front panel
17.5 in. (44.5cm) behind front panel

MK77966
3 Amp 3AG*
1.5 Amp 3AG

*Configuration as shipped

MK77975
3 Amp5 x 20 mm
1.5 Amp
5 x 20mm*

DEPTH: 21.1 in. (53.6cm) with all protrusions
20.0 in. (50.8 cm) without foam front
HUMIDITY: Up to 90% relative. non-condensing

VIII-10

ORDERING INFORMATION
DESIGNATOR

DESCRIPTION

MD-RMC12

Rack-mounted CPU subsystem with MD series 12-slot card MK77966
cage with U.S. line cord and fuse. 100/115/230 Volts
50/60Hz AC operation. front panel. support bracket for rack
mounting. and Operation Manual included.

MD-RMC12-50

Same as above except with 5 x 20mm fuse and European
line cord.

PART NO.

MD-RMC12 Operations Manual Only

VIII-11

MK77975
MK79738

VIII-12

MOSTEI(.
PERIPHERAL

RMDFSS
MK78183, MK78185
FEATURES

RMDFSS PHOTO

o Standard 19-inch rack-mountable chassis; 7-inch panel
height

o Removable structural foam disk bezel for internal access

o

Front panel POWER-ON indicator

o

Mounts two standard 8-inch floppy disk drives

o

Disks mounted horizontally for low profile

o

Self-contained power supply and 115 CFM fan

o 100/1151230 Volt, 50/60 Hz operation
GENERAL DESCRIPTION
The Mostek RMDFSS offers a solution to rack mounting two
standard 8-inch floppy disk drives. The system features a
self-contained power supply designed to work on voltages
and frequencies available worldwide. An attractive
structural foam-front disk bezel is provided with a power-on
indicator. The disk bezel is designed with quick-release ball
studs so that it can be easily removed for access to the
drives. The drives are mounted in a horizontal plane for a
low-profile appearance and to conserve panel height in the
rack. Drives and power supply may be removed individually

from front or top for ease of maintenance. The back panel
has an I/O panel prepunched for one 50-pin "D" interface
to the disk controller. AC components on the back panel
include: On/Off switch, voltage selection switch, fuse
holder (3AG or 5 x 20 mm) and AC input receptacle/line
filter.

VIII-13

INPUT POWER

LINE CORD SUPPLIED

100/1151230 Volts AC ± 10% 50/60Hz
50Hz
MK78185

MK78183
Similar to Belden
model
17205B

60Hz
MK78183

MK78185
Similar to Feller
model
1100

DC POWER AVAILABLE
FRONT PANEL INDICATOR

+5 VDC at 3.0A max.
-5 VDC at 0.5A max.
+24 VDC at 3.4A max.

Power-on

REAR PANEL CONTROLS
LOAD REGULATION

AC Power On/Off
AC fuse holder
AC line receptacle/filter
AC line voltage selector

± .05% for a 50% load change
OUTPUT RIPPLE
3.0 mV PK-PK max.

WEIGHT

TRANSIENT RESPONSE

50 Ibs (22.7 kg)

30 microseconds for a 50% load change

OPERATING TEMPERATURE RANGE
SHORT CIRCUIT AND OVERLOAD PROTECTION

O°C to 40°C (Disk Media Limitation)

Automatic current limit/foldback

DIMENSIONS

OVERVOLTAGE PROTECTION
+5 Volt output set to 6.2

Height: 7.0 in. (17.8 cm) panel space
7.3 in. (18.5 cm) overall, includes feet

± 0.4 Volts

Width: 19.0 in. (48.3 cm) at front panel
17.5 in. (44.5 cm) behind front panel

STABILITY

± 0.3% for 24 hours after warmup

Depth: 21.1 in. (54.0 cm) with all protrusions
20.0 in. (50.8 cm) without foam front

THERMAL PROTECTION
Bi-metal thermostat on primary AC line set to cut out at
180°F (82°C)

HUMIDITY
Up to 90% relative, noncondensing.

DISK DRIVES
Shugart 800-2 or equivalent

FUSING
Line

MK78183

MK78185

Voltage
110/115V

3 Amp 3AG*

3Amp5x20 mm

230 V

1.5 Amp 3AG

1.5 Amp
5 x 20mm*

*Configuration as shipped

VIII-14

ORDERING INFORMATION
DESIGNATOR

DESCRIPTION

PART NO.

RMDFSS

Rack-mountable dual floppy enclosure with 8-inch drives for
100/1151230 Volt operation. Includes interface cable to SDERMC6 or MD-RMC12, front disk bezel, support bracket for rack
mounting and Operations Manual. 60Hz model.

MK78183

RMDFSS-50

50 Hz model.

MK78185

RMDFSS Operations Manual Only

MK79740

VIII-16

MICRO SYSTEMS DATA BOOK

MOSTEI(.
MD SERIES DATA PROCESSING

MO-SBC1
MK77851-0
FEATURES

MD-SBC1 BOARD PHOTO

o Z80 Microprocessor

o

2K byte RAM capacity with 1 K included

o

Sockets for 8K bytes 2716 EPROM

o

Crystal clock - 2.5 MHz

o

Three TTL-buffered 8-bit OUTPUT ports

o

Two TTL-buffered 8-bit INPUT ports

o

Two interrupt inputs

o

Single +5 volt power supply

DESCRIPTION
The MD-SBC1 is a complete Z80-based microcomputer on
a 41h inch by 61h inch circuit module. All 1/0 is fully TTLbuffered and is brought to a 56-pin edge connector.
The smaller card size and the single power supply makes
the MD-SBC1 easierto package and easierto use than most
other modules. While the module size is small, no
compromises have been made in computing power due to
increasing MOS-LSI densities and the use of the Z80
microcomputer. The 40 buffered TTL 1/0 lines and the 8K
bytes of EPROM provide the capability to solve many control
problems encountered by the OEM microcomputer user.
The expandable MD Series (MDX) has the same form factor
allowing easy expansion to a multi-board system with
increased capability.

sockets are provided for up to 8K byte of EPROM, and are
decoded in 2K blocks starting at address zero. The output
ports are 74LS244 latches which are brought to the card
cage connector. The input ports are 74LS240 Octal Buffers
with 4.7K Ohm pull-up resistors on the inputs. These input
lines are also brought to the edge connector. The Z80-CPU
is driven by a crystal clock at 2.5MHz (400nsec T-State).
Both the NMI and INT interrupt inputs to the Z80-CPU are
terminated with 4.7K Ohm pull ups and brought to the card
edge connector. An external clock can be used by changing
strapping options on the board. Power-on-reset circuitry is
included on the CPU's RESET input. Provision is made to
expand the 1/0 capability through the use of on-board
connectors.

Figure 1 is a block diagram of the MD-SBC1. The basic
module comes with 1 K bytes of· RAM expandable to 2K
bytes by the addition of two 2114~type RAMs. Four 2716

IX-1

MD-SBC1 BLOCK DIAGRAM
Figure 1

a
MASKABLE
INTERRUPT
NON·MASKABLE
INTERRUPT

'M6M~&

PROCESSOR

zao

~

RESET

~

EXTERNAL
CLOCK ~

INPUT
PORT 01
DATA

a

8

a

a

PROM.'

';R6{l2

a

,~~4!1)'a.

ADDRESS
BUS

a,

,J9~I!'}a
6

1924;~a

a

OUTPUT
PORTS

a

If9t~~a

~'R'A~'
INPUT
PORT 00
DATA

OUTPUT
PORT 00
DATA
OUTPUT
PORT 01
DATA
OUTPUT
PORT 02
DATA

a

,,~O}':~,

VRo~:3
ON·BOARD
CLOCK
GENERATOR
2.5 MHz

a,

DATA BUS

INPUT
PORTS

~

a

RAM

1024xa

J1 . J2

a

BUS AND
DECODED STROBES
TO I/O PORTS 02·07

DATA BUS

SHADING INDICATES SOCKETS ONLY

WORD SIZE

MEMORY SPEED REQUIRED

Instruction:
Data:

8, 16, 24 or 32 bits
8 bits

CYCLE TIME
Clock period (T state):
Instruction Cycle:

400 ns at 2.5 MHz
Min. 4 T states
Max. 23 T states

Memory

Access Time
Required

Cycle Time
Required

2716*
2114

450nsec
450nsec

450nsec
450nsec

*Single 5 volt type required

1/0 ADDRESSING AND CAPACITY

MEMORY CAPACITY
8K bytes of 2716 memory (none included)
2K bytes of 2114 memory (1 K bytes i ncl uded)

Port Type

HEX
Address

Data
Capacity

Input
Output

00 and 01
00,01,02

16 lines
24 lines

MEMORY ADDRESSING
I/O INTERFACES
EPROM
Number

HEX
Address

0
1
2
3

0000-07FF
08oo-0FFF
1000-17FF
1800-1 FFF

RAM
Number

HEX
Address

Standard
Optional

2000-23FF
24oo-27FF

Inputs:
Outputs:

One 74LS load plus a 4.7K-Ohm pull up
resistor
IOH =-3mA at VOH = 2.4 volts
IOL = 24mA at VOL =0.5 volts

INTERRUPTS
Two (active low:) NMI and INT, See Z80 CPU (MK3880)
Technical Manual for a full description of
Z80 interrupts,
IX-2

SYSTEM CLOCK

MD-SBCl

CARD DIMENSIONS
MIN

MAX

250kHz

2.5MHz

4.5 in. (11.43 cm) high by 6.50 in. (16.51 cm) long
0.48 in. (1.22 cm) maximum profile thickness
0.062 in. (0.16 cm) printed circuit board thickness
CONNECTORS

OPERATING TEMPERATURE RANGE
Function

Configuration

STD-Z80 BUS 56-pin

Mating
Connector
PRINTED CIRCUIT
Viking 3VH-28/
lCE5

0.125 in. centers
POWER SUPPLY REQUIREMENTS

WIRE WRAP
Viking 3VH-28/
lCND5

+5 volts ± 5% at 1.2A max (fully loaded)
(1 OOmA per RAM, 1OOmA per EPROM)

SOLDER LUG
Viking 3VH-28/
lCN5

ORDERING INFORMATION

DESIGNATOR

DESCRIPTION

PART NO.

MD-SBCl

Complete Z80 Single Board Computer with Operations
Manual less EPROMs and mating connector.

MKi7851-0

MD-SBCl Operations Manual only.

MK79609

IX-3

MICRO SYSTEMS DATA BOOK

MOS I '[1(.
SDE SERIES DATA PROCESSING

OEM-SOE
MK78122, MK78124-3
FEATURES

OEM-80E BOARD PHOTO

o Z80CPU
o 20K x 8 EPROM
o Accepts 2708, 2716, or 2532 EPROM's
o 256 x 8 static scratchpad RAM on-board
o 16K (4K) x 8 dynamic RAM
o Z80 CTC - four counter/timer channels
o Restart to OOOOH or EOOOH (switch option)
DOn-board serial I/O port
o Software-programmable baud rate
o Current loop or RS-232-C (V.24) interface
o Four 8-bit parallel ports with handshake
o Ports buffered with TTL, socket-programmed

16K bytes on-board. The Z80 built-in refresh logic reduces
the area taken by the dynamic RAMs to that required by
other manufacturers' 1K byte static RAM, the cost per bit
being significantly reduced. Also on-board are two memorydecoding bipolar PROMs. These allow a wide range of
RAM/PROM/ROM combinations to be selected by the
user; if the exact combination required is not already
supported, new PROMs can be easily programmed.

o Port direction in 4-bit blocks
o Programmable polarity on strobe lines
o Halt lamp
o Power-on-reset logic

The user switch-selectable restart address allows the DDT80 debug program to reside in the system without conflict
with the user's own PROM-based software. If a problem
develops, the user can switch from address 0 reset to
address EOOO(where DDT-80 resides) and use the powerful
commands of the 2K byte DDT-80 to localize the problem.

o Fully hysteresis-buffered SDE bus

DESCRIPTION
The OEM-80E is a Z80 CPU-based computer board. The
card has sufficient on-board I/O and memory to be used in a
stand-alone mode in many applications, yet it is fully
expandable to support more memory and I/O in
applications requiring it. The five EPROM sockets on-board
can be strapped to use a number of standard 24-pin
ROM/EPROM products including PROMs and ROMs with
capacities of up to 4K bytes each. The eight RAM sockets
can be strapped for 4K or 16K RAMs, giving a maximum

The "E" format and DIN connectors allow quick integration
into the user's system hardware. Putting all connectors on
one card edge is a unique feature in microcomputer
modules, although it is standard design practice for many
large system builders. The simplified maintenance and
clean cabling made possible by this technique should be
appreciated by all experienced users.

X-1

MEMORY ADDRESSING AND CAPACITY

COUNTER/TIMER CHANNELS

The recommended memory map is shown below:
00OO-3FFF PROM (1 TO 16K)
4000-7FFF RAM (4 TO 16K)
8000-DFFF EXTERNAL MEMORY
EOOO-E7FF DDT-80 (2K)
E800-FEFF EXTERNAL MEMORY
FFOO-FFFF SCRATCHPAD RAM (256 bytes,
needed only if DDT-80 is used)

Four counter/timer channels are provided on the card in a
Z80-CTC chip. One channel is used as the baud rate
generator of the serial I/O port. The other three channels
are ava ilable to the user. The channels may be programmed
as delay generators, event counters or simply discrete
interrupt inputs with a programmable edge trigger. The
device can generate four interrupts.
INTERRUPTS

Memory cycle time required for the PROMs is 450 ns.
The OEM-80E has nine on-board interrupts. They are:
One Z80 CPU NMI (non-maskable interrupt)
Four Z80 PI0(2) Mod 2 Interrupts
Four Z80 CTC Mod 2 Interrupts
SERIAL I/O PORTS
A UART with 20mA current loop and RS-232-C (V.24)
buffers/drivers provides a serial communication channel
for interfacing to TTY or CRTterminalsor serial printers. The
baud rate is software-programmable over the range of 110
to 9600 baud.

PARALLEL I/O PORTS
The four parallel ports are designed to allow maximum
flexibility in matching the MOS I/O ports tothe real world of
long lines or high Voltages. Two ports support bidirectional
TTL I/O with hystersis inputs. The ports can also be
programmed for input or output only. The other ports are
supplied with sockets which support a number of standard
TTL devices for buffering. A list of pin-compatible devices is
given below:

More interrupt devices (up to 128 total) can be added to the
SDE bus.
BUS INTERFACE
All Z80 signals are buffered before leaving the OEM-80E.
The buffering protects the MOS components from static
charge during handling and from bus transients which
could otherwise destroy these devices. The bus supports
DMA transfers and the daisy-chained, mUlti-level interrupt
structure oftheZ80. The bus uses hystersis-input receivers
and current-limited bus drivers to improve the noise margin
of the bus. Switching the bus drivers on only when data is
needed and stable further reduces the noise on the bus.
POWER REQUIREMENTS
+5V ±5% at 1.5 A
+12V ±5% atO.175 A
-12V ±5% at 0.1 A
OPERATING TEMPERATURE RANGE
DOC to 50°C

TYPE
7400
7402
7408
7426
7437
7438

USE
16mA TTL inverting output
TTL inverting input
16mA TTL non-inverting output
16mA high-voltage inverting opencollector output
48mA TTL inverting output
48mA TTL inverting open-collector output

BOARD SIZE
233.4mm (9.19 in) X 250 mm (9.84 in.)
CONNECTORS
Two 64-pin DIN 41612 (a-c) indirect, male

X-2

ORDERING INFORMATION

D ESIGNATOR

DESCRIPTION

PART NO.

oEM-80E/4

OEM-80E/4 with 4K bytes of RAM (MK4027), 5 sockets for
EPROM or ROM, 2 PIOs with sockets for TIL buffering logic,
CTC, UART, socket for 256-byte scratch-pad RAM and sockets
for memory mapping PROMs.

MK78122

oEM-80E/16

Same as OEM-80E/4 except with 16K bytes of RAM
(MK4116)

MK78124

OEM-80E Operations Manual only

MK78548

X-3

X-4

MICRO SYSTEMS DATA BOOK

. . . -=

~===-=-==..:::-:.

___ Peripherals I

MOSTEl(.

SDESERIES INPUT/OUTPUT

A/D-SOE
MK78172-42, MK78172-56,
MK78175-40, MK78177-26
FEATURES

A/DeBOE BOARD PHOTOS

A/D-80E/1791 - Analog Input/Output Board
MK78172-42
o Input ranges: ± 5V
±10V
o -10V
0- 5V

o

16 Single Ended Input Channels

o

12 Bit AID Converter

o

Programmable Gain Option

0.

2 D/A Output Channels with Scope Control

A/D-80E/1791 - Analog Input/Output Board
MK78172-56

o

Input ranges: ± 5V
±10V
o -10V
0- 5V

o

32 Differential Input Channels

o

12 Bit AID Converter

o 2 DIA Output Channels with Scope Control

o 12 Bit AID Converter
o Programmable Gain Option

A/D-80E-1798 - Analog Input Board

o 2 D/A Output Channels with Scope Control

MK78177-26

A/D-80E-1795 - Analog Input/Output Board

o Wide-range, Isolated Inputs'

MK78175-40

o Input Ranges: ± mV to ±10V

o Low-level, Wide-range Input

o 4 Double Ended Input Channels

o Input Ranges: ± 1OmV to ± 10V

o 12 Bit AID Converter

o 16 Single Ended Input Channels

o Programmable Gain Option

XI-1

A/D-80E BLOCK DIAGRAM

0-4

r--...;::s~---k

____ RD OAT 1

L~:"':::~~~:':":'_~---- RD OAT 2

PORT DECODE &
BUFFER CTl

DATA

ADDR

(8)

(8)

DESCRIPTION

A/D-80E INTERFACE

The A/D-BOE line of analog 1/0 systems is offered as a part
of the SD Series. Available in four different versions with
various user-specified options, the A/D-BOE can be
contoured with the right combination of analog 1/0 to meet
the system designer's needs.

The ZBO-PIO chip and some external logic are utilized to
provide the interface for the A/D-BOE. In this manner, the
ZBO-PIO chip is used to provide all the interrupt circuitry for
ZBO-Mode 2 operation, i.e., a vectored daisy chain priority
interrupt structure.

The A/D-BOE line of analog 1/0 boards has been designed
using DATAX-IITM data acquisition modules
manufactured by Data Translation, Inc. Each DATAX
module is a complete self-contained unit with multiple
shielding for operation in a microprocessor system. This
eliminates ground-loop and noise problems inherent in
interconnection of separate modules.

XI-2

A/D-SOE ANALOG INPUT SPECIFICATION
A/D-SOE/1791

A/D-SOE/1795

A/D-SOE/179S

Number of channels

16 single ended
or 32 differentia I

16 single ended

4 differential

Input Impedance

100 megOhm

100 megOhm

10 megOhm

Input Overvoltage

±35V non-destructive

±15V non-destructive

15V DC max.

Input Range

0-5V, ±5V, 0-1 OV,
±10V

±1 OmV to ±1 OV

0-10V unipolar, ±10V
bipolar

Optional programmable

gains: 1, 2, 4, S

Not Available

gains: 1, 10, 100, 500

Conversion resolution

12 bits

12 bits

12 bits

Linearity

±Y2 LSB

±Y2 LSB

±Y2 LSB

Inherent quantizing error

±Y2 LSB

±Y2 LSB

±Y2 LSB

Stability Tempco

±25ppm/ DC, F.S.R.

±30ppm/DC

Zero - ±20 micro Volt/DC
Full Scale - ±30ppm/ oC

T hroughput

35kHz stand.
100kHz optional

31kHz

20 H~ random
40 Hz Sequentiar;

Power Requirements

+5V @ 2.0A Max

+5V @ 2.0A Max

+5V @ 2.0A Max

Mechanical printedcircuit board

S.5" x 12.0" x .65"

S.5" x 12.0" x .65"

S.5" x 12.0" x .65"

Temperature

00

00

00

Implementation

Programmed 1/0 and
Interrupt Functions

Programmed 1/0 and
Interrupt Functions

Programmed 1/0 and
Interrupt Fu nctions

Device address

Selectable via
jumper

Selectable via
jumper

Selectable via
jumper

_

700

-

70 0

_

70 0

ANALOG OUTPUT SPECIFICATIONS
Resolution -

12 Bits

Linearity -

±Y2 LSB

Range -

±10V, 0-1 OV; @ 25mA
minimum current output, all
jumper selectable

Relative Accuracy-

±O.025%

Full Scale Settling -

0.1 % - 1 microsecond, 0.01 %
- 3 microsecond into 50 ft.,
coaxial cable terminated with
470 Ohm

Z Axis Control -

The Interface contains all the
control circu itry of Z axis and
scope control mode bits

Z Output (I ntensity) -

LO (O.BV) to HI (2.4V) TTL
compatible into 50 Ohm
termination

Z Risetime-

100 nsec into 50 ft. of
terminated COAX

Z Pulse Width -

Temperature Coefficient - 25ppm/oC

XI-3.

J

Jumper Selectable
a. 0.5 microsecond
b.5 microsecond
c. external RC 1 microsecond
to 0.5 msec

ORDERING INFORMATION
DESIGNATOR

DESCRIPTION

PART NO.

AlD-80E/1791-16

High Level, Analog Input/Output (16 S.E. Input!?)

MK78172-42

AlD-80E/1791-32

.High.Level, Analog Input/Output (32 D.E. Inputs)

MK78172-56

A/D-80E/1795

Low Level, Non-Isolated Analog Input/Output

MK78175-40

A/D-80E/1798

Wide Range Isolated Analog Input

MK78177-26

AlD-80E Operations Manual Only

MK79660

XI-4

..

MOSTEI(.

SD SERIES INPUT/OUTPUT

DCC-SOE
MK78192
FEATURES

DCC-80E BOARD PHOTO

o Four independent full-duplex channels
o Independent programmable baud rate clocks
o Data rates - 75 to 38.4K bits per second
o Receiver data registers quadruply-buffered
o Transmitter data registers double-buffered
o Asynchronous operation
o Binary synchronous operation
o HDLC or IBM SDLC operation
o Both CRC-16 and CRC-CCITT (-0 and -1) hardware
implemented
o Modem control
o Operates as DTE or DCE
o Serial input and output as RS-232-C
o Address programmable
o Compatible with SDE BUS
o 4-Channel NRZI encoder/decoder

DESCRIPTION
The Multichannel Serial Input/Output Module, DCC80E, is designed to be a multiprotocol asynchronous or
synchronous I/O module for the SDE BUS. The module
is designed around the Mostek® MK3887™ Z80-S10
which provides two full-duplex .serial data channels.
Each channel has an independent programmable baud
rate clock generator to increase module flexibility. Each
channel is capable of, handling asynchronous, synchronous, and synchronous bit-oriented protocols such
as IBM BiSync, SDLC, HDLC, and virtually any other
serial protocol. It can generate CRC codes in any
synchronous mode and can be programmed by the CPU
for any traditional asynchronous format. The serial

input and output data is fully buffered and is provided at
the connector as RS-232-C levels. A modem control
section is also provided for handshaking and status. The
module can be jumper-configured as a data terminal
(DTE) or as a modem (DCE) in order tofacilitate a variety
of interface configurations.
Figure 1 is a block diagram of the DCC-80E module
which consists of eight main elements: the channel
configuration headers, line drivers and receivers,
MK3887 Z80-SIO, programmable CTC baud rate
generators, address decode, NRZI encoder/decoder,
clock circuitry, and data bus buffers. Input and output to
the board is provided via the SK2 connector. The
configuration and pin out headers of each channel are
identical.
Several features are available as options that are
selected by the port-configuration header. The headers
are used to select the orientation of the data
communication interface. The DCC-80E can be selected
to act as either a terminal or processor (Data Terminal
Equipment - DTE) or as the modem (Data Communications Equipment - DCE). The channelcconfiguration

DCC-80E BLOCK DIAGRAM
Figure 1

CTC
AS

BAUD
RATE'
AND

, SID

CHANNEL

TIME
OllT

SK1
SYSTEM,
BUS

BOARD LEVEL

1-0

BUS

headers allow reconfiguration of data interchange and
signals. This allows the data to be asynchronous or
synchronous serial stream or synchronous NRZI
encoded.
Line drivers and receivers provide the correct electrical
signal levels, slew rate and impedance for interfacing
RS-232-C peripherals.

The Mostek MK3887 Z80-SIO is the central element of
this module. This device is a multifunction component
designed to satisfy a wide variety of serial data
communications requirements in microcomputer systems.lts basic role is that of a serial-to-parallel, parallelto-serial converter/controller, but within that role it is
configured by software programming so that its
function can be optimized for a given serial data
communications application. The MK3887 provides two
independent, full-duplex channels: A and B. Each
channel features the following:
ASYNCHRONOUS OPERATION
- 5, 6, 7. or 8 bits/character
- 1. 1 112 or 2 stop bits
- Even. odd or no parity

- X1. x16. x32. and x64 clock modes
- Break generation and detection
- Parity. Overrun, and Framing error detection
BINARY SYNCHRONOUS OPERATION
- One or two sync characters in separate registers
- Automatic sync character insertion
-CRC generation and checking
HDLC OR IBM SDLC OPERATION
- Automatic Zero Insertion and Deletion
- Automatic Flag Insertion
- Address Field Recognition
- I-Field Residue Handling
- Overrun protection for valid receive' messages
- CRC generation and checking
The MK3887 also provides modem control inputs and
outputs as well as daisy~chain priority interrupt logic.
Eight different interrupt vectors can be generated by the
SIO in response to various conditions affecting the data
communications channel transmission and reception.
Address decoding. SDE BUS interface and bus
management for the module are performed by the
Address Decode and Data Bus circuit. The DCC-80E

XI-6

contains command registers that are programmed to
select the desired operational mode. The addressing
scheme is as follows:
PORT
ADDRESS

PORT
FUNCTION

X 0H .. .
X 1H .. .
X 2H .. .
X 3H .. .

CTC as baud-rate generator for Channel A
CTC as programmable timer
SIO Data Input/Output of Channel A
SIO Status/Control for Channel A

X 4H .. .
X 5H .. .
X 6H .. .
X 7H .. .

CTC as baud rate generator for Channel B
CTC as programmable timer
SIO Data Input/Output of Channel B
SIO Status/Control for Channel B

X 8H
X 9H
X AH
X BH

CTC as baud rate generator for Channel C
CTC as programmable timer
SIO Data Input/Output of Channel C
SIO Status/Control for Channel C

.. .
.. .
.. .
.. .

X CH .. .
X DH .. .
X EH .. .
X FH .. .

STANDARD BAUD RATE
Table 1

Standard Baud Rate
Asynchronous
50
75
110
150
300
600
1200
2400
4800
9600
19,200
38.400

CTC as baud generator for Channel D
CTC as programmable timer
SIO Data Input/Output of Channel D
SIO Status/Control for Channel D

Synchronous

600
1200
2400
4800
9600
19,200
38.400

OPERATIONAL FEATURES
The channel interface connects DCC-80E to data
terminal/communications equipment. It consists of
four basic parts.

The CTC channels used as baud rate generators are
controlled through ports XOH, X4H, X8H, and XCH.

1. Drivers and Receivers for RS-232-C
2. NRZI encoder
3. NRZI clock recovery circuit

Remaining ports (X1 H, X5H, X9H, XDH) may be used as
programmable timers for Time-Out checks.

Operation of DCC-80E can be tailored to any functional
environment by means of prewiring two jumper fields,
per channel, to one desired configuration.

Ports X2H, X6H, XAH, and XEH are data channels of
Z80-S10 devices. The CPU loads them with data to be
sent and conversely reads back data assembled in the
receiver buffer.

WORD SIZE
The write registers 0-7 of the SIO are preset by write
operation on ports X3H, X7H, XBH, AND XFH to control
proper operation.

Data: 5,6,7,8 bits
I/O addressing: 8-bits
I/O CAPACITY

(The X indicates the binary code necessary to represent
which one of the 64 port addresses is selected.)

Serial: Four full-duplex serial ports, either synchronous
or asynchronous. Special control registers and circuitry
to permit implementation of SDLC, BiSync, Monosync,
HDLC, and other formats can be programmed. All
synchronous formats can be NRZI encoded.

SERIAL BAUD RATES
Each channel has an individual programmable baud
rate generator. The X1 multiplier on the Z80-S10 must
be used in the synchronous mode. The X16, X32, or X64
Z80-S10 clock rate can be specified for the asynchronous mode. Table 1 indicates the possible baud
rates available for both operation modes.

I/O ADDRESSING
On-board fully programmable

XI-7

INTERRUPTS

OPERATING TEMPERATURE

Generates vectored interrupts to 32 different locations
corresponding to conditions within four SIO channels
and four CTC channels. Interrupt vector location
programmable. Daisy-chained priority interrupt
circuitry.

O°C to 50°C

+12 volts± 5% at 120mA max.
-12 volts ± 5% at 80mA max.
+5 volts ± 5% at 1.2 A max.

SYSTEM CLOCK

DCC-80E

POWER SUPPLY REQUIREMENTS

MIN.

MAX.

250kHz

2.5MHz

SYSTEM INTERRUPT UNITS (SIU)

=3

CARD DIMENSIONS
233.4 mm x 257.62 mm x 25 mm

ORDER INFORMATION
DESIGNATOR

DESCRIPTION

PART NUMBER

DCC-80E

Four-channel data communication controller module with
operations manual.

MK78192

DCC-80E Operations Manual Only

MK79812

XI-8

MOSI'[I(.
SD SERIES INPUT/OUTPUT

FLP-80E
MK78146
FEATURES

FLP-80E BOARD PHOTO

o

Soft-sector format compatible with IBM 3740 data entry
system format

o

Capable of controlling up to four flexible disk drives per
subsystem

o

Full disk initialization (Formatting)

o

Full-sector (128 bytes) FIFO buffering for data

o

Double buffering for.control and status

o

Automatic track-seek with verification

o

Completely interruptable for real-time systems

APPLICATIONS

o

Flexible disk-drive interface for use with Mostek's
Software Development Board (OEM-80E) in a disk-based
Z80 Development System (MATRIX).

o

Single or multiple flexible disk-drive controller/formatter
for disk-based OEM systems using the OEM-80E Single
Board Computer.

DESCRIPTION
The FLP-80E is an add-on flexible disk controller module
used to interface up to fourflexible disk drives to the Mostek
Software Develol?ment Board (QEM-80E).
The FLP-80E provides the necessary electronics to

accomplish track selection, nead loading, data transfer.
error detection. flexible drive interface. status reporting and
format generation/recognition. The FLP-80E is designed to
operate with either Shugart SA-800 Single-Sided or SA850 Double-Sided Flexible Disk Drives. In addition to
functioning as an add-on card tothe OEM-80E system. the
FLP-80E may be utilized directly in OEM applications to
control/format up to four flexible disk drives of either singleor dual-sided type in 8080A or Z80 systems.

. XI-9

FLP-80E BLOCK DIAGRAM

DRIVE &

S~~:~E~:~: }

.

WRTGATE DIRECTION STEP

V
CONTROL INTERRUPT
LINES

ADDRESS
BUS

+12V +12V +5V"=

DATA
BUS

AVAILABLE SOFTWARE

POWER SUPPLY REQUIREMENTS (Typical)

Software for the FLP-80E disk controller is the Mostek Disk
Operating System (FLP-80DOS). A user can easily design
his own OEM software package around 20 powerful disk
operating system commands permitting complex record
insertion, deletion, and position manipulation. Other
software includes· application pacJ~"':'incl'lJde another file within an assembly.
NAME
program name definition.
assembly language source statements, it may be applied to
any ASCII text delimited by '~carriage returns".
ORG
program origin.
PSECT
- ' program section definition.
The Editor has a pseudo-macro command processing
EJECT
- eject a page of listing.
option. Up to two sets of commands may be stored and
TITLE
- place heading at top of each page of listing.
processed at anytime during the editing process. The Editor
LIST
- turn listing on.
'
allows the following commands:
NLiST
- turn listing off.

w-

An Advance record pointer n records.
Bn Backup record pointer n records.
Cn dS1dS2d - Change string S1 to string S2 for n
occurrences.
Dn Delete the 'next n records.
En Exchange current records with records to be
inserted.
If n = 0, reduce printout to console device (for
Fn TIY and slow consoles). '
1I
Insert records.
Go to line number n,
Ln Mn Enter commands into one of two alternate
command buffers (pseudo-macro). '
QQuit - Return to Monitor.
Sn dS1 d -Search for nth occurrence of string S1.
TInsert records at top of
before first record,
Vn Output n records to console device.
Wn Output n records to Logical Unit Number fi~e
(LUN 5) with line numbers.
Xn Execute alternate qommand buffer n.

file

Z80 ASSEMBLER - ASM
The FLP-80DOS Assembler reads standard

zao

source

RELOCATING !..INKING LOADER - RLL
The Mostek FLP-80DOS Relocating Linking Loader
provides state-of-the-art capability for loading programs
into memory: Loading and linking of any number of
relocatable or nonrelocatable object modules is done in one
pass: A non-relocatable module is always loaded at its
starting address as defined by the ORG pseudo-op during
.asse'intily: A relocatable object module can be positioned
anywhere in 'memory at an offset address.
The Loader automatically links and relocates global symbols
which are used, to provide communication or linkage
between program modules. As object modules are loaded, a
table containing global symbol references and definitions is
built Lip .. Thesym!:lol table can be printed to list all global
symbols' and their •load address. The number of object
modules which can be loaded by the Loader is limited only
by the amountof RAM available for the modules and the
symbol table~
, The Lo~der also loads industry-standard non-relocatable,
non-linkab'le object modUles.

XIV-2 .

LINKER - LINK

INPUT10UTPUT CONTROL SYSTEM - 10CS

The Linker provides capability for linking object modules
together and creating a binary (RAM image) file on disk. A
binaryfile can be loaded using the Monitor GET or IMPLIED
RUN command. Modules are linked together using global
symbols for communication between modules. The linker
produces a global symbol table and a global cross reference
table which may be listed on any output device.

The first package is called the 1/0 Control System (lOCS).
This is a generalized blockerIdeblocker which can interface
to any device handler. Input and output can be done via the
10CS in any of four modes:
1. Single-byte transfer.
2. Line at a time, where the end of a line is defined by
carriage return.
3. Multibyte transfers, where the number of bytes to be
transferred is defined as the logical record length.
4. Continuous transfer to end-of-file, which is used for
binary (RAM-image) files.

The Linker also provides a library search option for all global
symbols undefined after the specified object modules are
processed. If a symbol is undefined, the Linker searches the
disk for an object file having the file-name of the symbol. If
the file is found, it is linked with the main module in an
attempt to resolve the undefined symbol.

PERIPHERAL INTERCHANGE PROGRAM - PIP
The Peripheral Interchange Program provides complete file
maintenance facilities for the system. In addition, it can be
used to copy information from any device orfile to any other
device or file. The command language is easy to use and
resembles that used on DEC minicomputers. The following
commands are supported:
COMMAND
APPEND
COPY
DIRECT
ERASE
FORMAT
INIT
RENAME
STATUS
QUIT

FUNCITON
Append files.
Copy files from any device to another
device or file.
List Directory of specified Disk Unit.
Delete a file.
Format a disk.
Initialize the disk handler.
Rename a file.
List number of used and available sectors
on specified disk unit.
Return to Monitor.

The first letter only of each command may be used.

The 10CS provides easy application of 1/0 oriented
packages to any device. There is one entry point, and all
parameters are passed via a vector defined by the calling
program. Any given handler defines the physical attributes
of its device which are, in turn, used by the 10CS to perform
blocking and deblocking.
FLOPPY DISK HANDLER - FDH
The Floppy Disk Handler (FDH) interfaces from the 10CS to a
firmware controller for up to four floppy disk units. The FDH
provides a sophisticated command structure to handle
advanced OEM products. The firmware controller interfaces to Mostek's FLP-80E Controller Board. The disk
format is IBM 3740 soft sectored. The software can be
easily adapted to double-sided and double-density disks.
The Floppy Disk Handler commands include:
- erase file
- create file
- open file
- close file
- rename file
- rewind file
- read next n sectors
- reread current sector
- read previous sector
- skip forward n sectors
- skip backward n sectors
- replace (rewrite) current sector
- delete n sectors

DISK OPERATING SOFTWARE
The disk software, as well as being the heart of the MATRIX
development system, can be used directly in OEM
applications. The software consists of two programs which
provide a complete disk handling facility.

The FDH has advanced error recovery capability. It supports
a bad sector map and an extensive directory which allows
multiple users. The file structure is doubly-linked to
increase data integrity on the disk, and a bad file can be
recovered from either its start or end.

XIV-3

FLP-80 DOS BLOCK DIAGRAM
FLP80DOS
MONITOR

+

t

J

;

DEBUGGER
(DDT)

TEXT
EDITOR
(EDIT)

Z80
ASSEMBLER
(ASM)

t

t

t

- -- -- --

-- -- --

-.-

,.

1

RELOCATING
LINKAGE
LOADER
(RLL)

~

PERIPHERAL
INTERCHANGE
PROGRAM
(PIP)

~

1

LINKER
(LINK)

OEM
APPLICATION

1
1
J
1
-- - -- -- -- -- -- -- --

-

1/0 CONTROL
SYSTEM
(lOCS)

f

1

+

CONSOLE
DEVICE
HANDLER

LINE
PRINTER
HANDLER

:

~

J

HARDWARE
UART

HARDWARE
PIO

DISK
CONTROLLER
FIRMWARE

t

t

FLOPPY DISK
HANDLER
(FDH)

~INE
PRINTER

CONSOLE

DD

-

1

OTHER
DEVICE
HANDLERS

(FLOPPY DISK UNITS)
AND
FLP-80 BOARD

ORDERING INFORMATION

DESIGNATOR

DESCRIPTION

PART NO.

FLP-8000S

SDE based development system software (SO PROMs)

MK78142

FLP-80DOS

MD based development system software (MO PROMs)

MK77962

FLP-80DOS Operations Manual Only

MK78557

XIV-4

-

MOSIEI(.
SOFTWARE DISK BASED

MITE-80/BIOS
MK77972
FEATURES

the routines and drivers provided are designed for real-time
multiple asynchronous applications. The MITE-SO/BIOS
package is provided on diskette and includes:

o

Multi-tasking executive

o

Debugger which recognizes task data structures

o

Macro files to facilitate building tasks

o

Memory-pool manager

o

Timer handler which simulates any number of timers
using one hardware timer

o

I/O drivers for line printer, terminal, and floppy disk

o Basic I/O service subroutines to facilitate building new
I/O drivers

o Error-handler task which provides standard system error
recovery

MITE-SO/BIOS Terminal Driver
MITE-SO/BIOS Printer Driver
MITE-SO/BIOS Floppy-Disk Driver
MITE-SO/BIOS Basic I/O Servuce Routines
MITE-SO/BIOS MACRO Files
MITE-SO/BIOS Equate Files
MITE-SO/BIOS Error-HandlerTask
MITE-SO
MITE-SO provides a user with centralized control of the ZSO
CPU's resources. In managing this control. MITE-SO uses two
data structures, a Task Control Block (TCB). and a Message
Block (MB). as well as several system services that are
callable from user programs.
TASK CONTROL BLOCK (TCB)

INTRODUCTION
The Mostek MITE-SO software package is designed for
applications requiring asynchronous event handling of
multiple tasks. MITE-SO provides the basic services for
managing the CPU's resources in a real-time, multi-task
environment.MITE-SO is a software package provided on
diskette and includes:
MITE-SO
MITE-SO Debug
MITE-SO MACROS
MITE-SO System Linkages
MITE-SO Timer Handler
MITE-SO Memory-Pool Manager

A TCB uniquely identifies a task within the system. Each TCB
isa minimum 10bytes in length and contains the task status,
task priority, system link, message pointer, stack pointer, and
task name. Each task is also required to provide a minimum of
16 bytes of stack area for MITE-SO usage. The number of
tasks that MITE-SO can accommodate is limited only by the
amount of user-aliocatedTCB memory. The determination of
which task executes, and when, is accomplished by a status
byte and a priority level. A task can be assigned anyone of
127 priority levels and any number of tasks can share the
same priority level.
MESSAGE BLOCK (MB)

These programs provide the capability for controlling realtime, multiple-task applications as well as providing a way of
developing and debugging real-time programs. The programs
can be developed using a Mostek FLP-SODOS software
package that includes a MACRO-SO Assembler.
MITE-SO/BIOS is the Mostek Basic Input/Output Services
software package. It provides a common set of routines to
facilitate the design of I/O drivers and includes the I/O
drivers for terminal, printer, and floppy disk. All of the MITESO/BIOS modules are designed to operate under MITE-SO.
The MITE-SO/BIOS package supplements MITE-SO in that

An MB is used to transfer information between tasks. Each
MB is a minimum eight bytes in length and contains status,
message priority, system link, receiver pointer, and sender
pointer. An optional data field can follow the MB; its contents
and length are defined by user application. MBs can be sent
with a queuing option of FIFO or LIFO and with the option of
either specified priority or task priority. The order in which a
task processes MBs is determined by the MB's priority level.
Anyone of 127 priority levels can be selected.
SERVICES
The MITE-SO services provided allow for the handling of

XIV-5

messages between tasks and for task creation and cancelling.
Additional services allow for the control of interrupt events
and CPU interruptS.
The Services provided are:
Send a message to a task
MBSN MBSNW - Send a message to a task and wait for a
message to be available.
MBRSN Resend a message to a task.
MBRSNW - Resend a message to a task and wait for a
meSsage to be available.
MBRCV Receive a message if one is available.
MBRCVW - Receive a message, otherwise wait until one
is available.
MBFWD - Forward a message to a task.
MBFWDW - Forward a message to a task and wait fora
message to be available.
MBRET Return a message to the sending task.
MBRETW - Return a message to the sending task and
wait until a message is available.
MBCAN - Cancel a meSSage sent to a task.
MBFIND - Find the TCB address of a specified task
name.
MBWINT - Wait for an interrupt event to be posted.
MBPINT Post an interru()t event which is completed.
MITE-SO DEBUG
The MITE-SO DEBUG program provides a facility for interactively debugging relative and absolute ZSO programs
executing under MITE-BO. The various commands allow
displaying and modifying memory and CPU registers, setting
breakpoints, and executing programs. Additional commands
allow for breakpoints on tasks and serviCes, for .service
history, and for displaying Task Control Block and Message
Block contents. Mnemonics are used to represent ZSO
registers and MITE-BOservices, thus simplifying the
command language.
' .
The commands provided are:
B - Insert a breakpoint in the user's program.
C - Copy the contents of a block of memory to another
location in memory.
D - Display the past history of Tasks executed along·'
with the MITE-80 services used.
E - Execute program.
F - Fill memory limits with an B-bit data pattern.
H - Perform 16-bit hexadecimal addition andlor
subtraction.
J - Snap-shot a Task Control Block and its queued
Message Blocks.
K - Breakpoint on aTask calling MITE-80.
L - Locate all occurrences of an B-or 16-bit data
pattern. '
M - Display, update, or tabulate the contents of memory.
Set the offset constant.
P - Display or update the contents of an 110 port.
0- Ouit MITE-80 DEBUG.
R - Display the contents of the user registers.
V - Verify that two blocks of memory are equal.
, W - Software single step.
X - Duplicate console output to printer device.

MITE-SO SYSTEM LINKAGES
A system linkage file is provided which contains linkage
addresses for the system routines. The user can. link unique
application programs to the MITE-80 services with this file.
This file will minimize any impact on user programs
whenever MITE-BO is enhanced.
MITE-SO TIMER HANDLER
A Timer Handler is provided for control over an MK3BB2
Counter Timer Circuit (CTC) chip. The timer can be used for
applications requiring event time delays or for event
watchdog alerts. The timer executes as a MITE-BO task. A
maximum time duration of approximately 14 minutes in
increments of 12.B milliseconds is provided.
MITE-SO MEMORY-POOL MANAGER
A Memory-Pool Manager provides the user with a way of
allocating and deallocating memory blocks. The user can
configure an area of memory in up to 253 memory pools, with
each pool consisting of a unique memory-block size. A macro
is provided in the MITE-SO MACRO FILE to aid the user in
configuring the poo,ls.
MITE-SO MACROS
A macro file is provided to aid the user in defining and
developing MITE~BO TCBs. The macros will construct and
integrity-check a'TCB from user-specified parameters. The
macros will also generate code which will install the TCB into
the MITE-BO system.
MITE-SOl BIOS TERMINAL DRIVER
The Terminal Driver provides asynchronous input and output
interface between user tasks operating under MITE-80 and
an operator's terminal interfaced to an MDX-EPROM/UART
Card. The Driver operates as a task under MITE-SO !:Ind can
accommodate mUltiple terminal devices. Various plirameters
are user-configurable to allow the specifying :of unique
characteristics for each terminal.
MITE-SOl BIOS PRINTER DRIVER
The Printer Driver provides output control between user tasks
operating under MITE-BO and a printer interfaced to a Mostek
MDX-PIO Card. The Driver operates as a task under MITE-BO
and can accommodate mUltiple printer devices. Various
Driver parameters are user-configurable to allow the
specifying of unique characteristics for each printer.

o-

MITE-SOl BIOS FLOPPY-DISK DRIVER
The Floppy-Disk Driver provides input and output control
between user tasks'operating under MITE-BO and a floppydisk drive interfaced to an MDX-FLP Card. The Driver
operates as a task under MITE~BO and can accommodate
multiple disk drives; The Driver can handle the standard

XIV-6

eight-inch and the mini 5.25-inch disk drives. Various Driver
parameters are user-configurableto allow the specifying of unique
characteristics for each disk drive.
MITE-BO/BIOS BASIC I/O SERVICE ROUTINES
The basic I/O routines provide a common set of I/O services
which can be used to facilitate the design of user-developed
drivers. The routines provide functions that all drivers need,
such as user-buffer-pointer maintenance, hardware
initialization and character interpretation. All of the routines
are re-entrant and can be used by as many Driver tasks as
required by the application. The routines work with data
provided in the calling task's Task Control Block and the
Message Block currently being serviced by the Driver task.

MITE-BO/BIOS MACRO FilES
A pair of I/O macro files is provided to assist in constructing
the Driver's Task Control Block a long with their unique device
characteristics. A general-purpose I/O task macro is also
included for constructing the mandatory TCB parameters on
user-developed Drivers.
MITE-BO/BIOS EQUATE FilES
Two equate files are provided to support MITE-80/BIOS. The
file 10TASK.EQU provides default definitions for various
MITE-80/BIOS macros. The file BIOS.EQU provides
definitions for the MITE-80/BIOS extensions to the MITE-80
task control block (TCB) and message block (MB).

The Mostek-supplied drivers for Terminal, Printer, and Floppy
Disk all use the basic I/O routines. Memory savings can be
realized by using the basic I/O routines since common
functions such as buffer-pointer maintenance and specialcharacter interpretation (carriage return, line feed, tab)
required by many I/O drivers are centralized in the basic I/O
service routines.
MITE-80/BIOS provides seven callable routines for accessing
the common services:
CAll
NAME

SERVICES

100WHY
100GNC
100PNC
100ISR
1000PN
100EOS
100Ill

- Common decode of request and initialization
- Get next character from buffer, for output
- Put next character into buffer, for input
- Interrupt service handling
- Open device
- End-of-Block Routine
- Illegal operation processor

MITE-SO/BIOS ERROR-HANDLER TASK
The Error-Handler task provides a common facility for I/O
error recovery for all MITE-80/BIOS driver tasks.
CONFIGURATION
The various modules of MITE-80/BIOS are designed to work
with specific Mostek hardware:
Terminal Driver:
MDX-EPROM/UART Card and one CTC Channel (MK3883
available on MDX-CPU Card), interfaced to a Hazeltine or
equivalent terminal.
Printer Driver:
MDX-PIO Card interfaced to a Centronics type printer or
equivalent.
Floppy-Disk Driver:
MDX-FlP Card interfaced to a Shugart type disk drive or
equivalent.

XIV-7

ORDERING INFORMATION

DESIGNATOR

DESCRIPTION

PART NO.

MITE-SO/BIOS

MITE-SO/BIOS Software Package. The software is supplied
on Mostek diskette as relocatable object. The software includes MITE-SO, MITE-SO DEBUG, MACROS, EQUATES,
BIOS Timer Handler, Terminal Driver, Floppy-Disk Driver,
Printer Driver, Cjnd Memory-Pool Manager. MITE-SO/BIOS
Operation Manual is included. The attached
Standard Software License Agreement and Registration Form
must accompany the Purchase Order.

MK77972

MITE-SO Operation Manual. Detailed description of the
operation and use of the MITE-SO software package.

MK79726

BIOS Operation Manual. Detailed description of the operation
and use of the BIOS-SO software package.

MK797S4

. ...

XIV-8

MOSTEl{.
SOFTWARE DISK BASED

ANSI BASIC Software Interpreter
MK78157
FEATURES

o

Meets ANSI standard on BASIC (X3.60 - 1978)

o Occupies only 23K bytes, not including operating system

o

Direct access to CPU I/O Ports

o

Supports console and line printer I/O

o

Ability to read or write any memory location (PEEK,
POKE)

o

Allows console output to be redirected to the line printer

o

WHILE ... WEND structured construct

o

Arrays with up to 255 dimensions

o

o
Dynamic allocation and deallocation of arrays

Programs can be saved on disk in a protected format that
cannot be listed on console

o

IF ... THEN ... ELSE and IF ... GO TO (both if's may be
nested)

o

Direct (immediate) execution of statements

o

Error trapping, with error messages in English

o

Four variable types: Integer, string, real and doubleprecision real

o

Long variable names significant up to 40 characters

o

Full PRINT USING capabilities for formatted output

o

Extensive program editing facilities

o

Trace facililties

o

Can call any number of assembly-language subroutines

o

Boolean (logical) operations

o

Supports upto six sequential and random access files on
floppy disk

o

Variable record length in random access files from one to
128 bytes/ record

o

Complete set of file manipulation statements

DESCRIPTION
Mostek ANSI BASIC is an extensive implementation of
Microsoft BASIC for the Z80 microprocessor. Its features
are comparable to the BASICs found on minicomputers and
large mainframes. Mostek ANSI BASIC is among the fastest
microprocessor BASICs available. Designed to operate on
Mostek Systems with FLP-80DOS V2.1 and with 48K bytes
or more memory, Mostek BASIC provides a sophisticated
software development tool.
Mostek ANSI BASIC is implemented as an interpreter and is
highly suitable for user-interactive processing. Programs
and data are stored in a compressed internal format to
maximize memory utilization. In a 64K system, 28K of
user's program and data storage area are available.
Unique features include long variable names, substring
assignments and hexadecimal and octal constants. Many
other features ease the task of programming complex
functions. The Programmer is seldom limited by array size
(up to 255 dimensions, with run-time allocation and
deallocation) or I/O restrictions. Full PRINT USING
capabilities allow formatted output, while both input and
output may be performed with multiple sequential and
random files on floppy disk as well as with the CPU I/O
ports. Editing, error trapping, and trace facilities greatly
simplify program debugging.

XIV-9

Commands:
EDIT
MERGE
RUN
WIDTH

CLEAR
LIST
NULL
SYSTEM

CONT
LLiST
RENUM
TRON

DELETE
LOAD
RESET
TROFF

CHAIN
DEFSNG
ERASE
IF ... THEN(ELSE)
ON ... GOTO
RESUME

COMMON
DEFSTR
ERROR
IF. . GOTO
OPTION BASE
STOP

DEF DBL
DEFUSR
FOR .. NEXT
LET
RANDOMIZE
SWAP

DEF FN
DIM
GOSUB ... RETURN
ON ERROR GOTO

DATA
KILL
LSET
PRINT USING
RESTORE

FIELD
LINE INPUT
NAME
PRINT#
RESET

GET
LINE INPUT#
OPEN
PRINT# USING WRITE
RSET

INPUT
LPRINT
OUT
PUT
WRITE#

>=

"
<>

>

<

<=

XOR

MOD
IMP

NOT
EOU

AND

OR

AUTO
FILES
NEW
SAVE
Program Statements:
CALL
DEFINT
END
GOTO
ON ... GOSUB
REM
WHILE ... WEND

Input/Output Statements:
CLOSE
INPUT#
LPRINT USING
PRINT
READ
Operators:

+
1\

/

Arithmetic Functions:
ABS
EXP
LOG
USR

ATN
ERR
RND
VARPTR

CDBL
ERL
SGN

CINT
FIX
SIN

COS
FRE
SOR

CSNG
INT
TAN

CHRS
OCT
VAL

HEXS
RIGHTS

INSTR
SPACES

LEFT
SPCS

LEN
STRS

CVD
LOF
PEEK

DSKF
LOG
POKE

EOF
LPOS
POS

INP
MKDS
TAB

String Functions:
ASC
MIDS
STRINGS

Input/Output Functions:
CVI
INPUTS
MKIS
WAr.

CVS
LOC
MKSS

XIV-10

ORDERING INFORMATION
DESIGNATOR

DESCRIPTION

PART NO.

Mostek ANSI
BASIC

BASIC INTERPRETER high-level language to run
on FLP-80DOS. Requires 48K or more bytes of memory.

MK78157

BASIC Operation Manual Only

MK79708

In order to receive Mostek ANSI BASIC. the Mostek BASIC
non-disclosure agreement must be signed and returned
with each purchase order.

XIV-11

XIV-12

MOSIEI{.
SOFTWARE DISK BASED

FORTRAN IV Compiler
MK78158
FORTRAN IV COMPILER PHOTO

FEATURES

o

All of ANSI standard FORTRAN IV (X3.9-1966) except
complex data type

o

Generates relocatable linkable object code

o

Subroutines may be compiled separately and stored in a
system library

o

Compiles several hundred statements per minute in a
single pass

o

Enhancements include
1.
2.
3.
4.

5.
6.

7.

S.

LOGICAL variables which can be used as integer
quantities
LOGICAL DO loops for tighter, faster execution of
small-valued integer loops
Mixed-mode arithmetic
Hexadecimal constants
Literals and Hollerithsallowed in expressions
Logical operations on integer data .. AND., .OR., .NOT.
and XOR. can be used for 16-bit or S-bit Boolean
operations
READ/WRITE End-of-File or Error Condition transfer.
END=n and ERR=n (where n is the statement
number) can be included in READ or WRITE
statements to transfer control to the specified
statement on detection of an error or end-of-file
condition
ENCODE/DECODE for FORMAT operations to
memory

o

Long descriptive error messages

o

Extended optimizations

o

ZSO-assembly-Ianguage subprograms maybe called from
FORTRAN programs

DESCRIPTION
Mostek's FORTRAN IV Compiler package provides new
capabilities for users of ZSO-based microcomputer systems.
Mostek FORTRAN is comparable to FORTRAN compilers on
large mainframes and minicomputers. All of ANSI Standard
FORTRAN X3.9-1966 is included except the COMPLEX data
type. Therefore, users may take advantage of the many
applications programs already written in FORTRAN.

Mostek FORTRAN IV is unique in that it provides a
microprocessor FORTRAN development package that
generates relocatable object modules. This means that only
the subroutines and system routines required to run
FORTRAN programs are loaded before execution.
Subroutines can be placed in a system library so that users
can develop a common set of subroutines that are used in
their programs. Also, if only one module of a program is
changed, it is necessary to re-compile only that module.
The standard library of subroutines supplied with FORTRAN
includes:
ASS
lABS
AINT
DABS
INT
IDINT
AMOD
MOD
AMAXO
AMAX1
MAXO
MAX1
DMAX1
AMIN1
AMINO
MINO
MIN1
DMIN1
FLOAT
IFIX
DSIGN
SIGN
DIM
ISIGN
101M
DBLE
EXP
SNGL
DEXP
DLOG
ALOG10
ALOG
DLOG10
SIN
DSIN
COS
DCOS
TANH
SORT
DSORT
DATAN
ATAN
ATAN2
DATAN2
DMOD
PEEK
POKE
INP
OUT

XIV-13

The library also contains routines for 32-bitand 64-bitfloating
point addition, subtraction, multiplication, division, etc. These
routines are among the fastest available for performing these
·functions on the Z80.
A minimum system size of 4SK bytes (including FLP-SODOS)
is required to provide efficient optimization. The Mostek
FORTRAN compiler optimizes the generated object code in
several ways:
1.

Common subexpression elimination. Common subexpressions are evaluated once, and the value is
substituted in later occurrehces of the subexpression.

2.

Peephole Optimization. Small sections of code are
replaced by more-compact, faster code in special cases.

showing the addresses assigned to labels, variables and
constants.
LINKER
A relocating linking loader (LINK-SO) and a library manager
(LlB-80) are included in the Mostek FORTRAN package.
LINK-SO resolves internal and external references between
the object modules loaded and also performs library searches
for system subroutines and generates a load map of memory
showing the locations of the main program, subroutines and
common areas.

LIBRARY MANAGER

3.

Constant folding. Integer constant expressions are
evaluated at compile time.

4.

Branch Optimizations. The number of conditional
jumps in arithmetic and 10gicailFs is minimized.

LIB-SO allows users to customize libraries of object modules.
LlB-80 can be used to insert, replace or delete objectmodules
within a library, or create a new library from scratch. Library
modules ancithe symbol definitions they contain may also be
listed.

XCPM UTILITY

Long descriptive error messages are another feature of the
compiler. For instance:
?Statement unrecognizable
is printed if the compiler scans a statement that is not an
assignment or other FORTRAN statement. The last twenty
characters scanned before the detected error are also printed.

A utility program (XCPM) is incl uded which allows the user to
copy FORTRAN source programs from CP/M diskettes to
FLP-80DOS diskettes. At this point the programs can be
compiled using the Mostek FORTRAN compiler.

As an option, the compiler generates a fully symbolic listing of
the machine language to be generated. At the end of the
listing, the compiler produces an error summary and tables

FTRANS allows the userto convert object programs produced
by the Mostek Z80assembler toa form that is linkable to
FORTRAN programs.

FTRANS UTILITY

DESIGNATOR

DESCRIPTION·

PART.NO.

Mostek FORTRAN IV

FORTRAN IV high-level compiler to run on FLP-SODOS.
Requires 4SK bytes of RAM. Includes Operations Manual.

MK7S15S

Mostek FORTRAN IV Operations Manual only

MK79643

XIV-14

SOFlWARE DISK BASED

MACRO-70
MK79085
FEATURES

o

Assembles standard 3870/F8 instruction set to produce
relocatable, linkable object modules.

o

Provides nested conditional assembly, an extensive
expression evaluation capability, and an extended set of
assembler pseudo-ops:
- origin
- equate
- define constant
DC
- set/define macro label
DEFL
DEFM
- define message
- define byte
DEFB
- define word
DEFW
- define storage
DEFS
- end of program
END
- global symbol definition
GLOBAL
- module name definition
NAME
PSECT
- program section definition
- conditional assembly
IF/ENDIF
- include another file in source module
INCLUDE
LlST/NLIST - list on/off
- code listing only of macro expansions
CLiST
- list/no list of macro expansions
ELiST
- eject a page of listing
EJECT
TITLE
- place title on listing

o An extended instruction set for the MK3870 is defined
via a macro definition file and is shipped with the
MACRO-70 diskette.

o

Listing and object modules can be output on disk files or
any device.

o

Compatible with other Mostek 3870/F8 assemblers and
FLP-80DOS Version 2.0 or higher. Requires 32Kor more
of system RAM.

ORG
EQU

o

DESCRIPTION
MACRO-70 is an advanced upgrade from the 3870/F8
Cross Assembler (FZCASM). In addition to its macro
capabilities, it provides for nested conditional assembly il nd
allows symbol lengths of any number of characters. It
supports global symbols, relocatable programs, a symbol
cross-reference listing, and an unused-symbol reference
table. MACRO-70 is upward compatible with all other
Mostek 3870/F8 Assemblers.
The Mostek
designed to
System with
Version 2.0
following:

Provides options for obtaining a printed cross-reference
listing, terminating after pass one if errors are
encountered, redefining standard MK3870 opcodes via
macros, and obtaining an unused-symbol reference
table.

o Provides the most advanced macro handling capability
on the microcomputer market which includes:
- optional arguments
- defualt arguments
- looping capability
- global/local macro labels
- nested/recursive expansions
- integer/boolean variables
- string manipulation
- conditional expansion based on symbol definition
- call-by-value facility
- expansion of code-producing statements only
- expansion of macro-call statements only

3870/F8 Macro Assembler (MACRO-70) is
run on the Mostek Dual-Disk Development
32K or more of RAM. It requires FLP-80DOS,
or higher. Macro pseudo-ops include the

MACRO/MEND
MNEXT
MIF
MGOTO
MEXIT
MERROR
MLOCAL

- define a macro
- step to next argument
- evaluate expression and branch to
local macro label if true
- branch to local macro label
- terminate macro expansion
- print error message in listing
- define local macro label

Predefined macro-related parameters include the following:
%NEXP
%NARC
#PRM
%NPRM
%NCHAR

- current number of this expansion
- number of arguments passed to
expansion
- expand last-used argument
- number of last-used argument
- number of characters in
argument

The operations manual describes in detail all facilities
available in MACRO-70 and provides a host of examples
XIV-15

and sample print-outs. An extended instruction set which is
designed to ease programming for the MK3870 is defined
in the manual. The new instructions are provided on the
MACRO-70 diskette in the form of a macro definition file

which can be included in a source program.
Downloading to other Mostek systems is facilitated by a
utility program called F8DUMP, which is supplied on the
MACRO-70 diskette.

ORDERING INFORMATION
DESGINATOR

DESCRIPTION

PARTNO.

MACRO-70

3870/F8 Macro Cross Assembler, binary program supplied
on a standard FLP-80DOS diskette. Includes F8DUMP utility,
an extended instruction set, macro definition file, and the
Operations Manual.

MK79085

MACRO-70 Operations Manual

MK79635

XIV-16

MOSTEI{.
SOFTWARE DISK BASED

MACRO-80
MK78165
FEATURES

D Listing and object modules can be output on disk files or
any device.

D Assembles standard Z80 instruction set to produce

relocatable, linkable, object modules

D Compatible with other Mostek Z80 assemblers and FLP-

80DOS Version 2.0 or higher. Requires 32K or more of
system RAM.

D Provides nested conditional assembly, an extensive

expression evaluation capability, and an extended set of
assembler pseudo-ops:
ORG
- origin
- equate
EQU
- set/define macro label
DEFL
- define message
DEFM
- defi ne byte
DEFB
DEFW
- define word
- defi ne storage
DEFS
END
- end of program
- global symbol definition
GLOBAL
NAME
- module name definition
- program section definition
PSECT
- conditional assembly
IF/ENDIF
INCLUDE
- include another file in source module
LlST/NLIST - list on/off
CLlST
- code listing only of macro expansions
ELiST
- list/no list of macro expansions
EJECT
- eject a page of listing
TITLE
- place title on listing

DESCRIPTION
MACRO-80 is an advanced upgrade from the FLP-80DOS
Assembler (ASM). In addition to its macro capabilities, it
provides for nested conditional assembly and allows symbol
lengths of any number of characters. It supports global
symbols, relocatable programs, a symbol cross-reference
listing, and an unused-symbol reference table. MACRO-80
is upward compatible with all other Mostek Z80
assemblers.
The Mostek Z80 Macro Assembler (MACRO-80) is
designed to run on the Mostek Dual-Disk Development
System with 32K or more of RAM. It requires FLP-80DOS,
Version 2.0 or higher. Macro pseudo-ops include the
following:
MACRO/MEND
MNEXT
MIF

D Provides options for obtaining a printed cross-reference

listing, terminating after pass one if errors are
encountered, redefining standard Z80 opcodes via
macros, and obtaining an unused-symbol reference
table.
D Provides the most advanced macro handling capability in

the microcomputer market which includes:
- optional arguments
- default arguments
- looping capability
- global/local macro labels
- nested/recursive expansions
- integer/boolean variables
- string manipulation
- conditional expansion based on symbol definition
- call-by-value facility
- expansion of code-producing statements only
- expansion of macro-call statement only

MGOTO
MEXIT
MERROR
MLOCAL

- defi ne a macro
- step to next argument
- evaluate expression and branch to
local macro label if true
- branch to local macro label
- terminate macro expansion
- print error message in listing
- define local macro label

Predefined macro-related parameters include the following:
O/ONEXP
O/ONARC
#PRM
O/ONPRM
O/ONCHAR

- current number of this expansion
- number of arguments passed to
expansion
- expand last-used argument
- number of last-used argument
- number of characters in
argument

The operations manual describes in detail all facilites
available in MACRO-80 and provides a host of examples
and sample print-outs.
XIV-17

ORDERING INFORMATION
DESIGNATOR

DESCRIPTION

PART NO.

MACRO-80

Z80 Macro Assembler, binary program supplied on a standard

MK78165

FLP-80DOS diskette, with Operations Manual.
MACRO-80 Operations Manual

XIV-18

MK79635

MOSTEI(.
SOFTWARE DISK BASED

MEDEX-80
MK77968
ability, the diagnostic programs can be supplied by the user.
The expandable structure of MEDEX-80 permits the
inclusion of user-developed diagnostic programs within its
structure. The diagnostic software modules that are
supplied in MEDEX-80, version 2.0 are as follows:

FEATURES

o

Modular MDX board-level software

o User-expandable diagnostic software

o

Stand-alone or integrated diagnostic package execution

o

Interrupt-or non-interrupt-driven diagnostics

o

Board-level diagnostics for:
CPU
RAM
ROM

SC/D
FLP
MATH

1. MDINI - Initialization which provides the set-up
requirements of other MEDEX-80 modules.
2. MDMON - Monitor which provides control supervision
and interface to rest of diagnostic modules.

3. MDSCH - MDX-SC/D card handler which provides
user interface to the card's 1/0 devices.

AID 8

4. MDRAM - Diagnostic RAM test which provides
confidence test of RAM areas by means of pattern tests.

DESCRIPTION
MEDEX-80 is a diagnostic software package for the MDX
series of cards. MEDEX-80 is an acronym for MDX
Expandable Diagnostic Exercise software for the Z80. It is a
modular software package designed to diagnose faulty
MDX card(s) within a system configuration. MEDEX-80 can
function as a stand-alone package or it can be integrated
into a user's software package. Only those modules
applicable to a user's requirements need be used.
MEDEX-80 can reside in either RAM or EPROM, and the
amount of memory required is dependent on the standard
modules selected and the uniqueuser modules included in
the package. This diagnostic software package is designed
to operate with the following minimum hardware
configuration:
• Mostek MDX-CPU card (MDX-CPU1 or CPU2)
• Mostek MDX-SC/D card

5. MDROM - Diagnostic ROM test which provides
confidence test of ROM areas by means of checksums.

6. MDCTC - Diagnostic CTC test which provides
confidence test of MDX-CPU card's CTC by means of
functional exercising.

7. MDSCD - SC/D card test which provides confidence
test of MDX-SCD card by means of functional
exercising.
8. MDFLP - Diagnostic Floppy Disk card test which
provides confidence test of MDX-FLP card by means of
functional exercising.
9. MDMTH - Diagnostic Math Card test which provides
confidence test of AM 9511 Math Chip and MDXMATH card by means of functional testing.

SOFlWARE DESCRIPTION
MEDEX-80 is comprised of system software and diagnostic
software. The system software consists of initialization,
monitor, and MDX-SC/D card handler. The diagnostics
software consists of test programs for only those MDX
cards having little or no on-card user configurability. For
those MDX cards having extensive on-card user configur-

10. MDAD8 - Diagnostic AID 8 card test which provides
confidence test which provides confidence test of
MDX-AiD 8 card by means of functional exercising.
A software users manual for each diagnostic module is
provided on the MEDEX-80 diskette and provides indepth
description of each module.

XIV-19

THEORY OF OPERATION
The basic theory of operation of both MEDEX-80 and the
MDX-SC/D Card is as follows. The user provides a CPU
control transfer to the MEDEX-80 initialization module
through a jump instruction or a depressed switch action.
This initialization module sets up the MEDEX-80 monitor,
other MDX cards that need initialization, and the MDXSC/D card. Once initialization is complete, the monitor
takes control ofthe diagnostic system. To perform a test, the
operator selects the desired diagnostic test number via the
thumbwheels on the SC/D card. The RESET/START
switch is then momentarily depressed to the Start position
to activate the !ipecified test number. The monitor validates
the test number and transfers CPU control to the proper
diagnostic test program. The display will indicate a "test in
progress" readout. If the test is permitted to execute until
completion of the selected diagnostic test, then; upon
completion, the test results will be indicated in the display.
The display indication of pass or fail, and type of fail, is
dependent on the diagnostic test program. A different or
same diagnostic test can now be executed following the
cycle as just described. Ifthe operator desires to terminate a
diagnostic test in progress, or to reinitialize the diagnostic
system, the RESET/START switch is momentarily
depressed to the RESET position. The depression to the
RESET position will cause the MEDEX-80 initialization
module to again. be executed, or cause execution of the
users initialization (OOOOH) routine if the Reset Switch is
' "
strapped to PBRESET.

interrupt control word to disable interrupts. During the
MEDEX-80 initialization phase, the Z80 system-wide
interrupt capability is disabled. MEDEX-80 will enable
system-wIde interrupt capability after all diagnostic
modules have completed their unique initiaiization. During
each diagnostic module's initialization, the user should
disable the unique MDX card's in·ter'rupt. When the
diagnostic module is selected to execute, the first operation
should be to enable its respective MDX card's interrupt
capability, and upon completion of the test, the card's
interrupt capability should be disabled.
CONCEPT OF DIAGNOSTIC MODULE
The diagnostic module is a program which executes a
specific test or tests, and, upon completion, outputs the test
results to the operator display in the form of a coded
number.
Each diagnostic module is composed of the following
programs, or submodules:
1.

Initialization - Provides the unique initialization
requirements.

2.

Test - Provides the unique test(s) to exercise and
determine specific faults, determines the pass/fail
decision on the performed test, and provides coded
operator display.

3.

ISR - Provides the unique interrupt service routine
, handling if applicable to this diag~ostic module.

INTERRUPTS
MEDEX-80 utilizes the mode 2 interrupts of the Z80. Each
diagnostic module's initialization' process will load its
respective interrupt vector(s) on 'its respective MDX card.
MEDEX-80 will initialize the CPU's I register during its
initialization. Whenever an interrupt occurs, the MDX
Card's interrupt vector is linked with the I register, forming
an address which points to the respective entry address of
the Diagnostic Interrupt Vector Table. An indirect branch to
the address within this entry is then performed by the CPU
and process control is transferred to the specified interrupt
service routine.

MEDEX-80 DISKETTE
A floppy diskette formattF:d in the IBM 3740 soft-sectored
single-density fashion is provided with the SC/D Card. The
diskette is readable on a FLP-80DOS-based MDX or
MATRIX system. The diskette includes the following:
1. " Modules - An assembly source-code file of each of the
MEDEX-80 modules.

2.
The handling of an interrupt from an MDX card is the
responsibility of the respective card's diagnostic module. If a
user elects not to involve interrupts within the diagnostic
module test, then, during the diagnostic module's
initialization, the user should configure the MDX card's

User Manuals -Asoftware user manual for each ofthe
above source modules. The user manual files are in
ASCII text format for output to a printer. Each user
manual has a unique section number which permits,
once all sections are printed, the assembling into one
MEDEX-80 User Manual.

ORDERING INFORMATION
DESIGNATOR

DESCRIPTION

PART NUMBER

MEDEX-80

MEDEX-80 diskette with 10 diagnostic software modules and
a user manual (in ASCII test format) for each of the modules.

MK77968

MEDEX-80 Users Manual Only

MK79873

XIV-20

Standard License, Agreemerit and Registration Form
All Mostek Corporation software products are sold
on condition that the purchaser agrees to
the following terms:
1. The Purchaser agrees not to sell, provide, give away, or otherwise make available to any unauthorized persons, all or any part of, the
Mostek software products listed below, including, but not restricted to: object code, source code, and program listings. This license allows
the purchaser to operate the software product only on the system referenced by serial number below. Mostek retains title to all Mostek
software products including diskettes and tapes.
.
2. The Purchaser may at any time demonstrate the normal operation of the Mostek software product to any person.
3. Purchaser may not copy materials furnished with Mostek software products but copies may be obtained from Mostek. No part of the
Mostek software products maybe copied by Purchaser in printed or machine-readable form unless for the purpose of study, modification
or back-up. Purchaser will place Mostek's copyright notice on all copies and maintain records, available at Mostek's request, ofthe location
of the copies.
4. Mostek's sole obligation shall be to make available to Purchaser all published modifications or updates made by Mostek to licensed
software products which are published and made generally available within one (1) year from date of purchase, provided Purchaser has
complied with the Software License Agreement and Registration Form.
5.ln no event will Mostek be held liable for any loss, expense or damage, of any kind whatsoever, director indirect, including asa result of
Mostek's negligence. Mostek shall not be liable for any incidental damages, consequential damages and lost profits, arising out of or
connected in any manner with any of Mostek's software products described below.
6. MOSTEK MAKES NO WARRANTIES OF ANY KIND, WHETHER STATUTORY, WRITTEN, ORAL, EXPRESSED OR IMPLIED (INCLUDING
WARRANTIES OF FITNESS FOR A PARTICULAR PURPOSE AND MERCHANTABILITY AND WARRANTIES ARISING FROM COURSE OR
DEALING OR USAGE OF TRADE) WITH RESPECT TO THE SOFTWARE DESCRIBED BELOW.
7. Any license under this agreement maybe terminated for breach byone month's prior written notice and Purchaser will promptly return
all copies of any parts of Mostek Software products.
List the following Software Products subject to this agreement
Mostek Product
Number (MK#)

Product Name

Mostek Product
Number (MK#)

Product Name

AGREED TO:
PURCHASER

MOSTEK CORPORATION

Name (PRINT)

Name

Signature (PARTY)
Title

Date

Title

Date

PLEASE PRINT FOLLOWING INFORMATION:
Company Name ___________________________________ Date ___________________________________________
Address __________________________________________________________________________________________

City ___________________________ State _________________________ Zip Code _____________
Country _____________________________________ Telephone..!.(____"--_____________________________
Mostek Disk System Serial #

or Mostek Disk Controller Serial # _____________________

or 0 Non Mostek Hardware
DateofPurohase _________________________________________________________________
Place of Purchase _______________________________________________________________

XIV-21

If you are purchasing this product from a Distributor, print the Distributor's name below and return this form to the Distributor; The
distributor will provide a purchase order # and will then forward this form to the address below.
Distributor Name _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
If you are purchasing this product direct from Mostek, check the Customer PO # box, provide your purchase order #, and return this form
to the address below.
Purchase Order # to Mostek

o Customer PO #
or
o Distributor PO #

PO # _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

RETURN THIS FORM TO:
Software Librarian, MS #510
Micro System Department
Mostek Corporation
1215 W. Crosby Road
P.O. Box 169
Carrollton, Texas 75006
*NOTE: Mostek will not ship this software product to customer until this signed form is received by the Mostek software librarian.

XIV-22

MOSTEI{.
SOFTWARE DISK BASED

LIB-80-V1
MK78164
FEATURES
o Includes 23 useful subroutines and programs for the
Z80, including:
o Lawrence Livermore Lab's Basic
o Generalized sort program for up to eight fields per
record
o 8080 - Z80 source-code converter
o Fast disk-to-disk copy utility
o Hexadecimal Dump Utility to dump memory on files
o Assembly Language Formatter Utility to format Z80
source into columns
o Word Processor Program Version 2.0, used to format
documents
o Disk Recovery Utility used to recover bad disk files

o

All programs are supplied in source, object, and binary
format with complete documentation on a standard FLP80DOS diskette

o

Requires FLP-80DOS Version 2.0 or higher

DESCRIPTION
The Mostek FLP-80DOS Software Library is a collection of

programs of general utility that run under FLP-80DOS
Version 2.0 or higher. These programs are used quite
extensively at Mostek. They are being offered in source
format on diskette so that the user may not only use them as
supplied, but may use them as a base for individuallytailored software.
This software library differs from other libraries in that all
programs in the library have been developed or modified
in-house. All programs in the library are in use at Mostek
and all have some utility.
The FLP-80DOS Software Library Volume 1 consists of a
User's Guide and two diskettes containing the source and
binary (or object for subroutines) forms for each one of the
twenty-three included programs. In order to reduce the cost
of the library, printed source listing are not supplied. The
user can obtain a source listing easily by assembling the
required source program. A brief User's Guide is a part of
each program source.
The FLP-80DOS Software Library is a "Level 2" product.
"Level 2" software products are supplied by Mostek but are
not supported in the areas of technical assistance or
updates.

ORDERING INFORMATION
DESIGNATOR

DESCRIPTION

PART NO.

LlB-80 Volume 1

Software Library including source, object, and binary
formats on diskette, and a printed user's guide.

MK78164

Software Library Operation Manual Only

MK79621

XIV-23

MICRO SYSTEMS DATA BOOK

MOSIEl(.
DEVELOPMENT SYSTEMS

MATRIXTM-80/SDS
MK78188, MK78189
INTRODUCTION
The Mostek MATRI)(TM is a complete state-of -the-art, floppy
disk-based computer. Not only does it provide all the
necessary tools for software development, but it provides
complete hardware/software debug through Mostek's
AIMTM series of in-circuit emulation cards forthe Z80, 8086,
and 8088 as well as the 3870 family of single-chip
microcomputers. The MATRIX has at its heart the powerful
OEM-80E (Single Board Computer), the RAM-80BE (RAM
I/O add-on board), and the FLP-80E (floppy disk controller
board). Because these boards and software are available
separately to OEM users, the MATRIX serves as an
excellent test bed for developing systems applications.
The disk-based system eliminates the need for other mass
storage media and provides ease of interface to any
peripheral normally used with computers. The file-based
structure for storage and retrieval consolidates the data
base and provides a reliable portable media to speed and
facilitate software development.
The FLP-80DOS Disk Operating System is designed for
maximum flexibility both in use and expansion to meet a
multitude of end-user or OEM needs. FLP-80DOS is
compatible with Mostek's SD and MD Series of OEM
boards, allowing software designed on the MATRIX to be
directly used in OEM board applications.
Development System Features
The MATRIX is an excellent integration of both hardware
and software development tools for use throughout the
complete' system design and development phase. The
software development is begun by using the combination of
Mostek's Text Editor with "roll in-roll out" virtual memory
operation and the Mostek relocating assembler. Debug can
then proceed inside the MATRIX domain using its resources
as if they were in the final system. Using combinations of
the Monitor, Designer's Debugging Tool, execution time
breakpoints, and single step/ multistep operation along
with a formatted memory dump, provides control for
attacking those tough problems. The use of the Mostek
AIMTM options provides extended debug with versatile
hardware breakpoints on memory or port locations, a
buffered in-circuit emulation cable for extending the

XV-1

software debug into its own natural hardware environment,
and a history memory to capture bus transactions in real
time for later examination.
The relocatable and linking feature of the assembler
enables the use of contemporary modular design
techniques whereby major system alterations can be made
in small tractable modules. Using the Linker, the small
modules can be combined to form a run-time module
without major reassembly of the entire program.
Package System Features
From a system standpoint, the MATRIX has been designed
to be the basis of an end product such as' a small
business/industrial computer. The flexibility provided in the
FLP-80DOS operating system permits application programs
to be as diverse as a high-level language compiler or a
supervisory control system in the industrial environment.
Other hardware options are available, with even more to be
added. Expansion 'of the disk drive units to a total of four
single-sided or double-sided units provides up to two
megabytes of storage. This computer uses the thirdgeneration Z80 processor supported with the power of a

FLP-80DOS BLOCK DIAGRAM

OTHER
DEVICE
HANDLERS

FLOPPY
DISK
UNITS

complete family of peripheral chips. Through the use of its
15S instructions, including .16-bit arithmetic, bit
manipulation, advanced block moves and interrupt
handling, almost any application from communication
concentrators to general purpose accounting. systems is
made easy.
OEM Features

MATRIX SYSTEM SPECIFICATIONS

•
•
•
•

•

..

Device drivers for paper tape 'readers, punches,card
readers, line printers, Silent 700'5, Teletypes and CRT's
are included. Others can be added.
.
PROM programmer I/O port. Programmer. itself is
optional.
.
Bus compatible with Moste~, SPE series of OEIVi'b6c;J~ds

MATRIX RESIDENT SOFTWARE (FLP-80DOS)

The hardware and softWare basis for the MATRIX is also
available separately to the OEM purchaser. Through a
. software licensing agreement, all Mostek software can be
utilized on these OEM series of cards.

•
•
•
•
•

•

ZSOCPU
4K-byte PROM bootstrap and ZSO debugger
60K bytes user RAM (56K contiguous)
4K bytes PROM bootstrap
Eight .S-bit I/O ports using four PIOs with userdefinable drivers/receivers
Serial port: RS-232C and 20 rnA current loop
4 channel counter/timer (CTC)
Two single-density, single-sided disk drives; 250K
bytes per floppy disk·
Three positions for AIM modules, AID cards, Serial
Interface, etc.

A totally integrated package of residentsoftware is offered
in conjunction with the MATRIX consisting of:
Monitor
Text Editor
MACRO SO Assembler
Linker
DDT-SO with extended debug through AIMTM
modules
Peripheral Interchange Program
Floppy Disk Handler.
I/O Control System.
Device Driver Library
Batch Mode Operation
Monitor
The FLP-SODOS Monitor is th~ environment from which all
activity in the system initiates. From the Monitor,any
system routine such as PIP or a user-Ilenerated program is

XV-2

DEFS
END
GLOBAL
NAME
PSECT
IF/ENDIF
INCLUDE
LlST/NLIST
CLiST

begun by simply entering the program name. FLP-aODOS
I/O is done in terms of logical unit numbers, as is commonly
done in FORTRAN. A set of logical units is pre-assigned to
default. I/O drivers upon power up or reset. From the
console the user can reassign any logical unit to any new
I/O device and can also display logical unit assignments.
Executable file creation can be done by the Save command;
printable absolute object files can be produced using the
Dump command.

ELiST
EJECT
TITLE

Text Editor
The Text Editor permits editing/creating of any source file
independent of the language being written. The Editor is
both line and string oriented to give maximum utility ano
user flexibility. The Editor, through its virtual memory "roll
in-roll out" technique, can edit a file whose length is limited
only by maximum diskette storage. Included in the
repertoire of #15 commands are macro commands to save
time when encountering a redundant editing task. The
Editor is also capable of performing in one operation all the
commands which will fit into an aO-column command
buffer.
The video Editor displays the text to be edited directly on the
CRT screen as if it were a window into memory.
The window and cursor need only be positioned over the
character to be changed. Then the new text can be added or
the old deleted with the changed data displayed
immediately on the screen. The video Editor allows
programs (or any text) to be entered or corrected much more
quickly and easily than TTY-oriented Editors allow.

ZSO Macro Assembler (MACRO-SO)
The Mostek zao Macro Assembler (MACRO-aO) is the most
powerful macro assembler in the microcomputer market. In
addition to its macro capabilities, it provides for nested
conditional assembly and allows symbol lengths of any
number of characters. It supports global symbols and
relocatable programs. Features of MACRO-aO include the
following:
•

Assembles standard zao instruction set to produce
relocatable, linkable, object modules.

•

Provides nested conditional assembly, an extensive
expression evaluation capability, and an extended set of
assembler pseudo-ops:
ORG
EQU
DEFL
DEFM
DEFB
DEFW

- define storage
- end of program
- global symbol definition
- module name definition
- program section definition
- conditional assembly
- include another file in source module
- list on/off
- code listing only of macro expansions
- list/no list of macro expansions
- eject a page of listing
- place title on listing

Provides options for obtaining a printed cross-reference
listing, terminating after pass one if errors are encountered,
redefi n i ng sta nda rd zao opcodes via macros, and obta i n i ng
an unused symbol reference table.
•

Listing and object modules can be output on disk files or
any device.

•

Compatible with other Mostek zao assemblers and
FLP-aODOS Version 2.0 higher.

•

Provides the most advanced macro handling capability
in the microcomputer market which includes:
- optional arguments
- default arguments looping capability
- global/local macro labels
- nested/recursive expansions
- integer/boolean variables
- string manipulation
- conditional expansion based on symbol definition
- call by value facility
- expansion of code-producing statements only
- expansion of macro call statement only

Macro pseudo-ops include the following:
MACRO/
MEND
MNEXT
MIF
MGOTO
MEXIT
MERROR
MLOCAL
Predefined
following:

- orgin
- equate
- set/define macro label
- define message
- defi ne byte
- define word

%NEXP
%NARC
#PRM
%NPRM
%NCHAR

XV-3

- define a macro
- step to next argument
- evaluate expression and branch to
local macro label if true
- branch to local macro label
- terminate macro expansion
- print error message in listing
- define local macro label
macro-related

parameters

include

the

- current number of this expansion
- numberofargumentspassedtoexpansion
- expand last used argument
- number of last used argument
- number of characters in argument

Erase

The operations manual describes in detail all facilities
available in MACRO-80 and provides a host of examples
and sample print-outs.

Format

Unker
The Linker program provi~es the capability of. linking
assembler-generated, absolute or relocatable object
modules together to create a. binary or run-time file. This
process permits generation of programs which may require
the total memory resources of the system. The linking
process includes the library search option which, if elected,
will link in standard library object files (device drivers, math
pack functions)· from disk to resolve undefined global
symbols. Another option selects a complete global symbol
cross-reference lIsting.

Init

Rename

Status
Peripheral Interchange Program (PIP)
PIP provides complete file· maintenance activity for
operations such as copy file from disk to disk, disk to
peripheral. or any peripheral to any other peripheral
supporting both file-structured and character-oriented
devices. Key operations such as renaming, appending, and
erasing files also exist along with status commands for
diskette 10 and vital statistics. PIP can search the diskette
directories for any file or a file of a specific name, extension,
and user number. The PIP operations are:
Append
Copy

Date

Directory

- appends file 1 to file 2 without
changing file 1.
- copies input files or data from an input
device to an output file or device. The
Copy command can be used for a
variety of purposes such as listing
files, concatenating individual files, or
copying all the files on a single file
from one disk unit (e.g. DKO) to a
second disk unit (e.g. DK1)
- allows the specifying of the date in
day, month, and yearformat. The date
specified will be used to date tag any
file which is created or
edited.
- lists the directory of a specified disk
unit (DKO, DK1, etc.). The file name,
extension, user number and creation
or edited date are listed for each file in
the direc1:ory. The user can also request listing-only files of a specified
name, only files of a specified
extension, or only files of a specified
user number. The list device can be
any device supported by the system as
well as a file.

Quit -

- erases a single file or files from a
diskette in a specified disk unit. The
user has the option to erase all files,
only files of a specified file name, or
only files of a specified user number.
- takes completely-unformatted softsectored diskettes, formats to IBM
3740, and prepares to be a system
diskette. Operation is performed on
diskette unit 1 and a unique 11character name is assigned to that
diskette, if specified.
- initializes maps in the disk handler
when a new diskette has been
inserted while in the PIP environ
ment.
- renames a file, its extension, and user
number to a file of name X, extension
y, and user Z.
- lists all vital statistics of a disk unit to
any device. These include the number
of allocated records, the number of
used records, and the number of
bad records
returns to Monitor Environment.

DOS/Disk Handler

The heart of the FLP-BODOS software package is the Disk
Operating System. Capable of supporting up to four singledensity, single- or double-sided units, the system provides a
file-structure orientation timed and optimized for rapid
storage and retrieval. Program debug is enhanced by
complete error reporting supplied with the DOS.
Additionally, extensive error recovery and bad sector
allocation insure data and file integrity. The DOS not only
provides file reading and writing capability, but special
pointer manipulation, record deletions, record insertions,
skip records both forward and backward, as well as
directory manipulation such as file creation, renaming, and
erasure. The DOS is initiated by a calling vector which is a
subset of the I/O control system vector or through the
standard 10CS calling sequence to elect buffer allocation,
blocking, and deblocking of data to a user-selectable, logical
record type.
A unique dynamic allocation algorithm makes optimal use
of disk storage space. Run-time (Binary) files are given first
priority to large blocks offree space to eliminate overhead in
operating system and overlay programs. The algorithm
marks storage fragments as low priority and uses them only
when the diskette is nearing maximum capacity. The DOS
permits seven files to be opened for operations at anyone
time, thus permitting execution of complex application
programs.

XV-4

provide additional I/O expansion as system needs grow.
Standard system configuration is 4aK bytes for a system
total of 60K bytes user RAM (56K contiguous).

I/O Control System
The I/O Control System provides a central facility from
which all calls to I/O can be structured. This permits a
system applications program to dissolve any device
dependence by utilizing the logical unit approach of large,
main-frame computers. For example, a programmer may
want to structure the utility to use logical unit No.5 as the
list device which normally in the system defaults to the line
printer. He may, however, at run time, assign a different
device for logical unit No.5. The application program
remains unchanged.

FLP-SOE
Integral to the MATRIX system is the floppy controller. The
FLP-aOE is a complete IBM 3740 single-density/doublesided controller for up to four drives. The controller has 12a
bytes of FIFO buffer resulting in a completely interruptable
disk system.

Interface by a user tolOCS is done by entering a device
mnemonic in a table and observing the calling sequence
format. 10CS supplies a physical buffer of desired length,
handles buffer allocation, blocking, deblocking, and
provides a logical record structure as specified by the user.

OPTIONAL MODULES COMPATIBLE WITH MATRIX
AIM-SOE (2.5 MHz max. clock rate)

Batch-Mode Operation
In Batch-Mode Operation, a command file is built on disk or
assigned to a peripheral input device such as a card reader.
The console input normally taken from the keyboard is
taken from this batch device or batch file. While operating
under direction of a batch file, the console output prompts
the user as normal, or the prompting can be directed to any
other output device. The Batch operation is especially useful
for the execution of redundant procedures not requiring
constant attention of the operator.

HARDWARE DESCRIPTION
OEM-SOE
The OEM-aOE provides the essential CPU power of the
system. While using the zao as the central processing unit,
the OEM-aOE is provided with other zao family peripheral
chip support. Two zao PIO's gilie four completely
programmable a-bit parallel I/O ports with handshake from
which the standard system peripherals are interfaced. Also
on the card is the ZaO-CTC counter/timer circuit which has
three free flexible channels to perform critical counting and
timing functions. Along with 16K of RAM, the OEM-aOE
provides five ROM/PROM sockets which can be utilized for
10/20K of ROM or 5/1 OK PROM. Four sockets contain the
firmware portion of FLP-aODOS. The remaining socket can
be strapped for other ROM/PROM elements.

RAM-SOBE
The RAM-aOBE adds additional memory with Mostek's
MK4116 16K dynamic memory along with more I/O. These
two fully-programmable a-bit I/O ports with handshake

The AIM-aOE module provides extended debug for the
MATRIX. In zao development, real-time in-circuit
emulation permits debug ofthe hardware ar:ld the software
atthe most intimate level. Hardwaresingle-step/multi-step
with register trace, execution intercept on memory access,
port access, or externa I trigger provides absol ute control
over any system regardless of how complex it is. The
"pushbutton intercept" enables the programmerto perform
a controlled recovery for those extremely difficult-to-trace
processor-lock-out loops. With the memory clock selectable
history module, any past 256 events of data, address, or
control bus operation are captured in real time and may be
displayed.
The AIM-aOE includes aK bytes of ROM firmware
introducing unique software including a mnemonic
disassembler for inverse assembly of history module
contents of single-step/multi-step operations. "In-line"
code disassembled to language mnemonics provides
insight into execution resultsas if examining an assemblergenerated listing. Extra added capability is the ROMresident self-test of OEM-aOE or target RAM.

AIM-ZSOAE (4.0 MHz max. clock rate)
The AIM-ZaOAE is an improved version of the above module
usable at zao-cpu clock rates of up to 4MHz. The AIMZaOAE is a two-processor solution to in-circuit emulation
which utilizes a zao-cpu in the buffer box for accurate
emulation at high clock rates with minimum restrictions on
the target system. The AIM-ZaOAE provides real-time
emulation (no WAIT states) while providing full access to
RESET, NMI and INT control lines. Eight single-byte
software breakpoints (in RAM) are provided as well as one
hardware trap (RAM or ROM). The emulation RAM on the
AIM-ZaOA is mappable into the target system in 256-byte

XV-5

increments. A 1024 word x 48-bit history memory is
triggerable by the hardware intercept and can be read back
to the terminal to provide a formatted display of the Z80CPU address, data, and control busses during the execution
of the program under test. Several trigger options are
available to condition the loading of the history memory.

Summary of Editor Commands
Advance N
Backup N
Change
N/S1/S2
Delete N

A/D-SOE

Exchange N

A family of 12-bit AID and DI A modules for the MATRIX
system. Options include single-ended or differential inputs
up to 64 channels per module.

Get file

Insert
AIM-72E

Line N
Macro 1 or
Macro 2

The AIM-72E module provides debug and in.-circuit
emulation capabilities for the 3870 series microcomputers
(3870, 3872, 3874 and 3876) on the MATRIX. Multiplebreakpoint capability and single-step operation allow the
designer complete control over the execution of the 3870
Series microcomputer.

Put N file
Quit

Register, Port display, and modification capability provides
information needed to find system "bugs." All 110 is in the
user's system connected to AIM-72 by a 40-pin interface
cable.

Search N/S1

Top

,

The .debugging operation is controlled by ZAIM-72, a
mnemonic debugger which controls the interaction
between the Z80 host computer and the 3870 slave. It
includes a history module for the last 1024 CPU cycles and
also supports all 3870 family circuits.

Verify N

Write N

Assembly and linking is done using the MACRO-70
Assembler and the standard FLP-80DOS linker.

eXecute N
Breakpoint

DDT
Register
Offset

The Designer's Debugging Tool consists of commands for
facilitating an otherwise difficult debugging process. The
MATRIX rapid source changes through the editor and reassemblies, followed by DDT operations close the loop on
the debug cycle. The DDT commands include:
Memory
Port
Execute
Hexadecimal
Copy

- display, update, or tabulate memory
- display, update or tabulate 1/0 ports
- execute user's program
- performs 16 bit addl sub
- copy one block to another

Fill
Verify
Walk
Quit

- advance line pointer N line
- backs up N lines
- change N occurrences of String 1 to
String 2
- delete current line plus next N-1 lines
of text
- exchanges current line plus next N-1
lines with lines to be inserted while in
insert mode
- reads another file and inserts it into
the file being edited after the current
line
- place Editor in insert mode. Text will
be inserted after present line
- place line pointer on Line N.
- defines Macro 1 or Macro 2 by the
following string of Text Editor commands.
- outputs N lines of the file being edited
to another disk file.
- stores off file under editing process
and returns to Monitor environment
- searches from existing pointer
location until Nth occurrence of
string Sl is located and prints it.
- inerts records at top of file before
first line.
- print current record to console plus
next N-1 records while advancing
pointer N records ahead.
- prints current records plus next N-1
records to source output device while
advancing pointer N records.
- executes Macro 1 or Macro 2 as
defined by Macro command.
- sets software trap in user code for
interrupting execution in order to
examine CPU registers
- displays contents of user's registers
- enters address adder for debug of
relocatable modules
- fills specified portion of memory with
8 bit byte
- compares two blocks of memory
- software single steplmultistep
- retu rns to Mon itor

Debuggers for other processors have similar or enhanced
capability and are included with the appropriate AIMTM;

XV-6

INPUT VOLTAGE

Disk subsystem -

100/11 51230 volts AC± 10%
50 Hz (MK78189) or 60 Hz (MK78188)

HUMIDITY
Up to 90% relative, noncondensing.

OUTPUT VOLTAGES
CPU subsystem

Disk subsystem

8" high x 21" wide x 22" deep
(20.3 cm x 53.3 cm x 55.8 cm)

MATERIAL

+5 VDC at 12 A max.
+12 VDC at 1.7 A max.
-1 2. VDC at 1 .7 A max.

Structural Foam (Noryl)
WEIGHT

+5 VDC at 3.0 A max.
-5 VDC at 0.5 A max.
+24 VDC at 3.4 A max.

CPU Subsystem 25 Ibs. (11.3 Kg)
Disk Subsystem 50 LBS. (22.7 Kg)

OPERATING TEMPERATURE
FAN CAPACITY
+1 O°C to +40°C
115 CFM
OVERALL DIMENSIONS
CARD CAGE
CPU subsystem -

8" high x 21" wide x 22" deep
(20.3 cm x 53.3 cm x 55.8 cm)

Six slots DIN 41612 type connectors

ORDERING INFORMATION
BASIC SYSTEM

DESIGNATOR

DESCRIPTION

PART NO.
:,"

MATRIXTM

Z80 floppy disk-based microcomputer with 60K bytes
of RAM (56K bytes contiguous RAM), 4K bytes PROM
bootstrap, two 250K-byte single-density floppy disk drives
with Operations Manual. Includes the software packages
of FLP-80DOS and MACRO-80 distributed on diskette.
Requires signed license agreement with purchase order.

MK78188 (60 Hz)
MK78189 (50 Hz)

MATRIXTM Operations Manual Only

MK79730

FLP-80DOS Operations Manual Only

MK78557

MACRO-80 Operations Manual Only

MK79635

XV-7

IN-CIRCUIT EMULATION MODULES
DESIGNATOR

DESCRIPTION

PART NO.

AIM-80E

2.5 MHz RAM-based Z80 In-Circuit Emulator with buffer
box, cables and Operations Manual

MK78106

AIM-80E Operations Manual Only

MK78559

4.0 MHz RAM-based Z80 In-Circuit Emulator with expanded
history trace, buffer box, cables and Operations Manual
16K Bytes emulation RAM
32K Bytes emulation RAM

MK78181-1
MK78181-2

AIM-Z80AE Operations Manual Only

MK79650

RAM-based In-Circuit Emulator for the 3870 series of
single-chip microcomputers (3870, 3872, 3874 and 3876)
with cables and Operations Manual

MK79077

AIM-72E Operations Manual Only

MK79079

AIM-Z80AE

AIM-nE

XV-8

MOSTEI(.
DEVELOPMENT SYSTEMS

MATRIX-80/S0T
MK78197
FEATURES

o One single-density, single-sided disk drive; 250K bytes
per floppy disk

o zao CPU based
o 4K-byte PROM bootstrap and zao debugger

o Device drivers for paper tape readers, punches, card
readers, line printers, Silent 7oo's, Teletypes and CRT's
are included. Others can be added

o RAM option of 4aK or 64K bytes
o Two a-bit 1/0 ports for Line Printer PROM programmer
o Serial port: RS-232C and 20mA current Loop

o PROM programmer 1/0 port. Programmer itself is
optional
o BUS compatible with Mostek STD-ZaO MD Series
boards

?CV-9

XV-10

MOSTEI{.
DEVELOPMENT KITS

MDX-PROTO
MK77951-0, MK77951-4
FEATURES

MDX-PROTO BOARD PHOTO

o STD-Z80 Bus compatible

o

6-slot card cage with mother board (MK77954)

o

MDX-CPU1 module (MK77850-0, MK77850-4)

o

MDX-DRAM8 module (MK77750-0): 2.5MHz version

o

MDX-DRAM16-4 module (MK77754-4): 4MHz version

o

MDX-DEBUG module (MK77950-0, MK77950-4)

o

MD-WW2 Wire-wrap board (MK77952)

o

MD-EXT Extender board (MK77593)

o

Cables for RS-232 device (MK77955) orTIY (MK77956)

o

4MHz option available (MDX-PROTO-4)

DESCRIPTION
The Mostek MDX-CPU1 is the heart of an MD Series Z80
system. Based on the powerful Z80 microprocessor, the
MDX-CPU1 can be used with great versatility in an OEM
microcomputer system application. This is done simply by
inserting custom ROM or EPROM memories into the
sockets provided on the board and configuring them
virtually anywhere within the Z80 memory map.

CPUl-4). In this version, one wait cycle is automatically
inserted each time on-board memory is accessed by a read
or write cycle. This is necessary to make the access times of
the 2716 PROMs and the 3539 scratch pad RAM
compatible with the MK3880-4 4MHz Z80-CPU.

On-board memory is provided in the form of 4K of EPROM
(two-2716's) and 256 bytes of scratchpad RAM as pictured in
the block diagram. In addition, a MK3882 Counter/Timer
Circuit is included on the MDX-CPU1 to provide counting
and timing functions for the Z80. Either 2716 EPROM can
be located atany 2K boundary within any given 16K block in
the Z80 memory map via a jumper arrangement.

The MDX-DRAM is designed to be a RAM memory
expansion board for the Mostek MD Series of Z80 based
microcomputers. It is available in three memory capacities:
8K bytes (MDX-DRAM8), 16K bytes (MDX-DRAM16), and
32K bytes (MDX-DRAM32). Additionally, the MDXDRAM16 and the MDX-DRAM32 are available in a 4MHz
version. Thus, the designer can choose from the various
options to tailor his add-on dynamic RAM directly to his
system requirements.

The MDX-CPU1 can be used in conjunction with the MDXDEBUG and MDX-DRAM modules to utilize DDT-80 and
ASMB-80 in system development. This is accomplished by
strapping the scratchpad RAM to reside at location FFOO so
that it will act as the Operating System RAM for DDT-80.
The MDX-CPU1 is also available in a 4MHz version (MDX-

MDX-DRAM DESCRIPTION

The MDX-DRAM8 is designed using Mostek's MK4108
8, 192-bit dynamic RAM. The MDX-DRAM32 utilizes highperformance MK4116, 16K-bit dynamic RAMs which allow
4MHz versions of these boards to be offered. No wait-state
insertion circuitry is required on any of the RAM cards.

XV-11

MDX-PROTO BLOCK DIAGRAM
STDZBO BUS

L:==>lRAS

20 MA INPUT.
OUTPUT AND
READER STEP

RS-232
INPUT. OUTPUT
AN~MODEM

'CoNTROL
MDX-CPU 1

MDX-DRAM

Address selection is provided on all MDX-DRAM cards for
positioning the SK. 16K. or 32K of memory to start on any
4K boundary.

DDT-SO COMMAND SUMMARY
Ms
M s, f
-p s

MDX-DEBUG DESCRIPTION
The MDXcDEBUG Module has sockets for 10K bytes of
masked, ROM that are populated with a ZSO firmware
package (D,DT-SO/ ASMB-SO), This module has a STD BUS
interface and is available in both .2.5MHz and 4,OMHz
versions. Included on board is a fully buffered asynchronous
I/O port capable of 110-19200 baud rates, Serial Data
interf~ces are available for 20mA current loop (with reader
step control) and RS-232.

D's.f

L
Es
H

C s.f.d
DEBUGGER DESCRIPTION
B s,

DDT-SO is the Operating System for the MDX-DEBUG
Module and resides in a 2K ROM (MK34000 series), It
provides the necessary tools and techniques to operate the
system i.e., to efficiently and conveniently develop
microcomputer software, DDT-SO is designed to support
the user from initial design through production testing. It
allows the user to display and update memory. reg isters and
ports. load and dump object files. set breakpoints. copy
blocks of memory. and execute programs.

MDX-DEBUG

R

- Display and/or update'the contents of
memory location s,
- Tabulate the contents of memory locations s
through f.
- Display and/or update the contents of I/O
port s.
- Dump the contents of memory locations s
through f in a format suitable to be read by
the L command.
- Load data which is in the appropriate format
into memory.
- Transfer control from DDT'SO to a user's
program starting at location s,
- Perform 16-bit hexadecimal addition and/or
subtraction.
- Copy,the contents of memory locations s
through f to another location in memory
starting at location d.
- Insert a breakpoint in the' user's program
(must be in RAM) at location s which
transfers control back to DDT-SO, This
allows the user to intercept his program ata
specific point (location s) and examine
memory and CPU registers to determine if
his program is working correctly:
- Display the contents of user registers.

The s.f. and d represent start" finish, and destination,
operands required for each command. "
XV-12

MEMORY. PORT AND REGISTER COMMANDS
(M.P.R)
The M. p. and R commands provide the means for
displaying the contents of specified memory locations. port
addresses. or CPU registers. The M and P commands
sequentially access memory locations or ports and display
their contents. The user has the option of updating the
content of the memory location or port. (Note some ports are
output only and their contents cannot be read or displayed.)
The M command also gives the user access to the CPU
registers through an area in RAM called the Register Map
(discussed in the Execute and Breakpoint section below).
The M and R commands are used to tabulate blocks of
memory locations (M) or the CPU registers (R). The M
command will accept two operands. the starting and ending
addresses of the memory block to tabulated. The R
command will accept either no operand or one. If no
operand is specified. the CPU registers will be displayed
without a heading. If an operand is specified. then a heading
which labels the register contents will be displayed as well.
EXECUTE AND BREAKPOINT (E.B)
The E command is used to execute all programs. including
aids such as the Assembler. The B command is used to set a
breakpoint to exit from a program at some predetermined
location for debugging purposes. At the instant of a
breakpoint exit. the contents of all CPU registers are saved
in a designated area of MDX-DEBUG RAM called the
Register Map. In the Register Map. the register contents
may be examined or modified using the M command and a
predefined mnemonic (or absolute address) of the storage
location for that register (example: PC. :A. .... :SP). The
Register Map is also used to initialize the CPU registers
whenever execution is initiated or resumed. Thus the E and
B commands can be used together to initialize. execute. and
examine the results of individual program segments.

HEXADECIMAL ARITHMETIC (H)
The H command is a dummy command used to allow
hexadecimal addition and subtraction for expression
evaluation without performing any other operation.

DDT-SO I/O CAPABILITIES
DDT-SO specifies I/O channels. designated 'Console\,
·Object'. and ·Source'. to which any suitable devices milY be
assigned. The Channel Assignment Table is located in RAM
where it may be examined or modified using the M
command. The table addresses correspond to the I/O
channels and the table contents correspond to 1he
addresses of the peripheral driver routines. A channel
which has a device assignment may have that devic!,!
assignment changed using the M command. This is
accomplished by merely modifying the table contents ofthat
channel's table address to correspond to the new peripheral
driver routine. A set of peripheral driver routines is supplied
and listed below. This scheme also allows the user to write
a driver routine for his own peripheral. load it into memory.
and easily configure that peripheral into the system.

DDT-SO I/O PERIPHERAL DRIVERS

1. A serial input driver (usually a keyboard).
2. A serial output driver (usually a CRT or teletype
typehead).

3. A serial input driver which sends out a reader step signal
(usually a teletype reader).

4. A serial output driver which forces a delay after a
carriage return (usually a Silent700 typehead).

5. A parallel input driver (usually for high-speed paper tf;lpe
input)

6. A parallel output driver (usually for high-speed paper
tape output).

The B command gives the user the option of having all CPU
registers displayed when the breakpoint is encountered.
This is done by entering a second operand to the B
command. Otherwise. DDT-SO defaults to displaying the PC
and AF registers. When all CPU registers are displayed. the
format is the same as for the R command previously
discussed.

7. A parallel output driver (usually for a line printer).
TEXT EDITOR DESCRIPTION

The Land 0 commands load and dump object files through
the object I/O channel in standard industry Hex format.
Check sums are used for error detection. and the addresses
of questionable blocks are typed automatically while
loading.

The Text Editor permits random access editing of ASCII
character strings. It can be used as a line or characteroriented editor. Individual characters may be located by
position or context. The Editor works on blocks of characters
which are typically read into memory from magnetic tape or
paper tape. Each edited block can be output to magnetic
tape or paper tape after editing is completed. While the
primary application for the Text Editor is in editing assembly
language source statements. it may be applied to any ASCII
test delimited by "carriage returns".

The Ccommand will copy the contents ofthe memory block
specified to another block of memory. There are no
restrictions on the direction of the copy or on whether the
blocks overlap.

The Editor has a macro command processing option. Up to
two sets of commands may be stored and processed at any
time during the editing process. All I/O is done via thE!
DDT-SO channels. The Editor can be used with the Mostek

LOAD. DUMP. AND COPY. (L.D.C)

XV-13

ASMB-80 Assembler and Loader to edit, assemble, and
load programs in memory without the need for external
media for intermediate storage.

LIST
NLiST

- turn listing on
- turn listing off

RELOCATING LINKING LOADER DESCRIPTION
The following commands are recognized by the Text Editor:
The Mostek Relocating Linking Loader provides state-ofthe-art capability for loading programs into memory by
allowing loading and linking of any number of relocatable
and non-relocatable object modules. Non-relocatable
modules are always loaded at their starting address as
defined by the ORG pseudo-op during assembly.
Relocatable object modules can be positioned anywh'ere in
memory at an offset address.

An
- Advance record pointer n records
Bn
- Backup record pointer n records
Cn dS1 dS2D - Change string Sl to string S2 for n
occurences
Dn
- Delete n records
- Excha nge current record with records
E
to be inserted
- Insert records
- Go to line number n.
Ln
- Enter command buffers (pseudo-macro)
Mn
- Print top, bottom and current line number
N
- Pu nch n records from buffer
Pn
- Read source records into buffer
R
- Search for nth occurrence of signal Sl
Sn dS1 d
ASSEMBLER DESCRIPTION
The Assembler reads Z80 source mnemonics and pseudoops and outputs an assembly listing and object code. The
assembly listing shows address, machine code, statement
number, and source statement. The object code is in
industry-standard hexadecimal format modified for relocatable, linkable assemblies.
The Assembler supports conditional assemblies, global
symbols, relocatable programs and a printed symbol table. It
can assemble any length program, limited only by a symbol
table size which is user-selectable. Expressions involving
addition and subtraction are allowed. A global symbol is
categorized as "internal" if it appears as a label in the
program; otherwise it is an "external" symbol. The printed
symbol table shows which symbols are internal and which
are external. The assembler allows the user to select
relocatable or non-relocatable assembly via the "PSECT"
pseudo-op. Relocation records are placed in the object
output for relocatable assemblies. (The Mostek object
format is defined below.) The Assembler can be run as a
single-pass assembler or as a learning tool. (In this mode,
global symbols and forward references are not allowed.)
The followi ng pseudo-ops are recognized by the Assembler:
EQU
DEFL
DEFM
DEFB
DEFW
DEFS
END
NAME
PSECT

EJECT
TITLE

- equate label
- defi ne label
- defi ne message
- defi ne byte
- define word
- define storage
- end statement
- program name definition
- global symbol definition
Supports the following assembler
psuedo-ops
- eject a page of listing
- place headi ng at top of each page

The Loader automatically links and relocates global symbols
which are used to provide communication or linkage
between program modules. As object programs are loaded,
a table containing global symbol references and definitions
is built up. At the end of each module, the loader resolves all
references to global symbols which are defined by either the
current or a previously loaded module. It also prints on the
console device the number of defined global symbols that
have been referenced. The symbol table can be printed in
order to list all global symbols and their load .address. The
number of object modules which can be loaded by the
Loader is limited only by the amount of RAM available for
the modules and the symbol table. Space for the symbol
table is allocated dynamically downward in memory from
either the top of memory or from a specified address entered
as an operand of the load command.
All I/O is done via the DDT -80 channels. Assembliescan be
done from source statements stored. in memory (by the
Editor). The object output can be directedto a memory buffer
rather than to an external device. Thus, assembly and
loading can be done without external storage media.
The Loader prints the beginning and ending address of each
module as it is loaded. The trapsfer address as defined by
the END pseudo-op is printed for the first module loaded.
The Loader execute command (E) can be used to
automatically start execution at the transfer address.
The Loader Commands are the following:
L offset

E
T

- loadobject module at address "offset" plus
program origin address
- execute loaded program at transfer address
of first module
- print global symbol table

MOSTEK OBJECT OUTPUT DEFINITION
Each record of an object .module begins with a delimiter
(colon or dollar sign) and ends with carriage return and line
feed. A colon (:) is used for data records and end-of-file
record. A dollar sign ($) is used for records containing
relocation information and linking information. All information is in ASCII. Each record is identified by ';type". The type
is determined by the 8th and 9th bytes of the record which

XV-14

OBJECT MODULE TYPES

rDEUM""R
1

•
•
•
•

2

RECORD TYPE

,----A--..

3

'0

4

.

7

6
I

START ADDRESS
OF DATA

.

0

5
I

#OF
BINARY 4
DATA BYTES

I

110

9
I

0

0

.

TRANSFER ADDRESS
OF MODULE

0

8

·

0

CHECK
SUM

DATA

CHECK
SUM

1

CD1

CD

I

·

INTERNAL
SYMBOL NAME

$

.

I

0

2

0

3

CD1

CHECK
SUM

ADDRESS

J

$

$

EXTERNAL SYMBOL NAME
#OF ~
BINARY
BYTES

.

i

I

CD4

0

0

0

0

MODULE NAME

$

--L

i

·-

0

CHECK
SUM

CD

1

ADDRESSES WHICH
... REQUIRE RELOCATION ...

4

0

.

UNK
ADDRESS
I

.

CD1

CHECK
SUM
I

i

FLAGS

6

0

0

CD

I

NOTES:
1. Check Sum is negative of the binary sum of all bytes except delimiter and carriage return/line feed.
.
2. Link Address points to last addresS in the data which uses the external symbol. This stans a backward link list through the data records for that external symbol. The list
terminates at OFfFfH.
3. The flags are one binary byte.
0- absolute module
1 - relocatable module
4. Maximum of 64 ASCII bytes.

en 0 is defined as:

can take the following values:
00 - data
01 - end-of-file
02 - internal symbol
03 - external symbol
04 - relocation information
05 - module definition

MEMORY CAPACITY
On-Board EPROM - 4K bytes (sockets only)
On-Board RAM-256 bytes
Off-Board Expansion - Up to 65,536 bytes with userBoard Expansion - specified combinations of RAM, ROM,
PROM
MEMORY ADDRESSING

MDX-CPU1 SPECIFICATIONS
WORD SIZE

On-Board EPROM: jumper-selectable for any 2K boundary
within a 16K block of zao memory map.
On-Board RAM: FFOO-FFFF

Instruction: a, 16, 24, or 32 bits
Data: bits

MEMORY SPEED REQUIRED

a

CYCLE TIME
Clock period or T state = 0.4 microsecond at 2.5MHz
0.25 microsecond at 4.0MHz
Instructions required from 4 to 23 T states

Memory
2716*

Access Time
450ns

*Single 5-volt type required

XV-15

Cycle Time
450ns

1/0 ADDRESSING

ADDRESS SELECTION

On-Board Programmable Timer

Selection of 8K, 16K, or 32K contig uous memory blocks to
reside at any 4K boundary.

Port
Address (HEX)
7C
7D
7E
7F

MK3882
Channel

ACCESS TIME

o
1

2
3
MDX-DRAM
MDX-DRAM-4

1/0 CAPACITY
Up to 252 port address can be decoded off-board. Four port
addresses are on-board. 252 + 4V = 256 total 110 ports.

SYSTEM CLOCK

INTERRUPTS

MDX-DRAM
MDX-DRAM-4

Multi-level with three vectoring modes (Mode 0,1,2).
Interrupt requrests may originate from user-specified 1/0 or
from the on-board MK3882 CTC.

Memory
Access
Times

Memory
Cycle
Times

2.5MHz
4.0MHz

350ns max.
200ns max.

465ns min.
325ns min.

MIN
1.25MHz
1.25MHz

MAX
2.5MHz
4.0MHz

SYSTEM INTERRUPT UNITS (SIU) = 1
STD BUS INTERFACE

SYSTEM CLOCK

MDX-CPU1
MDX-CPU-4

System
Clock

MIN
500 kHz
500 kHz

MAX
2.50MHz
4.0MHz

Inputs:
Outputs:

One 74LS load max.
10H = -3mA min. at 2.4 volts
10L = 24mA min. at 0.5 volts

OPERATING TEMPERATURE
SYSTEM INTERRUPT UNITS (SIU) = 1
O°C to 60°C
STD BUS INTERFACE
Inputs:
Outputs:

One 74LS load max.
10H = -3mA min. at 2.4 volts
10L = 24mA min. at 0.5 volts

POWER SUPPLY REQUIREMENTS
+5V ± 5% at 0.6A max.
+12V ± 5% at 0.25A max.
-12V ± 5% at 0.03A max.

OPERATING TEMPERATURE
MDX-DEBUG SPECIFICATIONS
POWER SUPPLY REQUIREMENTS
WORD SIZE
5V ± 5% at 1.1A maximum
8 bits for PROM
5 to 8 bits for serial 1/0
MDX-DRAM SPECIFICATIONS
WORD SIZE
8 bits
MEMORY SIZE
MDX-DRAM8 - 8,192 bytes
MDX-DRAM16 - 16,384 bytes
MDX-DRAM32 - 32,768 bytes

MEMORY SIZE
10K bytes of firmware
MEMORY ADDRESSING
2K blocks jumper-selectable for any 2K boundary within a
given 16K block ofthe Z80 memory map. MDX-DEBUG has
ROMs strapped every 2K beginning at COOOH.

XV-16

1/0 ADDRESSING

CARD DIMENSIONS

On-board Serial 1/0 Port
Control Port: XXXXXX01
Data Port: XXXXXXOO
Module and Reader Step Control Port: XXXXXX10
XXXXXX represents six strap-selectable address bits

4.5 in. (11.43 cm) high by 6.50 in. (16.51 cm) long
0.48 in. (1.22 cm) maximum profile thickness
0.062 in. (.016 cm) printed-circuit-board thickness

SYSTEM CLOCK

CONNECTORS

MDX-DEBUG
MDX-DEBUG-4

MAX.

MIN.
250KHz
250KHz

2.5MHz
4.0MHz

Function
STD-Z80 BUS

Configuration
56-pin

SERIAL COMMUNICATIONS INTERFACE
0.125 in. centers

BUFFERED FOR:
20mA
RS-232
Current
Loop

SIGNAL

Transmitted data
Received data
Data Terminal Read (DTR)
Request to Send (RTS)
Carrier Detect (CDET)
Clear to Send (CTS)
Data Set Ready (DSR)
Reader Step relay (RS)

Output
Input

Output
Input
Input
Input
Output
Output
Output

Serial 1/0

26-pin
0.100 in. grid

FLAT RIBBON
Ansley 609
2600M
DISCRETE WIRES
Winchester
PGB26A
(housing)
Winchester
100-700205
(contacts)

=0

STD BUS INTERFACE
Inputs:
Outputs:

WIRE WRAP
Viking 3VH281
1CND5
SOLDER LUG
Viking 3VH281
1CN5

Output
(40mA)

SYSTEM INTERRUPT UNITS (SIU)

Mating
Connector
PRINTED CIRCUIT
Viking 3VH281
1CE5

One 74LS load max.
10H = -3mA min. at 2.4 volts
10L = 24mA min. at 0.5 volts

OPERATING TEMPERATURE

POWER SUPPLY REQUIREMENTS
+ 12 Volts ± 5% at 50 rnA max.
-12 Volts ± 5% at 35 rnA max.
+5 Volts ± 1 .2 rnA max.

1/0 TRANSFER RATE
110, 300, 600, 1200, 2400, 4800, 9600, 19200 baud

XV-17

ORDERING INFORMATION
DESIGNATOR

DESCRIPTION

PART NO.

MDX-PROTO

Prototyping package with Operations Manuals.
2.5 MHz version.
Note: 2.5 MHz version includes 8K dynamic RAM board
MDX-DRAMB only.

MK77951

MDX-PROTO-4

Prototyping package with Operations Manuals.
4.0 MHz version.
Note: 4.0 MHz version includes 16K dynamic RAM board
MDX-DRAM16-4.

MK77951-4

XV-18

MOsm<.

DEVELOPMENT SYSTEMS EMULATION BOARDS

A~M*-80E

MK78106
HARDWARE FEATURES

AIM-BOE BOARD PHOTO

o Direct interface with OEM-aOE

o

Single-step/multistep with register trace

o

Execution intercept (breakpoint) intercepts on memory
access, port access, external trigger, event counter, or
delay counter

o

Push-button execution intercept

o

256 x 32 history memory which samples Data Bus,
Address Bus, M1, MREO, RD, IORO, and four external
probes

o

History memory clock-selectable from M 1, MREO, IORO,
or INTERRUPT ACKNOWLEDGE

o

Selectable history memory clock conditions: read only,
write only, DMA only, or external probe only (high or low)

o

aK x a ROM memory (firmware)

SOFTWARE FEATURES

o

ROM-resident mnemonic dis-assembler

o

ROM-resident RAM test for SDB or target RAM

DESCRIPTION
AIM-BOE provides zao system debug assistance for both
software and hardware via in-circuit emulation. (See Block
Diagram)
Single-step/multistep allows the programmer to trace
through a program and display the CPU registers after each
instruction. The execution intercept feature allows
suspending program execution on the nth occurrence of an
address or other specified condition. If the program has
begun an unknown sequence, the intercept pushbutton will

return the system to the single-step mode. Single-step and
execution intercept (breakpoint) operate in RAM or
ROM/PROM.
Hardware debugging is aided greatly by use of the 256 x 32
history memory which monitors bus transactions for a
specified period. This information may then be displayed on
the console. The data bus, address bus, M1, MREO, RD,
IORO, and inputs from four probes are sampled and stored
in the hif"tory memory upon every occurrence of the userspecified clock (M1, MREO, IORO, or interrupt
acknowledge) qualified by the user-specified conditions
(read only, write only, DMA only, probe High only, or probe
Low only). Upon the occurrence of the selected intercept,
.AIM-aOE returns control to the system debug (DDT-aO). The
history memory may then be displayed (See Figure 1) with
or without mnemonic dis-assembly.

• Trademark of Mostek Corporation

XVI-1

BLOCK DIAGRAM

r---------------------,

I
I

PROBES

I
I
I

I
I
I

I
I

I TARGET

I
I

I

I
I

1________

___

AIM-SOX

-+---

SYSTEM

I
JI

TARGET
INTERFACE
BUFFER

PROBE SIGNALS
SYSTEM CONTROL
CPU CONTROL
ADDRESS BUS
DATA BUS
BUFFER CONTROL SIGNAL
/
/

AIM-BOE
CONTROL CARD
S2 (CLOCK SELECT)

~~----~~----~----~~~

ROM
SKxS

HISTORY
RAM
256 x32

BUFFER
CONTROL

SINGLE
STEP

BAUD
RATE

OEM-SOE
SYSTEM BUS

XVI-2

AIM-SOE PRINTOUT EXAMPLE
(User entries underlined)

.I2,Tl..

Set intercept at address 0002H with trigger option

TRIG D~ (MREQ'IORQ/+/-. M
EVENT CNT (I-FF) 2
DELAY CNT (O-FFl 3
CLOCK ON (Ml,MREQ,IO~Q,INT8) MR TO
ONLY IF (RD,WR-DMA'H/L'

Trigger on MRm
After 2 occurrences
Delay 1 clock after trigger
Clock history (sample) memory on MREO or lORa
No qualifying conditions selected
Begin execution at address 0002H
Intercept occurs at second occurrence of addres!i
2 with a delay of one.

.~

02

00 C":', 24::0 1

At this point the history memory contains the bus transactions which occurred before the intercept.

Aq;

Trace for 15 lines· starting at
.r------offset ·11 before trigger.
Offset from trigger
Memory Address Bus contents
Data Bus contents

~

•.LE...!.=.E 1.

~Dis-assembled instructions
Control Bus

I

I

0, 8DD~' [IB
-DB 0000 3E

- 08

I) 0" 1

;:: I)

- 09

"~11

LD

au T

A,20~

(0) , A

I)

0
0

1
1

I)

1

1

0

1
CI

1
1

1 - First occurrence of address 0002H
1
1

1
1

1
1

1
1
1
1

1
1
1
1

2000
0004
0(10'5
-04 OOOE.
-o~: 0007
-02 I) fl o:.~
-1)1 00CI 9
+00 OO(i,::
+01 01)(13
+OC' 2300
+0:3 0004

20
3C
3C

H!;~:

A

(I

I)

INC

0

'::C
("3

IN':
.IP

A
"1

I)

U1)02!-j

0

0
0
0

o;::~

0

I)

01)

U

(I
I)

(I

I)

0

1

(,0.1 ,A

00

0
0
0
(,
(I

2:=:

.-,,..:.'-.0

HIe:

Ft

I)

(I

Y

.0

1.1 0

'J1_:r

G

1
1

[r?

-Fe

,)
I~I

E:

1
1

0

I) 0 1);:0

D3

0

'i'll;O,;;:D 10 R

- 08 0 (I (I ::

-o?
-U6
-os

Prsbes (red, blue, green, yellow)
I

I

1

(I

I)

1

1
1 - Trigger (OS ~ 01 (2nd occurrence
1
1
of address 0)
11
1
1"""'-- Delay 1 count after trigger

?..:.. 0(

No more data in history module

USING THE AIM-SOE

assembler makes correlation with the user's source listing
easier and reduces the necessity of memorizing op codes.

AIM-80E may be added directly to any OEM-80E system. All
system bus signals are wired one to one between OEM-80E
and AIM-80E. Voltage requirements for the AIM-80E are
the same as for the OEM-80E. Programs may be debugged
in OEM-80E memory space or, with the target interface
buffer box (AIM-80X), may be debugged in the target
environment. Dynamic memory mapping allows target
memory to be simulated using OEM-80E system RAM. All
peripheral devices of the OEM-80E are still functions with
the AIM-80E.

OPERATING FREQUENCY
2.5 MHz (with OEM-80E)
INTERFACE
OEM-80E compatible
TOP CONNECTORS
One 40-pin 3M ribbon
One 50-pin 3M ribbon

SYSTEM FIRMWARE
To minimize the impact of the AIM-80E, firmware is
resident in one MK360OQ, 8K x 8 ROM. This firmware is
completely compatible with DDT-80 firmware and includes
five new commands for control of the AIM-80E. The
interactive nature of the commands makes operation
simple and avoids operator errors. The ROM-resident dis-

OPERATING TEMPERATURE RANGE
O°C to +50°C
POWER SUPPLY REQUIREMENTS (Typical)
+ 12V ± 5% at 12mA
+5V ± 5% at 1.0 Amp

XVI-3

. BOARD SIZE
250mm x 233.4mm x 18mm

BOTTOM CONNECTORS
Dual 64-pin Eurocard
Connector, DIN 41612, form
D; A and C Pinned

ORDERING INFORMATION
....

DESIGNATOR
AIM-80E

PART NO.

. DESCRIPTION
AIM-80E Control Card includes AIM-80E Firmware and
AIM-80E Operations Manual

MK78106

Target Interface Buffer (AIM-80X) includes: cables, connectors,
4 probe clips
.
..
AIM-80E Operations Manual only

)(VI-4

....

MK78559

MOSTEl{.
DEVELOPMENT SYSTEMS EMULATION BOARDS

AIM*-Z80AE
MK78181-1, M K78181-2
HARDWARE FEATURES

o

Direct interface to Mostek's development system

o

In-circuit emulation of ZSO or ZSOA microprocessors

o

Real-time execution (4 MHz - no wait states)

o

Flexible breakpoints (hardware and eight single-byte
software)

o

Single-step execution

o

16K bytes emulation RAM (expandable to 32K bytes)

o

Memory Mappable into Target system in 256 byte blocks

o

Illegal write to memory detection

o

Nonexistent memory access detect

AIM-Z80AE SYSTEM PHOTOGRAPH

o Forty-eight channel by 1024 words history memory

o

Event counter

o .Delay counter
o

Execution T-state timer

o

Keyboard escape function

SOFTWARE FEATURES

o

Simple-to-use, single character commands.

o

Flexible display format includes disassembly of opcodes

o

System configuration parameters stored on disk for
future use

space or ports are used and all signals including RESET,INT
and NMI are functional during emulation.
Single-step circuitry allows the user to execute Target
instructions one at a time to see the exact effect of each
instruction. Single step is functional in ROM as well as
RAM.
Sixteen K bytes of emulation RAM may be mapped into the
Target memory map at any desired address so that software
may be developed even before Target memory is available.
Breakpoint-detect circuitry allows real-time execution .to
proceed to any desired point in the user's program and then
terminate with all registers and status information saved so
that execution may later be resumed. Real-time execution
may also be terminated at any time by enabling the Escape
Key. EVENT and DELAY counters give added flexibility for
viewing the exact point of interest in the user's program.

DESCRIPTION
AIM-zaOAE is an advanced development tool which
provides debug assistance for both software and hardware
via in-circuit emulation of the zao microprocessor. Use of
the AIM-ZSOAE is completely transparent to the user'sfinal
system configuration (referred to as the Target). No memory
'Trademark of Mostek Corporation

A 4S-channel history circuit will simultaneously record any
bus transaction which the user may desire to see. The
address bus, data bus and control signals plus eighteen
external probes which can be used to monitor the Target
system's circuitry at other points are recorded by the History
circuit.
XVI-5

SYSTEM PHOTOGRAPH
AIM-Z80AE

USING THE AIM-Z80AE
AIM-Z80AE is partitioned on three modules. The Control
and History modules are installed directly into the
development system. Cables from these modules connect
to the Buffer module which plugs directly into the Target"
system'sZ80CPU socket. AfterAIM-Z80AE is installed, the
development system is powered up and the system booted
up as normal. All development, system software and

hardware are still functional. The software to control AIMZ80AE (AIMZ80) is initialized by using the implied run
command. AIMZ80 will sign on, take control of the Target
system and allowthe user to initialize the Target system and
use any of the AIMZ80 commands to load, test, and debug
his Target program. An exarnple of the use of some of the
AIMZ80 commands is given in the following examples.

XVI-6

AIM-Z80AE INITIALIZATION
EXAMPLE 1

$AIMZ80(CR)

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