1980_Motorola_Memory_Data_Manual 1980 Motorola Memory Data Manual
User Manual: 1980_Motorola_Memory_Data_Manual
Open the PDF directly: View PDF 
.
Page Count: 384
| Download | |
| Open PDF In Browser | View PDF |
MEMORY
QUALITY
RELIABILITY
TECHNOLOGY
SELECTOR
GUIDES
CROSS-REFERENCE
MOS Memories
RAM, EPROM, EEPROM, ROM
•
CMOS Memories
RAM, ROM
Bipolar Memories
TTL, MECL-RAM, PROM
Memory Boards
Mechanical Data
•
•
II
MOTOROLA
MEMORIES
Prepared by
Technical Information Center
Motorola has developed a very broad range of reliable MOS and
bipolar memories for virtually any digital data processing system application. Complete specifications for the individual circuits are provided in the form of data sheets. In addition, selector guides are included to simplify the task of choosing the best combination of circuits for optimum system architecture.
New Motorola memories are being introduced continually. For the
latest releases, and additional technical information or pricing, contact your nearest authorized Motorola distributor or Motorola sales office.
The information in this book has been carefully checked; no responsibility, however, is assumed for inaccuracies. Furthermore, this information does not convey to the purchaser of microelectronic devices
any license under the patent rights of the manufacturer.
Printed In U.S.A.
Series B
©MOTOROLA INC., 1980
Previous Edition ©1979
"All Rights Reserved"
MECL, EXORciser are trademarks of Motorola Inc.
ii
Table of Contents
Organization
Page
Alphanumeric Index ..................................................................................................................v
CHAPTER 1
Memories Selection Guide...................................................................................................... 1-2
Memory Systems Board Selector Guide and Cross Reference .............................................. 1-8
MOS Memory Cross-Reference .............................................................................................1-9
CHAPTER 2 -
MOS
Dynamic RAMs
MCM4027A
MCM4116B
MCM4117
MCM4132
MCM4616
MCM4617
MCM6632
MCM6633
MCM6664
MCM6665
MCM6665L25
4K x 1 ..................................................................................2-3
16Kx1 ............................................................................... 2-13
16K x 1 ............................................................................... 2-20
32Kx 1 ...............................................................................2-27
16K x 1 ...............................................................................2-32
16K x 1 ............................................................................... 2-36
32K x 1 ............................................................................... 2-42
32K x 1 ...............................................................................2-50
64K x 1 ...............................................................................2-57
64K 1< 1 ...............................................................................2-65
64K x 1 ...............................................................................2-72
Static RAMs
MCM2114, 21 L14
1K x 4 .................................................................................2-79
MCM2115A, 21L15A, 2125A, 21L25A 1Kx 1.................................................................................2-84
MCM2115H, 2125H
1K x 1................................................................................. 2-90
MCM2147
4K x 1.................................................................................2-91
MCM2147H
4K x 1.................................................................................2-96
MCM2148
1K x 4 .................................................................................2-97
MCM2148H
1K x 4 ...............................................................................2-101
MCM2149
1K x 4 ...............................................................................2-102
MCM2167
16Kx1 .............................................................................. 2-103
MCM4016
2K x 8 ...............................................................................2-104
MCM6641, 66L41
4K x 1 ...............................................................................2-105
128x8 ..............................................................................2-109
MCM6810, 68A10, 68B10
EPROMs
MCM2532,25L32
MCM27OS, 27AOS
MCM2716,27L16
TMS2716, TMS27A16
MCM687OS, 68A708
MCM68732, 68L732
MCM68764, 68L764
MCM68766
4Kx8 ...............................................................................2-113
1Kx8 ...............................................................................2-119
2Kx8 ...............................................................................2-125
2K x8 ...............................................................................2-131
1Kx8 ...............................................................................2-137
4Kx8 ...............................................................................2-143
8Kx8 ...............................................................................2-14B
8Kx8 ............................................................................... 2-153
EEPROMs
MCM2801
MCM2816
16x 16 ..............................................................................2-158
2Kx8 ...............................................................................2-163
ROMs
MCM6870,6874
MCM66700, 710, 714, 72D, 730, 734,
740, 750, 751, 760, 770, 780, 790
MCM68A30A, 68B30A
MCM68A308, 68B308
MCM68A316A
MCM68A316E
128x (7x 5) ........................................................................2-164
128 x (7 x 9)... .....................................................................2-171
1K x 8 ...............................................................................2-185
1K x 8 ...............................................................................2-190
2K x 8 ...............................................................................2-195
2Kx8 ............................................................................... 2-199
iii
Table of Contents (Continued)
Organization
MCM68A332
MCM68A364, 688364
MCM68366
MCM68366
Page
4KxS ...............................................................................2-203
SKxS ...............................................................................2-207
SK xS ...............................................................................2-212
SKxS ...............................................................................2-217
CHAPTER 3 - CMOS Memories
Static RAMs
MCM14605
MCM14637
MCM14652
MCM5101,51L01
MCM6508, 6518
MCM65114
MCM65116
MCM66147
MCM65148
64x 1...................................................................................3-3
256 x 1................................................................................3-12
64x4 .................................................................................3-20
256x4 ................................................................................3-27
lKx 1.................................................................................3-31
1Kx4.................................................................................3-35
2KxS .................................................................................3-36
4Kx 1.................................................................................3-37
lKx4 .................................................................................3-38
ROMs
MCM14524
MCM65516
256x4 ................................................................................3-39
2KxS .................................................................................3-45
CHAPTER 4 - Bipolar Memories
TTL RAMs
MCM93415
MCM93425
1024x1 ............................................................................... .4-3
1024 x 1................................................................................4-7
TTL PROMs
MCM7680, 7681
MCM7684, 7685
1024xS .............................................................................. 4-11
2K x 4 .................................................................................4-15
MECL Memories
General Information ..........................................................................................................4-19
MECL RAMs
MCM10143
MCM10144,
MCM10145,
MCM10146,
MCM10147,
MCM10148,
MCM10152,
10544
10545
10546
10547
10548
10552
Sx2 ................................................................................... 4-22
256 x 1................................................................................ 4-27
16x4 ................................................................................. 4-29
1024 x 1 ..............................................................................4-31
12Sx 1................................................................................4-33
64x 1 .................................................................................4-35
256 x 1................................................................................4-37
MECL PROMs
MCM10139, 10539
MCM10149, 10549
32xS .................................................................................4-39
256x4 ................................................................................4-43
CHAPTER 5 - Memory Subsystems
Board Level
MMS1102
MMS1122
MMS1132
MMS1117
MMS1119
MMS1128
MMS1170
MMS780
MMS8064
LSI-ll Compatible Add-In Memory (32K x lS) ............................... 5-3
LSI-11 , LSI-ll/23 Compo Add-In Memory (32K x 16) ....................... 5-5
LSI-11 , LSI-11/23 Compo Add-In Memory (l28K x 16) ..................... 5-7
PDP-ll Compatible (HEX SPC) Add-In Memory (64K x lS) ............... 5-9
PDP-11 (Modified or Extended Unibus) Compo Memory (l28K x lS) .. 5-11
PDP-ll (Modified Unibus) Memory Compo (32K, 48K x lS) ............. 5-15
PDP-11170 Compatible Add-In Memory ...................................... 5-20
VAX-111780 Compatible Add-In Memory ....................................5-22
Intel Multibus Compatible Memory ............................................ 5-25
CHAPTER 6 - Mechanical Data .................................................................................6-1
iv
Alphanumeric Index
Device
Page
MCM10139 ................................................ .4-39
MCM10143 ................................................ .4-22
MCM10144 ................................................. 4-27
MCM10145 ................................................ .4-29
MCM10146 ................................................. 4-31
MCM10147 ................................................. 4-33
MCM10148 ................................................. 4-35
MCM10149 ................................................. 4-43
MCM10152 ................................................. 4-37
MCM10539 ................................................. 4-39
MCM10544 ................................................. 4-27
MCM10545 ..................................... , ........... 4-29
MCM10546 ................................................. 4-31
MCM10547 ................................................ .4-33
MCM10548 .................................................4-35
MCM10549 .................................................4-43
MCM10552 .................................................4-37
MCMl4505 .................................................. 3-3
MCMl4524 ................................................. 3-39
MCMl4537 ................................................. 3-12
MCM14552 ................................................. 3-20
MCM21 L14 ................................................. 2-79
MCM21 L15A ............................................... 2-84
MCM21 L25A ............................................... 2-84
MCM2114 .................................................. 2-79
MCM2115A ................................................ 2-84
MCM2115H ................................................ 2-90
MCM2125A ................................................ 2-84
MCM2125H ................................................ 2-90
MCM2147 .................................................. 2-91
MCM2147H ................................................ 2-96
MCM2148 .................................................. 2-97
MCM2148H ............................................... 2-101
MCM2149 ................................................. 2-102
MCM2167 ................................................. 2-103
MCM25L32 ............................................... 2-113
MCM2532 ................................................. 2-113
MCM27A08 ............................................... 2-119
MCM27L 16 ............................................... 2-125
MCM2708 ................................................. 2-119
MCM2716 ................................................. 2-125
MCM2801 ................................................. 2-158
MCM2816 ................................................. 2-163
MCM4016 ................................................. 2-104
MCM2047A .................................................. 2-3
MCM4116B ................................................ 2-13
MCM4117 .................................................. 2-20
MCM4132 .................................................. 2-27
MCM4516 .................................................. 2-32
MCM4517 .................................................. 2-36
MCM51L01 ................................................. 3-27
MCM5101 .................................................. 3-27
MCM6508 .................................................. 3-31
MCM65114 ................................................. 3-35
MCM65116 ................................................. 3-36
MCM65147 ................................................. 3-37
MCM65148 ................................................. 3-38
MCM6518 .................................................. 3-31
MCM65516 ................................................. 3-45
MCM66L41 ............................................... 2-105
Device
Page
MCM6632 .................................................. 2-42
MCM6633 .................................................. 2-50
MCM6641 ................................................. 2-105
MCM6664 .................................................. 2-57
MCM6665 .................................................. 2-65
MCM6665L25 .............................................. 2-72
MCM6670 ................................................. 2-164
MCM66700 ............................................... 2-171
MCM66710 ............................................... 2-171
MCM66714 ............................................... 2-171
MCM66720 ............................................... 2-171
MCM66730 ............................................... 2-171
MCM66734 ............................................... 2-171
MCM6674 ................................................. 2-164
MCM66740 ............................................... 2-171
MCM66750 ............................................... 2-171
MCM66751 ............................................... 2-171
MCM66760 ............................................... 2-171
MCM66nO ............................................... 2-171
MCM66780 ............................................... 2-171
MCM66790 ............................................... 2-171
MCM68A10 ............................................... 2-109
MCM68A30A ............................................. 2-185
MCM68A308 ............................................. 2-190
MCM68A316A ........................................... 2-195
MCM68A316E ............................................ 2-199
MCM68A332 ............................................. 2-203
MCM68A364 ............................................. 2-207
MCM68A708 ............................................. 2-137
MCM68B10 ............................................... 2-109
MCM68B30A ............................................. 2-185
MCM68B308 ............................................. 2-190
MCM68B364 ............................................. 2-207
MCM68L732 .............................................. 2-143
MCM68L764 .............................................. 2-148
MCM6810 ................................................. 2-109
MCM68365 ............................................... 2-212
MCM68366 ............................................... 2-217
MCM68708 ............................................... 2-137
MCM68732 ............................................... 2-143
MCM68764 ............................................... 2-148
MCM68766 ............................................... 2-153
MCM7680 .................................................. 4-11
MCM7681 .................................................. 4-11
MCM7684 .................................................. 4-15
MCM7685 ..................................................4-15
MCM93415 ..................................................4-3
MCM93425 ................................................. .4-7
MMS1102 ....................................................5-3
MMS1117 .........•.......................................... 5-9
MMS1119 .................................................. 5-11
MMS1122 ....................................................5-5
MMS1128 .................................................. 5-15
MMS1132 ....................................................5-7
MMSl170 .................................................. 5-20
MMS780 ....................................................5-22
MMS8064 .................................................. 5-25
TMS27L16 ................................................ 2-131
TMS2716 .................................................. 2-131
v
SE~~~~:
CROSS-REFERENCE
1-1
l1li',:,
--t
MEMORIES SELECTION GUIDE
NOTES
Not all package options are listed.
Operating temperature ranges:
MOS - OOC to 70°C
CMOS - O°C to 70°C
ECl - Consult individual data sheets
TTL - Military - 55°C to + 125°C, Commercial O°C to 70°C
FOOTNOTES
1Motorola's innovative p}n#1 refresh
2AII MOS memory outputs are three-state except the open collector MCM2115A series.
3Character generators include shifted and unshifted characters, ASCII, alphanumeric
control, math, Japanese, British, German, European and French symbols.
*To be introduced.
1-2
MEMORIES SELECTION GUIDE (continued)
RAMs
MOS DYNAMIC RAMs
Part Number
Organization
Access Time
(ns max)
150
200
Power
Supplies
+12.±5V
+12.±5 V
+12. ±5V
No. of
Pins
16
16
16
16
16
16
16
16
16
16
16
16
16
4096 x 1
4096 x 1
4096 x 1
MCM4027AC-2
MCM4027AC-3
MCM4027AC-4
16384 x 1
16384 x 1
16384 x 1
163B4x 1
16384 x 1
16384 x 1
163B4x 1
16384 x 1
16384 x 1
16384 x 1
MCM4116BC15
MCM4116BC2O
MCM4116BC25
MCM4116BC30
MCM4516C12· 1
MCM4516C15· 1
MCM4516C2O· 1
MCM4517C12
MCM4517C15
MCM4517C2O
150
200
250
120
150
200
120
150
200
+12. ±5V
+12.±5V
+12. ±5V
+12. ±5V
+5V
+5V
+5V
+5V
+5V
+5V
3276Bx 1
3276Bx 1
3276Bx 1
3276Bx 1
3276Bx 1
3276Bx 1
3276Bx 1
3276Bx 1
3276Bx 1
3276Bx 1
MCM4132L15
MCM4132L20
MCM4132L25
MCM4132L30
MCM6632L15'
MCM6632L201
MCM6632L251
MCM6B33L15
MCM6B33L20
MCM6B33L25
150
200
250
300
150
200
250
150
200
250
+12. ±5V
+12. ±5V
+12. ±5V
+12. ±5V
+5V
+5V
+5V
+5V
+5V
+5V
18
18
18
18
16
16
16
16
16
16
65536 x 1
65536x 1
65636x 1
65536 x 1
65536 x 1
65636 x 1
MCM6664L151
MCM6664L201
MCM6664L251
MCM6665L15
MCM6665L20
MCM6665L25
150
200
+5V
+5V
+5V
+5V
+5V
+5V
16
16
16
16
16
16
250
3X)
250
150
200
250
TTL BIPOLAR RAMs
256 x 4
256 x 4
MCM93412
MCM93422
Access TIm8
(ns max)
45
45
1024 x 1
1024 x 1
MCM93415
MCM93425
45
45
Organization
Part Number
See Notes on Page 1-2.
1-3
Output
No. of
Open Collector
3-State
Pins
22
22
Open Collector
3-State
16
16
•
MEMORIES SELECTION GUIDE (continued)
MOS STATIC RAMs ( + 5 Volts)
Organization
128x8
128x8
128x8
MCM6810
MCM68A10
MCM68B10
1024x4
1024 x 4
1024 x 4
1024x4
1024x4
1024 x 4
1024 x 4
1024 x 4
MCM2114P20
MCM2114P25
MCM2114P30
MCM2114P45
MCM21 l14P20
MCM21l14P25
1024 x
1024 x
1024 x
1024 x
1024 x
1024 x
1024 x
1024 x
1024 x
1024 x
No. of
Pins
24
24
24
Access lima
Ins max)
Part Number
450
360
250
200
MCM21l14P~
250
300
MCM21 l14P45
450
18
18
18
18
18
18
18
18
MCM2115AC452
MCM2115AC552
MCM2115AC702
MCM21L15AC451
MCM21 L15AC702
MCM2125AC45
MCM2125AC55
MCM2125AC70
MCM21L25AC45
MCM21L25AC70
45
55
70
45
70
45
55
70
45
70
16
16
16
16
16
16
16
16
16
16
4096 x 1
4096 x 1
4096 x 1
MCM2147C55
MCM2147C70
MCM2147C85
55
70
18
18
18
1024 x 4
1024x4
1024x4
1024x4
1024 x 4
1024 x 4
MCM2148C55·
MCM2148C70·
MCM2148C85·
MCM2149C55·
MCM2149C70·
MCM2149C85·
1
1
1
1
1
1
1
1
1
1
250
300
450
200
85
18
18
18
18
18
18
55
70
85
55
70
85
CMOS STATIC RAMs ( + 5 Volts)
Organization
256x4
256 x 4
256 x 4
256 x 4
1024 x
1024 x
1024 x
1024 x
1
1
1
1
Accass Time
Ins max)
650
800
Part Number
MCM5101P65
MCM5101P80
MCM51 lOl P45
MCM51 lOl P65
No. of
Pins
~.
22
22
22
450
650
MCM6508C~
300
MCM6508C46
460
MCM6518C~
300
MCM6518C46
460
16
16
18
18
ECl BIPOLAR RAMs
Organization
8x2
256x 1
16x4
1024 x 1
128x 1
256 x 1
256x4
Access lime
Ins max)
15
26
15
29
15
15
10
Part Number
MCM10143
MCM10144
MCM10145
MCM10146
MCM10147
MCM10152
MCM10422·
See notes on page 1-2
1-4
Output
ECloutput
ECloutput
ECloutput
ECloutput
ECloutput
ECloutput
ECloutput
No. of
Pins
24
16
16
16
16
16
24
..,
~
MEMORIES SELECTION GUIDE (continued)
,
EPROMs
MOS EPROMs
1.024x8
1024 x 8
1024 x 8
1024 x 8
MCM2708C
MCM27A08C
MCM68708C
MCM68A708C
Accass TIme
(ns max)
450
300
450
300
2048 x 8
2048 x 8
2048 x 8
2048 x 8
2048 x 8
2048 x 8
TMS2716C
TMS27A16C
MCM2716C
MCM2716C35
MCM27L16C
MCM27L16C35
450
300
450
350
450
350
+12. ±5V
+12.±5V
+5V
+5V
+5V
+5V
24
24
24
24
24
24
4096x8
4096 x 8
4096 x 8
4096 x 8
MCM2532C
MCM2532C35
MCM25L32C
MCM25L32C35
450
350
450
350
+5V
+5V
+5V
+5V
24
24
24
24
8192x8
8192x8
8192x8
8192x8
8192x8
MCM68764C
MCM68764C35
MCM68L764C
MCM68L764C35
MCM68766C35
450
350
450
350
350
+5V
+5V
+5V
+5V
+5V
24
24
24
24
24
Accass TIme
(ns max)
101'5
Power
Supplies
No. of
Pins
14
Organization
Part Number
Power
Supplies
+12.±5V
+12. ±5V
+12. ±5V
+12.±5V
No. of
Pins
24
24
24
24
EEPROM
MOS EEPROM
Organization
16x16
Part Number
MCM2801C·
See notes on page 1-2
1-5
+5V
MEMORIES SELECTION GUIDE (continued)
ROMs
MOS STATIC ROMs (+5 Volts)
Character Generators3
128x(7x5)
128x(7x5)
MCM6670P
MCM6674P
Access TIme
(ns maxI
350
350
128x(9x7)
128x(9x7)
128x(9x7)
128x (9x 7)
128x(9x7)
128x (9x 7)
128x(9x7)
128x(9x7)
128x (9x7)
128x (9x7)
128x(9x7)
128x (9x7)
MCM66700P
MCM66710P
MCM66714P
MCM66720P
MCM66730P
MCM66734P
MCM66740P
MCM66750P
MCM66760P
MCM66770P
MCM66780P
MCM66790P
350
350
350
350
350
350
350
350
350
350
350
350
24
24
24
24
24
24
24
24
24
24
24
24
Access TIma
(ns maxI
No. of
Pins
24
24
24
Organization
Part Number
No. of
Pins
18
18
Binary ROMs (+ 5 Volts)
Organization
Part Number
1.024 x 8
1024 x 8
1024 x 8
MCM68A308P
MCM68A308P7
MCM68B308P
350
350
250
2048 x 8
2048 x 8
2048x8
MCM68A316AP
MCM68A316EP
MCM68A316P91
350
350
350
24
24
24
4096 x 8
4096 x 8
MCM68A332P
MCM68A332P2
350
350
24
24
8192x 8
8192x8
8192x8
8192x8
8192x8
8192x8
8192x8
8192x8
MCM68A364P
MCM68A364P3
MCM68B364P
MCM68365P25
MCM68365P36
MCM68366P25
MCM68366P36
MCM68766C45
350
350
250
250
350
250
350
24
24
24
24
24
24
24
24
450
CMOS ROMs ( + 5 Volts)
Organization
256 x 4
2048 x 8
2048 x 8
Access TIme
(ns maxI
Part Number
MCMI4524
MCM65516C43
MCM65516C55
1200
430
550
See notes on page 1-2
1-6
No. of
Pins
16
18
18
MEMORIES SELECTION GUIDE (continued)
•
PROMs
Eel PROMs
Organization
32x8
256 x 4
Part Number
Accass TIme
(ns maxI
Output
No. of
Pins
25
30
ECloutput
ECloutput
16
16
Access Time
(ns maxI
Output
No. of
Pins
MCM10139
MCM10149
TTL PROMs
Organization
Part Number
64x8
64x8
MCM5003/5303
MCM5004/5304
125
125
Open Collector
2K Pull-Up
24
24
512x4
512x4
MCM7620
MCM7621
70
70
Open Collector
3-State
16
16
512x8
512x8
MCM7640
MCM7641
70
70
Open Collector
3-State
24
24
1024 x 4
1024 x 4
MCM7642
MCM7643
70
70
Open Collector
3-State
18
18
1024 x 8
1024 x 8
MCM7680
MCM7681
70
70
Open Collector
3-State
24
24
2048x4
2048x4
MCM7684*
MCM7685*
70
70
18
18
2048x4
MCM7686*
70
2048x4
MCM7687*
70
2048x4
MCM7688*
-
2048x4
MCM7689*
-
Open Collector
3-State
Open Collector
with latches
3-State
with latches
Open Collector
with Registers
3-State
with Registers
175
70
3-State
3-State
1Kx8
1Kx8
MCM76lS81*
MCM82708*
See notes on page 1-2
1-7
20
20
20
20
24
24
•
Memory Systems Board Selector Guide and Cross Reference
DEC
COMPUTERS
+lS111
LSI 11/02
LSI 11/23
PDP 11/03
(0 Bus Plus
slot)
I
co
MMSll02-31
8K x
16K x
32K x
64K x
128K x
6K x
16K x
32K x
64K x
128K x
16
18
18
18
18
18
MMS1132
+PDP 11/04
05, 10,34,
35,40,45,
50, 55, 60
(MUD8US
SPC slot)
16K x
32K x
48K x
64K x
16K x
32K x
48K x
64K x
16
16
16
16
18
18
18
18
MMS1117-x2
MMS1117-x4
MMS1117-x6
MMS1117-xS
MMSII17-x2PC
MMSI117-x4PC
MMSII17-x6PC
MMSII17-x8PC
+PDP-W04
PDP-11/34
PDP-W60
(Mudbus
slot)
16K
32K
48K
64K
96K
x 18
x 18
x 18
x 18
x 18
MMS1128Px016
MMS1128Px032
MMS1128Px048
"MMS1128Px064
tMMS1128Px096
+PDP-l1/04
32K
64K
96K
128K
256K
512K
x
x
x
x
x
MMS 1119P x 032
MMS1119Px064
MMS1119Px096
MMS1119px128
"MMS1119Px256
"MMS1119Px512
PDP-11/34
PDP-W60
(Mudbus
slot)
-"
MOrOROLA
PART NUMBER
MEMORY SIZE
+ PDP-11/70
16
16
16
MMS1122N3032
MMS1122N~
MMS1132
16
MMS1102-31PC
MMSll02-32PC
MMSI102-34PC
MONOLITHIC
SYSTEMS
PART NUMBER
DEC
PART NUMBER
INIEL
PART NUMBER
MOSTEK
PART NUMBER
MSV11-BG
MSV11-DC
MSVI1-DD
CM-5004-616
CM-5004-632
MK 8005-03
MK 8005-02
MK 8005-00
NS23P
MSC4601 16K x 16
MSC4601 32K x 16
MSV1HC
MSV1H8
MSV1HD
CM-5004-816
CM-5004-832
MK 8005-14
MK 8005-12
MK 8005-10
NS23P
MSC4604 16K x 18
MSC4604 32K x 18
MK 8001-02
MK 8001-01
NS11/34-16
NS11/34-32
NATIONAL
PART NUMBER
MMS1132
MMS1132
18
18
18
18
18
x 18
32K x 39
MK 8001-00
MK 8011-02,
MK 8011-01
CM-5034-832
CM-5034-848
CM-5034-864
MS1HA
MK 8011-00
NS11/34P-16
NS11/34P-32
MS1H8
MS11-LC
CM-5034-832
CM-5034-864
x 16
x 16
x 16
x 18
x 18
x 18
x 18
16K
32K
48K
128K
x 18
x 18
x 18
MK 8012-00
MSC3606
MSC3606
MSC3606
MSC3606
MK
MK
MK
MK
MSC3606
MSC3606
MSC3606
MSC3606
32K
64K
96K
128K
x 18
x 18
x 18
MK 8011-02
MK 8011-01
CM-5034-832
CM-5034-848
MS1HA
MS1HB
MS1HC
MS1HD
NS11/34P-16
NS11/34P-32
8012-03
8012-02
8012-01
8012-00
NSlli34Q
NS11/34Q
NS11134Q
PLESSEY
PART NUMBER
CDC
PART NUMBER
DR-115S
DR-115S
DR-115S
DR-113S
DR-113S
DR-115S
DR-115S
DR-115S
DR-113S
DR-113S
PM-SV32A1103
PM-SV32A/l02
PM-SV32A1100
941n16
94123-32
PM-S1164/102
PM-S1164/101
PM-S1164/100
94234-16
94234-32
PM-Sl1L1I00
PM-Sl1l1I00
PM-Slll1100
PM-Sl1l1I00
PM-Sl1L1I00
PM-Slll1100
OR-114S
DR-114S
DR-114S
94134-32
94134-64
+VAX 11/780
Memo SUBslot)
MYSTE~
I
32K x 72
MMS780AE1032
+ DEC, lSI-ll, PDP-H, and VAX-l1J780 are
trademarks of Digital EqUipment Corp.
PINCOMM is a registered trademark of Trendata
Standard Memories.
PS
PS
PS
PS
PINCOMM PS
+PINCOMM
70S
I
MS780-DA
(M8210)
MK 8016-01
I
I
NS 780
I
I
MSC 3610
DR-178S
I
I
t Populated with 32K RAMS
• Populated with 64K RAMS
x =3 for fast speed
x =4 for standard speed
P/PC- Parity + Controller elimmates the need for
DEC's 7850 controller.
+PINCOMM
PINCOMM
PINCOMM
PINCDMM
94134-128
MMS1170El064
I
PS
PS
PS
PS
PS
PS
PS
PS
+PINCOMM PS
(Add-In)
I
+ PINCOMM
PINCOMM
PINCOMM
PINCOMM
PINCOMM
PINCOMM
PINCOMM
PINCOMM
INTEL
MICROCOMPUTERS
MEMORY
SIZE
+iSBC 80/10,
B0/20,
86112
+ ~D~l11:v~~pment
INTEL
PAR)
NUMBER
SBC
SBC
SBC
SBC
016
032
048
064
System
SYSTEM 80
+ MULTI BUS and iSBC are trademarks of INTEL Corp.
BlC is a trademark of NATIONAL Semi-conductorCoro.
t Compatible with limitations
NATIONAL
PART
NUMBER
+ BlC 016
BLC 032
BLC 048
BLC 064
CHRISLIN
PART
NUMBER
CI8080
CI8080
CI 8080
-
"
I
DR-114S
x 18
94234-16
94234-32
PM-S1164A/102
PM-S1164A/101
PM-SI164A11OO
DR-114S
DR-114S
DR-114S
DR-114S
DR-114S
x 18
STANDARD
MEMORIES
PART NUMBER
PM-SV32AP/l03
PM-SV32AP/l02
PM-SV32AP/ 100
DR-114S
DR-114S
DR-114S
DR-114S
OR-114S
DR-114S
DR-114S
DR-114S
MSC3503 16K x 16
MSC3503 32K
MSC3503 48K
MSC3503 64K
MSC3605 16K
MSC3605 32K
MSC3605 48K
MSC3605 64K
OATARAM
PART NUMBER
I
I
+PINCDMM
780S
I
~
j
I
NOTE THIS DOCUMENT IS INTENDED ASAN AID
TO OUR CUSTOMERS IN SELECTING THE
PROPER A~O-IN MEMORY BOARD. WE
RECOMMEND THATTHE DATA SHEET &
TECHNICAL MANUALS FOR THE
PARTICULAR BOARD IN QUESTION BE
USED BEFORE INSTALLATION
THE OFFICIAL MOS MEMORY
CROSS·REFERENCE
From Motorola
NOVEMBER 1980
Part Number
AMD
Am270B
Am2716
Am4D44
Am9016
Am9114
Am91L14
Am9147
Am920BB
Am9217
Am9218
Am9232
AMI
S2114
S2114L
S2147
S4264
S5101
S6508
S8518
S6810
S6830
S6831A
S6831B
S68332
Organization
Descrtptlon
1024x8 EPROM
2048 x 8 EPROM
4096 x 1 SRAM
16,384 x 1 DRAM
1024x4SRAM
1024x4SRAM
4096 x 1 SRAM
1024x8SROM
2048x8SROM
2048x8 SROM
4096x8SROM
1024x4 SRAM
1024x4SRAM
4096 x 1 SRAM
8192x8 SROM
256x4 SRAM
1024 x 1 SRAM
1024 x 1 SRAM
128x8SRAM
1024x8SROM
2048x8SROM
2048x8SROM
4096x8 ROM
Motorola's
Access Time
(ns Max)
Number 01
Pins
Po_
Supplies
Motorola Plnolo·Pln
Replacement
24
24
18
16
18
18
18
24
24
24
24
+12,±5V
+5V
+5V
+12,±5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
MCM270B
MCM2716
MCM88L41
MCM4116
MCM2114
MCM21L14
MCM2147
MCM88A308
MCM88A316A
MCM88A316E
MCM88A332
200-450
200-450
7()'loo
350
450-800
18
18
18
24
30().480
30().480
16
18
24
24
24
24
24
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
MCM2114
MCM21L14
MCM2147
MCM68A384
MCM5101
MCM6508
MCM6518
MCM6810
MCM68A30A
MCM68A316A
MCM68A316E
MCM88A332
16
18
24
24
24
24
24
16
24
24
24
+12, ±5V
+5V
+12, ±5V
+12, ±5V
+5V
+5V
+5V
+12, ±5V
+5V
+5V
+12,±5V
MCM4116
MCM2114
MCM270B
MCM27AOB
MCM2716
MCM68A308
MCM68A316E
MCM4027A
MCM68Bl0
MCM68B308
MCM6870B
+5V
+5V
+5V
+5V
+12,±5V
+12,±5V
+5V
+12,±5V
MCM2147
MCM2716
MCM6641
MCM2114
MCM4116
MCM4027A
MCM68A308
MCM270B
+5V
+5V
+5V
+5V
MCM68A316A
MCM68A316E
MCM68A332
MCM68365-35
300-450
450
200-450
150-300
200·450
200·450
55-85
350
350
350
350
250-450
350
350
350
350
22
FAIRCHILD
F16K
2114
F270B
F270BI
2716
3508
F3516E
FM4027
F68Bl0
F88B308
F6870B
16,384 x 1 DRAM
1024x4 SRAM
1024x8 EPROM
1024x8 EPROM
2048 x 8 EPROM
1024x8 SROM
2048x8 SROM
4096 x 1 DRAM
128x8 SRAM
1024x8SROM
1024x8 EPROM
FUJITSU
MB2147
MBM2718
MB4044
MB8114
MB6116
MB8227
MB8308
MB8518H
4096xl SRAM
2048 x 8 EPROM
4096 x 1 SRAM
1024x4 SRAM
16,384 x 1 DRAM
4096 x 1 DRAM
1024x8SROM
1024x8 EPROM
350
450
18
24
18
18
16
16
24
24
2048 x
2048 x
4096 x
6092 x
350
350
350
350
24
24
24
24
...."" ......' 1
R03-l1316B
R03·9316B
R03-9332C
R03·9364B
8
8
8
8
SROM
SROM
SROM
SROM
150-300
200-450
450
300
450
350
350
120·250
250-450
250-350
450
7()'loo
450
200-450
200-450
150-300
120·250
1-9
Part Number
Organization
o.lcrlptlon
Motorola's
Acce •• Time
(ns Max)
Number 01
Pins
Power
Supplies
Motorola Pln·to·Pln
Replacement
HARRIS
6501
6508
6514
6518
256x4 SRAM
1024 x 1 SRAM
1024x 1 SRAM
1024 x 1 SRAM
450·600
300·460
200·450
300·460
22
16
18
18
+5V
+5V
+5V
+5V
MCM5101
MCM6508
MCM65114
MCM6518
HITACHI
HM4334P
HM435101
HM462316EP
HM462532
HM462708
HM462716
HM46332
HM46364
HM468A10
HM46830
HM4716
HM472114A
HM48016
HM4816
HM4847
HM4864
HM6116P
HM6147P
HM6148P
1024 x4 SRAM
256 x 4 CMOS SRAM
2048x8 SROM
4096 x 8 EPROM
1024 x 8 EPROM
2048x8
4096x8 SROM
8192x8 SROM
128x8 SRAM
1024x8 SROM
16,384 x 1 DRAM
1024 x 1 SRAM
2048 x 8 EEPROM
16,384 x 1 DRAM
4096 x 1 SRAM
65,536 x 1 DRAM
2048 x 8 CMOS SRAM
4096 x 1 CMOS SRAM
1024x4 CMOS SRAM
300·450
450·800
350
450
450
450
350
350
350
350
150·300
200·450
350
100·200
55·85
150·200
120·200
55·70
55·85
18
22
24
24
24
24
24
24
24
24
16
18
24
16
18
16
18
18
18
+5V
+5V
+5 V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+12,±5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
MCM65114
MCM5101
MCM68A316E
MCM2532
MCM2708
MCM2'716
MCM68A332
MCM68A364
MCM68A10
MCM68A30A
MCM4116
MCM2114
MCM2816
MCM4517
MCM2147
MCM6665
MCM65116
MCM65147
MCM65148
INTEL
2114
2114L
2115A
2115AL
2115H
2117
2118
2125A
2125AL
2125H
2147
2147H
2148
2148H
2149H
2308
2316A
2316E
2332
2708
2708·1
2716
2716·1
2816
1024x4 SRAM
1024 x4 SRAM
1024x 1 SRAM
1024 x 1 SRAM
1024x 1 SRAM
16,384 x 1 DRAM
16,384 x 1 DRAM
1024x 1 SRAM
1024 x 1 SRAM
1024 x 1 SRAM
4096 x 1 SRAM
4096 x 1 SRAM
1024 x4 SRAM
1024x4 SRAM
1024x4 SRAM
1024x8 SROM
2048x8 SROM
2048x8 SROM
4096x8 SROM
1024 x 8 EPROM
1024 x 8 EPROM
2048 x 8 EPROM
2048x8 EPROM
2048 x 8 EEPROM
200·450
200·450
45·70
45·70
20·35
150·300
100·200
45·70
45·70
20·35
55·100
35·55
70·85
45·55
45·55
350
350
350
350
450
350
450
350
350
18
18
16
16
16
16
16
16
16
16
18
18
18
18
18
24
24
24
24'
24
24
24
24
24
+5V
+5V
+5V
+5V
+5V
+12, ±5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+12, ±5V
+12, ±5V
+5V
+5V
+5V
MCM2114
MCM21L14
MCM2115A
MCM21L15A
MCM2115H
MCM4116
MCM4517
MCM2125A
MCM21L25A
MCM2125H
MCM2147
MCM2147H
MCM2148
MCM2148H
MCM2149H
MCM68A308
MCM68A316A
MCM68A316E
MCM68A332
MCM2708
MCM27A08
MCM2716
MCM27A16
MCM2816
INTERSIL
2114 (IM2114)
IM2147
MK4027
IM650S
IM6518
IM7027
IM2114L
IM4116
IM7141
IM7141L
1024x4 SRAM
4096 x 1 SRAM
4096 x 1 DRAM
1024 x 1 SRAM
1024x 1 SRAM
4096 x 1 DRAM
1024x4 SRAM
16,384 x 1 DRAM
4096 x 1 SRAM
4096 x 1 SRAM
200·450
55·85
150·250
300·460
300·460
120·250
200·450
150·300
200·450
200·450
18
18
16
16
18
6
18
16
18
18
+5V
+5V
+12,±5V
+5V
+5V
+12, ±5V
+5V
+12, ±5V
+5V
+5V
MCM2114
MCM2147
MCM4027A
MCM6508
MCM6518
MCM4027A
MCM21L14
MCM4116
MCM6641
MCM66L41
ITT
ITT4027
ITT4116
4096 x 1 DRAM
16,384 x 1 DRAM
120·250
150·300
16
16
+12, ±5V
+12, ±5V
MCM4027A
MCM4116
1-10
PlrtNumber
Orglnlzltlon
Dncrlptlon
Motoroll'.
AccIs. Time
(n. Mex)
Number of
Pin.
Power
Supplle.
Motorole Pln·to·Pln
R.plecemenl
MIC
MIC2316E
MIC2332
2048x8 SROM
4096x8 SROM
350
350
24
24
+5V
+5V
MCM68A316E
MCM68A332
MOSTEK
MK2147
MK2716
MK4027
MK4116
MK4516
MK4164
MK30000
MK31000
MK32000
MK34000
MK36000
MK36000-4
4096 x 1 SRAM
2048 x 8 EPROM
4096 x 1 DRAM
16,364 x 1 DRAM
16,364 x 1 DRAM
65,536 x 1 DRAM
1024x8 SROM
2048x6SROM
4096x8SROM
2048x8 SROM
8192x8SROM
8192x8SROM
70-100
450
150·250
150-300
120·200
150·250
350
350
350
350
350
250
18
24
16
16
16
16
24
24
24
24
24
24
+5V
+5V
+12, :t5 V
+12, :t5 V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
MCM2147
MCM2716
MCM4027A
MCM4116
MCM4516
MCM6864
MCM68A308
MCM68A316A
MCM68A332
MCM68A316E
MCM68A364
MCM68B364
NATIONAL
MM2114
MM2147
MM2708
MM2716
MM5235
MM5257
MM5257L
MM5290
1024x4 SRAM
4096 x 1 SRAM
1024 x 8 EPROM
2048 x 8 EPROM
8192x8 SROM
4096 x 1 SRAM
4096 x 1 SRAM
16,364 x 1 DRAM
200·450
55-85
450
450
350
200-450
200-450
150·300
18
18
24
24
24
18
18
16
+5V
+5V
+12, :t5V
+5V
+5V
+5V
+5V
+12, :t5 V
MCM2114
MCM2147
MCM2708
MCM2716
MCM68A364
MCM6841
MCM68L41
MCM4116
4096 x 1 DRAM
16,364 x 1 DRAM
1024x4 SRAM
4096 x 1 SRAM
4096x8 ROM
2048 x 8 EPROM
4096 x 1 SRAM
256x4 SRAM
1024x1 SRAM
1024x4SRAM
1024x8SROM
150·250
150·300
200-450
55-85
350
450
200-450
450-800
300-460
200·450
350
16
16
18
18
24
24
18
16
18
24
+12, :t5 V
+12, :t5 V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
MCM4027A
MCM4116A
MCM21L14
MCM2147
MCM68A332
MCM2716
MCM66L41
MCM5101
MCM6508
MCM2114
MCM68A308
2048x8SROM
350
24
+5V
MCM68A316A
2048x8SROM
1024x8 EPROM
2048 x 8 EPROM
4096x8SROM
350
450
450
350
24
24
24
24
+5V
+12, :t5 V
+5V
+5V
MCM68A316E
MCM2708
MCM2716
MCM68A332
128x(7x9) SROM
128x(7x9) SROM
128x(1x9) SROM
128x(1x9) SROM
128x(7x9) SROM
128x(7x9) SROM
350
350
350
350
350
350
24
24
24
24
24
24
+5V
+5V
+5V
+5V
+5V
+5V
MCM66700
MCM66710
MCM66720
MCM68730
MCM66740
MCM66750
1024x8SROM
1024x8SROM
128x(7x9) SROM
4096 x 1 DRAM
1024x4SRAM
2048x8SROM
4096x8SROM
8192x8 SROM
16,364 x 1 DRAM
1024 x 8 EPROM
2048 x 8 EPROM
4096 x 1 DRAM
256x4 SRAM
350
350
350
120-250
200-450
350
350
350
250-350
450
450
150-250
24
24
24
16
18
24
24
24
16
24
24
18
22
+5V
+5V
+5V
+12,
+5V
+5V
+5V
+5V
+12,
+12,
+5V
+12,
+5V
MCM68A308
MCM68A30A
MCM66700
MCM4027A
MCM21L14
MCM68A316E
MCM68A332
MCM68A364
MCM4116
MCM2708
MCM2716
MCM4027A
MCM5101
NECIEA
~PD414A
~PD416
~PD2114L
~PD2147
~PD2332
~PD2716
~PD4104
~PD5101
~PD6508
EA2114
EA2308J8308
~PD or
EA2316A18316A
~PD or
EA2316E18316E
EA2708
~PD or EA2716
EA8332
NITRON
NC6570
NC8571
NC6572
NC6573
NC6574
NC6575
SIGNETICS
2607
2608
2608
2860
2614
2616
2633
2684
2890
2708
2716
4027
5101
450-800
1-11
22
:t5V
:t5V
:t5V
:t5V
•
Organization
Oaecrlptlon
Part Number
Motorola's
Access Time
(ns Max)
SYNERTEK
SY2114
SY2147
SY2318A
SY2316B
SY2332
SY2716
SY5101
1024x4SRAM
4096 x 1 SRAM
2048x8SROM
2048x8SROM
4096x8 ROM
2048 x 8 EPROM
256x4SRAM
TEXAS INSTRUMENTS
TMS2114
TMS2147
TMS2516
TMS2532
TMS2708
TMS2716
TMS4016
TMS4044
TMS4116
TMS4164
TMS4732
TMS4764
1024x4SRAM
4096 x 1 SRAM
2048 x 8 EPROM
4096x8 EPROM
1024 x 8 EPROM
2048 x 8 EPROM
2048x8 SRAM
4096 x 1 SRAM
16,364 x 1 DRAM
65,536 x 1 DRAM
4096x8 SROM
8192x8 SROM
200-450
55-85
450
350-450
450
450
200
TOSHIBA
TMM314
TMM2147
TC5516P
1024x4 SRAM
4096 x 1 SRAM
2048x8 SRAM
200-450
55-85
I
200-450
55-85
350
350
350
450
450-800
200-450
150-300
150-250
350
350
200
Numberol
Pins
Po_
Suppll..
Motorola Pin-to-Pin
Replacament
18
18
24
24
24
24
22
+5V
+5V
+5V
+5V
+5V
+5V
+5V
MCM21L14
MCM2147
MCM68A316A
MCM68A316E
MCM68A332
MCM2716
MCM5101
18
18
24
24
24
24
24
18
16
16
24
24
+5V
+5V
+5V
+5V
+12, :1:5 V
+12, :1:5 V
+5V
+5V
+12, :1:5 V
+5V
+5V
+5V
MCM2114
MCM2147
MCM2716
MCM2532
MCM2708
TMS2716
MCM4016
MCM8641
MCM4116
MCM6685
MCM68A332
MCM68365
18
18
24
+5V
+5V
+5V
MCM2114
MCM2147
MCM4016
Part Number Guide _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Directly 6800
.~~
.oooo,~ _7.'-~M
;CM?4
MCM68A30A
e\
Motorola'MOS
Memory Prefix
Low Power
Version
7'_'00
Package Type
P = Plastic
L = Side Braze
C = Cerdlp Frit-Seal Ceramic
1-12
...l~ ~~."_
Memory Prefix
No Letter = :.: 450 ns
A=:<350ns
B= ",250 ns
MOS Memories
RAM, EPROM, EEPROM, ROM
2-1
2-2
@ MOTOROLA
MCM4027A
MOS
4096-BIT DYNAMIC RANDOM ACCESS MEMORY
(N·CHANNEL, SILICON·GATE)
The MCM4027A is a 4096 x 1 bit high-speed dynamic Random
Access Memory. It has smaller die size than the MCM4027 providing improved speed selections. The MCM4027 A is fabricated
using Motorola's highly reliable N-channel silicon·gate technology.
By multiplexing row and column address inputs, the MCM4027A
requires only six address lines and permits packaging in Motorola's
standard 16-pin dual-in-line packages. Complete address decoding is
done on chip with address latches incorporated.
All inputs are TTL compatible, and the output is 3-state TTL
compatible. The MCM4027A incorporates a one-transistor cell
design and dynamic storage techniques, with each of the 64 row
addresses requiring a refresh cycle every 2.0 milliseconds.
•
Maximum Access Time = 120
150
200
250
ns
ns
ns
ns
-
MCM4027AC1
MCM4027AC2
MCM4027AC3
MCM4027AC4
C SUFFIX
FRIT-SEAL CERAMIC PACKAGE
CASE 620-06
•
Maximum Read and Write Cycle Time =
320 ns - MCM4027AC1, C2
375 ns - MCM4027AC3, C4
•
Low Power Dissipation - 470 mW Max (Active)
27 mW Max (Standby)
•
3·State Output for OR·Ties
PIN ASSIGNMENT
V88
•
On-Chip Latches for Address, Chip Select, and Data In
•
Power Supply Pins on Package Corners for Optimum Layout
•
4096-BIT DYNAMIC
RANDOM ACCESS
MEMORY
•
Page·Mode Capability
Compatible with the Popular 21 04/MK4096/MCM6604
•
Second Source for MK4027
VSS
15 CAS
WE
!lAS
Industry Standard 16-Pin Package
•
['ii\-I16
Din
14 Dout
4
13
CS
AO
12
A3
A2
11
A4
A1
7
10~A5
Vool 8
91'V CC
Ref
Function
TRUTH TABLE
Data Out
Inputs
RAg
<:AS
CS"
L
L
L
L
L
L
L
L
H
L
H
H
H
WE
Cycle Power
Previous
Interim
Present
L
Valid data
High Imp.
Input data
Full-operating
Ves
Write cycle
H
Valid data
High Imp.
Valid data. (cell)
Full-operating
Ves
Read cycle
X
Valid data
High Imp.
High Imp.
Full-operating
Ves
Deselected-refresh
X
X
Valid data
Valid data
Valid data
Reduced operating
Ves
RAS only-refresh
L
X
X
Valid data
High Imp.
High Imp,
Standby
No
Standby-output disabled
H
X
X
Valid data
Valid data
Valid data
Standby
No
Standby-output valid
H = High, L = Low, X = Don't eare
OS9464R1111-78
2-3
•
MCM4027A
BLOCK DIAGRAM
WRITE----------~~~----------------------------------------------~
'-----,,----'
•
RAS Clocks
-pLI
1-____________-,
Address
Clocks
L
1--
CAS
Clocks
~
~
CAS--~-----------~.I----~-4--------~----------------------~
Enable
J
A5 ________~---J--~----~.r--~~
A4------------~
A3
A2
------------1
------------1
Al ------------~
AO------------~
Address
Buffers
(61
Rowand
Column
Data
Reset
Row
Decoder
----
Out
Dummy Cells
-L.
~
Memory Array
64 Sense Refresh Amplifiers
Data In/Out Gating
(1-of-641
Data Out
Buffer
--.I
~
~
,
1-of-2
Data 8us
Select
I Memory Array I
I
I
I Dummy Cells
I
Column Decoder
ij
~~__r-_(~1~-O~f~-3~2~1__y_~
'----_ _ _--------'t
t
'-=======~~
OPERATING CHARACTERISTICS
ADDRESSING
DATA OUTPUT
The MCM4027 A has six address inputs (AO-A5) and
two clock signals· designated Row Address Strobe (RAS)
and Column Address Strobe (CAS). At the beginning of
a memory cycle, the six low order address bits AO through
A5 are strobed into the chip with RAS to select one of
the 64 rows. The row address strobe also initiates the tim·
ing that will enable the 64 column sense amplifiers. After
a specified hold time, the row address is removed and the
.six high order address bits (A6-A 11) are placed on the
address pins. This address is then strobed into the chip
with CAS. Two of the 64 column sense amplifiers are
selected by A 1 through A5. A one of two data bus select
is accomplished by AO to complete the data selection.
The Chip Select (CS") is latched into the port along with
the column addresses.
In order to simplify the memory system designed and
reduce the total package count, the MCM4027 A contains
an input data latch and a buffered output data latch. The
state of the output latch and buffer at the end of a memo
ory cycle will depend on the type of memory cycle per·
formed and whether the chip is selected or unselected for
that memory cycle.
A chip will be unselected during a memory cycle if:
(1)
The chip receives both RAS and CAS signals,
but no Chip Select signal.
(2) The chip receives a CAS signal but no RAS
signal. With this condition, the chip will be
unselected regardless of the state of Chip
Select input.
If, during a read, write, or read·modify·write cycle,
2-4
MCM4027A
INPUT/OUTPUT LEVELS
the chip is unselected, the output buffer will be in the
high impedance state at the end of the memory cycle.
The output buffer will remain in the high impedance state
until the chip is selected for a memory cycle.
For a chip to be selected during a memory cycle, it
must receive the following signals: RAS, CAS, and Chip
Select. The state of the output latch and buffer of a
selected chip during the following type of memory cycles
would be:
(1)
All of the inputs to the MCM4027 A are TTL·compatible,
featuring high impedance and low capacitance (5 to 7 pF).
The three-state data output buffer is TTL-compatible and
has sufficient current sink capability (3.2 mAl to drive
two TTL loads. The output buffer also has a separate
VCC pin so that it can be powered from the same supply
as the logic being employed.
REFRESH
Read Cycle - On the negative edge of CAS,
the output buffer will unconditionally go to a
high impedance state. It will remain in this
state until access time. At this time, the output latch and buffer will assume the logic
state of the data read from the selected cell.
This output state will be maintained until the'
chip receives the next CAS signal.
(2)
Write Cycle - If the WE input is switched to a
logic 0 before the CAS transition, the output
latch and buffer will be switched to the state
of the data input at the end of the access time.
This logic state will be maintained until the
chip receives the next CAS signal.
(3)
Read-Modify-Write - Same as read cycle.
In order to maintain valid data, each of the 64 internal
rows of the MCM4027 A must be refreshed once every 2 ms.
Any cycle in which a RAS signal occurs accomplishes a
refresh operation. Any read, write, or read·modify·write
cycle will refresh an entire internally selected row. How·
ever, if a write or read·modify·write cycle is used to per·
form a refresh cycle the chip must be deselected to pre·
vent writing data into the selected cell. The memory can
also be refreshed by employing only the RAS cycle. This
refresh mode will not shorten the refresh cycle time; how·
ever, the system standby power can be reduced by approx·
imately 30%.
If the RAS only refresh cycles are employed for an ex·
tended length of time, the output buffer may eventually
lose data and assume the high impedance state. Applying
CAS to the chip will restore activity of the output buffer.
POWER DISSIPATION
DATA INPUT
Since the MCM4027A is a dynamic RAM, its power
drain will be extremely small during the time the chip is
unselected.
The power increases when the chip is selected and
most of this increase is encountered on the address
strobe edge. The circuitry of the MCM4027A is largely
dynamic so power is not drawn during the whole time
the strobe is active. Thus the dynamic power is a function
of the operating frequency rather than the active duty
cycle.
In a memory system, the CAS signal must be supplied
to all the memory chips to ensure that the outputs of
the unselected chips are switched to the high impedance
state. Those chips that do not receive a RAS signal will
not dissipate any power on the CAS edge except for that
required to turn off the chip outputs. Thus, in order to
ensure minimum system power, the RAS signal should be
decoded so that only the chips to be selected receive a
FfAS signal. If the RAS signal is decoded, then the chip
select input of all the chips can be set to a logic 0 state.
Data to be written into a selected storage cell of the
memory chip is first stored in the on-chip data latch.
The gating of this latch is performed with a combination
of the WE and CAS signals. The last of these signals to
make a negative transition will strobe the data into the
latch. If the WE input is switching to a logic 0 in the
beginning of a write cycle, the falling edge of CAS strobes
the data into the latch. The data setup and hold times
are then referenced to the negative edge of CAS.
If a read·modify·write cycle is being performed, the
WE input would not make its negative transistion until
after the CAS signal was enabled. Thus, the data would
not be strobed into the latch until the negative transistion
of WE. The data setup and hold times would now be ref·
erenced to the negative edge of the WE signal. The only
other timing constraints for a write·type·cycle is that both
the CAS and WE signals remain in the logic 0 state for a
sufficient time to accomplish the permanent storage of
the data into the selected cell.
Circuit diagrams external to or containing Motorola products are included as a means of illustration only. Complete information
sufficient for construction purposes may not be fully illustrated. Although the information herein has been carefully checked and is believed
to be reliable, Motorola assumes no responsibility for inaccuracies. Information herein does not convey to the purchaser any license under
the patent rights of Motorola or others.
The information contained herein is for guidance only, with no warranty of any type, expressed or implied. Motorola reserves the right
to make any changes to the information and the product(s) to which the information applies and to discontinue manufacture of the
product(s) at any time.
2-5
•
•
MCM4027A
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted.)
RECOMMENDED OPERATING CONDITIONS (Referenced to Vss
Parameter
= Ground)
Notes
Symbol
Min
Typ
Max
Unit
VOO
10.8
12.0
13.2
Vdc
2
VCC
5.0
3
0
VOO
0
Vdc
VSS
VSS
0
Vdc
2
VBB
-4.5
-5.0
-5.5
Vdc
2
Logic 1 Voltage, RAS, CAS, WRITE
VIHC
2.4
5.0
7.0
Vdc
"2,4
Logic 1 Voltage, all inputs except RAS, CAS, WRITE
VIH
2.2
5.0
7.0
Vdc
2,4
Logic 0 Voltage, all inputs
VIL
-1.0
0
0.8
Vdc
2,4
Supply Voltage
DC CHARACTERISTICS (VOO = 12 V ± 10% VCC = 5 0 V -+ 10% VBB = -5 0 V ±10%, VSS = 0 V, T A = 0 to 70 0 C.) Notes I, 5
Characteristic
Symbol
Average VOO Power Supply Current
Vee Power Supply Current
Average
Ves
Typ
Min
IDOl
Max
Units
Notes
35
rnA
6
mA
7
ICC
Power Supply Current
IBB
250
I'A
Standby VOO Power Supply Current
1002
2
mA
9
Average VOO Power Supply CUrrent during
1003
25
mA
6
Input Leakage Current (any input)
II!U
10
I'A
8
Output Leakage Current
10(U
10
I'A
9,10
"RAS only" cycles
Output Logic 1 Voltage @ lout - -5 mA
Output Logic 0 Voltage @ lout
VOH
= 3.2 mA
Vdc
2.4
Vdc
0.4
VOL
NOTES 1 through 11:
1. T A is specified for operation at frequencies to tRC 'P tAc(minL
Operation at higher cycle rates with reduced ambient temperatures
and higher power dissipation is permissible provided that all ac
parameters are met.
6. Current. is proportional to cycle rate. 1001 (max) is measured
at the cycle rate specified by tRc(minl.
7. ICC depends on output loading. During readout of high level
data Vee is connected through a low impedance (135 n typ) to
Data Out. At all other times ICC consists of leakage currents only.
2. All voltages referenced to VSS.
3. Output voltage will swing from VSS to VCC when enabled,
with no output load. For purposes of maintaining data in standby
mode, Vce may be reduced to VSS without affecting refresh
operations or data retention. However, the VOH(min) specification is not guaranteed in this mode.
8. All device pins at 0 volts except VSS which is at -5 volts and
the pin under test which is at +10 volts.
9. Output is disabled (high-impedance) and RAS and CAS are
both at a logic 1. Transient stabilization is required prior to
measurement of this parameter.
4. Device speed is not guaranteed at input voltages greater than
10.0 V" VO ut " +10 V.
11. EffeCtive capacitance is calculated from the equation:
TTL levels (0 to 5 vI.
5. Several cycles are required after power-up before proper
device operation is achieved. Any 8 cycles which perform refresh
are adequate for this purpose.
C ""
~e with 1:J.V =
3 volts.
EFFECTIVE CAPACITANCE (Full operating voltage and temperature range, periodically sampled rather than 100% testedl Note 11
Characteristic
Input. Capacitance
(AO-A5I, Din, CS
Symbol
Max
Unit
Cin(EFF)
5.0
pF
RAS, CAS, WRITE
10.0
Output Capacitance
Cout(EFFl
7.0
pF
ABSOLUTE MAXIMUM RATINGS (See Notes 1 and 2)
Rating
Symbol
Value
Unit
vin, Vout
-0.5 to +20
Vdc
Operating Temperature Range
TA
o to +70
Storage Temperature Range
Output Current (Short Circuit)
Tstg
-65 to +150
°c
°c
lout
50
mAdc
Voltage on Any Pin Relative to vSS*
• (Vss·- V ••
> 4.5 V)
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS
ARE EXCEEDED. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages
for extended periods of time eQuid affect device .reliability. Ves must be applied
prior to Vec and VDD. Vas must also be the last power supply switched off.
2-6
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised that
normal precautions be taken to avoid applieation of any voltage higher than maximum rated
voltages to this high impedance circuit.
MCM4027A
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Read, Write, and Read-Modify-Write Cycles)
RECOMMENDED AC OPERATING CONDITIONS
(Voo = 12 V '10%, VCC = 5.0 V' 10%,
TA
Peramater
Symbol
Random Read or Write Cycle Time
Read Write Cycle Time
Paae Mode Cvcle Time
Access Time From Row Address Strobe
Access Time From Column Address SHObe
OU!Q!JI Buffer and Turn-Off Delay
Row Address Strobe Precharg8 Time
Row Address Strobe Pulse Width
Row Address Strobe Hold Time
Column Address Strobe Pulse Width
Column Address Strobe Hold Time
Row to Column Strobe Lead Time
Row Address Setup Time
Row Address Hold Time
Column Address SetuD Time
Column Address Hold Time
Column Address Hold Time Referenced to RA5
ChiD Select SetuD TI me
ChiD Select Hold Time
Chip Select Hold Time Referenced to RA'S
Transition Time Rise and Fall
Read Command Setup Time
Read Command Hold Time
Write Command Hold Time
Write Command Hold Time Referenced to RA'S'
Write Command Pulse Width
Write Command to Row Strobe Lead Time
Write Command to Column Strobe Lead Time
Data in Setup Time
Data in Hold Time
Data in Hold Time Referenced to AAS
Column to Row Strobe Precharge Time
Column Precharge Time
Refresh Period
WrIte Command Setup Time
'RC
RWC
PC
'RAe
'CAe
OFF
'RP
'RAS
'RSH
'CAS
'CSH
'0
CAS
WRITE Delav
RAS
~ Delav
Data Out Hold Time
'0
MCM4027ACl
Min
M ••
320
320
160
35
'ASC
'eAH
·5
40
'AR
ICSC
80
0
40
'T
'RCS
'ACH
'wCH
'WCR
WP
'RWL
'CWL
'DS
'DH
'DHR
'CRP
'CP
'RFSH
'wcs
'CWD
'RWD
DOH
80
3
0
0
40
40
375
375
225
100
150
100
100
150
20
0
20
·10
45
10,000
50
95
·10
45
95
3
35
35
0
0
45
80
40
50
50
0
40
80
0
60
95
45
50
50
0
45
95
0
60
2
0
60
100
10
MCM4027AC3
Min
M ••
150
100
40
80
'ASR
'RAH
'CH
'CHR
MCM4027AC2
Min
Max
320
320
170
10.000
vss
-5.0 V· 10%, VSS - 0 V,
70 0 C.) Notes 1,5,12,18
120
100
120
80
80
120
15
0
15
tRCD
=0 to
200
135
50
120
200
135
135
200
25
0
25
·10
55
120
·10
55
120
3
0
0
55
120
55
70
70
0
55
120
0
80
2
0
60
110
10
MCM4027AC4
Min
Max
375
375
285
10.000
65
50
250
165
60
120
250
165
165
250
35
0
35
·10
75
160
·10
75
160
3
0
0
75
160
75
10.000
85
50
85
85
0
75
160
0
110
2
2
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
n!l
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Not ••
13
13
13
14,16
15,16
17
18
19
19
0
0
no
80
80
ns
20
145
10
175
10
ns
20
JIS
18.VIHc{min) or VIH{min) and VIL(max) are reference levels for
measuring timing of input signals. Also, transition times are
measured between VIHC or VIH and VIL'
19.These parameters are referenced to CAS leading edge in
random write cycles and to WRITE leading edge in delayed write
or read~modify write cycles.
NOTES 12 through 20:
12. AC measurements assume tT;: 5 ns.
13. The specifications for tRc(min) and tRwc(min) are used only
to indicate cycle time at which proper operation over the full
temperature range (OoC =0;; T A =0;; 70 0 C) is assured.
14.Assumes that tRCD .;;tRCO(max).
20. twCS. tewD, and tRWD are not restrictive operating para~
meters. They are included in the data sheet as electrical charac~
terisitcs only: If twcs ;ilo twcs(min), the cycle is an early write
cycle and Data Out will contain the data written into the selected
15. Assumes that tRCO ;;. tRCO (max).
16. Measured with a load circuit equivalent to 2 TTL loads and
l00pF.
17. Operation within the tRCO(max) limit insures that tRAc(max)
can be met. tRco(max) is specified as a reference point only; if
tRCO is greater than the specified tRco(max) limit, then access
time is controlled exclusively by tCAe.
cell. If tcwo ;;. tcwo(min) and tRWO ;;. tRWO(minl. the cycle is
a read·write cycle and Data Out will contain data read from the
selected cell. If neither of the above sets of conditions is satisfied,
the condition of Data Out (at access time) is indeterminate.
2-7
PI
MCM4027A
READ CYCLE TIMING
tRC-
tRAS
"I
tAR
RAS
CAS
j
V1HC
Jt
'RSH
VIL
'C~H
1--'CRP~
'CAS
f.-- t RCO- -
VIHC
tRP--
VIL
'-r~
tASR
ADDRESSES
VIH
VIL
~
~
Row
:r
'ASC
Address
.'CAHColumn
:X 'W
Address
tRCS+---,
WRITE
---<0
VIHC XX
VIL
'RC H
r----:..x
tCHR
'CS~
CS
!-'CH .....
VIH
~x
VIL
.x
'CAC --------to j.--tDDW--'OFF-'-1
°out
~
VOH
tRAe
2-8
VALID
DATA
i'=-
MCM4027A
WAITE CY CLE TIMING
tAC
VIHC---VIL
ADDRESSES
D
out
VOH
VOL
2-9
-
--
•
MCM4027A
READ-MODIFY-WRITE TIMING
•
'RWC
tRAS
'ARi
-----,
rL'RP_f\'CAS
i---'RCD
to--'CRP--<9S
>66
'CAC---tDO~
Oout
Vo H
Vo L
'OFF.±!
'\
.1
Op.n~
11
VALID
DATA
II
tRAC
RAS ONLY REFRESH TIMING
ADDRESSES
C aut
2-10
MCM4027A
PAGE MODE READ CYCLE
~------------------------tRAS------------------------~
•
DO ut
PAGE MODE WRITE CYCLE
~--------------------------tRAS------------------------~
RAS
VIHCVIL -
CAS
VIHCVIL -
----------
~--~~----~------------~'~I
VtH-
Addresses V I L-
cs
DOUT
Write
Din
VIH -
VIL -
VOH
VOL
VIHC-
VIL
-
VIHV 1L -
2-11
MCM4027A
Row Address
Column Address
•
AS A4 A3 A2 A 1 AD
A5 A4 AJ A2 A 1 AD
Column Addresses
A A A A A A
Rows
203E
2030
2020
202E
543210
2010
201E
200E
2000
H
H
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
L
L
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
L
L
L
H
H
H
H
H
H
la3E
1830 182E
1820
1alE
1810
lacE
1800
L
L
H
H
H
H
283E
2830
2820
281E
2810
2BOE
2800
H
H
L
L
H
H
L
L
L
L
L
L
L
L
2B2E
L
L
H
H
L
L
H
H
H
H
L
L
H
H
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
H
H
H
H
L
L
L
L
L
L
H
H
L
L
L
L
H
H
L
L
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
103E
1030 102E
1020 101E
1010
loaE
1000
L
L
303E
3030 302E
3020 301E
3010
30aE
3000
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L
L
L
L
L
H
H
H
L
L
H
083E
0830 082E
0820
3B3E
3830 382E
3820 3B1E
081 E
OS10 OBOE
0800
3aDE
3800
3810
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
0030 002E
0020
~OlE
0010 DODE
0000
<1:0 ...JI::t...J...JI::t...J...JII...J...JII...J ...JII...J...JJ::t...l...JJ::t...J..JJ:I...J ..JIl:..J-III...I...JII...J...JJ:I...J ...JII...J...JII...J...JII...J...JII...J
003E
L
L
H
H
L
L
H
L
L
H
H
H
H
L
L
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
L
L
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
L
L
L
L
H
H
L
L
H
H
H
H
L
L
H
H
L
L
H
H
H
H
L
L
~ tRWO (min), the cycle is a read·write cycle and the data out will contain data read from
the selected cell; If neither of the above sets of conditions is satisfied the condition of the data out (at access time) is indeterminate.
17. Assumes that tCRP > 50 ns.
2-15
•
MCM4116B
READ CYCLE TIMING
i o e - - - - - - - - - - - - - - - 'RC ----------------10.1
'RAS - - - - _ _ '
----------J
II
ioe-----------'AR
~------------------'CSH+_------------~~
'RCD---~~---~-'RSH------Ho.I
ioe----'---- 'CAS
---~~
ADDRESSES VIH
VIL
!..--'CAC
I--
'RAC--------eo.I
a (Data Out) VOH
tOFF
lr-----J
Valid
Oata
--------_________________ High Z
VOL
WRITE CYCLE TIMING
ioe---------------'RC
ioe-----------'RAS
ioe-----'AR
---------------~
~-~--'RSH ----~~
ioe---------+-~'CSH-------~
- - - ' - - - ' - - - - - 'CAS - - - - . !
ADDRESSES
VIH
VIL
'W~
VIH
VIL
WRITE
'WP
tWCR
o toata
In}
tCWL
~tWCH
I
'
I,
,RWL..1
j-. 'OS I-- 'DH
V'H
VIL
Valid
Data
tOHR
a (Data Out)
VOH
VOL
High Z
2-16
MCM4116B
READ-WRITE/READ-MODIFYWRITE CYCLE
_____ 'AWC __________
~------------..
~I----tRAS
~------'AA-------~-·
V,H
AAS
V,L
tRP
---------------~-
r'""~
'------f----------:_'C_SH_,C_AS_ _ _---+{---,,--':
V,H
CAS
V,L
V,H
ADDRESSES
V,L
~----------~--~I---'AWD---------------"
~I·'-------'CWD-----~
V,H
WRITE
V,L
Q
lData Outl
VOH
VOL
V,H
D lData Inl
V,L
RAS ONLY REFRESH TIMING
Not., CAS
= V'HC, WRITE = Don't Car.
ADDRESSES
VOH
Q
lData Outl
------------------High Z - - - - - - - - - - - - - - - - - - - -
2-17
•
•
MCM4116B
PAGE MODE READ CYCLE
Addresses
~IH
IL
Q
tDala Ouli
VOH
VOL
--------;~
PAGE MODE WRITE CYCLE
2-18
MCM4116B
MCM4116B BIT ADDRESS MAP
Row Address AS A5 A4 A3 A2 A 1 AO
Column Address A6 A5 A4 A3 A2 A 1 AO
Rows
Pin 8
D
Column Addresses
Hex
o
1
o
1
1
0
1
0
1
0
1
0
0
1
,.
,.
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
17
0
0
0
0
0
1F
30
31
0
0
0
0
1C
28
0
0
10
2.
0
0
1
1
0
1
1A
26
0
0
1
0
1
0
1B
27
0
1
18
2.
19
25
118
119
16
22
0
17
,.
23
0
20
0
15
21
12
18
10
11
1E
1 = potential well filled
with electrons
OE
~
§§§§§ ~ §§§
~ ~ ~ ~ ~
I
~
~
:ii'
;;:
~
~
~
'"
:g
0
is
~
~
~ ~ ~
is 0 !l 8 g :g :g
~
:g
~
'"
'"'"
0
0
.
~
;g
~
N
~
~
0
0
0
0
0
:!
~
:i!
Dpin16
2-19
A6 A5 A4 A3 A2 A1 AO
76
77
13
0'" potential well filled
with electrons
Dec
"
1
1
0
0
0
1
0
0
0
1
0
OF
15
OC
12
OD
13
0
0
0
1
OA
10
0
0
0
1
OB
11
1
0
0
1
1
0
0
1
1
0
0
0
0
0
1
08
0
0
0
0
0
09
0
0
0
0
0
06
0
0
07
0
0
0
0
0
1
04
0
0
0
0
1
0
05
0
0
0
0
1
0
02
0
0
0
0
0
0
0
03
0
0
0
00
0
0
0
0
01
0
0
0
0
0
1
0
0
1
•
•
®
MOTOROLA
MCM4117
16.384-BIT DYNAMIC RANDOM ACCESS MEMORY
The MCM4117 is a 16,384-bit, high-speed dynamic Random Access
Memory designed for high-performance, low-cost applications in mainframe and buffer inemories and peripheral storage. Organized as 16,384
one-bit words and fabricated using Motorola's highly reliable N-channel
double-polysilicon technology, this device optimizes speed, power, and
density tradeoffs.
By multiplexing row and column address inputs, the MCM4117 requires only seven address lines and permits packaging in Motorola's
standard la-pin dual in-line packages. This packaging technique allows
high system density and is compatible with widely available automated
test and insertion equipment. Complete address decoding is done on
chip with address latches incorporated.
All inputs are TTL compatible, and the output is 3-state TTL compatible. The data output of the MCM4117 is controlled by the column address strobe and remains valid from access time until the column address strobe returns to the high state. This output scheme allows higher
degrees of system design flexibility such as common inputloutput
operation and two dimensional memory selection by decoding both row
address and column address strobes.
The MCM4117 incorporates a one-transistor cell design and dynamic
storage techniques, with each of the 128 row addresses requiring a
refreSh cycle every 2 milliseconds.
• Flexible Timing With Read-Modify-Write, RAS-Only Refresh, and
Page-Mode Capability
• Industry Standard la-Pin Package
• 16,384x 1 Organization
• ± 10% Tolerance on All Power Supplies
• All Inputs are Fully TTL Compatible
• Three-State Fully TTL-Compatible Output
• Common 1/0 Capability When Using "Early Write" Mode
MOS
IN-CHANNEL)
16.384-BIT DYNAMIC
RANDOM ACCESS
MEMORY
~
L SUFFIX
CERAMIC PACKAGE
CASE 68(}{)6
PIN ASSIGNMENT
VBB
~~VSS
17~CAS"
D
IN 3
RAS" 4
m"
16PCAS""
15 ~O
5
14 ~A6
• On-Chip Latches for Addresses and Data In
• Low Power Dissipation - 463 mW Active, 20 mW Standby (Max)
AO 6
13 A3
A1
12 A4
• Fast Access
150 ns 200 ns 250 ns 300 ns -
A2
Time Options:
MCM4117L-15
MCM41l7L-20
MCM4117L-25
MCM4117L-30
• Easy Upgrade from la-Pin 4K RAMs
ABSOLUTE MAXIMUM RATINGS ISee Notel
Symbol
Value
Rating
Unit
Voltage on Any Pin Relative to VBB
Vdc
Vin, Vout -0.5 to +20
Oper.ting Temperature Range
to + 70
·C
TA
Storage Temperature Range
-66 to +150
·C
Tstg
Power Dissipation
1.0
W
PD
Data Out Current
50
mA
lout
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING
CONDITIONS. Exposure to higher than recommended volt.ges for extended periods
of time could affect device reliability.
o
8
11 A5
VDD ...9__--10... VCC
"Tie pins 4 and 5 together.
""Tie pins 16 and 17 together.
Consideration should be given in PC
board layout to allow easy upgrade to the
MCM4132.
~_
PIN NAMES.
AO-A6 .......................... Address Inputs
CAS ................ Column Address Strobe
D .......................................... D.ta In
O ..•..................................... Data Out
RAS ..................... Row Address Strobe
W............................ Read/Write Input
VBB ............................. Power 1-5VI
VCC·····························Powerl+5VI
VDD····························Powerl+12VI
VSS······································Ground
This device contains circuitry fa protect
the inputs ag.inst damage due to high
st.tic volt.ges or electric fields; however,
it is advised that normal precautions be
taken to avoid application of any voltage
higher than maximum rated voltages to
this high impedance circuit.
DS9836/11-80
2-20
MCM4117
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full Operating Voltage and Temperature Ranges Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Typ
Max
VOO
VCC
VSS
VBB
10.8
4.5
12.0
5.0
13.2
5.5
-4.5 -5.0 -5.5
VIH
2.4
VIL
-1.0
Supply Voltage
Logic 1 Voltage, All Inputs
Logic
a Voltage,
All Inputs
a
Unit Notes
V
1
1,2
1
1
-
7.0
V
1
-
0.8
V
1
a
a
•
"
"
- a V ± 10%
-
DC CHARACTERISTICS IVOO -12 V ± 10% VCC- 5
aV
-
VBB - - 5
± 10% VSS -
aV
a
T A - to 70CC)
Symbol Min Max
Characteristic
Average VOO Power Supply Current
1001
V CC Power Supply Current
-
35
ICC
Unit Notes
rnA
4
rnA
5
IBB1,3
-
200
Standby VBB Power Supply Current
IBB2
-
100
~A
Standby VOO Power Supply Current
1002
-
1.5
rnA
6
27
rnA
4
10
~A
Average VBB Power Supply Current
Average VOO Power Supply Current Ouring
"AAS" Only" Cycles
1003
~A
Input Leakage Current IAny Input)
IIiLi
Output Leakage Current
IOILi
-
10
~A
6,7
Output Logic 1 Voltage @ lout - - 5 rnA
VOH
2.4
-
V
2
a Vol.tage @
VOL
-
0.4
V
Output Logic
lout~4.2
NOTES:
1.
All voltages referenced to
rnA
vss. Vss
must be applied before and removed after other supply voltages.
Vee
2.
Output voltage will swing from VSS to
3.
may be reduced to VSS without affecting refresh operations. VOH(min) specification is not guaranteed in this mode.
Several cycles are required after power-up before proper device operation is achieved. Any a cycles which pelform refresh are adequate.
4.
5.
Current is proportional to cycle rate; maximum current is measured at the fastest cycle rate.
ICC depends upon output loading. The VCC supply is connected to the output buffer only.
CAS
under open circuit conditions. For purposes of maintaining data
6.
Output is disabled (open-circuit) when
7.
8.
0 V ~ V out ..;; + 5.5 V.
CapacItance, measured wlIh a Boonton meter or effective capacitance calculated from the equatIon: C'" tat/aV.
In
power down mode,
is at a logic 1.
BLOCK OIAGRAM
4-----
Write
Ctqcks
Clock
_, Generator
No.1
~
I
Multiplexed
Clock
Generator
~
T
A6
fG'
~
Clock
Generator
No.2
_1
A3
A2
Mux
Address
Input
Buffers
!
~
r-rv
Row
Decoder
1 :128
171
AO
-
I
:,
,
128
Row
Lines
!
A1
,
,
I
---'
~
Mux
Switch
----Vaa
Data In
~_
Out
Buffer
Dummy Cells
A5
A4
I
Data
Latch
Release
~
•
Data
In
Buffer
2-21
0
~
Memory Array
128 -'Sense - Refresh Amps
1·of·2
Data
~
~
Data
Memory
--
Alb
V OO
+_---vee
"'---VSS
Array
Dummy Cells
64·Colum-n
Select Lines
- --
Column Decoders
1·of·64
AO
In/Out
au,
Select
L-.
e-
Vee
•
MCM4117
AC OPERATING CONDITIONS AND CHARACTERISTICS
(See Notes 3, 9, 14)
(Read, Write, and Read-Modify-Write Cycles)
RECOMMENDED AC OPERATING CONDITIONS
(VDD=12V±10% VCC=50V±10% VBB=-50V±10% VSs=OV, TA=Ot070'C)
MCM4117-20
MCM4117-15
Symbol
Parameter
Min
Max
Min
Max
-
375
150
tCAC
-
Output Buffer and Turn-off Delay
tOFF
Row Address Strobe Pracharge Time
Random Read or Write Cycle Time
MCM4117-25
Min
Max
MCM4117-30
Min
Max
Unit Notes
410
-
4BO
-
375
-
515
-
660
-
ns
200
135
-
250
-
10,12
-
165
300
200
ns
100
-
ns
11,12
0
50
0
50
0
60
0
60
ns
17
tRP
100
-
120
-
150
-
160
-
ns
tRC
375
Read Write Cycle Time
tRWC
375
Access Time from Row Address Strobe
tRAC
Access Time from Column Address Strobe
ns
Row Address Strobe Pulse Width
tRAS
150
10,000
200
10,000
250
10,000
300
10,000
ns
Column Address Strobe Pulse Width
tCAS
100
10,000
135
10,000
165
10,000
200
10,000
ns
Row to Column Strobe Lead Time
tRCD
20
50
25
65
35
65
60
100
ns
Row Address Setup Time
tASR
0
-
0
-
0
-
0
-
ns
20
60
35
tRAH
tASC
Column Address Hold Time
tCAH
45
tAR
95
-
120
-
160
-
200
-
ns
tT
3.0
35
3.0
50
3.0
50
3.0
50
ns
tRCS
0
-
0
0
-
0
-
ns
Column Address Hold Time Referenced
to RAS
Transition Time (R ise and Fall)
25
ns
Row Address Hold Time
Column Address Setup Time
10
10
10
55
10
ns
100
75
13
ns
14
Read Command Hold Time
tRCH
0
0
0
-
0
-
ns
Write Command Hold Time
tWCH
45
-
-
55
-
75
-
100
-
ns
Write Command Hold Time Referenced
to R7iS
tWCR
95
-
120
-
160
-
200
-
ns
twp
45
-
55
75
-
100
-
ns
tRWL
60
-
80
-
100
-
180
60
-
80
-
100
-
180
-
ns
-
0
-
0
-
0
ns
15
55
-
75
-
100
-
ns
15
Read Command Setup Time
Write Command Pulse Width
Write Command to Row Strobe Lead Time
Write Command to Column Strobe
Lead Time
tCWL
Data in Setup Time
tDS
0
Data in Hold Time
tDH
Data in Hold Time Reierenced to ~
tDHR
45
95
-
120
Column to Row Strobe Precharge Time
tCRP
-20
-
-20
RAS Hold Time
tRSH
100
-
Refresh Period
tRFSH
-
lWCS
tc:wn
-20
WRi'f'E Command
Setup Time
CAS to WRITE Delay
rn to WRITE Delay
CAS Pracharge Time
!Page Mode Cycle Only)
Page Mode Cycle Time
!::AS
Hold time
200
-
ns
-20
200
-
ns
165
-
2.0
-
2.0
-
2.0
ms
-20
-
-20
125
16
210
-
280
-
ns
160
-
ns
16
-
80
-
100
-
100
-
ns
170
-
225
200
-
325
-
-
275
150
-20
135
2.0
-
-
-20
70
tRWD
120
-
tcp
60
tpc
tCSH
95
5.0 ns.
10. Assumes that tACO" tRCD (max).
11. AssumesthattACD;' tRCD (maxI.
250
180
300
ns
ns
ns
-
ns
Symbol
Typ
Max
Input Capacitance (AO-A5), 0
Cll·
4.0
5.0
pF
Input Capacitance
CI2
Co
8.0
10
pF
8
5.0
7.0
pF
8
Parameter
=
160
-
NOTES: (continued)
9. AC measurements assume tT
ns
rn, CAS, W
Output Capacitance 10)
Unit Notes
8
12. Measured with a load circuit equivalent to 2 TTL loads and 100 pF.
13. Operation within the tRCO (max) limit ensures that tRAC (max) can be met. tRCo (max) is specified as a reference point only; if tACO
is greater than the specified tRCO (max) limit, then access time is controlled exclusively by tCAC.
14. VIHc.(min) or VIH (min) and VIL (max) are reference levefs for measuring timing of input signals. Also. transistion times are measured
between VIHC or VIH and VIL.
15. These parameters are referenced to CAS leading edge in random write cycles and to WRITE·leading edge in delayed write or read-modifywrite cycles.
16. twCS. tewD and tRWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: If
twes ~ twes (min), the cycle is an early write. cycle and the data out pin will remain open circuit (high impedance) throughout the
entire cycle; If tewD ~ tewD (min) and tAWD ;> tRWD (min), the cycle is a read-write cycle and the data out will contain l:tata read from
the selected cell; If neither of the above sets of conditions is satisfied the condition of the data out (at ·access time) is indeterminate.
17. Assumes that teRP
> 50
ns,
2-22
MCM4117
READ CYCLE TIMING
~-----------------------tRC--------------------~
tRAS - - - -__
-----"\1 ~__- - - - - tAR
~----------tCSH~-------~
..-J~--~---tRSH-----~
ADDRESSES
tCAC
tRAC-----·------.
----------+--
1 _ _
Q (Data Out! VOH
_ _ _ _ _ _ _ _ _ _ _ _ _ _ High Z
vOL
WRITE CYCLE TIMING
~---------------------------tRC--------------------------------.
'------'------------- tRAS ----------------.
14------ tA R
V,H
V,L
CAS
ADDRESSES
V ,H
V,L
V,H
V,L
WRiTE
o IData
Q
Inl
lData Outl
VOH ___________________________________
VOL
2-23
High Z
•
II
MCM4117
READWRITE/READ-MDDIFYWRITE CYCLE
r - - - - - - - - - - - - - - - - - - 'RWC -----------------4~
r-------------~~---'RAS
--~
v,H
V,L
RAS
tCSH
V ,H
CAS
V,L
V,H
ADDRESSES
V,L
L
J
I~·~------'CWD-----~
V,L
V,H
I
VOH
a IData Out}
VOL
'CAC=3
High Z
• . . . . ".
o IOsta In}
m
'RAC
VIH
Valid
.
SOFF
"_ _ _-,.----..:D::.:;'::.a_ _ _ _ _ _ _~f-_
'OS
j ~~'DH
.
Valid
~ou
V,L
ONLY REFRESH TIMING
Not.: CAS· VIHC, WiiTfE· Don'tCo ..
.
..,~,,."~"~
,
~ A:;~"=-
ADDRESSES
a IData Oull
.
VOH
-------------------High Z - - - - - - - - - - - - - - - - - -
MCM4117
PAGE MODE READ CYCLE
r----------------.tRAS----------B---I
RAS
r===1:~~:::;---------i l - - - - tRSH
teAs
A(lcJresses
tRP
tCRP
V,H
V IL
I
o
I.
VOH
IData Out) VOL - - - - - - - . ; -
PAGE MODE WRITE CYCLE
RAS
CAS
Write
V,H
VIL·~~~~~~_~pL~~~~~--~~~~~ F~Lf~--tL~~~~~~
2-25
MCM4117
MCM4117
BIT ADDRESS MAP
Pin 8
Row Address A6 A5 A4 A3 A2 Al AD
D
Column Address A6 A5 A4 A3 A2 A 1 AD
•
Rows
"-
re
Column Addresses
Hox Doc
76
77
16
17
"15
12
13
o = potential well filled
1 '" potential well filled
with electrons
with electrons
~
"-
(; !! 8 ~ 0~ :g E; :g
(; (; (; (; (; (; (; (; (;
"-
§ §§g §~ ~ §
~
g
0
0
~
8
(;
!! 8
~
¥
0
~
0
:g E; :g
~
0
"M
..
0
"-
l3
;1;
N
~
~
0
0(
J
~
a:
:;;
~
0
000
M
0(
0
0
0
o
0
::!
..
.~
0(
Dp;nl6
2-26
118
II.
1
0
1
I
0
1
22
0
0
0
1
23
0
0
20
0
0
21
0
18
I.
I
0
I
1
0
1
0
0
I
0
I
0
0
0
1
0
0
1
0
1
0
0
0
0
0
10
16
0
0
0
0
0
0
11
IE
17
0
0
0
0
0
0
0
1
1
1
IF
30
31
0
0
lC
28
0
0
1
10
2.
0
0
1
0
0
lA
26
18
27
0
0
18
I.
2'
2B
0
0
0
OE
8
8
A6 A5 A4 A3 A2 Al AO
I.
0
1
1
0
1
0
1
0
1
0
1
1
1
0
0
0
0
1
0
0
0
0
1
0
0
0
1
12
0
0
I
0
13
0
0
1
0
10
0
0
0
11
0
0
0
0
0
0
0
0
1
1
1
0
OF
lB
OC
OD
OA
08
08
0
0
09
0
0
0
06
0
0
0
0
07
0
0
0
0
O.
0
0
0
OS
0
0
02
0
0
0
0
0
1
0
1
1
03
0
0
0
0
0
1
00
0
0
0
0
0
0
0
01
0
0
0
0
0
0
1
®
MOTOROLA
MCM4132
32,768 x 1 BIT DYNAMIC RAM
MOS
The MCM4132 is a 32,768-bit high-speed Dynamic Random Access
Memory designed for high-performance, low-cost applications in mainframe and buffer memories and peripheral storage. Organized as 32,768
one-bit words and fabricated using Motorola's highly reliable N-channel
double-polysilicon technology, this device optimizes speed, power, and
density tradeoffs.
The MCM4132 consists of two MCM411616,384-bit high-speed MOS
dynamic Random Access Memories, each in its own package permanently connected, pin-for-pin, one on top of the other. The lower
package is referenced as Module 1, the upper as Module 2, thereby
resuhing in an 18-pin memory device, organized as 32,768 words of one
bit each, with essentially the same characteristics of the MCM4116.
IN-CHANNEL, SILICON-GATEI
32,768-BIT DYNAMIC
RANDOM ACCESS MEMORY
• 32,768 x 1 Organization
• ± 10% Tolerance on All Power Supplies
• All Inputs Are Fully TTL Compatible
L SUFFIX
• Three-State Fully TTL Compatible Output
• Common I/O Capability when using "Early-Write" Mode
•
SIDEBRAZE
CASE
Flexible Timing with Read-Modify-Write, RAS-Only Refresh, and
Page-Mode Capability
749-01
• On-Chip Latches for Addresses and Data In
•
Fast Access
150 ns 200 ns 250 ns 300 ns -
PIN ASSIGNMENT
Time Options:
MCM4132L15
MCM4132L20
MCM4132L25
MCM4132L30
VBB
ABSOLUTE MAXIMUM RATINGS ISee Notel
Rating
Voltage on Any Pin Relative to VBB
Operating Temperture Range
Storage Temperature Range
Power DiSSipation
Data Out Current
3
16 CAS 2
15
RAS2 0
14 A6
0
AO 6
13 A3
Al
7
12 A4
Vin. Vout
TA
Tstg
PD
lout
-0.5to +20
o to + 70
-65to +150
1.0
V
A2
8
11
A5
VDO 9
10
VCC
50
'c
'c
W
mA
NOTE: RASl and CAS, indicate bottom device.
AO-A6
CASl
CAS2
0
0
RASl
~S2
CAPACITANCE
If = 1.0 MHz, TA = 25'C, VCC= 5 V, periodically sampled rather than 100% tested.1
Output Capacitance 101
W
RASl 4
Unit
CONDITIONS. Exposure to higher than recommended voltages for extended periods
of time could affect device reliability.
--
17 CAS 1
Value
ceeded. Functional operation should be restricted to RECOMMENDED OPERATING
Parameter
VSS
2
Symbol
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are ex-
input Capacitance IAO-A51, D
Input Capacitance ~, CAS', WRITE
[ieV18
D
Symbol
Typ
Max
Cll
CI2
Co
4.0
8.0
5.0
10
13
14
Unit
pF
pF
pF
Motorola reserves the right to make changes to any products herein to improve
reliability, function or deSign. Motorola does not assume any liabilty arising out
of the application or use of any product or circuit described herein; neither does
it convey any lisence under its patent rights nor the rights of others.
Notes
8
8
8
W
VBB
VCC
VDD
VSS
PIN NAMES
Address Inputs
Column Address Strobe, Module 1
Column Address Strobe, Module 2
Data In
Data Out
Row Address Strobe, Module 1
Row Address Strobe, Module 2
Read/Write Input
Power 1-5 VI
Power 1+5 VI
Power 1+ 12 VI
Ground
This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it is advised that normal precautions be taken to avod application of
any voltage higher than maximum rated voltages
to this high impedance circuit.
059827/11-80
2-27
•
MCM4132
BLOCK DIAGRAM
WRii'EE
Write
Clocks
.~
J
m
I
Clock
_I Generator 1
lor 2
No.1
I •
•I
Data
In
Suffer
MU!tlPI~Xed
Clock
Generator
CAS"
lor 2
_VDO
_VCC
_VSS
-Vss
I
*'
~
L
Clock
Generator
No.2
I
~
A6
Latch
~~
I
Release
-L
A5
__ Mux
A4 - - - - - - Address
Row
A3 Input ~ Decoder
Suffers
1:128
A2
L-
Memory Array
128
Row
Lines
m
128 - Sense -
,
I
-
10f2
Data
R·efresh Amps ~ Sus
~ Select
Data ' - :-
InlOut
Memory Array
I
---
i==-"0ata Out (0)
Dummy Cells
,,
,
A1
AO
Data
Out
Suffer
Data In (0)
I
Dummy Cells
-
--- ~~I~r,.:~ __ -
-
Mux
Switch
===-t
Column Decoders
1 of 64
A -All
DC OPERATING CONDITIONS AND CHARACTERISTICS
IFull operating voltage and temperature range unless otherwise noted)
RECOMMENDED OPERATING CONDITIONS
P.~r
Svmbol
Min
Tvo
Max
Unit
N0t88
VOO
VCC
VSS
VSS
10.8
4.5
0
-4.5
12.0
5.0
0
-5.0
13.2
5.5
0
-5.5
V
1
1,2
1
1
Logic 1 Voltage, All Inputs
VIH
-
V
VIL
2.4
-1.0
7.0
Logic 0 Voltage, All Inputs
0.8
V
1
1
Symbol
Min
1 Max
Unit
N0t88
IDOl
ICC
-
36.5
mA
mA
p.A
4
Supply Voltage
DC CHARACTERISTICS
Characteriatfc
1 Chip Selected
Average VOO Powe,-Supply Current
V CC Power Supply Current
Average VSS Power Supply Current
ISS1,3
ISS2
1002
Standby VBS Power Supply Current
. Standby VOO Power Supply Current
Averege VOO Power Supply Current During "RAS Only"· Cycles
Input Leakage Current IAny Input)
Output Leakage Current
Output Logic 1 Voltage
1003
IIiU
10lU
VOH
VOL
@ lout= -5 mA
Output Logic 0 Voltage @ .lout = 4.2 mA
300
200
-
3
"A
mA
-
28.5
10
mA
p.A
10
p.A
2.4
-
V
0.4
V
70
-
mA
mA
400
p.A
200
"A
mA
mA
5
6
4
6,7
2
2 Chip Selected (17)
Average VOO Power Supply Current
1001
V CC Power Supply Current
Average VSS Power Supply Current
ICC
ISSl 3
ISB2
1002
Standby ilSS Power Supply Current
Standby VOO Power Supply Current
Average VOO Power Supply Current During "RAS Only" Cycles
Input Leakage Current IAny Input)
1003
IIiU
Output Leakage Current
10lU
Output Logic 1 Voltage@ lout- -5 mA
Output Logic Voltage @ lout =4.2 mA
VOH
VOL
2-28
-
-
3
54
-
10
2.4
-
-
0.4
10
"A
".A
V
V
4
6
6
4
6,7
2
MCM4132
AC OPERATING CONDITIONS AND CHARACTERISTICS
IVDD= 12 V
ISee Notes 3, 9, 14)
-5.0 V ± 10%, VSS=O V, TA=O to 70·C)
± 10%, VCC= 5.0 V ± 10%, VBB=
READ WRiTE AND READ-MODiFY-WRITE CYCLES
Parameter
Random Read or Write Cycle Time
Symbol
MCM4132-15
Min
Max
410
375
-
515
-
200
-
-
135
375
375
-
150
-
100
375
Read Write Cycle Time
tRWC
Access Time from Row Address Strobe
tRAC
tCAC
MCM4132-25
Min
Max
-
-
tRC
Access Time from Column
._. Address Strobe
MCM4132-20
Min
Max
-
MCM4132-30
Min
Max
Unit
-
-
250
-
300
ns
10,12
-
165
-
200
ns
II, 12
ns
ns
Output Buffer and Turn·off Delay
tOFF
0
50
0
50
0
50
0
tRP
100
-
120
-
1'50
-
160
50
-
ns
Row Address Strobe Precharge Time
Row Address Strobe Pulse Width
tRAS
150
10,000
200
10,000
250
10,000
300
10,000
ns
Column Address Strobe Pulse Width
tCAS
100
10,000
135
10,000
165
10,000
200
10,000
ns
Row to Column Strobe Lead Time
tRr.n
20
50
25
65
35
85
60
100
ns
Row Address Setup Time
tASR
0
-
0
-
0
-
0
ns
Row Address Hold Time
tR.AH
20
-
25
35
Column Address Setup Time
tASC
-10
-10
-10
-
-10
tCAH
45
55
-
75
-
100
-
ns
Column Address Hold Time
-
-
-
tAR
95
-
120
-
160
-
200
-
ns
tT
3.0
35
3.0
50
3.0
50
3.0
50
ns
tRCS
0
-
0
0
-
0
-
ns
0
-
0
-
ns
75
-
100
-
ns
Column Address Hold Time
Referenced to RAS
~ooiime
IRise and Fall!
Notes
480
550
60
ns
13
ns
ns
14
Read Command Hold time
tRCH
0
-
0
Write Command Hold Time
tWCH
45
-
55
-
Write Command Hold Time
Referenced to ~
tWCR
95
-
120
-
160
-
200
-
ns
twp
45
-
55
-
75
-
100
-
ns
Write Command to Row Strobe
Lead Time
tRWL
60
-
60
-
100
-
160
-
ns
Write Command to Column Strobe
Lead Time
tCWL
60
-
60
-
100
-
160
-
ns
0
-
0
-
0
-
ns
15
100
-
ns
15
-
200
-
ns
ns
Read Command Setup Time
Write Command Pulse Width
f-=- .._ ...
,..,
.
Column to Row Strobe Precharge Time
tCRP
-20
RAS Hold Time
tRSH
100
-
Refresh Period
tRFSH
-
Data in Setup Time
tDS
0
Data in Hold Time
tDH
45
tDHR
95
.....
~'in
Hold Time Referenced to RAS
55
.-
120
75
-'160
-20
-
-20
-
-20
-
135
-
165
-
200
-
ns
2.0
-
2.0
-
2.0
-
2.0
ms
-20
-
-20
ns
16
210
-
260
-
ns
125
ns
16
100
-
ns
WRITE Command Setup Time
twr.s
-20
trwn
70
-
-20
CAS to WRITE Delay
RAS to WRITE Delay
tRWD
120
-
160
-
tcp
60
-
60
-
100
-
tpc
170
225
-
325
-
ns
150
-
275
tr.SH
-
250
-
300
-
ns
CAS' Precharge Time
IPage Mode Cycle Only)
Page Mode Cycle Time
~~ldTime
95
200
160
NOTES.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
All voltages referenced to VSS. VeB must be applied before and removed after other supply voltages.
Output voltage will swing from VSS to Vee under open circuit conditions. For purposes of maintaining data in power-down mode, Vee may be reduced to
VSS without affecting refresh operations. VOH (mIni specification is not guaranteed in this mode.
Several cycles are required after power-up before proper device operation IS achieved. Any 8 cycles which perform refresh are adequate.
Current is proportional to cycle rate, maximum current is measured at the fastest cycle rate.
Ice depends upon output loading. The Vec supply is connected to the output buffer only.
Output is disabled (open-circuit) when CAS is at a logic 1.
OVsV out s+5.5V.
Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = 14T / 4V.
AC measurements assume tT = 5.0 ns
Assumes that tRCO S tRCD (maxI.
Assumes that tACO ~tReD (max).
Measured with a load circuit equivalent to 2 TTL loads and 100 pF.
Operation within the tACO (max) limit ensures that tRAC (max) can be met. tACO (max) is specified as a reference point only; if tRCD is greater than the
specified tACO (Max) limit, then access time is controlled exclusively by tCAC.
VIH (min) or VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH or VIH and VIL.
These parameters are referenced to CAS" leading edge in random write cycles and to WRTTE leading edge in delayed write or read-modify-write cycles.
twcs, tewD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: If tWCSii!: twcs (min),
the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tCWD~tCWD (min) and
tRWD~tRWD (min), the cycle is a read-write cycle and the data out will contain data read from the selected cell; if neither of the above sets of condittons is
satisfied, the condition of the data out (at access time) is indeterminate.
Two chips selected is only applicable for RAS only refresh on the 32K. module.
2-29
•
MCM4132
READ CYCLE TIMING
'RC
tRAS ----~,
•
tCSH
.--__-__-~I-
tRCO _ _~)4--
CAS
ADDRESSES
tAS H
I
VIH
'CAS
VIL
VIH
VIL
WRITE
VIH
VIL
Q
IData Outl
VDH
VOL
High Z
WRITE CYCLE TIMING
ADDRESSES
WRITE
D IData Inl
Q
VIM
VIL
VIH~~~~
'"
VI
L
VIM
Z>()CiC<'X)rznV"i:kAA?""'.....~ r---:-----
lData Outl
-~~~"'"""""'"
High Z - - - - - - - - - - - - - - - -
2-30
MCM4132
READ·WRITE/READ·MODIFY·WRITE CYCLE
RAS
I--~:-~t;-=A-R-=-=-=-;-~--=~±:~~~_~~:_~'~~_-
v,H
V,L
3- I·
_ _.._.-.-_1C",
(::
tCSH
-
teAs - - - - - - - - - - . - ,
CAS
V,L
ADDRESSES
Q
IData Outl
I
~~--~------------~~~
V,H
V,L
I_
WFfiTE
tCRP...j
I
V,H
tCWD-----.j
V,H
V,L
VOH
VOL
o lData Inl
V,H
V,L
RAS ONLY REFRESH TIMING
Note:
CAS~VIH, WRITE~
Don't Care
ADC~ESSES
Q lData Outl
- - - - - - - - - - - - - - High Z - - - - - - - - - - - - - - - - -
'During a read or write cycle, one '6K segment is selected. Depending on segment being addressed, RAS,/CAS, or RAS2/CAS2 is deselected.
2-31
I
®
MCM4516
MOTOROLA
Product Previe'VV
MOS
IN·CHANNEL, SILlCON·GATEI
16,384-BIT DYNAMIC RAM
The MCM4516 is a 16,384-bit, high-speed, dynamic Random-Access
Memory. Organized as 16,384 one-bit words and fabricated using HMOS
high-performance, N-channel, silicon-gate technology. This new bree.d of
5-volt only dynamic RAM combines high performance with low cost and
improved reliability.
By multiplexing row- and column-address inputs, the MCM4516 requires only eight address lines and permits packaging in standard 16-pin
dual-in-line packages. Complete address decoding is done on chip with
address latches incorporated. Data out is controlled by CAS allowing
for greater system flexibility.
All inputs and outputs, including clocks, are fully TTL compatible.
The MCM4516 incorporates a one-transistor cell design and dynamic
storage techniques. In addition to the RAS-only refresh mode, refresh
control function available on pin 1 provides automatic and self-refresh
modes.
•
Organized as 16,384 Words of 1 Bit
•
Single +5 Volt Operation
•
Fast 120 ns Operation
•
Low Power Dissipation:
200 mW Maximum (Active)
20 mW Maximum (Standby)
16,384-BIT
DYNAMIC RAM
L SUFFIX
CERAMIC PACKAGE
CASE 69(}13
e SUFFIX
FRIT-SEAL
CERAMIC PACKAGE
CASE 620-06
16
-
.
',,!;'
,
PIN ASSIGNMENT
REFRESH
i'iV16pvss
D
15 peAS
W
RAS
14PQ
4
13pA6
12 pA3
AO
5
•
Three-State Data Output
A2
6
11
•
Internal Latches for Address and Data Input
A1
7
10pA5
•
Early-Write Output Capabil ity
•
64K Compatible 128-Cycle, 2 ms Refresh
Vec 8
•
Control on Pin 1 for Automatic and Self Refresh
•
R'AS-only Refresh Mode
•
CAS Controlled Output Providing Latched or Unlatched Data
•
Upward Pin Compatibility from the 16K RAM (MCrA4116)
to the 64K RAM (MCM6664)
pA4
SPN/C
PIN NAMES
....... Refresh
.. ... Address Input
.. ........ Dataln
. ..... DataOut
. ..... Read/Write Input
... Row Address Strobe
........... Column Address Strobe
........ Power I + 5 VI
............................. Ground
REFRESH
AO-A6 .. ..
D ................. ..
Q ..
W ..
RAS
CAS
VCC
VSS ..
OUTPUT BUFFER TRUTH TABLE
Internal
Early Write
CAS
H
X
X
H
X
IXI
X
IXI
High Z
L
L
L
IHI
Maintains Previous
L
L
H
III
Active
Refresh Control (CAS Internal)
Output Buffer
High Z
Data
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however. it is advised that
normal precautions be taken to avoid application of any voltage higher than maximum rated
voltages to this high impedance circuit.
NP303/4-79
2-32
MCM4516
PIN ASSIGNMENT COMPARISON
1.
MCM4516
MCM6632
MCM4517
REFRESH
VSS
N/C
0
CAS
IN
VSS
REFRESH
VSS
0
15
CAS
0
CAS
IN
14
0
A6
RAS
13
A6
RAS
A6
A3
0
RAS
16
W
0
AO
12
A3
AO
12
A3
AO
A2
11
A4
A2
11
A4
A2
A4
Al
10
A5
Al
10
A5
Al
A5
VCC
9
VCC
9
1.
N/C
MCM6633
N/C·
D
N/C
MCM6665
VSS
REFRESH
VSS
NIC
VSS
CAS
D
15
CAS
D
CAS
IN
0
W
IN
14
Q
RAS
A6
RAS
13
A6
RAS
AO
A3
AO
12
A3
AO
11
A4
A2
11
A4
A2
11
A4
10
A5
Al
10
A5
Al
10
A5
9
A7
Vce
9
A7
Vce
9
A7
A2
6
Al
Vce
8
--
A7
VCC
MCM6664
A6
A3
8
PIN VARIATIONS
Pin Number
MCM4116
MCM4616
MCM4617
MCM6632
Vaal-5 VI
REFRESH
N/C
REFRESH
MCM6663
N/C
MCM6664
1
REFRESH
N/C
8
9
VDD(+ 12 VI
VCC
VCC
VCC(+5VI
N/C
N/C
VCC
A7
VCC
A7
VCC
A7
VCC
A7
ON·CHIP REFRESH FEATURES/BENEFITS
Reduce System Refresh Controller Design Problem
Reduce System Parts Count
Reduce System Noise Increasing System Reliability
Reduce System Power During Refresh
READ CYCLE TIMING
14---------
-++____.....___.
V IHC _ _ _ _
140-----
o IData Oull
VOL
'RAS
+-_
j4-_ _
~tOFF
'RAC
----------High Z ------{]
~
2-33
Valid Data
_ _ _ _~~
MCM6666
MCM4616
WRITE CYCLE TIMING
V I HC
•
~
______________
---------"L.f\.~...------
~
___ 'RC ______________________
~
'AR
V,L
V,HC
----------+~~::~~~::~t'--t_---
V,L
V,H
ADDRESSES
V,L
V I He "''7r"'7r"it""'X''''X-7\:-7I.
VIL~~~~~~_r~~~::=+::::~t;~~~~~~~~~~~X-~~~~~~~-K~~~
V,H
o IData In)
~~~~~~~~_x~1J~~~::::~~~x_~~~~w_w_w_w_r_~x_~x_~~~
VIL~~~~~~~~~~---------~~~~~~~~~~~~~~~~~
14--------
a lData Out)
'DH R ------~
VOH
vOL
----------------------------------- High Z - - - - - - - - - - - - - - - - - - - - - - - - -
READ-WRITE/READ-MODIFY-WRITE CYCLE TIMING
~---------------------'RWC --------------~
RAS
CAS
ADDRESSES
a IData Out)
o lData In)
MCM4516
SELF REFRESH MODE (BItIIIIY Backupl
(SEE NOTE 171
''"~
VIL
\----l\
tRFD
tFBR
-1~--------
VIH----------,I
AUTOMATIC PULSE REFRESH CYCLE (SEE NOTE 171
SINGLE PULSE
VIH~~~--------------------------~
i4--------------tFRD-------·--------~
tRFD
VIH
i 4 - - - - - - - - - - - - ' F P - - - - - - - - - - -__
REFRESH
YIL
AUTOMATIC PULSE REFRESH CYCLE - MULTIPLE PULSE
(SEE NOTE 171
RAS-ONL Y REFRESH CYCLE
(Data-In and WRITE are Don't Care, CAS is HIGHI
~---------tRC---------j"i
VIH
VIL
Y IH V":r-
MCM4517
PIN ASSIGNMENT COMPARISON
MCM4516
MCM6632
MCM4517
1.
1.
16
VSS
N/C
2
15
CAS
D
14
Q
13
A6
A6
12
A3
A3
AO
5
12
A3
6
11
A4
A4
A2
6
Al
7
10
A5
A5
A1
"
A4
VCC
8
9
REFRESH
D
W
RAS
4
AO
A2
1.
D
W
Q
A2
W
VCC
MCM6633
N/C·
CAS
W
N/C
REFRESH
VSS
VCC
VSS
REFRESH
D
Q
1.
16
VSS
N/C·
2
15
CAS
D
14
Q
W
A6
RAS
4
13
A6
RAS
AO
A3
AO
5
12
A3
AO
11
A4
A2
6
A2
10
A5
A1
"
A4
A5
A1
9
A7
VCC
A7
VCC
VCC
8
10
8
CAS
14
Q
13
A6
10
8
•
A5
A7
1.
VSS
CAS
W
RAS
Al
VSS
MCM6665
MCM6664
CAS
16
15
Q
4
A6
A3
6
8
"
A4
A5
A7
PIN VARIATIONS
Pin Number
MCM4116
MCM4516
MCM4517
MCM6632
MCM6663
MCM6664
MCM6665
1
VBB(-5 VI
VDD(+ 12 VI
VCC(+5 VI
REFRESH
N/C
REFRESH
N/C·
REFRESH
N/C·
VCC
VCC
N/C
N/C
VCC
A7
VCC
A7
VCC
A7
VCC
A7
8
9
*!nternal pull up resistor should be left open or tied to
Vee.
2-41
•
®
MOTOROI.A
MCM6632
32,768-BIT DYNAMIC RAM
MOS
The MCM6632 is a 32,768 bit, high-speed, dynamic Random-Access
Memory. Organized as 32,768 one-bit words and fabricated using
HMOS high-performance N-channel silicon-gate technology. This new
breed of 5-volt only dynamic RAM combines high performance with low
cost and improved reliability.
By multiplexing row- and column-address inputs, the MCM6632 requires only eight address lines and permits packaging in standard 16-pin
dual-in-line packages. Complete ~ddress decoding is done on chip with
address latches incorporated. Data out is controlled by CAS allowing
for greater system flexibility.
All inputs and outputs, including clocks, are fully TTL compatible.
The MCM6632 incorporates a one-transistor cell design and dynamic
storage techniques. In addition to the RAS-only refresh mode, refresh
control function available on pin 1 provides automatic and self-refresh
modes.
• Organized as 32,768 Words of 1 Bit
IN-CHANNEL, SILICON-GATE)
32,768-BIT
DYNAMIC RANDOM ACCESS
MEMORY
• Single + 5 V Operation
• Fast 150 ns Operation
• Low Power Dissipation
275 mW Maximum (Activel
30 mW Maximum (Standby)
•
•
•
•
•
•
•
•
•
•
LSUFFIX
CERAMIC PACKAGE
CASE 690
Three-State Data Output
Internal Latches for Address and Data Input
Early-Write Common I/O Capability
16K Compatible 128-Cycle, 2 ms Refresh
Control on Pin 1 for Automatic and Self Refresh
RAS-only Refresh Mode
CAS Controlled Output
Upward Pin Compatible from the 16K RAM (MCM4116)
.One Half of the 64K RAM MCM6664
The Operating Half of the MCM6632 is Indicated by Device Marking:
MCM66320 Tie A7 CAS (A15) Low "0"
MCM66321 Tie A7 CAS (A151 High "1"
PIN ASSIGNMENT
REFRESH [['ii\..I""i6b VSS
D [ 2
W
RAS
15
P CAS
14P
P A3
AD
12
A2
11
A4
At
lOb
A5
A7
VCC
BLOCK DIAGRAM
Q
13p A6
_vCC
_-VSS
recharg
Clock
Sense AmplifIer
D
~
~
Al_
j
A2 .....
E
0.
"j;>
A4 .....
u
"j;>
~
0
~
"0
"0
a:
~
16, 384-Bit Memory
0
~
1/211 of 2561
Column Decoder
1/2 Cell
Logic
11
i+-CAS
a:
~wrjte,W
;;
1/211 of 2561
Column Decoder
I+-- ~
~
~
!--REFRESH
0
"0
16,384-Bit Me,mary
Array
@
D
~
a:
16,384-8it Memory
Array
g> ~Data
E
i=
g
-
t-+0utput
Data. Q
This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it is advised that norany voltage higher than maximum rated voltages
15
Sense Amplifier
In, D
mal precautions be taken to avoid application of
~
A7-Clock
REFRESH.
. Refresh
AD-A7..
. ....... Addresslnput
D ......................................... Data In
Q ....................................... Data Out
W...
................. Read/Write Input
RAS..
. .... Row Address Strobe
CAS ............... Column Address Strobe
. .................... Power 1+5 V)
VCC..
VSS .... ..................
. ... Ground
u
Ii;
..:
recharg
.... RAS
u
Array
"0
~
CD
~
~
0
16,384 Bit Memory
Array
~
A3 __
A6 .....
PIN NAMES
Sense Amplifier
@
AO_
A5 .....
~
"0
to this high-impedance circuit.
Sense Amplifier
L----
DS9826/9-80
2-42
MCM6632
ABSOLUTE MAXIMUM RATINGS ISee Notel
Rating
~oltage
-
on Any Pin Relative toVSS lexcept Veci
Voltage on VCC Supply Relative to VSS
Symbol
Value
Vin, Vout
- 2 to + 7
V
Vin, Vout
--1 to + 7
V
o to
°c
TA
Operating Temperature Range
Storage Temperature Range
Power Dissipation
._---
Data Out Current
+70
FIGURE 1 - OUTPUT LOAD
5V
Unit
Tsto
Po
-65 to + 150
°c
1.0
W
lout
50
mA
970 II
NOTE' Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
-Includes Jig Capacitance
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted,)
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
MCM6664-15, -20
Logic 1 Voltage, All Inputs
Logic
a Voltage,
All Inputs
Symbol
Min
Typ
Max
Unit
Notes
VCC
VSS
4.5
5.0
5.5
a
a
a
VV
I
1
VIH
2A
VCC+l
0.8
1
-2.0
-
V
VIL
V
1
DC CHARACTERISTICS
Symbol
Min
Max
Units
Notes
VCC Power Supply Current ItRC min.1
ICCI
50
mA
4
Standby VCC Power Supply Current
ICC2
5
mA
5
VCC Power Supply Current During RAS Only Refresh Cycles
ICC3
-
IIILI
IF
40
10
mA
Input Leakage Current lany inputl lexcept REFRESHI IVSSSVinSVCCI
-
~A
-
125
~A
-
Characteristic
REFRESH Input Current
IVF~VSSI
---..- -
Output Leakage Current (CAS at logic 1, Os;Vouts5.5)
IOILi
Output Logic 1 Voltage @ lout ~ - 4 mA
VOH
a Voltage @
VOL
Output Logic
lout~4
mA
10
-
~A
-
2A
-
V
OA
V
-
Max Units
CAPACITANCE If~ -1.0 MHz, TA~ 25°C, VCC ~ 5 V Periodically Sampled Rather Than 100% Testedl
Symbol
Typ
Input Capacitance (AO-A71, Din
Cll
4
Input Capacitance RAS, CAS, WRITE
CI2
Co
8
Parameter
Output Capacitance 1D0uti ICAS ~ VIH to disable output)
5
5
10
7
Notes
pF
7
pF
7
pF
7
Units
Notes
ns
ns
ns
ns
ns
ns
ns
ns
8,9
8,9
to,12
11,12
18
ns
ns
ns
13
AC OPERATING CONDITIONS AND CHARACTERISTICS
ISee Notes 2,3,6, and Figure II
IRead, Write, and Read-Modify-Write Cyclesl
IFull Operating Voltage and Temperature Range Unless Otherwise Notedl
Symbol
Parameter
Random Read or Write Cycle Time
Read Write Cycle Time
tRC
tRWC
tRAC
tCAC
tOFF
tRP
Access Time from Row Address Strobe
Access Time from Column Address Strobe
Output Buffer and Turn-Off Delay
Row Address Strobe Precharge Time
Row Address Strobe Pulse Width
tRAS
tCAS
tRCD
tASR
tRAH
tASC
tCAH
tAR
tT
Column Address Strobe Pulse Width
Row to Column Strobe Lead Time
Row Address Setup Time
Row Address Hold Time
Column Address Setup Time
Column Address Hold Time
Column Address Hold Time Referenced to RAS
Transition Time (Rise and Fall!
2-43
MCM6632-15 ' MCM6632-20
Min
Max
Min
Max
300
300
-
a
-
350
350
-
150
75
30
-
200
110
a
40
-
-1()()()()
1()()()()
90
-
120
150
75
1()()()()
1()()()()
140
200
110
30
75
35
a
a
45
120
-
3
50
25
a
30
0
55
155
3
-
50
ns
ns
ns
ns
-
-
6
MCM6632
AC OPERATING CONDITIONS AND CHARACTERISTICS
(See Notes 2, 3, 6 and Figure 11
IRead, Write, and Read-Modify-Write Cycles)
(Full Operating Voltage and Temperature Range Unless Otherwise Notedl
Parameter
Symbol
MCM6632-15
MCM6632-20
Min
Max
Min
Max
-
0
10
35
55
155
55
-
ns
-
ns
14
ns
14
ns
-
ns
-
ns
-
-
ns
-
ns
15
-
ns
15
ns
-
ns
110
-
-
Read Command Setup Time
tRCS
0
Read Command Hold Time
tRCH
10
Read Command Hold Time Referenced to RAS
tRRH
30
Write Command Hold Time
tWCH
tWr.R
45
i'fAS
-
t~
45
Write Command to Row Strobe Lead Time
tRWL
45
-
Write Command to Column Strobe Lead Time
tCWL
45
-
55
tDS
0
-
0
Write Command Hold Time Referenced to
Write Command Pulse Width
Data in Setup Time
Data in Hold Time
120
55
ns
Notes
tDH
45
tDHR
120
Column to Row Strobe Precharge Time
tCRP
-10
RAS Hold Time
tRSH
75
-
Refresh Period
tRFSH
-
2.0
-
2.0
ms
WRITE Command Setup Time
twcs
-10
-10
-
ns
16
to WRITE Delay
tCWD
45
-
55
ns
16
WRiit Delay
tRWD
125
'160
-
ns
16
tCSH
-
ns
tRFD
0
ns
-
Data in Hold Time Referenced to
m
RAS to
'R'AS
CAS Hold Time
i'fAS
55
Units
155
-10
160
200
ns
tFBP
2000
-
2000
-
tFBR
390
-
460
-
ns
REFRESH Cycle Time (Auto Pulse Model
tFC
330
-
360
-
ns
REFRESH Pulse Period (Auto Period Mode)
tFP
60
2000
60
2000
ns
-
ns
-
ns
-
-
ns
-
ns
-
to
mlrrS'R
Delay
REFRESH Period (Battery Backup Model
REFRESH to
RAS
Precharge Time IBattery Backup Model
0
REFRESH to RAS Setup Time (Auto Pulse Model
tFSR
30
-
30
REFRESH to RAS Delay Time (Auto Pulse Model
tFRD
390
-
460
~ Inactive Time
RAS
NOTES:
to REFRESH Lead Time
tFI
30
tFRL
390
30'
460
ns
-
1. All voltages referenced to VSS.
2. VIH min and VIL max are reference levels for measuring timing of input signals. Transition times are measured between VIH and
VIL·
3. An initial pause of 100 P.s is required after powerwup followed by any 8 RAS cycles before proper device operation guaranteed.
4. Current is a function of cycle rate and output loading; maximum current is measured at the fastest cycle rate with the output
open.
5. OutpUt is disabled (open-circuitl and RAS and CAS are both at a logic 1.
6. The transition time specification applies f6r all input signals. In addition to meeting the transition rate specification, all input sig~
nals must transmit between VIH and VIL (or between VIL and VIHI in a monotonic manner.
7. Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = ~
8. The specifications for tRC (mini, and tRWC (mini are used only to indicate cycle time at which proper operation over the full temperature range (O°C:sT A:S 70°C) is assured.
9. AC measurements assume tT = 5.0 ns.
10. Assumes that tRCDStRCD IMaxl
11. Assumes that tRCD"tRCD (Max)
12. Measured with a current load equivalent to 2 TTL loads 1+200 I'A, -4 mAl and 100 pF (VOH=2.0 V, VOL = -0.8 VI.
13. Operation within the tRCD (maxi limit ensures that tRAC Imaxl can be met. tRCD Imaxl is specified as a reference point only; if
tRCO is greater than'the specified tRCO (max) limit, then access time is controlled exclusively by tCAC.
14. Either tRRH or tRCH must be satisfied for a read cycle.
.
15. These parameters are referenced to CAS leading edge in random write cycles and to WRITE leading edge in delayed write or readmodify-write cycles.
16. twcs, tCWD~ and tRWO are not restrictive operating parameters. They are i~cluded in the data sheet as electrical characteri.istics only: if twcs"twcs (mini, the cycle is an early write cycle and the data out pin will remain open circuit Ihigh impedancel
throughout the entire cycle; if tCWD" tCWD (min) and tRWD" tRWD Iminl, the cycle is a read-write cycle and the data out will
contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out lat
access time) is indeterminate.
17. Addresses, data-in and WRITE are don't care. Data-out depends on the state of CAS. If (;AS remains low, the previous output
will remain ,(alid. CAS is allowed to·make an active to inactive transition during the pin #1 refresh cycle. When CAS is brought
high, the output will assume a high-impedance state.
18. toff (maxi defines the time at which the output achieves the open CIrcuit condition and is not referenced to output voltage levels.
2-44
MCM6632
PIN ASSIGNMENT COMPARISON
1.
MCM4516
VSS
D
15
CAS
VIi
14
Q
1.
MCM6632
MCM4517
16
REFRESH
N/C
16
VSS
REFRESH
1b
VSS
D
15
CAS
D
15
CAS
W
14
Q
VIi
14
0
1.
RAS
4
13
A6
RAS
4
13
A6
RAS
13
A6
AO
5
12
A3
AO
5
12
A3
AO
12
A3
A2
11
A4
A2
11
A4
A2
11
A4
A1
10
A5
A1
10
A5
A1
10
A5
9
A7
N/C
Vcc
16
VSS
REFRESH
D
15
CAS
VIi
14
Q
RAS
13
N/C
VCC
16
Vss
N/C
16
VSS
D
15
CAS
D
15
CAS
VIi
14
Q
W
14
Q
A6
RAS
13
A6
RAS
13
A6
12
A3
AO
12
A3
AO
12
A3
11
A4
A2
11
A4
A2
11
A4
10
A5
A1
10
A5
A1
10
A5
9
A7
VCC
9
A7
VCC
Vec
1.
MCM6633
N/C
AO
A2
6
A1
VCC
8
8
1.
•
MCM6665
MCM6664
A7
PIN VARIATIONS
Pin Number
MCM4ll6
MCM4516
MCM4517
MCM6632
MCM6663
MCM6664
1
VSSI-5 VI
REFRESH
N/C
REFRESH
N/C
REFRESH
N/C
8
9
VDDI+ 12 VI
VCC
VCC
VCCI+5VI
N/C
N/C
VCC
A7
VCC
A7
VCC
A7
VCC
A7
On-Chip Refresh Features/Benefits
Reduce
Reduce
Reduce
Reduce
System
System
System
System
Refresh Controller Design Problem
Parts Count
Noise IncreaSing System Reliability
Power During Refresh
_._
ORDERING INFORMATION
..
Part Number
Description
Speed
Marking"
MCM6632L15
32K Dynamic
150
MCM66320L 15/MCM66321 L 15
MCM66320L 15
Random Access
Memory
150
MCM66320L 15
MCM66321 L15
150
MCM66321 L 15
MCM6632L20
Sidebraze
MCM66320L20/ MCM66321 L20
MCM66320L20
Package "L"
200
200
200
MCM66321 L20
* MCM66320 = Tie A7 CAS IA151 Low "0"
MCM66321 = Tie A7 CAS IA151 High "1"
2-45
MCM66320L20
MCM66321 L20
MCM6665
•
MCM6632
,
READ CYCLE TIMING
lAC
tAAS
tAA
VIH
i'iAS
Vll
tASHCAS
tCAS
VIH
Addresses
VIL
Vii
VIL
LtCAC
tAAC
Q (Data Oull
tOFF
VOH
Valid
Dala
High Z
VOL
,
WRITE CYCLE TIMING
VIH
tAA
AAS
VIL
tASR
VIH
r
tRAH
~tASC-I1+
Row
Address
Addresses
VIL
~
VIL
I+-
~
__
I
tCAH
J
\T,\
-.eX (X
I I
VIH
~tCRP
V
I
Column
Address
"# VJJf
twcs
- - L tAP- - - .
tCAS
1\ \
VIL
tRSH
tCSH
~tAC
W
~
I
VIH
CAS
lAC
tRAS
tCWL
j.twc~
I twp I
AX.
I
I
IAWL]
I
~
'--li-tDS !4-tDH=-'
~tWCA
o IDala Inl
VIH
[lI.lI..[Jl\oI
Valid
Data
VIL
r&'x
[X,
E
;::
~
--.Output
Data.
Q
This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however,
it is advised that normal precautions be
taken to avoid application of any voltage
higher than maximum rated voltages to
this high-impedance circuit.
a
~
,..Data In, D
u
~
Sense Amplifier
... Write,W
rn
f4-+ g
g
~
'"
4-CAS
;;
~
~
4-RAS
u
a
~
a
~
A7+
PIN NAMES
AO-A7...
0....
~
16.384 Bit Memory
E
A4_
A6_
Sense Amplifier
~
D
C.
A2 .....
w
"0
AO+
Al+
-VSS
Sense Amplifier
A5
A7
VCC
Sense Amplifier
~
D89825/9-80
2-50
MCM6633
FIGURE 1 -
ABSOLUTE MAXIMUM RATINGS ISee Notel
Rating
Symbol
Value
Unit
Voltage on Any Pin Relative to VSS IExcept VCCI
Vin, Vout
- 210 + 7
V
Voltage on VCC Supply Relative to VSS
Operating Temperature Range
Vin, Vout
-1 to +7
V
TA
Oto +70
°c
°c
Storage Temperature Range
TstQ
Po
Power Dissipation
Data Out Current
66 to +150
1
50
lout
OUTPUT LOAO
5V
9701}
Q--~--~-+a--.
W
mA
100 pF"
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
*Includes Jig Capacitance
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted.)
RECOMMENDED OPERATING CONDITIONS
Parameter
MCM6633L 15/ MCM6633L20
M CM6633L 15-5/ M CM6633L20-5
Supply Voltage
Symbol
Min
Typ
Max
Unit
Notes
VCC
VCC
VSS
4.5
4.75
0
5.0
5.0
0
5.5
5.25
0
Vdc
1
7.0
Vdc
1
0.8
Vdc
1
Notes
Logic 1 Voltage, All Inputs
VIH
2.4
Logic 0 Voltage
VIL
.-2.0
-
DC CHARACTERISTICS
Symbol
Min
Max
Units
VCC Power Supply Current ItRC min.1
ICCl
50
mA
4
Standby V CC Power Supply Current
ICC2
-
5
mA
5
ICC3
-
40
mA
-
10
~A
Characteristic
VCC Power Supply Current During
WiS
Only Refresh Cycles
Input Leakage Current lany input I 10",Vin",5.51 I Except Pin 11
IIiLi
Output Leakage Current IOsVout",5.5I1CAS at Logic 11
IOILi
-
10
~A
-
Output Logic 1 Voltage @ lout = - 4 mA
VOH
2.4
-
V
Output Logic 0 Voltage @ lout = 4 mA
VOL
-
0.4
V
-
AC OPERATING CONDITIONS AND CHARACTERISTICS
ISee Notes 2, 3, 6, and Figure 11
IRead, Write, and Read-Modify-Write Cyclesl
IFull Operating Voltage and Temperature Range Unless Otherwise Notedl
Parameter
Symbol
Random Read or Write Cycle Time
tRC
Read Write Cycle Time
tRWC
Access Time from Row Address Strobe
Access Time from Column Address Strobe
Output Buffer and Turn-Off Delay
tRAC
Row Address Strobe Precharge Time
tCAC
tOFF
tRP
Row Address Strobe Pulse Width
tRAS
Column Address Strobe Pulse Width
tCAS
Row to Column Strobe Lead Time
tRCD
Row Address Setup Time
Row Address Hold Time'
Column Address Setup Time
tASR
tRAH
tASC
tCAH
Column Address Hold Time
Column Address Hold Time Referenced to RAS
tAR
tT
Transition Time IRise and Falll
2-51
MCM6633-15
Min
Max
300
300
0
120
150
75
30
0
25
0
45
120
3
-
MCM6633-20
Units
Min
Max
Notes
-
ns
ns
8,9
200
110
40
ns
10,12
ns
ns
11. 12
17
8,9
-
350
350
0
140
-
ns
-
10000
200
10000
-
10000
110
10000
ns
ns
75
35
90
ns
13
-
0
30
-
ns
ns
-
-
0
-
55
-
ns
ns
-
-
-
155
3
-
ns
-
50
ns
6
150
75
30
50
•
MCM6633
AC OPERATING CONDITIONS AND CHARACTERISTICS
ISee Notes 2, 3, 6, and Figure 11
I Read, Write, and Read-Modify-Write Cycles I
IFull Operating Voltage and Temperature Range Unless Otherwise Notedl
Parameter
Symbol
MCM6633-15
Min
Max
MCM6633-20
Units Notes
Min
Max
Read Command Setup Time
tRCS
0
-
Read Command Hold time
tRCH
tRRH
10
-
0
10
30
45
-
35
-
-
55
-
120
-
155
-
45
45
-
55
-
45
-
Read Command Hold Time Referenced to
Write Command Hold Time
Ri'\S
tWCH
Write Command Hold Time Referenced to RAS
tWCR
twp
Write Command Pulse Width
Write Command to R.ow Strobe Lead Time
Write Command to Column Strobe Lead Time
Data in Setup Time
tRWL
tCWL
tDS
Data in Hold Time
Data in Hold Time Referenced to
'DH
tDHR
Ri'\S
Column to Row Strobe Precharge Time
tCRP
tRSH
RAS Hold Time
Refresh Period
WRITE Command Setup Time
CAS to WRITE Delay
~ to
CAS'
wmn: Delay
Hold Time
0
45
120
10
55
55
0
ns
ns
ns
ns
-
ns
ns
-
15
-
ns
ns
-
ns
-
15
75
-
-
ns
ns
-
2.0
-
2.0
ms
-
-10
-
-10
45
125
-
55
160
-
ns
ns
16
16
ns
16
ns
-
tRFSH
twcs
tCWD
(RWD
tCSH
150
-
10
110
-
-
ns
ns
-
55
155
14
14
200
CAPACITANCE If= 1.0 MHz, TA=25°C VCC=5 V Periodically Sampled Rather Than 100% Testedl
Parameter
Input Capacitance IAO-A71, D
Input Capacitance RAS,
Ci'iS, wmTE
Output Capacitance 101 ICAS = VIH to disable output)
Max Units
Symbol
Typ
CI1
4
5
pF
7
CI2
8
10
pF
7
Co
5
7
pF
7
Notes
NOTES:
1. All voltages referenced to VSS.
2. VIH min and VIL max are reference levels for measuring timing of input signals. Transition times are measured between VIH and
VIL·
3. An initial pause of 100 its is required after power-up followed by any 8 RAS cycles before proper device operation guaranteed.
4. Current is a function of cycle rate and output loading; maximum current is measured at the fastest cycle rate with the output
open.
5. Output is disabled lopen-circuit) and RAS and CAS are both at a logic 1.
6. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input Signals must transmit between VIH and VIL (or between VIL and VIH) in a monotonic manner.
7. Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C= ~
B. The specifications for tRC (min), and tRWC (min) are used only to indicate cycle time at which proper operation over the full temperature range (O°Cs TAS70°C) is assured.
9. AC measurements assume tT = 5.0 ns.
10. Assumes that tRCDStRCD Imaxl.
Assumes that tRCD"'tRCD Imaxl.
12. Measured with a current load equivalent to 2 TTL loads 1+200 "A, - 4 mAl and 100 pF IVOH = 2.0 V, VOL = - 0.8 V)
13. Operation within the tRCD Imaxl limit ensures that tRAC Imaxl can be met. tRCD Imaxl is specified as a reference pOint.only; if
tRCD is greater than the specified tRCD Imaxl limit, then access time is controlled exclusively by tCAC·
14. Either tRRH or tRCH must be satisfied for a read cycle.
15. These parameters are referenced to CE leading edge in random write cycles and to WRITE leading edge in delayed write or read-
".
modIfy-write cycles.
16. twcs, tewD, and tRWD are not restrictive operating parameters. They are included in the data sheet as electrical characteriistics only: if twcs ~ twcs (minI, the cycle is an early write cycle and the data out pin will remain open circuit (high impedancel
throughout the entire cycle; if tCWD",tCWD Imin) and tRWD",tRWD Iminl, the cycle is a read-write cycle and the data out will
contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at
access time) is indeterminate.
17. toff (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels.
2-52
MCM6633
PIN ASSIGNMENT COMPARISON
MCM451S
MCM4517
~
VSS
N/C
VSS
REFRrnl
D
CAS
D
15
~
D
w
14
a
13
A6
12
A3
AO
a
W
m
m
AS
AO
12
A3
AO
VSS
m
a
W
m
A3
A2
6
11
A4
A2
.6
11
A4
A2
A4
A1
7
10
A5
A1
7
10
A5
A1
A5
VCC
8
9
N/C
VCC
8
9
N/C
VCC
A7
16
VSS
RErnESR
VSS
N/C
D
15
CAS
D
CAS
D
W
14
a
13
A6
RAS
A6
RAS
12
A3
AO
A3
AO
i1
A4
A2
A4
A2
10
A5
A1
A5
A1
7
9
A7
VCC
A7
VCC
8
1.
MCM6633
N/C
RAS
4
AO
A2
6
A1
VCC
8
-
A6
1.
MCM6665
W
VSS
~
a
W
Q
4
A6
A3
A4
A5
9
A7
PIN VARIATIONS
MCM6666
Pin Number
MCM4116
MCM4516
MCM4517
MCM6632
MCM6663
MCM6664
1
VBBI-5 VI
REFRESH
N/C
REFRESH
N/C
REFRESH
N/C
8
9
VDDI + 12 VI
VCC
VCC
VCCI+5 VI
N/C
N/C
VCC
A7
VCC
A7
VCC
A7
VCC
A7
ORDERING INSTRUCTIONS
PART NUMBER
DESCRIPTION
SPEED
MCM6633L15
MCM66330L15
MCM66331L15
MCM6633L20
MCM66330L20
.32K RAM
Sidebraze
Package
"L"
66330L 15/66331 L 15
150
66330L15
150
200
MCM66331 L20
·MCM66330L20 = Tie A7 CAS IA 151 Low " 0"
MCM66331L20 = Tie A7 CAS IA15J High "1"
2-53
MARKING"
150
66331L15
66330L20/66331 L20
200
66330L20
200
66331L20
MCM6633
Addresses
~------------tRAC------------~
tOFF
Q (Oata Out) VOH _ _ _ _ _ _ _ _ _ _ _ _ High Z - -_ _ _ _~
Valid
~_ _~Da~t~a___
VOL
,-
WRITE CYCLE TIMING
-
VIH
RAS
VIL
i\ \
VIL
tASR
Addresses
VIL
r
W{
tRAH
~tASC-I1-Row
Address
~
VIH
W
VIL
D (Data In)
AX.
....
~tw
I
I
I--'CRP......
/
!
tCAH
tL'i rY
UOO\X
/
~)(\\
tCWL
j.tWCH!I
I
ILtRP~ '--
tCAS
I
Column
Address
V>M
I
twcs
tRSH
tCSH
4-- tRC
VIH
'"
I
VIH
CAS
tRC
tRAS
tAR
r
Ilv.
:)(
~)(
rY
I
I
tRWLI
I
~
!+-tWCR ...
j4-tDS !4-tDH::::::"
VIH
Valid
Data
VIL
r&
f-W
rYrY
tDHR
Q (Data Out)
VOH
_______________________________ HighZ ______________________________
VOL
2-54
MCM6633
RAS-ONL Y REFRESH CYCLE
!Data·in and Write are Don't Care, CAS is HIGH)
~~----------IRC------------------~
Addresses,
AD-AS
READ-WRITE/READ-MODIFY-WRITE CYCLE
tAWC
tRAS
~~
~
__------tAR--------~
tRSH
tCSH
tCAS
VIHI ------i+---------4~""'
VIL
Addresses
__-----tCWD----......,~
2-55
•
MCM6633
MCM811116 BIT ADDRESS MAP
Pin 8
o
Row Address A7 A6 A5 A4 A3 A2 Al AO
Column Addre.. A7 A6 A5 A4 A3 A2 A 1 AO
Row
•
Column Add.....
Hex
FE
FF
·FC
FD
FA
Fa
FB
Dec
254
A6
1
1
1
1
1
1
1
1
A3
1
1
1
1
1
1
1
1
A4
1
1
1
1
1
1
1
1
AS
1
1
1
1
1
1
1
1
A2
1
1
1
1
AO
1
1
0
251
248
249
A7
1
1
1
1
1
1
1
1
1
1
0
0
F9
··
··
··
130
131
126
129
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B3
80
81
7F
7E
70
127
126
125
0
0
1
1
1
1
1
1
1
1
1
04
·
0
0
0
0
0
0
0
0
0
0
0
0
256
252
253
250
B2
$2:::58
~~
~~
5555
00
~~
W~
~~
......
02
01
00
~~.
o~
o~
0 0 ........ 0 0 ......... 0
~
~
~~
0 ........ 0 0 ........... 0 0
~
0 ............... 0 0 0 0
.COtOr--I.O~NM
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
...... O
~
~~
~~
~~
.-00000000
~~
~~
oaoooqooo
~
~~
000000000
~~
~~
000000000
~
00
000000000
~
0
0
0
0
;
~1'lt;:g,Hj858
~~
~
4
3
2
1
03
§§U
88
; If 1±:
··
··
··
··
·
···
0
Data Stored = Din. Aox. A1Y
Column
DItII
Stored
Add......
A1
o
o
2-56
o
1
o
Invened
True
True
Invened
0
0
0
0
0
0
0
0
1
1
Al
0
1
0
1
0
1
0
1
0
1
0
0
0
1
1
1
1
1
1
1
0
0
1
,
0
0
1
0
1
1
0
0
0
0
0
0
1
0
®
MOTOROLA
MCM6664
65.536-BIT DYNAMIC RAM
The MCM6664 is a 65,536 bit, high-speed, dynamic Random-Access
Memory. Organized as 65,536 one-bit words and fabricated using
HMOS high-performance N-channel silicon-gate technology. This new
breed of 5-volt only dynamic RAM combines high performance with low
cost and improved reliability.
By multiplexing row- and column-address inputs, the MCM6664 requires only eight address lines and permits packaging in standard 16-pin
dual-in-line packages. Complete address decoding is done on chip with
address latches. incorporated. Data out is controlled by CAS allowing
for greater system flexibility.
All inputs and outputs, including clocks, are fully TTL compatible.
The MCM6664 incorporates a one-transistor cell design and dynamic
storage techniqueS. In addition to the RAS-only refresh mode, refresh
control function available on pin 1 provides automatic and self-refresh
modes.
MOS
(N-CHANNEL, SILICON-GATE)
65. 536-B IT
DYNAMIC RANDOM ACCESS
MEMORY
• Organized as 65,536 Words of 1 Bit
L SUFFIX
• Single + 5 V Operat!on
CERAMIC PACKAGE
CASE 690
• Fast 150 ns Operation
• Low Power Dissipation
275 mW Maximum (Active)
30 mW Maximum (Standby)
PIN ASSIGNMENT
• Three-State Data Output
• Internal Latches for Address and Data Input
• Early-Write Common 1/0 Capability
REFRESH
r;'i\J"i6
VSS
D
15
CAS
W
14
0
RAS
13
A6
AO
12
A3
A2
11
A4
• 16K Compatible 128-Cycle, 2 ms Refresh
• Control on Pin 1 for Automatic and Self Refresh
• RAS-only Refresh Mode
• CAS Controlled Output
• Upward Pin Compatible from the 16K RAM (MCM4116)
;"",
VCC
BLOCK DIAGRAM
I.
recharge
Clock
Sense
Ampll~ier
A3'
....
...
....
A5 ....
....
A4
,
A7
REFRESH
AO-A7 ..
D .. .
0
j
.g.
0
16,384 B,t Memory
Array
a:
~
16, 384-Bit Memory
-
§
112 11 of 2561
112 (I of 2561
0
"2 Cell
Column Decoder
logic
Column Decoder
~
~
~
'"
~
"0
... .
Array
Clock
~
0
~
~
;;
f4-(
"C
~
0
16,384-8it Memory
g>
1--1Data In. 0
E
....
;::
Array
g
0
~
Output
Data, Q
This device contains circuitry to protect the in-
puts against damage due to high static voltages
or electric fields; however, it is advised that normal precautions be taken to avoid application of
0
-
f4-'Write,W
RAS .... .
CAS ..
VCC
VSS
PIN NAMES
..................... Refresh
. Address Inpul
.. ........... Data In
.. ......... Data Out
.. ....... Read/Write Input
........ Row Address Strobe
.. .. Column Address Strobe
.............. Power 1+5 VI
.. .......... Ground
~ 14-'
a:
Sense Amplifier
w. .... .
A5
A7
u
~
16,384-8it Memory
1+-'
a:
"C
"0
recharge
.....
.....
0 .. ..
§
u
Array
0
~
~
e
~
~
A2
,----Sense Amplifier
~
AD
AI .
.
"C
10
8
Sense Amplifier
-
any voltage higher than maximum rated voltages
to this high-impedance circuit.
059822/9-80
2-57
•
PI
MCM6664
ABSOLUTE MAXIMUM RATINGS ISee Notel
FIGURE 1 -
Rating
Symbol
Value
Unit
Voltage on Any Pin Relative to VSS lexcept VCCI
Yin, Vout
-2 to + 7
V
Voltage on VCC Supply Relative to VSS
Yin, Vout
-1 to + 7
V
o to
°c
Operating Temperature Range
TA
Storage Temperature Range
+ 70
Tsta
-66 to +150
°c
Power Dissipation
PD
1.0
W
Data Out Current
lout
50
mA
OUTPUT LOAD
5V
9700
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are ex·
ceeded. Functional operation should be restricted to RECOMMENDED OPERAT·
ING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
·Includes Jig Capacitance
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Fun operating voltage and temperature range unless otherwise noted,)
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
MCM6664-15, -20
Symbol
Min
Typ
Max
Unit
Notes
VCC
VSS
4.5
0
5.0
0
5.5
0
V
V
1
1
-
VCC+l
V
1
0.8
V
1
Notes
Logic 1 Voltage, All Inputs
VIH
2.4
Logic 0 Voltage, All Inputs
VIL
-2.0
DC CHARACTERISTICS
Characteristic
Symbol
Min
Max
Units
VCC Power Supply Current ItRC min.1
ICCl
50
mA
4
Standby V CC Power Supply Current
ICC2
5
mA
5
VCC Power Supply Current During RAS Only Refresh Cycles
ICC3
-
40
mA
Input Leakage Current lany input except REFRESHI IVSS",Vin",VCCI
IIiLi
-
10
~A
-
IE.
-
125
~A
-
Output Leakage Current ICAS at logic 1, 0",V out s5.51
IOILi
-
10
~A
Output Logic 1 Voltage @ lout = - 4 mA
VOH
2.4
-
V
Output Logic 0 Voltage @ lout = 4 mA
VOL
-
0.4
V
-
Symbol
Typ
Max
Units
Notes
Cll
4
5
pF
7
CI2
8
10
pF
7
Co
5
7
pF
7
Units
Notes
Rl:I"IfESFi
Input Current IVF- VSSI
CAPACITANCE If= 1.0 MHz, TA= 25°C VCC= 5 V Periodically Sampled Rather Than 100% Testedl
Parameter
Input Capacitance lAO-Ali, D
Input Capacitance RAS,
CAS,
Output Capacitance 101
1m = VIH to disable outputl
WRITE
AC OPERATING CONDITIONS AND CHARACTERISTICS
ISee Notes 2, 3, 6 and Figure 1I
IRead, Write, and Read-Modify-Write Cyclesl
IFull Operating Voltage and Temperature Range Unless Otherwise Notedl
Symbol
Parameter
Random Read or Write Cycle Time
Read Write Cycle Time
M M _15
Min
Max
MCM6664-20
Min
Max
-
ns
8,9
ns
8,9
-
200
ns
10,12
110
ns
11,12
tRC
300
-
350
tRWC
300
-
350
tRAC
-
150
tCAC
-
75
tOFF
0
0
40
ns
18
tRP
120
30
-
140
-
ns
-
Row Address Strobe Pulse Width
tRAS
150
10000
200
10000
ns
-
Column Address Strobe Pulse Width
tCAS
75
10000
110
10000
ns
-
Row to Column Strobe Lead Time
tRCD
30
75
35
90
ns
13
30
-
ns
0
ns
-
55
-
ns
-
155
-
ns
3
50
ns
6
Access Time from Row Address Strobe
Access Time from Column Address Strobe
Output Buffer and Turn-Off Delay
--
Row Address Strobe Precharge Time
Row Address SetupTime
tASR
0
Row Address Hold Time
tRAH
25
Column Address Setup Time
tASC
0
Column Address Hold Time
tCAH
45
tAR
120
-
tT
3
50
Column Address Hold Time Referenced to RAS
Transition Time (Rise and Fall)
2-58
ns
0
MCM6664
AC OPERATING CONDITIONS AND CHARACTERISTICS
(See Notes 2, 3, 6, and Figure 1I
(Read, Write, and Read-Modify-Write Cycles I
(Full Operating Voltage and Temperature Range Unless Otherwise Noted)
Parameter
Symbol
MCM6664-15
Units
Notes
Max
Min
Max
-
0
ns
-
ns
14
ns
14
ns
ns
-
0
-
ns
15
55
-
ns
15
155
ns
-
-10
ns
Read Command Setup Time
tRCS
0
Read Command Hold Time
tRCH
10
Read Command Hold Time Referenced to RAS
tRRH
30
Write Command Hold Time
tWCH
45
Write Command Hold Time Referenced to RAS
tWCR
120
Write Command Pulse Width
MCM6664-20
Min
twp
45
Write Command to Row Strobe Lead Time
tElWJ.
45
Write Command to Column Strobe Lead Time
tCWL
45
10
35
55
155
55
55
55
ns
ns
ns
Data in Setup Time
tDS
0
Data in Hold Time
tDH
45
Data in Hold Time Referenced to RAS
tDHR
120
Column to Row Strobe Precharge Time
tCRP
-10
RAS Hold Time
tRSH
75
-
110
-
Refresh Period
tRFSH
-
2.0
-
2.0
ms
-
WRITE Command Setup Time
twcs
-10
-
-10
16
tCWD
45
55
tRWD
125
tCSH
150
tRFD
0
tFBP
2000
-
2000
tFBR
390
-
460
REFRESH Cycle Time (Auto Pulse Model
tFC
330
-
380
-
ns
CAS to WR ITE Delay
REFRESH Pulse Period (Auto Period Model
tFP
60
2000
60
2000
ns
-
30
-
ns
RAS to
WRiit
Delay
CAS Hold Time
RAS
to
RrrI1E"S"R
Delay
REFRESH Period (Battery Backup Model
REFRESH to
RAS
Precharge Time (Battery Backup Model
REFRESH to RAS Setup Time (Auto Pulse Model
tFSR
30
REFRESH to RAS Delay Time (Auto Pulse Model
tFRD
390
tFI
30
tFRL
390
REFRESH Inactive Time
RAS to REFRESH Lead Time
NOTES:
160
200
0
460
30
460
ns
ns
16
ns
16
ns
-
ns
ns
ns
ns
ns
ns
ns
1. All voltages referenced tc V S S.
2. VIH min and VIL max are reference levels for measuring timing of input signals. Transition times are measured between VIH and
VIL·
_
3. An initial pause of 100 P.s is required after power-up followed by any 8 RAS cycles before proper device operation guaranteed.
4. Current is a function of cycle rate and output loading; maximum current is measured at the fastest cycle rate with the output
open.
5. Output is disabled (open-circuitl and RAS and CAS are both at a logic 1.
6. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, ali input sig~
nals must transmit between VIH and VIL (or between VIL and VIH) in a monotonic manner.
7. Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C= ~
8. The specifications for tRC (min), and tRWC (min) are used only to indicate cycle time at which proper operation over the full tem~
perature range (Q°CsTAS70°C) is assured.
9. AC measurements assume tT = 5.0 ns.
10. Assumes that tRCD",tRCD IMaxl
11. Assumes that tRCD'" tRCD IMaxl
12. Measured with a current load equivalent to 2 TTL (+ 200 I'A, -4 mAl loads and 100 pF (VOH ~ 2.0 V, VOL ~ - 0.8 VI.
13. Operation within the tRCO (max) limit ensures that tRAC (max) can be met. tRCO (max) is specified as a reference point only; if
tRCO is greater than the specified tACO (max) limit, then access time is controlled exclusively by tCAC.
14. Either tRRH or tRCH must be satisfied for a read cycle.
15. These parameters are referenced to CAS leading edge in random write cycles and to WA ITE leading edge in delayed write or readmodify-write cycles.
16. twcs, tcwo, and tRWO are not restrictive operating parameters. They are included in the data sheet as electrical characteriistics only: if twcs C:: twcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance)
throughout the entire cycle; if tCWD",tCWD (mini and tRWD>:tRWD Iminl, the cycle is a read-write cycle and the data out will
contain data read from the selected celi; if neither of the above sets of conditions is satisfied, the condition of the data out (at
access time) IS indeterminate.
17. Addresses, data-in and WRITE are don't care. Data-out depends on the state of CAS. If CAS remains low, the previous output
will remain valid. CAS is allowed to make an active to inactive transition during the pin #1 refresh cycle. When CAS is brought
high, the output will assume a high-impedance state.
18. toff (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels.
2-59
•
•
MCM6664
PIN ASSIGNMENT COMPARISON
MCM4516
VSS
N/C
VSS
REFRESH
D
CAS
D
CAS
D
W
W
Q
Q
3
14
Q
4
13
A6
AO
A3
AO
A3
AO
A2
A4
A2
A4
A2
A5
A1
10
A5
N/C
VCC
N/C
VSS
REFRESH
D
CAS
D
VCC
8
9
Q
RAS
AO
A2
6
A1
VCC
8
W
A6
RAS
3
12
A3
11
A4
10
A5
9
A7
VCC
8
16
VSS
N/C
CAS
D
'.
VSS
15
14
Q
13
A6
RAS
4
A6
MCM6665
MCM6684
W
6
N/C
8
1.
VSS
CAS
W
A6
A6
16
15
RAS
RAS
Al
RAS
1.
MCM6632
MCM4517
REFRESH
A3
AO
5
12
A3
AO
11
A4
A2
6
11
A4
A2
10
A5
Al
10
A5
Al
9
A7
VCC
9
A7
VCC
8
CAS
W
Q
A3
6
8
11
A4
10
A5
9
A7
PIN VARIATIONS
Pin Number
MCM4116
MCM4516
MCM4517
MCM6632
MCM6663
MCM6664
1
VBBI-5 VI
REFRESH
N/C
REFRESH
N/C
REFRESH
8
9
VDDI+ 12 VI
VCC
VCC
VCCI+5 VI
N/C
N/C
VCC
A7
VCC
A7
VCC
A7
On-Chip Refresh Featuresl Benefits
Reduce
Reduce
Reduce
Reduce
System
System
System
System
Refresh Controiler Design Problem
Parts Count
Noise Increasing System ReHa.bility
Power During Refresh
2-60
MCM6666
N/C
VCC
A7
MCM6664
,
READ CYCLE TIMING
tRC
tRAS
tAR
VIH
RAS
VIL
-
tRSHtCAS
VIH
CAS
Addresses
~------------tRAC------------~
VOH
Q IData Out) VOL - - - - - - - - - - - - H i g h Z - - - - - - - - - < I
tOFF
Valid
Data
~-~::..--r
WRITE CYCLE TIMING
,
...
...
VIH
RAS
tRC
tRAS
tAR
VIL
'L-
I
~tRC
VIH
CAS
tRAH
~
VIL
W
.....
..IIf.t1 tASC~ f4--
tASR (--
VIH .,.......
Addresses
tCAS
Row
Address
~
Column
I
VIH XXX. lXX.
AX.
VIL
twcs
4- t
~
wC'R'--I
I
I
!
tCAH
tt:lXXXY.
"\
:AXA
-
tCWL
f.tWCf+!'J
I twp I
Rx
lXlXXXX.
tRWL
I--tDS ~tDH=--'
~
VIH
VIL
~
t--t CRP- - '
V
Address
I
o IData Inl
I
~ \
VIL
LtRP--"
tRSH
tCSH
Valid
Data
\X
~X.lX.
tDHR
Q lData OutJ
VOH
------------------High
VOL
2-61
Z----------------
MCM6664
SELF REFRESH MODE (Battery Backup)
(SEE NOTE 171
\r------l\
tFBR
VIH
--1'---------
-_----------..1
AUTOMATIC PULSE REFRESH CYCLE - SINGLE PULSE
(SEE NOTE 17)
VIHMr~~-------------------------------------------~
~-----------tFRD-----------~~
tRFD
~-------------·tFP------------------~
AUTOMATIC PULSE REFRESH CYCLE - MULTIPLE PULSE
(SEE NOTE 17)
VIHnr~4r----------------~~--------------------~
.-----~
tFS R
RAS-ONL Y REFRESH CYCLE
(Data-In and WRITE are Don't Care, CAS is HIGH)
~---------------"tRC---------~---~
VIHiI7"'l7'V'V'V'V'-
ADDRESSES,
AO-A6
2-62
MCM6664
READ-WRITE/READ-MODIFY-WRITE CYCLE
i
IRWC
RAS
VIH
tRAS
~
tAR
VIL
tRSH
tCSH
tCAS
CAS
VIH
VIL
VIH
Addresses
VIL
Address
~------;----,-I-tRWD-------_"
~--tCWD----____~
VIH
W
VIL
D lData Inl
2-63
II
MCM6664
MCM6664 BIT ADDRESS MAP
~:~~~~~e~: ~
Pin 8
o
:::::: :i :~ :~ AO
Row
Column Addresses
Hex
FF
Fe
FO
FA
Fa
F8
F9
Dec
254
255
252
253
250
251
248
249
A7
1
1
1
1
1
1
1
1
82
83
80
81
130
131
128
129
1
1
1
1
7F
7E
70
127
126
125
~H
•
··
··
··
···
·
··
·
~:::o8
~~
~~
0500
00
~
··
·
···
§§§~
~
88
4
3
2
1
0
04
03
02
01
00
W~
W~
~~
~iQ
"'~
NN.
0_
0_
00..-.-00..-.-0
--
--
0..--00..-.-00
--
-00000000
----
----
A3
1
1
1
1
1
1
1
1
A4
1
1
1
1
1
1
1
1
A5
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
a
0
0
0
0
1
1
1
1
1 ·1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
a
1
1
1
0
0
0
a
a
~8t:i~;g~858
~~
......
AS
1
1
1
1
1
1
1
1
eOOter--o.n..,.N(")...-Q
--
0
--
........... . . - . - 0 0 0 0
000000000
--
000000000
--
000000000
00
000000000
Data Stored - Din" AOX" A1Y
Column
Row
Address
Al
Address
AO
Stored
0
0
0
Inverted
True
0
Data
True
Inverted
2-64
A2.
1
1
1
1
0
0
AD
1
1
0
0
1.
1
0
At
1
1
0
0
a
1
1
0
1
0
1
0
1
1
a
a
1
a
1
a
1
a
a
a a 1
0
a
0
0
1
1
1
1
0
0
0
0
1
0
1
0
1
a 1
a a
®
MOTOROLA
MCM6665
65,536-BIT DYNAMIC RAM
The MCM6665 is a 65,536 bit, high-speed, dynamic Random-Access
Memory. Organized as 65,536 one-bit words and fabricated using
HMOS high-performance N-channel silicon-gate technology. This new
breed of 5-volt only dynamic RAM combines high performance with low
COS! and improved reliability.
By multiplexing row- and column-address inputs, the MCM6665 reQUires only eight address lines and permits packaging in standard 16-pin
dual-in-line packages. Complete address decoding is done on chip with
address latr-hes incorporated. Data out is controlled by CAS allowing
for greater system flexibility.
All inputs and outputs, including clocks, are fully TTL compatible .
The MCM6665 incorporates a one-transistor cell design and dynamic
storage techniques.
• Organized as 65,536 Words of 1 Bit
• Single + 5 V Operation
• Fast 150 ns Operation
• Low Power Dissipation
275 mW Maximum IActive)
30 mW Maximum IStandby)
•
•
•
•
MOS
IN-CHANNEL, SILICON-GATEI
65,536-BIT
DYNAMIC RANDOM ACCESS
MEMORY
..~
L SUFFIX
CERAMIC PACKAGE
CASE 600
Three-State Data Output
Internal Latches for Address and Data Input
Early-Write Common 1/0 Capability
16K Compatible 128-Cycle, 2 ms Refresh
PIN ASSIGNMENT
N/C·
• RAS-only Refresh Mode
• CAS Controlled Output
• Upward Pin Compatible from the 16K RAM IMCM4116, MCM4517)
BLOCK DIAGRAM
D
W
'i'i'J'"i6~
15
VSS
PCAS
14p
Q
i'i7iS
13
PA6
A3
AD
12
A2
"t!A4
A1
10
A5
VCC ' -_ _-' A7
Precharg
Clock
...
A 1-11
~
~
A3
~
A4
5
~
i
A6
~
•
~
<;
0
16.384 Bit Memory
Array
'"
~
§
16, 384-Bit Memory
u
Array
a
~
~
~
~
A5
A7
PIN NAMES
D
j
A2 -II
'•.
'•.
~
Sense Amplifier
"~
'
AD
• For maximum compatibility with MCM6632 and
MCM6664 a VCC trace should go to pin #1.
,-Sense Amphfier
1/211 of 2561
Coh:Jmn Decoder
IX>
"
16.384-Bit Memory
Array
""
recharg
Clock
1/2 Cell
Logic
~0
frl
0
~
1/2 II of 2561
Column Decoder
1+-1Write,W
e 1--1Data In, D
g
!+-II' ~
~
u
g>
16.3tW-Bit Memory
Array
II-t
E
;::
~
--
~
a
Sense Amplifier
~
Sense Amplifier
'--
AD-A7 .......................... Address Input
O.......................................... Oata In
Q ........................................ Oata Out
W............................ Read/Write Input
RAS ..................... Row Address Strobe
CAS.
.. ........ Column Address Strobe
VCC..
.Power 1+5 VI
VSS....
.. .... Ground
Output
Data, Q
This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however,
it is advised that normal precautions be
taken to avoid application of any voltage
higher than maximum rated voltages to
this high-impedance circuit.
OS9824/9-80
2-65
•
II
MCM6665
FIGURE 1 - OUTPUT LOAD
5V
ABSOLUTE MAXIMUM RATINGS ISee Note)
Rating
Symbol
Value
Unit
Voltage on Any Pin Relative to VSS IExcept VCC)
Vin.
v out
- 2 to + 7
V
Voltage on VCC Supply Relative to VSS
Vin, Vout
Tstg
-1 to +7
V
-65 to + 150
°c
1
50
mA
Storage Temperature Range
Power Dissipation
Po
Data Out Current
lout
970 Il
o-......- ......---too-.......
W
100 pF'
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
·'ncludes Jig Capacitance
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted.)
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
MCM6666L 151 MCM6665L20
MCM6665LI5-5/MCM6665L20-5
Supply Voltage
VCC
VCC
VSS
Min
4.5
4}5
0
Typ
Max
Unit
Notes
5.0
5.0
0
5.5
5.25
0
V
1
1
VCC+l
0.8
V
1
V
1
Logic 1 Voltage, All Inputs
VIH
2.4
-
Logic 0 Voltage, All Inputs
VIL
-2.0
-
DC CHARACTERISTICS IFull Operating Voltage and Temperature Ranges Unless Otherwise Notedl
Symbol
Min
Max
Units
Notes
VCC Power Supply Current ItRC min.1
ICCI
-
50
mA
4
Standby V CC Power Supply Current
ICC2
-
5
mA
5
VCC Power Supply Current During ~ Only Refresh Cycles
ICC3
-
40
mA
-
Input Leakage Current lany inputl 10:sVins5.51 IExcept Pin II
IIiU
-
10
I'A
-
Output Leakage Current IOsVouts5.5I1CAS at Logic II
IOIU
-
10
Output Logic 1 Voltage @ lout = - 4 mA
VOH
2.4
-
I'A
V
Output Logic 0 Voltage @ lout=4 mA
VOL
-
0.4
V
-
Characteristic
AC OPERATING CONDITIONS AND CHARACTERISTICS
ISee Notes 2, 3, 6, and Figure 1I
IRead, Write, and Read-Modify-Write Cyclesl
IFull Operating Voltage and Temperature Range Unless Otherwise Notedl
Parameter
Symbol
MCM6665-15
Min
Max
MCM6665-20
Units
Min
Max
Read Write Cycle Time
tRWC
300
300
-
Access Time from Row Address Strobe
Access Time from Column Address Strobe
tRAC
-
tCAC
-
150
75
-
200
110
Output Buffer and Turn-Off Delay
tOFF
0
30
Row Address Strobe Precharge Time
tRP
tRAS
120
-
0
140
150
10000
tCAS
75
Row to Column Strobe Lead Time
tRCD
30
10000
75
Row Address Setup Time
0
Row Address Hold Time
tASR
tRAH
Column Address Setup Time
Column Address Hold Time
tASC
0
tCAH
45
tAR
tT
Random Read or Write Cycle Time
tRC
Row Address Strobe Pulse Width
Column Address Strobe Pulse Width
Column Address Hold Time Referenced to RAS
Transition Time I Rise and Falll
2-66
350
-
350
ns
8.9
ns
ns
8.9
ns
10. 12
11. 12
40
ns
17
-
ns
-
200
110
10000
ns
-
10000
35
90
ns
ns
13
0
-
ns
-
30
55
155
-
120
-
-
ns
ns
3
50
3
50
ns
25
Notes
0
ns
ns
-
6
MCM6665
AC OPERATING CONDITIONS AND CHARACTERISTICS
ISee Notes 2, 3, 6, and Figure 1)
IRead, Write, and Read-Modify-Write Cycles)
IFull Operating Voltage and Temperature Range Uriless Otherwise Noted)
Parameter
Symbol
Read Command Setup Time
tRCS
tRCH
tRRH
Read Command Hold time
Read Command Hold Time Referenced to RAS
Write Command Hold Time
Write Command Pulse Width
Write Command to Row Strobe Lead Time
Write Command to Column Strobe Lead Time
Data in Setup Time
Data in Hold Time
MCM6665-20
Min
Max
Min
Max
0
10
-
0
10
-
35
55
30
45
tWCR
twp
120
tRWL
tCWL
45
tDS
0
tDH
-
tWCH
Write Command Hold Time Referenced to RAS
MCM6666-15
45
45
155
Units Notes
-
ns
-
ns
14
ns
14
-
ns
-
ns
ns
-
-
55
55
55
0
-
ns
ns
ns
-
15
-
ns
ns
15
ns
-
-
Data in Hold Time Referenced to RAS
tDHR
45
120
Column to Row Strobe Precharge Time
tCRP
-10
-
55
155
-10
RAS Hold Time
tRSH
75
-
110
-
ns
Refresh Period
WRITE Command Setup Time
CAS to WRITE Delay
tRFSH
-
2.0
-
2.0
ms
ns
-
twcs
-10
-
-10
-
45
16
160
-
ns
125
ns
16
CAS Hold Time
tCSH
150
-
55
RAS to WRITE Delay
tcwo
tRWD
200
-
ns
-
16
CAPACITANCE If= 10 MHz TA=25'C VCC=5 V Periodically Sampled Rather Than 100% Testedl
Parameter
Input Capacitance IAO-A7I, D
Input Capacitance
R1\S, CAS, WI1T'ft
Output Capacitance 101 ICAS = VIH to disable output)
Symbol
Typ
Max
Units
CI1
4
5
pF
7
CI2
8
10
pF
7
Co
5
7
pF
7
Notes
NOTES:
1. All voltages referenced to VSS.
2. V1H min and VIL max are reference levels for measuring timing of input signals. Tran~ition times are measured between V1H and
VIL·
3. An initial pause of 100 Jls is required after power-up followed by any 8 RAS cycles before proper device operation guaranteed.
4. Current is a function of cycle rate and output loading; maximum current is measured at the fastest cycle rate with the output
open.
5. Output is disabled lopen-circuit) and RAS and CAS are both at a logic 1.
6. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input 5ig·
nals must transmit between VIH and VIL (or between VIL and VIH) in a monotonic manner.
7. Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C= ~
8. The specifications for tAC (min), and tRWC (min) are used only to indicate cycle time at which proper operation over the full tern·
perature range (0°CSTAS70°C) is assured.
9. AC measurements assume tT = 5.0 ns.
10.
11.
12.
13.
14.
15.
16.
17.
Assumes that tRCDStRCD Imaxl.
Assumes that tRCD"'tRCO Imaxl.
I Measured with a current load equivalent to 2 TTL loads 1+200 ~A, -4 rnA) and 100 pF IVOH= 2.0 V, VOL = -0.8 VI.
Operation within the tACO (max) limit ensures that tRAG (max) can be met. tRCO (max) is specified as a reference point only; if
tRCD is greater than the specified tRCD Imaxl limit, then access time is controlled exclusively by tCAe.
Either tRRH or tRCH must be satisfied for a read cycle.
These parameters are referenced to CAS leading edge in random write cycles and to WAITE leading edge in delayed write or read~
modify-write cycles.
tWGS. tCWD, and tAwn are not restrictive operating parameters. They are included in the data sheet as electrical characteri~
istics only: if twcs~twcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance)
throughout the entire cycle; if tCWD",tCWD Iminl and tRWD",tRWD Imin), the cycle is a read-write cycle and the data out will
contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at
access time) is indeterminate.
toft (max) defines the time at which the output achieves the open circuit condition and is not refp,renced to output voltage levels.
2-67
•
•
MCM6665
PIN ASSIGNMENT COMPARISON
REFRESH
VSS
N/C
D
CAS
D
a
A6
AO
'.
MCM4517
16
'.
MCM6632
2
15
VSS
CAS
W 3
RAS 4
14
a
REFRESH
D
VSS
2
CAS
W 3
RAS 4
A6
A3
13
A6
A3
AO
5
12
A3
AO
5
A2
6
11
A4
A2 .6
11
A4
A2
6
A4
Al
7
10
A5
Al
7
10
A5
Al
7
A5
VCC
8
9
N/C
VCC
8
9
N/C
VCC
8
A7
VSS
REFRESH
VSS
N/C
CAS
D
CAS
D
a
W 3
MCM6633
N/C
a
2
W 3
RAS 4
A6
VCC
'.
MCM6664
A3
AO
5
A4
A2
6
A5
A1
A7
VCC
'.
MCM6665
m
A6
4
16 Vss
15
CAS
14
a
13
A6
A3
A3
AO
12
11
A4
A2
11
A4
10
A6
A1
10
AS
9 A7
VCC
9
A7
8
PIN VARIATIONS
Pin Number
1
8
9
MCM4116
VBB(-5 VI
VDD(+12 VI
VCC(+5 VI
MCM4516
REFRESH
MCM4517
MCMS832
MCM6683
MCM8664
MCM8111111
N/C
~
N/C
~
VCC
VCC
N/C
VCC
A7
VCC
A7
N/C
VCC
N/C
VCC
A7
2-68
A7
MCM6665
,
READ CYCLE TIMING
tRC---
tRAS
RAS
tAR
VIH
VIL
•
tRSH-
CAS
tCAS
VIH
VIL
Addresses
VIL
W
VIH
~tCAC
VIL
tRAC
Q IData Out!
VOH
tOFF
Valid
High Z
VOL
Data
,
WRITE CYCLE TIMING
tRC
tRAS
VIH
tAR
RAS
VIL
~
I
tRSH
L t RP- '
tCSH
tCAS
Ioi--tRC
VIH
CAS
VIL
tASR
VIH
Addresses
VIL
W
r
~
_
tRAH
~ tASC-!"
Row
Address
~
~
:n.
I
-Ill
I
tRWLI
~
'--ll-tDSl4--tDH~
VIH
VIL
,'Mx.
'\..".
./
~\tI'x.~rx .~
tCWL
4-tWCR
o (Data Inl
I
j.tWCH!I
I twp I
VIL
t--t CRP-
V
. . . tCAH
Column
Address
I I
twcs
VIH
I
\
\
Valid
Data
~x.
~x
OUt
~>
ex.
tDHR
Q (Data Outl
VOH
------------------HighZ----------------
VOL
2-69
MCM6665
RAS-ONL Y REFRESH CYCLE
I Data-in and "Writ. are Don't Cara, CAs is HIGH)
j 4 - - - - - - - - t R C - - - - - - - - -...
•
Addresses,
AO-A6
l-tCAC~
w
'=:i",-rJ
Q"~ ,., ::: ~----.:.~--------tR-A-C---"'" ~~
o lData In),
r
tOFF
~
1itIOOOOOOOOOOO
V~
IH
D~~
VIL
2-70
MCM6665
MCM6666 BIT ADDRESS MAP
Pin 8
Row Address A7 A6 A5 A4 A3 A2 A 1 AD
Column Address A7 A6 A5 A4 A3 A2 Al AD
D
Row
Column Addresses
Hex
FE
Ff
Fe
fD
FA
FB
FB
F9
Doc
254
255
252
253
250
251
248
249
A7
1
I
1
1
1
I
I
I
AS
1
I
I
I
I
1
I
1
1>3 A4 A5 1>2 AD A1
I
1
1
I
I
0
I
I
I
1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
82
83
BO
81
7F
7E
130
131
12B
129
I
I
I
I
127
126
125
0
0
0
0
0
0
0
1
I
1
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
··
··
··
7D
~
·
···
··
···
···
~:::58
~
5585
55
·
04
§§§~
88
~
r
I
W~
~~
~
W
~
~~
c ~~
"'~
NN.
;{
0_
0_
~ ~
--
---
~
0:
:;:
--
!f1 -::I - -
-~-~D< - "~
......
4
3
2
1
0
03
02
01
00
1
I
1
0
0
0
0
0
0
I
I
0
0
0
I
0
I
0
I
0
0
0
0
0
0
0
0
0
0
0
0
I
I
0
0
0
I
0
I
1
1
1
1
1
1
I
I
I
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
I
1
0
0
0
I
0
I
0
I
1
I
1
I
~8b:gSB858
.CO<.Or--
E
f+ Output
Data, Q
m
........
16,384-Bit Memory
;::
Array
g
(;
Sense Amplifier
-
PIN NAMES
. ........... Address Input
. .. Data In
. ....... Dato Out
W......
............. Aead/Write Input
RAS.. ............. Aow Address Stroba
CAS
.Column Address Strobe
VCC
..................... Power 1+5 VI
VSS ................................... Ground
AD-A7..
D....
D...
0
u
'"
~
-.
~
"0
~
"0
CD
~IRAS
;;
~
"S
recharg
Clock
112 Cell
Logic
eg
u
-
~
~
"0
16, 384-8.t Memory
Array
(;
~
!::
"'.
~
A5
A7
'VCC1 does not draw any current but
must be tied to VCC to inactivate inter-
..-
~
-.
... !
...
... .
A5,
A6
recharg
Clock
VCC
Sense Arnplifier
-
This device contains circuitry to protect the inputs against damage due to high static voltages
or electriC fields; however, it is advised that normal precautions be taken to avoid application of
any voltage higher than maximum rated voltages
to this high-impedance circuit.
089836/11-80
2-72
MCM6665L25
ABSOLUTE MAXIMUM RATINGS (See Notel
Rating
Symbol
Value
Voltage on Any Pin Relative to VSS (Except VCCI
Vin, Vout
-2 to + 7
V
Voltage on VCC Supply Relative to VSS
Vin. Vout
-1 to +7
TA_
Tsta
O to +50
V
DC
-66 to +150
DC
Power Dissipation
Po
1.0
W
Data Out Current
lout
50
mA
Operating Temperature Range
Storage Temperature Range
FIGURE 1 - OUTPUT LOAD
5V
Unit
970 !l
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
-Includes Jig Capacitance
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted,)
RECOMMENDED OPERATING CONDITIONS
Parameter
Min
4.5
0
2.4
Typ
5.0
0
Max
5.5
0
Unit
Notes
V
1
Logic 1 Voltage, All Inputs
Svmbol
VCC
VSS
'IIH
-
VCC+ 1.0
V
1
Logic 0 Voltage, All Inputs
VIL
-2.0
-
0.8
V
1
Supply Voltage
MCM6665L25
DC CHARACTERISTICS
Symbol
Min
Max
Unit
Nota.
VCC Power Supply Current (tRC min.1
ICC
-
50
mA
4
Standby V CC Power Supply Current
ICC2
-
5
mA
5
VCC Power Supply Current During i'fiiS Only Refresh Cycles
Input Leakage Current tany input I (Os Vin S 5.51 (Except Pin 11
ICC3
II(L)
-
40
mA
-
10
fl.A
Input Leakage Current (Pin 11 (Vin = VCCI
II(L)
10
fl.A
Output Leakage Current (Os VoutS 5.51 (Except Pin 11
IO(L)
-
-
10
Output Logic 1 Voltage @ lout = - 4 mA
VOH
2.4
-
fl.A
V
Output Logic 0 Voltage @ lout = 4 mA
VOL
-
0.4
V
Characteristic
5,6
-
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full Operating Voltage and Temperature Range Unless Otherwise Notedl
(See Notes 2, 3, 9, 141
(Read, Write, and Read-Modify-Write Cycles)
Max
Unit
Notes
ns
8,9
Symbol
Min
tRC
450
Read Write Cycle Time
tRWC
450
-
ns
8,9
Access Time from Row Address Strobe
tRAC
-
250
ns
10,12
Access Time from Column Address Strobe
tCAC
-
145
ns
11,12
Output Buffer and Turn-Off Delay
0
50
ns
17
Row Address Strobe Precharge Time
tOFF
tRP
190
-
ns
-
Row Address Strobe Pulse Width
tRAS
250
10000
ns
-
Column Address Strobe Pulse Width
tCAS
145
10000
ns
-
Row to Column Strobe Lead Time
tRCO
55
105
ns
13
-
ns
Parameter
Random Read or Write Cycle Time
Row Address Setup Time
tASR
0
Row Address Hold Time
tRAH
45
Column Address Setup Time
tASC
0
Column Address Hold Time
tCAH
75
tAR
200
-
ns
-
tT
3.0
50
ns
6
Column Address Hold Time Referenced to RAS
Transition Time (Rise and Falll
2-73
ns
ns
-
ns
II
MCM6665L25
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full Operating Voltage and Temperature Range Unless Otherwise Notea)
(See Notes 2, 3, 9, 14)
(Read, Write, and Read-Modify-Write Cycles)
Symbol
Min
Max
Read Command Setup Time
tRCS
0
Read Command Hold Time
tRCH
10
-
Parameter
Read Command Hold Time Referenced to
RAS
tRRH
40
Write Command Hold Time
tWCH
75
Write Command Hold Time Referenced to RAS
tWCR
200
Write Command Pulse Width
twp
70
Write Command to Row Strobe Lead Time
tRWL
70
Write Command to Column Strobe Lead Time
tCWL
70
Data in Setup Time
tos
0
Data in Hold Time
tDH
75
Data in Hold Time Referenced to~ .
tDHR
200
Column to Row Strobe Precharge Time
tCRP
-10
RAS
tRSH
Units Notes
ns
-
ns
14
ns
14
ns
-
ns
ns
-
-
ns
-
ns
-
ns
15
ns
15
ns
-
ns
-
145
-
ns
-
tRFSH
--
2.0
ms
twcs
-10
ns
16
CAS to WRITE Delay
tCWD
70
ns
16
RAS to WfI1i'E Delay
tRWD
195
ns
16
CAS Hold Time
tCSH
250
-
ns
-
Hold Time
Refresh Period
_~RI.!E Command Setup Time
CAPACITANCE (f= 10 MHz
Input Capecitance (AO-A71,
Input CapaCitance RAS,
TA=25°C VCC=5 V Periodically Sampled Rather Than
Parameter
0
CAS, WRITE
Output Capacitance (01
100%
Testedl
Symbol
Typ
Max Units
Notes
Cil
4.0
5.0
pF
7
CI2
8.0
10.0
pF
7
Co
5.0
7.0
pF
7
NOTES
All voltages referenced to V S S.
VIH mm and VIL max are reference levels for ,neasunng timing of Input Signals Transition times are measured between VIH and
VIL
_
3. An Initial pause of 100 1'5 IS reqUired after power-up foHowed by any 8 RAS cycles before proper deVice operation guaranteed.
4. Current I~ a function of cycie rate and output loading; maximum current IS measured at the fastest cycle rate with the output
open
5. Output IS disabled (open-clrcuIO and RAS and CAS are both at a logiC 1
6 The transition time specification applies for all Input Signals. In addition to meeting the tlcHlSltlon rate speCification, alllnpul signals must transmit between VIH and VIL (or between VIL and VI H) In a monotoniC manner
7. Capacitance measured with a Boonton Meter or effective capacitance calculated from the eQuatlor>' C = ~
8. The specifications for lAC (min!, and tAWC (min) are used only to Indicate cycle time at which proper operation ovel the full tempelature range (Q°C~ T A~ 70°C) IS assured.
9. AC measurements assume tT = 5.0 llS.
10. Assumes that tACO S; tACO (max).
11. Assumes that tRCD'" tRCD Imaxl.
12. Measured with a current load equivalent to 2 TTL loads (+ 200 pA, - 4 mAl and 100 pF IVOH = 2.0 V, VOL = - 0.8 VI.
13. Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCO (max) is specified as a reference point only; If
tACO is greater than the specified tRCO (max) limit, then access time IS controlled exclusively by tCAC.
14. Either tARH or tRCH must be satisfied for a read cycle.
15. These parameters are referenced to CAS leading edge in random write cycles and to"WRii'I leading edge Irl delayed write or readmodify-write cycles.
16. tWCS. tCWO. and tRWO are not restrictive operating parameters. They are tncluded in the data sheet as electrical characteriistics or,ly' if twcs~twcs (min). the cycle is an early write cycle and the data out pin will femam open Circuit (high Impedance)
throughout the entire cycle; if tcWO~tCWD (minl and tRWD~ tRWO (min), the. cycle is a read-write cycle -:md the data out will
contain data read from the selected cell; if neither of the above sets of conditions is satIsfied, the condition of the data out (at
access time) is indeterminate.
17. toft (max) defines the tIme at which the output achieves the open circuit condition and is not referenced to output voltage levels.
2-74
MCM6665L25
PIN ASSIGNMENT COMPARISON
REFRESH
MCM4516
16
VSS
N/C
D
15
CAS
D
W
14
a
13
A6
RAS
MCM6632
MCM4517
16
VSS
REFRESH
2
15
CAS
D
W 3
14
a
4
13
A6
1.
1.
VSS
CAS
a
W
A6
12
A3
AO
12
A3
AO
12
A2
11
A4
A2
6
11
A4
A2
11
A4
A1
10
A5
A1
7
10
A5
10
A5
9
A7
N/C
VCC
16
VSS
REFRESH
D
15
W
A3
N/C
VCC
VSS
N/C
VSS
CAS
CAS
D
CAS
14
a
a
13
A6
A6
12
A3
AO
5
12
A3
AO
12
A2
A4
A2
6
11
A4
A2
11
A4
A1
A5
A1
10
A5
A1
7
10
A5
VCC
A7
VCC
9
A7
Vcc
8
9
A7
VCC
9
MCM6633
N/C
RAS
AO
1.
4
MCM6665
8
a
W
A6
A3
PIN VARIATIONS
Pin Number
MCM4116
MCM4616
MCM4617
MCM6632
MCM6663
MCM6664
MCM6666
1
VBBI-5 VI
VDDI+ 12 VI
VCCI+5 VI
REFRESH
N/C
REFRESH
N/C
REFRESH
N/C
VCC
VCC
N/C
N/C
VCC
A7
VCC
A7
VCC
A7
VCC
A7
8
9
2-75
MCM6665L25
Addresses
o IData Out)
VOH
VOL - - - - - - - - - - - -
,
WRITE CYCLE TIMING
""'-
tAR
RAS
VIL
I
,~
tRAH
tASR
I
VIH
Addresses
VIL
W
I-H1tAS~-I j4Row
Address
VIH [XJU<.N(
~
I
twp
I
--
I
tRWL
I
,/
ex III (X
tCWL
I
I
tCAH
I I
~
VIL
14--
/
Column
Address
' ViJ!iIT
twcs
!4-tCRP- .
tCAS
1\ \
VIL
l-tRP~ i"'-----
tRSH
tCSH
ioi--- tRC
VIH
CAS
tRC
tRAS
VIH
''\
-
joetw~_
:X[)\.
Ill(
..r
'--l 14-tDS~tDH::::':"
j4---tWCR
o IData In)
VIH
J(
Valid
Data
ll\..
VIL
tDHR
Q IData Out)
VOH
VOL
~y:
--
~
[XX lX
[ltlXX
ll\..lXJI.Y
-----------------HiQhZ---------------2-76
MCM6665L25
RAS-ONL Y REFRESH CYCLE
(Data-in and Write are Don't Care, CAS is HIGH)
~------------IRC------------------~
RAS
Addresses,
AD-AB
READ-WRITE/READ-MODIFY-WniTE CYCLE
~-------------------------IRWC--------------------------------
RAS
VIH
. .__________________ tRAS~----------------------------~
~~~-------tAR--------~.,~
VIL
tRSH
tCSH
-----I~r_--_7------·-tCAS----------------~
CAS
VIH
VIL
VIH
Addresses
VIL
Address
~----+--_:_I-tRWD---------Itt
~--tCWD--------~
VIH
W
VIL
2-77
MCM6665L25
MCM6666 BIT ADDRESS MAP
Pin 8
Row Address A7 A6 A5 A4 A3 A2 Al AD
Column Address A7 A6 AS A4 A3 A2 A1 AO
0
Row
•
Column Addressee
Hex
FE
FF
Fe
FD
FA
FB
F8
F9
Dec
82
80
81
130
131
128
129
7F
7E
70
127
128
125
254
255
252
253
250
251
248
249
83
I
~
«
~
~
A7 A6 />:J A4 A5 I>:l AD Al
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
u
~---------------------4----------------.------~~
03
§§§~
+-____________________
L-____________________
02
01
~OO
;WLJ..
I~~
J~~~
~ ~o.-
~ ~ -0 . . - . - . - ..... 0 0 0 0
:tl-::1--
..-00000000
000000000
:2--
000000000
~--
000000000
~D~.-.-
000000000
Dala S1ared - Din" AOX .. A 1Y
Column
Addreoa
A1
a
a
Row
Add""",
AO
a
a
Data
Stored
Inverted
True
True
Inverted
2-78
1
1
0
0
0
1
®
MCM2114
MCM21L14
MOTOROLA
MOS
4096-BIT STATIC RANDOM ACCESS MEMORY
The MCM2114 is a 4096-bit random access memory fabricated with
high density, high reliability N-channel silicon-gate technology. For ease
of use, the device operates from a single power supply, is directly compatible with TTL and DTL, and requires no clocks or refreshing because
of fully static operation. Data access is particularly simple, since address
setup times are not required. The output data has the same polarity as
the input data.
The MCM2114 is designed for memory applications where simple interfacing is the design objective. The MCM2114 is assembled in 18-pin
dual-in-line packages with the industry standard pin-out. A separate
chip select (Sllead allows easy selection of an individual package when
the three-state outputs are OR-tied.
The MCM2114 series has a maximum current of 100 mAo Low power
versions Ii.e., MCM21 L 14 series) are available with a maximum current
of only 70 mAo
IN·CHANNEL, SILlCON·GATE)
4096-BIT STATIC
RANDOM ACCESS
MEMORY
~
••u,'"
~~~ ~ ~ P~STIC
PACKAGE
CASE 707
• 1024 Words by 4-Bit Organization
• Industry Standard 18-Pin Configuration
~.
• Single + 5 Volt Supply
• No Clock or Timing Strobe Required
• Fully Static: Cycle Time = Access Time
• Maximum Access Time
MCM2114-20/MCM21L14-20 200
MCM2114-25/MCM21L14-25 250
MCM2114-30/MCM21L 14-30300
MCM2114-45/MCM21 L14-45450
• Fully TTL Compatible
ns
ns
ns
ns
CERAMIC PACKAGE
CASE 680
• Common Data Input and Output
• Three-State Outputs for OR-Ties
PIN ASSIGNMENT
• Low Power Version Available
A6
'ii'-'Ta~vcc
A5 2
BLOCK OIAGRAM
A9
A4
15
Vee = Pin
3
A6
A7
AS
17
3
16~A8
A3
4
15~A9
AD
5
14~DQ1
Al
6
13~DQ2
A2
7
12
18
VSS=Pin9
Memory Array
~8
64 Row
64 Columns
17~A7
A4
D03
t1DQ4
VSS L-_
9
to....
_
Vi
16
14
DOl
PIN NAMES
D02 13
AO-A9 .......................... Address Input
iN ......
.......... Write Enable
S................................ Chip Select
DQ1-DQ4 ............... Data Input/Output
VCC..
.......
...Power 1+5 V)
VSS ... ............................... Ground
10
W--"--,,
AO A1 A2 A3
DS9800/1-79
2-79
•
•
MCM2114-MCM21 L14
ABSOLUTE MAXIMUM RATINGS ISee Notel
Rating
Temperature Under Bias
Voltage on Any Pin With Respect to VSS
Value
Unit
-10to +80
°C
-0.5 to + 7.0
V
5.0
mA
1.0
Watt
DC Output Current
Power Dissipation
o to
Operating Temperature Range
Storage Temperature Range
+ 70
This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however,
it is advised that normal precautions be
taken to avoid application of any voltage
higher than maximum rated voltages to
this high-impedance circuit .
°c
-66 to + 150
°c
NOTE: Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted.)
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Min
Typ
Max
Supply Voltage
VCC
VSS
4.75
0
5.0
0
5.25
Logic 1 Voltage, All Inputs
VIH
2.0
_.
Logic 0 Voltage, All Inputs
VIL
-0.5
..
Parameter
U
6.0
0.8
Uni
V
V
V
DC CHARACTERISTICS
Parameter
Symbol
Min
MCM2114
Typ Max
.-
10
-
10
MCM21L14
Typ Max
Min
I/O Leakage Current IS=2.4 V, VOO=O.4 V to VCCI
IILOI
-
Power Supply Current IVin-5.5 V, 100-0 mA, TA-25°CI
ICCl
-
80
95
Power Supply Current IVin=5.5 V, 100-0 rnA, TA-O°CI
-
-
100
Output Low Current VOL = 0.4 V
ICC2
IOL
-
2.1
6.0
-
2.1
Output High Current VOH=2.4 V
IOH
-
Input Load Current IAII Input Pins, Yin = 0 to 5.5 VI
III
-1.4 -1.0
-
Unit
-
6.0
-
mA
10
".A
10
66
".A
mA
70
mA
-1.4 -1.0
mA
NOTE: Duration not to exceed 30 seconds.
CAPACITANCE If = 1.0 MHz, T A = 25°C, periodically sampled rather than 100% testedl
Characteristic
Input Capacitance (Vin = 0 V)
Input/Output Capacitance IVDO=O VI
Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C= l.6.t/.6.V.
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature unless otherwise noted.)
Input Pulse Levels
.......................... 0.8 Volt to 2.4 Volts
Input Rise and Fall Times..
. ...................... 10 ns
Input and Output Timing Levels..
'" .1.5 Volts
Output load ................................. 1 TTL Gate and CL = 100 pF
READ (NOTE 1) WRITE (NOTE 2) CYCLES
Parameter
Symbol
MCM2114-20
MCM21 L14-20
Min
Max
MCM2114-25
MCM21 L 14-25
Min
Max
-
450
-
ns
-
450
ns
85
100
-
120
ns
-
20
-
20
-
ns
100
ns
200
-
250
-
tAVOV
200
250
Chip Select Low to Data Valid
tSLOV
70
Chip Select Low to Output Don't Care
tSLOX
20
-
20
Chip Select High to Output High Z
tSHOZ
-
Address Oon't Care to Output High Z
tAXOZ
50
60
-
Write Low to Write High
tWLWH
120
Write High to Address Don't Care
tWHAX
20
Write Low to Output High Z
tWLOZ
-
Data Valid to Write High
tDVWH
120
Write High to Data Don't
tWHDX
0
NOTES: 1. A Read occurs during the overlap of a low S" and a high W
2. A Write occurs during the overlap of a low S and a low W.
2-80
Unit
300
tAVAX
Address Valid to Output Valid
-
MCM2114-45
MCM21Ll4-45
Min
Max
300
-
Address Valid to Address Don't Care
-
MCM2114-30
MCM21 L14-30
Min
Max
80
70
50
-
50
-
135
150
-
200
20
-
20
-
60
-
-
70
-
135
-
150
0
-
0
ns
50
ns
20
-
80
-
100
ns
-
200
0
ns
ns
-
ns
MCM2114-MCM21 L14
READ CYCLE TIMING
i.W HELD HIGH)
14------tAVAX-------i~
~-----tAVOV----------~~
Address
o
WRITE CYCLE TIMING (NOTE 3)
..
tAVAX
Address
~/jllil (1111111111111/
\\\ \ \ \ \ \ \ \ \ \ \ \' l\\\
11
tWLWH
W
o
k\\'\
-
f----tWHAX
V! f
tWLOZ
--
tDVWH
tWHDX
!4----
D
3. If the S low transition occurs simultaneously with the Wlow transition, the output buffers remain in a high-Irnpedance state.
WAVEFORMS
Waveform
Symbol
Input
Qutp"·
MUST BE
VALID
WILL BE
VALID
~
CHANGE
FROM H TO L
WILL CHANGE
FROM H TO L
JlllZ7
CH-,\NGE
FROM L TO H
WILL CHANGE
FROM L TO H
~
DON'T CARE
ANY CHANGE
PERMITTED
:=J-
CHANGING
STATE
UNKNOWN
HIGH
IMPEDANCE
2-81
•
MCM2114-MCM21 L14
TYPICAL CHARACTERISTICS
SUPPLY CURRENT versus SUPPLY VOLTAGE
SUPPLY CURRENT versus AMBIENT TEMPERATURE
80
<
E
...
~
1:l
7·5
...........
............
75
---
70
~
~
~
~
65
j..--t-
~
.........
-
...........
r-..........
...............
.............
50
60
4.5
4.75
5.0
VCC. SUPPLY VOLTAGE (VOLTS)
5.25
o
5.5
OUTPUT SOURCE CURRENT versus OUTPUT VOL TAGE
7.0
1\
5.0
4.0
...~
::>
'"
6.0
3.0
E
3. 0
\
2.0
2.0
\
1.0
1.0
0I
01
\
2.0
80
/
V
I
/
I
/
/
1.
'\
o
/
I
i\
1
\
51
!
/
7.0
i\
w
0
8.0
\
\
\
\
I
'"
::>
'"
60
9.0
6.0
...
20
40
TA. AMBIENT TEMPERATURE IOC)
OUTPUT SINK CURR ENT versus OUTPUT VOL rAGE
8.0
<
E
.........
3.0
4.0
VOH. OUTPUT VOLTAGE (VOLTS)
5.0
6.0
2-82
0.1
0.2
0.3
0.4
VOL. OUTPUT VOLTAGE (VOLTS)
0.5
0.6
MCM2114-MCM21 L14
TYPICAL ACCESS TIME versus TEMPERATURE
NORMALIZED ACCESS TIME versus TEMPERATURE
1.0
,.
g
V
0.95
0.90
Z
/
/v
0
..,.- V
0.85
./
f/
«
~
"j
/
160
V
«
"~
!
/'
~
~
/
/'
;::
v
170
14
0.80
0.7 5
o
20
40
TA. TEMPERATURE lOCI
/'
13 0
20
80
60
°v
V
V
40
60
TA. TEMPERATURE lOCI
80
MCM2114/MCM21 L 14 BIT MAP
PIN lB
PIN 1
Vee
D
D
1023 ....
1007
100B 1023 0(
1007
D03 !PIN NO. 121
15
I{
100B 10230(
1007
D041PIN NO. III
16
0 15
I{
100B 10231{
1007
DOl IPIN NO. 141
16
0 15
D02 IPIN NO. 131
16
0 15
I{
100B
16
0
0(
To determine the precise location on the die of a word in memory. reassign address numbers to the address pins as
in the table below. The bit locations can then be determined directly from the bit map.
REASSIGNED
PIN NUMBER
4
5
ADDRESS NUMBER
-------
PIN NUMBER
A6
A5
A4
A3
AO
6
7
15
16
17
2-83
REASSIGNED
ADDRESS NUMBER
Al
A2
A9
Ali
A7
90
•
®
MCM211SA
MCM21L1SA
MCM212SA
MCM21L2SA
MOTOROLA
1024 x 1 STATIC RAM
MOS
The MCM2115A and MCM2125A families are high-speed, 1024words
by one-bit, random-access memories fabricated using HMOS, highperformance N-channel silicon-gate technology. Both open collector
(MCM2115A) and three-state output (MCM2125AI are available. The
devices use fully static circuitry throughout and require no clocks or
timing strobes. Data out has the same polarity as the input data.
Access times are fully compatible with the industry-produced 1K
Bipolar RAMs, yet offer up to 50% reduction in power over their Bipolar
equivalents.
All inputs and output are directly TTL compatible. The chip select
allows easy selection of an individual device when outputs are OR-tied.
•
•
•
•
•
(N-CHANNEL, SILICON-GATE)
1024-BIT STATIC
RANDOM ACCESS
MEMORY
Organized as 1024 Words of 1 Bit
Single +5 V Operation
Maximum Access Time of 45 ns, 55 ns, and 70 ns available
Low Operating Power Dissipation
Pin Compatible to 93415A (2115A) and 93425A (2125A)
C SUFFIX
• TTL Inputs and Outputs
• Uncommitted Collector (2115A) and Three-State (2125A) Output
FAIT-SEAL
CEAAMIC PACKAGE
CASE 620--06
BLOCK DIAGRAM
PIN ASSIGNMENT
S
le'J""i'6
AI
A2
0
A..
X
Output
2115A Family
Q
X
H
L
L
L
H
L
L
L
H
H
H
Data Out
X
14
W
13
A9
A3
12
AS
A4 6
11
A7
0
10 A6
VSS
A5
PIN NAMES
TRUTH TABLE
Inputs
W
0
4
A5 A6 A7 AS A9
AD AI A2 A3 A4
S
H
Vce
15 0
AD
D ..
Output
2125A Family
Q
High Z
High Z
Mode
0 ...
Not Selected
Write "0"
Vee·
High Z
Write" 1"
Data Out
Read
s.
VSS .
w..
........ Address
. ... Data Input
Data Output
. . . . . . . . . . . . . . .. ehip Select
+5V Supply
.................. Ground
. ... Write Enable
058819/5-80
2-84
MCM2115A-MCM21 L 15A-MCM2125A-MCM21 L25A
ABSOLUTE MAXIMUM RATINGS ISee Notel
Rating
Temperature Under Bias
Voltage on Any Pin With Respect to VSS
Value
Unit
-lOto +80
'c
-0.5 to + 7.0
Vdc
DC Output Current
20
rnA
Power Dissipation
1.0
Watt
o to
Operating Temperature Range
Storage Temperature Range
NOTE:
+ 70
-65to +150
This device coma ins circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it IS advised that normal prE!cautions be taken to avoid application of
any voltage higher than maximum rated voltages
to this high-impedance circuit.
'c
'c
Permanent damage may occur if ABSOLUTE MAXIMUM RATINGS
are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time CQuid affect device
reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted,)
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Min
Typ
Max
Unit
Supply Voltage
VCC
VSS
4.75
0
5.0
0
5.25
0
V
Logic 1 Voltage, All Inputs
VIH
2.1
-
6
V
Logic 0 Voltage, All Inputs
VIL
-0.3
-
0.8
V
Parameter
DC OPERATING CHARACTERISTICS
Symbol
Parameter
Input Low Current IAII Input Pins, Vin ~ 0 to 5.5 VI
IlL
Input High Current
IIH
Output Leakage Current
(Vout~0.5/2.4
Output Leakage Current
IVout~4.5
VI
VI
Power Supply Current IS - VIL, Outputs Open T A ~ 25'CI
Output Low Voltage IIOL - 7.0 rnA, 2125A, 16 rnA 2115AI
10L
ICEX
ICC
VOL
Output High Voltage IIOH ~ - 4.0 mAl
VOH
Current Short Circuit to Ground
lOS
MCM2115A MCM21L15A MCM2125A MCM21L25A
Min
-
Min
-
Max
-40
40
100
125
0.45
-
Max
-40
-40
~A
40
-
40
~A
50
-
50
~A
-
~A
-
75
rnA
0.45
-
0.45
V
-
2.4
-
V
-
-100
rnA
Min
Max
-40
-
125
0.45
-
-
2.4
-
-
40
100
75
Unit
Min
-
Max
-
-100
MCM2115A FAMILY AC OPERATING CONDITIONS AND CHARACTERISTICS, READ, WRITE CYCLES
(TA -0
- to 70'C VCC-5 0 V ±5%1
MCM2115A-45 MCM2115A-55 MCM2115A-70
Units
Symbol
Parameter
Max
Min
Max
Min
Max
Min
-
Chip Select Low Output Valid
tSLQV
5
Chip Select High to Output Invalid
tSHOZ
Address Valid to Output Valid
tAVQV
-
Address Valid to Output Invalid
tAVQX
Write Low to Output Disable
Write High to Output Valid
Write Low to Write High IWrite Pulse Width I
tWLWH
Data Valid to Write Low
tDVWL
Write High to Data Don't Care IData Holdl
tWHD)!'
5
Address Valid to Write Low (Address Setupl
tAVWL
5
Write High to Address Don't Care
tWHAX
5
Chip Select Low to Write Low
tSLWL
5
Write High to Chip Select High
tWHSH
5
Address Valid to Address Don't Care
tAVAX
Chip Select Low to Chip Select High
tSLSH
-
30
30
5
35
35
-
40
40
-
70
ns
10
-
ns
5
ns
45
-
10
-
10
55
-
tWLQZ
-
30
-
36
40
ns
tWHQV
0
30
0
35
0
45
ns
30
-
40
5
-
ns
-
-
50
5
-
ns
-
5
-
ns
45
-
70
ns
70
ns
2-85
45
5
5
5
5
5
5
5
15
5
5
55
55
-
ns
ns
ns
ns
ns
•
MCM2115A-MCM21 L15A-MCM2125A-MCM21 L25A
MCM21LI5A FAMILY AC OPERATING CONDITIONS AND CHARACTERISTICS, READ, WRITE CYCLES
(TA=Ot070·C VCC=50V ±5%)
Parameter
MCM21 L15A-46 MCM21L15A·70
Units
Min
Max
Min
Max
Symbol
Chip Select Low to Output Valid
tSLOV
Chip Select High to Output Invalid
tSHOZ
Address Valid to Output Valid
tAVOV
Address Valid to Output Invalid
Write Low to Output Disable
ns
-
30
30
70
-
10
-
-
25
-
25
ns
ns
0
25
0
25
ns
30
0
5
5
-
30
0
5
5
5
5
5
-
-
ns
-
ns
5
-
30
30
45
tAVOX
tWLOZ
10
Write High to Output Valid
tWHOV
Write Low to Write High (Write Pulse Width)
tWLWH
Data Valid to Write Low
Write High to Data Don't Care
tDVWL
tWHDX
Address Valid to Write Low (Address Setup)
tAVWL
Write High to Address Don't Care
tWHAX
tSLWL
Chip Select Low to Write Low
Write High to Chip Select High
6
tWHSH
5
5
Address Valid to Address Don't Care
tAVAX
-
45
Chip Select Low to Chip Select High
tSLSH
-
45
5
-
ns
ns
ns
ns
ns
ns
ns
70
ns
70
ns
MCM2125A FAMILY AC OPERATING CONDITIONS AND CHARACTERISTICS, READ, WRITE CYCLES
(TA=Ot070·C VCC=50V ±5%)
Parameter
Symbol
MCM2125A-46
Min
Max
Chip Select Low to Output Valid
tSLOV
5
Chip Select High to Output High Z
tSHOZ
-
Addrass Valid to Output Valid
tAVOV
Address Valid to Output Invalid
tAVOX
10
Write Low to Output High Z
tWLOZ
tWHOV
-
30
30
45
MCM2125A·56
Min
Max
5
10
-
Write High to Address Don't Care
tAVWL
tWHAX
0
30
5
5
5
5
30
30
-
Chip Select Low to Write Low
Write High to Chip Select High
tSLWL
5
-
tWHSH
5
-
0
40
5
5
5
5
5
5
Address Valid to Address Don't Care
tAVAX
-
Chip Select Low to Chip Select High
tSLSH
-
45
45
-
Write High to Output Valid
Write Low to Write High (Write Pulse Width)
Data Valid to Write Low
Write High to Data Don't Care
tWLWH
tDVWL
tWHDX
Address Valid to Write Low (Address Setup)
35
35
55
MCM2125A·70
Max
Min
5
-
40
40
70
10
35
35
-
40
45
-
Units
ns
ns
ns
ns
ns
ns
-
0
50
5
5
15
5
5
5
55
-
70
ns
55
-
70
ns
-
ns
ns
ns
-
ns
-
ns
ns
-
ns
MCM21L25A FAMILY AC OPERATING CONDITIONS AND CHARACTERISTICS, READ, WRITE CYCLES
(TA=O to 70·C, Vcc=5.0 V ±5%)
Symbol
Parameter
MCM21L25A-46 MCM21L25A·70
Units
Min
Max
Min
Max
Chip Select Low to Output Valid
tSLOV
5
Chip Select High to Output High Z
tSHOZ
Address Valid to Output Valid
tAVOV
-
30
30
45
-
Address Valid to Output Invalid
tAVOX
tWLOZ
tWHOV
10
-
10
-
25
25
-
'WLWH
tDVWL
-
30
0
5
5
5
5
5
-
Write Low to Output High Z
Write High to Output Valid
Write Low to Write High (Write Pulse Width)
0
Chip Select Low to Write Low
tSLWL
Write High to .Chip Select High
tWHSH
30
0
5
5
5
5
5
Address Valid to Address Don't Care
tAVAX
-
45
Chip Select Low to Chip Select High
tSLSH
-
45
Data Valid to Write Low
Write High to Data Don't Care
Address VaHd to Write Low (Address Setup)
tWHDX
tAVWL
tWHAX
Write High to Address Don't Care
2-86
-
-
5
0
30
30
70
25
25
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
ns
ns
70
ns
MCM2115A-MCM21 L15A-MCM2125A-MCM21 L25A
CAPACITANCE (1=1.0 MHz, TA=25°C, periodically sampled rather than
OUTPUT LOAD
100% tested.!
VCC
Characteristic
Input Capacitance IVin = 0 VI
30011
Output Capacitance IVout = 0 VI
2115A
Capacitance measured with a Boonton Meter or effective capacitance calculated
from the equation: C=16t/6V.
O--.-----i
30 pF
Iinciuding
scope and jigl
600
2115A FAMILY
READ CYCLE TIMING 1
IS Held Low, W Held Highl
~,
tAVAX
___________-J)(~_____ :.:V
Address
Q IData Outl
===~~~~~~~=t~~~c=======~~~~=========VOH
Previous Data Valid
Data Valid
VOL
READ CYCLE TIMING 2'
(TN Held Highl
~---------------------3.5V
Address~
Address Valid
0V
_ _ _ _-----.I+-------tSLSH------+l~---- 3.5 V
OV
~ tSHOZ
---tSLOV---1
Q
'\' - - - -Data- -Valid- . . . /f
lData Out)
VOH
-
VOL
WRITE CYCLE TIMING
-------35V
tWHAX
r-----------
IN
tDVWL - ,
DIDatalnl~
r-
3.5 V
-OV
I'"=IW~ _ _
Data Valid
~:.:V
--I
~IWHOV
o IData Out) ~~~~~~Ge~~~~~~----~~~~~~~~=VOH
Data OUI= Data In
IWLOZ
~-------VOL
IAII Time Measurements Referenced 10 1.5 VI
2-87
•
MCM2115A-MCM21 L15A-MCM2125A-MCM21 ~A
OUTPUT LOAD
WAVEFORMS
Waveform
Symbol
\~~
Input
Output
Must Be
Valid
Will Be
Valid
Change
From H to L
Will Change
From H to L
VCC
510
2125A
0 -......- - .
300
IITm
Change
From L to H
Will Change
From L to H
OOOOOOOOC
Don't Care:
Any Change
Permitted
Changing
State
Unknown
~
30 pF
(Including
Scope and jig I
High
Impedance
2125A FAMILY
READ CYCLE TIMING 1
(S Held Low,W Held High)
Address
===~~~~~~~=E88~~~========~~~~========VOH
Q (Data Outl
Previous Data Valid
Data Valid
VOL
READ CYCLE TIMING 2
!W Held High)
~---------------------------3.5V
Address~
________,
Address Valid
0V
;..~-----tSLSH-----_.!r_------- 3.5 V
S
-OV
-VOH
Hi-Z -VOL
Q (Data Outl--------
WRITE CYCLE TIMING
.--;K~~========~tAAV~A~Xt=========~---------------35V
A~~~"w'1
---------0 V
tWHAX
!--tAVWL
___- - - - - - - - - - 3 . 5 V
w
tDVWL
1
D(Dataln)~
r-rData Valid
-.ltWLQZrQ (Data
~:.:V
~iWHOV
OUtl"'~"""''''''''''''''''a'''t1<:a'''~'''nd'''e'''f~Hi-Z
-OV
tWHDX _
,--------VOH
Data Out= Data In
~-------VOL
(All time measurements referenced to 1.5 VI
2-88
MCM2115A-MCM21 L15A-MCM2125A-MCM21 L25A
2115A FAMILY
WRITE ENABLE TO HIGH-Z DELAY
PROPAGATION DELAY FROM CHIP SELECT TO HIGH-Z
Write
Enable
Chip
Select
tWLOZ
Data
Output
i+---*tSHOZ
,------_ _ _ _ _ _ _-', 0.5 V
r--------Hi-Z
Hi-Z
Data
Output _ _ _ _ _-J' 0.5 V
2125A FAMILY
WRITE ENABLE TO HIGH-Z DELAY
Write
Enable
PROPAGATION DELAY FROM CHIP SELECT TO HIGH-Z
Chip
Select
1.5 V
1---_+tSHOZ
-tWLOZ
,------
Data.
Output
"0" Level, 0.5 V
Data
Output
Hi-Z
'----Hi-z
_....:"O~"..:L:::ev;:.:e::...I_ _-', 0.5 V
"1" Level
"1" Level
Data
Data
Output
Output
2-89
•
•
®
MCM2115H
MCM2125H
MOTOROLA
Product Previe"",
MOS
tN-CHANNEL, SILICON-GATEI
1024 x 1 STATIC RAM
l024-BIT STATIC
RANDOM ACCESS
MEMORY
The MCM2115H and MCM2125H families are high-speed, 1024 words
by one-bit, random-access memories fabricated using HMOS, highperformance N-channel silicon-gate technology. Both open collector
(MCM2115H) and three-state output (MCM2125H) are available. The
devices use fully static circuitry throughout and require no clocks or
refreshing to operate. Data out has the same polarity as the input data.
Access times are fully compatible wih the industry-produced 1K
Bipolar RAMs, yet offer up to 50% reduction in power.over their Bipolar
equivalents.
All inputs and outputs are directly TTL compatible. A separate chip
select allows easy selection of an individual device when outputs are
OR-tied.
• Organized as 1024 Words of 1 Bit
C SUFFIX
• Single + 5 V Operation
Maximum Access Time of 20 ns, 25 ns, 30 ns, and 35 ns Available
FRIT-SEAL
CERAMIC PACKAGE
CASE 620-06
•
• Low Operating Power Dissipation
• Pin Compatible to 93415A (2115H) and 93425A (2125H)
• TTL Inputs and Outputs
• Uncommitted Collector (2115H) and Three-State (2125H) Output
PIN ASSIGNMENT
5 [[i'i'J""i6 Vee
BLOCK DIAGRAM
Word
32x 32
Driver
Array
Vec= Pin 16
Vss=Pin8
~
t
Sense Amps
Control
Logic
And
Write Drivers
Q
i
Address
Address
Decoder
Decoder
15 0
AH 3
14 IN
A2[ 4
13 A9
A3! 5
12
A8
A4
11
A7
Q
10~A6
VSS 8
9 A5
PIN NAMES
A ..
D ..
0 ...
s.
:0111:4
AO[ L
S W
A51J71 :9
Vee· .
VSS·· .
IN.
0
............. Address
.......... Data Input
Data Output
ehip Select
+ 5 V Supply
. ........... Ground
. Write Enable
TRUTH TABLE
Inputs
S
H
L
L
L
W
x
L
L
H
D
X
L
H
X
Output
2115H Family
Output
2125H Family
a
a
H
H
H
Data Out
High Z
High Z
High Z
Data Out
Mode
Not Selected
Write "0"
Write "1"
Read
Motorola reserves the right to make changes to
any product herein to improve reliability, function or design. Motorola does not assume any
liability arising out of the application or use of
any product or circuit described herein; neither
does it convey any license under its patent rights
nor the rights of others.
NP321/1HlO
2-90
®
MOTOROLA
MCM2147
4096-BIT STATIC RANDOM ACCESS MEMORY
MOS
The MCM2147 is a 4096-bit static random access memory
organized as 4096 words by l-bit using Motorola's N-channel silicongate MOS technology. It uses a design approach which provides the
simple timing features associated with fully static memories and
the reduced standby power associated with semi-static and dynamic
memories. This means low standby power without the need for
clocks, nor reduced data rates due to cycle times that exceed access
times.
E controls the power-down feature. It is not a clock but rather
a chip select that affects power consumption. In less than a cycle
time after E goes high, deselect mode, the part automatically reduces
its power requirements and remains in this low-power standby mode
as long as E remains high. This feature r.esults in system power
savings as great as 85% in larger systems, where most devices are
deselected. The automatic power·down feature causes no perfor·
mance degradation.
The MCM2147 is in an 18 pin dual in-line package with the
industry standard pinout. It is TTL compatible in all respects. The
data out has the same polarity as the input data. A data input and
a separate three-state output provide flexibility and allow easy
OR-ties.
•
IN·CHANNEL, SILlCON·GATEI
4096-BIT STATIC
RANDOM ACCESS
MEMORY
C SUFFIX
FR IT-SEAL
CERAMIC PACKAGE
PLASTIC PACKAGE
CASE 7OHJ2
Fully Static Memory - No Clock or Timing Strobe Required
• Single +5 V Supply
• High Density 18 Pin Package
• Automatic Power·Down
• Di rectly TT L Compatible-All Inputs and Outputs
• Separate Data Input and Output
• Three·State Output
• Access Time - MCM2147·55 = 55 ns max
MCM2147-70 = 70 ns max
MCM2147-85 = 85 ns max
MCM2147·100 = 100 ns max
PIN ASSIGNMENT
AO
'i'i'J"iB
A2
16 A7
3
A3 4
15
A8
A4
14
A9
13
Al0
A5 6
12 A11
Q
Vii
Vss 9
BLOCK DIAGRAM
Vce
17 A6
Al
11
0
10
E
AO
Vee
A1
A2
A6
A7
AS
17
16
Row
Select
•
•
•
Memory Arrav
64 Row
64 Columns
= Pin
18
PIN NAMES
AO·All. ..................... Address Inpul
Vss = Pin 9
W.
.. Write Enable
.................. Chip Enable
................... Oata Input
................ Oata Output
.......... Power I + 5 VI
E..
0 ..
Q..
15
Vee ..
vss ..
11
. ...................... Ground
Q
D
TRUTH TABLE
A3
A4 AS A9 A10 A11
E
W
Mode
Output
Power
H
X
Not Selected
High Z
Standby
L
L
Write
High Z
Active
L
H
Read
Data Out
Active
059821/10-80
2-91
MCM2147
ABSOLUTE MAXIMUM RATINGS (See Notel
Value
Unit
-10to+85
°c
-0.5 to +7.0
Vdc
20
rnA
1.0
Watt
o to +70
°c
°c
Rating
Temperature Under Bias
Voltage on Any Pin With Respect to
Vee
DC Output Current
II
Power Dissipation
Operating Temperature Range
-65 to +150
Storage Temperature Range
Note:
This device contains circuitry to protect the
inputs against damagedueto high static voltages
or electric fields; however, it is advised that
normal precautions be taken to avoid applica-
tion of any voltage higher than maximum rated
voltages to this high-impedance circuit.
Permanent device damage may occur if ABSOLUTE MAXIMUM
RATINGS are exceeded, Functional operation should be restricted
to RECOMMENDED OPERATING CONDITIONS. Exposure to
higher than recommended voltages for extended periods of time eQuid
affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted)
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Logic 1 Voltage, All Inputs
Symbol
Min
Typ
Max
Unit
Vee
VSS
4.5
0
2.0
-0.3
5.0
0
5.5
0
V
-
Vee
0.8
VIH
VIL
Logic 0 Voltage, All Inputs
-
V
V
DC CHARACTERISTICS
MCM2147-55
MCM2147-70
MCM2147-85
MCM2147-100
Symbol
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IlL
-
0.01
10
-
0.01
10
-
0.01
10
-
0.01
10
/'A
Output Leakage Current
("E"' 2.0 V, V out = 0 to 5.5 VI
IOL
-
0.1
50
-
0.1
50
-
0.1
50
-
0.1
50
/'A
Power Supply Current
IE = V I L, Outputs Open, T A • 250 Cl
ICCl
-
120
170
-
100
150
-
95
130
-
90
110
rnA
Power Supply Current
(e = VIL, OutP~ts Open, T A = OOCI
ICC2
-
-
180
-
-
160
-
-
140
-
-
120
rnA
Parameter
I nput Load Current
(All Input Pins, Vin
0 to 5.5 VI
=
Standby Current
(E=VIHI
Input Low Voltage
IS8
-
15
30
-
10
20
-
15
25
-
10
20
rnA
VIL
-0.3
-0.3
-0.3
-0.3
V
2.0
6.0
2.0
6.0
2.0
-
0.8
6.0
-
0.8
2.0
-
0.8
VIH
-
0.8
Input High Voltage
6.0
V
Output Low Voltage
(lOL = 8.0 mAl
VOL
-
-
0.4
-
~
0.4
-
-
0.4
-
-
0.4
V
Output High Voltage
(lOH = -4.0 rnAI
VOH
2.4
-
-
2.4
-
2.4
-
-
2.4
-
-
V
TYPical values are for T A
=
25°C and Vee
=
+5.0 V.
FIGURE 1 - OUTPUT LOAD
CAPACITANCE
(f = 1.0 MHz, TA = 25°C, periodically sampled rather than 100% tested.)
Characteristic
Input Capacitance (Vin - 0 V)
Output Capacitance (V out
=0 V)
Symbol
Vee
Max
Unit
Cin
5.0
pF
Cout
10
pF
Capacitance measured with a Boonton Meter or eff,ective capacitance calculated
from the equation: C
-
lat
510
a--..----..
30 pF
300
= il.V'
2-92
"' (Including
scope and jig)
MCM2147
AC OPERATING CONDITIONS AND CHARACTERISTICS
I Full operating voltage and temperature unless otherwise notedl
Input Pulse Levels ........ .
Input Rise and Fall Times ...
....... 0 Volt to 3.5 Volts
............ 10 ns
Input and Output Timing Levels .................. .
Output Load ........................... .
. ......... 1.5Volts
See Figure 1
READ, WRITE CYCLES
Parameter
Symbol
Address Valid to Address Don't Care
ICycle Time When Chip Enable is Held Activel
Chip Enable Low to Chip Enable High
Address Valid to Output Valid IAccessl
MCM2147-56
Min
Max
55
-
70
-
85
-
100
-
55
-
70
-
85
-
100
-
ns
-
55
-
70
-
85
-
100
ns
55
70
85
100
ns
tj\)
~5
110
ns
-
ns
10
0
0
40
40
-
0
0
10
0
-
tpD
0
30
0
30
-
0
-
10
Chip Enable Low to Output Invalid
tELQX
tEHQZ
tpu
10
10
-
Chip Deselection to Power-Down Time
Address Valid to Chip Enable Low
IAddress Setupl
<.;hip cnaDle LoW to write High
tAVEL
0
tELWH
45
Address Valid to Write High
tAVWH
45
Address Valid to Write Low IAddress Setup!
tAVWL
Write Low to Write High IWrite Pulse Width I
tWLWH
0
35
Write High to Address Don't Care
tWHAX
10
-
Data Valid to Write High
tDVWH
25
-
30
Write High to Data -Don't Care lData Holdl
tWHDX
tWLQZ
10
-
10
-
0
30
0
35
Write Low to Output High Z
Write High to Output Valid
55
55
40
10
0
40
ns
ns
0
-
0
30
0
-
ns
0
30
0
ns
-
0
-
ns
-
80
80
-
70
0
55
0
-
65
ns
ns
55
-
ns
10
-
ns
0
50
0
-
ns
ns
-
15
45
-
10
-
0
45
IS
-
ns
ns
-
15
-
ns
-
access from chip enable for
TIMING LIMITS
I
t X X X X
,;,0"
10
70
0
40
15
10
0
0
0
tWHQV
*tELQV1 IS access from chip enable when the 2147 IS deselected for at least 55 ns pnor to this cycle. tELQV2
o ns <.. deselect time < 55 ns. If deselect time = 0 os, then tELQV = tAVQV.
TIMING PARAMETER ABBREVIATIONS
ns
65
-
tAVQX
Chip Selection to Power-Up Time
Unit
tELEH
tAVQV
Address Valid to Output Invalid
Chip Enable High to Output High Z
MCM2147-1oo
Min
Max
MCM2147-86
Min
Max
tAVAX
tELQV"
tELQV2'
Chip Enable Low to Output Valid IAccessl
MCM2147-70
Min
Max
~m. ""'" wh;,h ;o~.o;. d.l;o",.J
transition direction for first signal
signal name to which interval is defined
transition direction for second signal
The table of timing values shows either a minimum or
maximum limit for each parameter. Input requirements
are specified from the external system point of view.
Thus, address setup time is shown as a minimum since the
system must supply at least that much time (even though
most devices do not requi re it). On the other hand,
responses from the memory are specified from the device
point of view. Thus, the access time is shown as a maximum since the device never provides data later than
that time.
I I
~
The transition definitions used in this data sheet are:
H = transition to high
L = transition to low
V = transition to valid
X = transition to invalid or don't care
Z = transition to off (high impedance)
2-93
MCM2147
~E~~dC~O~ETIMING 1
~
'AvAX---------.~"' _ _ _ _ _
-*
ADDRESS
------
VIH
' - - - - - VIL
tAV~~~---~
a(Dataout)-----=p-,.-v~;O-U-'~D~.-U~v-.iC;d~--~~nr,~,-------~D~a-'-.7V~.~II~d------VOH
--------------LA4~~~~-----------------VOL
I-- 'AVEL
.::j
READ CYCLE TIMING 2
ADDRESS
Address Valid
(XlII:
tELEH
~
-
I---'ELQX---t
Q (Data out)
Vee
Supply
Current
II~~
High Z
I
- - - -
NOTE:
Data Valid
'EHQZr--
I
). High Z VOH
-~ ~~r=-------------~---'-P-D-t
-
W is
high for Read Cycles.
WRITE CYCLE TIMING
tAVAX
ADDRESS
-IHIIIIIIIIIIIII/'
~·------·-'ELWH
ill ~
tAVWH
I----tAVWL
twLWH
.\
twHAX
Data out"" Data in
WAVEFORMS
Waveform
Symbol
Input
Output
MUST BE
VALID
WILL BE
VALID
CHANGE
WILL CHANGE
~
FROM HTO L
FROM H TO L
-'llZl7
CHANGE
FROM L TOH
WILL CHANGE
~
DON'T CARE:
ANY CHANGE
PERMITTED
CHANGING:
STATE
UNKNOWN
=>---
FROM L TO H
HIGH
IMPEDANCE
2-94
VOL
MCM2147
FIGURE 2 - AVERAGE DEVICE DISSIPATION
versus MEMORY SIZE
DEVICE DESCRIPTION
The MCM2147 is produced with a high-performance
MOS technology which combines on-chip substrate bias
generation with device scaling to achieve high speed_
The speed-power product of this process is about four
times better than earlier MOS processes_
This gives the MCM2147 its high speed, low power and
ease-of-use. The low-power standby feature is controlled
with the E input. E is not a clock and does not have to
be cycled. This allows the user to tie E directly to system
addresses and use the line as part of the normal decoding
logic. Whenever the MCM2147 is deseiected, it automatically reduces its power requirements.
ICC
SYSTEM POWER SAVINGS
The automatic power-down feature adds up to significant system power savings. Unselected devices draw low
standby power and only the active devices draw active
power. Thus the average power consumed by a device
declines as the system size increases, asymptotically
approaching the standby power level as shown in Figure 2.
The automatic power-down feature is obtained without
any performance degradation, since access time from chip
enable is .;; access time from address valid. Also the fully
static design gives access time equal cycle time so multiple
read or write operations are possible during a single select
period. The resultant data rates are 14.3 MHz and 18 MHz
for the MCM2147-70 and MCM2147-55 respectively.
ISB.~~-7.;==~;;:=====::::;~
4K 8K 16K
32K
64K
MEMORY SIZE IN WORDS
FIGURE 3 - PC LAYOUT
DECOUPLING AND BOARD LAYOUT
CONSIDERATIONS
The power switching characteristic of the MCM2147
requires careful decoupling. It is recommended that a
0.1 !IF to 0.3 !IF ceramic capacitor be used on every
other device, with a 22 !IF to 47 !IF bulk electrolytic
decoupler every 16 devices. The actual values to be used
will depend on board layout, trace widths and duty cycle.
Power supply gridding b recommended for PC board
layout. A very satisfactory grid can be developed on
a t""o-Iayer board with vertical traces on one side and
horizontal traces on the other, as shown in Figure 3.
If fast drivers are used, termination. are recommended
on input signal lines to the MCM2147 because significant
reflections are possible when driving their high impedance
inputs. Terminations may be required to match the
impedance of the line to the driver.
2-95
®
MOTOROI.A
MCM2147H
Product Previe'VV
MOS
•
4096·BIT STATIC RANDOM ACCESS MEMORY
IN·CHANNEL, SILlCON·GATEI
The MCM2147H is a 4096-bit static random access memory organized
as 4096 words by l·bit using Motorola's high-performance N-channel
silicon-gate MOS technology (HMOS), It uses a design approach which
provides the simple timing features associated with fully static
memories and the reduced standby power associated with semi-static
and dynamic memories, This means low standby power without the
need for clocks, nor reduced data rates due to cycle times that exceed
access ti mes.
E controls the power-down feature, It is not a clock.but rather a chip
select that affects power consumption, In less than a cycle time after E
goes high, deselect mode, the part automatically reduces its power requirements and remains in this low-power standby mode as long as E
remains high. This feature results in system power savings as great as
85% in larger systems, where most devices are deselected, The
automatic power-down feature causes no performance degradation.
The MCM2147H is in an 18 pin dual in-line package with the industry
standard pinout. It is TTL compatible in all respects. The data out has
the same polarity as the input data, A data input and a separate threestate output provide flexibility and allow easy OR-ties,
• Fully Static Memory - No Clock or Timing Strobe R..quired
4096-BIT STATIC
RANDOM ACCESS
MEMORY
•
•
•
•
•
•
•
•
~
~1'Yii~~)[( ~
U Uc SUFFIX
FRIT·SEAL
CERAMIC PACKAGE
CASE 72S-02
PIN~ENT
AO 1.
18 Vee
HMOS Technology
Single + 5 V Supply
High Density 18 Pin Package
Automatic Power-Down
Directly TTL Compatible - All Inputs and Outputs
Separate Data Input and Output
Three-State Output
Access Time
MCM2147H-35~35
MCM2147H-45~45
MCM2147H-55~55
ns Max
ns Max
ns Max
A1
2
17
A6
A2
3
16
A7
A3
4
15
A8
A4 5
14
A9
A5 6
13
Al0
a
7
12
Ail
W
'8
11
0
VSS 9
10
E
PIN NAMES
Vi,
AO
E.
A2
A7
AS
17
16
Row
Select
•
•
•
Memory Array
. Chip Enable
Data Input
0
Vee'" Pin 18
A1
A6
.Address Input
Write Enable
AO·A11
BLOCK DIAGRAM
a ..
VSS=-Pin9
Data Output
Power 1+5 VI
Vee,
VSS
64 Row
64 Columns
15
..... Ground
.......
TRUTH TABLE
11
0
Q
E
W
Mode
Output
H
X
Not Selected
High Z
Power
Standby
L
L
Write
High Z
Active
L
H
Read
Data Out
Active
Motorola reserves the right to make changes to
any product herein to improve reliability,
A3
func~
tion or design. Motorola does not assume any
liability arising out of the application or use of
any product or circuit described herein; neither
does it convey any license under its patent rights
nor the rights of others.
A4 A5 A9 Al0 A1l
NP322/11-80
2-96
@
MOTOROLA
MCM2148
Advance InforIllation
MOS
4096-BIT STATIC RANDOM ACCESS MEMORY
IN-CHANNEL, SILICON-GATE I
The MCM2148 is a 4096-blt random access memory fabricated using
HMOS, high performance MOS technology. For ease of use, the device
operates from a single power supply, is directly compatible With TTL
and reqUires no clocks or refresh;ng because of fully static operation.
Data access IS particularly simple, Since address setup times are not required. The output data has the same polarity as the Input data.
The MCM2148 is designed for memory applications where simple InterfaCing is the design objective. The MCM2148 is assembled in 18-pin
dual-in-line packages with the Industry standard pin-out. A separate
chip select (E) lead allows easy selection of an individual package when
the three-state outputs are OR-tied.
•
1024 Words by 4-8it Organization
•
•
HMOS Technology
Industry Standard 18-Pin Configuration
4096-BIT STATIC
RANDOM ACCESS
MEMORY
CASE 726
• Single + 5 Volt Supply
• No Clock or Timing Strobe Required
• Maximum Access Time
70 ns MCM2148-70
85 ns MCM2148-85
L SUFFIX
•
Power Dissipation
140 mA Maximum (Active)
30 mA Maximum (Standby)
CASE 680
•
Fully TTL! DTL Compatible
PIN ASSIGNMENT
• Common Data Input and Output
• Three-State Outputs for OR-Ties
• Automatic Power Down
A6
BLOCK DIAGRAM
VCC= Pin 18
Vss=Pin9
A4
3
A5
A6
A7
A8
A9
001
17
16
Row
Select
Memory Array
15PA9
AO
14 '001
Al
13
002
A2 7
12
003
11
004
10 W
•
14
PIN NAMES
AO-A9__
\flo.
__ ______ . __________ Address Input
......... Write Enable
E__
.. Chip Select
001-0Q4__
__ __ .Oata Input/Output
Vec-- ____________ . ___________ Power 1+5 VI
VSS-__________ Ground
004
W
A3 4
15
003 12
8
7
10
16PA8
VSS
OQ2 13
E
17~A7
A4
E
64 Rows
64 Columns
fie\-JiB~vee
A5
4
AO Al A2 A3
AOI851/9-80
2-97
•
•
MCM2148
ABSOLUTE MAXIMUM RATINGS ISee Note)
Rating
Temperature Under Bias
Voltage on Any Pin With .Respect to VSS
Value
Unit
-10to +80
°c
-3.5 to +7.0
V
DC Output Current
20
mA
Power Dissi pation
1.2
Watt
o to
Operating Temperature Range
Storage Temperature Range.
+ 70
-65 to.+ 150
This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however,
it is advised that normal precautions be
taken to avoid application of any voltage
higher than maximum rated voltages to
°c
this high-impedance circuit.
°c
NOTE: Permanentdevice damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods oHime could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
IFul1 operating voltage and temperature ranges unless otherwise noted.)
RECOMMENDED
OC OPERATING CONDITIONS
Symbol
Min
Typ
Max
Supply Voltage
VCC
VSS
4.5
0
5.0
0
Logic 1 Voltage, All Inputs
VIH
-
Logic 0 Voltage, All Inputs
VIL
2.0
-3.0
5.5
0
6.0
-
0.8
V
Parameter
Unit
V
V
DC CHARACTERISTICS
Symbol
Min
Typ
Ma.
Unit
Input Load Current IAlllnput Pins, Vin=O to 5.5 V, Vcc=Max)
III
0.01
10
p.A
Output Leakage Current If,. VIH, VCC= Max, Vout=O to 4.5 V)
IiLOI
-
0.1
50
p.A
Output Low Voltage IIOL = 8 mAl
VOL
-
0.4
r-;;;A
Output High Voltage IIOH = - 2.0 mAl
Power Supply Current IVin=5.5,IDO-0 mA, TA-25°C, t"-VILI
VOH
2.4
-
-
rnA
ICCl
100
135
mA
-
140
mA
12
30
mA
25
50
mA
-
+150
mA
Parameter
Power Supply Current IVin=5.5 V,IDO=O mA, TI\=QoC, E=VILI
ICC2
Standby Current IVcc=Min to Max, E=VIHI
Peak Power on Current IVCC=O to VCC Min, t=VIH mini"
ICC3
IpO
-
Output Short Circuit Current IV out = GND to VCCI
lOS
-150
• A pullup resIstor to
Vee on
the E mput IS required to keep the device deselected, otherwise, power-on current approaches ICC-
CAPACITANCE If= 1.0 MHz, TA=25°C, periodically sampled rather than 100% tested.1
Characteristic
Input Capacitance IVin = 0 VI
Output Capacitance IV out - 0 VI
FIGURE 2
FIGURE 1
+5 V
+5V
5100
5100
o
o
3300
30 pF
IIncluding scope and jigl
3300
2-98
5 pF
MCM2148
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature unless otherwise noted.)
Input Pulse Levels ....
Input Rise and Fall Times ..
................... 0 Volt to 3.0 Volts
............ 10 ns
Input and Output Timing Levels ..
Output Load ..
Symbol
Parameter
. .......... 1.5 Volts
. .... See Figure 1
MCM2148-70 MCM2148-85
Min
Max
Min
85
Address Valid to Address Don't Care ICycle Time if E = VIL}
tAVAX
70
-
Address Valid to Output Valid (Address Access Time)
tAVOV
-
70
Address Valid to Output Undefined
tAVOX
5
-
5
Chip Enable Low to Chip Enable High (Cycle Time)
tELEH
70
-
85
Chip Enable Low to Output Undefined
tELOX
25
-
25
Chip Enable Low to Output Valid IChip Select Access Time}
tELOV1
tELOV2
-
70
80
-
.-
-
Unit Notes
Max
_.
ns
85
ns
-
ns
ns
6
85
95
ns
ns
1
2
ns
Chip Selection to Powerup Time
tpu
0
-
0
-
ns
Chip Deselection to Powerdown Time
tpD
-
30
-
30
ns
tEHOZ
0
20
0
20
ns
-
ns
Chip Enable High to Output High Z
6
Chip Enable Low to Write High
tELWH
65
-
80
Address Valid to Write Low (Address Setup)
tAVWL
0
-
0
Write High to Address Don't Care
tWHAX
5
5
Write Low to Write High (Write Pulse Width)
tWLWH
50
-
60
Data Valid to Write High
tDVWH
25
-
30
ns
Write High to Data Don't Care
tWHDX
5
-
5
ns
Write Low to Output High Z
tWLOZ
0
25
0
30
ns
6
Write High to Output Active
tWHOV
0
-
0
-
ns
6
NOTES:
1. Chip deselected for greater than 55 ns prior to
E transition
ns
ns
ns
low.
2.
Chip deselected for a finite time that is less than 55 ns prior to
selected and access occurs according to Read Cycle 1.1
E transition
low. (If the deselect time is 0 ns, the chip is by definition
3.
W is
4.
Device is continuously selected,
5.
Addresses valid pnor to or cOincident with E transition low.
6.
Transition is measured ± 500 mV from high impedance with the load in Figure 2. This parameter is sampled and not 100% tested.
high for read cycles
READ CYCLE TIMING 1 13, 4)
LOW, W HELD HIGH)
IE HELD
E= VIL.
~--------------------tAVAX --------------------~
Address
o IData
Data Valid
Out}
READ CYCLE TIMING 2 13, 51
(Iii HELD HIGHI
Address
~________________________________A_d_d_re_ss__V_al_id_________________________________________
~------------------tELEH ------------------~~~~-----------------14-----Io+-tEHOZ
o IData
High-Z
Out!
High-Z
-------=---------t---'==--'-i(
Data Valid
14-------tPD
Operating
Current
Standby ___________________- " .
Current
2-99
•
MCM2148
WRITE CYCLE 1
(W CONTROLLED)
~-------------------------tAVAX--------------------------------~
Address
Address Valid
~-------------------tELWH
•
~--------------------------tAVWH--------------------~~
~--------------tWLWH---------------!~----------~-----
~-----tOVWH-----1*"""'~-
W
OIOatalnl---------------------+-----------------(>CX)~
Data Valid
1+-----_+tWHOVI4, 5)
o IData DuO
High Impedance
Data Undefined
NOTE:
1. If l' goes high simultaneously with W high, the output remains in a high-impedance state.
2. tWHAX is measured from the earlier of S or Vii going high to the end of the write cycle.
3. During this period, DO pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.
4. If S is low during this period, the DO pins are in the output state. Then the data input signals of opposite phase to the outputs must not
be applied to them.
5. 0 is the same phase of write data of this write cycle,
WRITE CYCLE 2
(I' CONTROLLED)
~---------------------------tAVAX----------------------------------~
Address
Address Valid
___~~_, ~14------------------·tELWH-----------------~c------~---
~------'------------------
tAVWH
----------------------_+{
~-------------- tWLWH ----------------~'k_,~~:;_,_c~_r'7-"?
w
tOVWH ----...j4---H-
High Impedance
o 10ataOuO---------------------------------------------------------------------------------------
2-100
®
MOTOROLA
MCM2148H
Product Previe'VV
MOS
IN·CHANNEL. SILlCON·GATEI
4096-BIT STATIC RANDOM ACCESS MEMORY
The MCM2148H is a 4096-bit random access memory fabricated using HMOS, high performance MOS technology. For ease of use, the
device operates from a single power supply, is directly compatible with
TTL and requires no clocks or refreshing because of fully static operation. Data access is particularly simple, since address setup times are
not required. The output data has the same polarity as the input data.
The MCM2148H is designed for memory applications where simple
interfacing ;s the design objective. The MCM2148H is assembled in
18-pin dual-in-line packages with the industry standard pin-out. A
separate chip enable (EI lead allows easy selection of an individual
package when the three-state outputs are OR-tied.
•
•
•
•
•
•
-~
Iii
II
-
-
~
1024 Words by 4-Bit Organization
HMOS Technology
Industry Standard 18-Pin Configuration
Single + 5 Volt Supply
No Clock or Timing Strobe Required
Maximum Access Time
MCM2148H-45=45 ns
MCM2148H-55= 55 ns
c SUFFIX
FRIT·SEAL PACKAGE
CASE 726-02
...
L SUFFIX
CERAMIC PACKAGE
CASE 6B().06
• Power Dissipation
180 mA Maximum (Activel
30 mA Maximum (Standbyl
•
•
•
•
4096-BIT STATIC
RANDOM ACCESS
MEMORY
Fully TTL Compatible
Common Data Input and Output
Three-State Outputs for OR-Ties
Automatic Power Down
PIN ASSIGNMENT
A6
A5
[1e\../"i8 ~ V ce
2
t7~A7
4
15~A9
16~A8
A4
A3
BLOCK DIAGRAM
Vce= Pin 18
VSS·= Pin 9
A4
A6
A7
A9
14
Al
13
D02
12
D03
A2
A5
A8
AO
17
16
Row
Select
7
E 8
Memory Array
64 Rows
64 Columns
VSS
15
DOl
11
D04
10
W
PIN NAMES
AO-A9..
. ....... Address Input
14
W.............................. Write Enable
E... ................... ...... Chip Enable
D02 13
001-004 ................ Data Input/Output
Vce ........................... Power (+5 VI
VSS......
. .... Ground
DOl
D04
E
6
10
W
Motorola reserves the right to make changes to
any product herein to improve reliability, function or design. Motorola does not assume any
liability ariSing out of the application or use of
8
7
4
any product or circuit described herein; neither
AO Al A2 A3
does it convey any license under its patent rights
nor the rights of others.
NP323/II-SO
2-101
•
®
MCM2149
MOTOROLA
Product Previe'W'
MOS
(N·CHANNEL. SILICON·GATE)
4096-BIT STATIC RANDOM ACCESS MEMORY
The MCM2149 is a 4096-bit random access memory fabricated using
HMOS, high performance MOS technology. For ease of use, the device
operates from a single power supply, is directly compatible with TTL
and requires no clocks or refreshing because of fully static operation.
Data access is particularly simple, since address setup times are not required. The output data has the same polarity as the input data.
The MCM2149 is designed for memory applications where simple interfacing is the design objective. The MCM2149 is assembled in 18-pin
dual-in-line packages with the industry standard pin-out. A separate
chip select (S) lead allows easy selection of an individual package when
the three-state outputs are OR-tied.
• 1024 Words by 4-Bit Organization
• Single + 5 Volt Supply
• No Clock or Timing Strobe Required
~
L SUFFIX
CERAMIC PACKAGE
CASE 6llO-06
.
Chip Select Access Time
MCM2149-70=30 ns Max.
MCM2149-85= 35 ns Max.
140 mA Maximum (Active)
• Fully TTL Compatible
• Common Data Input and Output
PIN ASSIGNMENT
• Three-State Outputs for OR-Ties
• Automatic Power Down Version Available -
A6
MCM2148
VCC= Pin 18
VSS'= Pin 9
A4~----~'-'---~
A5-----l
A6-----l
A7 _1_7_ _ _--1
Row
Select
A8 _1_6_ _ _-1
•
•
•
16 AS
A3 4
15 A9
AD 5
14 DOl
Al 6
13
A2 7
12 D03
8
VSS 9
64 Rows
64 Columns
AD-A9 ..
Vi
S..
• •
D01·D04 ..
Vee ..
VSS
D02 _13_---1+H
VCC
17 A7
A4 3
S
Memory Array
A9_1_5_ _ _~~~~
~==::::
1eV1s
A5 2
BLOCK DIAGRAM
14
DQ1--_--l
C SUFFIX
~.
• Maximum Access Time
MCM2149-70=70 ns Max.
MCM2149-B5=85 ns Max.
• Power Dissipation -
-.
I
FRIT-SEAL PACKAGE
CASE 726-02
• HMOS Technology
• Industry Standard IS-Pin Configuration
•
4096-BIT STATIC
RANDOM ACCESS
MEMORY
D02
11 004
10 W
PIN NAMES
................ Address Input
.. Write Enable
...... Chip Select
.. ... Data Input/ Output
..Power 1+5 V)
....... Ground
D03 _1_2_++-+--1
D04-...+t+H
Motoro)a reserves the right to make changes to
any product herein to improve reliability, function or design. Motorola does not assume any
liability arising out of the application or use of
any product or circuit described herein; neither
AD Al A2 A3
does it convey any license under its patent rights
nor the rights of others.
NP324/11-80
2-102
®
MCM2167
MOTOROLA
Product
Previe~
MOS
16,384-BIT STATIC RANDOM ACCESS MEMORY
(N-CHANNEL, SILICON-GATEI
The MCM2167 is a 16,384-bit static random access memory organized as 16,384 words by l-bit using Motorola's N-channel Silicon-gate
MOS technology. It uses a design approach which provides the simple
timing features associated with fully static memories and the reduced
standby power associated with semi-static and dynamic memories. This
means low standby power without the need for clocks, nor reduced
data rates due to cycle times that exceed access times.
E controls the power-down feature. It is not a clock but rather a chip
select that affects power consumption. In less than a cycle time after E
goes high, deselect mode, the part automatically reduces its power requirements and remains in this low-power standby mode as long as E
remains high. This feature results in sytem power savings as great as
85% in larger systems, where most devices are deselected. The
automatic power-down feature causes no performance degradation.
The MCM2167 is in a 20 pin dual in-line package with the industry
standard pinout. It is TTL compatible in all respects. The data out has
the same polarity as the input data. A data input and a separate threestate output provide flexibility and allow easy OR-ties.
16,384-BIT STATIC
RANDOM ACCESS
MEMORY
• Fully Static Memory - No Clock or Timing Strobe Required
•
•
•
•
•
PIN ASSIGNMENT
Single + 5 V Supply
High Density 20 Pin Package
Automatic Power-Down
Directly TTL Compatible - All Inputs and Three-State Output
Separate Data Input and Output
• Access Time
MCM2167-55 MCM2167-70 MCM2167-85 MCM2167-1oo -
•
VCC
A13
A12
All
AlO
55 ns max
70 ns max
85 ns max
100 ns max
A9
AS
A7
D
VSS~_ _ _--r
BLOCK DIAGRAM
Vcc=Pin 20
VSS= Pin 10
•
Row
Select
•
E
PIN NAMES
J-;;;:o:A'3 ......................... Address Input
Memory Array
128 Rows
128 Columns
W..
.................... Write Enable
E..
..Chip Enable
. .. Data Input
. ... Data Output
. ............. Power 1+5 VI
D..
G..
VCC..
'{s£...
•
. ........................... Ground
TRUTH TABLE
G
E
H
L
L
W
X
L
H
Mode
Not Selected
Write --_.
Read
O~t
Power
High Z
High Z
Data Out
Standby
Active
Active
~~----.
NP326/11-80
2-103
•
®
MCM4016
MOTOROLA
Product Previe'VV
MOS
2048xB-BIT STATIC RANDOM ACCESS MEMORY
IN-CHANNEL, SILICON-GATE)
The MCM4016 is a 16,384-bit static Random Access Memory organized as 2048 words by 8-bits, fabricated using Motorola's highperformance silicon-gate metal oxide semiconductor (HMOS)
technology. Its static design means that no refresh clocking circuitry is
needed and timing requirements are simplified. Access time is equal to
cycle time.
A chip select control is provided for controlling the flow of data in and
data out, and an output enable function is provided which eliminates
the need for external bus buffers.
The MCM4016 is in a 24-pin dual-in-line package with the industry
standard pinout and is pinout compatible with the industry standard
16K EPROM and 16K mask programmable ROM.
2048 X 8 BIT STATIC
RANDOM ACCESS MEMORY
• 2048 Words by 8-8its Organization
• HMOS Technology
• Single + 5 V Supply
• Fully Static: No Clock or Timing Strobe Required
• Low Power Dissipation 35 mW Typical (Standby)
400 mW Typical (Active)
• Maximum Access Time: MCM4016-20 - 200 ns
PIN ASSIGNMENTS
• Fully TTL Compatible
• Pinout Compatible with Industry Standard 2716 16K EPROM and
Mask Programmable ROM
A7
VCC
AS
A6
A5
A9
• Output Enable (IT) Eliminates Need for Extern,,1 8us 8uffers
W
Al0
BLOCK DIAGRAM
AO
Al
A2
A3
A4
A5
A6
8
7
6
5
4
3
2
~
=:
~
'==
Row
Decoder
~
Memory Matrix
•
128x 128
~
>c-:-
t"
Pin 24= VCC
Pin 12= VSS
---.--.
001
005
DQ2
004
>--VSS
DO~~J-
001
D02ih-
D03~
004~
D05~
006+
D07~
~
rr~
~
r-e
Input
Data
•
Column I/O
r--.!-
Control
r-!-
1
23
~
A7
~
A8
~ "T ~,
l
~
A9
003
PIN NAMES
AO-A 10 .......................... Address Input
QOO-D07 ................. Data Input/Output
Q ................................. Output Enable
Chip Select
W .................................. Write Enable
VCC············ ..... ···· ........ Powerl+5V)
VSS···· ... ······ ......................... Ground
.s ....................................
Column Decoder
~
L--_ _ _...J
l
Al0
I I
: I I
• I I
I I
....
Motorola reserves the right to make changes to
any product herein to improve reliability, function or design. Motorola does not assume any
E
G
W
liability ariSing out of the application or use of
18
20
Control
21
Logic
any product or circuit described herein; neither
does it convey any license under its patent rights
nor the rights of others.
NP329/11-80
2-104
®
MCM6641
MCM66L41
MOTOROLA
Advance InforIllation
MOS
4096-BIT STATIC RANDOM ACCESS MEMORIES
(N-CHANNEL, SILlCON·GATEI
The MCM6641 series 4096 x l-bit Random Access Memory is
fabricated with high density, high reliability N-channel silicon-gate
technology. For ease of use, the device operates from a single 5-volt
power supply, is directly compatible with TTL and DTL, and requires no
clocks or refreshing because of fully static operation. The fully static
operation allows chip selects to be tied low, further simplifying system
timing. Data access is particularly simple, since address setup times are
not required. The output data has the same polarity as the data input.
The MCM6641 is designed for memory applications where simple interfacing is the design objective, and is assembled in 18-pin dual-in-line
packages with the industry standard pin-outs.
4096-BIT STATIC
RANDOM ACCESS MEMORIES
_
• Single ± 10% + 5 V Supply
• Fully Static Operation - No Clock, Timing Strobe, Pre-Charge, or
Refresh Required
•
•
•
•
•
Industry Standard 18-Pin Configuration
Fully TTL Compatible
Common Data Input and Output Capability
Three-State Outputs for OR-Tie Capability
Power Dissipation MCM6641 Less Than 550 mW (Maximum)
MCM66L41 Less Than 385 mW (Maximum)
• Standby Power Dissipation Less Than 125 mW (Typicall
• Plug-In Replacement For TM S4044
. C SUFFIX
FRIT·SEAL CERAMIC PACKAGE
CASE 707·01
..
P SUFFIX
PLASTIC PACKAGE
CASE 707·02
PIN ASSIGNMENT
AO
MAXIMUM ACCESS TIME/MINIMUM CYCLE TIME
MCM6641·20
MCM66L41·20
MCM6641·25
MCM66L41·25
200 ns
MCM6641·30
MCM66L41·30
250 ns
MCM6641-45
MCM66L41-45
,'
300 ns
450 os
['ii\..J"i8
Vee
All 2
17
A6
A2[ 3
16
A7
A314
15
A8
A4[ 5
14
A9
A5[ 6
13
A10
G[ 7
12
A11
Wl8
11
D
V SS l9
10
S
BLOCK DIAGRAM
Ao'------~~-i------A 1 ____
PIN NAMES
o 4 I _ _ V SS
AO-A11
......... Address Input
D
............. Data Input
G ............................... Data Gutput
S .................................... Chip Select
Vee .................. PowerSupply(+5VI
~s ..................................... Ground
W ................................ Write Enable
...J~.__...,
A2-_-Q\:::::l
A8. _ _ _ _...J~..-...,
Row
Select
Memory Array
64 Row
-----Vee
64 Columns
A7
Q
TRUTH TABLE
w---..............
5 -i.>c>+---e--L.-I
A3 A4 A5A11A10A9
S
W
0
a
Mode
H
X
X
High Z
Not Selected
L
L
L
High Z
Write "0"
L
L
H
High Z
Write "1"
L
H
X
Output data
Read
ADI475/2-78
2-105
•
•
MCM6641-MCM66L41
ABSOLUTE MAXIMUM RATINGS (See Note I
Value
Unit
Temperature Under Bias
-10 to +80
°c
Voltage on Any Pin With Respect to VSS
-0.5 to +7.0
Vdc
Rating
DC Output Current
20
mA
Power Dissipation
1.0
Watt
o to +70
°c
°c
Operating Temperature Range
-65 to +150
Storage Temperature Range
Note:
This device contains circuitry to protect the
inputs against damage due to high static voltages
or electric fields; however, it is advised that
normal precautions be taken to avoid application of any voltage higher than maximum rated
voltages to this high-impedance circuit.
Permanent device damage may occur if ABSOLUTE MAX IMUM
RATINGS are exceeded. Functional operation should be restricted
to RECOMMENDED OPERATING CONDITIONS. Exposure to
higher than recommended voltages for extended periods of time could
affect device reliability.
DC PPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted)
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Min
Typ
Ma.
Unit
Supply Voltage
VCC
VSS
4.5
0
5.0
0
5.5
0
V
Logic 1 Voltage, All Inputs
VIH
2.0
6.0
V
Logic 0 Voltage, All Inputs
VIL
-0.5
-
0.8
V
Parameter
DC CHARACTERISTICS
Symbol
Parameter
-
Input Load Current IAII Input Pins, Vin = 0 to 5.5 VI
III
Output Leakage Current ICS-2.4 V, Vin=O.4 to VCcl
IILol
ICC
Power Supply Current 1VCC=5.5 V, 10ut=0 mA, TA=O'CI
Output Low Voltage, 10L = 2.1 mA
VOL
Output High Vol1age, 10H = 1.0 mA
VOH
lOS·
Output Short Circuit Current
Min
MCM6641
Typ Ma.
-
-
-
80
0.15
-
2.4
-
10
10
100
0.4
40
MCM66L41
Min Typ Ma.
-
55
Unit
-
0.15
10
10
70
0.4
2.4
-
-
V
-
-
40
mA
--
pA
pA
mA
V
·Ouration not to exceed 30 seconds.
CAPACITANCE 11= 1.0 MHz, T A = 25'C, VCC = 5.0 V, periodically sampled rather than 100% testedl
Characteristic
Input Capacitance IVin = 0 VI
Output Capacitance IVout=O VI
Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C= 1At/AV.
STANDBY OPERATION
ITypical Supply Valuasl
Device
Supply
Operating
Standby
MCM6641
VCC
+5 V
+2.4 V
225mW
MCM66L41
VCC
+5 V
+2.4 V
150mW
2-106
Max Standby Power
MCM6641-MCM66L41
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted)
Input Pulse Levels.... . ............................... 0.8 Volt to 2.0 Volts
Input Rise and Fall Times .............................................. 10 ns
Input and Output Timing Levels .................................. 1.5 lIolts
Output Load .................................. l TTL Gate and CL ~ 100 pF
READ (NOTE 11. WRITE (NOTE 2) CYCLES
MCM6641-20
MCM66L41-20
Parameter
Read Cycle Time
MCM6641-25
MCM66L41-25
MCM6641-30
MCM6641-45
MCM66L41-30 MCM66 L41-45
Svmbol
Min
Max
Min
Max
Min
Max
Min
Max
Units
tRC
200
-
250
-
300
-
450
-
ns
tA
200
450
ns
70
-
85
-
100
-
120
ns
-
10
-
10
-
10
-
ns
100
ns
Chip Selection to Output Valid
tso
-
Chip Selection to Output Active
tsx
10
Output 3-State From Deselection
tOTO
Output Hold From Address Change
tOHA
50
50
50
50
ns
twc
200
250
300
450
ns
tw
100
125
150
200
tWR
0
Access Time
Write Cycle Time
Write Time
Write Release Time
250
40
-
tOTW
Data to Write Time Overlap
tow
100
Data Hold From Write Time
tOH
0
60
0
·40
Output 3-5tate From Write
_.
-
0
80
0
60
-
-
0
80
150
125
-
300
0
ns
-
ns
100
ns
ns
200
-
0
-
ns
REAO CYCLE TIMING
(WHELD HIGH)
tAC
jooIf---------
----------------~
tA -------I~
Address
Oout----------------------------------~--------4e~r_------~~~----------------NOTES:
1. A Read occurs during the overlap of a low S and a high W.
2. A Write occurs during the overlap of a low S and a low W.
3. If the S low transition occurs simultaneously with the
W low transition,
2-107
the output buffers remain in a high-impedance state.
•
•
MCM6641-MCM66L41
WRITE CYCLE TIMING (Note 31
144._------------
Address
~C
®
MCM6810
1.0 MHz
MCM68A10
1.5 MHz
MCM68B10
2.0 MHz
MOTOROLA
MOS
128 X 8-BIT STATIC RANDOM ACCESS MEMORY
(N-CHANNEL, SILICON-GATE I
The MCM6810 is a byte-organized memory designed for use iI,
bus-organized systems. It is fabricated with N-channel silicon-gate
128 X 8-BIT STATIC
RANDOM ACCESS
MEMORY
technology. For ease of use, the device operates from a single power
supply, has compatibility with TTL and DTL, and n""ds no
clocks or refreshing because of static operation.
The
memory is compatible with the M6800 Microcomputer
Family,
providing random storage in byte increments. Memory
expansion is provided through multiple Chip Select inputs.
•
P SUFFIX
PLASTIC PACKAGE
CASE 709·02
Organized as 128 Bytes of 8 Bits
•
Static Operation
•
Bidirectional Three-State Data Input/Output
•
Six Chip Select Inputs (Four Active Low, Two Active Highl
•
Single 5-Volt Power Supply
•
•
TTL Compatible
Maximum Access Time = 450 ns - MCM6810
360 ns - MCM68A 10
250 ns - MCM68Bl0
~
~UU!I"-
PIN ASSIGNMENT
GNO[~
1.0 MHz
MC6810P, L
MC6810CP, CL
MC6810BJCS
MC6810CJCS
MIL-STD-883B
MIL-STD-883C
1.5 MHz
MC68Al0P, L
MC68Al0CP, CL
2.0 MHz
MC68Bl0P, L
2
23
Vee
AO
Al
01 [ 3
22
02[ 4
21
A2
03[ 5
20
A3
04[ 6
19
A4
05[ 7
18
A5
06[ 8
17
A6
07[ 9
16
R/W
eSO[ 10
15
e55
o to + 70°C
Cs1[ 11
14
e54
-40 to +85 0 C
Cs2[ 12
13
e53
ORDERING INFORMATION
Device
, CERAMIC
""""
PACKAGE
CASE 716-06
Dol
Speed
~
Temperature Range
o
to 70°C
-40 to +85 0 C
- 55 to + 125°C
o to + 70°C
M6800 MICROCOMPUTER FAMILY
BLOCK DIAGRAM
r-----..,
MCM6810 - RANDOM ACCESS MEMORY
BLOCK DIAGRAM
Data
Bu,
Memory Address
and Control
Address Data
Bus
Bus
OS948717-78
2-109
•
•
MCM6810eMCM68A10eMCM68B10
MAXIMUM RATINGS
Symbol
Value
Unit
Supply Voltage
VCC
-0.3 to +7.0
Vdc
Input Voltage
Vin
-0.3 to +7.0
Vdc
Operating Temperature Range
TA
°c
°C/W
Rating
Storage Temperature Range
Tstg
TL to TH
Oto 70
-40 t085
-.55 to 125
-65 to +150
Thermal Resistance
8JA
82.5
This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however,
it is advised that normal precautions be
taken to avoid application of any voltage
higher than maximum rated voltages to
this high impedance circuit.
°c
ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ±5%. VSS = O. TA = TL to TH unless otherwise noted. I
Symbol
Min
Typ
M..
Unit
lin
-
-
2.5
~Adc
VOH
2.4
-
-
Vdc
VOL
-
-
0.4
Vdc
ITSI
-
-
10
~Adc
ICC
-
-
80
100
mAde
Input Capacitance (An. R/W. CS n • CSnl
(Vi" = O. T A = 2S oC. f = 1.0 MHzl
Cin
-
-
7.5
pF
Output Capacitance (On)
Cout
-
-
12.5
pF
Characteristic
Input Current (An. R/W. CS n • CSnl
(Vin = 0 to 5.25 VI
Output High Voltage
IiOH = -205 ~AI
Output Low Voltage
IiOL = 1.6 mAl
Output Leakage Current (Three-State)
(CS = 0.8 V or CS = 2.0 V. Vout =0.4 V to 2.4 VI
1.0 MHz
1.5.2.0 MHz
Supply Current
(VCC = 5.25 V. all other pins groundedl
(V out = O. TA = 25°C. f = 1.0 MHz. CS0 =01
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Input High Voltage
Input Low Voltage
BLOCK DIAGRAM
2
AO
A1
A2
A3
A4
A5
A6
23
22
21
20
19
18
17
CS5
CS4
,.
CS3
13
CS2
CS1
12
CSO
10
3
•
Address
Decode
00
01
02
03
5
6
7
8
05
06
~
07
O'
15
Vee
= Pin 24
3nd = Pin 1
"
2-110
MCM6810-MCM68A10-MCM68B10
FIGURE 1 - AC TEST LOAD
5.0 V
AC TEST CONDITIONS
Condition
AL = 2.5k
Value
Input Pulse Levels
0.8 V '02.0 V
Test Poin t <>-....----,,"~F-------
2.0 V
AddreSS~;8
V
.
......
'AS
2.0V
CS---------------+~~~~
0.8 V
R/Vii
0.8 V
r~'" 'osw - - - - t
Oa'a 'n
'H
r-
'T.~7'7'7'7~"7'"'T"7~"7'"~T'?'/j'7'@//////O'TT7'T'77'7'7"r~'"Jc-;~=:~,,~---o--a,--a'n-s,-ab-'e-----"J~#/m~
Wffi
=
Don', Care
Note: CS and
Cs
can be enabled for consecutive write cycles
provided R/W is strobed to V I H before or coincident
with the Address change, and remains high for time tAS'
2-112
®
MCM2532
MCM25L32
MOTOROLA
4096 x 8-BIT UV ERASABLE PROM
MOS
The MCM2532/25L32 is a 32,768-bit Erasable and Electrically
Reprogrammable PROM designed for system debug usage and similar
applications requiring nonvolatile memory that could be reprogrammed
periodically. The transparent window in the package allows the memory
content to be erased with ultraviolet light.
For ease of use, the device operates from a single power supply and
has static power-down mode. Pin-for-pin compatible mask programmable ROMs are available for large volume production runs of systems
initially using the M CM2532.
•
•
•
•
•
•
IN-CHANNEL, SiliCON-GATE I
4096 X a-BIT
UV ERASABLE PROM
Single +5 V Power Supply
Organized as 4096 Bytes of 8 Bits
Automatic Power-Down Mode IStandby)
Fully Static Operation INo Clocks)
TTL Compatible During Both Read and Program
Maximum Access Time=450 ns MCM2532
350 ns MCM2532-35
250 ns MCM2532-25
l SUFFIX CERAMIC PACKAGE
ALSO AVAilABLE - CASE 716
• Pin Compatible with MCM68A332 Mask Programmable ROMs
• Low Power Version
MCM25L32 Active - 50 mA Max
Standby - 10 mA Max
MCM25L32-25 Active - 70 mA
Standby - 15 mA
PIN ASSIGNMENT
Vee
A8
A9
Vpp
E/Progr
MOTOROLA'S PIN-COMPATIBLE EPROM FAMILY
:12K
A10
18K
A11
D07
D06
D05
D04
D03
MCM88784
MOTOROLA'S PIN·COMPATIBLE ROM FAMILY
32K
18K
AT
AI
'PIN NAMES
A............... .
DO.
E/Progr.
"
03
...... Address
Data Input/Output
Dual Function Enable
(Power-Down/Program Pulsel
·New Industry standard nomenclature
MCM88A318E
INDUSTRY STANDARD PINOUTS
DS9816/4-80
2-113
•
MCM2532-MCM25L32
ABSOLUTE MAXIMUM RATINGS
Rating
Value
-lOto +80
Temperature Under Bias
o to
Operating Temperature Range
'e
'e
-65 to + 125
'e
All Input/Output Voltages with
Respect to VSS
+6 to -0.3
Vdc
Vpp Supply Voltage with Respect to VSS
+28to -0.3
Vdc
Storage Temperature
•
+ 70
Unit
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric fields; however. it is advised that normal precautions be taken to avoid application of any voltage
higher than maximum rated voltages to this highimpedance circuit .
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restncted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
MODE SELECTION
Pin Number
9-11,
13-17
DQ
Mode
Read
Output Disable
12
VSS
Data Out VSS
High Z VSS
Standby
High Z
VSS
Program
Data In
VSS
Program Verify
Data Out VSS
High Z Vss
Program Inhibit
20
EjProgr
21
Vpp
24
VCC
VIL
5V
Vee
VIH
VIH
Pulsed
VIH to VIL
5 to 25 V
Vce
5V
Vee
VpPH
Vee
VIL
5V
Vee
VIH
VPPH
Vee
BLOCK DIAGRAM
Data Input/Output DQO-DQ7
FIGURE 1 - AC TEST LOAD
~
5.0 V
Test Point o---r--.,....-I~r--1
·100 pF
MMD6150
or Equiv.
MMD7000
or Equiv.
Y Gating
AO-A11
·Includes Jig Capacitance
Memory
Matrix
1256 x 1281
2-114
=
MCM2532-MCM25L32
CAPACITANCE (f = 1.0 MHz, T = 25°C, periodically sampled rather than 100% tested. I
Characteristic
Input Capacitance (Vin = 0 VI
Output Capacitance (Vout - 0 VI
Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C= lA-tlaV.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Fully operating voltage and temperature range unless otherwise noted I
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Min
Typ
Max
Unit
MCM25L32/MCM2532
MCM2532-35/ MCM2532-25
VCC
4.75
4.5
5.0
5.0
5.25
5.5
Vdc
M CM25L32-35/ M CM25L32-25
Vpp
VCC-0.6
2.2
-0.1
5.0
VCC+0.6
VCC+ 1.0
0.65
Parameter
Supply Voltage"
Input High Voltage
VIH
Input Low Voltage
VIL
-
-
Vdc
Vdc
RECOMMENDED DC OPERATING CHARACTERISTICS
Characteristic
MCM2532
Min Max
MCM25L32
Min Max
Condition
Symbol
Vin-5.25 V
lin
10
10
uA
Vout-5.25 V
ILO
10
10
I'A
E=VIH
ICC1
-
25
-
10
rnA
ICC1
-
25
-
15
rnA
E=VIL
ICC2
-
100
-
50
rnA
E=VIL
Vpp-5.65 V
ICC2
IpPl
-
120
-
70
rnA
5.0
'mA
Output Low Voltage
10l -2.1 rnA
V
IIOH--400I'A
VOL
VOH
0.45
Output High Voltage
Address and E Input Sink Current
Output Leakage Current
VCC Supply Current" (Standbyl
MCM2532
MCM2532-35
VCC Standby Current" (Standbyl
MCM2532-25
V CC Supply Current" (Activel
MCM2532
MCM2532-35
V CC Supply Current" (Activel
MCM2532-25
Vpp Supply Current"
E=VIH
5.0
-
0.45
2.4
2.4
Unit·
V
"VCC must be applied simultaneously or prior to Vpp. VCC must also be switched off simultaneously with or after Vpp. With Vpp connected
directly to VCC during the read operation, the supply current would be the sum of IPP1 and ICC. The additional 0.6 V tolerance on Vpp makes
it possible to use a driver circuit for switching Vpp supply from VCC in Read mode to + 25 V for programming. Typical values are for
T A = 25°C and nominal supply voltages.
AC READ OPERATING CONDITIONS AND CHARACTERISTICS
(Full Operating Voltage and Temperature Range Unless Otherwise Notedl
Input Pulse levels....................... 0.65 Volt and 2.2 Volts
Input Riseand Fall Times ................................ 20ns
Characteristic
Input and Output Timing levels ................. 0.8 and 2.0 Volts
Output load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. See Figure 1
Symbol
MCM2532-25
Max
Min
Address Valid to Outout Valid IE/Proor-VIII
tAVOV
-
250
E to Outout Valid
i: to High Z Output
tElOV
tEHOZ
0
250
100
tAXDX
0
-
Data Hold from Address
(E- VIU
2-115
MCM2532-36
Max
Min
MCM2632
Min Max
-
350
350
-
450
450
0
0
100
0
100
0
Unit
ns
ns
ns
ns
•
MCM2532-MCM25L32
READ MODE TIMING DIAGRAMS I!:=VIU
A"~".'4
o IData Dutl
A~~''',"
~
STANDBY MODE
A IAddressl
l:AProgrl
Address Valid
I
-
_ _- J
a IData Outl
Output Valid
New Address Valid
\
Siandby Mode
I)-----High Z
-
Active Mode
"CO,
~_-------,.)--
C
Output Valid
.
DC PROGRAMMING CONDITIONS AND CHARACTERISTICS
ITA=25°C±5'C)
RECOMMENDED PROGRAMMING OPERATION CONDITIONS
Symbol
Min
Nom
Max
Unit
VCC.VPPL
VpPH
4.75
24
5.0
25
5.25
26
Vdc
VIH
VIL
2.2
-
VCC+l
0.65
Parameter
Supply Voltage
Input High Voltage for Data
Input Low Voltage for Data
-0.1
Vdc
Vdc
·VCC must be applied simultaneously or prior to Vpp. VCC must also be switched off simultaneously with or after Vpp. The
device must not be inserted into or removed from a board with VPP at +25 V. VPP must not exceed the +26 V maximum
specifications.
PROGRAMMING OPERATION DC CHARACTERISTICS
Condition
Symbol
Min
Typ
Max
Unit
Address and EI Progr Input Sink Current
Vin = 5.25 V10.45 V
III
E/Progr= VIH
IPPl
-
10
Vpp Supply Current IVpp=25 V ± 1 VI
-
"Adc
mAde
VPP Programming Pulse Supply Current IVpp = 25 V ± 1 VI
E/Progr= VIL
IPP2
-
-
Characteristic
VCC Supply Current - MCM2532
10
30
160
ICC
mAde
mAde
AC PROGRAMMING OPERATING CONDITIONS AND CHARACTERISTICS
Symbol
Min
Max
Unit
Address Setup Time
tAVEL
2.0
-
I's
Vpp Setup Time
Data Setup Time
tPHEL
tDVEL
0
ns
2.0
-
Characteristic
""
""
Address Hold Time
tEHAX
2.0
V PP to Enable Low Time
Data Hold Time
tPLEL
tEHOZ
0
2.0
Vpp Hold Time
tEHPL
Enable IProgram) Active Time
tELEH
0
1·
55
ms
Enable IE/Progr) Pulse Transition Time
tTIPE)
5
-
ns
Vpp Rise and Fall Time from 5 to 25 V
tR. tF
0.5
2
""
-
"If shorter than 45 ms (min) pulses are used, the same number of pulses should be applied after the specific data has been verified.
2-116
ns
"s
ns
MCM2532-MCM25L32
PROGRAMMING OPERATION TIMING DIAGRAM
Program
VIH------,
A (Addressl
VIL------..J
Program Verifv----..f
r----
Address N Valid
tAVEL
-----+j
---tEHAX:---+t
""
.
1
......
Jr".....:....-------'--'"'\l
VOHIVIH
o or Q (Datal - - - - - - H i - Z - - - - - - - < . I
VOLIVIL
1'---:------;--"'[
Output Valid
Ir--~
tELQV
VIH---------+-----~
E/Progr
VIL
PROGRAMMING INSTRUCTIONS
After the completion of an ERASE operation, every bit in
the device is in the "'" state (represented by Output High),
Data are entered by programming zeros (Output Low) into
the required bits. The words are addressed the same way as
in the READ operation. A programmed "0" can only be
changed to a "'" by ultraviolet light erasure.
To set the memory up for PROGRAM mode, the VPP input (pin 2') should be raised to + 25 V. The V CC supply
voltage is the same as for the READ operation. Programming
data is entered in 8-bit words through the data out (DO) terminals while E/Progr is high. ·Only "D's" will be programmed
when "D's" and ""s" are entered in the data word.
After address and data setup, a 50 ms program pulse (VIH
to VIL) is applied to the E/Progr input. A program pulse is
applied to each address location to be programmed. To
minimize programming time, a 2 ms pulse width is recommended. The maximum program pulse width is 55 ms;
therefore, programming must not be attempted with a dc
signal applied to the E/Progr input.
Multiple MCM2532s may be programmed in parallel with
the same data by connecting together like inputs and apply-
ing the program pulse to the 1:1 PrOgr inputs. Different data
may be programmed into multiple MCM2532s connected in
parallel by using the PROGRAM INHIBIT mode. Except for
the E/Progr pin, all like inputs may be common.
PROGRAM VERIFY for the MCM2532 is the read operation.
READ OPERATION
After access time, data is valid at the outputs in the READ
mode.
ERASING INSTRUCTIONS
The MCM2532/25 L32 can be erased by exposure to high
intensity shortwave ultraviolet light, with a wave-length of
2537 angstroms. The recommended integrated dose Ii.e.,
UV-intensity X exposure time) is '5 Ws/cm 2 As an example, using the "M·odel 30-000" UV-Eraser Turner Designs,
Mountain View, CA94043) the ERASE-time is 36 minutes.
The lamps should be used without shortwave filters and the
MCM2532125L32 should be positioned about one inch away
from the UV-tubes.
2-117
•
•
MCM2532·MCM25L32
TIMING PARAMETER ABBREVIATIONS
TIMING LIMITS
The table of timing values shows either a minimum or a
maximum limit for each parameter. Input requirements are
specified from the external system paint of view. Thus, address setup time is shown as a minimum since the system
must supply at least that much time (even though most
devices do not require it). On the other hand, responses from
the memory are specified from the device point of view.
Thus, the access time is shown as a maximum since the
device never provides data later than that time.
t X X X X
signal name from which interval is defined ~
transition direction for first signal
signal name to which interval is defined
transition direction for second Signal
III
The transition definitions used in this data sheet are:
H = transition to high
L = transition to low
V = transition to valid
X = transition to invalid or don't care
Z = transition to off (high impedance)
WAVEFORMS
Waveform
Symbol
Input
Output
Must Be
Will Be
Valid
Valid
~
From H to L
. From H to L
Jlll7
Change
From L to H
Will Change
From L to H
VllllYl
Don't Care:
Any Change
Permitted
Changing:
State
Change
==>-
Will Change
Unknown
High
Impedance
2-118
®
MCM2708
MCM27A08
MOTOROLA
1024 X 8 ERASABLE PROM
MOS
The MCM2708/27A08 is an 8192-bit Erasable and Electrically
Reprogrammable PROM designed for system debug usage and
similar applications requiring nonvolatile memory that could be
reprogrammed periodically. The transparent window on the package
allows the memory content to be erased with ultraviolet light.
Pin-far-pin mask-programmable ROMs are available for large volume
production runs of systems initially using the MCM2708/27A08.
•
Organized as 1024 Bytes of 8 Bits
•
Static Operati on
•
Standard Power Supplies of +12 V, +5 V and -5 V
•
Maximum Access Time = 300 ns 450 ns Low Power Dissipation
•
Chip-Select Input for Memory Expansion
TTL Compatible
•
Three-State Outputs
1024 X 8-BIT
UV ERASABLE PROM
MCM27A08
MCM2708
•
•
IN-CHANNEL, SILICON-GATE)
FRIT-SEAL CERAMIC PACKAGE
CASE 623A-02
•
Pin Equivalent to the 2708
•
Pin-for-Pin Compatible to MCM65308, MCM6830B or 2308
Mask-Programmable ROMs
CERAMIC PACKAGE
CASE 716-07
PIN CONNECTION OURING READ DR PROGRAM
Mode
Pin Number
9-11.13-17
1.2
18
19
20
21
24
Read
Dout
VSS
VSS
VDD
VIL
VaB
Vee
Program
Din
VSS
Pulsed
VDD
VIHW
Vaa
Vee
VIHP
I
A7
ABSOLUTE MAXIMUM RATINGS (1)
Rating
Operating Temperature
Value
Unit
o to +70
+35 to -0_3
°c
°c
Vdc
Vdc
Vdc
Vdc
Vdc
1.8
Watts
VOD with Respect to VaB
-65 to +125
+20 to -0_3
Vec and VSS with Respect to VBB
+15 to -0.3
Storage Temperature
All Input or Output Voltages with Respect to VSB during Read
CS/WE Input with Respect to
Vas
PIN ASSIGNMENT
during Programming
~!am InP.:'.t with Respect tOYSB
Power Dissipation
+15 to -0.3
+20 to -0.3
Note 1:
Permanent device damage may occur if
A6
Vee
A8
A5
A9
A4
VBB
A3
CS/WE
A2
VDD
Al
PROGR.
AO
D7
DO
D6
Dl
D5
D2
D4
VSS
D3
ABSOLUTE MAXIMUM RATINGS .re
exceeded. Functional operation should
be restricted to RECOMMENDED OP-
ERATING CONDITIONS. Exposure to
higher than recommended voltages for
extended periods of time could affect
device reliability.
DS9440 R2/1-79
2-119
MCM27OS-MCM27AOS
BLOCK DIAGRAM
•
Y Gating
AO-A9
Memory
Matrix
164 x 128)
DC READ OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted.)
RECOMMENDED DC READ OPERATING CONDITIONS
Parameter
Symbol
Min
Nom
Max
Unit
VCC
4.75
5.0
5.25
Vdc
VOO
11.4
12
12.6
Vdc
Vaa
-5.25
-5.0
-4.75
Vdc
Input High Voltage
VIH
3.0
-
VCC+ LO
Vdc
Input Low Voltage
VIL
VSS
-
0.65
Vdc
Symbol
Min
Typ
Max
Unit
1
10
/LA
-
1
10
/LA
50
65
rnA
6
10
mA
30
45
mA
0.45
V
V
Supply Voltage
READ OPERATION DC CHARACTERISTICS
Characteristic
Address and CS Input Sink Current
Output Leakage Current
J
Condition
Yin = 5.25 V or Yin = VIL
Vout = 5.25 V, CS/WE = 5 V
lin
ILO
Worst-Case Supply Cun:ents
All Inputs High
100
ICC
-
CSIWE = 5.0 V, TA = OoC
laa
-
Output Low Voltage
IOL = 1.6 rnA
VOL
Output High Voltage
IOH =-100/LA
'yOH1
Output"High Voltage
IOH =-1.0rnA
VOO Supply Current
j--,.:V~C~C:..:S::u:::P:::P::.IY:...::C=u:..:rr.::e::.nt:""'_-II
VB8 Supply Curren.
I
Power Dissipation
(No.e 2)
(No'. 2)
TA = 70°C
3.7
-
-
VOH2
2.4
-
Po
-
-
._.
800
V
mW
Not. 2:
The total power dissipation is specified at 800 mW. It is not calculable by summing the various current (100. ICC. and laa) multiplied by
their respective voltages, since current paths exist between the various power supplies and VSS. The 100, ICC. and laa currents should be
used to determine power supply capacity only_
Ves must be applied prior to Vee and VDD- Vee must also be the last power supply switched off.
2-120
MCM2700-MCM27AOO
AC READ OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted.)
(All timing with tr = tf = 20 ns, Load per Note 3)
MCM2708
MCM27A08
Symbol
Min
Typ'
Max
Min
Typ
Max
Unit
Address to Output Delay
tAO
220
300
-
280
450
ns
Chip Select to Output Delay
tco
-
60
120
-
60
120
ns
Data Hold from Address
tDHA
0
-
-
0
-
Data Hold from Deselection
tDHD
0
120
0
Characteristic
ns
120
ns
CAPACITANCE (periodically sampled rather than 100% tested)
Characteristic
1nput Capacitance
Condition
Symbol
Typ
Max
Unit
Vin - 0 V. TA = 25°C
Cin
4.0
6.0
pF
V out = 0 V. TA = 25°C
Cout
8.0
12
pF
(f= 1.0 MHz)
Output Capacitance
(f = 1.0 MHz)
Note 3:
Output Load = 1 TTL Gate and CL = 100 pF (includes Jig Capacitance)
Timing Measurement Reference Levels:
Inputs:
O.S V and 2.8 V
Outputs: 0.8 V and 2.4 V
AC TEST LOAD
5.0 V
Test Pomt 0--""'1......-
.....- , . . -..
100pF';::"
--
MMD6150
or Equiv
MMD7000
or Equiv
-Includes Jig Capacitance
·-For VOH'
READ OPERATION TIMING DIAGRAM
Address
2-121
MCM27OS-MCM27AOS
DC PROGRAMMING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted.)
RECOMMENDED PROGRAMMING OPERATING CONDITIONS
Symbol
Min
Nom
Max
Unit
VCC
4.75
5.0
5.25
Vde
VDD
11.4
12
12.6
Vdc
Vaa
-5.25
-5.0
-4.75
Vde
Input High Voltage for All Addresses and Data
VIH
3.0
VCC+l.0
Vde
Input Low Voltage (except Program)
VIL
0.65
Vde
VIHW
VSS
11.4
12
12.6
Vde
Program Pulse Input High Voltage (Note 4)
VIHP
25
27
Vde
Program Pulse Input Low Voltage (Note 5)
VILP
VSS
-
1.0
Vde
Symbol
ILl
Min
-
Program Pulse Source Current
IIPL
Program Pulse Sink Current
IIPH
Parameter
Supply Voltage
CS/WE Input High Voltage
(Note 41
Note 4: Referenced to V S5.
Nota 5: VIHP - VILP = 25 V min.
PROGRAMMING OPERATION DC CHARACTERISTICS
Characteristic
Condition
Address and CS/WE Input Sink Current
Yin = 5.25 V
Typ
Max
Unit
-
10
!,Ade
-
-
3.0
mAde
-
20
50
65
mAde
mAde
6
10
mAde
30
45
mAde
Worst-Case Supply Currents
100
V CC Supply Current
All Inputs High
ICC
-
Vaa Supply current
CS/WE = 5 V. TA = OoC
laa
-
VDD Supply Current
AC PROGRAMMING OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature unless otherwise noted.)
Characteristic
Symbol
Min
Max
Unit
Address Setup Time
tAS
10
!,s
CS/wE Setup Time
tcss
10
-
Data Setup Time
tDS
10
Address Hold Time
tAH
1.0
CS/WE Hold Time
tCH
0.5
Data Hold Time
tDH
1.0
Chip Deselect to Output Float Delay
tDF
0
120
ns
tDPR
-
10
!,s
Program to Read Delay
!,s
!,s
!,s
-
!,s
!,s
Program Pulse Width
tpw
0.1
1.0
ms
Program Pulse Rise Time
tPR
0.5
2.0
!,S
Program Pulse Fall Time
tpF
0.5
2.0
!,S
2-122
MCM2708-MCM27A08
PROGRAMMING OPERATION TIMING DIAGRAM
\ 4 - - - - - - - - - - - - - - 1 of N Program Loops -------------<-+00--- READ(After N
Program
Loops)
CS/WE
'CH
---+11-+0Note 6
Address 0
tAH ___
VIH
Data Out
Data
Valid
tDH -4---1--
tPR--l---+------tPw--4---i-o>--- tpF
Program
Pulse
VIL-------J
Note 6: The CS/WE transition must occur after the Program Pulse transition and before the Address Transition.
2-123
•
MCM27OB·MCM27AOB
PROGRAMMING INSTRUCTIONS
After the completion of an E RASE operation, every
bit in the device is in the "1" state (represented by
Output High). Data are entered by programming zeros
(Output Low) into the required bits. The words are
addressed the same way as in the READ operation. A
programmed "0" can only be changed to a "1" by ultraviolet light erasure.
To set the memory up for programming mode, the
CSIWE input (Pin 20) should be raised to +12 V. Programming data is entered in 8-bit words through the
data output terminals (DO to D7).
Logic levels for the data lines and addresses and the
supply voltages (VCC, VDD, Vaa) are the same as for the
READ operation.
After address and data setup one program pulse per
address is applied to the program input (Pin 18). A pro·
gram loop is a full pass through all addresses. Total
programming time, TPtotal = N x tpw ;;. 100 ms. The
required number of program loops (N) is a function of the
program pulse width (tPW), where: 0.1 ms .;; tpw .;;
1.0 ms; correspondingly N is: 100';; N ';;1000. There
must be N successive loops through all 1024 addresses. It
is not permitted to apply more than one program pulse in
succession to the same address (Le., N program pulses to
an address and then change to the next address to be programmed). At the end of a program sequence the CSIWE
falling edge transition must occur before the first ~ddress
transition, when changing from a PROGRAM to a READ
cycle. The program pin (Pin 18) should be pulled down
to V ILP with an active device, because this pin sources a
small amount of current "IPL) when CSIWE is at VIHW
(12 V) and the program pulse is at V ILP'
EXAMPLES FOR PROGRAMMING
Always use the Tpiotal = N x tpw;;' 100 ms relationship.
1. All 8192 bits should be programmed with a 0.2 ms
program pulse width .
The minimum number of program loops:
N -_ TPtotal = 100 ms -_ 500. One program loop
tpw
0.2 ms
consists of words 0 to 1023.
2. Words 0 to 200 and 300 to 700 are to be programmed. All other bits are "don't care". The
program pulse width is 0.5 ms. The minimum
100
number of program loops, N = D.5 = 200. One
program loop consists of words 0 to 1023. The
data entered into the "don't care" bits should be
all ls.
3. Same requirements as example 2, but the EPROM is
now to be updated to include data for words 850
to 880. The minimum number of program loops is
the same as in the previous example, N = 200. One
program loop consists of words 0 to 1023. The data
entered into the "don't care" bits should be all 15.
Addresses 0 to 200 and 300 to 100 must be reprogrammed with their original data pattern.
ERASING INSTRUCTIONS
The MCM2708/27A08 can be erased by exposure to
high intensity shortwave ultraviolet light, with a wavelength of 2537 A. The recommended integrated dose (Le.,
UV-intensity x exposure time) is 12_5 Ws/cm 2. As an
example, using the "Model 30-000" UV-Eraser (Turner
Designs, Mountain View, CA94043) the ERASE-time is
30 minutes. The lamps should be used without shortwave
filters and the MCM2708/27 A08 should be positioned
about one inch away from the UV-tubes.
2·124
®
MCM2716
MCM27L16
MOTOROLA
2048 x 8-BIT UV ERASABLE PROM
MOS
(N-CHANNEL, SILICON-GATE)
The MCM2716127L16 is a 16,384-bit Erasable and Electrically
Reprogrammable PROM designed for system debug usage and similar
applications requiring nonvolatile memory that could be reprogrammed
periodically. The transparent lid on the package allows the memory content to be erased with ultraviolet light.
For ease of use, the device operates from a single power supply and
has a static power-down mode. Pin-for-pin mask programmable ROMs
are available for large volume production runs of systems initially using
the MCM2716/27L 16.
2048 X 8-BIT
UV ERASABLE PROM
• Single 5 V Power Supply
• Automatic Power-down Mode (Standby)
• Organized as 2048 Bytes of 8 Bits
• Low Power Version 27L16127L 16-35 Active 50 mA Max
Standby 10 mA Max
27L16-25 Active 70 mA Max
Standby 15 mA Max
L SUFFIX CERAMIC PACKAGE
ALSO AVAILABLE - CASE 716
• TTL Compatible During Read and Program
• Maximum Access Time=450 ns MCM2716
350 ns MCM2716-35
250 ns MCM2716-25
PIN ASSIGNMENT
• Pin Equivalent to Intel's 2716
• Pin Compatible to MCM68A316E
• Output Enable Active Level is User Selectable
14K
Vee
A7
MOTOROLA'S PIN·COMPATIBLE EPROM FAMILY
32K
MOTOROLA'S PIN·COMPATIBLE ROM FAMILY
32K
A6
AS
A5
A9
A4
Vpp
A3
IT
A2
Al0
Al
E/Progr
AO
D07
DOO
D06
DOl
D05
D02
D04
VSS
D03
1,,,
.........
,
·Pin NameS
11
11
UI
OJ
MCMllllA318E
A
. Address
DO .... Data Input/Output
E/Progr .... Chip Enable/Program
G .... Output Enable
• New Industry standard nomenclature
INDUSTRY STANDARD PINOUTS
DS9817/4-80
2-125
•
•
MCM2716-MCM27L 16
ABSOLUTE MAXIMUM RATINGS
Rating
Temperature Under Bias
Value
Unit
-10to +00
·C
a to
Operating Temperature Range
+ 70
-65 to + 125
·C
All Input or Output Voltages with Respect to VSS
+6 to -0.3
Vdc
VPP Supply Voltage with Respect to VSS
+28 to -0.3
Vdc
Storage Temperature
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage
higher than maximum rated voltages to this highimpedance circuit.
·C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
MODE SELECTION
Pin Number
9-11,
13-17
DQ
12
VSS
18
E/Progr
Data Out
High Z
VSS
VSS
VIL
Don't Car~
Standby
High Z
VSS
Program
Data In
VSS
Program Verify
Data Out
VSS
Program Inhibit
High Z
VSS
Mode
Read
Output Disable
20
21
Vpp
VCC
VIL
VCC'
VCC
VIH
Don't Care
VCC'
VCC
VCC'
VCC
VIH
VIHP
VCC
VIL
VIL
VIL
VIH
VIHP
VIHP
VCC
VCC
VIH
Pulsed
VIL to VIH
'In the Read Mode if VpP",VIH, then G (active lowl
VPPSVI'L, ihen G (active highl
BLOCK DIAGRAM
Data Input/Output DOo.DQ7
~
FIGURE 1 - AC TEST LOAD
5.0V
l:/Progr
G
Test POint <>---p---~--iI4I--+
Y Gating
'106 pF
Memory
Matrix
1128 x 1281
'Includes Jig Capacitance
A(}'Al0
2-126
24
G*
MMD6150
or Equiv.
MMD7000
or Equiv.'
MCM2716-MCM27L 16
CAPACITANCE (1= 1.0 MHz, T =25°C, periodically sampled rather than 100% tested)
Characteristic
Input Capacitance (Vin = 0 V)
Output Capacitance (Vout=O VI
Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C
=~
I!J.V·
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted)
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Symbol
Min
Nom
Max
5.0
5.0
5.0
5.25
5.5
VCC+0.6
-
VCC+ 1.0
0.8
Input High Voltage
VIH
4.75
4.5
VCC-0.6
2.0
Input Low Voltage
VIL
-0.1
MCM27L 16/MCM2716
Supply Voltage'
MCM27L 16-351 MCM27L16-251 MCM2716-351 MCM2716-25
VCC
Vpp
Unit
Vdc
Vdc
Vdc
RECOMMENDED DC OPERATING CHARACTERISTICS
Characteristic
Condition
Symbol
MCM271S
Min Typ Max
MCM27L1S
Unite
Min Typ Max
Vin=5.25 V
lin
-
-
10
-
-
10
"A
Output Leakage Current
Vou t=5.25 V
G=5.0 V
ILO
-
-
10
-
-
10
"A
VCC Supply Current (Standby) 2716/2716-35
E/P!.ogr= VIH
G=VIL
ICCI
-
-
25
-
-
10
mA
ICCI
-
-
25
-
-
15
mA
ICC2
-
-
100
-
-
50
mA
ICC2
-
-
120
-
-
70
mA
IPPI
-
-
5.0
0.45
-
5.0
mA
-
-
0.45
V
-
2.4
-
-
V
Address, G and E/Progr Input Sink Current
E/P~gr=VIH
VCC Supply Current (Standby) 2716-25
V CC Supply Current IActive} 2716/2716-35
IOutputs Open}
VCC Supply Current (Active) 2716-25
(Outputs Open)
Vpp Supply Current'
Output Low Voltage
GIVIL
G=E/Progr=
VIL
G= E/Progr=
VIL
Vpp=5.85 V
IOL =2.1 mA
Output High Voltage
IOH- -4OO,.A
VOL
VOH
2.4
'VCC must be applied simultaneously or prior to Vpp. VCC must also be switched off simultaneously with or after Vpp. With Vpp connected
directly to VCC during the read operation, the supply current would then be the sum of IpPl and ICC. The additional 0.6 V tolerance on Vpp
makes it possible to use a driver circuit for switching theVpp supply pin from Vee in Read mode to ± 25 V for programming. Typical values are
for TA = 25°C and nominal supply voltages.
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise notedl
Input Pulse Levels. . . . . . . . . . . . .
. O.S Volt and 2.2 Volts
Input Rise and Fall Times .......................... 20 ns
Characteristic
Address Valid to Output Valid
EI Progr to Output Valid
Output Enable to Output Valid
tl Progr to
Hi-Z Output
Output Disable to Hi-Z Output
Data Hold from Address
Input and Output Timing Levels .......... 2.0 and O.S Volts
Output Load .............................. See Figure 1
MCM2716-25 MCM2716-3E MCM2716
Units
Min Max Min Max Min Max
Condition
Symbol
E/Progr=G=VIL
(Note 2)
tAVOV
-
250
tELOV
-
250
E/Progr- VIL
tGLOV
tEHOZ
-
150
-
0
100
E/Progr=VIL
tGHOZ
0
E/Progr=G=VIL
tAXDX
0
-
2-127
350
350
-
450
-
0
150
100
0
150
100
100
0
100
0
100
-
0
-
0
-
450
ns
•
MCM2716eMCM27L16
R~D MODE TIMING DIAGRAMS iE/Progr=VILl
Output Valid
STANDBY MODE (Output Enable = VILI
Standby Mode (EiProgr= VIHI
A IAddressl
Active Mode
tELQV (Note 21
Output Valid
Q (Data Outl
NOTE 2: tELQV is referenced to
EI Progr or stable address,
whichever occurs last.
DC PROGRAMMING CONDITIONS AND CHARACTERISTICS
(TA=25°C±5°CI
RECOMMENDED PROGRAMMING OPERATING CONDITIONS
Symbol
Min
Nom
Max
Supply Voltage
VCC
VPP
4.75
24
5.0
25
5.25
Input High Voltage for Data
VIH
VIL
2.2
-0.1
-
VCC + 1
0.8
Parameter
Input Low Voltage for Data
Unit
Vdc
26
Vdc
Vdc
PROGRAMMING OPERATION DC CHARACTERISTICS
Condition
Symbol
Min
Typ
Max
Unit
EI Progr Input Sink Current
Vin = 5.25 V10.45 ~
III
-
10
VPP Supply Current (Vpp = 25 V ± 1 VI
VPP Programming Pulse Supply Current (VPP = 25 V ± 1 VI
VCC Supply Current (Outputs Openl
E/Progr=VIL
IPPl
IPP2
"Adc
mAde
E/Progr= VIH
-
ICC
-
Characteristic
Address, G and
-
10
-
30
-
160
mAde
mAde
Unit
AC PROGRAMMING OPERATING CONDITIONS AND CHARACTERISTICS
Symbol
Min
Max
Address Setup Time
tAVEH
2.0
-
Output Enable High to Program Pulse
tGHEH
2.0
Data Setup Time
Address Hold Time
tDVEH
tELAX
2.0
2.0
Output Enable Hold Time
tELGL
2.0
Data Hold Time
tELQZ
2.0
VPP Setup Time
tPHEH
0
VPP to Enable Low Time
tELPL
tGHQZ
0
-
ns
0
150
ns
-
150
l'
55
ns
ms
Program Pulse Rise Time
tGlQV
tEHEL
tpR
5
Program Pulse Fall Time
tpF
5
-
ns
ns
Characteristic
Output Disable to High Z Output
Output Enable to Valid Data (E/Progr- VILl
Program Pulse Width
-
'If shorter than 45 ms (mini pulses are used, the same number of pulses should be applied after the specific data has been verified.
2-128
"s
"s
"s
"s
"s
"s
ns
MCM2716-MCM27L16
PROGRAMMING OPERATION TIMING DIAGRAM
Program Verify
Program
A (Address)
Address N Valid
io+----tELAX-----+i
G (Output
Enable)
tGHQZ
D or Q (Oata)
tGHEH
tOVEH
"--':;";";""--tEHEL
'E/Progr
tpR
tPF
j+-t PHEH
tt
ELPL
PROGRAMMING INSTRUCTIONS
After the completion of an ERASE operation, every bit in
the device is in the "1" state (represented by Output High),
Data are entered by programming zeros (Output Lowl into
the required bits, The words are addressed the same way as
in the READ operation, A programmed "0" can only be
changed to a "1" by ultraviolet light erasure.
To set the memory up for Program Mode, the Vpp input
(Pin 21) should be raised to + 25 V. The VCC supply voltage
is the same as for the Read operation and G is at VIH. Programming data is entered in a-bit words through the data out
mO) terminals. Only "O's" will be programmed when "O's"
and "1's" are entered in the 8-bit data word.
After address and data setup, a program pulse (VIL to
VIH) is applied to the EiProgr input. A program pulse is applied to each address location to be programmed. To
minimize programming time, a 2 ms pulse width is recommended. The maximum program pulse width is 55 ms;
therefore, programming must not be attempted with a dc
signal applied to the EiProgr input.
Multiple MCM2716s may be programmed in parallel by
connecting together like inputs and applying the program
pulse to the EI Progr inputs. Different data may be programmed into mUltiple MCM2716s connected in parallel by using
the PROGRAM INHIB)T mode. Except for the E/Progr pin,
all like inputs (including Output Enable) may be common,
2-129
The PROGRAM VERIFY mode with Vpp at 25 V is used to
determine that all programmed bits were correctly programmed.
READ OPERATION
After access time, data is valid at the outputs in the READ
mode. With stable system addresses, effectively faster access time can be obtained by gating the data onto the bus
with Ou'tput Enable,
The Standby mode is available to reduce active power
dissipation, The outputs are in the high impedance state
when the E/Progr input pin is high (VIH) independent of the
Output Enable input.
ERASING INSTRUCTIONS
The MCM2716127L 16 can be erased by exposure to high
intensity shortwave ultraviolet light, with a wavelength of
2537 angstroms, The recommended integrated dose (i.e"
UV-intensity X exposure time) is 15 Ws/cm 2. As an example, using the "Model 30-000" UV-Eraser (Turner Designs,
Mountain View, CA 94043) the ERASE-time is 36 minutes.
The lamps should be used without shortwave filters and the
MCM2716/MCM27L 16 should be positioned about one inch
away from the UV-tubes.
•
MCM2716eMCM27L 16
TIMING PARAMETER ABBREVIATIONS
TIMING LIMITS
t X X X X
signal name from which interval is defined ~
transition direction for first signal
signal name to which interval is defined
transition direction for second signal
The table of timing values shows either a minimum or a
maximum limit for each parameter. Input requirements are
specified from the external system point of view. Thus, address setup time is shown as a minimum since the system
must supply at least that much time leven though most
devices do not require it). On the other hand, responses from
the memory are specified from the device point of view.
Thus, the access time is shown as a maximum since the
device never provides data later than that time.
III
The transition definitions used in this data sheet are:
H = transition to high
L = transition to low
V = transition to valid
X = transition to invalid or don't care
Z = transition to off (high impedance)
WAVEFORMS
Waveform
Symbol
Input
Output
Must Be
Will Be
Valid
Valid
~
From H to L
Will Change
From H to L
~
Change
Will Change
From L to H
From L to H
:m:&&
Don't Care:
Changing:
Any Change
Permitted
Unknown
Change
==>-
State
High
Impedance
2-130
®
TM52716
TM527A16
MOTOROLA
MOS
2048 X 8 ERASABLE PROM
The TMS2716 and TMS27A 16 are 16,384-bit Erasable and
Electrically Reprogrammable PROMs designed for system debug
usage and similar applications requiring nonvolatile memory that
could be reprogrammed periodically _The transparent window on the
package allows the memory content to be erased with ultraviolet
light. The TMS2716 is pin compatible with 2708 EPROMs, allowing
easy memory size doubling.
•
IN-CHANNEL, SI LICON-GATE)
2048 X 8-BIT
UV ERASABLE PROM
Organized as 2048 Bytes of 8 Bits
•
Fully Static Operation (No Clocks, No Refresh)
•
Standard Power Supplies of + 12 V, +5 V, and -5 V
•
Maximum Access Time
•
Chip-Select Input for Memory Expansion
•
TTL Compatible - No Pull-up Resistors Required
•
Three-State Outputs for OR-Tie Capability
•
The TMS2716 is Pin Compatible to MCM2708 and
MCM68708 EPROMs
= 300 ns - TMS27A 16
450 ns - TMS2716
FRIT-SEAL PACKAGE
CASE 623A-02
CERAMIC PACKAGE
CASE 716-07
PIN ASSIGNMENT
BLOCK DIAGRAM
A7[~~VCCIE)
Data "Input/Output
OQO-OQ7
~A8
A6[ 2
23
A5[ 3
22 ~A9
A4[ 4
21 ~Vaa
A3[5
20 PAlO
A2[ 6
19 PVDD
Al[ 7
18
AO[ 8
17 ~DQ7
~"S
(Progr)
DOO[ 9
16 ~D06
DOl [ 10
15
D02 [ 11
14 PD04
VSS[ 12
13 PD03
Y Gating
AD-A10
~D05
PIN NAMES
Memory Matrix
AD-AID..
DOO-D07....
1128X 128)
IE) ..
5 ..
IProgr) ...
Vaa··
VCe.·
VDD··
VSS··
. ............. Address Inputs
. ... Data Input (Program or
Output IRead)
........ Program Enable
. .... Chip Select
....... ". Program Pulse
. ........... - 5 V Power Supply
.... + 5 V Power Supply
. + 12 V Power Supply
................... Ground
DS9618 R1/1-79
2-131
•
TMS2716-TMS27A16
ABSOLUTE MAXIMUM RATINGS (1)
Rating
Value
Unit
o to +70
°e
Storage Temperature
-65 to +125
°e
VOO with Respect to VSS
+20to -0.3
V
Vee and VSS with Respect to Vas
+15 to -0.3
V
All Input or Output Voltage with Respect to Vas During Read
+15 to -0.3
V
Operating Temperature
(E) Input with Respect to
Vas
Program Input with Respect to
During Programming
+20 to -0.3
V
Vas
+35 to -0.3
V
1.8
Watts
Power Dissipation
PIN CONNECTION DURING
READ OR PROGRAM
Pin Number
Mode
9-11,
13-17
Read
D out
Program
Din
18
24
VILor
VIH
Pulsed
Vee
VIHW
VIHP
NOTE 1: Permanent device damage may occur it ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
DC READ OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted)
RECOMMENDED DC READ OPERATING CONDITIONS
Parameter
Symbol
Min
Nom
Max
Unit
TMS2716
Vee
Vee
VBB
4.75
11.4
-5.25
5.0
12
-5.0
5.25
12.6
-4.75
V
V
V
TMS27A16
Vec
Vee
VBB
4.5
10.8
-5.5
5.0
12
-5.0
5.5
13.2
-4.5
V
V
V
Supply Voltage
Input High Voltage
VIH
2.2
-
Vee+ 1.0
V
Input Low Voltage
VIL
VSS
-
0.65
V
Symbol
Min
Typ
Max
Unit
lin
-
1
10
~A
1
10
~A
-
65
mA
READ OPERATING DC CHARACTERISTICS
Characteristic
Address Input Sink Current
Condition
Vin
= VCCmax or
Vin :: VIL
Output Leakage Current
V out - Vccmax and S = 5 V
ILO
V DD Supply Current
lee
VSS Supply Current
Worst-Case Supply Currents
All Inputs High
(E) = 5.0 V, TA = DoC
IBB
-
Output Low Voltage
IOL = 1.6mA
VOL
-
Output High Voltage
IOH =-100~A
VOHl
Output High Voltage
IOH - -1.0 mA
VOH2
Vee Supply Current
ICC
-
12
mA
45
mA
0.45
V
3.7
-
-
V
2.4
-
-
V
Vse must be applied pnor to Vee and VOD' VSS must also be the last power supply sWitched off.
CAPACITANCE (periodically sampled rather than 100% tested)
Characteristic
Input Capacitance
Condition
Symbol
Typ
Max
Unit
Vin=OV,TA=250e
Cin
4.0
6.0
pF
V out = 0 V, T A = 25°C
Cout
8.0
12
pF
(f = 1.0 MHz)
Output Capacitance
(f = 1.0 MHz)
2-132
TMS2716-TMS27A16
AC READ OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted)
(All timing with tr ~ tf ~ 20 ns, Load ~er Note 2)
TMS2716
Characteristic
TMS27A16
Symbol
Min
Max
Min
Max
Unit
Address to Output Delay
'AVQV
Chip Select to Output Delay
'SLQV
-
450
120
-
300
120
ns
Data Hold from Address
'AXQZ
10
-
10
Data Hold from Deselection
'SHQZ
10
120
10
NOTE 2: Output Load = 1 TTL Gate and CL '" 100 pF (Includes Jig Capacitance)
Timing Measurement Reference Levels - Inputs: 0.8 V and 2.8 V
ns
ns
~-
120
ns
AC TEST LOAD
Outputs: 0.8 V and 2.4 V
\
50 V
AL=2.2k
Tes! P(lInt
D---1r---.,.--......- ..
100 pF • ;:"'
37 k··
MMD6150
or E.qul~
MM[)lOQa
or Equlv
I
TIMING PARAMETER ABBREVIATIONS
TIMING LIMITS
t X X X X
""" "m,
'.om w'", '"''',,'', ,,"" 00 -'
transition direction for first signal
The table of timing values shows either a minimum or
I[I
a maximum limit for each parameter. Input requirements
are specified from the external system point of view.
signal name to which interval is defined
transition direction for second signal
Thus, address setup time is shown as a minimum since the
The transition definitions used in this data sheet are:
H ~ transition to high
L ~ transition to low
V ~ transition to valid
X
== transition to invalid or don't care
Z
~
system must supply at least that much time (even though
most devices do not require it). On the other hand,
responses from the memory are specified from the device
point of view. Thus, the access time is shown as a maxi-
mum since the device never provides data later than
that time.
transition to off (high impedance)
READ OPERATION TIMING DIAGRAM
Address Valid
Chip Select,
Data Out,
"'ncludes Jig Capacitance
··For VO H
S
Q
2-133
•
•
TMS2716-TMS27A16
DC PRO.GRAMMING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted)
RECOMMENDED PROGRAMMING OPERATING CONDITIONS
Symbol
Min
Nom
Max
Unit
Supply Voltage - TMS2716 and TMS27A16
VCC
VDD
VSS
4.75
11.4
-5.25
5.0
12
-5.0
5.25
12.6
-4.75
Vde
Vde
Vde
Parameter
Input High Voltage for Data
VIHD
3.8
VCC+ 1
Vdc
Input Low Voltage for Data
VILD
-
0.65
Vde
Input High Voltage for Addresses
VIHA
VSS
3.8
-
VCC+ 1
Vdc
Input Low Voltage for Addresses
VILA
-
0.4
Vde
Program Enable (E) Input High Voltage (Note 3)
VIHW
VSS
11.4
12
12.6
Vdc
Program Enable (EI Input Low Voltage (Note 3)
VILW-VCC
4.75
5.0
5.25
Vde
Program Pulse Input High Voltage (Note 3)
VIHP
25
27
Vde
Program Pulse Input Low Voltage (Note 4)
VILP
VSS
1.0
Vde
-
NOTE 3: Referenced to VSS.
NOTE 4: VIHP - VILP = 25 V min.
PROGRAMMING OPERATION DC CHARACTERISTICS
Characteristic
Condition
Symbol
Min
Typ
Max
Unit
-
10
~Ade
mAde
Program Pulse Source Current
IIPL
-
IIPH
-
-
3.0
Program Pulse Sink Current
20
mAde
Address Input Sink Current
Yin = 5.25 V
ILl
VOO Supply Current
Worst-Case Supply Currents
IDO
-
-
65
mAde
V CC Supply Current
All Inputs High
(E) = 5 V, T A = OoC
ICC
-
15
mAde
-
45
mAde
Vee Supply current
ISS
AC PROGRAMMING OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature unless otherwise noted)
Symbol
Min
Max
Unit
Address Setup Time
tAVPH
10
-
~s
(E) Setup Time
tEHPH
10
-
~s
Data Setup Time
10
Address Hold Time
tDVPH
tpLAX
1.0
(E) Hold Time
tPLEL
0.5
Data Hold Time
tpLDX
1.0
Program to Read Delay
tELQV
-
10
I'S
Program Pulse Width
tpHPL
0.1
1.0
ms
Characteristic
I'S
I'S
-
I'S
I'S
Program Pulse Rise Time
tpR
0.5
2.0
I'S
Program Pulse Fall Time
tPF
0.5
2.0
I'S
2-134
TMS2716-TMS27 A 16
PROGRAMMING OPERATION TIMING DIAGRAM
\-------------1
of N Program Loop.
------------oj..-.-
READ-
(After N
Program
Loop.)
Program
Enable, (E)
tpLEL --~-j4-
Note 5
tEHPH
VIHA
Address 0
VILA
Data Out
Valid
t?LOX
tOVPH
-~-+t---
tPA-~~-+_------tpHPL--~--~~--
V IHP - - - - r - - - - - {
f-----.I
Program
Pulse, P
V,LP-------------J
NOTE 5: This Program Enable tranistion must occur after the Program Pulse transition and before the Address Transition.
WAVEFORM DEFINITIONS
Waveform
Symbol
Input
Output
MUST BE
VALID
WILL BE
~
CHANGE
FROM H TO L
WILL CHANGE
FROM H TO L
-.!Zlll1
CHANGE
WILL CHANGE
FROM l TO H
FROM l TO H
Waveform
Svmbol
~
VALID
=:J---
2-135
Input
Output
DON'T CARE.
ANY CHANGE
CHANGING
PERMITTED
UNKNOWN
STATE
HIGH
IMPEDANCE
•
TMS2716-TMS27A16
PROGRAMMING INSTRUCTIONS
EXAMPLE FOR PROGRAMMING
Always use the TPtotal = N X tpHPL ~ 100 ms
relationship.
1. All 16,384 bits should be programmed with a 0.2 ms
program pulse width .
The minimum number of program loops:
After the completion of an ERASE operation, every bit
in the device is in the "1" state (represented by Output
High). Data are entered by programming zeros (Out·
put Low) into the required bits. The words are addressed
the same way as in the READ operation. A programmed
"0" can only be changed to a "1" by ultraviolet light
erasure.
To set the memory up for programming mode, the
VCC(E) input (Pin 24) should be raised to +12 V. Pro·
gramming data is entered in 8·bit words through the data
output terminals (000 to 007).
,The VOO and Vaa supply voltages are the same as for
the READ operation,
After address and data setup, one program pulse per
address is applied to the program input. A program loop is
a full pass through all addresses, Total programming timet
address, TPtotal = N X tPHPL ~ 100 ms, The required
number of program loops (N) is a function of the program
pulse width (tPHPLl where: 0.1 ms"; tpHPL ..; 1.0 ms;
correspondingly, N is: 100 ..; N ..; 1000. There must be
N successive loops through all 2048 addresses. It is not
permitted to apply more than one program pulse in
succession to the same address (i.e., N program pulses to
an address and then change to the next address to be
programmed). At the end of a program sequence the
Program Enable (E) falling edge transition must occur
before the first address transition, when changing from
a PROGRAM to a READ cycle. The program pin should
be pulled down to VI LP with an active device, because
this pin sources a small amount of current (lIPL) when
(EI is at VIHW (12 V) and the program pulse is at VILP.
N = TPtotal
tpHPL
= 100 ms = 500.
0.2 ms
One program loop consists of words 0 to 2047.
2. Words 0 to 200 and 300 to 700 are to be programmed. All other bits are "don't care". The program
pulse width is 0.5 ms. The minimum number of program
loops, N = 100/0.5 = 200. One program loop consists of
words 0 to 2047. The data entered into the "don't care"
bits should be all 1s.
3. Same requirements as example 2, but the EPROM is
now to b~ updated to include data for words 850 to 880.
The minimum number of program loops is the same as in
the previous example, N = 200. One program loop consists
of words 0 to 2047. The data entered into the "don't
care" bits should be all 1s. Addresses 0 to 200 and
300 to 700 must be reprogrammed with their original
data pattern.
ERASING INSTRUCTIONS
The TMS2716/27A16 can be erased by exposure to
high intensity shortwave ultraviolet light, with a wave·
length of 2537 it The recommended integrated dose (i.e.,
UV·intensity X exposure time) is 12.5 Ws/cm 2 . As an
example, using the "Model 30·000" UV ·Eraser (Turner
Designs, Mountain View, CA 94043) the ERASE·time is
30 minutes. The lamps should be used without shortwave
filters and the TMS2716/27A16 should be positioned
about one inch away from the UV-tubes.
2-136
®
MCM68708
MCM68A708
MOTOROLA
1024 X
MOS
a ERASABLE PROM
(N-CHANNEL, SILICON-GATEI
The MCM68708/68A708 is a 8192-bit Erasable and Electrically
Reprogrammable PROM designed for system debug usage and
similar applications requiring nonvolatile memory that could be
reprogrammed periodically. The transparent window on the package
allows the memory content to be erased with ultraviolet light.
Pin-for·pin mask-programmable ROMs are available for large volume
production runs of systems initially using the MCM68708/68A708.
•
1024 X a-BIT
UV ERASABLE PROM
Organized as 1024 Bytes of 8 Bits
•
Fully Static Operation
•
Standard Power Supplies of +12 V, +5 V and -5 V
•
Maximum Access Time
= 300
ns 450 ns -
MCM68A708
MCM68708
•
Low Power Dissipation
•
Chip-Select Input for Memory Expansion
•
TTL Compatible
•
Three-State Outputs
L SUFFIX
CERAMIC PACKAGE
CASE 716-07
PIN ASSIGNMENT
• Pin Equivalent to the 2708
•
A7[~ vee
Pin-for-Pin Compatible to MCM65308, MCM68308 or 2308
Mask-Programmable ROMs
•
A6[ 2
23
AS
A5[ 3
22
A9
A4[ 4
21
VBB
A3[ 5
20
GS/WE
Bus Compatible to the M6800 Family
PIN CONNECTION DURING READ OR PROGRAM
A2[ 6
19
VDD
Al[ 7
18
PROGR.
AO! 8
17
D7
DO[ 9
16
D6
Pin Number
Mode
9-11,13-17
12
18
19
20
21
24
Dl[ 10
15
D5
Read
D out
VSS
VSS
VDD
VIL
VBB
Vee
D2[ 11
14
D4
Program
Din
VSS
Pulsed
VIHW
VBB
VCC
VSS[ 12
13
D3
VDD
VIHP
I
MC6800
Microprocessor
I
MCM6S70S/6SA70S READ ONLY
MEMORY BLOCK DIAGRAM
M6800 MICROCOMPUTER FAMILY
BLOCK DIAGRAM
f------i
I
~
.--
MCM68708 ~
MCM68A 708
EPROM
Random
Access
Memory
~
Interface
Adapter
~
Interface
Memory
Matrix
j
(1024 x 81
r--
i
I
Data
Buffers
~OataBu5
'----
Selection
and Control
Adapter
Modem
J
MemoJ Address
Address Data
8us
and Control
Bus
DS9439 R1!1-79
2-137
•
MCM68708eMCM68A708
aLOCK DIAGRAM
Data Output
00-07
ABSOLUTE MAXIMUM RATINGS1
Program
CS/WE
Value
Unit
Rating
Operating Temperature
Storage Temperature
-65 to +125
°c
°c
VDD with Respect to Vee
+20 to -0.3
Vdc
VCC and VSS with Respect to Vae
+15 to -0.3
Vdc
All Input or Output Voltages with
+15 to -0.3
Vdc
+20 to -0.3
Vdc
o to
.70
Respect to Vas during Read
CS/WE Input with Respect to Vee
during Programming
Y Gating
Program Input with Respect to VaB
Power Dissipation
+35 to -0.3
Vdc
1.8
Watts
AO-A9
Note 1:
Permanent device damage may occur if ABSOLUTE MAXIMUM
RATINGS are exceeded. Functional operation should be restricted
to RECOMMENDED OPERATING CONDITIONS. Exposure to
higher than recommended voltages for extended periods of time
could affect device reliability.
Memory
Matrix
164 x 1281
DC READ OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted.)
RECOMMENDED DC READ OPERATING CONDITIONS
Parameter
Symbol
Min
Nom
Max
Unit
VCC
4.75
5.0
5.25
Vdc
VOO
11.4
12
12.6
Vdc
VeB.
-5.25
-5.0
-4.75
Vdc
Input High Voltage
VIH
VSS +2.0
VIL
VSS -0.3
VCC
VSS +0.8
Vdc
Input Low Voltage
-
Symbol
Supply Voltage
Vdc
READ OPERATION DC CHARACTERISTICS
Characteristic
Output Leakage Current
V DO Supply Current
V CC Supply Current
Vee Supply Current
I
I
Min
Typ
Max
Unit
= 5.25 Vor Vin = VIL
Vout = 5.25 V, CSIWE - 5 V
lin
-
1
10
I'A
ILO
-
1
10
I'A
Worst-Case Supply Currents
100
-
50
65
mA
All Inputs High
ICC
-
6
10
mA
leB
-
30
45
mA
-
-
VSS +0.4
-
BOO
Condition
Address and CS Input Sink Current
(Note 21
I
Vin
CS/WE
= 5.0 V, TA = OoC
Output Low Voltage
IOL -1.6mA
VOL
Output High Voltage
= -1001'A
TA = 700 C
VOH
Power Dissipation
IOH
(Note 2)
Po
VSS +2.4
-
-
V
V
mW
Note 2:
The total power dissipation is specified at 800 mW. It is not calculable by summing the various currents (100. ICC. and les) multiplied by
their r,espective voltages. since current paths exist between the various power supplies and VSS. The 100. ICC. and ISS currents should be
used to determine power supply capacity only.
Vas must be applied prior to Vee and VOO- VSS must also be the last power supply switched off,
2-138
MCM68708-MCM68A708
AC READ OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted.)
(All timing with tr = tf = 20 ns, Load per Note 3)
MCM68708
MCM68A708
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
Address to Output Delav
tAO
-
220
300
-
280
450
ns
Chip Select to Output Delay
tco
-
60
120
-
60
120
ns
Data Hold from Address
tDHA
10
-
-
10
-
-
ns
Data Hold from Deselection
tDHD
10
120
10
120
ns
Characteristic
CAPACITANCE Iperiodically sampled rather than 100% tested)
Characteristic
Input Capacitance
Condition
Symbol
Typ
Max
Unit
If.in = 0 V. TA = 25°C
Cin
4.0
6.0
pF
V out = 0 V. TA = 25°C
Cout
8.0
12
pF
(f=1.0MHz)
Output Capacitance
If = 1.0 MHz)
Not. 3:
Output Load
=
1 TTL Gate and CL = 100 pF (Includes Jig Capacitance)
Timing Measurement Reference Levels:
Inputs:
0.8 V and 2.8 V
Outputs: 0.8 V and 2.4 V
ACTESTLOAD
5.0 V
RL=2.2k
.....-I+-"
Test Point ()-~r--
'OOpF'
;;:~
24 k
MMD61S0
or Equiv
MMD7000
or Equiv
• Includes Jig Capacitance
READ OPERATION TIMING DIAGRAM
Address
2-139
•
MCM687OS-MCM68A7OS
DC PROGRAMMING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted.)
RECOMMENDED PROGRAMMING OPERATING CONDITIONS
Symbol
Min
Nom
Max
Unit
VCC
4.75
5.0
5.25
Vdc
VOO
11.4
12
12.6
Vdc
VSS
-5.25
-5.0
-4.75
Vdc
VIH
3.0
VCC+l.0
Vdc
VIL
0.65
Vdc
VIHW
VSS
11.4
12
12.6
Vdc
Program Pulse Input High Voltage (Note 4)
VIHP
25
27
Vdc
Program Pulse Input Low Voltage (Note 5)
VILP
VSS
-
1.0
Vdc
Symbol
Min
Typ
Max
Unit
ILl
-
-
10
I'Adc
3.0
mAde
20
50
65
mAde
mAde
6
10
mAde
30
45
mAde
Parameter
Supply Voltage
Input High Voltage for All Addresses and Data
Input Low Voltage (except Program)
CSIWE Input High Voltage
(Note 4)
Note 4: Referenced to VSS.
Note 5: VIHP - VILP = 25 V min.
PROGRAMMING OPERATION DC CHARACTERISTICS
Characteristic
Condition
Address and CS/WE Input Sink Current
Yin
= 5.25 V
Program Pulse Source Current
IIPL
Program Pulse Sink Current
IIPH
VOO Supply Current
Worst-Case SupplV CUrrents
100
VCC Supply Current
All Inputs High
ICC
Vas Supply current
CS/WE
= 5 V. TA = OoC
ISS
AC PROGRAMMING OPE~ATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature unless otherwise noted.)
Symbol
Min
Max
Unit
Address Setup Time
tAS
10
-
I'S
CS/WE Setup Time
tcss
10
-
I'S
Data Setup Time
tos
10
Address Hold Time
tAH
1.0
CSIWE Hold Time
tCH
0.5
Data Hold Time
tOH
1.0
Chip Deselect to Ouptut Float Delay
tOF
0
120
ns
tOPR
-
10
1"
Characteristic
Program to Read Delay
1"
-
I'S
I'S
IlS
Program Pulse Width
tpw
0.1
1.0
ms
Program Pulse Rise Time
tPR
tpF
0.5
2.0
IlS
0.5
2.0
IlS
Program Pulse Fall Time
2-140
MCM68708-MCM68A708
PROGRAMMING OPERATION TIMING DIAGRAM
/-------------1
of N Program Loops ----------~.j.-- READ-------
(After N
Program
Loops)
CS/WE
Note 6
Address 0
VIH
Data Out
Data
Valid
'DS
'DH ---if-----1---
'PR - - - f - - J - - - - - - - t PW ----1--1----
Program
Pulse
VIL------------~
Note 6: The CS/WE transistion must occur after the Program Pulse transition and before the Address Transistion.
2-141
•
•
MCM687OS-MCM68A7OS
PROGRAMMING INSTRUCTIONS
After the completion of an E RASE operation, every
bit in the device is in the "1" state (represented by
Output High). Data are entered by programming zeros
(Output Low) into the required bits. The words are
addressed the same way as in the READ operation. A
programmed "0" can only be changed to a "1" by ultra·
violet light erasure.
To set the memory up for programming mode, the
CS/WE input (Pin 20) should be raised to +12 V. Pro·
gramming data is entered in 8·bit words through the
data output terminals (DO to 07).
Logic levels for the data lines and addresses and the
supply voltages (VCC, VDD, V8B) are the same as for the
READ operation.
After address and data setup one program pulse per
address is applied to the program input (Pin 18). A pro·
gram loop is a full pass through all addresses. Total
programming time, TPtotal = N x tpw ;;;. 100 ms. The
required number of program loops (N) is a function of the
program pulse width (tPW>' where: 0.1 ms .;; tpw .;;
1.0 ms; correspondingly N is: 100';; N .;; 1000. There
must be N successive loops through all 1024 addresses. It
is not permitted to apply more than one program pulse in
succession to the same address (i.e., N program pulses to
an address and then change to the next address to be pro·
grammed). At the end of a program sequence the CSIWE
falling edge transition must occur before the first address
transition, when changing from a PROGRAM to a READ
cycle. The program pin (Pin 18) should be pulled down
to VILP with an active device, because this pin sources a
small amount of current (IIPL) when CS/WE is at VIHW
(12 V) and the program pulse is at V I Lp.
EXAMPLES FOR PROGRAMMING
Always use the TPtotal = NxtpW;;;' 100 ms relationship.
1. All 8092 bits should be programmed with a 0.2 ms
program pulse width.
The minimum number of program loops:
N = TPtotal = 100 ms = 500. One program loop
tpw
0.2 ms
consists of words 0 to 1023.
2. Words 0 to 200 and 300 to 700 are to be pro·
grammed. All other bits are "don't care". The
program pulse width is 0.5 ms. The minimum
100
number of program loops, N = 0:5 = 200. One
program loop consists of words 0 to 1023. The
data entered into the "don't care" bits should be
all 1s.
3. Same requirements as example 2, but the EPROM is
now to be updated to include data for words 850
to 880. The minimum number of program loops is
the same as in the previous example, N = 200. One
program loop consists of words 0 to 1023. The data
entered into the "don't care" bits should be all 1s.
Addresses 0 to 200 and 300 to 700 must be reo
programmed with their original data pattern.
ERASING INSTRUCTIONS
The MCM68708/68A708 can be erased by exposure to
high intensity shortwave ultraviolet light, with a wave·
length of 2537 A.. The recommended integrated dose (i.e.,
UV·intensity x exposure time) is 12.5 Ws/cm 2 As an
example, using the "Model 30·000" UV·Eraser (Turner
Designs, Mountain View, CA 94043) the ERASE·time is
30 minutes. The lamps should be used without shortwave
filters and the MCM68708/68A708 shOUld be positioned
about one inch away from the UV·tubes.
2-142
®
MCM68732
MCM68L732
MOTOROLA
4096 x 8-BIT UV ERASABLE PROM
The MCM68732/68L732 is a 32,768-bit Erasable and Electrically
Reprogrammable PROM designed for system debug usage and similar
applications requiring nonvolatile memory that could be reprogrammed
periodically, or for replacing 32K ROMs for fast turnaround time. The
transparent window on the package allows the memory content to be
erased with ultraviolet light.
.
For ease of use, the device operates from a single power supply and
has a static power-down mode. Pin-for-pin compatible mask programmable ROMs are available for large volume production runs of systems
initially using the MCM68732/68L732.
MOS
IN-CHANNEL, SILICON-GATE)
4096x8-BIT
UV ERASABLE PROGRAMMABLE
READ ONLY MEMORY
• Single + 5 V Power Supply
• Automatic Power-down Mode (Standby) with Chip Enable
• Organized as 4096 Bytes of 8 Bits
• Low Power Dissipation
• Fully TTL Compatible
• Maximum Access Time = 450 ns MCM68732
350 ns MCM68732-35
• Standard 24-Pin DIP for EPROM Upgradability
• Pin Compatible to MCM68A332 Mask Programmable ROM
• AR Selects the Operational 32K Portion of the Die
MCM68732-1 AR = 1 = HIGH
MCM68732-0 AR = 0= LOW
• Pin Compatible With the MCM2532 32K EPROM in the Read Mode
• Low Power Version
MCM68L732 Active 60 mA Maximum
Standby 15 mA Maximum
MCM68L732-35 Active 100 mA Maximum
Standby 25 mA Maximum
.,
.....
..
MOTOROLA'S PIN-COMPATIBLE EPROM FAMILY
14K
UK
AI
L SUFFIX SIOEBRAZE CERAMIC PACKAGE
ALSO AVAILABLE - CASE 716
PIN ASSIGNMENT
A7
VCC
A6
AS
A5
A9
A4
AR
A3
E/vpp
A2
AID
Al
All
AD
OQ?
.1
DOD
006
oao
001
005
0Q2
004
VSS
OQ3
AI
MCM18714
MOTOROLA'S PIN·CQMPATlBLE ROM FAMILY
.,
14K
UK
AI
AI
.1
·Pin Names
AI
GO
A .... Address
AR .... Address Reference
00 .... Oata Input/Output
E/Vpp .... Chip Enable/Program
* New
industry standard nomenclature
INDUSTRY STANDARD PINOUTS
OS9814 Rl/1O-8O
2-143
II
MCM68732-MCM68l732
ABSOLUTE MAXIMUM RATINGS (1)
Rating
Temperature Under Bias
Value
Unit
-10 to +80
°c
o to
Operating Temperature Range
Storage Temperature
+ 70
°c
-65to +125
°c
All Input or Output Voltages with Respect to VSS
+6 to -0.3
Vdc
Vpp Supply Voltage with Respect to VSS
+28 to -0.3
Vdc
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric fields; however, it is advised that normal precau~
tions be taken to avoid application of any voltage
higher than maximum rated voltages to this highimpedance circuit,
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENOEO OPERATING CONOITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
MODE SELECTION
Pin Number
Mode
9-11,
13-17,
DQ
12
VSS
20
E/vpp
VCC
VCC
24
Data out
VSS
VIL
Output Disable
High Z
VSS
VIH
VCC
Standby
High Z
VSS
VCC
Program
Data in
VSS
VIH
usea
VILP to VIHP
Read
VCC
BLOCK DIAGRAM
VCC_
VSS _
Data Input/Output DOO-Dm
~
FIGURE 1 - AC TEST LOAD
EIVpp
~M{
AfrAl1 {
AR
.
5.0V
Test Point o--f--~-1~I---+
Y Gating
"100 pF
Memory
Matrix
MMD6150
or Equiv.
MMD7000
ar Equiv.
"Includes Jig Capacitance
CAPACITANCE 11.= 1.0 MHz, TA- 25°C, periodically sampled rather than 100% tested.!
Characteristic
Symbol
Typ
Max
Unit
Input Capacitance IVin=O VI Except EIVpp
Cin
4.0
6.0
pF
Input Capacitance EIVpp
Cin
60
100
pF
Cout
8.0
12
pF
Output Capacitance IV out = 0 VI
Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C=I.t1t/4V.
2-144
MCM68732-MCM68L732
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise not.ed)
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Symbol
Min
Nom
Ma.
VCC
4.75
4.5
5.0
5.0
5.25
5.5
V
Input High Voltage
VIH
2.0
-
VCC+ 1.0
V
Input Low Voltage
VIL
-0.1
-
0.8
V
MCM68L732/MCM68732
MCM68L732-35/MCM68732-35
Supply Voltage
Unit
RECOMMENDED DC OPERATING CHARACTERISTICS
Units
Min
"!.yp
Max
Vin=5.25 V
lin
-
-
10
-
-
10
~A
V ou t=5.25 V
ILO
-
-
10
-
10
~A
EIVpp=O.4
IEL
-
-
100
100
~A
EIVpp= 2.4
IEH=IPL
EIVpp=VIH
ICCl
-
-
400
25
25
120
160
0.45
-
-
-
EIVpp Input Sink Current
VCC Supply Current IActive) MCM68732-3510utputs Open)
EIVpp=VIL
ICC2
Output Low Voltage
IOL=2.1 mA
VOL
-
Output High Voltage
lOW -400~
VOH
2.4
VCC Supply Current IStandby) MCM68732
MCM68L732
Symbol
Address Input Sink Current
Output Leakage Current
MCM68732
Min Typ Ma.
Condition
Characteristic
VCC Supply Current IStandby) MCM68732-35
EIVpp=VIH
ICCl
VCC Supply Current IActive) MCM6873210utputs Open)
EIVpp- VIL
ICC2
-
-
-
2.4
400
~A
15
mA
25
60
mA
100
mA
mA
0.45
V
-
V
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted)
Input Pulse Levels ...
. .......... 0.8 Volt and 2.2 Volts
Input Rise and Fall Times
.................................... 20 ns
Input Timing Levels ................................... 1.0 Volt and 2 Volts
Output Timing Levels
Output Load ...
...... 0.8 Volt and 2 Volts
......................... See Figure 1
MCM68732-
Condition
Symbol
E=VIL
E to Output Valid
E to Hi-Z Output
Characteristic
Address Valid to Output Valid
Data Hold from Address
35
MCM68732
Max
Min
Max
tAVQV
-
350
450
ns
-
tELQV
-
350
-
450
ns
-
tEHQZ
0
100
0
100
ns
E - VIL
tAXDX
0
-
0
-
ns
READ MODE TIMING DIAGRAM
A IAddress)
Address Valid
E/Vpp
High Z
Q IOutput) - - - . . : . . - - - - (
High Z
2-145
Units
Min
•
•
MCM68732-MCM68L732
DC PROGRAMMING CONDITIONS AND CHARACTERISTICS
ITA= 25± 5'CI
RECOMMENDED PROGRAMMING OPERATING CONDITIONS
Parameter
Symbol
Min
Nom
Max
Unit
Supply Voltage
VCC
4.75
5.0
5.25
V
Input High Voltage for All Addresses and Data
VIH
2.2
-
V
Input Low Voltage for All Addresses and Data
VIL
-0.1
-
VCC + 1
0.8
Program Pulse Input High Voltage
VIHP
24
25
26
V
Program Pulse Input Low Voltage
VILP
2.0
VCC
6.0
V
Unit
V
PROGRAMMING OPERATION DC CHARACTERISTICS
Condition
Symbol
Min
Typ
Max
Vin = 5.25 V
III
-
Vpp Program Pulse Supply Current IVpp = 25 V ± 1 VI
-
IPH
Vpp Supply Current IVpp = 2.4 VI
-
IPL = IEH
-
-
10
30
400
160
Characteristic
Address Input Sink Current
V CC Supply Current IVpp = 5.0 VI
-
ICC
~A
mA
~A
mA
AC PROGRAMMING OPERATING CONDITIONS AND CHARACTERISTICS
Symbol
Min
Max
Unit
Address Setup Time
tAVPH
2.0
-
~
Data Setup Time
tDVPH
2.0
-
~
Chip Enable to Valid Data
tELQV
450
-
Chip Disable to Data In
tEHDV
2.0
-
Program Pulse Width
tPHPL
tPR
1.9
2.1
"s
ms
0.5
2.0
~s
Characteristic
Program Pulse Rise Time
Program Pulse Fall Time
ns
0.5
2.0
tPF
"s
Cumulative Programming Time Per Word·
tcp
12
50
ms
• Block mode programming must be used. Block mode programming is defined as one program pulse applied to each of the 4096 address locations in sequence. Multiple blocks are used to accumulate programming time (tcpl.
PROGRAMMING OPERATION TIMING DIAGRAM
A IAddressl
Dar Q IData)
E/vpp
2-146
MCM68732-MCM68L732
PROGRAMMING INSTRUCTIONS
READ OPERATION
After access time, data is valid at the outputs in the Read
mode. A single input (EIVpp) enables the,..9utputs and puts
the chip in active or standby mode. With EIVpp = "0" the
outputs are enabled and the chip is in active mode; with
EIVpp = "1" the outputs are three-stated and the chip is in
standby mode. During standby mode, the power dissipation
is reduced.
Multiple MCM68732s may share a common data bus with
like outputs OR-tied together. In this configuration the
EIVpp input should be high on all unselected MCM68732s to
prevent data contention.
After the completion of an ERASE operation, every bit in
the device is in the "1" state (represented by Output High).
Data are entered by programming zeros (Output Low) into
the required bits. The words are addressed the same way as
in the READ operation. A programmed "0" can only be
changed to a "1" by ultraviolet light erasure.
To set the memory up for Program Mode, the EIVpp input
(Pin 20) should be between + 2.0 and + 6.0 V, which will
three-state the outputs and allow data to be setup on the DQ
terminals. The V CC voltage is the same as for the Read
operation. Only "D's" will be programmed when "D's" and
"1's" are entered in the 8-bit data word.
After address and data setup, 25-volt programming pulse
(VIH to VIHP) is applied to the EIVpp input. A program
pulse is applied to each address location to be programmed.
The maximum program pulse width is 2 ms and the maximum program pulse amplitude is 26 V.
Multiple MCM68732s may be programmed in parallel by
connecting like inputs and applying the program pulse to the
EIVpp inputs. Different data may be programmed into multiple MCM68732s connected in parallel by selectively applying
the programming pulse only to the MCM68732s to be programmed.
ERASING INSTRUCTIONS
The MCM68732 can be erased by exposure to high intensity shortwave ultraviolet light, with a wavelength of 2537
angstroms. The recommended integrated dose (i.e., UVintensity X exposure time) is 15 Ws/cm 2 As an example, using the "Model 30-000" UV-Eraser (Turner Designs, Mountain View, CA 94043) the ERASE-time is 36 minutes. The
lamps should be used without shortwave filters and the
MCM68732 should be positioned about one inch away from
the UV-tubes.
TIMING LIMITS
The table of timing values shows either a minimum or a
maximum limit for each parameter. Input requirements are
specified from the external system point of view. Thus, address setup time is shown as a minimum since the system
must supply at least that much time (even though most
devices do not require it). On the other hand, responses from
the memory are specified from the device point of view.
Thus, the access time is shown as a maximum since the
device never provides data later than that time.
TIMING PARAMETER ABBREVIATIONS
II
t X X X X
Signal name from which interval is defined ----.J
transition direction for first signal
signal name to which interval is defined
transition direction for second signal
I
The transition definitions used in this data sheet are:
H = transition to high
L = transition to low
V = transition to valid
X = transition to invalid or don't care
Z = transition to off (high impedance)
WAVEFORMS
Input
Output
Must Be
Valid
Will Be
Valid
~
. Change
From H to L
Will Change
From H to L
~
Change
From L to H
Will Change
From L to H
:m:f.lN
Don't Care:
Any Change
Changing:
State
Permitted
Unknown
Waveform
Symbol
==>-
High
Impedance
2-147
@
MCM68764
MCM68L764
MOTOROLA
MOS
8192 x 8-BIT UV ERASABLE PROM
•
IN-CHANNEL, SILICON-GATEI
8192x8-BIT
The MCM68764/68L764 is a 65,536-bit Erasable and Electrically
Reprogrammable PROM designed for system debug usage and similar
applications requiring nonvolatile memory that could be reprogrammed
periodically, or for replacing 64K ROMs for fast turnaround time. The
transparent window on the package allows the memory content to be
erased with ultraviolet light.
For ease of use, the device operates from a single power supply and
has a static power-down mode. Pin- for-pin mask programmable ROMs
are available for large volume production runs of systems initially using
the MCM68764/68L764.
Single + 5 V Power Supply
Automatic Power-down Mode IStandbyl with Chip Enable
Organized as 8192 Bytes of 8 Bits
Low Power Dissipation
Fully TTL Compatible
Maxirnum Access Time = 450 ns MCM68764
350 ns MCM68764-35
• Standard 24-Pin DIP for EPROM Upgradability
• Pin Compatible to MCM68A364 Mask Programmable ROM
• Low Power Version
MCM68L764 Active 60 mA Maximum
Standby 15 mA Maximum
MCM68L764-35 Active 100 mA Maximum
Standby 25 mA Maximum
•
•
•
•
•
•
C SUFFIX
FRIT-SEAL CERAMIC PACKAGE
CASE 623A-02
L SUFFIX CERAMIC PACKAGE
ALSO AVAILABLE - CASE 716-07
PIN ASSIGNMENT
MOTOROLA'S PIN·COMPATIBLE EPROM FAMILY
32K
UV ERASABLE
PROGRAMMABLE READ
ONLY MEMORY
18K
A7
Vee
A6
AS
A5
A9
A4
A12
A3
E/vpp
AlO
All
AO
DOl
001
005
006
MCM8I784
004
MOTOROLA'S PIN·COMPATIBLE ROM FAMILY
14K
32K
Vss
13
003
*Pin Names
'''"",__=MCM88A384
A. .. Address
DO .
. Data Input/Output
E/vpp .... ~/Program
INDUSTRY STANDARD PINOUTS
"New industry standard nomenclature
DS9815 Rl/9-80
2-148
MCM68764-MCM68L764
ABSOLUTE MAXIMUM RATINGS ISee Notel
Rating
Temperature Under Bias
Value
Unit
-10to +80
°e
o to
Operating Temperature Range
Storage Temperature
+ 70
This device contains circuitry to protect the inputs
against damage due to high static voltages or elec~
trie fields; however, it is advised that normal precautions be taken to avoid application of any voltage
higher than maximum rated voltages to this highimpedance circuit.
°e
-65 to +125
°e
All Input or Output Voltages with Respect to VSS
+6 to -0.3
Vdc
Vpp Supply Voltage with Respect to VSS
+2B to -0.3
Vdc
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
•
MODE SELECTION
Pin Number
9-11,
13--17,
DO
Mode
12
20
24
VSS
EIVpp
Vee
Read
Data out
VSS
VIL
Vee
Output Disable
High-Z
VSS
VIH
Vee
Standby
High-Z
VSS
Vee
Program
Data in
VSS
VIH
Pulsed
VILP to VIHP
Vee _
VSS_
Vee
BLOCK DIAGRAM
Data Input/Output
000-007
/~
FIGURE 1 -
AC TEST LOAD
EIVpp
5.0 V
....t--;
Test Point O--r-~-
Y Gating
·100 pF
Memory
Matrix
• Includes Jig Capacitance
2-149
MMD6150
or Equiv.
MMD7000
or Equiv.
•
MCM68764e MCM68l764
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise notedl
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Min
Nom
Max
Unit
VCC
4.75
4.5
5.0
5.0
5.25
5.5
Vdc
Input High Voltage
VIH
2.0
-
Input Low Voltage
VIL
-0.1
-
VCC + 1.0
- 0.8
Parameter
MCM68L764/MCM68764
MCM68764-35/MCM68L764-35
Supply Voltage
Vd:,,--Vdc
RECOMMENDED DC OPERATING CHARACTERISTICS
Condition
Characteristic
- - --
Symbol
MCM68764
Min Typ Max
ILO
-
ElVpp Input Sink Current
Vin=5.25 V
Vout -5.25 V
ElVpp=O.4
IEL
-
ElVpp = 2.4
IEH= IpL
VCC Supply Current (Standbyl MCM68764
ElVpp-VIH
ICCl
-
VCC Supply Current (Standbyl MCM68764-35
ElVpp-VIH
ICCl
VCC Supply Current (Activel MCM68764 (Outputs Open I
ElVpp=VIL
ICC2
-
VCC Supply Current (Activel MCM68764-35 (Outputs Open I
Output Low Voltage
ElVpp=VIL
IOL-2.1 mA
ICC2
VOL
-
Output High Voltage
IOH=-400~
VOH
2.4
Address Input Sink Current
Output Leakage Current
lin
-
-
MCM68L764
Units
Min Typ Max
10
-
-
10
~A
10
-
-
100
-
-
10
100
~A-
400
25
25
120
160
0.45
-
-
-
-
-
-
2.4
-
CAPACITANCE (1=1 0 MHz TA=25°C periodically sampled rather than 100% tested I
Characteristic
Input Capacitance IVin - 0 VI Except ElVpp
Input Capacitance ElVpp
Output Capacitance IV out = 0 VI
Typ
Max
Cin
4.0
60
8.0
6.0
100
12
Cin
Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C =
~
tN
READ MODE TIMING DIAGRAM
Address Valid
A IAddressl
ElVpp
tEHQZ
tAVQVltELQV
High-Z
Q (Outputl-----=------{ X:)<~)<~)c(~
2-150
High-Z
Data Valid
400 , ~A
15
mA
mA
25
mA
60
100
mA
0.45
V
V
-
Symbol
Cout
~A
Unit
pF
pF
pF
MCM68764-MCM68L764
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted)
Input Pulse Levels .......................... 0.8 Volt and 2.2 Volts
Input Rise and Fall Times..
.. ........................ 20ns
Input Timing Levels ............................... 1.0 and 2 Volts
Output Timing Levels ......................... 0.8 Volt and 2 Volts
Output Load ........................................... See Figure 1
MCM68764-
Characteristic
Condition
Address Valid to Output Valid
MCM6B764
Units
Min
Max
Min
Max
tAVOV
-
450
450
ns
ns
-
tEHOZ
ns
tAX OX
a
a
100
E - VIL
350
350
100
-
-
tELOV
-
ns
E = VIL
-
E to Output Valid
E to Hi-Z Output
Data Hold from Address
36
Symbol
-
a
a
DC PROGRAMMING CONDITIONS AND CHARACTERISTICS
(TA=25± 5°C)
RECOMMENDED PROGRAMMING OPERATING CONDITIONS
Parameter
Symbol
Min
Nom
Max
Unit
Supply Voltage
VCC
4.75
5.0
5.25
V
Input High Voltage for All Addresses and Data
VIH
-
VIL
-
VCC + 1
0.8
V
Input Low Voltage for All Addresses and Data
2.2
-0.1
Program Pulse Input High Voltage
VIHP
24
25
26
V
V
Program Pulse Input Low Voltage
VILP
2.0
VCC
6.0
V
PROGRAMMING OPERATION DC CHARACTERISTICS
Characteristic
Address Input Sink Current
Vpp Program Pulse Supply Current (Vpp = 25 V
± 1 V)
Vpp Supply Current (Vpp - 2.4 V)
Condition
Symbol
Min
Typ
Mex
Unit
Yin = 5.25 V
III
IPH
-
10
-
-
30
I'A
mA
400
160
I'A
mA
VCC Supply Current (Vpp - 5.0 V)
IPL - IEH
ICC
AC PROGRAMMING OPERATING CONDITIONS AND CHARACTERISTICS
Charactarlstlc
Unit
Symbol
Min
Mex
Address Satup Time
tAVPH
2.0
Data Setup Time
tDVPH
2.0
Chip Enable to Valid Data
tELOV
450
Chip Disable to Data In
tEHDV
tpHPL
tpR
2.0
-
1.9
2.1
"s
ms
0.5
2.0
"s
tpF
0.5
2.0
Program Pulse Width
Program Pulse Rise Time
Program Pulse Fall Time
Cumulative Programming Time Per Word-
~s
~s
ns
"s
12
50
ms
• Block mode programming must be used. Block mode programming IS defined as one program pulse applied to each of the 8,192 address locations in sequence. Multiple blocks are used to accumulate programming time ItCp).
t~p
2-151
•
MCM68764-MCM68L764
PROGRAMMING OPERATION TIMING DIAGRAM
Address 0
A (Address)
o or Q IData).
Data Out
E/vpp
tELQV
READ OPERATION
PROGRAMMING INSTRUCTIONS
After access time, data is valid at the outputs in the Read
mode. A single input (ElVpp) enables the Q!!tputs and puts
the chip in active or standby mode. With ElVpp= "0" the
outputs are enabled and the chip is in active mode; with
ElVpp= "'" the outputs are three-stated and the chip is in
standby mode. During standby mode, the power dissipation
is reduced.
Multiple MCM68764s may share a common data bus with
like outputs OR-tied together. In this configuration, only one
ElVpp input should be low and no other device outputs
should be active on the same bus. This will prevent data contention on the bus.
After the completion of an ERASE operation, every bit in
the device is in the "'" state (represented by Output High).
Data are entered by programming zeros (Output Low) into
the required bits. The words are addressed the same way as
in the READ operation. A programmed "0" can only be
changed to a "'" by ultraviolet light erasure.
To set the memory up for Program Mode, the ElVpp input
(Pin 20) should be between +2.0 and +6.0 V, which will
three-state the outputs and allow data to be setup on the DO
terminals. The V CC voltage is the same as for the Read
operation. Only "0'5" will be programmed when "O's" and
""s" are entered in the B-bit data word.
After address and data setup, 25-volt programming pulse
(VIH to VIHP) is applied to the ElVpp input. The program
pulse width is 2 ms and the maximum program pulse
amplitude is 26 V.
Multiple MCM68764s may be programmed in parallel by
connecting like inputs and applying the program pulse to the
ElVpp inputs. Different data may be programmed into multiple M CM68764s connected in parallel by selectively applying
the programming pulse only to the M CM68764s to be programmed.
ERASING INSTRUCTIONS
The M CM68764 can be erased by exposure to high intensity shortwave ultraviolet light, with a wavelength of 2537
angstroms. The recommended integrated dose (i.e., UVintensity X exposure time) is 15 Ws/cm2 . As an example, using the "Model 30-000" UV-Eraser (Turner Designs, Mountain View, CA 94043) the ERASE-time is 36 minutes. The
lamps should be used without shortwave filters and the
M CM68764 should be positioned about one inch away from
the UV-tubes.
2-152
®
MOTOROLA
MCM68766
Advance InforIDation
MOS
tN-CHANNEL, SILICON-GATEI
8192x8-BIT UV ERASABLE PROM
The MC68766 is a 65,536-bit Erasable and Electrically Reprogrammabie PROM designed for system debug usage and similar applications
requiring nonvolatile memory that could be reprogrammed periodically,
or for replacing 64K ROMs for fast turnaround time. The transparent
window on the package allows the memory content to be erased with
ultraviolet light.
For ease of use, the device operates from a single power supply that
has an output enable control and is pin-for-pin compatible with the
MCM68366 mask programmable ROMs, which are available for large
vol~me production runs of systems initially using the MCM68766.
8192x8-BIT
UV ERASABLE
PROGRAMMABLE READ ONLY
MEMORY
• Single + 5 V Power Supply
• Organized as 8192 Bytes of 8 Bits
• Fully TTL Compatible
• Maximum Access Time=450 ns MCM68766
350 ns MCM68766-35
•
FRIT -SEAL CERAMIC PACKAGE
CASE 623A-02
L SUFFIX CERAMIC PACKAGE
ALSO AVAILABLE - CASE 716-07
Standard 24-Pin DIP for EPROM Upgradability
• Pin Compatible to MCM68366 Mask Programmable ROM
• Power Dissipation -
160 mA Maximum
PIN ASSIGNMENT
VCC
MOTOROLA'S PIN-COMPATIBLE EPROM FAMILY
12K
A6
12K
AS
A9
A12
G/Vpp
AlO
,,MCM88788
MCM88732
"
DQ5
13
D03
All
AO
DOl
DOl
005
Vss
003
MCM2532
006
004
MOTOROLA'S PIN·COMPATIBLE ROM FAMILY
12K
18K
15
"
t
QI
...
Q,
MCM88A318E
*Pin Names
A..
...Address
DO..
...Data Input/Output
G/Vpp ....... Output Enable/ Program
• New industry standard nomenclature
INDUSTRY STANDARD PINOUTS
ADI843/9-80
2-153
•
MCM68766
ABSOLUTE MAXIMUM RATINGS
Rating
Temperature Under Bias
Operating Temperature Range
Storage Temperature
Value
10 to +80
to + 70
66 to + 125
+6 to 0.3
+26 to -0.3
o
All Input or Output Voltages with Respect to VSS
Vpp Supply Voltage with Respect to VSS
Unit
De
De
De
Vdc
Vdc
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage
higher"than maximum rated voltages to this highimpedance circuit.
NOTE: Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to REeOMMENDED OPERATINGeONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
MODE SELECTION
Pin Number
9-11,
13-17,
Da
Data Out
High-Z
Mode
Read
Output Disable
Data In
Program
Vee
VSS
-+-+-
12
VSS
20
~/VPP
24
Vec
VSS
VSS
VIL
VIH
Pulsed
VILP to VIHP
Vce
Vce
VSS
BLOCK DIAGRAM
Data Input/Output DaO-Da7
~
FIGURE 1 - AC TEST LOAD
~lVpp
5.0 V
Test Point o--..--_~t.-I--+
Y Gating
·l00pF
Memory
Matrix
·Includes Jig Capacitance
2-154
MMD6150
or Equiv.
MMD7000
or Equiv.
Vee
MCM68766
CAPACITANCE (f-1
-
a MHz
TA - 25'C VCC - 5 V periodically sampled rather than 100% tested)
Characteristic
Input Capacitance (Vin = a V) Except GNpp
Input Capacitance (GNpp)
Output Capacitance (V out = a V)
Symbol
Typ
Cin
Cin
Cout
4.0
Max
6.0
100
12
60
8.0
Unit
pF
pF
pF
Capacitance measured with a Boonton Meter or effective capacitance calculated from thel equation: C= Illt/IlV.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted)
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Parameter
MCM68766
MCM68766-35
Supply Voltage
VCC
Input High Voltage
Input Low Voltage
VIH
VIL
Min
Nom
5.0
5.0
Max
5.25
5.5
Unit
4.75
4.5
2.0
-0.1
-
VCC+1.0
0.8
Vdc
Vdc
Vdc
DC OPERATING CHARACTERISTICS
Conditton
Symbol
Min
Typ
Vin=5.25 V
Vout - 5.25 V
ITNpp~O.4 V
lin
-
-
-
-
2.4
-
Characteristic
Address Input Sink Current
Output Leakage Current
ILO
IC;I
GNpp=2.4 V IGH-lpL
ITNpp Input Sink Current
VCC Supply Current (Outputs Open)
Output Low Voltage
Output High Voltage
GNpp=VIL
IOL-2.1 mA
IOH- -400 "A
ICC
VOL
VOH
-
Max Units
10
p.A
10
p.A
100
~A
400
p.A
160
mA
V
0.45
V
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted)
Input Timing Levels ..
Output Timing Levels ..
Output Load ..
Input Pulse Levels ................................... 0.8 Volt and 2.2 Volts
Input Rise and Fall Times....... .. .............. ...... .......
.. ... 20 ns
.. .... 1.0 Volt and 2 Volts
. .... 0.8 Volt and 2 Volts
.. ............ See Figure 1
MCM68766-
Condition
Characteristic
Address Valid to Output Valid
G=VIL
-
G to Output Valid
-
G to Hi-Z Output
Data Hold from Address
G=VIL
READ MODE TIMING DIAGRAM
A (Address)
-
>f
Address Valid
Symbol
35
Max
Min
Max
tAVQV
-
350
tGLQV
-
150
100
-
450
150
100
-
tGHQZ
tAXDX
a
a
-
GNpp
tGHQZ
High-Z
High-Z
----------<
Data Valid
2-155
a
a
X,'-----
- t A V Q V- - - - - - "
Q (Output)
MCM68766
Min
Units
ns
ns
ns
ns
•
MCM68766
DC PROGRAMMING CONDITIONS AND CHARACTERISTICS
ITA=25± 5°C}
RECOMMENDED PROGRAMMING OPERATING CONDITIONS
Parameter
Symbol
Min
Nom
Max
Unit
Supply Voltage
Vce
4.75
5.0
5.25
Vdc
Input High Voltage for All Addresses and Data
~- ~
VCC + 1
O.B
Vdc
VIL
-0.1
-
Program Pulse Input High Voltage
VIHP
24
25
26
Vdc
Program Pulse Input Low Voltage
VILP
2.0
VCC
6.0
Vdc
Condition
Symbol
Min
Typ
Max
Unit
Yin = 5.25 V
III
-
-
10
"Adc
mAdc
-
-
400
Input Low Voltage for All Addresses and Data
Vdc
PROGRAMMING OPERATION DC CHARACTERISTICS
Characteristic
Address Input Sink Current
Vpp Program Pulse Supply Current IVpp - 25 V ± 1 V}
-
IpH
Vpp Supply Current IVpp - 2.4 V}
-
IpL - IGH
VCC Supply Current IVpp - 5 V}
-
ICC
30
"A
mAdc
160
AC PROGRAMMING OPERATING CONDITIONS AND CHARACTERISTICS
Symbol
Min
Max
Address Setup Time
tAVPH
2.0
Data Setup Time
tDVPH
2.0
-
Dutput Enable to Valid Data
tGLOV
150
-
ns
Dutput Disable to Data In
tGHDV
2.0
-
Program Pulse Width
Charactaristic
Unit
"s
p's
tpHPL
1.9
2.1
"s
ms
Program Pulse Rise Time
tPR
0.5
2.0
"s
Program Pulse Fall Time
tpF
0.5
2.0
"s
12
ms
tcp
50
Cumulative Pro~ramming Time Per Word'
,
Block mode programming must be used. Block mode programming IS defined as one program pulse applied to each of the B, 192 address locations in sequence. Multiple blocks are used to accumulate programming time Itcpl.
PROGRAMMING OPERATION TIMING DIAGRAM
A IAddress}
Dar 0 lData}
Address 1 ... B, 191
Address 0
Address 0
Data Out
Data In
Data In
tpHPL
G/Vpp
tPF
tDVPH
2-156
tGLOV
MCM68766
PROGRAMMING INSTRUCTIONS
READ OPERATION
After the completion of an ERASE operation, every bit in
the device is in the "1" state (represented by Output High).
Data are entered by programming zeros (Output Lowl into
the required bits. The words are addressed the same way as
in the READ operation. A programmed "0" can only be
changed to a "1" by ultraviolet light erasure.
_
To set the memory up for Program Mode, the GlVpp input (Pin 20) should be between + 2.0 and + 6.0 V, which will
three-state the outputs and allow data to be set up on the
DQ terminals. The V CC voltage is the same as for the Read
operation. Only "O's" will be programmed when "O's" and
"1's" are entered in the 8-bit data word.
After address and data setup, 25-volt programming pulse
(VIH to VIHP) is applied to the GlVpp input. The program
pulse width is 2 ms and the maximum program pulse
amplitude is 26 V.
Multiple MCM68766s may be programmed in parallel by
connecting like inputs and applying the program pulse to the
GlVpp inputs. Different data may be programmed into
multiple MCM68766s connected in parallel by selectively applying the programming pulse only to the MCM68766s to be
programmed.
After access time, data is valid at the outputs in the Read
mode. With GlVpp = "0" the outputs are enabled; with
GlVpp = "1" the outputs are three-stated.
Multiple MCM68766s may share a common data bus with
like outputs OR-tied together. In this configuration only one
GlVpp input should be low and no other device outputs
should be active on the same bus. This will prevent data contention on the bus.
ERASING INSRUCTIONS
The MCM68766 can be erased by exposure to high intensity shortwave ultraviolet light, with a wavelength of 2537
angstroms. The recommended integrated dose (Le., UVintensity X exposure time) is 15 Ws/cm 2 . As an example, using the "Model 3Q-OOO" UV Eraser (Turner Designs, Mountain View, CA 94043) the ERASE-time is 36 minutes. The
lamps should be used without shortwave filters and the
MCM68766 should be positioned about one inch away from
the UV-tubes.
2-157
•
®
MOTOROLA
MCM2801
Advance Infor:rnation
MOS
16 x 16-BIT SERIAL ELECTRICALLY ERASABLE PROM
The MCM2801 is a 256-bit serial Electrically Erasable PROM designed
for handling small amounts of data in applications requiring both nonvolatile memory and in-system information updates.
The MCM2801 saves time and money because of the in-system erase
and reprogram capability. It has external control of timing functions and
serial format for data and address. The MCM2801 is fabricated in
floating gate technology for high reliability and producibility.
IN-CHANNEL, SILICON GATE)
16x 16 BIT
ELECTRICALLY ERASABLE
PROGRAMMABLE READ
ONLY MEMORY
• Single + 5 V Power Supply
• Organized as 16 Words of 16 Bits
• Fully TTL Compatible
• Single + 25 V Power Supply for Erase and Program
"
• In-System Program/ Erase Capability
-
CERDIP PACKAGE
CASE 632-00
1
PLASTIC PACKAGE ALSO AVAILABLE CASE 646-05
BLOCK DIAGRAM
PIN ASSIGNMENT
V PP
[i"i\J"i4 PVCC
'T2
13pCTAl
N/C
12 PCTA2
'BE
4
'n
11 pCTA3
10
S
pPVC
9PC
VSS
8 PADO
'"For normal operation, these inputs should
be hardwired to VSS.
ADO
PIN NAMES
........Multiplexed Address/
Data-ln/Data-Out
C..
. ............................. Clock
. .......... Program Voltage Control
PVC..
.. .... Control
CTA1, 2, 3.
BE..
. ................. Block Erase
S
.................... Chip Select
Tl, T2.. .
.. .. Test Pins
FIGURE 1 - Vpp CONTROL
Vpp
- - - I J -___
r----~VpP
VCC
10 k
This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this highimpedance circuit.
Vss
~-~\/VV--"
PVC
47kO
ADIB41/8-80
2-158
MCM2801
MODE SELECTION
Pin Number
Mode
Write
1
Vpp
VSS or Vee
Vpp
Vpp
Serial Data Out
Serial Address In
Serial Data In
Read
Standby
Vss
VSS
VSS
VSS
VSS
Standby
Word Erase
or
or
or
or
or
Vee
Vee
Vee
Vee
Vee
6
7
S
VSS
Vss
VSS
VSS
Vss
Vss
Vss
Vss
Vss
VIH
VIL
VIL
VIL
VIL
VIL
VIL
VIH
11
eTR3
VIH
VIH
VIL
VIH
VIL
VIH
VIL
VIL
12
eTR2
VIH
VIL
VIH
VIH
VIL
VIL
VIH
VIL
13
eTRl
VIH
VIL
VIL
VIL
VIH
VIH
VIH
VIL
14
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
ABSOLUTE MAXIMUM RATINGS (1f
Rating
Temperature Under Bias
Operating Temperature Range
Storage Temperature
All Input or Output Voltages with Respect to VSS
Vpp Supply Voltage with Respect to VSS
Value
-40 to +85
to + 70
-55to +150
+8 to -0.5
+30 to -0.5
o
Unit
ac
ac
ac
Vdc
Vdc
NOTE 1: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should
be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONSIFull operating voltage and temperature range unless otherwise noted.1
Parameter
Symbol
Min
Nom
Max
5.0
5.5
4.5
Vee
Supply Voltage
25.0
Vpp
24.0
26.0
Input High Voltage
4.0
Vee+ 1.0
VIH
Input Low Voltage
0.1
0.8
VIL
OPERATING DC CHARACTERISTICS
Characteristic
Input Sink Current
Vee Supply Current
Vpp Supply Current
Output Low Voltage
Output High Voltage
Condition
Symbol
Ot
Read
I
~I
1 tCtrVCH
>¢
~,r:_____
Serial Data Out 116 Clocks)
~
tCHOV
0---
-
Data Bit 1
-Hi-Z- -
....J
Data Bit 2
Data Bit 16
"'"
~
Ol
~
SERIAL DATA IN
C
ICtrVCH
CTR1, CTR2,
CTR3
Serial Data In (16 Clocks)
I"
o
~I tOVCl
Data Bit 1
Data Bit 16
11.
j4-tCHOZ
•
MCM2801
ERASE-WRITE SEQUENCE
i+-----tERASE - - - - - - t l....- - - - - tWRITE --------i~
C
CTR1, CTR2,
CTR3
NOTE: One clock pulse is sufficient to load a new op code.
FUNCTIONAL DESCRIPTION
The memory stores sixteen words each of sixteen bits. All
functions are controlled by a 3-bit parallel instruction bus and
an applied clock.
Data Protection
When Vpp is turned off, data stored in the array is always
protected. A Vpp control output is provided for switching
the Vpp supply. It consists of a pull-down device to VSS.
This device is turned on· only when: VCC is present and a
WRITE or WORD ERASE code has been loaded with a clock
pulse.
A schematic for this external Vpp control is proposed in
Figure 1.
When this feature is not used for data protection, Vpp
must not be present if VCC is not supplied. The TEST1,
TEST2, and BLOCK ERASE pins are provided for testing
purpose only and should be h·ard-wired to VSS in any application.
Read-Out
1) The 13-bit parallel) serial address instruction code is
presented while the 4-bit serial address is shifted in on
the 110 bus through the ADO pin.
2) The READ instruction is presented for one clock time.
This reads the word from the new address in the
memory array and parallel loads it into the shift register.
3) The SERIAL DATA-OUT instruction is presented for
16-clock pulses, causing the data to be shifted out on
the lID bus through the ADO pin. During the serial
data-out instruction, data is recirculated to allow further
readout of the original data without access to the
memory array.
Power Up/Power Down Sequence
Using an external Vpp control as given in Figure 1, Vpp
and V CC may be turned on or off in any sequence, without
disturbing data in the non-volatile memory array, providing
that neither a WORD ERASE nor a WRITE is present on the
control inputs, or that S=low, or that C=high.
Writing
1) The address is changed, if necessary, in the same manner as in the readout.
2) Data is serially loaded o.nto the chip by presenting the
SERIAL DATA-IN instruction for 16-clock pulses.
3) The WORD ERASE instruction is presented for the
specified Erase Time. This erases only the addressed
word.
4) The WRITE instruction is presented for the specified
Write Time. This transfers the data to the selected address in the MCM2801.
Instruction Sequences
The clock signal has no effect during WRITE or ERASE.
READ should be presented for one clock cycle only since
frequent unnecessary use may disturb data.
WRITE If or any address) must be preceded by the WORD
ERASE instruction at the same address.
All instructions except SERIAL DATA-OUT cause the data
output driver to be high impedance.
Vpp is necessary for WRITE, WORD ERASE and in conjunction with the BLOCK ERASE pin. In all other cases, it
can be switched to high impedance, VCC or VSS.
BLOCK ERASE can be used for testing purposes. For
clearing the whole array, Vpp should be applied and BE pin
kept at Vce for the normal erase time.
When the chip is deselected IS = 1), the output buffer is in
the OFF state.
The TEST1 and TEST2 pins are for manufacturing use only and are not available to the user.
Standby
The STANDBY INSTRUCTION when strobed in by the
clock puts the memory in a quiescent state where the output
is in the high-impedance state, and the clock presence or
absence will not affect the chip.
Clock
The active high clock signal is used for loading instruction
codes, for introducing serial addresses and data, and for
shifting serial data out. The clock has no influence on any
other function.
2-162
®
MOTOROLA
MCM2816
Product Previe"""
MOS
IN-CHANNEL, SILICON GATEI
2048 x 8-BIT ELECTRICALLY ERASABLE PROM
The MCM2816 is a 16,384-bit Electrically Erasable Programmable
Read Only Memory designed for handling data in applications requiring
both nonvolatile memory arid in-system reprogramming. The industry
standard pinout in a 24-pin dual-in-line package makes the MCM2816
EEPROM compatible with the popular MCM2716 EPROM.
The MCM2816 saves time and money because of the in-system erase
and reprogram capability. While Vpp is at 25 V and Gis at VIL, a 100 ms
active high TTL erase pulse applied to the E/Progr pin allows the entire
memory to be erased to the" 1" state. In addition to in-system programmability, this new-generation PROM is programmable on the standard
EPROM programmer.
For ease of use, the device operates in the read mode from a single
power supply and has a static power-down mode. The MCM2816 is
fabricated in floating gate technology for high reliability and producibility.
•
•
•
•
•
Single + 5 V Power Supply
Automatic Power-Down Mode (Standby)
Single + 25 V Power Supply for Erase and Program
Organized as 2048 Bytes of 8 Bits
TTL Compatible During Read and Program (No High Voltage Pulses)
• Maximum Access Time=450 ns MCM2816
350 ns MCM2816-35
A7
~
A6
2
23
AS
3
22 A9
A4
4
A3
5
"
A2
6
19
AIO
A7~
18
t/Progr
A6
,
Vee
A8
PIN ASSIGNMENT
A7
A8
A4
Vpp
A3
G
A2
AlO
A1
E/Progr
AO
DOl
DOO
D06
DOl
D05
D02
D04
VSS
D03
Vpp
G
2
:.13
Vee
·Pin Names
A8
A....
.. ........................... Address
DO..
.. ............ Doto Input/Output
E/ Progr ...... Chip Enable/ Program-Erase
G .................. .. ........ Output Enable
AO
d
17
DOl
AS
3
22 A9
000
9
16
DO'
A4
Vpp
10
15
005
A3
,
21
001
20
G
002
11
14
004
A2
6
19
Al0
VSS
12
13
003
AI
1
18
EIProgr
AO
d
17
DOl
000
9
16
006
001
10
15
DOS
002
11
14PDQ4
VSS
12
MCM2816
L SUFFIX CERAMIC PACKAGE
ALSO AVAILABLE - CASE 716-07
A5
PINOUT
COMPARISON
2816 AND 2716
AI
C SUFFIX
FRIT-SEAL CERAMIC
PACKAGE
CASE 623-04
A6
• Pin Compatible to MCM68316E and MCM2716
• In-System Programl Erase Capability
20
2048x8-BIT
ELECTRICALLY ERASABLE
PROGRAMMABLE READ
ONLY MEMORY
4
13 pOO3
MCM2716
-New industry standard nomenclature
Motorola reserves the right to make changes to
any product herein to improve reliability, function or design. Motorola does not assume any
liability arising out of the application or use of
any product or circuit described herein; neither
does it convey any license under its patent rights
nor the rights of others.
NP332/1l-BO
2-163
•
®
MCM6670
MCM6674
MOTOROLA
MOS
128c X 7 X 5 CHARACTER GENERATOR
IN-CHANNEL, SILICON GATE}
The MCM6670 is a mask-programmable horizontal-scan (row
select) character generator containing 128 characters in a 5 X 7
matrix. A 7-bit address code is used to select one of the 128 available
characters, and a 3-bit row select code chooses the appropriate row
to appear at the outputs. The rows are sequentially displayed,
providing a 7-word sequence of 5 parallel bits per word for each
character selected by the address inputs.
The MCM6674 is a preprogrammed version. of the MCM6670.
The complete pattern of this device is contained in this data sheet.
•
Fully Static Operation
•
•
TTL Compatibility
Single ±1O% +5 Volt Power Supply
•
•
18-Pi n Package
Diagonal Corner Power Supply Pins
•
Fast Access Time, 350 ns (max)
ABSOLUTE MAXIMUM RATINGS IS •• Note
128cx7x5
HORIZONTAL-SCAN
CHARACTER GENERATOR
L SUFFIX
CERAMIC PACKAGE
CASE68(l.()6
1)
Symbol
Value
Unit
Vee
-0.3 to +7.0
I nput Voltage
Vin
-0.3 to +7.0
Operating Temperature Range
TA
o to +70
T stg
-65 to +150
Vdc
Vdc
°e
°c
Rating
Supply Voltage
Storage Temperature Range
NOTE1: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
P SUFFIX
PLASTIC PACKAGE
eASE 70HJ2
PIN ASSIGNMENT
A6![ii\-1i8
A4
16
04
15
03
4
BLOCK DIAGRAM
AO
A1
A2
A3
A4
A5
A6
7
6
5
4
3
2
1
13 D1
Memory
Matrix
Row
14 D2
Decode
15 03
A2 5
14 02
A1
13 01
6
12
00
RS3 8
AD
11
RS1
GNO 9
10
RS2
16 04
11
10
8
This device contains circuitry to protect the
inputs against damage due to high static volt~
ages or electric fields; however, it is advised that
normal precautions be taken to avoid applica~
AS1 RS2 RS3
Vee"'" Pin 18
Gnd
cs
1'7
A3
12 DO
Vee
A5
= Pin
9
17
CS
tion of any voltage higher than maximum rated
voltages to this ~igh impedance circuit.
OS9459/12-77
2-164
MCM6670-MCM6674
DC OPERATING CONDITIONS AND CHARACTERISITCS
(Full operating voltage and temperature range unless otherwise noted.)
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Symbol
Min
Nom
Max
Unit
Supply Voltage
VCC
4.5
5.0
5.5
Vde
Input High Voltage
VIH
2.0
5.5
Vde
Input Low Voltage
VIL
-0.3
-
0.8
Vde
Symbol
Min
Typ
Max
Unit
'in
-
-
2.5
!lAde
Output High Voltage
(lOH = -205I'A)
VOH
2.4
-
VCC
Vde
Output Low Voltage
VOL
-
-
0.4
Vde
Output Leakage C~ent (Three-Statel
(CS = 2.0 V or CS = 0.8 V. V out = 0.4 V to 2.4 V)
ILO
-
-
10
,uAdc
Supply Current
(VCC = 5.5 V. TA= DoC)
ICC
-
-
130
mAde
DC CHARACTERISTICS
Characteristic
Input Current
(Vin
= 0 to
5.5 VI
(lOL = 1.6 mAl
CAPACITANCE (T A = 25 0 C , = 1.0 MHz)
I
Symbol
I
Typ
I
Unit
Input Capacitance
I
Gin
I
5.0
I
pF
Output Capacitance
I
Cout
I
5.0
Characteristic
2-165
I
pF
I
i
I
•
•
MCM6670-MCM6674
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted.)
AC TEST LOAD
5.0 V
RL
AC TEST CONDITIONS
Condition
Value
Input Pulse Levels
Test Point
o-......~r--+....-
0.8 V to 2.0 V
Input Rise and Fall Times
Output Load
20 os
30 pF
1 TTL Gate and CL = 30 pF
;OF
= 2.5
k
..,. MMD6150
or Equiv
11.7 k
MMD7000
,.
or Equiv
AC CHARACTERISTICS
Characteristic
Symbol
Min
Max
tcyc
350
-
ns
tacc(A)
350
ns
tacc(RS)
-
350
ns
tco
-
150
ns
Cycle Time
Address Access Time
Row Select Access Time
Chip Select to Output Delay
Unit
TIMING DIAGRAM
..
tcyC
tacc(A)
Address
=.=y
~
2.0 V
0.8 V
I
tacc( RS)
RS
X
cs
2.0 V
0.8 V
K
2.0 V
0.8 V
teo
2.0~
0.8 V
Data Out
.)1\,
~=
Don't Care
2-166
2A V
04 V
X
Data Valid
~
~
MCM6670·MCM6674
CUSTOM PROGRAMMING FOR MCM6670
as VOH; the dots left blank will be at VOL. RO is always
programmed to be blank (VOL). (Blank formats appear at
the end of this data sheet for your convenience; they are
not to be submitted to Motorola, however.)
2. Convert the characters to hexadecimal coding treating dots as ones and blanks as zeros, and enter this information in the blocks to the right of the character font
format. The information for D4 must be a hex one or
zero, and is entered in the left block. The information for
D3 thru DO is entered in the right block, with D3 the
most significant bit for the hex coding, and DO the
least significant.
3. Transfer the hexadecimal figures either to punched
cards (Figure 3) or to paper tape (Figurp 51.
4. Transmit this data to Motorola, along with the
customer name. customer part number and revision, and
an indication that the source device is the MCM6670.
By the programming of a single photomask, the customer may specify the content of the MCM6670. Encoding of the photomask is done with the aid of a computer to provide quick, efficient implementation of the
custom bit pattern while reducing the cost of implementation.
I nformation for the custom memory content may be
sent to Motorola in the following forms, in order of
preference:
1. Hexadecimal coding using IBM Punch Cards (Figures 3 and 4).
2. Hexadecimal coding using ASCII Paper Tape Punch
(Figure 5).
Programming of the MCM6670 can be achieved by
using the following sequence:
1. Create the 128 characters in a 5 x 7 font using
the format shown in Figure 1. Note that information at
output D4 appears in column one, D3 in column two,
thru DO information in column five. The dots filled in
and programmed as a logic "1" will appear at the outputs
5. Information should be submitted on an organizational data form such as that shown in Figure 2.
FIGURE 1 - CHARACTER FORMAT
Character Numbe(kVmm~&/Alf'(/!?
ROW SELECT
TRUTH TABLE
RS3 RS2 RSI
0
0
0
0
0
0
1
1
0
1
0
1
1
1
1
1
0
0
1
1
0
1
0
1
MSB
LSB
Character
HEX
MSB
RO 00000 () 0
Rl 0018100 0 "
R20 01810 0 A
R3 181 0 0 0181 I I
R4 1&1 00 0 ~ I I
R5 1&1 ~ 181 ~ 181 { F
RS 181 0 0 181 I I
R7liaDODI8I I I
0403
DO
OUTPUT
RO
Rl
R2
R3
R4
R5
RS
R7
Number(,.CII51?JA7€~ IlJfrJT)
LSB
HEX
RoOOOOD
00
12!118I181181131
I F
R1
R21810000 I 0
R3 ~OOOO I 0
R4~
~OO
I C
R5 t8I 0000 I 0
RSI8I 000 / ()
R7 181181181 ~ 181 I F
0403
DO
FIGURE 2 - FORMAT FOR PROGRAMMING GENERAL OPTIONS
ORGANIZATIONAL DATA
MCM6670 MOS READ ONLY MEMORY
Customer:
Motorola Use Only:
Company ___________________________________
Quote: ________________________
Part No.
Originator ________________________________
Phone No. __________________________
Chip-Select Options:
CS
Part No ..
Speci!. No.:
Active High
Active Low
1
o
D
D
2-167
No-Connect
D
II
MCM667OeMCM6674
FIGURE 3 - CARD PUNCH FORMAT
Columns
1·9 Blank
10·25 Hex coding for first character
26
Slash (I)
27·42 Hex coding for second character
43
Slash (I)
44·59 Hex coding for third character
60
Slash (I)
61·76 Hex coding for fourth character
77·78 Blank
79·80 Card number (starting 01; thru 32)
Column lOon the first card contains either a zero or
a one to program D4 of row RO for the first character.
Column 11 contains the hex character for D3 thru DO.
Columns 12 and 13 contain the information to program
R1. The entire first character is coded in columns 10 thru
25. Each card contains the coding for four characters;
32 cards are required to program the entire 128 characters.
The characters must be programmed in sequence from
the first character to the last in order to establish proper
addressing for the part. Figure 3 provides an illustration of
the correct format.
FIGURE 4 - EXAMPLE OF CARD PUNCH FORMAT
(First 12 Charactars of MCM6670P4)
••• 0000°°11°0000000000011111°°°1°1°1°1°1°11111°10101°101000111101010101010000110
12345'J.'m"nQ~~3nUR~~nnNft.R
•• H~U»MU.~ •• u~aU~6.QUUH~UQMH.nMHUfluaMUAnuu.nnnH~_D.~.
11111111111111111111111111111111111111111111111111111111111 111111111111111111111
22222222222221111111111222222222222222222222222222222222222222222222222222222222
o
333333333333 J J J J J J 3 3 3 J J 3 333 3 3 J 3 3 3 3 3 3 3 33 3 3 3 3 3 3 3 3 3 3 3 J 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 33 3 3 3 ~
44444444444444444444444444444444444444444444441414141414144444444444444444444444
55555555555555555555555555555555555555555555555555555555555555555555555555555555
0
~
&&&&&&&&&&&&1&6&&16666661116&1&&&&&&&&&&6&&&6&&&&&1&&6&&6&166666&&6666666661&&~6
1111111111111111 I I I I I 1111111111111111111 11111111 III 1111111111111111 1111111111117
.11.111'.81.8811111111111118118111188888888888.88.88 8 818 8 8 8 8 8 8 8 8 8 8.8888.8.111111
!119999999999999999999!9999'99999'999999999999999999999999S999999S99!99'99999999
I t J 4 t • 7. '"11" P M 151817" ,UUI unH2UI 21 2I2U' 31
GLOU $-1
STANDARD fORM
:n3334n:lln.!'404I4HHU54&4H"9~~;1 ~B~::.I5lI5UHS ;~5~:'~",
,~. ~'., ··~:;o"
727374J511n alln
FIGURE 5 - PAPER TAPE FORMAT
Frames
Leader
1 toM
M + I, M + 2
M+3toM+66
M +67, M +68
M +69to
M +2114
Blank Tape
Allowed for customer use (M ... 64)
CR; LF (Carriage Return; Line Feed)
First line of pattern information
(64 hex figures per line)
CR;LF
Remaining 31 lines of hex figures,
each line followed by a Carriage Re·
turn and Line Feed
Blank Tape
Frames 1 to M are left to the customer for internal
identification, where M... 64. Any combination of alpha·
numerics may be used. This information is terminated
with a Carriage Return and Line Feed, delineating the
start of data entry. (Note that the tape cannot begin with
a CR and/or LF, or the customer identification will be
assumed to be programming data.)
Frame M + 3 contains a zero or a one to program D4
of row RO for the first character. Frame M + 4 contains
the hex character for D3 thru DO, completing the pro·
gramming information for RO. Frames M + 5 and M + 6
contain the information to program R 1. The entire first
character is coded in Frames M + 3 thru M + 18. Four
complete characters are programmed with each line. A
total of 32 lines program all 128 characters (32 x 4).
The characters must be programmed in sequence from the
first character to the last in order to establish proper
addressing for the part.
2-168
MCM6670-MCM6674
The formats below are given for your convenience in preparing character information for MCM6670 programming. THESE
FORMATS ARE NOT TO BE USED TO TRANSMIT THE INFORMATION TO MOTOROLA. Refer to the Custom Programming instructions for detailed procedures.
Character Number _ __
MSB
LSB
HEX
RODj'DDDD 0
R1D.DDDD
R2DIDDDO
R3GDDDD
R4DlbDDD
R5DDDDD
R6 DI'DDDD
R7DDDDD
0403
0
00
LSB
MSB
HEX
LSB
Character Number _. _ __
HEX
MSB
RO 0 DOD 0 0
R1DODDD
R200DDO
R3DODDD
R4DODDO
R5DODDO
R6D DOD
R70000D
04 03
Character Number _ __
MSB
Character Number _ __
00
MSB
LSB
DO
0403
Character Number _ __
MSB
LSB
HEX
DO
LSB
LSB
DO
0 0
HEX
0
0403
DO
LSB
HEX
RODODOO
R100000
R2DOOOO
R3DOOOO
R4DODOO
R5DODDO
R600000
R700DOO
0 0
MSB
HEX
DO
LSB
HEX
Character Number _ _ _
MSB
LSB
04103
MSB
0
DO
LSB
HEX
ROOOODO
R100000
R2DOOOO
R3DODDC]
R4DODOO
R5DOODO
R6DOOOO
R700DOD
00
04 03
2-169
DO
MSB
LSB
HFX
RodODOD 00
R100000
R200DOO
R300DOO
R40000D
R5DODDO
R600000
mOODOO
DO
Character Number _ _ __
MSB
LSB
RO 00000
R10000D
R200DOO
R300DDO
R400000
R5DODDO
R600000
R700DOD
0403
Character Number _ __
HEX
ROO DOD o
R100000
R200DOO
R300000
R4DOOOO
R5DOODO
R60 DOD
R700000
DO
DO
Chnracter Number _ _ __
0403
RO 00000 0 0
R100000
R2DODOO
R300DOO
R4DOODO
R500DDO
R600DOO
R7DODOD
0403
RODODDD o
R1DODDD
R2000DO
R3DDDDO
R4DODOO
R5DODDD
R6DoDDo
R7DDDDD
04 D3
HEX
Character Number _ _ . _
DO
CharClcter Number _ _ _
MSB
LSB
0403
RODODDD 0 0
R1DODDO
R200DDO
R3DODDO
R4DDDOO
R5DDDDD
R6DODDO
R7DDDDD
0403
MSB
RO 00000
R100000
R200DOO
R300000
R4 00DDD
R500DDO
R600000
R70DDOO
MSB
HEX
Character NumI-Jer _ __
MSB
HEX
0 0
Character Number _ _ _ _
RODDDDD 00
R1DDDDD
R2DODDO
R3DODDO
R4DODDD
R5DODDD
R6DODDO
R7DDDDD
0403
LSB
RODODOD
R100000
R200DDO
R3DOODO
R4DOODO
R5DOODO
R6DODOO
R700DOO
04 03
Character Number _ __
Character Number _ _ __
HEX
0 01
DO
Character Number . _ __
MSB
LSB
HEX
RO 00000 o
R100DOO
R200000
R300DOO
R4 00DDO
R500000
R6DOODO
R70000D
0403
DO
0
•
MCM6670-MCM6674
FIGVRE 6 - MCM6674 PATTERN
2-170
®
MOTOROLA
8192-BIT READ ONLY MEMORIES
ROW SELECT CHARACTER GENERATORS
The MCM66700 is a mask-programmable 8192-bit horizontal-scan
(row select) character generator. It contains 128 characters in
a 7 X 9 matrix, and has the capability of shifting certain characters
that normally extend below the baseline such as i. y, g, p, and
q. Circuitry is supplied internally to effectively lower the whole
MCM66700 MCM66710
MCM66714 MCM66720
MCM66730 MCM66734
MCM66740 MCM66750
MCM66751 MCM66760
MCM66770 MCM66780
MCM66790
matrix for this type of character-a feature previously requiring
external circuitry.
MOS
A seven-bit address code is used to select one of the 128 available
characters. Each character is defined as a specific combination of
logic 1s and Os stored in a 7 X 9 matrix. When a specific four-bit
binary row select code is appl ied, a word of seven parall el bits appears
at the output. The rows can be sequentially selected, providing
a nine-word sequence of seven parallel
bits per word for each
character selected by the address inputs. As the row select inputs
are sequentially addressed, the devices will automatically place
(N-CHANNEL, SILICON-GATE)
8K READ ONLY MEMORIES
HORIZONTAL-SCAN
CHARACTER GENERATORS
WITH SHIFTED CHARACTERS
the 7 X 9 character in one of two preprogrammed positions on
the 16-row matrix, with the positions defined by the four row
select inputs. Rows that are not part of the character are
automatically blanked.
The devices listed are preprogrammed versions of the MCM66700.
They contain various sets of characters to meet the requirements
of diverse applications. The complete patterns of these devices
are contained in this data sheet.
•
•
•
Fully Static Operation
Fully TTL Compatible with Three-State Outputs
CMOS and MPU Compatible, Single ± 10% 5 Volt Supply
•
Shifted Character Capability
(Except MCM66720, MCM66730, and MCM66734)
•
•
•
Maximum Access Time = 350 ns
4 Programmable Chip Selects (0, 1, or X)
Pin-far-Pin Replacement for the MCM6570,
Including All Standard Patterns
AO
15
A1
16
A2
12
A3
11
A4
C SUFFIX
FRIT-SEAL CERAMIC PACKAGE
CASE 623-04
~"i
24.
1 !
P SUFFIX
PLASTIC PACKAGE
CASE 709-02
PIN ASSIGNMENT
Address
Decode
Vee
Memory
Matrix
(8064)
A5
A6
06
4
04
02
Shift
00
Control
Matrix
BLOCK
Al
(128)
DIAGRAM
A2
Vss
OS9516/8-78
2-171
MCM66700 Series
ABSOLUTE MAXIMUM RATINGS (See Note 1, Voltages Referenced to Vss)
Rating
Symbol
Value
Unit
Vee
-0.3 to 7.0
Vdc
Input Voltage
Vin
Operating Temperature Range
TA
T stg
-0.3 to 7.0
o to +70
-55 to +125
Vdc
DC
Supply Voltages
•
Storage Temperature Range
ue
NOTE 1: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation, should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher-than-recommended voltages for
extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted)
RECOMMeNDED DC OPERATING CONDITIONS (Referenced to VSS)
Symbol
Min
Nom
Max
Unit
Supply Voltage
Vee
5.0
5.5
Vdc
I nput Logic "1" Voltage
VIH
-
Vee
Vdc
Input Logic "0" Voltage
VIL
4.5
2.0
-0.3
-
0.8
Vdc
Symbol
Min
Typ
Max
Unit
IIH
-
-
2.5
"Adc
Output Low Voltage (Blank)
(I0L = 1.6 mAdc)
VOL
0
0.4
Vdc
Output High Voltage (Dotl
(I0H = -205 "Adc)
VOH
2.4
-
-
Vdc
ICC
Po
-
-
80
440
mAdc
200
Parameter
DC CHARACTERISTICS
Characterjstic
Input Leakage Current
(VIH = 5.5 Vdc, Vee
Power Supply Current
Power Dissipation
= 4.5 Vdc)
mW
CAPACITANCE (Periodically sampled rather than 100% tested)
Input Capacitance
(f
= 1.0 MHz)
Output Capacitance
If = 1.0 MHz)
Cin
-
4.0
7.0
pF
Cout
-
4.0
7.0
pF
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that
normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
2-172
MCM66700 Series
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted)
ACTEST LOAD
5.0 V
Test Point o-.....-
2.0 V
0.8 V
t:x
2.0 V
.
;!<.)VVV<.
0.8 V
'CO
2.0 V
./'...XX~
0.8 V
_'DHD~
_'DHA
2.4 V
0.4 V
Data Out
2-187
.x
X/'...;!<.
II
MCM68A30A-MCM68B30A
CUSTOM PROGRAMMING
By the programming of a single photomask for the
MCM68A30A/MCM68B30A, the customer may specify
the content of the memory and the method of enabling
the outputs.
FIGURE 2 - BINARY TO HEXADECIMAL CONVERSION
Binary
Hexadecimal
Character
Data
Information on
the general
options of the
MCM68A30A/MCM68B30A should be submitted on
an Organizational Data form such as that shown in Figure
3. IUNo Connect" must always be the highest order Chip
Select pinlsl.1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
5
1
1
0
6
1
2
1
1
3
0
0
4
1
1
7
0
8
1
9
1
0
A
1
1
8
1
1
0
0
0
C
1
1
D
1
1
1
0
E
1
1
1
1
F
1
1
3. EPROM IMCM2708, MCM27A08, or MCM68708).
0
0
0
1
1. Paper tape output of the Motorola M6800 Software.
1
0
1
1
2. Hexadecimal coding using IBM Punch Cards.
0
1
0
0
0
0
1
Information for custom memory content may be sent
to Motorola in one of four forms Ishown in order of
preference 1:
0
0
4. Hand·punched paper tape IFigure 31.
PAPER TAPE
IBM PUNCH CARDS
Included in the software packages developed for the
M6800 Microcomputer Family is the ability to produce
a paper tape output for computerized mask generation.
The hexadecimal equivalent Ifrom Figure 21 may be
placed on 80 column IBM punch cards as follows:
The assembler directives are used to control allocation
of memory, to assign values for stored data, and for
controlling the assembly process. The paper tape must
specify the full 1024 bytes.
2-188
Step
1
Column
12
2
13
3
14·75
4
77·80
Byte "0" Hexadecimal equivalent for
outputs D7 thru D4 ID7 = M.S.B.I
Byte "0" Hexadecimal equivalent for
outputs D3 thru DO ID3 = M.S.B.I
Alternate steps 1 and 2 for consecutive
bytes.
Card number Istarting 00011
MCM68A30A-MCM68B30A
FIGURE 3 - HAND·PUNCHED PAPER TAPE FORMAT
Frames
Leader
1 to M
M+1,M+2
M +3 to M + 66
M + 67, M + 68
M + 69 to M + 2112
Blank Tape
Allowed for customer use (M ";;;64)
CR; LF (Carriage Return; Line
Feed)
First line of pattern information
(64 hex figures per line)
CR;LF
Remaining 31 lines of hex figures,
each line followed by a Carriage
Return and Line Feed
Blank Tape
Frames 1 to M are left to the customer for internal
identification, where M .,;;; 64. Any combination of alpha·
numerics may be used. This information is terminated
with a Carriage Return and Line Feed, delineating the
start of data entry. (Note that the tape cannot begin
with a CR and/or LF, or the customer identification will
be assumed to be programming data.)
Option A (1024 x 8)
Frame M + 3 contains the hexadecimal equivalent of
bits D7 thru D4 of byte O. Frame M + 4 contains bits
D3 thru DO. These two hex figures together program byte
O. Likewise, frames M + 5 and M + 6 program byte 1,
while M + 7 and M + 8 program byte 2. Frames M + 3 to
M + 66 comprise the first line of the printout and program,
in sequence, the first 32 bytes of storage. The line is
terminated with a CR and LF.
Option B (2048 x 4)
Frame M + 3 contains the hexadecimal equivalent
of byte 0, bits D3 thru DO. Frame M + 4 contains byte 1,
frame M + 5 byte 2, and so on. Frames M + 3 to M + 66
sequentially program bytes 0 to 31 (the first 32 bytes).
The line is terminated with a CR and LF.
Both Options
The remaining 31 lines of data are punched in sequence
using the same format, each line terminated with a CR
and LF. The total 32 lines of data contain 32 x 64 or
2048 characters. Since each character programs 4 bits of
information, a full 8192 bits are programmed.
As an example, a printout of the punched tape for
Figure 13 would read as shown in Figure 10 (a CR and
LF is implicit at the end of each line).
FIGURE 4 - FORMAT FOR PROGRAMMING GENERAL OPTIONS
ORGANIZATIONAL DATA
MCM68A30A/68B30A MOS READ ONLY MEMORY
Customer:
Motorola Use Only:
Company
Quote: _ _ _ _ _ _ _ _ _ _ __
Part No.
Part No.: _ _ _ _ _ _ _ _ _ _ __
Originator _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Specif. No.: _ _ _ _ _ _ _ _ _ __
Phone No. _ _ _ _ _ _ _ _ _ _ _ __
Chip Select Options:
CS1
CS2
CS3
CS4
Active
High
Active
Low
D
D
D
D
D
D
0
0
2-189
No Connect
"Don't Care"
0
0
0
0
•
®
MCM68A308
MCM68B308
MOTOROLA
MOS
1024 X 8·BIT READ ONLY MEMORY
The MCM68A308/MCM68B308 is a mask-programmable byteorganized memory designed for use in bus-organized systems. It is
fabricated with N-channel silicon·gate technology. For ease of use,
the device operates from a single power supply, has compatibility
with TTL and DTL, and needs no clocks or refreshing because
of static operation.
The memory is compatible with the M6800 Microcomputer
Family, providing read only storage in byte increments. Memory
expansion is provided through multiple Chip Select inputs. The
active level of the Chip Select inputs and the memory content
are defined by the customer.
• Organized as 1024 Bytes of 8 Bits
• Static Operation
• Th ree-State Data Output
• Mask-Programm·able Chip Selects for
Simplified Memory Expansion
• Single ± 10% 5-Volt Power Supply
• TTL Compatible
• Maximum Access Time ~ 350 ns - MCM68A308
250 ns - MCM68B308
• 350 mW Typical Power Dissipation
IN-CHANNEL, SILICON-GATE)
1024 X 8·BIT
READ ONLY MEMORY
C SUFFIX
FRIT-SEAL CERAMIC PACKAGE
CASE 623·04
P SUFFIX
PLASTIC PACKAGE
CASE 709-02
PIN ASSIGNMENT
MOTOROLA'S PIN-COMPATIBLE EPROM FAMILY
••
A7
32K
A6
AI
AI
••
A5
AS
A4
S3
S1
...
S4
D01
DQ2
S2
MCM2718
07
MOTOROLA'S PIN-COMPATIBLE ROM FAMILY
06
11K
05
04
03
PIN NAMES
11
Q3
MCM88A31&E
AO-A9 . . . . Address Inputs
51-54.
. Chip Selects
00-07 .
. Data Output
Vee . . . .
INDUSTRY STANDARD PINOUTS
+5
V Power Supply
vss . . . . Ground
DS9601 16--78
. 2-190
MCM68A308·MCM68B308
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted)
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Min
Typ
M;'1x
Unit
Supply Voltage
VCC
5.0
Input High Voltage
VIH
VIL
5.5
5.5
0.8
Vdc
I nput Low Voltage
4.5
2.0
-0.3
Parameter
~
.-
Vdc
Vdc
DC CHARACTERISTICS
Characteristic
Symbol
Input Current
IVin =
0 to 5.5
Output Low Voltage
1.6
,uAde
VOH
2.4
VOL
--
~
Vdc
0.8
0.4
Vdc
ILO
10
,LIAne
ICC
130
mArie
mAl
Output Leakage Current (Three-State)
V or
S = 2.0 V,
V out =
0.4
V to
2.4
VI
Supply Current
IVCC =
Unit
2.5
-205 ~AI
IIOH =
IS =
Max
VI
Output High Voltage
IIOL =
Min
lin
5.5
V, TA = OOCI
ABSOLUTE MAXIMUM RATINGS
Rating
IS •• Note
11
Symbol
Value
Unit
VCC
-0.3 to +7.0
Vdc
Input Voltage
Vin
-0.3 to +7.0
Vdc
Operating Temperature Range
TA
Supply Voltage
Storage Temperature Rnnge
T stg
o to
-65
to
+70
°c
+ 150
DC
NOTE 1: Permanent device damage may occur
if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be
M6800 MICROCOMPUTER FAMILY
BLOCK DIAGRAM
restricted to RECOMMENDED OPERATING
CONDITIONS. Exposure to higher than recom-
mended voltages for extended periods of time
could affect deyice reliability.
Addr.ss
Bus
BLOCK
DIAGRAM
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
51'
5253'
54'
8
00
01
02
03
04
05
16 06
17 07
9
10
11
13
14
15
6
Address
4
3
Data
Bus
Decade
1
23
22
20
18
21
19
Vee'" Pin 24
VSS=Pin12
• Active level defined by the user.
2-191
II
MCM68A308-MCM688308
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature unles') otherwise noted.
All timing with tr = tf:::: 20 ns, Load of Figure 1)
MCM68B308
MCM68A30B
Symbol
Min
Cycle Time
tcyc
350
Access Time
tace
-
Chip Select to Output Delay
tso
Characteristic
Max
Min
Max
-
350
250
150
150
Data Hold from Address
tDHA
10
-
10
Data Hold from Deselection
tDHD
10
150
10
CAPACITANCE
Unit
ns
250
ns
ns
ns
150
ns
This device contains circuitry to protect
the inputs against damage due to high static
voltages or electric fields; however, it is
advised that normal precautions be taken
to avoid application of any voltage higher
than maximum rated voltages to this
high-impedance circuit.
(I: 2.0 MHz, T A : 25°C, periodically sampled rather than 100% tested I
Characteristic
Input Capacitance
Output Capacitance
FIGURE 1 - AC TEST LOAD
5:0 V
AL "" 2.5 k
Test Point
.....- ..
O--.....-1~--+
130 pF· ;;"
11.7 k
,r
MM06150
~
MM07000
"
or Equ;v
or Equiv
-'ncludes Jig Capacitance
TIMING DIAGRAM
tCYC
tace
Address
:=y
2.0 V
0.8 V
~
~
2.0 V
s
0.8 V
'so
2.0 V
0.8 V
~
.X
r-'OHO~
I-'OHA
Data OUt
~
~
~
"" Don't care
2-192
2.4 V
0.4 V
~
~
MCM68A308e MCM68B308
CUSTOM PROGRAMMING
FIGURE 2 - BINARY TO' HEXADECIMAL CONVERSION
By the programming of a single photomask for the
MCM68A308/MCM68B308, the customer may specify
the content of the memory and the method of enabling
the outputs. (A "no-connect" must always be the highest
order chip-select(s).)
Binary
0
0
0
0
0
Information
on
the
general
options of the
MCM68A308/MCM68B308 should be submitted on an
Organizational Data form such as that shown in Figure 4.
0
0
0
1
1
Information for customer memory content may be
sent to Motorola in one of four forms (shown in order
of preference) :
1.
2.
3.
4.
Hexadecimal
Character
Data
1
1
1
1
1
1
Paper tape output of the Motorola M6800 Software.
Hexadecimal coding using IBM Punch Cards.
EPROM one MCM68A708 or equivalent.
Hand punched paper tape (Figure 3).
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
0
0
0
1
1
1
1
0
1
1
0
0
0
1
1
0
1
0
1
0
1
0
2
3
4
1
0
6
5
1
7
0
1
8
9
0
1
0
1
A
B
0
1
C
0
E
F
IBM PUNCH CARDS
The hexadecimal equivalent (from Figure 2) may be
placed on 80 column IBM punch cards as follows:
PAPER TAPE
Step
Column
1
12
2
13
3
14-75
4
77-80
Included in the software packages developed for the
M6800 Microcomputer Family is the ability to produce
a paper tape output for computerized mask generation.
The assembler directives are used to control allocation
of memory, to assign values for stored data, and for
controlling the assembly process. The paper tape must
specify the full 1024 bytes.
Byte "0" Hexadecimal equivalent for
outputs 07 thru 04 (07 = M.S.B.)
Byte "0" Hexadecimal equivalent for
outputs 03 thru 00 (03 = M,S.B.)
Alternate steps 1 and 2 for consecutive
bytes.
Card number (starting 0001)
FIGURE 3 - HAND·PUNCHED PAPER TAPE FORMAT
Frames
Leader
1 to M
M + 1, M
Blank Tape
Allowed for customer use (M ";64)
CR; LF (Carriage Return; Line
Feed)
First line of pattern information
(64 hex figures per line)
CR; LF
Remaining 31 lines of hex figures,
each line followed by a Carriage
Return and Line Feed
Blank Tape
with a CR andlor LF, or the customer identification will
be assumed to be programming data.)
Frame M + 3 contains the hexadecimal equivalent of
bits 07 thru 04 of byte O. Frame M + 4 contains bits
03 thru 00. These two hex figures together program byte
O. Likewise, frames M + 5 and M + 6 program byte 1,
while M + 7 and M + 8 program byte 2. Frames M + 3 to
M + 66 comprise the first line ofthe printout and program,
in sequence, the first 32 bytes of storage. The line is
terminated with a CR and LF.
Frames 1 to M are left to the customer for internal
identification, where M ..; 64. Any combination of alphanumerics may be used. This information is terminated
with a Carriage Return and Line Feed, delineating the
start of data entry. (Note that the tape cannot begin
The remaining 31 lines of data are punched in sequence
using the same format, each line terminated with a CR
and LF. The total 32 lines of data contain 32 x 64 or
2048 characters. Since each character programs 4 bits of
information, a full 8192 bits are programmed.
+2
M + 3 to M + 66
M + 67, M + 68
M + 69 to M + 2112
2-193
MCM68A308-MCM688308
FIGURE 4 - FORMAT FOR PROGRAMMING GENERAL OPTIONS
..
ORGANIZATIONAL DATA
MCM68308 MOS READ ONLY MEMORY
Motorola Use 0 nl y:
Customer:
Company _________________________________
Quote: _____________________
Part No.
Part No.: _____________________
Originator _________________________________
Specif. No.: _________________
Phone No. ________________________
Chip Select:
51
52
53
54
Active
High
Active
Low
No
Connect
D
0
D
0
D
D
D
0
D
D
0
0
2-194
®
MCM68A316A
MOTOROLA
2048 X 8-BIT READ ONLY MEMORY
MOS
The MCM68A316A is a mask-programmable byte-organized
memory designed for use in bus-organized systems. It is fabricated
with N·channel silicon-gate technology. For ease of use, the device
operates from a single power supply, has compatibility with TTL
and DTL, and needs no clocks or refreshing because of fully
static operation.
(N·CHANNEL, SILICON-GATE)
2048 X 8-BIT
READ ONLY MEMORY
The memory is compatible with the M6800 Microcomputer
Family, providing read·only storage in byte increments. Memory
expansion is provided through multiple Chip Select inputs. The
active level of the Chip Select inputs and the memory content
are defined by the user.
•
•
•
•
•
•
•
e SUFFIX
F"IT·SEAL CERAMIC PACKAGE
CASE 623-04
Fully Static Operation
Three-State Data Output
Mask·Programmable Chip Selects for
Simplified Memory Expansion
Single ± 10% 5-Volt Power Supply
TTL Compatible
Maximum Access Time = 350 ns
Plug-in Compatible with 2316A
P SUFFIX
PLASTIC PACKAGE
CASE 709-02
ABSOLUTE MAXIMUM RATINGS (See Note 1)
Rating
Supply Voltage
Symbol
Value
Unit
VCC
-0.3 to +7.0
-0.3 to +7.0
to +70
-65 to +150
Vdc
Input Voltage
Vin
Operating Temperature Range
TA
T stg
Storage Temperature Range
NOTE 1:
o
Vdc
°c
°c
PIN ASSIGNMENT
Permanent deVice damage may occur if ABSOLUTE MAXIMUM RATINGS are
A7
Vee
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages
for extended periods of time could affect device reliability.
AS
00
M6800 MICROCOMPUTER FAMILY BLOCK OIAGRAM
A9
01
Al0
02
AO
03
Al
04
A2
05
A3
06
A4
Q7
A5
A6
51
52
Vss
53
PIN NAMES
AO-A10.
S1-S3
QD-Q7
Address
Data
Bus
Bus
· Address Inputs
· Chip Selects
. . Data Output
Vec
· +5 V Power Supply
Vss
· Ground
DS9502/6-78
2-195
•
•
MCM68A316A
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted)
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Min
Typ
Max
Unit
Supply Voltage
VCC
4.5
5.0
5.5
Vdc
Input High Voltage
VIH
2.0
5.5
Vdc
Input Low Voltage
VIL
-0.3
-
0.8
Vdc
Parameter
DC CHARACTERISTICS
lin
Min
-
Output High Voltage
(lOH = -205 pAl
VOH
2.4
Output Low Voltage
VOL
-
0.4
Vdc
ILO
-
10
pAdc
ICC
-
130
mAde
Characteristic
Symbol
Input CUrrent
Max
Unit
2.5
pAdc
(Vin = 0 to 5.5 V)
Vdc
(lOL=I.6mAl
Output Leakage Current (Three-State)
(S = 0.8 V or
S = 2.0 V, V out = 0.4 V
to 2.4 V)
Supply Current
(VCC = 5.5 V, TA = OoC)
CAPACITANCE
(f '"' 2.0 MHz, T A
I
= 25°C, periodically sampled rather than 100% tested)
I
Characteristic
I Input Capacitance
I
I
LOutput Capacitance
Symbol
Cin
Cout
I
I
I
Max
Unit
7.5
pF
12.5
pF
I
I
I
This device contains circuitry to protect the
inputs against damage due to high static volt·
ages or electric fields; however, it is advised that
normal precautions be taken to avoid applica·
tion of any voltage higher than maximum rated
voltages to this high impedance circuit.
FIGURE l-AC TEST LOAD
50V
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature unless otherwise noted.
All timing with tr
Characteristic
= tf
=
Min
Cycle Time
tcyC
Access Time
tace
Chip Select to Output Delay
tso
Data Hold from Address
s,'
Unit
350
-
ns
-
350
ns
150
ns
10
-
ns
tH
10
150
ns
AD 5
Al 6
A2 7
A3 8
A4 9
A5 10
A6 11
A7
A8
A9 3
AID 4
BLOCK
Max
tOHA
Data Hold from Deselection
DIAGRAM
..-~
Test PoInt c>-~~r---t
20 ns, Load of Figure 1)
Symbol
130 pF·
MM07000
or Equiv
·Includes Jig Capacitance
23
22
21
20
19
18
17
16
Address
Decode
00
01
02
03
04
05
06
07
15
$"3* 13
Vee == Pin 24
Vss
Active level defined by the user.
2-196
or Equiv
11.7 k
52+- 14
*
MM06150
=
Pin 12
-
MCM68A316A
TIMING DIAGRAM
.
tcyC
_I
tace
s==:y
Addres
i
t:xt
2.0 V
0.8 V
'SO«)'
5
•
\
2.0 V
X
0.8 V
"XJ(
"X)O.
2.0 V
0.8 V
"XX X)(
~
X XXX)(X
f--tH::j
f-tDHA
Data Out
~
2.4 V
0.4 V
2-197
Ox
•
MCM68A316A
CUSTOM PROGRAMMING
FIGURE 2 - BINARY TO HEXADECIMAL CONVERSION
By the programming of a single photomask for the
MCM6B316A, the customer may specify the content of
the memory and the method of enabling the outputs.
Bmary
Data
0
0
Information
on
the
general
options of the
MCM68A316A should be submitted on an Organizational
Data form such as that shown in Figure 3.
0
0
Information for custom memory content may be sent
to Motorola in one of four forms (shown in order of
preference) :
Hexadecimal
Character
0
0
0
0
0
1
1
1
0
0
2
0
0
1
1
3
0
1
0
0
4
0
0
0
1
0
1
5
1
1
0
6
1
1
1
7
1
0
0
8
1
0
0
1
0
9
A
1
1
B
C
1
1. Paper tape output of the Motorola M6800 Software.
1
0
0
0
2. Hexadecimal coding using IBM Punch Cards.
1
1
0
0
1
1
0
1
D
3. EPROM (TMS2716 or MCM2716).
1
1
1
0
E
4. Hand-punched paper tape.
1
1
1
1
F
1
IBM PUNCH CARDS
PAPER TAPE
Included in the software packages developed for the
M6800 Microcomputer Family is the ability to produce a
paper tape output for computerized mask generation. The
assembler directives are used to control allocation of
memory, to assign values for stored data, and for control·
ling the assembly process. The paper tape must specify the
full 2048 bytes.
The hexadecimal equivalent (from Figure 2) may be
placed on 80 column IBM punch cards as follows:
Step
Column
1
12
Byte "0" Hexadecimal equivalent for
outputs Q7 thru Q4 (Q7 ~ M.S.B.)
2
13
Byte "0" Hexadeci mal equivalent for
outputs Q3 thru QO (03 ~ M.S.B.)
3
14-75
Alternate steps 1 and 2 for consecutive
bytes.
4
77-80
Card number (starting 0001)
Total number of cards (64)
FIGURE 3- FORMAT FOR PROGRAMMING GENERAL OPTIONS
ORGANIZATIONAL DATA
MCM68A316A MOS READ ONLY MEMORY
Customer:
Motorola Use Only:
Company _____________________________________
Quote: _________________________
Part No.
Part No.: _______________________
Originator ____________
Phone No. ___________________________
Specif. No.:
Chip Select:
'Don't Care
Active High
o
o
D
Active Low
o
o
D
(No Connect)
o
o
D
*A don't care must always be the highest order Chip Select (s l.
2-198
®
MCM68A316E
MOTOROL.A
MOS
2048 X 8 BIT READ ONLY MEMORY
(NCHANNEL. SILICON-GATEI
The MCM68A316E is a mask-programmable byte-organized
memory designed for use in bus-organized systems_ It is fabricated
with N-channel silicon-gate technology. For ease of use, the device
operates from a single power supply, has compatibility with TTL and
DTL, and needs no clocks or refeshing because of static operation.
The memory is compatible with the M6800 Microcomputer
Family, providing read only storage in byte increments. Memory
expansion is provided through multiple Chip Select inputs. The
active level of the Chip Select inputs and the memory content
are defined by the user.
2048 X 8 BIT
READ ONL Y MEMORY
C SUFFIX
FRIT -SEAL CERAMIC PACKAGE
CASE 62341
• Fully Static Operation
• Three-State Data Output
• Mask-Programmable Chip Selects for
Simplified Memory Expansion
• Single ±10% 5-Volt Power Supply
• TTL Compatible
• Maximum Access Time = 350 ns
• Plug-in Compatible with 2316E
• Pin Compatible with 2708 and TMS2716 EPROMs
P SUFFIX
PLASTIC PACKAGE
CASE 709-02
PIN ASSIGNMENT
MOTOROLA'S PIN-COMPATIBLE EPROM FAMILY
32K
UK
11K
MOTOROLA'S PIN-COMPATIBLE ROM FAMILY
32K
11K
PIN NAMES
AO-A 1 O.
.. Address Inputs
S1-S3 . . . . Chip Selects
aO-07 . . . . Data Output
.. + 5 V Power
Vee
Vss ' ... Ground
INDUSTRY STANDARD PINOUTS
Supply
059600/6-78
2-199
•
MCM68A316E
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted)
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Min
Typ
Max
Unit
Supply Voltage
Vee
4.5
5.0
5.5
Vde
Input High Voltage
VIH
2.0
-
5.5
Vde
Input Low Voltage
VIL
-0.3
-
0.8
Vde
Parameter
DC CHARACTERISTICS
Characteristic
Symbol
Min
Max
Unit
lin
-
2.5
/lAde
VOH
2.4
-
Vde
VOL
-
0.4
Vde
ILO
-
10
/lAde
130
mAde
I nput Current
IV in
=0 to 5.5 VI
Output High Voltage
IIOH
= -205/lAI
Output Low Voltage
IIOL
= 1.6 mAl
Output Leakage Current (Three-State)
IS
=0.8 V orS =2.0 V, V out = 0.4 V to 2.4 VI
Supply Current
IVee = 5.5 V, TA
lee
= oOel
ABSOLUTE MAXIMUM RATINGS ISee Note 11
Rating
Symbol
Value
Unit
Vee
-0.3 to +7.0
Vdc
Input Voltage
Vin
-0.3 to +7.0
Vde
Operating Temperature Range
Storage Temperature Range
TA
T stg
o to +70
°e
-65 to +150
°e
Supply Voltage
NOTE 1: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS .re
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages
for extended periods of time could affect device reliability,
r;======,----~------..,
CAPACITANCE
(f "" 2.0 MHz, T A"" 25°C, periodically sampled rather than 1 00% tested)
I
I
Characteristic
I I nput Capacitance
I
I
LOutput Capacitance
Symbol
I
Cin
Cout
I
I
Max
Unit
7.5
pF
12.5
pF
M6BOO MICROCOMPUTER FAMIL Y
BLOeK OIAGRAM
Address Data
Bus
AO
Al
A2
AJ
A4
AS
A6
A7
AS
A9
BLOCK
DIAGRAM
Al0
S
9 00
10 01
6
4
J
2
1
2J
22
19
8us
11 Q2
OJ
13
14
15
16
17
Address
Decode
04
05
06
07
51'
52'
53'
Vee'" Pin 24
*
Active level defined bv the user.
Gnd'" Pin 12
2-200
MCM68A316E
FIGURE l-AC TEST LOAD
50 V
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature unless otherwise noted.
All timing with tr = tf = 20 ns, Load of Figure 1)
Test POint
---1.--4....- ..
0 -....
......
130pF"
~
MM06150
or EqUiv
11.7k
MM07000
or Et:!ul\I
Characteristic
Symbol
Min
Max
Unit
Cycle Time
tcyc
350
-
ns
Access Time
Chip Select to Output Delay
tace
350
ns
'SO
-
150
ns
'DHA
10
-
ns
'H
10
150
ns
Data Hold from Address
Data Hold from Deselection
·Includes Jig Capacitance
TIMING DIAGRAM
This device contains circuitry to
protect the inputs against damage
due to high static voltages or electric fields; however. it is advised
that normal precautions be taken
to avoid application of any voltage higher than maximum rated
voltages to this high-impedance
circuit.
-.t eve
---------1
-----1
2-201
•
MCM68A316E
CUSTOM PROGRAMMING
FIGURE 2 - BINARY TO HEXADECIMAL CONVERSION
By the programming of a single photomask for the
MCM68A316E, the customer may specify the content of
the memory and the method of enabling the outputs.
Binary
Hexadecimal
Character
Data
0
0
0
0
0
0
0
Information on the general
options of the
MCM68A316E should be submitted on an Organizational
Data form such as that shown in Figure 3. ("No·Connect"
must always be the highest order Chip Select(s).)
,
,
,
,
,
,
,
,
,
,,
,
Information for custom memory content may be sent
to Motorola in one of three forms (shown in order of
preference) :
1. Paper tape output of the Motorola M6800 Software.
2. Hexadecimal coding using IBM Punch Cards.
3. EPROM (TMS2716 or MCM2716).
,
0
0
,
,
0
2
3
0
0
0
4
5
,
0
,
,
,
6
8
9
0
0
0
0
0
0
,
,
,
0
,
7
0
0
0
0
0
0
0
,
0
,
,
0
0
0
c
,
0
0
E
F
,
,
,
,
,
,
A
B
IBM PUNCH CARDS
PAPER TAPE
Included in the software packages developed for the
M6BOO Microcomputer Family is the ability to produce a
paper tape output for computerized mask generation. The
assembler directives are used to control allocation of
memory, to assign values for stored data, and for control·
ling the assembly process. The paper tape must specify the
fu II 204B bytes.
The hexadecimal equivalent (from Figure 2) may be
placed on 80 column· IBM punch cards as follows:
Step
Column
1
12
2
13
3
14-75
4
77-80
Byte "0" Hexadecimal equivalent for
outputs 07 thru 04 (07 = M.S.B.)
Byte "0" Hexadecimal equivalent for
outputs 03 thru 00 (03 = M.S.B.)
Alternate steps 1 and 2 for consecutive
bytes.
Card number (starting 0001)
Total number of cards (64)
FIGURE 3- FORMAT FOR PROGRAMMING GENERAL OPTIONS
ORGANIZATIONAL DATA
MCM68A316E MOS READ ONLY MEMORY
Customer:
Motorola Use Only:
Company __________________________________
Ouote: _________________________
Part No.
Part No.: _______________________
Originator ___________________________________
Phone No. __________________________
Chip Select:
Active
High
SI
S2
S3
o
o
o
2-202
Specif. No.:
Active
Low
D
0
0
No
Connect
0
0
0
@
MCM68A332
MOTOROLA
MOS
4096 X 8-BIT READ ONLY MEMORY
The MCM68A332 is a mask-programmable byte-organized
memory designed for use in bus-organized systems. It is fabricated
with N-channel silicon-gate technology. For ease of use, the device
operates from a single power supply, has compatibility with TTL and
DTL, and needs no clocks or refreshing because of static operation.
IN{;HANNEL. SILICON-GATE I
4096 X 8-BIT
READ ONLY MEMORY
The memory is compatible with the M6800 Microcomputer
Family, providing read only storage in byte increments. Memory
expansion is provided through multiple Chip Select inputs. The
active level of the Chip Select inputs and the memory content
are defined by the user.
•
Fully Static Operation
•
Three-State Data Output for OR-Ties
•
Mask-Prog,-ammable Chip Selects for Simplified Memory
C SUFFIX
FRIT-SEAL CERAMIC PACKAGE
CASE 623-04
Expansion
•
Single ± 10% 5-Volt Power Supply
•
Fully TTL Compatible
•
Maximum Access Time ~ 350 ns
•
Directly Compatible with 4732
•
Pin Compatible with 2708 and 2716 EPROMs
•
Preprogrammed MCM68A332-2 Available
P SUFFIX
PLASTIC PACKAGE
CASE 709-02
PIN ASSIGNMENT
MOTOROLA'S PIN·COMPATIBLE EPROM FAMILY
!14K
A7
AI
AS
A7
Vee
A6
A8
.u
A5
..
A9
A2
S2
ST
Al0
MCMM7!14
A11
MCMM7~
07
MOTOROLA'S PIN-COMPATIBLE ROM FAMILY
..
06
32K
A7
AS
A'
01
05
02
04
VSS
03
At
M
PIN NAMES
AO--A 11
S .
00-07 .
Vee.
INDUSTRY STANDARD PINOUTS
Vss
.. Address Inputs
Programmable
Chip Selects
. Data Output
. _ + 5 V Power Supply
. Ground
OS961917-78
2-203
•
MCM68A332
BLOCK
DIAGRAM
•
AO
AI
A2
A3
A4
A5
A6
A7
AS
A9
Ala
Al1
8
7
6
5
Address
Oecode
4
3
2
1
23
22
19
18
51·
52·
*
9 QO
10 Ql
11 Q2
13 Q3
14 Q4
15 QS
16 Q6
17 Q7
20
21
Vee
=
VSS
= Pin
Pin 24
12
Active level defined by the user.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted)
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Min
Typ
Max
Unit
Supply Voltage (Vee must be apphed at least 100 pS belore proper deVICe operatIOn IS achieved.)
Vee
4.5
5.0
5.5
Vdc
Input High Voltage
VIH
2.0
_.
5.5
Vdc
Input Low Voltage
VIL
-0.3
-
0.8
Vdc
Parameter
DC CHARACTERISTICS
Symbol
Min
Max
Unit
Input Current
(Vin = 0 to 5.5 VI
lin
-
2.5
,uAdc
Output High Voltage
VOH
2.4
Output Low Voltage
(lOL .~ 1.6 mAl
VOL
-
0.4
Vdc
Output Leakage Current (Three-State)
(S = DB V or S = 2.0 V, V out = 0.4 V to 2.4 VI
ILO
-
10
,uAdc
Supply Current
lee
-
80
mAde
Characteristic
Vdc
(IOH = -205 pAl
(Vee
=
5.5 V, TA = DOe I
ABSOLUTE MAXIMUM RATINGS
Rating
(See Note 1)
Symbol
Value
Unit
Vee
-0.3 to +7.0
Vdc
Input Voltage
Vin
-0.3 to +7.0
Vdc
Operating Temperature Range
TA
Supply Voltage
Storage Temperature Range
T stg
o to
+70
-65 to +150
°e
°e
NOTE1: Permanent deVice damage may occur If ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages
for extended periods of time could affect device reliability.
This device contains circuitry to
protect the inputs against damage
due to high !ltatic voltages or electric fields; however, it is advised
that normal precautions be taken
to avoid application of any voltage higher than maximum rated
voltages to this high-impedance
circuit.
CAPACITANCE
Characteristic
Input Capacitance
Output Capacitance
C out
M6800 MICROCOMPUTER FAMILY
BLOCK OIAGRAM
Address
Bus
2-204
Data
Bus
MCM68A332
FIGURE l-AC TEST LOAD
5.0 V
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature unless otherwise natecL
RL == 2.5 k
All timing with tr '" tf
Test Point
0--.--.>----+_._-. MMD6150
Characteristic
MMD7000
Min
tcyc
350
Access Time
lace
-
Chip Select to Output Delay
or equivalent
20 ns, Load of Figure 1)
Cycle Time
or equ ivalent
130pF·
=
Symbol
Data Hold from Address
Data Hold from Deselection
Max
-
350
Unit
ns
ns
tDHA
10
-
ns
ns
'H
10
150
ns
150
'SO
.. I ncl udes j i9 capacitance
TIMING DIAGRAM
~
_ _ _ _ _ _ _ _ _ _ tcyc _ _ _ _ _ _ _ _ _
~
~-------tacc------~
Address, A
2.0 V.
.8 V
Chip Select, S
~-----
Chip Select,
S
Output, Q
Waveform
Symbol
tso
----~..j
0.8 V
-------------------------~(~O~2:~~~~~_____J~----Waveform
Input
Output
MUST BE
WI LL BE
VALID
VALID
Symbol
Input
~ :~;;H~::EE
PERMITTED
2-205
Output
CHANGING:
STATE
UNKNOWN
Waveform
Symbol
=>-
Input
Output
-
HIGH
IMPEDANCE
MCM68A332
MCM68A332 CUSTOM PROGRAMMING
FIGURE 2 - BINARY TO HEXADECIMAL CONVERSION
By the programming of a single photomask for the
MCM68A332, the customer may specify the content of the
0
0
0
memory and the method of ~i1a.blin9 the outputs.
Information on the gerieral options of the MCM68A332
should be submitted on an Organizational Data form such as that
3. (A "No-Connect" or "Don't Care" must always
a
a
be the highest order Chip Select(s),)
Information for custom memory content may be sent to
0
.0
shown in
Fig~re
Hexadecimal
Character
Binary Data
a
Motorola in one of four forrt:"s (shown in order of preference):
1. IBM Punch"Cards:
A. Hexadecimal Format
1
1
1
1
1
1
1
1
B. Intel Format
C. Binary Negative-Postive Format
2. EPROMs-two 16K IMCM2716 or TMS2716) or four
BK IMCM2708)
3. Paper tape output of the Motorola .M6BOa software
0
0
a
a
a
1
a
1
O·
1
a
a
1
1
1
1
1
1
a
a
a
1
2
3
4
5
1
1
a
6
1
7
a
a
a
a
a
a
a
8
9
1
1
a
1
1
1
1
a
a
a
c
1
1
1
a
D
E
F
1
A
B
1
1
4. Hand punched paper tape
PRE-PROGRAMMED MCM68A332P2, MCM68A332C2
PAPER TAPE
Included, in, the software packages developed for the M6800
Microcomputer FamUy is the ability to produce a paper tape
output for computerized mask generation. The assembler directives are used to co~r01 a!location of memory. to assign values for
stored data. and for controlling the assembly process. The paper
tape must specify the full, 4096 bytes.
The -2 standard ROM pattern contains sine-lookup and arctanlookup tables.
Locations 0000 through 2001 contain, the sin~ values, The
sine's first quadrant is divided into 1000 parts with sine values
corresponding to these angles stored in the ROM. Sin 11:/2 is
included and 'is rounded .to 0.9999.
The 'arctan values contain angles in radians corresponding to
the arc tangents of 0 through 1 in steps of 0.001 and are contained
in locations 2048 through 4049.
Locations 2002 through 2047 and 4050 through 4095 are
zero filled.
All values are represented in absolute decimal format with four
digit precision. They are stored in BCD format with the two most
significant digits in the lower byte and the two least significant
digits in the upper byte. The decimal point i~ assumed to be to
the left of the most significant digit.
IBM PUNCH CARDS, i-tEXA~ECIMAL FORMAT
The hexadecimal equivalent (from Figure 2) may be placed on
80 column IBM, purtch cards as follows:
Step
Column
Byte "0" Hexadecimal equivalent for outputs
07 through 04 107 = M.S.B.)
Byte- "0" Hexadecimal equivalent for outputs
03 through 00103 = M.S.B.)
12
2
13
3
4
5
14-75
77-79
Alternate steps 1 and 2 for consecutive bytes.
Card number (starting 001).
Total number of cards must equal 128_
Example: Sin 110100
. Address
%) =·0.0016 decimal
Contents
0002
0003
0000
0001
0000
0110
FIGURE 3 - FORMAT FOR PROGRAMMING GENERAL OPTIONS
ORGANIZATIONAL DATA
MCM68A332 MOS READ ONL Y MEMORY
Customer:
Motorola Use Only
Company _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
Part No. _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Origin8tor ___________________
PhoneNo. _ _ _ _ _ _ _ _ _ _
Chip Select Options:
~~
____
Active High
S1
S2
0
0
Quote
Part No..
Specif. No.
Active Low
0
0
No-Connect
0
0
®
MCM68A364
MCM68B364
MOTOROI.A
MOS
8192 X 8-BIT REAt) ON;LY MEMORY
The MCM68A364/MCM688364 is a mask-programmable byteorganized memory designed for use in bus-organized systems. It is
fabricated with N-channel silicon-gate technology. For ease of use.
the device operates from a single power supply. and has
compatibility with TTL. The addresses are latched with the Chip Enable
input - no external latches required.
The memory is compatible with the M6800 Microcomputer
Family. providing read only storage in byte increments. The Chip
Enable input deselects the output and puts the chip in a power-down
mode.
• Automatic Power Down
• Low Power Dissipation -
8192 X 8-BIT
READ ONLY MEMORY
L SUFFIX
CERAMIC PACKAGE
CASE 716-06
150 mW active (typical)
35 mW standby (typical)
• Single ±10% 5-Volt Power Supply
• High Output Drive Capability (2 TTL Loads)
• Three-State Data Output for OR-Ties
• TTL Compatible
• Maximum Access Time -
(N-CHANNEl. SILICON-GATE)
P SUFFIX
PLASTIC PACKAGE
CASE 709-02
250 ns - MCM68B364
350 AS - MCM68A364
• Pin Compatible with 8K - MCI\l1&8A3D8. 16K - MCM68A316E.
and 32K - MCM68A332 Mask-Programmable ROMs
• Pin Compatible with 24-pin 64K EPROM MCM68764
.-
MOTOROLA'S PIN.cOMPATIIIU EJIIIIOM FAMILY
.,
AI
AI
...,. ,
AI
DOl
•
v u-c: ___=-.
PIN ASSIGNMENT
Vee
A7
A6
AS
A5
A9
A4
A12
A3
A2
A10
Al
All
AO
07
QQ
Q6
Ql
Q5
Q2
Q4
VSS
Q3
MOTOROLA'S PIN.coMPATtIlLE ROM FAMILY
PIN NAMES
HI(
AO -A12
E
00--07.
Address
Chip Enable
Data Output
Vee·
+ 5 V Power Supply
VSS'
Ground
This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however,
it is advised that normal precautions be
taken to avoid application of any voltage
higher than maximum rated voltages to
INDUSTRY STANDARD PINOUTS
this high-impedance circuit.
OS9805I7-79
2-207
•
•
MCM68A364·MCM68B364
BLOCK
DIAGRAM
AO
Al
A2
A3
A4
A5
A6
A7
A8
A9
Al0
All
A12
8
9
10
11
13
14
15
16
17
7
6
4
3
2
Address
Decode
23
DO
01
02
03
04
05
06
07
22
1918
21
E 20
Vee"" Pin 24
Vss
=
Pin 12
ABSOLUTE MAXIMUM RATINGS ISee notel
Rating
Supply Voltage
Symbol
Value
Unit
VCC
+ 7.0
-0.5 to + 7.0
o to + 70
-65 to + 150
Vdc
Input Voltage
Vin
Operating Temperature Range
TA
Storage Temperature Range
Tstg
-0.5 to
Vdc
°c
°c
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could
affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted.)
RECOMMENDED OPERATING CONDITIONS
Para.meter
Symbol
Min
Nom
Max
Unit
Supply Voltage
IVee must be applied at least 100 /JS before proper device
operation is ac.hievedl
Vee
4.5
5.0
5.5
Vdc
Input High Voltage
VIH
2.0
Vdc
VIL
-0.5
-
5.5
Input Low Voltage
0.8
Vdc
SymbQI
Min
Typ
Max
Unit
lin
-10
-
10
/JAde
Output High Voltage (IOH = -220 /JAI
VOH
2.4
-
-
Output Low Voltage (IOL = 3.2 mAl
VOL
-
-
0.4
Vdc
Output Leakage Current (Three-Statel
IE = 2.0 V. Vout = 0 V to 5.5 VI
ILO
-
10
/JAde
Supply Current - Active*
(Minimum Cycle Ratel
ICC
-
25
40
mAde
Supply Current (E =VIHI
ISB
-
7
10
mAde
RECOMMENDED OPERATING CHARACTERISTICS
Characteristic
Input Current (Vin "0 to 5.5 VI
Standby
*Current is proportional to cycle rate.
CAPACITANCE If= 1.0 MHz, T A= 25°C, periodically sampled rather than 100% testedl
Characteristic
Input Capacitance
Output Capacitance
2-208
-10
Vde
MCM68A364-MCM68B364
AC OPERATING CONDITIONS AND CHARACTERISTICS
Read Cycle
RECOMMENDED OPERATING CONDITIONS
ITA ~ 0 to 70"C VCC ~ 5 0 V ~ 10% All timing with tr ~ tf ~ 20 ns load of Figure 1)
MCM688364
MCM68A364
Symbol
Min
Min
Max
Unit
Chip Enable Low to Chip Enable Low of Next Cycle ICycle Time)
tELEL
375
-
450
-
ns
Chip Enable Low to Chip Enable High
tELEH
250
-
300
--
ns
Ch ip Enable Low to Output Valid (Access)
tELQV
-
300
ns
Chip Enable High to Output High Z (Off Time)
Chip Enable Low to Address Don', Care (Hold)
Parameter
Max
-
250
tEHQZ
-
60
-
75
r,s
tELAX
60
-
75
ns
ns
Address Valid to Chip Enable Low (Address Setup)
tAVEL
0
-
0
-
Chip Enable Precharge Time
tEHEL
125
-
150
-
TIMING DIAGRAM
tELEL
VIHCHIP ENABLE, E
VILtELEH
ADDRESS, A
tELQV
VOHDATA OUTPUT, Q
High Z
VOL-
~
VALID
High Z
FIGURE 1 - AC TEST LOAD
WAVEFORMS
5,OV
..- ,
Test Point
100 pF* ;;
0;;
RL
~
...
"
Output
MUST BE
VALID
WILL BE
VALID
~
CHANGE
FROM HTO L
WILL CHANGE.
FROM H TO L
-.!llZZT
CHANGE
WILL CHANGE
FADM L TO H
FROM L TO H
DON'T CARE
ANY CHANGE
CHANGING
PERMITTED
UNKNOWN
1.2 k
MMD6150
or Equiv
10,9 k
---'
Input
Waveform
Symbol
MMD7000
or Equiv
~
STATE
'::'
~
*Includes Jig Capacitance
2-209
HIGH
IMPEDANCE
ns
•
MCM68A364-MCM68B364
CUSTOM PROGRAMMING
TIMING PARAMETER ABBREVIATIONS
I II
t X X X X
signal name from ."","",0. .,"' "d."o", --'
transition direction for first signal
signal name to which interval .is defined
transition direction for second signal
By the programming of a single photomask for the
MCM6BA364/MCM6BB364, the customer may specify the
contents of the memory.
Information for custom memory content may be sent to
Motorola in one of two forms (shown in order of preference):
1. Magnetic Tape - 9 Track, 800 bpi, odd parity written
in EBCDIC character code. Motorola's R.O.M.S. format.
2. EPROMs one 64K (MCM68764). two 32K
(MCM2532), four 16K (MCM2716 or TMS2716), or
eight 8K (MCM27081.
3. IBM Punch Cards
A. Hexadecimal Format
B. INTEL Hexadecimal Format
The transition definitions used in this data sheet are:
H = transition to high
L = transition to low
V = transition to valid
X = transition to invalid or don't care
Z = transition to off (high iinpedance)
IBM PUNCH CARDS, HEXADECIMAL
FORMAT
TIMING LIMITS
The hexadecimal equivalent (from Figure 2) may be
placed on 80 column IBM punch cards as follows:
~ Column
1
12
Byte "0" Hexadecimal equivalent for outputs Q7 through 04 (07= M.S.B.)
Byte "0" Hexadecimal equivalent for out2
13
puis 03 through 00 (03= M.S.B.)
3
14--75 Alternate steps 1 and 2 for consecutive
bytes
77-79 Card number (starting 0011
4
Total number of cards must equal 256
5
The table of timing values shows either a minimum or
a maximum limit for each parameter. Input requirements
are specified from the external system point of view.
Thus, address setup time is shown as a minirpum since the
system must supply at least that much time (even though
most devices do not require it). On the other hand,
responses from the memory are specified from the device
point of view. Thus, the access time is shown as a maximum since the device never provides data later than
that time.
FIGURE 2 - BINARY TO HEXAOECIMAL CONVERSION
Binary
Hexadecimal
Character
Data
0
a
a
a
a
a
a
a
a
a
a
a
a
1
1
a
a
2
0
1
1
3
1
a
a
a
4
1
1
5
1
1
a
6
1
0
1
1
1
7
1
a
a
a
a
a
a
a
8
1
9
1
a
A
1
1
B
c
1
1
1
1
1
1
a
a
a
1
1
D
1
1
1
a
E
1
1
1
1
F
2-210
MCM68A364-MCM68B364
M6800 MICROCOMPUTER FAMILY
BLOCK DIAGRAM
.-....,1----1
READ ONLY MEMORY
BLOCK DIAGRAM
MCM68A364
MCM688364
Read Only
Memory
Memory
Matrix
Random
Data 8us
(8192 X 8)
Access
Memory
Interface
Adapter
Interface
Adapter
Address Data
Bus
Bus
Memory Address
and Control
PRE-PROGRAMMED MCM68A364P3/L3
The -3 standard ROM pattern contains log (base 10)
and antilog (base 10) lookup tables for the 64K ROM.
Locations 0000 through 3599 contain log base 10
values. The arguments for the log table range from 1.00
through 9.99 incrementing in steps of 1/100. Each log
value 's '''~i bsented by ,m eight-digit decimal number
with decimal pc ',,[ assumed to be to the left olthe mostsigniiicant digit.
A~!ilog (base 10) are stored in locations 4096 through
80'15. Tht. , .uments range from .000 through .999
incrementing ,n steps of 1/1000. Each antilog value is
represented by an eight-digit decimal number with
decimal point assumed to be to the right of the mostsignificant digit.
Locations 3600 through 4095 and 8096 through
8191 are zero filled.
All values are represented in absolute decimal format
with eight digit precision. They are stored in 8CD format
with the two most significant digits in the lower byte and
the remaining six digits in the three consecutive
locations.
Example:
1091O (1.01) = .00432137 decimal
Address
4
5
6
7
Contents
0000
0100
0010
0011
2-111
0000
0011
0001
alII
®
MOTOROLA
MCM68365
Advance InforIDation
MOS
II
B192x8-BIT READ ONLY MEMORY
IN-CHANNEL, SILICON-GATEI
The MCM68365 is a mask-programmable byte-organized memory
designed for use in bus-organized systems. It is fabricated with
N-channel silicon-gate technology. For ease of use, the device operates
from a single power supply, has compatibility with TTL, and needs no
clocks or refreshing because of static operation.
The memory is compatible with the M6800 Microcomputer Family,
providing read only storage in byte increments. The active level of the
Chip Enable input and the memory content is defined by the user. The
Chip Enable input deselects the output and puts the chip in a powerdown mode.
• Fully Static Operation
• Automatic Power Down
• Low Power Dissipation - 225 mW Active (Typical)
30 mW Standby (Typical)
•
•
•
•
B192x B-BIT
READ ONLY MEMORY
~~~
24
'
;
Single ± 10% 5-Volt Power Supply
High Output Drive Capability (2 TTL Loadsl
Three-State Data Output for OR-Ties
Mask Programmable Chip Enable
24
C SUFFIX
P SUFFIX
FRIT-SEAL
CERAMIC PACKAGE
CASE 623
PLASTIC PACKAGE
CASE 709
• TTL Compatible
• Maximum Access Time - 250 ns - MCM68365-25
350 ns - MCM68365-35
PIN ASSIGNMENT
• Pin Compatible with 8K - MCM68A308, 16K - MCM68A316E,
and 32K - MCM68A332 Mask-Programmable ROMs
A7
VCC
A6
MOTOROLA'S PIN·COMPATIBLE EPROM FAMILY
23
A4
AS
22
A9
21
A12
E
A3
14K
14K
U
1"
A2
A10
Al
All
AO
07
00
06
01 10
05
02 11
04
VSS 12
03
MOTOROLA'S PIN·COMPATIBLE ROM FAMILY
12K
PIN NAMES
AO-A12 . . . Address
E ..... Chip Enable
00-07
.. Data Output
V CC ...... + 5 V Power Supply
VSS ...... Ground
This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is ad·
vised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this high im·
pedance circuit.
INDUSTRY STANDARD PINOUTS
ADI844/9-80
2-212
MCM68365
BLOCK DIAGRAM
AD
Al
A2
A3
A4
A5
A6
A7
A8
A9
Al0
A11
A12
'E
10
11
13
6
4
3
2-
Address
Decode
Memory
Matrix
(8192 X 8)
23
22
19
18
21
20
VCC~
DO
Dl
D2
D3
D4
D5
D6
D7
•
Pin 24
VSS~PIn12
• Active level defined by the user.
ABSOLUTE MAXIMUM RATINGS ISee NOlel
Rating
Symbol
Supply Voltage
Input Voltage
Operating Temperature Range
Storage Temperature Range
Note:
Value
0.3 to + 7.0
0.3 to + 7.0
o to + 70
65 to + 150
VCC
Vin
TA
Tstg
Unit
V
V
'c
'c
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted)
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
tV CC must be applied at least 100 P.s before proper device operation is achieved)
Input High Voltage
Input Low Voltage
Symbol
Min
Nom
Max
VCC
4.5
5.0
5.5
V
V
VIL
2.0
0.3
-
5.5
0.8
V
Symbol
Min
Typ
lin
VOH
VOL
IlO
ICC
ISB
-
-
Max
10
Un~
RECOMMENDED OPERATING CHARACTERISTICS
Characteristic
Input Current IVin ~ 0 to 5.5 VI
Output High Voltage 1I0H
205 ~AI
Output low Voltage IIOl - 3.2 mAl
Qutput leakage Current IThree-StateIIE-2.0 V, Vout -O.4 V to 2.4 VI
Supply Current - Active IV CC - 5.5 V, T A - O°CI
Supply Current
Standby IVCC-5.5 V, TA-O°C, E-VIHI
CAPACITANCE
If~
1.0 MHz, TA~25°C, periodically sampled rather than 100% testedl
Characteristic
Input Capacitance
utput Capacitance
2-213
2.4
-
-
45
6.0
0.4
10
80
15
Unk
~A
V
V
~A
mA
mA
•
MCM68365
AC OPERATING CONDITIONS AND CHARACTERISTICS
Read Cycle
RECOMMENDED OPERATING CONDITIONS
IT A=O to 70·C, VcC=5.0 v ± 10%. All timing with tr=tf= 10 ns, load of Figure 1)
Parameter
Symbol
MCM68365-25
Min
Max
Address Valid to Address Don't Care ICycle Time when Chip Enable is held Active)
Chip Enable Low to Chip Enable High
tAVAX
tFLEH
250
250
-
350
350
-
Address Valid to Output Valid IAccess)
Chip Enable Low to Output Valid IAccess)
Address Valid to Output Invalid
{;nip Enable Low to Output Invalid
Chip Enable High to Output High-Z
(;nip Selection to Power Up Time
Chip Deselection to Power Down Time
Address Valid to Chip Enable Low IAddress Setup I
tAVOV
tELOV
tAVOX
tELOX
tEHOZ
tpu
tpD
-
250
250
-
350
350
10
10
-
10
10
a
a
70
80
-
a
a
-
-
100
120
a
-
-
a
-
READ CYCLE TIMING 1
IE Held Low)
Address
o lData
tAVEL
-----1'~~
MCM68366-36
Min
Max
-
-
-
tAVAX--------~~t
~=======:~:~
tAvoV----l.~1
tAVOX~
alid
Data Valid
VOL
Outl-====p~;·~~~~v~~==~~~~t=======~!3~L==:==VOH
_
READ CYCLE TIMING 2
revmus Data
---l
~tAVEL
Address XYYYYY.M.
VIH
Address Valid
VIL
'1
tELEH
:;;~
tELOV
!+--tELOX
o (Qata Outl
Vee
Supply
:~~
~
-
tEHOZr-
HI-Z~"~=lC.l<:.lOolP-_ _ _ _..;D:;;a:;;t::.a.:.V::..I;;:ld=-_..:.._~}-Hi-Z.
________ ~~ t=___________-____
l
VOH
VOL
tP_D_t
Current
TIMING PARAMETER ABBREVIATIONS
TIMING LIMITS
t X X X X
'gM' "'~transition
from w,"' '""~, • d.'"'" ~
direction for first signal
III
Signal name to which interval is defined
. transition direction for second signal
The transition definitions used in this data sheet are:
H = transition to high
L=transition to low
V = transition to valid
X = transition to invalid or don't care
Z= transition to off (high impedance)
The table of timing values shows either a minimum or a
maximum limit for each parameter. Input requirements are
specified from the external system point of view. Thus, address setup time is shown as a minimum since the system
must supply at least that much. time (even though most
devices do not require it). On the other hand,.responses from
the memory are specified from the device point of view.
Thus, the access time is shown as a maximum since the
device never provides data later than that time.
2-214
MCM68365
READ ONLY MEMORY BLOCK DIAGRAM
MCM68365
Read Only
Memory
Memory
Matrix
Data Bus
(S192xS)
Memory Address
and Control
Address Data
Bus
Bus
PRE-PROGRAMMED MCM68366P35-3!C3&-3.
MCM68366P25-3! C25-3
The - 3 standard ROM pattern contains log Ibase 10) and
antilog Ibase 10) lookup tables for the 64K ROM.
Locations 0000 through 3599 contain log base 10 values.
The arguments for the log table range from 1.00 through
9.99 incrementing in steps of 1/100. Each log value is
represented by an eight-digit decimal number with decimal
point assumed to be to the left of the most-significant digit.
Antilog Ibase 10) are stored in locations 4096 through
8095. The arguments range from .000 through .999 incrementing in steps of 111000. Each antilog value is
represented by an eight-digit decimal number with decimal
point assumed to be to the right of the most-significant digit.
Locations 3600 through 4095 and 8096 through 8191 are
zero filled.
All values are represented in absolute decimal format with
eight digit precision. They are stored in BCD format with the
two most significant digits in the lower byte and the remaining six digits in the three consecutive locations.
Example: 1091011.01) =0.00432137 decimal
Address
4
5
6
7
2-215
Contents
0000
0000
0100
0011
0010
0001
0011
0111
•
MCM68365
CUSTOM PROGRAMMING
Information for custom memory content may be sent to
Motorola in one of two forms (shown in order of preference):
By the progralDming of a single photomask for the
MCM68365, the customer may specify the content of the
memory and the method of enabling the outputs .
Information on the general options of the MCM68365
should be submitted on an Organizational Data form such as
that shown in Figure 2.
1. Magnetic Tape
9 track,BOO bpi, odd parity written in EBCDIC character code. Motorola R.O.M.S. format,
2. EPROMs - four 16K (MCM2716, or TMS2716, or eight
8K (MCM2708), one 64K or two 32K)
FIGURE 2 - FORMAT FOR PROGRAMMING GENERAL OPTIONS
ORGANIZATIONAL DATA
MCM68365 MOS READ ONLY MEMORY
Customer:
Company ______-----------------------------Part No. ____________________________________
Part No: _ _ _ _ _ _ _ _ _ _ __
Originato' _______________________
Speci!. No:
Phone No. ____________________
Enable Options:
Active High Active Low
Chip Enable
0
2-216
Motorola Use Only:
Quote: _ _ _ _ _ _ _ _ _ _ __
D
®
MOTOROLA
MCM68366
Advance InforIllation
MOS
8192x8-BIT READ ONLY MEMORY
IN·CHANNEL, SILlCON·GATE}
The MCM68366 is a mask-programmable byte-organized memory
designed for use in bus-organized systems. It is fabricated with
N-channel silicon-gate technology. For ease of use, the device operates
from a single power supply, has compatibility with TTL and DTl, and
needs no clocks or refreshing because of static operation.
The memory is compatible with the M6800 Microcomputer Family,
providing read only storage in byte increments. The active level of the
Output Enable input and the memory content is defined by the user.
The Output Enable input deselects the output.
•
•
•
•
•
•
•
Fully Static Operation
Fast Data Valid Time for High Speed Microprocessors
low Power Dissipation - 225 mW Active ITypical)
Single ± 10% 5-Volt Power Supply
High Output Drive Capability 12 TTL loads)
Three-State Data Output for OR-Ties
Mask Programmable Output Enable
8192x8-BIT
READ ONLY MEMORY
C SUFFIX
P SUFFIX
FRIT·SEAL
CERAMIC PACKAGE
CASE 623
PLASTIC PACKAGE
CASE 709
• TTL Compatible
• Maximum Access Time - 120 ns from Output Enable
250 ns from Address - MCM68366-25
350 ns from Address - MCM683fl6-35
• Pin Compatible with 8K and 32K - Mask-Programmable ROMs
• Pin Compatible with MCM68766 64K EPROM
PIN ASSIGNMENT
Vce
A8
A9
A12
G
Al0
MOTOROLA'S PIN·COMPATIBLE EPROM FAMILY
All
UK
Q7
06
05
.
..
04
Vss
03
PIN NAMES
MOTOROLA'S PIN·COMPATIBLE ROM FAMILY
.,
02
AO-A12 ..
32K
. Address
G..... Output Enable
.. Data Output
Vee ..... +5V Power Supply
VSS ..... Ground
00-Q7
AI
AI
,.
Q5
1404
t
'"
MCMII8A318e
This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this high impedance circuit.
INDUSTRY STANDARD PINOUTS
ADI842/9·80
2-217
MCM68366
BLOCK DIAGRAM
8
AO
AI
7
A2
6
5
A3
4
A4
AS
3
A6
A7
A8 23
A9 22
Al0 19
All 18
A12 21
•
"-cr
Address
Oecode
20
9
10
11
DO
D1
02
13
14
15
03
04
D5
16
D6
17
07
Vcc=Pin 24
Vss=Pin 12
"Active level Defined by the User
ABSOLUTE MAXIMUM RATINGS (See Note 1)
Symbol
Value
Unit
Supply Voltage
VCC
-0.3 to + 7.0
Vdc
Input Voltage
Vin
~0.3
Operating Temperature Range
TA
Vdc
·C
Rating
to + 7.0
o to
+ 70
Storage Temperature Range
-66 to +150
·C
Tstg
NOTE 1. Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded. FunCllonal operation should be restncted to
RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommen;; (Vin or V out ):=>;; VOO.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDDI.
3-3
Strobe 5
eE16
CE28
R!W9
VoD '" Pin 14
VSS = Pin 7
•
•
MCM14505
ELECTRICAL CHARACTERISTICS
Characteristic
Output Voltage
Symbol
"0" Level
Voo
Vdc
VOL
VOO or 0
Vin
"1" Level
VOH
00' VOO
Vi"
Noise Immunity ~
(.N out ·• 0.8 Vdc)
(:,V out ..; 1.0 Vdc)
(!\Vout ...;: 1.5 Vdc)
VNL
(·N out';; 0.8 Vdcl
VNH
(N out " 1.0 Vdc)
(.N out" 1.5 Vdc)
Qutput Drive Current (AL Devicel
(VOH <. 2.5 Vdc)
Source
= 0.4 Vdc)
= 0.5 Vdc)
= 1.5 Vdcl
Sink
Output Drive Current (CLlCP Device)
(VOH
(VOH
(VOH
(VOH
(VOL
(VOL
(VOL
= 2.5 Vdc)
= 4.6 Vdcl
= 9.5 Vdc)
= 13_5 Vdcl
= 0.4 Vdc)
= 0.5 Vdc)
= 1.5 Vdcl
IOL
25°C
IOL
Thi h*
Ma.
Min
Typ
Ma.
Min
Max
Unit
-
-
0.05
0.05
0.05
-
Vdc
-
0.05
0.05
0.05
-
Vdc
5.0
10
15
-
0.05
0.05
0.05
-
0
0
0
5.0
10
15
4.95
9.95
14.95
-
4.95
9.95
14.95
5.0
10
15
-
4.95
9.95
14.95
5.0
10
15
1.5
3.0
4.5
1.5
3.0
4.5
2.25
4.50
6.75
-
1.4
2.9
4.4
-
5.0
10
15
1.4
2.9
4.4
-
1.5
3.0
4.5
2.25
4.50
6.75
.-
1.5
3.0
4.5
-
5.0
5.0
10
15
-1.2
-0.25
-0.62
-l.B
-1.0
-0.2
-0.5
-1.5
-1.7
-0.36
-0.9
-3.5
5.0
10
15
0.3
0.9
2.2
0.25
0.75
1.7
0.35
1.2
4.5
-
-
-
0.18
0.50
1.2
5.0
5.0
10
15
-1.0
-0.2
-0.5
-1.4
-0.8
-0.16
-0.4
-1.2
-1.7
-0.36
-0.9
-3.5
-
-0.6
-0.12
-0.3
-1.0
-
5.0
10
15
0.2
0.6
3.9
0.15
0.5
0.75
0.35
1.2
4.5
-
-
0.1
0.4
0.6
10.00001
10.1
.-
iO.OOOOl
±1.0
-
5.0
-
Vdc
-
Vdc
mAde
-
-
-
-0.7
-0.14
-0.35
-1.1
-
mAde
mAde
IOH
Source
Sink
.
IOH
(VOH " 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL
(VOL
(VOL
Tlow
Min
Input Current (AL Device)
lin
15
Input Current (CLlCP Device)
lin
15
Input Capacitance
Gin
-
-
-
±O.l
-
±
1.0
-
-
-
-
mAde
± 1.0
"Adc
-
±14
7.5
-
-
"Adc
pF
-
.uAdc
-
150
300
600
-
375
750
1500
"Adc
(Vin" 0)
Quiescent Current (AL Device)
(Per Package)
100
5.0
10
15
-
5.0
10
20
-
0.050
0.100
0.150
5.0
10
20
Quiescent Currer:Jt (CLlCP Device)
100
5.0
10
15
-
50
100
200
-
0.050
0.100
0.150
50
100
(Per Package)
Total Supply Current* ··t
(Dynamic plus Quiescent,
Per Package)
(CL -: 50 pF on all outputs, all
buffers switching)
IT
5.0
10
15
Three-State Leakage Current
(AL Device)
ITL
15
Three-State Leakage Current
ITL
15
-
200
IJAdc
'T -(1.28 "A/kHz) I + 100
IT =(2.56 "A/kHz) I + 100
'T =(3.85 .A/kHz) I + 100
.-
±O.l
-
'0.00001
±O.l
-
±3.0
"Adc
±1.0
--
'0.00001
± 1.0
-
±7.5
"Adc
(CL/CP Device)
*Tlow = -S5 0 C for AL Device. -40 0 C for CL/CP Oevice.
Thigh = +125 0 C lor AL Device. +85 0 C for CL/CP Device.
#Noise immunity specified for worst-case input combination_
tTo calculate total supply current at loads other than SO pF:
IT(CL)= 'T(50 pF) + 1 • 10-3 (CL -50) VDDf
where: IT is in JlA (per package), CL in pF. VOO in Vdc, and f in kHz is input frequency.
··The formulas given are for the typical characteristics only at 2S o C.
3-4
MCM14505
SWITCHING CHARACTERISTICS*
(CL: 50 pF T A: 25°C)
Symbol
Characteristic
Output Rise Time
tTLH: (2.43 ns/pF)
tTLH: (LOS ns/pF)
tTLH : (0.72 ns/pF)
Output Fall Time
tTHL: (2.16 ns/pF)
tTH L : (0.96 ns/pF)
tTHL: (0.69 ns/pF)
CL + 5S.5 ns
CL + 36 ns
CL + 39 ns
Min
Typ
Max
5.0
10
15
-
-
1S0
90
75
360
1S0
150
5.0
10
15
-
160
SO
65
320
160
130
----
5.0
10
15
-
455
210
130
750
400
300
5.0
10
15
500
125
95
100
50
75
-
5.0
10
15
300
120
90
-100
-40
-25
-
5.0
10
15
200
75
55
70
25
20
-
5.0
10
15
270
60
45
90
20
15
-
5.0
10
15
400
100
75
SO
25
11
-
5.0
10
15
75
25
20
15
10
5.0
-
5.0
10
15
50
15
10
0
0
0
-
5.0
10
15
0
0
0
-90
-25
-10
-
5.0
10
15
0
0
0
5.0
10
30
-
5.0
10
15
-
500
200
150
750
400
300
-
440
275
200
700
550
415
-
200
SO
60
600
200
150
ns
ns
taee(A)
tace(A) : (1.4 ns/pF) CL + 3S5 ns
taee(A) : (10.7 ns/pF) CL + 175 ns
taee(A) : (0.5 ns/pF) CL + 105 ns
Strobe Down Time
ns
tWL
._-_.
Address Setup Time
.
Address Release Time
__..
I
l
ns
ns
ns
ns
trellA)
n5
trellW)
n5
tcye(A)
tcye(W)
5.0
10
15
-
n.
n5
tdis
(10% Output Change into 1.0 kS1 Load)
5.0
10
15
The formula IS for the typIcal charactenstlcs only.
3-5
/
-
th(D)
;
Output Disable Delay
-
trellA)
1
Write Cycle Time
ns
tsu(W)
I
Read Release Time
Read Cycle Time
ns
tsu(A)
Data Hold Time
Write Release Time
ns
tsu(D)
Read Setup Time
Write Setup Time
-
tsu
Data Setup Time
Unit
ns
tTHL
CL + 52 ns
CL + 32 ns
CL + 33 ns
Propagation Delay Time
Read Access Time
--:-:-:--:: ...
VOO
tTLH
MCM14505
FIGURE 1 - READ CYCLE TIMING DIAGRAM
Address
Strobe
tWHmin
= 'tcyc(R)
max tWLmin
The read/write input can be maintained at a logical "'"
(high voltage) during a read cycle.
j-----k:----::--:----:----- VOH
Data Output - - - - "
FIGURE 2 - WRITE CYCLE TIMING DIAGRAM
•
Address
tWHmin
= tcyc(W)
max -tWL min
Strobe
The read/write input can be maintained at a logic "0"
(low voltage) during a write cycle. If the read/write
input is maintained at a logic "0" ....... hile the strobe is
8 logic ",", then the output data will be disabled (high
ReadlWrite - - - - ,
Data
In _ _ _ _ _ _
's_:o_':e~h-(D-)-------
FIGURE 3 - MAXIMUM STROBE PULSE WIDTH
vorsus TEMPERATURE
impedance) during the write cycle.
FIGURE 4 - TYPICAL READ ACCESS TIME
versus LOAD CAPACITANCE
100
800
TA=25 0 C
Voo
=:
~
5.0 Vdc
600
";::
-
~~ 400
10 Vdc
"
~
15Vdc
0
1
o
o
0.01
-60
-20
20
60
100
140
TA. AM81ENT TEMPERATURE IOC)
-
I--
f.-- I--
VOO = 5.0 Vdc
10Vdc
r--
15 Vdc
20
40
60
Cl, LOAD CAPACITANCE (pF)
3-6
_r-"
80
100
MCM14505
FIGURE 5 - TYPICAL OUTPUT SOURCE
CAPABILITY versus TEMPERATURE
FIGURE 6 - TYPICAL OUTPUT SINK
CAPABILITY versus TEMPERATURE
V OO Vlnput
lDS
0---
--
----I I-
300 "'
10 kHI
VOO
Notes
1. Cycle R/W to ground and then to VOO
prior to measurement to insure turn
, -_ _ _ _ _--;_ _ _,
on of the device under test.
2. For the P-channel characteristics,
VOS'-' VOH -- V OD -
AO
A1
D out
A2
A3
AO
3. For the N-channel characteristics,
VOS is measured directly.
A1
E
A2
A3
4. For the drain current, I D '" 100 Amp
A4
A4
A5
A5
~-f-<>--I Din
~-f-<>--I C E 1
'--f-<>--I CE2
Vi n
r-<>-j----t----<;
Din
~-f-<>--- CE 1
'---t--<>-- CE2
R/W
0----1-0---1 Str abe
RIW
0-----1'-0--- St r abe
V 1n
External
Power
'---------4
Supply
0
[La
E
8. 0
"
G
/ 1//
60
II /,
~
"
4. 0
~
~
-B.O
-6.0
-4.0
/V~
olL ~
liM
o
-1.0
VOS.ORAIN VOLTAGE (Vdc)
,
15Vdc
V-
a
10
./
b
(a)
TA - -55°C
(b}TA - +25'C-
~t5.0 Vdc
C
2.0
Vdc
c
V
4.0
(ellA
I
6.0
Vos. ORAIN VOLTAGE (Vdc)
3-7
Power
Supply
/
o~
-10 '-------.J._--:'-::-_.l.-/L.f:V,---'----;V":-a---'-_-:-:-_'-----c
-10
2.
l,ij'
/
Vi
~
External
r- VI
I / V Iv
;;'
e-
~ VOoo
L
Vss
B.O
=:
+125 0 C
I
10
•
MCM14505
FIGURE 7 - FUNCTIONAL CIRCUIT DIAGRAM
Data 1n
o-+--+----~_
AO
.
;g
"~
.c
A1
~
0
~
c
§
A2
"~
~
A3
"'<:
II:
·i
"0
u
0
0
<:
R/W
Strobe
CE 1
CE 2
Basic Memory Cell
n
~rD.t.out
L _________
L._-_-_-_-~-O-~-t-_-_-_---1"J+-
3-8
A4
.
~.~',..".'
A5
MCM14505
OPERATING CHARACTERISTICS
row is in the low state, and the unselected 15 rows retain their
logic "1" level due to the row capacitance that exists when the row
decoder inhibit gates are disabled. This capacitive storage mechanism requires a maximum strobe width (see Figure 3) equal to the
junction reverse bias RC time constant. When the strobe is returned
to a logic "0" the rows are forced to VOO by the row decoder
inhibit gates (pullup devices!. Similarly the column read/write
inhibit gates (pulldown devices) force the column lines to a logic
"0" state.
Two column lines are associated with each memory cell in order
to write into the cell. The write selection drivers are enabled when
the A/W line is a logic "0" and the strobe line is a logic "1". The
input data is written into the column selected by the column
decoder. For instance, if a "1" is to be written in the memory cell
associated with row 1 and column 1, then row 1 would be enabled
(logic "0") while column 1b is forced high and column 1a is forced
low by the write selection drivers. If a logic "0" is to be written
into the cell, then column 1a is forced high and 1b is forced low.
The data that is retained in the memory cell is the data that was
present on the data input pin at the moment the strobe goes low
when RIW is low, or when R/W goes high when the strobe is high.
In considering the operation of the MCM 14505 CMOS memory.
refer to the functional circuit diagram of Figure 7 and timing
diagrams shown in Figures 1 and 2. The basic memory cell is a
cross-coupled flip-flop consisting of two inverter gates and two
P-chennel devices for read/write control. The push·pull cell provides
high speed as well 85 low power.
During a read cycle, when the strobe line is high the write
selection drivers are disabled and the data from the selected row is
available on columns 1b, 2b, 3b, and 4b. The A4 and A5 address
bits are decoded to select output data from one of the four columns.
The output data is available on the data output pin only when the
strobe and read/write lines are high simultaneously and after the
read access time, taec(A). has occurred (see Figure 1). Note that
the output is initially disabled and always goes to the logic "0" state
(low voltage) before data is valid. The output is in the highM
impedance state (disabled) when the strobe line or the RIW line is
in the low state. The memory is strobed for reading or writing only
when the strobe, CE1, and CE2 are high simultaneously. The RIW
line can be a dc voltage during a read or write cycle and need not
be pulsed, as shown in the timing diagrams. For this case the R/W
line should be a logic "1" (high) for reading and a logic "0" for
writing.
When the strobe line is high, the column read/write inhibit
gates and the row decoder inhibit gates are disabled, the selected
APPLICATIONS INFORMATION
Figure 8 showsa 256-word by "-bit static RAM memory system
The outputs of four MCM14505 devices are tied together to form
256 words by 1 bit. Additional bits are attained by paralleling the
inputs in groups of four. Memories of larger words can be attained
by decoding the most significant bits of the address and ANDing
them with the strobe input.
Fan-in and fan-out of the memory is limited only by speed
requirements. The extremely low input and output leakage current
(100 nA maximum) keep the output voltage levels from changing
significantly as more outputs are tied together. With the output
levels independent of fan-out, most of the power supply range is
available as logic swing, regardless of the number of units wired
together. As a result, high noise immunity is maintained under
all conditions.
Power dissipation is 0.1 ~W per bit at a 1.0Mk Hz rate for a
volt power supply, while the static power dissipation is 2.0 nW
5.0M
per bit. This low power allows nonMvolatile information storage
when the memory is powered by a small standby battery,
Figure 9 shows an optional standby power supply circuit for
making a CMOS memory "nonMvolatile". When the usual power
fails, a battery is used to sustain operation or maintain stored
information. While normal power supply voltage is present, the
battery is trickle-charged through a resistor which sets the charging
rate. VB is the sustaining voltage, and V+ is the ordinary voltage
from a power supply. VOO connects to the power pin on the
memory.
Low-leakage diodes are recommended to conserve
battery power.
The memory system shown in Figure 8 can be interfaced
directly with the other devices in the McMOS family. No external
components are required.
At the inputs to the CMOS memory, TTL devices can interface
directly if an open-collector logic gate such as the MC7407 is used
as shown in Figure 10. Driver circuits are not required since the
input capacitance is low (4.0 to 6.0 pFI. The address, data, and
read/write inputs do not need to be fast since they can be changed
for the duration when the strobe pulse is low, tSTL (see Figures 1
and 2). For high-speed operation, a push-pull driver should be used
if more than five strobe inputs must be driven at one time. One
circuit of the type shown in Figure 10 can be used for every ten
strobe inputs.
Figures 11, 12, and 13 show methods of interfacing the
memory output to TT L logic at various memory voltages. If a
VOO of 5.0 volts is used for slow-speed, lowMpower applications,
one transistor and one resistor must be used (Figure 11). The
MCM14505AL will drive one 10wMpower TTL gate directly.
If a VOO of 10 volts is used, the output of the memory device
can fan out to two low-power TTL gates (Figure 12a) or to a
discrete transistor (Figure 12b). The discrete transistor circuit
provides higher speed and/or high fan-out. A pulldown resistor
at the base of the transistor is not needed for fast turn-off because
of the push-pull output of the memory. Turn-on time of the
transistor is much faster in Figure 12b since the voltage rise is only
0.75 volt. The low output capacitance of the MCM14505 means
that several outputs can be wire-O Red without significantly degrading performance. The read access time is increased by only
20 ns typically for 16 outputs tied together when Figure 12b
is used.
Five 10wMpower TT L gates can be driven from the memory
output if a VOO of 15 volts is used (Figure 13a). Figure 13b
shows the interface if a discrete transistor is used. The 1.0 kilohm
resistor in the base is required to insure that not more than 10 rnA
flows through the output as listed in the maximum ratings. If a
2.0 kilohm collector resistor is used (fan-out = 3), the turn-on
time of the transistor is only slightly faster than in the circuit
shown in Figure 12b due to the lower output impedance when
VOO = 15 volts. The voltage at the memory data output has to
rise to only 1.3 volts to insuredriving a f8n-out of three TTL devices.
If a 510-ohm collector resistor is used, 20 TTL loads may be
driven. The read access time is increased about 20 ns when four
memory outputs are tied together since the output voltage must
rise to 3.7 volts before the transistor can sink the full 10 L for a
fan-out of 20 TT L devices. Almost any NPN transistor with a
minimum beta of 15 can be used for the interlace shown in
Figures 11, 12 and 13.
The high source current from the push-pull output stage of the
MCM14505 makes for a simpler interlace circuit since a low source
current memory requires a differential comparator to achieve highM
speed operation.
3-9
II
•
MCM14505
FIGURE 8 - CMOS 256-WORD BY n-BIT STATIC
READIWRITE MEMORY
1
2
A
Address
Lines
B
C
0
E
F
3
4
11
12
6
8
_5
G
H
MCM14505
64-Bit
10
t--
Ram
0--9
13
-
,
r,L>
G
H=>
;:;
1
2
3
4
11
12
6
8
-=
f0-
r-
Data In
MCM14505
1064-Bit
Ram
5
9
13
r--oBo Out
1
2
3
4
11
12
6
8
Dvnamic
StrOb:..JL
MCM14505
64-Bit
10
c---<
10
t--
Ram
5
>---- r- 9
~ 13
1
2
3
4
11
12
6
8
MCM14505
64-Bit
Ram
5
9
Aead/Write
~
I I I I II II "
1111111111
I I I I 11111 I
I II 1111 I II
13
I I
I I
I I
I I
Expand Vertically For n-Bits
Circuit diagrams utilizing Motorola products are included 85 a means
of illustrating tvpical semiconductor applications; consequently.
complete information suffic.ient for construction purposes is not
is believed to be entirely reliable. However. no responsibility is
assumed for inaccuracies. Furthermore. such information does not
convey to the purchaser of the semiconductor devices described any
necessarily given.
license under the patent rights of Motorola Inc. or others.
The information has been carefully checked and
3-10
MCM14505
FIGURE 9 - STAND BY
BATTERY CIRCUIT
FIGURE 11 - CMOS·TO·TTL INTERFACE
FOR VOO = 5.0 V
FIGURE 10 - TTL TO CMOS INTERFACE
V+
(
Voo
= 5.0
Vee
V
2.0 k
.---<.....- - - - 0 VOO
470
TO TTL
R
IF.O.
X>--e Package
Extended Operating
Temperature Range
Limited Operating
5 Vdc
Temperature Range
Noise Immunity = 45% of VDD typical
•
3-state Output Capability for Memory Expansion
•
Output Data Latch Eliminates Need for Storage Buffer
•
Access Time = 700 ns typical @ VDD = 10 Vdc
PIN ASSIGNMENT
•
Fully Decoded and Buffered
16
•
Supply Voltage Range = 3.0 Vdc to 18 Vdc
15
•
Capable of Driving Two Low-power TTL Loads, One Low-power
Schottky TTL Load or Two HTL Loads Over the Rated Temperature Range
14
4
13
6
12
6
11
10
8
MAXIMUM RATINGS (Voltages referenced to Vssl
Symbol
Rating
DC Supply Voltage
VOO
Value
-0.5 to +18
Unit
Vdc
Vdc
Input Voltage, All Inputs
Vin
-0.5 to VOO + 0.5
DC Current Drain per Pin
I
10
-55 to +125
-40 to +85
mAde
TA
T stg
-65 to +150
°c
Operating Temperature Range - AL Device
CLlCP Device
Storage Temperature Range
°c
9
This device contains circuitry to protect
the inputs against damage due to high static
voltages or electric fields; however, it is
advised that normal precautions be taken
to avoid application of any voltage higher
than maximum rated voltages to this high
impedance circuit. For proper operation it
is recommended that Vin and Vout be
constrained to the range VSS ,.;;; (Vin or
Voutl.; VOD'
Unused inputs must alwavs be tied to an
appropriate logic voltage level (e.g., either
Vssor VDOI.
3-12
MCM14537
ELECTRICAL CHARACTERISTICS
voo
Characteristic
Output Voltage
Vin VOD or
Y,n
Vdc
"0" Level
VOL
5.0
10
15
"1" Level
VOH
5.0
10
15
4.95
9.95
14.95
5.0
10
15
1.5
3.0
4.5
5.0
10
15
a
a or VDD
Noise Immunity p
( V out ', 0.8 Vdcl
'-0
VNH
V aut "; 1.0 Vdc)
..y Out '- 1.5 Vdcl
OutPllt Drive Current (AL Device)
(V DH " 2.5 Vdcl
Source
(VOH " 4.6 Vdcl
(VOH " 9.5 Vdcl
(VOH" 13.5 Vdcl
Sink
Output Drive Current (CL/CP Device)
Source
(VOH " 2.5 Vdcl
IVOH " 4.6 Vdcl
(VOH "9.5 Vdcl
(VOH" 13.5 Vdcl
(VOL" 0.4 Vdcl
(VOL" 0.5 Vdcl
(VOL" 1.5 Vdcl
Ma.
25°C
Min
0.05
0.05
0.05
4.95
9.95
14.95
Thi h*
TVp
Ma.
a
a
a
0.05
0.05
0.05
Min
5.0
10
15
4.95
9.95
14.95
1.5
3.0
4.5
2.25
4.50
6.75
1.4
2.9
4.4
1.4
2.9
4.4
1.5
3.0
4.5
2.25
4.50
6.75
1.5
3.0
4.5
5.0
5.0
10
15
-1.2
-0.25
-0.62
-1.8
.. 1.0
-0.2
-0.5
-1.5
-1.7
-0.36
-0.9
-3.5
-0.7
-0.14
-0.35
-1.1
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
5.0
5.0
10
15
-1.0
-0.2
-0.5
-1.4
-0.8
-0.16
-0.4
-1.2
-1.7
-0.36
-0.9
-3.5
-0.6
-0.12
-0.3
-1.0
5.0
10
15
0.52
1.3
3.6
0.44
0.88
2.25
8.8
0.36
0.9
2.4
Ma.
Unit
0.05
0.05
0.05
Vdc
VdC)
Vdc
1.5 Vdcl
.y out .. 0.8 Vdcl
(VOL" 0.4 Vdcl
(VOL" 0.5 Vdcl
(VOL" 1.5 Vdcl
.
VNL
V out "" 1.0 Vdc)
-V out
Tlow
Min
Symbol
Sink
Vdc
mAde
IOH
IOl
mAde
mAde
IOH
IOl
1.1
3.0
mAde
Inpul Current (AL Devicel
'in
15
'0.1
'0.00001
!O.l
± 1.0
,uAdc
Input Current (CLlCP Device)
lin
15
f1.0
±0.00001
±l.a
±14
J,lAdc
5.0
7.5
Input Capacitance
(Vin'" 01
QUiescent Current (AL Device)
(Per Package)
Gin
lOa
lOa
pF
5.0
10
15
0.5
1.0
1.5
200
400
1800
3600
7200
IJAdc
200
400
IDD
5.0
10
15
100
200
400
0.5
1.0
1.5
100
200
400
1800
3600
7200
pAdc
IT
5.0
10
15
Three-State Leakage Current
(AL Device)
ITl
15
± 0.1
-0.00001
± 0.1
.3.0
~Adc
Three-State Leakage Current
ITl
15
±1.0
-0.00001
± 1.0
±7.5
~Adc
QUiescent Current (CLlCP Device)
(Per Package)
Total Supply Current··t
.IDD
(DVnamic plus Quiescent,
Per Package)
tel - 50 pF on all outputs. all
buffers switching)
J;
IT - (1.46 "A/kHzl I + IDD
IT - (2.91 pA/kHzl I + IDD
IT" (4.37 pA/kHzl f + IDD
(CLlCP Devicel
-Tlow ,. -SSoC for AL Device. -40°C for CLlCP Device.
Thigh = +12SoC for AL Device. +8So C for CLlCP Device.
:;:Noise immunity specified for worst-case input combination.
NOise Margin for both "1" and "0" level'" 1.0 Vdc min@ VDO
~ 5.0 Vdc
2.0 Vdc min@ VDD " 10 Vdc
2.5 Vdc min @ VDD " 15 Vdc
tTo calculate total supply current at loads other than SO pF:
IT(Cl) " IT(50 pFI + 1 • 10-3 (Cl -501 VDDI
where: IT is in JJA (per package). CL in pF. VOO in Vdc. and f in kHz is input frequency.
--The formulas given are for the typical characteristics only at 2SoC.
3-13
.uAdc
•
•
MCM14537
SWITCHING CHARACTERISTICS·
ICL
= 50 pF
TA
= 250 C)
Characteristic
Figure
3
Output Rise Time
tTLH = 13.0 ns/pF) CL + 30 ns
tTLH = 11.5 ns/pF) CL + 15 ns
tTLH = (1.1 ns/pF) CL + 10 ns
Output Fall Time
tTHL = (1.5 ns/pF) CL + 25 ns
tTHL = (0.75 ns/pF) CL + 12.5 ns
tTH L = (0.55 ns/pF) CL + 9.5 ns
Read Access Time from ST or CE2
taee = (1.4 ns/pF) CL + 2480 ns
tace = (0.7 ns/pF) CL + 690 ns
tace = (0.5 ns/pF) CL + 393 ns
Output Enable Delay from CEI or CE2
3
4,5
5,6
Setup Time from An to ST or CE2
4,5,6,7
Hold Time from An to ST or CE2
4,5,6,7
..
..
Data Hold Time
---_._-----
7
Data Setup Time
7
Write Enable Hold Time
7
Write Enable Setup Time
7
Write Enable to Dout Disable"'·
4
Strobe or CE2 Pulse Width When Reading
4,5,6
-.~-----
Strobe, eEl or CE2 Pulse Width When Writing
Write Recovery Time
tw = 11.4 ns/pF) CL + 219 ns
tw = (0.7 ns/pF) CL + 70 ns
tw = (0.5 ns/pF) CL +47.5 ns
~; or CE2 to Dout Disable Oelay·*
,,--- .-.
7
4
Symbol
Typ
Max
5.0
10
15
-
180
90
65
360
180
130
5.0
10
15
-
100
50
40
200
100
80
-
-
ns
-
ns
5.0
400
2500
6000
10
150
700
2000
15
115
400
1500
taco(CE n )
5.0
70
300
900
10
25
100
300
15
20
70
225
5.0
1800
600
tsu(A)
10
600
200
15
450
140
5.0
600
200
th(A)
10
240
80
15
180
55
1--;-- - - - - - - _ ..
5.0
1400
480
th(D)
10
500
160
15
375
110
5.0
3600
1200
tsulD)
10
1800
600
15
1350
420
5.0
150
50
th(WE)
10
60
20
15
45
15
5.0
720
240
tsulWE)
10
240
80
15
180
55
5.0
720
240
tWE
10
240
80
15
180
55
5.0
1350
450
tWL(R)
10
450
150
15
340
100
5.0
2400
1200
twLIW)
10
1260
600
15
945
420
-
r---:-'-"-
4,5
tsu(R)
Read Hold Time
4,5
'hlR)
Read Cycle' Time
4,5
teye(R)
Write Cycle Time
7
'eye(W)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tR(W)
Read Setup Time
Unit
ns
tseelR)
tCEn
3-14
Min
tTHL
6
The formula given is for the tvpical characteristics only.
**10% output change into a 1.0 knload.
VDD
tTLH
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
70
25
20
70
25
20
0
0
0
540
240
180
-
240
80
55
300
100
70
·100
·40
-30
180
60
45
2500
700
500
1400
700
500
720
240
180
900
300
225
-
ns
ns
ns
-
6000
2100
1575
4800
2100
1575
ns
ns
MCM14537
FIGURE 1 - TYPICAL OUTPUT SOURCE AND SINK CURRENT CHARACTERISTICS TEST CIRCUIT
--'IV DO
AO
Al
A2
A3
A4
r
Pul~
Generator
A5
Input
Dout
A6
A7
(Single Pulse)
V out
$
ST
WE
v 00
CEl
01
Djn
?
02
Djn
VGS
VOS
External
Power
Supply
CE2
SWl
v ss
WE
I
Output Source
Characteristics
Characteristics
Pulse Once
Pulse Once
Output Sink
SWl in Position 1 SWl in Position 2
-VOD
VOO
Vout-VOD
V out
I
VSS
~
FIGURE 2 - POWER DISSIPATION TEST CIRCUIT AND WAVEFORMS
?VOO
$
+
500 J.1.F
I
Pulse
Gen~rator
II
fl
-
Iceco
0.01
9
AO
~F
mic
(~
Pulse
Generator
Al
\'------
1
A2
Pulse
A3
Generator
2
A4
0
A5
l
Pulse
Gen~ator
II
A6
A7
12
-'1
utput (Oout) - - - - - - " " " " ' \ ' -_ _ _ _ _ _
D out
ST
1"
WE
CEl
CE2
D jn
£VSS
~
FIGURE 3 - AC TEST CIRCUIT
9
Voo
AO
Al
A2
A3
Pulse
Generator
A4
1
A5
D out
A6
A7
P.G.2
P.G.3
I
t"
ST
P.G.4
WE
CEl
P.G.5
CE2
P.G.6
Din
i
3-15
VSS
II
MCM14537
FIGURE 4 - READ CYCLE WAVEFORMS UTILIZING STROBE-tO-ACCESS MEMORY
Address
Inputs
(An)
:::::::::r::--------------------t-.-u-(A-)--------------~~r50--%-t-h--(-A~)~~~~~~~~~~~:::
~----------------~--------------Voo
50%
'--------- Vss
/4-------- tWL( R) -------I
~-------------
Write Enable
(WE)
VOO
'------J------------------Vss
.,)<--::9-::0:::%,------- V OH
Data Output
50%
(Dout )
10%
"''---------- VOL
•
WE is
1
High impedance output state occurs when
"0" (low level).
2
The output momentarily displays data from the previous state.
maintained as a logical
3
For read operation, WE may be maintained at a logical "1" (high level)
during the complete cycle.
4
eEl and CE2 are maintained at a logical "0" state (low level).
5
All input rise and fall times are 20 n$.
FIGURE 5 - READ CYCLE WAVEFORMS UTILIZING CE2 FOR ACCESS MEMORY
Address
Inputs
(An)
~~----------ts-U(-A)---------------------th-(A-'~~O%---------------
tWL(A1)
Voo
VSS
VOO
Chip Enable 2
(CE;;)
VSS
,I"" ~
~%-----------
Write Enable
(WE)
90%
Data Output
(D out )
VOO
VSS
VOH
VOL
NOTES:
1
High Impedance output state occurs when eEl or CE2 is maintained
in the logical " ' " state (high level).
2
4
The output momentarily displays data from the previous state.
For read operation, WE may be maintained at a logical "'" (high level)
during the complete cvcle.
All input rise and fa" times are 20 n5.
5
tWL(R1) ~tacc (R) max
3
3-16
MCM14537
FIGURE 6 - READ CYCLE WAVEFORMS UTILIZING CEI AND CE2 TO ACCESS MEMORY
~
Address
Inputs
(An)
,."'~
'WL(R2)
CE2
Vee
VSS
Vee
®
NOTES:
Vss
r
tdetay(CE2)
--Vee
1
High impedance output state occurs when eEl or CE2 is maintained
2
3
WE.
4
tdelay(CE2) minimum aSlusres that only data presently addressed
•
in the logical "'" state (high level).
is maintained at the logical "'" state for this example.
All input rise and fall times are 20 n$
will appear at the output.
tdelav(CE2) min.
5
tWL(R2)
= taceR
max. - t aCc (CE1) min.
~tdelay (c·t~f) min + tace (CE n ) max
FIGURE 7 - WRITE CYCLE WAVEFORMS
Address
Inputs
(An)
~-
~__________________________________________ ~r,O-%-----------------
'su(A)
"I-
S'robeor
i l lCEI,
or CE2
(ST,
CE2)
/ I""-----------------
~1::===-=-=-=-'-W-L-(W-)~::~--'C-y.c.(~W
. ..)~~~-=-'-h-(A-)---. .-I---....~I
r--r---------~'\.L'-7------V
"'
" " -'-_________
' -________________J/
(j)
;':'"'""
Write Enable
50%
(WE)
; -
Data Input
(Din)
Vee
VSS
Vee
VSS
~vee
VSS
~-%-~--VOH
'---------------------------VOl
NOTES;
1
2
3
4
5
The Strobe, CE 1 and 'C"E2 may be utilized to control a write cycle,
however, during changes of address either Strobe or CE2 must
be in the logical "1" state (high level).
Data input logic level is don't care during the Indicated intervals.
Data input logic level must remain fixed.
Write Enable may be maintained as a logical "0" during the write cycle.
All input rise and fall times are 20 ns.
3-17
II
MCM14537
LOGIC/BLOCK DIAGRAM
1-------
I
Din o-~:-----------------___,
I
CIT
I
o-.....,r----Q-,
3-State Enable
(High Resistance State)
I
I
I
I
I
WE
o--t-+-_~
I
I
I
§'f
I
A7
I
I
I
A6
I
A5
I
I
I
A4
Set
Output
A3
Latch
A2
r--L--o
b
I
I
I
Reset
A1
I
I
I
AO
I
I
_ __ J
L ______ _
FUNCTION
CE1
CE2
X
X
Address c;hanging
valid
X
Address changing
not valid
X
D out disabled in
high resistance state
WE
Din
D out
X
X
RIA
COMMENTS
~ will be actj~e_if
eEl and
CE2'" "0" and WE "" "1",
CE2 == "1", fully disables internal
logic and output.
X
X
X
0
0
X
X
X
X
X
X
R
CE1 '" "1" disables write cycle
and 0out.
X
X
X
R
The chip is fully disabled.
X
0
X
R
WE "'" "0" enables writing into
memory if eEl, C,E2, and
X
X
ST
X
R
RIA Changing address in this mode
may result in altered data.
§'f
%
If ST
Dout enabled in
active state
0
0
0
0
X
X
A
X
A
Read addressed
memory location
into output latch.
0
0
Disable reading
from memory
X
1
X
X
X
Write into memory
0
0
0
X
1
Write disabled
X
R
"0".
=
"1", the output stores
and reads the previous data
from or written into memory.
The output reads the present
contents that are addressed.
The addressed location is read
into output latch with output in
the "R" state.
X
X
R
X
X
RIA
A
R
Din is written into memory
and into the output latch
R
WE
X
1
X
X
X
X
X
1
X
X
X
X
X
X
X
X
1
X
R
Address changing can take
place in this condition.
'=
WE =
"1" is a read enable.
"0" is a write enable,
RIA
RIA
R "" High resistance state at D out
A::
R/A""
X::
1 =
0=
An active level of either VSS or Veo
An R or A condition depending on the don't care condition
Don't care condition (must be in thu "1" or "0" statel
A high level at Veo
A low level .. t VSS
3-18
D out
MCM14537
TYPICAL APPLICATION FOR SERIAL WORDS UTILIZING BUS TECHNIQUES
Address
Register
I
I
I~C:ln4537 I I~CM~~537 I
eEl
D
CD
eE1
0
I
I
@
)~- ---0
I
1 of n
Decoder
I 1--1
I
Twor d '" tacc(s-i)+ (n-1)
t acc (CE1)
II
Tword(t yp ) == 3.8 J.1S for a 32-bit serial -..yord at VOD '" 10 V
----------~--~~Xr~~--------4_--------~
v
lO-Bit
Address
Typical 1024 x 1 RAM Utilizing Four MCM14537's .
.{=- I~II
10-Bit
Addres
I111
An
l
1 of 4
Oecoder
CE2
~
11I1
TI I I
I111
An
0
CE2
I
I
Djl~II~~1
I
I
I
I
I
Typical Low Power 1024 x 1 RAM Utilizing Four MCM14537's.
3-19
I
I
D out
•
®
MCM14552
MOTOROLA
CMOS LSI
256-BIT STATIC RANDOM ACCESS MEMORY
ILOW.pOWER COMPLEMENTARY MOS)
The MCM14552 is a static random access memory (RAM) organized in a 64 x 4 bit pattern. The three chip enable inputs can be used
as extensions of the six address inputs, creating 9-bit address scheme.
Eight MCM14552 devices may be used to comprise a 2048·bit memory (512 x 4) without additional address decoding.
The mode control (M) is used to change the control logic charac·
teristic of the circuit. For example, with M high, the 3·state input
(T) fully controls the 3-state characteristic of the output. With M
low, the output 3'state characteristic is controlled by chip enable
inputs (CE), write enable input (WE) and T.
The memory is designed so that dc signals may operate the memory, with no maximum pulse width restrictions.
Medium speed, micropower operation, and control flexibility
make the device usefu I in scratch pad or buffer applications where
battery operation or high noise immunity are required.
• Quiescent Current = 50 /lA/package typical
@
256-BIT (64 X 41 STATIC
RANDOM ACCESS MEMORY
J.".
1-
LSUFFIX
5 Vdc
CERAMIC PACKAGE
CASE 623
• Noise Immunity = 45% of VDD typical
• 3-state Output Capability for Memory Expansion
• Output Data Latch Eliminates Need for Storage 8uffer
• Access Time = 700 ns typical
@
VDD = 10 Vdc
• Fully Decoded and Buffered
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
r
PSUFFIX
PLASTIC PACKAGE
CASE 709
• Capable of Driving Two Low·power TTL Loads, One Low·power
Schottky TTL Load or Two HTL Loads Over the Rated Temper·
ature Range
ORDERING INFORMATION
MOM"'"
M"
t:
NOTE: Pin 20(LE)) must be connected to VSS
L
P
A
C
MAXIMUM RATINGS
IVoltagesreferenced to Vss)
Symbol
Value
Unit
VDD
-0.5 to +18
Vdc
Input Voltage, All Inputs
Vi"
-0.5 to VDO + 0.5
Vdc
DC Current Drain per Pin
I
10
mAdc
TA
-55 to +125
-40 to +85
°c
T stg
-65 to +150
°c
Rating
DC Supply Voltage
Operating Temperature Range - AL Device
CL/CP Device
Storage Temperature Range
PIN ASSIGNMENT
2
3
4
6
This device contains circuitry to protect the inputs against damage due to high
static voltages or electric fields.; however, it is advised that normal precautions be
taken to avoid application of any voltage higher than maximum rated voltages
to this high impedance circuit.
For proper operation it is recommended that
Vin and Vout be constrained to the range VSS::S;;;; (Vin or Voutl ~VDD·
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either
VSSor VDD.
3-20
0. _ _
Ceramic Package
Plastic Package
Extended Operating
Temperature Range
Limited Operating
Temperature Range
8
9
10
11
12
MCM14552
ELECTRICAL CHARACTERISTICS
voo
Symbol
Vdc
"0" Level
VOL
5.0
10
15
"1" Level
VOH
5.0
10
15
Characteristic
Output Voltage
a
Vin
VDD or
Vin
o or VOO
"0" Level
Input Voltage#
IVo 4.5 or 0.5 Vdc)
Tlow
.
Min
Max
0.05
0.05
0.05
4.95
9.95
14.95
4.95
9.95
14.95
Typ
Max
Thi h*
Min
Max
a
a
a
0.05
0.05
0.05
0.05
0.05
0.05
4.95
9.95
14.95
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
VIH
IVo - 0.5 or 4.5 Vdel
IVo ~ 1.0 or 9.0 Vdel
IVO" 1.5 or 13.5 Vdcl
5.0
10
15
3.5
7.0
11.0
3.5
7.0
11.0
2.75
5.50
8.25
3.5
7.0
11.0
5.0
5.0
10
15
-1.2
-0.25
-0.62
-1.8
-1.0
-0.2
-0.5
-1.5
-1.7
-0.36
-0.9
-3.5
-0.7
-0.14
-0.35
-1.1
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
5.0
5.0
10
15
-1.0
-0.2
-0.5
-1.4
-0.8
-0.16
-0.4
-1.2
-1.7
-0.36
-0.9
-3.5
-0.6
-0.12
-0.3
-1.0
IOl
5.0
10
15
0.52
1.3
3.6
0.44
1.1
3.0
0.88
2.25
8.8
0.36
0.9
2.4
Input Current (AL Device)
lin
15
±
0.1
±0.00001
fO.l
Input Current (eLlep Device)
lin
15
i
1.0
iO.OOOOl
±l.D
5.0
7.5
IVOH
IVOH .'
IVOH "
IVOH"
c'
2.5 Vdel
4.6 Vdel
9.5 Vdcl
13.5 lidel
IVOl " 0.4 Vdel
IVOl " 0.5 Vdel
IVOl" 1.5 Vdel
Output Drive Current (CLlep Device)
IVOH 2.5 Vdel
IVOH " 4.6 Vdel
IVOH "9.5 Vdel
IVOH" 13.5 Vdel
Source
IVOl "0.4 Vdel
IVOl " 0.5 Vdel
IVOl" 1.5 Vdel
Sink
Input Capacitance
IVin
=
Vde
mAde
IOH
Source
Sink
Vdc
Vdc
5.0
10
15
Output Drive Current (AL Device)
Unit
Vde
Vil
IVo 9.0 or 1.0 Vdel
IVO" 13.50r 1.5 Vdel
"1" Level
25°C
Min
IOl
mAde
mAde
IOH
Gin
mAde
1.0
"Ade
±14.0
~Adc
±
pF
01
Quiescent Current (AL Device)
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.050
0.100
0.150
5.0
10
20
150
300
600
"Adc
Quiescent Current (CLle? DeVice)
(Per Package)
IDD
5.0
10
15
50
100
200
0.050
0.100
0.150
50
100
200
375
750
1500
J.J.Adc
Total Supply Current* * t
(Dynamic plus Quiescent,
Per Package)
(el -: 50 pF on all outputs, all
buffers switching)
IT
5.0
10
15
Three·State Leakage Current
!AL Device)
ITl
15
± 0.1
-0.00001
± 0.1
±3.0
"Adc
Three·State Leakage Current
!CL/CP Device)
ITl
15
.1.0
'0.00001
± 1.0
±7.5
J..'Adc
o-Tlow::: -55°C for AL Device, -40 o C for CL/CP Device.
Thigh = +'25 0 C for AL Device. +85 0 C for CL/CP Device.
pNoise immunity specified for worst·case input combination.
NOise Margin for both "'" and "0" level = 1.0 Vdc min @ VOO " 5.0 Vde
2.0 Vde min
2.5 Vdc min
/..lAde
IT" 11.98 "A/kHzI , + IDD
IT" 13.96 "A/kHzI f + 100
IT = 15.86 "A/kHzI f + 100
@
@
VOO = 10 Vde
VOO " 15 Vdc
tTo calculate total supply current at loads other than 50 pF:
ITIClI" ITI50 pFI +4 x 10-3 ICl -501 VOO'
where: IT is in J..'A (per package). CL in pF, VOD in Vdc, and f in kHz is input frequency,
HThe formulas given are for the typical characteristics only at 25°C.
3-21
--
•
MCM14552
SWITCHING CHARACTERISTlCS*
ICL· 50 pF T A • 25°C)
Characteristic
Output Rise Time
tTLH· 13.0 ns/pF) CL + 30 ns
tTLH· 11.5 ns/pFI CL + 25 ns
tTLH • 11.1 ns/pF) CL + 10 ns
Output Fall Time
tTHL = 11.5 ns/pF) CL + 25 ns
tTHL· 10.75 ns/pF) CL + 12.5 ns
tTHL· 10.55 ns/pFI CL + 9.5 ns
Read Cycle Time
VOO
Min
Typ
Max
5.0
10
15
-
180
90
65
360
180
130
5.0
10
15
-
100
50
40
lcyclR)
5.0
10
15
-
200
100
80
6000
2200
1650
Figure
Symbol
1
'TLH
1
1,2
Unit
ns
-
ns
tTHL
-
2000
750
500
Write Cycle Time
3,4
tcyclW)
5.0
10
15
-
1200
750
500
3600
2200
1650
ns
Address to Strobe Setup Time
1,3
tsuIA·ST)
5.0
10
15
500
150
120
-
ns
-
5.0
10
15
5.0
10
15
5.0
10
15
1500
450
350
150
100
75
1800
600
450
450
300
225
1800
450
350
Strobe to Address Hold Time
1,3
thIST·AI
Address to Chip Enable Serup Time
2,4
tsuIA·CE)
Chip Enable to Address Hold Time
2,4
thICE.A)
Strobe or Chip Enable Pulse Width When Reading
1,2
twLlR)
Strobe or Chip Enable Pulse Width When Writing
3,4
tWLIW)
5.0
10
15
5.0
10
15
3600
1800
1350
50
0
0
600
200
150
150
100
75
450
150
100
1200
600
400
Read Setup Time
1
tsulR)
5.0
10
15
Read Hold Time
1
thlR)
5.0
10
15
0
-100
-40
0
0--_._- -_. -30
540
180
240
60
180
45
Data Setup Time
3,4
tsulDI
5.0
10
15
1800
600
450
600
200
150
Data Hold Time
3,4
thlD)
5.0
10
15
600
150
120
200
50
30
--
*The formula given IS for the
tYPical characteristics only_
.
..
ns
-
ns
-
ns
ns
-
-
ns
ns
ns
ns
-
ns
-
ns
(continued)
3-22
MCM14552
(CL = 50 pF, TA ~ 25 0 CI (continuedl
Figure
Symbol
SWITCHING CHARACTERISTICS'
Characteristic
3,4
Write Enable Setup Time
tsu(WEI
3,4
Write Enable Hold Time
th(WEI
1,3
Read Access Time from Strobe
Read Access Time from Chip Enable
tacc(R·STI
-----~---.-----.
Three-State Enable/Disable Output Delay
Min
Typ
Max
Unit
720
240
180
240
80
55
-
ns
5.0
10
15
150
60
45
50
20
15
5.0
10
15
-
2000
700
350
2100
750
400
6000
2100
1600
ns
6300
2250
1700
ns
400
200
150
400
160
120
1200
600
450
ns
1200
480
360
ns
500
200
150
1500
600
450
ns
-
5.0
10
15
- - - - - f--~---- f - - - . - --2,4
5.0
tRICE"!.
10
tR(WEI
15
--._2
Output Enable/Disable Delay from Chip Enable or
Write Enable
VOO
5.0
10
15
tBcc(R-CEI
---"
2
t(TI
5.0
10
15
-
1
tLE
5.0
10
15
-
Latch to Output Propagation Delay
-
ns
-
*The formula given IS for the typical characteristics only.
Din Din Din Din
1
2
3
o
LOGIC DIAGRAM
4
Q
6
8
T
19
10
Q Q
M
CEI 23
CE222
CE3
21
A5 18 0 - - - - - - - - - - . . . . . ,
3 to 8
A4 17 0 - - - - - - - - - - . . . . . ,
Decoder
DO
A3160----------.....,
A1140----------.....,
3 C aut 0
01
5 0aut 1
02
02
7 D out 2
03
03
9 C aut 3
01
Memory
A2150----------.....,
00
64 x 4
3 to 8
Latches
Array
Decoder
AO 1 3 0 - - - - - - - - - - . . . . . ,
VOO
= Pin
24
VSS = Pin 12
3-23
•
MCM14552
FIGURE 1 - READ CYCLE WAVEFORMS UTILIZING STROBE TO ACCESS MEMORY
Address
j
tcyc(RI
VOO
VSS
t,"
(A-ST)
50%
Strobe
VOO
VSS
tWL(R)
VOO
Write Enable
VSS
tsu(RJ
Latch Enable
Data Out
Notes:
1 ~ eEl, CE2, CE3 and T are low, M is high.
2 - WE may be held high during the complete read cycle.
FIGURE 2 - READ CYCLE WAVEFORMS UTILIZING CHIP ENABLE TO ACCESS MEMORY
1--------tCYC(R)----------<~-I •
---*50%
Address
Voo
VSS
r------, --------- VOO
'--------VSS
Data Out
Notes:
, _. Unused CE, ST, M and T are low and WE is high.
2 - High impedance output state occurs when any CE is high
and M is low, or when
T
is high.
3 -
The output disP,lays data from the previous state.
4 -
tWL(R) ~ tacc(R.CElmax-
3-24
MCM14552
FIGURE 3 - WRITE CYCLE WAVEFORMS UTILIZING STROBE
VDD
Address
VSS
'h(A·!IT1
VDD
S'trO"be
VSS
VDD
Write Enable
VSS
VDD
Data In
Data Out
3
5
4
c:::
VOL
Notes:
1 - CE1, CE2. CE3 and T are maintained at the logical "0" level.
2 - M is maintained at the logical "1" level.
3 - The output displays the contents of the previous stata.
4 - The output displays the contents of the presently addressed location as in a
read modify write cycle.
5 - The output displays the data that was written into addressed location.
FIGURE 4 - WRITE CYCLE WAVEFORM UTILIZING CHIP ENABLE
~
;=====~'::CY~C~(W~I=======::::'.j
Addr...
'h (A ·CiH----I
'su(A·~1
VOO
*50%
VSS
lr-----"'----------VDD
Chip Enable
'----------VSS
,r-----VOD
50%
Write Enable
- - - - - - VSS
,---------+----- VDD
Da'a In
-------~----------+_--~JI'~-'·'--------------4_---------vss
,-----VOH
Data Out
Notes:
1 - High impedance output state occurs when
'EE
'-----VOL
is high or when WE
Is lOW, for M and T maintained In the low state.
2 - Unused CE's, fi. M and Tar. maintailied at the logical "0" lavel.
3-25
•
•
MCM14552
TRUTH TABLE
Function
eEl
eE2
eE3
LE
M
ST
WE
Din
X
Address
Changing
Valid
Address Changing
Not Valid
Do..
R/A
R/A
R/A
R/A
R/A
Dout Disabled
lin high resistancesrate)
X
Comments
Dout will be active if all
CE = 0, T= Oand ~
or if M= 1 andT=O
=,
00ut will be active if T = 0
and WE = 1 orifM = 1
andT"'O
Disables write circuitry
T '" 1 always disables Oout
M = 0 and writ.e operation
disables oout
x
00UT E'l"labled
~ inactive state}
A
A
Read Addressed
R/A
Read operation. Dout active
Read or write. Dout active
If WE = 0, Din = 00ut
Memory Location
Into Output Latch
Disable Reading
R/A
R/A
R/A
R/A
R/A
From Memory
Write Into Memory
a
A
R/A
Wnte Disabled
R/A
R/A
R/A
R/A
R/A
Output latch Enabled
R/A
Output Latch Disabled
R/A
R/A
R/A
R/A
R/A
I
A = High reSistance state at DOU !'
A "- An ------JOC=::J
Vcc=Pin 18
Vss=Pin9
Ii;
A2 t>-----CC=:J ~"8
A3O------1~====~ oc~
A4 o---Cli:=::=:l
Memory Matrix
64x64
.......... Address
........... Chip Enable
.............................. Oata In
G ...
...... Data Out
E..
w.
vee.
A5~--~~==~~
DO---
o ..
AO-All.
vss·· .
Column 1/0
. ......... Write
.......... Power (+5 VI
. .................... Ground
H:>-~G
Motorola reserves the right to make changes to any product
herein to improve reliability, function or design. Motorola
does not assume any liability arising out of the application or
use of any product or circuit described herein; neither does
it convey any license under its patent rights nor the rights of
others.
A6A7 A8 A9Al0All
w o--~t~le--------~
NP328/1HlO
3-37
•
•
®
MOTOROLA
MCM65148
Product Previe-vv
CMOS
4096-BIT STATIC RANDOM ACCESS MEMORY
ICOMPLEMENTARY MOS)
The MCM65148 is a 4096-bit Random Access Memory organized as
1024 words by 4-bits, fabricated using Motorola's high-performance
silicon-gate complementary metal oxide semiconductor IHCMOS)
technology. For ease of use, the device operates from a single power
supply, is directly compatible with TTL and requires no clocks or
refreshing because of its fully static design. Data access is particularly
simple, since address setup times are not required. The output data has
the same polarity as the input data.
The MCM65148 is designed for memory applications where simple interfacing is the design objective. The MCM65148 is assembled in an
18-pin dual-in-line. package with the industry standard pinout. A chip
enable IE) lead allows easy selection of an individual package when the
three-state outputs are OR-tied.
. _
,
I
U' -
!
I
FRIT~E;~~~~KAGE
I
CASE 726
• 1024 Words by 4-Bit Organization
•
•
•
•
•
4096-BIT STATIC
RANDOM ACCESS MEMORY
~
HCMOS Technology
Single + 5 V Supply
No Clock or Timing Strobe Required
Industry Standard 18-Pin Configuration
Maximum Access Time
MCM65148-70 - 70 ns
MCM65148-85 - 85 ns
L SUFFIX
CERAMIC PACKAGE
CASE 680
PIN ASSIGNMENT
• Automatic Power Down
• Power Dissipation
200 mW TypicallActive)
100 p,W Typical IStandby)
A6 [ii\Ji8p vec
A5[ 2
17PA!
• Fully TTL Compatible
• Common Data Inputs and Outputs
• Three-State Outputs for OR-Ties
A4
16pA8
AJ 4
15 pA9
14
Al
13
0Q2
12
003
II
004
A2
BLOCK DIAGRAM
Vcc~Pin
7
E
18
VSS~Pln9
10 W
VSS
A4~----~~-i--
om
AD
A5 --=-----\
A6 17
~
A7
~
A8 16
~
Row
Select
Memory Array
64 Rows
64 Columns
PIN NAMES
AD-A9 ..
E..
A9~
001 -----1
(Add', ...
0
(Ad:,...
>l(
I
B2
B3
I
Ad:, ...)
BINARY TO HEXADECIMAL CONVERSION TABLE
0
x c: Don t Care
-Indicates contents of specified Address will appear at outputs as stated above.
BINARY
WORD
CARD
oESIRED CHARACTER
0
0
0
0
0
0
0
0
Two methods may be used to transmit the custom memory
pattern to Motorola.
METHOD A: PUNCHED COMPUTER CARDS
o
o
o
o
0
0
1
1
0
0
,,, ,
0
1
0
0
1
2
0
1
0
4
5
6
7
,
,,,
,, 0 0 0,
0 0
, 0 ,, 0
,, 0, 0 0,
0
,, ,, ,, 0
A binary coded decimal equivalent of each desired output may
be punched in standard computer cards (four cards are required
for all 256 words) in numerical (word number) order. 64 words
1
per card are punched in columns 12 thru 75 using the Binary to
Hexadecimal conversion table. Columns 77 and 78 are used
to number the cards, which must be in numerical order. Please
use characters as shown in the table when punching computer cards.
3
8
9
A
1
B
1
C
D
E
F
1
ROM SAMPLE WORD PROGRAMMING FOR PUNCHED CARD
SAMPLE WORD
OUTPUTS
ADDRESS INPUTS
WORD
NUMBER
0
1
2
3
255
A7
0
0
0
A6
A5
0
0
0
0
0
0
0
0
1
1
1
0
A4
0
A3
A2
Al
AO
B3
B2
Bl
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
1
1
1
1
0
1
0
0
BO
0
CARD
CHARACTER
0
,
0
3
3
0
0
A
1
}
Card
NO_,
WORD NUMBER
o1 2
J 4 5 H J 8 g 10 11 1213 14
1~
16 1118192021
n
2J 24 2, 26 2128 ?!I 30 11 J2 J3 34 3b 36 31 38 39 40 414243 44
Shown in columns
12 - 15 on card
below
4~
46 41 48 49
~
51,253!>4 55 56 5/ 58 59 ijO 61 626301
00000000000100111111111111111111111111111111111111111111111111111111111111101000
I
21~ 5'1"'111""~""II~dHnHHMnUIIDaVUU"UUM".HaUO"UUUCIUUWM~~~"~~9~U'I"~"~"~"Bnl1nn"~linnnn
1111111111111111111111111111111111111111111111111111111111111111111111 1 111111111
22222222222222222222222222222222222222222222222222222222222222222222222222222222
3 3 3 3 3 3 3 33 3 3 3113 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 33 3 3 3 3 3 3 3 3 3 3 33 3 3 3 3 3 3 3 3 3
44444444444444444444444444444444444444444444444444444444444444444444444444444444
55555555555555555555555555555555555555555555555555555555555555555555555555555555
""""6'&'&6666666666666666666666666666666666666666666666666666666666666666666
1111117711777111177 J J J 1111 J 1111lJ 7 JJ JJ J J JJ 7 J JJ 7 JJ JJ J J J J J J J J J J J J J J J J J J lJ J J J J J J J J J
11111 111111 8 88 8 88 81 8 8 II 8 88 88 18 8 88 8 88 8 8 88 8 8 8 88 8 88 8 88 8 8 8 8 88 8 8 8 8 88 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
99999999999999999999999999999999999999999999999999999999999999999999999999999999
I t14' I
GL.08E NO.1
J.t~111Jl1~~11111IdnllnnNHHiIUII.3Iun~»nJJn"U41UQ"~U"~UH'IU~~~~5'"~~'lilnll~M~lri"nlIRlll'11~11JI~U
STANDARD FORM 5081
3-43
MCM14524
METHOO B: TRUTH TABLE
For customers who do not have access to punch cards, Motorola
will accept Truth Tables. When filting out the table, use the 0 to F
hexidecimal character in column "e".
CUSTOM PROGRAM for the MCM14524 Read Only Memory
WORD
WORD
C
WORD
a
51
1
52
103
2
3
53
54
4
55
5
56
57
C
WORD
C
WORD
204
153
154
205
104
155
206
105
156
207
106
157
208
107
158
209
159
210
58
108
109
160
8
9
59
110
161
211
212
60
111
10
61
112
162
163
213
214
11
12
62
113
114
164
215
165
216
115
116
117
166
167
168
217
218
219
220
221
6
7
•
C
13
14
15
16
17
63
64
65
66
67
68
18
69
19
70
71
20
21
102
118
169
119
120
170
171
121
172
122
173
174
175
222
223
224
225
72
123
22
23
73
74
124
125
176
226
227
24
75
76
126
177
228
127
178
229
26
27
77
128
179
230
78
129
180
231
28
79
130
181
232
29
80
81
131
182
233
132
183
82
83
133
184
234
235
134
185
236
84
135
186
237
238
239
25
30
31
32
33
34
85
136
187
35
86
137
188
36
37
87
138
189
240
88
190
38
89
139
140
191
241
242
39
141
192
243
40
90
91
142
245
246
41
92
143
193
194
42
93
144
195
43
44
45
94
145
196
247
95
96
97
146
197
248
147
198
199
250
46
47
148
98
149
48
49
99
100
150
200
201
151
202
50
101
152
203
3-44
244
249
251
252
253
254
255
C
®
MOTOROLA
MCM65516
Advance InforIllation
CMOS
(COMPLEMENTARY MOSI
2048 x 8 BIT READ ONLY MEMORY
The MCM65516 is a complementary MOS mask programmable byte
organized read only memory (ROM), The MCM65516 is organized as
2048 bytes of 8 bits, designed for use in multiplex bus systems. It is
fabricated using Motorola's silicon gate CMOS technology, which offers low-power operation from a single 5.0 volt supply.
The memory is compatible with CMOS microprocessors that share
address and data lines. Compatibility is enhanced by pins 13, 14, 16,
and 17 which give the user the versatility of selecting the active levels of
each. Pin 17 allows the user to choose active high, active low or a third
option of programming which is termed the "MOTEL" mode. If this
mode is selected by the user, it provides direct compatibility with either
the Motorola MCl46805E2 or Intel 8085 type microprocessor series. In
the MOTEL operation the ROM can accept either polarity signal on the
data strobe input as long as the signal toggles during the cycle. This
unique operational feature makes the ROM an extremely versatile part.
• 2Kx8 CMOS ROM
• 3 to 6 Volt Supply
• Access Time
430 ns (5 V) MCM65516-43
550 ns (5 V) MCM65516-55
2048 x 8 BIT
MULTIPLEXED BUS
READ ONLY MEMORY
~
..
L SUFFIX
CERAMIC PACKAGE
CASE 680-06
PIN ASSIGNMENTS
• Low Power Dissipation
30 mA Maximum (Active)
5O,.A Maximum (Standby)
AQO[fii\...I"iij
• Multiplex Bus Directly Compatible With All CMOS Microprocessors
(MCl46805E2, NSCBOO)
AQI
17
~VCC
G
• Pins 13, 14, 16, and 17 are Mask Programmable
• MOTEL Mask Option Also Insures Direct Compatibility with NMOS
Microprocessors Like MC6803, MC6801 , 8085, and 8086
A02
3
16
AQ3
4
15
M
14
• Standard 18 Pin Package
AQ5
S
E
AQO-AQ7
BLOCK DIAGRAM
AQ4
6
13
A06
12
Ala
AQ7
11
A9
VSS
9
10 A8
E
S
E
G
PIN NAMES
AQO-AQ7.. . ...... Address/Data Output
AS-A 10
..... Address
M ................. Multiplex Address Strobe
E
........... Chip Enable
S
.......................... Chip Select
G
... Data Strobe IOutput Enablel
M - - - - - -......
S Disables
Output Buffers
E, E Limit
Power DiSSipation
This device contains circuitry to protect
the inputs against damage due to high
ROM Array
1128x 1281
static voltages or electric fields; however,
it is advised that normal precautions be
taken to avoid application of any voltage
higher than maximum rated voltages to
this high-impedance circuit.
ADI854/9-80
3-45
II
MCM65516
ABSOLUTE MAXIMUM RATINGS ISee Notel
Symbol
Value
Unit
Supply Voltage
VCC
-0.3 to + 7.0
V
Input Voltage
Yin
-0.3 to + 7.0
Operating Temperature Range
TA
Rating
o to
+ 70
V
'c
Storage Temperature Range
-65 to + 150
'c
Tsta
NOTE: Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operatIOn should be restncted to
RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommimded voltages for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwIse noted.)
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
IVCC must be applied at least 100 pS before proper device operation is achievedl
Input High Voltage
Input Low Voltage
RECOMMENDED OPERATING CHARACTERISTICS
MCM66616-43
Characteristic
Symbol
Min
Max
Output High Voltage
MCM66616-55
Min
Max
Symbol
Min
Nom
Max
Unit
VCC
4.5
5.0
5.5
V
VIH
VCC-2.0
-
5.5
V
VIL
-0.3
-
0.8
V
Unit
Test Condition
VOH
VCC-O.4 V
-
VCC-OA V
-
V
VOL
-
0.4
-
0.4
V
Supply Current (Operating I
ICCI
-
30
-
30
mA
CL -130 pF, Vin- VIH to VIL
tcyc= 1.0 pS
Supply Current IDC Activel
Ice2
100
75
Vin- Vec to GND
50
-
pA
IISB
-
100
Standby Current
pA
Vin-VCe to GND
Input Leakage
lin
-10
+ 10
-10
+10
pA
Output Leakage
IOL
-10
+10
-10
+10
pA
Source Current - 1.6 rnA
Output Low Voltage
Sink Current + 1.6 mA
CAPACITANCE If= 1.0 MHz, T A= 25'C, periodically sampled rather than 100% tested. I
Characteristic
Input Capacitance
Output Capacitance
AC OPERATING CONDITIONS AND CHARACTERISTICS
IFull operating voltage and temperature range unless otherwise noted.1
READ CYCLE
CL= 130 pF
Symbol
Parameter
MCM66616-43
Min
Max
-
ns
725
175
-
ns
-
ns
-
50
160
-
ns
-
50
50
-
ns
-
80
-
ns
-
50
50
-
tMLDV
430
tMHMH
5BO
Multiplex Address Strobe High to Multiplex Address Strobe Low IPulse Width I
tMHML
150
-
Data Strobe Low to Multiplex Address Strobe Low
tGLML
50
Multiplex Address Strobe Low to Data Strobe High
100
Address Valid to Multiplex Address Strobe Low
tMLGH
tAVML
Chip Select Low to Multiplex Address Strobe Low
tSLML
Multiplex AddresS Strobe Low to Chip Select High
tMLSH
tELML
tEHML
Read Cycle Time
Multiplex Address Strobe Low to Address Don't Care
tMLAX
Data Strobe High to Data Valid
tGHDV
Data Strobe Low to High-Z
tGLDZ
50
50
50
50
50
50
175
-
Data Strobe High to Address Don't Care
tGHDX
20
Chip Enable Low/High to Multiplex Address Strobe Low
3-46
Unit
550
-
Address Strobe Access Time
MCM66616-55
Min
Max
-
-
80
-
ns
ns
ns
ns
200
-
ns
160
-
160
ns
-
20
-
ns
,
MCM65516
READ CYCLE TIMING
1+---------- tMHMH
IRead Cycle T l m e l - - - - - - - - - - - - - + i
VIH
M
VIL
VIH
G
VIL
VIH
E and
E
VIL
VIH
S
VIL
VIH
AS to AlO
VIL
VIH
AOO to A07
VIL
FUNCTIONAL DESCRIPTION
of address strobe. Address strobe has a minimum pulse
width requirement since the circuit is internally precharged
during this time and is setup for the next cycle on the trailing
edge of address strobe. Access time is measured tram the
negative edge of address strobe.
The part is equipped with a data strobe input IG) which
controls the output of data onto the bus lines after the addresses are off the bus. The data strobe has three potential
modes of operation which are programmable with the ROM
array. The first mode is termed the MOTEL mode of operation. In this mode, the circuit can work with either the
Motorola or Intel type microprocessor series. The difference
between the two series for a ROM peripheral is only the
polarity of the data strobe signal. Therefore, in the MOTEL
mode the ROM recognizes the state of the data strobe signal
at the trailing edge of address strobe (requires a setup and
hold time), latches the state into the circuit after address
strobe, and turns on the data outputs when an opposite
polarity signal appears on the data strobe input. In this manner the data strobe input can work with either polarity signal
but that signal must toggle during a cycle to output data on
the bus lines. (f the data strobe remains at a d.c. level the
outputs will remain off. The data strobe input has two other
programmable modes of operation and those are the standard static select modes (high or low) where a d.c. input not
synchronous with the address strobe will turn the outputs on
or off.
The chip enable and chip select inputs are all programmable with the ROM array to either a high or low select. The
chip select acts as an additional address and is latched on the
address strobe trailing edge. On deselect the chip select
merely turns off the output drivers acting as an output
disable. It does not power down the chip. The chip enable inputs, however, do put the chip in a power down standby
mode but they are not latched with address strobe and must
be maintained in a d.c. state for a full cycle.
The 2K x 8 bit CMOS ROM (MCM65516) shares address
and data lines and, therefore, is compatible with the majority
at CMOS microprocessors in the industry. The package size
is reduced from 24 pins for standard NMOS ROMs to 18 pins
because of the multiplexed bus approach. The savings in
package size and external bus lines adds up to tighter board
packing density which is handy for battery powered hand
carried CMOS systems. This ROM is designed with the intention of having very low active as well as standby currents.
The active power dissipation of 150 mW (at V CC = 5 V
freq = 1 M Hz) and standby power of 250 I'W lat V CC = 5 V)
add up to low power for battery operation. The typical access time of the ROM is 280 ns making it acceptable for
operation with today's existing CMOS microprocessors.
An example of thiS operation is shown in Figure 1. Shown
is a typical connection with either the Motorola MCl46805E2
CMOS microprocessor (M6800 series) or the National
NSCSOO which is an 8085 or ZOO based system. The main difference between the systems is that the data strobe IDS) on
the MCl46805E2 and the read bar IRD) on the 8085 both
control the output of data from the ROM but are of opposite
polamy. The Motorola 2K x 8 ROM can accept either polarity
Signal on the data strobe input as long as the signal toggles
during the cycle. This IS termed the MOTEL mode of operation. This unique operational feature makes the ROM an extremely versatile part. Further operational features are explained in the following section.
Operational Features
In order to operate in a multiplexed bus sytem the ROM
latches, for one cycle, the address and chip select input information on the trailing edge of address strobe 1M) so the
address signals can be taken off the bus.
Since they are latched, the address and chip select signals
have a setup and hold time referenced to the negative edge
3-47
MCM65516
FIGURE I
TYPICAL MINIMUM SYSTEM - MOTOROLA
IRQ
LI
Microprocessor
MCI46805E2
•
High Order Address Bus (5)
Bus Control Signals (3)
TYPICAL SYSTEM - NATIONAL
v c
+--
~
----
r1 !
4 - - BACK
------
,--.
----.
-
X2
-1-~
-
~
RESET
A8-AI5
NSC800
WAIT
Manual Reset
.AA ....
yy
~
0
XI
BREQ
~~
:
ADO-AD7
INTA
INT
~
ALE
Al3
Al21 Al3
~
NMI
AD
~
RST A
WR
~
RST B
10/M
~
RST C
ClK
~
:>
L'"
SO~
RFSR"
PS
SIr----RESET OUT
!!
u
>
z
CD
~
VV
A8-AIO AQO-AQ7
VCCGND-
M
2Kx8ROM
MCM65516
G
E
S
...
V
CE ADO-AD7 ~
To IN
<0:
I To OUT
PA
I~ I~
Muxed RAM
PB
-•
I::. tu
Q (/)
w
a:
PC
UU U
3-48
MCM65516
CUSTOM PROGRAMMING
Information for custom memory content may be sent to
Motorola in one of two forms Ish own in order of preferencel:
1. Magnetic Tape
9 track, 800 bpi, odd parity written in EBCDIC character code. Motorola's R.O.M.S. format.
2. EPROMs
One 16K IMCM2716, or TMS27161.
By the programming of a single photomask for the
MCM65516 the customer may specify the content of the
memory and the method of enabling the outputs, or selection of the "MOTEL" option IPin 171.
Information on the general options of the MCM65516
should be submitted on an Organizational Oata form such as
that shown in the below figure.
FORMAT FOR PROGRAMMING GENERAL OPTIONS
ORGANIZATIONAL DATA MOS READ ONLY MEMORY
Customer:
Company _________________________________
Motorola Use Only
Part No.--_______________________________
Originator _________________________________
Quote: ___________________________
Part No. :__________________________
Specif. No.: _________________
Phone No. -------------------------
Programmable Pin Options:
Active
High
Active
Low
13
14
16
17
o
o
o
o
o
o
o
o
MOTEL 0
3-49
•
•
3-50
Bipolar Memories _
TTL, MECL-RAM, PROM ~
4-1
•
4-2
®
MOTOROI.A
MCM93415
1024-BIT RANDOM ACCESS MEMORY
TTL
1024 X 1 BIT
RANDOM ACCESS MEMORY
The MCM93415 is a 1024-bit Read/Write RAM organized 1024
words by 1 bit.
The MCM93415 is designed for buffer control storage and high
performance main memory applications, and has a typical access
time of 35 ns.
The MCM93415 has full decoding on-chip, separate data
input and data output lines, and an active low chip select. The
device is fully compatible with standard DTL and TTL logic
families and features an uncommitted collector output for ease
F SUFFIX
CASE 650
of memory expansion.
•
Uncommitted Collector Output
•
TTL Inputs and Output
•
Non·lnverting Data Output
•
High Speed Access Time - 35 ns Typical
Chip Select - 15 ns Typical
•
Power Dissipation Decreases with Increasing Temperature
•
•
Power Dissipation 0.5 mW/Bit Typical
Organized 1024 Words X 1 Bit
,.
I.
_
1
a SUFFIX
CEAAM Ie PACKAGE
CASE 620
'-11
BLOCK OIAGRAM
P SUFFIX
•
PLASTIC PACKAGE
CASE 648
Sense Amp
and
}-------o D out
Write Drivers
PIN ASSIGNMENT
16
Word
Drivers
15
32 X 32
14
14
Array
4
13
6
11
12
10
15
1 of 32
Decoder
1 of 32
Pin Designation
Decoder
13
AD
9
8
A 1 A2 A3 A4 A5 A6 A 7 AS
A9
Vee"" Pin 16
Gnd"'Pin8
4-3
cs
Chip Select
AO-A9
Address Inputs
WE
Write Enable
Din
Data Input
D out
Data Output
I
•
MCM93415
FUNCTIONAL DESCRIPTION
The MCM93415 is a fully decoded 1024-bit Random Access
Memory organized 1024 words by one bit. Bit selection is
achieved by means of a 10-bit address, AD to A9.
The Chip Select input provides for memory array expansion.
VCCIMin)
.; RL';
IOL - FOI·1.6)
VCCIMin)-VOH
nIlCEX) + FOI0.04)
RL is in kn
n "" number of wired-OR outputs tied together
FO "" number of TTL Unit Loads (ULI driven
lCEX ""·Memory OutP~t Leakage Current
VOH := Required Output High Level at Output Node
IOL "" Output Low Current
For large memories, the fast chip select access time permits the
decoding of Chip Select (CS) from the address without affecting
system performance.
The read and write operations are controlled by the state of
the activ~ low Write Enable (WE, Pin 14). With WE held low and
the chip selected, the data at Din is written into the addressed
location. To read, WE is held high and the chip selected. Data in
The minimum RL value is limited by output current sinking
ability. The maximum R L value is determined by the output and
input leakage current which must be supplied to hold the output
at VOH. One Unit Load = 40 /lA High/l.6 mA Low.
the specified location is presented at Dout and is non-inverted.
Uncommitted collector outputs are provided to allow wiredOR applications. In any application an external pull-up resistor of
RL value must be used to provide a high at the output when it is
off. Any RL value within the range specified below may be used.
ABSOLUTE MAXIMUM RATINGS (Note 1)
TRUTH TABLE
Output
Inputs
Storage Temperature
Ceramic Package (D and F Suffix)
Plastic Package (P Suffix)
-55°C to +165 0 C
-55°C to +125 0 C
Operating Junction Temperatu.re, T J
Ceramic Package (0 and F Suffix)
Plastic Package (P Suffix)
-0.5 V to +7.0 V
Input Voltage Ide)
-0.5 V to +5.5 V
+20 mA
I nput Current (dc)
Din
X
Open
Collector
Mode
H
Not Selected
H
X
L
L
L
H
Write "0"
L
L
H
H
Write "1"
L
H
X
°out
Read
H = High Voltage Level
L = Low Voltage Level
X = Don't Care (High or Low)
-0.5 V to +5.5 V
Voltage Applied to Outputs (Output High)
Output Current (dc) (Output Low)
WE
CS
< 165°C
< 125°C
V CC Pin Potential to Ground Pin
-
-12 rnA to +5.0 rnA
NOTE 1: Device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded .
GUARANTEED OPERATING RANGES (Note 2)
Supply Voltage IVCC)
Part Number
Min
MCM934150C, PC
4.75 V
MCM93415FM, OM
4.50 V
I
I
I
Nom
5.0 V
5.0 V
I
Ambient Temperature (TAl
OOC to +75 0 C
Max
I 5.25 V
I 5.50 V
-55°C to +125 0 C
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted)
Limits
Symbol
Characteristic
Min
Max
Unit
0.45
Vde
VCC = Min, IOL = 16 mA
Vde
Guaranteed Input High Voltage for All Inputs
Vde
Guaranteed Input Low Voltage for All Inputs
Conditions
VOL
Output Low Voltage
VIH
Input High Voltage
VIL
Input Low Voltage
0.8
IlL
Input Low Current
-400
/lAde
VCC - Max, Yin - 0.4 V
IIH
Input High Current
40
/lAde
VCC - Max, Vin = 4.5 V
1.0
mAdc
VCC = Max, Vin - 5.25 V
Output Leakage Current
100
/lAde
VCC = Max, V out = 4.5 V
VCD
Input Diode Clamp Voltage
-1.5
Vde
ICC
Power Supply Current
130
mAde
TA = Max
155
mAde
TA - OoC
170
mAde
TA=Min
ICEX
2.1
4-4
VCC = Max, lin = -10 mA
I
I
I
VCC = Max,
All Inputs Grounded
MCM93415
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature unless otherwise noted)
AC TEST LOAD AND WAVEFORM
Input Pulses
Loading Condition
--',.---------""'rx'- - $(y
Vcc
All I nput Pulses
3.5V p _p
I
I I
_11" _ _ _ _ _ _ _ _ 1-
: :
Gnd :-.-, ,......10 ns
MCM93415
600
n
90%
__ 10%
: I
----...t
1--10 ns
~--------i~--90%
-:r:
'
,,
Gnd-=--I~10ns
~~10ns
30 pF
3.5Vp~ll _ _ _ _ _ _ _ _
Capacitance
( Including
Scope and Jig)
1
10%
MCM93415DC,PC MCM93415DM, FM
Symbol
Characteristic (Notes 2, 3)
READ MODE
Min
Max
Min
Unit
Max
Conditions
DELAY TIMES
tACS
Chip Select Time
35
45
See Test Circuit
tRCS
eh ip Select Recovery Time
35
50
and Waveforms
Address Access Time
45
60
tAA
WRITE MODE
DELAY TIMES
tws
Write Disable Time
35
45
See Test Circuit
tWR
Write Recovery Time
40
50
and Waveforms
INPUT TIMING REQUIREMENTS
tw
30
Write Pulse Width (to guarantee write)
tWSD
Data Setup Time Prior to Write
tWHD
Data Hold Time After Write
See Test Circuit
40
and Waveforms
tWSA
Address Setup Time (at tw '" Min)
10
15
tWHA
Address Hold Time
10
10
twscs
Ch ip Select Setup Time
tWHCS
Ch ip Select Hold Time
READ OPERATION TIMING DIAGRAM
Propagation Delay from Address Inputs
Propagation Delay from Chip Select
cs
Chip Select
AO-A~
Addre~,-_ _ _ _ _ _ _ __
r
\1
I
~~~atoutPut-----+--"'\
1
tACS
I
---t----i
'----i-,__J
I'
1
1
D out
Data Output
I
I
'RCS
(All Time Measurements Referenced to 1.5 V)
4-5
•
•
MCM93415
WRITE CYCLE TIMING
cs
Chip Select
'\
I
~
~~;r:'~,_n_p_u_ts___.Ji__.....J~
Din
Data Input
WE
!
~
~
~
~
I
I
I
I
i
I
I
tWHol
I
l.-tWHA-I
ItWSDl----i
D out
Data Output
I
111
i--tWSA-.I
"""'--twscs--l
____________________~I~-J
I
I
I
I
tws--f---------i
!
i
____________-JI
------:-----;C--+-"""'~l---tW---i1;!
Write Enable
r
________________________________--JI
I
I
~tWHCS_____l
I
\1
I
I
I~
I
I
I
I
____________
t----+tWR
(All Time Measurements Referenced to 1.5 V)
NOTE 2:
DC and AC specifications limits guaranteed with 500 linear feet per minute blown air. Contact your Motorola Sales Representative
if extended temperature or modified operating conditions are desired.
8 JA (Junction to Ambient)
Package
Blown
D Suffix
50 o C/W
85 0 C/W
F Suffix
55 0 C/W
90 o C/W
150 C/W
P Suffix
65 0 C/W
100o C/W
25 0 C/W
Still
8 JC (Junction to Case)
NOTE 3: The AC limits are guaranteed to be the worst case bit in the memory.
4-6
150 C/W
®
MCM93425
MOTOROLA
1024-BIT RANDOM ACCESS MEMORY
The MCM93425 is a 1024-bit Read/Write RAM, organized 1024
words by 1 bit.
The MCM93425 is designed for high performance main memory
and control storage appl ications and has a typical address time of
35 ns.
The MCM93425 has full decoding on·chip, separate data input
and data output lines, and an active low·chip select and write enable.
The device is fully compatible with standard DTL and TTL logic
families. A three·state output is provided to drive bus·organized
systems and/or highly capacitive loads.
•
Three·State Output
•
TTL Inputs and Output
•
Non·lnverting Data Output
•
High Speed Access Time - 35 ns Typical
•
Power Dissipation - 0.5 mW/Bit Typical
•
Power Dissipation Decreases With Increasing Temperature
TTL
1024 X 1 BIT
RANDOM ACCESS MEMORY
F SUFFIX
CERAMIC PACKAGE
CASE 650
Chip Select - 15 ns Typical
D SUFFIX
CERAMIC PACKAGE
CASE 620
BLOCK DIAGRAM
P SUFFIX
PLASTIC PACKAGE
Sense Amp
CASE 648
°out
and
Write Drivers
PIN ASSIGNMENT
Word
Drivers
32 X 32
Array
16
14
15
WE
14
3
cs
13
4
12
11
6
15
Din
1 of 32
Decoder
1 of 32
·10
9
8
Decoder
Pin Description
13
AD
A 1 A2 A3 A4 AS A6 A 7 AS
Vee"" Pin 16
cs
Gnd == Pin 8
AO-A9
Address Inputs
WE
Write Enable
Din
Data Input
°out
Data Output
A9
NOTE: Logic driving sense amp/write driven depicts
negative-only write used on C4m.
4-7
Chip Select
•
MCM93425
FUNCTIONAL DESCRIPTION
The MCM93425 is a fully decoded 1024-bit Randorn Access
Memory organized 1024 words by one bit. Word selection is
'low, the data at Din is written into the addressed location. To
read, WE is held high and
held low. Data in the specified
location is presented at Dout and is non-inverted.
The three-state output provides drive capability for higher
speeds with. capacitive load systems. The third state (high
impedance) allows bus organized systems where multiple outputs
are connected to a common bus.
During writing, the output is held in the high-impedance state.
Cs
achieved by means of a 1 O·bit address, AO-A9.
The ~hip Select (<55) input provides for memory array expansion. For large memories, the fast chip select time permits the
decoding of chip select from the address without increasing
address access time.
The read and write operations are controlled by the state of
the active low Write Enable (WE, Pin 14). With WE and
Cs
held
ABSOLUTE MAXIMUM RATINGS (Note 1)
Storage Temperature
Ceramic Package (D and F Suffix)
TRUTH TABLE
Inputs
-55°C to +165 0 C
Plastic Package (P Suffix)
-5SoC to +12SoC
Operating Junction Temperature, T J
Ceramic Package (0 and F Suffix)
Plastic Package (P Suffix)
CS
WE
H
X
<165°C
< 125°C
V CC Pin Potential to Ground Pin
-0.5 V to +7.0 V
Input Voltage (de)
-0.5 V to +5.5 V
Voltage Applied to Outputs (Output High)
-0.5 V to +5.5 V
Output Current (dc) (Output Low)
Mode
Dout
High Z
Not Sel ected
L
L
L
High Z
Write "0"
L
L
H
High Z
Write "1"
L
H
X
D out
Read
H = High Voltage Level
L "" Low Voltage Level
X '" Don't Care (High or Low)
+20 rnA
Input Current (de)
Output
Din
X
-12 rnA to +5.0 rnA
NOTE1: Device damage may occur if ABSOLUTE MAXIMUM RA TlNGS are exceeded.
GUARANTEED OPERATING RANGES (Notes 2 and 3)
Supply Voltage /VCCI
Part Number
•
Min
MCM934250C, PC
4.75 V
MCM93425FM, OM
4-50 V
I
I
Nom
I
I
5.0 V
5.0 V
Max
Ambient Temperature (T A)
1 5.25 V
OOC to +7SoC
1 5.50 V
-55°C to +125 0 C
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted)
Limits
Symbol
Max
Units
0.45
Vdc
VCC - Min, IOL - 16 mA
Vdc
Guaranteed Input High Voltage for all Inputs
Input Low Voltage
0.8
Vdc
Guaranteed Input Low Voltage for all Inputs
IlL
Input Low Current
-400
"Adc
VCC
IIH
Input High Current
40
"Adc
VCC - Max, Yin - 4.5 V
1.0
mAde
VCC - Max, Yin
loff
Output Current (High Z)
50
"Adc
VCC
lOS
Output Current Short Circuit to Ground
Characteristic
VOL
Output Low Voltage
VIH
Input High Voltage
VIL
Min
2_1
-50
I MCM934250C, PC
I MCM93425FM, DM
-100
2.4
Conditions
~
~
Max, Yin
~
~
0.4 V
5.25 V
Max, V out " 2.4 V
VCC - Max, V out - 0.5 V
mAde
Vdc
VCC
Max
VOH
Output High Voltage
Vdc
10H - -5.2 rnA
VCO
Input Diode Clamp Voltage
-1.5
Vdc
VCC - Max, lin - -10 rnA
IC_C
Power Supply Current
130
mAde
155
mAde
170
mAde
2.4
4-8
10H" -10.3 rnA, VCC" 5.0 V ±5%
T A - Max
T A - OoC
TA - Min
J
I
I
VCe" Max,
All Inputs Grounded
MCM93425
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature unless otherwise noted)
AC TEST LOAD AND WAVEFORMS
Input Pulses
Loading Conditions
All Input Pulses
~
,- i - -
--------- -~--90%
I
I
- - - - -1- \..,-_1_0_%_ __
Vee
3.5 V p •p
300.n
I 1
=--t
30pF
30 pF
~-
-
'O:p.~:...\
---=t"
-
Load B
Load A
I I
---t
1--10 ns
I
I
-
-
-
-
-
-
1--10 ns
- { - 10%
_____ --/~-90%
I
I :
I
- --t !-- 10
--!
ns
~10 ns
MCM93425DC. PC MCM93425DM. FM
Characteristic (Notes 2. 4)
Symbol
Min
Max
Max
Min
DELAY TIMES
tACS
tZRCS
Chip Select Time
Chip Select to High Z
'AA
Address Access Time
WRITE MODE
DELAY TIMES
tzws
Write Disable to High Z
twR
Write Recovery Time
35
35
45
45
50
60
35
40
45
50
Conditions
See Test Circuit
and Waveforms
ns
'W
Write Pulse Width (to guarantee write)
tWSD
Data Setup Time Prior to Write
Data Hold Time After Write
30
5
5
10
10
5
5
Address Setup Time (at tw = Min)
tWHA
Address Hold Time
twscs
Chip Select Setup Time
tWHCS
Chip Select Hold Time
See Test Circuit
and Waveforms
ns
INPUT TIMING REQUIREMENTS
tWHD
tWSA
Units
ns
READ MODE
See Test Circuit
40
5
5
15
10
5
5
and Waveforms
READ OPERATION TIMING DIAGRAM
Propagation Delay from Chip Select
Propagation Delay from Address Inut
AO-A9
cs
Address Inputs
~
--'1\. . . .---------I
I
Chip Select
D out
Load A
D out
Data Output
D out
Load B
_____~i,______'~
~'AA--I
(All time measurements referenced to 1.5 V)
4-9
..
MCM93425
WRITE CYCLE TIMING
cs
I
\.
Chip Select
AO-A9
\1
Address
J\.
\./
J\.
\
J
Din
J\.
Data Input
\.!--'W_ /
WE
Write Enable
J
\
TWSD-:-
_
_
!.-tWHD
!4-tWSA-tWHA-+I
I----tWSCS _ _ _ _ _ - t W H C S Load A
°out
Data Outpu t
--
~~----)==
High Z
tWR
Load B
(All above measurements reference to 1.5 V)
WRITE ENABLE TO HIGH Z DELAY
SV
WE
r-
Write Enable
~lSV
TZWS---..j~_ _ _ _
00ut
Data Output "0" Level
\
_
O.SV
High Z
"1" Level
°out"
Data Output
Load C
Propagation Delay from Chip Select to High Z
cs
!1.5V
Chip Select
~tZRCS
oout
Data Output
,----
"0" Level
--:':"~1'::-':-L.-V:-.'~-'I-
High Z
O.S V
0.5 V
oout
Data Output
High Z
(All tzxxx parameters are measured at a delta of 0.5 V from the logic level and using Load C)
NOTE 2: DC and AC specifications limits guaranteed with 500 linear feet per minute blown air. Contact your Motorola Sales Representative
if extended temperature or modified operating conditions are desired.
Package
9 JA (Junction to Ambient)
Still
Blown
9 JC (Junction to Case)
D Suffix
F Suffix
SOoCIW
8SoCIW
SSoC/W
900 C/W
1SoCIW
1SoC/W
P Suffix
6SoC/W
1000 C/W
2SoC/W
NOTE 3: Output short circuit conditions must not exceed 1 second duration.
NOTE 4: The maximum address access time is guaranteed to be the worst case bit in the memory.
4-10
®
MCM7G80
MCM7G81
MOTOROLA
8192-BIT PROGRAMMABLE READ ONLY MEMORY
MTTL
The MCM76BO/Bl together with the MCM7620/21, MCM7640/43
comprise a complete, compatible family having common dc electrical characteristics and identical programming requirements. They
are fully decoded, high-speed, field-programmable ROMs and are
available in commonly used organizations, with both open-collector
and three-state outputs. All bits are manufactured storing a logical
"1" (outputs high), and can be selectively programmed for logical "0"
(outputs low).
The field·programmable PROM can be custom-programmed to
any pattern using a simple programming procedure. Schottky bipolar
circuitry provides fast access time, and features temperature and
voltage compensation to minimize access time variations.
Pinouts are compatible to industry·standard PROMs and ROMs.
In addition, the MCM76BO and Bl are pin compatible replacement
for the 512 X B with pin 2 connected as A9 on the 1024 X B.
In addition to the conventional storage array, extra test rows and
columns are included to assure high programmability, and guarantee
parametric and ac performance. Fuses in these test rows and columns
are blown prior to shipment.
•
•
•
•
•
•
8192-BIT PROGRAMMABLE
READ ONLY MEMORIES
MCM7680 - 1024 X 8 - Open-Collector
MCM7681 - 1024 X 8 - Three-State
CERAMIC PACKAGE
CASE 623
Common dc Electrical Characteristics and
Programming Procedure
Simple, High-Speed Programming Procedure
(0.1 second per 1024 Bits, Typical)
Expandable - Open-Collector or Three·State
Outputs and Ch ip Enable Inputs
Inputs and Outputs TTL-Compatible
Low Input Current - 250 pA Logic "0", 40 pA Logic "1"
Full Output Drive - 16 mA Sink, 2.0 mA Source
Fast Access Time - Guaranteed for Worst-Case
N2 Sequencing, Over Commercial and Military
Temperature Ranges
Pin·Compatible with Industry-Standard PROMs and ROMs
PIN ASSIGNMENT
24
23
22
4
ABSOLUTE MAXIMUM RATINGS (See Notel
Rating
Supply Voltage (operating)
Input Voltage
21
20
Svmbol
Value
Unit
19
VCC
+7.0
Vdc
18
Vin
+5.5
Vdc
8
VOH
+7.0
Vdc
9
16
ICC
650
mAde
10
15
I nput Current
lin
-20
mAde
11
14
Output Sink Current
10
100
mAde
12
13
Output Voltage (operating)
Supply Current
Operating Temperature Range
MCM76xxDM
MCM76xxDC
Storage Temperature Range
Maximum Junction Temperature
°c
TA
-55 to +125
to +70
o
T stg
-55 to +150
TJ
+175
°c
°c
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS .,.
exceeded.
Functional operation should be restricted to RECOMMENDED
Exposure to higher than recommended voltages
OPERATING CONDITIONS.
for extended periods of time could affect device reliability. (While programming,
follow the programming specifications,)
4-11
17
--
•
MCM7680, MCM7681
DC OPERATING CONDITIONS AND CHARACTERISTICS
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Min
Nom
Max
4.50
4.75
5.0
5.0
5.50
5.25
VIH
2.0
Vde
-
-
-
VIL
0.8
Vde
Symbol
Supply Voltage
MCM76xxDM
MCM76xxDC
Vcc
Input High Voltage
Input Low Voltage
Unit
Vde
DC CHARACTERISTICS
Three-State
Output
Open-Collector
Output
Symbol
Parameter
Test Conditions
Address/Enable
"1"
.Input Current
"0"
VIH = VCC Max
VIL = 0.45 V
VOH
VOL
Output Voltage
"1"
"0"
10H
IOL
IOHE
IOLE
Output Disabled
Current
"1"
"0"
VOH, VCC - VCC Max
VOL = +0.3 V, VCC; VCC Max
IOH
Output Leakage
"1"
VOH, VCC - VCC Max
VCl
Input Clamp Voltage
lin - -10 mA
lOS
Output Short Circuit Current
VCC = VCC Max, Vaut - 0.0 V
One Output Only for 1 s Max
ICC
Power Supply Current
MCM7680/MCM7681 DC
MCM7680/MCM7681 DM
VCC = VCC Max
All Inputs Grounded
IRA,IRE
IFA,IFE
CAPACITANCE
(f
= -2.0 mA, VCC - VCC Min
= +16 mA, VCC = VCC Min
= 1.0 MHz, T A = 25 0 C, periodically
Typ
Max
Unit
-
40
!lAde
-0.1
-0.25
mAde
3.4
0.35
0.45
Vde
Vde
-
100.
-100
!lAde
!lAde
-
N/A
!lAde
-
-1.5
Vde
N/A
15
-
70
mAde
150
170
-
110
110
150
170
mAde
-
Min
Typ
Max
-
-
40
-0.1
-0.25
Min
-
N/A
-
-
2.4
-
0.35
0.45
-
100
N/A
-
100
-
-
-1.5
N/A
-
-
110
110
mAde
sampled rather than 100% tested.l
Characteristic
Input Capacitance
Output· Capacitance
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature unless otherwise noted)
o to +70o C
-55 to +1250 C
Symbol
Typ
Max
Typ
Max
Unit
Address to Output Access Time
tAA
45
70
45
85
ns
Chip Enable Access Time
tEA
30
40
30
50
Characteristic
ns
MCM7680/81
AC TEST LOAD
TIMING DIAGRAM
Vee
~
3.0V
Address ~--,.------o.o V
tAA~
Output
~r------
1.5
V~
1'------
cs ---;-;::;y
~
es
~ 3.0
1.5V
I~,---t
tEA--1
~
r--
I
"0" Output
1.5 V \
1
V
0.0 V
r---tEA
Fv
1
Test Point
u:
30 pF·
Ox
00
600
·Includes Jig Capacitance
4-12
MCM7680, MCM7681
PROGRAMMING
his own programmer to satisfy the sepcifications described
in Table 1, or buy any of th~ commercially available pro·
grammers which meet these specifications. These PROMs
can be programmed automatically or by the manual pro·
cedure shown below.
The .PROMs are manufactured with all bits/outputs
Logical "1" (Output High). Any desired bit/output can
be programmed to a Logical "0" (Output Low) by follow·
ing the simple procedure shown below. One may build
PROGRAMMING PROCEDURE
while the Vee input is raised to VpH by applying
output enable pulses to each output which is to be
programmed. The output enable pulses must be
separated by a minimum interval of td'
7. Lower Vee to 4.5 Volts following a delay of td
from the last programming enable pulse applied to
1. Address the PROM with the binary address of the
selected word to be programmed. Address inputs
are TTL·compatible. An open circuit should not be
used to address the PROM.
2. Disable the chip by applying inputs highs (VIH) to
the es inputs. es inputs must remain at VIH for
program and verify. The chip select is TTL·compatible.
An open circuit should not be used to disable the
chip.
3. Disable the woyramming circuitry by applying an
Output Voltage Disable of less than VOPD to the
output of the PROM. The output may be left open
to achieve the disable.
4. Raise Vee to VpH with rise time equal to t r .
5. After a delay equal to or greater than td' apply a
pulse with amplitude of VOPE and duration of tp to
the output selected for programming. Note that the
PROM is supplied with fuses intact generating an
output high. Programming a fuse will cause the
output to go low in the verify mode.
6. Other bits in the same word may be programmed
an output.
8. Enable the PROM for verification by applying a
logic "0" (V I L) to the es inputs.
9. If any bit does not verify as programmed, repeat
Steps 2 through 8 until the bit has received a total
of 1.0 ms of programming time. Bits which do not
program within 1.0 ms may be considered pro·
gramming rejects.
Multiple pulses of durations
shorter than 1.0 ms may be used to enhance pro·
gramming speed.
10. Repeat Steps 1 through 9 for all other bits to be
programmed in the PROM.
11. Programming rejects returned to the factory must
be accompanied by data giving address with desired
and actual output data of a location in which a
programming failure has occurred.
TABLE 1
PROGRAMMING SPECIFICATIONS
Symbol
Parameter
VIH
VIL
Address Input
VPH
VPL
Programming/Verify
ICCp
Voltagelll
Min
Typ
Max
Unit
2.4
0.0
5.0
0.4
5.0
0.8
V
V
11.75
12.0
Voltage to VCC
4.5
4.5
12.25
5.5
V
V
Programming Voltage Current Limit
600
600
650
mA
10
10
I"
Programming IVCCI
tr
tf
Voltage Rise and
1
Fall Time
I
1
1
td
Programming Delay
10
10
100
IlS
tp
Programming Pulse Width
100
-
1000
IlS
DC
Programming Duty Cycle
-
50
90
%
10.0
4.5
10.5
5.0
11.0
5.5
V
V
IlS
Output Voltage
VOPE
VOPD
lOPE
TC
Enable
Disable(21
Output Voltage Enable Current
2
4
10
mA
Case Temperature
-
25
75
°c
(1) Address and chip select should not be left open for VIH.
(2) Disable condition will be met with output open circuit.
4-13
MCM7680, MCM7681
FIGURE 1 - TYPICAL PROGRAMMING WAVEFORMS
cs ____- I
VpH----
Vee
VPL---""':':::':::'.IJ
J
Oata-2 -----------~
Oats-N - - - - - - - - - - - - - - - - - '
II
4-14
®
[
MCM7684
MCM7685
MOTOROLA
]
Advance InforIllation
MllL
8192-BIT PROGRAMMABLE READ ONLY MEMORY
The MCM7684/85 together with the MCM7620/21 /40/41 /42/43/
80/81 comprise a complete, compatible family having common dc
electrical characteristics and identical programming requirements.
They are fully decoded, high-speed, field-programmable ROMs
and are available in commonly used organizations, with both opencollector and three-state outputs. All bits are manufactured storing
a logical "I" (outputs high). and can be selectively programmed
for logical "0" (outputs low).
The field·programmable PROM can be custom-programmed
to any pattern using a simple programming procedure. Schottky
bipolar circuitry provides fast access time, and features temperature
and voltage compensation to minimize access time variations.
Pinouts are compatible to industry-standard PROMs and ROMs.
In addition, the MCM7684 and 85 are pin compatible replacement
for the 1024 X 4 with pin 8 connected as Al 0 on the 2048 X 4.
In addition to the conventional storage array, extra test rows and
columns are included to assure high programmability, and guarantee
parametric and ac performance. Fuses in these test rows and columns
are blown prior to shipment.
• Common dc Electrical Characteristics and
Programming Procedure
• Simple, High-Speed Programming Procedure
(0.1 second per 1024 Bits, Typical)
• Expandable - Open-Collector or Three-State
Outputs and Chip Enable Input
• Inputs and Outputs TTL-Compatible
Low Input Current - 250 /1A Logic "0",40 /1A Logic "I"
Full Output Drive - 16 mA Sink, 2.0 mA Source
• Fast Access Time - Guaranteed for Worst-Case
N2 Sequencing, Over Commercial and Military
Temperature Ranges
• Pin-Compatible with Industry-Standard PROMs and ROMs
8192-BIT PROGRAMMABLE
READ ONLY MEMORIES
MCM7684 - 2048 X 4 - Open-Collector
MCM7685 - 2048 X 4 - Three-State
D SUFFIX
CERAMIC PACKAGE
CASE 726
PIN ASSIGNMENT
18
2
16
4
15
ABSOLUTE MAXIMUM RATINGS (See Notel
14
Symbol
Value
Unit
VCC
+7.0
Vde
Vin
+5.5
VOH
ICC
Input Current
Output Sink Current
Rating
Supply Voltage (operating)
I nput Va Itage
Output Voltage (operating)
Supply Current
Operating Temperature Range
6
13
Vdo
8
11
+7.0
Vde
9
10
650
mAde
lin
-20
mAde
10
100
mAde
Maximum Junction Temperature
°c
TA
MCM76xxDM
MCM76xxDC
Storage Temperature Range
17
3
-55 to +125
o to +70
Tst9
-55 to +150
TJ
+175
°c
°c
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
Functional operation should b. restricted to RECOMMENDED
exceeded.
OPERATING CONDITIONS.
Exposure to higher than recommended voltages
for extended periods of time could affect device reliability.
follow the programming specifications.)
(While programming,
This is advance information and spectfic.ations are subject to change without notice.
4-15
12
II
•
MCM7684, MCM7685
DC OPERATING CONDITIONS AND CHARACTERISTICS
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Symbol
Mini
Nom
Max
4.50
4.75
5.0
5.0
5.50
5.25
Unit
Supply Voltage
MCM76xxDM
MCM76xxDC
Vcc
Input High Voltage
VIH
2.0
-
-
Vde
Input Low Voltage
VIL
-
-
0.8
Vde
Vde
DC CHARACTERISTICS
(Over Recommended Operating Temperature Range)
Open-Collector
Three~State
Output
Parameter
Svmbol
IRA. IRE
IFA.IFE
Address/Enable
VOH
VOL
Output Voltage
10HZ
10LZ
I nput Current
Output Disabled
Test Conditions
"'"
","
"'"
"0"
= VCC Max
VIL = 0.45 V
10H = -2.0 mAo VCC Min
10L = +,6 mAo VCC Min
"0"
VOH. VCC Max
VOL = +0.3 V. VCC Max
10H
Current
Output Leakage
VIC
Input Clamp Voltage
lin--'OmA
lOS
Output Short Circuit Current
VCC Max. Vout = 0.0 V
One Output Only for's Max
ICC
Power Supply Current
VCC Max
All Inputs Grounded
"'"
(I = 1.0 MHz.
Max
Min
Typ
Max
Unit
-
-
40
-
-
40
~Ade
-0.,
-0.25
-
-0.,
-0.25
mAde
N/A
-
-
2.4
-
-
0.35
0.45
-
3.4
0.35
0.45
Vde
Vde
-
-
,00
N/A
-
-
-
,00
-,00
/lAde
N/A
/lAde
-
-
-1.5
-
N/A
,5
80
80
120
140
-
N/A
-
TA = 25 0 C. periodically
-
,00
VOH. VCC Max
MCM7684/MCM7685 DC
MCM7684/MCM7685 OM
CAPACITANCE
Typ
VIH
"0"
Output
Min
-
~Ade
-1.5
Vde
-
70
mAde
80
80
120
140
mAde
mAde
sampled rather than 100% tested.)
Characteristic
Input Capacitance
Output Capacitance
ACOPERATING CONDITIONS AND CHARACTERISTICS
o to +700 C
(Full operating voltage and temperature unless otherwise noted)
Characteristic
Address to Output Access Time
Chip Enable Access Time
-55 to +'25 0 C
Symbol
Typ
Max
Typ
Max
Unit
tAA
45
70
45
85
ns
tEA
,5
25
15
30
ns
AC TEST LOAD
TIMING DIAGRAM
Vee
,
~
3.0V
Addre.. ~--,-------O.O V
tAA~
Output
~r-------
1.5 V ~
,'-------
cs --;;::;v
~
CS
~ 3.0 V
1.5V
teA--l....,..~-----i-t r--te~O V
"0" Output
1.5
V~
,
r;;:v
Input t r • tf
< 5.0
;_,.'"'~o.
30PF°tJ600
ns
·Includes Jig Capacitance
4-16
MCM7684, MCM7685
PROGRAMMING
The PROMs are manufactured with all bits/outputs
Logical "1" (Output High). Any desired bit/output can
be programmed to a Logical "0" (Output Low) by follow·
ing the simple procedure shown below. One may build
his own programmer to satisfy the sepcifications described
in Table 1. or buy any of the commercially available programmers which meet these specifications. These PROMs
can be programmed automatically or by the manual procedure shown below.
PROGRAMMING PROCEDURE
1. Address the PROM with the binary address of the
selected word to be programmed. Address inputs
are TTL·compatible. An open circuit should not be
used to address the PROM.
while the Vee input is raised to VpH by applying
output enable pulses to each output which is to be
programmed. The output enable pulses must be
separated by " minimum interval of td'
Lower Vee to 4.5 Volts following a delay of td
from the last programming enable pulse applied to
an output.
Enable the PROM for verification by applying a
logic "0" (V I Ll to the es inputs.
If any bit does not verify as programmed, repeat
Steps 2 through 8 until the bit has received a total
of 1.0 ms of programming time. Bits which do not
program within 1.0 ms may be considered pro·
gramming rejects.
Multiple pulses of durations
shorter than 1.0 ms may be used to enhance programming speed.
Repeat Steps 1 through 9 for all other bits to be
programmed in the PROM.
Programming rejects returned to the factory must
be accompanied by data giving address with desired
and actual output data of a location in which a
programming failure has occurred.
7.
2. Disable the chip by applying an input high (V IH) to
the es input. The chip select is TTL·compatible.
An open circuit should not be used to disable the
chip.
8.
9.
3. Disable the programming circuitry by applying an
Output Voltage Disable of less than VOPD to the
output of the PROM. The output may be lett open
to achieve the disable.
4. Raise Vee to VpH with rise time equal to t r ·
5. After a delay equal to or greater than td' apply a
pulse with amplitude of VOPE and duration of tp to
the output selected for programming. Note that the
PROM is supplied with fuses intact generating an
output high. Programming a fuse will cause the
output to go low in the verify mode.
10.
11.
6. Other bits in the same word may be programmed
TABLE 1
PROGRAMMING SPECIFICATIONS
Min
TVp
Max
Unit
VIH
VIL
Address Input
2.4
5.0
5.0
Voltage(l!
0.0
0.4
0.8
V
V
VPH
VPL
Programming/Verify
Voltage to Vce
11.75
4.5
12.0
4.5
12.25
5.5
V
V
600
600
650
mA
1
1
1
1
10
10
~s
Symbol
ICCp
Parameter
Programming Voltage Current Limit
Programming (Vee!
tr
tf
Voltage Rise and
Fall Time
~s
td
Programming Delay
10
10
100
~s
tp
Programming Pulse Width
100
-
1000
~s
DC
Programming Duty Cycle
-
50
90
%
10.0
4.5
10.5
11.0
5.0
5.5
V
V
Output Voltage
VOPE
VOPD
lOPE
TC
Enable
Disable(2!
Output Voltage Enable Current
2
4
10
mA
Case Temperature
-
25
75
°c
(1) Address and chip select should not be left open for VIH.
(2) Disable condition will be met with output open circuit.
4-17
MCM7684, MCM7685
FIGURE 1 - TYPICAL,PROGRAMMING WAVEFORMS
cs-----~
-"''''-';;0
VPH
- - - - - - 1 1 ...- - - - - - - - - - - - _
VPL
----.:.::.::.Jf
vee
Data-1
00'0-2 _ _ _ _ _ _ _ _ _ _ _....J
VOP-E
Oo.o-N _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _....J
•
4-18
MECL MEMORIES
GENERAL INFORMATION
Complete information is available in the M EC L Data Book. Contact your sales representative or authorized
distributor for information.
TABLE 1 - LIMITS BEYOND WHICH DEVICE LIFE MAY BE IMPAIRED
Characteristic
Supply Voltage
Input Voltage (VCC = 0)
Output Source Current -
Rating
Unit
VEE
-8.0 to 0
V
Vin
Continuous
Surge
Junction Temperature - Ceramic PackageG)
Plastic Package
Storage Temperature
CD
Symbol
a to
VEE
V
lout
50
100
mA
TJ
165
150
°c
T stg
-55to+150
°c
Maximum T J may be exceeded (";; 250°C) for short periods of time (";; 240 hours) without significant
reduction in device life.
TABLE 2 - LIMITS BEYOND WHICH PERFORMANCE MAY BE DEGRADED
Characteristic
Supply Voltage (VCC = 0)0
Output Drive -
MCM1 01 00 Series
M CM 10500 Series
Operating Temperature Range@
MCM 1 01 00 Series
MCM1 0500 Series
Unit
Symbol
Rating
VEE
-4.94 to -5.46
V
-
50 n to -2.0 V
100 n to -2.0 V
n
TA
°c
o to
75
-55to+125
Functionality only. Data sheet limits are specified for -5.19 to -5.21 V.
With airflow .. 500 Ifpm.
4-19
II
•
MECL MEMORIES (continued)
TABLE 3 - DC TEST PARAMETERS
Each M EeL 10,000 series device has been designed to meet the dc spe6iii~ations shown in the test table, after
thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board
and transverse airflow greater than 500 linear feet per minute is maintained. VEE = -5.2 V ± 0.010 V.
VIHmax
-0.880
-1.080
-1.100
-1.255
-1.510
-1.635
-1.655
-1.920
0.5
= VOHmax
VOHAmin
VIHAmin
VILAmin
VOLAmin
r
VOLAmax
.
7SoC
2SoC
Parameter MCM10500* MCM10100** MCM10100** MCM10500* MCM10100**
VOHmin
VILmin
VILmin
OOC
-SSoC
Forcing
Function
.
VOLmin
IINLmin
• Driving 100
··Driving 50
n
-0.840
-1.000
-1.020
-1.145
-1.490
-1.645
-1.665
-1.870
0.5
-0.810
-0.960
-0.980
-1.105
-1.475
-1.630
-1.650
-1.850
0.5
-0.780
-0.930
-0.950
-1.105
-1.475
-1.600
-1.620
-1.850
0.5
-0.720
-0.900
-0.920
-1.045
-1.450
-1.605
-1.625
-1.830
0.3
12SoC
MCM10S00*
-0.630
-0.825
-0.845
-1.000
-1.400
-1.525
-1.545
-1.820
0.3
to -2.0 V .
n to -2.0 V.
Vee
= Gnd
____ 1!L __ .,
0-
,,
I
I
I
I
I
I
I
I
I
I
I
I
I
I
INPUT
A,
A2
A3
A4
A5
tr
I
A7
I
RT
I
I
I
I
I
I
Din
rf -
2.0 ns typo
All timing measurements referenced to 50% of input levels.
I
I
I
=:
Dout
A6
I
I
L~VELS
C5' CS2 CS3
"0
eLl
CL
OS;;;
5,0 pF (including jig and stray capacitance)
Delay should be derated 30 ps/pF for capacitive load up to 50 pF
~
-2.0 V
I
WE
I
I
I
c-------Tr,",
I
-6.2 Vdc
VEE
FIGURE 1 - SWITCHING TIME TEST CIRCUIT
4-20
MECL MEMORIES (continued)
FIGURE 2 - CHIP SELECT ACCESS TIME WAVEFORM
Chip Select
cs
C out
FIGURE 3 - ADDRESS ACCESS TIME WAVEFORM
Address
FIGURE 4 - SETUP AND HOLD WAVEFORMS (WRITE MODEl
Address
II
50%
50%
D out
~-----tWSA------
tws
4-21
•
MCM10143
@ MOTOROLA
8 X 2 MULTIPORT REGISTER
FILE (RAM)
8 x 2 MULTIPORT REGISTER FILE
(RAM)
The MCM10143 is an 8 word by 2 bit multipart register file
(RAM) capable of read,ing two locations and writing one location simultaneously. Two sets of eight latches are used for data
storage In this LSI circuit.
WRITE
The word to be written is selected by addresses AO-A2. Each bit
of the word has a separate write enable to allow more flexibility in
system design. A write occurs on the positive transition of the clock.
Data is enabled by having the write enables at a low level when the
clock makes the transition. To inhibit a bit from being written, the
bit enable must be at a high level when the clock goes low and not
change until the clock goes high. Operation of the clock and the bit
enables can be reversed. While the clock is Iowa positive transition of
the bit enable will write that bit into the address selected by AO-A2.
L SUFFIX
CERAMIC PACKAGE
CASE 623
READ
When the clock is high any two words may be read out simultaneously, as selected by addresses 80-82 and CO-C2, including the
word written during the preceding half clock cycle. When the clock
goes low the addressed data is stored in the slaves. Level changes on
the read address lines have no effect on the output until the clock
again goes high. Read out is accomplished at any time by enabling
output gates (80-81), (CO-Gl).
PIN ASSIGNMENT
Vcco
tpd:
Glock to Data out ~ 5 ns (typ)
(Read Selected)
Address to Data out ~ IOns (typ)
(Glock High)
Read Enable to Data out ~ 2.8 ns (typ)
(Clock high, Addresses present)
PD ~ 610 mW/pkg (typ no load)
VCC
OBI
VCCI
23
3
aBO
OCI
22
4
REs
QCO
21
5
B2
REC
20
19
BO
Clock
Bl
C2
18
8
WEI
Co
17
9
WEO
Cl
16
DO
Al
15
01
AO
14
VEE
A2
13
6
10
TRUTH TABLE
INPUT
"MODE
Write
4*Clock
WEo
WEI
DO
L_
L
L
H
,~
OUTPUT
Dl
REC
OBo
OBI
OCo
OCI
H
H-
H
L
H
L
H
L
H
Q
Q
L
L
H
¢
Q
L
L
H
H
H
H
H
H
¢
Q
L
H
H
H
H
L~H
L
L
L
H
L
H
H
L
L
L
L
H
¢
'"
Q
Q
L
L
L
H
L
H
H
Read
Read
W+L
Read
L-)-H-1>l
Write
Read
"
Q
Q
L
• °Note: Clock occurs sequentially through Truth Table
• Note: AQ-A2, BO-S2. and CO-C2 are all set to same address location
Q
11
REB
throughout Table.
Don't Care
4-22
24
2
12
MCM10143
BLOCK DIAGRAM
4
6
Read
Decoder ---<
B
7
5
~
f-----~
9
WEo
~
10
DO
Write
Amplifier
Bit 0
'--
r-;:;
~
14
~
01
~
16
18
20
t-- f~
Slave
B-bit 0
-
~
f-
-
L,..
Output
Gate
B-bit 1
~
aBl
Output
Gate
B-bit 0
~
aBO
8 xl
Master Latches
Bit 0
8 x 1
Master Latches
,..Bit 1
f---+
17
Multiplexer
B-bit 0
r--
Slave
B-bit 1
I~
Write
Amplifier
Bit 1
~
~
~
Write
Decoder
A
15
13
8
11
WEl
Multiplexer
B-bit 1
Read
Decoder
C
~
Multiplexer
C-bit 1
~
-
r--
- L.
Multiplexer
C-bit 0
4-23
~
II
Slave
C-bit 1
Slave
C-bit 0
f----
Output
Gate
C-bit 1
.E...o
-
Output
Gate
C-bit 0
~ aco
--.....
aCl
II
MCM10143
ELECTRICAL CHARACTERISTICS
oOC
+25 0 C
+75 0 C
Characteristics
Symbol
Min
Max
Min
Typ
Max
Min
Max
Unit
Power Supply Drain Current
IE
-
150
-
118
150
-
150
mAde
-
245
200
-
-
-
-
245
200
-
245
200
Input Current
Pins 10,11,19
All other pins
linH
!LAde
-
Switching Times (!)
ns
Read Mode
Address Input
Read Enable
Data
Setup
Address
Hold
Address
as ±
4.0
1.1
1.7
15.3
5.3
7.3
4.5
10
14.5
4.5
15.5
tRE-QB+
tClock+QB-
1.2
2.0
3.5
5.0
5.0
7.0
1.2
2.0
5.5
7.6
tsetup(B-Clock-)
-
-
8.5
5.5
-
-
-
thold(Clock-B+)
-
-
-1.5
-4.5
-
-
-
-
7.0
1.0
8.0
5.0
4.0
-2.0
5.0
2.0
-
-
-
2.5
-2.0
-3.0
-2.0
ts ±-
Write Mode
Setup
Write Enable
Address
Data
Hold
Write Enable
Address
Data
Write Pulse Width
Rise Time, Fall Time
(20% to 80%)
tsetup(WE-Clock+)
tsetup(WE+Clock- )
tsetup (A -Clock +)
tsetuolD -Clock +1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5.5
1.0
1.0
1.0
PWWE
-
-
8.0
5.0
-
t r , tf
1.1
4.2
1.1
2.5
4.0
4-24
-
-
thold(Clock +WE +)
thold(Clock+WE-)
thold (Clock + A +)
thold(Clock+D+)
(j)AC timing figures do not show all the necessary presetting conditions.
-
-
-
-
-
1.1
4.5
MCM10143
READ TIMING DIAGRAMS
FIGURE 1
Enable
RE
FIGURE 2
a
FIGURE 3
FIGUR.E 4
4-25
II
II
MCM10143
WRITE TIMING DIAGRAM
Enable Setup
WE
FIGURE 5
Clock
Enable Hold
WE
Clock
\
~
-~.,
FIGURE 6
Disable
FIGURE 7
WE
Clock
Pulse Width
FIGURE 8
Clock
t»
Address
A ----,.
tsetup
r--------- - - - "-------+---------'1\- - - - -
Clock _ _ _ _ _ _ _ _ _ _ _JI
4-26
FIGURE9
®
MCM1 0144/MCM1 0544
256 x 1-BIT RANDOM
MOTOROL.A
ACCESS MEMORY
-::
AD
A1
A2
A3
A4
2
:
~
'
.
.
"
-g:;
1D"l)
=8
3
~~
'lID
4
'It!
,,1;
3:.
9
14
WE
!~
0;: 1\1
'ON
Q
13
Din
3:
A5
A6
The MCM 1 0144/1 0544 is a 256 word
X 1-bit RAM. Bit selection is achieved by
means of an 8-bit address AD th rough A 7.
The active-low chip select allows memory
expansion up to 2048 words. The fast ch ip
select access time allows memory expansion
without affecting system performance.
The operating mode of the RAM (CS inputs
low) is controlled by the WE input. With WE
low the chip is in the write mode-the output
is low and the data present at Din is stored
at the selected address. With WE high the chip
is in the read mode-the data state at the
selected memory location is presented noninverted at D out .
•
Typical Address Access Time = 17 ns
•
Typical Chip Select Access Time = 4.0 ns
•
50 kf!. Input Pulldown Resistors on Chip
Select
•
Power Dissipation (470 mW typ @ 25 0 C)
Decreases with Increasing Temperature
•
Pin-for-Pin Replacement for F10410
A7
TRUTH TABLE
MODE
INPUT
OUTPUT
Dout
cs·
WE
Write "0"
L
L
L
L
Write "1"
L
L
H
L
Read
L
H
H
'"
'"
Q
Disabled
Din
'"
PIN ASSIGNMENT
16
15
L
cP =
3
Don't Care.
4
~
~~CUE:AMIC
14
13
12
6
F SUFFIX
LSUFFIX
PACKAGE
CERAMIC PACKAGE
CASE 650
CASE 620
4-27
11
10
8
9
II
II
MCM10144/MCM10544
ELECTRICAL CHARACTERISTICS
OOC
-55°C
Characteristic
+25 0 C
+75 0 C
+125 0 C
Symbol Min Max Min Max Min Max Min Max Min Max
Power Supply Drain Current
lEE
-
140
-
135
-
130
Input Current High
linH
-
375
-
220
-
220
-
Unit
125
-
125
mAdc
220
-
220
MAdc
-55°C and +125 0 C test values apply to MC105xx devices only_
SWITCHING CHARACTERISTICS (Note 1)
MCM10144 MCM10544
TA=Oto
+ 75°C,
VEE =
-5.2 Vdc
± 5%
Characteristics
Read Mode
Chip Select Access Time
Chip Select Recovery Time
Address Access Time
Write Mode
Write Pulse Width
Data Setup Time Prior to Write
Data Hold Time After Write
Address Setup Time Prior to Write
Address Hold Time After Write
Chip Select Setup Time Prior to
Write
Chip Select Hold Time After Write
Write Disable Time
Write Recovery Time
Rise and Fall Time
Symbol Min
Max
2.0
2.0
7.0
10
10
26
2.0
2.0
7.0
10
10
26
tw
25
2.0
2.0
8.0
-
25
2.0
2.0
8.0
-
0.0
2.0
-
2.0
2.5
2.5
10
twSD
tWHD
tWSA
twHA
tWSCS
tWHCS
tws
tWR
t r , tf
Address to Output
to Output
NOTES:
Min
tACS
tRCS
tAA
CS or WE
Capacitance
Input Capacitance
Output Capacitance
Max
TA = -55 to
+125 0 C,
VEE =
-5.2 Vdc
± 5%
Cin
Cout
-
2.0
-
2.0
-
2.0
2.5
2.5
10
10
-
Unit
Conditions
ns
Measured from 50% of
input to 50% of outPUt.
See Note 2.
ns
tWSA - 8.0 ns
Measured at 50% of
input to 50% of output.
tw = 25 ns.
ns
Measured between 20%
and 80% points.
pF
Measured with a pulse
technique.
-
10
1.5
1.5
7.0
5.0
1.5
1.5
7.0
5.0
-
5.0
-
8.0
-
5.0
8.0
1. Test circuit characteristics: RT = 50 n, MCM10144; 100 n, MCM10544. CL';; 5.0 pF (including jig
and stray capacitance). Delay should be derated 30 ps/pF for capacitive load up to 50 pF.
2. The maximum Address Access Time is guaranteed to be the Worst-Case Bit in the Memory.
3. For proper use of MECL Memories in a system environment, consult MECL System Desl-gn
Handbook.
4-28
®
MCM10145/MCM10545
MOTOROL.A
16 X 4-BIT REGISTER FILE
(RAM)
The MCM10145/10545 is a 16 word X 4-bit
RAM. Bit selection is achieved by means of
a 4-bit address AO th rough A3.
The active-low chip salect allows memory
expansion up to 32 words. The fast ch ip
select access time allows memory expansion
without affecting system performance.
The operating mode of the RAM (CS input
low) is controlled by the WE input. With WE
low the chip is in the write mode-the output
is low and the data present at Dn is stored at
the selected address. With WE high the chip
is in the read mode-the data state at the
selected memory location is presented noninverted at
an-
•
Typical Address Access Time = 10, ns
•
Typical Ch ip Select Access Time = 4.5 ns
kn
•
50
•
Power Dissipation (470 mW typ @ 25 0 C)
Decreases with Increasing Temperature
Pulldown Resistors on All Inputs
WE
PIN ASSIGNMENT
00
01
02
03
I
01
Vee
16
03
14
15
TRUTH TABLE
MODE
INPUT
OUTPUT
4
13
6
11
12
Write "0"
L SUFFIX
Write "1"
L
R.ad
L
Disabled
H
q, ""
H
H
L
o
DonOt Care.
CERAMIC PACKAGE
CASE 620
FIGURE 1 - CHIP ENABLE STROBE MODE
A _ _ _ _.I1
Din-----4..J
F SUFFIX
CERAMIC PACKAGE
CASE 650
10
8
~ --------------~I
4-29
9
•
•
MCM10145/MCM10545
ELECTRICAL CHARACTERISTICS
Ooc
-SSoC
Characteristic
+7SoC
+2SoC
+ 12SoC
Symbol Min Max Min Max Min Max Min Max Min Max
Power Supply Drain Current
lEE
-
135
-
130
-
125
Input Current High
linH
-
375
-
220
-
220
-
120
-
120
220
-
220
Unit
mAdc
~Adc
-55°C and +1250 C test values apply to MC105xx devices only.
SWITCHING CHARACTERISTICS (Note 1)
MCM10145 MCM10545
TA=Oto
+75 0 C,
VEE=
-S.2 Vdc
± 5%
Characteristics
Read Mode
Chip Select Access Time
Chip Select Recovery Time
Address Access Time
Write Mode
Write Pulse Width
Data Setup Time Prior to Write
Data Hold Time After Write
Address Setup Time Prior to Write
Address Hold Time After Write
Chip Select Setup Time Prior to
Write
Chip Select Hold Time After Write
Write Disable Time
Write Recovery Time
Chip Enable Strobe Mode
Data Setup Prior to Chip Select
Write Enable Setup Prior to
Chip Select
Address Setup Prior to Chip Select
Data Hold Time After Chip Select
Write Enable Hold Time After
Chip Select
~ddress Hold Time After Chip
Select
Chip Select Minimum Pulse Width
Rise and Fall Time
Address to Output
CS to Output
Capacitance
Input Capacitance
Output Capacitance
NOTES:
Symbol
Min
Max
TA=-5Sto
+ 125°C,
VEE =
-5.2 Vdc
±5%
Min
Max
tACS
tRCS
tAA
2.0
2.0
4.0
8.0
8.0
15
2.0
2.0
4.0
10
10
18
tw
twSD
tWHD
tWSA
tWHA
tWSCS
8.0
0
3.0
5.0
1.0
'0
-
-
8.0
0
4.0
S.O
3.0
S.O
-
tWHCS
tws
tWR
0
2.0
2.0
8.0
8.0
0
2.0
2.0
10
10
tCSD
tcsw
0
0
-
-
-
tCSA
tCHD
tCHW
0
2.0
0
-
-
-
tCHA
4.0
-
-
-
tcs
18
-
-
-
1.5
1.5
7.0
5.0
1.5
1.5
7.0
5.0
-
6.0
8.0
-
6.0
8.0
-
Conditions
ns
Measured from 50% of
input to 50% of output.
See Note 2.
ns
tWSA = 5 ns
Measured at 50% of
input to 50% of output.
tw = 8 ns.
ns
Guaranteed but not
tested on standard
product. See Figure 1.
ns
Measured between 20%
and 80% points.
pF
Measured with a pulse
technique.
-
t r , tf
Cin
Cout
Unit
1. Test circuit characteristics: RT = 50 n, MCM10145; 100 n, MCM10545. CL";; 5.0 pF (including jig
and Stray Capacitance). Delay should be derated 30 ps/pF for capacitive loads up to 50 pF:
2. The maximum Address Access Time is guaranteed to be the worst-case bit in the memory.
3. For proper use of MECL Memories in a system environment, consult MECL S'ystem Design Handbook.
4-30
®
AO
AI
A2
A3
A4
2
3
4
MCM1 0146/MCM1 0546
MOTOROLA
1024 X 1-BIT RANDOM
ACCESS MEMORY
.=-.-
"''''
'" 0
"",0~
The MCM10146/10546 is a 1024 Xl-bit
RAM. Bit selection is achieved by means of
a 10-bit address, AO to A9.
The active-low chip select is provided for
memory expansion up to 2048 words.
The operating mode of the RAM (~ input
low) is controlled by the WE input. With WE
low, the chip is in the write mode, the output,
Dout, is low and the data state present at
Din is stored at the selected address. With WE
high, the chip is in the read mode and the data
stored at the selected memory location will be
presented non-inverted at D out . (See Truth
Table.)
13
o~
5
~~
6
~m
N
,
15
A5
A6
A7
AS
A9
•
Pin-for-Pin Compatible with the 10415
•
Power Dissipation (520 mW typ @ 25 0 C)
Decreases with I ncreasing Temperature
•
Typical Address Access of'24 ns
•
Typical Chip Select Access of 4.0 ns
•
50 k!l Pulldown Resistor on Chip Select
Input
PIN ASSIGNMENT
TRUTH TABLE
MODE
INPUT
WE
Din
Dout
Write "0"
L
L
L
L
Write "1"
L
L
H
L
H
'"
0
Read
L
Disabled
H
ttJ
c
'"
Don't Car •.
16
OUTPUT
CS
'"
15
14
4
13
12
6
11
S
9
L
10
_LSUFFIX
CERAMIC PACKAGE
CASE 620
CERAMIC PACKAGE
CASE 650-03
4-31
III
!
•
MCM10146/MCM10546
ELECTRICAL CHARACTERISTICS
Ooc;:
-55°C;:
Characteristic
Symbol
Power Supply Drain Current
lEE
Input Current High
Logic "0" Output Voltage
'inH
VOL
+75 0 C
+ 25°C;:
+ 125°C
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
--
155
-
150
-
145
-
125
-
125
mAde
220
-
220
/JAdc
375
220
220
-1.970 -1.655 -1.920 -1.665 -1.900 -1.650 -1.880 -1.625 -1.870 -1.545
Vdc
NOTE: -55°C and +125 0 C test values apply to MCM105XX only.
SWITCHING CHARACTERISTICS (Note 1)
Characteristics
Read Mode
Chip Select Access Time
Chip Select Recovery Time
Address Access Time
WriteMode
Write Pulse Width
Symbol
MCM10146
MCM10546
TA = 0 to
+ 75°C.
VEE = -5.2 Vdc
± 5%
TA=-55to
+ 125°C.
VEE = -5.2 Vdc
± 5%
Min
Max
Min
Max
Unit
ns
tACS
tRCS
tAA
2.0
2.0
8.0
7.0
7.0
29
2.0
2.0
8.0
8.0
8.0
40
tw
25
-
25
-
tWSD
tWHD
tWSA
tWHA
tWSCS
5.0
5.0
8.0
2.0
5.0
-
-
-
5.0
5.0
10
8.0
5.0
tWHCS
5.0
2.8
2.8
7.0
7.0
5.0
2.8
2.8
12
12
1.5
4.0
1.5
4.0
1.5
8.0
1.5
8.0
-
5.0
8.0
-
5.0
8.0
ns
tWSA =8.0 ns.
Measured at 50% of input
to 50% of output.
tw = 25 ns
ns
Measured between 20% and
80% points.
pF
Measured with a pulse
technique.
(To guarantee writing)
Data Setup Time Prior to Write
Data Hold Time After Write
Address Setup Time Prior to Write
Address Hold Time After Write
Chip Select Setup Time Prior to
Write
Chip Select Hold Time After Write
Write Disable Time
Write Recovery Time
Rise and Fall Time
ES or iiiiE to Output
tws
twA
-
-
-
t r • tf
Address to Output
Capacitance
I nput Capacitance
Output Capacitance
Cin
Cout
Conditions
Measured at 50% of input
to 50% of output.
See Note 2.
NOTES: 1. Test circuit characteristics: RT = 50 n. MCM10146; 100 n. MCM10546. CL" 5.0 pf including Jig and stray capacitance.
For Capacitance Loading .. 50 pF. delay should be derated by 30 ps/pF.
2. The maximum Address Access Time is guaranteed to be the Worst·Case Bit in the Memory.
3. For proper use of MECL Memories in a system environment. consult MECL System Design Handbook.
4-32
®
MCM10147/MCM10547
MOTOROL.A
128 X 1-BIT
RANDOM ACCESS MEMORY
The MCM1047/10547 is a fast 128-word
X 1-bit RAM. Bit selection is achieved by
means of a 7-bit address, AD through A6.
The active-low chip selects and fast chip
select access time allow easy memory expansion
up to 512 words without affecting system
performance.
The operating mode (CS inputs low) is
controlled by the WE input. With WE low the
chip is in the write mode-the output is low and
AO
AI
12
WE
4
A2
A3
11
A4
AS
the data present at Din is stored at the selected
address. With WE high the chip is in the read
mode-the data state at the selected memory
location is presented non-inverted at D out .
•
Typical Address Access Time of 10 ns
•
Typical Chip Select Access Time of 4.0 ns
•
50
•
Power Dissipation (420 mW typ @ 25 0 C)
Decreases with I ncreasing Temperature
•
Similar to F 1 0405
A6
kn
Input Pulldown Resistors
on All Inputs
PIN ASSIGNMENT
TRUTH TABLE
16
MODE
15
14
13
4
12
11
AS
8
INPUT
cs'
WE
Write "0"
L
L
L
L
Write "'"
L
L
H
L
Read
L
H
f/J
a
Oisabled
H
f/J
f/J
L
t/J
A6
OUTPUT
Dout
=
Din
Don't Care.
N.C.
:_LSUFFIX
CERAMIC PACKAGE
CASE 620
4-33
CASE 650
•
•
MCM10147/MCM10547
ELECTRICAL CHARACTERISTICS
ooc
-55°C
Characteristic
Symbol
Power Supply Drain Cu
0
"0" r---O~
460
Test
Po i n t
n
Outputs
VEE
-5.2 V
CE
Open
8
VEE
VEE
-5.2 V
-5.2 V
7.5 k
(All Outputs)
~
VEE
-5.2 V
FIGURE 2 - AUTOMATIC PROGRAMMING CIRCUIT
Address
--1
I
Vce
--1
u
U
I
I
U~------'L
I
I~!--""'L
1 4 - - - - - - - - - - - - - <1
Second
4-41
--------------.j
•
•
MCM10139/MCM10539
RECOMMENDED PROGRAMMING PROCEDURE*
The MCM10139 is shipped with all bits at logical "0" (low). To write logical "1s", proceed as follows.
MANUAL (See Figure 1)
AUTOMATIC (See Figure 2)
Step 1
Step 1
Connect VEE (Pin 8) to -5.2 V and VCC (Pin 16) to
0.0 V. Address the word to be programmed by applying
-1.2 to -0.6 volts for' logic "1" and -5.2 to -4.2 volts for a logic
"0" to the appropriate address inputs.
to 0.0 volts. Apply the proper address data and raise
Raise Vec (Pin 16) to +6.8 volts.
Step 3
After VCC has stabilized at +6.8 volts (including any
Vee
(Pin 16) to +6.8 volts.
Step 2
Step 2
Connect VEE (Pin 8) to -5.2 volts and VCC (Pin 16)
After a minimum delay of 100 jJ.S and a maximum delay
of '.0 ms, apply a 2.5 mA current pulse to the first bit to
be programmed (0.1 .. PW" 1 msl.
ringing which may be present on the
Vee
Step 3
Repeat Step 2 for each bit of the selected word specified
as a logic "'''. ~Program only one bit at a time. The delay
between output programming pulses should be equal to or less than
line), apply
a current pulse of 2.5 rnA to the output pin corresponding to the
bit to be programmed to a logic "1".
1.0 ms.l
Step 4
Return VCC to 0.0 Volts.
Step 4
CAUTION
To prevent excessive chip temperature rise, Vee should not
be allowed to remain at +6.8 volts for more than 1 second.
After all the desired bits of the selected word have been
programmed,
change
address
data
and
repeat
Steps 2 and 3.
Verify that the selected bit has programmed by con·
necting a 460 Sl resistor to -5.2 volts and measuring
the voltage at the output pin. If a logic "1" is not detected at the
NOTE: If all the maximum times listed above are maintained, the
entire memory will program in less than 1 second. Therefore, it
would be permissible for Vee to remain at +6.8 volts during the
entire programming time.
output, the procedure should be repeated once, During verification
VIH should be -1.0 to -0.6 volts.
Step 5
Step 5
Step 6
After stepping through all address words, return V CC to
0.0 volts and verify that each bit has programmed. If one
or more bits have· not programmed, repeat the entire procedure
once. During verification VIH should be -1.0 to -0.6 volts.
If verification is positive, proceed to the next bit to
be programmed.
*NOTE: For devices that program incorrectly-return serialized units with individual truth tables. Noncompliance voids warranty .
PROGRAMMING SPECIFICATIONS
Characteristic
Power Supply Voltage
To Program
To Verify
Programming Supply Current
Symbol
Min
Limits
Typ
VEE
VCCP
VCCV
ICCp
VIH Program
VIH Verify
VIL
-5.46
+6.04
0
-5.2
+6.8
0
-
200
-1.2
-1.0
-5.2
Max
Units
-4.94
+7.56
0
600
-0.6
-0.6
-4.2
1.0
Vdc
Vdc
Vdc
-
-
-
Output Programming Current
lOp
2.0
2.5
Output Program Pulse Width
to
0.5
Output Pulse Rise Time
Programming Pulse Delay (1)
Following V CC change
Between Output Pulses
-
-
-
3.0
1.0
10
td
td 1
0.1
0.01
-
1.0
1.0
Address Voltage
Logical "1"
Logical "0"
Maximum Time a~ V CC = V CCP
NOTE 1. Maximum is specified to minimize the amount of time
Vee is at
4-42
+6.8 volts.
mA
Vdc
Vdc
Vdc
sec
mAdc
ms
,",S
ms
ms
Conditions
VCC = +6.8 Vdc
®
MOTOROLA
PIN ASSIGNMENT
MCM10149/MCM10549
256 X 4-BIT PROGRAMMABLE
READ-ONLY MEMORY
The MCM10149/1 0549 is a 256-word X 4-bit
field programmable read only memory (PROM).
Prior to programming, all stored bits are at logic
1 (high) levels. The logic state of each bit
can then be changed by on-chip programming
circuitry. The memory has a single negative
logic chip enable. When the chip is disabled
(CS = high), all outputs are forced to a logic
(low).
o
•
Typical Address Access Time of 20 ns
•
Typical Chip Select Access Time of 8.0 ns
•
50
•
Power Dissipation (540 mW typ @ 25 0 C)
Decreases with Increasing Temperature
kn
Input Pulldown Resistors
on All Inputs
32)( 32
Input
Decoder
Array and
Associated Drivers
L SUFFIX
CERAMIC PACKAGE
CASE 620
Output
A39
-c>---~ Decoder
r----+----
~13---------------------~~----~~----~+-----~
F SUFFIX
CERAMIC PACKAGE
CASE 650
4-43
11
12
14
15
03
02
01
00
•
MCM10149/MCM10549
ELECTRICAL CHARACTERISTICS
-SSoC
Characteristic
Power Supply Drain Current
Input Current High
_55°C and
+125 0
ooc
+7SoC
+2SoC
+12SoC
Symbol Min Max Min Max Min Max Min Max Min Max
125
130
125
140
135
lEE
mAdc
[Lo5
I'Adc
linH
450
265
265
265
Unit
C test values apply to MC105xx devices only.
SWITCHING CHARACTERISTICS (Note 1)
Characteristics
Read Mode
Chip Select Access Time
Chip Select Recovery Time
Address Access Time
Rise and Fall Time
Symbol
MCM10149
MCM10549
TA - 0 to +75 0 C,
VEE = -S.2 Vdc ± 5%
Min
Max
TA - -55 to +125 0 C,
VEE = -5.2 Vdc ±5%
Min
Max
tACS
tRCS
tAA
2.0
2.0
7.0
10
10
25
tr,tf
1.5
7.0
Unit
ns
··
·
*
*
*
See Note 1.
.
*
ns
pF
Output Capacitance
ein
Cout
-
5.0
8.0
Measured between 20%
and 80% points.
Capacitance
Input Capacitance
Conditions
Measured from 50% of
input to 50% of output.
-
5.0
8.0
-
Measured with a pulse
technique,
NOTES. 1. Test CirCUit characterIStics. RT 50 n, MCM10149, 100 n, MCM10549.
CL .;;; 5.0 pF (including jig and stray capacitance)
Oelay should be derated 30 ps/pF for capacitive load up to 50 pF
2. The maximum Address Access Time is guaranteed to be the Worst-Case Bit in the Memory.
3. For proper use of MECL Memories in a system environment, consult MECL System Design Handbook.
4. VCP = VCC = Gnd for normal operation.
*To be determined; contact your Motorola representative for up-to-date information.
PROGRAMMING THE MCM10149
During programming of the MCM10149, input
pins 7, 9, and 10 are addressed with standard
M ECl 10K logic levels. However, during programming input pins 2, 3, 4, 5, ·and 6 are addressed
with 0 V .;; VIH .;; + 0.25 V and VEE';; Vll';;
-3.0 V. It should be stressed that this deviation
from standard input levels is required only during
the programming mode. During normal operation,
standard M EC l 10,000 input levels must be used.
With these requirements met, and with VCP =
VCC = 0 V and VEE = - 5.2 V ± 5%, the address
is set up. After a minimum of 100 ns delay, VCP
(pin 1) is ramped up to +12 V ± 0.5 V (total
Coincident with,
NOTE:
or at some delay after the
V CP pulse has reached its 100% level, the desired
bit to be fused can be selected. This is done by
taking the corresonding output pin to a voltage
of + 2.85 V ± 5%. It is to be noted that only one bit
is to be fused at a time. The other three unselected
outputs should remain terminated through their
50 ohm load resistor (100 ohm for MCM10549)
to -2.0 V. Current into the selected output is
5 mA maximum,
After the bit select pulse has been applied to
the appropriate output, the fusing current is
sourced out of the chip select pin 13. The 0% to
100% rise time of this current pulse should be
250 ns max. Its pulse width should be greater than
100 IlS. Pulse magnitude is 50 mA ±5.0 mAo The
voltage clamp on this current source is to
be -6.0 V.
voltage VCP to VEE is now 17.2 V, + 12 V [-5.2 Vl). The rise time of this VCP voltage
pulse should be in the 1 -10 Ils range, while its
pulse width (t w 1) should be greater than 100 Ils
but less than 1 ms. The V CP supply current at + 12
V will be approximately 525 mA while current
drain from V CC will be approximately 175 mAo A
current limit should therefore be set on both of
these supplies. The current limit on the VCP
supply should be set at 700 mA while the V CC supply should be limited to 250 mAo It should be
noted that the VEE supply must be capable of
sinking the combined current of the VCC and
VCP supplies while maintaining a voltage of
-5.2 V ± 5%.
t
t
After the fusing current source has returned
mA, the bit select pulse is returned to it initial
level, i.e., the output is returned through its load
to -2.0 V. Thereafter, VCP is returned to 0 V.
Strobing of the outputs to determine success in
programming
should
occur no sooner than
100 ns after VCP has returned to 0 V. The remaining bits are programmed in a similar fashion.
o
For devices that program incorrectly, return serialized units with individual truth tables.
Non compliance voids warranty.
4-44
MCM10149/MCM10549
PROGRAMMING SPECIFICATIONS
The following timing diagrams and fusing
information represent programming specifications
for the MCM10149.
Vee -'- Pin 16 - 0 V
VEE"" Pin 8 ""' -5.2 V ±5%
Definitions and values of timing symbols are
as follows.
Symbol
Definition
Value
+12 V
;;. 1 !ls
tr1
Rise Time,
Programming Voltage
0 V
tw1
Pulse Width,
Programming Voltage
+2.85 V
tD1
Delay Time,
Programming Voltage
Pulse to Bit
tw2
Pulse Width, Bit Select
;;. 100!ls
tD2
Delay Time, Bit Select
Pulse to Programming
Voltage Pulse
;;'0
tD3
Delay Time, Bit Select
Pulse to Programming
;;. 1 !lS
tr3
Rise Time, Programming
Current Pulse
All addressing must be done 100 ns prior to the
tw3
beginning of the VCP pulse, i.e., VCP = 0 V.
Likewise, strobing of the outputs to determine
success in programming should occur no sooner
Pulse Width,
Programming
tD4
Delay Time,
Programming Current
Pulse to Bit
Select Pulse
'05V
VCP - Pm 1
t"J
tw' __
! 5%
Selected Output Open
Pin (11, 12, 140r 1!:i)
;;. 100!ls
<
1 ms
;;'0
Select Pu Ise
to,
50 rnA
!5mA
Chip Select Pin 13
0 mA---+J
Cu rrent Pu Ise
The timing diagram is shown for programming
one bit. Note that only one bit is blown at a time.
250 ns max
;;. 100!ls
Current Pulse
than 100 ns after VCP returns to 0 V.
Note that the fusing current is defined as
a positive current out of the chip select, pin 13.
A programming duty cycle of .;; 15% is to be
observed.
4-45
;;. 1 !ls
II
•
MCM10149/MCM10549
MANUAL PROGRAMMING CIRCUIT
+5V
+5 V
~05~F
12k
J201~s
....--......,
+5 V
Delay
1
Verify
1/6 MC7406
~2k
~F
0.005
Q
1/2
MC8602
680""l....-.r"
Enable
Current
Pulsa
1/2
MC8602
Cp Q
..r--L.
>100~s
CD
Program
Program '-----,---'
Enable
+5 V
+5 V
~
lN914
-5.2 V
(-6 V Clamp)
510
510
lN914
or EQuiv.
100
-5.2 V
-12 V
+5 V
+12.5 V
r-----1~_O+5
1/4
MC7438
160
61
n,
1/2W
240
1/4 MC7438
180
180n,1/2W
lN914
..
+5 V o-~---.---t*""--~---
~_ 0.1 ~F
13
VCP
7
CS
A7
1.0 k
-5.2 V
1.0 k
-6.2 V
1.0 k
-6.2 V
11
5
A6
03
6
A5
12
10
02
A4
1.0 k
-5.2 V
1.0 k
-6.2 V
1.0 k
-5.2 V
1.0 k
-5.2 V
1.0 k
-5.2 V
9
A3
680
-5.2 V
MCM101491
10549
14
01
3
680
-6.2 V
A2
2
15
Al
C
Rotary SW
DO
4
AO
16
446
680
-6.2 V
V
Memory Boards
III
I,,;
5-1
•
5-2
®
MOTOROLA
MMSII02
Advance Information
ADD-ON MEMORY CARD FOR THE LSI-"
FAMILY
The MMSll 02 is a dual height (5.187" x 8.94") add-on memory card for the LSI-ll family of computers.
It is compatible with the LSI-ll 12 and LSI-ll processors as well as the PDP 11 V03 computer systems. It
incorporates byte parity storage as well as generation and detection logic.
Specification Highlights
INTERFACE
LSI-ll, "Q" Bus-Plus.
CAPACITY
BK words x 16 bits, 16K words x 16 bits, 32K words x 16 bits.
PARITY
Optional on-board storage, generation and detection logic for both upper and lower byte.
Parity option does not degrade access times.
SPEED
The MMSl J02-3X has a read access time under 300 ns. Read access time is defined here
as the time from receipt of SYNC H to the transmission of RPLY H, assuming that the
SYNC H to DIN H time is no greater than 160 ns.
ADDRESSING
Switch-selectable, to start on any 4K word boundary between 0 and 12BK.
liD PAGE USE
Three switches allow anyone of the lowest three kilowords of the 1/0 page to be used
as ReadlWrite memory.
BATIERY BACKUP Jumper selectable; allows the MMSll02 to be operated from a separate uninterrupted
power source (+5 BBU and + 12 BBU).
REFRESH
Implemented internal to the MMSll02 and totally transparent to the system.
5-3
•
MMS1102
MMSll02-XX ORDERING INFORMATION
Storage Capacity
Part Number
(With Parity and Controller)
Part Number
(No Parity)
16 Kilobytes
MMSll02-31PC
MMSll02-31
32 Kilobytes
MMSll02-32PC
MMSll02-32
64 Kilobytes
MMSll02-34PC
MMSll02-34
MMSll02-3X - AC OPk:RATING CHARACTERISTICS
Write Acce•• (ns)
Read Acce•• (n.)
Worst Case
Typical
Worst Case
Typical
Acee•• Time'
250
300
125
175
Cycle Time"
470
500
350
Refresh Latency'"
175
400
175
400
400
'As measured from receipt of RSYNC H to transmission of TRPLY H.
"This is the reCiprocal of the maximum continuous transfer rate, assuming no refresh interference.
*"Occurs approximately once every 16 microseconds.
MMS1102 POWER REQUIREMENTS
Current Requirement. (mA)
Standby
Nominal Voltage
Min
Max
Typical
+5 VDC (Total)
4.75
5.25
725
925'
Active
Worst
Case
Worst
Case
Input Pin.
775
1000'
850
1100"
AA2. BA2
AD2. BD2
Typical
800
1000'
+12 VDC
11.40
12.60
100
150
250
400
+5 VDC (BBU)
4.75
5.25
400
500
450
550
AV1**
+12 VDC (BBU)
11.40
12.60
100
150
250
400
AS1 ***
·Parity version only.
"In systems without battery backup this voltage is obtained from the regular +5 V rail via an on-board jumper.
"'The +12 V supply requirement can be met via an on-board jumper from the regular +12 V rail.
MMSll02 BACKPLANE CONNECTOR PIN ASSIGNMENT
Side
Pin
A
B
C
0
E
F
H
J
K
L
M
N
P
R
S
T
U
V
B
A
Row
1
-
+5 V
-
-
BAD16 L"
BAD17 L
GND
+12 V
BDOUT L
BRPLY L
BDIN L
BSYNC L
BWTBTL
-
GND
},
GND
1
2
GND
}
,
-
BBS7 L
BREF L
+12 V BBU
GND
BDMGI L } " .
BDMGO L
+5 V BBU
+5 V
-
-
-
-
8DCOK H
-
;AKIL }.,.
BIAKO L
BDALO L
BDAL 1 L
GND
-
GND
-
+5V
'Must be hardwired on backplane or damage to MOS devices may result.
"Or PRTYER or PRTYCK.
"'Hardwired on MMSll02.
5-4
2
GND
+12 V
BDAL 2
BDAL 3
BDAL 4
BDAL 5
BDAL 6
BDAL 7
BDAL 8
BDAL 9
L
L
L
L
L
L
L
L
BDAL 10
BDAL 11
BDAL 12
BDAL 13
BDAL 14
BDAL 15
L
L
L
L
L
L
®
MOTOROLA
MMSl122
Product Previe,",
I
ADD-IN MEMORY CARD FOR THE LSI-"
FAMILY
The MMS1122 is a dual height (5.19" x 8.94") add-on memory card for the LSI-11 family of computers. It is compatible with
LSI-ll, LSI-11/2, and LSI-l1/23 processors as well as PDP-11V03' computer systems. It utilizes MCM4132L 32K RAM
modules.
FEATURES
• Capacity of·32K Words, Each 16-Bits Long
• Effective Capacity is Switch Selectable at any 1K Word Increment
• Addressing is Switch Selectable to Start on Any 1K Word Boundary
From 0 to 127K
• Read Access Time of 300 ns (max.)
• Cycle Time 500 ns (max.)
Refresh Implemented Internal to the Card (Transparent to the
System). On-Board Jumpers Permit Synchronization of Refresh if
Desired.
•
Refresh and~
Address.,
Memory Array
Multiplexer
• Jumper Selectable Battery Backup Provisions Allow Use of Separate
Power Source
• LSI-11 (O-Bus and O-Bus Plus) Interface Compatible
I
ORDERING INFORMATION
User Option
Switches/
MMSl122N3032
L
Basic Part
l=r~
No Parity
Number
Speed
(300 ns Accessl
vi
«
MA1-MA14
r;=--
Jumpers
IL---
Uf-
Jl£
~
I
Size
(32K Wordl
-5 Volt
Generator and
Battery Backup
Circuitry
0
6
f-
BREFL (Optional!
+ 12 V+5 V-5 V
'"
f=
«
Memory Control
c
«
0
0
JI
'5
--,II
«0:;
i"
0
mV
00
BREFL BDOUTL
BRPLYL
r
Multiplexed
Address/ Data
Buffers
Control/ ~~~NNLCL
Status ~~ST7tL
Buffers BDCOKH
SIMILAR PRODUCTS
Other Add-In memory cards for the LSI-11 family include the
MMSll02 and MMS1132.
ENVIRONMENTAL RATINGS
Symbol
Rating
Operating Temperature
TA
Tst9
RH
Storage Temperature
Relative Humidity IWithout Condensation I
---
'PDP is a trademark of Digital Equipment Corporation.
5-5
Limit
o to
+50
-40 to +80
5 to 90
Units
'C
'C
%
•
•
MMS1122
PHYSICAL DIMENSIONS
Dimension
Inches
S.94
5.19
0.082
0.325
0.060
Millimeters
Width
227.08
131.75
Height
PC Board Thickness
1.575
0.826
1.524
Clearance Required (Component Side)·
Clearance Required ISolder Sidel'
'Measured from surface of PC Board.
POWER REQUIREMENTS 1+5 Voltsl
Pin
Mode
Active
Standby
Battery Backup
Current Required
Units
Typical Worst-Case
"
"
0.775
0.S50
Adc
0.725
0.800
Adc
AVl
0.400
0.500
Adc
POWER REQUIREMENTS 1+ 12 Voltsl
Pin
Mode
Current Required
Units
Typical Worst-Ca ..
'"
'"
0.250
Standby
0.100
0.400
0.150
Adc
Adc
Battery Backup
ASl
0.100
0.150
Adc
Active
"AA2, BA2, BV1, AVl IJumper option allows all +5 V current to be supplied by AA2, BA2, and BVl if battery backup operation is not required!.
"'AD2, BD2, ASl IJumper option allows all + 12 V current to be supplied by AD2 and BD2 if battery backup operation is not requiredl.
AC OPERATING CHARACTERISTICS
Characteristic
Cycle Time -
Read or Write
Access Time - Read
Write
Typical
Worst-Ca..
500
525
250
125
300
175
Unit
ns
ns
BACKPLANE CONNECTOR PIN ASSIGNMENT
Pin
AA2
ACl
AC2
ADl
AD2
AE2
AF2
AH2
AJl
AJ2
AKl
Symbol
+5V
BDAL 1161
GND
BDAL 1171
+12 V
BDOUT L
BRPLY L
BDIN L
GND
BSYNC L
INote 11
Pin
AL1
AK2
AMl
AM2
AN2
AP2
ARl
AR2
AS2
AS1
ATl
Symbol
INote 11
BWTBT L
GND
BIAKI L
BIAKO L
BBS7 L
BREF L
BDMGI L
BDMGO L
+12 V BBU2
GND
Pin
Symbol
Pin
AU2
AV1
AV2
BAl
BA2
BCl
BC2
BDl
BD2
BEl
BE2
BDAL IOJ
+5 V BBU2
BDAL III
BDCOK H
+5V
BDAL 1181
GND
BDAL 1191
+12 V
BDAL 1201
BDAL 121
BFl
BF2
BH2
BJl
BJ2
BKl
BLl
BK2
BL2
BMl
BM2
Symbol
BDAL 1211
BDAL .131
BDAL 141
GND
BDAL 151
INote 31
INote 31
BDAL 161
BDAL 171
GND
BDAL lSI
Pin
Symbol
BN2
BP2
BR2
BS2
BTl
BT2
BU2
BVl
BV2
BDAL
BDAL
BDAL
BDAL
GND
BDAL
BDAL
+5V
BDAL
BV2
BDAL 1151
191
1101
1111
1121
(3)
1141
1151
Notes: 111 AK 1 and ALl normally connected together at backplane. User jumper option allows negative 5 V supply to be connected through
ALl if desired.
121 + 12 V BBU and +5 V BBU may be driven by normal +5 V and + 12 V if desired.
131 User jumper options allow BKl and BL 1 to be used for synchronous refresh.
5-6
®
MMSl132
MOTOROLA
Product Previe'W'
ADD-IN MEMORY CARD FOR THE LSI-11 FAMILY
The MMSl132 is a dual height (5.19" x 8.94"1 add-on memory card for the LSI-ll family of computers. It is compatible with
LSI-ll, LSI-11/2, and LSI-11/23 processors as well as PDP-llV03' computer systems. It utilizes MCM6633L 32K RAM or
MCM6665L 64K RAM chips.
FEATURES
• Capacity of up to128K Words, Each 16-Bits Long
Without Parity, 18-Bits with Parity
• Effective Capacity is Switch Selectable at any 1K Word Increment
• Addressing is Switch Selectable to Start on Any 1K Word Boundary
From 0 to 127K
Refresh and~
Address'
• Optional Parity and On-Board Parity Controller
Multiplexer
l
Memory Array
• Read Access Time of 300 ns (max.1
• Cycle Time 500 ns (max. 1
Refresh Implemented Internal to the Card (Transparent to the
System!. On-Board Jumpers Permit Synchronization of Refresh if
Desired.
•
• Single +5 V Power Supply
• Jumper Selectable Battery Backup Provisions Allow Use of Separate
Power Source
-=-
User Option
Switches/
• LSI-ll (Q-Bus and Q-Bus Plusl Interface Compatible
en«
MA1-MA16
Jumpers
~
I
Jl1
L-
BREFL IOptionali
L
Basic Part
Number
~
P
Option
L P I Parity
No Paritv
N
X
I
Speed
Z2
Z,
Zo
0
0
1
3
6
2
2
4
8
BREFL
Capacity
32K Words
64K Words
128K Words
0
6
>-
«
0
c
ORDERING INFORMATION
MMSl132 X 3 Z2Z1Z0
"~
t=
«
Memory Control
IBDOUTL
BRPLYL
BDINL
Control I BSYNCL
Status
BWTBL
Buffers BBS7L
BDCOKH
0
--,"
«0;
06
CDv
.-
"g
~
is
Multiplexed
Addressl Data
Buffers
1300 ns Accessl
Note: K=1024, Word = 16 BitsW/O, 18 Bits With Parity
SIMILAR PRODUCTS
Other Add-In memory cards for the LSI-ll family include the
MMSll02 and MMSl122.
ENVIRONMENTAL RATINGS
Rating
Operating Temperature
Storage Temperature
Relative Humidity (Without Condensation)
'PDP is a trademark of Digital Equipment Corporation.
5-7
Symbol
Lim~
TA
Tst9
RH
o to +50
-40 to +80
5 to 90
Units
'C
'C
%
•
•
MMS1132
PHYSICAL DIMENSIONS
Dimension
~-
Millimeters
Inches
227.08
131.75
1.575
8.94
---
Height
PC Board Thickness
5.19
0.082
Clearance Required (Component Side)·
0.826
0.325
Clearance Required ISolder Sidel'
1.524
0.080
'Measured from surface of PC Boord.
POWER REQUIREMENTS 1+5 V Only Requiredl
Total Required Current
Mode
Pins
Active
Standby
Battery Backup
32K Word Capacity
Typical
Worst-Case
1.375
0.965
1.80
AA2, BA2, BV1, AV1"
AVl
0.640
AA2, BA2, BV1, AV1"
1.15
0.86
64 or 128K Word Ca»llcity Units
Typical
Worst-Case
1.50
1.95
Adc
1.05
1.25
Adc
0.70
0.93
Adc
,. Jumper option allows all current to be supplied by AA2, BA2, and BVl if battery backup operation is not required.
AC OPERATING CHARACTERISTICS
Characteristic
Cycle Time - Read
Write
Access Time -
Read
Write
Typical
Worst-Case
470
350
250
125
500
400
300
175
ns
ns
BACKPLANE CONNECTOR PIN ASSIGNMENT
Pin
AA2
ACl
AC2
ADl
AD2
AE2
AF2
AH2
AJl
AJ2
AKl
Symbol
+5V
BDAL 1161
GND
BDAL 1171
+12 V
BDOUT L
BRPLY L
BDIN L
GND
BSYNC L
INote 11
Pin
Symbol
All INote 11
AK2 BWTBT L
AM1 GND
AM2 BIAKI L
AN2 BIAKO L
AP2 BBS7 L
AR1 BREF L
AR2 BDMGI L
AS2 BDMGO L
AS1 + 12 V BBU2
ATl GND
Pin
Symbol
AU2
AVl
AV2
BAl
BA2
BCl
BC2
BDl
BD2
BEl
BE2
BOAL 101
+5VBBU2
BDAL 111
BDCOK H
+5 V
BDAL 1181
GND
BDAL 1191
+12 V
BDAL 1201
BDAL 121
-
Pin
BFl
BF2
BH2
BJl
BJ2
BKl
BLl
BK2
BL2
BMl
BM2
Notes. 111 +5 V BBU may be driven by normal +5 V If deslfed.
121 User jumper options allow BK1 and BLl to be used for synchronous refresh .
5-8
Symbol
BDAL 1211
BDAL 131
BDAL 141
GND
BDAL 151
INote 31
INote 31
BDAL 161
BDAL 171
GND
BDAL 181
Pin
Units
Symbol
BN2
BP2
BR2
BS2
BTl
BT2
BU2
BVl
BV2
BDAL
BDAL
BDAL
BDAL
GND
BDAL
BDAL
+5V
BDAL
191
1101
1111
1121
BV2
BDAL 1151
131
1141
1151
®
MOTOROLA
MMSll17
Advance Infor:rn.ation
PDP-11* UNIBUS* COMPATIBLE RANDOM ACCESS MEMORIES, UP TO 128 KILOBYTES OF
STORAGE CAPACITY PLUS OPTIONAL PARITY CONTROLLER ON A SINGLE CARD
The MMS1117 family of memory systems offers owners of PCP-11* computers an opportunity to easily add
storage capacity and parity features to their system. Each member of the family is contained on asingle plugin circuit card that interfaces mechanically and electrically with the following models of UNIBUS' PDP-11*
processors: 11/04, 11/05, 11110, 11/34, 11135, 11/40, 11/45, 11/50, 11/55, and 11/60. It plugs into a single hex
SPC slot in any of the following backplanes: 0011-8, DD11-C, '0011-D and DD11-P.
The MMS1117 can provide up to 128K 8-bit bytes of main memory on a single module. Quick address
select changes are possible via onboard switches. In addition, 1 or 2 kilowords of liD page can selectively be
made available for random access storage. Optional parity as well as full parity generation, detection, and
exception control circuits can be provided on the same card with the memory. No additional bus loading is
imposed on the system by the addition of the fully compatible parity controller option.
MMS1117 FEATURES
•
High Density
•
Fully UNIBUS Compatible
•
Low Cost
•
High Reliability
•
Fast Access and Cycle Times
•
One UNIBUS Load
•
LowPower
*Trademark of Digital Equipment Corporation
5-9
•
•
MMS1117
MMSll17 OPTION DESIGNATOR SUFFIX
Total Storage Capacity (in Kilobytes)
Typical Read
Access Time
Parity Options
32K
64K
96K
128K
290 ns
Parity + Controller
-34-PC
-34-P
-34
-36-PC
-36-P
-36
-3S-PC
-38-P
-38
No Parity
-32-PC
-32-P
-.12
360 ns
Parity + Controller
Parity Data Only
No Parity
-42-PC
-42-P
-42
-44-PC
-44-P
-44
-46-PC
-46-P
-46
-48-PC
-48-P
-48
390 ns
Parity + Controller
-52-PC
-52-P
-52
-54-PC
-54-P
-54
-56-PC
-56-P
-56
-58-PC
-58-P
-58
Parity Data Only
Parity Data Only
No Parity
ACCESS AND CYCLE TIMES
Cycle
R~ad
Write
Option Designator
Suffix
Typical
Worst Case
Typical
Worst Case
Typical
Worst Case
-3X
105
125
290
315
375
390
-4X
115
135
360
390
480
500
-5X
115
135
390
420
560
585
MMSll17 POWER REQUIREMENTS
Current Requirements
Standby-Typ/WC
Voltage Tolerance
Active-TVp/WC
Nominai Voltage
Min
Max
(Amps)
(Amps)
Input Pins
+5 Vdc
4.75
5.25
2_0/2.5
2.0/2.5
DA2. EA2, F A2
+15 Vdc
15
20
0.15/0.20
0.35/0.70
AV1,AR1,CE1,CUl
-15 Vdc
-7.0
-20
0.015/0.030
0.015/0_030
FB2
MMSll17 BACK PLANE CONNECTOR PIN ASSIGNMENT
Row
Side
A
1
1
2
Pin A
r ••
[
Pin B
Pine
Gnd
Gnd
Pin 0
+5BB
Pin E
*SSyn
2
1
..
1
Gnd
Gnd
D15
A17
A15
'PA DE '''VDD
D14
MSyn
A16
D13
A02
Cl
D12
AOl
AOO
Pin J
Dl0
D09
r ••
..
Pin L
D08
PinM
D07
r ••
D04
L ••
Init
SSyn
CO
A14
A13
'Pl
Pin P
'PO
D05
r ••
Al0
Pin R
"'VDD
DOl
l ••
A09
DCLO
Pin U
Pin V
"'VDD
Gnd
2
+5 V
r ••
AOS
A07
PB
DOO
Gnd
D03
u*VOD
D02
A06
A04
D06
A05
A03
Gnd
Options for use wIth External Panty Controller.
**Grant Continuity Jumpers
***VbD is any voltage between + 15 Vdc and +20 Vdc on anyone of the four listed pins.
5-10
L ..
Gnd
All
Pin N
Gnd
1
+5 V
A12
Gnd
Pin K
Pin T
2
-15V
PA
Dl1
PinS
.
2
+5 V
Pin F
Pin H
1
F
E
0
C
[J
2
Gnd
Gnd
®
MOTOROLA
MMS1119
Advance Infor:rn.ation
PDP-11* MODIFIED UNIBUS*/EXTENDED UNIBUS COMPATIBLE MEMORY SYSTEM
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Uses 16K or 64K Dynamic RAM Chips
Available in 64K, 96K, 128K, 2OOK, and 512K Word Capacities
Read Access Time Typically 300 ns (Measured Inside Buffers)
Cycle Times as Low as 390 ns Typical
Two Speed Options Available
Worst-Case AC Limits Specified at Card Edge
On-Board Parity and Parity Controller Standard
Also Available Without Parity
Starting Address Configurable at Any 4K Boundary
Optional Selection of 1/0 Page Size; 2K, 4K, or 8K Words
Automatic Internal Refresh
Provisions for External Refresh Control
Battery Backup Capability Standard
Single 5-Volt Power Supply Required for 200K and 512K Word
Versions
ORDERING INFORMATION
M
M
5
1
1
1 9
Z1
Zo
I
I
Basic Product
Designation
I
I
y
I Read Access I
I Parity + Controller I
I No Parity""
I
3
I :nJ ns ITypl I
I 350 ns ITypl I
x I Option
P
N
4
Z2
0
0
1
2
5
•• Available on special order
Z1
Zo
6
9
4
2
6
8
5
6
Capacity
64K Words
96K Words
128K Words
256K Words
612K Words
NOTE: K= 1024, Word = 16 Bits WID, 18 Bits With Parity
"PDP-" and UNIBUS are trademarks of Digital Equipment Corporation
5-11
•
•
MMS1119
ABSOLUTE MAXIMUM RATINGS
Limit
Symbol
Rating
VDD
Supply Voltage (Relative to Ground)
Input Voltage (Any input relative to Ground)
Min
Max
-0.3
20.0
Units
VCC
-0.3
7.0
VBB
-20.0
+0.3
Vdc
Vin
-0.7
+5.5
Vdc
NOTES: 1. Permanent damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended Operating Conditions.
2. Permanent damage may also occur if VDD is applied for more than one second while VBB is outside its Recommended Operating
Range.
ENVIRONMENTAL RATINGS
Symbol
Limit
Operating Temperature
Rating
TA
o to +70
Units
·C
Storage Tempereture
Tstg
RH
-40 to +85
·C
Oto 90
%
Relative Humidity (Without Condensation)
RECOMMENDED DC OPERATION CONDITIONS
Symbol
Parameter
Supply Voltage
-Nominal + 15 V or nominal + 12 V, pin ARI
VDD
- Nominal + 6 V, pins AA2, BA2, CA2
-Nominal +5V BBU, pin BDI
-Nominal-15Vornominal-12V,pinASl
VCC
VCC/BBU
VBB
Umit
Min
Max
14.50
11.40
4.75
4.75
-7.00
16.50
12.60
5.25
5.25
-20.00
Units
Nota
Vdc
1,3
2
3
3,4
NOTES: 1. + 16 V or + 12 V is jumper selectable on all modules populated with 16K RAMs.
2. Pins AA2, BA2, and CA2 are connected together on the MMSl119.
3. These voltages must be present on cards populated with 16K RAMs if Battery Backup is required. Only VCC/BBU need be
present for cards populated with 32K or 64K RAMs.
4. VDD and VBB not required for cards populated with 32K or 64K RAMs.
DC OPERATING CHARACTERISTICS (o·C< TA < 70·C)
Characteri8lic
Supply Current - Nominal + 15 V or + 12 V Supply
CapecitY
IK Wordsl
64,96,128
64,96,128
Supply Current - Nominal + 5 V Supply and + 5 V BBU 64,96,128
Supply Current - Nominal + 5 V BBU
64,96,126
256
+ 6 V BBU·
256
+5 V Supply and +5 V BBU
512
+ 15 V BBU
512
-15 V or -12 V Supply
64,96,128
Supply Current - Nominal +5 V Supply and +5 V BBU
Supply Current '- Nominal
Mode
Symbol
Active
Standby
Active/Standby
100
BBU
ICC
Active/ Standby
ICC
100
100
BBU
ICC
Active/Standby
ICC
BBU
ICC
All
IBB
Umit
Typ
Max
-
0.25
0.50
Adc
1,2
0.16
0.30
Ac;lc
1,2
3.30
3.90
Adc
1,2
1.10
1.30
Adc
1
3.30
4.60
Adc
1
1.00
1.50
Adc
1
3.BO
5.1
Adc
1
1.50
2.00
Adc
1
12
20
mAde
1,2
15
50
,.Adc
3
-1.0
-50
"Adc
3
Min
Units
Notes
Logic "I" Input Current - Any Input, VIH=2.4 Vde
Any
All
IIH
Logic "0" Input Current - Any Input, VIL -0.4 Vde
Any
All
IlL
-
Logic "I" Leakage Current - Any Output,
V Bus=4.0 Vdc
Any
All
VOH
-
20
100
,.Adc
3
Logic "0" Output Voltage - Any Output, IOL = 50 mAde
Any
All
VOL
-
0.40
0.70
Vde
3
Input Threshold Voltage - Any Input High LogiC State
VILH
1.BO
2.26
2.50
Vdc
Input Threshold Voltage - Any Input Low Logic State
VIHL
1.06
1.30
1.55
Vde
Supply Current - Nominal
Supply Current - Nominal
Supply Current - Nominal
NOTES: 1. Active Mode= Memory accesses at maximum continuous rates; Standby Mode= Internal Refresh Cycles only; Battery Backup
(BBU) = Standby Mode with + 5 V applied only through Pin BD1.
2. + 151 + 12 V and -15/ -12 V supplies not required for products populated with 64K RAMs.
3. Negative sign = Current out of pin. MiniMax Limits refer to absolute values of current.
5-12
MMS1119
AC OPERATING CONDITIONS
Parameter
Um~
Symbol
Min
Max
tAH
tAS
tPH
25
75
-
-
0
tDHW
40
-
tDSW
15
-
Address Hold Time - MSYN' to A <0:21> Invalid
Address Setup Time - A <0:21> Valid to MSYN'
Processor Handshake Time - SSYN' to MSYN t
Data Hold Time (Write Cycle/DATal - MSYN' to 0 <0:15> Invalid
Data Setup Time (Write Cycle/DATal - 0 <0:15> Valid to MSYNI
Un~
Note
ns
ns
ns
ns
ns
1
1
1,2
1
-
1
NOTES: 1. All timing is referenced at card edge. Operation is assumed to be in a properly terminated backplane, with memory not busy and no
refresh arbitration.
2. Assumes handshaking occurs immediately.
AC OPERATING CHARACTERISTICS (0·C:sTA:S70·CI
Symbol
MMS1119X3XXX
Min Typ Max
Un~
Note
Cycle Time - Read (DATil Cycle
tRCYC
390
360
-
440
425
-
ns
1
Read Access Time - MSYN I to SSYN I
Data Hold Time - Read (DATIl
Cycle MSYNt to Data Invalid
Data Setup Time - Read (DATil
Cycle 0<0:15> Valid to SSYNI
tRACC
-
330
360
-
380
430
ns
1
tDH
70
-
-
70
-
-
ns
1
Characteristics
MMS1119X4XXX
Min Typ Max
tDS
0
-
-
0
-
-
ns
1
Memory Handshake Time - Read IDATII
or Write (DATal Cycle MSYN.t to SSYN I
tMH
-
-
75
-
-
75
ns
1
Write Access Time - MSYN' to SSYN'
Cycle Time - Write (DATal Cycle
tWACC
tWCYC
-
125
165
-
125
165
340
-
-
440
-
-
ns
ns
1
1
NOTES: 1. All timing is referenced at card edge. Operation is assumed to be in a properly terminated backplane, with memory not busy and no
refresh arbitration.
2. Assumes handshaking occurs immediately.
WRITE CYCLE TIMING
Bus A <0:21> L _~"'-_-+
Bus D <0:16> L
____+-_-I'''''..L..<'''''<'-L..L....<'''''<-L
----;:::=l=~r--+----<:==::>--
Bus MSYN L
Bus SSYN L ----+-+-~
___...Y-+----
tDH
i-----tWCYC:-----I
READ CYCLE TIMING
t'AS
Bus A <0:21> L
tRACC
tAH
--
~~
X
~
Bus C <0:1> L
tPH ....
I-
Bus MSYN L
I--tM
~
Bus SSYN L
tDs1
Bus D <0:15> L
tRCYC
5-13
I-
I-tD~'
•
•
MMS1119
TIMING
The MMSll19 is fully compatible with the PDP-ll
Modified and Extended UNIBUS protocol and timing. Limits
are specified in the AC Conditions/Characteristics Tables in
conjunction with the DATI/DATO waveforms.
REFRESH
The storage cells in the MMSll19 are implemented with
dynamic MOS RAM's. The charge stored in the cells must be
refreshed every 2 milliseconds, requiring a single refresh cycle to be initiated approximately once every 16 M Seconds.
The latency induced to bus cycles concurrent with refresh
cycles is no greater than the specified minimum cycle time
for the MMSll19 version chosen.
The MMS 1119 contains circuitry to automatically refresh
the memory cells. An option is also provided to allow the
User to control the refresh externally. In this case, the
Refresh Latency will be no greater than the refresh cycle time
defined by the external circuitry. Note that any external
refresh circuitry must conform to the requirements previously mentioned, i.e., each cell refreshed at a 2 millisecond rate
and a refresh cycle time not less than the minimum Read Cycle time.
AVAILABLE OPTIONS
The MMS 1119 features a variety of options, allowing its
configuration into a wide range of applications. 'Several of
these options are installed at the factory, with most of these
specified by the part number as shown in the "Ordering Information" on Page 1. Others are chosen by the User prior to
installation of the product.
MEMORY CAPACITY
The MMS1119 utilizes either 16K or 64K RAM components. to allow optional storage capacities of 64K, 96K,
128K, 256K, or 512K Words. As noted on Page 1 (Ordering
Information), the last three digits of the full part number
identifies the total memory capacity in K Words.
BUS INTERFACE
The.MMS1119 is provided with a switch to select the type
of Bus to be used. With this switch closed, the interface is to
an Extended UNIBUS backplane (22 bit address). The
memory operates with a Modified UNIBUS system (lB bit
address) with this switch open.
STARTING ADDRESS
The MMS1119 utilizes a set of switches to allow the starting address to be selected at any 4K boundary. This feature
is available· regardless of the Bus Interface or Memory
Capacity option chosen. In cases where the sum of the starting address and the memory capacity exceeds the host
machine addressing capability, the capability is automatically
reduced. INa wraparound to starting address locations occurs.)
I/O PAGE SIZE
When the MMSll19 is located in high memory, the User
may select part of the I/O page as Read/Write memory. This
is implemented via three switches, resulting in optional I/O
pa'ge sizes of 2K, 4K, or BK words.'
PARITY OPTIONS
The MMS1119PXXXX contains parity control circuitry
which is fully compatible with the DEC parity module. This
circuitry does not degrade access or cycle times, and the
Parity Control Status Register (CSR) address can be switch
selected to any standard pre-assigned bus address. (772100a
thru 772136a for Modified UNIBUS, 1772100a thru 1772136a
for Extended UNIBUS. In any case, the CSR occupies a
single two-byte address spacel. The on-board parity circuitry
does not impose any additional bus loading on the system.
The MMSll19PXXXX can also be used in systems which
utilize the DEC Parity Module. The User selects this mode of
operation by opening a switch Iprovided on the MMS1119P)
prior to installation of the memory. The parity generation and
detection circuitry of the MMS1119P is fully compatible with
the DEC Parity Module.
The MMS1119NXXXX version is available for those
systems not requiring parity. This product is supplied as a
16-bit word memory with the Internal/External Parity Control
switch open (External!.
1/0 SIGNAL DESCRIPTION
Signal
Type
Deacription
A<0:21>
Input
Address lines to select memory locations. AO selects byte in DATOB
0<0:15>
C<0:1>
Bidir.
Input
Data lines used to communicate with Master
Control lines to specify type of cycle
MSYN
input
SSYN
INIT
Output
Input
DClO
Input
PB
P<0:1>
PAR DET
Outout
Bidir.
Input
INT SSYN
Output
Timing control from Master. Used to start cycle
Timing control used to notify Master that cycle is complete
System Reset
Power monitoring
Sianal to Master that parity error has occurred
Data Parity Bits
Indicates external parity module is in use
Slave Sync used with external parity module only
NOTE: All Signals are low assertion level.
5-14
®
MOTOROLA
IIS1128
Advance InforIllation
*PDP-ll MODIFIED UNIBUS* COMPATIBLE MEMORY SYSTEM
• Uses 16K, 32K, or 64K Dynamic RAM Chips
• Available in 32K, 48K, 64K, 96K, and 128K Word
Capacities
• Read Access Time Typically 300 ns (Measured Inside
Buffersl
•
•
•
•
•
•
Cycle Times as Low as 460 ns Typical
Two Speed Options Available
Worst-Case AC Limits Specified at Card Edge
On-Board Parity and Parity Controller Standard
Also Available Without Parity
Starting Address Configurable at any 4K Boundary
•
•
•
•
Automatic Internal Refresh
Provisions for External Refresh Control
Battery Backup Capability Standard
Single 5-Volt Power Supply Required for 64K, 96K, 128K,
Word Versions
ORDERING INFORMATION
-rI
Controller I
Option
Basic Product
Designation
Parity +
No Parity··
I
I
I
I
I
y
3
4
I
I
I
Head Access
300 ns Ityp)
350 ns (typ)
"" Available on speCial order
I
I
I
NOTE: K
5-15
I
Z2
0
0
Zl
3
4
Zo
Capacity
2
32 K Words
8
48 K Words
0
6
4
64 K Words
0
9
6
96 K Words
1
2
8
128 K Words
= 1024, Word = 16 Bits WIO,
18 Bits With Parity
•
•
MMS1128
1/0 SIGNAL DESCRIPTION
Signal
Type
A <0:17>
Input
D <0:15>
C <0:1>
MSYN
Bidirectional
Input
Input
SSYN
Output
INIT
Input
System Reset.
DClO
Input
Power monitoring.
PB
Output
P <0:1>
Bidirectional
PAR DET
INT SSYN
Output
Description
Address lines to select memory locations. AO selects byte in DATOB.
Data lines used to communicate with Master.
Control lines to specify type of cycle.
Timing contr·ol from Master. Used to start cycle.
Timing control used to notify Master that cycle is complete.
Signal to Master that parity error has occurred.
Data Parity Bits.
Indicates extend parity module in
Input
USB.
Slave SYnc used with externaLParity module onJy--.:
NOTE: All signals are low asserllon level.
ABSOLUTE MAXIMUM RATINGS
Rating
Limn
Symbol
Min
Max
-0.3
20.0
VCC
-0.3
7.0
VBB
-20.0
0.3
0.7
5.5
VDD
Supply Voltage I Relative to Groundl
Input
Vo~age
(Any input relative to GND)
Yin
Units
Vde
Vde
NOTES: 1. Permanent damage may occur If Absolute Maximum Ratings are exceeded. Funcllonal operallon shall be restncted to
·Recommended Operating Conditions.
2. Permanent damage may also occur if VDD is applied for more than one second while VBB is outside its Recommended Operating
Range.
ENVIRONMENTAL RATINGS
Rating
Operating Temperature
Storage Temperature
Relative Humidity (Without Condensation)
Symbol
limit
Unn&
TA
O.to 55
Tstg
RH
-40 to +85
°c
°c
a to 90
%
RECOMMENDED DC OPERATION CONDITIONS
Symbol
Parameter
Supply Voltage
- Nominal + 15 V or nominal
-
Nominal
- Nominal
+ 12 V,
+ 5 V, pins AA2, BA2,
+ 5 V BBU, pin BDI
pin ARI
VDO
CA2
VCC
VCC/BBU
- Nominal -15 V or nominal -12 V, pin ASI
NOTES: 1.
+ 15 V or + 12 V
VBB
IS Jumper selectable on all modules populated with 16K RAMs.
Limn
Min
Max
14.50
16.50
11.40
12.60
4.75
5.25
4.75
5.25
7.00
20.00
Unn&
Note
1,3
Vdc
I--2
f-----J
~
2. Pins AA2, BA2, and CA2 are connected together on the MMS1128.
3. These voltages must be present on cards populated with 16K RAMs if Battery Back Up is required. Only VCC/BBU need be
present for cards populated with 32K or 64K RAMs.
4. VDO and VBB not required for cards populated with 32K or 64K RAMs.
5-16
MMS1128
WRITE CYCLE TIMING (DATOI
tAS -
...._ - - - tWACC - - - + \
Bus A <0:17> L
BusC <0:1> L
Bus D <0:15> L - -_ _ _ _-{
Bus MSYN L
tMH
Bus SSYN L
~--------tWCYC---------~~
READ CYCLE TIMING (DATI)
tAH.-..
_tAS
Bus A <0:17> L
'1/
BusOL
'I/,
....
tRACC
:JIIIIIII
-...
'JIIIIII/.
_tpH
Bus MSYN L
.... tMH
I
Bus SSYN L
t DS- ,
Bus D <0:15> L
tRCYC
5-17
~ ....tDH:I
•
•
MMS1128
DC OPERATING CHARACTERISTICS 10° < TA < 55'CI
Capacity
(K Words)
Limit
Typ
Max
0.25
0.50
0.16
0.30
Units
Notes
Adc
1,2
1.50
Adc
1
0.80
Adc
1
Adc
1
Mode
Symbol
32,48
Active
Standby
100
100
- Nominal + 5 V Supply
32,48
Act/Stby
ICC
1.20
- Nominal + 5 V BBU
32,48
BBU
ICC
0.55
- Nominal + 5 V Supply
64,96,128
Act/Stby
ICC
1.80
2.25
- Nominal + 5 V BBU
64,96,128
BBU
ICC
0.80
1.15
Adc
1
32,48
All
IBB
12
20
mAdc
1,2
15
Characteristic
Min
Supply Current
- Nominal + 15 V or + 12V Supply BBU
- Nominal -15 V or - 12 V Supply BBU
32,48
50
~Adc
3
-1.6
mAdc
3
VOH
20
100
~Adc
3
VOL
0.4
0.70
Vdc
3
2.25
2.50
Vdc
Logic "1" Input Current -
Any Input, VIH=4.0 Vdc
IIH
Logic "0" Input Current -
Any Input, VIL = 0.4 Vdc
IlL
Logic "1" Output Current - Any Output,
V Bus=4.0 Vdc
Logic "0" Output Voltage - Any Output,
IOL=50 mAdc
Any Input
Input Threshold Voltage
High Logic State
1.80
VILH
Input Threshold Voltage - Any Input Vdc
1.05 1.30 1.55
VIHl
Low Logic State
NOTES: 1. Active Mode=Memory accesses at maximum continuous rates; Standby Mode=lnternal Refresh Cycles only; Battery Back Up
IBBUI = Standby Mode with + 5 V applied only through Pin BDl.
2.
+ 15 V / + 12 V and
- 15 V /-12 V supplies not required for products populated with 64K RAMs.
3. Negative Sign=Current out of pin. MiniMax Limits refer to absolute values of current.
AC OPERATING CONDITIONS
Symbol
Parameter
Address Hold Time
MSYN to A<0:17> Invalid
Address Setup Time - A <0:17> Valid to MSYN
tAH
Processor Handshake Time - SSYN to MSYN
Data Hold Time IWrite Cycle/DATO) - MSYN to 0 <0:15> Invalid
Limit
Min Max
50
tAS
tpH
75
tDHW
40
0
Unit
Note
ns
1
ns
1
ns
ns
1,2
1
15
ns
1
Data Setup Time (Write Cycle/DATO) - <0:15> Valid to MSYN
tDSW
NOTES: 1. All timing IS referenced at card edge. Operallon IS assumed to be In a properly terminated backplane, With memory not busy and
no refresh arbitration.
2. Assumes handshaking occurs immediately.
AC OPERATING CHARACTERISTICS (O°C < T A < 70°C)
Characteristics
Cycle Time -
Read (DATil Cycle
Read Access Time - MSYN to SSYN
Symbol
MMS1128X3XXX
Min Typ Max
MMSll28X4XXX
Min Typ Max
Unit
Note
tRCYC
480
515
510
565
ns
1
tRACC
330
380
380
430
ns
1
70
ns
1
ns
2
75
ns
1
166
ns
1
Data Hold Time - Read IDATII Cycle MSYN to Data Invalid
tDH
Data Setup Time - Read (DATil
Cycle 0 <0:15> Valid to SSYN
tDS
0
tMH
25
Memory Handshake Time - Read (DATil or
Write IDArOI Cycle - MSYN to SSYN
Write Access Time - MSYN to SSYN
tWACC
Cycle Time - Write IDATOI Cycle
70
0
75
125
166
25
125
ns
1
325
340
425
440
tWCYC
NOTES: 1. All timing IS referenced at card edge. Operation IS assumed to be In a properly terminated backplane, With memory not busy and
no refresh arbitration.
2. Timing is referenced inside Bus Drivers.
5-18
MMS1128
TIMING
the last three digits of the full part number identifies the total
memory capacity in K Words.
The MMSl128 is fully compatible with the PDP-11
Modified UNI8US protocol and timing. Limits are specified
in the A.C. ConditionslCharacteristics Tables in conjunction
with the DA TIlDA TO waveforms.
STARTING ADDRESS
The MMSl128 utilizes a set of switches to allow the starting address to be selected at any 4K boundary. This feature
is available regardless of the Memory Capacity option
chosen. In cases where the sum of the starting address and
the memory capacity exceeds the host machine addressing
capability, the capability is automatically reduced. (No
wraparound to starting address location occurs.)
REFRESH
The storage cells in the MMSl128 are implemented with
dynamic MOS RAM's. The charge stored in the cells must be
refreshed every 2 milliseconds, requiring a single refresh cycle to be initiated approximately once every 16 milliseconds.
The latency induced to bus cycles concurred with refresh
cycles is no greater than the specified minimum cycle time
for the MMSl128 version chosen.
The MMSl128 contains circuitry to automatically refresh
the memory cells. An option is also provided to allow the
User to control the refresh externally. In this case, the
Refresh Latency will be no greater than the refresh cycle time
defined by the external circuitry. Note that any external
refresh circuitry must conform to the requirements previously mentioned, i.e., each cell refreshed at a 2 millisecond rate
and a refresh cycle time not less than the minimum Read Cycle time.
1/0 PAGE SIZE
When the MMS2118 is located in high memory, the User
may select part of the 1/0 page as ReadlWrite memory. This
is implemented via three switches, resulting in optional 1/0
page sizes of 2K, 4K, or 8K words.
PARITY OPTIONS
The MMS2118PXXXX contains parity control circuitry
which is fully compatible with the DEC parity module. This
circuitry does. not degrade access or cycle times, and the
Parity Control Status Register (CSR) address can be switch
selected to any standard pre-assigned bus address. (7721008
through 7721368.) In any case, the CSR occupies a single
two-byte address space. The on-board parity circuitry does
not impose any additional bus loading on the system.
The MMSl128PXXXX can also be used in systems which
utilize the DEC Parity Module. The User selects this mode of
operation by inserting a jumper prior to installation of the
memory. The parity generation and detection circuitry of the
M MS 1128P is fully compatible with the DEC Parity Module.
The MMSl128PXXXX version is available for those
systems not requiring parity. This product is supplied as a
16-bit word memory with the InternallExternal Parity Control
switch open (External).
AVAILABLE OPTIONS
The MMSl128 features a variety of options, allowing its
configuration into a wide range of applications. Several of
these options are installed at the factory, with most of these
specified by the part number as shown in the "Ordering Information" on Page 1. Others are chosen by the User prior to
installation of the product.
MEMORY CAPACITY
The MMSl128utilizes 16K, 32K, or64K RAM components
to allow optional storage capacities of 32K, 48K, 64K, 96K,
or 128K Words. As noted on Page 1 (Ordering Information),
•
5-19
•
®
MOTOROLA
MM51170
Product PrevieW'
MEMORY ARRAY CARD FOR PDP*-11/70
The MMSl170 is a dynamic memory array system
specifically designed for use in PDP-11170 minicomputers
from Digital Equipment Corporation. The array has a capacity of 64K double words (256K bytes I using 16K RAM chips.
It is hardware and software compatible with the PDP-11170
memory controller module and DEC diagnostics.
The MMSl170 is designed to occupy a single hex slot of
the DEC MK-11 Memory System chassis. It features an On
Line/Off Line switch (with an LED indicatorl to facilitate
trouble-shooting. A separate LED indicates when battery
backup voltage is available via the backplane connector.
All RAMs used on the MMSl170 are socketed. Two spare
16K x 1 RAMs are provided on the board. The product is fully burned-in and covered by the Motorola Memory System
One-Year Limited Warranty.
OROERING INFORMATION
Basic Pan No.
ECC
Speed Option
NOTE: Double Word = 32 Date and 7 ECC Bits
'PDP is a trademark of Digital Equipment Corporation
5-20
Size (64 x 1024 Double Words)
MMS1170
ENVIRONMENTAL RATINGS
Symbol
Rating
Operating Temperature
TA
Tsta
RH
Storage Temperature
Relative Humidity (Without Condensation I
Limit
Units
o to
'C
'C
o
%
+50
-40 to +80
to 90
PHYSICAL DIMENSIONS
Dimension
Millimeters
39.85
Width
Height
PC Board Thickness
Clearance Required (Component Side)"
Clearance Required (Solder Side)"
22.225
0.142
0.952
0.254
Inches
15.688
8.75
0.058
0.375
0.10
"Measured from surface of PC Board.
POWER REOUIREMENTS
Maximum Current Requirements
Units
Operating Standby Battery Backup
Input Voltage
+12 B
1.5
+5V
-12 B
0.4
0.04
+5 VB
0.9
0.25
0.35
0.02
0.8
0.25
0
Adc
Adc
0.02
0.8
Adc
Adc
AC OPERATING CHARACTERISTICS
Nominal··
Characteristic
Cycle Time -
Read
650
Write
680
320
70
Access Time - Read
Write
Units
ns
ns
""The actual'response times are determined by OEC MK-ll Memory System Controiler design. Nominal values shown are for reference only .
•
5-21
•
®
MOTOROLA
MMS780
Advance InforD1.ation
MEMORY ARRAY CARD FOR VAX-11/180*
The MMS780 is a dynamic memory array system specifically designed for use in VAX-11/780 minicomputers
from Digital Equipment Corporation. The array has a capacity of 32K words (256K Bytes) using 16K RAM chips. It
is fully compatible with the VAX-11/780 memory controller module .
ORDERING INFORMATION
FlO
MMS780AE1032
Basic
r.;;;:
I
ECC
Speed Option
Size IK Words)
Note: K = 1024
Word=64 Data + 8 ECC Bits
·VAX is a trademark of Digital Equipment Corporation.
5-22
MMS780
ENVIRONMENTAL RATINGS
Rating
Symbol
Operating Temperature
TA
Storage Temperature
Tstg
RH
Relative Humidity (Without Condensationl
Limit
o to
Units
DC
+55
40 to +80
DC
o to 90
%
PHYSICAL DIMENSIONS
MAlimeters
Inches
Width
39.B5
15.888
Height
30.48
0.142
0.952
0.254
Dimension
PC Board Thickness
Clearance Required (Component Sidel"
Clearance Required (Solder Sidel"
12.0
0.056
0.375
0.10
"Measured from surface of PC Board.
POWER REQUIREMENTS
Maximum Currant Requirements
Units
Standby Bettery Backup
fnput Voltage
Operating
+12 V
1.5
0.25
0.25
Adc
+5V
0.7
0.6
0
Adc
-5V
0.04
0.02
0.02
Adc
+5 V Battery
0.9
0.8
0.8
Adc
AC OPERATING CHARACTERISTICS
Characteristic
Nominal**
530
Cycle Time - Read, Refresh, or Init.
- Read/Modify/Write
1100
Access Time - Read
- Write
250
750
Units
ns
ns
""The actual response times are determined by VAX-ll/780 Memory Subsystem Controlier design. Nominal values shown are for reference
only.
OPERATING PRINCIPLES
The MSM780 is based on 16K x 1 dynamic RAMs arranged
in two banks, each containing 72 chips. The 72-bit word thus
formed is subdivided into two 32-bit long words (Upper and
Lower) and eight ECC bits. All memory array accesses correspond to a Read from, or write to, the selected 72-bit
word. (All 8, 16, and 32 bit memory operations are
transformed into 72 bit accesses by the memory controller.)
The memory array selection is accomplished via address
lines (ADR19:ADR16) and four select signals at the Memory
Subsystem 8ackplane. This 8ackplane has 16 slots
dedicated for memory array cards, with the select signals
uniquely specified for each slot. This arrangement eliminates
the need for special jumpers and address SWitches. The
MMS780 is merely inserted in the next available backplane
slot. A total of 4 Megabytes of memory can be accomodated
by one Memory Subsystem.
5-23
USAGE RECOMMENDATIONS
The MMS780 is recommended for use with any
VAX-11/780 memory subsystem set up for operation with
the DEC M8210 array card. It is hardware and software compatible with the VAX-11/780, including DEC diagnostics
which allow failure isolation at the chip level. The M M S780 is
also compatible with DEC battery backup provisions.
INTERFACE
The VAX-11 1780 computer system is normally configured
with either one or two memory subsystems, as shown in
Figure 1. The normal interface signals ut'lized within each
subsystem are depicted in Figure 2. The MMS780 Array
Module functions in any slot of either subsystem, with no
modifications required.
•
•
MMS780
FIGURE 1 -
NORMAL VAX-ll 1780 MEMORY CONFIGURATION
VAX-lll780
CPU
Cache Memory
Synchronous Backplane Interconnect
"I "Ir·
"1
~J
r-'------,
I
"
I
I
I
I
:
I
I
Optional
Memory
Controller
I
I~'
...
0-16
Memory
Array Cards
I
I I I
I I I I
IMMS780)
MEMORY SUBSYSTEM INTERFACE
r---
M
E
M
Memory
Controller
Memory
R
Board Select Addr. )
V
Y
Board Select Addr.
.....
Extended Addr.· < ADR15:ADR13>
Slot Select . )
a
.....
Y
V
Base Chip Addr.· < ADR12:ADROl > : : )
S
T
E
M
Control Signals·· 18)
.....
ECC Bits
Data
V
A
C
)
K
P
~
L
A
N
E
./
Array
IMMS780)
Base Chip Addresses < ADR12:ADROl > )
B
/
'-r
~
I
(~ .. --~'~
1",-- _, /1
! I :'A
I
I
L
______ JI ~ ~ L
______ j-t-A
.
I
IMMS780)
FIGURE 2 -
r .. -------, I
I
r ... -----, I I I
I
: " I
,... . . - - - - - ,
r--~--'
I
2-16
Memory
Array Cards
Memory
Controiler
r-----.,
~7
r
Control Signals·· 18)
~
V
V
i'r
>- ~
ECC Bits < C07:COO>
-)
V
Data -;
·Extended Addresses are labeled ADR13, ADRCS, and ADREXT. During normal operation, they correspond to >ADR15:ADR13<.
··Control signals are: Read, Column Address Strobe ICAS), Row Address Strobe IRAS), Multiplexer Control, Refresh Cycle, Bus Select, Bus Output Enable, and Initiate.
5-24
®
MMS8064(P)
MMS8048(P)
MMS8032(P)
MMSS016(P)
MOTOROLA
Advance Information
SBC-COMPATIBLE MEMORY SYSTEMS
The MMS80XX family of memory systems is designed
for use with the Intel SBC 80 Series computers, System
80 microcomputers, MDS systems, and the 16-bit SBC
86/12. The modules employ 16K dynamic RAM's
mounted on a single 6 3/4" X 12" PC board along with
timing, control, and bus interface logic, Eight models are
available, all having the same access and cycle times. All
electrical connections are made via two edge connectors.
• Pin, Function, and Form-Factor Compatible with
MULTIBUS' Systems
• Even/Odd Bank Address Allows 16-Bit or 8-Bit
Operation
• Addresses Selectable in Independent 8K Blocks
• 20 Address Lines -
Operates in 1M Byte System
• Handles Early or Late Inhibits
• Operates in Delayed Write, Advance Write, and Read
Modes
• 8attery Backup Capability through use of Memory
Protect Signal on P2 Connector
• On-Board Refresh Control Circuitry
• Programmable Advanced Acknowledge (AACK/)
Signal
• On-board Vee Generation (-5 V) Allows Operation
from 12 V, +5 V, and -12 V, -10 V, or -5 V Supplies
• Cycle Times of 700 ns (Read, Delayed, Write) and
1240 ns (Advanced Write)
• Available in 16K, 32K, 48K, and 64K Byte
Configurations
PHYSICAL CHARACTERISTICS
ORDERING INFORMATION
No Parity
Parity
Capacity
MMSB064
MMSB064P
MMSB04B
MMSB032
MMSB04BP
MMSB032P
64K eytes
4BK Bytes
MMSB016
MMSB016P
Characteristic
Width
Depth
limit
30.4B cm (12.00 inches)
17.15 cm (6.75 inches)
32K Bytes
Thickness
1.27 cm (0.50 inches)
16K Bytes
Weight
397 grams (14.0 ounces)
"Trademark of Intel. Inc.
5-25
•
MMS8064(p)eMMS8048(p)eMMS8032(p)eMMS8016(P)
AC OPERATING CONDITIONS
Limit
Parametar
Read or Delayed Write Cycle
Advanced Write Cycle
Cycle Time
Symbol
Min
Units
Notes
tCYC
tCYCIAI
700
1240
ns
1,2
1,2,3
Max
Address Setup Time
Address Valid to MRDC/I or MWRC/I
tAS
50
ns
Address Hold Time
MRDC/I or MWRC/I to Address Invalid
tAH
0
ns
Data Valid to MWRC/I
tDSW
-100
ns
Write Data Setup Time (Delayed Write)
Write Data Delay Time
(Advanced Write)
MWRC/I to Data Invalid
ns
tDHW
0
ns
tlS1
tlS2
10
-50
ns
Early Inhibit
Late Inhibit Option Installed
Inhibit Setup Time
INHII Valid to MRDC/I or MWRC/I
500
tDDAW
Write Data Hold Time
Inhibit Hold Time
MRDC/I or MWRC/I to INHI Invalid
tlH
100
ns
Byte High Enable Setup Time
BHENI Valid to MRDC/I or MWRC/I
tas
50
ns
MRDC/I or MWRC/I to BHENI Invalid
tBH
0
ns
Memory Protect Setup Time
MPRO/I to VCC
< 4.75 Vdc
tMPS
15
I'S
Memory Protect Hold Time
VCC 2: 4.75 Vdc to MPRO/I
tMPH
0
tRI
12.7
Byte High Enable Hold Time
Refresh Interval
NOTES:
3
ns
15.6
ms
Typ
Max
Units
Notes
4DO
450
ns
1,3
1) Add Refresh Delay Time (TRO) to these parameters when Asynchronous Refresh occurs.
2) Add 40 ns (Typ), 50 ns (Max) to these parameters if Late Inhibit Option is installed.
3) Applicable only if Advanced Write Cycle option is installed.
AC OPERATING CHARACTERISTICS (OOC <
- TA -< 55°C)
Limit
Symbol
Parameter
MRDC/I to Data Valid
tACC
Read Data Valid to XACK/I
tOSR
0
XACK/I to Data Invalid
tOHR
0
MRDC/I or MWTC/I to AACK/I
tAAK
-
Read Access Time
Read Data Setup Time
Read Data Hold Time
Advance Acknowledge
Delay Time
Transfer Acknowledge
Delay Time
Acknowledge Turn-Off Time
Parity Error Setup Time
Parity Error Hold Time
ns
-
MRDC/I or MWTC/I to XACK/I
tACK
MRDC/I or MWTC/I to AACK/I or
XACK/I
tTO
15
PAR ERRI Valid to XACKll
tps
0
XACK/I to PAR ERR/lnvalid
tPH
50
65
ns
-
ns
1,4,5
50
ns
1.2
55
ns
ns
ns
550
tOR
Refresh Delay Time
NOTES:
Min
ns
1) Add 40 ns (Typ), 50 ns (Max) to these parameters If Late Inhibit option IS ,"stalled.
2) Add 450 ns (Typ), 500 ns (Max) to these parameters for Advanced Write Cycle operations.
3) Add Refresh Delay Time (tRO) to these parameters when Asynchronous Refresh occurs.
4) See Advance Acknowledge options table for Delay Time.
5) Advance Acknowledge is delayed until Transfer Acknowledge Time if Asynchronous Refresh occurs .
ADVANCE ACKNOWLEDGE OPTIONS
The MMS8060 Series can be programmed to
provide an ADV ACK Delay (tAAK) of 100 to
Option Selected
450 ns. Available options are as noted in table
at right. Selection is made via installation of a
single jumper between two terminals of a 16-
Limit
8-9
1-16
7-10
2-16
3-14
5-12
4-13
6-11
Units
Min
70
120
165
215
260
310
360
4DO
ns
pin DIP socket. (Jumper between pins 8 & 9lOOns Typ, betwe.en 1 & 16 - 150 ns, etc.).
Typ
100
150
200
250
300
350
4DO
450
ns
Max
125
175
230
285
335
4DO
450
500
ns
5-26
MMS8064(p)eMMS8048(p)eMMS8032(p)eMMS8016(P)
ABSOLUTE MAXIMUM RATINGS
Limit
Symbol
Min
Max
Units
Nominal +5 Vdc
Vee
-0.3
+7.0
Vdc
Nominal +12 Vdc
VOO
-0.3
+15.0
Vdc
Nominal -5 Vdc (Negative voltage regulator disabled)
Nominal -10 Vdc or -12 Vdc (Negative voltage regulator enabled)
Vss
+0.3
+0.3
-7.0
-15.0
Vdc
Vdc
VIN
-0.3
+5.5
Vdc
Rating
Power Supply Voltage
(Measured at Connector
P1 or P2 With Respect
to GNO).
Input Voltage, Any Input. (Measured at P1 or P2 Conn. With Respect to GND).
NOTES;
1) Permanent damage may occur If Absolute MaXimum Ratings are exceeded. Functional operation should be restricted to
Recommended Operating Conditions.
2) Permanent damage may also occur if Von is applied for more than one second while Vas is outside its Recommended
Operating Range.
ENVIRONMENTAL RATINGS
Limit
Rating
Symbol
Min
Max
Unit
TA
0
+55
°C
Storage Temperature
Tstg
-40
+85
°C
R.lative Humidity (Without Condensation)
R.H.
0
90
%
Symbol
Min
Max
Units
Nominal +5 Vdc
Vee
4.75
5.25
Vde
Nominal +12 Vde
VOD
11.4
12.6
Vde
Nominal -5 Vde (Negative voltage regulator disabled)
Nominal -10 Vde or -12 Vde (Negative voltage regulator enabled)
VSS
-4.75
-9.5
-5.25
-12.6
Vde
Operating Temperature
RECOMMENDED DC OPERATING CONDITIONS
Limit
Condition
Supply Voltage
Logic Zero Input Voltage, Any Input
VIL
-0.3
+0.8
Vde
Logie One, Input Voltage, Any Input
VIH
+2.0
+5.25
Vde
Max
Units
DC OPERATING CHARACTERISTICS (ODC <
- TA <
-- 55°C)
Limit
Symbol
Parameter
Min
Typ
Supply Current
Nominal +5 Vde
lee
3.0
Ade
(Normal Mode)
Nominal +12 Vde
IDO
260
mAde
Nominal -5 Vde (Negative voltage regulator disabled)
Nominal -10 Vde or -12 Vde (Negative voltage regulator enabled)
Iss
14
30
mAde
mAde
Supply Current
Nominal +5 Vde
lee
1.1
Ade
(Battery Backup Mode)
Nominal +12 Vdc
100
90
mAde
Nominal -5 Vde (Negative voltage regulator disabled)
Nominal -10 Vde or -12 Vde (Negative voltage regulator enabled)
ISS
7.2
14
mAde
mAde
Logic One Input Current
(Vee = 4.75 Vde, VIH = 2.4 Vde
DATO/-DATFI
All Other Inputs
IIH
250
40
pAde
pAde
Logic Zero Input Current
(Vee = 5.25 Vde, VIL = 0.4 Vde)
DATO/-DATFI
All Other Inputs
IlL
-600
-400
pAde
pAde
Logic One Output Voltage
All Outputs
VOH
All Outputs
VOL
2.4
Vde
(Vee = 4.75 Vde, IOH = -5 mAde)
Logie Zero Output Voltage
(Vec = 4.75 Vde, IOL = 48 mAde)
5-27
0.5
Vde
•
•
MMS8064(p)eMMS8048(p)eMMS8032(p)eMMS8016(P)
BASIC CYCLE TIMING
teye
Address
tAHj4'1----
MWRCI ________________~
or
MRDCI
AACKI
XACKI
INHll
BHENI
READ CYCLE TIMING
/
MRDCI
t-
DATA
______
tDHRJ-----_
XACK
PARERR-----------------
~
t
PH
-1
~~-----
DELAYED WRITE CYCLE TIMING
MWRCI
r-tDSW}----::f
t:'"-
p------
DATA-------L
ADVANCED WRITE CYCLE TIMING
MWRCI
j
\.
DATA _________
I~~.========_tD_D_A_W~~~~~~~~:~::--------------
5-28
~ ~~
__t_DH_W
____
MMS8064(p)eMMS8048(p)eMMS8032(p)eMMS8016(P)
P1 CONNECTOR PIN ASSIGNMENTS
Symbol
Pin No.
VSS
VSS
VSS
VSS
VOO
Vee
Vee
Vee
Vee
VBB
VBB1
VBB2
XACKI
1.2
11,12
75, 76
85,86
7,8
3,4
5,6,
81,82
83,84
9,10
77,78
79,80
23
AACKI
25
Command
INHll
24
Inhibit
Byte High
Enable
BHENI
27
Signal Name
Ground
Ground
Ground
Ground
+12 V Supply
+5 V Supply
+5 V Supply
+5 V Supply
+5 V Supply
-5 V Supply
-10 V Supply
-12 V SUDolv
Transfer
Acknowledge
Advance
Acknowledge
Signal Name
Address
Address
Address
Address
Address
Address
Li ne
Line
Line
Line
Line
Line
0
1
2
3
4
5
Address Li ne 6
Address
Address
Address
Address
Address
Address
Address
Add ress
Address
Address
Address
Add ress
Address
Li ne
Line
Line
Line
Line
Line
Line
Li ne
Line
Line
Line
Une
Line
7
B
9
A
B
C
0
E
F
10
11
I2
13
Symbol
Pin No.
Signal Name
AOROI
ADRll
ADR21
ADR31
ADR41
ADR51
ADR61
ADR71
ADRBI
ADR91
ADRAI
AD RBI
ADRCI
ADROI
ADREI
ADRFI
ADR101
ADRlll
ADR121
ADR131
57
58
55
56
53
54
51
52
49
50
47
48
45
46
43
44
28
30
32
34
Memory Read
Command
Memory Write
Command
Data Line 0
Symbol
Pin No.
MRDCI
MWTCI
19
20
DATOI
DAT1I
DAT2I
DAT31
DAT41
DAT51
DAT61
DAT71
DATSI
OAT91
DATAl
DATBI
DATc/
DATDI
DATEI
DATFI
73
74
71
Symbol
Pin No.
TP-PART 2 & 3
VSS
Vee (BATT)
VDO(BATT)
VBB (BATT)
44
1,2
3,4
Data Line 1
Data Line 2
Data Line 3
Data Line 4
Data
Data
Data
Data
Line
Line
Line
Line
5
6
7
8
Data Line 9
Data Line A
Data Line B
Data
Data
Data
Data
Line
Line
Line
Line
C
0
E
F
72
69
70
67
68
65
66
63
64
61
62
59
60
NOTE: Pins not listed are not connected to Memory System circuitry.
P2 CONNECTOR PIN ASSIGNMENTS
Signal Name
Memory Protect
Parity Error
Test Point - Advanced Write
Test Point Test Point -
Refresh Clock
Parity 0 & I
Symbol
Pin No.
MPROI
PAR ERRI
TP-ADVW
TP-REFCLK
TP-PART 0 & I
20
29
38
40
42
Signal Name
Test Point -
Parity 2 & 3
Ground
+5 V (Battery)
+12 V (Battery)
-5 V (Battery)
9,10
NOTE: PinS not listed are not connected to Memory System circuitry.
MMS80XX SYSTEM
Description
Signal (P1)
ADROI-ADRFI
Lower Order Address used to select 1 location out of 64K* block
ADR10-ADR-131
High Order Addresss used to select one 64K block out of 1024K
DATOI-DAT71
Data signals for 8-bit mode or lower byte of data signals for 16-bit mode
DATBI-DATFI
High order byte data signals for 16-bit mode
AACKI
(Programmable -
8 timing selections) Advanced Acknowledgement Signal from Memory Card in response to
MWTCI or MRDC
XACKI
Acknowledgement Signal from Memory Card indicating that Data Transfer has occurred
MRDCI
Signal to Memory Card requesting to read RAM memory
MWTCI
Signal to Memory Card requesting to write data into RAM memory
INHll
Signal disabling response of the Memory card to MWTCI and MRDCI
BHENI
Signal used to enable the 16-bit mode of operation
Description
Signal (P2)
MPROI
Signal used to enable the transfer from normal voltages to battery back-up voltages by disabling all circuits except
refresh. Can also be used separately from battery back-up to do same thing
PAR ERRI
Signal used to indicate a Parity Error
TP-ADVW
Test Point Signal used to select Advanced Write Mode
TP-REF C/K
Test Point Signal used to c.lock refresh flip-flop externally (used only for evaluation purposes)
TP-PART 0 AND I
Test Point Signal used to force a Parity Error on Reading Banks 0 or 1
TP-PART 2 AND 3
Test Point Signal used to force a Parity Error on Reading Banks 2 or 3
*K = 1024 Bytes
5-29
MMS8064(p)eMMS8048(p)eMMS8032(p)eMMS8016(P)
GENERAL DESCRIPTION
series allows the userto select an Advance-Acknowledge
Delay Time of 100 to 450 ns (in 50 ns increments). This
facilitates tailoring of the memory response time to the
system speed.
An Inhibit input is provided with the MMSSOXX series
to allow the Bus Master to turn offthe memory for certain
operations. In general, the system activates this Signal
prior to a Memory Read (MRDC/) or Write (MWRC/)
command. In certain types of systems, however, the
Inhibit signal arrives after the Read/Write command. A
jumper option is provided with the MMSSOXX Series;
allowing the Inhibit input to respond to a "Late Inhibit"
signal. This option should be installed only if the system
requires it, since it slows the Memory System response by
approximately 50 ns.
Most SBC systems utilize a "Delayed Write:' command
wherein the Data is available coincident with activation of
MWRC/. Some systems, however, utilize an "Advanced
Write" technique, with the data becoming valid some 500
ns after the Write Command. Ajumper option is provided
with the MMSSOXX series to allow operation in the Write
Cycle. Transfer Acknowledge (XACK/) is inhibited during
the dummy cycle, but Advance Acknowledge (AACK/)
occurs·if programmed to do so. XACK/ then occurs during
the actual Write Cycle unless the system has responded
to the AACK/ Signal. (In this case, system response to the
AACK/ signal is defined as a deactivation ofthe MWRC/
input). Selection of the "Advanced Write" option does not
affect Read Cycle operations.
In general, SBC backplanes provide -5 volts at pins 9
and 10 of connector Pl. Some systems, however, provide
only -10 volts at pins 77 and 7S and/or -12 volts of pins
79 and SO. The MMSSOXX Series contain an on-board
negative 5 volt regulator to allow operation with such
systems .
The MSMSOXX series is designed for operation with
SSC/BLC SO Series Single-Board Computers (including
the SBC S6/12 16-bit computer), System SO Series
Microcomputers, and Intel MDS Systems. The four
configurations are plug-in replacements for
Intel/National SBC/BLC 016, 032, O4S, 064 memory
cards.
OPTIONS
The MMSSOXX series is available in four population
options. Each of these configurations can be obtained
with or without parity. (See Ordering Information on Page
1.) In addition to the population and parity options,
provisions are made to allow the user to configure the
memory card to meet system requirements. The primary
user options are Address Selection, AdvanceAcknowledge Response time, Early/Late Inhibit options,
Advanced/Delayed Write selection, and -5 Vdc
derivation.
Address Selection options allow the user to I.ocate the
memory card in anyone of sixteen memory segments with each of these segments defined as a 64K memory
space. If the MMSS064 is chosen, the memory system
responds to all addresses within the selected memory
segment. When depopulated modules (S016/S032/
S04S1 are used, address selection for independent SK
Byte blocks is provided. The MMSS04S, for example, can
be configured to respond to 6 of the eight SK blocks in the
chosen segment.
Advance Acknowledge is utilizedto prevent initiation of
unnecessary processor "Wait" states. (In effect, the
signal indicates that the memory transfer will be
completed during the current cycle). The MMSSOXX
•
5-30
Mechanical Data
l1li
!
6-1
•
6-2
MECHANICAL DATA
The packaging availability for each device is indicated on the individual data sheets. Dimensions
for the packages are given in this section.
----------14-PIN PACKAGES----------FRIT-SEAL CERAMIC PACKAGE
CASE 632
4
SS1
~
-It-oj
1
7~
F
MILLIMETERS
MIN
MAX
19.05 19.94
6.10
7.49
5.08
0.38
0.58
1.40
1.77
2.54 BSC
1.91
2.29
J
0.20
0.38
K
5.08
3.18
L
7.62 BSC
150
M
N
0.51
1.02
DIM
A
8
C
D
F
G
H
INCHES
MIN
MAX
0.750 0.785
0.240 0.295
0.200
0.015 0.023
0.055 0.070
0.1008SC
0.075 0.090
0.008 0.015
0.125 0.200
0.300 asc
150
0.020 0.040
NOTES:
1. ALL RULES AND NOTES ASSOCIATED
WITH MO-OOI AA OUTLINE SHALL APPLY.
2. DIMENSION "L"TD CENTER OF LEADS
WHEN FORMED PARALLEl.
3. DIMENSION "A" AND "8" (632·06) DO
NOT INCLUDE GLASS RUN-OUT.
4. LEAOS WITHIN 0.25 mm (0.010) DIA
OF TRUE POSITION AT SEATING PLANE
AND MAXIMUM MATERIAL CONDITION.
CASE 632-06
PLASTIC PACKAGE
CASE 646
MILLIMETERS
MAX
DIM MIN
A 18.16 19.56
6.60
B 6.10
4.06
5.08
C
0.38
0.53
D
F
1.02
1.78
.54 BSC
G
1.32
2.41
H
0.20
0.38
J
K
2.92
3.43
7.62 asc
L
00
100
M
0.51
1.02
N
INCHES
MIN
MAX
0.715 0.770
0.240 0.260
0.160 0.200
0.015 0.021
0.040 0.070
0.10 B~
0.052 0.095
0.008 0.015
0.1 5 0.135
0.300 BSC
00
100
0.020 0.040
CASE 646-05
6-3
NOTES:
1. LEADS WITH IN 0.13 mm
(0.005) RADIUS OF TRUE
POSITION AT SEATING
PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION "L" TO
CENTER OF LEADS
WHEN FORMED
PARALLEL.
3. DIMENSION "B" DOES NOT
INCLUDE MOLD FLASH.
4. ROUNDED CORNERS OPTIONAL .
•
•
MECHANICAL DATA (Continued)
- - - - - - - - - - 16-PIN PACKAGES
FRIT-SEAL CERAMIC PACKAGE
CASE 620
~1
~~
1. LEADS WITHIN 0.13 mm (0.005) RADIUS
OF TRUE POSITIDN AT SEATING PLANE
AT MAXIMUM MATERIAL CONDITION.
2. PACKAGE INDEX: NOTCH IN LEAD
NOTCH IN CERAMIC OR INK DDT.
3. DIM "L"TO CENTER OF LEADS WHEN
FORMED PARALLEL
MI LLiMETERS
MAX
DIM MIN
A 19.05 19.94
7.49
6.10
B
5.08
C
0.53
0.38
D
1.40
1.78
F
2.54 BSC
G
0.51
1.14
H
0.30
J
0.20
5.08
3.18
K
7.62 BSC
L
150
M
N
0.51
1.02
4. DIM "A" ANO "B" 00 NOT INCLUDE
GLASS RUN·OUT.
5. DIM "F" MAY NARROW TO 0.76 mm
(0.030) WHERE THE LEAD ENTERS
THE CERAMIC BODY.
INCHES
MIN MAX
0.750 0.785
0.240 0.295
0.200
0.015 0.021
0.055 0.070
0.100 BSC
0.020 0.045
0.008 0.012
0.125 0.200
0.300 BSC
150
0.020 0.040
CASE 620-06
PLASTIC PACKAGE
CASE 648
\
A -----j
OPTIONAL LEAD
CONFIG. (1,8,9,& 16)
NOTE 5
MILLIMETERS
DIM MIN
MAX
A 18.80 21.34
B
6.10
6.60
C
4.06
5.08
0.38
0.53
0
F
1.02
1.78
2.54 BSC
G
H
0.38
2.41
J
0.20
0.38
K
.9
3.43
7.62 BSC
L
100
M
0"
N
0.51
1.02
INCHES
MIN
MAX
0.740 0.840
0.240 0.260
0.160 0.200
0.015 0.021
0.040 0.070
0.100 BSC
0.D15 0.095
0.008 0.015
O. 15 0.135
0.300 BSC
100
00
0.020 0.040
CASE 648-05
6-4
NOTES:
1. LEADS WITHIN 0.13 mm
(0.005) RADIUS OF TRUE
POSITION AT SEATING
PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DlMENSIDN "L" TO
CENTER OF LEADS
WHEN FORMED
PARALLEL.
3. DIMENSION "B" DOES NDT
INCLUDE MOLD FLASH.
4. "F" DIMENSION IS FOR FULL
LEADS. "HALF" LEADS ARE
OPTIONAL AT LEAD PDSITIONS
1,8,9, and 16).
5. ROUNDED CORNERS OPTIONAL
MECHANICAL DATA (Continued)
- - - - - - - - - 1 6 - P I N PACKAGES (Continued) - - - - - - - - CERAMIC PACKAGE
CASE 650
r;------,
9
8 I
_.1
L
(I.
liftc
t
-l
A
-i
_-.l t
l'
' 16
rI
iN
R
DIM
L
A
I
I
B
"I"
I
B
C
KI~
0
~
G
Ft
H
K
I--o~N
NOTES:
1. LEAD NO.1 IDENTIFIED BY TAB
ON LEAD OR DOT ON COVER.
2. LEADS WITHIN 0.13 mm 10.005)
TOTAL OF TRUE POSITION AT
MAXIMUM MATERIAL CONDITION.
R
MILLIMETERS
MIN
MAX
INCHES
MIN
MAX
9.40 10.16
7.24
6.22
1.52
2.03
0.41
0.48
0.15
0.08
1.278SC
0.89
0.64
9.40
6.35
18.92
0.51
0.38
-
0.370 0.400
0.245 0.285
0.060 0.080
0.D16 0.019
0.003 0.006
0.0508SC
0.025 0.035
0.250 0.370
0.745
0.020
0.015
CASE 650-03
CERAMIC PACKAGE
CASE 690
NOTES:
1. ·A· AND ·B· ARE DATUMS.
2. T IS SEATING PLANE
3. POSITIONAL TOLERANCE FOR LEADS (0).
[JlJJl:2510.01o)el TI A
DIM
A
B
C
0
F
G
H
J
K
L
M
N
MILLIMETERS
MIN
MAX
20.07 20.57
7.62
7.11
2.67
4.19
0.38
0.53
0.76
1.52
2.54 BSC
0.76
1.78
0.20
0.30
3.18
5.08
7.62 BSC
100
0.38
1.52
INCHES
MIN
MAX
0.790 0.810
0.280 0.300
0.105 0.165
0.015 0.021
0.030 0.060
0.100 Bse
0.030 0.070
0.008 0.012
0.125 0.200
0.300 Bse
100
0.015 0.060
CASE 690-13
6-5
021 B B I
4. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL
5. DIMENSIONING AND TO LERANCING
PER ANSI Y14.5, 1973.
6.690-11 AND 690·12 OBSOLETE.
NEW STANDARD 690·13.
•
•
MECHANICAL DATA (Continued)
- - - - - - - - - - 1 8 - P I N PACKAGES - - - - - - - - - CERAMIC PACKAGE
CASE 6BO
"
D
MILLIMETERS
DIM MIN
MAX
A 22.48 23.24
B
7.16
7.57
3.18
4.27
C
D
0.38
0.58
1.40
F 0.76
G
2.54
H
1.02
1.52
J
0.20
0.30
2.68
4.44
K
L
7.R7
7.37
M
100
N
0.38
1.40
Ise
NOTES:
1. LEADS WITHIN 0.13 mm (0.005) RAD OF
TRUE POSITION AT SEATING PLANE AT
MAXIMUM MATERIAL CONDITION.
2. DIMENSION "L" TO CENTER OF LEAOS
WHEN FORMED PARALLEL.
INCHES
MIN
MAX
0.885 0.915
0.282 0.298
0.125 0.168
0.015 0.023
0.030 0.055
0.100
0.040 0.060
0.008 0.012
0.105 0.175
0.290 0.310
100
0.015 0.055
asc
CASE 6BO-06
PLASTIC PACKAGE
CASE 701-01
NOTES:
1. LEADS WITHIN 0.13mm
(0.005) RADIUM OF TRUE
POSITION AT SEATING
PLANE AT MAXIMUM
MATERIAL CONDITION
(DIM "G").
2. DIMENSION "L" TO CENTER
OF LEADS WHEN FORMEO
PARALLEL.
MILLIMETERS
DIM MIN MAX
A 23.11 23.88
a 6.10 6.60
e 4.06 4.57
D 0.38
0.51
F 1.02
1.52
2.54 asc
G
H 1.32
1.83
J 0.20 0.30
K 2.92
3.43
7.87
L 7.37
M D·
10·
1.02
N 0.51
INCHES
MIN
MAX
0.910 0.940
0.240 0.260
0.160 0.180
I 0.020
i
1 0.072
10.012
0.135
0.290 0.310
D·.
10·
0.020 0.040
CASE 701-01
6-6
~
~
MECHANICAL DATA (Continued)
- - - - - - - - - 1 8 - P I N PACKAGES (Continued)
PLASTIC PACKAGE
CASE 707
A
,
c
--J G lNOTES:
1. POSITIONAL TOLERANCE OF LEADS 10),
SHALL BE WITHIN 0.25mm(0.010) AT
MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND
EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL
3. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
r. L=J
~~
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
MAX
A 22.22 23.24 0.875 0.915
6.60 0.240 0.260
6.10
B
3.94
4.57 0.155 0.180
C
0.56 0.014 0.022
D
0.36
1.27
1.78 0.050 0.070
F
0.100 BSC
2.54 8SC
G
1.02
1.52 0.040 0.060
H
0.20
J
0.30 0.008 0.012
3.43 0.115 0.135
K
2.92
0300 BSC
L
7.62 BSC
150
15 0
M
00
00
0.51
N
1.02 0.020 0.040
CASE 707-02
FRIT SEAL CERAMIC PACKAGE
CASE 726
t
B
~'rFI"'FI"F'rFI"'FI"F~~
G.J
DIM
NOTES:
1. LEADS, TRUE POSITIONED
WITHIN 0.25 mm (0.010) OIA.
AT SEATING PLANE,AT
MAXIMUM MATERIAL
CONDITION.
2. DIM "L"TD CENTER OF
LEADS WHEN FORMEO
PARALLEl.
3. OIM "A" & "S"INCLUDES
MENISCUS.
A
B
C
0
F
G
H
J
K
L
M
N
MILLIMETERS
MIN
MAX
23.11
7.75
4.06
0.51
0.41
1.27
1.52
2.54BSC
1.40
0.30
0.20
4.44
7.37
8.00
00
150
1.27
0.51
22.35
7.11
INCHES
MAX
MIN
0.910
0.305
0.160
0.016 0.020
0.050 0.060
0.100BSC
0.880
0.2BO
U.U~~
0.008
0.290
00
0.020
0.012
0.175
0.315
150
0.050
CASE 726-02
6-7
•
•
MECHANICAL DATA (Continued)
- - - - - - - - - 1 8 - P I N PACKAGES (Continued) - - - - - - - CERAMIC PACKAGE
CASE 749
I
J
'L
--I
NOTES:
1. DIMENSION IXlIS DATUM.
2. PDSITIONAL TOLERANCE FOR LEADS:
1-$10.25 (0.010)
@I T IA@I
3. iIlls SEATING PLANE.
4. DIMENSIONING ANO TOLERANCING PER
ANSI Y14.5, 1973.
MILLIMETERS
MIN MAX
22.61 23.11
7.24 7.75
8.64
0.36 0.61
0.89 1.40
2.54 SSC
3.30
0.23 0.30
2.92
7.37 7.87
0.64
1.14
P
9.14
DIM
A
8
C
D
F
G
H
J
K
L
N
INCHES
MIN
MAX
0.890 0.910
0.285 0.305
- 0.340
0.014 0.024
0.035 0.055
0.100 SSC
0.130
0.009 0.012
- 0.115
0.290 0.310
0.025 0.045
- 0.360
CASE 749-01
----------20-PIN PACKAGE---------CERAMIC PACKAGE
CASE 7'lB
DIM
A
8
C
D
F
G
H
J
K
L
M
N
NOTE:
1. LEADS WITHIN 0.13 mm (0.005)
RAOIUS OF TRUE POSITION AT
SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF
LEAOS WHEN FORMED
PARALLEL
MILLIMETERS
MAX
MIN
24.64 25.91
7.06 8.13
2.19 4.70
0.38 0~51
1.14 1.40
2.54 sse
0.89
1.52
1.30
0.2U
3.18 4.57
7.62 SS
00
100
0.51
1.52
INCHES
MAX
MIN
0.970 1.020
0.21S 0.320
0.110 0.185
0.015 0.020
0.D45 0.055
0.100 esc
I 0.035 0.060
I U.UUH I u.012
0.125 0.18U
0.300 esc
00
100
0.020 I 0.060
CASE72!Hl2
6-8
MECHANICAL DATA (Continued)
- - - - - - - - - - 22-PIN P A C K A G E S - - - - - - - - - PLASTIC PACKAGE
CASE 708
B
L
MILLIMETERS
DIM MIN
MAX
A 27.56 28.32
B
8.64
9.14
3.94
C
5.08
0.56
0
0.36
F
1.27
1.78
G
2.54 BSC
H
1.02
1.52
J
0.38
0.20
K
2.92~ 3.43
L
10.16BSC
M
15°
0°
N
0.51.1 1.02
N C
!
!
K
-'G~
-'-F
-'- 0
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D).
SHALL BE WITHIN 0.25I11mlO.Ol0) AT
MAXIMUM MATERIAL CONDITION. IN
RELATION TO SEATING PLANE AND
EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS
WHEN FORMEO PARALLEL.
3. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
INCHES
MIN
MAX
1.085 1.115
0.340 0.360
0.155 0.200
0.014 0.022
0.050 0.070
0.100 SSC
0.040 0.060
0.008 0.015
0.115 0.135
0.400 BSC
150
0°
0.020 0.040
CASE 708-04
FRIT-SEAL CERAMIC PACKAGE
CASE 736
DIM
••
C
0
F
G
H
J
K
L
NOTES:
1. LEADS TRUE POSITIONED
WITHIN 0.25 mrn (n.Oln) DIA AT
SEATING PLANE AT MAXIMUM
MATERIAL CONDITION (DIM "D").
2. DIM "l" TO CENTER OF LEADS
WHEN FO RMEO PARALLEL.
•
MILLIMETEAS
MIN
MAX
26.80 27.81
9.14 9.91
INCHES
MI.
MAX
1.055 1.095
0.360 0.390
3.81 5.46
0.38 0.53
1.27 1.65
2.54 8SC
0.51
1.27
.30
0.20
2.54 4.32
9.91 10.41
- 15
0.25 0.89
0.150 0.215
0.015 0.021
0.050 0.1l65
0.1008SC
0.020 0.050
8 .012
0.100 0.170
0.390 0.410
1
0.010 0.035
CASE 736-01
6-9
•
•
MECHANICAL DATA (Continued)
- - - - - - - - - - 24-PIN PACKAGES - - - - - - - - - FRIT-SEAL CERAMIC PACKAGE
CASE 623
NOTES:
1. DIM "L" TO CENTER OF
LEADS WHEN FORMED
PARALLEL
2. LEADS WITHIN 0.13 mm
(0.005) RADIUS OF TRUE
POSITION AT SEATING
PLANE AT MAXIMUM
MATERIAL CONDITION.
(WHEN FORMED PARALLEl)
DIM
MILLIMETERS
MIN
MAX
INCHES
MIN
MAX
A
B
C
D
F
G
J
K
L
M
N
31.24 32.77
12.70 15.49
4.06
5.59
0.41
0.51
1.27
1.52
2.54 BSC
0.20
0.30
2.29
4.06
15.24 Bse
0°
15°
1.27
0.51
1.230 1.290
0.500 0.610
0.160 0.220
0.016 0.020
0.050 0.060
0.100 BSC
0.008 0.012
0.090 0.160
0.6008SC
0°
15°
0.020 0.050
CASE 623-04
FRIT-SEAL CERAMIC PACKAGE
CASE 623A
DIM
A
8
C
0
F
NOTES:
1. DIM "L" TO CENTER OF
LEADS WHEN FORMED
PARALLEl.
2. LEADS WITHIN 0.13 mm
(0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE
AT MAXIMUM MATERIAL
CONDITION. (WHEN FORMED
PARALLEL) .
G
J
K
L
M
N
MILLIMETERS
MIN
MAX
31.24 32.77
12.70 15.49
4.06 5.84
0.41
0.51
1.27
1.52
2.54 sse
0.20 0.30
2.29 1 4.06
15.24 Bse
15°
0°
0.51
1.27
INCHES
MIN
MAX
1.23,2_~
0.500 0.610
0.160 0.230
0.016 0.020
0.050 0.060
0.100 sse
0.008 0.012
0.090 0.160
0.600 sse
15°
0°
0.020 0.050
CASE 623A-02
6-10
MECHANICAL DATA (Continued)
- - - - - - - - - 2 4 - P I N PACKAGES (Continued)--------PLASTIC PACKAGE
CASE 700
MILLIMETERS
DIM MIN
MAX
A
31.37 32.13
13.72 14.22
B
3.94
5.08
C
0.56
0.36
D
F
1.02
1.52
2.54 BSC
G
1.65
H
2.03
0.20
0.38
J
K
2.92
3.43
15.24 BSC
L
1)0
150
M
1.02
N
0.51
NOTES:
1. POSITIONAL TOLERANCE OF LEAOS (0),
SHALL BE WITHIN 0.25 mm (0.010) AT
MAXIMUM MATERIAL CONDITION,IN
RELATION TO SEATING PLANE AND
EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEl.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
INCHES
MIN
MAX
1.235 1.265
0.540 0.560
0.155 0.200
0.014 0.022
0.040 0.060
0.100 BSC
0.065 0.080
0.008 0.015
0.115 0.135
0.600 BSC
0"
15 0
0.020 0.040
CASE 709-02
CERAMIC PACKAGE
CASE 716
[0::11"J
,0
. . . ___
1-
H
J~i
i:J1-o
._.~
A
NOTE:
1. LEADS TRUE POSITIONED WITHIN
0.25mm (0.010) DIA (AT SEATING
PLANE) AT MAXIMUM MATERIAL
CONDITION.
2. DIM "L"TO CENTER OF LEADS
WHEN FORMED PARALLEl.
___
~
iL----j
n--.-1
II
I ,
: iii
C
.:-."". 't;;:;j
':iij; ~
SEATrNG'UN~~
K ~J
L
I
\
M~ \r
MILLIMETERS
INCHES
DIM MIN
MAX
MIN
MAX
A 27.S4 30.99 1.088 1.220
B 14.94 15.34 0.588 0.604
0.105 0.170
2.S7
4.32
C
D
0.38
0.53
0.015 0.021
F
0.76
1.40 0.030 0.055
G
2.54 BSC
010 BS
H
0.76
1.78 0.030 0.070
J
0.20
0.30 0.008 0.01
K
4.19 0.100 0.165
2.54
L 14.99 15.49 0.590 0.610
M
100
100
N
1.02
1.52 0.040 0.060
CASE 716-06
6-11
•
MECHANICAL DATA (Continued)
- - - - - - - - - 2 4 - P I N PACKAGES (Continued)------_ __
CERAMIC PACKAGE
CASE 716
DIM
A
8
e
0
F
G
H
J
K
L
M
N
NOTE:
1. LEADS TRUE POSITIONED WITHIN
0.25mm (0.010) DIA (AT SEATING
PLANE) AT MAXIMUM MATERIAL
CONDITION.
2. DIM "L"TO CENTER OF LEADS
WHEN FORMED PARALLEl.
MILLIMETERS
INCHES
MIN
MAX
MIN
MAX
27.64 30.99 1.088 1.220
14.73 15.34 0.580 0.604
3.18
0.125 0.200
5.08
0.38
0.53
0.015 0.021
0.76
1.40 0.030 0.055
2.54 SSC
0.100 sse
0.76
1.78
0.030 0.070
0.20
0.30
0.008 0.012
2.54
4.57
0.100 0.180
14.99 15.49 0.590 0.610
100
100
1.02
1.52
0.040 0.060
CASE 716-07
I
6-12
I
I
,
,
•
SELECTOR
GUIDES
CROSS-REFERENCE
•
MOS Memories
RAM, EPROM, EEPROM, ROM
•
CMOS Memories
RAM, ROM
I
Bipolar Memories
TTL, MECL-RAM, PROM
•
Memory Boards
I
Mechanical Data
MOTOROLA Semiconductor Products Inc.
3501 ED BLUESTEIN BLVD., AUSTIN , TEXAS 78721 • A SUBSIDIARY OF MOTOROLA INC.
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19 Create Date : 2017:07:16 12:39:58-08:00 Modify Date : 2017:07:16 13:04:52-07:00 Metadata Date : 2017:07:16 13:04:52-07:00 Producer : Adobe Acrobat 9.0 Paper Capture Plug-in Format : application/pdf Document ID : uuid:853f863a-5fb0-9b46-b06b-e8687d6127e4 Instance ID : uuid:699e3c66-f05f-4244-9d5a-2d4166010dfd Page Layout : SinglePage Page Mode : UseNone Page Count : 384EXIF Metadata provided by EXIF.tools