1980_NEC_Microcomputer_Catalog 1980 NEC Microcomputer Catalog

User Manual: 1980_NEC_Microcomputer_Catalog
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, i'

ttlEC

I
I

CONTENTS
FUNCTIONAL AND NUMERICAL INDEXES
ROM ORDERING PROCEDURE

MEMORY SELECTION GUIDE
AND ALTERNATE SOURCE ,GUIDE

RANDOM ACCESS MEMORI ES

II
II
II
,

READ ONLY MEMORIES

MICROCOMPUTER SELECTION GUIDE
AND ALTERNATE SOURCE GUIDE

•
•II
~

JlCOM-4 SINGLE CHIP
4-BIT MICROCOMPUTERS

i

JlCOM-8 MICROPROCESSORS

JlCOM~8

SINGLE CHIP
8~BIT MICROCOMPUTERS,

JlCOM-8 PERIPHERALS

,,NEe Microcomputers, Inc. "
1980

Product Catalog

REFERENCE SECTION
Quality Assurance Chart
Representatives & Distributors

I
I
II
I
•

NOTES

2

NEe

NEe Microcomputers, Inc.
FUNCTIONAL INDEX
RANDOM ACCESS MEMORIES
Selection Guide. . . . . . . . • . . •.
Alternate Source Guide . . . • • '. .•
Dynamic NMOS RAMs
tLPD411 . . . . • • . • . . • . . . .
tLPD411A . . . • • . . . . • . • • .
tLPD416 . . . . . . . . . . • . • • .
tLPD21i8 . • . • . . . . . • . . . .
tLPD4164 . . • . . . . . . . . . . .
Static NMOS RAMs
tLPD410 . . . . . . . . . . . • . . •
tLPD4104 . . . . . . . . . . • . . .
tLPD2114L . . . . . . . . . . . • .
tLPD2147 . . . . . . . . . . . . . .
tLPD421 . . . • . • . • • . . . . . .
tLPD2167 . • • . . . . . . . . . . .
CMOS RAMs
tLPD5101 L . . • . . . . . . • . . .
tLPD444/6514 . • . • • . . • . . . .
tLPD445 L . . . • . • . . • • • . • .

8
9
11
19
27
36
37
43
47
53
59
63
67
69
75
79

READ ONLY MEMORIES
Selection Guide. . • . • • . • • . . •. 8
Alternate Source Guide . . . . . . .. 9
ROM Ordering Procedure . . . • . •. 6
Mask Programmable ROMs
tLPD2308A . . • . . . • . • . • . • 85
tLPD2316E . . . . . . . . • . . • . 89
tLPD2332A/B . . . • . . . . . • • • 93,
tLPD2364 . . . . . . . . . . . . . . 97
Field Programmable ROMs
(U.V. Erasable)
tLPD2716 . . . . . . . . . . . . . 101
tLPD2732 . . . . • • . . . • . • . 102
tLCOM-4SINGLE CHIP
4·BIT MICROCOMPUTERS
Selection Guide. . . • . . . . • • . •
ROM Ordering Procedure . • . . ••
tLCOM·42 . . . . . . . . . . • • . • .
tLPD548 . . • • . • . . . . • . • •
tLCOM-43/44/45 . . . . . . . . . . .
tLPD546 . . . . • . . . . • • . • .
tLPD553 . . . . • • . . . . • . • .
tLPD557L . . . . . . . . . . . • .
tLPD650 . . . . . . . • . ,. . . . .
tLPD547 . . . . . . . . . • . . • •
tLPD547L . . . . . . . . . . • . .
tLPD552 . . • . • • . . . . • . • •
tLPD651 . . . . . . . . . . . . . .
tLPD550 . . • . . . . . . . . . • .

104
6
109
11,3
115
121
123
125
127
129
131
133
135
139

tLPD550L . • . . . . . . . . . • •
/-lPD554 • • . . . . • • . • • ' ..•
tLPD554L . . . • . . . . . . • • •
tLPD652 • • . . . . . . . • . . . .
Evaluation Chips
tLPD555 . . . . ',' • • . • • . • .
tLPD556 . • • . •• • . .. . . • •
tLCOM·75
tLPD7520 . . . • . • . . . . . • •

II

141
143
145
147
149
153
157

tLCOM-8 MICROPROCESSORS
Selection Guide • . . . . • . . • • . .
Alternate Source Guide . . . . • . •
tLPD8080AF . . . . • . . • • . •
tLPD8085A . • . . • . . . • • • •

104
106
165
179

tLCOM-8 SINGLE CHIP.
8-BIT MICROCOMPUTERS
Selection Guide • . . . . • . . . . . •
Alternate Source Guide •.••.•.
ROM Ordering Procedure . . . • ..
tLPD7801 . • • . . • . . . . . . .
tLPD8021 . . . . . . . . . . . . .
tLPD8022 . . • • . • • . • . • • .
tLPD8041/8741A . . • . . • . . .
tLPD8048/8748/8035L . . . • •
tLPD8049/8039L . . . . . . . .

104
106
6
193
199
205
211
219
23'1

tLCOM-8 PERIPHERALS
Selection Guide . . . . . . . . • . • •
Alternate Source GU,ide . . . • . . •
tLPD765 . . . . • • • • . . . . • •
tLPD781 . . . . . . . . . . . . • •
tLPD782 • . • . • . . • . . • • . •
tLPD3301 . . . . . . . . . . . • .
tLPD7001 . • . • • . . • . . . . . .
tLPD7002 . • . • . . . . • . . • .
tLPD8155/8156 . . . . . . • • . •
tLPB8212 • • . • • • . . . • . • .
tLPB8214 • . . . • • . . • . • • •
tLPB8216/8226 . • • . . . . . • .
tLPB8224 . • • . . • . . • • • • .
tLPB8228 . • . . . . . . . • . . •
tLPD8,243 • • . • • • • . • . • • .
tLPD8251/8251 A . • . . • • . • •
tLPD8253 • • . . . • . . . . . . .
tLPD8255/8255A-5 • • . • • • . .
tLPD8257 . . . • • • • . • . • • .
tLPD8259 • • • . • • . . • . • . •
tLPD8279-5 • .. • • • . •. • • •
tLPD8355/8755A . . • . • • . . .

105
106
241
259
271
283
291
295
299
307
313
319
323
329
335
341
359
367
375
383
399
409

3

NOTES

4

.

.

NEe

NEe Microcomputers, Inc.
NUMERICAL INDEX
PRODUCT

PAGE

PRODUCT

~PD4·10

.. ' . . • . . . . . • . . . .

43

~PD4104

...............

47

~PD411

. . . . . . . . . . . • . . ..

11

~PD4164

. . . . . . . . . . . . . ..

37

. . . . . . . . . . . . ..

69

.....

19

~PD5101

~PD416 .. '. . . . . . . . . • . . ..

27

IlPD7001

~PD421

~PD411A

.....•.. "

L

. . . • . . . . . . . . . . . 291

................

63

j.£PD7002 . . . . . . • . . . . . . . . 295

IlPD444/6514 . . . . . . . ; . . . ..

75

~PD7520

~PD445L

79.

~PD7801

. . • . • . • . . . . . . . . 193

~PD8021

. . . . . . . . . . . . . . . 199

. . . . . . . . . . . . . ..

~PD546

. . . . . . . . . . . . . . . . 121

~PD547

. . . . . . . . . . . • . . . . 1.29

~PD547L

. . . . . . . . . . . . . . • 157

. ~PD8022 . . . . . . .. . . . . . . . 205

. . . . . . . . . . . . . . . 131

~PD8035L

~PD548

. . . . . • . . . . . . . . . . 113

~PD8039L

~PD550

. . . . . . . . . . . . . . . . 139

~PD8041

~PD550L

. . . . . . . . . . . . . . 219
. . . . . . . . . . . . . . 231
. . . . . . . .., . . . . . 21.1

. . . . . . . . . . . . . . . 141

~PD8048

. . . . . . . . . . . . . . . 219

~PD552

..• ' . . . . . • . . . . . . . 133

~PD8049

. . . . . . . . • . . . . . . 23.1

~PD553

. . . . . • . . . . . . . . . . 123

~PD8080AF

~PD554

. . . . . . . . . • . . . . . . 143

~PD554L

~PD8085A

. . . . . . . . . . . . . 165
. . . . . . . . . . . . . . 179

~PD8155

. . . . . . . . . . . . . . . 299

~PD555 . . . • . . . . . . . . . : .. 149

~PD8156

. . . . . . . . . . . . . . . 299

~PD556

. . . . . . . . . . . . . . . . 153

~PB8212

. . . . . . • . . . . . . . . 307

. . . . . . . . . . . . . . . 125

~PB8214

. . . . . . , . . . . . . . . . 313

~PD650

. . . . . . . . . . . . . . . . 127

~PB8216

. . . . . . . . . . . . . . . 319

~PD651

. . . . . . . . . . . . . . . . 135

~PB8224

. . . . . . . . . . . . . . . 323

~PD652

. . . . . . . . . . . . . . . . 147

~PB8226

. . . . . . . . . . . . . . . 319

. . . . . . . • . . . . . . . 145

~PD557L

~PD765

. . . . . . . . . . . . . . . . 241

~PB8228

. . . . . . . . . . . . . . . 329

~PD781

. . . . . . . . . . . . . . . . 259

~PD8243

. . . . . . . . . . . . . . . 335

~PD782

. . . . . . . . . . . . . . . • 271

~PD8251

. . . . . . . . . . . . . . . 341

~PD2114L

~PD2118

..............

53

~PD8251A

...............

36

~PD8253

. . . . . . . . . . . . . . . 359

. . . . . . . . . . ..

59

~PD8255

. . . . . . . . . . . . . . . 367

j.£PD2147 '"
~PD2167

. . . . . . . . . . . . • . 341

...............

67

~PD8255A-5

~PD2308A

............ "

85

IlPD8257 . . . . . . . . . . . . . . . 375

~PD2316E

..............

89

~PD8259

93

~PD8279-5

97

~PD8355

~PD2332A/B

. . . . . . . . . . . "

II

PAGE

~PD2364

...............

~PD2716

. . . . . . . . . . . . . . . 101

~PD8741A

~PD2732

. . . . . . . . . . . . . . . 102

~PD8748

~PD3301

. . . . . . . . . . . . . . . 283

~PD8755A

. . . . . . . . . . . • . 367

. . . . . . . . .'. . . . . . 383
. . . . . . . . . . . . . . 399
. . . . . . . . . . . . . . . 409
. . . . . . . . . . . . . . 211
•.......... . . . . . 219
. . . . . . . . . . . . . . 409

5

·NEC

NEe Microcomputers, Inc.
ROM ORDERING PROCEDURE -

MEMORIES AND MICROCOMPUTERS

The following NEC products fall under the guidelines set by the ROM Ordering Procedure:
JlPD2308A
JlPD2316E
JlPD2332A/B
JlPD2364
JlPD7801
JlPD8021
JlPD8022
JlPD8041
JlPD8048

JlPD8049
JlPD8355
JlPD546
JlPD547
JlPD547L
JlPD548
JlPD550
JlPD552

JlPD553
JlPD554
JlPD554L
JlPD557 L
JlPD650
JlPD651
JlPD652
JlPD7520

In order to facilitate the transferal of ROM mask information, NEC Microcomputers, Inc., is able to ac.cept mask patterns
in a variety of formats. These are intended to suit various customer needs and minimize the turnaround time. A listing of
the code must always be enclosed. The following is a list of valid media for code transferal.
•
•
•
•
•
•
•

Sample ROMs or ROM-based microcomputers
PROM/EPROM equivalent to ROM parts
NEC JlPD458 EEPROM
BNPF Paper Tapes
Hex Paper Tapes
Timesharing Files
Other (Contact NEC Microcomputers, Inc., for arrangements.)

Thoroughly tested verification procedures protect against unnecessary delays or costly mistakes. NEC Microcomputers,
Inc., will return the ROM mask patterns to. the customer in the most convenient format. Unprogrammed EPROMs, if sent
with the ROM code can be programmed and returned for verification.
Earth satellites and the world-wide GE Mark III timesharing systems provide reliable and instant communication of ROM
patterns to the factory. Customers with access to GE-TSS may further reduce the turnaround time by transferring files
directly to N EC Microcomputers, Inc.
The following is an example of a ROM mask transferal procedure. The JlPD8048 is used here, however the process is the
same for the other ROM-based products.
1. The customer contacts NEC Microcomputers, Inc., concerning a ROM pattern for the JlPD8048 that he would
like to send.
2. Since an EPROM version of that part is available, the 8748 is proposed as a code transferal medium, or alternatively, a paper tape and listing.
3. Two programmed 8748's are sent to NEC Microcomputers, Inc., with a listing and a paper tape as back-up.
4. NEC Microcomputers, Inc" compares the media provided and enters the code into GE-TSS. The GE-TSS file is
accessed at the NEC factory and a copy of the code is returned to NEC Microcomputers for verification purposes.
One of the 8748's is erased and reprogrammed with the customer's code as the NEC factory has it. Both 8748's
along with a new papertape and listing are returned to the customer for his final verification.
5. Once the customer notifies NEC Microcomputers,lnc., in writing that the code Is verified, and provides the mask
charge and hard copy of the purchase order, work commences immed iately on the development of.h is JlPD8048s.

6

,

,

','

I
MEMORIES···

7

NEe

NEe Microcomputers, Inc.
MEMORY SELECTIO.N GUIDE

DYNAMIC RANDOM ACCESS MEMORIES
/lPD411

4K x 1 TS

NMOS

150 ns

380 ns

+12,+5,-5

D

22

/lPD411-4

4K x 1 TS

NMOS

135 ns

320 ns

+15, +5,-5

D

22

4K x 1 TS

NMOS

200 ns

400 ns

+12, +5,-5

C

22

/lPD416

16Kx 1 TS

NMOS

120 hs

320ns

+12, +5,-5

C/D

16

/lPD2118

16Kx 1 TS

NMOS

100 ns

235 ns

+5

D

16

. /lPD4164

64Kx1TS

NMOS

200 ns

375 ns

+5

D

16

22

/lPD411A

STATIC RANDOM ACCESS MEMORIES
256 x 4 TS

CMOS

450 ns

450 ns

'+5

C

/lPD44416514

1Kx4TS

CMOS

200 ns

200 ns

+5

C

18

/lPD445L

1K.x 4 TS

CMOS

450 ns

450 ns

+5

C

20

/lPD2167

16K x 1 TS

/lPD5101L

"

NMOS

35 ns

5505

+5

D

20

/lPD2114L

1Kx4TS.

NI\iIOS,

150 ns

150 ns

+5

C/D

18

/lPD2147

4K x 1:r~

NMOS.

55 ns

55 ns

+5

D

18

/lPD410

~Kx 1TS: .... NMOS

90 ns

220 ns

+12,+5,-5

C/D

22

/lPD421

1K x 8 TS

NMOS

150 ns

150 ns

+5

D

22

/lPD4104

4Kx1 TS

, NrylOS

150ns

260 ns

+5

C/D

18

MASK PROGRAMMED READ ONI- Y MEMORIES
/lPD2308A

' 1Kx8TS

NMOS

450 ns

450 ns

+1)

C/D

24

/lPD2316E

2K x 8TS

NMOS

450 ns

450 ns

+5

C

24

/lPD2332A/B

4Kx8T$ .

NMos.

:'450ns

450 ns

+5

C

24

/lPD2332A/B- r

4K x 8 TS

NMOS

350ns., , 350 ns

+5

C

24

" . BKx B TS

NMOS

-+5

C'

24

. '

'j.ipb23S4

,;

.

,'450 ns
"

450 ns

,"

.flELDPROGFlAMMABLE READ ONL Y MEMOIUES(U.V.ERASABLEJ
/lPD2716
/lPD2732

Notes: IF) • CDTS -

8

Future Product
Read Mode
Plastic Package
Hermetic. Pack"ge
3-State

NEe

NEe Microcomputers, Inc.
. MEMORY ALTERNATE SOURCE GUIDE

I

MANUFAcTURER

AMD

EM&M

: PART NUMBER
2716 '
8308
9016
9060
9107
9114
9124,
9147
9216
2114
4200
4300
4402
8108

'.

DESCRIPTION

NEC REPLACEMENT

2K x8 EPROM
lKx8ROM
16K x.l ,DRAM
4K x 1 DRAM
4K x 1 DRAM
'lKx4SRAM
lKx4.SRAM,
4Kx 1 SRAM
2Kx8ROM

pPD2716
pPD23P8A
pPD416.: .' ', ..,
pPD411/pPD411 A
. pPD411/jlPD411 A
pPD2114L
'pPD2114L
pPD2147
pPD2316E

·lKx 4 SRAM
4K x lSRAM
4K xl SRAM
4Kx 1 SRAM
lK x8SRAM

pPQ2l14L
pPD410
pPD41Q
JlPD410
IlPD421

FAIRCHILD

F2114 '
F2716
F16K

lK x4SRAM
2Kx8 EPROM
16K x 1 DRAM

pPD2114L
pPQ2716
pPD416

FUJITSU

MBM2147
MBM2716
MBM2732 "
MB8107
MB8114
MB8J16
MB8216
M~830a
MB8414

4K x.l SRAM
2Kx 8 EPROM
4Kx 8 EPROM
41< x 1 DRAM
·lKx4SRAM
16K x 1 DRAM'
16K x 1 DRAM
1.K x 1 .ROM
lK x 4SRAM

pPD2147
pPD2716
pPD2732
pPD411/pPD4l1A
pPD2114L
pPD416
pPD416
pPD2308A

"

pPD444/6514

.

HARRIS

HM6501
HM6514

256 x 4 SRAM
lKx4SRAM

pPD5101 L
pPD444/6514

HITACHI

HM435101
:HM4716A
HM4816
HM4864
HM6147

256x4 SRAM
16K x, 1 DRAM
16K x 1 DRAM
16K x 1 DRAM
4Kx 1 SRAM

pPD5101L
pPD416
pPD2118
pPD4164
pPD2147

INTEL

2197
21.14
2117
211~

2147
2308A
2316E
2332
2364
2716
2732
5101

4Kx 1 DRAM
"
lK x4SRAM
.16K x 1 DRAM
16Kx 1 DRAM
4K x 1 SRAM
lK x8 ROM
2Kx8 ROM
4K x8 ROM
8Kx 8 ROM ..
2Kx 8 EPROM
4K x8 EPROM
256 x4SRAM

pPD411/pPD411A
pPD2114L
pPD416
pPD2118
pPD2147
pPD2308A
pPD2316E
pPD2332A/B
pPD2364
pPD2716
pPDi132
pPD5101 L

J

I

NEe

NECMicrocomputers, Inc.
MEMORY ALTERNATE SOURCE GUIDE

I

10

MANUFACTURER

PART NUMBER

INTERSIL

IM7114

MITSUBISHI

M5L2114LP

MOSTEK

MK2147
MK2716
MK30000
MK32000
MK34000
MK36000
MK4104
MK4116
MK4164
MK4516

MOTOROLA

,

DESCRIPTION

NEC,REPLACEMENT

1 K x 4 SRAM

tLPD2114L

1Kx 4SRAM

tLPD2114L

4K xl SRAM
2K x 8 EPROM
1K x 8 ROM
4K x8 ROM
2K x8 ROM
8K x 8 ROM
4K xl SRAM
16K x 1 DRAM
64K x 1 DRAM
16K x 1 DRAM

tLPD2147
tLPD2716
tLPD2308A
tLPD 2332A/B
tLPD2316E
tLPD2364
tLPD4104
tLPD416
tLPD4164
tLPD2118

MCM145101
MCM2114
MCM2147
MCM2716
MCM4116
MCM4516
MCM6616
MCM6664
MCM68A308
MCM68A316E
MCM68317
MCM68A332
MCM68A364

256 x 4 SRAM
1K x 4 SRAM
4K xl SRAM
2K x 8 EPROM
16K x 1 DRAM
16K x 1 DRAM
16K x 1 DRAM
64K x 1 D.RAM
1024 x 8.ROM
2Kx8ROM
2K x 8 ROM
4K x 8 ROM
8K x8 ROM

tLPD5101 L
tLPD2114L
tLPD2147
tLPD2716
tLPD41 6
tLPD41 6
tLPD416
tLPD41 64
tLPD2308A
tLPD2316E
tLPD2316E
tLPD2332A/B
tLPD2364

NATIONAL

LH2308A
MM5257
MM5280A
MM5281
MM5290
MM74C920

1024 x 8 ROM
4K xl SRAM
4K x 1 DRAM
4K x 1 DRAM
16K x 1 DRAM
256 x 4 SRAM

,i!PD2308A
tLPD4104
tLPD411/tLPD411A
tLPD411/tLPD411A
tLPD41 6
tLPD5101L

RCA

MWS5114

SIGNETICS

2316
2680
2690

2K x8 ROM
4K x 1 DRAM
16K x 1 DRAM

tLPD2316E
tLPD411/tLPD411A
tLPD416

T.r.

TMS4044
TMS4045
TMS4060
TMS4116
TMS4700
TMS4732

4K
1K
4K
16K
1K
4K

tLPD4104
tLPD2114L
tLPD411/tLPD411 A
tLPD41 6
tLPD2308A
tLPD2332A/B

TOSHIBA

TC5047

1K x 4 SRAM

xl SRAM
x 4 SRAM
x 1 DRAM
x 1 DRAM
x 8 ROM
x8 ROM

1Kx4SRAM

tLPD444/6514

tLPD445L

I

NEe

NEe Microcomputers, Inc.

fLPD411
fLPD411·1
fL PD411·2
IL PD411·3
J£ PD411·4

FULLY DECODED RANDOM ACCESS MEMORY
DESCR I PTION

The I1PD411 Family consists of six 4096 words by 1 bit dynamic N-channel MOS
RAMs. They are designed for memory applications where very low cost and large bit
storage are important design objectives. The I1PD411 Family is designed using dynamic
circuitry which reduces the standby power dissipation.
Reading information from the memory is a non-destructive. Refreshing is easily
accomplished by performing one read cycle on each of the 64 row addresses. Each
row address must be refreshed every two milliseconds. The memory is refreshed
whether Chip Select is a logic high or. a logic low.

FEATURES

PIN CONFIGURATION

I

All of these products are guaranteed for operation over the 0 to 70°C temperature
range.
Important features of the I1PD411 family are:
• Low Standby Power
• 4096 words x.1 bit Organization
• A single low-capacitance high level clock input with solid ±1 volt margins,
• Inactive Power/0.3 mW (Typ.)
• Power Supply: +12, +5, - 5V
• Easy System Interface
• TTL Compatible (Except CE)
• Address Registers on the Chip
• Simple Memory Expansion by Chip Select
• Three State Output and TTL Compatible
• 22 pin Ceramic Dual-in-Line Package
• Replacement for INTEL'S 21078, TI'S 4060 and Equivalent Devices.
• 5 Performance Ranges:
ACCESS TIME

RIW CYCLE

RMWCYCLE

REFRESH TIME

JlPD411

300 ns

470 ns

650 ns

2ms

JlPD411-1

250 ns

470 ns

640 ns

2 ms

JlPD411-2

200 ns

400 ns

520 ns

2 ms

JlPD411-3

150 ns

380 ns

470 ns

2ms

JlPD411-4

135 ns

320 ns

320 ns

2 ms

vss

vss

Ag

AS

AlO
All

cs
DIN
DOUT

Address Inputs

A7

CE

Chip_Enable

A6

CS

Chip Select

VDO
CE

DIN

Data Input

NC

AO

PIN NAMES
AO-All
AO-A5

A5

Refresh Addresses

DOUT

Data Output

WE

Write Enable

VOD

Power (+12V)

VCC

Power (+5V)

VSS

Ground

Al

A4

VSS

Power

A2

A3

NC

No Connection

VCC

WE

Rev/3

11

}LPD411
FUNCTIONALDESCHIPTION

CE Chip Enable
A single external clock input is required. All read, write, refresh and read-modify·write
operations take place when chip enable input is high. When the chip enable is low, the
memory is. in the low power standbY mode. No read/write operations can take place
because the chip is automatically precharging.
CS Chip Select
The chip select terminal affects the data in, data out and read/write inputs. The data
input and data output terminals are enabled when chip select is low. The chip select
input must be low on or before the rising edge of the chip enable and can be driven
from standard TTL circuits. A register for the cnip select input is provided on the chip
to reduce overhead and simplify system design.
WE Write Enable
The read or write mode is selected through the write enable input. A logic high on the
WE input selects the read mode and a logic low selects the write mode. The WE
terminal can be driven from standard TTL circuits. The data input is disabled when the
read mode is selected.
AO-A" Addresses
All addresses must be stable on or before the rising edge of the chip enable pulse. All
address inputs can be driven from standard TTL circuits. Address registers are pro·
vided on the chip to reduce overhead and simplify system design.
DIN Data Input
Data is written during a write or read-modify·write cycle· while the chip enable is high.
The data in terminal can be driven from standard TTL circuits. There is no register on
the data in terminal.
DOUT Data Output
The three state output buffer provides direct TTL compatibility with a fan-out of two
TTL gates. The output is in the high·impedance (floating) state when the chip enable
is low or when the Chip Select input is high. Data output is inverted from data in.
Refresh
Refresh must be performed every two milliseconds by cycling through the 64 addresses
of the lower·order-address inputs AO through A5 or by addressing every row witnin any
2-millisecond period. Addressing any row refreshes all 64 bits in that row.
The chip does not need to be selected during the refresh. If the chip is refreshed during
a write mode, the Chip select must be high.

-oVDD
-oVCC
-Q

VSS

~VBB

CE

Al0
A9 All

12

BLOCK DIAGRAM

,.,.PD411
ABSOLUTE MAXIMUM
RATINGS*

pPD411-4

pPD411 FAMILY
(EXCEPT 411-4)

... 0°Cto+70°C
-55°C to +150°C
-0.3 to +20 Volts
-0.3 to +20 Volts
-0.3 to +20 Volts
- 0.3 to +20 Volts
. . . . . . . . 1.0W

Operating Temperature.
Storage Temperature
All Output Voltages ..
All Input Voltages ...
Supply Voltage VDD ..
Supply Voltage VCC
Power Dissipation ...

eimum Rating~': may cause permanent
damage to the device. This is a stress rating only and functional operation of the devi~e at thes'e or
any-other ,conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximUn1 rating conditions for extended periods may affect device
reliability.

DC CHARACTERISTICS

"Ta

= 25"C

Ta ""

aOc to 70°C, VOO = +12V ±5%. Vee = +5V is%, Vee = -5V ±5%, Vss = av.

II

Except Voo:z: +16V ±5" for 4114.
PARAMETER

LIMITS

SYMBOL
MIN

Input Load Current
CE Input

Load Current

TYP(!)

TEST CONOITIONS

III

0,01

10

~A

ILC

0,01

10

~A

ILO

0.Q1

10

~A

200

~A

CE = 1.0V to 0.6V

Output Leakage Current
for High Impedance State

UNIT
MAX

VOO Supply Current

VIN = VIL MIN to VIH MAX
VIN - VILC MIN to VIHC MAX
CE = VILC Of,CS ~N1IH
Vo = OV to 5.25V,"

IDO OFF

20

IODON

35@

6O@

mA

CE '" VIHC, Ta'" ~5°C

~PD411

IDOAV

37
37

Cycle Time

~PD411·2

IDD AV
IDOAV

mA
mA

Cycle Time = 470 ris

~PD41H

mA

Cycle Time

~PD411·3

IDDAV

"P04114

IDOAV

41
55

60
60
60
65
80

Isa

5

100

~A

ICC OFF

0.01

10

~A

.during'CE off
Voo Supply Current,
during CE on
Average Vee Current

VBB S~pply Current

®

Ta

37

Vec Supply Current
during CE off

@

mA
mA

Cycle Time"" 320 'I)S

VIL

1.0

0.6

Input High Voltage

VIH

2.4

VCC+l

V

CE Input Low Voitage

VILC

1.0

0.6

V

CE Input "'igh Voltage

VIHC

Output Low Voltage

VOL

0

Output High Voltage

VOH

2.4

Notes:

VOO

2'5°C

=470 ns
= 4.00 ns
cvcie Time = 380'M

Input Low Voltage

VOO-l

III

,<,,'.

CE =VILC orCS -Vifi

V

VOO+l

V

0.40

V

IPL = 3.2 mA

V

10H =2.0 mA

VCC

X MIN MAX

Cycle Time

'CY

Time BetWeen Refresh

'REF

Address to CE Set Up Time

'AC

0

0

0

0

0

ns

Address Hold Time

'AH

150

150

150

150

100

ns

CE Off Time

'cc

130

170

130

130

80

~E

tT

0

40

0

40

0

40

0

40

0

40

ns
ns

'CF

0

130

0

130

0

130

0

130

0

130

ns

CEon Time

'CE

300

3000

260

3000

230

3000

210

3000

200

3000

WE,o'CEoff

'W

180

180

150

150

65

ns

'cw

300

260

230

210

200

ns

'OW

0

0

0

0

0

ns

D,N Hold Time

'DH

40

40

40

40

40

ns

WE Pulse Width

'WP

180

180

150

100

65

ns

Transition Time

CE Off to Output High
Impedance State

CE to WE
D,N '0 WE Se,

Note:

0(. C'

~ I"
f"', l\.
I

t-

V
0<:'

SPEC LIMIT: .2m.A. 2.4V

"

20

V
,/

,~

VV
[Z

SPEC LIMIT: 3.2inA.O.4V

~.

~

v

V 1/

10

~

V

t-

.2
VOH(V)

VOO - Vas

r-~~Y
§

e-W-

14

~Q~ ~~--

13

,

J..'fI

1000

r-- ~~:::~~~E~EGIO~

i--

-

~

t-.... i'-

100

~

0

.:'-.

"
E

I'-..

JY~ t"-

"-

w

IF

·f

I"-- I'-..

10

11

SPE~ LI~T' ~. m,

t7'
~ ?~ t-

~.'

10

..."
-:l

i'-

-5

I I I

I~

-6

-7

60

-8

Vae (V)'

Power consumption = V DD x I DDAV + V BB x I BB .

POWER CONSUMPTION

Typica.1 power dissiption for each product is shown below.
mW(TYP.)

CONDITIONS.

450

'fa = 25° C;tCY = 470ns, tCE = 300ns

/oIPD411-1

. 450

-r- a =26° C, t~y= 470ns; tCE = 260ns

/oIPD411-2

. - 450

Ta = 25° C, tey= 400ns, tCE = 230ns

/oIPD411-3

550

Ta.= 25° C, tcy - 380ns, tCE = 21 Ons

/oIPD411-4

660

Ta - 25° C,tey = 320ns, :te.E - 200n5

/oIPD411

See above curves for power dissipation:versus eycle time.

16

JLPD411
300

100

CURRENT WAVEFORMS

~,.,
ICE ImAI

400

500

·I _ _·~\~C_·
.

' : f,---,--···

---,-..;.~_~_----.;...[\__. _

2:·.jt-----'-1--,-1
·20

r - ._ _ _ _ _

1"-----:-_ __

---,----\,,1\

120 ~~--~----------~--------~~----~--~~.----80 r---~r-~-------------------+-+~---------r~~~

IOOlmAI

IOOON

.40

w

r---------~--------~----------~~--------------

188 1mAI

·20 ~-----\--t-----'~----------------------------+-+-~

·40 '---------'.......--------------------------------~-""'----

PACKAGE OUTLINE
IlPD411D

~----------A----------~~

M

ITEM

A
B

MILLIMETERS

27.43 MAX
1.27 MAX

C

2.~±0.1

0
E
F
G
H
I

0.42 ± 0.1
25.4 ± 0.3
1.5 ± 0.2·
3.5. ± 0.3
3.7 ±0.3
4.2 MAX
5.08 MAX
10.l6±0.15
9.1 ±0.2
0.25 ± 0.05

J
K
L
M

INCHES

1.079 MAX
0.05 MAX
0.10
0.016
1.0
0.059
0,138
0.145
0.165 MAX
0.200 MAX
0.400
0.358
0.009

SP411-10-79-GY-CAT

17

I

NOTES

18

NEe

NEe Microcomputers, Inc.

","PD411A

","PD411A-1
","PD411A-2

4096 BIT DYNAMIC RAMS
DESCRIPTION

The tLPD411 A Family consists of four 4096 words by 1 bit dynamic N-channel MOS
RAMs. They are designed for memory applications where very low cost and large bit
storage are important design objectives. The tLPD411A Family is designed using
dynamic circuitry which reduces the standby power dissipation.
Reading information from the memory is non-destructive. Refreshing is easily
accomplished by performing one read cycle on each of the 611 row addresses. Each
row address must be refreshed every two milliseconds. The memory is refreshed Whether
Chip Select is a logic high or a logic low.

FEATURES

•

ll

Low Standby Power

• 4096 words x 1 bit Organization
• A single low-capacitance high level clock input with solid ±1 volt margins.
•

Inactive Power 0.7 mW (Typ.)

•

Power Supply +12, +5, -5V

•

Easy System Interface

• TTL Compatible (Except CE)
• Address Registers on the Chip
• Simple Memory Expansion by Chip Select
• Three State Output and TTL Compatible
•

LLpinPlastic Dual-in-Line,Package

•

Replacement for INTE L's 21078, Tl's 4060 and Equivalent Devices.

•

3 Performance Ranges:

~PD4llA
~PD4llA-l
~PD4llA-2

PIN CONFIGURATION

Vss
Ag
A10
A11

Cs
DIN

ACCESS TIME

R/W CYCLE

RMWCYCLE

REFRESH TIME

300 ns
250 ns
200 ns

470 ns
430 ns

650 ns
600 ns
520 ns

2 ms

400 ns

2ms
2 ms

PIN NAMES

Vss
AS

AO-All

Address Inputs

AO-A5

Refresh Addresses

A7

CE

Chip Enable

AS

es

Chip Select

VDD
CE

DIN

Data Input

DDUT
WE

Data Output
Write Enable

VDD

Power (+12VI

DOUT

NC

AO

As

A1

A4

AZ

1'.3

VCC

WE

VCC

Power (+5VI

VSS

Ground

VBB

(Pow•. -5VI

NC

No Connection

Rev!l

19

J-LPD411A
CE Chip Enable
A single external clock input is required. All read, write, refresh and read-modify-write
operations take place when chip enable input is high. When the chip enable is low, the
memory is in the low power standby mode. No read/write operations can take place
because the chip is automatically precharging.

FUNCTIONAL DESCRIPTION

CS Chip Select
The chip select terminal affects the data in, data out and read/write inputs. The data
input and data output terminals are enabled when chip select is low. The chip select
input must be low on or before the rising edge of the chip enable and can be driven
from standard TTL circuits. A register for the chip select input is provided on the chip
to reduce overhead and simplify system design.
WE Write Enable
The read or write mode is selected through the write enable input. A logic high on the
WE input selects the read mode and a logic low selects the write mode. The WE
terminal can be driven from standard TTL circuits. The data input is disabled when the
read mode is selected.
AO-All Addresses
All addresses must be stable on or before the rising edge of the chip enable pulse. All
address inputs can be driven from standard TTL circuits. Address registers are pro·
vided on the chip to reduce overhead and simplify system design.
DIN Data Input
Data is written during a write or read·modify·write cycle while the chip enable is high.
The data in terminal can be driven from standard TTL circuits. There is no register on
the data in terminal.
DOU:r Data Output
The three state output buffer provides direct TTL compatibility with a fan-out of two
TTL gates. The output is in the high·impedance (floating) state when the chip enable
is low or when the Chip Select input is high. Data output is inverted from data in.
Refresh
Refresh must be performed every two milliseconds by cycling through the 64 addresses
of the lower·order·address inputs AO through A5 or by addressing every row within any
2·millisecond period. Addressing any row refreshes all 64 bits in that row;
The chip does not need to be selected during the refresh. If the chip is refreshed during
a write mode, the chip select must be high.

BLOCK DIAGRAM
AO
A1

A2
A3

A4O--_'"i

AS

«
w

«
w
o

u.
u.

o
u

:::J
CIl

w

en
w

-----:

I-.--.()Cs
WE
TIMING
CE

20

GENERATOR

JA-PD411A
ABSOLUTE MAXIMUM
RATINGS*

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . O°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-'5SoC to +l25°C
Output Voltagelr-_-+- V'H
DIN CAN CHANGE

----r--tt---------'lf--------4-~~\~~~~-V"

'CO--_

Dour =-HiGH- -

-I-'----'@'t======::jr-l
Ii

---rl-__-_L7-_-_-_-'A-CC-_-_-_.:;_~_~_-_-_~~4--------~---~~~~_VOL
IMPEDANCE

Notes:

CD

UNDEFINED

(J)

For refresh cycle, row and column addresses must be stable tAC and
remain stable for entire tAH per'iod.

®

VDD - 2V is, the. reference level for measuring timing of CE,.

@

VSS

@

VIHMIN is the referencEl level for measuring timing of the addresses,
CS, WE and DIN.

@

+ 2V is the reference level for measuring ti~ing of CEo

VILMAX is the reference level for measuring timing of the addresses,
and DIN.

CS, WE

®

VSS

(j)

VSS

+ O.SV is the reference level for measuring timing of DOUT.

®

WE

must be at V I H until end of teo'·

+ 2.0V is the reference level for measuring timing of DOUT·

23

t ODAV ..... ICY

70

60

1-1- I-

1.25

I I
II
SpJC'LI~IT

T 'I

1\

I

t CE =,

I I
J I

~

"'i', ',"

l/
"

1

'"

S

'0.25

II I I
I I I I I
IOH~ V OH

I"

30

I'

~

I'---

IOL - VOL
50

·40

_0

- I--

NORMALIZED CYCLE TIME

50

E

I

2 .

50

h! C}

:<

J

CONST. -

,,\

0.5

.. -'--

Typ DOAV

~- ....,.rcyrli~· 400n
30

I-- I- I--IMIN:MUJ CY~LE ~,'MEI-- I--

.. 1.0

-~

·20

'" ~
"""
" """

10

1/

"v / V
,.'%v /'
l/'l

>-

">0" 0"

20

I'\.

f-

1,/

V

40

I"

TYPICAL OPERATING
CHARACTERISTICS

SPEC LIMIT; .2rrt,2.4V

10

~

~

I
I

/ V

//
h
,/-

SPEC LIMIT: 3.2mA,O.4V

I-

0

ttL
r~~

Voo - VBB

14

13

:E
0
>0

12

::!

~;

,..

1000

'""'-

r- 6~~R:ri~~E~EGtON

!""

k>

I"--

~I~I

100

v-

...............

J
w
~

I

10

11

10 "

10

./

c.7'

SP~1 ,LltT :

~ c.._

fms

I I
20

40
Ta eel

60

·B

·4

POWER CONSUMPTION

Power consumption = VDD x IDDAV + VBB x IBB
Typical power dissipation for each product is shown below,

mW(TVP.1

CONDITIONS

~PD411A

460mW

. Ta = 25 C, tcy= 470 ns, tCE = 300 ns

~PD411A.l

460mW

T a = 25°C, tty = 430 ns, tCE = 260 ns

j.lPD411A·2

460mW

T a = .25°C,. tcy = 400 ns, tCE = 230 ns

See curve above for power dissipation verSuS cyel!! time.

24

,",PD411A

CURRENT WAVEFORMS.: 

w

10

(.)

>

5

0

50

100

150

200

250

300

350

Aoo

450

500

TIME (ns)

100.
80
~

.5

60

0

9

•

.40
20

0

50

100

l!?O

200

300

350

400

450

500

TIME (ns)

30
~

.5

'"

!!'

20
10
0
450

500

-10

-20

~

40

.5
(.)

!:?

30
20
10

0

50

100

200

150

250

300

350

400

450

500

TIME (ns)

~

.5

w

30
20

!:?
10
251')

0

I

I

50

100

150

200

300,

3!\Q

400

450

I

500

..

TIME (ns)

-10
-20
-30

Note:



Relative to VBB
Relative to VSS

COMMENT: Stress above those I,Isted Under "Absolute Maximum Ratings" mav cause permanent
damage to the device. This Is a stress rating only and functional operation of the device at these or
any other conditions above those Indicated in the operational sections of th is specification is not
Implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

*Ta = 25°C
T a = O°C to 70°C, VDO = +12V ± 10%, VBB = -5V ± 10%, VCC = +5V ± 10%,
VSS= OV
PARAMETER
I nput Capacitance
(Ao-A6), DIN
I nput Capacitance
RAS, CAS, WRITE
Output Capacitance
(DOUT)

28

SYMBOL

MIN

LIMITS
TYP MAX

UNIT

CIl

4

5

pF

CI2

8

10

pF

Co

5

7

pF

TEST
CONDITIONS

CAPACITANCE

f'PD416
DC CHARACTERISTICS

Ta

~ O°C to +70°CC!),

VDO

= +12V

±

10%, VCC

= +5V

±

10%, Vee

= -5V

±

10%, VSS

LIMITS
PARAMETER

UNIT

SYMBOL

MIN'

TYP

MAX

Supply Voltage

VDO

10.8

12.0

13.2

V

Supply Voltage

VCC

4.5

5.0

5.5

V

Supply Voltage

VSS

0

0

0

V

Supply Voltage

Vss

- 4.5

-5.0

-5.5

V

@
@@
@
@

Input High. I Logic 11
Voltage, RAS, CAS,
WRITE

VIHC

2.7

7.0

V

@

VIH

2.4

7.0

V

@

VIL

- 1.0

0.8

V

Input High'ILogic 11
Voltage, all inputs

except RAS, CAS

= OV

TEST
CONDITIONS

WRITE
Input Low '( Logic 0)

Voltage, all inputs
Operating VOO Current

Standby VOO Current

RefreShl~1l Speeds.
VOD

35

IDOl

1.5

1002

rnA
rnA

RAS = VIHC, 00UT
::: Hi9h Impedance

except IlP0416-5

IOD3

25

rnA

IlP0416-5

ID03

2·7

rnA

Currentl

Page Mode V D D
Current
Operating
Current

Vee

Standby Vee Current

27

ID04

ICC2

-10

10
• ___0 -

II

®

RAS cycling, CAS =
VIHC; tRC = 375 ns

®

RAS - VIL, CAS
cyCling; tpc =.
225ns@

rnA

IlA

ICCl

@
RAS, CAS cycling;
tRC = tRC Min.

I

IlA

-.---

RAS, CAS cycling,

tRC = 375 ns@
RAS = VIHC,
00UT = H~gh
Impedance

-.-

RAS cycling;
Refresh

Vee Current

ICC3

-10

10

IlA

CtiS·=
iRC

Page Mode VCC

Current

ICC4

=

VIHC.
375 n,

IlA

RAS = VIL. CAS
cyclmg, tpc
225n,@

ISSl

200

IlA

RAS. CAS cycling;
tRC - 375 n,

Standby VSS
Current

ISS2

100

IlA

RAS" VIHC,
DOUT" H'gh
Impedance

Refresh Vse
Current

ISS3

200

IlA

CtiS =

Operating VSS
Current

Page Mode'VSS

Current

Input Leakage

RAS
200

ISS4

IlA

IIIL!

-10

10

IlA

Output Leakage

IOILI

-10

10

IlA

Output Low Voltage
I Logic 01

VOH
VOL

2.4
0.4

= VIL,

CAS

cycling;

tpc

(any input)

Output High Voltage
I Logic 11

RAS cycling,
VIHC;
= 375 ns

'RC

= 225 ns

VSS - -5V, OV '"
VIN '" +7V,
all other pins not
under test::: OV
.DOUT is disabled,.
OV '" VOUT '" +5.5V

V

lOUT

= -5 rnA@

II

lOUT

= 4.2 rnA

Notes:C!) T a 'is 'specified here for operation at frequencies to tRC::;;' tRC (min). Operation at higher cycle rates with reduced
ambient temperatures and high power dissipation is permissible, however, provided Ae operating parameters are met.
See Figure 1 for derating curve.
.
@Allvoltages referenced to VSS.
.
cr:> OutPut voltage will swing from VSS to Vee when activated with no current loading. For purposes of maintaining
data in standby mode, Vee may be reduced to VSS without affecting refresh operations or data retention. However,
the VOH (min) specification is not guaranteed in this mode.
@ 1001, 10D3, and 1004 depend on cycle rate. See Fi,gures 2, 3 and 4 for 100 limits at other cycle rates.

® il:;'~d~~~~~f3'5~~~~1 tU:~~t~~t~t~~~~j~~h~Ut\~:~~~o~~s~s~~g~f l~vae~aC:t~u~~~ti: ~~v~ected through' a low

2.9

p.PD416
DERATING CURVES
CYCLE T(ME tRC (nsl
320
500 400 375

1000

300 250

50 rnA
I'PD416-5

1000

u
°

70

500

I
-Ta(MAX)

4O~

320
1375 1:00

,,:
:;;
60

ffZ

w

iii
:;
50

-'

q(~~

0..
0..

~y "

;:)

en

20 rnA

_0

.~./

X

-'
0..
0..

:l
III

20 rnA

~

o
o

-

X

~ lOrnA

.....

o

---- -"\'{\',

.....

o
o

1.0

2.0

3.0

CYCLE RATE (MHz) = 10 3 /tRC (ns)
FIGURE 3
Maximum I D03 versus cycle rate for device
operation at extended frequencies.

30

SPEC LIMIT

u

4.0

o

1 .0

2.0

3.0

4.0

5.0

CYCL,E RATE (MHz) = 10 3 /tRC (ns)
FIGURE 4
Maximum IDD4 versus cycle rate for device
operation in page mode.

6.0

fLPD416
AC
CHARACTERISnCS

T. = o"C mHO·C, VOD· +12V:Il ~h. Vcc· tSV

t

1• • VBB""-I,v':i: 10%. V$s·,,:2 V
~lilliTS

TEST
CONDITIONS
~rnrf!ldorWfit•

.;y... ,,,",, "

,'~tj.,...fri:l~
Access time fr~m

,CAs' ,

@®

,

, ",,200

Output buffer
lU:rn-off del,ay'

tOFF

ttilniitlOntitne
!~!tIt and fall~

I. rn pT.chlirg. tim. .

,"T " /

mhokftim8'

"3

"'AS

,300

IRSH

200

. teAS

~

I"

CAs' purse wi~th

35

'0
',3

200

. AAs pul .. ~ttl

®®

80

100

,120

150

10.000

250

:'0,OQO

10.000

1~

200

32,000

10.000

135

15Q

32.000

100

135

166'

10,000

100

, 35

100

100

120

10,000

80
.10.000

80

,10,000

RASto~d8lav
time

II

®

CASto~

precharge time

Aowaddress
S8t-uptime

Rowaddr.

lRAH

hold time
Colurnn~ress

set-uptime

Column address

leAH

hold Time

Column address hold
time referenced to
"AS

40

35

-10

-10

90

75

190

160

25

20

15

~,o

-10

55

45

40

120

95

80

-10,

Read command
set-uptlme

,0

Read command
hold time

,0

Write command
hold time

90

75

55

190

160

120

90

'n.

40

Write command

hold time
,.flfeneed to FiAS

tWCA

Write command
pulse width

'WI'

Write cOmmand to
RAs lead time

tRWL

120

Write command
CASlnd time
"

tCWL

120

Data-in set-up time

'OS

to

®

.5

:

70

40

50

50

50

50

45

tDHA

190

150

120

95

.0

'ep

120

100

" ,80

60

60,

twcs

,20

-20

-20

-'20

CAS to WAITE
deJay

tewD

140

125

95

70

80

AASto WAITE
deley

tAWD

240

200

150

120

120

CAS precharge time
(for page mode
cycle' sn Iy)
pe~iod

®
®

',0

55

Refresh

@

95

70

75

Dete·in hold time
referenced to FiAS

WA ITE1:ommand
set,uptime

G)

. ',"55

60

,90

Data·in hold time'

Notes:

75

95

40

tREF
'no

@

@

Ac measurements assume IT = 5 ns.
.
VIHC (min) or VII; (mini andn-chipto simplify
system timing requirements.

FEATURES

• 4096 Words x 1 BitOrganization
•
•
•
•
•
•
•
•
•
•
•
•

PIN CONFIGURATION

Fully Decoded
TTL Compatible (except CEI
High Speed-Access Time: 90 ns max.
Cycle Time: 220 ns min.
Static Operation - No Refresh Required
Standby Power: 75 mW max.
Active Power: 470 mW typo
Supply Voltages: VDD = +·12V. VCC = +5V. Vaa = -5V
Address Registers on the Chip
Three State Output
Standard 22 Pin Ceramic Dual-in-Line Package
Pin Compatible with J.lPD411 and Other 4K Dynamic RAMs

Vas
Ag

vss
AS

AlO

A7

A11

AS

cs

VDD
CE

DIN
DOUT
AO

INC)
A5

Al

A4

A2

A3
WE

VCC

Rev!1

43

,",PD41 0

BLOCK DIAGRAM

AO
A1

ROW
DECODER
AND
SUFFER
REGISTER

A2
A3
A4

MEMORY
-ARRAY
',64 x 64

A5

CE

DIN
WE

esPOUT

Operating Temperature ......•.•..••..••....••....•...• O°C to +70·C
Storage Temperature .••....•..•...••......•••.••.•.. -65·C to +150·<:'r.\
All Output Voltages .•.•...•••••...•.....••.••.••.• -0.3 to +20 Volts0
All Input Voltages. . . . • • . • . • . . • • . . . . . . • . . . . . • • . . . .• -0.3 to +20 Volts(!)
Supply Voltage VOO . : • • • • . • • . • • . . . • . . . . . . . • • • • • . .• -0.3 to +20 Volts(!)
Supply Voltage VCC .... : 'I' . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 to +20 Volts(!)
Supply Voltage VSS .•.•. ;~. . • • . • • . . . • . . . . . . • . . . . • •• -0.3 to +20 Volts(!)
Power 0 issipation . . . . . .• .0.. • • • • • • • • • • • • • • . • • • • • • • • • • • • . • • •• 1.0v!/

ABSOLUTE MAXIMUM
RATINGS*

Note: (!) Relative to VBB
COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute miU(jmum rating conditions for extended periods may affect device
reliability.
*Ta

= 2SoC
Ta'" 0 C to 70' C' VDD

=

12V

+

5%' Vee

=

5V • 5%' Ves = -5V

+

5%- VSS = OV

LIMITS
PARAMETER

'SYMBOL

MIN

MAX

UNIT

III

10

.A

CE Input leakage Current

ILC

10

.A

VIN = VILCMIN to

Output leakage Current

ILO

10

.A

CE - VllC or

Input Leakage Current

DC CHARACTER ISTICS

TEST
CONDITIONS
VIN - VILMIN to
V1HMAX

VIHCMAX

CS = VIH
Vo = OV to 5.25V
VOO Supply Current
during eE off

IOOOFF

200

"A

CE = -l,OV toO.6V

VOO Supply Current
during CE on

1000N

20

mA

CE

jJPD41 0
jJPD41 0·'

IOOAV
IODAV

.PD41
PD410.3

10D, V

24
32
45
45

mA
mA
mA
mA

Minimum Cycle Time

Average VOO
Current

I·

'DOAV

Vas Supply Current

IBS

100

"A

Vee Supply Current
during CE off

ICCOFF

15

mA

Average Vec Current

'CCAV

21

mA

Input low Voltage

VIL

-1,0

Input High Voltage

VIH

2.4

CE Input Low Voltage

VILe

-1.0

CE Input High Voltage

VIHC

VOO-1

Output Low Voltage

VOL

0

Output High Voltage

VOH

2.4

Ta

~=Vllcor

CS

0.6

= VIH

00UT = No load

V
V

VCC+1

0.6

V

VOO+l

V

0.4
VCC

V

IOl = 3.2 mA

V

IOfj

= 2.0mA

= O·C to 70·C; VOO = 12V ± 5%; VCC = 5V ± 5%; VBB = -5V ± 5%; \ISS = OV
LIMITS
PARAMETER

SYMBOL

TYP

MAX

UNIT

TEST
CONDITIONS

6
6

pF

VIN = VSS

pF

VIN = VSS

B

10

pF

VIN =VSS

CWE

5
8

7
10

pF
pi

VOUT-VSS
VIN -VSS

GeE

18

27

pi

VIN - VSS

CAD
Ccs

DIN Capacitance

CIN
COUT·

CE Capacitance

MIN

4
4

Address Capacitance
CS Capacitance
00UT Capacitance
WE Capacitance

44

= VIHC

CAPACITANCE

).LPD41 0
AC CHARACTERISTICS

Ta = O°Cto 70°C;VDD= 12V ± 5%; Vee= 5V ± 5%;VBB= -5V ± 5%; VSS ",OV

L
SYMBOL

I

LIMITS
410-1

410
PARAMETER

MIN

MIN

MAX

410-2

MAX

MIN

410-3

MAX

MIN

MAX

UNIT

TEST
CONDITIONS

READ, WRITE AND READ·MODIFY-WRITE

tAC

0

0

0

0

n,

tAH

90

70

50

50

n,

CE Off Time

tcc

190

140

90

90

eE Transition
Time

'T

0

40

•0

40

0

40

0

40

n,
n,

CE off to Output
High Impedance
State

'CF

0

90

0

90

0

90

0

90

n'

Cycle T'ime

2000

Address to CE

Set Up Time
.Address Hold

Time

READ

ICY

440

eE on Time

'CE

230

eE Output

'CO

190

140

90

80

n,
n,
n,

Access
Time

tAce

200

150

100

90

n,

CE to WE

'WL

20

20

WE to CE on

'WC

0

0

~'!

330
2000

170

220
2000

220

2000

110

110

20

20

0

0

tr'" 10 ns
Load = 50 pF + ITTL
Ref'" 2.0 or a.BV
tAce = tAC

+tco+tr

n,
n,

I

WRITE
Cycle Time

ICY

440

CE on Time

ICE

230

we to CE off

'w

130

100

70

70

330
2000

170

220
2000

220

110

2000

110

no
2000

eE to WE

'cw

130

100

70

70

DIN to WE
Set Up

'ow

0

0

0

0

DIN Hold Time

'OH

60

40

20

20

WE Pulse

'WP

130

100

70

70

n,
n'

tRWC

560

420

280

no

tCRW

350

Width

tT'" 10,ns

n,
n,
n,
n,

READ-MODiFY·WRITE
Read-Modify·

280

tT'" 10 ns

Write {RMW)
Cycle Time
CE Width

2000

260

2000

2000

170

170

2000

no

During RMW

n,
n,
n,

0

0

0

0

'w

130

100

70

70

'WP

130

100

70

70

DIN roWE
Set Up

'OW

0

0

0

0

no

DIN Hold
Time

tOH

60

40

20

20

n'

WE to CE on

'WC

WE to CE off
WE Pulse
Width

ICE
to Output
Delay
Access Time

'CO

190

140

90

80

tAce

200

150

100

90

I~-----l

PACKAGE OUTLINE
j.LPD410D

n'
n,

Load - 50 pF + ITTL,
Ref ~ 2:(\ or O.BV

tACC eo tAC
+ teo:+: tT

,.,

(~m-)IJ
..LI~~
i--LI
H

TJ '.

_ I.
,

-g-

!

:

:

'

J

I

~cf--

i

Fr--.I

'

IG
--',---

M

B

ITEM
A
B
C

0
E
F
G

H
I
J
K
L

M

MILLIMETERS

INCHES

27.43 Max.
1.27 Max.
2.54 + 0.1
0.42 ±0.1
25.4 ± 0.3
1.5 ±0.2
3.5 ±O.3
3.7 ± 0.3
4.2 Max.
5.08 Max.
10.16 ± 0.15
9.1 ± 0.2
0.25 ± 0.05

1.079 Max.
0.05 Max.
0.10
0.016
1.0
0.059
0.138
0.145
0.165 Max.
0.200 Max.
0.400
0.358
0.009

45

JLPD41'O
TIMING WAVEFORIYIS
READ CYCLE
CE

ADDRESS
ANDCS

DDUT

WRITE CYCLE
CE

ADDRESS
ANDCS

WECAN CHANGE

----+---f:L..--L.-Hf-'--:-----+---

VIL

----_+\~~~~---_+~~~.~~--~----- VIH

DIN STABLE
-----+,~-------+--~~---_+----VIL

HIGH::-=-:-:.:-;:jl---~----t;;......;;.t
IMPEDANCE

------~---------+--~

READ-MODI FY-WRl'tE CYCLE

VOH

UNDEFINED
j----VOL

rI;==~~=~~LF;:=:=;:cc:==9
tCRW

CE

ADDRESS
ANDCS

WE

Notes:

(j)

VOO - 2V is the reference level for mea~uring timing of CEo

(2)

VSS

@

VIHMIN is the reference level for measuring timing of the addresses,

+ 2V is the reference level

for measuring timing of CEo

CS. WE and DIN.
@ VllMAX is the reference level for measuring timing of the. addresses.

CS. WE and DIN.
@


VSS + 2.0V is the reference level for measuring timing of COUTo

Vss + O.SV is the reference level for measuring timing of COUTo

 W£ must be at VIH until end of tcO.
The information presented in th is document is believed to be accurate and reliable. The information is subject to change without notice.
SP410-7-78-2.SK-GY

46

NEe

NEe Microcomputers, Inc.

p,PD4104
p,PD41 04·1
p,PD41 04·2
pPD4104-3

4096 x 1 STATIC NMOS RAM
OESCR IPTION

FEATURES

The IlPD4104 is a high performance 4K static RAM. Organized as 4096 x 1, it uses
a combination of static storage cells with dynamic input/output circuitry to achieve
high speed and low power in the same device. Utilizing NMOS technology, the
IlPD4104 is fully TTL compatible and operates with a single +5V ± 10% supply.

I

• FastAccessTime-150ns (IlPD4104-3).
• Very Low Stand·By Power - 28 mW Max.
• Low VCC Data Retention Mode to +3 Volts.
• Single +5V ±10% Supply.
• Fully TTL Compatible.
• Available in 18 Pin Plastic and Ceramic Dual·in-Line Packages.
• 4 Performance Ranges:

SUPPLY CURRENT
ACCESS TIME

RIWCYCLE

ACTIVE

STANDBY

LOWVcC

/JPD4104

300 ns

460 ns

21 rnA

5mA

5mA

/JPD41 04-1

250 ns

385ns

21 rnA

5mA

3.3 rnA

/JPD41 04-2

200 ns

310 ns

25 rnA

5mA

3.3 rnA

/JPD41 04-3

150 ns

260 ns

40 rnA

5mA

3.3mA

PIN CONFIGURATION
A3

VCC

A2

A5

A1

A4

AO

A7

A11

A8

AlO

Ag

DOUT

A6

WE

DIN

VSS

CE

PIN NAMES
AO-A11

Address Inputs

CE

Chip Enable

DIN'

Data Input

DOUT

Data Output

VSS

Ground

VCC

Power (+5V)

WE

Write Enable

Rev/2

47

fLPD4104
AO
A1

BLOCK DIAGRAM

ROW
OECODER
AND
BUFFER

A2
A3
A4
A5

MEMORY
ARRAY

64 x 64

CE

OIN

-;---.L.---"_f-__"'~

COLUMN
DECODER AND
BUFFER

°OUT

Operating Temperature . . . . . . . . • . . . . . . . . . . . . . . . . . . . . •. O· C to +70· C
Storage Temperature (Plastic Package) . • . . . . . . . . . . . . . . . . . -55·C to +125·C
(Ceramic Package) . . . . • . . . . . . . • . . . . . -65·C to +150·C
Voltage on Any Pin . . . . • . • . . • . • . . . . . . . . . . . • . . • • . . -1 to +7 Voltsgic "1" Voltage All Inputs
Logic "0" Voltage All Inputs

4.6
2.2
-,.0

VCC
VIH
VIL
ICC,
ICC,
ICC,
ICC,
ICC2
IlL

jlPD4'04
jlPD4'04-'
jlPD4'04-2
Current
jlPD4'04-3
Standby VCC Power Supply Current
Input Leakage Curront (Any Input)
Output Leakage Current

:~=r~~~y

UNIT



100
100
300

LIMITS
4104-1
4104-2
MIN
MAX MIN
MAX
3.0
3.0
3,3
3,3
100
100
100
100
250
200

TPPD

150

125

VIH
TRC

2.2
600

2.2
600

SYMBOL

4104
MIN
MAX
3.0
5.0

100
2,2

600

4104-3
MIN
MAX
3.0
3,3
100
100
160
100

n.

2.2
600

V
os

UNIT
V

TEST
CONDITIoNs

.....

rnA

'--

J L!.I~
¥
F

':

M 0-15"

J

SP4104-9-79-CAT

52

NEe

NEe Microcomputers, Inc.

~PD2114L

JAoPD2114L.1
JAoPD2114L·2
JAoPD2114L·3
JAoPD2114L·S

4096 BIT (1024 x 4 BITS) STATIC RAM
OESCR I PTION

The NEC pPD2114L is a 4096 bit static Random Access Memory organized as 1024
words by 4 bits using N-channel Silicon-gate MOS technology. It uses fully DC stable
(static) circuitry throughout, in both the array and the decoding, and therefore requires
no clocks or refreshing to operate and simplify system design. The data is read out
nondestructively and has the same polarity as the input data. Common input/output
pins are provided.
The pPD2114L is designed for memory applications where high performance, low cost,
large bit storage, and simple interfacing are important design objectives. The pPD2114L
is placed in an 18-pin package for the highest possible density.
It is directly TTL compatible in all respects: inputs, outputs, and a single +5V supply.
A separate Chip Select (CS) lead allows easy selection of an individual package when
outputs are OR-Tied.

F EATU RES

PIN CONFIGURATION

• Access Time: Selection from 150-450 ns
• Single +5 Volt Supply
• Directly TTL Compatible - AI.I Inputs and Outputs
• Completely Static - No Clock or Timing Strobe Required
• Low Operating Power - Typically -0.06 mW/Bit
• Identical Cycle and Access Times
• Common Data Input and Output using Three-State Output
• High Density 18-pin Plastic and Ceramic Packages
• Replacement for 2114L and Equivalent Devices

A6
A5

A7

A4

AS

A3

Ag

Ao

1/01

A1

1/02

A2

IT
GND

PIN NAMES

Vee

1/03

AO-Ag

Address Inputs

WE

Write Enable

es

ehip Select

1101- 1/ 0 1\'

Data Input/Output

Vee

Power (+5V)

GND

Ground

1/04

WE

Rev/l

53

II

jJ.PD2114L

BLOCK DIAGRAM

AJ~4)-~------{)S=====~

_____--.,@Vee

MEMORY ARRAY
64 ROWS
64 COLUMNS

ROW

A. ,)---------{::i:;::::::====~

SELECTOR

AS 16}---------~>====I
liD, 14~----_r_--{::i:;::::::==~

1/02 13}---"""""1+--~>====I

SENSE SWITCH

INPUT
DATA
CONTROL

Operating'Temperature . . . . .. . . . . . . . . . . .
. . . . . . . . . .. _10°C to +80°C
. . . . . . . . . . . -6SoC to +lS0°C
Storage Temperature (Ceramic) . . . . . . . . . . . .
(Plastic) . . . . . . . . . . . . . . . . . . . . . . . . . . -6SoC to +12SoC
Voltage on any P)n . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . -O.S to 7 Volts 1
Power Dissipation . . . . . . . . . . . . . . . . . . . ; . . . . . . . . . . . . . . . . . . . . . 1 Watt
Note: CD With respect to ground.

ABSOLUTE MAXIMUM
RATINGS*

COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a'stress rating only and functional operation of the device at these or
any other conditions above those indicated in the' operational sections of this specification is
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

not

*Ta = 2SoC
Ta = 25°C' f =

CAPACITANCE

10 MHz
LIMITS
MIN

TYP

MAX

TEST
UNIT CONDITIONS

PARAMETER

SYMBOL

Input/Output Capacitance

CI/O

8

pf

VI/O = OV

Input Capacitance

CIN

5

pf

VIN - OV

DC CHARACTE R ISTICS

Ta = 0° e to 70° C; Vec = +5V ± 10% unless otherWISe noted,
LIMITS

MAX

UNIT

ILl

10

IJA

V IN = 0 to5.5V

,ILO

10

IJA

CS = 2V, V I/O = OAV to Vec

ICCl

65

rnA

V IN = 5.5V, 11/0 = 0 mA,
,Ta = 25°C

Current

ICC2

70

rnA

V IN = 5,5V,IIio
Ta = oO,e

Input Low Voltage

V IL

-0,5

0.8

Input High Voltage

VIH

2.0

6,0

Output Low Current

10L

3.2

PARAMETER
Input Load Current

(A II I nput Pi nsl
1/0 Leakage
Current

SYMBOL

MIN

Power Supply

Current
Power Supply

Output High

Current

10H

TYP

-1.0

TEST CONDITIONS

V
V
mA

VOL

rnA

VOH = 2:4V, VCC - 4.75V
V OH

54

= 0 mA,

= 0.4V

= 2.2V, V CC =4.5V

JLPD2114L
AC CHARACTERISTICS

Ta '" O°C to +7Q"C; Vee = +5V ± 10%. unless otherwise noted.

LIMITS
PARAMETER

SYMBOL

2114L·2 I 2114L-3 I 2114L-6
MIN I MAX I MIN I MAX! MIN I MAX MIN MAX I MIN-I MAX

I

2114L

2114L·'

.1

TEST

UNIT

CONDITIONS

READ CYCLE
Read Cycle Time

tAe

Access Time

tA

450

300

250

200

150

Chip Selection
to Output ,valid

tea

120

100

80

70

60

.450

Chip Selection.

to Output Active

20

tex

Output 3,Slate
from Deselection

tOHA

250

20

100

tOTO

Output Hold from

Address Change

300

20

80

50

50

200

150

20

70

and 2.0V

ljO

50

50

Load = 1 TTL gate
Input Levels'" 0.8

20

60

50

IT'" Ir = If '" 10 ns
'CL = 100 pF

Vref = 1.5V

WRITE CYCLE
Write Cycle Time

twe

450

300

250

200

150

Write Time

tw

200

150

120

120

80

Write Release
Time

tWA

-0

Output 3-S1ate

100

taTW

from Write

Data to Write
tow

Time Overlap

t,-=t r =tf=10ns
CL=100pF

200

80

150

Load = 1 TTL gate

70

120

60
120

50

80

Input Levels'" 0.8
and 2.0V

re

V f .... 1.5V

Data Hold from

Write Time

tOH

Address to Write
Setup Time

tAw

TIMING WAVEFORMS

READ CYCLE

------------------------

1SB

WE is high for Read Cycles.
Device is continuously selected,

CS =

VIL·

@ Addresses valid prior to or coincident with CS transition low.

61

JLPQ2147
Ta

=

oOe to

+70 o e;

vee

=

+5V ± 10%, unless otherwise noted.
LIMITS

PARAMETER

~PD2147·3

SYMBOL

MIN

~PP2147·2

MAX MIN

TEST
CONDITIONS

UNIT

MAX

Write Cycle Time

'we

55

70

ns

Chip Selection to End

'ew

45

55

;ns

'AW

45

55

ns

. AC CHARACTERISTICS
WRITE CYCLE'

of Write
Address Valid to End
of Write

Address Setup Time

'AS

0

0

ns

Write Pulse Width

'WP

35

40

ns

Write Recovery Ti me

'WR

10

15

ns

Data Valid to End

'OW

25

30

ns

Data Hold Time

'OH

10

Write Enabled to Out-

'wz

0

'OW

0

of Write

ns

10
30

ns

35

0

put in High Z

Output Active from

ns

0

End of Write

TIMING WAVEFORM
WRITE CYCLE

'we
-,.
ADDRESS

~

'ew

t{

}//
'AW

I----'AS

-'WP-

////

I--'WR-

~\.

WE

'OH

I

I

*:

DATA IN

'ow

,\

DATA IN VALID

'1

--'WZ
DATA OUT ------O-A-T-A-U-N-O-EF-I-N-E-o-----1

I·

IMPEOAN~-----'ew

HIGH

rF,~=I

-I

'rJ
,~~

~tt5,=i'
,,'
::
. .
A

Hi,

T:

,

"

,.J
ii

I

'G

ITEM

.

M

MILLIMETERS

INCHES

A

23.2 MAX.

0.91 MAX.

B

1.44
2.54
0.45
20.32
1.2

0.055
0.1
0.02
0.8
0.06

2.5MIN.

0.1 MIN.
0.02 MIN.

C
0
F
G
H

I

0.5 MIN.
4.6 MAX.
5.1 MAX.

K

L

M

PACKAGE OUTLINE
!.lPD2147D

7.62
6.7
0.25

0.18 MAX.
0.2 MAX.
0.3
0.26
0.01

SP2147·1-80·CAT

62

NEe

NEe Microcomputers, Inc.

fLPD421
fLPD421-1
fLPD421-2
fLPD421-3
fLPD421-5

[POO~[~~~~illOOW
8K BIT STATIC RAM
DEseR IPTION

FEATURES

PIN CONFIGURATION

The NEC pPD421is a very high speed 8192 bit static Random Access Memory organized as 1024-words by 8 bits. Features include a power down mode control'led by the
chip select input for an 80% power saving.

• 1024 x 8-bit Organization
• Very Fast Access Time: 150/200/250/300/450 ns
• Single +5V Power Supply
• Low Power Standby Mode
• N-Channel Silicon Gate. Process
• Fully TTL Compatible
• 6-Device Static Cell
• Three State Common I/O
• Compatible with 8108 and Equivalent Devices
• Avail.able in 22 Pin Ceramic Dual-in-Line Package

Vee

AS
AS
A4
A3

2

A7

3
4

A9

A2

5

A1

S

AS

es

pPD
421

AO

7

1/°1
1/°2

S

1/°3

10

1/°5

GND

11

1/°4

I/OS

15

1/°7
I/OS

63

II

,",PD421
BLOCK DIAGRAM
A3
A4
A5

MEMORY ARRAY
12S ROWS
64 COLUMNS

AS
A7
AS
Ag

1/°1

1/°2
1/°3
1/°4
1/°5

INPUT
OATA
CONTROL

I/O S
1/°7
I/O S

cs-_.....,-,
WE~-=t-)-----------------~~~~~

.'_ .. oOe to +70o e ABSOLUTE MAXIMUM
.. ,-65°e to +150o e RATINGS*
. -0.5 to +7 Volts : 2O.n$

Timing measurement .
reference level:
1.6V~1t

OU1put load: ITTL
150

130

0

ns

Gate and CL'= 100 pF

ns

0

Valid with Respect
to Address Change

,:

Previous Read Data
Valid with Respect
to Chip Enable

0

tOH2

I

ns

0

WRITE CYCLE
Ta

=

OoC to 70°C;

Vee = 5V±5%,

unless otherwise specified
LIMITS

PAR,AMETER

LOWVCC DATA RETENTION
CHARACTERISTICS

SYMBOL

5101L

5101L·1

MI,N

TVP MAX MIN

:Y~!T.

TEST CONDITIONS

TYP MAX

ns

Input pulse .amplitude:
0.65 to 2.2 Volts

350

ns

400

250

ns

Timing measurement
reference level:
1.5 Volt

100

50

400

250

'WR

50

50

'OS,

150

.130

Write Cycle
Write Delav

'WC

650

450

'AW

150

130

Chip Enable (EEl)
to Write
Chip Enable (CE2)
to Write
Data Setup
Data Hold
Write Pulse
Write Recovery
Output Disable Setup

tew1

550

350

tCW2

550

'OW
'OH
'WP

Input rise and fall
times: 20 ns

Output load:" }TiL

ns
ns

Gate and CL =
100pF

Ta =0°Cto70'C
LIMITS'
PARAMETER
VCC for Data

SYMBOL

MIN

VCCDR

+2,0

TYP

MAX

UNIT
V

TEST CONDITIONS
CE2';;; +0.2V

Retention
Data Retention
Current

ICCDR

Chip Deselect

tCDR

+10

JlA

VCCDR = +:2.0V
CE2';;; +0.2V

0

ns

iRCCD

ns

Setup Time

Chip Deselect
Hold Time
Note:

tR



10
IOH (mAl

tA - Vee (Ta)
7-00

rUL'

LOAD

60 0

,\

50 0

-

"

~,I

-.........:

30 0

ro

E

pF

--

\~

40 0

1

~

,

20 0

'HOC

~ ~
~

L,
VCCIV~

0

T"
Vcc

25C
5V

60 0

~ V,

CE2

0
500

o!---

.-1---- I----

./

1

j----j---- ..Jcc.

'02V

"'~
,,>J

. / ~~ ~

o to Vee

'Jcc~

b:7

300

0.0 1
20 0

100

200

300

400

10

500

20

Cl. ipFI

30

40

50

60

T" ( CI

PACKAGE OUTLINE
J.lPD5101LC

ITEM

MILLIMETERS

a Mdx'

A

28

F
G

2.54
0.50 0_10
25.4
140
2.54 tJ111\
0.5 Min
4.7 M,Ix
5.2 MdX

14 MdX

+010

025

0.075 M,Il<
0.10
0,07 0_004
1,0
0,055
0_10 MI!l

D',07 Min
0.18 M.p(
0_20 M.l>:

040
0,33

10_16

8.5
M

INCHES
1,10 MdX

0'05

001

to 004
D_OO:?

SP5101 L-8-77-GY-CAT

73

NOTES
·r

..
;~

.• .1.

74

NEe

NEe Microcomputers, Inc.

JLiPD44416514
JLPD44416514·1
JLPD44416514·2
JL,PD44416514.3

1024 x 4 BIT STATIC CMOS RAM
DESCRIPTION

The I.IPD444/6514 is a high speed, low power, silicon gate CMOS 4096 bit static RAM
organized 1024 words by 4-bits. It uses fully DC stable (static) circuitry throughout
and therefore requires no clock or refreshing to operate. Data access is particularly
simple since address setup times are not. required. The data is read out nondestructively and has the same polarity as the input data. Common input/output pins are
provided.
CS controls the power down feature. In less than a cycle time after CS goes high deselecting the I.IPD444/6514 - the part automatically reduces its power requirements
and remains in this low power standby mode as long as CS remains high. There is no
minimum CS high time for device operation, although it will determine the length of
time in the power down mode. When CS goes low, selecting the I.IPD444/6514, the
I.IPD444/6514 automatically powers up.
The I.IPD444/6514 is placed in an 1a-pin plastic package for the highest possible
density. It is directly TTL compatible in all respects: inputs, outputs, and a single
+5V supply. The I.IPD444/6514 is pin compatible with the I.IPD2114L NMOS Static
RAM.
Data Retention is guaranteed t'o 2 volts on all parts. These devices are ideally suited
for low power applications where battery operation or battery backup for nonvolatility are required.

F EATU R ES

• Low Power Standby - 51.1W Typ.
•
•
•
•
•
•
•
•
•
•
•
•

PIN CONFIGURATION

Low Power Operation
Data Retention - 2.0V Min.
Capability of Battery Backup Operation
Fast Access Time - 200-450 ns
IdenticlIl Cycle and Access Times
Single +5V Supply
No Clock or Timing Strobe Required
Completely Static Memory·
Automatic Power-Down
Directly TTL compatible: All Inputs and Outputs
Common Data Input and Output 'using Three-State Outputs
Replacement for I.IPD2114L and Equivalent Devices
Available i,n a Standard 1a-Pin Plastic Package

As

Vee

AS

A7

A.t

AS

. WE

Write Enable

A3

AS

CS

Chip select

Ao

I/O,

1/01-1/ 0 4

Data Input/Output

A,

1/02

A2

1/03

cs
GND

PIN NAMES
AO-A9

Address Inputs

VCC

Power (+5V)

GND

Ground

1/04

WE
Rev/1

75

E

j-LPD444/6514
A,

A5

ROW
SELECT

~

A,

~

A,

f--?
.-=:J

Ag

~VCC

·
·
·
r-

f-2.

A6

BLOCK DIAGRAM

r-

~

_______ GND
MEMORY ARRAY

64 ROWS
64 COLUMNS

1•
~
~

liOI

,....:J

1-:'

11°2

~
11°3

INPUT
DATA

. ·1

COLUMN I'QCIACUITS

COLUMN SELECT

CONTROL

,....::J

~ ~~ ~~ ~~~

1104

.....J

A,

AO

!

A,

I

/I

r-

L

~-

A3

~/I'

L

.~

-LJ

1 1

:"
_40" e to +85" e
-55"e to +125"e
-0.3 to Vee +0.3 Volts CD
+8.0 Volts

Operating Temperatur~: .
Storage Temperature.
All Input 'and Output Voltages.
Supply Voltage

Note:

CD

..

"',

ABSOLUTE MAXIMUM
RATINGS*

With Respect to Ground

COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

'Ta
Ta

=

25"e

= -4o"e to +85°e;

Vee

= +5V

DC CHARACTERISTICS

± 10% unless otherwise tested
LIMITS

444/6514·3
PARAMETER

SYMBOL MIN TYP

444/6514·2

MAX

MIN

TYP

444/6514

444/6514·1

MAX

MIN TYP

Input Leakage Current

'LI

-1.0

1.0

-1.0

1.0

-1.0

I/O Leakage Current

'La

-1.0

1.0

-1.0

1.0

-1.0

MAX

MIN TYP

1.0

-1.0

1.0

-1.0

MAX

1.0

UNIT

TEST CONDITIONS

.A

VIN "GND to Vee

1.0

.A

es = VIH, Vila - GND

35

14

35

mA

es = VIL. VIN- Vee,
Outputs Open

40

17

40

mA

es'" VIL. VIN- 2.4V,
Outputs Open

mA

ViN = GNO or Vee,
Outputs Open f = 1 MHz.
Duty 50%

50

.A

CS'" Vee. VIN = GND

0.8

v

to Vee
Operating Supply

ICCAl

20

35

18

35

16

ICCA2

24

40

22

40

19

ICCA3

10

Current
Operating Supply
Current
Average Operatmg
Supply Current

Standby Supply Current

lecs

Input Low Voltage

VIL

-0.3
2.4

50

50

50

to Vee

Input High Voltage

V,"

OutPut Low Voltage

VOL

Output High Voltage

VOH

O.B

-0.3

Vee + 0.3

2.4

0.4

0.8

-0.3

Vee + 0.3

2.4

0.4

2.4

-0.3

Vee t 0.3

2.4

0.4
2.4

2.4

0.8

2.4

Ta = 2S"C, f = 1 MHz

v

IOL = 2.0 mA

V

IOH - -1.0 mA

CAPACITANCE
LIMITS
MIN

TY.

PARAMETER

SYMBOL

UNIT

TEST CONDITIONS

Input/Output Capacitance

CliO

MAX
10

pF

V,IO = oV

Input Capacitance

C'N

5

pF

VIN - OV

Nott!: This parameter is periodically sampled and not 100% tested.

76

Vee + 0.3

0.4

!-,p D.444/6514
AC CHARACTERISTICS

Ta " -40 C to +85 C'

Vee'"

+5V • 10% unless 'OtherwIse noted

.1

J

LIMITS

,1444/6514-3 44416514-2144416514.,

I

PARAMETER

I

I

I

I

444/6514

I

I

SYMBOL! MIN MAX MIN MAX MIN MAX MIN1 MAX UNIT

,

tACS2

Output Hold from Address Change
Chip SaIKllon to Output In Low Z

'OH
'LZ

tn

High 2

2SO
200
200 .
2SO

tAC!;;1

ChIP $elect Access Time (.V

ChiP Oeselectlon to Output

200

'Ae
'AA

Read Cvcle
Address Access Time

Chip Select Access rime 1

.TEST CONDITIONS

READ CYCLE

SO
20

SO
20

4SO
.450

300
300
3SO
50
20

500
SO.

Input Pulse Levels:
+0.8 to +2.4 Volts
Times: 10-ns
Input and Output TIming

Levels: ,1.5 Volt
100

80

n.

.n5. Input Rise and Fall

. Output Load: 1 TTL

20:

70

60

'HZ

450

300
2SO
2SO
300

Gate and CL = 100 pF

WAITECVCLE

Write Cycle

T'~e

'we
'ew
'AW
'AS
'w,
'WA
'OW
'OJ<
'wz
'OW

Chip Selection to end of Write
Address Valid to End of Write

Address Setup TIme
Wrtte Pulse WIdth
Write Recovery TIme
Data Valid to End of Write
Data Hold Tlnle
Wrtte Enabled to Output in HIgh Z
Output Active from End of Write

Notes:

CD

200
-180
180
0··
180
0'
120
0

2SO
230
230

300
2SO
2SO

210

230

0
140
0

l'npy"t Pulse Levels:

350~

+0.8,to +2.4 Volts
Input Rise and Fall

350~

T!mes: 10ns
Input and 04tput TimIng
Levels: 1:.5 Volt
Output Load: 1 TTL
Gaieand'CL = 100pF

.0 ~
300',
0;

ISO

200)

o· .

a

eo

450:

70

100

80
0·-

Chip deselected for greater than 100 ns prtor to selection.

(i) Chip deselected for a finite time that IS less than 100 ns prIor to selectlon.'W .the dMleCt time IS a ns; the chip IS by deltn'ltlon
selected and access occurt according to Read Cycle No, 1.1

LOWVCC DATA
RETENTION
CHARACTERISTICS

LIMITS
PARAMETER
Data Retention Supply
Voltage
Data Retention Supply
Current
Chip Deselect to Data
Retention Time
Operation Recovery
Time
Note:

PACKAGE OUTLINE
MPD444/6514C

Q)

MIN

SYMBOL

TYP

MAX

2.0

VCCDR

0.1

ICCDR
0

tCDR
tR

tRCQ)

10

UNIT

TEST CONDITIONS

VI

CS = VCC;VIN = VCC
tcrGND

ilA

VCC - 3V, CS"= VCC
VIN =VCC to GND

ns
ns

tRC = Read Cycle Time

~----------A--~------~

Plastic
ITEM

MILLIMETERS

INCHES

A

23,2 MAX,

0.91 MAX.

1.44

0,055

e

2."

0.1

0

0.45

0.02

20.32

0.8

1.2

0,05

G

2.SMIN.

D.1MIN.

H

Q,5MIN.

0,02 MIN,

K

M

4.6 MAX,

Q,18 MAX.

5.1 MAX.

0.2M'AX.

7.62

0.3

6.7

0.26

0.25

0.01

77

II

READ CYCLE G)

ADDRESS

TIMI,NGWAVE'F.O,RMS

-

'ew

\

-I

II

'AW

'WR

_'WP-':"-

I---'AS-

'OW

~
D,N

" ~I

Notes:

'DH

DATA IN
VALID

'wz

"

I--

..,

_\

DOUT

IIIII

I

~,1 ; / / / /

HIGH IMPEDANCE

I1\

"

"

"

CD WE is high for Read Cycles.
@

DeVlce,ls continuously selected,

@
@

Address valid prior to or coincident With

CS

= VIL

CS transition

low.

If th, CS low transition occurs simultaneously With the WE low transition, the
output buffers remain in a high impedance state.

® WE must be high during all address transitions.
® "twP is me~sured from the latter of CS or WE going low to the earlier of CS or We
going high.

LOW VCC DATA RETENTION

VCC

------------~--~

V,L

OV - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

SP444/6514-1 G-79-CAT

78

NEe

NEe Microcomputers, Inc.

p..PD445L
p..PD445L·1

FULLY DECODED 4096 STATIC CMOS RAM
DESCRIPTION

The f.lPD445L is avery low power 4,096 bit( 1024 words by 4 bits) static RAM fabricated
with NEC's complementary MOS (CMOS) process. It has two chip enable inputs (CE1,
CE2). Minimum standby current is drawn when CEl is at ahigh level, while inhibiting
all address and control line transitions or, unconditionally when CE2 is at a low level.
This device ideally meets thelow power requirements of battery operated systems and
battery back-up systems for non-volatility of data.
The f.lPD445l- uses fully static circuitry requiring no clocking. Output data is read out
non-destructively by placing a high on the R!W pin and has the same polarity as input
data. All inputs and outputs are directly TTL compatible. The device has common
input/output data busses and an OD (Output Disable) pin,for use in common I/O bus
systems.
The f.lPD445L is guaranteed to retain data with the power sl,lpply voltage as low as 2.0
volts.

FEATURES

• Single+5VPowerSupply
• Ideal for Battery Operation
• Low Standby Power for Data Retention
• Simple Memory Expansion - Chip Enable Inputs
• Access Time- 650 ns Max. (f.lPD445L)
4.50 ns Max. (f.lPD445L-l)
• DirectlyTTL Compatible - All Inputs and Outputs
• Common Data Input and Output
• Static CMOS - No Clocks Refreshing Required
• 20 Pin Dual-In-Line Plastic Package

PIN CONFIGURATION
A3

PIN NAMES

vcc

A2

A4

A,

R/W

AO'Ag
OD
R/W
CE,

AO

GE,

A5

00

As

CE2

1/01-1/°4

A7

AS

GND

Ag

VCC
GND

I/O,

1/°4

1/°2

1/03

CE2

Address Input
Output Disable.
Read/Write
Chip Enable 1
Chip Enable 2
Data Input/Output
Power Supply
Ground

OPERATION MODES

CE1
0
0

CE2

,
,

00

Chip

0

Output Mode
Data Out

Selected
1
High Impedance

Others

Non-Selected

79

BLOCK DIAGRAM
MEMo'RY
,CELL'

x·
. OEcobER

MATRIX,

64 x 64

00

..... -100 eto,+70oe
. ... -400 eto+125°e
-0.3 to Vee +0.3 Volts
. ., .......... -0.3 to Vee +0.3 Volts
. ........... ~.. . .. -0.3 to +7 Volts

Operating Temperature .... .
Storage Tem perature.. .
All Output Voltages .. .
All Input Voltages ... .
Supply Voltage Vee ..... .

ABSOLUTE MAXIMUM
RATINGS*

COMMENT: Stress above those listed under "'AbSolute Maximum Ratil)gs" may cause permanent·
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

*Ta = 25°e
Ta "" -10 to +7

Output Low Voltage

Val

Input Leakage
Current High

TEST
CONDITIONS

UNIT
V
V
V
V

IOH
IOH

+ 0.4

V

IOl = +2.0 mA

ILiH

+ 1.0

~A

VI

Input leakage
Current low

IUl .

-

~A

VI oOV

Output Leakage
Current High

IlOH

+ 1.0 ..

~A

~= Vce
eEl = 2.2V·

Output leakage
Current low

IlOl

~A

Va' OV.
eEl = 2.2V

Supply Cu~ent

ICCl

1.0

1.0

12

,25

mA

~.

0

-1.0 mA

~

100~A

Vee

Outputs Op,en
~ = Vce except
eEl" 0.65V

Supply Current

ICC2

16

30

mA

Outputs Ope~
V I '" 2.2V except
eel " 0.65V

Standby Current

80

ICCl

40·

~A

VI' = 0 to 5.25V

Except CE2 '" O.2V

DC CHARACTERISTICS

JLPD445L
AC CHARACTERISTICS

READ CYCLE
Ta ~ _10°C to +70°C' VCC ~ +5V +- 10%
LIMITS
445L
PARAMETER

SYMBOL

MIN

445L·l
MAX

MAX

MIN

TEST
CONDITIONS

UNIT

Read Cycle Time

tRC

Access Time

tA

650

450

ns

Chip Enable
(CE1) to Output

tC01

600

400

ns

Chip Enable
(CE2) to Output

tC02

700

500

ns

Input Rise Time
20 ns

Output Enable
to Output

too

350

250

ns

Input Fall Time
20 ns

Output Disabl e
(001 to Floating

tDF

0

130

ns

Data Output
Hold Time

tOHl

0

0

n,

Chip Disable
to Floating

tOH2

0

0

ns

Address Rise
and Fall Time

tr
tf

650

ns

450

150

0

300

Ta ~ DoC to +70°C' VCC ~ +5V -+ 10%

300

Input Voltage Levels
V

~

+0.65 to +2.2V

Timing Measurement
Reference Level ~
+1.5V

Output Load
1 TTL + 100 pF
For Address change
during Chip Enabled

ns

WRITE CYCLE
LIMITS

445L
PARAMETER
Write Cycle Time

SYMBOL

MIN

445L·l
MIN MAX

MAX

TEST
CONDITIONS

UNIT

twc

650

450

ns

Time

tAW

150

130

ns

Chip Enable
(CE1) to Write '.
End

tCWl

550

350

ns

Input Rise Time
20 ns

Chip Enable
(CE21 to Write
End

tCW2

550

350

ns

Input Fall Time
20 ns

Data Setup Time

tow

400

250

ns

Data Hold Time

tDH

100

50

ns

Write Pulse Width

twp

400

250

ns

Address Hold
Time

tWR

50

50

ns

Output Disable
Setup Time

tDS

150

130

ns

Address Rise
and Fall Time

tr
tf

Address Setup

V I ~ +0.65 to +2.2V

Ta ~ _10°C to +70°C

300

300

SYMBOL

MIN

VCC for Data Retention

VCCDR

+2.0

Data Retention Current

ICCDR

Chip Deselect Setup Time

tCDR

Chip Deselect Hold Time

tR

CD

tRC

Timing Measu rement

Reference Level
+1.5V

~

For Address change
during Chip Enabled

ns

LOW VCC DATA RETENTION

PARAMETER

Note:

Input Voltage Levels

LIMITS
TYP

MAX

UNIT
V

40

I'A

0

ns

tRCG)

ns

TEST
CONDITIONS
CE2';;;+0.2V
VCCDR ~ +2.0V
CE2';;; +0.2V

~ Read Cycle Time

81

II

JLPD445L~
TIMING WAVEFORMS

READ CYCLE

ADDRESS

'OH2

00
(COMMON I/O)

f----'A

'OP-----

------<~

DATA OUT

-

-

- - HIGH IMPEDANCE STATE

WRITE CYCLE
f----~-----'wc----------------__4
ADDRESS

____+_...... !------'ewl ------1

r--+-------'ew2--------4~

00
(COMMON 1101

'oH
DATA
IN

L-._I-------'ow - - - - - - 1 -

---+- r - - - - - - - ' W p - - - - . - 1 , - - - - ! - - - R/W
-

-

-

-

HIGH IMPEDANCE STATE

LOW VCC DATA RETENTIONG)
DATA RETENTION MODE

4.75V

'R

SUPPLY VOLTAGE (Vee)

---j

VeCOR

VI~
CHIP ENABLE (CE2)

O.2V

~

Jt"'H

'-__________________

O.2V .

w----------------------------Note

(j)

Apply

les~

than VCCDR 'to all Inputs for data retention mode.

fl,PD445L:
CAPACITANCE

UNIT

TEST
CONDITIONS

SYMBOL

Input Capacitance

Cr

5

8

pF

VI =OV

Co

8

12

pF

VO=OV

Output Capacitance

MIN

LIMITS
TYP MAX

PARAMETER

PACKAGE OUTLINE
J.lPD445LC

ITEM
A

MILLIMETERS

INCHES

27.00

1.07

8

2.07

0.08

C

2.54

0.10

D

0.50

0.02

E

22.86

0.90

F

1.20

0.05

G

2.54 MIN

0.10 MIN

H

0.50 MIN

0.02 MIN

I

4.58 MAX

0.18

J

5.08 MAX

0.20

~--

K

10.16

0.40

L

8.60

0.39

M

0.25

~~:~~

+0.004
0.01 -0.002

SP445 L-8-78-G Y-CAT

83

NOTES
"

84,

NEe

NEe Microcomputers, Inc.

J.L PD2308A

FULLY DECODED 8,192 BIT MASK
PROGRAMMABLE READ ONLY MEMORY

DESCR IPTION

The NEC ILPD230SA is a high speed S,192 bit mask programmable Read Only Memory
organized as 1024 words by S bits. The ILPD230SA is fabricated with N·channel MOS
technology.
The inputs and outputs are fully TTL compatible. The device operates with a single
+5V power supply. The three chip select inputs are programmable. Any combination
of active high or low level chip select inputs can be defined and desired chip select
code is fixed during the masking process.

F EATU R ES

II

• Access Time 450 ns Max
• 1024 Words x·S Bits Organization
• Single +5V ±10% Power Supply Voltage
• Directly TTL Compatible - All Inputs and Outputs
• Two Programmable Chip Select Inputs for Easy Memory Expansion
• Three·State Output - OR·Tie Capability
• On·Chip Address Fully Decoded
• All Inputs Protected Against Static Charge
• Direct Replacement for 230SA
• Available in 24·pinpiastic or ceramic packages

PIN CONFIGURATION

24

Vcc

2

23

AS

A5

3

22

A9

A4

4

21

NC

20

CS1

19

NC

A7
A6

A3

5

A2

6

A1

Il PD
2308A

1S

CS2

S

17

07

DO

9

16

01

10

02

11

14

04

GND

12

13

03

AO

PIN NAMES

I

AO - A9 I Address Inputs
I DO - 07 I Data Outputs
I CS1 - CS21Programmabie Chip Select

Input~

06
05

Rev/1

85

p.PD2308A
~Vcc

BLOCK DIAGRAM

-GND

Ag
AS
CHIP
SELECT
PROG.

8,192 BIT
CELL MATRIX
INPUT
BUFFERS
AO

-1O o e to +70o e
. . .. -65°e to +125°e
: -0.5 to +7.0 Volts

Operating Temperature, ............. .
Storage Temperatu re ..... , ..... .
'Voltage on Any Pin ........ .
Note:

CD

ABSOLUTE MAXIMUM
RATINGS*

CD With Respect to Ground.

COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for .extended periods may affect device
reliability.

*Ta=25°e

T a = _10°C to +70°C: Vee

==

+5 ± 5% unless otherwise noted.

DC CHARACTERISTICS

LIMITS
PARAMETER

MIN

TYP



MIN.

60

= 2.2V
= 2.2V

(Deselected) V OUT

= VCC

IDeselected) V OUT = OV

V

VCC + 1.0V
0.40

2.4

V

3.2mA

V

-20011A

 Bol

+-,

8,. Bol

_0

(OP,

IDP]

Skip If K4 - 1

IAccl" IDPI
"IACCI- 13 12 I, 10

K4- 1

PC- (TRI. Pa-O

PCs-4 ~ P&-4
pea-O +- P3-0V IAcel
PCe-o~ P&-D

(STACK] +- (PCI
PC +-1000PS Ps P4 Pa P2 P, Po

pc- {STACK1
PC- (STACK]
pC .... IPC) + 1
Enable IA port

Disable tAport
Enable IB port

Disable IB port
U7-0- 17-0
R7-0 +- 107-01
Enable R

pan

Disable R port
R~(al

R7-4 .... (TRI, R3-0 -IDPLI

s- IAcel
S port Input Mode

ACC"" S

ACC- K
F,_O

1=,-1
F2 -0
F2-'
F3- a

F3-'
F4- 0
F4-'
F5+- 0

f5-'

Fe+- a

Fe-'
F7- 0

F7-'
Fa- O

Fa- 1
Fg-a

Fg_'

Fa-a
Fa-'
No Operation

SP42-9-78-GN-CAT

112

NEe

NEe Microcomputers, Inc.

p.PD548

P. COM·42 SINGLE CHIP MICROCOMPUTER
DESCR I PT I ON

ABSOLUTE MAXIMUM
RATINGS*

the JlPD548 is the only version of the JlCOM-42. This PMOS,-l 0 volt part is designed
to have TTL-level compatible inputs and was specifically designed for external RAM
expansion. As a JlCOM-42, it includes 1920 x 10 ROM, 96 x 4 RAM and 351/0 lines
in a 42 pin plastic dual-in-line package.
Operating Temperature.
Storage Temperature..
Supply Voltage VGG . .
Input Voltages. . . . . . .
Output Voltages . . . . .

.
.
.
.
.

..
..
. .
. .
•.

.
.
.
.
.

.
.
.
.
.

.
.
.
.
.

.
.
.
.
.

.
.
.
.
.

.
.
.
.
.

.
.
.
.
.

.
.
.
.
.

. .
. .
..
. .
..

.
.
.
.
.

.
.
.
.
.

.
.
.
.
.

.
.
.
.
.

.
.
.
.
.

.
.
.
.
.

.
.
.
.
.

.
.
.
.
.

.
.
.
.
.

.
.
.
.
.

.
.
.
.
.

..
..
..
..
..

. ..
..
..
..
..

-10°C to +70°C
-40°C to +125°C
-15 to +0.3 Volts
-40 to +0.3 Volts
-40 to +0.3 Volts

COMMENT: Stress above those listed under" Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
rei iabi! ity.

DC CHARACTER ISTICS

Ta = -10°C to +70°C; VGG = -10V ± 10%
LIMITS
PARAMETER

SYMBOL MIN

TYP

MAX

UNIT
V

TEST
CONDITIONS

Input High Voltage

VIH

0

- 2.0

Input Low Voltage

VIL

-4.3

VGG

V
V

10H =-4 mACD

V

10H =-1 mA
(for S port outputs)

Output High Voltage

VOHl

- 3.0

Output High Voltage

VOH2

- 1.0

I nput Leakage
Current High

ILiH

+10

JlA

VI=-lV

Input Leakage
Current Low

ILiL

-30

JlA

VI= -36V

Output Current High

IOH

mA

VOH =-lV

Output Lea kage
Current Low

ILOL 1

-30

JlA

VO=-36V

Output Leakage
Current Low

ILOL2

-10

JlA

VO=-5V
(for S port outputs)

Supply Current

IGG

-60

mA

-1.0

-30

Note: CD For R port, and when only 1 bit is ON (high level)

AC CHARACTER ISTICS

Ta = -10°C to +70°C; VGG ,:, -10V ± 10%, unless otherwise noted
LIMITS
PARAMETER
Clock Frequency

SYMBOL MIN
frfJ

100

Clock Pulse Width

trfJw

2.25

Clock Rise-Fall Time

tr, tf

TYP

MAX

UNIT

200

KHz

TEST
CONDITIONS

JlS
0.5

JlS

113

II

J.LP,DS48
,"

,,~

"

•

Q'

.

,
Ta'" 25 C·VGG
= -10V -+ 10% unless otherwise noted
LIMITS
PARAMETER

SYMBOL

MIN

TYP

CAPACITANCE

MAX

UNIT

Capacitance, Any
Input Except S

CI

15

pF

Capacitance, Any
Output Except S

Co

15

pF

SPort
.
..,
.,
Capacitance

CIO

15

pF

TEST
CONDITIONS

f = 1 MHz

CLOCK WAVEFORM

.....- - - - 1 M - - - - - - t

tf

PACKAGE OUTLINE

I

I

A

~PD548C

ITEM

MILLIMETERS

A

56.0 MAX
2.6 MAX

B

INCHES
2.2 MAX
0.1 MAX

C

2.54

0.1

0

0.6 ±0.1

0.02 + 0.004
2.0

E

50.8

F

1.5

0.059

G

3.2MIN

0.126 MIN

H
I

0.5 MIN

0.02 MIN

5.22 MAX

0.lOMAX

J

5.72 MAX

0.22 MAX

K

15.24

0.6

L
M

13.2
0.3± 0.1

0.52
0.01 ± 0.004

SP548-9-78-G N-CA T

114

NEe Microcomputers, Inc.
fLCOM·43/44/45 4·81T SINGLE CHIP
MICROCOMPUTERS

DESCRIPTION

The pCOM-43 Family consists ofthree device types designed to offer a full range of
cost/performance tradeoffs. All three devices share compatible hardware and instruction set. The pCOM-43 Family is designed for general purpose controlter applic~tions
and offers ideal devices for industrial controls, appliance controls, games, etc.
All three devices contain the functional blocks necessary to enable their use for both
industrial and non-industrial controller applications. These blocks include: a 4-bit
parallel ALU; 8-bit wide ROM for program storage; 4-bit wide RAM for data storage;
stack register for subroutines; extensive I/O; and an on-chip clock generator.
The instruction set of the pCOM-43 Family is designed to perform controller-oriented
functions and for efficient use of the fixed program memory space. The instruction
set includes a number of multifunction instructions, powerful I/O instructions _
including single bit manipulation, and test-and-skip instructions for conditional
processi ng.
The three device types comprising the pCOM-43 Family are differentiated by ROM/
RAM size and I/O lines. The pCOM-43 has 2000 x 8 ROM, 96 x 4 RAM and 35 or 21 I/O
lines. The pCOM-44 has 1000 x 8 ROM, 64 x 4 RAM and 35 I/O lines. The pCOM-45
has 1000 x 8 or 640 x 8 ROM, 32 x 4 RAM and 21 I/O lines. In addition, the
pCOM-43 has real hardware interrupt, 3 level stack and programmable timer, while
the pCOM-44/45 have pseudo-interrupt capability and a single level stack.

FEATU RES

II

• Stand Alone 4-Bit Microcomputers for Control Applications
•

Powerful I nstruction Set Capable of: Binary Addition; Decimal Addition and
Subtraction; Logical Operations

•

10 ps Instruction Cycle

•

Choice of ROM Size: 2000 x 8 - pCOM-43
1000 x 8 - pCOM-44

100q x 8 _ COM-45
640 x 8 P
•

Choice of RAM Size:

96 x 4 - pCOM-43
64 x 4 - pCOM-44
32 x 4 - pCOM-45

•

Choice of I/O Power:

35 lines _ COM.43
21 lines p
35 lines - pCOM-44
21 lines - pCOM-45

•

All Capable of Single Bit Manipulation and 4-Bit Parallel Processing.

•

Interrupt Capability

•

On-Chip Clock Generator

•

Open Drain Outputs

•

Choice of PMOS or CMOS Technology, Both Requiring Single Supplies

•

Available in 42 Pin or 28 Pin Plastic Dual-in-line Packages

115

JLCOM,~43/44/45
1

CL1
-PCO
PC1
PC2
PC3
iNT
RES
PDO
PD1
PD2
PD3
PEO
PE1
PE2
PE3
PFo
PF1
PF2
PF3
TEST
Vss

2

3
4
5
6
7

IlCOM
43/ (1)
44

CL1
PCo
PC1
, PC2
PC3
PDO
PD1
PD2
PD3
PEO
PE1
PE2
PE3
Vss(OVI

IlCOM
43/®
45

CLo
VGG(-10V)
PB3
PB2
PB1
PBO
PA3
PA2
PA1
PAO
PI2
PI1
PIO
PH3
PH2

PIN CONFIGURATiONS
PIN NAMES
CL O-CL 1

External Clock Source

PCO PC3

Input/Output,Port C

INT

Interrupt Input

".

Reset

PDO-PD3

Input/Output Port 0

,--PEO- PE 3

Output Port E

PF O- PF 3

Output Port F

f---

TEST

Input for Testing

PGO-PG3

Output Port G

(Normally GND)

PHO-PH3

Output Port H

PH1

PIO PI3

Output Port I

PHO
PG3
PG2
PG1
PGo

PAO PA3

Input Port A

PBO-PB3
1-____

Input Port B

CLo
VGG(-10V)
RES
INT
PA3,
PA2
PA1
PAO
PGo
PF3
PF2
PF1

PFo
TEST

--

RES

Notes:

--

PIN NAMES
External Clock Source

CLO-CL1
PCO-PC3

I nput/Output Port C

PDO-PD3

Input/Output Port 0

PEO-PE3

Output Port E

PFO-PF3

Output Port F

PGO

Output Port G

PAO-PA3

Input Port A

INT

Interrupt Input

RES

Reset

5 volt power
supply, a 2 mA (max), 800 f.lA (typ) current drain and extended temperature range. As
a f.lCOM-43, it includes 2000 x 8 ROM, 96 x 4 RAM and 35 I/O lines in a 42 pin plastic
dual-in-line package.
Operating Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -30°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . -55°C to +125°C
Supply Voltage
. . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . .. '--0.3 to +7.0 Volts
Input Voltages. . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .. .;..0.3 to +7.0 Volts
Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +7.0 Volts
Output Current (Each Output Bit) .. , _ . . . . . . . . . . . . . . _.' ........... 2.5 mA
COMMENT: Stress above those listed under I I Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress ~ating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

*Ta = 25°C
DC/ACCHARACTERISTICS

Ta =-30°Cto+85°C VCC=+5V±10%.
LIMITS
PARAMETER

SYMBOL

MIN

I nput High Voltage

VIH

0.7Vec

Input Low Voltage

VIL

Input Leakage

ILiH

+10

I nput Lea kage
Current Low

ILIL

-10

IJA

Ports A and B, INT, RES
IVI = OV)

I/O Leakage
Current High

IIOH

+10

IJA

Ports e and D IVI - Vec)

I/O Leakage
Current Low

IIOL

-10

IJA

Ports C and DIVa = 0V)

Output High
Volta~e 1

VOH1

VCC-O.S

V

VCe-O.S

V

Ports C and D
IIOH = -1 rnA)
Ports E and I
IIOH = -0.6 rnA)

TYP

MAX
Vce

a

0.3Vee

UNIT.

TEST CONDITIONS

V

Ports A to D, INT, RES

V

Ports A to D, INT, RES

IJA

Ports A and B, INT, RES
IVI = Vee)

Current H'igh

Output High
Voltage 2
Output Low Voltage I

Supply Current
Clock High
Voltage
Clock Low
Voltage

V

Ports C to I IIOH - -2 rnA)

VOLl

0.6

V

VOL2

0.4

V

Ports E to I
IIOL = 2 rnA)
Ports E to I
IIOL = 1.2 rnA)

2.0

VOH2

VCC-2.S

VH

0.7VCC

0.8

Vec

rnA
V

CLO, Ext. Clk.

VL

a

0.3VCC

V

CLO, Ext. Clk.
eLO, Ext. CI k.
(VOH = Vee!
CLO, Ext. Ok.
IY.o.J. = OV)

ICC

Clock Leakage
Cu rrent High

ILH

200

IJA

Clock Lea kage
Current Low
Clock Frequency

ILL

-200

IJA

440

KHz

Clock Rise and Fall
Times
Clock Pulse Width

f

150

I

tr, tf

a

0.3

IJS

Ext. Clk.

tW

0.5

5.6

IJS

Ext. Clk.,

127

a

j.+IP0650
Ta

= _30°C to +85°C, VCC =+5V ± 10%.

CAPACITANCE
LIMITS

PARAMETER
Input Capacitance
Output Capacitance
I/O Capacitance

SYMBOL

MIN

MAX

UNIT

CI

15

pf

Co

15

pf

CIO

15

pf

llf

TYP

TEST CONDITIONS
f = 1 MHz

CLOCK WAVEFORM

------l

- - - - - - - - O.7VCC

OV - - - - -

PACKAGE OUTLINE
IlPD650C

ITEM

MI LLlME.TE.RS

A

56.0. MAX

2.2 MAX

INCHES-

B

2.6 MAX

0:1 MAX

C

2.54

0.1

0
E
F
G

0.5 ± 0.1

0.02 ± 0.004

50.8

2.0

1.5

0.059

3.2 MIN

0.126MIN

H

0.5 MIN

0.02 MIN

1

5.22 MAX

0.20 MAX

J

5.72 MAX

0.22 MAX

K

15.24

0.6

L

13.2
0.3±O.1

0.52
0.01 ± 0.004

M

SP6S()'9-78·GN·CA T

128

NEe

NEe Microcomputers, Inc.

fLPD547

fLCOM·44 SINGLE CHIP MICROCOMPUTER

DESCR IPTION

ABSOLUTE MAXIMUM
RATINGS*

The IlPD547 is the standard version ofthe IlCOM-44_ This PMOS, -10 volt part is
designed to have TTL-level compatible inputs and is easily interfaced to external static
RAM. As a IlCOM-44, it includes 1000 x 8 ROM, 64 x 4 RAM and 35 I/O lines in a
42 pin plastic dual-in-line package.
Operating Temperature. _ . . . . . . . . . . . . . . . . . . . . . . . . . ..
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . .
Input Voltages .. _ .. _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltages . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . .
Output Current ..... _ . . . . . . . . . . . . . . . . . _ ....... _ . __

-10°C to +70°C
_40°C to +125°C
-15 to +0.3 Volts
-15 to +0.3 Volts
-15 to +0.3 Volts
. . . . . .. -4 mA

COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operati'onal sections of this specification is not

implied. Exposure to absolute maximum rating conditions for. extended periods may affect device
reliability.

DC/AC CHARACTERISTICS

Ta = _10°C to +70"C, VGG = -10V ± 10%
LIMITS
PARAMETER

SYMBOL

MIN

Input High Voltage

VIH

0

Input low Voltage

Vil

-4.3

Input leakage
Current High
Input leakage

TYP

MAX

UNIT

-2.0

V

VGG

V

ILiH

+10

/lA

ILil

-10

/lA

IIOH

+10

/lA

II0l

-10

/lA

Current Low

ct;o leakage
Current High
I/O leakage
Current Low

Output Voltage

VOHI
VOH2

I
Output leakage
Current
Supply Cu rrent

10l

Oscillator Frequency

F

-30

IGG
150

TEST
CONDITIONS

II

Ports A to 0, I NT,
RES
Ports A to 0,
INT, RES
Ports A and B,
INT, RES, TEST
VI = -IV
Ports A and B,
iNT, RES, rEST
VI ~ -llV
Ports C and
VI =-IV

°
°

Ports C and
VI = -IIV
Ports C to I
10H = -1.0 mA

-1.0

V

-2.3

V

Ports C to I
10H =-3.3 mA

-10

/lA

Ports C to I
VO=-IIV

-50
440

mA
KHz

129

p.PD547

Ta

= 25

u

C. f

= 1 MHz

CAPACITANCE
LIMITS

PARAMETER

SYMBOL MIN TYP MAX UNIT TEST CONDITIONS

Input Capacitance

CI

15

pf

Output Capacitance

Co

15

pf

Input/Output Capacitance

CIO

15

pf

f = 1 MHz

CLOCK WAVEFORM

1----1/1 ---..!
OV- r

--

VGG- - - - -

K

ITEM

MI LLiMETERS

A

56.0 MAX
2.6 MAX
2.54
0.5 ± 0.1

B

C
0
E
F

G
H
I
J
K

L
M

50.8
1.5
3.2MIN
0.5 MIN
5.22 MAX
5.72 MAX
15.24
13.2
0.3± 0.1

PACKAGE OUTLINE
iJ PD547C

INCHES

2.2 MAX
0.1 MAX
0.1
0.02 ± 0.004
2.0
0.059
0.126MIN
0.02 MIN
0.20 MAX
0.22 MAX
0.6
0.52
0.01 ± 0.004

SP54 7-9-78-G N-CAT

NEe

NEe Microcomputers, Inc.

fLPD547L

fLCOM·44 SINGLE CHIP MICROCOMPUTER
DESCR IPTION

ABSOLUTE MAXIMUM
RATINGS'

The pPD547L is a low power version of the pOOM-44. It is a modified PMOSdevice
requiring a -8 volt power supply with a reduced supply current specification. As a
pOOM-44, it includes 1000 x 8 ROM, 64 x 4 RAM and 35 I/O lines in a 42 pin plastic
dual-in-line package.
Operating Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . ... -10°0 to + 70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +125°C
Supply Voltage . . . . . . . . . . . . . . . ,' . . . . . . . . . . . . . . . . . . . -15 to +0.3 Volts
Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15 to +0.3 Volts
Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15 to +0.3 Volts
Output Current ...... ,' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , -4 mA
COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent

damage to the device. This is a stress rating only and functional' operation of the device at these or
any other conditions above those indicated in the operational sections of this specific~'~jon is n.ot
implied. Exposure to absolute maximum rating conditions for extended periods may a~ifect device

rei iability.

*Ta = 25°0

DC/ AC CHARACTERISTICS

Ta = _10°0 to +70°0, VGG = -8V ±10%
LIMITS
PARAMETER

SYMBOL

MIN

TYP

TEST
CONDITIONS

MAX

UNIT

-1.6

V

Ports A to D, INT,
RES

VGG

V

Ports A to D,
INT, RES
Ports A and B,
INT, RES, TEST
VI = -lV

Input High Voltage

VIH

0

Input Low Voltage

VIL

-3.8

Input Leakage
Curr'mt High

IUH

+10

IlA

Input Leakage
Current Low

ILiL

-10

IlA

I/O Leakage

IIOH

+10

IlA

IIOL

-10

IlA

Paris C and D
VI = -'9V

-1.0

V

Ports C to I
IOH =-0.7 rnA

-2.3

V

Ports C to I
IOH =-2.6 mA

-10

Il A

Ports C to I
VO=-9V

-25

rnA

180

KHz

Current High

I/O Leakage
Current Low

Output Voltage

VOHl
VOH2

I
Output Leakage
Current

10L

Supply Current

IGG

Oscillator Frequency

F

-15
100

Ports A and B,
INT, RES, TEST
VI = -9V
Ports C and D
VI = -lV

1:U

JLPD547L

T a = 25°C; f

=

1 MHz

PARAMETER
Input Capacitance
Output Capacitance
Input!Output Capacitance

CAPACITANCE
LIMITS
SYMBOL MIN TYP MAX UNIT TEST CONDITIONS
CI
Co
CIO

15
15
15

pf
pf
pf

~---l/f

f = 1 MHz

CLOCK WAVEFORM

---...I

ov-- -vGG-----

PACKAGE OUTLINE
/JPD547LC

,ITEM

MILLIMETERS

A

D

56.0 MAX
2.6 MAx
2.54
0.5 ± 0.1

E
F

50.8
1.5

B

C

G
H
I

J
K
L
M

3.2 MIN
0.5 MIN
5.22 MAX
5.72 MAX
15.24
13.2
0.3± 0.1

INCHES
2.2MAX
0.1 MAX
0.1
' 0.02 ± 0.004
2.0
0.059
0.126MIN
0.02 MIN
0.20 MAX'
0.22 MAX
0.6
0.52
0.01 ± 0.004

SP54 7L·9-78-GN·CA T

NEe

NEe Microcomputers, Inc.

JLPD552

JLC0I\t1.44SINGLE CHIP MICROCOMPUTER
DESCRIPTION

The IlPD552'is a high' negative output version of the IlCOM:44. This PMOS, -10 vort'
part i,s designed with outputs capable of being pulled ":35volts. This allows direct
interfacing with Fluorescent Indicator Panels (FIPs). As a1lCOM44,it inchides 1000 x
8 ROM, 64 x 4 RAM and 35 If0 lines in a 42 pin plastic dual-in,·line package.

ABSOLUTE MAxIMUM
RATINGS*

Operating Temperature ... '. . . . ... . . . . . .. . . . . •. .. .. .. -10°C to+70°C
Storage Temperatu re . . . . . . . . . . . . '. . . . . . . . . . .. ... • . .. , -40° C to + 125° C
Supply Voltage, . . . . . . . . . . . . . . . . . . . . : . . . . . . . . . . . . .. -15 to +0.3 Volts
'Input Voltages (Port A,iNT, RES, TEST) . . . . . . . . . . " . . . . .. -15 to +0.3 Volts
(All Other Inputs) . . . . . . . . . . . . . . . . . . . . . . . -40 to +0.3 Volts
Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to +0.3 Volts
Output Current (Each Output Bit) . • . . . . . . . . . . . . . . . . . . . . . . . . .-12 mA
(Total Current) . '. . . . . . . . . . . . . . . . . . . . . . . . . • ;. -60 mA

to

COMMENT: Stress above those listed under "Absolute MaxirTlum ,Ratings" may cause permanent
damage til the device. This is a stress rating only and functional operation of the device'at these or,
any 'other conditions above those indicated in the operationaisectionsof this specification i.'not
implied. Exposure to absolute maximum rating conditions "for'extended periods may affect device
rei iabil i t y . '
,

*Ta =25°C

DC/AGCHARACTERISTICS

'Ta =-10°Cto +70°C, VGG =-10V ± 10%
"

LIMITS
PARAMETER

SYMBOL

MIN

TYP

MAX UNIT

Inpui High Volta!ie '

VIH

0

Input Low Voltage

VIL1

-7.5

VGG

V

VIL2
ILiH

• -7.5

-35
+10

/lA

ILlL1

-10

/lA

ILlL2

-30

/lA

IIOH

+10

/lA

ilOL1

-10

/lA

IIOL2

-30

~A

Input L~kage
Current High
Input Leakage "
Current Low"

1/0 Leakage
Current High
1/0 Leakage
C~rrerrt 'Low

-3.5

~-

V

V

Output Voltage"

VOH

Output Leakage
Current

lOll

-10

/LA

IOL2

-30

/lA

-50
440

mA
KHz

Supply Cu rrent
Oscillator Frequency

IGG
F

-2.0

-30
150

V

II

TEST
CONDITIONS
Ports A to D,INT"
RES
Ports A and B,
INT, RES
Ports C and D
Ports A and B,
jij'f, RES, TEST
VI =~IV
Ports A and B,
iNT, RES, TEST
VI =-IIV
Parts A and B
VI = -35V
Ports C and D
VI =-IV
Ports C and D
VI =-IIV
Ports C and D
VI =-35V
Ports C to I
lo=-SmA
PortsC to I
VO=-IIV
Ports C to I
,VO=-35V

:133

f'PD552
CAPACITANCE

Ta=25"C,f=1MHz
. LIMITS
PARAMETER

"

SYMBOL MIN TYP MAX UNIT TEST CONDITIONS

Input Capacitance

CI

15

pf

OUtput Capacit~nce .

Co

15

pf

Input/OutpUt Capacitance

Cia

15

i>f

ovm_~
~"'

f = 1 MHz

'''~ _____
~.~.OV

CLOCK WAVEFORM

_ _ _....

vGG--- - -

PACKAGE OUTLINE
",PD552C

, ~ "

"

ITEM

MILLIMETERS

A
B
C

56.0 MAX
2.6 MAX

0
E
F
G
H

r
J
K

L
M

2.64
0.5±0.1
50.B
1.5
3.2 MIN
d.5MIN
5.22 MAX
5.72 MAX
15.24
13.2
0.3± 0.1

INCHES

2.2 MAX
0.1 MAX
0.1
0.02± 0.004
2.0
0.059.
0.126 MIN
0.02 MIN
O.2DMAX
0.22 MAX
0.6
0.52
0.01 ± 0.004

SP552·9·78GN·CAT

NEe

NEe Microcomputers, Inc.

fLPD651

fLCOM·44 SINGLE CHIP MICROCOMPUTER
DEseR IPTION

ABSOLUTE MAXIMUM
RATINGS*

The pPD651 is a CMOS version of the pCOM-44. It features a single +5 volt power
supply, a 2 mA (max). 800 pA (typ) current drain and e~tended temperature range.
As a pCOM-44, it includesl000 x 8 ROM, 64 x 4 RAM and 35 I/O lines ina42 pin
plastic dual-in-line package, or a 52 pin flat plastic package.
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . .
Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Current (Each Output Bit) . . . . . . . . . . . . . . . . . . . _ ..

_30°C to +85°C
_55°C to +125°C
-0.3 to +7.0 Volts
-0.3 to +7.0 Volts
-0.3 to +7.0 Volts
2.5 mA

COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause perma'nent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability

DC/AC CHARACTERISTICS

T a =-30°Cto+85°C, VCC=+5V± 10%.
LIMITS
PARAMETER

SYMBOL

MIN

Input High Voltage

VIH

0.7VCC

Input Low Voltage

VIL

Input, Leakage
Current High

IUH

Input Leakage
Current Low
1/0 Leakage
Current High
1/0 Leakage
Current Low
Output High
Voltage 1

Output High
Voltage 2
Output Low Voltage

Supply Current
Clock High
Voltage
Clock Low
Voltage
Clock Leakage
Current High
Clock Leakage
Current Low
Clock Frequency
Clock Rise and Fall
Times
Clock Pulse Width

TYP

MAX

UNIT

TEST CONDITIONS
Ports A to D, INT, RES

VCC

V

0.3VCC

V

Ports A to D, INT, RES

+10

IJ,A

Ports A and B, INT, RES
(VI = VCC)

IUL

-10

IJ,A

Ports A and B, INT, RES
(VI =OV)

IIOH

+10

IJ,A

Ports C and D (VI = VCC)

IIOL

-10

IJ,A

Ports C and D (VO - OV)

VCC-0.5

V

VCe-0•5

V

Ports C and D
(JOH =-1 mAl
Ports E to I
(JOH =-1 mAl

VCC-2.5

V

Ports C to I IIOH - -2 mAl
Ports E to I
(JOL = 2 mAl
Ports E to I
IIOL=1.2mA)

VOH1

VOH2

0

VOLl

0.6

V

VOL2

0.4

V

2.0

VH

0.7VCC

VCC

mA
V

CLO, Ext. Clk.

VL

0

0.3VCC

V

CLO, Ext. Clk.

0.8

ICC

ILH

200

IJ,A

CLO, Ext. Clk.

ILL

-200

IJ,A

CLO, Ext. Clk_
(VOl ~OV)

('{mL=V~

f

150

tr, tf

0

tW

0.5

Rev/l

440
0.3
5_6

KHz
!J,S

Ext. elk.

IJ,S

Ext. Clk.

a

,.,. PD651

T if = -30°C to +85°C. VCC

CAPACiTANCE

=+5V ± 10%.
LIMITS

PARAMETER
I nput Capacitance
Output Capacitance

1/0 Capacitance

MAX

UNIT

CI

15

pf

Co

15

pf

CIO

15

pf

SYMBOL

MIN

TYP

1/f _ _ _ _ _

TEST CONDITIONS

f = 1MHz

CLOCK WAVEFORM

~

- - - - - - - - 0. 7V cc

OV - - - - -

K

i

,

A ' .

'.

~

DUAL-iN-LINE
PACKAGE OUTLINE

~~J' J~.~:PD651C
ITEM

MILLIMETERS

A

56.0 MAX

2.2 MAX

INCHES

6

2.6 MAX

0.1 MAX

C

2.54

0.1

D

0.5 + 0.1

0.02 + 0.004

E

50.6

F

1.5

0.059

G

3.2 MIN

0.126 MIN

H

0.5 MIN

0.02 MIN

I

5.22 MAX

0.20 MAX

J

5.72 MAX

0.22 MAX

2.0

K

15.24

0.6

L

13.2

0.52

M

0.3 + 0.1

0.01 + 0.004

f'PD651

PIN CONFIGURATION,
FLAT PACKAGE

NC
NC

NC
NC
NC

NC
PH2
PH3
P'o
P',

PE3
PE2
PE,

"PO

PEo

651

P'2
PAO
PA,
PA2
PA3

P03
P02
Po,
POo
RES

PBo

NC

Notes: ~ NC = No connection.
2 p. in 1 index ("0" mark) is located where the pin 2 line and pin 51 line cross,
3 Pin 7 and 33 of "PD651 G are connected inside the package

iA -1'~B
-------y-

FLAT PACKAGE OUTLINE
).lPD651G

II

ITEM

MILLIMETERS

A

12.0 MAX.

B

1.0 ± 0.1

C

14.0

D

0.4

E

21.S ± 0.4

INCHES
0.47 MAX.
0.04 ± 0.004
0.55
0.Q16
0.S6 ± 0.Q16

F

0.15

0.006

G

2.6

0.1

SP651 -1 -SO-CA T

137

NOTES

I.
~"

I

1'38

NEe

NEe Microcomputers, Inc.

jLPD550

JLCOM-45 SINGLE CHIP MICROCOMPUTER
DESC R I PT I ON

ABSOLUTE MAXIMUM
RATINGS*

The J.Lf'D550 is the 640 x 8 ROM version of the t/COM-45_ This PMOS', -10 volt part
features both TTL-level compatible inputs as well as outputs capable of bei'ng pulled
to -35 volts. This allows direct interfacing with Fluorescent Indicator Panels (FIPs).
As a t/COM-45, it includes 32 x,4 RAM and 21 I/O lines ina 28 pin plastic dual-inline package.
Operating Temperature . . . . . . . . . . . . . '~ ... " . . . . . . . . . . . . _10°C to +70o C
Storage Temperature ;' . . .. . . . . . . .. . . . . . .. . . . . . . . . . .. -'40°C to +125°C
Su~ply Vt;>ltage. . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . .. -15 to +0.3 Volts
Input Voltages (Port A, INT, RES, TEST) . . . . . . . . . . . . , .... -15 to +0.3 Volts
(All Other Inputs) ..... . . . . . . . . . . . . . . .. -40 to +0.3 Volts
Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to +0.3 Volts
Output Current (Ports C, 0) . . . . . . . . . . . . . . . . . . . . . '. .. . . . . . . .. -4 mA
(Ports E, F, G) . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . -15 mA
(Total Current) ....... , . . . . . . . . . . . . . . . . . . . . . . -69,mA
COMMENT: Stress above those listed under "Absolute Ma,ximum Ratings" may,cause permanent
damage to the device. This is a :stress rating only and functional operation cif the device ~t these or
any other conditions above those indicated in the operational sections of this specification is not
implied., Exposure to absolute maximum rating conditions for extended periods may affect device
renability.

DC/AC CHARACTERISTICS

Ta = _10°C to+70°C, VGG = -IOV'± 10%.
PARAMETER

SYMBi::lI..,

Inout High Voltage
Input Low Voltage

MIN

VIH,

0

VILl
VIL2

-4.3
-4.3

LIMiTS
TYP
MAX
-2.0

UNIT

TEST
CONDITIONS

D,

V

Ports A, C,
RES

INT,

VGG
-35

V
V

Ports A, INT, RES
Port C and D

Input Leakage Current
High

ILIH

+10

/LA

Ports A; INT, RES,
TEST
VI = lV

Input' Leakage Current
Low

ILIL

-10

/LA

I/O ,Leakage Current
High

IIOH

HO

/LA

I/O Leakage Current Low

II0Ll

-10

/LA

IIOL2

-30

/LA

Ports A"INT, RES,
TEST
VI =-llV
Ports C and D
VI =-1V
Ports C and D
VI =-11V
Ports C and D
VI = -35V
Ports C and D
10=-2 mA

Output Voltage

Output Lea kage Current

Supply, Current
'Oscillator Frequency

VOHl

-1;0

V

VOH2

-2.5

V

lOLl

-10

/LA

IOL2

-30

/LA'

-40
440

rnA
KHz

IGG
F

Rev/1

-20
150

Ports E, F, G
10 = -10 mA
Ports C, D, E, F, G
Vo = -11V
Ports C, D" E, F, G
Vo = -35V

II

JoLPD550
Ta=25"C, f=.l MHz

CAPACITANCE
LIMITS

PARAMETER
I nput Capacitance

SYMBOL MIN TYP

MAX

CI

UNIT TEST CONDITIONS

15

pf

15

pf
. pf

Output Capacitance

Co
Input/Output Capacitance ..... CIO

15

f = 1 MHz
>

CLOCK WAVEFORM

t----l/f--~

ov-_ -.vGG-----

PACKAGE OUTLINE
j.lPD550C

ITEM' ,
A

'MILLIMETERS

INCHES

38,0 MAX.

1.496 MAX.

B

2.49

0.098

C

2.54

0.10

0

0.5 ± 0.1

E

33,02

0.02 ± 0.004
: 1.3

F

1.5

0.059

G

2.54 MIN.

0.10 MIN.

H

0.5 MIN.

0.02 MIN.

I
J

5.22 MAX.

0.205 MAX.

5.72 MAX.

0.225 MAX.

K

··15.24

0.6

L

13.2

0.52

M

025 + 0.10.
.
0.05

001 + 0.004
.
0.002

SP550-10,79.-GN-CAT

140

NEe

NEe M,icrocomputers,lnc.

~PD550L

~ COM-45
•- '

DESCRIPTION

ABsoLuTE MAXIMUM
RATINGS*

•

SINGLE CHIP MICROCOMPUTER·

',,-

>'

,,'

. . . .'

..- . , . , , '

.',.

r-

' , '

,

ThettPD55o.l is the 640. x8 HOM,19W power version of the ttCOM-45_ .It is a modified
PMOS device requiring a -8 Volt power supply, with a red~ced supply current spec'ification. ThettPD55DL features both TTL level compatible inputs as well as outputs
capable of being p'ulled to-35 Volt~ for direct interfacing with FluorE!scent>lndicator
Panels (FIPs). Asa tlCOI\ll-45~it.·inciudes 640. x SHOM;' 32x 4 RAM', and 21 I/O lines
in a 28 pin plastic dual-in-line package.

OperatingTempe~at~re

•....j '.' ••• : , •••.'._' •••.•••••••• _10°C to +7o. o C
Storage Temperature ...... ': .................. , .. _ . '.' .. :4Do C to +125°C
Supply Voltage '" ...... , .; .•.....•..•....... ,'.. ;. " ... ~15 to' +0..3 Volts
Input Voltages (Port A, INT, RES) ... , ... : . . . . . . . . . . , ... ~15 to: +0.3 Volts
(Ports C, D) , . . . . . . . . . . . ,.............. -4o..to +0..3 \lolts
Output Voltages .......... ; . . . . . . . . . . . . . . . . . . . . . . .. -40. to +0..3 Volts
Output Current (f'prts C, D) . . . . . . . . . . . . . . ' ..................... ;:4 mA
(PorKE,F, G) . . . . . . . . . . . . . . . :. : ',' .. : ... ; ... '. -15mA
.(Total Current) .. , . . . . . . . . . . . , ....... : . , .. ' ..... -60. mA
COMMENT: Str~ss above those listed under "Absolute Maximum Ratings" may cause.permanent
damage tei the device. This is a stress rating only and functional opera.tion of the device at these or

any ot~er conditions ?bove 't'h6se

indicat~ in the opera~ional sections of th is specification is not

'impli~d,Exposure to absolute maximum rating conditions for extended periods may affect.device

.

.

~~~

.

.

.

UNIT

CONDITIONS

*Ta ='25°C

DC/AC CHARACTERISTICS

T a =~1O°Cto+70°C'VGG'=-av -+ 10%
LIMITS
PARAMETER
Input Voltage High

SYMBOL

MIN

VIH

0

VILl

-4.5

. VIL2

-4.5

Clock Voltage High

VrkH

0

Clock Voltage Low

.,Vct>L

Input Voltage Low

I nput Leakage Current
High
. Input Leakage'Current,
Low

TYP

TEST
MAX
-1.6

VGG
-35
-0.6

-5.0

V

Ports A,C, D, INT, RES·

V

Ports A,'.INT, RES

V

Ports C and D

V

CLO Input, External Clock

V'

C LO Input, External Clock

IUH

VGG
+10

p.A

Ports A, C, D, INT, RES
VI :'-lY'

lUll

-10

p.A

Ports A, C, D, INT, RES
VI = -9V

-30

p.A

Ports C and D; VI = -35V

Clock Leakage Current
High

I.LH

+200

p.A

Clock Leakage Current
Low

ILL

-200

p.A

CLO I nput, External Clock,
VOH = OV
CLO Input, External Clock,
VOL =-9V

Output Volta~. High.

VOHl

-1.0

V

Ports C and D; 10 = -2 mA

VOH2

-2.5

V

: Ports E,F, G; 10 - -10 mA

IUL2

I LOll

-10

p.A

Ports C, D, E, F, G
Vo =-9Y

ILOL2

-30

p.A

Ports C, D, E, F, G
Vo = -35V

Output Leakage Current
'.

SupplV Curre!)t

IGG'

O",illator Frequency

t.

Rise and Fall

t"tf

-10

100

-24

mA

180

KHz

0

0.3

p.s

External Clock

Times

Clock Pulse Width High

tdlWH

2.0

.8.0

p.s

External Cioek

Clock Pulse Width Low

tWL

2.0

11.0

p.s

External Clock.

14l

•

p.PD550L

CAPACITANCE
.LIMITS

PARAMETER

SYMBOL MIN TVP MAX UNIT TEST CONDITIONS

Input Capacitance

CI

15

pf

Output Capacitance

Co

15

pf

Input/Output Capacitance

tlO

15

pf

f = 1 MHz

CLOCK WAVEFOHM

1 - - - - - - 1 / 1 -------1
t.pWL
- -

VGG""- - -

-

-

- - -O.6V

--

PACKAGE OUTLINE
J.lPD550LC

ITEM

MILLIMETERS

A

38.0 MAX.

INCHES
1.496 MAX.

B

2.49

0.098

C

2.54

0.10

D

0.5 ± 0.1

0.02 ± 0.004
1.3

E

33.02

F

1.5

0.059

G

2.54 MIN.

0.10MIN.

H

0.5 MIN.

I
J

5.22 MAX.
5.72 MAX.

0.02 MIN.
.: 0.205 MAX.
0.225 MAX.

K

15.24

0.6

L

13.2

0.52

M

025 + D.W
.
0.05

+ 0.004
0.01

0.002

SP550L·l0·79·CAT

NEe

NEe Microcomputers, Inc.

,",PD554

JLCOM.45 SINGLE CHIP MICROCOMPUTER
DESCRIPTION

The J,!P0554 is the 1000 x 8 ROM version of the J,!COM-45. This PMOS; -10 volt part
features both TTL-level compatible inputs as well as outputs capable ot being puiled to
-35 volts. This allows direct interfacing with Fluorescent Indicator Panels (FIPs). As a
J,!COM-45, it includes 32 x 4 RAM and 21 I/O lines in a 28 pin plastic, dual-in-line
package.

ABSOLUTE MAXIMUM
RATINGS*

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _10°C to +70 o C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. _40°C to +125°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15 to +0.3 Volts
Input Voltages (Port A, INT, RES, TEST) . . . . . . . . . . . . . . . . . -15 to +0.3 Volts
(All Other Inputs). . . . . . . . . . . . . . . . . . . . . .. -40 to +0.3 Volts
Output Voltages ... : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to +0.3 Volts
Output Current (Ports C, 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -4 mA
(Ports E, F, G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15 mA
(Total Current) . . . . . . . . . . . . ". . . . . . . . . . . . . . . . . . . -60 mA
COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent

damage to the device. This is a stress rating only and functional

oper~tiH

0

Clock Voltage Low

V1>L

-5.0

I nput Leakage Current

-0.6

CLO Input, External Clock

VGG

V

IUH

+10

/lA

Ports A, C, D, INT, RES
VI ~ -1V

IUL1

-10

/lA

Ports A, C, D, INT, RES
VI ~ -9V

High
Input Leakage Current

CONDITIONS

Low

-30

/lA

Ports C and D; VI = -35V

Clock Leakage Current
High

IL1>H

+200

/lA

CLO Input,vOH - OV

Clock Leakage Current

IL1>L

-200

/lA

CLO Input, VOL = -9V

IUL2

~.
Output Voltage High

VOH1

-1.0

V

Ports C and D; 10

VOH2

-2.5

V

Ports E, F, G; 10

ILOL1

-10

/lA

Ports C, D, E, F, G
Vo ~ -9V

ILOL2

-30

/lA

Ports C, D, E, F, G
Vo ~ -35V

Output Leakage Current

Supply Current

~

-12

-24

mA

180

KHz

Oscillator Frequency

IGG
f

100

Rise and Fall

tr,tf

0

0.3

/lS

External Clock

Times

Clock Pulse Width High

tWH

2.0

8.0

/lS

External Clock

Clock Pulse Width Low

t1>WL

2.0

8.0

/lS

External Clock

-2 mA

-10mA

II

,""PD554L

Ta

= 25°C, f = 1 MHz.

CAPACITANCE
LIMITS

PARAMETER
I nput Capacitance
Output Capacitance
I nput/Output Capacitance

SYMBOL MIN TYP MAX UNIT TEST CONDITIONS
CI

15

pf

Co

15

pf

CIO

15

pf

f = 1 MHz

CLOCK WAVEFORM

~---l/f--_0.1

ov-- --

VGG-- - - -

PACKAGE OUTLINE
J.lPD554LC

ITEM

MILLIMETERS

INCHES

A

38.0 MAX.

1.496 MAX.

B

2.49

0.098

C

2.54

0.10

D

0.5 ± 0.1

0.02 ± 0.004

E

33.02

F

1.5

1.3
0.059

G

2.54 MIN.

0.10 MIN.

H

0.5 MIN.

0.02 MIN.

I

5.22 MAX.

0.205 MAX.

J

5.72 MAX.

0.225 MAX.

K

15.24

0.6

L

13.2

0.52

M

025 + 0.10
.
0.05

+ 0.004
0.01

0.002

SP554L-l0-79-CAT

146

NEe

NEe Microcomputers, Inc.

fLPPS52

JLCOM·45 SINGLE CHIP MICROCOMPUTER
DESCR IPTION

The J.lPD652 is a CMOS version of the J.lCOM-45. It features a single +5 volt power
supply, a 2 mA (max). 800 J.lA (typ) current drain and extended temperature ra~ge. As
a J.lCOM-45, it includes 1000 x 8 ROM, 32 4 RAM, and 21 I/O I.ines in a 28 pin
plastic dual-in-lifle package .

'x

. ABSOLUTE MAXIMUM
RATINGS*

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -30°C to +85°C
Storage Temperature . . . . . . . . . . . : . . . . . . . . . . . . . . . . . . . _55°,C to +125°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ":'0.3 to +7.0 Volts
Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . : .... -0.3 to +7.0 Volts
Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,-0.3 to +7.0 Volts
Output Current (Each Output Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 mA
COMMENT: Stress above tnose listed under "Absolute Maximum Ratings" may cause permanent
damage'to the devi~e. This is a stress rating only and functional operation 'of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum' rating conditions for extended periods may; affect device

reliabil';ty.

.

.

,

*Ta; 25°C

DC/AC CHARACTERISTICS

Ta; -30°C to +85°C VCC; +5V -+ 10%
LIMITS
PARAMETER

SYMBOL

MIN

I nput High Voltage

VIH

0.7VCC

TYP

Input Low Voltage

VIL

Input Leakage
Current High

IUH

+10

Input Leakage
Current Low
I/O Leakage
Current High
I/O 'Leakage
Current Low.
Output High
Voltage 1

ILiL

-Hi

/JA

IIOH

+10

/JA

Ports A, C, D, INT, RES
(VI = OVI
Ports Cand D (VI = VCC)

IIOL

-10

/JA

Ports C and D (VO = 0V)

VCC-0.5

V

VCe-0.5

V

Ports C and D.
(lOH =-1 mAl
Ports Eta G
(lOH = -1 mAl

MAX

UNIT

TEST CONDITIONS
0"

Output High
Voltage 2
Output Low Voltage

Supply Current·
Clock High
Voltage
Clock Low
Voltage
Clock Leakage
Current High
Clock Leakage
Current Low
Clock Frequency
Clock Rise and Fall
Times
Clock Pulse Width

VOHl

VCC
0.3 V r.r.

0

V

Ports A,.C, DiINT, RES

V

Ports A, C, D; INT, RES

/JA

Ports A, C, D,'INT, RES
(VI = VCC)

V

PortsGto G (IOH =-2mA)

VOL1

0.6

V

VOL2

0.4

V

Ports E to G
(lOL = 2 rnA)
Ports E to G
(lOL = 1.2 rnA)

2.0

VOH2

VCC-2.5

0.8

VI/>H

0.7VCC

VCC

rnA
V

CLO, Ext. Clk.

VI/>L

0

0.3VCC

V

CLO,. Ext. Clk.
CI..O, Ext. Clk.
(VOH = VCe!
CLO, Ext. Clk.
(Vni ;OV)

ICC

ILI/>H

200

/JA

ILI/>L

-200

/JA

440

KHz

I

tr, tl
tl/>W

150
0
0.5

0.3

/JS

,Ext. Clk.

5.6

/JS

Ext. Clk.

147

t, ,",

•

p.PD652
.

Ta

.'
=-30·c'to +sijoc, VCC =+5V ± 10%

CAPACITANCE
LIMITS

PARAMETER

SYMBOL

MIN

Input Capacitance'
·.CI
Output Capacitance
Co
I/O Capacitance
CIO

TYP

MAX

UNIT

~5

pf
pf
pf

15 ..
15

TEST CONDITIONS

,
f = 1 MH.z

CLOCK WAVEFORM

lIt

.;.-- - -.,.. - - O.7V.CC

OV-----

PACKAGE OUTLINE
IlPD652C

ITEM

MILLIMETERS

INCHES

A

38.0 MAX.

1.496 MAX.

B

2.49

0.098

C

2.54

0.10

0

0.5 ± 0.1

0.02 ± 0.004
1.3

E

33.02

F

1.5

0.059

G

2.54 MIN.

0.10MIN.

H

0.5 MIN.

0.02 MIN.

I

. 5.22 MAX.

0.205 MAX.

J

5.72 MAX.

0.225 MAX.

K

15.24

0.6

L

13.2

0.52

M

025 + 0.10 ,
.
0.05

+ 0.004
0.01

0.002'

SP652-1D-79-GN-CAT

NEe

NEe Microcomputers, Inc.

JLPD555

EVACHIP·42

OESCR I PTI ON

The!.lPD555 is a system evaluation chip designed to support bot/1.hardware and software
debugging of the !.lCOM-42 (!.lPD548) one-chip microcomputer system;
The !.lPD555 and the!.lPD548 have the same functionality in all aspects except that the
!.lPD555 does not contain a read only memory, but provides addressing capabil ity to
external memory and HOLD function for step-by-step operation.

FEATURES.4-BitParalieIProcessor
• Powerful 72 Instruction Set Including Decimal/Binary Arithmetic Operations
• 10 IJS Instruction Cycle Time
eAddressing Capability up to 1920 WorCJs by 1O-Bits of External Program Memory
• 96 Words by 4-Bit Data Memory.On Chip
• 4-Level Su broutines
• Two Interrupt Input Lines (fA andlB)
• HOLD Capability
• A Variety of I nput/OutputPorts 10 Discrete Output Ports (Fg-FO)
Two 8-Bit Output Ports (U7-UO; R7-RO)
4-B it I nput Port (1<:3- KO)
4-Bit Input/Output Port (S3-S0)
I/O Level Compatible with !.lPD5101
1-Bit TestlnputLine
• P-Channel MOS
• Open Drain Output
• Single Power Supply: -10V
• Available.in a 64 Pin Ceramic Dual-in-Line Package
PIN CONFIGURATION

GND
P3
P2

Pl
Po
A6
A5
A4
A3
A2
A1
AO
10
1.1
12
'3
14
15
16
17
18
19

HOLD
RO
R'1
R2
R3
R4
R5
R6
R7
(-10V) VGG

uo
U,
U2
U3
U4
U5
U6
U7
F9
F8
F7
F6
F5
F4
F3
F2
F1
FO
S3
S2
S1
So
IA
18
TEST
K3
K2
K1
KO

PIN NAMES

Po - P3

Page Output

AO-A6

Address Output

10- 19

Instruction Input

HOLD

HOLD Input

AO- A7

Output Port R '



Clock Input

RES

Reset Input

K'

K4 Test Input Line

KO- K3

K Input Port

TEST

Ie Test

IA,IB

Interrupt Input

Fg

UO- U7

.

Input/Output Port S

So - 53
Fa -

Input

Output ,Port .F

I

Output Port U

."

149;

H.-Pll5~5
,

• U7·Q

Fg· Fa

HOLD

IA

18

K4

S:LOCK DIAG RAM

CG

RES

Operating Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Storage Temperature ........................ , .......
SupplyVoltageVGG . . . . . . . . . . . . . . . . . . . . . . . : .......
All Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . , .....
All Output Voltages . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . .

-10°C to +70°C
-40°C to +125°C
-15 to +0.3 Volts
-20 to ;1"0.3 Volts
- 20 to +0.3 Volts

ABSOLUTE MAXIMUM
RATINGS*

. COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. Th is is a stress rating only and fu Ilctional OI'eration of the device at these or
any other conditions above those indicated in the operational ·sections of this specification is not
. implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
'Ta '" 25°C

CAPACITANCE
LIMITS

",

. ,-PARAMETER

SYMBOL MIN TYP

MAX

TEST
UNIT CONDITIONS

Input Capacitance

CI

.15

pf

Output Capacitance

Co

15

pf

Input/Output Capacitance

CIO

15

pf

15(1

~

f= 1 MHz

fLPD555

DC CHARACTE R ISTICS

Ta = -10°C to +70°C; VGG = -10V ± 10%, unlessotherwise noted.
LIMITS
PARAMETER

AC CHARACTE RISTICS

SYMBOL

MIN

TYP

MAX

UNIT

TEST
CONDITIONS

High level Input
Voltage

VIH

0

Low Level Input
Voltage

VIL1

-4.3

V

VIL2

-7.0

V

Except S, o.RT1 2 .

So

Po.RT11

S4

Po.RT 10

S1

i' o.RT43

S5

PORT 10 - Po.RT13

Input Po.RT 1

Po.RT 30 - Po.RT 31

o.utput Po.RT 3

Po.RT 40 - Po.RT 43 . I/O. Po.RT4
TO -T6

'SO - S7

Dig.it Drive
Signals
Segment Drive
Signals

Po.RT42

S2

ClK

Po.RT41

S6

RESET

Reset

Po.RT40

S3
VGG

T5

S7

Power S.upply
(-6Vto-10VI

T4

TO

"SS

Ground

T3

T1

VSS

T2

Clock.

II

·/-LPD7,520
The pPD7520 is a low-cost, 4-Bit Single Chip Microcomputer, fabricated with
P,Channel MOS technology. Its design is optimized .for applications which require an
. LED Display, but thepPD7520 can also function efficif!ntly as a general-purpose
microcomputer. Its wide operating voltage range and minimum external component
r~quiremerits make the pPD7520 desirable for a broad range of applications.

FUNCTIONAL
DESCRIPTION

The pPD7520'spdw.ilrful instruction setencornpasses 47 of the pCOM,75 family
commands. These instructions can perform me'mory transfers, bit manipulation,
automatic increment/decrement, table look-up, constant table formulation, input of
c.ommand strings, and multiple branches .. These enhancements allow the user to create
highly efficient programs for his pPD7520 application.
The Programmable Display Controller of,the pPD7520 is designed to interface directly
with 4·digit to a·digit LED displays. Synchronization of the timing of the segment and
digit lines is accomplished automatically by the on-board display controller. Display of. an .
LED array can be done when the pPD7520 is configured in the general:purpose mode.

BLOCK DIAGRAM

PAOGRAM MEMORV
781 II 8 BIT ROM

INSTRUCTION

DECODER'
CONTROLLER

.
I
f

I

VOG_

v.. _

RESET_
eLK

".,

TO~

Operating Temperature . . . . . . . . . . . . . • . . . . . . . . . . • . . . . . . -10° to +70 0 C
Storage Temperllture •......•... " •......... , . . . . . . . . . -400 to+125°C
Supply Voltage .. ; . . . . . . . . . . . . . • _ . . . . . . . .. . . . • • .. -15 to +0.3 Volts
Input Voltage .............••.•..•........•.•.... -15 to +0.3 Volts
Output Voltage . . . . . . . . • . . . . . • . . . . . • . . . . . • . . . . . . . -15 to +0.3 Volts
Output Current (IOH Total) .•....•........•.•......•.•..... -100 mA
(lOL Total) ......•...•..•.•...•......•.•...... 90 mA
COMMENT: Stress above those listed under" Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at tnese or
any other conditi.ons above those indicated in the operational sections of this. specificatil'ln is not
implied .. Exposure to absolute maximum rating conditions for extended periods may affect device
reliabilitY .

158;'

ABSOLUTE MAXIMUM
RATINGS*

p.PD1520
CAPACITANCE

Ta =-10°C to +70°C;VGG =-6V to -10V
PARAMETER

liMITS

SYMBOL'
MIN

TYP

TEST
CONDITIONS

UNIT
MAX

Input
Capacitance

CI

15

pF

Port 1. Reset
f.,l MHz

Output
Capacitance

Co

TBA

pF

Port 3" SO-57. TO-T5
f = 1 MHz

1/0 Capacitance

ClIO

15

pF

Port 4.

Clock
Capacitance

CClock

TBA

pF

ClK.

@

f = 1 MHz

DC CHARACTE R ISTICS

@

f = 1 MHz

T.· -lO'C to +70'C. VGG' -6V to -IOV
PARAMETER

SYMBOL

Input Voltage
High

LIMITS
MIN

TYP

V,L

Low
Clock Voltage
High

VOH

Clock Voltage

VOL

Low
Input Load
Current

"H

Input Leakage
Current High

IUH

UNIT

TEST CONDITIONS

-2

V

Port 1, Pori 4, Reset. VGG

-1.8

V

Port', Port 4, Reset, VGG ;;; -6V to -10V

VGG+2

V

Port 1,Port 4, Reset, VGG =-9V ± lV

VGG+l

V

Port 1, port 4, Reset. VGG '" -6V to -10V

V

eLK, External Clock

V

elK. External Clock

V,H

Input Voltage

MAX

-0.5
TBA,

@

180

=

-9V ± lV

#A

jVGG --9V ± IV. V, =OV
Port 1. Res""jVGG --SV. V,-OV

+5

#A

Port 4, V, =OV
POrt 1, Reset, V.GG = -10V, VI'" OV

40

lULl

-5

#A

IUL2

-5

#A

Port 4. V,- OV

ILOH

TBA

#A

elK. External.Clock VOH =OV

Clock Leakage
Current Low

'LOL

TBA

#A

elK.

Output Voltage
Low

VOL

VGG+O·5

V

Output Current
High

IOH1

-1.0
-0.6

mA

Port 3,

VGG--9V± IV. V,," --1.0V
VGG - -6V. VOH - -l!JV

IOH2

-2.0
1.2

mA

Port 4,

VGG --9V ± IV. VO> --l.OV
VGG - -6V. VOH - -l!JV
VGG --9V ± IV. VO. - -2.0V
VGG --611. VOH- 2.0V

Input Leakage
Current Low

Clock Leakage

@

Current High

Port 3, VGG ;;; -6Vto-l0V No Load

-10
6

mA'

So-57.

IOH4

-48
27
-18

mA

VGG = -9V ± IV. Vn~ = -2.0V
TO·T5. VGG - 9V ± IV. Va> --l!JV
VGG - -BV. VOH --1.0V

0.2
O.S
0.2

mA

Port 3,

VGG --9V ± IV. VOL = VGG + lvQ)
VGG --9V ± IV. VOL' VGG + 3V1t)
VGG
VOL --5V 1
VGG
VOL --25VCi)

9
2
2

mA

So-S7

VGG --9V ± IV. VOL' -4V
V(;G = 9V ± IV. VOL - VGG + 3.5V
VGG - 6V. VOL' 2_5V

Port 4,

TO·T5:
Vo =OV

Port 4.

TO·T5:
VO' -IOV

1
lOLl

,

IOL2

4.5
1
1

Output Leakage
CUrfent High

C,lock VOL = -10V

IOH3

Output Current
Low

'LOH

+5

.A

Output Leakage
Current Low

'LOL

-5

#A

Supply Current

IGG

Notes:

E~ternal

@

-5

mA

--avo
--avo

TO' 2S'C: VGG' -9V No Load



-

Exchange
Complement
Exclusive OR

IJ.
[

11';')

Immediate data, used as an address where n is the bit length of
the address.

1

Additional comment or explanation

INSTRUCTION SET
SYMBOL DEFINITIONS

pPD7520

INSTRUCTION
SET

,

LOAD

L

A-(HLI

LIS

A-(HLI
L:L+1
Skip if L =OH

1
1

1

13

12

1

0

1

,0

11

10

1

1

1,

0

14

13

12

11.

10

1

1

Load the upper 4 bits of
Table Data in ROM to A:
Load the lower 4 bits of
. Table Data in ROM to HL

0

1

0

1

1

1

1

0

1

2

Load A with the contents

0

1

0

1

0

0

1

0

1

1

0

1

0

1

0

0

0

1

1

1'+S

L =OH

0

1

0

1

0

0

,0

0

1

1 +S

L = FH

0

0

Os

04

03

02

01

DO

2

2
2
1

LHI data 2

(HLI- (PC9-6. O. C. AIL

1

a. 'STORE
0

Immediate,da~a

A - (PCg-6. O. C. AIH

10

SKIP
CONDITION

0

[data 4 - 13.()J
H -data 2
[data 2: 11.()J
HL-data5

LAMT

CYCLES

0

Load A with 4 bits of

J

BYTES

0

A-data4

~-14
L- 13.()

DO

0,

LAI data 4

LHLI data S

INSTRUCTION CODE
D7 D6 D5 D4 D3 1)2 Dl

DESCRIPTION

'FUNCTIQN

MNEMONIC

Load H with 2 bits of
Immediate data
Load HL with 5 bits of
Immedi~te

11

data

of RAM addressed by HL

LOS

LAOR addr 6

A-(HLI
'L = L-1
Skip if L" FH

Load A with the contents of
RAM addressed by H L: incre-

ment L; skip jf L = OH
Load A with·the contents of
RAM addressed by H L;
decrement L; skip if L "" FH

A - (addr 61
[addr 6 = DS.()J

Load A with the conlents of
RAM addressed bv the 6 bit

ST

(HLI-A

immediate data addr 6
Store A into the RAM location
addressed by H L

STU data 4

(HLI-data4
L-L+ 1
[data 4 = 13.()J
A1'().-c. Hl'()
A3_2-00H
A-L
A-->(HL)

XAH
XAL
X

Store 4 bits of immediate
data info the RAM location
addressed by HL; increment L
Exchange A with H
Exchange A with L
Exchange A with the contents
of the RAM location addressed

1

1

1

2
1

13

12

11

10

1

1

1

1

Q

1

0

1

1

1

1

0

1

1

1

1

0

1

1

0

1
1

0

1

0

1

0,

1

1

1 +S

L =OH

1

0

1

0

1

0

0

1

1 +S

L

0
0

1
05

1
04

1
03

0
02

0
01

1
DO

2

2

0

1

0

1

0

1

0

0

0

1

1

0
0

1
1

1
0

0

1

0

0

1

by HL
A-(HL)
Skip if L -OH

Exchange A with the contents
of the R AM location
addressed by H L; increment L;

XOS

A-(HL)
L+-L-l
Skip if L = FH

Exchange A with the contents
of the RAM location
addressed by HL; decrement L;

XAOR addr6

A-(addr61:
[addr 6 = 05.()J

Exchange A with the contents

0

of RAM addressed by the 6-

0

XIS

L-L+ 1

skip if L =OH
z

FH

skip if L = FH

bit immediate data addr 6
ARITHMETIC AND LOGIC
AISC data 4

ASC

A-A+data4
Skip if carry
[data 4 = 13.()1
A-A+(HLI

skip if carry
ACSC

A.C-A+(HLI+C

skip if carry

EXL

A-AV(HLI

=1

Add the 4-bit immediate data
to A; Skip if carry is
generated
Add the cbntents of RAM
addressed by H L to A; skip if
carry is. generated
Add the contents of RAM
addressed by H L and the carry
flag to A; skip if carry is
generated

0

0' 0

0

13

12'

11

)0

1

1+S

Carry Flag

0

1

1

1

1

1

0

1

1

1 +S

carry Flag· 1

0

1

1

1

1

1

0

0

1

1 +S

Carry Flag:: 1

Perform an exclusive - OR
operation between the contents

0

1

1

1

1

1

1

0

1

1

0

1
1
1

1
1
1

1
1

1
1
,1

1
0
0

1
0

1
1

1
1

0

1
0
1

l'

1

of RAM addressed by HL and A;
CMA
RC
SC

A-A
C-O
C-I

store the result in A
Complement A
Reset carry Flag to 0
Set carry Flag to 1

0
0

1

INCREMENT AND DECREMENT
ILS'

L+-L+1

Increment L;

Skip if L =OH
(addr 61 -(addr 61 + 1
Skip if (addr 61 = OH
05-0 = OOH - 2FH

Skip if L =OH

'IORSaddr 6

OLS
OORSaddr 6

L-L-1
Skip if L = FH
(add. 61 - (add. 61- 1
Skip if (add. 61 = F H
[05'() - OOH-2FHI

Increment the contents of RAM
addressed by the 6 Bit immediate data addr 6; Skip if the
contents ~ OH
Decrement L;
Skip if L

= FH

Decrement the contents of

0

1

0

1

1

0

0

1

1

1 +S

L =OH

0
0

0
0

1
05

1
04

1
03

1

1
DO

2

2+S

(addr 61 =OH

~2

0
01

0

1

0

1

1

0

0

0

1

1 +S

L = FH

0

0

1

1

1

1

0

0

2

2+S

(addr6) - FH

0

0

RAM add.ossad by tho 6-Bit

immediate data addr 6; skip if
the contents - FH

Qs D4 03 02 01

Do

163

II

fLPD7520

INSTRUCTION
SET
(CaNT.)·

"

FUNCTION

MNEMON.IC

INSTRUCTION CODE
D7 D6 D5 D4 D3 D2 D,

DESCRIPTION

BIT MANIPULATION
RMB

IHL)bit..{l
[bit· Bl~l

5MB

(HL)bit~1

[bit

Reset a single bit of RAM.
denoted by Bl BO. at the
location addressed by HL, to
zero
Sat a single bit of RAM.
denoted by Bl BO. at the
location' addressed by' HL to
one

= Bl~l

DO

BYTES

CYCLES

0

1

1

0

,

0

Bl

Be

1

1

0

1

1

0

1

1

Bl

BO

1

1

2

2

SKIP
CONDITION

JUMP AND CALL
JMP add, 10

PCg~ ~

add, 10
[add, 10 - Pg~l

Jump to the address specified
by the 10 bit immediate
data add, 10

0
P7

0
P6

1
Ps

0
P4

0
P3

0
P2

Pg
PI

Ps
Po

JAM add, 2

P~·e~add'2

Jump to the address which
is specified by the 20bit
immediate data addr 2. A. and
IHL)

0
0

0
0

1
0

1
1

1
0

1
0

1
PI

1
Po

2

2

1

0

Ps

P4

P3

P2

PI

Po

1

1

0
P7

0
P6

1
Ps

1
P4

0
P3

0
P2

Pg
PI

Ps
Po

2

2

1

1

1

P4

P3

P2

PI

Po

1

1

0
0

1
1

0
0

1
1

0
1

0
0

1
1

1
1

1
1

1
1 +S

Unconditional

PC74~A

PC3~~(HL)
[add,2 = Pl~l

JCP add,6

PCs~ ~add,
[add, 6 • PS~1

CALL add' 10 Stack -PC + 2

P::J.~~ad~' 1~
[0 d, 10 -

CAL add, X

g~

Stack -PC + 1

~;J'd~ ;-!dd' X
01 P4P3000P2Pl POl

Jump to the address within
the current' page specified
. bv the 60bit immediate data

add,6
Store a return address
(PC + 2) in the stack; call
the subroutine program at
the location specified by
the 1O-bit immediate data
add,10
Store a return address
(PC + 1) in the stack; call the
subroutine program at one
of the limited, specialloC8tions

specified by the 10-bit immediate data addr X

PC-Stack

Return from Subroutine

PC~Stack

Skip unconditionally

Return from Subroutine; Skip
unconditionally

SKC

Skip if C-l

Skip ifC-l

0

1

0

1

1

0

1

0

1

1 +S

C -1

SKMBT bit

Skip if (HL) bit = 1 .

0

1

1

0

0

1

Bl

BO

1

I+S

(HL) bit-I

SKMBF bit

Skip if (HL) bit = 0
[bit = Bl~1

0

1

1

0

0

0

Bl

BO

1

1 +S

(HL) bit

SKABT Bit

Skip if Abi~ - 1
(bit = B3~.
Skip if A = Data 4
[Data 4 = 13~1
Skip if A = (HL)

1

SKAEI
Data 4
SKAEM

Skip If the .ingle bit of tho
location addressed by (H L).
denoted by B1BO is true. ,
Skip if the .ingle bit of the
location addressed by IH L).
denoted by BIBO i. fafse.
Skip if the .ingla bit of A
denoted by BIBO is true.
Skip if A aqual. tha 4-bit
Immediate data Data 4
Skip if A equals the contents
of RAM .dd,essad by HL.

lPL

A~Port

RT
RTS

SKIP

=0

0

1

1

1

0

Bl

BO

1

I+S

Abit- 1

0
0
0

0
1
1

1
1
0

1
0
1

1
1
13 12
1 ,. 1

1
11
1

1
10
1

2
1

2+S
1 +5

A=Oata4
A=(HL)

0

1

1

1

0

0

0

1

1

1

1/0

IL)

IPI

A-Port 1

OPL

Port (L)~A

OP3

Port 3 ~Al~

Input the contents of the port
.pecified by L to A
Input the contents of Port 1
loA
Output A to the port specified
by L
Output the lower 2 bits of A
,to Port 3

0

0

1

1

0

0

0

1

1

1

0

1

1

1·

0

0

1

0

1

1

0

1

1

1

0

0

1

1

1

1

0

0

0

0

0

0

0

1

1

CPU CONTROL
NOP

Perform no operation; consume
one machine cycle

0

SP7 520 ·1-80-CAT

1R4

NEe
NEe Microcomputers, Inl!.

}LPD8080AF
}L PD8080AF·2
}L PD8080AF·1

}LPD8080AF 8·BIT N·CHANNEL
MICROPROCESSOR FAMILY

DESCR I PTI ON

FEATURES

The MPD8080AF is a complete 8-bit parallel processor for use in general purpose
digital computer systems. It is fabricated on a single LSI chip using N-channel silicon
flate MOS process, which offers much higher performance than conventional microprocessors (1.28 MS minimum instruction cycle). A complete microcomputer syste(Tl
is formed when the MPD8080AF is interfaced with I/O ports (up to 256 input and 256
output ports) and any type or speed of semiconductor memory. It is available in a
40 pin ceramic or plastic package.
•

•

•
•
•
•
•
•
•
•

PIN CONFIGURATION

78 Powerful Instructions
Three Devices - Three Clock Frequencies
.MPD8080AF - 2.0 MHz
MPD8080AF-2 - 2.5 MHz
/lPD8080AF-l - 3.0 MHz
Direct Access to 64K Bytes of Memory with 16-Bit Program Counter
256 8-Bit I nput Ports and 256 8-Bit Output Ports
Double Length Operations Including Addition
Automatic Stack Memory Operation with 16-B it Stack Poi nter
TTL Compatible (Except Clocks)
Multi-byte I nterrupt Capability
. Fully Compatible with Industry Standard 8080A
Available in either Plastic or Ceramic Package

Al0
VSS
04
05
06
07
03
02
01
00
VBS
RESET
HOLO
INT
2

16

INTE

Phase Two '(input)



()

>-

~

::>

'"
O . 5 1 . . . - - - - ' - - - - _ ' - -_ _---l
+75
+50
+25

o

AMBIENT TEMPERATURE lOCI

Notes:

 VIH internal active pull-up resistors will
@
@

be switched onto 'the data bus,
Minus (-I designates current flow out of the device.
AI supply/ATa = -0.45%/"C.

Ta ~ 25°C, VCC = VDD= VSS = OV, VBB = -5V.

CAPACITANCE

LIMITS
PARAMETER

SYMllOL

MIN

TYP MAX' UNIT TEST CONDITIONS

Clock Capacitance

C1>

17

input Capacitance
Output Capacitance

CIN
COUT

6
10

25
10
20

pF
pF
pF

Ie = 1 MHz
Unmeasured Pins
Returned to VSS

JLPD,8080AF
PROCESSOR STATE
TR6.\NSITION DIAGRAM

Notes:

$

,

INTE F/F IS RESET IF INTERNAL INT F/F IS SET.
INTERNAL INT F/F IS RESET IF INTE F1F IS'RESET.
IF REQUIRED, T4. AND T5 ARE COMPLETED SIMULTANEOUSLY
WITH ENTERING HOLD STATE.
,

169

fL PD8080AF
Ta "" O°C to +70°C, VOO "" +12V ± 5%,
specified.

Vee"" +5V

± 5%,

Vas'" -5V ± 5%, Vss = OV, unless otherwise

LIMITS
PARAMETER
Clock Period

SYMBOL

MIN

MAX

UNIT

tcv@

0.48

TYP

2.0

~sec

50

nsec

Clock. Rise and Fall Time

t r , tf

0

<1>1 Pulse Width

t1

60

nsec

<1>2 Pulse Width

t2

220

nsec

Delay <1>1 to <1>2

t01

0

nsec

Delay $2 to <1>1

t02

70

nsec

Delay 411 to t:P2 Leading Edges

t03

80

Address Output Delay From tP~

tOA@

200

nsec

Data Output Delay From tj)2

too@

220

osec

TEST CONDITIONS

nsec

CL=100pF

Signal OutPl,jt Delay From CPl,

or <1>2 (SYNC, WR, WAIT,
HLOAi

toc @

OBIN Delay From q,2

tOF @

25

120

nsec

140

nsec

'OF

nsec

CL = 50 pF

Delay for Input Bus to Enter

CD

Input Mode

tOI

Data Setup Time During /f;l1 and
OBIN

tOS1

30

nsec

Data Setup Time to CP2 During
OBIN

tOS2

150

nsec

Data Hold Time From tP2 During

CD

2 (READY,
INT, HOLOi

tH

0

nsec

HOLD Setup Time to q,2

nsec

200

nsec

CL = 50 pF

tNT Setup Time During cJ>2

Delay to Float During Hold
(Address and Data Bus)

tFO

Address Stable Prior to WA

tAW@

Output Data Stable Prior to WR
Output Data Stable From WR

two

Address Stable from WR

120

nsec

®

osec

tow@

®

nsec

 'cy Min.

TYPICAL .:l OUTPUT DELAY VS .
.:l CAPACITANCE
+20

~
>

j

+10

w
()

>-

0

[

>-

::J

0
1

60

nsec

1>2 Pulse Width

t2

175

nsec

Delay ¢1 to 1>2

tDl

0

nsec

Delay <1>2 to <1>1

tD2

70

nsec

tD3

70

Delay

2

tDA@

175

nsec

Data Output Delay From cb2

tDD@

200

nsec

CL

= 100 pF

CL

= 50 pF

CL

= 50

CL

= 100 pF:

Signal Output Delay From ¢1,

or <1>2 (SYNC, WR, WAIT,
HLDAI

tDC@

OBIN Delay From 1>2

tDF@

25

120

nsec

140

nsec

tDF

nsec

Delay for Input Bus to Enter
Input Mode

tDI

CD

Data Setup Time During ¢1 and

DBIN

tDSl

20

nsec

Data Setup Time to rp2 During
DBIN

tDS2

130

nsec

Data Hold Time From 1>2 During
"DBIN

tDH

INTE Output Delay From ¢2

'IE @

READY Setup Time During rJ>2

tRS

90

nsec

HOLD Setup Time to ¢2

tHS

120

nsec

tNT Setup Time During (/)2
(tor all modes)

tiS

100

nsec

Hold Time from 4>2 (READY,
INT, HOLDI

tH

0

nsec

Delay to Float During Hold
(Address and Data Bus)

tFD

Address Stable Prior to WR

tAW@

(§)

nsee

Output Data Stable Prior to WR

tDW@

®

nsec

Output Data Stable From WR

tWD0

(J)
(J)

nsec

Add~ess Stable from

WR

CD

tWA 0

CD

nsec
200

120

nsec

pF

nsec

HLOA to Float Delay

tHF 0
tWF 0

®
®

nsec

WA to Float Delay
Address Hold Time nfter DB I N
during HLDA

tAH @

-20

nsec

nsec

Address,

Data

nsec

CL

= 50 pF:

WR,
HLDA, DBIN

Notes Continued:

@)

The following are relevant when interfacing the ,uPD80BOAF to devices having VIH

=;

3.3V.

a. Maximum output rise time from D.BV to 3.3V "" 100 ns at CL = SPEC.
b. Output delay when measured to 3.0V = SPEC +60 ns at CL =SPEC.
c. If CL " SPEC, add 0.6 ns/pF if CL > CSPEC, subtract 0.3 ns/pF (from modified delay I if

CL

< CSPEC.

171

JLPD8080AF
Ta = aOe to +70°C,
specified,

Von:.::: +12V

± 5%,

Vee = +5V

± 5%,

Vas

= -5V ± 5%,

Vss "" OV, unless otherwise

LIMITS
PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Clock Period

tCY@

Clock Rise and Fall Time

tr,tf

0.32

2.0

,usee

0

25

cpl Pulse Width

tI

50

{/>2 Pulse Width

t2

145

nsec

Delay 1 to <1>2

t01

0

nsee

Delay 2 to 1

t02

60

nsec

Delay cpl to ct>2 Leading Edges

t03

60

Address Output Delay From rp2

tOA@

150

nsec

Data Output Delay From 1>2

too@

180

nsec

Signal Output Delay ,From cPl,
0' 2 (SYNC, WR, WAIT,
HLOAl

toc@

OBIN Delay From 2

tOF @

TEST CONOITIONS

nsec
nsec

nsec

25

110

nsec

130

nsec

tOF

nsec

CL = 50 pF

CL = 50 pF

Delay for Input Bus to Enter

CD

Input Mode

tOI

Data Setup Time During ¢1 and
OBIN

tOS1

10

nsec

Data Setup Time to rp2 During
OBIN

tOS2

120

nsec

Data Hold Time From cf>2' During

CD

OBIN

tOH

INTE Output Delay Frqm 1>2

tlE@

READY Setup Time During rp2

'RS
tHS

HOLD Setup Time to cP2

CD
- 90

nsec
200

nsee

CL - 50 pF

nsec

120

nsec

I NT Setup Time During ¢2
(for all modes)

tiS

100

nsec

Hold Time from 2 (READY,
INT, HOLD)

tH

0

osec

Delay to Float During Hold
(Address and Data Bus)

tFO

Address Stable Prior to WR

tAW@

Output Data Stable Prior to WR
Output Data Stable From WR

tiNo 0

Address Stable from WR

tWA

120

tow@

0

®
®

nsec
nsec

nsec
nsec

(!
(!

nsec

H LOA to Float Delay

tHF0

8

nsec

WR to Float Delay

tWF 0

9

nsec

Address Hold Time after OBI N
during HLDA

tAH @

-20

nsec

Notes Continued:

®

~P 08080A F-2

~P08080AF-1

®

2 tev - t03 - tr<1>2 - 140
130
2tCY t03
t r¢2
110
2tCY t03 tr2
tow

Device
~P08080AF
~P08080AF-2

~PO"080AF-1

CL = 50 pF: WR,
HLOA,OBIN

tAW

Device
~P08080AF

CL = 50 pF: Address,
Data

'CY - '03 - ',2 -170
70
'CY t03 tr2
15u
'CY t03
t"1>2

Q)

If not HLOA, two = tWA = t03 + tr2 + 10 ns,lf HLOA, two = twA = tWF,

®
®

tHF = '03 + t,2 - 50 ns.
tWF = t03 + tr2 - 10 ns.

AC CHARACTERISTICS
MPD8080AF-'

TIMING WAVEFORMS

0

(Note: Timing measurements are made at the following reference voltages: CLOCK "1" = 8.0V,
"0" = 1.0V; INPUTS "1" = 3.3V, "0" = O.BV; OUTPUTS "1" = 2.0V, "0" = O.BV.)

: ~fnj'h fn frlfn frL1-'03_1

t 02 1 -

A,5 -Ao

°

WR_~=
_ _ ~~~~=ftH~~
-~-I~ ~~~
~ t=
~
~::'~

7 ,00

SYNC

OBIN

_____

READY _ _ _ _

~

______ _

~tHF

'" t

WAIT
HOLD

HlDA

- - II

tl~H--=:II__

..

~ j,,----i-

.-t"-:L_

_...J~I---.__

INTE

CD

Data in must be stable for this period during OBIN • T3. Both t051 and t052 must be satisfied.

®

Ready signal must be stable for this period during T2 or TWo (Must be externally synchronized.)

@

Hold signal must be stable for this period during,T2 or TW when entering hold mode, and during T3. T4. TS and TWH when in hold mode.

<-External synchronization is not required.)

@) I~terrupt signal must be stable during this period of the last clock cvcle of any

Instruction in order to be recognized in the following instruction.

(External synchronization is not required.J

......
(j

-

£~I~~t--~

INT

Notes:

I

.

-..

®
®

a.ov, ~'O" == 1.0V;, INPUTS "1"

1=

"'0

C

C»

i

This riming diagram shows timing relationships only; it does not represent any specific machine cycle.
Timing measurements are made at the following reference voltages: CLOCK "1" ==
OUTPUTS "1" = 2.0V, "0" = O.BV.

__

== 3.3V; "0" == O.8V;

~

"TI

J'PD8080AF
The instruction set includes arithmetic and logical operators with direct, register,
'indirect, and immediate addressing modes.
Move, load, and store instruction groups provide the ability to move either B or 16
bits of data between memory, the six working registers and the accumulator using
direct, register, indirect, and immediate addressing modes.
The ability to branch to different portions of the program is provided with direct,
conditional, or computed jumps. Also the ability to call and return from subroutines
is provided both conditionally and unconditionally. The RESTART (or single byte
call instruction) is useful for interrupt vector operation.
Conditional jumps, calls arid returns execute based ori the state of the four testable
flags (Sign, Zero, Parity and Carry). The state of each flag is determined by the result
of the last instruction executed that affected flags. (See Instruction Set Table.)
The Sign flag is set (High) if bit 7 of the result is a "1 "; otherwise it is reset (Low). The
Zero flag is set if the result is "0"; otherwise it is reset. The Parity flag is set if the
modulo 2 sum of the bits of the result is "0" (Even Parity); otherwise (Odd Parity) it
is reset. The Carry flag is set if the last instruction resulted in a carry or a borrow out
of the most significant bit (bit 7) of the result; otherwise it is reset.
In addition to the four testable flags, the IlPDBOBOAF has another flag (ACY) that is
not directly testable. It is used for multiple precision arithmetic operations with the
DAA instruction. The Auxiliary Carry flag is set if the last instruction resulted in a
carry or a borrow from bit 3 into bit 4; otherwise it is reset.
Double precision operators such as stack manipulation and double add instructions
extend both the arithmetic and interrupt handling capability of the IlPDBOBOAF.
The ability to increment and decrement memory, the six general registers and the
accumulator are provided as well as extended increment and decrement instructions to
operate on the register pairs and stack pointer. Further capability is provided by the
ability to rotate the accumulator left or right through or around the carry bit.
Input and output may be accomplished using memory addresses as I/O ports or the
directly addressed I/O provided for in the IlPDBOBOAF instruction set.
The special instruction group completes the IlPD8080AF instruction set: NOP, HALT
stop processor execution; DAA provides decimal arithmetic capability; STC sets the
carry flag; CMC complements it; CMA complements the contents of the accumulator;
and XCHG exchanges the contents of two 16-bit register pairs directly.

I NSTRUCTI ON SET

Data in the IlPD8080AF is stored as B-bit binary integers_ All data/instruction transfers to the system data bus are in the following format:

DATA AND INSTRUCTION
FORMATS

1071061051041031021011001
MSB

DATA WORD

LSB

Instructions are one, two, or three bytes long. Multiple byte instructions must be
stored in successive locations of program memory. The address of the first byte is used
as the address of the instruction.
One Byte Instructions

TYPICAL INSTRUCTIONS
Register to register, memory
reference, arithmetic or logical

Two Byte Instructions

1071 061 051 04 1031021 011DO I, OP CODE
/071 06/ 05/ 04/ 03 /02101 /DO / OPERAND

rotate, return, push, pop, enable,
or disable interrupt instructions
Immediate mode or I/O instructions

Three Byte Instructions

107/ 06/05104,'103 /02101 /DO / OP CODE ~~o~~i~s~l:u~i~i~~ct load and
1071 061 051 041 031021 011DO 1LOW ADDRESS OR OPERAND 1
1071 061 0511;>41 031 021 011DO 1HIGH ADDRESSOR OPERAND 2

174

ILPD8080AF
INSTRUCTION SET TABLE
INSTRUCTION CODE 2
MNEMONIC 1

DESCRIPTION

07

06 05 04 03 02 0,

INSTRUCTION CODE 2

Clock

DO

Cvcles3

MNEMONIC'

DESCRIPTION

MOVE
MOVd,>
MOV M,s
MOV d,M
MVI d,08
MVI M,DB

Move register to register

D

1

Move register to memory

Move memory to register

D
0

1
1

Move Immediate to register
Move Immediate 10 memory

0
0

OCR M

0

1
1

0

,

LXI 0,016

1

lOt

1

0

1D

LXI H,Ol6

d
d

pair DE

d

1

0

Load immediate register
pair HL
Load immediate Stack

Pomte,

0

S88 s

XRAS

CMPs

Subtract register from A
Subtract register from A
with borrow
AND reg'ster with A
ExciusiveOR Reglste,

0

0

0

0

PUSH H

1

0

0

0

1

PUSH PSW

o
1

0

o

0
1

1
0

0

D

1

1

0

o

S

ORA M
CMPM

ACI08

Add ,mmed,ate to A
Add Immediate to A With

0

0

0

0

1

0

0

0
1

1
0

1

ORI DB
CPI08

0

Add BCto HL
Add DE 10 HL

0

DAD H
0

I

o

Add Stack POlr'lter to HL
0

ARC
RAL
RAR

Rotate A left, MSB 10
carr\, la-bltl
Rotate A fight, LSB 10
carry 18-b'tl
Rotate A left through
carry 19-bill
Rotate A "ght through
carry (9-bnl

JNC AODR
JC ADDA
JPO AODA
JPE ADOA
JP ADOR
JM AOOA

Jump uncand,loonal
Jump on nat zero
Jump on zero
Jump Or'l na carry
Jump on carry
Jump on panty odd
Jump on parity even
Jump on positive
Jump on minus

1010110
1
0
1
1
0
1
1
0
0
1
1
0

IncremenlBC
lNX 0
INX H
INX SP

1

1

0

0

0

1

1
1

0
0

0
1

1
0

1

1

Increment HL
lrn;rementStack Pointer

Call unconditional
Call on not zero
Can on zero
Call 0" no carry
Callan carry
Call on parity odd
Call on parity even
Call on pOSitive

OCX 8
Decrement DE
OCX H
I)CX SP

0
1

1
0

1
1

o
o

0
0

o

1

:~C

:::~~~ ~~ ~:~arry
Return
Return
Return
Return
AelUrn

RP

on
on
on
on
on

carrv
parity odd
parity even
positIve
minus

0

1

10

11

0

0

1

0

1

1

0

1

0
0

1
1

0
0

1
1

11

1000001

10

0
1

0

1

0

0

0

1

1D

1

0
1

0
0

0
0

0
0

1
1

10

00001001
00011001
o 0 1 0 1 0

10
10

o

0

1

000000
o 0 0- 1 0 0
001000
o 0 1 1 0 0

1

Decrement' Stack POinter

0000101
o 0 0 1 1 0 1
o 0 1 0 1 0 1
o 0 1
1
0
1

STAX B
STAX D
LOAX B

Store A at
Store A al
Load A al
Load A at

ADDR In BC
AOOR In DE
AOOR on BC
ADDR on DE

0000010

00100

0

000010
0
0
1

o

DIRECT

o

a

0

0

1

LOA ADOR
SHLD ADDA
lHLO AODR

L'oad A direct
Slore HL direct
Load HL direct

XCHG

E",change DE and HL
register pairs
E1ichange tOP of stack

o

1
0
0
1
0
1
1
a 1
0100010

o

1

13
13
16

0

DOD
MOVE REGISTER "'R

o

0

0

0

1

o

0
0
1

0
1
0

0
0
0

1

o
1

0

o
1
1

1
0
0

1

1

10
10
10

0
1

0
0

0
1

0
0

1
1

1
1

SPHL

Hlta Stack Pointer
Hl !O Program Counter

1
1

1D

10

0
0

0
0

1

0

1

0
0
1
1

1
1
0
0

0
1
0

1

1

0
0

1
0

17
11/17

0

11/17
11/17
11/17

11117

1
1
1

0
0
0
0

1

0

1

0

11117
0

~ ~ ~ ~

0

Input
Output
Enable Interrupts
Oisablelnterrupts

OUT A

"

~

~ ~ ~

1

0
1
1

0

1
0
0
1

1
0
1

0
0

5~~ 1

0
0
0
0
0

5111
5111
5111
5/11
5111

0

~: ~ ~

0

1

0
0
0

1
0
0

1

0

1

1

0

1

1

0

1

0

0

1

1

D

1

0

0

1

1

CMA
STC

Complamant A
Set carry
Compleme"t carry
Decimal adjust A
No operation
Halt

DAA
NOP

11117
11/17

~ ~

1
0
I
1

o

RST A

o

o
0

18
1
1

5

INPUT/buTPUT

10
10

1-___---,
R.i._"m_ _ _ _ _ _ _R_ET_URN_ _ _ _ _ _ _ _ _ _ _ _--i

RC
RPO

0

1

000001

CMAOOR

Return on not lero

0

REGISTER 'ND'RECT
1

I----------------------------i
RET

1

DECREMENT REGISTER PA

MOV R, M; ADD M;
ADC M; SUB M;SB B M;
ANAM;XRAM;
ORAM;CMPM

PCR4

Q) H LR3(J}

7

PCR3 @

PCR3 @

8BW3

PCR3 @

PCR3 @

BBR3 @

PCR3 @

PCR3

BCW3
DEW3
BCR3
DER3

INR M and OCR M

PCR4

Q) HLR3

MVIM

PCR4

MVI A; ADI; ACI; SUI;
581; ANI; XRI; ORI; CPI

PCR4

<1J
CD

MOVM,R

,PCR4

PCR3

CD

OUT

PCR4

IN

PCR4

HLT

PCR4

CD
G>
G>

8BW3'

@

16

BBW3 ()

16

7
7
7

HLW3

PCR3 (Z) HLW3

Q) HLW3

PCR4

EI; 01 ADO R;
ADCR;SUBR;
SBB A; ANA R; XRA R;
ORA R; CMP R; RLC;
RRC; RAL; RAR;
OAA; CMA; STC;
CMC; NOP; XCHG

processor which is 100 percent software'
compatibl~ with the indust~y' standard SOSOA.lt has the ability' of increasing system
performance of the standard 8080A by operating at a higher speed. Using the
MPD8085Ain conjunction with its family of ICs allows the designer complete
flexibility with minimum chip count.

• Single Power Supply :+5 Volt
•
•

I nternal Clock Generation and
. System Control
I nternal Serial I n/Out Port.

•

Fully TTL Compatible

•

Internal 4-Level Interrupt Structure

•

Multiplexed Address/Data Bus for
I ncreased System Performance

•

Complete Family of Components for
Design Flexibility

•

Software Compatible with Standaru 8080A

•

Higher Throughput: MPD8085A - 3 MHz
MPD8085A - 2-5 MHz

•

Available in Either Plastic or Ceramic Package

PIN CONFIGURATION
Xl
X2
RO
SOD
SID
TRAP
RST 7.5
RSTS.5
RST 5.5
INTR
INTA
ADO
ADI
AD2
AD3
AD4
AD5
ADS
AD7

Vee
HOLD
HLDA
eLK (OUT)
RESET IN
READY

loiM

pPD
BOS5A

SI
RD
WR
ALE
So
A15
A14
A13
Al2
All
A1(i
Ag

VSS

AS

REV/l

179

jLPD8085A
The/lPD8085A contains six 8-bit data registers, an 8-bit accumulator, four testable
flag bits, and an 8-bit parallel binary arithmetic unit_ The IlPD8085A also provides
decimal arithmetic capability and it includes 16-bit arithmetic and immediate operators
which greatly simplify memory address calculations, and high speed arithmetic
operations_

FUNCTIONAL
DESCRIPTION

The IlPD8085A has a stack architecture wherein any portion of the external memory
can be used as a last in/first out (LI FO) stack to store/retrieve the contents of the
accumulator, the flags, or any of the data registers_
The IlPD8085A also contains a 16-bit stack pointer to control the addressing of this
external stack. One of the major advantages of the stack is that multiple level interrupts can easily be handled since complete system status can be saved when an interrupt occurs and then restored after the interrupt is complete. Another major advantage
is that almost unlimited subroutine nesting is possible.
The IlPD8085A was designed with speed and simplicity of the overall system in mind.
The multiplexed address/data bus increases available pins for advanced functions in the
processor and peripheral chips while providing increased system speed and less critical
timing functions. All signals to and from the IlPD8085A are fully TTL compatible.
The internal interrupt structure of the IlPD8085A features 4 levels of prioritized
interrupt with three levels internally maskable.
Communication on both the address lines and the data lines can be interlocked by using
the HOLD input. When the Hold Acknowledge (HLDA) signal is issued by the processor, its operation is suspended and the address, data and control lines are forced to be
in the FLOATING state. This permits other devices, such as direct memory access
channels (DMA), to be connected to the address and data busses.
The JlPD8085A features internal clock generation with status outputs available for
advanced read/write timing and memory/IO instruction indications. The clock may be
crystal controlled, RC controlled, or driven by an external signal.
On chip serial in/out port is available and controlled by the newly added R 1M and SIM
instructions.

BLOCK DIAGRAM
81T 1
£lIT 6

ACY AUXltlARY CARRY
ALWAYS "0

o
Bill
81T 0

-,
-,

180

--Vee

fLPD8085A
PIN IDENTIFICATION

PIN
NO.

. NAME

SYMBOL

1.2
RO

FUNCTION

loput!'

Crystal In

Crystal, Re. or external CIO!=K

Reset Out

Acknowledge that the processor
used as a system reset

1-bl! data out by the SI'M mstru<:tlon

IS

helng reset to be

SOD

Serial Out pata

SID

Serial In Data

l·bl! data Into ACe bit 7 by ,'he RIM instruction"

Trap

Trap Interrupt

Highest priority nonmaskable restart Interrupt

RST 7.'5
RST 6.5

Restart

Inpul
Pflorlty restart Interrupt Inputs. of which 7,5 ;s the
highest and 5,5 the lowest prlonty

Interrupts

RST 5.5

10

INTA

A gen'eral Interrupt mput which stops the PC from
incrementing. generates INTA. and samples the data
bus for a restart or call instruction

Interrupt

Request In
Interrupt

INTA

11

An output which indicates thaI Ihe processor has
responded to INTR'

Acknowledge

ADO - AD7

Low
Address/Data 8us

Multiplexed low address and data bus

20

VSS

Ground

Ground Reference

21·28

AS - A15

High Address Bus

Nonmultlplexed high 8-blts of the address' bus

29.33

SO. S,

Status Outputs

Outputs which indicate data bus status
Read. Fetch

30

ALE

Address Latch
Enable OUI

A Signal which indicates that the lower 8·blts of
address are valid on the AD lines

12-19

Halt: WI lIe.

31,32

WR.RD

Wrtte/Read
Strobes Out

Signals out which are used as Wille and read,strobes
for memory and I fa deVices

34

10 ' M

I/O or Memory

A Signal dut which indicates whether RD or WR
strobes are for If0 or memory deVices

Indicator

35

Ready

Ready ",nput

An Input which IS used to Increase the data and
address bus access time!; '(can be used for slow

36

Reset In

Reset Input

An mput which IS used to start Ihe processor activity
at ad{'jress O. resetting IE and HLDA flip-flops

memoryf

ABSOLUTE MAXIMUM
RATINGS*

37

eLK

38.39

HLDA,

40

Vee

HOLD

Clock Out

System Clqck Output

Hold Acknowledge
Out <.lnd Hold
Inpu! Request

Used 10 request and Indicate that the processor should
relinquish the bus for DMA actlVI!y, When'hold IS
acknowledged, RD, WR, 101M, Address and Data
busses are all 3-stated,

5V Supply

Power Supply Input

....... O°C to +70'C
-65"C to +150"C
-40°C to +12SoC
-0.3 to +7 Volts
-0.3 to +7 Volts
-0.3 to +7 Volts
1.5W

Operating Temperature,
Storage Temperature (Ceramic Package), .
(Plastic Packagel ..
All Output Voltages. . . .
. ........ .
All Input Voltages.
Supply Voltage VCC . . . . . . . . . . . . . . .
Power Dissipation " , , . , , , , . , . , .... , ,

II

COMMENT Stress above those listed under "Absolute MaXimum Ratings" may cause permanent
damage to the deVice, ThiS IS a stress rating only and functional operation of the deVice at these or
any other conditions above tho:ie Indicated In the operational sectIOns of thiS specification IS not
Implied. Exposure to absolute maximum ratl,ng conditions for,extended peflods may affect deVice
reliability.

-Ta -=25C

DC CHARACTER ISTics

Ta

~

0 CIa +70 e. Vce

0

+5V' '5% VSS

0

GND. unless olh"w"e spe"',ed
LIMITS

PARAMETER

SYMBOL

Input Low Voltage

V,L

Input High Voltage

V,H

Output Low Voltage

VOL

Output High Voltage

VOH

Power Supply Current lVCCf

lee IAV)

MIN
VSS

TVP
0.5

2.0

MAX

UNIT

VSS + 0.8

V

·VCC+O.5

V

045

V

IOL

V

IOH '"

2.4

170

CD
CD

I nput Leakage

',L

'10

Output Leakage

ILD

;10

Input Low Level, Reset

VILR

-0.5.

+0.8

Input High Level, Reset

VIHR

2.4

VCC + '0,5

HysteresIs. Reset

VHV

0.25

Note:

G)

TEST
CONDITIONS

mA

2 mA on all outputs

400'.,

CD

tCY mill

.A

V,N . Vee'

.A

O.45V '" VOUT"' Vee

V
V
V

Minus I -) deSignates current flow out of the deVice,

181

jiP-08085A
T a = OoC to

+ 70°C; Vee = 5V

± 5%; VSS =

ov

AC C.H.A.RACTERISTICS
LIMITS

PARAM~TER

SYMBOL

PPD8085A
MIN
MAX
',320 .

elK Cycle Period

TCVC

elK Low Time

tl

. 80-

elK,High Time

110

ALE Width

t2
tr.tt
tAL
tlA
tll

ALE Low During elK High

tLCK

eL:.K Rise and Fall Time
Address Valid Before Trailing Edge of ALE
AddressHold Time After ALE

Training Edge of ALE to Lea'ding Edge of
Control

,tLC

Address Float After Leading Edge of
READ (INTAI

tAFR

Valid Address to Valid Data In

tAD
tRO

R'EAD

(or INTAI to Valid Data

2000

120

pPD8oi16A-2
MIN
MAX
200
40·
70

30

30

TCVC '" 320 ns

...

Output Voltages
VL "-0.8 'Volts

60

,,yH .. 2.0 Volts

575
300
150

90

tCA
"tow

120
420
100
400
50

60
230
60

two
tcc
tCl

READY Valid from Address Valid
READY Setup Time to leading Edge of CLK
AEADY Hold Time
HlOA Valid to Training Edge of ClK
Bus Float After HlOA
HlOA to Bus Enable
ALE to Valid Data In
Control Training Edge to Leading Edge of
Next Control

tAAY
tAYS
tAYH

Address Valid to leading Edge of Control
HOLD Setup Time to Training Edge of ClK
HOLD Hold Time
INTR Setup Time to leading Edge of ClK
IM1, T1 only). Also AST and TRAP
INTR Hold Time
Falling to ClK Aising
X1 Falling to ClK Falling

tHACK
tHABF
tHA8E
tlOA
tRV

350

Input Voltages

150

VL '" 0,8 Volts

VH "1,6 Volts at

tRDH
tAAE

Note:

~ONDITIONS

'CL=150pF

aD
50

100
130.

Data Hold Time After READ (lNTAI

x,

UNIT

2000

50
50 .

100
140

Training Edge of REAl') to Ae-Enabling
of Address

Address 1AS-A1S) Valid After Control 5"DC

-{>llf>I r·
.,.

In

''----TI

470

+5V

Clock

X~i

----~~~--.l-J_==__.~
VV
,

, H'q"U'1 10 memory
Movp m~r"u'y to 'eq"TE"
Mnv~ ,mrnpd'dle 10 'P,!,,'e,
Mow Immecjodre tn fTjPm<;'Y

d
1

d
I

,

d

In,.rt'nwnl
Ir"rpm~rl1

o
o

mem,,,,,

Derremp,"memwy

LXI H,01'(;

LOdll,rnmed"u" 'eq"IP'
p.m HL
lo.,(j ,mme,j'dtP S,,,,.k

p,",
LX15P,016

,

reql\l~'

Dpnf'menl reQ'~"'1

L,,,,d ,m,,'ed'dIP
lOdd "",neoi'dle

0

0

I---------------------~-----_i

OCR ,I
INH M

,,~q"I'"

LX) B.016
LXI D,Ol6

p.", Be
o

U

,

"
0
0

0

,

o

0

'I,~"I"I

DE

o

0

o

0

o

Add '€'l,\!er 10 A

1

("''''V
5,,111',U;1

r~4',ler

Irom A

S"I"''''I re4"'l'r trom A

()

0

"o

"

wtlh bort()w
AND

reqtSt~'

E~.-ll"'V€

OR

0

0

()

0

0

0

0

0

0

0

o

0

0

a

REGISTER TO ACCUMULATOR
0

0

Add 'PQ'''P' In A woIh

SUB,
SBB,

0

0

PUSH

o
AlU

o

,

w,th A

PUSH PSW

Pu~h

o

POP 8

Pnp '~!l""" I),'"

o

POPl)

A ,1".1 IiI,'ck

,
U

0

Be

oil

1

Rt'q.~I~'

0

OR ,eq,ste, W>1h A
CO'''P,It~

'eq,"p.t wtth A

o
MEMORY TO ACCUMULA101:t

ArJrlmemo,y I{)A
A.jd ml'mo.y 10 A w,lh
SUB M

saB M

1

0

0

0

0

,

0

o

()

o

(J

0

0

o

0

Add Be I" Ht

o

"

1
0

()

o

0

0

U

0

1

INCH~MENI

c.'R

0

0

OOUSI E ADD

,

SuI",,,. I mpmo,y "om A
SUlll'dC' memo,y I,om A

0

,

REGISTER PAIR

-.,'fY', '~ .',

Comp.ltl' m"mo,v w"h A

1----------:--:-'Mc:Mc:'c:U-:'A-:-TE-:,c:O-:A-cc-:'-:;M:-U-,.-'''OH---------i :~~ ~I'
ADI08

Alid ,mmed,.,,,· 10 A
Add ,mmpd ... ,p ,,, A WHI.

SUIOH

SUbl •. "l ,mmpd'.,ll' t",m A
5ul)".1<'1 'mmpd'dIH I,om A

ANI DB

AND ,mmed'd!p Wllh A

ORI DH

OR .mme,h;"e ",'!h A
C,,'np,ltl' ,mme,h,tle

o

St"'~

CPI08

o

0

0

DECREMENT REGISTER PAIR

o
o

0
0

Q

o

0

u
o

o

A .. 1 AllUR ", Be

StoJp A ,J' AlJOR", UE:

""!,, A

Lo,,,1 A, ,., Al)UH ,n !:Ie
It, DE

0

o

CJ

0
0

,

0

1

0

0

ROTATl
H'''dle A letl, M58 t"

,

,

HOI"'!' A "qhl, LSB '"
,-""vla·I"I)
Rnl"'e AII'll I",ou'lh
("trV t9·1)l11

o

SH~

0 AIJDH
I HlOA[)Dfl

0

Rrl'dlf A ""illlh"''''II,

<,,"'y 19 h,'1

l~ch.",,1P

JMP AllOR

Ju,np Urt<"o"(j,!,n,, .. •

JNC ADDR
JCADDR

Jump"" ""lIP'"
Jumf,) on lH'"
Jump un nO <.." 'y
Jumf,)onl,"'y

~PO AQDR
JPf AODR

JM AODR

Jump "" pd"t~ ,,(J(j
Jump on p,,, ,ty t'yen
Jump 011 P()\"'Ye
J"mp on m,,,OJ'

W
I'll)

f,t

o

0

I
0

0
0

,

,
I
\

0

'''P "I ,I."

/'10

Inpul

,

Oulpu,

,

{)

0

U

,

I

()

0

') 18

o

0

,"

C"ll0r\l"",y
ePE ADOH

He
RPO

C"II On n.""v o'id
C.,II 0" P""'v Hv~n

1RR

,
o

0

C.,llo"m'(1u\

o

0

CJ

CJ

1

1
1
0

i-l"'U'''''"Il''',,,,V
i-lPlu"'(jI1',"'y

Hl'llHn 0" P,""Y ",Id
i-l .. ,u,

"'
"M

"o

(;.011 ",. P"''''y,'

T1 o~

0

0

0
0
0
0
0

0
0
0
0

1

0
0

0

a

SI'I

Im~"UpT

M.",

()

II

()

()

o

U

()

(I

,

u

0

0

HSl A

9'18

MISCE:LlANEOUS

\)18

COmplf'1!Wn' A

9:18
9,18
9118
9'18

SC'C'"try

6'12
6112
6112
6112
6112

6'12
611]

o

0

C"",plernt"" (,,,ty
O"",m,,! .,dIU" A
No npP'.l"O"

"

o
o

,

0
0

0

c;

,

"

00000000

0008

\

p.Il,ty "",.,.

RP.I"'" on D"""YF

,
CJ

1
0

,
o

0

U",II,I" '"1"1'''~''
H",ld IFI""'''I)I M,l>'

18

,

En,,!,I .. "'I<-',,up',

/'10

Cd: ""<'0"011'0",,1

CZ AODR

,

o

I" P'()4t,.m C,,""',·,

110
/'I()

1
1

511\1
CALL ADOR

,

~

."d Ht
Hl 10 51,,, ~ PD'"''''

0

6'12

110
d
PSW

"

,ll'sT"1 .. !,o"

'e9'~lf'

5tatu~

Wo,d

M~rl"HV

001C

0\00

01lE

111 A

31wo po",!JI,,"y~l~ 1'1Tl,,~ 17 10\ '''d'~,t1~
"'~t!UCI'Or\ Cy(I~~ dp!)t·"d~"1

fl'''l~

03
4.

II.Iq .III~, I,.,j
II"!;",,, "ffc(tt'ci

o

1t"y"""1

1

lia'l",1

on

,",PD8085A

INSTRUCTION CYCLE
TIMES

One to five machine cycles (Ml - M5) are required to execute an instruction. Each
machine cycle involves the transfer of an. instruction or data byte into the processor or
a transfer .of a data byte out bf the processor (the sole exception being the doubLe add
instruction). The first one, two or three machine cycles obtain the instruction from the
memory or an interrupting I/O controller. The remaining cycles are used to execute the
instruction. Each machine ·cycle requires from three to five clock times (Tl - T5).
Machine cycles and clock states used for. each type of instruction are shown below.
INSTRUCTION
TYPE

MACHINE CYCLES EXECUTED
MIN/MAX

ALU R
CMC
CMA
DAA
DCR R
. DI
EI
INR R
MOVR, R
NOP
ROTATE
RIM
SIM
STC
XCHG
HLT
DCX
INX
PCHL
RET CONDo
SPHL
ALU I
ALU M
JNC
LDAX
MVI
MOV M, R
MOV R, M
STAX
CALL CONDo
DAD
DCR M
IN
INR M
JMP
LOAD PAIR
MVIM
OUT
POP
RET
PUSH
RST
LDA
STA
LHLD
SHLD
XTHL
CALL

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1/3
1
2
2
2/3
2
2
2
2
2
2/5
3
3

3
3
3
3

3
3
3
3
3
3

4
4
5
5
5
5

CLOCK STATUS
MIN/MAX

4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
5
6
6
6
6/12
6

7
7
7/10

7
7
7
7

7
9/18
10
10
10
10
10
10
10
10
10
10
12
12
13
13
16
16
16
18

189

Jl.PD8085A
PACKAGE OUTLINE
/-IPD8085AC/D

Plastic
ITEM

MILLIMETERS

A

51.5 MAX

B
C

1.62

0.064

2.54.± 0.1

0.10 ± 0.004

0

0.5 ± 0.1

0.019 ± 0.004

E
F

H

1

e~r

48.26
1.2 MIN

1.9
0.047 MIN

G

2.54 MIN

0.10 MIN

H

0.5 MIN

0.019 MIN

I

5.22 MAX

0.206 MAX

J

5.72 MAX

0.22SMAX

K

15.24

L

13.2

M

0.25

0.600
0.520
+ 0.1

0.05

A

I-

INCHES
2.028 MAX

G

0.010

+ 0.004

0.002

-E~j~
0_10°

F
E

Ceramic
ITEM

MILLIMETERS

INCHES

A
B
C
0
E

51.5 MAX.
1.62 MAX.
2.54 ± 0.1
0.5 ± 0.1
4B.26 ± 0.1
1.02 MIN.
3.2 MIN.
1.0MIN.
3.5 MAX.
4.5 MAX.
15.24 TYP.
14.93 TYP.
0.25 ± 0.05

2.03 MAX.
0.06 MAX.
0.1 ± 0.004
0.02 ± 0.004
1.9 ± 0.004
0.04 MIN.
0.13MIN.
0.04 MIN.
0.14 MAX.
0.18 MAX.
0.6 TYP.
0.59 TYP.
0.01 ± 0.0019

F
G
H

I
J
K

L
M

.. nn

pPD8085A
IlPD8085A FAMILY MINIMUM
SYSTEM CONFIGURATION

A minimum computer system consisting of a processor, ROM, RAM, and
I/O can be built v.rith only 3-40 pin packs. This system is shciwn below with
its address, data,control busses and I/O ,ports.
'

Vcc

rl

INTERRUPTS

'l l

I

f

RST 75 RST 6.5 RST 5.5 TRAP

5

RESET IN

~

t tt

SID SOD SI SO

XI
~PDS085A

~

PROCESSOR

I-

'III II i'

0

w

111

0'("
l:t >


PORTB

I

I-

X2
ADO - - - - --AD7 AS - - - - --AI5

ADo
ADI

-'

PORTC

PORTA

r--

1:Ii",

ef ;JI~I~~~

1J.

TIMER
OUT

,,-

AD2
AD3

I- DATA

AD4
AD5
AD6
AD7

As
Ag
Al0
All

r- ADR

A12
A13
A14
A15
ALE

RD
ViR
10/11:1
ROY

t- CON

elK
RESET
HOLD
HlDA
INTR
INTA

~1~:f3 ~ ~I!I;I~
a:Ua::S!

FEATURES OF

ALE ADO - - - - - AD7

~PD80B5A

~PDB355

MINIMUM ,SYSTEM
2K - BYTE ROM
256 ~ BYTE RAM
1 - INTERVAL TIMER
4 - B·BIT 1/0 PORTS
1 - 6·BIT I/O-llTATUS
4 -'INTERRUPT lEVELS

~PDB755A

ROM·I/O
PR9M.I/O 2K X 8

PAo - - - - - - - - PA7

PBg-- - - ----PB7

Jill I

11111111

I

PORTA

II

i

PORTB

SP8085A-1 0-79-CA T
1Q1

II

NOlES

.

,NEe

NEe Microcomputers, Inc.

JLPD7801

~~~[~~~~ill~W
SINGLE CHIP 8-BIT MICROCOMPUTER
DESC R I PTION

The NEC IlPD7801 is an advanced 8-bit general purpose single chip microcomputer
using N-channel silicon gate MOS technology. All the basic functional blocks4096 x 8 of ROM program memory, 128 x 8 of RAM data memory, 8-bit ALU, 48 I/O
lines, 12-bit timer and clock generator are provided on·chip to enhance single chip
applications. The IlPD7801 is fully compatible with the industry standard 8080A's bus
structure. Thus, expanded system operation can be easi Iy implemented using any of
the 8080A peripherals. Total memory space can be increased to 65K bytes with
industry stalJdard ROM and RAM products.
The powerful 125 instruction set coupled with 4K bytes of ROM program memory
and 128 bytes of RAM data memory greatly extends the range of single chip microcomputer applications. Five level vectored interrupt capability plus a 2 Il.S cycle time
enables the IlPD780l to compete with multi-chip microprocessor systems with the
advantage that most of the support functions are on-chip.

F EATU RES

• NMOS Silicon Gate Technology Requiring a Single +5V Supply
•
•
•
•
•
•
•
•
•
•
•
•
•

2 IlS Cycle Time
4096 x 8 ROM Program Memory
128 x 8 RAM Data .Memory
48 I/O Lines
Serial I/O Lines
Powerful. 125 Instruction Set.
12-Bit Timer
Vectored Interrupts -'- 3 Externa.I;2 Internal
Internal Clock Generator
Fully Bus Compatibie with 8080A
Expandable using 8080A,Periphtirals and Standard Memories
Direct Addressing Capability to 65K Bytes·
Available in 64 Pin Plastic Quad-ln-LinePackage

PIN CONFIGURATION
vcc (+5V)

PE15 .
"'OUT
DB7
DBS
DBS
DB4
DB3

PE'4
PE'3
PE12
PE11
PE10
PEg

D~

Pq

DB1
DBO
INT2
INTI
INTO
WAIT

PE7
PES
PE5
PE4
PE3
PE2
PE,
PEo

MI

WJ!i

~

PC7
PCs
PCs
PC4
PC3
PC2
PC,
PCO
~

SI
So
~

IlPD
7801

Ph

PBS
PB5
PB4
PB3
PB2
PBl
PBO
PA7
PA6
PAS

pA4
PA3

X2

PA2

VSS(OV)

_t..=:_ _ _ _...::..::.--PAO

x,

II

PA,

193

jJ.PD7801
PIN DESCRIPTION

PIN
NO.

SYMBOL

FUNCTION

2

 INTT >
INTI> INT2 > INTS, where INTT and INTS are internal interrupts.
Refer to later sections.

14

WAIT

WAIT is the wait request input. The J.!PD7801 can be wait-stated if
memories with slower access times are used by applying an active low
signal to this input.

15

Ml

Ml is an output pin signifying the first machine cycle of each instruction. It will go to an active high level during the fetch cycle of the first
opcode from Tl to T3. Ml is also useful for single step or break
operations.

16

WR

WR is an active low signal generated by the J.!PD7801 to initiate data
flow 'from the processor to the peripheral, memory, or I/O device.

17

RD

R D is an active low signal generated by the J.!PD7801 to initiate data
flow to the processor from the peripheral, memory or I/O device.

PCO·7

This isan 8-bit I/O port. Tile upper 6 bits (PC2-71 can be programmed
to provide various control capabilities using the MODE register. A more
detailed description of this port's operation will follow in a later
section.

26

SCK

SCK is the Serial In/Serial Out clock for the serial data port.

27

SI

SI is the Serial Input Port. Data is loaded through this port into the
processor, Serial Register with the rising edge of SCK: The bit order for
input data is from MSB to LSB.

28

SO

SO is the Serial Output Port. Serial output data is strobed from this
port by the falling edge of SCK. The bit order for output data is from
MSB to LSB.

29

RESET

RESET is.an active low input for processor initialization. See subsequent sections for detailed description of the initialization process.

X2,Xl

These are the crystal inputs for the internal clock generator. X 1 can be
used as an external clock input. Refer to following sections for
suggested clock input circuits.

18-25

30,31

VSS(OVI

The processor's ground potential.

33-40

PAO-7

Port A is an 8-1>it output port. Data at this port remains latched .until
written over by new data. Reference subsequent sections for further
explanation.

41·48

PBO-7

Port B is an 8-1>it I/O port. Both input and output data are latched
here. Each I/O line of Port B can be programmed through the MODE B
Register to either an input or an output. A more detailed description
fallows later.

49-63

PEO·15

Port E is a 16-bit address bus/output port. Three different programmable modes are selectable under software control. A more detailed
descriptio.n follows later.

VCC

Processor's +5V supply input.

32

64

194

p.PD7801
BLOCK DIAGRAM

1NTOo----r----,
SP

1NTlo----I

'v

INT
CONTROL

1NT2o----I

I-~B-.~f-',--'::'0--11 ,MAIN
1-7.--t---7----11 G.R.
1---"-'--+"--"--1 I

AL T

I---"-"--+-'-~-II

G.R.

PC71 PCeI
HOLD HLDA

FUNCTIONAL DESCRIPTION

DATA
MErt/lORY
(128 BYTE)

PROGRAM'
MEMORY
14K BYTE)

RD

PAO-7 (Port AI
Port A is an 8-bit latched output port. Data can be readily transferred between the
accumulator and the output latch buffers. The contents of the output latche.s can be
modified using ,/\rithmetic and Logic instructions. Data remains latched at Port A
unless acted on by another Port A instruction OJ a RESET is issued.
PBO-7 (PortBI
Port B is an 8-t;lit I/O port. Data is' latched at Port B in both the Input or Output
modes. Each bit of Port B can be independently set to either Input or Output modes.
The Mode B register programs the individual lines of Port B to be either an Input
(Mode Bn = 11 or ,an Output (Mode Bn = 01.
PCO-7 (Port CI
Port C is an 8-bit I/O port. The Mode C register is used to program the upper 6 bits
of Port C to provide controlfuhctions or to set the I/O structure per the following
table.

--

MODE

en- 0

MODE

en" 1

!'Co

OUTPUT

INPUT

PC,

OUTPUT

INPUT

PC2

S'aINPUT

INPUT

PC,

SAK OUTPUT

OUTPUT

I'C4

TOOUTPur

OUTPUT

Pes

JO/MOUTPUT

OUTPUT

Pes

. HI:.OA OUTPUT

I'C7

HOLD INPUT

OUTPUT· '
INPUT

DBO-7 (Data Busl
DBO-7 form the 8-bit bidirectional data bus. Data moves between external memory or
I/O and the accumulator are handled through this bus.

195

II

p.PO·7801
PEO-15 (Port E)
Port E is a 16-bit address bus/output port. It can be set to one of three operating
modes using the PER, PEN, or PEX instructions.
•

16-Bit Address Bus - the PER instruction sets this mode for use with external I/O
or memory expansion (up to 60K bytes, externally).
• 4-Bit Output Port/12-Bit Address Bus - the PEN instruction sets this mode which
allows for memory expansion of up toAK bytes, externally, pius the transfer of
4-bit nibbles.
• 16-Bit Output Port - the PEX instruction sets Port E to a 16-bit output .port. The
contents of the Band C registers appear on PES-1S and PEO-l, respectively.
M1 (Machine Cycle 1)
Ml is an output pin used to signal external devices at the first machine cycle of each
instruction. It can also be used in single step or breakpoint operation.
WAIT (Wait Request)
WAIT (active-low) is used to extend the read/write timing for systems using slow speed
external memories. A logic 0 detected at the end of T2 forces the IlPD7S01 to a wait
state until WAIT goes high.
INTO, INT" INT2 (Interrupt Request)
INTO-2 are the interrupt request lines. Their priorities are as follows: INTO> INTT >
INTl > INT2 > INTS, where INTT and INTS are internal interrupts. In order to minimize any possible noise interference, an internal sampling technique is used requiring
an external interrupt be held for 41ls ~o be recognized.
•
•
•
•

INTO is an active-high level-sensitive interrupt line.
INTl is a rising-edge-sensitive interrupt line.
INT2 is a programmable edge-sensitive interrupt line.
If the ES-bit in the MASK register is set to ES = 1, then INT2 is rising-edge-sensitive.
If ES = 0, INT2 is falling-edge-sensitive.

SCK (Serial Clock)
SCK is the serial input/output clock for the serial data port. The rising edge of SCK
loads data from the Serial Input Port (SI) into the Serial Register (S/P). The falling edge
of SCK loads data from the Serial Register to the Serial Output Port (SO). The bit
order of data flow into and out of the Serial Ports is MSB first.
RESET (Reset)
An active low-signal on this input for more t!1an 41ls forces the IlPD7S01 into a Reset
condition. RESET affeCts the following internal functions:
•
•
•
•
•
•
•
•
•
•
•

The Interrupt Enable Flags are reset, and Interrupts are inhibited.
The Interrupt Request Flag is reset.
The HALT flipflop is reset, and the Halt-state is released.
The contents of the MODE B register are set to FFH, and Port B becomes an input
port.
The contents of the MODE C register are set to FFH. Port C becomes an I/O port
and output lines go low.
All Flags are reset to O.
The. internal COUNT register for timer operation.is set to FFFH and the timer F/F
is reset.
The ACK FIF is set.
The HLDA F/F is reset.
The contents of the Program Counter are set to OOOOH.
The Address Bus (PEO-1SI. Data Bus (DBO-7), RD, and WRgo toa high impedance
state.

Once the RESET input goes high, the program is started at location OOOOH.

FUNCTIONAL
DESCRIPTION (CaNT.)

f'PD7801
REGISTE.RS

The IJPD7a01 contains sixteen 8-bit registers and two 16-bit registers

o

15
.PC

I

SP
70

0

I

V

I

7
A

B

C

D

E

I
Main

L

I

V'

A'

I

B'

C'

D'

.E'

H'

L'

H

I

Alternate

General Purpose Registers (B, C, D, E, H, L)
There are two sets of general purpose registers (Main: B, C, D, E, H, L: Alternate: B',
C', D', E', H', L'). They can function as auxiliary registers to the accumulator or in
pairs as data pointers (BC, DE, HL, B'C', D'E", H'L'). Auto Increment and Decrement
addressing mode capabilities extend the uses for the DE, H L, D'E', and H'L' registerpairs. The contents of the BC, DE, and HL register-pairs can be exchanged with their
Alternate Register counterparts using the EXX instruction.
Vector Register (V)
When defining a scratch pad area in the memory space, the upper 8-bit memory
address is defined in the V-register and the lower 8-bits is defined by the immediate
data of an instruction. Also the scratch pad indicated by the V-register can be used as
256 x 8-bit working registers for storing software flags, parameters and counters.
Accumulator (A)
All data transfers between the IJPD7801 and external memory or I/O are done through
the accumulator. The contents of the Accumulator and Vector Registers can be
exchanged with their Alternate Registers using the EX instruction.
Program Counter (PC)
The PC is a 16-bit register containing the address of the next instruction to be fetched.
Under normal program flow, the PC is automatically incremented. However, in the
case of a branch instruction, the PC contents are from another register or an instruction's immediate data. A reset sets the PC to OOOOH.
Stack Pointer (SP)
The stack pointer is a 16-bit register used to maintain the top of the stack area (last-infirst-out). The contents of the SP are decremented during a CALL or PUSH instruction
or if an interrupt occurs. The SP is incremented during a RETU RN or POP instruction.

TIME R

The IJPD7801 contains a 12-bit programmable interval timer. It is composed of
TIMER REG 0 (8-bitl, TIMER REG 1 (4-bitl, PRESCALER, and 12-bit DOWN
COUNTER and is capable qf counting from 4 IJs to 16 ms with a 4 IJs increment.

197

II
:

h'PD1801
The IlPD7801 can directly address up to 64K bytes of memory. Except for the on-chip
ROM (0-4095) and .RAM (65,408-65,535), any memory location can be used as
either ROM or RAM. The following memory map defines the 0-64K byte memory
space for the IlPD7801 showing that the Reset Start Address, Interrupt Start Address,
Call Tables, etc., are located in the internal ROM area.

r---:---,,-------'::-o

RESET

MEMORY

MEMORY-MAP

INTERNAL
ROM

4 t--"IN;.;.T",O_-i

1040951

:::+----+

8 t-..;;IN;.;.T"-'_-I

16

INT,

32

INIa

64

INTS

EXTERNAL
MEMORY

,

61,312 x B

:::::.+-----11INTERNAL
RAM

66.635 L.._ _...J

.-0

128
129

LOW ADOR }
HIGH ADOR

130
131

LOWADDR } •••
HIGH ADDR

264'

LOW ADOR }

265

HIGH ADDA

tilt

63

USER'S
AREA

I~------------A------------~

PACKAGE OUTLINE
IlPD7801B

~--------------E~----------~~~I

-M

F
ITEM

A

D

G

MILLIMETERS

41.8 MAX.
1.22

0.05

2.54

0.'

a.s±o.1

0.02:t 0.004

39.37

'.55

'.27

0.06

6.75

0.27

9.3

0.37

3.6

0.14

36.'

'.39

30.0

1.18

16.6
M

INCHES

'.65

O.25± 0.06

0.65
' 0.01

t

0.002

SP7801-12-79-7K-GN

198

NEe

NEe Microcomputers, Inc.

p.PD8021

SINGLE CHIP 8·BIT
MICROCOMPUTER
DESC R I PTI ON

FEATURES

The N EC pPD8021 is a stand alone 8-bit parallel microcomputer incorporating the
following features usually found in external peripherals. The pPD8Q21 contains:
1 K x 8 bits of mask ROM program memory, 64 x 8 bits of RAM data memory, 21
I/O lines, an 8-bit interval timer/event counter, and internal clock circuitry.

• 8-Bit Processor, ROM, RAM, I/O, Timer/Counter
• Single +5V Supply (+4.5V to +6.5V)
• NMOS Silicon Gate Technology
• 8.38 ps Instruction Cycle Time
• All Instructions 1 or 2 Cycles
• Instructions are Subset of pPD8048/8748/8035
• High Current Drive Capability - 2 I/O Pins
• Clock Generation Using Crystal or Single Inductor
• Zero-Cross Detection Capabil ity
• Expandable I/O Using p8243's
• Available in 28 Pin Plastic Package

PIN CONFIGURATION

vee

P22
P23
PROG

P21
P20

PO~

P17
P16

POl
P02

P15

P03

P14

P04
P0 5

P12

P06

P11

PQ7

P10
RESET

II

P13

ALE
T1

XTAL 2

VSS

XTAL1

Rev/1

199

JLP08021
The NEe pPD8021 is a single compona'nt, 8-bit, parallel microprocesso(usihg
N-channel silicon gate MOS technology. The self-contained 1 K x B-bit'ROM,
64 X 8-bit RAM, B-bit timer/counter, and clock circuitry allow the pPD8021 to
operate as a single-chip microcomputer in applications ranging from controllers to
arithmetic processors.

FUNCTIONAL DESCRIPTION

The instruction set, a subset of the pPD8048/8748/8035, is optimum for high-volume,
low cost applications where I/O flexibility and instruction set power are required. The
pPD8021 instruction set is comprised,mostly of single-byte instructions with no
instructions over two bytes.

BLOCK DIAGRAM

Operating Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OOC to +70°C
Storage Temperature (Ceramic Package) . . . . . . . . . . . . . . . . . . . -65°C to +150°C
(Plastic Package) . . . . . . . . . . . . . . . . . . . . -65°C to +125°C
Voltage on Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " -0_5 to +7 Volts . . _____
../'

WRITE OPERATION - DATA BUS BUFFER REGISTER

' - - - - - - - - SYSTEM
ADDRESS8US

WR

DATA BUS _ _.::O;;:AT~A.::C;;:;AN:.:C:;;H;;:AN.:;G;.:;.'_ _
(INPUT!

214

WR ITE CONTROL

1'"'_-.....;==;;:...-_=>[ :,--_...;;;DA.;;T.;;A,;;;CA.;;.N;.,;;C.;;.HA.;.N;;;;G;..'_ _

Jo'PD8041 /8741 A

PACKAGE OUTLINE
pPD8041C/D
pPD8741 ACID

(Plastic)
ITEM

MILLIMETERS

A

51.5 MAX

INCHES
2.028 MAX

B

1.62

0.064

C

2.54 ±0.1

0.10 ± 0.004

0.5 ± 0.1

0.019 ± 0.004

D
E

48.26

1.9

F
G

1.2MIN

0.047 MIN

2.54 MIN

0.10 MIN

H

0.5MIN

0.019 MIN

I

5.22 MAX

0.206 MAX

J

5.72 MAX

0.225 MAX

K

15.24

0.600

L

13.2

0.520

0.25

M

+ 0.1
- 0.05

+ 0.004
0.010 _ 0.002

~:28

J'~
G

..

"
M".

\--

0_100

F
f---------E-------~

Ceramic

ITEM

MILLIMETERS

INCHES

A

51.5 MAX.
1.62 MAX.
2.54± 0.1
0.5 ± 0.1
48.26 ± 0.1
1.02 MIN.
3.2 MIN.
1.0 MIN.
3.5 MAX.
4.5 MAX.
15.24 TYP.
14.93 TYP.
0.25 + 0.05

2.03 MAX.
0.06 MAX.
0.1 ± 0.004
0.02 + 0.004
1.9 ± 0.004
0.04 MIN.
0.13 MIN.
0.04 MIN.
0.14 MAX.
0.18 MAX.
0.6 TYP.
0.59 TYP.
0.01 + 0.0019

B

C
D
E
F

G
H
I
J
K

L
M

II

215

JLPD8041 18741 A
INSTRUCTION SET
INSTRUCTION CODE

MNEMONIC

F.UNCTlQN

DESCRIPTION

07

~

tAl + data

ADD A. ;: dlJta

(A)

ADD A, Ar

(A)' tAl t lAd
for r ~ 0 - 7

Add contents of designated register to
the Accumulator.

,Add Immedia,te the specified Data to the
Accumulator.

ADDA,@Rr

(AI"" (AI t (IRrH
for r" 0 1

Add Indirect the contents the data
memory location to the Accumulator.

(A)' (A) + Ie) t data

Add Immediate With cafrY the specified
data to the Accumulator.

ADOC A, Ar

(A)· (AI + Ie) t (Ar)

Add With carry the contents of the
designated register to the Accumulator

7

(AI .- (AI tie) + HRrH
for r = 0 1

Add Indirect With carry the contents oj
data memory location to the
Accumulator.

ANL A, "data

(A)· tAl AND data

Logical and specilled Immediate Data
With Accumulator.

ANL A, Rr

(A)

(AI AND tAr)
for r '" O· 7

Logical and contents oj deSignated
register With AccumulatOr.

ANLA,@Rr

(AI .- (AI AND ((Ad)
for r = 0
1

Logical and Indirect the contents.of data
memory With Accumulator.

CPL A

(A)

+-

NOT (A)

Complement the contents of the
Accumulatol

CLA A

(AI

+

0

CLEAR the contents 01 the Accumulator'

DA A

DEC A

04

FLAGS

03

02

01

DO

0

0

dS

dS

d4

d3

d2

d,

dO

0
d6

dS

d4

d3

d2

d,

dO

dS

d4

d3

d2

d,

dO

dS

d4

d3

d2

dl

1
dO

0

0

1
d6

dS

d4

0
d3

0
d2

dl

dO

b2
a,

b,
a6

bO
"5

84

a3

a2

a,

'0

a7

,
a6

1
as

a4

0'
a3
"2

a,

'0

a7

0'
a6
as

a4

0
a3

1
a2

a,

'0

a7

1
a6

as

a4

0
a3

a2

a,

'0

a'0
a7

a9
a6

aa
as

a4

a3

'
a2

a1

'0

d7

d7

0

ADflC A,@Rr

+--

Os

0

Acoe A. :: data

for r" 0

06

LAT R

A

1
d7

d6

o

0

0

DECIMAL ADJUST the contents of the
Accumulator.
(AI· tAl

1

DECREMENT by , the accumulators

INCA

(AI·

DALA, "data

(AI .- (AI OR data

Logical OR or speCIfied Immediate data
With Accumulator

CAL A, Ar

IAf· tAl OR (Rr)

Logical OR contents of deSignated
register With Accumulator.

for

(AI + 1

I ~

0

Increment by , the accumulator's

7

(AI· (AIDA ((Ar))
for r" 0 1

Logical OR Indirect the contents of data
memory location With Accumulator

RL A

(AN + 1)' (ANI

Rotate Accumulator left by '·blt Without
carry

RLe A

for N" 0 6
IAN + 11 +-- (ANI; N" 0

6

Rotate Accumulator left by I-bit through
carry

6

Rotate Accumulator fight bv '·blt
Without carry

1Ao1- leI
le)- IA71
RR A

IAN) -. (AN t 1), N ~ 0
~A7)'

~AO)

RRC A

iAN) -

~AN

~A71'

+ 1); N

~

0 - 6

~Cl

1
d6

0

ORLA,@Rr

tAOI - IA71

d7

Rotate Accumulator fight by '·b'l
through carry.

IC)' lAO)
Swap the 2 4·b,t nibbles in the
Accumulator.

SWAP A

(A4-7).' lAO - 31

XRL A," data

(AI·

XRl A, Ar

(AI" (AI XOA tAr!
fon=0-7

Logical XOR contents of deSignated
register With Accumulator.

XALA,@Rr

~A)' (AI XQR liAr))
for r" 0 - 1

Logical XOA Indirect the contents of data
memory locat.on With Accumulator

~Al

XOA data

Logical XDR specilled Immediate data
wlti1 Accumulator,

d7

1

BRANCH
DJNZ Ar, add,

JBb add.
JC add,

(Ar) ..... (Rr) - 1; r "0 1
If (Rr)". 0:
(PC 0 - 7) -- addr
(PC 0 - 71 0- addr if Bb " 1
(PCI ~ (PC) + 2 If Bb" 0

Decrement the specified register and

Jump to speCified address If
Accumulator billS set.

o

(PC 0 - 71 .... addr if C " 1
(PCI <- ~PC) t 2.fC" 0

Jump to specl"ed address If carry flag

JfO addr

(PC 0 - 71 .... adclr If FO " 1
(PCl --)(PC) t 2 If FO" 0

Jump to specified address " Flag FO IS
set.

JFl add,

,PC 0 - 1) <-- addr if F 1 " 1
(PC)
(PCl + 2 If F, '" 0

Jump to speCified address II Flag F 1 IS

JMP addr

(PC 8 - '01 <- addr 8 10
(PC 0 - 1) -- addr 0 - 7
(PC 111-- DBF

DIrect Jump to specified address WIthin
the 2K address block.

JMPP@A

(PCO-71...-UAII

Jump IndIrect to speCified address with
With address page,

JNC addr

IPC 0 - 7) - addr if C '" 0
(PCI - (PC) + 2 if C '" 1

Jump to specified addreu if carry flag is
low.

a7

as

8S

114

83

a2

81

ao

JNIBF addr

(PC 0 - 71 - addr if IBF '"
(PCI +- (PC) + 2 if tBF '" 1

Jump to specified addr8n if input buff.r
futl flag is low.

1
a7

1
86

0
as

a4

0
a3

1
a2

a1

ao

JOBF

(PC 0 - 7) .... addr if OBF '" 1 Jump to specified address if output
(PC)·- (PC) + 2 if OB'F "' 0
buffer lull flag is set.

1
a7

a6

0
as

a4

0
a3

1
Ilt2

a1

ao

0---

216

o

o

o

1

0

0

CYCLES

BYTES

C

AC

FO

Fl

IBF

QBF

JLPD8041/8741A

INSTRUCTION SET (CaNT.)
INSTRUCTION CODe
MNEMONIC

FUNCTION

01

(PC 0- 71 <-addr,' TO" 0
~PCJ ~- (PC) + 2 if TO ,. 1

Jump to specified address If Test 0 IS tow.

JNTl add,

(PC 0- 71 <- addr If Tl " 0
(PC) • (PC) + 2 if T1 "1

Jump to specified address jf Test 1 IS low

(PC 0- 7) <-addr,' A '" 0

Jump to speclfu;!d address If accumulator

JNZ add,

(PC) • - (PC) + 2 If A
JTF add,

=

0

(PC 0- 7) <-addr ,f TF" 1
(PC) • (PC) + 2 " TF '" 0

Jump to specified address jf Timer Flag

Issetto1.

JTOaddl

(PC 0- 7) -addr if TO" 1
(PC) .... (PC) + Zif TO"'O

Jump to specified address .f Test 0 is a J

JTl addr

(PCO 71 ..... addr if T1 " 1
(PC) ~ (PC) + 2 " T1 = 0

Jump to specified address

(PC 0 - 7) .... adw If A " 0
(PCI ,- (PCI + 2 If A I 0

Jump to specified address "
is O.

JZaddr

EN'

If

IS

'5
0
'5
0

'6

",
"

'6
0
'6
0
'6

"0

'6

D.

FLAGS

0,

DO

, "
, ",

'0
0
'0
0
'0
0
'0
0
'0
0
'0
0
'0

03

02

'5
0

,

'5

''..
',,.
',.
'.

'3
0

'2

'3

'2

'3

'2

"0

0

,

'3

'2

0

,

"
"
"

'3

'2

0
'3
0

'2

"

'3

'2

"

d3

d,

d,

dO

,

'5
0
'5
0

'6

'5

0
d,

d6

d5

d.

d,

d6

d5

d.

d3

d2

d,

dO

d,

d6

dS

d.

d3

d2

d,

dO

a 1.

Enable the External Interrupt Input

DIS I

,

"0

"
"
Accumulator
"
CQN1ROL

Test 1

Os

CYCLES

BYTES

C AC

FO

F'

,BF

OBF

N

BRANCH
jNTQ addr

Of;

'6

, ",

0

Disable the External Interrupt Input

SEL ABO

(BS) - 0

Select Bank 0 lIocatioll6 0 - 7) of Data
Memory.

SEL RB1

(BS) '-1

Select Bank 1 (iocatlom 24
Data Memory

MOV A, ::data

(AI ~ data

MOlle Immediate the speCified data Into
the AccumUlator.

MOV A, Ar

(AI <- (Arl,r'" 0- 7

Malle the contents of the deSignated
registers IOtotheAccumulator.

MOVA,@AT

(AI - HArll;r '" 0

MOVA, PSW

(A)

MOV Ar, #' data

(Ad - data, r '" 0 - 7

MOV Rr, A

(Ar) <- (A); r = 0

31) of

,

DATA MOVES

~

,

(PSW)

MOlle Indirect the contents of data
memory location IOto the Accumulator.
Move contents of the Program Status
Word Into the Accumulator.

,

Move Immediate the speCified data IOta
the designated register.

MOV@Rr,A

({Ar)}- (AI; r =0- 1

Move Indirect Accumulator Contents
Into data memory location.

MOV@ Rr, ;; data

((Ar)) <-data; r = 0 - 1

Move Immediate the speCified data Into
data memory.

MOV PSW, A

(PSW1<-(M

Move contents of Accumulator mto the
program status word.

MQVP A,@A

(PC 0- 7) <- (A)
(A) <- ((PC)!

Mo"e data Ifl the Current page IntO the
Accumulator.

MOVP3 A,@A

(PC 0- 7) ... (A)
(PCB-101--Oll
fA) .... ((PCH

Move Program data
AccumUlator.

XCH A, Ar

(A)~

Exchange the Accumulator and
deSignated register's contents.

XCH A,@Ar

(A) -;:f(Ar/I;

XCHD A,@Ar

(AO-3):'::;((Rrj'0-3));
r = 0

CPLC

IC) ..... NOT (e)

Complement Content of carry bit.

CPL FO

(FO)"" NOT (FO)

Complement Content of Flag FO

CPL F1

(FlI-NOT(F1)

Complement Content of Flag Fl

CLR C

IC) +-(

Clear content of carry bit to 0

CLA FO

(FOI ..... O

Clear content of Flag 0 to O.

CLR F1

(Ft) .... 0

Clear content of Flag. 1 to 0

(Ar);r = 0 - 7

T'"

,

0-1

, ,

Move Accumulator Contents mto the
deSignated register.

Ifl

0

Page 3 mto the

Exchange Indirect contents of Accumulator and locahon in data memory_
Exchange Indirect 4·blt contents of
Accumulator and data memory.
FLAGS

II

217

,... PD8041/8741A
INSTRUCTION SET (.cONT.)
INSTRUCTION CODE
MNEMONIC

07

DESCRIPTION

FUNCTION

06

05

04

03

02

FLAGS
01

DO

CYCLES

BYTES

C AC

FO

F1

ISF

OBF

INPUT/OUTPUT
ANL pp. "data

IPpl·
p 1

ANLD PP. A

log'cal and

IPp\ AND data
2

speel/led data
with deSignated port 11 or 21

IPpl· (Ppl AND (A 0
4 7

31

p
IN A. Po

(AI, (Ppl. p

IN A, DBB

{Al

1

MOVO A. Pp

(A 0
IA 4

31· (Ppl. p
71· 0

MOVD PP. A

IPp I·

A 0

Immedl~te

2

P

d7

dl

dO

I I p
d7
dS
dS
d4
d3
d2
d,

P
dO

Logical and contents of Accumulator
with desiQnllted port (4 - 7),
Input data !.r,om

de~,gnaled

port \1

d6

dS

d4

o

0

1

d3

d2

.0

21

,nlO Accumula'lOr.
+-

(DB B)

Input strobed DBB data into
Accumulator and cJear ISF

:>

p

4

7

Move contents of deSignated port 14

7

Move contents of Accumulator to

IPpi· (Ppl OR (A 0
4 7

3)

des.gnaled port 14

ORLDPp.A

71

mto Accumulator
4

71

Logical or contents of Accumulato. with

p

deSignated port (4

71

IPp)' IPp) OR data
1 2

Logical or lmmedlate specII,erJ data With
des,gnated port (1
2)

OUT OBS. A

(DBB) (A)

Output contents of Accumulator onto
DBB and set OaF.

OUTl PP. A

(Ppl·

IAI,p

DEC Rr

IRd·

IRr)

OR L pP. '" data

p

1

2

1.'

0

0

0

0

0

Output contents of Accumulator to
deSignated port 11
2)
REGISTERS

IRrl

7

D~cr~ment

by 1 contents 01 deSignated

reg,ster
INC Rf

IRd· (Rrl +1, r

INC@Rr

I!Rdl' IIRdl + 1
r • 0 1

CAll addr

IISPI) . IPC). {PSW 4

0

0

Increment by 1 contents of deSignated

7

Increment Indlfect by 1 the contents of
data memory location

SUBROUTINE

71

Call deSignated Subroutine

(SPI' ISPI + 1
IPC 8 10)· addr 8 10
(PC 0 7)· addr 0 7
IPC 11)' DB'

RET

(SPI . (SPI
1
(PC) . liSP))

Return from SubrOutine Without
restoring Program Status Word

RETR

ISPI· {SPI
1
iPCI· {(SP))
(PSW 4 71· (ISP))

Return from Subroutine restoring
Program Status Word.

a,o

a9

a8

"7

as

as

a4

83

32

a,

ao

TIMER/COUNTER

0

EN TCNTI

Enable Internal Interrupt Flag for
T,mer/Counter output

DIS TeNTI

Disable Internal Interrupt Flag tor
T,mer/Counter output.

MOV A. T

IA) . ITI

MOV T. A

m·

IAI

Move contents of TImer/Counter Into
Accumulator
Move content: ot ilccumulator Into
T,mer/Counter.

STOP TCNT

Stop Count for Event Counter

STAT :NT

Start Count for Event Counter.

STAT T

Start Count for TImer

(i)
@

!\jot.',

I No Operation performed.

I

NOP

0

MISCELLANEOUS

I

0

0

1

I

COdt' D""<'1I'<1I,on, • ""t1 11 fo'on 111>< t"ndty 'l'il'1'5I'nt,111011 Of 'h" R!'q,q,·., _I"!! Po' h

Th,'

,101

und," ~h" ,lPP'OD'"ltl' 11,1lj 1),1 ,ntl'L;),e,

111,11

ots COrltf'nt

",>uI1lt'L'1

to Chd"'lt'

I,y

IIW'

'hl'u(

0

R"t"I"t1lP, lu t'lf' ,l(tll'e"~ ,111(j ,),I\d ,I't' specll,{,o .11 I~ytf'~ 2,111(10' 101 'hI' ''',I'uCI 0"

(4)

l\Jur"r't" C.I 5ul)\( 'PI'> ,IPP~d""4 1(l11H' FUNCTION colun111 r;>t"rence thl'speClllc b,ts :tffttctetl.

!---<

'0

I
X

VALID

>----<

M"

ADDRESS

X

NEXT DATA
our VALID

>----

X

X

'70 ~'1

OATAOUT

L-

I

\

ADDRESS
1G11VALIQ

VERIFVMODE TIMING
("PDB04818748 .ONLVI

lllale. G)Cond'I'OfK
I... 10K

a

TTlL"",c··l·~.Ao

TTllogtC"O"'mullDl!","

,"",or Ie Vee lor fl.' and IOK .....1O< 10 vss 10' A.a.

dlate'the
the Accumulator

o.

2047) of

~048

,.

40951 of

31) of
DATA MOVES

MOV A,

data

MOV A. RI

IA)'

IRrI,

MOVA,(" A.

(AI.

((A,I),

MOV A. PSW

IAI' IPSWI

MOV Ar.

(R,I· fiala,'

data

!Ad

MOtt'A., A

MOV

t~

MOVl"'Ar,

d.lIiI,

MOV PSW, A
MOVP A,

t~

A

0

7
0

71

1

a

1

d3

1

1

d2

dl

dO

<17

u6

1

0

d5

d4

d3

d2

'dl

clO

d3

d2

d,

dO

0

Move Indllec! AccumulatOr Contents
+nto data memory location
Move Immed,l

d4

1

'MOVX A. 0l A
MOVX

" ,
cl5

Statu~

Movt' Accumuliltor Conlenh ;, eompatible with Industry Standard 80'49/80'39
• Pin Compatible with the pPD8O'48/8748/8O'35
• NMOS Silicon Gate Technology Requiring a Single +5V ±lO'% Supply.
• 1.36 ps Cycle Time. AJllnstructions lor 2 Bytes
• Programmable Interval Timer/Event Counter
• 2K x 8 Bytes of ROM, 128 x 8 Bytes of RAM
• Single Level Interrupt
• 96 Instructions: 70' Percent Single Byte
• 27 I/O Lines
• I nternal Clock Generator
• Expandable with 8O'8O'Al8O'85A Peripherals
• Available in Both Ceramic and Plastic 4O'-Pin Packages

PIN CONFIGURATION

TO
XTALI
XTAL2

Vee

REsET
55

I,NT
EA
RD

PSEiii
WR
ALE
DBo
DBl
DB2
DB3
DB4
DB5
DB6
DB7
Vss

IlPD
80'49/
8O'39L

Tl
P27
P26
P25
P24
P17
P16
P15
P14
P13
P12
Pll
Pl0
VDD
PROG
P23
P22
P21
P20

(

II

231

.fL PD8049/8039L
The NEC J..iPDS049 and J..iPDS039L are high performance, single component, S-bit
parallel microcomputers using N-channel silicon gate MOS technology. The J..iPDS049
and J..iPDS039L function efficiently in control as well as arithmetic applications. The
powerful instruction set eases bit handling applications and provides facilities for binary
and BCD ·arithmetic. Standard logic functions implementation is facilitated by the
large variety of branch and table look-up instructions.

FUNCTIONAL
DESCRIPTION

The J..iPDS049 and J..iPDS039L instruction set is comprisedof 1 and 2 byte instructions
with over 70 percent single-byte. The instruction set requires only 1 or 2 cycles per
instruction with over 50 percent single-cycle.
The J..iPDS049 and J..iPDS039L microprocessors will function as stand-alone microcomputers. Their functions can easily be expanded using standard SOSOA/SOS5A
peripherals and memories.
The J..iPDS049 contains the following functions usually found in external peripheral
devices: 204S x S bits of mask ROM program memory; 12S x S bits of RAM data
memory; 27 "110 lines; an S-bit interval timer/event counter; and oscillator and clock
circuitry.
The J..iPDS039L is intended for applications using external program memory only. It
contains all the features of the J..iPDS049 except the 204S x S-bit internal ROM. The
external program memory can be implemented using standard SOSOA/SOS5A memory
products.
POWER SU"l Y

I

I

lvoo

PROGRAM
SUPPL.Y

lvee
"v

ILOWPOWER
STANDI"'I

BLOCK DIAGRAM

I~ss
GROUND

EXPANSION TO ADDITIONAL

EXTERNAL MEMORY AND 110

BU'
BUFFER
AND
PORT 1

REGISTER :2
REGISTER 3

REGISTER 4
REGISTER S

AEGISTER6
REGISTEFI?
LEVEL STACK
(VARIABLE WORD LENGTHI

ICNAl SECOND

EGISTER IANI(
DATASTo;RE

CONTROLANDTIMLNG

RESIDENT DATA MiMOR' - RAM

l128x81

CLOCK

232

JL PD8049/8039L
PIN IDENTIFICATION

PIN
FUNCTION
NO.

SYMBOL

1

TO

2

XTAl1

One side of the crystal, lC, or external frequency source. (Non·TTl
compatible VIH')

3

XTAl2

The other side of the crystal or lC frequency source. For external
sources, XTAL 2 must be driven with the logical complement of
the XTAL 1 input.

4

RESET

Active low input from processor initialization. RESET is also used for
PROM programming'verification and power·down (non·TTL com·
patible VIH).

5

SS

Single Step input (active·low). SS together with ALE allows the
processor to "single-step" through each instruction in program
memory.

6

INT

Interrupt input (active·low). INT will start an interrupt if an .enable
interrupt instructiol') has been 'execu'ted. A reset will disable the interrupt;INT can be·tested by issuing a conditional jump instruction.

7

EA

External Access input (aciive-high): A fogic "1" at'this input com·
mands the processor to perform all program memory fetches from
external memory.

8

RD

READ strobe outputs active-low)"RD will pulse low when the processor performs a BUS READ. Ri5 will also enable data onto the
processor BUS from a peripheral device and function as a READ
STROBE for external DATA MEMORY.

9

PSEN

Program Store Enable output (active·low). PSEN becomes active only
during an external memory fetch.

10

WR

WR ITE strobe output (active-low). WR will pulse iow when the
processor performs a BUS WR ITE. WR can also function as a WR ITE
STROBE for external DATA MEMORY.

11

ALE

Address Latch Enable output (active-high). Occurrihg once each cycle,
the falling edge of ALE latches the address for external memory or
. peripherals. ALE can also be used as a clock output.

12-19

DO-D7 BUS

8-bit, bidirectional port. Synchronous reads and writes can, be performed on this port using R Dand WR strobes. The contents of the
DO-D7 BUS can be latched in a static mode.
During an external memory fetch, the DO-D7 BUS holds the least
significant bits' of the program counter. PSEN controls the incoming
addressed .instructibn. Also, for an external RAM data store instruction the DO-D7 BUS, controlled by ALE, RD and WR, contains
address and data information.

Testable input using conditional transfer functions JTO and JNTO. The
internal State Clock (ClK) is available to TO using the ENTO ClK
instruction. TO can also be used during programming as a testable flag.

20

VSS

21·24,
35-38

P20-P27:
PORT 2

Processor'" GROUND potential.
Port 2 is the second of two 8-bit quasi-bidirectional ports. For external
data memory fetches, the four most significant bits of the program
counter are contained in P20-P23.· Bits P20,P23 are also used as a
4-bit I/O bus for the IlPD8243,INPUT/OUTPUr EXPANDER.

25

PROG

PROG is used as anoutput strobe for IlPD8243's during I/O expansion. When the IlPD8049 is used in a stand-alone mode the PROG pan
can be allowed to float.

26

VDD

VDO is used to provlde +5V to the 128 x 8 bit RAM section. During
normal operation V CC must also be +5V to provide power to the other
functions in the device. During stand-by operation VOO must remain
at +5V while Vee is at ground potential.

27·34

P10-P17:
PORT 1

39

T1

40

VCC

Port 1 is one of two 8-bit quasi·bidirectional ports.
Testable input-using conditional transfer functions JT1 and JNT1. T1

can be made the counter/timer input using the STRT CNT instruction.
Primary Power supply. VCC is +5V during normal operation.

233

II

P. PD8049/8039L
Operating Temperature ..
Storage Temperature (Ceramic Package).
Storage Temperature (Plastic Package) .
Voltage on Any Pin
Power Dissipation : .......•..
Note:



Processor

Control signal for transf,r of data from
FOC to Data Bus, when ;'0" (low),
Control signal for transfer of data to Foe
via Data Bus, when "0" flowl.

3

WR

Write

Inputw

ProcessCY

Clpck Active (High)

01>0

Clock Rise Time'

oI>r

20

ns

Clock Fall Time

oI>f

20

ns

AO, CS, DACK Set Up Time to RD I

TAR

0

ns

AO, CS, DACK Hold Time from RD t

TRA

0

ns

RDWidth

TRR

250

Data Access Time from R 0 ...

TRD

Flo~t

Delay Time from RD t

125

500

ns

Clock Period

DB to

120

TEST
UNIT
CONDITIONS
MAX

ns

40

ns
200

ns

CL = 100 pf

100

ns

CL=100pF

TDF

20

AO, CS, DACK Set Up Time to WR I

TAW

0

ns

AO, CS, DACK Hold Time to WR t

TWA

0

ns

WRWidth

TWW

250

ns

Data Set Up Time to WR t

TOW

150

ns

Data Hold Time from WR t

TWO

5

INT Delay Time from RD t

TRI

500

INT Delay Time from WR t .

TWI

500

ORa Cycle Time

TMCY

ORa Deley Time from DACK I

TAM

TCWidth

TTC

Reset Width

TRST

WCK Cycle Time

ns

13

ns
ns
I'S

200
1

ns
CY

14

CY
2 or 4(6)

TCY

MFM -0
I'S

10r2

WCK Active Time (High)

TO

350

ns

WCK Rise Time

Tr

20

ns

WCK Fall Time

Tf

20

ns

Pre-Shift Oeley Time from WCK t

TCp

20

100

ns

WDA Deley Time from WCK t

TCD

20

100

ns

ROD Active Time (High)

TROD

40

Window Cycle Time
Wintlow Hold Time to/from ROD

BO

250

ns
MFM =0

2.0
TWCY
TROW

MFM=l

I'S

1.0
15

ns

MFM = 1

TWRD

,

USO,l Hold Time to RW/SEEK t

TUS

12

I'S

SEEK/RW Hold Time to LOW CURRENT/
DIRECTION t

TSD

7

I'S

LOW CURRENT/DIRECTION Hold Time to
FAULT RESET/STEP t

TDST

1.0

I'S

USO,l Hold Time from FAULT
RESET/STEP t

TSTU

5.0

I'S

STEP Active Time (High)

TSTP

STEP Cycle Time

TSC

FAULT RESET Active Time (High)

TFR

Write Data Width

5.0
33
8.0

@

I'S

G>
10

~s
~s

ns

USO;l Hold Time After SEEK

TWDD TO-50
15
TSU

Seek Hold Time from 0 I R

TDS

30

1'5

DIR Hold Time after STEP

TSTD

24

I'S

I'S

in"dex Pulse Width

TIDX

625

I'S

RD I Deiav from ORa

TMR

800

ns

WR I Delay from ORa

TMW

250

WE or RD Response Time from ORa t

TMRW

Notes:

ns
12

8 MHz Clock
Period

8 MHz Clock
Period

I'S

CD Typical vaJues tar'Ta:: 2S'C and nominal supply voltage•.
® The former value of 2 and 1 are applied to Standard Floppy. and the latter valu'e of 4 and 2 are
,
applied to Mini-flopPV.
® Under Software Control. The range is from 1 ms to 16 ms at 8 MHz Clock Period. and 2 to 32 ms
at 4 MHz Clock Period.

244

8 MHz Clock
Period

fLPD765
TIMING WAVEFORMS

PROCESSOR READ OPERATION

PROCESSOR WRITE OPERATION

'L

INT

CLOCK
eLK
I 90

I

I

I

I '--i I
6R~ 1--11

I

---' I--OF

DIV!A OPERATION

FDD WRITE OPERATION

- J I--To
I
WRITE CLOCK

I

I .....- - J I

I

TR __: : _

I

I

~

:

I

WRITE ENABLE

I

f--'-- T CY ---l

I l--l I-- T F

I II

~

t--TCP

-:-V---"'!Io~I:

PRESHIFT 0 OR

V-1""="'-"---..JX'----"--

'-..J\

_I

I

--l

~TCD

I

I--TWDD

WRITE DATA

i----TCD
PRESH1FT

NORMAL
LATE

EARLY
INVALID

a

PRESHIFT 1

,
,

0
0

0

,

0

,

245

!-,P0765
SEEK OPERATION

uSa.l

RW/SEEK

---v:ow
--A------.Jt'-----J tu sf---1 tsu r-STABLE

Yr~------~:
Itosl - I f - - - - -

-----..J-

X"';".--i-:-----

~

tOST--j

r--

-I

-,tSOt--

DIRECTION _ _ _ _ _

STEP

TIMING WAVEFORMS
(CONT;)

I--~TU--1

________~S_TD------~I~
tSTP~

f--

1

r.
I.
.
. - - - -

tsc - - -.....--ll

FL T RESET
I

FAULTRESET~

INDEX

I

~

FILE UNSAFE RESET

I
T F R 1-04---

II

~

1

I~---'r

1 TIDX

II

H

T,OX

I

r--=----J

FDD READ OPERATION

-J1________.,n.______

READ DATA

-:

:--TRDD

:-TWRD-j

X

_ _ _ _ _ ___.

READ DATA WINDOW

Note: Either polarity data window is valid.

I

:-TRDW-j

I

~,
I

A..-

o----TWCy

•

' -.I. .

:

RESET
TERMINAL COUNT

H~

RESET.--J: .

TC-n-

--l

~TTC

---'

I-- TRST

The IlPD765 contains two registers which may be accessed by the main system processor; a Status Register and a Data Register. The 8-bit Main Status Register contains the
status information of the FOe, and may be accessed at any time. The 8-bit Data
Register (actually consists of several registers in a stack with only one register p'resen ted to the data bus at a time), which stores data, commands, parameters, and FDD
status information. Data bytes are read out of, or written into, the Data Register in
order to program or obtain the results after a particular command. The Status
Register may only be read and is used to facilitate the transfer of data between the
processor and J.1PD765.
The relationship between the Status/Data registers and the signals RD, WR, and AO
is shown below.
AO
0
0
0
1
1
1

246

RD
0

WR

1

0
0
0

0
0
0
1

1

1

0

.

FUNCTION
Read Main Status Register
Illegal
Illegal
Illegal
Read from Data Register
Write into Data Register

I NTE RNA L REG ISTE RS

p.PD7,65
INTERNAL REGISTERS
(CaNT.)

The bits in the Main Status Register are defined as follows:
.
BIT NUMBEB

NAME

SYMBOL

FDD 0 Busy

aBo
OBI
DB2
DBa

FDD I BuSV
FDD 2 Busv
FDD 3 Busy

DB4

FDC Busy

DB5

Non-DMA mode

DESCRIPTION

FOD number 0 is in: the Seek mode.
FOD num!l~r 1 is in the Seek mode.

DOB
DIB
D2B

FOD number 2 is in the Seek mode.
FOD number 3 is in the Seek mode.
A read or write command is in process.

DaB
CB
NOM

Indicates the FOC is in the non-OMA mode.

This bit is set only during execution phase in
non-DMA mode. When DBS goes low, execuDBS

Data Input/Output

010

DB7

Request for Master

ROM

tion ·phase has ended.
Indicates direction of data transfer between
FOC and Data Register. If 010 = "1" then
transfer is from Data Register to the Processor.
If 010 = "0", then transfer is from the Processor to Data Register.
Indicates Data Register is ready to send or
receive data to or from the Processor. Both bits
010 'and ROM should be used to perform the
hand:.sha,king functions of "ready" and "direction" to the processor.

The 010 and ROM .bits in the Status Register indicate when Data is ready and in which direction
data will be transferred on the Data, Bus. The'max time from the trailing edge of the last Ri5 in the
result phase to when DB4 (FDC Busy) goes low is 12 ~s.
Out

Data In/Out
Out Processor and Into

(010)

Foe and

Into Processor

~

FocI

ReadV

I

I

I ,
I
~
Not
'I
I
I

Request for Master I
IROM)
I
I

.

II

I

Ready

I

I

I

I

I

I

I

WR'

I

:

Ro~:
I A I B I A IBI A I c I D i e ID IBI A I
Notes, ~ - Data register ready to be written IOta by processor

PACKAGE OUTLINE
JLPD765C

[ill -

Data register not ready to be wntten IOta by processor

{f] '[Q] -

Data register ready fur next dala byte to be read by the processor

I·
1
+1_ i

~Ill=

ITEM

.lr~1
TTJ _I~__ - -

A

~WJ

MILLIMETERS
51.SMAX
1,62
2.54!0.!
0.5'0.1
48.26
1.2 MIN
2.S4MIN
O.SMIN
5.22 MAX
5.72 MAX
15.24
13.2
+0.1
0.25
0.05

COMMAND SEQUENCE

Data register not re.:ldy for next data byte to be read by processor

-Ie

t

'I=±t

-g-

G

M 00 _15 0

I-

INCHES
2.028 MAX
0.064
0.10

!

O.Q04

0,019·0.004

"

0,047 MIN
0.10 MIN
0.019 MIN
0.206 MAX
O.22SMAX
0 ....
0.520
+ 0.004

0.010

0.002

The I1P0765 is capable of performing 15 different commands. Each command is initiated by a
multi·byte transfer from the processor, and the resu It after execution of the command may also
be a multi-byte transfer back to the processor. Because of this multi-byte interchange of information between the I1P0765 and the processor, it is convenienuo consider each command as
consisting of three phases:
Command Phase:

The FOC receives all information required to perform a particular
operatio~ from the processor.

Execution Phase:

The FOC performs the operation

Result Phase:

After completion of the operation, status and other housekeeping
information are made available to the processor.

i~

was instructed

~o

do.

247

",PD765

INSTRUCTION SET (j) @

J

DATA BUS
PHASE

R/wID7

0605040302

0,

I
REMARKS

DO I

PHASE

R/W

Command

W

MT

W

W
W

w
W
W
W

w

MF

SK

0

X

X

X

06

05

HO

Command

usa

US1

~~'======

~,======

W

MT

W

X

W

--------c--------

W

W
W
W
W
W

0

X

X

Result

MT

MF

W
W
W
W

W
W
W

W

X

HO US1

R

Sector 10 information prior
to Command execution

---H======
---------EOT------------------GPL------------------OTL------

=====STOI--===
---------ST2---------- - -H=========
ST1-

R

R
R

W

MF

a a

Sector 10 information after
Command execution

Sector 10 information prior
to Command execution

X

X

X

HO

US1

Command

R

MF

W

X

X

a a
X

R

W

o

MF

HD US1

0
X

usa

1
X

X

HO US1

Status information after
Command, exec:ution
Sector 10 information during
Execution Phase

Command Codes

USO

-----GPL==
====S~-======

Execution

Bytes/Sector
SectorslTrack
Gap 3
Filler Byte
FOC formats an entire track

R

===STST'0======
=
-------ST
2-------

====-C,====

Status information after
Command execution
In this case, -"Ie 10 information
has no meaning

N

SCAN EOUJ}L
Status information after
Command execution

Command

W

MT

W

Sector 10 information aiter
Command execution

Status information after
Command execution
Sector 10 information after
Command execution

====-~====

Symbols used in this table are described at the end of this section.

MF
X

SK

1

1

X

HO

USl

Sector 10 information prior
to Command execution

W
W
W
W
W
W

Command Codes

usa

W

===E~T;====
----GPL------------STP----------

Execution

Oata-compared between the
Fi)O and main-system

-===ST 0======
---------ST2-----

@ Aa should equal binary 1 for all operations.
@) X '" Don't care, usually made to equal binary O.

X

---------STO---------===-STST 2'=====
=
-------C---------

Result

====STO=======
ST'
---------ST2----------

Commands

1

X

The first correct 10 information
on the Cylinder is stored in
Data Register

R

Sector 10 information prior
to Command execution

----- C
- - - - - H --------

R

248

a

W
W
W
W

Result

Data-transfer between the
FOD and main-system

ReSUlt

Sector 10 informationatter
Command execution

N

usa

Execution

Status information after
Command execution

FORMAT A TRACK

Command Codes

W
W
W
W
W
W
W

CD

-----R------

Status information after
Command execution

N

Note:

---------STO------------------ST'---------===S~ 2',,==:===

W

Result

WRITE DELETED DATA
MT

uso

Execution

------- R - - - - -

W

US1

---------OTL_----~----

Data-transfer between the
main-system and FDD

Result

HD

READ 10

Command

usa

Execution

Command

R

R

Command Codes
X

Command Codes
X

Sector 10 information prior
to Command execution

W

0

X

REMARKS

Data-transfer between t he
FDD and main-system_ FDC
reads aU data fields
from index hole to Ear .

R
R

WRITE DATA
W

X

------~-GPL,----------

R

N

Command

a

X

----------EO;T==========

Data-transfer between the
FDD and main-system

------- C -------

SK

W

Command execution
Sector 10 information after
Command execution

-----EOT
-----GPL--===========
-----OTL------

---------5TO---------=========ST'---------ST2-----

MF

Status information after

Command Codes

~'~,====

o

W
W
W
W

usa

HD USl

Execution

Result

DO

FDD and main-system

N

M F SK

0

Execution

READ DELETED DATA
Command

03' 02

W

w
Data-transfer between the

-----STO----__
-----ST'-=======
-----ST2-

W

W
Sector ID information prior
to Command execution

----- EOT' -=====
-----GPL-----OTL,------

Execution

Result

04

READ A TRACK
Command Codes

X

'1

DATA BUS

07

READ DATA

R

STl

====~=====
--------N---------

Status information after
Command execution
Sector 10 information after
Command execution

INSTRUCTION SET
(CONT.)
-I
PHASE

AM

fL PD765
J

DATA BUS
D7

""- D. D.

D3

D.

D

REN!ARK,S

Dol

PHASE

AM-

I

SCAN LOW OR eQUAL
Command

W

MT

MF

SK

,

W

X

X

X

X

W

HO US1

W
W

USO

Sector 10 information prior

C
H

-w

Command

Command Codes
X

C~'!1maAd

execution

X

""
X

DS D.

D3 D2" 'D,

w

N
eOT
GPL

W

STP

W

'Command

0

0

X

X

Command Codes
-X

W

FDD and main-system

Result

USO

Command Codes

Command execution

W

0

W
W

SAT
HLT

.. ..
0

0

SK

1

X

X

Command

Comr:nanq execution

W
W

X

0

0

X

X

EaT

W
W

GPL

•

NO
Command Codes

X

HO US1

HO

US~

USO

Status information about FoD

SeEK
Command

USO

Sector 10 information prior
Comman~ execution

C
H
A
N

W

HUT

5T,3

Result
Command Codes

X

Command Codes

0

SENSE DRIVE STATUS

Sector 10 information after

SCAN HIGH OR EQUAL
MT- MF

Status information at 'the end
of seek· operation about the FOC

STO
PCN

SPECIFY

Command

Status information after

STO
ST1
ST2
C
II
A
N

A
A
A
A
A
A

W
W

X

0

0

X

X

1
X

HO US1

Command Codes

USO

NCN

W
Execution

Head is positioned over
proper Cvlinder on
Diskette

-Sn>

Execution

Data-compared between the
FOO and main-system

A
A
A
A
A
A

US1

0

Data-compared bet~en the

Result

C

Head retracted to Track 0

Result

ExecUtion

W
W
W
W

REMARKS

SENSE INTERRUPT STATUS

w

W·
W

DO

RECALIBRATE

Execution

W

Command

I

DATA BUS.
~7

Status information after
Command 8xetution

STO
ST1

ST2

Command

INVALID
_ _ _ Invalid Codes _ _ _ _

W

Result

ST 0

Invalid Command Codes
(NoOp - FOe goes into
Standby Statel
STO-80
(16)

Sector 10 information after
Command execution

C
A
N

COMMAND SYMBOL
DESCRIPTION

NAME

SYMBOL

AO

Address Line 0

DESCRIPTION

AO control~ selection of Main Status
Register (AO
(AO = 1)

~

0) or Data Register

C

Cylinder Number

C stands for the current/selected Cylinder
!track) number a through 76 of the
medium.

0

Data

07-0 0

Data Bus

OTL

Data. Length

EOT

. End of Track

GPL

Gap length

o stands for the data pattern which is
gOing to be written Inte. a Sector.
8-blt Data Bus, where 07 stands for a most
significant bit, and DO stands· for a least
significant bit.
When N IS defined a!. bo, OTl stands for
the data length wtllch users are gOing to
read out or wnte into the Sector.
EOT sta"ds for the final Sector number
on a e Ilnder.
GPl stands for the length of Gap 3
(spacing between Sectots excluding veo
Sync_ Field).

Head Address

H stands for head number 0 or 1. as
specified in 10 field_
HD stands for a selected head number 0
or 1. (H '" HO In all command words.)

HD

Head

HLT

Head Load Time

HL T stands for the head load time In the
FDD (2 to 254 ms in 2 ffi$ increments)_

HUT

Head Unload Time

MF

FM or MFM Mode

HUT stands tor the head unload time
after a read or write operation has
occurred (16 to 240 ms in 16 ms
Increments).
If MF' IS low, FM mode IS selected, and if
it is hl~, MFM mode is selected.

MT

Multi-Track

II

If MT is high, a multi-track operation IS to
be performed. (A cylinder under both

Hbo and HOl Will be read or written.) ,

249

fLP0765
' NAME

SYMBOL
N

Numbet,

NCN

New Cylinder Number

DESCRIPTION

N stands for the number ot data bytes

"

.COMIIiiAN DSYM BO L
DESCRIPTION (CONT.,)

\Mitten in a Sector.

NCN stands for a new Cylinder number.
which is goi.ng to be reached as a result of the
Seek operation. Desired position of Head.

NO

Nan·OMA Mode

ND stands for operation in the Non-DMA Mode.

PCN

Present Cylinder

PCN stands for the Cylinder number at the com·
pletian of SENSE INTERRUPT STATUS
Command. Position of Head at present time.

Number
R

Record

RNV

ReadNVrite

R stands for the Sector number, which will
be read or written.
RIW stands for either Read (RI or Write (WI

signal.
SC indicates the number of Sectors per

SC

Sector

SK

Skip

SK stands for Skip Deleted Data Address Mark.

SRT

Step Rate Time

SRT stands for the Stepping Rate for the FOO.

Cylinder.

I
I
ST 0
ST 1
ST 2
ST3

(1 to 16 ms in 1 ms increments.) Stepping Rate

applies to all drives, (F
Status
Status
Statu.
Status

0
1
2
3.,

= 1 ms, E

c

2 ms, etc.),

5T 0-3 stand for one of four registers which

store the status information after a command .
has been executed. This information is
available during the result phase after command

execution. Thes~ registers should not be con·,
fused with the main status register (selected by

I

AO = 01. ST 0-3 may be read only after a com·
mand has been executed and contain informatior
relevant to that pal'ticular command.

During a Scan oper~tion.. if 5TP = 1, the data in
contiguous sectors is compared byte by byte

STP

with data sent from the processor (or DMA);

and if 5TP =,2, then alternate sectors afe read
and compared.
USO, US1

US stands for a selected drive number 0 or 1.

Unit Select

SYSTEM CONFIGURATION

OBa-7

AO

MEMR

OBo-7

iOR

Ri5

MEMW

\VA
Cs

iOW
CS

INT

HRa

RESET

HLDA

ORa

J,l.P08257

CON~~;lLER

DACK

TC
TERMINAL
COUNT

READ

fLPD765
PROCESSOR INTERFACE

During Command or Result Phases the Main Status Register (described earlier) must be
read by the processor before each byte of information is written into or read from the
Data Register. Bits D6 and D7 in the Main Status Register must be in a 0 and 1 state,
respectively, before each byte of the command word may be written into thepPD765.
Many of the commands require multiple bytes, and as a result the Main Status Reg·
ister must be read prior to each byte transfer to the IlPD765. On the other hand, during
the Result Phase, D6 and D7 in the Main Status Register must both be 1:s (D6 = 1 and
D7 = 1) before reading each byte from the Data Register. Note, this reading of the
Main Status Register before each byte transfer to the IlPD765 is required in only the
Command and Result Phases, and NOT during the Execution Phase.
During the Execution Phase, the Main Status Register ne.ed not be read. If the IlPD765
is in the NON·DMA Mode, then the receipt of each data byte (if IlPD765 is reading
data from FDD) is indicated byan Interrupt signal on pin 18 (INT = 1). The generation
of a Read signal (RD = 0) will reset the Interrupt as well as output the Data onto the
Data Bus. If the processor cannot handle Interrupts fast enough (every 13 IlS) then it
may poll the Main Status Registerand then bit D7 (ROM)functions just like the Inter·
rupt signal. If a Write Command is in process then the WR signal performs the reset to
the Interrupt signal.
If the IlPD765 is in the DMA Mode, no Interrupts are generated during the Execution
Phase. The'IlPD765 generates DRO's (DMA Requests) when each byte of data is avail·
able. The DMA Controller responds to this request with both a DACK = 0 (DMA
Acknowledge) and a RD = 0 (Read signal). When the DMA Acknowledge signal goes
low (DACK = 0) then the DMA Request is reset (DRO = 0). If a Write Command has
been programmed then a WR signal will appear instead of RD. After the Execution
Phase has been completed (Terminal Count has occurred) then an Interrupt wi II occur
(lNT = 1). This signifies the beginning of the Result Phase. When the first byte of data
is read during the Result Phase, the Interrupt is automatically reset (INT = 0).
It is important to note that during the Result Phase all bytes shown in the Command
Table must be read. The Read Data Command, for example has seven bytes of data in
the Result Phase. All seven bytes mlJst be read in order to successfully complete the
Read Data Command. ThellPD765 will not accept a new command until all seven
bytes have been read. Other commands may require fewer bytes to be read during the
Result Phase.
The IlPD765 contains five Status Registers. The Main Status Register mentioned above
may be read by the processor at any time. The other four Status Registers (STO, ST1,
ST2, and ST3) are only available during the Result Phase, and may be read only after
successfully completing a command. The particular command which has been executed
determines how many of the Status Registers will be read.
The bytes of data which are sent to the IlPD765 to form the Command Phase, and are
read out of the IlPD765 in the Result Phase, must occur in.the order shown in the
Command Table. That is, the Command Code must be sent first and the other bytes
sent in the prescribed sequence. No foreshortening of the Command or Result Phases
are allowed. After the last byte of data in the Command Phase is sent to the IlPD765,
the Execution Phase automatically starts. in a similarfashion, when the last byte of
data is read out in the Result Phase, the command is automatically ended and the
IlPD765 is ready for a new command. A command may be truncated (prematurely
ended) by simply sending a Terminal Count signal to pin 16 (TC = 1). This is a can·
venient means of ensuring that the processor may always get the IlPD765's attention
even if the disk system hangs up in an abnormal manner.

POLLING FEATURE OF
THE IlPD765

After the Specify command has been sent to the IlPD765, the Unit Select line USO and
US1 will automatically go into a polling mode. In between .commands (and between step
pulses in the SEEK command) the IlPD765 polls all four FDD's looking for a change
in the Ready line from any of the drives. If the Ready line changes state (usually due
to a door opening or closing) then the IlPD765 will generate an interrupt. When Status
Register 0 (STO) is read (after Sense Interrupt Status is issued!. Not Ready (NR) will
be indicated. The polling of the Ready line by the IlPD765 occurs continuously
between instructions, thus notifying the processor which drives are on or off line.

251

II

fLPD765
READ DATA
A set of nine (9) byte words are required to place the FDC into the Read Data Mode. After the Read Data
command has been issued the FOe loads the head (if it is in the unloaded state), waits the specified head
settling time (defined in the Specify Command), and begins reading ID Address Marks and ID fields. When
the current sector number ("R") stored in the 10 Register (lOR) compares with the sector number read off
the diskette, then the FDC outputs data (from the data field) byte·to·byte to the main system via the data

bus.
After completion of the read operation from the current sector, the Sector Number;s incremented by one,
and the data from the next sector is read and output on the data bus. This continuous read function is called
a "Multi-Sector Read Operation." The Read Data Command may be terminated by the receipt of a Terminal
Count signal. Upon receipt of this signal, the FOe stops outputting data to the processor, bu~ will continue
to read data from the current sector, check CRC (Cyclic Redundancy Count) bytes, and then at the end of
the sector terminate the Read Data Command.
The amount of data which can be handled with, a single command to the FDC depends upon MT (multitrack), MF (MFM/FM), and N (Number of Bytes/Sector). Table 1 below shows the Transfer Capacity.
Multi· Track
MT

MFM/FM
MF

Bytes/Sector
N

0
0

0
1

00
01

1
1

0
1

00
01

Maximum Transfer Capacity
(Bytes/Sector) (Number of Sectors)

=
=
(128) (52) =
(256) (52) =
(128) (26)
(256) (26)

3,328
6,656
6,656
13,312

0
0

0
1

01
02

(256) (15) =

1
1

0
1

01
02

(256) (30) - 7,680
(512) (30) = 15,360

0
0

0
1

02
03

1
1

0
1

02
03

(512) (15)

3,840

= 7,680

(512) (8)
(1024) (8)

4,096
8,192

=
(512) (16) = 8,192
(1024) (16) = 16,384

Final Sector Read
from Diskette
26 at Side 0
or 26 at Side 1
26 at Side 1
15 at Side 0
or 1 5 at Side 1
15 at Side 1
8 at Side 0
or 8 at Side 1
8 at Side 1

Table 1. Transfer Capacity

The "multi·track" function (MT) allows the FOC to read data from both sides of the diskette. For a
particular cylinder, data will 'be transferred starting at Sector 0, Side 0 and completing at Sector L, Side 1
(Sector L ::: last sector on the side). Note, this function pertains to only one cylinder (the same track) on
each side of the diskette.
When N = 0, then DTL defines the data length which the F DC must treat as a sector. If DTL is smaller than
the actual data length- in a Sector, the data beyond DTL in the Sector, is not sent to the Data Bus. The FOe
reads (internally) the complete Sector performing the CRC,check, and depending upon the manner of com·
mand termination, may perform a Multi-Sector Read Operation. When N is non-zero, then OTL has no
meaning and should be set to FF Hexidecimal.

At the completion of the Read Data Command, the head is not unloaded until after Head Unload Time
Interval (specified in the Specify Command) has elapsed. If the processor issues another command before
the head unloads then the head settling time may be saved between subsequent reads. This time out is
particularly valuable when a diskette is copied from one drive to another.
If the FDC detects the Index Hole twice without finding the right sector, (indicated in "Rill, then the FOC
sets the NO (No Data) flag in Status Register 1 to a 1 (high), and terminates the 'Read Data Command.
(Status Register 0 also has bits 7 and 6 set to 0 and 1 respectively.)
After reading the 10 and Data Fields in each sector, the-fDC checks the CRC bytes. If a read error is
detected (incorrect CRC in ID field), the FDC sets the DE (Data Error) flag in Status Register 1 to a 1 (high),
and if a CRC error occurs in the Data Field the F DC also sets the DO (Data Error in Data Field) flag in
Status Register 2 to a 1 (high), and term'inates the Re,ad Data Command. (Status Register 0 also has bits 7
and 6 set.to 0 and 1 respectively.)
Status Register 2 to a 1 (high), and terminates the Read Data Command.
If the FOC reads a Deleted Data Address Mark off the diskette, and ,the SK bit (bit D5 in the first Command
Word) is not set (SK = 0), then the FoC sets the CM (Control Mark) flag in Status Register 2 to a l (high),
and terminates the Read Data Command, after reading all the data in the Sector. If SK = 1, the FDC skips
the sector with the Deleted Data Address Mark and reads the next sector. The CRC bits in the deleted data
field are not checked when SK = 1.

During disk data transfers between the FOC and the processor, via the data bus, the FoC. must be serviced
by the processor every 27 ps in the FM Mode,' and every 13 J,J.S in the MFM Mode, or the FOC sets the OR
(Over Run) flag in Status Register 1 to a 1 (high), and terminates the Read Data Command.
If the processor terminates a read (or write) operation in the FoC, then the 10 Information in the Result
Phase is dependent upon the state of the MT bit and EOT byte. Table 2 shows the values for C, H, R, and
N, when the processor terminates the Command.

FUNCTIONAL
DESCR IPTION--QF
COMMANDS

j.J. PD765
FUNCTIONAL
DESCRIPTION OF
COMMANDS (CONT.)

MT

EOT

Final Sector Transferred

C

H

R

N

NC

NC

A+ 1

NC

08

Sector 1 to ~5 at Side a
Sector 1 to 14 at Side 0
Sector 1 to 7 at Side 0

lA
OF
08

Sector 26 at Side 0
Sector 1.5 at Side a
Sector 8 at Side 0

C+l

NC

R = 01

NC

lA
OF
08

Sector 1 .to 25 at Side 1·
Sector 1 to 14 at Side 1
Sector 1 to 7 at Side 1

NC

NC

A+l

NC

lA
OF
08

Sector 26 at Side 1
Sector 15 at Side 1
Sector 8 at Side 1

C+l

NC

R = 01

NC

lA
OF

NC

NC

A+ 1

NC

08

Sect~r 1 to 25 at·Side a
Sector 1 to 14 at Side 0
Sector 1 to 7 at Side 0

lA
OF
08

Sector 26 at Side a
Sector 15 at Side 0
Sector 8 at Side 0

NC

LS8

R = 01

NC

lA
OF
08

Sector 1 to 25 at Side 1
Sector 1 to 14 at Side 1
Sector 1 to 7 at Side 1

NC

NC

A+l

NC

lA
OF

Sector 26 at Side 1
Sector 15 at Side 1
Sector 8 at Side 1

C+l

LSB

A = 01

NC

lA
OF

a

1

08

Notes:

10 Information at Result Phase

to Processor

1 NC (No Change): The sam~ valu~ as the one at the beginning of command execution.

2 LSB (Least Significant Bit): The least significant bit of· H is complemented.

Table 2: 10 Information When Processo! T.erminates Comma!1d
WRITE DATA
A set of nine (9) bytes are required to set the FDC into the Write Data mode. After the Write Data command
has been issued the FOe loads the head (if it is in the unloaded state), waits the specified heat settling time

(defined in the Specify Command). and begins reading ID Fields. When the current sector number ("R"),
stored in the 10 Aegister (IDA) compares with the sector number read off the diskette, then the FDC takes
data from the processor byte·by·byte via the data buk, and outputs it to the FDD.
After writing data into the current sector, the Sectpr Number stored in "R" is incremented by one, 8F1d the
next data field is written into. The FOe continues this "Multi-Sector Write Operation" until the issuance of
a Terminal Count signal. If a Terminal Count signal is sent to the FOC it continues writing into the current
sector to complete the data field. If the Terminal Count signal is received while a data field is being written

then the remainder of the data field is filled with 00 (zeros).
The FDC reads the ID field of each sector and checks the CAC bytes. If the FDC detec~ a read error
(incorrect CRC) in one of the ID Fields, it sets the DE (Data Error) "ag'of Status Aegister 1 to a 1 (high),
and terminates the Write Data Command., (Status Register a a~so has bits 7 and 6 set to a and 1 respectively.)
The Write Command operates in much the same manner as the Read Command. The following items are the
same, and one should refer to the Read Data Command for details:
•

Transfer Capacity

• EN (End of Cylinder) Flag
• NO (No Data) Flag

•

Head Unload Time IntelVal

• 10 Information when the processor terminates command (see Table 2)
• Definition of DTL when N= 0 and when N''''' 0

In the Write Data mode, data transfers 'between the processor and FOC, via the Data Bus; must occur every

31 !,S in the FM mode, and every 15!,s in the MFM mode. If the time interval between data transfers is
longer than this then the' FDC sets the OR (Over Aun) flag in Status fjegister 1 to a 1 (hi!lh), and terminates
the Write Data Command. (Status Register 0 also has bit 7 and 6 set to 0 and 1 respectively.)
WRITE DELETED DATA
This command is the same as the Write Data Command except a Deleted Data Address Mark is written at the

beginning of the Data Field instead of the normal Data Address Mark.
AEAD DELETED DATA
This command is the same as the Read Data Command except that when the FOC detects a Data Address

Mark at the beginning of a Data Field (and SK

= a (low),

it will read all the data in the sector and set the

CM flag in Status Register 2 to a 1 (high), and then terminate the command. If SK = 1, then the FOC skips
the sector with the Data Address Mark and reads the next sector.

253

II

JL PD765
READ A TRACK

This command is similar to- READ DATA Command except that this,is a continuous READ operation
where the entire data field from each of the sectors are read. Immediately after encountering the
INDEX HOLE, the FOe starts reading all data fields on the track, as continuous blocks of data. If the
FOC finds an error in the 10 or DATA CRC check bytes, it continues to read data from the track. The
FoC compares the 10 information read from each sector with the value stored in the lOR, and sets the
NO flag of Status Register 1 to a 1 (high) if there is no comparison. Multi-track or skip operations are not
allowed with this command.

FUNCTIONAL
DESCR IPTION OF
COMMANDS (CONT.)

This command terminates when EOT number of sectors have been read. If the FOC does not find an 10
Address Mark on the diskette after it encounters the INDEX HOLE for the second time, then it sets the
MA (missing address mark) flag in Status Register 1 to a 1 (high), and terminates the command. (Status
Register 0 has bits 7 and 6 set to 0 and 1 respectively.)
READ 10

The READ 10 Command is used to give the present position of the recording head. The FOe' stores the
values from the first 10 Field it is able to read. If no proper ID Address Mark is found on the diskette,
before the INDEX HOLE is encountered for the second time then the MA(Missing Address Markl flag in
Status Register 1 is set to a 1 (high), and if no data is found then the NO (No Data) flag is also set in Status
Register 1 to a 1 (high). The command is then terminated with Bits 7 and 6 in Status Register 0 set to 0
and 1 respectively.
FORMAT A TRACK

The Format Command allows an entire track to be formatted. After the INDEX HOLE is detected, Data is
written on the Diskette; Gaps, Address Marks, 10 Fields and Data Fields, all per the IBM System 34 (Double
Density) or System 3740 (Single Density) Format are recorded. The particular format which will be written
is controlled by the values programmed into N (number of bytes/sectorl. SC (sectors/cylinderl, GPL (Gap
Lengthl, and 0 (Data Pattern I which are supplied by the processor during the Command Phase. The Data
Field is filled with the Byte of data stored in D. The 10 Field for each sector is supplied by the processor;
that is, four data requests per sector are made by the FDC for C (Cylinder Number), H (Head Number),
R (Sector Numberl and N(Number of Bytes/Sectorl. This allows the diskette to be formatted with non·
sequential sector numbers, if desired.
After formatting each sector, the processor must send new values for C, H, R, and N to the J,tPD765 for
each sector on the track. The contents of the R register is incremented by one after each sector is
formatted, thus, the R register contains a value of R when it is read during the Result Phase. This incrementing and formatting continues for the whole track until the FOC encounters the INDEX HOLE for the
second time, whereupon it terminates 'the command.
If a FAULT signal is received from the FDD at the end of a write operation, then the FDC sets the
EC flag of Status Register 0 to a 1 (highl, and terminates the command after setting bits 7 and 6 of Status
Register 0 to O.and 1 respectively. Also the loss, of a READY signal at the beginning of a command
executiqn phase causes bits 7 and 6 of Status Register 0 to be set to 0 and 1 respecitvely.
Table 3 shows the relationship between N, SC, and GPL for various sector sizes:
8" STANDARD FLOPPY
FORMAT

FM Mode

FM Mode

MFM Mode

SECTOR SIZE

N

SC

GPLG)

GPL®

128 bytes/Sector

00

lA(161

.07(161

1 B(161

IBM Diskette 1

256

01

2A(161

IBM Diskette 2

02

OF(161
08

OE(161

512

1 B(161

1024 bytes/Sector

03

04

47

204B

04

02

C8

4096

05

01

CB

256

01

lA(161

OE(161

512

02

OF(161

lB(161

54(161

1024

03

08

35(161

2048

04

04

99

74(161
FF

4096

05

02

C8

8192

06

01

C8

REMARKS



SC

GPLCl

12B bytes/Sector

00

12

07

GPL

 DProcessor
DFDD < Dprocessor

1

Scan High or Equal

COMMENTS

= SH

0
0
1

"*

Dprocessor

< Dprocessor

DFDD> Dprocessor

Table 4

= 0), then it regards the
sector as the last sector on the cylinder, sets CM (Control Mark) flag of Status 'Register 2 to a 1 (high) and
terminates the command. If SK = 1, the FDC skips the sector with the Deleted Address Ma,rk, and reads
the next sector. In the second case (SK = 1), the FDC sets the CM (Control Mark) flag of Status Register 2
to a 1 (high) in order to show that a Deleted Sector had been encountered.
If the FDC encounters a Deleted Data Address Mark on one of the sectors (and SK

When either the STP (contiguous sectors = 01, or alternate sectors = 02 sectors are read) or the MT (MultiTrack) are programmed, it is necessary to remember that the last sector on the track must be read. For
example, if STP = 02, MT == 0, the sectors are numbered sequentially 1 through 26, and we start the Scan
Command at sector 21; the following will happen. Sectors 21, 23, and 25 will be read, then the next sector
(26) will be skipped and the I ndex Hole will be encountered before the EOT value of 26 can be read. This
will result in an abnormal termination of the command. If the EDT had been set at 25 or the scanning
started at sector 20, then the Scan Command would be completed in a normal manner.
During the Scan Command data is supplied by either the processor or OMA Controller for comparison
against the data read from the diskette. In order to avoid having the OR (Over Run) flag set ,in Status
Register 1, it is necessary to have the data available in less than 27 IlS (FM Mode) or 13 IlS (MFM Mode). If
an Overrun occurs the FOC ends the command with bits 7 and 6 of Status Register,_O se,t to 0 and 1,
respect ivel y.
SEEK

The read/write head within the FOD is moved from cylinder to cylinder under control of the Seek
Command. The FOC compares the PCN (Present Cylinder Number) which is the current head position
with the NCN (New Cylinder Number), and if there is a difference performs the following operation:
PCN < NCN: Direction signal to FDD set to a 1 (high), and Step Pulses are issued. (Step In.)
PCN> NCN: Direction signal to FDD set to a 0 (low), and Step Pulses are issued. (Step Out.)
The rate at which Step Pulses are issued is controlled by SRT (Stepping Rate Time) in the SPECIFY Com·
. mand. After each Step Pulse is issued NCN is 'compared against PCN, and when NCN = PCN, then the SE
(Seek End) flag is set in Status Register 0 to a 1 (high), and the command is terminated.
During the Command Phase of the Seek operation the FDC is in the FDC BUSY state, but during the
Execution Phase it is in the NON BUSY state. While the FDC is in the NON BUSY state, another Seek

Command may be issued; and in this manner parallel seek operations may be done on up to 4 Drives at
once.
If an FOD is in a NOT READY state at the beginning of the command execution phase or during the seek
operation, then the NR (NOT READY) flag is set io Status Register 0 to a 1 (high), and the command is

terminated after bits 7 and 6 of Status Register 0 are set to

a and 1 respectively.

255

II

fI: PD765
RECALIBRATE

The function of this command is to retract the read/write head within the FDD to the Track 0 position.
The FOG clears the contents of the peN counter, and checks the status of the Track 0 signal from the
FDD. As long as the Track 0 signal is low, the Direction signal remains a (low) and Step Pulses are issued.
When the Track 0 signal goes high, the SE (SEEK END) flag in Status Register 0 is set to a 1 (high) and the
command is terminated. If the Track 0 signal is still low after 77 Step Pulse have been issued, the FOe sets
the SE (SEEK END) and EC (EQUIPMENT CHECK) 11ags of Status Register 0 to both 1s (highs), and
terminates the command after bits 7 and 6 of Status Register 0 is set to 0 and 1 respectively.
The ability to do overlap RECALIBRATE Commands to multiple FDDs and the loss of the READY signal,
as described in the SEEK Command, also applies to the RECALIBRATE Command.
SENSE INTERRUPT STATUS

An I nterrupt signal is generated by the FOe for one of the following reasons:
1. Upon entering the Result Phase of:
a. Read Data Command
b. Read a Track Command
c. Read I D Command
d. Read Deleted Data Command
e. Write Data Command
f. Format aCyl inder Command
g. Write Deleted Data Command
h. Scan Commands
2. Ready Line of FDD changes state
3. End of Seek or Recalibrate Command
4. During Execution Phase in.the NON·DMA Mode
Interrupts caused by reasons 1 and 4 above occur during normal command operations and are easily discernible by the processor. However, interrupts caused by reasons 2 and 3 above may be uniquely identified
with the aid of the Sense I nterrupt Status Command. This command when issued resets the interrupt signal
and via bits 5, 6, and 7 of Status Register identifies the cause of the interrupt.

a

SEEK END
BIT 5

INTERRUPT CODE
BITS

CAUSE

BIT 7

0

1

1

Ready Line changed state, either polarity,

1

0

1

1

0
0

Abnormal Termination of Seek or Recalibrate'Command

Normal Termination of Seek or Recalibrate Command

Table 5
Neither the Seek or Recalibrate Command have a Result Phase. Therefore, it is mandatory tOluse the Sense
Interrupt Status Command after these commands to effectively terminate them and to provide..verification of
vvhere the head is positioned (PCN).

SPECIFY
The Specify Command sets the initial values for each of the three internal timers. The HUT .(Head Un.load Time)
defines the time from the end of the Execution Phase of one of the Read/Write Commands to-,the head unload
state. This timer is programmable from 16 to 240 ms in increments of 16 ms (01 :: 16 ms, 02 == 32 ms '. '.' . OF ==
240 ms). The SRT (Step Rate Time) defines the time interval between adjacent step pulses. This timer is programmable from 1 to 16 ms in increments of 1 ms {F :: 1 ms, E == 2 ms, D ;: 3 ms, etc.>. The HLT (Head Load
Time) defines the time between when the Head Load signal goes high and when the Read/Write operation starts.
This timer is programmable from 2 to 254 ms in increments of 2 ms {01 = 2 ms, 02;: 4 ms, 03 = 6 ms ... 7F =
254 msl.
The time intervals mentioned above are a direct function of the clock (eLK on pin 19), Times indicated above
are for an 8 MHz clock, if the clock was reduced to 4 MHz (mini-floppy application) then all time intervals are
increased by a factor of 2.
The choice of DMA or NON-DMA operation is made by the NO (NON-OMA) bit. When this bit is high (NO
the NON·OMA mode is selected, and when NO = a the OMA mode is selected.

= 1)

SENSE DRIVE STATUS
This command may be used by the processor whenever it wishes to obtain the status of the FOOs. Status Register
3 contains the Drive Status information.
INVALID
If an invalid command is sent to the FOC (a command not defined above), then the FDe will terminate the command after bits 7 and 6 of Status Register a are set to 1 and a respectively. No interrupt is generated by the
J.tPD765 during this condition. Bit 6 and bit 7 (DIQ and RQM) in the Main Status Register are both high ("1")
indicating to the processor that the ,uPD765 is in the Result Phase and the contents of Status Register a (STO)
must be read. When the processor reads Status Register 0 it will find a 80 hex indicating an invalid command
was received.
A Sense Interrupt Status Command must be sent after a Seek or Recalibrate Interrupt, otherwise the FOC will
consider the next command to be an Invalid Command.
In some applications the user may. wish to use this command as a No-Op command, to place the FOC in a
standby or no operation state.

FUNCTIONAL
DESCRIPTION OF
COMMANDS (CONT,)

,u.PD765
STATUS REGISTER
IDENTIFICATION

NO.

BIT
NAME

SYMBOL

DESCRIPTION

STATUS REGISTER 0

07 = 0 and 06 = 0
Normal Termination of Command, (NT). Command was completed and properly executed.

07
Interrupt
Code

IC

07 - 0 and 06 - 1
Abnormal Termination of Command, (AT).
Execution of Command was started, but was not
successfully completed.

06

07= 1 and 06 = 0
Invalid Command issue, (IC). Command which
was issued was never started.

07 = 1 and 06 - 1
Abnormal Termination because during command
execution the ready signal from FDD changed
state.
05

Seek End

SE

When the FDC completes the SEEK Command,
this flag is set to 1 (high).

04

Equipment
Check

EC

If a fault Signal is received from the FDO, or if
the Track 0 Signal fails to occur after 77 Step
Pulses (Recalibrate Command) then this flag is
set.

03

Not Ready

NR

When the FDD is in the not-ready state and a
read or write command is issued, this flag is set_
If a read or write command is issued to Side 1 of
a single sided drive, then th is flag is set.

02

Head
Address

HD

This flag is used to indicate the state of the head
at Interrupt.

01
00

Unit Select 1
Unit Select 0

US 1
'US 0

These flags are used to indicate a Drive Unit
Number at Interrupt

07

End of
Cylinder

EN

When the FDC tries to access aSector beyond
the final Sector of a Cylinder, this flag is set.

06
05

Date Error

DE

When the F DC detects a CRC error in either the
10 field or the data field, this flag is set.

04

Over Run

OR

If the FDC is not serviced by the main-systems
during data transfers, within a certain time
interval, this flag is set.

03
02

No Data

NO

During execution of READ DATA, WRITE
DELETED DATA or SCAN Command, if the
FDC cannot find the Sector specified in the lOR
Register, this flag is set.

STATUS REGISTER 1

Not used. This bit is always 0 (low).

Not used. Th is bit always 0 (low).

During executing the READ 10 Command, if
th e F DC can not read th e 10 fi el d with out an
error, th en th is fl ag is set.
During the execution of the READ A Cylinder
Command, if the starting sector cannot be
found, then this flag is set.

257

p.PD765
BIT
NO.

NAME

SYMBOL

I

DESCRIPTION

STATUS REGISTER
IDENTIFICATION (CONT.)

STATUS REGISTER 1 (CONT.)
D1

Not
Writable

NW

During execution of WRITE DATA, WRITE
DELETED DATA or Format A Cylinder Com·
mand, if the FDC detects a write protect signal
from the FDD, then this flag is set.

DO

Missing
Address
Mark

MA

Ilth,e FDC cannot detect the ID Address Mark
after encountering the index hole twice, then
this flag is set.
If the FDC cannot detect the Data Address Mark
or Deleted Data Address Mark, th is flag is set.
Also at the same time, the MD (Missing Address
Mark in Data Field) of Status Register 2 is set.
STATUS REGISTER 2
Not used. This bit is always

D7

-

a (low).

D6

Control
Mark

CM

During executing the READ DATA or SCAN
Command, if the F DC encou nters a Sector wh ich
contains a Deleted Data Address Mark, this
flag is set.

D5

Data Error in
Data Field

DD

If the FDC detects a CRC error in the data field
then th is flag is set.

D4

Wrong
Cylinder

WC

This bit is related with the ND bit, and when the
contents of C on the medium is different from
that stored in the IDR, this flag is set.

D3

Scan Equal
Hit

SH

During execution, the SCAN Command, if the
condition of "equal" is satisfied, th is flag is set.

D2

Scan Not
Satisfied

SN

During executing the SCAN Command, if the
FDC cannot find a Sector on the cylinder which
meets the condition, then this flag is set.

D1

Bad
Cylinder

BC

This bit is related with the ND bit, and when the
content of C on the medium is different from
that stored in the I DR and the content of C is
FF, then this flag is set.

DO

Missing
Address Mark
in Data Field

MD

When data is read from the medium, if the FDC
ca'1not find a Data Address Mark or Deleted
Data Address Mark, then this flag is set.

D7

Fault

FT

This bit is used to indicate the status of the
Fault signal from the FDD.

D6

Write
Protected

WP

This bit is used to indicate the status of the
Write Protected signal from the FDD.

D5

Ready

RY

This bit is used to indicate the status of the
Ready signal from the FDD,

D4

Track

TO

This bit is used to indicate the status of the
Track a signal from the FDD.

D3

Two Side

TS

Th is bit is used to indicate the status of the
Two Side signal from the FDD,

D2

Head Address

HD

This bit is used to indicate the status of Side
Select signal to the FDD.

D1

Unit Select 1

US 1

This bit is used to indicate the status of the Unit
Sel ect 1 signal to the F DD.

DO

Unit Select

a

usa

This bit is used to indicate the status of the Unit
Select a signal to the F DD.

STATUS REGISTER 3

a

SP765-1-80-CA T

NEC

NEe Microcomputers, Inc.

ILP0781

DOT MATRIX PRINTER CONTROLLER
DESCRIPTION

The ,uPD781 is an LSI Dot Matrix Printer Controller chip which contains all the
circuitry and control functions for interfacing an 8-bit processor to the Epson model
512, 522, and 542 Dot Matrix Printers_ These printers are capable of printing 40
columns per row with a 5 x 7 dot matrix_ The ,uPD781 is ideally suited for low-cost
Electronic Cash Registers (ECR) and Point of Sale (POS) systems because it frees
the processor from direct control of the printer and simplifies I/O software.
There are nine separate instructions which the ,uPD781 will execute_ Each of these
instructions requires only a single 8-bit byte from the processor to be executed.
Upon receipt of the instruction the ,uPD781 assumes control of the printer, increments
the print he.ad, activates the print solenoids, performs line feed on either receipt or
journal registers (or both), and performs these operations for an entire print line of
40 columns.
The ,uPD781 contains its own on-board character generator of 96 symbols_ It contains a 40 column printer buffer and is capable of supplying status information to the
host processor on both the controller itself as well as the printer. Characters to be
printed are written into the ,uPD781 by the processor, and after the receipt of 40
characters the entire row is printed out with a single print command.

F EA TU R ES

• Compatible with most Microprocessors including 8080A, 8085A, ,uPD780 (Z80™)
• Capable of I nterfacing to Epson Model 512, 522, or 542 Printers
• Print Technique - Serial Dot Matrix
• Print Font - 5 x 7 Dot Matrix
• Column Print Capacity: 40 Columns for Model 512 and 522; 18 Columns for
Receipt and 18 Columns for Journal-Model
• Buffer Capacity: 40 Columns - Model 512 and 522; 2 to 18 Columns - Model 542
• 96 Character Set (Alphanumerics Plus Symbols)
• Print Speed - Approximately 3 Lines/sec (Bidirectional Printing)
• Paper Feed: Independent or Simultaneous; Receipt and Journal Feed; Fast Feed
• Stamp Drive Output - Also Cutter Drive Output and Slip Release for Model 522.
• Sense Printer Status: Validation (Left/R ight) Sensor - Model 512 and 522; TOF,
BOF Sensor - Model 542; Low Paper Detector - Model 512 and 522
• On-Board 6 MHz Oscillator (External Crystal Required)
• Operates from a Single +5V Power Supply (NMOS Technology)
• Available in 40-Pin Plastic Package

PIN CONFIGURATION

PIN

NAM~

RL

RL

X1
X2
RESET

RR

VCC3

CS
RO

Reset
Chip Select
Read

VSS2
RO

C/O

Command/Data

WR

Write

00-7
PR1-i'R7
VDR/BOF
VDL!TOF

Print Solenoids
Validation (RJ!BOF Sensor

X1,X2
RESET

cs

C/O

WR
OPEN1

DO
01
02
03
04
05

06
07
VSS1

VOLITOF
VOR/BOF

Reset Signal (LI
Reset Signal (R)
Crystal Inputs

Data Bus

Validation (LI/TOP Sensor

NE

Low Paper Detector

VCC2
OPEN2

rvrro

Motor Drive

SC'R

Slip Release

i'R4

STM

PR2

PFJ
PFR

Stamp
Paper Feed Journal
Paper Feed Receipt

PR1

TiM

Timing Signal

PR3

TM: Z80 is a registered trademark of Zilog, Inc.

259

fLPD781
BLOCK DIAGRAM

" +---1
c/o

+---1

AD

READ/WRITE

CONTROL

f--<'-'~

VDLlTOF

WR+-~-1

PIN
NUMBER

SYMBOL

2,3

X1,X2

NAME
External

I/O

I

Crystal
Input
4

RESET

Reset

FUNCTION
This is a connection to external crystal

(Frequency: 6 MHz). X1 could also be
used as input for external oscillator.

I

The Reset signal initializes the I'PD781.
When RESET = 0, the buffer and register
contents are:
Bus Buffer - (lOM-1, IOB=PSR=OI.
Column Buffer - All characters in this
buffer become 20(16) (ASCII).
Column Buffer Pointer - It indicates

the left side of the buffer.
Column Capacity - 40 columns.
Print Head - Current Position.

6

CS

Chip Select

I

If the Chip Select is 0 when the data bus
becomes active, it enables the transfer of
data between the processor and the
I'PD781 via the data bus. If it is 1, the
data bus goes into High-Impedance state
(inactivel. However, the operation of the

printer is not affected when CS=1.
8

RD

Read

I

The Read Control Signal is used to read
controller status or printer status, to the
host processor. When RD=1, status information is presented.

10

WR

Write

I

The Write Control Signal is used to'write
commands or print data to the I'PD781.
When'WR=O, data on the data bus is written into the .uPD781.

9

C/D

Command/
Data Select

I

The C/D Select is used to indicate what
kind of data is being input/output on the

data bus by the host processor. When
C/D=1 in Read Operation, it is a Controller
Status and in Write Operation it gives
commands. When C/D=O in Read Operation it is a Printer Status and in Write
Operation it is print data.

PIN IDENTIFICATION

fLPD781
PIN IDENTIFICATION
(CaNT.)

PIN
I/O
NUMBER

SYMBOL

FUNCTION

NAME

12-19

00-7

Data Bus

5.26.
40

VCC1-3

DC Power

7.20

VSS1-2

Signal
Ground

11.25

OPEN1_2

No
Connection

21-24,
35-37

PR1-PR7

Print
Solenoid

I/O
3-State

It is an a-bit bi-des transferred from the
Buffer Output Control.ler.
,
Outputs the CSR based on the Blinking Time etc. at the posit,ion indicated by Cursor Address.

Light Pen Register
Memorizes a row address and colum~ address when the L PEN signal is input. By using READ
LIGHT PEN instruction, the CPU can read the contents.

ABSOLUTE MAXIMUM
RATINGS*

Operating Temperature . . . . . : . . . :. . . . . . . . . . . . . . . . . . ", .. · .. " . ",O°C to +700 C

Storage Temperature
All Output Vpltages
All Input Voltages.
Supply Voltage VCC

. .. ,-'65°'C to +125° C
. · , . , . -0.5 to +7 Volts
. · . . . . -0.5 to +7 Volts
, · . . . . -0.5 to +7 Volts

.. ' . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. , . "',,' " . . . . . . . . . . . . . . . . . . . . . .
, ..... "','" . " . . . . . . . . . . . . . . " ...
. . . . . . . . . . . . : . . . . . . . . . . . . . . . '..

COMMENT: Stress above those listed under ,"Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional oper~tion of the device at these or
any other conditions above,those indicated in the operational sections of this specification is not
implied. Exposure to aboo'lute maximum rating conditions for extenpad periods may affect device
reliability.

DC CHARACTERISTICS

Ta =o°c to +70°C; VCC = +5V ± 5%
PARAMETER

SYMBOL

Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage

VIL
VIH
VOL
VOH

Low Level Input Leakage
High Level Input Leakage
Low Level Output Leakage
High Level Output Leakage
Power Supply Current

IlL
IIH
IOL
IOH
ICC

LIMITS,
MIN TYP
-0.5
2.2,

UNIT

MAX
0.8
VCC + 0.5
0.45

2.4

VCC
-10

V
V
V
V
"A
p.A

+10
-10
+10

"A
p.A

TEST
CONDITIONS

IOL-l.6 mA
OBO_7: IOH - -150 "A.
All Others: -80 "A
VIN = o.V
VIN - VCC
VOUT =OV
VOUT -VCC

mA

90

CAPACITANCE
LIMITS
PARAMETER

SYMBOL

MIN

MAX

UNIT

Input Capacitance

CIN

10

pF

Output Capacitance

COUT

20

pF

TEST CONDITIONS
fc = 1 MHz,
All Pins Except Pin
Under Test Tied to
AC Ground

II

J'PD3301

PARAMETER

SYMBOL

LIMITS
MIN

MAX

UNIT

Clock Cycle !"PD3301-1

tCY

0.5

10

Time

"S

tCY

0.38

10

"s

J"PD3301'2

TEST
CONDITIONS

Clock High level

tCH

150

Clock low level

tCl

150

1000

ns

Clock Rise Time

tCR

5

30

ns

Clock Fall Time

tCl

5

30

ns

Output Delay from C ClK t

tCOl

0

150

ns

lTTl + 15 pF:
HRTC, CCO-7

400

ns

lTTl + 15 pF:
Except HRTC, CCO.7

Output Delay
from C ClK t

"PD3301-1

tC02

"PD3301-2

tC02

ns

300

ns

"S

tE

2tCY + 200

ns

tCY;;' 400

tE

1

tCY < 400 "s

AO, CS Set Up Time to WR

tAW

0

"s
ns

AO, CS Hold Time to WR

tWA

0

ns

WR Pulse Width

tww

200

ns

Data Set Up Time to WR

tow

150

ns

Data Hold Time to WR

two

30

ns

DACK

tKW

0

ns

tWK

0

ns

tKQ

0

Command Cycle Time

j

Set Up Time to WR

DACK t Hold Time to WR
DRQ Delay

fro~

DACK

j

INT Delay from WR t

tWI

INT Delay fromC ClK t

tCI

AO, CS Set Up Time to RD

tAR

AD, CS Hold Time to RD
RD Pulse Width
Data Access Time from RD

j

tCY + 20

250

ns

lTTl + 50 pF

2tCY + 300

ns

lTTl + 50 pF

300

ns

lTTl + 50 pf

0

ns

tRA

0

ns

tRR

300

tRD

0

Data Float Delay from RD t ' tOR

ns
250

, ns

Cl = 100 pF

150

ns

Cl = 100 pF

ns

Cl = 15pF

20

TIMING WAVEFORMS

CLOCK AND OUTPUT DELAY
~---------tCY----------~~

CCLK

'CR

HATC

-----+---.

,CC O-7 -";"---f--J

LCO_3, RVV
VRTC, H L G T - - - - - f - - - - .
VSP, GPA

SLo. SL'2
CSR
'C02

AC CHARACTERISTICS

'C02

p;PD3301
READ OPERATION

TIMING WAVEFORMS
(CaNT.)
.

RO---,---"'\I

OBO·7--~----

DMA. INTERRUPT AND WRITE OPERATION

'e
AO

cs

)
I-twA_

~

\

,

f---tww-:----

-

'e

1-r-'oiN~

)

OBO·7

-

I~Kw"
OACK

two I--

'WK

\
t-"tKO-

!--'KOORO

t--

\

II

J
__ 'WI

CC~K

\_287

J'P03301

From the external memory which contains the information about characters and attributes, the
data 'is transferred to the Row Buffer under the control of ,uPD8257 DMA Controller. The data
read from the Row B'uffer are Video Control Outputs and ROM Address Signal Outputs toward
External Character Generator., The ,uPD3301 also outputs horizontal and vertical retrace signals.

SYSTEM BUS

R

r

G

B

I

~

~

CS---.

RD

WR

L PEN
C ClK

VRTC
RVV
CSR
HRTC
HLGT
GPA

CHARACTER
GENERATOR

~LCO-3

Sl12
VSP
Slo

ITCCO-7

~

,uPD3301
CRTC

INT
... DBO_7

DRQ
MEMR

I"

ts HLDA RESET
A.

DBO·7 AO-3
IIOR

100-

"'H.

DACK

MEMW

A5 - A15 HLDR

IIOW

<1>2

..
r

.

VIDEO
H. DRIVE
V. DRIVE

l"- BRIGHTNESS

n
AO

rrr-

HI-SPEED
VIDEO INTERFACE

COlO~

MEMORY

SYSTEM CON F I GU RATION

,uPD8257
DMA CONTROLLER

},PD3301

PACKAGE OUTLINES
tlPD3301 C/D

Plastic

ITEM

MILLIMETERS

INCHES

A
B
C
D
E
F
G
H
I
J
K
L

51.5 MAX.
1.62 MAX.
2.54 ± 0.1
0.5 ± 0.1
48.26 ± 0.1
1.2 MIN.
2.54 MIN.
0.5 MIN.
5.22 MAX.
5.72 MAX.
15.24 TYP.
13.2 TYP.
+0.1
0.25 -0.05

2.028.MAX.
0.064 MAX.
0.10 ± 0.004
0.Q19 ± 0.004
1.9 ± 0.004
0.047 MIN.
0.10MIN.
0.019 MIN.
0.206 MAX.
0.225 MAX.
0.600 TYP.
0.520 TYP.

M

0010 +0.004
.
-0.002

G

F

r--------E---,--------I
Ceramic

ITEM

MILLIMETERS

INCHES

A
B
C
D
E
F
G
H
I
J
K
L
M

51.5 MAX.
1.62 MAX.
2.54 ± 0.1
0.5 ± 0.1
48.26 ± 0.1
1.02 MIN.
3.2 MIN.
1.0 MIN.
3.5 MAX.
4.5 MAX.
15.24 TYP.
14.93 TYP.
0.25 ± 0.05

2.03 MAX.
0.06 MAX.
0.1 ± 0.004
0.02 ± 0.004
1.9 ± 0.004
0.04 MIN.
0.13MIN.
0.04 MIN.
0.14 MAX.
0.18 MAX.
0.6 TYP.
0.59 TYP.
0.01 ± 0.0019

II
SP330 1-1 0-79-CA T

289

NOTES

290

NEe

NEe Microc~mputers, Inc.

p.PD7001

8-BIT SERIAL OUTPUT AID CONVERTER
DESCRIPTION

ThejlPD7001 is a high performance, low power 8-bit CMOS AID converter which
contains a 4 channel analog multiplexer and a digital interface circuit for serial
data 1/0. The AID converter uses a successive approximation as a conversion
technique.

AID SQnversion system can be easily designed with the IlPD7001 including all
circuits for AID convertion. The IlPD7001 can be directly connected to 8-bit or
4-bit microprocessors.

F EATU RES

• Single chip AID Converter
•
•
•
•
•
•
•
•
•

PIN CONFIGURATION

Resolution: 8 Bit
4 Channel Analog Multiplexer
Auto-Zeroscale and Auto-Fullscale Corrections without any external components
Serial Data Transmission
High Input Impedance: 1,000 Mn Single +5V Power Supply
Conversion Speed: 112 p.s (Typ.)
Low Power Operation
Available in 16 Pin Plastic Package
PIN NAMES

EOC

V DD

EOC

ns

SCK to SO, RL - 3K,
CL=loopF

ns

es to High Impedance SO

ns

200

At a low level of CS the data is exchanged with external digital circuit and at a high level of CS the
J,l.P07001 performsA/O conversion and does not accept any external digital signal. However, 5 pulses
of internal clock are needed before digital data output and then the pPD7001 remains at the pre'vious state of high level CS.
The rating corresponds to the 5 pulses of clock signal.

tSCSK 1M in. I " SliCK

@

DC CHARACTE R ISTICS

The serial data delay time depends on load capacitance and pull-up resistance.

Ta = 25°C ± 10%; VDD = +5V ± 10%; VREF = 2.5V; fCK = 500

k:~z.

LIMITS
PARAMETER

TEST
CONDITIONS

UNIT

SYMBOL
MIN

TYP

MAX

8

Resolution

8

Bit

O.B

%FSR

VOO" 5V
VREF

Non Linearity

2

Full-Scale Error

2.25 to 2.75V

LSB
ppmtC

30

Full-Scale Error Temp.
Coefficient

~

VOO." 5V
VREF "" 2.25 to 2.75V

2

Zero Error

ppmtc

30

Zero Error Temp.
Coefficient

LSB

Total Unadjusted
Error 1

TUE 1

2

LSB

VOO" 5V

Total Unadjusted

TUE2

2

LSB

VOD

VREF

Error 2

~

~

2.25 to 2.75V

4.5 to 5.5V

VAEF" 2.5V

Analog I nput Voltage

V,

Analog Input Resistance

AI

Supply Voltage Rejection

SVA

Conversion Time

teoNV

Clock Frequency Range

ICK

-Clock
- Frequency
Distribution

0

VREF

1000
1
112
0.01

0.5
±5

':)'fCK

0.65
20

V

CD

MI1

V, =OtoVDD

LSB

VOO:=' 4.5 to 6.DV

.s

@

MHz
%

R

:=.

47 Kil, C '" 20 pF

liCK ~ 0.5 MH,I

'--

Serial Clock Frequency

ISCK

High Level Voltage

V,H

Low Level Voltage

V,L

Digital Input Leakage

II

1

MHz

@

V

3.6
1.4
1.0

10

V
.A

V, ;: VSS to +lDV

V

'OL:=' 1.7 rnA
VO:=' +10V

Current
Low Level Output
Voltage

VOL

Output Leakage Current

'L

1.0

10

.A

Power Dissipation

Pd

5

15

mW

Notes:

0.4

CD All digital ~utputs are put at a high level when V, > VAEF'
@

The

AID conversion is started with

CS going to a high

level and at the final step of the first

AID

conversion the EOe is at a low.
The conversion time

is:

tCONV ·14 x 4 x 1/fCK

@

For fSCK > 500 kHz, the load capacitor (stray capacitance included) and the pull·up resistor which
are connected to serial output are required to be not more than 30 pF and 4 Kn respectively.

293

,,"PD7001
DIGITAL DATA OUTPUT

TIMING WAVEFORMS

L-J~------~fI~-------------

'HECSf4--i

I

5

«

'SCSK H 'WHKI • -I •• IWLK
II

1JLr-

SCK,

--I f-- ' D K O - i I--'FCSO

SO------"I'O-'\j,....-M-SB-C~

LSB I

ANALOG CHANNEL SELECTION

'sCSKH
SCK
H'SIK
H'HKI
SI:::::::::::::X'-__D...;1...;@_2_---J~""_D.;.O_@__J- - - - - I---J'HKDL
DL
----------------~ ~----HWHDD
CD The address set can be performed simultaneously with the digital data

n

Notes:

outputting.

®

Analog Multiplexer Channel Selections:
Analog Input Address

DO

01

AO

L

L

Al

H

L

A2

L

H

A3

H

H

@ Rise and fall time of the above waveforms should not be more than 50 ns.
PACKAGE OUTLINE
J.lPD7001C

~---------A--------~

\"ITEM

MILLIMETERS

INCHES

A

19.4 MAX.

0.76 MAX.

no3

0.81

2.54

~IO

~5

0.02

17.78

~70

1.3

0.051

2.54 MIN.

0.10 MIN.

0.5 MIN.

0.02 MIN.

4.05 MAX.

0.16 MAX.

4.66 MAX.

0.18 MAX.

7.62

0.30
0.25

6.4
M

~25

+0.10

-0.06

0.01

SP7001-1-80-CAT

294

!\fEe

NEe Microcomputers, Inc.

p.PD7002

12-BIT BINARY AID CONVERTER
DESCRIPTION

FEATURES

The /.IPD7002 is a high performance, low power, monolithic CMOS AID converter
designed for microprocessor applications. The analog input voltage is applied to one
of the four analog inputs. By loading the input register with the multiplexer channel
and the desired resolution (8 or 12 bits) the integrating AID conversion sequence is
started. At the end of conversion EOC signal goes low and if connected to the interrupt line of microprocessor it will cause an interrupt. At this point the digital data can
be read in two bytes from the output registers. The /.IPD7002 also features a status
register that can be read at any time.

• Single Chip CMOS LSI
• Resolution: 8 or 12 Bits
• 4 Channel Analog Multiplexer
• Auto·Zeroscale and Auto·Fuliscale Corrections without any
External Components
• High Input Impedance: 1000 MHz
• Readout of Internal Status Register Through Data Bus
• Single +5V Power Supply
• Interfaces to Most 8-Bit Microprocessors
• Conversion Speed: 5 ms
• Power Consumption: 20 mW
• Available in a 28 Pin Plastic Package

PIN CONFIGURATION

PIN NAMES

EOC

Xo

XO,XI

Clock Input

AO

VSS

TTL Ground

RO

CI

Integrating Capacitor

5

WR

GO

Guard

cs

VREF

Reference Voltage

DO

GNo

Analog Ground

01

CH3

Analog Channel 3

02

CH2

Analog Channel 2

03

CHI

Analog Channel I

CH2

04

CHO

Analog Channel 0

CHI

05

Voo

TTL Voltage (+5V)

CHO

06

00-0 7

Data Bus

07

CS

Chip Select

WR,Ro

Control Bus

AoAI

Address Bus

EOC

End of Conversion Interrupt

2

AI

Vss

3

CI

4

GO

XI

CI

6

GO

7

VREF

8

GNO

9

/.IPD
7002

CH3

VOO

II

Rev/1

295

c

JoLPD7002
0,0-

n

_r---

0200,0000-

n

~ I MPX OECODE

'I

0.0-

0,0-

c
H

n

'-0

I

-

BLOCK DIAGRAM

VREF

I

L.OW BYTE

-91
- .....
I
I II I

A/CANALOG
SECTION

~

r-

r-o ,

REGISTER '

+

INTEGRAT ING
CAPACIT OR
ANALOG
GNO

CONVERSION
DATA

CONTROL
MODE
DATA

REGISTER

fl

rViR 0 - rADO- rADO- r',0- rr050-

-

1218

12 SIT OATA
SeQUENCE

CONTROL
SECTION

AID DIGITAL
SECTION

Eoeo-

1

VOO

I

REGISTER

THREE

STATE
BUFFER

n

ANALOG
MUL.TIPLEXER

AND 12/8 BIT

HIGH BYTE

-

C

2

I I I I

t/QSECTtQN

)I

0.0- 0.0- -

c
H

r-o

Vss

=!:$

II

DC CHARACTERISTICS

T. = 25 ± 2'C; VOO = +5 ± O.25V. VREF = +2,50V.fCK = 1 MHz
LIMITS
PARAMETER

SYMBOL

MIN

Resolution

TYP

MAX

12

Non Linearity

0.025

TEST
CONDITIONS

Bits

0.08

%FSR
%FSR

Fullscale Error

0.025

0.08

Zeroscale Error

0,05

0,08

Fullscale Temperature

UNIT

%FSR

VREF • 2.25 to 2.75V;

'0

PPMfc

VOO = 5V

'0

PPMfc

Coefficient

Zeroscale Temperature
Coefficient
Analog Input Voltage

VIA

0

VREF

V

Range
Analog Input

rnn

1000

RIA

VIA = VSS to VOO

Resistance
Total Unadjusted
Error 1

TUE 1

C.05

0.08

%FSR

VREF = 2.25 to 2.75V
VOO = 5V

Total Unadjusted
: Error 2

TUE2

0.05

0.08

%FSR

VREF =2,5V
VOO = 4.75 to 5.25V

50

"A

Clock Input Current

IXI

Clock Input High Level

VXIH

5

V

VOO

-'.6

Clock Input Low Level

VXIL

High Level Input
Voltage

VIH

Low Level Input
Voltage

VIL

High Level Output
Voltage

VOH

Low Level Output
Voltage

VOL

Digital Input Leakage
Current

II

,

10

"A

VI = Vss to VOO

I Leak

1

10

"A

Vo = VSS to VOO

15

25

rnW

fCK.;;1 MHz

High-Z oUtput
Leakage Current

Power Dissipation

296

VSS
+1.4
2.0
0.8
3.5
0.4

V
V

Ta '" 0° to 70°C

V

Ta '" 0° to 70°C

V

10 =-2 rnA

V

10 =+2 rnA

"

Pd

Jl.PD7002
ABSOLUTE MAXIMUM
RATINGS*

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . oOe to +70 o e
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -65°C to +125°e
All Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to VDD + 0.3 Volts
Power Supply .; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +7 Volts
Power Dissipation .......................................... 300 mW
Analog GND Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS ± 0.3 Volts
COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. Thi;is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this, specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device

reliability.

*Ta

AC CHARACTER ISTICS

25°C

=

Ta = 25° ± 2°C; VDD = +5 ± 0.25V; VREF = 2.5V; fCK. = 1 MHz; CINT = 0.033 "F

PARAMETER
Conversion Speed 112 bit)
Conversion Speed 18 bit)
Clock Fr.equency Range
Integrating CapacitorValue
Address Setup Time
C$, AD, A l ..to WR
Address Setup Time·
es, AQ. AI, to RD
Address Hold Time WR to
es,AO,Al
Address Hold Time R 0 to
es,AO,Al
Low Level WR Pulse Width
Low Level R D Pulse Width
Data Setup Time Input
Data to WR
Data Hold Time WR to
Input Data

SYMBOL

Output Delay Time RD to
Output Data
Delay Time to High Z
Output RD to Floating
Output
Note:

K--I
.....-.

~RA

)(
tRR
~

~

II

7

tAR

--- - - - _./ ~
--- - - tRD

-'~

-r tDF -

- --

-

-297

JLPD7002
CONTROL TERMINALS
CS

RD

WR

A,

AO

MODE

INTERNAL
FUNCTION

H

x

x

x

x

Not selected

-

L

H

H

x

x

-

-

L

H

L

L

L

Write mode

DATA INPUT-OUTPUT
TERMINALS

CONTROL TERMINAL
FUNCTIONS

High irr:tpedance

Data latch
A/O.tart

Input statu., 0" 00.-= MPX address
03 = S'bit/12 bit conversion
designation.

CD

-

-

L

H

L

L

H

L

H

L

H

L

L

H

L

H

H

Test mode

Test status

1nput status

L

L

H

L

L

Read mode

Internal status

07 = EOC, 06 = BUSY, 05 = MSS,

High impedance

®

04 = 2nd MSB, 03 = S/12,
02 = not defined, 01 = MPX,
00= MPX
L

L

H

H

L

Read mode

High data byte'

L

L

H

L

H

Read mode

Low data byte

L

L

H

H

H

Read mode

Low data byte

Notes:

07-04 = 9th - 12th bit, 03-00 = L

tPD8156'_ _ _ _J

101M

ALE

WRITE CYCLE

ce
(>tPD8155)
OR

CE
I>tP081561_ _ _...J

I DIM

ADo-,
----~~------~-+~~~----------~~ALE

302

TIMING WAVEFORMS

f'PD8155/8156
TIMING WAVEFORMS
(CaNT.)

STROBED INPUT MODE

----

SF

t5BF

INTR

INPUTOATA----------~F_--_1--~,_-------------------------------
FROM PORT

----------~F---~--_f~-------------------------------STROBED OUTPUT MODE

SF

________________J,

INTA

OUTPUT DATA

TOPORT ______________________~~------------------------------

BASIC INPUT MODE

RO
INPUT

~

-=t.~RP
~

~
J.4-tPR

~~-----------

DATA BUS : : : : : :

.

:x____________

BASIC OUTPUT MODE

-?=

OUTPUT __________________

~

TIMER OUTPUT
LOAD
COUNTER

FROMClR
COUNT

--i

I

RELOAD

FC.l'ci',n~~ - i
I

I

TIMER-IN

~
IPULSEI ____________
TIME-OUT
ISQ.WAVEI- -

-

~r7J:!::=:::!~--~~

-COUNTDOWN FROM 3 TO 0
uPD8155/8156
,uPD8165-2/8156-2
320 ns MIN.
200 ns MIN.
30 ns MAX.
30"$ MAX.
tRISE & tFALL
80 nl MIN.
40 ns MIN.
120 ns MIN.
70 ns MIN.
'2
TlMER·IN to TIMER-OUT LOW ITO BE DEFINED).
'Tl
TIMER-IN to TIMER:OUT HIGH (TO BE DEFINED).
'TH

teye

t,

303

f'PD8155/8156

The Command Status Register is an 8-bit register which must be programmed before
the ~PD8155/8156 may perform any useful functions. Its purpose is to define the
mode of operation for the three ports and the timer. Programming of the device may
be accomplished by writing to I/O address XXXXXOOO (X denotes don't care) with a
specific bit pattern. Reading of the Command Status Register can be accomplished by
performing an I/O read operation at address XXXXXOOO. The pattern returned will
be a 7-bit status (eport of PA, PB and the Timer. The bit patterns for the Command
Status Register are defined as follows:
COMMAND STATUS WRITE

I

TMl

TM2

IEB

PB

lEA

PA

where:
TM2·TMl

Define Timer Mode

IEB

Enable Port B Interrupt

lEA

Enable Port A Interrupt

PC2"PCl
PB/PA

Define Port C Mode
Define Port B/A as In or Out



ALT 4 <2>

pca

IN
IN
IN
IN
IN
IN

OUT
OUT
OUT
OUT
OUT
OUT

AINTR
A BF
A!ffii
OUT
OUT
OUT

AINTR
ABF
Am
B INTR
B BF
Bm

PCl
PC2

PC3
PC4
PC5

Notes: (j) PB/PA Sets Port B/A Mode:

a· Input; 1 =Output

~ In AL T 3 and AL T 4 mode the control signals are initialized as follows:

INPUT

OUTPUT

ffi (Input Strobel·

Input Control

Input Control

INTR (Interrupt Requestl

Low
low

High

CONTROL

BF (Buffer Fulll

304

Low

COMMAND STATUS
REGISTER

ILPD8155/8156

COMMAND STATUS
REGISTER (CaNT.)

COMMAND STATUS READ
TI

INTE

B

B

BF

INTR
B

INTE
A

A
BF

INTR
A

Where the function of each bit is as follows:
TI

Defines a Timer Interrupt. Latched high at TC and
reset after reading the CS register or starting a new
count.

INTE B/A

Defines If Port B/A Interrupt is Enabled.
High = enabled.

B/A BF

Defines If Port B/A Buffer is Full-Input Mode or
Empty-Output Mode. High = active.

INTR B/A

Port B/ A Interrupt Request. High

= active.

The programming address summary for the status, ports, and timer are as follows:
I/O Address

Number of Bits

XXXXXOOO

8
8
8
6
8
8

XXXXXOOl
XXXXX010
XXXXXOll
XXXXX100
XXXXX101

TI ME R

Function
Command Status
PA
PB
PC
Timer-Low
Timer-High

The Internal Timer is a 14-bit binary down counter capable of operating in 4 modes. Its
desired mode of operation is programmable at any time during operation. Any TTL
clock meeting timer in requirements (See AC Characteristics) may be used as a time
base and fed to the timer input. The timer output may be looped around and cause an
interrupt or used as I/O control. The operational modes are defined as follows and
programmed along with the 6 high bits of timer data.

M2

Ml

Operation

0

0

High at Start, Low During Second Half of Count

0

1

Square Wave
(Period = Count Length, Auto Reload at TC)

1

0

Single Pulse at TC

1

1

Single Pulse at TC with Auto Reload

11
305

p.PD8155/8156
TIMER (CaNT.)

Programming the timer requires two words to be written to the J,lPD8155/8156 at I/O
address XXXXX100 and XXXXX10l for the low and high order bytes respectively.
Valid count length must be between 2H and 3FFFH. The bit assignments for the high
and low programming words are as follows:
Word
High Byte
Low Byte

Bit Pattern

I/O Address

I
I I
I
I I I I I I I I I
M21 Ml

T131 T121 Tll

Tl0

T91 T8

XXXXX10l

T1

T5

T2

Tl

XXXXX100

T6

T4

T3

TO

The control of the timer is performed by TM2 and TMl of the Command Status Word.

Note that counting will be stopped by a hardware reset and a START command
must be issued via the Command Status Register to begin counting. A new mode
and/or count length can be loaded while counter is counting, but will not be
used until a START command is issued.

i
A
i r~1
HJ~'
------II '
III II
"
,=tt
M
~Bt:
;:r.: -j c t;
-b
I
0° - 15°

PACKAGE OUTLINE
J,lPD8155C
J,lPD8156C

I-

Plastic
ITEM

MILLIMETERS

A

51.5 MAX

8
C
0

E
F
G

INCHES
2.028 MAX

1.62
2.54 ± 0.1

0.064

0.5 ± 0.1

0.019 ± 0.004

48.26

0.10 ± 0.004

1.2MIN

1.9
0.047 MIN

2.54 MIN

0.10MIN

H

0.5 MIN

0.019 MIN

I

5.22 MAX
5.72 MAX
15.24

0.206 MAX

13.2

0.520

J
K
L
M

0.25

+ 0.1
0.05

0.225 MAX
0.600
0.010 + 0.004
- 0.002

SP8155/B156-1-BO-CAT

306

NEe

NEe Microcomputers, Inc.

,.,.PB8212

EIGHT·BIT INPUT/OUTPUT PORT

DESC R I PTI ON

The tlPB8212 input/output port consists of an 8-bit latch with three-state output
buffers along with control and device selection logic. Also included is a service request
flip·flop for the control and generation of interrupts to the microprocessor.
The device is multimode in nature and can be used to implement latches, gated buffers
or multiplexers. Thus, all of the principal peripheral and input/output functions of a
microcomputer system can be implemented with this device.

FEATURES

• Fully Parallel8·Bit Data Register and Buffer
• Service
•

Requ~st

Flip·Flop for Interrupt Generation

Low Input Load Current - 0.25 mA Max.

• Three State Outputs
• Outputs Sink 15 mA
• 3 ..65V Output High Voltage for Direct Interface to 8080A Processor
• Asynchronous Register Clear
•

Replaces Buffers, Latches and Multiplexers in Microcomputer Systems

•

Reduces System Package Count

• Available in 24-pin Plastic and Cerdip Packages

PIN CONFIGURATION

vcc

0s1
MD

2

Dll

3

iNT

DOl
DI2

5

D02

s

Dla

7

DOa

S

tl PB
8212

PIN NAMES

22

DiS

21

DOS

011 - DiS

Data In

20

DI7

DOl - DOS

Data Out

19

D07

DSI. DS2

Device Select

IS

DiS

MQ

Mode

17

DOS

STB

Strobe

DI4

9

DI5

INT

Interrupt (Active Low)

D04

10

D05

CLR

Clear (Active Low)

ern

STB
GND

12

DS2

Rev/1

307

JLPB8212
Data Latch

FUNCTIONAL DESCRIPTION

The 8 flip-flops that compose the data latch are of a "0" type design_ The output (Q)
of the flip-flop follows the data input (0) while the clock input (C) is high. Latching
occurs when the clock (C) returns low.
The data latch is cleared by an asynchronous reset input (CLR).
(Note: Clock (C) Overrides Reset (CLR).)
Output Buffer
The output of the data latch (Q) are connected to three-state, non-inverting output
buffers. These buffers'have a common control line (EN); enabling the buffer to transmit the data from the outputs of the data latch (Q) or disabling the buffer, forcing the
output into a high impedance state (three-state).
This high-impedance state allows the designer to connect the /lPB8212 directly to the
microprocessor bi-directional data bus.
Control Logic
The /lPB8212 has four control inputs: OSl, OS2, MO and STB. These inputs are
employed to control device selection, data latching, output buffer state and the
service'request flip-flop.
DS1. DS2 (Device Select)
These two inputs are employed for device selection. When OSl is low and OS2 is high
(OSl • DS2) the device is selected. In the selected state the output buffer is enabled and
the service request flip-flop (SR) is asynchronously set.
Service Request Flip-Flop (SR)
The (SR) flip-flop is employed to generate and control interrupts in microcomputer
systems. It is asynchronously set by the CLR input (active low). When the (SR) flipflop is set it is in the non-interrupting state.
The output (Q) of the (SR) flip-flop is connected to an inverting input of a "NOR"
gate. The other input of the "NOR" gate is non-inverting and is connected to the
device selection logic (OSl • OS2). The output of the "NOR" gate (I NT) is active
low (interrupting state) for connection to active low input priority generating circuits.
MD (Mode)
This input is employed to control the state of the output buffer and to determine the
source of the clock input (C) to the data latch.
When MO is in the output mode (high) the output buffers are enabled and the source
of clock (C) to the data latch is from the device selection logic (OSl • OS2).
When MO is in the input mode (low) the output buffer state is determined by the
device selection logic (OSl • OS2) and the source of clock (C) to the data latch is
the STB (Strobe) input.
STB (Strobe)
STB is employed as the clock (C) to the data latch for the input mode (MO = 0) and
to synchronously reset the service request flip-flop (SR).
Note that the SR flip-flop triggers on the negative edge of STB which overrides CLR.
0° C to +70° C
Operating Temperature . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
All Output or Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7 Volts
All Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0 to +5.5Volts
Output Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 mA
COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
"Ta

308

=

25'C

ABSOLUTE MAXIMUM
RATINGS*

BLOCK DIAGRAM

p.PB8212

STB MO (OS,·OS21
0
1
0
1
0
1
0
1

0
0
1
1
0
0
1
1

B

tc
PRIORITY
COMPARATOR

D

-=IC

INTERRUPT
FLlp·FlOP

Ol--~----------I
INTERRUPT
DISABLE
FLIP-FLOP

INTEG)~--------------------------------J
ClK 6r-------------------------------------~

General
The JlPB8214 is an LSI device designed to simplify the circuitry required to
implement an interrupt driven microcomputer system. Up to eight interrupting
devices can be connected to a JlPB8214, which will assign priority to incoming
interrupt requests and accept the highest. It will also compare the priority of the
highest incoming request with the priority of the interrupt being serviced. If the
serviced interrupt has a higher priority, the incoming request will not be accepted.
A system with more than eight interrupting devices can be implemented by inter·
connecting additional JlPB8214s. In order to facilitate this expansion, control
signals are provided for cascading the controllers so that there is a priority estab·
lished among the controllers. In addition, the interrupt and vector information
outputs are open collector.
Priority Encoder and Request Latch
The priority encoder portion of the JlPB8214 accepts up to eight active low
interrupt requests (RO-R7)' The circuit assigns priority to the incoming requests,
with R7 having the highest priority and RO the lowest. If two or more requests
occur simultaneously, the JlPB8214 accepts the one having the highest priority.
Once an incoming interrupt request is accepted, it is stored by the request latch and
a three-bit code is output. As shown in the following table, the outputs, (AO-A2)
are the complement of the request level (modulo 8) and directly correspond to the
bit pattern required to generate the one byte RESTART (RST) instructions
recognized by an 8080A. Simultaneously with the AO-A2 outputs, a system
interrupt request (INT) is output by the JlPB8214. It should be noted that incoming
interrupt requests that are not accepted are not latched and must remain as an
inputto the JlPB8214 in order to be serviced.

314

FUNCTIONAL
DESCRIPTION

fLPB8214

FUNCTIONAL
DESCRIPTION
(CONT.)

RESTART GENERATION TABLE

,---

LOWEST

03

02

01

°0

1

1

1

1

1

0

1

1

1

0

1

1

1

1

0

0

1

1

1

1

RO

7

1

1

1

1

1

R1

6

1

1

1

1

! s

1

1

1

f--T~

1

,-

1

1
0

1

1

1

1

1

1

!

0

1

0

1

1

I

0

0

1

1

1

0

0

0

1

1

~-t--~RS

'CAUTION

04

°6

1

R2

HIGHEST

05

°7
RST

PRIORITY
REQUEST

2

R6

1

1

1

R7

0'

1

1

~A1T~r:J

I

I

1

"
1

1

RST 0 will vectol the ploglam counter to location 0 (zero) and

Invoke the same routlrl{' as the "RESET" Input to 8080A.

Current Status Register
The current status register is designed to prevent an incoming interrupt request from
overriding the servicing of an interrupt with higher priority. Via software, the priority
level of the interrupt being serviced by the microprocessor is written into the current
status register on BO-B2.'The bit pattern written should be the complement of the
interrupt level.
The interrupt level currently being serviced is written into the current status register
by driving ECS (Enable Current Status) low. The pPB8214 will only accept interrupts
with a higher priority than the value contained by the current status register. Note
that the programmer is free to use the current status register for other than as above.
Other levels may be written into it. The comparison may be completely disabled by
driving SGS (Status Group Select) low when ECS is driven low. This will cause the
pPB8214 to accept incoming interrupts only on the basis of their priority to each
other.
Priority Comparator
The priority comparator circuitry compares the level of the interrupt accepted by the
priority encoder and request latch with the contents of the current status register.
If the incoming request has a priority level higher than that of the current status
register, the INT output is enabled. Note that this comparison can be disabled by
loading the current status register with SGS~O.
Expansion Control Signals
A microcomputer design may often require more than eight different interrupts. The
pPB8214 is designed so that interrupt system expansion is easily performed via the
use of three signals: ETLG (Enable This Level Group); ENLG (Enable Next Level
Group); and ELR (Enable Level Read). A high input to ETLG indicates that the
pPB8214 may accept an interrupt. In a typical system, the'ENLG output from one
pPB8214 is connected to the ETLG input of another pPB8214, etc. The ETLG of
the pPB8214 with the highest priority is tied high. This confIguration sets up
priority among the cascaded pPB8214's. The ENLG output will be high for any
device that does not have an interrupt pending, thereby allowing a device with lower
priority to accept interrupts. The ELR input is basically a chip enable and allows
hardware or software to selectively disable/enable individual pPB8214's. A low on
the Et..:R input enables the device.
.

315

II

JLPB8214
Interrupt Control Circuitry
The MPB8214 contains two flip-flops and several gates which determine whether an
accepted interrupt request to the MPB8214 will generate a system interrupt to the
8080A. A condition gate drives the 0 input of the interrupt flip-flop whenever an
interrupt request has been completely accepted. This requires that: the ETlG
(Enable This level Group) and INTE (Interrupt Enable) inputs to the MPB8214 are
high; the ElR input is low; the incoming request must be of a higher priority than
the contents of the current status register; and the MPB8214 must have been enabled
to accept interrupt requests by the clearing of the interrupt disable fl ip-flop.

FUNCTIONAL
DESCRIPTION
(CONT_)

Once the condition gate drives the 0 input of the interrupt flip-flop high, a system
interrupt (INT) to the 8080A is generated on the next rising edge of the ClK input
to the j.1PB8214. This ClK input is typically connected to the ¢2 (TTL) output of an
8224 so that 8080A set-up time specifications are met. When INT is generated, it
sets the interrupt disable flip-flop so that no additional system interrupts will b~
generated until itis reset. It is reset by driving ECS (Enable Current Status) low,
thereby writing into the current status register.
It should be noted that the open collector j'j\ff output from the j.1PB8214 is active
for only one clock period and thus must be externally latched for inputting to the
8080A. Also, because the INT output is open collector, when MPB8214's are
cascaded, an INT output from anyone will set all of the interrupt disable flipflops in the array. Each j.1PB8214's interrupt disable flip-flop must then be
cleared individually in order to generate subsequent system interrupts.

TYPICAL MPB8214
CIRCUITRY

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° C to +70° C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65° C to +125° C
All Output and Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7 Volts
All Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0 to +5.5 Volts
Output Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

316

ABSOLUTE MAXIMUM
RATINGS*

JLPB8214
DC CHARACTERISTICS

Ta = oOe to +7oo e, Vee = 5V ± 5%
PARAMETER

SYMBOL

Input Clamp Voltage (all inputs)

Vc
IF

Input Forward Current: ETLG input
all other inputs
Input Reverse Current: ETLG input
all other inputs
Input LOW Voltage: all mputs
Power Supply Current

Short Circuit Output Current: ENLG output

fNT and AO-..l\2

Input

Ca~acitance

1.0
0.5
-0.25
80
40
0.8

90
2.4
-20

.3
3.0
35

ICEX

TEST CONDITI ONS

V
mA
mA

IC"'5mA
VF-0.45V

~A

VA-5.25V

~A

V
V
mA
V
'V

130
.45

VCC-5.0V
VCC-5.0V

(i)

-55

mA

10L 10mA'
10H--lmA
VOS-OV. VCC-5.0V

100

~A

VCEX-5.25V

.

liMITS
TYP.(j)

MAX.

CIN

5

10

pF

VBIAS=2.5V

COUT

7

12

pF

VCC=5V
f=lmHz

MIN.

LIMITS
TYP.(j)

SYMBOL

Output Capacitance

UNIT

MAX.

2.0

Ta = 25°e
PARAMETER

AC CHARACTERISTICS

'.15
-.08

VIL
VIH
ICC
VOL
VOH
lOS

Output LOW Volt3!::!e: all outputs
Output HIGH Voltage: ENLG output

CAPACITANCE @

LIMITS
TYP.(j)

IR

Input HIGH Voltage: all inputs

Output Leakage Current:

MIN.

MIN.

UNIT

TEST CONDITIONS

Ta = oOe to +7ooe Vee = +5V +
- 5%
PARAMETER

SYMBOL

MAX.

UNIT

TEST CONDITIONS

elK Cycle Time

tCY

80

50

ns

Input pulse

elK, ECS, INT PuisI'" Width

tpw

25

15

ns

amplitude-: 2.5 Velts

INTE Setup Time to elK

tlSS

16

12

ns

INTE Hold Time after eLK

'ISH
tETCS@

20

10

ns

25

12

-ns

ETLG Hold Time After ClK
ECS Setup Time to ClK

tETCH@

20

10

ns

tECCS@

80

50

ns

ECS Hold Time After ClK
ECS Setup Time to ClK

tECCH@

0

tECRS@

110

ECS Hold Time After ClK

tECRH@

0

ECS Setup Time to ClK
ECS Hold Time After CLK
SGS and 80-82 Setup Time to GIl<
SGS and 80-82 Hold Time After elK
RO-R7 Setup Time to ClK
RO-R7 Hold Time After ClK
tNT' Setup Time to ClK
ClK to INT Propagation Delay
RO-R7 Setup Time to tNT
RO-R7 Hold Time After INT

tECSS@)

75

tECSH@

0

RO-R7 to AO-A2 Propagation Delay
ELR to AO-A2 Propagation Delay

tRA

80

100

ns

tELA

40

55

ns

ECS to AO-A2 Propagation Delay
ETLG to AO-A2 Propagation Delay

tECA

100

120

ns

tETA

35

70

ns

SGS and 80 .... 82 Setup Time to ECS
SGS and BO-B2 Hold Time After ECS
RO-R7 to ENlG Propagation Delay

tDECS®

15

10

tDECH®

15

10

tREN

45

70

ns

ELTG to ENLG Propagation'Delay
ECS to EN LG Propagation Delay
ECS to ENLG Propagation Delay

tETEN

20

25

ns

tECRN

85

90

ns

tECSN

35

55

ns

ETLG Setup Time to elK

Notes:

. .

tDCS@)

70

tDCH@

0

tRCS@

90

ns
70

ns

70

ns

Output -loading of

55

ns

50
55

ns

Speed measurements
taken at the 1.5 Volts

ns

levels.

35

ns

ns

15

tCI

15 mA and. 30 pF.

ns

0

tACH@
'ICS

Input rise and fall

times: 5 ns. between
1 and 2 Volts

tRIS@

10

0

tRIH®

35

20

25

ns
ns
ns

ns

II

ns

°

Typical values are for T a=25 C, V CC=5.0V
8O-B2' SGS, ClK, Ro-R4 grounded, all other inputs and all outputs

open.
This parameter is periodically sampled and not 100% tested.
Required for proper operation if INTE is enabled during next clock pulse.

These times are not required for proper operation but for desired
change in interrupt flip-flop.
Required for new request or status to be properly loaded.

317

fLPB8214

1'"-------------

-------,
ETLG

-------

----~(~----.X"-

tACS

--

I

- - -- ---

X---- ------- ----

----------

_J

tETCH 1

--------X =x----- ----------tETes

-J

"' r---J
tDECS

I):'

tDEC~

'-

I

"' ~

e

tIS~-.b - I
_______ J~
toes

.

tpw

-

~

x=-x
t--

teeRS

tlSH

------- ----

J

I

tOCH

tEecH

teTA

L.Jf
ttcs

tCI

r-----"\
_tpw=!'----

-----------

'r
-----------

1

tELA

--- ---- ---- -

r___ ..J
tETEN

tREN

-

1

tCY

- ---- --- ------ ------ '(-tRA

tECSH

"tECAH

- ----- --- ------ - --------_ ......

tECA

tECSS

,I

f

tEces

~~

tECSN

TIMING WAVEFORMS

-----~I
tAIH
~t tRIS

tRCH

"\
'---

INTE

-- -,- --

1

-~---------

- -,J'I'-___________________ _

ENLG _ _ _ _ _ _ _ _ _ _ _ _ _

vee

OOT~::
TEST CIRCUIT

PACKAGE OUTLINE
J.lPB8214C

IrEM

MILLIMETERS
33 MAX.
2.53

2.54
O.5±O.1

27.94

H

I
J
K

1.'
3,2 MIN.
O.SMIN.
S.22MAK
5.72 MAX.

15.24
1>2
O.2S±O.1

INCHES

1.28

.,

O.t

0.02 ± 0.004

1.1
.059
D.125 MIN.

0.02 MIN.
0.205 MAX.
0.225 MAX.

0.6
0.52
0.01 ± 0.004

SP8214·2·77·GN·eAT

318

NEe
p.PB8216
p.PB8226

NEe Microcomputers, Inc.

4 BIT PARALLEL BIDIRECTIONAL
BUS DRIVER
DESCRIPTION

FEATURES

All inputs are low power TTL compatible. For drilling MOS, the DO outputs provide
a high 3.65V (VoHI, and for high capacitance terminated bus structures, the DB
outputs provide a high 55 mA (lOLl capability.

• Data Bus Buffer Driver for ,.COM·S Microprocessor Family
•

Low Input Load Current - 0.25 mA'Maximum

•

High Output Drive Capability for Driving System Data Bus

• 3.65V Output High Voltage fo( Direct Interface to ,.COM·S Microprocessor
Family
• Three State Outputs
•

Reduces System Package Count

• Available in 16 pin packages: Cerdip and Plastic

PIN CONFIGURATION

es

Vee

00 0

OlEN

OBO

0°3

01 0

OB 3

001

01 3

OB l

0°2

PIN NAMES
DBO - 083

Data Bu, Bi-Directional

DID - 013

Data Input

011. Output
Data in Enable Direction Control
ChipSeIKl

OB 2

II

Rev/2

319

p.PB8216/8226
Microprocessors like the ),IPD8080A are MOS devices and are generally capable of
driving asingle TTL load. This also applies to MOS memory devices. This type of drive
is sUfficient for small systems with a few components, but often it is necessary to
buffer the microprocessor and memories when adding components or expanding to a
multi-board system.

FUNCTIONAL
DESCRIPTION

The ),IPD8216/8226 is a four bit bi·directional bus driver specifically designed to buffer
microcomputer system components.
Bi-Directional Driver
Each buffered line of the four bit driver consists of two separate buffers. They are
three state in nature to achieve direct bus interface and bi-directional capability. On
one side of the driver the output of one buffer and the input of another are tied
together (DB), this is used to interface to the system side components such as memories, I/O, etc. Its interface is directly TTL compatible and it has high drive (55 mAl.
For maximum flexibility on the other side ofthe driver the inputs and outputs are
separate. They can be tied together so that the driver can be used to buffer a true
bi·directional bus such as the 8080A Data Bus. The DO outputs on this side of the
driver have a special high voltage output drive capability (3.65V) so that direct inter·
face to the 8080A processor is achieved with an adequate amount of noise immunity
(650 mV worst case).
Control Gating CS, OlEN
The CS input is used for device selection. When CS is "high" the output drivers are
all forced to their high·impedance state. When it is "low" the device is selected
(enabled) and the data flow direction is determined by the OlEN input.
The i5iEN input controls the data flow direction (see Block Diagrams for. compl~e.
truth table). This directional control is accomplished by forcing one of th.e :pai.r··of··' .
buffers to its high impedance state. This allows the other to transmit its datil'/t;hiiS .is"
accomplished by a simple two. gate circuit.
.' .
The ),IPB8216/8226 is a device that will reduce component count in microcomputer'
systems and at the same time enhance noise immunity to assure reliabl.e, high"
performance. operation.

8226
DIOo-----U~--t-,

BLOCK DIAGRAMS

DIO
DBO
DOo
DI1
DB1

",--oDB1
[)01
DI2

DB2
D02
DI3
D0 3

cs

320

~--~~---ocs
DIEN

Cf

RESULT

0

0

01 "'OB

1

0

OB ·00

0

1

r--, "1 ~Hi9h

DB3

DIEN 0 - -...- - - - - '

OlEN

Impedance

",PB8216/8226
ABSOLUTE MAXIMUM
RATINGS*

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... O°C to 70°C
Storage Temperature (Cerdip) . .
. ............ .
-65°C to +150°C
(Plastic) . . . . . . . . . . . . . . . . . . . . . .
-65°C to +125°C
All Output and Supply Voltages ... .
. . -0.5 to +7 Volts
All Input Voltages . . . . . . . . . . . . . .
. ...• -1.3 to +5.5 Volts
Output Currents
....... .
. . . . . . . . . . . . 125 mA

COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other cor'lditions above those indicated in the operational. sections of this specification is not
implied. Exposure to absolute maximum rating conditions ,for exte,nded periods may affect device
reliability.
"Ta ~ 25°C

DC CHARACTERISTICS
SYMBOL

PARAMETER

Input Load Current

lJi"tN,

LIMITS
MIN

TYPQ)

MAX

UNIT

TEST CONDITIONS
~

IF 1

-0.5

mA

VF

0.45

IF2

-0.25

mA

VF - 0.45

IRI

20

~A

VR - 5.25V

IR2

10

~A

VR - 5.25V

Vc

-1.0

V

IC- -SmA

~

Input Load Current AU

Other Inputs
Input Leakage Current
DIEN,~

Input Leakage Current
01 Inputs

Input Forward Voltage
Clamp
Input "Low" Voltage

Vil

Input "High" Voltage

VIH

Output Leakage Current DO
13·State)
DB

10
10

20
100

~A

ICC
ICC

130
120

mA
mA

Power Supply Current

8216
8226

V
V

Vall

Output "Low" Voltage

Va ~ 0.45/5.25V

U48

V

DO Outputs tOL 15mA
DB Outputs 10l ~ 25 mA

8216

VOl2

0.7

V

DB Outputs 10l

8226

0.7

V

DB Outputs 10H - 50 mA

Output "High" Voltage

VOl2
VOHI

3.6~

V

DO Outputs IOH -

1 mA

Output "High" Voltage

VOH2

2.4

V

DB. Outputs tOH

lOrnA

Output Short Circuit
Current

In~

mA
mA

Db Outputs Va - Oil
DB Outputs Vce 5.0V

Output "Low" Voltage

Note:

CAPACITANCE

0.95
2.0

CD

lOS

Typical values are for Ta

==

15
--30

25°C. Vec

==

-65
-120

SYMBOL

LIMITS
MIN

TYP

MAX

Input Capacitance
Output Capacitance

COUT1

10~

Output Capacitance

COUT2

18~

Notes:

CIN

55 mA

5.0V.

 DO Outputs, CL = 30 pF, R, = 300/10 Kn, R2 ~ 600/1 Kn,
OUT

L
C

:'

TEST CIRCUIT

TIMING WAVEFORMS

INPUTS

OUTPUT
ENABLE

OUTPUTS

Cerdip
INCHES
0.784 MAX

PACKAGE OUTLINE
IlPB8216C/D
IlPB8226C/D

106

2."
0.46' 0.10
17.78

010

2.54 MIN

5.08 MAX

.0"
a,20MAX

0.30

Plastic
MILLIMETERS
19.4 MAX
~-------A--~

____

~

081

2.54 MIN

0.18 MAX

7.62

0.30

6.4
0.25

0.25
.0.10

1).01

SP8216/8226-8-77-GN-CAT

NEe
NEe Microcomputers, Inc.

~PB8224

CLOCK GENERATOR AND DRIVER FOR
8080A PROCESSORS

DESCR IPTION

The ¢'B8224 is a single chip "lock generator and driver for 8080A processors.
The clock freque'ncy is determined by a u~e~'~pecified crystal and is capable of
meeting the timing requirements of the entire a080A family of processors. MOS
and TTL level clock outputs are generated.
Additional logic circuitry of the ¢'B8224 provides signals for power·up reset, an
advance status strobe and properly synchronizes the ready signal to the processor.
This greatly reduces the number of chips needed for 8080A systems.
The ¢'B8224 is fabricated using NEC's Schottky bipolar process.

FEATU R ES

• Crystal Controlled Clocks
Oscillator Output for External Timing
MOS Level Clocks for 8080A Proce.ssor
TTL Level Clock for-DMA Activities
Power·up Reset for 8080A Processor
Ready Synchronization
Advanced Status Strobe'
Reduces System Package Count
Available in 16·pin Cerdip and Plastic Packages

•
•
•
•
•
•
•
•

PIN CONFIGURATION

RESET

REsiN

XTAL 1

RDYIN

XTAL2

READY

TANK

SYNC

PIN NAMES

Vcc

OSC

Reset Output
Ready Input

Ready Output
Sync Input

StatusSTB

STsTs

<1>2 (TTL)

<1>1

STSTB

<1>2

01>1
01>2
XTALI
XTAL2

VDD

TANK

GND

Reset Input

RESIN
RESET
ROYIN
REAOY
SYNC

Output

}

Processor
Clocks

} Crystal
Connections
Used With
Overtone

Crystal
Oscillator

OSC
2,
which are buffered and at MOS levels, a TTL level 1

2tCY

¢2 Pulse Width

t~2

5tCY

4>1 to 1'/)2 Delay

tOl

4>2 to 4>1 Delav

,t02

tPl to tP2 Delav

t03

9

TYP

tR

$, and ¢2 Fall Time

tF

~2

t~2

to ~2ITTL) Delay

TEST CONOITIONS

MAX

-20n$

9""""

-35ns

a
2tcv

9

ns
CL' 20pF t050pF

-14n5
2tcv

2tCY

9

"9
4>1 and 412 Rise Time

UNIT

+2Ons

'20

20
-5

ns

+15

~2

R"

TTL. CL ' 30 pF
300n

R2 'Goon
tP2 to STSTB Delay

6tcv

toss

9

STSTB Pulse Width

tpw

tcv

RDVIN Setup Time

tORS

toST'ffi
RDVIN Hold Time

ns

9

9 - 15nl
50n5-

STsi'ii. CL ~ 15 pF

4tCY

g-

o

ns

R,' 2K
R2' 4K

4tcv

Aher"Si'SB

tDRH

-g-

READY or RESET

tOR

4tCY

to'CP2 Delay

6tCY

-30ns

9""

ns

-25n5

Ready and Reset

CL -10 pF
R"',2K
R2 '4K

Crystal FrequencyS

MHz

..L

fCLK

tcv

Maximum Oscillating

27

fMAX

MHz

Frequency

Note:

--------

.

___ - __ .

VOLTAGE MEASUREMENT POINTS' DO·D 1 IwhtnoUlgUIS. LQoUIc "0" • 0.8'11. LOII"c "1" • 3.0'1/. All olh,r 511"ilis ",ps.ued
ill1.S'l/.

332

#-,PQ8228

STATUS WORD CHART

!,PD8080A
OUTPUT

!,PB8228/8238
OUTPUT

II
333

,",PB8228

PACKAGE OUTLINE
f..I

PB8228C/D

pPB8228
(Plastic)
ITEM

MILLIMETERS

INCHES

A

38.0 MAX.

1.496 MAX.

B

2.49

0.098

C

2.54

0.10

D

o 5 ~ 0.1

0.02 ± 0.004

E

33.02

F

1.5

0.059

1.3

G

2.54 MIN.

0.10MIN.

H

0.5MIN.

0.02MIN.

I

5.22 MAX.

0.205 MAX.

J

5.72 MAX.

0.225 MAX.

K

15.24

0.6

L

13.2

0.52

M

025 + 0.10
. - 0.05

+ 0.004
0,01 _ 0.002

~------------A----------~~

pPB8228
(Ceramic)
ITEM

MILLIMETERS

INCHES

A

36.2 MAX.
1.59 MAX.
2.54
0.46 ± 0.05
33.02
1.02
3.2 MIN.
1.0
3.5
4.5
15.24
14.93
0.25 ± 0.05

1.43
0.06
0.1
0.02 ± 0.004
1.3
0.04
0.13
0.04
0.14
0.18
0.6
0.59
0,01 ± 0.002

B

C
0
E
F
G
H
I
J
K
L
M

SP8228/38·10-79-CA T

NEe

NEe Microcomputers, Inc.

p.PD8243

INPUT/OUTPUT EXPANDER FOR
P. P08048/8748/8035

DESCR I PTION

The pPD8243 input/output expander is directly compatible with the pPD8048 family
of singie-chip microcomputers. Using NMOS technology the ,uPD8243 provides high
drive capabilities while requiring only a sing'le +5V suppiy voltage.
The pPD8243 interfaces to the pPD8048 family through a 4-bit I/O port and offers
four 4-bit bi-directional static I/O ports. The ease of expansion allows for multiple
J.lPD8243's to be added using the bus port:
The bi:directional I/O ports of the ,uPD8243 act as an extension of the I/O capabilities
of the ,uPD'8048 microcomputer family. They are accessible with their own ANL, MOV,
and OR L instructions.

FEATU RES

• Four 4-Bit I/O Ports
•
•
•
•
•
•
•
•

PIN CONFIGURATION

Fully Compatible with ,uPD8048 Microcomputer Family
High Output Drive
".
NMOS Technol?gy
Single +5V Supply
Direct Extension of Resident pPD8048 I/O Ports
Logical AND and OR Directly to Ports
Compatible with Industry Standard 8243
Available in a 24-Pin Plastic Package

Vee

P50
P40

2

P51

P41

3

P52
P53

P42

4

P43

5

CS

6

Peo

,uPD
8243

P61

PROG

7

P23

8

P-63

P22

9

. P73

P62

. P21

Pn

P20

P71

GNO

P70

II
335

p.PD8243
General Operation
The I/O capabilities of the J.LPD8048/8748/8035 can be enhanced in four 4-bit I/O port
increments using one or more J.LPD8243's. These additional I/O lines are addressed as
ports 4-7. The following lists the operations which can be performed on ports 4-7.
• logical AND Accumulator to Port.
• logical OR Accumulator to Port.
• Transfer Port to Accumulator.
• Transfer Accumulator to Port.
Port 2 (P20-P23) forms the 4-bit bus through which the J.LPD8243 communicates with
the host processor. The PROG output from the J.LPD8048/8748/8035 provides the
necessary tim[ng to the J.LPD8243. There are two 4-bit nibbles involved in each data
transfer. The first nibble contains the op-code and port address followed by the second
nibble containing the 4-bit data_ Multiple J.LPD8243's can be used for ,additional I/O.
The output lines from the J.LPD8048/8748/8035 can be used to form the chip selects
for the add itional J.LPD8243' s.
Power On Initialization
Applying power to the J.LPD8243 sets ports 4-7 to the tri-state mode and port 2 to the
input mode. The state of the PROG pin at power on may be either high or low. The
PROG pin must make a high-to-Iow transition in order to exit from the power on
mode. The power on sequence is initiated any time VCC drops bel9w IV. The table
below shows how the 4-bit nibbles on Port 2 correspond to the J.LPD8243 operations.
Port Address
P20
0
1
0
1

P21
0
0
1
1

Op-Code
Address Code
Port 4
Port 5
Port 6
Port 7

P23
0
0
1
1

P22
0
1
0
1

Instruction Code
Read
Write
ORlD
ANlD

For example an 0010 appearing on P20-P23, respectively, would
result in a Write to Port 4.
Read Mode
There is one Read mode in the J.LPD8243. A falling edge on the PROG pin IJtches the
op-code and port address from input Port 2. The port address and Read operation are
then decoded causing the appropriate outputs to be tri-stated and the input buffers
switched on. The rising edge of PROG terminates the Reael operation. The Port
(4,5,6, or 7) that was selected by the Port address (P21-P20) is returned to the tri-state
mode, and Port 2 is switched,to the input mode.
Generally, in the read mode, a port will be an input and in the write mode it wiil be an
output. If during program operation, the J.LPD8243's modes are changed, the first read
pulse immediately following a write should be ignored. The subsequent read signals are
valid. Reading a port will then force that port to a high impedance state.
, Write Modes
There are three write modes in the J.LPD8243. The MOVD Pp,A instruction from the
J.LPD8048/8748/8035 writes the new data directly to the specified port (4,5,6, or 7).
The old data previously latched at that port is lost. The OR lD Pp,A instruction performs a logical OR between the new data and the data currently latched at the
selected port. The result is then latched at that port. The final write mode uses the
ANlD Pp,A instruction. It performs a logical AND between the new data and the
data currently latched at the specified port. The result is latched at that port.
The data remains latched at the selected port following the logical manipulation until
new data is written to that port.

FUNCTIONAL
DESCRIPTION

,",PD8243
BLOCK DIAGRAM

PIN IDENTIFICATION

PIN
NO.

SYMBOL

2·5
1,21.23
17·20
13·16

P4o- P43
P5o- P53
P6o- P63
P70, P73

The four 4·bit staticbi·directional I/O ports. They
are programmable into the following modes:
input mode (during a Read operation); low
impedance latched output mode (after a Write
operation); and the tri·state mode (following a
Read operation). Data appearing on I/O lines
P20,P23 can be written directly. That data can
also be logically ANDed or ORed with the previous
data on those lines.

6

CS

Chip Select input (active·low). When the IlPD8343
is deselected (CS = 1), output or internal
status changes are inhibited.

7

PROG

Clock input pin. The control and address informa·
tion are present on port lines P20,P23 when PROG
makes a high·to·low transition. Data is present on
port lines P20,P23 when PROG makes a low·to-high
transition.

8-11

P20, P23

P2o-P23 form a 4·bit bi·directional port. Refer to
PROG function for contents of P20,P23 at the
rising and falling edges of PROG. Data from a
selected port is present on P2o-P23 prior to the
rising edge of PROG if during a Read operation.

12

GND

The IlPD8041 /8741 ground potential.

24

VCC

+5 volt supply.

FUNCTION

337

11

f,'P,DfS 243
O°C to +70°C
-65°C to +150°C
. -65°C to +125°C
- 0.5 to +7 Volts  Data Bus
Data Bus -> pPD8251 /pPD8251A
Status -> Data Bus
Data Bus -> Control
Data Bus

TM:Z80 is a registered trademark of Zilog. ,

342

->

3-Stcte

fLPD8251 18251 A
BLOCK DIAGRAM
hD

SYNDET (~P08251)
SYNDET/BD (~P08251A)

ABSOLUTE MAXIMUM
RATINGS*

Operating Temperature . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . -o°c to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125°C
Ali Output Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 to +7 Volts
All Input Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . .. -0.5 to +7 Volts
Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ""'0.5 to +7 Volts
COMMENT: Stress above those listed under "AbsOlute Maximum Ratings" may cause permane~t
damage to the device. This, is a stress rating only and functional operation of the device at these or
any other conditions above those indicated, in the operational sections of th is specification is not
implied. Exposure to absolute maximum rating conditions for"extended periods may affect device
rei iabil itv.

*Ta = 25°C
DC CHARACTERISTICS

Ta:

rfc 10 70·C; VCC = 5.0V

± 5%; GND = OV

LIMITS
PD82S1
PARAMETER
Input Low Voltage

VIL

-0.5

Input High Voltage

VIH

2.0

Output Low Voltage

Output, High, Voltage

Data Bus Leakage

Input load Curre.nt
Power ~pplV Currem

CAPACIT ANCE

SYMBOL MIN TVP

MAX

0.8

0.5

0.8

2.0 VCC

0.45

2.4

0.45

2.4

IDL
IlL

Icc

MIN

VCC

VOL

VOH

"PD82S1A

MAX

45

,

-SO

-10

10

10

UNIT

TEST CONDITIONS

V
V
V

V

~PD8251.:

IOL = 1.7 mA

~PD8251A:

10L

~PD82S1:

IOH=~10Q"A

~PD82S1A:

10H

= 2.2mA
=-400 "A

=0.45V
VOUT = VCC
VOUT

"A

10

10

"A

80

100

mA

AIS.5V
~PD8251A:

All Outputs

=

Logic 1

Ta = 2S·C; VCC = GND = OV
LIMITS
PARAMETER

SVMBOL

MIN'

TVP

MAX

UNIT

Input Capacitance

CIN

10

pF

I/O Capacitance

ClIO

20

pF,

TEST
CONDITIONS

fe = 1 MHz
Unmeasured
pins returned

toGND

343

II

,.,.p [)8251l8251 A
Ta ~

O"c

to

Ufe, Vee ~ 5.0V· 5%;GNO

=

AC CHARACTER ISTICS

av.

L
I
PARAMETER

SVMBOLI

LIMITS

I

J'PD8251
MIN

I

I

MAX

~PD821$A

MIN

MA~ UNIT

TEST
CONDITIONS

READ
Address Stable before READ, Its. C7QI

tAR

Address Hold Time fO~~

tRA

READ Pulse W,dth

tRR'

Dala Delav from REAO

tRO

350

200

REA15 to Data Floatmg

tOF

200

100

50
430

250

25

pP0825t:'CL = 100pF
",P08251A: CL" 1&OpF
",P08251

10

Cl = 100pF
CL = 15pF

WRITE
Address Siable before WRITE

tAW

Address Hold r!me for WRITE

20

tWA

20

tww

400

250

Data Sel'Up Time for WRITE

tow

200

150

Data Hold Time for WRITE

two

40

0

Recoverv Time Between WRITES ~

tRV

6

WRI

re Pulse Width

tey

OTHER TIMING
Clock Period

QJ

tow

Clock Pulse Width Low

tow

l,;lock Rise and Fall rime

'R,IF

TxD Delav from Failing Edge of -TxC

'oT)(

Ax Data Set-Up Time 10 Sampling Pulse

'SA;!!;

Ax Data Hold Time to Sampling Pu!se

IHAx

Transmitter Inpul Clock Frequency
I X Baud Rate
16X Baud A'lle
64X Baud Aale

'T,

rranSlnlffer Input Clock PUlse \'Vldtn
TX Baud Rate
16X and 64X Baud Rate

tTPW

Transmiller Input Clock Pulse Delay
I X Baud Rate
16X arld 64 X Baud Rate

ITPQ

Receiver Input Clock Frequency
IX Baud Rate
16X Baud Rale
64X Baud Rale

'R,

Receiver Input Clock P\llse Width
IX Baud Rale
l6X and 64X Baud Rale

tRPW

Receiver Input Clock P\llse Delay
IX Baud Rate
16X and 64X Baud,Rale

tRPD

TxADV Delay from Center of Data 811

tT,

RxADV Delay from Center of Data elt

tRX

Internal SYNOET Delay Irom Ce... ter
01 Data 81t
External SYNDET Set·Up Tin" before
Failing Edge of RxC
TxEMPTY Delay Irom Center of Data BI'

@
@

1.35

0.32

O. 7tCY

120

1.35

'Cy·9O

"'

90
50

20

"'

2.

..

"'
4
310
615

k~.
kH.

12

12

.

te,
tCY

15

tCY
tCY

DC
DC

I DC

..

64
310
615
12

kH
kH.
kH,
~

tev

15

•

•

520
520

12
1

",P08251: CL = 100 pF

"'

520
520

15

Control to READ Set·Up Time fDSA, CTS}

CD
®

220

DC
DC
DC

I I,.:ontrol Delay !!2t!! I!i!Wg Edge of
WRITE (TilE. OTR, RTSI

Notes.

0.420

tCY

Clock Pulse Width High

tCY
tey

"J
16

/JPD8251: C ·50pF

tey

20

24

tIS

25

24

tey

tES' .

16

16

tCY

tTxE

16
16

20
,8

tey

twc
teR

16

20

tCY

«
...J

w

0

f-

D.U.T.

'+10

0

::>

t - - t " - - -.......

0..

f-

::>

24K (82511
6K (8251AI

0

-10

<3,

-20
-100

Figure 1.

-50

0

+50

+100

A CAPACITANCE (pFI

Typical 1:1 Output
Delay Versus 1:1 Capacitance (pF)

344

TEST LOAD CIRCUIT

Ji.P 0825118251 A
TIMING WAVEFORM
CLOCK

SYSTEM CLOCK INPUT

TPW

:I':::~:DE~, ~
'.~.~~ ~ .~
f--- 'DTX

T,DATA

~

ITPD--l

'DTX'

.

I--

~l-----------x::=

TRANSMITTER CLOCK AND DATA

RII DATA

RxClh:MODE)

_U----

RXC (16 MODE)
INTSAMPlING
PULSE

RECEIVER CLOCK AND DATA

TJC ROY

OATA IN 10.8.1

_ __~D~ON~'~T~CA~R~E____{£~~~~~

__~~~~

CID

WRITE DATA CYCLE (PROCESSOR -HJSART)

Rx ROY

DATA OUT 10.8.1

C/l!

II

_~~~DA~T~A~F~lO~A~T~__-f~~~~~$)~~~~

--------"""'1

e!

READ DATA'CYCLE (PROCESSOR +-USART)

.345

o

DTR. R T S - - - - - - - - - - - - - - -.....

r-----

WR---------~I

DATA IN (D.B,)

--------~tt==t}~-----

CID _ _ _ _ _ _ _- J

tWA

~-------..... r

WRITE CONTROL OR OUTPUT PORT CYCLE
(PROCESSOR -+ USART)

o

DSR.CTS - - - -...... , . - - - - - - - - - - - - - - - -

RD

------~---

DATAOUT _ _ _ _~_ _ _ _ _~t:=::::::j]~---(D,B,)

cf15 _ _ _ _ _ _...,.JI

~-------1tAR
READ CONTROL OR INPUT PORT CYCLE
(PROCESSOR +- USART)

NOTES:

CD TWC I"cl~


DATA CH;;ACTER

RECEIVE FORMAT
Not.. :~, Generated by "PD8251/8251 A

2 Does not appear on the Data Bus.

3 If character length is defined as 5. 6. or 7 bits. the
unused bits are set to "zero."

353

J'PD825118251 A
SYNCHRONOUS
TRANSMISSION

As in Asynchronous transmission. the TxD output remains "high" (marking)
until the J.lPD8251 and J.lPD8251A receive the first character (usually a SYNC
character) from the processor. After a Command Instruction has set TxEN and
after Clear to Send (CTS) goes low. the first character is serially transmitted.
Data is shifted out on the falling edge of TxC and the same rate as TxC.
Once transmission has started. Synchronous Mode format requires that the serial data
stream at TxD continue at the TxC rate or SYNC will be lost. If a data character is
not provided by the processor before the J.lPD8251 and J.lPD8251A Transmit
Buffer becomes empty. the SYNC character(s) loaded directly following the Mode
Instruction will be automatically inserted in the TxD data stream. The SYNC
character(s) are inserted to fill the line and maintain synchronization until new data
characters are available for transmission. If the J.lPD8251 and J.lPD8251A become
empty. and must send the SYNC character(s). the TxEMPTY output is raised to signal
the processor that the Transmitter Buffer is empty and SYNC characters are being
transmitted. TxEMPTY is automatically reset by the next character from the processor.
In Synchronous Receive. character synchronization can be either external or internal.
If the internal SYNC mode has been selected. and the Enter HUNT (EH) bit
has been set by a Command Instruction. the receiver goes into the HUNT mode.

SYNCHRONOUS
RECEIVE

Incoming data on the RxD input is sampled on the rising edge of RxC. and the
Receive Buffer is compared with the first SYNC character after each bit has been
loaded until a match is found. It' two SYNC characters have been programmed. the
next received character is also compared. When the SYNC character(s) programmed
have been detected. the J.lPD8251 and J.lPD8251A leave the HUNT mode and are in character synchronization. At this time. the SYNDET (output) i.s set high. SYNDET is
automatically reset by a STATUS READ.
If external SYNC has been specified in the Mode Instruction. a "one" applied
to the SYNDET (input) for at least one FiXC cycle will synchronize the USART.
Parity and Overrun Errors are treated the same in the Synchronous as in the
Asynchronous Mode. If not in HUNT. parity will continue to be checked even
if the receiver is not enabled. Framing errors do not apply in the Synchronous
format.
The processor may command the receiver to enter the HUNT mode with a Command
Instruction which sets Enter HUNT (EH) ifsynchronization is lost.
07

06

05

04

03

D.,

01

DO

MODE INSTRUCTION
FORMAT
SYNCHRONOUS MODE

I I I I IL, ILl I I I
scs

ESO

EP

PEN

0

I

0

CHARACTER LENGTH

I

0

1

0

0

0

1

1

5
BITS

6

7
BITS

8

BITS

1

BITS

PARI TV ENABLE
11 ENABLEI
10

DISABLE!

eVEN PARITY GENERATION/CHE CK
1 EVEN
0 000

ExTERNAL SYNC DETECT
1 SYNOET IS AN INPUT
0 SYNDET IS AN OUTPUT

SINGLE CHARACTER SYNC
SINGLE SYNC CHARACTER
DOUBLE SYNC CHARACTER

}LPD8251/8251 A
TRANSMIT/RECEIVE
FORMAT
SYNCH RONOUS MODE

PROCESSOR BYTES 15-8 BITSfCHARI

OAT A CH;\;ACTERS

ASSEI\JBLED SERIAL DATA OUTPUT

(T"O~

OATACHAR~;_C_T_ER_S

______

~

TRANSMIT FORMAT
SERIAL DATA INPUT IR,OI

DATACHA~~A_C_T_ER_S

______

PROCESSOR BYTES 15·B BITS CHARI

~

CD

DATAC:~
RECEIVE FORMAT
Note

COMMAND INSTRUCTION
FORMAT

STATUS READ FORMAT

PARITY ERROR

OV ERR UN E R RO R

FRAMING ERROR

I

-0.5

Input High Voltage
(ClK + WR Clockl

VIH(I

2.4

V CC Supply Current

ICC

2.4

TYPG)

MAX
0.8

UNIT

TEST
CONDITIONS

V

VCC + 0.5

V

0.45

V

IOL

VCC
0.65

V

IOH

VCC + 0.5

V

= 2.0 mA
= -200 IlA

V

150

rnA

10

IlA

-10

IlA

High Level Output
Leakage Current

IlOH

10

IlA

= VCC
= OV
VOUT = VCC

Low Level Output
Leakage Current

ILOL

-10

IlA

VOUT

I nput Load Current

(All Input Pins)

III

Note: (i)Typical values for Ta = 2SoC and nominal supply voltage.

242

VIN
VIN

=+0.45V

f.L PD8049/8039L

INSTRUCTION SET
INSTRUCTION CODE
MNEMONIC

FUNCTION

07

DESCRIPTION

06

FLAGS

Os

04

03

02

0,

DO

CYCLES

BYTES

C AC

FO

Fl

ACCUMULATOR
(AI + data

ADD A,:: data

(AI·

ADD A, Ar

(AI, (AI + (Rd
for r - 0 - 7

the AccumulatOr,

(AI, (AI + ((Rdl
for r" 0 1

memory location to the Accumulator.

ADD A,@Ar

Add Immediate the specil ied Data to Ine
Accumulator.

(AI,

(AI + (CI + data

AOOC A, Ar

(AI,
for r

(AI + (CI + (Ad

0

Add Immediate With carry the specified
data to the Accumulator.
Add With carry the contents of the

deSignated register to the Accumulator.

ADDC A.@Ar

(AI, (AI + (CI + IIRr))
for r = 0 I

Add Indirect With carry the contents 01
data memory location to the
Accumulator.

ANL A, :: data

(AI, (A) AND data

ANL A, Rr

(AI, (AI AND (Rd
for r" 0 7

d4

d3

ti2

til

dO

d7

dS

dS

d4

03

02

fi1

dO

d4

d3

d2

d,

ti~

register wl'th Accumulator.

ANLA,@Ar

(AI· (A) AND {(Arll
for r = 0 1

Logical and Indirect the contents of data
memory With Accumulator

CPL A

{AI, NOT (A)

Complement the contents of the
Accumulator

CLA A

(AI· 0

d4

d3

d2

dl

dO

dl

dO

1

0'

,

Logical and specilled Immediate Data
With Accumulator.

d7

dS

dS

o

Logical and contents of deSignated

CLEAR the contents of the Accumulator

OAA

DECIMAL ADJUST the contents of the
ACcumulator.

DEC A

(AI,

(AI

(A) + 1

1

DECAEMENT by 1 the accumulator's

INC A

(AI,

ORL A. ;: data

(AI' (AI OA data

Logical OR specified Immediate data
With Accumulator

OAL A, Ar

(AI, (A) OR (Arl
for r ; 0 7

Logical OR contents of deSignated
register With Accumulator.

OALA,@Rr

(AI, (A) OR ((Ad)
tor r = 0 1

Logical OR Indirect the contents of data
memory location With Accumulafor.

(AN + 1)' (AN)

Rotate Accumulator left by l·blt Without
carry.

Increment by 1 the accumulator's
contents.

IA O)- (A7 1
for N = 0 6

ALC A

dS

0

7

RL A

0
d6

Add IndIrect the contents the data

ADDC A, " data

=

0
d7

Add contents of deSignated register to

(AN + 1) -- (AM; N = 0

6

(AOI ...... (C)

Rotate Accumulator left by
carry

'·b"

d7

d6

a

d5

·0

1

through

{CI' (A71

0- 6

Aotate Accumulator right by '·blt
Without carry.

RAC A

(AN) - (AN + 1); N" 0 . 6
(A71' (C)
lei, (AOI

Rotate Accumulator right by l·blt
through carry

SWAP A

IA4-71 ," (AD

Swap the 2 4·b,t nibbles In the
Accumulator.

XAL A, =data

(AI· (AI XOR data

Logical XOR speCified Immediate data
With Accumulator

XRL A, Ar

IAI·- (AI XOR (Arl
for r ; 0 - 7

Logical XOR contents of deSignated
register with Accumulator.

XAL A,@Rr

(AI,
for r

RR A

(AN) - (AN + 11, N

=

(A71· (AOI

IAI
=

3)

XOR URr))

,
d7

d5

d4

d3

d2

bO
a5

o

Logical XOR Indirect the contents of data
memory location With ACCumulator

0 - 1

d6

1

BRANCH
DJNZ Ar, addr

(Rr) -

(Rr)

l;r'"

a

7

Decrement the specified register and

If (Rrl *- 0

II

(PC 0 - 7) - addr
JBb addr

{PC 0 71 ...... addr If Bb " 1
(PC)' (PCI t 2 If Bb < 0

Jump to specified address If
Accum:..llator bit IS set.

JCaddr

(PC 0 - 71 - addr If C = I
(PC}' (PCI + 2 If C ~

Jump to specified address If carry flag

(PC 0 71 - addr If FO '" 1
(PC) . HPCI + 2 If FO -. 0

Jump to speclfu;'d address,f Flag Fa IS
set.

WC 0
(PC)"

Jump to specified address If Flag F, IS

JFOaddr
JFl addr
JMP addr

a

7} - addr If F 1 " 1
(PC) t 2 ,f Fl =

a

(PC8 101· addrS'O
(PC 0 71
addr 0
(PC 111· OBF

D,rectJumptospecd,edadd,esswlthm
the 2K address block

JMPP@A

(PC 0

Jump mdlfect to specified address With
With address page.

JNC addr

(PC
7)· addr If C '"
(PCI' {PCI + 2 if C ' 1

JNI addr

(PC 0
(PC)"

0 -

a

7)· (tA))

a

Jump to specified address If carry flay IS
low.

71·- addr If \ ~ 0
Jump to specd,ed address If Q11errupt
(PCI t 2 If I l l s low

b2
a7

b,
a6

014

a3

a2

al

00

a7

a6

a5

~4

a3

a2

a,

ao

a7

a6

a5

a4

a3

a2

a,

ao

a7

a6

a5

a4

013

a2

a,

aO

a,O
a7

a9
016

as
a5

(14

013

012

a,

aO

a7

a6

a5

84

a3

il2

al

aO

a7

0
a6

0
a5

a4

a3

82

al

ao

,

0

,

n

237

J.L PD8049/8039L
INSTRUCTION SET (CONT.)
INSTRUCTION CODE
MNEMONIC

FUNCTION

07

DESCRIPTION

Os

Os

FLAGS

04

03

02

01

DO

'.

'3

'2

'1

0

1

'0
0

'3
0
'3
0
'3

'1

'0
0

'2
'2

'1
1
'1

'0
0
'0

'2

'1

'0

'3
0

'2

'1

'3

'2

'1

'0
0
'0

CYCLES

BYTES

C AC

FO

Fl

BRANCH (CO NT.)
~'addr

JNTO addr

(PC 0- 7)

JNT1 addr

(PC 0 _. 7) .- addr if T1 =
I PC)· (PC) + 2 If T1
1

JNZ addr

(PC

~-

(PC)

(PC)

a

7)

0-

i-

if TO=- 0
= 1

'*

addr If A

(PCI· (PC) + 2 d A
JTF addr

(PC

a

0

'7
Jump to specified 1;Iddress If Test 1

IS

'7
Jump to

~pecilled

0-addr if TF = 1
(PC) + 211 TF
0

(PC 0- 7) ...... addr if TO "- 1
<-- (PC) + 2 if TO = 0

Jump to specified address if Test 0 is a

JTl addr

(PC 0

7)· addr if T1 '" 1

Jump to specified addre.ss If Test 1 is a 1.

(PC)·

(PCI + 2 If T1

J2 addr

(PC 0 - 7) • - addr if A -' 0
(PC)' (PC) + 2 If A '

(PCI

0

a

Jump to specified address if Accumulator
is O.

0

1

'6

'5

'7

'6

'7

'6

'5
0
'5

d7

d6

d5

d4

d3

d2

dl

dO

d7

d6

d5

d4

d3

d2

dl

dO

d3

d2

dl

dO

1

Enable the External Interrupt input.

DIS I

1

'4

'4

0
'3

1
1

0

1

Disable the External Interrupt Input.
Enable the Clock Output pin TO.

ENTO CLK
SEL MBa

'2

'7

CONTROL
EN I

''..
'.
'.

'7

'7

JTO addr

'5
0
'5
0
'5
0
'5

'6
0
'6
0
'6

address If accumulator

Jump to sJ.)ecltled address If Timer Flag
IS set to 1.

'6
1

low.

0

a - 7)

(PC)·

Jump to specified address if Test 0 is low.

2 If TO

(OBF)·

a

Select Bank a (locations a
Program Memory.

2047) of

SEL MBl

10BF) . 1

Select Bank 1 (locations 2048
Program Memory.

SEL ABO

(BS)· a

Select Bank 0 (locations a - 7) of Data
Memory.

SEL AB1

(BS) .

Select Bank 1 (locations 24
Data Memory.

MOV A, "data

(A).

data

MOV A, Ar

(A),

(Rrl;r

MOV A,@Rr

(A)·

IIRr)); r: 0

MOV A, PSW

(A)·

(PSWJ

MOV Rr, " data

(Ad·

MOV AI', A

(Ad·- (A); r '" 0

MOV@Rr,A

((Ad)·- (Aj; r '" 0

MOV @ Ar, == data

HAd)' data; r - 0

MOV PSW, A

(PSW)· (A)

Move contents of Accumulator Into the
program status word.

MOVP A, @A

(PC 0 7) ,- (A)
(A)' ((PC))

Move data 10 the current page Into the
Accumulator.

MOVP3 A,@A

(PC a 7)· (A)
(PCB
10)~'011
(A)' ((PC))

Move Program data In Page 3 Into the
Accumulator.

MOVX A,@R

(AI -

((Rr));r '"

MOVX@A,A

({Rd)

<-

XCH A, Ar

(AI ~ (Ad; r"" a - 7

XCH A,@Ar

(A)

XCHD A,@Ar

(A 0 - 3) ~ (lAd) 0':' 3));
r '" 0- 1

Exchange Indirect 4-blt contents of
Accumulator and data memory.

CPL C

(C)·

Complement Con'tent of carry bit.

4095) of

31) of
DATA MOVES

~.

Move Immediate the speCified data Into
the Accumulator.
0

7

Move the conte.nts of the deSignated
registers Into the Accumulator
1

Move Indirect the contents of data
memory location Into the Accumulator
Move contents of the Program Status
Word into the Accumulator.

data; r : 0

7

Move Immediate the specified data mto
the designated register.

7

0

Move Accumulator Conte'lts Into the
deSignated register.
1
,.

Move Indirect Accumulator Contents
Into data memory locatIOn.
Move Immediate the speCified data Into
data memory,

1

d7

1

Move Indifect the contents of external
data memory IOto the Accumulator.

(AI;r: 0

1

Move Indirect the contents of the
Accumulator Into external data memory.
Exchange the Accumulator and
deSignated register's contents.
Exchange Indirect contents 01 Accumulator and location In data memory.

flAGS
NOT ICI

CPL Fa

(Fa) - NOT (FO)

Complement Content of Flag FO

CPL F1

1Ft)· NOT IF1)

Complement Content of Flag F1

CLR C

IC)' 0

CLA Fa

(Fa)

0

Clear content of Flag 0 to O.

CLA F1

(Ft)· 0

Clear content of Flag 1 tD O.

238

~-

Clear content of carry bit to 0

d6

d5
0

d.

0

1

,

a

((Rd); r = 0'- 1

0

NEe

NEe Microcomputers, Inc.

p.PD8253
/-,PD8253·5

PROGRAMMABLE INTERVAL TIMER
DESCR I PTiON

The NEG MPD8253 contains three independent, programmable, multi-modal 16-bit
counter Iti mers. It is designed as a general purpose device, fully compatible with the
8080 family. The MPD8253 interfaces dire.ctly to the busses of the processor as an
array of 1/0 ports.
The MPD8253 can generate accurate time delays under the control of system software.
The three independent 16-bit counters can be clocked at ratEls from DC to 3 MHz
(MPD8253-5 DC to 4 MHz). The system software controls the loading and starting of
the counters to provide accurate multiple time delays. The 'counter output flags the
processor at the completion of the time-out cycles.
System overhead is greatly improved by relieving the software from the maintenance of
timing loops. Some other common uses for the pPD8253 in microprocessor based
systems are:

FEATURES

•

Programmable Baud Rate Generator

•

Event Counter

•

Binary Rate Multiplier

•

Real Time Clock

•

Digital One-Shot

•

Complex Motor Controller

• Three Independent 16-BitCouilters
•

PIN CONFIGURATION

Clo.ck Rate: DC to 2 MHz (MPD8253)
DC to 4 MHz (MPD8253-5)

•

Count Binary or BCD

•

Single +5 Volt Supply

•

24 Dual-In-Line Plastic Package
07

VCC

PIN NAMES

06

2

23

05

3

.22

RO

04'

4

21

CS

03

5

20

Al

02

6

pPD

19

Ao

RO

Read Counter

01

7

8253/
8253-5

18

ClK 2

WR

Write Command or Data

17

OUT2

CS

Chip Select

16

GATE 2

AO,A1

Cou nter Select

ClK 1

VCC
GNO

+5 Volts

DO

8

ClK 0

9

OUT 0
GATE 0

WR

GATE 1

GNO

OUT 1

Rev/3

07-0 0
ClKN

Data Bus (8-Bitl
·Counter Clock Inputs

GATE N

Counter Gate Inputs

OUTN

Counter OOtputs

Ground

11

!-,PD8253
Data Bus Buffer
The 3-state, 8-bit, bi-directional Data Bus Buffer interfaces the ~PD8253 to the 8080A
microprocessor system. It will transmit or receive data in accordance with the INput or
OUTput instructions executed by the processor. There are three basic functions of the
Data Bus Buffer.
1. Program the modes of the ~PD8253 '
2. Load the count registers.
3. Read the count values.
Read/Write Logic
The Read/Write Logic controls the overall operation of the ~PD8253 and is governed
by inputs received from the processor system, bus.
Control Word Register
Two bits from the address bus of the processor, AO and A1, select the Control Word
Register when both are at a logic "1" (active-high logic). When selected, the Control
Word Register stores data from the Data Bus Buffer in a register. This data is then
used to control:
1. The operational MOD E of the counters.
2. The selection of BCD or Binary counting.
3. The loading of the count registers.
RD (Read)
This active-low signal instructs the ~PD8253 to transmit the selected counter value to
the processor.
WR (Write)
This active-low signal instructs the ~PD8253 to receive MODE information or counter
input data from the processor.
A1. AO
The A1 and AO inputs are normally connected to the address bus of the processor.
They control the one-of-three counter selection and address the control word register
to select one of the six operational MOD ES.
CS (Chip Select!
The ~PD8253 is enabled when an active-low signal is applied to this input. Reading or
writing from this device is inhibited when the chip is disabled. The counter operation,
however. is not affecte~.
Counters #0. #1. #2
The three identical, 16-bit down counters are functionally independent allowing for
separate MODE configuration and counting operation. They function as Binary or
BCD counters with their gate. input and output line configuration determined by the
operational MODE data stored in the Control Word Register. The system software
overhead time can be reduced by allowing the control word to govern the loading of
the count data.
The programmer, with READ operations, has access to each counter's contents. The
contains the commands and logic to read each counter's contents while still
counting without disturbing its operation.
The following is a table showing how the counters are manipulated by the input signals
to the Read/Write Log ic.

~PD8253

cs
0
0
0
0
0
0
0
0
1
0

RD
1
1
1
1
0
0
0
0

WR
0
0
0
0
1
1
1
1

A1
0
0
1
1
0
0
1
1

AD

X

X

1

1

X
X

X
X

0
1
0
1
0
1
0
1

FUNCTION
Load Counter No. 0
Load Counter No. 1
Load Counter No. 2
Write Mode Word
Read Counter No_ 0
Read Counter No.1
Read Counter No.2
No-Operation. 3-51ate
Disable, 3-State
No-Operation, 3-State

FUNCTIONAL'
DESCRIPTION

jiPD8253
BLOCK DIAGRAM

r-----------------------------~~--~
' I

I

I

I

I

I

I
I
I
I

I
I
I
I

07- 0 0 :

JLOCK 0

I

DATA
BUS
BUFFER

QUTO

II
I

I
I

I
I
I

J--+-o. ~
clock cycles; Low Period ~. clock periods, where.N is the decimal value of count
data). If the count register is reloaded with a new value during counting, the new value
will be reflected immediately after the output transition of the current count.
The OUTPUT will be held in the high state while GATE is asserted. Counting will start·
from the full count data after the GATE has been removed.

0l!!--!--L--2!6l

OuTPuT '".

,,--.J

2

~61

L--..J

2

o~

L--.J

~""~"'~--------~12~"2"~"2~
Ollf'UTI,·.,

L-.J

L----1

L--..J

Mode 4: Software Triggered Strobe
The OUTPUT goes high when MODE 4 is set, and counting begins after the second
byte of data has been loaded. When the terminal count is reached, the OUTPUT will
pulse low for one clock period. Changes in count data are reflected in the OUTPUT as
soon as the new data has been loaded into the count registers. During the loading of
new data, the OUTPUT is held high and counting is inhibited.
The OUTPUT is held high for the duration of GATE. The counters are reset and
counting begins from the full data value after GATE is removed.

"'~--------~r-----------

Mode 5: Hardware Triggered Strobe
Loading MODE 5 sets OUTPUT high. Counting begins when count data is .loaded and
GATE goes high. After terminal count is reached, the OUTPUT wi:1 pulse low for one
clock period. Subsequent trigger pulses will restart the counting ser;uence with the
OUTPUT pulsing low on terminal count following the last rising eoge of the trigger
input (Reference bottom half of timing diagram).

;;;;,l..=...J-------------------

____

~~r------------

365

II

p..PD8253
PACKAGE
~PD8253C
OUTLINE
~PD8253C-5

SPB253-10-79-CAT

366

NE'C
NEe Microcomputers, Inc.

JLPD8255
JLPD8255A·5

PROGRAMMABLE PERIPHERAL INTERFACES
DESCR I PTION

F EATU R ES

The pPD8255 and pPD8255A-5 are general purpose programmable INPUT/OUTPUT
devices designed for use with the 8080A/8085A microprocessors_ Twenty-four (24)
I/O lines may be programmed in two groups· Of twelve (group I and group II) and used
in three modes of operation. In the Basic mode, (MODE 0), each group of twelve I/O
pins may be programmed in sets of 4 to be in~ut or output. In the Strobed mode,
(MODE 1), each group may be prqgrammed to have 8 lines of·input or output. Three
of the remaining four pins in each group are used for handshaking strobes and interrupt
control signals. The Bidirectional Bus mode, (MODE 2), uses the 8 lines of Port A for
a bidirectional bus, and five lines from Port C for bus control signals. The pPD8255
and pPD8255A-5 are pa<;kaged in 40 pin plastic dual-in-line packages.

• Fully Compatible with the 8080A!8085 Microprocessor Families
•

PIN CONFIGURATION

All Inputs and Outputs TTL Compatible

•

24 Programmable I/O Pins

•

Direct Bit SET/RESET Eases Control Application Interfaces

•

8 - 2 mA Darlington Drive Outputs for Printers and Displays (pPD8255)

•

8 - 4 mA Darlington Drive O.utputs for Printers and Displays (pPD8255A-5)

•

LSI Drastically Reduces System Package Count

•

Standard 40 Pin Dual-in-Line Plastic and Ceramic Packages

PA3
PA2
PAl
PAo
RO

CS
GNO
A,
AO
PC7
PCa
PCs
PC4
PCo
PC,
PC2
PC3
PBO
PB,

PA4
PAS
PAa
PA7
WR
RESET
DO
0,
02
03
04
05
Oa
07
VCC
PB7
PBa
PBS
PB4
PB3

IlPD
8255/
8255A-5

P~2

PIN NAMES
07-0 0
RESET

Data Bus (Bi·Directional)
Reset Input

CS

Chip Select

Ri'i

Read Input

WR

Write Input

Ao. Al
PA7-PAO

Port Address

PB7-PBO

~ort A (Bid
Port B (Bid

PC7-PCO

Port C (Bid

Vee

+5 Volts

GNO

o Volts

Revl2

367

JLPD8255/8255A·5
General
FUNCTIONAL DESCRIPTION
The ~PD8255 and ~PD8255A·5 Programmable Peripheral Interfaces (PPI) are designed
for use in 8080A/8085A microprocessor systems. Peripheral equipment can be effectively
and efficiently interfaced to the 8080A/8085A data and control busses with the~PD8255
and ~PD8255A·5. The ~PD8255 and ~PD8255A·5 are functionally configured to be
programmed by system software to avoid external logic for peripheral interfaces.
Data Bus Buffer
The 3·state, bidirectional, eight bit Data Bus Buffer (DO·D7) of the ~PD8255 and
~PD8255A·5 can be directly interfaced to the processor's system Data Bus (DO·D7).
The Data Bus B,uffer is controlled by execution of IN and OUT instructions by the
processor. Control Words and Status information are also transmitted via the Data Bus
Buffer.
ReadlWrite and Control Logic
This block manages all of the internal and external transfers of Data, Control and
Status. Through this block, the processor Address and Control busses can control the
peripheral interfaces.
Chip Select, ~, pin 6
A Logic Low, VIL. on this input enables the ~PD8255 and
munication with the 8080A/8085A.

~PD8255A·5

for com·

Read, RD, pin 5
A Logic Low, VIL. on this input enables the ~PD8255 and ~PD8255A·5 to send Data
or Status to the processor via the Data Bus Buffer.
Write, WR, pin 36
A Logic Low, VIL, on this input enables the Data Bus Buffer to receive Data or Con·
trol Words from the processor.
Port Select 0, AO, pin 9
Port Select 1, A1, pin 8
These two inputs are used in conjunction with CS, RD, and WR to control the selec·
tion of one of three ports on the Control Word Register. AO and A1 are usually
connected to AO and A1 of the processor Address 8us.
Reset, pin 35
A Logic High, VIH, on this input clears the Control Register and sets ports A, B, and
C to the input mode. The input latches in ports A, B, and C are not cleared.

, ."

Group I and Group II Controls
Through an OUT instruction' in System S.oftware from'the processor, a control word
is transmitted to the ~PD825p and ~PD8255A·5. Information such as "MODE,"
"Bit SET," and "Bit RESET" is used to initialize the functional configuration of each
I/O port.
Each qroup (I and II) accepts "commands" from the ReadIWrite Control Logic and
"control words" from the internal data bus and in turn controls its associated I/O
ports.
Group I - Port A and upper Port C (PC7·PC4)
Group II - Port B and lower Port C (PC3·PCO)
While'the Control Word Register can be written into, the contents cannot be read back
to the processor.
Ports A, B,and C
The three 8·bit 'I/O ports (A, B, and C) in the ~PD8255 and ~PD8255A·5 can all be
configured to meet a wide variety of functional requirements through system software.
The effectiveness and flexibility of the ~PD8255 and ~PD8255A·5 is further
enhanced by special features unique to each of the ports.
Port A = An 8·bit data output latch/buffer and data input latch.
Port B = An 8·bit data input/output latch/buffer and an 8·bit data input buffer.
Port C = An 8·bit output latch/buffer and a data input buffer (input not latched).
Port C may be divided into two independent 4·bit control and status ports for use with
Ports A and B.

368

fL PD8255/8255A·5
TIMING WAVEFORMS
(COI\IT.)

WR-----"

MODE 1

OBF

INTR

------I--+-+.....,j
------If-""'-Il

ACR ------If------~-'\.I

OUTPUT TO PERIPHERAL

tST--lv--._ _ _ _ _ _ _ _ _- .____
STB FROM PER IPHERAL

IBF ________-'I

INTR _ _ _ _ _ _ _ _ _ _ _

~..,

R6----------4--4-~~I~--~::::::t--INPUT FROM
PER IPHERAL

WRITE
DATA FROM

MODE 2

~PD8080A

TO

~PD8255

AND

~PD8255A

tAOB

INTR

ACK FROM PERIPHERAL

STB FROM PERIPHERAL

IBF

-----------'1

PERIPHERAL ______ {~==~~~
BUS
-.

tRIB

RD------~-------~~----"'\.
DATA FROM
PERIPHERAL TO ~PD8255
AND ~PD8255A-5

Note:



Tracking Specification

®
®

o

378

Load = 1 TTL

= 1 TTL + tRL =3.3KI, VOH

< 50ns
< 50ns
HOCT < 50 ns

HAK

HOGl

= 3.3V

TIMI-NG WAVEFORMS
DMA (MASTER) MODE

'~CONTROl OVERRIDE SEQUENCE

CLOCK

CLOCK

Tas

---------

DR00-3

'1RD

DRClQ..3

HRD
-'""\

'-----

HLDA

AEN

HLOA

AEN

------------

AODO_7
tlOWERADRI

-------~-

ADDSTB

----- -----------------

ADR STB

i5AC'K0-3

DACKQ·3

MEMRD/i'iO'""'FiD ___
~EMWR/i'ii)"'Wii'

OATAo_7
tUPPER ADAI

MEMAD/i7O"'RD

___

MEMWR/i'iO"WR
T AS

TRS

READY ___

TC/MARK___

FLrTAK

READY

c--\

tS

c--\

"

---TC/MARK

1::

."

C

C»

N)

en

(,)

-...

~

II

,uPD8257
Internally the 8257 contains six different states (SO, S1, S2, S3, S4 and SW). the
DMA OPE RATION
duration of each state is determined by the input clock. In the idle state, (S1). no DMA
operation is being executed. A DMA cycle is started upon receipt of one or more DMA
Requests (DRO n ). then the 8257 enters the SO state. Duri,ng state SO a Hold Request
(HRO) is sent to the 8080 and the 8257 waits in SO until the 8080 issues a Hold
Acknowledge (HLDA) back. During SO, DMA Requests are sampled and DMA priority
is resolved (based upon either the fixed or priority scheme). After recei~t of HLDA, the
DMA Acknowledge line (DACK n ) with the highest priority is driven low selecting that
particular peripheral for the DMA cycle. The DMA Request line (DR an) must remain
high until either a DMA Acknowledge (DACK n ) or both DACK n and TC (Terminal
Count) occur, indicating the end of a block or sector transfer (burst mode).
The DMA cycle consists of four internal states; Si, S2, S3 and S4. If the access time
of the memory or I/O device is not fast enough to return a Ready command to the
8257 after it reaches state S3, then a Wllit state is initiated (SW). One or more than
one Wait state occurs until a Ready signal is received, and the 8257 is allowed to go
into state S4.Either the extended write option or the DMA Verify mode may
eliminate any Wait state.
If the 8257 should lose control ofthe system bus (i.e., H LDA goes low) then the
current DMA cycle is completed, the device goes into the S 1 state, and no more
DMA cycles occur until the bus is reacquired. Ready setup time (tRS), write setup
time hDW). read data access time (tRD) and H LDA setup time has) should all be
carefully observed during the handshaking mode between the 8257 and the 8080.
During DMA write cycles, the I/O Read (I/O R) output is generated at the beginning
of state S2 and the Memory Write (MEMW) output is generated at the beginning of
S3. During DMA read cycles, the Memory Read (iiiiEiViR) output i~ generated at the
beginning of state S2 and the I/O Write (I/O W) goes low at the beginning of state S3.
No Read or Write control signals are generated',during DMA verify cycles.

RESET

Notes:

380

 V OUT > GND + 0.45V

CAPACITANCE

Ta = 25°C; VCC = GND = OV
PARAMETER

LIMITS

SYMBOL
MIN.

I nput Capacitance

1/0 Capacitance

UNIT

TYP.

TEST CONDITIONS

MAX.

CIN

10

pF

fc= 1 MHz

ClIO

20

pF

Unmeasured pins
returned to GND

PACKAGE OUTLINE
I.IPD8257C
I.IPD8257C-5

ITEM

MILLIMETERS

INCHES

A
B
C
D

51.5 MAX
1.62
2.54 ± 0.1
0.5 ± 0.1
4S.26
.1.2 MIN
2.54 MIN
0.5MIN
5.2.2 MAX
5.72 MAX
15.24
13.2

2.02S MAX
0.064
0.10 ± 0.004
0.019± 0.004
1.9
0.047 MIN
0.10MIN
0.019 MIN
0.206 MAX
0.225 MAX
0.600
0.520
+ 0.004
0.010
- 0.002

E
F

G
H
I
J
K
L
M

0.25 + 0.1
- 0.05

SP8257 -1-80-CAT

382

!\fEe
NEe Microcomputers, Inc..

JLPD8259
J.L PD8259·5.··

PROGRAMMABLE INTERRUPT CONTROLLER

OESCR I PTI ON

F EATU RES

The NEC IlPD8259 is a programmable interrupt controller directly.compatible with the
80aOA!~85A/IlPD780(Z80TM). It can .service eight levels of interrupts and contains
on-chip logic to expand interrupt capabilities up to sixty-four, lev.els with the addition
of other.IlPD8259's. The user is offered a selection of prlorii:y algodthms to tailor the
priority processing to meet his systems requirements. These algorithms can be dynlllT)- .
ically modified during oper,.tion, eXPllnding.the versatility of the microprocessor
system.

• Eight Level Priority Controller
Programmable Base Vector Address
Expandable to 64 Levels
Programmable Interrupt Modes .(Algorithms)
Individual Request Mask Capability
Single +5V Supply (No Clocks)
Full Compatibility with 8O80A/IlPD7BO(Z80™)
IlPD8259-5 Compatible with B085A Speeds
Available in 28 Pin Plastic an~ Ceramjc Packages.

•
•
•
•
•
•
•
•

cs

PIN CONFIGURATION

.vcc

WR

AO

AD

iN-i'A

07

IR7

Os

IR6

PIN NAMES
D7- Dn
RD
WR

05

IR5

04

'IR4

AO
CAS2-CASO

03.
02

IR3

SJ5

IR2

01

IR1

DO

IRO

INT
INTA
IRO-IR7

CASO

INT

CAS1

SP

GND

CAS 2

~

Data Bus (Bi-Directional) :.
Read Input
Write Input
Command Select Address
Cascade Lines
Slave Program Input
Interrupt Output
Interrupt Acknowledge Input
Interrupt Request Inputs
Chip Select

TM: Z80 i. a registared trademark of Zilog, Inc.

383

II

f"P 08259
INTERRUPT REQUEST REGISTER URR) AND IN-SERVICE REGISTER /lSR)
The interrupt request register and in-service register store the in-coming interrupt
request signals appearing on the IRO-7 lines (refer to functional block diagram). The
inputs requesting service are stored in the I RR while the interrupts actually being
serviced are stored in the ISR.
A positive transition on an IR input sets the corresponding bit in the Interrupt Request
Register, and at the same time the INT output of the J.lPD8259 is set hi9.h. The IR input
line must remain high until the first iNTA input has been received. Multiple, nonmasked interrupts occurring simultaneously can be stored in thelRR. The incoming
INTA sets the appropriate ISA bit (determined by the programmed interrupt algorithm)
and resets the corresponding IRR bit. The ISR bit stays high-active during the interrupt
service subroutine until it is reset by the programmed End-of-Interrupt (EOI) command.
PRIORITY RESOLVER
The priority resolver decides the priority of the interrupt levels in the IR R. When the
highest priority interrupt is determined it is loaded into the appropriate bit of the
In-Service register by the first 'iNTA pulse.
DATA BUS BUFFER
The 3-state, B-bit, bi-directional ddta bus buffer interfaces the J.lPD8259 to the
processor's system bus. It buffers the Control Word and Status Data transfers between
the J.lP08259 and the processor bus.
READJWRITE LOGIC
The read/write logic accepts processor data and stores it in its Initiali~ation:Command
Word (lCW) and Operation Command Word (OCW) registers. It also controls the
transfer of the Status Data to the processor's data bus.
CHIP SELECT (CS)
The J.lPD8259 is enabled when an active-low signal is received at this input. Reading
or writing of the J.lPQ8259 is inhibited when it is not selected.
WRITEIWfU
This active· low signal instructs the J.lPD8259 to receive Command Data from the
processor.
READ

(RD)

When an active-low signal is received on the RD input, the status of the Interrupt
Request Register, In-Service Register, Interrupt Mask Register or binary -code of the
Interrupt Level is placed on the data bus.
INTERRUPT (lNT)
The interrupt output from the J.lPD8259 is directly connected to the processor's INT
input. The voltage levels of this outpUt are compatible with the 8080's input voltage
/, and timing requirements.
\'

.

,; :i"I~TERRUPT MASK REGISTER (lMR)
The interrupt mask register stores the bits for the individual interrupt bits to be masked.
The IMR masks the data in the ISR. Lower priority lines afe not affected by masking a
higher priority line.

384

BASIC FUNCTIONAL
DESCRIPTION

J.l.PD8259
FUNCTIONAL DESCRIPTION
(CONT.)

INTERRUPT ACKNOWLEDGE (lNTA)
The interrupt acknowledge signal is usually received from the 8228 (system controller
for the 8080A),' The system controller generates three INTA pulses to signal the 8259
to issue a 3-byte CA LL instruction onto the data bus.
AO
AO is usually connected to the processor's address bus. Together with WR and RD
signals it directs the loading of data into the command register or the reading of
status data. The following table illustrates the basic operations performed. Note that
it is divided into three functions: Input, Output and Bus Disable distinguished by the
RD, WR, and Cs inputs.

~PD8259

AO

D4

D3

0
1

BASIC OPERATION

RD

WR

CS

PROCESSOR INPUT OPERATION (READ)

0
0

1
1

0
0

IR R, ISR or IR -+ Data. Bus 

FUNCTION

The contents of OCW2 written prior to the READ operation governs the
selection of the IRR, ISR or Interrupt Level.
The sequencer logic on the ~PD8259 aligns these commands in the
proper order.

CASCADE BUFFER/COMPARATOR. ~ForUse- in Multiple ~PD8259 Array.}
The ID's of all ~PD8259's are buffered and compared in the cascade buffer/ comparator. The master ~PD8259 will send the ID of the interrupting slave device along
the CASO, 1, 2 lines to all slave devices. The cascade buffer/comparator compares its
preprogrammed ID to the CASO, 1, 2 lines. The next two iiiiTA pulses strobe the preprogrammed, 2 byte CALL routine address onto the data bus from the slave whose ID
matches the code on the CASO, 1, 2 lines.

SLAVE PROGRAM (SP). (For Use in

Multiple~PD8259 Array.)

The interrupt capability can be expanded to 64 levels by cascading multiple ~PD8259's
in a master-plu9-slaves array. The master controls the slaves through the CASO, 1, 2
lines. The SP input to the device selects the CASO-21ines as either outputs.(SP=1) for
the master or as inputs (SP=O) for the slaves. For one device ~nly the SP must be set
to a logic "1" since it is functioning as a master.

385

II

fLPD8259
BLOCK DIAGRAM

PROCESSOR PROCESSOR PROCESSOR
ADDRESS
CONTROL
DATA

INTERNAL

BUS

WS
SLAVE_
PROGRAM CASCADE

Operating Temperature .....
Storage Temperature ..
Voltage on Any Pin . . . . . . . . . . .
Power Dissipation ... .
Note:

.•....... , O°C to +70°C
..... -65°C to +125°C
-0.5 to +7 Volts
1W

ABSOLUTE MAXIMUM
RATINGS*



Decoded Sc~n·Sensor Matrix

0

Strobed Input, Decoded Display Scan
Program Clock

i

I~

...

Where PPPPP is the presealer value between 2 and 3,. this presealer divides the ·external
clock by PPPPP to develop its internal frequency. After reset,. a default value of 31 is
generated.
Read FIFO/Sensor RAM
101110lA11xIAIAIAI

AO=O

AI is the auto-increment flag. AAA is the row to be read by the processor. The read
command is acc6mplished with (Cs . RD . Ali) by the processor. If AI is 1, the row
select counter will be incremented after each read. Note that auto-incrementing has
no effect 01') the display.
Read Display RAM

Where AI is the auto-increment flag and AAAA is the character which the processor
is about to read.
Write Display RAM
[i]oloIAlIAIAIAIAI
where AAAA is the character the processor is about to write.
Display Write Inhibit Blanking

ttl 11 I~r~wl ~ll~l I
X

Where IWA and IWB are Inhibit Writing nibble A and B respectively, and BLA, BlB
are blanking. When using the display as a dual 4-bit, it is necessary to mask one of the
4-bit hal.ves to.eliminate interaction between the two halves. This is accomplished with
the IW flags. The Bl flags allow the programmer to blank either half of tile display
independently, To blank a displaY formatted as a single B-bit, it is necessary to set
both BlA and BlB. Default after a·reset is all zeros. All sig~als are ac.tive high (1).

405

p.P 08279·5
Clear
0 I CD I CD I CD I CF I CA
CD

CD
0

1
1
0

CD

X

All zeros
AB = 2016
All ones
Disable clear display

0
1

X

X

This command is used to clear the display RAM, the FIFO, or both. The CD options
allow the user the ability to clear the display RAM to either all zeros or all ones.
CF clears the FIFO.
CA clears all.
Clearing the display takes one complete display scan. During this time the processor
can't write to the display RAM.
CF will set the FIFO empty flag and reset I RO. The sensor matrix mode RAM pointer
will then be set to row O.
CA is equivalent to CF and CD. The display is cleared using the display clear code
specified and resets the internal timing logic to synchronize it.

End Interrupt/Error Mode Set
1111111ElxlxlxlxI
In the sensor matrix mode, this instruction clears IRO and allows writing into RAM.
In N key rollover, setting the E bit to 1 allows for operating in the special Error mode.
See Description of FIFO status~

FIFO Status
I DU I S/E I 0 IU I FIN I N N
Where: DU = Display Unavailable because a clear display or clear all command is in
progress.
S/E = Sensor Error flag due to multiple closure of switch matrix.
o = F!FO Overrun since an attempt was made to push too many
characters into the FI FO.
U = FIFO Underrun. An indication that the processor tried to read an
empty FIFO.
F = FIFO Full Flag.
NNN = The Number of characters presently in the FIFO.
The FIFO Status is Read with AO high and CS, RD active low.
The Display not available is an indication that the CD or CA command has not
completed its clearing. The S/E flags are used to show an error in multiple closures has
occurred. The 0 or U, overrun or underrun, flags occur when too many characters are
written into the FIFO or the processor tries to read an empty FI FO. F is an indication
that the FIFO is full and NNN isthe number of characters in the FIFO.

Data Read
Data can be read during AO = 0 and when CS, .AD are active low. The source of the
data is determined by the Read Display or Read FIFO commands.

Data Write
Data is written to the chip when AO, CS, and WR are active low. Data will be written
into the display RAM with its address selected by the latest Read or Write Display
command.

406

COMMAND OPERATION
(CONT.)

J.L P 08279·5
Data Format

COMMAND OPERATION
(CO NT.)
iCNTLi

SH

: SCAN:

In the Scanned Key mode, the characters in the FIFO correspond to the above format
where CNTL and SH are the most significant bits and the SCAN and return lines are
the scan and column counters.

I

I

R L7

I

R L6

I

R L5

R L4

I

R L3

I

R L2

I

R L1

I

R La

I

In the Sensor Matrix mode, the data corresponds directly to the row of the sensor
RAM being scanned. Shift and control (SH, CNTL) are not used in this mode.

Control Address Summary
DATA
MSB

LSB

a

a

a

a

a

a

a

a

a

a

a

a

0

0

K

K

K

Keyboard Display Mode Set

P

P

P

P

P

Load Program Clock

Al

X

A

A

A

Read FIFO/Sensor RAM

Al

A

A

A

A

Read Display RAM

I Al

A

A

A

A

Write Display RAM

I
I

a

Display Write Inhibit/Blanking

I I

a

I CD I CD I CD I CF I CA I

Clear

I I I I I I
LiJ
lou I I u I
I I I
X

E

0

S/E

PACKAGE OUTLINE
J.LPD8279C-5

I

X

X

X

End Interrupt/Error Mode Set

FIN

N

N

FIFO Status
I

~K

'

:IL~

"ii\lm~V~ll\lu\I1MMl\l\i\)vr~'
}M __~JI~
-.:..j81
ct -tr
A

I

....

I

·F

0°_15°

(Plastic)
ITEM

MILLIMETERS

A

51.5 MAX

1.62
2.54

D

0.5 ± 0.1

E

1.

0.1

48.26

0.10 ± 0.004
0,019 ± 0.004
1.9

F

1.2~IN

0.047 MIN

G

2.54 MIN

0.10 MIN

H

O.5MIN

0.019 MIN

I

5.22 MAX

0.206 MAX

J

5.72 MAX

0.225 MAX

K

15.24

L

13.2

M

0.25

II

0.064

C

B

INCHES
2.028 MAX

0.600
0.520

+ 0.1
0.05

0.010

+ 0.004
0.002

SP8279-9-78-G N-C AT

407

NOTES

408

NEe

NEe Microcomputers, Inc.

JLPD8355
JLPD8755A

16,384 BIT ROM WITH 110 PORTS
16,384 BIT EPROM WITH 1/0 PORTS

DESCRIPTION

FEA TU RES

The /lPD8355 and the /lPD8755A are /lPD8085A Family components with the
/lPD8355 containing 2048 X 8 bits of mask ROM and the J.LPD8755A containing
2048 X 8 bits of mask EPROM for program development. Both components also con·
tain two general purpose 8·bit 110 ports. They are housed in 40 pin packages, are
designed to directly interface to the /lPD8085A and are pin for pi~ compatible to each
other.

• 2048 X 8 Bits Mask ROM (/lPD8355)
•
•
•
•
•
•
•
•

PIN CONFIGURATIONS

2048 X 8 Bits Mask EPROM (/lPD8755A)
2 Programmable 110 Ports
Single Power Supplies: +5V
Directly Interfaces to the /lPD8085A
Pin for Pin Compatible
J.LPD8755A: UV Eraseable and Electrically Programmable
J.LPD8355 available in Plastic Package
J.LPD8755A Available in Ceramic Package

CE

vcc

CE

vcc

CE
CLK
RESET
NC
READY

PB7
PBS
PB5
PB4
PB3
PB2
PB1
PBo
PA7

CE
CLK
RESET
VDD,
READY

PB7
PBS
PB5
PB4
PB3
PB2
PB1
PBo
PA7
PAS

101M

loR

AD
iQvii

ALE
ADO
AD1
AD2
AD3
AD4
AD5
ADS
AD7
VSS

"PO
8355

PAs
PA5
PA4
PA3
PA2
PA1
PAO
AlO
Ag
AS

101M

lOR
RD
lOW
ALE
ADO
AD'1
AD2
AD3,
AD4
AD5
ADS
AD7
VSS

J.LPO
8755A

P.6.5

PA4
PAl
PA2
PA1
PAO
AlO
Ag
AS

NC: Not Connected

409

II

p.PD8355/8755A

The IlPD8355 and IlPD8755A contain 16,384 bits of mask ROM and EPROM
respectively, organized as 2048 X 8. The 2048 word memory location may be
selected anywhere within the 64K memory space by using the upper 5-bits of
address from the IlPD8085A as a chip select.

FUNCTIONAL DESCRIPTION

The two general purpose I/O ports may be programmed input or output at any
time. Upon power up, they will be reset to the input mode.
vDDCD

VCC (+5V)

BLOCK DIAGRAM

8
AD7 - ADD ---;-..
A1O' A8
READY
CE
CE
ALE

2048 X 8
ROM

RD
lOW
lOR
CLK-

loiM
RESET

G

8

G

8

PA7·PAO

PB7 - PBo

VSS (OV)
Note: CD VDD applies to IlPD8755A only.

Operating Temperature (MPD8355). . . . . . . . . . . . . . . . . . . . . . .. O°C to +70°C
(MPD8755A) . . . . . . . . . . . . . . . . . . . . -10°C to +70°C
Storage Temperature (Ceramic Package) . . . . . . . . . . . . . . . . . , -65°C to +150o C
(Plastic Package). . . . . . . . . . . . . . . . . .. -40°C to +125°C
Voltage on Any Pin (MPD8355). . . . . . . . . . . . . . . . . . . . . . . -0.3 to +7 Volts CD
(JLPD8755A) . . . . . . . . . . . . . . . . . . . . . -0.5 to +7 Volts CD
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " 1.5W
Note:

CD

ABSOLUTE MAXIMUM
RATINGS*

With Respect to Ground

COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied.' ,Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
.

*Ta=25°C

DC CHARACTERISTI.CS

Ta" DoC to +70°C; VCC ~ 5V ± 5%
LIMITS
PARAMETER

SYMBOL

MIN

Input Low Voltage

VIL

-0.5

Input High Voltage

VIH

2.0

TYP

MAX

UNIT

TEST
CONDITIONS

= 5.ovCD
= 5.0V:(j)
IOL = 2 rnA

0.8

V

VCC

VCC+0.5

V

VCC

Output Low Voltage

VOL

Output High Voltage

VOH

I nput Leakage

IlL

10

IlA

VIN

Output Leakage Current

ILO

±10

IlA

0.45V "VOUT "VCC

VCC Supply Current

ICC

0.45

Note: CD These conditions apply to IlPD8355 only.

410

V

V

2.4

180

rnA

IOH =-400IlA

=VCC to OV

fLPD8355/8755A

PIN IDENTIFICATION
NO.

PIN
SYMBOL

1,2

CE, CE

Chip Enables

Enable Chip activity for
memory or I/O

NAME

FUNCTION

3

ClK

Clock Input

Used to Synchronize Ready

4

Reset

Reset Input

Resets PA and PB to all inputs

5CD

NC

Not Connected

5~

VDD

Programming
Voltage

Used as a programming voltage,
tied to +5V normally

6

Ready

Ready Output

A tri·state output which is
active during data direction
register loading

7

10/M

I/O or Memory
Indicator

An input signal which is used
to indicate I/O or memory
activity

B

lOR

I/O Read

I/O Read Strobe In

9

RD

Memory Read

MemoryRead Strobe In

10

lOW

I/O Write

1/0 Write Strobe In

11

ALE

Address low
Enable

Indicates information on
Address/Data lines is valid

12-19

ADO-AD7

low Address/Data
Bus

Multiplexed low Address and
Data Bus

20

VSS

Ground

Ground Reference

21-23

As-A 10

High Address

High Address inputs for ROM
reading

24-31

PAO-PA7

Port A

General Purpose I/O Port

32-39

PBO-PB7

Port B

General Purpose I/O Port

40

Vce

5V Input

Power Supply

Notes: CD MPDS355
. ~ MPDS755A

I/O PORTS

I/O Port activity is controlled by performing I/O reads and writes to selected 1/0 port
numbers. Any activity to and from the MPDS355 requires the chip enables to be active.
This can be accomplished with no external decoding for mUltiple devices by utilizing
the upper address lines for chip selects. CD Port activity is controlled by the following
1/0 addresses:
AD1

ADO

0

0

PORT SELECTED
A

FUNCTION
Read or Write PA

0

1

B

Read or Write PB

1

0

A

Write PA Data Direction

1

1

B

Write PB Data Direction

Since the data direction registers for PA and PB are each S-bits, any pin on PA or PB
may be programmed as input or output (0 = in, 1 = out).
Note:

CD During ALE time the data/address lines are duplicated on A15-AS.
411

JA-PD8355/8755A
T a'" O"c to +70°C' Vee"" 5V + 5%

AC CHARACTERISTICS

LIMITS
PARAMETER

SYMBOL

MIN

'eve

320

elK Pulse Width

T2

120

eLK Rise and Fall TIme

If. Ir

Address to Latch Set Up T'ime

tAL

Clock Cycle Time
eLK Pulse Width

TYP

TEST
MAX

UNIT

BO

CONDITIONS

CLOAD'" 150 pF

30
50

Address Hold Time After Latch

tLA

BO

Latch to READfWAITE Control

tlC

100

Valid Data Out Delay from READ Control

tAD

~

400_C+_-----j 150 pF Load
f--:-Add-,-"co"_S,,.,.b-,",,',.,'-,-0,_,,_0_"_,V_'_"d_ _ _t-...:'A"O'--+~C+_-+_
Latch Enable Width

100

ILL

100

Data Bus Float Alter READ

'ROF

READ/WAITE Control to Larch Enable

tel

20

READ/WRITE Control Width

tce

250

Data In to WRITE Set Up TIme

lOW

150

Data In Hold Time After WAITE

two

103

WRITE to Port Output

twp

POrt Input Set Up Time

tpR

50

POrt Input Hold Time

IA P

50

400

~
,-------------------+--t--f-"-=-j------1
READY HOLD TIME

tAYH

ADDRESS ICE) to FlEADY

'ARY
IRV

Data Out Delay from READ Control

IRDE

NOles

CD

@

,",P08355
j.!P08755A

@

160

300

Recovery T,me Between Controls

10

30 n5 for j.!PD8755A

ROM READ, I/O READ AND WRITE (j)
elK

TIMING WAVEFORMS.

CtCy/r---\~\'__...JIr----,r=Tl=fT2'-

DATA

tee

tow

PROM READ, I/O READ AND WRITE @
ADDRESS

~-.J"f-_--D-A-T-A--_Jf" - - - . . (
ALE

Notes:

(i) I'PD8355

@

®
412

tee

I'PD8755A
CE must remain low for the entire cycle

ADDRESS } .

",PD835518755A
TIMING WAVEFORMS
(CONT.)

CLOCK

If

WAIT STATE TIMING (READY = 0)
elK

ICE = 1).

ICE

=

01

ALE

I/O PORT

INPUT MODE'

--V
...1\___________

DAT.A----- -.
BUS _ _ _ _ _ _ _

OUTPUT MODE,

EPROM PROGRAMMING
J,lPD8755A

Erasure of the JlPD8755A occurs when exposed to ultraviolet light sources of wavelengths less than 4000A. It is recommended, if the device is exposed to room
fluorescent li. ghting or direct sunlight, that opaque labels be placed over the window to
prevent exposure. To erase, expose the device to ultraviolet light at 2537 A at a
minimum of 15 W-sec/cm 2 (intensity X expose time). After erasure, all bits are in the
logic 1 state. Logic O's must be selectively programmed into the desired locations. It
is recommended that NEC's prom programmer be used for this application.

413

JLPD8355/8755A

A. I
~K==r1

------A---,-------II

l~1

1-1

r----------------h-.
1-f'l-.f"l-{"l--rH<--n-4n-<1--ffi--m-.f"l-{"l--rH<--n-4n-<.............f"il-I

I

J_

J -

-

G

- -

M

- -

OD _ 15D

--

PACKAGE OUTLINE
#-,PD8355C
#-,PD8755AD

I---

Plastic
ITEM

MILLIMETERS

A
8

51.5 MAX
1.62

C
0

E
F
G
H
I
J

INCHES
2_028 MAX
0.064

2.54;t 0.1

0.10± 0.004

0.5±0.1

0.019 ± 0.004

48.26
1.2 MIN

1.9
0.047Mm

2.54 MIN

0.10 MIN

0.5MIN
5.22 MAX

0.019 MIN
0.225 MAX

K

5.72 MAX
15.24

L

13.2

0.520

+0.1
0.25 _ 0.05

M

0.206 MAX
0.600
+ 0.004
0.010 _ 0.002

G

F

I---------E-------~

Ceramic
ITEM
A
B
C

0
E
F
G
H
I

J
K
L
M

MILLIMETERS

INCHES

51.5 MAX.
1.62 MAX.
2.54 ± 0.1
0.5 ± 0.1
48.26 ± 0.1
1.02 MIN.
3.2 MIN.
1.0MIN.
3.5 MAX.
4.5 MAX.
15.24 TVP.
14.93 TVP;
0.25 ± 0.05

2.03 MAX.
0.06 MAX.
0.1 ± 0.004
0.02 ± 0.004
1.9 ± 0.004
0.04 MIN.
0.13MIN.
0.04 MIN.
0.14 MAX.
0.18 MAX.
0.6 TVP.
0.59 TVP.
0.01 ± 0.00111

SP8355/8755A-l0-79-CAT

414

NEe

NEe Quality Assurance
Procedures

Manufacturing
Operation

One of the important factors
contributing to the final quality of
our memory and microcomputer
components is the attention
given to the parts during the
manufacturing process. All
Production Operations in NEC
follow the procedures of MI L
Standard 883A. Of particular
importance to the reliability
program are three areas that
demonstrate NEC's commitment
to the production of components
of the highest quality.

Wafer

Visual
Inspection
Method
2010.2 Condo B

I. Burn,ln ~AII memory and
microcomputer products are
dynamically burned in at an
ambient temperature sufficient to
bring the junction to a temperature
of 150°C. The duration of the
burn-in is periodically adjusted
to reflect the production history
and experience of N EC with each
product. 100% of all N EC memory
and microcomputer products
receive an operational burn-in
stress.
II. Electrical Test - Memory and
microcomputer testing at NEC is
not considered a statistical game
where the device is subjected to a
series of pseudo random address
and data patterns. Not only is this
unnecessarily time consuming,
but it does not effectively
eliminate weak or defective parts.
N EC's test procedures are based
on the internal physical and
electrical organization of each
device and are designed to
provide the maximum electrical
margin for solid board operation.
For further information on
N EC's testing procedures see your
local N EC representative.
III. After completion of all
100% test operations, production
lots are held in storage
until completion of two groups
of extended sample testing: an
operating life.test and a series
of environmental tests. Upon
successful completion of
these tests, the parts are released
'from storage and sent to final
a.A. testing.

r- --- - -~- -- -~---

A
I

•
I
I

I

I

I

A
L ____

~-_

NEe Microcomputers, Inc.

415

NEe

NEe Microcomputers, Inc.
NORTH AMERICAN REGIONAL SALES OFFICES
E.lI8rn
275 Broadhollow Ad; 'At. j 10
Melville NY 11747
516/293-5660

Midwest.."
5105 Tollview Drive
Aolling Meadows I L 60008
312/298-7081

Northeast.. "
21 G Olympia Avenue
Woburn MA 01801
617/935-6339

Southern
We• •"
14330 Midway Aoad, Suite 225 2914 E. K.tella Ave.
Delles TX 75234
Orange CA 92667
214/980-6976
714/633-2980

U.S. REPRESENTATIVES
AI....m.
20th Cantury Marketing, Inc.
Huntsville AL
205/772-9237

Illinois
Technology Sales, Inc.
Palatine I L '
312/991-6800

Arizona

Advanced Technical Sale.
Overland Perk KS
913/492·4333

Eltron
Phoenix AZ
802/997-1042
Ark.nsa.
Action Unlimited
Arlington TX

817/461-8039

Indiana
Technology S.les, Inc.
Palatine IL
312/991-6600,

Iowa

California

Electronic Innovators. Inc.

Cerea

Minneapolis MN
612/835'()303

San DiegoCA

Minnesota

North Carolina
Wolffs Electronic Sales, Inc.

Utah

612/835'()303

Aaleigh NC
919/851-2800

'Salt Lake City UT
801/486-4251

Mississippi

North Dakota

V.mont
Contact Sales, Inc,

Electronic Innovators, Ino.
Minneapolis MN

20th Century Merketing, Inc.
Huntsville AL
205/772-9237

Missouri
Advanced Technical Sales
, Overland Park KS
913/492-4333
Montana

Tri·Tronix, N.W.
Mercer Island WA

206/232-4993

714/560-9143
Kansas
Santana Sales
Los Alamitos CA
714/827-9100
Trident AlIOciate... Inc.

Sunnyvale CA
408/734-5900
Colorado
D/Z Associates, Inc.
Denver CO
303/534-3649
Connecticut
HLM Associates, Inc.
Torrington CT

203/482-6680
District of Columbia
Professional
Representatives, Inc.

Advanced Technical Sales
Overland Park KS
913/492-4333

N... raska

Electronic Innovators, Inc.
Minneapolis MN

612/835'()303

Burlington MA
617/273-1520

Ohio
Imtech, Inc.
Akron OH
216/666-1185
Dayton OH

Weshington
Tri·Tronix, N.W.
Mercer Island WA
206/232-4993

513/278-6507

West Virginia
l!"('Itsch, Inc.
Dayton OH
513/278-6507

Okl.homa
Action Unlimitad
Arlington,tx
817/46,1-8039

0,,,,,,,,,,

Overland Park KS
913/492-4333

TtFrlonix' N.W.
Wils,?nvill.;'OA

612/835'()303

503~2"'2<123

Technology Sales

Palatine IL
312/991·6600

Imtech, Inc.

Nevada

Pennaylvania

Dayton OH
513/278-6507

Eltron

Imtecb, Inc.
Akron OH
2.16/666-1185

Phoenix AZ

602/997-1042

Arlington TX
817/461-8039

Maine
Contact Sales, Inc.
Burlington MA

Trident Associates, Inc.

Sunnyvale CA
408/734·5900
New Hampshire
Contact Sales, Inc.
Burlington MA

617/273-1502

617/273-1520

Harry Nash Asooclates
Willow Grove PA
215/657-2213

Manitoba

Ontario
Wolffs'eJectronic'Sales, Inc.

HLM Associates, Inc.

Aaleigh NC
919/851-2Boo

Florida

Parsippeny NJ
201/263-1535

305/792-2211
Clearwater FL

81'3/585-3327

M.....huaetts

Harry Nash Associates

British Columbia

Electronic Innovators. Inc.

SaskatcheWan

Contact Sales, Inc.

",.Burlington MA

New Mexico

Tenn.....

Action Unlimited

Georgia

Stone Component Sales
Framingham MA

Arlington TX
817/461-8039

20th Century Marketing, Inc.
Knoxville TN
615/966-3608

20th Century Marketing, Inc.

617/875-3266

Huntsville AL
205/772-9237

Tri·Tronix, N.W.

Michigan
A.C. Nordstrom & Company
Lathrup Village MI
313/559-7373

Mercer Island WA
206/232-4993

616/457-5762

Idaho

416

Jenison MI

Now York
D.L'. Eiss Associates, Inc.
Aoche.ter NY

716/328·3000
HLM Assoc!ates, Inc.

Northport NY
516/757-1606

Kavtronics Limited
Concord Ontario

416/689-2262

South Dakota
Minneapolis MN
612/835'()303

617/273-1520

Orlando FL
305/275-1132

Denver CO

South Carolina
New J..say

Willow Grove PA
215/657-2213

D/Z Associates, Inc.

303/534-3649

CANADIAN
REPRESENTA TIVES

Professional
Representatives, Inc.

301/484-7970

Wyoming

Ahoda I.iand

Stone· Component Sales

Maryland

Pikesville MD

Milwaukee WI

414/744·6842

WalthamMA
617/890-1440.

Pikesville MD
301/484-7970

Perrott Associates, Inc.
Sunrise FL

Wisconsin
Electronic Innovators, Inc.
Minneapolis MN

Advanced Technical Sales

Kentucky

Louisiana
Action Unlimite~

O/Z Associates, Inc.

Texl.
Action Unlimited

Arlington TX
817/461-8039
Aound Aock TX
512/255-1381
Houston TX
·713/495-7119

Alberta
Berg/ord & Associates
OlympiaWA

206/866-2001
Now Brunswick
Newfoundland

Nova Scotia
Ontario

Princ. Edward Illand
Qu .....
Kaytronics Llmltad
Ville St. Pierre Quebec
514/487-3434
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