1980_National_MOS_Databook 1980 National MOS Databook

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MOS
Introduction:

DATABOOK

This is the MOS Data Book from National
Semiconductor. It contains information on
products fabricated from all the MOS processes
in high volume production today; NMOS, CMOS,
and PMOS. These products are unique functions
in electronic systems. Their common denominator
is providing the most cost-effective solution to a
system need.
To minimize system costs, many of these
products have customized features, such as the
COPS™ family of single chip micro-controllers,
MAXI-ROMS™ and Custom Circuits. Each of
these has minimum order quantities to maintain
production efficiencies.
A large part of this book is Standard Circuits
which, due to large scale integration, have
incorporated features which make many of them
unique and cost effective in specific
applications and/or markets. The organization of
this book highlights those areas. The Standards
have no minimum quantities.
Of concern to everyone who uses LSI
products is the quality and reliability levels of
the product. National is careful not to cut
corners in this respect, designing in both quality
and reliability from the ground up. From quality
control of the raw materials through design
engineering, wafer fab, test and assembly, the
emphasis is uniformly there and we are proud of
the results. Additional information may be
obtained through your local National
Semiconductor Sales Office.
Other large scale integration MOS product
lines not i'ncluded in this book are RAM and
PROM memories and Microprocessors, which
are covered in other National Semiconductor
Data Books
COPSTM and MAXJ~AOM TM are trademarks of National Semiconductor Corporation.

Introduction to COPS™
COPS Devices
COPS Application Information
MOS/ROMs
Speech Synthesis
Standard
MOS/LSI

Digital Clocks
Television/Radio
Games/Calculators
Telecommunications

Application Notes
Custom MOS/LSI

Information contained herein is intended to be a general product description and is
subject to change.
National does not assume any responsibility for use of any circuitry described; no
circuil patent licenses are implied; and National reserves the right, at any time
without notice, tq change said circuitry.

Ordering Information/
Physical Dimensions

Display Drivers
Oscillators
Electronic Data
Processing

II

Table of Contents
Section 1 COPS Devices
COPS™ Selection Guide ............................................................................ 1-3
COP402/COP402M ROMless N-Channel Microcontrollers ..................................... 1-5
COP404L ROM less N-Channel Microcontroller ................................................ 1-24
COP410LlCOP411 L Single-Chip N-Channel Microcontrollers ................................. 1-40
COP420/COP421 and COP320/COP321 Single-Chip N-Channel Microcontrollers ........... 1-56
COP420C/COP421C and COP320C/COP321C Single-Chip CMOS Microcontrollers ........ 1-79
COP420LlCOP421 L Single-Chip N-Channel Microcontrollers ................................. 1-96
COP444L1COP445L Single-Chip N-Channel Microcontrollers ............................... 1-115
COP430/COP431/COP432 A to D Converters .................................................. 1-134
COP450/COP451 PROM-RAM Interface Chip .................................................. 1-136
COP452 Frequency/Counter Peripheral ........................................................ 1-138
COP470 V.F. Display Driver ..................................................................... 1-140
COP472 Liquid Crystal Display Controller ..................................................... 1-147
COP498 Low Power CMOS RAM and Timer ................................. , ................. 1-153
COP499 Low Power CMOS Memory ............................................................ 1-155
Section 2 COPS Application Information
COP400 COPS™Family User's Guide ............................................................. 2-3
COP Note 1 Analog to Digital Conversion Techniques with COPs Family
Microcontrollers .................................................................. 2-84
COP Note 2 COP Television Controller ...................................................... 2-119
COP Brief 1 SIO Input/Output Register Description ........................................ 2-124
COP Brief 2 Easy Logarithms for COP400 .................................................. 2-126
COP Brief 3 Use of Macro-Assembled Code ................................................ 2-137
COP Brief 4 L-Bus Considerations ........................................................... 2-139
COP Brief 5 • Software and Opcode Differences in the COP444L Instruction Set ........ 2-140
COP Brief 6 RAM Keep-Alive ................................................................. 2-141
COP Brief 7 Microbus Programming Considerations ............................. , ........ 2-142
COP Brief 8 COPS Peripheral Chips ......................................................... 2-143
COP Brief 9 Serial Interface Between COPS Microcontrollers and Peripheral Chips ... 2-145
COP Brief 10 COP410LlCOP411L Hardware Subroutine Stack Emulator ................. 2-147
COP Brief 11 Power Seat with Memory ....................................................... 2-151
COP Brief 12 An Automotive Diagnostics Display ....................... , ................... 2-155
COP Brief 13 An Electronic Speedometer and Odometer with Permanent.
Mileage Accumulation .......................................................... 2-157
Section 3 MOS/ROMs
,MM52116(2316E) 16,384-Bit (2048 x 8) Read Only Memory ...................................... 3-3
M M52116FDW, M M52116FDX Character Generators ........................................... 3-6
MM52132 32,768-Bit (4096 x 8) MAXI-ROMTM .................................................... 3-13
MM52164 65,536-Bit (8192 x 8) MAXI-ROMTM .................................................... 3-16
MM52264 65,536-Bit (8192 x 8) Clocked MAXI-ROMTM .......................................... 3-19
Section 4 Speech Synthesis
DIGITALKER™ Speech Synthesis System ....................................................... .4-3
COPSTM, MAXIROMTM, DIGITALKERTM are trademarks of National Semiconductor Corporation.

III

Table of Contents

(continued)

Section 5 STANDARD MOS/LSI
Digital Cloqk Product Selection Guide .......................................... : ....... ; ........ ,5·3
Television/Radio Product Selection Guide .. , ............. : ............... : ....................... 5·4
Games/Calculators
Product Selection Guide .............. : ......................................
5·5
,
.
Telecommunication Device Product Selection Guide ........... , .............................. ,5·6
Display Driver Product Selection Guide ............................................................ 5·7
Oscillator/Divider Product Selection Guide ................... , .... , .. , ........................... 5·8
Electronic Data Processing Product,Selection Guide ......... : .............................. '.' .5·9
,

Digital Clocks
MM5309, MM5311, MM5312, MM5313, MM5314, MM5315 Digital Clocks ....... , ............ 5·13
MM5316 Digital Alarm Clocks ............... , ....................................... ; ............ 5·20
MM5387AA, MM53108 Digital Alarm Clocks ........ , ........................................... 5·25
MM53110 Series Auto Clock and Elapsed Timer, ........•. , .. , ................................ 5·31
MM53113 Digital Alarm Clock ...... , ... , .......................................... : .............. 5·36
MM53124 Automobile Clock and Elapsed Timer ......... : ..................................... 5·41
MM53224 Automobile Clock and Elapsed Timer ............................................... 5·45
MM5402, MM5405 Digital Alarm Clocks .......... ,:.......... : .................................. 5·49
MM5406 Delux Display and Clock.Radio .................. '............................... : ...... 5·54
MM5407 -Digital Thermometer. ............ : ...................................................... 5~1
MM5455 Digital Alarm Clock .......................................... : .......................... 5·66
MM5456, MM5457 Digital Alarm Clocks ................................................ '......... 5·7Q
MM58143, MM58144, MM58183, MM58184 LCD Alarm Clock Circuits .................. , .... 5·74
MM7317B, MM7318B Alarm Clock Calendar ......................... : ..................' .. , ... ,.. 5-81
Television/Radio
MM5321 TV Camera Sync Generator ..................................... ; ...................... 5·91
, MM5322 Color Bar Generator Chip ................................... : ........ .' ...... ~ .......... 5·97
·MM53100, MM53105 Programmable TV Timers ...... : ......................................... 5·102
.' MM53118AA TV Digital Tuning .............................. : ............................... , .. 5·107
MM5430, MM5431 AM/FM Radio Frequency Display ......................................... 5:115
MM5439 Microprocessor Compatible Phase Lock Loop (PLL) ............................... 5·120
MM55108, MM55110 PLL Frequency Synthesizer with Receive/Transmit Mode ........... 5·1,27
MM55121 Serial Data/PLL Frequency Synthesizer ........................................... 5·132
MM55122 Serial Data/PLLFrequency Synthesizer ........................................... 5·137
MM55123 Serial Data/PLL Frequency Synthesizer ........................................... 5·142
MM55124, MM55126 PLL FrequencySynthesizer ............................................. 5·147
MM5837 Digital Noise Source ............................................ : .... : ................. 5·151
MM5840 TV Channel Number (16·Channel) and Time OisplayCircuit ........................ 5·153
MM58106 Digital Clock and TV Display Circuit ........................... : ............. : ..... 5·158
MM58142 TV Synthesizer .............. : ......................................................... 5·163
MM58146 TV Clock and Channel Display .......................................... : ............ 5·168
MM58313 VaractorTuner Display Circuit .................................................. : ... 5·173

IV

Table of Contents
Section 5

(continued)

STANDARD MaS/LSI (continued)

Games/Calculators
MM5780 Educational Arithmetic Game ....................................................... 5-181
MM57455 Advanced Educational Arithmetic Game .......................................... 5-187
MM57459 8-Digit LED Direct-Drive Memory Calculator ....................................... 5-190
Telecommunications
MM5393, MM5394, MM53143, MM53144 Push Button Pulse DialerCircuits ................ 5-197
MM5395, MM53125 DTMF (Touch Tone® ) Generators ....................................... 5-202
MM53130 DTMF (Touch Tone® )Generator ................................................... 5-207
MM53190 Push-Button Pulse Dialer ............................................................ 5-212

Display Drivers
MM5445, MM5446, MM5447, MM5448 VF Display Drivers ................................... 5-219
MM5450, MM5451 LED Display Drivers ........................................................ 5-222
MM5452, MM5453 Liquid Crystal Display Drivers .................................. ; .......... 5-227
MM5480 LED Display Driver ..................................................................... 5-232
MM5481 LED Display Driver ..................................................................... 5-235
MM58201 Multiplexed LCD Driver .............................................................. 5-238
Oscillators
MM5368 CMOS Oscillator DividerCircuit ..................................................... 5-245
MM5369 Series 17 Stage Mask Programmable Oscillator/Divider ........................... 5-248
MM53107 Series 17-Stage OsciliatorlDivider...................... . ........................ 5-251
Electronic Data Processing
MM5034, MM5035 Octal80-Bit Static Shift Register ......................................... 5-257
MM5303 Universal Fully Asynchronous ReceiverfTransmitter .............................. 5-260
MM5307 Baud Rate Generator/Programmable Divider ....................................... 5-266
MM5330 41h-Digit Panel Meter Logic Block.............................. . ............. : .... 5-271
MM53200 EncodelDecoder ..................................................................... 5-278
MM54240 Asynchronous ReceiverfTransmitter Remote Controller ......................... 5-280
MM57109 MOS/LSI Number-Oriented Processor ............................................. 5-284
MM57436 Decimal/Binary Up/Down Counter .................................................. 5-309
MM57499 96- or 144-Key Serial Keyboard Interface (SKI)................
. ................ 5-316
. .................. 5-331
MM5863 12-Bit Binary AID Building Block..............................
MM5865 Universal Timer ....... ,.........................................
. .................. 5-337
MM58167 Microprocessor Compatible Real Time Clock........
. ...................... 5-347
MM58174 Microprocessor-Compatible Real Time Clock.. . ................................ 5-353
Touch Tone' is a Registered Trademark of Bell Telephone

v

Table of Contents

(continued)

Section 6
AN143
AN155
AN156
AN168
AN169
AN196
AN249

Application Notes
Using National Clock Integrated Circuit in Timer Applications ...................... 6-3
Digital Voltmeters and the MM5330 .....................................................6-7
Specifying A/D and D/A Converters .................................................... 6-15
MM5865 Universal Timer Applications ................................................ 6-21
A 4-Digit, 7-Function Stop Watch/Timer ............................................... 6-31
Programmable TV TimerlTime-Channel Display ...................................... 6-45
MM54240 Asynchronous Receiver/Transmitter Remote Controller
Applications .............................................................................6-55
AN250 Applications and Uses of the MM5321 TV Camera Sync Generator ................ 6-59
AN251 A Broadcast Quality TV Sync Generator Made Economical through LSi ........... 6-63
MOS Brief 19 Integrated Circuit Combination Provides Digital Frequency Readout
with Digital Clock for Radios .................................................... 6-69

Section 7 Custom MOS/LSI
Your Choice for Custom MOS/LSI Circuits ......................................................... 7-3
Working Together to Get the Job Done with Custom MOS/LSI ............................. :, ... 7-4
The Custom MOS/LSI Development Cycle .................... , ................................... 7-5
A Working Partnership ................ : ............................................................. 7-6
Section 8
Ordering Information ..................... : ..........................................................8-3
Physical Dimensions ................................................................................8-4

VI

Alpha-Numerical Index
COP320 Single·Chip N·Channel Microcontroller ............................................... 1-56
COP320C Single·Chip CMOS Microcontroller .................................................. 1-79
COP321 Single·Chip N·Channel Microcontroller ............................................... 1-56
COP321C Single·Chip CMOS Microcontroller .................................................. 1-79
COP400 COPS™Family User's Guide ............................................................. 2-3
COP402 ROMless N·Channel Microcontroller ................................................... 1-5
COP402M ROM less N·Channel Microcontroller ................................................. 1-5
COP404L ROMless N·Channel Microcontroller ................................................ 1-24
COP410L Single·Chip N·Channel Microcontroller .............................................. 1-40
COP411 L Single·Chip N·Channel Microcontroller .............................................. 1-40
COP420 Single·Chip N·Channel Microcontroller ............................................... 1-56
COP420C Single·Chip CMOS Microcontroller ............................. : .................... 1-79
COP420L Single·Chip N·Channel Microcontroller .............................................. 1-96
COP421 Single·Chip N·Channel Microcontroller .............................. : ................ 1-56
COP421C Single·Chip CMOS Microcontroller .................................................. 1-79
COP421L Single·Chip N·Channel Microcontroller .............................................. 1-96
COP430 A to D Converter ........................................ ~ ............................... 1-134
COP431 A to D Converter ........................................................................ 1-134
COP432 A to D Converter ........................................................................ 1-134
COP444L Single·Chip N·Channel Microcontroller ............................................ 1-115
COP445L Single·Chip N·Channel Microcontroller ............................................ 1-115
COP450 PROM·RAM Interface Chip ............................................................ 1~136
COP451 PROM·RAM Interface Chip .......................................................... ,.1-136
COP452 Frequency/Counter PeripheraL ....................................................... 1-138
COP470 V.F. Display Driver ..................................................................... 1-140
COP472 Liquid Crystal Display Controller ..................................................... 1-147
COP498 Low Power CMOS RAM and Timer ........................................ : .......... 1-153
COP499 Low Power CMOS Memory ......................................................... : .. 1-155
MM5034 Octal80·Bit Static Shift Register .................................................... 5-257
MM5035 Octal80·Bit Static Shift Register .................................................... 5-257
MM5303 Universal Fully Asynchronous ReceiverfTransmitter .............................. 5-260
MM5307 Baud Rate Generator/Programmable Divider ....................................... 5-266
MM5309 Digital Clock .............................................................................5-13
MM5311 Digital Clock ........................................................................ ; .... 5-13
MM5312 Digital Clock .............................................................................5-13
MM5313 Digital Clock ............................................................................ :5~13
MM5314 Digital Clock .............................................................................5-13
MM5315 Digital Clock ........................................................................ ; .... 5-13
MM5316 Digital Alarm ClockClock· ............................................. ~ ................ 5-20
MM5321 TV Camera Sync Generator ............................................................ 5-91
MM5322 Color Bar Generator Chip .............................................................. 5-97
MM5330 4%·Digit Panel Meter Logic Block ................................................... 5-271
MM5368 CMOS Oscillator Divider Circuit ..................................................... 5~245
MM5369 Series 17 Stage Mask Programmable Oscillator/Divider .......................... 5-248
MM5387AA Digital Alarm Clock .................................................."............... 5-25

VII

Alpha-Numerical Index

(Continued)

M M5393 Push Button Pu Ise Dialer Circuit ........................ '.' .... , ...................... 5·19.7
MM5394 Push Button Pulse Dialer Circuit. .................................................... 5·197
M M5395 DTM F (Touch Tone® ) Generator ..................................................... 5·202
MM5402 Digital Alarm Clock ......................... , ........................................... 5·49
MM5405 Digital Alarm Clock .................................................................... :5·49
MM5406 Deluxe Display and Clock Radio ........................... , .......................... 5·54
MM5407 Digital Thermometer .................................................................... 5·61
MM5430 AM/FM Radio Frequency Display ........................... : ........................ 5·115
MM5431 AM/FM Radio Frequency Display ................. ,......................... "......... 5·115
M M5439 Microprocessor Compatible Phase Lock Loop (PLL) .............................. .5·120
MM5445 VF Display Driver ...................................................................... 5·219
MM5446 VF Display Driver ........................................ : ............................. 5·219
MM5447 VF Display Driver .................................................... ',"'"'''''''' ,'''' .5·219
MM5448 VF Display Driver ........................ : ............................... ',"'"'''''' .. 5·219
MM5450 LED Display Driver .......................................................... , .......... 5·222
MM5451 LED Display Driver ................................................. , ................... 5·222
MM5452, Liquid Crystal Display Driver ......................................................... 5·227
MM5453 Liquid CrystalDisplay Driver ......................................................... 5·227
MM5455 Digital Alarm Clock ..................................................................... 5·66
MM5456 Digital Alarm Clock ................................................... , ................. 5·70
MM5457 Digital Alarm Clock .................. , ................................................. ,5·70
MM5480 LED Display Driver ..................................................................... 5·232
MM5481 LED Display Driver ....................................... , ............................. 5·235
MM5780 Educational Arithmetic Game ...................... : ................................. 5·181
MM5837 Digital Noise Source ..................................................................,5·151
MM5840 TV Channel Number (16·Channel) and Time Display Circuit ....................... 5·153
MM5863 12·Bit Binary AID Building Block .............................. : .... ",'''''' ........ ; .5·331
MM5865 Universal Timer ........................................................................ 5·337
MM7317B Alarm Clock Calendar ....................... : ........................................ 5·81
MM7318B Alarm Clock Calendar ............................................................... :5·81
MM52116(2316E) 16,384·Bit (2048 x 8) Read Only Memory ............... : ...................... 3·3
MM52116FDW Character Generator .............. , ............ , .................................. 3·6
M M52116FDX Character Generator .............................................................. 3·6
MM52132 32,768·Bit (4096 x 8) MAXI·ROWM .................................................... 3·13
MM52164 65,536·Bit (8192 x 8) MAXI·ROM ...................................................... 3·16
MM52264 65,536·Bit(8192 x 8) Clocked MAXI·ROM ............................................ 3·19
MM53100 Programmable TV Timer ............................................................. 5·102
MM53105 Programmable TVTimer ............................................................ .5·102
MM53107 Series 17·Stage Oscillator/Divider ............................... ,................... 5·251
MM53108 Digital Alarm Clock .................................................................... 5·25
MM53110 Series Auto Clock and Elapsed Timer ............................................... 5·31
MM53113 Digital Alarm Clock .............................................. : ..................... 5·36
MM53118AA TV Digital Tuning ...........................' ..................................... .5·107
MM53124 Automobile Clock and ElapsedTimer ............................................... 5·41
MAXI·ROMTM is a Trademark of National Semiconductor Corp.,

VIII

Touch Tone® is a Registered Trademark of Bell Telephone

Alpha-Numerical Index
MM53125
MM53130
MM53143
MM53144
MM53190
M M53200
MM53224
MM54240
MM55108
MM55110
MM55121
MM55122
MM55123
MM55124
MM55126
MM57109
MM57436
MM57455
MM57459
MM57499
MM58106
MM58142
MM58143
MM58144
MM58146
MM58167
MM58174
MM58183
MM58184
MM58201
MM58313

(Continued)

DTMF (Touch Tone®) Generator ..................................................... 5-202
DTMF (Touch Tone®) Generator ..................................................... 5-207
Push Button Pulse Dialer Circuit ................................................... 5-197
Push Button Pulse Dialer Circuit ................................................... 5-197
Push Button Pulse Dialer ............................................................ 5-212
EncodelDecoder ..................................................................... 5-278
Automobile Clock and Elapsed Timer ............................................... 5-45
Asynchronous Receiverrrransmitter Remote Controller ......................... 5-280
PLL Frequency Synthesizer with Receive/Transmit Mode ....................... 5-127
PLL Frequency Synthesizer with Receive/Transmit Mode ....................... 5-127
Serial Data/PLL Frequency.Synthesizer ........................................... 5-132
Serial Data/PLL Frequency Synthesizer ........................................... 5-137
Serial Data/PLL Frequency Synthesizer ........................................... 5-142
PLL Frequency Synthesizer ............................ ; ............................ 5-147
PLL Frequency Synthesizer .......................................................... 5-147
MOS/LSI Number-Oriented Processor ............................................. 5-284
Decimal/Binary UplDown Counter .................................................. 5-309
Advanced Educational Arithmetic Game .......................................... 5-187
8-Digit LED Direct-Drive Memory Calculator ....................................... 5-190
96- or 144-Key Serial Keyboard Interface (SKI) ..................................... 5-316
Digital Clock and TV Display Circuit ............................................... 5-158
TV Synthesizer ....................................................................... 5-163
LCD Alarm Clock Circuit .............................................................. 5-74
LCD Alarm Clock Circuit .............................................................. 5-74
TV Clock and Channel Display ...................................................... 5-168
Microprocessor-Compatible Real Time Clock ..................................... 5-347
Microprocessor-Compatible Real Time Clock ..................................... 5-353
LCD Alarm Clock Circuit .............................................................. 5-74
LCD Alarm Clock Circuit .............................................................. 5-74
Multiplexed LCD Driver .............................................................. 5-238
VaractorTuner Display Circuit ...................................................... 5-173

Touch Tone'" is a Registered Trademark of Bell Telephone

IX

Introduction to COPS™
COPS Single Chip
Microcontroller and Peripherals

COPS™ Family
Introduction:
Computer on a Chip

National Semiconductor manufactures a wide-ranging and
sophisticated family of single-chip microcomputers to meet the total
needs of the microcontroller marketplace.
Each member of the COP400 series of single-chip microcontrollers is a
complete "computer-on-a-chip," containing all system timing, internal
logic, ROM, RAM, and 1/0 necessary to implement dedicated control
functions in a wide variety of applications. The COP400 family of devices
feature instruction sets, internal architectures and 1/0 schemes designed
to ease keyboard input/display output and efficient binary and BCD data
manipulation. On-Chip ROM sizes range from 512 x 8 to 2,048 x 8 bits,
RAM from 32 x 4 to 128 x 4 bits, instruction sets from 43 to 57
commands, 1/0 lines from 16 to 36, and instruction cycle execution times
ranging from 4 to 16 microseconds. The family is fabricated using three
processes: an advanced, high speed N-channel MOS; a low power
NMOS; and an even lower power complementary MOS.
To ease program development on the new COP400 series a specially
designed COPS Product Development System (PDS), has been introduced.

Programmable Features

The range of the microcontrollers available in the COP400 family allow
the user to specify the optimum device for use in a particular application.
Not only can the user pick a part with RAM, ROM, 1/0 and speed
optimized for specific tasks, but the family also offers a choice of ports
with differing electrical characteristics. Each part contains a number of
clock, 1/0 and other options, mask programmed into the device at the
same time the ROM is coded with the user's dedicated program. This
allows great flexibility in matching particular COP400 microcontrollers to
the user need.
All COP400 devices feature single supply operation and fast
standardized test procedures that verify the internal logic and user
program. The flexible 110 configuration of the COP400 microcontrollers
allow them to interface and drive a wide range of devices using a
minimal amount of external parts. Typical interfaced devices include:
keyboards and displays (direct segment and direct digit drive), external
data memories, printers,other COP devices, AID and DIA converters,
power control devices such as SCRs and TRIACs, mechanical actuators,
general purpose microprocessors, shift registers and external ROM
storage devices.
'

Applications

The COP400 devices are aimed at such high volume applications as
clocks, timers, laboratory instruments, radio controllers, applicance
controllers, programmable sequencers, scales, cash registers,
calculators, microcontroller computational elements, toys, games, and
automotive computers.
.

Performance

The COP420/420Li420C devices constitute the center-piece
configurations of the family, with 1k x 8 ROM, 64 x 4 RAM, true vectored
interrupt plus restart, three level subroutine stack, 23 1/0 lines, 57
command instruction set, internal time base counter for real time
proceSSing, internal binary counter register with serial 1/0 capability,
gerieral purpose and TRI-STATE outputs, LED direct drive, and
softwarelhardware compatibility with the rest of the COP400 family - all
within a 28-piri dual-in-Iine package. The NMOS COP420 operates over a
4.5 to 6.3 volt single supply range and has a 4 microsecond instruction
cycle execution ~ime. Operating supply current is 20 milliamperes at 5
volts. The low power (40 mW, max.) NMOS COP420L differs from the
XIII

COP420 in that it has a 4:5 to 9.5 volt supply range, a 16/is instruction
cycle execution time, a divide by 32 crystal clock option and direct LED
digit drive capability. The COP420C is the CMOS version with a 2.4 to 6.0
volt operating supply range and a dual clock mode option for operation
at low speed (244/is) with low power consumption or high speed (16/is)
when necessary to perform internal data computations at a faster rate.
The COP420C also provides the user with a sleep (timed pause) mode
entered under program control with very low power consumption (15/iA).
The 24·pin COP421/421 L devices are identical to the COP420/420L
versions except that they have 19110 lines instead of 23, and no interrupt
capability. The COP410Ll411L have the same electrical specifications as
the COP420Ll421 L but half the program storage (512 x 8 ROM), half the
data storage (32 x 4 RAM), only 43 instructions, two instead of three
stack levels, no interrupt capability, 19 and 16 1/0 lines respectively.
They are in 24-pin and 20-pin packages, respectively.
The COP440/444L are expanded versions of the COP420/420L devices,
with the same instruction set but double the memory (2,048 x 8 ROM and
128 x 4 RAM). The 28-pin COP444L has 24110 lines and the 40-pin
COP440 (future product) has 36 lines of 1/0. The 40-pin COP402 and
COP404L are ROM-less version of the COP420 and COP444L,
respectively, available for prototyping, or in quantity for small volume
applications using up to 1024 x 8 and 2048 x 8 bits of external ROM.
Bus Compatibility

A key feature of the COP420 and COP 420C is that they are MICROBUS™
compatible, an option that allows it to be used as a peripheral
microprocessor device, inputting and outputting data from and to any
host microprocessor in National's MICROBUS-compatible family of 8-and
16-bit microprocessors. MICROBUS is a standard interconnect system
for 8-bit parallel data transfer between MOS/LSI CPUs and interface
devices. The COP402M is the ROM-less MICROBUS-compatible version
of the COP402. It is intended for use in prototyping systems in low
volume applications which use the COP420 as a host CPU peripheral
component.

Development Systems

To aid in the efficient and speedy programming of the COP400 series
microcontrollers National has developed the COP Product Development
System (PDS), built around a 16-bit microcomputer, 32k bytes of R/W
memory and 12k bytes of PROM firmware. The disk-based system features
an editor and assembler for handling source code entry, conversion to
object code and maintaining documentation. An in-circuit emulator card
attachment allows object code to be executed under the careful control
of a COP Monitor de-bug utility. The PDS also features a circuit fixture
for incoming inspection of COP400 devices.
National is continually expanding the COP400 family. Future members
will include expanded software and hardware capabilities, alternative
electrical specification devices, and smaller devices suitable for use in
less demanding applications.

Schools

A COPSTM training course is available for instruction in programming,
interfacing, and applications. For further information on the course,
contact your local National Semiconductor Sales Office.

XIV

Section 1
COPS Devices

NATIONAL SEMICONDUCTOR COP400 MICROCONTROLLER
FAMILY GUIDE
Specifications

M
E
M
0
R

Y

I
N

~
P:

ROMless Devices
404L
402
402M

I

ROM x 8

up to
1024 ext.

RAM x 4

64

Single·Chlp MlcracDnlroliers

410LJ 411L

420

I 420L I 420C

421

1421 L J 421 C

444L

I 445L

up to

2048

512

1024

1024

2048

32'

64'

64'

128'

ext.

128

I

Inputs

4

0

4

0

T

Bidirectional TRI·STATElM I/O

8

8

8

8

8

0

Bidirectional 110

4

4

3

4

4

4

Outputs

4

4

2

4

4

4

4

P
U

S
/'

0

U

T

P
U

T

S

Yes

Serial 110 and External Event Counter
Interrupt

Yes

I

No

Yes

Yes
Ves

Yes

510

Yes

510

I

No

Yes

No

2

3

3

3

No

No

Yes

No

G

E
N

Stack. Levels

3

E

R
A

MICROBUS1t~

Option

L

Instruction Cycle ij.ts)

P

0
W
E
R

/'
p
K
G

Supply Voltage

Supply Current (rnA)
Package Size (pins)

'RAM keep·alive option (except 420CI421C).

I

No

No

Ves

4

16

16

4

4.5-6.3

4.5-9.5

No

Yes

4.5-6.3'"

15

30
40

24

20

• "Fast: 800 "A. Slow: 3S,..A. Sleep: lS"A.

1·3

Yes

16

4

16

16

4_5-6.3 4.5-6.3'" 2.4-6.0 4.5-6.3 4.5-6.3'" 2.4-6.0
30

5

No

8

..

28
•• "4.5·9.5Voptionallv a.vailable

30

8
24

4_5-6.3'"

11

"
28

I

24

~National

~ Semiconductor

COP402lCOP402M ROMless N·Channel Microcontrollers
General Description

Features

The COP402 and COP402M ROM less Microcontrollers are members of the COPSTM family, fabricated
using N-channel silicon gate MOS technology. Each
part contains CPU, RAM and 1/0, and is identical to a
COP420 device, except the ROM has been removed;
pins have been added to output the ROM address
and to input ROM data. In a system, the COP402 or
402M will perform exactly as the COP420; this
important benefit facilitates development and debug
of a COP420 program prior to masking the final part.
These devices are also appropriate in low volume
applications, or when the program may require
changing. The COP402M is identical to the COP402,
except the MICROBUSTM interface option has been
implemented.

II
II
II
II
II
II
II
II

II

• 4.0,..s instruction time
Single supply operation (4.5V to 6.3V)
II Internal time-base counter for real-time
processing
II Internal binary counter register with serial 1/0
capability
II Softwarelhardware compatible with other
members of COP400 family
II

The COP402 may also be used to emulate the
COP410L, 411L, 420L or 420C by appropriately
reducing the clock frequency.

AOliiATA
J3

P,
PH
1P1
IP,
IPs
IP,
IP,
IP,
IP,
1P0

,"
l5

P
BUFFERS

Low cost
Exact circuit equivalent of COP420
Standard 40-pin dual-in-line package
Interfaces with standard PROM or ROM
64x4 RAM, addresses up to 1kx8 ROM
MICROBUSTM compatible (COP402M)
Powerful Instruction set
True vectored interrupt, plus restart
Three-level subroutine stack

"'0

Vee

~t7

'"0

CK!

+"

L

L

CLOCK
GENERATOR

COUNTER

(DIVIDE BY 1024)

10
J6

IP
BUFfERS

31

10
0
REGISTER

&
BUfFER

3B

39

"

0,
0,
0,
00

SKIP
(NOT USED)
25

SK

10
31

G,
G,
G,

110 CONTROLS

Go

~---------------t~~so

11

21 16 15
IN] IN2 IN1

12

13

14

18

19

20

21

26

!No

Figure 1. COP402l402M Block Diagram

1-5

:E

~

,Q.

o
o

'(q

~

oo

Absolute Maximum Ratings
Voltage at Any Pin Relative to GND
Ambient Operating Temperature
Ambient Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Power Dissipation
'

-9·5Vto t 7V
O·Cto + 70·C
-65·Cto +150·C
300~C

0.75 Watt at 25 ·C
0.4 Watt at 70·C

Absolute maximum ratings Indicate limits beyond which
damage to the device may occur. DC and AC electrical specifica·
tions are not ensured when operating the device at absolute
maximum ratings.

DC

Ele~trical

Characteristics o·c .. TA ..

Parameter

+ 70 ·C, 4.5V .. Vcc" 6.3V unless otherwise noted.

Conditions

Operating Voltage (Vee!
Operating Supply Current

Units

Min

Max

4.5

6.3

V

30

mA

Vee =5V, TA =25·C
(lill inputs and outputs open)

Input Voltage Levels
CKI Input Levels
Logic High (VI H)
Logic Low (VIU

"

RESET Input Levels
Logic High
Logic Low

0.4

V

0.6

V
V

0.7 Vee

RESET Hysteresis

1.0

SO Input Level (Test mode)

2.0

Input Levels
Logic High
Logic High
Logic Low
Logic Low (IN o:3 with Load)

,v

2.0

Vee=max
Vee=5V,±5% '

V

,
3.0

V

3.0
2.0
-0.3
-0.3

0.8
0.5

V
V
V
V

2.4
-0.3

0.4

V
V

Vee- 1
-0.3

0.2

V
V

Output Voltage ,Levels (Note 2)
TIL Operation
Logic High (V OH )
Logic Low (VOL)
CMOS Operation
Logic High (VOH )
Logic Low (VOL)

Vee=5V±5%
IOH= -100~
IOL= +1.6mA
IOH=-10"A
IOL= +10"A.

Output Current Levels
LED Direct Drive Output
Logic High (IOH)

Vee=6V
VOH =2.0V

TRI·STATE@ Output
Leakage Current
IP7 '" IPO Output Voltage Levels,
VOH
VOL

IOH = -'50"A.
IOL= +360"A

1·6

2.5

14

mA

-10

+10

"A

2.7
-0.3

0.4

V
V

AC Electrical Characteristics

0 'C " T

Parameter
Instruction Cycle Time -

A"

o

+ 70 'C, 4.5V " Vee" 6.3V unless otherwise noted.

Conditions
te

CKI Using Crystal (figure 8)
Input Frequency - fl
Duty Cycle (Note 2)

figure 3
.,. 16 mode
figure 3a

Min

Max

4

10

f'S

1.6
30

4
55

MHz
%

Units

tSETUP
t HOLD

1.7
312

f'S
ns

0.3
250

f'S
ns

51, IP 7 -IPo
tSETUP
t HOLD
OUTPUTS:

=

4.5V" Vee" 6.3V, CL
50pF,
VOH
0.7V ee , VOL
0.3Vee

=

=

SK as a Logic-Controlled Clock
tpD1
t pDO

1.1
0.3

f's
f'S

SO, SK as a Data Output
tpD1
tpDo
tpD1

1.4
0.3
0.7

f'S
f's
f's

1.6
0.6

f'S
f'S

2.4
0.4

f'S
f'S

0.5
0.5

f'S
f'S

0.6
0.6

f's
f'S

VOH

= 2V

0 3 - Do, G3 -G O
tpD1
t pDO
L7 - Lo (LED Direct Drive)
tpD1
tPDO
COP TO TTL PROPAGATION
DELAY

~

o

o"tJ
8N

s:

INPUTS: (figure 3a)
IN 3 -IN o, G 3 -G O, Lr La

COP TO CMOS PROPAGATION
DELAY

o
"tJ
8

VOH

= 2V
=

fanout
1 Standard TTL Load
Vee
5V ± 5%, CL
50pF,
VOH
2.4V, VOL
0.4V

=
=

=

ADIDATA
tpD1
t pDO

=

SKIP
tpD1
tpDo

-

1-7

:=

5i

a..
oo

AC Electrical Characteristics

(continued)

Parameter

o·c.;; TA .;; + 70·C, 4.5V';;

Conditions

Vee';; 6.3V unless otherwise noted.

Min

Max

Units

OUTPUTS (cont.):

C\I
~

SK as a Logic-Controlled Clock
t p01
tpDO

0.8
0.8

I'S
I's

oo

SK as a Data Output, SO
tpD1
tpDO

1.0
1.0

I's
I's

0 3 -00, G3 -G O
tpD1
tpDO

1.3
1.3

I'S
I's

L7 -Lo
tpD1
tpDO

1.4
0.4

I'S
I'S

I P7 -1 Po, Pg, Pa
tpD1
tpDO

1.5
1.5

1'5

CKO (figure 3a)
tpD1
tpDO

0.2
0.2

1'5

a..

MICROBUSTM TIMING
(COP402M)

CL

1'5

I'S

= 50pF, Vee = 5V ± 5%

A. Read Operation (figure 4)
Chip Select Stable before
RD - tesA
Chip Select Hold Time for
RD - tAes
RD Pulse Width - tAA
Data Delay from RD - tAD
RD to Data Floating - tDF

50

ns

5

ns

300
250
200

B. Write Operation (figure 5)
Chip Select Stable before
WR - tesw
Chip Select Hold Time for
WR - twes
WR Pulse Width - tww
Data Setup Time for
WR - tDW
Data Hold Time for
WR-tWD
INTR Transition Time from
WR - tWI

20

ns

20

ns

300
200

ns
ns

40

. ns
700

Note 1: Duty Cycle = tWlf(tWI + twO).
Note 2: See figure 11 for additional 110 characteristics.

1-8

ns
ns
ns

ns

CK"

40

DO

CKI

39

01

IP4

38

02

RESET

31

03

IP3

36

IPS

IP2

35

P8

IPI

34

P9

IPO

33

AD/DATA

32

SKIP

31

G3

IP1

COP402

IP6

10

L1

11

30

G2

l6

12

29

Gl

l5

13

28

GO

l4

14

21

IN3

INI

15

26

INO

IN2

16

25

SK

VCC

11

24

SO

l3

18

23

SI

l2

19

22

VSS

11

20

21

lO

CQP402M

Figure 2. Connection Diagram

Description

Pin
L7 -Lo

Description

Pin

8 bidirectional 110 ports with
TRI·STATE'"

G3-G O

4 bidirectional 110 ports

0 3-00

4 general purpose outputs

IN3-INo

4 general purpose inputs

SI

Serial input (or counter input)

SO

SKIP

Instruction skip output

CKI

System oscillator input

CKO

System oscillator output

RESET

System reset input

Vee

Power supply

GNO

Ground

Serial output (or general purpose
output)

IP7-IPO

8 bidirectional ROM address and data
ports

SK

Logic'controlled clock (or general
purpose output)

P8, P9

2 ROM address outputs

AOIDATA

Address out/data in flag

CKI
AO/iiiiTA. SK
(AS A ClOCKI _
l 0.
G3-Go.l1IN3-INO.
CKO & SI
G3- GO. INPUTS
03- 0 0.
l1-l0. SO. SK
OUTPUTS

............._

~~W&iWlj~iWljWkJ~~~iWlj~;=~==~X2WJilWkJ~WkJ~~

_j_______~~~~ihiiH---------...!-~~~

~~~!!L

---SKIP OUTPUT
J Push-Pull - an enhancement-mode
device to ground and Vee Intended to meet the
requirements associated with the MICROBUSTM
option. These outputs are TRI-STATE ' outputs,
allowing for connection of these outputs to a data
bus shared by other bus drivers.

=

f. Inputs have an on-chip depletion load, device to
Vee, as shown In figure 10f.
The above input and output configurations share
common enhancement~mode and depletion-mode

1-13

:E

~

c..

o
(J

~

c..

o

(J

devices. Specifically, all configurations use one or
more of six devices (numbered 1- 6, respectively).
Minimum and maximum current (lOUT and VOUT)
curves are given in figure 11 for each of these
devices.

The following Information is provided to assist the
user In understanding the operation of several
unique instructions and to provide notes useful to
programmers in writing programs.

The SO,SK outputs are configured as shown in figure
10c. The D and G outPUtS are configured as shown in
figure 10a. Note that when inputting data to the G
ports, the G outputs should be set to "1." The L
outputs' are configured as in figure 10d on the
COP402. On the COP402M the L outputs are as in
figure 10e.

XAS Instruction
XAS (Exchange A with SIO) exchanges the A·bit con·
tents of the accumulator with the 4-bit contents of
the SIO register. The contents of SIO will contain
serial-in/serial-out shift register or binary counter
data, depending on the value of the EN register. An
XAS instruction will also affect the SK output. (See
Functional Description, EN Register, above.) If SIO is
selected as a shift register, an XAS instruction must
be. performed once every 4 instruction cycles to
effect a continuous data stream.

An important point to remember if using configura·
tion d with the L drivers is that even when the L
drivers are disabled, the depletion load device will
source a small amount of current. (See figure 11.)
IP7 through IPO outputs are configured as shown in
figure 10c; P9, P8, SKIP and ADIDATA are configured
as shown in figure 10b.

JID Instruction
COP402l402M INSTRUCTION SET

JID (Jump Indirect) is an indirect addressing instruction, transferring program control to anew ROM
location pointed to indirectly by A and M. It loads the
lower 8 bitsof the ROM address register PC with the
contents of ROM addressed by the 10-bit word, PCg:s,
A, M. PC g and PC s are not affected by this instruction.

Table 1 is a symbol table providing internal architecture, instruction operand and operational symbols
used in the instruction set table.
Table 2 provides the mnemonic, operand, machine
code, data flow, skip conditions and description
associated with each instruction in the COP402l402M
instruction set.

Note that JID requires 2 instruction cycles.

Vcc

-C~
a. Standard

b. High Drive

c. Push·Pull

Vcc .

~#6

INPUT~~
d. LED

e. TRI·STATE'" Push· Pull

(""S DEPLETION DEVICE)

Figure 10. Input/Output Configurations

1-14

f. Input with Load

30

-0.4

!

25

!.!-

20

j'

15

II

10

VCC t.5V IMAXI

I-

VC~

/

{MI~!,....-- ~

~

.s

~I

~

VCC" 4.5V {~NI

~

-02

.

-0.1

~

1\

-'"

-1.25 t-'''d--t--t--j--t--t--j

0: -0.75

k-"t--.p.~-r-t--t--t--j

- 0.5

k-f"""''I.-ft""""chl--t--t--j

~MAX

\
r"-. 'J.

-0. 25 I--i""-+.f-""",~;/'I-"""'t--t--j

Depletion Load OFF Source Current

Standard Output Source Current

-3

-20

I I
.s...

..s...

0

0

,

=>

=>

-1

Vee'" 4.SV
'I{MINI

VoUT{VOLTSI

DEVICE2h

! - {~~~; 63

I I

~

-12

~

-10

.s

~

1\ ~ ~

\

i

~.¥

-2

VCC" 4.5V (MAXI

,

-4

J

~

~

-8

1 i
I I
I I I

Vcc " 6.3 V (MAXI

.......

-6

V~C" 4.~V

{MAXI}

VOUT {VOLTSI

High Drive Source Current

1

i

Lbo.

-16
-14

\
\

~

~

-18

Vcc i6.3VI{MAXI

1\

-2

OEVICE 2

VOUT {VOL TSI

DEVICE 2

VOUT (VOLTSI

Output Sink Current

r--t---r---j--t--t--t--j

E

OEVICE 1

VoUT {VOL TSI

-1.75

~ -l.D t.-+-"'<;¥---=t~-r~~-t--j

MIN

I I

r--r-r--,--.---,--,---,

-1.5 t.-....,..~t'--t--r-t--t--j

-0.3

"6)V {MAli

Vcc " 6.Jv

-2.0

DEVICE 3

VCC" 4.5V (MINI

I

)(

i,...--- ~

~ r<

1 1

l1

"

~
L

1 1

~'l

VOUT (VOL TSI

Push·Pull Source Current

I

VCC" 6.3V {MINI

I

OEVICE 4

LED Output Source Current

-18
-16
MAX
-14
~

.s

~

V

-12
VOUP 2.oV
-10

V

-8
-6
-4

.'

\

V

~

.s...
0

'

-5
MIN

...

•• , .0'

k t-

4.5

-10

=>

.. V

-2

5.5
Vcc {VOLTSI

-1;5

-'-15

V

\

.... 6.3V {M~XI
...... 4.5V (MAX)

VI\
1\ 1\ 1\ \
\ \ l\ \
1\ 1\ . /
k' K 1\

1\

1'\
1-1.0
...
=>
o

/.?C 6.3V {~AXI
VCC" 4.5V {MAXI

"\

l'lj

'\

1'\

-0.5

,A.5V {MINI
,. 6.3V {MINI

'I'""-'

VCC" 6.3V {MINI

WVCC" 4.5V {MINI_

'$

}«

r'\

VI I' 1""-

~

6.5
DEVICE 4

LED Output Direct LED Drive

VOUT {VOLTSI

DEVICE 5

TRI·STATE® Output Source Current

Figure 11. Input/Output Characteristics

1·15

VOUT (VOL TSI

DEVICE 6

Input Load Source Current

o
o"'C

~

o

o"'C

~
III)
3:

~

i

0-

o

Table 1. COP402l402M Instruction Set Table Symbols
Definition

Symbol

Symbol

Definition

INTERNAL ARCHITECTURE SYMBOLS

INSTRUCTION OPERAND SYMBOLS

A

4·bit Accumulator

d

6·bit RAM Address Register

4·bit Operand Field, 0-15 binary (RAM Digit
Select)

~

B
Br

Upper 2 bits of B (register address)

r

2·bit Operand Field, 0-3 binary (RAM
Register Select)

oo

Bd

Lower 4 bits of B (digit address)

a

C

l·bit Carry Register

1Q·bit Operand Field, 0-1023 binary (ROM
Address)

D

4·bit Data Output Port

y

EN

4·bit Enable Register

4·bit Operand Field, 0-15 binary
(immediate Data)

G

4·bit Register to latch data for G 110 Port

o

~
0-

IL

Two l·bit Latches associated with the IN3
or INo Inputs

RAM(s)

Contents of RAM location addressed by s

ROM(t)

Contents of ROM location addressed by t

IN

4·bit Input Port

OPERATIONAL SYMBOLS

IP

8·bit Bidirectional ROM Address & Data
Port

+

Plus

-

Minus

-

Replaces

L

8·bit TRI·STATE 110 Port

M

4·bit contents of RAM Memory pointed to
by B Register

P

2·bit ROM Address Port

PC

1Q-bit ROM Address Register (program
counter)

A

The ones complement of A

III

Exclusive·OR

Q

8-bit Register to latch data for L 110 Port

:

Range of values

SA

10-bit Subroutine Save Register A

SB

10·bit Subroutine Save Register B

=

SC

10'bit Subroutine Save Register C

SIO

4-bit Shift Register and Counter

SK

Logic-Controlled Clock Output

Is exchanged with
Is equal to

Table 2: COP402l402M .Instructlon Set Table (Note 1)

Mnemonic Operand

Hex
Code

Machine
Code
Binary)

Lan~Uage

Data Flow

Description

Skip Conditions

ARITHMETIC INSTRUCTIONS
ASC

30

10 0 1 110 0 0 0 I

A + C + RAM(B) - A
Carry - C

Carry

Add with Carry, Skip on
Carry

ADD

31

10011100011

A + RAM(B)- A

None

Add A to RAM.

ADT

4A

10100110101

A + 1010 - A

None

Add Ten to A

5-

10101 1 y

A+y-A

Carry

Add Immediate, Skip on
Carry (y" 0)

10

10001100001

Ii + RAM(B) + C - A

Carry

Complement and Add
with Carry, Skip on Carry

AISC
CASC

Y

1

Carry -,C
CLRA

00

10000100001

0- A

None

Clear A

COMP

40

101 001 00001

A-A

None

Ones complement of A to
A

NOP

44

10 1 00101 001

None

None

No Operation

RC

32

100 1 11001 01

"0"- C

None

Reset C

SC

22

1001 01 001 01

"1" - C

None

Set C

XOR

02

10000100101

A .. RAM(B)- A

None

Exclusive-OR A with RAM

1·16

o

o"'tJ

Table 2. COP402l402M Instruction Set Table (continued)
Machine
Mnemonic Operand

Hex
Code

Lan~uage Code

Binary)

Data Flow

Description

Skip Conditions

FF

11111111111

ROM (PC9:e,A,M) PC7:0

None

Jump Indirect (Note 3)

6-

1011OIOOla9:8!
a7:0
I
I

a- PC

None

Jump

--

a6:0
111
I
(pages 2,3 only)
or

a - PC6:0

--

a5:0
11 11
I
(all other pages)

a - PC5:0

--

1101

I

6-

-RET
RETSK

JMP

a

-JP

a

JSRP

a

JSR

a

None

Jump within Page
(Note 4)

PC + 1 - SA - SB SC
0010 - PC9:6
a- PC5:0

None

Jump to Subroutine Page
(Note 5)

1011°11Ola9:81
a7:0
I
I

PC + 1 - SA - SB a- PC

None

Jump to Subroutine

48

10 1 0011 0001

SC - SB - SA - PC

None

Return from Subroutine

49

10100110011

SC - SB - SA - PC

Always Skip on Return

Return from Subroutine
then Skip

a5:0

cAMO

33
3C

1001110011 1
100 11 11 1 0 01

A- 07:4
RAM(B) - 03:0

None

Copy A, RAM to 0

COMA

33
2C

10011100111
10 a 1 011 1 0 01

07:4 - RAM(B)
03:0-A

None

Copy 0 to RAM, A

-5

1001 r 101011

RAM(B)- A
Br", r - Br

None

Load RAM into A,
Exclusive·OR Br with r

r

LDD

r,d

LOID

10010100111
I d I

RAM(r,d) - A

None

--

10 01 r

Load A with RAM pointed
to directly by r,d

BF

11011111111

ROM(PC9:8,A,M) - 0
SB- SC

None

Load Q Indirect (Note 3)

0000-

RAM(B)O
RAM(BI1
RAM(B)2
RAM(B)3

None

Reset RAM Bit

1111-

RAM(B)O
RAM(B)1
RAM(B)2
RAM(B)3

None

Set RAM Bit

23

RMB

0
1
2
3

4C
45
42
43

10 1 0011 1 001
10 1 0010 1 011
101 00100101
101 0010 0 1 11

8MB

a

4D
47
46
4B

10
10
10
10

1
2
3

1 a 011
1 0 010
1 0010
1 0 011

1 0 11
1 1 11
11g
0 1 11

1-17

o"'tJ
~

MEMORY REFERENCE INSTRUCTIONS

LD

~

o

TRANSFER OF CONTROL INSTRUCTIONS
JID

~

o

~

s:

Table 2. COP402I402M Instruction 'Set Table (continued)

Mnemonic pperend

Hex
Code

Machine
Lan,uage Code
Binary)

Data Flow

Skip Conditions

Description

MEMORY REFERENCE INSTRUCTIONS (continued)
STII

y

7-

101 1 11

I

y- RAM(B)
Bd+l-Bd

None

Store Memory Immediate
and Increment Bd

X

r

-6

100IrlOl10 1

RAM(B)-A
Brlllr-Br

None

Exchange RAM with A,
Exclusive-OR Br with r

XAD

r,d

23

1001 01001 1[
110 1 r I d I

RAM(~,d)-

None

--

Exchange A with RAM
pointed to directly by r,d

r

-7

100IrlOllli

RAM(B)-A
Bd-l-Bd
Brlllr- Br

Bd decrements past 0

Exchange RAM with A
and Decrement Bd,
exclusive-OR Br with r

r

-4

1001 r 101001

RAM(B)-A
Bd +1- Bd
Brill r - Br

Bd Increments past 15

Exchange RAM with A
and Increment Bd,
Exclusive-OR Br with r

A-Bd

None

Copy A to Bd
,Copy Bd to A

XDS

y

~

XIS

A

REGISTER REFERENCE INSTRUCTIONS

50

CAB
CBA

10 1 00111 1 01

Bd-A

None

1001 r I!d -Ill
(d = 0,9:15)
or
10011100111
II 01 r I d I
(any d)

r,d- B

Skip until not a LBI

Load B Immediate with
r,d (Note 6)

33
6-

10011100111

y- EN

None

'Load EN Immediate
(Note 7)

12

10 0 0 1100 1 01

A-

None

Exchange A with Br

SKC

20

10010100001

C = "I"

Skip If C Is True

SKE

21

100101 0 0 0 11

A = RAM(B)

Skip If A Equals RAM

SKGZ

33
21

10011100111

G3:0'= 0

Skip if G is Zero
(all 4 bits)

33
01
11
03'
13

10011100111
10000100011
10001100011
100001001 11
100011001 11

01
11
03
13

10 0 0 010 0 0 11
10001100011
10000100111
10001100111

RAM(B)o = 0

41

1010QlOOOli

A time-base counter
carry has occurred
since last test

LBI

4E

10101100001

r,d

-33

-LEI

y

XABR

101101

'i.

I
Br (0,0 - A3.A2)

TEST INSTRUCTIONS

SKGBZ
0
1
2
3
SKMBZ

.0
1
2
3

I
SKT

10010100011
1st byte

Skip If G Bit Is Zero

}~d~'

GO =
Gl ,=
G2':'
G3 =

,0
0
0
0
Skip If RAM Bit Is Zero

RAM(BI1 = 0
RAM(B)2 = 0
RAM(B)3 = 0

1-18

Skip on .Timer
(Note 3)

C')

,.,
0

Table 2. COP402J402M Instruction Set Table (continued)

Mnemonic Operand

Hex
Code

Machine
Lan~Uage Code
Binary)

~

Data Flow

Skip Conditions

Description

0

~

C')

INPUT/OUTPUT INSTRUCTIONS

,.,

ING

33
2A

10 a 1110 a 111
10 01011 0101

G-A

None

Input G Ports to A

0

ININ

33
28

10 0 1 110 0 1 11

IN- A

None

1001 011 0001

Input IN Inputs to A
(Notes 2 and 8)

8N

INIL

33
29

10011100111
1001011 001 1

IL3,"1","0",ILO - A

None

Input IL Latches to A
(Notes 2 and 3)

INL

33
2E

10011100111
10010111101

L7:4 - RAM(B)
L3:0- A

None

Input L Ports to RAM,A

OBO

33
3E

10011100111
10 a 1 111 1 101

Bd- 0

None

Output Bd to 0 Outputs

10011100111
y I

y- G

None

5-

10101 1

Output to G Ports
Immediate

OMG

33
3A

10011100111
10011110101

RAM(B)- G

None

Output RAM to G Ports

XAS

4F

10100111111

A ' - 510, C - SKL

None

Exchange A with 510
(Note 3)

OGI

y

33

Note 1: All subscripts for alphabetical symbols indicate bit numbers unless explicitly defined (e.g., Br and Bd are explicitly defined). Bits are
numbered 0 to N where 0 signifies the least significant bit (low-order, right-most bit). For example, A3 indicates the most significant (left-most)
bit of the 4·bit A register.
Note 2: The IN1N instruction is not available on the 24-pin COP421 since this device does not contain the IN inputs.
Note 3: For additIonal information on the operation of the XAS, JID, LaiD, INIL, and SKT instructions, see below.
Note 4: The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location ~ithin the two-page boundary of pages 2 or 3.
The JP instruction, otherwise, permits a jump to a ROM location within the current 64-word page. JP may not jump to the last word of a page.

Not. 5: A JSRP transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of Pl. A JSRP may not be used when in pages
2 or 3. JSRP may not jump to the last word in page 2.
Note 6: LSI is a single-byte instruction if d :::;; 0,9,10,11,12,13,14, or 15. The machine code for the lower 4 bits equals the binary value of the "d"
data minus 1, e.g., to load the lower four bits of S (Sd) with the value 9 (10012), the lower4 bits of the LSI instruction equal 8 (10002)' To load 0, the
lower 4 bits of the LSI Instruction should equal 15 (11112)'
Note 7: Machine code for operand field y for LEI instruction should equal the binary value to be latched into EN, where a "1" or "0" in each bit of
EN corresponds with the selection or deselection of a particular function associated with each bit. (See Functional Description, EN Register.)

Not. 8: COP402M will always read a "1" into At with the ININ instruction.

1-19

s:

:e
~
0..
o(J

~0..

o(J

INIL Instruction

not set. If the latch has been set since the previous
test, the next program instruction is skipped and the
latch is reset. The features associated with this
instruction, therefore, allow the controller to
generate its own time-base for real-time processing
rather than relying on an external input signal.

INIL (Input IL Latches to A) inputs 2 latches, IL3 and
ILa (see figure 12) and CKO into A. The IL3 and ILa
latches are set If a low-going pulse ("1" to "0") has
occurred on the IN3 and INa Inputs since the last INIL
Instruction, provided the input pulse stays low for at
least two instruction times. Execution of an INIL
inputs IL3 and 1'-0 Into A3 and AO respectively, and
resets these latches to allow them to respond to subsequent low-going pulses on the IN3 and INa lines. If
CKO Is mask programmed as a general purpose
input, an INIL will Input the state of CKO Into A2. If
CKO has not been so programmed, a "1" will be
placed in A2. A "0" is always placed in A1 upon the
execution of an INIL. The general purpose inputs
IN3-INa are input to A upon the execution of ari ININ
instruction. (See table 2, ININ Instruction.) INIL is
useful in recognizing pulses of short duration or
pulses which occur too often to be read conveniently
by an ININ instruction.

For example, using a 2.097MHz crystal as the timebase to the clock generator, the instruction cycle
clock frequency will be 131 kHz (crystal frequency ...
16) and the binary counter output pulse frequency
will be 128Hz. For tlme-of-day or similar real-time
processing, the SKT Instruction can call a routine
which increments a "seconds" counter every 128
ticks.
Instruction Set Notes
a. The first word of a program (ROM address 0) must
be a CLRA (Clear A) instruction.
b. Although skipped instructions are not executed,
one instruction cycle time is devoted to skipping
each byte of the skipped instruction. Thus all
program paths take the same number of cycle
times whether instructions are skipped or
executed.

LQI D Instruction
LaiD (Load a Indirect) loads the 8-bit a register with
the contents of ROM pOinted to by the 10-bit word
PCg, PCa, A, M. LaID can be used for table lookup or
code conversion such as BCD to seven-segment. The
LaiD instruction "pushes" the stack (PC + 1 - SASB - SC) and replaces the least significant 8 bits of
PC as follows: A - PC7 :4 , RAM(B) - PC 3:a, leaving
PC g and PC a unchanged. The ROM data pOinted to by
the new address Is fetched and loaded into the a
latches. Next, the stack is "popped"(SC - SB - SA
- PC), restoring the saved value of PC to continue
sequential program execution. Since LaID pushes
SB - SC, the previous contents of SC are lost. Also,
when LaiD pops the stack, the previously pushed
contents of SB are left in SC. The riet result is that
the contents of SB are placed in SC (SB - SC). Note
that LaID takes two instruction cycle times to
execute.

c. The ROM is organized into 16 pages of 64 words
each. The Program Counter is a 10-bit binary
counter, and will count through page boundaries.
If a JP, JSRP, JID or LaiD instruction is located in
the last word of a page, the Instruction operates
as if It were in the. next page. For example: a JP
located in the last word of a page will Jump to a
location in the next page. Also, a LaiD or JID
located In the last word of page 3, 7, 11, or 15will
access data in the next group of 4 pages.

TYPICAL APPLICATIONS
PROM-Based System
The COP402 may be used to exactly emulate the
COP420. Figure 13 shows the Interconnect to implement a COP420 hardware emulation. This connection
uses two MM5204 EPROMs as external memory.
Other memory can be used such as bipolar PROM or
RAM.

COP420
ININ

1

INoIIN3

Pins IP7-IPO are bidirectional inputs and outputs.
When the ADIDATA clocking output turns on, the
EPROM drivers are disabled and IP7 -IPO output
addresses. The 8-blt latch (MM74C373) latches the
addresses to drive the memory.

INIL

Figure 12. INoIIN3 Latches

When AD/DATA turns off, the EPROMs are enabled
and the IP7-IPO pins will input the memory data. P8
and P9 output the most significant address bits to
the memory. (SKIP output may be used for program
debug if needed.)

SKT Instruction
The SKT (Skip on Timer) instruction tests the state of
an internal 10-bit time-base counter. This counter
divides the instruction cycle clock frequency by 1024
and provides a latched Indication of counter
overflow. The SKT instruction tests this latch,
executing the next program instruction if the latch is

The other 28 pins of the COP402 may be configured
exactly the same as a COP420. The COP402M chip
can be used if the MICROBUSTM feature of the
COP420 Is needed.

1-20

B

VCC

12

A

VSS
VBn
PROGRAM

Y
-12V

-2!
14
1J
11
10

9
8
7
6
5

19 16 15 12 9

5~

6

20 IlBIl71l6IlSU4UJIl2U1
VCC
GNO
MM74CJ7J
[E
OUTPUT DIS
08 07 06 05 04 OJ 02 01

VCC

~iTI

13 17 14 13 8

7

4 13

VLL
VOO
A8
A7
A6
AS
A4
AJ
A2
A1

PS

B6

22

---¥.22

IP7

P8
SKIP

~

CSr!--

87

n5

21

9
35

csfl-

AD

n

"'ru

MM5204
512x8 EPROM
(TWO)

20

10
IFe

84

36
IPS

BJ

19

18

3

5

IP4 IP3

1
2

B2

B1

17

BO

16

6

15

7

8

IP1

IP2

33
AD/DATA

IPO

34
P9
40
39
38
37
31

COP402

4
11

1L-

~
13

COP420
PINOUT

--

{

GNO CI(O CKIAESET L7 L6
123456

LS
7

14

L4
8

15

IN1

16

17

IN2 VCC
10 11

18

L3
12

19

L2
13

20

21

L1 LO
14, 15

23

SI
16

24

SO
17

25

SK
18

FIgure 13. COP402 Usod to Emulate a COP420

1-21

26

27

INO Ifl3
19 20

28

GO
21

29

G1
22

G2
23

G3
24

03
25

02
26

01
27

DO
28

:E

~
o

RAM· Based System

If the user desires more program flexibility than is available wl'th PROM, a RAM memory system may be
constructed as outlined below; data and addresses are entered by switch, and data may be reviewed on LED
Indicators.

o

~
Q.

oo

+5

LOAD

~N

+5

~

P8.P9
CDP420
FUNCTIONS

COP402

I

74C373

IPO·IP7

IT

AD/DATA

-=-

74C151 x 3

ADO

+5

it

ADDRESS
SWITCHES

AD9

10

AO·A9
DATA
SWITCHES
+5

81LS95
07

-=LED
DATA
DISPLAY
x8

"J

+5

81 LS95

-=-

Figure 14. RAM· Based External Memory for COP402

1·22

COP402 MASK OPTIONS
COP402 Mask Options
The following COP420 options have been implemented in this basic version of the COP402. Subsequent versions of
the COP402 will implement different combinations of available options;- such versions will be identified as
COP402·A, COP402-B, etc.
Option Value

Comment

Option 1 = 0

Ground Pin available

Option 2 = 0

CKO is clock generator
output to crystal

Option 3 = 0

CKI is crystal Input.;. 16
(may be overridden externally)

Option 4

=0

RESET pin has load device to
Vee

Option 5

= 2 (402)

L7 has LED direct·drive
output
L7 has TRI·STATE® push·pull
output

= 3 (402M)
Option 6 = 2,3

L5 same as L7

= 2,3

L4 same as L7

Option 9 = 0 (402)
= 1 (402M)
Option 10

= 0 (402)
= 1 (402M)

IN1 has load device to Vee
HiZ
IN2 has load device to Vee
Hi Z

Option 11 = 0

Vce pin available

Option 12 = 2,3

L3 same as L7

Option 13 = 2,3

L2 same as L7

= 2,3

L1 same as L7

Option 14

no option

Option 15 = 2,3

LO same as L7

Option 16 = 0

SI has load device to Vee

Option 17
Option 18
Option 19

=2
=2
=0

I\)

s:

L6 same as L7

Option 7 = 2,3
Option 8

no option

SO has push·pull output
SK has push·pull output
INO has load device to Vee

Option 20 = 0 (402) IN3 has load device to Vee
= 1 (402M) HiZ
Option 21 = 0

GO has standard output

=0

G1 same as GO

Option 23 = 0

G2 same as GO

=0

G3 same as GO

Option 22

Option 24

Option 25 = 0

D3 has standard output

=0

D2 same as D3

Option 27 = 0

D1 same as D3

Option 28 = 0

DO same as D3

Option 26

Option 29 = 0 (402) normal operation
= 1 (402M) MICROBUSTM operation
Option 30 = N/A

o
o-a
8
~
o
o-a
8

40·pin package

1-23

~Nalional

PRELIMINARY

~ Semiconductor

COP404l ROMless N·Channel Microcontroller
General Description

Features

The COP404L ROM less Microcontroller is a member of
the COPSTM family, fabricated using N-channel, silicon
gate MOS technology. The COP404L contains CPU,
RAM, I/O and is identical to a COP444L device except
the ROM has been removed and pins have been added
to output the ROM address and to input the ROM data.
In a system the COP404L will perform exactly as the
COP444L. This important benefit facilitates development and debug of a COP program prior to masking the
final part. The COP404L is also appropriate in low
volume applications, or when the program might be
changing. The COP404L may be used to emulate the
COP444L, COP445L, COP420L, and the COP421 L

..
..
..
..
..

Exact circuit equivalent o! COP444L
Low cost
Powerful instruction set
128 x 4 RAM, addresses 2048 x 8 ROM
True vectored interrupt, plus restart
II Three·level subroutine stack
1/1 151's instruction time
III Single supply operation (4.5·9.5V)
!II Low current drain (15mA max @ 5V)
II Internal time·base counter for real·time processing
II Internal binary counter register with MICROWIRElM
compatible serial I/O
II!I General purpose and TRI·STATEll outputs
III LSTTLICMOS compatible in and out
II! Direct drive of LED digit and segment lines
II Software/hardware compatible with other members
of COP400 family

(COP404LS ONLY)
AD/DATA

CK!

~,

33

OK"

t,

1P0
IP,
IP,
IP,
IP.
IPs
IP,
IP,

P,
P,

D3
D,

SKIP/PUI

D,
"0

25

SK

11

31

G,
G,

",

If 0 CONTROLS

Go

L-----------------r-~~SD

1112131418192021
27 i6 1526
OKO
(COP404lP ONLY)

INJ Irl2 INt INo

Figure 1. COP404L Block Diagram

1-24

(')

o"'tJ

Absolute Maximum Ratings
Voltage at Any Pin Relative to GND
Ambient Operating Temperature
Ambient Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Power Dissipation

- 0.3V to + 10V
o'C to + 70'C
-65'Cto + 150'C
300'C
0.75 Watt at 25 'C
0.4 Watt at 70 'C

~
~

r-

Absolute maximum ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifica lions are not
ensured when operating the device at absolute maximum ratings.

DC Electrical Characteristics a'C < TA < + 70 'c, 4.5V < Vee < 9.5V unless otherwise noted.
Parameter
Operating Voltage (Ved
404LS
404LP
Operating Supply Current
Vee Power-Low Failsafe Trip
Level (404LS)

Conditions
(Note 2)
RESET open (Note 2)
RL = 510Q (Note 2)

Min

Max

Units

4.5
7.5
4.5

9.5
9.5
9.5

V
V
V

15

mA

7.5

V

0.4

V
V
V

0.6

V
V

0.6

V
V

Vee =5V, TA =25'C
(all inputs and outputs open)
RESET open

4.5

Vee =9.5V
Vee=5V±10%

3.0
2.0

Input Voltage Levels
CKI Input Levels
Crystal Input
Logic High (V 1H )
Logic High (V 1H )
Logic Low (V1d
Schmitt Trigger Input (+4)
Logic High (V 1H )
Logic Low (V1d

0.7 Vee

RESET Input Levels
Logic High
Logic Low

0.7 Vee

RESET Hysteresis

1.0

SO Input Level (Test mode)

2.0

All Other Inputs
Logic High
Logic High
Logic Low

Vee =9.5V
with TTL trip level options
selected, Vee=5V±10%

3.0
2.0

Logic High
Logic Low

with high trip level options
selected

3.6

V
3.0

V

O.B

V
V
V

1.2

V
V

0.4

V
V

0.4

V
V

Output Voltage Levels
LSTTL Operation
Logic High (VOH )
Logic Low (Vod

Vee=5V±5%
IOH = -25f1A
IOL=0.36mA

2.7

IPO-IP7, PB, P9, SKIP/P10
Output Voltage Levels
Logic High
Logic Low

RL = 15 kQ (Note 1)
IOH = -100flA
IOL=1.6mA

2.7

SO and SK Outputs (Iod

Ve e =9.5V, VOL = 1.0V
Vee = 4.5V, VOL = 1.0V

4.5
2.2

22
11

mA
mA

Lo- L7 Outputs

Vee = 9.5V, VOL = 1.0V
Vee = 4.5V, VOL = 1.0V

2.0
1.0

9.0
4.5

mA
mA

GO-G 3 and Do- D3 Outputs

Vee =9.5V, VOL=1.0V
Vee=4.5V, VOL=1.0V

30
15

150
75

mA
mA

RESET Output (COP404LP)

Vee = 4.5V, VOL = 1.0V

250

Output Current Levels.
Output Sink Current

1-25

flA

§...I

DC Electrical Characteristics

e..

oo

Parameter

(continued)

o·c .. TA ..

Conditions

+ 70·C, 4,5V" Vce" 9.5V unless otherwise noted.
Min

Max

Units

Output Source Current:
Standard Configuration,
All Outputs (I OH )

Vee =9.5V, VoH =4.75V
Vec=4.5V, VoH =2.25V

-70
-26

-450
-190

fiA
fiA

Push-Pull Configuration,
SO and SK Outputs (l oH )

Vee =9.5V, VoH =4.75V
Vee=4.5V, VoH =2.25V

-1.45
-0.07

-15.5
-2.8

mA
mA

Lo-L7 Outputs

Vec =9.5V, VOH=2.0V
Vee=6.0V, VOH=2.0V

-3.0
-3.0

-30
-20

mA
mA

-10

'+10

fiA

TRI-STATE® Output Leakage
Current

AC Electrical Characteristics o·c .. T A ..
Parameter

+ 70·C, 4.5V .. Vee" 9.5V unless otherwise specified.

Conditions

Instruction Cycle Time
CKI
Input Frequency fi
Duty Cycle
Rise Time
Fall Time

(+32 mode)

Min

Max

Units

15

40

fiS

0.8
30

2.097
60
120
80

MHz
%
ns
ns

fi = 2.097 MHz

INPUTS:
SI,IP7-IPO
tSETUP
tHOLD
IN 3 -IN o, G3 -G O' L7- LO
tSETUP
tHOLD

2.0
1.0

fiS
fiS

4.0
1.0

fiS
fiS

OUTPUTS:
COP TO CMOS PROPAGATION
DELAY

VoH =0.7V ee , VoL =0.3V ee ,
C L = 50pF

SO, SK Outputs
tpd1
tpdO
D3 -D o, G3 -G O' L7- LO
tpd1
tpdO
IP7-IPO, P8, P9, SKIP/P10

fiS
fiS

6.5
3.0

fiS
fiS

7.0
7.0

fiS
fiS

3.5
3.0

fiS
fiS

5.0
5.0

fiS
fiS

7.0
7.0

fiS
fiS·

RL = 15kQ (Note 1)

tpd1
tpdo
COP TO LSTTL PROPAGATION
DELAY

4.0
1.2

Vee=5V±5%, VOH=2.7V
VOL = 0.4V, CL =50pF

SO, SK Outputs
tpd1
tpdO
D3 - Do, G3 - Go, L7tpd1
tpdO

La

IP7-IPO, P8, P9, SKIP/P10

RL = 15kQ (Note 1)

tpd1
tpdQ
Note 1: Pull-up resistors required on COP404LP only; COP404LS has Push-Pull drivers on these outputs,
Note 2: Vee voltage change must be less than O.5Vlms to maintain proper operation.

1-26

C')

eKO
eKI
IP4
RESET
IP3

40
39
38

00
01
DZ

37

03
IPS
P8
P9

36
35

IPZ
IPI
IPO

34

IP7
IP6

10

L7

II

L6
L5
L4

IZ
13
I.

INI

IS

INZ

16

Vee
L3
LZ

17

COP404lP
COP404LS

18
19
20

LI

o"'0
~

~

r

33
3Z

AD/DATA

31
30

G3
GZ

Z9
Z8
Z7
Z6

GI
GO
IN3
INO

Z5
Z4

SK
SO

Z3
22

SI

SKlP/P10

VSS
LO

21

Figure 2. Connection Diagram

Description

Pin

Description

Pin

LrLo

B bidirectional I/O ports with
TRI·STATE®

G3-G O

4 bidirectional I/O ports

DrDo

CKI

System oscillator input

CKO

General purpose input (COP404LP)
System oscillator output (COP404LS)

4 general purpose outputs

RESET

System reset input

IN3-INo

4 general purpose inputs

Vce

Power supply

SI

Serial input (or counter input)

GND

Ground

SO

Serial output (or general purpose output)

IP7-IPO

SK

Logic·controlled clock (or general
purpose output)

B bidirectional ROM address and data
ports

PB, P9

2 ROM address outputs

ADIDATA

Address out/data' in flag

SKIP/P10

Instruction skip output and ROM address
output

CKI

AO/l!ATiI, SK
(AS A CLOCK)
INO-IN3, GO-G3,
LO-L7, CKO, SI
IPO-IP7 INPUTS
GO-G3, 00-03,
LO·l7, SO, SI
OUTPUTS
SKIP/PIO
OUTPUT

-'1

1:- tpdl

-pVOH

I'

,I

t - tpdO

1

~VI~tSETup_~~tH---'o~'-_-1----;[~,.--..\

============I.=:::~-J

7_-,

- - - - - - - - - - - ''-'...1___

x::=, \
I

VOH

1

'

'

t p d O - t VOL

~

~-~~-H-~(S~K~IP~I---~~~_-_~~~~L_~(_PI_O)~_ _~-~tP_dO~_V~OL~~_ _ _ _ _~-~_t~P_d_']~'~-H----

I.

IPO-IP7, PB, PO
OUTPUTS

-1

tPdl---d

_ _ _-,-_-'I_r_--;~r---- ---- -- -

-

~tPdo~
,

Figure 3. Input/Output Timing Diagram

1-27

~ VOL

...I

~
c..

o()

FUNCTIONAL DESCRIPTION
A block diagram of the COP404L is given in figure 1. Data
paths are illustrated in simplified form to depict how the
various logic elements communicate with each other in
implementing the instruction set of the device. Positive
logic is used. When a bit is set, it is a logic "1" (greater
than 2 volts). When a bit is reset, it is a logic "a" (less
than 0.8 volts).

cycle time. (See XAS instruction and EN register description, below.)

Program Memory

The G register contents are outputs to 4 generalpurpose bidirectional I/O ports. G I/O ports can be
directly connected to the digits of a multiplexed LED
display.

Four general-purpose inputs, IN 3 -IN o, are provided.
The D register provides 4 general-purpose outputs and
is used as the destination register for the 4-bit contents
of Bd. The D outputs can be directly connected to the
digits of a multiplexed LED display.

Program Memory consists of a 2048 byte external memory. As can be seen by an examination of the COP404L
instruction set, these words may be program instruc·
tions, program data or ROM addressing data. Because of
the special characteristics associated with the J P, JSRP,
JID and LQID instructions, ROM must often be thought
of as being organized into 32 pages of 64 words each.

The Q register is an internal, latched, 8-bit register, used
to hold data loaded to or from M and A, as well as 8-bit
data from ROM. Its contents are output to the L I/O
ports when the L drivers are enabled under program
control. (See LEI instruction.)

ROM addressing is accomplished by a 1.1-bit PC
register. Its binary value selects one of the 2048 8-bit
words contained in ROM. A new address is loaded into
the PC register during each instruction cycle. Unless
the instruction is a transfer of control instruction, the
PC register is loaded with the next sequential 11-bit
binary count value. Three levels of subroutine nesting
are implemented by the·11-bit subroutine save registers,
SA, SB and SC, providing a last·in, first-out (LIFO)
hardware subroutine stack.

The 8 L drivers,when enabled, output the contents of
latched Q data to the L I/O ports. Also, the contents of L
may be read directly into A and M. L I/O ports can be
directly connected to the segments of a multiplexed
LED display (using the LED Direct Drive output configuration option) with Q data being outputted to the Sa-Sg
and decimal point segments of the display.
The SIO register functions as a 4-bit serial-in/serial-out
shift register or as a binary counter depending on the
contents of the EN register. (See EN register description, below.) Its contents can be exchanged with A, allowing it to input or output a contin.uous serial data
stream. SIO may also be used to provide additional
parallel I/O by connecting SO to external serial·in/parallelout shift registers.

ROM instruction words are fetched, decoded and
executed by the Instruction Decode, Control and Skip
Logic circuitry.

Data Memory
Data memory consists of a 512-bit RAM, organized as 8
data registers of 16 4-bit digits. RAM addressing is implemented by a 7-bit B register whose upper 3 bits (Br)
select 1 of 8 data registers and lower 4 bits (Bd) select 1
of 16 4-bit digits in the selected data register. While the
4-bit contents of the selected RAM digit (M) is usually
loaded into or from, or exchanged with, the A register
(accumulator), it may also be loaded into or from theQ
latches or loaded from the L ports. RAM addressing may
also be performed directly by the LDD and XAD instructions based upon the 7-bit contents of the operand field
of these instructions. The Bd register also serves as a
source register for 4-bit data sent directly to the D
outputs.

The XAS instruction copies C into the SKL latch. In the
counter mode, SK is the output of SKL; in the shift
register mode, SK outputs SKL AN Ded with the clock.
The EN register is an internal 4-bit register loaded under
program control by the LEI instruction. The state of
each bit of this register. selects or deselects the
particular feature associated with each bit of the EN
register (EN 3 - EN o).
1. The least Significant bit of the enable register, EN o,
selects the SIO register as either a 4-bit shift register
or a 4-bit binary counter. With EN o set, SIO is an
asynchronous binary counter, decrementing its value
by one upon each low-going pulse ("1" to "a") ocur·
ring on the SI input. Each pulse must be at least two
instruction cycles wide: SK outputs the value of SKL.
The SO output is equal to th.e value of EN 3 . With EN o
reset, SIO is a serial shift register shifting left each
instruction cycle time . .The data present at SI goes
into the least significant bit of SIO. SO can be
enabled to output the most significant bit of SIO
each cycle time. (See 4 below.) The SK output be:
comes a logic·controlled clock.

Internal Logic
The 4-bit A register (accumulator) is the source and
destination register for most I/O, arithmetic, logic and
data memory access operations. It can also be used to
load the Br and Bd portions of the B register, to 10ad and
input 4 bits of the 8-bit Q latch data, to input 4 bits of the
8-bit L I/O port data and to perform data exchanges with
the SIO register.

2. With EN 1set the IN1 input is enabled as an interrupt
input. Immediately following an interrupt, EN1 is
reset to disable further interrupts.

A 4·bit adder performs the arithmetic and logic functions, storing its results in A. It also outputs a carry bit
to the 1-bit C register, most often employed to indicate
arithmetic overflow. The C register, in conjunction with
the XAS instruction and the EN register, also serves to
control ihe SK output. C can be outputted directly to SK
or can enable SK to be a sync clock each instruction

3. With EN2 set, the L drivers are enabled to output the
data in Q to the L I/O ports. Resetting EN2 disables
the L drivers, placing the L I/O ports in a highimpedance input state.

1-28

4. EN 3, in conjunction with EN o, affects the SO output.
With ENo set (binary counter option selected) SO will
output the value loaded into EN 3. With ENo reset
(serial shift register option selected), setting EN3
enables SO as the output of the SIO shift register,
outputting serial shifted data each instruction time.
Resetting EN3 with the serial shift register option
selected disables SO as the shift register output;
data continues to be shifted through SIO and can be
exchanged with A via an XAS instruction but SO remains reset to "0." The table below provides a summary of the modes associated with EN3 and EN o.

logic status is saVed and program control is transferred to the interrupt servioing routine at hex
address OFF. At the end of the interrupt routine, a
RET instruction is executed to "pop" the stack and
return program control to the instruction following
the original ASC. At this time, the skip logic is
enabled and skips this instruction because of the
previous ASC carry. Subroutines and LQID instructions should not be nested within the interrupt
service routine, since their popping the stack will
enable any previously saved main program sldps, interfering with the orderly execution of the interrupt routine.
d. The first instruction of the interrupt
address OFF must be a Nap.

Interrupt
The following features are associated with the IN1
interrupt procedure and protocol and must be considered by the programmer when utilizing interrupts.

routi~e

at hex

e. A LEI instruction can be put immediately before the
RET to re·enable interrupts.
Initialization

a. The interrupt, once acknowledged as explained
below, pushes the next sequential program counter
address (PC + 1) onto the stack, pushing in turn the
contents of the other subroutine·save registers to the
next lower level (PC + 1 ~ SA ~ SB ~ SC). Any
previous contents of SC are lost. The program
counter is set to hex address OFF (the last word of
page 3) and EN1 is reset.

The Reset Logic will initialize (clear) the device upon
power·up if the power supply rise time is less than 1 ms
and greater than 11's. If the power supply rise time is
greater than 1 ms, the user must provide an external RC
network and diode to the RESET pin as shown below.
The RESET pin is configured as a Schmitt trigger input.
If not used it should be connected to Vce. Initialization
will occur whenever a logic "0" is applied to the RESET
input,provided it stays low for at least three instruction
cycle times.

b. An interrupt will be acknowledged only after the following conditions are met:
1 . EN 1 has been set.
2. A low-going pulse ("1" to "0") at least two instruc·
tion cycles wide occurs on the IN1 input.
3. A currently executing instruction has been completed.
4. All successive transfer of control instructions and
suocessive LBls have been completed (e.g., if the
main program is executing a JP instruction which
transfers program control to another JP instruction, the interrupt will not be acknowledged until
the second JP instruction 11as been executed.

RC;;' 5 x POWER SUPPL V RISE TIME

c. Upon acknowledgement of an interrupt, the sldp
logic status is saved and later restored upon popping
of the stack. For example, if an interrupt occurs
during the execution of ASC (Add with Carry, Skip on
Carry) instruction which results in carry, the skip

NOTE: IF POWER-LOW FAILSAFE OPTION
IS SELECTED. THE RC AND DIODE
CIRCUIT IS NOT USED

Enable Register Modes - Bits EN3 and ENO
EN3

ENo

SIO

SI

SO

SK

0

0

Shift Register

Input to Shift Register

0

If SKL= 1, SK = CLOCK
If SKL = 0, SK = 0

1

0

Shift Register.

Input to Shift Register

Serial Out

If SKL = 1, SK = CLOCK
If SKL = 0, SK = 0

0

1

Binary Counter

Input to Binary Counter

0

If SKL = 1, SK = 1
If SKL = 0, SK = 0

1

1

Binary Counter

Input to Binary Counter

1

If SKL = 1, SK = 1
If SKL = 0, SK = 0

1-29

..J

ic..

oo

Upon initialization, the PC register is cleared to 0 (ROM
address 0) and the A, B, C, D, EN,and G registers are
cleared. The .SK output is enabled as a SYNC output,
providing a pulse each instruction cycle time. Data
Memory (RAM) is not cleared upon initialization. The
first instruction at address 0 must be a CLRA.

b. Open·Drain - an enhancement·mode device to
ground only, allowing external pull·up as required by
the user's application. (Used on IP, P and SKIP/P10
outputs on COP404LP only).
c. Push· Pull An enhancement·mode device to
ground in conjunction with a depletion·mode device
paralleled by an enhancement·mode device to Vec.
This configuration has been provided to allow for
fast rise and fall times when driving capacitive loads.
(Used on SO and SK outputs on COP404LP and
404LS; also used on IP, P and SKIP/P10 outputs on
COP404LS only.)

External Memory Interface
The COP404L is designed for use with an external
Program Memory. This memory may be implemented
using any devices having the following characteristics:

d. LED Direct Drive - an enhancement·mode device to
ground and to Vec, meeting the typical current
sourcing requirements of the segments of an LED
display. The sourcing device is clamped to limit
current flow. These devices may be turned off under
program control (See Functional Description, EN
Register), placing the outputs in a high·impedance
state to provide required LED segment blanking for a
multiplexed display. (Used on L outputs).

1. random addressing
2. TTL·compatible TRI·STATE® outputs
3. TTL-compatible inputs
4. access time = 51's max
Typically these requirements are met using bipolar or
MOS PROMs.
During operation, the address of the next instruction is
sent out on P10, P9, P8, and JP7 through IPO during the
time that ADIDATA is high (logic "1" = address mode).
Address data on the IP lines is stored into an external
latch on the high-to·low transition of the ADIDATA line;
P9 and P8 are dedicated address outputs, and do not
need to be latched. SKIP/P10 outputs address data
when ADIDATA is low. When AD/DATA is low (logic
"0" data mode), the output of the memory is gated
onto IP7 through IPO, forming the input bus. Note that
the AOIDATA output has a period of one instruction
time, a duty cycle of approximately 50%, and specifies
whether the IP lines are used for address output or
instruction input.

COP404L inputs have an on-chip depletion load device
to Vee.
The above input and output configurations share
common enhancement·mode and depletion·mode devices.
Specifically, all configurations use one or more of six
devices (numbered 1- 6, respectively). Minimum and
maximum current (lOUT and VOUT) curves are given in figure
6 for each of these devices to allow the designer to effec·
tively use these I/O configurations in designing a system.

=

An important point to remember is that even when the L
drivers are disabled, the depletion load device will source
a small amount of current (see figure 6, device 2); however,
when the L·lines are used as inputs,the disabled depletion
device can not be relied on to source sufficient current to
pull an input to a logic "1".

Oscillator
Two basic clock oscillator configurations have been
implemented, as shown in figure 4.

Power-Low Failsafe Option (COP404LP only)

a. Crystal Controlled Oscillator (COP404LS only). CKI
and CKO are connected to an external crystal. The
instruction cycle time equals the crystal frequency
divided by 32

If the power supply voltage drops, an on·chip level de·
tection circuit will force the RESET pin low and reset
the chip while the power supply is still within the operating range. Reset will occur .with Vcc between 4.5 and
7.5 volts, allowing normal system operation between 7.5
and 9.5 volts. RESET is an output in this mode and can
drive other circuits.

b. External Oscillator (COP404LP only). CKI is an
external clock input signal. The external frequency is
divided by 32 to give the instruction cycle time. CKO
is used as a general purpose input.

This feature, implemented on the COP404LP only, can
be overridden by connecting RESET to Vcc through a
510Q resistor.

CKO as an Input
On the COP404LP, CKO has been configured as a general·
purpose input. The logic level applied to CKO will be
read into bit 2 of A (accumulator) upon execution of an
INIL instruction.

COP404LP and COP404LS
Two versions of the basic COP404L have been imple·
mented: the COP404LP, with open·drain memory inter·
face drivers, is used only in .the COP400- E04L Emulator
Card; the COP404LS, with push·pull memory interface,
is intended for use in small to medium volume produc·
tion appl ications.

Input/Output Configurations
COP404L outputs have the following configurations, illustrated in figure 5:
a. Standard - an enhancement mode device to ground
in conjunction with a depletion-mode device to Vee,
compatible with LSTTL and CMOS input require·
ments. (Used on D and G outputs.)

1-30

COP404LS

COP404LP

1M
EXTERNAL
CLOCK

GENERAL
PURPOSE INPUT

Jl..I"L

Figure 4. Oscillator

a. Standard Output

b. Open· Drain Output

c. Push·Pull Output

VCC

'-H~

#6

INPUT~f
e. Input with Load

d. L Output (LED)

I ... IS DEPLETION DEVICEI

Figure 5. Output Configurations

1-31

Input Current for Lo through
L7 when Output Programmed
Off by Software

Current for Inputs with
Load Device
-100

I
I

-90
-80

~

0

-900

~

-800
-700

j

'\

-50

IMAX@
~
-400
is'CC" '.5~
~
-300
IMIN@
Vcc" .5V.!. l~
-200
IMIN
~ JI~~c" 9.5
-100

1-'1"

I MAX}
VCC"'·5V

o

' \ IMAX@VCC"9.5V

-500

!:

~

IMIN@Vec"g·5V

-10

'\

-600

'"

'\

-20

::-...

~IN_rVCr 1.5

o

9.5

DEVICE a #2

DEVICE d #2

I\.

-60

,
~ -40
-30

1.0 2.0 3.0 '.0 5.0 6.0 7.0 8.0

-1000

I

I'\.IMAX@VCC"9.0V

-70

j

Source current for Standard
Output Configuration

Ii'-

~=-

1'.0

o

2.0

1

2

V 110

VI~j (VOLTS)

Source Current for SO and
SK in Push·Pu" Configuration

''\

_....... ~

o I-t-

3

•

5

6

7

~
B

9.5

VOH (VOLTS)

LED Output Direct Segment
and Digit Drive

L Output Source Current
-50

, DEVICE d f2 AND *4

AND DEVICE a '1

,-40
IMAX
ONE SEGMENTS

L

-30

"'"

V

.!
0

I-

-20

........./

V

~MAXEIGHT
SEGMENTS ON
............ , ..... IMIN

-10

1

I

:::: .......

10
VOH (VOLTS)

LED Output Direct Segment
Drive

Output Sink Current for SO
and SK

-50 r'::--""""...,--,--,---,---,
VOH"2.0V
DEVICE d
*2 AND,.

i~ f -

'"

!:

-20

"
..s

.....

.'
..........

I

!:

B

o

10

I

I

..
.'

......

'

If ..
V 'TYTr

to

IMIN

I

IMAX @.~.e~.:r-Y

'

lAir ........
....

-10

IMAX@Vec"9.5V

: :
f f t-

15
-30

IDEVICE c 11

~V 1~".1v
J I-I I
o

1

2

3

•

5

6

7

8

7

Output Sink Current IPO·IP7,
P8, P9, SKIP/P10
-30

400 r-.,.."'T'""""'-;-~=="""'''

-25

!:

10
VOL (VOLTS)

Output Sink Current Go·G 3
and 00.03

"~

9

VOL (VOLTS)

Vcc (VOLTS)

300

Output Sink Current for Lo
through L7

20

-40~--+---+---+---1---+---4

:;;
.!

Vcc (VOLTS)

I-'-+-r-t--t--t-++-+-t--l

-20

"5
.!

200~~-r-+~~~4-~-+~r-~

-10
-5

5

6

vcc

.5vlMAX)

VCC" 9.!V

-15

!:

4

J4
.IJ-t- VC~" gL (~A~)
f"
(MI~J......-!

7

VOL (VOLTS)

U k-r]
V.

f

VCC"'.5V (MIN)

11
VOUT(VOLTS)

Figure 6. 1/0 Characteristics

1-32

-

8

9

10

COP404L INSTRUCTION SET
Table 2 provides the mnemonic, operand, machine code,
data flow, skip conditions and description associated
with each instruction in the COP404L instruction set.

Table 1 is a symbol table providing internal architecture,
instruction operand and operation symbols used in the
instruction set table.

Table 1. COP404L Instruction Set Table Symbols

Symbol.

Definition

Symbol

Definition

INTERNAL ARCHITECTURE SYMBOLS

INSTRUCTION OPERAND SYMBOLS

A
B
Br
Bd
C
D
EN

d

G
IL
IN
IP
L
M

P
PC
Q

SA
SB
SC
SIO
SK

4·bit Accumulator
7·bit RAM Address Register
Upper 3 bits of B (register address)
Lower 4 bits of B (digit address)
1·bit Carry Register
4·bit Data Output Port
4-bit Enable Register
4-bit Register to latch data for G 110 Port
Two 1-bit Latches associated wi.th the IN3 or
INa Inputs
4-bit Input Port
8-bit Bidirectional ROM address and data
port
8-bit TRI-STATE 110 Port
4-bit contents of RAM Memory pointed to by
B Register
3-bit ROM address port
11-bit ROM Address Register (program
counter)
B-bit Register to latch data for L 110 Port
11-bit Subroutine Save Register A
11-bit Subroutine Save Register B
11-bit Subroutine Save Register C
4-bit Shift Register and Counter
Logic-Controlled Clock Output

a

RAM(s)
ROM(t)

4·bit Operand Field, 0-15 binary (RAM Digit
Select)
3·bit Operand Field. 0- 7 binary (RAM
Register Select)
11-bit Operand Field, 0-2047 binary (ROM
Address)
4-bit Operand Field, 0-15 binary (Immediate
Data)
Contents of RAM location addressed by s
Contents of ROM location addressed by t

OPERATIONAL SYMBOLS

+

A

1-33

Plus
Minus
Replaces
Is exchanged with
Is equal to
The ones complement of A
Exclusive-OR
Range of values

...J

IIII:t

Table 2. COP404L Instruction Set

iQ.

o
o

Mnemonic Operand

Hex
Code

Machine
Language Code
(Binary)

Data Flow

Skip Conditions

Description

ARITHMETIC INSTRUCTIONS
ASC

30

10011100001

A+C+RAM(B)- A
Carry - C

Carry

Add with Carry, Skip on
Carry

ADD

31

1°°111°°011

A+RAM(B) - A

None

Add RAM to A

ADT

4A

1° 1 °°11 ° 101

A+10lO- A

None

Add Ten to A

5-

1° 101 1

A+y-A

Carry

Add Immediate, Skip on
Carry (y ,,0)

10

1°0011°00°1

Ii: + RAM(B) + C - A

Carry

Complement and Add with
Carry, Skip on Carry

AISC

Y

CASC

y

I

Carry - C
CLRA

00

10 ° ° 010 ° ° 01

0- A

None

Clear A

COMP

40

1°10°1°00°1

A-A

None

Ones complement of A to A

NOP

44

1°10°1° 1 001

None

None

No Operation
Reset C

RC

32

1°0111°01°1

"0" - C

None

SC

22

1° 01 °1°° 1 01

"1" - C

None

Set C

XOR

02

1°0°°1°° 1 01

A

None

Exclusive·OR RAM with A

ai

RAM(B)- A

TRANSFER OF CONTROL INSTRUCTIONS
JID
JMP

FF

a

6--

JP

a

JSRP

a

JSR

a

Jump Indirect (Note 2)

11111111111

ROM (PC10:8, A,M) - PC7:0 None

1°11 °10IalO:81

a - PC

None

Jump

None

Jump within Page (Note 3)

PC + 1 - SA - SB - SC
00010 - PC10:6
a - PC5:0

None

Jump to Subroutine Page
(Note 4)

PC + 1 - SA - SB - SC
a - PC

None

Jump to Subroutine

1

a7:0

I

--

a6:0
111
I
(pages 2,3 only)
or

a - PC6:0

--

11 11 a5:0
(all other pages)

I

a - PC5:0

--

11 °1

a5:0

I

6-

1011°11Ia10:81

--

I

a7:0

RET

48

1° 1 °°11 0001

RETSK

49

I

1° 1 °°11 001 1

SC - SB - SA - PC

None

Return from Subroutine

SC - SB - SA - PC

Always Skip on Return

Return from Subroutine
then Skip

1-34

Table 2. COP404L Instruction Set (continued)

Mnemonic Operand

Hex
Code

Machine
Language Code
(Binary)

Data Flow

Skip Conditions

Description

MEMORY REFERENCE INSTRUCTIONS
CAMQ

CQMA

LD

r

LDD

r,d

5MB

\0011\0011\
\00 11\1100\

A - Q7:4
RAM(B) - Q3:0

None

Copy A, RAM to Q

Q7:4 - RAM(B)
Q3:0 - A

None

Copy Q to RAM, A

Load RAM into A,
Exclusive·OR Br with r

33

\00 11\00 11\

2C

\00 10\1100\

-5

\00\ r \0 10 1\
(r-0:3)

RAM(B) - A
Br .. r - Br

None

23

\00 10\00 11\

RAM(r,d) - A

None

\0\ r \

BF

\1011\1111\

ROM(PC10:S,A,M) - Q
SB- SC

None

Load Q Indirect (Note 2)

a

4C

\0 100\1100\

0- RAM(B)O

None

Reset RAM Bit

1

45

\0 1 00\0 1 a 1\

0- RAM(Bl1

None

Set RAM Bit

y - RAM (B)
Bd+1-Bd

None

Store Memory Immediate
and Increment Bd

None

Exchange RAM with A,

d

\

2

42

\0100\0010\

0- RAM(B)2

3

43

\0100\0011\

0- RAM(B)3

a

4D

\0100\1101\

1 - RAM(B)O

1

47

\0 100\1101\

1- RAM(Bh

2

46

\0100\0110\

1 - RAM(B)2

3

4B

\0 100\1011\

1- RAM(B)3

STII

Y

7-

\0 111\

X

r

-6

\00\ r \0 110\
(r-0:3)

RAM(B)- A

RAM(r,d) - A

XAD

Load A with RAM painted
to directly by r,d

-LQID

RMB

33
3C

r,d

y

\

23

\00 10\00 11\

--

\1\ r \

d

Exclusive·OR Br with r

BrEll r - Br

Exchange A with RAM

None

painted to directly by r,d

\

XDS

r

-7

\00\ riO 1111
(r=0:3)

RAM(B)- A
Bd-1- Bd
Br Ell r - Br

Bd decrements past

a

Exchange RAM with A
and Decrement Bd,
Exciusive·OR Br with r

XIS

r

-4

\00\ r \0 1 00\
(r-0:3)

RAM(B)- A
Bd+1- Bd
BrEll r - Br

Bd increments past 15

Exchange RAM with A
and Increment Bd,
Exclusive·OR Br with r

REGISTER REFERENCE INSTRUCTIONS
CAB

50

\0101\00001

A- Bd

None

Copy A to Bd

CBA

4E

\0 1 00\111 0\

Bd - A

None

Copy Bd to A

--

\00\ r \(d -1)\
(r=0:3;
d =0,9:15)
or

r,d - B

Skip until not a LBI

LBI

LEI

XABR

r,d

Y

33

\00 11\00 11\

--

\1\ r \ d \
(any r, any d)

33

\0011\0001\

6-

\0110\

12

\0001\ 0010 1

Y

Load B Immediate with r,d
(Note 5)

y- EN

None

Load EN Immediate (Note 6)

A-Br(0-A3)

None

Exchange A with Elr

\

1·35

..J
~

Table 2. COP404L Instruction Set (continued)

ic..

o
()

Hex
Code

Machine
Lanyuage Code
Binary)

SKC

20

1°01°1°00°1

C="1"

Skip if C is True

SKE

21

1°°1°10.0011

A=RAM(B)

Skip if A Equals RAM

SKGZ

33

1°011100111

G3:0

Skip if G is Zero (all 4 bits)

21

1°01°1°0011

33

1°°111°°111

Mnemonic Operand

Data Flow

Skip Conditions

Description

TEST INSTRUCTIONS

SKGBZ
0

SKMBZ

01

1st byte

Skip if G Bit is Zero
GO=O

1

11

I" "I'" '}

2

03

1°°001°°111

3

13

1°0011°°111

0

01

10000100011

RAM(B)O=O

1

11

10001100011

RAM(B)1 =0

2

03

10000100111

RAM(B)2=0

3

13

10001100111

RAM(B)3=0

41

1°1001°0011

A time-base counter
carry has occurred
since last test

Skip on Timer (Note 2)

G-A

None

Input G Ports to A

IN- A

None

Input IN Inputs to A

IL3, CKO, "0", ILa - A

None

Input IL Latches to A
(Note 2)

None

Input L Ports to RAM,A

SKT

GFO

10001100011

2nd byte

G2=0
G3=0
Skip if RAM Bit is Zero

INPUT/OUTPUT INSTRUCTIONS
ING

ININ

INIL

INL

OBO

OGI

OMG

XAS

y

33

1°011100111

2A

100 1 011 0 1 01

33

1°°11100111

28

10010110001

33

1°011100111

29

1001 °11 0011

33

10011100111

L7:4 - RAM (B)

2E

10010111101

L3:0 - A
Bd - 0

None

Output Bd to 0 Outputs

33

1°0111°0111

3E

1°0111111°1

33

1°0111°0111
y
1° 101 1

y-G

None

Output to G Ports Immediate

533

1°011100111

RAM(B)- G

None

Output RAM to G Ports

3A

1°0111101°1

4F

10100111111

A - SIO, C - SKL

None

Exchange A with SIO
(Note 2)

I

Note 1: All subscripts for alphabetical symbols indicate bit numbers unless explicitly defined (e.g., Sr and Bd are explicitly defined). Bits are numbered 0 to
N where 0 signifies the least significant bit (low-order, right·most bit). For example, A3 indicates the most significant (Ieft·most) bit of the 4·bit A register.
Note 2: For additional information on the operation of the XAS,

Ji'o, LalE>, INIL, and SKT instructions, see below.

Note 3: The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two·page boundary of pages 2 or 3. The JP
instruction, otherwise, permits a jump to a ROM location within the current 64-word page. JP may not jump to the last word of a page.

Note 4: A JSRP transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of Pl. A JSRP may not be used when in pages 2 or 3.
JSRP may not jump to the last word in page 2.

Note 5: LBI is a single-byte mstruction if d = 0,9.10. ", 12, 13, 14, or 15. The machine code for the lower 4 bits equals the binary value of the "d" data
minus 1, e.g_. to load the lower four bits of B (Bd) with the value 9 (100121, the lower 4 bits of the LBI instruction equal 8 (10002)' To load 0, the lower 4 bits of

the LBllnstructlon should equal ,51""2).
Note 6: Machine code for operand field y for LEI instruction should equal the binary value to be latched into EN, where a "1" or "0" in each bit of EN
corresponds ~ith the selection or deselect ion of a particular function aSSOciated, with each bit(See Functional Description, EN Register.)

1-36

(')

o
."

The followi~g information is provided to assist the user
in understanding the operation of several unique instructions and to provide notes useful to programmers in
writing COP404L programs_

~

o

.s::..
r-

CuP404L

XAS Instruction

ININ

XAS (Exchange A with SIO) exchanges the 4-bit contents
of the accumulator with. the 4-bit contents of the 510
register. The contents of SIO will contain serial-in!
serial-out shift register or binary counter data, depending
on the value of the EN register. An XAS instruction will
also affect the SK output. (See Functional Description,
EN Register, above,) If 510 is selected as a shift register, an XAS instruction must be performed once every 4
instruction cycles to effect a continuous data stream,

It'DI

1N

I

3

L
G[

1

JjImJ

l"'~r:=~

.~--~

LJ

{, RESET
lNll

J I D lilstruciion
JID (Jump Indirect) is an indirect addressing instruction,
transferring program control to a new ROM location
pointed to indirectly I}y A and M_ It loads the lower 8 bits
oi the ROM address register PC with the contents of
ROM addressed by the II-bit word, PC 1O :S ' A, 'M_ PC 10 ,
PC g and PC a are not affected by this instruction,

Figure 7, INIL Hardware Implementation

Note that JID requires 2 instruction cycles,

SKT Instruction

INIL Instruction

The SKT (Skip On Timer) instruction tests the state of an
internal 10-bit time-base counter. This counter divides
the instruction cycle clock frequency by 1024 and provides a latched indication of counter overflow, The SKT
instruction tests this latch, executing the next program
instruction if the latch is not set. If the latch has been
set since the previous test, the next program instruction
is skipped and the latch is reset. The features associated with this instruction, therefore, allow the COP404L
to generate its own time-base for real-time processing
ratlier than relying on an external input signal.

INIL (Input IL Latches to A) inputs 2 latches, IL3 and ILo
(see figure 7) and CKO into A, The IL3 and ILo latches are
set if a low-going pulse ("1" to "0") has occurred on the
IN3 and INo inputs since the last INIL instruction, provided
the input pulse stays low for at least two instruction
times_ Execution of an INIL inputs IL3 and ILo into A3
, and AO respectively, and resets these latches to allow
them to respond to subsequent low-going pulses on the
IN3 and INo lines_INIL will input the state of CKO into A2
on the COP404LP ("1" into A2 for the COP404LS)_ A "0"
is always placed in AI upon the execution of an INIL
The general purpose inputs IN3-INo are input to A upon
execution of an ININ instruction_ (See table 2, ININ instruction_) INIL is useful in recognizing pulses of short
duration or pulses which occur too often to be read conveniently by an IN IN instruction,

For example, using a 2_097 MHz oscillator as the time. base to the clock generator, the instruction cycle clock
frequency will be 65kHz (crystal frequency"," 32) and the
binary counter output pulse frequency will be 64Hz_ For
, time-of-day or similar real-time processing, the SKT instruction can call a routine which increments a
"seconds" counter every 64 ticks_

Note: I L latches are not cleared on reset.

Instruction Set Notes

LQID Instruction
LaiD (Load a Indirect) loads the 8-bit a register with the
contents of ROM pointed to by the II-bit word PC 10 ,
PCg, PCa, A, M_ LaiD can be used for table lookup or
code 'conversion such as BCD to seven-segment. The
LaiD instruction "pushes" the stack (PC + 1 - SA - SB
-SC) and replaces the least significant 8 bits of PC as
follows: A - PC 7:4, RAM (B) - PC 3:0 , leaving PC 10, PCg
and PCa unchanged_ The ROM data pointed to by the
new address is fetched and loaded into the a latches_
Next, the stack is "popped" (SC - S8 - SA -PC),
restoring the saved value of PC to continue sequential
program execution_ Since LaiD pushes S8 - SC, the
previous contents of SC are lost. Also, when LaiD pops
the stack, the previously pushed contents of SB are left
in SC_ The net result is that the contents of SB are placed
in SC (SB -. SC)_ Note that LaiD takes two instruction
cycle times to execute,

1-37

a_ The first word of a COP404L program (ROM address
0) must be a CLRA (Clear A) instruction,
b_ Although skipped instructions are not executed, one
instruction cycle time is devoted to skipping each
byte of the skipped instruction_ Thus all program
paths take the same number of cycle times whether
instructions are skipped or executed_
c_ The .ROM is organized into 32 pages of 64 words
each, The Program Counter is an II-bit binary counter, and will count through page boundaries_ If a J P,
JSRP, JID or LaiD instruction is located in the last
word of a page, the instruction operates as if it were
.inthe next page_ For example: a JP located in the last
word of a page will jump to a location in the next
page_ Also, a LaiD or JID located in the last word of
page 3, 7, 11, 15, 19, 23 or 27 will access data in the
next group of four pages,

...I

~
c..

oo

TYPICAL APPLICATIONS
PROM·Based System
The COP404L may be used to exactly emulate the
COP444L. Figure 8 shows the interconnect to imple·
ment a COP444L hardware emulation. This connection
uses a MM2716 EPROM as external memory. Other
memory can be used such as bipolar PROM or RAM.

When ADIDATA turns off, the EPROM is enabled and the
IP7·IPO pins will input the memory data. P8, P9 and
SKIP/P10 output the most significant address bits to
the memory. (SKIP output may be used for program
debug if needed.)

Pins IP7·IPO are bidirectional inputs and outputs. When
the ADIDATA clocking output turns on, the EPROM
drivers are disabled and IP7·IPO output addresses. The
8·bit latch (MM74C373) latches the addresses to drive
the memory.

The other 28 pins of the COP404L may be configured ex·
actly the same as a COP444L. The COP404L Vec can
vary from 4.5V to 9.5V. However, 5 volts is used for the
memory.

12 GNO
1
A,
2
A6
3
A,
4
A,
5
A3
6
A,
7
A,

....--!

+5V

- r1!!

~
~

~+5V

Vee
Vpp 21

MM2716
2048 x 8 EPROM

A,o
Ag

19
22

A. E....DE ~
CE ~

Ao
0, 06 0, 0, 03 0, 0, 00
17 16 15 14 13 11 10 9

19 16 15 12 9 6 5 2
D. 0, 0, 0, 0, 03 0, 0,
Vee
GND

RL-15k
[E"

MM74C373

REDUIRED ON
COP404LP ONLY

OUTPUT OIS
D. 0, 0, 0, 0, 03 0, 0,
18 17 14 13 8 7 4 3

I

+5V

J.

22

9 10 36 3 5 6 7 8
IP, IP, IP, IP, IP3 IP, IP, IPo

33 35 34 32
AD! p. Pg SKIP!
DATA
P,o

1
40

2
4
11

COP404LP
COP404LS

12

38

~

I-

~
14 15 16 17 18 19 20 21

GNO CKO CKI RESEll, L, L,
1234567

39

23 24 25 26 27 28 29 30 31

L, IN1 IN2 Vee L3 L, L, La SI SO SK INa IN3 Go G, G,
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Figure 8. COP404L System Diagram

1-38

G3 03 0, 0, Do
24 25 26 27 28

I

COP444L
PINOUT

COP404L Mask Options
The following COP444L options have been implemented on the basic versions of the COP404L:
Option Value

Comment

Option Value

Comment
SK has push-pull output

Option 1 =0

Ground, no option available

Option 18 = 2

Option 2 = 0 (404LS)

CKO is clock generator output
to crystal/resonator
CKO is general purpose input
with load device to Vee

Option 19=0

INO has load device to Vce

Option 20 = 0

IN3 has load device to Vee

=2 (404LP)
Option 3=0
Option 4=0

CKI is oscillator input (divide
by 32)

---

RESET pin has load device to
Vee

Option 5 = 2

Option 21 = 0
Option 22 = 0

GO]
G1 have very high current

Option 23=0

G2 standard output

Option 24=0

G3

Option 25 =0

0,]

Option 26 = 0

O2 have very high current
0 1 standard output
O2

Option 6=2

L, ] have LED direct-drive
L6

Option 27 = 0

Option 7=2

L5

Option 28 =0

Option 8=2

Option 29 = 0

Option 9 =0

L4
IN1 has load device to Vee

Option 10=0

IN2 has load device to Vec

Option 31 = 0

G

Option 11 = 1

Vee 4_5 to 9_5V operation

Option 32 = 0

SI

output

Option 12=2

Option 30 =0

~N ] h'" ","d",d '"PO'
levels

Option 33= 0

RESET has Schmitt trigger input

L2 have LED direct-drive
L1 output

Option 34 =0
Option 35 = N/A

CKO has standard input levels
40-pi n package

Option 16 = 0

Lo
SI.has load to Vee

Option 36 = 0 (404LS)
= 1 (404LP)

RESET pin used normally
Power-Low failsafe enabled

Option 17 = 2

SO has push-pull output

Option 13 = 2
Option 14 = 2
Option 15=2

L, ]

1-39

.
~ Semiconductor
~National

COP410L/COP411L Single-Chip
N·Channel Microcontrollers
General Description

Features

The COP410L and COP411L Single-Chip N-Channel
Microcontrollers are members of the COPSTM family,
fabricated using N-channel, silicon gate MOS
technology_ These Controller Oriented Processors
are complete microcomputers containing all system
timing, internal logic, ROM, RAM and 110 necessary
to implement dedicated control functions in a variety
of applications_ Features include single supply
operation, a variety of output configuration options,
with an instruction set, internal architecture and 110
scheme designed to facilitate keyboard input,
display output and BCD data manipulation. The
COP411 L is identical to theCOP410L, but with 16110
lines instead of 19. They are an appropriate choice
for use in numerous human interface control environments. Standard test procedures and reliable highdensity fabrication techniques provide the medium
to large volume customers with a customized
Controller Oriented Processor at a low end-product
cost.

Low cost
Powerful instruction set
II 512x8 ROM, 32x4 RAM
II 19110 lines (COP410L)
II Two-level subroutine stack
II 16;

~

c

-10

-700
~

t\.

I

-600

"'1"-1'\

IMAX @Vee-9.5V

~ -500

"'

IMAX@
-400 ",ee = 45~
~
...... IMIN @
-300
"
Vee = .5V
-200

I MAX}
Vee=4.5V
~

IMIN@Vee- 9.5V

mNrer~5V

o
o

9.5

ANI d #2

-000

I\..

-40

-20

1.0 2.0 3.0 4.0 5.0 6.0 7.00.0

"-

-50

DEVICE a #2

-900

!"...IMAX@Vee=9.0v

-60

-30

Source Current for Standard
Output Configuration

I 1'\
1~ ~ I/~~~ = 9.5V",
o - - J. ~f-+-(

t-...

-100

I'=: ~

1.0

2.0

Vall (VOLTS)

Source Current for LO through
L7 in TRI·STATE'"
Configuration (High Current
Option)

Source Current for SO and SK in
Push-Pull Configuration

"

0123456709.5

V liD

V IN (VOLTS)

Source Current for LO through
L7 in TRI·STATE"
Configuration (Low Current
Option)

-15

;<
.5

'"c
-5

H--\t"""""*

3

-10

-5

4

5

6

V OH (VOLTS)

7

0

9

10

1

2

3

4

5

6

7

0

9 '10

vOH (VOLTS)

Figure 8. I/O DC Current Characteristics

1-49

o

1

2

3

4

5

6

VOH (VOLTS)

7

0

9

10

o"tJ
~
......
o

C

(')

o"tJ
~
......
......

r-

...J
~

~

~

a..

LED Output Direct Segment
and Digit Drive
High Current Options on
LO-L7
Very High Current Options on
00-03

0
0

::J

LED Output Source Current
(lor High Current LED Option)

0

LED Output Source Current
(lor Low Current LED Option)

~

-5 0

a..

-40

OEVICE f #2 ANO #4

~

A~O DEVIICE a OR b #1

0
0

IMAX
ONE SEGMENTS
~

~

.§

.§

"

0

"

0

V

-2 0

V
........V
~AXEIGHT
..... ....... , .... iMIN SEGMENTS ON
~
1
::::" .......

-1 0

o

1

2

3

4

5

6

7

8

9

0

10

4.

VOH (VOLTS)

:1- ~-:
f l >-

DEVICE f
#2 AND #4
15

~

-3D

IMAX HIGH CURRENT

f--- t- OPTION

"

E

i/t :lw

-20

•
•••• /

-10

.'

.... •

..

l~

CURRENT

~

flV

o

./r~IN HIGH

•

CUR~ENT O~TION

r-~MIN

LOW
eu'iiRENT OPTION

~~!:.~:::::

o
10

I

I

I

.'
.....

.1

1

2

......

~EVICE

a #1
ANID b #1 AND c #1

'rrTI

V

IMIN @Vce =

V

3

4

5

6

7

8

9

1

10

r-,-,-.,-,--,-..,""""""-"-"""""
DEVICE a #1

1--!--1o--+-t-I-+-+-+--+--I

~

1---+1-++--+---"",1--1--+-+-+-1

.. ' .........',.-

. . .V

200

E

100

o

o~~~~~~~~--~~~

o

2

3

4

5

6

7

8

4

DEVICE a #1
ANDb#1
I
I
I
IMAX @Vce = 9.5 V

300
~

200

3

I .J

400

~

E

2

Output Sink Current lor
DO - 03 (lor High Current
Option)

ANO b#1

~

I--'l--t--t

10

V
-t,L ~-

,tV

o

1

2

VDL (VOLTS)

IMAX @VCC = .5
IMIN@VCC=9.5V
IMIN@VCC=4.5V

3

4

5

6

VOL (VOLTS)

Figure 8. I/O DC Current Characteristics

1-50

5

6

VOL (VOLTS)

Output Sink Current for 00·03
with·Very High Current Option

300

10

~

o

VOL (VOLTS)

Vec (VOLTS)

400

~

.§

~V 11114.~
o

I

IMAX @.~.~~.~~(~.Y

I

10

.§

OPTION

..... I

Output Sink Current lor LO·L7
and Standard Drive Option lor
00·03 and GO·G3

IMAX @VCC = 9.5 V

:

-40

.§

VCC (VOLTS)

Output Sink Current lor SO
and SK
20

VOH = 2.0 V

10

VOH (VOLTS)

LED Output Direct Segment Drive
-50

I-

L

-3 0

7

8

9

10

7

8

9

10

COP410Ll411L INSTRUCTION SET

Table 3 provides the mnemonic, operand, machine code,
data flow, skip conditions and description associated
with each instruction in the COP410Ll411L instruction
set.

Table 2 is a symbol table providing internal architecture,
instruction operand and operational symbols used in
the instruction set table.

o
o
"tJ
~
~

o

r:
o
o"tJ
~
~

Table 2. COP410U411L Instruction Set Table Symbols

~

Symbol

Definition

Symbol

INTERNAL ARCHITECTURE SYMBOLS
A
4·blt Accumulator
B
B·bit RAM Address Register
Br
Upper 2 bits of B (register address)
Bd
Lower 4 bits of B (digit address)
C
1·bit Carry Register

r-

Definition

INSTRUCTION OPERAND SYMBOLS
d
4·bit Operand Field, 0- 15 binary (RAM Digit Select)
r
2·bit Operand Field, 0-3 binary (RAM Register
Select)
a
y
RAM(s)
ROM(t)

D

4·bit Data Output Port

EN
G

4·bit Enable Register

L

B·bit TRI·STATE 110 Port

M

4·bit contents of RAM Memory pointed to by B

9·bit Operand Field, 0-511 binary (ROM Address)
4·bit Operand Field, 0- 15 binary (Immediate Data)
Contents 01 RAM location addressed by s
Contents of ROM location addressed by t

4·bit Register to latch data lor G 110 Port
OPERATIONAL SYMBOLS

PC

9·bit ROM Address Register (program counter)

Q

a·bit Register to latch data for L 1(0 Port

SA

9·bit Subroutine Save Register A

SB
SIO
SK

9·blt Subroutine Save Register B
4·bit Shift Register and Counter
Logic·Controlied Clock Output

Plus

+
-

Register

Minus

-=

Is exchanged with

A

The one's complement of A

Replaces
Is equal to

Exclusive-OR

ID

Range of val ues

Table 3. COP410LI411L Instruction Set

Mnemonic

Operand

Hex
Code

Machine
Language Code
(Binary)

Data Flow

Description

Skip Conditions

ARITHMETIC INSTRUCTIONS
ASC

30

10011100001

A + C + RAM(B) - A
Carry - C

ADD

31

10011100011

A

5-

10 1 011

I

A

CLRA

00

\0

a a 010 a a 01

COMP

40

10 1 00100001

AISC

Y

y

Carry

Add with Carry, Skip on
Carry

+ RAM (B) - A

None

Add RAM to A

+ Y- A

Carry

Add Immediate, Skip on
Carry (y " 0)

0- A

None

Clear A

A-A

None

One's complement of A to
A

NOP

44

10100101001

None

None

No Operation

RC

32

10 0 1 110 0 1 01

"0" - C

None

Reset C

SC

22

100 1 0100 1 01

"1"-C

None

Set C

XOR

02

10000100 1 01

A .. RAM(B)- A

None

Exclusive·OR RAM with A

1-51

,....
,....

..J

Table 3. COP410U411L Instruction Set (continued)

-.:::r

Q.

oo

::.
o
,....

Mnemonic Operand

Hex
Code

Machine
Language Code
(Binary)

Q.

Skip Conditions

Description

TRANSFER OF CONTROL INSTRUCTIONS
JID

FF

11111111111

ROM (PCS,A,M)PC7:0

None

Jump Indirect (Note 2)

-.:::r

o

Data Flow

JMP

a

o

JP

a

1011o l000iasi
a7:0
I

a - PC

None

Jump

--

6-

I

--

III

I

a - PC6:0

None

Jump within Page
(Note 3)

--

a5:0
1111
(all other pages)

I

a - PC5:0

--

110 1

I

PC + 1 - SA - SB

None

Jump to Subroutine Page
(Note 4)

PC + 1 - SA - SB
a- PC

None

Jump to Subroutine

a6:0
(pages 2,3 only)
or

JSRP

a

a5:0

010 - PCS:6
a - PC5:0
6--

101101100lasi

RET

4S

10100110001

SB - SA - PC

None

Return lrom Subroutine

RETSK

49

10100110011

SB - SA - PC

AI,ways Skip on Return

Return from Subroutine
then Skip

JSR

a

I

J

a7:0

MEMORY REFERENCE INSTRUCTIONS
CAMO

LD

r

LaiD

33
3C

1001 1100111
1001 1111001

A - 07:4
RAM(B) - 03:0

None

Copy A, RAM to 0

-5

1001 r 101011

RAM(B)- A
Br" r - Br

None

Load RAM into A,
Exclusive·OR Br with r

BF

1101 111 1 1 11

ROM(PCS,A,M) - 0
SA- SB

None

Load 0 Indirect (Note 2)

RMB

0
1
2
3

4C
45
42
43

10100111001
10 1 0 010 1 0 11
10 1 00100 1 01
101001001 11

0000-

RAM(B)O
RAM(BI1
RAM(B)2
RAM(B)3

None

Reset RAM Bit

5MB

0
1
2
3

4D
47
46
4B

1010011 1011
101001011 11
10100101101
10100110111

1111-

RAM(B)O
RAM(B)1
RAM(B)2
RAM(B)3

None

Set RAM Bit

STII

Y

7-

101 111

I

y - RAM(B)
Bd + 1 - Bd

None

Store Memory Immediate
and Increment Bd

X

r

-6

1001 r 101101

RAM(B)- A
Br" r - Br

None

Exchange RAM with A,
Exclusive·OR Br with r

XAD

3,15

RAM(3,15) -

None

Exchange A with RAM
(3,15)

y

23

100 1 0100 1 11

BF

1101 111 11 11

A

XDS

r

-7

1001 r 101 111

RAM(B)- A
Bd - 1 - Bd
Br" r - Br

Bd decrements past 0

Exchange RAM with A
and Decrement Bd,
Exclusive·OR Br with r

XIS

r

-4

100Ir 101001

RAM(B)- A
Bd + 1 - Bd
Br" r - Br

Bd increments past 15

Exchange RAM with A
and Increment Bd,
Exclusive·OR Sr with r

1-52

o

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Table 3. COP410U411L Instruction Set (continued)

Mnemonic Operand

Hex
Code

~

Machine
Language Code
(Binary)

-'"

Oata Flow

Skip Conditions

Description

o

CAB

50

10 1 0 110 0 0 01

A- Bd

None

Copy A to Bd

CBA

4E

10 1 0011 1 1 01

Bd - A

None

Copy Bdto A

10 0 r (d - 1)
(d = 0.9:15)

r.d - B

Skip until not a LBI

Load B Immediate with
r.d (Note 5)

y - EN

None

Load EN Immediate
(Note 6)

I I

I

LBI

r.d

--

LEI

y

33
6-

101 1 01

SKC

20

10 0 1 010 0 0 01

C

= "1"

Skip if C is True

SKE

21

10 0 1 010 0

a 11

A

= RAM(B)

Skip if A Equals RAM

SKGZ

33

10

21

10 0 1 010 0 0 11

10 01 110 0 1 11
y

I

TEST INSTRUCTIONS

SKGBZ

SKMBZ

a 1 110 0 1 11

33

10 0 1 110 0 1 11

0
1

01
11

10 0 0 010 0 0 11
10 0 0 110 0 0 11

G3:0

=0

Skip if G is Zero
(all 4 bits)

1st byte

Skip if G Bit is Zero
GO
G1

I,"' ""

=0
=0
=0
=0

2

03

10 0 0 010 0 1 11

3

13

1000 1100 1 11

0

01

10 0 0 010 0 0 11

RAM(B)O

1
2

11
03

1000 11000 11
10 0 0 010 0 1 11

RAM(Bl1
RAM(B)2

3

13

10 0 0 110 0 1 11

RAM(B)3

G2
G3

=0
=0
=0
=0

Skip if RAM Bit is Zero

INPUT/OUTPUT INSTRUCTIONS
ING

INL

OBD

OMG

XAS

o

C

REGISTER REFERENCE INSTRUCTIONS

33

10 0 1 110 0 1 11

2A

100 1 011 0 1 01

G-A

None

Input G Ports to A

33

10 0 1 110 0 1 11

Input L Ports to RAM. A

100 1 011 1 1 01

L7:4 - RAM(B)
L3:0 - A

None

2E
33

1001 1100111

Bd - D

None

Output Bd to D Outputs

3E

10011111101

33
3A

10011100111

RAM(B)- G

None

Output RAM to G Ports

4F

101 0011 1 1 11

A-

None

Exchange A with SIO
(Note 2)

10011110101
SIO. C - SKL

Nota 1: All subscripts for alphabetical symbols indicate bit numbers unless explicitly defined (e.g .. Br and Bd are explicitly defined). Bits are

numbered 0 to N where 0 signifies the least significant bit (low-order, right-most bit). For example, A3 indicates the most significant (lett-most)
bit of the 4-bit A register.
Note 2: For additional information on the operation of the XAS, JID. and LOID instructions, see below.
Note 3: The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two-page boundary of pages 2 or 3.
The JP instruction, otherwise, permits a jump to a ROM location within the current 54·word page. JP may not jump to the last word of a page.
Note 4: A JSRP transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of Pl. A JSRP may not be used when in pages
2 or 3. JSRP may not jump to the last word in page 2.
Note 5: The machine code for the lower 4 bits of the LSI instruction equals the binary value of the "d" data minus 1, e.g~, to load the lower four

bits of B IBd) with the value 9 (10012). the lower 4 bits of the LBI instruction equal 8 (10002)' To load O. the lower 4 bits of the LBI instruction
should equal 15 11"'2).
Note 6: Machine code for operand field y for LEI instruction should equal the binary value to be latched into EN, where a "1" or "0" in each bit of

EN corresponds with the selection or deselection of a particular function associated with each bit. (See Functional Description, EN Register.)

1-53

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The following information is provided to assist the user
in understanding the operation of several unique
instructions and to provide notes useful to programmers in writing COP410U411L programs_

OPTION LIST

XAS Instruction

The following is a list of COP410L options. When
specifying a COP411L chip, Option 2 must be set to
3, Options 20, 21, and 22 to O. The options are
programmed at the same time as the ROM pattern to
provide the user with the hardware flexibility to
interface to various I/O components using little or no
external circuitry.

The COP41 OU411 L mask-programmable options are
assigned numbers which correspond with the
COP410L pins.

XAS· (Exchange A with SIO) exchanges the 4-bit
contents of the accumulator with the 4-bit contents of
the SIO register. The contents of SIO will contain serialin/serial-out shift register or binary counter data,
depending on the value of the EN register. An XAS
instruction will also affect the SK output. (See
Functional Description, EN Register, above_) If SIO is
selected as a shift register, an XAS instruction must be
performed once every 4 instruction cycles to effect a
continuous data stream.

Option 1 = 0: Ground Pin -

no options available

Option 2: CKO Output (no option available for
COP411L)
= 0: clock output to ceramic resonator
= 1: pin is RAM power supply (V R) input
= 2: multi-COP SYNC input
= 3: No Connection

JID Instruction
JID (Jump Indirect) is an indirect addressing instruction,
transferring program control to a new ROM location
pointed to indirectly by A and M. It loads the lower a bits
of the ROM address register PC with the contents of
ROM addressed by the 9-bit word, PCa, A, M_ PCa is not
affected by this instruction.

Option 3: CKI Input
= 0: oscillator input divided by 8 (500 kHz max)
= 1: single-pin RC controlled oscillator divided
by 4
Option 4: RESET Input
= 0: load device to Vee
=1: Hi-Zinput

Note that JID requires 2 instruction cycles.
LaID Instruction
LQID (Load Q Indirect) loads the a-bit Q register with the
contents of ROM pointed to by the 9-bit word PCa, A, M.
LQID can be used for table lookup or code conversion
such as BCD to seven-segment. The LQID instruction
"pushes" the stack (PC + 1 -SA -SB) and replaces the
least significant a bits of PC as follows: A -PC 7:4,
RAM(B) -PC3:0 , leaving PCa unchanged. The ROM data
pOinted to by the new address is fetched and loaded
into the Q latches. Next, the stack is "popped" (SB -SA
- PC), restoring the saved value of PC to continue
sequential program execution. Since LQID pushes SASB, the previous contents of SB are lost. Also, when
LQID pops the stack, the previously pushed contents of
SA are left in SB. The net result is that the contents of
SA are placed in SB (SA -SB). Note that LQID takes two
instruction cycle times to execute.

Option
= 0:
= 1:
= 2:

5: L7 Driver
Standard output
Open-drain output
High current LED direct segment drive
output
= 3: High current TRI'STATE® push-pull output
= 4: Low-current LED direct segment drive
output
= 5: Low-current TRI-STATE® push-pull output

Option 6: L6 Driver
same as Option 5
Option 7: L5 Driver
same as Option 5
Option 8: L4 Driver
same as Option 5

Instruction Set Notes

Option 9: Vee Pin
=0: 4_5V to 6.3Voperation
= 1: 4.5\1 to 9.5V operation

a_ The first word of a COP410U411L program (ROM
address 0) must be a CLRA (Clear A) instruction.
b. Although skipped instruCtions are not executed, one
instruction cycle time is devoted to skipping each
byte of the skipped instruction. Thus all program
paths take the. same number of cycle times whether
instructions are skipped or executed.

Option 10: L3 Driver
same as Option 5
Option 11: L2 Driver
same as Option 5

c. The ROM is organized into a pages of 64 words each.
The Program Counter is a 9-bit binary counter, and
will count through page boundaries. If a JP, JSRP,
JID or LQID instruction is located in the last word of
a page, the instruction operates as if it were in the
next page. For example: a JP located in the last word
of a page will jump to a location in the next page.
Also, a LQID or JID located in the last word of page 3
or 7 will access data in the next group of 4 pages.

Option 12: L, Driver
same as Option 5
Option 13: Lo Driver
same as Option 5
Option 14: SI Input
= 0: load device to Vee
=1: HI-Zinput

1-54

(')
Option
= 0:
= 1:
= 2:

15: SO Driver
standard output
open-drain output
push-pull output

Option 22: D2 Output (no option available for
COP411L)
same as Option 21
Option 23: D1 Output
same as Option 21

Option 16: SK Driver
same as Option 15

Option 24: Do Output
same as Option 21

Option 17: Go 1/0 Port
= 0: standard o,utput
= 1: open-drain output

Option 25: L Input Levels
= 0: standard TIL input levels
("O"=O_BV, "1"=2_0V)
= 1: higher voltage input levels
("0" = 1.2V, "1" = 3.6 V)

Option 1B: G1 1/0 Port
same as Option 17
Option 19: G2 1/0 Port
same as Option 17

Option 26: G Input Levels
same as Option 25

Option 20: G3 1/0 Port (no option available for
COP411L)
same as Option 17

Option 27: SI Input Levels
same as Option 25
Option 2B: COP Bonding
= 0: COP410L (24-pin device)
= 1: COP411 L (20-pin device)

Option 21: D3 Output (no option available for
COP411L)
= 0: very-high sink current standard output
= 1: very-high sink current open-drain output
= 2: high sink current standard output
= 3: high sink current open-drain output
= 4: standard LSTTL output (fanout = 1)
= 5: open-drain LSTTL output (fanout = 1)

1-55

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COP420/COP421 AND COP320/321
~ Single·Chip N·Channel Microcontrollers
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General Description

Features

The COP420, COP421, COP320, COP321 Single-Chip
N-Channel Microcontrollers' are members of the
COPSTM family, fabricated using N-channel, silicon
gate MOS technology. They are complete microcomputers containing all system timing, internal logic,
ROM, RAM and I/O necessary to implement dedicated
control functions in a variety of applications.
Features include single supply operation, a variety of
output configuration options, with an instruction set,
internal architecture and I/O scheme designed to
facilitate keyboard input, display output and BCD
data manipulation. The COP421 is identical to the
COP420, except with 19 I/O lines instead of 23. They
are an appropriate choice for use in numerous
human interface control environments. Standard test
procedures and reliable high-density fabrication
techniques provide the medium to large volume
customers with a customized Controller Oriented
Processor at a low end-product cost.

•
•
•
•
•
•
•
•
•

Low cost
Powerful instruction set
1kx8 ROM, 64x4 RAM
23 I/O lines (COP420, COP320)
True vectored interrupt, plus restart
Three-level subroutine stack
4.0 I's instruction time
Single supply operation
Internal time-base counter for real-time
processing
Internal binary counter register with
MICROWIRETM compatible serial I/O
General purpose and TRI-STATE® outputs
TTL/CMOS compatible in and out
LED direct drive outputs
MICROBUSTM compatible
Software/hardware compatible with other
members of COP400 family
Extended temperature range device COP320/
COP321 (-40°C to +85°C)

•
•
•
•
•
•

The COP320 is the extended temperature range
version of the COP420 (likewise the COP321 is the
extended temperature range version of the COP421).
The COP320/321 are exact functional equivalents of
the COP420/421.

•

OND

~,
TIME-BASE

COUNTER

(DIVIDE BY 1024)

DJ
DJ

D,
DD

1----\-""'-+ SK
GJ

G,
G,

110 CONTROLS

COP420lCOP3200NLY

-,

'-_-'!T"-r--

Go

'-------~t-"-+-"

5

6

7

8

12

13

14

15

ZD 10 9
19
11'43 INZ INt INO '

Figure 1. COP420/COP421, COP320/COP321 Block Diagram

1-56

o

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COP420/COP421
Absolute Maximum Ratings
Voltage at Any Pin Relative to GND
Ambient Operating Temperature
Ambient Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Power Dissipation

DC Electrical Characteristics

-0.5Vto +7V
O'Cto + 70'C
- 65'C to + 150'C
300'C
0.75 Watt at 25 'C
0.4 Watt at 70 'C
O'C'; TA

Parameter

.;

Conditions

Min

Max

4.5

6.3

V

30

rnA

Note 3 (all outputs open)

2.0

Units

0.4

V
V

2.0
-0.3

0.8

V
V

0.7 Vee
-0.3

0.6

V
V

0.7 Vee
-0.3

0.6

V
V

Vee=5V±5%

Schmitt Trigger Input (+4)
Logic High (V IH )
Logic Low (VILl
RESET Input Levels
Logic High
Logic Low
RESET Hysteresis

1.0

SO Input Level (Test mode)

2.0
Vee=max
Vee=5V±5%

Input Levels High Trip Option
Logic High
Logic Low
HI Z Input Leakage

V
3.0

V

3.0
2.0
-0.3

0.8

V
V
V

3.6
-0.3

1.2

V
V

7

pF

-1

+1

I'A

2.4
-0.3

0.4

V
V

Vee- 1
-0.3

0.2

V
V

Input Capacitance

Output Voltage Levels
Standard Output
TTL Operation
Logic High (VOH )
Logic Low (VOL)
CMOS Operation
Logic High (Vo H)
Logic Low (VoLl

Vee=5V±5%
IOH = - 1OOI'A
10l= 1.6mA
IOH= - 1OI'A
IOl= 1O I'A

Output Current Levels
LED Direct Drive Output
Logic High (I0H)

Vee=6V
VO H =2.0V

TRI-STATE'" Output
Leakage Current

2.5

14

rnA

-10

+10

I'A

3

rnA

CKO Output
VR Power Saving Option
Power Requirements

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CKI Input Levels
Crystal Input
Logic High (V IH )
Logic Low (VILl

All Other Inputs
Logic High
Logic High
Logic Low

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~

Input Voltage Levels

TTL Input
Logic High (V IH)
Logic Low (VILl

~
S2
N

+ 70'C, 4.5V'; Vee'; 6.3V unless otherwise noted.

Operating Voltage (Vecl
Operating Supply Current

Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and
AC electrical specifications are not ensured when
operating the device at absolute maximum
ratings.

VR =3.3V

1-57

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~

COP420/COP421

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AC Electrical Characteristics o·c" TA ", + 70·C, 4.5V"

0..

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,...

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Parameter
Instruction Cycle Time - te
CKI Using Crystal (figure 8a)
Input Frequency - fl
Duty Cycle (Note 1)
CKI Using External Clock (figure 8b)
Input Frequency
Duty Cycle (Note 1)
Rise Time
Fall Time

o

~

0..

o

o

CKI Using RC (figure 8c)
Frequency
Instruction Cycle Time
CKO as SYNC Input (figure 8d)
t SYNO

Vee'" 6.3V unless otherwise stated.

Conditions

Units

Min

Max

4

10

f'S

... 16 mode
... 8 mode
figure 3a

1.6
0.8
30

4
2
55

MHz
MHz
%

... 16 mode
... 8 mode

1.6
0.8
30

4
2
60
60
40

MHz
MHz
%
ns
ns

0.5
4

1.0
8

MHz
f'S

figure 3

fl=4MHz
FI=4MHz
... 4 mode
R=15k±5%, C=100pF±10%

figure 3a

50

ns

1.7
300

gS
ns

0.3
250

f'S
ns

INPUTS: (figure 3)
INa·IN o, Ga,G o, L7'LO' CKO as Input
t SETUP
t HOLO
SI
t SETuP
t HOLO
OUTPUTS:
COP TO CMOS PROPOGATION
DELAY

4.5V'" Vee" 6.3V, CL = 50pF,
VoH =0.7Vee , VOL = 0.3 Vee

SK as a Logic,Controlied Clock
t p01
t poo

1.1
0.3

f'S
f'S

SO, SK as a Data Output
tp01
t poo
tp01

1.4
0.3
0.7

f'S
f'S
f'S

Da,Do, Ga,G o
tp01
tpoo

1.6
0.6

f'S
f'S

L7'Lo (Standard)
tp01
tpoo

1.4
0.3

f'S
f'S

2.4
0.4

f'.s
f'S

L7'Lo (LED Direct Drive)
tp01
tpoo

VOH =2V

VOH =2V

H8

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COP420/COP421
AC Electrical Characteristics o·c" TA" + 70·C, 4.5V"
Parameter

Vee" 6.3V unless otherwise stated.

Conditions

Min

Max

Units

fanout = 1 Standard TTL Load
Vee=5V±5%, C L =50pF
VOH = 2.4V, VOL = O.4V

~

-o
N

~

SK as a Logic-Controlled Clock
tp01
tpoo

0.8
0.8

SK as a Data Output, SO
T p01
T poo

1.0
1.0

f'S
f'S

D3·Do, G3-G O
tp01
tpoo

1.3
1.3

f's
f's

LrLo
tp01
tpoo

1.4
0.4

f'S
f'S

L 7 -Lo (Push-Pull)
tp01
tpoo

0.4
0.3

f'S
f'S

CKO (figure 3b)
tp01
tpoo

0.2
0.2

f's
f's

300
200

ns
ns
ns
ns
ns

700

ns
ns
ns
ns
ns
ns

MICROBUSTM TIMING

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OUTPUTS (cont.):
COP TO TTL PROPOGATION
DELAY

~
52

f's
f'S

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(,.)

N

52

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~
~

CL =50pF, Vee=5V±5%

A. Read Operation (figure 4)
Chip Select Stable Before RD - tesR
Chip Select Hold Time for RD - t Res
RD Pulse Width - tRR
Data Delay from RD - t RO
RD to Data Floating - tOF

50
5
400

Write Operation (figure 5)
Chip Select Stable Before WR - tesw
Chip Select Hold Time for WR - twes
WR Pulse Width - tww
Data Set-Up Time for WR - tow
Data Hold Time for WR - two
INTR Transition Time from WR - tWI

50
30
350
300
40

Note 1: Duty Cycle = tW1/(tWI + two).
Note 2: See figure 9 for additional 110 Cnaracteristics
Note 3: Vee voltage change must be less than O.5V/ms to maintain proper operation.

1-59

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COP320/COP321
Absolute Maximum Ratings
Voltage at Any Pin Relative to GND
Operating Temperature
Ambient Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Power Dissipation
Am~ient

DC Electrical Characteristics
Parameter

- 0.5V to + 7V
-40°C to + 85°C
- 65 °C to + 150°C
300°C
0.75 Watt at 25°C
0.25 Watt at 85 °C

Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and
AC electrical specifications are not ensured when
operating the device at absolute maximum
ratings.

-40°C .. TA .. +85°C, 4.5V .. Vee" 5.5V unless otherwise noted.
Conditions

Operating Voltage (Veel

Note 4

Operating Supply Current

(all outputs open)

Min

Max

4.5

5.5

V

40

mA

0.3

V
V

0.6

V
V

. 0.4

V
V

0.4

V
V

Units

Input Voltage Levels
CKI Input Levels
Crystal Input
Logic High (VIH )
Logic Low (Vld

2.2

TTL Input
Logic High (VIH)
Logic Low (Vld

2.2
-0.3

. Schmitt Trigger Input (+4)
Logic High (V IH )
Logic Low (Vld

0.7 Vee

RESET Input Levels
Logic High
Logic Low

0.7 Vee
-0.3

RESET Hysteresis

0.5

SO Input Level (Test mode)

2.2

3.0

V

All Other Inputs
Logic High
Logic Low

2.2
-0.3

0.6

V
V

3.6
-0.3

1.2

V
V

7

pF

-1

+1

"A

2.4
-0.3

0.4

V
V

Vee- 1
-0.3

0.2

V
V

Input Levels High Trip Option
Logic High
Logic Low
Input Capacitance
Hi Z Input Leakage

V

Output Voltage Levels
Standard Output
TTL Operation
Logic High (VOH )
Logic Low (VOL)
CMOS Operation
Logic High (VOH)
Logic Low (VOL)

Vee=5V±5%
10H= -75"A
IOL = 1.6mA
IOH= -10"A
IOL=10"A

Output Current Levels
LED Direct Drive Output
Logic High (I OH )

Vee = 5V (Note 1)
VOH =2.0V

TRI·STATE@ Output
Leakage Current

1.0

12

-10

+10

CKO Output
VR Power Saving Option
Power Requirements

VR = 3.3V to 5.5V

1-60

4

mA

o

COP320/COP321
AC Electrical Characteristics
Parameter
Instruction Cycle Time - tc
CKI Using Crystal (figure 8a)
Input Frequency - fl
Duty Cycle (Note 2)
CKI Using External Clock (figure 8b)
Input Frequency
Duty Cycle (Note 2)
Rise Time
Fall Time
CKI Using RC (figure 8c)
Frequency
Instruction Cycle Time
CKO as SYNC Input (figure 8d)
t SYNO

-40 'c .. T

A" + 85 'C, 4.5V .. Vee" 5.5V unless otherwise stated.

Conditions

Min

Max

4

10

IlS

... 16 mode
... 8 mode
figure 3a

1.6
0.8
40

4
2
55

MHz
MHz
%

... 16 mode
... 8 mode

1.6
0.8
40

4
2
60
60
40

MHz
MHz
%
ns
ns

1.0
8

MHz
Ils

figure 3

f l =4MHz
FI=4MHz
... 4 mode
R=15k±5%, C=100pF±10%

figure 3a

0.5
4

Units

50

ns

tSETUP
t HOLD

1.7
300

Ils
ns

tSETUP
t HOLD

0.3
250

IlS
ns

INPUTS: (figure 3)
IN 3·IN o, G3·GO, L7·Lo, CKO as Input

SI

OUTPUTS:
COP TO CMOS PROPOGATION
DELAY

C L =50pF,
VoH =0.7Vee , VOL = 0.3 Vee

SK as a Logie·Controlied Clock
. tpD1
t pDO

1.3
0.4

Ils
Ils

SO, SK as a Data Output
t pD1
t pDO
t pD1

1.6
0.4
0.75

IlS
IlS
IlS

D3·Do, G3·GO
t pD1
t pDO

2.0
1.0

IlS
IlS

LTLo (Standard)
tpD1
t pDO

2.0
1.0

Ils
Ils

3.0
1.0

IlS
IlS

LTLO (LED Direct Drive)
tpDl
t pDO

VoH =2V

VoH =2V

1·61

o
"'0

~
'2

o

o"'0

~
...A.

-

o

o"'0

~
'2

o

o"'0
~
...A.

,...

~

COP320/COP321

o()

AC Electrical Characteristics

c..

(9

Parameter

SK as a Logie,Controlled Clock
tpOl
tpoo

1.0
1.0

1'5

SK as a Data Output, SO
TpOl
Tpoo

1.2
1.2

1'5

D3 -Da, G3 -G O
tpOl
t poo

1_5
1.5

1'5

LrLo
t pOl
tpoo

1.6
0.5

1'5

L7-Lo (Push-Pull)
tpOl
tpoo

0.5
0.5

1'5

CKO (figure 3b)
tpOl
tpoo

0.25
0.25

1'5

o

COP TO TIL PROPOGATIGlN
DELAY

,...

~

c..

o
()
(9

~

c..

o()

Min

Units

OUTPUTS (cont.):

()

Conditions

Max

~

c..

-40·C'; TA'; + 85 ·C, 4.5V'; Vee'; 5.5V unless otherwise stated.

MICROBUSTM TIMING

fanout = 1 Standard TTL Load
Vee=5V±5%, CL =50pF
VOH = 2.4V, VOL = O.4V

1'5

1'5

1'5

1'5

!JS

1'5

CL =50pF, Vee=5V±5%

A. Read Operation (figure 4)
Chip Select Stable Before RD - tesR
Chip Select Hold Time for RD - t Res
RD Pulse Width- tRR
Data Delay from RD - tRO
RD to Data Floating - tOF

10
400

Write Operation (figure 5) .
Chip Select Stable Before WR - tesw
Chip Select Hold Time for WR - twes
WR Pulse Width - tww
Data Set-Up Time for WR - tow
Data Hold Time for WR - two
INTR Transition Time from WR - tWI

100
50
400
350
50

350
250

ns
ns
ns
ns
ns

800

n5
ns
ns
ns
n5
ns

60

Note 1: Exercise great care not to exceed maximum device power dissipation limits when direct·driving LEOs (or sourcing similiar
loads) at high temperature.
Note 2: Duty Cycle = tWI/(tWI + two).
Note 3: See figure 9 for additional 1/0 Characteristics.
Note 4: Vee voltage change must be less than O.5V/ms.

1-62

o

GNO
CKO
CKI

28

Ii£ID
L7
L6
L5
L4
INI
IN2
VCC
L3
L2
Ll

11
12
13
14

17
16
15

DO
01
02
03
G3
G2
Gl
GO
IN3
INO
SK
SO
SI
LO

GNO
CKO
CKI

24
23
22
21
20
19
18
17
16
15
14
13

Rffi"f
L7
L6
L5
L4
VCC
L3
L2

10
11
12

L1

eOP420, eOP320

DO
01
02
03
G3
G2
Gl
GO
SK
SO
SI
LO

o."
t
S2
o
o
."

t
.....

-oo

."

eOP421, eOP321

~
S2

Figure 2. Connection Diagrams

o

Pin

Description

L7 -Yl

Pin

8 bidirectional 1/0 ports with
TRI-STATEI!l

Description

CKI

System oscillator input

CKO

System os.cillator output (or general·
purpose input or RAM power supply)
System reset input

G3 -G O

4 bidirectional 1/0 ports

0 3 -00

4 general purpose outputs

RESET

IN3-INo

4 general purpose inputs (COP420/320
only)

Vcc

Power supply

GNO

Ground

SI

Serial input (or counter input)

SO

Serial output (or general purpose output)

SK

Logic-controlled clock (or general
purpose output)

Figura 3. Input/Output Timing Diagrams (crystal divide by 16 mod~)

CKI

~\ ~twl
CKO
(INPUT)

1

CKI

-.lLJLJ .

--h ·1n\1 /T

!-ISVNCO

"P01-!

Figure 3A. Synchronization Timing

~ ~1pOO

Figure 3B. eKO Output Timing

1-63

o
."
CAl

N
.....

..~

Q.

oo

(lN21

.1

ell

• --tRcs~1

tRR

C5
~

IL7-LOI

07-00

Q.

o
~
..-

Figure 4. MICROBUS™ Read Operation Timing

tcsw __ •
(lN21

.~

CS

J
~IOW-

Q.

oo

C5
~

IL7-LOI

07-00

IGol

INTR

Q.

oo

.--twes-1.

tww

\.

.

twl

--- two.lJ..

.t______

Figure 5. MIC ROBUS™ Write Operation Timing

FUNCTIONAL DESCRIPTION COP420/COP421/COP320/COP321
For ease of reading this description, only COP420
and/or COP421 are referenced; however, all such
references apply equally to COP320 and/or COP321,
respectively.
.

of 16 4-bit digits in the selected data register. While the
4-bit contents of the selected RAM digit (M) is usually
loaded into or from, or exchanged with, the A register
(accumulator), it may also be loaded into or from the Q
latches or loaded from the L ports. RAM addressing
may also be performed directly by the LDD and XAD
instructions based upon the 6-bit contents of the
operand field of these instructions. The Bd register also
serves as a source register for 4-blt data sent directly to
the D outputs.

A block diagram of the COP420 is given in figure 1. Data
paths are illustrated in simplified form to depict how the
various logic elements communicate with each other in
implementing the instruction set of the device. Positive
logic is used. When a bit is set, it is a logic "1" (greater
than 2 volts). When a bit is reset, it is a logic "0" (less
than 0.8 volts).

Internal Logic

Program Memory

The 4-bit A register (accumulator) is the source and
destination register for most I/O, arithmetic, logic and
data memory access operations. It can also be used to
load the Br and Bd portions of the B register, to load and
input 4 bits of the 8-bit Q latch data, to input 4 bits of the
8-bit L I/O port data and to perform data exchanges with
the SIO register.

Program Memory consists of a 1,024 byte ROM. As can
be seen by an examination of the COP420/421
instruction set, these words may be program
instructions, program data or ROM addressing data.
Because of the special characteristics associated with
the JP, JSRP, JID and LQID instructions, ROM must
often be thought of as being orgainzed into 16 pages of
64 words each.

A 4·bit adder performs the arithmetic and logic functions of the COP420/421, storing its results in A. It also
outputs a carry bit to the 1-bit C register, most often
employed to indicate arithmetic overflOW. The C
register, in conjunction with the XAS instruction and the
EN register, also serves to control the SK output. C can
be outputted directly to SK or can enable SK to be a
sync clock each instruction cycle time. (See XAS
instruction and EN register description, below.)

ROM addressing is accomplished by a 10-bit PC
register. Its binary value selects one of the 1,024 8-bit
words contained in ROM. A new address is loaded into
the PC register during each instruction cycle. Unless
the instruction is a transfer of control instruction, the
PC register is loaded with the next sequential 10-bit
binary count value. Three levels of subroutine nesting
are implemented by the 10-bit subroutine save registers,
SA, SB and SC, providing a last-in, first-out (LIFO)
hardware subroutine stack.

Four general·purpose inputs, IN 3 -IN o, are provided; IN 1,
IN2 and IN3 may be selected, by a mask-programmable
option, as Read Strobe, Chip Select and Write Strobe
inputs, respectively, for use in MICROBUSTM
applications.

ROM instruction words are fetched, decoded and
executed by the Instruction Decode, Control and Skip
'
Logic circuitry.

Data Memory

The D register provides 4 general-purpose outputs and
is used as the destination register for the 4-bit contents
of Bd.

Data memory consists of a 256-bit RAM, organized as 4
data registers of 16 4-bit digits. RAM addressing is
implemented by a 6-bit B register whose upper 2 bits (Br)
select 1 of 4 data registers and lower 4 bits (Bd) select 1

The G register contents are outputs to 4 generalpurpose bidirectional I/O ports. Go may be maskprogrammed as an output for MICROBUSTM
applications.

1-64

The Q register is an internal, latched, 8-bit register, used
to hold data loaded to or from M and A, as well as 8-bit
data from ROM. Its contents are output to the L I/O
ports when the L drivers are enabled under program
control. (See LEI instruction). With the MICROBUSTM
option selected, Q can also be loaded with the 8-bit
contents of the L I/O ports upon the occurence of a
write strobe from the host CPU_

1. The least significant bit of the enable register, EN o,
selects the SIO register as either a 4-bit shift register
or a 4-bit· binary counter. With EN o set, SIO is an
asynchronous binary counter, decrementing its value
by one upon each low-going pulse ("1" to "o")
ocurring on the Sllnput. Each pulse must be at least
two instruction cycles wide. SK outputs the value of
SKL. The SO output is equal to the value of EN 3. With
EN o reset, SIO is a serial shift register shifting left
each instruction cycle time. The data present at SI
goes into the least significant bit of SIO. SO can be
enabled to output the most significant bit of SIO
each cycle time. (See 4 below.) The SK output
becomes a logic-controlled clock.

The 8 L drivers,when ef}abled, output the coments of
latched Q data to the L I/O ports. Also, the contents of L
may be read directly into A and M. As explained above,
the MICROBUSTM option allows L I/O port data to be
latched into the Q register. L I/O ports can be directly
connected to the segments of a multiplexed LED
display (using the LED Direct Drive output configuration
option) with Q data being outputted to the Sa-Sg and
decimal pOint segments of the display.

2. With EN1 set the IN1 input is enabled as an interrupt
input. Immediately following an interrupt, EN1 is
reset to disable further interrupts.
3. With EN2 set, the L drivers are enabled to output the
data in Q to the L I/O ports. Resetting EN2 disables
the L drivers, placing the L I/O ports in a highimpedance input state.
4. EN 3, in conjunction with EN o, affects the SO output.
With EN o set (binary counter option selected) SO will
output the value loaded into EN 3. With EN o reset
(serial shift register option selected), setting EN3
enables SO as the output of the SIO. shift register,
outputting serial shifted data each instruction time.
Resetting EN3 with the serial shift register option
selected disables SO as the shift register output;
data continues to be shifted through SIO and can be
exchanged with A via an XAS instruction but SO
remains reset to "0." The table below provides a
summary of the modes associated with EN3 and EN o.

The SIO register functions as a 4-bit serial-in/serial-out
shift register or as a binary counter depending on the
contents of the EN register. (See EN register
description, below.) Its contents can be exchanged with
A, allowing it to input or output a continuous serial data
stream. SIO may also be used to provide additional
parallel I/O by connecting SO to external serialin/parallel-out shift registers. For example of additional
parallel output cap- see Application #2_
The XAS instruction copies C into the SKL latch. In the
counter mode, SK is the output of SKL; in the shift
register mode, SK outputs SKL ANDed with the clock.
The EN register is an internal 4-bit register loaded under
program control by the LEI instruction. The state of
each bit of this register selects or deselects the
particular feature associated with each bit of the EN
register (EN3 - END).

Enable Register Modes - Bits EN3 and ENO

EN3

ENo

SIO

SI

SO

SK

°

°
°

Shift Register

Input to Shift Register

°

If SKL= 1, SK = CLOCK

°

1

Binary Counter

1

1

1

Shift Register

Input to ,Shift Register

Serial Out

If SKL = 0, SK =

If SKL = 1, SK = CLOCK
If SKL = 0, SK =

Binary Counter

Input to Binary Counter

Input to Binary Counter

°

If SKL = 1, SK = 1

1

If SKL = 1, SK = 1

If SKL = 0, SK = 0

If SKL = 0, SK =

1-65

°
°
°

o
o"'C

~
52

o

o

"'C

~
......

-o
o

"'C

~

52

o

o"'C
(,.)

N

......

~

~

c..

o()

a

~

c..

o()

~

~

c..

o

()

a

~

c..

o

()

Interrupt
The following features are associated with the IN1
interrupt procedure and protocol and must be considered by the programmer when utilizing interrupts.

capability necessary for asynchronous data transfer
between the host CPU and the COP420.
"T:his option has been designed for compatibility with
National's MICROBUSTM - a standard interconnect
system for 8-bit parallel data transfer between MOS/LSI
CPUs and interfacing devices. (See MICROBUSTM
National Publication.) The functioning and timing relationships between the COP420 signal lines affected by
this opotion are as specified for the MICROBUSTM
interface, and are given in the AC electrical characteristics and shown in the timing diagrams (figures 4 and 5).
Connection of the COP420 to the MICROBUSTM is
shown in figure 6.

a_ The interrupt, once acknowledged as explained
below, pushes the next sequential program counter
address (PC + 1) onto the stack, pushing In turn the
contents of the other subroutine-save registers to the
next lower level (PC + 1 - SA - SB - SC). Any
previous contehts of SC are lost. The program counter
is set to hex address OFF (the last word of page 3)
and EN1 is reset.
b. An interrupt will be acknowledged only after the
following conditions are met:
1 . EN1 has been set.
2. A low-going pulse ("1" to "0") at least two
instruction cycles wide occurs on the IN1 input.

POWER
SUPPl Y

3. A currently executing instruction has been
completed.
4. All successive transfer of control instructions and
successive LBls have been completed (e.g., if the
main program is executing a JP instruction which
transfers program control to another JP instruction,
the interrupt will not be acknowledged until the
second JP instruction has been executed.
c_ Upon acknowledgement of an interrupt, the skip
logic status is saved and later restored upon popping
of the stack_ For example, if an interrupt occurs
during the execution of ASC (Add with Carry, Skip on
Carry) instruction which results in carry, the skip
logic status is saved and program control is transferred to the interrupt servicing routine at hex
address OFF_ At the end of the interrupt routine, a
RET instruction is executed to "pop" the stack and
return program control to the instruction following
the original ASC. At this time, the skip logiC is
enabled and skips this instruction because of the
previous ASC carry. Subroutines and LaiD instructions should not be nested within the interrupt service routine, since their popping the stack will enable
any previously saved main program skips, interfering
with the orderly execution of the interrupt routine.
d_ The first instruction of the interrupt routine at hex
address OFF must be a NOP.
e_ A LEI instruction can be put immediately before the
RET to re-enable interrupts.

CLOCK

INTERRUPT flNTR)
B·BIT DATA BUS

MICROPROCESSOR

READ STROBE liITl)
CHIP SELECT ICS)
WRITE STROBE IWRI

IN
OUT

RESET

Figure 6. MICROBUS™ Option Interconnect

Initialization
The Reset Logic, internal to the COP420/421 , will initialize (clear) the device upon power-up if the power supply
rise time is less than 1 ms and greater than 1 flS. If the
power supply rise time is greater than 1 ms, the user
must provide an externalRC network and diode to the
RESET pin as shown below. The RESET pin is configured
as a Schmitt trigger input. If not used it should be connected to Vee. Initialization will occur whenever a logic
"0" is applied to the RESET input, provided it stays low
for at least three instruction cycle times.
Upon initialization, the PC register is cleared to 0 (ROM
address 0) and the A, B, C, D, EN, and G registers are
cleared. The SK output is enabled as a SYNC output,
providing a pulse each instruction cycle time. Data
Memory (RAM) must be cleared by the user's program.
The first instruction at address 0 must be a CLRA.

Mlcrobus™ Interface
The COP420 has an option which allows it to be used as
a peripheral microprocessor device, inputting and outputting data from and to a host microprocessor ~P).
IN 1, IN2 and IN3 general purpose inputs become
MICROBUSTM compatible read-strobe, chip-select, and
write-strobe lines, respectively. IN1 becomes RD - a
logic "0" on this input will cause a latch data to be
enabled to the L ports for input to the flP. IN2 becomes
CS - a logic "0" on this line selects the COP420 as the
flP peripheral device by enabling the operation of the RD
and WR lines and allows for the selection of one of
several peripheral components. IN3 becomes WR - a
logic "0" on this line will write bus data from the L ports
to the a latches for input to the COP420. Go becomes
INTR a "ready" output, reset by a write pulse from the
flP on the WR line, providing the "handshaking

P+-_. . .----,

U
W
E
R

S

U
P
P
L

VCC

RESET COP420/421
GND

y

RC" 5 x POWER SUPPL Y RISE TIME

Figure 7 .. Power-Up Clear Circuit

1-66

(")

Oscillator
There are four basic clock oscillator configurations
available as shown by figure 8.

an INIL instruction. As another option, CKO can be a
RAM power supply pin (V R), allowing its connection
to a standby/backup power supply to maintain the
integrity of RAM data with minimum power drain
when the main supply is inoperative or shut down to
conserve power. Using either option is appropriate in
applications where the COP420/421 system timing
configuration does not require use of the CKO pin.

a. Crystal Controlled Oscillator. CKI and CKO are
connected to an external crystal. The instruction
cycle time equals the crystal frequency divided by 16
(optional by 8).
b. External Oscillator. CKI is an external clock input
signal. The external frequency is divided by 16
(optional by 8) to give the instruction cycle time. CKO
is now available to be used as the RAM power supply
(V R) or as a general purpose input.

RAM Keep·Alive Option
Selecting CKO as the RAM power supply (VR) allows
the user to shut off the chip power supply (Vccl and
maintain data In the RAM. To insure that RAM data
integrity is maintained, the following conditions
must be met:

c. RC Controlled Oscillator. CKI is configured as a
single pin RC controlled Schmitt trigger oscillator.
The instruction cycle equals the oscillation frequency
divided by 4. CKO is available for non·timing func·
tions.

1. RESET must go low before Vcc goes below spec
during power-off; Vcc must be within spec before
RESET goes high on power-up.
2. VR must be within the operating range of the chip,
and equal to Vcc ± 1V during normal operation.
3. VR must be ;;'3.3V with Vcc off.

d. Externally Synchronized Oscillator. Intended for use
in multi-COP systems, CKO is programmed to function
as an input connected to the SK output of another
COP420/421 with CKI connected as shown. In this
configuration, the SK output connected to CKO must
provide a SYNC (instruction cycle) signal to CKO,
thereby allowingsynchronou~ data transfer between
the COPs using only the SI and SO serial I/O pins in
conjunction with the XAS instruction. Note that on
power·up SK is automatically enabled as a SYNC
output (See Functional Description, Initialization,
above).

CKO Pin Options
In a crystal controlled oscillator system, CKO is used
as an output to the crystal network. As an option
CKO can be a SYNC input as described above. As
another option CKO can be a general purpose input,
read into bit 2 of A (accumulator) upon execution of
an INIL instruction. As another option, CKO can be a
RAM power supply pin (V R), allowing its connection
to a standby/backup power supply to maintain the
integrity of RAM data with minimum power drain
when the main supply is inoperative or shut down to
conserve power. USing either option is appropriate in
applications where the COP420/421 system timing
configuration does not require use of the CKO pin.

CKO Pin Options
In a crystal controlled oscillator system, CKO is used
as an output to the crystal network. As an option
CKO can be a SYNC input as described above. As
another option CKO can be a general purpose input,
read into bit 2 of A (accumulator) upon execution of

COP42OJ421

J1.J
EXTfANAL

(VA OR GENERAL
PlJRPOSE INPlIT

CLOCK

PIN)

so
RC Controlled Oscillator

ExtOl/mal Oscillator

Crystal Oscillator

Externally Synchronized Oscillator

Crystal Oscillator

Crystal
Value

COP4201421

so

RC Co'ntrolled Oscillator

Component Values
Rl

R2

C

4MHz

lk

1M

27pF

3.58MHz
2.09MHz

lk

1M

27 pF

lk

1M

56pF

R(knl

c (OF)

12

100

6.8

220

5.3 ± 23%

8.2

300

22

100

S± 29%
8.6 ± 16%

Figure 8. COP420/4211COP320/321 Oscillator

1-67

Instruction
Cycle Time
in J.ts

5± 20%

Nole: 50k;;' R ;. 5k
360pF;. C;' 50pF

o""C
it;

S2
(")

o
."

....it;

-o
( ")

."
~

I\)

S2
(")

o
."
~

....

I\)

,..
~

0..

oo
cs
C\I

('I)

0..

oo
,..

~

0..

oo
cs
~

0..

o
o

1/0 Options
COP420/421 outputs have the following
configurations, illustrated in figure 9a:

optional

i. A Hi·Z input which must be driven to a "1" or "0" by
external components.

a. Standard - an enhancement mode device to ground
in conjunction with a depletion·mode device to Vee,
compatible with TTL and CMOS input requirements.
Available on SO, SK, and all 0 and G outputs.
b. Open·Draln - an enhancement·mode device to
ground only, allowing e¥ternal pull·up as required by
the user's application. Available on SO, SK, and all 0
and G outputs.
c. Push·Pull.;..
An enhancement·mode device to
ground in conjLinction with a depletion·mode device
paralleled by an enhancement·mode device to Vee.
This configuration has been provided to allow for
fast rise and fall times when driving capacitive loads.
Available on SO and SK outputs only.

The above input and output configurations share com·
mon enhancement-mode and depletion·mode devices.
Specifically, all configurations use one or more of six
devices (numbered 1-6, respectively)_ Minimum and
maximum cLirrent (lOUT and VOUT ) curves are given in
figure 9b for each of these devices to allow the designer
to effectively use these 110 configurations in designing
a COP420/421 system.
The SO, SK outputs canbe configured as shown in a.,
b., or c. The 0 and G outputs can be configured as
shown in a. or b. Note that when inputting data to the G
ports, the G outputs should be set to "1." The L outputs
can be configured as in d., e., f. or g.
An important paint to remember if using configuration
d. or f. with the L drivers is that even when the L drivers
are disabled, the depletion load device will source a
small amount of current (see figure 9b, device 2);
however, when the L lines are used as inputs, the
disabled depletion device can not be relied on to source
sufficient currentto pull an input to logic "1".

d. Standard L - same as a., but may be disabled.
Available on L outputs only.
e. Open Drain L - same as b., but may be disabled.
Available on L outputs only.

f. LED Direct Drive - an enhancement·mode device to
ground and to Vee, meeting the typical current
sourcing requirements of the segments of an LED display. the sourcing device is clamped to limit
current flow. These devices may be turned off under
program .control (See Functional Description, EN
Register), placing the outputs in a high·impedance
state to provide required LED segment blanking for a
multiplexed display.
g. TRI·STATE@ Push·Pull - an enhancement·mode
device to ground and Vce ' These outputs are TRISTATE outputs, allowing for connection of these
outputs to a data bus shared by other bus drivers.

COP421
If the COP420 is bonded as a 24-pin device, it becomes
the COP421, illustrated in. figure 2, COP420/421
Connection Diagrams. Note that the COP421 does not
contain the four general purpose IN inputs (IN3-INo).
Use of this option precludes, of course, use of the IN
options, interrupt feature, and the MICROBUSTM option
which uses IN 1 -IN 3 . All other options are available for
the COP421.

COP420/COP421 inputs have the following optional
configurations:
h. An on-chip depletion load device to Vee.

a. Standard Output

c. Push-Pull Output

b. Open·Drain Output

Vee

DISABlE.

DlSABlE~~

(.ISOEPlETlDHDfVICE)

d. Standard L Output

g.

TRI·STATE~

e. Open-Drain L Output

Push·Pull (L Output)

h. Input with Load

Figure 9a. Input/Output Configurations

1·68

f. LED (L Output)

I. Hi·Z Input

C')

o

Output Sink Current

Depletion Load OFF Source Current

!

25

;<

S

Vee L.5V iMAX)

fJf·

20

t-

ve~

(MI~)_ i--

Vee' 6.Jv

>~

15

0

10

V

C')

;<

\

S
~-O.2

~I

f1

S2

-0.3

• 6.31V (MJ)

o

"tJ

~
.....

\

-

MAX

Vee' 4.5V (MIN)
-0.1

f

\

MIN

I I

""-

C')

o

'J.

"tJ

DEVICE 1

VOUT (VOLTS)

VOUT (VOLTS)

OEVleE 2

-1.5
~-1,25

1

/v6e' dv (MJX)

--0.75
-0.5
-0.25

Vee

y

"'- ,/'"
~

s

,

'~

.......

~

Vee' 4.5V (MIN)

...........

K

\
\

;<

vJe· 4.iv (MAX)

E

-1

vee' 6.3V (MIN)

r-- IS ~

Vee it5V
(MIN)

DEVICE 2

-18
-16
-14

/ 1'\.1
1
\ Vee' 6.3V (MAX) 1
V

......

~-12
~-lD

-2

1

\

-='-8
-4

\.

"" -

Y

1

\

,.t

/

~

~

1
1
1

1-

1

;<

S -10

~
-5

VOUT' 2.DV

10

...... V

>-

~ -8

1

.'

-4
-2

1

V

V

-6

1

o

~Il~~

.......

r-r-

4.5

5.5
Vee (VOLTS)

DEVICE 4 AND 2

Input Load Source Current

¥6.3V(MAX)
.... 4.5V (MAX)

\ !\
\

\
,\ \
\ '\ ......"k\ K \
1\

\

;...4.5V (MIN)
.... 6.JV(MIN)

4
VOUT (VOLTS)

OEVleE 5

Figure 9b.COP420/COP421 Input/Output Characteristics

1·69

,,"'-

/

-12

, \V\

\

DEVICE3AND2

MAX

TRI·STATE® Output Source Current

-15

4r

I\, ~ ~I

-14

4

VOUT (VOLTS)

~ t-(~,Cfx)

-16

Vee' 6.3V (MIN)

1
I'd

1

LED Output Direct LED Drive

Vee' 4.5V (MIN)

1\

1

-18

Vee' 4.5V (MAX)

1\....

S

-6

1

vee' 6'
(MIN)

VOUT{VOLTS)

LED Output Source Current
-20

1

6.3V I(MAX)

1

~

\

K

VOUT (VOLTS)

i

1\

-2

E

~ -1.0

o"tJ

-3

-1.15

~
S2
C')

Push-Pull Source Current

Standard Output Source Current
-2.0

"tJ

t

-0.4

3D

6.5
DEVICE 4 AND 2

~
I\)

.....

.,..
C\I

OUTPUT SINK CURRENT

('I)

Q;,

30

0

25

I

(J

aC\I

('I)

e..
0

-"VCC = 5.5J (MAX\
-"VCcl=

20

<
.!§.
l-

-.,..

15

~

~

VCC

II1I::I"

-0.4

.!§.

~ -0.3

-0.2

~ 4.5V i(MIN)

-0.1

1 I'

~AX
~N_I\
2

4.
VOUT (VOLTS)

e..
0

VOUT (VOLTS)

DEVICE 1

STANDARD OUTPUT SOURCE CURRENT

(J

-1.75

a

-1.5

~

(J

<

VCC - 5.5V (MIN)

10

C\I

4.5~ (MINI
I

::>

::

(J

e..
0

OEPLETION LOAD OFF SOURCE CURRENT

-1.25

~ -1.0
I-

VCC

"

::
-1.0

'\ l/CC = 4.5V (MIN)
)<

1---11.

r~l~5.5V

1\

-2.5

VCC - 4.5V (MAi)

VCC=5.5}
-0.5 (MI~

DEVICE 2

VCC 114.5V\
- 0.5 (MIN)

~"
~~

VCC =14.5V
(MAX)r
VCC -5.5V
(MIN)

lJ

1\...' ~

r--..

2

4

VOUT (VOLTSI

DEVICE 2 AND 3

4

VOUT (VOLTS)

DEVICE 2

LED OUTPUT DEVICE LED DRIVE
I

LED OUTPUT SOURCE CURRENT
-14

/

..,12

VMAX

-10

<
.!§.

<
.!§.

l-

I-

::

::

::>

l

-8

1/

::>

-6
-4
-2

VOUT (VOLTS)

DEVICE 4 AND 2

o

I
I

/

VOUT=2.0V

I

4.0 4.5
5.0
VCC (VOLTS)

TRISTATE OUTPUT SOURCE CURRENT

..

v
...... V
5.5

6.0

DEVICE 4 AND 2

INPUT LOAD SOURCE CURRENT

-1.0 i--I--+--j--+--t---l

-0.8

-D.21--'-----';:-+-"i.-i"'i....+----l
4

VOUT (VOLTS)

6

5
VOUT (VOLTS)

DEVICE 5

Figure 9c. COP320/COP321 Input/Output Characteristics

1-70

DEVICE 6

o

COP420/421/320/321 INSTRUCTION SET
Table 1 is a symbol table providing internal architecture,
instruction operand and operation symbols used in the
instruction set table.

Table 2 provides the mnemonic, operand, machine code,
data flow, skip conditions and description associated
with each instruction in the COP420/421 instruction set.

o"C
~
S2

o

o

Table 1. COP420/421/320/321 Instruction Set Table Symbols

Symbol

Symbol

Definition

INTERNAL ARCHITECTURE SYMBOLS
A
4-bit Accumulator
6-bit RAM Address Register
B
Br
Upper 2 bits of B (register address)
Bd
Lower 4 bits of B (digit address)
C
1-bit Carry Register
4·bit Data Output Port
0
4-bit Enable Register
EN
4·bit Register to latch data for GilD Port
G
IL
Two 1·blt Latches associated with the IN3 or INO

OPERATIONAL SYMBOLS

4·bit Input Port
S·bit TRI·STATE 110 Port
4·bit contents of RAM Memory pointed to by B

a
SA
SB
SC
SID
SK

+

Plus

-

Minus

-

Register

PC

~
......

Definition

INSTRUCTION OPERAND SYMBOLS
4·bit Operand Field, 0-15 binary (RAM Digit Select)
d
r
2·bit Operand Field, 0-3 binary (RAM Register
Select)
a
10·blt Operand Field. 0-1023 binary (ROM Address)
y
4·bit Operand Field, 0-15 binary (immediate Data)
RAM(s)
Contents of RAM location addressed by 5
ROM(t)
Contents of ROM location addressed by t

Inputs

IN
L
M

"C

10·bit ROM Address Register (program counter)
S·bit Register to latch data for L 110 Port

A

The ones complement of A

•

10-bit Subroutine Save Register A

Exclusive-OR

10·bit Subroutine Save Register C
4-bit Shift Register and Counter

Logic·Controlied Clock Output

Table 2. COP420/421 Instruction Set

Mnemonic Operand

Hex
Code

Machine
Language Code
(Binary)

Data Flow

Skip Conditions

Description

ARITHMETIC INSTRUCTIONS
ASC

30

10

a 1 110 a a a I

A + C + RAM(8) - A
Carry - C

Carry

Add with Carry, Ski'p on
Carry

ADD

31

10

a 1 110 a a 11

A + RAM(B)- A

None

Add RAM to A

ADT

4A

10 1 a 011

A + 1010 - A

None

Add Ten to A

AISC

5-

10 10 1

I

A + y- A

Carry

Add Immediate, Skip on
Carry (y" 0)

CASC

10

10

a a 110 a a a I

A+ RAM(B) + C- A
Carry - C

Carry

Complement and Add
with Carry, Skip on Carry

CLRA

00

10

a a 010 a a a I

a-A

None

Clear A

COMP

40

10 1

a 010 a a a I

A-A

None

Ones complement of A to
A

NOP

44

10 1 0010 1 001

None

None

No Operation

Y

a 1 aI
y

I

RC

32

10011100101

SC

22

a 1 010 a 1 aI

XOR

02

10

10000100101

"a" -

None

Reset C

"1"-C

None

Set C

A

None

Exclusive·OR RAM with A

ffi

C

RAM(B)- A

1-71

S2

o

o"C
......

Range of values

10-bit Subroutine Save Register B

W

I\)

N

15 exchanged with

Is equal to

"C

W

Replaces

=

-oo

,....
~
a..

Table 2. COP420/421/320/321 Instruction Set (continued)

oo

~

('I)

a..

oo

,....

Mnemonic Operand

oo

JID

JMP

a

oo

Data Flow

FF

11111111111

6-

1011°100Ia9:81
a7:0
I
1

-JP

a

(3

~
a..

Machine··
Lan,uage Code
Binary)

Skip Conditions

Description

TRANSFER OF .CONTROL INSTRUCTIONS

~

a..

Hex
Code

ROM (PC9:8,A,M) PC7:0

None

Jump Indirect (Note 3)

a -PC

None

Jump

None

Jump within Page
(Note 4)

--

a6:0
111
(pages 2,30nly)
or

I

a - PC6:0

--

a5:0
1111
I
(all other pages)

a - PC5:0

!1 01

I

PC + 1 - SA - SB - SC None
0010 - PC9:6
a - PC5:0

Jump to Subroutine Page
(Note 5

JSRP

a

--

JSR

a

6-

a5:0

10110 /1 Oa9:8
a7:0

I

I
I

PC + 1 - SA - SB - SC None
a- PC

Jump to Subroutine

-RET

48

10 1 0011 000

I

sc -

SB - SA - PC

None

Return from Subroutine

RETSK

49

10 1 0011 00 11

sc -

SB - SA - PC

Always Skip on
Return

Return from Subroutine
then Skip

MEMORY REFERENCE INSTRUCTIONS
CAMO

33
3C

10 0 1 110 0 1 1 I
100 1 111 1 001

A - 07:4
RAM(B) - 03:0

None

Copy A, RAM to 0

COMA

33
2C

1001 11001 1 I
100 1 0111 001

07:4 - RAM(B)
03:0-A

Neine

Copy 0 to RAM, A

-5

1001 rl01011

RAM(B)- A

None
Brmr-Br

Load RAM into A,
Exclusive·OR Br with r

23

100 1 010 0 1 1 I
d
100 r
1

RAM(r,d) - A

None

--

Load A with RAM pOinted
to directly by r,d

BF

11011111111

ROM(PC9:8,A,M) - 0
SB- SC

None

Load 0 Indirect (Note 3)

LD

r

LDD

r,d

LOID

I I

RMB

0
1
2
3

4C
45
42
43

101 0011
10 1 0 010
10 1 0 010
10 1 0 010

1 001
101I
0 101
0 11I

0000-

RAM(B)O
RAM(Bl1
RAM(B)2
RAM(B)3

None

Reset RAM Bit

5MB

0
1
2
3

4D
47
46
4B

101 00111 01 I
101 0010 1 1 1 1
10 1 0 010 1 1 0 I
10 1 0 011 0 1 1 I

1111-

RAM(B)O
RAM(B)1
RAM(B)2
RAM(Bb

None

Set RAM Bit

,

1·72

(")

o

Table 2. COP420142113201321 Instruction Set (continued)

'"C

'0l::I0
Mnemonic Operand

Hex
Code

I\)

Machine
Language Code
(Binary) ,

Data Flow

Skip Conditions

Description

y

7-

10111

X

r

-6

XAD

r,d

23

XDS

XIS

r

r

I

y

I

y - RAM(B)
Bd+l-Bd

None

Store Memory Immediate
and Increment Bd

100 1 r 101101

RAM(B)- A
BrEI> r- Br

None

Exchange RAM with A,
Exclusive·OR Br with r

1001 0100 1 11
d
1101 r
I

RAM(r,d)- A

None

--

Exchange A with RAM
pOinted to directly by r,d

-7

100 1 r 101111

RAM(B)- A
Bd-1- Bd
BrEl>r- Br

Bd decrements past 0

Exchange RAM with A
and Decrement Bd,
Exclusive·OR Br with r

RAM(B)- A
Bd+1- Bd
Brm r - Br

Bd increments past 15

Exchange RAM with A
and Increment Bd,
Exclusive·OR Br with r

A- Bd

None

Copy A to Bd

-4

I

100 1 r 101001

REGISTER REFERENCE INSTRUCTIONS
CAB

50

10 1 0 110 0 0 0 I

CBA

4E

10100111101

Bd - A

None

Copy Bd to A

--

1001 r l(d-1)
(d =0,9:15)
or
1001 11 001 11
d
110 1r
(any d)

I

r,d- B

Skip until not a LBI

Load B Immediate with
r,d (Note 6)

33
6-

10011100111
10110 1 y
I

y - EN

None

Load EN Immediate
(Note 7)

12

10001100101

A - Br (0,0 - A3,A2)

None

Exchange A with Br

SKC

20

1001010000

C="1"

Skip if C is True

SKE

21

1001010001

A=RAM(B)

Skip if A Equals RAM

SKGZ

33
21

1001 11001 1
1001010001

G3:0=0

Skip if G is Zero
(all 4 bits)

0
1
2
3

33
01
11
03
13

1001 11001 1
1000010001
1000 110 0 01
100001001 1
100011001 1

0
1
2
3

01
11
03
13

1000010001
1000110001
1000010011
1000110011

RAM(B)O
RAM(BII
RAM(B)2
RAM(B)3

41

101 001000 1

A time·base counter
carry has occurred
since last test

LBI

r,d

33

-LEI

y

XABR

I

I

TEST INSTRUCTIONS

SKGBZ

SKMBZ

SKT

(")

o
'"C

MEMORY REFERENCE INSTRUCTIONS (continued)
STIl

S2

1st byte

)

2nd byte

1·73

Skip if G Bit Is Zero
GO
G1
G2
G3

=
=
=
=

0
0
0
0
=
=
=
=

0
0
0
0

Skip if RAM Bit is Zero

Skip on Timer
(Note 3)

~
......

-o
( ")

'"C

~
S2
(")

o'"C
~
......

,..

~
0
0
CS

\

Table 2. COP4201421/3201321 Instruction set (continued)

0-

C'I
('I)

0-

0

Mnemonic Operand

Hex
Code

Machine
Language Code
(Binary)

Data Flow

Skip Conditions

Description

INPUT/OUTPUT INSTRUCTIONS
ING

0

33
2A

1001 11001 11
10 0 1 011 0 1 0

G-A

None

Input G Ports to A

I

,..

ININ

33
28

10011100111
10 0 1 011 0 0 0 I

IN- A

None

Input IN Inputs to A
(Note 2)

0-

INIL

33
29

10011100111
10 0 1 011 0 0 1

IL3, CKO, "0", ILo - A

None

Input IL Latches to A
(Note 3)

0

INL

33
2E

10 0 1 110 0 1 1 1
10010111101

L7:4 - RAM(B)
L3:0- A

None

Input L Ports to RAM,A

0-

OBO

33
3E

10 0 1 110 0 1 1 1
10011111101

Bd - 0

None

Output Bd to 0 Outputs

0

OGI

33

10011100111
10101 1 y 1

y- G

/IIone

5-

Output to G Ports
Immediate

OMG

33
3A

10011100111
100 i 111 0101

RAM(B)- G

None

Output RAM to G Ports

XAS

4F

10 1 00111 1 11

A-

None

Exchange A with 510
(Note 3)

~
0

0

~
0

Y

I

SID, C - SKL

Note 1: All subscripts for alphabetical symbols Indicate bit numbers unless explicitly defilied (e.g., Br and Bd are explicitly defined). Bits are
numbered 0 to N where 0 signifies the least significant bit (low'Order, rlght·most bit). For example, A3 Indicates the most significant (Ieft·most)
bit of the 4·blt A register.
Note 2: The ININ instruction Is not available on the 24·pln COP4211COP321 since this device does not contain the IN Inputs.
Note 3: For addilional Information on the operallon of the XAS, JID, LOID, INIL, ~nd SKT Ins,ructlons, see below.
Note 4: The JP Instruction allows a Jump, while In subroullne pages 2 or 3,to any ROM location within the two·page boundary of pages 2 or 3.
The JP Instrucllon, otherwise, permits a jump to a ROM locallon within the current 54·word page; JP may not Jump to the last word of a page.
Note 5: A JSRP transfers program control to subroullne page 2 (0010 Is loaded Into the upper 4 bits of PI. A JSRP may not be used when In pages
2 or 3. JSRP may not jump to the last word in page 2.
Note 6: LBlls a single·byte instruction if d = 0,9,10, II, 12, 13, 14, or 15. The machine code for the lower 4 bits equ'als the binary value olthe "d"
data minus I, e.g., to load the lower four bits of B (Bd) with the value 9 (10012), the lower 4 bits of the LBIInstru9110n equal 8 (IOOO2l. To load 0, the
lower 4 bits 01 the LBI instruction should equal 15 (11112)'
Note1: Machine code lor operand field y for LEllnstruclion should equal the binary value to be latched Into EN, where a "I" or "O"ln each bit 01
EN ';orr~sponds with the selecllon or deselecllon ~fa particular function associated with each bit. (See Functional Descrlpllon, EN Register.)

1·74

LaiD Instruction
The lollowing inlormation is provided to assist the user
in understanding the operation 01 several unique
instructions and to provide notes uselul to
programmers in writing COP420/421 programs.

LQID (Load Q Indirect) loads the 8·bit Q register with the
contents 01 ROM pointed to by the 10·bit word PCg, PCs,
A, M. LQID can be used for table lookup or code conver·
sian such as BCD to seven·segment. The LQID instruction "pushes" the stack (PC + 1 - SA - SB -SC) and
replaces the least signilicant 8 bits of PC as follows: A
- PC 7 :4 , RAM(B) - PC 3:a, leaving PCg and PCs
unchanged. The ROM data pointed to by the new address
is fetched and loaded into the Q latches. Next, the stack
is "popped" (SC - SB - SA -PC), restoring the saved
value 01 PC to continue sequential program execution.
Since LQID pushes SB - SC, the previous contents of
SC are lost. Also, when LQID pops the stack, the previously pushed contents of S8 are left in SC. The net result
is that the contents of SB are placed in SC (SB - SC).
Note that LQID takes two instruction cycle times to
execute.

XAS Instruction
XAS (Exchange A with SIO) exchanges the 4·bit contents 01 the accumulator with the 4·bit contents 01 the
SIO register. The contents olSIO will contain seriaiin/serial·out shift register or binary counter data,
depending on the value 01 the EN register. An XAS
instruction will also affect the SK output. (See
Functional Description, EN Register, above.) II SIO is
selected as a shift register, an XAS instruction must be
perlormed once every 4 instruction cycles to effect a
continuous data stream.

JID Instruction

SKT Instruction

JID (Jump Indirect) is an indirect addressing instruction,
translerring program control to a new ROM location
pointed to indirectly by A and M. It loads ,the lower 8 bits
01 the ROM address register PC with the contents 01
ROM addressed by the 10·bit word, PCg:s, A, M. PCg and
PCs are not allected by this instruction.

The SKT (Skip On Timer) instruction tests the state of an
internal 10·bit time·base counter. This counter divides
the instruction cycle clock Irequency by 1024 and pro·
vides a latched indication 01 counter overflow. The SKT
instruction tests this latch, executing the next program
instruction if the latch is not set. II the latch has been
set since the previous test, the next program instruction
is skipped and the latch is reset. The features associ·
ated with this instruction, .therefore, allow the COP420/
421 to generate its own time·base for real·time proces·
sing rather than relying on an external input signal.

Note that JID requires 2 instruction cycles.

INIL Instruction
INIL (Input IL Latches to A) inputs 2 latches, IL3 and ILa
(see ligure 10) and CKO into A. The IL3 and ILa latches
are set il a low-going pulse ("1" to "0") has occurred on
the IN3 and INa inputs since the last INIL instruction,
provided the input pulse stays low lor at least two
instruction times. Execution 01 an INIL inputs IL3 and
ILa into A3 and AO respectively, and resets these latches
to allow them to respond to subsequent low-going
pulses on the IN3 and INa lines. II CKO is mask
programmed as a general purpose input, an INIL will
input the state 01 CKO into A2. II CKO has not been so
programmed, a "1" will be placed in A2. A "0" is always
placed in A1 upon the execution 01 an INIL The general
purpose inputs IN3-INa are input to A upon execution 01
an ININ instruction. (See table 2, ININ instruction.) INIL
is useful in recognizing pulses 01 short duration or
pulses which occur too often to be read conveniently by
an ININ instruction.

For example, using a 2.097 MHz crystal as the time-base
to the clock generator, the instruction cycle clock fre·
quency will be 131 kHz (crystal Irequency -+- 16) and the
binary counter output pulse frequency will be 128 Hz.
For time·ol-day or similar real-time processing, the SKT
instruction can call a routine which increments a "seconds" counter every 128 ticks.

Instruction Set Notes
a. The lirst word of a COP420/421 program (ROM
address 0) must be a CLRA (Clear A) instruction.
b. Although skipped instructions are not executed, one
instruction cycle time is devoted to skipping each
byte of the skipped instruction. Thus all program
paths take the same number of cycle times whether
instructions are skipped or executed.

Note: IL latches are not cleared on reset.

c. The ROM is organized into 16 pages 01 .64 words
each. The Program Counter is an 10·bit binary
counter, and will count through page boundaries. II a
JP, JSRP, JID or LQID instruction is located in the
last word 01 a page, the instruction operates as if it
were in the next page. For example: a JP located in
the last word 01 a page will jump to a location in the
next page. Also, a LQID or JID located in the last
word 01 page 3, 7, 11 or 15 will access data in the next
group 01 lour pages.

COP42D
ININ

.1.
INoI1N3

INll

1-75

o

o

"tJ

~o
o

"tJ

~
......

-

o
o
"'tJ

CN

I\)

S2

(')

o"tJ
~
......

T'"

~

OPTION LIST

oo

The COP420/421 mask-programmable options are
assigned numbers which correspond with the
COP420 pins_

Il..

o
~

Il..

o

-~
o

T '"

oo

o

~

Il..

o
o

Option 16: SI Input
same as Option 9
Option
= 0:
= 1:
= 2:

The following is a list of COP420 options_ When
specifying a COP421 chip, Options 9, 10, 19, 20 and
29 must all be set to zero_ The options are
programmed at the same time as the ROM pattern to
provide the user with the hardware flexibility to
interface to various I/O components using little or no
external circuitry_
Option 1 = 0: Ground Pin -

Option 18: SK Driver
same as Option .17
Option 19: INo Input
same as Option 9

no options available

Option 20: IN3 Input
same as Option 9

Option 2: CKO Pin
= 0: clock generator output to crystal
(0 not available if option 3 = 4 or 5)
= 1: pin is RAM power supply (V R) input
= 2: general purpose input with load device
= 3: multi-COP SYNC input
=4: general purpose Hi Z input
Option
= 0:
= 1:
= 2:
=3:
= 4:
= 5:

Option 21: Go I/O Port
= 0: Standard output (A)
= 1: Open-Drain output (B)
Option 22: G1 I/O Port
same as Option 21

3: CKI Input
crystal input divided by 16
crystal input divided by 8
TTL external clock input divided by 16
TTL external clock input divided by 8
single-pin RC controlled oscillator ( ..... 4)
Schmitt trigger clock input (+4)

Option 23: G2 I/O Port
same as Option 21
Option 24: G3 I/O Port
same as Option 21
Option 25: 0 3 Output
= 0: Standard output (A)
= 1: Open-Drain output (B)

Option 4: RESET Pin
= 0: Load devices to Vee
= 1: Hi-Z input
Option
= 0:
= 1:
= 2:
= 3:

Option 26: O2 Output
same as Option 25
Option 27: 0 1 Output
same as Option 25

5: L7 Driver
Standard output (figure 90)
Open-Drain. output (E)
LED direct drive output (F)
TRI-STATE® push-pull push-pull output (G)

Option 28: Do Output
same as Option 25
Option 29: COP Function
= 0: normal operation
= 1: MICROBUSTM option

Option 6: L6 Driver
same as Option 5
Option 7: L5 Driver
same as Option 5

Option 30: COP Bonding
= 0: COP420 (28-pin device)
= 1: COP421 (24-pin device)

Option 8: L4 Driver
same as Option 5

Option 31: IN Input Levels
= 0: Normal input levels
'= 1: Higher voltage input levels
("0"=1.2V, "1"=3.6V)

Option 9: IN1 Input
= 0: load device to Vee (H)
= 1: Hi-Z input (I)

Option 32: G Input Levels
same as Option 31

Option 10: IN2 Input
same as Option 9
Option 11 =0: Vee Pin -

17: SO Driver
standard output (A)
open-drain output (B)
push-pull output (C)

Option 33: L Input Levels
same as Option 31

no options available

Option 12: L3 Driver
same as Option 5

Option 34: CKO Input Levels
same as Option 31

Option 13: L2 Driver
same as Option 5

Option 35: SI Input Levels
same as Option 31

Option 14: L1 Driver
same as Option 5
Option 15: Lo Driver
same as Option 5

1-76

o

o

TEST MODE (Non-Standard Operation
The SO output has been configured to provide for
standard test procedures for the custom-programmed
COP420. With SO forced to logic "1," two test modes
are provided, depending upon the value of SI:
a. RAM and Internal Logic Test Mode (SI
b. ROM Test Mode (SI = 0)

2. The D3- Do outputs drive the digits of them
multiplexed display directly and scan the columns of
the 4 x 4 keyboard matrix.

3. The IN3-INo inputs are used to input the 4 rows of the
keyboard matrix. Reading the IN lines in conjunction
with the current value of the 0 outputs allows
detection, debouncing, and decoding of anyone of
the 16 keyswitches.
4. CKI is configured as a single·pin oscillator input
allowing system timing to be controlled by a Singlepin RC network. CKO is therefore available for use as
a VR RAM power supply pin. RAM data integrity is
thereby assured when the main power supply is shut
down (see RAM Keep·Alive Option description).
5. SI is selected as the input to a binary counter input.
With SIO used as a binary counter, SO and SK can be
used as general purpose outputs.
6. The 4 bidirectional G I/O ports (G 3-G O) are available
for use as required by the user's application.

= 1)

These special test modes should not be employed by
the user; they are intended for manufacturing test only.

APPLICATION #1: COP420 General Controller
Figure a shows an interconnect diagram for a COP420
used as a general controller. Operation of the system is
as follows:
1. The Lr Lo outputs are configured as LED Direct
Drive outputs, allowing direct connection to the
segments of the display.
l.lV

Vee

CKO

Vce

LO
L7

t-......,="."...---,
t--=-==-.....,

CKI
4·DIGIT
LED DISPLAY

GNO

COP42D

00
0,
02
RESET

0,

4GENERAL
1i0

'N,

.,

'NO

KEYSWITCH
MATRIX

IN2
EVENT
COUNTER - - . . . SI'
INPUT

IN,

'51, SO and SK may also be used lor serial 110
Figure 11. COP420 Keyboard/Display Interlace

APPLICATION #2:
Figure 12 provides an interconnect diagram for a versa·
tile application the COP420 as a keyboard/display
interface to a microprocessor (flP). Generally, operation
of the COP420 in this configuration is as follows:

into SIO to be tested as one of the 4 row lines tied to
the keyboard matrix. SO is used to output display
segment data (loaded into SIO with an XAS instruction) to the cascaded 74C164s (a·bit parallel·out serial
shift registers). SK functions as a logic-controlled
clock, sending a SYNC signal to a clock serial data
into the 74C164s.
4. The 16 bits of data shifted into the 74C164s are
buffered through the DSaa67s (a·segment LED drivers) to the 16 segments of the alpha-numeric LED
displays.

1. The MICROBUSTM option has been selected.
2. System timing is provided by an external crystal. The
time base for the real·time (counter and clock) modes
is provided by the internal time-base counter, tested
by the SKT instruction.

3. The SIO register is used as a serial·in/serial·out shift
register. In this configuration, however, SI is shifted

1-77

'"'0

t

52

o

o'"'0

t

-o
......

o

'"'0

(,.)
I\)

52

o

o"tJ
rd
......

'r"

C'\I
M

Il.

oo

25
~

Il.

oo

or-

~

Il.

o

o

8.. The various operations which can be performed by
the system include the following "handshaking" and
COP420"stand-alone" modes:
a. keyboard to I'P (7-bit ASCII)
b. I'P to display
c. display to I'P
d. display to "p
e. "p to clock
f. clock to "p
g. keyboard to display
h. clock to display

5. The 00·01 outputs are decoded by the .OS8864
(14-digit decoder/driver) and used to select one of the
14 digits of the multiplexed display as well as to scan
the 13 columns of the keyboard matrix and the strap
.
switch scan line (014).
6. The G1-G 3 lines together with SI are connected to the
4 rows of the keyboard matrix and the 4 strap switch
lines to input key or strap switch data to the COP420.
The strap switches can be used to select one of
several of the system modes listed below.
7. The Lo-L7 TRI-STATE'" bidirectional I/O prots are
connected to the microprocessor data bus to allow
for input or output of data to and from the microprocessor and the COP420.

25
~

F

Il.

o
o

r
TO

DJ
D,
D

CONNECTOR

06

LOCK1

t,
t,
t,
t,
t,
t,

D,
D,
D,

LJ

.,,,.' t '

D,

INTR

RD

os

WR

"'"
'"

INO

SPARE INPUT

Vee

Vee

C0P420

"J

RESET

DJ
D,
D,
D,

(VCC-PIN18.

GNO - PIN9i

"
CONNECTOR
TO " ' ' '

1
SEE SEGMENT
CONFIGURATION
FOR PINOUTS

~

TRAPS~D7J1" j

r-~-"---1r-Vcc

2019811
4 11.01 02 03 04

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5

1615141]
Os 06 III 08

1
81 :

~::

'i'~~.I&J.'
,,' .

,f/./I:"'J
"-D,-

.
D,
D,
,

15

SEGMENT PIN

"" "
"
21

10

CO"ECTOR

Vee

KEYBOARD LAVOUT

, ,

. ,,

ALI

Q

W

A

,

Z

X

_A,_~

A,
A,

16
013 014

058664

ALPHANUMERIC DISPlAV
SEGMENT CONFIGURATION

SEGMfNT PIN

111098
09 OlD 11 0 12

01-0n
TO KEYED

J

,
,
, , , , ,
I

%

@

-~

9

,

R

D

F

,

C

v

.

T

V

"
N

M

U

,

,

t

D

P

I

Figure 12. COP420 Keyboard/Display Interlace

1-78

".... ~CTRl "

OU

RET

~SHIFT "

"

BS....

l,jSHIFT

RUB

II
9

l,J.SPAR

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(")

o"tJ

~National

~ Semiconductor

~
o
Q

CO P420C/CO P421 C and COP320C/COP321 C

(")

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Single·Chip CMOS Microcontrollers
General Description
The COP420C, COP421C, COP320C, and COP321C
Single-Chip CMOS Microcontrollers are members of
the COPSTM family, fabricated using complementary
MOS technology. They are complete microcomputers
containing ali system timing, internal logic, ROM,
RAM and 110 necessary to implement dedicated control functions in a variety of applications. Features
include single supply operation, a variety of output
configuration options, with an instruction set, internal
architecture and 1/0 scheme designed to facilitate
keyboard input, display output and BCD and binary
data manipulation. The COP421C is identical to the
COP420C, except with 191/0 lines instead of 23. They
are an appropriate choice for use in numerous human
interface control environments. Standard test procedures and reliable high-density fabrication techniques
provide the medium to large volume customers with
a customized Control Oriented Processor at a low
end-product cost.

The COP320C/321C are exact functional equivalents
of the COP420C/421C. .

~
......

Features

(")

Q
•
•
•
•
•
•
•

Lowest power dissipation (50I'W typical)
Power saving "Idle" state
Powerful instruction set
1kx8 ROM, 64x4 RAM, 231/0 lines (COP420C)
True vectored Interrupt, plus restart
Three-level subroutine stack
151's instruction time, plus software selectable
oscillators
Single supply operation (2.4-6.0V)
Internal time-base counter for real-time processing
MICROWIRETM compatible serial 1/0
General purpose and TRI-STATE® outputs
TTL/CMOS compatible
LED direct drive outputs
MICROBUSTM compatible
Softwarelhardware compatible with other members
of COP400 family
Extended temperature range device
COP320C/COP321C (-40°C to +85°C)

•
•
•
•
•
•
•
•

The COP320C is the extended temperature range
version of the COP420C (likewise the COP321C is the
extended temperature range version of the COP421C).

•

COP420C/421 C Block Diagram
OND

~,
TlME·BASE

COUNTER

DIVIDE BY 1024)

D3

D,
D,
DO

"
r--,...--+o-!l-"'3

l-LEVElSTACK

1---1-'14 "
1----1-'14 "

I/O CONTROLS

-

L_...!l--""""-'!""'·o

--,

I
I
I

I

L-_ _ _ _~_.......,~!...,.SD

I
5

6

1

8

\2

20 to 9
19
IN] 11112 IN, 11110

1-79

Il

14

15

o"tJ
~
o
Q

(")

o"tJ
(,.)

I'\)
......

(")

()

,....

~
Q.

o

~
~

Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature Range

-0.3VtoVce +0.3V

O·Cto +70·C
-40·Cto +85·C
-65·Cto +150·C
Storage Temperature Range
300·C
Lead Temperature (Soldering, 10 seconds)
Package Power Dissipation
500mW
COP420C/421C
COP320C/321C

Q.

o
()

o,....

DC Electrical Characteristics

Q.

Operation Voltage

~

o
()

o
~

Q.

o
()

Parameter

Conditions

Min

Max

Units

2.4

6.0

Volts

Supply Current
(Note 1)

Vee
Vee
Vee
Vee

2.4V
5.0V
5.0V
5.0V

FIN
FIN
FIN
FIN

= 32kHz
= 32kHz
= 500kHz
2.097MHz (.;. 32mode)

=

35
100
800
1200

/loA
/loA
/loA
/loA

Idle State Current

Vee = 2.4V
Vee = 5.0V

FIN
FIN

= 32kHz
= 500kHz

15
250

/loA
/loA

0.1 Vee

V
V

0.25Vee

V
V

0.4

V
V

0.2

V
V

=
=
=
=

Input Voltage Levels
Schmitt Trigger Inputs
RESET, CKI (as RIC)
and .00 (as Clock)
Logic High
Logic Low

0.9Vee

All Other Inputs
Logic High
Logic Low

0.6 Vee

Output Voltage Levels
Standard Output
TTL Operation
Logic High
Logic Low

Vee = 5V±5%
IOH= -100/loA
IOL = 1.6mA

CMOS Operation
Logic High
Logic Low

IOH = -:10/loA
IOL=10/loA

2.4

Vee - 0.2

Output Current Levels
L Outputs with
High Current Option
Logic High
Logic Low

Vee = 6V, VOH = 2.0V
VOL = 0.4V

Hi-Z or Tri-State
Input Current Levels

1-80

-2.5
1.6

-15

mA
mA

-1.0

1.0

/loA

(')

AC Electrical Characteristics
Parameter
Instruction Cycle Time
COP420C/COP421C
Operating CKI Frequency
COP420C/COP421C

Instruction Cycle Time
CO P320C/CO P321 C
Operating CKI Frequency
CO P320C/CO P321 C

Instruction Cycle Time
DO as Clock or CKI (RIC)
CKO as SYNC Input
tSYNe

2.4V

~

Vee

~

Condition
Vee;' 4.5V
Vee;' 2.4V
+8 mode
+ 16 mode
+32 mode

Vee;' 4.5V

+8 mode
+16 mode
+32 mode

Vee;' 2.4V
Vee;' 4.5V
Vee;' 2.4V

+8 mode
+ 16 mode
+32 mode

o""0

6.0V unless otherwise stated

Vee;' 4.5V

+8 mode
+16 mode
Vee;' 2.4V
+32 mode
R=30k ±5%, C= 100pF ± 10%
Vee =5V

Min
15
50
32
64
128
32
64
128
15
50
64
128
256
64
128
256

Max
245
245
500
1000
2097

Units

160
320
640
125
125

kHz
kHz
kHz

500
1000
2097
160
320
640
25

kHz
kHz
kHz
kHz
kHz
kHz

I's
kHz
kHz
kHz

I's

~

I\)
......
Q

(')

o""0
(,.)
I\)

o
Q

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400

ns

(,.)
I\)

2
0.6

I's
I's

4
2

I's
I's

3
3

I's
I's

0.4
0.4

I's
I's

50
5
400
300
200

ns
ns
ns
ns
ns

700

ns
ns
ns
ns
ns
ns

VOH =0.7V ee, VOL = 0.2Vee
CL =50pF

Fanout = 1 Standard TTL Load.
CL =50pF, Vee = 5V±5%
VOH =2.4V
VOL=0.4V

tpOl
tpoo
MICROBUSTM TIMING

o""0

o""0
......

tSETUP
tHOLO

t pOl
tpoo
CKO Output

Q

(')

I'S

15

INPUTS:

OUTPUTS:
COP to CMOS
tpOl
tpoo
COP to TTL

~
o

CL = 50pF, Vee = 5V ± 5%

Read Operation (figure 4)
Chip Select Stable Before RD - tesR
Chip Select Hold Time for RD.;.. tRes
RD Pulse Width -tRR
Data Delay from RD - tRo
RD to Data Floating -tOI
Write Operation (figure 5)
Chip Select Stable Before WR - tesw
Chip Select Hold Time for WR - twes
WR Pulse Width - tww
Data Set·Up Time for WR -tow
Data Hold Time for WR - two
INTR Transition Time from WR -tWI

50
30
350
300
40

Note 1 - Supply current is measured with a squarewave clock, all inputs at Vee.
and all outputs open while the COP420C is running.

1-81

(')

,...
~

Q.

o

GNO
CKO
CKI

()

o

Rmf

~

L7
L6
L5
L4
IN1
IN2
VCC
L3
L2
11

Q.

o
~
,...
~

Q.

o

COP420C
10
11
12
1J
14

()

28
27
26
25
24
2J
22
21
20
19
18
17
16
15

DO
01
02
03
GJ
G2
G1
GO
INJ
INO
SK
SO
SI
LO

GNO
CKO
CKI

Rmf
L7
L6
L5
L4
VCC
LJ
L2
11

COP421C

10
11

12

24
2J
22
21
20
19
18
17
16
15
14
1J

DO
01
02
OJ
GJ
G2
G1
GO
SK
SO
SI
LO

Figure 2. Connection Diagrams

C5
~

Q.

o
()

Pin Description
8 bidirectional I/O ports with TRI-STATE@

CKI

System oscillator input

CKO

INs-INo
SI

4 bidirectional I/O ports
3 general purpose outputs
General purpose output or oscillator input
4 general purpose inputs (COP420C only)
Serial input

Vee

System oscillator output (or general purpose
input)
System reset input
Power supply

GNO

Ground

SO
SK

Serial output
Logic-controlled clock

LTLO
G3·G O
0 3-0 1

DO

RESET

Figure 3. Input/Output Timing Diagrams (divide by 8 mode)

-1 !-two

CKI

JlJlJLJL
-l~I-'SYNC

two-+-I-I-two
CKIJLnJ

CKo-MW-

'P01~

CKO
(INPUT)

Figure 3A. Synchronization Timing

I- -I

!-'POO

Figure 36. CKO Output Timing

1-82

o

o

.

"'0

IRR

• -IRCS-=4'

\

_IDF

_ICSR_I_IRD_(
{L)-LOI

.j
}-

D)-DO

~

Q

o

o

"'0

Figure 4. MICROBUSTM Read Operation Timing

~

N
tcsw---.. ..

\.

{L)-LOI

{Gol

D)-DO

~

lWW

!WCs-l.

1

___ IDW _ _ _

-

.

!WI

Jo-

!WD

J..

~

Q

o

o"'tJ

~

~

Q

o

INTR

Figure 5. MICROBUSTM Write Operation Timing

o"'0

~

FUNCTIONAL DESCRIPTION

~

select 1 of 16 4·bit digits in the selected data register.
While the 4-bit contents of the selected RAM digit (M) is
usually loaded into or from, or exchanged with, the A
register (accumulator), it may also be loaded into or
from the a latches or loaded from the L ports. RAM
addressing may also be performed directly by the LDD
and XAD instructions based upon the 6·bit contents of
the operand field of these instructions. The Bd register
also serves as a source register for 4-bit data sent
directly to the D outputs.

For ease of reading this description, only COP420C and/
or COP421C are referenced; however, all such references
apply equally to COP320C and/or COP321C, respectively.
A block diagram of the COP420C is given in Figure 1.
Data paths are illustrated in simplified form to depict
how the various logic elements communicate with each
other in implementing the instruction set of the device.
Positive logic is used. When a bit is set, it is a logic "1".
When a bit is reset, it is a logic "0"
Program Memory
Program Memory consists of a 1,024·byte ROM. As can
be seen by an examination of the COP420C/421C
instruction set, these words may be program instruc·
tions, program data or ROM addressing data. Because
of the special characteristics associated with the JP,
JSRP, JID and LaiD instructions, ROM must often be
thought of as being organized into 16 pages of 64 words
each.

Internal Logic
The 4·bit A register (accumulator) is the source and
destination register for most 110, arithmetic, logic and
data memory access operations. It can also be used to
load the Br and Bd portions of the B register, to load and
input 4 bits of the 8-bit a latch data, to input 4 bits of the
8-bit L 110 port data and to perform data exchanges with
the SIO register.

ROM addressing is accomplished by a 10-bit PC
register. Its binary value selects one of the 1,024 8-bit
words contained in ROM. A new address is loaded into
the PC register during each instruction cycle. Unless
the instruction is a transfer of control instruction, the
PC register is loaded with the next sequential 10-blt
binary count value. Three levels of subroutine nesting
are implemented by the 10·bit binary subroutine save
registers, SA, SB and SC, providing a last·in, first-out
(LIFO) hardware subroutine stack.

A 4·bit adder performs the arithmetic and logic
functions of the COP420C/421C, storing its results In A.
It also outputs a carry bit to the 1·bit C register, most
olten employed to indicate arithmetic overflow. The C
register, in conjuction with the XAS Instruction and the
EN register, also serves to control the SK output, C can
be outputted directly to SK or can enable the SK to be a
sync clock each instruction cycle time. (See XAS instruction and EN register description, below.)

Data Memory

Four general·purpose inputs, IN 3-IN o, are provided; IN j ,
IN2 and IN3 may be selected, by a mask·programmable
option, as Read Strobe, Chip Select and Write Strobe
inputs, respectively, for use in MICROBUSTM applications.

Data Memory consists of a 256-bit RAM, organized as 4
data registers of 16 4-bit digits. RAM addressing is
implemented by a 6·bit B·register ~hose upper 2 bits
(Br) select 1 of 4 data registers and lower 4 bits (Bd)

The 0 register provides 4 general purpose outputs and
is used as the destination register for the 4·bit contents
of Bd. In the dual clock mode, D·register bit 0 controls
the clock selection (see dual oscillator below).

ROM instruction words are fetched, decoded and
executed by the Instruction Decode, Control and Skip
Logic circuitry.

1-83

o

o,..
~

a..

oo

o
~
a..
oo

o,..
~

a..

oo

oo
~

a..
oo

The XAS instruction copies C into the SKL Latch. SK out·
puts SKL ANDed with the internal instruction cycle clock.

The G register contents are outputs to 4 general:
purpose bidirectional 1/0 ports. Go may be maskprogrammed as an output for MICROBUSTM applications.

The EN Register is an internal 4-bit register loaded
under program control by the LEI instruction. The state
of each bit of this register selects or deselects the
particular feature associated with each bit of the EN
register (EN 3-EN o)'

The Q register is an Internal, latched, 8-bit register, used
to hold data loaded to or from M and A, as well as 8-bit
data from ROM. Its contents are output to the L 1/0
ports when the L drivers are enabled under program
control (see LEI instruction). With the MICROBUSTM
option selected, Q can also be loaded with the 8-bit
contents of the L 1/0 ports upon the occurence of a
write strobe from the host CPU.

1. The least significant bit of the enable register, EN o,
must be set at O.

2. With EN1 set the IN1 input is enabled as an interrupt
input. Immediately following an interrupt, EN1 is
reset to disable further interrupts.

The 8 L drivers, when enabled,output the contents of
latched Q data to the L 1/0 ports. Also, the contents of L
may be read directly into A and M. As explained above,
the MICROBUSTM option allows L 1/0 port data to be
latched into the Q register. L 1/0 ports can be directly
connected to the segments of a multiplexed LED
display (using the LED Direct Drive output configuration
option) with Q data being outputted to the Sa-Sg and
decimal point segments of the display.

3. With EN2 set, the L drivers are enabled to output the
data in Q to the L I/O ports. Resetting EN2 disables the
L drivers, plaCing the L I/O ports in a high-impedance
input state. If the MICROBUSTM option is being used,
EN2 does not affect the L drivers.
4. EN3 affects the SO output. Setting EN3 enables SO
as the output of the SIO shift register, outputting
serial shifted data each instruction time. Resetting
EN 3 disabies SO as the shift register output: data
continues to be shifted through 510 and can be exchanged with A via an XAS instruction but SO remains
reset to "0."

The 510 register functions as a 4-bit serial-in/serial-out
serial shift register shifting left each instruction cycle
time. The data present at SI goes into the least significant bit of SIO. SO can be enabled to output the most
significant bit of SIOeach cycle time (see 4 below). The
SK output becomes a logic-controlled clock. The SIO
contents can be exchanged with A, allowing It to input
or output a continuous serial data stream. SIO may also
be used to provide additional parallel 1/0 by connecting
SO to external serial-in/parallel-out shift registers.

1-84

(')
COP420C/421C INSTRUCTION SET

Table 2 provides the mnemonic, operand, machine
code, data flow, skip conditions and description associated with each instruction in the COP420C/421C
instruction set.

Table 1 is a symbol table providing internal architecture, instruction operand and operational symbols used
in the instruction set table.

Table 1_ COP420C/421C Instruction Set Table Symbols
Symbol

INSTRUCTION OPERAND SYMBOLS
4-bit Operand Field, 0-15 binary (RAM Digit
d
Select)
2-bit Operand Field, 0-3 binary (RAM
r
Register Select)
la-bit Operand Field, 0-1023 binary (ROM
a
Address)
4·bit Operand Field, 0-15 binary (Immediate
y
Data)
RAM(s) Contents of RAM location addressed by s
ROM(t) Contents of ROM location addressed by t

Hex
Code

Machine Language
Code (Binary)

OPERATIONAL SYMBOLS
Plus
+
Minus
Replaces
Is exchanged with
Is equal to
-=
A
The ones complement of A
Exclusive·OR
:
Range of values

(')

'"

Data Flow

Skip Conditions

Description

A + C + RAM (B) - A
Carry - C

Carry

Add with Carry, Skip on
Carry

ADD

31

10 0 1 110 a a 11

A + RAM(B) - A

None

Add RAM to A

ADT

4A

10 1 0011 01 01

A + 10'0 - A

None

Add Ten to A

5-

10 1 a 11

I

A + y- A

Carry

Add Immediate, Skip
on Carry (y " 0)

10

10 a a 110 0 a a

I

-

Carry

Complement and Add
with Carry,
Skip on Carry

A + RAM (B) + C-A
Carry - C

CLRA

00

10 a a 010 a a a

I

~

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......

--

10011100001

CASC

(')

o"tJ

CAl

30

y

~
......
Q

(')

ASC

Y

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ARITHMETIC INSTRUCTIONS

AISC

o
Q

Q

Table 2. COP420C/421C Instruction Set Table (Note 1)

Mnemonic Operand

~
I\)

(')

Definition

INTERNAL ARCHITECTURE SYMBOLS
A
4-bit Accumulator
6-blt RAM Address Register
B
Br
Upper 2 bits of B (register address)
Bd
Lower 4 bits of B (digit address)
C
l-bit Carry Register
D
4-bit Data Output Port
EN
4-bit Enable Register
G
4-bit Register to latch data for G I/O Port
IL
Two l-bit Latches associated with the IN3 or
INolnputs
IN
4-bit Input Port
8-bit TRI-STATE I/O Port
L
M
4-bit contents of RAM Memory pointed to by
B Register
PC
10-bit ROM Address Register (program
counter)
Q
8-bit Register to latch data for L I/O Port
10-bit Subroutine Save Register A
SA
SB
10-bit Subroutine Save Register B
SC
10-bit Subroutine Save Register C
SIO
4-bit Shift Register
SK
Logic-Controlled Clock Output

o"tJ

0- A

None

Clear A

None

Ones complement of A
to A

COMP

40

10 1 a 010 a a 01

A-A

NOP

44

10100101001

None

None

No Operation
Reset C

RC

32

10011100101

"0" - C

None

SC

22

100 1 010 a 1 01

"l"-C

None

Set C

XOR

02

10 a a 010 a 1 01

A" RAM(B)-A

None

Exclusive·OR A with
RAM

1-85

(J

,...

Table 2. COP420C/421 C Instruction Set Table (continued)

~

£:L

o(J

Mnemonic Operand

Hex . Machine Language
Code
Code (Binary)

Data Flow

Skip Conditions

Description

TRANSFER OF CONTROL INSTRUCTIONS

o
~
£:L

J.ID

o(J

o,...

11111111111

ROM (PC9:8,A,M) PC7:0

None

Jump Indirect (Note 3)

10 11010 °la9:81
a7:0

a - PC

None

Jump

a - PC6:0

None

Jump within Page
(Note 4)

JMP

a

6--

JP

a

--

a6:0
11
(pages 2,3 only)
or

--

1111 a5:0
(all other pages)

~

I

I
I

I

I

a - PC5:0

I

PC + 1 - SA - SB SC
0010 - PC9:6
a - PC5:0

None

Jump to Subroutine Page
(Note 5)

101 1 01 1 0la9:81
a7:0
I

PC + 1 - SA - SB a- PC

None

Jump to Subroutine

-RET

48

10 100110001

SC - SB - SA - PC

None

Return from Subroutine

RETSK

49

101

a 0J1 a a 11

SC - SB - SA - PC

Always Skip on Return

Return from Subroutine
then Skip

IT

33
39

Ia a 1 110 a 1 11

£:L

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FF

JSRP

a

--

JSR

a

6-

110

I

a5:0

o
~£:L

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I

PC- PC

Idle till Timer overflows
then continue

10011110011

MEMORY REFERENCE INSTRUCTIONS
CAMQ

CQMA

33
3C

Ia a 1 110 a 1 11

33
2C

I a a 1 110 a 1 11

10011111001

10010111.001

A- Q7:4
RAM(B) - Q3:0

None

Copy A, RAM to Q

Q7:4 - RAM(B)
Q3:0- A

None

Copy Q to RAM, A

LD

r

-5

100lrl01011

RAM(B)- A
Br --L.r----

IONP_U_T_ _ _ _ _ _ _ _ _ _ _ _

o

o()

o
~
0..

1\

I

TO
A2

~(

CKI

o
()

SYSTEM
CLOCKS
(INCLUDING SKI

o
,...

.~

0..

Figure 10a. Oscillator Options Block Diagram Using SKT Instruction

o
()

o
~
0..

o
()

r-1~:
-=
1,

INIL

...L

INPU~
'"' . ~~

r-:.:;:-'l

~----q1 ~
asc. OUT

Figure 10b. Oscillator Options Block Diagram Using IT Instruction
NPUT

~
T

CKO
1------otH
' -_ _- '
OSC. OUT

TO
A2

.

~qvcc

, -_ _ _ _....J

CKI

~8HAI.T

'IT'

i5J
S

R

Figure 11. Dual Clock Option .Block Diagram

1·92

SYSTEM
CLOCKS

(")

1/0 Options

COP420C/421C inputs have the following options:

COP420C/421C outputs have the following optional
configurations, illustrated in figure 13:

g. A HiZ input which must be driven by user logic.

f. An on chip pullup load device to Vee.

a. Standard - An N channel device to ground in
conjunction with a Pchannel device to Vee,
compatible with CMOS and TIL.
b. Open Drain - An N channel device to ground only,
allowing external pull·up as required by the user's
application.

The above input and output configurations share
common devices. SpeCifically, all configurations use
one or more of four devices (numbered 1- 4,
respectively). Minimum and maximum current (lOUT and
VOUT) curves are given in figure 12 for each of these
devices to allow the designer to effectively use these 1/0
configurations.

c. TRI·STATE'"

L Output - A CMOS output buffer
which may be disabled by program control. These
outputs meet the requirements associated with the
MICROBUSTM option. These outputs are also capable
of meeting the current sourcing requirements of the
segments of a small LED display.
d. Standard L Output - This is the same configuration
as c. above except that the sourcing current is
standard.
e. Open Drain L Output - This has the N channel
device to ground only.

COP421C
If the COP420C is bonded as a 24'pin device, it becomes
the COP421C, illustrated in figure 2, COP420C/421C
Connection Diagrams. Note that the COP421C does not
contain the four general purpose IN inputs (IN 3·IN o). Use
of this option precludes, of course, use of the IN
options, interrupt feature, and the MICROBUSTM option
which uses IN ,·IN 3 . All other options are available for
the COP421 C.

o
"tJ
,.J::Io

~

Q
(')

o"tJ

~
......
Q

(')

o

"tJ

(,.)

~

Q
(")

o
"tJ

(,.)

STANDARD OUTPUT smK GURRENT

.0

35
3D

25
20
15
10

STANDARD OUTPUT SOURCE CURRENT

Vee ~ 6V (MAX CURRENT)

fl

I I
I I

"3.

1 _I,

t

t - r7 ~VleeI 'J.2.51M~)1.1 Vee~6V (MIN)
I
I
~\_
t/' n T ~c~r5VI(MI~)

l - I- Vee ~ 2.5V (MIN)
3

4

5

-2.0 1--+--I-~-j--+---1-+-+-I
-1.5

I-f"o
tSETUP
tHOLO

S
600

"s
ns

2
600

"s
ns

All Standard Output
Configurations
tpD1

6.5

"s

SO, SK Outputs
tpD1 (push-pull)
tpDO

4.0
1.2

"s
"S

D3- Do, G3-GO
tpDO (standard size)
tpDO (high current)
tpDo (very high current)

2.7
2.5
2.4

"s
"s
"S

L7-4>
tpDO
tpD1 (standard size push-pull)
tpD1 (high current push·pull)

2.7
3.0
2.5

"S
"S
"S

SI
tSETUP
tHoLD
OUTPUTS:
COP TO CMOS PROPAGATION
DELAY

L7- 4> LED Direct Drive Outputs
tpD1 (standard size)
tpD1 (high current)

VOH = 0.7 Vcc, VOL = 0.3 Vcc,
CL = 50pF

6.0V';; Vec';; 9.5V, VOH=2.0V
CL =50pF

1-99

5:0
4.5

"S
"S

o

o
"ot

o
r-

o

"'0

t

"""""
r-

....

...J

lo

AC Electrical Characteristics (continued)
o·c .. TA .. + 70·C, 4.5V .. Vee" 9.5V unless otherwise specified.
Conditions

Parameter

Min

Max'

Units

~
o

COP TO LSTTL PROPAGATION

0..

SO, SK Outputs
t P01 (standard)
t po1 (push·pull),
tpDo

5
3.5
3

lIS
lIS
lIS

L7- Lo Outputs
t pD1 (push-pull)

1.5

lIS

L7-La, G3 -G O, 0 3 -00 Outputs
tpD1 (standard)
tpoo

5.0
2.0

lIS
lIS

CKO (figure 3b)
tp01
tpDO

0.4
0.4

lIS
lIS

~

o
o

Vee=5V±5%, VOH=2.7V
VOL = 0.4 V, CL=50pF

DELAY

" .,
"
"25 .,
.,

GNO
CKO
CKI

00

02
OJ

IIffiT
17

16
l5
L'
INI
IN'

Vee
Ll
l2
11

COP420l
ID

24
23
22

21
20
19
19
11

11
12

13
I.

"
15

DO
D1

GNO
CKO
eKI

24
23
22

IIffiT

21

L1
16
L5
L4
Vee
Ll
L2
LI

20

Gl
•0
IN'
INO
SK

so

..

COP421l

02
OJ

"

Gl
GO
SK

18
11

0

16

ID

"

11
12

.,.,
so

I.

SI

13

LD

SI
LD

Figure 2. Connection Diagrams

Pin
L,-Lo

Pin
CKI
CKO

Dascrlpt'lon

8 bidirectional I/O ports with
TRI·STAT~

G,-Go
D.-Do
IN,-INo
Sl
SO
SK

4 bidirectional

110 ports

Description

System oscillator input
System oscillator output (or general

purpose Input.

SYNC Input))

4 general purpose outputs

RESET

4 general purpose Inputs (COP420L only)

R~M

power supply or.

System reset Input

Serial Input (or counter Input)

Vee

Power supply

Serial output (or general purpose output)

GND

Ground

loglc-controlled clock (or general
purpose output)

Figure 3. Input/Output Timing Diagrams (Crystal Dlvlde·by·16 Mode)

CKI~

I.
"D~"DD
I

Figure 3a. Synchronization Timing

Figure 3b. CKO Output Timing

1-100

o

FUNCTIONAL DESCRIPTION

A block diagram of the COP420L is given in figure 1.
Data paths are illustrated in simplified form to depict
how the various logic elements communicate with
each other in implementing the instruction set of the
device. Positive logic is used. When a bit is set, it is a
logic "1" (greater than 2 volts). When a bit is reset, it
is a logic "0" (less than 0.8 volts).
Program Memory

enable SK to be a sync clock each instruction cycle
time. (See XAS instruction and EN register descrip·
tion, below.)
Four general·purpose inputs, IN 3 -IN o, are provided.
The D register provides 4 general·purpose outputs
and is used as the destination register for the 4·bit
contents of Bd. The D outputs can be directly con·
nected to the digits of a multiplexed LED display.

Program Memory consists of a 1,024·byte ROM. As
can be seen by an examination of the COP420U421L
instruction set, these words may be program
instructions, program data or ROM addressing data.
Because of the special characteristics associated
with the JP, JSRP, JID and LaiD instructions, ROM
must often be thought of as being organized into 16
pages of 64 words each.

The G register contents are outputs to 4 general·
purpose bidirectional 1/0 ports. G 1/0 ports can be
directly connected to the digits of a multiplexed LED
display.
The a register is an internal, latched, 8·bit register,
used to hold data loaded to or from M and A, as well
as 8·bit data from ROM. Its contents are output to the
L 1/0 ports when the L drivers are enabled under
program control. (See LEI instruction.)

ROM addressing is accomplished by a 10·bit PC
register. Its binary value selects one of the 1,024 8·bit
words contained in ROM. A new address is loaded
into the PC register during each instruction cycle.
Unless the instruction is a transfer of control instruction, the PC register is loaded with the next
sequential 10·bit binary count value. Three levels of
subroutine nesting are implemented by the 10-bit
subroutine save registers, SA, SB and SC, providing a
last·in, first-out (LIFO) hardware subroutine stack.

The 8 L drivers, when enabled, output the contents of
latched a data to the L 1/0 ports. Also, the contents
of L may be read directly into A and M. L 1/0 ports can
be directly connected to the segments of a multi·
plexed LED display (using the LED Direct Drive
output configuration option) with a data being
outputted to the Sa- Sg and decimal point segments
of the display.
The SIO register functions as a 4·bit serial-in/serial·
out shift register or as a binary counter depending on
the contents of the EN register. (See EN register
description, below.) Its contents can be exchanged
with A, allowing it to input or output a continuous
serial data stream. SIO may also be used to provide
additional parallel 1/0 by connecting SO to external
serial·in/parallel·out shift registers. For example of
additional parallel output capacity see Application

ROM instruction words are fetched, decoded' and
executed by the Instruction Decode, Control and
Skip Logic circuitry.
Data Memory

Data memory consists of a 256·bit RAM, organized as
4 data registers of 16 4·bit digits. RAM addressing is
implemented by a 6·bit B register whose upper 2 bits
(Br) select 1 of 4 data registers and lower 4 bits (Bd)
select 1 of 16 4-bit digits in the selected data register.
While the 4·bit contents of the selected RAM digit (M)
is usually loaded into or from, or exchanged with, the
A register (accumulator), it may also be loaded into
or from the a latches or loaded from the L ports. RAM
addreSSing may also be performed directly by the
LDD and XAD instructions based upon the 6·bit
contents of the operand field of these instructions.
The Bd register also serves as a source register for
4·bit data sent directly to the D outputs.

#2.
The EN register is an internal 4·bit register loaded
under program control by the LEI instruction. The
state of each bit of this register selects or deSelects
the particular feature associated with each bit of the
EN register (EN 3 - EN o).
1. The least significant bit of the enable register,
EN o, selects the SIO register as either a 4·bit shift
register or a 4-bit binary counter. With ENo set, SIO
is an asynchronous binary counter, decrementing
its value by one upon each low·going pulse ("1" to
"0") occurring on the SI input. Each pulse must be
at least two instruction cycles wide. SK outputs
the val ue of C upon execution of XAS and remains
the same, until the execution of another XAS
instruction. The SO output is equal to the value of
EN 3. With ENo reset, SIO is a serial shift register
shifting left each instruction cycle time. The data
present at SI goes into the least significant bit of
SIO. SO can be enabled to output the most
significant bit of SIO each cycle time. (See 4
below.) The SK output becomes a logic·controlled
clock, providing a SYNC signal each instruction
time. It will start outputting a SYNC pulse upon
the execution of an XAS instruction with C = 1,
stopping upon the execution of a subsequent XAS
with C=O.

Internal Logic
The 4·bit A register (accumulator) is the source and
destination register for most 1/0, arithmetic, logic
and data memory access operations. It can also be
used to load the Br and Bd portions of the B register,
to load and input 4 bits of the 8'bit a latch data, to
input 4 bits of the 8·bit LIIO port data and to perform
data exchanges with the SIO register.
A 4·bit adder performs the arithmetic and logic func·
tions of the COP420U421 L, storing its results in A. It
also outputs a carry bit to the 1·bit C register, most
often employed to indicate arithmetic overflow. The
C register, in conjunction with the XAS instruction
and the EN register, also serves to control the SK
output. C can be outputted directly to SK or can

1-101

o"'tJ

~

-oo
r-

"'tJ

~
......

r-

..J

.~

'~

D;.

oo

. .J

~
c..

o

With ENo reset (serial shift register option
,selected), setting ENa enables SO as the output of
the SIO shift register, outputting serial shifted
. data each instruction time. Resetting ENa with the
serial shift register option selected disables SO as
the shift register output; data ,continues to be
shifted through SIO and can be exchanged with A
via an XAS instruction but SO remains reset to
"0." The table below provides a summary of the
modes associated with ENa and EN o.

2. With EN1 set the IN1 input is enabled as an inter·
rupt input. Immediately following an interrupt, EN1
Is re,set to. disable fUrther interrupts. ,

3. With EN2 set, the L drivers are enabled to output
the dat~ in Q to the L I/O ports. Resetting EN2
disables the L drivers, placing the L I/O poris in a
hlgh·lmpedance input state.
4. EN3, in' conjunction with EN o, affects the SO
0lltput. With ENoset (binary counter option
selected) SO will output the value ioaded into EN a.

o

Enable Register Ft!Iodes - Bits EN3 and ENO
EN3

'EN o
0'

0

SIO

SI

SO

Shift Register

Input to Shift Register

0

"

'

SK after XAS
If C = 1, SK =' SYNC
If C = 0, SK = 0

'1

0

Shift- Register,

Input to Shift Register

Serial Out

If C = 1, SK = SYNC
If C = 0, SK = 0

0

1

Bi nary, Counter

InpOt to Binary Counter

o-

1

1

Bl'na'ry Counter

l!lput to Binary Counter

1

, If C ,,;' 1, Sk = 1
'Ife = ,O"SK =0
If C = 1, SK = 1
If C = 0, SK = 0

Interrupt
The following features are associated with the IN1
..interrupt procedure and protocol and must' be
considered by the programmer when utilizing inter·
tupts.
' ,
" ,
a. The interrupt, once acknowledged as, explained
below, pushes' the next 'sequential program
cO,unter address (PC + 1) onto the stack, pushing
in turn the contents of the either subroutine·save
registers to the next lower level, (PC + 1 ... SA':' SB
... sq. Any previous contents of SC are lost. The
program counter is set to hex address OFF (the
, last word of page 3) and,EN 1 1s reset.
b. An Interrupt will be acknowledged only after the
,following conditionsare met:
1. EN1has been set.
2. A low-going pulse ("1" to "0") at least two
instruction 'cycles wide occurs o'rnhe IN 1 lnput.
,3. A currently executing' ,instruction has been
, completed.'

c. Upon acknowledgement of an interrupt, the skip
logic status is saved and later restored upon the
execution of a subsequ,ent RET instruction. F.or
example, if an interf!Jpt ,.occurs du'ring' the
execution of ASC (Add with Ca'rry, Skip on Carry)
instruction which, results in carry, the skip logic
status is saved and program control Is transferred
to the, interrupt servicing routine at hex address
'oFF. At the end of the interrupt routine, a RET
instruction is executed to "pop" the stack and
return program control to the Instruction following
the original ASC. At th'is, time, th'e skip logic is
enabled and skips this, instruction because of the
previous ASe carry. Since, as explained above, it
is the RET instruction which enables the pre·
viously saved status of the skip logic, subrqutines
should not be nested within the interrupt servicing
routine since their 'RETinstruction will enable any
previously saved main program skips; interfering
with the orderly execution of the interrupt r6utlne.

4. All successive transfer of control instructi,ons
and successive LBls have been completed (e.g.,
If .. the main program is executing a JP
Instruction which transfers program control to
another JP instruction, the Interrupt
not be
acknowledged, uniil ~he second JP instruction
has been executed.

will

1-102

d. the first instruction of the interrupt routine at hex
address OFF must be a Nap.
e. A LEI instruction can be put immediately before
the RET to re-enableinterrupts.

(")

Initialization

Oscillator

The Reset Logic will initialize (clear) the device upon
power·up if the power supply rise time is less than
1 ms and greater than 1!,s. If the power supply rise
time is greater than 1 ms, the user must provide an
external RC network and diode to the RESET pin as
shown below. The RESET pin is configured as a
Schmitt trigger input. If not used it should be
connected to Vcc. Initialization will occur whenever a
logic "0" is applied to the RESET input, provided it
stays low for at least two instruction cycle times.

There are four basic clock oscillator configurations
available as shown by figure 4.

P +

o

- r -......- - - - ,

w

COP420l/421l
~_RESET

U

P
P

GND

l

Y-------..I
5x
RC

~

POWER SUPPl V RISE TIME

Power·Up Clear Circuit

Upon initialization, the PC register is cleared to 0
(ROM address 0) and the A, S, C, D, EN, and G
registers are cleared. The SK output is enabled as a
SYNC output, providing a pulse each instruction
cycle time. Data Memory (RAM) must be cleared by
the user's program. The first instruction at address 0
must be a CLRA.

CKI

b. External Oscillator. CKI is an external clock input
signal. The external frequency is divided by 32
(optional by 16 or 8) to give the instruction cycle
time. CKO is now available to be used as the RAM
power supply (V R), as a general purpose input, or
as a SYNC input.
c. RC Controlled Oscillator. CKI is configured as a
single pin RC controlled Schmitt trigger oscillator.
The instruction cycle equals the oscillation
frequency divided by 4. CKO is available as the
RAM power supply (V R) or as a general purpose
input.

VCC

E
R
S

a. Crystal Controlled Oscillator. CKI and CKO are
connected to an external crystal. The instruction
cycle time equals the crystal frequency divided by
32 (optional by 16 or 8).

d. Externally Synchronized Oscillator. Intended for
use in multi·COP systems, CKO is programmed to
function as an input connected to the SK output of
another COP chip operating at the same
frequency (COP chip with L or C suffix) with CKI
connected as shown. In this configuration, the SK
output connected to CKO must provide a SYNC
(instruction cycle) signal to CKO, thereby allowing
synchronous data transfer between the COPs
using only the SI and SO serial 110 pins in
conjunction with the XAS instruction. 'Note that on
power·up SK is automatically enabled as a SYNC
output (see Functional Description, Initialization,
above).

1
10
II JI

~

CKO

R2

CKI
VCC

~

CKI

eKO

T ... .

(SYNC)

CKO

t

t

CKI

CKO

SK~

~ (VR OR GENERAL

I

PURPOSE INPUT

."..

COP420L!421 L

PIN)

COP420 l/421 l

SO-SI
SI_SO

.Jl..J

EXTERNAL
CLOCK

(VR OR GENERAL

PURPOSE INPUT
OR SYNC PIN)

RC Controlled Oscillator

Crystal Oscillator

R1 (Q)

455kHz
2.097MHz

R (kQ)

C (pF)

Instruction
Cycle Time
in !'s)

51
82

100
56

19±15%
19±13%

Component Values

Crystal
Value

R2 (Q)

C1 (pF)

16k

1M

80

80

1k

1M

56

6-36

C2 (pF)

Figure 4. COP420Ll421 L Oscillator

1·103

o"'tJ

~
o
r-

-o
( ")

"'tJ

~
I\,)

......

r-

-I
T""

~

C-

o

~

-I

o
~
CO

(.)

CKO Pin Options

under
program
control
(see
Functional
Description, EN Register), placing the outputs in a
high,impedance state to provide required LED
segment blanking for a multiplexed display.
Available on L outputs only.

In a crystal controlled oscillator system, CKO is used
as an output to the crystal network. As an option
CKO can be a SYNC input as described above. As
another option CKO can be a general purpose input,
read into bit 2 of A (accumulator) upon execution of
an INIL instruction. As another option, CKO can be a
RAM power supply pin (V R), allowing its connection
to a standby/backup power supply to maintain the
integrity of RAM data with minimum power drain
when the main supply is inoperative or shut down to
conserve power. Using either option is appropriate in
applications where the COP420U421 L system timing
configuration .does not require use of the CKO pin.

g. TRI·STATE® Push·Puli - an enhancement-mode
device to ground and Vcc. These outputs are TRISTATE outputs, allowing for connection of these
outputs to a data bus shared by other bus drivers.
Available on L outputs only.

110 Options

i. A Hi-Z input which must be driven to a "1" or "0"
by external components.

COP420U421 L outputs have the following optional
configurations, illustrated in figure 5:
a. Standard - an enhancement-mode device to
ground in conjunction with a depletion-mode
device to Vcc , compatible with LSTTL and CMOS
input requirements. Available on SO,SK, and all D
and G outputs.
b. Open'Draln - an enhancement-mode device to
ground only, allowing external pull-up as required
by the user's application. Available on SO, SK, and
all D and G outputs.
c_ Push-Pull ,- an enhancement-mode device to
ground in conjunction with a depletion-mode
device paralleled by an enhancement·mode device
to Vcc. This configuration has been provided to
allow for fast rise and fall times when driving
capacitive loads. Available on SO and SK outputs
only.
d. Standard L - same as a_, but may be disabled.
Available on L outputs only.
e_ Open Drain L - same as b., but may be disabled.
Available on L outputs only.

f. LED Direct Drive - an enhancement mode device
to ground and to Vcc , meeting the typical current
sourcing requirements of the segments of an LED
display. The sourcing device is clamped to limit
current flow. These devices may be turned off

COP420U421L inputs have the following optional
configurations:
h. An on-chip depletion load device to Vcc.

The above input and output configurations share
common enhancement-mode and depletion-mode
devices. Specifically, all configurations use one or
more of six devices (numbered 1 - 6, respectively).
Minimum and maximum current (lour and Vour)
curves are given in figure 6 for each of these devices
to allow the designer to effectively use these I/O
configurations in designing a COP420U421 L system.
The SO,SK outputs can be configured as shown in a.,
b., or c. The D and G outputs can be configured as
shown in a. or b. Note that when inputting data to the
G ports, the G outputs should be set to "1." The L
outputs can be configured as in d., e., for g.
An important point. to remember if using configura·
tion d. or f. with the L drivers is that even when the L
drivers are disabled, the depletion load device will
sou'rce a small amount of current (see figure 6,
device 2).
COP421L
If the COP420L is bonded as a 24-pin device, it
becomes the COP421 L, illustrated in figure 2,
COP420U421L Connection Diagrams. Note that the
COP421 L does not contain the four general purpose
IN inputs (IN 3 -IN o). Use of this option precludes, of
course, use of the IN options and the interrupt
feature, which uses IN 1 -IN 3 . All other options are
available forthe COP421L.

o
o
"'tJ

~

-oo
r-

a. Standard Output

b. Open·Drain Output

c. Push·Pull Output

"'tJ

~
.....

r-

OISABLE~~

(.'''S DEPLETION DEVICE)

d. Standard L Output

e. Open· Drain L Output

f. LED (L Output)

h. Input with Load

i. Hi·Z Input

g. TRI·STATE® Push·Pull (L Output)

Figure 5. Output Configurations
Input Current for LO through L7 when
Output Programmed Off by Software

Input Current INO-IN3

Source Current for Standard Output
Configuration
-1000

-100
DEVICE d #2
AND f #2

-90
-80
-150

1

-100

1

-60

~

-50

c

E

~

E
-50

o t::!:::I::::!:Y~~::..i.::----1J
o 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.5

"-

-40

I

-600

1 -500

§

"'

I MAX)
-JO
Vee = 4.5 V
-20
IMIN@Vee= 9.5V
-10

o

-700

t\.

~

o

~

-200

.-:::::

1.0

-100

"""

"- IMAx@Vee= 9.5 V

IMAX@
-400 sec
= 4.5~

-JOO

~NJVef=~·5V

-20

-15

1'\

IMIN@
Vee = .5V
"
-r!-~
IMIN @
ee = 9.5V

!""'\

I"v

1.'1( f'-t-(

-I2

2.0

J

4

5

6

7

8

VOH (VOLTS)

Source Current for LO through L7 in
TRI·STATE" Configuration
(High Current Option)

Source Current for SO and SK in
Push· Pull Configuration

"'

1"\

V liD

VIN (VOLTS)

<
.§
E"

-800

I\. IMAX @Vee = 9.5V

-70

DEVICE a #2
AN~ d #2

-900

"'"

9.5

Source Current for LO through L7 in
TRI·STATE" Configuration
(Low Current Option)

r-l""T..-,,-,.--r-,-,-"-,,-,

-15

<
.§

-10

§

-5

-10

-5

4

5

6

V OH (VOLTS)

7

o

1

2

J

4

5

6

VOH (VOLTS)

1-105

7

8

9

10

o

1

2

J

4

5

6

VOH (VOLTS)

7

8

9

10

,..

..J
N
.q-

LED Output Direct Segment and Digit
Drive
High Current Options on LO- L7
Very High Current Options on 00- 03
or GO-G3

c..

0

LED Output Source Current
(lor Low Current LED Option)

LED Output Source Current
(lor High Current LED Option)

0

. .J
0
N

DEVICE f #2 AND #4
A~D DE~ICE. DR b #1

-40

.q-

c..

0

0

IMAX
ONE SEGEMENT
C[

C[

oS

oS

E

E

:z:

-30

/

:z:
-20

-10

•••••

..'

...v .//

:... ...

5

6

7

B

9

...

VOH (VOLTS)

VCC (VOLTS)

Output Sink Current for SOand SK

Output Sink Current lor LO- L7 and
Standard Drive Option lor 00- 03 and
GO-G3

20
DEVICE f
#2 AND #4
15

C[

:z:

E

-20

....'

.'

~]WCURRENT
h';;IN HIGH

I

i

..

'

I

I

..
.'

'

···l··r· .......

o

!

bEVICE. #1
A j b #1 AND c #1

IV"" 1-1""I1.....

9

10

o

5

1

2

3

Output Sink Current for GO- G3and
00- 03 (for High Current Option)

1.J

DEVICE.
#1
AND b #1
I
I
I
IMAX @VCC = 9.5 V

.. , ...........-

300

/

C[

200

I -I 1

~-tI-r-+--II--+--I--+-4--t--t

~

200

E

100

V

tV' m2"

-~

IMAX

VCC = .5 V
IMIN@VCC=9.5V

IMIN @VCC = 4.5 V

00~9::t2:r3::4~15--6L-17~--L-Jl0

o

o

1

2

3

4

5

6

VOL (VOLTS)

VDL (VOLTS)

1-106

4

6

VOL (VOLTS)

DEVICE. #1
AND b #1

E

IMIN@VCC =4.L

o~~~~~~~~~~

B

400

1-+-+-t--t-4r--+-+-+-t--l

I

It' /I..-r--;--r-

VOL (VOLTS)

C[

.1

1~IN~VCC=9.5V

I

I/VV

V

Output Sink Current
GO- G3 and 00- 03 with Very High
Current Option

~

IMAX@VCC=4.5 V t-j---

•

10

234567

Vcc (VOLTS)

300

~
I I I

f

TYTT
IMIN @VCC=

10

15 ~~,~-t-4r--+-~-r-t-4~
1
IMAX @VCC 9.5 V

..I.

~V' 11114.~
o

OPTION

20r-~,.~-r~~~;-~,-,
DEVICE. #1, b #1
d # r r f #10R9#1

I

/

IIV

I-tUR~ENT O~TION
.....' ....... /r
I ~~~WRLE~~

......
~::: ........

IMAX @VCC = 4.5 V

10

OPTION

~

-10

IMAX @VCC= 9.5 V

..

I - - r-- ~~~rD~IGH CURRENT I -

oS

ifc- f-

i .f.. ~

f

-40

-30

1

10

LED Output Direct Segment Drive
VOH = 2.0 V

1

IMIN

10

VOH (VOLTS)

-50

~

" , IMAX EIGHT
SEGMENTS ON-

f'"

':... ••••••
4

oyf-"

7

B

9

10

7

B

9

10

COP420U421L INSTRUCTION SET

Table 1 is a symbol table providing Internal architecture, instruction operand and operational symbols
used in the instruction set table.

Table 2 provides the mnemonic, operand, machine
code, data flow,. skip conditions and description
associated
with
each
Instruction
in
the
COP420U421 L instruction set.

Table 1. COP420Ll421L Instruction Set Table Symbols

Symbol

Symbol

Definition

PC

a
SA
SB
SC
SID

SK

Definition

INSTRUCTION OPERAND SYMBOLS
d
4-blt Operand Field, 0-15 binary (RAM Digit Select)
2·blt Operand Field, 0-3 binary (RAM Register
Select)
a
10-bit Operand Field, 0-1024 binary (ROM Address)
4-blt Operand Field, 0-15 binary (Immediate Data)
Y
RAM(s)
Contents of RAM location addressed by s
Contents of ROM locallon addressed by t
ROM(t)

INTERNAL ARCHITECTURE SYMBOLS
A
4·blt Accumulator
B
6-blt RAM Address Register
Br
Upper 2 bits of B (register address)
Bd
Lower 4 bits of B (digit address)
C
1·blt Carry Register
D
4·blt Data Output Port
EN
4·blt Enable Register
G
4·blt Register to latch data for G 110 Port
IL
Two 1·blt Latches associated with the IN3 or INO
Inputs
IN
4·blt Input Port
L
a-bit TRI·STATE 110 Port
M
4-blt contents of RAM Memory pOinted to by B
Register

OPERATIONAL SYMBOLS
+
Plus
Minus
Replaces
Is exchanged with
Is equal to
The ones complement of A
Exclusive·OR.
Range of values

10-blt ROM Address Register (program counter)
8-blt Register to latch data for L 110 Port
1()'blt Subroutine Save Register A
1()'blt Subroutine Save Register B
1()'bit Subroutine Save Register C
4·bit Shift Register and Counter
Loglc·Controlied Clock Output

"

1-107

· Table 2. COP.420U421 L InstructJon Set
Machine

Mnemonic Operand

Hex
Code

Lan~uage Code

." Binary)

Data Flow

Skip Conditions

Description

ARITHMETIC INSTRUCTIONS
ASC

30

100 1110 0 001

A + C + RAM(B) - A
Carry- C

Carry

Add with Carry, Skip on
Carry

ADD

31

1001 110 0 011

A + RAM(B)- A

None

Add RAM to A

ADT

4A

10 1 0011 0 1 01

A + 1010- A

None

Add Ten to A

A+y-A

Carry

Add Immediate, Skip on
Carry (y + 0)

AISC

,

,

5-

10101 1

CASC

10

1000110 0001

A+

RAM(B) '+ C-A·
Carry - C

Carry

Complement and Add
with Carry, Skip on Carry

CLRA

00

10 0 0 010 0 0 01

O-A

None

Clear A

COMP

40

10 1 00100001

'A-A

None

Ones complement of A to
A

NOP

44

10 1 0 010 1 001

None

None

No Operation

RC

32

1001 110 0 1 01

"O"-C

None

Reset C

SC

22

10 0 1 010 0 1 01

"1"-C

None

Set C

XOR

02

10 0 0 010 0 1 01

AlB RAM(B)-A

None

Exclusive·OR RAM with A

Y

y

I

TRANSFER OF CONTROL INSTRUCTIONS
JID

JMP

a

JP

a

FF

11 1 1 111 1 1 11

ROM (PC9:8,A,M) PC7:0

None

Jump Indirect (Note 3)

6-

10 11 0~0Ia9:81
I a7:0
I

a- PC

None

Jump'

86:0
I
111
(pages 2,3 only)
or

a - PC6:0

None

Jump within Page
(Note 4)

1111 a5:0
I
(all other pages)

a - PC5:0

None

Jump to Subroutine Page
(Note 5)

----

JSRP

a

JSR

a

-6-

1101

a5:0

I

PC+ 1-SA-SBSC
0010- PCg:6
a- PC5:0

10 1 1 Op 0la9:81
I a7:0
I

PC + 1 - SA - SB - SC None
a- PC

Jump to Subroutine

-RET

46

10 1 0 011 0 0 01

sc -

None

Return from Subroutine

RETSK

49

10100110011

SC-SB-SA-PC

Always Skip on Return

Return from Subroutine
then Skip

SB - SA - PC

1·108

o

o"tJ

Table 2. COP420U421 L Instruction Set (continued)
Machine
Mnemonic Operand

Hex
Code

Lan~Uage Code

Binary)

Data Flow

Skip Conditions

Description

CAMQ

A- Q7:4
RAM (B) - Q3:0

None

Copy A. RAM to Q

Q7:4 - RAM(B)
Q3:0- A

None

Copy Q to RAM, A

1001 r 101011

RAM(B)- A
Br .. r - Br

None

Load RAM into A,
Exclusive·OR Br with r

33
3C

1001 11 1100 1

CQMA

33

1001 1100111

2C

10010111001

LD

r

-5

LDD

r,d

LQID

1001 1100111

100 1 0100 1 11
I d I

RAM(r,d)- A

None

--

100 1 r

Load A with RAM pointed
to directly by r,d

BF

1101 1111 1 11

ROM(PC9:8,A,M) - Q
SB- SC

None

Load Q Indirect (Note 3)

23

RMB

0
1
2
3

4C
45
42
43

101
10 1
101
10 1

0011 100 1
0 010 1 0 1 I
0010010 1
0 010 0 1 1 I

0000-

RAM(B)O
RAM(B)1
RAM(B)2
RAM(B)3

None

Reset RAM Bit

5MB

0
1
2
3

40
47
46
4B

10100111011
10100101111
10 1 0 010 1 1 0 I
1010011 0 11 1

1111-

RAM(B)O
RAM(Bl1
RAM(B)2
RAM(B)3

None

Set RAM Bit

STII

Y

7-

101 111

I

y - RAM(B)
Bd + 1 - Bd

None

Store Memory Immediate
and Increment Bd

X

r

-6

1001 r 101101

RAM(B)- A
Br .. r - Br

None

Exchange RAM with A,
Exclusive·OR Br with r

XAD

r,d

23

None

Exchange A with RAM
pointed to directly by r,d

y

I

10 0 1 010 0 1 1
I d I

--

110 1 r

. RAM(r,d) -

A

XDS

r

-7

1001 r 101111

RAM(B)- A
Bd-1-Bd
Br .. r - Br

Bd decrements past 0

Exchange RAM with A
and Decrement Bd,
Exclusive·OR Br with r

XIS

r

-4

1001 r 101001

RAM(B)-A
Bd+1-Bd
Br .. r - Br

Bd increments past 15

Exchange RAM with A
and Increment Bd,
Exclusive·OR Br with r

Copy A to Bd

REGISTER REFERENCE INSTRUCTIONS
CAB

50

10 1 0 1100001

A- Bd

None

CBA

4E

10100111101

Bd - A

None

--

100 1 r (d -1)
(d - 0,9:15)
or

I

r,d - B

Skip until not a LBI

Load B Immediate with
r,d (Note 6)

33

--

1001 100111
110 1 r 1 d
(any d)

33
6-

10011100111
101 10 1 y I

y -. EN

None

Load EN Immediate
(Note 7)

12

joo011 0010 1

A-

None

Exchange A with Br

LBI

LEI

XABR

r,d

y

~
o

-o

r

MEMORY REFERENCE INSTRUCTIONS

I

.

Copy Bd to A

I

Br (0,0 - A3,A2)

1-109

o

"tJ

....r~

,...

...J

~
c..

o

-

Table 2. COP420Ll421 L Instruction Set (continued)
Machine
Mnemonic Operand

Hex
Code

Lan~Uage Code

Binary)

Data Flow

Skip Conditions

o

TEST INSTRUCTIONS

...J

SKC

20

100 1 0100001

C

C\I
"=t

SKE

21

100 1 01000 11

A

SKGZ

33

10011100111

G3:0

21

100 1 01000 11

33
01

100001000 11

o

c..

o
o

SKGBZ
0
1

SKMBZ

11

1001 11001 11

= "1"
= RAM(B)
=0

Description

Skip if C is True
Skip if A Equals RAM
Skip if G is Zero
(all 4 bits)

1st byte

Skip if G Bit is Zero
GO

},," '.'

=0
=0
=0
=0

2

03

100011000 11
10 0 0 010 0 1 11

3

13

10001100111

G3

0

01

100001000 11

RAM(B)O

1
2

11
03

1000 110 00 11
10000100 1 11

RAM(B)l
RAM(B)2

13

1000 110 0 1 11

RAM(B)3

41

10 1 001000 11

A time·base counter
carry has occurred
since last test

Skip on Timer
(Note 3)

3
SKT

Gl
G2

=0
=0
=0
=0

Skip if RAM Bit is Zero

INPUT/OUTPUT INSTRUCTIONS
ING

1001 11001 11
10010110101

G-A

None

Input G Ports to A

10011100111
10010110001

IN- A

None

Input IN Inputs to A
(Note 2)

1001 11 001 11
1001 011 001 1

IL3,CKO,"0",ILO - A

None

29

Input IL Latches to A
(Note 3)

33
2E

10011100111

L7:4 - RAM(B)
L3:0 - A

None

Input L Ports to RAM,A

10010111101

33

1001 1100111

Bd- 0

None

Output Bd to 0 Outputs

3E

1001 111 11 01

33

1001 110011 1
y
10101 1
I

y- G

None

Output to G Ports
Immediate

1001 11001 11
10011110101

RAM(B)- G

None

Output RAM to G Ports

3A
4F

10100111111

A-SIO, C- SK

None

Exchange A with SIO
(Note 3)

33
2A

ININ

33
28

INIL

33

INL

OBO

OGI

y

5OMG

XAS

33

,

Note 1: All subscripts for alphabetical symbo"ls indicate bit numbers unless explicitly defined (e.g., Sr and Bd are explicitly defined). Bits are numbered
o to N where a signifies the least significant bit (low-order, right-most bit). For example, A3 indicates the most significant (left·most) bit of the 4·bit A
register.
Note 2: The IN1 instruction is not available on the 24·pin COP421L since this device does not contain the IN inputs.
Note 3: For additional information on the operation of the XAS, JID, LQID, INIL, and SKT instructions, see below.
Note 4: The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two·page boundary of pages 2 or 3. The JP
instruction, otherwise, permits a jump to a ROM location within the current 64-word page. JP may not jump to the last word of a page.
Note 5: A JSRP transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of P). A JSRP may not be used when in pages 2 or 3.

JSRP may not jump to the last word in page 2.
Note 6: LSI is a single-byte instruction if d = 0,9,10, 11,12,13,14, or 15. The machine code for the lower 4 bits equals the binary value of the Old" data
minus 1, e.g., to load the lower four bits of B (Bd) with the value 9 (10012), the lower 4 bits of the LBI instruction equal 8 (10002), To load 0, the lower 4 bits

of the LBI instruction should equal 15 (11112)'
Note 7: Machine code for operand field y for LEI instruction should equal the binary value to be latched into EN, where a "1" or "0" in each bit of EN
corresponds with the selection or deselection of a particular function associated with each bit. (See Functional Description, EN Register.)

1-110

(')

o

The following information is provided to assist the
user in understanding the operation of ,several
unique instructions and to provide notes useful to
programmers in writing COP420U421L programs.

COP420l
ININ

1-

XAS Instruction
XAS (Exchange A with SIO) exchanges the 4·bit con·
tents of the accumulator with the 4·bit contents of
the SIO register. The contents of SIO will contain
serial·in/serial·out shift register or binary counter
data, depending on the value of the EN register. An
XAS instruction will also affect the SK output,
providing a logic controlled clock if SIO is selected
as a shift register or C - SK if SIO is selected as
binary counter. (See Functional Description, EN
Register, above.) If SIO is selected as a shift register,
an XAS instruction must be performed once every 4
instruction cycles to effect a continuous data
stream.

JID (Jump Indirect) is'an indirect addressing instruc·
tion, transferring program control to a new ROM
location pointed to indirectly by A and M. It loads the
lower B bits of the ROM address register PC with the
contents of ROM addressed by the 10·bit word, PCg: s,
A, M. PCg and PCa are not affected by this instruc·
tion.

I NIL Instruction'
INIL (Input IL Latches to A) inputs 2 latches, IL3 and
ILo (see figure 11) and CKO into A. The IL3 and ILo
latches are set if a low·going pulse ("1" to "0") has
occurred on the IN3 and INo inputs since the last INIL
instruction, provided the input pulse stays low for at
least two instruction times. Execution of an INIL
inputs IL3 and ILa into A3 and AO respectively, and
resets these latches to allow them to respond to subsequent low·going pulses on the IN3 and INo lines. If
CKO is mask programmed as a general purpose
input, an INIL will input the state of CKO into A2. If
CKO has not been so programmed, a "1" will, be
placed in A2. A "0" is always placed in A1 upon the
execution of an INIL. The general purpose inputs
IN3-INo are input to A upon the execution of an IN IN
instruction. (See table 2, ININ Instruction.) INIL is
useful in recognizing pulses of short duration or
pulses which occur too often to be read conveniently
by an ININ instruction. Available on COP420L only.
LQI D Instruction
LaiD (Load a Indirect) loads the B·bit a register with
the contents of ROM pointed to by the 10·bit word
PCg, PCa, A, M. LaID can be used for table lookup or
code conversion such as BCD to seven·segment. The
LaID instruction "pushes" the stack (PC + 1 - SASB - SC) and replaces the least significant B bits of
PC as follows: A - PC 7 :4 , RAM(B) - PC 3:0 , leaving
PCg and PCa unchanged. The ROM data pOinted to by
the new address is fetched and loaded into the a
latches. Next, the stack is "popped"(SC - SB - SA
- PC), restoring the saved value of PC to continue
. sequential program execution. Since LaID pushes
SB - SC, the previous contents of SC are lost. Also,

1-111

r-

"~
....I.

INll

Figure 10. INIL Hardware Implementation

when LaiD pops the stack, the previously pushed
contents of SB are left in SC. The net result is that
the co·ntents of SB are placed in SC (SB - SC). Note
that LaID takes two instruction cycle times to
execute.
SKT Instruction

Note that JID requires 2 instruction cycles.

-o
( ')

INO/IN3

a

JID Instruction

"o~

The SKT (Skip on Timer) instruction tests the state of
an internal 10·bit time·base counter., This counter
divides the instruction cycle clock frequency by 1024
and provides a latched indication of counter
overflow. The SKT instruction tests this latch,
executing the next program instruction if the latch is
not set. If the latch has been set since the previous
test, the next program Instruction is skipped and the
latch is reset. The features associated with this
instruction, therefore, allow the COP420U421 L to
generate its own time·base for real·time processing
rather than relying on an external input signal.
For example, using a 2.097 MHz crystal as the time·
base to the clock generator, the instruction cycle
clock frequency will be 65 kHz (crystal frequency.,. 32)
and the binary counter output pulse frequency will be
64 Hz. For time·of·day or similar real·time processing,
the SKT instruction can call a routine which incre·
ments a "seconds" counter every 64 ticks.
Instruction Set Notes
a. The first word of a COP420U421L program (ROM
address 0) must be a CLRA (Clear A) instruction.
b. Although skipped instructions are not executed,
one instruction cycle time is devoted to skipping
each byte of the skipped instruction. Thus all
program paths take the same number of cycle
times whether instructions are skipped or
executed.
c. The ROM is organized into 16 pages of 64 words
each. The Program Counter is a 10·bit binary
counter, and will count through page boundaries.
If a JP, JSRP, JID or,LalD instruction is located in
the last word of a page, the instruction operates
as if it were in the next page. For example: a JP
located in the last word of a page will jump to a
location in the next page. Also, a LaiD or JID
located in the last word of page 3, 7,11, or 15 will
access data in the next group of 4 pages,

r-

..J
.,..

OPTION LIST .

l

The COP420Ll421L mask-programmable options are
assigned numbers which correspond with the
COP420L pins.

-~
8
. .J

a.

o

o

The foilowlng is a list of COP420L options. When
specifying aCOP421L chip. Options 9. 10. 19. and 20
must ail be set to zero. The options are programmed
at the same time as the ROM pattern to provide the
user with the hardware flexibility to in.terface to
various 110 components using' little or no external
circuitry.
Option 1 = 0: Ground Pin":" no options available
Option 2: CKO Output
= 0: clock generator output to crystallresonator
(0 not ailowable value if Option 3 = 3)
= 1: pin is RAM power supply (VR) input
=2: general purpose input. load device to Vee
::: 3: general purpose Input. hlgh-Z
= 4: niulti-COP SYNC Input (CKI .... 32. CKI + 16)
= 5: multi-COP SYNC input (C~I .,. 8)
Option
= 0:
= 1:
= 2:
= 3:

3: CKI Input
oscillator Input divided by 32 (2 MHz niax)
oscillator Input divided by 16 (1 MHz max)
osciilator Input divided by 8 (500 kHz max)
single-pin RC controiled oscillator divided
by 4
.

Option 4: .RESET Input
= 0: load device. to Vee
= 1: HI-Z input
Option
=.0:
= 1:
= 2:

5: L7 Dr.lver
Standard output
Open-drain output
High current LED direct segment drive
output
=3: High current TRI-STATE push-puil output
= 4: Low-current LED direct segment drive
output
= 5: Low-current TRI-STATE push-puil output

Option 13: L2 Driver
same as Option.5
Option 14: L1 Driver
same as Option 5
Option 15: La Driver
same as Option 5
Option 16: SI Input
same as Option 9
Option
;= 0:
. = 1:
.= 2:

17: SO Driver
standard output
op.en-draln output
push-puil output

"option 18: SK Driver
\ same as Option 17
Option 19: INa Input
same as Option 9
Option 20: IN3 Input
same as Option 9
Option
= 0:
= 1:
=2:
= 3:
= 4:
= 5:

21: Go 1/0 Port
very-high 'current standard output
very-high current open-drain output
high current standard output
high current open-drain output
standard LSTTL output (fanout = 1)
open-draln LSTTL output (fanout = 1)

Option 22: G1 110 Port
same as Option 21
Option 23: G2 1/0 Port
same as Optio~ 21
Option 24: G3 1/0 Port
same as Option 21
Option 25: D3 Output
same as Option 21

Option 6: y, Driver
same as Option 5

Option 26: D2 Output
same as Option 21

Option 7: L5 Driver
same as Option 5

Option 27: Dl Output
same as Option 21

Option 8: ~ Driver
same as Option 5

Option 28: Do Output
sanie as Option 21

Option 9: .INI Input
=0: load device to Vee
= 1: Hi-Z input

Option 29: L Input Levels
= 0: standard TTL input levels
. ("0" =0.8V. "1"=2.0V)
= 1: .higher voltage input levels
("0" = 1.2V."1" =3.6V)

Option 10: IN2 Input
same as Option 9
Option 11: Vee pin
.= 0: . 4.5 V to 6.3 V operation
. = 1: 4.5V to 9.5V operation

ciPtlO~ 12: L3 Driver
same as Option 5

Option 30: IN Input Levels
same as Option 29
Option 31: 'G Input Levels'
same as Option 29
Option 32: 51 Input Levels
same as Option 29

1-112

Option
= 0:
= 1:
=2:

33: RESET Input
Schmitt trigger input
standard TIL input levels
higher voltage input levels

Figure 7 shows an interconnect diagram for a
COP420L used as a general controller. Operation of
the system is as follows:

Option 34: CKO Input Levels (CKO = input;
Option 2 = 2,3)
same as Option 29

1_ The L,- La outputs are configured as LED Direct
Drive outputs, allowing direct connection to the
segments of the display.

Option 35: COP Bonding
= 0: COP420L (28-pin device)
= 1: COP421L (24-pin device)

2. The 0 3 - Do outputs drive the digits of the multiplexed display directly and scan the columns of
the 4 x 4 keyboard matrix.

APPLICATION #1: COP420L General Controller

3. The INa-INo inputs are used to input the 4 rows of
the keyboard matrix. Reading the IN lines in conjunction with the current value of the 0 outputs
allows detection, debouncing, and decoding of
anyone of the 16 keyswitches.
TEST MODE (Non-Standard Operation)

4. CKI is configured as a single-pin oscillator input
allowing system timing to be controlled by a
single-pin RC network. CKO is therefore available
for use as a VR RAM power supply pin_ RAM data
integrity is thereby assured when the main power
supply is shut down.

The SO output has' been configured to provide for
standard test procedures for the customprogrammed COP420L. With SO forced to logic "1,"
two test modes are provided, depending upon the
value of SI:

b. ROM Test Mode (SI = 0)

5. SI is selected as the input to a binary counter
input. With SIO used as a binary counter, SO and
SK can be used as general purpose outputs.

These special test modes should not be employed by
the user; they are intended for manufacturing test
only.

6. The 4 bidirectional G I/O ports (Ga-G o) are
available for use as required by the user's application.

a. RAM and Internal Logic Test Mode (SI = 1)

33V

I

....IIo....l

..... JlVR
CKO

113BATTERIES
NICAD sl VCC

LO

Vcc.

8 SEGMENT
DATA LINES

L7

~

~

..>-

CKI

:::

BBBB

GND

GND

~

-=

4·DI.G IT
LED DISPLAY

COP420L
DOr-Dl
D3
D4

~

f'-.

~

~

I'-

I'-

'-

I'-

~
I'-

~
I'-

'-

I"-

'-

I'-

INO

4GENERAL~
liD

EVENT
COUNTER
INPUT'

~O
INl

G3

-

IN2
SI
IN3
SK

SO

L.:

2 GENERAL OUTPUTS'

* SO. SI. SK MAY ALSO BE USED FOR SERIAL 110
Figure 7_ COP420L Keyboard/Display Interface

1-113

4x4
KEYSWITCH
MATRIX

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......

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APPLICATION #2: Digitally Tuned Automotive
Radio Controller and Clock

-

Figure 8 shows the COP420L interconnect diagram
for a digitally tuned AM/FM car r.adio with digital
clock LEO display and 4 x 6 keyboard for storage and
recall of station, search up and search down or scan
up and scan down of stations, AM/FM select and
time setting and display. Operation of the system is
as follows:

a..
o
o

1. The OS8907 uses a 4.0MHz crystal to provide the
time base for frequency synthesis and the 500 kHz
time base for operation of the COP420L and the
50Hz signal for the timekeeping function.

oo

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~

3. A switched 5V supply that goes high whim the
radio is turned on goes to the Vee pin of the
OS8907 for the frequency generating circuitry and
to the G1 1/0 pin of the COP420L.
4. L1 through 4; are outputs to the keyboard (push·
pull options selected) and INo through IN4 are the
keyboard inputs (pullup to Vee and high trip levels
selected).
5. SK provides the clock and SO provides the data to
the MM5450 display driver with serial input and to
the OS8907 PLL synthesizer. L7 is the enable pin
for the MM5450 and Go (standard option selected)
is the enable line for the OS8907.

2. An unswiiched 5V supply goes to the VeeM pin of
th.e OS8907 for the operation of the oscillator and
divide·down for the 500kHz and 50Hz signals. It
also provides Vee for the COP420L so the time·
keeping channel storage and last station selected
data are not lost when the ignition is off.

l

GNO
INO

VCC
G2

6. In the search up and search down operations, G2
informs the COP420L when a station has been
detected.

KEYBOARO

-=

SEARCH
UP

Ml

Gl

,-51

SCAN
UP
FAST

INI

M2

SCAN
UP
SLOW

IN2

MJ

SCAN
OOWN
FAST

IN3
Ll

M4

STORE

TIME

COP420L

,..-

CKI

-

GO
SK
SO

L7

L6

L5

L4

LJ

L2

II I

SEARCH
OOWN

+

I

SLOW

5SEC
OISPLAY

SET
MIN
SET
HR

J 1

f

SWITCHEO
B+

~

DISPLAY

~

"=?"
BRlhTNESS
ENABLE

SCAN
DOWN

AM/FM

,.

MM5450

t

OATA
CLOCK

t

tt

ri°~Z

ENABLE
500'kHz

OS0907
PLL SYNTHESIZER

50Hz
VCCM

VCC

GNO

t

~

Figure 8. Electronically Tuned Radio System

1-114

f::
f::
fo-

VARACTOR CPO OUT
AM/FM BANOSWITCH
LOCAL/OISTANT
STEREO
MUTE·

SWITCHEO 5V (RADIO)
UNSWITCHEO 5V

~National

PRELIMINARY

~ Semiconductor

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COP444L/445L Single-Chip N-Channel Microcontrollers

o

General Description

Features

The COP444L and COP445L Single-Chip N-Channel
Microcontrollers are members of the COPSTM family,
fabricated using N-channel, silicon gate MOS
technology. These controller oriented processors are
complete microcomputers containing all system
timing, internal logic, ROM, RAM and 1/0 necessary
to implement dedicated control functions in a variety
of applications. Features include single supply
operation, a variety of output configuration options,
with an instruction set, internal architecture and 1/0
scheme designed to facilitate keyboard input,
display output and BCD data manipulation. The
COP445L is identical to the COP444L, but with 191/0
lines instead of 23. They are an appropriate choice
for use in numerous human interface control environments. Standard test procedures and reliable highdensity fabrication techniques provide the medium
to large volume customers with a customized controller ,oriented processor at a low end-product cost.

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•
•
•
•
•
•
•
•
•
•

Low cost
Powerful instruction set
2kxB ROM, 12Bx4 RAM
23 1/0 lines (COP444L)
True vectored interrupt, plus restart
Three-level subroutine stack
15f's instruction time
Single supply operation (4.5-6.3V)
Low current drain (11 mA max @ 5V)
Internal time-base counter for real-time
procesing
• Internal binary counter register with
MICROWIRETM serial 1/0 capability
• General purpose and TRI-STATE@ outputs
• LSTILICMOS compatible in and out
• Direct drive of LED digit and segment lines
• Softwarelhardware compatible with other
members of COP400 family
•. Extended temperature range device to be
available (-40'C to +B5'C)
• Wider supply range (4.5-9.5V)
optionally available

GND

~,
TlME·BASE
COUNTER

(DlVIDEBV1024\

25

D,
D,
D,
DO

11

J.LEVElSTACK

SK

G,
G,
G,

If0 CONTROLS

Go

--,

I
I
I

SI

I

so

I
!i
20109

6

1

8

12

13

14

15

19

IN3 INZ INI INa

L7

La

LS

L4

L3

LZ

Ll

LO

Figure 1. COP444L1445L Block Diagram

1-115

~
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Absolute Maximum Ratings
Voltage at Any Pin Relative to GND
Ambient Operating Temperature
Ambient Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Power Dissipation

- 0.3V to + 10V
O·Cto +70·C
-65·Cto +150·C
300·C
0.75 Watt at 25 ·C
0.4 Watt at 70·C

Absolute maximum ratings indicate limits beyond which
damage to the device may occur. DC and AC electrical specifications are .not ensured when operating the device at absolute
maximum ratings.

DC Electrical Characteristics O·C" TA "
Parameter

+ 70·C, 4.5V" Vee "9.5V unless otherwise noted.

Conditions

Operating Voltage (Veel

Note 1

Operating Supply Current

Vee =5V, TA =25·C.
(all inputs and outputs open)

Min

Max

Units

4.5

9.5

V

11

rnA

0.4

V
V
V

0.6

V
V

0.6

Y
V

3.0

V

0.8

V
V
V

1.2

V
V

0.4

V
V

0.2

V
V

Input Voltage Levels
CKI Input Levels
Crystal Input
Logic High (V 1H )
Logic High (Y 1H)
Logic Low (V 1L)

3.0
2.0

Vee =9.5V
Vee = 5V ±.10%

Schmitt Trigger Input (+4)
Logic High (VIH)
Logic Low (V 1L)

0.7 Vee

RESET Input Levels
Logic High
Logic Low

0.7 Vee

RESET Hysteresis

1.0
·2.0

SO Input Level (Test mode)
All Other Inputs
Logic High
Logic High
Logic Low

Vee =9.5V
with TTL trip level options
selected, Vee=5V±10%

3.0
2.0

Logic !-ligh
Logic Low

with high trip level options
selected

3.6

Output Voltage Levels
LSTTL Operation
Logic High (VOH )
Logic Low (VoLl
CMOS Operation
Logic High ..
Logic Low

Vee=5V±5%
10H = -25,..A
10L =0.36mA

V

2.7

10H= -10,..A
10L= 10,..A

Vee- 1

Note 1: Vee voltage change must be less than O.5Vlms to maintain proper operation.

1.-116

()

DC Electrical Characteristics

(continued) O·C .;; T A';; + 70·C, 4.5V';; Vee';; 9.5V unless otherwise noted.

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~

Parameter

Conditions

Min

Max

Units

SO and SK Outputs {loll

Vee =9.5V, VOL=1.0V
Vee =4.5V, VoL =1.0V

4.5
2.2

22
11

mA
mA

Lo- L7 Outputs and
Standard Size GO-G 3 and
Do- D3 Outputs (loll

Vee =9.5V, VOL =1.0V
Vee =4.5V, VOL=1.0V

2.0
1.0

9.0
4.5

mA
mA

GO-G 3 and Do- D3 Outputs
with High Current Options
(I OL)

Vcc =9.5V, VOL=1.0V
Vee=4.5V, VOL=1.0V

15
7.0

75
35

mA
mA

GO-G 3 and Do-D3 Outputs
with Very High Current
Options (loll

Vee =9.5V, VoL =1.0V
Vee = 4.5V, VOL=1.0V

30
15

150
75

mA
mA

Vee =9.5V, VoH =4.75V
Vee=4.5V, VoH =2.25V
Vee =9.5V, VOH =4.75V
Vee=4.5V, VoH =2.25V

-70
-26

-450
-190

-1.45
-0.07

-15.5
-2.8

"A
"A
mA
mA

LED Configuration,
Lo- L7 Outputs, Low
Current Driver Option
(I0H)

Vee =9.5V, VoH =4.75V
Vee =4.5V, VoH =2.25V

-1.5
-1.5

-15
-9.0

mA
mA

LED Configuration,
Lo-L7 Outputs, High
Current Driver Option
(I OH )
TRI·STATE Configuration,
Lo- L7 Outputs, Low
Current Driver Option
(IOH)

Vee = 9.5V, VOH=2.0V
Vee = 6.0V, VOH = 2.0V

-3.0
-3.0

-30
-20

mA
mA

Vee =9.5V, VoH =4.75V
Vee=4.5V, VoH =2.25V

-2.4
-0.06

24.5
3.8

mA
mA

Vee =9.5V, VoH =4.75V
Vee =4.5V, VoH =2.25V

-4.9
-0.12

-47.5
-8.1

mA
mA

3.0

mA

+10

"A

Output Source Current:

Push·Pull Configuration,
SO and SK Outputs (lOH)

TRI·STATE Configuration,
Lo- L7 Outputs, High
Current Driver Option
(I0H)
CKO Output
RAM Power Supply Option
Power Requirement'

()

Output Sink Current

Standard Configuration,
All Outputs (lOH)

t

r-

Output Current Levels

VR =3.3V

TRI·STATE® Output Leakage
Current

-10

1·117

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AC Electrical Characteristics o~c,,; TA ";

oo

Instruction Cycle Time -

...J

CKI Using Crystal

-3

'. Parameter

Input Frequency -

Conditions

.

te

fl

C-

oo

..

+ 70'C, 4.5V ";Voo ,,;9.5V unless otherwise speoified .

+32 mode
+ 16 mode
+8 mode

Duty Cycle

Min

Max

Units

15

40

Jis

0.8
0.4
0.2

2.091'
1.0
0.5 .

MHz
MHz
MHz

30

55

%

0.8
0.4
0.2

2.097
1.0
0.5

MHz
MHz
MHz

CKI Using External Clock
Input Frequency --, fl

+32 mode
+16 mode
+8 mode

30

Duty Cycle
Rise Time

fl = 2.097 MHz

Fall Time
CKI Using RC (Option 3 = 3)

60

%

120

ns

80

ns

25

I'S '

R =51 kQ ±5%, C = 100pF± 10%
+4 mode
15

Instruction Cycle Time
CKO asSYNC Input

400

t SyNe

ns

INPUTS:
IN 3 -IN o, G3 -G O' L7- L o
tSETUP
t HOLO

..,'.

8
600

I'S
ns·

'.

SI
I'S
ns

2'
600

tSETUP
t HOLD

,"

OUTPUTS:
COP TO CMOS PROPAGATION
DELAY
All Standard Output
Configurations
tpD1
SO, SK Outputs
t pD1 (push-pull)
t pDo

VOH =0.7 Vee. VOL = 0.3 Vee.
CL = 50pF

,

0 3 -0 0 • G3 -G O
t pDO
L7-Lo
t pDo
tpD1 (standard size push·pull)
tpD1 (high current push·pull)
L7 - Lo LED Direct Drive Outputs
t pD1 (standard size)
tpD1 (high current)

6.0V"; Vee"; 9.5V. VOH = 2.0V
CL =50pF

1-118

6.5

I'S

4.0
1,,2

I'S.
I'S

2.7

I'S

2.7
3.0
2.5

I'S
I'S
I'S

5.0
4.5

I'S
I'S

o

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AC Electrical Characteristics (continued)
oDC';; TA';; + 70 DC, 4.5V';; Vce';; 9.5V unless otherwise specified.
Conditions

Parameter
COP to LSTTL Propagation
Delay

Min

Max

Units

SO, SK Outputs
t pOl (standard)
tpOl (push·pull)
t poo

5
3.5
3

L7 - La Outputs
tpOl (push'pull)

1.5

L7 - La, G3-G O' 0 3- Do Outputs
tpOl (standard)
tpoo

5.0
5.0

GN'

2B

CK'
CK'

17

D1

"2S

D1
Dl
GJ
G2
GI
GO
1N3

ArnT
17
16
l5
L4

COP444L
9

'N'
'N2

10
11
12
13
14

Vee
13
L2
LI

24
23
22
21
10
19
18

'NO

DO

OK'
OK'

mu
17
16
l5
L4

11

so

16

51

IS

LO

CDP445L

13
L2
LI

24
2l

DO
D1

22

D1
Dl
GJ
G2

21
10
19
18
11

vee

'NO
SK

."GO

16

"

IS

11

14
13

12

SK

so
51

LO

Figure 2. Connection Diagrams

Description

Pin

Pin

Description

L7 -La

8 bidirectional 1/0 ports with
TRI·STATE'"

G3-G O

4 bidirectional 1/0 ports

0 3-0 0

4 general purpose outputs

IN3-INo

4 general purpose inputs (COP420L only)

RESET

Serial input (or counter input)

Vee

Power supply

SO

Serial output (or general purpose output)

GND

Ground

SK

Logic·controlled clock (or general
purpose output)

SI

CKI

System oscillator input

CKO

System oscillator output (or general
purpose input, RAM power supply or
SYNC input»
System reset Input

CKI

S~i~~:

Gl'G~~~;~~~:
CKD&SI

"'47v..L_==_~,":-..J

_ ......_"

_..;.._ _ _ _ _ _~--.l-tSETUP-lI-,....tH;;;O;,;;LO;;.----

r.I X ----+1

INPUTS

X'-_____

tpDl

G~;~&.~b.~~

"VOH

OUTPUTS

Figure 3. Input/Output Timing Diagrams (Crystal Dlvlde·by·16 Mode)

-I

I-!WD

CKI

CKD
(INPUT)

CKI

='

I--!WI

-U

I

I-ISYN. C

.'

I

tPO~tPDO

\'----~""""'l"---. . . .----

Figure 3b. CKO Output Timing

Figure 3a. SYllchronization Timing

1-119

tr-

oo

Vee=5V±5%, VoH =2.7V
VOL = 0.4V, CL = 50pF

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8

FUNCTIONAL DESCRIPTION
A block diagram of the COP444L Is given In figure 1.
Data paths are illustrated In simplified form to depict
how the various logic elements communicate with
each other in implementing the instruction set of the
device. Positive logic is used. When a bit Is set, it is a
logic "1" (greater than 2 volts). When a bit is reset, It
is a logic "0" (less than 0.8 volts).

Program Memory
Program Memory consists of a 2048 byte ROM. As
can be seen by an examination of the'COP444L1445L
Instruction set, these words may be program
instructions, program data or ROM addreSSing data.
Because of. the special characteristics associated
with the JP, JSRP, JID and LaiD instructions, ROM
must often be thought of as being organized into 32
pages of 64 words each.
ROM addreSSing Is accomplished by a 11-bit PC
register. Its binary value selects one of the 2048 8-bit
words contained In ROM. A new address is loaded
into the PC register during each instruction cycle.
Unless the instruction is a transfer of control instruction, the PC register is loaded with the'next
sequential 11-bit binary count value. Three levels of
subroutine, nesting are implemented by the 11-blt
subroutine save registers, SA, SB and SC, providing a
last-in, first-out (UFO) hardware subroutine stack.
ROM instruction words are fetched, decoded and
executed by the Instruction Decode, Control and
Skip L:ogic circuitry.

Data Memory
Data memory conslsts,of a 512-bit RAM, organized as
8 data registers of 16 4:bit digits. RAM addreSSing is
implemented by a 7-bit B register whose upper 3 bits
(Br) select 1 of 8 data registers and lower 4 bits (Bd)
select 1 of 16 4-blt digits In the selected data register.
While the 4-bit contents of the selected RAM digit (M)
is usually loaded Into or from, or exchanged with, the
A register (accumulator), it may also be loaded into
or from the a latches or loaded from the L ports. RAM
addressing may also be performed directly by the
LDD and XAD instructions based 'upon the 7-blt
contents of the operand field of these instructions.
The Bd register also serves as a source register for
4-bit data sent directly to the 0 outputs.

Internal Logic
The 4-bit A register (accumulator) is the source and
destination register for most 1/0, arithmetic, logic
and data memory access operations. It can also be
used to load the Br and Bd portions of the B register,
to load and input 4 bits of the 8-bit a latch data, to
Input 4 bits of the 8-bit L I/O port data and to perform
data exchanges with the SIO register.
A 4-bit adder performs the arithmetic and logic functions, storing its results in A. It also outputs a carry
bit to the 1-blt C register, most ,often employed to
Indicate arithmetic overflow. The C register, In
conjunction with the XAS Instruction and the EN
register, also serve,s to control the SK output. C can

be outputted directly to SK or can enable SK to be a
sync clock each instruction cycle time. (See XAS
Instruction and EN register description, below.)
Four general-purpose inputs, IN 3 -lN o, are provided.
The 0 register 'provides 4 general-purpose outputs
and Is used as the destination register for the 4-bit , ,
contents of Bd. The 0 outputs can be directly connected to the digits of a multiplexed LED display. '
The Greglster contents are outputs to 4 generalpurpose bidirectional I/O ports. G I/O ports can be
directly connected to the digits of a multiplexed LED
display.
The a register Is an internal; latched, 8-bit reglste~,
used to hold data loaded to or from M and A, as well
as 8-bit data from ROM. Its contents are output to the
L I/O ports when the L drivers are enabled under
program control. (See LEI Instruction.)
The 8 L drivers,when enabled, output the contents of
latched a data to the L I/O ports. Also, the contents
of L may be read directly into A and M. L I/O ports can
be directly connected to the segments of a multiplexed LED display (using the LED Direct Drive
outp!)t configuration option) with CI data being
outputted to the Sa-Sg and decimal point segments
of the display.
The SIO register functions as a 4-bit serlal-in/serlalout shift register or as a binary counter depending on
the contents of the EN register. (See EN register
description, below.) Its contents can be exchanged
with A, allowing it to Input or output a continuous
serial data stream. SIO may also be used ,to provide
additional parallel I/O by connecting SO to external
serial-in/parallel-out shift registers~
The XAS Instruction copies C into the SKL latch. In
the counter mode, SK is the output of SKL; in the
shift register mode, SK outputs SKL ANDed with the
clock.
The EN register is an Internal 4-bit register loaded
under program contol by the LEI Instruction. The
state of each bit of this' register selects or deselects
the particular feature associated with each bit of the
EN register (EN 3- EN o).
1. The least significant bit of the enable register,
EN o, selects the SIO register as either a 4-bit shift
register or a 4-bit binary counter. With ENo set, SIO
is an asynchronous binary counter, decrementing
its value by one upon each low-going pulse ("1" to
"0") ocurrlng on the SI input. Each pulse must be
at least two instruction cycles wide. SK outputs
the value ofSKL. The SO output 15 equal to the
value of EN 3 . With ENo reset, SIO Is a serial shift
register shifting left each instruction cycle time.
The data present at SI goes into the least significant bit of SIO. SO, can be enab.led to output the
most significant bit of 510 each cycle time. (See 4
below.) The SK output becomes 'a logic-controlled
clock.
"
2. With EN1 set the INl input 15 enabled as an interrupt input Immediately follOWing an Interrupt, EN1
is reset to disable further interrupts.

1-120

(")

3. With EN2 set, the .L drivers are enabled to output
the data in 0 to the Lila ports. Resetting EN2
disables the L drivers, placing the Lila ports in a
high-impedance input state.

c. Upon acknowledgement of an interrupt, the skip
logic status is saved and later restored upon
popping of the stack. For example, if an interrupt
occurs during the execution of ASC (Add with
Carry, Skip on Carry) instruction which results in
carry, the skip logic status is saved and program
control is transferred to the interrupt servicing
routine at hex address OFF. At the end of the
interrupt routine, a RET instruction is executed to
"pop" the stack and return program control tothe
instruction following the original ASC. At this
time, the skip logic is enabled and skips this
instruction because of the previous ASC carry.
Subroutines and LOID instructions should not be
nested within the interrupt service routine, since
their popping the stack will enable any previously
saved main program skips, interfering with the
orderly execution of the interrupt routine.

4. EN 3, in conjunction with ENe, affects the SO
output. With ENo set (binary counter option
selected) SO will output the value loaded into EN 3.
With ENo reset (serial shift register option
selected), setting EN3 enables SO as the output of
the SIO shift register, outputting serial shifted
data each instruction time. Resetting EN3 with the
serial shift register option selected disables SO as
the shift register output; data continues to be
shifted through SIO and can be exchanged with A
via an XAS instruction but SO remains reset to
"0." The table below provides a summary of the
modes associated with EN3 and EN o.

Enable Register Modes - Bits EN3 and ENO
EN3

ENe

510

51

50

0

0

Shift Register

Input to Shift Register

0

5K
If SKL = 1, SI<
If SKL

0

1

Shift Register

Input to Shift Register

Serial Out

If SKL
If SKL

0

1

Binary Counter

Input to Binary Counter

0

If SKL
If SKL

1

1

Binary Counter

Input to Binary Counter

1

If SKL
If SKL

= CLOCK
= 0, SK = 0
= 1, SK = CLOCK
= 0, SK = 0
= 1, SK = 1
= 0, SK = 0
= 1, SK = 1
= 0, SK = 0

Interrupt
The following features are associated with the IN1
interrupt procedure and protocol and must be considered by the programmer when utilizing interrupts.

d. The first instruction of the interrupt routine at hex
address OFF must be a Nap.
e. A LEI instruction can be put immediately before
the RET to re-enable interrupts.

a. The interrupt, once acknowledged as explained
below, pushes the next sequential program
counter address (PC + 1) onto the stack, pushing
in turn the contents of the other subroutine-save
registers to the next lower level (PC + 1 ~ SA ~ SB
~ Se). Any previous contents of SC are lost. The
program counter is set to hex address OFF (the
last word of page 3) and EN1 is reset.

Initialization

b. An interrupt will be acknowledged only after the
following conditions are met:
1 . EN1 has been set.

2. A low-going pulse ("1" to "0") at least two
instruction cycles wide occurs on the IN1 input.
3. A currently executing instruction has been·
completed.
4. All successive transfer of control instructions
and successive LBls have been completed (e.g.,
if the main program is executing a JP instruction which transfers program control to another
JP instruction, the interrupt will not be acknowledged until the second JP instruction has been
executed.

The Reset Logic will initialize (clear) the device upon
power-up if the power supply rise time is less than
1 ms and greater than 1 flS. If the power supply rise
time is greater than 1 ms, the user must provide an
external RG network and diode to the RESET pin as
shown below. The RESET pin is configured as a
Schmitt trigger input. If not used it should be
connected to Vcc. Initialization will occur whenever a
logic "0" is applied to the RESET input, provided it
stays low for at least three instruction cycle times.

1-121

P
0

Vee

w
E
R
S
U

P
P
l
Y

liRESET
[WO

AC;o 5 ~ POWER SUPPL Y RISE TIME

Note: If power-low failsafe option is selected, the RC and
diode circuit is not used.
Power·Up Clear Circuit

o'"'0
~
~
~

-o
r-

( ")

'"'0

t

(J1

r-

...I

l
o.

-3
o

. ..I

-.:r

c..
oo

Upon Initialization, the PC register is cleared to 0 (ROM
address 0) and the A, B, C, D, EN, and G registers are
cleared. The SK output is enabled as a SYNC output,
providing a pulse each instruction cycle time. Data
Memory (RAM) is not cleared upon initialization. The
first instruction at address 0 must be a CLRA.

c. RC Controlled Oscillator. CKI is configured as a
single pin RC controlled Schmitt trigger oscillator.
The· instruction cycle equals the oscillation
frequency divided by 4. CKO 'is available .as 'the
RAM power supply (V R) or as a general purpose
Input.

Oscillator

d. Externally Synchronized Oscillator. Intended for
use in multi·COP systems, CKO Is programmed to
function as an input connected to ttie SK output of
.another COP chip operating at the sarile
frequen'cy (COP chip with Lor C suffix) with CKI
connected as shown. In this configuration, the SK
output connected toCKO must provide a SYNC
(instruction cycle) signal to CKO, thereby allowing
. synchronous data transfer between the COPs
using only the SI and SO· serial 110· pins In
conjunction with the XAS instruction. Note that on
power·up SK is automatically enabled as a SYNC
output (See Functional Description, Initialization,
above).

There are fourba~lcclock oscillator configurations
..
available as shown by figure 4.
a. Crystal.Controlled Oscillator. CKI and CKO are
connected to an external crystal. The Instruction
cycle time equals the crystal frequency divided by
32 (optional by 16 or 8).

b.

External Oscillator. CKI is an external clock input
signal. The external frequency is divided by 32
(optional by 16 or 8) to give the instruction cycle
time. CKO is now available to be used as the RAM
power supply (V R), as a general purpose Input, or
.
as a SYNC input.

(SYNC)
CKI .

CKO
R2

CKO

CKO

t

VCC
(VR OR GENERAL
PURPOSE INPUT
PINI

.J'1.r

EXTERNAL
CLOCK

COP444L/445l

(VR OR GENERAL
PURPOSE INPUT
OR SYNC PIN)

Crystal Oscillator

RC Controlled Oscillator

Crystal
Value

Component Values
C1 (pF)
R1
R2

455kHz

16k

1M

80

80

2.097 mHz

1k

1M

56

6-36

C2 (pF)

R (kQ)

C(pF)

Instruction
Cycle Time
In /lSI

!?1
82

100
.56

19±15%
19±13%

Figure 4. COP444L/445L Oscillator

1·122

o

o

CKO Pin Options
In a crystal controlled oscillator system, CKO is used
as an output to the crystal network. As an option
CKO can be a SYNC input as described above. As
another option CKO can be a general purpose input,
read into bit 2 of A (accumulator) upon execution of
an INIL instruction. As another option, CKO can be a
RAM power supply pin (V R), allowing its connection
to a standbylbackup power supply to maintain the
integrity of RAM data with minimum power drain
when the main supply is inoperative or shut down to
conserve power. Using either option is appropriate in
applications where the COP444L1445L system timing
configuration does not require use of the CKO pin.

1/0 Options
COP444U445L outputs have the following optional
configurations, illustrated in figure 5:
a. Standard an enhancement mode device to
ground in conjunction with a depletion-mode
device to Vee, compatible with LSTTL and CMOS
input requirements. Available on SO, SK, and all D
and G outputs.
b. Open· Drain - an enhancement-mode device to
ground only, allowing external pull-up as required
by the user's application. Available on SO, SK, and
all D and G outputs.
c. Push· Pull An enhancement-mode device to
ground in conjunction with a depletion-mode
device paralleled by an enhancement-mode device
to Vee. This configuration has been provided to
allow for fast rise and fall times when driving
capacitive loads. Available on SO and SK outputs
only.
d. Standard L - same as a., but may be disabled.
Available on L outputs, only.
e. Open Drain L - same as b., but may be disabled.
Available on L outputs only.
f. LED, Direct Drive - an enhancement·mode device
to ground and to Vee, meeting the typical current
sourcing requirements of the segments of an LED
display. The sourcing device is clamped to limit
current' flow. These devices may be turned off
under program control (See Functional Descrip'
tion, EN Register), placing the outputs in a highimpedance state to provide required LED segment
blanking for a multiplexed display. Available on L
outputs only.
g. TRI-STATE® Push-Pull - an enhancement-mode
device taground and Vee. These outputs are TRISTATE outputs, allowing for connection of these
outputs to a data bus shared by other bus drivers.
Available on L outputs only.
COP444UCOP445L inputs have the following optional
configurations:

Minimum and maximum current (lOUT and VOUT)
curveI' are given in figure 6 for each of these devices
to allow the designer to effectively use these 1/0
configurations in designing a COP444U445L system.
The SO, SK outputs can be configured as shown in a.,
b.,or c. The D and G outputs can be configured as
shown in a. or b. Note that when inputting data to the
G ports, the G outputs should be set to "1." The L
outputs can be configured as in d., e., f. or g.
An important point to remember if using configuration d. or f. with the L drivers is that even when the L
drivers are disabled, the depletion load device will
source a smail amount of current (see figure 6, device
2); however, when the L-lines are used as inputs, the
disabled depletion device can not be relied on to
source sufficient current to pull an input to logic "1".

Power· Low Failsafe Option
If this option is selected, an on·chip level detection
circuit will force the RESET pin low and reset the
chip while the power, supply Is stili within the
operating range. Reset will occur with Vee between
4.5 and 7.5 volts, allowing normal system operation
between 7.5 anti 9.5 volts.

RAM Keep·Aive Option
Selecting CKO as the RAM power supply (VR) allows
the user to shut off the chip power supply (Vecl and
maintain data in the lower four (r = 0,1,2,3) registers
of RAM., To Insure that RAM data integrity is
maintained, the following conditions must be met:
1. RESET must go low before Vee goes low during
power off; Vee must go high before RESET goes
high on power-up.
2. VR must be within the operating range of the chip,
and equal to Vee ± 1 V during normal operation.
3. VR must be .. 3.3V with Vee off.

COP445L
If the COP444L is bonded as a 24-pin device, it becomes the COP445L, illustrated in figure 2, COP444LI
445L Connection Diagrams. Note that the COP445L
does not contain the four general purpose IN inputs
(lN3-INo). Use of this option precludes, of course,
use of the IN options and the interrupt feature, which
uses IN 1 • All other options' are available for the
COP445L.

h. An on-chip depletion load device to Vee.
i. A Hi-Zinput which must be driven to a "1" or "0"
by external components.
The above input and output configurations share
common enhancement-mode and depletion-mode
devices. Specifically, all configurations use one' or
more of six devices (numbered 1- 6, respectively).

1-123

"'0

t

-o
r-

o

"'0

~

r-

....I
II)

3

CL.

o
2
....I

a. Standard Output

!

b. Open',Draln Output,

CL.

o

DISABLE~_

o

IX-,

~l'

(AIS DEPLeTlDN DEVICE)

f. LED (L Output)

e. Open·Drain L Output

d. Standard L Output

Vcc

.-I~

INPUT~{

#6

"'"'~f
g. TRI·STATE'" Push· Pull (L Output)

i. HI·Z Input

h. Input with Load
Flgure,5. Output Configurations

Current for Inputs with Load
'Device

Input Current for Lo through 'L7 '
when Output Programmed Off
by Software

'

-IUUU

-100

DEVICE d #2
AND 1#2

'-90
-80

j

....
~

~

§

"

E

'\

-50

o

~

-200
-100

-2U

, -15

"1'1\.I\.

IMAX@VCC=9,5V

ts

IMAX@
cc = 4.5V

I-' ,,\b~MjN @

.'I\.

Vc~= .5V

if,~ J/~MIN
Vec = 9.5

!"

o t-t-~~~

~Io..

I.U·

3

2.0

4

5

6

1

VO H (VOLTS)

Source Current for Lo through
L7 in TRI·STATE·, Configura·
tion (High Current Option)

Source Current for SO and SK
In Push· Pull Configuration,

-15

~

VI/O

V IN (VOLTS)

'-'-'-'-"-""""""'T'....,..-'r....,

I'\.

~N~VCr~·5

U

-400
-300

IMIN@VCC= 9.5V

-IU

-20

E

'\

-600

:z: ,-5UU

I MAX}
VCC: 4.5V

-30

9.5

j

I'\.

"

-40

-20

1.0 2.0 3.0 4.0 5.0 6.U 1.U 8.U

-800
, -100

r\.

-60

DEVICE. #2
ANf d #2

-9UU

I\. 'MAX @Vcc: 9.5V

-10

j

Source Current for Standard
Output Configuration

8

"'"

9.5

Source Current for Lo through
L7 in TRI·STATE'" ,Configura·
tion (Low Current Option)

r-rT'rtr-...,.,............,.......,......,.....,

1-+-11--+\--+--+-11-

<

<

E

E

..s:z:

~

-10

1--HrJ--'\+-/-I-It-+-+-/-i

-5

23456,1
VOH (VOLTS)

VOH (VDLTS)

1·124

10

2 ,3

4

5

6

VOH (VOLTS)

I,

8

9

10

o

LED Output Source Current
(for High Current LED Option)

o"U

LED Output Direct Segment
Drive
High Current Options on Lo·L 7
Very High Current Options on
on 0 0.0 3 or GO·G3

LED Output Source Current
(for Low Current LED Option)

t

r(;

-50

-20

OEVICE f #2 ANO #4

o

A~O DEV1ICE. OR b #1

-40

...s

-30

..

.s

'"
E

'"

E

-15

...s

-10

E'"

4

VO~

5

6

7

B

9

10

1

20
VOH = 2.0 V

E'"

-

-20

:r~rO~IGH CURRENT

.'
.......

-10

V
........
~MAXEIGHT
..... ...... . ' " . SEGMENTS ON
IMIN
I
I
::::" .......

/CJw

...s

I-

fl

CURRENT

10

-'

E

OPTION

•

.... ......
•

7

B

10

9

10
VCC (VOLTS)

Output Sink Current for Lo·L7
and Standard Drive Option for
0 0.03 and GO·G 3

i

/r!1;:;;N'HIGH
CURijENT O~TION
f-~MIN LOW
CIiWRENT OPTION

o
10

I

I

I

DEVICE. #1. b #1
f #10R9#1

I

IN AX @.~~r'F'Y ......
.'
~EVICE' #1
'.'

15

J

..

..

ANID b #1 AND c #1

.s

1

3

4

5

6

Output Sink Current
GO·G3 and 0 0.°3 with Very
High Current Option
400 r-'T""""'T""'"T"'-r.....,-r-..-...-'"T"'"""1

E

11
rJ/
o

7

B

9

10

IMAX@VCC=4.5Vr--

/f-t-

1-+-+-1--1--1-+-+-+--1--1

'"

o

200

I--tf+-+--M is internally bonded to Vee in the COP451.)

•
•
•
•
•

Low power
Low cost
Directly interfaces up to 8k RAM or 32k ROM
Single supply operation (2.5V-6V)
Protects external RAM data when processor power
turned off

• Compatible with all COP400 processors
(processor Vee" 9.5V)
• Small (20-pin) dual-in·llne package for COP451
• MICROWIRE compatible serial 110

Address and Read/Write commands are entered serially
into 01 clocked by SK when CSishigh. Data is read and
written in 64-bit groups. A write enable latch - not reset
by CS - is set or reset by a write enable, or write disable
command, so that incorrect data at SK and 01 (which
might occur while the COPS microcontroller is powering up or down) cannot change data stored in RAM.
The COP450/COP451 and a CMOS RAM may be used for
low power backup memory in a COPS system. The
COP450 and a ROM or PROM may be used for large
look-up tables.

Vee

I
f-- Vee
DI

•I

11-81T ADDRESS REGISTER

SK

CS

-

~~
---I
ADDRESS
COUNTER

I

f-- GND

WRITE
ENA8LE
LATCH
8-81T DATA REGISTER,

00

DI

-

--I

SK

-

-

CS

- -1,

•I

11-81T ADDRESS REGISTER

I

WRITE
ENA8LE
LATCH
6-81T
ADDRESS COUNTER

I

GND

COP450 Block Diagram"

COP451 Block Diagram

1-136

0

0
(Asl As
(A'I A,
(A.I A,
01
SK
CS

I,

Ui

10

Vee

11

{AJI AO
(Ad Al

12
13

(AS I A,

"

A7 (Al0)

As
A,

20
19

As (A11)

A.

18
17

28
27
26
25
2.
23
22

A. (A,)

2'
20
19
18

I,
I,
GNO

DI

A, (EOI
AiO (Ei)

Aii(Wi

13
12

GNO
A,
A,

11

Ao

14

10

As

~

CJ1

52
0

EO
Ei
Vi

16
15

SK
CS
Vee
A,
A,

"tJ

A,
AlO
Al1

0

"tJ
~

CJ1

.....

iTIiM

17

DO (A,I
IdA,1

'6
15

16 (An)

COP450

COP451

(Pin names in parenthesis are used
if the COP450 is accessing RAM)

Pin

Description

Vee
GND

Positive power supply

CS

Negative supply pin

Ao"'A11

Memory address outputs

ROM

ROM operation select input

10"'17

ROM data inputs
Dynamic ROM address load output

Chip select input

DI

Serial data input

LD

SK

Serial clock input

EO. E1

Enable RAM outputs

DO

Serial data output

W

Write RAM output

Instruction Set

(ROM =Vecl

0

1

E1

Eo

A11

A 10

Ag

As

A7

A6

Write to RAM

0

E1

Eo

A11

A10

Ag

As

A7

A6

Read RAM

0

1

0

0

X

X

X

X

X

X

X

X

Write Enable

0

0

0

X

X

X

X

X

X

X

X

Write Disable (Protect)

0

0

A11

A10

A7

A6

A5

A4

A3

Read from ROM

(ROM=GND)
Ag

As

Vee (RAMI
Vee (CPUI

Vee (ROM)

Vee

1

.1
AD"" Att

01

COP.20

~~

12

4kxB

ROM

COP420

SI

~

COP450 System Diagram

01
SK
SO
SII-

CS
SK COP4S1
01

~

J
E,
CS

E,
Ao "" A1\

w

IT

COP451 System Diagram

1-137

I

CS
4kxl
RAM

12

R/W

DATA,.
OATAOUT

r-

~
o

COPS™ Peripheral
Product Brief
PRELIMINARY

o

COP452 Frequency/Counter Peripheral
General Description

Features

The COP452 is a peripheral member of the COPSTM
family fabricated using N-channel silicon·gate MOS
technology. Containing 2 independent 16·bit counter!
register pairs, it is well suited to a wide variety of tasks
involving the measurement and!or generation of times
and!or frequencies. Included are multiple tones, precise
duty cycles, event counting, waveform measurement,
"white noise" generation, and A·DID-A conversions. An
on·chip zero·crosslng detector can trigger a pulse with a
programmed delay and duration.

• Compatible with ailCOP400 processors
• MICROWIRETM compatible serial 110

vee

• 14·pin package
• Single supply operation (4.5·6.3V)
• Low Cost
• Crystal or external clock (25kHz to 4.4 MHz)
•
•
•
•
•
•

TTL compatible
User programmable
True zero crossi ng detect
17 stage pseudo random white noise Qenerator
Wider supply· range (4.5·9.5V) optionally available
Extended temperature range device to be available
(-40°Cto +85°C)

GND

CKI CKO

~
01--+-.........

cs _+-+-..:.:;RE;,:S,:.;ET,-,

COUNTER CLOCK

.....-t-t-OA

SK-+-+---~----~-'----~

INB
ENB

ZI

--:~:~:::::::r=='r--jr-t""p.1'--_ _~--.;.;;....!

.....-t--t-OB

--1------1

ZO--+--~---CI--~

DO

COP452 Block Diagram

1-138

n

COP452
Connection Diagram

Pin

Description

01

Serial data input

SK
CS

Chip select input

Serial clock input

ZO-1
OA- 2
INB- 3
ENB- 4
OB- 5

\J

Vcc- 6
CKO- 7

14-ZI
13-00
12-01
II-SK
10-CS
9 -GNO
B-CKI

0

"

~

CJ1

COP452 Instruction Set

0 000 0
0

o0

0 1

I\)

LDRB Load Register B from 01
LORA Load Register A from 01

0 0 0 1 0

RDRB Read Register B

0 0 0 1 1

RDRA Read Register A

DO

Serial data output

Vee

Power supply

GND

Ground

CKI
CKO

Crystal input
Crystal output

0 0 1 1 0

RDCB Read Counter B

OA

Output from counter A

0 0 1 1 1

RDCA Read Counter A

OB

Output from counter B

0 1 0

INB

External input to counter B

ENB

Enable input INB

ZI

AC waveform input

ZO

Square wave output of ZI

0 0 1 0 0

LDCB Load Counter B from Register B

o

LDCA Load Counter A from Register A

0 1 0 1

o0

CK4

CKI Divide By Four

0 1 0 0 1

CK1

CKI Divide By One

LDM

Load Mode Latches

1

XXXX

•

Pulse Measurement

Mode Description
•

Dual Frequency
OA outputs a square wave of width A

Counter A counts the pulse width high on INB

OB outputs a square wave of width B

Counter B counts the pulse width low on INB

INB J - A - + - B : = = !

L

L

• Triggered Pulse
OB--.3- 8

==1-- 8- '

OA outputs a pulse of width B triggered by ZI
crossing zero delayed by A.

A = contents Counter A
B = contents Counter B
•

Frequency and Count
OA outputs a square wave of width A
Counter B counts external pulses on INB

•

Dual Count
Counter A counts pulses on ZI
• Triggered Pulse and Count

Counter B counts pulses on INB
•

OA outputs a pulse triggered by ZI delayed by A.

Number of Pulses

Counter B counts INB

OA outputs a square wave of width A for B
number of pulses
•

• White Noise and Frequency
OA outputs white noise

Duty Cycle

OB outputs a square wave of width B

OA outputs a duty cycle wave form of width
high = A and width low = B

• White Noise and Duration
OA outputs white noise for duration B

L

•

1-139

RESET

~
~

o(J

~National

~ Semiconductor
COP41O V.F. Display Driver
General Description

Features

The COP470 is a peripheral member of National's
COPSTM Microcontroller family. It is designed to directly
drive a multiplexed Vacuum Fluorescent display. Data is
loaded serially and held in internal latches. The COP470
has an on·chip oscillator to multiplex four digits of eight
segment display, and may be cascaded and/or stacked
to drive more digits, more segments, or both.

• Directly interfaces to multiplexed 4 digit by 8
segment Vacuum Fluorescent displays
• Expandable to drive 8 digits andlor 16 segments
• Compatible with all COP400 processors
• Needs no refresh from processor
• Internal or external oscillator
• No "glitches" on outputs when loading data
• Drives large and small displays
• Programmable display brightness
• Small (20 pin) dual·in·line package
• Operates from 4.5 V to 9.5 V
• Outputs switch 35 volts and require no external
resistors

With the addition of external drivers, the COP470 also
provides a convenient means of interfacing to a large·
digit LED display.

• Static latches
• Microwire™ compatible serial 1/0

Connection and Block Diagrams

sc

SA
SB
"

so

20

SE

so

19

Sf

so

sa

18

SA

17

SH

OSC

16

NOT USED

15

"G

COP47D

VDD

01

SK

lOS

vss

10

14

D4

13

03

12

02

11

01

3

SE
SO

2

SG
Sf

01
8H

1 20 19 18 17

osc

03
02

04

11 12 13 14

Figure 1. COP470 Pin
Connection

01-'-+---,---------1

..!.Voo

SK~-----------~~~--,

..l!VGCl

IOS-q--------------~-~~---~

Figure 2. COP470 Block Diagram

1·140

.lI!vss

(')

Absolute Maximum Ratings

o

Electrical Characteristics

(Vss = 0)

'"tJ

Voltage at Display Outputs ......... +0.3Vto -35V
Voltage at All Other Pins ........... +0.3V to -20V
Operating Temperature ............. 0·Cto +70·C
Storage Temperature ........... -65·Cto +150·C
Lead Temperature (10 Seconds) ............. 300·C

Vss = 0, Voo = -4.5V to -9.5V, VGG = -30V to -35V,
TA = 0 to 70·C unless otherwise specified.

D. C. Electrical Specifications
Min.

Max.

Unit

-9.5
-35

-4.5
Voo

Volts
Volts

5
1

rnA
rnA

+0.3
-4.0

V
V

Power Supply Voltage
Voo
VGG
Power Supply Current
100
IGG (Display Blanked)
Input Levels
V1H
V1L

-1.5
-10.0

Output Drive
10H @ VoH =Vss -3V
10H @ VoH =Vss -2V
IOL @ VOL = VGG + 2V
Output Drive
IOH

10
7
10

rnA
rnA
,.,A

1

rnA

@ VGG = VDD = Vss - 5V

@ VoH =Vss -2V

A. C. Electrical Specifications
osc Period

(internal or external)

4

OSC Pulse Width

20

1.5

Clock Period T (twice OSC period)

,.,Sec
,.,Sec

8

40

,.,Sec

390
190

2000
1000

Hz
Hz

SK Clock Frequency

0

250

SK Clock Width

1.5

Display Frequency
4 digits = 1/64 T
8 digits = 1/128T

Data Set·up and Hold Time
t set·up
thold

kHz
,.,Sec

1.0
50

,.,Sec
nSec

1.0
1.0

,.,Sec
,.,Sec

CS Set·up and Hold Time
t set·up
t hold
Duty Cycle
4 digits
8 digits

1164
11128

15/64
15/128

Input Capacitance

7

pF

Input Leakage

1

,.,A

1-141

~
o

:e
'II1I:I"

Timing Diagram

Il.

--I 1__ CS SETUP
1- ,'I-SK WIDTH

oo

,
~---,

,

I I
SK

I0

DI~I01

--I

--SETUP
...,- !--HDLD

Figure 3. Serial Load Timing Diagram

Typical Performance Characteristics
-24
-20

""E

%

-16
-12
-8

-4
-2 -4

-6

-8 -10 -12 -14

VOH VOLTS
OUTPUT SOURCE CURRENT

Functional DeSCription
The fifth and sixth bits control the multiplex digits. To
enable the COP470 to drive a 4 digit multiplex display,
set both bits to one. If two COP470s are used to drive an
8 digit display, bit five is set on the left COP470 and bit
six is set on the right COP470 (see Fig. 6). In the eight
digit mode, the display duty cycle is on time/128.

Segment Data Bits
Data is loaded in serially in sets. Each set of segment
data is in the following format:

I SA I SB I SC I SO I SE I SF I SG I SH I
Data is shifted into an eight bit shift register. The first
bit of the data is for segment H, digit 1. The eighth bit is
segment A, digit 1.

The seventh bit selects internal or external oscillator.
The OSC pin of the COP470 is either an output of the
'internal oscillator (bit 7 = 0) or is an input allowing the
COP470 to run from an external oscillator (bit 7 = 1).

A set of eight bits is shifted in and then loaded into the
digit one latches. The second set of 8 bits is loaded into
digit two latches. The third set into digit three latches
and the fourth set is loaded into digit four latches.

The eighth bit is set to synchronize two COP470s. For
example, to set the COP470 to internal osc, 4 digits, and
maximum brightness, send out six ones and two zeros.

Display on Time and Control Bits
The fifth set of 8 data bits contains blank time data and
control data in the following format:
Display Digits
I

Sync

Ext. I Right

Left 1 . . - On Time _

Osc. 14 of 814 of81 LSB

I

I MSB I

the first four bits shifted in contain the on time. This is
used to control display brightness. The brightness is a
function of the on time of each segment divided by the
total time (duty cycle). The on time is programmable
from 0 to 15 and the total time is 64. For example, if the
on time is 15, the duty cycle is 15/64 which is maximum
brightness. If on time is 8, the duty cycle is 8/64, about
1/2 brightness. There are 16 levels of brightness from
15/64 to 0/64 (off).

Figure 4. System Diagram -

1-142

4 Digit Display

o

o"'tJ

.I=ao
.....

o

64T
T __
11-15T_1
ANY SEGMENT

~

U

ON

~

01J

ON

OFF

L-_

ON

__________________

~r----

ON TIME = 15
(MAX BRIGHTNESS)

02
03
041

I-BT-l-BT-I
ANY SEGMENT.

ON

OFF

ON

ON
) ON TIME=B

01~

1 _ 1 5 T - J I-T
ANY SEGMENT

n

n

L-____________~n~

____ )
.

01~

ON TIME=l

Figure 5. Segment and Digit Output Timing Diagram

Loading Sequence:

3.

Step
Turn CS Low.
2
3

Clock in 8 bits of data for digit 1.
Clock in 8 bits of data for digit 2.

4.

4
5

Clock in 8 bits of data for digit 3.
Clock in 8 bits of data for digit 4.

6

Clock in 8 bits of data for on time and control
bits.
Turn CS high.

5.
6.
7.

7

8.

Note: CS may be turned high after any step. For ex~le, to
load only 2 digits of data do steps 1,2,3, and 7. CS must
make a high to low transition before loading data in order to
reset internal counters.

Shift in 4 bits of on time, a zero and three ones.
This synchronizes both chips, sets to external
oscillator, and to right four of eight digits. Thus
both chips are synchronized and the oscillator
is stopped ..
Turn CS high to both chips.
Turn CS low to the left COP470.
Shift in 32 bits of data for the left 4 digits.
Shift in 4 bits of on time, a one and three zeros.
This sets this COP470 to internal oscillator and
to left four of eight digits. Now both chips start
and run off the same oscillator.
Turn CS high.

The chips are now synchronized and driving eight digits
of display. To load new data simply load each chip
separately in the normal manner.

8 Digit Displays

16 Segment Display

Two COP470s may be tied together in order to drive an
eight digit multiplexed display. This is shown in Figure
6. The following is the loading sequence to drive an
eight digit display using two COP470s.

Two COP470s may be tied together in order to drive a
sixteen segment display. This is shown in Figure 8. To
do this, both chips must be synchronized, one must run
off external oscillator while the other runs off its
internal oscillator outputting to the other. Similarly, four
COP470s could be tied together to drive eight digits of
sixteen segments.

1.
2.

Turn CS low on both COP470s.
Shift in 32 bits of data for the right 4 digits.

1·143

~'

8

D.

DIGIT VF OISPLAY

oo

SA. S8, SC, SO, SE, SF, SG, P

01 02 03 04

-{)
8

I

SEGMENTS

I

SA-SH

SA-SHl

8)

COP470
(CHIP A)

-

SO

1

SK
CONDO

COP470
(CHIP

sKI

011

D5 06 07 08

cSI

SK

011

CS

I

00
01

Figure 6. System Diagram 8 Digit Display

---,

01

--fD2l

---,

r--I

CHIP A

r--L

CHIPA

03

I""CiiiPn

04

CHIP A

01

CHIP B

02

CHIP B

03

CHIP B

04

CHIP B

II
II

.--,
r-l

r---l~

SEGMENT CHIP A

r

.--,

__________________

~r---1~

________~S~EG~M~EN~T~CH~IP~B________~~~____~II~

_____________

RESULTANT SEGMENT
SEG. ,CHIP A & SEG. CHIP 8 WIRED TOGETHER

Figure 7. Segm"nt and Digit Output Timing Diagram for 8
Digits

4 DIGIT, 16 SEGMENT
YF DISPLAY

/~

~
l8,j

B
SEG.

SEG.

SA-SH

SA-SH

01 02 03 04
COP47D
01
SK

cs

-

SO
SK
cOP
400

-

00

1

I

1

I

OSC_

III
04 03 02 01
COP47D

01 SK
I

I

I

01

Figure 8. System Diagram lor t6 Segm!mt Display

1-144

_____

cs

LED Display
The COP470 may be used to drive LED displays. The
COP470 can drive the segments directly on small, low
current LED displays as shown in Figure 9. By adding

display drivers, large, high current LED displays can be
driven as shown in Figure 10.

Example:
COP420 Code to Load COP470
(Display Data is in Memory 0, 12 -

LOOP:

0, 15)

LB10,12

; Point to first display data

aBO

; Turn CS low (DO)

CLRA
LaiD

: Look up segment data

caM A

; Copy data from a to M.& A

SC
XAS
Nap

; Set C to turn on SK
; Output lower 4 bits of data

Nap

; Delay

; Delay

LD

; Load A with upper 4 bits

XAS
Nap

; Output 4 bits of data
; Delay

Nap

; Delay

RC

; Reset C

XAS

; Turn off SK clock

XIS

; Increment B for next data

JP LOOP

; Skip this jump after last digit

SC

; Set C

CLRA
AISC 15

; 15 to A

XAS
Nap

; Output on time (max brightness)

CLRA
AISC 12

; 12 to A

XAS
Nap

; Output control bits

LB10,15

; 15 to B

RC

.; Reset C

XAS

; Turn off SK

OBD

; Turn CS high (DO)

1-145

~
~

Q.

0
0

6.0 TO ·9.5V

VSS

COP420L

SO

01

SK

SK

DO

CS

COP470

Voo

-=-

VGG

-=-

-=-

·SEGMENT BUFFER MAY BE ADDED
FOR LARGER DISPLAYS

Figure 9. LED Display

V+
Vee

Vss
4 DIGITS

CDP42D

SO

DI

SK

SK

DO

CS

4 DIGIT
VERY LARGE
LED DISPLAY
(COMMON CATHODE)

CDP47D

GND

-=-

-=-=Figure 10. Large LED Display

+5 VOLTS
FUTABA 4-BT-03
422

r

l-Il-I • '-Il-I
1 Il I • 1 Il I
12 10

B

5

6

2 13~14 11

3

1

r!!-4

9L

+5 vtTS

DO
COP420

SO
SK

A

B C 0

E F

G H

D1 '02 D3 D4

cs
01

CDP410

SK
Voo

1-

1Figure 11. Sample V.F. System

1-146

~- -20 VOLTS
~ +5 VOLTS

(')

~National

PRELIMINARY

0

"'tJ

~ Semiconductor

~
N

COP472 Liquid Crystal Display Controller
General Description

Features

The COP472 Liquid Crystal Display (LCD) Controller is a
peripheral member of the COPS™ family, fabricated
using CMOS technology. The COP472 drives a multi·
plexed liquid crystal display directly. Data is loaded
serially and is held in internal latches. The COP472
contains an on·chip oscillator and generates all the
multi·level waveforms. for backplanes and segment
outputs on a triplex display. One COP472 can drive 36
segments multiplexed as 3x 12 (4'12 digit display). Two
COP472 devices can be used together to drive 72
segments (3 x 24) which could be an 8'12 digit display.

• Direct interface to TRIPLEX LCD
• Low power dissipation (100!,W typ.)
• Low cost
• Compatible with all COP400 processors
• Needs no refresh from processor
• On-chip oscillator and latches
• Expandable to longer displays
• Software compatible with COP470 V.F. Display
Driver chip
• Operates from display voltage
• MICROWIRe M compatible serial 1/0
• 20-pin dual-in-line package

BPA BP, BPe

SA, SB,

sc,

SA, SB,

sc,

SA, S8,

sc,

SA, SB,

sc,

VDD

GNO

01 -1-:------1
SK--~-----~-~

~--r_----------~~-------~

COP472 Block Diagram

1-147

Absolute Maximum Ratings
. Voltage at CS, DI, SK pins
Voltage at all other Pins
Operating Temperature Range
Storage Temperature
Lead Temperature (Soldering, 10 Seconds)

Electrical Characteristics

-0.3V to +9.5V
- 0.3V to VDD + 0.3V
O'Cto 70'C
-65'Cto +150'C
300'C

=ov,

=

GND
VDD 2.4V to 5.5V,
TA 0 'C to 70 'C (depends on display characteristics)

=

D.C. Electrical Specifications
Min.

Max.

Units

Power Supply Voltage, VDD

Parameter

Conditions

2.4

5.5

Volts

Power Supply Current, IDD

30

60

iJ. A

Input Levels
DI, SK, CS
VIL
VIH
BPA (as Osc. In)
VIL
V1H

0.7VDD

0.8
9.5

Volts
Volts

VDD-0.6

0.6
VDD

Volts
Volts

Output Levels,BPC (as Osc. Oat)
VOL
VOH

VDD-0.4

0.4
VDD

Volts
Volts
Volts
Volts
Volts
Volts

Backplane Outputs (BPA, BPB, BPC)
VBPA, BPB, BPC ON
VBPA, BPB, BPC OFF
VBPA, BPS, BPC ON
VBPA, BPB, BPC OFF
Segment Outputs (SA1 '" SA4 )
VSEG ON
VSEG OFF
VSEG ON
VSEG OFF

During
BP+ Time

1/, VDD - 0.1

During
BP- Time

0
2/,VDD - 0.1

VDD
+ 0.1
0.1
2faVDD+0.1

During
BP+ Time

0
2faVDD - 0.1

0.1
2faVDD + 0.1

Volts
Volts

During
BP- Time

1/, VDD - 0.1

VDD
+ 0.1

Volts
Volts

VDD - 0.1

VDD - 0.1

1j, VDD

1j, VDD

Internal Oscillator Frequency

60

110

Frame Time (Int. Osc,

3.4

6.4

ms

4

250

kHz

-i-

384)

SK Clock Frequency
SK Width

kHz

1.7

iJ.s

1.0
100

iJ.s
ns

1.0
1.0

iJ.S
iJ.S

DI
Data Setup, tSETUP
Data Hold, tHOLD
CS
tSETUP
tHOLD
Output Loading Capacitance

100

1·148

pF

o

COP472
Connection Diagram

SB'
SC,

20

SA.
SA'
SC'
BPB
BPC
BPA
SK
SC'
SC2
SA'

SB'

18
17

Voo

'6
'5

cs

GNO
01
SA2
SB'
SB2

14

13

'0

'2
11

Description

Pin

'9

o"tJ
~

CS

Chip select

VDD
GND
DI

Power supply (display voltage)
Ground
Serial data input

SK

Serial clock input

BP A

Display backplane A(or oscillator in)

BP B

Display backplane B

BP c
SA1 evSC4

Display backplane C (or oscillator out)
12 multiplexed outputs

N

Figure 2. Connection Diagram

cs-l

cs

LCSSETUP

--,~ rSKWIDTH

HOlO

----lI

r--

r

I I
SK

Figure 3. Serial Load Timing Diagram

osc
VDD
BPA

o

t

VDD
BPB 213

'f,
o
VDD

8pe

S81

SCl

:f:

E

:::~~~ _ _ _....

o
VDD
¥,
SEGMENT 113

o

Figure 4. Backplane and Segment Waveforms

D

SAl

LI~8I=1A

.:r.

C

SP

1if

Figure 5. Typical Display Internal Connections
Epson LD-370

1·149

BPB

Functional Description

Segment Data bits

The COP472 drives 36 bits of display information organized as twelve segments and three backplanes. The
COP472 requires 40 information bits: 36 data and 4 con·
trol. The functiori of each control bit is described below.
Display information format is a function 01 the LCD
interconnections. A typical segment/backplane configuration is illustrated in Figure 5, with this configuration
the COP472 will drive 4 digits of 9 segments.

Data is loaded in serially, in sets of eight bits. Each set
of segment data is in the following format:
I SA I SB I SC I SO I SE I SF I SG I SH I
Data is shifted into an eight bit shift register. The first
bit of the data is for segment H, digit 1. The eighth bit is
segment A, digit 1. A set of eight bits is shifted in and
then loaded into the digit one latches. The second set of
8 bits is loaded into digit two latches. The third set into
digit three latches, and the fourth set is loaded into digit
four latches.

To adapt the COP472 to any LCD display configuration,
the segment/backplane multiplex scheme is illustated, in
Table 1.
Two or more COP472 chips can be cascaded to drive ad·
ditional segments. There is no limit to the number of
COP472's that can be used as long as ihe output loading
capacitance does not exceed specification.

Control Bits
The fifth set of 8 data bits contains special segment
data and control data in the following format:
ISYNCI Q7

Table 1. COP472 Segment/Backplane Multiplex Scheme
Data to
Numeric Display

Bit Number

Segment, Backplane

1
2
3
4
5
6
7
8

SA1, BPC
SB1, BPB
SC1,BPA
SC1, BPB
SB1, BPC
SA1, BPB
SA1,BPA
SB1, BPA

SH
SG
SF
SE
SO
SC
SB
SA

9
10
11
12
13
14
15
16

SA2,BPC
SB2, BPB
SC2, BPA
SC2, BPB
SB2, BPC
SA2,BPB
SA2, BPA
SB2,BPA

SH
SG
SF
SE
SO
SC
SB
SA

17
18
19
20
21
22
23
24

SA3,BPC
SB3, BPB
SC3,BPA
SC3, BPB
SB3, BPC
SA3,BPB
SA3, BPA
SB3, BPA

SH
SG
SF
SE
SO
SC
SB
SA

25
26
27
28
29
30
31
32

SA4, BPC
SB4, BPB
SC4,BPA
SC4, BPB
SB4, BPC
SA4, BPB
SA4, BPA
SB4,BPA

SH
SG
SF
SE
SO
SC
SB
SA

Digit 4

33
34
35
36
37
38
39
40

SC1, BPC
SC2, BPC
SC3, BPC
SC4,BPC
not used
06
07
SYNC

SP1
SP2
SP3
SP4

Digit 1
Digit 2
Digit 3
Digit4

, 06

I X

,SP4 I SP3' SP2 I SP1 I

The first four bits shifted in contain the special character
segment data. The fifth bit is not used. The sixth and
seventh bits program the COP472 as a stand alone LCD
driver or as a master or slave for cascading COP472's.
BPC of the master is conected to BPA of each slaye.
The following table summarizes the function of bits six
and seven:

07

Digit 1

06

o
o

o

Digit 2

0

BPC Output

BPA Output

Slave

Function

Backplane
Output

Oscillator
Input

Stand Alone

Backplane
Output

Backplane
Output,

Internal
Osc. Output

Oscillator
Input

Internal
Osc. Output

Backplane
Output

'Not Used
Master

The eighth bit is used to synchronize two COP472's to
drive an 81f2·digit display.
Loading Sequence to Drive a 4 V2 ·Digit Display
Steps:
Digit 3

1. Turn CS low.
2. Clock in 8 bits of data for digit 1.
3. Clock in 8 bits of datafor digit 2.
4. Clock in 8 bits of data for digit 3.
5. Clock in 8 bits of data for digit 4.
6. Clock in 8 bits of data for special segment and control
function of BPC 'and BPA.

I 0 , 0 , 1
7. TurnCS high.

I 1 ,SP4, SP3 , SP2 , SP1 I

Note: CS may be turned high after any step. For example
to load only 2 digits of data, do steps 1, 2, 3, and 7.
CS must make a high to low transition before loading
data in order to ,reset internal counters:
Loading Sequence to Drive an aV2-Digit Display
Two or more COP472's may be connected together to
drive additiof)al segments. An eight digit multiplexed dis·
play is shown in Figure 7. The following is the loading se·
quence to drive an eight digit display using two COP472's.
The right chip is the master and the left the slave.

1-150

(')

Vee

7. Shift in four bits of special segment data, a one and
three zeros.
! 0 ! 0 ! 0

This sets the master COP472 to BPA as a normal
backplane output and BPC as oscillator output. Now
both the chips start and run off the same oscillator.

COP420

SO

GNO

! 1 !SP4!SP3!SP2!SP1!

1------1
SK 1------1
00 1------1

DISPLAY
VOLTAGE

L..--r--~

Figure 6. System Diagram -

4V2 Digit Display

8. Turn CS high.
The chips are now synchronized and driving 8 digits of
display. To load new data simply load each chip separately in the normal manner, keeping the correct status
bits to each COP472.

Steps:
1. Turn CS low on both COP472's.
2. Shift in 32 bits of data for for the slave's four digits.

Vee

3. Shift in 4 bits of special segment data: a zero and.
three ones.
.

Voo

! 1 ! 1 ! 1 ! 0 ! SP4! SP3! SP2 ! SP1 !
This synchronizes both the chips and BPA is oscillator input. Both chips are now stopped.

COP420
SOr---~+-;_---~
SKI----~;_----~

4. Turn CS high to both chips.
5. Turn CS low to master COP472.
6. Shift in 32 bits of data for the master's 4 digits.

Voo

OOr:::::::::~
GNO

01

I-

_____J

'---.----'

Figure 7_ System Diagram - 8% Digit Display

Example Software
Example 1.
COP420 Code to load a COP472 [Display data is in M(O, 12)-M(O, 15), special segment data is in M(O, 0)]

LOOP:

LBI 0, 12
OBD
CLRA
LOID
COMA
SC
XAS
NOP
NOP
LD
XAS
NOP
NOP
RC
XAS
XIS
JP LOOP
SC
LBIO,O
LD
XAS
NOP
CLRA
AISC 12
XAS
NOP
LBI 0, 15
RC
XAS
OBD

; POINT TO FIRST DISPLAY DATA
; TURN CS LOW (DO)
; LOOK UP SEGMENT DATA
.; COPY DATA FROM 0 TO M & A
; SET C TO TURN ON SK
; OUTPUT LOWER 4 BITS OF DATA
; DELAY
; DELAY
; LOAD A WITH UPPER 4 BITS
; OUTPUT 4 BITS OF DATA
; DELAY
; DELAY
; RESET C
; TURN OFF SK CLOCK
; INCREMENT B FOR NEXT DATA
; SKIP THIS JUMP AFTER LAST DIGIT
; SET C
; ADDRESS SPECIAL SEGMENTS
;LOAD INTO A
; OUTPUT SPECIAL SEGMENTS

; 12 to A
; .OUTPUT CONTROL BITS
; 15 to B
; RESET C
; TURN OFF SK
; TURN CS HIGH (DO)

o""0

~

Example 2
eOP420 Code to load two eOP472 parts [display data is in M(O, 12)·M(O,15) and M(1, 12)·M(1, 15), special segment data 15
in M(O, Q)and M(1, 0)]
INIT:

LBI·
OBD
LEI
Re
XAS
LBI
STII
LBI
JSR

0, 15

8

3, 15
7·
0,12·
OUT

; TURN BOTH es's HIGH
; ENABLE SO OUT OF S. R.
; TURN OFF SK CLOCK
, ; USE M(3, 15) FOR CONTROL BITS
; STORE 7 TO SYNC BOTH CHIPS
; SET B TO TURN BOTH CS'S LOW
; CALL OUTPUT SUBROUTINE .

. MAIN DISPLAY SEQUENCE
DISPLAY:

LBI
STII
LBI
JSR
LBI
STII
LBI
JSR

3,15 .

8
0, .13
OUT
3, 15

6
1,14
OUT

; SET CONTROL BITS FOR SLAVE
; SET B TO TURN SLAVE CS LOW
; OUTPUT DATA FROM REG.

°

; SET CONTROL BITS FOR MASTER
; SET B TO TURN MASTER CS LOW
; OUTPUT DATA FROM REG. 1

OUTPUT SUBROUTINE
OUT:

LOOP:

OBD
CLRA
AISC
CAB
CLRA
LOID
COMA
SC
XAS
NOP
NOP
LD
XAS
NOP
NOP
RC
XAS
XIS
JP
SC
NOP
LD
XAS
NOP
LBI

LD
XAS
NOP
NOP
RC
XAS
OBD
RET

; OUTPUT B TO CS'S
12

; 12 TO A
; POINT TO DISPLAY DIGIT (BD= 12)
; LOOK UP SEGMENT DATA
; COPY DATA FROM 0 TO M & A

LOOP

; OUTPUT LOWER 4 BITS OF DATA
; DELAY
; DELAY
; LOAD A WITH UPPER 4 BITS
; OUTPUT 4 BITS OF DATA
; DELAY
; DELAY
; RESETC
; TURN OFF SK
; INCREMENT B FOR NEXT DISPLAY DIGIT
; SKIP THIS JUMP AFTER LAST DIGIT
; SETC
; LOAD SPECIAL SEGS. TO A (BD=O)
; ·OUTPUT SPECIAL SEGMENTS

3, 15
; LOAD A
; OUTPUT CONTROL BITS

• ; TURN OFF SK
; TURN CS'S HIGH (BD=15)

1·152

COPS™ Peripheral
Product Brief
PRELIMINARY

o

o"'0
~

CO

COP498 Low Power CMOS RAM and Timer
General Description

Features

The COP498 low power CMOS Random-Access Memory
and Timer is a peripheral member of the COPSTM family,
fabricated using CMOS technology. It is an external
memory and timer chip with the simple MICROWIRpM
serial interface. The device contains 256 bits of
read/write memory divided into 4 registers of 64 bits
each. Each register can be serially loaded or read by a
COP400 controller. The COP498 also contains a crystalbased timer for timekeeping purposes,and can provide
a "wake-up" signal to turn on a COPS controller.
The COP498 can be used for low power standby memory
and can also be used for low power operation by turning
the controller off and on, on a duty cycle basis.

A COP400 N-channel controller coupled with the
COP498 RAM/Timer offers a user the low-power advantages of a CMOS system and the low-cost advantage of
an NMOS system. This type of system solution is ideally
suited to a wide variety of automotive and instrumentation applications.

• Low power dissipation
• Low cost
• Single supply operation (2.5V·6.0V)
• CMOS compatible I/O
• 4 x 64 serial read/write memory
• Selectable crystal-based timer
(2.097152 MHz or 32.768 kHz)
!!l

Software selectable 1 Hz or 16 Hz "wake-up"
signal for COPS controller

• External override
• Compatible with all COP400 processors
(processor Vcc " 9.5V)
• MICROWIRE compatible serial I/O
• 14-pin dual-in-line package

XlN

XOUT

'-"G~-i-;><>--+""

SK

__

osc
XSEL

256-BIT
RAM

--

SLEEP
CE
CS

1 Hz
OVR

INSTRUCTION
OECOOE

01

ON
DD

Vee

GND

COP498 Block Diagram

1.. 153

~

oo

COP498
Connection Diagram

CS
CE

SK
01
00
XSEL
GNO

Pin

14
13

Yee
OSC

12
11
10
9

XOUT
X,N
OYR

Description

CS
CE
SK

ON
1 Hz

01

Chip Select
Chip Enable
Serial Data Clock
Serial Data Input

DO
XSEL
XIN
XOUT
1 Hz

Serial Data Output
Crystal Option Select
Crystal Oscillator Input
CrystalOsci lIator Output
1 Hz square wave output

ON

Active low wake-up signal to COPS
controller

OVR

External override wake-up for COPS
controller
Open drain oscillator output
Power Supply

OSC
Vee
GND

Ground

COP498 Instruction Set

WRITE
READ

s 1 r, ro
1 0 r, ro

WREN
WRDS
TSEC
SLEEP

0 0 1 .1
0 0 0 0
0 0 10
0 o 0 1

s = ON (wake up signal) frequency select
1 = 16 Hz; 0 = 1 Hz
r, ro=register number (00, 01,10,11)
Write Enable
Write Disable
Test timer seconds latch
Put COP controller to sleep (ON goes high)

The instruction setup and chip select/chip enable structure is organized so as to
provide maximum protection to the read/write memory while the COPSTM controller
is powered up and down.

Y+

B.2k

00 CKI

1 - - - - - - - 1 SI
1 - - - - - - - 1 so
~~~~r----------1SK

Typical System Diagram

1-154

Yee
COP420

GNO

COPS™ Peripheral
Product Brief
PRELIMINARY

o

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~

CO

COP499 Low Power CMOS Memory
General Description

Features

The COP499 Low Power CMOS Random-Access
Memory is a peripheral member of the COPSTM family,
fabricated using CMOS technology. It is an external
memory and switch chip iNith the simple MICROWIRETM
serial interface. The device contains 256 bits of readl
write memory divided into 4 registers of 64 bits each.
Each register can be serially loaded or read by a
COP400 controller. The C,DP499 also contains circuitry
that enables the user to turn a controller on and off
while maintaining the integrity of the memory.

• Low power dissipation
• Low cost
• Single supply operation (2.5V-6.0V)
•
•
•
•

CMOS compatible 1/0
4 x 64 serial readlwrite memory
External "wake-up" signal for COPS controller
Compatible with all COP400 processors
(processor Vee ~ 9.5V)
• MICROWIRE compatible serial 1/0
• B-pin mini-DIP

OVR

SK

~~-----_r-I~C:O:UN:T:ER~-'
-1.'-----.-_......
6 ..... ADDRESS

r----

'-- S
256·BIT
RAM

~RY OUTPUT

Q

LATCH

r-- R

Q

~

-r-- jjjj

SLEEP
INSTRUCTION
DECODE

CE_r-

DI

ENABLE

.I-;J:>----+-.
.

1 ----1
_+---6-t t
Vee

GNO

COP499 Block Diagram

1-155

DO

i

'~

0..

8

COP499
Connection Diagram

Pin
CE
SK

CEOs ve

SK
2
013
00
4

70VR

01

SON
5

DO

GND

Vee
GND
ON
OVR

Description
Chip enable
Serial data clock
Serial data input
Serial data output
Power supply
Ground
Active low wake-up signal to COPS
controller
External wake-up signal

COP499 Instruction Set

WRITE

0 1 r1 ro

READ
WREN

1 0 r1 ro
0 o 1 1

' Write to memory
Write Enable

WRDS

0 0 0 0

Write Disable

SLEEP

0 0 0

Put COP controller to sleep (ON goes high)

r1 ro= register number (00, 01,10,11)

Read from memory

The instruction setup and chip select/chip enable structure is organized so as to provide maximum protection
to the read/write memory while the COPSTM controller is powered up and down.

V+

, ,1k

ON

COP499

OVR

CE

1--------1

00 r - - ' - - - - - - - I
DII------~

GND

SKr--------I

Typical,System Diagram

1-156

Section 2
COPS Application Information

COP400
Microcontroller
Family

COPSTM Family User's Guide

II)i"A National
~

.
Semiconductor

420305785·001

2-3

·Table of Contents
Page

Section

Description

1.1

Summary of CQP400 Microcontroller Features ........................... 2·8

Chapter 1. Introduction to COP400 Microcontrollers

Chapter 2. COP400 Architecture
2.1
COP420/COP421 Architecture ........................................ 2·10
2.2
COP420/COP421 Functional Description ..............................• 2·12
2.3
Initialization ....................................................... 2·13
2.4
COP420/COP421 Mask Programmable Options .......................... 2·14
2.5, COP420/COP421 Option List ....... " .. , ............. '.' .............. 2·18
2.6
COP420UCOP421L Description ....................................... 2·19
2.7
CO P420UCOP421 L Mask Programmable Options ........................ 2·19
2.8
COP420UCOP421LOption List ....................................... 2·21
2.9
COP420C Description ............................................... 2·22
2.10 COP444L Description ............................................... 2·23
2.11 COP402 and COP402M ROM·less Part Description ....................... 2·23
2.12 'COP404L ROM·less Part Description .... , ............................. 2·23
2.13 COP410UCOP411LArchitecture.: ..................... , .............. 2·23
2.14 COP410UCOP411L Functional Description ............................. 2·25
2.15 COP410UCOP411L Mask Programmable Options ........................ 2·26
2.16 COP410UCOP411LOption List ....................................... 2·26
Chapter 3. COP400 Instruction Sets
3.1
3.2
3.3
3.4
3.5

COP420·Series/COP444L Instruction Set ............................... 2·29
COP420·Series/COP444L Instruction Set Description ..................... 2·33
COP421·Series Instruction Set Differences ............................. 2·40
COP410UCOP411L Instruction Set ................................... :2.40
COP410UCOP411 L Instruction Set Differences ......................... 2·43

2-4

Table of Contents
Section

Description

Page

Chapter 4. COP400 Programming Techniques
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11

P-<)gram Memory Allocation .......................................... 2·48
Data Memory Allocation and Manipulation ............................. 2·51
Subroutine Techniques .............................................. 2·52
Utility Routines .................................................... 2·53
Timing Considerations .............................................. 2-54
BCD Arithmetic Routines ............................................ 2-55
Simple Display Loop Routine ......................................... 2-57
Interrupt Service Routine ............................................ 2·59
Timekeeping Routine ............................................... 2-59
String Search Routine ............................................... 2-62
Programming Techniques for the COP421-Series, COP410L and 411 L ....... 2·63

5.1
5.2
5.3
5.4
5.5
5.6

Hardware Interfacing Techniques ..................................... 2-64
Software 110 Techniques ............................................. 2-69
KeyboardlDisplay Interface .......................................... 2-70
SIO (Serial) Input/Output ............................................. 2·81
Add-on RAM ....................................................... 2-82
IN311No Inputs ...................................................... 2·83

Chapter 5. COP400 110 Techniques

Appendices -

COP400 Data Sheets

2·5

List of Figures
Figure

Description

2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
3.1
3.2,
4.1
4.2
4.3
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
'5.10
5.11
5.12
5.13
5.14
5.15
5.16
5.17
5.18
5.19
5.20
5.21
5.22

COP420/COP421 Block Diagram .. '" .......... , ...................... 2·10
COP420/COP421 Connection Diagrams ........ '........................ 2·11
COP420/COP421 Pin Descriptions ..................................... 2·11
Power-Clear Circuit. '" ...................................... , ...... 2·11
COP420/COP421 Clock Osci lIator Configurations ...........•..... , ...... 2·15
COP420/COP421 Input/Output Configurations .......................... 2-16
COP420/COP421 Input/Output Characteristics ... '" .................... 2-17
COP420UCOP421 L Oscillator Configurations ........................... 2-20
COP410UCOP411L Block Diagram .................................... 2-24
COP410LlCOP411LConnection Diagrams .............................. 2·25
COP410LlCOP411 L Pin Description ................................... 2·25
COP410LlCOP411 L Oscillator Configurations ........................... 2·27
INIL Hardware Implementation ....................................... 2-34
Enable Register Features - Bits EN3 and ENo .......................... 2·39
COP420 Data Memory Map ........................................... 2·51
Flowchart for Multiply Routine ....................................... 2-56
Flowchart for Timekeeping Routine ................................... 2·60
COP420 I/O Lines ................................................... 2-65
COP420 I/O Options ................................................. 2·65
COP420 Standard Output Characteristics ..............................,2·65
COP420 I/O Interconnect Examples ................................... 2-66
COP420 IN Input Characteristics ...................................... 2·66
D and G Port Characteristics .......................................... 2·67
COP420L I/O Port Characteristics ..................................... 2·67
COP420 SI, SO, SK Characteristics .................................... 2·68
COP420 CKO, CKI, RESET Characteristics .............................. 2·68
COP420 I/O Expansion .......................... , ............ , ...... 2·69
COP420 LED Display System ......................................... 2·69
COP420 VF Display System .......................................... 2·69
COP420 MICROBUSTM Interconnect .................. , ................ 2·69
COP420Add·On RAM ............................................... 2·69
Display/Keyboard Interconnect ..................................... : .2·70
Flowchart for Display/Keyboard Debounce Routine ..... , ..... , .......... 2-71
Display Timing Diagram ............................................. 2·72
Display/Keyboard Interface Source Code ................... ", ......... 2·77
Key·Decode Routine Assembler Output Listing .......................... 2·80
Additional I/O Using SI and SO ........................................ 2-81
Multi·COP420 System ............................................... 2-81
Add-On RAM Interconnect .................................. : ........ 2·83

2-6

Page

List of Tables
Table

1.1
2.1
3.1
3.2
3.3
3.4
3.5
3.6
3_7
3.8
4.1
5.1
5.2
5.3

Description

Page

COP400 Device Features ............................................. 2-9
Enable Register Functions - Bits EN3 and ENo ......................... 2-14
COP420lCOP421 Instruction Set Table ................................. 2-30
COP420lCOP421 Instruction Set Symbols .............................. 2-33
COP410UCOP411 L Instruction SetTable ............................... 2-40
COP410UCOP411L Instruction Set Symbols ............................ 2-43
Alphabetical Mnemonic Index of COP420lCOP421 Instructions ............ 2-44
COP420lCOP421 Instructions Listed by Hex Opcodes .................... 2-44
Alphabetical Mnemonic Index of COP410UCOP411 L Instructions .......... 2-46
COP410UCOP411 L Instructions Listed by Hex Opcodes .................. 2-47
Page to Hexadecimal Address .................... _....... : ........... 2-48
COP400 110 Comparison Chart ........................................ 2-64
Seven-Segment Decode Values ... _................................... 2-74
JID Pointer Table for DisplaylKeyboard Routine ......................... 2-79

2-7

Introduction to the
COP400 Microcontrollers

1
:I;

en
Do
o

This manual provides information on the COP400
series of National's single-chip microcontrollers_
The material contained in this manual Is intended'
to assist the reader in understanding the internal
architecture, instruction set, programming
techniques, and hardware and software 1/0 techniques pertaining to the COP400 family of microcontroller devices.

mask-programmed into the part at the same time
as the user's program; this allows even greater
flexibility in matching the COP400 Microcontroller
to the user's specifications, reducing the need for
external interface logic.
All COP400 devices feature single-supply operation
and fast, standardized, "in-house" test procedures
which verify the internal logic and user program
(ROM code) mask-programmed into the device_
Several COP400 controllers are available in ROMless versions for use in prototyping a COP400
system (using the COP400 Development System) or
for low-volume applications.

The primary focus of this manual is the COP420 at the time of this printing the most inclusive
device, on a hardware and software level, of the
COP400 family. Other members of the COP400
family are discussed primarily in terms of the less
inclusive features of these other parts (i.e_, the
COP421, COP410L, COP411L).This approach
should not result in a lack of understanding in
terms of the operation and programming of these
parts since they are "subset" devices of the
COP420, distinguished, for the most part, by
deleted hardware and software features. For further
information on these other devices and on future
COP400 devices the reader should consult the data
sheets appropriate to particular COP400 devices.

Table 1.1 provides a list of COP400 devices
currentlyavailf\ble or in design, together with a
summary of the basic feaiures of each device.
Refer to this manual and data sheets of particular
devices for further information on these parts.
Future members of the COP400 family will include
more powerful hardware and software capabilities,
alternative electrical specification devices (low
power, CMOS versions) and peripheral devices
suitable for use in many applications.

1.1 Summary of COP400 Microcontroller
Features

The flexible 1/0 configuration of COP400
Microcontrollers allows them to interface with and
drive a wide range of devices using minimal
external parts. Typical peripheral devices include:

COP400 Microcontrollers are fabricated using
CMOS or N-channel, silicon gate MOS technology.
They are complete microcomputers containing all
system timing, internal logic, ROM, RAM, and 1/0
necessary to implement dedicated control
functions in a variety of applications. Features of
the COP400 devices include an instruction set,
internal architecture, and 1/0 scheme designed to
facilitate keyboard input, display output, and
efficient BCD data manipulation.

1. Keyboards a.nd displays (direct segment and
digit drive possible for several devices).
2. External data memories.
3. Printers_
4. Other COPSTM devices.
5. AiD and DIA converters.

The various members of the COP400 family allow
the user to specify a microcontroller best suited for
use in a particular dedicated application.
Specifically, COP400 devices offer a choice among
single-chip parts with differing amounts of ROM,
RAM, 1/0 capability, and number of instructions.
Additionally, many parts have different versions
which allow a choice of electrical characteristics
while retaining the basic architecture and
instruction set of the basic device. (For example,
the COP420L and COP420Care available as lowpower and CMOS versions, respectively, of the
standard COP420 device.) Finally, each part
contains a number of clock, 1/0 and other options,

6. Power control devices (SCRs, TRIACs).
7. Mechanical actuators.
8. General purpose microprocessors
(communication with host CPUs over National's
MICROBUSTM for several COP400 devices).
9. Shift registers.
10. External ROM data storage devices.

2·8

In conclusion, National's COP400 series of
Microcontrollers provides low-cost solutions to lowend computing and control problems_ Proven
applications include:

5. Programmable sequencers.
6. Scales, cash registers.
7. Calculators.

1_ Clocks, timers_
2_ Laboratory instruments_

8. Microcontroller computational elements.

3_ Radio controllers.

9. Toys and games.
10. Automotive computers.

4. Appliance controllers.

~

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Table ,1.1 , COP400 Device, Featut,es

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2-9

2

COP400 Architecture

This chapter provides information on the
architecture of the COP400 Microcontrollers.
Consistent with the general approach of this
manual, the COP420 is primarily discussed with the
COP421 treated in terms of differences with
respect to the COP420. The COP410L, COP411L
and COP444L are similarly treated. The text,
therefore, primarily discusses the internal
architecture of the COP420, with differences noted
forthe other devices. Also briefly discussed are
different versions of each primary device (e.g., for
the COP420, the COP420L and COP420C). As these
additional devices, as well as the most inclusive
COP400 device, the COP440, become available,
further information will be provided in data sheets
for each part.

2.1 COP420/COP421 Architecture
Figure 2.1 provides a block diagram of the
COP420/COP421. It is intended to acquaint the user
with the functions of, and interconnections among,
the various logic blocks within the processor. Data
paths are illustrated in simplified form to depict
how the logic elements communicate with each
other in implementing the instruction set of the
devices. Note that the IN3-INo general purpose
inputs are not available on the COP421, norare the
two internal IL latches associated with IN3 and IN o.

One should consult the COP420/COP421 data sheet
for maximum ratings, DC and AC electrical
characteristics for these devices.

Figure 2.2 shows the connection diagrams for the
28-pin COP420 and the 24-pin COP421. Figure 2.3
provides a pin description for the COP420/COP421
devices.

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2-11

2.2 COP420/COP421 Functional Description
LDD and XADinstructions based upon the 6·bit
contents of the operand field of these instructions.
The Bd register also serves as a source register for
4·bit data sent directly to the D outputs.

The following text provides a functional description
of the logic elements depicted in the
COP420/COP421 plock diagram.
Program Memory
Program memory consists of a 1,024·byte ROM.
ROM words may be program instructions, program
data or ROM address pointers. Due to the special
characteristics associated with the J P and JSRP
instructions, ROM must often be conceived of as
organized into 16 pages of 64 words (bytes) each.
Also, because of the unique operations performed
by the LaiD and JID instructions, ROM pages must
often be thought of as organized into four
consecutive blocks of four ROM pages. (For fur!her
information on the paging characteristics of these
Instructions, see Section 4.1.)

The 4·bit A register (accumulator) is the source and
destination register for most 1/0, arithmetic, logic
and data memory access operations. It can also be
used to load the Br and Bd portions of the B register,
to load and input 4 bits of the B·bit a latch data, to
input 4 bits of the B·bit L 110 port data and to
perform data exchanges with the SIO register.

ROM addressing is accomplished by the 10·blt P
register. Its binary value selects one of the 1,024
B·bit words (1 7 -1 0) contained in ROM. The value of P
is automatically incremented by 1 prior to the
execution of the current instruction to point to the
next sequential ROM location, unless the current
instruction is a transfer of control instruction. In
the latter case, P is loaded with the appropriate
non·sequential value to implement the transfer of
control operation performed by the instruction. It
should be noted that P will automatically
"roll·over" to point to the next page of program
memory, This feature has particular significance
for transfer of control instructions with paging
restrictions, i.e., JP, JSRP, JID and LaiD. Since Pis
incremented to roll·over to the next ROM page prior
to executing these instructions, they will be treated
as residing on the next ROM page if they reside in
the last word of a ROM page. Further information
Is provided in Section 4.1.

Four general·purpose inputs, IN3-INo, are provided
for the COP420: INlo IN2 and IN3 may be selected,
by a mask·programmable option, as Read Strobe,
Chip Select and Write Strobe inputs, respectively,
for use in MICROBUS™ applications.

Internal Logic

A 4·bit adder performs the arithmetic and logic
functions of the COP420, storing results in A. It
also outputs a carry bit to the 1·bit C register, most
often employed to indicate arithmetic overflow. The
C register, in conjunction with the XAS instruction
and the EN rElgister, also serves to control the SK
output. C can be outputted directly to SKL or can
enable SKL to be a SYNC pulse, providing a clock
each instruction cycle time. (See XAS instruction,
Table 3.1, and EN register description, below.)

The COP421 does not contain the IN3-INo inputs
and, therefore, must use the 4 bidirectional G 110
ports or B bidirectional L 110 ports as input pins to
the device. Use of National's MICROBUS is
inappropriate with the COP421.
The D register provides 4 general purpose outputs
and is used as the destination register for the 4·bit
contents of Bd.

Three levels of subroutine are implemented by the
10·bit subroutine save registers, SA, SB and SC,
providing a last·in, first·out (LIFO) hardware
subroutine stack.

The G register contents are output to 4 general·
purpose bidirectional 110 ports. The COP420 Go pin
may be mask·programmed as a "ready" output for
MICROBUS applications.

ROM instruction words are fetched, decoded and
executed by the Instruction Decode, Control and
Skip Logic circuitry.

The a register is an internal, latched, B·bit register,
used to hold data loaded to or 'from M and A, as
well as B·bit program data from ROM. Its contents
are output to the L 110 ports when the L drivers are
enabled under program control (via an LEI
instruction). The COP420 may use the MICROBUS
option to write L 110 port data into a upon the
occurrence of a WS pulse from the host CPU.

Data Memory

Data memory consists of a 256·bit RAM, organized
as 4 data registers of 16 4·bit digits. RAM
addressing Is implemented by a 6·bit B register
whose upper 2 bits (Br) select 1 of 4 data registers
and lower 4 bits (Bd) select 1 of 16 4·bit digits in
the selected data register. While the 4·bit contents
of the selected RAM digit (M) are usually loaded
Into or from, or exchanged with, the A register
(accumulator), they may also be loaded into or from
the a latches or loaded from the L ports. RAM
addressing may also be performed directly by the

The B L drivers, when enabled, output the contents
of latched a data to the L 110 ports. Also, the
contents of L may be read directly into A and M. As
explained above, the COP420 MICROBUS option
allows L 110 port data to be latched into the a

2·12

register. L 1/0 ports can be directly connected to
the segments of a multiplexed LED display (using
the TRI-STATE® LED Direct Drive output
configuration option) with Q data being outputted
to the Sa- Sg and decimal point segments of the
display.

of the Enable Register is, therefore, a "don't
care" bit for the COP421: setting or resetting
this bit via an LEI instruction will have no effect
on the operation of the COP421. (For further
information on the procedure and protocol of
this COP420 interrupt feature, see Section 3.2,
LEI instruction description.)

The SIO register functions as a 4·bit serial'inl
serial·out shift register or as a binary counter
depending on the contents of the EN register. (See
EN register description, below.) Its contents can be
exchanged with A, allowing it to input or output a
continuous serial data stream. SIO may also be
used to provide additional parallel 1/0 when used
as a shift register with its input or output
connected to external serial·in/parallel·out shift
registers.

3. With EN2 set, the L drivers are enabled to output
the data in Q to the L 1/0 ports. Resetting EN2
disables the L drivers, placing the L 1/0 ports in
a high·impedance input state. If the COP420
MICROBUSTM option is being used, EN2 does not
affect the L drivers.
4. EN3, in conjunction with EN o, affects the SO
output. With ENo set (binary counter option
selected), SO will output the value loaded into
EN 3. With ENo reset (serial shift register option
selected), setting EN3 enables SO as the output
of the SIO shift register, outputting serial shifted
data each instruction time. Resetting EN3 with
the serial shift register option selected disables
SO as the shift register output: data continues
to be shifted through SIO and can be exchanged
with A via an XAS instruction but SO remains
reset to "0." Table 2.1 provides a summary of the
options and features associated with EN3 and
ENo·

The 10·bit time base counter divides the instruction
cycle frequency by 1,024, providing a pulse upon
overflow. The COP420 SKT instruction tests for the
occurrence of this pulse, allowing the programmer
to rely on this internal time·base rather than
external inputs (e.g., 50/60 Hz signals) to implement
"real·time" routines.
The EN register is an internal 4·bit register loaded
under program control by the LEI instruction. The
state of each bit of this register selects or
deselects the particular feature associated with
each bit of the EN register (EN r EN o).

2.3 Initialization

1. The least Significant bit of the enable register,
EN o, selects the SIO register as either a 4·bit
shift register or a 4·bit binary counter. With ENo
set, SIO is an asynchronous binary counter,
decrementing its value by one upon each low·
going pulse ("1" to "0") occurring on the SI input
(count·down counter). Each pulse must be at
least two instruction cycles wide. SK outputs the
value of C upon execution of XAS and remains
latched until the execution of another XAS
instruction. The SO output is equal to the value
of EN 3. With ENo reset, SIO is a serial shift
register shifting left each instruction cycle time.
The data present at SI goes into the least
significant bit of SIO. SO can be enabled to
output the most significant bit of SIO each cycle
time. (See Table 2.2 below.) The SK output
becomes a logic·controlled clock, providing a
SYNC signal each instruction time. It will start
outputting a SYNC pulse upon the execution of
an XAS instruction with C = 1, stopping upon the
execution of a subsequent XAS with C = O.

Upon initialization of the COP420/COP421 as
described below, the P register is cleared to 0
(ROM address 0) and the A, B, C, D, EN, and G
registers are cleared. The INa and IN3 latches are
not cleared. The SK output is enabled as a SYNC
output, providing a pulse each instruction cycle
time. Data memory (RAM) can only be cleared by
the user's program. The first instruction at address
o must be a CLRA.
The Reset Logic, internal to the COP420/COP421,
will initialize (clear) the device upon power·up if the
power supply rise time is less than 1 ms and
greater than 1 f's. If the power supply rise time is
greater than 1 ms, the user must provide an
external RC network and diode to the RESET pin as
shown in Figure 2.4 below. The RESET pin is
configured as a Schmitt trigger input. If not used, it
should be connected to Vee. Initialization will occur
whenever a logic "0" is applied to the RESET input,
provided it stays low for at least three instruction
cycle times. In order to reset the Time Base
Counter, a RESET pulse ten instruction cycle times
wide must be applied; note that the counter will
overflow and generate an output pulse.

2. With EN1 set, the COP420 IN1 input is enabled
as an interrupt input. Immediately following an
interrupt, EN1 is reset to disable further
interrupts. Note that this interrupt feature
associated with IN1 is unavailable on the
COP421 since it lacks the IN inputs. Bit 1 (EN 1)

2-13

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2.4 COP420/COP421 Mask Programmable
Options
d. Externally Synchronized Oscillator. Intended for
use in multi·COP systems, CKO is programmed
to function as an input connected to the SK
output of another COP420lCOP421 with CKI
connected as shown. In this configuration, the
SK output connected to CKO must provide a
SYNC (instruction cycle) signal to CKO, thereby
allowing synchronous data transfer between the
COPs using only theSI and SO serial 110 pins in
conjunction with the XAS instruction. Note that
on power·up SK is automatically enabled as a
SYNC output. (See Initialization, above.)

To allow even greater flexibility in specifying a
COP400device appropriate to the user's
application, all COP400 microcontrollers have
specific clock configuration, 110 and other mask·
programmable options associated with them. These
options are masked into the part simultaneously
with the masking of the user's program in ROM and
have been chosen to offer the user a wide range of
options which encompasses design options most
frequently employed in dedicated, small system
applications.
The following text summarizes the COP420lCOP421
options according to the various functions
(OSCillator, 110, etc.) with which they are associated.

The lower portion of Figure 2.5 provides component
val ues for several instruction cycle times and
crystal values associated with the RC controlled
and Crystal Oscillator options, respectively.

Clock Oscillator Options
There are four basic COP420lCOP421 clock
oscillator configurations avilable as shown by
. Figure 2.5 (a-d):
.

CKO Non·Tlmlng Options

In a crystal controlled or multi·COP oscillator
system, CKO is used as an output to the crystal
network. In the other two configurations (external
clock or RC controlled oscillator), CKO may be
mask·programmed to perform one of two available
options. Specifically, CKO may be mask·
programmed as a general purpose input, read into
bit 1 of the accumulator (A2) upon the execution of
an INIL instruction.

a. Crystal Controlled Oscillator. CKI and CKO are
connected to an external crystal. The instruction
cycle time equals the crystal frequency. (4 MHz
maximum) divided by 16 (optional by 8).
b. External Oscillator. CKI is configured as ·a TTL
compatible input accepting an external clock
signal. The external frequency (4 MHz maximum)
is divided by 16 (optional by 8) to derive the
instruction cycle time. CKO is now available to
be used as the RAM power supply (VR) pin, as a
general purpose input, or as a synchronizing
input.

As another option (for both the COP420 and
COP421), CKO can be a RAM power supply pin (VR),
allowing its connection to a' standbylbackup power
supply to maintain the integrity of RAM data with
minimum power drain when the main supply is
inoperative or shut down to conserve power. Use of
this options should include external circuitry to
detect loss of Vee power and force RESET low
before Vee drops below spec.

c. RC Controlled Oscillator. CKI is configured as a
single·pin RC controlled SC.hmitt trigger
oscillator. The instruction cycle equals the
oscillation frequency divided by 4. CKO is
available for non·timing functions as in b above.

2·14

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PURPOSE INPUT
OR SYNC PIN)

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(VR OR GENERAL
PURPOSE INPUT
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c. RC Controlled Oscillator

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eKO

2-15

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MICROBUSTM Option

1/0 Options

The COP420 has an option which allows it to be
used as a peripheral microprocessor device.
ineutting and outputting data from and to a host
microprocessor V
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CKO

COP410L (or COP42DLI

421 Ll444L/445L1

= 1:

When specifying a COP411 L device, Option 2 must
be set to a value of "3," and Options 20, 21, and 22
must be set to a value of "0," since the COP411 L
does not include these pins.

Option 4: RESET Input

= 0:

The following is a list of COP410UCOP411L
options:
Option 1 = 0: Ground Pin -

Option 5: L7 Driver

no options available

= 0:
= 1:

clock generator output to crystal/resonator

standard output (Figure 2.6d)
open-drain output (Figure 2.6e)

= 2: high current LED direct segment drive
output (Figure 2.6f)

pin is RAM power supply (VR) input

=3:

= 2: multi·COP SYNC input (CKI .;. 8)
=3: no connection (COP411L)

high current TRI-STATE® push-pull output
(Figure 2.6g)

= 4: low current LED direct drive output (Figure
2.6g)

Option 3: CKI Input

= 0:

load device to Vee

= 1: hi-Z input

Option 2: CKO Output

=0:
= 1:

single'pin RC controlled oscillator divided
by 4

oscillator input divided by 8
(500kHz maximum)

=5:
2-27

low current TRI-STATE® push-pull output
(Figure 2.9f)

CD

Option 6: Ls Driver

Option 19:

Option 7: L5 Driver

110 Port

Option 20: G3 110 Port
same as Option 17

same as Option 5
Option 8: L4 Driver

G~

same as Option 17

same as Option 5

Option 21: D3 Output
= 0: very high current standard output

same as Option 5

= 1: very high current open·drain output

Option 9: Vee Pin
= 0: 4.5·6.3Voperation

= 2: high current standard output

= 1: 4.5·9.5V operation (extra cost option)

= 3: high current open·drain output
= 4: standard LSTTL output (fanout = 1)

Option 10: L3 Driver

= 5: open·drain LSTTL output (fanout = 1)

same as Option 5

Option 22: D2 Output

Option 11: L2 Driver

same as Option 21

same as Option 5

Option 23: D1 Output

Option 12: L1 Driver

same as Option 21

same as Option 5

Option 24: Do Output

Option 13: La Driver

same as Option 21

same as Option 5

Option 25: L Input Levels

Option 14: SI Input

= 0: standard TTL input levels ("0" = 0.8V,
"1"=2.0V)

same as Option 4
Option 15: SO Driver

= 1: higher voltage input levels ("0" = 1.2V,
"1"=3.6V)

= 0: standard output (Figure 2.6a)
= 1: open·drain output (Figure 2.6b)

Option 26: G Input Levels

= 2: push·pull output (Figure 2.6c)

same as Option 25

Option 16: SK Driver

Option 27: SI Input Levels

same as Option 15

same as Option 25

Option 17: Go 110 Port

Option 28: .COP Bonding

= 0: standard output (Figure 2.6a)

=0: COP410L

= 1: open·drain output (Figure 2.6b)

= 1: COP411L

Option 18: G1 110 Port
same as Option 17

2·28

3

COP400 Instruction Sets

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3_1 COP420·Series/COP444L Instruction Set

This chapter provides information on the
instruction sets of the COP400 microcontrollers. As
with the architecture of the different devices in the
COP400 family, the instruction sets of the various
devices allow the user to choose among several
devices to provide only as much software
capability as is needed for a particular application.
Specifically, the instruction sets of the various
devices are, generally, subsets of the most
inclusive instruction set of the COP440. This
chapter will discuss the COP420-series (includes
COP421, COP421L, COP421C), COP444L, COP410L,
and COP411L, respectively. Users of the COP440
should refer to the COP440 data sheet (when the
device becomes available) for information on the
additional instructions associated with the COP440
instruction set.

Table 3.1 provides the mnemonic, operand, machine
code, data flow, skip conditions and description
associated with each instruction in the COP420series/COP444L instruction set. As indicated, an
asterisk in the description column signifies a
double·byte instruction. Also, notes are provided
following this table which describe or refer to
additional information relevant to particular
instructions. As indicated by Note 3, the INI and
INIL instructions are not included in the COP421
instruction set, due to its lack of IN inputs and the
IL3 and ILa latches associated with two of the IN
inputs (lN3 and INa, respectively).
Note that the COP420·series/COP444L set, as with
all COP400 instruction sets, is divided into the
following categories: Arithmetic Operations,
Input/Output Instructions, Transfer of Control
Instructions, Memory Reference Instructions,
Register Reference Instructions, and Test
Instructions.

This chapter primarily provides information on the
machine operations associated with the instruction
set of COP400 devices. However, where
appropriate, short examples indicating typical
usage of particular instructions are provided. For a
detailed treatment on using COP400 instructions to
write COP400 assembly language programs, see
Chapter 4 of this manual.

2·29

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3_2 COP420-Series/COP444L Instruction Set
Description

Table 3.2 provides a list of internal architecture,
instruction operand and operational symbols used
in the COP420·series/COP444L Instruction Set
Table. Table 3.5 shows an alphabetical mnemonic
index of COP420-series/COP444L instructions,
indicating the hexadecimal opcode and description
associated with each instruction. Table 3.6 is a list
of COP420-series/COP444L instructions arranged in
order of their hexadecimal opcodes.

Arithmetic Instructions
Ase (Add with carry, Skip on Carry) performs a
binary addition of A, C (Carry bit), and M, placing
the result in A and C. If a carry occurs, the next
program instruction is skipped.
ADD (ADD) performs binary addition. The 4-bit
addends are A and M. The 4-bit sum is placed in A.
ADD does not affect the carry or skip.

The following text gives a description of each
COP420-series/COP444L instruction, explaining the
machine operations performed by each instruction
and, where appropriate, providing short examples
illustrating typical usage of particular instructions.

ADT (ADd Ten to A) adds ten (1010 2) to A and, like
ADD, does not affect the carry or Skip. It is
intended to facilitate Binary Coded Decimal (BCD)
arithmetic. For example, the following sequence of
instructions will perform a single-digit BCD add of
the contents of A and M [the carry is assumed set
when entering this routine if addition of the
previous least significant digits produced an
overflow (A > 9)]:

Table 3_2 COP42Q·Sarios/COP444l
Instruction Set Table Symbols

Symbol

Oofinilion

. INTERNAL ARCHITECTURE SYMBOLS

A
B,

4·bit Accumulator
6·bi! RAM Address Register

AISC 6
ASC
ADT

BrUppor 2 bi!s of B (register addressi
Lower 4 bits of S (digit address)

ad

H;llt Carry Register

The AISC 6 instruction adds a BCD correction
factor (I.e., 6) to the digit in the accumulator. (See
AISC instruction.) Since the accumulator contains a
BCD digit (<: 9) no carry will occur and the next
instruction, ASC, will always be executed. The ASC
instruction adds the carry and memory digit to A,
as explained above. If the result does not produce
a carry, signifying that the previous AISC 6
(correction factor) instruction was unnecessary, the
ADT instruction is executed, readjusting the
accumulator to the proper BCD result. (Remember:
ADT neither affects the carry nor skips.)

4-bit Data Output Port

G
IL
IN,

L
M

4-bit Enaole Register
4,bit Register to latch data for G 110 Port
Two, 1~bit Latches assoclnled with the iN3 Of INo
Inputs
~'bit 'Input Port

Ii·bit TRI'STATE 1I0Port
4·blt contents of RAM Merno,y poi,lted ,to by B
Register

PC
Q

SA

sa
SC

'

to-bit ROM Addross Register

(prograrn counter)

,8-0it Regisle, to lat,ctrdata for L 110 port
··10-bil ..~~.brout~ne SalJ.~. R~~is~er.~
'10'oil Subroutine Save Registe, B
iO;blt Subroutine Save Register C

If the ASC result does produce a carry, C is set for
propagation to the addition of the next most
significant digits and, since no readjustment of the
result is necessary, the ADT instruction is skipped.

A-bit Shift Register an,d Counter

Symbol

Osllnition

INSTRUCTION OPERAND SYMBOLS
d'
4;bl\ Operand Field, 0-1ii binary (RAMOI9I!

AISe (Add Immediate, Skip on Carry) adds the
instruction operand constant "y" (1-15) to A,
skipping the next instruction if a carry out occurs
(C is not changed). This instruction finds frequent
use in BCD add and subtract routines (see ADT and
CASC descriptions) as well as in testing the value
of A. (If A is greater than 12, for instance, an
AISC 5 will skip the next instruction.)

S~lecl)

2·bit Operand Field,' 0-3 binary (RAM Rggister
Select)

,

"'O'bll Operand Fiald,()-t023llIJlary iROMAd~r"ssl
4·bllOperand Field. 0-15 binary uminedi~te Datal
ROM(tt

,contents of RAM location addressed by s
Contentse! ROM lacotlon.:iddressed by t

CASe (Complement and Add, Skip on Carry)
performs a binary subtraction of A from M by
summing the complement of A (A) with C and M,
placing the result in A and C. If no carry out
occurs, indicating a borrow, C is reset and the next
instruction is executed. If a carry occurs, indicating
no borrow, C is set and the next instruction is
skipped.

2-33

InputlOutput Instructions

A single BCD digit binary subtraction of A from M
may be performed as follOWS. (The carry bit is
assumed set upon initial entry to the routine.)

ING (INpui G ports to A) transfers the 4·bit
contents olthe IN ports (IN3-INo) to A.

CASC

ININ (INput IN inputs to A) transfers the 4-bit
contents of the IN ports (IN3-INo) to A.

ADT

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The CASC instruction will set C and skip the ADT
instruction if .the subtraction does not result in a
borrow (A > M). If a borrow occurs, the ADT
instruction is executed, readjusting the result to
the proper .BCD value, leaving C reset for
propagation of the borrow in the subtraction of the
next most significant BCD digits. CASC is
functionally equivalent to a COMP instruction
fOllowed by. an ASC.

INIL (INput IL latches to A) is a special purpose
instruction which inputs the two latches IL3 and ILa
(see Figure 3.1 below) and, if the appropriate option
is selected, a general-purpose input, CKO, to the
accumulator - the unused bitlbits of A are reset.
Specifically, INIL places IL3 - A3, CKO - A2 ,
"0" - A 1, ILa - Ao. IL3 and ILa are the outputs of
latches associated with the IN3 and INo inputs.
(The general purpose inputs, IN 3-IN o, are input to A
upon the execution of an ININ instruction. (See
ININ Instruction.) The IL3 and ILa latches are set if
a low-going pulse ("1" to "0") has occurred on the
IN3 and INo inputs, respectively, since the last INIL
instruction, provided the input pulse stays low for
at least two instruction times. Execution of an INIL
inputs IL3 and ILo into A3 and Ao respectively, and
resets these latches to allow them to respond to
subsequent low-going pulses on the IN3 and INo
lines.

CLRA (CLeaR A) clears the accumulator by placing
zeros in each of the 4 bits of A.
This instruction is often required prior to loading A
equal to a desired value with an AISC instruction if
the previous contents of A are unknown. For
instance, to load A= 11, the following sequence
may be used:
CLRA
AISC

11

The skip features associated with AISC need not
be. considered in this example. (A carry will never
occur.)

If CKO is mask-programmed as a general-purpose
input, an INIL will input the state of CKO into A2. If
CKO has not been so programmed, a "1" will be
placed in A2. A "0" is always placed in A1 upon the
execution of an INIL.

COMP (COMPlement A) changes the state of each
of 4 bits of A with ones becoming zeros and zeros
becoming ones. It has the effect of, and may be
used to perform, a binary (one's complement)
subtraction of A from 15 (11112), e.g.,
complementing A 6 (01102) will yield 9 (10012).

INIL is useful in recognizing and capturing pulses
of short duration or which can't be read
conveniently by an ININ instruction.

=

NOP (No OPeration) does not perform any
operation. It is useful, however, for simple single
instruction time delays or to defeat the skip
conditions associated with particular instructions.
SC (Set Carry) and RC (Reset Carry) set C and reset
C, respectively. SC and RC are most often·
employed to initializeC prior to entering arithmetic
routines. They also allow C to be used as a
general-purpose (testable) flag, as long as
subsequent instructions do not inadvertently affect
the C register.
XOR (eXclusive-OR A with M) performs a logical
EXCLUSIVE-OR operation of each bit of A with
each corresponding bit of M, plaCing the result in
A. This operation can be used to change the state
of any bit in M, if the corresponding (equally
weighted) bit of A is set. This follows from the
EXCLUSIVE-OR truth table where a X + "'" X, and
a X + "0" = X, assuming the "X" bits to be one of
the 4 bits in M, and the "1" and "0" to be equally
weighted bits in A. This instruction, therefore,
allows the selective complementing or toggling of
one or more bits of M. Example: to change the
state of bit 2 of M, set A = 0100, perform an XOR,
then exchange A into M with an X instruction.

=

INL (INput L ports to M, A) transfers the 8-bit
contents of the bidirectional TRI-STATE'" 1/0 ports
to M, A. L7 - L4 are placed in M3- Mo (the memory
digit pOinted to by the B register); L3- Lo are placed
in A3-AO.

2-34

aBO (Output Bd to D outputs) transfers the 4-bit
contents of Bd (lower 4 bits of the B register) to the
D output ports (D 3 - Do)- Since, in many
applications, the D outputs are connected to a digit
decoder, the direct output of Bd allows for a
standard interconnect to the binary inputs of the
decoder/driver device.

JMP (JuMP) transfers program control to any word
in the ROM as specified by the "a" field of this
instruction. The 10·bit "a" field is placed in Pg- Po.
JMP is used to transfer program control from one
page to another page (if in page 2 or 3, the more
efficient single·byte JP instruction may be used) or
to transfer control to the last word of the current
page - an invalid transfer for the JP instruction.

OGI (Output to G ports Immediate) transfers the
four bits specified in the "y" operand field of this
instruction (0-15, binary) to G3 - Go.

JP (Jump within Page) transfers program control to
the ROM address specified in the operand field of
this instruction. The machine code and operand
field of this instruction have two formats. If
program execution is currently within page 2 or 3
(subroutine pages) a 7-bit "a" field is specified,
transferring program control to a word within either
of the two subroutine pages. Otherwise, only a 6·bit
"a" field is specified, transferring program control
to a particular word within the current 64-word
ROM page.

OMG (Output M to G ports) transfers the 4-bit
contents of M (M 3 - Mo) to Gr Go.
XAS (eXchange A with SIO) exchanges the 4-bit
contents of A (A3 - Ao) with the 4-bit contents of the
SIO register (SI0 3-SIO o)' SIO will contain serialin/serial-out shift register or binary counter data,
depending on the value of the EN register. An XAS
instruction will also affect the SK output, providing
a logic controlled clock if SIO is selected as a shift
register or C - SK if SIO is selected as a binary
counter.

Specifically, this instruction places a6-aO in P6-PO
if the program is currently in subroutine page 2 or
3. If in any other page, it places a5-aO in P5- Po· .

For further information on the EN register and its
relationship to the XAS instruction, see LEI
Instruction, below. If SIO is selected as a shift
register, an XAS instruction must be performed
once every 4 instruction cycle times to effect a
continuous serial-in or serial-out data stream.

The restrictions associated with the JP instruction,
therefore, are that a 7-bit "a" field may be used
only when in pages 2 or 3. Otherwise, a JP may be
used only to jump within the current page by
specifying a 6-bit "a" field in the operand of this
instruction. An additional restriction associated
with the JP instruction, in either of the above two
formats, is that a JP to the last word of any page is
invalid, i.e., "a" may not equal all 1s. A transfer of
program control to last word on a page may be
effected by using a JMP instruction. (See JMP
Instruction, above.)

Transfer of Control Instructions
JID (Jump InDirect) is an indirect addressing
instruction, transferring program control to a new
ROM location addrssed by the contents of the ROM
location painted to by A and M. Specifically, it
loads the lower 8 bits of the ROM address register
P with the contents of ROM pOinted to by the 10-bit
word P9PSA3A2A1AoM3M2M1 Mo. The contents of
the selected ROM location (1 7 -1 0) are, therefore,
loaded into P7 - Po, changing the lower 8 bits of P
to transfer program control to the new ROM
location.

JSRP (Jump to SubRoutine Page) is used to
transfer program control froma page other.than 2 .
or 3 to a word within page 2. It accomplishes this
by placing a 2 (00102) in Pg- P6, and the word
address specified .in the 6·bit "a" field of the
instruction into P5- Po. Designed to transfer control
to subroutines, it pushes the stack to save the
subroutine return address - the address of the
next program instruction is saved in SA and the
other subroutine-save registers are likewise pushed
(P + 1 - SA - SB - SC). Any previous contents of
SC are lost, since SC is the last of the three
subroutine-save registers. Subroutine nesting,
therefore, is permitted to three levels. JSRP is used
in conjunction with the RET or RETSK instructions
which "pop" the stack at the end of subroutine to
return program control to the main program. As
with the JP instruction, JSRP may not transfer
program control to the last word of page 2: "a"
may not equal all "1s." A JSR may be used to jump
to the last word of a subroutine beginning at the
last word of page 2. (See JSR, below.) As
mentioned above, a further restriction is that a

Pg and Ps remain unchanged throughout the
execution of the JID instruction. JID, therefore, may
only jump to a ROM location within the current
4-page ROM "block" (pages 0- 3, 4- 7, 8-11 or
12-15). For further information regarding the
"paging" restrictions associated with the JID
instruction, see Section 4.1.
JID can be useful in keyboard-decode routines
when the values associated with the row and
column of a particular key closure are placed in A
and M for a jump indirect to the contents of ROM
which point to the starting address of the
appropriate routine associated with that particular
key closure. For an example of use of the JID
instruction to access a keyboard-decode ROM
pOinter table, see Display/Keyboard Program,
Section 5.3, #16.

2-35

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JSRP may not be used when in subroutine pages 2
or 3. To transfer program control to a subroutine in
page 2 when in pages 2 or 3, the double-byte JSR
should be used, or, if it is not necessary to push
the stack, a JP instruction may be used.

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CQMA (Copy Q to M, A) transfers the 8-bit contents
of the 0 latches to M and A. 0 7 -0 4 are placed in
M3-MO; 0 3-0 0 are placed in A3-Ao. CQMA can be
employed after an LOID (Load 0 InDirect)
instruction to input or alter the value of lookup
data_ COMA is also an essential instruction when
the COP420 is employed as a MICROBUSTM
peripheral component. In such applications, IN3 is
used by the control microprocessor to write bus
data from the L ports to the Q latches. (See Section
2.4, MICROBUSTM option.) A CQMA will then input
this data to M, A as explained above ·for processing
by the COP420 program.

JSR (Jump to SubRoutine) transfers program
control to a subroutine located at a particular word
address in any ROM page. It modifies the entire P
register with the value of the "a" operand of this
instruction, as follows: a9-aO - Pg - Po. As with the
JSRP instruction, JSR pushes the stack
(P +1 - SA - SB -+ SC), saving the next program
instruction for a return from the subroutine to the
main program via a RET or RETSK instruction. JSR
may be used to overcome the restrictions
associated with the JSRP instruction: to jump to a
subroutine and push the stack when in pages 20r
3, or to jump to a subroutine located at the last
word of page 2.

Memory Reference Instructions
LD(LoaD M into A) loads M (the 4-bit contents of
RAM pointed to by the B register: M3- Mo) into
A3-Ao. After M is loaded into A, the 2-bit "r"
operand field is EXCLUSIVE-ORed with the
contents of Br (upper 2 bits of B - RAM register
select) to point to a new RAM register for
successive memory reference operations. Since the
properties of the EXCLUSIVE-OR logiC operation
are such that a 1  9

4.3 Subroutine Techniques
Any section of program code used repeatedly
within the main program should be coded as a
subroutine, preferably on "subroutine pages" 2 or 3
for the reasons discussed above. Subroutines are
jumped to or "called" by the JSRP or JSR (double·
byte) instruction, both of which "push" the stack,
saving the next memory location address after the
subroutine call in the SA subroutine·save register.
The other subroutine·save registers are
correspondingly pushed. Subroutine nesting on the
COP420·serles is permitted to 3 levels, since this
device contains 3 subroutine·save registers.

ADD:

.PAGE 2

; START PAGE 2 CODE

ADD

; ADD SUBROUTINE - ADDS TWO
; BCD DIGITS; RESULT TO A

AISC

OVERFLOW AND SKIP IF RESULT
>9
RETURN WITHOUT SKIP (RESULT
.. 9)
RETURN THEN SKIP (RESULT> 9)

RET
RETSK

2-52

o

4.4 Utility Routines

o"'0

Programmers often build a library of basic routines
which are useful in numerous applications. This
and the following sections provide examples of
several such "utility" routines.

~
'"

~

3_.

Register Move Routine
It is often necessary to move data from one
memory register to another. The following are
examples of this type of routine. Note that the
routines may be easily modified to perform moves
in the opposite direction (e.g., from register 1 to 0)
or to include a move of register 1 to 2.

~

c:
t/)
(I)

'"'t.

t/)

C)

c

ADJACENT MEMORY MOVE ROUTINE
;
;
;
;
;

ADJACENT MEMORY REGISTER MOVE, MULTIPLE ENTRY POINT SUBROUTINE
MOVOT1: MOVE MEMORY REGISTER 0 TO REGISTER 1 ENTRY POINT
MOV2T3: MOVE MEMORY REGISTER 2 TO REGISTER 3 ENTRY POINT
ROUTINE MOVES DIGITS 15 THROUGH 0
PREVIOUS CONTENTS OF A AND B ARE LOST

MOVOT1:
MOV2T3:
MOV:

LBI
LBI
LD
XDS
JP
RET

0,15
2,15
1
1
MOV

; POINT TO M(0,15)
; NOTE LBI SUCCESSIVE SKIP FEATURE
; TRANSFER M TO A; EXCLUSIVE·OR 1 WITH BR
; EXCHANGE A WITH M; EXCLUSIVE·OR 1 WITH BR; DECREMENT BD
; JUMP TO "MOV" IF MORE DIGITS TO MOVE
; RETURN WHEN XDS SKIPS (LAST DIGIT MOVED)

DATA MEMORY SHIFT AND ROTATE ROUTINES
;
;
;
;
;
;
;

MULTIPLE ENTRY POINT SUBROUTINE TO RIGHT SHIFT MEMORY REGISTER 0,1,2, OR 3 ONE DIGIT POSITION
ZEROS ARE SHIFTED INTO DIGIT 15
PREVIOUS CONTENTS OF A AND B ARE LOST
RSHO: RIGHT SHIFT REGISTER 0 ENTRY POINT
RSH1: RIGHT SHIFT REGISTER 1 ENTRY POINT
RSH2: RIGHT SHIFT REGISTER 2 ENTRY POINT
RSH3: RIGHT SHIFT REGISTER 3 ENTRY POINT

RSHO:
RSH1:
RSH2:
RSH3:
SHFTR:

LBI
LBI
LBI
LBI
CLRA
XDS
JP
RET

0,15
1,15
2,15
3,15

SHFTR

; POINT TO DIGIT 15 IN APPROPRIATE REGISTER
; NOTE LBI SUCCESSIVE SKIP FEATURE

;
;
;
;

ZEROS IN FIRST DIGIT (DIGIT 15)
SHIFT RIGHT'
CONTINUE UNTIL ENTIRE REGISTER SHIFTED
RETURN WHEN FINISHED ("XDS" SKIPS)

"NOTE THAT THE ABOVE ROUTINE CAN SHIFT THE REGISTERS ONE DIGIT TO THE LEFT USING THE "XIS" INSTRUCTION IN PLACE OF
"XDS" AND STARTING AT DIGIT O.
; MULTIPLE ENTRY POINT SUBROUTINE TO LEFT SHIFT THE BITS OF A MEMORY DIGIT
; UPON ENTRY, BMUST POINT TO THE DIGIT TO BE SHIFTED
; ZEROS ARE SHIFTED IN FROM THE RIGHT
; PREVIOUS CONTENTS OF A ARE LOST
; LEF1: SHIFT DIGIT LEFT 1 BIT ENTRY POINT
; LEF2: SHIFT DIGIT LEFT 2 BITS ENTRY POINT
; LEF3: SHIFT DIGIT LEFT 3 BITS ENTRY POINT
LEF3:

LEF2:

LEF1:

LD
ADD
X
LD
ADD
X
LD
ADD
X
RET

DIGIT TO A
ADD DIGIT TO ITSELF
SHIFTED DIGIT TO MEMORY

2·53

c::
(I)

;
;
;
;
;
;

MULTIPLE ENTRY POINT SUBROUTINE TO LEFT ROTATE THE BITS OF A MEMORY DIGIT
UPON ENTRY, B MUST POINT TO THE DIGIT TO BE ROTATED
PREVIOUS CONTENTS OF A ARE LOST
LR01: ROTATE DIGIT LEFT 1 BIT ENTRY POINT
LR02: ROTATE DIGIT LEFT 2 BITS ENTRY POINT
LR03: ROTATE DIGIT LEFT 3 BITS ENTRY POINT (SAME AS RIGHT ROTATE 1)

LOR3:
LOR2:
LOR1:

JSR
JSR
LD
ADD
X
AISC
RET
5MB
RET

LR01
LR01

0

; ROTATE 1, THEN 2 MORE
; DIGIT TO A
; ADD DIGIT TO ITSELF
; EXCHANGE M WITH A
; WAS MEMORY BIT3 ON?
; NO, RETURN
; YES, WRAP AROUND BITO

ACCUMULATOR SHIFT ROUTINE:
; SUBROUTINE TO LEFT SHIFT BITS OF A BY USING THE SIO REGISTER (SIO MUST BE ENABLED AS A SERIAL SHIFT REGISTER)
; SI MUST BE CONNECTED TO LOGIC "0" (GROUND)
; ZEROS ARE SHIFTED IN FROM THE RIGHT
; LFTA1: LEFT SHIFT A 1 BIT ENTRY POINT
; LFTA2: LEFT SHIFT A 2 BITS ENTRY POINT
; LFTA3: LEFT SHIFT A 3 BITS ENTRY POINT
LFTA1:
LFT2:
LFTA2:
LFT3:
LFTA3:

XAS
XAS
RET
XAS
JP
XAS
JP

; ATO SIO
; SIO TO A (SIO SHIFT RIGHT 1 BIT)

LFT2
LFT3

;
;
;
;

ATO SIO
DELAY 1 INSTRUCTION CYCLE TIME ATO SIO
DELAY 1 INSTRUCTION CYCLE TIME -

SIO SHIFT RIGHT 1 MORE BIT
SI SHIFT RIGHT 2 MORE BITS

CLEAR DATA MEMORY ROUTINE:
; SUBROUTINE TO CLEAR ALL RAM
; CLEAR REGISTERS 3 THROUGH 0 IN SUCCESSION, THEN RETURN
CLRAM:
CLR:

LBI
CLRA
XDS
JP
XABR
AISC
RET
XABR
JP

3,15

CLR
15

CLR

; START BY CLEARING REGISTER 3
; OTO A
; EXCHANGE WITH DIGIT 15, DECREMENT DIGIT
; CONTINUE UNTIL DIGIT 0 CLEARED
'; BR TO A
; REGISTER 0 CLEARED?
; YES, RETURN
; NO, REPLACE BR -1 INTO BR
; CLEAR NEXT REGISTER

4.5 Timing Considerations
Programmers must often synchronize programs
with external events ("real·time" programming).
Such programs must be balanced with respect to
the execution times of the various branches taken
by the program. To ensure equal execution times,
program timing delays are added. There are
numerous ways of introducing timing delays, the
simplest but least efficient involving the use of
NOPs. Obviously these are appropriate for only the
shortest delays.

is more efficient for longer delays, but destroys the,
previous contents of A. Another method is to use a
"scratch'pad" counter in data memory using the
XAD instruction. For example, assuming the use of
a counter in M(3,15):
XAD
AISC
JP
:XAD

A counting loop, such as:
CLRA
AISC
JP
CONTINUE: .

.-1

3,15

.-1

;
;
;
;

COUNTER TO A; A TO M(3,15)
ADD 1 TO COUNTER UNTIL IT
OVERFLOWS·
RESTORE A THEN CONTINUE

"Note: The above timing code example shows
the use of a special assembler symbol in the
operand of the JP instruction. Namely, the
operand of the JP instruction, rather than
using a program label, references the

; AOD 1 TO A UNTIL' A
; OVERFLOWS·

2·54

assembler location counter (which equals the
address of the current program address). The
"." signifies the assembler location counter
and the value of the operand equals the
location counter minus the number of memory
bytes to the right of the "." sign. Use of the
"." location pointer symbol for transfer of
control instructions facilitates coding in
avoiding the need to create unique program
labels to reference memory addresses.

JSR
JSR

LR03
LROl

; LEFT ROTATE 3 BITS
; LEFT ROTATE 1 MORE BIT

This combination of subroutines only affects A,
while maintaining the integrity of data in the
rotated memory digit.

4.6 BCD Arithmetic Routines
BCD data manipulation routines are essential in
applications which interface with human operators
of a microcomputer system. They are easily

;
;
;
;
;

Unsigned BCD Integer Add and Subtract Routines

3_.

SUBROUTINE TO DO UNSIGNED BCD INTEGER ADD OF Rl AND RO, RESULT TO RO
EACH INTEGER OCCUPIES MEMORY DIGITS 0 (LOW ORDER) THROUGH 12 (HIGH ORDER)
ON RETURN, C = 1 INDICATES OVERFLOW
PREVIOUS CONTENTS OF A AND B ARE LOST
ENTRY POINT: BCDADD

BCDADD:
ADDL:

;
;
;
;
;
;
;

."

The following programs present unsigned BCD
integer add and subtract subroutines. Data is
stored in data memory registers 0 and 1 and is 13
digits long, occupying memory digits 0 through 12,
respectively. The most significant BCD digit is in
memory digit 12. The techniques used to
manipulate the contents of memory address
register B are common to many arithmetic routines.
The LD and XIS instructions transfer data between
memory and A. After the transfer they modify B.
LD 1 causes a "1" to be exclusive·ORed with Br.
Since, in these routines, Br is always equal to 1
when the LD 1 instruction operates upon it, Br is
always changed to O. (LD 1 causes Br to point to
memory register 0.) Similarly, XIS 1 also changes Br
to point to memory register 0, as well as
incrementing the value of Bd to pOint to the next
higher memory digit. Thus, Br "flip·flops" between
registers 1 and 0 while Bd "walks·up" the digits of
the registers.

Larger delays may be implemented by using multi·
digit RAM counters. Another technique is calling
unrelated subroutines which change registers or
memory locations not currently in use or whose net
effect on memory is null. An example of the latter
technique is illustrated below.

LBI
RC
LD
AISC
ASC
ADT
XIS
CBA
AISC
JP
RET

1,0

6

3
ADDL

; POINT TO LOW ORDER DIGIT. REGISTER 1
INITIALIZE C TO "0", (NO CARRY)

;
;
;
;
;
;
;
;
;
;

MOVE Rl DIGIT TO A, POINT TO SAME DIGIT IN RO
ADD BCD CORRECTION FACTOR OF 6 TO A
ADD RO DIGIT TO Rl DIGIT
RESTORE BCD VALUE IF BCD CORRECTION NOT NECESSARY
MOVE SUM DIGIT-TO RO: POINT TO Rl, NEXT HIGHER DIGIT
BD TO A
LAST DIGITS ADDED?
NO, ADD NEXT HIGHER DIGITS
YES. RETURN

SUBROUTINE TO DO UNSIGNED BCD INTEGER SUBTRACT
MINUEND IS IN RO, SUBTRAHEND IS IN Rl
DIFFERENCE IS PLACED IN RO
MINUEND, SUBTRAHEND AND DIFFERENCE DIGITS EACH OCCUPY MEMORY DIGITS 0 (LOW ORDER) THROUGH 12 (HIGH ORDER)
ON RETURN: C = 1 INDICATES NO BORROW. C = 0 INDICATES BORROW
PREVIOUS CONTENTS OF A AND B ARE LOST
ENTRY POINT: BCDSUB

BCDSUB:
SUB:

LBI
SC
LD
CASC
ADT
XIS
CBA
AISC
JP
RET

1.0

SUB

; POINT TO LOW ORDER DIGIT IN Rl
; INITIALIZE C TO "1" (NO BORROW)
; LOAD Rl DIGIT TO A. POINT TO SAME DIGIT IN RO
; SUBTRACT Rl DIGIT FROM RO DIGIT
; BCD ADJUST IF BORROW (C = 0)
; PLACE DIFFERENCE DIGIT IN RO, POINT TO NEXT HIGHER DIGIT IN Rl
; BDTO A
; HIGH ORDER DIGITS (12) SUBTRACTED?
: NO, SUBTRACT NEXT HIGHER DIGITS
; YES. RETURN

2-55

o

translated to and from codes used by decimal
displays and keyboards. The COP400 series
instruction set and internal architecture has been
deSigned to perform BCD routines efficiently. The
following routines are examples of simple BCD
data manipulation routines.

o

CI.!
;c

~

~

c:
(/)

CD
""to

(/)

G')
C

c::
CD

BCD Integer Multiply Routine

This routine will multiply the contents of data
memory register 2 with register 1, placing the. result
in register 2 (digits 0-12). It also cal,ls the BCD add
routine ("BCDADD") given above. Note that a loop·
counter is contained in M(0,13) which causes the
program to return after all 12 digits have been
multiplied. Also note the alternate·return feature of
page 3 subroutine TMZERO (Test Memory Digit =0).
A flowchart for the routine is given in Figure 4.2.

; TWO;LEVEL BCD INTE~ER·MULTIPLX Sl;BROUTINE
; 12 DIGIT BCD INTEGER CONTAINED IN REGISTER 1, DIGITS 0 - 12 (LOW ORDER TO HIGH ORDER) MULTIPLIED BY 12 DIGIT BCD
; INTEGER CONTAINED IN REGISTER 2, DIGITS 0 - 12 (LOW ORDER TO HIGH ORDER), RESULT TO REGISTER 2
; MULTIPLICATION OF DIGITS PERFORMED BY MULTIPLE ADDITIONS OF REGISTER 1 ACCORDING TO VALUE OF REGISTER 2
; DIGITS
; DIGIT ADDITION RESULTS TEMPORARILY STORED IN RO·AND CONSECUTIVELY RIGHT SHIFTED INTO RESULT REGISTER 2, HIGH
; ORDER DIGIT
; ENTRY POINT: MULT
; SUBROUTINES CALLED: RSHRO, RSHR2, CLR. DEC 1, INC 1, TMZERO, BCDADD
MULT:
MULT1;

NOTZ:

;
;
;
;

LBI
JSR
LBI
JSR
JP
JSR
JSR
LBI
LD
AISC
JP
RET
JSR
JP
JSR
JSR
JP

0,13
CLR
2,0
TMZERO
NOTZ
RSHRO
RSHR2
0,13

.+2
INC1
MULT1
DEC1
BCDADD
MULT1

; POINT TO M(O,13)
; CLEAR REGISTER 0, DIGITS 13 - 0
; POINT TO M(2,O)
; IS M(2,O); O?
; NO, JUMP TO NOTZ
; YES, RIGHT SHIFT REGISTER 0, DIGITS 12 - 0
.; RIGHT SHIFT REGISTER 2, DIGITS 12 - 0
; POINT TO LOOP COUNTER
; LOOP COUNTER TO A
; IS COUNTER> 12
; NO, CONTINUE
; YES, ALL DIGITS MULTIPLIED, RETURN
; CONTINUE, INCREMENT LOOP COUNTER DIGIT
; MULTIPLY NEXT HIGHER ORDER DIGITS
; DECREMENT M(2,0)
; ADD RO, DIGITS 0 - 12, TO R1, DIGITS 0 - 12, RESULT TO RO
; JUMP BACK TO MULT 1

MULTIPLE ENTRY POINT SUBROUTINE TO RIGHT SHIFT DIGITS 12 - 0 OF REGISTERO OR 2
ON RETURN A CONTAINS LOW ORDER REGISTER DIGIT
RSHRO: RIGHT SHIFT DIGITS OF REGISTER 0 ENTRY POINT
RSHR2: RIGHT SHIFT DIGITS OF REGISTER 2 ENTRY POINT

RSHRO:
RSHR2:
RSH:

LBI
LBI
XDS
JP
RET

0,12
2,12

POINT TO HIGH ORDER DIGIT, REGISTER 0
POINT TO HIGH ORDER DIGIT, REGISTER 2
SHIFT RIGHT DIGITS 12 - 0 IN REGISTER

RSH

2-56

; SUBROUTINE TO CLEAR ALL DIGITS TO THE RIGHT AND INCLUSIVE OF A HIGH·ORDER DIGIT OF A REGISTER
; ON ENTRY, B MUST POINT TO THE REGISTER AND HIGH ORDER DIGIT NUMBER
CLR:

;
;
;
;

CLRA
XDS
JP
RET

; CLEAR REGISTER, STARTING WITH HIGH ORDER DIGIT
CLR
; RETURN WHEN DIGIT

a CLEARED

MULTIPLE ENTRY SUBROUTINE TO EITHER DECREMENT OR INCREMENT BY 1 THE VALUE OF A MEMORY DIGIT
ON ENTRY, B MUST POINT TO THE DIGIT TO BE OPERATED UPON
DEC1: ENTRY POINT TO DECREMENT A DIGIT
INC1: ENTRY POINT TO INCREMENT A DIGIT

DEC1:
AD EX:

INC1:

CLRA
COMP
ADD
X
RET
CLRA
AISC
JP

;
;
;
;
1
ADEX

15 TO A
ADD MEMORY DIGIT TO A
EXCHANGE BACK TO MEMORY
RETURN

; 1 TO A
; ADD AND EXCHANGE WITH MEMORY DIGIT

; SUBROUTINE TO TEST MEMORY DIGIT EQUAL TO ZERO
; ON ENTRY, B MUST POINT TO MEMORY DIGIT TO BE TESTED
; ON RETURN, SKIP FIRST INSTRUCTION IF MEMORY DIGIT EQUAL TO ZERO
; NORMAL RETURN IF MEMORY DIGIT NOT EQUAL TO ZERO
TMZERO:

CLRA
SKE
RET
RETSK

;OTO A
; DIGIT = ZERO?
; NO, NORMAL RETURN
; YES, RETURN TH EN SKI P

4.7 Simple Display Loop Routine
Due to these considerations, page 4, words 0-9
should equal the 8·bit, seven-segment decode
lookup data for the BCD digits 0-9 respectively. (In
this example the low-order bit - decimal point of each lookup data word is reset, signifying that
the decimal point is off.) ROM seven-segment
decode lookup data is placed in ROM memory
locations by the Assembler WORD directive. (See
PDS User's Manual, Section 8.4.)

The following routine is a Simple LED display loop
routine. It illustrates the use of LEI and LQID
instructions, both designed to facilitate the
outputting of segment data to a multiplexed
display. As explained in Section 3.2, LEI Instruction
description, setting bit 2 of the EN register enables
o latch (segment) data to the L I/O ports; resetting
EN2 disables the L I/O ports, providing segment
blanking for the LED display. EN2 is set and reset,
respectively, by the LEI4 and LEI 0 instructions.

Another feature of this routine is the dual function
of Bd. Its value may be output directly to the D
outputs to select one of 16 digits of the
multiplexed display (assuming the D outputs are
connected to a 1-of·16 decoder/driver device). Also,
its value is used to select one of 16 RAM digits
whose contents are used by the LOID instruction to
access the segment data to be output to the
selected digit. To faCilitate coding (by avoiding the
need to change the value of Bd after its contents
are output to D to select or display digit), RAM digit
locations should correspond to the digit of the
display. In other words, RAM digits 0-15 should
contain, respectively, the LOID pointers to segment
data for display digits 0-15. This technique, used
below, allows Bd to first enable the appropriate
display digit and then, without its value being
changed, to point to the RAM digit used to access
the segment data for the same display digit.

As explained in Sections 3.2 and 4.1, LQID loads
the 8-bit 0 register with the contents of a ROM
location pointed to by A and M (ROM "lookup" data
must be within the same 4·page ROM block as the
LQID instruction). In this example, since A is
always equal to 0 at the time of the LOID
instruction, the ROM data accessed by this
instruction must be within the first 16 words of the
first page of the ROM block in which the LQID
instruction is located as pOinted to by the 4-bit
contents of M (Pg and Ps remain the same, Pr P4
equal "0"). For example, if, as is the case for the
following routine, LQID is in page 5, it will lookup
data within one of the first 16 locations of page 4.
The value of the contents of the memory digit
pOinted to by the B register at the time of the LOID
instruction determines which one of the 16 words
is accessed (e.g., if M = 2, word 2 is loaded into Q).

2·57

Q\1
3_.

; SEVEN·SEGMENT DECODE DATA TABLE:
; ROM BITS 17 - 10;SA - SG, D.P. (DECIMAL POINT) BITS, RESPECTIVELY

LOOKUP:

.PAGE
.wORD
.WORD
.wORD
.WORD
.wORD
.wORD
.wORD
.wORD
.wORD
.WORD

X'FC
X'60
X'DA
X'F2
/<'66
X'B6
X'BE
X'EO
X'F4
X'F6

; PLACE LOOKUP DATA IN WORDS 0 - 9, PAGE 4
;;0 (SEVEN·SEGMENT DECODE HEX VALUES)
;;1

;;2
;;3
;;4

;;5
;;6
;;7
;;8

;;9
; NEXT FIVE LOCATIONS CAN BE USED FOR SPECIAL ALPHABI'TICAL DISPLAY
; CHARACTER DATA

enQ.
::E

oo

; BEGIN CODE FOR DISPLAY LOOP

DSPLY:
lOOP:

.PAGE
LBI
CLRA
LEI
OBD
LQID
LEI
CBA
AISC
JP
CAB
JP

0,15

15

.+3
LOOP

; PLACE FOLLOWING CODE ON PAGE 5
; POINT TO HIGH ORDER RAM DIGIT, BD; 15
; A;O FOR LOOKUP
; BLANK SEGMENTS (EN2 ;0)
; OUTPUT DIGIT VALUE
; LOOKUP DATA TO Q
; OUTPUT SEGMENT DATA (EN2; 1)
; BD TO A
; DECREMENT A
; JUMP 3 WORDS WHEN FINISHED
; A(BD-1) TO BD
; DISPLAY NEXT LOWER DIGIT
; CONTINUE WHEN FINISHED

2-58

4.8 Interrupt Service Routine
As explained in Section 3.2, LEI Instruction
description, setting bit 1 of the EN register enables
the COP420·series and COP444L IN1 input as an
interrupt input, responding to low going pulses.
Upon the occurrence of an interrupt signal, the
subroutine stacl~ is pushed and program control is
transferred to the last word of page 3 (address
OFF 16). The following routine contains code which
may be placed at the beginning and end of the
interrupt service routine to save the contents of A,
C and S, freeing them for use by the interrupt
routine. At the end of the routine the previous
contents of A, C and S are restored for use by the
main program. It should be noted that the main
program need only enable IN1 as an interrupt input
once; thereafter, the interrupt service routine, itself,
re-enables interrupt servicing (LEI 1 instruction
before return).
;
;
;
;

QV

3_.

~

c::
(J)

C'D
..".

(J)

G)
C

c:
C'D

INTERRUPT SERVICE ROUTINE TO SAVE AND RESTORE THE CONTENTS OF A, C AND B (BR AND BO) IN MEMORY REGISTER 0,
DIGITS a - 2.
AUTOMATIC ENTRY TO LAST WORD OF PAGE 3
ON RETURN, IN1 INPUT RE·ENABLEO AS INTERRUPT INPUT

INTSER:

NOP
XAO
CBA
XAO
XABR
SKC
AISC
XAO

LOO
RC
AISC
SC
XABR
LOO
CAB
LOO
LEI
RET

0,0
0,1

8
0,2

0,2

0,1
0,0

;
;
;
;
;
;
;
;
;

FIRST INTERRUPT ROUTINE INSTRUCTION MUST BE A NOP (LOCATION X'FF)
SAVE A IN M(O,O)
BO TO A
SAVE BO IN M(0,1)
BR TO A
CARRY = 1?
NO, SET A3
SAVE C AND BR IN M(0,2)
PERFORM INTERRUPT ROUTINE

;
;
;
;
;
;
;
;
;
;

M(0,2) (C AN 0 BR) TO A
RESET CARRY
A3 SET (SAVED CARRY = a)?
NO, RESTORE CARRY = 1
RESTORE BR
M(0,1) (BO) TO A
RESTORE BO
M(O,O) TO A, RESTORE A
ENABLE INTERRUPT (SET IN1)
RETURN FROM INTERRUPT SERVICE ROUTINE

4.9 Timekeeping Routine
The following multilevel subroutine counts time in
a 12·hour format. It relies on the COP420 system
oscillator, itself (controlled by an inexpensive
3.58 MHz color TV crystal), and the COP420 internal
time·base counter for a real-time base, rather than
on a 60 Hz external input. The subroutine is entered
each time the SKT instruction skips, indicating
time-base counter overflow. As explained in Section
3.2, SKT Instruction description, overflow frequency
is dependent upon the frequency of the
COPSTMsystem oscillator. This frequency equals
the oscillator frequency, first divided by 16 by the
instruction cycle divider, then by 1024 by the
internal 10-bit time-base counter. In this case the
SKT overflow fr~quency will equal a fractional

number: 218.478 Hz (3.58 MHz divided by 16, divided
by 1024). Consequently, the timekeeping calling
routine must execute a SKT instruction at least
once approximately each 218 Hz to ensure that
each SKT overflow is detected.
As indicated above, using an inexpensive TV
crystal results in a fractional SKT frequency.
Program compensation techniques, therefore, must
be employed to derive an integer which may be
used by the program in counting seconds, the
basic timekeeping units.

2·59

• Using a 3.58MHz crystal resulting in a
218.478 Hz SKT frequency, an SKT integer count
of 786,521 is obtained each hour (218.478 x 3600
seconds/hour).

This routine derives this integer and utilizes it to
keep accurate time in the following manner:
• A 2-dlgit binary "SKT" counter In RAM is
Initialized to different val ues at different times
during the course of an hour so that the total
counts for the hour equal an integer which
corresponds to the 218.478 Hz SKT frequency.

• Using the above compensation scheme, the
same number of "SKT" counts (786,521) is
required to increment the time by 1 hour. This
follows since 392,400 counts are required by the
"odd" seconds compensation (30 x 60 x 218
counts); 381,060 by the "even" seconds
compensation (29 x 60 x 219 counts); 12,862 by
the "minutes" compensation (59 x 218 counts)
and 199 by the "hours" compensation resulting in a total hours count of 786,521.

• Every odd second in the range of 0- 59 seconds,
the SKT counter Is set to 218, decremented by 1
each time the SKT instruction skips. When
decremented to 0, a 2-digit BCD "seconds"
counter in RAM is incremented by 1. (The
seconds counter overflows every 60 counts to a
2-digit BCD "minute" counter. The minutes
counter overflows every 60 counts to a 1-digit
"hours" counter.)

A flowchart and a RAM map for this routine are
provided in Figure 4.3. Note that an assembler
assignment statement is used in the assembler
source code to equate the address of low order
digits of the RAM SKT counter and seconds
counter with the symbols "COUNT" and "SECS,"
respectively. This provides clearer documentation
of the program since an instruction referencing the
seconds counter, for instance, can use the word
"SECS" instead of a numerical value in the
operand field (i.e., LBI SECS). For further
information on the assignment statement, see PDS
USI!"s Manual, Section 8.4. Also note that the
program initializes the SKT counter to 218, 219 and
199, respectively, by loading its two digits with the
following binary equivalent pairs (high-order value,
low-order value): 13, 10; 13, 11; and 12,7.

• Every even second in the range of 0- 59 seconds,
the SKT counter is set to 219 and decremented
by 1, as above, each time the SKT pulse occ,urs.
• Every minute In the range of 0-59 minutes, the
SKT counter is set to 218 and decremented as
above.
• Every hour, the SKT counter is set to 199 and
decremented as above.
The above compensation techniques result in a
timekeeping routine which Is accurate at the end of
each hour. (During the hour, inaccuracy is
extremely small.) The basis for the above
compensation scheme is as follows:

2-60

placed in separate "utility" files on a disk. They
can then be added or included, when needed, to
main programs at a later date. For an example of a
program which includes this "TIMEKP" subroutine
(using the assembler .INCLD directive), see Figure
5.18.

This subroutine is coded to reside on subroutine
page 2. The source code provided below also
illustrates the use of the PDS Assembler .LOCAL
directive and local symbol labels. Specifically, the
program begins and ends with a .LOCAL directive,
making the memory addresses between them a
local region. Within this local region, local symbols
(labels whose first character is a "$") will be
defined only within the local region - they will not
conflict with labels appearing in other portions of
program source code. This relieves the programmer
from worry about duplicate label definitions,
allowing the subroutine or other utility program to
be included or added to different programs,
regardless of the labels used by these other
programs.

Local symbols must begin with a "$" and be
unique within the particular local region in the first
4 characters following the "$." The programmer
may, as is done in this example, use local labels
with more than four characters for convenience
and, although not "recognized" by the assembler,
these extra characters will be printed out on the
assembler output listing. Note: The label of the
starting address of a local utility routine must be a
long (regular) label, since it will be referenced by a
portion of the program outside of the local region
(e.g., "TIMEKP" is not a local label).

In effect, therefore, utility programs or commonly
used subroutines may be coded in this manner and

; PAGE 2 SUBROUTINE TO KEEP TIME IN A 12·HOUR FORMAT USING A 3.58 MHZ TV CRYSTAL
; 2·DIGIT "SKT"" COUNTER CONTAINED IN M(2.15) - M(2.14): HIGH· TO LOW·ORDER
; 1·DIGIT BINARY HOURS COUNTER IN M(2.13)
; 2·DIGIT BCD MINUTES COUNTER IN M(2,12) - M(2,11): HIGH- TO LOW-ORDER
; 2-DIGIT BCD SECONDS COUNTER IN M(2,1O) - M(2,9): HIGH- TO LOW-ORDER
; ENTRY POINT: TIMEKP; ENTRY UPON SKT INSTRUCTION OVERFLOW
; SUBROUTINES CALLED: INC2
.PAGE
.LOCAL
$COUNT
$SECS

=2,14
=2,9

;
;
;
;

PAGE 2 SUBROUTINE
CREATE LOCAL REGION FOR LOCAL SYMBOLS
ASSIGN "COUNT" = ADDRESS OF LOW-ORDER SKT COUNTER DIGIT
ASSIGN "SECS" = ADDRESS OF LOW-ORDER SECONDS COUNTER DIGIT

;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;

POINT TO LOW-ORDER DIGIT OF SKT COUNTER
LOAD DIGIT TO A
DIGIT = o? (A = DIGIT -1)
YES, TEST HIGH-ORDER DIGIT
NO, EXCHANGE DIGIT -1 INTO M
RETURN UNTIL NEXT SKT OVERFLOW
REPLACE DIGIT IN COUNTER, INCREMENT BD
JUMP BACK AND TEST HIGH-ORDER DIGIT - IF ALREADY TESTED AND =0,
SKIP AND CONTINUE
POINT TO LOW-ORDER SECS DIGIT
INCREMENT SECS COUNTER
SECS < 60, TEST SECS FOR ODD OR EVEN
SECS= 60, TO HIGH-ORDER DIGIT, POINT TO LOW-ORDER M!NS DIGIT
INCREMENT MINS COUNTER
MINS < 60, SET COUNTER = 218
MINS = 60, TO HIGH-ORDER DIGIT, POINT TO HOURS DIGIT
LOAD HOURS DIGIT TO A
INCREMENT HOURS
PLACE IN M, PREVIOUS HRS TO A
HOURS> 12?
NO, SET COUNTER = 199
YES, SET HOURS = 1
POINT TO LOW-ORDER COUNTER DIGIT
SET COUNTER = 199 (BINARY 12,7)

;
;
;
;
;
;

RETURN UNTIL NEXT SKT OVERFLOW
POINT TO LOW-ORDER SECS DIGIT
SECS ODD?
YES, SET COUNTER=218 (BINARY 13,10)
NO, POINT TO LOW-ORDER COUNTER DIGIT
SET COUNTER=219 (BINARY 13,11)

TIMEKP:

$HIGHTST:

$C199:

$TSEC:

$C219:
$C21X
$C218:

LBI
LD
AISC
JP
X
RET
XIS
JP
LBI
JSR
JP
STII
JSR
JP
STII
LD
AISC
X
AISC
JP
STII
LBI
STII
STII
RET
LBI
SKMBZ
JP
LBI
STII
STI113
RET
LBI
STII
JP

$COUNT
15
$HIGHST

TIMEKP+ 1
$SECS
$INC2
$TSEC

°

$INC2
$C218

$C199
1
$COUNT

°

°

12
$SECS

°

$C218
$COUNT
11

COUNT
. 10
$C21X

POINT TO LOW-ORDER COUNTER DIGIT
SET COUNTER = 218
JUMP TO "C21X" THEN RETURN

2-61

; SUBROUTINE TO INCREMENT A 2-DIGIT BCD RAM COUNTER
; ON'ENTRY, B MUST POINT TO LOW-ORDER DIGIT OF COUNTER
; ENTRY POINT: INC2
; NORMAL RETURN IF 2-DIGIT VALUE LESS THAN 60
; RETURN THEN SKIP IF 2-DIGIT VALUE EQUAL TO 60
; BOTH RETURNS EXIT WITH B POINTING TO HIGH-ORDER DIGIT
$INC2:
SC
CLRA
AISC
ASC
ADT
XIS
CLRA
AISC
ASC
ADT

6

6

X
LD
AISC
RET
RETSK
_LOCAL

10

; INITIALIZE C TO 1 TO ADD TO LOW-ORDER DIGIT
; ZERO TO A
; BCD ADJUST RESULT IF NECESSARY
; I F RESULT> 9, LOW ORDER DIGIT = 0
; PLACE INCREMENTED DIGIT IN M, POINT TO HIGH-ORDER DIGIT
; ZERO TO A
; ADD CARRY, IF PROPAGATED FROM LOW-ORDER DIGIT TO HIGH-ORDER DIGIT
;
;
;
;
;
;
;

BCD RESULT IF NECESSARY
REPLACE DIGIT IN M
LOAD HIGH-ORDER DIGIT INTO A
HIGH-ORDER DIGIT = 6 (COUNT = 60)?
NO, NORMAL RETURN
YES, RETURN THEN SKIP
END LOCAL REGION

4.10 String Search Routine.
character tests, using the simple character test
instructions provided below containing modified
LDD instructions whose operands specify the
additional characters to be matched. Also, the code
may be easily modified to search through more
than one RAM register for a match.

It is often necessary to search data memory for a
string of characters. The following routine searches
register 0 for a match with three contiguous 4·bit
characters, "X," "Y," and "Z," Note that a match
with more than three characters is easily
accommodated by providing for additional
;
;
;
;
;
;

SUBROUTINE TO SEARCH STRING OF DATA MEMORY CHARACTERS FOR A MATCH WITH "X," "Y," AND "Z" CONTIGUOUS
CHARACTERS
16 4-BIT CHARACTERS ASSUMED STORED IN M(0,15) THROUGH M(O,O)
"X," "Y," AND "Z" CHARACTERS ASSUMED STORED IN AND ASSIGNED VALUES OF M(1,15) THROUGH M(1,13), RESPECTIVELY
NORMAL RETURN IF NO MATCH
RETURN THEN SKIP IF MATCH OCCURS WITH THE ACCUMULATOR CONTAINING THE DIGIT NUMBER OF "X"
X=1,15
Y=1,14
Z=1.13

SEARCH:
LBI

0,15

; POINT TO M(O,15)

LDD
SKE
JP
XDS
JP

X

; XTOA
; X FOUND?
; NO, JUMP TO X
; YES, POINT TO NEXT LOWER DIGIT
; LOOK FOR Y MATCH, IF AT M(O.O) SKIP AND NORMAL RETURN -

LOOKX:

NOX
LOOKY

NO MATCH

NOX:
LD
XDS
JP
RET

LOOKX

; DECREMENT DIGIT POINTER
; LOOK AGAIN FOR X MATCH, IF AT M(O.O), SKIP AND NORMAL RETURN ; MATCH

NO

LOOKY:
LDD
SKE
JP
XDS
JP
RET

Y

LDD
SKE
JP
DBA
AISC
RETSK

Z

LOOKX
LOOKX

;YTOA
; Y FOUND?
; NO, TRY AGAIN
; YES, POINT TO NEXT LOWER DIGIT
; LOOK FOR Z MATCH, IF AT M(O,O), SKIP AND NORMAL RETURN -

LOOKZ;

LOOKX
2

;ZTO A
; Z FOUND?
; NO. TRY AGAIN
; YES, MATCH COMPLETE, COPY Z DIGIT ADDRESS TO A
; ADD 2 TO A TO EQUAL X DIGIT ADDRESS
; RETURN THEN SKIP - MATCH FOUND

2·62

NO MATCH

4.11 Programming Techniques for the
COP421·Series, COP410L and COP411L

words, limiting program code to eight pages
(pages 0- 7). RAM consists of a 32 x 4·bit RAM,
organized as four RAM registers (0-3) conSisting
of 8 4-bit digits (9-15,0). The LBI register
reference instruction should, therefore, contain a
"d" field equal to 9-15 or O. Since all LBls will
reference RAM digits 9-15 or 0, all LBls are
single·byte instructions, occupying one word in
program memory. A field restriction occurs with
respect to the memory reference XAD
instruction: only an XAD 3,15 instruction is valid,
limiting its use to reference a RAM
"scratch·pad" digit contained in M(3, 15) only.

COP421·Serles Programming
Since the COP421-series differs from the COP420series only in not having the IN3-INo Inputs, the
foregoing programming considerationll and
examples for the COP420-series are, for the most
part, relevant to COP421-series programming_
However, due to its lack of IN inputs, the COP421series does not include the ININ instruction, and its
INIL instruction inputs only CKO into A (when CKO
is programmed as a general-purpo!;e input)_ The
following'are the results Of these COP421
differences:

2. The COP410UCOP411 L has 2 subroutine save
registers, SA and SB. Only two levels of
subroutine nesting, therefore, are allowed. The
programmer should also realize that since LQID
push~s and pops the stack in performing the
operation associated with this instruction, only 1
level of subroutine nesting should be in effect at
the time of the execution of this instruction.
(Otherwise the second level of previous
subroutine nesting will be disrupted - the
previous contents of SB will be lost.)

1_ MICROBUSTtoj interface programming is not
available since IN3-INo cannot be maskprogrammed as WR, CS, and RD, respectively_
Also, Go cannot be mask-programmed as a
"ready" output to facilitate "handshaking" with
a host CPU over the MICROBUSTM bus_ The
COP421 may still, however, function as a CPU
peripheral component, relying on more general,
programmed 110 techniques.
2. Due to the lack of IN inputs, other bidirectional
110 pins must be used as general purpose input
pins when implementing a programmed input
operation.

3. Since the COP410UCOP411L does not have an
internal divide-by-1024 time-base counter, the
SKT instruction is not available. "Real·time"
routines, such as 12·hour timekeeping and the
like, must rely on external time-base inputs in
order to derive a time-base for such routines
(e.g., external 50/60 Hz input for time-of-day
routines).

3. A hardware interrupt utilizing IN , is not possible.
(Setting EN, has no effect on the operation of
any COP421.) Any interrupt servicing must be
accomplished using software interrupt
techniques. (The routine provided in Section 4.8
is inapplicable to the COP421-series.)

4. Certain deleted or altered instructions have
already been mentioned: INIL, ININ, and SKT are not
available; LBls must have a "d" field
equal to 9-15 or 0, and XAD's
operand must equal 3,15. The following
instructions have also been deleted from the
COP410UCOP411L instruction set. To the right
of each of the following deleted instructions,
where appropriate, alternative
COP410UCOP411L instructions are shown
which, when executed in succession, will
perform the same or similar operation as the
deleted instruction:

4. A software Interrupt cannot rely on the inputting
and testing of the IL3 or ILa latches associated
with IN3 and INo Inputs. Software interrupts,
therefore, require that the interrupt signal be tied
to one of the non-latched input pins. As a result,
the input interrupt signal must be input and
tested at least once during each "low" and
"high" pulse occurring during each period of the
Signal. For example, If the interrupt signal is a
50% duty cycle, 60Hz square wave, it must be
tested at least twice every 1,\;0 second.
COP410UCOP411L Programming
Since the COP410UCOP411L, as with the COP421·
series, does not have IN Inputs, the above
programming considflrations relating to the
COP421 apply as well as to COP410UCOP411L
programming. Also, since, as discussed below,
other hardware logic elements are not Included In
the archit,ecture of the COP410L, the following
additional considerations apply to COP410L
programming:

Deleted

Alternative
COP410UCOP411L

Instructions

Instructions

LOO
CASC
AOT
COMA
OGI
XABR
SKT
ININ
INIL

LBI, LO
COMP, ASC
AISC 10, NOP
INL
OMG

For further information on deleted or altered
COP410UCOP411L instructions and the operations
performed by the alternative instructions given
above, see Section 3.4.

1. The COP410UCOP411L has one-half the ROM
and RAM of the COP420-series and COP421series. ROM, therefore, consists of 512 x 8-blt

2-63

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5

COP400 1/0 Techniques

This chapter provides information and examples
pertaining to hardware and software interfacing
techniques for the COP400 Microcontrollers. The
information contained in this chapter is derived, in
large part, from material already provided in
previous chapters, particularly Chapter 2. The
reader should refer to this chapter when reading
the following material to obtain a complete picture
of the COP400 series 1/0 characteristics and
capability.

5.1 Hardware Interfacing Techniques
COP420 1/0
Figure 5.1 depictsthe 1/0 lines associated with the
COP420. As indicated, there are 24 1/0 lines. The
following discussion provides information on the
capabilities of the mask'programmable 1/0 options
associated with the COP420. These optional
configurations are shown in Figure 5.2.
COP420 Inputs

The following text provides 1/0 examples for the
COP420 specifically. The 1/0 capability of the other
members of the COP420·series (e.g., COP420L and
COP420C), the COP444L and other, less inclusive
devices, the COP410L and COP411 L, are
summarized in Table 5.1.

COP420 inputs may be programmed either with a
depletion·load device to Vee or. floating (Hi·Z input).
All inputs are TTUCMOS compatible. Hi·Z inputs
should not be left floating; they should be
connected to the output of a "high" and "low"
driving device if active or to Vee or ground if
unused. Inputs may also be optionally programmed
for higher trip levels for interfacing to non·TTL
sources (e.g., keyboards, switches).

2·64

o

COP420 Outputs
Standard Output: The N-channel device to ground

base of an external transistor for current sourcing
since the depletion-load device's current capability
is limited to a safe operating area_ Figure 5_3
provides a summary of the characteristics of the
COP420 Standard Output.

is good at sinking current and is compatible with
the sinking requirements of 1 TTL load (1_6mA at
OAV); it will meet the "low" voltage requirements of
CMOS logic. All output options use this device
(device # 1), as illustrated in Figure 5_2, for current
sinking_ The depletion-load device to Vce provides
low sourcing capability (100!,A at 2AV)_ While this
device meets the sourcing requirements of TTL
logic and will go to Vee to meet the "high" voltage
requirements of CMOS logic, an external resistor to
Vee may be required to interface to other external
devices requiring higher sourcing capability_ A
standard output may be connected directly to the

Open·Orain Output: The COP420 open-drain output
uses the same enhancement mode device to
ground as the standard output with the same
current sinking capability_ As its name implies, this
output configuration does not contain a load device
to Vee, allowing various external pull up techniques
as required by the user's application.

2·65

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II:

Push·Puli Output: The COP420 push·pull output
differs from the standard output configuration in
having an enhancement mode device in parallel
with the depletion·load device to Vee, providing
greater current sourcing capability and faster rise
and fall times when driving capacitive loads. This
option is available for the COP420 SO and SK
outputs, often tied to the highly capacitive clock
lines of external shift registers to provide
additional external 1/0 for the COP420. (For an
example, see Figure 5.20.) If a push·pull output is
interfaced to an external transistor, a limiting
resistor must be placed in series with the base of
the transistor to avoid excessive source current
flow out of the push·pull output.

COP420 I/O Summary
Figures 5.5 through 5.9 provide diagrams of the
internal logic and a summary of the hardware and
software features associated with the COP420 110
ports.
Interconnect Examples
Figures 5.10 through 5.14 provide interconnect
diagrams illustrating several schemes for
interconnectirig the COP420 to external devices.
Several of these interconnect diagrams, with minor
variations, are used in providing software 110
techniques in the final sections of this chapter.

Figure 5.4 summarizes, in interconnect form, the
information provided above relevant to the
capabilities of the push·pull, open drain and
standard outputs, as well as the Hi·Z and load
device input configurations.
For an example of use of the SK output, configured
as a push·pull output to drive the clock lines of an
external shift register, see Figure 5.10.
LED Direct Drive Output: The COP420 LED direct
drive output differs from the standard output
configuration in two basic ways:
1. Its depletion·load device to Vee is paralleled by
an enhancement mode device to Vee to allow for
the greater current sourcing capacity required by
the segments of an LED display. Source current
is clamped to prevent excessive source current
flow.
2. This configuration can be disabled under
program control by resetting bit 2 (EN2) of the
enable register to provide simplified display
segment blanking. However, while both
enhancement mode devices are turne!=l off in the
disabled mode, the depletion·load device taVee
will still source up to, 0.125mA when this output
is turned off. (This is not a worst case pull·up for
keyboard input loads).
For an example of' use of ttie L 1/0 ports, using this
option, to directly drive the segments of a LED and
VF display, respectively, see Figures 5.11 and 5.12.
TRI·STATE'" Push·Puli Output
This COP420 output was designed to meet the
specifications of National's MICROBUSTM,
outputting data over the data bus to a host CPU. It
has TRI·STATE'" logic to disable both
enhancement mode devices to free the
MICROBUSTM'data lines for COP420 input
operation. Figure 5.13 shows an interconnect
between a host CPU and the COP420 over the
MICROBUSTM using this Loutput option.

2·66

2-67

2·68

COP400 I/O Comparison Table

Table 5.1 provides a comparison table of the 1/0
capabilities of COP400 series devices. It should be
understood that this is a partial listing of COP400
devices, since more inclusive parts (the COP440
and its related devices) as well as other devices
will be available in the near future. For complete
information on the listed devices, as well as other
members of the COP400 Microcontroller family,
consult the appropriate data sheets.

5.3 Keyboard/Display Interface
The most common type of display consists of
several seven-segment digits (see lower right
section of Figure 5.15). Each light emitting diode
segment has two terminals and conducts current in
only one direction, Various combinations of
segments are turned on to represent numbers and
a few alphabetical characters. In our example, the
cathodes of all segments (Sa-Sg, D.P.) in a given
digit are connected together and the anodes of
corresponding segments of the different digits are
also connected together (common cathode display).

One of the primary considerations in the design of
the internal architect Lire of the COP400 family was
to allow for easy interface to keyboards and
numeric displays, the Input and output peripherals
commonly associated with small system
applications, using a minimum amount of external
circuitry. To further aid in the implementation of
such systems, the instruction set was carefully
designed to service these peripherals and handle
BCD data manipulation with a minimum amount of
external circuitry and program code. The following
sections describe a typical keyboard/display
interface. system to output BCD data stored in data
memory (RAM) to a 14·digit LED display, and input
keys witch closure data entered from a 4 x 4
keyboard matrix. In addition, the sample program
also makes provision for a timekeeping routine,
another typical user application.

The cathode or digit lines are driven by a
decoder/driver device, the DS8664, which provides a
4-to-14 buffered decode of the COP420 D outputs.
The anode or segment lines are driven directly by
the COP420 L I/O ports, utilizing the L output LED'
Direct Drive output option. A given segment is
turned on only if both its digit and segment lines
are driven.

Figures 5.15 through 5.18, respectively, provide the
hardware interconnect diagram, program flowchart,
display timing diagram and assembly source code
for the basic interface scheme. The general
approach of the interface is common to most
keyboard/display interfaces. It takes advantage of
the fact that an image persists in the eye for a
fraction of a second after the source is removed. It
is not necessary, therefore, to have all display
digits on simultaneously: the digits are sequentially
enabled (multiplexed) at a rate fast enough to avoid
noticeable flicker. Multiplexing greatly reduces the
amount of interconnect and buffer hardware
required.

Each digit of the display is multiplexed, with each
digit scanned in sequence by changing the binary
output code at the D outputs. The DS8664
decoder/driver will set a corresponding D line to a
low level to drive each cathode. At the same time
the L outputs are set at a high level to correspond
to the values necessary to turn on the segments
associated with the numeric or alphabetical
character to be displayed for the present digit. (To
display a "3" at digit 5, segments Sa, Sb, Sc, Sd
and Sg would be driven high when Ds is driven low.)

2-70

Since people operate keyboards at a rate which Is
very slow compared to the COP420 instruction
cycle time, it is possible to scan the keyboard as
well as service the display and execute the
timekeeping routine without missing a key closure.
As with the display, the keys are connected in a
matrix to minimize interconnect. Further economy
is gained by sharing the D lines with the display. In
fact, the program loop used to scan the display is

also used to scan the keyboard. When the program
addresses a display digit; It also addresses a
column in the keyboard matrix. The program
senses the closure of a particular key in that
column by testing the GilD ports which are tied to
the rows of the keyboard matrix: each key is
associated with the conjunction of one D line and
one GilD line.

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2·71

drive the segments of the LED display. An
average L output source current capability of
8mA is assumed, being midway,between the
minimum (2.5mA) and maximum (14mA) current
sourcing specifications for this output
configuration at Vee = 6V. -

The following is a list of design criteria and
considerations relevant to the sample
keyboardldisplay Interface:
1. With this design, if two keys on different G 110
lines are pressed simultaneously, key identity
may be lost. After sensing a key closure, the
program requires that the keyboard be clear (no
keys pressed) for a short duration before it will
Input another key. "Rollover" and "shift·key"
schemes may be implemented with more
sophisticated designs.

'5. To prevent flickering of the, display, the display
should be refreshed at a rate, of at least 100 Hz
(1/P In Figure 5.17).
6. The duty cycle (SIP, in Figure 5.17) must be
maintained to ensure adequate brightness, The L
port segment current capability is assumed, as
mentioned above, to be 8mA and the NSA5140
requires 0.5 mA average current. Average current
is determined by the segment duty cycle and
, should'be the average display current
requirement divided by the peak output current
or 0.5";' 8 = 1/16. Therefore, the program must be
written to ensure a duty cycle of at least 1/16 for
proper LED display brightness.

2. Multiple key closures on the same GilD line will
allow segment current to flow through the
keyboard causing display digits to be ANDed.
Key closure is still detected, however, because
the "on" driver presents a small resistanceta
GND compared to the resistance 'that the "off"
driver and G port present to Vce. The ANDing of
display digits may be prevented by placing
diodes on each digit line. If key identity must be
maintained when more than two keys are,closed,
a diode must be placed in series with each
keyswitch.

7. Each segment on time, (S in Figure 5.17) must be
the same width to ensure that all digits are
uniformly bright.

3. For this design, the G ports are configured as
standard outputs (options 21- 24 = 0). The
program itself sets them each to "1" at the
beginning and on each pass through the main
program loop. When all keys in the associated
matrix row are up, the port will read as a "1."
When a key Is closed, its corresponding D line
will pull the associated G port low, with a "0,"
therefore signifying key closure.

8. Since keyswitches bounce, the program must de·
bounce or filter the signals on the G lines. This
Is achieved by requiring that Ii key be held down
, for at least four display cycles before being
accepted. A key must also be lifted for at least
four display cycles before a new key can be
accepted.
9. To prevent crosstalk or ghosting between display
digits, a LED display requires segment blanking
(Sb in Figure 5.17).

4. The L ports are configured as LED Direct Drive
outputs (options 5-8 and 12-15= 2) to directly

2·72

10. The system clock oscillator is configured as a
crystal controlled oscillator with the instruction
cycle frequency derived by driving the crystal
oscillator frequency by 16 (options 2 and 3 =0).
This interface scheme uses an inexpensive
3.58MHz TV crystal to provide the clock
oscillator frequency, divided by 16 to derive a
4.51's instruction cycle time. This also allows
use of the "TIMEKP" (timekeeping) routine given
in Section 4.9, which uses the internal COP420
Time·Base Counter and the SKT instruction,
together with program compensation techniques,
to provide a "real time base" for keeping time eliminating the need for an external 60 Hz realtime input and associated external circuitry.

As will be seen, the two leftmost bits of the KBC
("up" and "NRB") are tested during the
debounce routine to determine which branch of
the routine will be executed. The rightmost bits,
the binary counter bits, provide a binary count of
the number of times the program falls through
the debounce routine.
3. The internal time-base counter is tested for
overflow by an SKT instruction, calling the
"TIMEKP" subroutine given in Section 4.9 to
keep time if the SKT instruction tests "true."
4. The digit position is set to 14, the most
significant digit of the display. As indicated by
the source code, the digit position is set by
loading Bd (the RAM digit-select register) with
the digit position value with an LBI instruction.
Bd is later output to the D ports using an OBD
instruction, decoded by the DS8664 to enable
the appropriate display digit line (D'4 - D,). Since,
as mentioned, Bd also functions as a pointer to
a particular RAM digit as well as being the
source of a direct output of data to the D ports,
loading Bd also is used to access the contents
of a particular RAM digit, used later by an LaiD
instruction to obtain seven-segment decode data
contained in a lookup table. Because 6f'this
dual function of Bd, the segment data for a
particular display digit should be located in a
numerically corresponding RAM digit of the RAM
display register (register 0). For example, when
Bd is set to 14 by an LBI 0,14 to later enable
display digit 14, it will also be used to obtain the
segment lookup data for that display digit
located in RAM register 0, digit 14. Consequently
the segment data pOinters for display digits 14
through 1 are located in RAM register 0, digits
14 through 1, respectively.

Sample Display/Keyboard Debounce-Decode
Program
Figure 5.16 depicts the flowchart for the sample
displaylkeyboard debounce routine. The actual
assembly source code written to perform the
flowchart operations is given in Figure 5.18.
Following the flowchart from top to bottom, and
referring to the source code where appropriate, the
following sequence of operations is performed:
1. The G port is set to 15 (each G line set to "1").
This allows them to be driven low when scanned
by their associated D lines. If a keyswitch is
closed, the associated G line will therefore
become a "0," to be input and tested by the
keyboard servicing routine ..
2. The program initializes the KBC (Keyboard
Debounce Counter) to 15 (1111 2). This counter
name, as well as two other RAM status digit
names, "DIGIT" and "STORE," are assigned the
values of their RAM register and digit numbers
by assembler assignment statements at the
beginning of the source code. This allows these
names to be substituted in the operand field of
instructions which reference these RAM digits,
providing more effective documentation of the
source code program. For example, since the
KBC is located in RAM register 3, digit 15 and
since this value (3,15) must be contained in the
operand field of an instruction referencing the
KBC, an assignment statement of KBC = 3,15 is
written at the beginning of the program.
Thereafter, an instruction referencing the KBC
may use its name, rather than its RAM value, in
the operand field of the instruction (e.g., an
LBI KBC will be interpreted by the assembler as
an LBI3,15).

As will be seen below, the segment data
contained in a particular RAM digit, although
used by LaiD to obtain the actual sevensegment data output to the display, will equal
the binary equivalent of the numeral to be
displayed (e.g., if a RAM register 0 digit
contents = 0010 2, the LaiD instruction will
access the seven-segment diode data for the
numeral "2." RAM digit contents equal to 10-15
will be used to access special seven-segment
alphabetical characters.
5. The value of the digit position loaded into Bd is
saved in M(1,15), equated by an assembler
statement, as explained in 1. above, to the
symbol name "DIGIT." The digit value is saved
for later manipulation by the display program
(testing, decrementing).

The contents of the KBC are depicted in the
upper right hand corner of the flowchart. From
left to right, the bits of the counter indicate the
following status conditions: the "up" bit, set to
"1" if all keys are up; the "not ready" bit (NRB),
set to "1" if keyswitch data has not been
debounced; two binary counte·r bits, both set to
"1" at the beginning of the debounce sequence.

6. The segments of the display are blanked, a
requirement for LED multiplexed displays. This
is accomplished by disabling the drivers from
the a latches (which contain the seven-segment
decode display data) to the L ports by resetting
bit 2 of the EN register with an LEI 0 instruction.

2-73

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comments to the program, that ROM word bits
17-10 (rightmost to leftmost) represent and are
tied via the L ports to the Sa-Sg, D.P. segments
of the display. A"1" bit for a particular segment
means that that segment will be turned on. In all
cases, each seven-segment decode word has the
D.P. bit (10) seg; if no\ later reset by the program
the decimal pOint segment of a particular digit
will be turned on when that digit is serviced. See
Table 5.2 for a representation of the
interconnection of the seven-segments of a
display digit and a list of binary and hex values
associated with setting the segments of a digit
to display the numerals 0-9.

With the L drivers thus disabled, the Lila ports
are disabled, turning off the segments of the
display.

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7. Next, the program utilizes an LQID instruction to
access and load seven-segment decode data
contained in a lookup table into the Q latches.
This is accomplished in the following manner: as
explained in Section 3.2, LQID loads QrQo with
the 8-bit contents of ROM (lr 10) poi nted to by
Pa, Ps, A and M. In this example, LQID is located
in page 0, with the result that, at the time of .
execution, Pa, Ps = 0,0. The program sets
A = 0100 with an AISC 4 instruction before
execution of the LQID instruction so that
P7,P6 =0,1 and P5 ,P 4 =0,0. Since the upper 4
bits of P may be thought of a ROM
"page-select" bits, selecting 1 of 16 pages
(0-15) and, since these 4 bits will equal 0001 at
the time of the execution of the LQID
instruction, it will always "look to" page 1. The
lowest 6 bits of P (P 5 - Po) may be thought of a
ROM "word-select" bits, selecting 1 of 64 (0-63)
words on a "looked-to" page. Moreover, P5 and
P4, the upper 2 bits of these 6 word-select bits,
may be thought of as ROM "sub-page-select"
bits, selecting 1 of 4 (0-3) successive groups of
16 words on a 64-word ROM page. Since P5 and
P4 will always equal 0,0 upon the execution of
the LQID i'nstruction, it will always look to one of
the first 16 words located in page 1. Since the
contents of M (the RAM digit pointed to by the B
register), are loaded into the lowest 4 bits of P
(P 3 - Po), it is the binary contents of M direcily
(0-15) which determine which of the first 16
words (0-15) on page 1 are "looked up" and
placed in Q.
In effect, M is the only variable involved in the
LQID operation with its contents directly
determining which one of the 16 words in page 1
(words 0-15) are loaded into· Q. Of course, the
seven-segment decode values have been placed
in these locations. Also, as indicated above, the
first 10 words (locations 0-9) have been loaded
with the seven-segment decode values for the
numerals 0-9, respectively. Consequently if
M = 3 binary (0011 2 ), a LQID will place the sevensegment lookup data for a display numeral 3
into Q. If M = 10-15 binary, LQID will place the
seven-segment decode values for the special
alphabetical characters P, A, U, C, F and E,
respectively, into Q, since page 1, locations
10-15, contain the decode values to display
these characters on the display.

8. A comparison is made to see whether the
decimal point position stored in RAM is equal to
the digit position of the digit to be displayed
during the present pass through the display
loop. If the comparison result is "false," the
program jumps to "NODP," which resets the
least significant bit of Q to keep the decimal
point segment of the current digit off when Q
latch data is later output to the display via the L
ports. Note that an X instruction must follow the
CQMA and precede the CAMQ instruction to
maintain the integrity (bit-weights) of the Q data,
since these instructions perform opposite
exchanges with respect to A and M. (See Section
3.2.)

The hexadecimal value of the seven-segment
lookup data is placed in page 1, locations 0-15
with the assembler .WORD directive. Although
operands of the .WORD may be concatenated
(I.e., .wORD X'FD, X'1 F, ... ), each 8-bit segment
decode value has been placed in successive
memory locations with a separate .WORD
,directive. It shou,ld be noted, as indicated by the

9. If the comparison tests "true," the least
significant bit of Q is left set to turn on the
decimal point of the current digit and a delay is
added to ensure that the program will require
2-74

the same amount of execution time whether or
not the comparison tests "false" (goes to
"NODP") or "true." This and other delays
contained in the program ensure that the
servicing of a particular display digit will always
require the same number of instruction cycle
times regardless of which branch of the program
is executed during a pass through the program;
this is necessary for equal segment-on time for
each digit and uniform brightness among the
various digits of the display.
10. Digit position data is output from Bd to the D
outputs, decoded by the DS8664, enabling the
appropriate digit of the display and scanning the
corresponding D line (if connected) to the
keyboard matrix column or strap switch line.
11. Segment data is output to the current digit by
enabling the L drivers with an LEI4 instruction,
setting bit 2 of the EN register and outputting
the 8-bit Q latch data to the L I/O ports, the
latter connected directly to the segments of the
display.
12. Having output data to one digit of the display,
the program now begins to service the keyboard.
A test is made to see whether any key closure
has occurred. If so, the program jumps to
"KEYDWN," first testing to see if the key
closure occurred on a strap digit line. If this test
result is true, the strap data is read into RAM
and the program goes to "NRDY." If the key
closure was associated with the keyboard
matrix, the "up" bit of the KBC is reset and the
KBC is tested for all 4 bits equal to O. If the KBC
equals 0, indicating a debounced keyswitch
closure, the program blanks the display, inputs
the G port (keyswitch row data) into A, and
jumps to the keyboard decode routine. If the
KBC did not equal 0, the program also goes to
"NRDY" (with the KBC "up" bit reset to indicate
a key closure).
It should be noted that the "up" bit is not reset
if the key closure was a strap data switch. As
will be seen, this means the program will not
treat this· switch closure as a key depression
(since the "up" bit remains set) and does not
debounce this closure nor jump to decode a
strap switch closure. Strap switches are of the
on/off type not requiring debouncing as do the
momentary on/off keyswitches. Also, a strap
switch decode routine, in this example, is not
necessary. The strap data bits read into RAM
may be tested at any time for execution of a
routine implementing the "mode" associated
with a particular strap switch closure.

last digit has been displayed, the program falls
through to "DEBaUN," the keyswitch
debouncing portion of the program.
14. Debouncing begins at "DEBaUN" by testing to
see whether the up bit has been reset, indicating
a keyswitch closure. If not, the program takes
the right branch to "ALLUP" and tests the not
ready bit (NRB) of the KBC. If NRB is equal to 1,
the KBC is decremented, the up bit remains set
and the program goes back to "DSP1" to output
data to all 14 digits again. If, on the first pass
through the program, no key closure has
occurred, the KBC will enter the debounce
routine equal to 1111, exiting with a
decremented value of 1110. Provided all keys
remain up, it will take four passes through the
right debounce branch before the KBC has been
decremented to 1011, thereby resetting the not
ready bit. If all keys remain up after four passes,
the program will continue to fall through the
NRB not equal to 1 (right) branch, keeping the
KBC at 1011. The foregoing operations ensure
that all keys remain up for at least four
debounce passes before the not ready bit is
reset to 0 (and a key closure will be accepted for
keydown-debouncing).
.
15. If, upon entering the debounce routine, the up
bit has been reset indicating a key closure, the
program will take the left debounce branch. If
the not ready bit has been reset to 0, indicating
as explained above that all keys have previously
remained up for at least four passes, the
program will continue to decrement the KBC,
exiting by setting the up bit and going back to
"DSP2." Assuming that the right debounce
branch has previously decremented the KBC to
1011, "DEBaUN" will be entered with the KBC
equal to 0011. (A key closure resets the up bit.) If
the key remains down for four passes, the left
branch will decrement the KBC to 0000 and go
back to "DSP1" with the KBC equal to 1000 (up
bit reset). On the next pass, with the keyswitch
still down, "KBCTST" will reset the up bit, the
KBC will equal 0000 and the program will jump
to the keyboard decode routine with the value of
the current D line stored in RAM and the G port
data in A.
If the left branch of the debounce routine is
entered without the keys having been up for at
least four passes (NRB equal to 1), the program
will set the KBC to 1111, continuing to do so
until the key is lifted and remains up for four
passes through the right branch of tile debounce
loop. Consequently, the program requires that a
key be down, as well as up, for at least four
debounce periods before keyboard data will be
accepted and de.coded. Since it takes 16
milliseconds to execute four program passes,
ample time is provided to debounce even the
most inexpensive keyboards.

13. If the program jumps to "NRDY," a test is made
to determine whether the digit position equals 1,
indicating that all 14 digits have been displayed.
If the last digit has not been displayed, the digit
position is decremented by one and the program
goes to "DSP2" to service the next digit. If the

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First, the programmer must specify a label for
the first instruction of each keyswitch decode
routine - in this example labels
"KEY1"-"KEY16" are given for the starting
address of keyswitch number 1-16 decode
routines, respectively. (No decode servicing code
is given.) As already mentioned, these decode
labels and the code for each decode routine
must reside within the same ROM block as the
JID instruction (ROM block 2, pages 4- 7).

16. Once a keyswitch closure has been debounced,
the program exits to "KEYDEC" (keyboard
decode routine). Upon entry to."KEYDEC," G
port data is in the accumulator and represents
the particular row of the keyboard matrix upon
which a key closure has occurred. Data memory
M(1,15) contains the value of the 0 line and
represents the particular keyboard matrix
column upon which a key closure has occurred.
The conjunction of a particular D line value and
the state of a particular G port bit, therefore,
define one of sixteen key closures. Only two
instructions are necessary to jump to the
particular decode routine associated with each
key closure based upon the contents of A and
M(1,15): a COMP and a JID instruction.

Second, at each pOinter address for each key
closure as Indicated in Table 5.3, an .ADDR
directive must be used to place the lower a bits
of the address of the beginning of each
keyswitch decode routine within each pointer.
location. This is easily accomplished by moving
the assembler location counter to the
appropriate pointer address using an
assignment statement which assigns the
location counter (':.") to the hexadecimal
address of the appropriate JID pOinter location.
In this example, for instance, the "KEY1" pointer
should be located at address X'111. The
assignment statement, . = X'111, moves the
assembler location counter to this address. The
assembler will then generate code into
successive memory locations starting at this
location until the assembler location counter is
again moved.

The COMP instruction is necessary to invert the
contents of A since a particular key closure will
result in one bit of G being driven to "0," with
the remaining bits of G set to "1."
Complementing A results in a "1" representing a
key closure with the value of A equai to 0001,
0010, 0100, or 1000 (binary) if the key closure
occurred on the Go-G J row lines, respectively. 0
will equal 0001, 0010, 0011, or 0100 (binary) if the
key closure occurred on the D,- 0 4 lines,
respectively. The JID instruction can then use A
and M without further manipulation to access
key routine pointers, provided these pointers
have been placed in appropriate ROM locations
(those which the JID will access based upon the
values of A and M associated with each key).

After moving the assembler location counter to
the proper JID pointer address, the a-bit value of
the address of each appropriate keyswitch
decode label location is loaded into the painter
address by using an .ADDR directive with an
operand specifying the label associated with the
first instruction of each key decode routine. For
example, to load the keyswitch number 1 decode
routine starting address into its pointer location,
an .ADDR KEY1 directive will place the lower a
bits of the address of the KEY1 label into the
ROM painter location.

The operation of the JID instruction is similar to
that of the LQID instruction in that it accesses a
ROM location based upon the current value of
Pg, Ps, AJ , A2, A1, AD, MJ , M2, M1, Mo. JID,
however, then uses the contents of this ROM
location as a pointer and transfers program
control to this "pointed-to" address. The exact
location of this address (first instruction of each
decode routine) need not be of concern to the
programmer provided It resides within the same
ROM block as the JID instruction (see Section
4.1); in this example within ROM block 2 (pages
4-7).

As can be seen, once labels have been given to
the beginning of each decode routine and the
assembler location pointer has been moved to
the proper JID pointer location, a simple
.ADDR (label) statement for each label will
automatically allow the JID instruction to
transfer program control to the appropriate
decode routine for each keyswitch immediately
after exiting from the DISPLAY/KEYBOARD
DEBOUNCE routine (after complementing G data
as explained above). In this example, the
assembler location pointer need only be moved
four times, since each group of 4 JID pointers
resides in successive memory locations. (See
Table 5.3.)

The location of each JID key decode routine
pointer must correspond with the current value
of P9 and Ps, and with the value of A (G port·
data) and M (0 line data) associated with each
particular key closure. Table 5.3 depicts the
various address values of Pg, Ps, A and M for
each keyswitch closure. The programmer must
place, within these address locations, the lower
a bits of the address of the first instruction of
each keydecode routine, to allow the JID
instruction to automatically transfer program
control to one of these Instructions. This loading
of ROM address pOinters with the proper a-bit
data Is easily accomplished using the assembler
assignment statement and the .ADDR directive.

Of course, the gaps which exist between the JID
painter locations on pages 4-6 are available for
use by other portions of program code. To aid
the user in understanding the operations of the
assignment statements and .ADDR directives in

2-76

this sample program, an assembler output
listing of the program is provided in Figure 5.19,
indicating in the leftmost columns the line
numbers, memory addresses and B·bit memory
contents associated with the use of these
assembler control statements.
For convenience, the "KEY1"-"KEY16" labels
are placed in successive double-byte memory
locations, jumping back to "DSP1." In a "real"
program, each of these labels would be

followed, respectively, by the code required to
perform the program operations associated with
each key closure. Alternatively, they might still
be placed in successive double-byte memory
locations if they used a JMP 'instruction to jump
to any location within the 1K ROM area to a
routine which serviced the appropriate
keyswitch. For further information on the use of
the PDS assembler, see Chapter B, PDS User's
Manual.

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2-80

5.4 SIO Input/Output
SI and SO can be used to provide additional 1/0
capability for the COP400 family by connecting, for
example, external 8·bit parallel·to·serial
(MM74C165) and serial·to·parallel (MM74C164) shift
registers, as shown in Figure 5.20. The following
routine will oUiput 8 bits of data serially using the
SIO registers, at the same time inputting 8 bits
serially. Data is output from and input to A and M.
This program must be entered with the SIO register
enabled as a serial shift register. The execution of
an XAS instruction with C "1" and "0"
respectively will enable and disable SK as a SYNC
output. (See Section 3.2, LEI instruction
description.) With SK enabled as a SYNC output it
will provide a clock pulse to the shift registers
each instruction cycle time. Note that SI is
simultaneously shifting 1 bit of serial data into SIO
while SO is shifting 1 bit of serial data out. Since
the 4·bit contents of SIO are continuously shifted
each instruction cycle time, the routine is written
to insure that SIO is exchanged with A every 4
instruction cycle times.

Figure 5.21 shows an example of a multi·COP420
system. As Is indicated, data transfers between the
two devices are done in a serial fashion, with one
COP providing a SYNC pulse via the SK output to
the CKO pin of the second COP. To ensure the
validity of the data being transferred, both COPs
must contain a routine which will synchronize the
inputting and outputting of data between the two
devices using the SIO register. The following code
accomplishes this by providing that each COP
receive and send a string of four "15" (SIO = 1111 2)
before an SIO data transfer is effected.

=

;
;
;
;
;

;
;
;
;
;

ROUTINE TO SYNCHRONIZE SERIAL DATA TRANSFERS
BETWEEN TWO COP DEVICES (COPA AND COPB) USING
THE SIO REGISTER
SIO MUST HAVE BEEN PREVIOUSLY ENABLED AS A SERIAL
SHIFT REGISTER

; COPA CODE:
BACK:

NOP
CLRA
XAS
NOP
CLRA
COMP
XAS
AISC
JP

ROUTINE TO OUTPUT 8 BITS OF DATA SERIALLY FROM M
AND A WHILE INPUTIING 8 BITS OF SERIAL DATA INTO M
AND A USING THE SIO REGISTER
UPON ENTRY, SIO MUST BE ENABLED AS A SERIAL SHIFT
REGISTER (ENO = 0)

; ADD 1 INSTR. CYCLE TIME FOR
; RE·SYNC
; ZERO TO A
; OUTPUT ZEROS. WAIT 4 INSTR.
; CYCLE TIMES

1
BACK

SERIO:
SC
XAS
NOP
NOP
LD
XAS
X
CLRA
RC
XAS

;
;
;
;
;

SET CARRY TO ENABLE Sl< AS A SYNC
OUTPUT
START SYNC, A TO SIO, START SHIFTING
A OUT, SI DATA IN
WAIT 4 INSTR. CYCLE TIMES

;
;
;
;
;

15 TO A
OUTPUT 15 VIA SK. SI BITS TO A
ARE INPUT BITS = 15?
NO, TRY AGAI N
YES. DEVICES SYNCHRONIZED

; COPB CODE:
BACK:
; OUTPUT ZEROS IN 4·CYCLE
; LOOP

CLRA

; M TO A
; FIRST 4 SI BITS TO A, A TO SIO,
; CONTINUE SHIFTING SIIN, SO OUT
; STORE FIRST 4 SI BITS IN M
; CLEAR A (WAIT 4 INSTR. CYCLE TIMES)
; RESET C TO DISABLE SK AS A SYNC
; OUTPUT
; STOP SYNC, LAST 4 SI BITS TO A

XAS
AISC
JP
COMP
XAS
NOP
NOP
NOP

2·81

1
BACK

; 15 FROM COPA?
; NO, KEEP SENDING OUT ZEROS
; YES, OUTPUT 15 TO COPA
; DEVICES SYNCHRONIZED
; WAIT FOR COPA TO START

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5.5 Add·On RAM
memory digit M(3,15). It then reads from or write 1/0
data into COP RAM memory, register O,digits 0-15,
respectively,

The following routine will interface the COP420 to
an additional 2K bits (512 x 4) of RAM. The
interconnect diagram (see Figure 5.22) shows the
COP420 interfaced to two additional MM2112
(256 x 4) RAM devices, although CMOS equivalents
(MM74C921s) may also be used where lower power
consumption or RAM battery backup is desired. Up
to four devices may be used by decoding the Do
and D1 lines (2·to·4 binary decoder). If all 4 bits of D
are used, up to 16 additional RAM devices can be
Interfaced utilizing a 4·to·16 binary decoder (an
additional 2K bytes of RAM).

Note that two different operands for the LEI
instruction are used to select or de·select specific
operations associated with three of the four bits of
the EN register. The LEI13 instruction sets
EN 3 - ENo equal to 1101 with the result that EN3
and ENo are equal to "1" and, therefore, SO will
output a "I" to the WE pins of external RAM to
perform a read operation. EN2 is also set to "I" to
enable the L drivers so that Q latch data will be
output to the Lila ports and, via the interconnect,
to the RAM address lines. The LEI 5 instruction
alters EN3 to "0," resulting in SO being driven low,
enabling a write operation into the external RAM
device.

The following routine treats the 1024 bits of
external RAM as organized as 16 registers of 16
4·blt digits. It sequentially addresses digits 0
through 15 in a particular external RAM register (as
determined by the 4·bit contents of COP RAM

; SUBROUTINE TO READ·FROM/WRITE TO ONE OF TWO EXTERNAL RAM DEVICES (256 x 4 BITS EACH)
; 16 4·BIT DIGITS OF 1/0 DATA READ FROM OR WRITTEN INTO COP RAM, REGISTER 0, DIGITS 0 - 15
; C ~ 0 INDICATES A READ OPERATI,ON, C ~ 1 INDICATES A WRITE OPERATION
; 8·BIT RAM ADDRESS SPECIFIED BY A 4-BIT REGISTER NUMBER CONTAINED IN M(3,15). ASSIGNED TO SYMBOL "'DIGIT"'
; CHIP·SELECT NUMBER (1110 OR 1101 BINARY) CONTAINED IN M(2,15). ASSIGNED TO SYMBOL "'CSEL" .
; READ: ENTRY POINT TO READ RAM
; WRITE: ENTRY POINT TO WRITE RAM
DIGIT
CSEL
REG

~1,15
~2.15
~3,15

READ:
RC
JP

; RESET CARRY FOR READ OPERATION
RW

WRITE:
SC
RW:
OGI
LEI
LBI
OBD
LBI
CLRA

15

13

;
;
;
;

SET CARRY FOR WRITE OPERATION
READIWRITE CODE
SET G3 - GO HIGH,
SO ~ 1, ENABLE L DRIVERS

CSEL
DIGIT

; OUTPUT CHIP SELECT VALUE
; POINT TO DIGIT NUMBER
; START WITH DIGIT 0

RWL:
X
LDD
CAMQ
LD
CAB
SKC
. JP
LEI
OMG
LEI
OGI

REG

RR

13
15

; EXCHANGE A INTO DIGIT NUMBER IN M
; REGISTER NUMBER TO A
; OUTPUT REGISTER AND DIGIT NUMBER FOR RAM ADDRESS
; DIGIT NUMBER TO A, POINT TO REGISTER 0
; DIGIT NUMBER TO BD TO POINT TO 1/0 DATA IN M
; IS CARRY EQUAL TO 1?
; NO. JUMP TO READ RAM
; YES. PERFORM WRITE OPERATION, DRIVE WRITE ENABLE LOW
; OUTPUT DATA TO RAM
; SET WRITE ENABLE HIGH
; SET G3 - GO HIGH

RWCONT:
LBI
LD
AISC
JP
OBD
RET

DIGIT
1
RWL

; POINT TO DIGIT NUMBER
; DIGIT NUMBER TO A
; INCREMENT DIGIT NUMBER, IS DIGIT ~ 15?
; NO, CONTINUE READIWRITE
; YES, DISABLE RAMS (CHIP SELECTS HIGH)
; RETURN

RR:
ING
X
JP

RWCONT

READ RAM DATA
STORE IN 1/0 DIGIT IN M
CONTINUE

2·82

.

I

~D

~

01

l"

COP420

L1L7

G9
G3
DO

have testable input latches associated with them .
These latches, IL3 and ILo, will be set if a low going
pulse, at least two instruction cycles wide, has
occurred on the IN3 or INa inputs, respectively. The
INIL instruction inputs these latches to A, as
explained in Section 3.2, to allow them to be tested
as software interrupt flags (A3 and Ao).

t

...

SO

I

;\7
!/01

ilo,

r.rw.

CE

MM2112
OR

MM7.C921

To accomplish a software interrupt, an INIL
instruction must be executed often enough to
respond to the requirements of the interrupt signal
tied to IN3 or IN o. For example, in timekeeping
applications, IN3 or INa may be connected to a
60 Hz square wave. The program must, in this case,
execute an INIL instruction at least every 1/60
second.

AD

I~
1 "

e~l

•
:

MMZ112
OR
MM74C921

liD'
WE

CE

+

Figure 5.22 Typical Add·On RAM Interconnect

If an interrupt input occurs irregularly, it will be
more efficient to connect it to the hardware
interrupt pin, IN 1, to insure that no interrupt is
missed due to infrequent testing. Conversely, if an
interrupt input occurs regularly and predictably
(such as a 60 Hz signal) a software interrupt may be
efficiently utilized by simply building into the
program a sufficient test rate to insure that no
inputs are missed.

5.6 IN311No Inputs
Section 4.8 has already provided an example of an
interrupt service routine utilizing the "hardware"
interrupt capability of the IN1 COP420 pin. It is also
possible to implement a "software" interrupt, using
either the COP420 IN3 or INa inputs, since they

Technical Assistance
National Semiconductor will be pleased to provide
technical assistance to aid a user in design an'd
development. Inquiries may be directed to any of
our Field Applications Engineers (FAEs) - located
in every National sales office - or to our in-plant
COPS™ Applications Group at (408) 737-5582 ..

2-83

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CD

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CD

m

National Semiconductor
Leonard A. Distaso
February 1980
COP Note 1

Analog to Digital
Conversion Techniques
C.co!!
u- With COPS™ Family
CDe Microcontrollers
::I
cr 0
._

-

.... C

CO

ou

Table of Contents

CD.S:!

II.

.- 0
f!! ...

~:E

I.

8~

C. Conclusions .......................... 2·88
III.

.-~

0'(1)
00.

-0

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Introduction ........................... 2·84
Simple Capacitor Charge Time
Measurement .......................... 2·84
A. Basic Approach ........................ 2·84
B. Accuracy Improvements ................. 2·87

-E

S'"
'-LL
en

In a software driven system the D/A converter and
comparator are present but the control logic is
replaced by instruction sequences. There are a
variety of software/hardware techniques for implementing AID converters. They differ primarily in their
approach to the included D/A. There are two primary
approaches to the digital to analog conversion which
can in turn be divided into a number of subcategories:

IV.

"'c:c3:

• D/ A as a function of weighted closures
- R/2R ladder
- Binary weighted ladder
• D/A as a function of time
RC exponential charge
- Linear charge/discharge (dual slope)
- Pulse width modulation

Pulse Width Modulation (Duty Cycle)
'Technique ............. ; ... : ........... 2·89
A. MathematiCal Analysis .................. 2·89
B. Basic Implementation .................. 2·90
C. Accuracy Improvements ................ 2·93
Dual Slope Integration Techniques ......... 2·97

These techniques should be generally familiar to
persons skilled in the electronic art. The objective
here is to illustrate the application of these
established methods to a low cost system with a
COPS microcontroller as the intelligent control
element. Circuit configurations are provided as well
as the appropriate flow charts and code to
implement the function.

A. Mathematical Background ............... 2·97
B. Basic Dual Slope Technique ............. 2·98
C. Modified Dual Slope Technique .......... 2·100

C'-

V.
A.
B.
C.
D.

Voltage to Frequency Converters, VCO's ... 2-103
Basic Approach ....................... 2-103
The LM131/LM231/LM331 .............. 2-105
Voltage Controlled Oscillators ........... 2·105
A Combined Approach ................. 2-105

Some mathematical and theoretical analysis is
presented as an aid to understanding the various
techniques and their limits. However, it is not the
purpose here to provide a definitive theoretical
analysiS of the analog to digital conversion process
or of the various techniques described.

VI. Successive Approximation .............. 2·107
A. Basic Approach ....................... 2-107
B. Some Comments on Resistor Ladders .... 2·109
VII. "Offboard"Techniques ................. 2-112
A. General Comments .................... 2-112

II. Simple Capacitor Charge Time
Measurement

B. ADC0800 Interface .................... 2·112
C. Naked-8™ Interface ................... 2·113
D. TheMM5407asanAIDConverter ........ 2·115

A. BASIC APPROACH
A.1 General

VIII. Conclusion .... , ...................... 2-118
IX.

Perhaps the simplest means to perform an analog to
digital conversion is to charge a capacitor until the
capaCitor voltage is equal to the unknown voltage.
The capacitor voltage and the unknown are compared by means of a standard analog comparator.
The unknown is determined simply by counting, in
the microcontroller, the amount of time it takes for
the charge on the capaCitor to reach a value equal to
the unknown voltage. The capacitor voltage is given
by the standard capaCitor charge equation:

References ........................... 2-118

I. Introduction

,..
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A variety of techniques for performing analog to
digital conversion are presented. The COP420 microcontroller is used as the control element in all cases.
However, any of the COPSTM family of microcontrollers could be used with only minor changes in
some component values to allow for different
instruction cycle times.
All Indirect analog to digital converters
composed of three basic building blocks:

Vc=VO+[V1-VO][1-e**(-t/RC)]
where: Vc = capaCitor voltage
VO = "discharge voltage" - low level voltage
V1 = high level voltage

are

• 0/ A Converter
• Comparator
• Control logic

The most obvious problem with this method, from the
standpoint of software implementation, is the nonlinearity of the relationship. This can be circumvented in

2·84

this basic implementation. The levels of V1 and VO are
not Vcc and ground as would be desired. The level is
defined by the load on the output, the value of Vee, and
the device itself. Furthermore, these levels are likely to
change from device to device and over temperature. To
be sure, the output values will be at least those given in
the data sheet, but it must be remembered that those
values are minimum high voltages and n'laximum low
voltages. Typically, the high value will be greater than
the spec minimum and the low value will be lower than
the spec maximum. In fact, with a light load the values
will be close to Vee and ground. Therefore, in order to
obtain any accurate result for a voltage measurement
the exact val ues of V1 and VO need to be measured and
somehow stored in the microcontroller. Typical values
of these voltages can be measured experimentally and
an average could be used for a final implementation.

several ways. First of all, a routine to calculate the
exponential can be implemented. This, however, usually.
requires too much code if the exponential routine is not
otherwise required in the program. Alternatively, the
range of input voltages can be restricted so that only a
portion of the capacitor charge curve - which can be
approximated with a linear relationship or with some
minor straight line curve fitting - is used. Finally, a
look up table can be used which will effectively convert
the measured time to the appropriate voltage. The look
up table has the advantage that all the math can be built
into the table, thereby simplifying matters significantly.
If arithmetic routines are going to be used, it is clear
that the relationship is simplified if VO is 0 volts
because it then drops out the equation.

A.2. Basic Circuit Implementation
The circuit in Figure 1 is the basic implementation of
the capacitor charge method of AID conversion. The
selection of input and output used is arbitrary and is
dictated by general system considerations. VO is the
"0" level of the G output and V1 is the "1" level of the
output. The technique is basically to discharge the
capacitor to VO (which is ideally ground) and then to
apply V1 and increment an internal counter until the
comparator changes state. The flow chart and code for
this implementation are shown in Figure 2.

The other problem associated with the levels is that the
capacitive load on the output line is substantial and far
in excess of the values used when specifying the
characteristics of the various COP420 outputs. The
significant effect of this is that it will take longer than
"normal" for the output to reach its maximum value. In
addition, it is likely that there will be dips in the output
as it rises to its maximum value since the capacitor will
start to draw charging current from the output. All of
this will be fast relative to the other system times. Still,
it will affect the result since the level to which the
'capacitor is attempting to charge is not being applied
uniformly and "instantaneously". It can be viewed as
though the voltage V1 is bouncing before it stabilizes.

A.3 Accuracy Considerations
The levels reached by the microcontroller output
constitute one of the more significant problems with

Vee

vee

3k

VIN

20

IN3
COP420

-=

Vee
CRYSTAL OSCILLATOR VALUES CHOSEN TO GIVE 4~S CYCLE TIME WITH DIVIDE BY 16 OPTION
SELECTED ON COP 420 CKO/CKI PINS

Vee= +5V

Figure 1. Basic Capacitor Charge Technique

2·85

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......

,....
Q)

OGI
0
,TURN OFF G TO DISCHARGE CAPACITOR
; INSERT SOME DELAY TO MAKE SURE CAPACITOR DISCHARGED
,USING 12 BIT COUNTER, BUT ONLY UPPER 8 USED IN TABLE
,LOOK UP DUE TO ACCURACY OF RC CHARGE METHOD.
THE OTHER
'BITS COULD BE USED BUT THE COMPLICATIONS ARE NOT WORTH
,THE EFFORT FOR THIS PARTICULAR TECHNIGUE.
ALSO, HERE THE
,INPUT RANGE IS RESTRICTED SO THAT THE TOP 3 BITS ARE ZERO

'0

z

C-

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R(:!ll>:

INti!:
B)NPI.!·,:
B)NPl J,

t:NH:

,TURN ON THE G LINE
oGI
1
2,13
,BINARY INCREMENT OF 12 BIT COUNTER
LBI
;LOWER FOUR BITS WILL BE DISCARDED
SC
; ONLY TOP BITS USED IN TABLE LOOK UP
CLRA
; SPEED WOULD BE IMPROVED IF THE ADD WERE
IISC
;~TRAIGHT LINE CODED-BUT COSTS MORE CODE
NOP
XIS
BINPL1
JP
;READ IN3 TO SEE IF COMPARATOR CHANGED
IN IN
A/SC
8
JP
END
CI.RA
JP
INCR
oGI
0
; TURN OFF THE G LINE AND DISCHARGE C
,DO ARITHMETIC HERE OR LOOK UP TABLE OR WHATEVER IS
;REGUIRED--SAMPLE LOOK UP TABLE CONTROL INDICATED BELOW
; SAMPLE TABLE WRITTEN CORRECTING. FOR THE EXPONENTIAL
JRELATIONSHIP.
THE TABLE ALSO INCORPORATES A CONVERSION
;TO BCD.
THE VALUE IN THE TABLE IS THE RATIO OF
; THE CAPACITOR VOLTAGE V TO THE MAX IMUM VOLTAGE VMAX.
; THE NUMBER IS A TWO DIGIT BCD FRACTION.
WE ·ARE USING
;A 5 BIT COUNT IN THIS EXAMPLE.
ADDRESSING ARBITRARILY
; SET UP ASSUMING THAT CONTROL CODE IS IN PAGE 0 (OTHER
; THAN AT ADDRESS 0) AND THAT THE TABLE THEREFORE IS IN
;PAGE 1 (STARTING AT HEX ADDRESS 040).
; POINT TO TOP 4 BITS
; TOP 4 IN A,POINTING TO LOWER 4 IN 2,14
;THIS MERELY ADJUSTING FOR ADDRESS--NO
; OTHER FUNCTION
LOID
;DO THE LOOK UP
COMA
; FETCH THE ADJUSTED VALUE FROM Q
; THE ADJUSTED VALUE IS NOW INA AND M.
FROM THIS POINT MAY
,USE THE VALUE IN OTHER CALCULATIONS OR OUTPUT THE INFORMATION,.
;OR WHATEVER MAY BE REGUIRED BY THE APPLICATION.
LBI
2,13
,CLEAR THE COUNTER
STII
0
STI!
0
LBI
XDS
AISC

2,15
4

STIr

0

JP

RCAD:

,JUMP BACK AND REPEAT

,SET UP TABLE ADDRESS
000,003,006,008 ; SET UP THE TABLE VALUES
011,014,016,019 ,HERE, COMPENSATED FOR EXPONENTIAL
021,023,026,028 ,AND CONVERTED TO BCD FRACTION
030,032,034,036 ,TABLE VALUE IS RATIO V/VMAX
038,039,041,043
045,046,048,049
051,052,053,055

.~X'040

.
.
.
.
.
.
.
.

WORD
WORD
WORD
WORD
WORD
WORD
WORD
WORD

056.057.059.060

Figure 2A. Typical RC Charge AID Code

0- GO

APPLY V,
(INPUT VOLTAGE)

1 - GO

Figure 2B. RC Charge Flow Chart

2·86

A more general problem is that of the tolerance of RC
time constant. The value of the voltage with respect to
time is obviously related to the RC value. Therefore, a
change in that value will result in a change in the
voltage for a given time period t. The graph in Figure 3
illustrates the effect of a ±10% variation in the RC
value upon the voltage measured for a given time t. If
one cares to work out the math, it comes out that the
error is an exponential relationship in much the same
manner as the capacitor voltage itself. The maximum
error induced for ±10% RC variation is ±3.9%.

input is 13 cycle times. For a 9 to 12 bit binary counter
this minimum time is 17 cycle times. Note also that the
minimum time to perform the function does not necessarily correspond to the minimum number of code
words required to implement the function. At a cycle
time of 4 microseconds, the 13 cycle times correspond
to 52 microseconds.

B. ACCURACY IMPROVEMENTS
Several options are available if it is desired to improve
the accuracy of this method. Three such improvements
are shown in Figure 4. Figure 4A is the smallest change.
Here a pullup resistor has been added to the G output
line and the G line Is run open drain internally, I.e., the
internal pullup is removed. This improves the "bounce"
problem mentioned earlier. The G line will go to the high
state and remain there with this setup. However, the
addition of the resistor does little more than eliminate
the bounce. The degree of improvement is not great, but
it is an easy way to eliminate a minor source of error.

Remember also that we are measuring time. Therefore
variation in the RC value will have a direct, linear effect
on the time required to measure a given voltage. It is
also necessary that the time base for the COP420 b~
accurate. A variation in the accuracy in the operating
frequency -of the COP420 will have a direct impact on
the accuracy of the result.
Given the errors mentioned so far and assuming that no
changes are made in the hardware, the accuracy of the
technique then is determined by the resolution of the
time measurement. This is improved in two ways: in·
crease the RC time constant so that there is a smaller
change in capacitor voltage for a given time period or
try to minimize the loop time required to increment the
counter. Lengthening the RC time constant is easier but
the cost is increased conversion time. The minimum
time to increment a 5 to 8 bit binary counter and test an

Figure 48 is the next step. A 74C04 is used as a buffer.
The 74C04 was chosen because of its symmetric output
characteristics. Any CMOS gate with such characteris·
tics could be used. The software can easily be adjusted
to provide the proper polarity. The COP420 output drives
a CMOS gate which in turn drives the RC network. This
change does make significant improvements in accu·
racy. With a light load the CMOS gate will typically

% ERROR IN MEASUREO VOLTAGE (FOR A GIVEN
PERIOO) AS A RESULT OF A ±10% VARIATION IN
RCVALUE

3.5
3
2.5

1.5
w

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co
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ffi

.5

.'"en'"
I1i
:IE

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-.5

.6

.8

1.2 1.4 1.6

1.8

2

2.2

2.4

2.6

2.8

3.2

IIRC~

CALCULATEO (NO ERROR FACTOR)

-1

'"
'"w,.-1.5
-2
-2.5
-3
-3.5
-4

Figure 3

2-87

3.4

3.6

3.8

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2.
CD

.....

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the system and eliminates the need to add another
package to the system.

swing from ground to Vcc and its output level is not as
likely to be affected by the capacitor discharge.
Figure 4C is the best approach, but it involves the
greatest component cost. Here two G outputs are
controlling analog switches. Ground is connected to the
RC network to discharge the capacitor, and a positive
reference is used to charge the capacitor. This refer·
ence can be any suitable voltage source: zener diodes,
Vec , etc. The controlling voltage tolerance is now
clearly the tolerance of the reference. Precise voltage
references are readily obtainable. Figure 4C also shows
an analog switch connected directly across the
capacitor to speed up the capacitor'discharge time.
When using this version of the basic scheme, remember
to include the 'on' resistance of the analog switch
connected to VREF in the RC calculation. Failure to do
so will introduce error into the result.

C. CONCLUSIONS
This approach is an inexpensive way to perform an AID
cqnversion. However, it is not that accurate. With a 10%
Vcc supply and a 10% tolerance in the RC value and
10% variation in the oscillator frequency the best that
can be hoped for is about 25% accuracy. If a 1 % refer·
ence voltage is used, this accuracy becomes about 15%.
Under laboratory conditions - holding all variables
constant and using precise measured values in the cal·
culations --' the configuration of Figure 2 yielded 5 bit
accuracy over an input range of 0 to 3.5 volts; Over the
same range and under the same conditions, the circuit
of Figure 4B yield 7 to 8 bit accuracy. It must be
emphasized that these accuracies were obtained under
controlled conditions. All variables were held constant
and actual measured values were used. in all calcula·
tions. It is unlikely that the general situation will yield
these accuracies unless adjustments are provided and
a calibration procedure is used. This could defeat the
low cost objective.

Note that the LM339 is a quad comparator. If these
comparators are not otherwise needed in the system,
they can be used in much the same manner as the
CMOS gate mentioned above. They can be used to
buffer the output of the COPSTM device and to reset the
capacitor, or whatever other function is required. This
has the advantage of fully utilizing the components in

Vee
Vee

Vee
' CKI

CKO

V,N
20

V,N
20

IN3

IN3

COP420
'COP420

-=Vee
21

5k

Vee

B

A

Vee

COP420

GO

L-__

~

______________________--J21

c
Figure 4

2·88

()

III. Pulse Width Modulation

solving fllr t1 and t2 we have:

(Duty Cycle) Technique

t1 = -RC In[(VA - VO)/(Vs - YO)]
t2 = - RC In[(Vs - V1)/(VA - V1)]

A. MATHEMATICAL ANALYSIS

VA =V1N -d1
Vs =V1N +d2
substituting the above, the equations for t1 and t2
become:

In this technique, the capacitor voltage Vc is compared
to the voltage to be measured by means of an analog
comparator. The duty cycle is then adjusted to cause Vc
to approach the input voltage. The COPSTM device reads
the comparator output and then drives one of its
outputs high or low depending on the result, i.e., if Vc is
lower than the input voltage, a positive voltage (V1) is
applied to charge the capacitor; if Vc is higher than the
input voltage, a lower voltage (VO) is applied to
discharge the capacitor. Thus the capacitor voltage will
seek a point where.it varies above and below the input
voltage by a small amount. Figure 6 illustrates the
capaCitor voltage and the comparator output.

t1 = - RC In{[1 - (d1/(V 1N - VO))]/[1 + (d2/(V1N - VO))Jl
t2 = -RC In{[1 - (d2/(VIN - V1))]/[1 - (d1/(VIN - V1))Jl
the equations reduce by means of the following
assumptions:
1. d1 =d2=d
2. IVIN - VOl» d
IVIN - V11» d
applying these assumptions, we get the following:
t1 = - RC In[(1 + x)/(1 - x)] where x = ~d/(VIN - YO)
t2 = - RC In[(1 + x)/(1 - y)] where y = d/(VIN - V1)

Some mathematical analysis here will be useful to help
clarify the technique and to point out its restrictions.
Referrring to Figure 6, we have the following:

because of the assumptions above, the x and y terms in
the preceding equations are less than 1, therefore the
following expansion can be used:

VA = VO+ lVs - VO]le* *( -t1/RC)]
Vs=VA+lV1-VAH1-e**(-t2/RC)]
= V1 + [VA - V1][e * *( -t2/RC)]

In[(1 +z)/(1-z)]=2[z+(z**3)/3+(z**5)/5+ ... ]

VI-

vo-

I
I
I
I..... T1 __ I_T2--1
I

I

I

V _(V1-VO)·T1
c- 11 +T2

I'lgure 5

VI~----------------------------------

VB

v
v
--11---12---VO~----------------------------------

CAPACITOR VOLTAGE

COMPARATOR OUTPUT

Figure 6

2·89

Z

2CD
.....

let:

The pulse width modulation, or duty cycle, conversion
technique is based on the fact that if a repetitive pulse
waveform is applied to an RC network, the capacitor will
charge to the average voltage of the waveform provided
that the RC time constant is sufficiently large relative to
the pulse period. See Figure 5.

o-a

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CD

'0

z

a...

oo

then select, within reason, how close to the references
he can allow the input voltage to go.

substituting we have:
t1 = -2RC[x + (x**3)/3 + ... 1

The next consideration is really just one of simplifica·
tion. It is clear that if VO is zero, it drops out of the first
equation and the relationship is simplified. Therefore, it
is desireable to use zero volts as the VO value. The
equation then becomes:

t2 = -2RC[y + (y* *3)/3 + ... 1
under assumption 2 above, the linear term completely
swamps the exponential terms yielding the following
result (after substituting back into the equation):
t1 = 2dRC/(VIN - YO)

t2 = -2dRC/(VIN - Vl)

VIN = V1t2/(t 1 + t2).

therefore:

It is obvious by now that the heart of the technique lies
in accurately measuring the times t1 and t2. Clearly this
requires that the time base of the COP420 be accurate.
Short term variations in the COP420 time base will clearly
impact the accuracy of the result. In addition to that
there is a serious problem in being able to check the
comparator output often enough to get any accuracy
and resolution out of simply measuring the times t1 and
t2. This problem is circumvented by measuring many
periods of the waveform. Doing this gives a large aver·
age,which improves the accuracy and tends to elimi·
nate any spurious changes. Of course, the trade off is
increased time to do the conversion. However if the time
is available, the technique becomes restricted only by
the accuracy of the external components. Those of the
comparator and the reference voltage are most critical.

t1/(t1 +t2)=(V1-VIN )/(V1-VO)
t2/(t 1 + t2) = (VIN - VO)/(V1 - YO)

solving for VIN:
VIN = [t2/(t1 + t2)][V1 - VOl + VO
orVIN =V1-[t1/(t1 +t2)][V1-VOI
It follows from the above results that by measuring the
times t1 and t2, the input voltage can be accurately
determined. As will be seen, the restrictions based upon
the assumptions above do not cause any serious
difficulty.

A.2 General Accuracy Considerations
In the preceding calculations it was assumed that the
differential output above and below the input voltage
was the same. If the comparator output is checked at
absolutely regular intervals, and if the intervals are kept
as small as possible this assumption can be fairly
easily guaranteed - at least to within the comparator
offset which is only a few millivolts. As we shall see,
this aspect of the technique presents few, if any, diffi·
culties. In addition, there is an RC network at the input
of the comparator. The time constant of this network
must be long relative to the time between checks of the
comparator output. This will insure that the capacitor
voltage does not change very much between checks
and thereby help to insure that the differences above
and below the input voltage are the same.

It is clear from the equation above that the accuracy of
the result is directly dependent upon the accuracy of
the reference voltage V1. In other words, it is not pas·
sible to be more accurate than the reference voltage. If,
however, all that is required is a ratio between the input
voltage and the reference voltage, the accuracy of the
reference will not be a controlling factor provided that
the input voltage tracks the reference. This requires that
the input voltage be generated from the reference voltage
in some form, e.g., a voltage divider with VIN coming off
a variable resistance.
Finally, we have noted that the difference d must be
small. If the capacitor had to charge or discharge a long
way toward VIN' the nonlinearity of the capacitor charge
curve would be significant. This therefore requires that
the conversion begin with the capacitor voltage close to
the input voltage.

The next major approximation has to do with the differ·
ence between the input voltage and either V1 or YO. We
have relied on this difference being much greater than
the amount the capacitor voltage changes above and
below the input voltage. This approximation allows the
nonlinear terms in the logarithmic expansion to be
discarded. In practicality, the approximation means
that the input voltage must not be "close" to either V1
or YO. Therefore, it becomes necessary to determine
how closely the input voltage can approach V1 or YO. It
is obvious that the smaller the difference d can be
made, the closer the input voltage can approach either
reference. The following calculations illustrate the
method for determining that difference d. Note, using
either V1 or VO produces the same result. Thus
V=V1 =VO.

Note that the RC value is not part of the equation.
Therefore the accuracy of the time constant has no ef·
fect on the result as long as the time constant is long
relative to the time between checks of the comparator
output.
The final paint is that the reference voltages, whatever
they may be, must be hard sources. Should these vol·
tages vary or drift at all, they will directly affect the
result. In those configurations where the references are
being switched in and out, the voltage should not change
when it is switched into the circuit.

For at least 1% accuracy

B. BASIC IMPLEMENTATION

x +(x**3)/3 < 1.01x
therefore x < 0.173

B.1. General

since x =d/l(VIN - V)I we have d < 0.1731(VIN - V)I.

The objective, then, is to measure the times t1 and t2.
This is accomplished in the software by means of two
counters. One of the two counters counts the t2 time;
the other counter counts the total time t1 + t2.

Using the same analysis for 0.1 % accuracy in the
approximation we get d < 0.05481(VIN - V)I. By applying
this relationship, the RC time constant can be adjusted
so that, within the time interval, the capacitor voltage
does not change by more than d volts. The user may

It is necessary to check the comparator output at
regular intervals. Thus the software must insure that

2·90

path lengths through the test and increment loops are
equal in time. Further it is desirable to keep the time
required to increment the counters as short as possible.
A trade off usually comes into play here. The shortest
loop in terms of code required to implement the
function is rarely the shortest loop in terms of time
required to execute the function. The user has to decide
which implementation is best for him. The choice will
frequently be governed by factors other than the AID
conversion limits.

The code and flow chart in Figure 8 implement the
technique as described above. The large averaging
technique is used as it would be too difficult to measure
the times t1 and t2 in a single period. The total time,
t1 + t2, is the viewing window under complete control of
the software. This window is a time equal to the total
number of counts, determined by desired accuracy,
multiplied by the loop time for a single count. A second
counter is counting the t2 time. Special ca,e is taken to
insure that all paths through the code take the same
length of time since the integrity of the time count is the
essence of the technique. The full conversion scheme
would use the subroutine in Figure 8. Normally the
subroutine would be called first just to get the capacitor
charged close to the input voltage. The result obtained
here would be discarded. Then the routine would be
called a second time and the result used as required.

It must be remembered that we are now dealing with
analog signals. If significant accuracy is required, we
are handling very small analog signals. This requires
the user to take precautions that are normally required
when working with linear circuits, e.g., power supply
decoupling and bypassing, lead length restrictions,
crosstalk, op amp and comparator stabilization and
compensation, desired and undesired feedback, etc. As
greater accuracy is sought these factors are more and
more significant. It is suggested that the reader refer to
the National Semiconductor Linear Applications
Handbook and to the data sheets for the various
components inVOlved to see what specific precautions
should be taken both in general and for a specific
device.

In the configuration in Figure 7, there is an RC network
in both input legs of the comparator. This is to balance
the inputs of the device. For this reason, R1 = R2. C1 is
the capacitor whose voltage Is being varied by the pulse
waveform. C2 is in the circuit only for stabilization and
symmetry and is not significant in the result. The
comparator tends to oscillate when the + and - inputs
are nearly equal without capaCitor C2 in the circuit.

B.2 The Basic Circuit

As would be expected, the basic circuit has some diffi·
culties. By far the most serious of these difficulties is
the output level of the G line. To be sure of the high and
low level of this output the levels should be measured.
The "1" level will be between the spec minimum of 2.4V
and Vcc (here assumed to be 5 volts). The "0" level will
be between the O.4V spec maximum and ground. With
light loads, these levels are likely to vary from device to
device. Furthermore, we have the same "1" level
problem that was mentioned in the simplest technique:
the capacitive load is large and the capaCitor is

Figure 7 shows the diagram for the basic circuit
required to implement the duty cycle conversion
scheme. The flow chart and code required to implement
the function are shown in Figure 8. Note that the flow
chart and code do not change - except for possible
polarity change on output to allow for an inverting
buffer - for any of the improvements in accuracy
discussed later. The only exception to this is the
technique illustrated in Figure 10 and the variations
there are minor.

Vee

3k
20 IN3

COP420

Vee = +5V
VIN = 0 -3.5V

Figure 7. Basic Duty Cycle AID

2·91

o

o
."
Z

2CD

....

,..
.CD

'0
a..

z

o
o

charging while the output is trying to go to the high
level.

Under laboratory conditions - holding all variables
constant and using precise measured values In the
calculations - the circuit of Figure 7 yielded 5 bit ± 1
bit accuracy over the range of VO (here measured to be
0.028 volts) to 3.5 volts (the maximum specified Input
voltage for the comparator with Vs 5 volts). Increasing
the number of total counts had very little "effect on the
result. In the general case, the basic scheme should not
be relied upon for more than 4 bits of accuracy,
especially if one assumes that V1 Vee and VO O. As
shall be seen, it is not difficult to improve this accuracy
considerably.

There is also a problem with the low level. When the
output goes low, the capacitor begins to discharge
through the output device of the COP420. This dis·
charge current has the effect of raising the "0" level and
thereby introducing. error. Note that we are not talking
about large changes In the voltages, especially the low
level. Typically, the change will only be a few millivolts
but that can translate into~ a loss of accuracy of several
bits.

=
=

; ATIlI' IS· THE FULL CONVERSION SCHEME WRITTEN AS A SUBROUTINE
AOI(1l1:
; MAKE SURE COUNTERS CLEARED
LBI
1. 10
CLEAR
.1SRP
LBI
2.10
.1SRP
CLEAR
; PRELOAD FOR TOTAL COUNT
2048
1. 13
LBI
STII
0
0
STII
STII
8
AO' DIll : ININ
,READ COMPARATOR--INPUT TO 420 = IN3
AISC
8
,JP
SNDOI
SNIlJI\: LBI
; USING OMG BELOW TO SAVE STATE OF OTHER G
3.0
; VALUES IF IT WAS NECESSARY TO DO SO. ELSE USE OGI
,VIN> Vc.DRIVE Vc HIGHER
5MB
2
,THIS CODE STRAIGHT LINED FOR SPEED
OMG
,APPLV POSITIVE REFERENCE
SC
, INCREMENT THE SUB COUNTER
CLRA
2.13
LBI
ASC
NOP
XIS
CLRA
ASC
; BINARV INCREMENT.
NOP
,WOULD ELIMINATE THESE 4 WORDS IF 8 BIT
XIS
., COUNTER OR LESS-HERE SET UP FOR UP TO 12 BIl
CLRA
,COUNTER
ASC
NOP
X
.1P
TOTAL
SNIlOJ: LBI
3.0
RMB
2
OMG
CLRA
,THIS PART OF THE CODE MERELV INSURES THAT
AISC
10
,ALL PATHS THROUGH THE ROUTINE ARE EQUAL IN TI
NOP
01 V:
AISC
1
JP
DLV
Hnl\l:
CLRA
LSI
1. 13
SC
; INCREMENT THE TOTAL LOOP COUNTER
ASC
,WHEN OVERFL.OW. DONE SO EX IT
NOP
XIS
CLRA
ASC

AlI1IK':
CLEAR:

NOP
XIS
CLRA
ASC
.1P
RET
X
JP
.PAGE
CLRA
XIS
JP
RET

ATOD2
ATODI
2
CLEAR

Figure 8A: Duty Cycle AID Code

2·92

=

o

o"'C
Z

9.
CD
.....

(

AlOOl

)

(

Figure BB. Duty Cycle AID Flow Chart

C. ACCURACY IMPROVEMENTS

Under laboratory conditions, the circuit of Figure 9A
yielded the accuracies as indicated below for various
total counts. The accuracy increased with the total
count until the count exceeded 2048. There was no
significant increase in accuracy with this circuit for
counts in excess of 2048. (Remember that these results
were obtained under controlled conditions). We may
then view the results obtained with 2048 counts as the
upper limit of accuracy with the circuit of Figure 9A. The
results were as,follows:

C.1 General Improvements
Figure 9 illustrates circuit changes that will make
significant improvements in the accuracy of the
technique. In Figure 9A a CMOS buffer is used to drive
the RC network. The output of the COP420 drives the
CMOS gate, which here is a 74C04 because of its output
characteristics. The main thing that this technique does
is ,to reduce the difficulties with the output levels.
Typically, VO is 0 volts and V1 is Vcc. We also have a
"harder" source for the voltages - the levels don't
·change while the capacitor is charging or discharging.
Now, even more clearly than before, the accuracy of Vee
is the contro'liing voltage tolerance. The accuracy of the
result will be no better than the accuracy of Vee (for a
system requiring absolute accuracy).

Total
Count
512
1024
2048
4096

2·93

Resultant Accuracy
8± 112 bits
9± 1 bits
9± 1/2 bits
9±1/2bits

,...

G)

0

23 G2
Vee

Vee

Z

fl.

100k

3k

0
0

20 IN3

100k

COP420

VIN

Vee

A

V1

VO

23

G2

'/,CD4066
COP420
100k

100k
VIN

Vee

Vee

B

Vee

Vee

VO
VI

COP420

L-~~

____________________

2~3

G2

c
Figure 9. Improvements to Duty Cycle ·A/D

2·94

The circuit of Figure 9B makes a significant change to
improve accuracy. Now the GOP420 is controlling
analog switches and switching in positive and negative
references. Therefore the accuracy of the reference
voltages is the controlling factor. Generally this will
improve the accuracy over that obtained with Figure 9A.
With the circuit of Figure 9B, with VO = 1 volt (negative
reference), and V1 = 3 volts (positive reference), 9 bit
accuracy was achieved with a total count of 1024. VO
and V1 were arbitrarily chosen to place, the input
voltage approximately in the center of the allowable
comparator input range with Vs = 5 volts. Remember,
the accuracy of the references is controlling. The result
can be no more accurate than the references.
Furthermore, these references must be hard sources;
i.e., they must not change when they are switched into
the circuit as that contributes error into the result.

Figure 10 illustrates a further refinement of the basic
approach. This configuration can be used if greater
accuracies are needed. The major change is the
addition of a summing amplifier to the circuit for the
purpose of adding a fixed offset voltage to the input
voltage. This has the effect of moving the input voltage
away from the negative reference (which is 0 volts here).
This offset voltage should be stable as the changes in it
will directly affect the result. The offset voltage should
be chosen so as to place the effective input voltage (the
voltage a~ the comparator input) approximately in the
center of the range between the two references. The
precise value of the offset in not critical nor is its
source. The forward voltage drop across a germanium
diode is used as the offset in Figure 10, but this offset
can be generated in any convenient manner. The
forward voltage drop of the germanium diode is
aproximately 0.3 volts. Given this and the negative
reference of 0 volts and a positive reference of 2.5 volts,
the input voltage is restricted to a range of 0 to 2 volts.
Therefore, the effective input voltage (at the comparator
input) is approximately 0.3 volts to 2.3 volts - well
within the limits of the two references. The circuit also
includes provision for an autozero self calibration
procedure.

In Figure 9G, capacitive feedback was added to the
comparator circuit and the series resistance to VIN was
decreased. The feedback added hysteresis and forced
the comparator to slew at its maximum rate (significant
errors are introduced if the comparator does not change
state in a time shorter than the cycle time of the controller). Both of these changes resulted in increased accuracy of the result. With VO = 0, V1 = 5 volts {Vcd and Vcc
held steady at 5.000 volts, an accuracy of 10 bits ± 1 bit
was achieved over the input range of 0 to 3.5 volts.

Note that the resistors in the summing amplifier should
be matched. The absolute accuracy of these resistors is
not Significant, but their accuracy relative to one
another can have a significant bearing on the result.
The restriction is imposed so that the output of the
summing amplifier is exactly the sum of the input
voltage and the offset voltage. This requires unity gain

It is obviously possible to use any combination of the
configurations in Figure 9 for a given application. What
is used will depend on the user and his specific
requirements.

4

Vee

lOOk
2.5V
9102

Vee

lOOk"

>-+-IIN3
B.2k
0.5-1~F

~"'-'---"VV'r----'
Vee

Vee= +5V
VINo---....

0",VIN",2V

"RESISTORS SHOULD BE MATCHED

Flgur~ 10. Improved Duty Cycle AID with Autozero

2-95

COP420

o

o"'tI
Z

9CD

...

,...
CD

'0

z

c..
o
o

through the amplifier and that the impedance in each
summing leg be the same. These effects can become
very serious if one Is trying for significant accuracy e.g., if 12 bit accuracy is being sought 1% matching of
those resistors can introduce an error of 1% maximum.
While 1% accurate is fairly good,it is significantly less
tllan 12 bit accuracy. Related to this effect is a possible
problem with the source impedance of the input
voltage. If that impedance Is significant in terms of its
ratio to the summing resistor, errors are introduced just
as if the resistors are mismatched. "Significant" is
determined in terms of the desired system accuracy and
the relative Impedance values. The comparator section
is using some feedback to provide hysteresis for
stability and a low series resistance is used for the
input to the comparator.

autozero function by tying the input to ground and
measuring the result. Thus the system offsets ean be
calculated, stored and subtracted from the result. This
improves the accuracy and is also more forgiving on the
choice of the comparator and op amp selected. Furthermore, the offset can be periodically recomputed by the
COP420 thereby compensating for drift in system
offsets. Nonetheless, the accuracy of the reference is
the controlling factor. It is NOT possible to obtain an
absolute (as opposed to ratiometric) accuracy of 12 bits
without a reference that is accurate to 12 bits. The
LM136 used in Figure 10 is a 1% reference. Although
. not inherently accurate to 12 bits, the voltage of the
LM136 may be trimmed to an exact value by means of a
variable resistor. The data sheet of the LM136 iIIus·
trates this connection. Under laboratory conditions, the
circuit of Figure 1 yielded 11 bit ± 1 bit accuracy with a
total count of 4096 over the input range of 0 to 2 volts.
Figure 11 indicates the flow chart and the code required
to implement the technique of Figure 10.

Most significantly, this configuration allows a true
zeroing of the system. Through the additional analog
switches shown, the COP420 can easily perform an

,CODE FOR IMPROVED A TO 0 PULSE WIDTH METHOD
FIGURE 8A FOR CODE FOR ROUTINE ATOD

,,SEE

Alnn.R: LIlI
3,0
,DO AUTO ZERO, 3. 0 CONTAINS G STATUS
RMIl
3
,SET UP TO GRNDINPUT & MEASURE OFFSET
JSR
ATOD
,FIRST TIME IS TO GET CLOSE
JSR
AT 00
,MEASURE THE OFFSET
LIlI
2.13
,NOW SAVE THE OFFSET VOLTAGE
XI-HI:
LD
1
,SAVE THE OFFSET VALUE IN M3
XIS
1
JP
XFER
LBI
0.0
JP
INPUT
MHI!lun:
,NOW DO REAL MEASUR(lST TIME IS OFFSET>
JSR
ATOD
,FIRST TIME TO GET CLOSE
JSR
ATOD
,NOW REAL MEASUREMENT
JSRP
BINSUB ,SUBTRACT THE OFFSET
,HAVE THE VALUE AT THIS POINT(IN BINARY)-NOW DO WHAT
,THE APPLICATION REQUIRES.
VALUE MUST BE MULTIPLIED
,BY (VREF+/TOTAL COUNT) TO GET FINAL VALUE IF SUCH IS
, DESIRED
LBI
1.0
,INCREMENT COUNTER FOR NEW OFFSET MEASURE
LD
AISC
1
JP
SAVE
X
,IS 16TH TIME. MEASURE OFFSET AGAIN
JP
AUTZER
SIIVl·.:

X

LBI
5MB
JP
. PAGE
BIN::;UB: LBI
SC
BNH\m~':
LD
CAse
NOP
XIS
JP
RET

3.0
·3
MEASUR
2
3.13

,SET BIT SO CAN MEASURE VIN

1

BNSUB2

Figure 11A. Duly Cycle A 10 D, Improved Method

2-96

(')

o"'tJ
Z

9.....

CD

Vc

(

Figure 12. Dual Slope Integration -

Basic Concept

dV
Ix=C""dt = Vx/R
dv
Vx=RCdi

\~' Vxdt = \ v RCdV

.0

.0

VxT1 = RCV
V = VxT1/RC = IxT1/C
Similarly:
dV
IREF = C dt = VREF/R
dV
VREF = RC'dt
'Tl+Tx

'0

\ VREFdt = \ RCdV
. T1

J

V

VREFTX= -RCV
V= -VREFTx/RC
- VREFTx/RC = VxT1/RC

Figure 11 B. Flow Chart for Improved Duty Cycle AID

Vx = -VREFTx/T1
Two important facts arise from the preceding mathematics. First of all, there is a linear relationship involved in
determining the unknown voltage. Secondly, the nega·
tive sign in the final equation indicates that the refer·
ence and the unknown, relative to some point (which
may be 0 volts or some bias voltage), have opposite
polarity. Thus, if it is desired to measure 0 to +5 volts,
the reference voltage must be -5 volts. If the input is
restricted to 2.5 to 5 volts, the reference can be 0 volts
as the integrator and comparator are biased at +2.5
volts (then the 0 volts is in fact -2.5 volts relative to the
biasing voltage, and the input range is 0 to 2.5 volts
relative to the same bias voltage).

IV. Dual Slope Integration Techniques
A. MATHEMATICAL BACKGROUND
(Some of this background information is taken from
National Semiconductor linear Applications Note
AN-155. The reader is referred to that document for
other related general information.)
The basic approach of dual slope integration
conversion techniques is to integrate a voltage across a
capacitor for a fixed time, and then to integrate in the
other direction with a known voltage until the starting
point is reached. The ratio of the two times then
represents the 'unknown ·voltage. Some of the math
below in conjunction with Figure 12 will illustrate the
approach.

There are some difficulties with dual polarity conver·
sion using the dual slope method. It is clear from the
math above that if the input voltage will be dual polarity,
it is necessary to have two references - one of each
polarity. The midrange biasing arrangement briefly

2-97

T""

CI)

'5

z

fl..

oo

B. THE BASIC DUAL SLOPE TECHNIQUE

described above eliminates the need for two different
polarities but does not help very much since two
references are still required - one at the positive value
and one at the bias value. Ground is the other reference.
Further, the need to select one of two references further,
complicates the circuitry involved to implement the
approach. Also, the dual requirement brings up a
difficulty with the bias currents of the integrator and
comparator. They could add to the slope in one polarity
and subtract in the other.

Figure 13 indicates an implementation of the basic dual
slope techn ique. This is a single polarity system and
thus requires only the single reference voltage. The
circuit of Figure 13 is perhaps not the cheapest way to
implement such a scheme but it is representative and
illustrates the factors that must be considered.
Consider first the means of initializing the integrating
capacitor C1. The routine here connects the input to
ground and does a conversion on zero volts as a means
of initialization. Subsequently - and this is typical of
the more usual technique - two conversions are
performed. The first conversion is to initialize the
capacitor. The second conversion yields the result.
Some form of initialization or calibration prodcedure is
required to achieve optimum accuracy from dual slope
conversion schemes.

The only real operational difficulty in dual slope
systems is establishing the initial conditions on the
integrating capacitor. If this capacitor is not at the
proper initial conditions, accuracy will be severely
impaired. Figure 12 indicates it switch across the
capacitor as a means of initializing it. In a software
driven system, the initilization can be accomplished by
doing two successive conversions. The result of the
first conversion is discarded. It is performed only to
initialize, the capacitor. The second conversion
produces the valid result. One need only insure that
there is not significant time lapse between the two
conversions. They should take place immediately after
one another.

The comparator in this circuit is used in the inverting
mode and has positive feedback as recommended in
the LM 111 data sheet. The voltage reference is the
LH0070, which is a 0.01 % reference. A resistive voltage
divider on the LH0070 creates the 5 volt value. The use
of the voltage divider brings up two difficulties (which
can be overcome if the LH0070 is used at its full value,
thus eliminating the divider, and the result properly
scaled in the microcontroller or series integrating
resistor increased). First, the impedance of the reference must be small relative to the series resistance
used in the integrator. If this were not the case, the

This approach obviously lengthens conversion time but
it eliminates many problems. The alternative to this
approach of two successive conversions is to take a
great deal of care in insuring the initial state of the
integrating capacitor and in selecting op amps and
comparators with low offsets.

Vs
VIN

0-'+----... "-+-+-f:'"
10

COP420
lOOk
20 IN3

+5,OOOV

470k

-Vs

*

1M
VIN
2 Your LH0070

-Vs
500k
lOOk

Vs= +15V
-Vs= -15V
Vee = +5V
VIN = 0 TO -;5V

':'

Figure 13. Basic Dual Slope Integration AID Scheme

2-98

Vee

Figure 14 shows the flow chart and code required to
implement the basic dual slope technique as shown in
Figure 13. Under laboratory conditions an accuracy of
12 bits ±1 bit was achieved. The method is slow, with
the maximum conversion time equal to 2 x TREF. Notice
that the accuracy of Vcc and that of the integrating
resistor and capacitor are not involved in the accuracy
of the result. The accuracy of VREF is, of course,
controlling if absolute accuracy - rather than ratiometric accuracy - is desired. The absolute accuracy of
the circuit can be no better than the accuracy of the
reference. If ratiometric accuracy is all that is required,
there is no particular problem. The accuracy is merely
relative to the reference. The Rand C values do not
impact the accuracy because the integration in both
directions it> being done through the same Rand C.
Results would be quite different is a different value of R
or C was used for one of the slopes.
'

slopes would show an effect due to the difference in the
R value between the applied reference voltage and the
unknown input. (By the same token, the output impedance of the source supplying the unknown must also be
small relative to that series integrating resistor).
Secondly, the bias currents of the integrator may be
such as to affect the reference voltage when it is
coming from a simple resistor divider. Both problems
are reduced if small resistor values are used in the
divider. Note also that current mode switching would
reduce the problem as well. It should be pointed out that
the errors introduced by these problems are not gross
deviations from the expected value. They are small
errors that will not make much difference in the majority
of applications. They are, however the kind of errors
that can make the difference between a system accurate to 10 bits and one accurate to 12 bits (assuming all
other factors the same).

DlJl !iI f':

oGI
,HOLD THE INPUT TO GROUND TO RESET THE
LBI
2,11
, INTEGRATING CAPACITOR
JSRP
CLEAR
,CLEAR THE COUNTER
JSR
INCRA
,TO GET US CLOSE, NEXT READING IS REAL
CI f-/\U;': LB I
2, 11
,NOW CLEAR THE COUNTER
JSRP
CLEAR
,MAKE SURE COUNTER CLEARED TO ZERO
,J, 1~
0 AND START AT 1,13 FOR COUNT = 4096
, J, J~,
14 AND START AT 1. 12 FOR COUNT
8192
, J. I~,
12 AND START AT 1. 12 FOR COUNT = 16384
,1-(11,[ OW SAME PATTERN FOR OTHER COUNTS
INCRA, RUN THRU THE INCREMENTS
,)SR
, NOW HAVE THE BINARY VALUE, USE IT AS IS OR
, MULTIPLY BY (V,·ef/TOTAL COUNT> TO CREATE THE VOLTAGE
, RESULT--THEN CONTINUE WITH THE OPERATION
l.B I
2, 11
JSRP
CLEAR
,CLEAR THE COUNTER
JSR
INCRA
,TO GET CAP CLOSE TO 0 AGAIN
JP
CLEAR2
,HILl UWING SUBROUTINE INCRA IS THE REAL PART OF THE ROUTINE
,CIINGFRNED WITH THE COUNTING FOR THE CONVERSION.
IN(;UI\:
LBI
1,15
,Rl IS CLEARED PRIOR TO START
STII
15
,PRESET THE COUNTER FOR 4096
OGI
4
,APPLY VIN
IN<:I!:
LBI
1. 12

MI·I\!illR:

SC

[lINAIH:

CLRA
ASC
NOP
XIS
JP
NOP
NOP
SKC
JP
OGI
INCI!;':
LBI
SC
IllNAI);'>: CLRA
ASC
NOP
XIS
JP
ININ
AISC
JP
OU1PU1: OGI
RET

BINADl
,2 NOPS TO EGUALIZE TIMES

INCR
2
2, 12

BINAD2
8
INCR2
1

,DONE,NOW APPLY VREF
,COUNT ,UNTIL COMPARATOR CHANGES

,STRAIGHT LINE
; SAVE WORDS BY
; SEE IF IN3=1
,IN3 IS O,KEEP
, KEEP INPUT AT

THE ADD FOR SPEED
USING G
COUNTING
0

Figure 14A. Dual Slope AID Code

2-99

o

o'"tJ
Z

9CD

....

,...

Go)

VREF

0

z

a..

0
0

VMAX

(

INCR A )
Vc

I

I

I

I

I

l--tAEF-I ___ tX_'
I

,

I

Figure 15. Modified Dual Slope -

Basic Concept

The math analysis is much the same:
dV
Ix = C di= (Vx - VMAX)/R
dV
VX-VMAX=RCdi
(Vx - VMAX )T1 = RC
V = (V x - VMAX)T1/RC
Similarly:
dV
IREF = C di . = (VREF - VMAX)/R
(VREF-VMAX)Tx= -VRC
V= -(VREF-VMAX)Tx/RC
(VMAX - VREF)Tx = (V x - VMAX )T1
Vx = VMAX + (V MAX - VREF)Tx /T1
The' main d'ifference between this and the basic
approach is the offset voltage VMAX ' The main
restriction is that all input voltage values (V x) are less
than VMAX ' It is also apparent that the total count is
proportional to the difference between VMAX and Vx. The
only significant effect of this is, however, to slightly
complicate the arithmetic required to arrive at a value
for Vx .
Given that the input voltage Vx is always less than
VMAX , the modified dual slope technique is automatic
polarity. This fact comes straight out of the equation
above. Thus dual polarity references are not required.
However, two precise voltages are required: VMAX and
VREF ' However, the VMAX value can be used for a zero
adjust as indicated in Figure 16, This means that the
VMAX value need not be so precise as it will be adjusted
in a calibration procedure to produce a zero output. This
adjustment amounts to a compensation for the bias
currents and offsets. Thus the COP420 can use the
supposed value of VMAX with VMAX later being
"tweaked" to give the proper result at zero input. In
addition, the initialization loop for the integrating
capacitor includes the comparator. Thus the initial
condition on the capacitor becomes not zero but the

Figure 14B. Basic Dual Slope AID Flow Chart

C. MODIFIED DUAL SLOPE TECHNIQUE
C.1 General
The basic idea of the modified dual slope technique is
the same as that of the basic approach. The mOdified
approach eliminates the need for dual polarity refer·
ences and is also more forgiving in the selection of the
op amp and comparator required. Figure 15 illustrates
the basic idea
'

2·100

sum of the offset voltages of the comparator and op
amp. Thus the choice of these components is not
critical in a modified dual slope approach.

capacitor can charge to either supply voltage depending
on which direction it is integrating. This causes the
wave shape shown in Figure 15 to flatten out. This effec·
tively limits the input range for all accuracy is lost once
that waveform flattens out. In fact, this was the limiting
factor on the accuracy in Figure 16 as shown. Given the
amount of time required for an increment of the counter
for TREF (or Tx), it was not possible to reach the 4096
counts required for 12 bit accuracy before the waveform
flattened out. Decreasing the total count solves the
problem at the expense of accuracy. It is therefore
desirable to keep the loop time required for an incre·
ment as fast as possible. The code to implement Figure
16 is shown in Figurli 17 and reflects that concern. The
other way to solve the problem is to use a large value for
Rand C. This is the easiest solution and preserves
accuracy. its cost is increased conversion time.

C.2 An Example of the Modified Dual Slope
Approach
Figure 16 illustrates an implementation of the modified
dual slope technique. The system is calibrated by
holding VIN to ground and then adjusting VMAX for a "0"
result. Capacitor C1 is the integrating capacitor.
Capacitor C2 is used only to cause a rapid transition on
the comparator output. C2 is especially useful if an op
amp is being used as the comparator stage. Resistor R1
is just part of the capacitor initializing loop. An LH0070
is being used to generate the reference voltage and the
VMAX value. The discussion previously about these
being hard sources is equally relevant here. In fact, this
problem was much more significant in this particular
implementation and made the difference between a 10
and 12 bit system. As shown, the technique was
accurate to 10 bits. Another bit was obtained when the
VMAX and VREF values were buffered. It must be
remembered that when trying to achieve accuracies of
this magnitude board layout, parts placement, lead
length, etc. become significant factors that must be
specifically addressed by the user.

Both the basic and modified dual slope schemes can be
very accurate and are commonly used. They tend to be
relatively slow. In many applications, however, speed is
not a factor and these approaches can serve very well.
There are various approaches to dual slope analog to
digital conversion which try to improve speed and/or
accuracy. These are usually multiple ramping schemes
of one form or another. The heart of the approach is the
basic scheme described above. It is not the purpose
here to delve into all the possible ways that dual slope
conversion may be accomplished. The control software
is not significantly different regardless of which parti·
cular variation is used. The basic ramping control is the
same as that indicated here.

There are some other considerations in using this
technique. The amount of time required to count the
specified number of counts starts to become a signifi·
cant factor. If it takes "too long" to do the counting, the

Vs

COP420

G1

22

11

Vee
Vs=+15V
-Vs= -15V
vee= +5V

-4V D: CLRA
ASC
NOP
XIS
JP
BINADD
SKC
• NOW SEE IF. DONE
JP
TIME
,NO COUNTER OVERFLOW. CONTINUE
LEI
0
, DONE. DISABLE INTERRUPT
FIN:
,AT THIS POINT HAVE THE VALUE--CONVERT IT TO DECIMAL OR
'SEND IT OUT OR PROCESS IT FURTHER. WHATEVER IS REQUIRED
,BV THE APPLICATION. ARITHMETIC IS REQUIRED TO CREATE THE
.VOLTAGE VALUE. USUALLY A SIMPLE MULTIPLV
,MAV HAVE TO DOUBLE THE RESULT TO COMPENSATE LOOKING FOR
iONLV 1/2 SECOND IN THIS CASE
JP
MEASUR
.,=X 'OFF
IN'I ~Nl: NOP
IN1U,.,,: LSI

INHII:

2,12

SC
CLRA
ASC'
NOP
XIS
CLRA
ASC
NOP
XIS
CLRA
ASC
NOP
XIS
CLRA
ASC
, NOP

'S~~OA~~R~~~R T~G~~~

FOR(,INTERRUPT
,ADDRESS OFF MUST BE NOP'FOR INTERRUPT
,DO ADD OF THE VALUE FOR FREQ CNT
,STRAIGHT LINE THE CODE FOR pPEED

ADJUST VALUE

IF TIME < 1 SEC
e.g. FOR TIME
= 'I. SEC. DOUBLE
VALUE

X

LEI
RET

2

,ENABLE THE INTERRUPT AGAIN

Figure ,19A. V to F By Counting Pulses

Figure 19B. V 10 F By Counting Pulses

,USE INTERRUPT FOR CATCHING THE PULSE EDGE
V~PI'R:

WAn:

IN1~.Nl:

Cr~lNl

:

PI UtH:

LBI
STII
STII
STII
STII
LBI
LEI
SC
LBI
JP
.=X'OFF
NOP
LSI
SKMBl
JP
5MB
LEI
LBI
SC
CLRA
ASC
NOP
XIS
CLRA,
ASC
NOP
XIS
CLRA
ASC
NOP

0.12

,CLEAR COUNTER SPACE AND FLAG

0
0
0
'0

0.12
2
0.12
WAIT

,NOW ENABLE THE INTERRUPT
,DUMMV WAIT LOOP. WAITING FOR SIGNAL TO
,INTERRUPT THE CONTROLLER
,SET ADDRESS TO OFF--INTERRUPT ENTRV POINT
,REQUIRED FOR INTERRUPT ENTRV

O. 12
0
DONE
0
2
O. 13

i NOW CHECKING TO SEE IF SECOND INTERRUPT

,I.E .• ARE WE DONE?

,SET BIT FOR NEXT INTERRUPT
,ENABLE INTERRUPT AGAIN
,NOW START COUNTING
,STRAIGHT LINE THE CODE FOR SPEED

X

DUNI';

JP
PLUSI
,FINISHED WHEN GET HERE--THE COUNT REPRESENTS THE PERIOD
,WITH ABOVE CODE. THE ACTUAL PERIOD IS THE COUNT MULTIPLIED
,BV IS(THE NUMBER OF WORDS TO INCREMENT BV II PLUS AN OVERHEAD
'OF 9 CYCLE TIMES = 24 CYCLE TIMES. AT 4U5 THIS IS 96 us
,OR A FREQUENCV OF JUST OVER 10KHz. MAX COUNT HERE IS 4095 .
• THIS GIVES A MAXIMUM PERIOD = 61434 CYCLE TIMES(=245, 736ms AT
, 4us). THIS CORRESPONDS TO A FREQUENCV OF JUST OVER 4Hz
,NOTE. THIS IS 12 BIT RESOLUTION

Flg'ure 19C. Alo 0 wllh VF ConverterlVCO By Measuring Period

2·104

components. The circuit may be calibrated by means of
a variable resistance in the Rs term (a gain adjust) and
an offset adjust. The offset adjust is optional but its
inclusion in the circuit will allow maximum accuracy to
be obtained. The standard calibration procedure is to
t"rim· the gain adjust (Rs) until the output frequency is
correct near full scale. Then set the input ot 0.01 or
0.001 of full scale and trim the offset adjust to get FOUT
to be correct at 0.01 or 0.001 of full scale. With that
calibration, the circuit of Figure 20 is accurate to within
±0.03% typical and ±O.14% maximum. The circuit of
Figure 21 attains the spec limit accuracy of ± 0.01 %.

THESE TESTS INSURE SYNCliRONIZATION
- COUNT EXACTLY THE RIGHT PERIOD CATCH THE PULSE EOGE

C. VOLTAGE CONTROLLED OSCILLATORS
(VCO's)
A VCO is simply another form of voltage to frequency
converter. It is an oscillator whose oscillation frequency
is dependant upon the input voltage. Numerous designs
for VCO's exist and the reader should refer to the data
sheets and application notes for various op-amps and
VCO devices. The code in Figure 19 is still applicable if
a VCO is used. The only possible difficulty that might be
encountered is if the relationship between frequency
and input voltage is non-linear. This does not affect the
basic code but would affect the processing to create
the final result. A sample circuit, taken from the data
sheet of the LM358, is shown in Figure 22. The accuracy
of the VCO is the controlling factor.

CAUGHT NEGATIVE GOING EDGE COUNT UNTIL NEXT NEGATIVE GOING EDGE

D. A COMBINED APPROACH

Figure 190. V to F -

Elements of the period measurement and pulse
counting techniques can be combined to produce a
system with the advantages of both schemes and with
few problems. Such a system is only slightly more
complicated in terms of its software implementation
than the approaches mentioned above. Note that in a
microcontroll"r driven system, no additional hardware
beyond the voltage to frequency converter is required to
implement this approach. Basically, the micrccontroller
establishes a viewing window during which time the
microcontroller is both measuring time and counting
pulses. The result can be very precise if two conditions
are met. First, when the microcontroller determines that
it needs the conversion information, the microcontroller
does not begin counting time or pulses until the first
pulse is received from the VFC (first pulse after the
microcontroller "ready"). Note, the COPSTM microcontroller could provide a "start conversion" pulse to
enable the VFC if such an arrangement were desirable.
The time would be counted for a fixed period and the
number of pulses would be counted. After the fixed
period of time the controller would wait for the next
pulse from the VFC and continue to count time until
that pulse is received. The ratio of the total time to the
number of pulse is a very precise result provided that all
the system times are slow enough that the microcontroller can do its job. The speed limits mentioned
previously apply here. It is clear that the total time is not
fixed. It is some basic time period plus some variable
time. This is a little more complicated than simply using
a fixed time, but it allows greater accuracies to be
achieved. Also, the approach takes approximately the
same amount of time for all conversions. It is also faster
than the simple pulse counting scheme.

Measure Period

B. THE LM131/LM231/LM331
The LM131 is a standard product voltage to frequency
converter with a linear relationship between the input
voltage and the resultant frequency. The reader should
refer to the data sheet for the LM131 for further
information on the device itself and precautions that
should be taken when using the device. Figure 20 is the
basic circuit for using the LM131. Figure 21 represents
Improvements that increase the accuracy (by increasing
the linearity) of the result. Note that these circuits have
been taken from the data sheet of the LM131 and the
user is referred there for a further discussion of their
individual characteristics. With the LM131 the frequency output is given by the relationship:
FOUT =(V1N /2.09) (1/RTCr) (Rs/RL)
It is clear from the expression above that the accuracy
of the result depends upon the accuracy of the external
2-105

o
o

"'CJ

Z

o

CD

.....

,...
4mHz

CD

V,

15
a..

Hr

z

oo

6.8k1%

lOOk

VIN
10V

HC

FULL SCALE

CriO.Ol"F

Vee

LM331
1 CURRENT
OUTPUT
6 THRESHOLD

472

lOOk
1%

COP420

10k
FREQ. 3

101

OUTPUT

Hl
Vee
Vee= +5V
Vs= +15V
VIN=D-l0V

• USE STABLE COMPONENTS

Figure 20. Basic LM331 Connection

Vs
6.8k±1%*

H.C 5

r - - -.....---~HEFI

LM331

F~~~ j-:3:........._ _....!.f9 101

COP42D

10k
GAIN
ADJUST

22M

COMP 7

lOUT

IN

Vee

5k"
2.2k

VIN 1DOk±1%-

-10Vo-""'.........--"'I
FULL SCALE

VS=15V TO 5V

-Ys= -15VTO -5V

OFFSET
ADJUST

Yee=5V
VIN=OTO -10V
IN4002
lOOk

·STABLE COMPONENTS SHOULD BE USED

Figure 21. A to D with Precision Voltage to Frequency Converter

O.05J.(F

>~_-,9~IOl
C0P420

Figure 22. A to D with VCO

2-106

(")

VI. Successive Approximation

input voltage. The conversion time for the basic
approach increases with the input voltage. The prefer·
red approach is almost always faster than the basic
approach. The basic approach is faster only for those
voltages near zero where it has only a few increments to
perform.

A. BASIC APPROACH
The successive approximation technique is one of the
more standard approaches in analog to digital conver·
sion. It requires a counter or register (here provided by
the COP420), a digital to analog converter, and a com·
parator. Figure 23 illustrates the basic idea with the
COP420. In the most basic scheme, the counter is reset
to zero and then incremented until the voltage from the
digital to analog converter is equal to the input voltage.
The equality is determined by means of the comparator.
Figure 24 illustrates the flow chart and code for this
most basic approach. The preferred approach is illustra·
ted in Figure 25. This is the standard binary search
method. The counter or register is set at the midpoint
and the "delta" value set at one half the midpoint. The
"delta" value is added or subtracted from the initial
guess depending on the output of the comparator. The
"delta" value is divided by 2 before the next increment
or decrement. The method repeats until the desired
resolution is achieved. While this approach is some·
what more complicated than the basic approach it has
the advantage of always taking the same amount of
time for the conversion regardless of the value of the
LSB

The accuracy of the approach is governed by the
accuracy of the digital to analog converter and the
comparator. Thus, the result can be as accurate as one
desires depending on the choice of those components.
Digital to analog converters of various accuracies are
readily available as standard parts. Their cost is usually
in direct relation to their accuracy. The reader should
refer to the National Semiconductor Data Acquisition
Handbook for some possible candidates for digital to
analog converters. It is not the purpose here to compare
those parts. The COPSTM interface to these parts is
generally straightforward and follows the basic sche·
matics shown in Figure 23. The user should take note
and make sure the input and output ports of the conver·
ter are compatible - in terms of voltages and currents
- with the COPS device. This is generally not a problem
as most of the parts are TTL compatible on input and
output. The precautions and restrictions as to the use of
any given device are governed by that device and are
indicated in the respective data sheets.

Lo
o TO A

11

L3
L4

CoP42o

L5

L~
;/

L6

VOUT

L7

MSB

CLK

IVOUT

L2
DIGITAL TO
ANALOG
CONVERTER

DATA

I
1

L~
0--

so
SK

COP42O
IN

;/

IN

V"o--

Figure 23A. Basic Parallel Implementation

Figure 23B. Basic Serial Implementation

,8 BIT SUCCESSIVE APPROXIMATlON--BASIC SCHEME
,COMPARATOR INPUT TO COP
IN3
,OUTPUTS TO D TO A ARE L7 THRU LO WITH L7
MSB. LO

=

ClINVIH, LBI

INCU:
PI USJ:

mnl'Ul:

STII
STll
LEI
JP
SC
CLRA
LBI
ASC
NOP
XIS
JP
LBI
LD
XDS
CAMG
JSR

2.14

=

~

LSB

,SET THE RESULT VALUE TO ZERO

o
o
4
OUTPUT

,ENABLE THE L PORT AS OUTPUTS
,ROUTINE FOR INCREMENTING THE RESlIL T VALUE

2. 14

PLUSI
2.15

DELAY

,SEND THE RESULT VALUE. STORED IN 2.15-2.14 TO
,G AND THEREBY OUT THROUGH L

,THIS IS ANY CONVENIENT ROUTINE 10 MAKE SURE

jTHAT THE COP DOES NOT TEST THE COMPARATOR UNTIL

ININ
AISC
JP

,THE D TO A CONVERTER HAS HAD ENOUGH TIME TO DO
,THE CONVERSION--THE AMOUNT OF TIME REQUIRED
, IS CLEARLY DEPENDANT UPON THE D TO A CONVERTER
; USED
,NOI; READ THE COMPARATOR INPUT TO COP
B
,COULD SAVE A WORD IF USE G LINE AS INPUT
I N C R , INPUT VOLTAGE STILL) CONVERTED ANALOG VOLTACE

,CONVERSION DONE AT THIS POINT--THE COMPARATOR HAS CHANGED STATE
,HENCE. CONVERTED ANALOG VOLTAGE> INPUT VOLTAGE-'SO STOP

Figure 24A. Code for Basic Approach of Successive Approximation

2·107

o""C

Z

o

CD

...i.

or"

CD

'0
z
a..

o

U

Figure 24B. Basic Approach, Successive Approximation

; 8 BIT BINARY SEARCH SUCCESSIVE APPROXIMATION
; INPUT TO COP IS IN:], L BUS IS OUTPUT TO D TO A, L7=MSB, LO=LSB
; COMPARATOR=O WHEN D TD A VOLTAGE> VIN, OTHERWISE = I

B1N:iI-tH:

LBI

3,14

STII
STII
LBI
STII
STII
LEI
LBI
CLRA
AISC
mnl'lJl:

DIVl))[c:
DIVA:

[))Vl:

DJV2:

DIV::-t:

TEST:

D~CIl:

SUB:

INCR:
ADD:

BllPI I:

X

LD
XDS
CAMG
LBI
LD
AISC
JP
STII
JP
AISC

o

; SET INCREMENT = MAX VALUE/2 (WILL BECOME
;MAX VALUE/4 BEFORE FIRST USEI

B

2,14

; SET INITIAL VALUE OF RESULT TO MAX VALUE/2

8
4
1,15

; ENABLE THE L BUS AS OUTPUTS
; NOW SET UP THE BIT COUNTER-OVERFLOW WHEN 8 BITS

9
3

; DO IT THIS WAY FOR COMPATIBILITY WITH INCREMENT
; SAVE THE BIT COUNTER VALUE AND POINT TO RESULT

3,15

; DIVIDE THE INCREMENT VALUE" BY 2, CAN DE DONE
; IN SEVERAL WAYS SINCE THIS IS A VERY SPECIAL
;PURPOSE DIVIDE FUNCTION
; ALSO, DO THE DIVIDE HERE TO GIVE THE D TO A TIME
;TO DO THE DIGITAL TO ANALOGcCONVERSION

o

; SEND THE RESULT TO G AND HENCE TO L

8
DIVI
4
TEST
4
JP
DIV2
STII
2
JP
TEST
AISC
2
JP
DIV3
STII
1
JP
TEST
l.BI
3,14
AISC
I
JP
DIVA
STII
B
STII
0
; DEPENDING ON THE D TO A USED, MAY NEED MORE DELAY HERE
; MUST BE SURE THE RESULT IS STEADY BEFORE TEST THE COMPARATOR
LBI
3,14
ININ
; COULD SAVE A WORD IF USED G LINE AS INPUT
AISC
8
JP
INCR
SC
; INPUT LESS THAN D TO A CONVERTED VOLTAGE
; SUBTRACT THE INCREMENT VALUE FROM RESULT
LD
CASC
NOP
XIS
1
JP
SUB
JP
BITPLl
; INPUT> 0 TO A CONVERTED VOLTAGE
RC
; ADD THE INCREMENT VALUE TO RESULT VALUE
LD
ASC
NOP
XIS
I
JP
ADD
1,15
;NOW INCREMENT BIT COUNTER TO SEE IF DONE
LBI
LD
AISC
JP
OUTPUT
; CONVERSION DONE AT THIS POINT

Figure 25A. Binary Search Successive Approximation Code

2-108

OUTPUT ReSULT

TODTOA
INCR/Z
-INCR

Figure 25B. Binary Search Successive
Approximation Flow Chart

B. SOME COMMENTS ON RESISTOR LADDERS
If the user does not wish to use one of the standard
digital to analog converters, he can always build one of
his. own. One of the most standard methods of doing so
is to use a resistor ladder network of some form. Figure
26 illustrates the basic forms of binary ladders for
digital to analog converters. The figures also show the
transition from the basic binary weighted ladder in
Figure 26A to the standard R·2R ladder Figure 26C.
Consider Figure 26A. The choice of the terminating
resistor is made by hypothesizing that the ladder were
to go on ad infinitum. It can then be shown that the
equivalent resistance at point X in that figure would be
equal to 128R, the same value as the resistor to the
least significant bit output. This fact is used to create
the intermediate ladder of Figure 26B. This step is done
because it is usually undesirable to have to find the
multitude of resistor values required in the basic binary
ladder. Thus, the modification in Figure 26B signifi·
cantly reduces the number of resistor values required.
As stated earlier, the resistance looking down the
ladder at point X in Figure 2 is equal to the resistor
connected to the binary output at that pOint; here the
value is 2R. Remembering the objective is to minimize
the number of different values required, if we simply use
the same R·2R arrangement as before with a termination of 2R we get an effective resistance at pOint Y of
Figure 26B or 0.5R. This means that a serial resistance
of 1.5R is required to maintain the integrity of the
ladder. If we carry this on through 8 bits, the circuit of

Figure 26B results. From this it is only a small step to
create the standard R·2R network. The analysis is the
same as done previously.
There is absolutely no restriction that the ladders must
be binary. A ladder for any type of code can be
constructed with the same techniques. Ladders
comparable to Figures 26A and 26B are shown in Figure
27 for a standard 8421 BCD code. With the BCD code,
the input must be considered in groups of digits with
four bits creating one digit. This is the direct analog of 1
binary digit per input. We need four inputs to create one
decimal digit. Thus the resistor values in each decimal
digit are 10 times the values in the previous decimal
digit just as the resistor value for each successive
binary digit was twice the value for the preceding binary
digit. Note that this analysiS can be easily extended to
any code. The termination resistance is calculated in
the same manner assume the decimal digit
groupings extend out to infinity. It can be shown that
the resistance of the ladder at point X in Figure 27 A is
4BOR. Thus Figure 27A represents the basic B421 BCD
ladder for three digit BCD number. This termination
resistance will vary with where it is placed. Basically
this resistance is equal to nine times (for a decimal
ladder) the parallel resistance of the last digit
implemented.
(This
relation
can
be
shown
mathematically if one desires, the multiplier is a
function of the type of ladder used - multiplier = 1 for
binary systems, 9 for decimal systems, etc.) Thus the
termination resistance would be 48R if the network
were terminated after the 2nd digit and 4.BR if the

2R

27
2R
26

4R
25
BR
24
16R
23
32R
22
64R
21
12BR
2°
12BR

-=-

A

(")

o"'tJ

Z

o

CD

.....

,...
CI)

'6
z
D..

oo

network were terminated after the 1st digit
implemented. In Figure 278 we are attempting to use
only the resistor values for one decimal digit. This
means that the last terminating resistor must be a 4.8R
by the analysis above. Thus at point X in Figure 278 we
must have an equivalent of resistance of 4.8R. The
equivalent resistance at point Yof Figure 278, looking
down from the ladder, is 0.48R. Thus the other series
resistance must be 4.32R (4.8R - O.48R). Thus the
network of Figure 278 res'ults.

difficulties and complexities caused by the fact that the
analog to digital conversion is being performed on a
voltage source that changes nonlinearly, for example, a
thermistor. temperature probe. 8y using the properly
designed ladder network,. the nonlinearity can effectively be eliminated from consideration in the code
implementation of the analog to digital conversion.
The accuracy of ladders is a direct function of the
accuracy of the resistors and the accuracy of the
voltage source inputs. This is obvious since the analog
voltage is in fact created by means of equivalent
voltage dividers created when the various inputs are on
or off. It is also essential that the ladder sources be the
precise same value at all inputs to the ladder network. if
this is not the case, errors will be introduced. In
addition, the output impedance of the voltage source
should be as small as possible. The success of the
ladder scheme depends on the ratios of the resistance
values. Inaccuracies are introduced if those ratios are
disturbed. Some possible implementations of the
successive approximation approach with a ladder
network used for the digital to analog conversion are

Generally, ladders can be very effective tools when
understood and used properly. They can be significantly
more involved than indicated here. There are a number
of texts and articles that cover the subject very nicely
and the reader is referred to them If more information on
ladder design, the use of ladders, and advanced
techniques with ladders is desired.
One final note is of some interest. The ladders may be
readily constructed for any type of code to create the
analog voltage. Note that there is no restriction that the
code, or the ladder network, be linear. Thus, effective
use of ladder networks may significantly reduce system

MOST

""""'"''

r

DECIMAL
DIGIT·

.

2R

""

4R

MOST
SIGNIFICANT

DEC~~~~

2

{'

Your
2R

4

4R

2

BR

8R

1

4.32R
lOR

. {:

""

DECIMAL
DIGIT

20R
SECOND
OECIMAL
DIGIT

40R

2

BOR
1

{'

2R
4R
BR
X
4.32R

100R
LEAST
SIGNIFICANT
DECIMAL (BCD)
DIGIT

{'

200R

4

LEAST
SIGNIFICANT

400R

DEC~~G~~

2
BOOR

1

X

{'

2R

4

4R

2
BR

480R

4.BR

-=-

-=B

A

Figure 27. 8421 BCD Ladders

2-110

indicated in Figure 28. Note that these are functional
diagrams. Feedback or hysteresis for comparator
stabilization are not shown. The reader should be aware
that his particular application may require that these
factors be considered. Figure 28A is the simplest
scheme and also the least accurate. With I itlle or no
load, the high output level of the L buffer should be very
close to Vcc and the low level close to ground. Also the
output impedance of the buffers must be considered.
Therefore, rather large resistor values are used - both
to keep the load very small and to dwarf the effect of the

output impedance. With the configuration in Figure
28A, four bit accuracy is about the best that can be
aChieved. By being extremely careful and using
measured values, an additional bit of accuracy may be
obtained but care must be used. However, the
schematic of Figure 28A is very simple. Figure 28B
represents the next step of improvement. Here we have
placed CMOS buffers in the network. This eliminates
the output impedance and reduces the level problems
of the circuit of Figure 28A. The CMOS buffer will swing
rail to rail, or nearly so. The accuracy of Vcc and the
27

L7

L3

2'

L2

2'

L1

2'
2'

LD

R·2R
LADDER

(s~tF)8°~4)

CDP42D

L6

2'

L5

2'

L4

2'

n·2R
LADDER

L3

2'

Is~tF)8D~4)

L2

2'

L2

2'

L1

2'

IN3
YIN

YIN

A

B

YIN

IN3

Your

27
L7

2'
L6

2'

L5

2'
L4

R·2R
LADDER
R=10Dk
(SEE FIG. 24)

CDP420
2'
L3

2'
L2

2'

L1

L-______~L~D_r--~ !-+-.:...j._-!2'

c
Figure 28. Interfaces to Ladder Networks

2-111

o

o

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Z

o
..,
(I),

.....

,...

CD

o
z
a.
G)
o

resistor network is then controlling. Using 1% resistors
and holding Vcc constant, the user should be able to
achieve 7 to 8 bit accuracy without much difficulty.
Remember, however, that Vee is one of the controlling
factors. If Vee is ±5%, there is no point in using 1 %
resistors since the Vee tolerance swamps their effect;
Figure 28C is .the final and most accurate approach.
Naturally enough, it is the mo~t expensive. However,
one can get as accurate as one desires. Here, an
accurate reference is required. That reference is
switched into the network by means of the analog
switch. Alternately, ground may be connected to the
input. Now the user need only consider the accuracy of
the reference and the accuracy of the resistors.
However, the on impedance of the switches must be
considered. It is necessary to make this on impedance
as low as possible so as not to alter the effective
resistor values.

niques are generally applicable to other A to D converters not mentioned here and the user should not have
difficulty in applying these principles to other devices. It
should be pOinted out that in almost every instance, the
choice of COP420 inputs and outputs is arbitrary. Obviously, when there is an 8-bit bus it is natural, and most
effiCient, to use the L port to interface to the bus.
Gen·erally, the G lines have been used as outputs rather
than the D lines simply because the G lines are, in many
instances, somewhat easier to control. The choice of
input line is also free. If the interrupt is not otherwise
being used, it may be possible to utilize this feature of
IN1 for reading a return signal from the converter. However, this is by no means required. If there is a serial
- interface it is clearly more efficient to use the serial port
of the COP420 as the interface. If a clock is required, SK
is the natural choice.

B_ ADC0800 INTERFACE

VII. "Offboard" Techniques

The ADC0800 is an 8-bit analog to digital converter with
an 8-bit parallel output port with complementary
outputs. The ADC0800 requires a clock and a start
convert pulse. It generates an end of conversion signal.
There is an output enable which turns the outputs on in
order to read the 8-bit result.

A. GENERAL COMMENTS
This section is devoted to a few illustrations of
interfacing the COP420 to standard, stand alone analog
to digital converters. These standard converters are
used as peripherals to the COPSTM device. Whenever
the microcontroller requires it new reading of some
analog voltage, it simply initiates a read of the peripheral
analog to digital converter. As a result, the accuracies
and restrictions in using the converters are governed by
those devices and not by the COPS device. These tech-

The reader is referred to the data sheet for the ADC0800
for more information on the device. The circuit of Figure
29 illustrates the basic implementation of a system with
the ADC0800. The interface to the COP420 is straightforward. The appropriate timing restrictions on the
control signals are easily met by the microcontroller.

Vee

+

4.7~F*

FULL SCALE
ADJUST

10
Vss

LSB

ADC0800
(MM4357)

7.5k

13
14

15 RNET
TOP

16

13 L2

17

12 L3

1

8 L4

2

7 L5
6
L6

5 RNET
BOTTOM

-VG
ADJUST ZERO
WITH VIN =
ADJUST FULL
WITH YiN =

ADJUST
-5V
SCALE
+5V

Vee = +5V
-VG = -12V
VIN= -5 TO +5V

VIN

15 CKO
LO
14 L1

5 L7

MSB 4
OUT 7
ENABLE 6
START

23 G2
22
G1

EOC 9
11

18 SK

Voo CLOCK

COP420

9 IN1
GND

Vee
-VG

Figure 29. Simple AID with ADcoaoo

2-112

Figure 30 is the flow chart and code required to do the
interfacing. As can be seen, the overhead in the COP420
device is very small. The choice of inputs and outputs is
arbitrary. The only pin that is more or less restricted is
the use of SK as the clock for the converter. SK is
clearly the output to use for that function as, when
properly enabled, it provides pulses at the instruction
cycle rate.

interface and is generally a very useful offboard
converter: The interface is not significantly different
from that of the ADC0800, but the Naked·8 Is a much
better device. The four control signals are somewhat
different, although there are still four control lines. Here
we have a chip select, a read, a write, and an interrupt
signal. All are negative going signals. Start conversion
is the anding of chip select and write. Output enable is
the anding of chip select and read. The interrupt output
is an end convert signal of sorts. The device may be
clocked externally or an RC may be connected to it and
it will generate its own clock for the conversion. In
addition the device has differential inputs which allow

C. NAKED·a™ INTERFACE
The Naked·8 family of analog to digital converters
(ADC0801, ADC0802, ADC0803, ADC0804) is very easy to

, FLOAT THE L LINES
MFA!lUR: LEI
a
SC
,MAKE SURE SO STAYS ZERO
SlAln~': CLRA
,MAKE SURE SK STAYS CLOCK
XAS
, SEND START PULSE
OGI
2
OGI
0
LOI
2.13
R~.Allll:
ININ
,WAIT FOR EOC SIGNAL
AISC
14
JP
READI1
,HAVE EOC.ENAOLE OUTPUTS
OGI
4
,READ THE L LINES
INL
X
COMP
,CREATE PROPER POLARITY
XDS
COMP
X
OGI
,DISABLE ADCOBOO OUTPUT
0
,HAVE THE RESULT AT THIS POINT--USE IT IN WHATEVER
, MANNER IS REGUIRED BY THE APPLICATION
LBI
2. 10
JSRP
CLRR
JP
MEASUR
Figure 30A. A to D with ADC0800

Figure 308. ADC0800 Interface Flow

2·113

o

o"'0
Z

9.
CD
.....

~

CD

z'0
c..
o
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the COP420. Again, the interface is simple and straightforward. The code required to interface to the device is
minimal.. Figure 32 illustrates the flow chart and code
required to do the interface.
.

the 8-blt conversion to be performed over a given
window or rangtl of input voltages. The reader should
refer to the Naked-8™ data sheet for more information.
Figure 31 indicates a basic .interface of the Naked-B to

1_
CS
2 Rii'
3 Wii

Gl
G2

5

IN3
l7 5
l6 6
7
l5
8
l4
12
l3
13
l2
14
II
15
lO

COP420

Vee

20

Veel =VREF)

~

INTR
VREF/2

11

DB7
12 DB6

ADC0801
ADC0802
ADC0803
ADC0804

13 DB5

VREF/2

VIN+

VIN+ }
V
IN-

VIN-

14 084
15 DB3

ClK R

16 082

DIFFERENTIAL
INPUT

19
10k

17 081
lB 080
AGNO

r

150pF

Vee

Figure 31. COP420 - Naked·8 Interlace

,INTERFACE TO NAKED BCTM)
NAKI-I>B: OG I
LOUt':

LOIJI'~':

RI-Al):

15

LEI
OGI

o

OGI
OGI
OGI
ININ
AISC

10

B

-JP
-JP

READ
LOOP2

LSI
OGI
OGI
NOP

0,0

INL
OGI

14
14
15

14
12

15

,SET ALL GLINES HIGH I:
ClIMf';':

Arse
JP
se,
LBI
CLRA

5

; NOW TEST TO SEE IF IS MINUS
;ACCUMULAToR IS ZERO PRIOR TO THIS EXCHANGE
; TEST FOR THE MINUS CODE

ADD273
2. 13

; IS MINUS. TAKE TENS COMPLEMENT OF NUMBER
; ALSO. ZERO IS IN MINUS POSITION

COMP2
1.13

; NOW SET UP TO ADD 273 TO THE RESULT

x

CASC
. ADT
XIS
JP
Alm;a:<: LBI
STU
STU
STU

3

7
2

. Figure 34A. MM5407/COP420 AID Interface Code

2-116

RC
LIII
1. 13
A11l>l P:
LD
3
AISC
6
ASC
ADT
XIS
3
dP
ADDLf'
; 1·1 NI ~,IIED AT THIS POINT.
RET
. PAGE
2
CI (I(:KJ: CLRA
OGI
o
JP
CLK
CI 1I(;1~;': OGI
2
CLRA
CI K:
AISC
3
dP
. -1
4
AISC
,)P

. -1

OGI
NOP
NOP
NOP
NOP
ININ
AISC
RET
RETSK

3

o
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Z

DO ANY REGUIRED SCALING. ETC.

HERE

; THE REGUIRED SUBROUTINES HERE
; SEND CLOCK AND START SIGNAL LmJ
; SEND CLOCK ONLY LOW
; MAKING SIMPLE TIMING LOOP-HERE ADJUSTINO FOf,
; TOTAL PERIOD: 100u5(25 CYCLE THIES AT 4us
; INSTRUCTION CYCLE TIME)--HERE USING 13 CYCl.E
; TIMES ON. 12 CYCLE TIMES OFF
;SE1 CLOCK BACK HIGH
; THESE NOP's FOR TIMING ONLY

; READ THE INPUT LINE(I3)
8

Figure 34A. MM5407/COP420 AID Interface Code, conl'd

SEND CLOCKS
TO DO CONVERSION
RESET
STORAGE
MEMORY
SEND START
PULSE

i.e. START TO
TRANSMIT

SEND 4
CLOCKS

r----------.I~
SENO
CLOCK
READ BIT
AND STORE

Figure 348. MM5407 as AID Converter Flow Chart

2-117

2CD
.....

,...
Q)

'0
z

c..

o
()

VIII. Conclusion

circuits must be taken. These are described in the
National Semiconductor Linear Applications Handbook
and in the data sheets for the various I inear devices.
These precautions are especially significant when
greater accuracy is desired.

Several analog to digital techniques using the COPSTM
family have been presented. These are by no means the
only techniques possible. The user is limited only by his'
imagination and whatever parts he can find. The COPS
family of parts is extemely versatile and can readily be
used to perform the analog to digital conversion in
almost any method. Generally, those techniques where
the COPS device is dOing the counting or timekeeping
are slow. However, those techniques are generally slow
inherently. The fastest methods 'are those where the
conversion is being done offboard and the COPS device
is merely reading the result of the conversion when
required. Also, an attempt has been made to illustrate
the lower co'st techniques of analog to digital conversion. This, by itself, restricts most of the techniques
described to about 8-bits accuracy. As was mentioned
several times, the greater the accuracy that is desired
the more accurate the external circuits must be. Ten
and twelve-bit accuracies, and more, require references
that are accurate. These get very expensive very rapidly.
There is nothing inherent in the COPS devices that prevents them from being used in accurate systems. The
precautions are to be taken in the system regardless of
the microcontroller. The only problem is that, in those
accurate systems where the COPS device is doing the
timekeeping and counting, this increased accuracy is
paid for by increased time to perform the conversion.

The COPS family of microcontrollers has shown itself
to be very versatile and powerful when used to perform
analog to digital conversions. Most techniques are code
efficient and the microcontroller itself is almost never
the limiting factor. It is hoped that this document will
provide some guidance when it is necessary to perform
analog to digital conversion in a COPS system.

IX. References
1. "Digital Voltmeters and the MM5330", National
Semiconductor Application Note AN-155.
2. Walker, Monty, "Exploit. Ladder Network Design
PotentiaL" Part One of two part article on ladder
networks. Magazine and date unknown.
3. Wyland, David C., "VFC's give your ADC design high
resolution and wide range." EDN, Feb. 5, 1978.
4. Redfern, Thomas P., "Pulse Modulation AID Converter" Society of Automotive Engineers Congress and
Exposition Technical paper # 780435, March 1978.
5. National Semiconductor Linear Applications Handbook, 1978.

Several devices have been used in conjunction with the
COPS device in the previous sections. It is again
recommended that the user refer to the specific data
sheets of those devices when using any of those
circuits. It must again be mentioned that the standard
precautions when dealing with analog Signals and

6. National Semiconductor linear Databook, 1980.
7. National Semiconductor Data Acquisition Handbook,
1978.

2-118

COPS™ Television Controller

National Semiconductor
COP Note 2
Brett K. Nelson
May 1980

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Cii"

Introduction
As part of National Semiconductor's continuing effort to
define and implement a full spectrum of COPS Television
Controllers (CTCs), this document will describe progress
made in programming a COP420 to serve as a prototype
'low-end' CTC. Used in conjunction with an MM5439
Phase Locked Loop (PLL) and an MM5450 display driver,
this processor allows a television receiver to have the
following functions:

::I

§.
CD
'"'I

The MM5439 PLL is of next importance in the prototype
system. Originally designed for the European Micropro·
cessor Television Controller (MTC) market, the 5439 of·
fers capabilities found in traditional PLL circuits as well
as general purpose input and output pins and 6 pulse·
width modulation OfA converters. This allows the COP420
to use it to band-switch the UHF and VHF tuners in addition to providing analog outputs for controlling television
parameters such as volume, brightness, and color. The
MM5439 operates with a 14·bit code and is capable of
resolving the RF spectrum into 64kHz steps; more than
adequate for U.S. Television receivers.

1. Frequency Synthesis Tuning
2. Keyboard Scan and Decode
3. MM53126 Format Serial Decode
4. 64 Level Analog Outputs
5.
6.
7.
8.

system and provides the processing power to scan the
keyboard, decode the serial input, run the channel dis·
play, and control the PLL. System capabilities may be en·
hanced or scaled·down for different markets simply by
changing the processor's algorithms. This flexibility
combined with low-cost makes the COPS family, and in
particular the COP420, a standout in the field of high·
volume, low·to·medium range television controllers.

o·
::::s
n
o

Direct Channel Entry
Channel and Fine Tune Slewing
Analog Output Slewing
LED Channel Display

9. Last Channel Memory

System Overview
Shown in Figure 1, the heart of the CTC prototype hardware is the COP420 itself. This particular member of National's COPS family of 4·bit microcontrollers has 1024
bytes of program memory, 64 digits of scratch'pad RAM,
24 input and output pins, and an efficient 49-member instruction set. It is the workhorse of the television tuning

The serial input of Figure 1 is generated by using an
MM53126 infrared remote control circuit. The MM53126
scans and decodes a key closure and provides serial
data to drive infrared transmitter diodes. At the receiving
end, the infrared signal must be detected and amplified
to provide a digital signal for the COP420. The COPS de·
vice provides the intelligence to receive the serial data

~

ERIAl ...____~

INPUT

,..-----.,'------'" ANALOG
OUTPUTS
TO TUNER
INTERFACE

~

'If

COP

420

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Figure 1.

eTe

Block Diagram

2-119

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and to route program control just as if the key entry originated from the main keyboard.
.

c..

The third circuit shown in Figure 1 is the MM5450
display driver. The 5450 is a direct drive, serial input,
35-segment lED driver. Due to its serial nature, it is best
interfaced to the COPS' serial output port. The 5450 is
gaining popularity because of its low-cost, adjustable
high-current outputs, and low-noise non-multiplexed
display format. Its sole duty in the system is to display
the current channel number.

z

o
o

tor integrator that requires a current source from within
the receiver chassis. UHFfVHF band-switching is accomplished by using 3 general purpose open-collector outputs to drive dual transistor 24 volt buffers. The one transistor 4.0 MHz crystal oscillator also shown provides the
stable reference needed by the PlL. In addition, it is used
to generate a 4-microsecond instruction cycle within the
COP420. This speed is necessary to insure that pulseposition-modulated (PPM) signals coming from the
MM53126 are properly decoded.
The MM5439 and UHFIVHF tuner interface shown in Figure 2 is somewhat more complicated. By comparing the
UHFIVHF local oscillator to the 4 MHz system clock, the
5439 generates two negative-going Signals that are
designed to raise or lower the varactor tuning voltage,
and thus close the frequency synthesis loop. To accomplish this an lF351 is configured as a differential integrator to generate the tuning voltage. The single-pole filter
on the output is to minimize transients. The Pll NMOS
circuitry in the 5439 is not fast enough to handle the
tuner local oscillator directly, so two counters are used
to divide this frequency down. The SDA2001 ECl prescaler divides the frequency first by 64, and then the
74lS169 alternately divides by 15 or 16 under 5439
control.

Hardware Description
Utilizing the MM5439as the system Plldictated the basic
structure of much of the prototype circuitry. The MTC
series of components were designed to be MICROBUSTM
compatible. That is, they were designed to connect to an
a-bit bi-directional data bus, address lines, and control
strobes. The COPSTM family of processors does not possess a traditional bus structure, and to interface to a
parallel bus device such as an MM5439 requires that
COPS inputs and outputs emulate the data, address, and
control bus functions. Figure 2 illustrates the use of the
COPS l pins as the data bus, the G port for addressing,
SK as a read strobe, SO as a write strobe, and DO as
chip select.
Figure 2 also details the 5439 D/A, band-switching, and
oscillator circuitry. The D/A interface is a simple capaci-

+24V

10kPU

RfIN~RF

..l. I.

ALL NPN TRANSISTORS PROCESS 23

UHF/VHF
TUNER

ALl'PNP TRANSISTORS PROCESS 62
EXCEPTDI .

AGe

~~i~~~~~~~~~~CER~~~:~DS

IF OUT

1

BRT

4

COL 1

IF
.OUT

Vee

TUNING
VOLTAGE

BUFFERED SIGNAL
FROM MM53126

VOL

"::"
~AGC

RESISTORS IN OHMS

VHF

UHF

'"
10k

KEEP LEADS

TO AND FROM
PRESCALER AS
SHOAT AS

B

9

10 'N2

POSSIBLE

+FT,-+''-t''-1r--~2.,O IN3

DECOUPLE
All SUPPLIES

~~

0.001

KEYBOARD

O.15pf

FROM
10

ANALOG
OUTPUTS

TO RECEIVER
CHASSIS

Figure 2. Low·End eTC Schematic

2-120

5439
PIN 7

(')

o

Software Description
The major features of the software written for this lowend CTC implementation are described in the flowchart
of Figure 3_ Readily observable items of interest are the
initialization, serial-input, delay, and instruction decode
portions of the program_ The function blocks comprising
the PLL code calculations, serial processing, and display
routines are less noticeable, but worthy of additional
mention. They will now be summarized.

binary code is calculated from current BCD channel
number using the following equation:
PLL CODE

Z

9(I)
I\,)

The variable marked BIAS is necessary because there
are gaps between channel groups in the American tele·
vision RF spectrum. BIAS will have different values for
the channel ranges 2·4, 5-6, 7-13, and 14-83.

To successfully tune the television receiver a 14-bit
code must be presented to the MM5439 PLL. This 14-bit

(

=CHANNEL NUMBER' 6 MHz + BIAS

"C

POWER-OIl)

YES

f';\INSTRUCTION
\.:../ DECODE

NO

INSTIlUCTION
DECODE

Figure 3. eTC Major Program Flow

2-121

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a..

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(.)

NO

t:\CHECK
\!:J
KEYBOARD

Figure 3. eTC Major Program Flow (cont'd)

2-122

o

The most time critical software operation encountered
was processing the remote serial input stream. Speed
considerations necessitated that this routine be broken
into 'two portions, reading and decoding. Reading the
stream required that the time between each pulse in the
14·bit code (counting start and stop bits) be saved in a
unique memory location. Figures 4 and 5 illustrate the
pulse timing and serial format. Only after all 14 bits
were received could the timing be analyzed for validity
and converted into a parallel code. Because the MM53126
generates a continuous stream of pulse packages during
key depression, a form of debouncing was also needed
on the input so only the first packet was decoded as an
instruction.

particular positions in memory. Table 1 breaks down the
program data structures and lists the number of 4-bit
digits needed for each. RAM efficiency for this program
was 39/64 or approximately 60 percent.
Table 1. CTC RAM Allocation

Data Description
PLL Code and band data
Display and PLL word area
Remote input buffer
Remote command buffer

~ 200"'-1
1~1-2T
I-lollS

~

Digits
Used
5
5
13
3

DIA mirror values

6

Current channel

2

Channel storage

2

Flags

2

Key decoding

2

Misc.

2

Total

39

Table 2. CTC ROM Allocation

LSB

MSB LSB

MSB

AO A1 A2 A300D1 02 03 0405
1111111 I II
3T 1+11 11 11 1+1 111 11 lei

1 l
PRE·
PULSE

l_AooREss_l_coNTRoL_1
BITS
BITS

START

Routine Description

3T

Bytes
Used

Initialization

50

1

PLL code calculation

80

1

Increment, decrement, PLL 1/0
Remote input

STOP

Remote input decoder
Keyboard

Figure 5. Format of Remote Control Signal 0111001110

MM5450 display

The keyboard routine scans the key contacts by sweeping a logic low through the column outputs and checking
for a resulting low on the row inputs. Once a key closure
is sensed,it is converted into a unique 1 of 16 code and
acted upon. It must then be released 64 milliseconds
before a new key may be processed.
The last major routine shown only as a function block in
the flowchart is the MM5450 display interface routine.
In preparation to passing segment data to the 5450, the
COP420 must first convert each digit of the channel number into its seven-segment display equivalent and place
that information in a buffer. The final part of the display
routine is simply serializing that buffer along with a start
bit to the MM5450_
As previously stated, the COP420 has 64 digits of scratchpad RAM. Well designed data structures within this RAM
will optimize overall program efficiency., With this in
mind, the CTC structures were defined and assigned to

130
80
20
100
50

7-segment look-up table

10

Channel check

20

Slew control

40

PLL fine tune

20

Instruction decoding and main loop

180

Total

780

Conclusions
A COP420 has been shown to be ideal in performing the
functions of a low-end television controller. Manufacturers integrating COPS devices into their television receiver
designs would benefit from cost and capability advantages. Due to the fact that ROM and RAM are under utilized in the software described, it would be logical and
cost-effective from a product viewpoint to expand the
low-end concept and take full advantage of the COP420
by incorporating mid-range features into the controller
software. Conversely, a lesser member of the COPS
family could perform a subset of the functions presented in more cost-driven applications.

2-.123

Z

9CD
I\)

Listed in Table 2 are the major routines in the low-end
CTC program and their respective ROM usage. ROM efficiency in this case would be 780/1024 or 76 percent.

Figure 4. Pulse· Position· Modulation (PPM) Timing

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~

SIO Input/Output Register
Description

National Semiconductor
COP Brief 1
May 1980

Contents

Software Debug of Serial Register Functions

• Logical Operation

In order to understand the method of software debug
when dealing with the SIO register, one must first
become familiar with the method in which the COPS
Product Development System (PDS) BREAKPOINT and
TRACE operations are carried out. Once these 'operations are explained, the difficulties which could arise
when interrogating the status of the SIO register should
become apparent.

• Software Debug
• Serial Out During Breakpoint

:::s

• Serial Out During Trace
• Binary Counter During Breakpoint

:::s

• General
• Using SIO as temporary storage

:::s

COP400 Serial SIO Register

c

The general operation of the SIO port is treated in the
COP400 data sheet. A more detailed look at the internal
circuitry, as well as software debug, will be presented in
this brief.

c.

Q

c.

o

en

Serial Out During BREAKPOINT

Logical Operation
It is important to examine the logical diagram of the SIO
and SK circuitry to fully understand the operation of
this 1/0 port. The output at SK is a function of SYNC,
ENo, CARRY, and the XAS instruction.
If CARRY had been set and propogated to the SKL latch
by the execution of an XAS instruction, SYNC is enabled to SK and can only be overridden by ENo. Trouble
could arise if the user changes the state of ENo without
paying close attention to the state of the latch in the SK
circuit.
If the latch was set to a logical high and the SIO register
enabled as a binary counter, SK is driven high. From this
state, if the SIO register is enabled as a serial shift
register, SK will output the SYNC pulse immediately,
without any intervening XAS instruction.

When the PDS BREAKPOINTs, the COPS user program
execution is stopped and execution of a monitor-type
program, within the COP device is started. At no time
does the COP part "idle". The monitor program loads
the development system with the information contained
in the COP registers.
Note also that single-step is simply a BREAKPOINT on
every instruction.
If the COP chip is BREAKPOINTed while a serial function
is in progress, the contents of the SIO register will be
destroyed. By the time the monitor program dumps the
SIO register to the PDS, the contents of the SIO register
will have been written over by clocking in SI. To inspect
the SIO register using BREAKPOINT an XAS must be
executed prior to BREAKPOINT, therefore the SIO register will be saved in the accumulator.
An even more severe consequence is that the monitor
program executes an XAS instruction to get the contents
of the SIO register to the PDS. Therefore the SK Latch is
dependent on the state of the CARRY prior to the BREAKPOINT. In order to guarrantee the integrity of the SIO
register one must carefully choose the position of the
BREAKPOINT address.
As can be seen, it is impossible to single'step or BREAKPOINT through a serial operation in the SIO register.

Serial Out During TRACE
SYNCOR
ENo-

rANO

CARRY-

....

-

lATCH
ClK

-SKOUTPUT

-

xis

CD
"C

Binary Counter During BREAKPOINT

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In the TRACE mode, the user's program execution is
never stopped. This mode is a real-time description of
the program counter and the external event lines, therefore the four external event lines can be used as logic
analyzers to monitor the state of any input or output on
the COPS device. The external event lines must be tied
to the 1/0 which is to be monitored. The state of these 1/0
(External Event lines) is displayed along with the TRACE
information. The safest way to monitor the real-time
state of SO is to use the TRACE function in conjunction
with the External Event lines .

Logical Diagram of SK Circuit

Since the COPS chip is executing a Monitor Program
during BREAKPOINT the SIO register is still active. In
the Binary Counter mode SIO register will decrement on
every negative transition of the Slline providing the pulse

2-124

Temporary Storage
stays low for at least two instruction cycles. However, if
the pulse on SI occurs when the monitor is interrogating
the SIO register, an erroneous situation may occur.

General
During a BREAKPOINT operation data is transmitted to
the PDS over the SKIP output on the COP402.
Notice that the D register is not contained in the AutoPrint options. The reason for this is that the· contents of
D cannot be read via COP software. These may be monitored by the External Event lines in the trace mode.

It is sometimes desirable to temporarily store the value
of the accumulator. This can be done by designating a
RAM digit and dOing an exchange operation. If the user
can assure that the SIO register is in the binary counter
·mode and that SI is at a constant state, the SIO register
may be used as a temporary storage location. This is
advantagious because the storage and retrieval is accomplished by the single byte XAS instruction and does
not require the use of a RAM digit. The use of the SIO
register as a binary counter is not available on the
COP420C (CMOS version of the COP420), for this reason
the SIO register may not be used as temporary storage.

2-125

o

o"tJ
OJ

::::!.

CD

.....

§

c..

Easy Logarithms for COP400

National Semiconductor
COP Brief 2
May 1980

Logarithms have long been a' convenient tool for the sim·
plification of multiplication, division, and root extrac·
tion. Many assembly language' programmers avoid the
use of logarithms because of supposed complexity in
their application to binary computers. Logarithms con·
jure up visions of. time consuming iterations during the
solution of a long series. The problem is far simpler
than imagined and its sol ution yields, for the applica'
tions programmer, the classical benefits of logarithms:

In figure 1 some pOints. on the logarithmic curve are
identified and evaluated to the base2. Notice that the
characteristic in each case represents the highest even
power of 2 contained in thevalue of X. This is readily
seen when binary notation is used.

oo

...o

en

E

s:.

"C

as

.9
~
en
as

w

X10

3

0 0 0

4

0 0

8

0

10

0

1) Multiplication tan be performed by a single addition.

2) Division can be performed by a single subtraction:
3) Raising a number to a power involves a single multiply.
4) Extracting a root involves a single divide.
When applied to binary computer operation logarithms
yield two further important advantages. First, a broad
range of values can be handled without resorting to floating point techniques (other than implied by the characteristic). Second, it is possible to establish the significance of an answer during the body of a calculation,
again, without resorting to floating point techniques.
Implementation of base10 logarithms in a binary system
is cumbersome and unnecessary since logarithmic functions can be implemented in a number system of any
base. The techniques presented here deal only with
logarithms to the base2.
A logarithm consists of two parts: an integer characteristic and a fractional mantissa.

X2
Log2 X
Log2 X Where X =
24 23 22 21 20 Characteristic . Even Power of 2

.
.

.

.
o

0

2

010.0000

0 0 0

3

011.0000

o

3

0

Figure 2. Identification of the Characteristic
In Figure 2 each point evaluated in Figure 1 has been repeated using binary notation. An arrow subscript indicates the highest even power of 2 appearing in each value
of X. Notice that in X = 3 the highest even power of 2 is
21. Thus the characteristic of the IOg2 3 is 1. Where X =10
the characteristic of the IOg2 10 is 3.
To find the log2 X is very easy where X is an even power
of 2. We simply shift the value of X left until a carry bit
emerges from the high order position of the register. This
procedure is illustrated in Figure 3. This characteristic
is found by counting the number of shifts required and
subtracting the result from the number of bits in the register. In practice it is easier to begin with the number of
bits and count down once prior to each shift.

y
4

Y=LOG2 X

Counter For
Characteristic

LOG2 8 = 3.00

Value of X in Binary

1000
o1 1 1
01 10
0101
0100
001 1
Characteristic

o0 0 0
o0 0 1
o0 1 0
o1 0 0

1000
00 0 0
0000
0000
1 0 0 0 0000
o0 0 0 0 0 0 0
Mantissa

011.0000 0000
7

C'I

CD
"C

III

c..

o

o

CHARACTERISTIC
LOG2
LOG2
LOG2
LOG2

3=
4=
8=
10 =

8

9

10

Initial
First Shift
Second Shift
Third Shift
Fourth Shift
Fifth Shift
Final
Log2 X=3.00

Figure 3. Conversion to Base2 Logarithm by Base Shift

MANTISSA
0.95
0.00
0.00
0.52

Figure 1. The logarithmic function and some example
values

Examination of the final value obtained in Figure 3 reveals no bits in the mantissa. The value 3 in the characteristic, however, indicates that a bit did exist in the 23
position of the original number and would have to be
restored in order to reconstruct the original value
(antilog).
'

2-126

C')

The log of any even power of 2 can be found in this way:
Decimal

A simple flow chart, and program, can be devised for
generating the values found in the table and, as will be
apparent, a straight line approximation for values that
are not even powers of 2. The method, as already illus·
trated in Figure 3, involves only shifting a binary number
left until the most significant bit moves into the carry
position. The characteristic is formed by_counting. Since
a carryon each successive shift will yield a decreasing
power of 2, we must start the characteristic count with
the number of bits in the binary value (x) and count down
one each shift.

Binary

12810000000
6401000000
3200100000
4
00000100
2
00000010
1 00000001

0111.00000000
0110.00000000
0101.00000000
0010.00000000
0001.00000000
0000.00000000

Figure 4. Base2 Logarithms of Even Powers of 2

LOG2
LOAO EXPONENT WITH COUNT EQUAL TO
NUMBER OF BITS IN MANTISSA MINUS 1

SLP1
SHIFT MANTISSA LEFT ONE BIT POSITION

Figure 5. Log Flowchart

2-127

o
"tJ
OJ

'iii"
"'"
N

COP CROSS ASSEMBLER
LOGS

PAGE:

1

; TITLE LOGS

1

; BINARY LOGARITHMS

2

3

01A4

,CHIP 420

4
; •...-

5

CONVERT TO LOGARITHM _ ..••. ;

6
7

RAM ASSIGNMENT

8
9

' ; DIGIT:

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

13

12

11

10
I

; REG 1

09

08

07

06

05

04

03

02

CH HM LM

I

00

TEMP

TEMP

; REG 3

01

TEMP

CH HMILM

; REG 2

CH HMILM
TEMP

CH HMILM

. LOCAL
; CH, HM, LM REPRESENT ANY THREE SEQUENTIAL MEMORY DIGITS. THEY
;'MAY BE DEFINED IN ANY REGISTER, THE SYMBOLIC NOTATION CH, HM,
; AND LM ARE USED FOn ADDRESSING TO ALLOW USER FLEXIBILITY.
; UPON ENTRY TO THE ROUTINE HM AND LM CONTAIN THE HI AND LO
; OF SOME VALUE X, THE MEMORY POINTER MUST CONTAIN THE ADDRESS
; OF THE CHARACTERISTIC (CH). THE CONTENTS OF THIS LOCATION ARE
; IGNORED AND ARE LOST DURING EXECUTION,
; UPON EXIT CH, HM, LM CONTAIN A STRAIGHT LINE APPROXIMATION OF
; THE LOG BASE 2 OF X. CH = CHARACTERISTIC HM = HI ORDER MANTISSA
; LM = LO ORDER MANTISSA. AN 8 BIT MEMORY AREA (TEMP) IS USED IN
; THE REGISTER OPPOSITE DURING THE CORRECTION OF A STRAIGHT
LINE APPROXIMATION OF A LOG OR AN ANTILOG,
;
A TEST IS MADE FOR X = O. IF THE VALUE OF X
; IS NOT ZERO AN INSTRUCTION IS SKIPPED UPON RETURN
; ,TO THE CALLING ROUTINE.
-EXAMPLE-,
; SUBROUTIN E CALL,
; RETURN ,HERE IF X =0'; RETURN ,HERE IF X>O'-

000
001
002

00
57
06

COP CROSS ASSEMBLER
LOGS
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72

14

; REG 0

33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52

15

003

A4

004

A9

005
006
007
008
009'
OOA
OOB
OOC

20
C8
49
05
SF
48
06
C3

LOG2:

CLRA
AISC

JSR LOG2
JP
l!:ERO
CONTINUE

07

X
PAGE:

; SEt CHARACTERISTIC,
; TO REG LENGTH -1.
; STORE IN MEMORY.

2

SLP1:

JSRP

SDB2

JSRP

SHLR

$TS1:

SKC
JP
RETSK
LD
AISC
RET
X
JP

$LST:
$NO:
$1S2:

SNO

-1

SLPl

; SET ADDRESS POINTER
; BACK 2 DIGITS.
; RESET CARRY AND SHIFT
; REG LEFT ON E BIT.
; IS CARRY = 1 YET?
; NO - KEEP GOING.
; YES - FINISHED!!
; NO - LOAD COUNT IN ACC,
; SUBTRACT ONE:
; MANTISSA IS A O! RETURN
; STORE CHARACTERISTIC,
; DO IT AGAIN!

; 2 ROUTINES ARE CALLED FROM THE SUBROUTINE PAGE BY THIS
; PROGRAM: SDB2, SHLR.

Figure 6.

2·128

The program shown develops the log2 of any even power
of 2 by shifting and testing as previously described.
Examine what happens to a value of X that is not an even
power of 2. In Figure 7, the number 25 is converted to a
base 2 log.

To reconstruct the original value of X, find the antilog,
requires only restoration of the most significant bit and
then its alignment with the power of 2 position indicated
by the characteristic. In the example, approximation
(IOg2 25 = 0100.1001) restoration of MSB can be accomplished by shifting the mantissa (only) one position to
the right. In the process a one is shifted into the MSB
position.

2510=000110012
Shift left until carry = 1
Characteristic

Carry

0100

1

Mantissa

Approximation of LOg2 X

Restoration of MSB

Char. Mantissa

Char. Mantissa

0100.10010000

0100.11001000

Log 2

10010000 0100.10010000

Figure 7. Straight Line Approximation of a Base2 Log

The value of the characteristic is 4 so the mantissa
must be shifted to the right until MSB is aligned with the
24 position.

The resulting number when viewed as an integer characteristic and fractional mantissa is 4.562510. The fraction
0.5625 is a straight line approximation of the logarithmic
curve between the correct values for the base210gs of 24
and 25. The accuracy of this approximation is sufficient
for many applications. The error can be corrected, as
will be seen later in this discussion, but for now let's
look at the problem of exponents or the conversion to an
antilog.

26

2f

25 24

000

1

23

21

20

100

1

The completion of this operation restores the value of X
(X = 25) and is the procedure used to find an antilog.
Figure 8 is a flow chart for finding an antilog using this
procedure. The implementation in source code is shown
in Figure 9.

~

ALOG:

22

r--------~--...:----------.,
MOVE MANTISSA TO TEMPORARY MEMORY LOCATION
CLEAR MANTISSA AREA. SET X = 
SET CARRY = 1 TO FORCE MSB OF X

SSLX:

r-------~SH~I=~~C~A~R~RY~I~N=TO~X~------,
SUBTRACT 1 FROM CHARACTERISTIC

(

$TST:

Figure 8_ Flow Chart for Conversion to Antilog

2-129

RETURN)

o
o"'0
to

'""I

ar
I \')

C\I

CD

"i:
£Xl

a..

o()

COP CROSS ASSEMBLER PAGE 3
LOGS
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109

. FORM

; ..... - CONVERT TO ANTILOG _ ..... ;

; THE FOLLOWING SUBROUTINE CONVERTS THE STRAIGHT LINE
; THE APPROXIMATION OF A BASE 2 LOGARITHM TO ITS CORRESPONDING
; ANTILOG. UPON EXIT FROM THE ROUTINE THE CONTENTS OF CH
; WILL BE EQUAL TO THE HEXADECIMAL VALUE OF 'F".
LOCAL

000
OOE
OOF
010
011
012
013
014
015
01

A4
00
36
34
00
36
37
22
08
A9

017
018
019
01A
01B
01C

A3
AA
05
5F
48
36

010
01E

A4
06

ALOG:
CLRA

$SLM:

$SLX:
$TST:
$LST:

JSRP

SDB2

X
XIS
CLRA
X
XDS
SC
JP
JSRP

03
03

JSRP
JSRP
LD
AISC
RET
X

SDR2
SHLC

JSRP
JP

SDB2
$SLM

03
03

; SET ACC TO O.
; CLEAR MANTISSA AREA.
; AND MOVE MANTISSA TO
; TEMPORARY STORAGE.
; LEAVE POINTER AT LO
. ; ORDER OF MANTISSA.
; RESTORE MSB OF X.

$SLX
SHLR

-1
03

; SHIFT REMAINDER
; LEFT INTO CARRY.
; MOVE BACK 2 DIGITS.
; SHIFT X LEFT 1.
; LOAD CHARACTERISTIC.
; CHARACTERISTIC -1.
; IF NO CARRY - FINIS.
; STORE REMAINDER AND MOVE
; DOWN ONE REGISTER.
; MOVE BACK 2 DIGITS.
; DO IT AGAIN.

; 4 ROUTINES ARE CALLED FROM THE SUBROUTINE PAGE BY THIS
; PROGRAM: SDB2, SDR2, SHLR, SHLC.

Figure 9.

Using the linear approximation technique just described,
some error will result when converting any value of X
that is not an even power of 2.
Figure 10 contains a table of correct base 2 logarithms
for values of X from 1 through 32 along with the error
incurred for each when using linear approximation. Notice that no error results for values of X that are even
powers of 2. Also notice that the error incurred for multiples of even powers of 2 of any given value of X is
always the same:

2-130

Valueof X

Error

5
2x5=10
4x5=20
3
2x3= 6
4 x 3 = 12
8x3=24

0.12
0.12
0.12
0.15
0.15
0.15
0.15

o

X
1
2
3

Hexadecimal
Log Base

Linear
Approximation
of Log Base 2

Error in
Hexadecimal

0.00
1.00

0.00
1.00

0.00
0.00

1.95

1.80

0.15

4

2.00

5

2.52

2.00
2.40

0.00
0.12

6
7

2.95
2.CE

2.8Q
2.CO

0.15
O.OE

8
9

3.00
3.29

3.00
3.20

0.00
0.09

10
11
12

3.52
3.75
3.95

3.40
3.60
3.80

0.12
0.15
0.15

13
14
15

3.93
3.CE
3.E8

3.AO
3.CO
3.EO

0.13
O.OE
0.08

16

4.00

4.00

0.00

17

4.16
4.29
4.3F

4.10
4.20
4.30

0.06

4.52

4.40
4.50

O.OF
0.12
0.17

4.60

0.15

18
19
20

0.09

21
22

4.67
4.75

23
24

4.87
4.95
4.A4

4.70
4.80
4.90

0.17
0.15
0.14

4.93

4.1AO
4.90

0.13
0.11

25
26
27

4.C1

28
29

4.CE;
4.09

30
31
32
33

4.CO

O.OE

4.F4

4.00
4.EO
4.FO

0.09
0.08
0.04

5.00

5.00

0.00

4.E8

EM-1+

EM-EM-1
2

CD
N

0.03
0.09
0.00
0.11
0.15
0.16
0.16
0.16
0.15
0.14
0.12
0.10
0.00
O.OA
0.06
0.02

Figure 10. Error Incurred by Linear Approximation of Base 2 Logs

continues until at 16 correction pOints the maximum error for the absolute value of the logarithm is less than 1
percent. This can be reduced to 0.3 percent by distributing the error. Interpolated error values are listed in Flgure 10 and are repeated in Figure 11 as a binary table.

2-131

aJ

~.

5.1·

An error that repeats in this way is easily corrected
using a look-up table. The greatest absolute error will
occur for the least value of X not an even power of 2, x =3,
is about 8%. A '4 point correction table will eliminate
this error but will move the greatest uncompensated
error to X =9 where it will be about 4%. This process

o-a

....N
CD

·C

m

Q..

0
0

High Order
4 Mantissa
Bits

Binary
Correction
Value

Hexadecimal
Correction
Value

,0000
0001
0010
001 1
0100
0101
0110
0.1 1 1
1000
1001
1010
10 11
1100
110 1
1110
1111

0000 0000
0000 1001
00001101
0001 0001
0001 0101
00010110
00010110
00010110
00010101
0001 0100
0001 0010
0001 0000
00001101
0000 1010
00000110
00000010

o0
o9
o3

Notice in Figure 10 that left justification of the mantissa
causes its high order four bits to form a binary' sequence
that always corresponds to the proper correction value.
This works to advantage when combined with the COP400
LQID instruction. LQID implements a table look·up func·
tion using the contents of a memory location as the ad·
dress pOinter. Thus we can perform the required table
look·up without disturbing the mantissa.

1
1
1
1
1
1
1
1
1

1
5
6
6
6
5.
4
2
0
D
oA
.6
2

Figure 12 is the flow chart for correction of a logarithm
found by linear approximation. Figure 13 is its imple·
mentation in COP400 assembly language. Notice that
there are two entry pOints into the program. One is for
correction of logs (LADJ:), the other is for correction of a
value prior to its conversion to an antilog (AADJ:).

o
o
o

Figure 11. Correction Table for L2 X Linear
Approximations

(

START

)

t
LADJ:

SET MEMORY ADDRESS POINT
TO ORDER CORRECTION VALUE
SAVE TABLE POINTER IN MEMORY
LOAD HIGH ORDER MANTISSA
INTO ACCUMULATOR

$XPM:

STORE MANTISSA VALUE IN MEMORY
LOAD TABLE ADDRESS INTO ACCUMULATOR
LOAD C.DRRECTION VALUE INTO Q REGISTER

SQTM:

TRANSFER CORRECTION VALUE TO MEMORY'

$ADD:

ADD CORRECTION VALUE TO MANTISSA

t
SLST:

(

RETURN

)

Figure 12. Flow Chart for Correction of a Value Found by Straight Line Approximation

2·132

(")

COP CROSS ASSEMBLER
LOGS

o"tJ

PAGE:

to
0)"

""'I

110
111
112
113
114
115
116
117
118
119
120
121

122

123

124

125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151

. FORM

: .....- ADJUST VALUE OF LOGARITHM _ .....
. LOCAL

N

: THE FOLLOWING TABLE IS USED DURING THE CORRECTION OF VALUES
: FOUND BY STRAIGHT LINE APPROXIMATION. IT IS PLACED HERE IN
: ORDER TO ALIGN ITS BEGINNING ELEMENT WITH A ZERO ADDRESS AS
REQUIRED BY THE LQID INSTRUCTION.
01F
020
021
022
023
024
025
026
027
028
029
02A
02B
02C
02D
02E
02F

44
03
09
OD
11
15
16
16
16
15
14
12
10
OD
OA
06
02

: REGISTER WITH ZERO ADDRESS.

TPLS:

NOP
.WORD

. WORD

015,016,016,016

03,09,OD,011

. WORD

015,014,012,010

.WORD

OD,OA,06,02

; THE FOLLOWING SUBROUTINE ADJUSTS THE VALUE OF A BASE 2
: LOGARITHM FOUND BY STRAIGHT LINE APPROXIMATION. THE
: CORRECTION TERMS ARE TAKEN FROM THE TABLE ABOVE. THE
; SUBROUTINE HAS 2 ENTRY POINTS:
LADJ: -

ADJUSTS A VALUE DURING CONVERSION TO A LOG

AADJ: -

ADJUSTS A VALUE DURING CONVERSION TO ANTILOG

: THE CARRY FLAG IS SET UPON ENTRY TO DISTINGUISH BETWEEN LOG
: (C = 1) AND ANTILOG (C =0) CONVERSIONS. DURING A LOGARITHM
; CONVERSION THE VALUE FOUND IN THE ABOVE TABLE IS ADDED TO
; THE MANTISSA. DURING AN ANTILOG CONVERSION THE VALUE FOUND
; IN THE ABOVE TABLE IS SUBTRACTED FROM THE MANTISSA.

030
031
032
033
034
035
036
037
038
039

32
F3
22
05
07
05
37
06
00
52

COP CROSS ASSEMBLER
LOGS
152
153
154
155
156

03A
03B
03D
03F
03F

BF
332C
04
07
20

157
158
159
160
161
162
163
164
165
166
167
168
169
170
171

040
041

80
98

042
043

35
48

AADJ:
LADJ:
$LD

RC
JP
SC
LD
XDS
LD
XDS
X
CLRA
AISC

$LD

03

TBL

;
;
;
;
;
;
;
;
;
;

C =0 FOR ANTILOG
CONVERSION.
C = FOR LOG2 ADJ.
MOVE ADDRESS POINTER BACK
ONE LOGATION.
LOAD CONTENTS OF HI MANTISSA
AND STORE IT IN THE LO ORDER
OF THE TEMP MEMORY LOCATION.
SET TABLE POINTER
(ACC) TO TABLE ADDRESS.

PAGE:

$GTM:

; LOAD CORRECTION VALUE TO Q.
; TRANSFER Q REGISTER
; CONTENTS TO MEMORY.

LaiD
CQMA
XIS
XDS
SKC

; ANTILOG?

$ADD:

JSRP
JSRP

COMP
ADRO

$LST:

LD
RET

03
; CHARACTERISTIC AND

; YES - COMPLIMENT.
; ADD CORRECTION VALUE
; TO MANTISSA.
; SET POINTER TO
: RETURN.

; 2 ROUTINES ARE CALLED FROM THE SUBROUTINE PAGE BY THIS
;PROGRAM:COMP,ADRO
0020
0002

V1 = TPLS&OFF
TBL=V1/16

Figure 13.

2-133

C\I

Q)

·c

m
Q.

o
o

Subroutines Used by the Log and Antilog Programs
COP CROSS ASSEMBLER
LOGS

PAGE:

6

172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223

FORM
0080

; ....•- SUBROUTINES _ ..... ;

PAGE 02

; THE FOLLOWING ROUTINES RESIDE ON THE SUBROUTINE PAGE. THEY
; ARE CALLED BY THE LOGS PROGRAM BUT ARE GENERAL PURPOSE IN
; NATURE AND FUNCTION AS UTILITY ROUTINES.

; ...•.- COMPLEMENT 8 BITS _ ..... ;
. LOCAL
; THIS ROUTINE FORMS IN MEMORY THE 2'S COMPLEMENT OF THE TWO
; ADJACENT DIGITS IDENTIFIED BY THE ADDRESS POINTER. THE
; CONTENTS OF THE ADDRESS POINTER ARE NOT ALTERED.
; THERE ARE TWO ENTRY POINTS:
; COP: COMPLEMENT 8 BITS.
; CMPE: EXTEND THE COMPLEMENT TO AN ADDITIONAL 8 BITS

080
081
082
083
084
085
086
087
083
089
08A
08B
08C

22
00
06
10
44
04
00
06
10
44
04
44

A4

COMPo
CMPE:

SC
CLRA
X
CASC
NOP
XIS
CLRA
X
CASC
NOP
XIS
NOP
JP

; SET MINUEND; 0
; AND STORE IN MEMORY.

; SET MINUEND; 0
; AND STORE IN MEMORY.

SDB2

; AVOID SKIP IF DIGIT 15.
; RETURN THRU SDB2
; TO RESTORE POINTER.

; ....,- ADD 8 BITS IN ADJACENT REGISTERS _ ..... ;
. LOCAL

; THIS ROUTINE ADDS TWO BINARY DIGITS (8 BITS) FROM ANY REGISTER
; TO THE CORRESPONDING TWO BINARY DIGITS IN EITHER REGISTER
IMMEDIATELY ADJACENT. THERE ARE THREE ENTRY POINTS:
LADR: -

RESET CARRY AND ADD 2 DIGIT PAIRS

2-134

o

COP CROSS ASSEMBLER
LOGS
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270,
271
272
273
274
275
276

PAGE:

o"U

7

LADD: ADD1: -

ADD 2 DIGIT PAIRS WITH UNMODIFIED CARRY
ADD 2 SINGLE DIGITS WITH UNMODIFIED CARRY

...arm

I \)

080
08E
oaF

090
091
092
093
094
095
096
097

32
15
30
44
14
15
30
44
14
44
48

LADR:
LADD:

ADD1:

SLST:

RC
:0
ASC
NOP
XIS
LD
ASC
NOP
XIS
NOP
RET

01

01
01

01

;
;
;
;
;
;
;
;
;
;
;

RESET CARRY PRIOR TO ADD.
LD ADDEND AND MOVE TO ADJ REG
ADD AUGEND.
AVOID CARRY!
STORE SUM AND MOVE TO ADDEND
REPEAT PROCESS
FOR
HIGH ORDER
DIGIT.
AVOID SKIP IF DIGIT 15.
FINISHED - RETURN!!!!

; .....- ADD 8 BITS IN OPPOSITE REGISTERS _.- ;
. LOCAL

; THIS ROUTINE ADDS TWO BINARY DIGITS (8BITS) FROM ANY REGISTER
; TO THE CORRESPONDING TWO BINARY DIGITS IN EITHER REGISTER
; DIRECTLY OPPOSITE. THERE ARE THREE ENTRY POINTS:
ADRO: - RESET CARRY AND ADD 2 DIGIT PAIRS
ADDO: - ADD 2 DIGIT PAIRS WITH UNMODIFIED CARRY
AD01: - ADD 2 SINGLE DIGITS WITH UNMODIFIED CARRY

098
099
09A
09B
09C
090
09E
09F
OAO
OAl
0A2

32
35
30
44

ADRO:
ADDO:

34
15
30
44

AD01:

34
44

48

SLST:

RC
LD
ASC
NOP
XIS
LD
ASC
NOP
XIS
'NOP
RET

03

03
01

03

; .....- SET DIGIT ADDRESS BACK TWO _ ..... ;

277

2·135

; RESET CARRY PRIOR TO ADD.
; LD ADDEND AND MOVE TO OPP REG
; ADD AUGEND.
; AVOID CARRY!
; STORE SUM AND MOVE TO ADDEND.
; REPEAT PROCESS
; FOR
; HIGH ORDER
; DIGIT.
; AVOID SKIP IF DIGIT 15.
; FINISHED - RETURN!!!!

C\I

CD

-c

m

a..

oo

COP CROSS ASSEMBLER
LOGS

PAGE:

8

. LOCAL

278
279

280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331

; THIS ROUTINE SUBTRACTS 2 FROM THE CONTENTS OF THE
; DIGIT POINTER (B REGISTER). THE CONTENTS OF THE
; ACCUMULATOR ARE LOST IN THE PROCESS. THE USE OF
; SDB2 ALLOWS ADDRESSING WITHIN THE LOGS SUB
; ROUTINE TO BE RELATIVE TO THE CONTENTS OF THE
; ADDRESS POINTER (B REGISTER) UPON ENTRY.
; SDB2 IS COMMONLY USED IN BYTE OPERATIONS TO RESTORE THE
; DIGIT POINTER TO THE LOW ORDER POSITION.
; THERE ARE TWO ENTRY POINTS:
; SDR2:

; SDB2: SET DIGIT ADDRESS. BACK 2 RETAINING PRESENT REGISTER.

OA3
0A4
OA5
OA6
OA7
OA8

35
4E
5E
44
50
48

SDR2:
SDB2:

LD
CBA,
AISC
NOP
CAB
RET

03
-2

; MOVE TO OPPOSITE ·REGISTER.
; PLACE DIGIT COUNT IN ACC.
; SUBTRACT 2.
; SHOULD ALWAYS SKIP.
; PUT DIGIT COUNT BACK.
; FINISHED - RETURN!!

; ....• - SHIFT LEFT - ..... ;
. LOCAL
; THIS ROUTINE SHIFTS LEFT THE CONTENTS OF TWO MEMORY
; LOCATIONS ONE BIT. THERE ARE THREE ENTRY POINTS:
SHLR: RESETS THE CARRY BEFORE SHIFTING
IN ORDER TO FILL THE LOW ORDER
BIT POSITION WITH A O.
SHLC: SHIFTS THE STATE OF THE CARRY INTO
THE LOW ORDER BIT POSITION.
SHU: SHIFTS LEFT THE CONTENTS OF ONLY
ONE MEMORY LOCATION. THE STATE
OF THE CARRY IS SHIFTED INTO THE
LOW ORDER POSITION OF MEMORY.

OA9
OAA
OAB
OAC
OAD
OAE
OAF

32
05
30
44
04
05
30

COP CROSS ASSEMBLER
LOGS
332
333
334
335
336
337

SET DIGIT ADDRESS BACK 2 AND MOVE TO OPPOSITE REGISTER.

OBO
OB1
OB2

44
04
48

SHLR:
SHLC:

SHU:

PAGE:

RC
LD
ASC
NOP
XIS
LD
ASC

; CLEAR CARRY PRIOR TO SHIFT.
; LOAD FIRST MEM DIGIT.
; DOUBLE IT.
; AVOID SKIP.
; STORE SHIFTED DIGIT.
; LOAD NEXT MEM DIGIT.
; DOUBLE IT TOO.

NOP
XIS
RET

; AVOID SKIP, IF ANY
; STORE SHIFTED DIGIT.
; FINISHED - RETURN!

9

$LST:

.END

2-136

Use of Macro-Assembled
Code

c:
o(1)

National Semiconductor
COP Brief 3
May 1980

o

3
:
D)
(')

a
Introduction
The use of macro assembled code in a COP400 series
program can be beneficial to the user if implemented
correctly. Care must be taken to insure that ROM space
is not being utilized in a wasteful manner. In many cases
a block of commonly used code would lend itself to a
subroutine rather than repeating a macro. The purpose
of this brief is to illustrate the advantages of the macro
capability of the COP400 Product Development System
(PDS). Due to modifications in the assembler program
there is erroneous information concerning macro calls
in the COP400 PDS Manual. These modifications are
discussed in the section labeled GEN ERAL.
By using macros the programming process becomes
much more general in nature. In some circumstances,
with a good macro library, a pseudo higher level language can be created. This higher level of instructions
inefficiently utilizes ROM space. However, if the ROM
space is available, macros can ease the task of programming. A feasable approach to organized programming
might be to work from a macro library and in the event
of limited ROM space, optimize code by replacing the
macros which are repeatedly used, by a single subrou·
tine and calling statements.
Macros also may be used as programming aids which
ease the understanding of the instruction set. When utilizing macros to rename single instructions no ROM
space is wasted. Macro statements must be declared at
the'beginning of a source file. However, this does not
utilize ROM space unless the macro is called within the
source. Various methods of creating multiple andsingle
instructions macros are discussed below.

Creating Instruction

Ma~ros

One very basic use of macros is to rename instructions
or groups of instructions to suit individual preferences.
In the example shown the user must add the macro to
the source file and each time the new mnemonic is encountered the assembler will create the correct code.
B1 =0
B2=0
B4=2
B8=3
. MACRO
SKMBZ
. ENDM

; EQUATE STATEMENTS
; USED FOR PROGRAMMING
; CLARITY

By utilizing the equate capabilities the user can even
further personalize the instruction set. In the above example 'B1' is equated to '0', 'B2' to '1', etc. This translates
a bit position '0,1,2,3' to a bit weight of '1,2,4,8' which
may be of preference to the programmer. In any case,
the ability to manipulate the instruction set is available
to the user without direct modification to the assembler
program.
Conditional assembly in conjunction with macro capabilities may be utilized to further ease programming. In
the following example the 'JSR' and 'JSRP' instructions
are replaced with a simple 'CALL' statement. It is important to allocate the proper number of ROM spaces during
pass 1 of the assembler so as to assign a ROM location
to correspond to each label. It is not until pass 2 of the
assembler that information of label addresses is known.
Because of this the macro must be able to determine
whether the 'CALL' is a one or two byte instruction. This
can be accomplished by use of conditional assembly
statements. In the example shown, all subroutines located in page 2 must be labeled by an 'A' followed by the
subroutine name. Conversely, subroutines not located
in page 2 must not begin with the letter 'A'. Note that the
character 'A' was chosen arbitrarily and may be modified
to any legal character or characters.
· MACRO CALL,X,Y
· IFC #1 EQ A
JSRP X'Y
· ELSE
JSR X'Y
· ENDIF
· endm
CALL

3

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Q.
(')

oQ.
CD

; MACRO TO RENAME JSR, JSRP
; TEST IF LABEL IS PREFACED
; BY AN 'A'
; YES, ASSEMBLE SINGLE BYTE
; NO, ASSEMBLE DOUBLE BYTE
; MUST TERMINATE. IF
; TERMINATE MACRO

AINC

; CALL SUB IN PAGE 2

This statement will generate:
JSRP

AINC

; CALL SUB NOT IN PAGE 2

CALL SUB

This statement will generate:
JSR

The renamed instruction may now be utilized in the following way:

68
OR

sz

m

AINC must be located in page 2 or an assembler error
will occur.

SZ, BIT
BIT

sz

~

o

SUB

(')

o"tJ

...i"OJ

3

In both cases 'SKMBZ 3' will be assembled.

w

2-137

-

Table Look-Up Macro

o

This macro will place the look-up table in the ROM space
designated by the LOC parameter or if the parameter is
not specified the table will follow in successive locations
after being called.

C"')

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o

Macros of Interest

MACRO
TABLE,LOC
.IFC #>0

· x'

LOC
· ELSE
· ENDIF
. WORD
· WORD
. WORD .
.WORD
.WORD·
· WORD
· WORD
. WORD
· WORD
· WORD
.WORD
. WORD
. WORD
.WORD
. WORD
.WORD
. EN OM

TABLE

OFD
061
ODB
OF3
067
OB7
03F
OE1
OFF
OE7
OCF
OEF
070
-()9D
08F
000

024

; SEG TABLE LOOKUP
; TEST IF PARAMETER IS THERE
; YES, USE IT
; NO, ELIMINATE ROM POINTER
; TEMINATE . IF
;0
;1
;2
;3
;4

The code generated will correspond to the look·up table
given in the macro. This table may be modified to suit
any particular symbol. Sixteen segment arrays are listed
only to take advantage of the LQID instruction. These
may be modified to the user's preference.
Additional Macro information is available in the COP400
Product Development System Manual.

General
The COP PDS Manual defines parameter delimiters when
using macros as commas or blanks. When creating the
macro, parameters must be separated by commas whereas blanks are not acceptable. When calling the macro it
is acceptable to delimit the parameters by either blanks
or commas .

.; 5
;6
;7
;8
;9
;P
;A

In order to assure correct assembly when using the. IF or
. IFC directives it is essential to terminate these directives
by a .ENDIF. This point is not emphasized in the manual. However it is important in the assembly process .

;u
;C
;F
; BLANK

The. LIST directive may be used to suppress the macro
listing in the source or to expand it. The COP PDS Manual
covers LIST options in detail.
.

; SET ROM POINTER AT ROM
; LOCATION 024

OR
TABLE

; START SEVEN SEG AT PRESENT
; ROM LOCATION

2-138

L·Bus Considerations

National Semiconductor
COP Brief 4
May 1980

r:-

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en

o
o
::s
en

c:
CD

""'l

Q)

L·Bus Considerations
Users of the COP400 family of microcontrollers should
be aware that certain outputs exhibit peculiarities that
preclude their use as clocks for edge sensitive devices
such as flip-flops, counters, shift registers, etc_ All family
members excluding the COP410L and COP411L may

START:
CLRA
LEI
LBI
STII
AISC

4

: ENABLE THE 0
; REGISTER TO L LINES

TEST

12

LOOP:
LBI
CAMO
JP

TEST

; LOAD Q WITH X'C3

LOOP

Figure 1. Glitch Test Program

generate false states on 4J-L7 during the execution of the
CAMO instruction_ Figure 1 contains a short program to
illustrate this.

o::s·
en

In this program the internal 0 register is enabled onto
the L lines and a steady bit pattern of logic highs is output on Lo, L1, L6, L7, and logic lows on L2-L5 via the twobyte CAMO instruction. Timing constraints on the device
are such that the 0 register may be temporarily loaded
with the second byte of the CAMO opcode (X'3C) prior to
receiving the valid data pattern. If this occurs, the opcode
will ripple onto the L lines and cause negative-going
glitches on Lo, L1 , Le, L7, and positive glitches on L2-L5'
Glitch durations are under 2 microseconds, although
the exact value may vary due to data patterns, procesSing parameters, and L line loading. These false states
are peculiar only to the CAMO instruction and the L lines.
The user should experience no difficulty interfacing with
other COP420 outputs such as GO-G3 and 0 0 -03 to edge
sensitive components.

o

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(5.
~

2-139

Jj

National Semiconductor
COP Brief 5
May 1980

Software and Opcode
c::: Differences in the COP444L
o
;: Instruction Set

Co)

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~

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"-

The COP444L is essentially a COP420L with double
RAM and ROM. Because of this increased memory space
certain instructions have expanded capability in the
COP444L. Note that there are no new instructions in the
COP444L and that all instructions perform the same
operations in the COP444L as they did in the COP420L.
The expanded capability is merely to allow appropriate
handling of the increased memory space. The affected
Instructions are:

The LDD, XAD, and two byte LBI are modified so that
they may address the entire RAM space. The opcodes
are as follows:
LDD

100 1 0
101

LSI

I 00 1 11

rid

XAD

100 1 0
111

I 001 11

rid

10 0 1 110 0 1 11
111 r i d

Q)

Co)

c:::

~

Q)

is

JMP
JSR
LDD
XAD
LBI

a
a
r,d
r,d
r,d

The XABR instruction change is transparent to the user.
The opcode is not changed nor is the function of the
instruction.The change is that values of 0 through 7 in
A will address registers in the COP444L - i.e. the lower
three bits of A become the Br value following the instruction. In the COP420L, the lower two bits of A became the Br value following an XABR instruction.

(a = address)
(a = address)
(r,d = RAM address Br,Bd)
(r,d = RAM address Br,Bd)
(r,d = RAM address Br,Bd; only two byte
form of the instruction affected)

XABR

The JMP and .JSR instructions are modified in that the
address a may be anywhere within the 2048 words of
ROM space. The opcodes are as follows:

Note that those instructions which have an exclusive-or
argument (LD, X, XIS, XDS) are not affected. The argument is still two bits of the opcode. This means that the
exclusive·or aspect of these instructions works within
blocks of four registers. It is not possible to toggle Br
from a value between 0 and 3 to a value between 4 and 7
by means of these instructions.
There are no other software or opcode differences be·
tween the COP444L and the COP420L. Examination of
the above changes indicates that the existing opcodes
for those instructions have merely been extended.
There is no fundamental change.

II)

Q)

"£:
CO
Q.

0

CJ
2-140

National Semiconductor
COP Brief 6
May 1980

RAM Keep"Alive

A COPS™ application is a small scale computer system
and the design of a power shut·down is not trivial. During
the time that power is available, but out of the designed
operating range, the system must be prevented from do·
ing anything to harm protected data. This will typically
involve some type of external protection or timing circuit.
There is an option on the COP420, 420L, and 410L parts
called "RAM Keep·Alive" that provides a separate power
supply to the RAM area of the chip via the CKO pin. The
application of power to the RAM while the remainder of
the chip has been powered down via Vee will keep the
RAM "alive".
However, the integrity of data in the RAM is not only a
function of power but is also influenced by transient con·
ditions as power is removed and reapplied. During power·
on, the Power On Reset (POR) circuit wil.1 keep transients
from causing changes in the RAM states. The condition
of power loss will have some probability of data change
if external control is not used.
At some point below the minimum operating voltage
certain gates will no longer respond properly while
others may still be functional until a much lower vol·
tage. During this transition time any false signal could
cause a false write to one or more cells. Another effect
could be to turn on multiple address select lines causing
data destruction.

The desirable approach is to force the COP reset input
to zero before the voltage falls below 4.5V. This provides
a drop out rate of approximately 1 in 50k for the "L"
parts and 1 in 100k for the 420. By also stopping the
clock of the" L" parts they can achieve a drop·out rate
similar to the 420. While not perfect, the number of
cycles between data error should be considered with
respect to the needs of the application.
The external circuitry to control the chip during the power
transition has several implementations each one being
a function of the application. The simplest hardware is
found in a battery powered (automotive) application. The
circuit must sense that the switched 12V is falling (e.g.,
at some value much below 12V and still greater than 5V).
This can be done by using the unswitched 12V as a ref·
erence for a divider to a nominal voltage of 8V. As.the
switched 12V drops below the reference a detector will
turn on a clamp transistor to a series switch, the paR,
and/or the clock circuit (Figure 1).lt should be noted that
this draws current during the absence of the switched
12V circuit.
In non·automotive usage a similar circuit can be used
where there is a stable reference voltage available to
use with the comparator/clamp. Thus a 3.6V rechargable
Ni·Cad battery could be used as the reference voltage
and VRAM if the appropriate divider is used to level shift
to this operating range.

Testing the rate of data change is very difficult because
it must be done on a statistical basis with many turn/on·
turn/off cycles. Two factors have a major bearing on the
numbers derived by testing. One is to call any change in
a related data block a failure, even though more than
one bit in that block may have changed (thiS latter case
may well be due to the "address select mode"). The sec·
ond factor is that without massive instrumentation it is
impossible to examine the data after each power cycle.
Indeed, to do so might have caused errors!

In AC line·powered applications, a similar method could
be used with the raw DC being sensed for drop. Another
method would be to sense that the line had missed 2·3
cycles either by means of a charge pump or peak detec·
tion technique. This will provide the signal to turn on the
clamp. One must make this faster than the time to dis·
charge the output capacitance of the power supply, thus
assuring that the clamp has performed its function be·
fore the supply falls below spec value.

By running the power cycle for a period of time and then
looking for changes, one could overlook multiple changes
thus reducing the error rate. This has been minimized by
more frequent checking which indicates that the errors
are spread out randomly over time.

In conclusion, to protect the data stored in RAM during
a power·off cycle, the paR should go low before the Vee
power drops below spec and come up after Vee is within
spec. The first item must be handled with an external
circuit like Figure 1 and the latter by an RC per the data
sheet.

With a power supply that drops from 4.5 to 2V in approx·
imately 100 ms, the drop·out rate is 1 in 5k to 6k power
cycles. Reducing the voltage fall time will cause an im·
provement in the number of cycles per drop·out. This
will reach a limit condition of a very high number (1 per 1
million?) when the power falls within one instruction
cycle (4·10f's for the 420, 15·40f's for the "L" parts).
Attaining very rapid fall time may cause problems due
to the lack of decoupling/bypass capacitance. By insert·
ing an electronic switch between the regulator and Vee
of the COP chip one might be able to meet this type of
fall time. By implication some type of sensing is required
to cause the switching.

2-141

5W

+v (12V)

6Sk

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...CD

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tn

C

o MICROBUS™ Programming

;::

e

National Semiconductor
COP Brief 7
May 1980

Considerations

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c
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Introduction

MICROBUS™ Programming Considerations

The COP402 MICROBUSTM is a peripheral microproce~­
sordevice and its operating characteristics are described
· in the 402M data sheet and the Chip User's Manual. Given
in this brief are some clarifications as to the allowable
option selection and also as to programming requireC) ments that are not readily obvious.

E

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"en

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COPS IN Input Port Options on the
COP402M
.
Neither the IN Input options that maybe selected, nor the
input characteristics associated with the INIt: and ININ
instructions are clearly indicated in the COP402M data
sheet (Preliminary, September 1978). In the COP402M
configuration INo isa gerieral purpose latched input
with a load device to Vcc. All other IN inputs (CS, RD,
and WR), are selected as high impedance inputs without
· pull-up devices.
The COP402M and the COP420M. will execute ININ and
INIL instructions, yet the exact operation of these in·
structions is not detailed in the specification. INo information will be latched in accordance with the criteria
specified in the data sheet (rinin. 2 inst. cycle time at logic
zero), as will the WR, (IN 3) input if these criteria are met.
If theWR pulse does not meet the 2 instruction cycle criteria, yet does satisfy MICROBUS liming, the status of
the IL latch corresponding to the WR input (IN 3 ) cannot
be.predicted when the status of the IL latches is read in
.via an INIL instruction.
When executing the ININ instruction, the status of INo
and the MICROBUS signals will be read in with the exception of the RD (INt) signal. This signal will always
· read in as a logical one.

COPS IN Input Port Options on the
COP420M

Q)

When selecting a MICROBUS option it is possible to
select either load devices to Vcc or high impedance inputs on INo and all MICROBUS signals. These options
may be chosen individually corresponding to INo, CS,
WR, and RD signals. There is also a choice between
standard TTL input levels or a High Trip option for the IN
and MICROBUS inputs. The only restriction (for all 400
series devices) is that when either a High Trip or TTL trip
levels are chosen, they must be selected in blocks corresponding to that input port. For example, all IN lines
must have High Trip, rather than just one IN line.

The COP402M data sheet describes the handshaking
protocall required when implementing the COP420M as
a microprocessor' peripheral device. When a WR.strobe
is detected, an internal reset of the Go latch occurs.
This signal indicates that data is ready to be transferred
to the Q latches from the microprocessor bus. Due to
the relatively short timing requirements on the WR strobe
signal it is necessary to latch the write request such
that under program control the COP device can service
the write request. Upon completion of the data transfer
and any task that may have been performed, the user
then signals the microprocessor that it is available once
again by setting the Go latch. This portion of the
handshaking (setting Go) is the only time that the G Port
should be used as an output port. All G Ports in the
MICROBUS configuration should be used only as input
in order to guarantee that a WR strobe is not missed.
When using the G Port as an output Port it is possible
that a WR pulse may be ignored as explained in the
example below. The G Port may be utilized as an output
port in the following way, however, there is a 3 cycle
period that if a WR pulse occurred it would be ignored.
GPIN: LBI
ING

OUT:

RAM

;
;
X
;
5MB
X
;
;
SKGBZ 0
JP
OUT
;
JP
SERVICE ;
OMG
;

POINT TO RAM LOCATION
READ THE G PORT
STORE IN RAM
CHANGE G PORT INFO TO BE SENT OUT
SEE IF WR STROBE HAS OCCURED
HAVE NOT BEEN INTERRUPTED (YET)
GO SERVICE WR REQUEST
OUTPUT NEW G PORT INFORMATION

If a write pulse occured during the JP to OUT or the
OMG instructions it would not be recognized because
the OMG will set the Go latch to a logic one, signalling to
the microprocessor that the WR strobe has been
serviced.
It is possible to output to the G Port after WR and before
Go is set, and not miss a WR request. This means that
the data outputted on the Glines wil be updated only
after the microprocessor has initiated an interrupt.

General
The COP402M data sheet specified all IP address lines
as TTL compatible, with a fan out of one. Address lines
IP4 and IP5 do not meet this criterion, although all other
IP lines do. It is sufficient to say that all IP lines are
LSTIL compatible with a fan out of one, the restricting
factor being IP4 and IP5, (IOL @ O.4V, 360;<,..-.

tSETUP

~

I\..

SK

! - KoATA

01.

VALID

APPLICABLE FOR CoP49B, OS8906, MM5450

265

XI--1><=
I--

DATA
VALID

APPLICABLE FOR COP450, COP452, COP470, COP472

Figure 1. Serial Input Oata Timing

2-144

Serial Interlace Between
COPS™ Microcontrollers and
Peripheral Chips

National Semiconductor
COP Brief 9
May 1980

A variety of 1/0 and data memory expansion chips are
available 10 the COPS™ controllers fordilferent applications. Many of them use the serial port for data transfers,
and the COPS controllers allow multiple peripheral chips
to be tied in parallel for this purpose (see Figure 1). This
paper will discuss the system hardware considerations
needed to execute the data transfers. Most COPS controller pins allow various 1/0 options, and the user
should refer to the appropriate data sheet for specific
options information. For this discussion, it is assumed
that serial input (SI) is a high impedance input for simplicity, and serial output (SO) and clock (SK) are push·pull
outputs for lower switching time. All the chips are assumed to have the same power supply. The interface
response characteristics may be divided into two parts:
static and dynamic.

Standard and CMOS COPS controller outputs are designed to drive one TTL load or four LSTTL loads, where·
as the low power COPS controller outputs can drive only
one LSTTL load. If more drive is necessary, a buffer will
be needed. Standard and low power COPS controller
inputs have TTL input levels, therefore multiple TTL!
LSTTL TRI-STATE outputs can be connected together
directly to SI. The maximum total leakage current at the
SI input and all the TRI-STATE outputs determine the
maximum number of TRI-STATE outputs that can be tied
together_ The TTL! LSTIL output levels are not compatible with the CMOS COPS input levels so that extra external components will be necessary for the interface_
The simplest solution is to use a pull-up resistor to raise
the HIGH output level. A disadvantage is that the LOW
output level will be increased_

I. Static Response

Bipolar integrated circuits in other processes, e_g., a
DS8906 PLL chip manufactured by 12L process, may have
different input levels and different input source and sink
requirements. It is necessary to determine whether the
COPS output can meet the current requirement and
maintain a valid voltage level for the input.

2. Bipolar (TTL, LSTTL, 12L)

When the output to the serial interface changes state,
the input connected to the interface should detect the
change. This is done by keeping the output signal level
within the specified HIGH or LOW level range of the input. There are two types of transistors used in integrated
circuits, namely, MaS and bipolar transistors. They present different equivalent circuits to the output driver
and therefore are considered separately.

1. MOS (NMOS, CMOS, PMOS)
The MaS inputs look like capacitive loads to these outputs, with a maximum leakage current usually specified.
The COPS output driver must be able to sink or source
the total maximum leakage current resulting from various inputs connected to it, and keep the signal level
within the valid HIGH or LOW value range. Without any
leakage, the outputs should reach the same level as that
achieved when the output is not loaded.
Different IC devices have different HIGH and LOW input
ranges. Most NMOS parts have TIL compatible levels for
5V operation, i.e. OV to 0.8V for LOW level and 2.0V to Vcc
for HIGH level. The NMOS COPS controllers also allow
a mask-programmed optional range: OV to 1.2V for LOW
level and 3.6V to Vcc for HIGH level. Most CMOS parts
allow OV to 0.3Vcc for LOW level, 0.7Vcc to Vcc for HIGH
level. The COP470, a V.F. display controller in PMOS
process, has OV to Vcc - 4V for LOW level, and
Vcc -1.5V to Vcc for HIGH level.
When peripheral chips of different MOSFET types are
connected together, the output from the controller must
satisfy all the input requirements for each peripheral
Chip. When peripheral chips with TRI·STATE™ outputs
are tied to SI, each of the outputs must satisfy the input
level of the COPS controller, while supplying the maximum leakage current to the TRI·STATE outputs .. If an
input and an output have incompatible levels, external
Circuits may be necessary for level shifting.

3_ Mixed (Bipolar and MOS)
Both bipolar and MOS peripheral chips may be used in
the same system provided that all the current and voltage requirements are met. Most NMOS and bipolar chips
can be mixed together because of similar input voltage
levels. CMOS and PMOS chips, on the other hand, cannot be mixed with bipolar chips directly because of the
higher HIGH level required. The COPS output HIGH level
may be loaded down by the bipolar circuit to an unacceptable HIGH level for the CMOSIPMOS inputs. External circuits will be needed to solve the problem. The
simplest solution is a pull-up resistor which improves
the source current and raises the output to a higher HIGH
level. The resistance should not be too small to increase
the LOWlevel above TIL specification.

II. Dynamic Response
Provided an ouput can switch between a HIGH level and
a LOW level, it must do so in a predetermined amount of
time for the data transfer to occur. Since the transfer is
synchronous, the timing is relative to the system clock
(provided by SK). For example, if a COPS controller
outputs a value at the falling edge of the clock and is
latched in by the peripheral device at the rising edge,
then the following relationship has to be satisfied:
tOELAY + tSETUP

«

tCK (see Figure 1),

where tCK is the time from data output starts to switch
to data being latched into the peripheral chip, tSETUP is
the setup time for the peripheral device where the data
has to be at a valid level, and tDELAY the time for the output to read the valid level. tCK is related to the system

(")

o"'C
OJ
(6"
"""

co

2-145

Q)

"C

to

0..

oo

clock provided by the SK pin of the COPS controller and
can be increased by increasing the COPS instruction
cycle time. Maximum tSETUP is specified in the peripheral
chip data sheets. The maximum tSETUpis specified in
the peripheral chip data sheets. The maximum tDELAY
allowed may then be derived from the above relationship.

provides two sets of values, one for external loads that
includes TTLiLSTTL inputs, the other for pure capacitive
loads (MOS inputs).
If the capactive load is too large to satisfy the fJelay time
criterion, then three choices are available. An external
buffer may be used to drive the large load. The COPS in·
struction cycle may be slowed down. An external pull·up
resistor may be added to speed up the LOW level to HIGH
level transition. The resistor will also increase the output
LOW level and increase the HIGH level to LOW level tran·
sition time, but the increased time is negligible as long
as the output LOW level changes by less than O.3V. For
a 100pF load, the standard COPS controller may use a
4.7k external resistor, with the output LOW level in·
creased by less than O.2V. For the same load, the'low
power COPS controller may use a 22k resistor, with the
SO and SK output LOW levels increased by less than

Most of the delay time bef()re the output becomes valid
comes from charging the capacitive load connected to
the output. Each integrated circuit pin has a maximum
load of 7pF. Other sources come from connecting wires
and connection from PC boards. The total capacitive
load may then be estimated. The propagation delay
values given in data sheets assume particular capaci·
tive loads.
If the calcu'lated load is less than the given load, those
values should be used. If the calculated load is greater,
a conservative estimate is to assume the delay time is
proportional to the capacitive load. The COPS data sheet

O.1V.

This is MICROWIRETM
(Example System)

MICROWIRE
INTERFACE

VF
DISPLAY

SYSTEM
CONTROLS

2-146

COP410L/411L Hardware
Subroutine Stack Emulator

National Semiconductor
COP Brief 10
May 1980

(1)0

CO
C"-c
a~

-".

C"'"

-0

::::s_
CDO

The COP410Ll411 L devices differ from the COP420 devices primarily in the amount of available ROM and RAM,
and in the number of subroutine levels available_ The
COP420 has a 3 level subroutine stack, which allows
subroutines to be nested 3 levels deep_ If a subroutine is
called from the third subroutine level, the first return address is pushed from the top of the stack and lost. The
COP410L has a 2 level subroutine stack. When subroutines are nested 3 or more levels deep in a COP410L program, an overflow of the subroutine stack will occur
causing the return address from the first subroutine level
to be pushed off the top of the stack. The program will
not function properly if designed to return from the first
subroutine in the normal manner, since that return address will have been lost. The COP41 OLl411 L Hardware
Subroutine Stack Emulator is designed as a reliable aid
in finding subroutine stack overflow conditions in
COP410L programs.
The difficulty in finding a subroutine stack overflow condition lies in emulating the COP410L program. The COP402,
which is a ROMless functional equivalent of the COP420,
may be used to emulate the COP410L device. However,
the COP402 has a 3 level subroutine stack, as does the
COP420. Therefore,when emulating a COP410L device,
the program may exhibit an overflow of the 2 level stack
which will not be detected in the COP402 emUlator. Special care must be taken when writing COP410L programs
to insure that the 2 level subroutine stack is not violated.
The most obvious method of verifying the 2 level COP410L
stack is to systematically count the subroutine levels
directly from the program listing. With the listing, the programmer may follow through each subroutine, counting
the level of subroutines called from those routines. If subroutines are nested 3 levels deep, the COP410L program
will exhibit a stack overflow condition. This could cause
improper program execution in the COP410L and should
be corrected before submitting the program for production.
An alternate method of verifying the 2 level subroutine
stack is by writing a COP420 program that calls the entire
COP410L program as a subroutine. This effectively diminishes the COP402 stack by 1 level when emulating the
program. At the end of logical execution of theCOP410L
program a RET statement must be inserted to return to
the COP420 routine. If the COP410L program executes
correctly and then returns to the COP420 routine at the
correct location, the COP410L program may be free of
stack overflow violations. The breakpoint feature of the
COP Product Development System (PDS) is helpful in
detecting the return from the COP410L program. A breakpoint should be set at the COP420 program address immediately following the JSR statement that transfers
control to THE COP410L program. The PDS will breakpoint the COP402 at the return address from the COP41 OL
program, providing there are no stack violations in the
COP410L routine. All COP410L subroutines must be terminated in a RET or RETSK statement for the PDS to be
useful in verifying the 2 level stack. The COP420 return

address will be lost if the stack is deliberately overflowed
in the COP410L routine. Losing the COP420 return address will cause the PDS to indicate an erroneous stack
- overflow condition by returning from. the COP410L routine to an incorrect location. For this reason, all subroutines must end in a RET.
The previously described procedures for evaluating the
2 level subroutine stack are often unreliable due to different program structures. The most reliable method of
locating a subroutine -stack overflow is to use the
COP410Ll411 L Hardware Subroutine Stack Emulator.
This circuit will count the number of consecutive RET or
RETSK instructions that are executed. Counting the
return from subroutine instruction rather than the jump
to subroutines allows deliberate overflow of the subroutine stack, which may be necessary in some COP410L
programs.

(1)0
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.....
.....

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;

Block Diagram Description
The COP410U411 L Hardware Stack Emulator is designed
to be used with the COP400-E02 In-Circuit Emulator
Card. The system works in the following manner (see
Block Diagram, Figure 1). The COP410L program data is
latched onto the Hardware Stack Emulator card via the
<1>1 signal. The program data is decoded by the Data
Decode PROM and the appropriate control signals are
generated. During the second half of a 2-cycle instruction, the COP402 sends the SKIP line high. This signal is
used to disable the data decode PROM control signals
by forcing the PROM to decode data from the upper half
of memory in which all control signals are inactive (see
PROM Data, Table 1). The JSR and JSRP instructions
push the stack and the RET and RETSK instructions pop
the stack. The LQID instruction is a 2 cycle instruction
that first pushes the stack, then during the second instruction cycle, pops the stack. When a LQID is executed
at the second subroutine level a stack overflow condition will occur. Each time the stack is pushed, the stack
increment logic will clock the count down input of the
stack counter once and each time the stack is popped,
the stack decrement logic will clock the count down
input of the stack counter. The stack counter counts a
maximum of 2 pushes of the subroutine stack, after
which the increment logic is disabled. This .allows
deliberate overflowing of the subroutine stack. A subroutine stack overflow is registered when the stack
counter is popped 3 consecutive times. At this time, the
stack counter underflows and disables both the stack
increment and decrement logic, and lights the overflow
indicator.
The COP400 devices allow single-byte jumps (JP) within
any single page boundaries. Single-byte jumps are also
allowed anywhere within the boundaries of the subroutine pages (pages 2 and 3). Single-byte subroutine calls
(JSRP) are valid from anywhere in the program to routines on page 2. The op-codes for the JSRP instructions
are identical to the codes for the single-byte jumps in
pages 2-3. For this reason the JSRP call may not be used

2-147

o
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Cii"

.....

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'JSRP'
DISABLE
LATCH

a..

o(,)

14C74

sKIP-------_1
DATA
DECODE
PROM

·,c>----'
ENABLEC>--'---'

COP410L/411l
HARDWARE STACK

EMULATOA
BLOCK DIAGRAM

Figure 1. COP410LI411L Hardware Stack Emulator Block Diagram
on pages 2 or 3. However, the decode PROM on the Hard·
ware Stack Emulator will generate the JSRP signal
whenever a single-byte jump is executed on pages 2 or
3. The Address Decode Logic sets the JSRP disable
latch when the program is executing in pages 2 or 3 to
inhibit the JSRP control signal generated by executing
a single·byte jump on pages 2 or 3. Address 07F, while
not actually on page 2, is also decoded since a singlebyte jump from this location to anywhere in pages 20r3
is also coded as a JSRP and the JSRP signal generated
must, therefore, be inhibited. The JSR instruction is a
valid subroutine call anywhere within theCOP410L
program. Consequently, the Address Decode Logic does
not inhibit the JSR signal.

during the time ,that <1>, is high and program, data is
inputted by the COP402 when <1>, is low. The <1>, signal is
the basis for alltiming on the Hardware Stack Emulator.
<1>10 is created by delaying <1>, by approximately 3"s.This
signal is used to clock the decoded address into the
JSRP disable latch. The MM74C74 latches data on a lowto-high clock,transition. The <1>10 signal is used to insure
stable, valid data at the D input of the latch prior to the
clock pulse. ENABLE is generated by taking the NOR of
<1>, and <1>10. During the low period of ENABLE, the outputs of the ROM data latch are enabled to drive data to
the decode PROM. When the outputs are disabled, the
inputs to the decode PROM are held high with pull·ups.
At the rising edge of ENABLE valid data is latched into
the LQID and JSR latches. The stack counter is also
clocked on the rising edge of ENABLE. The data that
was set up at the stack counter inputs during the previ·
ous clock cycle enables or disables the ENABLE clock
appropriately.

Table 1. PROM Data
Address

Data

Address

Data

000

04

070

04

047

04

07F

04

048

OC

049

OC

04A

04

067

04

068

06

06F

080

05

OBE

05

OBF

00

OCO

04

1FF

04

Building the Hardware Stack Emulator
All signals required by the Hardware Stack Emulator are
available on the COP400- E02 Emulator Card. The signals
'may be brought to the Hardware Stack Emulator Card
with a 24 conductor ribbon cable plugged into the 5204
PROM 1 socket on the E02 Emulator Card. The signals
<1>" SKIP, and RST are not available at the 5204 PROM 1
socket so they must be either jumpered to the socket or
directly to the Hardware Stack Emulator board. If it is
desirable to run these signals via the 24 conductor
cable, then 3 printed circuit traces must be cut on the
E02 Emulator Card. The traces to pins 2, 3, and 23 of the
5204 PROM ,1 may be cut since these signals are not required by the Hardware Stack Emulator. SKIP, RST, and
<1>, may then be soldered to the socket and all required
signals will then be carried over the 24 conductor cable.
Power and ground are also carried to the Hardware Stack
Emulator board by the 24 conductor cable. ,The complete
circuit schematic and 5204 PROM 1 socket pinouts are
shown in Figure 2.

06

System Timing Description
The COP402 generates the ADIDATA signal which is
called <1>, in the COP410Ll411 L Hardware Stack Emulator
system(see COP402 Data Sheet). During program execution, address information is outputted by the COP402

2-148

52tl<
SOCKET
NUMBERS

Vec
12

IS5)AO
156) A,
(S7) A,

~CC

IS8) A,

Vce

PR

(S9)A.
lSI 0) AS
11

ISl1) A,
(513) A,
IS14) A.

IS2)SKIP

...E
IS22) 0,

18 De

1521) 0,

17 07

(S20) Os

14 06

(SI9) o.

13 05

1518)0,

8 O.
7 0,

1517) 0,
(516)0,

~
.j>.

ISI5) DO

74(;734

• 0,
3 0,
11
ClK

A.
1 A,

19
,• 16
,'5
, 12
9
,• 6

01

2 A,

748474

• A.
5 A,
7 A,

,

I

II

OUTPUT
DISABLE

8Ao

RA08

O'
__

r

RETl5K

IE.

E2 El

20~

CO
I I I I I
131211109

J5RP

02110 JSR

6 A,

, 5
2

r

D3 11 LOID

3 As

I

POWER SUPPLIES

'/~74C175

ENA.!!:.:........! ClK

_111

74COO
74C02
74C32
74(;74
74lS14

/.. ..

3.3kQ

Vee =PIN 16

r::::iiDi.· ....".
11

GND=PIN B

13

r

153) ~1 •
GNO

Vcc=PIN 14
GND=PIN 7

• ENABLE
• CIllO

~O.OOI.'

Vee = PIN 20
GNO == PIN 10

74C374

¢l2

.. :;J

-FiST 07

74(;175
14C193

Vee =PIN 24
%7.l514

'J. 74lS14

GNO=PIN 12

748474

RST

24 PIN CABLE FROM 5204 -

PROM 1 SOCKET ON E02 OR
EO' EMULATOR BOARD

~S23)

11

t:>o

10

• elR

%,74LS14
·SKIP, ¢It, RSf ARE !ill! CONNECTED TO THE 5204 PROM SOCKET PINS SHOWN 011 THE E02lE04 EMUlATOR
CARDS. THE PC TRACES MAY BE CUT TO THESE PINS aN THE EMULATOR CARD AND THE SIGNALS JUMPERED
TO THE PROM SOCKET FROM THE COP402 OR COP404l CONTROLLERS (¢l1 IS CALLED AD/Oln ON THE
COP4D2). IF CUTTING EMULATOR CARD TRACES IS UNDESIRABLE, THE SIGNALS SKIP. 4l1, AND JIST MAY BE
CONNECTED DIRECTlY TO THE HARDWARE EMULATOR VIA SEPARATE CONNECTIONS. THE CABLE IS

Vee ·SKIP -4l, Vee

Ao

At A2 A3 At As

Ati

Vee

SUGGESTED MERELY 'OR CONVENIENCE.

Figure 2. COP410Ll411L Hardware Stack Emulator

O~ 19 !JB

dOO

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CD
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16/15
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_
I-7.5/15~8.5/15-

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--13 /lSI~

~lD~
I

-I-----r..--_.-r

1

-.\ 1 - 500 ns

I

-11-l0ns -11-l0n5

EmU

IL..__........

L

Figure 3. COP410Ll411L Hardware Stack Emulator Signal Timing Relationships

2·150

Power Seat with Memory

"tJ

o
~
..,

National Semiconductor
Richard W. Kovener
COP Brief 11
May 1980

~

m

Introduction
CONSOLE SWITCHES

As cars continue to be downsized, more extra
features are being offered to the car purchaser to
individualize the car to his personal taste. This is
with
electronic
equipment.
especially
true
Automobiles are now available with digitally tuned
radios, trip computers, digital gauges and other
electronic systems. These have been made possible
only recently by the increasing level of semicon·
ductor integration and the resulting lower cost for
the components that make up each system.

0,1----1 STORE
cop
420l

A

A'

0,1----1

s·

0,1----1

c·

IGNITION

o·

This article describes another application for elec·
tronics in an automobile, a power seat with position
memory. This seat features powered adjustment in 8
different directions, the ability to store 2 sets of
position information in memory, and instant recall
and automatic adjustment to either of the 2
positions. The seat can therefore be adjusted to
accommodate 2 different drivers or 2 different driving
positions for the same driver and automatically
adjust to either of these positions on demand.
System Description
A block diagram of the seat control system is shown
in Figure 1. The heart of the system is the COP420L
microcontroller. This part is one of National
Semiconductor's COP400 Family of 4·bit, 1·chip
microcontrollers. Motor control information is output
to the TRI·STATE® octal latch and information from
the seat sensors is input through the TRI-STATE
octal buffer. Manual adjustment of the seat is
provided by 8 switches mounted on a console. These
manual controls have priority over automatic control
via the TRI-STATE control pin on the latch. In
addition, the controller software will terminate
automatic control if it detects the seat being
adjusted in a way different from its programmed
positions. This provides for manual override and is
necessary as a safety precaution. The system will
operate manually even with the controller part
removed, which gives a fail·safe operation.

MOTOR

o

Figure 1. Block Diagram

The Controller
The COP420L is an N·channel MOS device with
1K x 8·bit program memory and a 64 x 4·bit data
memory. Its internal architecture is shown in Figure
2, and electrical specifications are shown in Figure 3.
In this application, the bidirectional TRI-STATE L
lines are used to output motor control information to
the motor control latch and also are used to input

o

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2-151

-..........

,...
,...

-

Vee

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CK'

GND

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~,

L

eKO

L

TlME·BASE
COUNTER
(DIVIDE BY 1024)

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25

0

Z6

REGISTER

•

BUFFER

21
'8

18

se

SK

GJ
G

G,

REGISTER

•

G,

BUFFER

I/O CONTROLS

-

COP42DL ONl Y

Go

--,

I
I

SI03

I
5
9

SI02

SIO,

SlDo
11

I

IN) INZ IN1

S1

SEAIAll/O REGISTER

I

10

D,
00

10

].lEVEl STACK

20

OJ
0,

6

7

8

12

13

14

SO

15

19
INO

Figure 2. COP420L Block Diagram

Operating Voltage
Operating Supply Current
RAM Supply Requirements
Minimum Instruction Cycle Time

The IN lines of the COP420L are not used in this
design but could be used to interface more memory
control keys. There is available space in RAM to
store additional seat positions if desired..

4.5V-9.5V
BmA(max)
3mA(max)@ 3.3V
161-'s

The CKO pin is used· to provide power to the on·chip
RAM in order to retain seat position Information
when the ignition switch is turned off. Power to the
controller and other components is removed in this
condition to minimize current drain on the
automobile battery.

Figure 3.

seat position sensor information. The selection of
the L lines as inputs or outputs is done through
software control and a Do line controls the operation
of the TRI·STATE buffer to coordinate the reading of
sensor information or outputting motor control
information. The 0 1 line controls the operation of the
TRI·STATE latch. The G l - 3 lines are used to detect
closure of the memory control keys. Pressing 1
preceded by pressing SET will store the present seat
position in memory location 1 and pressing 2
preceded by SET will store position information in
memory location 2. Pressing 1 or 2 without first
pressing SET will cause the seat to adjust to the
respective previously stored position. The remaining
Go line is used to detect the car's ignition being
turned off so the seat can be moved back to allow
easy exit from the car.

System Power Supply
Careful consideration must be given to designing
power supply circuitry for automotive electronic
systems. Adequate protection must be provided
against the electrical transients present in the
automotive electrical system. These transients are
listed in Figure 4. In addition to these transients,
there exists the possibility of 2·battery jumps (+24 V)
and reversed 2·battery jumps (-24V). All of these
must be protected against for reliable operation.
National Semiconductor's LM2930 was specifically
designed for supply regulation in automotive electric
systems. Its electrical characteristics are listed in

2-152

Load Dump
Inductive Load Switching
Mutual Coupling

Max Operating Input Voltage
Over·Voltage Protection
Output Voltage
6V" VIN " 26V, 5mA" 10 " 200mA
Line Regulation
6V" VIN " 26V
Load Regulation
5mA" 10 " 200mA
Dropout Voltage
10=200mA

50V T=200ms
±250V T= 1 ms
±450V T=0.1fAs

Figure 4. Automotive Transients

26V
40V
4.5V-5.5V
80mVmax
50mVmax
0.6Vmax

Figure 5. LM2930 Speclllcations

R4
VR
r--~~-~~--~~~CKO

41
SI
Ll
Rl
BATIERY >-TTTT"I-.IVII'v-+-I

,....+_---+_-I Vee

GROUND~

COP420L

t-------------~GO
R7

IGNITION

>----"VI.I'v---......-_-t:"
47K.

Figure 6. Power Supply Circuitry

delayed by R4 and C4 and therefore the serial
register is loaded with "zeros" and'the RAM and seat
are initialized. C3 then charges up and turns' off 01
and 02 and the system returns to standby. (Note: The
values of the timing components have been estab·
lished experimentally.)

Figure 5. This part is Internally protected against
reverse battery installation and 2·battery jumps.
Therefore, all that is needed is to protect the part
from input voltages over 40V. This is easily done with
an R·L·C circuit. Designing for load dump protection
will give protection against the larger but faster
transients.
In order to minimize battery drain, Vee is turned off to
all the circuitry except for the COP's RAM when the
Ignition Is turned off. Refer to Figure 6. When the
Ignition Is on, 03 provides drive to 01 and 02. 01
also holds Go low. When the Ignition Is turned off, the
program software detects the low on Go being
released and performs a routine to park the seat. Vee
is supplied to the controller and circuitry until C3
charges up through .R2 to turn off 01 and 02,
allowing sufficient time for the seat to reach its
parked position. Each time Vce Is turned. on, the
program software checks the contents of the serial
register to see if power to the RAM has been lost. If
the serial register Is all "ones," power has not been
lost. If the contents are all "zeros," RAM power has
been lost and the RAM and seat are Initialized.

System Interface - Output
The 8 different directions of movement of the seat
are provided by 4 drive motors. These 8 directions
are:
A - Tilt Seai Back Rearward
A' - Tilt Seat Back Forward
B -

Move Seat Backward

B' -

Move Seat Forward

C -

Front of the Seat Up

C' -

Front of the Seat Down

D -

Rear of the Seat Up

D' -

Rear of the Seat Down

The motors that move the seat typically draw 2 amps
each when running, but draw up to 10 amps each
when stalled. The motors also require bidirectional

This procedure also occurs if the car battery has
been disconnected. When it is reconnected, C3 is
Initially discharged and turns on 01 and 02. VA Is

2·153

o

o"'tJ

...aJOr

......
......

,....
,....

-.-..
.

CI)

m

a..

oo

drive to operate them bo.th in forward and reyerse.
For these reasons, relays were chosen over semicon·
ductors for the interface .

It is not necessary in this approach to keep a
constant account of the seat's position since it can
be determined at any time by pOlling the
potentiometer sensors. The software is therefore
much simplified and allows the use of a COP410L
which has one-half the memory sizes of the
COP420L. The signal conditiOning circuitry for the
digital sensors that was described earlier is also
eliminated. These two things plus the lower cost for
potentiometer sensors result in an overall system
cost advantage.

A high voltage open collector buffer is used· to
energize the desired relay from the niotor control
bus. Zener diodes are necessary from the collectors
to ground to clamp the inductive turn-off transient to
a ·voltage below the BVCEO of the transistor: These
diodes also provide protection for the buffers against
load dump and the other transients on the battery
supply line.

System Interface - Input

CONSOLE SWITCHES

For the controller to be able to store a seat position
in memory and then later to adjust the seat to that
position, it is necessary for the controller to !<
C

LL

~

AC Test Circuit and Switching Time Waveforms
w
TEST
POINT
RL
1.66k

I

25k'

100pF*

* Includes jig capacitance

2.iJv
ADDRESS

------:--""'\x
~

O.BV

CHIP

SEl:~~

X

ADDRESS VALID

"------------------'

-----------""X

CHIP SELECT VALID

O.BV ----------~

X

-<_,'--_____

__-_ _
- __
-_ _
TR_I_.S_L_A_TE_®_-_-I-_-___

_ t AC

-!

l-t

2.0V

--------------.X

O.BV

OFF

D_A_T_A_V_A_L_ID_ _ _ _ _

FIGURE 1. Address Precedes Chip Select

ADDRESS

-!...JI- ~

'-----:---

VOH

OUT~~:

....- - - - -

.

X

'--------------'

.....- - - -

DATA VALID

FIGl,IRE2. Address Follows Chip Select

Functional Description
The chip is selected by applying the proper logic levels
to the 3·chip select pins. A 7·bit binary word must be
present at the character address inputs, AD-A6 to select'
a character. The dot matrix of selected characters is
generated by cycling the line count address inputs LD-L3
through the line counts necessary to generate the characters. A dot is generated when an output is a "1"
(at VOH).

Figure 3 shows an example of the conditions required at

the address and line count pins to generate the dot niatrix
of the character A. Figures 5 and 6 show the character
fonts of the MM52116FDW and MM52116FDX.

3·8

Functional Description

(Continued)
LD Ll L2 LJ
01 (LSB)

AD

02

Al

OJ

A2

05

A4

06

AS

07 (MSB)

A6

,ffi

CHIP SELECT
CS1 CS2 CS3
0

0

0

VIDEO OUTPUT

CS2 CSJ

CHARACTER ADDRESS
A6-"':' -A4 A 3 - - - 0

DOT
SHIFT
REGISTER

04

AJ

0

AO

'0

L3

LINE COUNT
L2
L1
LO

0

0

0

0
0,

0

0

0

0

0

-

- - 01

0

1
0

1

1

0

0

0

0

0

0
0

DOT MATRIX

07 - - - - -

1
0

1

1

1

0

0

0

Note. A "I" = VIH for address,line count and chip select inputs and a"'" = VOH for outputs.

FIGURE 3. Example of Generating the Character A
PERIPHERAL
INTERFACE

VIDEO
INTERFACE

I

I
ITO

I
DATA BUS

1--1r"---T'"-------..,..------I ATTRIBUTE
DECODE
I
I
I
I
I

MICRO
PROCESSOR

I
I
I
D~~~~~ I

r-_~=:-!:':.'~I}
SYSTEM CONTROL BUS

Xl

X2

FIGURE 4. Typical MM52116FDW and MM52116FDX Application

3·9

J.TERMINAL
MONITOR

~

LL

Functional Description

(Continued)
~~~~--.--.,--.--.---.--.---+--.

,...

CD
,...

.~

.:E
:E

;i

'Q
LL
CD

,...
,...
N

II)

:E
:E

AS

t-=-t==--+

Functional Description

3:
3:

(Continued)

Al AO

U1
000

AS

001

010

011

100

AS A4

101

110

111

........N

0)

"

~

3:
3:
U1

........N

0)

"C><

FIGURE 6. MM52116FDX

3·11

o><

Functional Description (Continued)

LL

CD
,....
,....
C\I

Lt)

::E
::E

3o
LL

CD
,....
,....

~

::E
::E

MM52116FDX ASCII CHARACTER SET IN HEXADECIMAL REPRESENTATION

Character
NUL
SOH
STX
ETX
EOT
ENO
ACK
BEL
BS
HT
LF
VT
FF
CR
SO
SI
OLE
OCl
OC2
OC3
OC4
NAK
SYN
ETB
CAN
EM
SUB
ESC
FS
GS
RS
US

l·Bit
Hexadecimal
Number
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
10
11
12
13
14
15
. 16
17
18
19
lA
1B
1C

"

"-

Character
SP
!

"

#
$
%

&
(

.
)

+

/

0
1
2
3
4

5
6
7
8
9
:

;

<

10

;

lE
IF

>
?

l·Bit
Hexadecimal
Number
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
20
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
30
3E
3F

Character
@

A
B
C
0
E
F
G
H
I
J

K
L
M
N
0

P
0

R
S
T
U
V
W

X
Y
Z
[

\
1

t
<-

3·12

l·Bit
Hexadecimal
Number
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
40
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
50
5E
5F

Character
\

l·Bit
Hexadecimal
Number

q

60
61
62
63
64
65
66
67
68
69
6A
6B
6C
60
6E.
6F
10
71

r

72

s

v

73
74
75
76

w

77

x

78
79
7A
7B
7C

a
b
c

d
e
f

9
h

i
j
k

I
m

n
0

p

t
u

y

z

ALT
ESC
OEL,RUBOUT

7D

7E
7F

MaS/ROMs

~National

~ Semiconductor
MM52132 32,768· Bit (4096 x 8) MAXI·ROM™
General Description

Features

The MM52132 is a static MOS 32)68-bit read-only
memory organized in a 4096-word-by-8-bit format.
It is fabricated using N-channel enhancement and
depletion-mode technology which provides complete
DTL!TTL compatibility and single power-supply operation.

• Fully decoded
• Single 5V power supply ±10% tolerance
• Inputs and outputs TTL compatible
• Outputs drive 2 TTL loads and 100 pF
• Static operation
• TRI-STATE outputs for bus interface
• Programmable chip selects
• 4096-word-by-8-bit organization
• Maximum access time - 450 ns
• Industry standard pin outs

Two programmable chip selects controlling the TR 1STATE® outputs allow for memory expansion.
Programming of the memory array and chip-select
active levels is accompiished by changing two masks
during fabrication.

Applications
• Microprocessor instruction store
• Control logic
• Table look·up

Block and Connection Diagrams

Dual-In-Line Package
01

24

A1
02
03

22 A9

A'

D.
ROM

RDWDECODE

OUTPUT BUFfER

ARRAY

21
A'
A3

0'

A2

01

A1

CSI

"
18

roc

rNO
A,

A9

A10

All

W
CSI

3-13

AIO
All

11

AO

DEC.

CS2

2Q

0'

O'

V"

23 A8

A6

16

01

O'01

02 10

15 06

OJ

14 05

11

13

GNO 12

D.

TOPVIEW

CS2

Order Number MM52132D
See NS Package D24C
Order Number MM52132N
See NS Package N24B

Absolute Maximum Ratings

Operating Conditions

(Note 1)

-0.5V to +7.0V
-65°C to +150°C
Storage Temperature Range
Power Dissipation
lW
300°C
Lead Temperature (Soldering, 10 seconds)

Voltage at Any Pin

O°C to +70°C

Operating Temperature Range

DC Electrical Characteristics
(TA within operating temperature range, VCC = 5V ±10, unless otherwise specified).

PARAMETER
(Note 2)
III

Input Current

VIH

Logical "1" Input Voltage

VIL

' Logical "0" Input Voltage

CONDITIONS

MIN

TYP
(Note 4)

MAX

VIN = 0 to VCC

10
2

VCC+l.0

-0.5

VOH

Logical "1" Output Voltage

IOH = -400 flA

VOL

Logical "0" Output Voltage

IOL = 3,2 mA

ILOH

Output Leakage Current

'VOUT = VCC Chip Deselected

ILOL

Output Leakage Current

VOUT =OV, Chip Deselected

ICCl

Power Supply Current

All Inputs = VCC, Data

UNITS
flA
V

0.8

V

OA

V

10

flA

130

mA

2A

V

-10

flA
100

Output Open

Capacitance
PARAMETER
(Note 3)
CIN

CONDITIONS

Input Capacitance IAII Inputs)

MIN

TYP
(Note 4)

VIN = OV, TA = 25 u C,

MAX

UNITS

7.5

pF

15.0

pF

f = 1 MHz. INote 2)
COUT

Output Capacitance

VOUT = OV, TA = 25°C,
f = 1 MHz, INote 2)

AC Electrical Characteristics
(TA within operating temperature range, VCC = 5V ±10%, unless otherwise specified). See AC test circuit and switching time
waveforms;

CONDITIONS

PARAMETER
tAC

Chip Select Access Time

tOFF

Output Turn OFF Delay

tA

Address Access Time

MIN

TYP
(Note 4)

MAX

UNITS

See AC Test Circuit. All Times IExcept tOFF)

150

ns

Measured to 1.5V Level with tr and tf of

150

ns

450

ns

Input < 20 ns, (Figures 1 and 2), tOFFTRI-STATE
Output Level Measured to Less than ±20 flA
Output Current

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed, Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.

Note 2: Positive true logic notation is used: logical "1" = most positive voltage level, logical "0"'= most negative voltage level.
Note 3: Capacitance is guaranteed by periodic testing.
Note 4: Typical values are for TA::O 25°C and nominal supply Voltage.

·3-14

AC Test Circuit and Switching Time Waveforms
SV

TEST
POINT

I.SV

:::~

O.4V

2.4V
CHIP SELECT

100"*1' ,:,'"

>C

ADO:E::~l

2.4V
ADDRESS

RL
1.66K

CHIPSELEI:T - - . / \

,

O4V

tOFFI-

,-----.1
OUTPUT
-";;;';':';';';';'--+-'-Ac--C

.

CHIPSELEC:~

DOY ___

DOY

~-+---'A-=--~------

OUTPlJT __'; ;.AI",sr",A'.; .'_+-__-(
!~_-J
lAC

*Includes jig capacitance

FIGURE 1. Address Precedes Chip Select

FIGURE 2. Address Follows Chip Select

ROM Programming Information
ROM programs for the MM52164 can be. supplied to
National by a number of means.

ternally via a sophisticated computerized system. The
original input device (PROM, tape, etc.) is read, the data
is reprocessed to formats required by various· production machines, and the final reconstructed data is then
compared back to the original input device.

A. 2708 PROM sets
B. 2516 PROM (or equivalent)
C. 2716 PROM (or equivalent)

The verification package returned to the customer for
approval will consist of a listing of the program and a
PROM or tape which matches the data National will use
to create the programmed MM52164. In a normal situation, the verification package returned to the customer for
approval, because of the system described, may consist
of the original PROM or tape submitted by the customer.
This program data, now in National's production format, is stored in archives for future customer re-orders.

D. Intellec HEX punched paper tape
E. Binary punched paper tape
Since the MM52164 has programmable chip selects, it
is imperative that chip select information be provided
along with the ROM program. The information should be
supplied as shown:
CS1 is to be programmedlogical_.__ (Hi or Lo)
Given any of the above means of program data is received
by National, verification of ROM programs is handled in·

3-18

MOS/ROMs

'?A National

PRELIMINARY

~ Semiconductor

MM52264 MAXI·ROM™ 65,536-Bit Clocked
Read Only Memory
General Description
The MM52264 is a clocked MOS 65,536-bit read-only
memory organized in an B192-word-by-B-bit format.
It is fabricated using N-channel enhancement and
depletion·mode technology which provides complete
DTL/TTL compatibility and single 5V power supply
operation.

The MM52264 was designed for those ROM applications
requiring fast access time and low power dissipation.
Dynamic circuitry has been used extensively to reduce
access time. The utilization of a clock input allows
the device to be put into a low power standby mode
during inactive periods. The device is put into the
standby mode by maintaining the clock input CE
at an input "1" voltage. CE must be maintained at
a "1" voltage for the minimum specified time (tp)
to allow for adequate precharging of the internal dynamic circuitry.

A read operation is initiated and address data are latched
by bringing CE to an input "0" voltage. The falling·edge
of CE triggers the generation of a series of internal clock
signals which decode addresses into row and column
lines and enable output sense amplifiers and buffers.
Since the address is latched in address buffers, the input
address data can be changed during a read operation
after the address·hold·time (tAH) specification is met.

Power dissipation increases during a read operation;
however, once the output data are latched in the TRISTATE® output buffers, most of the dynamic circuitry is automatically switched off to conserve power.
The output data remain
tained at a "0" voltage
voltage level returns the
and all data outputs to

valid as long as CE is
level. Switching CE to
device to the standby
a high·impedance OFF

main·
a "1"
mode
state.

Features
• Fully decoded
• Single 5V power supply ±1 0% tolerance
• Inputs and outputs TTL compatible
• Outputs drive 2 TTL loads and 100 pF
• Clocked operation
• TRI·STATE outputs for bus interface
• 8 192-word-by·B-bit organization
• 300 ns maximum access time
• Industry standard pin outs

Applications
•

Microprocessor instruction store

• Control logic
• Table look-up

Block and Connection Diagrams
Dual-In-Line Package

" Vee

Al

1]

A'
ADDRESS
LATCHES
AND

A'

SUfFERI
INVERHRS

M

AB

22 A9

"

A12

20_

A'a-.

CE

A3

Ala-.

19 AID

A1
ABa-.

1B

A1
A9a-.

17

AD

16

D1
D2

A12

! !

Vee

GND

03
Ot

02 OJ 04 05 06 01 DB

GND

10

15

11

J3

12

TOI'VIEW

3-19

All

DB
07
DO

0'
0'

Absolute Maximum Ratings

Operating Conditions

(Note 1)

Voltage at Any Pin
-0.5V to +6.5V
Storage Temperature Range
-65°C to +150°C
Power Dissipation
lW
Lead Temperature (Soldering, 10 seconds 1
300°C

Operating Temperature Range

O°C to +70°C

DC Electrical Characteristics
= 5V ±10%, unless otherwise specifiedl.

(T A within operating temperature range, VCC
PARAMETER
(Note 21

CONDITIONS

MIN

MAX

= 0 to VCC

III

Input Current

VIH

Logical "1" Input Voltage

2.0

VIL

Logical "0" Input Voltage

-0.5

VIN

TYP
(Note 41

UNITS

±10

VOH

Logical "1" Output Voltage

IOH

=

-200J.1A

VOL

Logical "0" Output Voltage

IOL

=

3.2 mA

ILOH

Output Leakage Current

VOUT

=

4V, Chip Deselected

ILOL

Output Leakage Current

VOUT

=

0.45V, Chip Deselected

ICCl

Power Supply Standby Current

All Inputs

ICC2

Power Supply Active Current

J.1A

VCC+1.0

V

0.8

V

2.4

V
0.4

V

10

J.1A

10

15

mA

30

50

mA

MAX

UNITS

-10

= 5.25V, Data

J.1A

Output Open

Capacitance
PARAMETER
(Note 31
CIN

CONDITIONS

Input Capacitance (All Inputsl

VIN
f

COUT

Output Capacitance

=

=

=

=

TYP
(Note 41

25 u C,

7.5

pF

15.0

pF

1 MHz

VOUT
f

OV, TA

MIN

=

OV, T A

=

25 u C,

1 MHz

AC Electrical Characteristics
(T A within operating temperature range, VCC
waveforms.

PARAMETER
tc

= 5V

±10%, unless otherwise specifiedl. See AC test circuit and switching time

CONDITIONS

CE Cycle Time

See AC Test Circuit and Figure 1.

MIN

TYP
(Note 41

MAX

UNITS

450

ns

All Times (Except tOFFI
tp

CE Precharge Time

150

ns

tCE

CE Pulse Width

300

ns

0

ns

50

ns

tAS

-

Address to CE Setup
Time

tAH

Address Hold Time
from CE

tAC

-

CE to Output Access

300

ns

150

ns

Time
tOFF

Output Turn OFF

AC Test Circuit Load Removed

Delay

Measured to 1.5V TRI-STATE
Level with tr and tf of Input < 20 ns

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.

Note 2: Positive true logic notation is used: logical "1":0 most positive voltage level, logical "0"
Note 3: Capacitance is guaranteed by periodic testing.

Note 4: Typical values are for TA

'=

25°C and nominal supply voltage.

3-20

= most negative voltage level.

AC Test Circuit and Switching Time Waveforms
Vee
TEST
POINT
RL
1.66K

ADDRESS

' '=--i

OUTPUT - - - - - " D P . ; ; E " ' - ____
- - -._
i

*Includes jig capacitance

~

VALID 'OFF
OUTPUT
}_
- _ _ _!!!DP!!EN=---_ __

FIGURE 1. AC Electrical Waveforms

Custom MAXI-ROM Programming
sponding to address 0000 through 1023 are in an
MM2708 designated "A;" output words corresponding to addresses 1024 through ,2047 are in an
MM2708 designated "B."

So that National can better serve its customers, we
will honor a variety of program format packages. They
, are, beginning with the m'ost desirable, listed below:
MM2708 or MM2716 EPROM FORMAT

c. The pair of MM270Bs containing a custom program
must be labeled (stickers" paint, etc.) with a number
corresponding to the program and a letter designating
which block of output words it contains. For example, assume three MM2316E custom programs.
There would be six MM2708s sent to NSC. They
would have labels o~them of:

The MM2708 or MM2716 EPROM is used either singly
or in combinations to support larger programs such as:
8 - MM2708 for 1·64k ROM
2..,. MM2716 for 1·32k ROM
2 - MM2708 for 1·16k ROM

lA
lB

etc.
Positive Logic is Preferred: Positive logic is defined as
follows: a logic "1" is the, most positive voltage level
and a logiC "0" is the most negative voltage level. When
this definition is applied to the MM2316E and the
MM2708, the following definitions result:

2A
2B

3A
3B

PAPER TAPE FORMAT
The paper tape which should be used is 1" wide paper
using 7 or a-bit ASCII code (such as a Model 33 ASR
Teletype produces).

A "1" = VIH for addresses and chip selects.
A "1" = VOH for outputs.

HEX PAPER TAPE FORMAT

A "0" = VIL for addresses and chip selects.

In the Hex Format, a data field contains,8·bit data. Two
ASCII hexadecimal characters must be used to represent 8-bit data.

A "0" = VOL for outputs.
This logic definition must be used for all pins on both
device types. Any other logic definition (or combi·
nation of definitions) will result in delays and additional
data processing steps and should be avoided.

Preceding the first data field and following the last
data field there must be a leader/trailer length of at
least 25 null characters. Comments (except for a colon)
may be placed on the tape leader.

Serialization-Identification (A Must): Two MM270B
EPROMs are required to store a custom'program for a
MM2316E ROM. Several custom 'programs may be
included in a single order. The following 'method of
serializing, identifying, and labeling is required to keep
everything clearly defined:

The format described below is readily generated by the
National Mask Programmi~g System (MPS) or by systems programmed by the user.
Record Mark Field: Frame 0 The ASCII code for a
colon (:) is used to signal the start of a record.

a. Each custom program (pattern) is numerically serialized 1, 2, 3, ... n.

Record Length Field: Frames 1 and 2 The number of
data bytes in the record is represented by 2 ASCII
hexadecimal digits in this field. The high-order digit
is in frame 1. The maximum number of data bytes
in a record is 255 (F F in hexadecimal). An end-offile record contains 2 ASCII zeros in this field.

b. The two MM2708s storing' a custom program are
designated "A" for the first block of 1024 output
words and "B" for the second block of 1024 output
words. Stated another way: output words corre-

3-21

Custom MAXI-ROM Programming

(Continued)

Load Address· Field: Frames 3-6 The 4 ASCII hexadecimal digits in frames 3-6 give the address at which
the data is loaded. The high·order digit is in frame 3,
the lower-order .digit in frame 6. The first data byte is
stored· in the· location indicated by the load address;
successive bytes are stored in successive memory locations. This field in an end-of-file record contains zeros
or the starting address of the program.
Record Type Field: Frames 7 and 8 The 2 ASCII hexadecimal digits in this field specify the record type.
The high-order digit is in frame 7. All data records
are type 0; end-of-file records are type 1. Other possible values for this field are reserved for future expansion.
Data Field: Frames 9 to 9 + 2 (record length) - 1
A data byte is represented by 2 frames containing the
ASCII characters 0-9 or A-F, which represent a hexadecimal value between 0 and FF (0 and 255 decimal).
The high-order digit is in the first frame of each r;>air,
If the data is 4-bit, then either the high or low-order
digit represents the data and the other digit of the pai r
may be any ASCII hexadecimal digit. There are no
data bytes in an end-of-file record_
Checksum Field:· Frames 9 + 2 (record length) to 9 +
2 (record length) + 1 The checksum field contairis
the ASCII hexadecimal representation of the two's
complement of the 8-bit sum of the 8-bit bytes that
result from converting each pair of ASCII hexadecimal
digits t~ 1 byte of biliary, from the record length field
to and including the last byte of the data field_ Therefore, the sum of all the ASCII pairs in a record after

converting to binary, from the record length field to
and including the checksum field, is zero.
Hex Example:
:10310000311A320E03117E31CD40003A9231B7C2EE
: 103'1100060310E00117031 CD40003A9231 B7C2607B
: 10312000312A7E31227A310E03117E31.CD40003ABO
: 103130009231 B7C260312A8C317CB5CA5031 OE044D
:10314000118831CD40003A9231B7C26031C327186
:103150000E01117A31CD40000E09119031CD4000A1
:103160000EOC119231CD40000E09119031CD40006E
:OA3.170007E31963101 00000092311 B
:10317C0092310100963180008C31923100009631F1
:04318E0092319231B7
:02319400923176
:00310001CE

Hardware Verification
When the custom program is submitted to NSC in a
PROM or EPROM, the customer will receive both
a verification listing and a duplicate of the ()riginal
units_ The: customer can use software (the listing)
or the PROMs to verify the program_ These PROMs
have been programmed and tested with tapes generated
by the NSC Mask Programming System (MPS). He
will be asked for a Go/No Go response within a week
after receipt of the verification package, listing ·and
PROM set.
Note that blank 16k bit PROMs for program verification must be supplied by customer, and must be pin
compatible to coinciding ROM.

Tape Format Illustrations
HEX TAPE FORMAT

• •• ••••• •
•
• •• •• • •
•
••
•
•
.•.......•..........•••.•.................•...•...•........•

••••••••••••••••••••• ••••••••••••••••••••• • ••• •••••••••••
•••••••••••••••••••• ••••••••••••••••••••• • •••••••••••
•••• • •
•
• ••• •
STANDARDS·BIT BINARY

r-------------,
o

. - - - - - - - - - : : - - - - - - , _ 8 I T lILS8)

0 '0

o0

0 0

.................
o0

o0

0 0

• • • • • • • • • • • • • • • • • • • •

~OO

~oo

I
I
I
I
I
I
I
I

OUTPUT
WORD

I-----r-:i-r----~ '-________..;...._°r-.__..........:..SIT S IMSS)

+

LWORD N·lIADDRESSN·ll
LWDRD N·2IADDRESS N·2)

Note: Start with a RUBOUT and enter the output words in sequence from word 0 (address OJ to word N - 1 (address N

~

1). There

must not be any other characters on the tape. The order information must indicate whether a pun~h equals,"O" or "1," THIS IS THE
LEAST RELIABLE FORMAT. IT HAS NO ERROR CHECKING AND SHOULD BE AVOIDED IF AT ALL POSSIBLE.

3·22

Section 4
Speech Synthesis

Speech Synthesis 2
C)

~National

PRELIMINARY

~ Semiconductor
DIGITALKER™ Speech Synthesis System
General Description

Features

The DIGITALKER is a speech synthesis system consisting
of multiple N-channel MaS integrated circuits_ It contains
a speech processor chip (SPC) and speech RoM and when
used with external filter, amplifier, and speaker, produces
a system which generates high quality speech including
the natural inflection and emphasis of the original speech.
Male, female, and children's voices can be synthesized.

• Designed to be easily interfaced to most popular
microprocessors
•
II
•
•
•

The SPC communicates with the speech ROM, which contains the compressed speech data as well as the frequency and amplitude data required for speech output. Up to
128k bits of speech data can be directly accessed. This
can be expanded with minimal external logic.

• TIL compatible
• MICROBUSTM compatible
• On-chip switch debounce for interfacing to manual
switches independent of a microprocessor
• Easily expandable to greater than 128k ROM
• Interrupt capability for cascading words or phrases
• Crystal controlled or externally driven oscillator
• Ability to store silence durations for timing sequences

With the addition of an external resistor, on-chip debounce is provided for use with a switch interface.
An interrupt is generated at the end of each speech sequence so that several sequences or words can be
cascaded to form different speech expressions.

• Consumer products

• Appliance
• Automotive
• Teaching aids

• Clocks
• Language translation
• Annunciators

7-11V

1M

---VSS

VSS

SPC

DATA BUS

ROATA 1-8

SPEECH

OSC
IN

OSC
OUT

SPEECH
ROM

CHIP ENABlE*

ROMEN

":'

."'--'
I
I

VCC

ADDRESS BUS

ADR 1-14

Cl'

1
1
.1

_______ J

1.5k
1M

* Only required for clocked
dynamic ROMs

FILTER AND
AMPLIFIER
OIGITALKER is a trademark 01 National Semiconductor Corp
MICROBUS IS a trademark of National Semiconductor Corp.

4-3

SPEAKER

(J)

"C
CD
CD

n

::::r

~
:::s

~
::::r
CD
en

en"

3

• Telecommunications

Minimum Configuration Using Switch Interface'

VDD

"

m
:c

CD

Applications

Encoding (digitizing) of custom word or phrase lists must
be done by National Semiconductor. Customers submit to
the factory high quality recorded magnetic reel to reel
tapes containing the words or phrases to be encoded.
National Semiconductor will sell kits consisting of the
SPC and ROM(s) containing the digitized word or phrases.

Typical Applications

256 possible addressable expressions
Male, female, and children's voices
Natural inflection and emphasis of original speech
Addresses 128k of ROM directly
Communicates with static or clocked dynamic ROMs

i!r-

DlGITAlKER
Klr

Absolute Maximum Ratings
- 65·C to + 150·C
0·Ct070·C
12V

Storage Temperature Range
Operating Temperature Range
Voo-Vss

12V

Voltage at Any Pin
Operating Voltage Range,Voo-Vss
. Lead Temperature (Soldering, 10 seoonds)

7Vt011V
300·C

DC Electrical Characteristics TA = o·c to 70·C, vo~ = 7V-11V, Vss = OV, unless otherwise specified.
Symbol

,

,

' Conditions

Parameter

Min

ryp

Max

Units
V

VIL

Input Low Voltage

-0.3

0.8

VIH

Input High Voltage

2.0

Voo

V

VOL

Output Low Voltage.

IOL=1,6 mA

0.4

V

10H= -100p.A

2.4

5.0

V

-0.3

0.6

V

4.0

Voo

V

50

mA

Input Leakage

±10

p.A

IILX

Clock Input Leakage

±10

p.A

Vs

Silence Voltage

VOUT

Peak to Peak Speech Output

VOH

Output High Voltage

VILX

Clock Input LowVoltage

VIHX

Clock Input High Voltage

100

Power Supply Current

IlL

Voo= 11V

0.45Voo

V

2.0

V

.',-

.;'

, AC Electrical Characte~istics TA = o~c to WC, Voo = 7V-11V, Vss = OV, unless otherwise specified.
Symbol

Max

Min

Parameter

Units

taw

CMS Valid to Write Strobe

350

ns

tcsw

Chip Select ON to Write Strobe

310

ns

tdw

Data Bus Valid to Write Strobe

50

ns

twa

CMS I:fold Time after Write Strobe

50

ns

t wd

Data Bus Hold Time after Write Strobe

100

ns

tww

Write Strobe Width (50% Point)

430

t,ed

\,!OMEN ON to Valid ROM Data

twss

Write Strobe to Speech Output Delay

ft

External Clock Frequency TOlerance

ns

Timing Waveforms
Command Sequence

~'.

P.s

410

P.s

±2

Note: Rise and fall times (iO% to 90%) of MICROBUS signals should be 50 ns maximum.

CMs=1

2

'VALID

.1

t.w

\

-~t=
tWw-

!esw
Wii

j(dW~
DATA BUS

VALID

(SW1-SWB)

4-4

-\or

%

2

Timing Waveforms (Continued)

C)

i!r-

ROM Data Timing

ADRl_14~1

"m

VALID ADDRESS

~~I----------------------------------

l::J

C/J

_________

"C
CD
CD

~--------tR-E_O~~-----------------~

ROM DATA 1-8

VALID DATA

n

=r

!R
::::s

~
-

Crystal Circuit Information

=r
CD

Typical Crystal Oscillator Network

en
_.

External Clock Input (4.0 MHz)

UI

SPC

VOO

EXTERNAL __,
CLOCK

"'R"'2"v-+--------......... i~RCUIT

~cz
Crystal

Rt

R2

Cl

C2

4.0 MHz

1M

1.Sk

10·30 pF

40·60 pF

st

r-

...---4......

SPC

CD

3

CIRCUIT

. lO
Timing

Min Units

IXH

100

ns

tXL

100

ns

Block and Connection Diagrams
Dual·ln·Line Package

ADR 1-14

40

OSC IN

39

OSC OUl

38

os

37

We

36

ADMEN

35

INlR

34

CMS

33

SW 8 (MS8)

J2

SW7
SW6

11

SW5
SW4
SW3
SW2
OSC IN

SW 1tlS8)
ROAlA 1tlS8)

OSC OUl
ADMEN

RDATA 2

ROAlA 3
ROAlA 4

SPEECH OUl

31

10

VSS

SPC

29

13

28

14

27

15

26

16

25

17

24

18

23

19

22

20

21

TOP VIEW

4·5

30

12

VOO
SPEECH OUl
ADA 14 (MSB)

AOR 13
AOR 12
ADR 11

AOR 10
AOR 9
AOR 8
AOR 7
AOR 6
AOR 5
AOR 4
ADR 3

AOR 2
AOR 1 (lS8)
ROAlA 8 (MSB)
ROAlA 7
ROAlA 6
ROAlA 5

E

(I)

Connection Diagrams (Continued) (Vee = 4.75V-5.25V)

U)

t1i
U)

"en
(I)
.c::::

bual-ln·Line Package
24

A7

C

~

(.)
(I)
(I)

Co

tn

a:

W

~
....I

~

e-

C!J

Vee

A7

2'

Vee

A6

23 A8

A6

23 A8

AS

22 A9

AS

22 A9

21 e53

A4

tn

.c::::

Dual·hi·Line Package

A4

20

A3

19

A2
MMS2116
AI

17

AO

16

01
02
03
GNO

18

10

IS

II

I'

12

13

e51

A3

AIO

A2

21
20
19
MMS2132

e52

AI

08

AO

07

01

06

02

05

03

04

GNO

17

16
10

23
22
21
20
19

A2
MMS2164
AI

16

01

03
GNO

06

04

2'

' A7

Vee

23

A6

AS
A9

22

AS

AI2

21

A4

e51

20

A3

AID

19

A2

Vee
A8
A9
AI2

CE
AID

MMS2264
18
17

AD

07

Dual·ln·Line Package
2'

A3

08

I' 05

32k

A4

All

13

16k

AS

AIO

II

TOP VIEW

A6

e51

12

Dual·ln·Line Package

02

IS

TOP VIEW

A7

18

e52

10

IS

11

I'

12

13

All

18

AI

08

AD

07

01

06

02

05

03

04

GNO

17
16

07

15

II

I' 05

12

13

TOP VIEW

64k

64k "Clocked"

4·6

08

10

TOP VIEW

For specific ROM device information, see MM52116, MM52132. MM52164orMM52264 data sheets.

All

06

04

c
is

Functional Description
The following describes the function of all SPC input and
output pins.

ROM Data (RDATA 1-8): This is an 8·bit parallel data bus
which contains the speech data from the speech ROM.
OUTPUT SIGNALS
Interrupt (INTR): This signal goes high at the completion
of any speech sequence. It is reset by the next valid com·
mand.lt is also reset at power up.

INPUT SIGNALS
Chip Select (05): The SPC is selected when CS is low. It is
only necessary to have CS low during a command to the
SPC. It is not necessary to hold CS low for the duration of
the speech data..

ROM Address (ADR1-ADR14): This is a 14·bit parallel bus
that supplies the address of the speech data to the speech
ROM.

Data Bus (SW 1-8): This is an 8·bit parallel data bus which
contains the starting address of the speech data.

ROM Enable (ROMEN): This line is for use with clocked
dynamic ROMs. When used, the high to low transition
must cause the speech ROM to generate a cycle and place
the speech data on the RDATA lines. Data must remain on
the RDATA lines while ROMEN is low. For low power
applications, this line can. be used to drive a transistor that
switches the supply for static speech ROMs. See ROM
data timing.

Command Select (CMS): This line is used to define the
two commandos to the SPC.
CMS

o

1

Function
Reset interrupt and start speech sequence
Reset interrupt only

Speech Output (Speech Out): This is the analog output
that represents the speech data. See frequency response
section.

Write Strobe (WR): This line latches the starting address
(SW1-SW8) into a register. On the riSing edge of the WR,
the SPC starts execution of the command specified by
CMS. The command sequence is shown in the timing
waveform section. If a command to start a new speech se·
quence is issued during a speech sequence, the new
speech sequence will be started immediately.

INPUT/OUTPUT SIGNALS
Clock Input/Output (OSCIN, OSCOUT): These two pins
connect the main timing reference (crystal) to the SPC.

Applications Information
Frequency Response of Combined Amplifier and Speaker

/'

.........

/

......
...... 1...

V
'"
~

-20

z

;;:

.,'"
w

>

~

a:

-40

/

lL

/

/'~

111120 dB/DECADE
"

.J..+tI NOTE 1

r-j'-..........

60 dB/DECADE

~
40 dB/DECADE
NOTE 2

lk

100

f'.

,:DTE3jf

"

':'60
10

~

r-

Note: In the following descriptions, a low represents a
logic 0 (O.4V nominal), and a high represents a logic 1 (2.4V
nominal).

f\
10k

FREQUENCY (Hz)

Note 1: This curve is the desired response of the entire audio system including speaker.
Minimum response is a lowpass filter with a cutoff frequency of 200 Hz. For an audio system
with a natural cutoff frequency around 200 Hz, this filter can be eliminated. This cutoff fre·
quency may be tuned for the particular voice being synthesized. For a low pitched male voice
it may be 100 Hz, while for ahigh pitched female or child's voice it might be 300 Hz.
Note 2: This is optional filtering that can be eliminated by proper selection of the speaker. If
this 2 pole response is electronically produced, it should be adjusted as described in Note 1.
Note 3: This is optional filtering that can be eliminated for simpler systems. The acceptable
range for this cutoff frequency is 6000 Hz-BOOO Hz.

4·7

"m
:l:J

o

"C
CD
CD
(')

::r

!R
:::s

::r
CD

en

iii"

!R
!L
CD
3

Typical Applications
Complete Applications Schematic for
High Quality Voice Reproduction

l-11V

Low Power Configuration Using Stallc ROM

., .-- -,---,,,-1--......,.,..---,

.......,.,L----."J......,I

Voo

~OO=-;;:07+-+I SW 1-8
t-WR':"R:'-:----~ WR

I-A:::O~H~CMS

AOR 1-14 ~A~O;::OR~E~SS~BFUS:..t

SPC

SPREOE~H

ROATA 1_81+_0:;;.AT;.;A;.;B"US'--f

~I=;""R+-t INTR

ROMEN

I

OSC
OUT

CSSPEECH OSC
OUT
IN

CHIP ENABLE"

I
I
I
I

CE

5V

l-11V

I

Vcc

DIGITAliK£R
KIT

J. voo

I,

L _______, _, ___ J

vss

VCC

Jk

SP::~H

SPC RUMEN

I

L ________ J

* Only required forclocked
dynamic ROMs

Minimum Filter Circuit
VOO
SPEECH (FROM SPC)
OUT

200"Hlj'

+

-

SPEAKER

200 Hz =

* LM346 or equivalent

Filter Circuit to Produce Maximum Frequency Response
VOO
SPEECH (FROM SPC)
OUT

C5

:tI

VOO

'
200"Hrj

+

T

,

'

"

SPEAKER

1

, 7000Hz=

2.-R1Cl
200Hz=

~1_

=

2'-R3C3
* LM346

4-8

or equivalent

2"R2C2
1
2"R4C4

1

2"R5C5

52

Typical Applications (Continued)

G')

;:::i DIGITALKER System Utilizing MICROBUS™ Interface

:t>
r-

,------------,

m

I

"en
:D

I

I

t...;;DO~-~D7;.p_+l SW 1-8
po
WR

"C
CD
CD

DlGITALKER
KIT
OSC
SPEECH IN

o
::::r

OSC
OUT

~
::::J

~
::::r
en
CD

iii"

U

T

T

CD

3

FIL TER
&

AMPLIFIER

Speech ROM Expansion for Requirements Greater Than 128k

rc

ROMEN*
ROATA 1-8

SPC

"B

ADR14

\

1

ADR 1-13

~

.

1ST MODULE

,

r-

+1

I

+

.

2ND MOOULE

,

\

I

I

+

+

64k
ROM

64k
ROM

64k
ROM

fi4k
ROM

cs

cs

cs

CS

L J

U

S

LSB

--+

1-0F-N
BINARY
OECODER

MOOULE
SELECT
REGISTER

~

b-

f-+
b.

~
4·9

* Only required for clocked
ROMs

Section 5
Standard MOS/LSI

Digital Clock Product Selection Guide
F••tur••

Indicators

Funcllanll

Product
Number

AppllUillons

D~:Y

Dlglla

Input

Time
Mode

Frequency

l!'

1

Output Form

i;:

Not••

J

MM5309

Clock

LEO

4/S

12124 Hrs.

50/60 Hz

MUX 7·Segment

11·19V

2mA

SmA

28

Reset, Output Enable

MM5311

Clock

LEO

41S

12124 Hrs.

50/60 Hz

MUX 7·Segment

11·19V

2mA

SmA

28

Hold, Output Enable

MM5312

Clock

LEO

12124 Hrs.

SOISO Hz

MUX 7-Segment

11·19V

2mA

SmA

24

1 PPS, Output Enable

MM5313

Clock

LEO

41S

12124 Hrs.

salsa Hz

MUX 7-Segment

11·19V

2mA

SmA

28

HOld, 1 PPS

MM5314

Clock

LEO

41S

12124 Hrs.

SO/60Hz

MUX 7·Segment

11·19V

2mA

SmA

24

Hold

MM5315

Clock

LEO

4/S

12124 Hrs.

SO/60Hz

MUX 7-Segment

11·19V

2mA

SmA

28

Reset Hold

MM5316

Clock Radio

VF

12/24 Hrs.

SOfSOHz

Direct 7·Segment

8-29V

a.SmA

40

~~~~~~~~II~~~~~~S ~!~~'

MM5387AA
(MM53108)

Clock Radio

LEO

12124 Hrs.

SO/SO Hz

Direct 7·Segment

8-26V

SmA

40

MM53108 is Mirror Image

MM53110AA

Auto Clock

VF

12 Hrs.

2MHz

MUX 7·Segment

S·28V

2 rnA

SmA

22

Elapse Time (19 Hrs., 59 Mln5.)

MM53110AB

Auto Clock

VF

12 Hrs.

2MHz

MUX 7·Segment

S·28V

2mA

8mA

22

Elapse Time (19 Mins" 59 Sees.)

MM53113

Clock Radio

VF

12124 Hrs.

SO/60Hz

Direct 7·Segment

8-29V

a.SmA

40

Pin-Out Same as MM5316

Elapse Time (24 Hrs.)'

M"'53124

Auto Clock

VF

12124 Hrs.

4MHz

Direct.7·Segment

5.2SV

O.4mA

40

MM53224

Auto Clock

VF

12/24 Hrs.

4MHz

Direct 7·Segment

S.2SV

O.4mA

40

Elapse Time (24 Hrs.)
Mln.lSecs. to HrsJMlns.

MM5402
(MM5405)

Clock Radio

LEO

12/24 Hrs.

SO/SO Hz

Direct 7·Segment

7·11V

10mA

40

MM5405 is Mirror Image

MM54D6

Temperature
Clock Radio

LEO

12/24'Hrs.

SO/60Hz

'Duplex 7·Segment

9-l1V

20mA

40

~~r~~~~I:~~~i~9

MM5407

Digital
Thermometer

LEO

14

~7~~~~~~~~~~:~~~~

MM5455

Clock Radio

LEO

12124 Hrs.

SO/60Hz

Duplex 7·Segment

7·11V

20mA

24

Duplex Display, Alarm Tone

MM5456

Clock

~adlo

LEO

1'2 Hrs.

.SOI6OHz

Duplex 7·Segment

7·l1V

20mA

22

Duplex Display, Alarm Tone

MM54S7

Clock Radio

LEO

12 Hrs.

50Hz

Duplex 7·Segment

7·11V

20mA

22

Duplex Display, Alarm Tone

MM58143
(MM581B3)

Clock Radio

LCD

12124 Hrs.

32.8kHz

Direct 7·Segment

1.5V

5 ....

40

Audlo/Static Alarm Tone,
Available in die form
MM58183 is Mlrtor Image

MM58144
(MM58184)

Travel
Alarm Clock

LCD

12124 Hrs.

32.8kHz

Direct 7·Segment

1.SV

5!IA

40

Voltage Multiplier
AudlOiStatlc Alarm,
MM58184 is Mirror Image

MM7317B

Calendar
Clock Radio

LEO

12124 Hrs.

S0/60Hz

Direct 7·Segment

8·26V

SmA

40

Calendar (Month· Date)

MM73188

Calendar
Clock Radio

LEO

12124 Hrs:

SO/60Hz

Direct 7·Segment

8·26V

SmA

40

Calendar (Month·Date)

9-11V

5·3

Min./Secs. to Hrs./Mins.

Television/Radio Product Selection Guide
Product
Number

Description

Process

I:'ackage
Pins Type

Notes

MM5321

TV Camera Sync Generator

PMOS

16

N/D

Horizontal/Vertical Control, Field Indexing and Color Burst Sync

MM5322

Color Bar Generator

PMOS

16

N/D

16 Patterns, 3.58 MHz Crystal Control

MM53100

Programmable TV Timer

CMOS

24

N

4/6 Digit, 24 Hr., 50/60 Hz Programmable TV "ON" Time, +18V
Reference Voltage ,

MM53105

Programmable TV Timer

CMOS

24

N

4/6 Digit, 24 Hr., 50/60 Hz Progammable TV "ON" Time, OV
Reference Voltage

MM53118AA

TV Digital Tuner

NMOS

28

N

117·Channel, 3 Band + Cable TV, Up/Down or Keyboard Entry,
Complete PLL Frequency Synthesizer

MM5430

AM/FM Radio Frequency Display

NMOS

40

N

AM/FM Frequency Display, 4.19 MHz Crystal or 50/60 Line Oper·
ation, Programmable IF Offset, Direct Interface to LED Display

MM5431

AM/FM Radio Frequency Display, NMOS

40

N

Mirror Image Pin·Out of the MM5430

MM5439

Microprocessor.Compatible PLL

NMOS

40

N

6 Potentiometer Outputs, 6 General Purpose Outputs, TGeneral
Purpose Input/Outputs

MM55108

PLL

Synthesizer

CMOS

18

N

Programmable 29.1 Division, 10.24 MHz Crystal provides 5kHz
Reference Frequency ,

MM55110

PLl:' Frequency Synthesizer

CMOS

24

N

Programmable 29.1 or,2 10·1 Division, 10.24 MHz Crystal
provides 5 kHz or 10 kHz Reference Frequency

MM55121

PLL Frequency Synthesizer

CMOS

16

N

Programmable 213.1 Division, 10.24 MHz Crystal provides 5kHz
Reference Frequency, 320 kHz/300 Hz/60 Hz Buffered Outputs

MM55122

PLL Frequency Synthesizer

CMOS

18

N

Programmab'le 29.1 Division, 10.24MHz Crystal provides 10kHz
Reference, Serial Data, 3 D to A Outputs

MM55123

PLL Frequency Synthesizer

CMOS

16

N

Programmable 213.1 Division, 10.24 MHz Crystal provides 1 kHz
Reference Frequency, 320kHz/300Hz/60Hz Buffered OutPuts

MM55124

PLL Frequency Synthesizer

CMOS

16

N

Programmable 28.1 Division, 5kHz or 10kHz Reference
Frequency

MM55126

PLL Frequency Synthesizer

CMOS

18

N

Programmable 29.1 Division, 5kHz or 10kHz Reference
Frequency

F~equency

MM5837

Digital Noise Source

' PMOS

8

N

White Noise Source

MM5840

TV Channel NumberlTime Display CMOS

28

N

16·Channel, 5/8 Digit, 12124 Hr. Time with Interface to MM53100
or MM53105

MM58106

Digital ClockllV Channel Display CMOS

28

N

,5/8 Digit, Channel (2·83) or Program (1·16) Display, 12/24 Hr.,
50/60 Hz

MM58142

TV Digital Tuner

NMOS

24

N

82·Channel PLL Frequency Synthesizer, Up/Down or Keyboard
Entry, Inteface to the MM58146

MM58146

TV ChannellTime Display

NMOS

22

N

4·Digit, Channel (2·83) Display, 12 Hr. Time, Interface to the
MM58142

MM58313

TV Varactor Tuner Display

CMOS

20

N

PAUNTSC Option, Channel Number Display, Screen Tuning
Bar Graph Scale.

5·4

Games/Calculators Product Selection Guide
Product
Number

Description

Process

Package
Pins
Type

Notes

MM5780

Educational Arithmetic Game

PMOS

24

N

8-Digit, Four-Function (+, -, x, -;0) Algebraic, "Right"/"Wrong"
Indicators

MM57455

Advanced Educational
Arithmetic Game

NMOS

28

N

Four Function (+, -:-' x, -;0) Algebraic, Table/Complex/AmateurPro Modes Interface to Special Format Display (NSA1481)

MM57459

LED Calculator with Memory

NMOS

24

N

8-Digit, 5-Function (+, -, x, -;0, %), Four Function Memory (M+,
M-, MR, MC), Auto Constant, Direct LED Display Interface

5-5

Telecommunication Device Product Selection Guide
Product
Number

Description

Process

Package
Pins
Type

Notes

MM5393

Push Button Pulse Dialer

CMOS

18

MM5394

Push Button Pulse Dialer

CMOS

16

J

Same as MM5393 without Pacifier Tone

MM5395

DTMF (Touch Tone® ) Generator

CMOS

18

N

Eight (8) Audio Output Frequencies from a 3.58 MHz Crystal,
Operation from a 2-of-8 Keypad'

MM53125

DTMF (Touch Tone'" ) Generator

CMOS

18

N

Eight (8) Audio Output Frequencies from a 3.58 MHz Crystal,
Operation from a Single-Contact Keypad

MM53130

DTMF (Touch Tone'" ) Generator

CMOS

18

N

Eight (8) Audio Output Frequencies from a 3.58 MHz Crystal,
BCD/Binary or 2-of-8 Interface Options, Tone Disable, Single/
Dual Tone Mode Select

MM53143

Push Button Pulse Dialer

CMOS

18

2:1 Break/Make Pulse Ratio, RC Oscillator, Redial of Last Number,
600 Hz Pacifier Tone

MM53144

Push Button Pulse Dialer

CMOS

18

2:1 Break/Make Pulse Ratio, RC Oscillator, Redial of LastNumber

MM53190

Push Button Pulse Dialer

CMOS

20

60/40 Break/Make Pulse Ratio, RC Oscillator, Radial of Last
Number, 600 Hz Pacifier Tone

N

5-6

Selectable Outpulsing Rate, Interdigit Pause and Break/Make
Ratio, Redial, Pacifier Tone, 2-of-7 or Single Contact Keyboard

Display Driver Product Selection Guide
Product
Number

Description

Process

Package
Pins
Type

Notes

MM5445

V.F. Display Driver

PMOS

40

N

33·Segment Direct Drive, Serial Data Input, Brightness Control,
Data Enable

MM5446

V.F. Display Driver

PMOS

40

N

34·Segment Direct Drive, Serial Data Input, Data Enable

MM5447

V.F. Display Driver

PMOS

40

N

34·Segment Direct Drive, Serial Data Input, Brightness Control

MM5448

V.F. Display Driver

PMOS

40

N

35·Segment Direct Drive, Serial Data Input

MM5450

LED Display Driver

NMOS

40

D,N

34-Segment Direct Drive, Serial Data Input

MM5451

LED Display Driver

NMOS

40

D,N

35·Segment Direct Drive, Serial Data Input

MM5452

LCD Display Driver

CMOS

40

N

32-Segment Direct Drive, Serial Data Input, Data Enable

MM5453

LCD Display Driver

CMOS

40

N

33-Segment Direct Drive, Serial Data Input

MM5480

LED Display Driver

NMOS

28

D,N

23-Segment Direct Drive, Serial Data Input, Brightness Control

MM5481

LED Display Driver

NMOS

20

D,N

14-Segment Direct Drive, Serial Data Input, Brightness Control

MM58201

LCD Matrix Display Driver

CMOS

40

N

5-7

Multiplexed Drive, 8 Backplanes, 24 Segments, 192-8it RAM,
Cascadable, RIC Oscillator

Oscillator/Divider Product Selection Guide
Product
Number

Description

Process

Package
Pins
Type

Notes

MM5368

Osciliator/Divider

CMOS

8.

N

32 kHz to 50 Hz or 60 Hz with 1 and 10 Hz Buffered Outputs

MM5369AA

Oscillator/Divider

CMOS

8

N

3.58 MHz to 60 Hz

MM5369EST

Oscillator/Divitler

CMOS

8

N

3.58 MHz to 100 Hz

MM5369EYR

OsciliatorlDivider

CMOS

8

N

3.58 M Hz to 50 Hz

MM53107AA

OsciliatorlDivider

CMOS

8

N

2.097152 M Hz to 60 Hz

MM53107FDU

Oscillator/Divider

CMOS

8

N

2.097152 M Hz to 100 Hz

5-8

Electronic Data Processing Product Selection Guide
Product
Number

Description

Process

Package
Pins
Type

Notes

MM5034

Shift Register

NMOS

22

D,N

Octal80·Bit Shift Register with Tri·State Outputs and Recirculate

MM5035

Shift Register

NMOS

20

D,N

Octal 80·Bit Shift Register with Recirculate

MM5303

UART

PMOS

40

D,N

Universal Asynchronous ReceiverlTransmitter

MM5307

Baud Rate Generator

PMOS

14

D,N

See Data Sheet for Specific Baud Rate Output Frequencies

MM5330

A to 0 Converter

PMOS

16

D,N

4 '/,·Digit Panel Meter Block, also called ADB4500PCN

MM53200

Digital Code Transmitter/Receiver

NMOS

18

N

Single·Chip contains both Encoder and Decoder, 4 valid words
for a Receive

MM54240

Asynchronous Transmitter/Receiver NMOS

24

N

Single·Wire, 128·Location Bi·Directional Data Transmission,
Master/Slave Configuration, 8·Bit Data

MM57109

Number·Oriented Processor

PMOS

28

N

Microprocessor·Compatible Scientific Calculator, Controller,
Memory Device

MM57436

Up/Down Counter

NMOS

24

N

Decimal or Binary Count, Up/Down, 4· or 8·Digit (16· or 32·Bit)
Counter Length

MM57499

Serial Keyboard Interface

NMOS

28

N

MM5863

A to 0 Converter

PMOS

28

D,N

128/144 Keys, Serial Transmit/Receive
12·Bit Binary A/D Block, also called ADB1200PCN

MM5865

Universal Timer

PMOS

40

N

7 Programmable Functions

MM58167

Microprocessor Real Time Clock

CMOS

24

N

Addressable Timekeeping from '/.'" sec. to hrs., Day, Date, and
Month, with corresponding Latches for Alarm·Type Functions,
Power Down Mode, 2 Interrrupt Outputs, 32 kHz Crystal
Controlled Oscillator

MM58174

Microprocessor Real Time Clock

CMOS

16

N

Addressable Timekeeping from '/., sec., to hrs., Day, Date, and
Month, Selectable Interrupt Output, 32 kHz Crystal·Controlled
Oscillator

5-9

Digital Clocks

Digital Clocks

~National

~ Semiconductor
MM5309, MM5311, MM5312, MM5313,
MM5314, MM5315 Digital Clocks
General Description
These digital clocks are monolithic MOS integrated
circuits utilizing P-channel low-threshold, enhancement
mode and ion implanted_ depletion mode devices_ The
devices provide all the logic required to build several
types of clocks_ Two display modes (4 or 6-digits)
facilitate end-product designs of varied sophistication.
The circuits interface to LED and gas discharge displays
with minimal additional components, and require only
a single power supply. The timekeeping function
operates from either a 50 or 60 Hz input, and the display format may be either 12 hours (with leading-zero
blanking) or 24 hours. Outputs consist of multiplexed
display drives (BCD and 7-segment) and digit enables_
The devices operate over a power supply range of 11 V
to 19V and do not require a regulated supply. These
clocks are packaged in dual-in-line packages.

•

Leading-zero blanking (12-hour format)

• 7-segment outputs
• Single power supply
•

Fast and slow set controls

•

Internal multiplex oscillator

•

For features of individual clocks, see Table I

Applications
•

Desk clocks

Features

•

Automobile clocks

• 50 or 60 Hz operation

•

Industrial clocks

•

•

Interval Timers

12 or 24-hour display format

TABLE I
MM5309

MM5311

MM5312

MM5313

BCD Outputs

X

X

X

X

4/6·Digit Display Mode

X

X

X

X

X

FEATURES

Hold Count Control

1 Hz Output

X

Output Enable Control

X

Reset

X

Connection Diagrams

X

~::oj
MM5J09

e....:..:

. .£HI0

MULTIPLEXED

d-=

.!iSO/60 H,INPUT

,.!.!

.!!..FAST SET

b...!.
MULTIPLEXED
7SEGMENT

MM5l11

c 9

c..!

tl!SI
20

d-:'

FS10

OUTPUTS

e..!!
~50f60 Hz INPUT
,.l!
~fASTSET
.
g..!!
t1!-SlOWSET
12/24 HOUR SELECT 11
~HOlO
50/60 Hz SELECT !1L-_ _ _ _-lr!!VSS
OUTPUTS

.!!.SlOWSET

lZ/24 HOUR SelECT J1

f14/6DIGITSElECT

BCD 4:.2.

~~~:~is

e.!1l
eE

!

p! OU;PUT ENABLE

Vao....!.

'BCil8..2.

DIGIT

l!.SI
3.!!.S10

50/60 Hz SELECT

X

p! MUX TIMING

(NEG~~~~~ =(::~
OUTPUTS

X
X

X

~4/6D1GITSELECT

~~~T~~LT~~;~ BCii4:..1

MULTIPLEXED'
lSEGMENT

X

X
X

X

.!!.OUTPUT ENABLE

~..l

b2.

MM5315

(Dual-In-Line Packages)

Voo..!.

l

MM5314

.!!.RESET

.!!L-_ _ _ _-l.!!.Vss

TOP VIEW

TOP VIEW

Order Number MM5311N
See Package 23

Order Number MM&309M
See Package 23

5-13

Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)

t

CW)
It)

:E.
:E

Electrical Characteristics

Vss + 0.3 to VSS - ,20V
-25°C to +70°C
-65°C to +150°C
300°C

T A within operating range, Yss

PARAMETER

= 1-1 V to 19V, VDD ~OV, unless otherwise specified.

CONDITIONS

MIN

= OV)
= 14V, (No Output Loads)

11

Power Supply Voltage

VSS (VDD

Power Supply Current

VSS

MAX

dc

UNITS

19

V

10

mA

60k

Hz

VSS
VSS..:,10

V

VDD
1.0

60

kHz

60

' kHz

"

',.

50/60 Hz Input Frequency

TYP

50 or 60

"

'

50/60 Hz Input Voltage
Logical High Level

VSS-l

Logical Low Level

VDD

Multiplex Frequency

, Determined by External R & C'

All Logic, Inputs

0.100

Driven by External Timebas'e

Logical High Level

VSS

dc

Internal Depletion Device to VSS

VSS-l

VSS,

VDD

VDD

Logical Low Level

V

V

VSS
VSS-l0

V

BCD and 7·Segment Outputs,
Logical High Level

2.0

Loaded :;1 kn to VDD

Logical Low Level

20

mA source

0.01

mA source

0.3

rnA source

25

mA sink

Digital Enable Outputs
Logical High Level
Logical Low Level

Loaded 100 n to VSS

Connection Diagrams
2-

BCD 1

.1

,2

MULTIPLEXED
BCD OUTPUTS
(NEGATIVE

r!!-MUXTIMING

• ....!.
,...!

~·l
r!!.
r!!M1D

MMS312

HI

., ' r

DIGIT
ENABLE

.

~HtO

r!L UPS OUTPUT

' • .2

.l!
50!&DHlSElECT .!!

fl!.SLOWSET

12/24 HR SELECT

fo!!vss

soi&o HI SELECT.!!

• .1

OUTPUTS

ENABLE

E;t

. l!'FASTSET
lLSLOWSET

~HOLD

.E

~VSS

Order Number MM5313N
See Package 23

.!! 4/6 DIGIT SELECT

v O....!.

.!!.M10

.

.!!. H1·

DIGIT

~ HtO

ENABLE
OUTPUTS

I-!.

f1!.SlD

r!!5D1GOHzINPUT

t2124 HR SELECT

.!.!

f1!.fAST~ET .

60160 Hz SELECT

.!1

~ SLOW SET

Vss

.!!

rEHDLD

TRUE)

I

~::~lTIMING

BCD i.l.

.!!Hl

b..!.

MU·~1~~~:~~
,
"

. OUTPUTS

MM5315:·

E.Sl

e...!

.!lSto

d...!,

e~

.!!!.&DI60 Hz INPUT
2!.FASTSET

,J.!

1!.SLOWSET

g.E

~HOLD

12JZ4 HR Sea:EcT.E

r1!.RESET

I

,'.60/60HIsEucr:l! .

~vss

Order Number MM5315N
See Package 23

Order Number MM5314N
See Package 22

5-14

DIGIT

~Hl0 ~~~:~~s

I..!

f1!. .,

,...!

f!:4I&DIGITSELECT

~~r;i~l~~~ 1::~~1

.!! MUXTIMING

MM5314

'DIGIT

l! 50/60 Hr,NPUT

IE
!IE

Order Number MM5312N
See Package 22

A"l

~Hl

.B .,,0

11'10
..!2. 1 PPS 0 UTPUT

r.l!

~FASTSET

MULTIPLEXED'
7SEGMENT
OUTPI1TS

MM5lIJ

9
d:-=

f1!SDI6UHzINPIJT

2.2.
• ..!.
,-!:
,..!.

1!Ml0

,...!

MULTIPLEXED
7 SEGMENT
OUTPUTS

I...!

VDD

'.'}

BCDZ...!

,.!.!!

OUTPUT ENABLE .1

.!!MUX TIMING

BCD 4....2

,

. OUTPUTS

• ...!

12/24 HR SELECT

..!.4/6 DIGITSELECT

Vou...!

~VDD

.-!

MULTIPLEXED
7SEGMENT
OUTPUTS

Dual-In-Line Packages (Top Views)

~8CD8

4

MULTlPLEX'D {BCD .J.
BCD OUTPUTS 'BCD 2
(NEGATIVE
!RUE)

(Cont'd)

5.0

.

Functional Description
A block diagram of the MM5309 digital clock is shown
in Figure 1. MM5311, MM5312, MM5313, MM5314
and MM5315 clocks are bonding options of MM5309
clock. Table I shows the pin·outs for these clocks.

6-digit select input, the divider determines whether data
will be output for 4 or 6 digits. A zero·blanking circuit
suppresses the zero that would otherwise sometimes
appear in the tens-of·hours display; blanking is effective
only in the 12-hour format. The multiplexer addresses
also become the display digit·enable outputs. The multiplexer outputs are applied to a decoder which is used
to address a programmable (code converting) ROM.
This ROM generates the final output codes, i.e., BCD
and 7-segment. The sequential output order is from
digit 6 (unit seconds) through digit 1 (tens of hours).

50 or 60 Hz Input: This input is applied to a Schmitt
Trigger shaping circuit which provides approximately
5V of hysteresis and allows using a filtered sinewave
input. A simple RC filter such as shown in Figure 10
should be used to remove possible line voltage transients
that could either cause the clock to gain time or damage
the device. The shaper output drives a counter chain
which performs the timekeeping function.

Multiplex Timing Input: The multiplex oscillator is
shown in Figure 2. Adding an external resistor and
capacitor to this circuit via the multiplex timing input
(as shown in Figure 4a) produces a relaxation oscillator.
The waveform at this input is a quasi·sawtooth that is
squared by the shaping action of the Schmitt Trigger in
Figure 2. Figure 3 provides guidelines for selecting the
external components relative to desired multiplex
frequency.

50 or 60 Hz Select Input: This input programs the
prescale counter to divide by either 50 or 60 to obtain a
1 Hz timebase. The counter is programmed for 60 Hz
operation by connecting this input to VOO. An internal
depletion device is common to this pin; simply leaving
this input unconnected programs the clock for 50 Hz
operation. As shown in Figure 1, the prescale counter
provides both 1 Hz and 10Hz signals, which can be
brought out as bonding options.

Figure 4 also illustrates two methods of synchronizing
the multiplex oscillator to an external timebase. The
external RC timing components may be omitted and
this input may. be driven by an external timebase; the
required logiC levels are the same as 50 or 60 Hz input ..

Time Setting Inputs: Both fast and slow setting inputs,
as well as a hold input, are provided. Internal depletion
devices provide the normal . timekeeping function.
Switching any of these inputs (one at a time) to VOO
results in the desired time setting function.

Reset: Applying VOO to this input resets the counters
to 0:00:00.00 in 12·hour format and 00:00:00.00 in
24-hour formats leaving the input unconnected (internal
depletion pull-up) selects normal operation. Proper
reset will be ensured when VOO to VSS slew rate is
no faster than one volt per microsecond. This can
be accomplished with a capacitor from the reset input
to VSS.

The three gates in the counter chain (Figure 1) are
used for setting time. During normal operation, gate A
connects the shaper output to a prescale counter (750
or 760); gates Band C cascade the remaining counters.
Gate A is used to inhibit the input to the counters for
the duration of slow, fast or hold time·setting input
activity. Gate B is used to connect the shaper output
directly to a seconds counter (760). the condition for
slow advance. Likewise, gate C connects the shaper
output directly to a minutes counter (760) for fast
advance.

4 or 6-0igit Select Input: Like the other control inputs,
this input is provided with an internal depletion PlJlI-up
device. With no input connection the clock outputs data
for a 4·digit display. Applying VOO to this input provides a 6-digit display.

Fast set then, advances hours information at one hour
per second and slow set advances minutes information
at one minute per second.

Output Enable Input: With this pin unconnected the
BCD and 7-segment outputs are enabled (via an internal
depletion pull·up). Switching VOO to this input inhibits
these outputs. (Not applicable to MM5312, MM5313,
and MM5315 clocks.)

12 or 24-Hour Select Input: This input is used to pro·
gram the hours counter to divide by either 12 or 24,
thereby providing the desired display format. The
12·hour display format is selected by connecting this
input to VOO; leaving the input unconnected (internal
depletion device) selects the 24·hour format.

Output Circuits: Figure 5a illustrates the circuit used
for the BCD and 7 -segment outputs. Figure 5b shows
the digit enable output circuit. Figure 6 illustrates
interfacing these outputs to standard and low power
TTL. Figures 7 and 8 illustrate methods of interfacing
these outputs to common anode and common cathode
LED displays, respectively. A method of interfacing
these clocks to gas discharge display tubes is shown in
Figure 9. When driving gas discharge displays which
enclose more than one digit in a common gas envelope,
it is necessary to inhibit the segment drive voltage(s)
during inter-digit transitions. Figure 9 .also illustrates a
method of generating a voltage for application to the
output enable input to accomplish the required interdigit blanking.

Output Multiplexer Operation: The seconds, minutes,
and hours counters continuously reflect the time of day.
Outputs from each counter (indicative of both units
and tens of seconds, minutes, and hours) are time·
division multiplexed to provide digit·sequential access
to the time data. Thus, instead of requiring 42 leads to
interconnect a 6·digit clock and its display (7 segments
per digit), only 13 output leads are required. The multi·
plexer is addressed by a multiplex divider decoder,
which is driven by a multiplex oscillator. The oscillator
and external timing components set the frequency of
the multiplexing function and, as controlled by the 4 or

5-15

Functional Description

(Cont'd)

~~~~~--------~----~~--------------~--~~--------,

r-~--....;.------------------_+IO

H,

HoLoo-----------------------~--------.,

50~~~~;~------.,...----..,...--~.

I-.-;i-------+I H,

SLDWSET~---------------~--J:::!:::t---~j_~~~=;'l'
FA~SET~::::::::::::::~:::t::::t:::::::~::~~~~~_!~---~~---J~--.,
RESET C

e>---,+}

VSS
VOD 0---. AS REO'D

L-~~:-----lrll-----------;:::::::::::::::::~~OOUTPUT
ENABLE
MULTIPLEXED
I!ClI OUTPUTS
MULTIPLEXED
7·SEGMENT
OUTPUTS

4/:E~I;g ~------------------,
MULTIPLEX
TIMING
OUTPUT

DIVIDER/
MULTIPLEX
DECODER

ENABLE
~::::::::~=::::::::::::::::::::::::::::::::::::::::::::::::) DIGIT
OUTPUTS

FIGURE 1, MM5309 Digital Clock Block Diagram

VOD----.,----.....,.

50/60 PPS

L

50/60 H,
INPUrOR
MULTIPLEX TIMING
CDMPDNENTS

--7"""t----..,...-.....,-'-----r-..X)-.:.....--I~ MULTIPLEX
OUTPUT OR
OSCILLATOR
OUTPUT

.....,...-;

lOOk

~

Vss

I

~

I

x

~

I
I
I
I

Ik

~

'"

100

I. ~

VSS
I

r11
I

0.001

0.01

0.1

C - CAPACITANCE ("FI WITH R' 220k

:

FIGURE 3. Multiplex Timing Component Selection Guide

......

11------0< 1- ______ ...1

vSS

L-.L-J.-'-'-'.uu.--.J-L..LJ.JJ-",,---'-.u..WJ>II

O.OO~I

I

I

10k

"'-I
Dotted components added to shaping
circuit to form multiplex oscillator

*Effectively
FIGURE 2, SO/SO Hz Shaping Circuit/Multiplex Oscillator

5-16

Functional Description

(Cont'd)

Vss

:s::
:s::
c.n

MUX TIMING

CN

......
......

MM5J09

Voo

FIGURE 4a. Relaxation Oscillator

Vss
Vss

Cl

0---1

C2

EXTERNAL
TIME
BASE

MULTIPLEX
TIMING INPUT
t-~~=;.;.;;;..:..:..t

MM5309

MM5309

(INPUT OR OUTPUT)

R'

VOO
VOO

FIGURE 4b. External Time Base

FIGURE 4c. External Clock

Note. Free running frequency should be set to run slightly lower than system frequency
over temperature. External time base may be input or output .
• R=100k.
FIGURE 4. Synchronizing or Triggering Multiplex Oscillators

i i -......-+---I

Vss

n---r}--1

~vss

DIGIT ENABLE
OUTPUT

100

voo

_
)·SEGMENT
OUTPUT

BC~

DR IpPS

COPEN DRAIN)

600

VOO

FIGURE 5a

voo

FIGURE 5b

FIGURE 5. Output Circuits

5-17

Ln

;,;

Functional Description

(Cont'd)

Ln

:e:
:e:
MOS to Low Power TTL Interface

MOS to TTL Interface
Vss'" 5V

Vss

ANY GATES

ANY TTL GATE

Vss e5V

Vee" 5V

MM5309

Voo

Von

For VSS = 5, VOO = 12, R = 10k
ForVSS = 10to 17V, VOO = Gnd, R = 3k

=

-lZV

For VSS = 5, VOo = -12, R = 7.5k
Note; ~igit select vvill drive TTL directly when
5, -12 supplies are used.

FIGURE 6. Interfacing TTL

V§----t---------~--------~-----

1--------1

VyS;PICAL

END~:~~ ~
OUT1'UT

A
I

TYPICAL LEO
SEGMENTS
(COMMON-ANODE)
SUCH AS
NSN71L, OR

M"'309

",M5309

TYPICAL LEO
SEG",ENTS
. (COOlMON·CATHODEI
SUCH AS NSN74R.
OR EQUIV.

EQUIY.
TYPICAL

TYPICAL

2k

EN~:~~!-. ....
-.....
-----1

SEGMENT ! - - -......M".......-I
OUTPUT .J"""l-

OUT1'UT
VDD

.......

5.n

VOO--____------------------~------

Vss - VOO VF 0.6V
RL=------------NIIF)
Where RL as in kn

Where R L is in kG

And VF = forward drop of LED
0.6V '" voltage drop of transistors

And VF = forward drop of LED
0.9V = voltage drop of transistor.;
N = number of digits in display

= number of digits in display
IF = required average LED current

N

IF

= required average

LED current

"Transistor.; may be replaced by OM75491, OM75492,
OM8861, oM8863 or equivalent segment/digit drivers.

FIGURE 7. Interfacing Common Anode LED Displays

FIGURE 8. Interfacing Common Cathode LED Displays

5-18

Functional Description

(Cont'd)

(DV)

TYPICAL

.-------------1

EN~;~i 1---.-OUTPUT

.........

(X6)
270k

TYPICAL
SEGMENT
MM53D9

TYPICAL
SEGMENT
OUTPUT

MULTIPLEX
TIMING

0.05

INPUT

~~lml+--1~---'

0.005

(X7)

210k
lOOk
39k
-.7k

Voo

....--i--I-Ir_-

(-15V)-------~=::~~::::=~:::=~MULTIPLEX TIMING AND

_35V _ _ _ _ _ _ _ _ _~IN~T~ER~o~0I~G~IT~B~LA~N~K~IN~G~_ _ _ _ __4~--+-_~_

-125V-------------------------_4>----FIGURE 9. Interface Panapiex 11* Neon Display Tube

*TM of Burroughs Corp.

DV

.0111'

lN914

lOOk

AC IN

":tOo"

19

15

~-Lo-

27
4/6

Vss

FAST

I..

I-r----ml~

01 25
0224
0323
0422

1B

I
I

SLOW

~-Lo-

MM5J09

17
1 Voo
13

abc

2B

1""=
I

6

26

,

f

o

•

,....L....

7891011 12

~
I-I

>q~9DPF .
2NJ904

I
I
I

I-:J

-- --

-15V
INTER·DlGlT BLANKING CIRCUIT

r,.--L...-..

'-:'1

lOOk

I:~

Il

1M

."

270k!

~

2N5086

-.L...

1

AM

,-------, . 2N50S6

I

--

,........L..,

I

, i, ,. i, i,
I
iJ- , h

--

I

-35V

d

DRIVER

L_ 1 - - - - -

SEG

14

ANODE
2N5D86

(X4)

Dlrx~

(X7)

PM

0.02
jDi

Tv~
CATHODE
DRIVER

I
I
I

~ ,'N9'4
-=)~
r-- --r---ZZOk

ZZk

47k

(X7)

(X7)

(X7)

-105V

FIGURE 10. MM5309 Driving Gas Discharge Display. Typical Applications

5-19

1\

~ "N9'4

41k

ZZk

~National

Digital Clocks

~ Semiconductor
MM5316 Digital Alarm Clock
General Description
The MM5316 digital alarm clock is a monolithic MOS
integrated circuit utilizing P-channel low-threshold,
enhancement mode and ion-implanted depletion mode
devices. It provides all the logic requiredto build several
types of clocks and timers. Four display modes (time,
seconds, alarm and sleep) are provided to optim ize
circuit utility. The circuit interfaces directly with 7segment fluorescent tubes, and requires only a single
power supply. The timekeeping function operates
from either a 50 or 60 Hz input, and the display for·
mat may be either 12 hours (with leading-zero blanking and AM/PM indication) or 24 hours. Outputs
consist of display drives, sleep (e.g., timed radio turn
off), and alarm enable. Power failure indication is
provided to inform the user that incorrect time is
being displayed. Setting the time cancels this indication. The device operates over a power supply range
of 8-29V and does not require a regulated supply.
The MM5316- is packaged in a 40-lead dual·in-line
package.

Features
• 50 or 60 Hz operation
• Single power supply
• Low power dissipation (36 mW at 9V)
• 12 or 24-hour display format

•
•
•
•
•
•
•
•
•

AM/PM outputs
}
.
.
12-hour format
Leading-zero blanking _
24-hour alarm setting
All counters are resettable
Fast and slow set controls
Power failure indication
Blanking/brightness control capability
Elimination of illegal time display at turn on
Direct interface to fluorescent tubes

•
•

9-m inute snooze alarm
Presettable 59-minute sleep timer

Applications
•
•
•
•
•
•
•
•
•
•
•

Alarm clocks
Desk clocks
Clock ra-dios
Automobile clocks
Stopwatches
Industrial clocks
Portable clocks
Photography timers
Industrial timers
Appliance_ timers
Sequential controllers

Block and Connection Diagrams
OUTPUT
COMMON
SOURCE

12/Z~EHL~~~

23

0-::'--------------------,

0-"'------------------,

Dual-In-Line Package

50160 HZ
INPUT

40 PMDUT

AM OUTPUT

39 1 HlOUT

lDHRS-b&c

38 lZ!24HRSElECT

HRS-I

"
"

HRS-g

HRS-I

J5

HRS-b
ALARM

II

HRS-t
TO HRS

DIGIT
SNOOZE

TO 10'S
OFMINS
DIGIT

10MINS-II&d
lDMINS-b

10MINS-e
10MINS-c

ToMINS
DIGIT

MINS-f
MINS-g
MINS-a

12

MINS-b

BLANKING 0-;';...7_ _ _--:-_ _ _-;-_~-,__----_+I
INPUT
JJ

MINS-c

SlOWSET~

l2

HRS-e

lDMINS-f
lOMINS-g

SLEEP
OUT

SLEEPelS
ALARM
OIS
SECONDS
OIS

J4

HRS-d

OUT
ALARM
OFF

10

J1

11

"

12

21 VSS
SLEEP OUT

t6

"

17

24

15

25

"
"

"

19

22
21

0----+-

FIGURE 1.

FIGURE 2.

5-20

ALARM DISPLAY IN
SLEEPOISPlAY IN

28 Vao

See Package 24

29

SECONDS DISPLAY IN

14

Order NumbeT MM5316N

"

Von

FAST SET IN
SLOW SET IN

13

TOPVIEW

J4

5D/liOHzIN

19

FASTSET~

Vss 0----+-

BLANKING IN
Sll/60HzSElECT

ALARM OFF IN
ALARM OUT
SNoo2E IN
OUT COMMON SOURCE
MINS-c
MINS-d

s:
s:
en

Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)

~

.....

VSS + 0.3 to VSS - 30V
-25°C to +70°C
-65°C to +150°C
300°C

0')

Electrical Characteristics
TA within operating range, VSS = 21 V to +29V, VDD = OV, unless otherwise specified.
PARAMETER

CONDITIONS

Power Supply Voltage

VSS (VDD = OVI

Power Supply Current

No Output Loads

MIN

TYP

21

MAX
29

UNITS
V

VSS= 8V

4

mA

VSS = 29V

5

mA

Counter Operation Voltage

29

8

50/60 Hz Input Frequency Voltage

dc

Logical High Level

VSS-l

Logical Low Level

VDD

50 or 60
VSS
VDD

V

10k

Hz

VSS

V

VDD+l

V

Blanking Input Voltage
Logical High Level

VSS-1.5

VSS

VSS

V

Logical Low Level

VDD

VDD

VSS-4

V

All Other Input Voltages
Logical High Level
Logical Low Level
Power Failure Detect Voltage
Output Currents, 1 Hz Display

Internal Depletion Device to VDD
(VSS Voltage)

VSS-l

VSS

VSS

V

VDD

VDD

VDD+2

V

20

V

10

VSS = 21V to 29V,
Output Common = VSS

Logical High Level

VOH = VSS - 2V .

Logical Low Level, Leakage

VOL = VDD

1500

fJ.A
1

fJ.A

10's of Hours (b & c), 10's of Minutes
(a & d)
Logical High Level

VOH = VSS - 2V

Logical Low Level, Leakage

VOL = VDD

1000

fJ.A
1

fJ.A

All Other Display, Alarm and Sleep Outputs
Logical High Level

VOH = VSS - 2V

Logical Low Level, Leakage

VOL = VDD

fJ.A

500
1

5·21

fJ.A

Functional Description
A block diagram of the MM5316 digital alarm clock is
shown in Figure 1. The various display modes provided
by this clock are listed in Table I. The functions of the
setting controls are listed in Table II. Figure 2 is a
connection diagram. The following discussions are based
on Figure 1.

fluorescent tube displays, VSS or a display brightness
control voltage is permanently connected to this pin.
Since the brightness of a fluorescent tube display is
dependent on the anode (segment) voltage, applying a
variable voltage to pin 23 results in a display brightness
control. This control is shown in Figure 6.

50 or 60 Hz Input (pin 35): A shaping circuit (Figure 3)
is provided to square the 50 or 60 Hz input. This circuit
allows use of a filtered sinewave input. The circuit is a
Schm itt Trigger that is designed to provide about 6V of
hysteresis. A simple RC filter, such as shown in Figure 6,
should be used to remove possible line-voltage transients
that could either cause the clock to gain time or damage
the device. The shaper output drives a counter chain
which performs the timekeeping function.

12 or 24-Hour Select Input (pin 38): By leaving this pin
unconnected, the outputs for the most-significant
display digit (10's of hours) are programmed to provide
a 12·hour display format. An internal depletion pull
down device is again provided. Connecting this pin
to VSS programs the 24-hollr display format. Segment connections for 10's of hours in 24-hour mode
are shown in Figure 5b.
Power Fail Indication: If the power to the integrated
circuit drops indicating a momentary ac power failure
and possible loss of clock, the power fail latch is set.
The power failure indication consists of a flashing of the
AM or PM indicator. at a 1 Hz rate. A fast or slow set
input resets an internal power failure latch and returns
the display to normal. In the 24-hour format, the power
failure indication consists of flashing segments "c" and
"f" for times less than 10 hours, and of a flashing
segment "c" for times equal to or greater than 10 hours
but less than 20 hours; and a flashing segment "g" for
times equal to or greater than 20 hours.

50 or 60 Hz Select Input (pin 36): A programmable
prescale counter divides the input line frequency by
either 50 or 60 to obtain a 1 Hz time base. This counter
is programmed to divide by 60 simply by leaving pin 36
unconnected; pull-down to VDD is provided by an
internal depletion device. Operation at 50 Hz is programmed by connecting pin 36 to VSS.
Display Mode Select Inputs (pins 30-32): In the
absence of any of these three inputs, the display drivers
present time-of-day information to the appropriate
display digits. Internal pull-down depletion devices allow
use of simple SPST switches to select the display moch!.
If more than one mode is selected, the priorities are as
noted in Table I. Alternate display modes are selected
by applying VSS to the appropriate pin. As shown in
Figure 1 the code converters receive time, seconds, alarm
and sleep information from appropriate points in the
clock circuitry. The display mode select inputs control
the gating of the desired data to the code converter
inputs and ultimately (via output drivers) to the display
digits.

Alarm Operation and Output (pin 25): The alarm
comparator (Figure 1) senses coincidence between the
alarm counters (the alarm setting) and the time counters
(real time). The comparator output is used to set a latch
in the alarm and sleep circuits. The latch output enables
the alarm output driver (Figure 4), the MM5316 output
that is used to control the external alarm sound generator'. The alarm latch remains set for 59 minutes, during
which the alarm will therefore sound if the latch output
is not temporarily inh ibited by another latch set by the
snooze alarm input (pin 24) or reset by the alarm "OFF"
input (pin 26). If power fail occurs and power comes
back up, the alarm output will be in high impedance
state.

Time Setting Inputs (pins 33 and 34): Both fast and
slow setting inputs are provided. These inputs are
applied either singly or in combination to obtain the
control functions listed in Table II. Again, internal
pull-down depletion devices are provided; application of
VSS to these pins effects the control functions. Note
that the control functions proper are dependent on the
selected display mode. For example, a hold-time control
function is obtained by selecting seconds display and
actuating the slow set input. As another example, the
clock time may be reset to 12:00:00 AM, in the 12-hour
format (00:00:00 in the 24-hour format), by selecting
seconds display and actuating both slow and fast set
inputs.

Snooze Alarm Input (pin 24): Momentarily connecting
pin 24 to VSS inhibits the alarm output for between 8
and 9 minutes, after which the alarm will again be
sounded. This input is pulled-down to VDD by an
internal depletion device. The snooze alarm feature may
be repeatedly used during the 59 minutes in which the
alarm latch remains set.
Alarm "OFF" Input (pin 26): Momentarily connecting
pin 26 to Vssresets the alarm latch and thereby silences
the alarm. This input is also returned to VDD by an
internal depletion device. The momentary alarm "OF F"
input also readies the alarm latch for the next comparator output, and the alarm will automatically sound again
in 24 hours (or at a new alarm setting). If it is desired
to silence the alarm for a day or more, the alarm "OFF"
input should remain at VSS.

Blanking Control Input (pin 37): Connecting this
Schmitt Trigger input to VDD places all display drivers
in a non·conducting, 'high-impedance state, thereby
inhibiting the display, (see Figures 3 and 4). Conversely,
VSS applied to this input enables the display.
Output Common Source Connection (pin 23): All
display output drivers are open-drain devices with all
sources common to pin 23 (Figure 4). When using

Sleep Timer and Output (pin 27): The sleep output
at pin 27 can be used to turn off a radio after a

5-22

Functional Description

(Cont'd)
and the sleep output current drive is removed, thereby
turning off the radio. The turn off may also be
manually controlled (at any time in the countdown) by
a momentary VSS connection to the snooze input
(pin 24). The output circuitry is the same as the other
outputs (Figure 4).

desired time interval of up to 59 minutes. The time
interval is chosen by selecting the sleep display mode
(Table I) and setting the desired time interval (Table II).
This automatically results in a current·source output
via pin 27, which can be used to turn on a radio
(or other appliance). When the sleep counter, which
counts downwards, reaches 00 minutes, a latch is reset
VOO

50/60 HZ

BiN;~~I~~ >-",--1

50/60 Hz

INPUT

) 0 -...- . .

~~:~~iNOGR
SIGNAL

VSS

FIGURE 3. 50/60 Hz or Blanking Input Shaping Circuit

*OUTPUT COMMON SOURCE BUS (PIN 23)

O:(OATA)~~

BLANKING
(FROM-t
SHAPER)

OUTPUT
(OPEN DRAIN)

Vss

* Alarm and sleep output sources are connected to VSS:
blanking is not applied to these outputs.
FIGURE 4. Output Circuit

PIN 39
1 Hz
PIN 40
PM

PIN 1
AM

PIN 1
AM

PIN 2
NC

b&c

"":'--+--NC

(a) 12·Hour Display Format

(bl 24·Hour Display Format

FIGURE 5. Wiring Tan's-of-Hours Digit

5-23

PIN 40
PM

PIN 2

b& c

Functional Description

(Cont'd)
TABLE I. MM5316 Display Modes

'SELECTED
DlSPLA Y MODE

DIGIT NO.1

DIGIT. NO.2

DIGIT NO.3

DIGIT NO. 4

Time Display

10's of Hours & AM/PM

Hours

10's of Minutes

Minutes

Seconds Display

Blanked

Minutes

lO's of Seconds

Seconds

Alarm Display

lO's of Hours & AM/PM

Hours

10's of Minutes

Minutes

Sleep Display

Blanked

Blanked

10's of Minutes

Minutes

*If more than one display mode input is applied, the display priorities are in the order of Sleep (overrides all others), Alarm,

Seconds, Time (no other mode selected).

TABLE II. MM5316 Setting Control Functions

CONTROL
INPUT

SELECTED
DISPLAY MODE

CONTROL FUNCTION

*Time

Slow
Fast
Both

Minutes Advance at 2 Hz Rate
Minutes Advance at 60 Hz Rate
Minutes Advance at 60 Hz Rate

Alarm

Slow
Fast
Both
Both

Alarm
Alarm
Alarm
Alarm

Seconds

Slow
Fast
Both
Both

Input to Entire Time Counter is Inhibited (Hold)
Seconds and 10's of Seconds Reset to Zero Without
a Carry to Minutes
Time Resets to 12:00:00 AM (12·hour format)
Time Resets to 00:00:00 (24·hour format)

Slow
Fast
Both

Substracts Count at 2 Hz
Substracts Count at 60 Hz
Substracts Count at 60 Hz

Sleep

Minutes Advance at 2 Hz Rate
Minutes Advance at 60 Hz Rate
Resets to 12:00 AM (12·hour format)
Resets to 00:00 (24·hour format)

*When setting time sleep minutes will decrement at rate of time counter, until the sleep counter reaches 00 minutes
(sleep counter will not recycle).

Typical Application
Figure 6 is a schematic diagram of a general purpose alarm clock using the MM5316 and a fluorescent tube display.

3

1156~~~

BRIGHTNESS

CONTROL

+-+l---<~~~-1HVss

18V lOOk

27k

OUTPUT COMMON
SOURCE
L...,~---l----l---I50!60 Hz INPUT

~tlH'
AM___~-'M ';'

MM5316

SLEEP

10'SOfHDUAS

UNIT HOURS

10'S OF MINUTES

UNIT MINUTES

OUT

:

: ~'Hr'~rT~"'-~~~T-~-T4-r-r+~~-T~~rr+--i--~~~

I
I
I.

\10'sOF
I HOURS
I FOR

I
I

I

L___

I
I

NC

I 24-HR

_ ___ J MODE

FIGURE 6. Schematic

5·24

ALARM
DRIVE

~National

Digital Clocks

~ Semiconductor
MM5387AA, MM53108 Digital Alarm Clocks
General Description

Features

The MM5387 AA, MM53108 digital alarm clocks are
monolithic MaS integrated circuits utilizing P-channel
low-threshold, enhancement mode and ion-implanted
depletion mode devices. They provide all the logic
required to build several types of clocks and timers
with up to four display modes (time, seconds, alarm
and sleep) to maximize circuit utility, but are specifically intended for clock-radio applications_ Both devices
will directly-drive 7-segment LED displays in either a
12 hour format (3'1, digits) with lead-zero blanking,
AM/PM indication and flashing colon, or 24 hour
format (4 digits) through hard-wire pin selection; the
timekeeping function operates from either a 50 or
60 Hz input, also through pin selection. Outputs consist
of display drivers, sleep (e.g .. timed radio turn-off), and
alarm enable_ A power-fail indication mode is provided
to inform the user of incorrect time display by flashing
all "ON" digits at a 1 Hz rate, and is cancelled by
simply resetting time_ The device operates over a supply
range of 24-26V which does not require regulation.

"
"

50 or 60 Hz operation
Single power supply

"

12 or 24 hour display format

"
"
"
"
"
"
"
"
"
"
"

AM/PM outputs
}
12 hour format
Leading-zero blanking
24-hour alarm setting
All counters are resettable
Fast and slow set controls
Power failure indication
Elimination of illegal time display at turn "ON"
Direct interface to LED displays
9-minute snooze alarm
Presettable 59-minute sleep timer
Available in standard (MM5387AA) or mirror image
(MM53108) pin-out

Applications

The MM53108 is electrically identical to the
MM5387AA, but with mirror-image pin-out to facilitate
PC board layout when designing a "module" where the
LED display and MaS chip are mounted on the same
side; the MM5387 AA is more suited for "L" shaped
module designs (vertical LED display, horizontal component board). Both devices are supplied in a 40-lead
dual-in-line package_

"
"

" Alarm clocks
" Desk clocks
" Clock radios
" Automobile clocks

II

Portable clocks
Photography timers
Industrial timers

" Appliance timers
" Sequential controllers

" Stopwatches
" Industrial clocks

Block Diagram
OUTPUT

COMMON
SOURCE
12/2~EHl~~~

23 (18)

0.::='------------------------,
0.::36"'13::.'_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---,

SO/60 HZ
INPUT

ALARM OUT

"':="---...,

ALARM OFF

0...:.="--.,

TO HRS
DIGIT

SNOOZE

SLEEP OUT

+''-''-''--'

TO 10'S
OF MINS

DIGIT

SLEEP 015 o-:;='---------------------~
ALARM DIS 0-'-31,,1::",-'_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

-1

SECONDS DIS

16-22
(19-25)

TO MINS

DIGIT

O-,-J2!..!':.c"_ _-'-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~
37(4)

NCO

33(8)

SlOWSET~

34m

FAST SET 0-------+
V

ss

28(13)

0----'-+

29(12)
VDD~

Note. MM53108 pin connections shown in parenthesis
FIGURE 1

5·25

Absolute Maximum Ratings
Voltage at Any Pin Except Segment Outputs
Voltage at Segment Outputs
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)

VSS + 0.3 to Vss - 30V
VSS + 0.3 to VSS - 15V
-25°C to +70°C
-65°C to +150°C
300°C

Electrical Characteristics
TA within operating range, Vss

~

24V-26V, VDD

PARAMETER
Power Supply Voltage

Power Supply Current

~

OV, unless otherwise specified.
CONDITIONS

MIN

TYP

MAX

UNITS

Output Driving Display

24

26

V

Functional Clock

8

26

V

No Output Loads
VSS

~

8V

4

mA

VSS

~

26V

5

mA

50/60 Hz Input
Frequency Voltage

VSS ~ 8V to 26V

dc

50 or 60

10k

Hz

Logical High Level

VSS-l

VSS

VSS

V

Logical Low Level

VDD

VDD

VDD+2
100

/lA

I nput Leakage

V

All Other Input Voltages
Logical High Level
Logical Low Level
Power Failure Detect Voltage

VSS-l

VSS

VSS

V

Internal Depletion Load to VDD

VDD

'VDD

VSS-6

V

(VSS Voltage), (Note2)

1

7.5

V

8

26

V

26

V

Count Operating Voltage
Hold Count Voltage
Output Current Levels

(Note 2)
VSS ~ 24V to 26V,
~

Output Common

VSS

10's of Hours (b & c), 10's of Minutes
(a &d)
Logical High Level, Source

VOH ~ VSS -4V

Logical Low Level, Leakage

VOL ~ VSS - 14V

mA

16
10

/lA

1 Hz Display
Logical High Level, Source

VOH ~ VSS - 4

Logical Low Level, Leakage

VOL ~ VSS -14

24

rnA
10

/lA

(Note 1)

mA

10

/lA

All Other Displays
Logical High Level, Source

VOH ~ VSS - 4V

Logical Low Level, Leakage

VOL ~ VSS - 14V

Alarm and Sleep Outputs

VSS

~

8

24V

Logical High, Source

VOH ~ VSS- 2

500

/lA

Logical Low, Sink

VOL ~ VSS - 2

1

/lA

Note 1: Segment output current must be limited to 11 rnA maximum by user; power dissipation must,be limited to 900 mW at 70° C and 1.2W
at 25°C.
Note 2: The power·fail detect voltage is O.5V or more above the hold count voltage. The power·fail latch trips into power-fail mode at least O.5V
above the voltage at which data stored in the time latch is lost.

"

5·26

Functional Description
gating of the desired data to the code converter inputs
and ultimately (via output drivers) to the display digits.

A block diagram of the MM5387AA, MM53108 digital
clock radio circuit is shown in Figure 1. The various
display setting modes are listed in Table I, and Table II
shows the setting control functions. The following
description is based on Figure 1 and refers to both
devices as they are electrically identical.

Time Setting Inputs: Both fast and slow setting inputs
are provided. These inputs are applied either singly or
in combination to obtain the control functions listed in
Table II. Again, internal depletion pull-down devices
are provided; application of VSS to these pins affects
the control functions. Note that the control functions
proper are dependent on the selected display mode.
For example, a hold-time control function is obtained
by selecting seconds display and actuating the slow set
input. As another example, the clock time may be reset
to 12:00:00 AM, by selecting seconds display and actu·
ating both slow and fast set inputs.

50 or 60 Hz Input: A shaping circuit (Figure 3) is provided to square the 50 or 60 Hz input. This circuit
allows use of a filtered sinewave input. The circuit is a
Schmitt trigger that is designed to provide about 6V of
hysteresis. A simple RC filter such as shown in Figure 7,
should be used to remove possible line-voltage tran·
sients that could either cause the clock to gain time or
damage the device. The shaper output drives a counter
chain which performs the timekeeping function.

Output Common Source Connection: All display output drivers are open-drain devices with all sources
common (Figure 4a). The common source pin should
be connected to VSS.

50 or 60 Hz Select Input: A programmable prescale
counter divides the input line frequency by either
50 or 60 to obtain a 1 Hz time base. This counter is
programmed to divide by 60 simply by leaving 50/
60 Hz select unconnected; pull-down to VOO is pro·
vided by an internal depletion load. Operation at 50 Hz
is programmed by connecting 50/60 Hz select to VSS.

12 or 24 Hour Select Input: By leaving this pin uncon·
nected, the outputs for the most-significant display
digit (1 O's of hours) are programmed to provide a
12-hour display format. An internal depletion pulldown device is again provided. Connecting this pin to
VSS programs the 24·hour display format. Segment
connections for 10's of Hours in 24·hour mode are
shown in Figure 6.

Display Mode Select Inputs: In the absence of any of
these three inputs, the display drivers present time·ofday information to the appropriate display digits.
Internal depletion pull·down devices allow use of simple
SPST switches to select the display mode. If more than
one mode is selected, the priorities are as noted in
Table I. Alternate display modes are selected by apply·
ing VSS to the appropriate pin. As shown in Figure 1
the code converters receive time, seconds, alarm and
sleep information from appropriate points in the clock
circuitry. The display mode select inputs .control the

Power Fail Indication: If the power to the integrated
circuit drops, indicating a momentary ac power failure
and possible loss of clock, all "ON" segments will
flash at 1 Hz rate. A fast or slow set input resets an
internal power failure latch and returns the display to
normal.

Connection Diagrams
Dual-In-Line Package
AM OUTPUT

39

10 HRS -b &c

3B

HRS -I

37

HAS -g

36

HRS -a

35

HRS -b

34

HRS -d

33

HRS -c

31

HAS -e
10MINS-f

10MINS-g
10 MINS - a & d

10MINS-b
10MINS-e
10 MINS -

10

31

11

30

11
13

"

MINS - g

17
18

MINS-e

11

COLON

12/14 HR SELECT

19

11

10

11

39

H,)

3B

11/14 HR SELECT

NC

37

NC

50/60 Hz SnECT

36

50/60 Hz SelECT

50/60 H, INPUT

35

50/60 Hz INPUT

FAST SET INPUT

FAST SET INPUT

SLOW SET INPUT

SLOW SET INPUT

SECOND DISPLAY INPUT

34
33
31

SECOND DISPLAY INPUT

ALARM DISPLAY INPUT

ALARM DISPLAY INPUT

SLEEP DISPLAY INPUT

SLEEP DISPLAY INPUT

VOO

VOO

vSS

vSS
SLEEP OUTPUT
ALARM "OFF"INPUT

ALARM OUTPUT

ALARM OUTPUT

SNOOZE INPUT

SNOOZE INPUT

OUTPUT COMMON SOURCE

40

PM OUTPUT

Hz)

ALARM "OFF" INPUT

16

-3

MINS - b

PM OUTPUT

COLON

SLEEP OUTPUT

15
I:

MINS -f

MINS

Dual-In-Line Package
40

OUTPUT COMMON SOURCE

MINS-t

MINS-c

MINS - d

MINS - d

TOP VIEW

31

10
11

30

11

19

13

lB

14

27

15

16

16

15

17

14

18

13

19

11

20

21

AM OUTPUT
10HRS-b&c

HRS -t
HRS - g

HRS-l
HRS -b

HRS -d
HRS - c
HRS - e
IOMINS-I
10MINS-g
10MINS-a&d

IOMINS-b
10 MINS - e

10MINS-c
MINS -I
MINS-g
MINS-a

MINS - b
MINS -e

TOP VIEW

Order Number MM53108N
See Package 24

Order Number MM5387AA/N
See Package 24

FIGURE 2(b). MM5310B (Mirror Image Pin-Out)

FIGURE 2(a). MM53B7AA

5-27

Functional Description

(Conl'd)

Alarm Operation and Output: The alarm comparator
(Figure 1) senses coincidence between the alarm counters (the alarm setting) and the time counters (real time)_
The comparator output is used to set a latch in the
alarm and sleep circuits. The latch output enables the
alarm output driver (Figure 4b) which is used to
control the external alarm sound generator. The alarm
latch remains set for 59 minutes, during which the alarm
will therefore sound if the latch output is not temporarily inhibited by another latch set by the snooze alarm
input or reset by the alarm "OFF"input.

silences the alarm. This input is also returned to VDD by
an internal depletion device_ The momentary alarm
"OFF" input also readies the alarm latch for the next
comparator output, and the alarm will automatically
sound again in 24 hours (or at a new alarm setting).
If it is desired to silence the alarm for a day or more,
the alarm "OFF" input should remain at VSS.
Sleep Timer and Output: The sleep output can be used
to turn "OFF" a radio after a desired time interval of up
to 59 minutes. The time interval is chosen by selecting
the sleep display mode, (Table I) and setting the desired
time interval (Table II). This automatically results in a
current-source output which can be used to turn "ON" a
radio (or other appliance). When the sleep counter,
which. counts downwards, reaches 00 minutes, a latch
is reset and the sleep output current drive is removed,
thereby turning "OFF" the radio. This turn "OFF"
may also be manually controlled (at any time in the
countdown) by a momentary VSS connection to the
Snooze input. The output circuitry is the same as the
other outputs (Figure 4b).

Snooze Alarm Input: Momentarily connecting snooze
to VSS inhibits the alarm output for between 8 and 9
minutes, after which the alarm will again be sounded.
This input is pulled-down to VDD by an internal depletion device. The snooze alarm feature may be repeatedly
used during the 59 minutes in which the alarm latch
remains set.
Alarm "OFF" Input: Momentarily connecting alarm
"OFF" to VSS resets the alarm latch and thereby

VDD

vss
FIGURE 3. 50/60 Hz Input Shaping Circuit

Vss

COMMON SOURCE BUS

~
>--i

FROM
ALARM
OR SLEEP
COMPARATOR

vss

~

>-1.•

OUTPUT

OUTPUT
(OPEN DRAIN)
VOO

FIGURE 4(a). Segment Outputs

. FIGURE 4(b). Alarm and Sleep Outputs

5-28

Functional Description

(Conl'd)

TABLE I. MM5387AA,MM53108 Display Modes
*SELECTED
DISPLAY MODE

DIGIT NO.1

DIGIT NO.2

DIGIT NO.3

DIGIT NO.4

Time Display

10's of Hours & AM/PM

Hours

lO's of Minutes

Minutes

Seconds Display

Blanked

Minutes

10's of Seconds

Seconds

Alarm Display

10's of Hours & AM/PM

Hours

10's of Minutes

Minutes

Sleep Display

Blanked

Blanked

10's of Minutes

Minutes

* If more than

one display mode input is applied, the display priorities are in the order of Sleep {overrides
all othersl. Alarm, Seconds, Time (no other mode selected).

TABLE II. MM5387AA, MM53108 Setting Control Functions
SELECTED
DISPLAY MODE

*Time

CONTROL
INPUT
Slow

Fast
Both
Alarm

Slow
Fast
Both

Seconds

Slow
Fast

80th

Both
Both,
Sleep

Slow
Fast
Both

I~

CONTROL FUNCTION
Minutes Advance at 2 Hz Rate
Minutes Advance at 60 Hz Rate
Minutes Advance at 60 Hz Rate
Alarm Minutes Advance at 2 Hz Rate
Alarm Minutes Advance at 60 Hz Rate
Alarm Resets to 12:00 AM (Midnight) (12-Hour Format)
Alarm Resets to 00:00 (24-Hour Format)
Input to Entire Time Counter is Inhibited (Holdl
Seconds and 1D's of Seconds Reset to Zero Without
a Carry to Minutes
Time Resets to 12:00:00 AM (Midnight) (12-Hour Format)
Time Resets to 00:00:00 (24-Hour Format)
Subtracts Count at 2 Hz
Subtracts Count at 60 Hz
Subtracts Count at 60 Hz

*When setting time sleep minutes will decrement at rate of time counter, until the sleep
counter reaches 00 minutes (sleep counter will not recycle).

10

/"

Vss :24V

voo '0

./

/
/
1

o I

AM

/
V

/

o

OUTPUT (DRAIN) VOLTAGE BELOW Vss

Switch A must be ganged with Sleep display as shown.

FIGURE 5.'Typical Output Current
Characteristics of MM5387 AA, MM53108

FIGURE 6. 24·Hour Operation:

1O's of Hours Digit Connections

5-29

Typical Application
Figure 7 is a schematic diagram of a general purpose alarm clock circuit (12-hour mode) using the MM5387AA or
MM53108 and a 3 1/2-digit lED display.

Vss
OUTPUT COMMON SOURCE
ALARM
DRIVE

-yo.""
lOOk ':'

10'S OF MINUTES

UNIT HOURS

Voe 10'S OF HOURS
1 Hl PM AM

f

•

e· f a&d

b

b

9

,
,

UNIT MINUTES

d

4.7k

Voo
PM

AM

COMMON CATHODE

,

--;'---l

=

II OPTION 1
I

BRIGHTNESS
CONTROL

VLEO
SUPPl V

,

L

I
_______ J
Voo

-

FIGURE 7

5-30

0,---

2

1

I
,

.-,:;:-220,'

, -:k

---i
II OPTION 2
,

,

L_.:. _____ 1

~National

Digital Clocks

~ Semiconductor
MM53110 Series Auto Clock and Elapsed limer
General Description
The MM53110 series clock is a monolithic MOS
integrated circuit utilizing P-channel low-threshold,
enhancement mode and ion-implanted depletion mode
devices. The circuit interfaces simply with vacuumfluorescent 4-digit displays. The display format is 12
hours for time display and 20 hours for elapsed time
displa'y with leading-zero blanking and colon indication.
The timekeeping function operates from a 2 MHz crystalcontrolled source.

Features
•
•

Elapsed time display
Crystal-controlled oscillator (2_097152 MHz)

•
•

12-hour display format
Colon output (1 1/2 seconds ON and 1/2 second
OFF)

•

Leading-zero blanking

•
•
•
•

Hours and minutes set controls
Elapsed time reset and display control
Brightness control capability
DC/DC converter pulse output

•
•
•
•

Day/night control
Elimination of illegal time display at turn-on
Simple interface to vacuum-fluorescent displays
Low standby power dissipation

Applications
•
•

Elapsed timer
Automobile clocks

•
•
•

Desk clocks
Portable clocks
High accuracy clocks

Block Diagram

Connection Diagram
Dual-In-Line Package

ase 1

r - - - - - - - - , 2 2 05e2

05&2
21

Ml

ase 1

MIO

HI

211 TIME SET

HIO

HIO
19 VOD
18 ELAPSED
TIME

TIME SET
MM53110

HI

11 Vss
16

,

IGN

NIGHT

14

COLON
10

DAV/NIGHT

DIN

BRIGHTNESS

COLON

IGNITION

IS DAY!

MIO

BRIGHTNESS

13 PULSE OUTPUT

11

12 Ml
TOP VIEW

Available Options Table

OPTION NAME

ELAPSED TIME FORMAT

AA

Hours-Minutes

AB

Minutes-Seconds

FIGURE 1. MM53110 Auto Clock Diagram

5-31

Order Number MM53110AA/N
or MM53110AB/N

See Package 21

.Absolute Maximum Ratings
Voltage at Any Pin
Voltage at Any Display Output Pin
Operating Temperature
Storage Temperature
Lead T~mperature (Soldering, 10. seconds)

Electrical Characteristics

VSS + o..3V to VSS - 29V.
VSS + o..3V to VSS - 29V
-40.° C to +85° C
-65°C to +15o.o C
3o.o.o C

T A within operating range, Vss = 9V to 28V, VDD = o.V, unless otherwise specified.

CONDITIONS

PARAMETER

MIN

TYP

MAX

UNITS

Power Supply Voltage (VSS)

Outputs and Osc. Operational

9

25

28

V

Power Supply Voltage (VSS)

No Loss of Time Memory

5

12

28

V

Power Su,Pply Current (ISS)

V SS = 12V, No Output Loads"

1

5

8

mA

1

9

15

mA

2.0.97152

2.1

(Ignition OF F)
Power Supply Current (ISS)

VSS'; 25V, No ~utput Loads,
(Ignition ON)

Power Supply Rise Time (tR)

10.0.

Input Frequency

Osc.l

Multiplex Rate

fiN = 2.0.97152 MHz

Brightness I nput Voltage

(Note 1)

DC

MHz
Hz

20.48

0.-10.0.% Intensity

Day/Night Input = High

10.0.% Intensity

Day/Night Input = Low

Set Input Current

/1sIV

0.

14

,VSS

V

±4.o.

mA

V

VSS

VIN = VSS or VDD, VSS'= 25V

Set I nput Voltage
Logical High Level

Set Minutes

,Logical Low Level

Set Hours

I nput Floating

Display Time

VSS-l.o.

VSS

VDD

VDD
Floating

V

VSS
VDO+l.o.

V

Elapsed Time Input Voltage
Logical High Level

Display Elapsed Time

Logical Low Level

Reset Elapsed Time

Input Floating

Display Time

Ignition Input Voltage

VSS-l.o.

VSS

VDD

VDD
Floating

V

VSS
VDD+l.o.

V

Internal 1M .Resistor to VDD

Logical High Level (ON)

VSS = 12V to 25V

6.5

14

VSS

V

Logical Low Level (OFF)

VSS= 25V

0.

0.'.

1.8

V

VSS
1.8

V

Day/Night Input Voltage

Internal 1M Resistor to VDD

Logical High Level (Night)

VSS= 25V

6.5

14

Logical Low Level (Day)

VSS= 25V

0.

0.

Ignition Input Current

VSS = 25V, VIN = 12V

4

40.

Day/Night Input Current

VSS = 25V, VIN = 12V

4

40.

Pulse Output

VOH = VSS.- 2V

V

..

/1A
/1 A

Logical High Level

VSS = 9V

1

mA

Logical High Level

VSS = 28V

4

mA

Logical Low Level

VOL=VDD+1V

6'.

/1 A

Internal Diffused Resistor to VDD
Digit Outputs
Logical High Level (ON)

VOH = VSS - IV

8.0.

mA

Logical Low Level (OFF)

VOL = VDD + 2V

40.

/1 A

Segment, Colon Outputs
Logical High Level (ON)

VOH = VSS - IV

2.0.

mA

Logical Low Level (0 F F)

VOL = VDD + 2V

40.

/1A

Note 1: In the day position, the brightness input is internally forced to VSS in order to supply maximum voltage to the disl?'ay.

5-32

Functional Description
A block diagram of the MM53110 auto clock is shown in
Figure 1. Connection diagrams for this device are shown
on the front page. Unless otherwise indicated, the
following discussions are based on Figure 1.

its display (7 segments per digit), only 11 outputs are
required. Note that the MM53110 actually provides 12
outputs (4 digit-grid drive outputs plus 8 segmentanode drive outputs). The additional "segment" drive
is provided to accommodate displays which feature a
colon. The colon output is switched at 1/2 Hz rate with
1 1/2 seconds ON and 1/2 second OFF to provide a
bl inking colon as a short-time indication that the clock
is operating. A zero-blanking circuit suppresses the zero
that would otherwise sometimes appear in the tens-ofhours display. Each digit is sequentially enabled for a
period of ~0.5 ms.

Crystal Oscillator (Pins 21 and 22): .A quartz crystal,
resonant at 2.097152 MHz, 2 capacitors and 1 resistor
together with the internal MOS circuits form a crystalcontrolled oscillator as shown in Figure 2. Varying 1 of
the capacitors allows precise frequency setting. For test
purposes, Osc. 1 is the input and Osc. 2 is the output of
an inverting amplifier.
Time Setting (Pin 20): Time setting is accomplished via
the set input pin. If this input is a logic high, the minutes
counter will advance at a 2 Hz rate with no carry to the
hours counter and will also cause seconds counter to
reset. If the set input is a logic low, the hours counter
will advance at a 2 Hz rate, minutes and seconds counter
will continue in real time. If the set input is floating, the
MM53110 will display normal time.

When time division multiplexing vacuum-fluorescent
displays, it is necessary to inhibit the segment drive
voltage(s) for a short time during inter-digit transitions.
The MM53110 auto clock' utilizes an interlaced output
sequence and inter-digit blanking circuitry to prevent
display ghosting problems. The digit sequence is: (1)
digit no. 1 (unit minutes), (2) digit 3 (unit hours), (3) digit
no. 2 (ten's of minutes), (4) digit no. 4 (ten's of hours).
Both segment data and digit enables are blanked. Figure
3 is a timing diagram which illustrates output timing
for the MM53110.

Output Multiplex Operation: Outputs from the appropriate internal counter are time division multiplexed to
provide digit-sequential access to the data. Thus, instead
of requiring 28 leads to interconnect a 4-digit clock and

VSS

FIGURE 2. Crystal Oscillator

DIGIT NO.1 VSS
UNITMINS OV

VSS/2

DIGIT NO.3 VSS
UNIT HOURS
OV

VSS/2

DIGIT NO.2 VSS
10'S MINS OV

VSS/2

OIGIT NO.4 VSS
10'S HOURS OV

VSS/2
OV

VSS

VSS/2

SEGMENTS
AND COLON

OV

ov -+---H
ov - t - - + t - - t....

OV

OV

100% Brightness

50% Brightness

FIGURE 3. MM531 10 Output Timing Diagram

5-33

Functional Description

(Continued)

Brightness Control (Pin 14): Since display brightness is
a function of digit and segment voltage, a capability of
directly driving the output logical high voltage results in
a brightness control. See Figure 6 for output voltage vs
brightness control voltage. If the day-night input is
switched to a logical low, the brightness input will be
forced to VSS, thus supplying VSS to the outputs for
100% brightness. If the day-night input is switched to a
logical high, the display brightness will vary from 0% to
100% depending on the magnitude of the voltage applied
to the brightness input. This is illustrated in Figure 3.

Ignition Input (Pin 16): This input is provided with an
internal 1 Mn pull-down to VDD and switch debounce
circuitry. If the ignition input is switched to a logical
low, or left floating, all outputs will go to VDD and the
time set and elapsed time inputs wiil be disabled. Since
the pulse output goes to VOO, the voltage doubler will
become disabled and the battery voltage will be applied
to VSS. If the ignition input is switched to a logical high,
all outputs and inputs will be enabled. The voltage
doubler will also be enabled and will allow VSS to
increase to the zener reference voltage_

Output Circuits (Pins 1-12): All display output drivers,
both digit and segment outputs, are push-pull drivers.
The pull-ups are enhancement devices with sources
common to the brightness input and the pull-downs are
depletion devices with drains common to VDD (Figure
4). Thus, all outputs are capable of sourcing and sinking
the required display currents. Figure 5 illustrates one
method of interfacing these outputs to· a vacuumfluorescent display. Figure 5 also shows the entire
circuitry required for a complete automobile clock
application.

Day-Night Input (Pin 15): This input is provided with
debounce circuitry and a ,I Mn pull-down to VOD. If
the day-night input is switched to a logical low, or left
floating, the MM53110 will force the brightness input to
VSS, thus providing the maximum voltage to the display.
If the day-night input is switched to a logical high, the
digit and segment output high ,levels can be varied from
OV to VSS by varying the brightness input voltage from
OV to VSS respectively. The brightness input current
will be the total of the digit and segment average currents.

Pulse Output (Pin 13): This output drives the external
DC/DC converter circuitry with a frequency of 8192 Hz
and a 25% duty cycle (31 f.1S at VSS and 91 f.1S at VDD).
The pulse output will start in a low state under any
combination of battery and ignition voltages. If the
ignition input is switched OFF (VDD), the pulse output
will go to VDD, thus disabling the DC/DC converter.
Figure 5 illustrates the interface of this output to the
voltage doubler circuit.

Elapsed Time Input (Pin 18): If this input is switched
to a logical low, the elapsed time counter will reset and
display 0:00. If the input is switched to a logical high,
the MM53110 will display elapsed time. If left floating,
the MM53110 will display real time_ During elapsed time
display, the MM53110AA will display hours-minutes up
to 19:59; the next count will be 0.00. The MM53110AB
will display minutes-seconds up to 19:59, the next count
will be 0:00_ The elapsed time input also contains
debounce circuitry_

VSS

DAY/NIGHT

~

BRIGHTNESS

TYPICAL DIGIT
OR SEGMENT
OUTPUT

VSS

n (DATA)

VOO

VDD

FIGURE 4. Output Circuit

5-34

Functional Description (Continued)
BATTERY 1+) GND

~

R5
lJO
JW

IGNITIDN 1+)

1.
!

!

SET
MINUTES

R2
41k

DISPLAY ELAPSED TIME

1

r-O-+0 DISPLAY REAL TIME

r<>--+0RUN

RESET ELAPSED TIME

ISET
HDURS

L1
2.2 mH
16

~I

...

17

+ Cl

IGN

20

18

TIME SET

ELAPSED TIME

VSS

Ml
MID

T411'F
J5V
Dl
25V

HI
MM5Jllo
MDS CLDCK
122 PINS)

~~

HID

Y"

'Y

lJ

BRIGHTNESS \ '

DSC 1

g

DSC 2 VDD DIN

21

22.£9

RJ
10M

15

14

1

f

2

.

GJ

4

c

b

5

a

rr

MUr

-~CJ

~5-JoPF

JoPF'J'

-=

R4
41k

~I

.... 1

FIGURE 5. Typica) Application for MM53110

5·35

OI11

CD~~N!

VACUUM·FLUDRESCENT

CDLDN\

d

1

..AAwy

C2- .....

DASH
LAMPS 1+)

f----l I
G2 G

PULSE

2.091152 MHz

MARKER
LAMPS 1+)

8
6

G4

Ri

...A~k

12

:

I

a

b

II

c

d

•

f

g

F

r0-

~
:

~

1

~

~National

Digital Clocks

~ Semiconductor
MM53113 Digital Alarm Clock
General Description
The MM53113 digital alarm clock is a monolithic MOS
integrated circuit utilizing P-channel low-threshold,
enhancement mode and ion-implanted depletion mode
devices. It provides all the logic required to build several
types of clocks and timers. Four display modes (time,
seconds, alarm and sleep) are provided to optimize
circuit utility. The circuit interfaces directly with 7segment fluorescent tubes, and requires only a single
power supply. The timekeeping function operates
from either a 50 or 60 Hz input, and the display for·
mat may be either 12 hours (with leading-zero blanking and AM/PM indication) or 24 hours. Outputs
consist of display drives, sleep (e.g., timed radio turn
offl. and alarm enable. Power failure indication is
provided to inform the user that incorrect time is
being displayed. Setting the time cancels this indication. The device operates over a power supply range
of 8-29V and does not require a regulated supply.
The MM53113 is packaged in a 40-lead dual-in-line
package.

• AM/PM outputs
}
• Leading-zero blanking 12-hour format
• 24-hour alarm setting
• All counters are resettable
• Fast and slow set controls
• Power failure indication
• Blanking capability
• Elimination of illegal time display at turn on
• Direct interface to fluorescent tubes
• 9-minute snooze alarm
• Presettable 59-minute sleep timer

Applications
•
•
•
•
•
•
•
•
•
•
•

Features
• 50 or 60 Hz operation
• Single power supply
• low power dissipation (36 mW at 9V)
• 12 or 24-hour display format

Alarm clocks
Desk clocks
Clock radios
Automobile clocks
Stopwatches
Industrial clocks
Portable clocks
Photography timers
Industrial timers
Appliance timers
Sequential controllers

Block and Connection Diagrams
OUTPUT
COMMON
SOURCE
1212~EHl~~~

2J

<>-"'--------------------,
<>-"'-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-,

Dual·1 n·Line Package

50/60 HZ
INPUT

40 PM DUI

AM OUTPUT

"

1 HI OUT
38 12/24 HR SElECT
J7
BLANKING IN

lDHRS-b&c
HRS - f

HRS-g
HRS

"
"

-8

J5

HRS-b

AL~~~

+!'--_-,

HRS-d

ALARM
OFF

DIGIT
SNOOZE

TO 10'8
OFMINS
DIGIT

10MINS-a& d
lDMINS-b

IDMINS-e
IOMINS-c

16 ·22

0-'-'---'----------------+1

0-.:'''-'--------________--1-1
SECON~~ 0-.:'''-'------------------1-1
AlA~~

DIGIT

MINS-f
MINS-g
MINS-a
MINS -b

BLANKING

37

BLANKiNG'

INPUT

33

DETECTOR

MINS-c

SLDWSET~

FAST SET

TO MINS

J2

HRS -e

IDMtNS-I
IOMINS - g

SLEEP
OUT

SLEEP DIS

JJ

HRS-c
TO HRS

10

J1
3Q

34

<>---+

28 Von

14

21 VSS
SLEEP OUT
26
ALARM Off IN

15

"

18

"
"

19

22

20

!I

11

2l

FIGURE 2

5·36

ALARM DISPLAY IN
SLEEP DISPLAY IN

13

VOD~

FIGURE 1

SECONDS DISPLAY IN

29

Order Number MM53113N
See Package 24

"
"

FAST SET IN
SLOW SET IN

12

TOPVIEW

VSS 0-----..

5[1/60 Hz SElECT
50/60 Hz IN

ALARM OUT
SNOOZE IN

OUT COMMON SOURCE
MINS-t;:
MINS-d

Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)

VSS + 0.3 to VSS - 30V
-25°C to +70°C
--65°C to +150°C
300°C

Electrical Characteristics
TA within operating range, Vss = 21V to +29V, VDD = OV, unless otherwise specified.
PARAMETER

CONDITIONS

Power Supply Voltage

VSS (VDD = OV)

Power Supply Current

No Output Loads

MIN

TVP

21

29

4
5

VSS= 8V
VSS = 29V
Counter Operation Voltage

MAX

(Note 2)

8

50/60 Hz Input Frequency Voltage
Logical High Level

29
dc

VSS-l

50 or 60

10k

V

mA
mA
V
Hz
V
V

Logical Low Level

VDD

VDD

VSS
VDD+l

Blanking Input Voltage
Logical High Level
Logical Low Level

VSS-l

VSS
VDD

VSS
VSS-4

V
V

VSS
VDD

VSS
VDD+2

V
V

B

V

1

p.A
p.A

1

p.A
p.A

1

p.A

VDD

All Other Input Voltages
Logical High Level
Logical Low Level

Internal Depletion Device to VDD

VDD

Power Failure Detect Voltage

(VSS Voltage), (Note 1)

1

Output Currents·,
1 Hz Display

VSS = 21V to 29V,
Output Common = VSS

VSS-l

Logical High Level

VOH = VSS - 2V

Logical Low Level, Leakage

VOL = VDD

VSS

UNITS

1500

1O's of Hours (b & c), 10's of Minutes
(a & d)
Logical High Level

VOH = VSS -2V

Logical Low Level, Leakage

VOL= VDD

All Other Display, Alarm and Sleep Outputs
Logical High Level
Logical Low Level,. Leakage

VOH = Vss -2V
VOL=VDD

1000

p.A

500

Note 1: The power fail detect voltage is O.25V or more above the hold count voltage. The power-fail latch trips into power·fail mode at least
O.2SV above the voltage at which data stored in the time latch is lost.
Nota 2: Output drive capability is not guaranteed over the range of 8-21V.

5-37

Functional Description
A block diagram cif the MM53113 digital alarm clock is
shown in Figure 1. The various display modes provided
by this clock are listed in Table I. The functions of the
setting' controls are listed in Table II. Figure 2 is a'
connection diagram. The following discussions are based
'
on Figure 1.

fluorescent tube displays, VSS or a display brightness
control voltage is permanently connected to this pin.
Since the brightness of a fluorescent tube display is
,dependent on the anode (segment) voltage, applying a
variable voltage to pin 23 results in a display brightness
control. This control is shown in Figure 6.

50 or 60 Hz Input (pin 35): A shaping circuit (Figure 3)
is provided to square the 50 or 60 Hz input. This circuit
allows use of a filtered sinewave input. The circuit is a
Schmitt Trigger that is designed to provide about 6\1 of
hysteresis. A simple RC filter, such as shown in Figure 6,
should be used to ,remove possible line-voltage transients
that could either cause the clock to gain time or damage
th~ device. The shaper output drives a counter chain
which performs the timekeeping function,

12 or 24-Hour Select Input (pin 38): By leaving this pin
unconnected, the outputs for the most-significant
display digit 11 O's of hours) are programmed to provide
a 12-hour display format. An internal depletion pull
down device is again provided. Connecting this pin
to VSS programs the 24-hour display format. Segment connections for 10's of hours, in 24-hour mode
are shown in Figure 5b.
Power Fail Indication: If the power to the integrated
circuit drops indicating a momentary ac power failure
and possible loss of clock, the power fail latch is set.
The power failure indication consists of a flashing of the
AM or PM indicator at a 1 Hz rate. A fast or slow set
input resets an internal power failure latch and returns
the display to normal. In the 24-hour format, the power
failure indication consists of flashing segments "c" and
"f" for times less than 10 hours, and of a flash ing
segment "c" for times equal to or greater than 10 hours
but less than 20 hours; and a flashing segment "g" for
times equal to or'greater than 20 hours.

50 or 60 Hz Select Input (pin 36): A programmable
prescale counter divides the input line frequency by
either 50 or 60 to obtain a 1 F/ztime base. This'counter
is programmed to divide by 60 simply by leaving pin 36
unconnected; pull-down to VOO is provided by an
internal depletion device. Operation at 50 Hz is programmed by connecting pin 36 to VSS.
Display Mode Select Inputs (pins 30-32): In the
absence of any of these three inputs, the display drivers
present time-of-day information to the app~opriate
display digits. Internal pull-down depletion devices allow
use of simple SPST switches to select the display ,mode.
If more than one mode is selected, the priorities are as
noted in Table I. Alternate display modes are selected
by applying VSS to the appropriate pin. As shown in
Figure 1 the code converters receive time, seconds, alarm
and :sleep information from appropriate points in the
clock circuitry. The display mode select inputs control
the gating of the desired data to t~e code converter
inputs and ultimately (via output drivers) to the display
digits.

Alarm Operation and Output (pin 25): The alarm
comparator (Figure 1) senses coincidence between the
alarm counters (the alarm setting) and the time counters
(real time). The comparator output is used to set a latch
in the alarm and sleep circuits. The latch outputenables
the alarm output drive (Figure 4), the MM53113 output
that is used to control the external alarm sound generator. The alarm I,atch remains set for 59 minutes, during
which, the alarm will therefore sound if the latch output
is not temporarily inhibited by another latch set by the
snooze alarm input (pin 24) or reset by the alarm "OFF"
input (pin 26). If power fail occurs and power comes'
back up, the alarm output will be in high impedance
state.

Time Setting Inputs (pins 33 and 34): Both fast and
slow setting inputs are provided. These inputs are
applied either singly or in combination to obtain the
control functions listed in Table II. Again, internal
pUll-down depletion devices are provided; application of
VSS' to these pins effects the control functions. Note
that the control functions proper are dependent on the
selected display mode. For example, a hold-time control
function is obtained by selecting seconds display and
actuating the slow set input. As another example, the
clock time may, be reset to 12:00:00 AM, in the ,12-hour
format (00:00:00 in the 24-hour format), by selecting
seconds display and actuating both slow and fast set
inputs.,

Snooze Alarm Input (pin 24): Momentarily connecting
pin 24 to VSS inhibits the alarm output for between 8
and 9 minutes, after which the alarm will again be
sounded. This input is pUlled-down to VOO by an
internal depletion device. The snooze alarm feature may
be repeatedly used during the 59 m ihutes in which the
alarm latch remains set.
Alarm "OFF" Input (pin 26): Momentarily connecting
pin 26 to VSS resets the alarm latch and thereby silences·
the alarm. This input is also 'returned to VOO by an
internal depletion device. The momentary alarm "OFF"
input also readies the alarm latch for the next comparator output, and the alarm will automatically sound again
in 24 hours (or at a new alarm setting). If it is desired
to silence the alarm for a day or more, the alarm "OFF"
input should remain at VSS.

Blanking Control Input (pin 37): Connecting 'this
Schmitt Trigger input to VOO places all display drivers
in a non-conducting, high-impedance state, thereby
inhibiting the display, (see Figures 3 and 4). Conversely,
VSS applied to this input enables the display.
Output Common Source Connection (pin 23): All
display output drivers are open-drain devices with all
sources common to pin 23 (Figure 4). When using

Sleep Timer and Output (pin 27): The sleep output
at pin 27 can be used to turn off a radio after a

5-38

Functional Description

(Continued)

desired time interval of up to 59 minutes. The time
interval is chosen by selecting the sleep display mode
(Table I) and setting the desired time interval (Table II).
This automatically results in a current-source output
via pin 27, which can be used to turn on a radio
(or other appliance). When the sleep counter, which
counts downwards, reaches 00 minutes, a latch is reset

and the sleep output current drive is removed, thereby
turning off the radio. The turn off may also be
manually controlled (at any time in the countdown) by
a momentary VSS connection to the snooze input
(pin 24). The output circuitry is the same as the other
outputs (Figure 4).

VOO

50/60 HZ

BI~:~JI~~ >-+---1

50/60 Hz

INPUT

]0-....-

. . ~~~~~;N~R
SIGNAL

VSS

FIGURE 3. 50/60 Hz or Blanking Input Shaping Circuit

*OUTPUT COMMON SOURCE BUS (PIN 23)

li(OATA)~~
---f

BLANKING
(FROM
SHAPER)

OUTPUT
(OPEN DRAIN)

VSS

* Alarm

and sleep output sources are connected to VSS:
blanking is not applied to these outputs.

FIGURE 4. Output Circuit

PIN 39
! Hz
PIN 40
PM

PIN!
AM

PIN!
AM

PIN 40
PM

PIN 2
b &c

NC

-"::'"""":"+-NC

(a) 12-Hour Display Format

(b) 24-Hour Display Format

FIGURE 5. Wiring Ten's-of-Hours Digit

5-39

PIN 2

b& c

Functional Description

(Continued)
TABLE I.MM53113 DISPLAY MODES

'SELECTED
DISPLA Y MODE

DIGIT NO. 2

·DIGIT NO.1

DIGIT NO. 3

DIGITNO.4

Time Display

10's of Hours & AM/PM

Hours

lO's of Minutes

Minutes

Seconds Display

Blanked

Minutes

10's of Seconds

Seconds

Alarm Display

10's of Hours & AM/PM

Hours

10's of Minutes

Minutes

Sleep Display

Blanked

Blanked

10's of Minutes

Minutes

* If more

than one display mode input is applied, the display priorities are in the order of Sleep (overrides all othersL Alarm,

Seconds, Time (no other mode selected).

TABLE II. MM53113 SETTING CONTROL FUNCTIONS
SELECTED
DISPLA Y MODE

CONTROL
INPUt

CONTROL FUNCTION

*Time

Slow
Fast
Both

Minutes Advance at 2' Hz Rate
Minutes Advance at 60 Hz Rate
Minutes Advance at 60 Hz Rate

Alarm

Slow
Fast
Both
Both

Alarm
Alarm
Alarm
Alarm

Seconds

Slow
Fast

Sleep

Minutes' Advance at 2 Hz Rate
Minutes Advance at 60 Hz Rate
Resets to 12:00 AM (12·hour format)
Resets. to 00:00 (24-hourformat)

Both
Both

.Input to Entire Ti,me Counter is Inhibited (Hold)
Seconds and 'lO's of Seconds Reset to Zero Without
a Carry to Minutes
Time Resets to 12:00:00 AM (12-hour format)
Time Resets to 00:00:00 (24-hour format)

Slow
Fast
Both

Substiacts Count at 2 Hz
Substiacts Count at 60 Hz
Substracts Count at. 60 Hz

"

*When setting time sleep minutes will decrement at"rate of time counter, until the sleep counter reaches 00 minutes
(sleep counter will not recycle).

Typical Application
Figure 6 is a schematic diagram of a general purpose alarm clock using the MM53113 and a fluorescent tube display.

3

1156~~~

BRIGHTNESS
CONTROL

t-~~~~t-~~v~
27.

lav 100k
OUTPUT COMMON
SOURCE
'-<~-1~-1~-+i50160 HI INPUT

ALARM
DRIVE

MM53113

....- .............---t-jVDD

1I.~*--

SLEEP

lD'S OF HOURS

UNIT HOURS

FIGURE 6:

5·40

. ID'S OF MINUTES

UNIT MINUTES

OUT

SLEEP
DRIVE

Digital Clocks

~National

~ Semiconductor

MM53124 Automobile Clock and Elapsed Timer
General Description
The MM53124 is a monolithic MOS integrated circuit
utilizing P-channel low-threshold, enhancement mode
and ion-implanted depletion mode devices. The circuit is
designed for continuous direct-drive vacuum fluorescentdisplays. The display format is 12 or 24-hours for real
time display and 24-hours for elapsed time display with
leading zero blanking and colon indication. The timekeep-ing function operates from a 4 MHz crystal-controlled
source. The circuit is available in a dual-in-line plastic,
40·pi n package.

.. Elapsed time hold mode
• Time hold mode and seconds reset for easy synchronizing
• Crystal-controlled oscillator (4.194304 MHz)
• Push to read feature if ignition OFF
• Brightness control capability
• Day/night control
• DC to DC converter pulse output
• Direct interface to vacuum fluorescent displays
.. Low standby power dissipation

Features
•
•
•

12-hour or 24-hour real time display format
24-hour elapsed time display
Elapsed time rolls over from minutes-seconds display
to hours-minutes display after accumulated time
reaches 1 hour

Applications
•

Automobile clocks

•
•

Desk clocks
Elapsed timer

Block and Connection Diagrams
Dual-In-Line Package
PULSE OUTPUT

_voo

osc IN

~vss

asc OUT

40 12/24

Voo

39

TEST
PU LSE OUTPUT
E1

AOI

Cl
12/24

Sl
S3

G2
E2
02

DAY/NIGHT

C2 10

IGN

GJ 11
12
E3
13
C3
G4 14

BRIGHTNESS

E'

MM53124

osc OUT

38 usc IN
31 G1
J6
F1
35
Bl
34
'2
3J
02
32
B2
31
COLON
30 Fl
29 AD]

28 BJ21 F4

15

26 A4

2'

D.

B'

24 BRIGHTNESS

23
SeGMENT OUTPUTS

IGNITION

22
DAV/NIGHT
21

vss

FIGURE 1

TOP VIEW

Order Number MM53124N
See Package 24

5-4.1

Absolute Maximum Ratings
Voltage at Any Pin
. VSS + 0.3V to VSS - 26V
Operating Temperature
-40°C to +85°C
Storage Temperature
-u5°C to +150°C
Lead Temperature (Soldering. 10 seconds) .
300°C

Electrical Characteristics

PARAMETER
VSS Supply Voltage
VSS Supply Voltage
ISS Supply Current

TA within operating range. V DO = ov unless otherwise specified.

MIN
5
6

CONDITIONS
No Loss of Memory
Operational
No Output Load (@ 25°C)

TYP

MAX
25
7.5

UNITS
V
V
mA

Input Pull-Down Current Source
@ Y,N .,; VSS. (lSINK) @ 25°C
V IL Input Logical "0"
V,H Input Logical"l"

10
0
VSS-l

VSS +0.3

Il A
V
V

Ignition Input and Day/Night
Input

Input Pull-Down Current Source
@ Y,N = VSS. (lSINK) @ 25°C
V,L Input Logical "0"
V,H Input Logical "1"

10
0
5

100
1.2
VSS +0.3

Il A
V
V

AD 1. AD3 Segments'
(Brightness =VSS)

VOL = 0.5 x VSS (lSINK)
VOH =VSS -1.5. VSS ~ 9V. (lSOURCE)

10
0.8

IlA
mA

All Other Segments
(Brightness = VSS)

VOL
VOH

=0.5 x VSS. (lSINK)
=VSS -1.5; VSS ~ 9V. (lSOURCE)

10
0.4

/1A
mA

SI. S2. S3 and 12/24 Hour
Select Inputs

Pulse Output
OSC IN,OSC OUT

.VOH = VSS - 2. Logical "I"

Output Impedance. Logical "0"

30
1

Oscillator Frequency

DC

100
1

120

kn
mA

4.194304

4,2

MHz

Functional Description
Crystal Oscillator (Pins 38 and 39): A quartz crystal,
resonant at 4.194304 MHz. 2 capacitors and 1 resistor
together with the interna.1 MOS circuits form a crystalcontrolled oscillator as shown in Figure 3. Varying the
capacitor on OSC OUT (pin 39) allows precise frequency
setting.

Pulse Output (Pin 3): In addition to being the crystal
oscillator calibration reference. this output also drives
the external DC/DC converter circuitry. if required. The
frequency is 8192 Hz and the duty cycle is 75% at VSS.
25% at VDD. If the ignition input is switched OFF

(VDD). the pulse output will go to VDD. thus disabling
the DC/DC converter.
Ignition Input (Pin 23): This input is provided with an
internal pull-down resistor to VOD and switch debounce
circuitry. If the ignition input is switched low (towards
VDD) or left floating. all outputs will go to VDD and all
inputs except for S2 are disabled. If S2 is connected to
VSS at this time. the segment drivers will display time
for as long as the S2 contact is made. When the pulse
output goes to VODas a result of ignition being turned
OFF. the voltage doubler will become disabled and the
battery voltage will be appl ied to V SS.

5-42 '

Functional Description

(Continued)

Segment Outputs (Pins 4-17, 25-37): All segment output
drivers are push-pull structures. The pull·ups are enhancement devices with sources common to the Brightness
input: The pull-downs are depletion devices with drains
common to VDD. Figure 2 shows a typical segment
output circuit with 2 of such push-pull devices.

night mode and the segment outputs will track the
voltage at the Brightness pin.
12/24 Hour Input (Pin 40): This input is provided with
an internal pull-down resistor to VDD. When this input
is switched low (to VDD) or left floating, real time will
be displayed in the 24-hour mode. When switched high
(to VSSI. real time will be displayed in the 12-hour mode.

Day/Night Input (Pin 22): This input is provided with an
internal pull-down resistor to VDD and switch debounce
circuitry. If the Day/Night input is switched low (towards
VDD) or left floating, the MM53124 will force the
Brightness input to VSS thus providing the maximum
voltage to the display. If the Day /Night input is switched
high (towards VSSI. the segment output drivers will
track the input voltage at the Brightness input.

S1, S2, S3 Switches (Pins 18, 19,20): The MM53124 has
4 functional modes and these switches control the mode
it is in. All 3 inputs are provided with internal pull-down
resistors to VDD and input debounce circuitries. In
addition to the 4 functional modes, the ignition input
can also inhibit S1 and S3 and puts S2 in a push-to·read
mode. When ignition is initially turned from OFF to
ON, the clock will be in the display time mode 1. If
minutes are incremented, seconds counter is reset and
held until clock is returned to display time mode 1.

Brightness Control (Pin 24): When the Day/Night input
is switched high (towards Vssl. the MM53124 is in the

VsS

E - Enhancement
D - Depletion

OAY/NIGHT-;

E

....- - - - - - -.....-BRIGHTNESS

SEGMENT OUTPUT

SEGMENT OUTPUT

FIGURE 2. Segment Output Circuit

130

JW

. . .-"M~----

IGNITION~

________""I

47k

2.Zmh
BATTERY (+I~.J"Y'I"Y'-...._
lBV
ZENER

lN4001

23
IGN
21

...._"'~",-.:.:.j
3

Vss
MM53124
PULSE
OSC IN
3B

22 47k
MARKER
DINt--MI'v--LAMPS
241N914
DASH
BRIGHTNESS
LAMPS
NC

OSC OUT
39

FIGURE 3

5-43

Functional Description

(Continued)

Tables .I and II illustrate the different modes. Switch
closure is connection to VSS.

Test Sequence: A test pin is supplied for testing purposes. This pin is normally low and raiSing it high
toward VSS will put the IC in the test mode. In this
mode, 128 Hz is output on the Pulse Output pin and
internal real time and elapsed time counters are sped
up by a factor of 8192. If the test pin and the ignition
input pin are held at VSS, a lamp test condition exists
and the real time counter is reset to 12:00.

In the elapsed time mode, the display shows minutesseconds until 1 hour has been accumulated. The display
then rolls over to hours-minutes. The colon output after
rollover will be continuously flashing at a 1/2 Hz rate.
The duty cycle of the flashing colon is 75% ON and 25%
OFF. The colon does not flash in the real time display
mode.

TABLE I. IGNITION IS ON
NO.

1

2

3

4

SWITCH FUNCTION

SWITCH CLOSURE

MODE

S1
S2

Display Time

Set Hour

Set Minutes

Elapsed Time

Any Mode 1-4

Changes to Set Hours Mode 2
Changes to Elapsed Time Mode 4

S3

Does Nothing

Sl

Ghanges to Set Minutes Mode 3

S2
S3

Changes to Elapsed Time Mode 4,

Sl

Changes to Display Time Mode 1

S2
S3

Changes to Elapsed Time Mode 4

S1

Starts Elapsed Timer

S2
S3

Stops and Holds Elapsed Timer

51 and 52 Together

Changes to Elapsed Time Mode 4

Increments Hours at 2 Hz Rate

Increments Minutes at 2 Hz Rate

Changes to Display Time Mode 1

and Resets Elapsed Timer

TABLE.!I. IGNITION IS OFF
SWITCH CLOSURE

Sl
S2

SWITCH FUNCTION

No Action
Displays Real Time, Hours·Minutes for

as long as 52 is Closed
S3

No Action

5-44

~National

Digital Clocks

~ Semiconductor

MM53224 Automobile Clock and Elapsed Timer
General Description
The MM53224 is a monolithic MOS integrated circuit
utilizing P-channel low-threshold, enhancemer.t mode
and ion-implanted depletion mode devices. The circuit is
designed for continuous direct-drive vacuum fluorescent
displays. The display format is 12 or 24-hours for real
time display and 24-hours for elapsed time display with
leading zero blanking and colon indication. The timekeeping function operates from a 4 MHz crystal-controlled
source. The circuit is available in a dual-in-line plastic,
40-pin package.

• Elapsed time hold mode
• Time hold mode and seconds reset for easy synchronizing
• Crystal-controlled oscillator (4:194304 MHz)
• Push to read feature if ignition OFF
• Brightness control capability
• Day/night control
• DC to DC converter pulse output
• Direct interface to vacuum fluorescent displays
" Low standby power dissipation

Features
•
•
•

12-hour or 24-hour real time display format
24-hour elapsed time display
Elapsed time rolls over from minutes-seconds display
to hours-minutes display after accumulated time
reaches 1 hour

Applications
•
•
•

Automobile clocks
Desk clocks
Elapsed timer'

Block and Connection Diagrams
Dual-In-Line Package
PULSE OUTPUT

_vDD
rvss

12/24

40 12124

VDD

J9

fffi

3.

PULSE OUTPUT

CSC OUT
nSCIN

31 G1
36

EI
ADI
CI
G2
E2

Ft

Bt
F2

A2
MM53224

B4
24 BRIGHTNESS

23
SEGMENT OUTPUTS

22
21

FIGURE 1

'TOP VIEW'

Order Number MM53224N
See Package 24

5-45

IGNITION
DAY/NIGHT

Vss

Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)

Electrical Characteristics

VSS + 0.3V to VSS - 26V
~O°C to +85°C
-65°C to +150°C'
300°C

TA within operating range; VD D =

ov unless otherWise specified.

MIN
5

PARAMETER
VSS Su~ply Voltage
VSS Supply Voltage
ISS Supply Current

CONDITIONS
No Loss of Memory
Operational
No Output Load (@ 25°C)

S1, S2, S3 and 12/24 Hour
Select Inputs

Input Pull·Down Current Source
@ VIN = VSS, (lSINK) @ 25°C
VIL Input Logical "0"

TYP

MAX

UNITS
V
V
mA

6

25
7.5

10
0

100
1

VSS-l

VSS +0:3

VI L Input Lo~ical "0"
VIH Input Logical "I"

10
0
5

100
1.2

AD1, AD3 Segments
(Brightness = VSS)

VOL = 0.5 x VSS (lSINK)
VOH = VSS -1.5, VSS ~ 9V, (lSOURCE)

10
0.8

J1A
mA

All Other Segments
(Brightness = VSS)

VOL = 0.5 x VSS, (ISINK)
VOH = VSS -1.5, VSS ~ 9V, (lSOURCE)

10
0.4

J1A
mA

Output Impedance, Logical "0"
YaH = VSS - 2, Logical "I"

30
1

Oscillator Frequency

DC

VIH Inpu,t Logical "I"
Ignition Input and Day/Night
Input

Pulse Output
OSC IN, OSC OUT

J1A
V
V

"

Input Pull·Down Current Source
@

VIN = VSS, (lSINK)

@

25°C

VSS + 0.3

120

J1A

V
V

,

kn
-rnA

4.194304

4.2

MHz

Functional Description
Crystal Oscillator (Pins 38 a~d' 39): A quartz crystal,
resonant, at 4.194304 MHz, 2 capacitors and 1 resistor
together with the internal MaS circuits form a crystal·,
controlled oscillator as shown in Figure 3. Varying the
capacitor on OSC OUT (pin 39) allows precise frequency
setting.

Pulse O~tput (Pin 3): In addition to being the crystal
oscillator ,calibration reference, this output also drives
the external DC/DC converter circuitry, if required. The
frequency is 32,768Hz and the duty cycle is 50% at VSS,
50% at VDD.lf the i\lnition input is switched OFF

(VDD), the pulse output will go to VDD, thus disabling
the DC/DC converter.
Ignition Input iPin 23): This input is provided with an
internal pull·down resistor to VDD and switch debounce
circuitry. If the ignition inpu,t is switched low (towards
VDD) or left floating, all outputs will go to VDD and all
, inputs except for S2 are disabled. If S2 is connected to
VSS at this time, the segment drivers will display time
, for as long as the S2 contact is made. When the pulse
output goes to VDD as a result of ignition being turned
OFF, the voltage doubler will become disabled and the
battery voltage will be applied to VSS.

5·46

Functional Description

(Continued)

Segment Outputs (Pins 4·17, 25·37): All segment output
drivers are push'pull structures. The pull-ups are enhancement devices with sources common to the Brightness
input. The pull-downs are depletion devices with drains
common to VDD. Figure 2 shows a typical segment
output circuit with 2 of such push-pull devices.

night mode and the segment outputs will track the
voltage at the Brightness pin.
12/24 Hour Input (Pin 40): This input is provided with
an internal pull-down resistor to VDD. When this input
is switched low (to VDD) or left floating, real time will
be displayed in the 24-hour mode. When switched high
(to VSS), real time will be displayed in the 12-hour mode.

Day/Night Input (Pin 22): This input is provided with an
internal pull-down resistor to VDD and switch debounce
circuitry. If the Day/Night input is switched low (towards
VDD) or left floating, the MM53224 will force the
Brightness input to VSS thus providing the maximum
voltage to the display. If the Day/Night input is switched
high (towards Vssl. the segment output drivers will
track the input voltage at the Brightness input.

S1, S2, S3 Switches (Pins 18,19,20): The MM53224 has
4 functional modes and these switches control the mode
it is in. All 3 inputs are provided with internal pull-down
resistors to VDD and input deboullce circuitries. III
addition to the 4 functional modes, the ignition input
can also inhibit S1 and S3 and puts S2 in a push-to-read
mode. When ignition is initially turned from OFF to
ON, the clock will be in the display time mode 1. If
minutes are incremented, seconds counter is reset and
held until clock is returned to display time mode 1.

Brightness Control (Pin 24): When the Day/Night input
is switched high (towards Vssl. the MM53224 is in the

vss
E - Enhancement

o-

Depletion

OAYINIGHT--i

E

...- - - - - - - -....-SRIGHTNESS

"",,,,1;:' ~'
voo

(O~TAJ

SEGMENT OUTPUT

voo
SEGMErn OUTPUT

FIGURE 2_ Segment Output Circuit

130

IGNITION~. ....I\~3\,,~1.-_ _ _ _ _ _ _ _---.

47k

1.1 mh

23
IGN
21
.....--.I-+~ VSS

22 47k
MARKER
OIN-"""'"-LAMPS

lN4001

BATTERY (+J ~..ry--,,-y""'-...-

10k

lBV
ZENER

-=- -=-

241N914

MM53224
3

PULSE

NC

T
+

500pFd

BRIGHTNESSF-I---'-'-+

V
DD

Note."MM5405 pin connections shown in parenthesis.

29(12)

<>---'-'-+

FIGURE 1

5-49

It)

~

Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature

300"C
(Note 1)

Storage Temperature

VSS to VSS +12Y
-2S'C to +70'C
-6S'C to +IS0'C

N "'

Electrical Characteristics

T A within operating range, Voo = 7V to llV, Vss = OV, unless otherwise specified.

:E
:E

Power Supply Voltage

:E
:E

~

PARAMETER

lead Temperature (Soldering, 10 seconds)
Segment" Output Current

CONDITIONS

. .output Driving

MIN

~isplay

Functional Clock
Power Supply Current

TYP

MAX

9
7

S

VOO= 7V to llV

All Other Input Voltages
Logical Low Level
Logical High Level

Internal Oepletion Load to VOO

Power Failure Oetect Voltage.

(VOO Voltage), (Note 2)

de

SOar 60

10k

VSS
VOO

VSS+O.S

Hz
V

VOO
100

IJA

VSS
VOO-3

Logical Low, Sink

V

S

V

7

11

V

(Note 2)

11

V

1

Common Anode

(Figure5a)

Logical Low Level, Sink
1 Hz Oisplay
Logical High Level, Leakage
Logical Low Level, Sink
All Other Segment Oisplays
Logical High Level, Leakage
Logical Low Level, Sink
Output Current Levels

Common Cathode
1 D's of Hours (b & c), 10's of Minutes
(a&d)
Logical High Level, Source
Logical Low Level, Leakage

1

VOH = VSS +2
VOL = VSS+2
VOO = 9,V to l1V

Logical High Level, Leakage

V

VOO= llV

Output Current. Levels

10's of Hours (b & c), 10's of Minutes
(a & d)

VSS+O.S

VSS
VOO

V

VOO

Count Operating Voltage
Hold Count Voltage

mA
mA

VSS
VOO-3

Input Leakage

Logical High, Source

V

4

Logical Low Level
Logical High Level

Alarm and Sleep Outputs

V

11

No Output Loads

VOO = 7V
VOO=IIV
SO/60 Hz Input
Frequency

UNITS

11

IJA
mA

5

-

Output Common = VSS
VOH = VOO
VOL = VSS+2V

24

VOH= VOO
VOL = VSS +2V

36

VOH =VOO
VOL = VSS +2V

12

10

IJA
rnA

10

IJA
mA

10

IJA
rnA

(Note 1)

VOO =·9V to llV

(Figure 5b)

Output Common = VSS + 4
rnA

20

VOH = VSS + 1.5V

10

VOL = Vss

IJA

1 Hz Oisplay
Logical High Level, Source

VOH = Vss + 1.5V

Logical Low Level, Leakage

VOL =. Vss

All Other Segment Oispl.ays
Logical High Level, Source
Logical Low Level, Leakage

30

rnA
10

10

VOH = VSS + 1.5V

mA
10

VOL = VSS

IJA

IJA

Note 1: Segment output current must be limited to 15 rnA maximum by user; power dissipation must be limited to 900 mW at 7rf C and 1.2W

.

mW~

Note 2: The power-fail detect voltage is 0.25V or more above the hold count voltage. The power-fail latch trips into power-fail mode at least
0.25V above the vol"lge at which data stored in the time latch is lost.
.
Note 3: Power 'supply voltage should not exceed a maximum-voltage of 12V under any circumstances, such ~s during plug in. power UP. display
"ON"/"OFF", or power supply ripple. Doing so runs the risk of permanently damaging the device.

5-50

Functional Description
A block diagram of the MM5402, MM5405 digital
clock radio circuit is shown in Figure 1. The various
display setting modes are listed in Table I, and Table II
shows the setting control functions. The following
description is based on Figure 1 and refers to both
devices as they are electrically identical.

Time Setting Inputs: Both fast and slow setting inputs
are provided. These inputs are applied either singly or
in combination to obtain the control functions listed in
Table II. Again, internal depletion pull-up devices
are provided; application of VSS to these pins affects
the control functions. Note that the control functions
proper are dependent on the selected display mode.
For example; a hold-time control function is obtained
by selecting seconds display and actuating the slow set
input. As another example, the clock time may be reset
to 12:00:00 AM, by selecting seconds display and actuating both slow and fast set inputs.

50 or 60 Hz Input: A shaping circuit (Figure 3) is provided to square the 50 or 60 Hz input. This circuit
allows use of a filtered sinewave input. The circuit is a
Schmitt trigger that .is designed to provide about 0.8V
hysteresis. A simple RC filter such as shown in Figure 1,
should be used to remove possible line-voltage transients
that could either cause the clock to gain time cir damage
the device. The shaper output drives a counter chain
which performs the timekeeping function.

Output Common: All display output drivers are open
drain devices with' all the sources connected to output
common pin.' This pin can be used as a common source
or a common drain. When used as a common source,
this pin is connected to VSS and when used as a common drain, this pin is connected to VDD. This allows
the use of either common anode or common cathode
LED's for displays. Figure 5 shows these connections.

50 or 60 Hz Select Input: A programmable prescale
counter divides the input line frequency by either
50 or 60 to obtain a 1 Hz time base. This counter is
programmed to divide by 60 simply by leaving 50/
60 Hz select unconnected; pull-up to VDD is provided by an internal depletion load. Operation at 50 Hz
is programmed by connecting 50/60 Hz select to VSS.

12 or 24 Hour Select Input: By leaving this pin unconnected, the outputs for the most-significant display
digit (10's of hours) are programmed to provide a
12-hour display format. An internal depletion pullup device is again provided. Connecting this pin to'
VSS programs the 24-hour display format. Segment
connections for 10's of hours in 24-hour mode are
shown in Figure 6.

Display Mode Select Inputs: In the absence of any of
these three inputs, the display drivers present time-ofday information to the, appropriate display digits.
Internal depletion pull-up devices allow use of simple
SPST switches to select the display mode. If more than
one mode is selected, the priorities are as noted in
Table I. Alternate display modes are selected by applying VSS to the appropriate pin. As shown in Figure 1
the code converters receive time, seconds, alarm and
sleep information from appropriate points in the clock
circuitry. The display mode select inputs control the
gating of the desired data to the code converter inputs
and ultimately (via output drivers) to the display digits.

Connection Diagrams

Power Fail Indication: If the power to the integrated
circuit drops, indicating a momentary ac power failure
and possible loss of clock, all "ON" segments will
flash at 1 Hz rate. A fast or slow set input resets an
internal power failure latch and returns the display to
normal.

(Top Views)

Dual-I n-Line Package

Dual-in-Line Package
40

AM OUTPUT

39

10HRS-b&c

PM OUTPUT

PM OUTPUT

COLON (1 Hz)

COLON (1 Hz)

AM OUTPUT
10 HRS - b & c

HRS-I

12(24 HR SELECT

HRS-,

10 HR b 124·HR)

10 HR b 124·HR)

HRS -,

HRS -a

50/60 Hz SELECT

50/60 Hz SElECT

HRS-l

12/24 HR SELECT

HRS -b

50/60 Hz INPUT

HRS -d

FAST SET INPUT

FAST SET INPUT

HRS -c

SLOW SET INPUT

SLOW SET INPUT

HRS -e
10MINS-I
10MINS-,

lUMINS -a & d
10MINS-b

tOMINS-e
10MINS-c

MINS -I
MINS-,
MINS -a
MINS -b
MINS-e

11
12
13
14
15
16

17
18
19
20

HRS -b

50/60 Hz INPUT

SECOND DISPLAY INPUT
10

HRS -I

HRS -d

HRS-c
J2

SECOND DISPLAY INPUT

ALARM DISPLAY INPUT

ALARM DISPLAY INPUT

SLEEP DISPLAY INPUT

SLEEP DISPLAY INPUT

VDD

VOO

VSS

VSS

SLEEP OUTPUT

SLEEP OUTPUT

ALARM "OFF"INPUT

ALARM "OFF" INPUT

ALARM OUTPUT

ALARM OUTPUT

SNOOZE INPUT

SNOOZE INPUT

OUTPUT COMMON

OUTPUT COMMON

MINS-c

MINS-c

MINS-d

MINS-d

Order Number MM5402N
See Package 24

10

31

11

30

12

29

13

28

14

27

15

26

16

25

17

24

18

23

19

22

20

21

Order Number MM5405N
See Package 24

5-51

HRS- e

10MfNS-I
10MINS -g
lUMINS ;""a&d
10 MINS - b
10MINS-e
lUMINS-c
MINS-I
MINS-g
MINS-a
MINS-b
MINS-e

Functional Description

(Continued)

Alarm Operation and. Output: The alarm comparator
(Figure 1) senses coincidence between the alarm count·
ers (the alarm setting) and the time counters (real time).
The comparator output is used to set a latch in the
alarm and sleep circuits. The latch output enables the
alarm output driver (Figure 4b) which is used to
control the external alarm sound generator. The alarm
latch remains set for 59 minutes, during which the alarm
will therefore sound if the. latch output is not tempor'
arily inhibited by another,latch set by the snooze alarm
input or reset by the alarm',"OFF" input.
Snooze Alarm Input: Momentarily connecting snooze
to VSS inhibits the alarm output for betw~en 8 and 9
minutes, after which the alarm will again be sounded.
This input is pulled·up to VOO -by an internal. deple·
tion device. The snooze alarm feature maY'be repeatedly
used during the 59 minutes in which the alarm latch
remains s~t.
Alarm. "OFF" Input: Momentarily connecting alarm
"OFF" to VSS resets the alarm latch and thereby

silences the alarm. This input is also returned to VOO by
an internal depletion device. The momentary alarm
"OFF" input also readies the alarm latch for the next
comparator output, and the alarm will automatically
sound again in 24 hours (or at a new. alarm setting).
If it is desired to silence the alarm for a day or more,
the alarm "OFF" input should remain at VSS.
Sleep Timer and Output: The sleep output can be used
to turn "OFF" a radio after a desired time interval of up
to 59 minutes. The time interval is chosen by selecting
the sleep display mode, (Table I) and setting the desired
time interval (Table II). This automatically results in a
current sink output which can be used to turn "ON" a
radio (or other appliance). When the sleep counter,
which counts downwards, reaches 00 minutes, a latch
is reset and the sleep output current drive is removed,
thereby turning "OFF" the radio. This turn "OFF"
may also be manually controlled (at any time in the
countdown) by a momentary VSS connection to the
Snooze input. The output circuitry is the same as the
other outputs (Figure 4b).

vss

FIGURE 3. 50/60 Hz Input Shaping Circuit

VSS
OUTPUT COMMON BUS

~
~
,,-

-.

ALARM. OR SLEEP
FROM
COMPARATOR

~

>-I. .

OUTPUT
OUTPUT
(OPEN DRAIN)
VOO

FiGURE 4(a). Segment Outputs

FIGURE 4(b). Alarm and Sleep Outputs

5-52

Functional Description

(Continued)

TABLE I. MM5402. MM5405 Display Modes

*SELECTED

DIGIT NO. 2

DIGIT NO.1

01 SPLA Y MODE

DIGIT NO.3

DIGIT NO. 4

Ti me Display

la's of Hours & AM/PM

Hours

10'5 of Minutes

Minutes

Seconds Display

Blanked

Minutes

10'5 of Seconds

Seconds

Alarm Display

10's of Hours & AM/PM

Hours

la's of Minutes

Minutes

Sleep Display

Blanked

Blanked

10'5 of Minutes

Minutes

* If more than one display mode input

is applied, the display priorities are in the order of Sleep (overrides

all others), Alarm, Seconds, Time (no other mode selected).

TABLE II. MM5402. MM5405 Setting Control Functions

SELECTED
DISPLAY MODE

CONTROL
INPUT

CONTROL FUNCTION

*Time

Slow
Fast
Both

Minutes Advance at 2 Hz Rate
Minutes Advance at 60 Hz Rate
Minutes Advance at 60 Hz Rate

Alarm

Slow

Alarm Minutes Advance at 2 Hz Rate
Alarm Minutes Advance at 60 Hz Rate

Fast
Both

Both
Seconds

Sleep

Slow
Fast

Alarm Resets to 12:00 AM (Midnight) (12-Hour Format)
Alarm Resets to 00:00 (24-Hour Format)

Both
Both

Input to Entire TIme Counter IS Inhibited (Hold)
Seconds and 10's of Seconds Reset to Zero Without
a Carry to Minutes
Time Resets to 12:00:00 AM (Midnight) (12-Hour Format)
Time Resets to 00:00:00 (24-Hour Format)

Slow
Fast
Both

Subtracts Count at 2 Hz
Subtracts Count at 60 Hz
Subtracts Count at 60 Hz

*When setting time sleep minutes will decrement at rate of time counter, until the sleep counter
reaches 00 minutes (sleep counter will not recycle).

10HR b 124 HRI

COMMON ANODE

--I

AM-I----4)l.

Vss

1
10 HR
b&c

FIGURE 5(a). Common

FIGURE 5(b). Common

FIGURE 6. 24·Hour Operation:

Anode Application

Cathode Application

10's of Hours Digit Connections

5·53

Digital Clocks

~National

~ Semiconductor
MM5406 Deluxe Display and Clock Radio
General Description
The MM5406 display and clock radio is a monolithic
MOS integrated circuit utilizing N-channellow-threshold.
enhancement mode and ion-implanted depletion mode
devices. The MM5406 circuit interfaces easily with
4 digit LED displays. The MM5406 will also display
alpha-numeric data originating from 16 possible MiniDIP add-on circuits. One of these circuits is the MM5407
digital thermometer circuit for a time/temperature
clock. Data communications will be via one common
I/O bus. Time information is transmitted from this
chip to the peripheral circuits.

Duplexed display
Power failure indication
Brightness control
Presettable 59-minute sleep timer

• Alarm display
• Seconds display
• 9-minute snooze alarm
• Blinking or constant colon
• Alarm tone output
• Stand-bY oscillator for power failure

Features
• Capability for 16 Mini-DIP add-on circuits
• Single line communications data bus
• Priority display system
• Alpha-numeric display
• 50 or 60 Hz operation
• 12 or 24-hour'
• Up/down. fast-slow and hour-minute set control
• Power-ON reset to 12:00:00 (time). 12:00 (alarm).
59 (sleep)
•

•
•
•
•

Applications

Alarm and PM indication

•

Sequential controller

•
•
•

Alarm clock
Desk clock
Indoor-outdoor thermometer and clock

•
•
•
•

Elapsed timer
Industrial and military clock
Humiditydisplay
Portable clock

Block Diagram
50/60 HllN

50/60 Hz SELECT

0>------+1
511{60 Hz

0>----.1

Al

"

C1

D1

SECONDS

E1
F1

G1

A2

"
C2
ALARM OUT

.---+------,

ALARM OFF

o---l---+rA;:;l:;AR;:;M~'~S~l';;';']Pl+ir----i

D2

SNOOZE IN

o--I--+L~c~rR~cu~IT~S--.J

SLEEP OUT

.---+---...1

FAST/HOURS

E2

F2

~""""_"""~

G2

HZ
1 kHz

J2

0--.

SlOWIMINUTES 0--+
TIME SET ALLOW

0--+

f - - - - - - - - - COLON

Vsso-+
Voo 0--+

HF Ext RIC

0>-----+1

10 kHI OUT

.-----~-.L-------------.r--_;;;;;_;!;,--__,

FAST-SlOW/HRS·MINS SELECT Q---tIi>

FIGURE 1

5-54

DATA rIO

2.0 r-r-r-r-r---l--r-,-r--,---,

Absolute Maximum Ratings

1-+-+-i--Ji--J-l-+-l--l---1
1-+-I--i--JH-l-+-l--l---1
1-+-I--i--JH-l-+-l--l---1

1.8

Maximum Voltage at Any Pin
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)

1.6

VSS to VSS + 12V
-25°C to +70°C
-65°C to +150°C
300°C

1.4

~[//~b?,1...

:.:

0:8~~1s(~~
0.6 ~jlW$$»$$$~
0.4
0.2

o

~$A/A/A/$$$M
W'4@,,$$$$$M

20

30

40

50

AMBIENTTEMPERATURE

Electrical Characteristics

MIN

MAX

UNITS

11

V

VOD = 9V
VDD=llV

10
13

mA

Logic "a ..

0.5

V
V

Exclude LED Current

50/60 Hz Input

-D.3 (Note 2)

Logic "1"

2.0

Fast/Hours-Up/Down Input

Logic "0" (Source, 1 mAl

a

Slow/Mins-Up!Down Input

Logic "1" (Sink, 1 mAl

Time Set Allow Input

TYP

9.0

Power Supply Voltage
Power Supply Current

70

(T A within operating range) Functional voltage, VSS = 0, VOO = 9V to 11 V
CONDITIONS

PARAMETER

60

r'c)

VDD-D·5

VDD

mA

0.5

V

VDO

V

0.5

V
V

....

Display Seconds Input
50/60 Hz Select Input
Display Sleep Input
Display Alarm Input

;..

Alarm OFF Input

Logic "a" (Source, 20 MA)

a

Logic "1" (Leakage, laMA)

3.0

VDD

2.0

V

Logic "1" (Source, 10 MA)

VOD-l.0

VDO

V

Logic "a" (Sink, 5 mAl
Logic "1" (Source, laMA)

2.0
VOD-l.0

VDO

V
V

Logic "a" (Sink, 100 MA)
Logic "1" (Source, 100 MA)

1.5

V

VDD-4.0

VDO

V

1.5

V

VDD

V

1.5

mA

30

mA

Snooze Input
12/24-Hour Select Input
Colon Control Input
Fast-Slow/Hr-Min Input .-

Sleep Out

Alarm Out

Data I/O

10kHz Output

Logic "0" (Sink, 5 mAl

Logic "a" (Sink, 3 mAl
Logic "1" (Source, 200 MA)

LED Current Control

Input Current Source

All Outputs For LED Drive
(Note 1)

Output Current at 1.5V

VDD-4.0
a

Note 1: Segment output current must be limited to 30 rnA by the user; power dissipatiqn must be limited to 800 mW at 70°C and 1.2W at 25°C.
Note 2: Applies to voltages directly at pin. See application in F;gure 4 for recommended configuration.

5-55

Functional Description
Dual-In-Line Package

Dual-In-Line Package

VOO

VSS
F2

SLOW/MINS-uP/OOWN

10 kHz

G2

CLOCK

TIME SET AllOW

E2

DATA I/O

DISPLAy SECONDS

02

50/60 Hz

J2

50/60 SElECT

C2

TRANSFER
ENABLE OUT
TRANSFER
ENABLE INPUT

DISPLAY SLEEP

H2

°crF

DISPLAY ALARM

B2

SLEEP OUTPUT
ALARM OUTPUT
ALARM OFF
SNOOZE IN

10
11

14

vss

FAST/HRS-UP/OOWN

TEST

SENSE
TEMP.
RCIN

MM5407
DIGITAL
THERMOMETER

REF OUT
FF OUT
VREF

B

7

A2

MM5406

TEST OUT

VOO

COMMON SOURCE

12

TOP VIEW

COLON

13

A1

12/24 SELECT

F1

COLON CONTROL

E1

20 kHz RIC

01
24

FAST-SLOW/HR-MIN

23

BRIGHTNESS

22

DATA 1/0

21

10 kHz OUTPUT

C1
G1
B1
ALARM/PM LAMP

TOP VIEW

Order Number MM5406N
See Package 24

FIGURE 2
Time Setting Inputs (Pins 2,3 and 17): Both fast·slow
and hours-minutes (up/down) setting inputs are provided.
These inputs are applied either singly or in combination
to obtain the control functions listed in Table II. Fast/
hours (pin 2) and slow/minutes (pin 3) are both 3·level
inputs with internal debounce circuitry. The 3 states
are: VSS. VOO. and open. The fast-slow/hours-minutes
select input (pin 17) is a 2-level input. When pin 17
is connected to VSS. the fast-slow set mode will be
selected. When pin 17 is connected to VOO. the hoursminutes set mode will be selected.

A block diagram of the MM5406 is shown in Figure 1.
The various display modes and their priorities are
listed in Table I. The functions of the setting controls
in combination with the selected display mode are
listed in Table II. Figure 2 is a connection diagram and
one add-on circuit. The following discussions are based
on Figure 1.
50 or 60 Hz Input (Pin 6): A shaping circuit is provided to square the 50 or 60 Hz input. A simple RC
filter. such as shown in Figure 4. should be used to
remove possible Iine voltage transients that could cause
the clock to gain time or cause damage to the clock.
The shaper circuit drives a counter chain which performs the timekeeping function.

When either set input (pin 2 or pin 3) is connected
to VOO. the appropriate counters will count up. When
connected to VSS. the counters will count down.
Note that the control functions are dependent on the
selected display mode. For one example. a time reset
function to 12:00:00 may be made by selecting either
time or seconds display mode and connecting pins
2 and 3 to VOO or VSS (provided the time set allow
input is applied): However. if sleep is the selected
display mode. the sleep counter is displayed. and reset
to 59 minutes.

50 or 60 Hz Select Input (Pin 7): A programmable
prescale counter· divides the input line frequency by
either 50 or 60 to obtain a 1 pps time base. This counter
is programmed to divide by 60 by simply leaving pin
(7) unconnected. A pull-up to VOO is provided by
an internal depletion load. 50 Hz operation. is programmed by connecting pin (7) to VSS.
Alarm. Sleep, and Seconds Display Inputs (Pins 9,
8, and 5): In the absence of any of these inputs (i. e.
pin open) the display drivers present time-of·day information to the appropriate display digits. All 3 inputs
have internal pull-up depletion loads to VOO. Connection of any combination of the 3 inputs to VSS results
in 1·of-5 display modes whose priorities and functions
are listed in Table I. Note that display sleep (pin 8) and
display alarm (pin 9) have equal priorities and when
both pins are connected to VSS. all of the display
drivers are turned on. providing a lamp test mode.

10 kHz Output (Pin 20): The 10 kHz output of the
mother chip (MM5406) provides the data clock for
each of the daughter chips. This clock is used for trans·
mitting and receiving serial data over the data I/O
bus line. All daughter chips will accept data from the
data I/O output (pin 19) during the high state (Vool.
and will output data on the low state (V SS). The
MM5406 will accept data during the low state and will
output data on the high state. See Figure 5 for the
data I/O· timing.

5-56

Functional Description

(Continued)
used, the MM5406 will then send out the next higher
select code. Whenever a daughter chip is enabled. it
will deselect the select code and send 20 bits of data
to the MM5406. This 20·bit data word contains 4
digits of 4 bits each, 2 special bits used for Alpha information, and 2 bits for enabling the PM DOT and
COLON. If the daughter circuit is constantly enabled,
the MM5406 will send the same select code on each
cycle until the daughter circuit is disabled. If the
MM5406 data I/O pin is left open (daughter circuits
disabled or not used), the circuit will then display

Data I/O (Pin 19): The data I/O pin is used for transmitting and receiving serial data via the common data
bus line. During the transmit mode, the MM5406 sends
out 16 bits of real-time data (H 1 0, H 1, M1 0, and M1
from time counter) followed by a select code containing
4 bits for selecting one of the 16 daughter chips.
After the select code is sent out, 4 status bits are sent.
These bits represent the status of the fast and slow
set inputs, the 10Hz internal signal, and the one pUlseper-day signal. If the daughter chip for that select
code is not enabled, or if that daughter chip is not

TABLE I. MM5406 DISPLAY MODES
SELECTED
DISPLAY MODES
(Note 11

DIGIT NO.1

Time Display

DIGIT NO.2

DIGIT NO.4

DIGIT NO.3

Time

Time

Time

Time

10's Hrs,

Hours

10'5 Mins

Mins, Alarm Set

Time

Time

Seconds

Indicator

AM/PM

Seconds Display

Time

Time

10'$ Mins

Mins

10's Sees

Alarm Display

Alarm

Alarm

Alarm

Alarm

10'5 Hrs,

Hours

10's Mins

Mins, Alarm Set

Sleep

Sleep

10'5 Mins

Minutes

Lamp Test

Lamp Test

Indicator

AM/PM
Sleep Display

Blanked

Blanked

Alarm and Sleep

Lamp Test

Lamp Test

Note 1: If more than one display mode input is applied, the display priorities are in the
order of alarm or sleep, seconds,then time. Alarm and sleep have equal priority over seconds;
however, when both alarm and sleep are applied, all outputs are ON, providing a lamp test.
This display mode has priority above all Qthers.

TABLE II. MM5406 CONTROL SETTING FUNCTIONS
SELECTED
DISPLAY MODE

CONTROL
INPUT

Time and Seconds

Time Set Allow and

Display

Slow Set
Time Set Allow and

PIN 17
VSS

VSS

Fast Set
Time Set Allow and

CONTROL FUNCTION

Minutes advance at 2 Hz and seconds
. counter resets to zero.
Minutes advance at 60 Hz and seconds
counter resets to zero.

VOO

Minutes Set

Minutes advance at 2 Hz and seconds
counter resets to zero. Hours counter
in hold mode.

Time Set Allow and

VOO

Hours Set
Time Set Allow and

Don't Care

Slow Set

Hours, minutes, and seconds are reset
to zero {12:00).

Fast and Slow
Alarm Display

Hours' advance at 2 Hz. Minutes and
seconds in normal count mode.

VSS

Alarm minutes counter advances at
2 Hz.

Fast Set

VSS

Alarm minutes counter advances at
60 Hz.

Minutes Set

VDO

Alarm minutes counter advances at
2 Hz. Alarm hours in hold mode.

Hours Set

VOD

Alarm hours counter advances at

Fast and Slow Set

Don't Care

Alarm minutes and hours counters

2 Hz. Alarm minutes in hold mode.
are reset to zero (12:00),
Sleep Display"

Slow

Sleep counter is decremented at a
2 Hz rate.

Fast

Sleep counter is decremented at a

Fast and Slow

Sleep counter is reset to 59 minutes.

10 Hz rate.

Sleep and Alarm

All outputs are driven to provide a lamp test.

Display

*Only when contents of ,sleep, counter are zero and sleep is the selected display mode, sleep
counter is set to 59 minutes.
Note. Alarm and time counters will also count down at the same rates specified above.

5-57

s:
s:
(J1

8

0')

Functional Description (Continued)
. its own time, alarm, and sleep counters. If sleep, se,
conds, or alarm is selected, the MM5406 will disable
the data I/O and display the selected counter. The
MM5406 has an internal pull·up to VOO, therefore,
all daughter chips will have open drain outputs.

Sleep Timer Output (Pin 10): The sleep output at
pin 10 can be used to turn off a radio. after a desired
time interv.al of up to 59 minutes. The time interval
is Chosen by selecting the sleep display mode (Table I)
and setting the desired time interval (Table II). This
automatically results in a current sink output via pin
10, which can be used to turn on a radio (or other
appliance). When the sleep counter, which counts
downward, reaches 00 minutes, .the sleep, latch. is
reset and the sleep output drive is removed, thereby
turning off the radio.

Time Set Allow Input (Pin 4): This .input is used to
enable fast·slow or hours·minutes setting of time when
the selected display mode is time or seconds. An in·
ternal pull·up depletion load is provided on the input.
To set time, one must connect pin 4 to VSS in com·
bination with pin 2 and/or pin 3 (provided time or
seconds is the selected display mode). Note when the
selected display mode is alarm or sleep, the time set
allow input does not inhibit alarm or sleep setting.
Time set allow must be applied before pins 2 and 3,
and must be released after releasing pins 2 and 3.

This turn·o.ff may also be manually controlled by a
momentary connection of the snooze input (pin 13)
to VSS. Also, when the contents of the sleep counter
reach 00 minutes, displaying the contents of the sleep
counter automatically sets the sleep counter to 59
minutes and enables the sleep output, causing a radio
to turn on. If a sleep time other than 59 minutes is
desired, a manual set must be performed, but most users
desire the longest sleep time possible before bedtime.
This feature minimizes pre·bedtime setting operation.
Note that 00 minutes on the sleep ~ounter will never
be displayed, as displaying sleep automatically sets
it to 59 minutes.

12/24·Hour Select Input (Pin 14): This input is used
to select between 12 and 24·hour output display for·
mats. An internal depletion pull·up is provided on the
input. If left open, the 12·f1our format is selected.
If connected to VSS, the 24·hour format is selected.
Colon Control Input (Pin 15): This input is used to
select between a flashing or. non·flashing colon. If
left unconnected, the colon will flash at a 1 Hz rate,
due to an internal depletion pull·up on the input.
Connection to VSS will produce a non·flashing (always
ON) colon.

Standby Oscillator Input (Pin 16): By supplying a
capacitor and resistor from this input to VSS and
VOO respectively, the stand·by oscillator can be used for
timekeeping purposes when the normal 60 Hz line
power fails (Figure 4). A 9 V battery is used to power
the MOS circuit and although the display is blanked,
the correct time is held by the time counters and
counting continues. When line power resumes, the
display returns to normal brightness, displaying the
correct time, without flashing.

Alarm Output and Alarm OFF Input (Pins 11 and 12):
The alarm comparator (Figure 1) senses coincidence be:
tween the alarm counters (the alarm setting) and the
time counters (real time). The comparator output
is used to set a latch inthe alarm circuit, whose output
enables the alarm tone to appear at the alarm output
(pin 11), which easily interfaces to a loudspeaker.
The alarm latch will remain set for 59 minutes, during
which time the alarm will sound, provided the latch
is not temporarily inhibited by another latch which
is set by the snooze input (pin 13) or reset by the
alarm OFF input (pin 12). The alarm tone is gener·
ated by an on·chip oscillator which also ·provides the
timing for the serial data input (pin· 19). The alarm
tone will be at 1 kHz. This square wave is then gated
by a 2 Hz square wave signal before being enabled
at the alarm output. Momentarily connecting pin 12
to VSS resets the alarm latch and thereby silences
the alarm. This input is also returned to VOO by an
internal depletion load. The momentary alarm OFF
input also readies the alarm latch for the next compar·
ator output, and the alarm will automatically sound
again in 24 hours (or at a new alarm setting). If it is
desired to silence the alarm for a day or more, the
alarm OFF input should remain at VSS. An alarm
indicator output (pin 21) is provided to indicate the
status of the alarm OFF input.

The stand·by oscillator is set to 20 kHz nominally
and has 3 functions. One is to supply the 10kHz data
rate for the data communications I/O bus (pin 19).
Another is to generate the 1 kHz tone for the alarm.
The third function is to provide a stand·by clock to
the timekeeping circuits in the event of a power failure.
Brightness Input (Pin 18): The LED output currents
may be varied by the simple connection of this input
to VOO through a variable resistor Rb. This simple
l'pin operation thereby controls the brightness of
the LED display. The output current typically equals
20 times the reference current set through Rb. Internal
resistance is included to limit the maximum current
(Figure 4).

LEO Display Outputs and Common Source (Pins 21·
39): All LEO display oUtputs are open drain devices
with all sources connected directly to common source
pin 30. Each display output has a separate driver which
may sink a maximum of 30 mA directly at 1.5V across
the output device. Fourteen segments Al-Gl and
A2-G2 are used fo· drive the numeric·duplex display.
Segments H2 and J2 are also provided in order to
display alpha·numeric data in the hours·tens and hours·
units position. See Table III for the alpha characters
available.

Snooze Input (Pin 13): Momentarily connecting pin
13 to VSS disables the sleep output (pin 10). If the
alarm has sounded just prior to this, the alarm output
is disabled for 8 to 9 minutes (depending upon the
contents of the real time seconds counter) after which
the alarm will again be sounded. The snooze feature
may be repeatedly used during the 59 minutes in which
the alarm latch remains set.

5·58

I

Functional Description

(Continued)

I

r-------- ---.,

I

BRIGHTNESS
INPUT

COMMON
SOURCE

I

I
I
IL

r-C>D--i

OIDATAI~

LAMP TEST

_______ _

COMMON
SOURCE

FIGURE 3 Brightness Control Circuitry
VDO

50k

BAIGHnJess eornROl
10K

L

1,~oOD

lOOK

50/60 HllN

16

-~O.OO2J.lF

-:J"
19t--DATA I/O
20!--lDkH1OUT

VDO

21

I

.

COMMON·SOURCE

FAST/HOURS UP·DOWN

SLOW/MINUTES UP·OOWN

NCO

3D

......
.....
......

3

FASr.5LOW!UP·OOWN 17

31
32

SlOW·UPI
MINUTES·UP

NCO
SlOW·DOWN!
MINUTES·DOWN

ODk'L'N40D1
'PI-

-if.

J.

UPfODWNO
FAST/SLOW

TIME SET INHIBITO

-

-=

J4

-1... DISPLAY

36

roO..l....-~

37

DISPLAY 5

39

~·-~8

3B

..l.. DISPLAY
-~,
...L

MM5406

~.

"

SNOOZE

~·-~13

,

....

d

.........

·
f

,

·

27

~14

23

....

....

......
....

~

....

.........

,

d

~12!24

~

DIGI~

b

2'
26

UNIT HOURS

J4-

COLON

24

60Hl0

f

•

~

TENS MINUTES

....
~

......

01GIT4.....

0

~

....

,......... ....

COLON

~

15

....

0

DNO

~

-=

12
10

SLEEP
OUT

RADID

VDO

11
ALARM
OUT

ALARM

~

VDO

FIGURE 4 Typical Application for MM5406

5-59

~

.....oiL
.... ....
....

FLASH

....!!!!o

~

....

b

"" ,

~~7

TlrJlESEl ALLOW

~

DlGITI~

FAST·DOWN!
HOURS-OOWN

TENS HOURS

....
.... .....

2

TIME SET 4

BATTERY

,!GtT ,. . .

T ~40

FAST·UP/HOURS-UP

1~i.~ODO...

9V

PM

ALARM/PM

100}JF..J.:

':"

':000

r----

6

DOD05';T

Il ~i
tN4740

~

BRIGHTNESS 18

La
J

UNITS MINUTES

Functional Description

10kHz

50/60

(Continued)

JUU1J1f

JUlJ1f

HZ..J

DATA 110

lal412111 a l412111 a l412111 a l412111 1
PREAMBLE
HID 1 HI
MID
Ml

'I

I

TIME

0

~

~
~

I
TRANSMIT

-RECEIVE11

L

50/60 Hz

DATA 110

L..JillI

1 lal41211 1 1 1 1 1 1
SELECT CODE
,.
~ !iil
;Jl

1 IBl a l412111 a l412111 a l412111 a l41211jA1 1 I
MSO I 2SD I ISO I LSD I
ACTIVE
I • COLON ENABLE
PM DOT ENABLE

I

I

RECEIVE

FIGURE 5. MM5406 Timing

,
TABLE III. MM5406 DISPLAY

HID (MSD)
2

B

8

4

I
I

I
I

I
I

I
I

I

I

I

I

I

I

1

1

1

1
1

1
1

1

0
0
0
0
I
I
I
1
1
1
1
1
0
0
0
0

1
0
0
0
0
1
1
1
I
1
1
I
I
0
0
0
0
I
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0

1
1
1
0
0
0
0
0
0
0
0
0
0
0
0

HI (2SD)
2

I

CHARACTER

A

8

4

I

CHARACTER

I

'-'

1

I

1

1

1

',

0
I
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

=,
'-=,
-'

1

1

1

I

I

1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

,,
,,

L:

';
,-

Cr

-,,
E:
'=1
(Blank)
-*

1

1

1

1

1
1

1
1

1
1

0
0
0
0
1

1
1
0

:=:
,,,-'--

0
0
0
0
0
0
0
0
0
0
0

I-I

,

'-'
,

,'-IT.,
,,-,,
,CI

,
',
T

I.LI

cl

Note. MI and MIa will display 0-9, blank and minus.
The following are examples of the alpha-display:
JA, FE, Mr, AP, MA, JU, JL, AU. SE, OC, NO, dE
SU, MO, TU, WE. TH. Fr. SA
AM, PM. FM, CH (channel no.l. FT (Feet)

I

I
1

1
1
1
1
1
1
1
0
0
0
0

1
0
0
0
0
1
1
1
I
1
1
1
1
0
0
0
0
1
1
1
1

,,
,-=,
=,
-'
'-',
'-'

r;

e
'-'
-,

,
E:
,-,

=,

(Blankl

-*

:=:
,'-

e
'I-I
',

,

'-'

,'-m,
,,Cr
T,
T

.L

,-,

MG (miles per gallon), MH (miles per houri, GA (gallons)
MI (miles)
Mn (minutes), Hr (hours), SC (seconds)

*Minus

5-60

~National

Digital Clocks

~ Semiconductor
MM5407 Digital Thermometer
General Description
The MM5407 Digital Thermometer is a monolithic MOS
integrated circuit utilizing N·channel metal gate low
threshold, enhancement mode and ion·implanted deple·
tion mode devices. The MM5407 interfaces directly
with the temperature transducer LM 134 and MM5406
digital clock. LM134 senses the temperature and outputs
voltage proportional to temperature in degrees Kelvin at
10 mVfK. MM5407 senses this analog voltage and converts it into BCD Centrigrade or Fahrenheit data.
MM5407 transfers temperature data serially to the
MM5406 clock which in turn converts this BCD data
into 7·segment display code. MM5406 interfaces directly
with LED display. MM5407 has capability of generating
serial data either for Centigrade or Fahrenheit temperatures. The temperature ranges are from -40°C to +SSoC
and -40° F to +194° F. MM5407 operates over the supply
range of 9-11V and is packaged in 14·pin plastic package.
Serial data output can also be generated by bringing

the transfer enable input low. In this mode the MM5407
can easily interface to a microprocessor.

Features
•
•
•
•
•
•

Centigrade or Fahrenheit data
Direct interface to MM5406 clock chip
Simple interface to LM 134 temperature transducer
Simple interface to microprocessor
Serial data output
Convenient 14·lead DIP package

Applications
• Indoor and outdoor digital thermometer
• Temperature sensor for microprocessor or minicomputer
• Digital thermostat

Block and Connection Diagrams
ENA~~~~~~~~ - - - - - - - - - - - . ,

r-"'------'-.,

10kHz

---------+1

TRANSFER
Et'ABLE
OUTPUT
INPUT/
OUTPUT

-+-~~~~UT

°CrF SELECT - - - - - - - - - - - .
F·F OUTPUT - - - - - - - . ,

--+-~~~JT

VOLTARGE:~~~~~~ - - - - - - . ,
RC INPUT
TEMPERATURE
SENSOR INPUT

-VSS
RE~~~i~~~

_ _ _ _ _ _...1
-VOD

FIGURE 1
Dual·ln-Line Package
14
VSS

INPUT/OUTPUT
TRANSFER
ENABLE OUTPUT
TRANSFER
ENABLE INPUT

TEST OUTPUT

13 TEMPERATURE
SENSOR INPUT
12
RC INPUT

10 kHz CLOCK

11

4

REF OUTPUT

10 FLlp.FLOP
OUTPUT
REFERENCE
VOLTAGE

°C OR OF SELECT
TESHNPUT

VOO

TOPVIEW

Order Number MM5407N
See Package 18

5-61

Absolute Maximum Ratings
Maximum Voltage at Any Pin
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)

Electrical Characteristics
PARAMETER

VSS to VSS + 12V
-25°C to +70°C
-65°C to +150°C
300°C

(TA within operating range) Functional Voltage, VSS = 0, VDD = 9 to llV
CONDITIONS

Power Supply Voltage

MIN

TYP

9

MAX

,UNITS

11

V

15
18

mA
mA

Power Supply Current

VDD = 9V
VDD=llV

Temperature Sensor Input Voltage

10mVfC'

2.33

3.61

V

RC Input, Input,Voltage

10 mVfC

2.33

3:61

V

VREF Input, Input Voltage

3.627

VREF Input Resistance to VSS

1.2

3.63

3.5

Temperature Display Resolution

Temperature Accuracy (AT)

-40

88

-40

194
±2

VDD=9tollV

kn
°c or of

1

Temperature Display Range

V

3.633

°c
of
of

Over the Range of -40°F to 194°F
10kHz, Clock Input

Input Output I/O as Input

Input Output I/O as Output

Log'ic "0"

VSS+0.6

V

VDD

V

VSS
VDD-2

VSS+0.3
VDD

V
V

VSS

VSS+O.4

V

VDD

V

VSS
VSS+2.4
1/2

VSS+0.6

V
V

VSS

VSS+O.4

V

VDD

V

Logic "1"

VSS
VSS+2.4

Logic "0"
Logic ".1"
Logic "0",
(ISINK = 2 mAl
Logic "1",

.'

(I LEAKAGE = 10/lA)

Transfer Enable Input

Transfer Enable Output

Logic "0"
Logic "1"
Pulsewidth
Logic "0",
(ISINK.= 2 mAl
Logic ",1",

VDD
18

10 kHz clks

(lSOURCE = 10 /lAl

Functional Description
A block diagram of the MM5407,is shown in Figure 1.
Individual pin function is described in the following
description. Figure 2A shows the typical application of
digital thermometer and clock using MM5407, MM5406
and temperature transducer LM134. Figure 3A shows
an application of the MM5407 as temperature sensor
"
for a microprocessor.

The MM5407 utilizes an analog·to·digital converter
circuit which senses analog voltage and converts 'it into
BCD digital. data. The analog·to-digital converter uses a
positive and negative reference voltage and a comparator
to determine the value of an analog input voltage. A
positive reference voltage is applied to an RC input
a'nd this voltage is compared with the tempera-

5-62

Functional Description

(Continued)

_I

510

1 I l--:t

1M

0"1' pF

FLIP-FLOP
OUTPUT.......

r--

LM141
VOLTAGE
REGULATOR

-

~"".;"' ~ ,~:-:"'

I = - L = ~;.
r

' "TlMEO+-O-0--0 ,

VOLTAGE
REFERENCE

15k

.

IC

1000PF

VDD

VSS
110

l .**
10k\I'
\

.~",:,

-: - t +

Rb ~
-;.

lOOk

11

....,..

-

tN400t

§j IL

tOOk

6o Hz

...... ,
.,..

-

r-

-:~tOO
... ,'1'pF

.,..

~
VOD

o-r-g
r-

~

I....o~.

r-oO
~

FAST/HR UP
SLOW/MIN UP

I

I
I
I
II

A~
"--

SlOW/MIN DOWN
FAST/HR DOWN

50k

--

9V-::-

~

VSS

~£
~£

:~

I
I

0-

I

I

DISPLAY SECONDS

H2(OPTIONALI

-*-....
':

DISPLAY SLEEP
ALARM OUT

SLOW/MIN SET

-L
0-

SNOOZE IN

~

2~

~~

:;;~

SLEEP OUT

~ ~ ~
~

~

,,~

~

m
....

-<~,

,.

~

~

~

VDO~

PM • ..:

:

~
':.....

} HtOIO EGREES UNIT

} HIf'F OR"C

LEO DISPLAY *
(DUPLEX)

RS

~

TO RADIO

~RADIOItOV)

..
~

0

z

~ ~
:;

1:1 1:1-1:1 1:1 • V:itERC~
FIGURE 2A. Typical Application of MM5407 Temperature IC and MM5406 Clock IC

5-63

} HtO.M 10/
OEGR EES 10's

.:

-6-

~

}""'

MINUS•.
BLANK OR ONE

ALARM':

12 (OPTIONAL)

DISPLAY ALARM

FAST/HR SET

I-I -I-I I-I

.:

'~

I

COMMON SOURCE

....
"',.
I~ ~
~V:!

~I-I

"OUTDOORTE MP
SELECT

t .....

ALARM/PM

-L

~.

AM/PM/'

I

I

MM5406

.~

.

tOOOpF

*INDOORTEMP
SELECT

COLON I

f

~

2

I
I
I
I

0.002pF

~

3

Dt

STAND·BY OSC
~ (20kHz)

i_I...

[ } - ,~.""'"

ct

CELL

VOO

to

LM134
TEMP

BI

==0.0005pF
IN40~

~

AI

10 kHz

~-:;~~~~ -i

50160 Hz
INPUT

1

_

10kHz

BRIGHT· DATA
I/O
NESS

2

':' *r

TEMP
SENSE
INPUT

..J""""

3

230

MM5401

.....

~

Functional Description

(Continued)

:E
:E

1 . . . _----'
PREAMBLE

SELECT
CODE

II * I I I U 1111111111111111 L
I
I
I
I
1~1 I~ Iii fI~ I
C
OR

F

* 1 pulse per day

v

-.1 OR

BLANK

TEN'S

UNITS

A

E

TRANSMIT

RECEIVE

Select code for MM5407 is "1111"
1 0 Hz is used for generating internal time clock

FIGURE 28. MM5407 Input/OutputTiming Diagram for MM5406 Configuration
ture sensor input voltage. When the RC input voltage is
greater than the temperature sensor voltage. the reference voltage polarity is reversed and the RC input'
discharges toward the negative reference Voltage. The RC
input voltage is then compared again with the temperature sensor voltage. When it is less than the temperature
sensor voltage the circuit again switches. applying the
positive reference voltage to the RC input. The circuit
eventually settles down to a duty cycle which when
measured by digital counters gives the absolute value
of the input voltage. Data from the digital counter is
stored in latches. The selection of °c or ° F transfers the
data serially on the 1/0 bus to MM5406. The MM5406
converts this data into 7-segment data and displays it on
a duplex driven LED display.
Temperature Sensor Input (Pin 13): This input senses
analog voltage generated by a temperature transducer
(e.g., LM 134). This input is one of the 2 comparator
inputs. The input senses voltage between the range
2.33V (~40°C) to 3.6111 (88°C). The input has
10m Vt C resolution.
RC Input and Flip-Flop Output (Pins 12,10): RC input
is the second input to the analog comparator. A 1 MQ
resistor is connected between pin 12 and 10 and a
0.01 pF capacitor is connected between pin 10 and
VSS, pin 1. Voltage at the RC input (pin 12) is
dependent on flip-flop output which in turn depends
on the analog input at pin 13. The external RC does
not require tight tolerances.

next, higher select code. Whenever a daughter chip such
as the MM5407 is enabled, it will deselect the select
code and send 20 bits of data to the MM5406. This 20·
bit data word contains 4 digits of 4 bits each, 2 special
bits used for Alpha information, and 2 bits for enabling
the PM DOT and COLON. If the MM5407is constantly
enabled,the MM5406, will send the same select code on
each cycle until the MM5407 is disabled. All data on
the data 1/0 pin will be active low (VSS). The MM5406
has an internal pull-up to VDD, therefore the MM5407
is designed to have an open drain output.,
°c or OF Select, (Pin 6): This input is a TRI-STATE®
input. If this pin is connected to VDD or VSS, the I/O,
pin 3, will transfer the serial temperature data through
an LED display. Connecting this pin to VDO selects OF
and connecting it to ground (VSS) selects °C. In floating
mode, the I/O pin will stop sending the data to MM5406,
which in turn will take over the display select mode and
display its own information.
10 kHz Clock: External clock of 10 kHz is used for
transmitting and receiving serial data over the data I/O '
bus line. The MM5406 prpvides 10 kHz clock for
MM5407. MM5407 will accept data from data I/O (pin
3) during (VSS). The transmit and receive timing is
shown in Figure 28.
Transfer Enable Input (Pin 5) and Transfer Enable
Output (Pin 4): MM5407 can be used with a microprocessor for sensing temperature. Transfer enable
input pin 5 strobes the °c or ° F input selection at pin 6
and enables output pin 4. Output enable signal can be
used to strobe serial data into shift register. After output
enable is oh, I/O pin trahsmits serial data to the external
shift register. The 18-bit serial data contains 4 digits
of temperature information. Pins 4 and 5 have internal
pull-up to VOO capable of sinking a maximum of 10 pA.
Use external resistor for higher current capability.

Reference Voltage (Pin 9): This input requires precision
re,ference voltage of 3.630 ±0.003V. On-chip voltage
divider produces second reference. The accuracy of these
2 references will determine the accuracy of displayed
temperature. The on-chip voltage divider can draw current up to 3 mAo
Input/Output (Pin 3): The data' 1/0 pin is used for
transmitting and receiving serial data via the common
data bus line. During the transmit mode, the MM5406
sends out 16 bits of real-tim'e data followed by a select
code containing 4 bits for selecting one of the 16
"daughter" chips such as MM5407. After the select code
is sent out, 4 status bits are sent. If. the daughter chip
for that select code is not enabled, or if that daughter
chip is not used, the MM5406 will then send out the

Test Input: This pin and the Test output are not uS,ed
during normal operation of the device., When the Test input is brought to VSS the on·chip oscillator is connected
to Test output, so its frequency range can be easily
measured. In addition the temperature counters are
accessed to fascilitate testing. There is an internal pull·up
to the Test input so during normal operation it should
be left open.
5-64

Functional Description

(Continued I
Voo

0.D1 "F

L

I l

FLlP·FLOP
OUTPUT ......... 10

12

LM741
VOLTAGE
REGULATOR

-=

LM329CH

~RCINPUT

Voo--o f

6.9V

RE~~~~~~~ t---..........c~
1000PF

T

VOO
LM134
TEMP
TRANSDUCER

TEMP 13
SENSE ~"'-D"'~
INPUT
MM5407

Vss

* INDOOR TEMP
SELECT
**OUTOOOR TEMP
SELECT

20k

1-...- - - - TRANSFER ENABLE OUTPUT

10 kHz INPUT

20k

..........,""..-0 V DD 110
TRANSFER ENABLE INPUT
FROM MICROPROCESSOR

5

.........- - - - lB BITS OF SERIAL DATA

FIGURE 3A. Typical Application of MM5407 Used as a
Temperature Sensor for Microprocessor

10 kHz
10
START

11

12

13

g

15

16

17

18

--'-'
L..l-J.-----------------------__________________________ I

OUTPUT
ENABLE _ _ _--'

L
1

OATA OUT

I

4

I

8

I4 I

1
BLANK
MINUS

OATA TRUE

TEN'S

DATA OUT

8

4

2

0

1

1

1

1

1

1

1

1

0

2
3

1

1

a

1

1

1

0

0

4

1

a

1

1

5

1

0

1

a

6

1

0

0

1

7

1

a

0

a

8
9

a
a

1

1

1

1

1

c

1

1

1

a
a

F

1

1

a

1

1-1

0

1

0

a

0

1

a

1

- Blank

1

FIGURE 3B, Timing for the Above Application

5·65

UNIT'S

~National

Digital Clocks

~ Semiconductor
MM5455 Digital Alarm Clock
General Description
The MM5455 digital alarm clock radio chip is a monolithic MOS integrated circuit utilizing N-channel, low
threshold, enhancement mode and ion-implanted depletion mode devices.

The MM5455 is bonded in a 24'pin package and is
capable of 24-hour/50 Hz, 12-hour/60 Hz and 12·hour/
50 Hz operations.

The MM5455 contains all the logic necessary for a
digital clock with sleep and alarm control and is in·
tended for clock·radio applications.

• Duplex LED display drive
• Fast/slow set capability
• 24·hour alarm
• "Snooze" function (9 minutes)
• On-chip alarm oscillator
• Alarm tone output gated at a 2 Hz rate
• Power fail indication-entire display flashes at a
1 Hz rate
• Automatic power-on reset
• PM display indicator
• Presettable 59 minute sleep timer

Features

Real time and alarm time are displayed in hours-minutes
and sleep time is displayed in minutes when setting
the sleep counter.
An alarm output is provided that "beeps" a 700 Hz
tone gated by 2 Hz rate when the alarm set time and
the real time matches. A sleep output that provides
a DC level is used to control the radio. It is activated
with the alarm output or programmed via the sleep
counter to turn OFF from 0 to 59 minutes after the
sleep counter is set.

Applications
• Alarm clocks
• Desk clocks
• Clock radios
• Automobile clocks
• Stopwatches
• Industrial clocks
• Portable clocks

A snooze feature is provided for a 9-minute recurrence
of the alarm after it has sounded. Setting is done" via
the standard fast and slow set buttons when in the
time set, alarm set or sleep set modes. These control
inputs areTR I-STATE®inputs to reduce pin count.
The 50/60 Hz clock selects what segment data is on
the outputs, i.e. a duplex LED display interface.

•

Timers

Block Diagram
50160 Hz 0-....- - - - - - - - - - - - - - - . . . . . ,

DISPLAY MUX
AND DECODE

SEGMENT OUTPUTS 1131

+-<> VOD
+-<> VSS
RC

ALARM OFFI
ALARM ONI
SLEEP SET

5·66

SLEEP
.OUT

ALARM
TONE OUT

Absolute Maximum Ratings

(Exceeding the following ratings may result in permanent damage to the device)

Voltage at Any Pin
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)

VSS to VSS +12V
-25°C to +70°C
--£5 C to +150°C
300°C

~

CJ'I
CJ'I

Q

Electrical Characteristics

Power supply voltage should not exceed a maximum of 12V under any circumstances.

T A within operating range, VDD = 7V to 11 V
PARAMETER
Power Supply Voltage

CONDITIONS

MIN

Output Driving Display

TYP

9

Functional - Count Operating
Power Supply Current

MAX

UNITS

11

V

11

V

No Output Loads
VDD

= 7V

VDD=11V
50/60 Hz I nput Frequency

4

mA

5

mA

DC

50/60

10k

Logical "0", Low Level

VSS

VSS

VSS+0.5

V

Logical "1", High Level

0.7 VDD

VDD

VDD

V

Input Leakage

10

VIN = VDD or VSS

Hz

J.1A

All Other Input Voltages
Logical "0", Low Level

VSS

VSS

VSS+0.5

V

Logical "1", High Level

VDD-1

VDD

VDD

V

5

V

Power Failure Detect Voltage

(VDD Voltage)

Alarm Output, Sleep Output

VDD=11V

= VDD -1V

Sourcing, Logical "1" High

VOH

Sinking, Logical "0" Low

VOL = VSS + 6V

5

Alarm Output Frequency

Fixed Rand C

560

Segment Outputs (Except

VDD

J.1A
mA
700

840

Hz

= 10V

HTADEG)
Output Sink, Logical "0" Low

VOL = VSS + 2V

Leakage, Logical "1" High

VOH

= VDD

VDD

= 10V

Segment Output (HTADEG)
Output Sink, Logical "0" Low

VOL=VSS+2V

Leakage, Logical "1" High

VOH

20

mA

10

J.1A

mA

40

= VDD

10

J.1A

Functional Description
50 or 60 Hz Input:A shaping circuit is provided internally to square the 50 or 60 Hz input. This circuit
allows use of a half sinewave input. A resistor in series
must be used to limit current into the MOS device.

the snooze can be activated by momentarily connecting fast set pin to VDD. This will turn off the
alarm for. 9-10 minutes, after which the alarm will
again be sounded. The snooze alarm feature may be
repeatedly used for up to 59 minutes or until alarm
OFF is activated by momentarily connecting this pin
to VDD. When alarm OFF is activated, the alarm latch
will reset and silence the alarm. The alarm will automatically sound again in 24 hours (or at a new alarm
setting). If it is desired to silence the alarm for a day
or more, the alarm OFF input should remain at VDD.
The alarm can be enabled again by allowing the input
to float.

24-Hour/50 Hz, 12-Hour/60 Hz, 12-Hour/50 Hz: This
input is a tri-Ievel input. When connected to VSS, the
display will be 24 hours with 50 Hz input. If connected
to VDD, the display will be 12 hours with 50 Hz input.
If left floating, the display will be 12 hours with 60 Hz
input.
Sleep Set/Alarm Enable/Alarm OFF: Whenever this
input is connected to VSS, the sleep counters will
display and be set to 59 minutes, if previously at 00
minutes. Fast set or slow set may be used to preset
time other than 59 minutes. When the alarm sounds,

External RC: The resistor and capacitor on this pin
set the frequency of the alarm tone. The frequency is
nominally set to 1400 Hz in order to produce a 700 Hz
(50% duty cycle) tone at the alarm output.

5-67

s:
s:
CJ'I

Functional Description

(Continued)

Time Set/Run/Alarm Set: This input must be activated
in order to set the time counter and alarm counter. When
connected to VOO, the time counter will be displayed
and may be set with the fast·slow input. Upon release
of fast and slow set, the time counter will be in a hold
mode. If time set/alarm set is left floating, the time
counter will be displayed, and the fast·slow input will
be disabled (normal run mode). When this input is con·
nected to VSS, the alarm counter will be displayed
and may be set with the fast·slow input.

OFF for 250 ms). This output contains an internal
pull-up to VOO in order to turn OFF the external
PNP transistor driver when the alarm is inactive.

Sleep Output: This output remains at VOO when
inactive. When the alarm latch becomes set or the sleep
counter is at other tlian 00 minutes, the sleep output
will be ON. Snooze or alarm OFF function will dis·
able this output simultaneously with alarm output
if activated by alarm latch. Snooze function will disable
this output at any time if activated by sleep counter
being set. This output contains an internal pull·up
to VOO in order to turn OFF the external PNP trans·
istor switch when the output is inactive.

Fast Set/Run/Slow Set: Whenever this input is con·
nected to VOO and time set or alarm set is activated,
the appropriate counter will advance at a 60 Hz rate.
If connected to Vss,the minutes counter will advance
at 2 Hz with carry into the hours counter. If left floating,
the clock will keep normal time. When connected to
VOO and sleep set is activated, the sleep counter will
count downward at a 10 Hz rate. If connected to VSS,
the sleep counter will count downward at the slower
rate; 2 Hz.

Segment Outputs: All segment outputs are open·drain
devices with all sources common to VSS.

Power ON and Power Failure: After power ON or
power fail, the display will flash at 1 Hz rate and time,
alarm, and seconds counters will be reset to 0:00:00

Alarm Output: This output remains at VOO when inac·
tive. When the alarm latch becomes set, the alarm
700 Hz tone will be gated by a 50% duty cycle 2 Hz
signal (i.e., the alarm tone will be ON for 250 ms and

(12:00:00). The alarm output will be held OFF also.

The power fail can be reset by enabling time set allow.

Typical Application
DUPLEX DlSPLAV

"

zw

ACINPU']
"

zw

SO/6D Hl
19 INPUT

SLEEP
DRIVE

Vss
. -_ _...._.., EXTne

MM5455

ALARM
DRIVE

. - - -..........,,.-i

VDD

12/50

12/600

1k

T
+

1k

tOOJ.lF
25VDC

5-68

Connection Diagram

Dual·ln·Line Package
12 or 24·Hour/50 or 60 Hz Clock
HTAOEG

HTB, PM
23

HUB, HUG

22

HUC, HUO

21

HUA, HUF

20

VSS

19

MTF, MTA
MM5455
MTG,MTB

16

MTE,MUE
MUB,MUG
MUC,MUO
MUA,MUF

10

15

11

14

12

13

TOP VIEW

Order Number MM5455N
See Package 22

5·69

NC
SLEEP OUT
24/50,12/60,12/50
50/60 Hz INPUT

18 ALARM OFF/ALARM ON/
SLEEP SET
17

MTD, MTC

HTC, HUE

EXT, RC
VOO
TIME SET/RUN/ALARM SET
FAST SET (SNOOZEI/RUN/SLOW SET
ALARM TONE OUT

Digital Clocks

~National

~ Semiconductor
MM5456, MM5457 Digital Alarm Clocks
General Description
The MM5456, MM5457 are bonded in a 22-pin package_
The MM5457 has a 24-hour/50 Hz option and the
MM5456 has the 12-hour/50 Hz or 12-hour/60 Hz
options.

The MM5456, MM5457 digital alarm clock radio chips
are monolithic MaS integrated circuits utilizing N-channel, low threshold, enhancement mode and ion-implanted depletion mode devices_
Each circuit contains all the logic necessary for a digital
clock with sleep and alarm control and is intended for
clock-radio applications_

Features
• Duplex LED display drive
• Fast/slow set capability
• 24-hour alarm
• "Snooze" function (9 minutesl
• On-chip alarm oscillator
• Alarm tone output gated at a 2 Hz rate
• Power fail indication-entire display flashes at a
1 Hz rate
• Automatic power-on reset
• PM display ind'icator
• Presettable 59 minute sleep timer

Real time and alarm time are displayed in hours-minutes
and sleep time is displayed in minutes when setting
the sleep counter_
An alarm output is provided that "beeps" a 50% duty
cycle, 700 Hz signal gated' at 2 Hz rate, when the alarm
set time and the real time matches_ A sleep output
that provides a DC level is used to control the radio_
It is activated with the alarm output or programmed
via the sleep counter to turn OFF from 0 to 59 minutes
after the sleep counter is set_

Applications

A snooze feature is provided for a 9-minute recurrence
of the alarm after it has: sounded.

•
•
•
•
•
•
•
•

Setting is done via the standard fa'st and slow set buttons
when in the time set, alarm set or sleep set modes.
These control inputs are TRI-STATE® inputs to reduce
pin count_
The 50/60 Hz clock selects what segment data is on
the outputs, i.e., a duplex LED display interface_

Block Diagram

Alarm clocks
Desk clocks
Clock radios
Automobile clocks
Stopwatches
Industrial clocks
Portable clocks
Timers

50/60H'o-......- - - - - - - - - - - - - ,

OISPLAVMUX
AND DECODE

SEGMENT OUTPUTS
MM5456: 12 OUTPUTS
MM5457: 13 OUTPUTS

+-OVSS

RC

ALARM OFFI
ALARM ONI
SLEEP SET

SLEEP
OUT

ALARM
TONE OUT

Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)

Electrical Characteristics

(Exceeding the following ratings may result in permanent damage to the device)
VSS to VSS +12V
-25°C to +70°C
-65°C to +150°C
300°C

..~

0)

Power supply voltage should not exceed a maximum of 12V under any circumstances.

PARAMETER

CONOITIONS
Output Oriving Oisplay

MIN

Functional - Count Operating
Power Supply Current

TYP

9
7

MAX
11

UNITS
V

11

V

No Output Loads
4
5

VOO = 7V
VOO=llV
50/60 Hz Input Frequency
Logical :'0", Low Level
Logical "1", High Levei
Input Leakage

mA
mA

OC

50/60

10k

Hz

VSS
0.7 VOO

VSS
VOO

VSS+0.5

V
V

VIN = VOO or VSS

VOO
10

/-LA

VSS+0.5
VOO

V
V

All Other Input Voltages
Logical "0", Low Level
Logical "1", High Level

VSS
VOO-1

Power Failure Oetect Voltage

(VOO Voltage)

Alarm Output, Sleep Output
Sourcing, Logical "1" High

VOO = 11V

Sinking, Logical "0" Low

1

VOL=VSS+ 6V

5

Alarm Output Frequency

R = 6Sk, C=O.l/-LF
VOO = 10V

Output Sink, Logical "0" Low
Leakage, Logical "1" High

VSS
VOO

1

VOH = VOO -lV

Segment Outputs (Except
HTAOEG)

V

5

/-LA
mA
Hz

700

20

VOL = VSS + 2V

mA
10

VOH = VOO

,

,

/-LA

.

Segment Output (HTAOEG)
Output Sink, Logical "0" Low
Leakage, Logical "1" High

s::
s::
en
~

T A within operating range, VOO = 7V to 11 V

Power Supply Voltage

s::
s::
en

VOO = 10V
rnA

40

VOL = VSS + 2V

10

VOH = VOO

/-LA

Functional Description
time other than 59 minutes. When the alarm sounds,
the snooze can be activated by momentarily connecting fast set pin to Voo. This will turn off the
alarm for 9-10 minutes, after which the alarm will
again be sounded. The snooze alarm feature may be
repeatedly used for up to 59 minutes or until alarm
OFF is activated by momentarily connecting this pin
to VOO. When alarm OFF is activated, the alarm latch
will reset and silence the alarm. The alarm will auto·
matically sound again in 24 hours (or at a new alarm
setting). If it is desired to silence the alarm for a day
or more, the alarm OFF input.s~ould remain at VOO.
The alarm can be enabled again by allowing the input
to float.

50 or 60 Hz Input:A shaping circuit is provided internally to square the' 50 or 60 Hz input. This circuit
allows use of a half sinewave input. A resistor in series
must be used to limit current into the MOS device.
24-Hour/50 Hz, 12-Hour/60 Hz, 12-Hour/50 Hz
(MM5456): When this input is connected to VOO, the
display will be 12 hours with 50 Hz input. If left floating,
the display will be 12 hours with 60 Hz input. (The
MM5457 is internally bonded to select the 24·hour/50
Hz mode. The MM5456 selects the 12·hour/50 Hz or the
12·hour/60 Hz modes.)
Sleep Set/Alarm Enable/Alarm OFF: Whenever this
input is connected to VSS, the sleep counters will
display and be set to 59 minutes, if previously at 00
minutes. Fast set or slow set may be used to preset

External RC: The resistor and capacitor on this pin
set the frequency of the alarm tone. The frequency is

5-71

en
.......

Functional Description

(Continued)

nominally set to 1400 Hz in order to produce a 700 Hz
(50% duty cycle) tone at the alarm output.
'

700 Hz tone will be gated by a 20% duty cycle 2 Hz
signal (i.e., the alarm tone will be ON for 100,ms,and
OFF for 400 ms). This output contains ,an internal
pull·up to VOO in order to turn OFF 'the external
PNP transistor driver when the alarm is inactive.

Time Set/Run/Alarm Set: This input must be activated
in order to set the time counter and alarm counter. When
connected toVOO, the time counter will be displayed
and may be set with the fast·slow input. Upon release
of fast and slow set, the time counter will be in a hold
mode. If time set/alarm set is left floating, the time
counter will be displayed, and the fast·slow input will
be disabled (normal run mode). When this input is con·
nected to VSS, the alarm counter will be displayed
and may be set with the fast·slow input.

Sleep Output: This output remains at VOD when
inactive. When the alarm latch becomes set or the sleep
counter is at other than 00 minutes, the sleep output
will be ON. Snooze or alarm OFF function will dis·
able this output simultaneously with alarm output
if activated by alarm latch. Snooze function will disable
this output at any time if activated by sleep counter
being set. This output contains an internal pull·up
to VOO in order to turn OFF the external PNP trans·
istor switch when the output is inactive.

Fast Set/Run/Slow Set: Whenever this input is con·
nected to VOO and time set or alarm set is activated,
the appropriate counter will advance at a 60 Hz rate.
If connected to Vss,the minutes counter will advance
at 2 Hz with carry into the hours counter. If left floating,
the clock will keep normal time. When connected to
VOO and sleep set is activated, the sleep counter will
count downward at a 10 Hz rate. If connected to VSS,
the sleep counter will count downward at the slower
rate; 2 Hz.

Segment Outputs: All segment outputs are open-drain
devices with all sources common to VSS.
Power ON and Power Failure: After power ON or
power fail, the display will flash at 1 Hz rate and time,
alarm, and seconds counters will be reset to 0:00:00
(12:00:00). The alarm output will be held OFF also.
The power fail can be reset by enabling time set allow.

Alarm Output: This output'remains at VOO when inac·
tive. When the: alarm latch becomes set, the alarm

Typical Application
OUPLEX DISPLAY

56
1W

56
1W

50/60 Hz
18

INPUT

SLEEP OUT

10

Vss

.---+....",-j EXT Rt

SLEEP
DRIVE

4.7k

MM5456

ALARM
TONE OUT

4.7k

DRIVE

11

. - - -....--1 Voo

4.711

Voo

1k

+

T

1DO,uF
15VOC

5·72

Connection Diagrams

(Dual-In-Line Packages, Top Views)

12·Hour/50 or 60 Hz Clock

HUB, HUG

22

HTB, PM

HUC, HUD

21

HTC, HUE

HUA, HUF

20

SLEEP OUT
12160,12150

VSS
MTF, MTA

50/60 Hz INPUT
ALARM OFF/ALARM ON/
SLEEP SET
EXT. RC

MM5456

MTB, MTG
MTD, MTC
MTE, MUE

VOD

MUB, MUG

14

TIME SET /RUN/ALARM SET

MUC, MUD

10

13

FAST SET (SNOOZEI/RUN/SLOW SET

MUA, MUF

11

12

ALARM TONE OUT

Order Number MM5456N
See Package 22

24·Hour/50 Hz Clock

HUB, HUG

HTB, PM

HUC, HUD

HTAOEG

HUA, HUF

HTC, HUE
SLEEP OUT

VSS
MTF, MTA

18
MM5457

MTB, MTG
MTD, MTC

17

16

50 Hz INPUT
ALARM OFF/ALARM ON/
SLEEP SET
EXT. RC

MTE, MUE

15

VDD

MUB, MUG

14

TIME SET/RUN/ALARM SET

MUC, MUD

10

13

FAST SET (SNOOZEI/RUN/SLOW SET

MUA, MUF

11

12

ALARM TONE OUT

Order Number MM5457N
See Package 22

5-73

~

a

National
Semiconductor

Digital Clocks

MM58143, MM58144, MM58183, MM58184
LCD Alarm Clock Circuits
.
General Description
The MM58143, MM58144 and their mirror versions
MM58183, MM58184 are low threshold voltage, ion
implanted, metal-gate CMOS integrated circuits that
provide all the functions necessary to implement several
liquid crystal alarm clocks_ Both circuits use a 32;768 Hz
quartz oscillator as the time base. Necessary. RC components for the oscillator are included on-chip to
minimize system components cost. 28 phase-controlled
32 Hz outputs are available to direct drive a 4-digit
display with PM, alarm, and sleep flags.' The circuits
include a 24-hour alarm function, a 59-minute sleep
timer, and a 7-minute snooze timer. Hours-minutes in
either 12 or 24-hour format are normally displayed.
Alternate display modes include seconds, alarm and
sleep time. The alarm output is a pulsating tone with a
maximum duration of one minute to minimize power
consumption_

external capacitors and can provide greater than-2.0V
drive at 1 pA load in order to drive 0_5" displays.
The MM58143, MM58144, MM58183 and MM58184
are available in standard 40-lead epoxy package_ In
addition, .the basic 49 pad MM58143 die is available
unpackaged suitabl.efor PCB module assembly systems_

Features
II
II
II
II

Two packaged versions are available for clock-radio and
travel alarm applications. The MM58143 or MM58183
clock-radio circuit allows multiple battery supplies of
1.5V for timing and logic controls and -1.5V or -3.0V
for display drive. The MM58144 or MM58184 travel
alarm circuit eliminates the sleep timer functions, but
includes an on-chip voltage multiplier for single 1.5V
battery operation. The voltage multiplier requires 3

II
II
II
II
II
II
II

Direct drive of 0.3" to 1_0" LCD displays
4-digit plus PM, sleep, and alarm flags
Selectable 12 or 24-hour time display
24-hou r al arm
Presettable 59-minute sleep timer
7-minute snooze timer
Selectable flashing or non-flashing colon (die only)
Fast and slow set controls
Low power dissipation
On-chip oscillator RC components
Efficient on-chip voltage mUltiplier

Block Diagram
osc

OUT

TRIPLE

osc

DOUBLE

IN

CAPt
CAP2

'-----+----- OP/32Hz:

SLOW

FI\ST
SLEEP
12/24 HR
28 SEGMENT
OUTPUTS

COLON SelECT
ALARM TONE
ALARM ENABLE

ALARM OUT

1-_ _ _ _ _ _ SLEEP OUT

FIGURE ,_ Block Diagram of MM58143, MM58144. MM58183. MM58184
5-74

Absolute Maximum Ratings
Voltage at Oouble,
Osc. Out, and All Inputs
Voltage at Triple Output
Voltage at All Other Outputs
Operating Temperature Range

-2S' C to +8S' C
8V
3V
300°C

Storage Temperature Range
VOO -VEE
VOO -VSS
Lead Temperature (Soldering, 10 seconds)

Voo + 0.3V to VSS - 0.3V
2 VOO to VSS - 0.3V
VOO + 0.3V to VEE - 0.3V
-S'C to +70'C

s:
s:

Electrical Characteristics
TA within operating range, Voo - Vss = 1.5V, Voo - VEE = 4:5V unless otherwise noted.
PARAMETER
Oscillator Start Voltage
Oscillator Sustaining Voltage

CONOITIONS

MIN

TYP

MAX

UNITS

TA = 25"C, INote 11

1.40

V

TA = _5°C. INote 11

1.30

V

Input Voltage Levels
BP/32 Hz Input
Logical "1"

VOO-{)·25

Logical "0"

VEE

VOO
VEE+0.25

V
V

All Others
Logical "1"
Logical "0"

VOO-{)·25

VOO

V

Open

Internal Pull-Down to VSS

VIN = VOO

12/24 Hr, Alarm Enable, Alarm

VIN = VOO

5

60

/lA

0.5

/lA

Tone, Colon Select
Output Current Levels

Segment Drivers
Logical "1"

VOUT = VOO - 0.2SV, VOO - VEE

= 3V

4

/lA

Logical "0"

VOUT = VEE - 0.2SV, VOO - VEE = 3V

4

/lA

Logical "1"

VOUT = VOO - 0.25V, VOO - VEE = 3V

40

/lA

Logical "0"

VOUT = VEE - 0.2SV, VOO - VEE = 3V

40

TA = 25°C

5

BP/32 Hz Output

FB Resistor R 1

/lA
40

Mfl.

Input Capacitance

Osc. Out

1=1 MHz, VIN=OV

All Others

All Other Pads GNO

20

pF
5

pF

-Supply Current (100)
Doubler Operation

TA = 2SoC, lEE = I/lA, f = 32.768 Hz,

15

/lA

Tripier Operation

VOO = 1.5V

20

/lA

Supply Voltage (VEE)

TA = 2SoC, C = 0.047/lF,

Doubler Operation

lEE = I/lA, f = 32,768 Hz,

-1.0

V

Tripier Operation

VOO - VSS = 1.5V

-2.0

V

Output Drive Current (Source)

Alarm Out, Sleep Out

VOO - VEE = 2.5V
mA

VOUT = VOO - 0.8V

Note 1: In oscillator network shown in Figure 6.

Functional Description
b) limit the power dissipation in the quartz crystal, and
c) provide added phase shift for good start·up and low
voltage operation. Cl and C2 in series provide the
parallel load capacitance required for precise tuning of
the quartz crystal. The network shown in Figure 6
provides greater than 100 ppm tuning range when used
with standard X-Y flexure quartz crystals trimmed for
CL = 13 pF. Tuning to better than 2 ppm is easily
obtainable. The 32 Hz output can be used to monitor
the oscillator frequency during the initial trimming
without disturbing the network itself.

A block diagram of the MM58143, MM58144, MM58183
and MM58184 LCO clock is shown in Figure 1, chip pad
layouts in Figure 2, connection diagrams in Figure 3,
and typical application in Figure 4.
Time Base: The precision time base of the clock is
provided by connecting a quartz crystal network to the
on-chip CMOS inverter/amplifier as shown in Figure 6.
For proper operation, the network should be tuned to
32,768 Hz. Resistor R 1 is used to bias the on·chip
inverter for Class A amplifier operation. Resistor R2 is
used to a) reduce the voltage sensitivity of the network;

5-75

CD

.....

..t
s:
s:
(II

CD
CD

.....

,SIo)

Input Current Levels

Fast, Slow, Oisplay, Sleep

(II

Functional Description

(Continued)

Display Control: The clock can display real time (real
hour and minutes), alarm time (alarm hour and minutes),
seconds, and sleep time (sleep minutes) under the
control of the "Display", "Sleep", "Fast" and "Slow"
switch inputs. The hour and the alarm hour are displayed in digit positions 1 and 2; the minutes, alarm.
minutes, seconds and. sleep minutes are displayed in
digits 3 and 4. Colon will be ON or flashing depending
on the logical state of the "Colon Select" input for all
modes, and OFF when alarm time is displayed. Hour and
Alarm Hour can be in either 12·hour format with PM

54.1

19.7

'.5- [lC4
19.7

23.,',

.... ,

~~

00

38.6

[lO' e;
[lEO ;1
[lC'

41.1

CAD~

29.2

61.3
61.9
16.B

(DEl

1•. 1

[lC2

99.6
107.2

[lO2
[l
[lE>

114.8

130.1
138.2

'45.9
162.5

~

~

L>

~i6

indicator or 24-hour format under the control of "12/
24 hour" input. Leading zero values of Hour and Alarm
Hour are blanked. Depressing the Display switch once
while the clock is in real time display will cause the
alarm time to be displayed and will return to real time
display after 5 seconds. Depressing Slow and/or Fast
while the clock is in real-time display mode will cause
the seconds to be displayed for as long as the said switch
is held and will return to real time display when the
switch is released.

71.2

106.9 122.8

92.5

0 0

§

o0

0 00.0

g ~~!~$~
S :=;
_

iii iii

::"
::: :;!"

III

~CoII

151.0
141.6

ADle

'32.1
122.7

F30
G30

103.8

AlIND[J

1

113.2

.U

B20
AlO

&7.1

no

512

G,C
G20

'17.'
41.1

39.3

~~

~'

AOEG ...

D

::l

---182MILS---

....
~CI ~ i ~

"0
G.C
8JC

1

MM58143

165.1

:I

Ii!
~

CleOlON

1551

0A40

w 11..."

[l

[lCI
[lCI
[lCI

142.•

1.8" 1".,115"1"00 I

!:~s

CI

~S;g§~al

Col

CC CCC [lC .,C

OOCOO

14J.;31,~J.1Z3;1116.9

aJ.:9"sJ.:',73J.s21.3,J.2

Do not use pads without function assigned

FIGURE 2. Chip Pad Layout

5-76

5.'

7J

Functional Description

(Continued)
Dual-In-Line Package

Dual-I n- Line Package
19

Vss
SLEEP

DISPLAY
ALARM OUT

SlOW

,. "

SLEEP OUT

C4

D4

"

F4

"

G4

EJ

,.

f3

COLON

OJ

Cl

02

"

C1

B2

E2

A2

CI

"

F2

24

BPlll HI

G2

BPlll HI

"

OSCIN

22

20

osc OUT

lJ

""

AlID]

CJ

J1

" ""

A4

C4

AllDJ

E2

SLOW

F4
JJ C4
12

CJ

02

16

35 A4

\0

Cl

lB

Vss

16

ALARM OUT

39 FAST

VDO

ALARM ENABLE

"

DISPLAY

40 ALARM ENABLE

12tH HR

40 12!Z411R

VDO

CAP2

VEE

11

3D

13
21

FJ

Gl

A2

""
"

"
"

2J
22 VEE
OSCOUT

20

OSC IN

s:
s:
en

TOPVIEW

TDI'VIEW

CO

Order Number MM58143N
See Package 24

Order Number MM58144N
See Package 24

CO

FIGURE 3a. MM58143 Clock-Radio

FIGURE 3b. MM58144 Travel Alarm
Clock Connection Diagram

Connection Diagram

.

Dual-In-Line Package
12/24 HR

19

ALARM ENABlE

Dual-In-Line Package
ALARM ENABLE

VDD

38 Vss
DISPLAY

J1

SLOW

J9 Voo

SLOW

38 Vss
J1

ALARM OUT

ALARM OUI

SLEEP OUT

GO

f4
GO

"

AJ/O]
AltO)

CJ
3D

Gl
Gl

COLON

,.

13

Cl
E2

"

F2
G2

VEE

B2

02

G2

"

2J
SPIll H1
22

C1

sPlllHl

2J

VEE

22

OSC OUT

OSt OUT

EJ

13

,." "

CI

"

,.

"

OSCIN

CAP2

Order Number MM58183N
See Package 24

Order Number MM58184N ,
See Package 24

FIGURE 3c. MM58183 Clock-Radio
Connection Diagram

FIGURE 3d. MM58184·Travel Alarm
Clock Connection Diagram

5-J/ipF

'---I--RADID

vss-'-L...----f

r---",,:,,---

I

....L..

ALARM

'1'
IL__ _

our 1-+-_--1

*Some pins are not available
in package version

FIGURE 4. Typical Application

5-77

JIl

s:
s:
en
CO

12124 HR

fAST

SLEEP

.....

.....

CO
0I:loo

Functional Description

(Continued)

~

o :0

Ob~O
=

o

60

I

:0 D<=)O 0:

C3

~

40PFI

O~O

_

I
1

~o

R1
20M

2~~k

C2

-,20pF

c. -< ~s~ _ _ _ ..J!.S~>IN

U 0::0 0::0 OU

IN

OUT

t---IOr------'
C1-~

ObO~ObO

32768 Hz

CRYSTAL

5-36 PF7f""

VOO DR VSS

FIGURE·6.,Osciliator Network

FIGURE 5. Character Font

ON

raSECS

. . .--,----In

JlI---..,;O~FF~n

1--1-----------

1 MINUTE

-1

i--ZSECS

n

10SECS

I

L

------------1

FIGURE 7. Alarm Output Waveform

Alarm Setting: Depressing the Display switch once while
the clock is in real time display will cause the alarm
hour and minutes to be displayed. Depressing the Fast
switch or both Fast and Slow switches will advance the
alarm time at 32 minutes per second until the switcl1es
are released. Depressing the Slow switch alone will
advance the alarm time at 2, Hz rate until the switch is
released. The clock will return to real time display in
5 seconds after the alarm time setting,

and alarm time display and setting controls are further
explained by the control state diagram shown in
Figure 8.

Sleep Timer and Output: The sleep output can be used
to turn off a radio (or other appliance) after a desired
interval of up to 59 minutes. The time interval is chosen
by selecting the sleep display mode and setting the
desired time interval. This automatically turns on a
current·source sleep output. When the sleep counter
which counts downwards, reaches 00 minutes, a latch
is reset and the sleep output current drive is removed.
The sleep output can be turned off by depressing
"Slow" or "Fast" switches while the clock is in real
time display. The sleep output will also be turned on
for -59 minutes whenever the alarm output turns on.

Time Setting: Depressing the Display switch once while
the clock is in alarm time display will cause the real
time to be displayed with hour and minutes flashing at
1 Hz rate indicating time setting is enabled. Depressing
the Fast switch or both Fast and Slow switch will
advance the real time at 32 minutes per second until the
switches are released. Depressing the Slow switch alone
will advance the real time at 2 Hz rate until the switch is
released. The clock will be in a hold mode whenever the
real time has been set, in which case, the seconds
counter is reset and held at zero; the colon will change
to the opposite mode, i.e., flashing colon with real time
display will change to fixed colon or vice versa. During
the time setting (Fast or Slow is depressed) the display
stops flashing, but the time is advancing at the setting
rate. Depressing Display. switch once while the clock is
in time setting mode or hold mode wiliTeturn the clock
to real time display and free the hold mode. This makes
it possible to easily synchronize seconds exactly. Real

Alarm Output: The current-source alarm output will
turn on at the preset alarm time if "Alarm Enable" is at
a logical "1" state. The alarm signal can be either a tone
or a DC level output depending on the logical state of
the "Alarm Tone" input. The tone output signal is
1024 Hz gated with 2 Hz. The alarm tone will be ON
and OFF periodically for 1 minute as shown in Figure 7
to conserve, power. If the "Slow", "Fast" or "Display"
switch is pushed during thisminute, the whole cycle as
indicated 'will repeat seven (7) minutes thereafter
(Snooze). The sleep out will also be OFF for 7 minutes,
then ON for another 59 minutes.

5-78

Functional Description

(Continued)

FAST
SEes DISPLAY

i

TIME DISPLAY

OR

:SEC

HR:MIN

SLOW

TURN Off

SLEEP

!

5SECI

R~~~~ I
IL

I

FAST OR
SLOW

LAMP

DISP2X

RESET

•

DrSP1X

FAST

__

SET ALARM

ALARM DISPLAY

FAST~

HR MIN
(NO COLON)

!

32 H!

SLOW= 2Hz

SLOW

BUTH"J2 Hz

OISPIX

s:
s:
en

SET TIME
FAST =]2 Hz

fAST/SLOW

SlOW-2 Hz
BOTH ~ 32 HI
EITHER ENABLES

HOLD

HOlOSEtOO

fAST

'--r-...----'

L-____

~----~I

AND SLOW

CO

......

'------'

iL-__________~FA~ST~A~NO~S~LO~W~__________~

CO

~C/.)

DJSPIX

s:
s:
en

FIGURE 8. Time and Alarm Display Setting Control State Diagram

CO
......

Sleep Timer Setting: Depressing the Sleep switch
while the clock is in real time display will cause the
content of the sleep counter to be displayed (if sleep
counter is at 00, it will reset to 59 immediately) until
the switch is released. Holding the switch closed for
longer than 2 seconds will decrement the sleep counter
by ten at a 2 Hz rate (i.e., 59,49, etc.) until the switch
is released. However, if Fast or Slow is also depressed
at the same time; the unit portion of sleep counter
will decrement at a 2 Hz rate until all switches are
released. The clock will return to real time display
after all switches have been released for 2 seconds.

when Fast and Slow are released and resume running
after Display is depressed once. This feature will enable
fast check of all segment interconnections and set the
clock to a known state. b) backplane/32 Hz (BP/32 Hz)
output can be used also as an input to speed up func·
tional testing.
SUMMARY OF CONTROL INPUTS
Each of the following inputs has a pull·down resistor
to VSS.

All snooze and sleep control features are further described
by the control state diagram of Figure 9.
Indicator Outputs: a) alarm indicator (ALlND) will be
flashing when alarm time is displayed. It will be ON and
fixed when alarm enable is at logical "1" state. This out·
put is not available for MM58144 and MM58184 pack·
aged units, b) sleep indicator (SLlND) will be flashing
when sleep minutes is displayed. It will be ON and fixed
when sleep output is ON. This output is not available for
all packaged versions, c) PM indicator will be on for PM
time in 12·hour mode for both real time and alarm time.

VSS OR OPEN

VDD

12/24 Hour

12·Hour Mode

24·Hour Mode

Alarm Tone
Alarm Enable

Tone
Alarm OFF

Alarm Enable

Colon Select

Flashing Colon

Fix Colon

DC

Contact Bounce:. Debounce circuitry is provided on the
Display, Slow, Fast and Sleep inputs to remove any
logic uncertainty upon either closure or release of
switches provided switch bounce settles within 125 ms
(8 Hz debounce frequency).

Power·ON Reset: When power is first applied, the
internal power·ON reset signal will reset and hold the
real time to 1 :00 AM and alarm time to 1 :01 AM.
The real time will be displayed with fix colon. De·
pressing the Display switch will free the clock into
normal running mode.

Segment Outputs: The segment outputs are designed to
drive field·effect liquid crystal displays. Each display
segment has its own output which furnishes the proper
32 Hz drive signal. By definition, the segment is OFF
when its drive signal is in phase with the display back·
plane signal (BP/32 Hz). The segment is ON when its
drive signal is 1800 out of phase with the di splay back·
plane signal. Typical output waveforms are shown in
Figure 11.

Test Features: a) master reset and lamp test. Depressing
the Display switch twice while either the Slow or Fast
switch is held in will cause all segments and indicators
to turn on and also reset real time to 1 :00 AM and alarm
time to 1 :01 AM. The clock will return to Hold mode

5·79

CO
~

Functional Description

(Continued)

RESET
SLEEP TO

00

SLEEP
(HELD >2 SECS,
AL ARMOFFI

SLOW OR
FAST

..

DISPLAY, SLOW

•

TIME DISPLAY
HR:MIN

J

_t

OR FAST
..(ALARM
•
ACTIVEI

SE~ 7 MIN
SNOOZE TIME

t

rJ

2 SEC AFTER
SLEEP RELEASE

I

DISPLAY
SLEEP COUNTER
IF 00 SET TO 59 MINS

DECREMENT SLEEP
COUNTER
TENS (59, 49 ...1

SLEEP
(HELD >2 SECSI

SLEEP

DECREMENT UNITS
1 MIN/SEC

AND SLOW
OR FAST

FIGURE 9. Snooze and Sleep Control State Diagram

El

PM

El

ALARM

A2

~F2D~
El

G2

C=>

C=>

~o E2~O

A3

C=>
0

E3D

COL 0 N

02

El

F3o:7(j

0

C30

<:::::=::j

SLEEP

F4

o:;u
A4

C=>

E4D

C40

<:::::=::j
04

03

FIGURE 10. Display Format

VOO
COMMON
VEE

VOO
SEGMENT
VEE

1-...

1<----

OFF - -_____

1_...< - - - -

ON

FIGURE 11. Common and SegmentOutput Signals

Digital Clocks

~National

~ Semiconductor

Preliminary

MM7317B, MM7318B Alarm Clock Calendar
General Description

Features

The MM7317B, MM7318B digital alarm clocks are
monolithic MOS integrated circuits utilizing P-channel
low-threshold enhancement mode and ion implanted
depletion mode devices. Featuring a 4-year calendar,
each chip includes all the logic required to build
several types of clocks and timers with up to 5
display modes: HOUR and MINUTE, MINUTE and
SECONDS, SLEEP DELAY, ALARM SETTING and
CALENDAR DISPLAY. Setting is done via the
standard Fast/Slow Set buttons when the chip is in
the various display modes. They are specifically
intended for clock-radio applications as radio noise
interference commonly associated with multiplexed
display drives is eliminated by direct drive output
buffers. 0_3" to 1.0" LED or fluorescent 7-segment
displays can be used without buffering. Through
hardware selection, users can have 12 HR with
AM/PM indicator or 24 HR display format, 50 or 60
Hz input for the timekeeping function. Outputs
also include the sleep (e.g. timed radio turn-off).
1 Hz activity indication and alarm output. A snooze
feature is provided for a 9-minute repeat of the alarm
after it \las sounded.

•
•
•
•
•
•
•
•
•
•
•
•
"
•
•
•

The chips operate over a wide supply range and low
standby operating voltage facilitates use of a battery
back-up in case of line voltage failure, whose occurrence is indicated by a special display mode. The
MM7318B incorporates, in addition, on-chip 50/60
Hz line frequency back-up oscillator, 900 Hz alarm
tone generator, a 9-minute delayed alarm mode and
loss of line frequency indication.

Applications

•
•
•
•
•

•
•
•
•
•
•

50/60 Hz operation
12/24 hour display mode
AM/PM outputs
24 hour alarm set
9-minute snooze alarm
Fast/Slow set
Direct LED, VF drive
Single power supply
Power failure indication
4 year calendar
Presettable 59-minute, sleep timer
Battery back-up
No illegal time display at Power-ON
Sink/source current to radio
Display blanking (MM7317B)
Separate alarm and radio (sleep) outputs for
simple off-chip mode switching
1 Hz activity indicator
On-chip line frequency back-up oscillator
(MM7318B)
On-chip alarm tone output (MM7318B)
Line frequency failure indication (MM7318B)
3 alarm modes (MM7318B): Alarm ON, Radio
ON, Alarm ON 9-minute after Radio ON'.

Alarm clock-calendars
Desk clock-calendars
Clock radios
Automobile clocks
Stop watches
Industrial clocks

•
•
•
•
•

Sequential controller
Portable clocks
Industrial timers
Appliance timers
Photography timers

Block Diagram
SNOOZE INPUT _ _ _ _ _.,

SEC

ALARM OFF

(MM731JB) _ _ _ _.,

1----+ HR DIGIT

1----+ 10's MIN DIGIT

AUTO ALARM
(MM73188) - - - - ,

1----+ MIN DIGIT
CODE

AUTO RADIO
(MM1318B)

CONVERTER
&
OUTPUT
DRIVE

ALARM OUTPUT

CIRCUIT

SLEEP OUTPUT

1 + - - - BLANKING (MM7317B)

ase

(MM7318Bl

IO .sHR ,:

OUTPUT COMMON
i+---SOURCE (MM73178)

50/60 Hz INPUT
50/60 Hz SELECT
FREn. CONTROL

1----+:{CI
1----+IH'

L,[""]r:I,J~---12124 HR SELECT

'--________-+-+--+_____ SECOND O[SPlAY
L-----------t--'------'--_ _ _ _ _ _ _ _ _ _......._ ' - -_ _ _ _
L-________.,-_________
L-___________________
Figure 1_

5-81

ALARM DISPLAY
SLEEP DISPLAY
SLOW SET

fAST SET

Absolute Maximum Ratings (Exceeding the following ratings may result in perrnanent damage to the device).
Voltage at Any Pin
Vss +0.3V to Vss -30V
0° to +70°C
Operating Temperature (ambi,entl
_55°C to 150°C
Storage Temperature
Lead Temperature (Soldering, 10seconds)
300°C

Electrical Characteristics
PARAMETER

(MM73188 values in brackets when they are different from those of MM7317B)
TA within operating range, Voo = OV, Vss = 8 to 30V (Vss = 7.5 to 28V)
Unless otherwise specified.

CONDITIONS

Power Supply Voltage

Operating
Functional Clock

Power Supply Current

No Output Loads
Vss = 7V (7.5V)
Vss = 30V (28V)

V
V

4 (5)
5 (6)

mA
mA

15K

Hz

Vss

V

Vss - 6
(Vss - 5)

V

(0.1)
(DC)
(-14)

(1.1 )
(5K)
(+ 14)

mA
Hz

Vss -1.5
Voo

Vss
Vss -;-5

V
V

V 1N = Vss -1:8V, TA = 25°C
C = 0.005 IlF, R Adjusted
For 1800 Hz at Vss = 9V

%

7.5V';;; Vss';;; 28V

(900)

Alarm Output Frequency
Alarm/Sleep Output Current
Logical High Level
Logical Low Level

Vss ;;'8V
VOH=Vss-2V
Vss = Voo + 0.6V

Output Current Levels

Vss ;;'24V
Output Common = Vss

10's Hours (B/C)
Logical High Level

50/60

Vss -1
(Vss -1 . 5)
Voo

Le~el

All Other Input Voltages
Logical High Level
Logical Low Level

30 (28)
30 (28)

DC

50/60 Hz and Blanking
Input Voltages
Logical High Level

Frequency Control Input
Input Current
Frequency OSC
OSC Frequency Variation

UNITS

TYP

8 (7.5)
7 (7.5)

50/60 Hz Input Frequency

Logical Low

MAX

MIN

Hz

mA
IlA

3.5
1.0
Note 1

VOH = Vss - 3.1V 12 Hour Mode
24 Hour Mode
VOL = Vss - 28V

20
10
-10

mA
mA
IlA

10's of Minutes (A/D)
Logical High Level
Logical Low Level

Vss;;' 24V
VOH =Vss -3.1V
VOL = Vss - 28V

20
-10

mA
IlA

1 Hz display
Logical High Level
Logical High Level

Vss ;;'24V
VOH = Vss - 3.1V
VOL = Vss - 28V

25
-10

mA
/iA

All Other Displays
Logical High Level
Logical Low Level

Vss;;' 24V
VOH =Vss -3.1V
VOL = Vss - 28V

10
-10

mA
IlA

Logical Low Level

Note 1: Output current must be limited so that total device power with loads does not exceed 750 mW at 70°C and l.4W at
25°C.

5-82

Functional Description
MM7317B, and 59 minutes for MM7318B) in which the
alarm latch remains set. Connecting this pin to Vss also
enables the calendar display mode as shown in Table L

A block diagram of the MM7317B, MM7318B digital
clock calendar circuit is shown in Figure 1. The various
display setting modes are listed in Table 1 and Table 2
shows the setting control functions. The following
decription is based on Figure 1 and refers to both
devices unless otherwise specified.

Alarm Modes (MM7318B): There are 3 alarm modes
which are auto alarm, auto radio and delayed alarm.
Internal pull·down resistors (typical 100K.Q) allow use
of simple SPSTswitches to select alarm modes. Selection
is effected by connecting the corresponding input pin to
Vss. In the auto radio mode, the radio output is enabled
when real time is coincident with alarm time. In the
auto alarm mode, the alarm output is enabled when real
time is coincident with alarm time. If both auto radio
and auto alarm modes are selected, a third mode results.
This is the delayed alarm mode in which the radio
output is enabled when real time is coincident to the
alarm time. 8 to 9 minutes later the alarm output is
enabled and snooze input only affects the alarm output.
To reset the alarm mode, connect the selection pins to
VDD·

50 or 60 Hz Input: A simple RC filter should be used to
remove possible line voltage transients that could either
cause the clock to gain time or damage the device. A
schmidt trigger circuit of 2V hysteresis is provided to
allow the use of sinewave input and its output drives a
counter chain that performs the timekeeping function.
50 or 60 Hz Select Input: A programmable prescale
counter divides the input frequency to obtain a 1 Hz
time base. 50 Hz operation is selected by connecting
this input to Vss. Leaving this input unconnected selects
60 Hz operation. Pull down to VDD is provided by an
internal depletion load (typical 100K.Q).

Frequency Control Input (MM7318B): A resistor in
parallel with a capacitor is typically connected from this
. pin to Vss. The frequency of osci lIation is divided by 2
to give the alarm tone. The frequency is further divided
by 18 for 50 Hz operation or by 15 for 60 Hz operation.
The frequency coming out of the divider chain is used as
a backup frequency when there is a loss of input line
frequency. For accurate backup operation, the oscillator
frequency must be set to 1800 Hz by adjustment of
the externally connected resistor/capacitor at this pin.

Display Mode Select Inputs: (Refer to Table I) Alter·
nate display modes are selected by applying Vss to the
appropriate pins. An internal pull·down resistor (typical
100K.Q) allows use of simple SPST switches to select the
display mode. In the absence of any of these inputs, the
display drivers present time of day information. If more
than one mode is selected, the priorities are as noted in
Table L Constant calendar display is possible by tying
both alarm display and seconds display inputs to Vss.
This mode has an automatic interrupt from calendar to
real time when the alarm output is enabled.

Blanking Control Input (MM7317B): Connecting this
schmidt trigger input to VDD places all display drivers
in a non·conducting, high·impedance state, thereby
inhibiting the display. ConverselY, Vss applied to this
input enables the display. This pin has a dual application. Pulse percentage modulation can offer display
brightness control. The input can also be used as a
display chip select.

Time Setting Inputs: (Refer to Table II) Both Fast
and Slow Setting inputs are provided. These inputs are
applied either Singly or in combination to obtain the
control function listed in Table I L Again, internal pull·
down resistors (typical 100K.Q)are providedjapplication
of VSS to these pins effects the control functions.
12 or 24 HR Select Input: By leaving this pin uncon·
nected, the outputs for the most significant display
digits (1 O's of hours) are programmed to provide a 12
hour display format. An internal pull·down resistor
(typical 100K.Q) is provided. Connecting this pin to
Vss programs the 24 hour display format. The output
connections are different for each format as illustrated
in Figure 2,

::--iJ'
PM-+OCi-J
TNC

Alarm Off Input (MM7317B): Momentarily connecting
this pin to Vss resets the alarm latch and thereby silences
the alarm. This input is returned to VDD by an internal
resistor (typcial 100K.Q). The momentary alarm off
input also enables the alarm latch for the next compara·
tor output and the alarm will automatically sound again
in 24 hours (or at a new alarm setting). If it is desired
to silence the alarm for a day or more, this pin shOUld
remain at Vss.

NC-II-AM
~
-I-I---

'H'

PM

Sleep Output: The sleep output may be used to turn off
a radio or other device after a desired time interval of up
to 59 minutes. The time interval is chosen by selecting
the sleep display mode and setting the desired time
interval (Table Ill. This automatically results in a current
source sleep output which may be used to turn on a
radio or other device. When the sleep counter which
counts downwards, reaches 0 minutes, the sleep output
current drive is removed, thereby turning off the device.
This turning off may also be manually controlled (at any
time in the countdown) by a momentary VSS connection to the snooze input.

B& C

12HR

24 HR

Figure 2. 1 D's. of Hours Digit Wiring Options
Snooze/Calendar Mode Input: Momentarily connecting
this pin to VSS inhibits the alarm output for between
8 and 9 minutes, after which the alarm will again be
sounded. This input is pulled down to VD D by an
internal resistor (typical 100K.Q). The snooze feature
may be repeatedly used during the time (45 minutes for

5-83

Functional Descriptions (Continued)
Table I. DISPLAY MODES
'Selected
Display Mode

Digit # 1

Digit#2

Digit#3

Digit#4

10's of Hours
and AM/PM

Hours

10's of Minutes

Minutes

Blanked

Minutes

10's of Seconds

Seconds

Alarm Display

10's of Hours
and AM/PM

Hours

10's of Minutes

Minutes

Sleep Display

Blanked

Blanked

10's of Minutes

Minutes

10's of Months
or Blanked

Months

10's of Days
or Blanked

Days

10's of Days
or Blanked

Days

10's of Months
or Blanked

. Months

Time Display

Seconds Display

Calendar Display
12 Hour Mode

24 Hour Mode

'If more than one display mode input is applied, the display priorities are in order of Sleep (overrides all others).
Calendar, Alarm, Seconds, and Time.

Table II. SETTING CONTROL FUNCTIONS
Selected
Display Mode

I

Enable
Via

'Time

Alarm

. Seconds

Control
Input

Control Function

Slow
Fast
Both

Minutes advance at 2 Hz rate.
Minutes advance at 60 Hz rate.
Minutes advance at 60 Hz rate.

Alarm
Display

Slow
Fast
Both
Both

Alarm
Alarm
Alarm
Alarm

Seconds
Display

Slow
Fast

Input to entire time counter is inhibited (hold).
Seconds and 10's of seconds reset to zero without a
carry to minutes.
Time resets to 12:00 AM (12·hour format).
Time resets to 00:00:00 (MM7318B), - 0:00:00 (MM7317B)
(24 hour format).

Both
Both

minutes advance at 2 Hz rate.
minutes advance at 60 Hz rate.
resets to 12:00 AM (12·hour format).
resets to 00:00 (24·hour format).

Sleep

Sleep
Display

Slow
Fast
Both

Subtracts count at 2 Hz.
Subtracts count at 60 Hz.
Subtracts count at 60 Hz.

Date

Snooze

Slow

Alarm (MM7318B)
Sleep (MM7317B)
and Seconds
Display

Fast

Day advances at
Month advances
Day advances at
Month advances

2 Hz rate.
after proper number of days.
60 Hz rate.
after proper number of days.

'When setting time, sleep minutes will decrement at rate of time counter until the sleep counter reaches 00
minutes (Sleep counter will not recycle).

5·84

Functional Descriptions

s:
s:
.......

(Continued)

Display Outputs: The 1 Hz display output is normally
used to drive the colon of the associated display. Refer
to Table III. for output drive capability.

latch remains set, the alarm wi II sound if the latch
outPut is not temporarily inhibited by another latch set
by the snooze input or reset by the alarm off input.
During a power fail detect condition, the alarm circuitry
may function as normal. However the power voltage
may drop enough so that the alarm circuitry inhibits its
output. In this case, the alarm has to be reset by going
to alarm set mode via the fast or slow set, resetting the
alarm time.

Table III. OUTPUT BUFFER DRIVE CAPABILITY
Display

10's Hrs

12 Hour
24 Hour

2
1

10's Mins

1 Hz

AM

PM

231
231

(MM7318B): Two latches are set to enable the alarm
output or sleep output followed by delayed alarm
output, depending on which mode was selected. The
sleep output provides a DC transition from VDO to VSS
at the alarm time, which can be used to turn on a radio
or other device. The alarm output is a square wave at
the frequency of Y, of the on·chip oscillator frequency.
If the frequency oscillator input pin is returned to V DO,
there will be no backup oscillator and the alarm outPut
will be a DC transition from Voo to Vss. The alarm
latch remains set for 59 minutes. During this time the
alarm will sound if the latch output is not temporarily
inhibited by another latch set by the snooze input or
reset by auto alarm and auto radio inputs. If snooze is
enabled while an alarm mode output is enabled, the
contents of the alarm counter may be altered, multiple
use of the snooze function may cause the total alarm
enable time to be less than 59 minutes.

All other buffers have 1 segment drive capability.
Power Fail Indication
(MM7317B): This indication consists of all on segments
flashing simultaneously at a 1 Hz rate. A Fast or Slow
Set input resets an internal power failure latch and
returns the display to normal. During a power fail
condition, the alarm setting may become invalid. In this
case, the alarm output is inhibited.
(MM7318B): There are two different power fail indications Frequency Fail and Voltage Fail. Frequency
failure will occur when the 50/60 Hz generated by the
internal oscillator frequency counts 4 cycles without the
line frequency making a positive transition. While line
frequency is missing, display will be bianked, and time
and alarm functions will continue to operate from the
internal oscillator frequency evenly divided down to
50/60 Hz. Auto alarm will override auto radio and
delayed alarm. Frequency failure is self-clearing, except
for the frequency fail indication, when line frequency is
restored. Frequency failure is indicated by the entire
display flashing at a 1 Hz rate.

Output Common Source Connection (MM7317B): All
display output drivers are open drain devices with all
sources common to this pin. This feature allows use of
either common cathode or common anode LED
displays. When using fluorescent tube displays, VSS or
a display brightness control voltage may be connected
to this pin. The common source connection also
facilitates generating AC drive voltages when liquid
crystal displays are used.

Voltage failure will occur when Vo 0 drops below a
minimum operating voltage into the detect range.
During low voltage failure, the display is blanked and the
time functions are reset and held in that state_ Sleep
counter is reset to 59 and seconds to 00. Alarm time
and time are reset to 12:00 AM (12 Hour Mode) or
00:00 (24 Hour Mode). Date is reset to 12 in month
units and 1 in day units.

---~+---__i 50/60 Hz INPUT

ALARM OUTPUT

MM7317
OUTPUT COMMON SOURCE

SLEEP OUTPUT

+---~-----~+--*-__ivoo

BLANKING INPUT

1--------'>; DISPLAY

L...------....:.:=fi:=========-____-l

SELECT PIN

MM5430 RADIO FRED.
COUNTER CIRCUIT

lEO DISPLAY
(COMMON ANODE)

Vss

Figure 4. Typical Application (MM7317BN): Clock/Calendar with Digital Frequency Readout for Radio

MM7318
SLEEP OUTPUT

t-'--.......'Nv'---I

Voo
ALARM OUTPUT t-'--~WV-----t

lEO DISPLAY
(COMMON CATHODE)

Figure 5. Typical Application (MM7318BN): Clock/Calendar with Battery Back-up

5-86

Connection Diagram

Dual-In-Line Package

TOP VIEW

~

AM OUTPUT

U

10HASB&C~

HASF
HAS G
HRSA

~

2
.1

~
~

~
~
~

-..!.

~

HRSB
HAS 02HAS C
HRS E
10 MINS F
IOMINSG

.,2

.!.Q
~

~

MM7317B
or
MM7318B

10MINSA&O..!1
10 MINS B .!2

~
10MINS C ~
MINS F ..!.!!

10MINSE

~

PM OUTPUT
I Hz OUTPUT
12124 HR SELECT (FREO. CONTROL)
BLANKING OUTPUT (501E0 Hz INPUT)
50/60 Hz SElECT
50/60 Hz INPUT (FAST SET INPUT!
FAST SET INPUT (SLOW SET INPUT)

SLOW SET INPUT (VOO)
SECONO OISPLAY INPUT (SLEEP OISP INPUT)

~...g ~;~ ~;~ ~ ~ ~I~ N~l~ :I: A:~:!: ~:~: UT)
~
~
~

~: ~;~ ~

(

7s
i-=

SLEEP OUTPUT (SECONOS OISPLAY INPUT)
ALARM OFF INPUT (ALARM OUTPUT!
ALARM OUTPUT (SLEEP OUTPUT)

SNOOZE/CALENOAR MOOE INPUT (ALARM OISP INPUT)

~ OUTPUT COMMON SOURCE (VSS)

'ft MINS C
I-'-'

MINS 0

) indicates pin connection for MM7318B
Order Number MM7317BN
or MM7318BN
See Package 24

5-87

Televisionl Radio

'?A National

Televisionl Radio

~ Semiconductor

MM5321 TV camera sync generator
general description

features

The MM5321 TV camera sync generator is aMOS,
P-channel enhancement mode, LSI chip designed to
supply the basic sync functions for either color or
monochrome 525 line/60 Hz interlaced camera and
video recorder applications_ Required power supplies
are +5V and --12V, or any other combination resulting
in VSS - 17V_ All inputs and outputs are TTL compatible without the use of external components_
.

"

Multi-function gen lock input provides flexible control of multiple camera installations

•

16-lead dual-in-line package

•

Conventional +5V, -12V power suppl ies

•

Uses 2_04545 MHz or 1.260 MHz input reference

•

Field indexing provided for VTR applications

•

Color burst gate and sync allow stable color operation

logic and connection diagrams
HORI10NTAl RESET

CONTAOL

HORIZONTAL

0-------------,
O------1r-----,

COLOR BURST
GATE OUT

RESET

CLOCK
INPUT

HORIZONTAL
DRIVE OUT

COLOR BURST
SYNC OUT

DIVIDER

CONTAOl

COMPOSITE
SYNC OUT

VERTICAL
RESET
CONTROL

VERTICAL
RESET

~--~L

_ _- - '
VERTICAL
DRIVE OUT

1

FIELD
INOE,x.

Vss

Dual-In-Line Package

COMPSYNC OUTPUT

VGO

16

DIVIDER CONTROL

15

Hz DRIVE

CLOCK INPUT

14

COMP BLANKING

Hz RESET

13

COLOR BURST SYNC

VERT RESET

12

COLOR BURST GATE

VERTICAL RESET

CONTROL
HORIZONTAL RESET
CONTROL

11

VERT DRIVE

10

OPEN
VERT INDEX

Vss

TOP VIEW

Order Number MM5321 N
See Package 19

5·91

absolute maximum ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)

VSS + 0.3 to VSS - 22
O°C to +70°C
-65°C to +150°C
300°C

dc electrical characteristics
TA within operating temperature range VSS= 5V ±5%, VGG = -12V ±5%, unless otherwise stated.
CONDITIONS

PARAMETER

MIN

MAX

UNITS

Input Levels
VIH

Logical Hig,' Level

VSS-l.5

VSS+0.3

V

VIL

Logical Low Level

VSS-18

VSS-4.2

V

VIN = -10V, TA = 25°C,

Input Leakage

0.5

JJ.A

6

pF

0.5

/.I.A

6

pF

All Other Pins GND
Input Capacitance

VIN=OV,f=lMHz,
All Other Pins GND, (Note 1)
VIN = -10V, TA = 25°C,

Clock Input Leakage

All Other Pins GND
Clock Input Capacitance

VIN = OV, f = 1 MHz,
All Other Pins GND, (Note 1)

Output Levels
VOH

Logical High Level

ISOURCE = -0.5 mA

VOL

Logical Low Level

ISINK = 1.6 mA
MOS Load

IGG

. Power Supply Current

2.4
VSS-12.5

TA = 25°C, VGG = -12V,

V

VSS
0.4

V

VSS-9

V

36

mA

q,PW = 235 ns, VSS = 5V,
Input Clock Frequency =
2.04545. MHz

ac electrical characteristics
T A within operating temperature range VSS = 5V ±5%, V GG = -12V ±5%, unless otherwise stated.
PARAMETER
q,PW

Input Clock Pulse Width

CONDITIONS

MIN

MAX

UNITS

Input Clock Frequency =

190

280

ns

300

570

ns

500

800

ns

2.04545 MHz, q,t r , q,tf= 20 ns
Input Clock Frequency = 1.26 MHz,
q,t r = q,tf = 20 ns
Horizontal Reset Pulse Width

Withi n 400 ns after the Fall ing Edge
of Master Clock, (Figure 5)
Rise and Fall Time = 20 ns

tpd

Output Propagation Delay

VOH

Logical High Level

Capacitance at the Output = 15 pF

750

ns

VOL

Logical Low Level

(Figure 5)

750

ns

Note 1: Capacitance is guaranteed by periodic testing.

5-92

functional description
EXTERNAL CONTROL LEVELS

eously by connecting the Vertical and Horizontal Reset
pins together and driving them with the same reset
signal. Actual resetting of the vertical divider is to
either of two states, depending upon the state of the
Vertical Reset Control input; to zero, or to the fifth
vertical serration pulse (eleven 0.5H time intervals from
leading edge of Vertical Blanking). Refer to the reset
table. The horizontal divider will always be reset to a
position which is 8 input clock pulses from the leading
edge of the serration gate in the horizontal timing
scheme (Figures 2 and 3). The generator is reset to the
odd field (field one). The Field Index output pulse
occurs once each odd field at the leading edge of Vertical
Blanking. It can be used to reset, or "gen·lock," similar
sync generator chips by connecting it to their Vertical
and Horizontal Reset inputs. The Horizontal Reset
Control selects Horizontal Reset to the start or center
of a line. For "gen·lock" both' Horizontal and Vertical
Reset pulses should not exceed 800ns.

Horizontal Reset occurs for Logic "0." This resets the
horizontal counter to a state shown in Figures 2 and 3.
Vertical Reset occurs for Logic "0." This resets the
vertical counter to a state determined by reset control
input as shown below:
VERTICAL RESET

PERMITS THE VERTICAL

CONTROL INPUT

COUNTER TO RESET TO THE:

VIH. (VSS)

Oth count

VIL. (VGG)

11th count

HORIZONTAL RESET

RESETS THE HORIZONTAL

CONTROL INPUT

DIVIDER TO:

VIH

Beginning of line
Center of line

VIL

Logic "0" = VIL
Logic "1' =VIH

OUTPUTS

The generator supplies the following standard output
functions: Horizontal Drive Out, Vertical Drive Out,
Composite Blanking Out, Composite Sync Out and the
Color Burst Gate.

Divide select input = V IL, (V GG) for master clock
frequency of 1.26 MHz.
Divide select input = VIH, (VSS) for master clock
frequency of 2.04545 MHz.

In addition, Field Index and Color Burst Sync outputs
are provided. The Field Index identifies the odd field,
or field one, by occurring for two clock periods at the
leading edge of Vertical Blanking in that field. Thus, its
rate is 30 Hz. As described above, it can also be used to
"gen·lock" other sync generator chips.

INPUTS

The user may select either of two input clock frequencies
by properly programming the Divider Control pin. In
one case the input frequency is 2.04545 MHz, which is
14.31818 MHz divided by seven. The other is eighty
times the horizontal frequency, or 1.26 MHz. The
divider control will be programmed by connecting it to
VIH (VSS) and VIL, (VGG) respectively.

The Color Burst Sync output signal occurs at half the
horizontal rate with the same timing as the Color Burst
Gate output. It may be used to sync the color burst as
it will have the same delay characteristics as the other
outputs (including, of course, the Color Burst Gate) the color burst sync is present during the vertical interval.

There are separate Vertical and Horizontal Reset inputs
which allow directly resetting the appropriate divider(s)
by a control pulse generated by external means. Both
horizontal and vertical dividers may be reset simultan·

Differences in phasing between outputs are minimized
by the use of identical push-pull output buffers clocked
by the internal clock.
.

typical performance characteristics
Typical IGG vs Power Supply
Voltage (VSS - VGGI

Typical IGG vs Temperature
34
32

1-'1 CLOCK FREQUENCY' 2.04545 MHz
TA '25'C
¢pw= 235 ns

30

'-'1-~'------'Ir-TI"""I-r-I'--1

'v

-,--,-..,...,...1"--,---,--,'1-...,.-,---,---,---,--

+5 - , - . . , . . . , - - , - . . , . . . , - - , - . . . , . - , - - - , - - - , - - - , - -....

ov

.,
'v

~9H~

I.: 1119H~1
I. '

,I

262.5H

.,
'v
+5

ov

[:----525H

nTTlr---'

~-~.

----21'

r1L-_,----,-----,-___

-+':-_-,,-+""7""'"-,,-'-;-1-,-,-:-1-,----------' +,,+,,+,,--l--SER·

EQUALI·

RATION

ZATION

COMPOSITE +5
SYNC
OV

•

b

~--~--------~

'12~

--I

FIGURE 1.

,

~ ITA =

"

2.04,545 MHz =

TID " 0.489>1$

MASTER
CLOCK

INPUT

--====='======~~~~~~~~~~

I

r:-~'TA""I'29'=1-

r--

SERRAT:iGATE

fRONT PORCH" 3 TA::'! 0.02ltH

~r~---------------------------EQUALIZATION
GATE

r

HORIZONTAL SYNC

1

-------13TA== O.lDOH~--1

HORIZONTAL DRIVE

r------

-----22TADO.t694H---.. -.~

HORIZONTAL BLANKING
5TA",D.OJ86H

COLOR
BURST GATE

FIGURE 2. Horizontal Timing Master Clock

5-94

= 2.04545 MHz

switching time waveforms

(Continued)

o

1

rTO'"

I
"
iT6'ii"Miii
= iiii·

I-

-J Is

O!

0.794iJ$

0.0375H

!EQUALIZATION GATE

=1-'

- - - -......
j

F

:Ta,-"0.015"

HORIZONTAL SYNC

~BTB~O.'H-----1
HORIZONTAL--1

BACK PORCH

I

610:::.0.075H

DRIVE

I

1-'---------

r--~14TB~O.175H-----------I
HORIZONTAL BLANKING
COLOR BURST GATE

- 3TS"'" 0.0375H

FIGURE 3. Horizontal Timing Master Clock

= 1.26 MHz

V

2H PERIOD
I8

12

~L-_ _ _ _ _ _ _ _ _ _~V~ER~T~IC~Al~8~lA~N~K~IN~G_ _ _ _ _ _ _ _ _~.~
21"

l:::~-'"--.-.

:=i=.- ---'"----.

EQUALIZATION GATE

SERRATION GATE

'"
VERTICAL DRIVE & HORIZONTAL SYNC INHIBIT

'"
MASTER CLOCK PERIOD
(ONCE EACH ODD FIELD)

fiELD INDEX

FIGURE 4. Vertical Timing

Display
V's
MASTER CLOCK

OV--II-=II

Vss--+---'"\ ,.,,,-""",----OUTPUT

IVss -,V)---t----"F"'-=----RESET PULSE

V7=VIL

V7 =VIH

FIGURE 6. Horizontal Reset Characteristics

FIGURE 5.

5·95

.....

~

typical application

U')

:E
:E

Vee ~ 5V

SV Vss
HORIZ
RESET

--,

8
16
15

I VERTICAL
RESET

14

13

I

COMPOSITE
SYNC INPUT

MM5321

12

11
HORIZ
RESET
CO NT

DIVIDE
SELECT

VGO

TTl

L -

TTl

-12V

ENil.J

L
TT L I "torfaco

5-96

-1'.0.J

~National

~ Semiconductor

.

Televisionl Radio

MM5322 color bar generator chip
general description

features

The MM5322 Color Bar Generator Chip is a complete
dot-bar and color hue generation system in a single
monolithic P-channel MOS integrated circuit. The chip
divides an internal oscillator (crystal controlled) fre'quency to provide the various timing, synchronization,
and video information required in the alignment of color
television receivers. A composite video output is provided for complete black and white dot-bar operation.
It consists of all synchronization, blanking, and video
information required for a fairly standard set of dot,
bar, and cross hatch screen patterns. In addition a
separate output for precise gating of 3_56 MHz color
bursts is provided_ For servicing ease an oscilloscope
trigger is provided on either the horizontal blanking or
vertical synchronization time slots.

typical application
,W1
POWER

~
1+ >

Battery operation

• Oscilloscope trigger
.. Composite video output signal
• Crystal controlled oscillator
•

Multiple screen patterns

•

Variable dot size

applications
•

Battery or bench powered test instruments

•

Manufacturing test sets

• Built in test capability

Typical Color Bar Generator Circuit

"POWER" INDICATOR
\ I/

~I

OSCilLOSCOPE

Ov'

TRIGGER
OUTPUT
(NOTE 41

LED= NSL5023

9V BATTERIES

~

•

V·

+

'WI
(NOTE 11

T'"'

.----t.------.....-or 0 - - v'

62pF

r;+--+---ts----t-,

--.--.-I ~

i3\-13

MM532Z

22M

BCD

1-....-~.;;...---t'D

10pF

(1)

(2)

l'~1~9~-i3~~4

NPO
(NOTE 3)

470

D.D01J,Jf
LEVEL

18)

__'~~'~~~~-~~"1

4.7k

lOOk

I.Sk
COLOR

(41

1k
47pF

:>011--'11''''''-+-1

SWJ

1k

~:~u

PATTERN
SELECTORS

10.

r - - - - -.....- -......JI,;'II'v-015V
~Iternative

Resonator

41

JOpF

PIN 1 3 0 - - - - -.....- - - - - - ,

l.Jk

L1,CII

r---+--~ ~kDDULATlON

O.OOljJF

LEVEL

P,IN 12 0 - - - - -.....- - - - - - ,
*TOKO RMC·2A7287HM
(455 kHl TRANSFORMER)

Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:

Uk

~15PFIJ9)
41

SW 1 should be "ON" only for color patterns_
Do not substitute Q2.
Variable cap may be used to trim color crystal to exact frequency.
SW 2 and 10k resistor on pins 16 and 1 are needed only if scope trigger pulse is desired.
SW 2 selects "H" or "V"trigger output pulses.
A 27k resistor in series with a 100k trimpot may be used in place of 82k resistor for variable vertical line width.
Modulation level adjusted for best patterns as viewed on TV screen.

5-97

absolute maximum ratings
Voltage at Any Pin
Operating Temperatures
Storage Temperature
Lead Temperatures (Soldering, 10 seconds)

electrical characteristics

Vss+0.3V to V ss -25V
-25°C to +75°C
-65°C to +150°C
300°C

TA within operating range, Vss

PARAMETER

CONDITIONS

=+12 to +19V, VGG =OV·
MIN

Power Supply Voltage (V ss )

MAX

TYP

12

Clock Input Frequency
OSC 1 and 2

Crystal or External
Drive (Note 1)

Clock Input Levels
Logical High
Logical Low

For External Drive.(Note 1)

Control Inputs
BCD and Trigge'r
Logical High
Logical Low

Internal Besistor
To V ss , 1M n Min.
(Note 2)

Control Output Currents
Cog and Cog
Logical High
Logical Low
Trigger and Z
Logical High
Logical High

19

UNITS
V
kHz

378

Vss-2
VGG

Vss+0.3
V GG +2

V
V

Vss-2
VGG

Vss+0.3
V GG +2

V
V

Vss - 2.0V
VGG - VGG/2 (Note 3)

2.5
0.25

mA
mA

With 10k to V GG ,
VG~ + 5.0V (Note 4)
With lk to V GG ,
VGG + 1 (Note 4)

0.5

mA

1.0

mA

Video Output
Analog Highs

With 2k to VGG (Note 5)

Power Supply Current

T A =25°C, Freq =378 kHz,
VGG = OV, Vss =+19V

2.0 to 4.0

mA
30

mA

. Note 1: The oscillator may be operated with external components to oscillate at 3'78 kHz or it may be driven by an external pulse source using
OSC 2 (Pin 13) as an input.
Note 2: These inputs are driven by switches.
Note 3: The color gate outputs are push·pull buffers.
Note4: The trigger output and Z output are open drain outputs and require a resistor to VGG for operation. Two possible resistor values are shown
with thei~ associated voltage an~ current levels.
Note 5: The video output requires a resistor to VGG for operation. This resistor must be trimmed externally to achieve the desired output levels.
The minimum voltage swing is 4.0 volts with a 10% change with temperature and from unit to unit. The percentage magnitude change with supply
voltage can approach one.

composi'te video output

2S-r·S
%

~..

.------:---"----.--VSyNC

'I~D'~D5":S

3.;-1.21'

u_ '-.

"D",~ 1--.11}--.

t

I,-J V

OLANK

V SLACK

100%

LL-VWMITE

VWH1TE

FIGURE 1. White Dot Video Information Pulse Width

FIGURE 2. Composite Video Voltaga Percentages

5-98

composite video output (con't)

MAX

250"'l
150n5

VOLANK

MAX-I

-MAX

I

VIILACK

't'"'

250ns

MAX

I- 4I

I 250n5
---r-MAX

250ns

MAX

,_-------BHll.42856J.15MAX-------_

VWHlTE

Note: line time aquab 63.492,.., with oscillator at euctly 378 kHz.

FIGURE 3. Composite Video Rise and Fall Times

FIGURE 4. Composite Video Pulse Timing, Horizontal Sync

SH

............................. ~
I - - - - - - - B v 1.396824

ms±5~~:

•

'j

Note: FJamefrequencvequals6D.114665 Hz.

FIGURE 5. Composite Video Pulse Timing, Vertical Sync

VERT~
SYNC

VIDEO OUT
HORIZONTAL SYNC

TR'GGER

OUTPUT

~

~I
°Jr~-- I~

HORZTSYNC

HORZT~

BLANKING

COG_-----.JO.2pS~nl
MAx-r~ I
2.6 to,1,...s

1-

.

TRIGGER~
OUTPUT

-..---

FIGURE 6. Color Gat. Signal Timing

FIGURE 7. Trigger Output Timing Relationship

5-99

video output patterns

I
II
15 x 21 Cross Hatch
0010

21 Vertical Lines
0001

15 Horizontal Lines

0000

.....................
.....................
.....................
.....................
.......................
,. ..... ............ .
.....................
.....................
.....................
.....................
.....................
.....
....... .. ...... .
.....................
.....................
.....................
,

GATEDRAIN80W

lBAAS

DARK

RASTER

NOl<:

Dots 15 x 21
0100

Gated Rai "bow

0011

Pon""twi"~ly is turned off" and to then disable
the outputs. In the TV, this input should be connected
to the 12V supply.
Manual "ON" Input: This input has an internal resistor
to VSS. When taken to logic "1 ", this input turns the
TV output to the "0" state. It is designed to have
typically 0.75 second debounce time to prevent maloperation.
Manual "OFF"
to VSS. When
TV output to
typically 0.75
operation.

TV "ON" Output: Figure 3
inverter output circuit used.

illustrates the CMOS

In the manual mode of operation, the manual "ON"
input sets this output to "0", the manual "OFF" input
resets this output to "1 ". The manual "ON" input
inhibits the auto "ON" output.

5'

Auto "ON" TV Output: An additional output is provided to indicate that the TV is "ON" in the automatic
mode of operation. This output goes to a logic "0"
for the duration of the auto "ON" time. Manual "ON"
switches this output back to a logic "1 ".

(J'I

BCD Outputs: Figure 4 illustrates the open drain output
circuits used, al MM53100, bl MM53105.
With the use of the external respective pull-up and pulldown resistors, these outputs are designed to be compatible with the MM5840 and MM5841 TV display

In the programmable mode, this output goes to "0"
when the programmed "ON" time coincides with the
real time (unless enable = 11. The output will then
stay at "0" for the selected period of 5, 10, 20 or 30
minutes before returning to 111/1 state. During this

circuits.

Note. Case (al for common VDD, case (bl for common
VSS when used with the MM5840.

TABLE IA. Digit Select Code
DIGIT DISPLAYED

DIGIT SELECT
LINES

Sl

S10

*

M1

M10

*

H1

H10

DX

1

0

0

1

1

0

0

1

Dy

1

1

0

0

0

0

1

1

DZ

0

0

0

0

1

1

1

1

TABLE lB. Period Select Code
VIEW PERIOD
PROGRAMMED

PERIOD SELECT
INPUTS
X
0
0
1
1

Y
5 mins
10 mins
20 mins

0
1
0
1

30 mins

VDD
VDD --~>----~~

VpOS

O/P
O/P

-f:
Vss

FIGURE 3. CMOS Output lTV
"ON", Auto "ON", Indicator)

FIGURE 4a. BCD Outputs, MM53100

5-105

(J'I

Manual "OFF" input will always reset the output to a
logic "1" state.

View Period Indicator: This output normally is a
logic "1 ". When the TV switches on at the programmed
time, this output transmits a 1 Hz waveform for the
duration of the selected view period. Hence, it can be
used to indicate that the TV is switched on for a limited
period only by means of a flashing on-screen and/or
off-screen display. The output will permanently return
to "1" at the end of the viewing period or when a valid
manual "ON" or "OFF" input signal is received during
the view period.

Input: This input has an internal resistor
taken to logic "1 ", this input turns the
the "1" state. It is designed to have
second debounce time to prevent mal-

s:
s:
w
....
o

DIP

Vss

FIGURE 4b. BCD Outputs, MM53105

s:
s:
w
....
o
(J'I

functional description

(Continued)

50/60 HI
SELECT

HEll

lav

BATTERY

IBV

18V

......HH>-i-'v
r-~fV------ TV VIDEO DIP etT (IBV)

I

15V

'v
HORIZ'------,

.....- - - 1 8 V FROM IV

F~--.--'\MI-

I - - -....-'Wlr-- HORIZ RETRACE

Oy

MM5840

VERT

'v

Oz

I-----.-'Wlr-- VE RT RETRACE

OSCINH--+-

"'='

6V

CLOCK
S/B·DIGIT
DISPLAY

: } POSITION AOJpST
MODE~

TV "ON" DIP

AUTO "ON" DIP
VIEW PERIOD OfP

CHANNEL

lIPS

FIGURE 5a. Typical System Diagram, MM53100

2.CElL
511/60 Hl
SElECT

BATTERY
lV

12V
-~HH""'12V

'v

r-~"V----- TV VIDEO DIP eeT

CULI

20
BATTERY

~H:.:O:::RI:jZ1--.--'lM.--....- - - 12V

.......W'y--HORIZ RETRACE

I---~

Ox
Oy

MM5840

VERT

Oz

I----'....-'Wlr-- VERT RETRACE

OSCINH---+

CLOCK
5/B-DIGIT
DISPLAY

: : : } POSITION ADJUST
MOOE~

TV "ON" OfP
AUTO "ON" DJP

VIEW PERIOD OfP

CHANNEL
liPS

FIGURE 5b. Typical System Diagram, MM53105

5-106

~National

Television/Radio

~ Semiconductor
MM53118AA TV Digital Tuning
General Description
The MM53118AA is a monolithic MOS integrated circuit
utilizing N-Channel silicon gate low threshold, enhancement mode and ion-implanted depletion mode devices_
This IC contains all input control, output control, and
PLL circuits required for a closed-loop digital tuning
system_

•

The MM53118AA contains complete input decoding
logic, up/down counters, a channel decoding ROM with
117 channel capacity, a complete PLL circuit including
the input oscillator, reference counter, phase comparator,
error detector, and output mode control circuits, and a
set of output buffers that drive external BCD display
drivers.

Interface to MM58146 digital clock/channel
display circuit
• Optional non-volatile memory for active channel
storage

•

Easy interface to television tuner
Wide choice of channel indicator displays
Choice of simple up/down or full keyboard channel
entry

Compatible with electronic remote control circuits

•

Standard broadcast and cable TV frequencies

•
•

PLLI AFT operation
Manual fine tune capability

•

Muting capability

•

Leading zero blanking

Functional Description
Figure 1 is a block diagram of the MM53118AA. Figure
2 is a system block diagram showing the major elements
required for a closed loop tuning system with up/down
channel selection. Figure 3 is an expansion of the basic
system to include direct access channel selection and
interface to a full 16 command remote control system.

Features
•
•

•

Block Diagram

22
KEYBOARD
A 23
AND/OR
B
REMOTE { C 24
OR
25
UP/DOWN
E
INPUTS

10 A} BANOSWITCH

TWO
4·BIT
UP/DOWN
COUNTER

11

B

OUTPUTS

18
. . - BROADCAST/CATV

SElECT

0 26

(FORMAT SELECT)

UP/DOWN
CLOCK '.

BCD
DATA

MUX

MODE CONTROL

AFT INPUT

ase IN

28
INTERI
OSC

ase OUT
EXT
REF

27

REF

EXT
REf

OIV

SelECT

21

INPUT

-=

t

13

VaOI

FIGURE 1

5-107

14
VOD2

Absolute Maximum Ratings
Maximum Voltage at Any Pin
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)

Electrical Characteristics

VSS - 0.3V to VSS + 10V
.
O°C to +70°C
-65°C to +150°C
300°C

(TA within operating range) functional voltages Vss = 0, VDDl

CONOITIONS

PARAMETER

MIN

TYP

VDD1

4.75

VDD2

7.6

5
8

= 5, VDD2 =8

MAX

UNITS

Power Supplies

VDD2
Power Supply CUrrent

Memory Only

7.6

V001 =5.25

5.25

V

8.4
8.4

V

20
2

VOO2=8.4
Unknown Signal Input

AC Coupled

Reference Signal Input

AC Coupled

Input Voltage Levels

4.75 < VDD1

V
mA
mA

0.6

2.6

Vp·p

0.6

2.6

Vp·p

VOD1-1
VSS - 0.3

VOD1
VSS + 0.9

V

VDD1

V

< 5.25

Keyboard and Stop

High Level
Low Level

V

Mode Control and

Broadcast/CATV
High Level

VDD1-1

Low Level

VSS -0.3

Input Current Levels

VSS +0,3

V

Internal Pull-ups

Keyboard IExcept Pin 261

-15

-35

IlA

-60

IlA

60

IlA

and Stop
Mode Control. Pin 26. and
Broadcast/CA TV

Source
Sink
BCD Data Outputs or

4.75 < VDD

I

< 5.25

Bandswitch Output
High Level Output Voltage
Lo~ Level Output Voltage

Phase Detector Output
High Level Output Voltage
Low Level Output Voltage

lOUT = 100llA
lOUT = -1.6 mA

2.6

lOUT = 0.2mA

4
0.5
-{l.3

Crystal Frequency

4.5

4 ±0.005%

V
V
MHz

Reference Input

Functional Description

V

V

lOUT = -{l.2 mA

AFTIN

E~ternal

V
0.4

1.5

2.0

2.5

(Continued)

The MM53118AA was designed to be used in several con·
figurations depending on the features required. The
basic tuning system is shown in Figure 2.
The timing is derived from a 4.000 MHz· crystal oscil·
lator which is divided down' to provide the keyboard
debounce timing, the clock for 4 different up/down
speeds and the reference signal to the phase comparator
which is 3.90625 kHz.
Channel entry by either up/down or di rect access
is done via the 5 input lines A, B, C, E and D (pins
22 thru 26). Input D acts as a control. If it is at the
logic "1" state (VDD - 1), the chip will ignore any

other inputs. When at logic "0" state, there are 16
possible commands via 'the other 4 input lines. The
functions performed are summarized in Table I. If the
D input is left floating, then inputs A -and B become up/
down controls at 1.5 channels per second and C and D
are up/down controls at 10 channels per second. This
is the simplest form of channel selection. The fast speed
is used to get close and the slow one to select the desired
channel. Also the slow speed allows scanning thru the
channels to see what programs are available. The up/
doWn method of channel selection mak~s possible the
use of a simple remote control, since it requires only 4
commands for channel' selection.

5·108'

MHz

Functional Description

(Continued)
12VMAX

VOD2

5V

~DrP_f

tUNING

VOLTAGE
TUNER

----+-+H-----,

,"W'R .........
SUPPLY

BANDSWITCH DATA

______

~~~

____

~~~~ ~"~~14
__

10 A
11

17

"
16

t"

STOP

REMOTE
CONTROL

RECEIVER

*Plessey Semiconductors.

FIGURE 2. Basic Tuning System With Simple Remote Control Option
12VMAX

TUNER

---+-+-HI--...,

POWEn ........
SUPPLY

10
BANDSWITCH DATA

11

17

MM53118AA

"
R1/2

"

ABC

t"

E 0

2223242516

STOP

1

,

4

5

6

,

B

,

UP

*Plessey Semiconductors.

3

ON

FIGURE 3. Tuning System With Full Keyboard And Remote Control

5-109

1-45pF":"

Functional Description

(Continued)

TABLE I. KEYBOARD INTERFACE TO MM53118AA
MM53118AA INPUTS
FUNCTION

A

B

C,

E

None

1

1

1

1

1

a

1

1

1

1

1

1

1

1

a

2

1

1

3

1

1

a
a

a

4

1

5

1

6
7

1

a
a
a
a

8

a
a
a
a
a
a
a
a

1

a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a

1

9
10

Memory Up

11

Memory Down

12

Slow Up

13

SlowDown

14

Search Up

1

1

1

1

a

a
a

1

1

1

1

1

a

1

a
a

a

1

a
a
a
a

a

1

1

1

1

a

a

1

D

The lock indicator output can be used to mute the
sound as a new channel is selected. In direct access
selection the output goes to logic "1:" after the second
entry and stays at logic "1" for approximately 92 ms.
This is sufficient time for the loop to acquire lock since
the reference to the phase comparator is approximately
4 kHz. in any of the up/down speeds the lock indicator
output stays at logic "1" for as long as any of the keys
is depressed and goes to logic "a .. approximately 92 ms
after the key is released. The operation described is
for the Pll mode. If the MM53118AA is used in the
AFT mode the operation is slightly different and is
described later.

Search Down
a a
Note. The ITT SAA 1025 can be used for remote Input to the
15

The outputs of the 2 BCD counters are brought out
to drive display drivers directly, which allows for wide
choice of display types, plus eliminating the possible
radiation caused by mUltiplexing. In the 2 system
diagrams (Figure 2 and Figure 3) the DS8669 is shown
as a 2·digit lED driver. Outputs A and B (pins 10 and
11) provide bandswitch information as shown in Table
II. This information has to be decoded and level shifted
as required for particular tuners.

MM53118AA

When direct access is used for channel. selection, a diode
matrix is required to provide the necessary input code.
Figure 4 shows the connection for entering numbers
a thru 9 plus slow up and slow down. Inputs A, B,
C and E have internal pull·up current sources, so only
one resistor is required at input D. Figure 6 shows the
use of the MM74C922 keyboard encoder as an alter·
native to the diode matrix. It shows the connection
for al'l 16 functions. In practice only the necessary
number will be used.

As shown in Figure 2 the output olthe divide·by·256
prescaler is AC coupled to the MM53118AA. This is
because the input is internally biased to accept sine wave
input of ECl p.p levels. This will minimize radiation
caused by fast rise and fall times at the output of the
diliide·by·256 at TTL levels. If a prescaler with TTL out·
puts is used it can either drive the MM53118AA directly
or a si mple RC filter can be used to slow rise and fall
times. The same input levels can be used for the exter·
nal reference input.

To select a channel via the keyboard or direct access
remote control, 2 entries are necessary. The first enters
the MSB (tens) and the second enters the lSB (units).
For channels 2 thru 9, the 0 has to be entered first. For
all channels the sequence is as follows: When the first
entry is made, the number will appear on the MSB
and a dash (-) will appear on the lSB. The second
entry will complete the sequence and then the new
channel number will be synthesized. If the second
entry is not completed the display will convert to the
original number approximately 4.5 seconds after the
first entry.

A digital phase comparator is used which provides a
pulse output proportional to the time difference be·'
tween the edges of the 2 inputs of the phase comparator.
Under ideal conditions, when the loop is in phase lock,
the output of the phase comparator will be open circuit
and the tuning voltage will be stored at the feedback
capacitor. However because of leakage and input bias
current for the operational amplifier there will always
be small pulses either 'to ground or to VDD. Those
pulses after integration will appear as noise on the tuning
voltage and change the frequency of the oscillator.
The amount of noise that can be tolerated is a function
of the gain constant of the oscillator and also of the
effect it has on the picture quality. The operational
amplifier shown has a FET input whose input bias is
in the pA range. If this type of input is necessary, it
will be determined by the. overall system requirements.

There are 2 debounce times available. One is approx·
imately 92 ms and the second is approximately 184 ms.
As shown in Table I, there are 16 possible direct access
functions. Ten are for direct access channel select
two for memory up/down at 250 channels per se'cond:
two for slow up/down at 1.5 channels per second
and 2 for search up/down at 5 channels per second. The
memory and search operation are explained later on.

5-110

An alternative solution is shown in Figure 5, where
the FET input op·amp has been replaced by a Darlington
amplifier.

Functional Description
o

1

2

(Continued)
J

4

5

6

1

SlOW

SLOW

UP

DOWN

~~b ~b ~b ~b ~b ~b ~b ~b ~b ~b ~b ~b

~--+--+--f----,+A

_

L.......t---+---++-t--+---t--+--ir--+-+---"t- -

8l
8

~-I-.....-t--+---+-4>-t-""+--II--+--t---I---::---=t- _ 8

M""IIIAA

FIGURE 4. Keyboard Interface
TABLE II. BANDSWITCH OUTPUT CODES
CABLE TV MODE
CH.NO.

L.O. FREQUENCY

3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

101
107
113
123
129
221
227
233
239
245
251
257
167
173
173
185
191
197
203
209
215
263
269
275
281
287
293
299
305
311
317
323
329
335
341

BROADCAST MODE
A

B

C,H. NO.

L.O. FREQUENCY

A

B

BAND

10
11
12
13
14

101
107
113
123
129
221
227
233
239
245
251
257
517

0
0
0
0
0
0
0
0

1
0

III

83

931

0

0

III

3

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

··

l'

0
0
0
0
0
0
0
0
0
0
0
0
0
0

5-111

 16,
Ignoring this precondition can result in an indeterminate
output frequency of the PLL or an irrecoverable latch-up
condition,

5

4
0-3

5·122

1

Not ready for new
data
Ready for new data

0 Circuit not in lock
1 PLL in lock
0 Always 0
1

Always 0
Always 0

Write
Do nothing
Transfer new data
to 14-bit register
No function
No function
Disable up-down
outputs
Enable up·down
outputs
No function

Pin Description

Connection Diagram

Digital-Analog Converter Outputs- Pins 4,5,12,13,38
and 39: 6-bit pulse width modulated outputs with open
drain output transistors.
Dual-In-Line Package

General.Purpose Outputs - Pins 6-11: 6 latched outputs
with open drain output transistors.
.

40

CHIP SELECT

General Purpose Input/Output- Pins 18, 19 and
21-25: 7-bit input/output logic. For inputs hysteresis
amplifiers are used, for outputs open drain transistors are
used.

39

NRDS

3B

NWDS

3J

O-A A

36

O-A B

35

Chip Select, NRDS, NWDS- Pins 1, 2 and 3: These pins
select the circuit and enable read or write operations. All
these signals are active low.

"'''"''
PURPOSE

OUTPUTS

(:
J

4

ADO-AD3- Pins 14-17: These are address bits that
select the internal registers for read/write operations.

5

34
33
32

1B
11

31
MM5439

11

19

O-A C

DBO-DB6- Pins 30-36: These are bidirectional data bus
pins for transferring data to and from the microprocessor.

O-A 0

ADO
ADI

Clock- Pin 37: The basic timing for the pulse width
modulators is obtained from this signal - the maximum
frequency is 4.5 MHz.

ADl
AD3

I/O (]
I/O 1

Prescaler Input- Pin 29: TTL compatible input from
Dual Modulus Counter chain driven from TV tuner local
oscillator.

Vss

30

13

lB

14

17

15

26

16

15

17

14

lB

13

19

11

10

11

Voo
O-A F

O-A E

CLOCK

066
DB5
DB<
DB3
DB>
DB!
DBO

PRESCAlER IIp
DUAL MODULUS CONTROL

OOWN
UP
I/O 6

t/o 5
[fa 4

[ID 3
[/0 2

TOP VIEW

Dual Modulus Control- Pin 28: TTL compatible output.
Controls modulus of prescaler counter chain.

Order Number MM5439N
See Package 24

Up-Down- Pins 26-27: Output of PLL phase detector.
Active low outputs interfacing to tuner via integrator.

Functional Description
CIRCUIT DESCRIPTION

General Purpose Latches

The block diagram in Figure 1 describes the requirements
of the circuit. The package is a 40-pin DIP.

These 6 latches store data .from the microprocessor. The
large number of outputs removes the need for decoders
external to the chip. All envisaged band/standard switching functions can be carried out with these bits.

HF Divider
This two stage divider takes the 4.00 MHz clock and produces two non-overlapping clocks which control the 0 to A
converters and PLL.

General Purpose 1/0
These 7 pins are used for either input or output under processor control. Figure 81 illustrates the principle. The
latched output controls an open drain output transistor.
Writing a logic 1 in this bit 1urns off the output transistor
thus permitting the use of this bit as an input. Data bus
bits DBO-DB6 are used for the I/O. See Appendix B for
description.

Potentiometers A- F
The data representing a particular potentiometer output is
stored in a 6-bit latch. This latch is parallel loaded with the
data on the I/O,bus by the load command. Table I shows
the address decoding required for each set of latches. The
outputs of the latch are compared with the outputs of a
6-bit reference counter. When the two are equal, the output
flip-flop is reset. The flip-flop is set during each zero crossing state of the reference counter. Thus a variable duty
cycle appears at the output, variable up to 63 steps. Output frequency is approximately 17 kHz. These potentiometers could be used to control brightness, volume,color
saturation, contrast, tone and fine tune. Loading 0 to
these circuits will result in the least positive output
voltage when integrated. See Figure A1 for a typical
application. See Appendix A for description.

Chip Select
The chip is selected by an active low signal from a separate peripheral select decoder.
Register Addressing
Table I shows the coding on address lines (ADO to AD3)
which selects the register to be parallel loaded.

5-123

Functional Description

(Continued)

1/0 TIMING
Read Mode

Write Mode

Figure 2 gives detailed timing in accordance with the
MICROBUS™ Specification for Class 1 Microprocessors
for the transfer of data from peripheral to microprocessor
(Table III).

Figure 3 gives detailed timing in accordance with the
MICROBUS Specification for Class 1 Microprocessors for
the transfer of data from microprocessor to peripheral
(Table IV).

All times are measured from (or to) valid logic 0 level = 0.8V
or valid logic 1 level = 2.0V.

TABLE III. TIMING: DATA FROM PERIPHERAL TO MICROPROCESSOR
Symbol

Parameter

tAcsa

Address Bus Valid to Chip
Select ON (CS = 0)

tCSR

Chip Select ON to Read Strobe

tAR

,

Conditions

Min

Data Hold Time from Trailing
Edge of Read Strobe

0

tRA

Address Bus Hold Time from
Trailing Edge of Read Strobe

50

t ACS1

Address Change to Chip
Select OFF

tHZ

Note 1

ns

ns

tRH

Address Bus Valid to Data Valid

40

250

Read Cycle Access Time from
Read Strobe to Data Bus Valid

Time from Trailing Edge of Read
Strobe until Interface Device Bus
Drivers are in TRI·STATE' Mode

Units

ns

tRo

tAD

Max

70

Note2

Address Bus Valid to Read Strobe

Typ

C L = 100 pF

ns

250

·ns
ns

500
Note 1

40
C L =100 pF

375

ns
ns

560
0

250

ns

TABLE IV. TIMING: DATA FROM MICROPROCESSOR TO PERIPHERAL
Symbol

Parameter

Min

Typ

Max

Units

40

Note 1

ns

t Asca

Address Bus Valid to Chip
Select ON (CS = 0)

tcsw

Chip Select ON to Write Strobe

310

tAw

Address Bus Valid to
Write Strobe

350

ns

tww

Write Strobe Width

430

ns

tow

Data Bus Valid before
Write Strobe

200

ns

tWD

Data Bus Hold Time Following
Write Strobe

100

ns

tWA

Address Bus Hold Time
Following Write Strobe

50

ns

tACSl

Address Change to Chip
Select OFF (CS = 1)

450

40

Note1: The maximum value of this parameter is dependent on the implementation of the chip select cIrcuit.

Nole 2:

ICSR = IAR-IACSa

TRI-STATE(! Is a registered trademark of National Semiconductor Corp.

5-124

ns

Note 1

ns

Functional Description

(Continued)

,!r-

~I
ADDRESS VALID

AD-All

I~

--'

tASC1-

--tASCO--

\

-

Er.:~

lRO_

_ICSR

NROS

tAR-

/

DATA

\

-

DATA VALID
FROM
PERIPHERAL

r\

V

tAD

FIGURE 2. Read Cycle

,

-tcsw-

NWOS

---tAW

1\

II

tww

J

tDw----

W

DATA

11\

tWA---

--

DATA VALID
FROM MICROPROCESSOR

two

"
\

FIGURE 3. Write Cycle

Frequency Too Low
REF COUNTER
DIP
PROGRAMMABLE
COUNTER
DIP

REF COUNTER
RESET

lOV

.If>...!...
512

MM54l9
...._

TUNER
...._

Frequency Too High

... OOWN

-I

.If<...!...

REF COUNTER
DIP

UP

-I

PROGRAMMABLE
COUNTER
DIP
PRESET COUNTER
RESET

Lock signal is set after 32 cycles of REF counter output without a preset.

FIGURE 4. Typical PLL Output Circuit

FIGURES

5·125

512

APPENDIX A

a

Potentiometer Voltage Generation

The flip-flop is set by circuit which detects the all O's
state of the 6-bit counter_ A 6-bit binary word is stored by
the microprocessor in the latch and its value is compared
with the state of the counter_

This integrated circuit contains 6 potentiometers of the
type shown in FigureA1_ These are used to provide waveforms of varying duty cycle which can be integrated and,
as an analog voltage, used to control volume, brightness,
color, etc_ in a TV set The circuit operation is shown in
Figure At.
'

When the comparator detects coincidence a signal resets
the flip-flop, thus the control word determines the mark
space ratio of thE! signal produced at output A. The PRF of
this waveform is 1/64 MHz with a duty cycle variable in 63
steps. This is shown in Figure A2.

DATA BUS
DO-OS

I

NWOS

I

64",

-----'r--

~-J2"'-",-1_ _

CS
AOOR

, Bit

05

Coda

04

03

02

01

DO

'1

Pulse width modulated output for analog functions
6-bit resolution/63 discrete steps

FIGURE A2. Output Voltages for
Two Different Digital Values

FIGUREA1
APPENDIX B
I/O Function

an input Thus a pin used as an input must have been
previously set, as an output, to a logic 1.

The seven pins dedicated to bidirectional operation are
identical, the logic diagram is given in Figure 81.

The signal read at the pin is a wired-OR function, As the 7
I/O bits are addressed at t,he same time by the microprocessor, it is important to note (in machine code
programming of the circuit) that by writing all bits used for
inputs, they are set to 1, Thus subsequent read operations
do not need t6 be preceded by a write.

Output is quite straightforward - data present on the
data bus Is latched by a write strobe, with the correct
address, and presented at the output However it is clear, if
the output transistor is on, then the pin cannot be used as

MICROPROCESSOR
DATA BUS

r--()--"'-

OUTPUT DRIVER

CHIP SELECT

ADDRESS

FIGURE B1. Logic of Input/Output Circuitry

5-126

~I~

~National

Televisionl Radio

~ Semiconductor

MM55108, MM55110 PLL Frequency Synthesizer
with Receive/Transmit Mode
General Description
provides a high level voltage (sources current) when the
¢VCO frequency is lower than the lock frequency, and
¢VCO provides a low level voltage (sinks current) when
the ¢VCO frequency is higher than the lock frequency.
The ¢VCO output goes to a high impedance state
(TRI-STATE®) while in lock mode, and the lock
detector output LD also goes to a high state under lock
condition.

The MM55108 and MM55110 PLL frequency synthesizers are monolithic metal gate CMOS integrated circuits
which contain phase locked loop circuits useful for
frequency synthesis applications_ The devices operate
from a single power supply and contain an oscillator
with feedback resistor, divider chain, a binary input programmable divider with control logic for the transmit
mode (7 by (N + 91)1. and the necessary phase detector
logic_ The devices may be used in double I F or single
I F systems.

Features
• Single crystal operation
• Single power supply
., Low power CMOS technology

Both the MM55108 and the MM55110 use a 10.24 MHz
quartz crystal to determine the reference frequency.
The MM55108 has a 211 divider chain which generates
a 5 kHz reference frequency. The MM55110 has a
selectable 2 10 or 211 divider chain which gives either a
10 ·kHz or 5 kHz reference frequency. The selection of
reference frequency is made by use of the FS pin.
In addition, the MM5511 0 contains an amplifier for filter
applications and an additional input to the programmable divider which allows 2 10 - 1 division of the input
frequency (fiN) for FM applications. Due to the internal
amplifier stage at input frequency input (fIN), the
MM55108 and MM55110 may take a 0.5 Vp-p signal at
fiN as the input frequency forthe programmable divider.
Inputs to the programmable divider are standard binary
signals. Selection of a channel is accomplished by
mechanical switches or by external electronic programming of the programmable divider. The. rfNCO output

Block Diagrams

•
•

Binary input channel select code
2 10 or 211 divider chain from oscillator input
(MM55110), 211 divider chain (MM55108)

• Buffered 5.12 MHz and buffered 10.24 MHz outputs
• On-chip oscillator with bias resistor
• Pull-down resistors on programmable divider inputs
• Receive/transmit input for 7 by (N+91) while in
transmit mode
•
•
•
•

Amplifier for filter applications (MM55110)
Programmable 2 9 - 1 division of fl N
Additional programmable input for 2 10 - 1 division
of fiN (MM55110)
Amplifier stage on fiN input to accept 0.5Vp-p signal

MM5510B
5.12MH~

lD24MHz

~vco

OUT

OUT

OUTPUT

8

LOCK
DETECTOR
"1" FOR
LOCKED
"0" fOR

UNLOCKED
PI PZ P3 RX P4 P5 P6 P7 P8
ITx

MM55110
FREQUENCY

SElECT
10.24 MHz "!"10kHl
OUT
"O"SkHz

CRYSTAL
OSC IN

.;>VCO
OUTPUT

3

11 LOCK

DETECTOR
"'" FOR
LOCKED
"0" FOR

fiN

UNLOCKED

Vee

PO PI P2 P3 RX P4 P5 P6 P1 P8 f'9

ITx

5-127

s:
s:
en

en
.....
o(X)

'"

s:
s:
en
en
.....

.....

o

o
,...
,...

Lt)
Lt)

:E
:E
00
o,...

Absolute Maximum Ratings
Voltage at Any Pin
Vee + 0.3V to Gnd - 0.3V
-30°C to +75°e
Operating Temperature Range
Storage Temperature
-40°C to +125°e
12V
Operating Vee
300°C
Lead Temperature (Soldering, 10 seconds)

Electrical Characteristics

Lt)
Lt)

:E
:E

T A within operating temperature range, GND = OV, unless otherwise specified

PARAMETER

CONDITIONS

TYP

4.5

Supply Voltage (Vec)
Supply Current (I ee)

MIN

MAX
10.0

UNITS
V

Freq. at Osc. ,In = 10.24 MHz at
fiN = 2.5 MHz, All Other I/O Pins
Open
Vee = 5V

10

15

mA

Vee = 10V

30

45

mA

Logical "1" Input Voltage (VIN(l))
PO-P9, FS, Rx/Tx

V

Vee-0.5

Logical "0" Input Voltage (VIN(O))
PO-P9, FS, RX/TX

0.5

V

Logical "1" Output Voltage
(VOUT(1))
Osc. Out, 10.24 MHz Out,

lOUT = -0.5 mA

V

Vee-0.5

5.12 MHz Out, LD, r/lveo,
Filter Out
Logical "0" Output Voltage
(VOUT(O))
Osc. Out, 10.24 MHz Out,

lOUT = 0.5 mA

0.5

V

nA

5.12 MHz Out, LD, r/lVeO,
Filter Out
Logical "1" Input Current (lIN(l))
Filter In (Pull-Up)

RX/TX (Pull·Up)
FS, PO-P9 (Pull-Down)

Vee = 4.5V, VIN = 4V

-300

-50

Vee = 10V, VIN = 9.5V

-500

-100

nA

Vee = 4.5V, VIN = 4V

-500

-40

J.1A

Vee= 10V, VIN =9.5V

-600

-50

J.1A

Vee = 4.5V, VIN = 4V

4

40

J.1A

Vee = 10V, VIN = 9.5V

20

200

J.1A

Logical "0" I nput Current (II N (0))
Filter In (Pull·upf

RX/TX (Pull-Up)
FS, PO-pg (Pull·Down)

Vee = 4.5V, VIN = 0.5V

--'600

-100

nA

Vee = 10V, VIN = 0.5V

-3.0

-0.5

J.1A

Vee = 4.5V, VIN = 0.5V

-800

-100

J.1A

Vee = 10V, VIN = 0.5V

-5.0

-0.8

mA
J.1A

Vee = 4.5V, VIN = 0.5V

1

10

Vce = 10V, VIN = 0.5V

2

30

Maximum Toggle Frequency at fiN

Vce = 5V

3

Vee'" l.5V

5

MHz

Input Signal at fiN

Small Signal (Ae Coupled) or

0.5

Vp-p

VIN(1)

Duty Cycle at fl N

V

Vee-0.5

VIN(O)
30

,

Maximum Osc. Frequency at Osc. In

Vee = 5V, 10.24 MHz Crystal

TRI-STATE® Leakage at r/lVCO

VOUT = Vce or Gnd

5-128

J.1A
MHz

0.5

V

70

%

10.24

MHz
1±11

!1A

s:
s:
c.n

Typical Applications

c.n

-"

~
5

BUFFERED
10.24MHz
OUT

6

s:
s:
c.n

BUFFERED
5.12MHz
OUT

c.n

-"
-"

o

,,,

OSCILLATOR DIVIDER

PROGRAMMABLE DIVIDER

ZL,

P8
1B

sw

GND

P1

P6

P5

P4

RX
IT,

P3

~

PI

111

11

12

13

14

15

16

17

vee

1

SWOPEN··RX \'"
SWClOSE-TX

CHANNEL
SELECT
SWITCH

182 < N < 270 where N = binary
number for programmable divider

FIGURE 1. MM55108 Single Crystal40·Channel Low Side Injection

TO TRANSMITTER
r - - - - - - - - - - - - - - - - - - - - - -... ~
~-..-26.965-27.405MHl
TO RECEIVER

i+-----------------+---+1STMIXER

31.660-38.100 MHl

BUFFERED
5

lQ.24MHI
OUT

BUFFERED
6

S.12MHl
OUT

,,,

OSCILLATOR DIVIDER

PROGRAMMABLE DIVIDER
29 _1

P8

1B

sw

SWOPEN

RX ,

SW CLOSE· T,

-1

GND

P7

P6

P5

P4

10

11

12

13

RX

PJ

P2

PI

14

15

16

17

IT,

Vee

.....

CHANNEL
SELECT
SWITCH

273 < N < 361 where N = binary
number for programmable divider

FIGURE 2. MM55108 Single Crystal 40·Channel High Side Injection

5-129

Truth Tables

TABLE I. Binary Inputs to Programmable Divider for MM55108

INPUTS

RX/TX
RX/TX
"1" DR "OPEN" "0" OR "CLOSED"
N
N

t>

28
P8

27
P7

P6

25
P5

24
P4

23
P3

22
P2

21
P1
0

1

92

0

0

0

0

0

0

0

2

93

0

0

0

0

0

0

0

1

4

95

0

0

0

0

0

0

1

0

Channel 1 -

182

273

0

1

0

1

1

0

1

1

Channel 40-

270

361

1

0

0

0

0

1

1

1

510

601

1

1

1

1

1

1

1

1

1 "logical "1"

o " logical "0"

TABLE II. Binary Inputs to Programmable Divider for MM55110

RX/TX
RX/TX
"1" OR "OPEN" "0" OR "CLOSED"
N
N

INPUTS
29
P9

28
PB

27
P7

26
P6

25
P5

24
P4

23
P3

22
P2

21
P1

20
PO

1

92

0

0

0

0

0

0

0

X

93

0

0

0

0

0

0

0

0

0
'0

1

94

0
0

0

3

0
0

0
0

0

2

0

1

1

Channel 1 -

182

273

0

0

1

0

1

1

0

1

1

0

Channel 40 -

270

361

0

1

0

0

0

0

1

1

1

0

1023

1114

1

1

1

1

1

1

1

1

1

1

x = don't care
1 = logical "1"
"0"

o = logical

5-130

s:
s:
CJ1
CJ1
....
o

Connection Diagrams

Dual-I n-L ine Package
PI

GNO

P2

P3

RX/TX

",CD
P6

P5

P4

P7

s:
s:
CJ1

....
.....
CJ1

o
MM5510B

ose
OUT

ose
IN

fiN

Vee

5.12

10.24

MHz

MHz

PB

LO

oveo

TOP VIEW

Order Number MM55108N
See Package 20

Dual-In-Line Package
PO

GNO

PI

P3

P2

Ne RX/TX P4

P5

P6

P7

PB
13

MM55110

Vee

fiN

ose
IN

ose
OUT

5.12 10.24

FS

MHz MHz

FIL
IN

FIL oveo
OUT

LO

P9

TOP VIEW

0'''9r Number MM55110N
See Package 22

Pin Descriptions
PO-P9

Progre:nmable Divider Inputs

fiN

Frequency Input From

OSCIN
OSC OUT
LD
q,VCO

Oscillator Amplifier Input
Oscillator Amplifier Output

10.24 MHz OUT

Lock Detector

FILTER IN
FILTER OUT

FS

veo

5.12 MHz OUT
(Mixed down)

Output of Phase Detector for Control of veo
Frequency Division Select
"1" for 2 10 Division
"0" for 211 Division

5-131

RX/TX

Buffe,ed 5.12 MHz Output IOsciliato,
Frequency.;. By 21
Buffered' 1 0.24 MHz Output (Oscillator
Frequency)
Filter Amplifier Input
Filter Amplifier Output
Receive/Transmit Input
"0" fo, Transmit Mode 1-' by IN+9111

~National

Televisionl Radio

~ Semiconductor
MM55121 Serial Data/PLL Frequency Synthesizer
General Description
The MM55121 device is a monolithic metal gate CMOS
integrated circuit which contains a phase locked loop circuit useful for frequency synthesizer applications in the
AM, FM, CB and SW frequency bands. It operates from a
single power supply and contains an oscillator with a feed·
back resistor, a 2" divider chain, a binary input programmable divider, and phase detector circuitry. Selection of a
channel is accomplished by exter(1al programming of the'
programmable divider with a 13-bit serial code derived from
a 16·bit data string fed to the SERIAL DATA I N. The serial
data format consists of a leading logical "1" synchronization bit, two control bits that are latched and made
available at OUT1 and OUT2 and a 13·bit binary input channel selection code.
The phase detector output, q,VCO, provides a high leve,1
voltage (sources current) when the VCO frequency is lower
than the lock frequency, and it provides a low level voltage
(sinks current) when the VCO frequency is higher than the

Block Diagram
vcc

GND

10.24 MHz
OUT

lock frequency.Theq,VCOoutput goes to a high impedance
(TRI-STATE® ) condition and the lock detector output LD
goes to a high state under lock conditions.

Features
•
•
•
•
•

Single crystal operation
Single power supply
Low power CMOS technology
On-chip oscillator with feedback resistor
Buffered outputs: 10.24 MHz, 320 kHz, 300 Hz and
60 Hz '

• Serial data input format consisting of a leading "1"
synchronization bit, 2 control bits available at
separate pins, and a 13-bit channel selection code
• fiN input amplifier stage to accept an AC coupled
0.8 Vp-p signal

320 kHz
OUT

~

CS-"'~------+I

INPUT
CLOCK

-..,*"--------..,...............>o-.....-+j
~

FIGURE 1

5-132

300 Hz
OUT

60 Hz
OUT

s:
s:
c.n

Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature Range
Storage Temperature Range
Operating Supply Voltage, Vee
Lead Temperature (Soldering, 10 seconds)

Electrical Characteristics

....
....

c.n

Vee + 0.3V to Gnd - 0.3V
-30'Cto +75"C
- 40'C to + 125'C
12V
300'C

I\)

Ambient temperature within the operating range and Gnd = OV, unless otherwise

specified.
Parameter

Conditions

Supply Voltage (Veel
Supply Current (Ieel

Min

Typ

6.5

Max

Units

10.0

V

Osc Frequency = 10.24 MHz
Prog. Divider Input (fiN)
Frequency=4.5 MHz
CS, Serial Data In, and
Input Clock at Gnd; All
Other Pins Open

LOGIC:

Vee =6.5V

20

30

mA

Vee=10.0V

30

45

mA

Logical "1" Input
Voltage (V IN (1))
INPUT CLOCK
SERIAL DATA IN
CS
Logical "a" Input
Voltage (VIN(O))
INPUT CLOCK
SERIAL DATA IN
CS
Logical "1" Output
Voltage (V OUT (1))
OSC OUT
10.24 MHz OUT
LD

V

0.8 Vee

0.2 Vee

V

0.8 Vee

lOUT = - 0.7 mA

V

~VCO

Logical "0" Output
Voltage (V OUT(O))
OSC OUT
10.24 MHz OUT
LD
WCO

IOUT=0.7 mA

Logical "1" Output
Voltage (V OUT(1))
320 kHz OUT
300 Hz OUT
60 Hz OUT

lOUT = - 0.5 mA

Logical "0" Output
Voltage (VOUT(O))
320 kHz OUT
300 Hz OUT
60 Hz OUT

IOUT=0.5 mA

0.2 Vee

V

0.8 Vee

0.2 Vee

5-133

V

V

..N
..II)
II)

:is
:is

Electrical Characteristics

(Continued) Ambient temperature within the operati~g range and Grid

=OV, unless

otherwise specified.
Parameter

Min

Conditions

Input Signal

4.5M

VIN(O)
Duty Cycle at fiN
Input Capacitance

OSC
IN:

Oscillator Frequency

CS:

Hz

V

0.8 Vee

VIN (1)

Units

Vp·p

0.8·

Small Signal (AC·Coupled)
or

fiN'
SERIAL
DATA IN,
INPUT
CLOCK:

Max

lOOk

Toggle Frequency

fiN:

Typ

0.2 Vee

V

60

%

10

pF

40
5
100

kll

10.24

MHz

Oscillator Input
Resistance
Including Feedback
Resistor
Input Capacitance

1

Mil

Input Resistance

1

Input Resistance
Including Feed·
back Resistor

5

INPUT
CLOCK:

Toggle Frequency

DC

Clock Rise Time
and Fall Time

0.5

+VCO:

TRI·STATE Leakage
at Vour=Vcc or Gnd

DELAYS:

Select to Data
Time Delay, t,d

pF
Mil

500

kHz
".s

-0.1

Data to Clock Time
Delay, tde

Connection· Diagram

10

+0.1

".A

0

ns

100

ns

Pin Descriptions

Dual·ln·Line Packa'ge

10.24 MHz OUT...!..

v

~OSCIN

OSCIN
OSC OUT
LD

.!!. OSC OUT

320 kHz OUT.l.

.!!. LO .

300 Hz OUT.2.

,VCO

.1!. .,;vco

GNO..!.
MM55121

10.24 MHz OUT

H~ OUT

fiN...!.

.!!.60

CS..!.

.!.!..OUT2

SERIAL DATA IN.2.

.!!. OUT 1

320 kHz OUT
300 Hz OUT
60 Hz OUT
SERIAL DATA IN
INPUT CLOCK

..!!.... VCC

INPUT CLOCK..!!.

Cs

TOP VIEW

OUT 1·2

Order Number MM55121N
See Package 19

FIGURE 2
5·134

Frequency Input from VCO (mixed
down)
Oscillator Amplifier Input
Oscillator Amplifier Output
Lock Detector Output: '''1'' for locked
condition; "0" for unlocked condition
Output of Phase Detector for VCO
Control
Buffered 1024 MHz Output (OSCillator
Frequency)
Buffered 320 kHz External Clock
Output
Buffered 300 Hz Output
Buffered 60 Hz Output
Serial Data Input
Internal Shift Register Clock
Chip Select Input
Control Outputs

Functional· Description
A block diagram of the MM55121 serial data/PLL frequency synthesizer is shown in Figure 1. The connection
diagram is shown in Figure 2.
The 5 kHz reference frequency of the phase detector is
generated by division of a 10.24 MHz oscillator frequency
in the 2" divider chain.This is compared with the output of
the programmable divider until a match iA phase is
reached to attain a lock condition. The inputs to the programmable divider are the veo frequency (mixed down)
input at fiN and the 13-bit binary channel selection code
which is the divisor of the fiN input to generate a corresponding 5 kHz signal for the channel frequency in
question.
Format of serial data generated in a controller and fed into the SERIAL DATA IN pin is shown in Figure 3. The logic
"1" synchronization bit, two control bits (that are latched

and made available at separate pins) and the 13-bit channel selection code are derived from this data string. The
chip select input, es, enables serial data transfer when it
is at ground potential.
Synchronization is maintained between the controller and
the serial PLL by use of a logical handshake and by clearing all the information out of the internal serial-to-parallel
shift register when the logical "1" signal is detected. The
operation is described as follows (Figure 3).
Sixteen·bit data is shifted into the 15-bit shift register and
"1" detector. The first bit is always a logical "1:' After this
is detected on the 15th clock pulse, data in the shift
register will be transferred (at the rising edge of the 16th
clock pulse) into the 15-bit latch. The falling edge of the
16th clock pulse disables transfer and resets all the shift
register bits.

SERIAL 0.8 VCC
DATA IN 0.2 VCC

_ 0.8 VCC
CS

INPUT
CLOCK 0.2 VCC _-/-_ _-\-

tsd;;:: Delay time between active chip select command and initial data Input.
tde

= Delay time

between initial data input and active clock.

f - - - - - - - - - S E R I A L DATA INPUT FORMAT-------...j

FIRST BIT ALWAYS
A LOGICAL "1"
SERIAL
OATA IN

~TlME

SYNC
13 BITS
BIT-+---I----+-------C-H-A-NN-E-L-S:.:E-=LE::.:C-=T-IO-N-C-O-D-E- - - - - - - - j

F R

INPUT
CLOCK

110 111 112 113 114 115 1161.1

I2 I3 I4 I5 I6 I
OATA C y C L E - - - - - - - - - - j

SYNCHRONIZATION STEPS
Clock Edga
Operation

15F

Detect Sync Bit

16R

Transfer Data into

Lalch
'6F

Disable Transfer,

Reset SIR and .. , ..
Detector

'R
2R

Clock In .. , .. (Sync Bit)
Clock In Data

FIGURE 3

5-135

Typical Application
Figure 4 shows an interconnect diagram for an MM55121
PLLlfrequency synthesizer with a COP420L acting as a
keyboard/display controller. The prescaler DS8626
enables the system to operate at a higher frequency

8-SEGMENT
DATA LINES

J~

range. The 60 Hz OUT provides a clock for timekeeping
function while the 300 Hz OUT is usually used as an alarm
tone.

to
S/

L7

I-I I-I I-I I-I
1:1 1:1 1:1 1:1

40 IGIT lEO
OISPLAY

TIMEKEEPING
CLOCK
12 60 Hz

osc

OUTPUT

,

GJ

ALARM
TONE

J
300 Hz
OUT

16

IN

CHIP

SELECT

osc

~'0.24MHZ

~:RYSTA'
15

OUT

10k

;aOPF#

-::-""4-

Vee

r?- r?- ~l

20pF

tOO

01

MM55121
SERIAL DATA/PlL
FREOUENCY
SYNTHESIZER

COP420l

02
OJ

/
/
/
/

/
/
/
/

/

/

/
/
/

/
/
/

Vee
INO
OUT 1

4

INPUT
CLOCK

OU12

4

2 320 kHz
OUT

lD.24

4

10k
INI

a

SK
OKI

MH,

IN2
7

SO
INJ

60-G2

JQ,
I/O

'0

DATA IN

~flN

10k

Vee

4 JI; 4 KEYBOARD
MATRIX

SERIAL

,.veol

--,

I
I

PRESCALER
058626

~

veo

~

fOUT

FIGURE 4. MM55121, COP420L Frequency Synthesizer/Controller

5-136

~

+-

LOW PASS
FILTER

~National

Television/Radio

~ Semiconductor
MM55122 Serial DatalPLL Frequency Synthesizer
General Description
The MM55122 is a monolithic metal gate CMOS integrated circuit which contains a phase-locked loop circuit
useful for frequency synthesizer application in CB
transceivers. The device operates from a single power
supply and contains an oscillator, a 2 10 divider chain,
a binary input programmable divider, and phase detector
circuitry. Selection of a channel is accomplished by
external programming of the programmable divider with
a 9·bit serial code derived from a 26·bitdata string fed
to the data I/O pin. The serial data format consists of a
leading logical "1" synchronization bit, three 4·bit data
to generate analog outputs (such as squelch, volume, or
A.V.C.), 4 control bits that are latched and made avail·
able at pins A-D, and a 9·bit binary input channel
select code.

lower than the lock frequency, and it provides a low
level voltage (sinks current) when the VCO frequency
is higher than lock frequency. The rtNCO output goes to
a high impedance (TRI·STATE@) condition and the
lock detector output, LD, goes to a high state under
lock conditions.

Features
• Single crystal operation
• Single power supply
Low power CMOS technology

II

.. On-chip oscillator with feedback resistor
" Buffered 5.12 MHz output

The MM55122 -may be used in single or double IF
systems. It uses a 10.24 MHz qua(tz crystal to determine
the reference frequency. It has an output pin which
provides a 5.12 MHz signal, which may be tripled for
use as a reference oscillator frequency in 2·crystal
systems.

" Serial data input format consisting of a leading "1"
synchronization bit, three 4·bit data to generate
analog outputs, 4 control bits available at separate
pins, and a 9·bit binary input channel selection code
" fiN input amplifier stage to accept 1 Vp·p signal
.. Programmable 2 g - 1 division of fl N

The phase detector output, rlNCO, provides a high level
voltage (sources current) when the VCO frequency is

"

Relative transmit/receive signal strength comparison

Block Diagram
5.12 MHz OUT

OSC IN

'0

¢VCO ABC

0

Vee

GNO

-+1--0--1
PHASE

OSCOUT--+....- -........

DETECTOR

29_1

PROGRAMMABLE DIVIDER

.---.,.--------------*-O/ADUT1
.----------'----I+-O/ADUT2

.--------+If-D/A OUTl

DATAl/a

+-..r----I

~~~~~-..r----I--------......- - - I

A.V.C.

I~~~~ -+t------I"L~~..J

FIGURE 1

5-137

C'I
N
~

:g
::aE
::aE

Absolute Maximum Ratings
Voltage at Any Pin
Vee + O.3V to Gnd - 0.3V
Operating Temperature Range
-30o e to +70o e
-40o e to +12Soe
Storage Temperature Range

Electrical Characteristics

Operating Vee
Lead Temperature (Soldering, 10 seconds)

T A within operating temperature range, GND = OV, unless otherwise specified
CONDITIONS

PARAMETER
Supply Voltage (Vcel
Supply Current (I cel

IOV
300 0 e

Frequen~y

MIN

TYP

MAX

7

8.5

10

UNITS
V

at Osc In = 10.24 MHz

and fiN = 3 MHz, All Other Pins
Open
Vcc = 7V

20

30

mA

VCC = 10V

30

45

mA

Logical "1" Input Voltage (VIN(I))

V

VCe-0.5

Data I/O
Clock Input
A.V.C. Compo Input

Logical "0" Input Voltage (VIN(O))

0.5

V

Data I/O
Clock Input
A.V.C. Compo Input

Logical "1" Output Voltage (VOUT(1))
LD

10UT=-1 mA

V

VCe- 1.O

VCO

Osc Out
5.12 MHz Out
Logical "0" Output Voltage (VOUT(O))

IOUT=l mA

1.0

V

LD
VCO

Osc Out
5.12 MHz Out
Logical "1" Output Voltage (VOUT(1))

lOUT = -0.5 mA

V

VCe-0.5

A,B,C,D
Logical "0" Output Voltage (VOUT(O))

lOUT = 0.5 mA

0.5

V

A,B,C,D
Analog Output Resistance
D/A Out 1,2,3

39

H2

VCC

V

VCC VCC
--+15 30

V

0

VCC
-3D

V

VCC = 7V, VIN = 6.5V

5

60

VCC = 10V, VIN = 9.5V

20
5

200

/lA

60

/lA

20

200

/lA

21

30

Analog Output Voltage
D/A Out 1,2,3

Full-Scale

VCC-

VCC

3D

VCC VCC
- 30
15

LSB ON
Zero-Scale
Logical "1" Input Current (1IN(l))
Input Clock (Pull·Down)
Data I/O (Pull-Down)

= 6.5V
VCC = 10V, VIN = 9.5V
VCC = 7V, VIN

Maximum Toggle Frequency at fiN
Input Signal at fiN

Small Signal (AC Coupled) or
VIN(1)

4.0

MHz

1.0

Vp·p
V

VCe-0.5

0.5

VIN(O)

5·138

/lA

V

Electrical Characteristics

T A within operating temperature range, Gnd

CONDITIONS

Duty Cycle at fiN

CJ'1

= OV, unless otherwise specified

PARAMETER

Frequency

fl N Ampl ifier Feedback

s:
s:
CJ'1

(Continued)

......

MIN

= 4 MHz

TYP

MAX

30

UNITS

70

Resist~.

%

500

Oscillator Frequency at Osc In

10.24 MHz Crystal

kll.
MHz

10.24

Osc In Feedback Resistor

Mil.

5

Maximum Toggle Frequency at Input Clock

500

TRI-STATE Leakage at qNCO

VOUT

kHz

= VCC or Gnd

1±11

f1A

Connection Diagram
Dual-In-Line Package
1
D/ADUT3DAlAl/a

u

~[)!AOUTl

OscillatOf amplifier input

OSC OUT

Oscillator amplifier output

LD

"o
MM55122 t-

ose IN...!!

~c

ose OUT.2

t2-'-B

5.12 ~~~.1

t-!lA

QVCO

Lock detector output: "1" for
locked condition; "0" for unlocked
Phase detector output for

veo

con-

trol

10
r-"WCD

9

lO-

(mixed

condition

I--'- GNO

1",-

veo

OSCIN

15

COMPARATOR --:
5

Frequency input from
down)

~D/AOUT2

r-1/ Vee

2-

CLOCK INPUT..2
A.V.C. 4
INPUT

PIN DESCRIPTION

TOP VIEW

Order Number MM55122N
See Package 20

5.12 MHz OUT

Buffered 5.12 MHz output (oscillator frequency ';-2)

Data 110
A.V.C. Comparator Input

Serial data input/output

A. B, C, D

Latched outputs derived from serial
data input

D/A OUT 1, 2, 3

Analog outputs formed in
ments of VCC/15 per LSB.
Internal shift register clock

Clock Input

Automatic volume
parator input

control

com-

incre-

FIGURE 2

Functional Description
detected. The chip operation is described as follows
(Figure 3):

A block diagram of the MM55122 Serial Data/PLL
Frequency Synthesizer is shown in Figure 1, while a
connection diagram is shown in Figure 2.

Data is shifted into the 25-bit shift register by the
clock input.

The 10kHz reference frequency of the phase detector
is generated by division of a 10.24 MHz oscillator frequency in the 2 10 divider chain. This is compared with
the output of the programmable divider until a match
in phase is reached to attain a lock condition. The
inputs to the programmable divider are the VCO frequency (mixed down) input at fiN and the 9-bit binary
channel selection code which is the divisor of the fiN
input to generate a corresponding 10kHz signal for the
channel frequency in question.

The first data bit will always be a logical "1 ". After this
"1" is d~tected by the "1" detector on the 25th clock
pulse, the data in the SIR will be transferred (at the
rising edge of the 26th clock pulse) to the 25-bit latch.
The falling edge of the 26th clock pulse disables the
transfer, enables the TRI-STATE Data I/O for output
mode, resets all of the SIR bits, and inhibits the clock
internally to the shift register.

Format of serial data generated in a controller and fed
into the Data I/O pin is shown in Figure 3. From this
data string, the logic "1" synchronization bit, three
4-bit data that are used to generate analog outputs, 4
control bits that are latched and made available at
separate pins and 9-bit. channel selection code are
derived.
Synchronization is maintained between the controlleroriented processor and the MM55122 by use of a logical
"1" handshake and by clearing all of the information
out of the shift register when the logical "1" signal is

5-139

The rising edge of the 27th clock pulse disables the
reset and will be used in the controller oriented processor to strobe the "1" data which will be present on the
Data I/O pin.
The falling edge of the 27th clock pulse removes the" 1"
from the Data I/O pin and enables the A.V.C. comparator data. This data will be stmbed into the controller by the rising edge of the 28th clock pulse. The
falling edge of the 28th clock pulse disables the A.V.C.
data output. The rising edge of the 29th clock pulse
enables th~ Data I/O as an input and the next clock
pulse clocks data into the SIR.

N
N

Functional Description

(Continued)

The A.V.C. comparator input is an additional feature
that enables the user to display relative transmit and
receive signal strengths. Actual signal strengths are
dynam ically compared with a weighted output from
the controller and made available at one of the D/A

outputs until a match is reached. Appropriate numbers
can then be displayed to indicate incoming signal
strength when in receive mode and relative power output when in transmit mode.

f - - - - - - - - - S E R I A L INPUT DATA F O R M A T - - - - - - - -

MSB

-I 1~1~~~I--__C:_::9_::BI:::TS';;___--D/A 3

D/A 2

O/A 1

CHANNEL

SELECTION CODE

SIR
CLOCK

SYNCHRONIZATION STEPS:
CLOCK EDGE
26R*
26F

OPERATION

CLOCK EDGE
28R

OPERATION
Transfer data into latch

Reset SIR, enable TRI-STATE
Data 110 for output mode,

Strobe Data 110 A.V.C. level
into controller
Remove A.V.C. data level from

28F

Data 110 line

inhibit clock

27R

Strobe Data 110 ''1'' level into

27F

controller
Enable A.V.C. comparator on

29R
1R
2R

Disable clock inhibit

Clock in "1" (sync bit)
Clock in data

Data 110
*R
F

= rising edge
=

falling edge

FIGURE 3

Typical Applications
ABC

0

VOLUME SQUELCH
CONTRllL CONTROL
VOLTAGE VOLTAGE

_

ANALOG A.V.C. VOLTAGE

+

FROM A.V.C. SECTION

COMPARATOR

FIGURE 4. Remote Microphone Serial Data System

5-140

-TIME

CONTROL
BITS
DIA
. . . . - - - - OUTPUTS

ABCO~

BV

rI

DATA
I/O

~~RC
"II

T IRx
CO.fROL

;~i2PFI

J

IDA

~

-"I

CONTROL
VOLTAGE

CA

CB

...L.

':'

O·

Q)

l>

'tJ

I

RO

;1T CONTROL CIRCUIT

'tJ

~

~

*For manual AT control function.
Replace C17 with this circuit

11112113 114116118 I,
IC·l
MM55122

('j

o
;:l.
c

10k

.
CB

I

0.01 "'

- L - el0

t

E$>

r

8A 626
R6

I=

til

A.V.C. COMPARATOR trJPUT

:;'
L2 TOKO

:::

CLOCK INPUT

BV

'0

liA~~~10 ~ ;:0

'~

:::J

R'
100

C2
TO.02211F

O·
Q)
O·

ct>

2:

::.24 MH,

OUTPUT

~l

FERRITE BEAD, B1

--'-ell
':'

':'

on

L7

C18
D.D22/.1F

O'022C~~~-L
IT~~~O"

8Tb .

J4

~rt1'

R7

lOOk

L3 TOKD

\Mv

~ Jl+-3

I

R15
470

8V

':'

':'

C31

O•o,",

':'

All resistors shown in ohms, ±5% tolerance. Capacitors in J.1F and pF, 80%-20% tolerance for J.1F, ±10% for pF.
Tuning capacitors parallel all transformers are built·in type with the coils. Details referred to Toko published specifications.

FIGURE 5, LM1862, MM55122 Single Crystal 40-Channel PLL Schematic Diagram

~~ ~ SS 11\111\1

~ ~National

~ ~ Semiconductor
:i

MM55123 Serial Data/PLL Frequency Synthesizer
General Description
The MM55123 device is a monolithic metal gate CMOS
integrated circuit which contains a phase locked loop circuit useful for frequency synthesizer applications in the
AM, FM, CB and SW frequency bands. It operates from a
single power supply and contains an oscillator with a feed·
back resistor, a 2" divider chain, a binary input programmable divider, and phase detectorcircuitry. Selection of a
channel is accomplished by external programming of the
programmable divider with a 13-bitserial code derived from
a 16·bit data string fed to the SERIAL DATA IN. The serial.
data format consists of a leading logical "1" synchroniza·
tion bit, two control bits that are latched and made
available at OUT 1 and OUT 2 and a 13-bit binary input chan·
nel selection code.
.
The phase detector output, q,VCb, provides a high level
voltage (sources current) when the VCO frequency is lower
than the lock frequency, and it provides a low level voltage
(sinks current) when the VCO frequency is higher than the
,
.

Block Diagram
vee

GNO

lock frequency.Theq,VCO output goes to a high impedance
(TRI·STATE® ) condition and the lock detector output LD
goes to a high state under lock conditions.

Features
•
•
•
•
•

Single crystal operation
Single power supply
Low power CMOS technology
On·chip oscillator with feedback resistor'
Bufiered outputs: 10.24 MHz, 320 kHz, 300 Hz and
60 Hz .
.

• Serial data input format consisting of a leading "1"
synchronization bit, 2 control bits available at
separate pins, and a 13·bit channel selection code
• fiN input amplifier stage to accept an AC coupled
0.8 Vp·p signal

J20 kHz
OUT

10.24 MHz
OUT

cs-l*-----.......
ri~~~~ ......*~---------~ ><>-"+1
FIGURE 1

5-142

JOO Hz
OUT

60 Hz
OUT

Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature Range
Storage Temperature Range
Operating Supply Voltage, V cc
Lead Temperature (Soldering, 10 seconds)

Electrical Characteristics

V cc + 0.3V to Gnd - 0.3V
- 30°Cto + 75°C
- 40°C to + 125°C
12V
300°C

Ambient temperature within the operating range and Gnd = OV, unless otherwise

specified.
Parameter

Conditions

Supply Voltage (Vcd
Supply Current (lcd

Min

Typ

6.5

Max

Units

10.0

V

Osc Frequency = 10.24 MHz
Prog. Divider Input (fiN)
Frequency = 4.5 MHz
CS, Serial Data In, and
Input Clock at Gnd; All
Other Pins Open

LOGIC:

Vce =6.5V

20

30

mA

Vee=10.0V

30

45

mA

Logical "1" Input
Voltage (V IN (1))
INPUT CLOCK
SERIAL DATA IN
CS
Logical "0" Input
Voltage (V INIO })
INPUT CLOCK
SERIAL DATA IN
CS
Logical "1" Output
Voltage (V OUTi1 })
OSC OUT
10.24 MHz OUT
LD

V

0.8 Vee

0.2 Vee

V

0.8 Vec

IOUT= -0.7 mA

V

~VCO

Logical "0" Output
Voltage (VOUTIO})
OSC OUT
10.24 MHz OUT

0.2 Vce

IOUT=0.7 mA

V

LD
~VCO

Logical "1" Output
Voltage (VOUTI1})
320 kHz OUT
300 Hz OUT
60 Hz OUT

lOUT = - 0.5 mA

Logical "0" Output
Voltage (VOUTIO})
320 kHz OUT
300 Hz OUT
60 Hz OUT

IOUT=0.5 mA

V

O.B Vcc

0.2 Vcc

5-143

V

('I)

,....

Electrical Characteristics

II)

unless otherwise specified.

N

(Continued) Ambient temperature within the operating range and Gnd

=OV,

Lt)

:E

:!E

Conditions

Parameter

Min
lOOk

Toggle Frequency

fiN:

Input Signal

Small Signal (AC·Coupled)
or

4.5M

0.8

0.2 Vee

V

70

%

10

pF

30
5

Input Capacitance

Hz

V

VIN(O)
Duty Cycle at fiN

Units

Vp-p

0.8 Vee

VIN (1)

fiN'
SERIAL
DATA IN,
INPUT
CLOCK:

Max

Typ

100

kll

10.24

MHz

Oscillator Input
Resistance
Including Feedback
Resistor
Input Capacitance

1

Mil

Input Resistance

1

INPUT
CLOCK:

Toggle Frequency

DC

Clock Rise Time
and Fall Time

0.5

~VCO:

TRI·STATE Leakage
at VOUT Vec or Gnd

Input Resistanc'e
Including Feedback Resistor
Oscillator Frequency

OSC
IN:

CS:

5

10

pF
Mil

500

kHz
I'S

-0.1

+0.1

I'A

0

ns

100

ns

=

DELAYS:

Select to Data
Time Delay, tsd
Data to Clock Time
Delay, tde

Connection Diagram

Pin Descriptions

Dual·ln-Line Package

10.24 MHz OUT...!..

u

~LD

..2.

~¢VCO

GND..!

5

~OSCIN

~ OSC OUT

320 kHz OUT..!..
300 Hz 0 UT

Frequency Input from VCO (mixed
down)
OSCIN
Oscillator Amplifier Input
OSC OUT
Oscillator Amplifier Output
LD
Lock Detector Output: "1" for locked
condition; "0" for unlocked condition
. Output of Phase Detector for VCO
~VCO
Control
10.24 MHz OUT
Buffered 10.24 MHz Output (Oscillator
Frequency)
320 kHz OUT
Buffered 320 kHz External Clock
Output
300 Hz OUT
Buffered 300 Hz Output
60 Hz OUT
Buffered 60 Hz Output
SERIAL DATA IN Serial Data Input
INPUT CLOCK
Internal Shift Register Clock
Cs
Chip Select Input
OUT 1·2
Control Outputs

MM55123

'IN-

.!!.. 60 Hz 0 UT

es...!.

..!.!... OUT2

SERIAL DATA IN..2..

.!2.. OUT 1

8
INPUT CLOCK-

1.. VCC

TOP VIEW
Order Number MM55123N
See Package 19

FIGURE 2

5-144

Functional Description
A block diagram of the MM55123 serial dataJPLL frequency synthesizer is shown in Figure 1. The connection
diagram is shown in Figure 2.
The 1 kHz reference frequency of the phase detector is
generated by division of a 10.24 MHz oscillator frequency
in the 2" divider chain.This is compared with the output of
the programmable divider until a match in phase is
reached to attain a lock condition. The inputs to the programmable divider are the veo frequency (mixed down)
input at fiN and the 13·bit binary channel selection code
which is the divisor of the fiN input to generate a corresponding 1 kHz signal for the channel frequency in
question.
Format of serial data generated in a controller and fed in·
to the SERIAL DATA IN pin is shown in Figure 3. The logic
"1" synchronization bit, two control bits (that are latched

and made available at separate pins)'and the 13-bit channel selection code are derived from this data string. The
chip select input, es, enables serial data transfer when it
is at ground potential.
Synchronization is maintained between the controller and
the serial PLL by use of a logical handshake and by clearing all the information out of the internal serial-to-parallel
shift register when the logical "1" signal is detected. The
operation is described as follows (Figure 3).
Sixteen-bit data is shifted into the 15·bit shift register and
"1" detector. The first bit is always a logical "1!' After this
is detected on the 15th clock pulse, data in the shift
register will be transferred (at the rising edge of the 16th
clock pulse) into the 15-bit latCh. The falling edge of the
16th clock pulse disables transfer and resets all the shift
register bits.

SERIAL O.B VCC
DATA IN 0.2 VCC

_ O.B VCC
CS

INPUT
CLOCK

0.2 Vcc _-/-_ _; -

tsd:;;; Delay time between active chip select command and initial data input.
tde

= Delay time between initial data input and active clock.

1 - - - - - - - - - SERIAL DATA INPUT FDRMAT'-------~.~I

FIRST BIT ALWAYS
A LOGICAL "I"

LSB
SERIAL
DATA IN
SYNC

13 BITS

BIT:-!-+-~~*~-----CH-A-N-N-E-L-SE-L-EC-T-IO-N-C-O-O-E-------1

F R
INPUT
CLOCK
110 111 112 113 114 115 1161.1

I 2 I· 3 I 4 I 5 I 6 I
DATA C Y C L E - - - - - - - - - -

SYNCHRONIZATION STEPS
Clock Edge
Operation
15F
16R

Detect Sync Bit
Transfer Data into

Latch
16F

Disable Transfer,
Reset SIR and ",..
Detector

lR
2R

Clock In "I" (Sync Bit)
Clock In Data

FIGURE 3

5-145

Typical Application
Figure 4 shows an Interconnect diagram for an MM55123
PLL/frequency synthesizer with a COP420L acting as a
keyboardidlsplay controller. The prescaler OS8626
enables the system to operate at a higher frequency

range. The 60 HzQUT provides a clock for timekeeping
function whi Ie the 300 Hz OUT Is usually used as an alarm

.

~~

B-SEGMENT
. -_ _;;;DA:.;;TA~L:.;;IN;:E;.S_ _-fLO

.-~------fL7

4-DrGtTleD
DISPLAY

300Hz
OUT

TIMEKEEPING
SI

CLOCK

12 DO Hz
OUTPUT

-1---.,

O~~ .-:1;.6

~ ~~~~CT

031-_....""""""6

B

VCC

MM55123

SERIAL DATAlPlL

CDP42DL

FREOUENCY
SYNTHESIZER

VCC

oUTl
SK

8

INPUT
ctOCK

2320kHz
OUT

CKI
SO

10

7

SERIAL
DATA IN

4 x 4 KEYBOARD
MATRIX
J GENERAL

I/O

VCO

.

'OUT

FIGURE 4. MM55123,COP420L Frequency Synthesizer/Controller

5-146

LOW PASS
FILTER

~National

Televisionl Radio

~ Semiconductor
MM55124, MM55126 PLL frequency synthesizer

general description
The MM55124 and MM55126 are phase locked loop
circuits for frequency synthesizer applications fabricated
with low threshold, metal gate CMOS technology. The
MM55124 and MM55126 operate from a single power
supply over a voltage range of 4.5-10V. An input
amplifier has been included on the FIN input, thereby
allowing operation of the programmable divider with as
little as a 0.5V peak-to-peak input signal. A feedback
resistor is also included on both circuits to bias the
reference oscillator.

The rfJVCO output provides a high level voltage (sources
current) when the VCO frequency is lower than the lock
frequency, and a low level voltage (sinks current) when
the VCO frequency is higher than the lock frequency.
The rfJVCO output goes to a high impedance state (TR 1STATE®) and the lock detector output LD goes to a
high state while the device is in lock mode.

The MM55124 and MM55126 may be used in double IF
or single IF systems. The devices use a 10.24 MHz or
5.12 MHz quartz crystal to determine the reference
frequency. The MM55126 has a buffered 5.12 MHz
output signal which may be tripled to generate a reference frequency in 1 or 2 crystal systems. Also, the
MM55126 provides an additional input to the programmable divider which allows 29 -1 division of the input
frequency (FIN!. The inputs to the programmable
divider are standard binary signals. Selection of a channel is accomplished by mechanical switches or by
external electronic programming of the programmable
divider.

features
•
•
•
•
•
•
•
•
•

Input amplifier on FIN
Single power supply
4.5-10V voltage operation
Low power CMOS technology
Binary input channel select code
5 kHz or 10kHz output from oscillator divide
Buffered 5.12 MHz output (MM55126 only)
On·chip oscillator with bias resistor
Pull·down resistors on programmable divider inputs

block diagrams

.,.
"'

FflEOSELECT

FREQSElECT

512mb

,

OSCOUT

\lVCOOUTPUT

6

''I'
"0"

-10~Hl

,

¢VCOOlJTPUT

LOCK
10HECT(lR
'1'FORlQCKED
'O'FORUNlOCKED

Vee

~NO

PO

PI

P2

Pl

P4

PS

P6

a

lOCK
OETECTOR
"1""fORLOCKEO

"O"FORUllilOCKEO

VccGIIIO

PI

PO

PI

P2

MM55124

MM55126

pin descriptions

truth table
Truth table for binary inputs to programmable divider.

PO-P8

Programmable divider inputs

FIN

Frequency input from

veo

(mixed

down)

OSCIN

Oscillator amplifier input terminal

OSC OUT

Oscillator amplifier output terminal
Lock detector
Output of phase detector for control

LD
100,..s)
is allowed for the bi·directional LSD bus to switch to the
"slave" or input mode before the input data on the bus is
entered. The input data is entered into the "Buffer" or the
"Units Counter". After completion of the entry, indepen·
dent of the state of the "MIS" line, the LSD bi·directional
bus is switched to the output state. No additional entries
are possible until the "MIS line reverts back to the "mas·
ter" state and a new, "slave" state is sensed. The
"slave" input is defined as the simultaneous closure to
ground (within one debounce time) of both the "UP" and
"DOWN" inputs.

The above elements in combination comprise a TV fre·
quency synthesizer phase·locked loop, capable of pre·
cisely tuning the tuner local oscillator to the required
frequency for each olthe 82 TV channels. Additionally,
an interface to conventional AFT and control logic in
the MM58142 provide precise tuning of nonstandard·
frequency VHF band channels whose picture carrier fre·
quencies are within ±2 MHz of nominal, and UHF band
channels whose picture carrier frequencies are within
± 1 MHz of nominal. The method of operation, synthesis
only or a combination of synthesis and AFT, is controlled
by an external mode select switch.

SKIP (Input)
A logic "1" on the "Skip" input, during the time "Change"
is low, causes the channel number to increment or dec·
rement ,to the next legal channel depending upon the
state of UP/DOWN, in conjunction with a "Skip Memory",
it is thereby possible to limit the set of channels accessi·
ble via the "UP/DOWN" command to those programmed
into the "Skip Memory". The "Skip" input can also be
used with a "Last Channel Memory" to load, by serial
interrogration, the "Last Channel Memory" contents. In
addition, the "Skip" input can be used to start the long
timer (Td. During the time "Change" is high, a high on the
"Skip" input starts the long timer (Td without executing
a "Skip" operation.

The synthesizer LSI also provides interfacing, control,
and timing circuits for remote or local customer control
and optional channel number display.
The control and display options include:
1. Up or Down Channel stepping
2. Up or Down Channel skipping (non·volatile skip memo
ory required)
3. Last channel recovery after power shutdown (non·
volatile last channel memory required)
4. Direct keyboard address of channel number
5. Compatibilty with an on·screen display generator IC,
the MM58146

In order to prevent false channel changes from occurring
due to kine·arc or system noise, the "Skip" input is in·
hibited approximately 98ms after the last "UP/DOWN"
operation of the interface·control logiC.

General Operation

CHANGE (Output)
UP/DOWN (Input)

A logic "1" on the "Change" output line indicates that
the 8·line BCD output is in the process of changing and
shall not be considered valid. The change Signal will go
high at least 2,..s prior to any change on the output bus
and will stay high for at least 40,..s'after the output bus
has been changed.

The up/down input commands, after being debounced,
produce an immediate increase or decrease in channel
number to the next legal channel number. Then after a
pause of approximately 650ms, the channel number
changes at a rate of approximately 10 counts per second.
Once the switch is closed, momentary opening (less than
16ms) or contact noise due to switch aging or to pres·
sure variation on the switch, is ignored.

During the "Half Entry" mode, "Change" remains high
until either the "Half Entry" mode has been aborted or a
second digit entry has been made. "Change" will stay
high for at least 40,..s after either the second digit entry
or abort operation has been completed and the output
bus data is valid. After a momentary power drop ou't
("Standby" mode), "Char,ge" will remain high for approxi.
mately 5.25 seconds, or until after the completion of the
next entry.

With a "Skip Memory" present,the "UP/DOWN" com·
mand produces a "skip" to the next programmed channel
as quickly as is practical and then pauses for 655 ms,
I.e., stepping between programmed channels at approxi·
mately 1.5 changes per second.

DISPLAY (Output/Input)
"PUP" (Bus)

The output consists of two sets of four lines, one set of ,
which determines the tens digit (MSD); the other set
determines the units digit (LSD). The output is a standard
positive logic BCD code with output drivers capable of
providing sufficient isolation to prevent any signal pick·
up on the output lines from changing the output state of
the binary counters.

The "Power is Up" (PUP) signal is internally generated on
the chip and has the capability of being bussed with the
"PUP" lines of other integrated circuits used in the tun·
ing system. A high on the "PUP" line indicates that the
logic power is within the normal operating range and that
the chip logic is capable of normal speed operations.

MASTER/SLAVE (Input)

Direct Keyboard Eritry

The four lines used for the units BCD (LSD) output are
bi·directional, under control of the MIS Input, and capable

In order to tune the TV receiver, two consecutive key·
board entries are required within a 5.25 second period.

5·165

The first entry is·loaded into the "Buffer" and puts.;the
system into a uHalf Entry" state. In the "Half Entry"
state, the output bus MSD is connected to the "Buffer"
and the LSD is forced to a code which will cause the,display to show a "dash". During the time the sysiem is in
the "Half Entry'! state, the "Change" output line ·is held
high since the bus data is no longer valid. The "Change"
line will remairi high until after either the second keyboard entry is made or the "Half Entry" state is aborted
due to a time out of UP/DOWN entry. Only after the second keyboard entry is made is the synthesizer logic
instructed to tune to a new channel:

completion of the next entry. During the time "Disconnect" is high the on-chip load on the 10V supply is reduced to a minimum.

1'10 high
P10 low
P5

Min_

Max_

Units

4.0
1.8
1.2

9.8

Volts

5.8
4.0

Volts
Volts

P10 high :l> P10 low + 1.0V

If the second entry is an UP/DOWN command rather than
a digit, the "Half Entry" state will be aborted and t'he
display will revert back to the channel number co.rresponding to the channel being watched for 655ms and
then if the UPIDOWN input is still valid, will continue
with the normal, UP/DOWN. operation.

Standard Synthesizer Blocks
Figure 1 is a simplified block diagram of the tuner control
portion of th~ synthesizer IC. The signal input to the
synthesizer is fLO + K, i.e., the appropriate VHF or UHF
local oscillator signal having been divided in frequency
by a factor K by the high-speed prescaler. The blocks in
the IC which comprise a standard synthesizer are:

If one of the direct keyboard entries resulting from the
simultaneous closure of i'wo or more keys is ncin-BCD or
Hex (A-F);the system will reject that entry and revert the
display back to the channel number corresponding to
the channel being watched. If the system isin the "Half
Entry" state at the time of the Hex entry, the logic will
inhibit the normal data transfer 'clock to the "Tens" and
"Units" counter. This will result in the reversion back to
ttie old channel number. Ifthe system is not in the'''Half
Entry" state at the time of the Hex entry, a normal 100id
operation is executed with the exception that the input
clock to the 5.25 second timer (TIM5) is switched from
the normal 488 Hz clock to a high speed 31 kHz clock.
This will result in the, execution of a "Time Out Abort" in
82 ms. At the end of the 82 ms the display will revert
back to the original channel number.

+ N Counter:

A programmable counter which divides
the input signal by a factor N where
N is an integer. number equal to the
local oscillator frequency, in MHz, of
the requested channel.

Channel # to
N Decoder

'Its input is the B-bit, BCD channel. number, supplied by the input portion of
the IC, and its output is the factor N.

+4/+1 Counter A bi-modulus counter with 4 as the
.
modulus for VHF band channels and
1 the modulus for UHF band channels.

Standby Power Operation
After initialturh-oh, any momentary power failure will
result in the logic establishing a power "Standby" state
with the "Biriary" UP/DOWN counter inputs disconnected
or isolated from the 5V logic and powered by the separate 10V supply. Normal power-up will occur if 'the 10V
supply ever drops below the level. With the supply below
the "P10" :leveL it must be assumed that .the counter
contents are. no ·Ionger valid and therefore upon the
return of power ttle normal "PUP" or initialization process will be execu~ed. If during the momentary power
failure the 10V supply remains above the "P10" level,
butthe5V supply drops below the "P5" level, the system
will immediately generate a "Standby" state for the 5V
logic and "Disconnect" state for the Binary UPIDOWN
counter. "Disconnect" is generated whenever the 5V
power drops below the P5 level.
"StandbY" will go high at start of "Disconnect" and will
remain high for approx,imately 262 ms after "Disco.nne,ct" goes low. During "Standby" all 110 functions in
process will be aborted and no new 110 function wiil be
initiated. During "Disconnect" the Binary UPIDOWN
counter's inputs will be inhibited and no counter state
chan'ges will be allowed. Independent of the Binary
Counter's input state, the transitions of "Disconn,ect"
will not alter the counter state. hi addition, the output
"Change" will go high during "Standby" and will remain
high for approximately 5.25 seconds, or until after the

5-166

Reference
Oscillator
Reference
Divider

Connected through IC pins'to a 4 MHz
crystal fee,jback network
An 11-stage binary ripple counter,
used to provide timing signals, and, in
particular, 10 stages are used to
provide the 3.90625 kHz phase-jock
reference. .

Phase
Comparator

An edge-triggered phase comparator.
In the synthesis mode, the output is
tri-state. When the signals are phaselocked, with O· phase error, the output
is ciff. The polarity of the output pulses
is determined by the polarity of phase·
error, and the pulse width determined
by the magnitude of the phase error.
In the AFT mode, the phase
comparator output is not' used.

Band Decoder

Provides two band select logic outputs
used by the operational amplifier band
switch IC to control tuner power for
low VHF, high VHF, and 'UHF bands.

Han'gup
Corrector

Automatically senses and corrects for
the situation(s) i'n which the varactor
tuning voltage, is at one 6f the power
supply stops and the syn,thesizer
phase detector outp'ut pulse polarity
is such as to hold the tuning voltage'
at the power supply stop.

Mute Control

The Reference Oscillator is an inverter with both input
and output connected through IC pins to a crystal feedback network. The oscillator frequency is to be
4.000000 MHz ± 0.00537.

Provides a short to ground for the
sound signal when a channel change
is requested. The short is removed
once the tuning voltage has stabilized
as indicated by the LOCK detector.
Muting remains effective when an
illegal channel is being tuned.

The Reference Divider contains a 13 stage binary ripple
counter. The input to the divider chain is the signal 4 MHz
from the Reference Oscillator. The output of the 13th
stage, the signal 500 Hz, is fed to the Step Timing block
in the input portion of the synthesizer IC. 500 Hz is the
input clock to a timing chain which produces a number
of time constants.

The remaining blocks are associated with the second
tuner control method of operation, in which both syn·
thesis and AFT are used to provide a precise tuning capa·
bility for nonstandard VHF TV signal frequencies within
±2 MHz of nominal and UHF frequencies within ±1 MHz
of nominal:
Lock Detector

Band Select Outputs
Logie Truth Table

When in the synthesis mode, provides
an indication that the frequency difference between the reference and
the counted-down local oscillator
signals is arbitrarily small. This indio
cation is a prerequisite for switching
to the AFT mode and for disabling the
muting function.

Offset Detector When in the AFT mode, provides an
indication whenever the local oscillator
has deviated by more than 1.25 MHz
from the frequency synthesized just
prior to entering the AFT mode.
Step Control
Controls which of three frequencies
are to be synthesized for each VHF
channel. The frequencies, in the order
used, are 0, or nominal, + 1 MHz, and
-1 MHz. For UHF channels only the 0,
or nominal frequency is synthesized.
Mode Control

Provides synchronized switching from
synthesis to AFT mode and vice versa.
It also generates various sampling,
switching, and reset signals for the
system.

5-167

A

B

Output

0
0
1
1

0
1
0
1

No Band
Low VHF
High VHF
UHF

Television/Radio

~National

~. Semiconductor

MM58146 TV Clock and Channel Display
General Description

Features

The MM58146TV Clock and Channel Display Circuit is a
monolithic NMOS integrated circuit which generates a
display of time and channel number on a television
screen.

• 12 hour operation

The chip contains a time of day clock and all the logic required to display time and a 2 digit channel number from
an external source, such as the MM53118 or MM58142 TV
Digital Tuning Chips.

• Interfaces to video system directly on many TVs

The horizontal, vertical, and 60 Hz inputs and display
outputs are designed to directly interface to the video
system of many TV' sets.

• Leading zero blanking on hours display
•

Black border around white character

• Clock and channel display or channel only display
• Two digit display need not be channel number.
Channel number is entered as BCD.

The time and channel number are displayed on the same
line near the bottom of the screen.

Block Diagram
EN

R~~~

___O_SC_.__

~ -'~~
__

______

~

BLK
WHT

HOR
(HORIZONTAL
PULSE)

_Voo
-

VSBY

_Vss'

MSO
LSO
CHANNEL INPUTS
A7-AO

Connection Diagram
VOD

22

VERT

60 Hz

21

WHT

EN2

20

BLK

EN

19

VSBY

1B

HDR
MSET

MM5B146

CHANNEL
LSD

r

17

RC

16

A2
A1

10

13

"}

AO

11

12

VSS

HSET

15
14

A6
A5

A4

Top View
Order Number MM58146N
See Package 21

5-168

CHANNEL
MSD

Absolute Maximum Ratings
Supply Voltage
Voltage at Any Pin
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)

Electrical Characteristics
Parameter
Voo
VSBY
Power Supply Current, 100
Power Supply Current, ISBY
Input Logic Levels
BCD Inputs, EN, HSET, MSET
Logic Low
Logic High
Internal Pullup (HSET and
MSET only)
60Hz Input
Logic Low
Logic High
Logic Low
Logic High
Horizontal, Vertical Input
Logic Low
Logic High
Logic Low
Logic High

12 Volts
12Volts
O·C to 70·C
-55·Cto +150·C
300·C

Voo =4.5 to 6.0V, VSBY= 10 to 12V, Vss=OV, TA=O to 70·C
Conditions

Min.

Max.

Units

4.5
10

6.0
12
45
7.0
1.4

V
V
rnA
rnA
rnA

-0.3
2.4

0.6
12

V
V

30

150

,..A

Without 100k Series
Input Resistor
With 100k Series
Input Resistor

-0.3
4.0
-5.5
4.0

0.6
12
0.6
12

V
V
V
V

Without 100k Series
Input Resistor
With 100k Series
Input Resistor

-0.3
4.0
-70
4.0

0.4
12
0.4
30

V
V
V
V

Vss=OV
Vss=OV
Vo o =6.0V
Voo = 4.5 to 6.0V
Voo=OV

Typ.

Output Logic Levels
BLK Output
Logic Low
Logic High
Rise and Fall Time·

I = 0.5 rnA, Sink
I = 2.5 rnA, Source
CL =30pF

6

1.0
11
70

V
V
ns

WHT Output
Logic Low
Logic High
Rise and Fall time

1=1.5mA, Sink.
I = 0.5 rnA, Source
CL =30pF

6

0.4
12
70

V
V
ns
MHz

Oscillator Frequency
External RC (Note 1)
R
C
C

4.5

5.0
2.5
33
20

f=5.25MHz
f=5.7MHz

Power Supply Rise Time

t.O

Nole 1: The external resistor and capacitor must be located as close as possible to pins 17 and lB.

5-169

5.7

k
pF
pF
ms

Functional Description
The display is generated' by means of an on-Chip RC
oscillator that operates nominally at 5 MHz. This 5 MHz
oscillator is divided down to form a 2.5MHz reference
clock. Each character frame of the display occupies a
rectangle 20 lines high and 8 reference clock periods
wide. The characters are composed either from the segments of a figure "8" or from a centered "1". The main
character output is' the WHT output. The BLK output Is
used to provide a border around the main character which
provides contrast on a.normally white picture. The top
line of the characters begins on the 192th horizontal line
after the vertical retrace pulse. The time information is
displayed on the left side. of the screen and the channel
number is displayed on the right side of the screen.

. ' plied and remain low after power (Voo) Is applied, the
time of day information will be blanked from the display
.and only the channel number will be.displayed.
A typical clock setting sequence is as follows:
1. Force HSET low until. the hours display equals the
desired value. Then raise HSET to a high.
2. Force MSET low until the minutes display equals the
desired value.
3. To synchronize to another time source, force both
MSET and HSET. low simultaneously. This will hold
the time information constant. WhElO the clock and
time source are equal, raise both MSET and HSET,
and the clock will start keeping time.

With power up of VSBY the real time clock is set to "00"
and the display is enabled. It will display a "- -:- -" for
22 to 30 seconds. It is cleared when one of the time set .
inputs is brought low as described under HSET and MSET
inputs.
.

.

Enable 2 (EN2): This is a mode control pin that must be
connected to Vss.
Channel Number Inputs (A7-AO): These inputs are the
external channel In puis. The most significant digits are
A7-A4 , with A7 being the most significant bit (MSB). The
least significant digits are Aa-Ao, with Aa being the most
significant bit. See the Truth Table for display font
coding.
.

.

If the Voo and VSBY supplies are on and HOR becomes a
logic "1" for at least 7.5 seconds, the display will then
be enabled for 22 to 30 seconds when HOR again becomes a logic "0".
It Voo goes down and up while VSBY remains up, the
seconds count is set to "30" and the minutes and hours
remain unchanged. The' clock remains' unchanged be·'
cause it receives power from VSBY ' Also, under these
power up conditions, a lock is established on display
enable such that EN must go low and then high again to'
cause the display to appear.

Output SignalS
White Output (WHn: This is the main character output.
Black Output (BLK): This output is used to provide a
border around the main character output (WHn.
Input/Output Signals

The following describes the functions of all the input
and output pins. In the following description, a low represents a logic "0" and a high represents a logic "1".

Oscillator Input and Output (RC, R): These pins connect
the external resistor and capacitor to the oscillator to
generate the main timing for the chip. See the Appllcation Section for connection details:

Input Signals
Vertical Pulse (VERn: This signal resets the line counter
and synchronizes the display to the vertical TV display.
Horizontal Pulse (HOR): This signal increments the line
counter and synchronizes the display to the horizontal
TV display.

Display Font Coding
Inputs
Aa A2 A1 Ao
or
A7 As As ~

60 Hz: This input provides the 60 Hz time base for the
real time clock. This Input is designed to accomodate a
sine wave input.

0
0
0
0
0
0
0
0

Enable (EN): This input, when high, will initiate the display. The display will stay on as long as EN is a logic
"1". The display will remain on from 3 to 4 seconds after
EN goes to a logic "0".
Hours Set and Minutes Set (Am and~: These two
inputs are used to set the clock to the desired time. When
HSET is low, the hours counter will advance at a 2 Hz
rate. When MSJ:f is low, the minutes counter will advance at a 2 Hz rate. Setting one counter does not affect
the other counter. When either HSET or MSET is low,
the seconds counter is forcibly reset to "00". Also,
when I'iii'SE'f and RSET are both low, the time remains
constant. This is llsed to synchronize the clock to the
master time source. Either or both input being low will
cause the display to be active for the duration of the low
signal, plus 3 to 4 seconds after the input goes high. If
MSET and HSET are both low when power (Voo) is ap-

0
0
0
0
1

0
0
0
0

5-170

WHT
Output

0
1
0
1
0
1
0

D

0
1
0
1
0' 0
0 1
0

B
9

0
0
1
1
0
0
1
0
0

I

2
3
y

5

Ei

1
(Colon)
(Lower halt of Colon)

p
0

(Upper halt of 8)
(Dash)
Blank

Display Format and Timing

~

:::;

o
o

10

I]
I]

20

u

u

'WHT OUTPUT-U

u

'SHOWN FOR LINES 5-8 AND 13-16

Display Format and Timing

Applications
Voo

VSBY

13

6

RC

!---16.7m.-!

11:=]11

-

EN
18

63.5~,

~=±
bON

MM53118AA

.JLJL
·LflJ
--1---1

---L-

lOOk':" 22

*OfF

ADJUSTMENT
fOR CENTERING
DISPLAY

17

VERT

lOOk
HDR

8LK

60Hz

WHT

lOOk

20

F---.
21

TO VIDEO
} NETWORK

'SEE ELECTRICAL SPECIFICATION FOR LIMITS ON THESE INPUTS

TV Channel and Time Display Interlacing witli MM53118AA

5-171

Applications

(cont'd)

VSBY

1
Ao
10

Al
A3

13

A4
MM58142

14

A5

As
A7
CHANGE

~)
Al'
A2

Az

8
13

19 VSBY

LSD

.) .,'".
As

15 A5
A6
16
A7

7

voo

MSD

R 18

EN

ADJUSTMENT
FOR CENTERING
DISPLAY

EN2
VS.

1_16.7ms_1

.1L-J1.
·LflJ
-+_--1
63.5",

11~11

lOOk":"

22

RC 17

~33PF

VERT

lOOk
HOR

8lK t-=2:.:.0_ _ _~}
.

lOOk

WHT

t-=2;.:.1 _ _ _~

60Hz

'SEE ELECTRICAL SPECIFICATION FOR LIMITS ON THESE INPUTS

TV Channel and Time Display Interfacing with MM58142

5-172

TO VIDEO
NETWORK

Televisioni Radio

~National

~ Semiconductor

PRELIMINARY

MM58313 Varactor Tuner Display Circuit
General Description

Features

The TV varactor display circuit is a monOlithic metal gate
CMOS integrated circuit designed to provide an on-screen
tuning bar graph scale for varactor tuned TV sets.

•
•
•
•
•
•

The tuning voltage is indicated by a vertical bar 36 lines
deep and approximately 6 mm wide which traverses the
screen in a linear relationship to the tuning voltage. An
option input is provided so that the tuning voltage can be
indicated by a horizontal line of variable length.
Three bands are provided, with an option to allow for cable
transmission. Characters relating to the appropriate band
selected are displayed on screen (Table I), the characters
being formed by a 6 x 7 dot matrix.

Electronic tuning scale for 3 bands
Linear tuning indication
Digital channel number display
Pin option for cable TV systems (PAL only)
Pin option for PAL and NTSC systems
Pin option for finger or horizontal bar tuning voltage
indication
• 12V operation compatible with digital tuning systems
• CMOS technology
• On-chip oscillator, frequency governed by external
timing components

Block Diagram
TIMING
COMPONENTS
~

2

3

VERT
SYNC
PULSE

HORIZ
SYNC PULSE

16

4

15

PAL/NTSC
OPTION
13

II

UHF
7
CABLE
OPTION

VARACTOR
INPUT

RESET
RAMP

.

EXTERNAL R & C

CONSTANT
CURRENT

RAMPGEN

RESET
VERTTIME
SLOT COUNTER

BAND
DECODER

VERT SLOT
DECODER

HORIZSLOT
DECODER

Output A < Output B
HORIZ
ENABLE

VERTICAL ENABLE

GATING
CIRCUITRY

CHARACTER
.ROM

~VDD
~VSS
·CLOCK

L-_ _ _ _ _....,f--=L;::IN:;;,E_+I

SH,F/~~,:,STER 1-----------1~

14 HORIZ!VERT

BAR OPTION

OUTPUT G·y

OUTPUT Y

5-173

Absolute Maximum Ratings
Supply Voltage (Voo-Vss)
Voltage at Any Pi n
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)

-0.3Vto +18V
Vss -0.3V to V oo + 0.3V
0·Ct070·C
-55·Cto +150·C
+300·C

Electrical Characteristics
Voo =12V, Vss= OV, TA = o·c to 70·C; Clock Frequency 3.3 MHz, unless otherwise noted.
Parameter

Conditions

Power Supply Voltage "00.

Vss=O

Min·

Typ

Max

Units

11.5

12

18

V

6

14

rnA

Vss
Voo

Vss +3.5
Voo+0.3

V
V

11

V

Power Supply Current
Input Voltage Levels
Logic 0
Logic 1

Voo-0.3
Voo-4.0

Analog Input

0

Input Frequency
Horizontal
Vertical
Horizontal
Vertical

15.625
50
15.75
60

Output Voltage Levels
Logic.O
Logic 1

lour= 110 I'A 1

Output Drive
Logic 0
Logic 1

Vss+2V
Voo-2V

Vss
V oo -50 mV

kHz
Hz (PAL)
kHz
Hz (NTSC)
V
V

Vss+50 mV
Voo

Vss
Voo

-1
1

mA
mA

External RC
CTiming
R1 Timing

47
1.2

pF
kG

R2 Timing
CRamp
R Ramp

2.0
33
'475

kG
pF
kO

1

I'A

Input Leakage (Except Pins 2,3,13)

V1N =12V

Input Capacitance

pF

5

Input Current (Pin 13)

80

V1N=OV.

I'A

TABLE I. BAND SELECT CHARACTER DISPLAY·
PAL System

NTSC Option

Display
Band I Band III UHF Transmission Option LHS RHS
0
1
1
0
1
1

1
0
1
1
0
1

1
1
0
1
1
O.

0
0
0
1
1
1

2
5
21
2
S2
'21

4
12
69
S1
20
69

Display
Band I Band 11/ UHF TransmissionOption LHS RHS
0
1
1

1
0
1

1
1
0

0
'0
0

2
5
14

4
13
83

Note: For NTSC system only•.channel display is equivalent for both
broadcast and cable systems.

5·174

Connection Diagram

Dual·ln·Line Package

~ VOO

MM5840 CLOCK ENABLE...!.
TIMING RESISTOR..!.

r!-!-VARACTOR CLOCK ENA8LE

TIMING CAPACITOR..2.

r!-!- OUTPUT Y
r!Z-OUTPUT G·Y

LIMIT RESISTOR..!

BAND I SELECT

2

MM58313

r!-!- HORIZ SYNC PULSE

~VERT SYNC

BAND 111 SELECT:-!

r!!. ~~~II~~ INDICATION

UHF SELECT...!.

~PAL/NTSC

TRANSMISSION OPTION....!!.

~ RAMP GEN. RESISTOR

VA~~CL;OA~!~~~~~ ....!!.

VSS...!.!! L -_ _ _ _- - - 'r!Z-RAMP GEN. CAPACITOR
TOP VIEW

Order Number MM58313N
See Package 20A

Description of Pin Functions
Pin No.

Function

Name

20
10
16
15
5
6
7
9

Voo
Vss
Horizontal Sync Input
Vertical Sync Input

8

Transmission Option Input

14

Tuning Indication Option
Input

3
2
4
12
11

Timing capacitor}
Timing Resistor
Limit Resistor

13

* PALINTSC Option

18

Video Output Y

17

Video Output G-Y

19

Varactor Clock Enable

Positive supply.
Ground.
Positive sync pulse from TV set.
Positive sync pulse from TV set.
Connect to Vss to select required
band, hence displaying corresponding band numbers.
Tuning voltage from varactor
diodes. Indicator position is proportional to this voltage (external
resistor divider required).
Connect to Vss for normal broadcast reception or to V DO for cable
transmission.
Connect to Vss for 'finger' display
or Voo for horizontal bar indication.

}
Band I Select Input
Band II Select Input
Band UHF Select Input
Varactor Tuning Voltage
Input

Ramp Generator Resistor
Ramp Generator Capacitor

I

MM5840 Clock Enable

.,. For this pin there is an internal pull up reSistor to VOD.

5-175

Frequency determining components.
Components governing the internalIy generated ramp voltage. Connect
to Vss.
Connect to Vss for PAL.
Connect to Voo for NTSC.
Active high output used to blank
video.
Active high output used to drive
color gun.
Enables 3.3 MHz oscillator from
vertical sync pulse to vertical line
58 ( + V E enable).
Enables 3.3 MHz oscillator when
MM5840 OIP is required (+ VE
enable) .

Functional Description
Operation (Block Diagram, Figures 6 and 7 for Timing
Diagrams).

Vertical Counter
9·stage static shift register counter with exclusive NOR
feedback. This counts the horizontal sync pulses and is
reset c;turing vertical sync pulse time.

Both graticule and character displays are positioned
digitally in the horizontal and vertical directions.

Horizontal Time Slot Decoder

Graticule (Figure 1)

ROM outputs from which are generated the required
decode times. This is used to generate the start/stop com·
mands . for the graticule display and to update the
character address circuitry with respect to the bank
selected.

The top of the graticule display is 24 lines down after the
vertical flyback pulse. The position is determined by
counting the horizontal flyback pulses.
The graticule is 14 lines high and is therefore displayed
from line 24 to line 38.

Vertical Time Slot Decoder

In the horizontal direction the display is positioned by
counting pulses from the internal 3.3 MHz osc. A divide by
6 counter is used to derive the 550 kHz required to
generate the graticule display.

ROM used to generate outputs at required vertical decode
time.
Divide·by·Two

Characters (Figure 3)

Used to divide the horizontal sync pulses by two; i.e., each
vertical decode implies that twice the number of line
scans has elapsed.

Provision is made for displaying two digit numbers on
both the left hand side and right hand side of the screen.
The initial arid final characters being coincident with the
graticule extremes (Figure 2).

Divide·by·Six
3·stage Johnson counter used to obtain the 550 kHzre·
qui red to produce the graticule display.

The characters are built up from 42 dots on a 6 x 7 matrix.
The dot rate is defined by the 3.3 MHz clock, each dot be·
ing 0.303 ",s wide and 2 lines high. Spacing between the
two digits is 0.606 ",s.

Band Decoder
4 to 5·line decoder one output of which is selected accord·
ing to the band selected and the state of the option input.

Tuning Indicator (Figure 4 and Figure 5)
The tuning indicator is derived by comparing the varactor
voltage with the ramp signal derived from a capacitor fed
with constant current.

Character Address Circuitry
Circuitry controlling the character addressed. This is up·
dated at required times so that the required characters will
be displayed during the correct time slots with respect to
the band selected .

A comparator organized as a window detector determines
the position and width of the tuning indicator.
. The first trip point occurs when the ramp voltage equals
that of the varactor input, and the second a set voltage
after.

Character ROM
ROM organized to produce characters of 6 x 7 format.

A constant. width bar is then generated dlJe to the linear
ramp.

Shift Register

Note that an option input permits the tuning indication to
appear as a horizontal line. This is achieved by enabling
one comparator output only.

7·bit shift register,.6 bits of character information are
loaded at the required horizontal times during each of the
7 vertical decode times for which the characters are
displayed. Character information is then clocked out
serially at 3.3 MHz.

Oscillator'

Constant Current Ramp Generator

Three pin oscillator frequency being determined by exter·
nal timing components. Output capable of driving
MM5840, MM5841 series of display chips is available from
one of the pins.

A current mirror circuit used to charge an external
capacitor to produce linear voltage ramp.
Comparators

Horizontal Counter

Analog comparator organized so that trip pOint 1 < trip
point 2 where trip pOint 1 varactor input voltage between
OV and 9V. A logic 1 output is obtained when trip pOint
1 < V ramp < trip point 2.

=

9·stage dynamic shift register counter utilizing exclusive
NOR feedback. This counts the 3.3 MHz pulses and is
reset during horizontal sync pulse time.

* 1.

Oscillator is enabled by varactorenable pin (high level) during the time
from vertical sync pulse to vertical decode 29.

AND/OR
2. Oscillator is enabled by output from MM5840 pin.

5-176

Functional Description (Continued)

SCREEN

FIGURE 1. Graticule Format and Screen Position

[lJlflflflJl1UU--lINEZ'
...
-----------------.....I.--Il-lINE38

[Ul- -LINE"
"lJ--lINE58

For cable display characters are 2. S2,

FIGURE 3. Typical Character Format - 6 x 7 Matrix

FIGURE 2. Band I Display

FIGURE 4. Vertical Tuning Indication

' "' '¥[lJlflflflJl1UU
LINE 30
LINE 36

FIGURE 5. Optional Horizontal Tuning Indication

5·177

Functional Description (Continued)

I'

20 m'

VERTICAL 1 I L - - - - .
SYNC

o

=n

1
HORIZONTAL
SYNC

1
JL

I-

64",-----------1,1

o

I

3.3 MHz 1 CLOCK

J1
Jl

o

I

550kHz

FIGURE 6. Input arid Internally Generated Waveforms

HORIZONTAL
SYNC

~

I

~----------------------------------

3.3 MHz
CLOCK

GRATICULE
OISPLAY

LINES 24-36

GRATICULE
DISPLAY

LlNES3S-38L

!l

21
CHARACTER
INFORMATION

TUNING
INOICATION
(VERT 8AR)

33

CLOCK PERIOO
41
124

35

--·-i~---{
I
I

LINES 44-58

I

____-'-..........J."" _ _ ..1._..L. ___ .1 ___

LINES 0-36

1S.TTRIP
POINT

-n-

130

132

L

138

~---~ ~---L

I
I
I
.J. ___ .1._J. __ _

2NO.TRIP
POINT

------~--~--~ ~----------------------TUNING

INDICATION
(HORIZ BAR)

LINES 30-36

I.

t--TRIPPOINT

FIGURE 7. Output Waveforms

5-178

Games/Calculators

~National

Games/Calculators

~ Semiconductor
MM5780 Educational Arithmetic Game
General Description
The MM5780 single-chip educational game was developed using a metal gate, P-channel, enhancement and
depletion mode MOS process. It was designed with low
end-product cost as the ·primary objective and is directed
toward the educational toy market. Besides the MM5780
as shown in Figure 1, requires only a keyboard, "Right"
and "Wrong" LED displaY, a 9V battery and an on/off
switch. Keyboard encoding and key debounce circuitry,
all clock and timing generation and the capability to
drive the two LEOs are all included on-chip and require
no external discrete components.

When the battery voltage falls below an operational
level, an internal circuit will disable both indicator
outputs; i.e., neither indicator will be on after depression
of Test.
The Ready output signal is used to indicate when the
game is performing an operation. It is useful in testing
of the device or if interfacing with other logic. Another
feature that is important in testing is the capability of
reducing the key debounce time from seven word times
to four word times by forcing the Digit 7 output high
during Digit 9 time.

The MM5780 educational game was designed to be an
arithmetic aid to school age children. Problems are
entered into the machine in algebraic form exactly as
they are written across a printed page. The student
provides the answer or missing factor and when finished,
depresses the Test key. "Right" and "Wrong" outputs
provide an indication of the results of the test. If wrong,
the student trys the problem again. If correct, he can
move on to the next problem. Most problems using +,
-, x and .;. can be learned using this machine. The
game does not have provisions for remainders in div'ision
or negative number entries. A negative result can be
entered before the Test key is depressed.

Features
• Full 8-digit entry capacity
• Four functions (+, -, x, .;.)
• Convenient algebraic key entry notation
• Floating point input and output
• Chain operations
• Direct 9V battery compatibility; low power

The MM5780 is a low power device which operates
directly from a 9V battery. Battery life is estimated to
be 10 to 30 hours depending on battery quality and
operating schedule.

•
•

Direct interface to LED indicators
No external components required other than keyboard
and LED display for complete educational game.

•

Overflow and divide-by-zero error indication

•

Low battery voltage sensing

Connection Diagram
Dual-In-Line Package

READY-.!..

~OlGIT4

OIGIT9.2..

~OIGIT5

,2-

r!!- DIGIT 6

OlGIT2...!..

FDlG'T7

DIGITJ

2..

~DIGIT8

Voo

...!.

~ KEV INPUT J (K3)

NC

..2..

OIGIT

NC

..!.

r!!- KEV INPUT 2 (K2)
r!l- KEY INPUT 1 (K1)

NC

..!.

16 "WRONG"
rlNOICATOR

NC

.!..!L

~IND1CATOR

NC

.ll.

~NC

Vss

.2l

15 "RIGHT"

r!!TOPVIEW

5-181

NC

Order Number MM5780N
See Package 22

Absolute Maximum Ratings
Voltage at Any Pin Relative to Vss. (All
other pins connected to V ss.)
Ambient Operating Temperature
Ambient Storage Temperature
Lead Temperature (Soldering, 10 seconds)

Vss + 0.3V to Vss - 12.0
O°C to +70°C
-55°C to +150°C.
300°C

Operating Voltage Range (Note

1)

B.5V ~ Vss - V DD ~ 9.5V
(Vss is always defined as the most positive supply voltage.)

DC Electrical Characteristics
PARAMETER
Operating Supply Current (I DO )
Keyboard Scan I nput Levels
(Kl, K2 and K3)
Logical High Level (V'H)
Logical Low Level (V,d
Digit Output Levels (Note 1)
Logical High Level (V oH)
Logical Low Level (Val)
Indicator Output Current
Source Current

Ready Output Levels
Logical High Level (V OH )
Logical Low Level (Val)

CONDITIONS
V DO

MIN

MAX

UNITS

8.0

14.0

mA

= Vss -9.5V, T A = 25°C

V ss -6.5V ~ Voo ~ V ss --9·5V
Voo = V ss -6.5V
V DO = V ss -9.5V

V ss -2.5

V ss -6.5V ~ V OD ~ V ss --9·5V
Voo = V ss -6.5V
Voo = V ss -9.5V

V ss -1.5

TA = 25°C
V OUT = V ss -4.5; V DD
V OUT = V ss -4.8, Voo
lOUT
lOUT

TYP

= V ss -6.5V
= Vss --9·5V

= -{).4 mA
= 10l1A

AC Electrical Characteristics
PARAMETER

-10.0

-15.0
-25.0

V ss -5.0
Vss-B.O

V
V
V

V ss -6.0
V ss -7.0

V
V
V

-32.0

V ss -l.0
V oo +l.0

mA
mA
V
V

(Figure 2)

CONDITIONS

MIN

TYP

MAX

UNITS

Word Time

0.6

1.5

5.2

ms

Digit Time

70

170

580

I1S

Keyboard Input (Kl, K2, K3)

ClOAo

= 100 pF

CLOAO

= 100 pF

4

I1S

High to Low Transition

Time After Key Release
Ready Propagation Time
Low to High Level (tPoH I
High to Low Level (t Pol I

60

140
0.5

480
1.5

I1S
ms

Key Bounce·out Stability Time
IThe time a keyboard input must
be continuously higher than the
minimum logical high level to be
accepted as a key closure, or
continuously lower than the maximum logical low level to be
accepted as a key release.)

4.2

10.5

35.0

ms

Calculation Time for
99999999 -0 1 = 99999999

90

220

765

ms

Note 1: The internal low battery voltage sensing circuit will disable both indicator outputs when VSS-VOD falls below a safe ':operating
voltage. That voltage may be less than or greater than 6.5V depending on process variables; the MM5780 will have been tested to operate correctly
for any voltage less than 9.5V at which an indicator output is enabled.

5-182

POWER
SWITCH

.rif'
--=-

9V

11

+l;;
"

" .,

~"

jo!-"

LED

~NOICATORG

G

~

RIGHT

WRONG

V",

"

IG

Voo

MM5180

19 '3
01 02 03 04 05 D6
OJ 08
4
5
24
23 22
21
3
20

6

09

I'

~"
~"

~o,.

jo!-"
~a...
~Q...

~"
i'o!-Q...

~"

"o.:-Q...

=

.,IJ---

~"
-

~

9

a....

0

~"
FIGURE 1. Complete Game

I-------WOROTIME---------I
~V"'-_t-r--'

DIGIT 9
,""Vee

1----'-INTERNAl DElAY

DIGIT 1

READY

", i

""'--t
Jr:V":""O-'------

-----....;

_____~~V~O~,---------~~------J
FIGURE 2. Output Timing

KEY INPUT BOUNCE AND NOISE REJECTION
The MM5780 game chip is designed to interface with
low cost keyboards, which are often the least desirable
from a noise and false entry standpoint.

or ringing has stopped and the stability time counter has
timed out. Noise that persists will inhibit key entry
indefinitely. Key release is timed in the same manner.

A key closure is sensed by the game chip when one of
the Key I n put Li nes, K1, K2 or K3 are forced more
positive than the Logical High Level specified in the Elec·
trical Specifications. At the instant of closure, an internal
"Key Bounce·out Stability Time" counter is started.
Any significant voltage perturbation occurring on the·
switched key input during timeout will reset the timer.
Hence, a key is not accepted as a valid entry until noise

One of the popular·. types of low cost keyboards
available, the elastomeric conductor type, has a key
pressure versus contact resistance characteristic that can
generate continuous noise during "teasing" or low pres·
sure key depressions. The MM5780 defines a series
contact resistance up to 50 kn as a valid key closure,
providing an optimum interface to that type of keyboard
as well as more conventional types.

5-183

Error Conditions
In the event of an overflow or divide-by-zero the
"Wrong" light will come on and, remain on until a
Clear key is depressed_ Normally the indicator lights are
'
activated only after depression of the -rEST key.
KEY OPERATIONS
Clear Key
The Clear key clears all registers to zero and places the
machine in an idle state.
Number Entries
First entry clears the entry register and enters the
number into the least significant digit (LSD) of the
entry register and extinguishes the indicator lights.
Second through eighth entry shifts the entry register
left one digit and enters the number into the LSD. The
ninth and subsequent entries, are ignored and no error
condition is generated. Because only seven positions
are allowed to follow the decimal point, the eighth and
subsequent entries after a decimal point entry are ignored.
Decimal Point
Depression results in a decimal point entry into the
entry register.
Add, Subtract, Multiply or Divide Keys
First depression
entry, perform
any, and record
operation to be

after a number entry will terminate the
the previously recorded operation, if
the function key depressed as the next
performed after another number entry.

Subsequent depressions of any function key, without an
interceding number or decimal point entry will supersede
the previous function as the next to be performed. If
function key is depressed after an equal key, the result
of the operation will be re·entered and the function key
depressed will become the next operation to be performed after a number entry is followed by another
function key (including equal) ..

a

Equal
First depression after a number ,entry will terminate the
entry, perform the previously recorded operation and
record the fact that an equal key has been depressed.
Depression after the add, subtract or divide keys, without an interceding number or decimal point entry, will
be ignored. After a multiply key, the number in the
entry register will be squared.
Resultant Entries
Results are entered as number entries after an equal key
and before the Test key. Results are assumed positive
and a plus key should not be entered prior to the
resultant. Negative results must be preceded by a minus
key.
Test
The Test key is used to terminate computations and
to initiate a test of· the student's' answer versus the
game's answer. If the answers match, the "Right" indicator is enabled, otherwise the "Wrong" indicator is
enabled. If the results are incorrect the problem must be
worked again from the beginning.

TABLE I. Ready Signal Description
GAME FUNCTION

READY SIGNAL

Idle

READY is quiescently at a Logical High Level ('\ovssf,

Key Entry and Functional Operation

When a key is depressed, the bounce-out stability timer is initiated.
READY remains high until the bounce-out time is completed and the
key isentered, at which time it changes to a Logical Low Level ('\oV DD ).

Key Release and Return to Idle

READY remains low until key release is debounced and the game
returns ro the idle state. The low to high transition signals the return
to idle.

TABLE II. Indicator Truth Table
INDICATOR OUTPUT

GAME CONDITION

PIN 15

PIN 16

Test was last key depressed with correct answer entered.

HIGH

LOW

Test was last key depressed with 'incorrect answer
entered or the problem has resulted in an error or
overflow condition.

LOW

HIGH

Any key other than Test was last depressed and
calculator is not in' an error or overflow condition.

LOW

LOW

Clear was last key depressed.

LOW

LOW

The battery supply voltage has fallen below a valid
Clperating voltage for the MM5780. Independent of
keys depressed.

LOW

LOW

5·184 ;

sample problems

I.

Simple Addition: 4 + 5 = ?
Key

Display

Comments

C

C
4

+
5
8
TEST
4

+
5
9
TEST

II.

6
+

5
11
TEST

Answer supplied
Wrong answer
Indicator goes out

Display

Comments

NONE
NONE
NONE
NONE
NONE
RIGHT

I ndicator goes out
Missing factor supplied

Subtraction: 4-7=?
Key

4
7
3
TEST

IV.

Clear necessary on power·up

Missing Factor Addition: 6 + ? = 11
Key

III.

NONE
NONE
NONE
NONE
NONE
NONE
WRONG
NONE
NONE
NONE
NONE
NONE
RIG HT

Display

Comments

NONE
NONE
NONE
NONE
NONE
NONE
RIGHT

Indicator goes out

Negative answer supplied

Multiplication: 7x3=?
Key

7
x
3
21
TEST

Display

Comments

NONE
NONE
NONE
NONE
NONE
RIGHT

5·185

I ndicator goes out

Answer supplied

0

CO

sample problems (con't)

:E

V.

......
U')

:E

Missing Factor Multiplication: 6 x? = 12
Key
6
x
3
12
TEST
6
x
2
12
TEST

VI.

Display

Comments

NONE
NONE
NONE
NONE
NONE
WRONG
NONE
NONE
NONE
NONE
NONE
RI GHT

I nd icator goes out
Missing factor supplied

Incorrect
Indicator goes out
Missing factor supplied

Division: 15 + 3 =?
Key
15
3
5
TEST

Display

Comments

NONE
NONE
NONE
NONE
NONE
RIGHT

Indicator goes out

Answer supplied

VII. Complex Chain: (6 + 2 -101 x 3 =?
Key
6

+
2
10
x
3

6
TEST

Display

Comments

NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
RIGHT

I ndicator goes out

'Negative answer supplied

5·186

~National

Games Calculators

~ Semiconductor

PRELIMINARY

MM57455 Advanced Educational Arithmetic Game
General Description
Figure 1 contains an electrical diagram of a complete
teaching game system.

• Internal timer gives the user about 10 seconds to
answer. If he doesn't answer, the problem is counted
wrong

Features

• Ten problems in each problem set
• Number of problems correct appears in the display at
the end of a problem .set, with the green LED flashing

• Produces add, subtract, multiply, and divide problems
which teach basic arithmetic

• "TABLE" button causes non-random problems to be
generated

•
•
•
•
•

• "COMPLEX" button causes algebra-type problems to
be generated
• "AMATEUR/PRO" buttons select easy/hard addition
and subtraction problems

6,562 different problems are produced
Problems are generated randomly and automatically
Automatic entry, no "ENTER" key is needed
Green LED lights when the correct answer is entered
If the wrong answer is entered, "E" appears in the
display and the user gets a second try

• If the user answers incorrectly on both tries, the correct answer is flashed in the display

• "NORMAL/FAST" buttons select 10 or 3 seconds to
answer a problem
• Automatically begins game on power "ON"
• Low system cost (Figure 1)

Electrical Diagram
GNo 471'F Vee

1t-'~
15-12
8-6
28
27
26
25
21
MM57455

22
23
24

19
9
10
20
CKI
3

Vee

I" IL'
" ~",'~
IL'

7

•t

Do
01

r100PF

r

O.1 1'F

,II L'

02
04
05
06
07

INo

AMATEUR

7

4

1

SLOW

PRO

8

5

2

FAST

ALGEBRA

9

6

,3

0

TABLE

I

x

-

+

IN1

,I

IN2
IN3

tJ

2N2907

L 1~0!

IL'" WII -

03

RESET
4
1B SK

47k

Vee

..,

NSA1481
Sa-Sg

~

GREEN

? / LED

-).
: 50012

•

...L..

5-187

1

Absolute Maximum Ratings
Voltage at 'Any Pin Relative to GND1
Ambient Operating Temperature
Ambient Storage Temperature
Lead Temperature (Soldering, 10 Secol]ds)
Power Dissipation

-0.3Vto +10V
O·Cto +70·C
-65·Cto +150·C
300·C
0.75 Watt at 25·C
0.4 Watt at 70·C

"Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur. DC and A C electrical specifica tions
are not ensured when operating the device at absolute maximum
ratings.

DC Electrical Characteristics
. Parameter
Operating Voltage (Ved
Operating Supply Current

O·C .. TA .. 70·C, 4.5V .. Vee

Conditions

~

9.5V, unless otherwise specified

Min.

Typ.

4.5

Max.

Units

9.5

V

8

rnA

0.6

V
V
V

Vee = 5V, TA = +25°C
(all inputs and outputs open) .

Input Voltage Levels
OSCIN,~

Logic High (VIH)
Logic Low (VIIJ
RESET Hysteresis
. All Other Inputs
Logic High (VIH)
Logic High (V1H)
Logic Low (VIIJ
Output Current Levels
Ouptut Sink Current
0 0 -07 (lotJ
Sa-Sg (Iou
Output Source Current
Sa-Sg (IOH)

0.7Vec
1.0
Vee = 9.5V
Vee=5V±10%

3.0
2.0
0.8

Vec = 9.5V,
Vee = 4.5V,
:Vee =9.5V,
Vee = 4.5V,

VOL = 1.0V
VOL';' 1.0V
VoL ';'1.0V
VOL.'" 1.0V

: Vee = 9.5V, VOH = 2.0V
Vee = 6.0V, VOH = 2.0V

V
.V
V

30
15
2.0
1.0

150
70
9.0
4.5

rnA
rnA
rnA
rnA

-3.0
-3.0

-30
-20

rnA
rnA

Functional Description
Display Configuration

Number Keys, "0';9"

The special LED display used with the,tv'lM57455 displays
anyof the 4 symbols "+", "-", "x", "I" in the third digit
position. An "=" is displayed.in the sixth digit position.
The remaining 6 dlgits are normal 7-segment numeral
displays.

These keys are used to enter answers to problems. ,After
a problem appears in the display, the user has 2 tries to
answer it correctly.

Power "ON~'

If the user keys in the correct answer to a problem, the
green LED lights up immediately for 1 Yo seconds. Then
a new problem appears.

Upon powering "ON" the MM57455, it begins displaying
the sysmbols''''':", "_", HX", "/", "~I1,:. :one after ana..
ther, each lasting about Yo second. This indicates that it
Is at the beginning of.a "problem set" and ready to accept a function key input.

Key Operations
Function Keys, u+", "_", I'X", 1'/"
One of these keys Is depressed to begin.a problem set.
After pressing one of these keys, a randomly generated
problem appears in the display. The problem is either
"+", "-", "x", "I", depending on the key that was
pressed.

Green LED

Incorrect Answer Indicator
If the user keys In a wrong answer to a problem, his:
answer disappears in the display and an "E" appears.

Second Try
If the user answers incorrectly, he gets a second try.
When the "E" appears (indicating that the answer is
wrong), he types in his second try. Again, the green LED
lights if correct, and an "E" appears.if wrong.

Functional Description

(cont'd)

Internal Timer
A non-random table digit can be selected by depressing
the desired number (1-1 0) just before pressing a function
button at the start of a problem set.

The MM57455 has an internal timer which allows the user
10 seconds to answer a problem. If he doesn't answer in
10 seconds, an "E" appears in the display, indicating a
wrong answer. The user then gets a second iry and again
must ilnswer within 10 seconds.

Example: press 9 x
and these problems will appear:

Flashing of a Correct Answer

9x1=
9x2=
9x3=

In the user answers wrong on both tries, the correct
answer flashes in the display. Then, the next problem
appears.

Ten Problems per Problem Set

9xO=

New problems appear one after another until 10 problems have been done.

"ALGEBRA" Key
If the" ALGEBRA" key Is depressed just before pressing
a function key at the start of a problem set, algebra-lype
problems will be displayed (the answer is present and
one of the factors is blarik, as: (15 + = 21). The user
must enter the missing factor. (Note. Both "ALGEBRA"
and "TABLE" buttons may be pressed before pressing a
function key. This will cause algebra-type table problems"
to be displayed.) The order of depression is unimportant;
i.e., "ALGEBRA" or "TABLE" may be pressed first.

Score at End of Problem Set
After 10 problems are done, the number of problems the
user got right appears in the display, and the green LED
flashes. Only first try answers are counted correct. After
16 flashes, the MM57455 again displays "+", "-", "x",
"''', "+", ... and is ready for another function key entry.

"TABLE" Key

"AMATEUR/PRO" Keys

If the "TABLE" key is depressed just before pressing a
function key at the start of a problem set, table problems
will appear, with a random table digit.

These keys select easy ("AMATEUR") or hard ("PRO")
addition and subtraction problems. Easy means sum < 30
and difference < 20. Hard means sum < 100 and difference <100.

Example: press "TABLE" x
and these problems may appear:

When power is turned "ON", the machine is in easy
("AMATEUR") mode.

6x1=
6x2=
6x3=

"NORMAL/FAST" Keys
These keys are used to select 10 second ("NORMAL") or
3 second ("FAST") answer time.

6x10=

When power is turned "ON", the machine is in the 10
second ("NORMAL") mode.

5-189

~National

Games/Calculators

~ Semiconductor

MM57459 a-Digit LED Direct-Drive Memory Calculator
General Description

Features

The single·chip MM57459 calculator was developed using
an N·channel enhancement and depletion mode MOS/LSI
technology with a primary object of low end·product cost.
A complete calculator as shown in Figure 1 requires
only the MM57459 calculator chip, and X·Y matrix key·
board, an NSAl188 LED display and a 9V battery.

• 8 Digits with four key memory (M+, M-, MR", MC)
• Low voltage operation (single power supply)
• Direct interlace with digits and segments of LED dis·
play
• Percent function with add·on/discount'
• Automatic constant on all .five functions

Keyboard decoding and key debounce circuitry, all
clocks, and timing generators, power·on clear, and
7,segment output display decoding are included on·
chip, and require no external components. Segments
and digits can usually be driven directly from the
MM57459, as,the segments source up tei 30mA max.
peak current and,the digit driv,ers sink 30mAmin. ,
Leading zero suppression and a floating negative sign
allow convenient reading of the display and conserve
power: Up to 8 digits for'positive numbers and 7, for
negativeriuiTlbers can be displayed, with the negative
sign displayed in the left·most position.

•
•
•
•
•
•

Floating minus sign
Leading zero suppression
Internal clock generator
Internal encoding for keyboard inputs
Internal debouncing for keyboard '(nputs
Display flash in calculator overflow state

Typical Keyb()ard and" Connection Diagram

GNO

1

24

DO

INO

2

23

01

CKI

3

22

RESET

4

S,

04

Sb

D5

MM57459

Sg

06

Sd

07

N.C.

VCC
Se

N.C.

Sa

INl

S p i 12

1 3 r Sc

Top View
Order Number MM57459N
See Package 22

5·190

D2
03

Absolute Maximum Ratings
Voltage at Any Pin Relative to GND1
Ambient Operating Temperature
Ambient Storage Temperature
Lead Temperature (Soldering, 10 Seconds)
Power Dissipation

-0.3Vto +10V
O·Cto +70·C
-55·Cto +150·C
3QO·C
0.75 Watt at 25·C
0.4 Watt at 70·C

Absolute Maximum Ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.

DC Electrical Characteristics
Parameter

O·C'" TA '" 70·C, 4.5V '" Vee'" 9.5V, unless otherwise specified

Conditions

Min.

Operating Voltage {Vecl
Operating Supply Current
Input Voltage Levels
CKI, RESET
Logic High (V1H)
Logic Low (V1u
RESET Hysteresis
All Other Inputs
Logic High (V1H)
Logic High (V1H )
Logic Low (V1u
Output Current Levels
Ouptut Sink Current
Do-:-D3 (Iou
Sa-Sg, Sp (loll
Output Source Current
Sa-Sg, Sp (IOH)

4.5
Vee =5V, TA= +25·C
(all inputs and outputs open)

Typ.

Max.

Units

9.5

V

8

rnA

0.6

V
V
V

0.7 Vee
1.0
Vee =9.5V
Vee=5V±10%

Vee = 9.5V,
Vee = 4.5V,
Vee = 9.5V,
Vee = 4.5V,

VOL =
VOL =
VOL =
VOL =

3.0
2.0

1.0V
1.0V
1.0V
1.0V

Vee = 9.5V, VOH = 2.0V
Vee = 6.0V, VOH = 2.0V

5-191

0.8

V
V
V

30
15
2.0
1.0

150
70
9.0
4.5

rnA
rnA
rnA
rnA

-3.0
-3.0

-30
-20

rnA
rnA

1. Key Definition

~ - Percent

0-0-8

The purpose of the percent key is to allow for the calcu·
lation of add-on and discount. Determination of add-on
requires the principal amount to be the first enter fol·
lowed by the + or x key, with the percentage being.
the second entry. Depression of the percent key yields
the amount to be added·on, such as tax or interest. De·
pression of the' = key adds this amount to be principal.
Discount is determined in a similar manner using the key (x and - keys). In the constant mode, new percentages to be added-on may be entered while retaining the
principal amount.

The first number key in a sequence will clear the display
and enter the digit in the LSD of the display. Successive
entries wi II shift the display left and enter data in the
LSD. The first decimal point entered is effective. An at·
tempted entry of more than 8 digits or 7 decimal places
will be ignored.

~

-

Clear

Clears the display and constant registers, and the result
overflow indicator. Memory register is not affected by
key. In the memory overflow condition, this key is opera·
tive as a clear memory key.

EJ -

Clear Entry

Clears the display of a number entry. In the result overflow mode, this key resets the overflow condition and
allows calculation to continue; however this key is inop·
erative during memory overflow.

B - Memory Recall
Transfers the contents of the memory register into the
. display register. Memory is retained except in the memo
ory overflow condition. In this case, memory is cleared
and its previous contents are displayed in the result overflow mode.

B-

~ - Memory Clear
Clears the memory.

B-

8- Plus

2. Error Conditions
Minus
Result Overflow

Stores a subtract operation and performs a possible
preceding operation. Repeat subtraction by the minus
key will not be possible. If this is depressed after a % ,
+ ,or = .key, subtraction becomes the pending opera·
tion. Immediately following a x or .;- key, this acts as
a data entry and - O. is displayed.

If the result in absOlute value exceeds 1()B - 1, the display
will flash, and only the C and CE keys are operative.

Memory Overflow
If a M+ or M- operation causes the contents of
memory to exceed the above value, the display will flash.
In this overflow condition, only the. C key is operative.

0- Multiply
Operates the same as the plus key except that a multiply
command is stored·. Successive depression of the mul·
tiply key will not alter the display.

3. Operation Characteristics

G - Divide

Data Entry

Operates the same as the plus key except that a divide
command Is stored. Successive depression of the divide
key will not alter the display.

0-

Memory Minus

Subtracts current display from the contents of memory.
M- will terminate a number entry.

Stores an addition operation and performs a possible
preceding operation. Successive depression of the plus
key will not affect the display.

[J -

Memory Plus

Add the current display to the contents of memory. M +
will termniate a number entry.

Entry is always floating. On data entry, the data will be
right hand justified with the last digit entered always
appearing in ihe least signiiicant digit position. The dis·
play register will left shift the display one digit as each
new digit is entered.

Equal

Executes any previous operation and maintains that
operation for possible use in the implied constant mode.
The first factor entered for multiplication and the second
factor entered for division, subtraction, and addition,
are retained for the constant operation. Completes the
add·on or discount mode when used following the %
key. The first depression of the equal key immediately
following a + or - key will not alter the display.

Data Output
The output data as a result of a calculation will be right
hand justified such that trailing insignificant zeros after
the decimal are not displayed. Numbers less than one (1)
will be displayed with one leading zero (0.25 for example).
Numbers greater than one (1) will not display ~eros to
the left of the most significant digit.

5-192

Output Display
Character Display

The output segments are fully decoded for standard
seven·segment display. The digit outputs are multiplexed
with the segment scan to provide the output.

0

!J

1

4

2
3
Y

5

:J

Digit and Segment Buffers

2

The segment buffers provide constant drop and operate
in conjunction with the constant current digit buffers to
provide display current.

3

Constant Operation

6

The MM57459 has an implied constant mode of operation
on + , - , x , '" , and % operations. The constant
calculation is performed automatically by the
key,
keys without a constant switch. The
% key, or %
second operand is treated as the constant for add, sub·
tract, and divide and the first operand is the constant
for multiplication.

7

,,-

w
I

B
9

8

=

=

SA S6 SC SO SE SF SG SP

n

9
Minus Sign

Dec. PI.
RESULT OVF: THE DISPLAY WILL FLASH.
MEMORY OVF: THE DISPLAY WILL FLASH.

For A ± 8%-type calculations, the first operand is treated
as the constant with the percentage displayed with the
proper sign.

Floating Minus Sign

Decimal Alignment

When displaying a negative number the minus indication
will be located one digit to the left of the MSD display.

The results of addition or subtraction remain aligned to
the preceding entry having the most decimal places unless a right shift is needed to keep the eight most significant digits (in which case the least significant decimal
digits are lost).

The results of multiplication and division are completely
right justified such that only the most significant digits are
displayed (the digits not displayed will be truncated).The
C key resets decimal alignment.

Display Font

Successive Operations

The following table shows the required segment outputs
as a function of the display. In the truth table, the symbol
• is used to indicate a selected segment.

Only the last operation entered is performed unless a entry follows a x or '" which sets up the calculator for
numeric entry only.

+v
47 ~F

r"9
~

51k

13
Sc

Vee

12
Sp

11
Sa

10

5,

8
Sd

7
Sg

6

Sb

15
5,

V+
: 100k

~

~

i

MM574759N

CKI

RESET

rr-'

10.1~F

100pF

GNO

-=1;

IN1 INO
14 2
1

4

2

5

3

6

+

-

07 06 05 04 03 02 01
Do
17 18
19 20
21 22 23 f4
CE C
7
MC

.
0

=

8

MR

%

9

M-

+

X

M+

KEYBOARO/

Figure 1. Typical Calculator Application

5-193

G B

F

NSA1188 LED DISPLAY
2 3 4 5 6 7

8

C OP A E
1

0

Telecommunications

~National

Telecommunications

~ Semiconductor
MM5393, MM5394, MM53143, MM53144
Push Button Pulse Dialer Circuits
General Description
The MM5393, MM5394, MM53143 and MM53144 are
low threshold voltage, ion-implanted, metal-gate CMOS
integrated circuits that convert pushbutton inputs into a
series of pulses to simulate a telephone rotary dial.
Pushbutton inputs require the use of a simple, low cost
single contact calculator type keypad_ An inexpensive
R/C oscillator network is used as the frequency reference. Storage is provided for 21 digits. A redial feature
via use of the # key is included. An interdigit pause can
be externally selected as either 420 or 840 ms. A mute
output is provided to mute receiver noise during outpulsing. No muting occurs during the interdigit pause,
thereby allowing the user to hear any busy or error
condition arising during the call. The MM5393 and
MM53143 provide a pacifier tone of 600 Hz every time

a key is depressed. The MM5393 and MM5394 provide a
1.6:1 break/make ratio. The MM53143 and MM53144
provide a 2:1 break/make ratio.

Features
•
•
•
•
•
•
•
•

Direct line powered operation
Low voltage operation to 2V
Low cost R/C oscillator
Single contact keypad
21-digit storage
Selectable interdigital pause
Redial of last number
600 Hz tone (available in MM5393 and MM53143)

Block and Connection Diagrams
Dual-In-Line Package
18
K<

03

K1

17 02

16

K2

Vss

Von

MM5J9J

r----------------l---l----------,

I

ase 1

I

READ

21 X4 RAM

K3

ase J

lOGIC

I
I
I
I

K'

-------01
KEYBOARD
SCAN

osc. AND
TIMING

DECODER

CONTROL

-------READ AND WRITE
CONTROL COUNTERS

L_________

______________

osc t asc 2 asc J

I

VOO

Vss

10

NO

Order Number MM5393J
or MM53143J
See Package 12
Dual-.ln-Line Package

K.

" 03

Kl 2

15 02
14 01

K2 3

__~

lOP
HOOK
SElECT SWITCH

K3
HKSW 5

ase 1

FIGURE 1

Tor~E

13

TOP VIEW

ji"[j'[S£

I
I
I
I

lDPSElECT

11 MUTE

DIAL PULSE

1
DIAL

OUTPUlSING
LOGIC

01

14

12

asc z

K2

03

OR
MM5314l

HKSW

Kl

02

15

K3

MMS394
OR
MM5J144

13 lOP SelECT
12 Voo
11

6

Vss

asc 2

10 MUTE

ase J

9 DIAL PULSE

TOP VIEW

Order Number MM5394J
or MM53144J
See Package 11
FIGURE 2

5-197

Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature Range
Storage Temperature Range
VDD-VSS
Lead Temperature (soldering, 10 seconds)

Electrical Characteristics
PARAMETER

VSS -o.3V to VDD +0.3V
-30°C to +70°C
-55°C; to +150°C
6.5V Max
300°C

TA within operating temperature range,Vss = Gnd, 2V::; VDD::; 5.5V
MIN

CONDITIONS

TVP

MAX

UNITS
..

Input Voltage Levels at
lOP Select, Hook Switch,
K1-K4
Logical "1"

VDD-0.25

VDD

V

Logical "0"

VSS

VSS+0.25

V

Input Pull·Up Resistor
Currents at K 1-K4, Source

VDD = 3V, VIN = VSS

1

3

/lA

VDD = 3V, VIN = 3V

1.5

3

/lA

1

k,Q

Input Pull·Down Resistor
Current at HK SW, Sink
Keypad Contact Resistance
Output Current Levels
Dial Pulse
Logical "1 ", Source

VDD = 3V, VOUT = VDD -0.9

150

/lA

Logical "0", Sink

VDD = 3V, VOUT = VSS +0.9

150

/lA

Mute
Logical "1 ", Source

VDD = 3V, VOUT= VDD -0.9

100

Logical "0", Sink

VDD = 3V, VOUT = VSS +0.9

100

Logical" 1", Source

VDD = 3V, VOUT = VDD -0.5

10

/lA

Logical "0", Sink

VDD= 3V, VOUT = VSS +0.5

10

/lA

Logical "1", Source

VDD = 3V, VOUT = VDD -0.5

20

/lA

Logical "0", Sink

VDD = 3V, VOUT = VSS +0.5

150

/lA

.

/lA
/lA

Tone

01,02,03

Supply Current

VDD = 3.3V, Osc Freq = 20kHz
VDD = 5.5V, "ON Hook" Osc Stopped

Outpulsing Frequency

Osc = 20 kHz

9

5,198

100
5'

/lA

11

Hz

/lA

Functional Description
A block diagram of the MM5393, MM5394, MM53143
and MM53144 integrated circuit is shown in Figure 1
and package connection diagrams for the 2 package
options are shown in Figure 2.
Oscillator (Pins 6, 7, and 8): The time base for the pulse
dialer integrated circuit is an R/C·controlied oscillator
like that shown in Figure 3, typically tuned to 20 kHz
by the R1 and C1 combination. Stability of ±10% of
typical frequency can be maintained over the voltage
range 3.0 - 5.5V and temperature range _30°C to
+70°C. At fixed voltage and temperature, part to part
variation is less than 5%.
This clock is successively divided to derive the necessary
timing for outpulsing and interdigit pause.
Keyboard (Pins 1-4 and 16-18 or 14·-16): The
MM5393, MM5394, MM53143 and MM53144 utilize an
inexpensive single contact (Form A, Figure 7) keypad.
A valid key closure is recorded when a single row (K x
input) is connected to a single column (Oy input).
Key closures are protected from contact bounce for
5ms.
Dial Pulse Output (Pin 9): The Dial Pulse output drives
an external bipolar transistor that sequentially opens
(breaks) the telephone loop a number of times equal to
the input digit selected. For example, key 5 will generate
5 loop current breaks. The break/make ratio of the
MM5393 and MM5394 is 1.6:1.0 (i.e. 61.5%:38.5%).
The break/make ratio of the MM53143 and MM53144
is 2.0:1.0 (i.e. 67%:33%).
lOP Select (Pin 15 or 13): The lOP select input is used
to select an interdigit separation of either 420 ms (logic
"0" = VSS) or 840 ms (logic "1" = VDD). An interdigit
delay precedes the first digit outpulse sequence.
Mute (Pin 11 or 10): The Mute output is used to drive
an external bipolar transistor that is used to mute the
receiver durin.g the outpulse period. System timing
between key closure, mute and dial pulse is shown by
the timing diagram in Figure 4.
Tone (Pin 14 MM5393 and MM53143 Only): The
MM5393 and MM53143 provide a tone output to
provide audio feedback to the user. The output is a 600
Hz tone that requires an external bipolar driver to
activate the telephone receiver.

Hook Switch Input (Pin 5): The function of the hook
switch input is to properly initialize the circuitry for
proper memory and redial operation. In the "ON Hook",
logic "0" or VSS condition, the hook switch input
a. Stops the 20 kHz oscillator
b. Sets the memory pointer back to digit 1
c. Clamps the dial pulse and mute outputs to logic
"1"orVDD
d. Resets all control logic
When the telephone is taken "OFF-Hook", this input
must be taken to logic "1" or VDD to release the
oscillator and enable the memory and various outputs.
For a non·redial application it is necessary to provide an
.RC delay of approximately 10)ls to the hook switch
input in order to provide a proper power·on clear
sequence.
Schematic diagrams for use of the MM5393, MM5394,
MM53143 and MM53144 in typical applications are
shown in Figures 5 and 6.
Redial Feature
Pushbutton inputs are accepted at an asynchronous rate.
If only 1 key is detected for 5 ms, the decoded key will
be loaded into a first-in-first-out memory and outpulsing
of the correct number of pulses will immediately begin.
After the first digit has been completed, outpulsing will
cease unless another key has been entered. This allows
use in a PBX system to insure receipt of a dial tone after
an access code has been entered and before entering the
remainder of the number. If the call was not successful,
it can be redialed at a later time by pressing the redial
(#) key. If an access code is required, as in a .PBX
system, it can be manually entered, the dial tone established, and then the redial key pushed to automatically
dial the remainder of the number. Only 1 key can be
entered before pushing the redial key.
An example of this operation is shown here:
KEY INPUTS

OUTPULSES

MEMORY

First Try

9 P 4087375000

94087375000

Second Try

9P#
9P#

94087375000
94087375000
94087375000

Third Trv

Where P implies a user pause

5-199

94087375000
94087375000

Functional Description

(Continued)

OSC I

VI

312 VOO

Voo
VI

I12VOO.

GNO
-112 VOO

VOO
VOUT
OV

FIGURE 3. Three Gate Oscillator and Waveforms

. DIGIT

DIGIT

3
2'
KEy~I_---""----

j i5ms

.
r~

.. M U T E !
.

-Ir-I

\---1 op---l

I-IDP---l

I

-11-12>0
t1 >O

I

.

DIALPULSE~lJlr-

J-LI--3S.S%

, 61.5%

FIGURE 4. Output Timing Waveforms

5-200

Functional Description

(Continued)

r-----------"

rlk>-~.~.'~k----~~----~---{~

I
I

I
I
I
I

o

TX

22k

I
I
I
I

4.1k

I
I
I

I
I
I
IL _ _ _ _ _ _ _ _

L _C ___Nr:::. __________ ~ ______

.J

IN PHONE

IN PHONE

Note 1: No redial.
Note 2:

Non-valued parts included in instrument.

Note 3: Letters refer to instrument terminals.

FIGURE 5. Typical Application of MM5394 in Type 5000 Telephone
OFF
HOOK

,.

I+--------~~--------~H~

r-----I

21k

UtTIP)

10llk

RINGER

____ ...: ______ J
IN PHONE

... Remainder of system is same as Figure 5.

FIGURE 6. Typical Application of MM5394 Using Redial Feature

!/

~

~

~

~

~

1./

8./

9../

!!/

"./

01

02

Kl

K2

K3

K4

03

FIGURE 7. Keypad Matrix

5-201

J

Telecommunications
~National
~ Semiconductor
MM5395, MM53125 DTMF (TOUCH TONE®) Generators
General Description

Features

The MM5395 and MM53125 are low threshold voltage,
ion-implanted, metal-gate CMOS integrated circuits that
generate all dual tone multi-frequency (DTMF) pairs
required in tone-dialing systems_ The 8 audio output
frequencies are generated from an on-chip 3_579545
MHz master oscillator_ No external components other
than the crystal are required for the oscillator_ The
MM5395 and MM53125 can be powered directly from
telephone lines over wide range loop conditions. The
MM53125 interfaces to an inexpensive single-contact
calculator type keypad. The MM5395 interfaces to a
standard telephone 2-of-8,keypad.

'.
•
•
•
•
•
•
•
•
•

Powered directly from telephone lin'e
Low voltage operation to '3.5V
Uses inexpensive 3,579545 MHz crystal
Tone accuracy better than ±1% without tuning
Operation with either single-contact or 2-of-8 keypads
Excellent thermal and voltage stabil ity
High band pre-emphasis
Multi-key lockout with single tone capability
Mute switch output
BCD interface mode

Block and Connection Diagrams
osc
OUT
PROGRAMMABLE OIVIDER
OSC IN

~46

~3B

~42

~34

Voo

TONE
KEYBOARD
LOGIC

+

.....--.FILTER
PROGRAMMABLE DIVIDER

CONTROL
LOGIC

C2
C3

C4

.--voo
.--VSS

Figure 1a
Dual-I n-Line Package
18

VSS

17

OSC 2
IN

16

NC

TONE
FILTER

15

USC 4
OUT

XMIT
14

MUTE

13

C4

12

C3

KB CONTROL

Rl
R2

11 R3

Cl

10

C2

TOP VIEW

@Registered trademark of Bell Telephone

VOO

Figure 1b

5-202

R4

Order Number MM5395N
or MM53125N
See Package 20

s:
s:
CJ1

Absolute Maximum Ratings
I

Voltage at Any Pin
VSS - 0,3V to VOD + 0.3V
-30°C to +70°C
Operating Temperature Range
-55°C to +150°C
Storage Temperature Range
6.5V
VDD - VSS
300°C
Lead Temperature (Soldering, 10 seconds)

J.TI

Electrical Characteristics

W

W
CO

s:
s:
CJ1
.....

T A within operating temperature range, 3.5V .::; VDD - VSS .::; 6V, unless otherwise specified
PARAMETER

CONDITIONS

MIN

I\)
TYP

MAX

UNITS

Input Pull-Up Resistor at Column Inputs

VIN

= VSS

100

400

kn

Input Pull-Down Resistor at "XMIT"

VIN

= VDD

100

400

kn

To VOD (MM5395)

VIN

400

kn

VIN

= VSS
= VDD

100

To VSS (MM53125)

100

400

kn

1

kn

Internal Resistor at Row Inputs

Keypad Contact Resistance
Input Voltage Levels
Logical "1"

VDO-0.25

Logical "0"

VSS

Output Voltage Swings at "TONE

VDD - VSS

OUTPUT"

RL ~ 500n

VOD
VSS+O.25

V
V

= 3.5V,

Low Band Only

820

mVp-p

High Band Only

1000

mVp·p

High Band Pre-Emphasis
Harmonic Distortion

2

dB

No External Filtering

-19

dB

With 1000 pF at Filter

-27

RL ~ 500n,

Tone Frequency Deviation
Operating Frequency

3.579545

Key Oebounce Time

2

Power Dissipation

VDD - VSS
RL

Output Current Level at "MUTE"
Logical "1"
Logical "0"

dB
1.0

= 6V,

%

MHz
4
50

ms
mW

= 500n

= 3.5V
= VDD - 0.2V
VOUT = VSS + 0.5V
VDO - VSS
VOUT

20

flA

2.0

mA

Functional Description
A functional block diagram of the MM5395 (or
MM53125) is shown in Figure ta, and a connection
diagram is shown in Figure tb. The oscillator will start
immediately upon power being applied. When a key is
pressed, both output tones start from zero on the
negative half cycle after a 2 to 4 ms key debounce period. If 2 or more keys are pressed together, one or both
tones will be switched OFF according to the functional
truth table, Figure 2a. Output frequencies and accuracies
are shown in Figure 2b.

5-203

The KB CONTROL input is used to change the interface
from keyboard to BCO according to Figure 3. In the
BCO interface mode, tone pairs are generated corresponding to the input BCD code on the ROW inputs
(Figure 4) and are enabled during the period XMIT is
high. By appropriate use of the COLUMN inputs during
this mode, individual tones can be generated for test
or signaling purposes.

CJ1

Functional Description

(Continued)
A MUTE output is provided to electronically control
common key functions such as switching out the transmitter and switching a muting resistor to the receiver.

supply near the low end of the line variation and the
output circuits shown in Figures 5 and 6 generate a line
current signal amplitude that will remain constant with
line voltage variations. Typical performance of this
circuit is shown in Figure 7. In order to meet all CEPT
and BPO guidelines for unwanted frequency components
at 10kHz and above the output, additional external
filtering is required as shown in Figure 8.

The sum of the 2 sine waves is provided at the TONE
output. A FI LTE R connection is available for access to
the base of the output emitter follower for efficient
filtering of the output waveform. A 1000 pF capacitor
produces a total harmonic distortion 20 dB below the in
band power without degrading high band pre-emphasis
for operation in the North American telephone system.
The TONE output signal amplitude varies directly with
the VDD supply. Using a zener diode to clamp this

Figure 9 is a keypad interconnection diagram to indicate
row and c?lumn connections for both types of keypads.
Timing waveforms are shown in Figure 10.

COLUMN

ROW

LOW BAND

HIGH BAND

None

None

DC

DC

One

One

fH

None'

One

IL
DC

One

None

IL

IH
DC

Two or more

None

DC

DC

Two or more

One

DC

None

Two or more

DC

IH
DC

One

Two or more

Two or more

Two or more

IL
DC

DC

DC

a. Functional Truth Table
INPUTS

DESIRED

ACTUAL

FREQUENCIES

FREQUENCY
(Hz)

fH (Hz)

fL 1Hz)

PERCENT
DEVIATION

R1

697

-

699.1

0.306

R2

770

766.2

-0.497

847.4

-0.536

948.0

0.741

R3

852

R4

941

-

C1

-

1209

1215.9

0.569

C2

-

1336

1331.7

-0.324

1477

1471.9

-0.35

1633

1645.0

C3
C4

0.736

b. Output Frequencies
FIGURE 2. Keypad Interface Mode

KB CONTROL

XMIT

INTERFACE MODE

Keypad

0

Open

1

0

Idle

1

1

Send tones

FIGURE 3. Interface Mode Control

XMIT

C1

C2

R1

R2

R3

R4

FREQUENCIES
GENERATED
fL (Hz) fH (Hz)

0

x

x

x

x

x

X

DC

DC

1

Open

Open

0

0

0

0

941

1336

1

ORen

Open

0

0

0

1

697

1209

1

Open

Open

0

0

1

0

697

1336

1

Open

Open

0

0

1

1

697

1477

1

Open

Open

0

1

0

0

770

1209

1

Open

Open

0

1

0

1

770

1336

1

Open

Open

0

1

1

0

770

1477

1

Open

Open

0

1

1

1

852

1209

1

Open

Open

1

0

0

0

852

1336

1

Open

Open

1

0

0

1

852

1477

1

0

Open

1

Open

0

fL
DC

IH

0

0

DC

DC

1

Valid BCD Inputs

DC

FIGURE 4. Functional Truth Table for Signal Interface Mode

5-204

Functional Description

(Continued)

AR

620

K1
HOOK SWITCH

S1

5m'

N,
GNO

N,
Note 1: All S switches are common with hookswitch.
Note 2: All K switches are common with KB.

Note 3: Switches shown in "OFF Hook" and "KB Depressed" positions.

FIGURE 5. MM5395 Typical Application

RR

'"

GNO

N,

FIGURE 6. MM53125 Typical Application

1.0
0.9

~

2

~

w

;

0~

~
w
~

-

OJAL

0.8

f-H~~

0.7

-

0.6

- t- LOW

r-

0.5

..........

r---

~

0.4

..........

i"""'-

I--

~

.....

O.l
0.2
0.1

o

o

10

20

lO

40

50

60

70

80

LOOP CURRENT (mAl

FIGURE 7. Typical Tone Output vs Loop Current

5·205

Lt')

,....

C\I

Functional Description

C")
Lt')

(Continued)

RR

~
~

620
VOO

Lrf

MM5395

C)
C")

8.2k

Lt')

OR
MM53125
TONE

~
~

Vss
4.3V

2.2

4.7k

mF

4.7 nF

600

FIGURE 8. Tone Output Circuit for European Application

r - - - - - - - - - - - 1 C1

.--------;C2

.-------1

C3

.----jC4

Rl
R2
MM5395

R2

RJ

MM53125
R3

R4
R4

1&
I

--F--..-IPt- ROW

ROW

\

I

J

_/

Vss

COLUMN

COLUMN

a) Standard Telephone Keypad

b) Single Contact Keypad

FIGURE.9. Keypad Interconnection 'Diagrams

VAllO
VALID INPUT

I

I

KB

------1

BCD CODE

---11""1---""'..____

XMTCONTROL _ _ _ _ _

MUTE~
TONE

MUTE

-----"'V'IIINV'WI/I..,.----I

1

---~120msl

1-2-4ms

TONE

a. Keyboard Mode (KB Control = 01

-------'VIM/INV...- - - -

b. BCD Mode (KB Control = 11
FIGURE 10

5-206

Telecommunications

II?A National

a

Semiconductor

MM53130 DTMF (TOUCH TONE®) Generator
General Description

Features

The MM53130 is a low threshold voltage, ion-implanted,
metal-gate CMOS integrated circuit that generates all
dual tone multi-frequency (DTMF) pairs required in tonedialing systems. The 8 audio output frequencies are
generated from an on-chip 3.579545 MHz master oscillator. No external components other than the crystal are
required for the oscillator. The MM53130 can be powered
directly from telephone lines over wide range loop conditions. The device can interface directly to an inexpensive
single-contact calculator type keyboard or a standard
telephone 2-of-8 keypad (Figure 4). The MM53130 is also
capable of accepting binary code inputs for microprocessor-controlled systems applications.

iii 3V-8V operating voltage

II
II
II
II
II
iii

III
II
ill

III
II!I
I!!I

On-chip 3.579545 MHz crystal-controlled oscillator
Tone accuracy better than ± 1 % without tuning
Interface with standard 2-of-8 telephone keypad
Interface with single-contact low cost keypad
Input signals can be in binary code
Multi-key lockout with/without single tone capability
On-chip high band and low band tone generators and
mixer
High band pre-emphasis
Low harmonic distortion
Open emitter-follower low impedance output
Separate receiver mute and transmitter mute switch
outputs
Powered directly from the telephone line

Block Diagram

VOO

PROGRAMMABLE
DIVIDER

723 719
721 717

C4

CONTROL
LOGIC

Rl
R2
RJ
R4
MOOE SelECT

VSS--'

PROGRAMMABLE
OIVIDER
7BO ~66

773 759

XMITSW
MUTE CONTROL

FIGURE 1
~ Registered trademark of Bell Telephone

5-207

XMIT SW
MUTE

Absolute Maximum Ratings
Voltage at Any Pin Except XMT SW and MUTE Vss - 0.3V to Voo + 0.3V
Voltage at XMT SW and MUTE Pins
Vss -0.3Vt015V
Operating Temperature Range
- 40·C to + 70·C
Storage Temperature Range
-65·Cto +150·C
15V
Voo-Vss
Lead Temperature(Soldering, 10 seconds)
300·C

Electrical Characteristics TA within operating temperature range, 3VsVoos8V,unless otherwise specified.
Parameter

Conditions

Input Pull·Up Resistor
Column and Row Inputs
Key/BCD Select
Mode Select
Tone Disable
Input Pull·Down Resistor
Column and Row Inputs

Min

Typ

Max

Units

25
200
200
200

50
650
650
650

90
1000
1000
1000

kn
kn
kn
kn

650
200

Voo=3V
Voo=8V

Input Voltage Levels
Logical "1"
Logical "a"

n
n

80% of Voo
Vss

Operating Frequency
Output Voltage Swing at Tone
Output
Low Band Alone
High Band Alone

RL>150n
RL>150n

Harmonic Distortion

RL>150n

Voo
20% 01 Voo
3.579545

MHz

820
1000

mVp·p
mVp·p

Tone Frequency Deviation
Typical Application Output
Level V L (See Figure 5)
Low Band Tone
High Band Tone
THD

20----.....

-= Vss
Connection Diagrams

40 OUTPUT BIT 18

Vss

"

OUTPUT BIT 11

JB

OUTPUT BIT 16

OUTPUT BIT 15
OUTPUT BIT 14

11

.,

J6

35

OUTPUT BIT 13

J4

OUTPUT 81T 12

"

OUTPUT BIT 11

OUTPUT BI110
OUTPUT BIT 9 10
DUTPUT"BIT B 11

OUTPUT BITl
OUTPUT BI16

OUTPUTBITS
OUTPUT 8114
OUTPUT BI13
OUTPUT BIT 2
OUTPUT BIT I

(Dual-In-Line Packages)

J2

11

MM544S/
MM5446

1Z

3D

"
"
"
"
"

Il

28

14

"
"
"
1l

23.

2Z
21

"

VGG 20
VDD

4D

Vss

Dur;UT BIT 19

OUTPUT BIT 17

OUTPUT BIT 20

OUTPUT81116

OUTPUT BIT 21

OUTPUT BIT 15

OUT,UT BIT 22

OUTPUT BIT 14

OUTPUT 81T 23

OUTPUT BIT 13

OUTPUT BIT 24

OUTPUT BIT 12

OUTPUT BIT 25

OU1PUTBI11'

OUTPUT BIT 2&
OUTPUT Bll 21

OUTPUT BlllO

"JB
17
J6

"
34

.,

OUTPUT BIT 9 10
11
OUTPUT BITI

OUTPUT BIT 28

OU1PUTBI17

OUTPUT BIT 29

OUTPUT BIT 3D

OUTPUl BI16

OUTPUT BIT'll

OUTPUT BIT 5

OUTPUT BIT 32

OU1PUT BI14

OUT'UTBIT J]

OU1PUT BI13

BRIGHT CONTR/OUTPUT BIT 34

OUTPUT BIT2

~

OUTPUT BI1.

DATA IN

J3

12
MM54471
MM5441

30

1Z

29

13

2B

"
"

21

1l

""

"

22

16

24

2l

"

VGG 20
VDD

CLOCK IN

31

21

TOP VIEW

TOPYIEW

Order Number MM5445N,
MM5446N
See Package 24

Order NumberMM5447N,
MM5448N
See Package 24

Figure 2&

Figure 2b

5-219

OUTPUT BIT'18
OUTPUT BIT'9
OUTPUT BIT 20
OUTPUT BIT 21
OUTPUT BIT 22
OUTPUT BIT 23
OUTPUT BIT 24
OUTPUT BIT 25
OUTPUT BIT28
OUTPUT BIT 21
OUTPUTBIT28
DUTPUTBIT29
OUTPUT alT 30
OUTPUT BIT 31
OU1PUT BIT 32
OUTPUT BIT 33
OUTPUT BIT 34
BRIGHT CONTR/OUTPUT BIT 35
DATA IN
CLOCK IN

·Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Power Dissipation
Junction Temperature
Lead Temperature (Soldering, 10 seconds)

Electrical Characteristics
Parameter
Power Supply
Vss
VGG
Vss.
Power Supply Current
Iss
IGG
Brightness Control
Input Logic Levels
Logic "0" Level
Logic "1" Level
Logic "0" Level
Logic "1" Level
Input Currents
DATA IN and CLOCK
DATA ENABLE
BRIGHTNESS CONTROL
Output Source Current
Segment OFF
Segment ON

Vss to Vss - 30V
-40·Cto +85·C
-65·Cto +150·C
560mWat +85·C
1Wat +25·C
+150·C
300·C

TA within operating range, Voo = OV, Vss = 4.5 to 5.5V, unless
Conditions

,

Vss=5V
Voo= VGG =0
Vss = 5V, VGG = -25V
Voo=O
With respect to Vss
-25V <> VGG <> -7V
..,25V <> VGG.<> -7V
Voo =VGG=0
Voo=VGG=O

Min.

Typ.

Max.

Units

4.5
-25
12

5.0

·5.5
-7
18

V
V
V

9
-2
Vss-VGd2

Vss

mA
mA
V

-0.3
2.2
-0.3
Vss-1

0.7
Vss+0 ..3
1
Vss+0.3

V
V
V
V

-10
-10

10
35
2

,..A
,..A
mA

-2

,..A
mA

250

kHz

60

.%

0.5

V

Excluding Output Loads
(Note 2)
Your = Vss - VGd2
Your = Vss - 2V (Notes 1 and ·2)

1

Input Clock Frequency

0

Duty Cycle

40

Output Matching

o~herwise specified.

50

-0.5

loui':=1.mA

Note 1: With Brightness Control tied to VSS (MM5445 and MM5447.) and VGG = -25V.
Note 2: All output source curient is .provided from the Brightness Control input pin (MM5445 and MM5447).

Functional Description
The MM5445 Series are specifically designed to· operate
4 or 5.digit alphanumeric displays with minimal inter·
face with the display and the data source. Character
generation is done external to the MM5445 Series. Serial
data transfer froni the data source to the display driver is
accomplished with 2 signals, serial data and clock. Using
a format of a leading "1" followed by the 35 data bits
allows data transfer without an additional load signal.
The 35 data bits are latched after the 36th bit is complete,
thus providing non·multiplexed, direct drive to the dis·
play. Outputs change only if the se~ial data bits differ
from the previous time. Display brightness is determined
by control of the positive output voltage level.

Figure 4 shows the input data format. A start bit of logi·
cal "1" precedes the 35 bits of data. At the 36th clock a
LOAD signal is generated synchronously with the high
state of the clock, which loads the 35 bits of the shift
registers into the latches. At the low state of the clock a
RESET signal is generated which clears all the shift reg·
isters for the next set of data. The sh ift registers are
static master·slave configuration. There is no clear for
the master portion of the fir!!t shift register, thus allowing
continuous operation.

There must be a complete set of 36 clocks or the shift
registers will not clear.
When the chip first powers ON an internal power ON
reset signal is generated which resets all registers and
all latches. The START bit and. the first clock return the
chip to its normal operation.

A block diagram is shown in Figure 1.
Figure 2 shows the· pin·out of the MM5445 series. Bit 1 is
the first bit following the start bit and it will apPear on
pin 18. A logical "1" at the input will turn on the
appropriate VF display segment.

Figure 3 shows the timing relationships between data,
clock and data enable. A maximum clock frequency of
250kHz is assumed:

5·220

Typical Applications

CLOCK~
OATA

"'CA"'TA"'EOOTNA""B;;-"i'LE

--~b~
MIN

too ns
MIN

1,=11" 50"S

Figure 3

36
CLOCK

START BIT 1

BIT 34 BIT 35

cyg4?ffg~~,-

__

n

LOAD _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...... · .._ _ __
UNTERNALI

n......___

UNTE:~~~1

Figure 4. Input Data Format

VF DISPLAY
AM
FM

}

Il- -,,-,
11::.7 :::1 LI
-

34---1

MM5446
DISPLAY DRIVER

KEYBOARD

COPs
ELECTRONIC TUNING
CONTROLLER

111
STATION
DETECT. ETC.

Basic Electronically Tuned Radio System

5-221

PLL
SYNTHESIZER

Display Drivers

~National

~ Semiconductor

MM5450, MM5451 LED Display Drivers
General. Description
The 5450 and MM5451 are monolithic MOS integrated
circuitl\" I,ltilizing N-channel metal-gate low threshold,
enhanc_El.rnent mode, and ion-implanted depletion mode
devices .. They are available in 40-pin molded dual-in-line
packages. A single pin controls the LED display brightness by setting a reference current through a variable
resistor connected to Voo.

• Enable (on MM5450)
.• Wide power supply operation
• TIL compatibility
• 34 or 35 outputs, 15mA sink capability
• Alphanumeric capability

Applications
• cOPS or microprocessor displays
• Industrial control indicator

Features
• Continuous brightness control

• Relay driver
• Digital clock, thermometer, counter, voltmeter.

• Serial data input
• No load signal required

• Instrumentation readouts

Block Diagram

OUTPUT 34

BRIGHTNESS
CONTROL

OUTPUT 1

--==;--......

r-....

24

18

DATOAU~~~m l==~~~l ~---.:::.t-.,
SEOR~~~ ~---.:::.t-l
CLOCK ~----'-'i--l

>------'
FIGURE 1

Connection Diagrams (Dual-In-line Packages)
OUTPUT BIT 18

VSS

OUTPUTB1T 19

OUTPUT BIT 11

OUTPUT BIT 16

OUTPUT BIT 20

OUTPUT BIT 16

OUTPUT BIT 15

OUTPUT BIT 21

OUTPUT BIT 15

OUTPUT BIT 22

OUTPUT BIT 14

OUTPUT BIT 23

OUTPUT BIT 13

OUTPUT BIT24

OUTPUT BIT 12

OUTPUT BIT 25

OUTPUTBITl1

OUTPUT BIT 26

OUTPUT BIT 10

OUTPUT BIT 21

OUTPUTBIT9

OUTPUT BIT 28

OUTPUT BIT B

OUTPUT BIT 29

OUTPUTBIT1

OUTPUT BITJO

OUTPUTBIT 6

OUTPUT BIT 31

OUTPUT BIT5

OUTPUT BIT 32

OUTPUT BIT4

OUTPUT BIT 33

OUTPUTBIT 3

VSS
OUTPUT BIT 11

36

OUTPUT BIT 14

35

OUTPUT BIT 13

34

OUTPUT BIT 12

33

OUTPUTBIT 11

32

OUTPUT BIT 10
OUTPUT BIT 9
OUTPUT BIT 8

31
MM5450

3D
29

OUTPUT BIT1

28

OUTPUT BIT6

21

OUTPUT BIT 5

26

OUTPUT BIT 4

25

OUTPUTBIT 3

24

OUTPUT BIT 2

23

OUTPUT BIT 1

22

BRIGHTNESS CONTROL

21

Voo
TOP

OUTPUT BIT 34

OUTPUT BIT 2

DATA ENABLE

'OUTPUT BIT 1

BRIGHTNESS CONTROL

DATA IN
CLOCK IN

4.
39
38
31
36
35
34
33
32
10
11

31
MM5451

3D

12

29

13

28

14

21

15

26

16
11

OUTPUT BIT 22
OUTPUT BIT 23
OUTPUTBIT 24
OUTPUTBI125
OUTPUT BIT 26
OUTPUT BI121
OUTPUT BIT 28
OUTPUTBIT 29"
OUTPUTBIT 3D
OUTPUTBIT 31

OUTPUT BIT 32

DATA IN
CLOCK IN

FIGURE 2b

5-222

OUTPUT BIT 21

OUTPUT BIT 35

20

Order Number MM5451N
See Package 24

FIGURE 2a

OUTPUT BIT 20

OUTPUT BIT 34

18
19

TOP VIEW

VI~W

OUTPUT BIT 19

OUTPUT BIT 33

Voo

Order Number MM5450N
See Package 24

OUTPUT 81T 18

I

Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Power Dissipation
Junction Temperature
Lead Temperature (Soldering, 10 seconds)

Electrical Characteristics
PARAMETER

VSS to VSS + 12V
-25°C to +85°C
--65°C to +150°C
560 mW at +85°C
1W at +25°C
+150°C
300°C

TA within operating range, VDD =4.75V to 11.0V,VSS = OV, unless otherwise specified.
CONDITIONS

Power Supply
Excluding Output Loads

Input Voltages
Logical "0" Level
Logical "1" Level

±10 /lA Input Bias
4.75~

VDD
VDD >5.25

~

5.25

Brightness Input (Note 2)

Brightness Input Voltage (Pin 19)

TYP

4.75

Power Supply Current

Output Sink Current (Note 3)
Segment OFF
Segment ON

MIN

MAX

UNITS

11

V

7

mA

--0.3
2.2
VDD -2

VDD
VDD

V
V
V

0

0.75

mA

10

IlA

10
4
25

IlA
mA
mA

0.8

VOUT= 3.0V
VOUT = 1V (Note 4)
Brightness Input = OIlA
Brightness Input = 100 IlA
Brightness Input = 750 IlA

2.0
15

Input Current = 750 /lA

0
2.7

3.0

4.3

.V

Input Clock Frequency

0

0.5

MHz

Duty Cycle

40

60

%

±20

%

50

Output Matching (Note 1)
Nola 1: Oulput matching is calculated as the percent variation from IMAX + IMIN/2.

Note 2: With a fixed resistor on the brightness input pin some variation in brightness will occur from one device to another.

Nole 3: Absolute maximum for each output should· be limited to 40m ....
Nole 4: The VOUT voltage should be regulaled by Ihe user. See Figures 6 and 7 for allowable VOUT vs. lOUT operation.

Functional Description
Both the MM5450 and the MM5451 are specifically
designed to operate 4 or 5·digit alphanumeric displays
with minimal interface with the display and the data
source. Serial data transfer from the data source to the
display driver is accomplished with 2 signals, serial
data and clock. Using a format of a leading "1" followed by the 35 data bits allows data transfer without
an additional load signal. The 35 data bits are latched
after the 36th bit is complete, thus providing non·
multiplexed, direct drive to the display. Outputs change
only if the serial data bits differ from the previous
time. Display brightness is determined by control
of the output 'current for LED displays. A 0.001 capacitor should be connected to brightness control, pin
19, to prevent possible oscillations.

Figure 4 shows the input data format. A start bit of

logical "1" precedes the 35 bits of data. At the 36th
clock a LOAD signal is generated synchronously with
the high state of the clock, which loads the 35 bits of
the shift registers into the latches. At the low state of
the clock a RESET signal is generated which clears all
the shift registers for the next set of data. The shift
registers are static master-slave configuration. There
is no clear for the master portion of the first shift
register, thus allowing continuous operation.
There must be a complete set of 36 clocks or the shift
registers will not clear.
When the chip first powers ON an internal power ON
reset signal is generated which resets all registers and all
latches. The START bit and the first clock return the
chip to its normal operation.

A block diagram is shown in Figure 1. For the MM5450
a DATA ENABLE is used instead of the 35th output.
The DATA ENABLE input is a metal option for the
MM5450. The output current is typically 20 times
greater than the current into pin 19, which is set by
an external variable resistor. There is an internal limiting
resistor of 4000. nominal value.

Figure 2 shows the pin-out ofthe MM5450 and MM5451.

Bit 1 is the first bit following the start bit and it will
appear on pin 18. A logical "1" at the input will turn
on the appropriate LED.

5-223

Functional Description

(Continued)

Figure 3 shows the timing relationships between data,
clock and data enable. A max clock frequency of 0.5 '
MHz is assumed.

where:
Tj = junction temperature +150°C max
VOUT = the voltage at the LED driver outputs
I LED = the LED current

For applications where a lesser number of outputs are
used, it is possible to either increase the current per
output, or operate the part at higher than 1 V VOUT.
The following equation can be used for calculations.

124°CIW = thermal coefficient of the package
T A = ambient temperature
The above equation was used to plofFigure 5, Figure 6,
and Figure 7.

Tj = (VOUT) (lLEO) (No. of segments) (124°CIW)+TA

FIGURE 3

CLOCK
START BIT 1

BIT 35 BIT 36

C""P'~~~$$$~

n

~O _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ' ..._ _ _ __
(INTERNAL)

n

RESET
(INTERNAL) _ _ _ _ _ _ _.....,.._ _ _- - - . . . . . , . . - - - _ . . . - - - . . .

FIGURE 4. Input Data Format

5-224

..._ _....,..._

Typical Applications
1.0

~

0.8

z
0

>=

;;:
~
0
co

~

0.6
0.4
0.2

20

40

60

80

100

TEMPERATURE (' C)

FIGURE 5

2.5
2.0

~>-

1.5

0

1.0

~

:>

110

11

1\

TA" 85°C
Ti ~ moc (MAXI

I

100

"JJ

""%c

«'~

'"
>-

z

80
70

co
co

60

E

I\~[\ J',~G'4?

";17

~

~

>-

~

>~

0

0.5

r--- ttVQUT"

90

50
40
30

'\

I'-..

10
12

16

20

24

28

o

10

-

~

15

r--.

::--

20

25

NUMBER OF SEGMENTS

ILEO (rnA)

FIGURE 6

FIGURE 7

Basic Electronically Tuned Radio System
LEO DISPLAY

AM
FM

'1-

-"~-I

11::1 ::1 LI

t -34--1
MM5450
DISPLAY
DRIVER

KEYBOARD

A=: 85"C

r--- ~VDUT-l.5V
-I 1 , - r-r--- 1\
VOUT" 2V
I\};f,r--- r--

20

o

'nr

IJ

COPs
ELECTRONIC
TUNING
CONTROLLER

111

STATION
rETECT, ETC.

5-225

PLL
SYNTHESIZER

::30

34

Typical Applications

(Continued)

Duplexing 8 Digits with One MM5450

MM5450

CLOCK IN

~

_ _ _.......J

DATA IN ~------' ......VV'......._
BRIGHTNESS
CONTROL

Voo

tOOK

TYP.

5-226

Display Drivers

~National

~ Semiconductor

MM5452, MM5453 Liquid Crystal Display Drivers
General Description
The MM5452 is a monolithic integrated circuit utilizing
CMOS metal gate, low threshold enhancement mode
devices. It is available in a40-pin molded package.The chip
can drive up t032 segments of LCD and can be paralleled to
increase this number. The chip is capable of driving a
4 1/2-digit 7-segment display with minimal interface between the display and the data source.
The MM5452 stores the display data in latches after it is
clocked in, and holds the data until new display data is
received.

• DATA ENABLE (MM5452)
• Wide power supply operation
• TTL compatibility
• 32 or 33 outputs
• Alphanumeric and bar graph capability
• Cascaded operation capability

Applications
• COPs or microprocessor displays
• Industrial control indicator

.Features

• Digital clock, thermometer, counter, voltmeter
• Serial data input

• Instrumentation readouts

• No load signal required

• Remote displays

Block and Connection Diagrams

VDD

LOAD

Z5

DATA ENABLE (MM54521

22

SERIAL
DATA

21

CLOCK

'='

FIGURE 1
Dual-ln·Line Package
Vss
P

39

OUTPUT BIT

3B

OUTPUT BIT 16

31

OUTPUT BIT 15

36

OUTPUT BIT 14

35

OUTPUT BIT 13

34

OUTPUT BIT 12

33

OUTPUT BIT 11

32

OUTPUTBIT 10
OUTPUT BIT 9
OUTPUT BIT 8

OUTPUT BIT 7
OUTPUT BIT 6
OUTPUT BIT 5
OUTPUTHIT 4
OUTPUT BIT 3
OUTPUT BIT 2

OUTPUT BIT 1
OSC IN

Dual-In-Line Package
40

10
11

31
MMS452

30

12

2'

13

18

14

27

15

26

16

25

17

24

lB

23

19

22

20

21

VOD

OUTPUT BIT "

OUTPUT BIT 17

OUTPUT BITZO

OUTPUT BIT 16

OUTPUT BIT 21

OUTPUT BIT 15

OUTPUT BIT 22

OUTPUT BIT 14

OUTPUT BIT 23

OUTPUT BIT 13

OUTPUT BIT 24

OUTPUT BIT 12

OUTPUTBIT 25

OUTP~T

OUTPUT BIT 26

OUTPUT BIT 10

OUTPUTBIT 27
OUTPUT BIT 2B
OUTPUT BIT 2'

OUTPUT BIT9
OUTPUT BIT B
OUTPUT BIT 7
OUTPUT BIT 6

OUTPUTBIT 31

OUTPUTBITS

OUTPUT BIT 32

OUTPUTBIT 4

DATA ENABLE

OUTPUT BIT 3

BACKPLANE IN

OUTPUT BIT 2
OUTPUT BIT 1

DATA IN

OSC IN

CLOCK IN

39
38
37
36
35
34
33

BIT 11

OUTPUT BIT 30

BACKPLANE OUT

40

Vss

OUTPUT BIT lB

32
10
11

31
MM5453

OUTPUT BIT 20
OUTPUT BITZI
OUTPUT BIT 22
OUTPUT BIT 23
OUTPUT BIT 24
OUTPUT BIT 25
OUTPUT BIT 26
OUTPUT BIT 27

OUTPUT BIT 29

13

OUTPUT BIT 30

14

OUTPUT BIT 31

15

OUTPUT BIT 32

16

OUTPUT BIT 33

17

BACKPlANE IN

18

13

19

11

20

21·

TOP VIEW

TOP VIEW

Order Number MM5452N
See Package 24

Order Number MM5453N
See Package 24

FIGURE 2b

5-227

OUTPUT" BIT 19

OUTPUT BIT 28

11

VDD

, FIGURE 2a

OUTPUT BIT lB

BACKPLANE OUT
DATA IN
CLOCK IN.

Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature

Vss to Vss + 10V
O·C to + 70·C
-65· to + 150·C

Power Dissipation

300mWat + 70·C
350mWat +25·C
Junction Temperature
+150·C
Lead Temperature (Soldering, 10 seconds)
300·C

Electrical Characteristics
TA within operating range, V oo =3.0V
to 10V,. Vss= OV, unless otherwise specified.
,
Parameter

Conditions

Typ

Min

Power Supply

3

Power Supply Current

Excluding Outputs
OSC= Vss , BP IN @ 32 Hz
V oo =5V, Open Outputs, No Clock

Clock Frequency

Max

Units

10

V

40
10

p.A
p.A

500

kHz

0.1 Voo
0.8

V
V

Voo
Voo

V
V

-20

p.A

Input Voltages
Logical '0' Level

-0.3
-0.3

Voo<4.75
V oo ",,4.75
V oo > 5.25
Voos5.25

Logical '1' Level

0.9 Voo
2.0

Output Current Levels
Segments
Sink

Voo= 3V, VOUT= 0,3V

Source

V oo =3V, VouT=Voo-O.3V

20

p.A

Backplane
Sink

V oo =3V, VOUT= 0.3V

Source

Voo = 3V, VOUT= Voo - 0.3V

Output Offset Voltage

-320

p.A'
p.A

±50

mV

320

Segment Load 250 pF
. Backplane Load 8750' pF

Functional Description (Continued)
Figure 4 shows the input data format. A start bit of logical
"1" precedes the 32 bits of data. At the 36th clock a LOAD
signal is generated synchronously with the high state of
the clock, which loads the 32 bits of the shift registers into
the latches. At the low state of the clock a RESET signal is
generated which clears all the shift registers for the next
set of data. The shift registers are static master·slave con·
figuration. There is no clear for the master portion of the
first shift register, thus allowing continuous operation.

The MM5452 is specifically designed to operate 4 1/2·digit
7·segment displays with minimal interface with the display
and the data source. Serial data transfer from the data
source to the display driver is accomplished with 2 signals,
serial data and clock. Since the MM5452 does not contain a
character generator, the formatting of the segment infor·
mation must be done prior to inputting the data to the
MM5452. Using a format of a leading "1" followed by the 32
data bits allows data transfer without an additional load
signal. The 32 data bits are latched after the 36th clock is
complete, thus providing non·multiplexed, direct drive to
the display. Outputs changeonly iftheserial data bits differ
from the previous time.
.

If the clock is not continuous, there mustbe a complete set
of 36 clocks otherwise the shift registers will not clear.

Figure 2a shows the pin·out of the MM5452. Bit 1 is the first
bit following the start bit and it will appear on pin 18.

A block diagram is shown in Figure 1. For the'MM5452 a
DATA ENABLE is used instead of the 33rd output. If the
DATA ENABLE signal is not required, the33rd output can be
brought out.This is the MM5453 device.

, Figure 3 shows the timing relationships between data,
clock and DATA ENABLE.

CLDCK~

. --"';'-)1'==Joons
DATA

DATA ENABLE'

MIN.

-'

--lOOns
MIN
TIME-

.

n'-_____

L~

(INTERNAL) ----------..;!!~I-....;.-------'
~ESET

nL____

(INTERNAL) ,....----------I'~I-,....,....---~.,--....
--'-'TIME

FIGURE.3

FIGURE 4. Input Data Format

.5-228

Functional Description (Continued)
are controllable. This application assumes a specific
display pinout. Different display/driver connection pat·
terns will, of course, yield a different input data format.

Figure 5 shows a typical application. Note how the input
data maps to the output pins and the display. The MM5452
and MM5453 do not have format restrictions, as ali outputs
Segmen t Identification

l~/b

'l~J.
d

II

I
BP

Gl

Fl

AT

61 G2 f2 A2 82 G3 F3 A3 B3 G4 F4

r

I l-I l-I l-I l-I

A4

I./~/./~/./~./~I

1 DP El 01 ClOP E2 02 C2 DP E3 03 C3 DP E4 04 C4 B4

~

L

-

--

....Vss

lB
19

16

20

15

21

'----14

E-IE-

13
12

24

11

25

10

26
27

9

t

'---

-=

17

B

-

'--'---

MM5453

2B

7

29

6

30

5

31

4

32

3

BACKPLANE OUT

2

BACKPLANE IN

1

33

T

DATA IN

DSC IN

.!:!;DCK IN

,,--L 470 pF

DATA FORMAT
TlME-lEFT END

"*

v+

POINT

4TH
DECIMAL
POINT

j

j

JRD

2ND
DECIMAL
POINT

DECIMAL

IA41

Consult LCD manufacturer's data sheet for specific pinouts

B41 C41 041 E41 F41 G41

FIGURE 5. Typical 4V2·Digit Display Application

5-229

NUllS

I

Functional Description

(Continued)

FigureBshows a four wire remote display that takes advantage of the device's serial. input to move .maflY bits of
display information on a few wires.
'
Using an External Clock

Deviations from a 50 % duty cycle result in an offset voltage
onthe LCD. In Figure 7,a flipflopisusedtoassurea50% duty cycle. The oscillator input is grounded to prevent oscillation and reduce current consumption in the chips. The
oscillator is not used.

The MM5452, MM5453 LCD Drivers can be used with an externally supplied clock, provided it has a duty cycle of 50%.

DISPLAY

BACKPLANE

BP
OSC OUT

IN
C'

BP

IN

T~""""
* The minimum recommended value for R fortheoscill~tor input is9 kn. An RC time constant of approximately
,4.91 x 10 - 4 should produce a backplane frequency between 30 Hz and 150 Hz.

FIGURE 6. Parallel Backplane Outputs

DISPLAY

BACKPLANE

BP
OUT
OSC
IN

2 X BACKPLANE _ ................
DRIVE FREQUENCY
CK

FIGURE 7. External Backplane Clock

5-230

BP
IN

Functional Description

(Continued)

Using an external clock allows synchronizing the display
drive with AC power, internal clocks, or DVM integration
time to reduce interference from the display.

The next clock pulse increments the staircase and clocks
the new data in.
With a buffer amplifier, the same staircase waveform can
be used for many displays. The digital·to·analog con·
verter need not be linear; logarithmic or other non·linear
functions can be displayed by using weighted resistors
or special DACs. This system can be used for status in·
dicators, spectrum analyzers, audio level and power
meters, tuning indicators, and other applications.

Figure 9 is a general block diagram that shows how the
device's serial input can be used to advantage in an
analog display. The analog voltage input is compared
with a staircase voltage generated by a counter and a
digital·to·analog converter or resistor array. The result of
this comparison is clocked into the MM5452, MM5453.

DISPLAY

l-' l-llll-1

I~./~/./~./~I
~

DATA

BYPASS-~
CAPACITOR -

11

~
Voo

DATA IN

GNE

BP OUT

BP IN

r

C~OCK

CLOCK IN

~

VSS

OSC IN

t

V-

R

~C

FIGURE 8. Four Wire Remote Display

LCD BAR GRAPH OISPLAY

11111000000

ANALOG VOLTAGE IN

BACKPLANE
COUNT
CLOCK

BP OUT
CLOCK

LOW TO SET
START BIT

Data is high until staircase>input

FIGURE 9. Analog Display

5·231

VOO

~ '?A National

Display Drivers

~ ~ Semiconductor

:E

MM5480 LED Display Driver
General Description
The 5480 is a monolithic MOS integrated circuit utilizing
N-channel metal gate low threshold, enhancement mode
and ion-implanted depletion mode devices. It utilizes
the MM5451 die packaged in a 28-pin package making it
ideal for a 3'12 digit display. A single pin controls the
LED display brightness by setting a reference current
through a variable resistor connected either to VDD or to
a separate supply of 11V maximum.

• Wide power supply operation
• TTL compatibility
• Alphanumeric capability

• 3'12 digit displays

Applications
• COPS or microprocessor displays

Features

• Industrial control indicator

• Continuous brightness control

• Relay driver
• Digital clock, thermometer, counter, voltmeter

• Serial data input
• No load signal required

• Instrumentation readouts

Block Diagram
BRIGHTNESS
CONTROL

VDD

OUTPUT 23

OUTPUT 1

...---+---::-::::-:-::--...

Figure 1

Connection Diagram

(Dual-In-Line Packages)
28
27
26
25
24

Vss
OUTPUT BIT 11
OUTPUT BIT 10
OUTPUT BIT
OUTPUT BIT
OUTPUT BIT
OUTPUT BIT

9
8
7
6

4

OUTPUT BIT
OUTPUT BIT
OUTPUT BIT
OUTPUT BIT
OUTPUT BIT

5
4
3
2
1

8

BRIGHT. CONT.
VDD

5480

. 9
10
11
12
13
14

16
15

Order Number MM5480N
See Package 23

Figure 2

5-232

OUTPUT BIT 12
OUTPUT BIT 13
OUTPUT BIT 14
OUTPUT BIT 15
OUTPUT BIT 16
OUTPUT BiT 17
OUTPUTBIT 18
OUTPUT BIT 19
OUTPUT BIT 20
OUTPUT BIT 21
OUTPUT BI122
OUTPUT BIT 23
OATA IN
CLOCK

Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Power Dissipation
Junction Temperature
Lead Temperature (Soldering, 10 seconds)

Electrical Characteristics
Parameter

Vss to Vss + 12V
-25'Cto +85'C
-65'Cto +150'C
490mWat +85'C
940mWat +25'C
+150'C
300'C

TAwithin operating range, Voo = 4.75 to 11.0V, Vss = OV, unless otherwise specified.
Min.

Conditions

Power Supply
Power Supply Current
Input Voltages
Logical "0" Level
Logical "1" Level

±lOI'A Input Bias
4.75 " Voo " 5.25
Voo> 5.25

Brightness Input Voltage (Pin 13)

Max.

Units

11.0

V

7.0

mA

-0.3
2.2
Voo-2

0.8
Voo
Voo

V
V
V

0

0.75

mA

10.0

I'A

10.0
4.0
25.0

I'A
mA
mA

Excluding Output Loads

Brightness Input (Note 2)
Output Sink Current (Note 3)
Segment OFF
Segment ON

Typ.

4.75

VouT=3.0V
VOUT = 1V (Note 4)
Brightness Input = OI'A
Brightness Input = lOOI'A
Brightness Input = 75Ol'A

0
2.0
15.0

Input Current = 75Ol'A

2.7

3.0

4.3

V

Input Clock Frequency

0

0.5

MHz

Duty Cycle

40

60

%

±20

%

Output Matching (Note 1)

50

Note 1: Output matching is calculated as the percent variation from IMAX + IMIN/2.
Note 2: With a fixed resistor on the brightness input pin some variation in brightness will occur from one device to another.
Note 3: Absolute maximum for each output should be limited to 40mA
Note 4: The VOUT voltage should be regulated by the user.

Functional Description
The MM5480 is specifically designed to operate 3'12-digit
alphanumeric displays with minimal interface with the
display and the data source. Serial data transfer from
the data source to the display driver is accomplished
with 2 signals, serial data and clock. Using a format of a
leading "1" followed by the 35 data bits allows data
transfer without an additional load signal. The 35 data
bits are latched after the 36th bit is complete, thus providing non-multiplexed, direct drive to the display. Outputs change only if the serial data bits differ from the
previous time. Display brightness is determined by control of the output current for LED displays. A 0.001 capacitor should be connected to brightness control, pin 13,
to prevent possible oscillations.

isters for the next set of data. The shift registers are
static master-slave configuration. There is no clear for
the master portion of the first shift register, thus allowing continuous operation.
There must be a complete set of 36 clocks or the shift
registers will not clear.
When the chip first powers ON an internal power ON
reset signal is generated which resets all registers and
all latches. The START bit and the first clock return the
chip to its normal operation.
Figure 5 shows the Output Data Format for the 5480.
Because it uses only 23 of the possible 35 outputs, 12 of
the bits are 'Don't Cares'.

A block diagram is shown in Figure 1. The output current
is typically 20 times greater than the current into pin 13,
which is set by an external variable resistor. There is an
internal limiting resistor of 400Q nominal value.

Figure 3 shows the timing relationships between data,
clock, and data enable. A maximum clock frequency of
0.5 MHz is assumed.
For applications where a lesser number of outputs are
used, it is possible to either increase the current per
output, or operate the part at higher than lV VOUT. The
following equation can be used for calculations.

Figure 4 shows the input data format. A start bit of logical "1" precedes the 35 bits of data. At the 36th clock a
LOAD signal is generated synchronously with the high
state of the clock, which loads the 35 bits of the shift
registers into the latches. At the low state of the clock a
RESET signal is generated which clears all the shift reg-

Ti = (VOUT) (I LED) (No. of segments) (132'C/W) + TA

5-233

Functional Description

(Continued)

where:
Tj = junction temperature + 150°C max.
VOUT = the voltage at the LED driver outputs
ILED = the LED current

132°C/W = thermal coefficient of the package
TA = ambient temperature

Figure 3

36
CLOCK

n

LOAD _ _ _ _ _ _ _ _ _ _ _---"_ _ _ _ _ _ _..
(INTERNAL)

1.._ _ _ __

·n'-___

RESET _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _......
(INTERNAL)
•

Figure 4. Input Data Format

Figure 5. Output Data Format .

1_7:1
II IL
_I

CLOCK

DATA

Basic 3 Y. Digit Interface

5·234

_

~National

Display Drivers

~ Semiconductor

MM5481 LED Display Driver
General Description
The 5481 is a monolithic MaS integrated circuit utilizing
N-channel metal gate low threshold, enhancement mode
and ion-implanted depletion mode devices. It utilizes
the MM5450 die packaged in a 20-pin package making it
ideal for a 2 digit display. A single pin controls the LED
display brightness by setting a reference current through
a variable resistor connected either to Voo or to a separate supply of 11V maximum.

• Wide power supply operation

Features

Applications

• Continuous brightness control

• COPS or microprocessor displays
• Industrial control indicator

• TTL compatibility
• Alphanumeric capability
• 2 digit LED driver

• Serial data input
• No load signal required

• Relay driver
• Instrumentation readouts

• Data enable

Block Diagram
VDD

OUTPUT 14

OUTPUT 1

BRIGHTNESS
CONTROL

Figure 1

Connection Diagram
(Dual-In-Line Package)

OUTPUT BIT8
OUTPUT BIT7
OUTPUT BIT 6
OUTPUT BIT 5
OUTPUTBIT4
OUTPUT BIT 3
OUTPUT BIT 2
OUTPUT BIT 1

20
19

5481

VSS

12
11

BRIGHT CONTR.

Voo

OUTPUT BIT 9
OUTPUT BIT 10
OUTPUT BIT 11
OUTPUT BIT 12
OUTPUT BIT 13

10

Top View
Order Number MM5481N
See Package 20A
Figure 2

5-235

OUTPUT BIT 14
DATA ENABLE
DATA IN
CLOCK

Absolute. Maximum Ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Power Dissipation
Junction Temperature
Lead Temperature (Soldering, 10 seconds)

Electrical Characteristics
Parameter

Vss to Vss + 12V
-25·Cto +85·C
-65·Cto +150·C
450mWat +85·C
860mWat +25·C
+150·C
300·C

TA within operating range, Voo =4.75 to 11.0V, Vss =OV, unless otherwise specified.
Conditions

Min.

Power Supply
Power Supply Current
Input Voltages
Logical "0" Level
Logical "1" Level

4.75
Excluding Output Loads
-0.3
2.2
Voo-2

±10"A Input Bias
4.75 .. Voo" 5.25
Voo> 5.25

Brightness Input (Note 2)
Output Sink Current (Note 3)
Segment OFF
Segment ON

Brightness Input Voltage (Pin 9)

Typ.

0
VouT=3.0V
VOUT= 1V (Note 4)
Brightness Input = O"A
Brightness Input = 100 "A
Brightness Input = 750"A

0
2.0
15

Input Current = 750 "A

2.7

Max.

Units

11

V

7

mA

0.8
Voo
Voo
0.75

V
V
V
mA

10

"A

10
4.0
25

"A
mA
mA

3.0

4.3

V

Input Clock Frequency

0

0.5

MHz

Duty Cycle

40

60

%

±20

%

Output Matching (Note 1)

50

Note 1: Output matching is calculated as the percent variation from IMAX + IM1N i2.
Note 2: With a fixed resistor on the brightness input pin some variation in brightness will occur from one device to another.
Note 3: Absolute maximum for each output should be limited to 40mA
Note 4: The VOUT voltage should be regulated by the user.

Functional Description
registers into the latches. At the low state of the clock a
RESET signal is generated which clears all the shift registers for the next set of data. The shift registers are
static master-siave configuration. There is no clear for
the master portion of the first shift register, thus allowing continuous operation.

The MM5481 uses the 5450 die which is packaged to
operate 2·digit alphanumeric displays with minimal in·
terface with the display and the data source. Serial data
transfer from the data source to the display driver is accomplished with 2 Signals, serial data and clock. Using
a format of a leading "1" followed by the 35 data bits
allows data transfer without an additional load signal.
The 35 data bits are latched after the 36th bit is complete,
thus providing non-multiplexed, direct drive to the display. Outputs change only if the serial data bits differ
from the previous time. Display brightness is determined
by control of the output current for LED displays. A 0.001
capacitor should be connected to brightness control, pin
9, to prevent possible oscillations.

There must be a complete set of 36 clocks or the shift
registers will not clear.
When the chip first powers ON an internal power ON
·reset signal Is generated which resets all registers and
all latches. The START bit and the first clock return the
chip to its normal operation.
Figure 5 shows the Output Data Format for the 5481.
Because it uses only 14 of the possible 34 outputs, 20 of
the bits are 'Don't Cares'. Note that only alternate groups
of 4 outputs are used.

A block diagram is shown in Figure 1. The output current
is typically 20 times greater than the current into pin 9,
which is set by an external variable resistor. There is an
internal limiting resistor of 400Q nominal value.

Figure 3 shows the timing relationships between data,
clock, and data enable. A maximum clock frequency of
O.5MHz is assumed.

Figure 4 shows tl\,e input data format. A start bit of logical "1" precedes the 35 bits of data. At the 36th clock a
LOAD signal is generated synchronously with the high
state of the clock, which loads the 35 bits of the shift

5-236

Functional Description

(Continued)

For applications where a lesser number of outputs are
used, it is possible to either increase the current per
output, or operate the part at higher than 1V VOUT. The
following equation can be used for calculations.

CLOCK

--I)Kr--------

Tj = (VOUT) (lLEO) (No. of segments) (145'C/W) + TA

OATA _ _ _ _ _ _ _

~11-i,1~~ns

where:
Tj = junction temperature + 150 'C max.
VOUT = the voltage at the LED driver outputs
ILEO = the LED current
145 'C/W thermal coefficient of the package
TA = ambient temperature

DATA ENABLE

---------~\

=

1.....-------

Figure 3

36
CLOCK
START

BIT 1

BIT 34 BIT 35

~~~~~

n
n

LOAO _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _......
(INTERNAL)

'--_ _ _ __

RESET _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- '
(INTERNAL)

Figure 4. Input Data Format

Figure 5. Output Data Format

Basic Electronically Tuned Television System

5·237

L _ _ __

,...

~ ~National

Display Drivers

~ ~ Semiconductor
~

MM58201Muitiplexed LCD Driver
General Description

Features

The MM58201 is a monolithic CMOS LCD driver capable of
driving up to 8 backplanes and 24 segments. A 192-bit
RAM stores the data for the display. Serial input and output pins are provided to interface with a controller. An RC
oscillator generates the timing necessary to refresh the
display. The magnitude of the driving waveforms can be
adjusted with the V TC inputto optimize display contrast.
Four additional bits of RAM allow the user to program the
number of backplanes being driven, and to designate the
driver as either a master or slave for cascading purposes.
When two or more drivers are cascaded, the master chip
drives the backplane lines, and the master and each slave
chip drive 24 segment lines. Synchronizing the cascaded
drivers is accomplished by tying the RC OSC pins together
and the BP1 pins together.

• Drives up to 8 backplanes and 24 segment lines
• Stores data for display

The MM58201
package.

• Cascadable
• Low power
• Fully static operation

Applications
• Dot matrix LCD driver
• Multiplexed 7-segment LCD driver
• Serial in/serial out memory

is packaged in a 40·lead dual·in·line

Block Diagram

Connection Diagram

BACKPLANE
OUTPUTS

Dual·ln-Line Package
40

Sl1

39

SID

38

S9

37

S8

36

ST

35

S6

34

S5

33

S4
S3
RC
OSC

S2
SI
BP8
BPT
BP6
BP5
BP4
BPJ
BP2
BPI
VSS

32
10

31

11

30

12

DATA
OUT

FIGURE 1

5-238

S15
S16
SIT
S18
S19
S2D
S21

S24

15

VTC

16

os

17

CLK IN

18

DATA IN

19
20

21

FIGURE 2

DATA
IN

S14

S2J

14

TOP VIEW

CLK IN

S13

S22

13

Order Number MM58201N
See Package 24

CS

VDD
S12

DATA OUT
RC OSC

Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature Range
Storage Temperature Range
Package Dissipation
Operating V DD Range
Lead Temperature (Soldering, 10 seconds)

Vss - 0.3V to Vss + 18V
O°C to 50°C
- 65°C to + 150°C
500 mW
Vss + 9.0V to Vss + 18.0V
300°C

DC Electrical Characteristics Minimax limits apply across temperature range unless otherwise noted.
Parameter

Conditions.

Icc

Supply Current

V DD =18V

VIN(1 )

Logical "1" Input Voltage

V DD =9V
V DD = 15V

Min

Typ

Max

Units

0.25

mA

4.0
6.5

VINIO)

Logical "0" Input Voltage

VOUTIO)

Logical "0" Output Voltage

IS)NK = 2.5 mA

IOUT(1)

Logical "1" Output Current

V DO =18V

IIN(1)

Logical "1" Input Current

VIN = 18V

IINIOI

Logical "0" Input Current

VIN=OV

Vrc

Input Voltage

4.5

Vrc

Input Impedance

15

Zour

Output Impedance

Backplane and Segment
Outputs

DC Offset Voltage

Between Any Backplane
and Segment Output

V
V
1.0

0

V

0.4

V

±10

p.A

1.0

p.A

-1.0

p.A
V

0

30

kn

12.5

kn

±10

mV

AC Electrical Characteristics TA and Voo within operating range unless otherwise noted.
Parameter

.

Conditions

Min

Typ

Max

Units

losc

Oscillator Frequency

128~

400~

IClK IN

Clock Frequency

DC

275

tON

Clock Pulse Width

1.8

tOFF

Clock OFF Time

1.8

P.s

ts

Input Data Set-Up Time

200

ns

Hz
kHz
ItS

tH

Input Data Hold Time

100

ns

t ACC

Access Time

1.0

ItS

I,

Rise Time

Backplane, Segment Outpuls
C L = 2000 pF

60

ItS

If

Fall Time

Backplane, Segmenl Outputs
C l =2000 pF

60

ItS

• 11 IS

the number of backplanes programmed.

5-239

,...

~

Switching Time Waveforms

an

:IE
:IE
~-------tON------~

ClK IN

DATA IN.

CS

DATA OUT

VALID

VALID

Backplane Output

Segment Output

0.68VTC

~11t:2_~." .

0.32 VTC - - - - -

Functional Description'
A block diagram of the MM58201 LCD driver is shown in
Figure 1. A connection diagram is shown in Figure 2.

allows the controller to operate at a lower supply voltage,
and also permits the DATA OUT output to be wired in
parallel with the DATA OUT outputs from any other drivers
in the system.

Serial Inputs and Output
A negative-going edge on the CS input initiates a frame.
The CS input must stay low for one rising edge of ClK IN,
however it may not be pulsed low more than once in 31
clocks. At least one clock must occur while CS is high.

To program the number of· backplanes being driven and
the MIS bit, load address 11000, a write bit, three bits for
the number of backplanes (Table I), and the MIS bit. The remaining 20 data bits will be ignored but it is necessary to
provide 21 more clocks before initiating another frame.

CLK IN latches data from the DATA IN input"on its rising
edge. Data from the DATA OUT pin changes on the falling
edge of ClK IN and is valid before the next rising edge.

TABLE I. BACKPLANE SELECT

The first five bits of data following CS are the address bits
(Figure 3). The address selects the column where the
operation is to start. Bit 1 is the MSB and bit 5 is the lSB.
The sixth oit is the readlwrite bit. A logic "1" specifies a
read operation and a logic "0" specifies a write operation.
The next 24 bits are the data bits. The first data bit cor·
responds to the BP1 row of the display, the second data bit
to the BP2 row, and so on. After the eighth and sixteenth
data bits, the column pointer is incremented. When start·
ing address 10110 or 10111 is specified, the column pointer
increments from 10111 to 00000.

Numberof

Backplanes
2
3
4
5
6
7
8

The DATA OUT output is an open drain N·channel device to
Vss (Figure 4). With an external pull·up this configuration

5-240

B2

B1

BO

a
a
a

a

1
0
1
0
1
0
1

1
1
1
1

1
1
0
0
1
1

Functional Description
RC

(Continued)

asc Pin

This oscillator generates the timing required for multiplexing the liquid crystal display. The oscillator operates at a
frequency that is 4~ times the refresh rate of the display,
where ~ is the number of backplanes programmed. Since
the refresh rate should be in the range from 32 Hz to
100 Hz, the oscillator frequency must be:

The voltage source on the VTC input must be of relatively
low impedance since the input impedance of VTC ranges
from 15 k!l to 30 kll. A suitable circuit is shown in Figure 5.
In a standby mode, the VTC input can be set to Vss. This
reduces the supply current to less than 250 itA per driver.

128~ :5 f asc:5 400~

Backplane and Segment Outputs

The frequency of oscillation is related to the external R
and C components in the following way:
fosc =

1
1.25RC

Connect the backplane and segment outputs directly to
the LCD row and column lines. The outputs are designed
to drive a display with a total ON capacitance of up to
2000 pF.

± 30%

The value used for the external resistor should be in the
range from 10 kll to 1 Mil.

The output structure consists of transmission gates
tapped off of a resistor divider driven by VTC (Figure 6).

The value used for the external capacitor should be less
than 0.02 1tF.
VTC Pin

A critical factor in the lifetime of an LCD is the amount of
DC offset between a backplane and segment signal.
Typically, 50 mV of offset is acceptable. The MM58201
guarantees an offset of less than 10 mV.

The VTC pin is an analog input that controls the contrast of
the segments on the LCD. If eight backplanes are being
driven (~= 8), a voltage of typically 8V is required at 25°C.
The voltage for optimum contrast will vary from display to
display. It also has a significant negative temperature
coefficient.

The BP1 output is disabled when the MIS bit is set to zero.
This allows the BP1 output from the master chip to be connected directly to it so that synchronizing signals can be
generated. Synchronization occurs once each refresh
cycle, so the cascaded chips are assured of remaining
synchronized.

cs
eLK IN

DATA IN

OON'T CAR'

1

A4

AJ

A2

Al

AD

R/W

OATA OUT

Sl

S2

SJ

S4

S5

S8

1 02

OJ

022

02J

1

01

02

OJ

022

02J

S18

024

1

S15

09

017

82

BP2

02

010

018

811

S19

S20

DON'T CARE

S14

S12

S17

1

01

S11

S16

1

024

SlJ

S9

S10

01

BPl

S6

S7

1

S21

522

S2J

524

-,
1
~
~

I

BPJ

OJ

011

019

BO

8P4

04

012

020

MIS I

BP5

05

01J

021

BP6

06

014

022

BP7

07

015

02J

8P8

08

016

024

0
1
1
0
0

0
1
1
0
1

0
1
1
1
0

~

J

A4
AJ
A2
Al
AO

0
0
0
0
0

0
0
0
0
1

0
0
0
1
0

0
0
0
1
1

0
0
1
0
0

0
0
1
0
1

0
0
1
1
0

0
0
1
1
1

0
1
0
0
0

0
1
0
0
1

0
1
0
1
0

0
1
0
1
1

0
1
1
1
1

1
0
0
0
0

1
0
0
0
1

1
0
0
1
0

1
0
0
1
1

1
0
1
0
0

1
0
1
0
1

Diagram above shows where data will appear on display if starling address 01100 is specified in data format

FIGURE 3_ Data Format'

5-241

1
0
1
1
0

1
0
1
1
1

1
1
0
0
0

Functional Description

(Continued)

FIGURE 4. DATA OUT Structure

15V
COP420L
DO

CS
15V

CLK
IN

15V

DATA
IN

D1

SK

CS

CLK
IN

SO

SI

DATA DATA
IN
DUT

JJk

MM58201

RC OSC.

RC OSC

VSS

-

MM58201

VDD

~O.o1P.F

Vss

S1-S24

S1-S24

8 x 48 DOT MATRIX
LIQUID CRYSTAL DISPLAY

FIGURE 5. Typical

~pplication

VTC
SELECT

1
t

L8ACKPLANE DR'
tlSEGMENTOUTPUT

l

SELECT

FIGURE 6. Structure of LCD Outputs

5·242

-

Oscillators

~National

Oscillators

~ Semiconductor
MM5368 CMOS Oscillator Divider Circuit
General Description

Features

The MM5368 is a CMOS integrated circuit generating
50 or 60 Hz, 10Hz, and 1 Hz outputs from a 32 kHz
crystal (32,768 Hz). For the 60 Hz selected output the
input time base is divided by 546.133, for the 50 Hz
mode it is divided by 655.36. The 50/60 Hz output is
then divided by 5 or 6 to obtain a 10Hz output which
is further divided to obtain a 1 Hz output. The 50/60 Hz
select input can be floated for a counter reset.

•

50/60 Hz output

•
•
•
..

1 Hz output
10Hz output
Low power dissipation
Fully static operation

•
•
•

Counter reset
3V -15V supply range
On-chip oscillator - tuning and load capacitors
are the only required external components besides
the crystal. (For operation below 5V it may be
necessary to use an ~ 1 MQ pullup on the oscillator
output to insure start-up. I

Block Diagram
OSC
IN

6

-----L.c v SS
1M

OSC
OUT

lOOk

5

r

8PF

DECODE
&
SELECT
LOGIC

1.--------.....----4 ~~~~~;
3

10 Hz
OUTPUT

4

1Hz
OUTPUT

COUNTER RESET
ION·CHIPI

FIGURE 1

Connection Diagram
Dual-In-Line Package
50/60 Hz OUT

50/60 Hz SELECT

VSS

10 Hz OUTPUT

OSC IN

1 Hz OUTPUT

OSC OUT

TOP VIEW

Order Number MM5368N

See Package 17
FIGURE 2. Pin-Out

5-245

Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Maximum VDD Voltage
Operati ng V D D Range
Lead Temperature (Soldering, 10 seconds)

-0.3V to VDD + 0.3V
OU C to +70°C
-65°C to +150°C
16V
3V~VDD~ 15V
300°C

Electrical Characteristics
T A within operating range, VSS = OV
PARAMETER

MIN

CONDITIONS

TYP

MAX

:UNITS

Quiescent Current Drain

VDD = 15V; 50/60 Select Floating

10

Jl.A

Operating Current Drain

fiN = 32 kHz, VDD = 3V

50

Jl.A

fiN = 32 kHz, VDD = 15V

1500

VDD = 3V

64

kHz

VDD = 15V

500

kHz

-400

/1A

Maximum Input Frequency

Output Current Levels

/1A

VDD = 5V

Logical "1 ", Source

VOH = VSS + 2.7V

Logical "0", Sink

VOL = VSS + O.4V

400

Jl.A

VDD = 9V
Logical "1 ", Source

VOH = VSS + 6.7V

Logical "0", Sink

VOL = VSS + O.4V

Input Current Levels

-1500
1500

Jl.A
Jl.A

50/60 Select Input

Logical "1" (lIH)

VDD = 3V, VIN ~0.9VDD

50

Jl.A

Logical "1" (IIH)

VOD = 15V, VIN ~0.9VOO

3

mA

Lqgical "0" (IlL)

VDD = 3V, VIN ~ O.lVDD

20

Jl.A

Logical "0" (11Ll

VDD = 15V, VIN ~O.lVDD

1

mA

Functional Description

(Figure 1)

The MM5368 initially divides the input time base by
256. From the resulting frequency (128 Hz for 32 kHz
crystal) 8 c10ck periods are dropped or eliminated during.
60 Hz operation and 28 clock periods are eliminated
during 50 Hz operation. This frequency is then divided
by 2 to obtain a 50 or 60 Hz output. This output is not
periodic from cycle to cycle; however, the waveform
repeats itself every second. Straight divide by 5 or 6 and
10 are used to obtain the 10 Hz output and the 1 Hz
outputs.
The 60Hz mode is obtained by tying pin 7 to VDD. The
60 Hz output waveform can be seen in Figure 3. The 10
Hz and 1 Hz outputs have an approximate 50% duty

5-246

cycle. In the 50 Hz mode the 50/60 select input is tied
to VSS. The 50 Hz output waveform can be seen in
Figure 3. The 10 Hz output has an approximate 40%
duty cycle arid the 1 Hz output has an approximate 50%
duty cycle.

For the 50/60 Hz select input floating, the counter chain
is held reset, except for the initial toggle flip-flop which
is needed for the reset function. A reset may also occur
when the input is switched (Figure 4). To insure the
floating state, current sourced from the input must be
limited to 1.0 Jl.A and current sunk by the input must
be limited to 1.0 Jl.A for VDD = 3V.

Timing Diagrams

60 Hz
OUTPUT

L(
,, :-(
,

:

PHASE SHIFTED EVERY 8 CLOCKS DUE TO
ELIMINATION OF 1 INPUT CLOCK (Le., 128 Hz CLOCK)

l~

1.8ms-\

:

i

50 Hz
OUTPUT

1 CLOCK DROPPED

rEVERY 5128 H, ClOCKS

L(

PHASE SHIFTED J TIMES/SEC
DUE TO ELIMINATION OF J
128 Hz CLOCKS

FIGURE 3. 50/60 Hz Output
Voo
16kHz

INPUT~
~ESET

...JnL.__--InL..__--'

RESET _ _ _

SO/50
SELECT

50/60
SElECT

FIG U R E 4. 50/60 Select and Reset

Typical Applications
RESET

VOO

LATCH

13

8 \Iss
.--_--1>-____...;'''i

NSB7861

R* 5 os!: SO/BO

.------""1 OSC IN

Vss
11

10

a

1 -_ _ _-j
L

* If the crystal used is a microwatt type an A value will
be required to limit power to the crystal.
3V
5V
10V

R = 0
R=100K
R = 330K

FIGURE 5.10 Minute (9:59.9) Timer

.-----<1..-"'"

VOD
osc Dur
50/60

HI~-----------......;2"i'
Torv

MM5J68
10Hz J

, H,

Vss

/-'INI,.......,

19 SET HRS

4

./'"""'l""'",- VIDEO CIRCUIT

18 SETMOS

16

50/60

23

SELECT

11

MMS8'D6

t--et;;r::::;:1::;:.: ~V
J

CHA~~~~

t-....~¥;"-tHORIZ
{

11

12

t-_"'O:w\r-- VERT
21
DIGIT
SELECT

FIGURE 6. TV Time/Channel Display

5-247

VERT

RETRACE

~National

Oscillators

~ Semiconductor
MM5369 Series 17 Stage
Oscillator/Divider
General Description

Features

The MMS369 is a CMOS integrated circuit with 17
binary divider stages that can be used to generate a
precise reference from commonly available high frequency quartz crystals_ An internal pulse is generated
by mask programming the combinations of stages 1
through 4,16 and 17 to set or reset the individual stages.
The MMS369 is advanced one count on the positive
transition of each clock pulse. Two buffered outputs
are available: the crystal frequency for tuning purposes
and the 17th stage output. The MMS369 is available
in an 8-lead dual-in-line epoxy package.

•

Crystal oscillator

•

Two buffered outputs
Output 1 crystal frequency
Output 2 full division

•

High speed (4 MHz at VDD

•

Wide supply range 3-1SV

•
•

Low power
Fully static operation

•
•

8 lead dual-in-line package
Low cu rrent

= 10V)

Options
•

MMS369AA

•

MMS369EYR

3.S8 MHz td 60 Hz
3.S8 MHz to SO Hz

•

MMS369EST

3.S8 MHz to 100 Hz

Connection Diagram

Block Diagram

Dual-in-Line Package

voo

I,

TUNER
OUTPUT

osc OUT

OSC IN

6

1

5

osc OUT

.--

t--

DIVIDER
OUTPUT

1

DIVIDER

1

vss

3
NC

I'

NC

OUTPUT

TOPVIEW

Order Number MM5369AA/N,
MM5369EYR/N, MM5369EST/N
See Package 17
FIGURE 1

FiGURE 2

5-248

Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Package Dissipation
Maximum VCC Voltage
Operating VCC Range
Lead Temperature (Soldering, 10 seconds)

-0.3V to VDD +0.3V
O°C to +70°C
-65°C to +150°C
500mW
16V
3V to 15V
300°C

Electrical Characteristics
T A within operating temperature range, VSS

= GND, 3V S VDD S

PARAMETER

15V unless otherwise specified.

CONDITIONS

MIN

Quiescent Current Drain

VDD

= 15V

Operating Current Drain

VDD

= 10V, fiN = 4.19 MHz

Frequency of Oscillation

VDD
VDD

= 10V
= 6V

VDD

= 10V

Output Current Levels

Vo

TYP

MAX
10

1.2

UNITS
IlA

2.5

mA

DC

4.5

MHz

DC

2

MHz

= 5V

Logical "1" Source

500

IlA

Logical "0" Sink

500

IlA

Output Voltage Levels

= 10V
= lallA

VDD
10

Logical "1"

V

9.0

Logical "0"

1.0

V

Functional Description
A connection diagram for the MM5369 is shown in
Figure 1 and a block diagram is shown in Figure 2.

DIVIDER
A pulse is generated when divider stages 1 through 4, 16
and 17 are in the correct state. By mask options, this
pulse is used to set or reset individual stages of the
counter. Figure 4 shows the relationship between the
duty cycle and the programmed modulus.

TIME BASE
A precision time base is provided by the interconnection
of a 3,579,545 Hz quartz crystal and the RC network
shown in Figure 3 together with the CMOS inverter/
amplifier provided between the OSC IN and the OSC
OUT terminals. Resistor R lis necessary to bias the
inverter for class A amplifier operation. Capacitors Cl
and C2 in series provide the parallel load capacitance
required for precise tuning of the quartz crystal.

OUTPUTS
The Tuner Output is a buffered output at the crystal
oscillator frequency. This output is provided so that the
crystal frequency can be obtained without disturbing the
crystal oscillator. The Divide Output is the input fre·
quency divided by the mask programmed number. Both
outputs are push· pull outputs. A typical application of
the MM5369 is shown in Figure 5.

The network shown provides> 100 ppm tuning range
when used with standard crystals trimmed for CL =
12 pF. Tuning to better than ±2 ppm is easily ob·
tainable.

5-249

!

Functional Description

(Continued)

Lt)

:E
:E

110
100
90
-OSCOUT

OSCIN-

~

E

'OM

*"'1k

W

;;

40

C>

0

C
C2
JDpF

/

)0
60
50

i:;

AI

I

ao

.--

30
ZO
10

o
"To be selected based on xtal used

o

10

ZO

--

30

,/

,/

40

50

,/

60

)0

uUTY CYCLE (%1

FIGURE 4. Plot of Divide·By vs Duty Cycle

FIGURE 3. Crystal Oscillator Network

FIGURE 5. Typical Application

Z.5

,,-

Z.O

u

1.5

V

l;l
C>
C>

1.0
0.5

I--

- ..

,,
V

,.." Vuu -10V

,

../'

,

.-J

b-

26.875

COUNTS

---i-----

32,714

COUNTS

==i.I

1--------59,659COUNTS-------i

~ ~- " Vuu' 5V

~I'""

MHz

FIGURE 6. Typical Current Drain vs Oscillator Frequency

FIGURE 7. Output Waveform for Standard MM5369AA

5·250

~National

Oscillators

~ Semiconductor
MM53107 Series 17·Stage Oscillator/Divider
General Description

Features

The MM53107 is a low threshold voltage CMOS
integrated circuit with 17 binary divider stages that can
be used to generate a precise reference from a 2.097152
MHz quartz crystal. An internal pulse is generated by the
combinations of stages 1-4, 16 and 17 to set or reset
the individual stages. The MM53107 is advanced one
count on the positive transition of each clock pulse. One
buffered output is available: the 17th stage 60 or 100 Hz
output. The MM53107 is available in an a·lead dual-inline epoxy package.

•
•
•
•
•
•
•
•

Options
MM53107AA
MM53107FDU

Input frequency-2.097152 MHz
Output frequency-60Hz or 100 Hz
Crystal oscillator
High speed (2 MHz at VDD ; 2.5V)
Wide'supply range 2-6V
Low power (0.5 mW @ 2 MHz/2.5V)
Fully static operation
8-lead dual-in-line package

2.09 MHz to 60 Hz
2.09MHzto 100Hz

Block and Connection Diagrams

Dual-In-Line Package
VOO

NC

OSC OUT

osc IIi

DSCIN
DIVIDER
DUTPUT
DSC D U T - - - - - - '
MM53107

t

VDD

FIGURE 1
DIVIDER

VSS

NC

NC

(60 Hz or 100Hz)

DUTPUT
TDP VIEW

FIGURE 2

Typical Performance Characteristics
Typical Current Drain vs
Oscillator Frequency
600
I.
550 *CRYSTAl
FREQUENCY
500
4JH'j'
45D
1//
L
~ 400
fl /
!;; 350
/,
/.
;0 300
.5
'I 1/ 1
250
/'
200 3.5~H'j
/
'}<1.53MH,·
150
100
50

~

~

E

2.0IMH'~4 TI0.9Mr'~~

o

VDD(VI

5-251

Order Number MM53107AA/N
or MM53107FDU/N
See Package 17

Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Package Dissipation
Maximum VCC Voltage
Operating VCC Range
Lead Temperature (Soldering, 10 seconds)

--o.3V to VCC + 0.3V
O°C to +70°C
--65°C to +150°C
500mW
7V
2.5V to 6V
300°C

Electrical Characteristics
TA within operating temperature range, VSS = Gnd, 2.5V:::; VDD :::; 6V unless otherwise specified.
PARAMETER

MIN

CONDITIONS

TYP

MAX

UNITS

VDD=6V

10

p.A

Operating Current Drain

VDD= 2.5V, fiN = 2.1 MHz

200

p.A

Frequency of Oscillation

VDD=2.4V
VDD= 6V

dc
dc

2.1
4.0

MHz
MHz

Output Current Levels
Logical "1 .. Source

VDD =4V,

Logical "0, " Sink

VOUT= 2V

100
100

Quiescent Current Drain

Output Voltage Levels
Logical "1"

VDD= 6V

Logical "0"

V

,5.0

loSource = 10p.A

V

1.0

loSink = -10p.A

Functional Description
A connection diagram for the MM53107 is shown in
Figure 2 and a block diagram is shown in Figure 1.

The network shown provides> 100 ppm tuning range
when used with standard crystals trimmed for CL =
12 pF. Tuning to better than ±2 ppm is easily obtainable.
DIVIDER
A pulse is generated when divider stages 1-4, 16 and 17
are in the correct state. This pulse is used to set or reset
individual stages of the counter, the modulus of the
counter is '34,952 to provide 60 Hz.

TIME BASE
A precision time base is provided by the interconnection
of a 2,097,152 Hz quartz crystal and the RC network
shown in Figure 3 together with the CMOS inverter!
alT!plifier provided between the Osc In and the Osc Out
terminals. Resistor R1 is. necessary to bias the inverter
for class A amplifier operation. Capacitors Cl and C2
in series provide the parallel load capacitance required
for precise tuning of the quartz crystal.

OSCIN- -- -

-

-- -- -

Rl
20M

-

OUTPUT
The Divide Output is the input frequency divided by
34,952. The output is a push-pull output. A typical
application of the MM53107 is shown in Figure 5.

-OSCOUT

--

1

~'~lk

2,16B

I

32,7B4

1...._ _ _ _ _ _

1"'1'"
---1"'0'"

.-:----t' 0 '1----..

- L 5-36 pF
Cl'

7~

2,Ot7,1521HZ
CL = 12pF

........,.. C2
30pF

T

VODORVSS~~------------------------~

"To be selected based on the crystal used
FIGURE 3. Crystal Oscillator Network

FIGURE 4. Duty Cycle for MM53107AA

5-252

Functional Description

(Continued)
12V

I

~J6'f£D9MH'i
c::::J

T

,v -:=-":"

~
, I

VDD
60Hz

VDO
20M

HOLD

~

SETURS

~

•

T

1iCii2

-"-"

....L

MMS11D7

..L",f

, mil
•, mi.

I

ZD

2 BCDB

....L
2

~

,t

24
2l

....L

SETMINS ~-_11

22

DX
Dy
DZ

....L
~-"

MANUAL TV "ON"

....L.

MANUAL TV "OFF" ~-I'
MM53100

....L.

DISPLAVSELECT ~

-16
12V

....L.

p-- -

ENABLE

7

+~--c

....L.

STANDBY ' - - - ,
12V-"
50/60 Hz
SELECT

NORMALLY
HARD\'IIRED
fOR EACH
APf'LlCATIDN

~

"k r-

PERIOD
SELECT X

11

......

'-"

PERIOD
SELECT Y

,~:

VIEW PERIOD

PULSE OUTPUT

13

J.VSS
,v

b,
---w..
BCD4

mi.
OX
DY
DZ

VSST

"2{

IvDO
14

"

5

4

,
"
•

05CINH.

~

TDTVVIDEO
OUTPUT CIRCUIT

INTENSITY
ADJ.

&.Ik

VIDEO
OUTPUT

":"

Jlf\.fi.,v

9

1

P

S.lk

"

~

KGRIZ.

Z
S.ak

JU1

~~~~~~DNN

12

'V---< ........

Nate. VSS of MM53107 and
M M53100 are common.

~~~;~UN~'

21

FROM TV

HDRIZONTA
RETRACE
-1LJL,v

12
13

19

MM5640

VERT.

4MHz

"'fT

~"'i

2k

P
.

Ik

CHANNEL
UNITS

[

'"-'r
TENS

4
f

12V

22

23

"

24

"
"

11
2D

21

21

H'i' ..

/.

...

I

.~

"

HORIZONTAL
POSITION
ADJ.

/5Dk

HOI

I

VERTICAL
IlETRACE

VERTICAL
POSITION
ADJ.

/'OOk
12V

I

7

DIGIT SELECT 12V FOR 8-DIGIT

11

J

GND FOR 5·DIGIT

MODE CONTROl12V FOR CHANNEL AND TIME
GND FOR CHANNEl ONl V

FIGURE 5. Typical Application TV Channel and Time Display

5-253

Electronic Data Processing

~National

Electronic Data Processing

~ Semiconductor

MM5034, MM5035 Octal80-Bit Static Shift Register
General Description
The MM5034 octal 80·bit shift register is a monolithic
MOS integrated circuit utilizing N·channel low threshold
enhancement mode and ion·implanted depletion mode
devices.
The MM5034 is designed for use in computer display
peripherals. All inputs and outputs are TTL compatible.
The clocks and recirculate logic are internal to reduce
system component count, and TRI·STATE® output
buffers provide bus interface. Because of its N·channel
characteristics, single 5V power supply operation is
required.
Simple interface to the NSC CRT DP8350 controller
and character generator to incorporate an entire CRT
terminal is feasible with the MM5034.
The MM5034 is available in a 22·lead dual·in·line pack·
age.

The MM5035 is a 20'pin version of the MM5034 with
the TRI·STATE output select feature omitted, for a
simple data in/data out operation.

Features
• Single 5V power supply
• Internal clocks
• High speed and static operation
• TRI·STATE output buffer
• Recirculate and output select independent
• TTL compatible

Applications
• CRT displays
• Computer peripherals

Connection Diagrams'

Dual·in·Line·Package

Dual·in·Line·Package
22

RECIRCULATE

VOO

20,VOO

RECIRCULATE

OUTPUT 8

21 INPUT 8

OUTPUT 8

19 INPUT 8

OUTPUT1

20 INPUT1

OUTPUT1

18 INPUT 7

OUTPUT 6

19 INPUT 6

OUTPUT 6

17 INPUT 6

18 INPUT 5

OUTPUT 5

OUTPUT 5
MM5034
OUTPUT 4

17
16

OUTPUT 3

15

OUTPUT 2

14

OUTPUT 1
OUTPUT SELECT
VSS

10

13
12

11

INPUT 4

OUTPUT 4

INPUT 3

OUTPUT 3

INPUT 2

OUTPUT 2

INPUT 1

OUTPUT 1

MM5035

15 INPUT 4
14

12

TOP VIEW

CLOCK IN

Order Number MM5035N
See Package 20A

Order Number MM5034N
See Package 21

5·257

INPUT 1

'

11 CLOCK IN

Vss

TOP VIEW

INPUT 3

13 INPUT 2

10

NC

16 INPUT 5

II)
CW)

f5

:E
:E

..

~
CW)

Absolute Maximum Ratings.
Supply Voltage
Input Voltage
Power Dissipation
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)

7VDC
7VDC
750mW
-65°C to +150°C
300°C

f5

:E
:E

Electrical Characteristics
PARAMETER
Clock Input
Logical "1" Input Voltage
Logical "0" Input Voltage

VDD =.5V ±5%, TA = o°c to +70°C
CONDITIONS

Outputs
Logical "1" Output Voltage
Logical "0" Output Voltage
TRI·STATE Output Current

MAX

UNITS

0.8

V
V

0.8

V

5.0
8.0

IlA
pF

2.2

VIN = 5V
VIN = 2.5V
lOUT = 100llA
IOUT= 1.6 mA
VOUT= 5V
. VOUT = OV

V

5.0
2.4

Supply Current
Timing
Clock Frequency
Clock Pulse Width High
Clock Pulse Width Low
Output Rise and Fall Time (t r, tf)
Set-Up Time
Hold Time
Output Enable Time
Output Disabl~ Time
Clock Rise and Fall Time
Output Delay, (tPD)

TYP

2.2

Data and Control Inputs
Logical "1" Input Voltage
Logical "0" Input Voltage
Data, Clock and Control Inputs
Logical "1" Input Current
Input Capacitance

MIN

2.8
0:25

60

(Note 1)
(Figure 1)
(Figure 1)

V
V

"

5.0

IlA
IlA

90

mA

3.0
10,000

0
125
125

(Figure 1)

0.4
-5.0

MHz

00

40

50

80

185
185
5.0
185

100
0

(Figure 1)
(Figure 1)
(Figure 1)
(FigWe 1)

Note 1: The cloc~ input must be at a low level for DC storage. Minimum pulse width assumes 10 ns tr and tt.

MM5034, MM5035 Recirculate and ~RI.STATE Operation
Recirculate is used to maintain data in the shift register
after it has been .Ioaded. While the shift register is being
loaded, Recirculate must be at a logical "0". When the
loading is completed, Recirculate should be brought to a
logical "1". This disables the data input and feeds the

. 5~258

output of the last shift cell back to the input of the first
shift cell for each of the 8 registers.
For the output to be in the TRI-STATE mode outputselect should be at the logical '1' level.

ns

ns
ns
ns
ns
ns
ns
IlS
ns

AC Test Circuits and Switching Time Waveforms

m·

s:
s:
en

OUT

o
CN
en

T""

OUTPUT DATA LINE

3V------------~r_--------­

RECIRCULATE
CONTROL

,v----------'\-_ _ _ __

3V--------,/-____
OUTPUT mID

,v ____________

-J~---------

FIGURE 1

Typical Application
PERIPHERAL

VIDEO
INTERFACE

INTERFACE

TO
ATTRIBUTE

DECODE

REGISTER

RAM

LOAD

lOGIC

VIDEO

OUTPUT
HORIZONTAL

}

~~~~~~~~%~~~~B~~~~~~~~~~----.:::.::....--~=~~..L..--------l=~~~Sy~Ntc
ADDRESS BUS

VERTICAL
SYNC
CURSOR

MONITOR
THREE-TERMINAL

I

' -____..:.EN"'A..:.Bl""+1
. -______, -________~S~YS~T~'M~C=O~NT~R~Ol~B=U~S_______________y1-----,_---------2~--_;~--~r

I

OMA CONTROL

FIGURE 2. CRT System Diagram Using the MM5034, MM5035 as a Line Buffer with DMA

5-259

('I)

~

~ National

:E

MM5303 Universal Fully Asynchronous
ReceiverlTransmitter

~

Electronic Data Processing

~ Semiconductor

General Description
The MM5303 is a fully asynchronous receiverltransmitter, fabricated with National's metal-gate, depletion load,
PMOS technology. All inputs and outputs are fully TTL
compatible, requiring no external resistors or level
shifting.

•

Fully externally programmable:
Word length
Parity mode
Number of stop bits
• Fully double buffered eliminating need for precise
synchronization
• Full or half duplex operation
• Direct TTL/DTL compatibility
• Automatic data received/transmitted status generation

This device is a programmable interface between an
asynchronous serial data channel and a parallel data
channel. The transmitter section converts parallel
data into a serial word which includes: start bit, data,
parity bit (if selected), and stop bit(s). The receiver
converts a serial word of the same format into a parallel one and automatically checks start bit, parity (if
selected), and stop bit(s).

• TRI-STATE outputs
• Automatic start bit generation/verification
• Internal pull·ups on all inputs

Both transmitter and receiver are doubly buffered; in
addition, received data out and status words may be
TR I-STATED, facilitating bus configurations.
Status conditions are: transmission complete, Tx buffer
register empty, Rx data available, parity error, framing
error, and over-run error.

Applications
• Peripherals
• Terminals
• Mini computers
• Facsimile transmission

The MM5303 is fully' programmable. It can operate
full or half duplex, transmitting and receiving simultaneously at different baud rates; word length may be 5,
6, 7 or 8 bits; parity generation/checking may be even,
odd or inhibited; the number of stop bits may be either
1 or 2, with 1 1/2 bits when transmitting a 5 bit code.

•
•
•
•

• Printers
• Data sets
• Controllers
• Keyboard encoders
• Remote data acquisition systems
• Asynchronous data cassettes

Features
•
•

Modems
Concentrators
Asynchronous data multiplexers
Card and tape readers

Low power
High speed

connection diagram
Dual-I n-Line Package
40

Vss

J9

VGG

"

VOO

J7

ROE

l6

RO 8

35

RO 7

34

RO'

J3

RO 5
RO'
RO 3
RO 1
ROI
RPE
RFE
ROR
SWE
RCP

ROAR
RD'
R5I

10

"31

11

3D

11

19

13

18

14

17

15

"

"

25

14

17

18

23

19

12

10

11

TOP VIEW

5-260

TCP
POE-

NOB 1
NOB 2

NS8
NPB
CS
TO 8
TO 7
TO'
TO 5

TO'
TO 3
T02

T01
TSO
TEGe

TDS
1BM1
MR

Order Number MM5303N

See Package 24

Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering.. 10 seconds)

(Note 1)
Vss -25VNss +0.3V·
-25°C to +70°C
-65°C to +150°C
300°C

'Outputs should not have more than V ss - 15V

DC Electrical Characteristics
'TA within operating temperature range, Vss = 5V ±5%, Voo = OV, VGG = -12V ±5% unless otherwise noted.
PARAMETER
V ,H

High Input Voltage Levels

V ,L

Low Input Voltage Levels

V OH

High Output Voltage Levels

CONDITIONS
INote 3)

10H =-100JiA

MIN

TYP

MAX

UNITS

V ss -1.5

Vss+0.3

V

Voo

O.S

V
V

2.4

VOL

Low Output Voltage Levels

10L = 1.6 mA

OA

V

I'H

High Level Input Current Levels

Y'N = Vss

10

JiA

I'L

Low Level Input Current Levels

1.6

mA

10L

Y'N = OAV, Vss = 5.25V

-- --

Output Leakage Current Level

-1

SWE = RDE = V ,H ,

JiA

O~ V OUT ~5V

los

25

mA

5

10

pF

V OUT = OV, (Note 4)

Output Short Circuit Current
Level

C'N

(Note 2)

I nput Capacitance
All Inputs

COUT

Y'N = V ss , f= 1 MHz

Output Capacitance

-- --

SWE = RDE = V ,H , f = 1 MHz

10

20

pF

Iss

Power Supply Current

All Inputs at V ss

13

25

mA

IGG

Power Supply Current

All I nputs at V ss

6

15

mA

MAX

UNITS

500

kHz

All Outputs

AC Electrical Characteristics

at 25°C

PARAMETER

tpw

CONDITIONS

MIN

TYP

Clock Frequency

RCP, TCP

de

Pulse Width
Clock
Master Reset
Control Strobe
Tx Data Strobe
Rx Data Available Reset

RCP, TCP
MR
CS
TDS
RDAR, (Note 5)

1
5·
1
300
200

JiS
Jis
Jis
ns
ns

tc

Coincidence Time

TDS
CS

300
1

ns

tSET

Input Set·Up Time

TD1-TDS
NPB, NSB, NDB, POE

0
0

ns
ns

tHOLD

Input Hold Time

TD1-TDS
NPB, NSB, NDB, POE

300
0

ns
ns

tOd~

Output Propagation Delay to
Low State

RDE, SWE Enable to Outputs Low

500

ns

tOd1

Output Propagation Delay to
High State

RDE, SWE Enable to Outputs High

500

ns

Jis

Note 1: "Absolute Maximum Ratings" are those values beyond which ·the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.

Note 2: Capacitance is guaranteed by periodic testing.
Note 3: Positive true logic notation is used:
Logic "1" = most positive voltage level
Logic "0" = most negativ~ voltage level
Note 4: Only one output should ~e shorted at a time.
Note 5: Refer to Receiver Timing diagram for detail.

5-261

('I)

i

Functional Block Diagrams

It)

:E
:E

...

f-+--.,.--,;tTS •

NPB

P.'

NDlt

APE

RFE

A'Dl1i

"

ROA

NOTE:::[l':r TRI-5TATE' OUTPUT

Flow Charts
Receiving Sequence

Transmitting Sequence

..
I

I
I

I
I
I
I

I

OPERATION EXTERNAL
TDUART

OPERATION EXTERNAL
TOUART

Note 1: Control Strobe should be made only at the beginning of transmission and remain inactive during transmission.
It may be tied high if no change is. necessary.
Note 2: The line must stay low for 8 Rep pulse. to be verified.
Note 3: ROAR - 0 will cause ROA - 0, refer to receiver timing for detail.

5·262

R••

Pin Functions
PIN NO.

SYMBOL

NAME

FUNCTION

1

Vss

Power Supply

+5V supply

2

VGG
Voo

Power Supply

-12V supply

3

Ground

Ground

4

RDE

Received Data Enable

A low-level input enables the outputs (RD8-RDll of the
receiver buffer register.

5-12

RD8-RDl

Receiver Data Outputs

These are the 8 TRI-STATE data outputs enabled by RDE.
Unused data output lines, as selected by NDBl and NDB2,
have a low-level output, and received characters are right

justified, i.e., the LSB always appears on the RDl output.
13

RPE

Output

This TRI-STATE output (enabled by SWEI is at a high-level
if the received character parity bit does not agree with the
selected parity.

Receiver Parity Error

14

RFE

Receiver Framing Error
Output

This TRI-STATE output (enabled by SWElis ata high-level
if the received character has no valid stop bit.

15

ROR

Receiver Over Run
Output

This TRI-STATE output (enabled by SWEI is at a high-level
if the previously received character is not read (RDA output
not reset) before the present character is transferred into the
receiver buffer register.

16

SWE

Status Word Enable
Input

A low-level input enables the outputs (RPE, RFE, ROR, RDA,
and TBMTI of the status word buffer register.

17

RCP

Receiver Clock

This input is a clock whose frequency is 16 times (16XI the
desired receiver baud rate.

18

RDAR

Receiver Data Available
Reset Input

A low-level input resets the RDA output to a low-level.

19

RDA

Receiver Data Available
Output

This TRI-STATE output (enabled by SWEI is at a high-level
when an entire character has been received and transferred
into the receiver buffer register.

20

RSI

Receiver Serial Input

This input accepts the serial bit input stream. A high-level
(mark) to low-level (space) transition is required to initiate
data reception.

21

MR

Master Reset

This input should be pulsed to a high-level after power turn-on.
This sets TSO, TEOC, and TBMT to a high-level and resets RDA,
RPE, RFE and ROR to a low-level.

22

TBMT

Transmitter Buffer Empty
Output

This TRI-STATE output (enabled by SWEI is at a high-level
when the transmitter buffer register is empty and
may be loaded with new data.

23

TDS

Transmitter Data Strobe
Input

A low-level input strobe enters the data bits into the transmitter
buffer register.

24

TEOC

Transmitter End of
Character Output

This output appears as a high-level each time a full character is
transmitted. It remains at this level until the start of transmission
of the next character or for one full TCP period in the case of
continuous transmission.

25

TSO

Transmitter Serial Output

This output serially provides the entire transmitted character.
TSO remains at a high-level when no data is being transmitted.

26-33

TD1-TD8

Transmitter Data Inputs

There are 8 data input lines (strobed by TDSI available_
Unused data input lines,as selected by NDBl and NDB2, may
be in either logic state. The LSB should always be placed on TDl.

34

CS

Control Strobe Input

A high-level input enters the control bits (NDB1, NDB2, NSB,
POE and NPB) into the control bits holding register. This line

may be strobed or hard wired to a high-level.
35

NPB

No Parity Bit

A high-level input eliminates the parity bit from being transmitted; the stop bit(sl immediately follow the last data bit_ In
addition, the receiver requires the stop bit(s) to follow imme-

diately after the last data bit. Also, the RPE output is forced
to a low-level. See pin 39, POE.
36

NSB

Number of Stop Bits

This input selects the number of stop bits, 1, 11/2, or 2 to be
transmitted. A low-level input selects 1 stop bit; a high-level
input selects 2 stop bits, except when 5-bit data is selected,
then 1 1/2 stop bits will occur.

5-263

Pin Functions

(cont'd)

PIN NO.

SYMBOL

NAME

37-38

NDB2.
NDB1

Number of Data Bits/
Character

FUNCTION

These 2 inputs are internally decoded to select either 5, 6, 7
or 8 data bits/ character as per the following truth table:
NDB2

39

POE

NDB1

data bits/character

L

L

5

L
H
H

H
L
H

6
7

8

The logic level on this input, in conjunction with the NPB

Odd/Even Parity
Select

input, determines the parity mode for both the receiver and
transmitter, as per the following truth table:
POE
L
H
X

NPB
L
L
H

MODE
odd parity
even parity

no parity

x == don't care
40

TCP

This input is a clock whose frequency is 16 times (16X) the
desired transmitter baud rate.

Transmitter Clock

Timing Diagrams
Transmitter Timing - a-Bit, Parity, 2 Stop Bits

TBMTU
STOP 2

START

----'nL-__

TEOC , ' - -_ _ _ _ _ _

Transmitter Start-Up

TCPJULj
.TOS

____ 1 1115 BIT TIME

LJ

r--

to low transition of the TCP clock following
the trailing edge of Tl)l;.

rA~
T50 _
5

Upon data transmission initiation, or when hot
transmitting at 100% line utilization, the start
bit will be placed on the TSO line at the high

IL._ _ _ _ _ __

Receiver Timing-a-Bit, Parity, 2 Stop Bits
ASI

r-I
'''-1START
DATA 1 ••••• I DATA 8 I PARITYJ
~
__
1
L_--1 _ _

STOP 1

STOP?

START

CENTER
BIT

SAMPH _ _ _ _----'_ _-'-_ _ _ _--'-_ _-'-_ _L-_--1._ _-'-_ _

RDA

Resetting RDA
RVA

I
I
RCP

JlS1.IL
I

I Rep MIN

I

t
tl
1---

~

ROAR may go low any time after the RDA
comes up but must stay low for at least 200 ns
after the first clock pulse period. ROAR
may be hard wired low, in which case ADA
will go high and remain high for the duration of

the positive clock pulse.

200 usMIN

5-264

Timing Diagrams

(cont'd)

Data/Control Timing Diagram

Start Bit Detect/Verify

,r~--''''--

V,H

M-

IDs

: .: ~l Vil

DATA INPUTS
If ~ If = 2111\\
'SET UP _ 0

~

I-""'~~
!~-'c----~I l'-

Vlfl-----

V,, ____...J

CONTROL INPUTS

Output Timing Diagram
R"OT.SWE
V,t
OUTPUTS
(RD1-RDS, RDA,

RPLRFL TBMTI

BEGIN VERIFY

RSI:~

---f'-------------'I

V O H - - - --------~ ,~------

+-________-J

VOL _ _ _

f'------

Note: Waveform drawings not to scale for clar,ity.

5-265

_ _ _---"':;EGIN VERIF'i

I

If the RSI line remains spacing for 1/2 a bit
time, a genuine start bit is verified. Should the
line return to a marking condition prior to 1/2
a bit time, the start bit verification process
begins again.

tHOlO _0

os

RCPLJL LJLJ
I
I

~National

Electronic Data Processing

~ Semiconductor
MM5307 Baud Rate Generator/Programmable Divider
General Description
The National Semiconductor MM5307 baud rate
generator/programmable divider is a MaS/LSI P-channel
enhancement mode device_ A master clock for the device
is generated either externally or by an on-chip crystal
oscillator (Note 4)_ An internal ROM controls a divider
circuit which produces the output frequency_ Logic
levels on the four control pins select between sixteen
output frequencies. The frequencies are chosen from
the following possible divisors: 2N, for 3 -:::: N -:::: 2048;
2N + 1 and 2N + 0.5 for 4 :::; N :::; 2048. Also one of the
sixteen frequencies may be gated from the external
frequency input. The MM5307 AA is supplied with the
divisors shown in the Control Table.

Applications

Features

•

• On-chip crystal oscillator

• System clocks

• Choice of 16 output frequencies from 1 crystal

•

•

External frequency input pin

•

Internal ROM allows generation of other frequencies
on order

•

Bipolar compatibility

• 0.01% accuracy (typ) exclusive of crystal
•

1 MHz master clock frequency

UAR/T clocks

Electrically programmable counters

Schematic and Connection Diagrams
A

Dual-In-Line Package
14 "OUT

EXTERNAL FRED.

13 RESET

NC
RESET

>----1

PROGRAMMABLE
DIVIDER

<1>1

2

OUTPUT

12 vGG

OUTPUT

11 A

Vss

r&....-I- - - - - '
(EXT.
FREQ.

EXTERNAL
CLOCK

5

10

B

CRYSTAL

EXTERNAL
CLOCK

>___.>,
~

;OUT

CRYSTAL

TOP VIEW

p

1..--..-----1

Order Number MM5307AA/N,
MM5307AB/N, MM5307FAG/N
See Package 18

5-266

Absolute Maximum Ratings
Voltage at Any Pin With Respect to VSS
Power Dissipation
Storage Temperature Range
Operating Temperature
Lead Temperature (Soldering, 10 seconds)

+0.3V to VSS - 20V
700mW
-65°C to +150°C
O°C to +70°C
300°C

DC Electrical Characteristics
T A within operating range, Vss

= 5V ±5'10, V GG = -12V ±5'10, unless otherwise specified.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

All Inputs (Except Crystal Pins)
Logical High Level

VSS-1.5

VSS+O.3

V

Logical Low Level

VSS-18

VSS-4·2
0.5

V
/lA

7.0

pF

Leakage

VIN

= -10V, TA = 25°C,

All Other Pins GND
Capacitance

VIN

= OV, t = 1 MHz,

All Other Pins GND, (Note 1)
40%

External Clock Duty Cycle
Capacitance Measured Across

60%

t = 1 MHz, (Note 3)

5.0

pF

Crystal Pi ns
Output Levels
VOH

Logical High Level

ISOURCE

VOL

Logical Low Level

ISINK

IGG

Power Supply Current

= -0.5 mA

VSS-2.6

V

VSS

= 1.6 mA

VSS-4.6

t = 1 MHz

35

V
mA

AC Electrical Characteristics
T A within operating range VSS = 5V ±5'10, V GG = -12V ±5'10, unless otherwise specified.
PARAMETER

CONDITIONS

MIN

Master Frequency

0.8

tA

Access Time

CL

tRD

Reset Delay Time

t

RpW

Reset Pulse Width

too

TYP

= 50 pF, (Note 21

UNITS

1.0

MHz

16

= Master Clock Frequency

500 + 4/t
500 + 4/t

= 0.5T ± 1If

500 + 4/t
T
f

= Output Period
= Master Frequency

Note 1: Capacitance is guaranteed by periodic measurement.
Note 2: Access time is defined as the time fram a change in control inputs (A, B.

/lS
ns
ns

Output Delay From Reset
Output Duty Cycle

MAX

ns

0.5T+l/t

·0.5T -lit

c. D) to a stable output frequency. Access time is a function of

frequency. The following formula may be used to calculate maximum access time for any master frequency: T A

=

2.8,us + 1ff x 13, f is in MHz.

Note 3: The MM5307 is designed to operate with a 921.6 kHz parallel resonant crystal. When ordering the crystal a value of load capacitance (eLl
must be specified. This is the capacitance "seen" by the crystal when it is operating in the circuit. The value of CL should match the capacitance
measured at the crystal frequency across the crystal input pins on the MM5307. Any mismatch will be reflected as a very small error in the
operating frequency. To achieve maximum accuracy, it may be necessary to add a small trimmer capacitor across the terminals.
Note 4: If the crystal oscillator is used Pin 5 (external clock) is connected to VSS. If an external clock is used Pin 7 is connected to VSS.

5-267

Control Table
Input Freq: 921.6.kHz Master Clock

NOMINAL BAUD RATES
(OUTPUT FREQUENCY/lSI

CONTROL PINS
A

B

C

D

0
0
0
0
0
0
0
1
1

0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0

0
1
1
0
0
1
1
0

ci

1
0
1
0
1
' 0
1
0
.1

1
1
0
0
1
1
0

0
1
0
1
0
1
0

1

1
1
1
1
1

0

AA

AB

FAG

50
75
110
134.5
150
300
600
900
1200
1800
2400
3600
4800
7200
9600

50
200
110
134.5
150
300
600
900
1200
1800
2400
3600
4800
75
9600

50
75
110
134.5
150
300
600
1050
1200
45.5
2400
56.9
4800
66.7
9600

DIVISOR
FORAA

1152
768
524
428.5
384
192
96
64
48
32
24
16
12
8
6

EXTERNAL FREO

Positive Logic: 1 = VH
O=VL

Typical Applications
. External Clock

Internal Oscillator

EXTFRED-+-..:.j

NC

14 "OUT
13
12

OUTPU~-. . .-""I

EXTFRED-....-..:.j
Vss (TO OPERATE)

,Vee (TO RESET)

NC
OUTPUT--4-=i

Vee

14 'I>OUT

viis (TO OPERATE)

13

Vee (TO RESET)
12

Vee

11 A

11 A

10

10 B

EXT CLOCK IN ....- + - = i

B 0

Vss

Vss

5·268

Application Hints

The external clock is brought in on pin 5 and pin 7 is
tied to Vss to enable the external clock input. Pin 6
can be left open; however, this may cause some current
flow that can be eliminated by connecting pin 6 to VDD.
1) To use the MM5307 with an external clock, hook
it up as follows:

The MM5307 does not always generate an output when
the power is up, even though the oscillator seems to be
operating properly. In order to eliminate this problem,
it is necessary to reset the chip at power "ON". This can
be done manually, with a reset signal by a host system,
or automatically by using RIC timing elements. The
reset is done internally, when program inputs change.
When using an RIC combination for auto resetting,
the time constant must be several times larger than
that of the power supply. For example, most lab power
supplies take at least 0.5 sec for the voltage to reach
90% of full level. A 10 kQ resistor and 300 IlF capacitor
combination should be adequate for most applications.

EXTEANAL CLOCK

2) To use a crystal directly:

vss

3) Reset (pin 13) must be at VSS to operate. It may be
necessary to take this to GND or VGG to reset the
ROM select circuit. An option is to tie", out (pin 14)
to external Freq In (pin 1)' if not otherwise used.
4) An interesting application might use two MM5307's
in series to generate additional frequencies, i.e., with
one programmed from the 921.6 kHz to 800 Hz out,
a second could divide that by 16 to give a 50 Hz
crystal controlled signal.
5) MM5307 AA divisors are on the data sheet. AB
divisors are the same as the AA except: 1) Code 0010
is divided by 288 -> 32 kHz out, 200 baud; 2) Code
1110 is divided by 768 -> 1.2 kHz, 75 baud.

-1vt-_--I

CLOCK TO INTERNAL
CIRCUITRY

TO

vss TO ENABLE XTAL
OSCillATION

* Component values should be selected based

vss---iVl--...--iul-.....--I

on crystal used.

~vss
vss

POWER SUPPLY TIMING

AT POWER UP

VOLTAGE

L

I

r----,=--

MANUAL
RESET

'"" 0.5 SEC
TIME

5-269

.....

~

Timing Diagrams

Lt)

::iB
::iB

¢2

1111111111111111111111111111111111111111111111111111111111111
+90%
+10%

A.B.CorO

--+---',,_--J"-____.....J~~---' '-_ _ _

. OUTPUT _ _

---oJ

'"-_-==~=~~,_

RESET

¢1

=EXT CLOCK

OUTPUT (2N DIVISOR)
OUTPUT (2N + 1 DIVISOR)
OUTPUT (2N + 0.5 OIVISOR)

:::...f1.JL. . ..fl.I1..........:flI1.........

~

-,
---,
-,

N
N

N

N

N +1

N +0.5

N

5-270

....JUl... ..
LN+l

N+ 1

N - 0.5

L

~National

Electronic Data Processing

~ Semiconductor

MM5330 41/2-Digit Panel Meter Logic Block
General Description

Features

The MM5330 is a monolithic integrated circuit which
provides the logic circuitry to implement a 4-1/2 digit
panel meter. The MM5330 utilizes P-channel low threshold enhancement mode devices and ion-implanted
depletion mode devices. All inputs and outputs are TTL
compatible with BCD output for direct interface with
various display drivers.

• dc to 400 kHz operation
• TTL compatible inputs and outputs
•
•
•
•

BCD output code
Overrange blanking
Valid sign bit during overrange
Standard supply voltages; +5, -15V

Connection and Block Diagrams
Dual-In-Line Package
SSD
16

1S0

"

LSD
14

RESET TRANSFER CLOCK

13

12

11

INT

VDl)

10

9

t-

L-

Order Number MM5330N

,
MSO

2
BCD
"1"

1
BCD
"2"

4

5

BCD
SGN
"4"
TOPVIEW

,
BCD
"S"

,

,

See Package 19

10k

RESET

ClOCK-f>--<.......- -

TRANSFER

seN

LSD

5-271

T50

SSO

MSO

Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)

Vss + 0.3V to Vss - 25V
o°c to +75°C
-40°C to +125°C
300°C

Electrical Characteristics
T A within operating range, Vss = 4.75V to 5.25V, V DD = -16.5V to -13.5V unless otherwise specified.
MIN

TVP

MAX

Power Supply Voltage IVssl

4.75

5

5.25

Power Supply Voltage IVaal

-16.5

-15

PARAMETER

Power Supply Current Iissl

CONDITIONS

No Load

Input Frequency

dc

Reset or Transfer Pulse Width

200

Input Voltage Levels
Logic "1"
Logic "a"

Vss = 5V, Vaa =-15V
Inputs Driven by TTL or Square Waves
Inputs Driven by TTL or Square Waves

Clock Input Voltage Levels
Logic "1"
Logic "a"

Driven by Sinewave

Output Current Levels

Vss = 5V, Vaa = -15V

3
-15
Vss-0.5
Vss-25

Driven by Sinewave

Digit Output State
Logic "1"
Logic "a"

Va Forced To 4.75V
Va Forced To 4.5V

100
-5

All Other Outputs
Logic "1"
Logic "a"

Vo Forced To 3V
Vo Forced To OAV

100
-2
0.1

Delay Frorn Digit Output to BCD Output

FUN'CTIONAL DESCRIPTION
Counters: The MM5330 has four 710 counters, one
74 counter, and one 72 for a count of 80,000 clock
pulses. A ripple carry is provided and all counter flip·
flops are synchronous with the negative transition of
the input clock. The last flip·flop in the divider chain
(72 in the block diagram) triggers with the "0" to "1"
transition of the previous flip·flop. The count sequence
is shown in the first column of the count diagram.
Reset: All counter stages are reset to "0" a nd the I NT
flip·flop (driving the I NT output) is set to "1" on the
first negative clock transition after a "0" is applied to
the Reset input. The internal reset is removed on the
first negative clock transition after the internal' reset
has occured and a "1" has been applied to the Reset
input. This timing provides an on·chip reset at least one
clock cycle wide and a one cycle delay to remove reset
before counting begins.
Transfer: 'Data in the counters is transferred to the
latches when the Transfer input is at "0." If the
Transfer input is held low the state of the counters is
continuously displayed (see count diagram). Data will
cease to transfer to the latches on the first positive clock

UNITS
V

-13.5

V

30

rnA

400

kHz
ns

5
0.8

V
V

Vss+0.3
Vss-4.5

V
V

-20

./1A
rnA
/1A
,rnA

5

transition after the first negative clock transition after a
"1" is applied to the Transfer input. This provides a
transfer pulse at least one half clock cycle wide and a
half clock cycle delay to remove the transfer signal
before the counters change state.
INT: The integrate output is used to set the charge time
on a dual slope integrator. INT is "1" from reset to the
18,OOOth clock pulse, then "0" until the next reset. The
dual slope integrator is the voltage monitoring part of
the external circuitry needed for a DPM. It charges a
capacitor at a rate proportional to the measured voltage
while INT is "1," then discharges at a rate proportional
to a fixed reference as shown in the dual slope diagram.
When the output of the integrator reaches OV a pulse is
generated and fed into the Transfer input of the chip.
As the dual slope diagram indicates, the number in the
latches is proportional to the measured voltage.
Multiplexing: The modulo 4 multiplex counter is
triggered by the carry from the second decade counter,
making the multiplex rate one hundredth the counting
rate (4 kHz for a 400 kHz clock). The LSD, TSD, SSD
and MSD (least significant, third significant, second
significant and most significant digits) outputs indicate
by a low level which decade latch is displayed at the
BCD outputs.

5·272

/1S

sign digit, either plus or minus, and a ten·thousand
counts digit for full display of ±19999. By eliminating
the right·most digits it may also be used as a 2·1/2 or
3-1/2 digit DVM chip.

FUNCTIONAL DESCRIPTION (Continued)
Overrange Blanking and Sign: The data in the latch for
the 72 counter is used to detect an out-of-range voltage.
If this latch is "0" the BCD and 10k outputs are forced
to all "1 's" and the SGN output is inverted. When the
data in the overrange latch and the sign bit latch are "1"
the sign bit generates the 9's complement of the decade
latches and the complement of the. 10k latch at the
respective outputs. When the overrange bit is "1" and
the sign bit is "0" true BCD of the decade latches and
the uncomplemented 10k latch appear at the outputs.

The basic modified dual slope system for which the
MM5330 is designed, is shown in Figure 1. The integrator
is now used in a non-inverting mode and is biased to
integrate negatively for all voltages below V MAX • Thus
if the maximum positive voltage at V IN is 1.9999V, then
V MAX would be set at 2.200V. In this way, all voltages
measured are below V MAX • This eliminates the need for
reference switching and provides automatic polarity with
no additional components. Also, it can be shown that
the amplifier input bias currents which cause errors in
conventional dual slope systems are eliminated by merely
zeroing the display. Thus low bias current op amps are
not necessarily required unless a high input impedance is
desired at V IN .

APPLICATIONS INFORMATION
The MM5330 is the display and control for a modified
dual slope system. It contains the counters and latches,
together with a multiplexing system to provide 4 digits
of display with one decoder driver. It also provides a

Count Diagram
OUTPUTS WITH TRANSFER LOW

INTERNAL STATES

BCD
DECADE
OUTPUTS

DECADE
COUNTERS

0
0

0
0

0

9

9

0

0

•
•
•
•
••

9

o

o
COMPLEMENT
OUTPUT
INTERVAL

}

POSITIVE
OVERRANGE

{"

•
•
•

0

•
•
•0

POSITIVE
VALUE

9

o

TRUE
OUTPUT
INTERVAL

9

9

o

0

o
o

o

NEGA TlVE
VALUE

9

0
0

I
1.

0

•
•
•

•
•
•0

o

0
0

o

o

0

0

o

•

•9
0

CONTINUOUS
COUNT

•
•
•9

••
0

o

0

DISPLAY
ZONE

o

1
BLANKING
ZONE

0

OUTPUT
BLANKED

0

9

0

0
01

NEGATIVE
OVER RANGE

[
1.

J
5-273

•
•9
•
•
•

9

parator crossing is detected within the next 2000
counts, a plus overrange condition will occur at the
display. This condition results in a lit "+" sign, a lit "1"
and four blanked rightmost digits. A transfer at 20,000
however, will create a reading of +1.9999, at 20,001 .a
reading of 19.998 and so on, until at 39,999 a reading
of +0000 would be displayed. A transfer occuring at
40,000 would cause a -{l000 display and so on until
60,000 counts were entered at which time a -1 with
four blanked digits would be displayed indicating a
minus overrange condition.

APPLICATIONS INFORMATION (Continued)

Secondly, the use of a conventional op amp for a
comparator allows zeroing of all voltage offsets in both
the op amp and comparator. This is achieved by zeroing
the voltage on the capacitor through the use of the
comparator as part of a negative feedback loop. During
the zeroing period, the non·inverting input of the
integrator is at V REF • As this voltage is within the active
common·mode range of the integrator the loop will
respond by placing the integrator and comparator in the
active region. The voltage on the capacitor is no longer
equal to zero, but rather to a voltage which is the sum
of both the op amp and comparator offset voltages.
Because of the intrinsic nature of an integrator, this
constant voltage remains throughout the integrating
cycle and serves to eliminate even large offset voltages.

A typical circuit for a low cost 4 1/2 digit DPM is
shown in Figure 2. The display interface used is a TTL,
7·segment decoder driver and four P·type transistors.
The ±1 digit is driven directly by CMOS. The clock·
synchronous reset and transfer functions prevent any
cyclic digit variations and present a blink·free, flicker·
free display. CMOS analog switches are used as reference,
zero, and input switches and used also in the comparator
slew rate circuit.

The waveforms at the output of the integrator are as
shown. The voltage' at A is the comparator threshold just
discussed. SimultaneouslY, with the opening of switch A,
V,N is connected to the input of the integrator via
switch B. The output then slews to V,N . Integration then
begins for the reference period, after which time the
reference voltage is again applied to the input. The
output again slews the difference between V REF and
V,N and integrates for the unknown period until the
comparator threshold is crossed. At this point, the
accumulated counts are transferred from the counters
to the latches and zeroing begins until the next
conversion interval.

A problem with all dual slope systems occurs when short
integrating times and high clock frequencies are used.
Because of the very slow rise time of the ramp into the
comparator, the output of the comparator will normally
ramp at approximately 1/10 of its actual slew rate.
Thus, a significant number of extra counts are displayed
due to the slow rate of rise of the comparator. A
technique to improve this consists of capacitor Cs and
analog switch four. An unstable positive loop is created
by this capacitor when the comparator comes out of
saturation. This causes the output to rise at its slew rate
to the comparator threshold. As soon as this threshold
is reached the analog switch opens and zeroing is initiated
as previously discussed.

It may be obvious, however, that while we have
eliminated several of the basic dual slope circuits
disadvantages, we have created another-the number
of counts are-no longer proportional to V,N but rather
to (VMAX-V,N)' In fact, when we short V,Nto ground
we are actually measuring our own 2.2000 VMAX '

A simplified approach to performing the modified dual
slope function combines the MM5330 and the LFl1300
dual slope analog block as in Figure 3. The LFl1300
provides the front analog circuitry required. This
includes a FET input amplifier, analog switches, inte·
grator and comparator. The LFl1300 provides auto
zero, > 1000 Mn input impedance, and a ±10V analog
range.

What is done in the MM5330 is to code convert the
number of counts as shown in the count diagram. This
chart shows a code conversion starting at the time of a
reset. The first 18,000 counts are the reference period
after which time the integrator changes slope. If a com·

Dual Slope Diagram
lB.DDD~1
BLANKING ZONE

DURING INTEGRATION

rrI

I I
I

I I

POSITIVE DVERRANGE

POSITIVE VALUES

NEGATIVE VALUES

V)( li'beanalogvoltage
to be converted.

5·274

I
I NEGATIVE
: OVERRANGE

Typical Applications

f-- TUR0--1

COMPARATOR
__ A
THRESHOLD

TAANSFER

FIGURE 1. Modified Dual Slope
O-199.99k~ !

TERMINALS

OHMS

10apF

10k

t-....~Mr-(J

·5V

INTEGRATE
'5V
-15V

4.7M

·5V

'--J--t-_t-l100~

12k
5"

RESET

"
SIGN

5

MM53)O

"

~'fd

TRANS

'00"

'5V
·5V

NSN1]

NSNl!

NSNl!

NSN1!

NSN71

DM7446

RA07 lOON

FIGURE 2. Typical Application Low Cost 4 1/2 Digit Volt·Ohm Meter

5-275

Typical Applications

(Cont'd)
lW

11

1

15V

T
,':"

':'"

001

11

,

8

2

,
2

2313

AAQ7150N

5

'" "
"

DISPLAY

>5

,,,

11

OM]~46

,

9

8

POL YSTY~ENE

"

""

NSB5911

~F

C 041

~F

"

Inverters - MM74C14 Hex Schmitt Trigger (MOS)
Two letters (AA, BB ... ) NAND gates - MM74COO CMOS quad NAND gates
One letter (A, B ... )

~IAND

gates

~

DM7400 TTL quad NAND gates

1 -> analog ground
.. digital ground

All resistors 1/4W, 5% unless otherwise noted.
All capacitor values in.uF unless otherwise noted.
INDUCTIVE COMPONENTS
STAVER

U5X021 MiCROTRAN

PCT69Jl TRANSFORMER

V~

HEATSINK

5

,1171"
·III:
(Second letter code)

.11

I I.

1------

' - - - - - - -.....-o-isv

.. --- -j

First letter code:
A -.. . anode
C --> cathode

NSB5917 Display (Front View)

MSD ~ digit 2
SSD - digit 3
TSD ~ digit 4
LSD - digit 5

FIGURE 3. 4 1/2-Di9it DVM

5-276

Timing Diagrams
4 1/2-0igit OPM

COMPARATOR
OUTPUT

RESET
PULSE

VOUT
dVOUT
d,
INTEGRATOR
OUTPUT

0

2.2 - 4.0
RC

dVOUT. 2.2 - Vx
-d-'-· -R-C-

-VB .....-"'---T·
OFFSET
CORRECT
RAMP
UNKNOWN

Note. Here the LF 13300 always operates
as an autozeroed. high input impedance
inverting integrator; bipolar input volt-

ages are handled by offsetting the analog
ground by 2.2V.

5-277

Electronic Data Processing

~National

~ Semiconductor

MM53200 Encoder/Decoder
The MM53200 EncoderlDecoder is an MaS/LSI Digital
Code Transmitter - Receiver system.

1. This code is generated at the rate of 0.96 ms/bit, or
11.52ms/word with 11.52ms reset pulse between words.

Features

Operation

In the receiver mode, the incoming signal is compared
to the local code in a sequential manner; ifthere is an
error, the system is reset and begins its comparison on
the next pulse. If all twelve bits are received correctly, a
"valid" signal will be generated. This signal clears a
64 ms counter and clocks a 3 stage counter. The 3 stage
counter counts the "valid" pulses and when 4 pulses
have been received, the transmit/receive output goes
low. After the transmit/receive output is enabled, the next
"valid" must be received within 128 ms, giving a one valid
in 6 requirement to keep the transmit/receive output low.

In the transmit mode the twelve inputs are scanned se·
quentially producing the output pattern shown in Figure

Connection diagrams for the device in the Receive and
Transmit modes are shown in Figures 2 and 3.

• A single chip contains both the Encoder and Decoder.
• Oscillator stability is non·critical, 5% components
may be used.
• Cross interference of receivers in close proximity is
virtually eliminated by circuitry which requires 4 valid
words to be received, each within 64 ms of the other.

"1"

-I

!-0.96ms'
'@

100 kHz Osc.

Figure 1. Output Waveform
J.11V

7-11V

lOOk

lOOk

18

Vcc----'l{I/'y..,
REC.OUTPU1--+_
REC.IOPU1---\-...
180pF

180pF

GND

--I>--ill--+

DSC--\---'

CODE SW
INPUTS 1-12

CODE

sw

INPUTS 1·12

10

RECEIVER CODE SW INPUT MUST BE SET TO SAME COMBINATION AS TRANSMITTER

TRANSMITTER CODE SW INPUTS MUST BE SET TO SAME COMBINATION AS RECEIVER

Figure 2. Pin Connections for Receiver Mode

Figure 3. Pin Connections for Transmitter Mode

5-278

Design Specifications
Storage Temperature
-65 DC to + 125 DC
Operating Temperature
-25·C to + 70·C
Lead Temperature, Max. (Soldering, 10 seconds)
+300·C
Power Supply
Vss + 7V to Vss + 11 V
Voo
12mA Max.
100

Electrical Characteristics
Parameter

Conditions

Input Voltage Levels
Schmitt Trigger Input

Level
Level
Level
Level

All Other Inputs

1
0
1
0

Input Resistor to Voo
Output Voltge (trans/rec)
Logic High "1"
Logic Low "0"

18·Pin DIP -

Units

Vss+2
Voo
Vss+0.5

V
V
V
V

1.2M

Q

Vss+4
Voo-0.5
Vss
200k

ISOURCE 5,..A
ISINK 2mA

Oscillator Frequency

Max.

Typ.

Min.

Voo-0.5
Vss

±15% exclusive of
external cornponents

Voo
Vss + 1.0
100

Top View

Pin Functions

181-- VCC

kHz

Pin #
DATA SELECT LINE -

1

DATA SELECT LINE -

2

171-- RECEIVE/TRANSMIT OUTPUT

1·12 These Data Select lines are used to set the address
of the encoder/decoder pair. They have on·chip pull·
ups and input switches should pull them to ground.

DATA SELECT LINE -

3

161-- RECEIVE INPUT

13

DATA SELECT LINE -

4

151-- MODE SELECT'
141-- VSS (GROUND)

DATA SELECT LINE -

5

DATA SELECT LINE -

6

131-- R.C. INPUT (OSCILLATOR)

DATA SELECT LINE -

7

121-- DATA SELECT LINE

DATA SELECT LINE -

8

DATA SELECT LINE -

9

I-- DATA SELECT LINE
10 I-- DATA SELECT LINE
11

14

Vss is the Ground Pin.

15

The Mode Select pin changes operation of the IC
from Receiver to Transmitter. By grounding pin 15
the IC is put in the Receiver mode. By connection
to Vee the IC is put in the Transmitter mode.

16

The Receiver input receives the digital PCM wave·
form from the Detector circuit.

17

The Output pin produces the PCM waveform when
in the Transmit mode and is active low in the Re·
ceive mode.

18

Vcc is the positive supply pin.

'a. GROUND CONNECTION IS RECEIVER MODE
b. VDD CONNECTION IS TRANSMITTER MODE

Order Number MM53200N
See Package 20

5·279

The R.C.lnput is the connection point for the single
pin Oscillator. A resistor is hooked from this pin to
Vce and a capacitor from this pin to GND. The fre·
quency = 2/RC. The frequency may be decreased
by increasing the resistor value.

o

~ ~National
~ ~ Semiconductor

Electronic Data Processing
PRELIMINARY

~

MM54240 Asynchronous Receiver/Transmitter
Remote Controller

General Description
The MM54240 is a monolithic MaS integrated circuit utilizing N-channellow-threshold, enhancement mode and ionimplanted depletion mode devices. The circuit is designed
for processor-type remote control applications. The data
transmission consists of a pulse-width modulated serial
data stream of 18 bits. This stream conSists of 7 address
bits, 1 command bit, 8 data bits, 1 parity bit and 1 dummy
bit in that order.
The MM54240 can be operated in either one of two modes;
namely "master" and "slave". The master works directly
from a processor bus structure. It is capable of polling and
controlling 128 slave circuits. The slave circuits are interfaced to remote data sources and/or data destinations.

Applications

microprocessor units, remote digital transducer or remote
data peripheral devices.

Features
• Supply voltage range - 4.75V to 11.5V single supply
• Low quiescent current - 5.0.mA maximum
• On-chip oscillator based on inexpensive R-C
components
• Pulse·width modulation techniques minimize error and
maximize frequency tolerance
• Mode input for either master or slave operations
• Chip select (CS) input in the master mode
• Selectable output port options in the slave mode

The MM54240 finds application in transmitting data to
and receiving data from remote A-to-O converters,'remote

Functional Block, Diagram
Pin Configuration

4
5
6
8

.....ovoo

rvss

10
11
12

Serial
Mode

13
14
15
16
17
18
19

VOD

20
21
22

OS

5-280

MODE

Vss
D8
D7
D6
D5
D4
D3
D2
D1

23
24

CS
RIC1
WIC2

S
OSC
A7
A6
A5
A4
A3
A2
A1

Absolute Maximum Ratings
(exceeding these ratings could result in permanent damage to the
device)
Voltage on Any Pin
with Respect to Vss
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)

-0.5Vto +12.0V
- 40·C to + 85·C
-65·Cto +150·C
300·C

Electrical Characteristics TA within operating range, Vss=OV
Symbol

Parameter

. Conditions

Min

Voo

Supply Voltage

100

Supply Current, Quiescent

Voo= 4.75V to 11.5V

V IL
V IH
V IH

Input Voltage
Logic "0"
Logic "1"
Logic "1"

Voo= 4.75V to 11.5V
Voo= 4.75V to 5.25V
V oo =5.25V to 11.5V

O.
2.4
V oo -2.85

IOL
IOH
IOH
IOH

Output Current (01-08)
VOL=0.4V
VOH=2.4V
Vo H =0.5V oo
Vo H =0.6 Voo(Weak V OH )

V oo =4.75V to 11.5V
Voo = 4.75V to 5.25V
Voo= 5.25V to 11.5V
Voo = 4.75V to 11.5V

2.0
200
200
0,5

IOL

Output (CS Slave)
VOL=0.5V

Voo=4.75V to 11.5V

0.4

F
F

Frequency RC Input
For a Fixed (RC)1
For a Fixed (RC)2

V oo =4.75V to 7.0V
Voo = 7.0V to 11.5V

200
200

IOL
ILEAK

Output Current (Serial)
VoL =0.4V
Open Drain Leakage

V oo =4.75V to 11.5V
V oo =4.75V to 11.5V

2.0

V oo =4.75V to 11.5V

15

Typ

Max

4.75

Units

11.5

V

5.0

mA

0.8
Voo
Voo

V
V
V

30

mA
p.A
p.A
p.A
mA

400
400

600
600

kHz
kHz

10

mA
p.A

100

p.A

Input Pull-Up Resistors
IlL·

VIN=VSS

Typical Application

(

A

DATA
BUS

I

/8

'1
ADDRESS

/7
I

PRDCESSDR

,
.
,

A

...

~

r

K

~

)

r---

.. ...

)

MASTER
MM54240

~

ES
iN

-

R
S

SLAVE #1
MM54240

SLAVE #128
MM54240

.

I

PERIPHERAL

I

H
ADDRESS
H ~ STRAPPED

':.!:'

A-

.

,

K~NC

.

~NC

..... NC

5-281

PERIPHERAL

Circuit Description
Read/Control 1 (RtC1): In the master mode, while CS is
active low, this input can be used to initiate either of the
following three operations depending upon the present
status of the circuit.

The MM54240 consists of four major logic blocks: Sequential Control, Shift Register, PWM Encoder and PWM
Oecoder.
Data Ports (01-08): The data ports are for input and output of data and there are three output levels. In addition to
the standard high and low states when the outputs are
driving an external circuit, the outputs can also be in a
weak pull-up state to VDD . For the master circuit, the outputs are configured with standard high and low states
coincident with properly enabled CS and R. This permits
direct interface or buffered interface with the standard
bus structure of a processor system. The first three data
ports (01,02,03) also serve as status pins coincident with
enabled CS and S.' For the slave Circuit, specialized input
and output options are available by selecting the C1 and
C2 inputs.

1. Toinitiateareadcommand
2. To enable output ports if transmission received is
valid
3. To terminate read command if transmission received
is incorrect
In the slave mode, this Input, together with iN/C2, selects
the specialized output port configuration.
Write/Control 2 (W/C2): In the master mode, while CS is
active low, this input can be used to initiate a write command. In the slave mode, this input, together with R/C1,
selects the specialized output port configuration.

Address Ports (A1-A7): The address ports are.iorthe input
of address information into the MM54240. For the master
circuit, the input must be valid during the Rand iN command strobes. For the slave circuit, a unique hard-wired
code must be on the address ports. This code is theaddress of the slave circuit for addreSSing purposes.

Status (5): In the master mode while CS is active low, this
input enables circuit status information to be output ·at the
first three data ports. The other five data ports will be at
logic "0". In the slave mode, this input sets all the output
(01-08) latches to the logiC "1" state.

Mode: This input is low for slave and high (or open) for
master selections. An internal pull-up resistor is provided.

RC: This input is for connection to a resistor-capacitor
circuit for the on·chip oscillator. Frequency tolerance is
specified for two voltage ranges. In
master-slave
system, if no one circuit has a frequency more than a factor of 2 different from any other circuit, then, valid
transmission is guaranteed. Nominal setting is 400 kHz.

a

Chip Select (65): In the slave mode, this pin will become
an output and will indicate logic "0" when the circuilis expecting to receive a transmission. In the master mode,.the
CS input has to be pulled low before the R, iN or Sstrobes
can be acknowledged. An internal pull-up resistor is
provided.
* The other data ports will output logic "0".

Serial: Input and output pin for serial transmission. Output has open drain configuration.

Data Format
1. Serially transmitted data

7 ADDRESS BITS

RiW
COMMAND

8 DATA BITS

PARITY

0= READ
1 = WRITE

DUMMY

EVEN
PARITY

2. Pulse Width Modulation Coding

'"'I.---~ 100% ---'-"'''~I

LOGIC "0"

LOGIC "I"

L

---'1

-l.

37.5%

1~62.5% .:1

L

I___-------II
I--- ---I
62.5%

37.5%

I---

A bit is equivalent to 96 clocks of the R-C oscillator frequency i.e.; when R-C frequency
1 word 4.32 ms.

=

5-282

=400 kHz, 1 bit =240 /LS,

Circuit Description (Continued)
Slave Circuit Logic Flow Diagram

SPECIALIZED OUTPUT OPTIONS FOR SLAVE CIRCUITS
C1

C2

1
0
0

1
1
0

1

0

Description

All 8 pins are high impedance input port,s
All 8 pins are standard low impedance output ports
D1-D4 are standard low impedance output ports
D5-D8 are high impedance input ports
• Logic "0" outputs are low impedance output ports
Logic "1" outputs are weak pull,ups to V DD

* In

this option, the slave data ports can be connected in a wired-OR configuration with
open-collector or open-drain outputs on the peripheral.

Master Circuit Logic Flow Diagram

5-283

Switching Time Waveforms
Master Write Operation

Mas.ter Read Operation

ADDRESS

DATA

SERIAL

-;,~~;~~: --ti--_T ••iD;;E;~V,il;C~TE IN" -~-I-----WAITING TDRH:mrE+·----j-----D',.nv+. - - - - - ,

* During "waiting to receive" state, Cscoupled with R/C1

t1-there is no overlap requirement for CHIP SELECT

will force devIce into the device ready state

t2-de1ay between master-slave transmission 0.2 mS to
1.4 ms

* * If address or parity do not match, the data invalid state is
entered. CS coupled with R/C1 will farce device into the
. device ready state

5·284

~National

Electronic Data Processing

~ Semiconductor
MM57109 MOS/LSI Number-Oriented Processor
General Description

Features

The MM57109is an MOS/LSI number-oriented processor
(actually, a pre-programmed single-chip microcomputer
member of National's COP family) intended for use in
number processing applications_ Scientific calculator
functions, test and branch capability, internal number
storage, and input/output instructions have been combined in this single chip device_ Programming is done in
calculator keyboard level language which simplifies
software development_ Generated code is more reliable
because algorithms are preprogrammed in an on-chip
ROM_ Data or instructions can be synchronous or asynchronous; I/O digit count, I/O notation mode, and error
control are user programmable; a sense input and flag
outputs are available for single bit control.

• Scientific calculator instructions (RPN)
• Up to 8-digit mantissa, 2-digit exponent
o Four-register stack, one memory register
• Trigonometric functions, logarithmic functions,

The MM57109 can be used as a stand-alone processor
with external ROM/PROM and program counter (PC).
Alternatively it can be configured as a peripheral device
on the bus of a microprocessor or minicomputer_

Applications
• Instruments
• Microprocessor/minicomputer peripheral
• Test equipment
• Process controllers

yx, eX, 1f, etc.

• Error flag generation and recovery
• Flexible input/output
• HOLD input allows asynchronous instructions or
single stepping
• Asynchronous digit input instruction (AIN) with
data ready (ADR) input
• Multidigit I/O instructions (IN, OUT) with floating
point or scientific notations
• Programmable mantissa digit count for IN, OUT
instructions
• Sense input and flag outputs
• 8ranch control
• Conditional and unconditional program branching
• Increment/decrement branch on non-zero for
program loops
• Interface simplicity
• Single 
3

R!Vi
~_ _~.-_DAS

"

OM

fiR
POR

MM57109

1

21 Voo

ISH

STACKj .. DlGITMANTISSA

20 004

HOLD

"

19

11

18

ROV 12

ERROR 13

F2

8 "}
.

OA2

22[jAS

OSC

POR

osc

24 J6 /JC

IS/ill

RNi

OAI

OOJ

002

16/JC

---------.J

CONTROL
LOGIC

MEMORY

15/m--------~
14/D4----~---~

11 001

IJ/DJ

16 Fl

IZ/o2

----i- T
Y -> Z
X->Y
d -> X
See description of number entry on page 12.

00
01
02
03
04
05

1
2

3
4

Move

OCTAL OP
CODE

1

2
3
4
5
6
7

8.
Digits that follow will be mantissa fraction.
Digits that follow will be exponent.
Change sign of exponent or mantissa.
Xm = X mantissa
Xe = X exponent
CS causes -Xm -> Xm or -Xe -> Xe depending
on whether or not an EE instruction was
executed after last number entry initiation.
3.1415927 -> X, stack not pushed.
Terminates digit entry and pushes the stack.
The argument entered will be in X and Y.
Z->T
Y->Z
. X->Y
Do nothing instruction that will terminate digit
entry.
External hardware detects HALT op code and
generates HOLD = 1. Processor waits for HOLD
= 0 before continuing. HALT acts as a NOP and
may be inserted between digit entry instructions
since it does not terminate digit entry.
Roll Stack.

Pop Stack.
Y->X
Z->Y
T->Z
O->T
Exchange X and Y.
X~Y

5·297

Exchange X with memory.
X+-?M
Store X in Memory.
X-> M
Recall Memory into X. Stack is pushed.
M->X->Y->Z->T
X mantissa is left shifted while leaving decimal
point in same position. Former most significant
digit is saved in link digit. Least significant digit
is zero. Former link digit is lost.
X mantissa is right shifted while leaving decimal
point in same position. Link digit, which is
normally zero except after a left shift, is shifted
into the most significant digit. Least significant
digit is lost.

Functional Description

(Continued)

TABLE III. MM571091NSTRUCTION DESCRIPTION TABLE (CONTINUED) (*INDICATES 2-WORD INSTRUCTION)
CLASS
Math

SUBCLASS
F (X,Y)

MNEMONIC*

+

71

Plus

Minus
Times
Divide
Yto X
Memory Plus

F (X,M)

YX
INV +*

F (X) Math

INV-*
INV x"
INV 1*
l/X

40,72
40, 73
40, 74
67

Memory Minus
Memory Times
Memory Divide
One Divided by X

64

F (X) Trig

SORT
SO
lOX
EX
LN
LOG
SIN

44

Square Root
Square
Ten to X
e to X
Natural log of X
Base 10 log of X
Sine X

COS
TAN
INV SIN'
INV COSo
INV TAN"
DTR
RTD
MCLR

45
46
40,44
40,45
40,46
55
54
57

Cosine X
Tangent X
Inverse sine X
Inverse cosine X
Inverse tan X
Degrees to radi ans
Radians to degrees
Master Clear

ECLR
JMP"

53

Error flag clear
Jump

TJC*

20

Test jump
condition

TERR*

24

Test error flag

TX = 0*

21

Test X = 0

TXF*

23

Test IXI < 1

TXLTO*

22

Test X < 0

Clear

Test

63
62
61

65
66

25

DESCRIPTION

FULL NAME

72
73
74
70
40, 71

x
/

Branch

OCTAL OP
CODE

5-298

Add X to y_ X + Y -+ X. On +, -, x, / and YX
instructions, stack is popped as follows:
Z ... Y
T-+Z
O"'T
Former X, Y are lost.
Subtract X from Y. Y - X'" X
Multiply X times Y. Y x X -+ X
Divide X into Y. Y -i- X -+ X
Raise Y to X power. yX -+ X
Add X to memory. M + X'" M
On INV +, -, x and / instructions, X, Y, Z,
andT are unchanged. Former M is lost.
Subtract X from memory. M - X'" M
Multiply X times memory. M x X -+ M
Divide X into memory. M -i- X'" M
1 -i- X -+ X. On all F (X) math instructions Y, Z,
T and M are unchanged and previous X is lost.
v'x -+ X
X2..,. X
lOX ... X

eX -+ X
In X'" X
log X -+ X
SIN(X) -+ X. On all F(X) trig functions, Y, Z, T,
and M are unchanged and the previous X is lost_
COS(X) -+ X
TAN(X) -+X
SI N-l (X) -+ X
COS-l (X) -+ X
TAN-l(X) +X
Convert X from degrees to radians.
Convert X from radians to degrees.
Clear all internal registers and memory; initialize
I/O control signals, MDC = 8, MODE = floating
point. (See INITIALIZATION.)
0-+ Error flag
Unconditional branch to address specified by
second instruction word. On all branch instructions, second word contains branch address to
be loaded into external PC.
Branch to address specified by second instruction word if JC (16) is true (=1)_ Otherwise,
skip over second word_
Branch to address specified by second instruction word if error flag is true (= 1). Otherwise,
skip over second word. May be used for
detecting specific errors as opposed to using the
automatic error recovery scheme dealt with in
the section on Error Control.
Branch to address specified by second instruction word if X = O. Otherwise, skip over second
word.
Branch to address specified by second instruction word if .IXI < 1. Otherwise, skip over
second word. (i_e. branch if X is a fraction.)
Branch to address specified by second instruction word if X < O. Otherwise, skip over second
word.

Functional Description

(Continued)

TABLE III. MM571091NSTRUCTION DESCRIPTION TABLE (CONTINUED) (* INDICATES 2·WORD INSTRUCTION)

CLASS

SUBCLASS

Branch

Count

I/O

MUlti-digit

MNEMONIC*

OCTALOP
CODE

IBNZ

31

DBNZ

32

IN"

27

OUT"

26

I/O

Single-digit

AIN

16

I/O

Flags

SF1
PFI

47
50

SF2
PF2

51
52

PRWI

75

PRW2

76

TOGM

42

SMDC'

30

INV"

40

Mode
Control

FULL NAME

DESCRIPTION

Increment memory M + 1 -+ M. If M = 0, skip second instruction
and branch if
word. Otherwise, branch to address specified
by second instruction word.
M 0
Decrement
M - 1 -+ M. If M = 0, skip second instruction
memory and
word. Otherwise, branch to address specified
branch if M 0
by second instruction word.
Multidigit
The processor supplies a 4-bit digit address
input to X
(DA4-DA 1) accompanied by a digit, address
strobe (DAS) for each digit to be input. The
high order address for the number to be input
would typically come from the second instruction word. The digit is input on D4-D I, using
ISEL = 0 to select digit data instead of instructions. The number of digits to be input
depends on the calculation mode (scientific
notation or floating point) and the mantissa
digit count (See DATA FORMATS and INSTRUCTION TIMING). Data to be input is
stored in X and the stack is pushed (X-+ Y -+
Z -+ T). At the conclusion of the input, DA4DAI = O.
Multidigit output
Addressing and number of digits is identical to
from X
IN instruction. Each time a new digit address is
supplied, the processor places the digit to be
output on D04-DOI and pulses the R/IfJ line
active low. At the conclusion of output, D04DOl = 0 and DA4-DA 1 = O.
Asynchronous
A single digit is read into the processor on 04Input
01. ISE L = 0 is used by external hardware to
select the digit instead of instruction. It will not
read the digit until AD R = 0 (lSE L = 0 selects
ADR instead of 15), indicating data valid. F2 is
pulsed active low to acknowledge data just read.
Set Flag 1
Set Fl high, i.e. Fl = 1.
Pulse Flag 1
Fl is pulsed active high. If Fl is already high,
this results in it being set low.
Set Flag 2
Set F2 high, i.e. F2 = 1.
Pulse Flag 2
F2 is pulsed active high. If F2 is already high,
this results in it being set low.
.
Pulse RtW 1
Generates R!W active low pulse which may be
used as a strobe or to clock extra instruction
bits into a flip·flop or register. '
Pulse R/W 2
Identical to PRWI instruction. Advantage may
be taken of the fact that the last 2 bits of the
PRWI op code are 01 and the last 2 bits of the
PRW2 op code are 10. Either of these bits can be
clocked into a flip-flop using the R!W pulse.
Toggle Mode
Change mode from floating .point to scientific
notation or vice-versa, depending on present
mode. The mode affects only the I N and OUT
instructions. Internal calculations are always in
8-digit scientific notation.
Set Mantissa
Mantissa digit count is set to the contents of the
Digit Count
second instruction word (=1 to 8).
Inverse Mode
Set inverse' mode for trig or memory function
instruction that will immediately follow; Inverse
mode is for next instruction only.

'*

'*

5·299

Functional Description

(Continued)
TABLE IV. MM57109 INSTRUCTION SUMMARY TABLE (* INDICATES 2·WORD INSTRUCTION)
1615

1

14-1

00

01

10

11

a

TJC'

0001

1

TX=O'

0010
0011

2
3

TXLTO*
TXF*

4
5

JMP'

TOGM
ROLL
SIN (SIN-I')
COS (COS- 1'j

6
7

OUT'
IN'

TAN (TAN-l*)

LOG

SFI

l/X

8

YX

0000

0100
0101
0110
0111

TERR*

INV'
.' EN

1000
1001
1010

9

SMOC'
IBNZ'

OP

OBNZ'

PFI
SF2
PF2

1011

EE

XEM

EcLR

1100

cs

1101

PI

MS
MR

1110

AIN

1111

HALT

XEY
EX
lOX
SQ
Note 1: HALT is same as NOP except it does not terminate
number entry. External hardware must generate HOLD = 1
to halt.
Not. 2: ISEL' =
for AIN. all 2-word instructions except
SMOC.

SQRT
LN

a

Note 3: All instructions with 16 15 = 00. do not terminate
number entry. Other instructions do terminate number entry.

+(M+*)

,

-(M-*)
x (MX')

RTD

I (Mi*)
PRWI

LSH

OTR
POP

RSH

MCLR

NOP

PRW2

TABLE V. INSTRUCTION EXECUTION TIMES
EXECUTION
INSTRUCTION
TIME
MNEMONIC
(MICROCYCLES)
(AVERAGE)

EXECUTION
EXECUTION
EXECUTION
INSTRUCTION
TIME
TIME
TIME
(MICROCYCLES)
MNEMONIC
(MICROCYCLES) (MICROCYClES)
(AVERAGE)
(WORST·CASE
(WORST·CASE
VAL.UES)
VALUES)

0-9

238

OUT

583

OP

152

IN

395

EE

151

SFI

163

CS

166

PFI

185

PI

1312
134

SF2

163

HALT

185

AIN

284

PF2
·PRWI

TJC

208

PRW2

130
130
95900

TX=O

278

SIN

TXLTO
, TXF

197

COS

56200

95900

271

TAN

35000

97600

TERR
JMP

191

INVSIN

54000

93900

186

INV COS

54000

93900

IBNZ

2314

INVTAN

30200

92900

56200

OBNZ

2314

LN

24800

SMOC

, 92000

163

LOG

30700

92600

XEM

812

EX

30800

93900

MS

839

lOX

27400

96500

MR

1385

+.-

2200

6600

LSH

168

1700

5000

RSH

173

INV+.INV(M+.M-)

22700

INV

' .

552

x'
INVx (MX)

3200

EN

166

2700

21400

TOGM

157

I

ROLL

905

INV I (M/)

7800
7300

22300
21100

ECLR

163

l/X

4500

22800

POP

448

YX

55400

95500

MCLR

734

SQRT

·7000

30200

XEY

652

SQ

3000.

21900

NOP

122

OTR.RTO

9600

41700

Note 1:' 'AII times are measured,from leading edge of ready for first word of the instruction to leading edge of ready for first word of the next
instruction. (Hold = 0).

Note 2: Add ,67 microcycles to the executi~n time of any instruction which initiates number entry and is preceded by an ENTER instruction.
Note 3: Add 482' microcycles to, ,the execution ,time of any instruction which initiates number entry and is not preceded by an ENTER

instruction.
'
Note 4: Add 1003 m~crocy~les. to the execution time of a~y instruction whi~h terlJ1inates number e~.try.
Nota 5: The execution time of each instruction is a function of the internal state of the device and is not necessarily related to the number of
digits in the operand. It is not possible to predict precisely what the execution time will be for any given instruction. This table shows worst-case
values for basic instructions, and both average and worst-case values for mathematical instructions.

5·300

Functional Description

(Continued)

--l
--l•

HOLD (INPUT)

EXECUTION TIME
ROY (OUTPUT)

n ....._____

RDV (OUTPUT!
ISEL (OUTPUT)

(HIGH FOR ENTIRE INSTRUCTION)

ISH (OUTPUT!

.JX'-____,--_____--'X'-_____

16- 11 (INPUTS)

tHIGH FOR ENTIRE INSTRUCTION)

:::::::x____________-'X'-______

',-', (INPUTSI _ _ _ _

•
POINTS

DESCRIPTION

ROY pulsed to indicate ready for next
instruction.

A

Instruction is plC_______...J>---::z:._==__<

'------

DESCRIPTION

ROY (OUTPUT)

C

Instruction is placed on I lines.
ISEL goes low for second word.
Second instruction word (= branch

D

becomes available to external program counter.
I .lines at this time are don't care, (exception:

E

for T JC instruction 16 (= JC) must contain the
jump condition signal during this time).
ISEL goes high prior to ROY pulse for next

B

ISEl (OUTPUT)

address)

instruction.

(b) Timing Characteristics for TJC, TX = 0, TXLTO, TXF,
TERR, IBNZ, and DBNZ with Branch Condition False
ROV (OUTPUT!

ISEl (OUTPUT)

DRlDUTPUT)

Next instruction is placed on I lines.

(e) Timing Characteristics for SMDC Instruction

POINTS

A

new MOC. (1-8).

C

U

16 = "JUMP CONDITION"

FOR TJC INSTRUCTI0ct-~~='~<=====
....JX'-______
....Jr=...'c

ADR i l N P U T ) - - - - - - - - - " - - - - . L - j

o

,>-____

(OU:P~~~; _ _ _ _ _ _ _ _ _- ' ' -_ _ _ _ _ _

F

F2(OUTPUT) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..L-,-I

B

C

DESCRIPTION

A
B

AIN instruction is placed on I lines.
ISEL goes low to select data digit on I lines.
IS and 14-11 are don't care as long as AOR
(15) = 1.

c

D

DESCRIPTION
Instruction is placed on I lines.
ISEL goes low for second word.

Second instruction word (= branch addre~s)
becomes available to external program counter.
I lines at this time are don't-care, (exception:
for TJC instruction 16 (='JCl 'must contain the
jump condition signal during this time).

E

F

o
E

H

Digit address appears on OA lines. DAS provides
1 microcycle active low pu'lse which frames DA
change. (Negative going edge occurs while DA
lines are still O. Positive going edge occurs after
DA lines have changed to their new value). The
first AIN instruction will have a digit address of
0000. Consecutive AIN instructions have digit
addresses of 0001, 0010, etc., up to 0111. In·
structions which terminate number entry reset
the internal digit address to 0000.
Data digit is placed on 04-01. AOR goes low
indicating valid data digit.
F2 is pulsed active low to indicate read of data

4-microeycle SA -active low pulse provides load
signal for external program counter.

on 04-Dl. AOR (= 15) must be low for this
pulse to occur. If ADR is high, the MMS7109

RDY leading edge occurs during BR pulse, thus

will wait till it goes low before reading the I
lines. ADR may go high again anytime after
negative going edge of F2. I lines are don't
care ~fter F2 is pulsed.
DA lines are reset to O. DAS provides a 1 microcycle pulse framing DA change.
ISEL goes high' prior 'to ROY pulse for next
instruction.
Next instruction appears on I lines.

loading program counter with branch, address.
G

u

POINTS

o

A

u

DAS(OUTPUTl

"-', (lNPUTSI _ _ _

POINTS

,

..J"-_ _J

16-11 (l1~PUTS) _ _ _ _

Next instruction appears on I lines prior to ROY
going low.
ISEL goes high for first word of next instruc-

tion, ROY pulse that usually occurs at this
time is suppressed.

(c) Timing Characteristics for TJC, TX = 0, TXL TO, TXF,
TERR, IBNZ, and DBNZ with Branch Condition True. Also
for JMP Instruction.

F
G

H

(f) Timing Characteristics for AIN Instruction

FIGURE 10, Instruction Timing Diagrams

Functional. Description

(Continued)

...,._---,r-L

ROY(OUTPUT)~_ _ _ _ _-,-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~

ISEl (OUTPUT)

________________ ______________________
~

~r----.

--~r-~--~~
16-11 (INPUTS) _ _" -_ _ _ _- '

H

OA4-0Al (oUTPUTS} _ _ _ _ _ _.,_---~'---J.'---J).---~--....J~--..J)~--~---~------

DAS(OUTPUn

POINTS

DESCRIPTION

A
8

IN instruction is placed on I lines.
ISEL goes low for second, instruction word. pata digits multiplexed onto I lines when ISEL = O. I lines are don't care until DAS pulse

C

Second word of instruction becomes available to external hardware as a high·order address for a RAM or other device.
First digit address appears on DA lines. This digit address is 0 or 2 depending on whether mode is scientific notation or floating point,
respectively. Each time a new digit address appears, a 1 microcycle active low pulse on DAS frames this change so that at the negative
going edge of DAS the old digit address is valid while at the positive going edge of DAS the new digit address is valid.
Digit data becomes valid on D4-D1 within 1/2 microcycle after DAS negative edge. Digit data must remain valid for 1 microcycle.
During this time data·is read.
Digit address advances to next digit, i.e., 0, 1, 2, 3, ... , N scientific notation or 2, 3,4, .. " N floating point
where N = MDC + 3 sci.entific notation
N = MDC + 1 floating point
(See DATA FORMATS),
Next digit is placed on 04-01, again within 112 microcycle after DAS negative edge.
All digits have been read in. Digit Address goes to 0000. DAS pulse occurs. ISEL goes high before ROY pulse for next instruction.
Number of digits read depends on'notation mode and mantissa digit count (see DATA FORMATS),

occurs.

o
E
F

G
H

(g) Timing Characteristics for IN Instruction

.JrL

RDV(DUTPUT) ~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~

ISEl {OUTPUT)

',-', (INPUTS)

________________________ ____________
c

~

~r----

,

:::)===~~>--~---------------------------------:-----DAS{oUT~UT)

......- - - - - -

D04-001 (OUTPUTS) _ _ _ _ _ _ _ _ _ _~!---~~--_'::'---~--,..-~-.,_-'~--_'::~-RM (OUTPUTI

POINTS

DESCRIPTION

A
OUT instruction is placed on I lines.
B I S E L goes low for second iflstruction word.
e
Second word of instruction becomes available to external hardware as a high order address for a RAM or other device.
D
First' digit address appears on DA lines, the same as for the IN instruction. qAS frames DA changes, as with IN instruction.
E
First digit output appears on 004-001 within 2 microcycles afte'r the negative edge of DAS.
F
R/IN active low pulse occurs to write data into RAM or other device. This is a 2 microcycle pulse occurring within 3 microcycles after
the negative edge of DAS.
G
Digit address advances to next digit, (See DATA FORMATS).
H
Next digit output appears on 004-001,14 microcycles after the last digit appeared .
. All digits have been output. Digit Address goes to 0000. ISEL goes high before ROY pulse 'for next ,instruction. Number of digits
read depends on notation mode and mantissa digit count (see DATA FORMATS),
M

(h) Timing Characteristics for OUT Instruction·
ROV (OUTPUTI----.lIL-_ _ _ _ _ _.... , L_ _ _ _ _ __

ROV (OUTPUT)

ISEl(OUTPUTI

ISH (OUTPUT)

{HIGH FOR ENTIRE INSTRUCTION)

JX'-__~_____JXI..________

',-', (lNPUTSI _ _ _ _

-'X\..___________- JX'-____

FIORF2----...;.;.A-------...,...--.,.------

U

RN{ (OUTPUT)

(HIGH FOR ENTIRE INSTRUCTION)

',-',IINPUTS) _ _ _ _

(OUTPUTS). _ _.,_------------~

B'

POINTS

DESCRIPTION

POINTS

DESCRIPTION

A

PRWl or PRW2 instruction is placed ori I lines

B

2·microcycle

A
B

SF1 or SF2 instruction is placed on I lines
Fl or F2 is set high.

Riw active low pulse occurs.

0) Timing Characteristics for PRW1, PRW2 I nstructiol')s

(j) Timing Characteristics for SF1, SF21nstructions

FIGURE 10. Instruction Timing Diagrams (Continued)

5-302

Functional Description

(Continued)

---IIlL _ _ __

Il

AOY IOUTPUTl _ _ _--1

ISEl{OUTPUn

L_______

(HIGH FOR ENTIRE

',-"IINPUTSI _ _ _ _

Ir~STRUCTIONf

I lL _ _ _..Jr--L-

AOYIOUTPUTI _ _ _ _ _ _ _ _ _.....

ISEL {OUTPUT)

~X~---------...JX\.-----

(HIGH FOR ENTIRE INSTRUCTION)

',-IIIINPUTS1 _ _ _ _ _ _ _ _ _~X~-----JX\.----

,

A

------------T'l11

Fl OR F2 _ _ _ _ _ _ _ _ _ _ _- - ' L_ _ _ _ _ _ __
(OUTPUTSI

,

ERROR FLAG
(OUTPUT) _ _ _ _~---------~------

POINTS

OESCRIPTION

POINTS

DESCRIPTION

A

PFl or PF2 instruction is placed on I lines
F1 or F2 is pulsed active high for 2 microcycles.

A

If an error occurs, ERROR is set high (see

B

Table VII.

B
C

lid Timing Characteristics for PF1, PF2 Instructions

ECLR instruction is placed on I lines.
Error flag is set low.

(I) Timing Characteristics for ECLR Instruction and Error
Occu rrenees

FIGURE 10. Instruction Timing Diagrams (Continued)
DATA FORMATS
IN/OUT Instructions
Mantissa digit count and notation mode determine data
format. Table V II shows the contents of the D, DO and
DA lines for an IN or OUT instruction. Anywhere from
4 to 11 digits will be input or output by a single instruction.
AI N Instruction
One digit is input per AI N instruction. A maximum of 8
digits may be entered into the X mantissa by using
consecutive AI N instructions. Digit entry is terminated
by EN or any function instruction, (see NUMBER
ENTRY). Table VII shows the DA lines for consecutive
AIN instructions.

SAMPLE SYSTEMS

ERROR CONTROL
The error flag, which can drive an LED indicator, is set
high upon detection of an arithmetic or output error.
(See Table VI).
TABLE VI. ERROR CONDITIONS
Error flag is Set when:
1. LN X when X < 0
LOG X when <;; 0

X

2. Any result

< 10-99

Any result

2: 10 100

3. TAN 900 , 270 0 , 450 0 , etc.
4. SIN

X, COS X, TAN X when IXI ~ 9000"
X, COS- 1 X when IXI > 1 or IXI <;; 10- 50

Figures 11-14 show sample systems using the MM571 09.
Figure 11 shows a simple demonstrator system using
switches to enter instructions. An LED display is used to
demonstrate the OUT instruction, with a switch to force
an OUT instruction on the I lines and to hold the HOLD
input low for 1 second for repeated execution of the
OUT instruction, resulting in a multiplexed display. A
flip-flop latches the BR pulse which occurs when a test
and branch instruction is true. LED lamps provide
visual indication of th'e various flags. An enter button
allows single instruction words to be entered one at a
time in the ENTER mode and causes the display to
light for 1 second in the DISPLAY mode.
Figure 12 shows a stand-alone system with external
program counter and a RAM to expand memory.

5. SIN-l

6. SORT X when X

For automatic error recovery, ERROR is wired to the
asynchronous clear input of the external program counter
(PC). The instruction at location 0 is an ECLR to clear
ERROR so that the next RDY pulse will advance the
PC to location 1. A JMP instruction at location 1 with
the branch address at location 2 of an error routine is
then executed, which results in a transfer of program
control to the error routine. These first 3 error recovery
locations are skipped over upon reset (POR) as can be
seen in the initialization and instruction fetch flowcharts.
The program shown in Table VIII shows typical error
recovery coding.

<0

7. I, INV/, 1/XwhenX=0

Figure 13 shows the MM57109 used as a microprocessor
peripheral. Latches contain instructions forthe MM57109
and digit data for the microprocessor.

8. In floating point mode OUT instruction if number
of mantissa digits to left of decimal point is greater
than the mantissa digit count.

Figure 14 shows a data acquisition system which obtains
data from a 3-digit AID converter. Figure 14(b) shows a
program which reads data from the A/D converter.
This coding should be studied as a general example of an
MM57109 program.

The error flag can be tested by the TE R R instruction
(which branches if ERROR = 1) or it can be used to
clear the external program counter, resulting in a hardware jump to location 0, the error recovery location.
In either case, an ECLR instruction must be executed to
clear the error fl ago

Figure 15 shows a microprocessor to MM571 09 interface
using 2 FIFO's for instruction and data buffering.

The occurrence of an error does not affect the operation
of the processor in any way. The OUT instruction will
not output digits if error condition 8 is true, but otherwise will output digits, even if the error flag is set.

5-303

These sample systems are not intended to be detailed
drawings of a complete system (except Figure 11). Their
purpose is to provide the designer with some ideas as to
how to use the MM571 09 in an actual system.

F,unctional Description

(Continued)

TABLE VII. DATA FORMATS
IN/OUT INSTRUCTIONS (A) MODE
IN:

DA4-DAl

OUT:

=SCIENTIFIC NOTATION

04

03

02

01

004

003

002

001

Most significant exponent digit
Least significant exponent digit
Sm
Se
Not used
Most significant mantissa digit (Decimal point follows this digit)
This digit must be non-zero on the AIN instruction unless the
entire number is zero. Failure to do this will result i~ errors in
cal~ulations. This digit will always be non-zero on the OUT

a

a

instruction, for non zero numbers.
Second most significant fTIantissa digit,

MDC +3

Least significant mantissa digit

IN/OUT INSTRUCTIONS (B) MODE = FLOATING POINT
DA4-DA1

DPX

2
3
4

11

5

10

MDC+3

12- MDC

IN:
OUT:

04

03

D2

Dl

004

003

D02

DOl

Sm
a
a
a
DP POS
Most significant mantissa digit"" 0-9. On the OUT
instruction, this digit will be non-zero unless
jXj < 1, in which case it will be zero and DP POS
will be 11. Leading zeroes are not blanked.
Second most significant mantissa digit

Least significant mantissa digit = 0-9

Notes:
MOe
Sm
Se
OP POS

=
:::

=
=

Mantissa digit count, set by SMOC instruction, initially = 8
Sign of mantissa, 0::: positive, 1 ::: negative
Sign of exponent (Se = 0 in floating point mode)
Decimal point position indicator is a value in the range from 11 down to
12 - MOC, which indicates a digit, as given by the OPX column in the
table. The decimal point is located immediately following this digit.
Example: If 'O'P POS = 10, then the decimal point follows the second most
significant mantissa digit (DPX ::: 10).

AIN INSTRUCTION
DA4-0Al

a

Most significant digit Xm (first AIN instruction)

Least significant digit Xm (eighth AIN instruction)
Note. Xm ::: X register mantissa. Decimal point follows last digit entered. An irrecoverable internal error will occur if more than 8 digits are entered in a row with AI N, or if
a non-BCD digit is entered.

TABLE VIII. ERROR RECOVERY CODING
OCTAL ADDRESS
00
01
02
03

75

OCTAL
OPCODE

LABEL

INSTRUCTION
MNEMONIC
ECLR
JMP

53
25
75

OPERAND

COMMENT

ERROR

Clear error flag
Jump to error routine
Address of label 'ERROR'

User Program

User error recovery routine

ERROR

5-304

Functional Description
Vss

(Continued)

Vss
TESTTRUE LED

GO

...L

vooJ
NC
NC
ROY
ERROR

I,
I,
I,
I,

DISPLAY
(FORCE OUT

INSTRUCTION)

VSS - VDD ~ 9.0V
Rl • Cl =0.1 sec
R2' C2;' 100!,s
R3 'C2 = 1 sec
(R2 ~ 200n, R3 = 2M)

MM57109

DO'

Vss

ZD

"
DO'

00'
001

CD45117·SEIlMENT
DECODER/DRIVER

18

17

6 INSTRUCTION SWITCHES
SHOWN IN POSITION:
OoDODo

oscl-!---------,

OA1-DA4

All resistors are 10k-20k
unless otherwise specified

13

I.
'I
F> I'

Vss

VooD--O

12

28272625

VOoo-~-----~JV~_t_t_r~

Operation:

1. To display, put switch in "DISPLAY" position
and press "GO". Display lights for 1 second.
2. To enter an instruction, set 6 instruction
switches for op code of instruction.
3. Make sure switch is in "ENTER INSTRUCTIONS" position.
4. Press "GO" button once.
5. If a 2-word instruction, set switches for second
word and press "GO" again.

15
11

aSS6M

MM74C8J
ADDER

12

DIGIT DRIVER

16
13

Vss

VDD

FIGURE 11. MM57109 Sample System with Switches for Instruction Entry
JcAifR

r-__~~~C~O~UN~T~_ _ _ _

r1r-______

~ROY

050

r-_ _ _~B~R~AN~C~H_ _ _ __+_t------~m

SYNC

'D'

MM51109

INPUTS

OUTPUTS

FIGURE 12. MM57109 Stand-Alone System

5·305

Fl

FLAG 1

F2

FLAG2

Functional Description

(Continued)

HOLD FLAG

HOLD

WRITE DATA SIGNAL

I/O SElECT SIGNAL
MICRO·
COMPUTER

--

Cl.

... .......

,

...

INSTRUCTIONS

l

161

,

HEX

LATCH OUT

_A

SYSTEM DATA BUS

I/O SELECT

r-

IN

SIGNALS

.J!!...
:...-

nUAD
LATCH
IN
(TAI·STATE)
OUT

.A

DIGIT DATA (4)

004-001
~

MM57109

ClK

CS

t

~~

cs

Q

DUTAOY

OUT 131

TRI.STATE·'

f-<

R/W

FF
RESET

ROY

ROY

BUFFERS

TRUE~_
FF
Q

Bii

SET

FIGURE 13(a). MM57109 as a Microcon,puter Peripheral

SUSPEND MM57109 AFTER INSTRUCTION
IS EXECUTED (ALTERNATIVE: TO USING
HOLD IS TO OUTPUT NOP INSTRUCTION
'-_-,-_......J TO LATCH)
MM57109

RM PULSE Will SET QUTROY.

QUTAOV IS CLEARED WHEN DIGIT IS READ

NEXT INSTRUCTION IS SENT TO MM57109

FIGURE 13(c). Microcomputer Software
for MM57109 OUT, Test Instructions

FIGURE 13(b). Microcomputer Software
for MM57109 Peripheral Interface

5-306

Functional Description

(Continued)
INSTRUCTION STORE

INSTRUCTION STORE

.1

START
SC

EoC

.r t

~

'n

P6

O

CONVERSION

~
ro'A

END OF
CONVERSION

ADA

Fl HOLD UA

QUAD
2-1 OUT
MUX

B

~

16-15

--y

SEL
JBCO

DIGIT

AID

CONVERTER

I~
DIGIT 1 to.
'--Cr

~

r---r'

~AQUAD

1 ______ '

3-1

F==t

I 0lGlT2

AI
A2
A3
A4
AS
A6
AI
AS

------

~

r--

MUX

B

SEL
A

I (.).

~

r--r' ....

oUTr-

~

QUAD

MM51109

,.-I,

2-1 OUT ----,j
r

MUX

B_--'

~
~
~ . r------t~~
OUT eLK

r--:it~=;--1'SEL

(')

OA4-0Al

roo-~

(31

r--

SEL ~======:t~
roo--

RM

(4)

- I-

004-001

r-

0'-01 r - -

I. (')

8·WPUT

ANALOG

A4-AI
256X4

MUX
(LATCHED
CHANNEl

~ """--

~~(.'~==~

RAM
AD-All'

SElECT)

RM 1+-1------'
(4)
I.-I,rvt-______..

,

CS~

":'

'---

...

r

,

°4TPUTS

FIGURE 14(a). MM57109 Analog Data Acquisition System Block Diagram

Acquisition System Instruction Format
TYPE OF
INSTRUCTION

17

P6

Select Analog Channel
AID Input

0

1

RAM 1/0

1

0

1

Acquisition System Coding

17

PSP4P3P2P, Po
OUT instruction
AIN instruction
IN/OUT instructions
for second word. Second
word PO-P3 are high

LOOP
-1

order RAM addresses
Others

P6

PS-PO

COMMENT

4
MS
SMDC

Number of channels to be input
Store in M
Mantissa Digit Count = 1

MR
OUT

Retrieve channel number
Select analog channel

·0

Other instructions
1

0
0

0

PF1
EN
AIN
AIN
AIN
DBNZ
LOOP

Start AID converter
Push stack
Read AID converter digit 1 when EOC = 0
Read AID converter digit 2
Read AID converter digit 3
Update channel number and check if 0

X
I

Channel 1 times channel 2 (C1 x C2)
(C1 x C2) + C3
COSINE (lC1 x C2) +C3)
C4 + COSINE ((C1 x C2) + C3)

COS

+
1
0
0

SMDC
3
OUT

Mantissa Digit Count = 3
Result to RAM (0)

0

FIGURE 14(b). MM57109 Analog Data Acquisition System Input Coding

5·307

Functional Description
~

(Continued)
---,
DATA

L

SVSTEM DATA BUS

K

BUS

':. "::::::1"

D:~:

..

...,.

FIFO
(lNSTRUCnONI

our ....._ _ _....."

IN

~ ~~~TE

OUT

----+-.....+..,..-4~~~DTy

I+":;''::;''::'O:;:'U:::''::''- - - :
,

JUMP

CONDITIO~:,

[

, ,.

1&-11

-I ROY

R~~~I+_ _ _ _

OUTPUT READY

-++---lf-___~______-.!HOLD

I+..:;'.::;"::.O:;:EM:::;PT~Y~_ _ _ _ _

INTERRUPTS

MM57109

OUTPUT DATA READY ,

OUTPUT READY

RJW

WRITE

CLK

.4

I/O

MICROCOMPUTER

loNTRO~

CONTROL
LOGIC

- : - - OUT
FIFO WRITE STROBE

'------',-

FIFO
(OUTPUTI

IN

OUT~~~11ATA

1'Ir____-tDD4-DD1

,

-y-

FIGURE 15. MM57109 Microcom'putednterface Using 2 FI FO's
Getting Your MM57109 Going
After wiring up a system using an MM571 09. the following steps should be followed to verify that the processor is operating properly:
1. Check power supply for proper level, polarity, and absence of ,noise.
2. Check oscillator frequency, levels, duty CYChl an'd ri~e.arid fall,times."
3. Verify presence of SYNC output.
4. Check POR reset pulse duration. levels and rise and fall times.
5. Put HOLD input high and verify that RDY stays high.
6. Put HOLD input low and verify that RDY is pulsing active high.
7. Check that the system'places the proper instructions on the I lines.
8. Force an OUT instruction on the I lines, put. HOLD Ipw. apply a reset pulse, and verify that D04, D02, DOl DA-DA 1. DAS and
R/W are changing.
. '

.5-308

Electronic Data Processing

~National

~ Semiconductor
MM57436 Decimal/Binary Up/Down Counter

General Description

Features

The MM57436 Counter, an NMOS silicon gate technology
device, is designed to be a minimal solution Decimal!
Binary Up!Down counter with display capability. The
counter length is user selectable at 4 digits decimal (16
bits binary) or a digits decimal (32 bits binary). The device
has the capability of direct drive of a 4 digit multiplexed
LED display. In the a·digit (32·bit) mode, the user may di·
rect either the top four digits or lower four digits to the
display. The MM57436 will run off an internal RC oscillator
or the user may supply an external oscillator for greater
precision in the count rate.

• Decimal or binary count
• Up or down count
• 4 or a digit (16 or 32 bit) counter length
• 4 digit, seven segment multiplexed LED display drive
• User display control
• Single supply operation
• Wide supply range (4.5V-9.5V)
• TTL compatible on inputs

r- D3

GNDl _

1

24

VCC2 -

2

231-- D2

DSCIN -

3

221-- Dl

RESET -

4

211-- DO

-

5

20

Sg -

6

Dm~~~

I--

S1- 7

GND2
4/B DIGIT DECIMAL
191- (16/32 BIT BINARY)
18 I - UP/DOWN

So -

8

171- DECIMAL/BINARY

VCCl -

9

161- N.C.

MM57436

S d - 10

151- N.C.

Se- II

141-- COUNT

S b - 12

131- Sa

Top View
Order Number MM57436N
See Package 22

Pin

Description

OSCIN

Oscillator Input RC

External Oscillator or

Display
Select

Control line to display upper or lower 4
digits (16 bits) of a-digit (32·bit) counter

SA-SG

Multiplexed 7-segment outputs

COUNT

Input for signal to be counted

Decimal!
Binary

Counter mode control

Up/Down

Up·down count control

4!a Digit
(16!32 Bit
Binary)

Counter length control

Do-D3
VCC1 , VCC2

Power supply

GND1,
GND2

Ground

Display digit strobes

Figure 1. Connection Diagram

5-309

Absolute Maximum Ratings
Voltage at Any Pin Relative to GND 1
Ambient Operating Temperature
Ambient Storage Temperature
Lead Temperature (Soldering, 10 Seconds)
Power Dissipation

-0.3V to + 10V
O°Cto +70°C
-65°Cto +150°C
300°C
0.75 Watt at 25°C
0.4 Watt at 70°C

"Absolute Maximum Ratings" indicate limits beyond which
damage to the device may occur. DC and AC electrical specifica·
tions are not ensured when operating the device at absolute
maximum ratings.

DC Electrical Characteristics

O°C ",'TA '" 70°C, 4.5V '" Vce '" 9.5V, unless otherwise specified

Conditions

Parameter

Min.

Operating Supply Current
Input Voltage Levels
OSC IN, RESET Levels
Logic High (V IH )
Logic Low (VIL)
RESET Hysteresis
All Other Inputs
Logic High (VIH )
Logic High (V IH )
Logic Low (VILl
Output Current Levels
Output Sink Current
Do·D 3 {loll
SA,SG (loll
Output Source Current
SA,SG{lOH)

Typ.

4.5

Operating Voltage (Veel
Vce=5V, TA = +25°C
(all inputs and outputs open)

Max.

Units

9.5

V

5.0

mA

0.6

V
V
V

0.7Vee
1.0
3.0
2.0

Vee=9.5V
Vee=5V ± 10%

Vee =
Vee =
Vee =
Vee =

9.5V,
4.5V,
9.5V,
4:5V,

VOL =
VOL =
VOL =
VOL =

1.0V
1.0V
1.0V
1.0V

Vee = 9.5V, VOH = 2.0V'
Vee = 6.0V, VOH = 2.0V

0.8

V
V
V

30
15
2.0
1.0

150
70
9.0
4.5

mA
mA
mA
mA

-3.0
-3.0

-30
-20

mA
mA

AC Electrical Characteristics o°C '" TA '" 70°C, 4.5V '" Vee'" 9.5V, unless otherwise specified
Parameter

Conditions

Min.

OSCIN
Frequency
Duty Cycle
Rise Time
Fall Time
Internal Time Base
(= 4/Frequency)
OSC IN Using RC
Frequency
Internal Time Base
(= 4/Frequency)

R=56kR±5%,
C=100pF±10%

Inputs
Up/Down, Display Select
tSETUP
t HOLD
Count
tSETUP
t HOLD

5·310

Typ.

Max.

Units

100
40

266.67
60
1
1

kHz
%
,..s
,..s

15

40

,..s

140

266.67

kHz

15

28

,..s

8
1

,..s
,..s

2
1

,..s
,..S

AC Electrical Characteristics
Parameter

(continued) 0 'C'; TA'; 70 'C, 4.5V'; Vee'; 9.5V, unless otherwise specified

Conditions

Count Input Frequency

Min.

Typ.

Max.

Units

14.4
5.43

kHz
kHz

13.6
5.13

kHz
kHz

9.52
3.57

kHz
kHz

9.17
3.44

kHz
kHz

16.3
6.14

kHz
kHz

15.3
5.76

kHz
kHz

11.2
4.21

kHz
kHz

10.3
3.86

kHz
kHz

Pulse Width
(= 8/aSC IN Frequency)

asc IN = 100kHz
asc IN = 266.67 kHz

80
30

flS
flS

RESET Input Pulse Width

Resetting device while
device running
asc IN = 100kHz
asc IN = 266.67 kHz

160
60

flS
flS

Functional Description
Up/Down - With this pin left open or at a logic "1"
(positive logic) the MM57436 will increment its internal
counter by 1 with every pulse input at the CaUNT input.
With this pin connected to ground or to a logic "0"
(positive logic), the MM57436 will decrement its internal
counter by 1 with every pulse at the CaUNT input. This
input may be tied high or low, may come from a switch
or may be controlled by a logic signal. It may be changed
by the user at any time. Note, if this input is to be controlled by a mechanical switch some external debounce
protection may be required depending on the application.
There is no debounce protection internally on this input.

The display is standard, seven·segment for the decimal
counter. In the binary mode, hex characters are displayed
as follows:
0·9,

A,

b,

C,

d,

E,

F

The mode controls of the MM57436 are as follows:

Display Select - With this input tied to Vee or at a logic
"1 ", the MM57436 will display the upper 4 digits (16 bits)
of the 8 digit (32 bit) counter. Connecting this pin to
ground or to a logic "0" will cause the lower 4 digits of
the 8 digit counter to be displayed. If the MM57436 is
operating as a 4-digit counter (pin 19 open or at Vecl the
Display Select input is ignored and has no effect whatsoever on the display. This input may be hard wired to
either Vee or ground; may be controlled by a switch or
may be controlled by a logic signal. The input may be
changed at any time by the user without impairing the
operation of the device.

Decimal/Binary - With this pin left open or tied to Vee,
the MM57436 is a decimal counter. Connecting this pin
to output D1 converts the MM57436 to a binary counter.
This mode is a strap option and may not be changed
while the device is running.
4/8-Digil Decimal (16/32-Bit Binary) - With this pin left
open or tied to Vec the MM57436 is a 4-digit decimal or
16-bit binary counter. Connecting this pin to ground
converts the MM57436 to an 8-digit decimal or 32 bit
binary counter. The counter length is a strap option and
may not be changed while the device is running.

5-311

......
~

4 Digit Decimal Up Count
asc IN = 266.67 kHz
asc IN = 100kHz
4 Digit Decimal Down Count
asc IN = 266.67 kHz
asc IN = 100kHz
8 Digit Decimal Up Count
asc IN = 266.67 kHz
asc IN = 100kHz
8 Digit Decimal Down Count
asc IN = 266.67 kHz
asc IN=100kHz
16 Bit Binary Up Count
asc IN = 266.67kHz
asc IN=100kHz
16 Bit Binary Down Count
asc IN = 266.67kHz
asc IN = 100kHz
32 Bit Binary Up Count
asc IN = 266.67 kHz
asc IN = 100kHz
32 Bit Binary Down Count
asc IN = 266.67 kHz
asc IN = 100kHz

The MM57436 will count pulsesat its count input and will
display 4 digits of the resultant count. Under user control
the device will count in either decimal or binary and will
either count up or count down. The user may also select
which group of 4 digits (16 bits) is to be displayed.

s:
s:
en
W

en

General Operation
Initialization
The RESET logic will clear the MM57436 if the power
supply rise time is between 1 ms and 11's. If the power
supply rise time is greater than 1 ms, the user must pro·
vide an external RC network and diode to the RESET pin
as shown below(Figure 2). The RESET input is configured
as a Schmitt trigger input. The user may control this
with an external signal if desired as long as the proper
levels are maintained. The RESET pin is the means by
which the user may clear the counter. RESET may be
brought low at any time. The MM57436 will be cleared
whenever the proper "0" level is applied at the RESET
input provided the input stays low for at least 16 clock
cycles. If the reset pin is not used it should be connected
to Vcc.
+
P
0
W
E
R

Power Supply
The MM57436 has two Vcc pins: VCC1 and VCC2 - and two
ground pins: GND1 and GND2. Both VCC1 and VCC2 must
be connected to the positive supply (Vccl. Both GND1
and GND2 must be connected to ground. Failure to do
this will result in improper operation of the MM57436.

I
~~

T

Count Input

VCC2

VCC1

RESET

S
U
P
P
L
Y

The external oscillator is recommended when the counting speed and/or the stability of the counting speed is
critical. The internal RC oscillator is only accurate to
about ± 15% to ±20%. However, if practical in the
application, the RC network can be tuned for the desired
operating frequency. Some typical RC values that place
the operating speed at near the maximum are shown
below (Figure 3).

The MM57436 counts negative-going pulses at the
Count Input. The width of the negative-going (logic "1"
to logic "0") must be at least 8 times the oscillator cycle
time.

MM57436

GND1

In order to maximize the counting speed and not to miss
any pulses, during the display cycles, the MM57436 has
a 4-bit register at the COUNT input which will accumulate
up to 15 counts. This register is added/subtracted ,from
the counter. Therefore at the higher input count speeds,
when the counter is changed from an up counter to a
down counter or vice versa, there is a window of up to 15
counts- the maximum value in the input register - in
the count. This effect is completely unobservable at
slow input count speeds and gradually becomes more
noticeable as the repetition rate of the count pulse
increases. If the up/down mode is not changed during
operation, the only observable effect of the input register
is that the display may appear to increment or decrement
by values greater than 1.

GND2

1

Re " 5 x POWER SUPPLY RISE TIME

Figure 2. Power· Up Clear Circuit'

Oscillator
The user has the option of connecting an RC network to
the OSC IN pin and using the internal oscillator or he
may supply an external oscillator to the OSC IN pin. The
OSC IN input is a Schmitt trigger input and the user must
insure that the proper levels are met when supplying an
external clock.

Vee
MM57436
OSC IN

O. 7Vee
O.6V

Jlf ~

I

I

MM57436
OSC IN

t

EXTERNAL CLOCK

RC Controlled Oscillator
R(kQ) ,C(pF)

OSC IN Period (!Js)

51

100

, 4.75±15%

82

56

4.75± 13%

Figure 3. MM57436 Oscillator
5-312

Input/Output Characteristics
Inputs

Outputs

The MM57436 has three types of inputs. Figure 4a is the
input with a depletion load to Vee found on pins 17, 18,
and 19 (Decimal/Binary, Up/Down, 4/8 Digit). Figure 4b is
a slightly different type of input with a depletion load to
Vee found on pins 4 and 14 (RESET, COUNT). The remaining input, pin 5-Display Select, has no load device
(Figure 4e).

There are only two types of outputs on the MM57436:
the segment drivers (Figure 5a) and the digit drivers
(Figure 5b).

Vee

Vee

It. = DEPLETION DEVICE

INPUT

INPUT

a. Pins 17, 18, 19

b. Pins 4, 14

c_ Pin 5

Figure 4. Input Configurations

Vee

Vee

It. = DEPLETION DEVICE

b. Digit Driver Outputs

a. Segment Driver Outputs
Figure 5. Output Configurations

5-313

Input Current Decimall
Binary, UplDown, 4/8
Digit

Input Current RESET,
Count
-200~~~~~~~~--~

-1000
-900
,-800

f-f""o.c:-+-+-+-+--+--+--H

-150

,

:!

:! -100 I-t---'~+-t-:-J.--..""",,",+-f--+I

§

~

-700
~MAX @ Vee = 9.5V

-600
-500

I"

IMAX @
Vee=4.5
iMIN @
Ree=4.5
::\.
IMIN @
Yee=9.5

-400

LS
-300
-200
-100

o C::::!~:I;;;;I:='::b~.::L...-1.I

o

1.0 2.03.04.05.06.07.0 B.O

9.5

r'\.

. i""+-!.l..

~

f-.I.t.

o

1

2

I......

.~""t-+3

4

5

6

7

LED Output Direct
Segment and Digit Drive

S.-Sg LED Output
. Source Current
-50

IMA!

-40

'c
E
;; -20

!

~

~

:z:

/

-20

........

-10

-10

4

5

6

7

8 9 10

4

YOH (VOLTS)

!.

-30
IMV

:z:

V V
IMIN

7

10

Output Sink Current
for 00-03

r-

-

~...

Q

-

SEGMENTS ON

VOH~2.0V

-40

c

~~AXEI~HT

Vee (VOLTS)

LED Output Direct
Segment Drive
-50

V

..... ...... I·......
:::::c......

o
3

I

ONE~-

_ -30

2

9.5

VIN (VOLTS)

VIN (VOLTS)

1

.........
8

-20

..

-10

.......

.... ......

o
4

5

300

I--'-Pi>-P-t--t-+-+--+--+--l

200

1-+1-+-+-+-+--+-+--+--+---'1

~

IMIN

7

10

1234567
VOL (VOLTS)

Vee (VOLTS)

Figure 6.. 1/0 DC Current
Characteristics
.

5-314

9

10

s:
s:
C1I
.......

Vee

.a::..

100pF

r

CAl

en
13

Vee OR NIC
RESET

Vee

Sb

COUNT UP

So
18

Sd

UPIOOWN

COUNT DOWN.,!.

12
11

10

S,
S,
Sg

MM57436

~

14

OECIMALI
BINARY
COUNT
03
02
0,
Do

17
24
23
22
21

20

-= -=
Figure 7. MM57436 as 16·Bit Binary Counter with RC Oscillator and Switch·Controlled UplDown Mode

13
Sb
So
Sd

Vee OR NIC

19
Vee

1

~

S,
Sg

MM57436

DISPLAY
SELECT

DISPLAY LOWER
4 DIGITS

D3
14

11
10

S,

4/8 DIGIT

-=

DISPLAY TOP
4 DIGITS

12

02
COUNT

0,
Do

24
23
22
21

20

Figure 8. MM57436 as 8·Digit Decimal Down Counter with Extenal Oscillator

5-31.5

Electronic Data Processing

~National

'
~ Semiconductor

MM57499 96 or 144-Key Serial Keyboard Interface (SKI)
General Description
The MM57499 keyboard interface, an NMOS silicon gate
technology device, is designed to bea minimum ICsolution
for the purpose of interfacing detached keyboards to termlnals.lt can reduce the usual 18 t024-wlrekeyboard toterminal interconnection to a 5-wire connection.
The 96-key operation is a simple direct interface to a 12 x 8
matrix keyboard. The additional capability of a 144-key option can be obtained by implementing an il)expensive 4 to
12-line decoder IC between the MM57499 and a 12 x 12
, matrix keyboard. If fewer than 96 or 144 keys are used, no
, connection is required in the matrix at the unused key
Ic;>cations.

• On-chip oscillator utilizes the standard
burst crystal

3.58 MHz color

• On-chip baud rate generator
• Serial transmit and receive
• 400 WPM burst rate (typical)
•
•
•
•
.•

2-key lockout
Auto repeat on all keys
Manual repeat key
Programmable phrase storage
Shift, cap loc, control, modes

• 144-key strap option
• Status information for up to 8 indicators

Features

• Single 5V supply
• 2.5 kO maximum ON resistance

• Full upper and lower case ASCII codes, numeric pad &
function encoding on-chip
,

• TTL compatible
• 28-pin dual-in-line package

Basic Application',

r----.,--.liIOllllll~.J 8 LED STATUS

,

OPTIONAL

"

'-.;.

SERIAL TO
PARALLEL
SHIFT
REGISTER
CLOCK

INDICATORS

DATA

r~---"I--.(J,~~.J
S'ERIAL TO
PARALLEL
SHIFT
REGiSTER

8 LED STATUS
INDICATORS

D!!! _ _ _ J

CLOCK

96 KEYS

MM57499
KEYBOARD
ENCODER

MM57499
KEYBOARD
ENCODER

8

---+ SERIAL TRANSMIT

SERIAL TRANSMIT

'------4

- - - - - -... SERIAL RECEIVE

SERIAL RECEIVE

144-Key Operation

96-Key Operation

5-316

/

/

Absolute Maximum Ratings

(Note 1)

Voltage at Any Pin Relative to GND
Ambient Operating Temperature (Note 1)
Ambient Storage Temperature
Power Dissipation

-0.5Vto+ 7V
O·C to + 70·C
-65·Cto +150·C
0.75 W at 25·C
0.4Wat70·C
300·C

Lead Temperature (Soldering, 10 seconds)

DC Electrical Characteristics
Parameter

O·CsTAs + 70·C, 4.5VsV ce s6.3V unless otherwise noted.
Conditions

Operating Voltage (Vecl
Operating Supply Current
Input Voltage Levels
Crystal Input
Logic High (V 1H)
Logic Low (V IL)
RESET Input Levels
Logic High
Logic Low
RESET Hysteresis
All Other Inputs
Logic High
Logic Low
Output Voltage Levels
Standard Output
TTL Operation
Logic High (V OH )
Logic Low (VoLl
CMOS Operation
Logic High (V OH)
Logic Low (Vall

Min

Max

4.5

6.3

V

30

rnA

0.4

V
V

Vee =5V, TA =25·C
(all inputs and outputs open)

2.0

0.7 Vee
0.6
1.0

Vee=5V±5%
IOH=100 "A
IOL= -1.6 rnA

V
V

0.4

V
V

0.2

V
V

2.4

Vee- 1

IOH=10"A
IOL= -10"A

V
V
V

1.2

3.0

Vee=max

Units

Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured
when operating the device at absolute maximum ratings.

AC Electrical Characteristics O·CsTAs + 70·C, 4.5VsV ce s6.3V unless otherwise noted.
Parameter

Conditions

Min

Max

Units

Cycle Time

4.469

IlS

Input Frequency

3.579

MHz

55

%

1.1
0.3

IlS
IlS

1.4
0.3
0.7

IlS
IlS
IlS

Duty Cycle
Outputs
MM57499 to CMOS Propagation
Delay Clock Output
.

30
4.5VsV ee s6.3V, C L =50 pF,
VoH =O.7 Vee, VoL =O.3 Vee

t PD1
tpDO

Pin 17 Data Output
tpD1
tpDo
tpD1

VoH =2V

5-317

AC Electrical Characteristics

(Continued) O·CsTAs

Parameter

+ 70·C, 4.5VsV cc s6.3V

Conditions

MM57499 to TTL Propagation
Delay

Min

unless otherwise noted.
Max

Units

0.8
0.8

I'S
I'S

1.0
1.0

I'S
I'S

1.3
1.3

I'S
I'S

Fanout = 1 Standard TTL Load
Vcc=5V±5%, C L =50 pF,
V oH =2.4V, V OL =O.4V

Pin 18 Clock Output
tp01
tpoD

Pin 17 Data Output
tp01
tpOD

Row Outputs, Transmit Output
tp01
t pOD

Key Cycle Timing
Down Debounce
td
Up Debounce
tu

See Figure 9
for
Timing
Sequence

Transmit Time
Decode Time
te
Burst Rates
Auto Repeat Rate

11.5
14.4

ms
ms

96·Key
144·Key
96/144·Key
96/144·Key

7.5
9.2
9.1
0.3

ms
ms
ms
ms

96·Key
144·Key

327

96·Key
144·Key
96·Key
144·Key

Manual RepeatRate

t

96·Key
144·Key

5.character words

Connection Diagram

Dual-In-Line Package

....!.
XTAL -2.

~XO

XTAL

...2.

~X2

RESET

....!

~xJ

GNO

'.

~Xl

y42

~

TRANSMIT OUT

y5...!

~

X6

~

X5

'7
y6_
MM57499
y7.2

~X4

...2.

~y8

RECEIVE INPUT

~yll

y9~
VCC

..!.!

yO

.E.

.!.L CLOCK OUT
.1L. DATA OUT (X7)

yl~

~yl0

y2..!!

.!!. yJ
TOP VIEW
Order Number MM57499N
See Package 23

5·318

423

WPM!
WPM!

15
12
66.
61

CPS
CPS
CPS
CPS

Functional Description
KEY SCAN

Diode isolation is required in the key matrix to guarantee
that if two keys and a. control key are simultaneously
pressed the MM57499 will process the correct key sequence. This maintains 2·key lockout and insures that an
erroneous control, shift, or repeat key is not encountered.

The MM57499 interfaces to a standard X-V keyboard
matrix. The strobe lines "walk" down the keyboard X
matrix lines (or external decoder) and are detected on the
Y inputs if a key is pressed. The sequential strobe/scan'
characterizes timing in many of the MM57499 functions.
The key function matrix is shown in Figure 1 and the complete code assignment is given in Table I.

z

. SHIFT
KEY

CONTROL

v

W

v

w

n

G

.

M

F

K

C

0

c

d

<

=

&

7

6

BREAK

7

6

OEL

-"

...

;

$

%

y9

0

yB

@

(

)

y7

B

9

.

#

H

A

•

y10

h

a

:

P

I

B

yll

p

i

b

+

-

/

n

J

i

X

x

q

r

k

y
y

R

S

L

E

z

5

I

•
>

?

T
t

m

f

SHIFT
LOC

CAP
LOC

U
u

N

0
0

g

REPEAT

!

0

5

4

3

2

1

0

y6

RTN

SP

ESC

LF

9

B

y5

5

4

3

2

1

0

y4

I

[

\

I

I
I

I

BS

TAB

....

y3

.j,

t

FMT

IL

DC

DL

FS

y2

EDL

EOS

CLEAR

SC

BTAB

OE

ADM

IC

yl

LS

FN7

FN6

FN5

FN4

FN3

FN2

FN1

yO

-

FIGURE 1. Key Function Matrix

5-319

Functional Description

(Continued)

TABLE I., CODE ASSIGNMENTS
Control

x

Code

Control

" Shllt

or

Shll' '

'

Shllt
Loc

Shllt Loc

Shllt Loc

"

Cap Loc

Cap
Loc

Key

o

,0

80

80

80

80

80

80

80

FN1

1

81

81

81

81

81

81

81

FN2

82

82

82

82

82

82

82

FN3

83

83

83

83

83

83

83

FN4

84

84 .

84

84

84

84

84

FN5

5

o
o
o
o
o

85

85

85

85

85

85

85

FN6

6

o

86

86

86

86

86

8~

86

FN7

7

o

87

87

87

87

87

87

87

LS

o

88

88

88

88

88

88

88

IC

1

89

89

89'

89

89

89

89

2
3
4

2

8A

8A

8A

8A

8A

,8A

8A

ADM
DE

3

8B

8B

8B

8B

8B

'8B

8B,

,BTAB

4

8C

8C

8C

8C

,8C

8C

8C

SC

5

80

80

80

80

80

'80

80

CLEAR

8E

, 8E

8E

8E

8E

8E

8E

8F

8F

8F

8F

8F

8F

8F

EOS
EOl

7

o

2

90

90

90

90

90

90

90

BS

l'

2

91

91

91

91

91

91

-91

2

92

92

92

92

92

~2

92

OL
DC

2

93

93

93

93

93

93

93

2

94

94

94

94

94

94

94

95

IL
FMT

2

95

95

95

95

95

95

6,

2

96

96

96

96

96

96

96

7

2

97

97

97

97

97

97

97

o

3

,98

98

98

98

98

98

98

09

09

09

09

09

09

09

TAB

2

08

08

08

08

08

08

08

BS

3

7B

1B

1B

5B

5B

5B

7B

4

7C

1C

1C

5C

, 5C

5C

7C

5

70

10'

10

50

50

'50

7D

6

7E

1E

1E

5E

5E

5E

7E

7

3

5F

1F

1F

7F

7F

,7F

5/7

o

4

30

30

30

30

30

30

30

1

4

31

31

• 31

31

31'

'31

31

2

32

32

32

32

32

32

32

33

33

33

33

33

33

33

o

34

34

34

34

34

34

34

5

4

35

35

35

35

35

35

35

6

4

36

36

36

36

36

36

36

7

4

37

37

37

37

37

37

37

o

5

38

38

38

38

38

39

39

38
'39

38

5

39

39

39

39

9'

5

OA

OA

OA

OA

OA

OA

OA

IF

3

5

1B

1B

1B

1B

1B

1B

1B

4

5

20

20

20

20

20

20

ESC
SP

5

5

00

00

00

00

00

20
00'

00

RTN

6

5

2E

2E

2E

2E

2E

2E

2E

7

5

FF

FF

FF

FF

FF

FF

FF

BREAK

o

6

30

30

30

30

30

30

30

o

4

5·320

6
8

Functional Description

(Continued)

TABLE I. CODE ASSIGNMENTS (Continued)
Addillonal Code. lor 144.Key Opllon

X

y

Code

Control

Control
10 Shllt
or
Shllt Lock

X

y

1

6

31

31

21

21

21

21

31

1

8

0

99

2

6

32

32

22

22

22

22

32

2

8

1

9A

3

6

33

33

23

23

23

23

33

3

8

2

9B

4

6

34

34

24

24

24

24

34

4

8

3

9C

5

6

35

35

25

25

25

25

35

5

8

4

90

6

6

36

36

26

26

26

26

36

6

8

5

9E

7

6

37

37

27

27

27

27

37

7

8

6

9F

0

7

38

38

28

28

28

28

38

8

8

7

AO

1

7

39

39

29

29

29

29

39

9

8

8

AI

2

7

3A

3A

2A

2A

2A

2A

3A

:

8

9

A2

3

7

3B

3B

2B

2B

2B

2B

3B

;

8

10

A3

8

11

A4

9

0

A5

9

1

A6
A7

Shllt

Shllt
Lac

Shllt Lac
10
Cap Lac

Cap
Lac

Key
Code

4

7

2C

2C

3C

3C

3C

3C

2C

5

7

20

20

3D

3D

3D

3D

20

6

7

2E

2E

3E

3E

3E

3E

2E

7

7

2F

2F

3F

3F

3F

3F

2F

I

9

2

0

8

40

00

00

60

60

60

40

@

9

3

A8

1

8

61

01

01

41

41

41

41

A

9

4

A9

2

8

62

02

02

42

42

42

42

B

9

5

AA

3

8

63

03

03

43

43

43

43

C

9

6

AB

4

8

64

04

04

44

44

44

44

0

9

7

AC

5

8

65

05

05

45

45

45

45

E

9

8

AD

6

8

66

06 '

06

46

46

46

46

F

9

9

AE

7

8

67

07

07

47

47

47

47

G

9

10

AF

0

9

68

08

08

48

48

48

48

H

9

11

BO

1

9

69

09

09

49

49

49

49

I

10

0

Bl
B2

,

-

2

9

6A

OA

OA

4A

4A

4A

4A

J

10

1

3

9

6B

OB

OB

4B

4B

4B

4B

K

10

2

B3

4

9

6C

OC

OC

4C

4C

4C

4C

L

10

3

B4

5

9

60

00

00

40

'40

40

40

M

10

4

B5

6

9

6E

OE

OE

4E

4E

4E

4E

N

10

5

B6

7

9

6F

OF

OF

4F

4F

4F

4F

0

10

6

B7

0

10

70

10

10

50

50

50

50

P

10

7

B8

1

10

71

11

11

51

51

51

51

a

10

8

B9

2

10

72

12

12

52

52

52

52

R

10

9

BA
BB

3

10

73

13

13

53

53

53

53

S

10

10

4

10

74

14

14

54

54

54

54

T

10

11

BC

5

10

75

15

15

55

55

55

55

U

11

0

BO

6

10

76

16

16

56

56

56

56

V

11

1

BE

7

10

77

17

17

57

57

57

57

W

11

2

BF

0

11

78

18

18

58

58

58

58

X

11

3

CO

1

11

79

19

19

59

59

59

59

Y

11

4

Cl

2

11

7A

lA

lA

5A

5A

5A

5A

Z

11

5

C2

3

11

ON-FC

OFF-FB

Cap Lac

11

6

C3

4

11

ON-FE

OFF-FO

Shilt Loc

11

7

C4

5

11

RPT

11

8

C5

6

11

CNTR

11

9

C6

7

11

SHIFT

11

10

C7

CNTR

ESC

PGM

11

11

C8

CNTR

;

NO CODE

NO CODE
FO"

ON-FA
OFF-F9 + CHARACTER STRING t

• II Shill Loc is ON. Shift will transmit FO and end Shift Loc ON mode.

t First time only.

5·321

Functional Description

(Continued)

KEY CYCLE TIMING

Valid key closures are detected by the MM57499 by recurring strobe/scan events. The MM57499 strobes rows of
the matrix at rates unique to the configuration (depending on either the 96 or 144-key mode option) of the
MM57499 and the number of keys down.

The only situation in which this timing would occur is
programmable phrase mode, where the 8-bit data words
are separated by 2 stop and 1 start bits. Under normal
operating conditions debounce time will stretch the stop
bits by transmitting a continuous logical "1:'

The MM57499 processes a key if the minimum debounce
requirements are met. To insure debounce the MM57499
verifies the key down closure. (Timing is summarized in
the Electrical Characteristics table.) After the key has
been verified down, the Iy1M57499 recognizes the key as
being valid and processes the ASCII code. Before the
next key is processed, the previous key pressed must
have been up for three scan times. If sufficient dwell on
the key is encountered the MM57499 will go into the
automatic repeat mode until the key is detected to be up.
Strobe/scan times are dependent on the keyboard situation. With no key pressed the full matrix scan is accomplished in 2.5 ms (3.4 ms)*. Under normal operating
conditions, burst rates of 423 words per minute (327)*
typical can be realized.

RECEIVE STATUS

The addition of an external serial in-parallel out shift
register permits status indicator drive capability. This
status information is inputted to pin 9 of the MM57499.
The serial data chain must have a valid start bit and at
least 1 stop bit or the MM57499 will not accept the status
change. The status is an 8-bit data word, and is clocked
into the status latch 0.178 ms after detecting a stop bit.
The data chain into the receive input is sampled 0.1 ms into the start bit and every 0.833 ms thereafter for the next 9
. .
bits (to include 8 data bits and 1 stop bit).
The status word read by the MM57499 encoder is complemented. The external serial to parallel shift register
LED driver will also do a complement of the data word.
Therefore the status indicator device (LED) is on with a
Logical "1" data bit received.

TRANSMIT

Designated as Tt in the key cycle timing diagram, the
transmit chain is made up of 1 stop bit, 1 start bit, 8 data
bits, and 1 stop bit, in that order. The timing is 0.833 ms
per biti which is 9.16 ms (1200 baud) for the complete
transmit cycle.

Data is transmitted to the status latch by a serial process. The status data transfer is completed in 8 cycle
times (see Figure 3 input/output timing diagram).

* 144·key mode

t

r--DATA(8)~

I

I

START OF
TRANSMIT

DATA(8)~

FIGURE 2_ Recurring Transmit Stream

3.58 MHz

CLOCK_.J...._J

STATUS
OATA __________________

RECEIVE AND
V COLUMN
_______________
1~IPUTS

b..

~-'~---'

1-.

X

'SET·UP

+~

-I f-X

'HOLD

~

_________....

'PO!=}

TRANSMIT AND
/
X ROW OUTPUT _ _ _ _ _ _ _ _ _ _ _ _ _ _-'_t-._--I

VOH

FIGURE 3. Input/Output Timing Diagrams

5-322

. I

Functional Description

(Continued I

TRANSMITIRECEIVE INTERRUPT
In the event the MM57499 is transmitting a character and,
at some time during that process a status word update is
sent to the MM57499, an interrupt in the transmit stream
will occur. The transmit output pin will drop to a logical
low and remain in that state until the received word is
processed. Once a break has been detected, the processor can determine that the data is not valid. The
MM57499 will process the received word and retransmit
the interrupted character. If the receiver status option is
not utilized, normal operation (without interrupts) will oc·
cur (see Figure 4 for transmit out and interrupt timing).

key is ON causes an FD code to be transmitted and the
shift loc is terminated.
The CAP LOC is similar in function to the SHIFT LOC in
that a cap loc ON code FC is transmitted upon a depres·
sion of the CAP LOC key. The CAP LOC mode will
capitalize alphabet and appropriate keys; i.e., if a "B" key
is depressed, a capital B is transmitted. The SHIFT LOC
key accommodates all other key secondary functions. A
second depression of the CAP LOC key transmits a cap
loc OFF code FB and the keyboard is returned to normal.
When more than one mode is entered coincidentally,
refer to the key codes for mode dominance.

SHIFT LOC AND CAP LaC KEYS
96·KEY OR 144·KEY SELECTION

Both the SHIFT LOC and CAP LOC are software latching
keys. When either is depressed they transmit a·bit codes
to indicate a mode change. When the SHIFT LOC is
pressed, a shift loc code FE is transmitted and all appropriate characters are Shifted. A second depression of
the SHIFT LOC key will cause a shift loc OFF code FD to
be transmitted and lower case ASCII is again transmitted.

The MM57499 can be configured to either a 96·key or
144·keyarrangement.
In the 96·key mode, a standard a x 12 matrix keyboard is
required, and the X·Y matrix lines are connected directly
to the keyboard as shown in the minimal configuration
(Figure 5). In this configuration pin 21 is used as a strobe
line. Note the diode isolation requirements also shown in
Figure 7.

The SHIFT KEY (not the SHIFT LOC key) will not transmit
a mode change unless the SHIFT LOC is ON. Keeping the
SHIFT KEY depressed accomplishes the same function
as the SHIFT LOC, much the same as most common
typewriters. (The shift key has a momentary action, the
shift loc key locks the keyboard until it is deliberately
released via the SHIFT or SHIFT LOC key). Relieving the
SHIFT KEY returns the character transmit to lower case
ASCII. Depressing the SHIFT KEY while the SHIFT LOC

r

If the 144-key mode is desired, pin 21 must be strapped to
ground to actuate the 144-key codes. An external 4 to
12-line decoder (12 lines of a 4 to 16-line decoder) must be
interfaced between the MM57499 and the keyboard on
the X matrix lines, as shown in Figure 6.

STATUS INTERRUPT

~~~~~~TR~~~:~iA_~-!_I-T~~~~~:I:_-_-_'...IlL....

1 . __

ST_A_R_T_......

1_

r
I

RETRANSMIT

_A_T_A_ - - '
&.I·_ _
ST_A_R_T_......_ _D

_ _ _...

12m, -1-l.48m'-11

TVPICAL

FIGURE 4. Transmit Output and Interrupt Timing

vO

VO

vII
XO
X7

• 12
• SCAN
• LINES

96
KEVS
12 x 8

• 12
• SCAN
• LINES

MM57499

I

·

·

VII

·

·

t ... t

MM57499
x4

t

··
·

8
STROBE
LINES

XO
Xl

_ SERIAL TRANSMIT

I

~

··

144 KEVS
12 x 12

4·TO·12
DECODER

I
4 COUNT LINES

o

SERIAL TRANSMIT OUT

FIGURE 6. 144·Key Configuration

FIGURE 5. Minimal Configuration-96-Key

5-323

~

......
U')

Functional Description

(Continued)

~
~

.......

"

~. ~

"A,\

~.

"-

A,\

A,\

"
"A,\
"A,\
A,\

~

.......
~

"

A,\

.

"A,\,
"A,\

-

""A"

~

"A\
"A"

~

""A,\

"A,\

"

~ ~~

...

~~

~

~ ~~

.......

~I~

~ ~~

............

~I

"

~ ~~

III••J

~I~

A" ~ .......
"- ~·I
A" ............ --

~ ",

"

~

~I~

V10
EXPAND FOR 144 KEVS

FIGURE 7. 96·Key Board Matrix (Note diode direction)

5·324

A~

~"
V11

Functional Description

(Continued)

CHARACTER REPEAT
As explained previously in the key cycle timing
paragraphs, normal depression of a character key
initiates a transmission of the character after a minimal
scanldebounce time. Keeping that same character key
depressed for one second will cause an automatic repeat
of that character, followed by successive transmits.

thereafter as a warning device until the CONTROL
SEMICOLON is keyed.
If the CONTROL SEMICOLON is keyed and the device
memory is unprogrammed (empty), the MM57499 will
ignore the keying.

These repeat rates are summarized in the AC Electrical.
Characteristics table. A secondary method of suc·
cessively repeating the character is by use of the
REPEAT KEY. In this case the desired character and the
repeat key are depressed simultaneously. The character
repeat begins immediately, with no initial pause.

STATUS LATCI-I APPLICATIONS
The status latches may be used for various applications.
An B·bit word with start and stop bits is received and then
clocked into the status latch immediately. If an invalid
word is received (i.e., no stop bit) the MM57499 will revert
to the previous valid status word and clock it into the
status latch. The detection of the leading edge of a start
bit on the receive line (pin 15) causes all other operations
within the MM57499 to cease until the status word has
been received and latched. Should the MM57499 be proc·
essing a key when a status word is sent, the operation is
restarted after the status word is received by the
MM57499. If the MM57499 is transmitting a word when a
valid status start bit is received, the transmit line drops to
a logical "0" (low) to denote a break (00). After the receive
is completed, the MM57499 will retransmit the inter·
rupted character in its entirety (see Figure 4).

PROGRAMMABLE PHRASE
In many terminal applications a certain word, phrase,
name, title, etc. is required periodically. It may also be
necessary that indent spacing or a predetermined tab se·
quence be recalled. The MM57499 has the unique
capability of storing up to 14 characters of key data,
whether they actually be key characters or control codes.
These 14 key strokes can be stored for later use.
To program this memory first press the CONTROL ESC
key. This causes the hex code FA to be transmitted and in·
dicates the programming mode is active. This FA code
could be used to enable a status indicator (see status ap·
pllcations for precautions). The next 1 to 14 key strokes will
be stored In the MM57499 memory for recall upon com·
mand. Keying the CONTROL SEMICOLON key will cause
the programmed characters to be transmitted at 1200
baud.

One status application would be to indicate the state of
the keyboard. If SHIFT LOC is pressed a hex FE is
transmitted to the CPU. The CPU at this time can send
back a status word to illuminate a single LED to be the
SHIFT LOC indicator. Upon the second depressing of
SHIFT LOC the MM57499 transmits a hex FD. At this time
the CPU can send back a status word to turn off the
SHIFT LOC indicator.

The first time this stored instruction or phrase is
transmitted, a hex code F9 is also included at the begin·
ning of the transmit data stream to indicate the termina·
tion of the programming mode. (The status indicator
could now be turned off if a status change command is
given.) Additional keying of the CONTROL SEMICOLON
keys retransmits the stored characters or control codes
(programmed phrase) as many times as recalled and until
the MM57499 memory is reprogrammed (via the same
steps as described above) with a new phrase. A power
down or a RESET operation will also clear. the memory.
Summarizing, the programming steps are:
1. CONTROL ESC
2. Program-up to 14 key strokes
3. CONTROL SEMICOLON
4. For additional recalls of memory key CONTROL
SEMICOLON
5. For reprogramming, repeat steps 1, 2, 3 above

When using the status indicators in conjunction with the
programmable phrase option, care must be taken to
guarantee the integrity of the character stream. If it is
desired to indicate the programming active state with the
keyboard status latch, some guidelines must be fol·
lowed. When entering the programming mode a hex FA is
transmitted ·to the CPU. In order to insure the integrity of
the following key strokes (to be stored as the pro·
grammed phrase) it is necessary to initiate transmission
of the status word within 10 ms from the time the FA
code is received. No other status changes should be sent
from the CPU during "PROGRAMMING MODE ON" se·
quence. There is a small probability that a status word in·
terrupt may cause a key stroke to be inadvertently ig·
nored. The minimum time to press the next key plus 10 ms
is the maximum allowable delay. In most applications
this is more than sufficient time to start the status cor·
rection. To indicate the termination of the programming
mode, care must also be taken. to send the status change
within 10 ms aft.er receiving a mode change from the
keyboard to assure that a conflict of send or receive data
does not occur. During normal key entry the keyboard en·
coder is capable of proceSSing a status word at any time.

Until the CONTROL SEMICOLON is keyed, the MM57499
will remain in the programming mode, regardless of how
many programming keys have been pressed, and even
though only the first 14 key strokes are stored. The phrase
is programmable from 1 to 14 key strokes, therefore it is
not necessary to program all 14 strokes prior to keying
the CONTROL SEMICOLON. If the 14 key stroke limit is
inadvertently exceeded and additional key strokes are
entered, the MM57499 will transmit an 07 bell code after
the 14th key stroke and for every additional key stroke

INITIALIZATION
The reset logic, internal to the MM57499, will initialize
(clear) the device upon power·up if the power supply rise

5·325

Functional Description

(Continued)
time is less than 1 ms and greater than 1 p.s. If the power
supply rise time is greater than 1 ms, the user must provide an external RC network and diode to the RESET pin
as shown below. The RESET pin is configured as a
Schmitt trigger input. If the RESET pin is not used it
should be connected to Vcc. Initialization will occur

whenever a logic "0" Is applied to the RESET input, pro.
vided It stays low for at least 10 p.S.
Table" is a routine showing how to. read from the. serial
keyboard encoder with the INS8250 ACE using the
INS8060 SCAMP" Microprocessor.

TABLE"
START:

; READ ACE STATUS REG.

005 (P3)

LD

; MOVE STATUS TO E REG.

XAE
LDE
ANI
JNZ

; IS FRAMING ERR SET
; FE IS SET, JUMP

008
ERR

; FE NOT SET, IS RECEIVER READY?
; WE COULD HAVE REREAD THE STATUS
; REG. BECAUSE RECEIVER READY ONLY
; CLEARS UPON READING THE RECEIVER
; OR WRITING A 000 TO THE STATUSER
; REG. IF WE WISH TO RING BEL UPON
; RECEIPT OF AN OVER RUN ERROR, WE
; CANNOT REREAD THE ACE STATUS BECAUSE
; THE FIRST READ CLEARED OUT THE ERRORS

LDE

ERR:

ANI
JNZ

001
RECEIV

,

JMP

START

; RECEIVER NOT READY, REPEAT LOOp·

LD
JMP

·000 (P3)
START

; RECEIVER IS READY, JUMP

; READ ACE RECEIVER, THROW AWAY DATA
; GO BACK TO SCAN BEGINNING

vcc

8 STATUS
'LEOS

KEY
CONFIGURATION

SERIAL
RECEIVE

SERIAL
TRANSMIT

FIGURE 8_ Status Indicator Configuration

I-KEy

KEY

I

t

r-KE~Up-1

80WN-j

..

1-,--_·-_-_-_-_-.....-...;..'-'1-·____

OUTPUT

1·----

·;,;..1
•• · ....

I-~ECOOE

I

I

=I.==~~~:_I._ tt~-I.I;:
Ie

FIGURE 9_ Key Cycle Timing

5·326

NEXT
KEY

Functional Description

(Continued)

RS232

r---------~~---+
LED INDICATORS

L--------f

MM57499
SERIAL KEYBOARD INTERFACE
(SKI)

96/144
KEYBOARD

FIGURE 10. MM57499 System Concept

POWER
SUPPL Y

RC~5XPOWERSU~LYR~ET~E

FIGURE 11. Power·Up Reset Circuit

Input with Load
VCC

"'"

Typcial Device Output

Vcc

~'~"" ~ ~::::'"~:::
FIGURE 12. Input/Output Devices

5·327

Hi·Z Input

Functional Description

(Continued)

Output Sink Current
Device Type 3
-30

,

,Vee = 4.5V (MAX)

-25
-20

;;r
.§.

l; -15
.E
-10

o

o
Vour (V)

Depletion Load Off Source Current
Device Type 2

Input Load Source Current
Device Type 1

0.4
1.5
0.3

;;r
.§.
t::>

0.2

.E

;;r

r"\

.§.

1.0

t::>

\

.E
0.5

0.1
\MAX

~'\

Vour (V)

Vour (V)

FIGURE 13. InputlOutput Device Characteristics

FIGURE 14. INS8250 ACE Receive Flow
When Utilizing Status Latches
(Interrupt 1/0 Mode)

5-328

Functional Description

(Continued)

Functional Application 96·Key Mode
VCC

I
I

STATU~G~ C~G ~Q ~Q ~Q ~Q ~C
LEOS

I
I
I

E

3

4

5

10

6

12

11

1

2J

L ___

MM14C164
SERIAL·TO PARALLEL SHIFT REGISTER

I

MM51499

~:
f}-I

-------------~

18

ALTERNATE
CLOCK INPUT
METHOD
OPTIONAL APPLICATION
RECOMMENDATIONS

_________ I
4

2

---L '.
1M

VCC

-tll

2 TTL CLOCK

MM51499

~
24

r::::J

8."

Tr--

~

r
I
I
I

11

I-

x5

23

X4

x3
21

22

• t- -

x2

25

t-

X'

26

xU
21

V"V 10 V9 v 8 v 1 v 6 v 5 v 4 v3 v 2 Vi VO
19 16 10 20 5

28

t-

I-

1

~ ~ ~ ~ 11 ~ ~:
~'

'1 '1

~

I
I
I
I
I
I

x6

.~~

.~ ~

~~

~'

1 '1 '1
~

~ ~ r-'
~ ~~ ~~

!-

'1

'1.

~

~ I

6

1

8 12 13 14 15

t"J:.
1

IL

":'"

VCC

.
10k

10k

I

Vce

I
I

10k

I

.
I

5·329

I10

. 1111

9
x1

3.51545 MHz

I
I

J

INS8250
ACEOR
UART

__

MM57499

;p
5'

Functional Application 144.Key Mode

-I

Vcc

sr~~~~Q~ G~ Q~Q~Q~Q~Q9G9
134561011
21
8

1213

MM74CI64
SERIAL·TO·PARALLEL SHIFT REGISTER

f-

18

i'n

4

;:,.

~IM ~

Vcc- .!.!.

.H

MM57499

J-=

3'

.:........

Vcc
124

en

8o

f

I

XII

x lO

13

11

X9
10

Xl

X8
9

B

..,!.

24
x7

---117

X4

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li 2

X3
25
2U

OM14LSI54 4-16 DECOOER
x4
x6
x5
7

6

Xl

I~l

126
21"

22

Xl
5

. XU

4

vII vlO v9 vB v7 v6 v5 v4 v3 v2 VI VO

28

19 16 10 2U 5

6 7

TRI
REI

9

8 12 13 14 IS

23
x2
3

xl,

xU

2

Vcc

I
10k

-11 -1' -1' -1' -1' -1' -1' -1' -11 -1' -1'

l).-l) l) l) l).l) l) l) l) l).l)

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~

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,~~

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10k

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3.579545 MHz

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~National

Electronic Data Processing

~ Semiconductor

MM5863 12·Bit Binary AID Building Block
General Description

Features

The MM5863 is the digital controller forthe LF13300D*
analog building block. Together they form an integrating
12·bit AID converter. The MM5863 provides all the
necessary control functions, plus features like auto
zeroing, polarity and overrange indication, as well as
continuous conversion. The 12·bit plus sign parallel and
serial outputs are TR I·STATE~) TTL level compatible.
The device also includes output latches to simplify
data bus interfacing.

•
•
•
•
•
•
•
•

12·bit binary output
Parallel or serial output
Parallel TR I-STATE output
Polarity indication
Over range indication
Continuous conversion capability
100% overrange capabi Iity
5V, -15V power requirements

*See LF13300D data sheet for more information

•
•

TTL compatible
Clock frequency to 500 kHz

Connection Diagram

Dual-I n-Line Package

2B (P/S) PARALLEL/SERIAL
SELECT
27
(CLK) INPUT CLOCK

(SCLK) SERIAL CLOCK
(SC) START CONVERSION

26 (PO) POLARITY
DETECT
25
VGG

(OE) OUTPUT ENABLE
(LSB) LEAST
SIGNIFICANT BIT

r12

24

rll

2- 10
r9

21

2-B
PARALLEL DATA
OUTPUT LINES

2-6

lB

2-5

GND

17 (POL/SDO) POLARITY/SERIAL
DATA OUTPUT
16
(OR) OVERRANGE

12
13

2-3
2-2

(RP) RAMP POSITIVE

20 (DC) OFFSET
CORRECTION
19
(RR) REFERENCE RAMP

2- 7

2-4

VSS

23 (EOC) END OF
CONVERSION
22
(RN) RAMP NEGATIVE

15 2- 1 (MSB) MOST
SIGNIFICANT BIT

14

TOP VIEW
Order Number MM5863N

See Package 23

5-331

·Absolute Maximum Ratings
Supply Voltage (VSS)
Supply Voltage (VGG)
Voltage at Any Input
Operating Temperature
Storage Temperature
Clock Frequency
Lead Temperature (Soldering, 10 seconds)

5.25V
-16.5V
5.25V
o°c to +70°C
-40°C to +150°C
·500 kHz
300°C

Electrical Characteristics
VSS = 5\.1, V GG = -15V, O°C to +70° C, unless otherwise specified.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Power Supply Voltage (VSS)

4.75

5.00·

5.25

V

Power Supply Voltage (VGG)

-13.5

-15.00

-16.5

V

Power Supply Current (ISS)

28

.mA

Power Supply Current (IGG)

34

mA

Logic "1" Input Voltage

3.4

logic "0" Input Voltage
Logic "1" Output Voltage

VSS = 4.75, IOH = 100 IJA

Logic "0" Output Voltage

VSS = 5.25, IOL = -1.6 mA

Width of EOC

Auto Cycle

Output Disable Time

V
V

0.4

4/f

V
Sec

5/f+l IJs

Sec

OE to Any Data Output,
SC= l,P/S=O

1.0

IJS

OE to Any Data Output,

2.4

IJS

0.9

IJS

2.2

IJS

1.0

IJS

SC
Output Enable Time

3.8

5/f

Prop. Delay PO to EOC
Output Enable Time

V
0.8

= 1, PIS = 0

PIS to Any Data Output
Except Polarity, SC = 1,
OE = 0

Output Disable Time

PIS to Any Data Output
Except Polarity, SC = 1,
OE = 0

Output Enable Time

.SC to Any Data Output,
.OE=O,P/S=O

Output Disable Time.

SC to Any Data Output,
OE= 0, PIS = 0

2.4

IJS

Prop. Delay Serial Clock

SCLK to POL/SDO

0.6

IJS

Conversion Time

Full Scale

8966/f

Sec

Conversion Time

100% Overrange

13062/f

Sec

5-332

Functional Description
OPERATION
The MM5863 is designed for use with the LF13300
analog front end. Four control signals are supplied to
the LF13300 and 1 control signal is required from the
LF 13300. The conversion cycle is composed of 5
distinct phases. They are: Phase I - Offset Correct;
Phase II - Polarity Detect; Phase III - Offset Correct;
Phase IV - Ramp Unknown; Phase V - Ramp Reference.

"1 ". These 2 signals will never be at logic "1" simul·
taneously.
Phase V - Ramp Reference

Phase I - Offset Correct' (256 Clock Periods)
This phase is initiated by taking the Start Conversion
(SC) and the Output Enable (OE) lines to a logic "1 ".
At this time, Offset Correct (OC) will be a logic "1 " ..
The LF13300 requires this phase to correct any intrinsic
offset voltage errors prior to the polarity detect phase.
Phase \I - Polarity Detect (256 Clock Periods)
This phase is used to determine polarity of the analog
input. At the midpoint of this phase, PO from the
LF13300 is examined for polarity. If PO = logic "1",
then the input voltage is positive. If PO = logic "0", then
the input is negative. The Ramp Positive signal (RP)
will be a logic "1 ", and Offset Correct will be iogic "0"
for the entire phase of 256 clock periods. The above
operation is also necessary to determine which integrator
input (positive or negative) of the LF13300 should be
used for proper AID conversion (see LF 13300 data
sheet).

This phase is a variable length phase depending on the
magnitude of the analog input voltage. During this time,
Ramp Reference (RR) will be in the logic "1" state.
When PO goes to a logic "0" state, or when the internal
counter reaches 100% of full scale (8192 clock periods).
the Ramp Reference (RR) signal goes to the logic "0"
state, the counter output is loaded into the output
register, and the End of Conversion, (EOC) signal goes
to a logic "1 ". The Polarity Bit will reflect whatever
value was determined during Phase II. The output
register will hold the data until a new conversion is
completed and new data is loaded into the register.
The OE line must be low in the logic "0" state and SC
must be high in the logic "1" state to enable the outputs.
DATA OUTPUTS
Both serial and parallel outputs are available. In either
case, OE must be low and SC must be high to enable
the outputs. For parallel output, the PIS line must be
low in the logic "0" state. For serial outputs, the PIS
line must be high. In the serial mode, the data is shifted
out of the Polarity/Serial Output POL/SDO line and all
other data outputs are in the high impedance state.
Each Serial Clock (SCLK) will right shift the output
register one bit. Thus, 13 clock pulses are required to
fully shift out the data. The data will be shifted out in
the follOWing order: Polarity, Overrange, MSB, 25B,
3S8, .. " L5B. If OE and PIS are in the logic "0" state
and SC in the logic "1" state, all outputs will momen·
tarily go to the logic "1 ". state for 1 clock period
immediately preceding EOC.

Phase III - Offset Correct (256 Clock Periods)
This phase is identical to Phase I and is used by the
LF13300 to eliminate any offsets induced as a result of
the Polarity Detect Phase. Offset Correct (OC) will be at
a logic "1 ".
.
Phase IV - Ramp Unknown (4096 Clock Periods)

CONTINUOUS CONVERT MODE
The unknown input voltage is integrated for a fixed
time during this phase. The result of the Phase II
Polarity Detect Cycle determines whether RP or RN
will be at logic "1". If Phase II indicates a positive input,
the RP signal will be a logic "1 ". If phase II indicates a
negative input, Ramp Negative (RN) will be a logic

In this mode, the End of Conversion (EOC) output is
connected to the OE input. As long as SC is in the
logic "1" state, then each EOC wil,l initiate a new con·
version. The data outputs will be disabled for the first
5 clock cycles after EOC goes high.·

Truth Table
MSB

OVER·
RANGE

1

1

1

a
a

a
a
a
a

OE

PIS

a
a
a
a
a
a

a
a

-100% Full Scale

a
a
a
a
a
a

1

1

1

.1

1

1

1

1

1

1

1

Any

1

X

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

z

z

z

z

z

z

z

z

z

z

z

z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

INPUT

SC

100% Full Scale
Full Scale
Zero
Zero'

-Full Scale

Any
Any

1

a

a

x

X

LSB
1

1

1

1

1

a
a

a
a

a
a

a
a

1

a
a

a
a

a
a

a
a

a
a

1

1 = High
0= Low
Z = High Impedance
X

a
a

1

= Don't Care

5-333

POLARITY

a
a
a
Z
Serial Output

Z

liming Diagrams
The following timing diagrams are shown for the MM5863 connected in the auto-cycle mode_
Positive Input
PHASE I
OFFSET
CORRECT

I

I

PHASE II
POLARITY
oE1;ECT

PHASE III
OFFSET
CORRECT

I I

PHASE IV
RAMP
UNKNOWN

I

PHASE V
RAMP
,REFERENCE

I

lff

ClK

rLfl...r-,'

SC

..J

DC

I-

25& X lff

I

RP

r-

25& X 1/1

I

25& X 1/1

409& X lff

nR

_ 8192 Xl/I

L-

PO
EoC (DEI

OUTPUT
DATA

L-

I5iil

J5iiL

1<
,

DATA FROM PREVIOUS CONVERSION

TRI-STATE

>-C

Negative Input
OFFSET CORR
RP

RN
RR

I

25& X 1/1
256 Xl/I

256 Xl/I

~

____________

~r-

I-

I
__________-'-_______--11 :. 8192 X lff L 4096 X 1/1

PO

EOe (DEI

f5iil~~----------~------------------~~
Serial Output

EOC(OEI

-1"lI...._______. . ,. .____________________. . ,. .__
I

I
I

SClK

POllSDO

I

I
I
I

PIS

.JI~------------------'-----------------SERIAL OUTPUT

.

SC~I~-------------------------------------I
5-334

Timing Diagrams

(Cont'd)
Output Enable/Disable Time
DE OR PIS

1/

2

,

---.J
DATA OUTPUT

,

2

~

----+-...,

TRI·STATE
50%j1---';';;''''''''---+-l
TRI·STATE
OUTPUT ENABLE (OE)--+------------_t.1
ENABLE
PARALlELISERIALIP/S)-1------------_t"l_ _ _ _ _

J

5-335

END OF CDNV, (EOC)

Typical Application

33/4-3 1/2-Digit DPM

,.,

IN10D4

,:]
lNl004

15V

<>-.....-..------,

18

"
MM51163,

25

21

-12V

30.

11

'v

POLARITY

-=

30.

'v

} N"5057
LEO'S

'v

N5B3881 DISPLAV

13

12
MM14C926

15

•

16

,

11

. 1-11-11-11-1
1::::1.1::::1.1::::1.1::::1.

2
4

11

10,

MSO

SSO

TSO

LSD

300

,

9

DIGITS

0'
11
1/8 D58811

....""'' '"-0 ,v

I

8

1/8058871

r

aOOmV

";"

Note 1: All diodes, 1N914.

Note 2: All resistors 1/4W, 5% tolerance.
Note 3: Circuit,drawn for 8V full scale operation input scaling not shown.

5-336

8V

D.P. POSITIONING FOR
RANGES

BOOV
SOV

s::
s::
CJ1

~National

~ Semiconductor

CO

0)

CJ1

MM5865 Universal Timer
General Description

Features

The MM5865 Universal Timer is a monolithic MOS
integrated circuit utilizing P-channel low-threshold,
enhancement mode and ion-implanted depletion mode
devices. The chip contains all the logic required to
control the two 4-digit counters, blank leading zeros,
compare the two counters and to cascade with another
MM5865. Input pins start, stop, reset and set the
counters, determine which of the 7 functions is performed, the resolution of the display (0.01 sec, 0.1 sec,
1 sec, or external clock) and what modulo the counters
divide by. Outputs include the comparator output,
multiplexed BCD outputs and digit enables. The BCD
outputs interface directly with MM14511, a BCD to
7-segment decoder, which interfaces with a LED display.
The digit enable outputs of 2 cascaded MM5865's
interface directly with a DM8863 LED 8·digit driver.
A DS8877 or DS75492 Hex Digit Driver may be used
with a single MM5865. The digit enable outputs interface directly with a DM8863, a LED digit driver. The
7 functions include start-stop with total elapsed time,
start-stop with accumulative event time, split, sequential
with total elapsed time, rally with total elapsed time,
program up count and program down count. The circuit
uses a 32.8 kHz crystal or an external clock and is
packaged in a 40-lead dual-in-line package.

•

Function 1: Standard Start-Stop with total elapsed
time memory

•

Function 2: Standard Start·Stop with total accumulative event time

•

Function
memory

3: Sequential

with

total

elapsed

•

Function 4: Standard split

•
•

Function 5: Rally with total elapsed time memory
Function 6: Programmable up count. Repeatable
upon command

•
•

Function 7: Programmable down count
Comparator output

II

Crystal controlled oscillator (32.8 kHz)

•

External clock input (option)

•

Provides external clock

•

Select resolution

•

Select count up or down

•

Select modulo 6 or 10 for digits 2,3 and 4

•

Blanking between digits

•

Leading-zero blanking

Applications

•
•

Multiplex rate output
External multiplex rate input (option)

•
•
•
•

Stop watch
Kitchen timer
Oven timer
Event timer/counter

• Can be cascaded
• Waiting state indicator
• Simple interface to LED display
• Elimination of illegal time display at turn-on

•
•
•

Rally timer
Navigational timer·
Industrial timer/counter

• Wide power supply range 7V-20V

Block and Connection Diagrams
PROGRAM
0161181-4

Dual-I n-Line Package

f-______ ~~~~~Ol
'----,--.----'

DIVIDE

SCALER

ClIN--'

DIVIDE SCALER 1

V~

39 PROGRAM DIGIT 11

DIVIDE SCALER 2

38 LATCHtONTROL
PROGRAMDIGIT2

DIVIOESCALERJ

FUNCTIONS
H
CONnOL

time

"

COMPARATOR ENABLE

PROGRAM DIGIT J
36 PROGRAMDlG1T4/

FUNCTION I

CONTROL
lOGIC

35 WAITING STATE
CONTROlCllN

FUNCTION 2

l4

fUNCTION 3

CONTAOl---+

C21N

Jl

FUNCTION 4

RESET----+

31

FUNCTIONS

START/STOP---+

J1

FUNCTION 6

11
FUNCTION 7
FINALEVENTSTOP/ 12
COMPARATOR OUT 13
RESET

FINAL EVENT---+

COMP~~~~~~---+L._--r_ _.J

STAAT/STOP

+-_-[==::::J

RESOLUTION SELECT 1
AESOLUTIoNSELECT2
BLANKING

V~-----+

OSCIN

VOD-----+

,.

26
16

24
23

22

19

21

FIGURE 1.

FIGURE 2.

5-337

0lGIT4
CONTRDLC21N
MULTIPLEX IN
MU!.TlPLEXoUT
Voo

Order Number MM5865N
See Package 24

SELECT.!'_ _ _ _ _ _ _ _ _ _ _ _- - '

DlGITJ
CONTROL C2 OUT

11

TOP VIEW

RESOLUTION-'-------------.l

DIGITI
0lGIT2

27

OSCDUT

1~~~~~----~~-----t

BCDI
BC04
BCOB

29

CLDCKIN{OUT

MUlT1P~~~ _ _ _ _ _

MULTIPLEXIN-----f--·L:.:.....:..:.:..:J

CONTROle! OUT
BC02

Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)

Vss + 0.3V to Vss - 25V
-25°C to +70°C
-65°C to +150°C
300°C

Electrical Characteristics
T A within operating range, 7V:::; vss :::; 20V, Voo = OV, unless otherwise specified.
PARAMETER
100

CONDITIONS

MIN

TYP
7

15

mA

dc

32.8

80

kHz

Power Supply Current
Input Frequency at OSC IN
Multiplex Frequency
Blanking Frequency
Clock Frequency

lV$~ '"'

MAX

UNITS

dc

0.4

80

kHz

dc

O.B

10

kHz

Vss = 7V

dc

0.1

10

kHz

Vss = lOV

dc

100

kHz

Voo
V ss - 1

V oo+l

V

Vss

V

I nput Levels
Input Logic Low

Internal Resistor

Input Logic High

~100k

to Voo

OUTPUT CURRENTS
Digit and BCD Outputs

Vss = 7V

Source Current

V OUT = Vss -2V

1

mA

Sink Current

V OUT = Vss - 6.3V

1

J1A

Blanking Output

Vss = 7V

Source Current

V OUT = Vss - 2V

1

mA

Sink Current

V OUT = Vss - 6.3V

1

J1A

Multiplex Output

Vss = 7V

Source Current

V OUT = Vss - 2.5V

500

J1A

Sink Current

VO.UT = Vss - 6.3V

8

J1A

Clock Output
Source Current
Sink Current
Control C1, C2 Outputs
Source Current
Control Cl, C2 Inputs
Sink Current
Comparator Output

Vss = 7V
V OUT = Vss -4V
V OUT =Vss - 6.3V

10

J1A

5

J1A

Vss = 7V
V OUT = Vss - 2.5V

500

J1A

8

J1A

Vss = 7V
V 1N = Vss - 6.3V
Vss = 7V

Sou rce Cu rren t

V OUT = Vss - 2V

1

mA

Sink Current

V OUT = Vss - 6.3V

1

J1A

Waiting State Indicator

Vss = 7V

Source Current

VouT=Vss-2V

1

mA

Sink Current

V OUT = Vss - 6.3V

1

J1A

.5-338

Functional Description
A block diagram of the MM5865 Universal Timer is
shown in Figure 1. A connection diagram is shown in
Figure 2. Unless otherwise indicated, the following
discussions are based on Figure 1.

V DD to V55 switches the display from counter 2 to
counter 1. Repetitive Start-Stop transitions switch the
display between counter 2 and counter 1.

Function 1

Function 2

In Function 1, counters 1 and 2 count up beginning
with a transition on the Start·Stop pin from VDO to
V55 • Counter 2 is shown counting. A second transition
from V DO to V55 on the Start·Stop pin inhibits the
clock pulses ·to counter 2, stores and displays the contents of counter' 2. Counter 1 continues to count. The
third transition from V DO to V55 on the Start-Stop
pin resets counter 2, enables clock pulses to counter 2
and displays counter 2 counting. Subsequent StartStop transitions repeat this sequence, all this time
counter 1 continues to count. At the conclusion of
the last event to be timed, a Final Event Stop transition
from V DO to V55 inhibits the. clock to both counters
and displays counter 2. A Start-Stop transition from

In Function 2, counter 1 and 2 count up beginning with
a transition on the Start-Stop pin. Counter 2 is displayed
counting. A second transition on the Start-Stop pin
inhibits the clock pulses to both counter 1 and counter
2, stores and displays the contents of counter 2. The
third transition on the Start-Stop pin resets counter 2,
enables the clock to both counters' and displays counter
2 counting. Subsequent Start-Stop transitions repeat
this sequence. At the conclusion of the last event to be
timed, a Final Event Stop transition inhibits the clock
to both counters and displays counter 2. A Start-Stop
transition switches the display from counter 2 to
counter 1. Repetitive Start-Stop transitions switch the
display between counter 2 and counter 1. The control
inputs (C1, C2) must be pulsed at Start-Stop command.
Pulse width is a function of clock period.

POWER.(JN

POWER.()N

RESET
FOReESTD

RESET
FORCESTD
THIS STATE

THIS STATE

Flow Chart for Function 1

Flow Chart fll' Function 2

Functional Description

(cont'd)

Function 3

Function 4

In Function 3, counter 1 and 2 count up beginningwith
" transition on the Start-Stop pin. Counter2 is displayed
counting. A second transition on the Start-Stop pin
stores and displays the contents of counter 2, resets
counter 2, and initiates a new up·count in counter 2;
however, the new up·count is not displayed. Counter 1
continues to count. A transition on the Latch Control
pin will, display, counter 2 counting until anothertransition' on the Start-Stop pin. A Final Event Stop transition
inhibits the clock pulses ,to both counters 1 and 2 and
displays the contents of counter 2. A Start-Stop transition after the Final E~ent transition switches the display
from counter 2 to counter 1. Repetitive Start-Stop
transitions switch the display between counter 2 and
counter 1.

In Function 4, counter 2 counts up beginning with a
transition on the Start-Stop pin. Counter 2 is displayed
counting. A second transition on the Start-Stop pin
stores and displays the contents of counter 2. Subsequent Start-Stop transitions update the display of
counter 2. A transition on the Latch Control pin will
display counter 2 counting until a transition on the
Start-Stop pin. A Final Event Stop transition inhibits the
clock pulses to counter 2 and displays the contents of
counter 2.

POWERON

RESET
fORCES TO
THIS STATE

FINAL
EVENT

STOP

.--+____-""<

YES

r"---t---,

~~NE~~
STOP

NO

Flow Chart for Function 3

Flow Chart for Function 4

5-340

Functional Description

s:
s:
en

(cont'd)

Function 5

Function 6

In Function 5, counter 1 and 2 count up beginning with
a transition on the Start·Stop pin. Counter 2 is displayed
counting. A second transition on the Start·Stop pin
inhibits the clock pulses to counter 2, and the contents
of counter 2 are displayed. Counter 1 continues count·
ing. The third Start·Stop transition enables the clock
pulses to counter 2 and counter 2 is displayed counting.
Subsequent Start·Stop transitions repeat this sequence,
all the time counter 1 continues counting. At the conclu·
sian of the last event to be timed, a Final Event Stop
inhibits the clock pulses to both counters 1 and 2, and
displays counter 2. A Start·Stop transition switches
the display from counter 2 to counter 1. Repetitive
Start·Stop transitions switch the display between counter
2 and counter 1.

In Function 6, counter 1 is displayed at power·on or
reset. Counter 1 is set to a specific count by Program
Digit 1-4 pins. Then the comparator is enabled. Counter
2 is displayed counting up beginning with a transition
on the Start·Stop pin. When counter 2 is coincident with
counter 1, the clock pulses to counter 2 are inhibited,
the contents of counter 2 are displayed and the Comparator Output is enabled. Upon the transition of Reset,
counter 1 is again displayed with the time that was set,
and the Comparator Output is disabled. Counter 1 can
be reprogrammed by the Program Digit 1-4 pins if
desired. A Start·Stop transition repeats the sequence.

CD

If the Comparator Output pin is connected to the
Reset pin, Automatic Reset will occur; however, this
connection must be broken during digit programming.

NO

RESET

'-------'

"
' -_ _ _ _ _-J'O

Flow Chart for Function' 5

Flow Chart for Function 6

5-341

en

en

Functional Description

(cont'd)

Function 7
In Function 7, counter 1 is displayed all the time.
Counter 1 is set to. a specific count by Program Digit
1-4 pins. Then the comparator and Control C1 In
are enabled. Pin 4 and pin 35 must be floating or connected to V DD during digit programming. Counter 1
counts down from the set count beginning with a
transition on the Start-Stop pin. When counter 1 counts
down to zero,. the clock pulses to counter 1 aJe inhibited and the comparator Output is enabled. This is not
repeatable without setting a new count into counter 1.
The comparator and. Control C1 In must be inhibited
and a reset pulse must occur before the new count
may be entered.

Stop to affect the counters, it must be held to Vss ,
a logic one. Logic zero results when the pin is tied to
V DD or left floating (internal pull·up to V DD)'
Final Event Stop/Comparator Output
This pin is used to indicate to the circuit that no more
events will be timed or counted;· Final Event Stop affects
the circuit when it is held to Vss. There is an internal
pull·up to V DD . This pin is also an output pin, Vss
indicates comparison between the two counters.
Divide Scale Inputs
These three inputs are used to determine whether the
counters will count in Modulo 6 or Modulo 10. Table I
shows the code for which digit will count in Modulo 6
or Modulo 10. A logic one is when the pin is held to
Vss. When the pin is tied to V DD or left floating (internal pull·up to V DD ), a logic zero results.

TABLE I. Divide Scaler Code
DIVIDE
SCALER

COUNTER 1

COUNTER 2

1

2

3

04

03

02

01

04

03

02

01

0

0

0

10

10

10

10

10

10

10

10

1

0

0

6

10

10

10

6

10

10

10

0

1

0

1.0

6

10

10

10

6

10

10

10
10

1

1

0

10

10

6

10

10

10

6

0

0

1

10

10

10

10

10

10

10

1

0

1

10

10

10

10

10

1

1

10

10

10

10

6
10

10

0

6

10

1

1

1

10

10

10

10

10

10

6

10
10
10

NO

COMPARATOR

Comparator Enable

NO

OUTPUT

This input enables the comparator. To enable the com·
parator, the pin is held to Vss or logic one. To disable
the comparator, the pin is tied to V DD or left floating
(internal pull·up to V DD)'
Resolution Select Inputs
YES
RESET

These two inputs are used to select the fr~quency of the
clock pulses to the counters, Table II shows the code for
each frequency. A logic one is when the pin is held to
Vss. A logic zero results when the pin is tied to V DD or
left floating (interrial pull·up to V DD).

L...._ _ _ _ _~NO

Flow Chart for Function 7

Reset
This input will reset all logic and counters in Functions
1-5 and Function 7. In Function 6, Reset will reset
logic but not counter 1. Reset is internally pulled to
V DD, or a logic zero. For a reset to occur, the Reset pin
must be held to Vss, a logic one.
Start·Stop
This input is used to control the counters. How it affects
the counters is explained in each function. For Start·

5·342

TABLE II. Resolution Select Code

RESOLUTION
SELECT
1
2
0
0
1
1

0
1
0
1

FREQUENCY
OF CLOCK TO
COUNTERS
100 Hz
10 Hz
1 Hz
External

DISPLAY
RESOLUTION
0.01 sec
0.1 sec
1 sec

Functional Description

(cont'd)

Clock In/Out

pie x Output pin is four ti.mes the internal multiplex
rate. To use the Multiplex Output pin, the Multiplex
Input pin must be tied to VDD • The Multiplex Input
must be used if the oscillator pins are not used. If the
Multiplex Input pin is used, OSC IN, OSC OUT and the
blanking output are not used.

This pin is either an input or output depending on the
code at the Resolutioll Select inputs. If the pin is used as
an output pin, it will output the clock frequency the
Resolution Select inputs have selected. When used as an
input, an external clock is used to clock the counters.

Control C1, C21n and Control C1, C2 Out
Blanking Output
These four input pins are used to cascade two chips
together_ When the Control C1 In pin is floating (internal pull-up to V DD ) or tied to V DD , the clock pulses to
counter 1 are inhibited. When Control C1 In is at Vss ,
counter 1 is enabled. Control ClOut is at Vss when
counter 1 is at it s maximum count, and it is floating
at all other times. The Control C1 In pin must be
floating (or connected to V DD) while digit programming in Function 7. Control C2 pins operate on counter
2 in a similar manner.

This output is used to blank the display at the beginning
and end of each digit time to allow for internal delay
between two cascaded chips, see Figure 3. The display
is blanked when the Blanking Output is at VDD .

i------ 1Dml - - - - - - \ - - i - 1 1 5 I T 1 S
DIGIT 1 \Iss
CHIP 1 Voo

DIGIT 1
CHlP2
DIGIT 2
CHIP 1
DIGIT 2
CHlP2

Program Digits 1-4

------~II~--~----------~I

________

DIGIT J
CHIP 1

~IIL

____________

DIGIT J
CHlP2

_______________

~r-l~

______________

DIGIT 4
CHIP 1

These four input pins are used to program or set any
count desired in counter 1 in Functions 6 and 7. When
Program Digit 1 is at Vss, the least significant digit of
counter 1 advances at a 2.5 Hz rate. There is no carryover from digit to digit. Program Digit 1 has no effect if
tied to VDD or left floating (internal pull-up to VDD ).
Only one Program Digit input may be held to Vss at
a time.

___________

~IIL

__________

""'''~
CHIP2

BLANKING Vss
OUTPUT Voo

[--I

f--

·---1I--.o.",m,

~

1.25m'

Program Digit l/Latch Control

o"m,:1

r
L

~LD.'22ms

This input has two functions; besides setting a count in
digit 1 of counter 1 in Functions 6 or 7, it also affects
Functions 3 and 4. In Functions 3 and 4, this input
allows the display to show counter 2 counting as described in Fu.nctions 3 and 4.

FIGURE 3. Blanking Output

Oscillator I n and Out
A quartz crystal, resonant at 32.8 kHz, two capacitors
and one resistor, together with the internal MOS circuits
form a crystal controlled oscillator as shown in Figure 4.
Varying one of the capacitors allows precise frequency
settings. For test purposes, OSC IN is the input and OSC
OUT is the output of an inverting amplifier.
v~

Program Digit 4/Waiting State Indicator
This input besides setting a count in digit 4 of counter 1
in Functions 6 and 7, also indicates that the chip has
been reset and is in the stand-by mode at power-on. In
Functions 1-5, the Waiting State Indicator is at Vss
until a Start-Stop transition has occured. Once a StartStop transition has occured. the output remains at VDD .
Leading Zero Blanking
In Functions 1-5, leading zeros are blanked for both
counters 1 and 2. In Functions 6 and 7, counter 2 has
leading zero blanking. At power-on, the display is blank
in Functions 1-,5, and all zeros are displayed in Functions 6 and 7. ;;
Output Circuits

FIGURE 4. Crystal Oscillator

For BCD and Digit Outputs. Vss is a logic one. Figure 5
illustrates the circuit used for all outputs except for
Control C1, C2 Out_ The Control C1, C2 Out circuit is
illustrated in Figure 6. Figure 7 illustrates the simple
interface needed for an 8-digit stop-watch. Figure 8
illustrates the MM5865 being used to count how many
events occur in a specified time. Figure 9 shows the
MM5865 as a simple industrial counter when the input
clock is a constant frequency above 400 Hz.

Multiplex Input and Output
The Multiplex Input pin allows an external multiplex
rate to be used in the chip. The multiplex rate inside the
chip is one fourth the Multiplex Input and Multiplex
Output rate. When using the Multiplex Input pin, the
Multiplex Output pin must be tied to Vss. The Multi-

5-343

Functional Description

cont'd)

OIDATAI~~V"
~
"

.•".o----{>----i~.

OUTPUT
PAD

L'CDNTADlCI
.

.

OUTPUT

Voo

FIGURE 5. Output Circuit

,
f

r;::::::: ;
,..-d
~.

n :~
[I. ~=J
D.P.

FIGURE 6. Control C1 Out Circuit

~= ~=
'=-11 ~,=~ ::~ ~:l:

I=~

u~

~:~

~ UC-J~
L

150

171

.-

116

I
f-

n18

9

~ 10

MM14511

'W

aM88S3

,

L

500
I

J
9

2N3904

GND

4'-J

I

30

+10V 0 - - -

21

40

MM5865

II I

1101

I

I21

30

MM5865

I"

II

I

I I

1101

I

I I

I"

L--

FUNCTION 1

~ •
2
3

5

-L-FINAL
EVENT

r-<>

f--<>- L AESET
-...L..STAATI

~

STOP

~~

LATCH

CONTADl

I'DISPlAY'
INHIBIT

-

~

~
6-25"-

~~t
~ 25':j

Display reads 12h 34m 56.78s

Maximum time 99h S9m 99s
Decimal point indicates waiting state

FIGURE 7. Stop Watch Application

5·344

B- \
STAAT/STOP

DIP

~

Functional Description

s:
s:
en

(cont'd)

CO
CD

en
EVENT

TIME

.

rl rCJ~ __ J~ r--:
~:
Ij t~~ U~~ Ir--- :'

,
I

~r

b

~,

r-- d
r-'

~

Ur-'J

[I :]
LL

150

~~

OJ

,

rh,

I,

~IB

I

MM14511

I L

I

I rt-J
10

DMBS6J

I' I

6

9

PROGRAM
DIGIT

-L4

~-L

t----o ~
t----o- Lo-!-

~-L~
GNO

I
40

JO

+lDV. 0 - -

21

40

MM5B65

MM5B65

,

I

I I I I I 101

21

JO

"ll

20
t--

I' I I I I I I I

1101

I 1

I I 120

COMP

.~

f--<>- L RESET

~
- L START/STOP
EVENT

(CLOCK IN)

e--

Display 15 events have ottured in 1 minute
Maximum events 99,999,999

~

~D~

Makimum Time 99m 595

6-15" ~ ~ 15"T

FIGURE 8. Application-of MM5865 to Count Events in a Specified Time

5-345

B-

Functional Description

(cont'd)

,
f

~ =~ =~

,

r;::::= ,
b

~ ~: :~

,

;-- d

~=~

15.
111

n'6

I,
~

IIB/U UILI'

9

DMB86J

MM14511

J8

~

L-

r-J'

IJ

I
9

GNO
+tOV

140111111

I

II I

30

rrr;;-

MM5865

Display reads a count of 1234
Maximu mcount 9999

"I , I I I , I I '10' , I I I II , '20
CLOCK

~(RESET
~

I

J

START/STOP

FIGURE 9. Industrial Counter

5-346

B-

~National

Electronic Data Processing

~ Semiconductor
MM58167 Microprocessor Compatible Real
Time Clock

General Description
The MM58167 is a low threshold metal-gate CMOS
circuit that functions as a real time clock calendar in
bus-oriented microprocessor systems. The device includes
an addressable counter, addressable latch for alarm-type
functions, and 2 interrupt outputs_ A power-down input
allows the chip to be disabled from the outside world
for standby low power operation. The time base is
generated from a 32,768 Hz crystal-controlled oscillator.

Features
•
•

•

•

Microprocessor compatible
Thousandths of seconds, hundredths of seconds,
tenths of seconds, seconds, minutes, hours, day of
the week, day of the month, and month counters
with corresponding latches for alarm-type functions
Interrupt output (maskable) with 8 possible interrupt
signals:
• Latch and counter comparison
• Every tenth of a second
• Every second
• Every minute
• Every hour
• Every day
• Every week
• Every month
Power-down mode that disables all outputs except for
an interrupt output that occurs on a counter latch
comparison_ This is not the same as the maskable
interrupt output

•
•
•

Don't care states in the latches
Status bit to indicate clock rollover during a read
32,768 Hz crystal reference, with only the input
tuning capacitor and load capacitor needed externally

•

Four year calendar

If either of the bytes in the above 8-bit counter words
do not legally reach 4-bit lengths (e.g., day of the week
uses only the 3 least significant bits) the unused bits will
be unrecognized during a write and held at VSS during
a read. If any illegal data is entered into the counters
during a write cycle, it may take up to 4 clocks (4
months in the case of the month counter) to restore
legal BCD data to the counter during normal counting.
The latches will read and write all 4 bits per byte. Each
of the counter and latch words can ~e reset with the
appropriate address and data inputs. The counter reset is
a write function. The latches can be programmed to
compare with the counters at all times by writing 1's
into the 2 most significant bits of each latch, thus-establishing a don't care state in the latch. The don't
care state is programmable on the byte level, i.e., tens
of hours can contain a don't care state, yet unit hours
can contain a valid code necessary for a comparison.

Connection Diagram
Dual-In-Line Package

u

Functional Description
The MM58167 is a microprocessor oriented real time
clock. The ci rcuit includes addressable real time counters
and addressable latches, each for thousandths of seconds
through months. The counter and latch are divided into
bytes of 4 bits each_ When addressed, 2 bytes will appear
on the data I/O bus. The data, in binary coded decimal,
can be transferred to and from the counters via the data
I/O bus so that each set of 2 bytes (1 word) can be
accessed independently as grouped in Table I.

~Voo

iE- POWER DOWN

WJi2

~07

ROY..!

~06

Ao2

~05

Al~

~04

A2...2

i!!... 03

A3...!

~02

M-.!!

.,!.!!.. Ul

osc IN..!.!!

~OO
~ STANOBY INTERRUPT

OSC OUT..!.!

OUTPUT

~
TOPVIEW

Order Number MM58167N
See Package 22

5-347

INTERRUPT OUTPUT

~

Absolute Maximum Ratings
Voltage at All Inputs and Outputs
Operating Temperature
Storage Temperature
VOO -VSS
Lead Temperature (Soldering, 10 seconds)

Electrical Characteristics

Voo + 0.3 to VSS - 0.3
-25°C to +85°C
--65°C to +150°C
6V
300°C
T A = -25°C to +85°C,

vss = OV
TYP

MIN

CONDITIONS

PARAMETER

MAX

UNITS

Supply Voltage
VDO
VOO (Note 1)

Outputs Enabled

4.0

5.5

V

Power Down Mode

2.0

5.5

V

Supply Current
100, Static

Outputs TRI-STATE,

10

IJA

100, Dynamic

fiN = DC, VOO = 5.5V
Outputs TRI·STATE,

20

/lA

12

mA

fiN = 32 kHz, VOO = 5.5V,
100, Dynamic

VIH ;?VOD-0.3V, VIL -:::; VSS +0.3V
Outputs TRI-STATE,
fiN = 32 kHz, VOO = 5.5V,
VIH = 2.0V; VIL = 0.8V

Input Voltage
Logical Low

0.0

0.8

V

Logical High

2.0

VOO

V

;

Input Leakage Current

VSS -:::; VIN -:::; VOO

Output Impedance
. Logical Low

(liD and Interrupt Output)

Logical High

0.4

VOO = 4.75V, 10L = 1.6 mA

V
V

0.8VOO

VOUT= OV,
VOUT= VOO

Output Impedance

V

2.4

VOO = 4.75Vi 10H = --400 /lA,
10H = -101lA

TRI-STATE@

IJA

-1

IJA

1

/lA

(Ready and Standby Interrupt Output)

Logical Low, Sink

Voo = 4.75V, 10L = 1.6 mA

0.4

V

Logical High, Leakage

VOUT-:::;VOO

10

p.A

Note 1: To insure that no illegal data is read from or written into the chip during power up,'the power down' input should be enabled only after
all other lines (Read .. Write, Chip Select, and Data Bus) are valid.

Functional Description

(Continued)

COUNTER ADDRESSED
Ten Thousandths of a Second

DO

TABLE I
UNITS
D1 D2

0

0

0

D3

MAX USED
BCD CODE

D4

TENS
05 06

07

MAX USED
BCD CODE

0

0

I/O

I/O

I/O

I/O

9

Tenths and Hundredths of Seconds

I/O

1/0

I/O

I/O

9

I/O

I/O

I/O

I/O

9

Seconds

I/O

I/O

I/O

I/O

9

I/O

I/O

I/O

0'

5

Minutes

I/O

I/O

I/O

I/O

9

I/O

I/O

I/O

0

5

Hours

I/O

I/O

I/O

I/O

9

I/O

I/O

0

0

2

Day of the Week

I/O

I/O

I/O

0

7

0

0

0

0

0

Day of the Month

I/O

I/O

I/O

I/O

9

I/O

I/O

0

0

3

Month

I/O

I/O

I/O

I/O

9

I/O

0

0

0

1

5-348

Functional Description

3:
3:
(11

(Continued)

CO

.....

TABLE II. ADDRESS CODES AND FUNCTIONS
A4

A3

A1

AO

0

0

0

0

0

0

0

Counter

0

0

1

Counter

0

0

0

Hundredths and Tenths of Seconds

0

Counter

Seconds

0

0

0

0

0

0

0

Counter
Counter

Minutes
Hours

0

0

0

1

Counter

Day of the Week

0

0

1

0

Counter - Day of the Month

0

0

1

A2

FUNCTION

Counter -

Thousandths of Seconds

Months

0

0

0

0

Latches - Thousandths of Seconds

0

0

0

1

Latches

Hundredths and Tenths of Seconds

0

0

0

Latches

Seconds

1

1

Latches

Minutes

0

0

Latches

Hours

Latches

Day of the Week

Latches
Latches

Day of the Month

0
0
0

0
1
·1

0

0
0

1
1

1

1

1

0

0

0

Months
Interrupt Status Register

0

0

0
0

0

0

0

Counter Reset

0

0
0

Status Bit

0

Standby Interrupt

0

Interrupt Control Register
Latch Reset

0

0

0

0

0

"GO" Command
Test Mode

All others unused.

TABLE III. COUNTER AND LATCH RESET FORMAT
DO

D1

02

1

0

0
0

07

0

0
0

D4

D5

O.

0
0
0

0
0
0

.0
0

0

0

0

0

1

0
0

0

0

0

1

0

0

0

0

1

0

0

0

0

0

0

0

0

0

D6

D3

COUNTER OR LATCH RESET
Thousandths of Seconds
Hundredths and Tenths of Seconds

0

Seconds

0

0

Minutes

0

0

0

Hours

1

-'f"-J.-/>-r1160

~-~~.....

INPUT
Hz

1M

OUTPUT
ENABLE
BCO 2 t--....-'VVI;-t

lOOk
SETTO
60 Hz
WITH LINE
UNCONNECTED

FIGURE 5. Fail-Safe Automatic Lights Timer. Four Hours Each 24 Hours

circuits. Because of the vast number of timing applications possible, this can in no way be looked at as the
limit of clock-timer circuits. Use of the Reset on the
MM5309 and MM5315 or the use of clocks in conjunction
with programmable counters such as the MM74C161
allows other possibilities to meet specific applications.
Also the clock chips themselves can run on frequencies
other than 50 or 60 Hz (actually from dc to 10 kHz)
which can allow scaling of the waveforms presented in
Figure 3 to different timing rates.

easily obtain square waves with periods of two seconds,
two minutes, twenty minutes and two hours. In other
cases, where the waveforms are asymmetric, a simple
flip-flop can square, while dividing by two, these waveforms producing other low frequency square waves as
long as one per two days.
SUMMARY

We have shown some simple low cost timer and waveform
generating examples using National clock integrated

6-3

~
,...
.

z

«

BCD '---

.....

TO DISPLAY
COUNTERS

6 COUNTS

5 COUNTS

.JJ I I I I IU-

JJJI I I I I 1lJJ:.

FIGURE 1. Basic veo Scheme

6-5

l>
Z
•
......

en
en

FI GuFi E 2. Typical VCO Circuit

'IN

GATE

FIGURE 3. Early Display Configuration

".--,------.".
GATE

FIGURE 4, Integrated Circuit Display

6·6

COUNTER

-

COUNTER

COUNTER

-

COUNTER

ATE8

-

NPUT

LATCH

I I

-

LATCH

;--

1 I

LATCH

1 I

LATCH

;--

I

I

I

I1
DECOOER

-<
OISPLAY

DRIVE A

~

~

DISPLAY

DISPLAY

I

~
DISPLAY

I

MULTIPLEX
CONTROL

FIGURE 5. Multiplexed Display

While multiplexing cuts display costs considerably, the
series connection of counters required to accumulate the
counts proportional to voltage, could not be multi·
plexed to do the very nature of VCO or dual slope
voltmeter schemes.

repeated for the next digit. At a repetition rate of 50 Hz
or greater, this produces a flicker·free, blink·free display.
As such the recirculating remainder system has but one
counter, one latch, and one decoder driver for as many
digits as are desired. Once again CMOS is used for its
capability to swing directly to the supply rail and con·
trois the R-2R ladder directly from the reference voltage.

The recirculating remainder circuitry to be discussed
next is unique in that the data is both derived and
displayed on multiplexed, that is sequential digit basis
(as seen in Figure 6.)
The technique used in the recirculating remainder
circuit is to subtract digit valued voltage steps from the
input voltage, until ten times the difference between
these two voltages is less than ten times the digit valued
steps. The number of voltage steps required is the
display data and the ten times the difference voltage
becomes the new voltage input for the next digit
conversion. An example is shown in Figure 7.

Some disadvantages of the system are the difficulties in
reading voltages of both polarities and an unusual sort
of error characteristic when slight ladder or reference
drifts occur. While both VCO and dual slope techniques
have gradual slope or linearity errors, the recirculating
remainder errors are step·like in response to gradual input.
voltage changes. LastlY, the update rate is fixed by
display flicker requirements and thus measurements of
noisy voltages cause an annoying inability to read the
last digits. It was however, an accurate low-cost technique
used successfully in pre-LSI digital voltmeters.

An analog input of 6.903V is applied to the [(V 1N VSTEP ) x10] amplifier. The ';'12 and decade counters
are clocked simultaneously until a (difference x 10) less
than V REF is detected by the comparator. At this time,
the decade counter stops counting. In this example, the
decade counter ceases counting on a six during the digit
one period, thus a six is latched in the display. When the
digit period ends, both counters are reset and the
(difference x 10) voltage is recirculated via the CMOS
switch and sample and hold capacitor to become the
digit two input voltage (9.03V). The process is then

The most widely used system for analog-to-digital
conversion is the dual slope circuit. The basic dual slope
system appears in Figure 8. Assuming the integrator
output at zero when V x is applied, the integrator
begins to ramp with an output voltage V = Ix tiC
where Ix = -V x/R. Simultaneously with the beginning
of this ramping, counts from an oscillator are fed into
the display counters. At some fixed time, usually
counter overflow, V x would be disconnected and the
reference voltage connected to the resistor. The integrator now ramps at V = IREF tiC where IREF = VREF/R.

6-7

:t>
.....

z.

CJ1
CJ1

Lt')
Lt')

,.....
Z

.OOO

DIGITIZE

DIGITIZE

DIGITIZE

DIGITIZE

DlGlTJ

DIGITIZE
DIGIT 4

DIGIT 1

OIGIT2

DISPLAY
DIGIT4

DISPLAV

DISPLAY

DISPLAY

DISPLAY

DIGIT 1

OIGl12

DlGITJ

SWITCHES

DlGIT4

SWITCHES

SWITCHES

SWITCHES

SWITCHES

DIGIT 1

E&O

Ase

.S 0

Ase

"0

CLOSED

CLOSED

CLOSED

CLOSED

CLOSED

0.3
3.000
-3.000

FIGURE 7,0 Recirculating Remainder Waveforms

6-8

6.903V)

o 1.000V

steps-display 0

3 1.000V steps-display 3

l>
Z

.

~

CJ1
CJ1

Ix

-V

=

Vx

=-

R

IREF Tx
-c-

IxTREf

-c-

IREFTx

C

.". VXTREF" VREFTx

FIGURE 8. Basic Dual Slope

When the integrator crosses the comparator threshold,
the counters are latched to the number of counts
accumulated from T to T x. Clearly the voltage at T REF
was Ix T REF/C and the voltage integrated from T REF
to T x was -I REF T x/C and these two voltages are
equal. Therefore,
Ix T REF
C

C

The MM5330 is the display and control for a modified
dual slope system. It contains, as shown in Figure 9, the
counters and latches, together with a multiplexing
system to provide four digits of display with one
decoder driver. It also provides a sign digit, either plus
or minus, and a ten-thousand counts digit for a full
display of ±19999. By eliminating the right·most digits
it may also be used as a 2 1/2 or 3 1/2 digit DVM chip.

or
The basic modified dual slope system for which the
MM5330 is designed, is shown in Figure 10. The
integrator is now used in a non·inverting mode and is
biased to integrate negatively for all voltages below
VMAX . Thus, if the maximum positive voltage at V 1N
is 1.9999V, the VMAX would be set at 2.2000V. In this
way, all voltages measured are below V MAX • This
eliminates the need for reference switching and makes
the system automatic polarity, with no additional components. Also, it can be shown that the amplifier input
bias currents which cause the aforementioned errors in
conventional dual slope systems, are eliminated by
merely zeroing the display. Thus, low bias current op
amps are not necessarily required ul")less a high input
impedance is desired at V 1N •

Thus, the number of counts accumulated in the display
from T REF to T x is proportional to the unknown
voltage. Thus, the basic dual slope system has no gate,
and requires stability of the R, C and count frequency
only over one conversion period.
The technique for insuring that the ramp begins at zero
on each conversion cycle, is to short the capacitor with
a switch after each conversion is made. This, of course,
forces the integrator output to zero until the next
conversion period begins. It is also necessary to start
each conversion cycle synchronously with the counter
input frequency, or cyclic display errors like that of
the gated VCO will appear in the display.

Secondly, the use of a conventional op amp for a
comparator, allows zeroing of all voltage offsets in both
the op amp and comparator. This is achieved by zeroing
the voltage on the capacitor through the use of the
comparator as part of a negative feedback loop. During
the zeroing period, the non·inverting input of the
integrator is at V REF. As this voltage is within the active
common·mode range of the integrator the loop will
respond by placing the integrator and comparator in the
active region. The voltage on the capacitor is no longer
equal to zero, but rather to a voltage which is the sum
of both the op amp and comparator offset voltages.
Because of the intrinsic nature of an integrator, this
constant voltage remains throughout the integrating
cycle and serves to eliminate even large offset voltages.

To measure both polarities in conventional dual slope
systems, V REF must change in polarity. A problem
which can occur is that bias currents which will add to
the slope in one polarity, will subtract from the slope in
the other. The usual solution, is to use op amps of very
low input bias current. Also offset voltages in either the
op amps or comparator can cause significant error
unless carefully controlled.
Hence, while conventional dual slope has many advan·
tages, its use requires considerable care in op amp, and
comparator selection. Also, the measurement of eith"er
polarity requires two reference voltages which are, in
accurate systems, quite expensive.

6-9

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The specification or selection of analog-to-digital (A/D)
or digital-to-analog (D/ A) converters can be a chancey
thing unless the specifications are understood by the
person making the selection_ Of course, you know you
want an accurate converter of specific resolution; but
how do you insure that you get what you want? For
example, 12 switches, 12 arbitrarily valued resistors, and
a reference will produce a 12-bit DAC exhibiting 12
quantum steps of output voltage. In all probability, the
user wants something better than the expected performance of such a DAC. Specifying a 12-bit DAC or an
ADC must be made with a full understanding of accuracy,
linearity, differential linearity, monotonicity, scale, gain,
offset, and hysteresis errors.

Accuracy is sometimes considered to be a non-specific
term when applied to D/A or A/D converters. A linearity
spec is generally considered as more descriptive. An
accuracy specification describes the worst case deviation
of the DAC output voltage from a straight line drawn
between zero and full scale; it includes all errors. A
12-bit DAC could not have a conversion accuracy better
than ±\I, LSB or ±1 part in 212+1 (±0.0122% of full
scale due to finite resolution). This would be the case in
figure 1 if there were no errors. Actually, ±0.0122% FS
represents a deviation from 100% accuracy; therefore
accuracy should be specified as 99.9878%. However,
convention would dictate 0.0122% as being an accuracy
spec rather than an inaccuracy (tolerance or error) spec.

This note explains the meanings of and the relationships
between the various specifications encountered in A/D
and D/A converter descriptions. It is intended that the
meanings be presented in the simplest and clearest
practical terms. Included are transfer curves showing the
several types of errors discussed. Timing and control
signals and several binary codes are described as they
relate to A/D and D/A converters.

Accuracy as applied to an ADC would describe the
difference between the actual input voltage and the fullscale weighted equivalent of the binary output code;
included are quantizing and all other errors. If a 12-bit
ADC is stated to be ±1 LSB accurate, this is equivalent
to ±0.0245% or twice the minimum possible quantizing
error of 0.0122%. An accuracy spec describes the
maximum sum of all errors including quantizing error,
but is rarely provided on data sheets as the several errors
are listed separately.

MEANING OF PERFORMANCE SPECS

Resolution describes the smallest standard incremental
change in output voltage of a DAC or the amount of
input voltage change required to increment the output of
an ADC between one code change and the next adjacent
code change. A converter with n switches can resolve 1
part in 2n_ Th'e least significant increment is then 2- n , or
one least significant bit (lSB). In contrast, the most
significant bit (MSB) carries a weight of 2-1. Resolution
applies to DACs and ADCs, and may be expressed in
percent of full scale or in binary bits. For example, an_
ADC with 12-bit resolution could resolve 1 part in 212
(1 part in 4096) or 0.0245% of full scale. A converter
with 10V full scale could resolve a 2.45mV input change.
Likewise, a 12-bit DAC would exhibit an output voltage
change of 0.0245% of full scale when the binary input
code is incremented one binary bit (1 LSB). Resolution
is a design parameter rather than a performance specification; it says nothing about accuracy or linearity.

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FS

>=>
>=>
o

'"o
~.

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o~----------------000 001

010 011

100 101

110 111

DIGITAL CODE

FIGURE 1.

Linear CAe Transfer Curve Showing Minimum
Resolution Error and Best Possible Accuracy

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cation of ±Y, LSB linearity implies error in addition to
the inherent ±v, LSB quantizing or resolution error. In
reference to figure 2, showing no errors other than
quantizing error, a linearity error allows for one or more
of the steps being greater or less than the ideal shown.

Differential Non-Linearity indicates the difference between actual analog voltage change and the ideal (1 LSB)
voltage change at any code change of a DAC. For
example, a DAC with a 1.5 LSB step at a code change
would be said to exhibit V, LSB differential nonlinearity (see figures 6 and 7). Differential non-linearity
may be expressed in fractional bits or in % FS.

Figure 6 shows a 3·bit DAC transfer curve with no more
than ±Y, LSB non·linearity, yet one step shown is of zero
amplitude. This is within the specification, as the maxi·
mum deviation from the ideal straight line is ±1 LSB
(V, LSB resolution error plus V, LSB non-linearity). With
any linearity error, there is a differential non-linearity
(see below)_ A ±Y, LSB linearity spec guarantees
monotonicity (see below) and ~ ±1 LSB differential nonlinearity (see below). In the example of figure 6, the
code transition from 100 to 101 is the worst possible
non-linearity, being the transition fr.om 1 LSB high at
code 100 to 1 LSB low at 110. Any fractional nonlinearity beyond ±Y, LSB will allow for a non-monotonic
transfer curve. Figure 7 shows a typical non-linear curve;
non-linearity is 1 % LSB yet the curve is smooth and
monotonic.

Differential linearity specs are just as important as linearity specs because the apparent quality of a converter
curve can be significantly affected by differential nonlinearity even though the linearity spec is good. Figure 6
shows a curve with a ±Y, LSB linearity and ±1 LSB
differential non-linearity while figure 7 shows a curve
with +1 % LSB linearity and ±Y, LSB differential nonlinearity. In many user applications, the curve of figure 7
would be preferred over that of figure 6 because the
curve is smoother. The differential non-linearity spec
describes the smoothness of a curve; therefore it is of
great importance to the user. A gross example of differential non-linearity is shown in figure 8 where the
linearity spec is ±1 LSB and the differential linearity
spec is ±2 LSB. The effect is to allow a transfer curve
with grossly degraded resolution; the normal 8-step curve
is reduced to 3 steps in figure 8. Similarly, a 16-step
curve (4-bit converter) with only 2 LSB differential nonlinearity could be reduced to 6 steps (a 2.6-bit converter?). The real message is, "Beware of the specs."
Do not ignore or omit differential linearity characteristics on a converter unless the linearity spec is tight
enough to guarantee the desired differential linearity. As
this characteristic is impractical to measure on a production basis, it is rarely, if ever, specified, and linearity is
the primary specified parameter. Differential non-linearity can always be as much as twice the non-linearity, but
no more.

FS

1 lSB OIH
NON.lINEA1

}} lSB DIFF
NON·lINEAR

/

t

/}lSB
/}I%lSB

o /
000 001

010 011

1(10 101

110 111

DIGITAL CODE

FIGURE 6.

±y, LSB Non-Linearity (Implies 1 LSB Possible
Error), 1 LSB Differential Non-Linearity (Implies
Monotonicity )

FS

/
/
/

% lSB DIH

y, lSB OIH'"
NON·lINEAR

NON'~INEAR

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3 lSB

;.,..--;../
---It
/

lSB
/

/

j/ /

2 lSB OIFF

~JON.lINEAR)

FS

/

/

3lSB

2lSB OIFF
NON·lINEAR

0 .........- ' - - - - - - - - - - - - 000 001 010 all 100 101 110 111

OIGITAl COOE
O~--L-------------

000 001 010 011 100 101 110 111

FIGURE 8.

±1 LSB Linear, ±2 LSB Differential Non-Linear

OIGITAL CODE

FIGURE 7. 1% LSB Non-Linear, % LSB Differential NonLinearity

Monotonicity. A monotonic curve has no change in sign
of the slope; thus all incremental elements of a monotonically increasing curve will have positive or zero, but
never negative slope. The converse is true for decreasing
curves. The transfer curve of a monotonic DAC will
contain steps of only positive or zero height, and no
negative steps. Thus a smooth line connecting all output
voltage points will contain no peaks or dips. The transfer
function of a monotonic ADC will provide no decreasing
output code for increasing input voltage.

Linearity specs refer to either ADCs or to DACs, and do
not include quantizing, gain, offset, or scale errors.
Linearity errors are of prime importance along with
differential linearity in either ADC or DAC specs, as all
other errors (except quantizing, and temperature and
long-term drifts) may be adjusted to zero. Linearity
errors may be expressed in % FS or fractional LSB.

6-15

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Figure 9 shows a non-monotonic DAC transfer curve.
For the curve, to be non·monotonic, the linearity error
must exceed ±y, LSB no matter by hqw little. The
greater the linearity error, the more significant the
negative step might be. A non-monotonic curve may not
be a special disadvantage in some systems; however, it is
a disaster in closed-loop servo systems of any type
(including a DAC-controlled ADC). A ±Y, LSB maximum
'linearity spec on an n-bit converter guarantees monotonicity to n bits. A converter exhibiting more than ±y,
LSB non-linearity may be monotonic, but is not
necessarily monotonic. For example, a 12-bit DAC with
±Y, bit linearity to 10 bits (not ±y, LSB) will be mono·
tonic at 10 bits but mayor may not be monotonic at 12
bits unless tested and guaranteed to be 12-bit monotonic.

2V!OIV

2psJOIV,

I ~to:r- SETTLING TIME
DAC OUTPUT

It

I

CONTROL lOGIC

J
1-

SLEW TIME

lal Full-Scale Step

y, LSB DIFF
NON-LINEAR

FS

I

1%

lS8

/

t/

/

10 mV!OIV

CONTROL lOGIC

;' ~/ 11Yz LSB
IlSB

/\

~

lYIlSBDIFF

1_

I I
SETTLING TIME

II
II
000

001

010

011

100 101

110

lps/DlV

111

DIGITAL CODE

(bl 1 LSB Step
FIGURE 9.

Non-Monotonic (Must be

> ±Y2

FIGURE 10.

LSB Non-Linear)

DAC Slew and Settling Time

bits are switched). These glitches are normally of
extremely short 'duration but could be of y, scale
amplitude. The current switching glitches are generally
somewhat attenuated at the voltage output of the DAC
because the output amplifier is unable to slew at a very
high rate; they are, however, partially coupled around
the amplifier via the amplifier feedback network and
seen at the output. The output amplifier introduces
overshoot and some non-critically damped ringing which
may be minimized but no't entirely eliminated except at
the expense of slew rate and settling time.

Settling Time is the elapsed time after a code transition
for DAC output to reach final value within specified
limits, usually ±Y, LSB. (See also Conversion Rate below.)
Settling time is often listed along with a slew rate
specification; if so, it may not include slew time. If no
slew rate spec is included, the settling time spec must be
expected to include slew time. Settling time is usually
summed with slew time to obtain total elapsed time for
the output to settle to final value. Figure 10 delineates
that part of the total elapsed time which is considered to
be slew and that part which is settling time. It is
apparent from this figure that the total time is greater
for a major than for a minor code change due to
amplifier slew limitations, but settling time may also be
different depending upon ,amplifier overload recovery
characteristics.

Temperature Coefficient of the various components of a
DAC or ADC can produce or increase any of the several
errors as the operating temperature varies. Zero scale
offset error can change due to the TC of the amplifier
and comparator input offset voltages and currents. Scale
error can occur due to shifts in the reference, changes in
ladder resistance or non-compensating RC product shifts
in dual-slope ADCs, changes in beta or reference current
in current switches, changes in amplifier bias current, or
drift in amplifier gain-set resistors. Linearity and monotonicity of the DAC can be affected by differential
temperature drifts of the ladder resistors and switches.
Overshoot, settling time, and slew rate can be affected
by temperature due to internal change in amplifier gain
and bandwidth. In short, every specification except
re~olution and quantizing error can be, affected by
temperature changes.

Slew Rate is an inherent limitation of the output
amplifier in a DAC which limits the rate of change of
output voltage after code transitions. Slew rate is usually
anywhere from 0.2 to several hundred voltsl/1s. Delay in
reaching final value of DAC output voltage is the sum of
slew time and settling time as shown in figure 10.
Overshoot and Glitches occur whenever a code transition
occurs in a DAC. There are two causes. The current
output of a DAC contains Iwitching glitches due to
possible asynchronous switching of the bit currents
(expected to be worst at half-scale transition when all

6-16

»
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Long-Term Drift, due mainly to resistor and semiconductor aging can affect all those characteristics which
temperature change can affect. Characteristics most
commonly affected are linearity, monotonicity, scale,
and offset. Scale change due to reference aging is usually
the most important change.

coded system. For example, a 12-bit BCD system has a
resolution of only 1 part in 1000 compared to 1 part in
4096 for a binary system. This represents a loss in
resolution of over 4: 1.

Supply Rejection relates to the ability of a DAC or ADC
to maintain scale, offset, TC, slew rate, and linearity
when the supply voltage is varied. The reference must, of.
course, remain constant unless considering a multiplying
DAC. Most affected are current sources (affecting
linearity and scale) and amplifiers or comparators
(affecting offset and slew rate). Supply rejection is
usually specified only as a % FS change at or near full
scale at 25°C.
Conversion Rate is the speed at which an ADC or DAC
can make repetitive data ·conversions. It is affected by
propagation delay in counting circuits, ladder switches
and comparators; ladder RC and amplifier settling times;
amplifier and comparator slew rates; and integrating time
of dual-slope converters. Conversion rate is specified as a
number of conversions per second, or conversion time is
specified as a number of microseconds to complete one
conversion (including the effects of settling time). Sometimes, conversion rate is specified for less than full
resolution, thus showing a misleading (high) rate.
Clock Rate is the minimum or maximum pulse rate at
which ADC counters may be driven. There is a fixed
relationship between the minimum conversion rate and
the clock rate depending upon the converter accuracy
and type. All· factors which affect conversion rate of an
ADC limit the clock rate.

Offset Binary is a natural binary code except that it is
offset (usually '12 scale) in order to represent negative and
positive values. Maximum negative scale is represented to
be all "zeros" while maximum positive scale is represented
as all "ones." Zero scale (actually center scale) is then
represented as a leading "one" and all remaining "zeros."
The comparison with binary is shown in figure 11.
Twos Complement Binary is an alternate and more
widely used code to represent negative values. With this
code, zero and positive values' are represented as in
natural binary while all negative values are represented
in a twos complement form. That is, the twos complement of a number represents a negative value so that
interface to a computer 'or microprocessor is simplified.
The twos complement is formed by complementing each
bit and. then adding a 1; any overflow is neglected. The
decimal number -8 is represented in twos complement
as follows: start with binary code of decimal 8 (off
scale for ± representation in 4 bits so not a valid code in
the ± scale of 4 bits) which is 1000; complement it to
0111; add 0001 to get 1000. The comparison with offset
binary is shown in figure 11. Note that the offset binary
representation of the ± scale differs from the twos
complement representation only in that the MSB. is
complemented. The conversion from offset binary to
twos complement only requires that the MSB be inverted.
111

Input Impedance of an ADC describes the load placed
on' the analog source.

110
101
co

Output Drive Capability describes the digital load driving
capability of an ADC or the analog load driving capacity
of a DAC; it is usually given as a current level or a voltage
output into a given load.

8

...

'00

~ 011

!;;
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001

CODES
Several types of DAC input or ADC output codes are in
common use. Each has its advantages depending upon
the system interfacing the converter. Most codes are
binary in form; each is described and compared below.
Natural Binary (or simply Binary) is the usual 2 n code
with 2, 4, 8, 16, ... , 2 n progression. An input' or output
high or "1" is considered a signal, whereas a "0" is
considered an absence of signal. This is a positive true
binary signal. Zero scale is then all "zeros" while full
scale is all "ones."

ANALOG SCALE

la) Zero to + Full-Scale
011 011 111
010 010 110
001 001 101
000 000 100
100

'complementary Binary (or Inverted Binary) is the
negative true binary system. It is identical to the binary
code except that all binary bits are inverted. Thus, zero
scale is all "ones" while full scale is all "zeros."

-~

-y,

101 111 011
110 110 010
111 101 001

Binary Coded Decimal (BCD) is the representation of
decimal numbers in binary forn" It is useful in ADC
systems intended to drive decimal displays. Its advantage
over decimal is that only 4 lines are needed to represent
10 digits. The disadvantage of coding DACs or ADCs in
BCD is that a full 4 bits could represent 16 digits while
only 10 are represented in BCD. The full-scale resolution
of a BCD coded system is less than that of a binary

100 000
LOFFSET BINARY
TWOS COMPLEMENT BINARY
SIGN + MAGNITUDE

t t

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±

Full-Scale

FIGURE 11. ADC Codes

6-17

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1-----------....

PROGRAM
DIGITS 1-4

CONTROL ClOUT

olVIOE
SCALER
FUNCTIONS

1-7

BCD OUTPUTS
BUFFER

CONTROL CllN

DIGIT OUTPUTS

FINAL EVENT

1-----------....

COMPARATOR ENABLE

CONTROL C2 OUT

~.,OSCIN,

-.....,-...;-+---1

MULTIPLEX OUT . .

'

~'OSCOUT

MULTIPLEX IN

L-_--I

CLOCK IN/OUT

------1......--....,.---1

I-----~ BLANKING

RESOLUTION - - - - - - - - - - - - - - - -....
SELECT ...;;,._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..J

Figure ',. Internal block diagram of the MM5865 Universal Timer.

DIVIDE SCALER 1
DIVIDE SCALER2
DIVIDE SCALER 3
COMPARATOR ENABLE
FUNCTION 1

Vss

2

PROGRAM DIGIT I/LATCH CONTROL/LSD
PROGRAMDIGIT2
PROGRAM DIGIT 3
PROGRAM DIGIT 4/WAITING STATE/MSD
CONTROL CIIN
34
CONTROL ClOUT
33
J2 BCD 1
31 BeDl 7 SEGMENTS
BCD4
.
BCOB
29
DIGIT !/LSD MM5865/N
0lGI12
21
DIGIT3
2&
DIGIT4/MSD
25
CONTROL C2 OUT
24 CONTROL C21N
23
MULTIPLEX IN
MULTIPLEX OUT
21
VDD

"

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FUNCTION 2
FUNCTIONl
fUNCTION 4
FUNCTIONS

10
FUNCTION 6
FUNCTION 1
12
FINAL EVENT STDP/COMPARATOR OUT
RESET
14
START/STOP
15
CLOCK INIOUT
RESOLUTION SElECT 1
17
RESOLUTION SELECT 2
BLANKING
OSCIN
20
OSCOUT

"
"
"
""

~

MM5B65/N

"

"

TOPYIEW

Figure 2. MM5865 connection diagram.

6-20

When an external multiplex rate is applied, to the Multiplex Input pin, the MUltiplex ,Output pin must be connected to Vss, and the Oscillator In, Oscillator Out, and
Blanking pins should be floating. The multiplex rate
inside .the chip is one fourth the frequency applied to
the Multiplex Input pin. In this mode of operation ,two
MM5865s may not be cascaded., In fact; to make use of
the Multiplex Output pin, the Multiplex Input pin must
be connected to VOD. The frequency at ,the Multiplex
Output pin is the same as that applied to the Multiplex
Input pin.
'
The multiplexer may also be controlled by using internal
MOS circuits to form a crystal controlled oscillator. To
form the oscillator·a crystal, two capacitors, and one
resistor must be added externally. One of the capacitors
should be' variable to allow precise frequency settings.
When these external components are connected to the
Oscillator Input and Oscillator Output pins, the Multiplex input pin must be connected to "DO.
When the input clock is at a constant frequency above
400Hz the Multiplex Input'pin maybe connected to the
Clock Input pin. In this mode of operation the input
clock which is being counted is also used as the externally generated multipl~x frequency. The multiplex
rate inside the chip will be one fourth the clock input
. frequency as described above.

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Oscillator

Control Logic

Figure 3 shows how external components may be
connected to the Oscillator Input and Output pins. A
frequency counter used to adjust the frequency of the
oscillator may be connected to the Oscillator Output pin
through a 50pF capacitor.

The block labeled "Control Logic" con~ains the logic
required to select one of the seven functions, reset all
logic and counters, start and stop the counters, indicate
that a final event has occurred, and display counter 2 in
Functions 3 and 4.
The selection of a function is accomplished by connecting one of the seven function pins to Vss; the other six
function pins are left floating.

Vss

.----+-.... TO

DIVIDER
CIRCUITS

VDD

INTERNAL

The Reset Input will reset all logic and counters in
Functions 1 - 5 and Function 7. In Function 6, Reset
will reset logic and counter 2. but not counter 1. For
reset to occur the Reset pin must be momentarily
connected to Vss. Internal control logic provides poweron reset, however, to insure proper power-on resetting
of aillogicandthe counters a 10.uF, 35V Solid Tantalum
Capacitor (Allied # 852-5680) should be used across the
VSS - VOO power busses.
In Function 6, the Reset Input pin may be connected
to the Comparator Output pin in order to automatically
reset logic and counter 2. When this connection is made,
a Start/Stop transition is all that is needed to repeat the
up count of counter 2.

Figure 3. Crystal oscillator connections.

The Start/Stop Input is used to control the counters by·
momentarily connecting pin 14 to Vss. The manner in
which this input affects the counters during the execu·
tion of each function will be explained as the descriptions of the functions are given.

Divider
The divider stages produce the blanking output by
dividing the oscillator input frequency by 41. This
output is used to blank the display at the beginning and
end of each digit time to allow for internal delay between
two cascaded chips. The display is blanked when the
Blanking Output is at VO D.
The divider stages then divide the blanking output by 2
to generate the Multiplex Output. The frequency which
appears at the Multiplex Output pin is further reduced in
frequency by the divider stages so that the Resolution
Select pins may be used to program the resolution of the
display. Table I shows how these two inputs are used to
select the frequency of the internal clock pulses to be .
appl ied to the two counters. The frequencies and display
resolutions for an oscillator frequency of 32.8kHz are
given.

The Final Event Stop/Comparator Output pin is used to
indicate to the circuit that no more events will be timed
or counted. Final Event Stop affects the circuit when it
is momentarily connected to Vss. When this pin is used
as the comparator output, a Vss level at the pin indicates
comparison between the two counters.
. Additional Control Logic
The three Divide Scaler inputs permit the counters to
be programmed to count in Modulo 6 or Modulo 10.
Table /I shows the possible codes which may be applied
to the Divide Scaler pins. A zero indicates that the pin
is left floating (or connected to Voo); a one indicates
that the pin is connected to Vss.

Table I. Resolution Select Code. A zero indicates that the pin is
left floating (or connected to Voo); a one indicates that the pin
is connected to VSS' Note that when an external clock is applied
to pin 15, pins 16 and 17 must be connected to VSS'

Resolution Select
Pin 16
0
0
1
1

Pin 17
0
1
0
1

Table II. Divide Scaler Code

Counter 1

1

Pin
2

3

4

Digit
3 2

0
1
0
1
0
1
0
1

0
0
1
1
0
0
1
1

0
0
0
0
1
1
1
1

10
6
10
10
10
10
10
10

10 10 10
10 10 10
6 10 10
10 6 10
10 10 10
10 10 10
10 10 10
10 10 10

Frequency of
Display Resolution
Clock to Counters
100Hz
10Hz
1 Hz
External

0.01 sec
0.1 sec
1
sec

-

The Clock Input/Output pin is either an input or an output depending on the code at the Resolution Select input
pins. If the pin is used as an output it will output the
clock frequency selected by the program appl ied to pins
16 and 17. When it is used as an input an external clock
must be used to clock the counters.

Modulo

Divide
Scalers

Counter 2
1

Digit
2

4

3

10
6
10
10
10
6
10
10

10 10 10
10 10 10
6 10 10
10 6 10
10 10 10
10 10 10
6 10 10
10 6 10

1

A zero indicates that the pin is left floating (or connected to
VOO); a one indicates that the pin is connected to Vss·

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Figure 4. Stopwatch/Timer application showing the ·connections
described in the text.

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6-22

S11 {

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RESET

S12

yl- START/STOP

single MM5865. Two cascaded'MM5865s may also be

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Pins 36 - 39, the Program Digit 1 - 4 pins, are used to
program a desired count into counter 1 when using
functions 6 and 7. When any of the four Program Digit
pins are connected toVss, the display digit of counter 1
associated with that pin advances at a 2.5 Hz rate (assuming the oscillator frequency is 32.8kHz). The Program
Digit 1 pin advances the least significant digit of counter
1; the Program Digit 4 pin advances the most significant
digit. There is no carryover from digit to digit, and only
one Program Digit Input may be connected to Vss at
a time.

must be provided if every digit of the display is to be
programmable. In addition, 'another switch would have
to be provided to break the pin 39 connection between
the two chips in functions 6 and 7. Of course, all of the
switching action could be provided by one ganged
rotary switch if desired; even the function 6 Reset to
Comparator Out connection could be accomplished if
the proper switch were used.
Electrical Characteristics
The maximum supply voltage which may be connected
between Vss and Voo (Voo ~ OV) is 20V. National
specifies that the minimum voltage at which the chip
will operate is 7V; however, some chips will operate well
down to Vss ~ 5V. With a 9V transistor battery used as
the power supply, and display inhibited, the power
supply current will be approximately 7mA to 15mA for
a one-chip stopwatch.
'

The Program Digit 1 pin also functions as a counter 2
latch control in functions 3 and 4. In functions 3 and 4,
momentarily connecting the Program Digit 1/Latch
Control pin to Vss permits the display to show counter
2 counting.
The Progra~ Digit 4 pin also serves two purposes; in
functions 1 - 5 this pin indicates that the chip has been
reset and is in the standby mode at power·on. Visual
indication of this condition may be accomplished by
connecting a transistor between the Program Digit 4/
Waiting State Indicator pin and the Segment DP Anode
of a multiplexed display. With the transistor connected
as shown in Figure 4, the Waiting State Indicator pin will
be at Vss at power·on until a Start/Stop transition
occurs. After a Start/Stop transition occurs, the Waiting
State Indicator pin will remain at Voo until power is
removed from the chip.
'

The maximum input frequency atthe oscillator is 80kHz;
however, the oscillator and dividers are designed for stopwatch applications using a 32.8kHz crystal. (A
32.768kHz crystal, available from Quest Electronics,
P.O. Box 4430 E, Santa Clara, CA 95054, may be used
without much loss in accuracy.)
Drivers must be provided for the Digit and BCD Outputs.
Two MM5865s interface directly with the MM14511
Segment Driver and the DS8863 Digit Driver. A DS8877
or DS75492 Hex Digit Driver may be used with a single
MM5865.

Leading Zero, Blanking
In functions 1 - 5, leading zeros are blanked for both
counters. In functions 6 and 7, counter 2 has leading
zero blanking but counter 1 does not. At power-on the
display is blank (or all decimal points if the Waiting
State Indicator pin is used) in functions 1 - 5; all zeros
are displayed in functions 6 and 7.

The Seven Functions
The one-chip circuit shown in Figure 4 indicates all
connections necessary to employ the MM5865 as a 4digit stopwatch!timer. The seven available functions will
be described using this figure, in which the desired
function is selected by switching S5. When necessary,
refer also to Figures 1 through 3.

Control Cl, C2 In and Control Cl, C2 Out
These four pins are used to cascade two chips together.
In this mode of operation the primary MM5865, which
is directly controlled by the crystal oscillator, connects
to another MM5865 in the following manner: the
Control C1 In pin of the primary chip is connected
to VSS except during,digit programming in function 7;
the Control C1 Out pin connects to the Control C1 In
pin of the other MM5865; the Control C2 In pin of the
primary chip is connected to Vss; the Control C2 Out
pin connects to the Control C2 In pin of the other
MM5865; the Control C1 Out and the Control C2 Out
pins of the second chip are left floating.

Function 1
In function 1, at power-on (Sl closed) four decimal
points are visible on the display, indicating that the
counters have, been reset, but not necessarily all logic.
If the Comparator Enable pin is connected to Vss (S3
in Function 6 - 7 position) at power-on, a Start/Stop
transition (obtained, by momeritarily closing S12) will
cause the decimal points to disappear from the display;
however, the chip will not begin counting. First it is
necessary to place S3 in the Functions 1 - 5 position,
then to reset the logic (by momentarily closing S11).'
Once all logic is reset (either by applying power with S3
in the Functions 1 - 5 position or by the method discussed above). a Start/Stop transition will cause both
counters to begin counting up. The up-count of counter
2 is displayed, the least significant digit advancing at a
1 Hz rate. A second Start/Stop transition inhibits the
clock pulses to counter 2 and stores and displays the
contents of counter 2; however, counter 1 continues to
count. A third Start/Stop transition resets counter 2,
enables clock pulses to counter 2 and, again, displays
counter 2 counting up. Subsequent Start/Stop transitions repeat this sequence. Counter 1 continues to
count, from the time of the first Start/Stop transition,
unti,l the occurrence of a Final Event Stop transition
(obtained by momentarily closing S10). A Final Event

When the Conttol C1 In pin is floati'ng (or connected
to Voo), the clock pulses to counter 1 are inhibited.
When the Control C1 In pin is connected to VSS, counter
1 is enabled. Control ClOut is at Vss when counter 1 is
at its maximum count, and it is floating at all other
times. The Control C2 pins affect counter 2 in a similar
manner.
Other possible connections between the two chips are:
1) all function pins connected together, 2) pins 12, 13,
14, and 15 connected together, 3) all BCD pins con·
nected together, and 4) pins 39 connected together in
functions 1 - 5 only.
When' two MM5865s are cascaded as described above,
eight momentary switches or individual electrical signals

6-23

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transition stores and displays the contents of counter 2.
Subsequent Start/Stop transitions update the display of
counter 2. A Latch Control transition will display
counting until the occurrence of a Start/Stop transition.
This Start/Stop transition, following the Latch Control
transition, does not reset counter 2 as it does in function
3. Rather, counter 2 continues to count up.- A Final
Event Stop transition inhibits the clock pulses to
counter 2 and displays' the contents of counter 2. A
Reset transition at any time resets counter 2·to "0000."

Stop transition inhibits the clock pulses to both counters
and displays counter 2. After this Final Event Stop
transition has occurred, a Start/Stop transition switches
the display from counter 2 to counter 1. Each subse·
quent Start/Stop transition alternately displays one of
the counters.
'
To summarize, in function 1 both counters start counting
up with an initial Start/Stop transition. Counter 1
continues to count (recording total elapsed time) until
a Final Event Stop transition. Counter 2 (alternately)
starts, then stops counting with each Start/Stop transition (timing as many intervals as desired), until a Final
Event Stop transition. Any time a Reset transition
occurs both counters are reset to "0000" and the 'display
blanks.

Function 5
Again, in. function 5 the power,on conditions are the
same as those in functions 1 -4. Once all logic is reset a
Start/Stop transition causes both counters to begin
counting up. Counter 2 is displayed counting. A second
transition on the Start/Stop pin inhibits the clock pulses
to counter 2, and the contents of counter 2 are displayed. Counter 1 continues to count. A third Start/
Stop transition enables the clock pulses to counter 2;
counter 2 resumes countingwhere it left off, and counter
2 is displayed counting.

Function 2
The only difference between functions 1 and 2 is that in
function 2, whenever a Start/Stop transition inhibits the
clock pulses to counter 2, the clock pulses to counter 1
are also inhibited. Start/Stop transitions which reset
counter 2 and enable clock pulses to counter 2 also
enable clock pulses to counter 1; counter 1 does not
reset, however. The up·count in counter 1 resumes at the
stored count; therefore, counter 1 records total accumulated time.

Subsequent Start/Stop transitions repeat this' sequence
with counter 1 counting continuously. A Final Event
Stop transition inhibits. the clock pulses to both counters
and displays counter 2. A 'Start/Stop transition switches
the display from counter 2 to counter 1. Repetitive
Start/Stop transitions switch the display between
counter 2 and counter 1. A Reset transition at any time
resets both counters to "0000."

Function 3
In function 3 the power·on conditions are the same as
those.in functions 1 and 2. Once all logic is reset a Start/
Stop transition causes both counters to begin counting
up Counter 2 is displayed counting. A second Start/Stop
transition stores and displays the contents of counter 2,
resets counter 2, and initiates a new up·count. However,
the new up·count is not displayed; Counter 1 continues
to count. The initial count remains displayed until a
third Start/Stop transition. This third Start/Stop transi·
tion and subsequent Start/Stop transitions repeat the
sequence described above, indicating the length of tfme
between successive Start/Stop transitions.
The occurrence of a Latch Control transition (obtained
by. momentarily closing S5) any time after .the second
Start/Stop transition will cause counter 2 to be displayed
while counting. The count will continue to be displayed
until a Start/Stop transition. This Start/Stop transition
also .stores and displays the contents of counter 2 and
then resets counter 2. As before, counter 1 continues to
count, but counter 2 begins a new count.
A Final Event Stop transition inhibits the clock pulses
to both counters and displays the contents of counter 2.
A Start/Stop transition occurring after the Final Event
Stop transition switches the display from counter 2 to
counter 1. Repetitive Start/Stop transitions switch the
display between counter 2. and counter 1. Any time a
Reset. transition occurs,. both counters are reset to
"0000" and the display blanks.

Function 6
At power·on in function 6, counter 1 is displayed with
"0000." If the comparator is enabled (S3 in the
Function 6-7 position) at power on, a Reset transition
(obtained by momentarily closing S11) is necessary
before a Start/Stop transition can begin the counter 2
count·up.
Counter 1 is ,programmed to the desired count by
holding each of the four Digit Programming Switches
Closed in turn. The comparator must then be enabled by
placing S3 in the Function 6 - 7 position (unless it was
already enabled at power·on). Counter 2 is diSPlayed
counting up beginning with a Start/Stop transition.
, When counter 2 is coincident with counter 1, the clock
pulses to counter 2 are inhibited, the contents of
counter 2 are displayed, and the Comparator Output is
enabled. A Reset transition after the counter 2/counter 1
coincidence disables the Comparator Output and
displays counter 1 with the programmed time. The Reset
transition can be obtained either by momentarily'
closing S11 or by. connecting the reset Input pin to the
Comparator Output pin after· Digit Programming.so.that
logic and counter 2 are reset automatically whenever
counter 2 is coincident with counter 1.
After each Reset transition, subsequent Start/Stop
transitions repeat the sequence. Counter 1 may be reprogrammed after any Reset transition, if desired. If a
Reset transition occurs while counter 2 is counting up,
the clock pulses to counter 2 are inhibited, counter 2
is reset, and counter 1 is displayed with the programmed
time.

Function 4
In function 4 the power·on conditions are the same as
those in functions 1 - 3. Once all logic is reset a Start/
Stop transition causes counter 2 to begin up·counting.
Counter 2 is displayed counting. A second Start/Stop

6-24

»
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output drive capability of 25mA. The DS8863 is an
8-digit driver; each driver is capable of sinking up to
75mA. The MM14511 may be operated at supply
voltages up to 15 V; however, the DS8863 cannot be
operated with supply voltage greater than 10V. For
operation with supplies up to 18V, the DS8963 is a
direct replacement for the DS8863.

If a Start/Stop transition occurs while counter 2 is
counting up, the clock pulses to counter 2 are inhibited
and counter 1 is displayed with the programmed time.
With the next Start/Stop transition, counter 2 resumes
counting where it was stopped.
If the Reset Input pin is not connected to the
Comparator Output pin and if a Final Event Stop tran·
sition occurs while counter 2 is counting up, the clock
pulses to counter 2 are inhibited and the contents of
counter 2 are displayed. The next Start/Stop transition
displays counter 1 with the programmed time. Repeti·
tive Start/Stop transitions switch the display between
counter 2 and counter 1. A Reset transition followed by
a Start/Stop transition starts the counter 2 up·count
sequence again.

The NSA398 is a 9-digit common cathode LED numeric
display with a 1/8-inch character height. Eight inputs
are provided for selection of the appropriate segments
and decimals (anodesl and nine inputs for digit
!cathodesl selection. The anodes are internally interconnected for mUltiplexing. The NSA398 has a red
faceplate which provides excellent visual contrast and
ease of visibility over a wide angle. Figure 5 shows the
physical dimensions and pin connections of the NSA398.

In function 6, and also in function 7, the digit which is
preprogrammed to count in Modulo 6 cannot, of course,
be programmed to a digit greater than 5.
Function 7
In function 7 counter 1 is displayed with "0000" at
power-on. If S3 is in the Function 6 - T position at
power-on, it must be placed in the "OFF" position;
then Sll must be momentarily closed. Counter 1 is
set to a specific count by holding each of the four Digit
Programming Switches closed in turn; then the
Comparator must be enabled by placing S3 in the
Function 6 - 7 position.
Counter 1 counts down from the set count beginning
with a Start/Stop transition. When counter 1 counts
down to zero the clock pulses to counter 1 are inhibited
and the Comparator Output is enabled. This is not
repeatable without a new count being entered into
counter 1. A Final Event transition halts the counter 1
down-count, and subsequent Start/Stop transitions have
no effect on counter 1 or counter 2. A Reset transition
resets counter 1 to "0000."
Peripheral
The other components shown in Figure 4 consist of
input/output interfaces between the user and the
MM5865. The crystal used in this stopwatch!timer
circuit is a watch crystal cut to oscillate at 32.768kHz.
(A 32.8kHz crystal would be best.) This means that the
blanking frequency is 799.2 Hz, the multiplex frequency
is 399.6 Hz, and the clock frequency to the counters is
0.99902Hz.

Practical Applications of the
StopwatchlTimer
Now that the basic operation of the MM5865 has been
presented, it is possible to examine practical applications
of the seven function universal timer shown in Figure 4.
This timer, as shown, has a maximum timing capability
of 99 minutes, 59 seconds. If another MM5865 is added
to the circuit, this timing capability may be extended to
99 hours, 59 minutes, 99.99 seconds. For very accurate
timing, the crystal should be cut to oscillate at 32.8 kHz,
and the oscillator frequency should be precisely tuned
to 32.8 kHz.
When the stopwatch!timer is being used to time any
event, the display should be disabled with S2 as much
as possible so that battery power will be conserved.
Function 1 may be used to time two events occurring
simultaneously in the following manner. A driver often
. travels from I-is home to a city some hours away. On the
way he passes a small town about halfway between his
home and the city. He. wishes to know how long it takes
him to travel from his home to the small town, how long
it takes to travel from the to;"'n to the city, and finally,
how long it takes him to travel from his home to the
city.
At the beginning of the trip the driver presses the Start/
Stop switch. The display begins to record the time
accumulating in counter 2. As he passes through the
small town he presses the Start/Stop switch again and
records the traveling time from his home to the town.
Then he presses the Start/Stop switch again. As he
arrives at the city he presses the Final Event Stop switch
and records the time shown in the display as being the
traveling time from the town to the city. He then
presses the Start/Stop switch and' sees in the display the
traveling time from his home to the city.

The oscillator frequency may be adjusted by connecting
a counter to 'pin 20 of the MM5865 through a 50pF
capacitor and then varying the capacitance of C3. Any
attempt to alter the values of R 1, C2, or C3 will probably
fail; that is, the oscillator will probably not oscillate.
Most of the switches which control the MM5865 are
momentary push-buttons which are available from many
sources. The function switch, however, is a very small
8-position switch in a TO-5 package; it is available from
James Electronics, P.O. Box 822, Belmont, CA 94002.

Function 2 may be used to record the total accumulated
time of several events while each event is being timed
individually. For example, a television repairman spends
his day ordering parts, talking to customers, and repairing televisions on the bench. He wants to record the time
he spends repairing each set so that customers may be
properly billed, and he wishes to record his total bench
time for the day.

The 2N4400 (a 2N3904 can also be used) drives the
decimal point anode of the display and is itself driven
by the Waiting State output of the MM5865.
The MM14511 provides the functions of a 4-bit storage
latch, an 8421 BCD-to-seven segment decoder, and an

6-25

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Figure 6. The MM5865 used in a simple counting circuit.

simply presses the Start/Stop switch to turn on the
enlarger for the desired length of time.

The 74COO in this circuit debounces the switch used as a
clock, S3. An LM555 is used to provide a multiplexer
input frequency of 233 Hz.

It is not necessary to enable the display while operating
the timer. The display must be enabled only to program
counter 1. The Reset switch may be pressed at any time
to turn off the enlarger. The enlarger may be turned on
for adjusting negatives by pressing the Start/Stop switch
without enabling the comparator.

The MM5865 is operating in function 5, and displays the
up·count of counter 2. After an initial Start/Stop transition, each closure of the manual switch advances the
displayed digits by one count. A Reset transition resets
counter 2 to "0000."

With proper interfaeing, function 7 may be used as a
down-count timer for many applications, including
cooking and washing. The desired time is simply programmed into counter 2, the comparator is e'1abled,
and then the Start/Stop switch is pressed. Counter 2 will
count down to zero and turn off the appliance.

Conclusion
The emphasis of th is presentation has been on the
general timing and programmable capabilities of the
MM5865 rather than on specific applications. Because
so many functions are available in one package, it is
possible to use the MM5865 as a general purpose chip,.
adding another MM5865 when it is necessary. In most
applications only one or several of the seven functions
need be used; however, because of its general purpose
nature, the MM5865 lends itself well to the concept of
quantity purchasing.

A few applications (some for which two MM5865s are
required) have been presented to illustrate the utility
of the MM5865. The Stopwatch/Timer discussed above
is but one general application for which the MM5865
may be used.

Figure 6 shows a simple manual counting circuit in
which the MM5865 is used to count the closures of a
manual switch. Of course, the manual clock could be
replaced by electrical pulses.

6-27

A final note: Unless the start pulse is externally synchronized to the clock (available at pin 15 of the MM5865, if
the internal oscillator is used). the amount of time which
will elapse between the arrival of the.start pulse at pin 14
of the MM5865 and the appearance of the first digit in
the display will not be equal to the programmed display
resolution. It is possible to develop a start pulse that is

synchronized .to the clock using an MM74C221 Dual
Monostable Multivibrator as shown in Figure 20. The
time constant of R1 - C1 should be equal to the display
resolution, the time constant of R2 - C2 should be less
than the programmed display resolution, and the time
constant of R3 -.C3 should be less than the time constant
of R2-C2.

VSS

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Figure 21. Start-Pulse Synchronizer. Time constant of R1-C1 =

display resolution. Time constant of' R2 - C2 < display resolution.
Tim. constant of R3 -C3 < tim. constant of R2 - C2.

6-28

A 4·0igit, 7·Function
Stop Watch/Timer

Introduction
This construction article is the second of a series which
is to concentrate on applications of the MM5865 universal timer. The first article, "MM5865 Universal
Timer Applications," presented in detail the programmable and functional characteristics of the MM5865.

4. Counter 2: Split-timing with total elapsed time
Counter 1: Not actively used
5. Counter 2: Total accumulated time
Counter 1: Total elapsed time
6. Counter 2: Up counter
Counter 1: Programmable counter

This second article illustrates the construction and use
of a 4·digit, 7·function stopwatch/timer in which the
display resolution and counter modulo may be pro·
grammed with printed circuit board jumper wires.

7. Counter 2: Programmable down counter
Counter 1 : Not actively used

Other than switches, all components of the stopwatch/
timer are mounted on a glass·epoxy or glass·polyester
board which is laminated with l·ounce copper foil on
one side. The board is mounted in the attractive instru·
ment/clock case available from James Electronics.

Operation
The switches which control the operation of the stopwatch/timer are visible on top of the case shown in the
photographs of Figures la and lb. Each switch is
indicated in the schematic drawing of Figure 2.

This instrument/clock case has provisions for the display,
precut holes for four calculator·type switches, and a
precut line cord hole. In addition, the case is sold with
a red display bezel, four rubber feet, and a flip-top to
conceal the four switches which may be assembled in
the precut holes.

In Figure la, the switch in the rear right hand corner of
the case is a 7-position rotary Function Switch (F). At
the front of the case the switches are, from left to right,
Digit 4 Programming Switch (04), Digit 3 Programming
Switch (03)' Comparator Switch (C), Digit 2 Program·
ming Switch (02), and Digit 1 Programming (01)/
Latch Control (LC) Switch. Digit 1 is the least significant
digit (LSD); Digit 4 is the most significant digit (MSD).

A display resolution of 1 second, 0.1 second, or 0.01
second may be programmed by on·board jumpers or a
suitable switch. Furthermore, the counters may be
programmed to count in modulo 6 or modulo 10.
When used as a photographic enlarger timer or as an
appliance timer, each digit is individually programmable
with one of four pushbutton switches. The comparator
output of the timer may be coupled to an enlarger/
appliance control circuit that can be permanently
mounted to the enlarger or appliance.

There are four switches under a center flip-cover. These
are shown in Figure lb. From left to right they are
Final Event Switch (FE), Reset Switch (R), Start/Stop
Switch (SS), and Automatic Reset Enable Switch (AR E),
The ARE switch is used only in function 6; it must be
OFF for all other functions. The C switch has three
positions: Comparator/Count Enable (CCE), used for
functions 6 and 7; Program Enable (PE), used for
function 7; and Count Enable (CE), used for functions
1 through 5. The D1/LC switch is a dual purpose switch;
for functions 3 and 4 it serves as the latch control switch,
and for functions 6 and 7 it serves as the Digit 1 program·
ming switch. There is no ON·OFF switch. Power is
applied to the stopwatch/timer by plugging the line cord
into a 120VAC/60 Hz outlet.

Applications for the stopwatch/timer include, but are
not limited to, the fOllowing:
•

Laboratory reaction and interval timer

•

Photographic enlarger and chemical processing timer

•

Stopwatch

•

Event timer

• Appliance timer
A simple listing of possible applications for the timer
does not adequately describe the enormous power of
the instrument. A tabulation of the seven functions
which includes a break·out of the functions performed
simultaneously by counters 1 and 2 of the MM5865 is
much more revealing, and is presented below:

Table I is a tabulation of the abbreviations used for the
switches and the functions to which they apply. If the F
switch is set to any of the stop watch functions (1
through 5) when power is initially applied to the
stopwatch/timer, the display will remain blank. See
"MM5865 Universal Timer Applications" for information
on using pin 39 as a power on indicator.

1. Counter 2: Start·stop timing
Counter 1: Total elapsed time

To operate the stopwatch/timer in any of the stopwatch
functions, rotate the. F switch to one of the stopwatch
function positions, place the ARE switch in the OFF
position, place the C switch in the CE position, and press
the R switch.

2. Counter 2: Start·stop timing
Counter 1: Total accumulated time
3. Counter 2: Sequential event timing
Counter 1: Total elapsed time

6-29

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Figure 1. External Photographs of Stopwatch/Timer. a) View of Function Switch, Comparator Switch. and Digit Programming Switches.

b) With flip-cover raised. four additional switches are seen. The flip-cover is designed so that a press of the closed cover closes the Start!
Stop Switch. c} A miniature jack is mounted at the rear of the case so that a cable may be run to the appliance control box.

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Figure 2. :Schematic Diagram of the 4·0igit, 7·Function Stopwatch/Timer. As drawn. the display resolution is 1 second. A SPST switch
may be included between pin 16 of IC2 and VSS to provide a display resolution of 0.01 second or 1 second. Another option, shown: in
the figure, is the Display Control Switch, which may be used to inhibit the display.

Table I. Switch Abbreviations

Abbreviation

Switch

Functions

ARE
C
01
02
03
04
F
FE
LC
R
SS

Automatic Reset Enable
Comparator
LSD Programming
Digit 2 Programming
' Digit 3 Programming
MSD Programming
Function
Final Event
Latch Control
Reset
Start/Stop

6
1-7
6, 7
6, 7
6, 7
6, 7
1-7
1-5
3,4
1-7
1-7

6-30

Table II. Resolution Select Code. A zero indicates that tl'\e pin
is left floating (or connected to VDD); a one indicates that the
pin is connected to VSS' Note that when an external clock is
applied to pin 15, pins 16 and 17 must be connected to VSS'

Resolution Select
Pin 16

Pin 17

0
0
1
1

0
1
0
1

made. The operation of each function is detailed in the
first article of this series.
To operate the timer in function 6, rotate the F switch
to function 6, place the C switch in the CCE position,
and press the R switch. The display will show four zeros
when the R switch is pressed.

Frequency of
Display Resolution
Clock to Counters

The count·up time is programmed into the timer by
pressing Dl through D4, one switch at a time, until the
desired count·up time appears in the display.

0.01 sec
0.1 sec
1
sec

100Hz
10Hz
1 Hz
External

-

After digit programming, place the AR E switch in the
ON position if autom.otic resetting is desired. The initial
press of the SS switch will cause the display to blank,
then to indicate the count·up to the programmed time.
During the up·count the CA3059 will be enabled,
allowing the appliance to be turned on. When the count·
up reaches the programmed time, the comparator output
will go from 0 volts to 8.4 volts. At this time the CA3059
will be inhibited, and the appliance will turn off.
Pressing the R switch any time after the digits have been
programmed causes the comparator and counter 2 to
reset. Switching the C switch to OFF causes the com·
parator output pin to go to Voo as long as 'it is OFF.
If the C switch is again placed in the CCE position
(before the R switch is pressed), the comparator output
pin will go back to Vss. Of course, any time the FE
switch is pressed the comparator output will go to Vss.

Table III. Divide Scaler Code

Modulo

Divide
Scalers

Counter 1

1

2

3

4

Digit
3
2

0
1

0
0
1
1

0
0

10
6
10
10
10
10
10
10

10
10
6
10
10
10
10
10

Pin

a
1

a a
1 a
0
1

1
1

a
a
1
1
1
1

10
10
10
6
10
10
10
10

Counter 2
1

4

Digit
2
3

10
10
10
10
10
10
10
10

10
6
10
10
10
6
10
10

10
10
6
10
10
10
6
10

10
10
10
6
10
10
10
6

1
10
10
10
10
10
10
10
10

If the ARE switch is ON, the count-up sequence may be
repeated by pressing the SS switch again. Nothing need
be changed until it is necessary to reprogram the digits.
When reprogramming is necessary, simply change the
time shown in the display to the new time, with the
ARE switch in the OFF position, using the digit programming switches. Then press the SS switch to start the upcount. If the A.RE switch is OFF, it is necessary to press
the reset before starting a new count-up.

A zero indicates that the pin is left floating (or connected to
VOO); a one indicates that the pin is connected to VSS.

Press the SS switch to initiate a sequence of timing
series. Press the SS switch again to end a serial (functions
1, 2, 3, 5) and simultaneoLisly initiate a new serial while
freezing the display (function 3), or to freeze the display
during a continuous count sequence (function 4).

To operate the timer in function 7, rotate the F switch
tofunction 7, place the ARE switch in the OFF position,
place the C switch in the PE position, and press the R
switch. The count-down time is programmed into the
timer by pressing D 1 through D4, one switch at a time,
until the desired count-down time appears in the display.
The C switch must then be placed in the CCE position.

Press the SS switch a third time to initiate a new timing
serial (functions' 1, 2, 3, 5) or to update the display
during a continuous count sequence (function 4).
Subsequent presses of the SS switch will repeat the
action described above.

Pressing the SS switch will cause counter 1 to begin its
down·count from the programmed time to "0000" and
will cause the CA3059 to be enabled, turning on the
appliance as in function 6. When counter 1 reaches
"0000" the CA3059 will be inhibited, turning the
appliance off. The down-count is displayed, and may be
halted at any time by pressing the FE switch; the downcount may not be resumed. Pressing the R switch any
time after digit programming will reset counter 1.

Press the LC switch to display a continuing, undisplayed
count (functions 3 and 4). Press the FE switch to end a
sequence. A final press of the SS switch at the end of a
sequence is required to display total elapsed time
(functions 1, 3, 5) or total accumulated time (function 2).
Subsequent presses of the SS switch after the end of a
sequence simply repeat the display of the final serial
time, then the total elapsed or total accumulated time.
The operations which may be performed in each function
are shown in the flow charts of Figures 3 through 8.
The first line of type in each PROCESS rectangle indio
cates a switch or the display upon which an action may
be performed. The seco<1d line of type indicates the
position in which the switch must be placed or the
action to be performed. The parallelograms in the flow
charts indicate points at which a DECISION must be

When using function 7, the comparator must be disabled
and the R switch must be pressed before digit programming. Then the comparator must be enabled. This is
unlike function 6"in which digit programming is allowed
at any time, regardless of the state of the comparator.
In addition, the ARE switch must not be used in
function 7.

6-31

»
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.

......

m

Figure 3. FUnctions 1 and 2. Pressing START/STOP after FINAL EVENT has been pressed gives Total Elapsed Time in Function 1.
Total Accumulated Time in Function 2.

Figure 4. Function 3. Pressing START/STOP after FINAL EVENT has been pressed gives Total Accumulated Time.

6-32

»
z
......

~

Figure 5. FUnction 4.

NO~

Figure 6. FUnction 5.

6·33

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z

Interfacing the Stopwatch/Timer
with an Appliance Circuit


The center portion of the top half of the case has been
designed for a switch assembly composed of three pushbutton switches and one slide switch_ The assembly is
made of calculator-type switches and a flex-circuit;
however, James Electronics provides neither the switches
nor the flex-circuit_

Figure 13a shows the layout of the flex-circuit; Figure
13b is a view of the flex-circuit after it has been folded
over the thin plastic insulator which is shown in Figure
13c_ The insulator must be oriented so that the circuldr

cutouts are between the .two sets of four copper hexagons_ The copper trace through each hexagon forms one
contact of a SPST switch_

(+-1'------11.6"--------+1'1

I~ ~o!o!o!

?o~oes

~

(a)

n

(b)

0' 0 0 0.[
0

0

0

(e)

(d)
Figure 13. Flex-Circuit, Assembly. a) Layout of the flex-circuit. b) Layout of the flex-circuit after it has been folded to form the
contacts' of thiee SPST momentary pushbutton -switches and one SPST slide switch. c} Thin plastic insulator which must be inserted
between the folded portions of the flex-circuit. d) Plastic cover which fits over the flex-circuit assembly to hold it in place in the top of

the case.

If the automatic reset feature for function 6 is to be
included, cut the slide switch hexagon connection to
Vss as shown in Figure 14 and cut a little square piece
from the thin insulator. This small square should be just
large enough to allow a solder connection to be made
between the trace going to the slide switch hexagon and
the trace going to the FE switch hexagon_ To solder
the traces together, pretin both traces slightly, fold the
flex-circuit as shown in Figure 13b, and apply a small
soldering iron tip to the trace going to the slide switch
hexagon at a point above the insulator cutout.

0

0
0

0

~

0

0

0

0

0

The switches should then be placed in the top of the box
in the spaces provided_ The flex-circuit is then placed
over the switches_ Finally, the plastic cover fits over the
entire assembly as shown in Figure 15_ Holding the
plastic cover firmly in place, touch a clean soldering iron
tip to each of the plastic pegs protruding through the
holes in the plastic switch assembly cover until the
assembly cover is sealed to the top of the case. Cut the
single tall plastic peg to the rear of the switch assembly
cutout ifthere is one_

0

0

0

0

0

0

0

0

0

0

0

0
0

0

0

0

0

Figure 14. Full·Size Partial Drawing of the Flex-Circuit Layout Showing the Trace which Must be Cut if the Auto Reset Option is
Desired.

6-37

Z
•
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m

Figure 15. Photograph Showing the Internal Construction of the Stopwatch/Timer. Note how flex-circuit runs from the top of the case
to the trace-side of the printed circuit board.

Drill the holes for the rotary function switch, the
comparator switch, and the four programming switches
as shown in the drilling guide of Figure 16. The drilling
guide must be modified as shown in Figure 17 if the
Centralab PS·l01 switch is used. The holes for the
rotary switch must be marked and drilled precisely.
In addition, if the Centralab PS·101 switch is used the.
filter capacitor, Cl, must lie on its side to make room
for the function switch. Mounting the top of the case to
the bottom is easier if theCentralab PS-101 switch is
used. If desired, a jack may be mounted'in the bottom
half of ,the case in the right hand rear corner, behind C1,
to provide a quick connection to an enlarger or appliance
control circuit. The fit will, be tight, but a miniature jack'
can be mounted without much difficulty. This completes
the case· preparations.

I

6-38

Before parts are mounted to the PC board, the fit of the
board to the case should be checked. It may be necessary
to adjust the mounting holes slightly with a small round
file. Try not to completely break the traces surrounding
the mounting holes. There are six mounting holes in the
PC board. These holes match six plastic pegs in the
bottom of the case. Two of the pegs are to be inserted
through the transfurrner mounting flanges if a trans·
former of. the correct size is used. If the Radio Shack,
or some other transformer which does not fit precisely,
is used, it may not be possible to fit the pegs through ~he
transformer mounting flanges.
After the IC sockets .are·mounted, the transformer imd
Cl should be mounted. If the Centralab PS·101 switch is
used, the filter capacitor should be attached t9 the board

:t>

11/64 DRlll4 HOLES

1/4 ORlll2 HOLES

z.

.....

0')

CO

1.2

0

o

00

-'='---

+- - -

0.7
0.95

i..'---------l--.------'

Lc},

~7.7_

I

5,"4 DRill

Figure 16. Drilling Guide for the Case Top if the MRC·'·10 Rotary Function Switch is Used. (Dimensions in inches.)

11/65 DRILl-

2 HOLES

o

1.2

0

0

o

=---+---1.2

I I 14-0.75
-*-87,-

I

~2.2--J

Figure 17. Drilling Guide for the Case Top if the PS-101 Rotary FUnction Switch is Used. (Dimensions in inches.)

with leads that are long enough to permit the capacitor
to lie on its side. The diameter of C1 must not be greater
than 0.7 inch and its length must not be greatSr than
1.2 inch.

Wire jumpers may be used to program the display
resolution and the modulo of the counters using the
charts shown in Tables I and II. The connections shown
in Figure 2 cause the display to read in tens of minutes,
minutes, tens of seconds, and seconds; maximum time is
99 min 59 sec. A pad which allows a connection to an
external clock is available at pin 15 of the MM5865.

The display mounting pins should be soldered to the
display before the display is mounted to the board. Be
careful not to lift the display pin pads when soldering.

After all components have been mounted and all wire
connections have been made, proceed to the preliminary
checkout and adjustments section before applying
power to the board.

Wires must be soldered to the board and connected to
the switches mounted to the top of the case. Refer to
the wiring diagram shown in Figure 18.

6-39

m
,....
z

-d:

After oscillation has been confirmed the display should
be examined for segment and digit defects. If any
segment or digit does not appear in the display (The g
segment does not appear when the display reads all
zeroes.), the board and the display mounting pin connections must be checked.

. . . - - - - - - - - - - - - - - -. . PIN 39

r--'--;:==========J---'"

PIN 38

...------+-~ PIN 35

.-------1---+ PIN 37
PIN 36

When handling the stopwatch/timer before it is mounted
in its case, extreme care must be used to not break the
connections between the flex·circuit and the printed
circuit board. However, these connections need not be
made until the oscillator and display have been checked
out.

L.......:..------f--f--.. PIN 4
...---+--+--'" PIN 6
r.--f--+--" PIN 5

After the oscillator and display checkout, the frequency
of the oscillator should be adjusted to the crystal fre·
quency using C3. Then the board may be placed in the
bottom of the case. Tbe balance of the preliminary
checkout consists of stepping through the operational
flow diagrams in Figures 3-8; a VOM should be con·
nected to the output jack during the functions 6 and 7
checkout. If any of the switches under the flip cover
fail to respond, check to see if the flex·circuit is broken
at the point where it connects to the board.

V*~"""I--. vss

'-.....,1--.

'----+--1.

L..--------1Hit:===:..--+

PIN 11
PIN 10
PIN 9

' - - - - - - -... PIN 8

'---------+ PIN 7
Figure 18. Wiring Diagram for the Switches Mounted in the Case

Final Assembly and Checkout

Top.

The board may be fastened to the bottom of the case by
forcing #6 tinnerman nuts over the plastic pegs which
appear through the holes indicated in Figure 11. This
!"(lay be done easily with a 5/16·inch nutdriver. Then
force. the line cord in the cutout provided.

Preliminary Checkout and Adjustments
The following tests and adjustments should be carefully
completed before power is appl ied to the stopwatch/
timer or the appliance control circuit.

The top of the case may then be carefully fitted to the
bottom, with the red plastic filter partially in place.

Rotate the F switch to function 7, place the AR E switch
in the OFF position, place the C switch in the CCE
position, and disconnect the tape recorder plug from the
jack at the rear of the stopwatchltimer case. Adjust R 1
for minimum resistance. Do not connect any appliance
to the appliance control circuit, but do place a fuse in
the fuse holder.

A slot in each half of the case retains the filter when the
case halves are fastened. If the M RC-l-l 0 switch is used,
the fit will be tight because of its proximity to Cl. The
cutout for the line cord in the top half of the case must
be forced over the line cord.
Once the two halves are fitted properly, fasten them
together using the four screws provided with the case.
Install the rubber feet and proceed with the final checkout.

Measure the following points for the indicated amount
of resistance:
1. Across the stopwatch/timer line cord plug> 50 ohms
2. Across Cl, with VOM on Xl K scale and common
probe to VDO, > 5k ohms, after C 1 charges

The final checkout is a repetition of the operational
checks using the flow diagrams. Each option at each
decision point in every flow diagram should be exercised.

3. Across R 1 < 15 ohms
4. Across C2 > 100 ohms

Resolution and Accuracy

5. Across the appliance control circuit line plug> 10k
ohms

If a crystal is used for the time base of the stopwatch/
timer, the accuracy of the displayed count will, of
course, depend upon the particular crystal used. In
addition, because the MM5865 begins to count on the
leading edge of the start/stop pulse, the width of this
pulse becomes important when the event time is very
short.

If these values of resistance cannot be found at the
points indicated, check the PC boards for opens or shorts
as necessary. Then, with a VOM connected across C2,
apply power- to the stopwatch/timer; the VOM should
read slightly more than 1 volt. Increase the resistance of
R 1 until the VOM reads 8.4·volts. Slightly under 8.4 volts
is better ~han slightly over. Pressing the reset switch
should cause "0000" to appear on the display, unless the
display already reads "0.000."

For example, When coupling the timer to an appliance,
if the width of the start/stop pulse is longer than the
event time, the appliance will not turn off at the end of
the programmed time.

If the display is blank or indicates only one or two
zeroes, the oscillator is probably not oscillating .. Rotate
C3, 360 degrees if necessary, while observing the display.
If the display still fails to respond properly, ch.eck the
voltage at pin 20. of the MM5865; it isvery close to 6
volts when the oscillator is functioning.

This is why C5 and R4 have been included. Together
they insure that the start/stop pulse will not be longer
than 0.01 second. This' purse width should be adequate
for most users. C5 and R4 may be omitted ifthe length

6-40

»
z

of time the start/stop switch is to be held closed will
always be less than any timed event. When C5 and R4
are om itted, the 55 switch simply connects to V55.

will elapse between the arriv.al ofthe start pulse· at pin 14
of the MM5865 and the appearance of the first digit in
the display will not be equal to the programmed display
resolution. It is possible to develop a start pulse that is
synchronized to the clock using an MM74C221 Dual
Monostable Multivibrator as shown in Figure 20. The
time constant of R 1 - Cl shOUld be equal to the display
resolution, the time constant of R2 - C2 should be less
than the programmed display resolution, and the time
constant of R3 - C3 should be less than the time constant
of R2 - C2.

As to crystal accuracy, the stopwatch/timer will lose
0.001 sec/sec if a 32.768kHz crystal is used instead of a
32.8kHz crystal. This should be insignificant for most
users.

Also, the display resolutions which may be programmed
by on board jumper wires will be adequate for most
users. Figure 2 illustrates the connections to the MM5865
which will cause the display to read in tens of minutes,
minutes, tens of seconds, and seconds.

Vss

When it becomes desirable to achieve a display resolution
which allows the timing of events that are hours in
length, it is necessary to provide the MM5865 with an
external time base. This may be done by cascading two
MM5865s or by using a simple timing circuit built around
an LM555 timer or a digital clock. Figure 19 shows how
an MM5315 digital clock may be used as a time base for
the MM5865. The MM5315 itself uses the line frequency
as a time base. The MM5315 is shown as it would be
connected for a 60 Hz line frequency.

TO
PIN 14
OF
MM5865

R2
&2

FROM
PIN 15
OF
MM5865

When an external time base is provided for the MM5865
in this manner, an external multiplexer must also be
provided. The oscillator formed with the 74C14 supplies
the desired multiplex frequency as shown in Figure 19.

RI
&1

voo

A final note: Unless the start pulse is externally synchro·
nized to the clock (available at pin 15 of the MM5865, if
the internal oscillator is used), the amount of time which

Figure 20. Start-Pulse Synchronizer. Time constant of R1 -C1 =

< display resolution.
< time constant of R2 - C2.

display resolution. Time constant of R2 - C2

Time constant of R3 - C3

r---------__------- AC
~-----.--------------------i------1~-----1~-VSS

r--------------+---t--+-----------------,--;r-~--;_--~--;_--VDD

R2

R3

D2
C2

14

19

20

~

21

DI
TO PIN 23 OF
IC2
21

RI
R2
R3
CI
C2·C4
01
D2

20kH. %W, 5% RESISTOR

220kn. ~W. 5% RESISTOR
1DOk!Z, %W. 5% RESISTOR

O.I"F CAPACITOR
o.OI"F CAPACITOR
IN4002 DIODE
B.2V ZENER DIODE

Figure 19. Using an MM5315 Digital Clock and an External Multiplexer to Provide an External Time Base for the MM5865 to Generate

a Display Resolution of 1 Minute.

6-41

•
......

0')

CO

m
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Z

«

PARTS LIST
Rl
R2
R3
R4
R5
R6
R7
R8
Cl
C2
C3
C4
C5
C6
C7
Dl, D2
Tl
ICl
IC2
IC3
1C4
IC5
IC6
IC7

5kn trimpot
240.11, Y..W, 5% resistor
20Mn, Y..W, 5% resistor
1 Mn, Y..W, 5% resistor
100kn, Y..W, 5% resistor
5.1 kn,Y..W, 5% resistor
4.7kn, Y..W, 5% resistor
10kn, 1W, 5'1!> resisto~
470 - 1000 m F, 25 V capacitor
10mF, 25WVoc solid tantalum capacitor
6 - 25pF variable capacitor. Sprague QT1-18
4 - 30pF may be used.
25 - 27pF, disc ceramic capacitor
O.OlmF disc ceramic capacitor
100mF, 25WVoc capacitor
0.05mF, 200WVoc capacitor
IN4003
10 -16.5V AC@ 300mA transformer
LM317T voltage regulator
MM5865 universal timer
CD14511 decoder/driver/latch
DS8877 or DS75492 digit driver
RA07 - 150 resistor array
74C02 quad 2-input NOR gate
CA3059 zero voltage switch

, NSB5411

HEP Rl723
1 A fast or normal ,blow fuse
32.8 kHz crystal (32.768kHz can be substi.
tuted. Timer will lose about 35 sec in 11 hr
20 min of use.)
Sl, S3, S5 SPST, NO, momentary pushbutton switches;
part of flex-circuit switch assembly.
SPST slide switch; part of flex-circuit switch
S2
assembly.
S4
DPDT, center OFF toggle switch
S6-S9
SPST, NO, momentary pushbutton switches
7 - 12 position rotary switch- Centralab
SlO
PS-101 or Alcoswitch MRC-l-10.
SPST toggle switch
Sll
SPDT toggle switch (oPtional)
S12
Display
National Semiconductor NS85411 4-digit
multiplexed display.
Heat Sink TO-220 heat sink. Two needed.
16 display mounting pins (strip of 16 pins);
Misc.
1 case; Clock/Instrument (available from
James Electronics); 1 flex-circuit; 1 flexcircuit insulator; 2 Tinnerman nuts, #6;
fuseholder; appliance control box, #LMB
C.R.-234; 115V Ai: chassis mounting socket;
miniature jacks; phone cable (shielded); IC
sockets.
Triac
Fl
XTAL

HULL D1GITS

II"'~- - ' - - - - - - - 3,OO"~------.t~1

RED FACE PLATE

SIDE V,IEW
PIN CONNECTIONS
ANODE G -PIN 1
ANODE F -PIN 2
ANDOE E -PIN 3
ANOOE 0 -PIN 4
ANODE A -PIN 5
ANODE C-PIN 6
ANODE B -PIN 7
ANODE AM/PM INDICATOR -PIN 8

PIN 16PIN 15PIN 14PIN 13PIN 12PIN 11PIN 10PIN 9-

ANODE COLON TOP
CATHDDE,5
CATHODE 4
CATHDOE 2 AND 3
CATHODE 1 AND AMIPM
LIGHT SENSOR
LIGHT SENSOR
ANODE COLON BOTTOM
SEGMENT
DESIGNATION

6-42

Programmable TV Timerl
Time-Channel Display

This application note describes an on screen TV real
time and channel display based on the MM53107,
MM53100 and MM5840 MaS/LSI integrated circuits.

As the MM53100 and MM5840 are situated on different
VSS levels, 4 pull·down resistors R2-R5 are required to
provide the display IC with the necessary full swing
from OV to 12V at its BCD inputs. The digital select
inputs at the MM53100, Ox (pin 24). Dy (pin 23). and
D z (pin 22) are directly driven by the display IC. The
code for each displayed digit is shown in the table
below:

The sample was assembled in a small (15 x 6 x 8 cm)
box, connected to the TV chassis with 10 wires. A
Grundig portable black and white Triumph set was used.
The highlight features of the clock are:
•
•
"
•
•
•

8, or optionally 5·digit time display
Channel number display and remote channel select
Programmable TV ON timer
Choice of ON durations, and safety turn·OFF
Remote manual TV ON and OFF
Display option with or without frame

•

Low power consumption

•

Battery back up for power failure or OFF TV mode

DIGIT
SELECT
LINES

S1

S10

x

M1

M10

x

H1

H10

Ox
Dy
Dz

1
1
0

0
1
0

0
0
0

1
0
0

1
0
1

0
0
1

0
1
1

1
1
1

DIGIT DISPLAYED

g

en

BASIC DESCRIPTION

-

"C

The time base for the on screen clock is a pulse generator,
consisting of a 2.097152 MHz crystal and an MM53107
divide·by·34952 oscillator/divider which delivers a buff·
ered 60 Hz pulse. A CMOS inverter/amplifier is provided
between the oscillator in (pin 5) and osci Ilator out
(pin 6) terminals. The 20 MQ resistor R 1 is required, to
bias the inverter for Class A amplifier operation. Capac·
itors C1 and CT1 provide the parallel load capacitance
needed for precise tuning of the quartz crystal (Figure 1).

TIME SETTING
To set real time as well as TV ON time, 3 inputs are
assigned: pin 17 for SET MINUTES, pin 18 for SET
HOURS, and pin 19 for HOLD. Internal pull·down
resistors provide logical zeros on all pins, which in turn
force normal timekeeping function of the clock. Switch·
ing anyone of these inputs (one at a time) to logical "1"
by means of the pushbuttons B 1, B2 or B3 results in the
desired time·setting function. SET HOU RS advances
hours information at 1 hour per second and SET
MINUTES advances minutes information at 1 minute per
second, without carryover into the hours counter. SET
MINUTES also resets the seconds counter to all ~O's.
Logical "1" at the HOLD input stops the clock (pulses)
to the minutes counter and resets the seconds counter.
Activating SET MINUTES and SET HOU RS simulta·
neously resets the displayed counters to all D's (Midnight).

The 60 Hz pulse frequency enters the MM53100 at pin
20. An internal prescaler divides by 60 to obtain seconds
of time of day. (The MM53100 will also accept 50 Hz
input at pin 20 by utilizing pin 21 50/60 Hz select pin.)
In the present application this pin 21 input must be a
logical "1" in order to divide the 60 Hz output from the
MM53107 to 1 Hz. An internal pull·down resistor is
common to pin 21 .and when left unconnected the
prescale divider pin 20 is programmed to divide 50 Hz
to 1 Hz.
Should one decide to utilize 50 or 60 Hz AC input di,
rectly from the AC power line in place of the MM53107
oscillator/divider, a simple RC filter should be used at
pin 20 to remove possible line voltage transients that
could cause the clock circuit MM53100 to gain time or
otherwise be damaged. The input on pin 20 should
swing between VDD and VSS.

In addition to its function as a clock, the MM53100
functions as an alarm clock. It is possible to preset a
time at which, when it coincides with real time, the
device will activate certain outputs. This is done by
switching the display control input, pin 16 with S4.
When taken to logical "1 ", real time is disabled from the
display. It is now possible to set an alarm time (displayed
on the screen) at which the TV will be automatically
switched ON. This TV ON time setting is controlled by
SET HOURS and SET MINUTES switches. The display
control input has internal pull·down resistors to VSS.
When taken to logical "0" or in open circuit condition,
real time is displayed and the SET HOU RS and SET
MINUTES inputs operate the real time counters.

MM53100, MM5840 INTERCONNECTION
(Also see Figure 1)
On the MM53100, pins 2, 3, 4 and 5 are the clock real
time outputs. The format is an inverted multiplexed
BCD·code and goes directly to the display IC MM5840.

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6-44

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WHITE FRAME
BLAe K 1.0
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DURATION OF TV ON TIME

input (pin 15) is brought to logical "1" (pushbutton B5
of Figure 1). The manual ON input as well as the
manual OFF input are provided with internal pull-down
resistors to VSS.

It is possible to determine the TV ON duration with
connections to the period select inputs X (pin11) and Y
(pin 12). The inputs are either permanently wired or
connected to a 2-pole, 4-way switch (S5 on Figure 1)
according to the following table:
Period Select Inputs

INDICATORS
The MM53100 has 2 indicator outputs, pins 9 and 10,
and are "Auto" ON and "View Period" indicators
respectively. "Auto" ON indicates that the TV is ON in
an automatic mode and is receptive to the alarm enable
and dis"ble programming modes.

View Period Programmed

X
0
0

y

0

5 Mins

L

1
1

a

10 Mins
20 Mins

1

30 Mins

The "View Period" indicator provides a 1 Hz output
during the ON time suitable for driving an ON or OFF
screen indicator. Both pins are normally a logical "1"
until the TV is switched ON in the automatic mode. Pin
10 stays on logical "0" for the duration of the automatically affected ON time while pin 9 alternates between
a logical "1" and 10gic,,1 "0" at a 1 Hz rate.

Internal pull-down resistors at the Period Select inputs
make it unnecessary to wire both VSS and VDD on the
switch S5_
ALARM ENABLE

In this application 2 LEOs driven by transistors 02 and
03 indicate that the TV is in the automatic mode and
that the set would be turned OFF after 5, 10, 20 or 30
minutes if there is no manual ON signal. (B4 on Figure
1)- If this were the case, pins 9 and 10 will go back to
logical "1 ". Resistors R7 and R8, as well "5 R6 for the
relay circuit, limit the base currents while R9 and R 10
provide for equal light intensity of the LEDs_ Pin 9 with
its switching 'transistor may also be used to make the
TV display flash at a 1 Hz rate as an indicator that the
set is in an "On Time Viewing Period"_ This is accomplished by means of 02 and a quad NAND gate
MM74COO. A 4 MHz oscillator is switched ON or OFF
at pin 1 (Figure 2).

Should the user decide against viewing the TV program
originally desired and had consequently programmed to
start via the alarm program enable, it is possible to
disable the alarm enable by placing a logical "1" on pin
7 of the MM53100 (S6 of Figure 1)_ Pin 7 has an internal
pull-down resistor to VSS keeping the input to logical
"0" thus enabling the TV alarm enable or turn-ON
time_
TVON OUTPUT
Pin 8 of the MM53100 provides the ON/OFF signal to
the TV chassis_ If pin 8 is in a logical "1" state the TV
is in a standby-OFF mode. There are 2 possible ways
this output can be taken to logical "0" to switch the TV
to ON.

STANDBY

If the alarm enable is ON (logical "0") and real time
coincides with the programmed ON time

The standby control input, pin 6, has an internal resistor
to VSS. Its function is to sense when the line generated
12V supply within the TV is turned OFF by the powerswitch SO and in turn disables the LED and relayoutput (pins 8, 9, and 10). This input prevents the
batteries from being drained by the base-current of
transistors 1 through 3, in case the manual ON switch is
accidently pushed while the TV set is disconnected from
the power AC line.

Or if pin 14 (manual ON input) is taken to logical "0"
(B4 on Figure 1).
Either of the above conditions will switch transistor Q1
and its corresponding relay. The TV ON output will be
"t 10gic~1 "1" and the relay will open if either the
programmed view period is over or the manual OFF

Voo -4.5V

MM53100
R7

FIGURE 2_ TV-Display "Flasher"

6-45

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in action only in the standby position. All the other TV
devices are interrupted by Sl of the relay. The D·C
power at the load capacitor, which varies from 15V
when the TV is ON to 22V in standby, is regulated by
means of an LM340·12 to a constant 12V for the clock
supply. As the TVis OFF (in standby) it is only necessary
to run the clock IC and 2 MHz oscillator/divider which
are the circuits responsible for real timekeeping. Channel
display and channel select, 4 MHz oscillator, display IC

MM5840, channel number decoder MM74C42, BCD
channel switch and the switching transistors (with the
exception of 01) can all be turned OFF. The VSS of all
these devices is interrupted from the TV's ground by
means of S2, operated in parallel with Sl by the relay.
As it can be seen, only 3 main circuits are closed in
standby: the voltage regulator circuit, the circuit of 01
which switches the coil of the relay, and the charging
circuit for the batteries (Figure 6).

12V

116

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FIGURE 7. Voltage Regulator

The voltage regulator circuit provides a constant 12V
with the set in standby or in ON position. A simpler
method also provides the necessary 12V (Figure 7).

The small amount of current of about 2 mA, 'plus the 3V
on the inputs of the ICs is of no real consequence as they
are controlled by the voltage regulator and TV power
supply, except that the 3V may cause the MM74COO to
oscillate and drain more battery current. Whether it
oscillates in this state is a matter of chance depending
on the logical state of the oscillator inhibit output when
the VSSis interrupted by S2. If the 2 mA can be
tolerated a 4.7k pull-down resistor R30 at the oscillator
inhibit output will keep the MM74COO from oscillating.
Otherwise diodes can be added to all signal lines to the
TV circuitry. The leaking circuit is generally interrupted
without affecting the normal signal path_

A zener diode alone would not be suitable. The total
supply current of the clock system will rise to about
80-100 mA when the TV switches ON in the automatic
mode of operation because 02 and 03 will switch,
powering the LEDs. To guarantee a clean switching of
the relay without a drop down of the positive voltage,
this circuit needs a quiescent current to' run through the
zener diode during standby. This current is only about
8 mA using the LM340T12.
With 01 constantly connected to 12V, the necessary
3 mA is guaranteed for switching the relay. D24 elimi·
nates voltage peaks at the moment of switching. I.n
standby, the current through this circuit is O.

The total quiescent current during standby consists of
10 mA, 8 mA voltage regulator current and 2 mA
battery charging current. C7 across the input of the
LM340T12 is important, to avoid oscillation caused by
the long wire from stray capacitance within the TV to
the voltage regulator.

This arrangement insures that the batteries are always
fully charged to run the MM53107 and MM53100 totally
and independently from the AC power line in case the
TV is switched OFF by the power switch. The quies·
cent current of the"" MM531()7 and MM53100 is about
170 !lA. This current will rise to 0.6 mA from the bat·
teryif the manual ON switch is set, because the
MM53100 provides a base current of about 0.4 mA
to 01.

CLOCK ACCURACY
How precise should the 60 Hz pulse frequency (adjusted
with Cl) be in order to guarantee the usual accuracy
in consumer clock devices of less than 1 minute per
year? The measurable reference is the buffered 60 Hz
divider output at pin 1. A direct measurement of the
HFoscillator, say at pin 5 or 6, would influence the
frequency by the inevitable load capacitance of the
frequency counter employed for this measurement.

Dl prevents the batteries from being drained by
components going from 12V to ground. This is true for
the BCD switch together with the 4 pull·down resistors,
'. or the mode and digital select switch with its correspond·
ing pull·down resistors. After switching the TV from
OFF to standby position, the voltage between VDD and
the switched OFF VSS will not be zero, but approxi·
mately 3V depending on the position of the BCD switch
and how many VDD switch~s with pull·down resistors
are closed (Figure 1).

A separate high frequency buffered output was not
made available in the MM53107 because of the increased
battery drain that would result. A coupling loop over
the crystal could be used to pick up the frequency. A
deviation of +1 minute per year means a deviation of
+3600 pulses at pin 1. More than 1,892,160,000 (60 x
60 x 60 x 24 x 365 = 1.89216 x 109 pulses per year),
the number of pulses with a 60 Hz frequency. As a

6-50

frequency counter down to 60 Hz is not available everywhere, it is more reasonable to measure the period of
60 Hz, which is 16,6666 ms_

continuous use. With a typical ON-time of only 3 or 4
hours per day, the error due to temperature would only
be about half a minute per year.
THE MM53100 OFF-SCREEN CLOCK

The flexibility of the programmable TV timer really
becomes clear in Figure 9 where it is shown in a LED
display application. The MM5840 display circuit in
Figure 1 is traded with a OS8664 decoder driver. Two
additional standard low cost CMOS ICs convert the
clock from ON screen to OFF screen LED, maintaining
all timer features as previously described.

The pulse frequency is still dependent on 2 parameters:
the supply voltage of the MM53107 and ambient temperature_ The deviation of the clock in terms of minutes
per year versus VBatt is shown in Figure 8_

The OS8664 is in this approach the workhorse_ The
internal oscillator, tuned for high frequency (130 kHz)
with low cost small capacitors, is fed to the MM74C90
counter. This counter terminates the count at Code 8,
and is used to step the X, Y, Z input of the timer chip,
also driving the decoder port of the OS8664. The digit
drive capability of the IC can easily handle the peak
current of 350 mA for a 0.8 inch display. The interdigit
blanking is taken care of by adding the clock to pin 6
(this avoids any ghost effect!.

It is to be seen that with a higher battery voltage, e.g.
4.5V, the deviation of the clock per V ~ 0.5V is almost
half the deviation at lower voltage operation.
The influence of temperature falls within a similar range.
The average value, when the whole clock device was
heated from 22°C up to 50°C, showed a typical period
shifting of +0.0001 ms. This represents about 3 minutes
of deviation per year, assuming that the clock was
adjusted at 22°C and that the TV reached a maximum
temperature of .50°C. It is also assumed that the TV
remains in constant operation.

The multiplexed BCD clock information is inverted and
7-segment encoded by MM74C04 and MM74C48.
All .Ievel Shifting between the battery operated and the
power supply 12V driven parts of the circuit is taken
care of by resistors.

This error can be greatly reduced however, if the
calculation is based upon the fact that the TV is not in

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The period has to be adjusted to values between
16,66664 ms (60,00009 Hz), or 1_892162700 pulses per
year, and 16,66669 ms (59,99991 Hz): 1,892,150,700
pulses per year. In the first case the clock will be 0_75
minute in advance of real time, in the second case it will
be 0_83 minute late per year. With a capacity range of
5-36 pF for C1 it is not too difficult to achieve this
result_

5.0

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6

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B 10 12 14

MINUTES PER YEAR (MINUTES)

FIGURE 8_ Drift vs VBATTERY

6-51

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MM54240 Asynchronous
Receiver/Transmitter Remote
Controller Applications

National Semiconductor
Application Note 249
J. Hong
May 1980

Introduction
The MM5420 Asynchronous ReceiverlTransmitter Remote
Controller is a low cost, easy·to·use circuit for serial data
transmission applications. The circuit is fabricated in
the N·channel metal gate process which gives It a wide
supply voltage range (VDD = 4.75V-11.50V) and TTL com·
patibility.
A typical application would consist of an information
handling center and up to 128 information gathering and
information supplying stations. The information handling
center would be composed of one MM54240 circuit interfaced to a microprocessor I/O system. The MM54240 in
this instance is called the "master" circuit. An infor·
mation gathering and supplying station would be one
MM54240 interfaced to a A·to·D converter/D·to·A converter system or a digital peripheral system or any informa·
tion source/destination. The MM54240 in this instance
is the "slave" circuit.
The simplest way to interface such a system is by means
of a twisted pair or a coaxial cable. A pull·up resistor is
necessary on this communication line since the circuit
drivers are open drain outputs. Care should be tallen to
reduce capacitance and resistance on this line. With the
use of pulse width modulation techniques, frequency

tolerance between the circuits is broadened. This
feature is extremely desirable since the need for an ex·
pensive crystal controlled oscillator or ceramic resonator
is eliminated. Furthermore, critical timing schemes with
start and stop bits are not used. In addition, a debounce
circuit is incorporated which contributes greatly to the
noise immunity feature of the circuit.

Circuit Description
A functional block diagram of the MM54240 is shown in
Figure 2. The Control Logic section consists of the
switching functions of the circuit. The PWM encoder/de·
coder encodes and decodes the pulse width modulation
data format. The Shift Registers store and shift the data.

Temperature Control and Security
Application
The MM54240 can be used in many different types of low
to medium speed processor controlled applications. For
a system with 128 "slave" Circuits, the time that it takes
to interrogate all "slave" circuits can range from 1 to 2.5
seconds depending on the oscillator frequency of each
individual circuit.

V+
DATA BUS
ADDRESS BUS

7

MICROPROCESSOR

CS
R
W
S

t

#1
MM54240
"SLAVE"

ADC/DAC
SYSTEM
#2

MM54240
"MASTER"

MM54240
"SLAVE"
III

•

..

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Figure 1. Typical System Block Diagram

6-53

UP TO 128

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The following example illustrates a possible in-the
home use of such a system. A set of MM54240 circuits
are used for controlling the temperature of the various
rooms inside the house, the security of the windows and
entrances, and also for turning the lights on and off when
certain events take place. The processor controlling the
system is a COP421 L and it is directly interfaced to the
MM54240 "master" circuit. Three address inputs of the
"master" circuit are not used and they are tied directly
to the power supply. A maximum of 16 "slave" circuits
are then· possible. They will start with address 112 and
go up to 127. The "master" circuit has the Data 1/0 ports
interfaced to the L 1/0 ports, the Address inputs interfaced to the D 1/0 ports, and the Control inputs interfaced
to the G output ports of the COP421 L. The Mode input is
tied to VDD to select "master" operation and the only external components are the R-C's connected to each circuit. The power supply terminals are shared between
the two circuits.

are set up for (0,1) the low impedance output port selection. D1 of the D outputs is used for furnace ignition. The
other D outputs are used for controlling the air blower's
variable speed. The second "slave" circuit has hardwired address 113 and it is used for temperature sensing
and ventilation opening control. The control (C 1, C2 ) inputs are set up for (0,0) 4 in/4 out selection. D1"D4 are
low impedance output ports for controlling the ventilator
opening; Ds-D8 are high impedance input ports for receiving temperature information from the thermocouple.
The third "slave" circuit has hard-wired address 114 and
it is used for security purposes. The control (C 1, C 2 ) inputs are set upfor (1,0) the weak pull-up option. The processor will have to initialize the output latches by loading
logic ones into them. The D6 1/0 port is for Arming and
Disarming the alarms. This is accomplished by a locking
switch shorting the 1/0 port to Vss when armed. The D1-DS
1/0 ports are connected to doors and windows. When
they are shut, the 1/0 ports are shorted to Vss. When a
window or door is opened, the voltage level of that 1/0
port will increase. When the COP421 L processor detects
this change, it will enable the alarm at the D8 1/0 port
and turn the light on at the D7 1/0 port. The processor
can also be programmed to turn the light - D7 1/0 port
- on when one or certain doors are open.

The heating system of the house consists of a furnace
with a multi-speed air blower. A thermocouple thermometer installed in each room supplies the temperature
information to the processor. The amount of air flowing
into a room is controlled by a variable ventilation
grating. When the temperature of the room falls, the
ventilator opens further to let in increasing amounts of
warm air. When all the rooms are sufficiently heated,
the furnace is turned off. The temperature in different
rooms may not be the same since the processor can
control and adjust them to a programmed setting.

The second and third "slave" circuit configurations can
be duplicated for other rooms. Each "slave" circuit has
an optional clear switch in case the processor circuit
fails and the "slave" circuit outputs have to be over·
ridden.

The first "slave" circuit has hard-wired address 112 and
it is used for furnace control. The control (C 1, C2) inputs

ADDRESS INPUT

CLOCK
GENERATOR

DATA 1/0

PWM
ENCOOERI
DECODER

CONTROL
LOGIC

t
Figure 2. Circuit Functional Block Diagram

6-54

CONTROL
INPUTS

"SLAVE"
(ADDRESS: 112)

I~+

V+l..

~

FURNACE

TTl I

A1 A2Aa f4A5A6A7
HVnn
FURNACE

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Ln-L7~

MM54240

COAXIAL
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I

ISERIAL

"MASTER"

4

On-D3~IA1-A4

02

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03
04
05
06
07

FAN
SPEED
CONTROL

OSC

C1l

"SLAVE"

I I

...
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WINDOWS/ ODORS

"SLAVE"
(ADDRESS: 114)

,gO",," " .

C1
MM54240
SERIAL
Vss

;;

ROOM

06

L--+--1[::~C2

" - - - I MODE

D·TO.A
CONVERTER

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LOCKING
SWITCH

L.J..--f-t---r IVnn
MM54240
SERIAL

FAN

08

Vss~

L
c:n
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Figure 3. Temperature Control and Security Application

. 6\7~·N"

~
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Power Line Transmission
medium. For power line transmission applications, an
interfacing circuit is used to modulate the information
on the 60 Hz AC lines. For the "master" circuit, the processor must generate a signal to control the direction of
transmission of the interface circuit. For the "slave"
circuit, the chip select (CS) output is designed for this
purpose and can be used directly to control the direction
of transmission of the interface circuit.

A MM54240 system can be interfaced using other techniques. The pulse width modulated information can be
transmitted bY.carriers like Radio Frequency, infra·red
waves, 'power line transmission or any other suitable

DATAl
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PROCESSOR

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POWER LINE
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SERIA~

MM54Z40
"MASTER"

.----

~ DATA

..

Radio Frequency Transmission
A Radio Frequency transmission system can be built in
a similar structure. An 110 multiplexing circuit has to be
designed to direct the flow of the transmitted data.

XMITI
RECEIVE

+

I

Conclusion

PDWER LINE
TRANSMISSION
INTERFACE
CIRCUIT
.... DATA III.

...
PERIPHERAL

r

SERIAL

The MM54240 is a flexible, easy-to-use, and adaptable
circuit. It can be used in any application where a serial
data transmission is desired. The transmitted data is
pulse width modulated. This gives ,it desirable features
such as a low. cost oscillator, wide 'frequency tolerance,
and excellent noise immunity. Up to 129 MM54240 circuits can be used for anyone system. The circuit is fabricated in the N-channel metal gate process. Designed
with National'sMICROBUSTM structure in mind, the circuit is easily and directly interfaced to most.microprocessor systems.

...---

I - DATA

MM54Z4D
"SLAVE"

CS

I

XMIT/·
RECEIVE

+

"

II

Figure 4. Power Line Transmission Application

Figure 5. Radio Frequency Transmission Application

6-56

National Semiconductor
Application Note 250
Edwin Schoell
May 1980

Applications and Uses of
the MM5321 TV Camera
Sync Generator

1. Introduction
The MM5321 has been introduced to replace the older
MM5320 and correct some difficulties associated with that
part. It is a plug·in replacement in almost all applications.

complished using +5V and -12V as shown in Figure 1.
Note that no ground is needed for the MM5321, but it is
used as the power return for peripheral chips.

Major Differences and Improvements are:

Input Interfacing

• Horizontal reset control allows resetting to beginning or
center of horizontal line.

Since the MM5321 is a P·channel device, input switching
thresholds are with respect to the most positive (Vss)
power supply voltage. For this reason, it is important to
use the same regulators, or insure the 5V supply to the
driver chip is the same as the 5V supply to the MM5321.
Problems with poor clocking can often be traced to drive
levels not coming to within 1.5 volts of the 5V supply to
the MM5321.ln some cases, the addition of a 470Q pull·up
reSistor from Clock input to Vss will solve the problem.

• Vertical (field) index pulse with both 1.26 and 2.045 MHz
clock.
• Improved clocking characteristics.
•

Vertical interval always generated after vertical reset
pulse at pin 5.

• Vertical sync separator included.

Input clocking problems have also been found with low
duty cycle waveforms of the 2.048 MHz clock. A look at
the data sheet will reveal that a 50 percent duty cycle is
best, but 3 to 4 on/off (43%·57%) ratio is satisfactory.
This can be obtained from a properly configured divide
by seven counter from a 14.31818 MHz clock.

Power Supplies
The MM5321 is designed to operate from a total supply
voltage of 17 volts, or various combinations to supply a
total of 17 volts. Interfacing to TTL or CMOS is best ac·

-f

<

n

m

3

CD

vss

5V

~

!!d
::s

27k

(')

TTL OR
CMOS

TTL OR
CMOS

MM5321

::s

27k
2

G>

(I)

(I)

Ql

1

r

-12V

RESISTORS
NfEDED FOR
CMOS INTERFACE
- NOT USED FOR TTL

o""'I

VSS=5V-----------------------VSS=1.5V_

---

- - - - LIMIT

HI

O.5V -

LOW

---

INPUT LOGIC LEVELS

- - - - LIMIT

Figure 1. Input/Output Interfacing

»z

I\)
(J1

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Z
N



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.

C\I

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10---1

c.n
.....

I--Tn = 1.26JMHZ = aHa = 0.7941-1$

I

I

l-sERRATION-1
5T,

~A~\5H

FRONT PORCH_I
2TB ';l: 0.025H

r-I-------------------------I _ _ I_EQUALIZATION GATE
3 iB ';l: 0.0375H

Ur------

1

--------c1c----;1

I-HORIZONTAL-I

-----;1

5TB~yoNg75H

Ii---------------------

Ii-----'--I- - -

_HORIZONTAL ORIVE_I_ BACK PORCH_I
SiB =O.lH
6iB ~ 0.075H

I

----~

_HoRIZONTAL BLANKING_
14TB=0.175H

r--------------------

COLOR BURST GATE
I- I
3TB~0.0375H

------1U

Figure 4. Horizontal Timing Diagram with the Input
Clock Equal to 1.260MHz

"~I

1
1-3i-:-KkHz
=6°.03175 sec

18~2

------1

~---------------------------~~I~
1--EOUAlIZ~~DN GATE - 1 - - - - 3 H - - - - I · · - - - - 3 H - - - - I

l

I

I

1--SERRATj~N GATE-~I

----------~I

rl-

rl--------~II-

I +.--------VERTICAL DRIVE & HORIZONTAL INHIBIT --------~.I

1~

_________

9H _ _ _ _ _ _ _ _

FIELO INDEX

~rl-

--u~~~----------------------------~II- 1 1 - m~~~E~A~~o~~EfgRri~~,

Figure 5. Vertical Timing Diagram

6·63

,...
Lt)

N

Z

«

2H INPUT
FROM HORIZ """"1r--------,
DIVIDER

10 STAGE
MOOULE 525
VERTICAL
COUNTER

42·81T
SHIFT
REGISTER

OECOOING
ANO
SHORT
CYCLE
LOGIC

Figure 6. Simplified Vertical Timing Logic
Figure 6 indicates the method of generating the vertical
output functions. Decoding logic detects the 525th state
and short cycles the counter by resetting it to zero. Sim·
ultaneously, the input of the 42·bit shift register is set to
zero and the vertical blanking and equalization gates are
initiated. Six register clock periods later, the equalization
gate is terminated and the serration pulse is initiated by
the arrival of a zero state at the sixth bit of the shift reg·
ister. Similarly, the serration gate is terminated and the
equalization gate reinitiated when a zero is detected at
the 12th tap and, finally, the equalization gate is termin·
ated when the 18th tap changes to a zero. The vertical
drive pulse is also initiated when the register input goes
to a zero, and is terminated when the zero reaches the
18th bit. The vertical blanking pulse lasts until the zero
propagates to the 42nd bit, at which time the register
input is reset to a logical "1" level.
In some applications, particularly video recorder tape
editing, it is necessary to identify which field of the ver·
tical frame the system is in. For that purpose, the gener·
ator derives a Field Index pulse which identified field
one by occurring for two input clock periods at the lead·
ing edge of the vertical blanking pulse of field one. Field
one is defined as the field with a whole scanning line in·
terval between the equalizing pulse and the last line sync
pulse of the preceding field.
When designing MaS circuits, one must be aware of the
effects of power supply variations, ambient temperature
excursions, and process variables on circuit performance.
This is the case in design of most circuits of course, but
MaS tends to be more sensitive than bipolar circuits
due to increased parasitic capacitance and limited cur·
rent drive capabilities. The speed of any MaS product is
essentially dependent upon how fast critical capacitive
nodes can be charged and discharged. The charging or
discharging current is in turn a function of the size, the
voltages applied to, and the threshold and gain factor of
the transistor(s) supplying the current. Threshold and
gain factor are functions of process variables such as
gate oxide thickness, the type of substrate material and

its impurity concentration. They are also affected by
temperature, which reduce the fermi potential (decreas·
ing threshold), and modifies the, carrier mobility in the
transistor channel (which lowers the gain factor). the reo
duction in gain factor generally has more effect than the
change in threshold, resulting in an overall reduction in
speed with increasing temperature.
As far as the sync generator is concerned, this variation
in performance as a function of environmental and power
supply conditions could cause skewing of individual
output timing edges, reducing the accuracy of the sync
functions. Careful design essentially eliminates this
problem in the MM5321. First, all output functions were
matched for total logic delay by simulating circuit per·
formance for all environmental and process variations,
and then optimizing the delays to the output buffers.
Second, all output functions are resynchronized at the
outputs by an internal clock signal running at the input
, clock rate, with its own optimized delay characteristics
with respect to the horizontal divider clock. For all
worst·case conditions the output functions reach the
synchronizing point before the synchronizing clock.
'Third, all the output buffers themselves are identical
and therefore have matched delays. Thus, the design
results in output functions, whose timing delays are
matched with respect to each other, but will have differences in delay·with respect to the input clock on a part
to part basis (due to variations in process variables).
Even on a part'to part basis, maximum differences in
delay between two parts with the maximum allowed process variation should be less than 200ns, or O.003H, at
similar temperature and power supply values.
The output buffers are push-pull using the circ,uit configuration shown in Figure 7. The output transistors Q1
and Q2 provide the sink and source characteristics
shown in Figure 8, When interfacing directly with TTL,
the 800Q resistor serves to limit the excess sink current
supplied to the TIL clamp diode, by reducing the gate
drive to Q2. This minimizes excessive power diSSipation
on the chip and protects the TTL diode. Q8 is the logiC
trarisfer device driven by the synchronizing clock.

6-64

»z

N
c.n
......

aOOQ

------11a

SYNCHRONIZING
CLOCK .,......,

BUFFER
OUTPUT
06

~----+-----~--~
Vss

Figure 7. Schematic of TTL Compatible Push· Pull Buffer used
on All Outputs of the Sync Generator

r----.... r---..

TA=-25°~

F=:::: ~

-........:.
-..........:::

--

........... ~25°C

::::::: ~

. T-

TA=7to C
vss = 5.0V
VGG=-12.0V

o

o

5

-1

VOUT (VOLTS)

VOUT (VOLTS)

Figure Sa. Typical Output Sink Current as a Function
of Output Voltage

Figure Sb. Typical Output Source Current as a Function
of Output Voltage
VGG

INTERNAL INTERNAL
CLOCK
CLOCK

CLOCK
INPUT

Vss

Figure 9. Schematic of Input Clock Buffer

+ 5 volts connected to Vss, and -12V connected to the
VGG pin. For a tolerance of 5%· on the Vss supply, the
guaranteed trip'points decipher to a required input level
more negative than 4.75V·4.2V, or 0.55V, for the "0" level,
and a required level more positive than 4.75V·2.0V, or 2.75,
for the "1" level. These levels are obtainable from stan·
dard TTL without any external interface components.
Q10 and Q11 are feedback latches which eliminate in·
ternal clock overlap problems.

The most critical. circuitry in the generator, from the
standpoint of speed, is the input clock buffer (Figure 9).
The buffer is designed to generate a two'phase, full
power supply amplitude clock signal from the single·
phase low amplitude input signal. Q1 through Q4 con·
stitute a Schmitt trigger type input stage that guarantees
a trip·point range of Vss - 4.2V maximum for "0" levels,
and Vss - 2.0V minimum for TTL "1" levels. When
interfacing directly with TTL, the normal supplies will be

6·65

,...

Lt)

~

z

«
r--t.>C--+......I I I ' v - - 1 P - t - - - - - - - - - - - - - t I N P U T
5·BIT S.R.
Vss

VERTICAL
RESET
CONTROL

TO VERTICAL
DIVIDER
RESET
CIRCUITRY

RESET
CONTROL
LOGIC

16·BIT S.R.

t

CLOCK FROM
INPUT CLOCK
BUFFER
Vss

Figure 10. Basic Logic for Detecting. Proper State of the Composite Sync Input
Signal for Resetting the Vertical Divider In "Gen·Lock" Operation

To provide as much versatility as possible, a variety of
divider reset ("gen·clock") features have been included.
The horizontal and vertical dividers have individual Ver·
tical and Horizontal Reset inputs which allow independ·
ent resetting of the appropriate divider. With the inputs
tied together, both dividers may be reset simultaneously.

register are reset to zeros. If the composite sync signal
remains low for fifteen master clock periods, another
two-phase signal is generated which acts as the clock
for a 5-bit shift register used to store the sampled state
of the inverted (and filtered) composite sync signal. The
sample is the average value of the filtered signal during
an approximately 200ns sampling window occurring just
before the fifteenth master clock time after the composite sync input signal initially went low. The input trippoint of the 5-bit register determines whether the sampled signal is stored as a "1" or "0'.' logiC state.

The vertical divider may be reset to either of two states,
depending upon the DC level of the Reset Control pin. If
the Reset Control is tied to Vss, the m9st positive supply,
a TTL 'T' to the "0" level transition on the Vertical Reset
pin will reset the vertical divider to all zeros, which is'
time zero as defined by the vertical timing diagram. With
the Reset Control returned to VGG, a Vertical Reset
pulse will reset the vertical divider to the fifth serration
pulse (eleven 0.5H time intervals from time zero). This
allows the reset pulse to be generated by analog detec·
tion of a composite sync or video signal, and used to
gen·lock the slave sync generator within the same field
interval. The horizontal divider is always reset to zero, as
defined by the horizontal timing diagram.

Fifteen input clock periods equals time of 7.31's at an
input clock frequency of 2.04545 MHz, and 11.91's when
the input rate is 1.260MHz. The only Interval of the composite sync waveform which is legitimately low during
this time is the vertical sync pulse. In the present design,
the first five serrated intervals must be successfully detected before the vertical divider is reset to the proper
state. The limitation in this design may be the difficuity
inacutally acquiring legitimate detection due to excessive noise and missing pulses in the composite sync
input signal. If this proves to be the case, it is possible
to eliminate the second and/or fourth bits of the 5-bit
register as detection requirements. This should improve
the statistical probability of getting an initial gen-Iock
condition within a reasonable time.

The Field Index output pulse occurs once during each
field one at time zero and last for two master clock peri·
ods. It can be used to gen·lock similar sync generator
chips by connecting it to their Vertical Reset inputs and
wiring the Reset Control to the Vss supply.
Another method of resetting the vertical divider is pro·
vided by using the Reset Control pin as an input for a
composite sync signal from which gen·locking Is desired.
The slaved generator detects the fifth serration pulse.
and resets the vertical divider to the p~oper state (Figure
10).

As illustrated above, the Reset Control input has a dual
function. It selects the reset state of the vertical divider
when hardwired to either Vss or VGG, and acts as a dynamic input when gen-Iocking is to be established using a
compOSite sync input signal. When using the Reset
Control as the input for a 'composite sync. signal, the
Vertical Reset pin should be hardwired to Vss.

The reset control logiC generates a two·phase clock with
a frequency equal to the input clock rate anytime the
composite sync input signal is more negative than the
Reset Control trip-point. A 16-bit dynamic shift· register
with its input connected to Vss is driven by the modulated clock signal. When the compOSite sync input becomes more positive than the Reset Control trip-point,
or If the 16th bit becomes a "1", all sixteen bits of the

The MM5321 TV Sync Generator has been designed with
both versatility and economy as the primary objectives.
We feel it exemplifies the role of MOS/LSI standard
products can play in providing useful consumer products
in a manner that both large and small volume users will
find attractive.

6-66

lJ-

(1)3o.CC

Integrated Circuit
Combination Provides Digital
Frequency Readout with
Digital Clock for Radios
, A digital frequency readout is one feature which can easily
upgrade existing radio receivers, as well as provide the
focal point for new designs of clock radios, 3-in-1
receivers, mid-fi and high-fi products, It is even more
desirable when it can provide a full feature clock radio
function using a common display.
The M M5430 from Natio'nal Semiconductor Corporation is
a radio frequency counter integrated circuit which drives a
common anode LED direct-drive display to provide a
digital frequency presentation of the frequency to which a
radio receiver is being tuned. It is an add-on circuit; no
changes in the basic receiver circuitry are required. It may
either replace existing dial pointer frequency indicators or
be used in conjunction with them.
The companion clock IC, the MM5402N also drives a common anode LED direct-drive display, so both ICs, with few
additional components, can drive a common display.
For those existing receiver designs which already have a
digital clock, the retrofit is relatively simple. The clock and
clock display are replaced by the MM5402 and NSB584
displays. The MM5430 and a few other components are
added.
The MM5430 counter accepts an input signal from the FM
or AM local oscillator, offsets it by the IF frequency, and
displays it. Using the pin selectable options, IF offsets for

Q)(I)

0'"

C~

-(I)

:eo.
:::r ::::;.
en
-.r:::

;::;:0
10.6 MHz, 10.7 MHz or 10.8 MHz in FM and 262.5 kHz,
455 kHz or 460 kHz in AM may be chosen.
The frequency base for the counter can be derived from
the 50 Hz or60 Hz mains, or by using a commonly available
4.194 MHz crystal. If the crystal option is used, the
MM5430 provides a 60 Hz output which can be used for the
frequency input of the MM5402 clock. This allows the
clock function to have quartz crystal accuracy and allows
the system to be operated from DC sources, so the system
can be used in automobile radios.
A pin select option provides for U.S. or European channel
spacing, and LW band may be displayed in the AM mode.
When the frequency remains fixed for longer than four
seconds, the display automatically shifts to the time
display. A change in frequency (when tuning to another
station) causes the system to read the frequency
automatically.
Connection to the tuner is simple. Take-off points can be
an additional winding on the local oscillator coil or from
some hot point of the oscillator circuit. A divide-by-100
prescaler, such as the DS8629N must be used for the FM
input. Based on factors such as low LO level or oscillator
pulling, additional buffering may be required, as well as
some realignment of the frequency and tracking.

0.010

MAX

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BOTH ENDS

Package 11
16-Lead Cavity DIP (J)
NS Pa'ckage Number J16A .

Package 12
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NS Package Number J1BA

f-------~~:) MAX--------1!

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NS Package Number N14A

Package 17
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NS Package Number N08A

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18-Lead Molded DIP (N)
NS Package Number N18A

Package 19
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NS Package Number N16A

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NS Package Number N20A

8-8

Physical Dimensions

inches (millimeters) (cont'd)
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Physical Dimensions

inches (millimeters) (cont'd)

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.
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1---(15875+0.635)--1
. .~

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0.050

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(1.270).
I-- (3.302!0.1271
0.130;0.005
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0.009-0015
(D.219-D.J81(·

- 0.075·0.D15

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'0.100

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0.018:,.0.003"

--11----(o.457±D,016)

~

Package 24
40·lead Molded DIP (N)
NS Package Number N40A

8·10

-'--1_

O.12SI0.50SJ

(3.175) MIN
~
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