1980_National_Memory_Data_Book 1980 National Memory Data Book

User Manual: 1980_National_Memory_Data_Book

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MEMORY

DATABOOK

NMOS RAMs
CMOS RAMs
Bipolar RAMs
Magnetic Bubble Memories
MOS EPROMs
Bipolar PROMs
MOS ROMs
Character Generators
Memory Support Circuits
Physical Dimensions
National Semiconductor Corporation

2900SemiconductorDrive

SantaClara,California95051

Tel: (408) 737-5000

TWX:(91 0) 339-9240

National does not assume any responslbllltv for use of any circuitry described. no circuli patent licenses are implied and National reserves the right at any lime without notice to change said circuitry

President's Message

Dear Customer:
The exciting future of memory applications is limited only by
our collective abilities to make use of the continuing stream of
rapid technological advances. Annual consumption of
semiconductor memory components has already surpassed a
billion dollars per year and will soon cross the two billion
dollar level. Years ago National established the reputation as
a high volume supplier of high quality, cost-effective components forthe complete range of discretes, linears, optoelectronics, transducers, AID and DIA, hybrids, large scale integrated memory, microprocessor and logic arrays. We are
pleased to continue our expansion of this broad product line
to include the m/emories you will require in the future.
National is leading the way to higher density memories and
we are the innovators of "the system environment approach to
memory component testing". *
Our world-wide network of factory representatives, local
stocking distributors, and field applications engineers is at
your service to help meet your needs - just give any of them a
call.
We appreciate your interest in National's products and services, and look forward to supplying your present and future
. requirements.

Charles E. Sporck
President

* Relerto the following page.

2

3:3:

MST™ Program

CDtb

The System Environment Approach to
Memory Component Testing

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The Memory System Test (MST) program is designed to provide our customers with mainframe·
memory components that have already been
through the test/temperature processing that the
usernormally implements at the board level.

•
•
•
•

This program assures memory components of sig_nificantly better quality and higher reliability than
that achieved by the usual approach to memory
component testing. MST processed components
have experienced board level environmental testing
over the temperature range of 25°C "to 70°C.The
parts are tested 4 separate times with 4 different
test set-ups and 3 kinds of testers (this includes the
final QA electrical testing) which also contributes
to the increased quality.

•

The result is you get higher quality ~ t lower cost.

Present Capability
The MST process can be specified for all of the
mainframe dynamic RAMs manufactured by
National. Tooling exists for the memory components listed here at the time of this printing.

Specifying MST processing offers you the
following:
•

•
•
•

Eliminates the need for additional burn-in and
testing at independent test laboratories
Reduces board rework
Reduces field failures and equipment downtime
Provides soft error detection during component
processing
Increases reliability

. Part No.

Provides parts that have already operated in a
system environment within system margins at
maximum operating temperature
Simplifies system checkout and shortens card
burn-in/test
Eliminates inventory throughput time at incoming test or at independent test laboratories
Eliminates inventory cost and throughput time
at board test and reduces inventory cost and
throughput time at system test

MM5298
MM5290
NMC5295
NMC4164

Organization
8kx1
16kx1
16k x 1 (5V only part)
64k x 1 (5V only part)

How to specify MST
Contact your local NSC Representative or Sales
Office for a full briefing on your options.

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Table of Contents
Edge Index by Product,Family. . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .. . . . . . . . . .
President's Message.......................................................
MST™ Program The System Environment Approach to
Memory Component Testing ........................ '. . . . . . . . . . . .. . . . . . . . . . .
Alpha-Numerical Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Definition of Terms .............................. '. . . . . . . . . . . . . . . . . . . . . . . . . . .
Proposed Standard Terminology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MOS RAM Selection Guide ........................ , . . . . . . . . . . . . . . . . . . . . . . . . .
CMOS RAM Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MOS EPROM Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bipolar PROM Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MOS ROM Selection Guide ................. '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MOS RAM Cross Reference Guige. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
, CMOS RAM Cross Reference Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MOS EPROM Cross Reference Guide ........................................ , .
Bipolar PROM Cross Reference Guide ........................... : . . . . . . . . . . . . .

1
2
3
8
13
14
15
16
17
18
19
20
20
21
21

Section 1-NMOS RAMs
Static RAMs
MM2102A, MM2102AL Family 1024-Bit (1024 x 1) Static RAMs. . . . . . . . . . . . . . . . . . . ..
MM2114, MM2114L Family 4096-Bit (1024 X 4) Static RAMs. . . . . . . . . . . . . . . . . . . . . . ..
MM2147/MM2147L Family 4096 x 1 Static RAMs ...............................
MM5257, MM5257L Family 4096-Bit(4096 x 1) Static RAMs .......................
NMC2114A, NMC2114AP 4096-Bit (1024 x 4) Static RAMs ........................
N MC2141, N MC5257 A 4096-Bit (4096 x 1) Static RAMs. . . . . . . . . . . . . . . . . . . . . . . . . ..
NMC2142A, NMC2142AP 4096-Bit (1024 x 4) Static RAMs .............. " ........
NMC2148/NMC214aL 1024 x 4 Static RAM ....................................

1-3
1-6
1-10
1-15
1-20
1-24
1-28
1-32

Pseudo-Static RAMs
NMC4864 64k Pseudo-Static Byte-Wide RAM .................................. 1-35
NMC6132 32k Pseudo·Static NMOS RAM ..................................... 1-42
Dynamic RAMs
MM4280 4096-Bit (4096 x 1) ExtendedTemperature Range Dynamic RAM ...........
MM5280 4096-Bit (4096 x 1) Dynamic RAM .....................................
MM5280-5 4096-Bit (4096 x 1) Dynamic RAM ...................................
MM5290 16,384-Bit (16,384 x 1) Dynamic RAM ..................................
MM5298 8192-Bit (8192 x 1) Dynamic RAM .....................................
NMC4164 65,536-Bit (65,536 x 1) Dynamic RAM ................. _...............
NMC529516,384-Bit (16,384 x 1) Dynamic RAM .................................

1·45
1-49
1·53
1-55
1-61
1-67
1-77

Section 2-CMOS RAMs,
MM54C89/MM74C89 64-Bit (16 x 4) TRI-STATE® RAM ............................. ,
MM54C200/MM74C200 256-Bit (256 x 1) TRI-STATE® RAM. . . . . . . . . . . . . . . . . . . . . . . . ..
MM54C910/MM74C910 256-Bit (64 x 4) TRI-SJATE® RAM.... . . . . . . . . . . . . . . . . . . . . . ..
MM54C920/MM74C920, MM54C921/MM74C921 1024-Bit (256 x 4) Static RAMs ........
, MM54C929/MM74C929, MM54C930/MM74C930 1024-Bit (1024 x 1) Static RAMs .......
MM54C989/MM74C989 64-Bit (16 x 4) TRI-STATE® RAM .................. ' ..........
NMC6504 4096-Bit (4096 x 1) Static RAM ........................................
4

2-1
2-5
2-8
2-12
2-19
2-26
2-30

Table of Contents (Continued)
Section 2-CMOS RAMs
NMC6508
NMC6514
NMC6518
N MC6551
NMC6552

(Continued)

1024·Bit (1024 X 1) Static RAM ........................................
4096·Bit (1024 x 4) Static RAM ........................................
1024·Bit (1024 x 1) Static RAM ........................................
1024·Bit (256 x 4) Static RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1024·Bit (256 x 4) Static RAM ....................................... "

2·37
2·43
2·49
2·55
2·61

Section 3- Bipolar RAMs
TTL
DM7589IDM8589 64·Bit (16 x 4) RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7599IDM8599 64·Bit (16 x 4) TRI·STATE® RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

3·3
3·6

Schottky
DM85S68 16 x 4 Edge Triggered Registers .................................... 3·13
IDM29705/1DM29705A 16·Word by 4·Bit Two·Port RAM/Register File ............... 3·15

Eel
DM10414, DM10414A 256 x 1 ECl Random Access Memory ......................
DM10415, DM10415A 1024 x 1 ECl Random Access Memory ....................
DM10422 1024·Bit (256 x 4) ECl RAM ............................. '............
DM10470 4096·Bit (4096 x 1) ECl RAM ........................................
DM100414 256·Bit (256 x 1) ECl RAM .........................................
DM100415 1024 x 1 ECl RAM ...............................................
DM100422 1024·Bit (256 x 4) ECl RAM .................................. " ....
DM100470 4096·Bit (4096 x 1) ECl RAM .......................................

3·23
3·28
3·33
3·34
3·35
3·36
3·37
3·38

Section 4- Magnetic Bubble Memories
DS3615 Bubble Memory Function Driver. . . . . . . . . . . . .
DS3616 Bubble Memory Coil Driver. . . . . . . . . . . . . . . . .
DS3617 Bubble Memory Sense Amplifier. . . . . . . . . . . . .
INS82851 Bubble Memory Controller. . . . . . . . . . . . . . . .
N BM2256 Bubble Memory. . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . ..
. . . . . . . . . . . . . . . . . . . . . . . . . ..
. . . . . . . . . . . . . . . . . . . . . . . . . ..
. . . . . . . . . . . . . . . . . . . . . . . . . ..
. . . . . . . . . . . . . . . . . . . . . . . . . ..

4·1
4·2
4·3
4·4
4·5

MM1702A 2048·Bit (256 x 8) UV Erasable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . ..
MM2708, MM2708·1 8192·Bit (1024 x 8) UV Erasable PROMs. . . . . . . . . . . . . . . . . . . . . . ..
MM2716 16,384·Bit (2048 x 8) UV Erasable PROM .................................
M M2716E 16,384·Bit (2048 x 8) UV Erasable PROM Extended Temperature Range. . . . ..
MM2716M 16,384·Bit (2048 x 8) UV Erasable PROM Military Temperature Range. " ....
MM2758 8192·Bit (1024 x 8) UV Erasable PROM ..................................
MM4203/MM5203 2048·Bit(256 x 8 or 512 x 4) UV Erasable PROM ...................
MM4204/MM5204 4096·Bit (512 x 8) UV Erasable PROM ............................
MM5204·1 4096·Bit (512 x 8) UV Erasable PROM ..................................
NMC2532 32k·Bit (4k x 8) UV Erasable PROM .................... , .............. ,
N MC2564 64k·Bit (8k x 8) UV Erasable PROM ....... , , ................... , . , . . . ..
NMC27C16 16,384·Bit (2048 x 8) UV Erasable CMOS PROM ........................
NMC2724 16k·Bit (2k x 8) UV Erasable PROM ....................................
NMC2732 32k·Bit (4k x 8) UV Erasable PROM ................................ , ...

5·1
5·7
5·12
5·18
5·24
5·30
5·36
5·41
5·46
5·49
5·54
5·55
5·61
5·66

Section 5-MOS EPROMs

5

Table of Contents (Continued)
Section 6- Bipolar PROMs
schottky
DM54S188/DM74S188 256-Bit (32 x 8) Open-Collector PROM. . . . . . . . . . . . . . .. . . . . ..
DM54S287/DM74S287 1024·Bit (256 x 4) TRI·STATE® PROM .................... "
DM54S288/DM74S288 256·Bit (32 x 8) TRI·STATE® PROM. . . . . . . . . . . . . . . . .. . . . . ..
DM54S387/DM74S3871024·Bit (256 x 4) Open·Coliector PROM .................. "
DM54S472/DM74S472 4096·Bit (512 x 8) TRI·STATE® PROM ............. .' . . . . . . ..
DM54S473/DM74S473 4096·Bit (512 x 8) Open-Collector PROM .................. "
DM54S474/DM74S474 4096·Bit (512 x 8) TRI·STATE® PROM ......................
DM54S475IDM74S475 4096·Bit (512 x 8) Open·Coliector PROM .................. "
DM54S570/DM74S570 2048·Bit (512 x 4) Open·Collector PROM ....................
DM54S571/DM74S571 2048·Bit (512 x 4) TRI·STATE® PROM ..................... "
DM54S572IDM74S572 4096·Bit (1024 x 4) Open·Collector PROM ...................
DM54S573IDM74S573 4096·Bit (1024 x 4) TRI·STATE® PROM ................... "
DM77S1801DM87S180, DM77S181/DM87S181 1024 x 8·Bit TTL PROM ..............
DM77S184/DM87S184 8192·Bit (2048 x 4) Open·Collector PROM ................ "
DM77S185/DM87S185 8192·Bit (2048 x 4) TRI·STATE® PROM ................... "
DM77S188/DM87S188, DM77S288/DM87S288 32 x 8·Bit TTL PROM .............. "
DM77S190/DM87S190, DM77S191/DM87S191 2048 x 8·Bit TTL PROM ............ "
Schottky PROM Programming Procedure ................................... "

6-3
6·5
6·3
6·5
6·8
6·8
6·10
6·10
6·13
6·13
6-16
6·16
6·18
6·20
6-20
6-22
6·24
6·26

Eel
DM10416 256 x 4·Bit ECL PROM ........................................... " 6-29
DM100416 256 x 4·Bit ECL PROM ............................................ 6-30

Section 7-MOS ROMs
MM5213 2048·Bit (256 x 8 or 512 x 4) ROM ..................................... "
MM5214 4096·Bit (512 x 8) ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5220 1024·Bit (128 x 8 or 256 x 4) ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM52211024·Bit (128 x 8 or 256 x 4) ROM ..................................... "
M M5230 2048·Bit (256 x 8 or 512. x 4) ROM .. :. . . . .. . . . .. . . .. .. . . .. . . . . . . .. . . .. . ..
MM52312048·Bit (256 x 8 or 512 x 4) ROM .......................................
MM5232 4096·Bit (512 x 8 or 1024 x 4) ROM .................................... "
MM5240 2560·Bit Static Character Generator ....................................
MM5241 3072·Bit (64 x 6 x 8) ROM .............................................
MM52116 (2316E) 16,384·Bit Read Only Memory ................................. "
MM52132 32,768·Bit (4096 x 8) MAXI·ROM™ .....................................
MM52164 65,536·Bit (8192" x 8) MAXI.ROM™ .................................... "
MM52264 MAXI~ROMTM 65,536·Bit Clocked Read Only Memory. . . . . . . . . . . . . . . . . . . . ..

7·1
7·3
7·5
7·9
7·13
7·17
7·21
7·24
7·27
7·30
7·33
7·36
7·39

Section 8-Character Generators
Bipolar
DM8678 Bipolar Character Generator ...................................... "
8·3
DM76S64IDM86S64 Bipolar Character Generator ............................... 8·15
DM76S128/DM86S128 Bipolar Character Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8·26

MOS
MM5240AA, MM5240AE, MM5241ABL American and European Character Fonts ... " 8-39
MM52116FDW, MM52116FDX Character Generators .......' .... '." .............. '. 8·43
6

Table of Contents (Continued)
Section 9- Memory Support Circuits
Memory Support Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Memory Support Circuits Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CD4518BM/CD4518BC, CD4520BM/CD4520BC Dual Synchronous Up Counters. . . . . . ..
DM7555IDM8555, DM7556/DM8556 TRI·STATE® Programmable
Decade/Binary Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM54LS373/DM74LS373, DM54LS374IDM74LS374 Octal D·Type Transparent Latches
and Edge·Triggered Flip·Flops .................................... , ...... : ..
DM54S240/DM 74S240, DM 54S241 IDM74S241 , DM54S940/DM74S940,
DM54S941IDM74S941 Octal TRI·STATE® Buffers/Line Drivers/Line Receivers.. . . . ..
DP7303IDP8303 8·Bit TRI·STATE® Bidirectional Transceiver (Inverting) ............. "
DP7304B/DP8304B 8·Bit TRI·STATE® Bidirectional Transceiver (Non·lnverting) ........
DP7307IDP8307 8·Bit TRI·STATE® Bidirectional Transceiver (Inverting) ..... , . . . . . . . ..
DP7308IDP8308 8·Bit TRI·STATE® Bidirectional Transceiver (Non·lnverting) ...........
DP8212, DP8212M 8·Bit Input/Output Port. ................ ' ......................
DP8216, DP8216M,DP8226, DP8226M 4·Bit Bidirectional Bus Transceivers .. , .........
DP8350 Series Programmable CRT Controllers ..................................
DS3622 Dual Fail·Safe TTL·MOS Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DS1628IDS3628 Octal TRI·STATE® MaS Driver ................................. "
DS 1631 IDS3631 , DS 1632/DS3632, DS 1633/DS3633, DS 1634IDS3634
CMOS Dual Peripheral Drivers .................................... , .........
DS3643, DS3673 Decoded Quad MOS Clock Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DS1644IDS3644 Quad TTL·MOS Clock Drivers ...................................
DS1645IDS3645 Hex TRI·STATE® TTL·MOS Latches/Drivers ........................
DS1647/DS3647 Quad TRI·STATE® MaS Memory I/O Registers .....................
DS1648IDS3648 TRI·STATE® MaS MultiplexerslDrivers ............................
DS1649/DS3649 Hex TRI·STATE® TTL·MOS Drivers ............................. :.
DS1674IDS3674 Quad TTL·MOS Clock Driver. ...................................
DS1675IDS3675 Hex TRI·STATE® TTL·MOS Latches/Drivers ........................
DS1677/DS3677 Quad TRI·STATE® MOS Memory I/O Registers. . . . . . . . . . . . . . . . . . . ..
DS1678IDS3678 TRI·STATE® MaS MultiplexerslDrivers ............................
DS1679/DS3679 Hex TRI·STATE® TTL·MOS Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DS16147IDS36147 Quad TRI·STATE® MOS Memory 110 Registers ...................
DS16149IDS36149 Hex MaS Drivers ............................................
DS16177IDS36177 Quad TRI·STATE® MOS Memory I/O Registers ...................
DS16179IDS36179 Hex MaS Drivers ................................... '.........
DS75322 Dual TTL·MOS Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DS8T26A, DS8T26AM, DS8T28, DS8T28M 4·Bit Bidirectional Bus Transceivers. . . . . . . ..
MM54C240/MM74C240 (Inverting Outputs), MM54C244/MM74C244 (Non·lnverting
Outputs) Octal Buffers and Line Drivers with TRI·STATE® Outputs ................
MM54C373/MM74C373 TRI·STATE® Octal D·Type Latch ...........................
MM54C374/MM74C374 TRI·STATE® Octal D·Type Flip·Flop .........................

9·1
9·4
9·5
9·6
9·7
9·8
9·9
9·10
9·11
9·12
9·13
9·14
9·15
9·25
9·16
9·17
9·23
9·18
9·19
9·20
9·21
9·22
9·18
9·19
9·20
9·21
9·22
9·20
9·24
9·20
9·24
9·25
9·26
9·27
9·28
9·28

Section 10-Physical Dimensions
Physical Dimensions ........................................................ 10·1

7

Alpha-Numerical Index
CD4518BM Dual Synchronous Up Counter. . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . ..
CD4518BC Dual Synchronous Up Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CD4520BM Dual Synchronous Up Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CD4520BC Dual Synchronous Up Counter ........... : . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM10414 256 x 1 ECl Random Access Memory ..................................
DM10414A 256 x 1 ECl Random Access Memory .................................
DM10415 1024 x 1 ECl Random Access Memory .................................
DM10415A 1024 x 1 ECl Random Access Memory ................................
DM10416 256 x 4-Bit ECl PROM ...............................................
DM10422 1024-Bit (256 x 4) ECl RAM ...........................................
DM10470 4096-Bit (4096 x 1) ECl RAM ..........................................
DM100414 256-Bit (256 x 1) ECl RAM ...........................................
DM100415 1024 x 1 ECl RAM .................................................
DM100416 256 x 4-Bit ECl PROM ..............................................
DM100422 1024-Bit (256 x 4) EC~ RAM ........... ~ ..............................
DM100470 4096-Bit (4096 x 1) ECl RAM .........................................
DM54S188 256-Bit (32 x 8) Open-Collector PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM54lS373 Octal D-Type Transparent latches and Edge-Triggered Flip-Flops. . . . . . . ..
DM54lS374 Octal D-Type Transparent latches and Edge-Triggered Flip-Flops. . . . . . . ..
DM54S240 Octal TRI-STATE®· Buffer/Line Driver/Line Receiver. . . . . . . . . . . . . . . . . . . . ..
DM54S241 Octal TRI-STATE® Buffer/Line Driver/Line Receiver. . . . . . . . . . . . . . . . . . . . ..
DM54S287 1024-Bit (256 x 4) TRI-STATE® PROM. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . ..
DM54S288 256-Bit (32 x 8) TRI-STATE® PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM54S387 1024-Bit (256 x 4) Open-Collector PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM54S472 4096-Bit(512 x 8) TRI-STATE® PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM54S473 4096-Bit (512 x 8) Open-Collector PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM54S474 4096-Bit (512 x 8) TRI-STATE® PROM ............ : .....................
DM54S475 4096-Bit (512 x 8) Open-Collector PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM54S570 2048-Bit (512 x 4) Open-Collector PROM ...............................
DM54S571 2048-Bit (512 x 4) TRI-STATE® PROM ..................................
DM54S572 4096-Bit (1024 x 4) Open-COllector PROM ..............................
DM54S573 4096-Bit (1024 x 4) TRI-STATE® PROM .................................
DM54S940 Octal TRI-STATE® Buffer/Line Driver/Line Receiver. . . . . . . . . . . . . . . . . . . . ..
DM54S941 Oc.tal TRI-STATE® Buffer/Line Driver/Line Receiver. . . . . . . . . . . . . . . . . . . . ..
DM74S188 256-Bit (32 x 8) Open-Collector PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM74lS373 Octal D-Type Transparent latches and Edge-Triggered Flip·Flops. . . . . . . ..
DM74lS374 Octal D-Type Transparent latches and Edge-Triggered Flip·Flops. . . . . . . ..
DM74S240 Octal TRI·STATE® Buffer/Line Driver/Line Receiver. . . . . . . . . . . . .. . . . . . ...
DM74S241 Octal TRI-STATE® Buffer/Line Driver/Line Receiver .................. '.' ..
DM74S2871024·Bit (256 x 4) TRI·STATE® PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM74S288 256-Bit (32 x 8) TRI·STATE® PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM74S387 1024·Bit (256 x 4) Open·Collector PROM .............................. .
DM74S472 4096-Bit (512 x 8) TRI-STATE® PROM ................................. .
DM74S473 4096·Bit (512 x 8) Open-Collector PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM74S474 4096·Bit (512 x 8) TRI-STATE® PROM ............. : ................... .
DM74S475 4096·Bit (512 x 8) Open·Collector PROM .............................. .
DM74S570 2048·Bit (512 x 4) Open·Coliector PROM .............................. .
DM74S571 2048·Bit (512 x 4) TRI·STATE® PROM ................................. .
DM74S572 4096·Bit (1024 x 4) Open·Coliector PROM .............................. .
8

9-5
9-5
9-5
9-5
3-23
3-23
3-28
3-28
6-29
3-33
3-34
3-35
3-36
6-29
3-37
3-38
6-3
9-7
9-7
9-8
9-8
6-5
6-3
6-5
6-8
6-8
6-10
6-10
6-13
6-13
6-16
6-16
9-8
9-8
6-3
9·7
9·7
9-8
9·8
6-5
6·3
6·5
6·8"
6-8
6·10
6·10
6·13
6·13
6-16

Alpha-Numerical Index (Continued)
DM74S573 4096-Bit (1024 X 4) TRI-STATE® PROM ................................ ,
DM74S940 Octal TRI-STATE® Buffer/Line Driver/Line Receiver. . . . . . . . . . . . . . . . . . . . ..
DM74S941 Octal TRI-STATE® Buffer/Line Driver/Line Receiver. . . . . . . . . . . . . . . . . . . . ..
DM7555 TRI-STATE® Programmable Decade/Binary Counter. . . . . . . . . . . . . . . . . . . . . ..
DM7556 TRI-STATE® Programmable Decade/Binary Counter ...................... ,
DM7589 64-Bit (16 x 4) RAM .................................................. ,
DM7599 64-Bit (16 x 4) TRI-STATE® RAM ....................................... ,
DM76S64 Bipolar Character Generator ........................................ ,
DM76S128 Bipolar Character Generator ....................................... ,
DM77S180 1024 x 8-Bit TTL PROM .............................................
DM77S181 1024 x 8-Bit TTL PROM .............................................
DM77S184 8192-Bit (2048 x 4) Open-Collector PROM ..............................
DM77S185 8192-Bit (2048 x 4)TRI-STATE® PROM .................................
DM77S188 32 x 8-Bit TTL PROM ...............................................
DM77S190 2048 x 8-Bit TTL PROM ............................................ ,
DM77S191 2048 x 8-Bit TTL PROM ............................................ ,
DM77S288 32 x 8-Bit TTL PROM .............................................. ,
DM8555 TRI-STATE® Programmable Decade/Binary Counter. . . . . . . . . . . . . . . . . . . . . ..
DM8556 TRI-STATE® Programmable Decade/Binary Counter. . . . . . . . . . . . . . . . . . . . . ..
DM85S6816 x 4 Edge-Triggered Register ........................................
DM8589 64-Bit (16 x 4) RAM .................................................. ,
DM8599 64·Bit (16 x 4) TRI-STATE® RAM.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM86S64 Bipolar Character Generator ........ , ............................... ,
DM8678 Bipolar Character Generator ......................................... ,
DM86S128 Bipolar Character Generator ....................................... ,
DM87S180 1024 x 8-Bit TIL PROM ............................................ ,
DM87S181 1024 x 8-Bit TIL PROM ................................... ; .........
DM87S184 8192-Bit (2048 x 4) Open-Collector PROM ............................. ,
DM87S185 8192-Bit (2048 x 4) TRI-STATE® PROM .................................
DM87S188 32 x 8-Bit TIL PROM .............................. '.' ...............
DM87S190 2048 x 8-Bit TIL PROM .............................................
DM87S191 2048 x 8-Bit TIL PROM ............................................ ,
DM87S288 32 x 8-Bit TIL PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DP7303 8-Bit TRI-STATE® Bidirectional Transceiver (Inverting). . . . . . . . . . . . . . . . . . . . ..
DP7304B 8-Bit TRI-STATE® Bidirectional Transceiver (Non-Inverting) ................ ,
DP7307 8-Bit TRI-STATE® Bidirectional Transceiver (Inverting) ..................... ,
DP7308 8-Bit TRI-STATE® Bidirectional Transceiver (Non-Inverting). . . . . . . . . . . . . . . . ..
DP8212 8-Bit Input/Output Port. .......................................... , ....
DP8212M 8-Bit Input/Output Port ............ : ............................ , ... ,
DP8216 4-Bit Bidirectional Bus Transceiver ..................................... ,
DP8216M 4-Bit Bidirectional Bus Transceiver ................................... ,
DP8226 4-Bit Bidirectional Bus Transceiver ................................. , ... ,
DP8226M 4-Bit Bidirectional Bus Transceiver ................................... ,
DP8303 8-Bit TRI-STATE® Bidirectional Transceiver (Inverting) ..................... ,
DP8304B 8-Bit TRI-STATE® Bidirectional Transceiver (Non-Inverting) ................ ,
DP8307 8-Bit TRI-STATE® Bidirectional Transceiver (Inverting). . . . . . . . . . . . . . . . . . . . ..
DP8308 8-Bit TRI-STATE® Bidirectional Transceiver (Non-Inverting) ................. ,
DP8350 Series Programmable CRT Controllers ..................................
DS8T26A 4-Bit Bidirectional Bus Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
9

6-16
9-8
9-8
9-6
9-6
3-3
3-6
8-15
8-26
6-18
6-18
6-20
6-20
6-22
6-24
6-24
6-22
9-6
9-6
3-13
3-3
3-6
8-15
8-3
8-26
6-18
6-18
6-20
6-20
6-22
6-24
6-24
6-22
9-9
9-10
9-11
9-12
9-13
9-13
9-14
9-14
9-14
9-14
9-9
9-10
9-11
9-12
9-15
9-26

Alpha-Numerical Index (Continued)
DS8T26AM 4·Bit Bidirectional Bus Transceiver ................................. "
DS8T28 4·Bit Bidirectional Bus Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DS8T28M 4·Bit Bidirectional Bus Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DS1628 Octal TRI·STATE® MOS Driver ........................................ "
DS1631 CMOS Dual Peripheral Driver ...................... : ................. "
DS1632 CMOS Dual Peripheral Driver ........................................ "
DS1633 CMOS Dual Peripheral Driver ..........................................
DS1634 CMOS Dual Peripheral Driver ........................................ "
DS1644 Quad TTL·MOS Clock Driver ......................................... "
DS1645 Hex TRI·STATE® TTL·MOS LatchlDriver ..................................
DS1647 Quad TRI·STATE® MaS Memory 1/0 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DS1648 TRI·STATE® MaS Multiplexer/Driver ............................ , ...... "
DS1649 Hex TRI·STATE® TTL·MOS Driver ..................................... "
DS1674 Quad TTL·MOS Clock Driver ...........................................
DS1675 Hex TRI·STATE® TTL·MOS LatchlDriver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DS1677 Quad TRI·STATE® MaS Memory 1/0 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DS1678 TRI·STATE® MaS Multiplexer/Driver ................................... "
DS1679 Hrx TRI·STATE® TTL·MOS Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DS3615 Bubble Memory Function Driver ...................................... "
DS3616 Bubble Memory Coil Driver ........................................... ~
DS3617 Bubble Memory Sense Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DS3622 Dual Fail·Safe TTL·MOS Driver ....................................... "
DS3628 Octal TRI·STATE® MaS Driver ........................................ "
DS3631 CMOS Dual Peripheral Driver ................... : .................... "
DS3632 CMOS Dual Peripheral Driver; .........................................
DS3633 CMOS Dual Peripheral Driver ....................... .-..................
DS3634 CMOS Dual Peripheral Driver ..........................................
DS3643 Decoded Quad MaS Clock Driver ..................................... "
DS3644 Quad TTL·MOS Clock Driver ...........................................
DS3645 Hex TRI·STATE® TTL·MOS LatchlDriver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DS3647 Quad TRI·STATE® MOS Memory 1/0 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DS3648 TRI·STATE® MaS MultiplexerlDriver ....................................
DS3649 Hex TRI·STATE® TTL·MOS Driver ..................................... "
DS3673 Decoded Quad MaS Clock Driver ...................................... "
DS3674 Quad TTL·MOS Clock Driver. ........................................ "
DS3675 Hex TRI·STATE® TTL·MOS LatchlDriver ................................ "
DS3677 Quad TRI·STATE® MOS Memory 1/0 Register ........................... "
DS3678 TRI·STATE® MaS MultiplexerlDriver ....................................
DS3679 Hex TRI·STATE® TTL·MOS Driver ................................. '. . . . ..
DS16147 QuadTRI·STATE® MaS Memory 1/0 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DS16149 Hex MOS Driver ................................................... ~.
0816177 Quad TRI·STATE® MaS Memory 1/0 Register ..........-. . . . . . . . . . . . . . . . . ..
DS16179 Hex MOS Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DS36147 Quad TRI·STATE® MaS Memory 1/0 Register. . . . . . . . . . . . . . . . . . . . . . . . . . ..
DS36149 Hex MOS Driver ................................................... "
DS36177 Quad TRI·STATE® MaS Memory 1/0 Register. . . . . . . . . . . . . . . . . . . . . . . . . . ..
DS36179 Hex MOS Driver ................................................... "
DS75322 Dual TTL·MOS Driver ...................... ; ....................... "
IDM29705 16·Word by 4·Bit Two·Port RAM/Register File ......................... "
10

9·26
9·26
9·26
9·16
9·17
9·17
9·17
9·17
9·18
9·19
9·20
9~21

9·22
9·18
9·19
9·20
9·21
9·22
4·1
4·2
4·3
9·25
9·16
9·17
9·17
9·17
9·17
9·23
9·18
9·19
9·20
9·21
9·22
9·23
9·18.
9·19
9·20
9·21
9·22
9·20
9·24
9·20
9·24
9·20
9·24
9·20
9·24
9·25
3·15

Alpha-Numerical Index (Continued)
IDM29705A 16·Word by 4·Bit Two·Port RAM/Register File ..........................
INS82851 Bubble Memory Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM1702A 2048·Bit (256 x 8) UV Erasable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM2102A Family 1024·Bit (1024 x 1) Static RAMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM2102AL Family 1024·Bit (1024 x 1) Static RAMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM2114 Family 4096·Bit (1024 x 4) Static RAMs ......... ~ . . . . . . . . . . . . . . . . . . . . . . . .
MM2114L Family 4096·Bit (1024 x 4) Static RAMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM2147 Family 4096 x 1 Static RAMs: .........................................
MM2147L Family 4096 x 1 Static RAMs .........................................
MM2708 8192·Bit (1024 x 8) UV Erasable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. ..
MM2708·1 8192·Bit (1024 x 8) UV Erasable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . ..
MM2716 16,384·Bit (2048 x 8) UV Erasable PROM .................................
MM2716E 16,384·Bit (2048 x 8) UV Erasable PROM Extended Temperature Range ......
MM2716M 16,384·Bit (2048 x 8) UV Erasable PROM Military Temperature Range .......
MM2758 8192·Bit (1024 x 8) UV Erasable PROM ..................................
MM4203 2048·Bit (256 x 8 or 512 x 4) UV Erasable PROM ...........................
M M4204 4096·Bit (512 x 8) UV Erasable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4280 4096·Bit (4096 x 1) Extended Temperature Range Dynamic RAM .............
MM5203 2048·Bit (256 x 8 or 512 x 4) UV Erasable PROM ...........................
MM5204 4096·Bit (512 x 8) UV Erasable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5204-1 4096·Bit (512 x 8) UV Erasable PROM ..................................
MM5213 2048·Bit (256 x 8 or 512 x 4) ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5214 4096-Bit (512 x 8) ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5220 1024·Bit (128 x 8 or 256 x 4) ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5221 1024-Bit (128 x 8 or 256 x 4) ROM ..................... '. . . . . . . . . . . . . . . . ..
MM5230 2048·Bit (256 x 8 or 512 x 4) ROM .......................................
MM5231 2048·Bit (256 x 8 or 512 x 4) ROM .......................................
MM5232 4096·Bit (512 x 8 or 1024 x 4) ROM ......................................
MM5240 2560·Bit Static Character Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5240AA American and European Character Fonts .............................
MM5240AE American and European Character Fonts. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5241 3072·Bit (64 x 6 x 8) ROM .............................................
MM5241ABL American and European Character Fonts. . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5257 Family 4096·Bit (4096 x 1) Static RAMs ..................................
MM5257L Family 4096·Bit (4096 x 1) Static RAMs .................................
MM5280 4096-Bit (4096 x 1) Dynamic RAM .......................................
MM5280·5 4096-Bit (4096 x 1) Dynamic RAM .....................................
MM5290 16,384·Bit (16,384 x 1) Dynamic RAM ....................................
MM5298 8192-Bit (8192 x 1) Dynamic RAM ......................................
MM52116 (2316E) 16,384-Bit Read Only Memory ..................................
MM52116FDW Character Generator.............................................
MM52116FDX Character Generator..............................................
MM52132 32,768·Bit (4096 x 8) MAXI·ROM™ ......................................
MM52164 65,536·Bit (8192 x 8) MAXI·ROM™ ..................... ; ................
MM52264 MAXI-ROMTM 65,536·Bit Clocked Read Only Memory. . . . . . . . . . . . . . . . . . . ..
M M54C89 64·Bit (16 x 4) TRI·STATE® RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
'MM54C200 256·Bit (256 x 1) TRI-STATE® RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM54C240 (Inverting Outputs) Octal Buffers and Line Drivers
with TRI·STATE® Outputs .................... : . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
11

3·15
4·4
5·1
1·3
'1·3
1·6
1·6
1·10
1-10
5·7
5-7
5-12
5-18
5-24
5-30
5·36
5-41
1-45
5·36
5·41
5·46
7·1
7·3
7·5
7·9
7·13.
7·17
7·21
7·24
8·39
8·39
7·27
8·39
1·15
1·15
1·49
1·53
1·55
1·61
7·30
8·43
8·43
7-33
7·36
7·39
2·1
2·5
9-27

Alpha-Numerical Index (Continued)
MM54C244 (Non·lnverting OutputS) Octal Buffers and Line Drivers
with TRI·STATE® Outputs. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . ..
MM54C373 TRI·STATE® Octal D·Type Latch ......................................
MM54C374 TRI·STATE® Octal D·Type Flip·Flop ...................................
MM54C910 256·Bit (64 x 4) TRI·STATE® RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
M M54C920 1024·Bit (256 x 4) Static RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM54C9211024·Bit (256 x 4) Static RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM54C929 1024·Bit (1024 x 1) Static RAM .......................................
MM54C930 1024·Bit (1024 x 1) Static RAM .......................................
MM54C989 64·Bit (16 x 4) TRI·STATE® RAM ... : .................... , .............
MM74C89 64·Bit (16 x 4) TRI·STATE® RAM ........................................ ~
MM74C200 256·Bit (256 x 1) TRI·STATE® RAM .............. : . . . . . . . . . . . . . . . . . . . ..
MM74C240 (Inverting Outputs) Octal Buffers and Line Drivers
with TRI·STATE® Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM74C244 (Non·lnverting Outputs) Octal Buffers and Line. Drivers
with TRI·STATE® Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM74C373 TRI·STATE® Octal D·Type Latch .....................................
MM74C374 TRI·STATE® Octal D·Type Flip·Flop ...................................
M M74C910 256·Bit (64 x 4) TRI·STATE® RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM74C920 1024·Bit (256 x 4) Static RAM ........................................
M M74C921 1024·Bit (256 x 4) Static RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM74C9291024·Bit (1024 x 1) Static RAM .......................................
MM74C930 1024·Bit (1024 x 1) Static RAM .......................................
MM74C989 64·Bit (16 x 4) TRI·STATE® RAM .... ~ .................................
NBM2256 Bubble Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . ..
NMC2114A 4096·Bit (1024 x 4) Static RAM .............. , ........................
NMC2114AP.4096·Bit (1024x4) Static RAM .....................................
NMC2141 4096·Bit (4096 x 1) Static RAM ........................................
NMC2142A 4096·Bit (1024 x 4) Static RAM .......................................
NMC2142AP 4096·Bit (1024 x 4) Static RAM .....................................
NMC21481024 x 4 Static RAM ................................................
NMC2148L 1024 x 4 Static RAM ...............................................
NMC2532 32k·Bit (4k x 8) UV Erasable PROM ....................................
NMC2564 64k·Bit (8k x 8) UV Erasable PROM ....................................
N MC27C16 16,384·Bit (2048 x 8) UV Erasable CMOS PROM. . . . . . . . . . . . . . . . . . . . . . ..
NMC2724 16k·Bit (2k x 8) UV Erasable PROM ....................................
NMC2732 32k·Bit (4k x 8) UV Erasable PROM ....................................
NMC4164 65,536·Bit (65,536 x 1) Dynamic RAM ..................................
NMC4864 64k Pseudo·Static Byte·Wide RAM ....................................
NMC5257A 4096·Bit(4096 x 1) Static RAM ...............•.......................
NMC5295 16,384·Bit (16,384 x 1) Dynamic RAM ....... '...........................
NMC6132 32k Pseudo·Static NMOS RAM .....................•.................
NMC6504 4096·Bit (4096 x 1) Static RAM ........................................
NMC65081024·Bit (1024 x 1) Static RAM ........................................
NMC6514 4096·Bit (1024 x 4) Static RAM ........................................
NMC651.81024·Bit (1024 x 1) Static RAM ........................................
NMC6551 1024·Bit (256 x 4) Static RAM ..... : ...................................
NMC6552 1024·Bit (256 x 4) Static RAM .............................. ~ ..........

12

9·27
9·28
9·28
2·8
2·12·
2~ 12
2·19
2·19
2·26
2·1
2·5·
9·27
9·27
9·28
9·28
2·8
2·12
2·12
2·19
2·19
2·26
4·5
1·20
1·20
1·24
1·28
1·28
1·32
1·32
5·49
5·54
5·55
5·61
5·66
1·67
1·35
1·24
1·77
1·42
2·30
2·37
2·43
2·49
2·55
2·61

Definition of Terms

The following selection guides as well as the data sheets in this manual include products that represent the state-of-the-art
design and processing of semiconductor memories. These devices had not been released to production at the time this book
was printed. No orders can be placed for these devices without prior approval by National Semiconductor via your local
National representative or distributor. These products are in various stages of design and/or pre-production. Samples may be
available as you read this. Contact your local representative or distributor for up-to-date status on product availability.
The individual data sheets show the product status at the time of printing. These classif~cation labels are defined as follows:
Status

Specifications

Product Stage

PREVIEW

Formative or In Design

This data sheet contains the design specifications for
product development. Specifications may change in any
manner without notice.

ADVANCE INFORMATION

Sampling or Pre-Production

This data sheet contains advance information and specifications are subject to change without notice.

PRELIMINARY

First Production

This data sheet contains preliminary data and supplementary data will be published at a later date. NSC
reserves the right to make changes at any time without
notice in order to improve design and supply the best
possible product.

13

Proposed Standard Terminology

This databook includes a new set of symbols. This new
format is a proposed industry standard for semiconductor
memories. It is intended to clarify the symbols, abbreviations and definitions, and to make all memory data sheets
consistent.

Example:
CHIP
SELECT

S

DC Electrical Parameter Abbreviations
All abbreviations use upper case letters with no subscripts. The initial symbol is one of these four characters:
V
I
P
C

Chip Select access time, TSLQV, the time from Chip
Select low to Data Out val id, and the time from Chip Select
low to Data Out active, TSLQX, are shown.

(Voltage)
(Current)
(Power)
(Capacitance)

Timing Limits

The second letter specifies input (I) or output (0), and the
third letter indicates the high (H), low (L) or off (Z) state of
the pin during measurements. Examples:

The table of timing values shows either a minimum or a
maximum limit for each parameter. Input requirements are
specified from the external system point of view; e.g., the
address set-up time is shown as a minimum since the
system must supply at least that much time. On the other
hand, responses from the memory are specified from the
device pOint of view, e.g., the access time is shown as a
maximum since the device never provides data later than
that time.

VIL-Input Low Voltage
10Z-Output Leakage Current

AC Electrical Parameter Abbreviations
All timing abbreviations use upper case characters with
no subscripts. The initial character is always T and is
followed by four or more descriptors. These characters
specify two signal points arranged in a "from-to" sequence that define a timing interval. The two or more
descriptors for each signal point specify the signal name
and signal transitions. The format using four descriptors
is:
T X X X X
Signal name from which Interval is defined
Transition direction for first signal
Signal name to which interval is defined
Transition direction for second signal

Waveforms
Waveform
Symbol

JIll

Signal Definitions:
A =Address
o = Data In
Q = Data Out
W = Write Enable
E = Chip Enable
S = Chip Select
G = Output Enable
Transition Definitions:
H
L
V
X
Z

= Transition
= Transition
= Transition
= Transition
= Transition

to
to
to
to
to

High
Low
Valid
Invalid or Don't Care
Off (High Impedance)

Input

Output

MUST BE
VALID

WILL BE
VALID

~

CHANGE
FROM HTO L

WILL CHANGE
FROM HTOL

~

CHANGE
FROM L TO H

WILL CHANGE
FROM L TO H

DON'T CARE:
ANY CHANGE
PERMITIED

CHANGING:
STATE UNKNOWN

N/A

14

HIGH
IMPEDANCE

MOS RAM Selection Guide
Size

65,536

32,768

16,384

8,192

4,096

4,096

1,024

Organization

65,536 x 1

Part No.

NMC4164·2
NMC4164·3
8,192x8 NMC4864
4,096x8 NMC6132·3
NMC6132·4
NMC6132-5
16,384 x 1 NMC5295-2
NMC5295-3
NMC5295-4
MM5290-1
MM5290-2
MM5290-3
MM5290-4
8,192 x 1 MM5298A-2
MM5298A-3
MM5298A-4
MM5298B-2
MM5298B-3
MM5298B-4
4,096 x 1 MM2147
MM2147-3
MM2147L
MM2147L-1
NMC2141
NMC5257A
MM5257
MM5257L
MM5257-2
MM5257-2L
4,096 x 1 MM5257-3
MM5257-3L
MM4280
MM5280
MM5280-5
1,024 x4 NMC2148
NMC2148-3
NMC2148L
NMC2142A
NMC2142AP
NMC2114A
NMC2114AP
MM2114
MM2114L
MM2114-2
MM2114-2L
MM2114-3
MM2114-3L
1,024 x 1 MM2102A
MM2102A-L
MM2102A-2
MM2102A-2L
MM2102A-4
MM2102A-4L
MM2102A-6
MM2102A-6L

Operation

Dynamic
Dynamic
Pseudo-Static
Pseudo-Static
Pseudo-Static
Pseudo-Static
Dynamic
Dynamic
Dynamic
Dynamic
Dynamic
Dynamic
Dynamic
Dynamic
Dynamic
Dynamic
Dynamic
Dynamic
Dynamic
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Dynamic
Dynamic
Dynamic
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static

Max
Max
Standby
Access
Current
Supply
Time
Current (rnA) (rnA)
(ns)
45
45
40
40
40
40
35
35
35
40
40
40
40
40
40
40
40
40
40
160
180
140
140
120
120
• 90
65
90
65
90
65
60
60
60
160
180
140
50
15
50
50
100
70
100
70
100
70
50
33
50
33
50
33
50
33

·c=o·c to 70·C
1= -40'C to +85·C
• • See Definition of Terms

15

4
4
6
25
25
25
4
4
4
1_5
1_5
1_5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
20
30
10
10
15
120
90
65
90
65
90
65
",0
",0
",0
20
30
10
50
15
50
15
100
70
100
70
100
70
50
33
50
33
50
33
50
33

120
150
150
200
250
300
80
100
120
120
150
200
250
150
200
250
150
200
250
70
55
70
90
120
120
450
450
200
200
300
300
270
200
270
70
55
70
120
120
120
120
450
450
200
200
300
300
350
350
250
250
450
450
650
650

Supply
Voltage

Pkg

Temp·
Range

Status··

16
16
28
28
28
28
16
16
16
16
16
16
16
16
16
16
16
16
16
18
18
18
18
18
18
18
18
18
18
18
18
22
22
22
18
18
18
20
20
20
18
18
18
18
18
18
18
16
16
16
16
16
16
16
16

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
I
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

Preview
Preview
Preview
Preview
Preview
Preview
Advance Info
Advance Info
Advance Info
Production
Production
Production
Production
Production
Production
Production
Production
Production
Production
Production
Production
Production
Production
Preview
Preview
Production
Production
Production
Production
Production
Production
Production
Production
Production
Preview
Preview
Preview
Preview
Preview
Preview
Preview
Production
Production
Production
Production
Production
Production
Production
Production
Production
Production
Production
Production
Production
Production

(V)

+5
+5
+5
+5
+5
+5
+5
+5
+5
±5, +12
±5, +12
±5, +12
±5, +12
±5, +12
±5, +12
±5, +12
±5, +12
±5, +12
±5, +12
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
±5, + 12
±5, + 12
±5, + 12
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5'
+5
+5
+5
+5
+5
+5

Q)

:2
::s

CMOS RAM Selection Guide

~

c:
o
;:
(J
Q)

Size

4,096

Organization

4,096 x 1

Q)

en

:E


..,..,

-

i-

..

T
~

30 pF
(INCLUDING
SCOPEAND
JIG)

>

'----

FIGURE 1. Output Load

NORMALIZED ICC

FIGURE 2. power On Current

Note 1: Guaranteed with transverse air flow greater than 400 linear feet per minute.
Note 2: A pull-up resistor to vee on the chip select input is required to keep the device deselected or power on current approaches Ice active
(see Figure 21Note 3: This parameter is guaranteed by periodic testing.
Note 4: This device requires a 500 ns time delay after vce reaches the specified minimum limit to ensure proper operation after power on. This
allows the internally generated substrate bias to reach its functional level.

1-12

Read Cycle AC Electrical Characteristics

s:
s:

TA = O°C to +70°C, VCC = 5V ±10%

I\)

"""'"

~

SYMBOL

MM2147·3

MM2147L·l

MM2147, MM2147L

PARAMETER
ALTERNATE

UNITS
MIN

STANDARD
Read Cycle Time

MAX

MIN

MAX

70

55

MIN

MAX

90

ns

::::!

s:
s:

tRC

TAVAV

tAA

TAVQV

Address Access Time

55

70

90

ns

I\)

tASCl

TSLOVI

Chip Select Access Time (Note 5)

55

70

90

ns

TSLOV2

Chip Select Access Time (Note 6)

65

80

105

ns

"""'
~"

tASC2
IOH

TAXOX

Output Hold from Address Change

5

5

5

ns

ILZ

TSLOX

Chip Selection to Output Active

10

10

10

ns

tHZ

TSHOZ

Chip Deselectlon to Output TR I STATE

0

tpu

TSLICCH

Chip SelectIOn to Power Up

0

tpD

TSLICCL

Chip De-selection to Power Down

40

0

40

0
30

0

50

ns

35

ns

ns

0
30

Note 5: Chip deselected for greater than 55 ns prior to selection.
Note 6: Chip deselected for a finite time that is less than 55 ns prior to selection.

Read Cycle Waveforms '"

Read Cycle No.1 (Continuously Selected)

*-

tRC
(TAVAV)

ADDRESS

,I

DATA OUT

PREVIOUS DATA VALID

*X X ~E1'------------------------------------DATA VALID

Read Cycle No.2 (Chip Select Switched)

~·--------------(T~C~V) -----------------~

~r

I\.

r--- (T~taX) -------O-lll
HIGH IMPEDANCE
1\

DATA OUT

f--IT;~~Z) -

X X \1/

, ________

II.
DATA VALID
r
I ,,'-______________+-___Ji

HIGH
IMPEDANCE

tF',----------------------------i"\,\ .

POWER ICC ---.-t-----;SUPPlY
7("
CURRENT IS8
1

--+--'
-

II ' - - - - - - - - -

;~~LlCCH)

(TSLlc~8-

• The symbols in parentheses are proposed industry standard.

1·13

I-

--....

rm
"T1

3
--

~

-e

~

Write Cycle AC Electrical Characteristics

If

SYMBOL

TA = O°C to +70°C, VCC = 5V ±10%

MM2147-3

MM2147, MM2147L

MM2147L-1

PARAMETER

UNITS

~

ALTERNATE

~
,...

twc

TAVAV

Write Cycle Time

55

70

90

ns

tcw

TSLWH

Chip Selection to End of Write

45

55

60

n,

N

tAW

TAVWH

Address Valid to End of Write

45

55

60

n,

tAS

TAVWL

Address Setup Time

0

0

0

n,

ns

r-...

:E
:E

ti,...
N

:E
:E

MAX

MIN

STANDARD

MIN

MAX

MIN

MAX

TAVSL
twp

TWLWL

Write Pulse Width

35

40

60

tWR

TWHAX

Write Recovery Time

10

15

20

ns

tow

TOVWH

Data Valid to End of Write

25

30

35

ns

tOH

TWHOX

Data Hold Time

10

twz

TWLOZ

Write Enabled to Output in Hi-Z

0

tow

TWHOX

Output Active from End of Write

0

Write Cycle Waveforms *

10

10
30

0

0

35

0

ns
40

0

ns
ns

(Note 7)
Write Cycle No.1 (WE Controlled)
tw C
(TAVAV)

ADDRESS

B(Sl
(NOTE 5)

,

~~

\"

ICW
(TSLWH)

R

IIJ IIII
lAS
(TAVWL)

(TW~~X)-

lAW
(TAVWH)
-(TW"fWL)-

I

\\'

Ie

C'-(T~e~H)

X

DATA IN

IDH
(TWHDX)

X

DATA IN VALID

f-(~k=1
DATA OUT

,

'\I

DATA UNDEFINED

I-(~~~x)
HIGH IMPEDANCE

'I
'\.

Write Cycle No.2 (CS Controlled)
IWC
(TAVAV)

ICW
(TSLWH)

- - - - - -twp- _
- -_1
_ - (T~~~X)
(TWLWL)

lOW
(TDVWH)
DATA IN

DATA IN VALID

~

LQ_Z_)_J-----------~-------------------

twz
DATA OUT _

________________________________
(TW
__
DATA UNDEFINED

HIGH IMPEDANCE

Note 7: A write occurs during the coincidental low of CS and WE. The output rerrlains TR I-STATE® if Cs and WE go high simultaneously. WE or CS or both must be. high during address transitions_
• The symbols in parentheses are proposed industry slandard.

1·14

~National

NMOS RAMs

~ Semiconductor
MM5257, MM5257L Family
4096·Bit (4096 x 1) Static RAMs

s:
s:
c.n

General-Description

Features

The MM5257 family of 4096-word by 1-bit static random access memories is fabricated using N-channel
silicon-gate technology. All internal circuits are fully
static and therefore require no clocks or refreshing for
operation. The data is read out nondestructively and has
the same polarity as the input data.

• All inputs and outputs directly TTL compatible
• Static operation-no clocks or refreshing required
•

Low power-225 mW typical

•

High speed-down to 200 ns access time

• TRI·STATE output for bus interface

The separate chip enable input (CE) controlling the
TRI-STATE® output allows easy memory expansion by
OR-tying individual devices to a data bus.

• Separate Data In and Data Out pins
• Single +5V supply

The output is held in a high impedance state during
write to simplify common I/O applications.

• Standard 18-pin dual-in-I ine package

Logic Symbol

Connection Diagram
Dual-ln·Line Package

AD
A1
A2
AJ

AD
A1
A2

01

A4

AJ

AS
A6
A7

A4
AS

AS

DO

A9
A1D

WE

01

GNO

CE

A11 CE

Y

TOP VIEW
Order Number MM5257J, J-2, J-25,
J-3, J-L, J-2L, J-25L or J-3L
See NS Package J18A
Order Number MM5257N, N-2, N-25,
N-3, N-L, N-2L, N-25L, or N-3L
See NS Package N18A

Truth Table
CE
H

WE
X

L
L

L
L
H

L

DI

X
H
L
X

DOUT
Hi-Z
Hi-Z
Hi-Z
DOUT
1-15

MODE
Not Selected
Write 1
Write 0
Read

WE DO

I\)

c.n

........

r-

~,

3
--

~

Functional Description
both CE and WE are low. Minimum write-pulse width,
twP, refers to this simultaneous low region. Data set-up
and hold times are measured with respect to whichever
control first rises. Successive write operations may be
performed with CE continuously held low. WE then is
used to terminate WR ITE between address changes.
Alternatively, WE may be held low for successive
WRITES and CE used for WRITE interruption between
address change.

Two pins control the operation of the MM5257. Chip
Enable (CE) enables write and read operations and
controls TRI-STATING of the data-output buffer. Write
Enable (WE) chooses between READ and WR ITE modes
and also controls output TRI-STATING. The truth table
details the states produced by combinations of the CE
and WE controls.
READ-cycle timin~shown in the section on Switch~
Time Waveforms. WE is kept high. Independent of CE,
any change in address code causes new data to be
fetched and brought to the output buffer. CE must be
low, however, for the output buffer to be enabled and
transfer the data to the output pin.
.

In any event, either WE or CE (or both) must be high
during address transitions to prevent erroneous WRITE.

Stand-by operation allows data to be maintained with
approximately 50% less operating current. The 2 require·
ments to guarantee data retention are: a) the power
supply voltage must meet the condition VCC ~ 1.5V,
and b) CE must be controlled; to disable the chip prior
to reducing VCC, to keep it disabled during the time
V CC is reduced, and to maintain the disabled state
long enough after VCC is increased to normal for the
chip to recover. These requirements are shown by the
stand-by waveforms and characteristics.

Address access time, tA, is the time required for an
address change to produce new data at the output pin,
assuming CE has enabled the output buffer prior to data
arrival. Chip Enable-to-output delay, teo, is the time
required for CE to enable the output buffer and transfer
previously fetched data to the output pin. Operation
with CE continuously held low is permissible.
WR ITE-cycle timing is shown in the section on Switching
Time Waveforms. Writing occurs only during the time

Block Diagram
18

+-0

A2
(LSB)

VCC

9

.--0 GNO
A3

AD
ROW SELECT
1 OF 64

MEMORY ARRAY
64 ROWS
64 COLUMNS

OATAIN
CONTROL

COLUMN I/O CIRCUITS

A1

A6

A7
(MSB)

01

DO

COLUMN SELECT

REAO/WRITE
CONTROL

A11
(MSB)

A1D

A9

1-16

A8

A5

A4
(LSB)

Absolute Maximum Ratings

Operating Conditions

Voltage on Any Pin Relative to Vss
Storage Temperature Range
Power Dissipation
Short-Circuit Output Current
Lead Temperature (Soldering, 10 seconds)

Supply Voltage (VCC)
Ambient Temperature (T A)

-0.3V to +7V
-65°C to +150°C
1W
50mA
300°C

DC Electrical Characteristics

SYMBOL

MIN
4.75
0

MAX
5.25
+70

UNITS
V
°c

T A = o°c to +70°C, vcc = 5V ±5%

PARAMETER

MM5257
MM5257-2
MM5257-25
MM5257-3
MAX
MIN

CONDITIONS

MM5257-L
MM5257-2L
MM5257-25L
MM5257-3L
MIN
MAX

UNITS

VIH

Logical "1" Input Voltage

2.0

VCC

2.0

VCC

V

VIL

Logical "0" Input Voltage

-0.5

0.8

-0.5

0.8

V

VOH

Logical "1" Output Voltage

VOL

Logical

III

Input Load Current

"a" Output Voltage

IOH = -200pA

2.4

2.4

IOL = 2.1 mA

V

0.4

VIN = 0 to 5.25V

-10

-10

10

-10

10

-10

0.4

V

10

pA

ILO

Output Leakage Current

Vo = 4V to O.4V, CE = VIH

10

pA

ICC

Power Supply Current

All Inputs = 5.25V, T A = 25°C

80

55

mA

ICC

Power Supply Current

All Inputs = 5.25V, T A = O°C

90

65

mA

AC Electrical Characteristics
SYMBOL

PARAMETER

T A = o°c to +70°C, vcc = 5V ±5%, (Note 2)
MM5257-2
MM5257-2L
MIN
MAX

MM5257-25
MM5257-25L
MIN
MAX

MM5257-3
MM5257-3L
MIN
MAX

MM5257
MM5257-L
MIN
MAX

200

250

300

450

UNITS

READ CYCLE
tRC

Read Cycle Time (WE = VIH)

ns

tA

Access Time

200

250

300

450

ns

tco

Chip Enable to Output Valid

80

100

150

200

ns

100

ns

tCOT

Chip Enable to Output TRI-STATE

0

tOHA

Output Hold from Address Change

30

60

0

70

0

80

0

30

30

30

ns

WRITE CYCLE
twc

Write Cycle Time

200

250

300

450

ns

twp

Write Pulse Width

100

100

150

200

ns

twR

Write Recovery Time

a

a

a

a

ns

tDS

Data Set-Up Time

85

85

120

175

ns

tDH

Data Hold Time

a

tWOT

Write Enable to Output TRI-STATE

0

two

Write Enable to Output Valid

a

0
80
80

0

80
80

0

100
100

a
a

ns
120

ns

120

ns

Note 1: Typical values at T A = 25° C.
Note 2: All input transitions:; 10 ns. Timing referenced to VIL(MAX) or VIH(MIN) for inputs, 0.8V and 2V for output. For test
purposes, input levels should swing between OV and 3V. Output load = 1 TTL gate and CL = 50 pF.

1-17

Switching Time Waveforms

Read Cycle
1 - - - - - - - - - ' t R C - - - - - : - - - - - l - - - - - - - - - - t R C ------~

AODRESSES

VIH
VIL

WRITE ENABLE
(NOTE 3)

VIH
VIL

-tA-tOHA-

CHIP ENABLE

VIH
VIL

DATA OUT

-

-

-

-

-OPEN- -

-OPEN- -

-

Write Cycle

ADDRESSES

VIH
VIL

twp (NOTE 4)
CHIP SELECT
(NOTE 5)

VIH

WRITE ENABLE
(NOTE 5)

VIH

DATA IN

VIL

VIL

VIH
VIL

DATA OUT

2.0

-

OPEN--

~~

VALID

O.B

Note 3: WE is high during a read cycle (WE? VIH(MIN)1.
Note 4: twp defines the period when both CE and WE are low. tAW is referenced to the later of CE or ~ gOing low while tDS. tDH
and tWR are referenced to the earlier of CE orWE going high. twOT and two are referenced to WE with CE low.
Note 5: Either WE orCE (or both) must be high during address transitions to prevent erroneous write.

1-18

Standby Characteristics

SYMBOL

T A : 0° C to +70° C

PARAMETER

CONDITIONS

MM5257
MM5257·2
MM5257·25
MM5257·3
MAX
MIN

MM5257·L
MM5257·2L
MM5257·25L
MM5257·3L
MAX
MIN

UNITS

1.5

1.5

V

2.0

2.0

V

VPD

VPD

V

VPD

VCC in Stand·by

VCES

CE Bias in Stand·by

2 ~ VPD ~ VCC(MAX)

VCES

CE Bias in Stand-by

1.5 ~ VPD ~ 2

IPDl

Stand·by Current

All Inputs: VPD : 1.5V

70

45

mA

IPD2

Stand·by Current

All Inputs: VPD : 2V

75

50

mA

tcp

Chip Deselect to Stand·by Time

0

0

ns

tR

Recovery Time

tRC

tRC

ns

CAPACITANCE TA: 25~C, f : 1 MHz, (Note 6)
CIN

Input Capacitance

All Inputs VIN : OV

5

5

pF

COUT

Output Capacitance

VO: OV

10

10

pF

Note 6: This parameter is guaranteed by periodic testing.

Standby Waveforms

VeES

CE
VIL
Vee
Vee

)4::5V~

1':,~5V

VpD

j

1·19

s:
s:
(II
I\)
(II

~

r-

~

3--

~

D..

.
~
,... ~National
,...
~ Semiconductor

NMOS RAMs
PREVIEW

N

o
:E
z..

~
,...
,...
N
o
:E
z

NMC2114A, NMC2114AP 4096·Bit (1024 x 4) Static RAMs
General Description

Features

These 1024-word by 4-bit static random access memories
are fabricated using N-channel silicon-gate technology_
All internal circuits are fully static and therefore require
no clocks or refreshing for operation_ The data is read out
nondestructively and has the same polarity as the input
data. Common input/output pins are provided.

•. All inputs and outputs directly TTL compatible
• Static operation-no clocks or refreshing required
• Low power-225 mW typical
• High speed"7'120 ns max access time
• TRI-STATE" output for bus interface
• Common Data In and Data Out pins
• Single 5V supply
• Power down option-NMC2114AP

The separate chip select input allows easy memory expansion by OR-tying individual devices to a data bus and
automatically powers down the NMC2114AP.

Block Diagram*

Connection Diagram*
Dual-ln·Line Package
.-J!..oVCC

A3

lB
A6

...-!.oVSS

11

A5

A4

AS
ROW
SELECT

Order Number
NMC2114AJ or
NMC2114APJ
See NS Package J18A

MEMORY ARRAY
64 ROWS
64 COLUMNS

A4

15
A3

A8

Order Number
Al
NMC2114AN or
A2
NMC2114APN
_
See NS Package N18A B (SI

16

1/01
(0011

14

1/02
(0021

13

1/03
(0031

12

1104
(0041

11

A9

14 1/01
(0011
13 1102
(0021
12 1/03
(0031
11 1/04
(0041

A6

A7

A7

16 AB

AD

17

vcc

10

vss

i/iE(WI

TOP VIEW
COLUMN 110 CIRCUITS

Logic Symbol *
1/01
(0011
AI
A2
A3

A4
AS
A6

A9

ES

CS
(S)

8

WE 1104
(WI(004)

(SI
Pin Names*
WE

10

(WI

* The symbols in parentheses are proposed industry standard.
1-20

AO·A9

Address Inputs

WE(W)

Write Enable

Cs(S)

Chip Select

1/01-1104 (OQ1-0Q4)

Data Input/Output

Operating Conditions

Absolute Maximum Ratings
Voltage at Any Pin with Respect to VSS
Storage Temperature

-1.5Vto +7V

Ambient Temperature (TA)

-65'Cto +150'C

Temperature with Bias

Units

Min

Max

4.5

5.5

V

+70

'C

0

-10'Cto +85'C
20mA

DC Output Current
Power Dissipation

1.2W

Lead Temperature (Soldering, 10 seconds)

300'C

DC Electrical Characteristics TA = O°C to
Symbol

Supply Voltage (VCC)

+ 70°C, VCC = 5V ± 10%
NMC2114A

Parameter

Conditions

Min

Max

NMC2114AP
Min

Max

Units

III

Input Load Current
(All Input Pins)

VIN = OV to 5.5V

10

10

/LA

IILOI

I/O Leakage Current

CS=2.4V,
VI/O = O.4V to VCC

10

10

/LA

ICC1

Power Supply Current

VIN =5.5V, 11/0=0 mA,
TA=25°C

45

45

mA

ICC2

Power Supply Current

VIN = 5.5V, 11/0 = 0 mA,
TA=O°C

50

50

mA
V

-1.0

0.8

-1.0

0.8

2.0

6.0

2.0

6.0

VIL

Input Low Voltage

VIH

Input High Voltage

10L

Output Low Current

VOL = O.4V

10H

Output High Current

VOH =2.4V

-4.0

lOS

Output Short Circuit Current

VI/O = VSS to VCC
(Note 1)

-120

IS8

Standby Current

VCC = Min to Max,
CS=VIH

IPO

Peak Power-On Current

VCC = VSS to VCC Min
CS = Lower of VCC or
VIH Min

8.0

8.0

V
mA

-4.0

mA
120

mA

ICC

15

mA

ICC

15

mA

120

-120

Capacitance TA=25°C, f= 1.0 MHz (Note 2)
Symbol

Parameter

NMC2114A
Min
Max

Conditions

NMC2114AP
Max
Min

Units

CliO

Input/Output Capacitance

VIIO=OV

10

10

pF

CIN

Input Capacitance

VIN=OV

5

5

pF

AC Test Conditions (Note 3)
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load

0.8V t02.4V
:510 ns
1.5V
1 TILGateandCL= 100pF

-

Note 1: Maximum duration of 60 seconds.
Note 2: This parameter is guaranteed by periodic testing.
Note 3: These circuits require 500 P.s time delay after VCC reaches the specified minimum limit to ensure proper operation after power on. This aliows the internaliy generated substrate bias to reach its functional level.

1-21

III

c..
~

,....
,....
C\I

CJ

:!:

Read Cycle AC Electrical Characteristics TA=O°C to
Symbol
Alternate
Standard

Parameter

t RC

TAVAV

Read Cycle Time

tA

TAVQV

Address Access Time

tco

TSLQV

Chip Select Access Time
(Notes 4 and 5)

tcx

TSLQX

Chip Select to Output Active

toTO

TSHQZ

Chip Select to Output TRI-STATE@

CJ

tOHA

TAXQX

Output Hold from Address Change

z

tpu

TSLICCH

Chip Select to Power Up

tpD

TSHICCL

Chip Select to Power Down

z...
~
,....
,....
C\I

:E

+70°C, VCC=5V ±10%

NMC2114A
Min
Max

NMC2114AP
Min
Max

120

120

Units
ns

120

120

ns

70

120

ns

20

20
60

ns
60

10

10

ns
ns

0

ns
60

ns

Read Cycle Waveforms·
Read Cycle 1 (Continuous Selection

CS =VIL, WE =VIH)

IRC
(TAVAV)
ADDRESS

I

~~
IA
(TAVOV)

Read Cycle 2 (Chip Select Switched,

CHIP SELECTZ

--1f-

CHIP SELECT 1

~ .....

-*

I

WE = VIH) (Note 5)

-\-

I~---------(TA~;V)-------------<-I

_
DATA OUT

____

,l

~~~~~I~CX~:(T:~:~~:~i)~~~~~*=I======~~~~======~--W:~~)
(TSLOX)

DATA VALID

HIIGH IMPEDANtCE tpu

ICC _ _ _ _ _ _ _ _
VCC
SUPPLY
CURRENT

I

(TSLICCH)

\}---~~=~~tPD HIGH~IMPEDANCE

--(TSHICCL)---

50%

50%

IS8 - - - - - - - - - - - - -

----

Note 4: This parameter Is Increa::ed by 10 ns for the NMC2114AP if the device is deselected for less than 55 ns.
Note 5: Addresses must be valid coincident with or prior to the chip select transition from high to low for the NMC2114AP. Addresses must be valid 50 ns or
more prior to the chip select transition from high to low for the NMC2114A.

* Symbols In parentheses are proposed industry standard.

1-22

Write Cycle AC Electrical Characteristics

(Note 6) TA

=o·e to

+ 70·e,

vee

=5V

± 10%

z
s:
o
.....
.....
I\)

Symbol
Alternate
Standard

NMC2114A

Parameter

Min

NMC2114AP
Min
Max

Max

Units

120

120

ns

0

0

ns

Write Time

60

60

ns

Write Recovery Time

10

10

ns

Data Set-Up Time

50

50

ns

TWHDX

Data Hold Time

10

TWLQZ

Write Enable to Output TRI-STATE

twc

TAVAV

Write Cycle Time

tAs

TAVSL
TAVWL

Address Set-Up Time

tw

TWLWL

tWR

TWHAX

tow

TDVWH

tOH
tOTW

Write Cycle Waveforms*

twc
(TAVAV)

I-'IWHAM

~ ~"-"-"""""""

tw
(TWLWL)

~~r

-,'I
J

I
DATA OUT

.y

.:::::«

,f-

~ ~"""''''''''''''

WRITE ENABLE

ns

tWR

-(T~e~L)CHIP SELECT

60

(Note 7)

~

ADDRESS

ns

10
60

<'>:«~:0.':
II

~«~

I

CS and WE.
CS low transition and the WE low transition occur simultaneously. WE or CS or both must be high

Note 6: A write occurs during the coincidence low of
Note 7: The butputs remain in TRI-STATE if the

)-j

tOH
(TWHOX)

during the address transitions.

* Symbols in parentheses are proposed industry standard.

1-23

~
Z

s:
o
I\)
.....
.....

~

"tJ

~National

NMOS RAMs
PREVIEW

U Semiconductor

NMC2141, NMC5257A 4096·Bit (4096 x 1) Static RAMs

,...
~
,...

oN
:E
z

General Description

Features

These 4096·word by 1·bit static random access memories
are fabricated using N·channel silicon·gate technology.
All internal circuits are fully static and therefore require
no clocks or refreshing for operation. The data is read out
nondestructively and has the same polarity as the input
data. Separate input/output pins are provided.

• All inputs and outputs directly TTL compatible
• Static operation-no clocks or refreshing required

The separate chip select input allows easy memory ex·
pal1,sion by OR·tying individual devices to a data bus and
automatic~lIy powers down the NMC2141.

•
•
•
•

Low power-225 mW typical
High speed-120 ns max access time
TRI-STATE® output for bus interface
Common Data In and Data Out pins

• Single 5V supp)y
• Power down option-NMC2141

Block Diagra,n*

Connection

Diagr~m*

Dual·ln·Line Package
18

AD

4vcc

AD

VCC

AI

9

.........a vss

A2

AI

Order Number
NMC2141J or
NMC5257AJ NS
See NS Package
NumberJ18A

A2
MEMORY ARRAY
64 ROWS
64 COLUMNS

ROWSELECT •
A3

Order Number
NMC2141N or
NMC5257AN NS
See NS Package
Number N18A

A4

AS

A3
A4

NMC2141
NMCS2S7A

AS

TOP VIEW

Logic Symbol*
COLUMN I/O CIRCUITS

DOUT
{Q}

COLUMN SELECT

A6

A7

A9

A8

AID

Pin Names·
AD·All

All Inputs

WE (W)

Write Enable

CS (S)

Chip Select

DIN (D)

Data Input

DOUT (0)

Data Output

* The symbols in parentheses are proposed Industry standard.
1·24

All

Absolute Maximum Ratings

.operating Conditions

Voltage at Any Pin with Respectto VSS

Supply Voltage (VCC)

-1.5Vto +7V

Storage Temperature

-65'Cto +150'C

Temperature with Bias

-10'Cto +85'C

Power Dissipation

20mA
1.2W

Lead Temperature (Soldering, 10 seconds)

300'C

DC Output Current

DC Electrical Characteristics TA=O·C to

AmbientTemperature(TA)

Min

Max

4.5

5.5

V

+70

'C

0

Units

z
s:
(")
I\)
.....
~
.....

z
s:
(")
(J1

+70·C, VCC=5V±10%

I\)
(J1

Symbol

Parameter

NMC5257A
Max
Min

Conditions

NMC2141
Min
Max

Units

ill

Input Load Current
(All input Pins)

VIN = OV to 5.5V

10

10

p.A

IILOI

Output Leakage Current

CS=2AV,
VOUT = OAV to VCC

10

10

p.A

ICC1

Power Supply Current

VIN=5.5V,
TA = 25·C Output Open

45

45

mA

ICC2

Power Supply Current

VIN =5.5V,
TA = O·C Output Open

50

50

mA

VIL

Input Low Voltage

-1.0

0.8

-1.0

0.8

V

VIH

input High Voltage

2.0

6.0

2.0

6.0

10L

Output Low Current

VOL=OAV

8.0

10H

Output High Current

VOH =2AV

-4.0

lOS

Output Short Circuit Current

VOUT = VSS to VCC
(Note 1)

-120

IS8

Standby Current

VCC = Min to Max,
CS=VIH

IPO

Peak Power-On
Current

VCC = VSS to VCC Min
CS = Lower of VCC or
VIH Min

8.0
-4.0
120

V
mA
mA

-120

120

mA

ICC

15

mA

ICC

15

mA

Capacitance TA=25·C, f= 1.0 MHz (Note 2)
Symbol

Parameter

NMC5257A
Min
Max

Conditions

NMC2141
Min
Max

Units

COUT

Output Capacitance

VOUT=OV

6

5

pF

CIN

Input Capacitance

VIN =OV

5

5

pF

AC Test Conditions (Note 3)
Input Pulse Levels
NMC2141
NMC5257A
Input Rise and Fall Times
input and Output Timing Levels
Output Load

GNDt03.5V
0.8Vto2AV
s10ns
1.5V
1 ITLGateandCL= 100pF

Note 1: Maximum duration of 60 seconds.
Note 2: This parameter is guaranteed by periodic testing.
Note 3: These circuits require 500 p's time delay after VCC reaches the specified minimum lim:. to ensure proper operation after power on. This allows the internally generated substrate biaS to reach its functional level.'

1-25

».......

Read Cycle AC Electrical CharacteristicsTA=o·Cto +70·C, VCC=5V
Symbol
Alternate
Standard

,...
~
,...
C\I

o

~

z

Parameter

tRc

TAVAV

Read Cycle Time

tAA

TAVQV

Address Access Time

tAcs

TSLQV

Chip Select Access Time
(Notes 4 and 5)

tLZ

TSLQX

Chip Select to Output Active

tHZ

TSHQZ

Chip Select to Output TRI-STATE

tOH

TAXQX

Output Hold from Address Change

t pu

TSLICCH

Chip Select to Power Up

tpD

TSHICCL

Chip Select to Power Down

±10%

NMC5257A
Min
Max

NMC2141
Min
Max

120

120

Units

ns

120

120

ns

70

120

ns

20

20
60

ns
60

10

10

ns
ns

0

ns
60

ns

Read Cycle Waveforms *

Read Cycle 1 (Continuous Selection

CS =VIL, WE = VIH)

tRC
\IAVAVI

ADDRESS ~I?

-

DATA DUT

tAA
(TAVQV)

-*

I

.m\'i<~~J.
tOH 1--1
t---(TAXQX)

Read Cycle 2 (Chip Select Switched, WE = VIH) (Note 5)

tRC
(TAVAV)
CHIP SElECT"~,-

DATA OUT

,'-

I-(T;t~X)
HIGH IMPEDANCE

I

~'"

ICC ________
VCC
SUPPLY
CURRENT ISB

tACS
(TSLQV)

I

I~'

DATA VALID

-(~~~QZ)
HIGH IMPEDANCE

., ~

-(TSHICCL)'"

(TSLICCH)

50%

50%

Note 4: This parameter is increased by 10 ns for the NMC2141lf the device is deselected for less than 55 ns.
Note 5: Addresses must be valid coincident with or prior to the chip select transition from high to low for the NMC2141. Addresses must be valid 50 ns or more

prior to the chip select transition from high to low for the NMC5257A.

* Symbols in parentheses are proposed industry standard.

1-26

Write Cycle AC Electrical Characteristics (Note 6) TA=O·C to
Symbol
Alternate
Standard

Parameter

t RC

TAVAV

Write Cycle Time

t AS

TAVSL
TAVWL

Address Set-Up Time

twp

TWLWL

Write Pulse Width

+70·C, VCC=5V ± 10%

NMC5257A
Min
Max

NMC2141
Max
Min

120

120

ns

0

0

ns

60

60

ns

Units

tWR

TWHAX

Write Recovery Time

10

10

ns

tow

TDVWH

Data Set-Up Time

50

50

ns

tOH

TWHDX

Data Hold Time

10

10

ns

twz

TWLQZ

Write Enable to Output TRI-STATE

tow

TWHQX

Write Enable to Output Active

tcw

TSLWH

tAW

TAVWH

60

60

ns

5

5

ns

Chip Select to End of Write

110

110

ns

Address Valid to End of Write

110

110

ns

Write Cycle Waveforms *

(Note 7)
Write Cycle 1 (Write Enable limited)
'WC
(TAVAV)

ADDRESS

~f-

-ct

-

~-

ICW
(TSLWH)

-.

lAS
(TAVWL)

I.

lAW

'WR

\'t'VVVMI

IIVVMAIlI

twp
(TWLWL)-

1

WRITE ENABLE

~

1!0

-yflOW
(TDVWH)

tDH
(TWHDX)

~~

-4-

DATA IN

-(~~liz)

\

~=ttow
(TWHQX)

HIGH IMPEDANCE

DATA OUT

,t,N

"
Write Cycle 2 (Chip Select Limited)

I

I

'Wc
(TAVAV)
ADDRESS

i

(TAV~~~-~

~ 'f-

[-

1-

ICW
(TSLWH)

~k-

-ltAW
(TAVWH)

I-(T~~~L)

WI\I'fEENABLE~~~~1\

(TW~:X) --

~~~~
tDH
(TWHDX)

IDW
(TDVWH)
DATA IN

~ 'f-

7~
'Wz
(TWLDZ)
HIGH IMPEDANCE

DATA OUT

Note 6: A write occurs during the coincidence low of CS and WE.
Note 7: The output remains TRI·STATE If the CS and WE go high simultaneously.

* Symbols in parentheses are proposed industry standard.
1-27

WE or CS or both must be high during the address transiticns.

z
3:
oC1I
I\)

c.n

~

c..

~
,...

~National

NMOS RAMs

PREVIEW
~ Semiconductor
o NMC2142A, NMC2142AP4096·Bit (1024 x 4) Static RAMs
:E
C\I

z

General Description

Features

~

These 1024-word by 4-bit static random access memories
are fabricated using N-channel silicon-gate technology.
All internal circuits are fully static and therefore require
no clocks or refreshing for operation. The data is read out
nondestructively and has the same polarity as the input
data. Common input/output pins are provided.

•
•
•
•
•
•
•
•

,...
C\I

o

:E

z

The separate chip select inputs allow easy memory expansion by OR-tying individual devices to a data bus and
automatically powers down the NMC2142AP..

All inputs and outputs directly TTL compatible
Static operation-no clocks or refreshing required
Low power-225 mW typical
High speed-120 ns max access time
TRI-STATE@ output for bus interface
Common Data In and Data Out pins
Single 5V supply
Power down option-NMC2142AP

Block Diagram*

Connection Diagram*
Dual·ln·L1ne Package

A3

~VCC

A6

+-.!.!!.o vss

AS

A4
A4
AS
ROW
SELECT

MEMORY ARRAY
64 ROWS
64 COLUMNS

A3

A6

S2

A7

A8

19

AD

18

AI

A2
1/01
(001)

IS

1/02
(002)

14

1/03
(003)

13

1/04
(004)

12

CSi (si)
11

VSS 10

~--------------~

WE
(W)

TOP VIEW

Order Number
NMC2142AJ or NMC2142APJ
See NS Package J20B
Order Number
NMC2142AN or NMC2142APN
See NS Package N20A

Lqgic Symbol*
CSi (S1)o----...-- tRCD(MAX).
Noto 11: Equivalent load is 2 standard TTL inputs plus 100 pF.
Noto 12: CAS going high disables the Data Output. tOFF is the delay to the high impedance state.
Noto 13: These parameters are referenced to the negative edge of CAS in an early-write cycle and to the negative edge of WE in a Read-ModifyWrite cycle. (See Note 12).
Noto 14: If twcs ~ tWCS(MIN), the Data Output is guaranteed to remain in the high impedance state for the duration of the cycle. This is the
"early-write" cycle.
Note 15: If tCWD ~ tCWD(MIN) and tRWD ~ tRWD(MIN), the Data Output will contain the original data in the selected cell. This is the ReadModify-Write cycle. If either of these conditions is not satisfied, the output will be indeterminate unless the early-write condition of Note 12 is met.

1-57

Switching Time Waveforms
Read Cycle

WE VIHCVil -

.......................""""'""+'...........**.1

----------------------OPEN----------------------~

Write Cycle (Early Write)

m

CAS

AD-A6

. VIHCVll-

VIHCVll-

VIHVll-

WE

01

DO

VIHCVll-

VIHVll-

VOH-

OPEN

VOL-

1-58

VALID
DATA

Switching Time Waveforms

3:
3:

(Continued)

CJ1
N
CO

Read-Write Cycle, Read-Modify-Write Cycle

AO-A6

o

VIHVll""'"

WI

DO

VIHC Vll-

VOH VOl-

01
RAS-Only Refresh Cycle

DO

VoHVOl-

Note. CAS

=

----------------oPEN---------------V I He, WE = don't care

1-59

o

~

Switching Time Waveforms

(Continued)

Lt)

~
~

Page Mode Read Cycle

RAS

VIHCVll-

CAS

AD-AS

VIHC Vll-

VIHVll-

VOHDO
VOl-

wt

Page Mode Write Cycle

WE

VIHCVll-

~~~~~~~~--~~~~~~~~~----~~~~~~P~~~~~-----4~~~~~~~~~

VIH01

Vll-

~~~::.:..:.;."

Note. Standard part not tested for page mode

1-60

~National

NMOS RAMs

~ Semiconductor

N
CO
CO

MM5298** 8192·Bit (8192 x 1) Dynamic RAM
General Description

Features

The MM5298 is an8192x 1-bitdynamic RAM. It features
a multiplexed address input with separate row and column strobes. This added flexibility allows the MM5298
to be used in page mode operation. The MM5298
employs the same masks and highly reliable productionproven 2-layer polysilicon NMOS technology as the
MM5290.

•

100% DC and AC compatible with MM5290

•

Only 64 Refresh cycles every 2 ms

•

Access Times: 150 ns, 200 ns, 250 ns

•

Low power: 528 mW max

•

TTL compatible: all inputs and output

•

Gated CAS-noncritical timing

•

Read, Write, Read-Modify-Write and RAS-only
Refresh cycles

•

Page mode operation

•

Industry standard 16-pin configuration

As shown in the block diagram, the MM5298 is available
as either the upper or lower half of the MM5290_ Address
A5 selects the operating half. For MM5298A, A5 should
be low (V I U during row address hold time (tRAH). For
MM5298B, A5 should be high (VIH) during tRAH. The
MM5298 requires only 64 cycles of Refresh every 2 ms.
This can be accomplished by performing any cycle
which brings the RAS active including an RAS-only
cycle at each of the 64 row addresses used.

s:
s:
en

Block Diagram
ADAlA2-

VOO

VCC

VSS

Vas

~

~
sv

~

~
-sv

12V

GNO

01

III

AJA4ASA6ROW
CLOCKS
ROW
CLOCKS
MEMORY ARRAY
64 X 128
COLUMN
CLOCKS

r:c
SENSE AMPLIFIERS (128)

o

00

o

~

WRITE
CLOCKS

Connection Diagram

MEMORY ARRAY
64 X 128

Logic Diagram

Dual-In-Line Package
Vas

01

16 VSS

AD

IS

Al

14

WE

13

rn

ill
00

AJ

A2

A4
10

Al

9

VOO

RAS
CAS
WE
AO-A6
DI
DO

A2

01

A6

AD

Pin Names

00

AS*
VCC

VDD
VCC
VSS
VBB

Row Address Strobe
Column Address Strobe
Write Enable
Address Inputs
Data Input
Data Output
Power (12VI
Power (5VI
Ground
Power (-5VI

Order Number MM5298AJ-2, MM5298BJ-2,
MM5298AJ-3, MM5298BJ-3,
MM5298AJ-4 or MM5298BJ-4
See NS Package J16A
Order Number MM5298AN-2, MM5298BN-2,
MM5298AN-3, MM5298BN-3,
MM5298AN-4 or MM5298BN-4
See NS Package N 16A

TOP VIEW

*For MM5298A A5 must be at VIL during tRAH'
For MM5298B A5 must be at VIH during tRAH.
** See the MST
Program pag~ 3.

™

1-61

Absolute Maximum Ratings
Storage Temperature
Power Dissipation
Voltage on Any Pin Relative to VBB

(Note 1)
-65°C to +150°C

lW
-0.3V to +20V

(VSS - VBB ~ 4.5V)
Lead Temperature (Soldering, 10 seconds)

300°C

Recommended DC Operating Conditions
SYMBOL

MIN

PARAMETER

TA

Ambient Temperature

VDD

Supply Voltages

0

VCC

MAX

UNITS

70

°c

NOTES

10.8

13.2

V

2, 3

4.5

5.5

V

2,3

VSS

0

0

V

2,3

VBB

-4.5

-5.5

V

2, 3
2

VIHC

Input High Voltage, RAS, CAS, WE

2.7

7.0

V

VIH

Input High Voltage"AO-A6, 01

2.4

7.0

V

2

VIL

Input Low Voltage, All Inputs

-1.0

0.8

V

2

DC Electrical Characteristics
SYMBOL

Over the range of Recommended DC Operating Conditions unless otherwise noted

PARAMETER

MIN

MAX

UNITS

1001

Operating Current

ICCl

Average Power Supply Operating Current

IBBl

(RAS,

1002

Standby Current

ICC2

Power Supply Standby Current (RAS = VIHC,

IBB2

00= High Impedance)

1003

Refresh Current

ICC3

Average Power Supply Current, Refresh Mode

IBB3

(RAS Cycling, CAS = VIHC; tRC';' tRC MIN)

1004

Page Mode Current

ICC4

Average Power Supply Current, Page Mode

IBB4

(R'AS = V I L, CAS Cycling; tpc = 225 ns)

200

/1 A

II(L)

Input Leakage

-10

10

/1 A

-10

10

/1A

CAS Cycling; tRC =

40

mA

200

Il A

1.5

mA

NOTES
4
5

tRC MIN)

-10

-10

10

IlA

100

Il A

30

mA

10
200

/1 A
/1 A

32

mA

4

4
5

Input Leakage Current, Any Input
(VBB = -5V, OV -:::; VIN -:::; 7V; All Other
Pins not Under Test = OV)
IO(L)

Output Leakage
Output Leakage Current (DO is Disabled,
OV -:::; VOUT -:::; 5.5V)
Output Levels

VOH

Output High Voltage (lOUT = -5 mAl

VOL

Output Low Voltage (lOUT = 4.2 mAl

0.4

V

CI

Input Capacitance AO-A6, 01

5

pF

6

Cc

Input Capacitance RAS, CAS, WE

10

pF

6

Co

Output Capacitance, DO

7

pF

6

2.4

V

CAPACITANCE

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Recommended OC Operating
Conditions" provides conditions for actual device operation.
Note 2: All voltages referenced to VSS' When applying voltages to the device, VOO, VCC or VSS should never be O.3V more negative than VBB.
Note 3: Several cycles are required after power-up before proper device operation is achieved. Any 8 RAS cycles are adequate for this purpose.
Note 4: 1001,1003, and 1004 depend on cycle rate.
Note 5: ICC depends on output load.
Note 6: Capacitance measured with Boonton Meter or effective capacitance calculated from the equation C = It:.t/t:.V. Capacitance is guaranteed
by periodic testing.

1-62

AC Electrical Characteristics
Over the range of Recommended DC Operating Conditions unless otherwise noted

PARAMETER

SYMBOL

MM5298-2A,
MM6298-2B
MAX

MIN

MM5298-3A,
MM5298-3B
MIN

MAX

MM5298-4A,
MM5298-4B
MIN

UNITS

NOTES

MAX

tRC

Random Read or Write Cycle Time

375

375

410

ns

7,8

tRWC

Read-Write Cycle Time

375

375

515

ns

7,8

tpc

Page Mode Cycle Time

170

225

275

ns

tRAC

Access Time from RAS

150

200

250

ns

tCAC

Access Time from CAS

100

135

165

ns

10,11

tOFF

Output Buffer Turn-Off Delay

0

40

0

50

0

60

ns

12

tT

Transition Time (Rise and Fall)

3

35

3

50

3

50

ns

tRP

RAS Precharge Time

100

tRAS

150

tRCD

RAS Pulse Width
RAS Hold Time
CAS Pulse Width
RAS to CAS Delay Time

tCRP

CAS to RAS Precharge Time

tASR
tRAH
tASC

Column Address Set-Up Time

tCAH

Column Address Hold Time

tAR

Column Address Hold Time Referenced to RAS

95

tRCS

Read Command Set-Up Time

0

tRCH

Read Command Hold Time

0

tWCH

Write Command Hold Time

tWCR

tRSH
tCAS

120
10,000

100

200
135

100

10,000

20

50

ns

150
10,000

250

10,000

ns

10,000

ns

ns

165

135

10,000

25

65

165

9,11

35

85

9

-20

Row Address Set-Up Time

0

0

0

ns

Row Address Hold Time

20

25

35

ns

-10

-10

-10

ns

45

55

75

ns

120

160

ns

0

0

ns

0

0

ns

45

55

75

ns

Write Command Hold Time Referenced to RAS

95

120

160

ns

twP

Write Command Pulse Width

45

55

75

ns

tRWL

Write Command to RAS Lead Time

60

80

100

ns

tCWL

Write Command to CAS Lead Time

60

80-

100

ns

tDS

Data-In Set-Up Time

0

0

0

ns

13,14

tDH

Data-In Hold Time

45

55

75

ns

13,14

tDHR

Data-In Hold Time Referenced to RAS

95

120

160

ns

tcp

CAS Precharge Time (for Page Mode

60

80

100

ns

-

-20

ns

-20

ns

Cycle Only)
tREF

Refresh Period

twcs

WE to CAS Set-Up Time

tCWD

CAS to

WE

-

-

tRWD

Delay

RAS to WE Delay

2

2

2
-40

ms

-40

-40

70

95

125

ns

15

120

160

200

ns

15

ns

14

Note 7: The specifications for tRC(MIN) and tRWC(MIN) are used only to indicate cycle time at which proper operation over the full temperature range is guaranteed.
Note 8: Transition times are measured between VIHC or VIH and V,L' Timing measurements are made between V'HC(M'N) or VIH(MIN) and
VIL(MAX), and assume tT = 5 ns.
Note 9: Assumes row-limited access, i.e_, tRCD :S. tRCD(MAX). If this condition is not satisfied, then note 10 applies_
Note 10: Assumes column-limited access, Le., tRCD > tRCD(MAXI.
Note 11: Equivalent load is 2 standard TTL inputs plus 100 pF.
Note 12: CAS going high disables the Data Output. tOFF is the delay to the high impedance state.
Note 13: These parameters are referenced to the negative edge of CAS in an early-write cycle and to the negative edge of WE in a Read-ModifyWrite cycle. (See Note 14 belowl.
Note 14: If twcs ~ tWCS(MINl, the Data Output is guaranteed to remain in the high impedance state for the duration of the cycle. This is the
"early-write" cycle.
Note 16: If tCWD ~ tCWD(MIN) and tRWD ~ tRWO(MIN), the Data Output will contain the original data in the selected cell. This is the ReadModify-Write cycle. If either of these conditions is not satisfied, the output will be indeterminate unless the early-write condition of Note 12 is met.

1-63

Switching Time Waveforms
Read Cycle

WE VIHCVI L-

DD VOHVOL -

""""""'"''"''4''''''''~

-----------OPEN------------

Write C.ycle (Early Write)

rn

VIHC-

rn

VIHC-

AD-A6

W£

DI

VIL-

VIL-

VIHVIL-

VIHCVIL-

VIHVIL -

DO

VOH-

DPEN

VOL -

1·64

VALID
DATA

Switching Time Waveforms

(Continued)

Read-Write Cycle, Read-Modify-Write Cycle

lIAS

CAS

VIHCVll-

VIHC Vll-

AD-A6

VIHVll-

WI

DO

VIHC Vll-

VOH VOl-

RAS-Only Refresh Cycle

m

VIHC-

VIl-

.

tASR

VIHAD-A6

.
'"'""'''"'~;..:.:.:.....,

.

Vil -

DO

VDHVOl-

Note. CAS

-----------------DPEN-----------------

= VIHC, WE = don't care

1-65

I

Switching Time Waveforms

(Continued)

In

:E
:E

Page Mode Read Cycle

VIH-

AD-A6

VIL-

VOH-

00

VOL-

Page Mode Write Cycle

VIH01

VIL _

~~~~;1

1"'......-+----1

Note. Standard part not tested for page mode

1-66

~National

NMOS RAMs

ZIIII Semiconductor

PREVIEW

NMC4164t 65,536-Bit (65,536 x 1) Dynamic RAM
General Description

Features

The NMC4164 is a 65,536 x 1 bit dynamic RAM. It features a
multiplexed address input with separate row and column
strobes.

• Single 5V ± 10% supply
• 256 cycle 4 ms refresh
• Access times:
NMC4164-1
NMC4164-2

The NMC4164 must be refreshed every 4 ms. This can be
accomplished by performing any cycle which brings the
Row Address Strobe actlv'e including an RAS (RE)-only
cycle at each of the 256 row addresses.
N-channel triple-polysilicon gate technology, developed
by National, is used in the manufacture of the NMC4164.
This process combines high density and performance
with reliability.

120ns
150ns
250mW

•
•
•
•

Lowpower
TIL compatible: all inputs and output
Gated CE - noncritical timing
Read, write, read-modify-write and RAS (RE)-onIY
refresh cycles

•
•
•
•
•

Buried refresh option
Page mode operation
Industry standard 16-pin configuration
TRI-STATE@ output
On-chip substrate bias generator

Block and Connection Diagrams * *

16k ARRAY

16k ARRAY

1
OF
256
ROW
DEC

128 SENSE
AMPLIFIERS

+--(~I)

128 SENSE
AMPLIFIERS

16k ARRAY

16k ARRAY

1 OF 128
COL DECOOER

1 OF 128
COL DECODER

AD

A7

00
8UFFER

~r~

Dual·ln·Llne Package

Pin Names

Order Number NMC4164J·X·
See NS Package J16A
Order Number NMC4164N·X·
See NS Package N16A

TOP VIEW

tSee the MST™ Program page 3.
•• Symbols In parentheses are proposed Industry standard.
* X = Speed selection

1-67

RAS(RE)

Row Address Strobe

CAS(CE)

Column Address Strobe

WErN)
AO-A?

Write Enable

01(0)

Data Input

00(0)

vec

Data Output
Power(5V)

VSS

Ground

Address Inputs

Absolute Maximum Ratings (Note 1)
Operating Temperature Range
Storage Temperature
Power Dissipation

O·Cto + 70·C
- 65 ·C to + 150 ·C
1W

Voltage on Any Pin Relative to VSS
Lead Temperature (Soldering, 10 seconds)

-1.0to +7V
300·C

Recommended DC Operating Conditions
Symbol
TA

Parameter

Min

Max

Units

Notes

0

70

·C

4.5
0

5.5
0

V
V

2,3
2,3

Input High Voltage, All Inputs

2.4

7.0

V

2

Input Low Voltage, All Inputs

-1.0

0.8

V

2

Ambient Temperature

VCC
VSS

Supply Voltages

VIH
VIL

DC Electrical Characteristics
Over the range

of Recommended DC Operating Conditions unless otherwise noted

Symbol
ICC1

Parameter

Min

Operating Current
Average Power Supply Operating Current
(RE, BE Cycling; TRELREL TRELREL Min)

=

Max

Units

Notes

45

mA

4

4

mA

ICC2

Standby Current
Power Supply Standby Current (RE
a:= High Impedance)

ICC3

Refresh Current .
Average Power Supply Current, Refresh Mode
BE Cycling, BE VIH; TRELREL TRELREL Min)

35

mA

4

Page Mode Current
Average Power Supply Current, Page Mode
(RE VIL, BE Cycling; TCELCEL 100 ns)

37

mA

4

-10

10

p.A

-10

10

p.A

=

ICC4

=

=

II

10Z

=VIH,

=

Input Leakage
Input Leakage Current, Any Input
(OVsVIN s7V, All Other Pins not Under Test

=OV)

Output Leakage
Output Leakage Current (a is Disabled,
OV s VOUT s 5.5V)
Output Levels

= - 5 mA)
=4;2 mA)

VOH

Output High Voltage (lOUT

VOL

Output Low Voltage (lOUT

2.4

V
V

0.4

Capacitance
Symbol

Max

Units

Notes

CI

Input Capacitance AO-A6, D

Parameter

5

pF

5

CC

Input Capacitance RE, CE, W

10

pF

5

ca·

Output Capacitance,

7

pF

5

a

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature
Range" they are not meant to imply that the devices should be operated at these limits. The table of "Recommended DC Operating Conditions" provides con·
ditions for actual device operation.
Note 2: All voltages referenced to VSS. When applying voltages to the device, VCC should never be 1.0V more negative than VSS.
Note 3: Several cycles are required after power-up before proper device operation Is achieved. Any 8

RE cycles are adequate for this purpose.

Note 4: ICC1,ICC3 and ICC4 depend on cycle rate.
Note 5: Capacitance measured with Boonton Meter or effective capacitance calculated from the equation C = IAt/AV. Capacitance is guaranteed by periodic
testing.

1·68

Read Cycle AC Electrical Characteristics (Notes 1,2,3 and 4)
Symbol
Alternate Standard

Parameter

NMC4164·1
Max
Min

NMC4164·2
Max
Min
305

Units

tRC

TRELREL

Random Read Cycle Time

270

tRAS

TRELREH

RAS Pulse Width

140

tRP

TREHREL

RAS Precharge Time

120

tr

TH1H2

Rise Time

3

50

3

50

ns

tr

TL2L1

Fall Time

3

50

3

50

ns

tRCO

TRELCEL

RAS to CAS Delay Time

25

55

30

60

ns

TCELREH

RAS Hold Time

85
135

tRSH

10,000

ns

165

10,000

ns

130

ns

100
150

tCSH'

TRELCEH

CAS Hold Time

TCELCEH

CAS Pulse Width

80

tcp

TCEHCEL

CAS Precharge Time

70

80

ns

tAsR

TAVREL

Row Address Set·Up Time

0

0

ns

20

25

ns

0

0

ns

100

ns
10,000

ns

tRAH

TRELAX

Row Address Hold Time

tASC

TAVCEL

Column Address Set-Up Time

tCAH

TCELAX

Column Address Hold Time

25

30

ns

tAR

TRELA(C)X

Column Address Hold Time Referenced
to RAS

80

90

ns

tRCS

TWHCEL

Read Command Set-Up Time

0

0

ns

tRCH

TCEHWX

Read Command Hold Time

0

0

tRAC

TRELQV

Access Time from RAS

tCAC

TCELQV

Access Time from CAS

tOFF

TCEHQZ

Output Buffer Turn-Off Delay

120
65
0

50

0

5

ns

tCAS

10,000

Notes

6

7

ns

8

150

ns

9, 10

90

ns

10, 11

55

ns

12

Read Cycle Waveforms·
_~IJI;.

II
ROW VIHADDRESS
STROBE VIL-

'RAS
IIHtLHtHI

'AR

'RP

IlntnntL,

HtLAI~IXI

0 3I\,G)

G)j

~

tTLZL1)-

\I

COLUMN VIHADDRESS
STROBE VIL-

'ASR

~
(TRE~RA~
ADDRESSES VIH VIL -

IltlElRElr

~

ADDRE:;S

~

-

-I

'CSH

HtL~tHI

\I

-

'RSH

~tLHtHI

'CAS

IrAI

(TCElAXI

Je

f

~::~~MN

'\c

'RCH
(TCEHWX:

'~t

(TWHC
WRITEVIH-~
ENABLE VIL ~

F4

J

~

'CAC

\I

DATA VOHOUT VDL-

"

~aHIHZ)

~

IIUL~tHI

f-;f1e, :El)

'0

lI~tLUVI

'RAC
HtLUVI

(TCE~o;k-j
It

Hi-Z

* Symbols In parentheses are proposed industry standard.
1-69

VALID
DATA

\.
¥-

Write Cycle AC Electrical Characteristics
Symbol
Alternate

Parameter

Standard

NMC4164·1

NMC4164·2

Min

Min

Max

Max

305

Units

twc

TRELREL

Random Write Cycle Time

270

tRM

TRELREH

RAS Pulse Width

140

tRP

TREHREL

RAS Precharge Time

120

tT

TH1H2

Rise Time

3

50

3

50

ns

tT

TL2L1

Fall 'rime

3

50

3

50

ns

tRCO

TRELCEL

RAS to CAS Delay Time

25

55

30

60

ns

tRSH

TCELREH

RAS Hold Time

85

100

tCSH

TRELCEH

CAS Hold Time

135

150

tCAS

TCELCEH

CAS Pulse Width

80

tcp

TCEHCEL

CAS Precharge Time

70

80

ns

tASR

TAVREL

Row Address Set·Up Time

0

0

ns

2b

25

ns

0

0

ns

10,000

165

ns
10,000

130

10,000

100

ns
ns

ns
ns
10,000

ns

tRAH

TRELAX

Row Address Hold Time

tAsC

TAVCEL

Column Address Set·Up Time

tCAH

TCELAX

Column Address Hold Time

25

30·

ns

tAR

TRELA(C)X

Column Address Hold Time Referenced
toRAS

80

90

ns

twcs

TWLCEL

WE to CAS Set·Up Time

tWCH

TCELWX

Write Command Hold Time

twp

TWLWH

Write Command Pulse Width

tCWL

TWLCEH

Write Command to CAS Lead Time

tRwL

TWLREH

Write Command to RAS Lead Time

90

100

ns

tWCR

TRELWX

Write Command Hold Time Referenced
to RAS

90

100

ns

tos

TDVCEL

Data In Set·Up Time

0

0

ns

tOH

TCELDX

Data In Hold Time

35

40

ns

tOHR

TRELDX

Data In Hold Time Referenced
to RAS

90

100

ns

0

0

ns

35

45

ns

40

45

ns

85

95

ns

Write Cycle (Early-Write) Waveforms· (Note 13)
'AR
"ntLA,.,.,
ROW VIHADDRESS
STRDBE VIL-

CDLUMN VIHADDRESS
STROBE VIL'ASR,
''',"HtL'l
VIHVIL-

..L ..'.R_A.H

:j

I "HtLAX'1

'RSH
"."HEHI

_'~S~
I"HtW n,

~
r-:::e,

:!.Ll

'CAS
".tL.tn,

r

'CAH
".tLAX,

...
•
A~~~:~~S

ADDRES

'wcs

'WCH
\I.tlWxI

'eWL

'Y/p
,"'L"HI

WRITEVIH-~

'RWL
,,"lHtHI

'Y/eR
ntL"AI

DATA VIHIN VIL-

'RP
"ntnntL/

1/

ITWleUI

ENABLE VIL-

L

I

~

'RCD
"ntL.tL,

ADDRESSES

'RC
"ntLntL,

'F AS
lint .HtHI

I~~~'~

(TDV;~~I-

-;-DHR
,ntLU.,

'DH
"UlUXI

DATA VOHDUT VOL-

Hi·Z

*Symbols In parentheses are proposed industry standard.
1-70

Notes

6

13

z

Read-Write and Read-Modify-Write Cycle AC Electrical Characteristics
Symbol
Alternate
Standard

NMC4164·1

Parameter

Min

Read-Write Cycle Time

345

TRELREH

RAS Pulse Width

215

TREHREL

RAS Precharge Time

120

NMC4164·2

Max

Min

Max

3:
Units

tRWC

TRELREL
(RIW)

tRAS
tRP
tT

TH1H2

Rise Time

3

50

3

50

ns

tT

TL2L1

Fall Time

3

50

3

50

ns

tRCO

TRELCEL

RAS to CAS Delay Time

25

55

30

60

ns

tRSH

TCELREH

RAS Hold Time

85

tCSH

TRELCEH

CAS Hold Time

135

tCAS

TCELCEH

CAS Pulse Width

160

tcp

TCEHCEL

CAS Precharge Time

tASR

TAVREL

Row Address Set·Up Time

385
10,000

245

10,000

Notes

ns

14

ns

14

ns

130

100

5

ns

150

ns
ns

14

70

80

ns

6

0

0

ns

20

25

ns

0

0

ns

10,000

185

10,000

tRAH

TRELAX

Row Address Hold Time

tASC

TAVCEL

Column Address Set·Up Time

tCAH

TCELAX

Column Address Hold Time

25

30

ns

tAR

TRELA(C)X

Column Address Hold Time Referenced
toRAS

80

90

ns

tRCS

TWHCEL

Read Command Set·Up Time

0

0

ns

twp

TWLWH

Write Command Pulse Width

40

45

ns

tcwL

TWLCEH

Write Command to CAS Lead Time

85

95

ns

tRWL

TWLREH

Write Command to RAS Lead Time

90

100

ns

tRWO

TRELWL

RAS to WE Delay

120

150

ns

tcwo

TCELWL

CAS to WE Delay

65

90

ns

tos

TDVWL

Data In Set·up Time

0

0

ns

35

13

tOH

TWLDX

Data In Hold Time

tRAC

TRELQV

Access Time from RAS

120

150

ns

9,10

tCAC

TCELQV

Access Time from CAS

65

90

ns

10,11

tOFF

TCEHQZ

Output Buffer Turn·Off Delay

55

ns

12

0

40

7

50

0

ns

Read-Write and Read-Modify-Write Waveforms·
f--------------ITREL'ttt.C{R/WIl----------------l
'RAS
(TRELREH)
ROW
ADDRESS
STROBE

fg~~:s~
STROBE

ADDRESSES

WRITE
ENABLE

VIHVIL-

VIHVIL-

VIHVIL-

VIH- ~WWX'l.;mWW1'
VIL ~~~~~~~

D~~~ ~~:

DATA
IN

=___4-_ _ _ __

VIHVIL-

* Symbols In parentheses are proposed industry standard.
1-71

0

.....

~

0')
~

RAS·Only Refresh and Buried Refresh AC Electrical Characteristics
Symbol
Alternate
Standard

NMC4164·1
Min
Max

Parameter

NMC4164·2
Min
Max

Units

TRELREL

Random Read or Write Cycle Time

270

TRELREH

RAS Pulse Width

140

TREHREL

RAS Precharge Time

120

TH1H2

Rise Time

3

50

3

50

ns

TL2L1

Fall Time

3

50

3

50

ns

55

30

60

TRELCEL

RAS to CAS Delay Time

25

TCELREH

RAS Hold Time

85
135

305
10,000

165

ns
10,000

ns
ns

130

100

ns

TRELCEH

CAS Hold Time

tCAS

TCELCEH

CAS Pulse Width

80

tcp

TCEHCEL

CAS Precharge Time

70

80

ns

TAVREL

Row Address Set·Up Time

o

o

ns

20

25

ns

o

o

ns

ns

150
100

10,00·0

ns

TRELAX

Row Address Hold Time

TAVCEL

Column Address Set-Up Time

TCELAX

Column Address Hold Time

25

30

ns

TRELA(C)X

Column Address Hold Time Referenced
to RAS

80

90

ns

o
o

o
o

ns

TWHCEL

Read Command Set-Up Time

TCEHWX

Read Command Hold Time

TRELQV

Access Time from RAS

120

tCAC

TCELQV

Access Time from CAS

tOFF

TCEHQZ

Output Buffer Turn-Off Delay

50

o

6

7

ns

8

ns

9,10

90

ns

10,11

55

ns

12

150

65

o

5

ns

tCSH

10,000

RAS·Only Refresh Waveforms· (CAS=VIH, WE = don't care)
f-----------(TR~~~ELI----------lJI
tRAS
(TRELREHI

I

tRP
(TREHRELI

I

ROW VIHADDRESS
STROBE VIL-

D~~~ ~~:=

-------_--------H;.Z-----------------

Buried Refresh Waveforms·

* Symbols in parentheses are proposed industry standard.
1·72

Notes

Page Mode Read Cycle AC Electrical Characteristics t
Symbol
Alternate

Parameter

Standard

tpc

TRELREL

tRAS

TRELREH

. Page Mode Cycle Time

NMC4164·1

NMC4164·2

Min

Max

Min

10,000

510

235

RAS Pulse Width

445
120

Units

Max

270
10,000

ns

14

ns

14

tRP

TREHREL

RAS Precharge Time

tr

TH1H2

Rise Time

3

50

3

50

ns

tr

TL2L1

Fall.Time

3

50

3

50

ns

tRCO

TRELCEL

RAS to CAS Delay Time

25

55

30

60

ns

tRSH

TCELREH

RAS Hold Time

85

tCSH

TRELCEH

CAS Hold Time

135

tCAS

TCELCEH

CAS Pulse Width

155

tcp

TCEHCEL

CAS Precharge Time, Page Mode

tASR

TAVREL

Row Address Set·Up Time

tRAH

TRELAX

Row Address Hold Time

tASC

TAVCEL

Column Address Set·Up Time

tCAH

TCELAX

Column Address Hold Time

tAR

TRELA(C)X

Column Address Hold Time Referenced
to RAS

130

ns

100

5

ns

150
10,000

Notes

180

10,000

ns

13

ns

14
6

70

80

ns

0

0

ns

20

25

ns

0

0

ns

25'

30

ns

80

90

ns

tRCS

TWHCEL

Read Command Set·Up Time

0

0

ns

twp

TWLWH

Write Command Pulse Width

40

45

ns

tCWL

TWLCEH

Write Command to CAS Lead Time

85

95

ns

tRWL

TWLREH

Write Command to RAS Lead Time

90

100

ns

tRWO

TRELWL

RAS to WE Delay

120

150

ns

tcwp

TCELWL

CAS to WE Delay

65

90

ns

0

0

ns

35

40

7

13

tos

TDVWL

Data In Set·Up Time

tOH

TWLDX

Data In Hold Time

tRAC

TRELQV

Access Time from RAS

120

150

ns

9, 10

tCAC

TCELQV

Access Time from CAS

65

90

ns

10, 11

tOFF

TCEHQZ

Output Buffer Turn·Off Delay

55

ns

12

50

0

ns

0

Page Mode Read Cycle Waveforms*
r(TR~~~EL)1

'RAS
(TRElREH)

. - (TRE'tA~C)X)ROW VIH- ~
ADDRESS
STROBE VIL-

(TR':t~El)

-

'CSH
(TRElCEH)
COLUMN VIHADDRESS
STROBE VIL

-(TRETA\~-

t--

~

".'L."

(TCElCEH)
e-.~'

i\

1- !~~~I-

I(TnAVC~l)

'--

~

~

iRAC

-(T~mV'

[ITRElnV)
DATA VOHOUT VOL-

'CAH

1- (TCElAX)

LAX)

I

It-- ~:~I ~lHHnZ)

(TWHCEl)

(TCE:rJ~)-

WRITE VIHENABLE Vll-

t Standard part not tested for page mode.
* Symbols In parentheses are proposed Industry standard.

r-.1

,_

(TCElnV)

"-- ~
'RC~-j _

~~l

jt .~
~~.C_

COL

r-~
r----, 'CAC

_

'RS~

'""Lntn,

~

\

I---

~~~
ii(max) (column limited timing). ,
Note 12: TCEHOZ Is measured to lOUT s IO(L).
Note 13: The placement of the negative going edge of Wwith respect to the negative edge of CAS determines the type of Write cycle. I! TWLCEL is greater than
o ns (negative edge of W before negative edge of CAS) the memory is In an Early-Write cycle and Data Out is TRI·STATE. If TCELWL is greater than
TCELWL(min) (negative edge of Wcoincident with or after Data Out valid) the memory Is In a Read-Write or Read-Modify·Write cycle and Data Out is the original contents of the selected cell. I! Wgoes LOW between these two times the cycle Is a Write cycle and Data Out is Indeterminate.
Note 14: (RIW) Indicates a Read-Write or Read-Modify-Wrlte cycle parameter.

1-76

National
~ Semiconductor
~

MOS RAMs
ADVANCE INFORMATION

NMC5295 t 16,384-Bit (16,384 x 1) Dynamic RAM

en

Features

The NMC5295 is a 16,384 x 1 bit dynamic RAM. It features
a multiplexed address input with separate row and column strobes. This added flexibility allows the NMC5295 to
be used in page mode operation.

•
•
•
•
•
•
•

Single 5V ± 10% supply
128 cycle, 2 ms refresh
Access times: 80 ns, 100 ns, 120 ns
Low power: 200 mW max
TTL compatible: all inputs and output
Gated CAS (CE)- non-critical timing
Read, write, read-modify-write and RAS (RE)-onIY
refresh cycles

•
•
•
•
•

Buried refresh option
Page mode operation
Industry standard 16-pin configuration
TRI-STATE~) output
On-chip substrate bias generator

N-channel triple-polysllicon gate technology, developed
by National, is used in the manufacture of the NMC5295.
This process combines high density and performance
with reliability. Greater system densities are achievable by
the use of a 16-pin dual-in-iine package for the NMC5295.

Block and Connection Diagrams * *

W(RE)----OI

ROW
TIMING

vcc

WRITE
TIMING

vss

11
ROW
LATCH

AIAD - ]
A2 -

01

+--01(0)

LATCH

ROW
DEC

A3 -

8k ARRAY

A4 A5 A6-

COL
LATCH

128 SENSE AMPS
AND COL DECODER

ROW
DEC

8k ARRAY

CAS (eE) - - - - Q COLUMN

+-+

1/0
CONTROL

&
BUFFER

TIMING

Dual-In-Llne Package

00(0)

NC

Pin Names

15 CAS(eE)

01 (D)

14 00 (0)

WE(W)

13

m(RE)

12

AD

II

A2

10

AI

9

VCC

Order Number NMC5295J-X·
See NS Package J16A

A6
A3

Order Number NMC5295N-X·
See NS Package N16A

A4
A5
NC

RAS(RE)
~AS(CE)

Row Address Strobe

'iiE(W)

Write Enable

AO-A6

Address Inputs

01(0)

Data Input

OO(Q)

Data Output

Column Address Strobe

VCC

Power (5V)

VSS

Ground

tSee the MST™ Program, page 3.
... Symbols in parentheses are proposed Industry standard.

TOP VIEW

* X = Speed selection
1-77

en
I\)

CD

General Description

The NMC5295 must be refreshed every 2 ms. This can be
accomplished by performing any cycle which brings the
Row Address Strobe active including RAS (RE)-only cycle
at each of the 128 row addresses.

z

s:
(')

II)

m

C\I

II)

o
:E
z

Absolute Maximum Ratings (Note 1)

\

O°Cto + 70°C
- 65°C to + 150°C
1W

Operating Temperature Range
Storage Temperature
Power Dissipation

-1.0to + 7V
300°C

Voltage on Any Pin Relative to VSS
Lead Temperature (Soldering, 10 seconds)

Recommended DC Operating Conditions
Symbol

Parameter

TA

Min

Ambient Temperature

vec

Supply Voltages

VSS

Max

Units

Notes

0

70

°C

4.5
0

5.5
0

V
V

2,3
2,3

VIH

Input High Voltage, All Inputs

2.4

7.0

V

2

VIL

Input Low Voltage, All Inputs

-1.0

0.8

V

2

DC Electrical Characteristics
Over the range of Recommended DC Operating Conditions unless otherwise noted.
Symbol

Parameter

ICC1

Max

Units

Notes

Operating Current
Average Power Supply Operating Current
CE Cycling; TRELREL TRELREL Min)

35

mA

4

Standby Current
Power Supply Standby Current
Q High Impedance)

4

mA

Refresh Current
Average Power Supply Current, Refresh Mode
(RE Cycling, CE VIH; TRELREL TRELREL Min)

.27

mA

4

Page Mode Current
Average Power Supply Current, Page Mode
(RE VIL, CE Cycling; TCELCEL 100 ns)

27

mA

4

-10

10

p.A

-10

10

p.A

(RE,

ICC2

=

=

ICC3

=

ICC4

Min

(RE =VIH,

=

=

=

Input Leakage
Input Leakage Current, Any Input
(OV:5 VI N:5 7V, All Other Pins not Under Test

II

=OV)

Output Leakage
Output Leakage Current (Q is Disabled,
OV :5 VOUT :5 5.5V)

IOZ

Output Levels

= - 5 mA)
=4.2 mA)

VOH

Output High Voltage (lOUT

VOL

Output Low Voltage (lOUT

2.4

V
0.4

V

Capacitance
Symbol

Parameter

Max

Units

Notes

CI

Input Capacitance AO-A6, D

5

pF

5

CC

Input Capacitance RE, CE, W

10

pF

5

CQ

Output Capacitance, Q

7

pF

5

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature
Range" they are not meant to imply that the devices should be operated at these limits. The table of "Recommended DC Operating Conditions" provides conditions for actual device operation.
Note 2: All voltages referenced to VSS. When applying voltage to the device, VCC should never be 1.0V more negative than VSS.
Note 3: Several cycles are required after power-up before proper device operation is aChieved. Any 8

RE cycles are adequate for this purpose.

Note 4: ICC1,ICC3 and ICC4 depend on cycle rate.
Note 5: CapaCitance measured with Boonton Meter or effective capacitance calculated fro,:" the equation C = 11l.WN. Capacitance is guaranteed by periodic
testing.

1-78

z

Read Cycle AC Electrical Characteristics (Notes 1,2,3 and 4)
Symbol
Alternate Standard

Parameter

3:

NMC5295·2
Min
Max

NMC5295·3
Min
Max

NMC5295·4
Min
Max

200

235

270

t AC

TRELREL

Random Read Cycle Time

t AAS

TRELREH

RAS Pulse Width

95

tAP

TREHREL

RAS Precharge Time

95

10,000

115

10,000

110

Units

10,000

ns
ns

tr

TH1H2

Rise Time

3

50

3

50

3

50

tT

TL2L1

Fall Time

3

50

3

50

3

50

ns

tACO

TRELCEL

RAS to CAS Delay Time

15

40

20

50

25

55

ns

t ASH

TCELREH

RAS Hold Time

55

tCSH

TRELCEH

CAS Hold Time

90

tCAS

TCELCEH

CAS Pulse Width

50

tcp

TCEHCEL

CAS Precharge Time

50

60

70

ns

t ASA

TAVREL

Row Address Set·Up Time

0

0

0

ns

tAAH

TRELAX

10

15

20

ns

t ASC

TAVCEL

Column Address Set·Up Time

0

0

0

ns

tCAH

TCELAX

Column Address Hold Time

15

20

25

ns

tAA

TRELA(C)X

Column Address Hold Time
Referenced to RAS

55

70

80

ns

tACS

TWHCEL

Read Command Set·Up Time

0

0

0

ns

0

. Row Address Hold Time

tACH

TCEHWX

Read Command Hold Time

t AAC

TRELQV

Access Time from RAS

60

t CAC

TCELQV

Access Time from CAS

TCEHQZ

Output Buffer Turn·Off Delay

10,000

0

40

10,000

6

7

ns

8

ns

9, 10

65

ns

10, 11

50

ns

12

50
45

ns

120

0

0

5

ns

80

100

40
0

ns

ns

135

110
10,000

80

tOFF

85

0

Read Cycle Waveforms*
tRAS
(TRElREH)

tAR
(TRElA(C)X)
ROW VIHADORESS
STROBE VIL-

0'
1TL2~r)~

COLUMN VIHADDRESS
STROBE VIL-

I::- (TRtrC~El)

tASR
(lAVREl)

~

-

J

ROW
ADDRESS

tCSH
(TRELCEH)

~

~;t1~~E

)e
tRr.~

(TWHCH)
WRITE V I H - "
ENABLE VIL ~

nH:~~El)1
CD; 11

"kCD

~H
(TRELA:O
ADDRESSES VIH VIL-

tRC
(TRHREL)

tRSH
(TCELREH)
tCAS
(TCElCEH)

I--- :lH1H2)

~

I~.u

,

(TCHAX)

~

CliLUMN
AIIDRESS

I

\.
J

tRCH.
(TCEHWX)

I

~

tCAC
(TCElQV)

tRAC
1tLUV

DATA VOHOUT VDL-

-

,

0

~
E~~kl-j
\

(TCE

VALID
DATA

Hi·Z

* Symbols In parentheses are proposed industry standard.
1-79

I-

o
C1'I

I\)

<0
C1'I

ns

140
120

65

Notes

Write Cycle AC Electrical Characteristics
Symbol
Alternate

Parameter

Standard

(Notes 1,2,3 and 4)

NMC5295-2
Min
Max

NMC5295-3
Min
Max

NMC5295-4
Min
Max

200

235

270

twc

TRELREL

Random Write Cycle Time

tRAS

TRELREH

RAS Pulse Width

95
95

10,000

115

10,000

140

Units
ns

10,000

ns

tRP

TREHREL

RAS Precharge Time

tT

TH1H2

Rise Time

3

50

3

50

3

50

ns

tT

TL2L1

Fall Time

3

50

3

50

3

50

ns

tRCO

TRELCEL

RAS to CAS Delay Time

15

40

20

50

25

55

ns

t RSH

TCELREH

RAS Hold Time

55

65

85

ns

tCSH

TRELCEH

CAS Hold Time

90

110

135

ns

tCAS

TCELCEH

CAS Pulse Width

50

tcp

TCEHCEL

CAS Precharge Time

50

60

70

ns

t ASR

TAVREL

Row Address Set-Up Time

0

0

0

ns

10

15

20

ns

0

0

0

ns

tRAH

TRELAX

Row Address Hold Time

tAse

TAVCEL

Column Address Set-Up Time

110

10,000

120

10,000

60

80

ns

10,000

ns

tCAH

TCELAX

Column Address Hold Time

15

20

25

ns

tAR

TRELA(C)X

Column Address Hold Time
Referenced to RAS

55

70

80

ns

twcs

TWLCEL

WE to CAS Set-Up Time

t WCH

TCELWX

Write Command Hold Time

twp

TWLWH

Write Command Pulse Width

35

35

40

ns

tCWL

TWLCEH

Write Command to CAS Lead
Time

55

65

85

ns

tRWL

TWLREH

Write Command to RAS Lead
Time

60

70

90

ns

tWCR

TRELWX

Write Command Hold Time
Referenced to RAS

70

80

90

ns

tos

TDVCEL

Data In Set-Up Time

0

0

0

ns

tOH

TCELDX

Data In Hold Time

30

30

30

ns

tOHR

TRELDX

Data in Hold Time
Referenced to RAS

70

80

90

ns

Write Cycle (Early-Write) Waveforms·

0

0

0

ns

30

30

35

ns

(Note 13)

'lAS
1t"1

'RC
IIRELRELI

L

II"'

'AR.
nRELAI~IX'

ROW VIHADDRESS
STROBE VIL-

•
I

COLUMN VIHADDRESS
STROBE VIL-

VIHVIL-

ENABLE VIL-

DATA VIHIN VIL-

n,

'CAS
" .... tn,

W!I'

'CAH
IILtLA',

A~~~::~S

ADORE!

WRITEV'H-~

'RSH
IILtL"tH,

'CSH

"no..,

-;::e, :~LI
--~_h~RR~~~

'ASR,
IIAY"tL'1
ADDRESSES

'RP
"ntnntL'

V
'RCD
"nt"'"

•

'WCS
ITWLCEL'

-'WCH
I'GELWx)

'CWL

'RWL
ITWLREH,

..

'WCR

" ,,"
IVAI I
DATA

, (TDVC'~~I-l ~DHR

'DH
IIGHUX)

II "tLUX)

DATA VDHOUT VOL-

...-

~

'WP
II"L"H,

Hi·Z

* Symbols In parentheses are proposed Industry standard.
1-80

Notes

6

13

z

Read-Write and Read-Modify-Write Cycle AC Electrical Characteristics

3:

(Notes 1, 2, 3 and 4)

(")

Symbol
Standard
Alternate
tAwc

TRELREL

Min

Read-Write Cycle Time

250

RAS Pulse Width

145

NMC5295·4

NMC5295·3
Max

NMC5295·2

Parameter

Max

Min

Min

295

345

Units

Max

Notes

ns

14

ns

14

(R/W)

tAAW

TRELREH
(RIW)

10,000

175

10,000

215

10,000

120

110

TREHREL

RAS Precharge Time

TH1H2

Rise Time

3

50

3

50

3

50

tT

TL2L1

Fall Time

3

50

3

50

3

50

ns

tACO

TRELCEL

RAS to CAS Delay Time

15

40

20

50

25

55

ns

t ASH

TCELREH

RAS Hold Time

55

tCSH

TRELCEH

CAS Hold Time

tCRW

TCELCEH
(RIW)

CAS Pulse Width

65

tcp

TCEHCEL

CAS Precharge Time

t ASA

TAVREL

Row Address Set·Up Time

125

10,000

ns

135
160

10,000

ns
10,000

ns

14
6

50

60

70

ns

a

0

a

ns

10

15

20

ns

a

0

0

ns

tAAH

TRELAX

Row Address Hold Time

t ASC

TAVCEL

Column Address Set-Up Time

tCAH

TCELAX

Column Address Hold Time

15

20

25

ns

tAA

TRELA(C)X

Column Address Hold Time
Referenced to RAS

55

70

80

ns

tACS

TWHCEL

Read Command Set·Up Time

0

0

a

ns

twp

TWLWH

Write Command Pulse Width

35

35

40

ns

tCWL

TWLCEH

Write Command to CAS Lead
Time

55

65

85

ns

t RWL

TWLREH

Write Command to RAS Lead
Time

60

70

90

ns

tAwo

TRELWL

RAS to WE Delay

80

100

120

ns

t cwo

TCELWL

CAS to WE Delay

40

50

65

ns

tos

TDVWL

Data In Set-Up Time

toH

TWLDX

Data In Hold Time

5

ns

85

110

90
105

a

0

a

ns

30

30

35

ns

7

13

t AAC

TRELQV

Access Time from RAS

80

100

120

ns

9,10

t CAC

TCELQV

Access Time from CAS

40

50

65

ns

10,11

tOFF

TCEHQZ

Output Buffer Turn·Off Delay

50

ns

12

40

0

0

a

45

Read-Write and Read-Modify-Write Waveforms·
'Rwe
,TRELRU (RIWII
'RAS
ITRELREH)

'AR
(TRELA(C)X)

I-(TR~~~EL)-

ROW VIH- - - - - .
ADDRESS
1\
STROBE VIL-

It
'RCO
(TRELCEL)

'CSH

'RSH
ITCELREHI

(IREl~EHI

COLUMN
ADDRESS VIHSTRDBE VIL-

~
~ (~A;~REL)

ADDRESSES VIHVIL-

ApDRESS

'RAH
(TRELAX)

~
(TWHCE"~-j

'CAS
ITCELCEH)

~~

hT~~~~X)-

H:leCEL)

~~~~~S~
'RWD
(TRELWL)

f-

~
leWD
(TCELWL)

WRITE VIH-~
~~
ENABLE VIL 'CAC
(TCELQV)

,~
I~ (~~~H) =J

DATA VOHDUT VDL-

DATA
'RAC
(TRELQV)

~TW"LilX)

DATA VIHIN VIL-

DATA

* Symbols in parentheses are proposed industry standard.
1-81

J.-

en

ns

tRP
tT

95

en

N
CO

-

HQZ)

\.

Y.

III

Lt)

~
Lt)

RAS·Only Refresh and Buried Refresh AC Electrical Characteristics

o
:E
z

Units

Notes

ns

ns
ns
ns
ns
ns

5

ns
ns
ns

15

ns

6

ns
ns
ns
ns
ns

7

ns

D~~~ ~~~:::

- - - - - - - - - - - - - - - - H I - Z - - - - - - - - - - - '_______

Buried Refresh' Waveforms *

ROW VIH-

ADDRESS
STROBE

VIL-

It••
ITREHREL)

r-t •• r

7~~------VALI~D:'~I--------~~~----

-,~

-:~~hQVI

II HtL.tLJ

• Symbols In parentheses are proposed Industry standard.

1-82

ns

8

ns

9,10

ns

10,11

ns

12

z

s:
o

Page Mode Read Cycle AC Electrical Characteristicst (Notes 1,2,3 and 4)
Symbol
Alternate Standard

Parameter

NMC5295·2
Max
Min

NMC5295·3
Max
Min

NMC5295·4
Min
Max

130

160

tpc

TRELREL

Page Mode Cycle Time

110
205

300

10,000

ns

t RAS

TRELREH

RAS Pulse Width

TREHREL

RAS Precharge Time

tT

TH1H2

Rise Time

3

.50

3

50

3

50

ns

tT

TL2L1

Fall Time

3

50

3

50

3

50

ns

tRCO

TRELCEL

RAS to CAS Delay Time

15

40

20

50

25

55

tRSH

TCELREH

RAS Hold Time

55

tCSH

TRELCEH

CAS Hold Time

90

tCAS

TCELCEH

CAS Pulse Width

50

tcp

TCEHCEL

CAS Precharge Time

50

60

70

ns

t ASR

TAVREL

Row Address Set-Up Time

0

0

0

ns

tRAH

TRELAX

Row Address Hold Time

10

15

20

ns

t ASC

TAVCEL

Column Address Set-Up Time

0

0

0

ns

tCAH

TCELAX

Column Address Hold Time

15

20

25

ns

tAR

TRELA(C)X

Column Address Hold Time
Referenced to RAS

55

70

80

ns

tRCS

TWHCEL

Read Command Set-Up Time

0

0

tRCH

TCEHWX

Read Command Hold Time

0

0

tRAC

TRELQV

Access Time from RAS

t CAC

TCELQV

Access Time from CAS

tOFF

TCEHQZ

Output Buffer Turn-Off Delay

10,000

245

60

80

0

0

45

ns

ns

8

ns

9, 10

65

ns

10,11

50

ns

12

ROW VIHADDRESS
STROBE VIL-

t
~(T~rtCEl)

IPC

ICSH
tTRH~EHI

-(lRE~R:x1-

VIHVIL-

1-

- "U'l
(TCELCEH)

(~

"j

ICAH

I-

~
.ICAH

f-o~

IIlD
-oJ

~,

iRAC
II HtLUVI

ICAC
(TCELQV)

DATA VOHDUT VDL-

,

I~

y~

IRSt
" ... , tn,

;;~~~"'
~~~
~~~ ~
iC~~
~

(lAVREL)
ADDRESSES

r--

ICAS
, .... tn,

~

COLUMN VIHADDRESS
STROBE VIL

I(TR:~~EL) .1

IRAS
(TRELREH)

IIH'LAI~IXI

----,

IRCSd
(TWHCEL)
~

~~:~i 'lH~(TCElQV) - ~:~tlHQZ) (lCElQV)

~K~WHQZ)

....... J

\-U

IRCH
(TCEHWX')-

WRITEVIH-~

ENABLE VIL-

~CAC

----J ICAC

t-1

\..-....f
~~~CEl)

-

W

t Standard part not tested for page mode.
* Symbols in parentheses are proposed industry standard.

1-83

7

120

Page Mode Read Cycle Waveforms *
,IAR

6

ns

0

50

40

10,000

°
100

40
0

80

10,000

5

ns

135

110

ns
ns

85

65

10,000

ns

120

110

r,IRCH
(TCEHWX)

en
I\)

CD

en

ns

tRP

95

10,000

Units Notes

Lt)

CD

C\I

Lt)

o
:E
z

Page Mode Write Cycle AC Electrical Characteristicst
Symbol
Alternate
Standard

twcs

Parameter

NMC5295-2
Min

NMC5295-3

Max

Min

10,000

245

NMC5295-4

Max

Min

10,000

300

Max

Units

TRELREL

Page Mode Cycle Time

110

TRELREH

RAS Pulse Width

205

TREHREL

RAS Precharge Time

TH1H2

Rise Time

3

50

3

50

3

50

TL2L1

Fall Time

3

50

3

50

3

50

ns

TRELCEL

RAS to CAS Delay Time

15

40

20

50

25

55

ns

160

130

95

ns
10,000

120

110

ns
ns
ns

TCELREH

RAS Hold Time

55

65

85

ns

TRELCEH

CAS Hold Time

90

110

135

ns

TCELCEH

CAS Pulse Width

50

TCEHCEL

CAS Precharge Time

50

60

70

ns

TAVREL

Row Address Set-Up Time

o

o

o

ns

10

15

20

ns

o

o

o

ns

10,000

60

10,000

80

10,000

ns

TRELAX

Row Address Hold Time

TAVCEL

Column Address Set-Up Time

TCELAX

Column Address Hold Time

15

20

25

ns

TRELA(C)X

Column Address Hold Time
Referenced to RAS

55

70

80

ns

o

o

o

TWLCEL

WE to CAS Set-Up Time

TCELWX

Write Command Hold Time

30

TWLWH

Write Command Pulse Width

35

35

40

ns .

TWLCEH

Write Command to CAS Lead
Time

55

65

85

ns

TWLREH

Write Command to RAS Lead
Time

60

70

90

ns

TRELWX

Write Command Hold Time
Referenced to RAS

70

80

90

ns

o

ns

o

30

o

35

ns
ns

TOVCEL

Data In Set-Up Time

TWLDX

Data In Hold Time

30

30

35

ns

TRELDX

Data In Hold Time
Referenced to RAS

70

80

90

ns

Page Mode Write Cycle Waveforms*
ROW
ADDRESS
STROBE

COLUMN
ADDRESS
STROBE

ADDRESSES

WRITE

ENABLE

DATA

IN

tStandard part not tested for page mode .
.. Symbols in parentheses are proposed industry standard.

1-84

Notes

6

13

Symbol
Alternate

Parameter

Standard

NMC5295·2
Max
Min

NMC5295·3
Min
Max

NMC5295·4
Min
Max

190

235

Units

tpc

TRELREL
(R/W)

Read·Write Cycle Time

160

tRAS

TRELREH
(RIW)

RAS Pulse Width

300

tRP

TREHREL

RAS Precharge Time

tT

TH1H2

Rise Time

3

50

3

50

3

50

ns

tT

TL2L1

Fail Time

3

50

3

50

3

50

ns

40

20

50

25

55

10,000

110

95

tRCO

TRELCEL

RAS to CAS Delay Time

15

t RSH

TCELREH

RAS Hold Time

55

tCSH

TRELCEH

CAS Hold Time

tCAS

TCELCEH
(R/W)

CAS Pulse Width

tcp

TCEHCEL

CAS Precharge Time

t ASR

TAVREL

Row Address Set·Up Time

10,000

360

445

10,000

10,000

ns

14

ns

14

ns

5

ns

135

120

Notes

ns

85

110

90
100

10,000

120

65

155

10,000

ns

13

ns

14
6

50

60

70

ns

0

0

0

ns

10

15

20

ns

0

0

0

ns

tRAH

TRELAX

Row Address Hold Time

t ASC

TAVCEL

Column Address Set·Up Time

tCAH

TCELAX

Column Address Hold Time

15

20

25

ns

tAR

TRELA(C)X

Column Address Hold Time
Referenced to RAS

55

70

80

ns

tRcs

TWHCEL

Read Command Set·Up Time

0

0

0

ns

twp

TWLWH

Write Command Pulse Width

35

35

40

ns

tCWL

TWLCEH

Write Command to CAS Lead
Time

55

65

85

ns

t AwL

TWLREH

Write Command to RAS Lead
Time

60

70

90

ns

7

t RWO

TRELWL

RAS to WE Delay

80

100

120

ns

t cwo

TCELWL

CAS to WE Delay

40

50

65

ns

tos

TDVWL

Data·ln Set·Up Time

ns

tOH

TWLDX

Data·ln Hold Time

t RAC

TRELOV

Access Time from RAS

80

100

120

ns

9,10

!cAC

TCELOV

Access Time from CAS

40

50

65

ns

10,11

tOFF

TCEHOZ

Output Buffer Turn·Off Delay

50

ns

12

0

0

0

30

30

35

40

0

45

0

Page Mode Read·Modify·Write Waveforms·

ROW
AOORESS
STROBE

~;mHRn'

1-:¥~rLAXI

-'--

1-:ftrLAXI

!pC
COLUMN
AOORESS
STROBE

AOORESSES

WRITE
ENABLE

.'ACO
ITRELCELI

VIHVIL-

'A

1'1

rlT~CL~~HI-1

-I

_L'WP

v

. -

~";\!k
'O~

'(lDvwLt-

I-:t

SSCELI

1-

;,..

VIL-

1-

IT~~hvl

r>:

•. ;:::)\, .~~ V':.

_L;fJ:LWH

'1

~ ~;),/"m'

1-

:-

J?:;:LOXI

...2ill. K§f~2»;<: X~

:)(. ~:~,~X:~;:::::::F>::;:;;A::::;~X

-I Jf--'"

H;·Z

-

i~--!t

-I 1-;~ttH

~

ITCE

-1=
~

.Y.

1-:mLAx,

t Standard part not tested for page mode.
* Symbols In parentheses are proposed industry standard.

1·85

'CA~

TCELCEHI

t:1

h~l~~-I ~~!-1 br~·(~mHI

~~CELI

i.--

VIH-

DATA VOHOUT VOL-

'CAS
ITCELCEHI

:, ~~'\~ t~~:

VIL-~~~4~
ITW~ ~CdH l~fLWLI
I

'CP
ITCEHCELI

-1

[OL

t~~~,
!,,,n(max) (column limited timing).
Note 12: TCEHOZ is measured to IOUT:s IO(L).
Note 13: The placement of the negative going edge ofW with respect to the negative edge of CAS determines the type of Write cycle.IfTWLCEL is greater than
o ns (negative edge of W before negative edge of CAS) the memory is in an Early-Write cycle and Data Out Is TRI·STATE. If TCELWL Is greater than
TCELWL(min) (negative edge of W coincident with or after Data Out valid) the memory Is In a Read·Write or Read·Modify·Write cycle and Data Out Is the original contents of the selected cell. If W goes LOW between these two times the cycle Is a Write cycle and Data Out Is Indeterminate.
Note 14: (R/W) indicates a Read-Write or Read-Modify-Write cycle parameter.
Note 15: Max limit does not apply for RAS-Only Refresh. During Buried Refresh CAS can be low and valid output maintained for any desired period of time.

1-86

Section 2
CMOS RAMs

CMOS RAMs provide the lowest power of any of
the semiconductor read/write memory technologies. National's CMOS memory line may be
mixed with our CMOS logic, TTL logic, bipolar
microprocessor, MOS microprocessor, custom
LSI, and our other semiconductor products to optimize system power/speed/cost tradeoffs. Refer
to National's related databooks and catalogs for
further details: an order form is included in this
book.

~National

CMOS RAMs

~ Semiconductor

MM54C89/MM74C89 64-Bit (16 x 4) TRI-STATi:® RAM
General Description
address by bringing write enable and memory
enable low.

The MM54C89/MM74C89 is a 16-word by 4-bit
random access read/write memory_ Inputs to the
memory consist of four address lines, four data
input lines, a write enable line and a memory
enable line. The four binary address inputs are
decoded internally to select each of the: 16 possible
word locations. An internal address register, latches
the address information on the positive to negative
transition of the memory enable input. The four
TRI-STATE® data output lines working in conjunction with the memory enable input provides
for easy memory expansion.

Read Operation: The complement of the information which was written into the memory is nondestructively read out at the four outputs. This is
accomplished by selecting the desired address and
bringing memory enable low and write enable
high.
When the device is writing or disabled the output
assumes a TRI-STATE (Hi-z) condition.

Features

Address Operation: Address inputs must be stable
tSA prior to the positive to negative transition
of memory enable. It is thus not necessary to
hold address information stable for more than
tHA after the memory is enabled (positive to
negative transition of memory enable).

• Wide supply voltage range
• Guaranteed noise margin

3.0V to 15V
1.0V
0.45 Vee typ
fan out of 2
driving 74L

•

High noise immunity

•

Low power TTL
compatibility

Note: The timing is different than the DM7489 in
that a positive to negative transition of the memory
enable must occur for the memory to be selected.

•
•

Input address register
Low power consumption

Write Operation: Information present at the data
inputs is written into the memory at the selected

• Fast access time
• TRI-STATE output

100 nW/package typ
@V ee = 5V

130 ns typ at Vee = 10V

Logic and Connection Diagrams
DATA
DATA
DATA
DATA
DATA
DAfli
DATA
DAfli
INPUT 1 iiiiTPUi'1INPUT I iiUfPifl1,NPUTl 0uffiffl,NPUT4 ififffijfi

Dual-In-Line Package
ADDRESS INPUT A

IIDll!IIVfNABU

Vee

z

'5

WRrnfNABU 1
DATA INPUT 1

~=1
DATA INPUT 2

iiAfAOUfPOlz

ADORESSINPUTB

14ADDRESSINPUTC

ADDRESS INPUT 0

.

11

DATAINPUT4

"iiAfA0ilfPijf4

J

g~iIUfflJTl

GND

TOPVIEW

Order Number MM54C89J
or MM74C89J
See NS Package J16A
Order Number MM74C89N
See NS Package N16A

2-1

Absolute Maximum Ratings

Operating Conditions

Voltage at Anyl'in

Ambient Temperature Range
MM54CB9
MM74CB9
Supply Voltage Range
MM54CB9
MM74C89

-0.3V to Vee + O.3V
-65°C to + 150°C

Storage Temperature Range
Package Dissipation

500mW
lBV
300°C

Absolute Maximum Vee
Lead Temperature (Soldering, 10 seconds)

-55°C to +125°C
_40° C to +B5° C
3V to 15V
3V to 15V

DC Electrical Characteristics
Min/max limits apply across temperature range, unless otherwise noted,
PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

CMOS TO CMOS
Logical "1" Input Voltage (V'NI'»)

Vee = 5.0V
Vee = 10V

Logical "0" Input Voltage (V ,NIOl )

Vee = 5.0V
Vee = 10V

Logical "1" Output Voltage

Vee = 5.0V, 10 = -lOJ1A
Vee = 10V, 10 = -10J1A

(VOUTI1l1
Logical "0" Output Voltage

3.5
B.O

V
V
1.5
2.0

V
V

4.5
9.0

Vee = 5.0V, 10 = +IOJ1A
Vee;" 10V, 10 = +10J1A

(VOUTIOl)
Logical "I" Input Current (I,NI1I)

Vee = 15V, V ,N = 15V

Logical "O"lnput Current (I,NIOlI

Vee = 15V, V ,N = OV

Output Current in High Impedance
State

Vee = 15V, Vo = 15V
Vee = 15V, Vo = OV

Supply Current (I eel

Vee = 15V

V
V

0.005

0.5
1.0

V
V

1.0

J1A

-1.0

-0.005
1,0

-1.0

0.005
-0.005

J1A
J1A

0.05

300

J1A

J1A

CMOS/LPTTL INTERFACE
Logical "I" Input Voltage (V ,NI1I )

54C, Vee = 4.5V
74C, Vee = 4.75V

Logical "0" Input Voltage (V ,NIOl )

54C, Vee = 4.5V
74C, Vee = 4.75V

Logical "1" Output Voltage

54C, Vee = 4.5V, 10 = -360J1A
74C, Vee = 4.75V, 10 = -360J1A

(VOUTI')!
Logical "0" Output Voltage

V
V

Vee - 1.5
Vee - 1.5

V
V

2.4
2.4

V
V

0.4
0.4

54C, Vee = 4.5V, 10 = +360J1A
74C, Vee = 4.75V, 10 = +360J1A

(VOUTIOl)

V
V

0.8
0.8

OUTPUT DRIVE (See 54C174C Family Cha·racteristics Data Sheet)
Output Source Current (lsouReE I
(P·Channel)

Vee = 5.0V, V OUT = OV
T A = 25°C

-1.75

-3.3

rnA

Output Source Current (lSOURCE I
(P·Channel)

Vee = 10V, VOUT = OV
T A =25°C

-B.O

-15

mA

Output Sink Current (lSINK)
(N-Channel)

Vee = 5.0V. V OUT = Vee
T A =25°C

1.75

3.6

rnA

Output Sink Current (lSINK)
(N-Channel)

Vee = 10V, V OUT = Vee
TA = 25°C

8.0

16

rnA

AC Electrical Characteristics

(T A = 25°C, C L = 50 pF, unless otherwise noted,)
TYP

MAX

UNITS

Vee = 5.0V
Vee = 10V

270
100

500
220

ns

Access Time from Address Input (tacc )

Vee = 5.0V
Vee = 10V

350
130

650
280

ns
ns

Address Input Setup Time (tSA)

Vee = 5.0V
Vee = lOV

150
60

ns
ns

Address Input Hold Time (tHAI

Vee = 5.0V
Vee = 10V

_60
40

ns

Memory Enable Pulse Width (tME)

Vee = 5.0V
Vee = 10V

400
150

250
90

ns
ns

Memory Enable Pulse Width (tME)

Vee = 5.0V
Vee = 10V

400
150

200
70

ns
ns

PARAMETER
Propagation Delay from Memory
(tpd)

CONDITIONS

EiliiiJie

2-2

MIN

ns

ns

AC Electrical Characteristics

3:
3:

(Continued)

PARAMETER

MIN

CONDITIONS

WrIte EnatiTe Setup Time for a Read

= 5.0V
= 10V
= 5.0V
= 10V

(tSA)

Vee
Vee

Write rnatiIe Setup Time for a Write
(tws)

Vee
Vee

Write ~ Pulse Width (twe)

Vee
Vee

Data Input Hold Time (tHO)

Vee
Vee = 10V

MAX

TYP

UNITS
ns
ns

0
0
tME
tME

= 5.0V. tws = 0
= 10V. tws = 0
= 5.0V

300
100

160
60

ns
ns

50

= 5.0V
= 10V
= 5.0V. CL = 5.0 pF.
= 10V. CL = 5.0 pF.

ns
ns

25

ns
ns

50
25

ns
ns

Data Input Setup (tso)

Vee
Vee

Propagation Delay from a Logical "1"
or Logical "0" to the High Impedance
State from Memory EnatiTe (t IH • tOH)

Vee
Vee

RL = 10k
RL = 10k

180
85

300
120

ns
ns

Propagation Delay from a Logical "1"
or Logical "0" to the High Impedance
State from Write Enable (tIH. to H )

Vee = 5.0V. CL = 5.0 pF. RL = 10k
Vee = 10V. CL = 5.0pF. RL = 10k

180
85

300
120

ns
ns

Input Capacity (Clt-,il

Any Input (Note 2)

5.0

pF

Output Capacity (C OUT )

Any Output (Note 2)

6.5

pF

Power Dissipation Capacity (C pd )

(Note 3)

230

pF

Note 1: "Absolute MaXimum Ratings" are those values beyond which thp. safety of the device cannot be guaranteed.
Except for "Operating Range" they are not meant to imply that the devices should be operated at these limits. The table
of "Electrical Charactenstics" provides conditions for actual device operation.
Note 2: Capacitance

IS

guaranteed by periodic testing.

Note 3: CpO determInes the no load ae pOlA-er consumption of any CMOS device. For complete explanation see 54C/74C
Family Characteristics application note. AN-gO

Truth Table
ME

WE

L

L

OPERATION
Write

CONDITION OF OUTPUTS
TRI-STATE

L

H

Read

Complement of.Selected Word

H

L

Inhibit, Storage

TRI·STATE

H

H

Inhibit. Storage

TRI·STATE

AC Test Circuits
tOH
Vee

Switching Time Waveforms
tOH

Vee

Vee
MEMID\Y

MEMORY

mm

fiillTI

OV_{""
Vee
t~H
~o.tvce
-----1

ov

r. . .---

t1H

J. ."
t'"~
0.1 Vee

0AfA
OUTPUT

-r

2-3

OV

en
~
0

00

52
3:
3:
~

~

0

00
CO

Switching Time Waveforms

(Continued)

Read Cycle

Write Cycle

ADDRESS
INPUT

v,, _ _ _ _ _ __
WRITE
ENABlE

DATA
OUT

vcc - - - - - - - _

'4:c-----·----··------·----·---------·-----+.....- - - - -

.

O _ _ _ _ _ ~I~A.::.~~~T~ _ _ /

'£"

DATA

INPUT

Read Modify Write Cycle

~~ :~- -------------------------------p~
NOTE: t,"'60m
I, '" 10 n~

2-4

CMOS RAMs

~National

~ Semiconductor
M M54C200/M M74C200
256·Bit (256 x 1) TRI·STATi:® . RAM
General Description
The MM54C200/MM74C200 is a 256-bit random
access read/write memory_ Inputs consist of eight
address lines. a data input line. a write enable
line. and three chip enables_ The eight binary
address inputs are decoded internally to select
each of the 256 locations_ An internal address
register. latches and address information on the
positive to negative edge of CE 3 - The TRI·
STATE data output line working in conjunction
with CE l or CE 2 inputs provides for easy memory
expansion_

Read Operation: The data is read out by selecting
the proper address and bringing CE 3 low and write
enable high_ Holding CE l or CE 2 or CE 3 at a
high level forces the output into TRI-STATE_
When used in bus organized systems. CEl. or CE 2 •
a TRI-STATE control. provides for fast access
times by not totally disabling the chip_

Address Operation: Address inputs must be stable
tSA prior to the positive to negative transition of
CE 3 _ It is thus not necessary to hold address
information stable for more than tHA after the
memory is enabled (positive to negative transition)_

Features

Write Operation: Data is written into the memory
with CE 3 low and write enable low_ The state of
CE l or CE 2 has no effect on the write cycle. The
output assumes TRI·STATE with write enable low.

•
•
•
•

Wide supply voltage range
3.0V to 15V
Guaranteed noise margin
1.0V
High noise immunity
0.45 Vee typ
TTL compatibility
fan out of 1 driving
standard TTL
500 nW typ
• Low power
• Internal address register

Note: The timing is different than the DM74200
in that a positive to negative transition of the
memory enable must occur for the memory to be
selected_

Logic and Connection Diagrams
ADDRESS

ADDRESS

ADDRESS

ADDRESS

INPUT D

INPUTC

INPUT B

INPUT A

Dual-In-Line Package

E:~[~--~------

________ __ __
~

~

~--~-r~L-~~~~~--~~

+ ______________I-__I-__-+I

ADDRESS 1
INPUT A

16 Vee

ADDRESS 2
INPUT B

15 ADDRESS
INPUT C

tE,

DA~: __

X-DECODER

ti,

ff,-----------=""

12 WRITE
ENABLE
11 ADDRESS
INPUT G
10 ADDRESS
INPUT F
9 ADDRESS
INPUT E

ti,

CE,----'

DATA 6
OUT
ADDRESS
INPUT 0

CE,----------..-.---i ~.....- ...

GND

250·8IT
MEMORY ARRAY

TOP VIEW

Order Number MM54C200J
or MM74C200J

See NS Package J16A
Order Number MM74C200N

See NS Package N16A

2-5

Absolute Maximum Ratings

Operating Conditions

(Note 1)

Voltage at Any Pin
-0.3V to Vee +0.3V
-65°C to +150°C
Storage Temperature Range
Package Dissipation
500 mW
18V
Absolute Maximum Vee
Lead Temperature (Soldering, 10 seconds)
300°C

Ambient Temperature Range
MM54C200
MM74C200

-55°C to +125°C
-40°C to +85°C

Supply Voltage Range
MM54C200
MM74C200

3V to 15V
3V to 15V

DC Electrical Characteristics
Min/max limits apply across temperature range, unless otherwise noted.
PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

CMOS TO CMOS
Logical "I" Input Voltage (V,N,,,I

Vee = 5.0V
Vee = 10V

"a" Input Voltage

Vee ,. 5.0V
Vee = 10V

Logical

(V ,N 1011

Log'cal "I" Output Voltage (VOUTIl,1
Logical

"a .. Output Voltage (V OUT '.0,1

V
V

3.5
8.0
1.5
2.0
10 =

1Oil A
1Oil A

Vee" 5.0V.
Vee = 10V.

10 "

Vee" 5.0V.
Vee = 10V.

10 = 'lOIJA
10 ~ • 1Oil A

Logical "I" Input Current (I'NI1,I

Vee=15V.

V'N = 15V

Logical "O"lnput Current (I'N, 0I 1

Vee = 15V

V'N = OV

Supply Current (Ieel

Vee = 15V

-1.5
9.0

V
V
V
V

0.5
1.0
0.005
1.0

1.0

0.005
010

V
V
pA
ilA

600

ilA

CMOS/TTL INTERFACE
Logical "I" Input Voltage (V'N,,,I

54C. Vee = 4.5V
74C. Vee =4.75V

Logjcal "O"lnput Voltage (V'N, 0I 1

54C. Vee = 4.5V
74C. Vee = 4.75V

Logical "I" Output Voltage (VOUTIl,1

54C. Vee' 4.5V. 10 = -1.6 mA
74C, Vee = 4.75V. 10 = -1.6 mA

Logical

"a" Output Voltage (V OUT {Q' I

1.5
1.5

Vee
Vee

V
V
08
0.8

V
V
V
V

7..4
2.4

54C. Vee = 4.5V. 10 = 1.6 mA
74C. Vee = 4.75V. 10 = 1.6 mA

0.4
0.4

V
V

OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet)

.6

Output Source Current (lsouAeE I
(P·Channell

Vee = 5.0V.
TA = 25"C

VOUT = OV

-4 .
-1.8

-6.0

mA

Output Source Current IlsouAeE I
(P·Channell

Vee = 10V.
TA = 25'C

V OUT = OV

-16.0
-1.50

-25

mA

Output Sink Current (lS'NK I IN·Channell

Vee ~ 5.0V.
TA = 25'C

V OUT = Vee

5.0

Output Sink Current (lS'NK I IN·Channell

Vee = 10V.
TA = 25'C

VouT=Vec

20.0

AC Electrical Characteristics
PARAMETER

Propagation Delay From
It pd )

CE3

Propagation Delay From

GE,

ItpCE')

or GE 2

mA

30

mA

T A = 25°C, C L = 50 pF, unless ~therwise specified.
TYP

MAX

Vee = 5.0V
Vee = 10V

450
200

900
400

ns
ns

Vee = 5.0V
Vee = 10V

360
120

700
300

ns
ns

Vec=50V
Vee = 10V

250
85

500
200

ns
ns

CONDITIONS

Access Time From Address (tAee)

8.0

MIN

UNITS

Address Setup Time (t SA )

Vee = 5.0V
Vee = 10V

200
100

80
30

ns
ns

Address Hold Time Itl-iA)

Vee = 5.0V
Vee = 10V

50
25

15
5

ns
ns

2-6

AC Electrical Characteristics

(Continued)
MIN

CONDITIONS

PARAMETER

TYP

Write Enable Pulse Width (tw.1

Vee oS.OV
Vee = 10V

150

160
70

t-EJ

Vee = S.OV
Vee = 10V

400
160

200
80

Pulse Widths IteE 1

300

MAX

UNITS

Input CapaCIty IC 'N 1

Any Input INote 21

5.0

pF

Output CapaCIty In TRI·STATE IC our 1

INote 21

9.0

pF

Power DISsipation Capacity IC pd 1

INote 31

400

pF

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical
Characteristics" provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: Cpd determines the no load ac power consumption of any CMOS device. For complete explanation see 54C/74C
Family Chatacteristics application note, AN·90.

Switching Time Waveforms
Read and Write Cycles Using Ce3 (CEl .. CE2

= logic 0)

,-----"'------------- Vce
~-----------DV

,---------Vee

ADDRESS
INPUT

~--------DV

------Vee
~----,--------DV

_----Vee

DATA
IN

."

~j

t~----:I::;E------~vee
-~~~-

~
Read and Write Cycles Using CE3 and CE 1 (or CE2)

}~----'/_ _ _ _ _ _ o:ee
r-------,------------V~

-------oV
-------Vee

ADDRESS
INPUT

~---------oV

Vec

I

r~'.rn

DATA
IN

- - - - - - -- TRI-STATE

~----J------DV

~

______

r'o<

~'"-_-_-----_-_...J____::e

TRI-STATE

----------__________ DV

Note: Used for fast Iccess time in bused systems.

2·7

~National

CMOS RAMs

D Semiconductor
MM54C91 O/MM74C91
0 256·Bit (64 x 4) TRI·STATE® RAM
/
.

General Description
The MM54C91 0/MM74C91 0 is a 64 word by 4 bit
random access memory. Inputs consist of six address
lines, four data input lines, a write enable, and a
memory enable line. The six address lines are internally
decoded to select one of 64 word locations. An internal
address register, latches the address information on the
positive to negative transition of memory enable. The
TRI·STATE outputs allow for easy memory expansion.

Read Operation: Data is nondestructively read from a
memory location by an address operation with write
enable held high.
Outputs are in the TRI·STATE (Hi·Z) condition when
the device is writing or disabled.

Features

Address Operation: Address inputs must be stable (tSA)
prior to the positive to negative transition of memory
enable, and (tHA) after the positive to negative transition
of memory enable. The address register holds the
information and stable address inputs are not needed at
any other time.
Write Operation: Data is written into memory at the
selected address if write enable goes low while memory
enable is low. Write enable must be held low for tWE
and data must remain stable tHO after write enable
returns high.

•

Supply voltage range

3V to 5.5V

•

High noise immunity

•
•

TTL compatible fan out
Input address register

0.45 Vee typ
1 TTL load

•

Low power consumption

250 nW/package typ
(chip enabled or disabled)

•
•

Fast access time
TRI·STATE outputs

•

High voltage inputs

250 ns typ at 5V

Logic and Connection Diagrams
o INI

Input Protection
DOUTI OlN2

OOUT2 0 IN)

0 OUT)

OlN4

OOUT4

Vee

Dual·ln·Line Package
Vee

0 CUll

o IN4

mfil! MEMORY
0 OUT4!NA'BU ENABLE

10

DOUTl

Order Number MM54C910J
or MM74C910J
See NS Package J1BA
Order Number MM74C910N
See NS Package N1BA

2-8

Absolute Maximum Ratings

Voltage At Any Output Pin
Voltage At Any Input Pin
Package Dissipation
Absolute Maximum VCC
Lead Temperature (Soldering, 10 seconds)

Operating Conditions

(Note 1)

-{).3V to VCC +0.3V
-{).3V to +15V
500 mW
6.0V
300°C

DC Electrical Characteristics

Supply Voltage (VCC)
MM54C910
MM74C910
Temperature (T A)
MM54C910
MM74C910

MIN

MAX

UNITS

4.5
4.75

5.5
5.25

V
V

-55
-40

"c
°c

+125
+85

Operating VCC Range

3.0V to 5.5V

Standby VCC Range

1.5V to 5.5V

MM54C91O/MM74C91O

(Min/max limits apply across the temperature and power supply range indicated)'
PARAMETER

CONDITIONS

V IN (1)

Logical "1" Input Voltage

Full Range

VIN(O)

Logical "0" Input Voltage

Full Range

IIN(1)

Logical "1" I nput Current

V IN = 15V

MIN

TYP

V
0.8

-1

IIN(o)

Logical "0" Input Current

V IN = OV

V OUT (l)

Logical "1" Output Voltage

10 = -150J.1A

Icc

10 = 1.6 mA

Output Current in High

Vo = 5V

I mpedence State

Vo = OV

Supply Current

Vcc = 5V

AC Electrical Characteristics
TA

0.005

2

0.005

1

-0.005

V
J.1A
J.1A
p.A

V cc -0.5

10 = -400J.1A
Logical "0" Output Voltage

UNITS

V cc -J:5

V IN = 5V

VOUT(O)

MAX

V

2.4

V
V

0.4
0.005
-1

1

J.1A

300

p.A

MAX

UNITS

-0.005
0.05

J.1A

MM54C910/MM74C910

= 25°C, Vee = 5V, C L = 50 pF
PARAMETER
tAcc

Access Time from Address

tpD

Propagation Delay from

MIN

ME

TYP
250

500

ns

180

360

ns

tSA

Address Input Set-Up Time

140

70

ns

tHA

Address Input Hold Time

20

10

ns

tME

Memory Enable Pulse Width

200

100

ns

tME

Memory Enable Pulse Width

400

200

ns

tso

Data Input Set-Up Time

0

tHO

Data Input Hold Time

30

15

tWE

Write Enable Pulse Width

140

70

tlH' tOH

Delay to TRI-STATE (Note 4) ,.

ns

100

ns
ns
200

ns

CAPACITANCE
CIN

Input Capacity
Any Input (Note 2)

COUT

Output Capacity

CpD

Power Dissipation'Capacity (Note 3)

Any Output (Note 2)

2·9

5

pF

9

pF

350

pF

....m0

0

AC Electrical Characteristics
CL

(Continued)

= 50 pF

III:t

r--

:E
:E

a....
m
0

~

:E
:E

MMS4C910
T A = -SSoC to +12SoC
Vee = 4.SV to S.SV

PARAMETER

MIN

MAX

MM74C910
T A = -40°c to +8SoC
Vee = 4.7SV to S.2SV
MIN

UNITS

MAX

860

700

ns

660

540

ns

tAC C

Access Time from Address

tpDl,tpDO

Propagation Delay from

tSA

Address Input Set·Up Time

200

160

ns

tHA

Address Input Hold Time

20

20

ns

tME

Memory Enable Pulse Width

280

260

ns

tME

Memory Enable Pulse Width

750

600

ns

tSD

Data Input Set·Up Time

0

0

ns

tHD

Data Input Hold Time

50

50

ns

tiNE

Write Enable Pulse Width

200

180

tlH, tOH

Delay to TRI·STATE (Note 4)

ME

ns
200

200

ns

Note 1: "Absolute Maximum Ratings" are those values beyond which the safetY of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: Cpd determines the no load ac power consumption for any CMOS device. For complete explanation see 54C/74C Family Characteristics
application note, AN·90.
.
Note 4: See ac test ci rcu it for t 1 H, tOH.

Typical Performance Characteristics

Truth Table

Typical Access Time vs Ambient
Temperature
400

"'
~

~
ell

..

300
250

ME

1--'''''''

350

WE

OPERATION

OUTPUTS
TRI·STATE

4.~1---

I.--~

L

L

Write

L,...-V 5~1---

j...ol.--""

L

H

Read

Data

H

L

Inhibit, Store

TRI·STATE

H

H

Inhibit, Store

TRI·STATE

L.,..J.-' ""I--' +-"~ j...o 1's.5V

200 F""
150
100
50
0
-55

-25

5

35

65

95

125

FREE AIR TEMPERATURE I'C)

AC Test Circuits
All Other AC Tests

tOH

l't,
l't"

.--002

003

001

004

L...--

2·10

1'1'

i ,!,
c

RL -10k

CL "10pF

Switching Time Waveforms
Read Cycle

Write Cycle
(See Note 1)

(See Note 1)
Vee---+-"-----....

Vr.e

~
ENABLE

MEMORV
ENABLE

ADDRESS
INPUT

Vee - - - - - " "

Vee
ADDRESS
INPUT

Vee
WAITE

ENABLE

DATA Vee
OUT
o_ _ _ _ _ ~I!!.A!!,~N~T~

J

Vee
DATA

__

INPUT

Read Modify Wr-ite Cycle
(See Note 1)

tOH

" '~--=f"""

r--- 'M' ---- ----

MEMORY

vcc--t-r

ENABLE

DATA OUT
ADDRESS

'- ;li:i--'
-r "' ' '
o

LATCHED ADDRESS

INPUT

0.1 Vee

WRITEvee _ _ _

ENABlE

J-'m~'HO~
~'H

---'X

DA~~ vee _ _ _ _ _ _ _ _ _ _

~

:c=

Vee

0.1 Vee

DATA OUT

Note1: ~ID must he brought high fOI w.e niinosecondsbetwetneveIVaddrench.nge.
Not,2: t, ~ If ·2001 for ,II inputs,

2·11

"; ,je
o

---TRI-STATE

~National

CMOS RAMs

~ Semiconductor

MM54C920/MM74C920, MM54C921 1M M74C921
1024-Bit(256 x 4) Static RAMs
General Description
these RAMs ideal elements for use in microprocessor,
minicomputer as well as main frame memory applications.

The MM54C920/MM74C920 256 x 4 random access
read/write memory is manufactured using silicon gate
CMOS technology. Data output is the same polarity as
data input. Internal latches store address inputs. CES
and data output. This RAM is specifically designed to
operate from standard 54/74 TTL power supplies.
All inputs and outputs are TTL compatible.

Features
•

256 x 4·bit organization

•
The MM54C921/MM74C921
is identical to the
MM54C920/MM74C920, except data inputs are inter·
nally connected to data outputs; the number of package
leads thereby is reduced to 18.

Access
250
275
300

•

TRI-STATE outputs

Complete address decoding as well as 2·chip select
functions, CE Land CES, and TR I·ST ATE® outputs
allow easy expansion with a minimum of external com·
ponents. Versatility plus high speed and low power make

•
•
•
•

Low power
On-chip registers
Single 5V supply
Data retained with VCC as low as 2V

time
ns max MM74C920, MM74C921
ns m·ax MM54C920, MM54C921
ns max MM74C921·3

Connection Diagrams

Logic Symbols

Dual-In-Line Package
A3

AD

A2
Al
AD
A5
MM54C920/
MM14C920

A6

m
rr

17

m

16

A1

15

GNO

14

011

13

001 10

012

19

18

11

Order Number MM54C920J, MM74C920J
or MM74C920J-3
See NS Package J22A

004
014

Order Number MM74C920N or MM74C920N-3
See NS Package N22A

003
013

12 002
TOPVIEW

Dual·ln-Line Package
18

A3
A2
Al

AD
VCC

11
3

AD
A5

MM54C9211
MM14C921

16

m

15

m

14S'f
13

AS 6

12

A1

m
01/04

11 01/03

GNO

10

01/01

Al

01/01

A4
01/02
MM54C9211
MM14C921
01/03

Order Number MM54C921J, MM74C921J
or MM74C921J-3
See NS Package J18A
Order Number MM74C921N or MM74C921N-3
See NS Package N18A

01/02

TOP VIEW

2-12

Functional Description
The functional description will reference the logic
diagram of the MM54C920/MM74C920 shown in
Figure 1. Input addresses and CES are clocked into
the input latches by the falling edge of STROBE. Input
set·up and hold times must be observed on these signals
(see timing diagrams): The true and complement add"ress
information is fed to the row and column decoders
which access the selected 4-bit memory word.

The outputs are in a high impedance state when the
chip is not selected (C-ES or GEL high) or when writing
(WE lowL Note that the information stored in the output latches will be changed whenever STROBE falls,
regardless of the logic states of WE, CEl or CES.

The switching time waveforms in Figures 2, 3 and 4
define the read, write, and output enable/disable parameters respectively.

The addressed word (4 bits) is fed to 4 sense amplifiers
through the column decoders. The information from the
sense amplifiers is latched into the output register when
STROBE rises. The register drives the TRI-STATE
output buffers.

Reduced-Voltage Operation

Chip select inputs, CE land CES, have identical functions
except that CES (Chip Enable Stored) is clocked into a
latch on the falling edge of STROBE; CEl (Chip Enable
level) is not.

These memories will retain data with reduced VCC and
hence are useful for battery-backup data storage. Certain
precautions must be observed as V CC is reduced: (1)
input voltages must remain between the VCC and ground
of the RAM or supply latch-up can occur, (2) WRITE
mode must be avoided, (3) during power-up of VCC,
ST logic state must be maintained (either GND or Vccl
while address control lines stabilize.

Note that set-up and hold times must be observed on
CES. Because CEl is not clocked by STROBE, it may
fall after STROBE has fallen without affecting access
time provided that the tOE requirement is met"

Logic Diagram

*

AO
Al
A2
A3
A4

ADDRESS
REGISTER
AND
INVERTERS

32
X

8

ROW
DECODER

(LATCH)

DO 1

011
012

WRITE
CONTROL

013
014

DATA OUT
REGISTER

DO Z

(LATCH)

DO 4

Sf

ill

ADDRESS REGISTER
AND INVERTERS
(LATCH)

m
WE
AS

A6

A7

FIGURE 1. MM54C920/MM74C920

* The logic diagram for the MM54C921 /MM74C921

is identical to this except that data inputs (011-0"14) are connpcted to data outputs

(001-004).

2-13

DO 3

Absolute Maximum Ratings

,

Operating Conditions

(Note 1)

7V
Supply Voltage, Vce
Voltage at Any Pin
-o.3V to VCC + 0.3V
--{i5°C to +150°C
Storage Temperature Range
Package Dissipation
500mW
300°C
lead Temperature (Soldering, 10 seconds)

DC Electrical Characteristics
SYMBOL

PARAMETER

VIH

Logical "1" Input Voltage

VIL

Logical

VOHl

Logical "1" Output Voltage

Supply Voltage (VCC)
MM54C920, MM54C921
MM74C920, MM74C921
MM74C920·3, MM74C921·3
Ambient Temperature (T A)
MM54C920, MM54C921
MM74C920, MM74C921
MM74C920·3, MM74C921·3

Logical "1" Output Voltage

VOll

logical

VOl2

logical

III

Input leakage

10

Output leakage

"a .. Output Voltage
"a" Output Voltage

CONDITIONS

UNITS

4.5
4.5
4.75

5.5
5.5
5.25

V
V
V

+125
+85
+70

°c
°e
°c

-55
-40
0

MM54C920

MM74C920

MM74C920-3

MM54C921

MM74C921

MM74C921·-3

MIN

MAX

MIN

MAX

MIN

MAX

Vee- 2 .O

Vee

Vee-2.O

Vee

Vec-l.5

Vce

a

0.8

a

0.8

a

0.8

2.4

2.4

10H = -1 mA
10UT=

MAX

(Note 2)

"a" Input Voltage

VOH2

MIN

a

Vec-O.l

2.4

a

V

V

0.4

0.01

V

V

Vcc-0. 1

Vcc-O.l
0.4

10l = 2 mA

UNITS

0.4

0.01

V

0.01

V

OV ~ VIN ~ VCC

-1.0

1.0

-1.0

1.0

-1.0

1.0

pA

OV ~ Vo ~ Vce,

-1.0

1.0

-1.0

1.0

-1.0

1.0

pA

100

pA

0.01 (typ)

pA

10UT=

CEl = VCC
lec

Supply Leakage Current

10

20

VIN = VCC, ST = OV,
VO=OV

VDR

VCC for Data Retention

(Note 3)

lOR

ICC for Data Retention

CEl = VCC = 2V,
Typical at 25°e

Capacitance

(Note 4)

SYMBOL

PARAMETER

2.0

2.0

2.0

0.01 (typ)

CONDITIONS

CIN

Input Capacitance

VIN = OV, f = 1 MHz, T A = 25°C

Co

Output Capacitance

CliO

Data Input/Output Capacitance

V

O.Ol(typ)

MIN

TYP

MAX

UNITS

4

7

pF

VIN = OV, f = 1 MHz, T A = 25°C

6

9

pF

~M54C921

8

12

pF

/MM74C921 Only

Note 1: "Absolute Maximum Ratings" are those values above which the device may be permanently damaged. They do not mean the device may
be operated at these values.
Note 2: These limits apply over the entire operat~ng range specified in the "Operating Conditions" unless otherwise stated:
Note 3: CEl = VCC - 2V or = 2V, whichever is greater.
Note 4: Capacitance is guaranteed by periodic testing.

2·14

Truth Table

ST

-CES*

-

CEl

WE

01*

FUNCTION

X

X

1

X

X

Output in Hi-Z state

0

1

X

X

X

Output in Hi-Z state

X

X

X

0

X

Output in Hi-Z state

0

0

0

0

0

Write "0", output in Hi-Z state

0

0

0

0

1

Write "1", output in Hi-Z state

0

0

0

1

X

Read data, output enabled

*Set-up and hold times must be met
X = don't care

,

AC Electrical Characteristics
SYMBOL

(Note 5)
MM54C920

MM74C920

MM54C921

MM74C921

PARAMETER

MIN

MAX

MIN

MM74C920-3
MM74C921-3

MAX

MIN

UNITS

MAX

tc

Cycle Time

tACC

Access Time From Address

275

250

325

ns

tACS

Access Time From Strobe

250

225

300

ns

tAS

Address Set-Up Time

25

25

25

ns

tAH

Address Hold Time

25

25

25

ns

tOE

Output Enable Time

150

130

130

ns

too

Output Disable Time

150

130

130

ns

-

290

255

330

ns

tST

ST Pulse Width (Negative)

150

130

165

ns

tST

ST Pulse Width (Positive)

140

125

165

ns

twp

Write Pulse Width (Negative)

150

130

165

ns

tDS

Data Set-Up Time

100

90

90

ns

tDH

Data Hold Time

60

60

60

ns

Note 5: These limits apply over the operating range specified in the "Operating Conditions" with tRISE
50 pF.

2-15

=

tFALL

=

5 ns, load

=

1 TTL gate +

Switching Time Waveforms

'ST
'ST
AO-AI

m:
1 - - - - - - - - - ' A C C - - - - - - - - - - 1 r-_ __
I
DOUT

- - - - - - - - - - - - - TRI-STATE-------------

,'---*twp (the Write Pulse Width) is the time
coincidentally low

FIGURE 2. Read Cycle (WE = VIH)

ST, eEL and WE are

FIGURE 3. Write Cycle

m

'DE---j,
____ l!!-sl.All..® _ _

FIGURE 4. Output Enable/Disable

2-16

_

-(
....
-_-_-_-_-_-_-_-

Typical Performance Characteristics
Access Time vs Ambient
Temperature

Access Time vs Power Supply
Voltage

400

300
TA .125 o e
250

300
200
]

200

-

vee=~:"--

L>

:f-

~.J-:::t:::~~

100

-

"

150

:f100

r---...

50

I

o

o
-55-40

0

25

85

3

125

4.5

3.5

Minimum Write Pulse Width
vs Ambient Temperature

Data-In Setup Time vs
Ambient Temperature

200

125

100

150

~

5.5

Vee (V)

TArt)

~

r-- :--- r--

--

75
100
c

Vee
50

50
25

=4.5V

-;::::::::. :::::: ~;;-

o
-55-40

0

25

85

125

TAce)

Minimum ST Pulse Width
(Positive) vs Ambient
Temperature

Data In Hold Time vs
Ambient Temperature

~

100

200

75

150

-;:. .100

50

It'
Vee
25

=4.5V _

I---

50

1--

r-r-55 -40

H--t-~""F'-+----t--=:=I-I

Vee = 5.5V
0

25

85

125

TAn)

Address Setup Time vs
Ambient Temperature

Address Hold Time vs
Ambient Temperature

-;,

40

30

30

25

20

CI)

Vee

:f-

=

15

:f-

4.5V

V"TV-

10

-5

o
-55-40

85

125

Vee = 5.5V

L..L.-'-_ _ _ _--'-_ _- - ' _ - - ' ' - '

-55-40

0

25
TA re)

2-17

85

125

Typical Performance Characteristics

(Continued)
Minimum Sr Pulse Width
{Negative) vs Ambient
Temperature

Output Enable Time vs
Ambient Temperature

~

200 ,...,.......--....--.-----.----.-,

200

150 ~+-+-+----+----H

150

100

e

I-+-+--+--+----+---:::;..H

-55-40

0

25

85

r-r-..,.---r-.,.---.,.--"""T'"1

~ 100

-55-40

125

0

25

Dynamic Current vs Power
Supply Voltage {VIH = Vec.
VIL = OV)

~

2.5

-20

-12.5

.E

-10

'"

-7.5

CI

>
.....

~

)
I
TA· -5S'C

'2

./

V

1.5

I I
I I

-15

V

~

z

~

VCC'SV
-17.5

V
./

.E

.L'" ~
. . . V ~ ~-r
.~
TA • 125'C
V- +--

-5
0.5

-2.5

o

o
3

3.S

4.5

125

Output Source Current vs
Output Voltage

'rA• 215,C
'"

85

TA ('C)

TA rC)

5.5

~

~
5

VCC (V)

~

4.5

I I

4

1.5

3

2.5

VOUT (V)

Output Sink Current vs
Output Voltage
40
VCC' 5V
35
TA • -55'C
30

'2

.E

. . .V

25

.L.l--.
TA' 25'C

/ ....... ..- ~T

20

IV ~ ~+15
'/
1/~ TA • 125'C
10
///
I
I
~
o
o

0.5

1

1.5

2

2.5

Vour (V)

2·18

3

---

3.5

4

2

1.5

1

.
U Semiconductor
~National

CMOS RAMs

MM54C929/M M74C929, M M54C930/M M74C930
1024-Bit(1024 x 1)Static RAMs
General Description
The MM54C929/MM74C929 and the MM54C930/
MM74C930 1024 x 1 random access read/write memories
are manufactured using silicon-gate CMOS technology.
These RAMs are specifically designed to operate from
standard 54/74 TTL power supplies; all inputs and
outputs are TTL compatible. Data output is the same
polarity as data input. Internal latches store the address
inputs and data output. Chip select input CS1 serves
as a chip strobe, controlling address and data latching.
The Data·ln and Data·Out terminals can be tied together
for common I/O applications. Complete address decoding,
3-chip select functions (MM54C930/MM74C930) and
TR I-STATE® output allow easy memory expansion and
organization. The MM54C929/MM74C929 differs from
the MM54C930/MM74C930 only in that CS1, CS2 and
CS3 are internally connected together, providing a single
chip-select input

Versatility, high speed, and low power make these RAMs
ideal elements for use in many microprocessor, minicomputer and main-frame-memory applications.

Features
•
•
•
•
•
•
•
•

<:s.

Fast access-250 ns max
TRI-STATE outputs
Low power-1 0 pA max standby
On·chip registers
Single 5V supply
Inputs and output TTL compatible
Data retained with VCC as low as 2V
Can be operated common I/O

Connection Diagrams

Logic Symbols

Dual·ln-Line Package
16

cs

AD
VCC

AO

01

Al

WE

A2
AJ

A9

MM54C929
MM74C929

AS

A4

A7

DO

A6

GNO

A5

Order Number MM54C929J. MM74C929J
or MM74C929J-3

DO

See NS Package J16A
Order Number MM74C929N or MM74C929N-3

See NS Package N16A

TOP VIEW

Dual·ln·Line Package

m

AD
17_
CSJ

m

16

AO

DI

AJ

15 _
WE

Al
A2

Al
A2

MM54C9JO
MM74C9JO

14
13

AJ

12

A4

A9

A4

Order Number MM54C930J, MM74C930J
or MM74C930J-3

See NS Package J18A
AS
A7

Order Number MM74C930N or MM74C930N-3

See NS Package N18A

10

GND

A6
A7
AS
A9
01

11 A6

DO

A5

A5

TOP VIEW

2-19

MM54C9JO
MM74C9JO

DO

Functional Description
, Reduced-Voltage Operation

Address inputs are clocked into the input latches by the
fall ing edge of chip strobe CS1; set-up and hold times
must be observed on these input signals (see timing diagram). The true and complement address information is
fed to the row and column decoders which select one of
the 1024-bit locations. The addressed bit is fed, via a
sense amplifier, to the output register and TRI-STATE
buffer. The information is latched into the output
register 01) the rising edge of chip strobe CS1. The output is in a high impedance state when the chip is not
selected (CS2 or CS3 high) or when writing (WE low).
Output buffer control is independent of chip strobe CS1.

These memories will retain data with reduced VCC and
hence are useful for battery-backup data storage. Certain
precautions must be observed as V CC is reduced: (1)
input voltages must remain between the VCC and ground
of the_ RAM or supply latch-up can occur, (2) WR ITE
mode must be avoided, (3) during power-up of VCC,
strobe (CS for the MM74C929 and CSl for the
MM74C930) logic state must be maintained (either'
GND or VCe! while address control lines stabilize.

Logic Diagram *
AO---'
ADDRESS
A l - - - ' REGISTER
A2
AND
INVERTERS
AJ
(LATCH)
A4

STORAGE
MATRIX

10

Ol--------~----~I

00

AS A6 A7 AS A9

..The MM74C930 has 3 chip selects CS1, CS2 and CS3. The MM74C929 has these internally
-,

connected together providing a single chip select input CS.

FIGURE 1

2-20

Absolute Maximum Ratings

Operating Conditions

7V
Supply Voltage, VCC
Voltage at Any Pin
-o.3V to VCC + 0.3V
Storage Temperature Range
-65°C to +150°C
Package Dissipation
500mW
Lead Temperature (Soldering 10 seconds)
300°C

Operating Temperature Range
MM54C929, MM54C930
MM74C929, MM74C930
MM74C929·3, MM74C930-3

DC Electrical Characteristics
SYMBOL

PARAMETER

-55°C to +125°C
-40°C to +85°C
O°C to +70°C

Vee = 5V ±10%, T A = Operating Range, unless otherwise noted

CONDITIONS

MM54C929,

MM74C929,

MM54C930

MM74C930

MM74C929·3,
MM74C930-3
(NOTE 1)

MIN

MAX

MIN

MAX

MIN

VIH

Logical "l"lnput Voltage

VCC-2.0

VCC

VCC-2.0

VCC

VCC-2.0

VIL

Logical "0" Input Voltage

0

0.8

0

0.8

a

VOHl

Logical "1" Output Voltage

10H

VOH2

Logical "1" Output Voltage

lOUT = 0

VOL1

Logical "0" Output Voltage

10L = 2.0 mA

"a" Output Voltage

~

1 mA

2.4

2.4

VCC-O.l

VCe-0 . 1

VOL2

Logical

IlL

I nput Lea kage

OV -::; VIN -::; VCC

-1.0

10

Output Leakage

OV -::; Vo -::; VCC, (Note 2)

-1.0

ICC

Supply Leakage Current

VIN = VCC, Va = OV

VDR

VCC for Data Retention

(Note 3)

IDR

ICC for Data Retention

VCC = 2V, T A = 25°C, (Note 2)

0.01

lOUT = 0

MAX
VCC

V

0.8

V

2.4

V
V

VCC-O.l
0.4

0.4

UNITS

0.4
0.01

0.01

V
V

1.0

-1.0

1.0

-1.0

1.0

pA

1.0

-1.0

1.0

-1.0

1.0

pA

100

pA

pA

10

20
2.0

2.0

2.0

V

0.01

0.01

0.1

(typ)

(typ)

(typ)

Note 1: VCC = 5V ±5%.
Note 2: CS2 = CS3 = VCC or CS = VCC.
Note 3: CS2 or CS3 or CS = VCC - 2V or

= 2V, whichever is greater.

AC Electrical Characteristics
TTL Interface (VIH = VCC ~ 2V VIL

SYMBOL

= 0 8V

Vee = 5V ±10%, T A = Operating Range, unless otherwise noted

Input tRISE = tFALL

PARAMETER

= 5 ns

Load = 1 TTL Gate + 50 pF)

MM54C929,

MM74C929,

MM54C930

MM74C930

MIN

MAX

290

MIN

MAX

MM74C929-3,
MM74C930-3
(NOTE 1)
MIN
330

ns

tc

Cycle Time

tACC

Access Time From Address

tACS,tACSl

Access Time From

tAS

Address Set·Up Time

15

tAH

Address Hold Time

50

tOE

Output Enable Time

150

130

130

ns

tOD

Output Disable Time

150

130

130

ns

tcs,tcsl
(Note 4)

CS, CSl

CS, CST

Pulse Width (Negative)

255

UNITS

MAX

265

240

315

250

225

300

50

150

ns
ns

15

15

ns

ns

50

130

165

ns

tCS,tCSl

CS, CSl Pulse Width (Positive)

140

125

165

ns

twp

Write Pu~se Width (Negative)

150

130

165

ns

tDS

Data Set-Up Time, (Note 5)

150

140

140

ns

tDH

{)ata Hold Time, (Note 5)

0

0

0

ns

Note 4: Greater than minimum CS pulse width must be used when reading data from the MM54C929/MM74C929 to ensure that output TRISTATING does not occur before data becomes valid. Writing has no such limitation.
Note 5: tDS and tDH are referenced to the low-to-high transition of CSl or CS2 or CS3 or WE,whichever switches first, for the MM54C930/
MM74C930 and are referenced to the CS or WE low-to-high transition, whichever switches first, for the MM54C929/MM74C929.

2-21

Capacitance

(Note 6)

SYMBOL

PARAMETER

MIN

CONDITIONS

MAX

UNITS
pF

CIN

I nput Capacitance

VIN=O,f= 1 MHz, TA=25°C

4

7

Co

Output Capacitance

VIN = 0, f= 1 MHz, TA = 25°C

6

9

pF

Ccs

Chip Select Capacitance

MM54C929/MM74C929, MM74C929-3

8

12

pF

Note 6: Capacitance maximum is guaranteed by periodic testing.

Truth Tables
MM54C930/MM74C930

MM54C929/MM74C929
CS

WE

01

1

X

X

m

FUNCTION
Output in Hi-Z State

CS2

CS3

WE

01

FUNCTION

X

1

X

X

X

Output in Hi-Z State

X

0

X

Output in Hi-Z State

X

X

1

X

X

Output in Hi-Z State

0

0

0

Write "0," Output in Hi-Z State

X

X

X

0

X

Output in'Hi-Z State

0

0

1

Write "1," Output in Hi-Z State

0

0

0

0

0

Write "0," Output in Hi-Z State

0

1

X

Read Data, Output Enabled

0

0

0

0

1

Write "1," Output in Hi-Z State

0

0

0

1

X

Read Data, Output Enabled

x = Don't care

Switching Time Waveforms

~--~----~*---------+---------tcs--------~

AO-A9
tAS

=k

- - tAH

lACS

DOUT - -

-- - - - -

-TRI~:i~TE®-- - - -

- -

DATA OUT VALID

*Greater than minimum CS pulse width must be used when reading data from the
MM54C929/MM74C929 to ensure that output TRI-STATING does not occur before data
becomes valid. Writing has no such limitation, (Figure 4a)_
FIGURE 2a. MM54C929/MM74C929 Read Cycle

t - - - - - - - t C S 1 - - - - - - t - - - - - - tCS1-------...-j
AO-A9
t------tOE-----~~

t - - - - - - - - - - - tACS1------------<-i
t----------tACC-------------·-I ,---------------DATA OUT VALID
DOUT - - - - - - - --TRI-STATE®- - - - - - -

FIGURE 2b. MM54C930/MM74C930 Read Cycle

2·22

Switching Time Waveforms

(Continued)

~~~~~j~-------tcs--------~I

AO-A9

*twp (the Write Pulse widthl is the time

CS

and WE are coincidentally low

FIGURE 3a. MM54C929/MM74C929 Write Cycle

*twp (the Write Pulse width) is the time CS1. CS2. CS3 and WE are coincidentally low
FIGURE 3b. MM54C930/MM74C930 Write Cycle

\ - J,f.
~~--------------~
~~

..,{
J

~--------------------

-tOEDOUT -

-

-tODDATA OUT VALID

-TRI-STATE®- - -

FIGURE 4a. MM54C929/MM74C929

--tOD-

-tOEDOUT -

-

-TRI-STATE®- - -

DATA OUT VALID

FIGURE 4b. MM54C930/MM74C930

2-23

Typical Performance

Characte~istics

Access Time vs Ambient
Temperature

Access Time vs Power Supply
Voltage

400 ,..,.....-,---r----r---,.---"T"'I

300
TA ='25"C
250

H-+--+-+---I---H

300

\.

200

-

u

!u

H-+--+-+---I--+1

200

:J.

'\

150

........

C[

100

r--....

r--:- ~

50

o
-55-40

85

125

3

3.5

5.5

4.5
VCC (V)

Minimum Write Pulse Width
vs Ambient Temperature

. Data-In Set-Up Time vs
Ambient Temperature

200 """"'-,---,----r---..---""T""I

150

I+-+---+---+---+---f-j

]: 100

H-+---1-,'--+-,---+---:::H

1=

200 n--r--.---r---r--T1

~

150

f+-+---+--+---t---f-j

100

t+-+---+--+---t---f-j

50 1-I"'''1'''==---+-

OU-...L--...J....-J._ _ _.l....-_.J..j

-50-40

125

85

85

125

Minimum CSI Pulse Width
(Positive) vs Ambient
Temperature

Data-In Hold Time vs
Ambient Temperature
25 rr'---r-'---.--~

200

150
~

!

~ -25

~

100

-50

50

-75

o

--

VCC = 4.5V

I

~

-

I
VfC = 5.5V

-55-40

85

125

-55-40

Address Hold Time vs
Ambient Temperature

-;;:

30

60

20

~

40

vCC = 5.5V

-55-40

0

25

I-~CC=4.5V

t1:::::r--

--

VCC = 5.5V

f

o

10

-

f-I- vcc = 4.5V
~

125

Address Set-Up Time vs
Ambient Temperature

80

20

85

'f

-10
85

125

-55-40

TA eC)

2-24

Typical Performance Characteristics

(Continued)

Minimum CSl Pulse Width
(Negative) vs Ambient
Temperature

Output Enable Time vs
Ambient Temperature
200 n--r--"T"""--,----,----n

Dynamic Current vs Power
Supply Voltage
(VIH = VCC. VIL =OV)

200

3
TA =1 250C
:t:

150

150

2.5

~
c(

.g

0

100

50

---rr-

~

--

Vcc =4.5V
Vcc = 5.5V

25

85

1.5

V

::>

<.>

::>

o
o

25

85

125

4.5
Vec (V)

Output Sink Current vs
Output Voltage

Output Source Current vs
Output Voltage
40

-20
VCC = SV

VCC = SV
3S

I I
I I

-15
-12.S

<
.g
-10
:t:
0

4

3.5

3

TA ('C)

-17.S

-

TA = -55°C
30

T~ = j5°C

<
.g

~=2~'C

-1.S

L / k-

-S

0

f-t::C

0
S

4.5

4

3.5

3

2.5

1

I

2

1.5

. . . .V

25

5
1

hV

if'
0

VOUT (V)

0.5

1

1.5

2

2.5

VOUT (V)

2-25

-

J/ k-"'11/ / ' ......TA = 125°C

15

0

L.l--TA=25°C

/~

/

20

10

~~:,......-~ TA=125°C

-2.S ~~

V

0
-55-40

125

/'

0.5

'"

TA (OC)

V V

1

>

_"'---'I_--J._..u
0

a:
a:

100

o ............

-55-40

2

lZ

3

3.5

4

5

S.5

6

~National

CMOS RAMs

D Semiconductor

MM54C989/MM74C989 64·Bit (16 x4) TRI·STATE@ RAM
General Description
Read Operation: The complement of the information
which was written into the memory is non-destructively
read out at the 4 outputs. This is accomplished by
selecting the desired address and bringing memory enable
low and write enable high.

The MM54C989/MM74C989 is a 16-word by 4-bit
random access read/write memory. Inputs to the memory
consist of 4 address lines, 4 data input lines, a write
enable line and a memory enable line. The 4 binary
address inputs are decoded internally to select each of
the 16 possible word locations. An internal address
register latches the address information on the positive
to negative transition of the memory enable input. The 4
TR I-STATE data output lines working in conjunction
with the memory enable input provides for easy memory
expansion.

When the device is writing or disabled the output assumes
a TRI-STATE (Hi-Zl condition.

Features

Note. The timing is different than the DM7489 in that
a positive to negative transition of the memory enable
must occur for the memory to be selected.
Write Operation: Information present at the data inputs
is written into the memory at the selected address by
bringing write enable and memory enable low.

Logic

~nd

3.0V to 5.5V

• Wide supply voltage range

Address Operation: Address inputs must be stable tSA
prior to the positive to negative transition of memory
enable. It is thus not necessary to hold address information stable for more than tHA after the memory is
enabled (positive to negative transition of memory
enable).

1.0V

•

Guaranteed noise margin

•

High noise immunity

•

Low power TTL
compatibility

•

Input address register

•

Low power consumption

•

Fast access time

0.45 VCC typ
fan out of 2
driving 74L

250 nW/package typ
@VCC=5V
140 ns typ at VCC = 5V

• TRI-STATE output

Connection Diagrams
DATA
DATA
DATA
DATA
DATA
iiAfA DATA iiAfA
INPUT 1 OUTPUT 1 INPUT 2 OUTPUT 2 INPUT 3 OUTPUT 3 INPUT 4 OUTPUT 4

Dual-in-Line Package

ADDRESS
INPUT A

WRITE
ENABLE

16

1

f.IDm!Y 2

iiEiiOiiY

£JmTI

ENABLE

wmn:

3

DATA
INPUT 1

4

£JmTI
iiAfA 5

INPUT A

mPilTl

DATA
INPUT2

6

iiAfA

1

11

DATA

il"Uffljf4
10 DATA
INPUT 3
9 lim
DlJffilT3

01iTPlff2
INPUTB

•
Vee

15 ADDRESS
INPUTB
14 ADDRESS
INPUTC
13 ADDRESS
INPUT 0
12 DATA
INPUT(

GND

TOP VIEW
INPUT e

Order Number MM54C989J
or MM74C989J
See NS Package J16A

INPUTB

Order Number MM74C989N
See NS Package N16A

2-26

Absolute Maximum Ratings

Operating Conditions

(Note 1)

Voltage at Any Pin
-{).3V to VCC + 0.3V
Package Dissipation
500mW
Absolute Maximum VCC
7.0V
Lead Temperature (Soldering, 10 seconds)
300°C

DC Electrical Characteristics

Supply Voltage (VCC)
MM54C989
MM74C989
Temperature (TA)
MM54C989
MM74C989

MIN

MAX

UNITS

4.7
4.75

5.5
5.25

V
V

+125
+85

°c
°c

-55

-40

Operating V CC Range

3.0V to 5.5V

Standby VCC Range

1.5V to 5.5V

(Min/max limits apply across the temperature and power supply range indicated).

VIN(1)

Logical "1" Input Voltage

VIN(O)

Logical "0" Input Voltage

CONDITIONS

MIN

TYP

MAX

0.8
1

Logical "1"lnput Current

VIN = 5V

Logical "0" I nput Current

VIN = 0

VOUT(1)

Logical "1" Output Voltage

10 = -360pA

2.4

V

10 = -1501lA

VCC-0.5

V

10 = 360pA

VO= 5V
VO= 0

ICC

Supply Current (Active)

0.005
-1

0.4

-1

1

-0.005
0.05

pA
pA

-0.005

0.005

ME = 0,

V
pA
pA

150

pA

3

pA

VCC = 5V
Supply Current (Stand-By)

AC Electrical Characteristics

ME= 5V

MM54C989/MM74C989

T A = 25°C, VCC = 5V, CL = 50 pF
PARAMETER

MIN

TYP

MAX

UNITS

ns

tACC

Access Time From Address

140

500

tPD

Propagation Delay From ME

110

360

tSA

Address Input Set-Up Time

tHA

Address Input Hold Time

20

15

ns

tME

Memory Enable Pulse Width

200

80

ns

100

140

ns
ns

30

tME

Memory Enable Pulse Width

400

tSD

Data Input Set-Up Time

0

tHD

Data Input Hold Time

30

20

ns

tWE

Write Enable Pulse Width

140

70

ns

t1H, tOH

Delay to TRI-STATE, CL = 5 pF, RL = 10k, (Note 4)

ns
ns

100

200

ns

\

CAPACITANCE

pF

CIN

Input Capacity, Any Input, (Note 2)

COUT

Output Capacity, Any Output, (Note 2)

8

pF

CPD

Power Dissipation Capacity, (Note 3)

350

pF

5

2-27

~

V

IIN(1)

Logical "0" Output Voltage

s:
s:
""'-01

V

VCc-1.5

Output Current in High Impedance State

se

UNITS

IIN(O)

VOUT(O)

~

(')
CO
CO

(')
CO
CO
CO

MM54C989/MM74C989

PARAMETER

s:
s:
en

fill

C)

co
C)

AC Electrical Characteristics

0

MM54C989: TA = -55°C to +125°C, VCC = 4.5V to 5.5V. CL = 50 pF

1'0

MM74C989: T A = -40° C to +85° C, V CC = 4.75V to 5.25V. CL = 50 pF

~

:e
:e
a;
CO

(Continued)

MM54C989

PARAMETER

MM74C989
UNITS

MAX

MIN

MIN

MAX

C)

tACC

Access Time From Address

500

620

ns

0

tPD1, tpDO

Propagation Delay From ME

350

430

ns

tSA

Address Input Set.-Up Time

150

140

ns

tHA

Address Input Hold Time

50

60

ns

tME

Memory Enable Pulse Width

250

310

ns

tME

Memory Enable Pulse Width

520

400

ns

tSD

Data Input Set-Up Time

0

0

ns

tHD

Data Input Hold Time

60

50

ns

tWE

Write Enable Pulse Width

220

t1 H, tOH

Delay to TRI-STATE, (Note 4)

~
II)

:e
:e

180

ns

200

200

ns

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: CPD determines the no load AC power consumption for any CMOS device. For complete explanation see 54C/74C Family Characteristics
application note, AN-gO.
Note 4: See AC test circuit for tl H, tOH.

Truth Table
OPERATION

CONDITION OF OUTPUTS

L

L

Write

TRI-STATE

L

H

Read

Complement of Selected Word

H

L

I nhibit, Storage

TRI-STATE

H

H

Inhibit, Storage

TRI-STATE

AC Test Circuits
All Other AC Tests

tOH

Vee

o

..=: 10k

-

DATA
OUTPUT

--5.0pF

T

10k

=:...

-=
2-28

--.

±:.OPF

.

DATA
OUTPUT

l50PF

T

Switching Time Waveforms
Read Cycle (Note 1)

Vee

Write Cycle (Note 1)

----l--_-----...

vee---t-.l------...

MfMil1f\'

MEMORY

[NAm

ENABLE

Vee------,

Vee------"
ADDRESS
INPUT

ADDRESS
INPUT

0------./

Vee-----------..

DATA Vee----------------r~-------­

tm1i

li1Tf

our

Read-Modify-Write Cycle (Note 1)

tOH

Vee--+-.l----,

MEMORY
ENABLE

v e e - - - - -......
ADDRESS
INPUT

WRITE
ENABLE

LATCHED ADDRESS

DATA
IN

qtWE

Vee

X

-

Vee

')CHD.

' -_ _ _ __

Note 1: MEMORY ENABLE must be brought high for tME ns between every address change.

Note 2: tr = tf = 20 ns for all inputs.

2-29

~

~ ~National

B
:E

CMOS RAMs

~ Semiconductor

PRELIMINARY

z

NMC6504 4096·Bit (4096 x 1) Static RAM
General Description

Features

The NMC6504 is a static CMOS random access read/write
memory organized as 4096 words of 1 bit each. This device
is fabricated with National Semiconductor's silicon·gate
CMOS technology and is fully compatible to the TTL environment. Synchronous operation is provided by on-chip
address, data, and write latches. The ENABLE input
serves as the device strobe controlling the latching functions. The TRI-STATE@ output, in conjunction with the
ENABLE input, allows easy memory expansion.

•
•
•
•
•
•
•
•
•
•
•
•
•

Industry standard pinout
Low data retention voltage - 2V
Low speed/power product
TTL compatible - all inputs and outputs
TRI-STATE@ outputs for bus operation
High output drive
High noise immunity
Military temperature range available
On-chip address registers (latches)
Common I/O - high density packaging
Output data latches
Input data latches
Select latch for microprocessor interface

Connection Diagram

Logic Symbol

Dual-In-Llne Package

Order Number NMC6504J-2, NMC6504J-9
or NMC6504J-5
See NS Package J18A

Order Number NMC6504N-5
See NS Package N18A

n

lL

GNO

E

TOP VIEW

Pin Names

Address Inputs
Chip Enable
Write Enable
Data Input
Data Output

AO-A11

E
iN
D
Q

2-30

Functional Description
An NMC6504 memory cycle is initiated by the falling edge
of the ENABLE (E) input which latches the address information Into the on-chip registers. On-chip latches allow
selection of a read, early write, or read· modify-write cycle
as a function of the ENABLE and WRITE (W) Input levels
and timing. Data output is enabled by the failing edge of
the ENABLE input and disabled by the rising edge except
when performing an early write cycle. The input and output data latches are transparent except during the write
pulse (not the WRITE input).

An early write cycle is performed by preceding the
ENABLE with the HIGH to LOW transition of the WRITE Input. The WRITE Input level Is latched, and set-up and hold
times must be met. The data output Is not enabled during
an early write cycle. The Input data set·up and hold times
are referenced to the leading edge of the write pulse,
which is initiated by the falling edge of the ENABLE input
and terminated by the rising edge of the ENABLE.
A read-modify-write cycle is performed as a read cycle, for
the enable access time, followed by the write pulse which
is Initiated by the falling edge of the WRITE input and
terminated by the rising edge of either the ENABLE or
WRITE input, whichever occurs first. The input data set-up
and hold times are referenced to the falling edge of the
WRITE input. Data is latched when the WRITE input goes
LOW, allowing the modified data to be written into the
memory while continuing to read the original data.'

When performing a read cycle a minimum ENABLE LOW
time Is required to assure valid data at the output. This
minimum LOW time is defined as the enable access time.
A minimum ENABLE HIGH time is required to return the
columns to the HIGH state and to precharge the sense
amplifiers in preparation of the next cycle.

Block Diagram

A8----1----,
A1----I
A6----I
AD----f

ADDRESS
LATCH AND
INVERTERS

FUNCTIONS ARE POSITIVE
LOGIC
GATED
ROW
DECODER

64

64x64
ARRAY

DATA LATCHES ON RISING
EDGE OF L

At----I

(:~~}------t-----r----J

Lt~

___...

ADDRESSES AND CONTROL
LATCHES ON THE RISING
EOGE OF L

A3 A4 AS All AID A9 (MSB}

2·31

Operating Range

Absolute Maximum Ratings

Min
Supply Voltage vee

7V

Voltage at Any Pi n

Supply Voltage
NMC6504·9
NMC6504·2
NMC6504·5

+ 0.3V
+ 150·C

- 0.3V to VCC

Storage Temperature Range

-65·Cto

Package Dissipation

500mW

lead Temperature(Soldering. 10 seconds)

Temperature
NMC6504·9
NMC6504·2
NMC6504·5

300·C

Max

4.5V
4.5V
4.75V

5.5V
5.5V
5.25V

-40·C
-55·C

85·C
125·C
75·C

O·C

DC Electrical Characteristics over the operating range, unless otherwise noted
Symbol

Parameter

I-N_M~C:-:-65_0_4._9'r-'N_M~C6:-5_0_4._2-t----:-::-:--N_M_Cr65_0_4-:-.5-:-----tU nits
Min
Max
Min
Max

Conditions

V

2.0

2.0

VCCDR

Data Retention Supply
Voltage

ICCSB

Standby Supply Current

50

500

p.A

ICCOp·

Operating Supply
Current

f=1 MHz, 10=0,
VI = VCC or GND

10

10

mA

ICCDR

Data Retention Supply
Current

VCC = 3.0V, 10 = 0,
VI = VCC or GND

25

500

p.A

VI=VCC, GND

VI=VCC,GND

II

Input Leakage Current

VIL

Input Low Voltage

VIH

Input High Voltage

10Z

Output Leakage Current

VOL

Output Low Voltage

IOL=2.0 mA

VOH

Output High Voltage

10H= -1.0 mA

CI

Input Capacitance

f= 1 MHz

CO

Output Capacitance

f= 1 MHz

-1.0

+1.0
0.8 .

-0.3
VCC-2.0

c:

SENSE AMPS

SENSE AMPS

COLUMN DECODER

COLUMN DECODER

0
0
0
0
0

0
0
0
0
I

I

I

I

I

I

I

I

I

o

I

"-----1._

I
0
0
0
0
0

I
0
0
0
0
I

-

2·32

I
I
I
I
I
0

I
I
I
I
I
I

I
I
I

I
I
I

0
0
0
0
0
0

0
0
0
0
0
0

V
p.A
V

8

8

pF

10

10

pF

(MSB)
(LSB)
ROWS
A2 AI AO A6 A1 AS

I-f-J2 COLUMNS - -

+10
0.45

NMC6504 Bit Map and Address Decoding

~

VCC+0.3

V

2.4

Input Rise and Fall Times: ::520 ns
All Timing Reference Levels: 1/2 VCC
Output Load: 1 TTL Load, 50 pF

~0 0
0 0

V

0.4
2.4

AC Test Conditions

'" AIO
~ All
A5
u
A4
(LSB) AJ

p.A

0.8

-10

+1.0

* ICCOP is proportional to operating frequency.

(MSB) A9

+10

VCC-2

VCC+0.3

-1.0

VI=VCC, GND

-10
-0.3

I
I

I
I
I

I
0
0

0 i

0

I

0
0
0
0

I
I
0
0

0
0
0
0
0

I
I

1 0 0
I
0
I
0

z

3:

Read Cycle AC Electrical Characteristics over the operating range

o

0)

UI

Symbol

NMC6504·9, NMC6504·2
Min
Max

Parameter

NMC6504·5
Min
Max

Units

TAVEL

Address Set·up Time

20

20

ns

TELAX

Address Hold Time

50

50

ns

TElQV

Enable Access Time

300

350

ns

TAVQV

Address Access Time

320

370

ns

TElEH

Enable (E) Minimum low Time

300

TElEl

Read or Write Cycle Time

420

350
500 .

TEHEl

Enable (E) Minimum High Time

120

150

TElQX

Output Enable from Enable (E)

100

100

ns

TEHQZ

Output Disable from Enable (E)

100

100

ns

.
Read Cycle Waveforms

A

~

-

TElAX,

"/Y

TAVEL

/Y'x

('y')(y

'IvY

~

-

t=

'\ILXXXXX

f-TElEL
TElEH

E

"&F
'LL:li\

TEHEL

~.-

-,~
I

~

-

TELQY
TAVQV

TEHQZ

-t-

Q

..,'!----TElQX

2·33

~

ns
ns
ns

o

~

IIII:t

0

Lt')

Write Cycle AC Electrical Characteristics over the operating range

CD

0

:E

z

Symbol

NMC6504·9, NMC6504·2

Parameter

Min

Max

NMC6504·5
Min

Max

Units

TAVEL

Address Set·up Time

ns

Address Hold Time

20
50·

20

TELAX

50

ns

TWLWH

Write Pulse Width (W Low)

80

100

ns

TELEL

Read or Write Cycle Time

420

500

ns

TELEH

Enable (E) Minimum Low Time

300

350

ns

TDVWL

Data Set·up Time

TEHEL

Enable (E) Minimum High Time

TWLDX

Data Hold Time

TELWH

Write Pulse Width

TELWL

Early Write Output Hi·Z Time

TWLEH

Write Pulse Width (Wand

TELQX

Output Enable from

TELQV

Enable Access Time

TEHQZ

Output Disable from

(E and W Low)

E Low)

0

30

ns

120

150

ns

80

100

ns

80

100

ns

0

0

ns

200

E
E

250
100

ns

300

350

ns

100

100

ns

Write Cycle Waveforms

Q

------H~~~---

2·34

ns

100

z.

s:
0

Early Write Cycle AC Electrical Characteristics over the operating range

0)
Symbol

NMC6504·9, NMC6504·2
Min
Max

Parameter

en

NMC6504·5
Min
Max

Units

Address Set·up Time

20

20

ns

TELAX

Address Hold Time

50

50

ns

TELWH

Write Pulse Width (E and W Low)

80

100

ns

TDVEL

Early Write Data Set·up Time

0

30

ns

TELEH

Enable (E) Minimum Low Time

300

350

ns

lWLEL

Early Write Set·up Time

0

0

ns

TEHEL

Enable (E) Minimum High Time

120

150

ns

TELDX

Early Write Data Hold Time

TELEL

Read or Write Cycle Time

TAVEL

80

100

ns

420

500

ns

Early Write Cycle Waveforms

-------------Hi·Z------------

2·35

0

.a:a.

-.::t

0
Lt)
CO

Read·Modify·Write Cycle AC Electrical Characteristics over the operating range

0

~

Z

Symbol
TAVEL

NMC6504·9, NMC6504·2
Min
Max

Parameter
Address Set·up Time

NMC6504·5
Max
Min

Units

20

20

ns

50

50

ns

TElAX

Address Hold Time

TElaV

Enable Access Time

300

350

ns

TAVaV

Address Access Time

320

370

ns

TEHEl

Enable (E) Minimum High Time

TWHEl

iN Read Mode Set·up Time
Write Pulse Width (iN and E low)

TWlEH

120

150

0

0

ns

200

250

ns

ns

0

0

ns

80

100

ns

80

100

TaVWl

Data Valid to Write Time

TWlWH

Write Pulse Width

TWlDX

Data Hold Time

TElaX

Output Enable from Enable (E)

100

100

ns

TEHaZ

Output Disable from Enable (E)

100

100

ns

TDVWl

Data Set·up Time

Read·Modify~Write

(iN low)

0

ns

30

ns

Cycle Waveforms

t----TWlEH - - - - t - - - - - 1 E H E l - - - - - i

TOVWl

o--------------~~~r-----~~------------~----------

2-36

z
o

~National

CMOS RAMs 3:

~ Semiconductor

0)'

01

o
co

NMC65081024·Bit (1024 x 1) Static RAM
General Description

Features

The NMC6508 is a static CMOS random access read/write
memory organized as 1024 words of 1 bit each. This device
is fabricated with National Semiconductor's silicon-gate
CMOS technology and is fully compatible to the TTL environment. Synchronous operation is provided by the onchip latches for the address inputs. The NMC6508 may be
used in common I/O applications by externally connecti ng
the data input and output terminals. The TRI·STATE"] out·
put, in conjunction with the ENABLE input, allows for easy
memory expansion.

•
•
•
•
•

Industry standard pinout
Low data retention voltage - 2V
Low speed/power product
TTL compatible - all inputs and outputs
TRI·STATE" outputs for bus operation

•
•
•
•
•
•

High output drive
High noise immunity
Military temperature range available
On-chip address registers (latches)
16 pin - high density packaging
Output data latches

Connection Diagram

Logic Symbol

Dual·ln·Line Package

16

E

vee

AD

, AD
Al
A2

A9

AJ

A4
10

a
GND

A6

a

AS

TOP VIEW

Order Number NMC6508J·2, NMC6508J·9
or NMC6508J·5
See NS Package J18A
Order Number NMC6508N·5
See NS Package N18A
Pin Names
AO-A9

E
IN
D
Q

Address Inputs
Chip Enable
Write Enable
Data Input
Data Output
2·37

00

o
II)
CO

o

:E

z

Functional Description
return the columns to the HIGH state and to precharge
the sense amplifiers in preparation of the next memory
cycle.

An NMC6508 memory cycle is initiated by the falling edge
of the ENABLE (E) input, which latches the address information into the on-chip registers. The output buffer is
enabled when the WRITE (W) input is HIGH and the
ENABLE input is LOW.

When performing a write cycle, the minimum ENABLE
LOW time is required to enter new data. The write pulse is
created by the coincident LOW of the ENABLE and
WRITE inputs. The data set-up and hold times are
referenced to the rising edge of either the ENABLE or
WRITE input, whichever occurs first.

When performing a read cycle a minimum ENABLE LOW
time is required to assure valid data at 'the output. This
minimum LOW time is defined as the device enable access time. A minimum ENABLE HIGH time is required to

Block Diagram

FUNCTIONS ARE POSITIVE
LOGIC
32 x 32
ARRAY

DATA LATCHES ON FALLING

EDGEOF"~

TRI·STATE®
OUTPUT
BUFFER

o

ADDRESS
LATCH AND
INVERTERS

ADDRESSES ARE
LATCHED ON THE RISING
EDGE OF L

A3 A4 AS A6 A7 (MSB)

2·38

Absolute Maximum Ratings
Supply Voltage VCC

7V

Voltage at Any Pin

-0.3VtoVCC +0.3V

Storage Temperature Range

Z

Operating Range
-65'Cto +150'C

Package Dissipation

500mW

Lead Temperature (Soldering. 10 seconds)

300'C

Min

Max

Supply Voltage
NMC6508B·9
NMC6508B·2
NMC6508-9
NMC6508-2
NMC6508·5

4.5V
4.5V
4.5V
4.5V
4.75V

5.5V
5.5V
5.5V
5.5V
5.25V

Temperature
NMC6508B·9
NMC6508B·2
NMC6508-9
NMC6508·2
NMC6508-5

-40'C
-55'C
-40'C
-55'C
O'C

85'C
125'C
85'C
125'C
75'C

DC Electrical Characteristics over the operating range, unless otherwise noted
Symbol

Parameter

NMC6508B·9, NMC6508B·2
NMC6508·9, NMC6508·2
Min
Max

Conditions

VCCDR

Data Retention Supply
Voltage

ICCSS

Standby Supply Current

ICCOP'

Operating Supply
Current

ICCDR

VI=VCC,GND

NMC6508·5
Min

Units

Max

2.0

2.0

V

10

100

p.A

f=1 MHz, 10=0,
VI = VCC or GND

4

4

mA

Data Retention Supply
Current

VCC = 3.0V, 10 = 0,
VI = VCC or GND

10

100

p.A

VI=VCC, GND

II

Input Leakage Current

VIL

Input Low Voltage

VIH

Input High Voltage

10Z

Output Leakage Current

VOL

Output Low Voltage

IOL=3.2 mA

VOH

Output High Voltage

10H= -0.4 mA

CI

Input Capacitance

f= 1 MHz

CO

Output Capacitance

f = 1 MHz

-1.0

+1.0

-1.0

+1.0

p.A

-0.3

0.8

-0.3

0.8

V

VCC-2.0
VI=VCC, GND

-1.0

VCC-2

VCC+0.3

p.A

0.4

V

6

6

pF

10

10

pF

0.4
2.4

AC Test Conditions
Input Rise and Fall Times: :::;20 ns
All Timing Reference Levels: 1/2 VCC
Output Load: 1 TTL Load, 50 pF

NMC6508 Bit Map and Address Decoding
(MSB) ROWS (LSB)
A9 AS A2 AI AD

16 COLUMNS - -

D D
D
D
D D
D D
D D

0
0

r
SENSE AMPS

SENSE AMPS

COLUMN DECODER

COLUMN DECODER

~D DOD
~A600
.11
AS 0 0
1 1
3A400
II
(LSB) A3 0 1
0 1
~~

(MSBI A7

3

rI -I - - - -1 -I
o
o
o

o

0 •
0
0
1

•

'2·39

•

-

1
1
I
0

V

2.4

~

1
1
I
I

V

+1.0

-1.0

+1.0

*ICCOP is proportional to operating frequency.

-

VCC+0.3

D
D
0
0
1
I

0
D
1
1
0
D

D
1
D
1
D
I

0
1

I

1

1

I

1

1

1

1

3:

00)

~

CO

co
o
II)

Read Cycle AC Electrical Characteristics over the operating range

CO

o

:E

z

Symbol

NMC6508B·9
NMC6508B·2
Min
Max

Parameter

NMC6508·9
NMC6508·2
Min
Max

NMC6508·5
Min

0

0

10

40

50

70

Units

Max
ns

TAVEL

Address Set·up Time

TELAX

Address Hold Time

TElOV

Enable Access Time

180

250

300

ns

TAVOV

Address Access Time

180

250

310

ns

TElEH

Enable (E) Minimum low Time

TElOX

Output Enable from Enable (E)

120

160

200

ns

Output Disable from Enable (E)

120

160

200

ns

TEHOZ
TEHEl
TElEl

180

280

Read or Write Cycle Time

300

250

100

Enable (E) Minimum High Time

A

TELAX,

100

ns

350

450

ns

-

t:::
Y'XX'X'/

~

YXX'A'

"

I

TAVEL

I-TELEL
TEHEL

TELEH

E

~Ir
1\

~~
~

-.'f-

7

-

TElQY
TAVQV
~I(

Q

TEHQZ

:....l~

-:If-

t---TElQX

-

2·40

ns

150

Read Cycle Waveforms

~

ns

Z

Write Cycle AC Electrical Characteristics over the operating range
Symbol

NMC6508B·9
NMC6508B·2
Min
Max

Parameter

TAVEL

Address Set·up Time

TELAX

Address Hold Time

TEHEL

Enable (E) Minimum High Time

NMC6508·9
NMC6508·2
Min
Max

3:

0
0)
NMC6508·5
Min

Units

Max

(X)

0

0

10

40

50

70

ns

100

100

150

ns

ns

TDVWH

Data Set·up Time

80

110

130

ns

TELWH

Write Pulse Width (E and Vi Low)

100

130

160

ns

1WLWH

Write Pulse Width (Vi Low)

100

130

160

ns

TELEL

Read or Write Cycle Time

280

350

450

ns

1WHDM

Data Hold Time

0

0

0

ns

1WLEH

Write Pulse Width (E and

100

130

160

ns

TELEH

Enable (E) Minimum Low Time

180

250

300

TELOX

Output Enable from

1WLOZ

Output Disable from

E

Vi Low)

ns

120

160

200

ns

120

160

200

ns

1WHOX

Vi
Output Enable from Vi

120

160

TEHOZ

Output Disable from

E

120

160

200
200

ns

Write Cycle Waveforms

Q---------+~~~--------~~~--------------

2·41

U1

0

ns

co

~

Read·Modify-Write Cycle AC Electrical Characteristics over the operating range

CD

0

:E

Z

Symbol

Parameter

NMC6508B·9
NMC6508B·2
Min
Max

NMC6508·9
NMC6508·2
Min
Max

NMC6508·5
Min

0

0

10

40

50

70

TAVEL

Address Set·up Time

TELAX

Address Hold Time

TELOV

Enable Access Time

180

TAVOV

Address Access Time

180

TEHEL

Enable (E) Minimum High Time

TWHDM

Data Hold Time

250
250

Units

Max
ns
ns

300
310

ns
ns

100

100

150

ns

0

0

0

ns

TOVWL

Data Valid to Write Time

0

0

0

ns

TWHEL

0

0
130

0

ns

TWLWH

WRead Mode Set-up Time
Write Pulse Width (W Low)

TELOX

Output Enable from Enable (E)

120

160

TEHOZ

Output Disable from Enable (E)

120

TWLOZ

Output Disable from Write (W)

120

TDVWH

Data S~t-up Time

TWHOX

Output Enable from Write (W)

100

80

160

ns

160

200

ns

160

·200

ns

200

ns

130

110
120

160

Read·Modify·Write Cycle Waveforms

* Output enable can be avoided by preceding the rising edge of iN with the rising edge of Eby time; TEHQZ

2-42

ns

200

ns

~National

CMOS RAMs
PRELIMINARY

~ Semiconductor

z

s:
o
en

en
......

~

NMC6514 4096-Bit (1024 x 4) Static RAM
General Description

Features

The NMC6514 is a static CMOS random access read/write
memory organized as 1024 words of 4 bits each. This
device is fabricated with National Semiconductor's
silicon·gate CMOS technology and is fully compatible
with the TIL environment. Synchronous operation is pro·
vided by on·chip address latches. The ENABLE input
serves as the device strobe controlling the address
latching function. The data I/O terminals, when not output
data enabled, represent a high impedance for easy
memory expansion.

•
•
•
•
•

Industry standard pinout
Low data retention voltage - 2V
Low speed/power product
TIL compatible - all inputs and outputs
TRI·STATE@ outputs for bus operation

•
•
•
•
•

High output drive
High noise immunity
Military temperature range available
On·chip address registers (latches)
Common I/O - high density packaging

Connection Diagram

Logic Symbol

Dual·ln·Llne Package

A6

Order Number NMC6514J·2, NMC6514J·9
or NMC6514J·5
See NS Package J18A

AS
A4
AJ

Order Number NMC6514N·5
See NS Package N18A

AD
At
A2

Pin Names

Address Inputs
Chip Enable
Write Enable
Data In/Out

AO-A9

E

GND

iN
TDP VIEW

DQO-DQ3,

2·43

~

.....
CD
o
it)

:E

z

Functional Description
An NMC6514 memory cycle is initiated by the falling edge
of the ENABLE (E) input, which latches the address information into the on-chip registers. Read, write, the readmodify-write cycles are selected as a function of the
ENABLE and WRITE (W) input levels and timing. Data out·
put is enabled by the falling edgeof the ENABLE input and
disabled by the rising edge when theWRITE input is HIGH.
The output is disabled when writing.

When performing a write cycle a minimum ENABLE LOW
time is required to enter the new data. The write pulse is
created by the coincident LOW of the ENABLE and
WRITE inputs. The data set-up and hold time are
referenced to the rising edge of either the ENABLE or
WRITE inputs whichever occurs first.
A read-modify-write cycle is performed as a read cycle, for
the enable access time, followed by the write pulse
caused by the LOW time of the WRITE input. The output
data is disabled by the falling edge of the WRITE input,
and input data, meeting the set·up and hold requirements
must be provided.

When performing a read cycle a minimum ENABLE LOW
time is required to assure valid data at the output. This
minimum LOW time is defined as the device enable access time. A minimum ENABLE HIGH time is required to
return the columns to the HIGH state and to precharge
the sense amplifiers in preparation of the next cycle.

Block Diagram

~----....

A9

FUNCTIONS ARE POSITIVE
LOGIC

AS

A7
A6

ADDRESS
LATCH AND
INVERTERS

12

GATED
ROW
DECODER

64

64 x 64
ARRAY

A5

~----------~----~64~----------------~

ADDRESSES
LATCH ON THE
RISING EDGE OF L

>---I--t-....+-+-+- DIlD

>-t--___

~t-Dlll

>-----+-----....+_ 0112
>--+---~..._

...--........

~----

AD AI A2 Al

2-44

(MSB)

TRI·STATE@
OUTPUT
BUFFERS

Dill

Absolute Maximum Ratings
Supply Voltage VCC

7V

Voltage at Any Pin

-65'Cto +150'C

Package Dissipation

500mW

Lead Temperature(Soldering, 10 seconds)

Temperature
NMC6514·9
NMC6514·2
NMC6514·5

300'C

3:

Min

Max

4.5V
4.5V
4.75V

5.5V
5.5V
5.25V

-40'C
-55'C
O'C

85'C
125'C
75'C

DC Electrical Characteristics over the operating range, unless otherwise noted
Symbol

Parameter

NMC6514·9, NMC6514·2
Max
Min

Conditions

NMC6514·5
Min
Max

Units

VCCDR

Data Retention Supply
Voltage

ICCSS

Standby Supply Current

50

500

p.A

ICCOp·

Operating Supply
Current

f=1 MHz, 10=0,
VI = VCC or GND

10

10

mA

ICCDR

Data Retention Supply
Current

VCC = 3.0V, 10 = 0,
VI = VCC or GND

25

500

p.A

VI =VCC, GND

VI = VCC, GND

II

Input Leakage Current

VIL

Input Low Voltage

VIH

Input High Voltage

IOZ

Output Leakage Current

2.0

2.0

V

-1.0

+ 1.0

-10

+10

p.A

-0:3

0.8

-0.3

0.8

V

VCC-2:0
VI =VCC, GND

VCC+0.3

-1.0

VCC-2

VCC+0.3

-10

+1.0

V

+10

p.A

0.4

V

VOL

Output Low Voltage

IOL=2.0 mA

VOH

Output High Voltage

IOH= -1.0 mA

CI

Input Capacitance

f=1 MHz

8

8

pF

CO

Output Capacitance

f=1 MHz

10

10

pF

0.4
2.4

2.4

V

• ICCOP is proportional to operating frequency.

AC Test Conditions
Input Rise and Fall Times: ::520 ns
All Timing Reference Levels: 1/2 VCC
Output Load: 1 TIL Load, 50 pF

NMC6514 Bit Map and Address Decoding

f--

16 COLUMNS-!---16 COLUMNS-

1"

(LSB)
(MSB)
ROWS
A4 A5 A6 Al AS A9

''''.''-1--- """.,,-

1
1

0

0

0
0
0

0

0

0

0

0

0

0

0
0

I

SENSE AMPS

SENSE AMPS

COLUMN DECDDER

COLUMN DECODER

'.~.,~[

•

1

0

0

1

0

0

I

0
0

0

:;;

AI

0

0

~

AO

0

0

(LSB) A3

0

1

1

I

SENSE AMPS

SENSE AMPS
COLUMN DECODER

COLUMN DECODER

·3·:
1

1

[0
~ .. :

~~'3':

0

0

I

0

0

1

0

1

1

0

1

1

2·45

I
1

1
1

1
0

.

"

j

I

1
1

1

~

...~

0

0)

Supply Voltage
NMC6514·9
NMC6514·2
NMC6514·5

-O.3VtoVCC +O.3V

Storage Temperature Range

Z

Operating Range

00

1
1

1

0

0
1

0

0

C11

...a.
~

,..
~

ll)

Read Cycle AC Electrical Characteristics over the operating range

CD

0

:E
Z

Symbol

NMC6514·9, NMC6514·2
Min
Max

Parameter

NMC6514·5
Min
Max

Units

TAVEL

Address Set·up Time

20

20

TELAX

Address Hold Time

50

50

TElOV

Enable Access Time

300

350

ns

TAVOV

Address Access Time

320

370

ns

TElEH

Enable (E) Minimum low Time

300

350

TEHEL

Enable (E) Minimum High Time

120

150

TElOX

Output Enable from Enable (E)

100

100

ns

TEHQZ

Output Disable from (E)

100

100

ns

TElEL

Read or Write Cycle Time

420

500

Read Cycle Waveforms

-

TAVEL

~

J-----------TELEL----------J
I------TELEH-----t-----TEHEL---~

-lJ
1 - - - - - - TELQY - - - - - - I

I-----+---TAVQV

TEHQZ

----~

Q

OQ

I---TELQX

2·46

r--

ns
ns

ns
ns

ns

Z

3:

Write Cycle AC Electrical Characteristics over the operating range

Symbol

NMC6514·9, NMC6514·2
Min
Max

Parameter

NMC6514·5
Max
Min

0Q)
en
..,.,.
Units

TAVEL

Address Set·up Time

20

20

TELAX

Address Hold Time

50

50

ns

TWLEH

Write Pulse Width (E and W Low)

300

350

ns

ns

TEHEl

Enable (E) Minimum High Time

120

150

ns

TWLWH

Write Pulse Width (W low)

300

350

ns

420

TElEl

Head or Write Cycle Time

TWHOX

Output Enable from Write (Vii)

100

100

ns

TElOX

Output Enable from Enable (E)

100

100

ns

TEHOZ

Output Disable from Enable (E)

100

100

ns

TWLOZ

Output Disable from Write (Vii)

100

100

ns

TDVWH

Data Set·up Time

TWHDZ

Data Hold Time

TElWH

Write Pulse Width (E and

iN low)

500

ns

200

250

ns

0

0

ns

300

350

ns

Write Cycle Waveforms

~---------------------------TELEL-------------------------~~

______ 1----------- TELWH------------f

* Avoid bus contention

2·47

t-------TEHEL------I

.a::.-

~
,...

ll)

Read·Modify·Write Cycle AC Electrical Characteristics over the operating range

CD

0

:E
Z

Symbol

NMC6514·9, NMC6514·2

Parameter

Min

Max

NMC6514·5
Min

Max

Units

TAVEL

Address Set·up Time

20

20

ns

TELAX

Address Hold Time

50

50

ns

TELaV

Enable Access Time

300

350

ns

TAVaV

Address Access Time

320

370

ns

lWLaZ

Output Disable from Write (W)

100

ns

TDVWH

Data Set·up Time

lWHDX

Data Hold Time

lWLEH

Write Pulse Width (Wand E Low)

TaVWL

Data Valid to Write Time

lWLWH

Write Pulse Width (W Low)

TELaX

Output Enable from Enable (E)

TEHEL

Enable (E) Minimum High Time

lWHEL

W Read Mode Set·up Time

100
200

250

ns

0

0

ns

300

350

ns

0

0

ns

300

350
100
150

ns

0

0

ns

i------TWLEH-------i

2·48

ns

120

Read·Modify·Write Cycle Waveforms

* Avoid bus contention

ns

100

z
oCD

~National

CMOS RAMs 3:

~ Semiconductor

.....

(J1

CO

NMC65181024·Bit (1024 x 1) Static RAM
General Description

Features

The NMC6518 is a static CMOS random access read/write
memory organized as 1024 words of 1 bit each. This device
is fabricated with National Semiconductor's silicon·gate
CMOS technology and is fully compatible with the TIL en·
vironment. Synchronous operation is provided by the on·
chip latches for the address inputs and data output. The
ENABLE input serves as the device strobe controlling the
latching functions. The TRI·STATE@ output, in conjunc·
tion with the ENABLE input, allow easy memory
expansion.

•
•
•
•
•
•
•
•
•
•
•

Industry standard pinout
Low data retention voltage - 2V
Low speed/power product
TIL compatible - all inputs and outputs
TRI·STATE@ outputs for bus operation
High output drive
High noise immunity
Military temperature range available
On·chip address registers (latches)
18 pin - high density packaging
Output data latches

Connection Diagram

Logic Symbol

Dual·ln·Line Package

AD
A1
A2
AJ

o

A4
A9

0
10

GND

W E S1 S2
AS

TOP VIEW

Order Number NMC6518J·2, NMC6518J·9
or NMC6518J·5
See NS Package J16A
Order Number NMC6518N·5
See NS Package N16A
Pin Names

AO-A9

E

IN
D
Q

Si,S2

Address Inputs
Chip Enable
Write Enable
Data Input
Data Output
Chip Selects
2·49

co
.....
II)
CD

o
:E
z

Functional Description
An NMC6518 memory cycle is initiated by the failing edge
of the ENABLE input, which latches the address Information Into the on-chip registers. Data output is enabled
when the WRITE (W) input is high and the ENABLE,
SELECT 1 (51) and SELECT 2 (82) inputs are LOW.

precharge the sense amplifiers in preparation of the next
cycle.
When performing a write cycle, the minimum ENABLE
LOW time Is required to enter new data. The write pulse is
created by the coincident LOW of the WRITE, ENABLE
and both SELECT Inputs. The input data set·up and hold
times are referenced to the rising edge of the WRITE,
ENABLE, SELECT 1 or SELECT 2 inputs, whichever oc·
curs first.
.

When performing a read cycle a minimum ENABLE LOW
time is required to assure valid data at the output. This
minimum ENABLE LOW time is defined as the device
enable access time. A minimum ENABLE HIGH time Is
required to return the columns to the HIGH state and to

Block Diagram

FUNCTIONS ARE POSITIVE
LOGIC

AD

A1

A2
A8

ADDRESS
LATCH AND
INVERTERS

1D

GATED
ROW
DECODER

32

32 x 32
ARRAY

DATA LATCHES ON FALLING
EDGE OF '"L'"

INPUT (WRITE)
CONTROL

D------------------------~ ~--_+--~

w

GATED
COLUMN
DECODER
AND I{O

DATA
OUTPUT
LATCH

ADDRESS
LATCH AND
INVERTERS

ADDRESSES ARE
LATCHED ON THE RISING
EDGE OF L

A3 A4 AS A6 A7 (MSB)

2·50

TRI·STATE®
OUTPUT
BUFFER
Q

Absolute Maximum Ratings
Supply Voltage VCC

7V

Voltage at Any Pin

- 0.3V to VCC + 0.3V

Storage Temperature Range

Z

Operating Range
-65'Cto +150'C

Package Dissipation

500mW

Lead Temperature (Soldering. 10 seconds)

300'C

Min

Max

Supply Voltage
NMC6518B·9
NMC6518B·2
NMC6518·9
NMC6518·2
NMC6518·5

4.5V
4.5V
4.5V
4.5V
4.75V

5.5V
5.5V
5.5V
5.5V
5.25V

Temperature
NMC6518B·9
NMC6518B·2
NMC6518·9
NMC6518·2
NMC6518·5

-40'C
-55'C
-40'C
-55'C
O'C

85'C
125'C
85'C
125'C
75'C

3:

0
m
c.n
~

CO

DC Electrical Characteristics over the operating range, unless otherwise noted
Symbol

Parameter

NMC6518B·9, NMC6518B·2
NMC6518·9, NMC6518·2
Min
Max

Conditions

NMC6518·5
Min

Units

Max

VCCDR

Data Retention Supply
Voltage

ICCSS

Standby Supply Current

10

100

p.A

ICCOP'

Operating Supply
Current

f=1 MHz, 10=0,
VI = VCC or GND

4

4

mA

ICCDR

Data Retention Supply
Current

VCC = 3.0V, 10 = 0,
VI = VCC or GND

10

100

p.A

VI=VCC, GND

p.A

VI=VCC, GND

2.0

2.0

V

II

Input Leakage Current

VIL

Input Low Voltage

-1.0

+1.0

-1.0

+1.0

-0.3

0.8

-0.3

0.8

VIH

Input High Voltage

V

VCC+0.3

V

10Z

Output Leakage Current

VI=VCC, GND

VOL

Output Low Voltage

IOL=3.2 mA

VOH

Output High Voltage

10H = -0.4 mA

CI

Input Capacitance

f= 1 MHz

6

6

pF

CO

Output Capacitance

f= 1 MHz

10

10

pF

VCC-2.0
-1.0

VCC-2

VCC+0.3

-1.0

+1.0

* ICCOP is proportional to operating frequency.

AC Test Conditions
Input Rise and Fall Times: :520 ns
All Timing Reference Levels: 1/2 vce
Output Load: 1 TTL Load, 50 pF

NMC6518 Bit Map and Address Decoding

~

(MSB) ROWS (LSB)
A9 AD A2 Al AD

' - 16COLUMNS ~

0
0
1
1
0
0

0
1
0
1

0
0

0
0
0
0
1
1

1
1

1
1

1
1

0
1

0
0
0

0

(MSB) A7

SENSE AMPS

SENSE AMPS
COLUMN DECODER

~0 0
0 0

~ A6

0

0

A5

0

0

~

SA400

•

1

1

1

1

11

(LSB)A3~~

r
- - - -1 -1
1 1
o
o
o

0
0
·0

1
1
1

o 1

-

0

2·51

1
1
1
1

0
1

p.A
V
V

2.4

2.4

COLUMN DECODER

+1.0
0.4

0.4

fJI

co
"I"""

It)

co

Read Cycle AC Electrical Characteristics over the operating range

o

:E

z

Symbol

NMC6518B·9
NMC6518B·2
Min
Max

Parameter

TAVEL

Address Set·up Time

TElAX

Address Hold Time

NMC6518·9
NMC6518·2
Min
Max

NMC6518·5
Min

Units

Max

0

0

10

ns

40

50

50

ns

TELOV

Enable Access Time

180

250

300

ns

TAVOV

Address Access Time

180

250

310

ns

TElEH

Enable (E) Minimum low Time

180

250

300

ns

TELEl

Read or Write Cycle Time

280

350

450

ns

TEHEl

Enable (E) Minimum High Time

100

100

150

TSHOX

Chip Select Output Disable Time

120

160

200

ns

TSLOX

Chip Select Output Enable Time

120

160

200

ns

ns

Read Cycle Waveforms

A

-

TAVEL

TELAX

t---

,

'W
ITELEL
TELEH

E

TEHEL

I

~t
TAvav

~~

~

TELav
S::.(

-'t-:lr

a

__

~TSl.X~

~

Sl. S2

2·52

Z

Write Cycle AC Electrical Characteristics over the operating range

3:

00)
(J1
Symbol

NMC6518B·9
NMC6518B·2
Min
Max

. Parameter

TAVEL

Address Set·up Time

TELAX

Address Hold Time

TWLWH Write Pulse Width

(W Low)

NMC6518·9
NMC6518·2
Min
Max

..A.

NMC6518·5
Min

Units

Max

0

0

10

40

50

50

ns

100

130

160

ns

ns

280

350

450

ns

TWLSH Chip Select Write Pulse Set·up Time

100

130

160

ns

TWLEH Chip Enable Write Pulse Set·up Time

100

130

160

ns

TSLWH Chip Select Write Pulse Hold Time

100

130

160

ns

0

0

0

ns
ns

TELEL

Read or Write Cycle Time

TWHDX Data Hold Time
TDVWH Data Set·up Time

80

110

130

TEHEL

Enable (E) Minimum High Time

100

100

150

ns

TELEH

Enable (E) Minimum Low Time

180

250

300

ns

100

130

160

ns

TELWH Write Pulse Width

(E and W Low)

CO

Write Cycle Waveforms

fJI

o ____________

~

______________

~H~i.Z~

___________________________

* TWLWH, thewrite pulse,ls coincidence low of E, W, 51, and S2lnputs

2·53

co
orU)

Read·Modify·Write Cycle AC Electrical Characteristics over the operating range

CD

0

:E
Z

Symbol

Parameter

TAVEL

Address Set·up Time

TELAX

Address Hold Time

TElOV

Enable Access Time

TAVOV

Address Access Time'

NMC6518B·9
NMC6518B·2
Min
Max

NMC6518·9
NMC6518·2
Min
Max

NMC6518·5
Min

0

0

10

40

50

50

TSHOX Chip Select Output Disable Time

Units

Max
ns
ns

180

250

300

ns

180
' 120

250

310

ns

160

200

ns

lWLWH Write Pulse Width (W Low)

100

130

160

ns

TEHEL

ns

100

100

150

lWLSH Chip Select Write Pulse Set-up Time

100

130

160

ns

lWLEH Chip Enable Write Pulse Set-up Time

100

130

160

ns

TSLOX

Enable (E) Minimum High Time

120

Chip Select Output Enable Time

lWHDX Data Hold Time
TDVWH Data Set-up Time

160

200

0

0

0

80

110

130

ns
ns
ns

lWHOX Output Enable from Write (W)

120

160

200

ns

lWLOZ Output Disable from Write (W)

120

160

200

ns

Read·Modify·Write Cycle Waveforms

TSlQX

* Precede iN rising edge with Erising edge to avoid unwanted output enabling

2-54

~National

CMOS RAMs

~ Semiconductor

General Description

Features

The NMC6551 is a static CMOS random access read/write
memory organized as 256 words of 4 bits each. This device
is fabricated with National Semiconductor's silicon-gate
CMOS technology and is fully compatible with the TIL environment. Synchronous operation is provided by on·chip
address input and data output latches. The ENABLE input
serves as the device strobe controlling the latching
functions. The 110 terminals when not data output enabled, represent high impedance ports for easy memory
expansion.

• Industry standard pinout
• Low data retention voltage - 2V
ill Low speed/power product
• TIL compatible - all inputs and outputs
• TRI-STATE® outputs for bus operation
•
•
•
•
•

High output drive
High noise immunity
Military temperature range available
On-chip address registers (latches)
22 pin - high density packaging

• Output data latches
• Select latch for microprocessor interface

Connection Diagram

Logic Symbol

Dual·ln·Llne Package

vee

A2

AI
AD

AS

Pin Names

A6

AD-A?

Address Inputs
Chip Enable
Write Enable
Data Input
Data Output
Chip Selects

E
W

A7

D
Q

GND

3:

oen

en
en
......

NMC65511024·Bit (256 x 4) Static RAM

A3

z

S:;,§2
DO
00

Dl
TOP VIEW

Order Number NMC6551J·2, NMC6551J·9
or NMC6551J-5
See NS Package J22A
Order Number NMC6551N-5
See NS Package N22A

2-55

~

It)
It)

CD

o

:E

z

Functional Description
An NMC6551 memory cycle is initiated by the falling edge
of the ENABLE (E) input, which latches the ADDRESS and
SELECT 2 (52) information into the on-chip registers. Setup and hold times must be met. Data output is enabled
when the WRITE (W) input is HIGH and the ENABLE and
SELECT 1 Inputs are LOW.
.

return the columns to the HIGH state and to precharge
the sense amplifiers in preparation of the next memory
cycle.
When performing a write cycle, the minimum ENABLE
LOW time is required to enter new data. The write pulse
timing is created by the coincident LOW of the WRITE,
ENABLE and SELECT 1 inputs. The data set-up and hold
times are referenced to the rising edge of the WRITE,
ENABLE, or SELECT 1 input, whichever occurs first.

When performing a read cycle a minimum ENABLE LOW
time is required to assure valid data at the outputs. This
minimum LOW time is defined as the device enable access time. A minimum ENABLE HIGH time is required to

Block Diagram
, . . - - - - - - . . , FUNCTIONS ARE POSITIVE
LOGIC

AD
A1
A2
A3

ADDRESS
LATCH AND
INVERTERS

10

GATED
ROW
DECODER

32

DATA LATCHES ON FAlliNG
EDGE OF L

32 x 32
ARRAY

A4
(MSB)

G

~------------~~--~32~------------------------------~

INPUT (WRITE)
CONTROL
GATED
COLUMN
DECODER
AND I/O

DATA
OUTPUT
LATCH

1 - - - - 1 ~~.f--"-+--+-- Dn1
~-----+----4~~Dn2

L--r-..rll >--I-TR-I.S-T-AT-E®........__......... OUTPUT
BUFFERS

ADDRESS AND SElECT
LATCHES ON THE RISING
EDGE OF L

AS·

2-56

A6

A7

(MSB)

Dn3

Supply Voltage VCC

7V

Voltage at Any Pin

Supply Voltage
NMC6551B·9
NMC6551B·2
NMC6551·9
NMC6551·2
NMC6551·5

- 0.3V to VCC + O.3V

Storage Temperature Range

Z

Operating Range

Absolute Maximum Ratings
-65·Cto +150·C

Package Dissipation

500mW
300·C

Lead Temperature (Soldering, 10 seconds)

Temperature
NMC6551B·9
NMC6551B·2
NMC6551·9
NMC6551·2
NMC6551·5

Min

Max

4.5V
4.5V
4.5V
4.5V
4.75V

5.5V
5.5V
5.5V
5.5V
5.25V

-40·C
-55·C
-40·C
-55·C

85·C
125·C
85·C
125·C
75·C

o·c

DC Electrical Characteristics over the operating range, unless otherwise noted
Parameter

Symbol

NMC6551B·9, NMC6551B·2
NMC6551·9, NMC6551·2
Min
Max

Conditions

VCCDR

Data Retention Supply
Voltage

VI=VCC, GND

ICCSS

Standby Supply Current

ICCOp·

Operating Supply
Current

ICCDR

NMC6551·5
Min

Units

Max
V

2.0

2.0
10
1( + 25°C)

100

p.A

f=1 MHz, 10=0,
VI = VCC or GND

4

4

mA

Data Retention Supply
Current

VCC = 3.0V, 10 = 0,
VI = VCC or GND

10

100

p.A.

VI=VCC, GND

II

Input Leakage Current

VIL

Input Low Voltage

VIH

Input High Voltage

10Z

Output Leakage Current

-1.0

+1.0

-1.0

+1.0

p.A

-0.3

0.8

-0.3

0.8

V

VCC-2.0

VCC+0.3

-1.0

VI=VCC, GND

VCC-2

VCC+0.3

-1.0

+1.0

+1.0
0.4

V
p.A
V

VOL

Output Low Voltage

IOL=3.2 mA

VOH

Output High Voltage

10H = -0.4 mA

CI

Input Capacitance

f= 1 MHz

6

6

pF

CO

Output Capacitance

f= 1 MHz

10

10

pF

0.4

V

2.4

2.4

• ICCOP is proportional to operating frequency.

AC Test Conditions
Input Rise and Fall Times: :520 ns
All Timing Reference Levels: 1/2 VCC
Output Load: 1 TTL Load, 50 pF

NMC6551 Bit Map and Address Decoding

~
1 - t - 8 COLUMNS- - 8 COLUMNS---

-

(MSB) ROWS (LSB)
A4 A3 A2 Al AD

8COLUMNS--8COLUMNS-

0
0

0

0
0
0
0
0
0

1
1

1
1

0
0

0

CO~~~B~ :~
(LSB) AS

SENSE AMPS

SENSE AMPS

SENSE AMPS

SENSE AMPS

COLUMN DECDDER

CDLUMN DECODER

COLUMN DECODER

COLUMN DECODER

[[
: ,
••
1 0

~

0

::.
1 0

3·~
0

[ [: 1
•••
1 0

~--------~

:
0

:,

0:

•

~--~----~

2·57

JJ.
:0

0

0

0

0

0

1

0

0

0

1
1

1
1

0

1

1
1

1
1

0

1

0 0

1

3:

0
en
U'I
U'I
~

,..

It)
It)

CO

Read Cycle AC Electrical Characteristics over the operating range

0

:IE
Z

Symbol

Parameter

NMC6551B-9
NMC6551 B-2
Min
Max

NMC6551-9
NMC6551-2
Max
Min

NMC6551-5
Min

0

0

10

40

50

70

Units

Max
ns

TAVEL

Address Set-up Time

TELAX

Address Hold Time

TELQV

Enable Access Time

220

300

350

ns

TAVQV

Address Access Time

220

300

360

ns

TELEH

Enable (E) Minimum Low Time

TELS2X

Chip Select 2 Hold Time

TEHEL

ns

220

300

350

ns

40

50

70

ns

Enable (E) Minimum High Time

100

100

150

ns

TELEL

Read or Write Cycle Time

320

400

500

TS1LQX

Chip Select 1 Output Enable Time

130

150

180

ns

TS1HQZ

Chip Select 1 Output Disable Time

130

150

180

ns

TS2LEL

Chip Select 2 Set-up Time

0

0

Read Cycle Waveforms

2-58

10

ns

ns

Z

s:
0

Write Cycle AC Electrical Characteristics over the operating range
Symbol

NMC6551B·9
NMC6551B·2
Min
Max

Parameter

TAVEL

Address Set-up Time

TElAX

Address Hold Time

0

NMC6551·9
NMC6551·2
Max
Min
0

NMC6551·5
Min

Units

Max
ns
ns

40

50

70

120

180

210

ns

TELEl

320

400

500

ns

TELEH . Enable (E) Minimum Low Time

220

300

350

ns

TS2LEL

Chip Select 2 Set-up Time

0

0

10

ns

TWHDX

Data Hold Time

0

0

0

ns

TELS2X

Chip Select 2 Hold Time

40

50

70

ns

TDVWH

Data Set·up Time

100

150

170

ns

TELWH

Write Pulse Width (E and

120

180

210

ns

TEHEL

Enable (E) Minimum High Time

100

100

150

ns

TWLEH

Write Pulse Width

W Low)

(E and W Low)

120

180

210

ns

TS1LWH Chip Select 1 Write Pulse Hold Time

120

180

210

ns

TWLS1H Chip Select 1 Write Pulse Set-up Time

120

180

210

TS1LQX

Output Enable from

TWLQZ

S1

130

W
W
Output Disable from E

ns

150

180

ns

Output Disable from

130

150

180

ns

TWHQX Output Enable from

130

150

180

ns

TEHQZ

130

150

180

ns

Write Cycle Waveforms

* TWLWH; the write pulse, Is the coincidence low of

E, W, and S1lnputs
2-59

UI
UI

....A.

10

TWLWH Write Pulse Width (W low)
Read or Write Cycle Time

en

~

Lt)
Lt)

CO

Read-Modify-Write Cycle AC Electrical Characteristics over the operating range

0

:E

Symbol

Parameter

Z

NMC6551B·9
NMC6551B·2
Min
Max

NMC6551·9
NMC6551·2
Min
Max

NMC6551·5
Min

TAVEL

Address Set·up Time

TELAX

Address Hold Time

TELOV

Enable Access Time

220

300

350

TAVOV

Address Access Time

220

300

360

lWLEH

Write Pulse Width (IN and E Low)

120

180

0

0

10

40

50

70

Units

Max
ns
ns
ns
ns

210

ns

TEHEL

Enable (E) Minimum High Time

100

100

150

ns

lWLWH

Write Pulse Width (IN Low)

120

180

210

ns

TELEL

Read or Write Cycle Time

320

400

500

TS1LOX

Chip Select 1 Output Enable Time

130

150

180

TS1HOZ

Chip Select 1 Output Disable Time

130

150

180

TS2LEL

Chip Select 2 Set·up Time

lWHDX

Data Hold Time

TELS2H

Chip Select 2 Hold Time

lWLS1H

Chip Select 1 Write Pulse Set-up Time

lWLOZ

Output Disable from Write (IN) .

TDVWH

Data Set-up Time

0

0

ns
ns
ns

10

ns

0

0

0

ns

40

50

70

ns

120

120

210

130
100

150
150

ns
ns

TOVWL

Data Valid to Write Time

0

0

0

IN Read Mode Set-up Time

0

0

0

TWHOX

Output Enable from Write (IN)

150

ns
180

Read-Modify-Write Cycle Waveforms

E----__

Q~----+_----~~==][~-t~m~~----

.. Avoid unwanted output by preceding rising edge of iN with rising edge of

51

by time; TS1HQZ

2-60

ns

170

lWHEL

130

ns
180

ns

~National

CMOS RAMs

z

s:

D Sem,iconductor

(")

NMC65521024·Bit (256 x 4) Static RAM

N

0')

en
en

General Description

Features

The NMC6552 is a static CMOS random access read/write
memory organized as 256 words of 4 bits each. This device
Is fabricated with National Semiconductor's silicon-gate
CMOS technology and is fully compatible with the TIL environment. Synchronous operation is provided by the onchip address input and data output registers. The
ENABLE input serves as the device strobe controlling the
latching functions. The data I/O terminals, when not output data enabled, represent a high impedance for easy
memory expansion.

•
•
•
•

Low data retention voltage - 2V
Low speed/power product
TIL compatible - all inputs and outputs
TRI-STATE® outputs for bus operation

• High output drive
a High noise immunity
• Military temperature range available
• On-Chip address registers (latches)
• Common I/O - high density packaging
• Output data latches
• Select latch for microprocessor interface

Connection Diagram

Logic Symbol

Dual-In-Line Package

AD

A3

Al
A2

Order Number NMC6552J·2, NMC6552J·9
or N MC6552J·5
See NS Package J18A

Al
AD

Order Number NMC6552N·5
See NS Package N18A

AS

A2
A3

A4
AS
A6
A7

A6
A7

GNO
000

TOP VIEW

Pin Names

AO-A7

E
iN
DQO-DQ3

S1,S2

Address Inputs
Chip Enable
Write Enable
Data In/Out
Chip Selects

2-61

Functional Description
An NMC6552 memory cycle is initiated by the falling edge
of the ENABLE (E) input, which latches the ADDRESS and
SELECT 2 (52) information into the on-chip registers. The
output data latches are transparent when the ENABLE
input is LOW, allowing the state of the memory to be
presented to the output buffers. The output buffers are
enabled when the WRITE (W) input is HIGH, and the
SELECT 1 (51) input is LOW.

to return the columns to the HIGH state and to precharge
the sense amplifiers in preparation of the next cycle. The
data is latched with the rising edge of the ENABLE input,
allowing maintenance of output data until the SELECT 1
input goes HIGH.
When ·performing a write cycle, a minimum ENABLE
LOW time is required for new data entry. The write pulse
timing is defined by the coincident LOW of the WRITE,
ENABLE and SELECT 1 inputs. The input data set-up and
hold times are referenced to the rising edge of the
WRITE, ENABLE, or SELECT 1 inputs, whichever occurs
first.

When performing a read cycle, a minimum ENABLE LOW
time is required to assure valid data at the device outputs. This minimum LOW time is defined as the enable
access time. A minimum ENABLE HIGH time is required

Block Diagram

r------..,
AD

Al
A2
A3

ADDRESS
LATCH AND
INVERTERS

10

GATED
ROW
DECUDER

·DATA LATCHES ON FALLING
EDGE OF L

32 x 32
ARRAY

32

FUNCTIONS ARE POSITIVE
LOGIC

A4
(MSB)
TRI-STATE®
OUTPUT
BUFFERS

INPUT (WRITE) CONTROL

DO------------~

>-+--+--QO

~~~_+~~

Dl--------------------~ >-~~~
D2------------------------~ ~----_+~~

GATED
COLUMN
DECODER
AND 1/0

DATA
OUTPUT
LATCH

ADDRESS AND SELECT
LATCHES ON THE RISING
EDGE OF L

2-62

A6

A7

.>----+-- Q2
Q3

D3---------------------r~?_1it_~~~--J

A5

Ql

(MSB)

Absolute Maximum Ratings
Supply Voltage VCC

7V

Voltage at Any Pin

- 0.3V to VCC + 0.3V

Storage Temperature Range

Z

Operating Range
-65·Cto +150'C

Package Dissipation

500mW
3OQ·C

Lead Temperature (Soldering. 10 seconds)

Min

Max

Supply Voltage
NMC6552B·9
NMC6552B·2
NMC6552·9
NMC6552·2
NMC6552-S

4.5V
4.5V
4.5V
4.5V
4.75V

5.SV
5.5V
5.5V
5.5V
5.25V

Temperature
NMC6552B·9
NMC6S52B·2
NMC6552-9
NMC6552-2
NMC6552-S

-40'C
-55'C
-40'C
';'SS'C
O'C

85·C
125'C
85·C
125'C
75'C

3:

0CJ)
C1I
C1I

I\)

DC Electrical Characteristics over the operating range, unless otherwise noted
Symbol

Parameter

NMC6552B·9, NMC6552B·2
NMC6552·9, NMC6552·2
Min
Max

Conditions

VCCDR

Data Retention Supply
Voltage

ICCSB

Standby Supply Current

ICCOp·

Operating Supply
Current

f = 1 MHz, 10 = 0,
VI = VCC or GND

ICCDR

Data Retention Supply
Current

VCC = 3.0V, 10 = 0,
VI = vce or GND
VI=VCC, GND

VI=VCC, GND

II

Input Leakage Current

VIL

Input Low Voltage

VIH

Input High Voltage

10Z

Output Leakage Current

VI=VCC, GND

VOL

Output Low Voltage

IOL=3.2 mA

VOH

Output High Voltage

10H= -0.4 mA

CI

Input Capacitance

f= 1 MHz

CO

Output Capacitance

f= 1 MHz

2.0

NMC6552·5

Min

\

Units

Max

2.0

V

10

100

p.A

4

mA

100

p.A

-1.0

+1.0

-1.0

+1.0

p.A

-0.3

0.8

-0.3

0.8

V

VCC+0.3

V

VCC-2.0
-1.0

VCC+0.3

VCC-2

+1.0

p.A

0.4

V

6

6

pF

10

10

pF

-1.0

+1.0
0.4

2.4

V

2.4

* ICCOP is proportional to operating frequency.

AC Test Conditions
Input Rise and Fall Times: s20 ns
All Timing Reference Levels: 1/2 VCC
Output Load: 1 TIL Load, 50 pF

NMC6552 Bit Map and Address Decoding

~
r--- 8 COLUMNS-

1--f-8 COLUMNS -

(MSB) ROWS (LSB)
A4 Al A2 AI AD

I-- BCOLUMNS--8COLUMNS---

0
0
0

0
0
0

0

0
0

0
0

I
I

SENSE AMPS

SENSE AMPS

SENSE AMPS

SENSE AMPS

COLUMN DECODER

COLUMN DECODER

COLUMN DECODER

COLUMN DECODER

CO~:~B~:~[[I: ~
••

(LSB) A5

I

0

0

::
I 0

.J].~ [[1:"
0

I

0

~--~--~

~

:1:0'

0

~--~--~

2-63

JJ.~o

0

.
I
I

0
0
0
0
I
I

0
0

I
I

I
I

0
0
I
I

D
I
D
I
0
I

0

I

fJI

N

Lt)
Lt)

Read Cycle AC Electrical Characteristics over the operating range

CO

0

:E
Z

Symbol

Parameter

NMC6552B·9
NMC6552B·2
Min

TAVEL

Address Set·up Time

TElAX

Address Hold Time

TElQV

Enable Access Time

TAVQV

Address Access Time

TElEH

Enable (E) Minimum Low Time

TElS2X

Chip Select 2 Hold Time

TEHEl

Max

NMC6552·9
NMC6552·2
Min

Max

NMC6552·5
Min

0

0

10

40

50

70

220

300

220

300

Units

Max
ns
ns
350

ns

360

ns

220

300

350

ns

40

50

70

ns

Enable (E) Minimum High Time

100

100

150

ns

TElEl

Read or Write Cycle Time

320

400

500

ns

TS1lQX

Chip Select 1 Output Enable Time

130

150

180

TS1HQZ

Chip Select 1 Output Disable Time

130

150

180

TS2lEl

Chip Select 2 Set·up Time

0

0

10

Read Cycle Waveforms

DQ--~ma~=r---

2·64

ns
ns
ns

Z

s:
0

Write Cycle AC Electrical Characteristics over the operating range

0')

Parameter

Symbol
TAVEL

Address Set·up Time

TELAX

Address Hold Time

TS2LEL

Chip Select 2 Set-up Time

TWHDX

Data Hold Time

TELEH

Enable (E) Minimum Low Time

TWLWH

Write Pulse Width

TELEL

Read or Write Cycle Time

TEHEL

Enable (E) Minimum High Time

TDVWH
TELWH

NMC6552B-9
NMC6552B·2
Min
Max

NMC6552·9
NMC6552-2
Min
Max

NMC6552·5
Min

Units

Max

0

0

10

40

50

70

ns

0

0

10

ns

ns

0

0

0

ns

220

300

350

ns

120

180

210

ns

320

400

500

ns

100

100

150

ns

Data Set-up Time

100

150

170

ns

120

180

210

ns

TWLEH

(E and IN Low)
Write Pulse Width (IN and E Low)

120

180

210

ns

TELS2H

Chip Select 2 Hold Time

40

50

70

ns

TWLS1H

Chip Select 1 Write Pulse Set-up Time

120

180

210

ns

TS1LWL

Chip Select 1 Write Pulse Hold Time

120

180

210

ns

(IN Low)

Write Pulse Width

Write Cycle Waveforms

w

DQ

------------+--~

* TWLWH. the write pulse. is the coincidence low of E. W. and 51 inputs
2-65

en
en
I\)

N

II)

II)

Read-Modify-Write Cycle AC Electrical Characteristics over the operating range

CD

0

::E

Z

Symbol

Parameter

TAVEL

Address Set·up Time

TElAX

Address Hold Time

TElOV

Enable Access Time

NMC6552B·9
NMC6552B·2
Min
Max

NMC6552·9
NMC6552·2
Min
Max

NMC6552·5
Min

0

0

10

40

50

70

220

300

220

300

Units

Max
ns
ns
350

ns

360

ns

TAVOV

Address Access Time

TS2lEl

Chip Select 2 Set·up Time

0

0

10

ns

TWHDX

Data Hold Time

0

0

0

ns

TElS2X

Chip Select 2, Hold Time

40

50

70

ns

TWlS1H

Chip Select 1 Write Pulse Set·up Time

120

180

210

T$1LOX

Chip Select 1 Output Enable Time

TDVWH

Data Set·up Time

TWLEH

Write Pulse Width

fiJ and Elow)

130

ns
180

150

ns

100

. 150

170

ns

120

180

210

ns

TOVWl

Data Valid to Write Time

0

0

0

ns

TWLWH

Write Pulse Width (iJ Low)

120

180

210

ns

TEHEL

Enable (E) Minimum High Time

100

100

150

ns

0

0

ns

TOVWL

Data Valid to Write Time

TWHOX

Output Enable from Write (W)

0
130

150

180

ns

TWLOZ

Output Disable from Write (W)

130

150

180

ns

Read-Modify-Write Cycle Waveforms

I-----TWLWH:....-----l

* Avoid bus contention
2·66

Section 3

Bipolar RAMs
Bipolar RAMs offer the best sclution to problems
requiring high speed read-write memory. National's
product line includes the devices in this section to
complement our bipolar microprocessor and logic
lines.

TTL

~National

Bipolar RAMs

~ Semiconductor
DM7589/DM8589 64-Bit (16 x 4) RAM
General Description

Memory Enable input is in the logical "1" state,
the outputs will go to the logical "1" state.

The DM7589/DM8589 is a fully decoded 64·bit
RAM organized as 16 4·bit words. The memory is
addressed by applying a binary number to the four
Address inputs. After addressing, information may
be either written into or read from the memory.
To write, both the Memory Enable and the Write
Enable inputs must be in the logical "0" state.
Information applied to the four Write inputs will
then be written into the addressed location. To
read information from the memory the Memory
Enable input must be in the logical "0" state and
the Write Enable input in the logical "1" state.
Information will be read as the complement ofwhat was written into the memory. When the

Features
•
•
•
•
•
•

Series 54/74 compatible
Organized as 16 4·bit words
Typical access from chip enable 23 ns
Typical access 35 ns
Typical power dissipation 400 mW
Open collector outputs to permit "wire OR"
capability

Block Diagram

ADDRESS
INPUTS

DATA
INPUTS

Connection Diagram

Truth Table

Dual·ln·Line Package

..

Order Number DM7589J
or DM8589J
See NS Package J16A
Order Number DM8589N
See NS Package N 16A

3·3

MEMORY
ENABLE

WRITE
ENABLE

OPERATION

OUTPUTS

0

Write
Read

X

Hold

Logical "1" State
Complement of Data
Stored in Memory
Logical "1" State

en

co
It)
CO

:E
C
CD
CO

It)

Absolute Maximum Ratings

Operating Conditions

(Note 1)

Supply Voltage
Input Voltage
Output Voltage

Operating Temperature Range
DM7589
DM8589

7V
5.5V
5.5V

Storage Temperature Range
Lead Temperature (Soldering, 10 sec)

-55°C to +1;15°C
O°C to +70°C

-65°C to +150°C
300°C

r-:E
C

Electrical Characteristics

(Note 2)

PARAMETER

CONDITIONS

MIN

Logical "1" Input Voltage

DM7589
DM8589

Vcc = 4.5V
Vce = 4.75V

Logical "0" I nput Voltage

DM7589
DM8589

Vce = 4.5V
Vee - 4.75V

Logical "1" Output Current

DM7589
DM8589

Vee = 5.5V
Vce - 5.25V

Logical "0" Output Voltage

DM7589
DM8589

Vee = 4.5V
Vee - 4.75V

Logical" 1" I nput Current

DM7589
DM8589

Vee = 5.5V
Vcc - 5.25V

V ,N = 2.4V

DM7589
DM8589

Vce = 5.5V
Vce - 5.25V

V ,N = 5.5V

Logical "0" Input Current

DM7589
DM8589

Vcc = 5.5V
Vee = 5.25V

Supply Current

DM7589
DM8589

Vee = 5.5V
Vce - 5.25V

Input Clamp Voltage

DM7589
DM8589

Vcc = 4.5V
Vee = 4.75V

Switching Characteristics

TYP

MAX

2.0

UNITS
V

0.8
100
20

Vo = 5.25V
10= 12mA

0.4

40

V
IlA
IlA
V

IlA
mA

-1.6
All Inputs at GND

80

120
-1.5

liN = -12 mA

mA

mA
V

(Over recommended operating ranges of Vee and T A·)

PARAMETER

I

CONDITIONS

DM7589
MIN

tpLH

DM8589

TYP

MAX

MIN

TYP

MAX

UNITS

34

80

34

60

ns

35

80

35

60

ns

Access Time From Address
tPHL
tpLH

Disable Time From Memory Enable

23

55

23

40

ns

tpHL

Enable Time From Memory Enable

23

55

23

40

ns

tSETuP Setup Time

Address to Write
Enable
Data to Write Enable
Memory Enable To
Write Enable

tHOLD

Hold Time

Address From Write

RL1 = 300n

0

-14

-14

ns

0

-15

-15

ns

-10

-10

ns

-7

-7

ns

0

-14

-14

ns

0

-10

-10

ns

20

ns

RL2 = 600n
CL = 30 pF

Enable
Data From Write
Enable
Memory Enable
From Write Enable
twp

Write Pulse Width

tSR

Sense Recovery Time

50

20
31

40
65

31

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot
be guaranteed. Except for "Operating Temperature Range" they are not meant to imply that the
devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions
for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the _55°C to +125°C temperature
range for the DM7589 and across the O°C to 70°C range for the DM8589. All typicals are given for
Vec = 5.0V and T A = 25°C.

3-4

55

ns

Typical Performance Characteristics
Delay from Memory Enable
to Output

Delay from Address to Output
80

80
Vee

=

5.0V

Vee' 5.0V

10

10

60

60
]
>

g

50

30
20

~

tPlH

-

40

.,.,..,

-~

]

50

~e>

40

~~ ~

30

'jHL

j"HL r-

20
10

10

o

o
-15 -50 -25

0

25

50

15

-15 -50 -25

100 125

40
=

25

50

15 100 125

Minimum Write Pulse Width

Sense Recovery Time
80
Vee

0

TEMPERATURE (Oe)

TEMPERATURE (Oe)

5.0V

Vee

=5.0V

35

10

60

30

!::c

50

25

-

l-

e

40

"r-

30

20

3:
~

15

=>

20

'wP

:.- f,.--

f-

10

10

o
-15 -50 -25

a

o
25

50

15 100 125

-15 -50 -25

0

25

50

15

100 125

TEMPERATURE (Oe)

TEMPERATURE n)

AC Test Circuit and Switching Time Waveforms
s.ov

Read Cycle

Write Cycle

·OUTPUT
ME

WE--+--'I

AOORESS----~

thul

20

g

/

15 I - 10

101--~-+--1--+--+--I--+-~

o
-75 -50 -25

0

25

50

t- Ilz

~-'--J...~~~~~_~~

TEMPERATURE IC)

Vee

=

50

75

100 125

Minimum Write Pulse Width
Vee = 5.0V

5.0V

35

·35

30

..,

25

>
C[

20

--

15

IZH

30

]
:>:
....
c

~
.L- ...IZl

i--

10

25
20

l::

-75 -50 -25

0

25

50

75

i--

15

::>

~

f..--

O~-'--J...~~~~~-~~

-75 -50 -25

100 125

0

25

SO

TEMPERATURE

TEMPERATURE 1°C)

75 100 125

ec)

Delay from Enable to Output
vs Load Capacitance

Sense Recovery Time
80

-

Iwp

10

o '---'--'-----''---'---"----'--'----'

Vee = 5.0V

70

50

tf-

60
40
50
40

;::

25

40

40

-~

0

TEMPERATURE ("'C)

Delay from Memory Enable to
Low Impedance State

c

1HZ

-75 -50 -25

75 100 125

-~

-

30

-

IZH

20

--

IZl

-; 30 f -

:5

t-

~ 20 f -

i-- ~

~

tf-

....

10 r-4--+~r-+--+~--+-~

10 f f-

0'---'--'--'---'--'---'--'---'

o '--

-75 -50 -25

0

25

50

75

Ip~HI++-Ht+I+-+-++++ftll

5 10

100 125

50 100

500

Cl (pF)

TEMPERATURE 1°C)

Test Circuit
r-,;l
I

I

.KI
ME.

ME,

STORED
"1"

STORED
"0"

...

Note: In a typical application the output of the TRISTATE memories might be wired together and one
would be switching to the low impedance state at the
same time the circuit previously selected would be
switching back into the hi'gh impedance state. The
measurements of delay versus load capacitance were
made under conditions which simulate actual operating
conditions in an application. (See test circuit.l

I

I

:

.... ~
u I.
u :.
I
-=1

ONE7rl'lO-;:t
Test Circuit for Delay vs Load Capacitance

3-8

c

s:
"""-I

AC Test Circuit

(J1

CD

Vee

~

TEST
POINT

C

RL1

FROM

O~:~~~
TEST

s:
CO

-....--...

-44...- .

(J1

CD
CD

Cl includes probe and jig capacitance.
All diodesarelN1064.

Switching Time Waveforms

J.OV

3.0V
ADDRESS
INPUT
(SEE NOTE B)

L
VOH - - - - -

OUTPUT

_____

AOORESS
INPUTS

'''"F

3.0V

I.SV

VOL-------------~------~

3.0V
MEMORY
ENABLE

3.0V

3.0V

WRITE
ENABLE
INPUT

MEMORY ENABLE
(SEE NOTE C)
OV----+-'~---------'

~

l.SV
WAVEFORM I
(SEE NOTE A)

WAVEFORM I
(SEE NOTE A)

VOL

VOL

-----+---'

VOH-------~

VOH
WAVEFORM 2
(SEE NOTE A)

WAVEFORM 2
(SEE NOTE A)
~

'" l.SV

l.SV-----··--·--'--I--J-+---r-

NOle A: Waveform I is for Ihe oulpul wilh inlernal condilions such thaI the OUlpul is low excepl when disabled. Waveform 2 is for Ihe oulpul wilh
inlernal condilions such Ihallh. oulpul is high excepl when disabled.
Nole B: When measuring delay limes from address inputs, Ihe memory enable inpul is low and the wrile enable inpul is high.
NOle C: When measuring delay limes from memory enable inpul, the address inpuls are sleadY'slale and Ihe wrile enable inpul is high.
Note O. fnpul waveforms are supplied by pulse generalors having Ihe following characterislics: I, S IOns, I, S IOns, PRR S 1.0 MHz, and ZOUT '" SOn.

3-9

Schottky

~National

Bipolar RAMs

~ Semiconductor

C1I

en

en

DM85568 16 x 4 Edge Triggered Registers

CO

General Description

Features

These Schottky memories are addressable "D" register
files_ Any of its 16 four-bit words may be asynchronously
read or may be written into on the next clock transition_
An input terminal is provided to enable or disable the synchronous writing of the input data into the location
specified by the address terminals_ An output disable terminal operates only as a TRI-STATE" output control terminaL The addressable register data may be latched at
the outputs and retained as long as the output store terminal is held in a low state_ This memory storage condition is independent of the state of the output disable terminaL

•
•
•
•
•

On-chip output register
PNP inputs reduce input loading
Edge triggered write
High speed-30 ns typ
All parameters guaranteed over temperature

•
•
•
•

TRI-STATE output
Schottky-clamped for high speed
Optimized for register stack applications
Typical power dissipation-350 mW

All input terminals are high impedance at all times, and
all outputs have low impedance active drive logic states
and the high impedance TRI-STATE condition_

Logic and Block Diagram

Connection Diagram
(WRITE C~~~K INPUT)

Dual.ln.Line Package

14
18

01

VCC
17

02

(WRITE ENABLE)

16 04

A2

15_
WE
14

AJ

wto--l"X>----------+/
'"~
~ '-y-,.---.---.----r-.---,---,-I

OJ

AD

15

C'_K

lJ_
05

Al

12

01

00

11 04

0,

Al~~

c

s:
CO

10

GNO

OJ

16x4MEMORY CELL ARRAY

A2~

TOPVIEW

Order Number DM85S68N
See NS Package N18A

lJ

~o---~~----+--+~--~~~.-----.-~~--~
(OUTPUT
STORE)

(OUTPUTS)

3-13

Operating Conditions

Absolute Maximum Ratings
Supply Voltage
Input Voltage
,
Output Voltage
Storage Temperature
lead Temperature (Soldering, 10 seconds)

-0.5Vlo +7V
- 1.2V to + 5.5V
- 0.5V to + 5.5V
- 65 ·C to + 150'C
300'C

MIN

Supply Voltage (V CC)
Ambient Temperature (TA)
Logical "0" Input Voltage (LOw)
Logical "1" Input Voltage (High)

4.75

MAX
5.25

UNITS
V

0

+70

·C

0

O.B

2.0

5.5

V
V

DC Electrical Characteristics (Note 2)
Parameter

Min

Conditions

Typ

Max

Units
V

VIH

High Level Input Voltage

V il

Low Level Input Voltage

VOH

High Level Output Voltage

Vcc = Min, IOH = - 5.2 mA

Val

Low Level Output Voltage

Vcc= Min, IOl= 16 mA

0.45

V

IIH

High Level Input Current

Vcc= Max, Clock Input
V IH = 2.4V All Others

50
25

p.A

II

High Level Input Current
at Maximum Voltage

Vcc = Max, VIH = 5.5V

1.0

mA

IlL

Low Level Input Current

Vcc = Max, Clock Input
Vil = 0.5V All Others

-500
-250

p.A
p.A

los

Short Circuit Output Current

Vcc = Max, VOL = OV
(Note 3)

-55

mA

2
0.8

V
V

2.4

-20

mA

Icc

Supply Current

Vcc= Max

VIC

Input Clamp Voltage

Vcc=Min, IIN= -18 mA

-1.2

V

loz

TRI·STATE Output Current

Vcc= Max Vo=2.4V
Vo=0.5V

40
-40

p.A

Units

70

AC Electrical Characteristics (With standard load)

5V ± 5%, O°C to

100

+ 70°C
Typ

Max

tZH

Output Enable to High Level

20

35

ns

tZl

Output Enable to Low Level

14

24

ns

tHZ

Output Disable Time from High Level

10

15

ns

tLZ

Output Disable Time from Low Level

12

18

ns

tAA

Access Time

Parameter

Conditions

Min

Address to Output

30

40

tOSA

Output Store to Output

20

30

tCA

Clock to Output

25

40

t ASC

Set-Up Time

Address to Clock

tosc

Data to Clock

tAsos

Address to Output Store

tWEsc

Write Enable Set-Up Time

15

5

5

5

30

0

5

15
0

Store Before Write (tlO)

10

Address from Clock

10

5

tOHC

Data from Clock

15

5

tAHOS

Addiess from Output Store

5

a

twEHC

Write Enable Hold Time

15

5

tossc
t AHC

Hold Time

Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that the device may be operated at
these values.
Note 2: These limits apply over the entire operating range unless staled otherwise. All typical values are for VCC =5V and TA =25 ·C.
Note 3: During ISC measureme~t, only one output at a time should be grounded. Permanent damage may otherwise result.
3-14

ns

ns

ns

Bipolar RAMs

~National

~ Semiconductor

IDM29705/IDM29705A 16-Word by 4-Bit Two-Port
RAM/Register File
General Description
The IDM29705 and IDM29705A are 16-word by 4-bit
RAM/Register File chips housed in a standard 28-pin
dual-in-line package. The IDM29705 and the
IDM29705A feature TRI-STATE® outputs. These
RAMs, which are fabricated using SCl® (Schottky
ECl Technology) feature two separate output ports
that enable any two 4-bit words to be read form these
outputs simultaneously. Each output port contains a
four-bit latch. A common latch Enable (lE) input is
used to control all eight latches. The device, which
has two Write Enable (WE) inputs, is designed so that
either Write Enable (WEI or 2) and latch Enable (lE)
inputs can be wired together to make the operation
of the RAM appear edge-triggered.

The writing of new data into the RAM is controlled by
the Write Enable inputs. With both Write Enable
inputs low, data is written into the word selected by
the B-address field. The memory outputs follow the
data inputs during writing if the latch Enable (lE) is
high. With either Write Enable high, no data is written
into the RAM.

Features and Benefits
• 16-Word by 4-Bit, 2-Port RAM/Register Files
• Two Output Ports, Each with Separate Output
Control
• 4-Bit latches on Each Output Port

The device, which has fully decoded A-address and
B-address fields, can address any of the 16 memory
words for the A-output port and, simultaneously,
select any of the 16 words for presentation at the
B-output port. Incoming data is written into the fourbit RAM word selected by the B-address. The D
inputs are used to load the new data into the device.

• Non-Inverted Data Output with Respect to Data
Input
• Output Enable and Write Enable Inputs Provide
Ease in Cascading
• SCl Technology (Schottky ECl) Provides ECl
Speeds While Keeping low Power Schottky Inputl
Output Voltage and Power Consumption
Compatibility

Several of these devices can be cascaded to increase
the total number of memory words in the system.
When OE-A is high, the A-output port is in the highimpedance mode. OE-B, when high, forces the
B-output port to the high-impedance state.

• 100% Reliability Testing in Compliance with
Mll-STD-883

IDM29705129705A Block Diagram
DO

A3

02

01

03

B3

•

16-WDRD BY 4·BIT
TWO·PORT RAM

ADDRES:

1

B
ADDRESS
DECODER

B2
Bl
BO

B·PORT

LE

B·OATA
4·BIT
LATCH

A·DATA
4·BIT
LATCH

3-15

Absolute Maximum Ratings

Operating Range

Storage Temperature
. - 65 ·C to + 150 ·C
Temperature (Ambient) Under Bias
-55·Cto +125·C
Supply Voltage to Ground Potential
- 0.5V to + 6.3V
DC Voltage Applied to Outputs for
High Output State
-0.5Vto + Vcc max
DC Input Voltage
- 0.5V to + 5.5V
DC Output Current, into Outputs
30mA
DC Input Current
- 30mA to + 5.0mA

Standard Screening

Ambient

PIN
IDM29705JC
IDM29705JM, JM/883
IDM29705AJC, NC
IDM29705AJM, JM/883

Temperature

Vee

O'C to + 70'C

4.75V to 5.25V

-55'C to +125'C
O'C to + 70'C
-55'C to +125'C

4.50V to 5.50V
4.75V to 5.25V
4.50V to 5.50V

(conforms to MIL·STD·883 for Class C parts)
Level

Step

MIL·STO·883
Method

Conditions

OC,PC

Pre·Seal Visual Inspection

2010

B

100%

100%

Stabilization Bake

1008

C: 24·hour 150·C

100%

100%

Temperature Cycle

1010

C: - 65·C to + 150·C
10 cycles

100%

100%

Centrifuge

2001

B: 10,000 G

100%

100%

Fine Leak

1014

Gross Leak

1014

Electrical Test.
Subgroups 1 and 7 and 9

5004

A: 5x 10- 8

atm·cc/cm 3

OM, FM

100%

100%

C2: Fluorocarbon

100%

100%

See below for
definitions of subgroups

100%

100%

Insert Additional Screening Here for Class B Parts
Group A Sample Tests
Subgroup 1
Subgroup 2
Subgroup 3
Subgroup 7
Subgroup 8
Subgroup 9

See below for
definitions of subgroups

5005

Additional Screening for Class B Parts
Level

MIL·STO·883
Method

Conditions

OMB, FMB

Burn·ln

1015

0: 125'C, 160 hours min

100%

Electrical TeJt
Subgroup 1
Subgroup 2
Subgroup 3
Subgroup 7
Subgroup 9

5004

Step

100%
100%
100%
100%
100%

Return to Group A Tests in Standard Screening

Group A Subgroups
(as defined In MIL·STD·883, method 5005)
SubQroup

P.rlmeter

1

DC

25'C

2

DC

Maximum rated temperature

3

DC

Minimum rated temperature

7
8

Function

25'C

Function

Maximum and minimum
rated temperature

Temperature

9

Switching

25'C

10

Switching

Maximum rated temperature

11

Switching

Minimum rated temperature

3·16

LTPD
LTPD
LTPD
LTPD
LTPD
LTPD

=5
=7
=7
=7
=7
=7

LTPD
LTPD
LTPD
LTPD
LTPD
LTPD

=
=
=
=
=
=

5
7
7
5
7
5

Electrical Characteristics

(over operating temperature range,unless otherwise noted)

VOH

VOL

Output HIGH Voltage
(IDM29705 only)

Vee = min
VIN = VIH or VIL

Output lOW Voltage

Vee = min
VIN = VIH or VIL

Typ
(Note 2) Max

Min

Test Conditions (Note 1)

Parameter

Mil, IOH = - 2.0mA

2.4

Com'l, IOH = -4.0mA

2.4

Volts

IOL = 4.0mA

0.4

IOL = 8.0mA

0.45

IOL = 12mA

0.5

2.0 .

Guaranteed input logical HIGH voltage for all
inputs

VIL

Input LOW Level

Guaranteed input logical LOW voltage for all
inputs

VI

Input Clamp Voltage

IlL

Input LOW Current

Volts

0.5

Com'l, IOL = 16mA
- - - -r - "
VIH
Input HIGH level

Units

Volts
0.8

Volts

Vee = min, liN = - 18mA

-1.5

Volts

Vee = max, VIN = OAV

-0.25

I Air Bj
Others

-0.36

1

mA

IIH

Input HIGH Current

Vee = max, VIN = 2.7V

20

IJA

II

Input HIGH Current

Vee = max, VIN = 5.5V

0.1

mA

loz

Off State (High Impedance)
Output Current

Vee = max
VIN = VIH or VIL

20
-20

IJA

Ise

Output Short Circuit Current
(Note 3)

Vee = max

-85

mA

Icc

Power Supply Current

Vee = max

I
I

Vo = 2.7V
Vo = OAV
-30

175

mA

= 70·C

110

155

mA

IAJM Vee = 5.5V, T = 125·C

145

mA

IAJC Vee = 5.25V, T

Note 1: For conditions shown as min or max, use the appropriate value specified under Electrical Characteristics for the applicable
device type.
Note 2: Typical limits are at VCC = 5.0V, 25°C ambient and maximum loading.
Note 3: Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second.

Switching Characteristics

(Input Levels = OV and 3.0V, Transitions measured at 1.5V)
Combinational Delays (In nanoseconds) (R L = 430n, CL = 50pF)

From

Parameters

A Address Stable

To

Conditions

YA Stable

Access Time

Comm'l

Mil

Max
(Note 5)

Max
(Note 6)

705

705A

705

705A

50

25

55

30

LE= HIGH
B Address Stable

50

25

55

30

YA=D

LE = HIGH, A= B

45

35

48

40

YB=D

LE = HIGH

45

35

48

40

25

20

25

20

20

20

20

20

YB Stable

Both WE LOW
Turn-On Time

OE-A or OE-B LOW

Turn-Off Time

OE-A or OE-B HIGH

Reset Time

A-LO LOW

YA LOW

30

20

30

25

Enable Time

LE HIGH

YA and YB Stable

25

20

25

25

Data In

YA or YB = D

45

35

45

40

YA or YB Off

C L = 5pF

LE=HIGH, WE
both LOW, A = B
3-17

Switching Characteristics (continued)
Minimum Setup and Hold Times (In nanoseconds)

Typ
Parameters

From

Conditions

To

Comm'l

Mil

Max
(Note 5)

Max
(Note 6)

(Note 4)

705

705A

705

705A

Data Setup Time

o Stable

Either WE HIGH

7

20

12

25

15

Data Hold Time

Either WE HIGH

o Changing

0

0

0

0

0

Address Setup Tim~ 8 Stable

80th WE LOW

0

5

0

5

3

Address Hold Time Either WE HIGH

8 Changing

0

0

0

0

0

Latch Close
Before Write Begins

LE LOW

WE, LOW

WE 2 LOW

0

0

0

0

0

LE LOW

WE 2 LOW

WE, LOW

0

0

0

0

0

8

30

15

40

20

Address Setup
A or 8 Stable
Before Latch Closes

LE LOW

Minimum Pulse Widths (In nanoseconds)

Typ

,

Parameters

From

Conditions

To

Mil

Max
(Note 5)

Max
(Note 6)

(Note 4)

705

705A

705

705A

WE,

HIGH·LOW·HIGH

WE 2 LOW

8

25

20

25

20

WE 2

HIGH·LOW·HIGH

WE, LOW

8

20

20

20

20

5

20

15

20

15

5

20

15

20

15

Write Pulse Width
A Latch Reset Pulse A·LO

HIGH·LOW·HIGH

Latch Data Capture LE

LOW·HIGH·LOW

Note 4: TA
Note 5: TA
Note 6: TA

Comm'l

Address Stable

= 25 ·C, VCC = 5.0V.
= O·C to + 70·C, VCC = 5.0V :t 5%.
= -55·Cto +125·C, VCC = 5.0V :t 10%.

Function Tables
Write Control
RAM Outputs at Latch Inputs
WE1

WE2

Function

A·Port

B·Port

L
X
H

L
H
X

Write 0 Into 8
No write
No write

A data (A ¢ 8)
A data
A data

o input data
8 data
B data

VA Read
Inputs
OE·A

A·LO

LE

VA Output

Function

H
L
L
L

X
L
H
H

X
X
H
L

Z

High Impedance
Force VA LOW
Latches transparent
Latches retain data

L
A·Port RAM data
NC

3·18

Function Tables (continued)
YB Read
Inputs

H
L
X

OE·B

LE

YB Output

Function

H
L
L

X
H
L

Z

High Impedance
Latches transparent
Latches retain data

= HIGH
= LOW
= Don't care

B·Port RAM data
NC
Z

= High Impedance

NC = No change

Pinout Descriptions of the
I DM29705/29705A
OE·B: B·port output enable. When low, data in the
B-data latch is presented at the YB I outputs. When
high, the YB j outputs are In the hlgh·impedance
mode.

D3 - Do: Through these inputs new data can be written
in the location specified by the B-address inputs.
A3 -Ao: The 4·bit address presented at the A inputs
selects one of the 16 memory words for presentation
at the A-data latch outputs.
B3 - Bo: The 4·bit address presented at the B inputs
selects one of the 16 memory words for presentation
at the B·data latch outputs. This address also selects
the location into which data is written.

LE: Latch enable. The LE input acts as control for
both the RAM·A and RAM·B output ports. When high
the latches are transparent and data from the RAM,
as selected by the A and B address inputs, is
presented at the outputs. When low, the latches
retain the last data read from the RAM regardless of
the current A and B address Inputs.

YA 3 - YAo: The four A·data latch outputs.
YB 3 - YBo: The four B-data latch outputs.
WE 1, WE 2 : Write enable inputs. When both are low,
enables data to be written into the RAM location
selected by the B-address field. When either Write
Enable input is high, no data can be written into
memory.

A·LO: Force A to zero. This input operates to force
the A·port latch outputs low independent of the LE
input or A address inputs, The A-output bus can be
forced low using this control input. With A-LO high,
the A latches operate in their normal manner. Once
forced low, the A latches remain low independent of
the A·LO input if the Latch Enable (LE) is low.

OE·A: A·port output enable. When low, data in the
A·data latch is present at the YA j outputs. When high,
the YA j outputs are In the high·impedance mode.

IDM29705/29705A Connections Diagram
0100WE1808182B3A·lOlEVBOVAOVB1VA1GNO-

1
28 ~ Vee
2
27 ...... 02
3
26~03
4
25 ...... WE2
5
24~AO
6
23 I - Al
7 IDM29705/ 22 ~A2
B 29705A
21 ...... A3
9
20 to- OE·A
10
19 to-nnI
11
18 to- VA3
12
17 to- VB3
13
16 i - VA2
14
15 i - VB2

3·19

Order Number IDM29705JC,
IDM29705JM,IDM29705JM/883,
IDM29705AJC,IDM29705AJM,
or IDM29705JM/883
See NS Package J28A
Order Number IDM29705NC
See NS Package N28A

Eel

Bipolar RAMs

~National

C

3:
.....

~ Semiconductor

o

DM10414, DM10414A 256 x 1 Eel Random Access Memory

.P-

General Description

Features

The DM10414, DM10414A is a 256-word by 1-bit
ECl random access memory. The fully static memory is
designed with active low chip selects and separate I/O
pins. The 8 address bits (AD through A71 are fully
decoded on the chip. Applications such as scratch pad,
cache, and buffer memories are ideal for this high speed
RAM.

•

3:
.....

~
.....

C

•
•
•
•

An unterminated emitter-follower output is provided
to allow the outputs to be wire-ORed. Separate Data
In and non-inverted Data Out pins are provided. These
RAMs are compatible with compensated and uncompensated 10k ECl families.

Block

~nd

•

Fully compatible with standard and voltage compensated 10k series ECl
Temperature range
DoC to +75°C
Unterminated emitter-follower output for wire-ORing
Power dissipation decreases with increasing temperature
Typical address access
DM10414
10 ns
DM10414A
7 ns
Typical chip select access
DM10414
4 ns
DM10414A
3 ns

o

~
.....

~

Connection Diagrams
Dual-in-Line Package

AD
Al
A2

ADDRESS
DECDDER

WORD
DRIVER

AD

16 X 16 ARRAY

A1

A3

A2

CST

A3

rn

CST

m

m

A6

rn

AS

VEE

A4

TOP VIEW

Order Number DM10414J
or DM10414AJ
See NS Packag~ J16A

A4 AS A6 A7

Logic Symbol
AD

Truth Table
Pin Names
AO-A7
Address Inputs
DIN
Data Input
DOUT
Data Output
CS1, CS2, CS3 Chip Select Inputs
WE
Write Enable

WE

DIN

H

X

X

L

L

L

H

L

Write 1

L

L

L

L

Write 0

L

H

X

DOUT

Read

DOUT

L = low (-1.7V nominal)
H = high (-O.9V nominal)
X = don't care

3-23

MODE

CS

Not Selected

•

~

~
,...
~
0,...

:E
C

-ei
,...
~
0
,...

:E
C

Absolute Maximum Ratings

Operating Conditions

Temperature Under Bias (Ambient)
Storage Temperature Range
VEE Relative to VCC
Any Input Relative to VCC
Output Current (Output High)
Lead Temperature (Soldering, 10 seconds)

Supply Voltage (VEE)
Ambient Temperature (T A)

-55°C to +125°C
--65°C to +150°C
-7.0V to +0.5V
VEE to +0.5V
-30 mA to +0.1 mA
300°C

MIN

MAX

-5.72
0

-4.68
+75

UNITS
V
°c

DC Electrical Characteristics
VEE = -5.2V ±10%, Output Load = 50n and 30 pF to -2.0V, T A = DoC to +75°C (Notes 1-4)
SYMBOL
VOH

VOL

VOHC

VOLC

VIH

PARAMETER
Output Voltage High

Output Voltage Low

Output Voltage High

Output Voltage Low

Input Voltage High

CONDITIONS

TA

B
LIMIT

A
LIMIT

UNITS

VIN = VIHA or VILB
O°C

-1000

-840

+25°C

-960

-810

+75°C

-900

-720

mV

VIN = VIHA or VILB

VIN = VIHB or VILA
Performed on one input
at a time

VIN = VIHB or VILA
Performed on one input
at a time

O°C

-1870

-1665

+25°C

-1850

-1650

+75°C

-1830

-1625

O°C

-1020

+25°C

-980

+75°C

-920

mV

mV

O°C

-1645

+25°C

-1630

+75°C

-1605

mV

Guaranteed Input Voltage High
for All Inputs

VIL

Input Voltage Low

O°C

-1145

-840

+25°C

-1105

-810

+75°C

-1045

-720

mV

Guaranteed Input Voltage Low
for All Inputs

IIH

Input Current H'igh

VIN = VIHA
Performed on one input
at a time

O°C

-1870

-1490

+25°C

-1850

-1475

+75°C

-1830

-1450

mV

O°C
to

220

}1A

170

}1A

+75°C
IlL

lEE

Input Current Low, CS

All Others

VIN = VILB
Performed on one input
at a time

Power Supply Current

All Inputs and Outputs Open

+25°C

0.5

+25°C

-50

O°C

-150

(Pin 8) (Note 5)
mA

Note 1: Conditions for testing not shown in the tables are chosen to guarantee operation under "worst case" conditions.
Note 2: The specified limits represent the "worst case" value for the parameter. Since these "worst case" values normally occur at the temperature
extremes, additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges.
Note 3: Guaranteed with transverse air flow exceeding 400 linear F.P.M. and 2-minute warm-up period. Typical resistance values of the package
are: 0JA, (Junction to Ambient) = 90°C/W (still air); 0JA (Junction to Ambient) = 50°C/W (at 400 F.P.M. air flow); 0JA (Junction to Case) =
25°C/W.
Note 4: "A" indicates the most positive value, "B" indicates the most negative value.
Note 5: Typical values at VEE = -5.2V: TA = o°c, lEE = -105 mA; TA = 75°C, lEE = -90 mAo

3-24

Functional Description
The device is selected with Cs low and deselected with
high. The operating mode is controlled by the active
low Write Enable (WE). WE low causes the data at the
Data Input (DIN) to be stored at the selected address.
WE low also causes the output to be disabled (low due
to the 50n pull·down resistor). WE high causes the data
stored at the selected address to be present at the Data
Out (DOUT) pin.

Addressing the DM10414, DM10414A is achieved by
means of the 8 address lines AO-A7. Each of the 2 8
one-zero combinations of the address lines corresponds
to a bit location in the memory. The active low Chip
Selects together with the unterminated emitter·follower
output. allows for wire-ORing. A 50n resistor to -2V
(or an equivalent network) is required to provide a low
at the output when the device is off. This termination
is required for both single device or wire·ORed operation.

Cs

AC Electrical Characteristics
VEE = -5.2V ±10%, Output Load = 50n, 30 pF to -2.0V, T A =

aOc to

75°C
DM10414

DM10414A
SYMBOL

PARAMETER

CONDITIONS
MIN

TYP
(NOTE 61

MAX

MIN

TYP
(NOTE 61

UNITS
MAX

READ MODE
tACS

Chip Select Ac,ess
Time

tRCS

Chip Select Recovery
Time

tAA

Measured Between
50% Points

3 I

5

4

7

ns

3

5

4

7

ns

7

10

10

15

ns

(Note 7)

Address Access Time

WRITE MODE
tw

Write Pulse Width

6

3.5

8

5

ns

2

0

2

0

ns

2

0

2

0

ns

3

0

4

0

ns

2

0

3

1

ns

2

0

2

0

ns

2

0

ns

(to Guarantee
Writing)
tWSD

Data Set·Up Time
Prior to Write

tWHD

Data Hold Time
After Write

tWSA

Measured Between
50% Points

Address Set·Up Time
Prior to Write

tWHA

Address Hold Time
After Write

tWSCS

Chip Select Set·Up
Time Prior to Write

\

tWHCS

Chip Select Hold Time

2

0

After Write
tws

Write Disable Time

5

3

7

4

ns

tWR

Write Recovery Time

5

3

7

4

ns

3

4

ns

3

4

ns

RISE TIME AND FALL TIME
tr

Output Rise Time

If

Output Fall Time

Measured Between
50% Points

Capacitance
DM10414A
SYMBOL

PARAMETER

CONDITIONS
MIN

CIN

I nput Pin Capacitance

COUT

Output Pin

TYP
(NOTE 61

DM10414
MAX

MIN

TYP
(NOTE 61

UNITS
MAX

4

5

4

5

pF

7

8

7

8

pF

Measure With a Pulse
Technique

Capacitance
Note 6: Typical valuesare at VEE: -S.2V. TA: 2SoC and maximum loading.
Note 7: The maximum address access time is guaranteed to be the worst case bit in the memory using a pseudorandom testing pattern.

3-25

Switching Time Waveforms

Chip Select Access Time

50%

CHIP SELECT

80%

- - - -

-

- -

-

- -

DATA OUTPUT

E

Address Access Time

ADDRESS INPUTS_ _ _ _

tAA=s¢'

~~V-IH-B----------

DATA OUTPUT
_ _ _ _ _ _ _ _ _ _ _ _- J

VILA

~~------------

Read Mode

ADDRESS INPUTS
AO-A7

CHIP SELECT

ID. CS2. CS3

DATA INPUT
DIN

WRITE ENABLE 50%
WE
-tWHA--

--

DATA OUTPUT
DOUT
__

3-26

tAA

__

tWSA

--

Switching Time Waveforms

(Continued)

Write Mode

ADDRESS INPUTS
Ao-A7

50%

CHIP SELECT
CS1. CS2. CSJ

-

- -

-

-

-

-

-

-

-

-

-

- -- -

-

-

---

50%

DATA INPUT
DIN

WRITE ENABLE
WE

DATA OUTPUT
DOUT

Test Conditions
Loading Conditions
GND

Input Levels

16

-O.9V - - - -.., . . . . . - - - - - - - - - - .

VCC
-1.7V
tr

All timing measurements referenced to 50% of input levels
CL = 10 pF including jig and stray capacitance

DDUT ~1_5-t....._ _~

RT = 50n

A8
A9

VEE

RT

8

To.01PF
-2.0V

=tf =2.5 ns TVP

CL

T
3-27

~National

Bipolar RAMs

z.t Semiconductor

DM10415, DM10415A 1024 x 1 Eel Random
Access Memory
General Description

Features

The DM10415, DM10415A is a 1024-word by 1-bit ECl
random access memory. This fully static memory is
designed with an active low chip select and separate
I/O pins. The 10 address bits (AO through A9) are fully
decoded on the chip. Applications such as scratch pad,
cache, and buffer memories are ideal for this high speed
RAM.

•

Fully compatible with standard and voltage compensated 10k series ECl

•

Temperature range

•

Unterminated emitter-follower output for wire-ORing

•

Power dissipation decreases with increasing temperature

•

Typical address access
DM10415
DM10415A

An unterminated emitter-follower output is provided
to allow the outputs to be wire-ORed. Separate Data
In and non-inverted Data Out pins are provided. These
RAMs are compatible with compensated and uncompensated 10k ECl families.

•

O°C to +75°C

25 ns
12 ns

Typical chip select access
DM10415
DM10415A

7 ns
4 ns

Block and Connection Diagrams
Dual-In-Line Package
AD
Al
ADDRESS
DECODER

A2

WORD
DRIVER

DOUT

J2 x 32 ARRAY

AJ

15 DIN

AD

A4
Al
A2

14

cs

13

WE

12 A9

A3

11 A8

A4

10 Al

A5

A6

VEE

TOP VIEW

Order Number DM10415J
or DM10415AJ
See NS Package J16A

A5 A6 Al A8 A9

Logic Symbol
AD

Truth Table
Pin Names

Al
A2

AO-A9
DIN
DOUT
CS
WE

Address Inputs
Data Input
Data Output
Chip Select
Write Enable

3-28

CS

WE

DIN

H

X

X

L

DOUT

MODE
Not Selected

L

L

H

L

Write 1

L

L

L

L

Write 0

L

H

X

DOUT

Read

L; low (-1.7V nominal)
H ; high (-O.9V nominal)
X ; don't care

Absolute Maximum Ratings
Temperature Under Bias (Ambient)
Storage Temperature Range
VEE Relative to VCC
Any Input Relative to VCC
Output Current (Output High)
Lead Temperature (Soldering, 10 seconds)

Operating Conditions
Supply Voltage (V EE)
Ambient Temperature (T A)

-55°C to +125°C
u
-£5 C to +150°C
-7.0V to +0.5V
VEE to +0.5V
-30 mA to +0.1 mA
300°C

MIN

MAX

UNITS

-5,46

-4.94
+75

°c

o

V

DC Electrical Characteristics
VEE

= -5.2V, Output

VOL

VOHC

= 50n and

30 pF to -2.0V, TA = O°C to +75°C (Notes 1 - 4)

CONDITIONS

PARAMETER

SYMBOL
VOH

Load

Output Voltage High

Output Voltage Low

Output Voltage High

VIN

VIN

VIN

TA

B
LIMIT

VIH

Output Voltage Low

Input Voltage High

VIN

UNITS

= VIHA or VILB
O°C

-1000

-840

+25°C

-960

-810

+75°C

-900

-720

mV

= VIHA or VILB

= VIHB

O°C

-1870

-1665

+25°C

-1850

-1650

+75°C

-1830

-1625

= VIHB

mV

or VILA
O°C

VOLC

A
LIMIT

-1020

+25°C

-980

+75°C

-920

mV

or VILA
O°C

-1645

+25°C

-1630

+75°C

-1605

mV

Guaranteed Input Voltage High
for All Inputs

VIL

Input Voltage Low

O°C

-1145

-840

+25°C

-1105

-810

+75°C

-1045

-720

mV

Guaranteed I nput Voltage Low
for All Inputs

IIH

Input Current High

VIN

O°C

-1870

-1490

+25°C

-1850

-1475

+75°C

-1830

-1450

mV

= VIHA
O°C
to

220

pA

170

pA

+75°C
IlL

lEE

Input Current Low, CS

VIN

= VILB

,

+25°C

0.5

All Others

+25°C

-50

Power Supply Current

All Inputs and Outputs Open

(Pin 8) (Note 5)
O°C

-150

mA

Note 1: Conditions for testing not shown in the tables are chosen to guarantee operation under "worst case" conditions.
Note 2: The specified limits represent the "worst case" value for the parameter. Since these "wo'rst case" values normally occur at the temperature
extremes, additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges.
Note 3: Guaranteed with transverse air flow exceeding 400 linear F .P.M. and 2-minute warm-up period. Typical resistance values of the package
are: 0JA, (Junction to Ambient) = 90°C/W (still air); 0JA (Junction to Ambient) = 50°C/W (at 400 F.P.M. air flow); 0JA (Junction to Case) =
25°C/W.
Note 4: "A" indicates the most positive value, "B" indicates the most negative value.
Note 5: Typical values at VEE = -5.2V: TA = O°C, lEE =-105mA; TA = 75°C, lEE =-90 mAo

3-29

~
,..

Functional Description

::E

c

Ltf
,..
o
,..
~

::E

c

The device is selected with CS low and deselected with
CS high. The operating mode is controlled by the active
low Write Enable (WE). WE low causes the data at the
Data Input (DIN) to be stored at the selected address.
WE low also causes the output to be disabled (low due
to the 50n pull·down resistor). WE high causes the data
stored at the selected address to be present at the Data
Out (DOUT) pin.

Addressing the DM1041S/DM1041SA is achieved by
means of the 10 address lines AO-A9. Each of the 2 10
one·zero combinations of the address lines corresponds
to a bit location in the memory. The active low Chip
Select (CS) together with the unterminated emitter·
follower output allows for memory array expansion to
2048 words without additional decoding. This emitter·
follower output allows for wire·ORing. A son resistor
to -2V (or an equivalent network) is required to provide
a low at the output when the device is off. This ter·
mination is required for both single device or wire·
ORed operation.

~

o
,..

AC Electrical Characteristics
VEE

= -S.2V ±S%; Output Load = son, 30 pF to -2.0V, T A = o°c to +75°C
DM10415A

CONDITIONS

PARAMETER

SYMBOL

MIN

I

TYP
(NOTE 6)

I

MAX

MIN

I

DM10415

TYP
(NOTE 6)

I

UNITS
MAX

READ MODE
tACS

Chip Select Access

tRCS

Chip Select Recovery

7

10

ns

Input to Valid Output

4

7

10

ns

25

35

ns

(Note 7)

Time
tAA

4
Measured at 50% of

Time

12

Address Access Time

20

WRITE MODE
tw

Write Pulse Width
(to Guarantee
Writing)

tWSD

10

25

20

ns

0

5

0

ns

0

5

0

ns

5

8

5

ns

0

4

1

ns

Chip Select Set·Up
Time Prior to Write

0

5

0

ns

Chip Select Hold Time

0

5

0

ns

DM10415A

twSA

DM10415

tWSA

= 8 ns
= 20 ns

12

Data Set·Up Time
Prior to Write

twHD

Data Hold Time
After Write

tWSA

Address Set·Up Time
Prior to Write

twHA

DM10415A

tw

DM10415

tw

= 12 ns
= 25 ns

Address Hold Time
After Write

tWSCS

twHCS

After Write
tws

Write Disable Time

4

7

10

ns

twR

Write Recovery Time

4

7

10

ns

RISE TIME AND

tf

FAL~

TIME

Output Rise Time

Measured Between 20%

ns

Output Fall Time

and 80% Points

ns

Capacitance
DM10415

DM10415A
SYMBOL

PARAMETER

CONDITIONS
MIN

CIN

Input Pin Capacitance

COUT

Output Pin

TYP
(NOTE 6)

MAX

MIN

TYP
(NOTE 6)

UNITS
MAX

4

5

4

5

pF

7

8

7

8

pF

Measure With a Pulse
Technique

Capacitance
Note 6: Typical values are at VEE = -5.2V, T A'" 25°C and maxumum loading.
Note 7: The maximum address access time is guaranteed to be the worst case bit in the memory using a pseudorandom testing pattern.

3·30

Switching Time Waveforms

Chip Select Access Time

CHIP SELECT

80%
DATA OUTPUT

---- -

-- ---

VIHB

E='AA5¢-

Address Access Time

ADDRESS I NPUTS_ _ _ _ _

~V-IH-8----------

DATA OUTPUT

VILA

_ _ _ _ _ _ _ _ _ _J

~-----------

Read Mode
ADDRESS INPUTS
AO-A9

CHIP SELECT

CS

DATA INPUT
DIN

~~~~~~~~~~~~~~~~~~~$~~~~

WRITE ENABLE
WE

DATA OUTPUT
DOUT

3-31

Switching Time Waveforms

(Continued)

Write Mode
ADDRESS INPUTS
AO-A9

SO%

--- ------------------

CHIP SELECT

CS

DATA INPUT
DIN

WRITE ENABLE
WE

DATA OUTPUT
DOUT

Test Conditions
Loading Conditions
GND

Input Levels
-O.9V

CS
AO

WE

VCC

-1.7 V
tr =tf =2.S ns TYP

tr

A2
A3

A4

DOUT

AS

1
All timing measurements referenced to 50% of input levels
CL = 30 pF including jig and stray capacitance

A6

RT = 50n

A7
A8
A9

VEE

RT

8

TO.01PF
-2.0V

Cl

T
3·32

~National

Bipolar RAMs
PREVIEW

D Semiconductor
DM104221024·Bit (256 x 4) Eel RAM
General Description

Features

The DM10422 is normally a 256·word by 4·bit random ac·
cess memory. However the memory has four Block Select
(BSO-BS3) inputs which allow "WIRE OR" of any of the
four blocks for a maximum 1024·word by 1·bit memory.
The high speed access time allows its use in scratch pad,
buffer, and control storage applications. The device is
voltage compensated and is compatible with all 10K
logic. Separate Data In and Data Out pins allow the set
up of data for a write cycle while performing a read.

• 4 separate Block Select inputs for from 256 x 4 to
1024 x 1 configuration
• Typical address access time-12 ns
•

Block Select access time-4 ns

• 10k logic compatible

Block and Connection Diagrams
AS

Dual·ln·Line Package
A7

AS

veeo

vee

DOD

BSO
001

A4

A3
BSI

A2
Al

DID

013

AD

011

we 0 - - - - - 1

012
17

WE

16

AS
000

DID

BSO

001

011

liSl

002

012

iiS2

003

013

Pin Names
BSO-BS3

Block Selects

AO-A7

Address Inputs

AD

WE

Write Enable

Al

010-013
000-003

Oata Inputs
Data Outputs

A2

A2

10

15

11

14

12

13

VEE
TOPVIEW

A3
A4

Truth Table (Positive Logic)
A6
DID

011

003

012
013
WE

Y

Input

002

A7

BS2

Output

Mode

BS

WE

01

H

X

X

L

Disable

L

L

L

L

Write "0"

L

L

H

L

Write "1"

L

H

X

DO

3-33

AS

BS3
Al

Logic Symbol

A7

Read

A5
A4
A3

~National

Bipolar RAMs
PREVIEW

U Semiconductor
DM10470 4096-Bit (4096 x 1) Eel RAM
General Description

Features

The DM100470 is a 4096-bit random access memory
organized 4096-words by 1-blt. It is designed for high
speed scratch pad and buffer storage applications. It is
voltage and temperature compensated and compatible
with all 100k logic. It has separate Data In and Data Out
pins. The active low Chip Select CS and open emitter outputs allow easy expansion.

•
•
•
•
•

Typical address access time-18 ns
Typical Chip Select access time-10 ns
100K logic compatible
Open emitter outputs
Power dissipation-O.25 mW/bit

Logic Diagram
WORD
DRIVER

DDUT

64 X 64
ARRAY

SENSE AMPS
AND
WRITE
DRIVERS

ADDRESS
DECODER

ADDRESS
DECODER

AD A1 A2 AJ A4 A5

Connection Diagram

Logic Symbol

Truth Table

Dual-In-Line Package

AD
A1
A2

cs

WE

DIN

Open Emitter

A2

H

X

X

L

AJ

L

L

L

L

Write "0"

A4

L

L

H

L

Write"'"

L

H

X

Dour

A6

DOUT

A7

A4

AS
A9

A5

Pin Names

A6
10
VEE

Mode'

A1

A5

A3

Output

Inputs

AD
DOUT

A7

TOP VIEW

3-34

CS

Chip Select Inputs

AO-A"
WE

Address Inputs
Write Enable

DIN

Data Input

DOUT

Data Output

Not Selected

Read

Bipolar RAMs

~National

PREVIEW

~ Semiconductor

DM100414 256·Bit (256 X 1) Eel RAM
Gener~1

Features

Description

The DM100414 is a 256-bit random access memory,
organized 256-words by 1-bit. It is designed for high speed
scratch pads, control and buffer storage applications.
The device has three chip selects (CS1-CS3) and separate
Data In and Data Out pins. The open emitter output
allows "OR" tying for easy expansion. It is both voltage
'and temperature compensated to be compatible with all
100k logic.

•
•
•
•

Typical address access time-7 ns
Typical chip select time-4 ns
50 kfl pull-down resistors
Open emitter outputs

Logic Diagram
AD

A1

A2

X
AOORESS
OECODER

WORD
DRIVER

16 X 16 ARRAY
MEMORY CELL

A3

DOUT

Y
ADDRESS
DECODER

Connection Diagram

Logic Symbol

Truth Table

Dual·ln-Line Package

Input
Output

AD
CS2

CS3

WE

DIN

X

X

H*

X

X

L

Not Selected

L

L

L

L

L

L

Write "0··

L

L

L

L

H

L

Write",,·

L

L

L

H

X

DOUT

* One or more Chip Selects HIGH
Pin Names

TOP VIEW

3-35

Mode

CS1

CS1, CS2, CS3

Chip Select Inputs'

AD·A7

Address Inputs

DIN

Data Input

Dour

Data Output

WE

Write Enable Input

Read

Lt)

; ~National
8..... D Semiconductor

:e

c

Bipolar RAMs
PREVIEW

DM100415 1024 x 1 Eel RAM
General Description

Features

The DM100415 is a 1024-word by 1-bit ECl random access
memory_ This fully static memory is designed with an active low chip select and separate 110 pins; The 10 address
bits (AO through A9) are fully decoded on the chip. Applications such as scratch pad, cache, and buffer
memories are ideal for this high speed RAM.

• Fully compatible with standard 100k logic
• Temperature range-O °C to + 85 °C
• Unterminated emitter-follower output-full wireDRing
.

An unterminated emitter-follower output is provided to
allow the outputs to be wire-ORed. Separate Data In and
non-inverted Data Out pins are provided. These RAMs are
compatible with all 100k logic.

• Typical address access-12 ns
• Typical chip select access-5 ns

• Power dissipation decreases with
temperature

increasing

Block Diagram
AD
AI

A2

WORD
DRIVER

ADDRESS
DECODER

32 X 32 ARRAY

A3
A4

A5 A6 A7 AS A9

Connection Diagram

Logic Symbol

Truth Table

Dual-In-Line Package

cs

WE

H
L

Mode

DIN

Dour

X

X

L

Not Selected

L

H

L

Write "1"
Write "0"

DOUT
AD
A1

cs

A2

WE

A3

A9

DOUT

L

L

L

L

L

H

X

Dour

Read

L = low (- 1.7V nominal)
H =high (- O.9V nominal)

A4

X = don't care

Pin Description
AO·A9
Address Inputs

AS
VEE

A6

TOP VIEW
I

3-36

DIN

Data Input

Dour

CS

Data Output
Chip Select

WE

Write Enable

~National

Bipolar RAMs
PREVIEW

~ Semiconductor

N

General Description

Features

The DM100422 is normally a 256-word by 4-bit random access memory. However the memory has four Block Select
(BSO-BS3) inputs which allow "wire-OR" of any of the four
blocks for a maximum 1024-word by 1-bit memory_ The
high speed access time allows its use in scratch pad,
buffer, and control storage application. The device is both
voltage and temperature compensated and is compatible
with all 100k logic_ Separate Data In and Data Out pins
allow the set up of data for a write cycle while performing
a read.

• 4 separate Block Select inputs for 256 x 4 to 1024 x 1
configuration
• Typical address access time-10 ns
• Block Select access time-3 ns
• 100k logic compatible

Logic and Connection Diagrams
Dual-In-Line Package
A7

A6

013
23 A7

002

A4
A3
A2

iiS3

A5

003

A4

Vee

AJ

Veeo

Al
000

AD

A2

16

BSO

AI

15 AD

DOl

WED-----I
14 WE
13

010 12

DOD

010

BSD

001

011

BSI

003

002

013
TOPVIEW

Logic Symbol

Truth Table (Positive Logic)

AD
Al
DOD

A2

as

I~t

H

X

X

L

Disable

L

L

L

L

Write "0"
Write "1"

WE

01

Output

A3

L

L

H

L

A4

L

H

X

DO

001

AS
A6
002

A7

Pin Names

DID

BSO·Bs3

Block Select

011

AO·A7

Address Inputs

WE

Write Enable

003

012
013
WE

BSD

BSI

BS2

BS3

DIO·DI3

Data Inputs

DOO-003

Data Outputs

Y
3-37

o
o

~

DM1004221024·Bit (256 x 4) Eel RAM

AS

c

3l:
.....

Mode

Read

011

~National

Bipolar RAMs

D Semiconductor

PREVIEW

DM100470 4096·Bit (4096 x 1) Eel RAM
General Description

Features

The DM10470 is a 4096-bit random access memory
organized 4096-words by 1-bit. It is designed for high
speed scratch pads and buffer storage applications. It is
voltage compensated for high noise immunity and compatible with all 10k series logic. It has, separate Data In
and Data Out pins. The active low Chip Select CS and
open emitter outputs allow easy expansion.

• Typical address access time-30 ns
• Typical Chip Select access time-10 ns
• 10k logic compatible
• Open emitter outputs
• Power dissipation-O.25 mW/bit

Block Diagram
WORD
DRIVER

64 X 64
ARRAY

ADDRESS
DECODER

ADDRESS
DECODER

DOUT

6

7

AD A1 A2 A3 A4 A5

Connection Diagram

Logic Symbol

Truth Table

Dual-ln·Line Package
Inputs

DOUT

WE

DIN

Open Emitter

A1

H

X

X

L

Not Selected

L

L

L

L

Write "0"

L

L

H

L

Write "1"

L

H

X

DOUT

A4

A5

A2

DOUT

A6

A3

A7

AS

A4

A9

A5

Pin Names

A1D

A6

Mode

CS

AD
A1

Output

AD

CS

A11

CS

DIN

WE

TOP VIEW

3-38

Chip Select Inputs

AO·A11

Address Inputs

WE

Write Enable '

DIN

Data Input

DOUT

Data Output

Read

Section 4
Magnetic Bubble
Memories

Magnetic domain memories, provide the highest density of the extant memory technologies. The inherent
simplicity in processing and lack of "charged"
elements promise high reliability not found in traditional memory technologies. The high density also
affords low cost. The non-volatility of bubble
memories make them especially suited for portable
applications and remote terminals. The solid state
nature offers higher reliability and lower maintenance
costs than moving medium technologies. Support circuits permitting easy design into any host system are
also shown in the section.

c

Magnetic Bubble Memories en
w
0')

~National

~ Semiconductor

PREVIEW

083615 Bubble Memory Function Driver
General Description

Features

The DS3615 is a function driver that
converts digital TIL level pulses
generated by a timing circuit into the
current pulses required by National's
NBM2256 256K-bit magnetic bubble
memory_ The DS3615 consists of input
logic gates that are TIL compatible, a
D flip-flop, a voltage boost circuit, and
six current generators. The current
generators deliver constant currents for
driving the swap gate, generator
element, map gate, and replicator gate
of the magnetic bubble memory.
Operation is from Q·G to 7Q·G.

• TIL compatible inputs
• Operates from two standard
supplies: +5V, + 12V
• PNP inputs minimize loading
• Built·in voltage boost
circuitry-does not require an extra
voltage supply
• Power up/down glitch-free
protection for both supplies

053615 Functional Block Diagram

vec

VDD GND

IGEN

ISWAP

IMAP

+12V

4-1

-'"
CJ1

co

20

~
c

~ National

Magnetic Bubble Memories

D Semiconductor

PREVIEW

053616 Bubble Memory Coil Driver
General Description

Features

A, B, C, and HLD-EN are TTL
compatible low current inputs to insure
easy interfacing to MaS controller
circuits. Internal logic controls the
output sinking and sourcing transistors
to drive the X and Y bubble memory
coils in a diode bridged push-pull
configuration.
Sourcing transistors are driven into
saturation by the on-chip voltage
booster for maximum current drive to
the coil.
An internal power up/down control
circuit prevents glitches and noise on
the outputs during system
initialization.

•
•
•
•
•
•
•

CS enables the output drive
transistors. The RUN output is used to
disable function drivers during power
up/down.
The DS3616 is characterized to operate
from O°C to 70°C.

DS3616 Functional Block Diagram

GND

VDD
!+'2VI

vee
!+5VI

4-2

Two high-current push-pull outputs
TTL compatible low current inputs
Two power supplies: +5V and +12V
Internal clamp diodes
Power up/down control circuit
Optional internal voltage booster
RUN output for function driver
control

Magnetic Bubble Memories

~National

D Semiconductor

PREVIEW

053617 Bubble Memory Sense Amplifier
General Description

Features

The DS3617 is a bubble memory sense
amplifier that converts low level
signals from the magneto-resistive
detector of a bubble memory into TTL
compatible output levels. Internal
functions consist of an input bias
circuit, an Internally AC coupled
amplifier, a high-speed precision
comparator, two flip-flops and a TRISTATE® output stage.
TTL compatible control inputs allow
either average-to-peak or clamp and
strobe (peak-to-peak) senSing of the
input signal. The threshold voltage and
the input bias voltage are externally
adjustable, allowing compatibility with
different types of bubble memories.
Operation is specified from O·C to
70·C.

• +5Vand +12V supply operation
• On-chip adjustable detector bias
circuit
• Choice of average-to-peak or clamp
and strobe senSing
• Guaranteed tight threshold limits
over the specified temperature and
supply voltage range
• Threshold externally adjustable over
OmV to 10mV range
• High threshold voltage sensitivity
• TRI-STATE® output
• Compatible with a wide range of
bubble memories
• Standard 16-pin DIP

DS3617 Functional Block Diagram

+12V

DATA

TRI

GND

CLAMP

4-3

,...

:8 ~ National
~ U Semiconductor

Magnetic Bubble Memories
PREVIEW

z
INS82851 Bubble Memory Controller
General Description

Features

The INS82851 is an NMOS controller
specifically programmed for use with
National Semiconductor's NBM2256
256K-bit magnetic bubble memory. The
controller provides all the system
control needed for a single NBM2256
module, and with the addition of a few
TTL parts can control 2, 4 or 8
modules. Among the functions
provided are power up/down
sequencing, error map bootstrap,
address initialization, address
conversion and cycle counting for data
read/write, redundant bit
insertion/deletion, error detection and
correction, FIFO buffering, timing
generator for interface circuits, and
data transfer signals for DMA, interrupt
or software polling. Operation is from
O·C to 70·C.

• Controls 1, 2, 4 or 8 N BM2256
modules
• MICROBUSTM interface for
microprocessor applications
• DMA, interrupt or polled transfer
signals
• Provides complete timing generation
for interface circuits
• Redundancy insertion/deletion
• FIFO buffering
• Error detection/correction
• 40-pin DIP, +5V supply

INS82851 Controller

DOUT

00-07

1/0
Buffer

DIN

AO-A2

cs

AD

D~~--

~

I'Bus
Control

Microcoded
Control
Section

INTR
RESET

INS82851

4-4

Timing
Generator

XA
XB
YA
YB

REPMAP
REPLIC
CUT
GEN
~
STROBE
CLKMAP XIN
SRCLK
XOUT
SWAP

Magnetic Bubble Memories

~National

.
~ Semiconductor

PREVIEW

NBM2256 Bubble Memory
General Description
National Semiconductor's NBM2256 is
a low cost, non-volatile, highly reliable
solid state memory that uses magnetic
bubble technology. The NBM2256 has
the form of a dual-in-line package
complete with the required in-plane
rotating field coils and permanent
magnet bias structure.
The package has a magnetic shield
around it to protect the data from
externally induced magnetic fields.
The magnetic materials are so chosen
that data integrity is guaranteed over a
wide temperature range.
The NBM2256 memory module has a
nominal* capacity of 256k bits
organized as 256 storage loops each
having 1024 storage locations. The
storage loops have an input track with
a swap gate on one side and an
output track with a replicate gate on
the other. The input track is serviced
by a generator and the output track
leads into a sensing area where
bubbles are stretched to produce a

signal large enough to be
discriminated reliably using standard
electronic circuitry.
In addition to storage area there is
one more storage loop which can be
used for the purpose of storing
defective loop information and/or the
address reference locations.
The NBM2256 Bubble Memory can
operate asynchronously up to its
maximum operating frequency, can be
started and stopped at will and does
not lose data when power is
disconnected.

Features

o
o
o
o
o
o
o
o
o
o

• A usable number: physically there are more loops to Impart
de!ee! loleraney

Solid State
Non-Volatile
High Density
Low Power
Redundant Storage Loops
Page-Oriented Access
Sequential Read/Write
Start/Stop Capability
Modular Capacity
On-Chip Error Map

Chip Organization
REP!.)D-_
_ _ _ _ _ _ _ _ _ _ _- .
9

B

DEl COM!')

7
REF DETI-)

ACTIVE DElI-!

4

YCOILl.)

C

Y COILl-)

4-5

General Specifications
Capacity
Bubble Size
Chip Size
Shift Rate
Average Access Time
Power Dissipation
Magnetic Shielding
Operating Temperature

256K bits
3jJm
~ 100K mil2
~ 100kHz
< 7m sec.
< 1 Watt
> 20 Oe
O°C to 70°C
(case)

with the transfer-in ports of the
storage loops. A .. read" operation
consists of pulsing the replicate gate
at the proper time when the required
data block is at the transferout/replicate port. Since data is
replicated, a true non-destructive read
operation is performed which does not
require storing back the data block as
in the case of major/minor loop
organization. The replicated data block
then is sequentially propagated
through the detectors to be sensed
electronically. A data modifying
operation is similar to the "write"
operation since "true swap" gates
used exchange the new data block
with the old one in one step. The old
data blo"ck is discarded by propagating .
through the guard rails. The swap
gates also eliminate the necessity of
sustaining power for a duration longer
than the swap operation in the event
of power failure.

~

Applications
o

o
o
o
o
o
o

o

Microcomputer Mass Storage
Word Processing Terminals
Stored Program Controllers
Measurement and Test Equipment
Electronic Disc Applications
Point-of-Sale Terminals
Operating System Storage
Fast Auxiliary Storage

Functions
What are magnetic bubbles
A "write" operation requires current
pulsing the generators sequentially
according to the data pattern desired
and then pulsing the swap gate when
the data block propagates and aligns

Magnetic bubbles are tiny cylindrical
magnetic domains which are formed
in a thin magnetic layer when a
stabilizing magnetic field of optimum

National's Magnetic Bubble Module
and Required Interface A Functional Block Diagram
+5V---+
+12V---+
NBM2256

+V

X
COIL

ACTIVE
REFERENCE
DETECTOR
DATA
BUS

y

INS82851
CONTROLLER

COIL

GENERATE
SWAP

110
CONTROL

REPLICATE
Mpp

4-6

OS3617
SENSE
AMP

Applications

magnitude is applied orthogonally to
the magnetic layer. This magnetic
layer is grown by liquid phase epitaxy
techniques over a non-magnetic
substrate.
The cylindrical magnetic domains can
be moved over in a controlled manner
with the aid of an in-plane rotating
field by the creation of attracting
manetic poles in a soft magnetic layer
such as Permalloy. These domains
can be created and destroyed at will
by using magnetic fields generated by
current-carrying conductors. The
absence or presence of a domain can
be used to denote binary information
("0", "1 ") used in digital computers.
The detection of the cyclindrical
domains is performed by their interaction with a magneto-resistive element
whose change in resistance is converted into a voltage by forcing a constant current through the element.

Magnetic bubble memories are
presently used in portable terminals,
as message recorders in telephone
systems and as floppy disc replacements where the environment is
hazardous to rotating memories. In
addition, they are being considered for
microprocessor mass storage applications, in word processing machines, in
point-of-sale terminals where the small
number of terminals can not justify a .
rotating memory, in data communication links, in programmable calculators, in diagnostic data logging for
large computers, and in military and
airborne applications where reliability
is of prime importance. They are also
being considered as cache between
main memory and large capacity disc
files to improve performance of the
total system.

Physical Dimensions inches (millimeters)
I?'JI National
~ Semiconductor

NBM2256

7909D43--------r~

LOT # AND DATE
OF FINAL TEST

XXXXXX
XXX

~

XXXXXX

1.100

,

HEXADECIMAL COOING
OF INOPERATIVE LOOPS-2 DIGITS
PER LOOP-MAXIMUM
20 LOOPS

PINI

I

t-~---121.941-----

I

-.L
0.150

CJ.i1i

T

~
0.125
(Jllij'

~10.'001_

ii254i1

~4'~I~l
=

I- - - -

-----u=====ffi111f

_---=

I

1.200

130.481-----

4-7

Section 5

MOSEPROMs

Customer-reprogram mabie read-only memory has
made a remarkable impact upon the art, of logic
design. National's EPROMs make practical new
applications of microprocessors. National is a volume
production source of the products included here, and
is developing larger EPROMs for tomorrow's
applications.

~National

MOS EPROMs

~ Semiconductor

MM1702A 2048·Bit (256 x 8) UV Erasable PROM
General Description
The MM1702A is a 256 word by 8-bit electrically
programmable ROM ideally suited for uses where fast
turn-around and pattern experimentation are important_
The MM1702A undergoes complete programming and
fun,ctional testing on each bit position prior to shipment,
thus insuring 100% programmability.

The MM1702A is fabricated with silicon gate technology.
This low threshold technology- allows the design and
production of higher performance MOS circuits and
provides a higher functional density on a monolithic
chip than conventional MOS technologies_

The MM1702AQ is packaged in a 24-pin dual-in-line
package with a transparent lid. The transparent Iid allows
the user to expose the chip to ultraviolet light to erase
the bit pattern_ A new pattern can then be written into
the device. The MM 1702AD is packaged in a 24-pin
dual-in-line package with a metal lid and is not erasable.

Features
• Fast programming-30 seconds for all 2048 bits
• All 2048 bits guaranteed programmable-100%
factory tested
• Fully decoded, 256 x 8 organization
Iii Static MOS-no clocks required
• Inputs and outputs DTL and TTL compatible
• TRI-STATE® output-OR-tie capability
• Simple memory expansion-chip select input lead
• Direct replacement for the Intel 1702A

The circuitry of the MM1702A is entirely static; no
clocks are required.
A pin-for-pin metal mask programmed ROM, the
MM1302 is ideal for large volume production runs of
systems initially using the MM 1702A_

Block and Connection Diagrams

Dual-I n-Line Package
PRO·
Voo

124

Vee

23

Vee

A3

22

A4

21

AS

20

AS

19

11

A7

Vee

17

Vo•

16

15

e{ GRAM

13

14

DATA
OUT 1

-

-

DATA
OUT8
Notl: In the 'lid modi I logic
"''',tth •• ddrll.inputslndd,tl
outputsil.hiUhlndloyic"O"il

• low.
I

A2

2

Al

3

AO

4

6

8

7

I

8

10

II

\~L~~B....;.-..;...-.O.;.A...
TA....O;..U-T...;.......;--:M~:a'

1'2
Vee

TOPVIEW
·Thilpinillhldu,inputl,ldduringprogrlmming.

Pin Names

Order Number MM1702AQ
See NS Package J24CQ

AO-A 7

Address Inputs

CS

Chip Select Input

DOUT

1 -

DouT a

Data Outputs
Pin Connections·

MODE/PIN
Read
Programming

12

13

14

15

16

22

23

(Vee!

(PROGRAM)

(CS)

(Vee)

(VGG)

(Vee)

(Vee)

Vee
GND

Vce
Program Pulse

GND
GND

Vee
Vas

VGG
Pulsed VGG (V 1L4P )

Vec
GND

Vee
GND

*The external lead connections to the MM 1702A differ, depending on whether the device is being programmed or used in
read mode_ (See following table.) In the programming mode, the data inputs are pins 4-11 respectively.

5-1

Absolute

Ma~imum

Ratings

(Note 1)

Storage Temperature
Power Dissipation
Read Operation
I nput Voltages and Supply Voltages with
Respect to Vee
Program Operation
Input Voltages and Supply Voltages with
Respect to Vec
Lead Temperature (Soldering, 10 seconds)

-65°C to +125°C
2W
+0.5V to .,...20V

-48V
300°C

Read Operation DC Characteristics
TA = o°c to +70°C, Vee = +5V ±5%, Voo = -9V ±5%, V GG = -9V ±5%, unless otherwise noted.
voltages and T A = 25°C. (Note 2)

SYMBOL
III

PARAMETER
Address and Chip Select

CONDITIONS

MIN

Typic~1 values are at nominal

TYP

MAX

UNITS

VIN ;" O.OV

1

J.1A

1

J.1A

5

10

mA

35

50

mA

CS = 0.0, 10L = 0.0 mA, T A = 25°C

32

46

mA

CS = Vee -2, 10L = 0.0 mA,

38.5

60

mA

8

14

mA

13

mA

1

J.1A

V ee -4.1

V

V cc -6

V

Vee+ 0 .3

V

I nput Load Current
I LO

Output Leakage Current

V OUT = O.OV, CS = V ee -2

1000

Power Supply Current

VGG = Vee, CS = Vee -2
10L = 0.0 mA, T A = 25°C,
(Note 2)

1001

Power Supply Current

-

CS = Vee -2, 10L ~ 0.0 mA,
T A =25°C

1002

Power Supply Current

1003

Power Supply Current

-

T A = O°c
ICF1

Output Clamp Current

V OUT = -1.0V, T A = O°C

leF2

Output Clamp Current

V OUT = -1.0, T A = 25°C

IGG

Gate Supply Current

V IL1

Input Low Voltage for

-1.0

TTL Interface
V IL2

Input Low Voltage for

Voo

MOS Interface
V IH

Address and Chip

V ee -2

Select Input High
Voltage
IOL

Output Sink Current

V OUT = 0.45V

IOH

Output Source Current

V OUT = O.OV

VOL

Output Low Voltage

10L = 1.6 mA

V OH

Output High Voltage

10H = -100J.1A

1.6

4

mA

-2.0

mA
-D.7

3.5

4.5

0.45

V
V

Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Note 2: Power· Down Option: VGG may be clocked to reduce power dissipation. The average 100 will vary between 1000 and 1001 depending
on the VGG duty cycle (see typical characteristics)' For this option, please specify MM1702AL.

5·2

Read Operation AC Characteristics
T A = o°c to +70°C, Vee

= +5V ±5%, V DD = -9V ±5%, VGG =-9V ±5%, unless otherwise noted.
PARAMETER

SYMBOL
Freq.

Repetition Rate

tOH

Previous Read Data Valid

tAee

Address to Output Delay

TYP

MIN

MAX

UNITS

1

0.7

MHz

100

ns

1

ps

100

ns

1

ps

tDVGG

Clocked VGG Set·Up (Note 1)

tes

Chip Select Delay

teo

Output Delay From CS

900

ns

tOD

Output Deselect

300

ns

toHe

Data Out Hold in Clocked VGG Mode (Note 1)

5

p.s

-

Capacitance Characteristics
SYMBOL

PARAMETER

T A = 25°C (Note 3)

CONDITIONS

= Vee

CIN

Input Capacitance

All Unused

COUT

Output Capacitance

Pins Are

CS = Vee

CVGG

VGG Capacitance
(Note 1)

At ac
Ground

VOUT

VIN

VGG

MIN

UNITS

TYP

MAX

8

15

pF

10

15

pF

30

pF

= Vee
= Vee

Note 3: This parameter is periodically sampled and is not 100% tested.

Read Operation Switching Time Waveforms
(b) Power·Down Option (Note

(al Constant VGG Operation

11

I--CYCLETIME'l/l~

ADDRESS

v," ""V 10%

.

-A

r
A--

·::-{
..~ f=".~
~

CLOCKEO Vcc
VGG

DATA
OUT

DATA
OUT

VOL-+--------~---J·

:',~X:
VOl

DATA
OUT

OATA OUT
INVALIO

\1

(NOTE 11

r=_"'"_c____
II DATA
OUT
INVALID

V," jLECTION OF OATA OUTPUT IN DR·TIE OPERATION

~

~ V'H----l~

II
"'+-___"':"~

VOL-----'--..J-------

DESELECTION OF DATA DUTPUT IN OR·TIE OPERATION

ADDRm

VGG

VO" _ _ _
tAC_C=-1

VOH-+------~

ADDRESS VOl

I

V'H

~

fS

90%~

toO
VOH----lnr-

!-=
II

VOL

teo

.

t---

VOH--t----,.
DATA OUT

Conditions of Test:
Input pulse amplitudes: 0-4V. tro If $ 50 ns. Outputlold is 1 TTL pte; measure·
ments mJd. It output of TTL gue (!Po ~ 15 nsJ,C L -15 pF.

Note 1: The output will r.mlin y,lid for toHe IS 10n;l. clocked VaG it.1 Vee. An
address thange mly occur IS soon .sthe output is Mnlld (tlocbd VaG mav still bu.
Vccl. Dill blcomes invalid for the old Iddress when clocked VaG is returned to VaG'
Not. 2: If ES makes. transition hom V1L to V1H whill clockld VaG is It Vaa. thin
desllection of output occurs.t IoD IS shown in stltic oplrltion with canstlnt VGG .

5·3

pw

Program Pulse Width

TYP

MAX
20

VGG = -35V, Voo =

3

UNITS
%
ms

V PROG = -48V
tow

Data Set-Up Time

25

/lS

tOH

Data Hold Time

10

/ls

tvw

V oo , VGG Set-Up

100

tvo

V oo , VGG Hold

10

tACW

Address Complement

/ls

100

/lS

(Note 6)

25

/lS

(Note 6)

25

/lS

Set-Up
tACH

Address Complement
Hold

tATw

Address True Set-Up

10

/ls

tATH

Address True Hold

10

/ls

Note 6: All 8 address bits must be in the complement state when pulsed VOO and VGG move to their negative levels. The addresses
(0-255) must be'programmed as shown in the timing diagram until data reads true, then over-programmed 4 times that amount.
(Symbolized by x + 4x.l
.

5-4

Programming Operation Switching Time Waveforms

-40TO
-48

PUlSEDV oo
PQWERSUPPlV

-4610
-48

PUlSEOV GG
PQWERSUPPlY
. J~ TO

·40
PROGRAMMING
PULSE

-46TO
-48
DATA INPUT
CondlllonsofTrst

(OEVICE

Input pul~t'
~'OV

OUTPUT
lINES)-46
-48

IIs •• nd

hllllmes_

Ij./I

Typical Performance Characteristics,
Output Current vs VDD
Supply Voltage

IDD Current vs Temperature

;t
~

...z

a:
a:

:::>

'"'cc

39
38
Vee' +5V
37 \
Vee' -9V
VGG • -9V
36
35 ~
INPUTS' Vee
34
OUTPUTS ARE OPEN
1'\
33
~
1 1_ r--r32
I' " CS'V ee _ r - r
31
30
29 r-- c,s', o.~v

,

1

"'

2~

20

40

~

...z

IA
r- s';ECI~IED
- r - llPE~~~~~

a:
a:

:::>

'"'

- Vee' +5'V
I---3 -VGG'-9V
_ VOL' +0.45V
TA ' +25°C
z
-3.5
a:
""""01.

12

a:
a:

10

...

'"'
60

80

100

tsr~

:::>
Q

t,......-'
-4

-3

-1

0

...z

-3

-5

'"'

-6

-7

-8

-9

10

-10

~-

;t

.g

45
40 I- CLOCKED VGG ' -9V
Vee' -9V
35 lts • V'H
• +25°C
TA
30
l-

c
c

25

'"

20

~

900
800

V

V

]

700

~

600

>= 500

/'"

~

,/

_

,/

ILi"

Access Time vs Temperature
1000
900

-~

700
600

--

-

>= 500

'"

'"'..:'"'

400
1 TTL LOAD", 20 pF
Vee = +5V
Vee = -9V

300
200
100

VfG ~ -9Y

I

,

10 20 30 40 50 60 70 80 90
AMBIENT TEMPERATURE

5-5

60

70

1-+--+--+-+-+-+--+--+-+--1
1-+--+--+-+-+-+--+--+-+_--1
I---jH-4""",**+=:f=~

1-+--+--+-+-+-+--+--+-+--1
1-+--+--+-+--+-+--+--+--+---1
I-t-t-+--t-t-t-l TTL LOAD

200

I-t-t-t-t-t-t- VGG • -9V

Vee' +5V
Veo' -9V

Tr~25°f
10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (pF)

DUTY CYCLE (%)

800

50

400
300

100

OUTPUT VOLTAGE (V)

40

1000 r-~~-r--r--'-""T""""""'''''''''''''''''''''''

10 20 30 40 50 60 70 80 90 100

1

3D

Access Time vs Load
Capacitance

15
10

20

AM81ENT TEMPERATURE rC)

Average Current vs Duty
Cycle for Clocked VGG
(Note 1)

vr
V

-2

~

SUPPLY VOLTAGE (V)

./

'"'z

;t

a:
a:

1

-4

CC)

:::>

...
...

'"'

:::>

120

Vee' +5V
Vee' -9V
VGG • -9V
TA ' +25"C

""en

a:
a:

:::>

,

~

16

....~z

fi

;t

Output Sink Current vs
Output Voltage
14

...z

7- 7-

:::>

AMBIENT TEMPERATURE

;t

;t
~

a:

1 1
1 1

27

Program Waveforms

I

;t

re)

Operation of the

M~1702A

in Program Mode

Initially, all 2048 bits of the ROM are in the "0"
state (output low). Information is introduced by selectively programming "l's" (output high) in the proper bit
locations.

mInimum of 10)1s before the program pulse is applied.
The addresses should be programmed in the sequence
0-255 for a minimum of 32 times. The eight output
terminals are used as data inputs to determine the
information pattern in the eight bits of each word. A low
data input level (-48V) will program a "1" and a high
data input level (ground) will leave a "0" (see table on
page 4-4). All eight bits of .one word are programmed
simultaneously be setting the desired bit information
patterns on the data input terminals.

Word address selection is done by the same decoding
circuitry used in the READ mode (see table for logic
levels). All 8 address bits must be in the binary comple·
ment state when pulsed V DD and VGG move to their
negative levels. The addresses must be held in their binary
complement state for a minimum of 25)1s after V DD and
V GG have moved to their negative levels. The addresses
must then make the transition to their true state a

During the programming, V GG , V DD and the Program
Pulse are pulsed signals.

MM1702A Erasing Procedure
out short·wave filters, and the MM 1702A to be erased
should be placed about one inch away from the lamp
tubes. There exists no absolute rule for erase time.
Establish a worst case time required with the equipment.
Then over·erase by a factor of 2, i.e., if the device
appears erased after 8 minutes, continue exposure for
an additional' 16 minutes for a total of 24 minutes.
(May be expressed as x + 2x.)

The MM1702A may be erased by exposure to high
intensity short·wave ultraviolet light at a wavelength of
2537A. The recommended integrated dose (i.e., UV
intensity x exposure time) is 6W sec/cm 2 . Examples of
ultraviolet sources which can erase the MM1702A in 10
to 20 minutes are the Model UVS·54 and Model S-52
short-wave ultraviolet lamps manufactured by Ultra·
Violet Products, Inc. (5114 Walnut Grove Avenue,
San Gabriel, California). The lamps should be used with·

5-6

~National

MOS EPROMs

~ Semiconductor
3:
3:
I\)
~

o

.....

MM2708, MM2708·1 8192·Bit
(1024 x 8) UV Erasable PROMs

CO

General Description

Features

The MM2708, MM2708-1 are high speed 8192 UV
erasable and electrically reprogrammable EPROMs
ideally suited for applications where fast turn-around
and pattern experimentation are important requirements.

•

1024 x 8 organization

• 800 mW max
•

Low power during programming

• Access time - MM2708, 450 ns; MM2708-1, 350 ns

The MM2708, MM2708-1 are packaged in a 24-pin
dual-in-line package with transparent lid. The transparent lid allows the user to expose the chip to ultraviolet Iight to erase the bit pattern. A new pattern can
then be written into the devices by following the programming procedure.

• Standard power supplies: 12V, 5V, -5V
• Static-no clocks required
•

These EPROMs are fabricated with the reliable, high
volume, time proven, N-channel silicon gate technology.

Inputs and outputs TTL compatible during both
read and program modes

• TRI-STATE® output

Dual-In-Line Package

Block and Connection Diagrams

24

A7
+-VDD+12V
+-vee+ 5V
+-vss GND
+-V BB --5V
DATA OUTPUTS (PRDGRAM INPUTS)
Dl-08

Vee

A6

23 A8

AS

22 A9

A4

21 VBB

A3

20 tSlWE

A2

19

AI

18

I

AD

17 08

I

Dl

16

_ _ PROGRAM
I
PULSE

I

I

02

I
I
I

03

I

Vss

10

15

11

14

VDD
PROGRAM

07
06

05
13 04

12

L ______ ~-------------~

TOPVIEW
Drder Number MM2708Q or MM2708Q-1
See NS Package J24CQ

Pin Connection During Read or Program

MODE

PIN NUMBER
18
19

9-11,13-17

12

Read

DOUT

VSS

VSS

VDD

Program

DIN

VSS

Pulsed

VDD

20

21

24

VIL

VBB

Vee

VIHW

VBB

Vee

VIHP
5-7

Pin Description
AO-A9
01-08

CS/WE

Address inputs
Data outputs
Chip select/write enable input

~

Absolute Maximum Ratings

(Note 1)

-25°C to +85°C
-65°C to +125°C
20V to -o.3V
15V to -0.3V

Temperature Under Bias
Storage Temperature
VDD with Respect to VSB
VCC and VSS with Respect to VSB
All Input or Output Voltages with
Respect to VBS During Read

CSIWE Input with Respect to VSS
20V to-o.3V
During Programming
35V to-o.3V
Program Input with Respect to VSS
Power Dissipation
1.5 W
300°C
Lead Temperature (Soldering, 10 seconds)

15V to-0.3V

Read Operation
DC Operating Characteristics
TA

= DoC to +70°C, vcc = 5V ±5%,

VDD

= 12V ±5%, vss = -5V ±5%, vss = OV,
CONDITIONS

PARAMETER

SYMBOL

Address and Chip Select Input

III

unless otherwise noted, (Note 3)

VIN

MIN

= 5.25V or VIN = VIL

TYP

MAX

UNITS

1

10

p.A

1

10

p.A

44

65

mA

7

10

mA

34

45

mA

Sink Current

= 5.25V,

= 5V

ILO

Output Leakage Current

VOUT

100

VDD Supply Current

Worst·Case Supply Currents, All Inputs
High, CS/WE

ICC

= 5V, T A = DoC

Worst·Case Supply Currents, All Inputs

VSS Supply Current

High, CS/WE
VIL

= 5V, T A = DoC

Worst·Case Supply Currents,AII Inputs

VCC Supply Current

High, CS/WE
ISS

CS/WE

= 5V, T A = DoC

Input Low Voltage

VSS

_0.65

3.0

VCC+1

V
V

VIH

Input High Voltage

VOH1

Output High Voltage

IOH

= -100p.A

3.7

V

VOH2

Output High Voltage

IOH

= -1mA

2.4

V

VOL

Output Low Votlage

IOL

= 1.6 mA

Po

Power Dissipation

0.45

V

800

mW

:AC Electrical Characteristics
T A = DoC to +70°C,
SYMBOL
tAce

vcc = 5V ±5%, VDD = 12V ±5%, vss = -5V ±5%, vss = OV, unless otherwise noted

PARAMETER
Address to Output Delay

teo

Chip Select to Output Delay

tDF

Chip Deselect to Output Delay

CONDITIONS
Output Load: 1 TTL Gate and CL = 100 pF,
Input Rise and Fall Times':; 20 ns: Timing
Measurement Reference Levels: O.BV

Address to Output Hold
tOH
CAPACITANCE (Note 2)
elN

Input Capacitance

COUT

Output Capacitance

MM2708
MIN
MAX

and 2.BV for Inputs; O.BV and 2.4V for
Outputs, Input Pulse Levels: 0.65V to 3V
VIN

= OV, T A = 25°e, f = 1 MHz

VOUT

= OV, T A = 25°C. f = 1 MHz

a
a

MM2708-1
MIN
MAX

UNITS

450

350

ns

120

120

ns

120

120

ns
ns

0
6

6

pF

12

12

pF

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing. T A = 25°C. f = 1 MHz
Note 3: Typical conditions are for operation at: T A = 25°C, VCC = 5V, VOO = 12V, VSS = -5V, and VSS = OV.

5·8

Switching Time Waveforms
ADDRESS

~/WE

DATA~~~~~~~~~~~
DUT,"~~~~~~~~~~

Programming Instructions
Initially, and after each erasure, all bits of the MM2708,
MM2708·1 are in the "1" state (output high). Inforation is introduced by selectively programming "0"
into the desired bit locations. A programmed "0"
can only be changed to a "1" by UV erasure.

required is a function of the program pulse width (tpW)
according to N x tpw ~ 100 ms.
The width of the program pulse is from 0.1 to 1 ms. The
number of loops (N) is from a minimum of 100 (tpw =
1 ms) to greater than 1000 (tPW = 0.1 ms). There must
be N successive loops through all 1024 addresses. It is
not permitted to apply N program pulses to an address
and then change to the next address to be programmed.
Caution should be observed regarding the end of a pro·
gram sequence. The CS/WE falling edge transition must
occur before the first address transition when changing
from a program to a read cycle. The program pin should
also be pulled down to VI LP with an active instead of a
passive device. This pin will source a small amount of
current (lIPL) when CS/WE is at VIHW (12V) and the
program pulse is at VILP.

The circuit is set up for programming operation by
raising the CE/WE input (pin 20) to +12V. The word
address is selected in the same manner as in the read
mode. Data to be programmed are presented, 8 bits in
parallel, to the data output lines (01-08). Logic levels
for address and data lines and the supply voltages are
the same as for the read mode. After address and data
set up, one program pulse per address is applied to the
program input (pin 18). One pass through all addresses
is defined as a program loop. The number of loops (N)

Programming Characteristics
TA = 25°C, VCC

= 5V ±5%, VDD =

12V ±5%, VBB

= -5V ±5%, VSS = OV, unless otherwise noted

DC Programming Characteristics
SYMBOL
III

PARAMETER
Address and CS/WE Input

CONDITIONS
VIN

MIN

TYP

= 5.25V

MAX

UNITS

10

/1 A

Sink Current
IIPL

Program Pulse Source Current

3

mA

IIPH

Program Pulse Sink Current

20

mA

IDO

VOO Supply Current

44

65

mA

7

10

mA

34

45

rnA

Worst·Case Supply Currents, All Inputs High,
CS/WE

ICC

VCC Supply Current

Worst·Case Supply Currents, All Inputs High,
CS/WE

IBB

VBB.SUpply Current

= 5V, TA = O°C

Worst·Case Supply Currents, All Inputs High,
CS/WE

VIL

= 5V, T A = O°C

= 5V, T A = O°C

Input Low Level (Except

VSS

0.65

V

3.0

VCC+1

V

Program)
VIH

Input High Level, All
Addresses and Oata

VIHW

CS/WE Input High Level

Referenced to VSS

11.4

12.6

V

VIHP

Program Pulse High Level

Referenced to VSS

25

27

V

VILP

Program Pulse Low Level

VIHP - VI LP

VSS

1

V

= 25V

Min

5·9

AC Programming Characteristics
PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

tAS

Address Set-.Up Time

10

/lS

tcss

CS/WE Set-Up Time

10

/lS

tDS

Data Set-Up Time

10

/lS

tAH

Address Hold Time

1

/lS

tCH

CS/WE Hold Time

0.5

/lS

tDH

Data Hold Time

1

tDF

Chip Deselect to Output Float Delay

0

tDPR

Program to Read Delay

tpw

Program Pulse Width

tPR
tpF

/lS

120

/lS

10

/lS

0.1

1.0

ms

Program Pulse Rise Time

0.5

2.0

/lS

Program Pulse Fall Time

0.5

2.0

/lS

Programming Waveforms
READ
(AFTER N PRDG ~
LDDPS)

1 OF N PROGRAM LOOPS
VIHW

C'S"iWE

,,,J

ICH(D.5)--j

I--ICSS(IO)VIH
ADDRESS
VIL

VIH
DATA
VIL

J
J

ADDRESS 0

ADDRESS 1

-

I-IAS(10)-

-

I--I0S(1D)IpR(D.5)VIHP

f---

(0.1 ms MIN!.-I
IpW (1.0 ms MAX)

,

I - IAH(1)

K:

I-- 10H(1)

-lpF(D.5)

ADDRESS 1023

-

-

I- (NOTE 1)

~

AODRESSD

I- IAH(1)
IACC MAX
DATA DUT~ ~DATADUT~
VALID
INVALlO,~

-

I-- 10H(1)
10PR(lD MAX)

j

PROGRAM
PULSE

VIL

\

~

Note 1: The CS/WE transition must occur after the program pulse transition and before the address transition.
Note 2: Numbers in parentheses indicate minimum timing in microseconds unless otherwise specified.

5-10

Functional Description
ERASING

if a UV lamp with a 12,000 pW/cm 2 power rating is
used. The MM2708 to be erased should be placed
1 inch away from the lamp and no filters should be used.

The MM2708 is erased by exposure to high intensity
ultraviolet light through the transparent window. This
exposure discharges the floating gate to its initial state
through induced photo current. It is recommended
that the MM2708 be kept out of direct sunlight. The
UV content of sunlight may cause a partial erasure
of some bits in a relatively short period of time. Direct
sunlight can also cause temporary functional failure.
Extended exposure to room level fluorescent lighting
will also cause erasure. An opaque coating (paint, tape,
label, etc.) should be placed over the package window
if this product is to be operated under these lighting
conditions.

An erasure system should be calibrated periodically.
The distance from lamp to unit should be maintained
at 1 inch. The erasure time is increased by the square
of the distance (if the distance is doubled the erasure
time goes up by a factor of 4). Lamps lose intensity
as they age. When a lamp is changed, the distance is
changed, or the lamp is aged, the system should be
checked to make certain full erasure is occurring. Incomplete erasure will cause symptoms that can be
mislea(iing. Programmers, components and system
designs have been erroneously suspected when incomplete erasure was the basic problem.

An ultraviolet source of 2537 A yielding a total integrated dosage of 15 watt-seconds/cm 2 is required. This
will erase the part in approximately 15 to 20 minutes

Typical AC Performance Characteristics
Access Time vs Load
Capacitance

Access Time vs Temperature
500

400
TA

1 TTL LOAD + 100 pF

-:1

400

,..,.

;: 300

..,'"

-~

'-'

cr 200

..,I

$

..sw

---

300

:;;

;:

~

~

=25°C

- ---

f--~

f--

200

cr
I

'-'

$

100

100

o
-20

20

40

60

BO

100

TA - AMBIENT TEMPERATURE (OC)

200

300

400

CL - LOAD CAPACITANCE (pF)

5-11

500

s:
s:
I\)
~

.....

o

CO.

~National

MOS EPROMs

~ Semiconductor

MM271616,384-Bit (2048 x 8) UV Erasable PROM
General Description

Features

The MM2716 is a high speed 16k UV erasable and
electrically reprogram mabie EPROM ideally suited for
appl ications where fast turn-around and pattern experimentation are important requirements.

• 2048 x 8 organization
• 525 mW max active power, 132 mW max standby
power
• Low power during programming
• Access time-MM2716, 450 ns; MM2716-1, 350 ns;
MM2716-2, 390 ns
• Single 5V power supply
• Static-no clocks required
• Inputs and outputs TTL compatible during both
read and program modes
• TRI-STATE® output

The MM2716 is packaged in a 24-pin dual-in-line package with transparent lid. The transparent lid allows
the user to expose the chip to ultraviolet light to erase
the bit pattern. A new pattern can then be written into
the device by following the programming procedure.
This EPROM is fabricated with the reliable, high volume,
tirne proven, N-channel silicon gate technology.

Block and Connection Diagrams *
Dual-In-Line Package

+++-

A1
VPP+5V
VCC+5V

A6

VSSGNO
A5

OATA OUTPUTS (PROGRAM INPUTS)
00-01 (00-01)

A4

A3
A2

Al

18 CElPGM (E/P)

AO

11 01(01)

0 0 (00)

16 06 (06)

01 (01) 10

15 Os (05)

02 (02) 11

14 04 (04)

vss

12

13 03 (03)
~------------~
TOP VIEW

Order Number MM27160, MM27160-1
or MM27160-2
See NS Package J24CO

Pin Connection During Read or Program

Pin Names

PIN NAME/NUMBER
MODE

Read
Program

CE/PGM
(E/P)
18

OE

VIL
Pulsed VIL
to VIH

VIH

(6)

VPP

VCC

OUTPUTS

20

21

24

9-11,13-17

VIL

5

5

DOUT

25

5

DIN

AO-Al0
.00-07 (00-07)
CE/PGM fE/PI
OE(G)
VPP

vcc

vss

*Symbols in par'entheses are proposed industry standard

5-12

Address Inputs
Data Outputs
Chip Enable/Program
Output Enable
Read 5V, Program 25V
Power (5V)
Ground

Absolute Maximum Ratings
Temperature Under Bias
Storage Temperature
VPP Supply Voltage with Respect
to VSS

(Note 1)
All Input or Output Voltages with
Respect to VSS (except VPP)
Power Dissipation
Lend Tempernture (Soldering, 10 seconds)

-25°C to +85°C
-65°C to +125°C
26.5V to -0.3V

6V to -0.3V
1.5W
300°C

READ OPERATION (Note 2)
DC Operating Characteristics
O
TA = oOe to +7o e, vee = 5V ±5%, (vee = 5V ±10% for MM2716-1),
Vpp = vee ±O.6V (Note 3), VSS = OV, unless otherwise noted.
SYMBOL

PARAMETER

CONDITIONS

III

I nput Current

VIN

ILO

Output Leakage Current

VOUT

IPPl

VPP Supply Current

VPP

ICCl

VCC Supply Current' (Standbyl

CE/PGM

= VIH,

C'E/PGM

=

=

= 5.85V
-

OE

= VIL

10

ICC2

vec Supply

VIL

Input Low Voltage

0.1

VIH

Input High Voltage

2.0

VOH

Output High Voltage

IOH

=

VOL

Output Low Voltage

IOL

= 2.1

AC Characteristics

MAX

= 5.25V, CE/PGM = 5V

-

Current (Active I

TYP

MIN

= VIL

5.25V or VIN

OE = VIL

57

UNITS

10

JJ.A

10

JJ.A

5

III A

25

mA

laO

mA

0.8

V

Vec + 1

V

0.45

V

2.4

400JJ.A

V

lllA

(Note 4)

o

TA = oOe to +70 e, vee = 5V ±5%, (vee = 5V ±10% for MM2716-1).
VPP = vee ±O.6V (Note 3). VSS = OV, unless otherwise noted.
SYMBOL

MM2716

PARAMETER
ALTERNATE

TAVOV

Address to Output Delay

tCE

TELOV

CE to Output Delay

OE=VIL

tOE

TGLOV

Output Enable to Output Delay

CE/PGM = VIL

tDF

TGHOZ

Output Enable High to Output Hi·Z

CE/PGM = VIL

tOH

TAXOX

Address to Output Hold

C'E/PGM =

too

TEHOZ

CE to Output Hi·Z

OE

CE/PGM = OE

-

= VIL

-

-

6E = VIL

= VIL

MM2716·2
UNITS

MIN

tACC

Capacitance

MM2716·1

CONDITIONS

STANDARD

MAX

MIN

MAX

350

390

ns

450

350

390

ns

120

lOa

0

100

0

a
a

MIN

450

120
0

MAX

100

0

100

a

120

ns

lOa

ns

100

ns

0

0

ns

(Note 5)

T A = 25°e, f = 1 MHz
SYMBOL

PARAMETER

TYP

MAX

CI

I nput Capacitance

VIN = OV

4

6

pF

CO

Output Capacitance

VOUT = OV

8

12

pF

CONDITIONS

UNITS

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Typical conditions are for operation at: TA = 25°C, VCC= 5V, VPP = VCC, and VSS = OV.
Note 3: VPP may be connected to VCC except during program. The ±0.6V tolerance allows a circuit to switch VPP between the read voltage
and the program voltage.
Note 4: Output load: 1 TTL gate and CL = 100 pF. Input rise and fall times.s. 20 ns.
Note 5: Capacitance is guaranteed by periodic testing.

5-13

CD

it:

Switching Time Waveforms *

C\I

:E
:E
Read Cycle (CE/PGM = VI L)
VIH
ADDRESSES
VIL

'@ff~~
'l///"

K

VALID

VALID

tOH
--(TAXQX)-VIH

\

OUTPUT ENABLE
VIL

..

VOH

I ...
I

tACC
(TAVIlV)----

I

tOE
(TGLOV)

tDF
(TGHIlZ)--

J

Hi-Z

OUTPUT

..

-,

VOL

:-~

VAllO

Hi-Z

1/

Read Cycle (OE = VI L)
VIH~~~~~-'------------------------~

ADDRESSES
VIL~~~~~~~

VIH

VALID
______________________

VALID
~

===========I:=======\.

CHIP ENABLE
VIL-----------t--------~----~--~---------J

~--_-I_- tCE
tACC
(TELIlV)
(TAVIlV)-

VOH
OUTPUT

too

(TEHIlZ)

--------~H:-::·Z::----~~~-----Jt'---------....,
I-

VOL--------------------------~

Hi-Z
VALID
>----.;.;.;..;;._ _
________________~

Standby Power Down Mode (OE

= VI L)

VIH~~~~~~~~~~~~~------~------------------

ADDRESSES

VALID
VIL========================~~

CHIP ENABLE

VALID
____________________________

VIH --------~r---------------1\
STANDBY
VIL-------I

VOH -

--

VALID FOR
OUTPUT
CURRENT ADDRESS
VOL~==========~

STANDBY

too

(TEHIlZ)
Hi-Z

*Symbols in parentheses are proposed industry standard

5-14

VALID FOR
CURRENT ADDRESS

Hi-Z

PROGRAM OPERATION

DC Electrical Characteristics and Operating Conditions (Notes 1 and 2)
(T A

= 25°C ±5°C)

(VCC

= 5V ±5%, VPP = 25V ±1 V)

SYMBOL

PARAMETER

III

TYP

MIN

Input Leakage Current (Note 3)

VIL

Input Low Level

-0.1

VIH

Input High Level

2.0

ICC

VCC Power Supply Current

MAX

UNITS

10

/lA

0.8

V

VCC+ 1

V

100

rnA

IPPl

VPP Supply Current (Note 4)

5

rnA

IPP2

VPP Supply Current During

30

rnA

Programming Pulse (Note 5)

AC Characteristics and Operating Conditions (Notes 1, 2, and 6)
(T A

= 25°C ±5°C)

(VCC

= 5V ±5%, VPP = 25V ± 1V)

SYMBOL
ALTERNATE

PARAMETER

STANDARD

MIN

TYP

MAX

UNITS

tAS

TAVPH

Address Setup Time

2

/lS

tos

TGHPH

OE Setup Time

2

/lS

tDS

TDVPH

Data Setup Time

2

/lS

tAH

TPLAX

Address Hold Time

2

/lS

tOH

TPLGX

OE Hold Time

2

/lS

tDH

TPLDX

Data Hold Time

2

tDF

TGHOZ

Chip Disable to Output Float

0

-

/lS

100

ns

120

ns

55

ms

Delay (Note 4)
tCE

TGLOV

Chip Enable to Output Delay (Note 4)

tpw

TPHPL

Program Pulse Width

45

tPR

TPH1PH2

Program Pulse Rise Time

5

ns

tpF

TPL2PL1

Program Pulse Fall Time

5

ns

50

Note 1: vee must be applied at thE' same time or before VPP and removed after or at the same time as VPP. To prevent damage to
the device it must not be inserted into a board with power applied.
Note 2: eare must be taken to prevent overshoot of the VPP supply when switching to +25V.
N~te 3: 0.45V V IN <:: 5.25V.
Note 4: CE/PGM = VIL, VPP = vee + O.6V.
Note 5: VPP = 26V.
Note 6: Transition times:::. 20 ns unless noted otherwise.

s:.

5-15

Timing Diagram *

ADDRESSES

Program Mode

VIH

==+r--------t------"'\

Vil ==;;/-~_--_--+_-----~

DATA

VIH

=======\

Vll===~

EIP

VIH

--'-------~

Vll======~

Functional Description
DEVICE OPERATION
The MM2716 has 3 modes of operation in the normal
system environment. These are shown in Table I.

Standby Mode (Power Down)
The MM2716 may be powered down to the standby
mode by making CE/PGM = VIH. This is independent of
OE and automatically puts the outputs in their Hi·Z
state. The power is reduced to 25% (132 mW max)
of the normal operating power. VCC and, VPP must be
maintained at 5V. Access time at power up remains
either tACC or tCE (see Switching Time Waveforms).

Read Mode
The MM2716 read operation requires that OE = VIL,
CE/PGM = VIL and that addresses AO-A10have been
stabilized. Valid data will appear on the output pins'
after tACC, tOE or tCE times (see Switching Time
Waveforms) depending on which is limiting.
Deselect Mode

PROGRAMMING

The MM2716 is deselected by making OE = VIH. This
mode is independent of CE/PGM and the condition of
the addresses. The outputs are Hi-Z when OE = VIH.
This allows OR-tying 2 or more MM2716's for memory
expansion.

The MM2716 is shipped from National completely
erased. All bits will be at a "1" level (output high)
in this initial state and after any full erasure. Table II
shows the 3 programming modes.

TABLE I. OPERATING MODES (VCC

= VPP = 5V)

PIN NAME/NUMBER
MODE

Read
Deselect

CE/PGM
(E/P)
18

OE
20

9-11,13-17

VIL

VIL

DOUT

VIH

Hi-Z

Don't Care

Hi·Z

Don't Care

Standby

OUTPUTS

(G)

VIH

TABLE II. PROGRAMMING MODES (VCC = 5V)
PIN NAME/NUMBER
MODE

Program

CE/PGM
(E/P)
18

-

OE

VPP

OUTPUTS Q

21

9-11,13-17

(G)

20

Pulsed VI L
to VIH

VIH

25

Program Verify

VIL

VIL

25(5)

Program Inhibit

VIL

VIH

25

'Symbols in parentheses are proposed industry standard

5·16

DIN
DOUT
Hi-Z

Functional Description

(Continued)

Program Mode
The MM2716 is programmed by introducing "O"s into
the desired locations. This is done 8 bits (a byte) at a
time. Any individual address, a sequence of addresses,
or addresses chosen at random may be programmed.
Any or all of the 8 bits associated with an address
location may be programmed with a single program
pulse applied to the chip enable pin. All input voltage
levels, including the program pulse on chip enable are
TTL compatible. The programming sequence 'is:

a unit while inhibiting the program pulse to a unit will
keep it from being programmed and keeping DE = VIH
will put its outputs in the Hi-Z state.

ERASING·
The MM2716 is erased by exposure to high intensity
ultraviolet light through the transparent window. This
exposure discharges the floating gate to its initial state
through induced photo current. It is recommended
that the MM2716 be kept out of direct sunlight_ The
UV content of sunlight may cause a partial erasure
of some bits in a relatively short period of time. Direct
sunlight can also cause temporary functional failure.
Extended exposure to room level fluorescent lighting
will also cause erasure. An opaque coating (paint, tape,
label, etc.) should be placed over the package window
if this product is to be operated under these lighting
conditions.

With VPP = 25V, VCC = 5V, DE = VIH and CE/PGM
= VIL, an address is selected and the desired data
word is applied to the output pins. (VI L = "0" and
VIL = "1" for both address and data.) After the
address and data signals are stable the program pin
is pulsed from V I L to V IH with a pulse width between 45 ms and 55 ms.
Multiple pulses are not needed but will not cause device
damage. No pins should be left open. A high level
(VIH or higher) must not be maintained longer than
tpW(MAX) on the program pin during programming.
MM2716's may be programmed in parallel with the
same data in this mode.
.

An ultraviolet source of 2537 A yielding a total integrated dosage of 15 watt-seconds/cm 2 is required.
This will erase the part in approximately 15 to 20
minutes if a UV lamp with a 12,000 J1W/cm2 power
rating is used. The MM2716 to be erased should be
placed 1 inch away from the lamp and no filters should
be used.

Program Verify Mode
The programming of the MM2716 may be verified
either 1 word at 'a time during the programming (as
shown in the timing diagram) or by reading all of the
words out at the end of the programming sequence.
This can be done with VPP = 25V (or 5V) in either case.

An erasure system should be calibrated periodically.
The distance from lamp to unit should be maintained
at 1 inch. The erasure time is increased by the square
of the distance (if the distance is doubled the erasure
time goes up by a factor of 4). Lamps lose intensity
as they age. Whim a lamp is changed, the distance is
changed, or the lamp is aged, the system should be
checked to make certain full erasure is occurring. Incomplete erasure will cause symptoms that can be
misleading. Programmers, components, and system
designs have been erroneously suspected when incomplete erasure was the basic problem.

Program Inhibit Mode
The program inhibit mode allows programming several
MM2716's simultaneously with different data for each
one by controlling which ones receive the program pulse.
All similar inputs of the MM2716 may be paralleled.
Pulsing the program pin (from VIL to VIH) will program

5-17

MOS EPROMs

~National

PRELIMINARY

~ Semiconductor

MM2716E ,16,384-Bit (2048 x 8) UV Erasable PROM
ExtendedTemperatur~ Range
'
General Description

Features

The MM2716E is a high speed 16k UVerasable and
electrically reprogrammable EPROM ideally suited for
applications where fast turn·around and pattern ex·
perimentation are important requirements.

• -40°C to +85°C
• 2048 x 8 organization
• 550 ITlW max active power, 137.5 mW max standby
power
• Low power during programming
• Access time - 450 ns
• Single 5V ±10% power supply
• Static-no clocks requ ired
• Inputs and outputs TTL compatible during both
read and program modes
• TRI·STATE@J output

The MM2716E is packaged in a 24-pin dual·in-line
package with transparent lid. The transparent lid allows
the user to expose the chip to ultraviolet light to erase
the bit pattern. A new pattern can then be written into
the device by following the programming procedure.
This EPROM is fabricated with the reliable, high volume,
time proven, N-ch,annel silicon gate technology.

Block and Connection Diagrams *
Dual-In-Line Package
+-vPP+SV

+-- vee- 5V

A7
A6

+ - VSS GNO
AS
OATA OUTPUTS (PROGRAM INPUTSI
°0- 0 7100-071

A4

iiEiGl

A3

20

A2

19 AID

Al

18 fE/PGM (E/P)

AD

17 07 (07)

0 0 (00)

16 06(06)

01 (01) 10

15 0S(05)

02 (02) 11

14 04 (04)

VSS

12

13 03(03)

TOPVIEW

Order Number MM2716QE
See NS Package J24CQ
Pin Names

Pin Connection During Read or Program
PIN NAME/NUMBER
MODE

Read
Program

CE/PGM
(E/P)
18

OE
(G)

VPP

VCC

OUTPUTS

20

21

24

9-11,13-17

VIL

VIL

5

5

DOUT

Pulsed VIL
to VIH

VIH

25

5

DIN

*Symbols in parentheses are proposed industry standard

5-18

AO-Al0
00-07 (00-07)
CE/PGM (E'/P)
OE (3)
VPP
VCC
VSS

Address Inputs
Data Outputs
Chip Enable/Program
Output Enable
Read 5V, Program 25V
Power (5V)
Ground

Absolute Maximum Ratings (Note 1)
-SO°C to +100°C
-6SoC to +12SoC

Temperature Under Bias
Storage Temperature
VPP Supply Voltage with Respect
to VSS

All Input or Output Voltages with
Respect to VSS (except VPP)
Power Dissipation
Lead Temperature (Soldering, 10 seconds)

26.SV to -0.3V

6V to -0.3V
1.SW
300°C

READ OPERATION (Note 2)
DC Operating Characteristics
TA

= _4o o e to +85°e, vee = 5V ±10%, vpp = vee ±o.6V
PARAMETER

SYMBOL

= OV, unless otherwise noted.

(Note 3), VSS

MIN

CONDITIONS

= 5.5V

I nput Current

VIN

ILO

Output Leakage Current

VOUT

IPPl

VPP Supply Current

VPP

ICCl

VCC Supply Current (Standby)

CE/PGM

= VIH,

ICC2

VCC Supply Current (Active)

CE/PGM

= OE = VIL

VIL

Input Low Voltage

-0.1

VIH

Input High Voltage

2.0

VOH

Output High Voltage

IOH

= -400 JJ.A

VOL

Output Low Voltage

IOL

= 2.1

AC Characteristics
TA

or VIN

= 5.5V,

TYP

= VIL

III

CE/PGM

UNITS

10

= 5V

= 6.1V
OE

MAX

= VI L

10
57

JJ.A

10

JJ.A

5

mA

25

mA

100

mA

0.8

V
V

VCC + 1

V

2.4

mA

V

0.45

(Note 4)

= -40o e to +85°e, vee = 5V ±10%, VPP = vee ±o.6V

(Note 3), VSS

= OV, unless otherwise noted.

SYMBOL
PARAMETER

CONDITIONS

MIN

MAX

UNITS

450

ns

ALTERNATE STANDARD

--

tACC

TAVOV

Address to Output Delay

CE/PGM

tCE

TELOV

E to Output Delay

OE

tOE

TGLOV

Output Enable to Output Delay

CE/PGM

tDF

TGHOZ

Output Enable High to Output Hi-Z

CE/PGM

= VIL

0

tOH

TAXOX

Address to Output Hold

CE/PGM

= OE = VIL

0

tOD

TEHOZ

E to Output Hi-Z

OE

= OE

= VI L

= VIL
= VIL

= VIL

0

450

ns

120

ns

100

ns
ns

100

ns

Capacitance (Note 5)
T A = 25°e, f = 1 MHz
SYMBOL

PARAMETER

CI

Input Capacitance

VIN = OV

CO

Output Capacitance

VOUT

CONDITIONS

= OV

TYP

MAX

4

6

UNITS
pF

8

12

pF

Note 1: "Absolute Maximum Ratings" are those values' beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation_
N'ote 2: Typical conditions are for operation at: T A = 2So e, vec = SV, VPP = vee, and VSS = OV.
Note 3: VPP may be connected to vec except during program. The ±0.6V tolerance allows a circuit to switch VPP between the read voltage
and the program voltage.
Note 4: Output load: 1 TTL gate and CL = 100 pF. Input rise and fall times:s. 20 ns.
Nota 5: Capacitance is guaranteed by periodic testing.

5-19

Switching Time Waveforms·

Read Cycle (CE/PGM

= VI L)

VIH ~~~~~~------------"'"
VALID
________________________

ADDRESSES

VIL~~~~~~~

VALID

~

tOH
--(TAXQX)-OUTPUT ENABLE
vIL-----------t------~~~-------------------J
1_..
_ -...._l-tDE
tDF
tACC
(TGLQV)
(TGHQZ)--

VOH------------~~-----(~T~A~V~Q~V)~----·~--------~----------.,
Hi·Z

OUTPUT

VOL-------------------------~

VALID
_ _ _ _ _ _ _ _ _ _ ___J

Hi·Z

Read Cycle (DE = VI L)
VIH~~~~~~-------------,

ADDRESSES
VIL~~~QQ~~~

VALID
______________________

VALID
~

tOH
--(TAXQX)-VIH ==~~~~~~~~=\­
CHIP ENABLE
VIL--~------_t--------~--~-------~
' -_ _-I--tCE

...

tACC
(TAVQV)--

too

(TELQV)

(TEHQZ)

VOH----------~~--~~~----~-----------1
OUTPUT

Hi·Z
VALID
V O L - - - - - - - - - - - - - - - - - - - - - - - - - - - x_ _ _ _ _ _ _ _ _ _ _--l

Hi·Z

Standby Power Down Mode (DE = VI L)

ADDRESSES

VIH

----------~r-------------~

CHIP ENABLE

STANDBY

VI L - - - - - - - 1

---

I

too

--(TEHQZ)

VOH==~~~~~=X
OUTPUT

STANDBY

VALID FOR
CURRENT ADORESS

Hi·Z

VOL~~~~~~~

·Symbols in parentheses are proposed industry standard

5-20

VALID FOR
CURRENT ADDRESS

Hi·Z

s:
s:
I\)

PROGRAM OPERATION

........

......

C')

DC Electrical Characteristics and Operating Conditions

m

(Notes 1 and 2)

(TA = 25°C ±5°C) (VCC = 5V ±5%, VPP= 25V ±lV)
MIN

SYMBOL

PARAMETER

III

Input Leakage Current (Note 3)

VIL

Input Low Level

-0.1

VIH

Input High Level

2.0

TYP

MAX

UNITS

10

J.1A

0.8

V

VCC + 1

V

ICC

VCC Power Supply Current

100

rnA

IPPl

VPP Supply Current (Note 4)

5

rnA

VPP Supply Current During

30

rnA

IPP2

Programming Pulse (Note 5)

AC Characteristics and Operating Conditions

(Notes 1, 2, and 6)

(T A' = 25°C ±5°C) (VCC = 5V 15%, VPP = 25V ±lV)
SYMBOL
ALTERNATE

PARAMETER

MIN

TYP

MAX

UNITS

STANDARD
TAVPH

Address Setup Time

2

tos

TGHPH

OE Setup Time

2

J.1S

tDS

TDVPH

Data Setup Time

2

JlS

tAH

TPLAX

Address Hold Time

2

J.1s

tOH

TPLGX

OE Hold Time

2

J.1s

tDH

TPLDX

Data Hold Time

2

tDF

TGHOZ

Chip Disable to Output Float

0

100

ns

tAS

J.1S

J.1S

Delay (Note 4)
tCE

TGLOV

Chip Enable to Output Delay (Note 4)

120

ns

tpw

TPHPL

Program .Pulse Width

45

55

ms

tpR

TPH1PH2

Program Pulse Rise Time

5

ns

tPF

TPL2PLl

Program Pulse Fall Time

5

ns

50

Note 1: vee must be applied at thp same time or before VPP and removed after or at the same time as VPP. To prevent damage to
the device it must not be inserted into a board with power applied.
Note 2: eare must be taken to prevent overshoot of the VPP supply when switching to +25V.
Note 3: 0.45VS VIN .; 5.25V.
Note 4: CE/PGM ~ VIL, VPP ~ vee + 0.6V.
Note 5: VPP ~ 26V.
Note 6: Transition times S 20 ns unless noted otherwise.

5-21

Timing Diagram*
ADDRESSES

Program Mode

VIH=====\,r--------------t--------------,
VIL~~~~_____________+------------~

VIH===~
DATA
VIL;;;;;;;;~~;;;;;;(

VIH

-------+1-

E/P
VIL--

'PF
- (TPllPlll

Functional Description

Note: VPP = 25V

DEVICE OPERATION
The MM27161; has 3 modes of operation in the normal
system environment. These are shown in Table I.

Standby Mode (Power Down)
The MM2716E may be powered down to the standby
mode by making CE/PGM = VIH. This is independent of
OE and automatically puts the outputs in their Hi-Z
state. The power is reduced to 25% (150 mW max)
of the normal operating power. VCC and VPP must
be maintained at 5V. Access time at power up remains
either tACC or tCE (see Switching Time Waveforms).

Read Mode
The MM2716E read operation requires that OE = VIL,
CE/PG M = V I L and that addresses AO-A 10 have been
stabilized. Valid data will appear on the output pins
after tACC, tOE, tCE times (see Switching Time Waveforms) depending on which is limiting.
Deselect Mode

PROGRAMMING
The MM2716E is deselected by making DE = VIH. This
mode is independent of CE/PGM and the condition of
the addresses. The outputs are Hi-Z when OE = VIH.
This allows OR-tying 2 or more MM2716Es for memory
expansion.

The MM2716E is shipped from National completely
erased. All bits will be at a "1" level (output high)
in this initial state and after any full erasure. Table"
shows the 3 programming modes.

TABLE I. OPERATING MODES (VCC = VPP = 5V)
PIN NAME/NUMBER
MODE

CE/PGM
(E'/P)
18

OE
20

9-11,13-17

VIL

VIL

DOUT

Don't Care

VIH

Hi-Z

VIH

Don't Care

Hi-Z

Read
Deselect
Standby

OUTPUTS

(<3)

TABLE II_ PROGRAMMING MODES (VCC = 5V)
PIN NAME/NUMBER
MODE

Program

CE/PGM

OE

(E/PI

(<3)

VPP

18

20

Pulsed VIL
to VIH

VIH

25

21

Program Verify

VIL

VIL

25(5)

Program Inhibit

VIL

VIH

25

*Symbols in parentheses are proposed industry standard

5-22

OUTPUTS

Q

9-11,13-17
DIN
DOUT
Hi-Z

, Functional Description

(Continued)

Program Mode
The MM2716E is programmed by introducing "O"s into
the desired locations. This is done 8 bits (a byte) at a
time. Any individual address, a sequence of addresses,
or addresses chosen at random may be programmed.
Any or all of the 8 bits associated with an address
location may be programmed with a single program
pulse applied to the chip enable pin. All input voltage
levels, including the program pulse on chip·enable are
TTL compatible. The programming sequence is:
With VPP = 25V, VCC = 5V, OE = VIH and CE/PGM
= V I L, an address is selected and the desired data
word is applied to the output pins. (VI L = "0"
and VIH = "1" for both address and data.) After
the address and data signals are stable the program
pin is pulsed from VIL to VIH with a pulse width
between 45 ms and 55 ms.
Multiple pulses are not needed but will not cause device
damage. No pins should be left open. A high level
(VIH or higher) must not be maintained longer than
tPW(MAX) on the program pin during programming.
MM2716Es may be programmed in parallel with the
same data in this mode.
Program Verify Mode
The programming of the MM2716E may be verified
either 1 word at a time during the programming (as
shown in the timing diagram) or by reading all of the
words out at the end of the programming sequence.
This can be done with VPP = 25V (or 5V) in either case.
Program Inhibit Mode
The program inhibit mode allows programming several
MM2716Es simultaneously with different data for each
one by controlling which ones receive the program
pulse. All similar inputs of the MM2716E may be par·
alleled. Pulsing the program pin (from VIL to VIH) will

program a unit while inhibiting the program pulse to a
unit will keep it from being programmed and keeping
OE = VIH will put its outputs in the Hi·Z state.
ERASING
The MM2716E is erased by exposure to high intensity
ultraviolet light through the transparent window. This
exposure discharges the floating gate to its initial state
through induced photo current. It is recommended that .'
the MM2716E be kept out of direct sunlight. The UV
content of sunlight may cause a partial erasure of some
bits in a relatively short period of time. Direct sunlight
(any intense light) can cause temporary functional fail·
ure due to generation of photo current. Extended expo·
sure to room level fluorescent lighting will also cause
erasure. An opaque coating (paint, tape, label, etc.)
should be placed over the package window if this prod·
uct is to be operated under these lighting conditions.
An ultraviolet source of 2537 A yielding a total inte·
grated dosage of 15 watt·seconds/cm 2 is required.
This will erase the part in approximately 15 to 20
minutes if a UV lamp with a 12,000 j.NJlcm 2 power
rating is used. The MM2I16E to be erased should be
placed 1 inch away from the lamp and no filters should
be used.
An erasure system should be calibrated periodically.
The distance from lamp to unit should be maintained
at 1 inch. The erasure time is increased by the square
of the distance (if the distance is doubled the erasure
time goes up by a factor of 4). Lamps lose intensity
as they age. When a lamp is changed, the distance is
changed, or the lamp is aged, the system should be
checked to make certain full erasure is occurring. In·
complete erasure will cause symptoms that can be
misleading. Programmers, components, and system
designs have been erroneously suspected when incom·
plete erasure was the basic problem.

5·23

~National

MOS EPROMs

~ Semiconductor

MM2716M 16,384-Bit (2048 x 8) UV Erasable PROM
Military Temperature Range
General Description

Features

The MM2716M is a high speed 16k UV erasable and
electrically reprogram mabie EPROM ideally suited for
appl ications where fast turn-around and pattern experimentation are important requirements.

• -55°C to +125°C
• 2048 x 8 organization
• 632 mW max active power, 150 mW max standby
power

The MM2716M is packaged in a 24-pin dual-in-line
package with transparent lid. The transparent lid allows
the user to expose the chip to ultraviolet light to erase
the bit pattern. A new pattern can then be written into
the device by following the programming procedure.
This EPROM is fabricated with the reliable, high volume,
time proven, N-channel silicon gate technology.

•

Low power during programming

•
•

Access time - 450 ns
Single 5V ±10% power supply

•
•

Static-no clocks required
Inputs and outputs TTL compatible during both
read and program modes

•

TRI-STATE® output

Block and Connection Diagrams *
Dual-In-Line Package

+-

VPP+sv

+ - vCC+sv
+ - VSS GNO
OATA OUTPUTS (PROGRAM INPUTS)
00-07 (00-07)

A7

24 VCC

A6

23 A8

AS

22 A9

A4

21 VPP

A3

20

lIT (il)

19 AID

Al

18 CElPGM (E/P)

AD

17 07 (07)
16 06(06)

TOP VIEW

Order Number MM2716QM
See NS Package J24CQ
Pin Names

Pin Connection During Read or Program
PIN NAME/NUMBER
MODE

Read
Program

CE/PGM
(E/P)

is

OE
(G)
20

21

24

VIL

VIL

5

5

DOUT

Pulsed VI L
to VIH

VIH

25

5

DIN

VPP

VCC

OUTPUTS
9-11,13-17

·Symbols in parentheses are proposed industry standard

5-24

AO-A10
00-07 (00-07)
CE/PGM (E/P)
OE (G)
VPP
VCC
VSS

Address Inputs
Data Outputs
Chip Enable/Program
Output Enable
Read 5V, Program 25V
Power (5V)
Ground

Absolute Maximum Ratings (Note 1)
-65°C to +125°C
-65°C to +125°C

Temperature Under Bias
Storage Temperature
VPP Supply Voltage with Respect
to VSS

READ OPERATION

All Input or Output Voltages with
Respect to VSS (except VPP)
Power Dissipation
Lead Temperature (Soldering, 10 seconds)

26.5V to -0.3V

6V to -0.3V
1.5W
300°C

(Note 2)

DC Operating Characteristics
TA

= -55°e to +125°e, vee = 5V ±10%, vpp = vee ±O.6V (Note 3), VSS = OV, unless otherwise noted.

SYMBOL

PARAMETER

MIN

CONDITIONS

TYP

MAX

UNITS

III

Input Current

VIN = 5.5V or VIN = VIL

10

ILO

Output Leakage Current

VOUT = 5.5V, CE/PGM = 5V

10

pA

IPPI

VPP Supply Current

VPP = 6.1V

5

mA

ICCI

vee Supply Current

ICC2

VCC Supply Current (Active)

VIL

Input Low Voltage

-0.1

VIH

Input High Voltage

2.0

(Standby)

CE/PGM = VIH, OE = VIL

10

30

mA

CE/PGM = OE = VIL

57

115

mA

VOH

Output High Voltage

10H = -400pA

VOL

Output Low Voltage

10L

AC Characteristics
TA

pA

= 2.1

V

0.8

V

VCC + 1

V

2.4

V

0.45

mA

(Note 4)

= -55°e to +125°e, vee = 5V

±10%, vpp

= vee ±a.6V

(Note 3), VSS

= OV, unless otherwise noted.

SYMBOL
PARAMETER

CONDITIONS

MIN

MAX

UNITS

ALTERNATE STANDARD
tACC

TAVOV

Address to Output Delay

CE/PGM = OE = VI L

450

ns

tCE

TELOV

E to Output Delay

OE = VIL

450

ns

tOE

TGLOV

Output Enable to Output Delay

CE/PGM = VIL

150

ns

tDF

TGHOZ

Output Enable High to Output Hi·Z

CE/PGM

130

ns

tOH

TAXOX

Address to Output Hold

CE/PGM = OE = VIL

0

too

TEHOZ

E to Output Hi·Z

OE = VIL

0

130

ns

Capacitance
T A = 25°e, f

= VIL

0

ns

(Note 5)

= 1 MHz

SYMBOL

PARAMETER

CI

Input Capacitance

CO

Output Capacitance VOUT=OV

CONDITIONS
VIN = OV

TYP

MAX

4

6

UNITS
pF

8

12

pF

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Typical conditions are for operation at: T A = 25° C, VCC = 5V, VPP = VCC, and VSS = OV.
Note 3: VPP may be connected to VCC except during program. The ±0.6V tolerance allows a circuit to switch VPP between the read voltage
and the program voltage.
Nota 4: Output load: 1 TTL gate and CL = 100 pF. Input rise and fall times ~ 20 ns.
Note 5: Capacitance is guaranteed by periodic testing.

5-25

Switching Time Waveforms*

Read Cycle (CE/PGM

= VI L)

VIH~~~~~~~----------------------~

ADDRESSES
VIL~~~~~~~

VALID
________________________

VALID
~

tOH
- - (TAXQX)-OUTPUT ENABLE
VIL----~-----t--------~~----------------~~
1~..
__- -....
Joo_r-tOE
tDF
tACC'
(TGLQV)
(TGHQZ)-VOH~________~~I~~~r_-_-_~~(~T~A~V~QV~)~___Joo~r-----------~------~
Hi.Z
VALID
OUTPUT

Hi·Z

VOL--------------~----------~----------------~

Read Cycle (OE
VIH
AODRESSES
VIL

/'l'~

~

~I

=VIL)

K

VALID

VALID

tOH
--(TAXQX)-VIH

J

\

CHIP ENABLE
VIL

I

.
VOH

tACC
(TAVQV)-----

,

J

Hi·Z

OUTPUT
VOL

tCE
(TELQV)

too
(TEHQZi-VALID

r--~

Hi·Z

1/

Standby Power Down Mode (OE = VI L)

AODRESSES

VIH

------------r-------""1\

VIL

----------#

CHIP ENABLE

--

STANDBY
I

too

-(TEHQZ)

VOH~~~~~~~
OUTPUT

STANDBY

VALID FOR
CURRENT AODRESS

'Hi-Z

VOL~~~~~~~

*Symbols in parentheses are proposed industry standard

5-26

VALID FOR
CURRENT ADDRESS

Hi·Z

PROGRAM OPERATION

DC Electrical Characteristics and Operating Conditions (Notes
(T A

= 25°C ±5°C)

(VCC

SYMBOL

MIN

PARAMETER

TYP

MAX

UNITS

10

pA

0.8

V

VCC + 1

V

VCC Power Supply Current

100

mA

VPP Supply Current (Note 4)

5

mA

VPP Supply Current During

30

mA

III

Input Leakage Current (Note 3)

VIL

Input Low Level

-0.1

VIH

Input High Level

2.0

ICC
IPPl
IPP2

1 and 2)

= 5V ±5%, VPP = 25V ±lV)

Programming Pulse (Note 5)

AC Characteristics and Operating Conditions (Notes
(TA

= 25°C ±5°C)

(VCC

SYMBOL
ALTERNATE
tAS

1,2, and 6)

= 5V 15%, VPP = 25V ±lV)
PARAMETER

MIN

TYP

MAX

UNITS

STANDARD
TAVPH

Address Setup Time

2

ps

tos

TGHPH

OE Setup Time

2

ps

tDS

TDVPH

Data Setup Time

2

ps

tAH

TPLAX

Address Hold Time

2

ps

tOH

TPLGX

OE Hold Time

2

ps

tDH

TPLDX

Data Hold Time

2

ps

tDF

TGHOZ

Chip Disable to Output Float

0

130

ns

Delay (Note 4)
tCE

TGLOV

Chip Enable to Output Delay (Note 4)

tpw

TPHPL

Program Pulse Width

tpR

TPH1PH2

Program Pulse Rise Time

5

ns

tpF

TPL2PL 1

Program Pulse Fall Time

5

ns

45

50

150

ns

55

ms

Note 1: vee must be applied at thE' same time or before VPP and removed after or at the same time as VPP. To prevent damage to
the device it must not be inserted into a board with power applied.
Note 2: eare must be taken to prevent overshoot of the VPP supply when switching to +25V.
Note 3: 0.45V~ VIN:S: 5.25V.
Note 4: CE/PGM = VIL. VPP = vee + 0.6V.
Note 5: VPP = 26V.
Note 6: Transition times :S: 20 ns unless noted otherwise.

5·27

Timing Diagram *

Program Mode

VIH

=====\-r-------t-------,

VIL

;;;;;;;;;;;;;;=f"1--------+-______~

ADDRESSES

VIH ::::::::::::~
DATA
VIL;;;;;;;;;;;:;;;;:;;;;{

GVIH------Jr---1--1--(T-PL~18:~)-~-t--t-~

(T~~~H)

VIL

--lOS
-(TGHPH)-

IpW
(TPHPl)

VIH

--------------+--1'-

VIL

;;;;;;;;;;;;;;====;:Jf

E/P

IpF
(TPL1PL1)

Functional Description

Note: Vpp = 25V

DEVICE OPERATION
The MM2716M has 3 modes of operation in the normal
system environment. These are shown in Table I.

Standby Mode (Power Down)
The MM2716M may be powered down to the standby
mode by making CE/PGM = VIH. This is independent of
.OE and automatically puts the outputs in their Hi-Z
state. The power is reduced to 25% (150 mW max)
of the normal operating power. VCC and VPP must
be maintained at 5V. Access time at power up remains
either tACC or tCE (see Switching Time Waveforms).

Read Mode
The MM2716M read operation requires that OE = VI L,
CE/PGM = VI L and that addresses AO-A 10 have been
stabilized. Valid data will appear on the output pins
after tACC, tOE, tCE times (see Switching Time Waveforms) depending on which is limiting.
Deselect Mode

PROGRAMMI~G

The MM2716M is deselected by making OE = VIH. This
mode is independent of CE/PGM and the condition of
the addresses. The outputs are Hi-Z when OE = VIH.
This allows OR-tying 2 or more MM2716M's for memory expansion.

The MM2716M is shipped from National completely
erased. All bits will be at a "1" level (output high)
in this initial state and after any full erasure. Table II
shows the 3 programming modes.

TABLE I. OPERATING MODES (VCC = VPP

= 5V)

PIN NAME/NUMBER
MODE

Read
Deselect

CE/PGM
(E/P)
18

OE
(0)
20

9-11,13-17

VIL

VIL

DOUT

VIH

Hi-Z

Don't Care

Hi-Z

Don't Care

Standby

VIH

OUTPUTS

TABLE II. PROGRAMMING MODES (VCC = 5V)
PIN NAME/NUMBER
MODE

Program

CE/PGM
(E/P)
18

OE
(0)
20

Pulsed VIL
to VIH

VIH

25

VPP

OUTPUTS Q

21

9-11,13-17

Program Verify

VIL

VIL

25(5)

Program Inhibit

VIL

VIH

25

*Symbols in parentheses are proposed industry standard

5-28

DIN
DOUT
Hi-Z

Functional Description

(Continued)

Program Mode
The MM2716M is programmed by introducing "O"s into
the desired locations. This is done 8 bits (a byte) at a
time. Any individual address, a sequence of addresses,
or addresses chosen at random may be programmed.
Any or all of the 8 bits associated with an address
location may be programmed with a single program
pulse applied to the chip enable pin. All input voltage
levels, including the program pulse on chip·enable are
TTL compatible. The programming sequence is:

program a unit while inhibiting the program pulse to a
unit will keep it from being programmed and keeping
DE = VIH will put its outputs in the Hi-Z state.
ERASING
The MM2716M is erased by exposure to high intensity
ultraviolet light through the transparent window. This
exposure discharges the floating gate to its initial state
through induced photo current. It is recommended
that the MM2716M be kept out of direct sunlight. The
UV content of sunlight may cause a partial erasure
of some bits in a relatively short period of time. Direct
sunlight can also cause temporary functional failure.
Extended exposure to room level fluorescent lighting
will also cause erasure. An opaque coating (paint, tape,
label, etc.) should be placed over the package window
if this product is to be operated under these lighting
conditions.

With VPP = 25V, VCC = 5V, DE = VIH and CE/PGM
= V I L, an address is selected and the desired data
word is applied to the output pins. (VI L = "0"
and VIH = "1" for both address and data.) After
the address and data signals are stable the program
pin is pulsed from VIL to VIH with a pulse width
between 45 ms and 55 ms.
.
Multiple pulses are not needed but will not cause device
damage. No pins should be left open. A high level
(VIH or higher) must not be maintained longer than
tpW(MAX) on the program pin during programming.
MM2716M's may be programmed in parallel with the
same data in this mode.

An ultraviolet source of 2537 A yielding a total inte·
grated dosage of 15 watt-seconds/cm 2 is required.
This will erase the part in approximately 15 to 20
minutes if a UV lamp with a 12,000 J1W/cm2 power
rating is used. The MM2716M to be erased should be
placed 1 inch away from the lamp and no filters should
be used.

Program Verify Mode
The programming of the MM2716M may be verified
either 1 word at a time during the programming (as
shown in the timing diagram) or by reading all of the
words out at the end of the programming sequence.
This can be done with VPP = 25V (or 5V) in either case.

An erasure system should be calibrated periodically.
The distance from lamp to unit should be maintained
at 1 inch. The erasure time is increased by the square
of the distance (if the distance is doubled the erasure
time goes up by a factor of 4). Lamps lose intensity
as they age. When a lamp is changed, the distance is
changed, or the lamp is aged, the system should be
checked to make certain full erasure is occurring. Incomplete erasure will cause symptoms that can be
misleading. Programmers, components, and system
designs have been erroneously suspected when incomplete erasure was the basic problem.

Program Inhibit Mode
The program inhibit mode allows programming several
MM2716M's simultaneously with different data for each
one by controlling which ones receive the program
pUlse. All similar inputs of the MM2716M may be par·
alleled. Pulsing the program pin (from VIL to VIH) will

5-29

~National

MOS EPROMs

D Semiconductor
MM2758 8192·Bit (1024 x 8) UV Erasable PROM
General Description

Features

The MM2758 is a high speed 8k UV erasable and electrically reprogrammable EPROM ideally suited for
appl ications where fast turn-around and pattern experimentation are important requirements.

•

1024 x 8 organization

•

525 mW max active power, 132 mW max standby
power

The MM2758 is packaged in a 24-pin dual-in-line package with transparent lid. The transparent lid allows
the user to expose the chip to ultraviolet light to erase
the bit pattern. A new pattern can then be written into
the device by following the programming procedure ..
This EPROM is fabricated with the reliable:high volume,
time proven, N-channel silicon gate technology_

•

Low power during programming.

•

Access time-450 ns

•
•
•

Single 5V power supply
Static-no clocks required
Inputs and outputs TTL compatible during both
read and program modes

•

TRI-STATE® output

Block and Connection Diagrams *
Dual-In-Line Package

+-- VPP+5V

A7

+-+--

A6

VCC+5V
VSS GND

A5
DATA OUTPUTS (PROGRAM INPUTS)
00-07 (UO-07)

A4
A3
A2
18 CElPGM (E/P)
17 07(U7)
16 06 (U6)
15 05(U5)
14 04 (U4)

02 (U2) 11
VSS

12

Pin Connection During Read or Program

Order Number MM2758AO
or MM2758BO
See NS Package J24CO

PIN NAME/NUMBER
MODE

Read
Program

CE/PGM
fE/PI
18

OE

VIL
Pulsed VIL
to VIH

(G)

VPP

VCC

OUTPUTS

20

21

24

9-11,13-17

VIL

5

5

VIH

25

5

13 03 (U3)

TOPVIEW

DOUT
DIN

*Symbols in parentheses are proposed industry standard
tFor MM2758A AR = VIL for all operating modes
For MM27588 AR = VIH for all operating modes

5-30

Pin Names
AO-A10

00-07 (00-07)
CE/PGM (E/P)
OE (<3)
VPP
VCC
VSS

Address Inputs
Data Outputs '
Chip Enable/Program
Output Enable
Read 5V, Program 25V
Power (5V)
Ground

Absolute Maximum Ratings

All Input or Output Voltages with
Respect to VSS (except VPP)
Power Dissipation
Lead Temperature (Soldering, 10 seconds)

-25°C to +85°C
--65°C to +125°C

Temperature Under Bias
Storage Temperature
VPP Supply Voltage with Respect
to VSS

READ OPERATION

(Note 1)

26.5V to -0.3V

6V to -0.3V
1.5W
300°C

(Note 2)

DC Operating Characteristics
oOe to +7oo e, vee = 5V ±5%,
vpp = vee ±O.6V (Note 3), VSS = OV,

TA =

unless otherwise noted.

PARAMETER

SYMBOL

CONDITIONS

MIN

Input Current

VIN

ILO

Output Leakage Current

VOUT

= 5.25V.

IPPl

VPP Supply Current

VPP

5.85V

ICCl

VCC Supply Current (Standby)

CE/PGM

ICC2

VCC Supply Current (Active)

VIL

Input Low Voltage

0.1

VIH

Input High Voltage

2.0

VOH

Output High Voltage

IOH

=

VOL

Output Low Voltage

IOL

=

AC Characteristics

TYP

MAX

= 5 25V or VIN = VIL

III

=

CE/PGM

VIH. DE

=

=

=

UNITS

10
5V

VIL

400 f.1A

f.1A

10

f.1A

5

rnA

10

25

rnA

57

.100

III A

0.8
Vee

V
+

1

V

2.4

V

2.1 mA

0.45

V

(Note 4)

oOe to +7oo e, vee = 5V ±5%,
vpp = vee iO.6V (Note 3), VSS = OV,

TA =

SYMBOL

unless otherwise noted.
MM2758

CONDITIONS

PARAMETER

MIN

ALTERNATE STANDARD

UNITS

MAX

tACC

TAVOV

Address to Output Delay

CE/PGM = OE = VI L

450

ns

tCE

TELOV

CE to Output Delay

'OE=VIL

450

ns

tOE

TGLOV

Output Enable to Output Delay

CE/PGM = VIL

120

ns

tDF

TGHOZ

Output Enable High to Output Hi·Z·

CE/PGM = VIL

0

100

ns

tOH

TAXOX

Address to Output Hold

CE/PGM = OE = VIL

0

TEHOZ

CE to Output Hi·Z

OE = VIL

0

tOD

Capacitance

ns
100

ns

(Note 5)

T A = 25°e, f = 1 MHz
SYMBOL

PARAMETER

CI

Input Capacitance

CONDITIONS
VIN = OV

CO

Output Capacitance

VOUT = OV

TYP

MAX

4

6

UNITS
pF

12

pF

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Typical conditions are for operation at: T A = 25°C, VCC = 5V, VPP = VCC, and VSS = OV.
Note 3: VPP may be connected to VCC except during program. The ±0.6V tolerance allows a circuit to switch VPP between the read voltage
and the program voltage.
Note 4: Output load: 1 TTL gate and CL = 100 pF. Input rise and fall times::; 20 ns.
Note 5: Capacitance is guaranteed by periodic testing.

5·31

co

;e
C\I

Switching Time Waveforms *

:E
:E
Read Cycle (CE/PGM = VI L)
VIHh4~~~~~'-------------------------~

VALID
~

VALID
________________________

~

~

~

~

~

~

L

I

V

ADDRESSES

tOH
--(TAXUX)-OUTPUT ENABLE

VIH

=====~====\.

vIL-----------t--------~~-------------------I

1_..
_ -...
~_l-tOE
tOF
tACC
(TGLQV)
(TGHQZ)--_ __________~~..
·~~-~-----~(T~A~V~Q~V)~---~_J~------------------~
VOH
Hi.Z
VALID
OUTPUT
VDL------~------------------'_________________J

Read Cycle (OE

Hi·Z

= VI L)

VIH~~~~~~------------------------~

VIH

VALID
________________________

VALID
~

~

~

~

~

~

~

L

I

V

ADDRESSES

========t:=======\.

CHIP ENABLE
VIL-----------t--------~----~-------------J

' -____-I--tCE
tACC
(TELQV)
(TAVQV)--

too

(TEHQZ)

VOH----------~~--~~~----i_------~--------1
OUTPUT

Hi·Z
VOL--------------------------~

VALID
__________________J

Hi·Z

Standby Power Down Mode (OE = VI L)
VIH~~~~~~~~~~~~~------~------------------

ADDRESSES

VALID
VIL======================~~~

VIH

VALID
__________________________

--------------,,-------------1\

CHIP ENABLE
VIL - - - - - - - 1

STANDBY

STANDBY

too

(TEHQZ)

VOH=============\
VALID FOR
OUTPUT

CURRENT ADDRESS

VDL~~~~~~~#

*Symbols in parentheses are proposed industry standard

Hi·Z

VALID FOR
CURRENT ADDRESS

Hi·Z

PROGRAM OPERATION

DC Electrical Characteristics and Operating Conditions (Notes 1 and 2)
(T A = 25°C ±5°C) (VCC = 5V ±5%, VPP = 25V ±lV)
SYMBOL

TYP

MIN

PARAMETER

III

Input Leakage Current (Note 3)

VIL

I nput Low Level

-0.1

VIH

Input High Level

2.0

ICC

VCC Power Supply Current

IPPl
IPP2

MAX

UNITS

10

pA

0.8

V

VCC+ 1

V

100

mA

VPP Supply Current (Note 4)

5

mA

VPP Supply Current During

30

mA

Programming Pulse (Note 5)

AC Characteristics and Operating Conditions (Notes 1,2, and 6)
(T A = 25°C ±5°C) (VCC = 5V ±5%, VPP = 25V ±lV)

SYMBOL
ALTERNATE

PARAMETER

STANDARD

MIN

TYP

MAX

UNITS

ps

TAVPH

Address Setup Time

tos

TGHPH

OE Setup Time

2

ps

tDS

TDVPH

Data Setup Time

2

ps

tAH

TPLAX

Address Hold Time

tOH

TPLGX

OE Hold Time

tDH

TPLDX

Data Hold Time

2

tDF

TGHOZ

Chip Disable to Output Float

0

tAS

2

2

ps

2

ps

-

ps
100

ns

120

ns

55

ms

Delay (Note 4)
tCE

TGLOV

Chip Enable to Output Delay (Note 4)

tpw

TPHPL

Program Pulse Width

45

tpR

TPH1PH2

Program Pulse Rise Time

5

ns

TPL2PL 1

Program Pulse Fall Time

5

ns

tPF

50

Note 1: vee must be applied at thl' same time or before VPP and removed after or at the same time as VPP. To prevent damage to
the device it must not be inserted into a board with power applied.
Note 2: eare must be taken to prevent overshoot of the VPP supply when switching to +25V.
Note 3: 0.45V~ VIN S 5.25V.
Note 4: CE/PGM = VI L, VPP = vee + 0.6V.
Note 5: VPP = 26V.
Note 6: Transition times ~ 20 ns unless noted otherwise.

5-33

Timing Diagram *

Program Mode

VIH

=====\-r------t------,

Vll

==;;;;t-"1--------+------~

ADDRESSES

VIH :::::::::~
DATA
Vll====;f

Ii VIH
Vll

VIH

E/P

--------t+

Vll======;;;;;1\"

Functional Description
DEVICE OPERATION
The MM2758 has 3 modes of operation in the normal
system environment. These are shown in Table I.

Standby Mode (Power Down)
The MM2758 may be powered down to the standby
mode by making CE/PGM = VIH. This is independent of
OE and automatically puts the outputs in their Hi·Z
state. The power is reduced to 25% (132 mW max)
of the normal operating power. VCC and VPP must be
maintained at 5V. Access time at- power up remains
either tACC or tCE (see Switching Time Wave~orms).

Read Mode
The MM2758 read operation requires that OE = VI L,
CE/PGM = VIL and that addresses AO-A10 have been
stabilized. Valid data will appear on the output pins
after tACC, tOE or tCE times (see Switching Time
Waveforms) depending on which is limiting.
Deselect Mode

PROGRAMMING
The MM2758 is shipped from National completely
erased. All bits will be at a "1" level (output high)
in this initial state and after any full erasure. Table II
shows the 3 programming modes.

The MM2758 is deselected by making OE = VIH. This
mode is independent of CE/PGM and the condition of
the addresses. The outputs are Hi-Z when OE = VIH.
This allows OR-tying 2 or more MM2716's for memory
expansion.

TABLE I. OPERATING MODES (VCC

= VPP = 5V)

PIN NAME/NUMBER
MODE

Read
Deselect
Standby

CE/PGM
(E/P)
18

OE

OUTPUTS

20

9-11,13-17

VIL

VIL

DOUT

VIH

Hi-Z

Don't Care

Hi-Z

(<3)

Don't Care
VIH

TABLE II. PROGRAMMING MODES (VCC

= 5V)

PIN NAME/NUMBER
CE/PGM
(Em
18

OE

Pulsed VI L
to VIH

VIH

Program Verify

VIL

VIL

25(5)

Program Inhibit

VIL

VIH

25

MODE

Program

*Symbols in parentheses are proposed industry standard

5-34

VPP

OUTPUTS

Q

(<3)

20

21
25

9-11,13-17
DIN
DOUT
Hi-Z

Functional Description

(Continued)

Program Mode
a unit while inhibiting the program pulse to a unit will
keep it from being programmed and keeping DE = VIH
will put its outputs in the Hi-Z state.

The MM2758 is programmed by introducing "O"s into
the desired locations. This is done 8 bits (a byte) at a
time. Any individual address, a sequence of addresses,
or addresses chosen at random may be programmed.
Any or all of the 8 bits associated with an address
location may be programmed with a single program
pulse applied to the chip enable pin. All input voltage
levels, including the program pulse on chip enable are
TTL compatible. The programming sequence is:

ERASING
The MM2758 is erased by exposure to high intensity
ultraviolet light through the transparent window. This
exposure discharges the floating gate to its initial state
through induced photo current. It is recommended
that the MM2758 be kept out of direct sunlight. The
UV content of sunlight may cause a partial erasure
of some bits in a relatively short period of time. Direct
sunlight can also cause temporary functional failure.
Extended exposure to room level fluorescent lighting
will also cause erasure. An opaque coating (paint, tape,
label, etc.) should be placed over the package window
if this product is used under these lighting conditions.

With VPP = 25V, VCC = 5V, ()E = VIH and CE/PGM
= VIL, an address is selected and the desired data
word is appl ied to the output pins. (V I L = "0" and
VIL = "1" for both address and data.) After the
address and data signals are stable the program pin
is pulsed from VIL to VIH with a pulse width between 45 ms and 55 ms.

-

Multiple pulses are not needed but will not cause device
damage. No pins should be left open. A high level
(VIH or higher) must not be maintained longer than
tPW(MAX) on the program pin during programming.
MM2758's may be programmed in parallel with the
same data in this mode.

An ultraviolet source of 2537 A yielding a total integrated dosage of 15 watt-seconds/cm 2 is required.
This will erase the part in approximately 15 to 20
minutes if a UV lamp with a 12,000 pW/cm 2 power
rating is used. The MM2758 to be erased should be
placed 1 inch away from the lamp and no filters should
be used.

Program Verify Mode
The programming of the MM2758 may be verified
either 1 word at a time during the programming (as
shown in the timing diagram) or by reading all of the
words out at the end of the programming sequence.
This can be done with VPP = 25V (or 5V) in either case.

An erasure system should be calibrated periodically.
The distance from lamp to unit should be maintained
at 1 inch. The erasure time is increased by the square
of the distance (if the distance is doubled the erasure
time goes up by a factor of 4). Lamps lose intensity
as they age. When a lamp is changed, the distance is
changed, or the lamp is aged, the system should be
checked to make certain full erasure is occurring. Incomplete erasure will cause symptoms that can be
misleading. Programmers, components, and system
designs have been erroneously suspected when incomplete erasure was the basic problem.

Program Inhibit Mode
The program inhibit mode allows programming reveral
MM2758s' simultaneously with different data for each
one by controlling which ones receive the program pulse.
All similar inputs of the MM2758 may be paralleled.
Pulsing the program pin (from VIL to VIH) will program

5-35

~National

MOSEPROMs

D Semiconductor
MM4203/MM5203 2048·Bit (256 x 8 or 512 x 4)
UV Erasable PROM
General Description
The MM4203/rylM5203 is a 2048-bit static readonly memory which is electrically programmable
and uses silicon gate technology to achieve bipolar
compatibility_ The device is a non-volatile memory
organized as a 256-8-bit words or 512-4-bit words_
Programming of the memory contents is accomplished by storing a charge in a cell location by
programming that location with a 50 volt pulse_
Separate output supply lead is provided to reduce
internal power dissipation in the output stage
(VLd-

•

Pin compatible with MM5213, MM5231 mask
programmable ROMs
• Static operation - no clocks required
• Common data busing (TRI-STATE@output)
• "0" quartz lid version erasable with short wave
ultra-violet light (i.e_ 253.7 n.m_)
• Chip select output control
• 256 x 8 or 512 x 4 organization

Applications
• Code conversion
• Random logic synthesis
• Table look-up
• Character generator
• Micro-programming

Features
•
•
•

Field programmable
Bipolar compatibility
High speed operation

+5V, -12V operation
1J1s max access time

Block and Connection Diagrams

Dual-In-Line Package
A31

Z4V LL

.,

Z

ZlV..

B,

•

II ..

.,
.. .

" ..

B,II

I.ES

Vsslt

13

I,

,

,

I.

" ..

,

I, •

11 VDO

At MSI

Order Number MM42030 or MM52030
See NS Package J24CO

Typical Applications
256 x 8 PROM Showing TTL Interface

fA,

Operating Modes

tSEL~

1.

256.8 ROM connection (shown)
Mode Control - HIGH (Vssl
Ag
- LOW

512.4 ROM connections
A,

17

At

..

Mode Control - LOW (GNO or VOOI
Ag
- Logic HIGH enables the odd (61. 83 .. 871 outputs
- Logic LOW enables the even (82. 84· Sa) outputs
The outputs are enabled when a logic LOW is applied to
the Chip Select line.
Programming is accomplished in 256.

,

"

1
5-36

a mode only.

Absolute Maximum Ratings

Operating Conditions

All Input or Output Voltages with
+.3V to -20V
Respect to Vaa Except During Programming
Power Dissipation
lW
-65°C to 125°C
Storage Temperature Range
300°C
Lead Temperature (Soldering, 10 sec)

Operating Temperature Range MM4203
MM5203

Electrical Characteristics
Vss = +5V ±5%, V DD
SYMBOL

= V LL = -12V,

-55°C to 85°C
O°C to 70°C

T A within operating temperature range,

±5%, Vss = PROGRAM = Vss unless otherwise noted.

PARAMETER

MIN

CONDITIONS

MAX

TYP

UNITS

III

Input Current

VIN = OV

I LO

Output Leakage

V OUT = OV

Iss

Power Supply Current

T A = 25°C CS = Vss - 2.0

V IL

Input LOW Voltage

Vss - 10

Vss - 4.0

V

V 1H

Input HIGH Voltage

Vss - 2.0

Vss +.3

V

VOL

Output LOW Voltage

1.6 mA sink -12.6V

ICF

Output Clamp Current

V LL = -3.0V V OUT = -1.0V (Note 8) T A = O°C
V LL = -12.6V V OUT = -1.0V (Note 8) T A = O°C

V OH

Output HIGH Voltage

0.8 mA source

TOH

Data Hold Time

(Min Access Time) Figures 1 & 2

CS = Vss

- 2.0
35

1

/lA

1

/lA
mA

55

< V LL < -3V

V

.40
6.0
15.0

3.5
8.0

mA
mA
V

2.4

= 25°C Figures

100

ns

1

/lS

T Acc

Access Time

TA

Tco

Chip Select Time

Figures 1 & 3

500

ns

Too

Chip Deselect Time

Figures 1 & 3

500

ns

tcs

Allowable Chip Select Delay

Figures 1 & 2
Allowable delay in selecting chip after change
of address without affecting access time.

100

ns

C IN

Input Capacitance

COUT

Output Capacitance

= Vss }
= Vss
Cs = Vs~ - 2.0
VIN

= 25°C,

Vss = OV, Vss = +12V ±10%,

SYMBOL

= 1.0 MHz

.700

(Note 2)

V OUT

Programming Characteristics
TA

f

1 & 2 (Note 6)

8

15

pF

8

15

pF

(see Figure 4)

Cs = OV unless otherwise noted

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS
mA

I LO

Address and Data Input Load Current

VIN =-50V

0

10

I LP

Program Load Current

VIN =-50V

0

10

mA

I LS

Vaa Supply Load Current

0

10

mA

I LOD

Peak

V 1HP

Input High Voltage

V 1LP

Address and Data Input Low Voltage

100

Supply Load Current (Note 3)

Voo

= Vprogram = -50V

Pulsed Input Low Voltage:
V oo , and Program, V OLP
V LL

(Note 5)

+.3

V

-50

-40

V

-50
-50

-48
0

V
V

Voo Pulse Duty Cycle
tpw

Program Pulse Width (Note 4)

Voo = Vprogram

mA

650
-2

= -50V

2

%

20

ms

tow

Data and Address Set Up Time

1

/lS

tOH

Data and Address Hold Time,

0

/ls

tss

Pulsed Voo Supply Overlap,

1

tSH

Pulsed Voo Supply Overlap,

-.1

V oo , Program, Address, and Input Rise
and Fall Times

Note 1: During programming. data is always applied in the 256 x 8 mode, regardless of the logic state of Ag and MODE
CONTROL.
Note 2: Capacitances are not tested on a production basis but are periodically sampled.
Note 3: lOOp flows only during program period tpWP. Average power supply current I LDD is typically 15 rnA at 2% duty cycle.
Note 4: Maximum duty cycle of tpw should not be greater than 2% of cycle time so that power dissipation is minimized. The
program cycle should be repeated until the data reads true, then over-program three times that number of cycles (symbolized
as X+3X programming.
Note 5: VlL is not needed during programming but may be tied to VOO for convenience.
Note 6: TACC '" 1000 ns + 2S(N-11 where N is the number of chips wired-OR together.
Note 7: Measured under continuous operation.
Note 8: ICF flows out the VlL pin, it does not flow out the VOO pin.

5·37

100

/ls

3

ms

1

/ls

Access Time Diagrams
+5.0V ±5%

INPUT

-12V±5%
Figure 1

ADDRESS

)C

~

• '"'.- - - - - - - - - - - - - - - -

CS

_----t--,.T
CHIP SELECT

r-

I

VSS-2.0V
Vss-4.0V

Vss - 2.0V
---

TOH

--

Vss - 4.0V

'"'__D_~_T:_L_~~_T

"fm.."~.."..",..N-D~-;-e-~-L~-~or,,.~I/~!"!~/!..,,II..,,II..,,~""~I

H----..,_mr,"
DATA OUT

I..

..I: ~~~~L~6

__

TACC
Figure 2

H-------..\

;r------VSS-2.OV

CHIP SELECT

Vss - 4.0V

~_ _ _ _ _ _ _- . J

H~""""~~~~""~~

DATA OUT

________

~~""~~~~~~

DATA VALID

Figure 3

Program Waveforms
ADDRESS&
DATA INPUTS

~~

W)~

~
VOD

INPUT STABLE

-I
~'-I---~l""'~-+-

1T'J,.,.,,.,,,.....------V

J

L-VDLP
1HP

b-tPW---'1-+---:::.
Figure 4

5·38

Operation of the MM4203/MM5203 in Program Mode
1-8 are pins 4-11 respectively regardless of the
logic state of Ag and mode control. Chip select
should be disabled (HIGH).

Initially, all 2048 bits of the MM4203/MM5203
are in the HIGH state. Information is introduced
by selectively programming LOWS in the proper
bit locations. (Note 1)

Positive logic is used during the read mode for
addresses and data out. Address 0 corresponds to
all address inputs at V I L and address 255 10 corresponds to all address inputs at V IH . A "1" or a
P at a data output corresponds to V0 H. A "0" or
an N at a data output corresponds to VOL' Positive logic is also used during the programming mode
for addresses. Address 0 corresponds to all address
inputs at V ILP and address 255 10 corresponds to
all address inputs at V 1HP .

Word address selection is done by the same de.:oding circuitry used in the Read mode. The eight
output terminals are used as data inputs to determine the information pattern in the eight bits of
each word. A LOW data input level (-50V) will
leave a HIGH and a HIGH data input level will
allow programming of a LOW. All eight bits of one
word are programmed simultaneously by setting
the desired bit information patterns on the data
input terminals. The duty cycle of the V DD pulse
(amplitude and width as specified on page 4)
should be limited to 2%. The address should be
applied for at least 1 ps before application of the
Program pulse. In programming mode, data inputs

Negative logic is used during the programming mode
for data in. A "1" or a P at a data input corresponds to V ILP . A "0" or an N at a data input
corresponds to V IHP .

DATA AND ADDRESS LINES
MDDE

Vss

Vas

HIGH

LOW

Read

Vss - 2.0

Vss - 4.0

+5

Vss

Program

Vss -2.0

Vss - 40

GND

+12

PROGRAM

Cs

VLL

-12

Vss

Vss - 4V

-3V lo-12V

-48
(Pulse)

-48
(Pulse)

GND

GND 10 -50 V

Voo

Erasing Procedure
minutes. Examples of UV sources include the
Model UVS-54 and Model S-2 manufactured by
Ultra-Violet Products, Inc. (5114 Walnut Grove
Avenue, San Gabriel, California). The lamps
should be used without short·wave filters. The
MM4203/MM5203 should be placed about one
inch away from the lamp for about 20-30
minutes.

The MM42030/MM52030 may be erased by
exposure to short-wave ultraviolet Iight-253_7 nm_
There exists no absolute rule for erasing time or
distance from source. The erasing equipment
output capability should be calibrated. Establish a
,worst-case time required with the equipment.
Then over-erase by a f~ctor of 2, i.e., if the device
appears erased after 8 minutes, continue exposure
for an additional 16 minutes for a total of 24

Preferred Tape Format
The custom patterns may be sent in on a Telex or
submitted as a paper tape in a 7 bit ASCII code

Start Character - - , Stop Character ---,
Leader: Rubout for

T~~ 1~~el:I(~e; I~:S~

,

.,

r;

I

from model 33 teletype or TWX. The paper tape
should be as the following example:

Carriage return line feed
allowed between F and B.
Data Field'

MSB (Pin 11)

LSB (Pin 4)

Itt

B P P P N P P N N F B N N P P N N P P F ... B N P N P N N N N F

25 frames.)

Trailer: Rubout for

~~I~~li~:~~:~Y
25 frames.)

Word 0

Word 1

All Address Inputs LOW

Word 255

All Address Inputs HIGH

·Data Field: Must have only P's or N's typed between Band F. No nulls or rubouts. Must have exactly eight P and N
characters between Band F. Any characters except Band F may be typed between the F stop character and the B start
character. If an error is made in preparing a tape the entire word including the Band F start and stop characters must
be rubbed out. Data for exactly 256 words must be entered, beginning with word O.

5-39

Alternate Format

[Punched Tape (Note 1) or Cards]

b8. MSB (Pin 11)

d

MM4203
Positive Logic
2

b l • LSB (Pin 4)

Spaces --+---A-O-OO-'~ onoooooo 0
AOO I
.~on~

Note 3
Note 1: The code is a 7-bit ASCII code on 8 punch tape. The tape
should begin and end with 25 or more "RUBOUT" punches .
Note 2: The ROM input address is expressed in decimal form and is
preceded by the leiter A.

OOOOO(l()'; ~
oonrJOOo~ ~
____

~~~~ ~~7:~:;1: ~

1--1 Space

Ano:,

00011100;1
ooooooon 0
00111100.
AOOR
00'100000 G
A:'II
OIGIOIOI.
TBR 1.0
T87 150
TB6 2"50
TRS .00
TS. 010
TA3 100
TB2 299
TBI 197

Nota 3: The total number of "1" bits in the output word.
Note 4: The total number of "1" bits in each output column or bit
position.

A006

AnO"

Note 4

t

1 Space

Typical Performance Characteristics

Maximum Access Time IT ACC)
as a Function of VOO Supply
Voltage

Maximum Supply Current ISS
as a Functi~n of Temperature
90 r-r--r--r-T-r,.......,....,...-r-r-T""'-"""""-'
80

~++4-~~I+4_I~~I(N~ot.~7~)

70
60
"'

50

~

40

~

t--t--t--t--t--lt- Vss = +4.75V1600

~~~ ~~5HUP~L~±lli
~r--t~~.

l/NOMSUPPLY

~

~1300

30 ~-+-+-t-r--t--1---t--+-~+~--l

1zoo

20

1100

10

1OOQ

o
0

25

50

=

Veo

-

1400 t--l'~......,-+-+--+--t---+-t--i

tl

1t

~-+-~--5o/.~,S+U~pp-LY~~/~~~~~~~~~

·50 -25

VLL

1500 t--t--t--t--t-t--+-+--+--i

75 100 125

""'-

f-+-+--+--+-......-F".....I"""'-~- i5'C
-9

TA ('C)

.......

I-+--t-.....
-T"-.d-,......,-""I"oo;;;:t---t--t-~

-10

-11

Vee (Volts)

5·40

-12

-13

MOS EPROMs

~National

D Semiconductor
MM4204/MM5204 4096·Bit (512 x 8)
UV Erasable PROM
General Description
The MM4204/MM5204 is a 4096-bit static read only
memory which is electrically programmable and uses
silicon gate technology to achieve bipolar compatibility.
The device is a non·volatile memory organized as 512
words by 8 bits per word. Programming of the memory
is accomplished by storing a charge in a cell location by
applying a -50V pulse. A logic input, Power Saver, is
provided which gives a 5:1 decrease in power when the
memory is not being accessed.

•

Static operation-no clock required

•

Easy memory expansion-TRI-STATE® output Chip
Select input (CS)
-

•

"Q" quartz lid version erasable with short wave ultra-

violet light (i.e., 253.7 nm)
• Low power dissipation
• "Power Saver" control for low power applications
•

Compatible with SC/MP II N·channel microprocessor

Features
Applications
•
•

Field programmable
Fast program time: ten seconds typical fo,r 4096 bits

•

Fast access time
MM4204
MM5204

•
•

DTLlTTL compatibility
Standard power supplies

•
•

Code conversion
Random logic synthesis

1.251ls
1 Ils

•
•

Table look-up
Character generator

5V,-12V

•
•

Microprogramming
Electronic keyboards

Block and Connection Diagrams
Dual·ln-Line Package
AD
AI
409&.8IT
EPROM
MATRIX
512,S

A2
A3

~VLl

vaa

~voo

POWER SAVER

VOO

I
~Vaa

12

~Vss

4

PROGRAM

B&

AD

B5

AI

84

A2

B3

~PROGRAM

A4

AS

A6

POWER SAVER

A1

A3

AS

16

A4

15
14

AS

13

TOP VIEW
BD 81 82 83 84 85 8681

Order Number MM4204D
orMM5204D
See NS Package D24C
Order Number MM4204Q
or MM5204Q
See NS Package J24CQ

5-41

BI
Bo
AI
A7

Absolute Maximum Ratings
All Input or Output Voltages with
Respect to VBB Except During Programming
Power Dissipation
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)

Operating Temperature Range
MM5204
MM4204

+O.3V to -20V
750mW
-65°C to +125°C
300°C

DC Electrical Characteristics
MM4204: Vss

Operating Conditions

(Note 1)

O°C to +70°C
-55°C to +B5°C

TA within operating temperature range, VLL = OV, VBB = PROGRAM
Vss = 5V ±5%, Voo = -12V ±5%, unless otherwise noted.
TYP

SYMBOL

PARAMETER

CONDITIONS

MIN

(Note 7)

MAX

V IL

Input Low Voltage

V ss -14

V ss -4.2

V IH

Input High Voltage

V ss -1.5

Vss+0.3

ILl

Input Current

V IN

= OV

VOL

Output Low Voltage

IOL

= 1.6 mA

V LL

V OH

Output High Voltage

IOH

= -0.8 mA

2.4

I Lo

Output Leakage Current

V OUT = OV, CS

100

Power Supply Current

MM5204

MM5204
MM4204
MM5204
MM4204
MM5204

Iss

1.0

-

MM4204

MM4204

SYMBOL
t Aee

tpo

teo

= V IH

CS = V IH , Power Saver = V IL
T A = O°C, CS = V IH , Power Saver = V IL
TA = O°C, CS = V IH , Power Saver = V IH
T A = O°C, CS = V IH , Power Saver = V IH
TA = O°C, CS = V IH , Power Saver = V IL
T A = O°C, CS = V IH , Power Saver = V IL
T A = O°C, CS = V IH , Power Saver = V IH
T A = O°C, CS = V IH , Power Saver = V IH

28

TA = O°C,

AC Electrical Characteristics
MM4204: Vss

= Vss,

= 5V ±10%, Voo = -12V ±10%, MM5204:

6.0

UNITS
V
V
pA

0.4

V

Vss

V

1.0

pA

40.0

mA

50.0

mA

8.0

mA

10.0

mA

42

mA

52

mA

10

mA

12

mA

TA within operating temperature range, VLL = OV, VBB = PROGRAM
Vss = 5V ±5%, Voo = -12V ±5%, unless otherwise noted.

= Vss,

= 5V ±10%, Voo = -12V ±10%, MM5204:

CONDITIONS

PARAMETER

MIN

TYP
(Note 7)

MAX

UNITS

Access Time

= 70°CJFigure

MM5204

TA

MM4204

T A = 85°C, (Figure 1), (Note 4)

1), (Note 4)

0.75

1.0

ps

1.25

ps

Power Saver Set·Up Time
MM5204

(Figure 1)

1.8

ps

MM4204

(Figure 1)

2.0

ps

Chip Select Delay
MM5204

(Figure 1)

500

ns

MM4204

(Figure 1)

600

ns

tOH

Data Hold Time

(Figure 1)

30

50

tODe

Chip Select
MM5204

(Figure 1)

30

300

500

ns

MM4204

(Figure 1)

30

300

600

ns

MM5204

(Figure 1)

30

300

500

ns

MM4204

(Figure 1)

30

300

600

ns

5.0

8.0

pF

8.0

15

pF

tODP

D~select

ns

Time

Power Saver Deselect Time

CIN

Input Capacitance (All Inputs)

V IN = V ss , f = 1.0 MHz, (Note 2)

COUT

Output Capacitance

V OUT

(All Outputs)

(Note 2)

= V ss , CS

= V IH , f = 1.0 MHz,

\

5·42

3:
3:

Programmer Electrical Characteristics
TA

= 25°C,

SYMBOL

Vss

= CS = Power Saver = OV,

VLL

= OV

to -14V, unless otherwise specified, (Figure 2), (Note 5).

CONDITIONS

PARAMETER

TYP

MIN

(Note 7)

~
I\)

MAX

UNITS

I LO

Data Input Load Current

V 1N =-18V

-10

mA

IALO

Address Input Load Current

V 1N = -50V

-10

mA

I LP

Program Load Current

V 1N = -50V

-10

mA

ILSS

Vss Load Current

50

mA

I LOO

Voo Load Current

-200

mA

V 1HP

Address Data and Power Saver

0.3

V

VOO = PROGRAM = -50V
-2.0

Input High Voltage
Address Input Low Voltage

-50

-11

V

Data Input Low Voltage

-18

-11

V

V OHP

Voo and Program High Voltage

-2.0

0.5

V

V OLP

Voo and Program Low Voltage

-50

-48

V

V SLP

Vss Low Voltage

0

0.4

V

V SHP

V ss High Voltage

11.4

12.6

V

Voo

Pulse Duty Cycle

25

%

5.0

ms

V 1LP

\

tpw

_Program Pulse Width

0.5

tos

Data and Address Set·Up Time

tOH

Data and Address Hold Time

0

tss

Pulsed Voo Set·Up Time

40

tSH

Pulsed Voo Hold Time

1.0

j1S

tss

Pulsed Vee Set· Up Time

1.0

I1 s

tSH

Pulsed Vse Hold Time

1.0

j1S

t pss

Power Saver Set·Up Time

1.0

j1S

tpSH

Power Saver Hold Time

1.0

j1S

t A , tF

V oo , Program, Address and Data

40

j1S
j1S

100

1.0

j1S

j1S

Rise and Fall Time
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: Positive true logic notation is used except on data inputs during programming
Logic "1" = most positive voltage level
Logic "a" = most negative voltage level
Note 4: tAce = 700 ns + 25 (N-1) where N is the n.umber of devices wire-OR'd together.
Note 5: The program cycle should be repeated until the data reads true, then over-programmed 5 times that number of cycles. (Symbolized as
X + 5X programming).
Note 6: The EPROM is initially programmed with all "a's." A VIHP on any data input 80-87 will leave the stored "O's" undisturbed, and a VILP
on any data input 80-87 will write a logic "1" into that location.
Note 7: Typical values are for nominal voltages and T A = 25°C, unless otherwise specified.

Erase Specification
The recommended dosage of ultraviolet light exposure\ is 6W sec/cm 2 .

Programming
The MM4204/MM5204 is normally shipped in the unprogrammed state_ All 4096-bits are at logic "0" state.
The table of electrical programming characteristics and
Figure 2 give the conditions for programming of the
device. In the program mode the device effectively
becomes a RAM with the 512 word locations selected by

address inputs AO-AB. Data inputs are 80-87 and
write operation is controlled by pUlsing the Program
input. Since the EROM is initially shipped with all "a's,"
a VIHP on any data input 80-87 will leave the stored
"a's" undisturbed and a VILP on any data input 80-87
will write a logic "'" into that location.

5-43

0

~

3:
3:
01

I\)

0

~

Programming

(Continued)

National offers programmer options with both the
IMP16-P and the PACE IPC-16P Microprocessor Development Systems.

Microprocessor System

Programmer Part Number

IMP16-P
IPC-16P

IMP16-P/S05
-IPC-16P/S05

Contact the local sales office 'for further information.
There are also several commercial programmers available
such as the Data I/O Model V.
Most National distributors have programming capabilities available. Those' distributors should be contacted
directly to determine which data entry formats are
available.
In addition, data may be submitted to National Semiconductor for factory programming. One of the following formats should be observed:

Preferred Format
The custom patterns may be sent in on a Telex or submitted as a paper tape in a 7-bit ASCII code from model 33 teletype or TWX. The paper tape should be as the following example:

Start Character

.l fr

l

Carriage return line feed

allowed between F and B.

Stop Character

I' - ,

Data Field"

MSB IPin 111

I

Leader: Rubout for

T~~t::el:~~:I~eS~

LSB IPon 41
Trailer: Rubout for
TWX or letter Key
for telex lat least
25 framesl.

BP P PN P PN N F BN NP PN NP P F ,,, BN P NP N N N N F

25 framesl.

Jl...._ _ _ _- - "

Word

a

Word 511

Word 1

,

All Address Inputs HIGH

All Address Inputs LOW

4Data Field: Must have only P's or N's typed between Band F. No nulls or rubouts. Must have exactly eight P and N characters between
Band F. Any characters except Band F may be typed between the F stop character and the B start character. If an error is made in preparing a tape the entire word including the Band F start and stop characters must be rubbed out. Data for exactly 512 words must be
entered beginning with word O.

Alternate Format

[Punched Tape (Note 1) or Cards)
" b 7 • MSB (Pin 22)

MM5204
Positive Logic

bOo LSB (Pin 15)

2 Spaces -,---+--------,
i'\nnf)
An,))

i\l1fl 5
~\ () !l f)

nqqdl}()fl')

1\ ,) ()

t~

I,

r)., I I I I no

4

O()I1f),)f)nn

"

-

() I ,11 r) I r)) I,
51 I
lSI t 4'1 ~--------i-HlG I ~()
165 ,)5i)
1114 4f)'1
TIl3 Ot'1
TB2 tOO
lSI 299
I SO 197
~'\

Note 1: The code is a 7-bit ASCII code on 8 punch tape. The
tape should begin and end with 25 or more "RUBDUT" punches.
Note 2: The ROM input address is expressed in decimal form
and is preceded by the latter A.
Note 3: The total number of "1" bits in the output word.
Note 4: The total number of "1" bits in each output column or
bit position.

1 Space

'l

"I

.~I1'l~

.. ~ ' ) I )

-

~-~--Note3

Of)f)'lnnnq n
nnW)()nn,) n
n I n III I "I
(V)ltllll i>
n(I())IIOf) .l

linn?
.'f)I)J

Note 4

t

L - - - - - - - - - t - - l Space

Erasing Procedure
The MM42040/MM52040 may be erased by exposure
to short-wave ultraviolet light-253.7 nm_ There exists
no absolute rule for erasing time or distance from
source. The erasing equipment output capability should
be calibrated. Establish a worse case time required with
the equipment. Then over-erase by a factor of 2, i.e., if
the device appears erased after S minutes, continue
exposure for an additional 16 minutes for a total of 24

minutes. Examples of UV sources include the Model
UVS-54 and Model S-52 manufactured by Ultra-Violet
Products, Inc. (5114 Walnut Grove Avenue, San Gabriel,
California). The lamps should be used without shortwave filters. The MM4204/MM5204 should be placed
about one inch away from the lamp for about 20-30
minutes.
5-44

AC Test Circuit

3:
3:

Typical Application

~
I\)

CHIP
SELECT

0

e

Cs"
AO

AO-AS

'"'"'"
INPUTS

MM4204!
MM5204

[
AS

12V'5%

VOO
Vss

12V

'5~.

OV

VBB
5V'5%
OV

PROGRAM
Vu

* tACC. tOH. tCD. and too measured
POWER
ON

at output of MM4204/MM5204.

Switching Time Waveforms
VIH
ADDRESS
VIL
VIH
POWER SAVER
VIL
VIH
CHIP SELECT
VIL
VIH
OATA OUT
VIL

Note. All times measured with respect to 1.5V level with tr and tf ::; 20 ns

FIGURE 1. Read Operation

Programming Waveforms

VOO
VOLP----I-'-------------J

VIHP
POWER
SAVER
VILP

VIHP=='0:':'~.1
AOORESS
ANO OATA

,-+--------+---..

VILP

VOHP - - - - - - - - .

PROGRAM
VOLP-------I~-------J------

FIGURE 2. Programming Waveforms

5-45

3:
3:
U1

I\)

MM4204!
MM5204

OMI400

AO-AS

BO

BI

0

~

~National

MOS EPROMs

~ Semiconductor

MM5204·1 4096·Bit (512 x 8) UV Erasable PROM
General Description
The MM5204-1 is a 4096-bit static Read Only Memory
which is electrically programmable and uses silicon gate
technology to achieve bipolar compatibility_ The device
is a non-volatile memory organized as 512 words by 8
bits per word. Programming of the memory is accomplished by storing a charge in a cell location by applying
a -50V pulse. A logic input, "Power Saver", is provided
which gives a 5: 1 decrease in power when the memory is
not being accessed.

• Static operation-no clock required
• Easy memory expansion-TRI-STATE® output Chip
Select input (CS)
• "Q" quartz lid version erasable with short wave ultraviolet light (i.e., 253.7 nm)
• Low power dissipation
• "Power Saver" control for low power applications
• Compatible with SC/MP II N-channel microprocessor

Features

Applications

• Field programmable
• Fast program time: ten seconds typical for 4096 bits
• Fast access time
MM5204-1
700 ns
• DTL/TTL compatibility
5V,-12V
• Standard power supplies

•
•
•
•
.•
•

Code conversion
Random logic synthesis
Table look-up
Character generator
Microprogramming
Electronic keyboards

Block and Connection Diagrams
Dual-In-Line Package
AD

.,2!..VLL

AI

.,lLvoo

A2

1
+--V88

A]

INPUT
8UFFERS

409681T
EPROM
MATRIX
512.8

24
2]
Voo
2287

CHIPSELECT ]

12
~VSS

~PROGRAM

A4

VLL

V88
POWER SAVER

PROGRAM
AO

A5

A6

AI

84

A2

8]

A7
A]
A8
16 81

A4
A5

15

10

1]

12

VSS
TOPVIEW

8081828] 84 85 86 87

Order Number MM5204Q-1
See NS Package J24CQ

5-46

80

14 A8

AS 11

A7

Absolute Maximum Ratings

(Note 1)

All Input or Output Voltages with
Respect to VBB Except During Programming
Power Dissipation
Storage Temperature Range
Lead Temrerature (Soldering, 10 seconds)

+0.3V to -20V
750mW
-65°C to +125°C
300°C

DC Electrical Characteristics
TA = DoC, to +70°C, VLL = OV, VBB = PROGRAM = VSS, VSS = 5V ±5%, VDD = -12V ±5%, unless otherwise noted.

SYMBOL

,

PARAMETER

CONDITIONS

VIL

Input Low Voltage

VIH

Input High Voltage

III

I nput Current

VIN

VOL

Output Low Voltage

IOL = 1.6 mA

VOH

Output High Voltage

IOH

ILO

Output Leakage Current

VOUT = OV, CS = VIH

100

Power Supply Current

T A = 0° C, CS = V I H,

ISS

VSS Current

MIN

TYP
(Note 2)

VSS-14
VSS-1.5
=

=

UNITS

VSS-4.2

V

VSS+0.3

V

1.0

J.1A

VLL

0.4

V

2.4

VSS

OV

-0.8 mA

MAX

V

1.0

J.1A

Power Saver = V I L

28

40.0

mA

Power Saver = V I H

6.0

8.0

mA

TA=O°C,CS=VIH
Power Saver = VI L

42

mA

Power Saver = V I H

10

mA

AC Electrical Characteristics
TA = DoC to +70°C, VLL =

SYMBOL

ov, VBB = PROGRAM =

Vss, Vss = 5V ±5%, VDD = -12V ±5%, unless otherwise noted.

PARAMETER

CONDITIONS

MIN

TYP
(Note 2)

MAX

UNITS

tACC

Access Time

T A = 70°C, (Figure 1)

700

ns

tpo

Power Saver Set-Up Time

(Figure 1)

1.4

J.1s

tco

Chip Se.lect Delay

(Figure 1)

250

tOH

Data Hold Time

(Figure 1)

30

tODC

Chip Select Deselect Time

(Figure 1)

30

200

500

ns

tODP

Power Saver Deselect Time

(Figure 1)

30

200

500

ns

CIN

Input Capacitance (All Inputs)

VIN = VSS, f = 1.0 MHz, (Note 3)

5.0

8.0

pF

COUT

Output Capacitance

VOUT = VSS,

8.0

15

pF

(All Outputs)

(Note 3)

CS = VIH,

f = 1.0 MHz,

ns
ns

50

Note1:"Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Typical values are for nominal voltages and T A = 2SoC, unless otherwise specified.
Note 3: Capacitance is guaranteed by periodic testing.

5-47

•

Typical Application

AC Test Circuit

CHIP
SELECT
80

ADDRESS [
INPUTS
MM5204·1
87

-12V ,5%

0-----1

5V ,5%

0--"'--1

ovO-----I

*tACC. tOH. teo and too measured at output of MM5204-1

POWER
ON

Switching Time Waveforms
VIH
ADDRESS
VIL
VIH
POWER SAVER
VIL
VIH
CHIPSELECT
VIL
VIH
DATA OUT
VIL

Note. All times measured with respect to 1.5V level with tr and tf ::; 20 ns
FIGURE 1. Read Operation

Programming Information
Refer to the MM4204/MM5204 data sheet for programming information.

5-48

~National

MOS EPROMs
ADVANCE INFORMATION

D Semiconductor

NMC2532 32k·Bit (4k x 8) UV Erasable PROM
General Description

Features

The NMC2532 Is a 32,768-blt EPROM operating trom a
single 5V power supply_ This device Is an ultraviolet
erasable, electrically programmable, read only memory
fabricated using National's high speed, low power, silicon
gate technology.

• Single 5V power supply
• 450 ns max access time

This device Is deselected when pin 20 Is high and automatIcally placed In the standby mode. This mode provides an
85% reduction In power with no Increase In access time.

•
•
•
•
•

Bits may be programmed at random, In sequence or singly. Typical erasure time Is 20 minutes using a 12 mW/cm 2
ultraviolet lamp.

• Lowpower:
Active -160 mA max
Standby - 25 mA max
Fullystatlc
TRI-STATEI!) output
All 110 pins TTL compatible
Pin compatible with existing EPROMs and ROMs
Single location programming

Block and Connection Diagrams*
Dual-In-Line Package
VCC

GNO
(VSS)

VPP

! ! !

--+
--+
--+
--+
--+
--+
--+

AU-All
ADDRESS
INPUTS

DATA OUTPUTS
°1-0a(01-0a)

•

X
DECODER

3Z.768·BIT
CELL MATRIX

---+

A7

vcc

A6

Aa

AS

A9

A4

VPP

A3

PO/PGM(S/P/

AZ

AID

Al

Al1

AD

Oa(oa)

01(01)

07(07)

02(02)

06(06)

03(03)

05(05)

GNO(VSS)

04(04)
TOP VIEW

Modes*
Order Number NMC2532Q
See NS Package J24CQ

Pin Name/Number
Mode
Read
Standby
Program
Program Verify
Program Inhibit

PD/PGM
(SIP)
20
VIL
VIH
Pulsed VIH
to VIL
VIL
VIH

VPP
21

VCC
24

Outputs
9-11,13-17

5V
5V
25V

5V
5V
5V

DOUT
Hi-Z
DIN

5V
25V

5V
5V

DOUT
Hi-Z

* Symbols In parentheses are proposed Industry standard.
5-49

Pin Names*
PD/PGM (SIP)
AO-A11

°1-°8(01-08)
VPP
VCC
GND(VSS)

Power Down (Chip Select)
Address Inputs
Data Outputs
Program Power (25V)
Power (5V)
Ground

Absolute Maximum Ratings (Note 1)
-10·Cto +80·C
- 65·C to + 125·C
+6Vto -0.3V

Temperature under Bias
Storage Temperature
All Input and Output Voltages
with Respect to VSS During Read
VPP Supply Voltage with Respect
. to VSS During Programming
Power Dissipation
Lead Temperature (Soldering, 10 seconds)

+ 26.5V to - 0.3V
1.5W
300·C

READ OPERATION
Operati~g
(Note 2)
TA = O·C to 70·C, VCC = 5V ± 5%, VSS = OV, VPP = VCC ± 0.6V (Note 3)

DC

Characteristics

Symbol

Max

Units

VIN =5.25V

10

p.A

VOUT=5.25V

10

p.A

25

mA

Parameter

Min

Conditions

III

Input Load Current

ILO

Output Leakage Current

ICC1

VCC Current Standby

PD/PGM (SIP) = VIH
PD/PGM (SIP) = VIL

ICC2

VCC Current Active

VIL

Input Low Voltage

VIH

Input High Voltage

VOL

Output Low Voltage

IOL=2.1 mA

VOH

Output High Voltage

IOH= -400p.A

IPP1/1PP2

VPP Standby/Active Current

AC Characteristics

Typ

15
85
-0.1
2.2

160

mA

0.65

V

VCC+1

V

0.45

V

300

p.A

2.4

V

TA = o·c to 70·C, VCC = 5V ± 5%, VSS = OV, VPP = VCC ± 0.6V (Note 3)

Symbol
Parameter
Alternate

Standard

t ACC

TAVQV

Address to Output Valid

t APR

TSLQV

Select to Output Valid

t pxz

TSHQZ

Select to Output Hi-Z

t pvx

TAXQX

Address to Output Hold

Conditions

Min

PG/PGM=VIL

0
PD/PGM =VIL

0

Max

Units

450

ns

450

ns

100

ns
ns

Capacitance (Note 4) TA = 25 ·C, f = 1 MHz
AC Test Conditions
Symbol

Parameter

Conditions

Typ

Max

Units

CIN

Input Capacitance

VIN =OV

4

6

pF

COUT

Output Capacitance

VOUT=OV

8

12

pF

Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: ::520 ns
Input Pulse Levels: 0.8V to 2.2V
Timing Measurement Reference Level:
Wand2V
Inputs
Outputs O.8V and 2V

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature
Range" they are not meant to imply that the devices should be operated at these limits. The table of "Recommended DC Operating Conditions" provides conditions for actual device operation.
Note2: Typical values are forTA

=25"C and nominal supply voltages.

Note 3: VPPcan be tied directly to VCC(except during programming).
Note 4: Capacitance measured with Boonton Meter or effective capacitance calculated from the equation C = l.:l.tI.:l.V. Capacitance is guaranteed by periodic
testing.

5-50

z

s::

Switching Time Waveforms·

o
N

en
W
N

Read Cycle
VIH~~~~~-'------------------------~

ADDRESSES
VIL~~~~~~~

VALID
________________________

VALID
~

tpvx
--(TAXQX)-VIH

==========~======~

PD/PGM
vIL-----------t---------1~

tACC

__________________

1_...
_ -.....-1- tAPR
(TSLQV)

~

tpxz
(TSHQZ)

VOH------------~·------(~T~A~VQ~V~)~~----~~------------------~
Hi·Z

OUTPUT

VOL--------------------------~

VALID
________________J

Hi·Z

Standby Power Down Mode
VIH
ADDRESSES

VALID

VALID

VIL

VIH
PD/PGM

VIL

VOH
OUTPUT
VOL

STANDBY

---

VALID FOR
CURRENT ADDRESS

STANDBY

tpxz
-(TSHQZ)
Hi·Z

* Symbols in parentheses are proposed Industry standard.

5·51

VALID FOR
CURRENT ADDRESS

Hi·Z

PROGRAM OPERATION
DC Characteristics TA = 25°C ± SoC, VCC = 5V ± 5%, VPP = 25V ± 1V
Symbol

Parameter

Min

Conditions

III

Input Current All Inputs

VIN = VIL or VIH

VOL

Output Low Voltage During Verify

IOL=2.1 rnA

VOH

Output High Voltage During Verify

IOH= -400~A

ICC

VCC Supply Current

VIL

Input Low Level All Inputs

VIH

Input High Level All Inputs Except VPP

IPP

VPP Supply Current

Typ

Max

Units

10

~A

0.45

V

160

rnA

2.4

V
85

-0.1
2.2

0.65

V

VCC+1

V

30

rnA

PD/PGM (SIP) = VIL

AC Characteristics TA=25°C±5°C, VCC=5V±5%
Symbol
Alternate

Parameter

Typ

Min

Units

Max

Standard

tSUA

TAVPL

Address Set·Up Time

2

P.s

tsuo

TDVPL

Data Set-Up Time

2

P.s

tsuvpp

TVPPHPL

VPP Set-Up Time

0

tWPR

TPLPH

Program Pulse Width

45

tHO

TPHDX

Data Hold Time

2

p's

t HVPP

TPHVPPL

VPP Hold Time

0

.ns

tHPR

TVPPLPL

VPP Recovery Time

0

tAPR

TSLOV

Select to Output Valid

tHA

TSHAX

Address Hold Time

t pxz

TSHOZ

ns
50

55

ms

ns
ns

450

ns

0

Select to Output Hi·Z

ns

100

0

Programming Waveforms· (Note5)TA=25°C±5°C, VCC=5V±5%, VPP=25V±1V

..
ADDRESSES

VIH

"-

VIL

I

)(

. .
..

..

,~I
,

ADDRESS X+1

tsuvpp
(TVPPHPL)

~r-

tAPR
(TSLQV)-

)r

tHVPP
\
(TPHVPPL)

twPR
(TPLPH)

..

1---

+5V

1"- DATA OUT VALID'

Hi·Z

-

tHO
(TPHDX)--

+Z5V

VPP

K

tSUA
(TAVPL)
DATA IN STABLE ~rADD X
..,'f..

VIL
tSUD
(TDVPL)

..

\

~

Note 5: The Input timing reference level Is O.65V for VIL and 2.2V for VIH,
• Symbols In parentheses are proposed Industry standard.

5·52

---

CSHnZ)
tpxz

tHA
(TSHAX)--

...

,~

~~

'----I~

--

Hi·Z

ADD X

1\

I

PD/PGM VIH
(S/P) VIL

PROGRAM
-VERIFY--

ADDRESS X

VIH
DATA

..

PROGRAM

tHPR
(TVPPLPL)

~

Functional Description
data). After the address and data signals are stable the
PD/PGM pin is pulsed from VIH to VIL with a pulse
width between 45 ms and 55 ms~

DEVICE OPERATION
The NMC2532 has two modes of operation in the normal
system environment. These are shown in Table I.

~

PD/PGM
(SIP)

Mode

ICC Max
24

Outputs
9-11,13-17

160 rnA
25 rnA

DOUT
Hi·Z

20,

VIL
VIH

Read
Standby

Multiple pulses are not needed but will not cause device
damage. No pins should be left open. A low level, VIL or
lower must not be maintained steady state (DC signal) on
the PD/PGM pin during programming. Several NMC2532s
may be programmed in parallel (the same data in each
one) in this mode.

=5V)*

TABLE I. OPERATING MODES (VCC

Program Verify
The programming of the NMC2532 may be verified, either
one word at a time during the programming (as shown in
the timing diagram) or by reading all of the words out at the
end of the programming sequence.

Read Mode

=

The NMC2532 read operation requires that PD/PGM VIL
and that addresses AO-A11 have been stabilized. Valid
data will apear on the output pins after t ACC or tAPA times
(see Switching Time Waveforms) depending on which is
limiting.

Program Inhibit
The program inhibit mode allows programming several
NMC2532s In parallel with different data for each one by
controlling which ones receive the program pulse. All
similar inputs may be paralleled. Pulsing the PD/PGM pin
from VIH to VIL on a selected unit or units will cause programming, while inhibiting the PD/PGM pulse will inhibit
programming and keep the outputs of the inhibited
devices in the Hi-Z state.

Standby Mode
The NMC2532 Is placed in the standby mode (deselected
and powered down) by making PD/PGM = VIH. This automatically controls the outputs to their Hi-Z state. The
power dissipation is reduced to 15% of the normal
operating power. VCC must be kept at 5V. Access time at
power up (chip selection) remains either t ACC or tAPA (see
Switching Time Waveforms).

ERASURE PROCEDURE
The NMC2732 is erased by exposure to high intensity ultraviolet light through the transparent window. This exposure discharges the floating gates to their initial state
through induced photo current. It is recommended that
this device be kept out of direct sunlight. The UV content
of sunlight may cause the a partial erasure of some bits in
a relatively short period of time. Direct sunlight (any intense light) can cause temporary functional failure due to
generation of photo current. Extended exposure to room
level fluorescent lighting will also cause erasure. An
opaque coating (paint, tape, label etc.) should be placed
over the package window if this product is to be operated
under these lighting conditions.

PROGRAMMING
The NMC2532 is shipped from National completely
erased. All bits will be at a "1" level (outputs high) in this initial state after any full erasure. Table II shows the three
programming modes.
TABLE II. PROGRAMMING MODES (VCC = 5V)*

I~
Mode

Program
Program Verify
Program Inhibit

PD/PGM (SIP)

VPP

Outputs

20

18

9-11,13-17

VIL
VIL
VIH

25V
5V
25V

DIN
DOUT
Hi-Z

An ultraviolet source of 2537A yielding a total integrated
dosage of 15 Watt-seconds/cm 2 is required. This will erase
a unit in approximately15t020 minuteswhena UV lampof
a 12 mW/cm 2 power rating is used. The NMC2532 to be
erased should be placed one inch away from the lamp and
no filters should be used .

. Program Mode
The NMC2532 is programmed by placing "O"s into the desired locations. This is done 8 bits (a byte) at a time. Any individual address, a sequence of addresses, or addresses
chosen at random may be programmed. Any or all of the 8
bits associated with an address location may be programmed with a single program pulse applied to the
PD/PGM (SIP) pin. All inp~oltage levels, including the
program pulse on the PD/PGM pin are TIL compatible. The
programming sequence is:

An erasure system should be calibrated periodically. The
distance from lamp to unit should be maintained at one
inch. The erasure time increases as the square of the
distance. (If distance is doubled the erasure time increases by a factor of 4.) Lamps lose intensity as they age.
When a lamp is changed, the distance has changed or the
lamp has aged, the system should be checked to make
certain full erasure is occurring. Incomplete erasure will
cause symptoms that can be misleading. Programmers,
components, and even system designs have been erroneously suspected when incomplete erasure was the
problem.

=

With the VPP pin at 25V and VCC 5V, an address is
selected and the desired data word is applied to the out·
put pins (VIL "0" and VIH "1" for both address and

=

=

* Symbols in parentheses are proposed Industry standard.
5-53

~National

MOS EPROMs

~ Semiconductor

NMC2564 64k·Bit (8k

X

PREVIEW

8) UV Erasable PROM

General Description

Features

The NMC2564 is a 65,536-bit EPROM operating from a
single 5V power supply. This device is an ultraviolet
erasable, electrically programmable, read only memory
fabricated using National's high speed, low power, silicon
gate technology.

• Single 5V power supply

This device is deselected when pin 20 is high and
automatically placed in the standby mode. This mode provides an 85% reduction in power with no increase in
access time.

•
•
•
•

• 450 ns max access time
• Low power:
Active - 200 mA max
Standby - 30 mA max

Bits may be programmed at random, in sequence or singly.
Typical erasure time is 20 minutes using a 12 mW/cm 2
ultraviolet lamp.

Fully static
TRI-STATE® output
All 1/0 pins TIL compatible
Pin compatible with the 2516 and 2532'EPROMs

• Separate chip selects for multiple bus systems
• Single location programming

Block and Connection Diagrams*
VPP

VCC

Dual-In-Line Package

GND
(VSS)

! ! !
5V

25V

28

VPP
DATA OUTPUTS
(01-08) 0,-08

VCC

CSi (Si)

GND

A7
A6
A5
OUTPUT BUFFERS

A4

---+.r---~----~---+t---------j

AJ

---+

A2

Y
DECODER

y·GATING

~~-----{==~------~

AO-Al1
ADDRESS
INPUTS

---+
---+
---+

AI
AD
0, (01)

X
DECODER

-.
-.

32,768·8IT
CELL MATRIX

02 (Cl2)
(Cl5) 05

--+

GND (VSS)

14

(Cl4) 04
TOP VIEW

Modes
Pin NamelNumber
PD/PGM

CS1

CS2

Outputs

1

(SIP)
22

(51)

(52)

2

27

(01-08)
11-13.15-19

5

5

VIL

VIL

VIL

DOUr

5

5

VIL

VIH

X

Hi·Z

Deselect

5

5

VIL

X

VIH

Hi·Z

vee

VPP

26,28
Read
Deselect

Mode

Pin Names
PD/PGM (SIP)
AO-A12
0 1-0 8 (01-08)
VPP

Standby

5

5

VIH

X

X

Hi·Z

Program Inhibit

5

25

VIH

X

X

DIN

Program Inhibit

5

25

X

VIH

X

DIN

vee

Program Inhibit

5

25

X

X

VIH

DIN

GND(VSS)

Program

5

25

Pulsed VIH
toVIL

VIL

VIL

DIN

x= don't care
• Symbols In parentheses are Industry standard

5-54

Power Down (Chip Select)
Address Inputs
Data Outputs
Program Power (+ 25V)
Power (+5V)
Ground

.
~ Semiconductor
~National

MOS EPROMs
PREVIEW

z

s:
o
I\)

"""-'
o
......
C')

NMC27C16 16,384-Bit (2048 x 8) UV Erasable CMOS PROM
General Description

Features

The NMC27C16 Is a high speed 16k UV erasable and
electrically reprogrammable EPROM ideally suited for
applications where fast turn-around and pattern experimentation are important requirements.

•
•
•
•
•
•

The NMC27C16 is packaged in a 24-pin dual-in-line
package with transparent lid. The transparent lid allows
the user to expose the chip to ultraviolet light to erase the
bit pattern. A new pattern can then be written into the
device by following the programming procedure.

2048 x 8 organization
Low power during programming
Access time-450 ns
Single 5V power supply
Static-no clocks required
Inputs and outputs TIL compatible during both read
and program modes

• TRI·STATE@ output

This ERPOM is fabricated with the reliable, high volume,
time proven, CMOS silicon gate technology.

Block and Connection Diagrams'"

Dual-In-Line Package
A7

+-- VPP+5V
+-- VCC+5V
+-- VSS GNO
DATA OUTPUTS (PROGRAM INPUTS)
00-07 (00-07)

A6

23 A8

A5

22 A9

A4

21 VPP

A3

20

A2

19 AIO

AI

18 CEiPGM(E"iP)

DE (ii)

AO

00 (00)

14 04 (04)
VSS

12

13 03(03)

TOP VIEW

Pin Connection During Read or Program

Pin Names
AO-A10
0 0-0 7 (00-07)
CE/PGM (EJP)
OE(G)
VPP
VCC
VSS

Pin Name/Number
Mode

Read
Program

CE/PGM
(ElP)

OE
(G)

18

20

VIL
Pulsed VIL
toVIH

VIL
VIH

VPP

VCC

Outputs

21

24

9-11,13-17

5
25

5
5

DOUr
DIN

* Symbols In parentheses are proposed Industry standard.

5-55

Addres Inputs
Data Outputs
Chip Enable/Program
Output Enable
Read 5V, Program 25V
Power5V
Ground

co

(3
t-.

N

o

~

z

Absolute Maximum Ratings (Note 1)
- 25°C to + 85°C
- 65°C to + 125°C
26.5V to - 0.3V

Temperature Under Bias
Storage Temperature
VPP Supply Voltage with Respect
toVSS
Allinput or Output Voltages with
Respect to VSS (except VPP)
Power Dissipation
Lead Temperature (Soldering, 10 seconds)

VCC + 0.3V to - 0.3V
1.5W
300°C

READ OPERATION
DC Operating Characteristics

TA=O°C to + 70°C, VCC=5V±5%, (VCC = 5V ± 10% for
NMC27C16-1), VPP = VCC ± 0.6V (Note 3), VSS = OV, unless otherwise noted.
Symbol

Parameter

Conditions

Min

Typ

Max

Units

III

Input Current

VIN = 5.25V or VIN = VIL

10

p.A

ILO

Output Leakage Current

VOUT = 5.25V, CE/PGM = 5V

10

p.A

IPP1

VPP Supply Current

VPP=5.B5V

5

rnA

ICC1

VCC Supply Current (Standby)

CE/PGM = VIH, OE = VIL

10

25

rnA

ICC2

VCC Supply Current (Active)

CE/PGM = OE = VIL

57

100

mA

VIL

Input Low Voltage

O.B

V

VIH

Input High Voltage

VCC+1

V

VOH

Output High Voltage

IOH = -400 p.A

VOL

Output Low Voltage

IOL=2.1 rnA

-0.1
2.0
2.4

V
V

0.45

AC Characteristics

(Note 2) TA = O°C to + 70°C, VCC = 5V ± 5%, (VCC = 5V ± 10% for NMC27C16-1),
VPP = VCC ± 0.6V (Note 3), VSS = OV, unless otherwise noted.
Symbol
Alternate Standard

Parameter

Conditions

NMC27C16
Min
Max

NMC27C16-1 NMC27C16-2
Max Units
Min
Min
Max

tACC

TAVQV

Address to Output Delay

CE/PGM = OE = VIL

450

350

390

ns

tCE

TELQV

CE to Output Delay

OE=VIL

450

350

390

ns

tOE

TGLQV

Output Enable to Output Delay

CE/PGM=VIL

120

120

120

ns

tDF

TGHQZ

Output Enable High to Output Hi·Z

CE/PGM=VIL

0

100

ns

tOH

TAXQX

Address to Output Hold

CE/PGM = OE = VIL

0

tOD

TEHQZ

CE to Output Hi·Z

OE=VIL

0

Capacitance TA=25°C, f=1
Symbol

Parameter

100

0

100

0
100

0

0
0

100

0

ns
100

ns

MHz

Conditions

Typ

, Max

Units

CI

Input Capacitance

VIN =OV

4

6

pF

CO

Output Capacitance

VOUT=OV

B

12

pF

AC Test Conditions
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: ::;20 ns

Note 1:"Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to Imply that the devices sh?uld be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Typical conditions are for operation at: TA= 2SoC, VCC=SV, VPP=VCC, and VSS =OV.
Note 3: VPP may be connected to VCC except during program. The ± O.6V tolerance allows a circuit to switch VPP between the read voltage and
the program voltage.
Note 4: Capacitance is guaranteed by periodic testing. TA =2S'C, f = 1 MHz.

5-56

Switching Time Waveforms ~
Read Cycle (CEJPGM = VIL)
VIH~~~~~~----------------------~

ADDRESSES
VIL~~~~~~

VIH
OUTPUT ENABLE

VALID
________________________

VALID
~

tDH
- - (TAXGX)--

:==========t========\.

vIL----------~--------~~-------------------J
tOE
I-.-.- - -....-~(TGLGV)
tDF
tACC
(TGHGZ)

VOH-----------~~~Hi~-Z~--~(T~A~V~G!V)~--~..-J~------------------.,
OUTPUT
VOL--------------------------~

VALID
________________J

Hi-Z

Read Cycle (OE = VIL)
VIH~~~~~~----------------------~

ADDRESSES

VIL

VIH
CHIP ENABLE

~~~~r:i'~

VALID
______
______

VALID
~

===========t:=======4-

VIL---------~---------r~----------------'
tCE
too
----I--(TELGV)
(TEHGZ)

..

VOH----------~~--~~~----~----------------1
OUTPUT

Hi-Z
VOL--------------------------~

VALID
_ _ _ _ _ _ _ ___J

Hi-Z

Standby Power Down Mode (DE = VIL)
VIH======================~'--------------------------

ADDRESSES

VALID
VIL======================~~

VIH

------------r--------

VIL

-------------#

CHIP ENABLE

VALID
__________________________

STANDBY

STANDBY

too

(TEHGZ)

VOH~~~~~~~
OUTPUT

VOL

VALID FOR
CURRENT ADDRESS

Hi-Z

* Symbols in parentheses are proPos~d Industry standard_
5-57

VALID FOR
CURRENT ADDRESS

Hi-Z

PROGRAM OPERATION
DC Electrical Characteristics and Operating Conditions (Notes 1 and 2)
=25°C ± 5°C) (VCC =5V ± 5%, VPP =25V ± 1V)

(TA

Symbol

Typ

Min

Parameter

III

Input Leakage Current (Note 3)

VIL

Input Low Level

VIH

Input High Level

ICC

VCC Power Supply Current

IPP1
IPP2

-0.1

Max

Units

10

p.A

0.8

V

VCC+1

V

100

mA

VPP Supply Current (Note 4)'

5

mA

VPP Supply Current During
Programming Pulse (Note 5)

30

mA

2.0

AC Characteristics and Operating Conditions (Notes 1, 2, and 6)
(TA =25°C ± 5°C) (VCC =5V ± 5%, VPP =25V ± 1V)
Symbol
Parameter

Min

Typ

Max

Units

Alternate

Standard

t AS

TAVPH

Address Set·up Time

2

p's

tos

TGHPH

OE Set·up Time

2

p's

tos

TDVPH

Data Set·up Time

2

p's

tAH

TPLAX

Address Hold Time

2

p's

tOH

TPLGX

OE Hold Time

2

p's

tOH

TPLDX

Data Hold Time

2

tOF

TGHOZ

Chip Disable to Output Float
Delay (Note 4)

0

tCE

TGLOV

Chip Enable to Output Delay (Note 4)

tpw

TPHPL

Program Pulse Width

45

tpR

TPH1PH2

Program Pulse Rise Time

5

ns

tpF

TPL2PL1

Program Pulse Fall Time

5

ns

p's

130

50

ns

150

ns

55

ms

Note 1:' VCC must be applied at the same time or before VPP and removed after or at the same time as VPP. To prevent damage to the device it must not be inserted into a board with power applied.
Note 2: Care must be taken to prevent overshoot of the VPP supply when switching to + 25V.
Note 3: 0.45V"VIN,,5.25V
Note 4: CE/PGM = VIL, VPP = VCC
Note 5: VPP = 26V
Note 6: Transition times" 20 ns unless noted otherwise.
I

5-58

Timing Diagram *

Program Mode

VIH

===\--1--------+------....,

VIL

;;;;;;;;;;;;;;~1_------~------~

VIH

==::::::::::::=\

ADDRESSES

DATA

VIL===~

VIH

G

---r--t-r~;;;;---t-t-~

VIL

VIH

-------++

E/P
VIL ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;:;;;;;;:;:;:Jf
tPF
(TPLlPlI)

Functional Description
DEVICE OPERATION
The NMC27C16 has 3 modes of operation in the normal
system environment. These are shown in Table I.

Standby Mode (Power Down)
The NMC27C16 may be powered down to the standby
mode by making CE/PGM VIH. This is independent of 6E
and automatically puts the outputs in their Hi-Z state. The
power is reduced to 25% (132 mW max) of the normal
operating power. VCC and VPP must be maintained at 5V.
Access time at power up remains either tAcc or tCE (see
Switching Time Waveforms).

=

Read Mode

=

The NMC27C16 read operation requires that 6E VIL,
CE/PGM VIL and that addresses AO-A10 have been sta·
bilized. Valid data will appear on the output pins aftertACC'
tOE or tCE times (see Switching Time Waveforms) depend·
ing on which is limiting.

=

Deselect Mode
PROGRAMMING

=
=

The NMC27C16 is deselected by making 6E VIH. This
mode is independent of CEtPGM and the condition of the
addresses. The outputs are Hi-Z when 6E VI H. This
allows OR-tying 2 or more NMC27C16's for memory
expansion.

The NMC27C16 is shipped from National completely
erased. All bits will be at a "1" level (output high) in this
initial state and after any full erasure. Table II shows the 3
programming modes.

TABLE I. OPERATING MODES (VCC

=VPP =SV)

Pin Name/Number
Mode
Read
Deselect
Standby

CE/PGM
(ElP)
18

OE
(G)
20

Outputs
9-11,13-17

VIL
Don't Care
VIH

VIL
VIH
Don't Care

·DOUT
Hi-Z
Hi-Z

TABLE II. PROGRAMMING MODES (VCC = SV)
Pin Name/Number
Mode
Program
Program Verify
Program Inhibit

CE/PGM
(EiP)
18

OE
(G)

Pulsed VIL
to VIH
VIL
VIL

* Symbols In parentheses are proposed industry standard

.5-59

VPP
21

Outputs Q
9-11,13-17

VIH

25

DIN

VIL
VIH

25(5)
25

DOUT
Hi·Z

20

CD

.....
o

'"

,N

o
:E
z

. Functional Description (Continued)
Program Mode
unit while Inhibiting the program pulse to a unit will keep it
from being programmed and keeping 6E = VIH will put its
outputs in the Hi-Z state.

The NMC27C16 is programmed by introducing "O"s into
the desired locations. This is done 8 bits (a byte) at a time.
Any individual address, a sequence of addresses, or ad·
dresses chosen at random may be programmed. Any or all
of the 8 bits associated with an address location may be
programmed with a Single program pulse applied to the
chip enable pin. All input voltage levels, including the program pulse on chip enable are TIL compatible. The programming sequence is:

ERASING
The NMC27C16 is erased by exposure to high intensity Ultraviolet light through the transparent window. This exposure discharges the floating gate to its initial state
through induced photo current. It is recommended that
the NMC27C16 be kept out of direct sunlight. The UV content of sunlight may cause a partial erasure of some bits In
a relatively short period of time. Direct sunlight can also
cause temporary functional failure. Extended exposure to
room level fluorescent lighting will also cause erasure. An
opaque coating (paint, tape, label, etc.) should be placed
over the package window if this product is to be operated
under these lighting conditions.

With VPP = 25V, VCC = 5V, 6E = VIH and CE/PGM = VIL,
an address is selected and the desired data word is applied to the output pins. (VIL="O" and VIL="1" for both
address and data.) After the address and data Signals
are stable the program pin is pulsed from VIL to VIH
with a pulse width between 45 ms and 55 ms.
Multiple pulses are not needed but will not cause device
damage. No pins should be left opmn. A high level (VIH or
higher) must not be maintained longer than tpW(MAX)on the
program pin during programming. NMC27C16s may be
programmed in parallel with the same data in this mode.

An ultraviolet source of 2537A yielding a total integrated
dosage of 15 watt·seconds/cm 2 is required. This will erase
the part in approximately 15 to 20 minutes if a UV lamp
with a 12,000 p.W/cm 2 power rating is used. The NMC27C16
to be erased should be placed 1 inch away from the lamp
and no filters should be used.

Program Verify Mbde
The programming of the NMC27C16 may be verified either
1 word at a time during the programming (as shown in the
timing diagram) or by reading all of the words out at the
end of the programming sequence. This can be done with
VPP = 25V (or 5V) in either case.

An erasure system should be calibrated periodically. The
distance from lamp to unit should be maintained at 1 inch.
The erasure time is increased by the square of the distance (if the distance is doubled the erasure time goes up
by a factor of 4). Lamps lose intensity as they age. When a
lamp is changed, the distance is changed, or the lamp is
aged, the system should be checked to make certain full
erasure is occurring. Incomplete erasure will cause symptoms that can be misleading. Programmers, components,
and system designs have been erroneously suspected
when incomplete erasure was the basic problem.

Program Inhibit Mode
The program inhibit mode allows programming several
NMC27C16s simultaneously with different data for each
one by controlling which ones receive the program pulse.
All similar inputs of the NMC27C16 may be paralleled.
Pulsing the program pin (from VIL to VIH) will program a

5·60

~National

MOS EPROMs

~ Semiconductor

PRELIMINARY

NMC272416k·Bit (2k X 8) UV Erasable PROM
General Description

Features

The NMC2724 is a 16,384-bit EPROM operating from a
single 5V power supply. This device is an ultraviolet
erasable, electrically programmable, read only memory
fabricated using National's high speed, low power, silicon
gate technology.

• Single 5V power supply

This device is deselected when pin 18 is high and automatically placed in the standby mode. This mode provides an
80% reduction in power with no increase in access time.
The NMC2724 has an output enable control to eliminate
bus contention in microprocessor systems.

• Fullystatic
• TRI-STATE® output

• 450 ns max access time
•

Low power:
Active-150 mA max
Standby-3D mA max

• All 1/0 pinsTTLcompatible
• Pin compatible with existing EPROMs and ROMs
• Output enable control

Bits may be programmed at random, in sequence or singly. Typical erasure time is 20 minutes using a 12 mW/cm 2
ultraviolet lamp.

Block and Connection Diagrams·
Dual-In-Line Package
VCC

VPP

GND
(VSS)

! ! !
5V

o!NPP(G:~::

25V

rt----+-i~~1

~r_--~----~--_+t--------~
Y

D_EC_O_DE_R_ _

-t====~~

______~
Y.GATING

20

A3

19

A2

18

Al

17

AO
AU-AIO
ADDRESS
INPUTS

16

00(01)
16,384·B1T
CELL MATRIX

X
DECODER

°1(02)
02(03)
GNO(VSS)

10

15

11

14

12

13

Pin Name/Number
(E)

18

A9
ARt
OEIVPP(CIVPP)
AIO

mE)
07(08)
°6(07)
°5(06)
°4(05)
°3(04)

TOP VIEW

Modes*

Mode

AS

21

A4
OUTPUT BUFFERS

I

CE

VCC

22

A5

.....
TIR_co_L_ _ _

:'r-__

23

A6

GNO

=JL___C~_~G
~

24

A1
DATA OUTPUTS
00-01 (QI-08)

OE/VPP
(G/VPP)
20

VCC
24

Outputs
9-11,13-17

5V

DOUT

Read

VIL

VIL

Standby

VIH

Don't Care

5V

Hi-Z

Program

VIL

25V

DIN
DOUT
Hi-Z

Program Verify

VIL

VIL

5V
5V

Program Inhibit

VIH

25V

5V

* Symbols in parentheses are proposed industry standard.
tNMC2724A, AR '" VIL for all operating modes,
NMC2724B, AR2: VIH for all operating modes.

5-61

Order Number NMC2724Q-A
or NMC2724Q-B
See NS Package J24CQ
Pin Names*
CE(E)

Chip Enable

OE(G)

Output Enable

AD-A1O
0 0 -0 7 (01-08)
VPP

Address Inputs
Data Outputs
Program Power 25V

VCC

Power 5V

GND(VSS)
AR

Ground
Select Reference
Input Level

/

Absolute Maximum Ratings (Note 1)
Temperature under Bias

-10°Cto +80°C

Storage Temperature

-65°Cto + 125°C

All Input and Output Voltages
with Respect to VSS During Read

+ 6Vto - 0.3V

VPP Supply Voltage with Respect
to VSS During Programming

+ 26.5V to - 0.3V

Power Dissipation

1.5W

Lead Temperature(Soldering, 10 seconds) .

300°C·

I

READ OPERATION
DC Operating Characteristics (Note 2) .TA = O°C to 70°C, VCC = 5V ± 5%, VSS = OV
Parameter

Symbol

Conditions

Typ

Min

Max

Units

ILl1

Input Load Current

VIN = 5.25V

10

p.A

ILl2

OEIVPP Input Load Current

VIN =5.25V

300

p.A

ICC1

VCC Current Standby

CE = VIH, OE = VIL

15

30

mA

ICC2

VCC Current Active

OE=CE=VIL

85

150

mA

VIL

Input Low Voltage

VIH

Input High VoltagE!

VOL

Output Low Voltage

IOL=2.1 mA

VOH

Output High Voltage

IOH = - 400 p.A

-0.1
2.0

0.8

V

VCC+1

V

0.45
2.4

V
V

AC Characteristics TA =O°C to 70°C, VCC = 5V ± 5%, VSS = OV
Symbol
Alternate

Conditions

Parameter

Min

Typ

Max

Units

Standard

t ACC

TAVQV

Address to Output Valid

CE=OE=Vll

450

ns

tCE

TElQV

CE to Output Delay

OE= VIL

450

ns

tOE

TGlQV

Output Enable to Output Delay

CE=Vll

120

ns

tOF

TGHQZ

Output Enable High to Output Hi·Z

CE = Vil

0

100

ns

tOH

TAXQX

Address to Output Hold

CE = OE = Vil

0

t pF

TEHQZ

CE (E) to Output Hi·Z

OE = Vil

0

100

ns

ns

Capacitance (Note 3) TA = 25°C, f = 1 MHz
AC Test Conditions
Symbol
CIN1

Parameter
Input Capacitance Except CDE/VPP
(G/VPP)

Conditions
VIN =OV

CIN2

OE/VPP (GIVPP) Input Capacitance VIN =OV

COUT

Output Capacitance

Typ

Max

Units

4

6

pF

20

pF

12

pF

VOUT=OV

Output Load: 1 TTL gate and CL= 100 pF
Input Rise and Fall Times: ::;20 ns
Input Pulse Levels: 0.8V to 2.2V
Timing Measurement Reference Level:
Inputs
1Vand2V
Outputs 0.8V and 2V

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature

Range" they are not meant to Imply that the devices should be operated at these limits. The table of "Recommended DC Operating Conditions" provides con·
ditions for actual device operation.
Note 2: Typical values are forTA = 25'C and nominal supply voltages.
Note 3: Capacitance measured with Boonton Meter or effective capacitance calculated from the equation C = l~t/~V. Capacitance is guaranteed by periodic
testing.
5·62

Switching Time Waveforms·
Read Cycle(CE

=VIL)
VALID

VALID

ADDRESSES

__

tOH

__

(TAXQX)
VIH
VIL
1-_____-

..

VOH

....._1- tOE

(TGLQV)

Hi·Z

OUTPUT

Hi·Z

VALID

VOL

Read Cycle (OE (G)

=VI L)

VIH
ADDRESSES

VALID

VALID

tOH
- - (TAXQX)-VIH
VIL
tCE
tACC ~---+-(TELQV)
--(TAVnV)
Hi·Z

tpF
(TEHQZ)

--,_----------1

VOH
OUTPUT

Hi·Z

VALID

VOL

Standby Power Down Mode(OE = VIL)
VIH
ADDRESSES

VALID
VIL _ _ _ _ _ _ _ _ _ _ _ _ _...J

VALID

VIH
STANDBY

STANDBY
VIL

VOH
OUTPUT

-----..1

--

tpF.
-(TEHQZ)

VALID FOR

Hi·Z

CURRENT ADDRESS
VOL _____________
-T

* Symbols in parentheses are proposed industry standard.
5-63

VALID FOR
.CURRENT ADDRESS

Hi·Z

PROGRAM OPERATION
DC Characteristics TA=25°C±5°C, VCC=5V±5%, VPP=25V± 1V
Symbol

Parameter

Min

Conditions

III

Input Current All Inputs

VIN = VIL or VIH

VOL

Output Low Voltage During Verify

IOL=2.1 mA

VOH

Output High Voltage During Verify

IOH = -400 p.A

ICC

VCC Supply Current

VIL

Input Low Level All Inputs

VIH

Input High Level All Inputs Except OEIVPP

IPP

VPP Supply Current

Typ

Max

Units

10

p.A

0.45

V

2.4

V
85

-0.1
2.0

150

mA

0.8

V

VCC+1

V

30

mA

CE = VIL, OE = VPP

AC Characteristics TA=25°C±5°C, VCC=5V±5%
Symbol
Alternate

Parameter

Min

Conditions

Typ

Max

Units

Standard

tAS

TAVEL

Address Set-Up Tirne

2

tOES

TVPPHEL

Program Voltage Set-Up Time

2

p's

tos

TDVEL

Data Set-Up Time

2

p's

tAH

TEHAX

Address Hold Time

0

P.s

tOEH

TEHVPPL

OE Hold Time

2

P.s

tOH

TEHDX

Data Hold Time

2

p's

tOF

TEHOZ

Chip Enable to Output Hi-Z

tov

TELOV

Data Valid from CE

t pw

TELEH

CE Pulse Width During Programming

tVR

TVPPLEL

VPP Recovery Time

P.s

0

ns

120

OE=VIL
45

50

1

p's

55

ms

2

p's

Programming Waveforms· (Note4)TA=25°C±5°C, VCC=5V±5%, VPP=25V± 1V

..

ADDRESSES

")("

VIH
VIL

VIL

. .

tDS
(TDVEL)
VPP

_VIH
CE
VIL

Note 4:

K

ADD X + t

tAS
(TAVEL)
DATA IN STABLE
ADD X
tDH
(TEHDX)--

"

~k-

Hi-Z

"'lr DATA OUT VALID'

-,f-

--

--tpw
(TELEH)

tOES
(TVPPHEL)

•

..

tDV
(TELQV)-

.. f\.1\

ADD X

-

tAH
(TEHAX)--

tOEO
(TEHVPPL)

•

.1

tVR
(TVPPLEL)

~~

I/'f.

~

--

-~

\r

I!ENpp~e
VIL

PROGRAM
- - VERIFY - - - -

ADDRESS X

. .

I

VIH
DATA

.

PROGRAM

I\.....-...J

j
"

The Input timing reference level is 1V for VIL and 2V for VIH.

* Symbols In parentheses are proposed Industry standard.
5-64

Hi·Z

J
tDF

CTEonll

Functional Description
DEVICE OPERATION
The NMC2724 has two.modes of operation in the normal
system environment. These are shown in Table I.
TABLE I. OPERATING MODES (VCC = 5V)

~
Mode

Read
Standby

CE

(E)

OE/VPP
(G/VPP)

18

20

VIL
VIH

VIL
Don't Care

data). After the address and data signals are stable the
CE pin Is pulsed from VIH to VIL with a pulse width
between 45 ms and 55 ms.

*

ICC Max

Outputs

24

9·11,13-17

150 rnA
30 rnA

DOUT

Multiple pulses are not needed but will not cause device
damage. No pins should be left open. A low level, VIL or
lower must not be maintained steady state (DC signal) on
the CE pin during programming. Several NMC2724s may
be programmed in parallel (the same data In each one) in
this mode.
Program Verify

HI·Z

The programming of the NMC2724 may be verified, either
one word at a time during the programming (as shown in
the timingdiagram)orby reading all of the words out at the
end of the programming sequence.

Read Mode

=

The NMC2724 read operation requires that CE VIL, and
OE/VPP VIL and that addresses AO-A1O have been
stabilized. Valid data will apear on the output pins after
tAcc, tOE, or tCE times (see Switching Time Waveforms)
depending on which is limiting.

=

Program Inhibit
The program inhibit mode allows programming several
NMC2724s in parallel with different data for each one by
controlling which ones receive the program pulse. All
similar inputs may be paralleled. Pulsing the CE pin from
VIH to VIL on a selected unit or units will cause program·
ming, while inhibiting the CE pulse will inhibit programming and keep the outputsof the inhibited devices in
the Hi·Z state.

Standby Mode
The NMC2724 is placed in the standby mode (deselected
and powered down) by making CE VIH. This is inde·
pendent of the Output Enable control and automatically
controls the outputs to their Hi·Z state. The power dissipa'
tion is reduced to 20% of the normal operating power. VCC
must be kept at 5V. Access time at power up (chip selec·
tion) remains either tAce or tCE (see Switching Time
Waveforms).

=

ERASURE PROCEDURE
The NMC2724 is erased by exposure to high intensity ultraviolet light through the transparent window. This exposure discharges the floating gates to their initial state
through induced photo current. It is recommended that
this device be kept out of direct sunlight. The UV content
of sunlight may cause the a partial erasure of some bits In
a relatively short period of time. Direct sunlight (any in·
tense light) can cause temporary functional failure due to
generation of photo currents. Extended exposure to room
level fluorescent lighting will also cause erasure. An
opaque coating (paint, tape, label, etc.) should be placed
over the package window if this product is to be operated
. under these lighting conditions.

PROGRAMMING
The NMC2724 is shipped from National completely
erased. All bits will be at a "1" level (outputs high) in this in·
itial state after any full erasure. Table II shows the three
programming modes.
TABLE II. PROGRAMMING MODES (VCC = 5V)

X
Mode

Program
Program Verify
Program Inhibit

*

CE
(E)

OE/VPP
(G/VPP)

18

20

9·11,13-17

VIL
VIL
VIH

25V
VIL
25V

DIN
DOUT
Hi·Z

Outputs

An ultraviolet source of 2537A yielding a total integrated
dosage of 15 Watt·seconds/cm 2 is required. This will erase
a unit in approximately 15t020 minutes when aUV lampof
a 12 mW/cm 2 power rating is used. The NMC2724 to be
erased should be placed one inch away from the lamp and
no fiiters should be used.

Program Mode
The N MC2724 is programmed by placing "O"s into the desired locations. This isdone8 bits(a byte) at a time. Any individual address, a sequence of addresses, or addresses
chosen at random may be programmed. Any or all of the 8
bits associated with an address location may be programmed with a single program pulse applied to the CE
pin. All input voltage levels, including the program pulse
on the CE pin are TIL compatible. The programming
sequence is:

An erasure system should be calibrated periodically. The
distance from lamp to unit should be maintained at one
inch. The erasure time increases as the square of the
distance. (If distance is doubled the erasure time in·
creases by a factor of 4.) Lamps lose intensity as they age.
When a lamp is changed, the distance has changed or the
lamp has aged, the system should be checked to make
certain full erasure is occurring. Incomplete erasure will
cause symptoms that can be misleading. Programmers,
components, and even system designs have been er·
roneously suspected when incomplete erasure was the
problem.

=

With the OEIVPP pin at 25V and VCC 5V, an address is
selected and the desired data word is applied to the out·
put pins (VIL "0" and VIH "1" for both address and

=

=

* Symbols in parentheses are proposed industry standard.
5·65

~National

MOS EPROMs
PRELIMINARY

D Semiconductor
NMC2732 32k·Bit (4k x 8) UV Erasable PROM
General Description

Features

1he NMC2732 is a 32,768-bit EPROM operating from a
single 5V power supply. This device is ,an ultraviolet
erasable, electrically programmable, read only memory
fabricated using National's high speed, low power, silicon
gate technology.

• Single 5V power supply
• 450 ns max access time
• Low power:
Active-150 mA max
Standby-30 mA max

This device is deselected when pin 18 is high and automatically placed in the standby mode. This mode provides an
80% reduction in power with no increase in access time.
1he NMC2732 has an output enable control to eliminate
bus contention in microprocessor systems.

•
•
•
•
•

Bits may be programmed at random, in sequence or singly. Typical erasure time is 20 minutes using a 12 mW/cm 2
ultraviolet lamp.

Fully static
TRI-STATE® output
All 1/0 pins TTL compatible
Pin compatible with existing EPROMs and ROMs
Output enable control

Block and Connection Diagrams*
Dual-In-Line Package
VCC

VPP

GND
(VSS)

5V

25V

24

A7

! ! !

DATA OUTPUTS
00-07 (01-08)

GND

23

A6

22

A5
CONTROL
LOGIC

'21

A4
OUTPUT 8UFFERS

19

A2

18

Al

17

AD

----.
----.
----.
----.
---+

16

00(01)

X
DECODER

32.768·BIT
CELL MATRIX

0,(02)
02(03)
GND(VSS)

AS
A9
All

20 ilEIVPP(ilIVPP)

A3

AO-Al1
ADDRESS
INPUTS

VCC

10

15

11

14

12

13

AID

mE)
°7(OS)
06(07)
05(06)
04(05)
03(04)

TOPVIEW

Order Number NMC2732Q
See NS Package J24CQ

Modes*
CE
Mode

(E)

18
Read
Standby
Program
Program Verify
Program Inhibit

VIL
VIH
VIL
VIL
VIH

, Pin Name/Number
OE/VPP
VCC
(G/VPP)
24
20
VIL
Don't Care
25V
VIL
25V

5V
5V
5V
5V
5V

Pin Names*
Outputs
9-11,13-17
DOUT
Hi-Z
DIN
DOUT
Hi-Z

* Symbols in parentheses are proposed industry standard.-

5-66

CE (E)
OE (G)
AO-A11
0 0-0 7 (01-08)
VPP
VCC
GND(VSS)

Chip Enable
Output Enable
Address Inputs
Data Outputs
Program Power 25V
Power5V
Ground

Absolute Maximum Ratings (Note 1)
Temperature under Bias

-10°Cto +80·C

Storage Temperature

-65·Cto + 125·C

All Input and Output Voltages
with Respect to VSS During Read

+6Vto -0.3V

VPP Supply Voltage with Respect
to VSS During Programming

+ 26.5V to - 0.3V

Power Dissipation

1.5W
300·C

Lead Temperature (Soldering, 10 seconds)

,

READ OPERATION
DC Operating Characteristics (Note 2)

TA = O·C to 70·C, VCC = 5V ± 5%, VSS = OV

Symbol

Conditions

Max

Units

ILl1

Input Load Current

Parameter

VIN = 5.25V

10

p,A

ILl2

OEIVPP Input Load Current

VIN = 5.25V

300

p,A

ICC1

VCC Current Standby

CE = VIH, OE = VIL

15

30

mA

OE=CE=VIL

85

150

mA

0.8

V

ICC2

VCC Current Active

VIL

Input Low Voltage

VIH

Input High Voltage

VOL

Output Low Voltage

IOL=2.1 mA

VOH

Output High Voltage

IOH = -400p,A

Typ

Min

-0.1
2.0

VeC+1

V

0.45

V

2.4

V

AC Characteristics TA =o·c to 70·e, vcc =5V ± 5%, VSS =OV
Symbol

Max

Units

CE=OE=VIL

450

ns

OE = VIL

450

ns

=VIL

120

ns

100

ns

Parameter

Conditions

Min

Alternate

Standard

t ACC

TAVQV

Address to Output Valid

tCE

TELQV

CE to Output Delay

tOE

TGLQV

Output Enable to Output Delay

CE

tDF

TGHQZ

Output Enable High to Output Hi·Z

CE= VIL

0

tOH

TAXQX

Address to Output Hold

CE = OE= VIL

0

tpF

TEHQZ

CE (E) to Output Hi·Z

OE=VIL

0

Typ

ns
100

ns

Capacitance (Note 3) TA =25·C, f = 1 MHz
Symbol

Parameter

Conditions

AC Test Conditions

Typ

Max

Units

4

6

pF

CIN1

Input Capacitance Except OE/vPP
(G/VPP)

CIN2

OE/vPP (G/VPP) Input Capacitance VIN=OV

20

pF

COUT

Output Capacitance

12

pF

VIN =OV

VOUT=OV

Output Load: 1 TIL gate and CL= 100 pF
Input Rise and Fall Times: :520 ns
Input Pulse Levels: O.BV to 2.2V
Timing Measurement Reference Level:
Inputs
1Vand2V
Outputs 0.8V and 2V

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature
Range" they are not meant to imply that the devices should be operated at these limits. The table of "Recommended DC Operating Conditions" provides con·
ditions for actual device operation.
Note 2: Typical values are for TA = 25'C and nominal supply voltages.
Note 3: Capacitance measured with Boonton Meter or effective capacitance calculated from the equation C = IAt/AV. Capacitance is guaranteed by periodic
testing.
5-67

Switching Time Waveforms·
Read Cycle (CE = VIL)
VIH
ADDRESSES

VALID

VALID
__

VIH

tOH

__

(TAXnX)

------i-----"'\.

--+-----

VIL

VOH

Hi·Z

OUTPUT

Hi·Z

VALID

VOL

Read Cycle (OE(G) = VIL)
'"\

VIH
ADDRESSES

VALID

VALID
VIL

tOH
- - (TAXnX)-VIH

CE
VIL
tCE
~---t-(TELQV)

1-

VOH

Hi·Z

OUTPUT

tpF
(TEHQZ)
Hi·Z

VALID

VOL

Standby Power Down Mode (OE = VIL)
VIH
ADDRESSES VIL __________________________
VALID
-'

VALID

VIH
VIL

VOH
OUTPUT

-----

--

STANDBY

STANDBY
tpF
-(TEHQZ)

VALID FOR
CURRENT ADDRESS - J
VOL ______________

Hi·Z

* Symbols In parentheses are proposed Industry standard.
5-68

VALID FOR
CURRENT ADDRESS

Hi·Z

PROGRAM OPERATION
DC Characteristics TA=25°C±5°C, VCC=5V±5%, VPP=25V± 1V
Symbol

Parameter
Input Current All Inputs

VIN = VIL or VIH

VOL

Output Low Voltage During Verify

IOL=2.1 mA

VOH

Output High Voltage During Verify

IOH = -400p.A

ICC

VCC Supply Current

VIL

Input Low Level All Inputs

VIH

Input High Level All Inputs Except OEIVPP

IPP

VPP Supply Current

Typ

Min

Conditions

III

Max

Units

10

p.A

0.45

V

2.4

V
85

-0.1
2.0

150

rnA

0.8

V

VCC+1

V

30

rnA

CE = VIL, OE = VPP

AC Characteristics TA=25°C±5°C, VCC=5V±5%
Symbol
Alternate

Parameter

Conditions

Min

Typ

Units

Max

Standard

t AS

TAVEL

Address Set·Up Time

2

P.s

~OES

TVPPHEL

Program Voltage Set-Up Time

2

P.s

tos

TDVEL

Data Set-Up Time

2

p's

tAH

TEHAX

Address Hold Time

0

p's

tOEH

TEHVPPL

OE Hold Time

2

P.s

tOH

TEHDX

Data Hold Time

2

p's

tOF

TEHQZ

Chip Enable to Output Hi-Z

tov

TELQV

Data Valid from CE

t pw

TELEH

CE Pulse Width During Programming

45

tVR

TVPPLEL

VPP Recovery Time

2

Programming Waveforms·

VIH

'\.

VIL

I

•

PROGRAM

)(

.

VIH

IDS
(TDVEL)

..

...

tpw
(TELEH)

tOES

Note 4:

ms

)(

tOEH

-----

...(TVPPHEL)..

..(TEHVPPL)..

tDV
(TELUV)-

I

\~

'----I

The input timing reference level Is 1V for VIL and 2V for VIH.

* Symbols In parentheses are proposed Industry standard.

5-69

-- -

tAH
(TEHAX)--

\.

~~

f\

...,'- DATAOUTVALID
ADD X
-'.-

~

iiElVPP

_VIH
CE
VIL

55

'
PROGRAM
-VERIFY--

Hi·Z

~

---\r

tDH
(TEHDX)--

VPP~{
VIL

P.s

ADD X + 1

lAS
(TAVEL)
DATA IN STABLE
ADD X

VIL

ns

1

p's

ADDRESS X

...
DATA

50

120

(Note4)TA=25°C±5°C, VCC=5V±5%, VPP=25V±1V

.
ADDRESSES

0
OE=VIL

tVR
(TVPPlEL)

,

~

Hi·Z

tDF

I~EH.l'

Functional Description
DEVICE OPERATION
The NMC2732 has two modes of operation in the normal
system environment. These are shown in Table I.

data). After the address and data signals are stable the
CE pin is pulsed from VIH to VIL with a pulse width
between 45 ms and 55 ms.
Multiple pulses are not needed but will not cause device
damage. No pins should be left open. A low level, VIL or
lower must not be maintained steady state (DC signal) on
the CE pin during programming. Several NMC2732s may
be programmed in parallel (the same data in each one) in
this mode.

TABLE I. OPERATING MODES (VCC = 5V)*

~
Mode

Read
Standby

CE

(E)
18

OE/VPP
(G/VPP)
20

VIL.
VIL
VIH
Don't Care

ICC Max
24

Outputs
9·11,13-17

150 rnA
30mA

DOUT
Hi-Z

Program Verify
The programming of the NMC2732 may be verified, either
one word at a time during the programming (as shown in
the timing diagram) or by reading all of the words out at the
end of the programming sequence.

Read Mode

=

The NMC2732 read operation requites that CE VIL, and
OEIVPP VIL and that addresses AO-A11 have been
stabilized. Valid data will apear on the output pins after
t ACC ' tOE, or tCE times (see Switching Time Waveforms)
depending on which is limiting.

=

Program Inhibit
The program inhibit mode allows programming several
NMC2732s in parallel with different data for each one by
controlling which ones receive the program pulse. All
similar inputs may be paralleled. Pulsing the CE pin from
VIH to VIL on a selected unit or units will cause program·
ming, while inhibiting the CE pulse will inhibit programming and keep the outputs of the inhibited devices in
the Hi·Z state.

Standby Mode
The NMC2732 is placed in the standby mode (deselected
and powered down) by making CE = VIH. This is independent of the Output Enable control and automatically
controls the outputs to their Hi-Z state. The power dissipation is reduced to 20% of the normal operating power. VCC
must be kept at 5V. Access time at power up (chip selection) remains either tAcc or tCE (see Switching Time
Waveforms).

ERASURE PROCEDURE
The NMC2532 is erased by exposure to high intensity ul$raviolet light through the transparent window. This exposure discharges the floating gates to their initial state
through induced photo current. It is recommended that
this device be kept out of direct sunlight. The UV content
of sunlight may cause the a partial erasure of some bits in
a relatively short period of time. Direct sunlight (any intense light) can cause temporary functional failure due to
generation of photo currents. Extended exposure to room
level fluorescent lighting will also cause erasure. An
opaque coating (paint, tape, label, etc.) should be placed
over the package window if this product is to be operated
under these lighting conditions.

PROGRAMMING
The NMC2732 is shipped from National completely
erased. All bits will be at a "1" level (outputs high) in this initial state after any full erasure. Table II shows the three
programming modes.
TABLE II. PROGRAMMING MODES (VCC = 5V) *

X

CE
18

OE/VPP
(G/VPP)
20

Outputs
9-11,13-17

VIL
VIL
VIH

25V
VIL
25V

DIN
DOUT
Hi-Z

(E)

Mode

Program Mode

An ultraviolet source of 2537..\ yielding a total integrated
dosage of 15 Watt-seconds/cm 2 is required. This will erase
a unit in approximately 15t020 minutes when a UV lampof
a 12 mW/cm 2 power rating is used. The NMC2732 to be
erased should be placed one inch away from the lamp and
no filters should be used.

The NMC2732 is programmed by placing "O"s into the desired locations. This is done 8 bits (a byte) at a time. Any individual address, a sequence of addresses, or addresses
chosen at random may be programmed. Any or all of the 8
bits associated with an address location may be programmed with a single program pulse applied to the CE
pin. All input voltage levels, including the program pulse
on the CE pin are TTL compatible. The programming
sequence is:
With the OEIVPP pin at 25V and VCC = 5V, an address is
selected and the desired data word is applied to the output pins (VIL "0" and VIH "1" for both address and

An erasure system should be calibrated periodically. The
distance from lamp to unit should be maintained at one
inch. The erasure time increases as the square of the
distance. (If distance is doubled the erasure time increases by a factor of 4.) Lamps lose intenSity as they age.
When a lamp is changed, the distance has changed or the
lamp has aged, the system should be checked to make
certain full erasure is occurring. Incomplete erasure will
cause symptoms that can be misleading. Programmers,
components, and even system designs have been erroneously suspected when incomplete erasure was the
problem.

Program
Program Verify
Program Inhibit

=

=

.. Symbols In parentheses are proposed Industry standard.

5-70

Section 6
Bipolar PROMs

High speed microcontrol storage is made practical at
very low cost through the use of National's bipolar
PROMs. This generic family utilizes the latest in
Schottky circuitry and Titanium-Tungsten fuse link
technology. National offers these and other memory
and logic products for state-of-the-art solutions to
data processing and control logic design problems.
Refer to National's Memory Applications Handbook
for suggestions on how to use these devices
effectively.

Schottky
PROMs

~National

a

Bipolar PROMs

Semiconductor

DM54S188/DM74S188 256·Bit (32 x 8)
Open·Coliector PROM
DM54S288/DM74S288 256·Bit (32 x 8)
TRI·STATE® PROM
General Description

Features

These Schottky PROM memories are organized in the
popular 32 words by 8 bits configuration. A memory
enable input is provided to control the output states.
When the enable input is in the low state, the outputs
present the contents of the selected word.

.. Advanced titanium-tungsten (Ti-W) fuses

.. Schottky-clamped for high speed
Address access-35 ns max
Enable access-25 ns max

If the enable input is raised to a high level, it causes all
8 outputs to go to the "OFF" or high impedance state.
The memories are available in both open-collector and
TRI-STATE® versions and are available as ROM's as
well as PROM's,

.. PNP inputs reduce input loading

.. All dc and ac parameters guaranteed over temperature

PROM's are shipped from the factory with lows in all
locations. A high may be programmed into any selected
location by following the programming instructions.
Once programmed, it is impossible to go back to a low.

.. Low voltage TRI-SAFE ™ programming

See the last page of this section for detailed programming information.

.. Board level programming

Commercial

OpenCollector

DM74S,188

X

X

DM74S288

X

Military

DM54S188

X

DM54S288

X

TRI-STATE

Package

X

N, J

N, J

X

J
X

Block Diagram

J

Connection Diagram
Dual-I n-Line Package
16

01
03

A3
. Al

IS6·BIT ARRAY
31 X881T
MEMQRYMATRIX

2

Vee

"n

3

04
05

AD

5

12 A2

06
10 AD

08

05

04

03

01

01

Logic Symbol
Order Number DM54S188J, DM54S288J,
DM74S188J or DM74S288J
See NS Package J16A
Order Number DM74S188N or DM74S288N
See NS Package N16A

6-3

Absolute Maximum Ratings
Supply Voltage (Note 2)
Input Voltage (Note 2)
Output Voltage (Note 2)
Storage Temperature
Lead Temperature (Soldering, 10 seconds)

Operating Conditions

(Note 1)

-{).5V to +7V
-l.2V to +5.5V
--o.5V to +5.5V
~5°C to +150°C
300°C

DC Electrical Characteristics

Supply Voltage (Vee)
DM54S188, Dry154S288
DM74S188, DM74S288
Ambient Temperature ITA)
. DM54S188, DM54S288
DM74S188, DM74S288

IIH

4.5
4.75

5.5
5.25

V
V
°c
°c

+125
+70

Logical "0" Input Voltage (Low)

0

0.8

V

Logical "1" Input Voltage (High)

2.0

5.5

V

(Note 3)

MIN

Input Leakage Current, All Inputs

UNITS

-55
0

DM54S188,54S288

Input Load Current, All Inputs

MAX

DM74S188,74S288

CONDITIONS

PARAMETER
IlL

MIN

TYP
-80

VCC = Max, VIN = 0.45V

MAX

MIN

-250

TYP
-80

MAX
-250·

UNITS
IlA

VCC = Max, VIN = 2.7V

25

25

IlA

Input Leakage Current, All Inputs

VCC= Max, VIN = 5.5V

1.0

1.0

mA

VOL

Low Level Output Voltage

VCC = Min, IOL = 16 mA

VIL

Low Level Input Voltage

VIH

High Level Input Voltage

ICE X

Output Leakage Current

VCC = Max, VCEX

0.35

0.35

0.5
0.80

= 2.4V

(Open·Coliector Only) (Note 5)

VCC = Max, VCEX = 5.5V

Input Clamp Voltage

VCC = Min, liN = -18 mAo

CIN

Input Capacitance

Vec = 5V, VIN

Co

Output Capacitance

VCC = 5V, Vo = 2V, TA = 25°C,

V
V

50
100
--{J.B

= 2V, T A = 25°C,

V

0.80
2.0

2.0

Vc

0.45

-1.2

--{J.8

50

IlA

100

Il A

-1.2

V

4.0

4.0

pF

6.0

6.0

pF

1 MHz

1 MHz, Output "OFF"
ICC

Power Supply Current

VCC

= Max, All Inputs Grounded,

70

110

70

110

mA

All Outputs Open
TRI-STATE PARAMETERS
ISC

Output Short Circuit Current

Vo = OV, VCC

= Max, (Note 4)

-20

-70

~20

-70

mA

±50

IlA

(Note 5)
1HZ

Output Leakage (TRI-STATE)

VCC

= Max, Vo = 0.45 to 2.4V,

±50

Chip Disabled
VOH

Output Voltage High, (Note 5)

IOH

= -2 mA

2.4

3.2

V

IOH = -6.5 mA

AC Electrical Characteristics

2.4

V

(With standard (oad)

DM54S188,54S288
PARAMETER

3.2

DM74S188,74S288

5V ±10%;-55°Cto+125°C 5V ±5%; O°C to +70°C

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

tAA

Address Access Time

22

45

22

35

ns

tEA

Enable Access Time

15

30

15

20

ns

tER

Enable Recovery Time

15

35

15

25

ns

Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that the device
may be operated at these values.
Note 2: These limits do not apply during programming. For the programming ratings, refer to the programming instructions.
Note 3: These limits apply over the entire operating range unless stated otherwise. All typical values are for VCC = 5V and T A = 25°C.
Note 4:

During ISC measurement, only one output at a time should be grounded. Permanent damage may otherwise result.

Note 5: To measure VOH, ICEX or ISC on an unprogrammed part, apply 10.5V to either AO (pin 10) or A4 (pin 14).

6-4

~National

Bipolar PROMs

~ Semiconductor
DM54S287/DM74S287 1024·Bit (256 x 4)
TRI·STATE® PROM
DM54S387/DM74S387 1024·Bit (256 x 4)
Open·Collector PROM
General Description

Features

These Schottky memories are organized in the popular
256 words by 4 bits configuration. Two memory enable
inputs are provided to control the output states. When
both enable inputs are in the low state, the outputs
present the contents of the selected word.

•

Advanced titanium-tungsten -(Ti-W) fuses

•

Schottky-clamped for high speed
Address access-50 ns max
Enable access-25 ns max

•

PNP inputs reduce input loading

•

All dc and ac parameters guaranteed over temperature

•

Low voltage TRI-SAFETM programming

•

Board le~el programming

•

ROM mates are DM74S187 and DM85S97

If either or both of the enable inputs is raised to a high
state, it causes all four outputs to go to the "OF F" or
high impedance state. The memories are available in
both open-collector and TR I-STATE versions and are
available as ROM's as well as PROM's.
PROM's are shipped from the factory with lows in all
locations. A high may be programmed into any selected
location by following the programming instructions.
Once programmed, it is impossible to go back to a low.
See the last page of this section for detailed programming information.
Military

DM74S287
DM54S387

Open·
Collector

X
X

DM74S387

DM54S287

Commercial

TRI·STATE

Package

X

N, J

X

J

X

N, J

X

X
X

J

Connection Diagram

Block Diagram

Dual-In-Line Package
MOST SIGNIFICANT
AOORESS BIT

A6

~

A5

A7

16
VCC
15

A4

A6

1014·BIT CEll
32 X 32·BIT
MEMORY MATRIX

AS
A4

A3

A3

TOP VIEW

Logic Symbol
01
02
03
02

04

01

Order Number DM54S287J. DM54S387J,
DM74S287J or DM74S387J
See NS Package J16A

A7

Order. Number DM74S287N or DM74S387N
See NS Package N16A

6-5

01
02
03
04

Al

03

n

10

A2
GNo

AD

13

11

Al

A2

n

12

AD

A7

14

"en
"
C

CO

Absolute Maximum Ratings

~

Supply Voltage (Note 2)
Input Voltage (Note 2)
Output Voltage (Note 2)
Storage Temperature
lead Temperature (Soldering, 10 seconds)

('I)

~

r::::
CO

Operating Conditions

(Note 1)

--{).5V to +7V
-1.2V to +5.5V
--{).5V to +5.5V
-65°C to +150°C
300°C

Supply Voltage (VCC)
DM54S387, DM54S287
DM74S387, DM74S287
Ambient Temperature (TA)
DM54S387, DM54S287
DM74S387, DM74S287

('I)

en

MIN

MAX

UNITS

4.5
4:75

5.5
5.25

V
V

-55
0

+125
+70

°c
°c

Logical "0" Input Voltage (Low)

0

0.8

V

Logical "1" Input Voltage (High)

2.0

5.5

V

~
Lt)

~

C

"
en
"C~

DC Electrical Characteristics
PARAMETER

CO
N
~

r::::

CO
N

~
Lt)
~

C

(Note 3)

CONDITIONS

DM54S387/54S287
MIN

TYP

MAX

DM74S387/74S287
MIN

TYP

UNITS
MA?<

IF

Input load Current, All Inputs

VCC = Max, VF = 0.45V

IR

Input Leakage Current, All Inputs

VCC = Max, VR = 2.7V

25

25

/lA

IRB

Input Leakage Current, All Inputs

,VCC = Max, VRB = 5.5V

1.0

1.0

mA

VOL

Low Level Output Voltage

VIL

Low Level Input Voltage

VIH

High Level Input Voltage

ICEX

Output Leakage Current

VCC = Max, VCEX ~ 2.4V

-80

VCC = Min, IOL = 16 mA

0.35

-250

-80

0.5

-250

0.35

0.80
2.0

(Open·Collector Only) (Note 5)

VCC = Max, VCEX = 5.5V

Vc

Input Clamp Voltage

VCC = Min, liN = -18 mA

CIN

Input Capacitance

VCC = 5V, VIN = 2V, TA = 25°C,

Co

Output Capacitance

VCC = 5V, Vo = 2V, TA = 25°C,

0.45

V

0.80

V

2.0

V

50
100
-0.8

-1.2

JlA

-0.8

50

/lA

100

/lA

-1.2

V

4.0

4.0

pF

6.0

6.0

pF

1 MHz

1 MHz, Output "OFF"
ICC

Power Supply Current

VCC = Max, All Inputs Grounded,

80

130

80

130

mA

All Outputs Open
TRI·STATE PARAMETERS
ISC

Output Short Circuit Current

Vo = OV, VCC = Max, (Note 4)

1HZ

Output Leakage (TR I·ST ATE)

VCC = Max, Vo = 0.45 to 2.4V,

-20

-70

-20

±50

-70

mA

±50

/lA

Chip Disabled
VOH

Output Voltage High, (Note 5)

IOH = -2 mA

2.4

V

3.2

IOH = -6.5 mA

AC Electrical Characteristics

PARAMETER

2.4

3.2

V

(With standard load)

CONDITIONS

tAA

Address Access Time

(Figure 1)

tEA

Enable Access Time

(Figure 2)

tER

Enable Recovery Time

(Figure 2)

DM54S387/54S287

DM74S387/74S287

5V ±10%;-55°C to +125°C

5V ±5%; o°c to +70 C

MIN

TYP

10

35
15
15

30

5

MAX

o

UNITS

MIN

TYP

60

10

35

50

ns

30

5

15

25

ns

5

15

25

ns

MAX

Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do n'ot mean that the device
may be operated at these values.
Note 2: These limits do not apply during programming. For the programming ratings, refer to the programming instructions.
Note 3: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vce = 5V and T A
Note 4: During ISC measurement. only one output at a time should be grounded. Permanent damage may otherwise result.
Note 5: To measure VOH or ICEX on an unprogrammed part, apply 10.5V to both A7 and A2 (pin 15 and pin 7).

6·6

= 25°C.

Standard Test Load
•

Input waveforms are supplied by a pulse generator
having the following characteristics: PRR = 1 MHz,
ZOUT = 50n. tr ~ 2.5 ns and tf ~ 2.5 ns (between
1.0V and 2.0V).
• tAA is measured with both enable inputs at a steady
low level.
• tEA and tER are measured from the 1.5V on inputs and outputs with all address inputs at a steady
level and with the unused enable input at a steady
low leve)f

Vee

MEMORY

O~J~~~ 0-+---...,

T

TEST

600

eL =30 PF*

* CL includes probe and jig capacitance.

Switching Time Waveforms
JV
ADDRESS INPUT

t.5V

ENABLE INPUT

OV

t.5V

OUTPUT

OUTPUT

FIGURE 1. Address Access Time

FIGURE 2. Enable Access Time and Recovery Time

Typical Performance Characteristics
Typical Switching Characteristics
as a Function of Temperature
(VCC = 5V. Standard Load)

Typical Switching Characteristics
as a Function of VCC (TA = 25°C.
Standard Load)
40

50

t~A- --

.......

40

-I--

--

-

tAA

~

30

30

:g

:g
i=

20
tEA

i=

20

tEA

~

tER

--I--

10

10
tER

o
-55

125

25
TA AMBIENT TEMPERATURE

4.5

re)

5.0

5.5

SUPPLY VOLTAGE (V)

Equivalent Circuits
Equivalent of Each Input

, Typical TRI-STATE Output

vee

Vee

INPUTo--. . .--t

......~H...-oOUTPUT

6-7

Typical Open-Collector Output

-~'"""'

~National

a

Bipolar PROMs

Semiconductor

DM54S473/DM74S473 4096·Bit (512 x 8)
Open·Coliector PROM
DM54S472/DM74S472 4096·Bit (512 x 8)
TRI·STATE® PROM
General Description

Features

These Schottky PROM memories are organized in the
popular 512 words by 8 bits configuration. A memory
enable input is provided to control the output states.
When the enable input is in the low state, the outputs
present the contents of the selected word.

•

• Schottky-clamped for high speed
Address access-60 ns max
Enable access-30 ns max

If the enable input is raised to a high level, it causes all
8 outputs to go to the "OFF" or high impedance state.
The memories are available in both open-collector and
TRI-STATE versions.

PROM's are shipped from the factory with lows in all
locations. A high may be programmed into any selected
location by following the programming instructions.
Once programmed, it is impossible to go back to a low.
See the last page of this section for detailed programming information.
Military

Advanced titanium-tungsten (Ti-W) fuses

•

PNP inputs reduce input loading

•

All dc and ac parameters guaranteed over temperature

•

Low voltage TRI-SAFETM programming

•

Board level programming

•

High density 20-pin package

Commercial

OpenCollector

X

X

X

DM74S472
DM54S473

X

DM54S472

X

TRI-STATE

Package

X

N, J

N,J
J

X
X

Block Diagram

J

Connection Diagram
Dual-I n·Line Package
Vee

4096·BITARRAY
64X64B1T

MEMORY MATRIX

16 AS

IS

n'

02

06
GNO

10 L-.._ _ _ _ _-'
TQPVIEW

Logic Symbol
Order Number DM54S472J, DM54S473J,
DM74S472J or DM74S473J
See NS Package J20B
Order Number DM74S472N or DM74S473N
See NS Package N20A

6-8

01

02

05

Absolute Maximum Ratings
Supply Voltage (Note 2)
Input Voltage (Note 2)
Output Voltage (Note 2)
Storage Temperature
Lead Temperature (Soldering, 10 seconds)

Operating Conditions

(Note 1)

--{).5V to +7V
-1.2V to +5.5V
--{).5V to +5.5V
o
---o5°e to +150 e
300°C

DC Electrical Characteristics

MIN

MAX'

4.5
4.75

5.5
5.25

V
V

-55
0

+125
+70

°e
°e

Logical "0" Input Voltage (Low)

0

0.8

V

Logical "1" Input Voltage (High)

2.0

5.5

V

Supply Voltage (Vee)
DM54S473, DM54S472
DM74S473, DM74S472
Ambient Temperature (TA)
DM54S473, DM54S472
DM74S473, DM74S472

(Note 3)
DM54S473.54S472

DM74S473,74S472

CONDITIONS

PARAMETER

UNITS

MIN

TYP
-80

MAX

MIN

-250

TYP.
-80

MAX
-250

UNITS

IlL

Input Load Current, All Inputs

Vee = Max, VIN = O.45V

IIH

Input Leakage Current, All Inputs

Vee = Max, VIN = 2.7V

25

25

p,A

II

Input Leakage Current, All Inputs

Vee = Max, VIN = S.SV

1.0

1.0

rnA

VOL

Low Level Output Voltage

VCC = Min, IOL = 16 rnA

VIL

Low Level Input Voltage

VIH

High Level Input Voltage

ICE X

Output Leakage Current

VCC = Max, VCEX = 2.4V

(Open·Coliector Only) (Note 5)

VCC = Max, VCEX = 5.5V

Vc

Input Clamp Voltage

VCC = Min, liN = -18 rnA

CIN

Input Capacitance

VCC = 5V, VIN = 2V, TA = 25°C,

Co

Output Capacitance

VCC = 5V, Vo = 2V, T A = 25°C,

0.35

0.35

0.5
0.80

0.45

V

0.80

V

2.0

2.0

V

50
100
-0.8

-0.8

-1.2

p,A

50

p,A

100

p,A

-1.2

V

4.0

4.0

pF

6.0

6.0

pF

1 MHz

1 MHz, Output "OFF"
ICC

Power Supply Current

VCC = Max, All Inputs Grounded,

120

120

155

155

rnA

All Outputs Open
TRI-STATE PARAMETERS
ISC

Output Short Circuit Current

Vo = OV, VCC = Max, (Note 4)

-20

-70

-20

-70

rnA

±50

I1A

(Note 5)
1HZ

Output Leakage (TRI-STATE)

±50

VCC = Max, Vo = 0.45 to 2.4V,
Chip Disabled

VOH

Output Voltage High, (Note 5)

2.4

IOH = -2 rnA

3.2

V

IOH = -6.5 rnA

AC Electrical Characteristics

2.4

V

(With standard load)
DM54S473.54S472

PARAMETER

3.2

DM74S473, 74S472
0

5V ±10%;-55°Cto+125°e 5V ±5%; O°C to +70 e

CONDITIONS

MIN

TYP

MAX

MIN

TYP

UNITS

MAX
ns

tAA

Address Access Time

75

60

tEA

Enable Access Time

35

30

ns

tER

Enable Recovery Time

35

30

ns

Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that the device
may be operated at these values.
Note 2: These limits do not apply during programming. For the programming ratings, refer to the programming instructions_
Note 3: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vee = 5V and T A = 25° e.
Note 4: During Ise measurement, only one output at a time should be grounded. Permanent damage may otherwise result.
Note 5: To measure VOH, leEX or Ise on an unprogrammed part, apply 10.5V.

6-9

~National

Bipolar PROMs

D Semiconductor
DM54S474/DM74S474 4096·Bit (512 x 8)
TRI·STATE® PROM
.
DM54S475/DM74S475 4096·Bit (512 x 8)
Open·Coliector PROM
General Description

Features

These Schottky memories are organized in the popular
512 words by 8 bits configuration. Four memory enable
inputs are provided to control the output states. When
E1 and E2 are low and E3 and E4 are high, the output
presents the contents of the selected word.

•

Advanced titanium-tungsten (Ti-W) fuses

•

Schottky-clamped for high speed
Address access-65 ns
Enable access-35 ns

•

PNP inputs reduce input loading

•

All de and ac parameters guaranteed over temperature

•

Low voltage TRI·SAFETM programming

•

Board level programming

•

ROM mates are DM87S95 and DM87S96

If E1 or E2 are high, or E3 or E4 are low, it causes all
8 outputs to go to the "OFF" or high impedance state.
The memories are available in both open·collector and
TR I-STATE versions and are available as ROM's as
well as PROM's.
PROM's are shipped from the factory with lows in all
locations. A high may be programmed into any selected
location by following' the programming instructions.
Once programmed, it is impossible to go back to a low.
See the last page of this section for detailed programming information.

Connection Diagram
Military

Commercial

OpenCollector

X

X

DM74S475

Dual-I n-Line Package

TRI-STATE

X

DM74S474
DM54S474

X

AJ

23

AB

N, J

A6

N, J

AS

22 NC

J

A4

21 £1

X

X
X

DM54S475

Package

X

J

A]

A2
Al

Block Diagram

11

AD

AS
AJ

A6

4096·81T CELL
64 X 64

AS

MEMORY MATRIX

A4

OB

16 OJ

01
02 10

15 06

11

14 05

0]

A]

13 04

GND 12

TOP VIEW
A2----~

Logic Symbol

Al-------t

AO------I

El E2 E3E4

El
E2--....r-I-'

~~--+-~-~+---.~--.-+-~~--+-~-~
E]----,._'"

E4
AD

A2
OB

OJ

06

05

03

04

Order Number DM54S474J, DM54S475J,
DM74S474J or DM74S475J
See NS Package J24A
Order Number DM74S474N or DM74S475N
See NS Package N24B

6-10

02

01

A3

A4
AS

A6
AJ

AS
01 02 03 04 05 06 07 OB

Absolute Maximum Ratings
Supply Voltage (Note 2)
Input Voltage (Note 2)
Output Voltage (Note 2)
Storage Temperature
Lead Temperature (Soldering, 10 seconds)

Operating Conditions

(Note 1)

-D.5V to +7V
-1 .2V to +5.5V
-D.5V to +5.5V
-65°C to +150°C
300°C

DC Electrical Characteristics

Supply Voltage (VCC)
DM54S474, DM54S475
DM74S474, DM74S475
Ambient Temperature (T A)
DM54S474, DM54S475
DM74S474, DM74S475

MIN

MAX

UNITS

4.5
4.75

5.5
5.25

V
V

-55
0

+125
+70

°c
°c

Logical "0" Input Voltage (Low)

0

0.8

V

Logical "1" I nput Voltage (High)

2.0

5.5

V

(Note 3)

. DM54S474, DM54S475

DM74S474, DM74S475

CONDITIONS

PARAMETER

UNITS
MIN

IlL

Input Load Current, All Inputs

VCC

= Max, VIN = 0.45V

IIH

Input Leakage Current, All Inputs

VCC

= Max, VIN = 2.7V

II

Input Leakage Current, All Inputs

VCC = Max, VIN

VOL

Low Level Output Voltage

VCC

VIL

Low Level Input Voltage

TYP

MAX

-80

-250

= 5.5V

= Min, IOL = 16 mA

0.35

MIN

TYP

MAX

-80

-250
25

pA

1.0

1.0

mA

0.35

0.5
0.80

VIH

High Level Input Voltage

ICEX

Output Leakage Current
(Open·Coliector Only) (Note 5)

= Max, VCEX = 2.4V
VCC = Max, VCEX = 5.5V

Vc

Input Clamp Voltage

VCC

= Min, liN = -18 mA

CIN

Input Capacitance

VCC

= 5V, VIN = 2V, T A = 25°C,

Co

Output Capacitance

VCC

0.45

V

0.80

V

2.0

2.0

V

50

VCC

100
--0.8

pA

25

-1.2

--0.8

50

pA

100

pA

-1.2

V

4.0

4.0

pF

6.0

6.0

pF

1 MHz

= 5V, Vo = 2V, TA = 25°C,

1 MHz, Output "OFF"
ICC

Power Supply Current

VCC

= Max, All Inputs Grounded,

115

170

115

170

mA

All Outputs Open
TRI-STATE PARAMETERS
ISC

Output Short Circuit Current

Vo

= OV, VCC = Max, (Note 4)

-70

·-20

-20

-70

rnA

±50

pA

(Note 5)
1HZ

Output Leakage (TRI·STATE)

VCC

= Max, Vo = 0.45 to 2.4V,

±50

Chip Disabled
VOH

Output Voltage High, (Note 5)

IOH
IOH

= -2 rnA
= -6.5 mA

AC Electrical Characteristics

2.4

V

3.2
2.4

V

(With standard load)
DM54S474, DM54S475

PARAMETER

3.2

DM74S474, DM74S475
o

5V ±10%;-55°eto+125°e 5V ±5%; oOe to +70 e

CONDITIONS

MIN

TYP

MAX

MIN

TYP

UNITS

MAX

tAA

Address Access Time

(Figure 1)

40

75

40

65

ns

tEA

Enable Access Time

(Figure 2)

20

40

20

35

ns

tER

Enable Recovery Time

(Figure 2)

20

40

20

35

ns

Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that the device
may be operated at these values.
Note 2: These limits do not apply during programming. For the programming ratings, refer to the programming instructions.
Note 3: These limits apply over the entire operating range unless stated otherwise. All tYpical values are for Vee = 5V and TA = 25°C.
Note 4:

During Ise measurement, only one output at a time should be grounded. Permanent damage may otherwise result.

Note 5: To measure VOH, leEX or ISC on an unprogrammed part, apply 10.5V to both A7 and A2 (pin 1 and pin 6).

6-11

Standard Test Load
•

Input waveforms are supplied by a pulse generator
having the following characteristics: PRR = 1 MHz,
ZOUT = son, tr ~ 2.S ns and tf ~ 2.S ns (between
1.0V and 2.0V).
• tAA is measured with both enable inputs at a steady
low level.
• tEA and tER are measured from the 1.SV on in·
puts and outputs with all address inputs at a steady
level and with the unused enable input at a steady
low level.

vcc

MEMORY

O~J~~~ 0-...- - -....
TEST

* CL includes probe and jig capacitance.

Switching Time Waveforms
3V
ADDRESS INPUT

3V

-JI '-_ _ _ _ _ _/1 ,---------

ENABLE INPUT

Qy _ _ _

1.5V
QV

OUTPUT

OUTPUT

tEA

FIGURE 2. Enable Access Time and Recovery Time

FIGURE 1. Address Access Time

Typical Performance Characteristics
Typical Switching Characteristics
as a Function of VCC (TA = 2So C,
Standard Load)

Typical Switching Characteristics
as a Function of Temperature
(VCC = SV, Standard Load)
70

50

!....

40

""""
r- '"-

r-

t~A
-.l

]

40

;::

3D

:g

-

4.5

125

I
I

t~A
I

o

25

-55

I

t~A

tEIR

10

I

o

~

20

t~R

10

--

50

I
I

::;;

I
1

60

l""- ~A

;:: . 30
20

70

I
I
I
I

60

5.0

5.5

SUPPLY VOLTAGE (VI

TA - AMBIENT TEMPERATURE ('C)

Equivalent Circuits
Equivalent of Each Input

vcc

Typical Open·Coliector Output

Typical TRI·STATE Output
VCC
\,

INPUT 0 - -....-

...

L-.~"'-<"l OUTPUT

6-12

~National

Bipolar PROMs

D Semiconductor
DM54S570/DM74S570 2048·Bit (512 x 4)
Open· Collector PROM
DM54S571/DM74S571 2048·Bit (512 x 4)
TRI·STATE® PROM
General Description

Features

These Schottky memories are organized in the popular
512 words by 4 bits configuration_ A memory enable
input is provided to control the output states. When
the enable input is in the low state, the outputs present
the contents of the selected word.

•

Advanced titanium-tungsten (Ti-W) fuses

•

Schottky-clamped for high speed
Address access-55 ns max
Enable access-30 ns max

•

PNP inputs reduce input loading

•

All dc and ac parameters guaranteed over temperature

•

Low voltage TRI-SAFETM programming

•

Board level programming

•

ROM mates are DM74S270 and DM74S370

If the enable input is raised to a high level, it causes all
4 outputs to go to the "OFF" or high impedance state.
The memories are available in both open-collector and
TRI-STATE versions and are available as ROM's as well
as PROM's.
PROM's are shipped from the factory with lows in all
locations. A high may be programmed into any selected
location by following the programming instructions.
Once programmed, it is impossible to go back to a low.
See the last page of this section for detailed programming information_

Commercial

Open·
Collector

DM74S570

X

X

DM74S571

X

Military

DM54S570

X

DM54S571

X

TRI·STATE

Package

X

N, J

.X

J

N,J

X

J

Block Diagram

Connection Diagram
Dual-In-Lirte Package

MOST SIGNIFICANT
AODRESS BIT

I
AS
A7
A6
AS
A4
A3

2048·BIT CEL lS
64 X 32·81T
MEMORY MATRIX

A6

VCC

AS

A7

A4

AS

A3

Ei

AD

01

Al

02

A2

A2

03

Al

GNO

04

AD
TOP VIEW

Logic Symbol
AD

MOST

SIG~~;~AB~~ - 0 4

03

02
01

Order Number DM54S570J, DM54S571J,
,
DM74S570J or DM74S571J
See NS Package J16A

Al

01

A2

02

A3

OJ

A4

04

AS
A6
A7

Order Number DM74S570N or DM74S571N
See NS Package N16A

6-13

El

or-

to-

Il)

Absolute Maximum Ratings

Operating Conditions

(Note 1)

en
~

'"
c

:E

.......
or-

Supply Voltage (Note 2)
Input Voltage (Note 2)
Output Voltage (Note 2)
Storage Temperature
Lead Temperature (Soldering, 10 seconds)

--Q.5V to +7V
-1.2V to +5.5V
--o.5V to +5.5V
-65°C to +150°C
300°C

Il)

en

~
Il)

DC Electrical Characteristics

Input Load Current, All Inputs

VCC = Max, VIN = 0.45V

:E

Input Leakage Current, All Inputs

VCC = Max, VIN

II

Input Leakage Current, All Inputs

VCC = Max, VIN = 5.5V

25

VOL

Low Level Output Voltage

VCC = Min, IOL = 16 mA

VIL

Low Level Input Voltage

VIH

High Level Input Voltage

ICEX

Output Leakage Current

'"
~
Il)

:E

c

V
V

-55
0

+125
+70

°c
°c

Logical "0" Input Voltage (Low)

0

O.S

V

Logical "1" Input Voltage (High)

2.0

5.5

V

MIN

IIH

Il)

5.5
5.25

CONDITIONS

I!L

'"
c

4.5
4.75

DM54S570, 54S571
PARAMETER

Il)

en
~

UNITS

(Note 3)

o

to-

MAX

Ambient Temperature (TA)
DM54S570, DM54S571
DM74S570, DM74S571

to-

~

MIN
Supply Voltage (VCC)
DM54S570, DM54S571
DM74S570, DM74S571

TYP
-SO

= 2.7V

0.35

DM74S570, 74S571
UNITS

MA)~

MIN

TYP
-SO

-250

pA

1.0

1.0

mA

0.5

0.35

VCC = Max, VCEX = 5.5V

Input Clamp Voltage

VCC = Min, liN = -lS mA

CIN

I nput Capacitance

VCC = 5V, VIN

Co

Output Capacitance

VCC = 5V, Vo = 2V, TA = 25°C,

= 2V, T A

V

O.SO

V
V

50
100
-O.S

= 25°C,

0.45

2.0

VCC = Max, VCEX ~ 2.4V

pA

25

2.0

(Open-Collector Only) (Note 5)

-250

25

O.SO

Vc

MAX

-1.2

-O.S

50

pA

100

pA

-1.2

V

4.0

4.0

pF

6.0

6.0

pF

1 MHz

1 MHz, Output "OFF"
ICC

Power Supply Current

VCC = ~ax, All Inputs Grounded,

90

130

90

130

mA

All Outputs Open
TRI-STATE PARAMETERS
ISC

Output Short Circuit Current

Vo = OV, VCC = Max, (Note 4)

-70

-20

-20

-70

mA

±50

pA

(Note 5)
1HZ

Output Leakage (TRI-STATE)

VCC = Max, Vo = 0.45 to 2.4V,

±50

Chip Disabled
VOH

Output Voltage High, (Note 5)

IOH = -2 mA

. 2.4

3.2

V

IOH = -6.5 mA

AC Electrical Characteristics

2.4

V

(With standard load)
DM54S570, 54S571

PARAMETER

3.2

DM74S570, 74S571

5V ±10%;-55°Cto+125°C 5V ±5%; O°C to +70°C

. CONDITIONS

MIN

TYP

MAX

MIN

TYP

UNITS

MAX

tAA

Address Access Time

(Figure 1)

40

65

40

55

ns

tEA

Enable Access Time

(Figure 2)

20

35

20

30

ns

tER

Enable Recovery Time

(Figure 2)

20

35

20

30

ns

Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged_ They do not mean that the device
may be operated at these values.
Note 2: These limits do not apply during programming. For the programming ratings, refer to the programming instructions.
Note 3: These limits apply over the entire operating range unless stated otherwise. All typical values are for VCC

= 5V and TA

Note 4: During ISC measurement, only one output at a time should be grounded. Permanent damage may otherwise result.
Note 5: To measure VOH, ICEX or ISC on an unprogrammed part, apply 10.5V to both AS and A2 (pin 14 and pin 7).

6-14

= 25°C.

Standard Test Load
•

Input waveforms are supplied by a pulse generator
having the following characteristics: PR R = 1 MHz,
ZOUT = 50n, tr ~ 2.5 ns and tf ~ 2.5 ns (between
1.0V and 2.0V).
• tAA is measured with both enable inputs at a steady
low level.
• tEA and tER are measured from the 1.5V on inputs and outputs with all address inputs at a steady
level and with the unused enable input at a steady
low level.

Vee

MEMORY

O~Jb~~ 0-....- - - . . . ,
TEST

* CL includes probe and jig capacitance.

Switching Time Waveforms
3V

3V

ADDRESS INPUT

1.5V

1.5V

ENABLE INPUT

OV

I.SV

1.5V

OUTPUT

1.5V

OUTPUT

'ER

FIGURE 1. Address Access Time

FIGURE 2. Enable Access Time and Recovery Time

Typical Performance Characteristics
Typical Switching Characteristics
as a Function 01 V CC (T A = 25°C,
Standard Load)

Typical Switching Characteristics
as a Function of Temperature
(VCC = 5V, Standard Load)
70

70

60

60

50

........

40

~
;::

30
20
10

--

-

,I

........

_

I,

I~A
1

~

;::

-

I~R

·25

40

30

r---

20

o

4.5

125

IdA

,I
I~A
tE,R

10

,

-55

---

50

"':"AA

,
I,

I
5.0

5.5

SUPPLY VOLTAGE (V)

TA - AMBIENT TEMPERATURE re)

Equivalent Circuits
Equivalent of Each Input

vee

Typical TRI·STATE Output
vee

INPUTo--....- - t

-o OUTPUT

L-.. . . . . . . . . .

6-15

Typical Open·Collector Output

~National

Bipolar PROMs

~ Semiconductor

DM54S572/DM74S572 4096·Bit (1024 x 4)
Open·Coliector PROM
DM54S573/DM74S573 4096·Bit (1024 x 4)
TRI·STATE® PROM

General Description

Features

These Schottky PROM memories are organized in the
popular 1024 words by 4 bits configuration. Two
memory enable inputs are provided to control the
output states. When the enable inputs are in the low
state, the outputs present the contents of the selected
word.

• Advanced titanium-tungsten (Ti-Wl fuses
• Schottky-clamped for high speed
Address access-60 ns max
Enable access-35 ns max

If either or both of the enable inputs is raised to a high
level, it causes all 4 outputs to go to the "OFF" or high
impedance state. The memories are available in both
open·collector and TR I·ST ATE® versions.
PROM's are shipped from the factory with lows in all
locations. A high may be programmed into any selected
location by following the programming instructions.
Once programmed, it is impossible to go back to a low.
See the last page of this section for detailed program·
ming information.

Military
DM74S572

X
X

DM74S573
DM54S572
DM54S573

Commercial

•

PNP inputs reduce input loading

•

All dc and ac parameters guaranteed over temperature

•

Low voltage TRI-SAFETM programming

•

Board level programming

•

High density 18-pin package

Open·
Collector

TRI·STATE

Package

X

N.J

X

X
X

N.J

X

J

X

Block Diagram

J

Connection Diagram

Logic Symbol

Dual·1 n·line Package
4096·BIT ARRAY
64 X 64-8IT
MEMORY MATRIX

lB

A6

11

AS

16

A4

15

A3

14

AD

13

Al

12

A2 7
_ 8
EI

AD

Vee

01

A7
02

A8
A9

03

01
04
02
03

11 04
IOn

GND

EI

E2

TOP VIEW
04

03

02

01

Order Number DM54S572J, DM54S573J,
DM74S572J or DM74S573J
See NS Package J18A

6·16

Order Number DM74S572N
or DM74S573N
See NS Package N 18A

Absolute Maximum Ratings
Supply Voltage (Note 2)
Input Voltage (Note 2)
Output Voltage (Note 2)
Storage Temperature
Lead Temperature (Soldering, 10 seconds)

Operating Conditions

(Note 1)

-{).5V to +7V
-1.2V to +5.5V
--{).5V to +5.5V
-65°C to +150°C
300°C

Supply Voltage (VCC)
DM54S572, DM54S573
DM74S572, DM74S573
Ambient Temperature (T A)
DM54S572, DM54S573

UNITS

4.5

5.5

V

4.75

5.25

V

+125

°c

0

+70

°c

Logical "0" Input Voltage (Low)

0

0.8

V

Logical "1" Input Voltage (High)

2.0

5.5

V

(Note 3)
DM54S572, 54S573

PARAMETER

DM74S572,74S573

CONDITIONS

UNITS
MIN

IlL

Input Load Current, All Inputs

VCC

Input Leakage Current, All Inputs

VCC

= Max,
= Max,

VIN

IIH

VIN

= 0.45V
= 2.7V

II

Input Leakage Current, All Inputs

VCC

= Max,

VIN

= 5.5V

VCC

= Min,

IOL

= 16 mA

VOL

Low Level Output Voltage

VIL

Low Level Input Voltage

VIH

High Level Input Voltage

ICEX

Output Leakage Current

Vc

Input Clamp Voltage

= Max, VCEX ~ 2.4V
VCC = Max, VCEX = 5.5V
VCC = Min, liN = -18 mA

CIN

Input Capacitance

VCC

Co

Output Capacitance

(Open-Collector Only) (Note 5)

MAX

-55

DM74S572, DM74S573

DC Electrical Characteristics

MIN

TYP
-80

0.35

MAX

MIN

-250

TYP

MAX

-80

-250
25

IlA

1.0

1.0

mA

0.35

0.50
0.80

2.0

= 5V,

= 2V,

VIN

TA

V
V
V

50
100
-0.8

= 25°C,

0.45
0.80

2.0

VCC

Il A

25

-1.2

-0.8

50

IlA

100

IlA

-1.2

V

4.0

4.0

pF

6.0

6.0

pF

1 MHz
VCC

= 5V,

Vo

= 2V,

TA

= 25'C,

1 MHz, Output "OFF"
ICC

Power Supply Current

VCC

= Max, All

Inputs Grounded,

125

140

125

140

mA

All Outputs Open
TRI-STATE PARAMETERS
ISC

Output Short Circuit Current

Vo

= OV,

VCC

= Max,

(Note 4)

-70

-20

-20

-70

mA

:':50

IlA

(Note 5)
1HZ

Output Leakage (TRI·STATE)

VCC

= Max,

Vo

= 0.45 to 2.4V,

:':50

Chip Disabled
VOH

Output Voltage High, (Note 5)

IOH
IOH

= -2 mA
= -6.5 mA

AC Electrical Characteristics

2.4

3.2

V
2.4

V

(With standard load)

DM54S572,54S573
PARAMETER

3.2

CONDITIONS

5V:':10%;-55°C'to+125°C
MIN

TYP

MAX

DM74S572,74S573
5V :':5%; OU C to +70°C
MIN

TYP

UNITS

MAX

tAA

Address Access Time

40

75

40

60

ns

tEA

Enable Access Time

25

45

25

35

ns

tER

Enable Recovery Time

25

45

25

35

ns

Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that the device
may be operated at these values.
Note 2: These limits do not apply during programming. For the programming ratings, refer to the programming instructions.
Note 3: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vce = 5V and T A
Note 4:

During Ise measurement, only one output at a time should be grounded. Permanent damage may otherwise result.

Note 5: To measure VOH, ICEX or Ise on an unprogrammed part, apply 10.5V to both A5 and A2 (pin 2 and pin 7).

6-17

=

25°e.

,....

,....
en
r-...

00

00

Bipolar PROMs

~National

~ Semiconductor

~
c-.... DM77S180/DM87S180, DM77S181/DM87S181
,.... 1024 X 8-Bit TTL PROM
00
,....

en
r-...
r-...

~

C

o
en
r-...

00
,....
00

~

c
oCO
,....

en
1'0

General Description

Features

These Schottky memqries are organized in the popular
1024 words by 8 bits configuration. Four memory enable
inputs are provided to control the output states. When E1
and E2 are low and E3 and E4 are high, the output
presents the contents of the selected word.

• Advanced titanium-tungsten (Ti-W) fuses
• Schottky-clamped for high speed
Address access-40 ns typ
Enable access-15 ns typ

If E1 or E2 are high, or E3 or E4 are low, it causes all 8 outputs to. go to the "OFF" or high impedance state. The
memories are available in both open-collector and TRISTATE''' versions.

• PNP inputs reduce input loading
• All DC and AC parameters guaranteed over
temperature
• Low voltage TRI-SAFETM programming
Military Commercial

PROMs are shipped from the factory with lows in alilocalions. A high may be programmed into any selected location by following the programming instructions.
See the last page of this section for detailed programming information.

DM87S180

X

DM87S181

X

DM77S180

X

DM77S181

X

Open·
TRI·STATE Package
Collector
N. J

X
X

N. J

J

X
X

J

r-...

~

C

Connection Diagram

Block Diagram

Dual·ln-Line Package
A9
A8
4096·81T CELL
64 X 128
MEMORY MATRIX

A1
A6
AS

A7

24 Vec

A6

23 A8
22

AS

A4

A9,

A4

21 El

AJ

20 _
E2

A2

19 EJ

AJ------t
A2------I
Al------I
AO------I

AI

18 E4

AD

11 08

E1
[ 2 - - , . . . .........
EJ
r-~~---.-r---~~---.-+--~~~--~+---~~---,

16 01

01
E4
10

15

OJ 11

14

12

13

02

08

01

06

05

04

OJ

02

01
GND

Logic Symbol
AD

06
05
04

TOPVIEW

01

Order Number DM77S180J, DM77S181J,
DM87S180J or DM87S181J
See NS Package J24A

02
OJ
04

Pin Names

. E1

to E4

Enable Inputs

AO to A9

Address Inputs

01 to 08

Data Outputs

6-18

Order Number DM87S180N
or DM87S181N
See NS Package N24B

Absolute Maximum Ratings (Note 1)

Operating Conditions

Supply Voltage (Note 2)

Supply Voltage (Vccl
DM77S180, DM77S181
DM87S180, DM87S181

Input Voltage (Note 2)

-0.5Vto + 7V
-1.2Vto +5.5V

Output Voltage (Note 2)

- 0.5V to + 5.5V
-65·Cto +150·C
Storage Temperature
300·C
Lead Temperature (Soldering, 10 seconds)

Ambient Temperature (TN
DM77S180, DM77S181
DM87S180, DM87S181

Units

Min

Max

4.5
4.75

5.5
5.25

V
V

+125
+70
0.8

·C
·C

5.5

V

-55
0
0
2.0

Logical "0" InputVoltage(Low)
Logical "1" Input Voltage (High)

V

DC Electrical Characteristics (Note 3)
Parameter

Conditions

DM77S180,
DM87S180,
Units
DM77S181
DM875181
Min
Typ
Max ' Min
Typ
Max

IlL

Input Load Current, All Inputs

-100

J1.A

IIH

Input Leakage Current, All Inputs Vcc= Max, V IN =2.7V

25

25

J1.A

II

Input Leakage Current, All Inputs Vcc=Max, VIN=5.5V

50

50

J1.A

VOL

Low Level Output Voltage

0.45

V

V IL

Low Level Input Voltage

V IH

High Level Input Voltage

leEx Output Leakage Current
(Open·Collector Only)

-10

Vcc= Max, V IN =0.45V

0.35

Vcc= Min, IOL = 16 mA

-100

-10

0.50

0.35

0.80
2.0

0.80
2.0

50
100

Vee=Max, VcEx =2.4V
Vcc= Max, VCEX = 5.5V

V
V

50
100

J1.A
J1.A

Vc

Input Clamp Voltage

Vcc=Min, IIN= -18 mA

C IN

Input Capacitance

Vce =5V, V IN =2V, TA =25·C,
1 MHz

4.0

4.0

pF

Co

Output Capacitance

Vcc =5V, Vo=2V, TA =25·C,
1 MHz, Output "OFF"

6.0

6.0

pF

Icc

Power Supply Current

Vcc= Max, All Inputs Grounded,
All Outputs Open

115

-0.8

-1.2

-0.8

170

115

-1.2

170

V

mA

TRI·STATEPARAMETERS
Isc

Output Short Circuit Current

Vo= OV, Vcc= Max, (Note 4)

1HZ

Output Leakage (TRI·STATE)

Vcc=Max, Vo =0.45to2.4V,
Chip Disabled

V OH Output Voltage High

-20

-20

±50
2.4

IOH= -2 mA
IOH= -6.5 mA

-70

-70

mA

±50

J1.A

3.2
2.4

V
V

3.2

AC Electrical Characteristics (With standard load)

Parameter

Conditions

DM77S180,
DM77S181
5V ± 10%; - 55°C to
+125°C
Min
Typ
Max

Address Access Time

40

75

tEA

Enable Access Time

15

35

tER

Enable Recovery Time

15

35

tAA

DM87S180,
DM875181
Units
5V±5%, O°C to
+70 o C
Min
Typ
Max
60

ns

15

30

ns

15

-30

ns

40

Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that the device may be

operated at these values.
Note 2: These limits do not apply during programming. For the programming ratings, refer to the programming instructions.
Note 3: These limits apply over the entire operating range unles stated otherwise. All typical values are for Vec = SV and TA = 2S·C.
Note 4: During ISC measurement, only one output at a time should be grounded. Permanent damage may otherwise result.

6-19

Bipolar PROMs

~National

~ Semiconductor

DM77S184/DM87S184 8192-Bit (2048 x 4)
Open-Collector PROM
DM77S185/DM87S185 8192-Bit (2048 x 4)
TRI-STATE@ PROM
General Description
These Schottky PROM memories are organized in the
popular 2048 words by 4 bits configuration_ One memory enable input is provided to control· the output
states. When the enable input is in the low state, the
outputs present the contents of the selected word.

See the last page of this section for detailed programming information_

If the enable input is raised to a high level, it causes
all 4 outputs to go to the "OFF" or high impedance
state. The memories are available in both open-collector and TRI-STATE®versions.

• Advanced titanium-tungsten (Ti-W) fuses
• Schottky-clamped for high speed
Address access-40 ns max
Enable access-15 ns max
• PNP inputs reduce input loading
• All DC and AC parameters guaranteed over temperature
• Low voltage TRI-SAFETM programming

Features

PROM's are shipped from the factory with lows in all
locations. A high may be programmed into any selected·
location by following the programming instructions.
Commercial

OpenCollector

DM87S184

X

X

DM87S185

X

Military

DM77S184

X

DM77S185

X

TRI-STATE

Package

X

N, J

X

J

N,J
J

X

Connection Diagram Logic Symbol

Block Diagram

Dual-In-Line Package
8192·81T ARRAY
128 X 54·BIT
MEMORY MATRIX

A6
A5

A4

A3

Al
A2
AID

TOP VIEW

04

03

02

01

Pin Names

E

Enable Input

Order Number DM77S184J, DM77S185J,
DM87S184J or DM87S185J
See NS Package J18A
Order Number DM87S184N
or DM87S185N
See N S Package N 18A

AO-A10 Address Inputs
01-04 Data Outputs
6-20

Absolute Maximum Ratings
Supply Voltage (Note 2)
Input Voltage (Note 2)
Output Voltage (Note 2)
Storage Temperature
Lead Temperature (Soldering, 10 seconds)

--
OU1PUT8 6

OUTPUY8 1

10

MSB OUTPUT 8,

INPUTA.

L..-________---!
Vss

12

4 ....----~~~BLE

Order Number MM5221J
See NS Package J24A
Order Number MM5221 N
See NS Package N24B

Note: For programming information see Memory Applications Handbook, page 4-6.

7-9

Absolute Maximum· Ratings

Operating Conditions

VGG Supply Voltage
Vss - 20V
Voo Supply Voltage
Vss - 20V
Input Voltage
(V ss - 20)V < VIN < (V ss +0.3)V
Storage Temperature
-65°C to +150°C
Lead Temperature (Soldering, 10 sec)
300°C

Operating Temperature

Electrical Characteristics
T A within operating temperature range, Vss = +5V ±5%, VGG = Voo = -12V ±5%, unless otherwise specified.

PARAMETER

CONDITIONS

MIN

Output VoltageLevels
MOS to TTL
Logical "1"
Logical "0"

6.8 kD ±5% to V GG Plus One
Standard 'Series 54/74 Gate

Output Current Capability
Logical "0"

V OUT

= 2.4V

100

IGG (Note 1)

UNITS

V
V
mA

Vss - 4.2

V
V

T A = 25°C
Vss = +5V
VGG = Voo

6.5

12.0
1

mA

1

IlA

5
15

25

pF
pF

700

950

I']S

= -12V

= Vss - 12V

VIN

Input Capacitance
V GG Capacitance (Note 4)

f
f

Address Time (Note 2)

See Timing Diagram
T A = 25°C,

= 1.0 MHz, VIN = OV
= 1.0 MHz, VIN = OV

VSS = 5V
VGG = Voo
Output AND Connections
(Note 3)

+0.4
+2.4

Vss - 2.0

I nput Leakage

T ACCESS

MAX

2.5

Input Voltage Levels
Logical "1"
Logical "0"
Power Supply Current

TYP

= -12V

6.8 kD ±5% to V GG Plus One
Standard Series 54/74 Gate

Note 1: The VGG supply may be clocked to reduce device power without affecting access time.
Note 2: Address time is measured from the change of data on any input except mode control or Chip
Enable line to the output of a TTL gate. (See Timing Diagram). See curves for guaranteed limit
over temperature.
Note 3: The address time in the TTL load configuration follows the equation:
T ACCESS = The specified limit + (N - 1) (50) ns
Where N = Number of AND connections.
Note 4: Capacitance guaranteed by design.

7-10

8

IlA

Performance Characteristics
Power Supply Current vs
Power Supply Voltages

Power Supply Current vs
Ambient Temperature
16 ~-r'-~-r'-~~~~~

16 rT-r~rT-r'-rT~~~~

N:-t--+-H-t-+ VSS = +5.0V
1'..,..,..
Voo = VGG =-12V

H--+-H-t--t-H--+- VDO = VGG
14

14

r+~~-r+-~-rTA=25C

12
l'O.
10 -1-1- MAXIMUM t'S..

.J...t""T
H-+--HF-::r-I- MAXIM UM -1--10 I-+-+-+-II-+-+--t-I-+-+--t-I-+-I
12

~

£

o
o

I--

~

£

8 1-+-+-+-+-+-+-+,-++-+-+-+-+-1

-

o
o

6 1-+-+-__I-1''''F-r-T"-t-I-+-+--t-I-+-I
H-+-H--t TYPICA L-t-~-r+-i

6

4
2H-t--HH-t--t-H-t--t-H-l

21-+-+-+-1-+-+-+-1-+-+--t-1-+-I

o

O ........-'--'--.L......I.-'--'--.L......I.-'--'--I.......J..-I

~-L~~-L~~-L~~~

17.0

16.0

18.0

-50 -25

Vss - VGG (V)

Typical Access Time vs
Power Supply Voltages

]

11

~1~
800

+10'C

+125'C

I'

~

600 H-t--H-t--t-t-+-+-+-+ +25· C

~

~

400 H-t--+-H-t--t-I-t-t--HI-t-l

~

200 I-+-+-+-I-+-+--t-I-+-+-+-II-+-I
16.0

15

100

r-T-r...,.--rT-r"rT-r~r-r-,

t-t-+-"""+-O;-±:::+-1I-+"'==r"~ +12 5 C
r-~ - - :;~.~

120

I-t-+-+~+-H-t--H- VDO = VGG

600 t-+-+--HI-t-+-+-t-+--+-H-+---l
400 H--t-H-t--H-t--t-t-t-t-+--l
200

r++-~-t-+-I-++-+-+-t-+-I

16.0

Vss - VGG (V)

17.0

18.0

Vss - VGG (V)

Timing Diagram/Address Time
-5V
'JV-

INPUT AN

rI

OV...J

L

ANYTTl/OTL

E'"·~10Pf
~

GATE

t

OUTPUT BM

)0-"'-0

MM5221
10 pf

I1-

l

~

ANY TTl I:;'
GATE

Vss-20V~

I EITHER

'.

~

t:::::: '''''";
'JV~
1,..----

':: I

125

0

18.0

17.0

50

1400

] 1:::

~

~-o s,

A,

I---D----f.-o e,

A"

TOP VIEW

Order Number MM5232J
See NS Package J24A

CON~~~i 0 - - - - '
CE,o----------l

Order Number MM5232N
See NS Package N24B

CE, o--------~

Note: For programming information see Memory Applications Handbook, page 4-6.

7-21

BJ

Absolute Maximum Ratings

Operating Conditions

VGG Supply Voltage
Vss - 20V
V LL Supply Voltage
Vss - 20V
Input Voltage
(V ss - 20) V < V IN < (V ss + .03)V
Storage Temperature Range
-65°C to +150°C
Lead Temperature (Soldering, 10 sec)
300°C

Operating Temperature Range

Electrical Characteristics

(Positive Logic)

TA within operating temperature range, Vss = +5.0V ±5%, VGG = VLL = -12V ±5%, unless otherwise noted.

PARAMETER
Output Voltage Levels
Logical "0", VOL
Logical "1", V OH

CONDITIONS

TYP

UNITS

V
V

2.4

VGG
Vss - 2.0

Power Supply Current
Iss (Note 4)

Vss; 5, V GG ; -12, V LL ; -12, T A ; 25°C

Input Leakage

V ,N

Input Capacitance (Note 1)

f; 1.0 MHz, V IN

;

OV

Output Capacitance (Note 1)

f; 1.0 MHz, V ,N

;

OV

Address Time (Note 2)

T A; 25°C, Vss; 5

;

MAX

.4

I L ; 1.6 mA Sink
I L ; 100 J.LA Source

I nput Voltage Levels
Logical "0", V'L
Logical "1", V ,H

TACCESS

MIN

23

Vss - 4.0
Vss +0.3

V
V

37

mA

15

pF

10

pF

1000

ns

Vss - 10V

J.LA

4
150

VGG ; V LL ; -12V
20

Output AND Connections (Note 3)

Note 1: Capacitances are measured periodically only.
Note 2: Address time is measured from the change' of data on any input or Chip Enable line to the output of a TTL gate.
(See Timing Diagram.)
Note 3: The address time follows the following equation: T ACCESS = the specified limit + (N - 1) x 25 ns where N = Number
of AND connections.
Note 4: Outputs open.

Timing Diagram/Address Time

E'N
+5V

EOUT

TIME

7·22

Performance Characteristics
Typical Access Time vs
Supply Voltage

Guaranteed Access Time vs
Supply Voltage
1600 r-T'""T""T.....-r-r-"T""'T""'-rT-,-,,-T-T"t
t-+-t-i'-t--H-+-+-+-+-+ VLL • Vee
t400 H--H-t-t++-t-t-H-HH-+-I
125°C I.d:--H-t-t++-t-t-H-I
1200 T... 70oCI:::+'f"'f......8--t-i-+-+-+--t

!

1000

1400 t-++-+-+-H-+-t-+-+-+-HH--+--t
1200 H--H-t-H-+-t-t-H-HH-+-t

1--r--r2;5°-=1Cf--t''A'-;''~FI''''i-H-i

~ 800 t-++-+-+-H--t-i-+-+-+-HH--+--t

..

600 H--H-t-t++-t-t-H-HH-+-t

... 600 H--H-t-H-+-t-t-H-HH-+-t

400 H--H-t-t++-t-t-H-HH--H

400 t-++-+-+-H-+-+-+-+-+-HH-+-t

200 H--H-t-t++-t-t-H--f-;H--H

200 t-++-+-+-H-+-t-+-+-+-HH-+-t

16.2

17.8

17.0

16.2

17.0

17.8

Vss + IVee I (V)

Power Supply Current vs
Temperature
80

Power Supply Current vs
Voltage
80

Vss' 5.0V
VLL = -12V

vGG '

70
60

60
~

~ 50

~

TA = 25°CVLL =V GG -

70

..,

MAXIMu'M

oS 40

MAXIMUM

40

50

Jl

30

30
TYPICAL
20

20

10

10
-50 -25

0

25

50

ThidL

16.2

75 100 125

TEMPERATURE (OC)

17.0

17.8

Vss + IVee I (V)

Typical Applications
TTL/MOS Interface
v,.

A,

B,

A.

B.

A,
A,

FIGURE 1. Power Saverfor
Small Memory Arrays

-,

r

I
I
I
I
.1
L ___ --'

B,
MMS232

A,

FIGURE 2. Power Saver for
Large Memory Arrays

B,
B,

A,

ASSUME IIV lL IIMIN. II-JV II

MOOE
CONTROL

VGG - VLL MIN· R (1.6 mAl (NI whett N· 1 for 5.1 font.
N- 1'0,6 .Slont.

eE, 0 - - - - - - 1

CE,o-----....J

Operating Modes

512 x 8 ROM connection
Mode Control = VIH
AID = VIL

1024 x 4 ROM connection
·Mode Control = VI L
AIO = VI L enables the odd (8, ... B7) outputs
VI H enables the even (B2 ... 88) outputs

Note: Both chip enables may be programmed to provide any of four combinations. Example if CE1 = 1 and CE2 = 1
outputs (Positive Logic) would be enabled only when device pins 2 and 3 are Logic "1". The outputs will be in the
third state when disabled.
-

7-23

I

I
I
I
I
I
I
I
I
L ___ --'

III

~National

MaS ROMs

~ Semiconductor

MM5240 2560·Bit Static Character Generator
General Description

Features

The MM5240 2560-bit static read only memory
is a P-channel. enhancement mode monolithic
MOS integrated circuit utilizing a low threshold
voltage technology to achieve bipolar compatibility_ TRI-STATE@ outputs provide wire ORed
capability without loading common data lines or
reducing system access times. The ROM is organized in a 64 x 8 word by 5-bit memory organi?ation.

• Bipolar compatibility
• High speed operation-500 ns max
• ±12 volt power suppl ies
• Static operation-no clocks required
• Multiple ROM logic appl ication-chip enable
output control
• Standard fonts available-off-the-shelf delivery

Applications
•
•
•
•

The MM5240 may be used as a 512 x 5-bit read
only memory for applications other than character generation.

Connection Diagram

Character generation
Random logic synthesis
Micro-programming
Table look-up

Dual-In-Line Package
l'
"OW
ADDRESS
INPUTS

L2

{
l,

Order Number MM5240J
See NS Package J24A

"

Order Number MM5240N
See NS Package N24B

B,

DATA
OUTPUTS

BJ
I,

I

CHII'
ENABLE

I,

Typical Application

I,

I,

..
LOAD/RECIRCULATE
CONTROL
-~'--------~--

'AC;ERfFRESH

MEMORY

lINfREFRESH
MEMORY

Note: For additional information refer to AN-40.
Note: Chip enable tied to VOO to enable.

7-24

Absolute Maximum Ratings

Operating Conditions

V GG Supply Voltage
V ss - 30V
V DD Supply Voltage
Vss - 15V
Input Voltage
(V ss - 20)V < V 1N < (V ss +0.3)V
Storage Temperature
-65°C to +150°C
Lead Temperature (Soldering, 10 sec)
300°C

Operating Temperature

Electrical Characteristics
PARAMETER
Output Voltage Levels
MOSto MOS
Logical "1"
Logical "0"

(Note 1)

MIN

CONDITIONS

MAX

UNITS

Vss - 9.0

V
V

+0.4

V
V

TYP

IMSl to GND
Vss - 1.0

MOS to TTL
Logical "1"
Logical "0"

6.8 kSl to V GG Plus One
Standard Series 54/74 Gate

Output Current Capability
Logical "0"

V OUT = Vss - 6.0V

+2.5

mA

2.5

Input Voltage Levels
Logical "1"
Logical "0"

Vss - 8.0
Vss - 2.0

V
V

Power Supply Current
25

IDD

IGG (Note 2)
Input Leakage

V 1N = Vss - 12V

Input Capacitance (Note 5)
VGG Capacitance (Note 5)

f=1.0MHz,V 1N =OV
f = 1.0 MHz, V 1N = OV

Address Time (Note 3)

See Timing Diagram
T A = 25°C

T ACCESS
Output AND Connection
(Note 4)

150

55
1

mA
/lA

1

/lA

5

8

25

40

pF
·pF

425

500

ns

4

MOS Load
TTL Load

10

Note 1: These specifications apply for VSS = +12V ±5%, VGG = -12V ±5%, T A = O°C to +70°C unless
otherwise specified.
Note 2: The V GG supply may be clocked to reduce device power without affecting access time.
Note 3: Address time is measured from the change of data on any input or Chip Enable line to the
output of a TTL gate. (See Timing Diagram). See curves for guaranteed limit over temperature.
Note 4: The address time in the TTL load configuration follows the equation:
T ACCESS = The specified limit + (N - 1) (50) ns
Where N = Number of AND connections.
The number of AND ties in the MOS load configuration can be increased at the expense of MOS "0"
level.
Note 5: Guaranteed by design.

7·25

Performance Characteristics
Guaranteed Access Time IT AI
vs Supply Voltage

Typical Access Time IT AI vs
Supply Voltage

.

1000 r - - - - - , - - - - , - - - - , - - . . . ,

1200

,

1000

800

"
600

-~

800

"

-.

600

,I-

400

400

.-;-~

(: 125'C

. ....-

~!O°C

':-"

25°C

200

200

10

11

12

13

12,0

lU

14

Voo Power Supply Current vs
Temperature

Power Supply Current vs
Voltage
60

Vss =+12,OV
VGG =-12,OV

TA = 25°C
50

50
40

~

...
30
20

~
T~P:CAl

-

-

I-

-I-

40
C[

--

E.

o

30

MA~

~ ...

I

J"'..

r-

...TYPICAL

:-."""

o

--- -r--

10

13,2

12,0

-50 -25

0 25

Timing Diagram/Address Time
+1ZV

OV

E,.

TACC£ss

·12V

OV
+JV

BV

EOUT

+JV

1,5V

OV

i - - - - - - - - - - - - - - - - -__ time

+12V

+JV-r-l

L

7-26

r--

50 15 100 125 150

TEMPERATURE

Vss & -VGG (V)

DV...J

- --.

20

10

10,8

13,2

Vss & -VGG (V)

Vss & - VGG (V)

C[

t-

I
I

r C)

MOS ROMs

~National

~ Semiconductor

MM5241 3072·Bit (64 X 6 X 8) ROM
General Description

Features

The MM5241 3072-bit static read only memory
is a P-channel enhancement mode monolithic MOS
integrated circuit utilizing a low threshold voltage
technology to achieve bipolar compatibility.
TRI-STATE® outputs provide wire ORed capability without loading common data lines or
reducing system access times. The ROM is organized in a 64 x 6 word by 8-bit memory organization. Programmable Chip Enables (CE, and CE 2 )
provide logic control of mUltiple packages without
external logic. A separate output supply lead is
provided to reduce internal power dissipation in
the output stages.

•

Bipolar compatibility

•

Standard supplies

•

Bus ORable output

•

Static operation

•

Multiple ROM control

No external
components required
+5V. -12V
TRI-STATE outputs
No clocks required
Two programmable
Chip Enable lines

Applications
•

Character generator

•

Random logic synthesis

•
•

Microprogramming
Table look-up

Block and Connection Diagrams
Dual-In-Line Package

"n

v"

'.

A.

10

"

·
·
·

22

11

"'.
"
" '.
"
""
""

12

IJ

CE.
CE,
Ne
A,
A,
A,

A.
A,

,

A,

DECODE

LSB Lo

I-----I:::t-t-O "
I--i:~f-O "
I-----I:::t-t-O '.
1---c~J-o '.
1--. -c::t-f-O ••

M[MORY
ARRAY

A,

v~

21

Vt;t;

20

I

19

1

11

"

"

"

1---c~J-o.,
I--i:~t-o ••

"

Order Number MM5241J
See NS Package J24A

CE,o----------1
CE,O----------I

CHIP
ENABLE
ARRAY

Order Number MM5241N
See NS Package N24B

Typical Applications

D E

FIGURE 1. Power Saver for
Small Memory Arrays

TTL/MOS Interface

FIGURE 2_ Power Saver for
Large Memory Arrays
v

v

,,--,

I,

.,.

I,

ANVTTllDTl
DEVICE

ANYTTlIOTL

DEVICE

CE,

v"

I
I
R
I
I
I
I
I
L ___ -.I

"----,

I

A.

-::- I
I

I

I

I

I

L ___ -.I

v"

ASSUME I!VLL .IMIN

I
I

=:

II-lV II

VGG - V LL MIN'" A (1.6 mAl (N) where N '" 1 fot 5 ... 1 font.
N = 810r6 ... 8 font

eE,-----'

Note: 80th chip enables may be programmed to provide any of four combinations. Example: If CEl = 1 and CE2 = 1 outputs
(Negative Logic) would be enabled only when device pins 2 and J are negative (Logic "1"). The outputs will be in the third state
when disabled. La, Ll and L2 (device pins 11, 13 and 14) are in positive logic (1 = most positive voltage levels = Vs - 2V; a =
most negative voltage level = Vss - 4V).
Note: For programming information see Memory Applications Handbook, page 4-6.

7-27

Absolute Maximum Ratings

Operating Conditions

VGG Supply Voltage
Vss - 20V
V LL Supply Voltage
Vss - 20V
Input Voltage
(Vss - 20) V < VIN < (V ss + .03)V
Storage Temperature Range
-65°C to +150°C
Lead Temperature (Soldering, 10 sec)
300°C

Operating Temperature Range

Electrical Characteristics

(Negative Logic) (Note 5)

TA within operating temperature range, VSS = +5.0V ±5%, VGG = V LL = -12V ±5%, unless otherwise noted.
PARAMETER
Output Voltage Levels
Logical "1"
Logical "0"

MIN

CONDITIONS
IL
IL

;
;

TYP

MAX
.4

1.6 mA sil'k
100 IlA source

2.4

Input Voltage Levels
Logical "1"
Logical "0"
Vss

= 5, VGG ; -12, VLL

Input Leakage

V1N

= Vss - 10V

Input Capacitance (Note 1)

f

;

-12, TA

= 25°C

23

= 1.0 MHz, V1N ": OV

Output Capacitance (Note 1)

f; 1.0 MHz, V 1N

Address Time (Note 2)
TACCESS

TA = 25°C. Vss; 5
VGG ; VLL = -12V

;

V
V

50

mA

1

IlA

15

pF

4

10

pF

700

900

ns

5

OV
150

V
V

Vss -4.0
Vss - 2.0

Power Supply Current
Iss (Note 4)

UNITS

20

Output AND Connections (Note 3)

Note 1: Address time is measured from the change of data on any input or Chip Enable line to the output of a TTL gate.
(See Timing Diagram.) See curves for guaranteed limit over temperature.
Note 2: Capacitances are measured periodically only.
Note 3:. The address time follows the following equation: T ACCESS = the specified limit + (N of AND connections.
Note 4: Outputs open.

11 x 25 ns where N = Number

Note 5: All addresses and ou'tputs are in negative true logic with the exception of LO, L,. and L2 which are in positive logic.

7-28

Performance Characteristics
Typical Access Time vs
Supply Voltage
1400

~

1200

I
I

1000

I

!

VLL

12~oc

Guaranteed Access Time vs
Supply Voltage
'

1600 """-'-'r-T'"-,-,-rT""'T-'-"""""T'""""""'''
I-++I-++-+-I-IH-+-+ VI I • VGG
1400 H-+-t-++-+--HH-+-t--t-t-t--t-t

VGG

125°C~:H-+t-+-H-r+-+,

1200

....

TA " 10°C ...
800
25"C

1000 TA "
~

..
... 600

;~:~Io::±-"'-F'poo;.oC:::J>.:;:p"l-i-++-i

~--H~~~~~~~+-+4

~ 800 I-+-HH-~-r+-+-+~-++-+,

600 H--+-IH-+-tH-+-+-++-+-+-+-+4
400

400 I-+-HH-~-r+-+-+++-++-+,

200

200 1-++-iH-~H-+-+-+++-++-+,
16.2

11.0

16.2

11.8

Power Supply Current
vs Temperature
80

<
~

11.8

Power Supply Current
vs Voltage
80

10

Vss= 5.0V
VGG " VLL = -12V

10

60

II

60

<
E
j!

50
MAXIMUM

40

11.0
Vss + IVGGI (V)

Vss + IV GG I (V)

TA ' 25"CV =V .-

iL I t'i-

50

MAXIMUM-

40

30

30

TYPltAll

TYPICAL
20

20

10

10
-50 -25

0

25

50

16.2

15 100 125

TEMPERATURE (OC)

11.0
Vss + IVGG I (V)

Timing Diagram/Address Time

+5V

EON

EOUT

TIME

7·29

11.8

~National

MOS ROMs

~ Semiconductor

MM52116 (2316E) 16,384·Bit Read Only Memory
General Description

Features

The MM52116 is a static MOS 16,384-bit read-only
memory organized in an 2048-word-by-8-bit format.
It is fabricated using N-channel enhancement and
depletion-mode technology which provides complete
DTL/TTL compatibility and single power-supply operation.

•
•
•
•
•
•
•
•
•
•
•

Three programmable chip selects controlling the TRI5T ATE".: outputs allow for memory expansion.
Programming of the memory array. and chip·select
active levels is accompl ished by changing two masks
during fabrication.

Fully decoded
Single 5V power supply ±10% tolerance
Inputs and outputs TTL compatible
Outputs drive 2 TTL loads and 100 pF
Static operation
TRI-STATE outputs for bus interface
Programmable chip selects
2048-word-by-8-bit organization
Maximum access time - 450 ns
Industry standard pin outs (2316E)
Compatible to standard EPROMs

Applications
• Microprocessor instruction store
• Control logic
• Table look-up

Block and Connection Diagrams

Dual-In-Line Package

AD
Al

02

A3
ROM
ARRAY

ROW DECODE

23 AS

04

AS

22 A9

05

A4

21 CS3

06

A3

2DCSI

A2

19 AID

01
A1

OS

IS CS2

Al

11

AD

~

VCC

A6

A2

A4

24

A1

OS

16 01

01

DEC.

rr

AS

A9

AID

CSI

7-30

CS2

CS3

02

10

IS 06
14 05

03 "

13 04

GND 12

ToPVIEW

Order Number MM52116D
See NS Package D24C
Order Number MM52116N
See NS Package N24B

Operating Conditions

Absolute Maximum Ratings

(Note 1)
Voltage at Any Pin
-0.5V to +7.0V
_65°C to +150°C
Storage Temperature Range
1W
Power Dissipation
300°C
Lead Temperature (Soldering, 10 seconds)

Operating Temperature Range

DC Electrical Characteristics
ITA within operating temperature range, VCC = 5V ±10%, unless otherwise specified).
PARAMETER
(Note 2)

CONDITIONS

TYP
(Note 4)

MIN

MAX

= 0 to VCC

UNITS

Input Current

VIN

VIH

Logical "1" Input Voltage

DoC

2.0

VCC+1.0

V

VIH

Logical "1" Input Voltage

_40°C

2.2

VCC+1.0

V

VIL

Logical "0" Input Voltage

-0.5

0.8

V

VOH

Logical "1" Output Voltage

IOH

= -40011A

VOL

Logical "0" Output Voltage

IOL

= 3.2 mA

ILOH

Output Leakage Current

VOUT

ILOL

Output Leakage Current

VOUT'" 0.45V, Chip Deselected

ICC1

Power Supply Current

All Inputs = 5.25V, Data
Output Open

III

10

2.4

I1A

V

= 4V, Chip Deselected

0.4

V

10

I1A

-10
70

100

TYP
(Note 4)

MAX

I1A
mA

Capacitance
PARAMETER
(Note 3)

CONDITIONS

MIN

UNITS

CIN

Input Capacitance (All Inputs)

VIN = OV, T A = 25°C,
f = 1 MHz, (Note 2)

7.5

pF

COUT

Output Capacitance

VOUT = OV, T A. = 25°C,
f = 1 MHz, (Note 2)

15.0

pF

AC Electrical Characteristics
(T A within operating temperature range, VCC = 5V ±10%, unless otherwise specified). See AC test circuit and switching time
waveforms.
.

PARAMETER
tAC

Chip Select Access Time

tOFF

Output Turn OFF Delay

tA

Address Access Time

MIN

CONDITIONS
See AC Test Circuit; tAC and tA Measured to
Valid Output Levels with tr and tf of Input
<20 ns, tOFF Measured to <±20 I1A Output
Current

TYP
(Note 4)

MAX

UNITS

120

ns

100

ns

450

ns

\

Note 1: "Absolute Maximum Ratings" are those values beyond which the. safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Positive true logic notation is used: logical "'"

= most positive

voltage level, logical "0"

Note 3: Capacitance is guaranteed by periodic testing.
Note 4: Typical. values are for T A = 25" C and nominal supply voltage.

7-31

= most negative voltage

level.

Switching Time Waveforms and AC Test Circuit

X~____________~x_____

2.DV
ADDRESS
-'

ADDRESS VALID

D.BV

X__________~x~__~

2.DV
CHIP SELECT

CHIP SELECT VALID

D.BV
~H

OUTPUT -

_ _ _ _TRI·STATE@
___ -

VOL

-~ _

l-t

--<

_t

AC

OFF

DATA VALID

-\

r-

-\

FIGURE 1. Address Precedes Chip Select
2.DV ---------~

r------------"' r---X~

X

ADD:E:~

____

r---+-t-----------------tA-1

X---+--______-,-________

CHIP SELECT
2.DV - - - - - " " " \
D.BV
•

VOH
TRI·STATE'"

.....

-<

Xi---------

OU~~~___
- __
-__
- ___
- -__-__
- ___~_ _ _D_A_T_A_IN_V_AL_IO_ _- J

' - -_ _
D_AT_A_V_A_lI_D_ __

FIGURE 2. Address Follows Chip Select

TEST
POINT

~

.....
lDOPF*r

":"

:

25k

~

* Includes jig capacitance

ROM Programming Information
ROM programs for the MM52116 can be supplied to
National in a number of means:
A. 2708 PROM sets
B. 2516 PROM (or equivalent)
C. 2716 PROM (or equivalent)
D. Intellec HEX punched paper tape
E. Binary punched paper tape
Since the MM52116 ha's programmable chip selects, it is
imperative that chip select information be provided
along with the ROM program. The information should
be supplied as shown:
CS1 is to be programmed logical _ _ _ (Hi or Lo)
CS2 is to be programmed 10gical _ _ _ (Hi or Lo)
CS3 is to be programmed 10gical _ _ _ (Hi or Lo)

handled internally via a sophisticated computerized
system. The original input device (PROM, tape, etc.) is
read, the data is reprocessed to formats required by
various production machines, and the final reconstructed
data is then compared back to the original input device.
The verification package returned to the customer for
approval will consist of a listing of the program and a
PROM or tape which matches the data National will use
to create the programmed MM52116. In a normal
situation, the verification package returned to the customer for approval, because of the system described,
may consist of the original PROM or tape submitted by
the customer. This program data, now in National's
production format, is stored in archives for future customer re-orders.

Given any of the above means of program data is received by National, verification of ROM program:: is

7-32

~Nalional

MOS ROMs

U Semiconductor
MM52132 32,768·Bit (4096 x 8) MAXI·ROM™
General Description

Features

The MM52132 is a static MOS 32,768-bit read-only
memory organized in a 4096-word-by-8-bit format.
I t is fabricated using N-channel enhancement and
depletion-mode technology which provides complete
DTL/TTL compatibility and single power-supply operation.

•
•
•

Fully decoded
Single 5V power supply ±10% tolerance
Inputs and outputs TTL compatible

•

Outputs drive 2 TTL loads and 100 pF

•
•

Static operation
TRI-STATE outputs for bus interface

Two programmable chip selects controlling the TR 1ST ATE® outputs allow for memory expansion.

•
•

Programmable chip selects
4096-word-by-8-bit organization

Programming of the memory array and chip-select
active levels is accomplished by changing two masks
du ring fabrication.

•

Maximum access time - 450 ns

•

I ndustry standard pin outs

Applications
•

Microprocessor instruction store

•
•

Control logic
Table look-up

Block' and Connection Diagrams

Dual-in-Line Package
AD

01

24

Al
Al

Vce

02

A2

03

A3

04
ROM
ARRAY

ROW DECODE

A4

05

A6

23 A8

A5

22 A9

06

A2

A6

01

Al

08

20

A3

A5

Al

21

A4

19 AID
18 All
11

AD

rr

A8

A9

AID

All

W
CSI

08

16 01

01
DEC.

eS2
CS1

02 10

15 06

11

14 05

GND 12

13 04

03

TOPV1EW

CS2

Order Number MM52132D
See NS Package D24C
Order Number MM52132N
See NS Package N24B

7-33

Absolute Maximum Ratings

Operating Conditions

(Note 1)

Voltage at Any Pin
-0.5V to +6.5V
-65°C to +150°C
Storage Temperature Range
Power Dissipation
lW
300°C
Lead Temperature (Soldering, 10 seconds)

Operating Temperature Range

DC Electrical Characteristics
(T A within operating temperature range, VCC

= 5V ±10%, unless otherwise specified).

PARAMETER
(Note 2)

CONDITIONS

MIN

MAX

a to VCC

10

III

Input Current

VIH

Logical "1" Input Voltage

2

VIL

Logical "0" Input Voltage

-0.5

VOH

Logical "1" Output Voltage

IOH = -200 /lA

VOL

Logical "0" Output Voltage

IOL

ILOH

Output Leakage Current

VOUT = 4V, Chip Deselected

ILOL

Output Leakage Current

VOUT = 0.45V, Chip Deselected

ICCl

Power Supply Current

All Inputs = 5.25V, Data

VIN =

TYP
(Note 4)

VCC+1.0
0.8

UNITS
/lA
V
V
V

2.4

= 3.2 mA

0.4

V

10

/lA

-20
100

130

/lA
mA

Output Open

Capacita nce
PARAMETER
(Note 3)

CONDITIONS

Input Capacitance (All Inputs)

MIN

TYP
(Note 4)

V I N = OV, T A = 25° C,

MAX

UNITS

7.5

pF

15.0

pF

f = 1 MHz, (Note 2)
COUT

Output Capacitance

VOUT = OV, T A

= 25°C,

f = 1 MHz, (Note 2)

AC Electrical Characteristics
(T A within operating temperature range, Vce = 5V ±10%, unless otherwise specified). See AC test circuit and switching time
waveforms.

CONDITIONS

PARAMETER
tAC

Chip Select Access Time

tOFF

Output Turn OFF Delay

tA

Address Access Time

MIN

TYP
(Note 4)

MAX

UNITS

See AC Test Circuit. All Times (Except tOFF)

120

Measured to 1.5V Level with tr and tf of

100

ns

450

ns

Input < 20 ns, (Figures 1 and 2), tOFF TR I·ST ATE
Output Level Measured to Less than ±20 /lA

ns

Output Current

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Positive true logic notation is used: logical "1" ; most positive voltage level, logical "0" = most negative voltage level.
Note 3: Capacitance is guaranteed by periodic testing.
Note 4: Typical values are for T A; 25° C and nominal supply voltage.

7·34

AC Test Circuit and Switching Time Waveforms
IV
TEST
POINT

2.4V

1.IV

ADDRESS
R[

D.4V

1.66K

2.4V - - - - " " " ' " , . - - - - - - , 1.,---

CIIiPSElECT
O.4V----J

IOOPF*r
TRI·STATE"··

OUTPUT

-----f-----{
tAC

*Includes jig capacitance

FIGURE 2. Address Follows Chip Select

FIGURE 1. Address Precedes Chip Select

Custom ROM Programming
INFORMATION NEEDED
So that National can better serve its customers, the following information must be submitted with each ROM order.
NATIONAL PART NUMBER

National Semiconductor Corporation

2900 Semiconductor Dr .• Santa Clara. CA. 95051
TWX 910·339·9240
Phone (408) 737·5000

ROM LETTER CODE (NATIONAL USE ONLY)

NAME

DATE

ADDRESS

CUSTOMER PRINT OR ID NO.

CITY

STATE

TELEPHONE

ZIP

PURCHASE ORDER NO.

J NAME OF PERSON NATIONAL CAN CONTACT (PRINT) AUTHORIZED SIGNATURE

CHIP SELECT INFORMATION

LOGIC

CS1

o POS

JDATE

o NEG

CS3

.1 CS2

Tape Entry Format
A. Binary Complement Format
000 a a a
00 00
a a
000
a 00
Punched
Paper Tape

-Bitl

000 0 0
000
00
000
00
00 00 0
00 00 0

11

--BitS

~:::;

Word
Word
Word
' - - - - - - - - Word
' - - - - - - - - Start

Com,l.m",

2 Complement
2 .
1 Complement
1

POSITIVE Logic: A punch is a "1" or most positive voltage. Omission of a punch
is a "0" or the more negative voltage.

Pre·Programmed PROM
B. Hex Format (I ntel Standard Hex)
•
•
•

2708
2716
Or combinations of the above to make 16k, 32k
or 64k bits.

7-35

MOS ROMs

~National

~ Semiconductor
MM52164 65,536-Bit (8192 x 8) MAXI-ROMTM
General Description

Features

The MM52164 is a static MOS 65,536-bit read-only
memory organized in an 8192-word by 8-bit format.
It is fabricated using N-channel enhancement and
depletion-mode technology which provides complete
DTL/TTL compatibility and single power-supply operation.

•
•
•

One programmable chip select controlling the TRISTATE® outputs allow for memory expansions.
Programming of the memory array and chip-select
active levels is accomplished by changing two masks
during fabrication.

Fully decoded
Single 5V power supply ±10% tolerance
Inputs and outputs TTL compatible

•

Outputs drive 2 TTL loads and 100 pF

•
•

Static operation
TRI-STATE outputs for bus interface

•
•
•

Programmable chip select
8192-word-by-8-bit organization
Maximum access time - 450 ns

•

Industry standard pin outs

Applications
•

Microprocessor instruction store

•
•

Control logic
Table look-up

Block and Connection Diagrams

Dual-In-Line Package
AD

01

AI

02

24

A1

2J

A6
A2

AS

OJ
22 A9

AS
AJ
A4

Vee

04

1192 X I
ROM
ARRAY

ROW DECODE

21

A4
05

20

AJ
AS

06

A6

01

A7

06

r

DEC.

rr

AI

A9

AID

All

Al2

A12
eSl

19 AID

AZ

lB All

AI

11

AD

OB

16 01

01
10

15 06

OJ 11

14 05

02

GND

13

12

04

TOPVIEW

CSI

Order Number MM52164D
See NS Package D24C
Order Number MM52164N
See NS Package N24B

7-36

Absolute Maximum Ratings

Operating Conditions

(Note 1)

Voltage at Any Pin
-0.5V to +6.5V
-65°C to +150°C
Storage Temperature Range
Power Dissipation
1W
300°C
Lead Temperature (Soldering, 10 seconds)

Operating Temperature Range

DC Electrical Characteristics
(T A within operating temperature range, VCC = 5V ±10%, unless otherwise specified).

PARAMETER
(Note 2)

CONDITIONS

TYP
(Note 4)

MAX

= 0 to VCC

10

III

Input Current

VIH

Logical "1" Input Voltage

VIL

Logical "0" Input Voltage

VOH

Logical "1" Output Voltage

VOL

Logical "0" Output Voltage

IOL = 3.2 mA

ILOH

Output Leakage Current

VOUT

= 4V, Chip Deselected

ILOL

Output Leakage Current

VOUT

= 0.45V, Chip Deselected

ICCl

Power Supply Current

All Inputs

VIN

MIN

2.2

/lA

VCC+l.0

V

0.6

V

-0.5

V

2.4

IOH = -200/lA

UNITS

0.4

V

10

pA

-20

= 5.25V, Data

100

130

pA
mA

Output Open

Capacitance
PARAMETER
(Note 3)

CONDITIONS

Input Capacitance (All Inputs)

Output Capacitance

TYP
(Note 4)

= OV, T A = 25°C,
= 1 MHz, (Note 2)

VIN
f

COUT

MIN

VOUT

= OV, T A = 25°C,

MAX

UNITS

7.5

pF

15.0

pF

f = 1 MHz, (Note 2)

AC Electrical Characteristics
(T A within operating temperature range, VCC = 5V ±10%, unless otherwise specified). See AC test circuit and switching time
waveforms.

CONDITIONS

PARAMETER
Chip Select Access Time

See AC Test Circuit. All Times (Except tOFF)

tOFF

Output Turn OFF Delay

Measured to 1.5V Level with tr and tf of

tA

Address Access Time

tAC

Input

< 20 ns, (Figures

1 and 2), tOFF TRI·STATE

Output Level Measured to Less than ±20 pA

MIN

TYP
(Note 4)

MAX

UNITS

120

ns

100

ns

450

ns

Output Current

Note 1: "Absolute Maximum Ratings" are those val'ues beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Positive true logic notation is used: logical "'" = most positive voltage level, logical "0" = most negative voltage level.
Note 3: Capacitance is guaranteed by periodic testing.
Note 4: Typical values are for T A = 25° C and nominal supply vol tage:

7-37

III

AC Test Circuit and Switching Time Waveforms
sv
TEST
POINT

Z.4V

ADDRESS

Rl
1.66K

I.5V

O.4V

·Z.4V----""'\

r-----"""""I

CHIPSElECT

lDOPf*r

O.4V----J

OUTPUT

TRI·STATE®

TRI·STATE"'
-----t-----<

OUTPUT

-----(/J,!J,

'f2lddiiL~

*Includes jig capacitance

FIGURE 1. Address Precedes Chip Select

FIGURE 2. Address Follows Chip Select

Custom ROM Programming
INFORMATION NEEDED
So that National can better serve its customers, the following information must be submitted with each ROM order.
NATIONAL PART NUMBER

National Semiconductor Corporation
2900 Semiconductor Dr., Santa Clara. CA. 95051
TWX 910-339-9240
Phone (408) 737-5000

ROM LETTER CODE (NATIONAL USE ONLY)

NAME

DATE.

ADDRESS

CUSTOMER PRINTOR IDNO.

CITY

STATE

TELEPHONE

ZIP

PURCHASE ORDER NO.

I NAME OF PERSON NATIONAL CAN CONTACT (PRINT) AUTHORIZED SIGNATURE

LOGIC

CHIP SELECT INFORMATION

o

I

CSI

POS

IDATE

o

NEG

CS3

CS2

Tape Entry Format
A. Binary Complement Format
-Bitl

000 0 0 0
00 00
0 0
000
0 00
Punched
Paper Tape

000 0 0
000
00
000
00
00 00 0
00 00 0

0
0
0
0
--BitS

\! \I

Wo.d 3 Com,l,m,"
~Word3

Word
Word
Word
L------Word
L------Start

2 Complement
2
1 Complement
1

POSITIVE Logic: A punch is a "1" or most positive voltage. Omission of a punch
is a "0" or the more negative voltage.

Pre-Programmed PROM
B. Hex Format (Intel Standard Hex)
•
•
•

2708
2716
Or combinations of the above to make 16k, 32k
or 64k bits.

7-38

~National

MOS ROMs

~ Semiconductor

PREVIEW

MM52264 MAXI-ROM™ 65,536-Bit Clocked
Read Only Memory
General Description
The MM52264 is a clocked MOS 65,536-bit read-only
memory organized in an 8192-word-by-8-bit format.
It is fabricated using N-channel enhancement and
depletion-mode technology which provides complete
DTL/TTL compatibility and single power-supply operation. Programming of the memory array is accomplished by changing two masks during fabrication.

Power dissipation increases during a read operation;
however once the output data is latched in the TR 1ST ATE® output buffers, most of the dynamic circuitry is automatically switched off to conserve power.
The output data remains valid as long as CE is maintained at a "0" voltage level. Switching CE to a "1"
voltage level will return the device to the standby
mode and all data outputs to a high impedance OFF
state.

The MM52264 was designed for those ROM applications
requiring fast access time and low power dissipation.
Dynamic circuitry has been used extensively to reduce
access time. The util ization of a clock input allows
the device to be put into a low power standby mode
during inactive periods. The device is put into the
standby mode by maintaining the clock input CE
at an input "1" voltage. CE must be maintained at
a "1" voltage for the minimum specified time (tp)
to allow for adequate precharging of the internal dynamic circuitry.

Features

After the address data has been applied to the device,
a read operation is initiated by bringing CE to an input
"0" voltage. The falling-edge of CE triggers the generation of a series of internal clock signals which latch
address data in address buffers, decode addresses into
row and column lines, and enable output sense amplifiers and buffers. Since the address is latched' in address
buffers, the input address data can be changed during
a read operation after the address hold time (tAH)
specification is met.

•
•
•

Fully decoded
Single 5V power supply ±1 0% tolerance
Inputs and outputs TTL compatible

•

Outputs drive 2 TTL loadsand 100 pF

•
•
•

Clocked operation
TRI·STATE outputs for bus interface
8192-word-by-8-bit organization

•
•

Maximum access time - 300 ns
Industry standard pin outs

Applications
II

Microprocessor instruction store

•
•

Control logic
Table look-up

Block and Connection Diagrams
Dual-In-Line Package

01
02
0:
04

14

A1

Vee

13

A6

A8

11 A9

A5

11

A4

All

05
06

10

A3

19 AID

A2
01

18

Al
08

11

AD

16

01
02
03
GNO

A8

A9

AID

All

Al2

7-39

CE

10

15

11

14

11

13

TOPVIEW

A11
OB

01
06
05
04

Absolute Maximum Ratings

Operating Conditions

(Note 1)

Voltage at Any Pin
-0.5V to +6.5V
Storage Temperature Range
-65°C to +150°C
Power Dissipation
lW
Lead Temperature (Soldering, 10 seconds)
300°C

Operating Temperature Range

DC Electrical Characteristics
(T A within operating temperature range, VCC = 5V ±10%, unless otherwise specified).
PARAMETER
(Note 3)

CONDITIONS

MIN

TYP
(Note 4)

MAX

VIN = 0 to VCC

III

Input Current

VIH

Logical "1" Input Voltage

2.0

VIL

Logical "0" Input Voltage

-0.5

UNITS

10

/lA
V

VCC+l.0
0.8

V

VOH

Logical "1" Output Voltage

IOH = -200 pA

VOL

Logical "0" Output Voltage

IOL = 3.2 mA

0.4

V

ILOH

Output Leakage Current

VOUT = 4V, Chip Deselected

10

/lA

2.4

ILOL

Output Leakage Current

VOUT = 0.45V, Chip Deselected

ICCl

Power Supply Standby Current

All Inputs = 5.25V, Data

ICC2

Power Supply Active Current

V

-10

pA

10

15

mA

30

50

mA

MAX

UNITS

Output Open

Capacitance
PARAMETER
(Note 3)
CIN

I nput Capacitance (All Inputs)

CONDITIONS

MIN

TYP
(Note 4)

VIN = OV, T A = 25°C,

7.5

pF

15.0

pF

f = 1 MHz, (Note 2)
COUT

Output Capacitance

VOUT = OV, TA = 25°C,
f = 1 MHz, (Note 2)

AC Electrical Characteristics
(T A within operating temperature range, VCC = 5V ±10%, unless otherwise specified). See AC test circuit and switching time
waveforms.
PARAMETER
tc

CE Cycle Time

CONDITIONS

MIN

See AC Test Circuit and Figure 1.

TYP
(Note 4)

MAX

450

UNITS
ns

All Times (Except tOFFI
tp

CE Precharge Time

150

ns

tCE

CE Pulse Width

300

ns

tAH

Address Hold Time

50

ns

0

ns

from CE
tAS

Address to CE Setup
Time

tAC

CE to Output' Access

300

ns

150

ns

Time
tOFF

Output Turn OF F

Measured to 1.5V TRI·STATE

Delay

Level with tr and tf of Input

< 20 ns

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Positive true logic notation is used: logical "1" = most positive voltage level, logical "0" = most negative voltage level.
Note 3: Capacitance is guaranteed by periodic testing.
Note 4: Typical values are for T A = 2SoC and nominal supply voltage.

7-40

Section 8

Character Generators

The Character Generators included in this section
represent very cost effective solutions to problems
arising in the design and implementation of CRT
display subsystems. National's innovations in these
devices in conjuction with the DP8350 series of CRT
Controllers have assisted in the growth of this very important marketplace. Contact your local National
representative for costs and other assistance.

Bipolar
Character Generators

~National

Character Generators

D Semiconductor
DM8678 Bipolar Character Generator
General Description
The DM8678 is a 64-character bipolar character generator
with serial output designed primarily for the CRT display marketplace, and packaged in a standard 16-pin DIP.
The DM8678 incorporates several CRT system level
functions, as well as a 7 x 9 or 5 x 7 row scan character
font. The DM8678 performs the system functions of
parallel to serial shifting, character address latching,
character spacing and character line spacing. These
system functions have required extra packages in the
past.

the character addresses "fall through" the latch. And
when the address latch control signal goes low, the
character addresses are latched.

Features

Shifted characters can be generated by the on-chip
subtractor.
The clear input
Load enable is
the line clock
triggered. When

and the load enable input are active low.
synchronous with the dot clock_ Both
and the dot clock are positive edgethe address latch control signal is high,
ROW SCAN

7x9

DM8678BWF

X

DM8678CAE

X
X

X
X

DM8678CAB
DM8678CAH
DM8678CAD
DM8678BTK
DM8678CAS

X
X
X
X

•

64-character-row scan

•
•

5 x 7 or 7 x 9 font
Shifted lower case descending characters

•
•
•
•

Serial output
16-pin package
16 MHz min clock rate
On-chip input latches

•
•

On-chip shift register
On-chip dot blanking

•
•

On-chip row blanking
TRI-STATE® output

5x7

PACKAGE

FONT

N, J

Upper Case Block Letters
Shifted Lower Case Block

N, J

X

Upper Case Block Letters

N, J

X

Shifted Lower Case Block

N, J

X
X
X

Kata Kana

N, J

Upper Case Script Letters

N, J

IBM 3741 Selectric

N,J

Block Diagram

Connection Diagram
Dual-In-Line Package
16

AJ

ADDRESS LATCH
CONTROL

Order Number
DM8678XXX/J
See NS Package J16A

A6

A5

15

A2
AI
ADDRESS LATCH
CONTROL

64 X 64 BIT
FONT
MATRIX

DM8678XXX/N
See NS Package N16A

13

4

A6

12 OUTPUT
II

LINE CLOCK

10

CLOCK CONTROL

AJ

A4
A5

Order Number
A4

VCC

LOAD

mID

DOT CLOCK

GIIID
A2
TOP VIEW
AI

Logic Symbol
ADDRESS LATCH
CONTROL
AI

CO~~~~~----f-'\1

A2
A3
LINE
CLOCK

A4
A5
Ai

fiDffi----------~

SERIAL
OUTPUT

DOT
CLOCK

LOAD

mm

OUTPUT

mID
LIlliE
CLOCK

8-3

rnABTI

OUTPUT

CLOCK
CONTROL

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Absolute Maximum Ratings

Operating Conditions
MIN

MAX

:E

Supply Voltage
Input Voltage
\
Output Voltage
Storage Temperature
Lead Temperature (Soldering, 10 seconds)

Supply Voltage (Vee)

4.75

5.25

Ambient Temperature (T A)

0

+70

°e

Logical "0" Input Voltage (Low)

0

0.8

V

Logical "1" Input Voltage (High)

2.0

5.5

V

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-o.5V to +7V
-1.5V to +5.5V
-o.5V to +5.5V
--65° C to +150°C
300°C

DC Electrical Characteristics

UNITS
V

(Note 2)
CONDITIONS

PARAMETER

MIN

= Max, VIN = 0.45V

IlL

Input Load Current, All Inputs

VCC

IIH

Input Leakage Current, All Inputs

VCC = Max, VIN = 2.4V

II

Input Leakage Current, All Inputs

VCC = Max, VIN

= 5.5V

VOL

Low Level Output Voltage

VCC= Min, IOL

= 16 mA

VIL

Low Level Input Voltage

VCC';' Min

VIH

High Level Input Voltage

VCC

= Min

Vc

Input Clamp Voltage

VCC

= Min,

CIN

Input Capacitance

VCC

= 5V,

Co

Output Capacitance

VCC

TYP

MAX

-0.8

-1.6

0.35

pA

1

mA

0.45

V

0.80

V
V

-0.8

= 2V, TA = 25°C,

VIN

mA

40

2.0

= -12 mA

liN

UNITS

-1.5

V

4.0

pF

6.0

pF

1 MHz

= 5V,

Vo

= 2V, TA = 25°C,

1 MHz, Output "OFF"
ICC

Power Supply Current

VCC

= Max, All

115

Inputs Grounded,

145

mA

All Outputs Open
TRI·STATE PARAMETERS

= OV,

ISC

Output Short·Circuit Current

Vo

1HZ

Output Leakage

VCC

VCC

= Max

-15

= Max, Vo = 0.45 to 2.4V,

-50

mA

±40

pA

Chip Disabled
VOH

Output Voltage High

AC Electrical Characteristics
PARAMETER

IOH

= -2 mA

2.4

V

3.2

(With standard load) (Note 2)
CONDITIONS

MIN

TYP

MAX

UNITS

Access Time
TOO

Dot Clock to Output

35

55

ns

TEA

Output Enable

20

45

ns

TER

Output Disable

20

45

ns

Set·Up Time
ns

TSl

Load to Dot Clock

40

25

TS2

Address to Load

350

200

TS3

Clear to Load

350

ns

TS4

Control to Line Clock

40

ns

TS5

Line Clock to Load

950

ns

TS6

Address to Address Latch

40

ns

flS
ns

See Switching Time Waveforms

ns

Hold Time
THl

Load from Dot Clock

0

TH2

Address from Load

0

TH3

Control from Line Clock

100

ns

TH4

Address from Address Latch

40

ns

8·4

AC Electrical Characteristics

(Continued) (With standard load) (Note 2)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Minimum Pulse Width
TW1

Line Clock

40

ns

TW2
TW3

Clear

40

ns

30

ns

TW4

Load

40

ns

TW5

Address Latch

40

Dot Clock

fMAX

See Switching Time Waveforms

Maximum Clock Frequency

16

ns
20

MHz

Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that the device
may be operated at these values.
Note 2: These limits apply over the entire operating range unless stated otherwise. All typical values are for VCC = 5V and T A = 25°C.

Standard Test Load
VCC

300

lk

•

Input waveforms are supplied by a pulse generator
having the following characteristics: PRR = 1 MHz,
ZOUT = 50 n, tr < 5 ns and tf < 5 ns (between
1.0V and 2.0V).
• TOO is measured with output enable at a steady low
level.

Switching Time Waveforms
~TS6~~------------TH4------------~

3V------"'"'
ADDRESS INPUT
OV-----------J

~====~T;S2~==~------~-------~=-=-=-~~TH2

ADDRESS
LATCH CONTROL

LINE CLOCK

CLOCK CONTROL

LOAD ENABLE

DDT CLOCK

OUTPUT ENABLE

OUTPUT

8·5

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b) Output

a) Address Latch

ADDRESS LATCH
CONTROL

FUNCTION
PERFORMED

OUTPUT
ENABLE

STATE OF
THE OUTPUT

0

Latched
Fall Through

1

0

Output Hi·Z
Data Out

1

c) 4-Bit Line Counter

CLOCK CONTROL

LINE CLOCK

CLEAR

H
X

.J"

H
L

X

L

X

H

""""L

H
H

LINE COUNTER
Increment line counter
Asynchronous clear
resets cou nter
Clock inhibited
No change on high·to·
low clock edge

X = Don't care

Definitions
Load Enable: Active low load command which routes
data from the character ROM to the "D" inputs of the
7-bit shift register.'

A 1-A6: Character address. A 6-bit code which selects
1 of the 64 characters in the font.
Clear: Active low clear for mod 16 row counter, (can be
used to truncate mod 16 counter).

Dot Clock: A low·to·high transitIOn of the dot clock
loads the shift register if load enable is low or shifts
data if load enable is high.

Line Clock: Clock that advances the line counter.
Advances counter on the low·to·high transition.
Clock Control: Enables line clock when
disables line clock when low.

Output Enable: An active low output enable. When high
the output is in theHi·Z state.

high and
Output: A TTL TR I·ST ATE output buffer.

Functional Description
To select a character, a 6-bit binary word must be
present at the address inputs A 1-A6 when the add; ess
latch contra) is high. This address can be latched by
bringing the address latch control signal low after a
40 ns set·up time. When the clear input receives a low
pulse, the counter is reset to zero. The shift register can
be loaded (TS2 ns) after the character is addressed.
Data, representing one horizontal line of the addressed
character, is available at the output when the load
enable input is brought low. As shown in Figure 1,
valid data arrives serially at the ou'tput. Dot clock
pulses beyond that required to shift out one line of the
character will add lows to the end of character. This
provides a horizontal spacing between characters.

pulses at the line clock input. Any additional line
clocks beyond that required to display the character
will put a vertical space between characters. This spacing
can be truncated by bringing the clear input low.
Detailed system application infomation is contained in
application note AN-167 available from National.
A two character display example is shown in Figure 3
and a typical system timing waveform is shown in
Figure 4.
A chip select input is provided for expansion of the
character font. The various standard fonts are shown in
Figures 5, 6, 7, 8, 9 and 10.

Figure 2 shows how the counter sequences through the
rows of addressed lines with the application of clock

8-6

Functional Description

(Continued)

Character Cycle - ROM data corresponding to one
line of characters is loaded into the shift register TS2
after the ROM is addressed. When load enable goes low,
ROM data is allowed to be present at the D input of
the shift register via the MUX. The first bit of the ROM
data is transferred to the output at the next low-to-high
transition of the dot clock. After load enable goes back
high, the second to seventh clock pulses shift out the
rest of the selected row of the addressed character.
Additional clock pulses will shift out low data used
for spacing.

LINE
CLOCK

"
V

Line Cycle - The line counter is a mod 16 counter.
A low-to-high transition of the line clock advances the
line counter to the next count_ If, for any reason, the
counts need to be truncated, a low signal at the Clear
input resets the counter to zero. The clock control may
be used as a line clock disable_ A high signal at the line
clock control terminal enables the counter and a low
signal disables the line clock_

r
J

....JX'___ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

CHARACTER
_________
AOORESS
INPUT

C

DOT CLOCK

OUTPUT

OUTPUT

(SE~~~TE)

/

[\
[\
------'"
~---~
~-~

~--------VALID OATA OUT - - - - - - - - - - 1

1-1

Note. Output goes and stays low following the leading edge of the eighth Dot-Clock pulse until Load enable is enabled again and new parallel data
is loaded into the shift register.
FIGURE 1. Character Cycle

CHARACTER
ADDRESS
INPUT _ _ _

~

-+-'

_______

LINE
CLOCK

CLOCK
CONTROL
DISPLAY
SECOND LINE
OF N CHARACTERS

OISPLAY
FIRST LINE
OF N CHARACTERS

FIGURE 2. Line Cycle

8-7

DISPLAY
THIRD LINE
OF N CHARACTERS

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Functional Description (Continued)

::!:
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!-.>--------TWO CHARACTER CYCLE
Al~~----------------~

--------.1

_________________
1

A2-------------------------------------------------ASCII
COD ED
ADDRESS
INPUTS

A3---,
......- - - - - - - - - - - - - - - - - - - -...
A4 - - ,.._______________--'

A6-----------------------------------------------LOAD
ENABLE

L.-I

u

u

DOT
CLOCK

CLOCK
LINE
OUTPUT
CO NTROL, CLOCK CLEAR ENABLE

ADDITIONAL
LINE COUNTS
FOR VERTICAL
SPACE

FIGURE 3. Example of Two Character Display Timing

8·8

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~National

Character Generators

D Semiconductor

ADVANCE INFQRMATION

DM76S128/DM86S128 Bipolar Character Generator
General Description
The DM76S128/DM86S128 is a 128-character bipolar
character generator with serial output designed primarily
for the CRT display marketplace, and packaged in a
standard 16-pin DIP. The DM76S128iDM86S128
incorporates several CRT system level functions, as
well as a 7 x 9 or 5 x 7 row scan character font. The
DM76S128/DM86S128 performs the system functions
of parallel to serial shifting, character address latching,
character spacing and character Iine spacing. These
system functions have required extra packages in the
past.

the character addresses "fall through" the latch. And
when the address latch control signal goes low, the
character addresses are latched.

Features
•

• Custom fonts available with shift options
• Serial output
• 16-pin package

Shifted characters can be generated by the on-chip
adder/subtracter.

• 35 MHz typical clock rate
• On-chip input latches
• On-chip shift register

The clear input and the load enable input are active low.
Load enable is synchronous with the dot clock. Both
the Iine clock and the dot clock are positive edgetriggered. When the address latch control signal is high,
7x9

• On-chip dot blanking
• On-chip row blanking
• Low power-400 mW typical

5x7

x

DM76S128CNC/DM86S128CNC
DM76S128CND/DM86S128CND
DM76S128COH/DM86S 128COH
DM76S128COJ/DM86S128COJ

128 character-row scan

• 5 x 7 or 7 x 9 font

x
x
x

FONT
Upper and Shifted Lower Case Block
Upper and Lower Case Block
ASCII CHARACTER SET
ASCII CHARACTER SET

PACKAGE
N, J
N, J
N, J
N, J

Connection Diagram

Block Diagram

Dual-ln·Line Package
ADDRESS LATCH
CONTROL

16

A2

A6

Order Number
DM76S128XXX* /J
or DM86S128XXX*/J
See NS Package J16A
Order Number
DM76S128XXX*/N
or DM86S128XXX* IN
See NS Package N16A

65X 12B·BIT
FDNT
MATRIX

ADDRESSLATCH
CDNTRDL

A3

14

AD
AS

VCC

15

Al

A4

13

4

A5

12

mAR

11

LINE CLDCK

A6
OUTPUT

10 LDADrnAm

CLDCK CDNTROL

9

GND

DOT CLOCK

TOPVIEW

Logic Symbol
CO~~~~~ -----f-"

ADDRESS LATCH
CDNTROL
AD

LINE
CLOCK
SERIAL
OUTPUT

CITliR -'------~

DOT
CLOCK

OUTPUT

Al
A2
A3
A4
AS
A6

OOT CLOCK

LOAD
ENABIT

* alpha pattern designators

LINE
CLOCK

8-26

CLOCK
CONTROL

Absolute Maximum Ratings

C

Operating Conditions

(Note 1)

:s::
en
.....
~
CJ)

Supply Voltage
Input Voltage
Output Voltage
Storage Temperature
Lead Temperature (Soldering, 10 seconds)

DC Electrical Characteristics

MIN

MAX

UNITS

4.5
4.75

5.5
5.25

V
V

I\)

Supply Voltage (Vee)
DM76S128
DM86S128

-D.5V to +7V
-1.5V to +5.5V
-D.5V to +5.5V
o
-65°e to +150 e
0
300 e

Ambient Temperature (TAl
DM76S128
DM86S128

-55
0

+125
+70

°e
°e

Logical "0" Input Voltage (Low)

0

0.8

V

Logical "1" Input Voltage (High)

2.0

5.5

V

S!!
C

:s::
en
.....
Q)

CJ)

I\)
Q)

(Note 2)
CONDITIONS

PARAMETER

MIN

TYP

MAX

UNITS

IlL

Input Load Current

VCC = Max, VIN = 0.45V

-800

IIH

Input Leakage Current

VCC = Max, VIN = 2.4V

40

pA

II

Input Leakage Current

VCC = Max, VIN = 5.5V

1

rnA

VOL

Low Level. Output Voltage

VCC'" Min, IOL = 16 mA

VOH

Output Voltage High

IOH = -2 mA

0.35

VIL

Low Level Input Voltage

VCC = Min

VIH

High Level Input Voltage

VCC = Min

Vc

Input Clamp Voltage

VCC = Min, liN = -12 mA

CIN

Input Capacitance

VCC = 5V, VIN = 2V, TA = 25°C,

Co

Output Capacitance

VCC = 5V, Vo = 2V, TA = 25°C,

2.4

pA

0.45

V

3.2

V
0.80

V

2.0

V
-0.8

-1.5

-.

V

4.0

pF

6.0

pF

1 MHz

1 MHz
ICC

Power Supply Current

100

VCC = Max, All Inputs Grounded,

140

rnA

Output Open
ISC

Output Short·Circuit Current

-15

Vo = OV, VCC = Max

-70

rnA

AC Electrical Characteristics
= -55°C to +125°e, Vee = 4.5V to 5.5V. eL = 50 pF.
o
DM86S128: TA = DoC to +70 e, Vee = 4.75V to 5.25V. eL = 50 pF.
DM76S128: TA

DM76S128

DM86S128

PARAMETER

UNITS
MIN

TYP

MAX

MIN

TYP

MAX

Access Time
TOO

Dot Clock to Output

25

50

25

40

ns

Set Up Time
TS1

Load to Dot Clock

25

7

20

7

ns

TS2

Address to Load

335

54

280

54

ns

TS3

Clear to Load

335

14

280

14

ns

TS4

Control to Line Clock

50

-10

ns

TS5

Line Clock to Load

1140

156

950

156

ns

Address to Address Latch

50

6

40

6

ns

TS6

....:.10

40

Hold'Time
TH1

Load from Dot Clock

5

-6

0

-6

ns

TH2

Address from Load

a

~14

0

-14

ns

TH3

Control from Line Clock

120

23

100

23

ns

TH4

Address from Address Latch

50

3

40

3

ns

Pulse Width

8-27

nil

co

C\I
,..
en
CD

AC Electrical Characteristics

(Continued) (With standard load) (Note 2)

CO

:e
C
CO

C\I
,..
en
CD
~

:e
C

DM86S128

DM76S128
PARAMETER

UNITS
TYP

MIN

MAX

MIN

TYP

MAX

TW1

line Clock

50

12

40

12

ns

TW2

Clear

50

6

40

6

ns

TW3

Dot Clock

25

12

20

12

ns

TW4

Load

40

8

30

8

ns

Address Latch

50

22

40

22

ns

Clock Frequency

18

35

22

35

MHz

TW5
fMAX

Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that the device
may be operated at these values.
Note 2: These limits apply over the entire operating range unles's stated otherwise. All typical values are for Vee = 5V and T A = 2 SoC.

Standard Test Load
Vcc

o

>

:~
~

DEVICE 0.
...... _ _ _ _ _.- ._ _ _ _. .
OUTPUT~
~

T

300

•

Input waveforms are supplied by a pulse generator
having the following characteristics: PRR = .1 MHz,
ZOUT = 50 n, tr < 5 ns and tf < 5 ns (between
1.0V and 2.0V).

3DPF

Truth Tables
B) 4-BIT LINE COUNTER

A) ADDRESS LATCH

ADDRESS LATCH
CONTROL

o
1

FUNCTION
PERFORMED

CLOCK CONTROL

LINE CLOCK

CLEAR

H

--F

H

Latched
Fall Through

X

X

L

L

X

H

~

H
H

X C' Don't care

8-28

LINE COUNTER
Increment line counter
Asynchronous clear
resets counter
Clock inhibited
No change on high·to·
low clock edge

Switching Time Waveforms

JV-------

~~------------TH4------------~

ADDRESS INPUT
DV-----------J ~====~T~S2~==~---------------~=-=-=-~~TH2
ADDRESS
LATCH CONTROL

LINE CLOCK

CLOCK CONTROL

LOAD ENABLE

TWJ-+----t
OOT CLOCK

OUTPUT

Definitions

AO-A6: Character address. A 7·bit code which selects
1 of the 128 characters in the font.

Load Enable: Active low load command which routes
data from the character ROM to the "D" inputs of the
7-bit shift register.

Clear: Active low clear for mod 16 row counter. (can be
used to truncate mod 16 counter).

Dot Clock: A low·to-high transition of the dot clock
loads the shift register if load enable is low or shifts
data if load enable is high.

Line Clock: Clock that advances the line counter.
Advances counter on the low·to·high transition.
Clock Control: Enables line clock when
disables line clock when low.

Output: A TTL BI·STATE output buffer.

high and

8-29

co

,...

N

(IJ

co
co
:?!

c

co
N
,...
(IJ

co
t-:?!

c

Functional Description
To select a character, a 7-bit binary word must be
present at the address inputs AO-A6 when the address
latch control is high. This address can be latched by
bringing the address latch control signal low after a
40 ns set-up time. When the clear input receives a low
pulse, the counter is reset to zero. The shift register can
be loaded (TS2 ns) after the character is addressed.
Data, representing one horizontal Iine of the addressed
character, is available at the output when the load
enable input is brought low. As shown in Figure 1,
valid data arrives serially at the output. Dot clock
pulses beyond that required to shift out one line of the
character will add lows to the end of character. This
provides a horizontal spacing between characters.

shifted by virtue of their placement in the matrix.
Descending characters in the 7 x 9 fonts are shifted (by
th on-chip line shifter/counter) the number of lines
indicated by the number in the upper left hand corner
of the character drawings in the figures.
Character Cycle - ROM data corresponding to one
line of characters is loaded into the shift register TS2
after the ROM is addressed. When load enable goes low,
ROM data is allowed to be present at the D input of
the shift register via the MUX. The first bit of the ROM
data is transferred to the output at the next low-to-high
transition of the dot clock. After load enable goes back
high, the second to seventh clock pulses shift out the
rest of the selected row of the addressed character.
Additional clock pulses will shift out low data used
for spacing.

Figure 2 shows how the counter sequences through the
rows of addressed lines with the application of clock
pulses at the line clock input. Any additional line
clocks beyond that required to display the character
will put a vertical space between characters. This spacing
input low.
can be truncated by bringing the

Line Cycle - The line counter is a mod 16 counter.
A low-to-high transition of the line clock advances the
line counter to the next count. If, for any reason, the
counts need to be truncated, a low signal at the C'l"e"ar
input resets the counter to zero. The clock control may
be used as a line clock disable. A high signal at the line
clock control terminal enables the counter and a low
signal disables the line clock.

crear

A two character display example is shown in Figure 3
and a typical system timing waveform is shown in
Figure 4. The standard fonts are shown in Figures 5,
6, 7 and 8. Descending characters in the 5 x 7 fonts are
J

LlNEv
CLOCK

CHARACTER
ADDRESS
INPUT ________________

X

~

~

_________________________________________________________________

C

DOT CLOCK

OUTPUT

1\

1\

' - - - - _ _ _- - - . - - I

_~

- - - - - - - - - V A L I D DATA OUT

1-1

OUTPUT

(SE~~~TE)

/

~_---J

----------1

Note. Output goes and stays low following the leading edge of the eighth Dot-Clock pulse until Load enable is enabled again and new parallel data
is loaded into the shift register.
FIGU~E

1. Character Cycle

CHARACTER
ADDRESS
INPUT _ _ _ _ _ _ _ _ _ _ _ _ _ _

-+..J

LINE
CLOCK

CLOCK
CONTROL
DISPLAY
FIRST LINE
OF N CHARACTERS

FIGURE 2_ Line Cycle

8·30

OISPLAY
SECONO LINE
OF N CHARACTERS

DISPLAY
THIRD LINE
OF N CHARACTERS

Functional Description

(Continued)

TWO
CHARACTER
CYCLE
OE-HEX-13
AD

I

\

\

Al----.1

ADDRESS
INPUTS

A2----.1

\

Al----.l

\

A4

/

\

A5~

I

AS

lDADE~

U

U

DOT ClK

ClK
CNRl

ADDITIONAL LINE
COUNTS FOR
VERTICAL SPACE

FIGURE 3. Example, Two Character Display Timing - DM86S128CNC

8-31

LINE

CLK

mr

DM76S128/DM86S128
~

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n

2)"

:J

!!.

c

CD

en
n

F40-f-40--j

-o·

'---~

oo

~

-6.

455 n. CYCLE

CHARACTER
AOORESS*
ADDRESS LATCH
CONTROL*
CLEAR

~
-~
~~ J

~
LINE CLOCK
CLOCK
CONTROL

co

iN
I\.')

LOAD

280 n.

OUTPUT

:J
~

r-'

3~

!

2::

950n.

~.-,".~
I

rnm
DOT CLOCK

280n.

(22 MHz DOT RATE)

1-30-

~'\.

~

'f/0'/j

-

ho//f

,~
-40

X

X

X~

-----

VALID DOT DATA

Y

----

~

-X
-I

LOW FOR SPACE---I

*Shown here for operation with dynamic memory _ For static memory operation the address latch control would be tied high and the character
addresses would be stable between each address change occurring 280 ns before the high-to-Iow transition of Load -enable_

FIGURE 4_ Typical System Timing Waveform

Functional Description

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(Continued)

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80008000 •

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0.00.00.0
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0.00.0080
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0.0000000
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8-33

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<
C

Absolute Maximum Ratings

U.
<0

(Note 1)

Voltage at Any Pin
Operating Temperature Range
Storage Temperature Range
Power Dissipation
Lead Temperature (Soldering, 10 seconds)

,...
,...
N

Lt)

:E
:E

-0.5V to +6.5V
D
D
-25 C to +85 C
D
D
-65 C to +150 C
1W
D
300 C

DC Electrical Characteristics

:t
C

(T A within operating temperature range, VCC

= 5V ±10%, unless oth~rwise specified).

u..

<0
,...
,...

PARAMETER
(Note 2)

N

rvp

MIN

CONDITIONS

(Note 4)

MAX
10

VIN = 0 to VCC

Lt)

III

Input Current

:E
:E

VIH

Logical" 1" Input Voltage

2.0

VIL

Logical "0" Input Voltage

-0.5

UNITS
IlA

VCC+l.0

V

0.8

V

V

V

204

VOH

Logical "1" Output Voltage

IOH =-400 IlA

VOL

Logical "0" Output Voltage

IOL = 3.2 mA

004

ILOH

Output Leakage Current

VOUT = 4V, Chip Deselected

10

IlA

ILOL

Output Leakage Current

VOUT = OA5V, Chip Deselected

-10

IlA

ICCl

Power Supply Current

All Inputs = 5.25V, Data
Output Open

70

100

mA

Capacitance
PARAMETER
(Note 3)

CONDITIONS

TYP
(Note 4)

MIN

MAX

UNITS

CIN

Input Capacitance (All Inputs)

VIN = OV, T A = 25°C,
f = 1 MHz, (Note 2)

7.5

pF

COUT

Output Capacitance

VOUT = OV, T A = 25°C,
f = 1 MHz, (Note 2)

15.0

pF

AC Electrical Characteristics
(T A within operating temperature range, VCC = 5V ±10%, unless
waveforms.

PARAMETER
tAC

Chip Select Access Time

tOFF

Output Turn OFF Delay

tAO'

Address Access Time

oth~rwise

specified). See AC test circuit and switching time

CONDITIONS
See AC Test Circuit; tAC and tA Measured to
Valid Output Levels with tr and tf of Input
<20 ns; tOFF Measured to <±20 IlA Output
Current

MIN

TYP
(Note 4)

MAX

UNITS

120

ns

100

ns

450

ns

\

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Positive true logic notation is used: logical "1" = most positive voltage level, logical "0" = most negative voltage level.
Note 3: Capacitance is guaranteed by periodic testing.
Note 4: Typical values are for TA = 2SoC and nominal supply voltage.

8-44

AC Test Circuit and Switching Time Waveforms
5V

RL
1.66k

* I ncludes jig capacitance

2.0V
ADDRESS

------...,.x

O.BV

X
ADDRESS VALID

"-------------------'

"'------

X'-------------"""X

2.0V - - - - - - - - - - - . . . , .
CHIP SELECT

CHIP SELECT VALID

-!

"'---~--

O.BV

l--t

VOH

OFF

OUT~~:-_-----------------TR-I-.S-T-AT-E-®------+_---__--__~
__~_______D_A_T_A_V_A_Ll_D________J~--

-I,c-I

FIGURE 1. Address Precedes Chip Select
2.0V
ADDRESS

----------...,.X

O.BV

X

'---------______

'------

2.0V - - - - - - ' " "
CHIP SELECT
O.BV _ _ _ _ _ _J

1-.--------tA--------~·-1
VOH -------T-R-I.S-T-A-T-E®-R------(--j~--------------...,.X, - - - - - - - - - - - -

OUT~~: - - - - - - - - - - - -

DATA INVALID

\._ _ _ _
DA_T_A_VA_L_I_D_ _ __

FIGURE 2. Address Follows Chip Select

Functional Description
The chip is selected by applying the proper logic levels
to the 3·chip select pins: A 7·bit binary word must be
present at the character address inputs, AO-A6 to select
a character. The dot matrix of selected characters is
generated by cycling the line count address inputs LO-L3
through the line counts necessary to generate the char·
acters. A dot is generated when an output is a "1"
(at VOH).

Figure 3 shows an example of the conditions required at
the address and line count pins to generate the dot matrix
of the character A. Figures 5 and 6 show the character
fonts of the MM52116FDW and MM52116FDX.

8·45

c><
u..

Functional Description

(Continued)
LO L1 L2 L3

co
.....
.....
N

AD

It)

A1

~
~

A2

~
C
u..

A5

DDT
SHIFT
REGISTER

A3
A4

A6

VIDEO OUTPUT

co

.....
.....
N

It)

CHIP SELECT
CS1 CS2 CS3

~
~

0

CHARACTER-ADDRESS
A6- - ~ A4 A3-- - -

0

0

0

0

AO

L3

0
0
0
0
0

0

0
0
0
0

0

0
0

DOT MATRIX
07 - - - - - - - - 01

LINE COUNT
LO
L2
L1

0

0
0

1

0
1

1

0
0

0
1

0
1

1

1

0

O·

0

Note. A "1" = V IH for address, line count and chip select inputs and a "1" = VOH for outputs.

FIGURE 3. Example of Generating the Character A
PERIPHERAL
INTERFACE

VIDEO
INTERFACE

I

I
ITO

I

t--:----""'I--------.....------IATTRIBUTE
OECOOE

I
I

I

MICRO
PROCESSOR

I
I

I
I
I
VIOEO

HORI~~;;~~

I

I} .

_---.;.SY;.;,;N;.;.C.

II

SYSTEM CONTROL BUS
X1

X2

II
FIGURE 4. Typical MM52116FDW and MM52116FDX Application

8·46

3·TERMINAL
MONITOR

Functional Description

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FIGURE 6. MM52116FDX

8·48

0 • • • • 00
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c • • • o.o
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00.00.0
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0000000

Functional Description

s:

s:

(Continued)

(J1
I\)

......
......
m
'T1

C

MM52116FDX ASCII CHARACTER SET IN HEXADECIMAL REPRESENTATION

Character
NUL
SOH
STX
ETX
EOT
ENO
ACK
BEL
BS
HT
LF
VT
FF
CR
SO
SI
DLE
DCl
DC2
DC3
DC4
NAK
SYN
ETB
CAN
EM
SUB
ESC
FS
GS
RS
US

7·Bit
Hexadecimal
Number
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
aD
OE
OF
10
11
12
13
14
15
16
17
18
19
lA
lB
lC

Character
SP
!
"

#
$

%
&
(
)

*

+

/

a
1
2
3
4
5
6
7
8
9
:

;

<

10

=

lE
1F

>
?

7·Bit
Hexadecimal
Number

Character

20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E 3F

@

A
B
C
D
E
F
G
H
I
J

K
L
M
N
0
p

0

R
S
T
U
V
W

X
Y

?
[

\
1

t
+-

8·49

7·Bit
Hexadecimal
Number
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F

Character

\
a
b

c
d
e
f

9

h
i
j
k

I
m
n
0

p
q

..:E
7·Bit
Hexadeci mal
Number
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71

r

72

s

73
74
75
76

t
u
v
w

77

x

78
79
7A
7B
7C
7D
7E
7F

y

z

ALT
ESC
DEL,RUBOUT

s:
s:

(J1
I\)

......
......
m

">
c~

CJ'I

I\)

o

m

3:
-..

o
c

~

Truth Table

CJ'I

I\)

CLOCK

ENABLE

ACTION

1

0

I ncrement counter

"--

0

Increment counter

X

0

No change,

f
0

"--

f

X

0

No change

0

0

No change

1

"--

0

No change

X

X

1

01 thru 04·= 0

f

X

=

o

RESET

m

o

Don't Care

Connection Diagram
Dual-In-line and Flat Package

Voo
16

RESET

04

CLOCK

10

11

COUNTER 1

c

ENABLE

ENABLE

01

12

14

15

R

CLOCK

02

03

Q1

R

COUNTER 2

02

03

TOP VIEW

9-5

04

RESET

VSS

~National

Memory Support Circuits

D Semiconductor
DM7555/DM8555, DM7556/DM8556 TRI·STATE®
Programmable Deca~e/Binary Counters
General Description

Features

These circuits are synchronous, edge-sensitive, fullyprogrammable 4-bit counters. The counters feature both
conventional totem-pole and TRI-STATE outputs; such
that when the outputs are in the high-impedance mode,
they can be used to enter data from the bus lines. In
addition, the clear input operates completely independent
of all other inputs. During the programming operation,
data is loaded into the flip-flops on the positive-going
edge of the clock pulse. To facilitate cascading of these
counters, the MAX COUNT output can be tied directly
into the count enable input.

•

DM7555/8555-Decade counter

•

DM7556/8556-Binary counter
35 MHz

• Typical clock frequency
•

TRI-STATE outputs

•

Fully independent clear

• Synchronous loading
•

Connection Diagram

Cascading circuitry provided internally

Truth Table
J

K

M

CLEAR

On+l

0
1
0
1
X
X

0
0
1
1
X
X

1
1
1
1
0

0
0
0
0
0
1

On

X

1
0
On
D

O·

* Asynchronous Transition
Note: See Timing Diagrams

Logic Diagrams

55

56

Vee" 06l
GND

~

18)

16)

D.

IS)

D.

9-6

13)

Ilc

12)

Do

~National

Memory Support Circuits

~ Semiconductor

DM54LS373/DM74LS373, DM54LS3741DM74LS374
Octal D-Type Transparent Latches
and Edge-Triggered Flip-Flops
General Description
These 8-bit registers feature totem-pole TRI-STATE@
outputs designed specifically for driving highly-capacitive
or relatively low impedance loads_ The high impedance
TRI-STATE and increased high logic level drive provide
these registers with the capability of being connected
directly to and driving the bus lines in a bus-organized
system without need for interface or pull-up components_ They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers.

A buffered output control input can be used to place
the 8 outputs in either a normal logic state (high or low
logic levels) or a high impedance state. In the high
impedance state the outputs neither load nor drive the
bus lines significantly.
The output control does not affect the internal operation
of the latches or fl ip-flops. That is, the old data can be
retained or new data can be entered even while the
outputs are OFF.

The 8 latches of the DM54LS373 are transparent Dtype latches meaning that while the enable (G) is high
the Q outputs will follow the data (D) inputs. When
the enable is taken low the output will be latched
at the level of the data that was set up.

Features

The 8 flip-flops of the DM54LS374/DM74LS374 are
edge-triggered D-type fl ip-flops. On the positive transition
of the clock, the Q outputs will be set to the logic states
that were set up at the D inputs.

•

Choice of 8 latches or 8 D-type flip-flops in a single
package

•
II

TRI-STATE bus driving outputs
Full parallel access for loading

•
•

Buffered control inputs
PNP inputs reduce DC

loading on

data

lines

05

CLOCK

Connection Diagrams and Truth Tables
DM54LS373/DM74LS373
Dual-In-Line Package

Vce
20

08
19

07

08
18

17

06

07

06
14

15

16

DM54LS374/DM74LS374
Dual-In-Line Package

05

13

05
12

ENABLE
G

Vce
20

11

08·
19

08
18

07
17

07

06
15

16

06

05

13

14

12

10

10
OUTPUT
CONTROL

01

01

02

02

03

03

TOPVIEW

ENABLE

0

OUTPUT

H

H

H

H

L

L

L

X

00

G

04

04

GNO

11

OUTPUT 01
CONTROL

01

02

02
03
TOP VIEW

03

D4

CLOCK
t
t

0

OUTPUT

H

H

L

L

L

X

00

When output control is high, the output is disabled to high impedance state; however, sequential
operation of these devices are not affected.

9-7

Q4

GNO

~National

Memory Support Circuits

~ Semiconductor
DM54S240/DM74S24O, DM54S241/DM74S241,
DM54S940/DM74S94O, DM54S941/DM74S941
Octal TRI·STATE® Buffers/Line Drivers/Line Receivers
General Description

Features

These buffers/line drivers are designed specifically to
improve both the performance and PC board density of
T R I-ST ATE® buffers/drivers employed as memoryaddress drivers, clock drivers, and bus-oriented transmitters/receivers. Featuring 400 mV of hysteresis at
each low current PNP data line input, they provide
improved noise rejection and high fanout outputs to
restore Schottky TTL levels completely, and can be used
to drive term inated Iines down to 133Q.

•

High performance Schottky TTL line drivers and/or
receivers in a high density 20-pin package
• TR I-STATE outputs drive bus lines directly
• PNP inputs reduce DC loading on bus lines
• Hysteresis at inputs improves noise margins

Connection Diagrams
DM54S240/DM74S240
Vee
20

Ie

21:

lYl

19

lAl

18

2Y4

2A4
17

lA2

lY2

2A3

16

2Y3

15

lA3

lY3
14

2Y2

2A2
13

lA4

DM54S241/DM74S241
lY4
12

2Yl

Vee

2Al

2G

20

11

GND

III

19

lAl

lYl
18

2Y4

2M
17

lA2

TDPVIEW

DM54S940/DM74S940
lYl

2A4

lY2

11:

lAl

2Y4

lA2

2Y3

2A3

2Y]

15

lA3

lY3

2A2

14

2Y2

lY4

13

1M

12

2Y1

2Al
11

GND

1 Y = 1A when 1 G is low
2Y = 2A when 2G is high
When 1 G is high, 1Y outputs are at a high impedance
Nhen 20 is low 2Y outputs are at a high impedance

io

2C

2A3

16

TOPVIEW

1Y = 1Awhen 10 is low
2Y = 2A when
is low
When 10 is high, 1Y outputs are at a high impedance
When 20 is high, 2Y outputs are at a high impedance

Vee

1Y2

DM54S941/DM74S941

lY3

2A2

lY4

2Al

Vee

211

lYl

2A4

lY2

2A3

lY3

2A2

lY4

2Al

2Y2

lA4

2Yl

GND

lC

lAl

2Y4

lA2

2Y3

lA3

2Y2

1M

2Yl

GND'

TOPVIEW

TDPVIEW

I Y = fA when fo and 2<3 are low
2Y = 2A when 10 and 20 are low

IY
2Y

When,either 1<3 or 2<3 is high, dll, outputs ar,e a high impedance

= lA when 10 and iG are low
= 2A when 10 and 20 are low

When either 10 or 2<3 is high, all outputs are at a high impedance

9-8

~National

Memory Support Circuits

~ Semiconductor

C

""C

---..

(,,)

o

~

C

""C

DP7303/DP8303 8-Bit TRI-STATi:® Bidirectional
Transceiver (Inverting)

Q)
(,,)

o

(,,)

Features
• 8-bit bidirectional data flow reduces system package
count
• Bidirectional TR I-STATE inputs/outputs interface
with bus oriented systems
• PNP inputs reduce input loading
• Output high voltage interfaces with TTL, MOS,
and CMOS
• 48 mA/300 pF bus drive capability

• Pinouts simplify system interconnections
• Transmit/Receive and chip disable simplify control
logic
• Compact 20-pin dual-in-line package
• Bus port glitch free power up/down

Logic and Connection Diagrams
Dual-In-Line Package
AD

""><>---e-f--() BO

ADo-+-....-f

I

I

AI~_

_ ---.r--<> BI

L_

A2o--r-

=
=

AJo-tAPORT

[

::~

A6o--(
A10--t... _

Al
A2

1

AJ

""t--..oB2

--l

A PORT

-j-oBJ

_~::

A4
B PORT

BPORT
AS

_=:J-o
.....r--o

B6

B7

A6

TRANSMIT/RECEIVE
(lIA)

A1

CHIP DISABLE

CHIP

DISA(~~~O'-"_ _ _ _ _ _ _ _'"

GND

10

11 TRAN/REC
TOP VIEW

Logic Table
Chip Disable
0
0
1

INPUTS
Transmit/Receive
0
1
X

RESULTING CONDITIONS
B Port
A Port
IN
OUT
OUT
IN
TRI-STATE

X = Don't care

9-9

TRI-STATE

m
~

o

~

CO

c..

~National

Memory Support Circuits

~ Semiconductor

c-..

m DP7304B/DP8304B 8-Bit TRI-STATi:®
~
o
Bidirectional Transceiver (Non-Inverting)
~

c"

c..
Features
• 8-bit bidirectional data flow reduces system package
count
• Bidirectional TRI-STATE inputs/outputs interface
with bus oriented systems
• PNP inputs reduce input loading
• Output high voltage interfaces with TTL, MOS,
and CMOS
' . 48 mA/300 pF bus drive capability

• Pinouts simplify system interconnections
• TransmitIReceive and chip disable simplify control
logic
• Compact 20-pin dual-in-line package
• Bus port glitch free power up/down

Logic and Connection Diagrams

Dual-In-Line Package
AO

AOo-4-+--!

APORT

!

">---......-+---OVCC
DIS 1

vee

IN 1

0lS2

OUT 2
IN J

OUT 4
OUTPUT

IN 5

OUT 6
INPUT
IN 1

OUT 8
GNO

'-----+---4 ><>----11-- OUT 1
~~----~-IN2

'----~---I

'><:>-----11--

OUTJ

~~----~-IN4

' - - - - - - t - - I ><>-----11--

OUT 5

~-+------+-- IN 6

'------t---1 ><>-----11--

DUll

I--------+-- IN B
TOP VIEW

GND
(ONE INVERTER SHOWN ONL Y)

Truth Table

Typical Application

Disable Input

r----...,
Input

Output

I

)I~D RES

DIS 1

DIS 2

H

H

X

Z

H

X

X

Z

...-t++-~

X

H

X

Z

'-+-~I+--.l

L

L

H

L

L

L

L
H

t::1a:1a:1:fl~ r~
~

H = high level
L = low level
X = don't care
Z = high impedance (off)

9·16

LINES

MM5290
6k DYNAMIC
RAM

~National

Memory 5upport Circuits

~ Semiconductor
051631/053631, 051632/053632, 051633/053633,
051634/053634 CM05 Oual Peripheral Orivers
General Description
high impedance OFF state with the same breakdown
levels as when Vee was applied.

The DS1631 series of dual peripheral drivers was
designed to be a universal set of interface components
for CMOS circuits.

Pin-outs are the same as the respective logic functions
found in the following popular series of circuits:
DS75451, DS75461, DS3611. This feature allows direct
conversion of present systems to the MM74C CMOS
family and DS1631 series circuits with great power
savings.

Each circuit has CMOS compatible inputs with thresholds
that track as a function of Vee (approximately 112 Veel.
The inputs are PNPs providing the high impedance
necessary for interfacing with CMOS.
Outputs have high voltage capability, minimum breakdown voltage is 56V at 250pA.

The DS1631
Vee = 5V.

The outputs are Darlington connected transistors. This
allows high current operation (300 mA max) at low
internal Vee current levels since base drive for the
output transistor is obtained from the load in proportion to the required loading conditions. This is essential
in order to minimize loading on the CMOS logic supply.

Features

Typical Vee = 5V power is 28 mW with both outputs
ON. Vee operating range is 4.5V to 15V.
The circuit also features output transistor protection if
the Vee supply is lost by forcing the output into the

Connection Diagrams
Vee

B2

Al

Bl

A2

X2

XI
TDPVIEW

GND

X2

Vee

82

Xl
TDPVIEW

GND

Al

Bl

GND

•

CMOS compatible inputs

•

TTLlDTL compatible inputs
PNP's

•

High impedance inputs

•

High output voltage breakdown

56V min

•

High output current capability

•

Same pin-outs and logic functions as DS75451,
DS75461 and DS3611 series circuits

300 mA max

•

Low Vee power dissipation (28 mW both outputs
"ON" at 5V)

(Dual-In-Line and Metal Can Packages)

A2

Vee

series is also TTLlDTL compatible at

Al

Vee

GND

Bl

A2

X2

Vee

B2

A2

X2

XI

GND

Al

Bl

Xl

GND

TDPV1EW

TOPVIEW

Vee

Vee

GND

TOP VIEW

TOPVIEW

GND
TDPVIEW

TOPVIEW

(P104 iselectmally connected tothe case.)

(PI04iserectricaltyconn~tedtothecase.l

(P104 iselectncally connected to the case.)

(PIO 4 IS electmally connected to the case.)

9-17

~

D

National
Semiconductor

Memory Support Circuits

OS16441053644, OS167410S3674
Quad TTL-MOS Clock Orivers

General Description
has a direct, low impedance output for use with or
without an external damping resistor.

The 051644/053644 and 051674/053674 are quad
bipolar·to·M05 clock drivers with TTL/OTL compatible
inputs. They are designed to provide high output current
and voltage capabilities necessary for optimum driving
of high capacitance N·channel M05 memory systems.

Features

The device features two common enable inputs, a
refresh input, and a clock control input for simplified
system designs. The circuit was designed for driving
highly capacitive ,loads at high speeds and uses 5chottky·
clamped transistors. PNP transistors are used on all
inputs thereby minimizing input loading.

• TTL/OTL compatible inputs
• 12V clock or 5V clock driver
• Operates from standard bipolar and M05 supplies

• PNP inputs minimize loading
• High voltage/current outputs
• Input and output clamping diodes
• Control logic optimized for use with M05 memory
systems
• Pin and function compatible with MC3460 and
3235
• Built·in damping resistors (051644/053644)

The circuit may be connected to provide a 12V clock
output amplitude as required by 4k RAMs or a 5V clock
output amplitude as required by 16k RAMs.
The 051644/053644 contains a 10[2 resistor in series
with each output to dampen the transients caused by
the fast·switching output, while the 051674/053674

Schematic and Connection Diagrams
VCC3
EQUIVALENT INPUT

EQUIVALENT QUTPUT

I
INPUT

' - - - - . -....J\I\i'\r-O

I

INTERNAL
LQGIC
CIRCUITRY

I

I
I
I

I

L ___ _
'---.------------~~------....- - - - - - - - - - _ . - - - - _ o G N O

* D51644/D53644 only
Dual·1 n·Line Package
VCCI

OUT 0

SEL 0

EN I

EN 2

SEL C

OUT C

VCC3

VCC2

OUT A

SEL A

CLK
IN

RFSH
IN

SEL BOUT B

GNO

TOP VIEW

9·18

OUTPUT

~National

a

Memory Support Circuits

Semiconductor

081645/083645,081675/083675
Hex TRI·STATE® TTL·MOS Latches/Orivers
General Description
The circuit employs a fall-through·latch which captures
the data in parallel with the output, thereby eliminating
the delay normally encountered in other latch circuits.
The OS1645/0S3645 and OS1675/DS3675 may be
used for input address lines or input/output data lines
of a MOS memory systern.

The OS1645/0S3645 and OS1675/0S3675 are hex
MOS latches/drivers with outputs designed to drive large
capacitive loads up to 500 pF associated with MOS
memory systems. PNP input transistors are used to
reduce input currents, allowing the large fan-out to
these drivers needed in memory systems. The circuit
has Schottky-clamped transistor logic for minimum
propagation delay, and TR I·ST ATE® outputs which
allow bus operation.

Features
• TTL/OTL compatible inputs
• PNP inputs minimize loading
• Capacitance-driving outputs
• TRI-STATE outputs
• Built-in damping resistor (OS1645/DS3645)

The OS1645/0S3645 has a 15 n resistor in series
with the outputs to dampen transilmts caused by the
fast switching output circuit. The OS1675/0S3675
has a direct, low impedance output for use with or
without an external resistor.

Logic and Connection Diagrams
DATA A O-~~----------f--"""l

Dual·ln-Line Package
Vee

DDs~~

DATA F

IN
ENBl

DATA A

OA

OF

DATA E

DE

DATA 0

aD

DATA e

fie

GND

DATA9o-C=======
DATAe

o-C

======= === ::::J-o
====::::J-o
=

= === ====

DATADo-C=======
DATAE

o-C

DATAF

o-C =

=

=

::J-o DE

=

== =

fie
liD

====::::J----<>fi F

== =

DATA 9 OB
TOPVIEW

~~!:~~ O------L~O-------------I

Truth Table
INPUT
ENABLE

OUTPUT
DISABLE

1
1

OPERATION

DATA

OUTPUT

0

1

0

Data Feed-Through

0

0

1

Data Feed-Through

0

0

X

Q

Latched to Data Present
when Enable Went Low

X

1

X

Hi-Z

High Impedance Output

X = Don·t care

Hi-Z = TRI-STATE mode

9-19

t--

t-,....
~National

Memory 8upport Circuits

~ Semiconductor
c 081647/083647,081677/083677,
;;:: 0816147/0836147, 0816177/0836177
t-,....
CD
,.... Quad TRI·8TATE® M08 Memory 1/0 Registers
CD

('I)

en
en
c

General Description

051647/053647 and 051677/053677 they are TRI5TATE_ The "8" port outputs are also designed for use
in bus organized data transmission systems and can sink
80 mA and source -5.2 mAo The "A" port outputs in
all four types are TRI-5TATE.

The 051647/053647 series are 4-bit I/O buffer registers
intended for use in M05 memory systems. The circuits
employ a fall-through latch for data storage. This method
of latching captures the data in parallel with the output,
thus eliminating the delays encountered in other designs.
The circuits use 5chottky-clamped transistor logic for
minimum propagation delay and employ PNP input
transistors-so that input currents are low, allowing large
fan-out' to' these circuits needed in a memory system.

Oata going from port" A" to port "8" is inverted in the
051647/053647 and 0516147/0536147 and is not
inverted in the 051677 /053677 and 0516177/0536177.
Oata going from port "8" to port "Au is inverted in
all four types.

Two pins per bit are provided, and data transfer is bidirectional so that the register can handle both input and
output data. The direction of data flow is controlled
through the input enables. The latch control, when
taken low, will cause the register to hold the data present
at that time and display it at the outputs. Oata can be
latched into the register independent of the output
disables or EXPAN510N input. Either or both of the
outputs may be taken to the high-impedance state with
the output disables. The EXPAN510N pin disables both
outputs to facilitate multiplexing with other I/O registers on the same data lines.

Features
• PNP inputs minimize loading
•

Fall-through latch design

•

Propagation delay of only 15 ns

• TRI-5TATE outputs
•

EXPAN510N control

•

8i-directional data flow

• TTL!OTL compatible

The '!8"port outputs in the 0516147/0536147 and
0516177/0536177 are open collectors, and in the

• Transmission line driver output

Logic and Connection Diagrams

r---------------------,
I
I
I

I

Dual-In-Line Package
Bl

I

Bl

B
MULTIPLEX

I

Al

I

I

INPUT
ENABLE

AI

L ____ _

_ _ _ _ _ .J

A2o-[== ===
AJo-[=====
A4o-[=====
r-----

=====}-oB2
=== ==}-oBJ
=====}-oB4
-----,

I

I
I

I
I
I

_

L ____ _

I
I
_ _ .J

A__________.._ B
INPUT
ENABLES

OUTPUT
DISABLES

EXPANSION

*Inverting 051647/053647 and OS16147/0536147 only

9-20

A
{

B

A2
B2

AJ

GND

B3

TOP VIEW

~National

Memory Support Circuits

en

D Semiconductor

~
c
en
CN

081648/083648,081678/083678
TRI-8TATE® M08 Multiplexers/Orivers

en

General Description
The OS1648/0S3648 and OS1678/0S3678 are quad
2-input multiplexers with TRI-STATE outputs designed
to drive the large capacitive loads (up to 500 pF)
associated with MOS memory systems_ A PNP input
structure is employed to minimize input currents so that
driver loading in large memory systems is reduced_ The
circuit employs Schottky-clamped transistors for high
speed and TR I-STATE outputs for bus operation_

low impedance output for use with or without an
external resistor_

The OS1648/0S3648 has a 15 n resistor in series with
the outputs to dampen transients caused by the fastswitching output_ The OS1678/0S3678 has a direct,

Features
•

TRI-STATE outputs interface directly with system
bus

•

Schottky-clamped for better ac performance

•

PNP inputs to minimize input loading

•
•
•

OTL and TTL compatible
High-speed capacitive load drivers
Built-in damping resistor (OS1648/0S3648 only)

1151

Al~121~------------_;~
Dual-I n-Line Package

Bl~IJI------r-------~~

Yl

VCC
'A2

151

B2

161

AJ

1111

OUTPUT
CONTROL

INPUTS
__________
A4
B4

OUTPUT
Y4

INPUTS
__________
AJ
BJ

OUTPUT
YJ

Y2

YJ

1101

8J~~----+-----~_;~

1141

A4~~----+-----~_;~

84 ~I1J-,-1-----+------Hr-"\

Y4

SELECT
SELECT

Al
Bl
~
INPUTS

Yl
OUTPUT

A2
B2
~
INPUTS

TOP VIEW

Schematic Diagram
EQUIVALENT OUTPUT

EOUIVALENT INPUT

r----------------.---------------.----~~----oVCC

OUTPUT
INPUT

INTERNAL
LOGIC
CIRCUITRY

--_.----------------~--------------~----_.----_oGND

"D516481053648 only

9-21

Y2
OUTPUT

&
c

en
......
en
"""-I

e

Logic and Connection Diagrams
OUTPUT
CONTROL

c
en
......

GNO

C

en
CN
en
"""-I
CO

~National

Memory 8upport Circuits

~ Semiconductor
081649/083649,081679/083679
Hex TRI·8TATE® TTL·M08 Drivers
General Description
The OS1649/0S3649 and OS1679/0S3679 are Hex
TR I-STATE MOS drivers with outputs designed to drive
large capacitive loads up to 500 pF associated with MOS
memory systems. PNP input transistors are.employed to
reduce input currents allowing the large fan-out to these
drivers needed in memory systems. The circuit has
Schottky-clamped tran·sistor logic for minimum propagation delay, and TR I-STATE outputs for bus operation.

ing output. The OS1679/0S3679 has a direct low impedance output for use with or without an external resistor.

Features
•

High speed capabilities,
• Typ 9 ns driving 50 pF
• Typ 30 ns driving 500 pF
• TRI-STATE outputs for data bussing
• Built-in 15 n damping resistor (OS1649/0S3649)
• Same pin-out as OM8096 and OM74366

The OS 1649/0S3649 has a 15 n resistor in series with the
outputs to dampen transients caused by the fast-switch-

Schematic Diagram

Truth Table

EQUIVALENT INPUT

VCC

EQUIVALENT OUTPUT

DISABLE INPUT

IS' OUTPUT

INPUT

OUTPUT

DIS 1

DIS 2

0

0

0

1

0

0

1

0

0

1

X

Hi-Z

1
1

0

X

Hi-Z

1

X

Hi-Z

x = Don't care
Hi-Z

L

= TRI-STATE

mode

GNO

*OS1649/0S3649 only

Connection Diagram

Typical Application

..-----...,r-----,
Dual-In-line

vcc

OIS2

IN6

OUT6

INS

OUTS

t-------t
t-------,

6·BITRAM
ADDRESS

Pack~ge
IN4

ADDRESS
LINES

OUT4
MMS270
OR
MMS280
MDS RAM
ARRAY

H H - " - - - I REFRESH &
HH-+-+-----, ~I~~~ESS

6·BITRAM
ADDRESS

L ___ _

OISI

INI

OUTI

IN2

OUT2

IN3

OUT3

OS3646
OR
DS3676

GND

TOP VIEW

ClOCK

MDS
COUNTER
DRIVER

ENABLE
ADDRESS OR
COUNT SElECT

9-22

"0" ADDRESS
"I" COUNTER

~National

Memory Support Circuits

~ Semiconductor
053643, 053673 Decoded Quad MOS Clock Drivers
General Description
The OS3643 and OS3673 are quad bipolar-to-MOS
decoder/clock drivers with TTL/OTL compatible inputs.
They are designed to provide high output current and
voltage capabilities necessary for optimum driving of
high capacitance N-channel MOS memory systems.

switching output. while the OS3673 has a direct, low
impedance output, for use with or without an external
resistor.

The device features full decoding of input address lines
from two inputs to one of four outputs. Also featured is
the capability of expanding to three inputs to one of
eight outputs with the use of the Expansion and
Expansion inputs. Also included are clock and refresh
inputs.

Features

The circuit was designed for driving large capacitive
loads at high speeds and uses Schottky-clamped transistors. PNP transistors are used on all inputs, thereby
minimizing input loading.
The OS3643 has a 10 S1 damping resistor in series with
each output to dampen transients caused by the fast

•
•

TTL/OTL compatible inputs
Operates from standard bipolar and MOS supplies

•

PNP inputs minimize input loading

•

Full logic decoding for either two inputs to one of
four outputs or three inputs to one of eight outputs

•

High voltage/cu rrent outputs

•

Input and output clamping diodes

•

Control logic optimized for use with MOS memory
systems

•

Built-in damping resistors (OS3643)

Logic and Connection Diagrams
Al

Dual-I n-Line Package
VCCI

OUT 4

ClK

VCC2

OUT 1

Al

RFSH

EXPN

OUT l

VCCl

A2

ITi'N

OUT 2

GNO

TOP VIEW

Truth Table
OUTPUTS

INPUTS
CLOCK

REFRESH

EXPANSION

EXPANSION

A2

A,

OUT 1

OUT 2

OUT 3

1

X

X

X

X

X

a

a

a

a
a
a
a
a
a
a
a

1

X

,

X

X

X

a
a
a
a
a
a
a

a
a

a

,

1

a

1

a
a
a
a

1

1

1

1

X

X

a
a

1

X

X

a

X

X

1
1

x = don't care state
9-23

1

1

a
a
a
a
a
a

OUT4

a

1

1

1

a

0

1

a
a

a
a
a
a
a

1

a
a

a
a
a
a

a
a
a

1

en

r--.
,..

CD

CW)

en

~National

Memory 5upport Circuits

~ Semiconductor

c 0516149/0536149,0516179/0536179
a;
r--. Hex M05 Orivers
,..

CD
,..
en
c

~
,..
CD
en
c
CW)

a;

,..
CD
,..
en
c
~

General Description
switching output. The OS1679/0S3679 has a direct low
impedance output for use with or without an external
resistor.

The OS16149/0S36149 and OS16179/0S36179 are
Hex MaS drivers with outputs designed to drive large
capacitive loads up to 500 pF associated with MaS
memory systems. PNP input transistors are employed to
reduce input currents allowing the large fan-out to these
drivers needed in memory systems. The circuit has
Schottky-clamped transistor logic for minimum propagation delay, and a disable control that places the outputs
in the logic "1" state (see truth table). This is especially
useful in MaS RAM applications where a set of address
lines has to be in the logic "1" state during refresh.

Features
•

High speed capab,ilities
• Typ 9 ns driving 50 pF
• Typ 29 ns driving 500 pF

• TR I-STATE outputs for data bussing
• Built-in 15 n damping resistor (OS16149/0S36149)
• Same pin-out as OM8096 and OM74366

The OS1649/0S3649 has a 15 n resistor in series with
the outputs to dampen transients caused by the fast-

Schematic Diagram

....

EaUIVALENT OUTPUT

EQUIVALENT INPUT

r-------------~~--.---

--_oVee

15*

JVl.rv--o OUTPUT

L - - -....
INPUT

L _

__ _

~-+--------~------~~--~---oGND

*OS16149/0S36149 only.

Truth Table

Connection Diagram
Dual-In-Line Package
Vee

DIS 2

IN 6

OUT6

IN 5

OUTS

IN 4

OUT4

DISABLE INPUT

IN lOUT I

I,N 2

OUT 2

IN J

OUT J

GND

TOPVIEW

9-24

OUTPUT

DIS 2

0

0

0

1

0

0

1

0

0

1

X

1

1

0

X

1

1

1

X

1

x = Don't care
DIS I

INPUT

DIS 1

~National

Memory Support Circuits

~ Semiconductor

DS75322 Dual TTL-MOS Driver
OS3622 Dual Fail-Safe TTL-MOS Driver
General Description
The OS75322 is a dual TTL-MOS high speed driver.
The input structure of the device is TTL and OTL
compatible. A common strobe input is provided for
gating the outputs to the low state. The outputs provide
high current and high voltage levels ideal for driving
MOS circuits. The OS75322 specifically meets the
requirements for driving N-channel RAMs where low
power dissipation is desirable when the driver is in the
low state.

The OS75322 and the 053622 are ideal for driving
the UP04110, MM52BO and the MM5270 4k RAMs.

Features
• Oual positive-logic and TTL-MOS driver
• TTL and OTL compatible inputs
• High voltage/current outputs
• Operates from standard bipolar and MOS supplies
• High speed switching
• Input and output clamping diodes
• Separate driver address inputs with common strobe

The OS3622 provides output fail-safe protection.
Powering down VCCl activates the fail-safe circuit,
forcing the outputs to the low state. The fail-safe feature
eliminates output glitches that may occur in systems
that power down VCC1. Functionally, the OS3622 and
the OS75322 are identical.

•
The OS75322, OS3622 require 2 external PNP transistors
per package.

VOH and VOL compatible with 4k RAMs and other
popular MOS RAMs

•

No current (leakage only) when outputs are in low
state (OS75322)

The OS75322, OS3622 are characterized for operation
from DoC to +70°C.

•

Outputs forced to low state with loss of VCCl
(OS3622)

Connection Diagram
. Dual-In-Line Package

VI
12

Positive Logic Y = AE
Recommended PNP Transistors
2N5910,2N5771

VCC2
11

V2
10

A2

Al

TOP VIEW

9-25

NC

GNo

~National

Memory Support Circuits

D Semiconductor

058T26A, DSST26AM, 058T28, DSST28M
4-Bit Bidirectional Bus Transceivers
General Description

Features

The DSBT26A, DSBT2B consists of 4 pairs of TR 1STATE® logic elements configured as quad bus drivers/
receivers along with separate buffered receiver enable
and driver enable lines. This single IC quad transceiver
design distinguishes the DSBT26A, DSBT2B from
conventional multi-IC implementations. In addition,
the DSBT26A, DSBT2B's ultra high speed while driving
heavy bus capacitance (300 pF) makes these devices
particularly suitable for memory systems and bidirectional data buses.

•
•
•
•
•
•
•
•

Inverting outputs in the DSBT26A
Non-inverting outputs in the DSBT2B
TRI-STATE outputs
Low current PNP inputs
Fast switching times (20 ns)
Advanced Schottky processing
Driver glitch free power up/down
Non-overlapping TRI-STATE

Both the driver and receiver gates have TRI-STATE
outputs and low current PNP inputs. PNP inputs reduce
input loading to 200 pA maximum.

Logic and Connection Diagrams
. RIE

RIE

ROUT

DOUT

DIN

0-----"'"

DIN

0-----"'"
DDUT

RDUT

RDUT

DOUT

.....- - - - Q O I N

Dual·ln·Line Package
16 Vee

RIE

15
RDUT

DIE

14
ROUT

DDUT
IN
RDUT

IN

DDUT

ROUT
10

IN

DDUT

GND

IN

TDPVIEW

9-26

Memory Support Circuits

~National

~ Semiconductor

ADVANCE INFORMATION

MM54C240/MM74C240 Inverting Outputs
MM54C2441MM74C244 Non-Inverting Outputs
Octal Buffers and Line Drivers with TRI-STATE® Outputs
General Description

Features

These octal buffers and line drivers are monolithic complementary MOS (CMOS) integrated circuits with TR 1ST ATE® outputs_ These outputs have been specially
designed to drive highly capacitive loads such as busoriented systems. These devices have a fan-out of 6 low
power Schottky loads. A high logic level on th~ output
disable control input G makes the outputs go into the
high impedance state.

• Wide supply voltage range - 3 V to 15 V
•

High noise immunity - 0.45 VCC typ

•

Low power consumption

•

High capacitive load

• TRI-STATE® outputs
•

Input protection

• TTL compatibility
•

Connection Diagrams
Vee

20-pin dual-in-line package

(TOPVIEWI

2G

lYl

2A4

lY2

2A3

lY3

2A2

lY4

2Al

10

lG

lAl

2Y4

lA2

2Y3

lA3

2Y2

lA4

2Y4

GNO

lY3

2A2

lY4

2Al

MM74C240

_ (TOPVIEWI

Vee

2G

lYl

2A4

lY2

2A3

10

fG'

lAl

2Y4

lA2

2Y3

lA3

MM74C244

9-27

2Y2

lA4

2Y4

GNO

Memory Support Circuits

~National

~ Semiconductor

MM54C373/MM74C373 TRI-STATE® Octal D-Type Latch
MM54C3741MM74C374 TRI-STATE® Octal D-Type Flip-Flop
General Description
The MM54C373/MM74C373, MM54C374/MM74C374
are integrated, complementary MaS (CMOS), 8-bit
storage elements with TR I-ST ATE® outputs. These
outputs have been specially designed to drive highly
capacitive loads, such as one might find when driving
a bus, and to have a fan-out of 1 when driving standard
TTL. When a high logic level is applied to the OUTPUT
DISABLE input, all outputs go to a high impedance
state, regardless of what signals are present at the other
inputs and the state of the storage elements.

the set-up and hold time requirements, is transferred to
the Q outputs on positive-going transitions of the
CLOCK input.
Both the MM54C373/MM74C373 and the MM54C374/
MM74C374 are being assembled in 20-pin dual-in-line
packages with 0.300" pin centers.

Features

The MM54C373/MM74C373 is an 8·bit latch. When
LATCH ENABLE is high the Q outputs will follow the
D inputs. When LATCH ENABLE goes low, data at the
D inputs, which meets the set-up and hold time requirements, will be retained at the outputs until LATCH
ENABLE returns high again.

The MM54C374/MM74C374 is an 8-bit, D·type, positiveedge triggered flip-flop. Data at the D inputs, meeting

•

Wide supply voltage range

•

High noise immunity

3.0V to 15V
0.45 VCC typ

•

Low power consumption

•

TTL compatibility

fan·out of 1 driving
standard TTL

•

Bus driving capability

•
•

TRI-STATE outputs
Eight storage elements in one package

•

Single CLOCK/LATCH
DISABLE control inputs

•

20-pin dual-in-line package with 0.300" centers takes
half the board space of a 24-pin package

ENABLE

and

OUTPUT

Connection Diagrams
MM54C374/MM74C374
Dual-I n- Line Package

MM54C373/MM74C373
Dual-In-Line Package

OUTPUT
DISABLE

OUTPUT
DISABLE

VCC

01

01

DB

01-+--H
02--+---+-4

VCC

I-I---+-~ 07

DB

01-+--H

H---+;;""OB

02--+---H

1-1"";""--+"-- 01

02

07

02

07

03

06

03

06

03-+--+-4

1-1---+-;;""06

OJ--+---H

H---+"'-- 06

04""';+---+-4

1-1---+-;"-'05

04-T--H

I-f---+=-- 05

04

04

05

05

GNO

GNO

TOP VIEW

CLOCK

TOPVIEW

9-28

Section 10

Physical Dimensions'

"tJ

~National

Physical Dimensions

~ Semiconductor

::r
'<
(f)

--

(')

-cm

-3

CD

:l
(f)

o--

:l

(f)

PACKAGES

Dual-In-Line Packages
(N) Devices ordered with "N" suffix are supplied in molded dual-in-line package. Molding material is EPOXY 82, a highly
reliable compound suitable for military as well as commercial temperature range applications. Lead material is Alloy 42
with a hot solder dipped surface to allow for ease of solderability.
(J)

Devices ordered with the "J" suffix are supplied in a ceramic dual-in-line package. The body and lid of the package are
made of ceramic. Hermeticity is accomplished through a high temperature sealing glass. Lead material is tin-plated
kovar.

(0) Devices ordered with the "0" suffix are supplied in glass/metal dual-in-line package. The top and bottom of the package
are gold-plated kovar. The side walls are glass, through which the leads extend forming a hermetic seal. The kovar leads
may be either gold or tin~plated.

(0) Devices ordered with the "Q" suffix are supplied in a glass/metal dual-in-line package with a round quartz window.

Note: All dimensions expressed as

inches
(millimeters)

0.050

u~
(~:~:: :~:~~:) -j

f--

(::~!~=:::!!) --I f-

0.165
(4.191)
MAX

0.125
(3.175)

MIN

NS Package D22B
22-Lead Cavity DIP (D)

10-1

0.020-0.060
(0.508-1.524)

o
c
.2
o

1-------(3~~28081------l1

c

MAX

Q)

1

E
.-

0.598
(15.1891

c

-as
.~

~

.c
D..

~~::r-r:-:r-r.::rj

ND.lIDENT

o

~
~

I

II

l

IIi3.208II
0520

0.050
11.2701
TVP

0.165

i4llii

~b'::::::'

m"",
0.008-0.015
(0203-0.3811

0.125

1---(~~6~:1----l

I I
I-

"

Dl00,0010
(2540'02541-1

REF

·0D15-0D23
-11-(0:381-0:5841

(3.1751
MIN

NS Package D24C
24-Lead Hermetic DIP (D)

0.025
(0.6351
RAD

(7.391)
MAX

L,."-...,,......,.-::-r-r:'T""T':'1-r:T"~:r-'~

1 ""'4""

U . ., "
0.160

''.
0.200

GLASS

~~~:~ J~~~~~~~~~. ~~:

~ (9.719,0.6351
~

(~~::I
MAX

I-

--11-

L0018'O'002
(0457,00511.

0.125
(3.1751

0.100,0.010
(2.540 ,0.2541

MIN

NS Package J16A
16-Lead Cavity DIP (J)

b
1

0.025
(0.635)
RAD

11

16

15

~~0.310
(23241)
(7.8741
MAX
14

13

12

11

r

MAX

o ,GLASS

0.290
(7.3661
MAX

L.--.~...............,..,..,....,...,.......,..,.,....,..,......,.."..~
0.290-0.320
(7.386-8.128)

GLASS
SEALANT

0.020-0.070
(0.508-1.1781

\{;;;;~~~;;;~;6~~~1

'h

~t

86'94'
TVP
0.018'0.003
(0.457,0.0761

-l

NS Package J18A
18-Lead Cavity DIP (J)

t

~ MAX

~

(3.1751
MIN

0.025
(0.6351
RAD

c
--

3

~

CD

(5.9691

)~0.020_O.010

:=it "...
~ ~

~~

0.I00io.olo

0.011io.002

(2.54oio.2541

(0.432'0.0511

~.""

(3.1151

MIN
.

NS Package J20B
20-lead Cavity DIP (J)

------11

0.420 MAX

:-L!!J....I.!.!J~:J....1!!U.!!.L..J.!.:J...J.!!JL....,L!;:.L....L::uI.!.!.L.J.!.!.L---I-f(10.6611 GLASS
0.025
. (0.6351
RAD

0.400
(10.161

L-~~~~~~~~~~~~~~~
0.200
(5.0801

~':~~::~:'
II (~::~:I
r-1f- MIN

0.018,0.003
(0.451,0.0761

NS Package J22A
22-lead Cavity DIP (J)

0.600
(15.2401
fMAX
:-1!!.LJ.!!J~J...J..:;!.L.J.!!!.L...L!!J...J.!!JL....1.:;~::U.:.:J...J..:.:.L...L:.:.L......t1 GLASS

I

0.025
(0.6351
RAD

0.515-0.525

L-~~~~~~~~~TT~~~~~(13.011rI3.3351
I-

0.590-0.620

95'i5'

"

~-(
+0.635)---1
15.875 -G.311
6.250 -G.015

0.200

---I

fll',
...

..,J

0.001-0.012

"~,,

0.060-0.100

(1.524-2.5401

f--

0.100'0.010
(2.540,0.2541

I
~ I-

NS Package J24A
24-lead Cavity DIP (J)

10-3

_11_

0.018,0.002
--11--(0.451 '0.0511

::J
t/)

0.125

TYP

(~~I.~:1 MAX

::J

t/)

-o

86' 0.125
94' (3.1151

TYP

MIN

U)

C

o
.U)
C

CI)

E
.-

0.025
10.6351

c

RAD

-

'"

.9
U)
~

.c
Q.

f---

1,m
0.200
(5.0801

0.160
0.590-0.620 §f14.0641

(Ii~m ~u"'H'.' J

i

0.008-0.012

"

0. 685 -l1.060
f---(11399 +0.635)---1·
. -1.524

0.060-0.100
11.524-2.5401

,m

10.508-1.71BI

•

f--

I I -4h:::~~ ::::~:I
f--

0.100'0.010
(2.540 ,0.2541-1

0.125
13.1751
MIN

NS Package J24CQ
24-Lead UV Window Cavity DIP (J)

1.490
t - - - - - - - - - - 1 3 1 . 8 4 6 1 MAX

I

------~il0~~~~1
MAX GLASS

0.025
10.6351

0.515-0.525

RAD

~~~~~~~~~~TT~~~~~~~

0.048-0.055

0.200

h

0.060-0.100
11.524-2.5401

-j

h

0.100'0.010
12.540,0.2541

~h
0.018'0.002
10.451 '0.5081

NS Package J28A
28-Lead Hermetic DIP (J)

16.350'0.1211

~:::;:::;:=;r:;:r:r.:;:::::;::::;:::::;:::;=;:::;:=;:;;:;:=1~
0.300-0.320

~

"""["'"

0.030
10.1621
MAX

0.040

f-J
0.100
(2.5401
TVP

NS Package N16A
16-Lead Molded DIP (N)

10-4

(5:
0.130'0.005

0.092
(2.ll7)
olA NOM
PIN NO. IIOENT

c-3

O.OlO
(0.762)
MAX.

0.lOO-0.l20

~

(:::~:=::~~~).

1

0.025,0.015
0.l25 +0.025
-0.015

(0.6n,0.l81)

(8255:~:~m

CD
::l

en

cr::l

en

~J

0.100
(2.540)
TYP

NS Package N1BA
1B-Lead Molded DIP (N)

0.092
(2.ll7)
olA NOM

-r

D.250±0.005

PIN No.lloENT

FDJ1BlITffR~rr.~~~~~d::JL·127)
0.ll0±0.005

~=r----------++-------- ~
~(::~:~)
MAX

-l

I-

0.075 '0.005
(1.905'0.127)

-+0.
I 0 2'0
II ~ (OM~~)
(0.457 ,0.076) -11- (~1~5)
0.018 ±O.OOl

NS Package N20A
20-Lead Molded DIP (N)

0.062
RAo (1.575)
PIN NO.1
loENT

~0.ll0±0.005

~____________________~~ (l.l02,O.127)

-r
--..1--.l.

_0.020
(0.508)

JtMIN

r-l

0.100±0.010
(2.540,0.254)

NS Package N22A
22-Lead Molded DIP (N)

10-5

r-lt-...

~

O.OUtO.OOl

(l.175)

(0.457±0.076)

MIN

o
c:
o
-U)
c:

1.270

1--------(32.2581-----~-I1
MAX

1

0.062
(1.5751
RAD

(1)

E
--

0.540.0.005

c

-CO

br:=;=;r.;=ffi"i'fi""'r.'Fi':'FF.rffi"'F.'r=r.;;;=;;TffiF]"""

U
-U)

0.030

~

~

0040

0.160,0005

"~jm;

.c:

c..

0009-0 015
(0.229-0.3811 ,
0075,0015
(1905,03811

.----t

~

I--

-I

0100
1--(25401
TYP

0018,0003
--H---(0457 ,00761

+

0015
0125 iD3aiI
-(3
51 MIN
.11
MIN

NS Package N24A
24-Lead Molded DIP (N)

I

1 - - - - - - - - ( 3 21.270
.2581-------1

MAX

I

0.063
(1.6001
RAD

0.540 '0.005

Ir"u"-"''''=:+r. "~
~:=""'
0.600-0.620

(1.9051

'(1:0161

0.160.0.005

~,::::,
t

f IIt
'
0'009-0'015~
I--

+0.025
0.625 -0 015
.
(15.875

~:~m~

--1

--(0.229-0.3811

---j

I

0.075 to.015
(1.905'0.3811

I--

f--

0.100
(2.5401
TYP

---j I--

0.018.0.003
(0.457 '0.0761

MIN

0.125
(3.1751
MIN

NS Package N24B
24-Lead Molded DIP (N)

0.030
(0.7621 ~

".~"~" ---I ."

0.050

."

"M" ~-=

lr=~IDt~ ~""';

r

0.625 +0.025

I---~----J
(15.875 ~:~m

0.009_0.015J
(0.229-0.3811
0.075'0.015
(1.905.0.3811

I

t-

I
--j

I

r--

0.100
(2.5401
TYP

NS Package N28A
28-Lead Molded DIP (N)

10·6

II
--i

r--

----+t
0.018.0.003
(0.457.0.0761

+

0.020
0.125(0.5 08 1
(3.1751 MIN
MIN



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