1980_Optoelectronics_Designers_Catalog 1980 Optoelectronics Designers Catalog

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\ I.

Optoelectronics
Designer's
Catalog
1980

Flin-

HEWLETT

~~ PACKARD

.

~..

I

1980 AUG 03

Optoelectronics
Designer's
Catalog
1980

Intensive solid state research, the
development of advanced manufacturing techniques and continued expansion has enabled HewlettPackard to become a high volume supplier of
quality, competitively priced LED displays,
LED lamps, optocouplers, fiber optics, and
emitters/detectors.
In addition to our broad product line,
Hewlett-Packard also offers the following

services: immediate delivery from
any of our authorized stocking distributors, applications support,
special QA testing, and a one year guarantee
on all of our optoelectronic products.

.This package of products and services has
enabled Hewlett-Packard to become a
recognized leader in the optoelectronic
industry.

A Brief
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. systems: Features',·••" .

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Advantagest",sendits,'· .• t~:·.~:T~i,~~<:'i.\:'• ' '2 "
,: '. ..Emitters and Detectors{,' "'"Y:~';'':<::'''''' ,' .. "
. .... Features. Advan~~i~!;A~~;i~;3.. .... .....
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• Emitters and Detectors,.

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Emitter/Detector Systems
• Features

• Advantages

• Benefits

HEDS-1000 HIGH RESOLUTION OPTICAL REFLECTIVE SENSOR
Focused optics

Gives higher resolution

Less error
No precision alignment of
discrete components

Visible light source

Can detect most colors

Not limited to black & white
patterns and objects

Photo IC detector

A. Faster response time

A. Can detect more transitions
in less time
B. Simplified interface
electronics

B. Speed, linearity, and
gain options available
Standard TO-5 package

Mounting hardware
readily available

Easy to mount and use

Sealed package

Moisture resistant

Reliable operation in indoor/
outdoor environments

Detector IC operates from
single ended 3.5V to 20V
power supply

Compatible with all IC
technologies

Easy to use

Fully integrated, assembled
and tested

No precision alignment
required

Easy to use
Faster design-in

Performance fully specified
and guaranteed

System design simplified

Assured performance

HEDS-3000 DIGITAL BAR CODE WAND
Digital output

No analog signal
conditioning circuitry
needed

Microprocessor compatible

Low digitizing error

High percentage
Good reads

Increased throughput

Push-to-read switch

Conserves power
No strobing circuitry
required

Longer battery life
in portable systems

Guaranteed performance

System design simplified

Easy to use

Single supply operation

Compatible with standard
digital systems

Easy to use

Lightweight stylized
plastic case

Minimizes operator fatigue

Increased throughput

Custom options
available

Styling to match
customer's products

OEM product image
enhanced

2

Emitters

[~
• Features

• Advantages

• Benefits

Near IR emission

Visible

Facilitates alignment

Functions with most
silicon phototransistors
and photodiodes

Easy to use

Cost effective implementation

Plastic Package

Low cost

Cost effective implementation

HEMT 3300 uses isotropic
LED chip

Provides floodlight type
beam

Well suited for applications
that require a large area to
be irradiated

HEMT 6000 uses surface
emitter LED chip

Provides bright spot
of light

Facilitates focusing light on
active area of photodetector

HEMT 6000 has offset
wirebond

Active area of the chip
is not masked or
shadowed

Facilitates use with fiber
optics

Detectors
(PIN Photodiodes)

.~/

• Features

• Advantages

• Benefits

Offset wirebond

Can be used with fiber
optiCS

Fiber can be placed directly
over active area

All HP PIN photodiodes
have anti~reflective coating

Converts more incident
radiation (light) into
photocurrent

High Responsivity

Wide spectral response
(ultraviolet through IR)

A single device can cover
the light spectrum plus
UV and IR

Works with a variety of
sources

Low junction capacitance

Wide bandwidth

Can detect high speed pulses

ULTRA Linear

Permits operation over
10 decades

Eliminates the need for
equalization

3

- : ,,-:,

HIGH 'RESOLUTION
,OPTICAL', REFLECTIVE
, '." . "'SENSOR

HEWLETT

PACKARD

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TECHNICAL DATA MARCH 1980

Features
• FOCUSED EMITTER AND DETECTOR
IN A SINGLE PACKAGE
• HIGH RESOLUTION - .190mm SPOT SIZE
• 700nm VISIBLE EMITTER
• LENS FILTERED TO REJECT AMBIENT LIGHT
• TO-S MINIATURE SEALED PACKAGE
• PHOTODIODE AND TRANSISTOR OUTPUT
• SOLID STATE RELIABILITY

Description
The HEDS-1000 is a fully integrated module designed for
optical reflective sensing. The module contains a .178mm
(.007 in.) diameter 700nm visible LED emitter and a
matched I.e. photodetector. A bifurcated aspheric lens is
used to image the active areas of the emitter and the
detector to a single spot 4.27mm (0.168 in.) in front of the
package. The reflected signal can be sensed directly from
the photodiode or through an internal transistor that can
be configured as a high gain amplifier.

Mechanical Considerations
The HEDS-1000 is packaged in a high profile 8 pin TO-S
metal can with a glass window. The emitter and
photodetector chips are mounted on the header at the
base of the package. Positioned above these active
elements is a bifurcated aspheric acrylic lens thatfocuses
them to the' same point.

Applications

The sensor can be rigidly secured by commercially
available two piece TO-5 style heat sinks, such as
Thermalloy 2205, or Aavid Engineering 3215. These
fixtures provide a stable reference platform and their
tapped mounting holes allow for ease of affixing this
assembly to the circuit board.

Applications include pattern recognition and verification,
object sizing, optical limit switching, tachometry, textile
thread counting and defect detection, dimensional
monitoring, line locating, mark, and bar code scanning,
and paper edge detection.

\

PaCkage Dimensions

&

!

MAXlMUIIISlGNAL POINT~

t~-l.~

PLANErl--~j 1D.162l
4.11

REFERENCE

m
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NOTES!
1. ALL DIMENSIONS IN MILLlMI>TERS AND (INCHES),
2. ALL UNTOlERANCeD DIMeNSIONS AftE fOR REFERENCE DNLY,
3. THE REFERENCE PLANE IS THE TOP SURFACe Of THE PACKAGE.
4. NICKEL CAN AND GOlO PLATED LEADS.
5. $.P. SEATING PLANE,
6. THE LEAO DIAMETER IS 0 . _ ID.Ol81n.1 TYP.

4

,

Electrical Operation
The detector section of the sensor can be connected as a
single photodiode, or as a photodiode transistor amplifier.
When photodiode operation is desired, it is recommended
that the substrate diodes be defeated by connecting the
collector of the transistor to the positive potential of the
power supply and shorting the base-emitter junction of
the transistor. Figure 15 shows photocurrent being
supplied from the anode of the photodiode to an inverting
input of the operational amplifier. The circuit is
recommended to improve the reflected photocurrent to
stray photocurrent ratio by keeping the substrate diodes
from acting as photodiodes.

The cathode of the 700nm emitter is physically and
electrically connected to the case-substrate of the device.
Applications that require modulation or switching of the
LED should be designed to have the cathode connected to
the electrical ground of the system. This insures minimum
capacitive coupling of the switching transients through
the substrate diodes to the detector amplifier section.

SCHEMATIC DIAGRAM

CONNECTION DIAGRAM

VD

The HEDS-1000 detector also includes an NPN transistor
which can be used to increase the output current of the
sensor. A current feedback amplifier as shown in Figure 6
provides moderate current gain and bias point stability.

Vc

REFLECTOR
REFERENCE
PLANE

t

TOP VIEW

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2
3
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: 'mAI'ISISTOR £MITTER

Absolute Maximum Ratings at TA=25°C

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FUNCTION
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TRANSISTOR COLUCTOR
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Parameter

Symbol

Mfn.

Max,

TS

-40

+75

-

Storage Temperature
Operating Temperature

TA

-.20 '.

Lead Soldering Temperature
1 ,6mm from Seating Plane

IF

Peak LEO Forward Current

IFPK

R'lverse LEO Input Voltage

VR

Package Power Dissipation

Pp

Collector Output Current

10

Supply and Output Voltage

VO,VC,vE

Transistor Base CUrrent

Is

'Transistor Emitter Base Voltage

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System Electrical/Optical Characteristics at TA =25°C
Parameter

Symbol

Min.

Typ.

Max.

Total Photocurrent (lPR+lps)

Ip

100

140

250

Transistor DC Static Current
Transfer Ratio

Fig.

Note

TA=-20'C
nA

IF=35mA, VD=Vc=5V

TA=25'C

2.3

TA=70'C

15

6.5

Ip=35mA, Vc=Vo=5V

3

200

TA=-20'C
Vce=5V, Ic=10!,A
TA-25'C

50
Reflected Photocurrent OPRl to
Internal Stray Photocurrent (Ips)

Conditions

Unite

375

4

IPR

iPS

4

hFe

50
100

Slew Rate
Image Diameter

d

Maximum Signal Point

Q

50% Modulation Transfer
Function

4.02

.06

VII's RL=100K
RF= 10M

.17

mm

If=35mA,Q=4.27mm 10.168In.)

mm

Measured from Reference Plane

4.27

MTF

2.5

Depth of Focus

.lQ
FWHM

1.2

Effective Numerical Aperature

NA

Image Location

D

Thermal Resistance

0JC

4.52

IpK=50mA
tON=100!,s, Rate = 1 kHz

loprlmrr IF"'35mA, Q =4.27mm
mm

50% of Ip atQ""4.27mm

.51

mm

Diameter Reference to Centerline
Q=4.27mm

85

'C/W

4,5
6

8.10

8,9

9
10,11

5,7

9

5

.3

6

Detector Electrical/Optical Characteristics at TA =25°C
Parameter

Symbol

Min.

Typ.

Max.

Units

5

120
10

pA
nA

Dark Current

Ipo

CapaCitance

Co

45

Flux Responslvity

Rd>

.22

pF

..h...

Conditions

I

TA=25'C
TA=70'CI

Fig.

Note

IF=Q, Vo=SV;
Reflection=O%

Vo=OV, Ip=O, 1=1 MHz
,\.=700nm, Vo=5V

12

W

Detector Area .

,160

Ao

mm2 Square. with Length=Amm/Side

Emitter Electrical/Optical Characteristics at TA=25°C
Parameter

Symbol

Forward Voltage

VF

Reverse Breakdown Voltage

eVR

Radiant Flux

Min.

Typ.

Max.

Units

1.6

1,8

V

IF=35rnA

V

IR=1001"A

5

Conditions

IF=35mA, ,\.=700nm

14

nm

IF=35mA

14

if>E

5

'\'p

680

700

Thermal Resistance

0JC

150

"CIW

tNF/.:.r

·1.2

mV/'C IF=35mA

. Temperature Coefficient of VF

6

13

!'W

-Peak Wavelength

9,0
720

Fig.

Note

Transistor Electrical Characteristics at TA=25°C
Parameter

Min.

Symbol

Typ.

Uax.

Units

Fi(j.

Conditions

Collector-Emitter Leakage

ICEO

1

pfA,

VCE"'5V

Base-Emitter VOltage

VeE

.6

V

1c=10pA•. ts=70nA

Collector-Emitter Saturation
Voltage

VceISAT)

.4

V

's=1~.

Collector·Base CapaCitance

CCB

.3

pF

f=1MHz, Vce=5V

~$e-Emitter Capacitance

CBe

.4

pF

f='lMHz, VBE=OV

.Thermal Resistance

eJC

200

'C/W

Nola

~

Ie=10PA

NOTES:
1. 300l's pulse width, 1 kHz pulse rate.
2. Derate Maximum Average Current linearly from 65· C by 6mA/· C.
3. Without heat sinking from TA = 65·C, derate Maximum Average Power linearly by 12mW/·C.
4. Measured from a reflector coated with a 99% reflective white paint (Kodak 6080) positioned 4.27mm (0.168 in.) from the reference plane.
5. Peak-to-Peak response to black and white bar patterns.
6. Center of maximum signal point image lies within a circle of diameter D relative to the center line of the package. A second emitter
image (through the detector lens) is also visible. This image does not affect normal operation.
7. This measurement is made with the lens cusp parallel to the black-white transition.
8. Image size is defined as the distance for the 10%-90% response as the sensor moves over an abrupt black-white edge.
9. (+) Indicates an increase in the distance from the reflector to the reference plane.
10. All voltages referenced to Pin 4.
11. CAUTION: The thermal constraints of the acrylic lens will not permit the use of conventional wave soldering procedures. Thetypical
preheat and post cleaning temperatures and dwell times can subject the lens to thermal stresses beyond the absolute maximum
ratings and can cause it to defocus.

2.01-~~+l+ttit-++tttHtt--t.,.H+ttitl-~-++Hftil
1.81-·-+~+l+ttit-++tttHtt--t--H+ttitl-~-++Hftil

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1
10
100
1000
10.000

60

80

Figure 2. Relative Total Photocurrent vs. LED DC
Forward Currem

Figure 1. Maximum Tolerable Peak Current vs; Pulse Duration

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REFLECTOR

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IF - DC FORWARD CURRENT (mA)

tp - PULSE OURATION IllS)

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SUBSTRATE, CASE
Ip=lpR+Ip.s
NOTE:
1.1, MEASUREMENT CONDITIONS ARE; R: '" 4.27mm,
KODAK 6080 PAINT REFLECTOR.
2. Ips MEASUREMENT CONDITIONS ARE; ~ _ 0 0
A CAVITY WHOSE DEPTH IS MUCH GREATER THAN
THE HEQS.1000 DEPTH OF FIELD.

Figure 3. Ip Test Circuit

7

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DETECTOR IMAGE
THROUGH EMITTER
LENS

+------.--Vo

f\

18

Figure 5. Common Emitter Collector Characteristics

-~--,

REFLECTOR

16

VeE - COLLECTOR-TO-EMITTER VOLTAGE (V)

Figure 4. Normalized Transistor DC Forward Current Gain vs.
Base Current at Temperature

PLANEr

~

i-""'" ,~

f-

10,000

1000

18 - BASE CURRENT (nA)

REFERENCE

i-""'"

20nA

100

IFPK =5OmA
tp-l00IlS, RATE = 1KHz

roo...... .....,.
.....,. .....,. ,....

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MAXIMUM

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Figure 6. Slew Rate Measurement Circuit

l

EMITTER IMAGE
THROUGH DETECTOR
LENS

Figure 7. I mage Location

0.4
110

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0.4

0.6

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iI£ - DISTANCE FROM MAXIMUM SIGNAL (mm)

12 - REFLECTOR DISTANCE (mm)

Figure S. Image Size vs. Maximum Signal Point

Figure 9. Reflector Distance vs. % Reflected Photocurrent

8

110
lOa

"-

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90

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SPATIAL FREQUENCY (LINE PAIR/mm)

Figure 11. Modulation Transfer Function

~,

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II:

40
30

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C

26"C"

20

I

10

I
600

700

900

800

1000
VF - FORWARD VOLTAGE (V)

A - WAVELENGTH (nm)

Figure 12. Detector Spectral Response

1.2

I\O'C

I

1.0

Figure 13. LED Forward Current vs. Forward Voltage
Characteristics

Vee

,

REFLECTOR

I

CATHODE

e.
660

~V

4

SUBSTRATE. CASE

~\.

I

O. 2

--,

ANODE

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fl I

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0.6

+

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REFERENCE
PLANEr

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0.8

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80
70

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60

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Figure 10. Step Edge Response

w

I

L

¢

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m

I"'"

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20

.:Id - EDGE DISTANCE (mm)

z

\.

70

0

J

1\

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---4-

r ~s
p

-

I

_..J

8

.~[\.

~~
680

700

720

740

760

x. - WAVELENGTH (nm)
Figure 14. Relative Radiant Flux vs. Wavelength

Figure 15. Photodiode Interconnection

9

VOUT

', ".,
,DIGITAL
BAR CODE WAND
Features
• 0.3 mm RESOLUTION
Enhances the Readability of dot matrix printed
bar codes
• DIGITAL OUTPUT
Open Collector Output Compatible
with TTL and CMOS
• PUSH-TO-READ SWITCH
Wand Consumes Power Only When Switch is
Depressed
• SINGLE SUPPLY OPERATION
• STYLIZED CASE
• DURABLE LOW FRICTION TIP
• SOLID STATE RELIABILITY
Uses LED and IC Technology

Description

Applications

The HEDS-3000 Digital Bar Code Wand is a hand held
scanner with integral push-to-read switch. It is designed
to read all common bar code formats that have the
narrowest bars printed with a nominal width of 0.3 mm
(0.012 in.). The wand contains an optical sensor with a 700
nm visible light source, photo IC detector, and precision
aspheric optics. Internal signal conditioning circuitry
converts the optical information into a logic level pulse
width representation of the bars and spaces.

The Digital Bar Code Wand is an effective alternative to
the keyboard when used to collect information in selfcontained blocks. Bar code scanning is faster than key
entry and also more accurate since most codes have
check-sums built-in to prevent incorrect reads from being
entered.
Applications include remote data collection, ticket
identification systems, security checkpoint verification,
file folder tracking, inventory control, identifying assemblies in service, repair, and manufacturing environments,
and programming appliances, intelligent instruments and
personal computers.

The HEDS-3000 comes equipped with a push-to-read
switch which is used to activate the electronics, and strain
relieved 104 cm (41 in.) cord with nine-pin subminiature
D-style connector.

wand Dimensions
" 23(0.91-,

------.jl~--.,--~;-- -----t~I
r---------~I'~-t:,U.Iol.I,l:':CJO]
'050 141.0)

. m;:E;lL OIMENSt()N$ IN Ml~LlMETRES AND IINCHES).
2, WEIGHT, ~.. 4ti,S. 11.5 ... l. Shit>!>lng 171g 15,5 ...).

10

,0 (08) J

Recommended Operating
Conditions

Electrical Operation
The HEDS-3000 consists of a precision optical sensor, an
analog r amplifier, a digitizing circuit, and an output
transistor. These elements provide a TTL compatible
output from a single voltage supply range of 3.6V to 5.75V.
A non-reflecting black bar results in a logic high (11 level,
while a reflecting white space will cause a logic low (01 at
the Va connection (pin 21. The output of the HEDS-3000 is
an open collector transistor.

A push-to-read switch is used to energize the 700 nm LED
emitter and electronic circuitry. When the switch is
initially depressed, its contact bounce may cause a series
of random pulses to appear at the output, Va. This pulse
train will typically settle to a final value within 0.5 ms.

Absolute Maximum Ratings
'MIn;

-0.5·

Electrical Characteristics (Vs = 3.6V to 5.75V at TA = 25°C, RL = 2.2kO,unless otherwise noted)
FIg•. Nqtes

OtitPutF.lIie.: :r(~'<
Outpu
(.

'"

. )

$~p!f

l ..

Block Diagram
~'

',\,

,
'

,

,~"

"

.3 E

11

Vs'9l
'(012).

GN\)f/f ..

GUARANTEED WIDTH ERROR PERFORMANCE
(Vs

= 5V, TA = Q·e to 55·e,

RL

= 2.2kO,unless otherwise noted)
Max,"

,Unlb'

Conclillons

, Fig. Notes

"';', -:~'5

.

'2,6 ~1,8,
11 ' ,.9~10

\,":~~:
• '·Width '

,

'~h

,9

·7

\~·Er.ror,\

.'

.

'.

,SPace::, '
< Witith':'
..,: Error':

'.. '

,em/s.·

EnliUer,Peak

WaVeI&ligth

TYPICAL WIDTH ERROR PERFORMANCE
1),Ic:I!J,W.E
Tlfl '" 0-

"

..

,Parameter
From

To,

Margin,

1st

15

lb

2s

lb

.lbl·

1s

2b

2s

2b

lb·

1.

~b2-2

0.11 (4.21 '

1,2

2b

1s

lb

2s

.1$2:-1

.18':"'2

2s

' AS2-2

5,7.8

mm
(In.1<10-3)

1.2 6.7,8

. 0,0f! (2.5)

0.07 {2.S;

'. mm
(in.)(10-31

1,2

6,7.8

1.2

6,7.8

1.2

6.7.8

1.2

6,~,8

1,2

6,7,8

mm
On.)(1O"3)

1,2

6,7,8

mm
(in.1<10·31

1.2

6.7,/:1

0.02 (0.7)

.... : . O.OS..d.91
:.:::'

'

"

0.05 (2.11:

" ,.(J.tl4j-1A)

.0;04 H.4)

H,O}

,(l.03 "1,11

.0.03

. .0.07:(-2.7;

"

.' :.0.08 (-3.31
.-

·2b

Flg. Notes.

0.040.6)

"

Space
Width
Error

Conditions

0.03 (1.21

. ,;" ," .' ,'.~';'

As'''':I'

= 2.2kO,unless otherwise noted)

mm
On.)(10-31

'.0.02..\0,9) .'•• "

;lb.1-?

RL

Units

..

' Ab2-:1

= 25·e,

Tilt'" SO·

Bar
Width
Error

TA

HeIght;'" O.OnIm

'0:08 i3.2J

Abl-',

= 5V,

,Typical WE

"

Hetght",O.25mm

Symbol

(Vs

-0.08 (-2.4)

.0.06 (02:41

Notes:
1. Storage Temperature is dictated by Wand case.
2. Power supply ripple and noise should be less than 100 mV.
3. Switch bounce causes a series of sub-millisecond pulses to
appear at the output, Vo.
4. Push-to-Read switch is depressed, and the Wand, is placed on
a non-reflecting (black 1 surface.
5. The margin refers to the reflecting (white) space that preceeds
the first bar of the bar code.
6. The interior bars and spaces are those which follOW the first
bar of bar COde tag.

Margin z 5mm
mm
Hr-l s--:Q.3mm
(In.)(10-3 1 ·2b=2s..o.6mm
TA"'25°C
mm
(lo,x10-3) . Vs=5V
vscan"'50cm/s
, ,mm
Preferred Orientation
(lo.XlQ-3)
Standard Test Tag
mm
iln.xl0-3 )

7. The standard, test tag consists of black bars, white spaces (0.3
mm, 0.012 in. min.) photographed on Kodagraph Transtar
TC5!!> paper with a print contrast Signal greater than 0.9.
8. The print contrast signal (PCS 1 is defined as: PCS = (Rw - Rb)
IRw. where Rw is the reflectance at 700 nm from the white
spaces. and Rb is the reflectance at 700 nm for the bars.
9. 1,.0 in. = 25.4 mm. 1 mm = 0.0394 in.
10. The Wand is in the preferred orientation when the surface of
the switch button is parallel to the height dimension of the bar
code.

12

[

OPERATION CONSIDERATIONS

j~

within a character. These techniques will produce a higher
, percentage of good reads.

The HEDS-3000 resolution is specified in terms of a bar
and space Width Error, WE. The width error is defined as
the difference between the calculated bar (space) width,
B, (S), and the optically measured bar (space) widths, b
(s), When a constant scan velocity is used, the width error
can be calculated from the following:

The Wand will respond to a bar code with a nominal
module width of 0.3 mm when it is scanned at tilt angles
between 0° and 30°, The optimum performance will be
obtained when the Wand is held in the preferred
orientation (Figure 1), tilted at an angle of 10° to 20°, and
the Wand tip is in contact with the tag. The Wand height,
when held normal to the tag, is measured from the tip's
aperture, and when it is tilted it is measured from the tip's
surface closest to the tag. The Width Error is specified for
the preferred orientation, and using a Standard Test Tag
consisting of black bars and white spaces. Figure 2
illustrates the random two level bar code tag. The
Standard Test Tag is photographed on Kodagraph
Transtar TC5® paper with a nominal module width of
0.3 mm (0.012 in.) and a Print Contrast Signal (PCS) of
greater than 90%.

B = tb' Vscan
S = ts' Vscan
Llb = B - b
Lls=S-s
Where
Llb, Lls=
b, s =
B, S =
Vscan =
tb, ts =

bar, space Width Error (mm)
optical bar, space width (mm)
calculated bar, space width (mm)
scan velocity (mm/s)
wand pulse width output(s)

The magnitude of the width error is dependent upon the
width of the bar (space) preceeding the space (bar) being
measured, The Guaranteed Width Errors are specified as a
maximum for the margin to first bar transition, as well as,
maximums and minimums for the bar and space width
errors resulting from transitions internal to the body of the
bar code character. The Typical Width Error Performance
specifies all possible transitions in a two level code (e.g. 2
of 5), For example, the Llb 2- 1 Width Error specifies the
width error of a single bar module (0.3 mm) when
preceeded by a double space module (0,6 mm).
The Bar Width Error Llb, typically has a positivO) polarity
which causes the calculated bar, B, to appear wider than
its printed counterpart. The typical negative polarity of the
Space Width Error Lls, causes the measured spaces to
appear narrower. The consistency of the polarity of the
bar and space Width Errors suggest decoding schemes
which average the measured bars and measured spaces

BAR WIDTH 0.3 mm (0.012 in.) BLACK & WHITE
RWHITE;;t. 75%,PCS> 0.9 KODAGRAPH TRANSTAR TCS8 PAPER

Figure 2. Standard Test Tag Format.

PUSH-TO-READ

-.l

+5V
./

0

Vs (91

4,7"F

;r-

RL =2.2kn

V

74LS14

(
HEOS-3000

Figure 1. Preferred Wand Orientation.

GN 0(7)

Figure 3. Recommended Logic Interface.

13

Typical performance Curves (R L = 2.2kn)
0.15

0,10

I

0.15

"

N

0.05 .'b,

PREFERRED
ORIENTATION

lS~BAR /: ...... ","

0.10

HEIGHT = 0.1 mm
vscan = 50 em/s

INTeRNA~ BAR~L,--, ~._

STANDARD TAG

WIDTH eRROR·l,.... ..."""

a:

oa:

0,05

(0.3 mm)

a:

Vs "" 5V

a?
a:

TA "" 25°C

ffi

w

:I:

b
!E

~

..\s, INTERNA~ SPAC;--.. ..
WIDTH ERROR

I -0.05

~
;:

.,

-0.10

I

-0.15

5'

o-

TILT - DEGREES

Figure 4. Width Error vs. Tilt (Preferred Orientation).

-

1ST BAR

0,10

I--

ffi

\

.ls, INTERNAL
SPACE WIDTH ERROR '

-0.05

-0.10

o

-

,..

L

J.

PREFERRED ORIENTATION

I-- I--

-0.10

r- t--0.15

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

I---f-- TILT" D·
vscan" 50 omi, 1--1-r-.-r- S~:~D5~RD TT:G=(~':u~m)
r-r---

o

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
h - HEIGHT - mm

h - HEIGHT - mm

Figure 6. Width Error vs. Height (Preferred Orientation).

Figure 7, Width Error vs. Height (Any Orientation).

0.15

0.15

0.10
~

I

~~

0.05
i

w

-L

!O

. +--

I

I

i

.~ .....

..

I

I

I

!

i

L

:

,
f-

r-

I I
I

I

I
I

i

Vs = 5V

vscan = 50 cm/s

I I I I I I

I

I

a:
oa:

I

:I:

~PACE

\

I

I . ~lo.TH

i

!E

I -0.05

_. f::...

r-0.15

-

t--

-

I--

o

10

i

I

..\.-1

I

WIDTH ERROR
I

-0.10

ERROR

.l" INTERNAL SPAce!

~
-f-

i
I

b

I

I'

ffi

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
b,s - BAR.

I

-j~'f-'b.INTEI!f'JAL BAR_

0.05

I

I

T.A. '" 25°C
TILT" 0"

I

I

1ST BAA

TT

pIREF~RR~D oIRIE~TAiION I

HEIGHT = 0.25 mm

I

a

i1

0.10

INTERNAL SPACE WIDTH ER'ROR

~ ~r

w
S

-0.15

I

1ST BlR

L"_1
~"

I -0.05

-0.10

I

I ..\b, lNTERNAL BAR WlOTH ~RAOR

a:
oa:
a:

i!'Cl

r,

\

PREFERRED ORIENTATION
TILT=O°
vscan"" 50 emls
STANDARD TAG (0.3 mm)
TA = 25"C
Vs = 5V

I--

r-0.15

H

-

J.

~

;:

I +I

0.151--1--+_++---:i.-G--4,.-+-+--+--+--I
1ST BAR /

\

..\'1lN~~~~Al. B,AR W!DTH ,EF!ROR

~
~

.Y

1/

TILT - DEGREES

Figure 5. Width Error vs. Tilt (Any Orientation).

1-,

0.15

a:

f---+-+-+--+-!---1"M-+--+-!--+-+

10' 15' 20' 25' 3D' 35'

o-

0.05

-0.05

w

r"-

-0.10

~

,--,--,.-,---r-r--r----r-,---r-,--,---,

I

r

I

PREFERRED ORIENTATION
TILT = 0°
HEIGHT = 0.25 mm
STANDARD TAG (0.3 mm)
TA = 25°C
Vs = 5V

20

30

40

50

60

70

80

vscan - SCAN VELOCITY - cm/s

WIDTH - mm

Figure 8. Width Error vs. Bar Width.

Figure 9. Width Error

14

VS.

Scan Velocity.

t-- t--

-I--

0.15

0.15

J

0.10
E
E

o

I

0.10

1ST BAR

0.05

I

.." INTERNAL BAR Wlo1 ~ERROR

0:

0.05
..lb. INTERNAL

0:

.. -=

0:
0:
W

lJ

BAk-

E
E

0

:I:

PREFERRED DRIENTATIDN
HEIGHT = 0.25 mm
TILT=O°
STANDARD TAG (0.3 mm)
Vs =5V
vscan'" 50 ~m/s I

0

W

0

:I:

f-

!WI WI.QTIi"('RROR-

"'

0:
0:

--

0

f-

0

ii:

As. INTI!

I -0.05

~
-0.10

- r-- r--

/INA

0

I

ii:

3.5

4.0

w

4>. INTERINAL SPACE WIDTH ERROR

;::

STANDARD TEST TAG (0.3 mm)
TA '" 25"

-0.15

I -0.05

SPo.cE ;WIDTHTROR-

PREFERRED ORIENTATION
HEIGHT' 0.25 mm
TILT· 0 vscan '" 50 em!s

4.5

5.0

-

.~

f-

-

-0.10

r-

5.5

~.15

6.0

5' 10' 15' 20" 25' 30' 35' 40' 46' 50' 55'
TA - TEMPERATURE - 'c

Vs - SUPPLY VOLTAGE - V

Figure 10. Width Error vs. Supply Voltage.

Figure 11. Width Error vs. Temperature.

MECHANICAL CONSIDERATIONS
The HEDS-3000 includes a standard nine pin D-style
connector with integral squeeze-to-release retention
mechanism. Two types of receptacles compatible with the
retention mechanism are available from AMP Corp.
(Printed circuit header: 745001-2 Panel mount: 745018,
body; 66570-3, pins). Panel mount connectors that are
compatible with the HEDS-3000 connector, but do not
include the retention mechanism, are the Molex A7224,
and AMP 2074-56-2.

HEDS-3001

Figure 12. Wand Tip.

After cleaning the tip aperture and sensor window, the tip
should be gently and securely screwed back into the
Wand assembly. The tip should be replaced if there are
visible indications of wear such as a disfigured, or
distorted aperture. The part number for the Wand tip is
HEDS-3001. It can be ordered from any Hewlett-Packard
parts center or franchised Hewlett-Packard distributor.

MAINTENANCE CONSIDERATIONS
While there are no user serviceable parts inside the Wand,
the tip should be checked periodically for wear and dirt, or
obstructions in the aperture. The tip aperture is designed
to reject particles and dirt but a gradual degradation in
performance will occur as the tip wears down, or becomes
obstructed by foreign materiais.

OPTIONAL FEATURES

Before unscrewing the tip, disconnect the Wand from the
system power source. The aperture can be cleaned with a
cotton swab or similar device and a liquid detergent.

The wand may also be ordered with the following special
features:
• 193 color options
• Customer specified label
• No label
• Heavy duty retractable coiled cord
• No connector
• No switch button
For more information, call your local Hewlett-Packard
sales office or franchised distributor.

The glass window on the sensor should be inspected and
cleaned if dust, dirt, or fingerprints are visible. To clean the
sensor window dampen a lint free cloth with a liquid
cleaner, then clean the window with the cloth taking care
not to disturb the orientation of the sensor. DO NOT
SPRAY CLEANER DIRECTLY ON THE SENSOR OR
~.

A

...41

~aw~

~ll

0l!1
. ~~5)
26.8

L~"", -~
.1

i

111:11

t

16.8
(0.62)

[llOOOOO

0000

j

NOTES:
1. ALL DIMENSIONS IN MILLIMETRES AND (INCHES).

IIII

98 76

Figure 13. Connector Specifications.

15

----- -----

--

--

1
2

.NC

3.
4
5
-6

NC
NC
NO

7
8
9

54321

~DH

FUNCTION

. PIN

DJ

VoOUTPUT

NC
GROUND
NC
v$ SUPFLY VOLTAGE

,

,,"

.

HEWLETt

.

','
,

PACKARD",

.,.. 670nm
·.HIGHRADIANT

HEMT·3300

. 'INTENSITY
·. ··EMlTTER

~:

-----.;.---.;.-----.;.----~~~~~~-~-=~~',
TECHNICAL DATA MARCH 1980

Features

.cPackage Dimensions

I ..

• HIGH EFFICIENCY
• NONSATURATING OUTPUT

}~tjffi

• NARROW BEAM ANGLE
• VISIBLE FLUX AIDS ALIGNMENT

!

I

• BANDWIDTH: DC TO 3 MHz
• IC COMPATIBLE/LOW CURRENT
REQUIREMENT

Description
The HEMT-3300 is a visible, near-IR, source using a
GaAsP on GaP LED chip optimized for maximum
quantum efficiency at 670 nm, The emitter's beam is
sufficiently narrow to minimize stray flux problems, yet
'broad enough to simplify optical alignment. This product
is suitable for use in consumer and industrial applications
such as optical transducers and encoders, smoke
detectors, assembly line monitors, small parts counters,
paper tape readers and fiber optic drivers,

Electrical/Optical Characteristics at TA =25°C

1?v

Desc:ription
Axial Radiant Intenslr/
Temperature CQefficient
of Intell$lty
luminous Efficacy

2eY.,

Half Intensity Total

XPEAK'

Peak Wavelength

AAi'EAK/AT

Spectral Shift Temperature
Coefficient

Symbol
Ie

Ke

"

600.

'1/pW?i.Y
.--_. .

-0.009

°C"

Reverse' Breakdown Voltage

'. ';'ilYliW

22

~ngre

22 "
670 .'
0.089

IF '" 10 mA

Figure

3,4

If '" 10 mA, Note 1
Note 2

deg.

Note 3,IF '" 10 mA

6

nm

Measured at Peak

1

nmfC

Measured at Peak.
Note 4

120

. ns

·50

ns

Ip~K ,., 10 mA Pulse

IpEAK=10mA

pF

\If .. 0; f = 1 MHz

V

~ <=

V

IF "10mA

·2.2 .'

mvfc

IF'" l00pA

160

°elW

Junction to cathode
lead at seating plane.

15

capacitance
,.
, .

Test Conditions

~>,,~,

(90%-10%1

Co

BVA

200

Output Fall Time

tv

Units

Typ.

Output Rise Time
(10%-90%)

,

tr

Max.

Min.

5.0

l00#A

,.

\If
AVr;/AT

9JC

Forward Voltage

Temperature Cf;Iefficient

of""
Therl'T1l!l Resistance

"1.9

2.5

2

Notes: 1, Ie (T) = Ie (2SoC)exp [Ke(T- 25"cll 2 Iv = 'lvle where Iv is in candela, Ie in watts/steradian and 'lv in lumen/wan,
3. El% is the off-axis angle at which the radiant intensity is half the axial intensity. The deviation between the mechanical and optical axis is
typically within a conical half-angle of five degrees. 4.I\PEAK (T) = I\PEAK (2S0C) + (AI\PEAK/AT) (T - 2S0C).

16

-.

.

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . .. 120 mW
(derate linearly from 50°C at 1.6 mW;oC)
Average Forward Current ..................... 30 mA
(derate linearly from 50°C at 0.4 mA/oC)
Peak Forward Current ................... See Figure 5
Operating and Storage
Temperature Range ............... -55° C to +1 OO°C
Lead Soldering Temperature .......... 260°C for 5 sec.
(1.6 mm [0.063 inch] from body)
If - FORWARD CURRENT - rnA

Figure 3. Relative Radiant Intensity versus Forward Current.

1.2

I
j

1.0

>

"'ffi"
~

08

w-

j

T. _2Si C

11\

II

0.2

600

tit
4-

I}

0.'

o

.,

\;

>
;::

g

j

i/

0 .•

I

I

..

i\

l'\:.
IITA+-'"

100·C

j

II

I

I I
620

640

660

l\

I

I
680

~

700

720

740

760

A - WAVELENGTH - nm

hAK - PEAK CURRENT - rnA

Figure 4. Relative Efficiency (Radiant Intensity per Unit
Current! versus Peak Current.

Figure 1. Relative Intensity versus Wavelength.

60

"E

A

I

"ffi

".~~

I

'0

/'

0:
0:

"'"
Ii!

";:
0:

~

r"

_.

~

1 I

.~4b 1/ "--"f-

50

~

,

_L

I

/1

I

20

V

I

I

I
I
I I

1/

10

o1.6

,
I ,--t-

7'

30

V

1/
1.8

2.0

2.2

2.4

VF - FORWARD VOLTAGE -

2.6

2.8

v

tp - PULSE DURA nON -

figure 2. Forward Current versus Forward Voltage.

J,lS

Figure 5. Maximum Tolerable Peak Current versus Pulse

Duration. (lDC MAX as per MAX Ratings)

0 - OFF-AXIS ANGLE - DEGREES(CONE HALF-ANGLE}

Figure 6. Far-Field Radiation Pattern.

17

'"
;l

,t~~i:,::- ;,

HEWLETT

PACKARO

700nm
HIGH INTENSITY
SUBMINIATURE
EMITTER

HEMT-6000

TECHNICAL DATA

Features

MARCH 1980

11 ,'"
1
~~~
.Lc=n:;: ;;"( ) ~~
T
eJ

• HIGH RADIANT INTENSITY

!6 f:ii22)
(.Ql~)

"l

,,·41.45)
BOTH $tO£$
r<'N •.J.

• NARROW BEAM ANGLE
• NONSATURATING OUTPUT
• BANDWIDTH: DC TO 5 MHz

ANOD/

• IC COMPATIBLE/LOW CURRENT
REQUIREMENT

CATtiOD£'

1.651....1 '
ti'i1:075t ,mAo

' '

L9l~

1.781.0701

MECHANICAL
AX,S

• VISIBLE FLUX AIDS ALIGNMENT

UNDlFfUSED.UNTlNTED
(CLEAR)
epoxY
~

,

~!

T=

The HEMT-6000 uses a GaAsP chip designed for optimum
tradeoff between speed and quantum efficiency. This
optimization allows a flat modulation bandwidth of 5 MHz
without peaking, yet provides a radiant flux level
comparable to that of 900nm IREDs. The subminiature
package allows operation of multiple closely-spaced
channels, while the harrow beam angle minimizes
crosstalk. The nominal 700nm wavelength can offer
spectral performance advantages over 900nm IREDs, and
is sufficiently visible to aid optical alignment. Applications
include paper-tape readers, punch-card readers, barcode
scanners, optical encoders or transducers, interrupt
modules, safety interlocks, tape loop stabilizers and fiber
optic drivers.

I~

I

=

n

1

j::

A><·::1
~
"
~
lJ
'-Hi\~'

.7.""30I M

t

2'S:ci~~Ol

U
J

lOOn

.

J.

.11 (.0""')
Dronm

Description

~'''''
r '"' rnT.'OUl

\\

--r.....,.,.-......J._;;;-r~~"
"g, 1.0151 MAX..J1l·V~
J UO...l.,
1.056)

I

i.- 1.96{&W

,

~

~

fil!:087J

seE NOTE 3

NOT£S:
tALL DlMHISIONS ARE IN MILUMHRES /INCHES\..
2. SitVER.PLAT-EO lf1:AOS, SEE APPLICATION BUlUTtN 3.
3..USEfl MAY BEND LEADSASSHQWN.

4. EPOXY ENCAPSULANT HAS A FttFRACTIVE INDEX OF t.53,
S, CHIP CENTERtNO wnHIN THE.PACKAGE IS CONSISTENT
wllH FOOTNOTe 3,

Maximum Ratings at TA = 25°C

1.2

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . .. 50 mW
(derate linearly from 70°C @ 1.0mW/°C)

1.0

>
f-

;;;

Average Forward Current ..................... 20 mA
(derate linearly from 70°C @ O.4mAfOC)

I
TA"

2:tc1

0.8

IE

f-

~
w

Peak Forward Current ................... See Figure 5

0.6

It

i
I-- I-U
IL _1
\

>

Operati ng and Storage
Temperature Range ................. -55° to +1 00° C

~
a:

fA '100"C

0.4

1.

0
640

II \

r-

\\

0.2

Lead Soldering
Temperature ...................... 260°Cfor5sec..
[1.6 mm (0.063 in.) from body]

-I--

,

;::

L

\~

~
660

680

I ' I::::::,
700

720

740

i\ - WAVELENGTH - om

Figure 1. Relative Intensity versus Wavelength.

18

".
2.92(.1,51

Electrical/Optical Characteristics at TA = 25°C
Symbol

Description
Radiant Intensity along Mechanical
Axis

Ie
....

[)

Ma)C.

Units

Min •.

Typ. ..

100

250

/J.W/sr

IF "10mA
Note 1

Fig.

Test Conditions

3,4
...

Ke

Temperature Coefficient of Intensity

-0.005

. oc·~

11\1

Luminous Efficacy

2.5

Im/W

26%

Optical Axis Half Intensity Total Angle

16

deg.

NOta 3, IF '" 10 mA

6

APl::AK

Peak Wavelength (Range)

mn .

Measured@Peak·

1

690·715

nmtc

Note 2

ll.Ap'~~

Spectral Shift Temperature Coefficient

tr

Output Rise Time (10%-90%)

70

os

Ii'EAK" 10 mA

tf

Output Fall Time (90%·10%)

40

ns

Ipl::AK=10roA

Co

capacitance

pF

VF ,. O;f "" 1 MHz . .

eVR

Reverse Breakdown Vo Itage

VF

Forward Voltage

.193

..

65
5

..

12

ll.Vf!/ll.T Temperature Coefficient of VF

1.5
-2.1

eJC

140

Thermal Resistance

...

1.8

iVleaslired@Peak, Note 4

=100 iJ.A

V

IR

V

IF=10mA ..

mVtc

°CIW

..

2

IF'" 100 iJ.A
Junction to cathode lead
at 0.79 mm ('031 inl
from body

NOTES: 1. I.(T) = Ie (25°C) exp [Ke (T - 25°Cl].
2 Iv =11vle where Iv is in candela, I. in watts/steradian, and 'I1v in lumen/watt.
3. 9% is the off-axis angle at which the radiant intensity is half the intensity along the optical axis. The deviation between the
mechanical and the optical axis is typically within a conical half-angle of three degrees.
4. k (T) = k (25"C) + (ak /aT) (T - 25°C)
PEAK

PEAK

PEAK

100

=T•• 25'f

~
I

~

~

1.5

-

"o

0;-

z'"
wE

V

~~

10

0:
0:

::>

==

0:

~

-_.

0:

~

-

>
~

z_
~"

"z"E
w_

~@
ON

ii:'"
"-0
Ww 1.0
wN

~~

I

I

A

"'-

I

I

>:::;

0:-'

I

I

;:;~

~~
~~

-

~WJt-

>:<

~~
we

~

lH

j

o:~

I

I

0:

-~

I

0.1

1.2

I
1.3

1.4

1.5

1.6

1.7

0.5
0.1

1.8

VF - FORWARD VOLTAGE - V

Figure 2. Forward Current versus

Figure 3. Relative Radiant Intensity

Forward Voltage.

versus Forward Current.

10

100

IpEAK - PEAK CURRENT - rnA

IF - FORWARD CURRENT - rnA

Figure 4. Relative Efficiency (Radiant Intensity
per Unit Current) versus Peak Current.

e

~

"'w
>-'
~'"

~~
Ww
~z

~8

~~

~2:

-''''

~'"

@~
:::i!::
NJ:

~;:

0:

~

tp -

PULSE DURATION

-.us

NORMALIZED INTENSITY

Figure 5. Maximum Tolerable Peak Current versus Pulse
Duration. (IDe MAX as per MAX Ratings)

0- OFF·AXISANGLE - DEGREES
(CONE HALF·ANGLE)

Figure 6. Far-Field Radiation Pattern.

19

·'~PfN.PHOTODIODES
TECHNICAL DATA

Features

MARCH 1980

Active area: I mm Oiam 5082-420B- TALL SIZE
5082-4203
0.5mm Oiam { 5082-4204 (TO-I 8)
5082-4220 - Short (TO-46)
0.25mm Magnified 2.5x 5082-4205 - Subminiature

• HIGH SENSITIVITY (NEP<-108 dBm)
• WIDE DYNAMIC RANGE (1% LINEARITY
OVER 100 dB)
• BROAD SPECTRAL RESPONSE
• HIGH SPEED (Tr, Tf,<1ns)
• STABILITY SUITABLE FOR PHOTOMETRY/
RADIOMETRY
• HIGH RELIABILITY
• FLOATING, SHIELDED CONSTRUCTION
• LOW CAPACITANCE
• LOW NOISE

Description
The HP silicon planar PIN photodiodes are ultra-fast light
detectors for visible and near infrared radiation. Their
response to blue and violet is unusually good for low dark
current silicon photodiodes.

The S082-4203, -4204, and -4207 are packaged on a
standard TO-18 header with a flat glass window cap. For
versatility of circuit connection, they are electrically
insulated from the header. The light sensitve area of the
S082-4203 and -4204 is 0.S08mm (0.020 inch) in diameter
and is located 1.90Smm (0.07S inch) behind the window.
The light sensitive area ofthe S082-4207 is 1.016mm (0.040
inch) in diameter and is also located 1.90Smm (0.07S inch)
behind the window.

These devices are suitable for applications such as high
speed tachometry, optical distance measurement, star
tracking, densitometry, radiometry, and fiber-optic
termination.
The speed of response of these detectors is less than one
nanosecond. Laser pulses shorter than 0.1 nanosecond
may be observed. The frequency response extends from
dc to 1 GHz.

The S082-420S is in a low capacitance Kovar and ceramic
package of very small dimensions, with a hemispherical
glass lens.
The S082-4220 is packaged on a TO-46 header with the
0.S08mm(0.020 inch) diameter sensitive area located
2.S40mm (0.100 inch) behind a flat glass window.

The low dark current of these planar diodes enables
detection of very low light levels. The quantum detection
efficiency is constant over ten decades of light intensity,
providing a wide dynamic range.

package Dimensions
DIMENSIONS IN MILLIMETRES (INCHES)
GLASS
WINDOW

ANOD:[E::;::::;t=~=t:::J I I~~~I
r--

1

t

5.003
(.197)

-~-~,~

.406

(.016)

38.10
I
(1.50)MIN. i

I

a,
I~

HEADER-TO·"

(.210)

0-

.,

_

1.511

~1.0601

Lf-~ 12~~1~_
5.334 _I

ANODE

.991
(.039)

CATHODE

CONNECTED
TO CASE

-4203, -4204, -4207

o

CATHODE

I '2.235_1

ANODE·e.: CATHODE

AND CASE

/'

1.--(,088)

-4205

20

-4220

TO 46 HEADER

Absolute

M~;xim.um Ratings
...... .ata-....

Operating and Storage Temperature _55° to 125°C

.1110 .

'. ·.100;.···

,-

. 'UnIts ..
roW .
" volts

..-42211
100
50

Electrical/Optical Characteristics at TA=25°C
AKlI\'.....
1leipoInJa'1I .

~14t.

~Ar. .

10

Rs
*se8

NOTES:
1. Peak Pulse Power
When exposing the diode to high level incidance the
following photocurrent limits must be observed:
Ip (avg MAX.) <

2.
3.

4.
5.

6.
7.

8.

9.
10.
11.
12.

n

Nota 4.

1000 A
Ip (avg MAX.)
Ip(PEAK); and in addition:

Ip • photocurrent (A) f - pulse repetion rate (M H~)
Ec - supply voltage (V) PI/>- power input via photon flux
t - pulse duration (,.s) PMAX - max dissipation (W).

Power dissipation limits apply to the sum of both the optical power input to the device and the electrical power input from flow
of photocurrent when reverse voltage is applied.
Exceeding the Peak Reverse Voltage will cause permanent damage to the diode. Forward current is harmless to the diode, within
the power dissipation limit. For optimum performance, the diode should be reversed biased with Ec between 5 and 20 volts.
Exceeding the Steady Reverse Voltage may impair the low-noise properties of the photodiodes, an effect which is noticeable only
if operation is diode-noise limited (see Figure 8).
The 5082-4205 has a lens with approximately 2.5x magnification; the actual junction area is 0.5 x 10-3 cm 2, corresponding to a
diameter of 0.25mm (.010"). Specification includes lens effect.
At any particular wavelength and for the flux in a small spot falling entirely within the active area, responsivity is the ratio of incremental
photodiode current to the incremental flux prodUCing it. It is related to quantum efficiency, 1Jq in electrons per photon by:
RI/>=1Jq (-L)
1240
where "- is the wavelength in nanometers.. Thus. at 770nm, a responsivity of 0.5 AIW corresponds to a quantum efficiency of 0.81 (or 81 %)
electrons per photon.
At -10V for the 5082-4204, -4205, and -4207; at -25V for the 5082-4203 and -4220.
For ("-, f, At) = (770nm, 100Hz, 6Hz) where f is the frequency for a spot noise measurement and af is the noise bandwidth, NEP is the
optical flux required for unity Signal/noise ratio normalized for bandwidth. Thus:
IN/..{M
where IN/.Jiii is the bandwidth - normalized noise current computed from the shot noise formula:
NEP=
-RI/>
IN/.J7{f=.J2tiiij = 17.9 x '0- '5 v'iD (Atv'Hzj where 10 is in nA.
oetectivity, OOis the active-ares-normalized signal to noise ratio. It is computed:
forA in cm 2,
for ("-, f, At) = (770nm, 100Hz, 6Hz).
At -1 OV for 5082-4204, -4205, -4207, -4220; at -25V for 5082-4203.
Between diode cathode lead and case - does not apply to 5082-4205, -4220.
With 50n load.
With 50n load and -20V bias.

21

f.O

0.8

z

~
or

-:-

,

..,.. ....

l

0.4

~ 0,2

......

ElECTRONS- [-

0.6 ~'PKOroN~••

/'"

7#All'('

~

O. 1
.08

.06
.04

\
.0 1

400

600

800

1000

BIAS VOLTAGE (ANODE TO CATHODE VOLTAGE)

1200

A - WAVELENGTH - nm

Figure 1. Spectral Response.

Figure'2. Relative Directional Sensitivity
of the PI N Photodlodeo.

Figure 3. Typical Output Characteristics
at ~ .. 900nm.

5ii82:-i204MAjCSHO;:~--·---------·---­

NOIS£ OF DiODE (10 • 400 pAl

10-

16

10 2

103
A, -

10 4

10 5-

10~

10 7

10'

LOAD RESISTANCE - OHMS

2~-+_~~~~~,~,_~,-~"

Figure 4. Dark Current at -10V Bias
vs. Temperature.

15~'c~--+-~~~--r-~~==~--~

Figure 6. Noise vs. Load Resistance.

ft:::::-·~~E
O.5~
-10 - 5
VA - REVERSE VOLTAGE - V

Figure 5. Typical Capacitance Variation
With Applied Voltage.
IDS .--.-....... -_ _

i

~

__

~

_ _ _ _ _ _....,

10'

RL - LOAD RESISTANCE - OHMS

Figure 8. Noise Equivalent Power

Figure 7. Photodiode Cut-Off Frequency
VI. Load Resistance (C = 2pF).

VI.

Load Resistance.

Ip=Signel current., 0.5/IA/",W x flux Input at no nm
IN" Shot noise current
<1.2 x 10-14 ampslHz1/2(5082-4204)
<4 x 10-14 ampslHz1/2(5082-4207)
10= Dark current
<600 x 10-12 amps at -10 V de (5082-4204)
<2500 x 10-12 amps at -10 V de (5082-4207)
Rp" 1011n,
RS· <50!!

Figure 9. Photodlode Equivalent Circuit.

22

_!Hlldt. tt

Application Information
NO.ISE FREE PROPERTIES

5082-4205 MOUNTING RECOMMENDATIONS

The noise current of the PIN diodes is negligible. This is a
direct result of the exceptionally low leakage current, in
accordance with the shot noise formula IN = (2qIRD.f) 1/2.
Since the leakage current does not exceed 600 picoamps
for the 5082-4204 at a reverse bias of 10 volts, shot noise
current is less than 1.4 x 10- 14 amp Hz- 1/2 at this voltage.

a. The 5082-4205 is intended to be soldered to a printed
circuit board having a thickness of from 0.51 to 1.S2mm
(0.02 to 0.06 inch).
b. Soldering temperature should be controlled so that at
no time does the case temperature approach 2800C.
The lowest solder melting pOint in the device is 2800C
(gold-tin eutectiC). If this temperature is approached,
the solder will soften, and the lens may fall off. Lead-tin
solder is recommended for mounting the package, and
should be applied with a small soldering iron, for the
shortest possible time, to avoid the temperature
approaching 2800C.
c. Contact to the lens end should be made by soldering
to one or both of the tabs provided. Care should be
exercised to prevent solder from coming in contact
with the lens.
d. If printed circuit board mounting is not convenient,
wire leads may be soldering or welded to the devices
using the precautions noted above.

Excess noise is also very low, appearing only at
frequencies below 10 Hz, and varying approximately as
1/f. When the output of the diode is observed in a load,
thermal noise of the load resistance (Rd is 1.28 x 10- 10
(Rd- 1/2 X (D.f)1/2 at 25°C, and far exceeds the diode shot
noise for load resistance less than 100 megohms (see
Figure 6). Thus in high frequency operation where low
values of load resistance are required for high cut-off
frequency, all PIN photodiodes contribute virtually no
noise to the system (see Figures 6 and 7).
HIGH SPEED PROPERTIES
Ultra-fast operation is possible because the HP PIN
photodiodes are capable of a response time less than one
nanosecond. A significant advantage of this device is that
the speed of response is exhibited at relatively low reverse
bias (-10 to -20 yolts).

LINEAR OPERATION
Having an equivalent circuit as shown in Figure 9,
operation of the photodiode is most linear when operated
with a current amplifier as shown in Figure 10.

-:.;,

OFF-AXIS INCIOP.NCE RESPONSE

II

Response of the photodiodes to a uniform field of radiant
incid!"nce Ee, parallel to the polar axis is given by I = (RA) x
Ee for 770nm. The response from a field not parallel to the
axis can be found by multiplying (RA) by a normalizing
factor obtained from the radiation pattern at the angle of
operation. For example, the multiplying factor for the
5082-4207 with incidance Ee at an angle of 40° from the
polar axis is 0.8. If Ee = 1mW/cm 2, then Ip = k x (RA) x Ee;
Ip = 0.8 x 4.0 x 1 = 3.2 /Lamps.

Rl "" Rz
VOUT = R, lip + lol

" - - - -____--------.--0+}VOUT
Figure 10. Linear Operation.

Lowest noise is obtained with Ec =0, but higher speed and
wider dynamic range are obtained if 5 < Ec < 20 volts. The
amplifier should have as high an input reSistance as
possible to permit high loop gain. If the photodiode is
reversed, bias should also be reversed.

SPECTRAL RESPONSE
To obtain the response at a wavelength other than 770nm,
the relative spectral response must be considered.
Referring to the spectral response curve, Figure 1, obtain
response, X, at the wavelength desired. Then the ratio of
the response at the desired wavelength to response at
770nm is given by:

LOGARITHMIC OPERATION
If the photodiode is operated at zero bias with a very high
impedance amplifier, the output voltage will be:

RATIO = 1S...
0,5
Multiplying this ratio by the incidance response at 770nm
gives the incidance response at the desired wavelength.

VOUT = (1

R2 kT
+-)-q RI

kT

where Is = IF (e nV -1) -I

ULTRAVIOLET RESPONSE
Under reverse bias, a region around the outside edge of
the nominal active area becomes responsive. Thewidth of
this annular ring is approximately 25/Lm (0.001 inch) at
-20V, and expands with higher reverse voltage. Responsivity in this edge region is higher than in the interior,
particularly at shorter wavelengths; at 400nm the interior,
responsivity is 0.1 AIW while edge responsivity is 0.35
AIW. At wavelengths shorter than 400nm, attenuation by
the glass window affects response adversely. Speed of
response for edge incidance is tr, tf ~ 300ns.

11

j/.n

Ip
(1+-)
Is

at" 0 < IF

< 0.1mA

using a circuit as shown in Figure 11.

Figure 11. Logarithmic Operation.

Output voltage, VOUT, is positive as the photocurrent, I p,
flows back through the photodiode making the anode
positive.

23

Fiber Optics!
Fiber optics is emerging as a practical, cost-effective technology for data communications.
Pulses of light traveling down hair-thin fibers are replacing electrical signals transmitted over
copper wires. The transmission of information over optical cables offers many features,
advantages, and benefits, some not available with any other technology:

• Features

• Advantages

• Benefits

Optical transmission
path

Complete input-output
electrical isolation

Freedom from ground loops.
Lightning safe.

Light pulse "carrier"
signals

No EMI susceptibility or
radiation

Freedom from induced noise.
Freedom from crosstalk.
Secure communications.

Very high distance/bandwidth
products achievable

Greater data rates at longer
distances than wire/coax.

Light weight, small diameter
cables possible

Lower cost installation and
maintenance. More bandwidth
(channels) per unit area or unit
weight.

Bandwidth independent
of cable size

Versatile
HP's new fiber optic systems are point-topOint links intended for short to intermediate
distance processor-to-processor or processor-to-peripheral interconnection in
commercial, industrial, or military applications. Some of these are:
• large computer installations
• Distributed processing (minicomputer)
systems
• Hospital computer systems
• Power plant communications/control
• Industrial/process control
• Industrial or military secure
communications
• Aircraft/shipboard data links
• High voltage or electromagnetic field
research
• Remote instrumentation systems
• Factory data collection
In many of these applications induced noise,
grou nd potential differences, high voltage, or
extended distance, make twisted wire or
coaxial data links difficult or impossible to
use. Fiber optics can offer an alternative to
expensive shielding, conduit, isolation
transformers, or data error checking and
retransmission circuitry.
26

C···

.....

Easy-To-Use
The HP Fiber Optic Link is a versatile, easyto-use system. It does not require optical
design expertise, calibration or adjustment.
To make it easy to get started, HP offers the
HFBR-0010, a complete 10 metre simplex
link consisting of a transmitter, a receiver, a
10 metre cable/connector assembly, and
technical literature. Also available are
separate components: the HFBR-1001 100
metre digital transmitter the HFBR-1002,
1000 metre digital transmitter, the HFBR2001 digital receiver, and the HFBR-3000
cable/connector assemblies.

System Specifications·
DATA RATE:
DATA FORMAT:
LINK DISTANCE:
BIT ERROR RATE:
DATA INPUT:
DATA OUTPUT:
CABLE
CONSTRUCTION:

HP systems feature:

DC to 10Mb/s NRZ
No restrictions
0 to 1000 metres
10-9 max. at 10Mb/s
NRZ
TTL compatible
(1 LSTTL load)
TTL compatible (up
to 20 LSTTL loads)

• Compatible plug-together transmitters;
receivers, and cable assemblies
• Miniature PC board mountable packages
• TTL electrical interfaces
• Single 5 volt power supply requirement
• Accepts any data format from DC to
10 Mbits NRZ

Reinforced, polyurethane jacketed,
single fiber, glass
core and cladding.

• Accommodates cable lengths up to
1000 metres

• Integral fiber optic connectors

POWER SUPPLY
REQUIREMENTS
TRANSMITTER:
RECEIVER:

• Built-in "link monitor"

5V±5% at 125mA
5V±5% at 100mA

OPERATING TEMPER?ATURE RANGE:
O°C to 70°C
• Detailed electrical and mechanicaf specifications are
contained in the following data sheets: HFBR-1001,
HFBR-1002, HFBR-2001, HFBR-3000.

Systems and Components
HP Part No.
HFBR-0010
HFBR-1001
HFBR-1002
HFBR-2001
HFBR-3000

Description
Complete 10 Metre Simplex System (Contains
one each HFBR-1001, -2001, -3001)
100 Metre Digital Transmitter
1000 Metre Digital Transmitter
Digital Receiver
Cable/Connector Assemblies: In User Specified
Cable Lengths

27

Page No.
(Contact HP
Sales Office)
28
32
36
40

HEWLETT
PACKARD .

. ..•. ·····FIBER OPTIC
;100MEJREDIGITAL
rRANSMITTER

(

TECHNICAL DATA

MARCH 1980

Features
• HIGH SPEED: dc

to 10MB/S NRZ"

• LONG DISTANCE: 100 metres"
• LOW PROFILE: Fits 12.7mm (0.5") spaced card rack
• NO HEAT SINK REQUIRED
• ARBITRARY DATA FORMAT"
• TTL INPUT LEVELS
• SCHMITT DATA INPUT
• OPTICAL PORT CONNECTOR
• SINGLE 5V SUPPLY
·When used with HFBR-2001 Receiver Module and HFBR-3000
Cable/Connector Assemblies.

Description
The HFBR-1001 fiber optic transmitter is an integrated electrical to optical transducer designed for digital data transmission over
single fiber channels. A bipolar integrated circuit and a GaAsP LED convert TTL level inputs to optical pulses at data rates from
dc to 10Mb/s NRZ. An integral optical connector on the module allows easy interfacing without problems of sourcelfiber
alignment. The low profile package is designed for direct printed circuit board mounting without additional heat sinking.
The HFBR-1oo1 is intended for use with HFBR-3000 fiber optic cable/connector assemblies, and the HFBR-2oo1 fiber optiC
receiver for transmission distances up to 100 metres. The HFBR-1OO1 generates optical signals in either of two externally
selectable modes. The internally-coded mode produces a 3-level coded optical signal for reception and decoding by the HFBR2001 receiver. This feature provides data format independence over the data rate range of dc to 10Mb/s NRZ while allowing for
wide dynamic range and high sensitivity at the receiver. The externally-coded mode produces a 2-level optical signal which is a
digital replica of the data input waveform. Used in this mode with the HFBR-2001 receiver, the user must provide proper data
formatting (explained in the HFBR-2001 data sheet) to insure proper receiver operation. In either mode, the radiant output is
radiologically safe (per ANSI Z136.1-1976).

Package Dimensions
PIN

WHITE DOT

CAUTION,
1. LOCK NUT AND MRREL SHOULD
NOT BE QISTUA8!O.

2. SCREWS ENTEAING THE 2-56
THREADED MOUNTING HOLES

3

~~n~~n£~%'b:~~~~R

SHOULD NOT BETIGHTEN£D
BEYOND THE LIMITS SPliCIFIED
IN THE H F6R.3000 DATA SHEET.

2.64 TYP.
1.100)
3.35
1.13Z)

L..=1

PIN
1

10.16 ±.2S
1.400±.010j

FUNCTION
MODE SELECT

2

N.C.

3

GROUND

4
S

vee
DATA INPUT

I·

NOTES,
1. DIMENSIONS 11\1 ",m (INCHElh..
2. UNLESS OTHERWI$E SPECifiED
THE TOLERANCE 'ON ALL
DIMI:N$lONS is l:.38mm b .015,'1

28

Absolute
Maximum Ratings
[~'-

Recommended
Operating Conditions

I'aramet.r

Storage Temperature

Supply Voltage
Mode,Select or
Oata Input Voltage

Electrical/Optical Characteristics ooe to 70 e Unless Otherwise Specified
D

Parameter

Hish Level
Input Current

Low Level
Input Current
Supply
Current

Mode

Hish L.evel
Optical
Flux

f

Coupling

Loss

from area mismatch
from numerical aperture,
mismatch

Peak EmiSSion Wavelength

Dynamic Characteristics

ODe to 70 De Unless Otherwise Specified

Parameter
High-to-Low Data Input'

Propagation
Delay

Voltage Step
L.ow·to-Hlgh Data Input

Voltage Step
Refresh Pulse
r-D_u-,"'_t_io_n_--:_r-'-"'-",+";_-I-_-I-_i-~,,:\:
Internally·Coded Mode
Repetition Sate

29

+5V~~~---------------'
MODE SELECT
DATA INPUT

DATA INPUT

OPTICAL OUTPUT

WITH
MODE SELECT LOW

OPTICAL OUTPUT
WITH
MODE SELECT HIGH

~~~~________________________~jrl________~2:5%~~~~==~~~~~~~~~~. t
Figure 1. Flux Coding and Timing Diagram.

4

r -------------- - - - - - - - ---,

:

vcc--~~----~------~----------~

I

,I

MODE SELECT -~-t------I----J
OPTICAL
SIGNAL
GENERATOR,

I
DATA INPUT

__
__

-'--

OPTICAL
PORT

-.I

I
_-...::5~1____

r

I
I

I
I
I

GROUNO--...::3~1------~-----------------J

----..I

Figure 2. Schematic Diagram.

~~::;;;;,..,":"iI'.,...;;r,I'TI-'I-r,',O ~

-+--ji--'--l--+~--l--Jr.~1--+--l.8

"

"2~1-~I~i-r...,10-,c~~I~~1

z

; ~

.

'"
" zw
-+-jh-+--+-j-4+--+-1--+-I.6 ~ ~
~

,0

1--+i--"i' '-I--+I-.J.H-.=-:C'~L,-:L
',i I
I
~!!"c·I.1
I
i I

.8H--l--l.-·4i/-Hl-+-~+,i'-,'1-'"•.1-.--1,

T

z -'

0"
-+--iH-l--+..,L-j--l-\+-I--+--l.4 .,

'~

P

-+---+-.I-+-+---+-+\-+-+--l.2

80·

90'1----+--+--1--_-+~

~
640

e-

OFF-AXIS ANGLE - DEGREES

660

680

700

720

740

760

A - WAVELENGTH - nm

Figure 4. Emission Spectrum.

Figure 3. Radiation Paltern.·

*The optical fiber is recessed within the barrel at a distance of approximately 7mm. Solid line represents radiation pattern from fiber
stub without obscuration by connector barrel. Dashed line represents radiation pattern as seen from outside of connector.

Notes (cont'd):
3. Measured at a point 2mm (.079 in.) from where lead enters
package.
4. A supply decoupling network of 2.2!£H with 60!£F is
recommended.
5. Average currents for steady-state conditions at Data Input.
6. For typical values. Vee = 5.00V and TA = 25'C.
7. Flux excursion ratio. k. is the ratio of flux excursion above mid
level to flux excursion below mid level.
. the
average flux is (d + L!.

30

Electrical Description

1. Steady state turn-on of the photo-emitter at maximum flux
level (e.g., for system diagnosis).

The HFBR-1001 has two modes of operation: Intemally-Coded
mode and Externally-Coded mode. These are selected by
making the Mode Select input "low" for Internally-Coded mode
and "high" for Externally-Coded mode. With Mode Select
"low," the optical signal generator in the HFBR-1001 produces
a "mid-level" flux which has positive or negative excursions,
depending on whether Data Input is "high" or "low." In this
Internally-Coded mode, a train of positive excursions is initiated when Data Input goes "high;" when Data Input goes
"low," a train of negative excursions is initiated. These excursions are pulses of approximately SOns duration with a
300kHz repetition rate. Each initiation of a pulse train starts
with a full-H, or «I>L. Direct analog operation is not
possible due to hysteresis in the response of the optical
signal to the Data Input signal.

Mechanical and
Thermal Considerations
Typical power consumption is less than 500mW so the transmitter can be mounted without consideration for external heat
sinking. The optical port is an optical fiber stub centered in a
metallic ferrule. This ferrule supports a split-wall cylindrical
spring sleeve which aligns the ferrule in the Transmitter with
the ferrule in the HFBR-3000 Fiber OptiC Cable/Connector.
The connection procedure is to FIRST start the Connector
ferrule into the sleeve; THEN screw the coupling ring on the
barrel. The barrel performs no alignment function; its
purpose is to hold the ferrule faces together when the
coupling ring is tightened as specified in the HFBR-3000
Fiber OptiC Cable/Connector data sheet.
The HFBR-1001 should be mounted so that the lock nut at the
optical port is not disturbed. Moving the lock nut can cause
misalignment of the optical fiber stub inside the module resulting in a reduction of power output. Mounting at the edge of a
printed circuit board with the lock nut overhanging the edge is
recommended.

With Mode Select "high," the optical signal is at full maximum
(-2 X mid level) when Data Input is "high," and nearly zero
when Data Input is "low." This mode provides for these three
applications:

31

TECHNICAL DATA

MARCH 1980

Features
• LONG DISTANCE TRANSMISSION:
1000 METRES"
• PIN COMPATIBLE WITH HFBR-1001
TRANSMITTER
• HIGH SPEED: DC TO 10 Mbaud"
• NO DATA ENCODING REQUIRED"
• FUNCTIONAL LINK MONITORING"
• TTL INPUT LEVELS
• BUILT-IN OPTICAL CONNECTOR
• LOW PROFILE: PCB MOUNTABLE
• SINGLE +5V SUPPLY
·When used with HFBR-2001 Receiver Module and any HewlettPackard HFBR-3000 Series Cable/Connector Assembly.

Description
The HFBR-l002 fiber optic transmitter is an integrated electrical to optical transducer designed for digital data
transmission over single optical fiber channels. A bipolar integrated circuit and a high efficiency GaAIAs LED convert
TTL level inputs to optical pulses at data rates from dc to 10 Mbaud (see note 5). An integral optical connector on the
module allows easy interfacing without problems of fiber alignment. The low profile rugged industrial package is
designed for direct circuit board mounting without additional heat sinking on printed circuit boards with 12.7 mm (0.5")
card rack spacing.
The HFBR-l002 is intended for use with Hewlett-Packard fiber optic cable/connector assemblies, and the HFBR-2001
fiber optic receiver for transmission distances to 1000 metres. It is a direct replacement for extending links currently using
the HFBR-l00l (100 metre) transmitter to give 1000 metre capability. The HFBR-l002 generates optical signals in either
of two externally selectable modes. True dc response (data high or low for arbitrary time interval) is available when using
the Internally-Coded mode.
WARNING: OBSERVING THE TRANSMITTER OUTPUT FLUX UNDER MAGNIFICATION MAY CAUSE INJURY TO
THE EYE. When viewed with the unaided eye, the near IR output flux is radiologically safe; however, when viewed under
magnification, precaution should be taken to avoid exceeding the limits recommended in ANSI ZI36.1-1976.

package Dimensions
CAutlOlll,
1. lOCK NUT .0,1;0 SARRRSHOOlO

NOT BE OISTU RilED.
1. SCREWS £NTEAING tHE 2$
THREADED MOUNTING HOLES
MUST NOT TOUCH BOTTOM.. .
3. THE CONNECTOR SHOULD NOT'SE
TIGHTENEIl BEYONO THE LIMITS
speClfl£OINTHE HEWUTTPACKARD CABL£! CONNECTOR
PATA SHEET (1INGERT1GtlT!.

PIN

32

MODE SELECT

4

vee

5

DATA INPUT

N.C.
GROUND

NOTES:
1. DIMENSIONS IN rom (lNCHESI .
UNLESS OTHERWISE SPECIFIall
THE TOLERANCE ON ALL
DIMENSIONS IS '.$8mm ("OIS",

2.

. MOUNTING HOLEUPLCS.·

FUNCTION

1
2
3

Absolute
Maximum Ratings

[

Recommended
Operating Conditions

Symbol Min Max Units Note

Parameter
Storage Temperature

TS

Operating Temperature

TA

-55 +85
o +70

Temperature

Lead Soldering

°c '

10

Time

Supply Voltage

VCC

Mode Select or
Data Input Voltage

VI

6

V

-0.5 5,5

V

-0.5

SUpplyVo~,:Y/:/;'''\':;;:'

't:

260 'C

Optical
Flux

Symbol

Transmitter (~~)
Output
:2

4rr

High Level

~ ~
~'~~,i~: ::~~;::'~"'. ~:,
~W
dIiIm
/lW;

50
100
t-;;i-.....

205'

5

••

105
0.8

k

"1.oW :',

1.2,

N.A.

,0,3

Dc

100

ar.c

3.0

ApK

820

'McldeS"':::,

-'
,','.

pm

"

"','

'\,',:', "

'IH

IlL

Externally-Coded
Supply
Current

Mode
ICC
Intllrnally-Coded

Mode

Dynamic Characteristics

40
68

95

Doe to 7Doe Unless Otherwise Specified

Parameter

Propagation
Delay

33

,D8\1i;~'$quare, ,,'

'W_at:500k,&)',
, ~

',:

;,

3

MODE

SEL~~6.

~

,....-------.,

GND _ _3_
H6::I~~~2
Vee _ _4_
TRANSMITiER
DATA INPUT _ _5_ ..._ _ _ _ _ _ _...

DATA INPUl

OPTICAL OUTPUT
WITH
MODE SELECT LOW

OPTICAL OUTPUT
WITH
MODE SELECT HIGH

Figure 1. Flux Coding and Timing Diagram.
Vee

4

DATA
INPUT

MODE
SELECT

OPTICAL
PORT

Figure 2. Schematic Diagram.

;-' f-

i

J:

-'

a"
f~

i
,

Z

"x
"

X
::>

i

"

a:
~
ll;

\1
/

11
IL if /

0,6

I V .(

.4

I-

o~

;;;1"
" -

760

'/ V

~ ./
780

I
:voe

\\ 1\
\

i

1\

I

--

1\\ \

\i\'

I

I
800

l -I--

~I

"

J

0.2

J1

,,~~c

1

E'l f
~ ;

oc

f

I

0.8

'r-r~

1 !

1.0

X

u. W
0 fw ~
z -'
0

OFF-AXIS ANGLE - DEGREES

1.2

o

a:

" in

o-

GROUND

~

w
-'

"z
1

80'

-=-

i\:

I

820

840

'"

860

~
880

A - WAVELENGTH - nm

Figure 3. Radialion Pattern.*

Figure 4. Emission Spectrum.

'The optical fiber is recessed within the barrel at a distance of approximately 7mm. Solid line represents radiation pattern from fiberstub
without obscuration by connector barrel. Dashed line represents radiation pattern as seen from outside of connector.
8. The transmitter output, ¢T, equals the flux excursion,
tl¢ =(¢H ~ ¢U/2. Notice that under the conditions specified
for tl¢, the ilverage flux is (¢H + ¢U/2.
9. Flux excursion ratio, k, is the ratio of flux excursion above mid
level to flux excursion below mid level.

Notes (cont'd):
3. Measured at a point 2mm (.079 in.) from where lead enters
package.
4. A supply decoupling network of 2.2}.!H with 60}.!Fis
recommended.
5. With NRZ data, 10 Mbaud corresponds to a data rate of 10
Mbits/second. With other codes, the data rate is the baud rate
divided by the number of code intervals per bit interval. Selfclocking code (e.g., Manchester! usually has two code
intervals per bit interval giving 5 Mbits/second at 10 Mbaud.
6. With Hewlett-Packard HFBR-2001 and HFBR-3000 Series
Cable/Connector Assembly.
7. For typical values, Vee = 5.00V and TA = 25°C.

k

= ¢H - ¢M
M - L

10. Average currents for steady-state conditions at Data Input.
11. The refresh pulse is interrupted (abbreviated, if Data Input
changes state during the refresh pulse. MAX propagation
delay is for Data Input changing state during the maximum
excursion of the refresh pulse.

34

[

Electrical Description

-

1. Steady state turn-on of the photo-emitter at maximum
flux level (e.g., for system diagnosis).

The HFBR-1002 has two modes of operation: InternallyCoded mode and Externally-Coded mode. These are
selected by making the Mode Select input "low" for
Internally-Coded mode and "high" for Externally-Coded
mode. With Mode Select "low," the optical signal
generator in the HFBR-1002 produces a "mid-level" flux
which has positive or negative excursions, depending on
whether Data Input is "high" or "low". In this InternallyCoded mode, a train of positive excursions is initiated when
Data Input goes "high;" when Data Input goes "low," a
train of negative excursions is initiated. These excursions
are pulses of approximately 40ns duration with a 300kHz
repetition rate. Each initiation of a pulse train starts with a
full-duration pulse, but when Data Input changes state,
the train is terminated - even at mid-pulse - as a new
train of opposite-polarity pulses is initiated. With this
coding scheme and the low duty factor, the average flux is
always near the mid-level, regardless of the data rate or
duration in either state. This coding scheme, which is
transparent to the user, is designed to operate the HFBR2001 Fiber Optic Receiver most effectively; the mid-level
flux operates the Receiver'S dc-restorer and the "refresh"
pulses of either polarity keep the Receiver'S ALC voltage
at the proper level, providing data format independence
(no data encoding required) over the data rate range of dc
to 10Mbaud. The Internally-Coded mode permits transmission of analog information, e.g., by means of Pulse
Width Modulation. Another advantage of the 3-level
Internally-Coded mode is that supply current is nearly the
same for either logic state, thus reducing transients on the
power supply line.

2. Stand-by mode (e.g., when the system is not in use).
3. Transmission of 2-level optical signals from externally
generated code (e.g., Manchester) for receivers not
configured for the 3-level code. With Mode Select
"high," the output is either 

Absolute Maximum Ratings
Pat.m..-r

[

Symbol

Min

Storage Temperatur.

TS

-55

Operatfng Temperature

TA

0

Lud ~1!lerln9

CVC!;, .

.Temperatur.
Time

SupPly Volt• .

Vee

OutputV~ttl!ll' IMl9h State)

VOH

Recommended Operating Conditions

Electrical/Optical Characteristics

O°C to 70°C Unless Otherwise Specified

High
Output

Voltage

37

DATA INPUT TO TRANSMITTER IHFBR-1001, INTERNALLY CODED) OMITTING TRANSMISSION DELAY

(I
3-LEVEL CODED FLUX AT RECEIVER INPUT

"5V~

____

~PLH

k = (.w~II(~-.L)

_ _ _ _ _ _ _\ _ ..

~H~

___

---,~?f~~f~f!SF
C~ ~ _':" ~ :~RC~~L_<5~' __ ~

DATA INPUT TO TRANSMITTER, E.G. MANCHESTER (HFBR-'OOl EXTERNALLY CODED) OMITTING TRANSMISSION DELAY

2-LEVEL CODED FLUX AT RECEIVER INPUT

Figure 1. Optical Input Timing Requirements.

Notes (confd):
3. Measured at a point 2mm (.079") from where the lead enters
the package.
4. If ripple exceeds the specified IimH, the regulator shown in
Figure 5 should be used. the LC filter shown in Fl9l.1re 5 Is
recommended whether the regulator is used or not.
5. For typical values, VCC = 5.00V and TA = 25·C.
6. Flux is averaged over an interval of at least 501£S. Flux values
specified are for the equivalent of a monochromatic source
between 700nm and 820nm.
7. For eHher 2-level or 3-level code, k= (4)H-4>M)I(M-4>Ll.
8. For the HFBR-2001, a 3-L.svel Code Is defined as having a
mid-level, with equal-amplitude and pulse width excursions to
high-level or to Iow-Ievel.
9. Link Monitor prOVIdes a check of link continuity. A low Link
Monitor output indicates that the optical signal path has been
interrupted. For example, it might indicate a broken cable or
a loose, dirty, or damaged connector. The link may still be
operational with Link Monitor low, but It should be checked
to determine the cause of the low indication. When the
source of ftux is an Internally-Coded HFBR-l001l1002 Fiber
Optic Transmitter, Link Monitor high will be a valid indication
of link continuity whether or not data is being transmitted. An
optical input with excursions (AM)
where Ip = 'average photodiode photocurrent
.
R4> = 0.4A1V\( = photodiode responsivity
4>M = average flux being received
1.1. Measured from the time at which opticel input crosses the 25%
level until DATA OUTPUT = 1.5V In HL transHion.
12. Measured from the time at which optical input crosses the 75%
level until DATA OUTPUT = 1.5V in LH transition.

.

r------------

'

vee

I

I
I

-L
OPTICAL -....
PORT
--

I
I

+-_+-----'-1-'-5 DATA
I
I

I

I
1

OUTPUT

r-+--~"';" TEST

'--"'VII'v-+--+---...,r-'

I
I

I

POINT

L......._ _ __
-4_--4_....j...;;3 GROUND
L ________
-

--....I

Figure 2. SchematiC Diagram.

13. Measured from the time at which optical input fluctuation begins
until LINK MONITOR riseS to 1.5V.
14. Measured from the time at which optical input fluctuation ceases
until LINK MONITOR falls to 1.5V.
15. With NRZ date, 10Mbeud corresponds to a date rate of .
10Mb/s. With other codes, the data rate is the baud rate divided
by the number of code intervals per bH interval-self-clocklng
code (e.g., Manchester) usually has two code intervals per
bit interval giving 5Mb/s at 10Mbaud.

38

Electrical Description

ity of excursion is the greater. If these excursions are too far
from being balanced, the gain limitation imposed by the larger
excursion may cause the smaller (opposite polarity) excursion
to be too small to operate the flip-flop.

Flux enters the HFBR-2001 via an optical fiber stub where a
PIN photodiode converts it to a photocurrent. This photocurrent goes to an I-V (current-to-voltage) amplifier which utilizes
both dc feedback and ALC (automatic level control).

The Link Monitor output is driven by an amplifier which responds to the ALC voltage. The Link Monitor is high when the
flux excursions are greater than or equal to O.8Jl.W.

The function of dc feedback is to keep the average value of
the signal centered in the linear range of the amplifier. The dc
feedback amplifier has a high impedance output to establish
a long time constant on a capacitor at its output. (The voltage
on the capacitor is observable at the test point). As seen in
the schematic diagram, the voltage on this capacitor extracts
the average component of photocurrent from the input of the
I-V amplifier so its average output is at a fixed level. Optical
flux excursions above and below the average cause voltage
excursion above and below the fixed level at the output of the
I-V amplifier.

Mechanical and Thermal
Considerations
Typical power consumption is less than 500mW so the Receiver
can be mounted without consideration for additional heat
sinking. The optical port is an optical fiber stub centered in a
metallic ferrule. This ferrule supports a split-wall cylindrical
spring sleeve which aligns the ferrule in the Receiver with the
ferrule in the HFBR-3000 Fiber Optic Cable/Connector. The
connection procedure is to FIRST start the Connector ferrule
into the sleeve, THEN screw the coupling ring on the barrel.
The barrel performs no alignment function; its purpose is to
hold the ferrule faces together when the coupling ring is
tightened as specified in the HFBR-3000 Fiber Optic
Cable/Connector data sheet.

The voltage excursions operate a flip-flop whose output drives
the Data Output amplifier; an excursion above the average
level sets the data output high, where it remains until an
excursion below the average level resets the flip-flop.
To prevent overdrive, an ALC circuit, responding to excursions
either above or below the average level, controls the gain of
the I-V amplifier. Gain is then determined by whichever polar-

0°

() - OFF-AXIS ANGLE - DEGREES

Figure 3. Reception Pattern.·
*The optical fiber is recessed within the barrel at a distance of approximately 7mm. Solid line represents reception pattern atfiberstub
without obscuration by connector barrel. Dashed line represents reception pattern as seen from outside of connector.

1.0

iJl
z
0

~a:
w

>

.8

.6

i=

~

a:

.4

I

,2
.2

-:r

,--

=i;~
'I

REGULATOR
7SQ6COR
EOUIVALENT'

_L

i--"

i"
\

f-

1\

\

I

.J
I

i

-+~

400

500

L

600

+8V

TO

\

T

2.2.u.H
i<1nJ

r--l4

60/1;

+

+12V

SUPPLY

HFBR·

2001
60llF

O.331lF

I
700

800

900

1000

1

x - WAVELENGTH - nm

3

*CRITICAL PARAMETER IS SPEED OF RESPONSE

Figure 4. Spectral Response.

Figure 5. Power Supply Transient Filter Recommendation.

39

FIBER OPTIC
SINGLE CHANNEL
CABLE/CONNECTOR
ASSEMBLIES

HFBR-300D

TECHNICAL DATA

MARCH 1980

Features
• USER SPECIFIED CABLE LENGTHS
• CONNECTORS FACTORY INSTALLED
AND TESTED
• PERFORMANCE GUARANTEED OVER
TEMPERATURE AND HUMIDITY
• HIGH STRENGTH
• LIGHT WEIGHT
• SMALL BEND RADIUS

Description
The HFBR-3000 Simplex Fiber Optic Cable/Connector
Assemblies are intended for use with the HFBR-1001/-1002
Transmitters and HFBR-2001 Receiver for digital data
transmission. The Connectors mate directly with the
optical ports on the Transmitters and Receiver. The cable
uses a single fused silica, partially graded index, glassclad fiber surrounded by silicone coating, buffer jacket,
and tensile strength members. This combination is then
covered by a scuff-resistant outer jacket. The cable
resistance to mechanical abuse, safety in flammable
environments, and inherent absence of electromagnetic
interference effects may make the use of conduit
unnecessary. However, the light weight and high strength
of these assemblies allows them to be drawn through most
electrical conduits. The HFBR-3099 Adapter, for interconnecting cables, consists of two parts: a sleeve to align
the ferrules and barrel to join the connector couplings.

POLYURETHANE OUTER JACKET

OPTICAL FIBER

Cable/Connector Ordering Guide
HFBR-3000 defines an optical cable of user specified
length supplied with factory installed and tested
connectors. Length must be specified in metres and'can
be anyone metre increment from 1 to 1000 metres. Length
information is shown as option 001 to the base product
number with quantity equal to the number of cable
assemblies ordered.
Examples:
For a single length of 245 metres specify:
HFBR-3000
Optic Cable Assy
Quantity
Option 001
245 metres long
Quantity
For seven lengths of 1000 metres specify:
HFBR-3000
Optic Cable Assy
Quantity
Option 001
1000 metres long
Quantity

HFBR-3000 CABLE LENGTH TOLERANCE
Cable Length (Metres)

1-10
11-100
> 100

Tolerance

+10
-0
+ 1
-0
+ 1
-0

{

STRENGTH MEMBERS
BUFFER JACKET
81 LICON E COATI NG
CLADDING (SILICA)
CORE (SILlCA)----.;~<"'~y;;:jC.J

Units
%
Metre

1
1
7
7

Systems intended to operate at distances greater than
1000 metres may require special component selection,
depending upon operating conditions. For cable lengths
greater than 1000 metres contact your local HewlettPackard sales office.

%

Mechanical Dimensions

HFBR·3099 ADAPTER
CAUTiON,
A. COUPLING SHOULD NOT
BE OVERTIGHTENED, SEE
MEC-HANICAL/OPTICAl
CHARACTERISTICS AND
NOTE 14.
B. GOOD SYSTEM PE.RFOR·

3.00
10.32 UNf THO.

~L ·J

40

~81

-fl=JI '

7,11

2+44

12801

1.0961

t

I<'--

MANCE REOUIRES CLEAN
FERRULE FACES TO

AVOfD OBST~UCTIN(j
THE OPTICAL P-ATH.

CLEAN COMPRESSED AIR
OFTEN IS SUFfiCIENT TO
REMOVE PARTICLES. A

COTTON SWAB SOAK ED
Jf-.J METHANOL OR

FREON"" MAY ALSO
SE USED.

Absolute Maximum Ratings

o
Mechanical/Optical Characteristics

0° C to

+7QO C Unless Otherwise Specified

9. Typical values are at TA = 25°C.
10. This applies for short term testing, less than one hour.

Notes! cont'd i:
4. 1800 bending at minimum bend radius, with 10N tensile load.
5. Force applied on 2.5 mm diameter mandrel laid across the cable on a
flat surface, for 100 hours, followed by flexure test.
6. For mass m dropped from height h on 25 mm diameter mandrel laid
across the cable on a flat surface.
7. Exit N.A. is defined as the sine of the angle at which the off·axis radiant
intensity is 10% of the axial radiant intensity.
8. Fiber 3dB Bandwidth. Length, (MHz. kmJ is defined as 3S0/fiber
dispersion {ns/km I.

11. Fiber loss exclusive of connector loss.
12. This applies to cable only.
13. When using HFBR-1002 transmitter with HFBR-3000 Cable/
Connector Assembly, Total Insertion Loss, aT;' O'F + ao (Q- 300) for
Q> 300 m; for lengths Q,; 300 m, ar = aF.
""""iOOO
14. Coupling Ring "Finger Tight", torque 0.05 < L < 0.1 N.m.
Overtightening may cause excessive fiber misalignment or permanent
damage.

20

I.
12

"I','["
w

~

"z >
"~ >":;;:z: :;>0;

08 w

.0'

~

z 5
x
i!
x

8
80

;:

"

~

~I~
WAVELENGTH (nm)

1/ - OFF·AXIS ANGLE - DEGREES

Figure 1. Optical Fiber Output Radiation Pattern.

Figure 2. Spectral Transmission.

OINlli

The actual fiber dispersion is determined from the RMS Pulse Spreading and can be approximated by:

-

tPl

100% - - -

50%--

-

-

____..J) :::::
DISPERSION "" ,/tP2 2 - tp,2

Q

IMPULSE: tPl < 3.5ns

Figure 3. Fiber Dispersion

41

OOUT

'

.. ~ ,~

,. ..

.: ..:

.42:

High Speed Optocouplers
Typical .Current Specified
Data Rata Transl'l!r Input
(NRZ)
Ratio
Current
1M bitls 7% Min.

Withstand
Test
Voltage

6N136

19% Min.

16mA

3000Vdc[3]

HCPL-2502

15-22%[2]

Device

Description
6N135

Ii~ if;-~I!lVct
~ v.

AIIIDE

CATIIIDE~

~v.

B

Transistor 0 utput

Applicetion[1]
Line Receiver, Analog
Circuits, TIl/CMOS,
TIL/LSTIL Ground
Isolation

Page
No.
46

c

t!JGMI

-

-'~~

CATHODE, 2 "

7 VOl

CATHDDEz 3

6

,,

ANODE z 4

v.

HCPL-2530

Dual Channel
Transistor Output

HCPL-2531

Line Receiver, Analog
Circuits, TIL/CMOS,
TIL/LSTIL Ground
Isolation

1M bitls

16mA

3000Vdc[3]

50

7% Min.
19% Min.

5 GNU

[3

ANODE 2
CATHODE

.'

6N137

Optically Coupled
Logic Gate

Line Receiver, High
Speed Log ic Gro und
Isolation

10M Bitls 700% Typ 5.OmA

3000Vdc[3]

54

HCPL-2601

High Common Mode
Rejection, Optically
Coupled Logic Gate

Line Receiver, High
Speed Logic Ground
Isolation In High
Ground or Induced
Noise Environments

10M bitls 700% Typ

3000Vdc!3]

58

HCPL-2602

Optically Coupled
Line Receiver

Replace Conventional
Line Receivers In High
Ground or Induced
Noise Environments

10M bitls 700% Typ. 5.OmA

3000Vdc[3] 62

HCPL-2630

Dual Channel
Optically Coupled
Gate

Line Receiver, High
Speed Logic Ground
Isolation

10M bitls 700% Typ. 5.0mA

3000Vdc!3] 68

Typical
Current Specified
Input
Data Rate Transfer
(NRZ)
Ratio
Current
300k bitls 300% Min. 1.6mA

Withstand
Page
Test
No.
Voltage
3000Vdcl3] 72

v,
vour

7

GNU

[!

.....---

vcc;Il

ANODE~ j ~.ro:; ~v,

r

CATHODE£!

~VoUT

'---aNo!J

[!

II

Vee

+INo{!

~r~
r~

-INi!

-I!

f!I

~VE
~.VOUT

t!J

3'"I>- Il11'1"
CATHOD.,II
II v..
3,1>ANOO.,!!
GIIII
AIIIDE,[I

CATHODE,[!

Vee

5.OmA

II

High Gain Optocouplers
Device
6N138

~v.
~l~"

AIIIIOE~~1

CATHOOE~

'-"m~
2

Application[ 1]

Low Saturation
Voltage, High Gain
Output, VCc=7VMax.

Line Rece iver .. Low
Current Ground
Isolation, TILmL,
LSTTLmL, CMOSI
TIL
Lille Receiver, Ultra
Low Current Gro und
Isolation, CMOS/LSTIL
CMOSITTL, CMOSI
CMOS

..

~

Low Saturation
Voltage, High Gain
Output, Vcc=18V
Max.

HCPL-2730

Dual Channel, High
Gain, Vcc=7V Max.
II Voz
HCPL-2731. . Dual Channel, High
1'---- .. Gain, Vcc=18V Max.
& GND
7 V01

_·s·
~

3

ANODEz 4

CATHODE

Description

---.

~VD

~GNIl.

B

~~.

z"

5 Vo

3

4 GND

4N45

Darlington 0 utput
Vcc=7V Max.

~

Darlington Output
Vcc=20V Max.

400% Min.

0.5mA

Line Receiver, Polari~ 300k bitls 300% Min. 1.6mA
Sansing, Low Current
Ground Isolation
400%Min. 0.5mA

3000Vdc[3]

76

250% Min. 1.0mA

3000Vdc!3]

80

AC Isolation, Relay·
Logic Isolation

3k bitls

350% Min. 0.5mA

44

L

AC/OC to Logic Interface Optocoupler
Description

Davin

[

Application 111

Input
Typical
Threshold
Data Rates Current

l-y--""-,

'"

..

HCPL-370D] ACIDC to Logic
-- ~-- ....~/ ' Threshold Sensing
Interface Optocoupler

0

~-.--,-.~

v('(

01, a v

Limit Switch
Sensing, Low Voltage
Detector, Relay
Contact Monitor

4 KHz

2_5mATH+
1.3mA TH-

Typical
Data Rate
(NRZ)

Current
Transfer
Ratio

Withstand
Test
Voltage

Output
Current
4_2mA

Page
No.

3000Vdcl31 84

Hermetic Optocouplers
Device

Description

6N134

-'~.
. "
~

~ Va:

I.

:I

IlATtlDDlrl
AlODEtl
7

......:

"VaI

ANODEt Z

I.VoI

'MI

•

•

·~r

I r ,a

3~~

4

r

,

:::::::

14
13

• :zs;:-;::::

12

I
7

"
II

~.;_

6N134

II
11

;..or

I_'

Dual Channel
Hermetically Sealed
Optically Coupled
Logic Gate.
TXV - Screened
TXVB - Screened
with Group B
Data

Application(1)
Line Receiver,
Ground Isolation for
High Reliability
Systems

Specified
Input
Current

Withstand
Test
Voltage

Page
No.

10M bitls 400% Typ_

lOrnA

1500Vdc

90

300% Min.

D.5mA

1500Vdc

94

1500Vdc

98

6N134TXVB

Hermetically Sealed
Package Containing
4 Low Input Current,
High Gain Optocouplers
6N140TXV TXV - Hi-Rei
Screened
TXVB - Hi-Rei
6N140TXVB Screened with
Ve( 'y,V
Group, B Data

(6N~~~

Line Receiver, Low
Power Ground
Isolation for High
Reliability Systems

300k bitls

"

/-.~

'~.

2
3,
4

II

I

14
13
12

•

'II

7,

II

I

Notes:

•

;'.~~

Oual Channel
Hermetically Sealed
Analog Optical
Coupler
4N55TXV TXV - Hi-Rei
?
Screened
Vee <~OV
TXVB - Hi-Rei
4N55TXVB Screened with
Group B Data

Line Receiver,
Analog Signal
Ground Isolation,
Switching Power
Supply Feedback
Element

700k bitls

7% Min.

16mA

AN 948, AN 951-1, and AN 951-2 are located in Application Notes Section, beginning on page 311_ For further
information ask for AN 939 and AN 947.
2. The HCPL-2502 Current Transfer Ratio Specification is guaranteed to be 15% minimum and 22% maximum.
3. Recognized under the Component Recognition Program of Underwriters Laboratories Inc. (File No. E5536l1,
220 VAC working voltage. This is guaranteed by 8 3000 Vdc withstand voltage test for 5 seconds.
1;

45

rh~

~V!..

HIGH SPEED
OPTOCOUPlERS

HEWLETT
PACKARD

6N135
6N136

HCPl-2502

TECHNICAL DATA MARCH 1980
OUTLINE DRAWING'

SCHEMATIC

illl..!lW

0.33{.Q131

~
2
ANODE

OIMEN$IONS~ IN MIL~JMETRE;$ AND (INCHES)

CATHODE

I,

?

8

vee

~---=-="--#-'

~------'

10

va

3

5
GND

Features

Applications

• HIGH SPEED: 1 Mbltls
• TTL COMPATIBLE
• RECOGNIZED UNDER THE COMPONENT
PROGRAM OF UNDERWRITERS
LABORATORIES, INC. (FILE NO. E55361)
• HIGH COMMON MODE TRANSIENT IMMUNITY:
1000V/j.lS
• 3000 Vdc WITHSTAND TEST VOLTAGE
• 2 MHz BANDWIDTH
• OPEN COLLECTOR OUTPUT

•
•
•

•
•

Description

Line Receivers - High common mdde transient immunity
(>1 OOOV Ills) and low input-output capacitance (O_6pF).
High Speed Logic Ground Isolation - TTL/TTL, TTL!
LTTL, TTL/CMOS, TTL/LSTTL
Replace Slow Phototransistor Isolators - Pins 2-7 of the
6N135/6 series conform to pins 1-6 of 6 pin phototransistor
couplers. Pin 8 can be tied to any available bias voltage of
1.5V to 15V for high speed operation.
Replace Pulse Transformers - Save board space and weight.
Analog Signal Ground Isolation - I ntegrated photon detector provides improved linearity over phototransistor type_

Absolute Maximum Ratings'

These diode-transistor optocouplers use a light emitting
diode and an integrated photon detector to provide 3000V dc
electrical insulation between input and output. Separate
con nection for the photodiode bias and output transistor
collector improve the speed up to a hundred times that of a
conventional photo-transistor coupler by reducing the basecollector capacitance.

Storage Temperature .. _ ... __ ....... -55°C to +125°C
Operating Temperature ............... _55°C to 100°C
Lead Solder Temperature. . . . . . . . . . . .
260°C for lOS
(1.6mm below seating plane)
Average Input Current - IF ................ 25mA[1]
Peak Input Current - IF ................... 50mA[2]
(50% duty cycle, 1 ms pulse width)
Peak Transient Input Current - IF .............. 1.0A
(';;l/ls pulse width, 300pps)
Reverse Input Voltage - VR (Pin 3-2) . . . . . . . . . . . .. 5V
Input Power Dissipation . . . . . . . . . . . . . . . . .. 45mW[3]
Average Output Current - 10 (Pin 6) ............ 8mA
Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . 16mA
Emitter-Base Reverse Voltage (Pin 5-7). . . . . . . . . . . .. 5V
Supply and Output Voltage - Vee (pin 8-5), Vo (pin 6-5)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 15V
Base Current - 18 (Pin 7) . . . . . . . . . . . . . . . . . . . . 5mA
Output Power Dissipation ................. 100mW[4]

The 6N135 is suitable for use in TTL/CMOS, TTL/LSTTL or
wide bandwidth analog appl ications. Cu rrent transfer ratio
(CTR) for the 6N135 is 7% minimum at IF = 16 mAo
The 6N136 is suitable for high speed TTL/TTL applications. A
standard 16 mA TTL sink current through the input LED will
provide enough output current for 1 TTL load and a 5.6 kO
pull-up resistor. CTR of the 6N136 is 19% minimum at IF =
16 mAo
The HCPL-2502 is suitable for use in applications where
matched or known CTR is desired. CTR is 15 to 22% at IF =
16 mAo
'JEDEC Registered Data. (The HCPL-2502 is not registered.)

See notes, following page.

46

Electrical specifications
Over recommended temperature (TA = O°C to 70°C) unless otherwise specified.
Parameter

,.-'.

81m.

Devic.

Min,

6Nt36

7

Typ.*"

6N136 ,,' 19
HCPL·2S02 '15,,>"
6111135., 5
CTR .• '
SN1S6
15

CTR'
-

Current Tl'ai'lsfer Ratio

Logic Low
Output Voltll9&

VoL

i

%

6111.136

""""

'J(,',

"'e'

%

tj.':;'6m.A, \,0·

•• 'll>

0.4

V

0.4

V

HCPl-2502

,

500

,

0.1

,
"

lOR
Logic Low
Supply Currant

.

"

Logic High
Supply Current
Input Forward Voftllge
Temperature Coefficient
of Forward Voltage
Input Reverse
Bre,ak down Vof tage
Input Capacitance
Input~utpUt 1n$Ulation
Leakage Current
ReSistance
(Input-Output)
Capacitance
(lnpUt~utpud

Transistor DC
Current Gain

'CCL

40

'ICOH"

0.02

,

.'/IA

2SO

~A

IF" OmA"VO'!'iVCp
"'15V
:"

#A

IF~.1SmA,

/lA

VF·
A.VF
A'fi:

V
mVfC,

~1.6

5

.6

,

'

Vo "'Op~n,Vc;C= 15~
'.'

IF" OmA,VO " Open, Vec'" 15V

:2

1,2

,"

'IF "OmA,VO·-Open, VCC:-'l5V
TA" 25·0.: . ','
".,.'

1.7

Note

"

#A

lCOH

FI9.

',,'~'

,>'0'""";,,,,.",

"

Ui

,'"

,,",

100

,""",

'

I

IF.~' 16f11.A"O"'~4fI1~.VCC"4,6V,

IF "OmA,VO =VCC",1.6V
TA,,:m·C,' ,',
"

e,

""'.

.' .. , ,,:,.'
O.5V,v~c=4.6V

tF·.. OrtiA;VO~'VCC"6.5V, '.
nA ":," TA"25"p
.., . . ,
",

loti-

Logie High
OutpUt Currant

.

tp-':t6ritA, Iri "';·MrtiA. VCC "4.li1t
",'

,

"

3

'

'F" lSmA,VO = 0.4V ,VCC =4.5"
TA-2!tC,
'

%

13
21
0.1
0.1

.

,':'., Te$t,Condltlons

UnittII'

22

aN13~

",

Max.

18
24

,

3

'F" 1SmA,TA = 25"C
IF= 16mA

"

5

eVR"

50

CIN

1.0

II~*

V

IFi= 1011A. TA =25"0.

pF

f'" tMHz, VF" 0
46% Relative HumidiW. t ~ 5s
VI~ c 3OOOVdc, TA= 25"C

/lA

6

RI~

1012

0

V...o =600Vdc

5

CI~

0.6

pF

t-'MHz

6

hFE

175

Vo =5V,IO:" 3mA

....
•• All typical. at T A = 25°C.

Switching specifications at TA =25°C Vee = 5V, IF = 16mA, unless otherwise specified.

r

~ym.

Parameter'
Propagation Deley
. Time Tu Logic Low
at Outj)ut
Propagation Dellly
Time To logic 'High
at Output

Device

...

6N135

..

Common Mode Tran"entlmmuoiity!!t Logie
Hl9h Level Output

IPHL* 5N135
HCPL·2602
I
6N135
tPLH* 6Nl36
HCPL·2602
aN135

'-,

.,

sient Immunity at Logie.
Low Levet Output,

CMH SNl36
, ....
\:ICPL-2502
,
6N135
.:,
CIViL 6N136
HCPL-2602

Bandwidth

BW

I: CommonModeTran-

'

Typ,

Mm.

.

1'et.tCo!1ditions

Units

0.5

1.5;:

I/.S

0.2

0.8

/IS .... RL. -1.9kO .'; ...... .,. . .....

0.4

1.5

0.3

0.8 ,

";1000'

."

R

.,.9kO

,'.., •..

".

vlJi$

8,9

6,9 I S,9

".
7,8.9

."

VcM,o 10Vo-D,l=Ii; '='4.1 Rn· ..... ..'.

2

Derate linearly above 70°C free-air temperature at a rate of 1.6mArC.
Derate linearly above 70°C free-air temperature at a rate of o.9mWfC,
Derate linearly above 70°C free-air temperature at a rate of 2.Omwfc.
CURRENT TRANSFER RATIO is defined as the ratio of output collector
current, 10, to the forward LED input current, IF. times 100%.
6. Device considered a two-terminal device: Pins 1,2,3, and 4 shorted
together and Pins 5,6. 7, and 8 shorted together.
7. Common mode transient immunity in Logic High level is the maximum
tolerable (positive) dVCM/dt on the leading edge of the common mode

6,9

"·IFaOI!l'«.VC~;':~OV~~~;';',9knJ'0
!' ...... '

-1000

"

Note

"'".'

.;0"'"

~10oo

,. .

Fig.

I'
• VIp,s ···IF.#OmA;VtM;.10VP1);R(;,.;.4;,kO I .....
L

V/#5

1000

NOTES:
1. Derate linearly above 70°C free-air temperature at a rate of O.8rnAfC.

2.
3.
4.
5.

Max,

10

7,8,9

8

10

pulse VCM. to assure that the outPut will remain in a Logic High state
Ii.e., Vo > 2.0V). Common mode transient immunity in Logic Low
level is the maximum tolerable (negative) dVCM/dt on the trailing
edge of the common mode pulse signal, VCM. to assure that the output
will remain in a Logic Low state (i.e., Vo < a.aV).
8. The 1.9kn load represents 1 TTL unit load of 1.6mA and the 5.6kn pull-up resistor.
9. The 4.1 kn load represents 1 LSTTL unit load of a.36mA and 6.1 kn pull-up resistor.
10. The frequency at which the ac output voltage is 3dB below the low frequency asymptote.

'JEDEC Registered Data.

47

10
0

~

II:
II:

w

"

!J;

E
I

l!0:

I-

iii0:

Il-

0:

2

<..>

0:
0:

I,

w

::>

."
I-

::>

I-

iilN

Vee -5V
• 25'C

<..>

TA

"

::;

E

"

0

I

""16mA

Vo #O.4V

:I;

0:

0
Z

10

0.1 0~-------!--------:"O'------',..JOO

20

Vo - OUTPUT VOLTAGE - V

IF - INPUT CURRENT - rnA

Figure 1. DC and Pulsed Transfer Characteristics.

Figure 2. Current Transfer Ratio vs. Input Current.

1.1

_J.

0

;::

10

"a:

0.9

\.'

0.8

<..>

\1

N

::;

"a:

.1

:I;

o. 7

0
2

O.6

-60

VF -

FORWARD VOLTAGE -

16rnA,

vee - MV'

-40

~

0

a:

a

-

10+ 2

~T-.

""

::>

§

500

~

400

.:

--_.:-

10°

<..>

I

§ 10- 1

~

I

.§
-20

20

40

60

80

10-2

---

-50

100

i"

140

/'
.

~

-25

,/

/

V

10+ 1

:I:

-40

120

J

I, -0'
VO-V""bS.oV

10+ 3

I-

-60

100

10-+ 4

a:
a:

600

0
2

.

80

.

>

;;:'"

60

Figure 4. Current Transfer Ratio vs. Temperature.

I

~

40

TA - TEMPERATURE - °C

~

0

20

-20

V

Figure 3. Input Current vs. Forward Voltage.

1, -

-

'\'

"iil

~
1

I

IF "I: 16mA
Vo -0.4V
Vee = 5V
T, I" 25'C

r\.,

0:

~

"ul

1'\,

iii0:

<..>

1-

NO~MALI~eD

II-

1.0

I-

"'

'\

~

2

iii0:
0:

./

"

I-

::>

1.0

.~

E
I

.;"
,(
;

0:

"

_L_16Nl1s
---SNlf6

..........

..}--- ~

"

/'

V

+25

./

+50

+75

+100

TA - TEMPERATURE _ Co

TA -TEMPERATURE-Co

Figure 5. Propagation Delay vs. Temperature.

Figure 6. Logic High Output Current vs. Temperature.

48

ill
I
w

(I)

Z

~a:

o

~
a::

JA - 2$'C, fl •• loon, Vee.- SV

~a:

I-

~a:



TECHNICAL DATA

;'P
-,W

MARCH 1980

SCHEMATIC

~

, . . - _ - - - - . 08 Vee

10,
7
~---6V01

4

_
'F2_

3

'02

...---1_-_.06 V02
5

--+--.oGND

Features

Applications

• HIGH SPEED: 1 Mbltls
• TTL COMPATIBLE
• HIGH COMMON MODE TRANSIENT IMMUNITY:

• Line Receivers - High common mode transient immunity
(>1 OOOV /,(Is) and low input·output capacitance (0.6pF).
• High Speed Logic Ground Isolation - TTLfTTL, TTL/
LTTL, TTL/CMOS, TTL/LSTTL
• Replace Pulse Transformers - Save board space and weight.
• Analog Signal Ground Isolation - Integrated photon de·
tector provides improved linearity over phototransistor type.
• Polarity Sensing.
• Isolated Analog Amplifier - Dual channel packaging enhances thermal tracking.

>1000V/",s
•
•
•
•
•

HIGH DENSITY PACKAGING
3000 Vdc WITHSTAND TEST VOLTAGE
3 MHz BANDWIDTH
OPEN COLLECTOR OUTPUTS
RECOGNIZED UNDER THE COMPONENT
PROGRAM OF UNDERWRITERS
LABORATORIES, INC. (FILE NO. E55361)

Description

Absolute Maximum Ratings

The HCPL·2530/31 dual couplers contain a pair of light emit·
ting diodes and integrated photon detectors with 3000V dc
electrical insulation between input and output. Separate con·
nection for the photodiode bias and output transistor coliec'
tors improve the speed up to a hundred times that of a conven·
tional phototransistor coupler by reducing the base·collector
capacitance.

Storage Temperature . . . . . . . . . . . . . . . _55°C to +125°C
Operating Temperature . . . . . . . . . . . . . . -55°C to +1 OO°C
Lead Solder Temperature . . . . . . . . . . . . . . 260°C for lOs
(1.6mm below seating plane)
Average Input Current - IF (each channell. . . . .. 25mA[1)
Peak Input Current - IF (each channell ......... 50mA[2]
(50% duty cycle, 1 ms pulse width)
Peak Transient Input Current - IF (each channell .... 1.0A
(';;l,(1s pulse width, 300pps)
Reverse Input Voltage - VR (each channel) ...... _ ... 5V
Input Power Dissipation (each channell . . . . . . .. 45mW[3]
Average Output Current - 10 (each channell ....... 8mA
Peak Output Current - 10 (each channel). ......... 16mA
Supply and Output Voltage - Vee (Pin 8-5), Vo (Pin 7,6·5)
· . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -O.5V to 15V
Output Power Dissipation (each channell. . . . . .
35mW[4]

The HCPL·2530 is suitable for use in TTL/CMOS, TTL/LSTTL
or wide bandwidth analog applications. Current transfer ratio
(CTR) for the ·2530 is 7% minimum at IF = 16 mAo
The HCPL·2531 is suitable for high speed TTLfTTL applica'
tions. A standard 16 mA TTL sink current through the input
LED will provide enough output current for 1 TTL load and a
5.6kn pull·up resistor. CTR of the -2531 is 19% minimum at
IF=16mA.

See notes, following page.

50

Electrical Specifications

5,

4691. ~We:';umIQlty, t .. 6 s

V 1..o,'"!39:OQVdC, fA" 26"C

,

4!W>P!:!II~ve

Hqrnidlty, t .. 5$

v,':'l;'5@dc
, "~itaruHl;: ",'

,'0.25

" Hnput411j:i.Utl,""

r

l

-

'

8

pF ;'

•• All typical. at 25° C.

Switching Specifications at TA=25°C Vcc = 5V, IF = 16mA, unless otherwise specified
:;

.,~~

,

Sym.

PropagirtionO&tav
Time Tol.09ic Low
at O\ltput;

I' .coI1'lM:GIlt.1odjl Tr,", ;'

2530

0.3

1.6

1'$

RL"'4.1kO

2531

0.2

0.8

liS

FiL: 1,91<£1

2530

0.4

1.5

11$

RL=4.1kn

2531

0.3

,0.8

lAS

RL "',9kO

2530

1000

V/#s

IF ~OmA;RL =4.1 kO,VCM""OVp•p

2531

1000

VIlAS

I,,=OmA,R L"".9kO,VCM=1 OVp-p

2530

-1000

Vlp.s

VCM=10Vp-p, RL .. 4.1k£1

2531

-1000

V/lls

VCM = 10Vp -p. RL =1.9kO

MH2

RL =.1000

Test Cortditions

CML

,LOW' \.iWeI;Ouiput

"~lthh.'."',.,;.,,.

Units

CMH

Co~ MOde'tiiln-

""lent fmmdllitv itt LOgic

Male.

Min.

tPLti

,"to.:"."
sient Imrnull;tYat Logic
High ~ OUtput '..

Typ.

HCPL·

tpHL

f'lWagetioi! Delay:
Ti~t9: l.,o9teHl9h.

Devi..

ew

3

Fig.

Note

5,9

10,11

5.9

10,11

10

9.10,11

10

9,10,11

8

12

NOTES:

1.
2.
3.
4.
5.
6.

Derate linearly above 70°C free-air temperature at a rate of O.8mAfC:
Derate linearly above 70°C free-air temperature at a rate of 1.6mAfC,
Derate linearly above 70°C free-air temperature at a rate of o.9mWfc.
Derate linearly above 70°C free-air temperature at a rate of 1.0mWfC.
Each channel.
CURRENT TRANSFER RATIO is defined as the ratio of output collector
current, 10, 'to the forward LED input current. IF. times 100%.
7. Device considered a two-terminal device: Pins 1,2.3, and 4 shorted
together and Pins 5, 6, 7, and 8 shorted together.

8. Measured betlN8en pins 1 and 2 shorted together, and pins 3 and 4
shorted together.
9. Common mode transient immunity in Logic High level is the maximum
tolerable (positive) dVCM/dt on the leading edge of the common mode
pulse VCM, to assure that the output will remain in a Logic Hi!ll state
(i.e., Va> 2.0V). Common mode transient immunity in Logic Low
level is the maximum tolereble (negatjvel dVCM/dt on the trailing
edge of the common mode pulse signal. VCM. to assure that the output
will remain in a Logic Low state (i.e., Va < o.avl.
10. The 1.9kn load represents 1 TIL unit load of 1.6mA and the 5.6kn
pull-up resistor.

51

11. The 4.1kn load represents 1 LSTTL uRit
load of O.36mA and 6.1kQ pull-up resistor.
12. The frequency at which the ec output
voltage is 3dS below the low
frequency asymptote.

10 -

1-5

_ --

",J.C'

fA
V",,'S,OV

.... 40 mA
"",,'"

...

- _.....
..
................
'/"" -_ -.......
,"--I'

.........

-:...-~

'

",,;.-,

'/

....

--~-. 'H~.2530
_HCI'I.-2531,

_35 mA,
0

;::

<
a:

-

"

1,0

ll;

....

z

<

I!:

1--"25 mA

----

5

\,

a:
w

... 30 rnA

NORMAlIZED'
"15mA

l-

I,

zw

,Y,;'

a:
a:
::>
u
0
w
N
::l

20 mA

Vcc:

TA

~,fN

'o25"C

0,5

<
:E

'SmA

o,QAV"

a:
0

z

10mA
IF -6mA

o

o

10

0,1 0~------~-----~'O~-----;';"~OO

20

IF -INPUTCURRENT-mA

Vo - OUTPUT VOLTAGE - V

Figure 1. DC and Pulsed Transfer Characteristics.
100

tJ

Figure 2. Currant Transfer Ratio VI. Input Current.

1.1

I
I

,.'" r--' ~

1,0
10

/

II f}-

/

1

.0 1
1.1

/

1.2

1.3

~L_l HCpL2530I~

,,,

- - - HCI'~.25311 '

NO:"'ALI~~O
I. -_A';'
Vo =0,4V
Vee =5V
T. -25"C

" ""

0.9

IF

1.0

........

",.

I

'\.,

!--

~'

0.8

\

0,7

1.4

1.5

1.6

1.7

O.6
-60

1.8

-40

20

-20

40

60

80

100

120

140

"" - FORWARD VOLTAGE - V

Figure 3. I nput Current vs. Forward Voltage.

Figure 4. Current Transfer Ratio

VI.

Temperature.

600

IF • 16mA. Vee .5,OV
~.,",,:::' .e!I3O

_

IRl • 4.1km

-2631 (Rl

-II
........

lriIj

1.9k!l)

-

......
1,... .... it>\.

0

::::'-4--

0
-60

--rI
-40

-20

--'
,,""

Io---..l.--

.......

..... .-

--20

IF -0

~

I

/

1.1... v.:c «5.0V

/'

K/

/'

./

.........

IP\.H

:J:

~ 100

~
§ 10- L...---'

/

I"

/'

""

u

1

I

I
40

60

80

]
100

10-2

-50

TA ..:. TEMPERATURE - Co

-26

+25

+50

+75

+100

TA - T~MPERATURE -C'

Figure 5. Propagation Delav vs. Temperature.

Figur.6. Logic High Output Current

52

V5.

Temperature.

III
I

w

I

[

a:

IIIN
:::;

"a:
:;

!i1

f - FREQUENCY - MHz

----f

+6V o--......

+16V

I. - QUIESCENT INPUT CURRENT - mA

Figure 7. Small-8ignal Currant Transfer Ratio vs.
Quiescent Input Current.

Figure 8. Frequency Response .

.....-1r----o +6V

1/1 r ;

.........

.

CapaCitance (lnput'-Output)
Input forward Voltage

'i'

7..•....•.

'

.
.
ICCl

low level Supply

UNLESS OTHERWISE NOTED

7

%

= 5V, TA = 25' C

switching Characteristics at TA =25°C Vcc =SV
I

Parameter

I

Symbol

.

Min_

Typ.

Max.

45

75

M

45

75

ns .':

. Units'

Propagation Delay Time to
High Output Level

tPLH

Propagation Delay Time to
Low Output Level

tpHL *

Output Rise-Fall Time

tr, tf

25

ns

Propagation Delay Time of
Enable from VEH to VEL

tELH

25

ns

Propagation Delay Time of
Enable from VEL to VEH

tEHL

15

ns

Common Mode Transient
Immunity at Logic High
Output Level

CMH

50

vIps

Common Mode Transient
Immunity at Logic Low
Output Level

CMl

-150

vlJ.Ls

.

'.'

Test-Conditions

Figure

Note

Rl=35On, CL'" 15pF,
. IF "'7.5mA

7,9

1

RL=350n,~=15pF.
IF=7,5mA

7,9

2

g

3

. "·8

4

VCM=10VRL,;,350n,
Vo (min.j=2V,IF=OmA

11

6

VCM=10VRL",350n,
Vo(max.)=O.8V,
1,,"'SmA

11

6

R1..,:,350n,~=15pF,
. IF"7~5mA' .'

(10-90%)

I

Rl",350n,Ct. =1t;pF,
'F"'7.5mA, VEH"'3.0V,
VEI."'O.5V·· . ·.
RL=350n, ~=15pF,

...

'

IF""7:5mAVSH'=3.-oV,
,VEl=O·5V

•JEDEC Registered Data.

55

Operating procedures and Definitions
Logic Convention. The 6N137 is defined in terms of positive
logic.
Bypassing. A ceramic capacitor (.01 to 0.1IlF) should be connected from pin 8 to pin 5 (Figure 12). Its purpose is to stabilize the operation of the high gain linear amplifier. Failure to
provide the bypassing may impair the switching properties. The
total lead length between capacitor and coupler should not exceed 20mm.
Polarities. All voltages are referenced to network ground (pin
5). Current flowing toward a terminal is considered positive.
Enable Input. No external pull-up required for a logic (1), i.e.,
can be open circuit.

... ......

80

70

..

E

.... ......

....

1~~

,> ...... i!~

60

...z

6;'~

I

~.

w

50

a:
a:

~

:::>

"
a;

40

w

30

.....- ,

..... ..
-

~~+

~

8

'1''''-

20

1

...

...

~-

r-

--I-- ---.

4,.J!>

r-- r--,. .

TA

.~()

.F

I'

lmA~1i!PS

f----,

1

10

o J
o

10

,:.
illa;
a;

:::I

1.0

U
Q

a;

t",.

SmA

..9

...

... -1'""'

\

...I
...I

~

NOTES:
1, The tPLH propagation delay is measured from the 3,7SmA point on the trailing
edge olthe Input pulse to the 1.SV point on the trailing edge olthe ouiput pulse.
2, The tPHL propagation delay is measured from the 3.75mA point on the leading
edge of the input pulse to 1.5V point on the leading edge of the output pulse.
3. The tELH enable propagation delay Is measured from the 1.SV point of the trailing
adge of the Input pulse to the 1.5V point on the trailing adge of the output pulse. ".
4. The tEHL enable propagation delay is measured from the 1,SV point on the
leading edge of the input pulse to the 1.5V point on the leading edge of the
output pulse.
S. Device considered a two terminal device: pins 2 and 3 shorted together, and
pins 5, 6, 7, and 8 shorted together.
6. Common mode transient immunity In Lagle High level Is the maximum tolerabl,
(positive) dVcM/dt on the I,ading edge of the common mode pulse, VCM, to
assure that the output will remain In a Lagle High state (I.e .. VO>2.0V). Common
mode transient immunity In Lagle Low level Is the maximum tolerable
(negative) dVcM/dt on the trailing edge of the common mode pulse Signal, VCM,
to assure that the output will remain in a Lagle Low state (i.e., VO

TA°2!i"C_

I

~

g

!
I

:f'

'\\

r---:-

" -\\
\

TA - TEMPERATURE _

RL

~~
41<0

l00r-~----------r---------~~------

.,.-_.pA

\11
"

°c

Figure 5. Output Voltage, VOL Yo. Temperature and Fan·Out.

__....

~

1IcC~6.5V

"

Vo

~5.5V'

IF - INPUT DIODE FORWARD CURRENT - mA

1>iD--+--+-O Vo
25

50

TA - TEMPERATURE -

Figure 3. I nput-Output Characteristics.

75

°c

Figure 6. Output Current, IOH yo. Temperature liF=250I'A).

56

INPUT VE
MONITORING NODE

+5V
"'-p-UL-se-'"

PULSE

GENERATORr---~~r=~~~~~_ _~

GENERATOR
20=500

Zo=Sofl

,tA'"Sns

...

tR= 50'$
OUTPUT Vo

&.I-+----1~O MONITORING
NODE

IF

:~PUT

H---+-o

470

MONITORING
NODE

OUTPUT Vo

MONITORING
NODE

-

*CL is approximately 15 pF, which includes
probe and stray wiring capacitance.

- 350mV (IF =7.5mA)

J------\,---'c'mVIIF.3.75mA)
---I

tpHL

I-

-I

r------

tpLH

I _______ I_____
~
I

e~TPUT

VaH
1.5V

- - - - - VOL

Figure 7. Test Circuit for tpHL and tpLH.**

100

-..J.Tt-1-

RL =4Kn .....

-,. .,,,

~

....

U
"tHI

Q
Z
Q

Figure 8. Test Circuit for tELH and tEHL.

-

Chan A

Chan B
H--+-1~-O

+5V

+

~

"/~tL'I35on
Ki""'"

50

~

IE

'k tpKL f" t--...

j

R 1'4K~>'

I

. j

"
17

I I

-

o

5

I

-

l"-

I

TA

N-i-

ChanA~

__ j tOL

·25~C

10

Chan B

15

50ns (delay in respon~to
logic High Level mput)

~
1___ tOH

=

==

20ns (delay in response to logic Low Level input)

I FH - PULSE INPUT CURRENT - rnA

Figure 9. Propagation Delay, tpHL and tpLH
vs. Pulse Input Current, IFH.

Figure 10. Response Delay Between TTL Gates.

tr = 160n5
tf'" 55n5

I - T - - - ; - - - O +5V

1 - + - - - " " " - - 0 Va
A
Va

5V

~
SWITCH AT A: IF= OmA

Va

HP1900A

~VOL

SWITCH AT B: IF= 5mA

PULSE GEN.

VCM

Zo = 50n ~

n)---+----,

Figure 11. Test Circuit for Transient Immunity and Typical Waveforms.

_____ _L

GND BUS (BACK)

\==M==¢=
N.C.

OUTPUT 1

-"""--T*rv-

Figure 12. Recommended Printed Circuit Board Layout .

•* JEDEC

ENABLE

(IF USED)

Registered Dala.

57

-=

HIGH CMR,HIGH~~EEO
OPtOCOUPLER

Flidl

HEWLETT
~r.. PACKARD

I

+)
VF

-

-71

I
~---+---r------~---oGND

5

TRUTH TABLE
(Positive Logic)
A 0.01 TO 0.1 "F BYPASS CAPACITOR
MUST BE CONNECTED BETWEEN
PINS 8 AND 5 (See Note 1I.

Figure 1. Schematic.

Input
H

L
H

Enable
H
H~

L·
L

OutPLft

L

H
H
H

Features

Applications

•

•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•

INTERNAL SHIELD FOR HIGH COMMON
MODE REJECTION (CMR)
HIGH SPEED
GUARANTEED MINIMUM COMMON MODE
TRANSIENT IMMUNITY: 1000V/~
LSTTLITTL COMPATIBLE
LOW INPUT CURRENT REQUiRED: SmA
GUARANTEED PERFORMANCE OVER TEMPERATURE: O°C to 70°C
STROBABLE OUTPUT
RECOGNIZED UNDER THE COMPONENT
PROGRAM OF UNDERWRITERS LABORATORIES, INC. (FILE NO. ESS361)
3000 Vdc WITHSTAND TEST VOLTAGE

Isolated Line Receiver
Simplex/Multiplex Data Transmission
Computer-Peripheral Interface
Microprocessor System Interface
Digital Isolation for A/D, D/A Conversion
Switching Power Supply
Instrument Input/Output Isolation
Ground Loop Elimination
Pulse Transformer Replacement

ReCOmmended Operating

CondOt"
I Ions

Sym. MIn.

Input Current, Low Level

IFL

Description

Input Current, High Level

IFH

Supply Voltage, Output

Vq;

The HCPL-2601 optically coupled gate combines a GaAsP
light emitting diode and an integrated high gain photon
detector. An enable input allows the detector to be
strobed. The output of the detector I.C. is an open
collector Schottky clamped transistor. The internal shield
provides a guaranteed common mode transient immunity
specification of 1000 volts/!,sec., equivalent to rejecting a
300 volt P-P sinusoid at 1 MHz.

High Level Enable Voltage

VEH

Low Level Enable Voltage

VEL.

•

Fan Out (TTL Load)

N

Operating Temperature

TA

Max;

250
6.3" :15
4.5 5.5
2.0 Vee
0

l:)

0

Unll$
p.A
mA

V
V
V

0.8
8

'

70

.·C

.

Absolute Maximum Ratings
(No Derating Required up to 70°C)
Storage Temperature ' ............. -55°Cto+125°C
Operating Temperature . . . . . . . . . . . . . . .. 0" C to +70" C
260°C for lOS
Lead Solder Temperature ...........
(1.6mm below seating plane)
Forward Input Current - IF (see Note 2) ....... 20 rnA
Reverse Input Voltage ........................... 5 V
Supply Voltage-Vee ......... 7V (1 Minute Maximum)
Enable Input Voltage - VE ....................... 5.5 V
(Not to exceed Vee by more than 500 mY)
Output Collector Current -10 ................. 25 rnA
Output Collector Power Dissipation . . . . . . . . . .. 40 mW
Output Collector Voltage - Vo .................... 7 V

This unique design provides maximum D.C. and A.C.
circuit isolation while achieving TTL compatibility. The
isolator D.C. operational parameters are guaranteed from
0° C to 70° C allowing troublefree system performance.
This isolation is achieved with a typical propagation delay
of 35 nsec.
The HCPL-2601's are suitable for high speed logic
interfacing, input/output buffering, as line receivers in
environments that conventional line receivers cannot
tolerate and are recommended for use in extremely high
ground or induced noise environments.

4S.3mA condition permits at least 20% CTR degradation guardband. Initial switching threshold is SmA or less.

58

Electrical Characteristics
(Over Recommended Temperature, TA = O°C to +70 o C, Unless Otherwise Noted)

1.5

0.8

V

1.75

V
IR ;".10 ,.tA.

V

fA =25"0

VI' ",p, 1=·1. MHz

pF

mWOC IF."'01Tl~,
• .

."

p.A

Relative Humidity = 45%
TA=25·C,.'t = 5 s,
Vl:"O';; 3000 Vdc

10 12

n

0.6

pF

VI-o"'500 V
f ""1 MHz

..:Ioso'lalion

;i:,~0:~~,'~frent

Capacitance> (lnput..Qutput)
• All typical values are at Vee

= 5V,

C1-0

3

T A = 25° e,

Switching Characteristics
Par. .te,

(TA

= 25°C, Vee = 5V)
Typ.

Max.

Units

propagation'Detay Time to
Rig" OutpUt leilel

tPLH

35

75

ns

Prop~t,o,...pelayTime to

tpHt

35

75

ns

Symbol

Min.

Test Conditions

RL'" 350

Note

6

4

6

5

CL'" 15.pF

low Outpl,itLiMll '.

RI$$ ;r~(1(f9O%)

n

Figure

IF= 7.5 mA

tt

25

ns

Output FaIlJimef-90-10%)

tf

15

ns

Propagation Pelay Time of
Enable.trOm. VEH to VEt

tELH

25

ns

RL"" 350 n, CL =15pF,
IF'" 7.5 mA,VEH = 3 V,
VEt'" 0 V

9

6

teHL

15

ns

Rt "" 350 n. GL = 15 pF,
IF '= 7.5 mA, VEH '" 3 V,
VEt -= OV

9

7

10,000

VI}J.s

VCM '" 50 V (peak),
Vo (min.) = 2 V,

12

8,10

VI}J.$

VeM"" 50 V (peak),

12

9,10

Output

::.:;" .<:',,:

i

Prop~~tionOelay. Time of
'EnableJ~om Ver,to VEH
...... .'.

'

Common Mooe'.
,'.
Tra.~lent Imrnimity .
at High Output Level

CMH

Common Mode
Immunity.'
atL6w Output Leve.l

CML

Trafl$.!enl

1000

.

RL "" 350

-1000 -10,000

59

.

n, IF '" 0 mA

Vo (max,) '" 0.8 V,
RL =' 350 n,II"= 7.5 rnA

NOTES:
1. Bypassing of the power supply line is required, with a 0.01 f.LF ceramic
disc capacitor adjacent to each isolator as illustrated in Figure 15. The
power supply bus for the isolator(s) should be separate from the bus for
any active loads, otherwise a larger value of bypass capacitor (up to 0.1
/-IF) may be needed to suppress regenerative feedback via the power
supply.
2. Peaking circuits may produce transient input currents up to 50 rnA, 50
ns maximum pulse width, provided average current does not exceed 20

6. The tELH enable propagation delay is measured from the 1.5 V point on
the trailing edge of the enable input pulse to the 1.5 V point on the
trailing edge of the output pulse.
7. The tEHL enable propagation delay is measured from the 1.5 V point on
the leading edge of the enable input pulse to the 1.5 V point on the
leading edge of the output pulse.
8. CMH is the maximum tolerable rate of rise of the common mode voltage
to assure that the output will remain in a high logic state (I.e., VOU·I

mAo

>2.0 V).

3. Device considered a two terminal device: pins 1, 2, 3 and 4 shorted
together. and pins 5. 6. 7 and 8 shorted together.
4. The tPLH propagation delay is measured from the 3.75 rnA point on the
trailing edge of the input pulse to the 1.5 V pOint on the trailing edge of
the output pulse.
S. The tpHL propagation delay is measured from the 3.7S mA point on the
leading edge of the input pulse to the 1.SV paint on the leading edge of
the output pulse.

>

-;.

'
Vee 1-= S.5V
Vo = 5.SV
v. ~ 2.0V
t,. = 250~A-

I

...

-

15

ffi

0:
0:

::>
u

...~

10

5o

"-

'-..

oJ

.......

w

~

V).

J

10. For sinusoidal voltages. (ldVCMI
--dt

-... t--....

0.8

Vee"" 5.5V
'*' 2.0V
"" 5.0mA

I
I I
I I

I

'F I

20

30

40

50

60

1

70

10

a...
0:

1.0

ir

~

j0.1

I

40

30

50

60

O.OO\':.0--L.,".2:---:"I.:"4--:'~.6--,:'..B:---:'2.0

70

TA - TEMPERATURE - QC

TA - TEMPERATURE - "c

Figure 2.

20

10

ffia:

/I

',/
'~I =6.4mA

10

I

V ,/

_'o=9.6mA/

~

o

E

lO=·'6.0~~

-'o,=12.B~A·

r.......

I

0

'"

...

o

l:

High Level Output Current
vs. Temperature.

= ,,-fcMVcM (p-p)

max

11. No external pull up is required for a high logic state on the enable input.

I

';:"
S>

9. CML is the maximum tolerable rate of fall of the common mode voltage
to assure that the output will remain in a low logic state (Le., VouT8007B,

9.0

IVee • S.OV

B.O
7.0

w

~
g
...::>
...::>
0
I

2.0

0

_O_'/(\°C

1.0

--

o
o

1

Rl • 'lktl
~TA-O-,/(\°C

-

--

L-==::::::~

2.0

3.0

4.0

5.0

Output Voltage
Input Current.

VS.

Forward

J

probe and stray wiring capacitance.
INPUT

6.0

___+ Nod.

*Ct. isapproKimately 15pF.which includes

~

IF - FORWARD INPUT CURRENT - rnA

Figure 5.

OutputVo
Monitoring

IF

1.0

60

i=

RL -3600
TA

::iw
z

I

3.0

70

Cl

'\

tpHL

1-

~

tpLH

!-

50

.. 1.5mA

--~

60

- c--

'PL~ ~L·4k.:1..... I--

I

±tPLH~
--- 'PLH R =lHl
tpHL RL 350n
f)ptn. R~ "" 1kU ......
..

::-:4

g:
30

.J-

?"""

;.HL Rc 4k!l
<

20
10

~~TPUT~_'5V
Figure 6. Test Circuit for tpHL and tpLH •

~

.,-_._- ' - -

=

40

0

I
---I,·7.5mA

1 - - - - - - 1 - - - IF ""3.75mA

-----l

''~""

-Vee' 5.0V
-If

I

>

I

5.0
4.0

I

>0

'5V

I

6.0

oJ

..

BO

e

Zo" 00 11
tR:5n.

I

>
I

PULSE
IJENERATOR

20

30

40

50

60

TA '" TEMPERATURE - °C

Figure 7.

Propagation Delay vs.
Temperature.

70

,...

2

Voo. $.OV
T4" ;5'.C

80

2

I

~

I

70

....
w
c

Z

o

~

60

2

L

C

.'"

50

~
g:

40

I

30

0

~

~

..

~_--+

t~Kt"'" 3!l0il"

'PHe "l

"lkO

Output Vo
Monitoring
Nod,

"CL is approximately 1SpF, wtlieh indudll$
jlroba and stray wiring capal;itance.

~
~w

~

w
I

'PHL lit -41tpLH for proper operation. A NOR flipflop has infinite CMR for POSITIVELY sloped transients
but requires tpHL < tpLH for proper· operation. An
exclusive-OR flip-flop has infinite CMR for common mode
transients of EITHER polarity and operates with either
tpHL > tpLH or tpHL  tpLH, so NAND gates are preferred in the R-S
flip-flop. A higher drive amplitude or different circuit
configuration could make tpHL 
tpLH or tpHL.

"J;',

e,

9.0

'~':

I

.'

7.0

~
g

..

8.0

4.0

::>
0

3.0

~
I

.~,

II:
II:

'"

": :",0

a

w

~....

g

1< orA
\;.:,
I ....
L"'k&l .

~.:-7lI'C

t" 1'i" CI-1O'C

~

r::-

o

i

w

~
....

I

->

l:

co
i

0

/

I
%

,~"

0

(p-p)

tow

co
~
~;Rt.~lIIIIIA···

= m(,MV(,M

rnll.\

11. No external pull up is required for a high logic state on the enable input.

I

":':~

1,0

dt

>

.'
~

J

---

I

".:/.

:r,

2.0

~

10, For sinusoidal voltages, (ldV('MI

1

&.0

!;

>2,0 V).
9, CM!. is the maximum tolerable rate of fall of the common mode voltage
to assure that the output will remain in a low logic state (i.e., VO('T<0.8
V),

lICe -.5.8V
.:)"

... ,;,

6. The tE!.H enable propagation delay is measured from the 1.5 V point on
the trailing edge of the. enable input pulse to the 1.5 V point on the
trailing edge of the output pulse.
7. The tEH!. enable propagation delay is measured from the 1.5 V point on
the leading edge of the enable input pulse to the 1.5 V point on the
leading edge of the output pulse.
8. CMH is the maximum tolerable rate of rise of ihe common mode voltage
to assure that the output will remain in a high logic state (i.e .. VOI'T

..P
1.0

2.0

3.0

4.0

5.0

8.0
II - INPUT CURRENT - rnA

Ip - FORWARD INPUT CURRENT - mA

Figure 2. Output Voltage va. Forward
Input Current.

TA - TEMPERATURE - "C

Figure 3. Input Characterlstlcl.

>

Figure 4. High Level Output Current
va. Temperatura.

..v

I

w

~

g

~

Output Vo
Monitoring
Node

o

....
w
~
....

-cL is .pproxi....,V 15 pF. which includ•
probe and strIy wiring CIIIIIchllnc..

~I

INPUT

II

~

:f

.

r-

...-I

TA -TEMPERATURE-OC

Figure 5. Low Level Output Voltage
va. Temperature.

U- - ' - - - -

~1·~.~_mA

----1'f------~A
tpHL

1-

-,

~~TPUT~I_

lpLH

r--

--Y-

----UV

Figure 8. Test Circuit for tPHL and tput-

66

TA - TEMPERATURE -·C

Figure 7. Propagation Delay VI.
Temperature.

".

-

Output Vo
Monitoring

~PUT

J------).---..

---3.0V

v

r-~~TPUT~_
---I

TA - TEMPERATURE -'C

I, - PULSE INPUT CURRENT - mA

Figure

a.

Propagation Delay vs. Pulse
Input Current.

Figure 9. Rise, Fall TIme vs.
Temperature.

tEHL

I--

-.., tELH

•••V

Figure 10. Test Circuit for tEHL and tELH.

!Zw

~

I!:

HP1900A

PULSE GEN.
Zo -600
VCM

w

~

DV

SWITCH AT A: II ., 0
5V

CMH

-J"--

I

SWITCHATB: II '"7.5mA

TA - TEMPEIIATURE -'C

figure 11. Enable Propagation Delay
vs. Temperature.

l

Vo o.s'v _ _ _

i ~O~~~-1~t-4--+~r~'+-~-1

Vo (mall.)

Figure 12. Test Circuit for Common Mode
Transient Immunity and
Typical Wa.veforms.

~

VeM - COMMON MODE
TRANSIENT AMPLITUDE - V

Figure 13. Common Mode Transient
Immunity vs. Common
Mode Transient Amplitude.

ENABLE
(lFUSEDI

OUTPUT 1

ENABLE
(lFUSEOI

OUTPUT 2
TA - TEMPERATURE -'C

Figure 14. Relative Common Mode
Transient Immunity vs.
Temperature.

Figure 15. Recommended Printed Circuit
Board Layout.

67

FliP'l

EI!.I

DUAL TTL

HEWLETT

COMPATIBLE
OPTOCOUPLER

PACKARD

HCPl-2630

TECHNICAL DA A

,:·3~

:,: '"

OUTLINE DRAWING

*~,

NOTE:
A .01 TO O.lMF BYPASS CAPACITOR MUST BE
CONNECTED BETWEEN PINS 8 AND 5.

MARCH 1980

n

TYPE
NUMBER

llJlIi991J
0.331.013)

-DATE
CODE

L-------~+----oGND

Features
•
•
•
•
•
•

HIGH DENSITY PACKAGING
DTL/TTL COMPATIBLE: 5V SUPPLY
ULTRA HIGH SPEED
LOW INPUT CURRENT REQUIRED
HIGH COMMON MODE REJECTION
GUARANTEED PERFORMANCE OVER
TEMPERATURE
• RECOGNIZED UNDER THE COMPONENT
PROGRAM OF UNDERWRITERS
LABORATORIES, INC. (FILE NO. E55361)
• 3000Vdc WITHSTAND TEST VOLTAGE

Recommended Operating
Conditions

Description/ Applications
The HCPL-2630 consists of a pair of inverting optically coupled
gates each with a GaAsP photon emitting diode and a unique
integrated detector. The photons are collected in the detector
by a photodiode and then amplified by a high gain linear amplifier that drives a Schottky clamped open collector output
transistor. Each circuit is temperature, current and voltage compensated.

Input Current, Low Level
Each Channel
Input Current, Hlgh Level
Each Channel
Supply Voltage, Output
Fan Out (TTL Load)
Each Channel

This unique dual coupler design provides maximum DC and AC
circuit isolation between each input and output while achieving
DTL/TTL circuit compatibility. The coupler operational parameters are guaranteed from OOC to 70°C, such that a minimum
input current of 5 mA in each channel will sink an eight gate
fan-out (13 mAl at the output with 5 volt VCC applied to the
detector. This isolation and coupling is achieved with a typical
propagation delay of 50 nsec.

Operating Temperature

!

Sym.

Min.

Max_

Units

IFL

0

250

JJA

IFH

6.3'
4.5

15
5.5

rnA
V

0

70

VCC

8

N

TA

°e

Absolute Maximum Ratings
(No derating required up to 70 o e)
Storage Temperature ................. -55°C to +125°C
Operating Temperature .................. O°C to +70°C
Lead Solder Temperature ................. 260°C for lOs
(1.6mm below seating plane)
Peak Forward Input
Current (each channel) ..... 30 mA (~1 msec Duration)
Average Forward Input Current (each channel) ..... 15mA
Reverse Input Voltage (each channel) ............... , 5V
Supply Voltage - Vec .......... 7V (1 Minute Maximum)
Output Current - 10 (each channel) ............ " 16 mA
Output Voltage - Vo (each channel) ................ 7V
Output Collector Power Dissipation ............. 60 mW

The HCPL-2630 can be used in high speed digital interface ap·
plications where common mode signals must be rejected such
as for a line receiver and digital programming of floating power
supplies, motors, and other machine control systems. The elimination of ground loops can be accomplished between system
interfaces such as between a computer and a peripheral memory, pri nter, contro Iler, etc.
The open collector output provides capability for bussing,
strobing and "W IR ED-O R" connection. In all applications, the
dual channel configuration allows for high density packaging,
increased convenience and more usable board space.

• 6.3mA condition permits at least 20% CTR degradation guardband.
Initial switching threshold is 5mA or less.

68

Electrical Characteristics
=O°C TO 70°C) UNLESS OTHERWISE NOTED

OVER RECOMMENDED TEMPERATURE (TA

Par. ..,~';' .

.l..tH'Ig\j~~~;';;':>"""""
<:~I';~';~.
.

'. ' . ' ; ;;;':":"'~~;

..........

~I

~;~:~~;,:,2l;~~>{;

,Milt'

Typ.* Max.

......,

','
7':;;0J;~,~~t~1 IS~;··:r';;·\;
l{:~~~;i:,:. I>. '.'
'...,;.•.,. . • <.••

High LQ\leISlipplyCUr~

,,,,,, ,

.::,.':

"

LoW Le\iel Supply

,,",

..

'

.,:~,L:;

,';

".'.

;>,.j~.:.: .. ":

~;: ,••• '

'.'

>• •

•

r

250

IJA

Vee'" 5.5V, Vo".6.5V,
IF 250J,IA

V

Vee '= 5.5V ,IF .. 5mA

.

....

Q.6

0.5

figure

Test Conditions

3

...

3

,

.'

,

..

",

14

30

mA

f2}.1~i\::
;:?~1:;~;; ...':.

26

36

mA

Vce "";5,5V, I" = 10mA
(Both ~hannel$)

1,0

I1A

Reli!tive Humidity'" 45%
TA ;. 20P C, t"; 55,
VI_O '" 3000Vdc

4

n

Vl-0 '" 50av. T A'" 25°C

4

I,;":~:;~f:':':' '.

~e$il~;mce (tnput-Output)'

..

':R/:o

10 12

Cj;Q

cap8eitance (I nput-Outputl
'l:/lpu,(F!1Itward Voltage

t:

0.6

:·'V
:""

tnplit -Reverse Breakdown
. \l;()ltlige

U

I"

1.75

5

.aVa

I

=

lOt (Sinl<;:

50

.

;:('

Units

Vee" 5.5V,IF.= 0
(Both ~~nnel$l

pF

f = 1MHz, TA '" 25°C

V

IF = 10.rnA, TA

V

la '" 10lJA, T A " 25°C

=25°C

.'

4

4

7,3
I

tnplitCapacitance

CIN

60

pF

Vf=O,f=lMHz

3

1nPl,lt-Input Insulation
l.eakage Current

11-1

0.005

p.A

Relative Humidity '" 45%,
t=55, VI_,=500V

8

Resistance (Input-Input)

Rj.f

1011

VI-' "500V

8

Capacitance (Input-Input)

C14

0.25

°

pF

Current Transfer Ratio

eTA

,700

%

"

. f= lMHz

,

8

IF = 5.0mA, RL

=<

lOon

2

6

• All typical values are at Vee = SV. TA = 2SOC

Switching Characteristics at TA=25°C,Vcc=5V
~CH

CHANNEL
Parameter .

.

Symbol

Min.

Typ .

Max.

Units

Test Conditions

Propagation Delay Time to
High Output Level

tpLH

65

75

ns

Rt" 350 0, Ct = 15pF,
IF" 7.5mA

Propag.tion Delay Time to
Low Output Level

tpHt

40

75

ns

RL = 350
Ct = 15pF,
If =7.5mA

Output Rise-Fall Time (1 ()'90%1

tr. tf

25

ns

Common Mode Transient
Immunity at High OutPl,lt Level

CM H

50

V!l1s

RL '" 350
CI.. " 15pF.
If'" 7.5mA
VCM = 10Vp_p•
Rt "'350n.
Vo (min.) '" 2V, IF '" OmA

CML

-150

V filS

n.

Figure

Note

6,7

1

6,7

2

9

5

9

5

n.

"

"
Common Mode TranSient
Immunity at Low Output Level

VCM '" 10Vp_p,
RI.. '" 3500,
Vo (max.) " O.8V
IF" 7.5mA

NOTE:

It i. essential that a bypass capacitor !.01"F to 0.1,,1". ceramic) be connected from pin 8 to pin 5. Total lead length between both
ends of the capacitor and the isolator pins should not exceed 20mm. Failure to provide the bypass may impair the switching properties( Figure 5).

69

i

NOTES:
>

1. The tpLH propagation delay is measured from the 3.75 rnA point

I

w

on the trailing edge of the input pulse to the 1.5V point on the trail-

Vee=- SxOV
5

'\ F\\
\\
\\:

~

ing edge of the output pulse.
2. The tPHL propagation delay is measured from the 3.75 rnA point

g

on the leading edge of the input pulse to the 1.5V point on the
leading edge of the output pulse.

I-

~

3. Each channel.

I

4. Measured between pins 1, 2, 3, and 4 shorted together, and pins 5, 6,
7. and 8 shorted tog;,ther.

~

1\

1

Ix..

TA.=<25°C--

RL

3500
Vl"Q
4kfi

X'

0

5. Common mode transient immunity in Logic High level is the maxi-

mum tolerable (positive) dVCM/dt on the leading edge of the com·
man mode pulse, VCM, to' assure that the output will remain in a

IF - INPUT DIODE FORWARD CURRENT·- mA

Logic High state (Le., VO>2.0V)' Common mode transient immunity
in Logic Low level is the maximum tolerable (negative) dVCM/dt on
the trailing edge of the common mode pulse signal, VCM, to assure
that the output wilf remain in a Logic Low state (j.e., VO

u

a:

I--------.J.:.-----....-I

20

g

~

0

u
I

10

!?
LOW LEVEL
iNPUT CURREN"

RANGE
Vo - COllECTOR VOLTAGE - V

NOTE: Dashed characteristics indicate pulsed operation.
10-'

L-~_LL-_L_L_~_~~_~_L!..J

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

VF - INPUT FORWARD VOL TAGE-V

Figure 4. Input Diode Forward Characteristic
CURVE
TRACER
TERMINALS

______ /GNDBUSIBACKI

Figure 2. Optocoupler Transfer Characteristics.

Figure 5. Recommended Printed Circuit Board Layout.

70

+SV
PUlS£

GetII£I\ATOA
·HP8007

Zo",501);
l.-Sm

~

L--~-ovo

*

INPUT
MONITORING
NODE

CL

"oz
;::
"""is

OUTPUT
MONITORING
NODE

CL is approximately 15 pF, which includes
probe and stray wiring capacitance.

il:
I

..
%

..
~

INPUT

IF

-

- 350mV (IF = 7.SmA)

J-----\---',SmvIIF:3.,SmAI
-----+I
I---- ---l
t*"-

i _______y____ ,V:~

tPHL

~~TPUT

tPLH

IFH - PULSE INPUT CURRENT - rnA

- - - - - VOL

Figure 7. Propagation Delay, tpH Land tPLH
yo. Pulse Input Current, I FH.

Figure 6. Test Circuit for tpHL and tPLH.

r---f~~-----------------------------------L~~-oChanA

+SV
INPUT

v--,~~--,.

rll:>oo---o Chan B
~'-------+---'---~+SV

1404

~anA-----'L________~

Chan B

-----+1--:___''____. 1.I
. 1-

470Q

tOl '" 50 os (delay in response to
logic low level input)

tDH '" 30 ns (delay in response to
logic high 18IIei input)

TA=25°C

Figure 8. Response Delay Between TTL Gates.

tr"160ns

,0%}

....------....--o +5V

,~

.,:9;:,0%::....".=.5.S"'
350n

"
Vo
Vo ---_~-------- SV
SWITCH AT A: IF'" OmA
VCM

Vo ------------~VOL

L-----------~----~,JL~------~

SWITCH AT B: IF = 7.5mA

HP 1900A
PULSE GEN.

Zo

"50n

Figure 9. Test Circuit for Transient Immunity and Typical Waveforms.

71

rli;'

HEWLETT
~~ PACKARD

LOW INPUT CURRENT,

&N138

HI(jH~GAIN

n

OPTOCQUpLERS

TECHNICAL DATA MARCH 1980

OUTLINE DRAWING* .

SCHEMATIC
~

8

ANODE]2
'~
lip

.

~

CATHOOE3

7

141

Features

Applications

•
•
•
•
•
•

• Ground Isolate Most Logic Families - TTL/TTL, CMOS!
TTL, CMOS/CMOS, LTTLmL, CMOS/LTTL

•
•
•
•

HIGH CURRENT TRANSFER RATIO - 800% TYPICAL
LOW INPUT CURRENT REQUIREMENT - 0.5mA
TTL COMPATIBLE OUTPUT - 0.1V VOL
3000 Vdc WITHSTAND TEST VOLTAGE
HIGH COMMON MODE REJECTION - 500V/J.Is
PERFORMANCE GUARANTEED OVER TEMPERATURE
O°C 10 70·C
.
BASE ACCESS ALLOWS GAIN BANDWIDTH
ADJUSTMENT
HIGH OUTPUT CURRENT - 60mA
DC TO 1M blt/s OPERATION
RECOGNIZED UNDER THE COMPONENT PROGRAM
OF UNDERWRITERS LABORATORIES, INC.
(FILE NO. E55361)

•

Low Input Current Line Receiver - Long Line or Partyline

.EIA R5-232C Line Receiver
• Telephone Ring Detector
•

117 V ac Line Voltage Status Indicator - Low Input Power
Dissipation

•

Low Power Systems - Ground Isolation

Description
These high gain series couplers use a Light Emitting Diode and
an integrated high gain photon detector to provide 3000V dc
electrical insulation, 500V/lAs common mode transient immunity and extremely high current transfer ratio between input
and output. Separate pins for the photodiode and output
stage result in TTL compatible saturation voltages and high
speed operation. Where desired the· Vee and Vo terminals
may be tied together to achieve conventional photodarlington
operation. A base access terminal allows a gain bandwidth
adjustment to be made.

Absolute Maximum Ratings·
Storage Temperature ............. -55·C to +125°C
Operating Temperature. . . . . . . . . . . . . . .. O·C to +70·C
Lead Solder Temperature . . . . . . . . . . . .
260°C for lOs
(1.6mm below seating plane)
Average InputCurrent-IF ................ 20mA [1)
Peak Input Current - IF . . . . . . . . . . . . . . . . . . . . 40mA
(50% duty cycle, 1 ms pulse width)
Peak Transient Input Current - 'F. . . . . . . . . . . . .. 1.0A
(=s;; lIAS pulse width, 300 pps)
Reverse InputVoltage - VR . . . . . . . . . . . . . . . . . . . 5V
Input Power Dissipation. . . . . . . . . . . . . . . .. 35mW [2)
Output Current - 10 (Pin 6) ....•......... 60mA [3)
Emitter-Base Reverse Voltage (Pin 5-7) ........... 0.5V
Supply and Output Voltage - Vee (Pin 8-5), Vo (Pin 6-5)
6N138 ...............•........... -0.5 to 7V
6·N139 . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 18V
Output Power Dissipation ................ 100mW [4)

The 6N139 is suitable for use in CMOS, LTTL or other
low power applications. A 400% minimum current transfer
ratio is guaranteed over a 0-70·C operating range for only
0.5mA of LED current.
The 6N138 is suitable for use mainly in TTL applications.
Current Transfer Ratio is 300% minimum over 0-70·C for an
LED current of 1.6mA [1 TTL unit load (U.L.)]. A 300%
minimum CTR enables operation with 1.U,L. in, 1 U.L. out
with a 2.2 krl pull-up resistor.

See note., following page.

"JEDEC Registered Data.

72

Electrical specifications
OVER RECOMMENDED TEMPERATURE (TA= O°C to 70°C), UNLESS OTHERWISE SPECIFIED
Param_
Current Transfer Ratio

r

Syro.

CTR*

Oeviee
GN139
GNUS

t...

Lo!IlC LOw
OutPUt VOItaQ.
, Logic High
OutPut, Current
, I.oglc L.ow,

VOL.

'OH·

Mm.

Typ."

400

800
900
600

500
300

6N139
6Nl38
6N139
GN138

M.x.

Units

Test Conditions

Fig.

Note

%

IF" o.SmA, Vo =0.4V, Vcc = 4.SV
IF "1.6mA, VO" OAV, VCC"4.5V
IF" !.6mA. VO" 0.4V, Vcc ·4;5V

3

5,6

%

0.1
0.1
0.2
0.1

0.4
0.4
OA
0.4

' 0.05
0.1

100
250

V
V, '
itA
pp.

IF .. 1.6mA, 10 .. UmA, Vcc ='4.5V
IF" SmA, 10 "15mA. VCC" 4.SV
1.2
IF" 12mA, 10 - 24mA, Vce" 4.5'1
IF • 1.6mA, 10" 4.BmA, 'ICC =4.5V,

6

IF" OmA. '10 ='ICC" l8V
IF "OmA, '10= 'ICC" 7V

6

IF" 1.6mA. VO" Open, VCC" 5V

6
6

SupQly Current.

ICCL

0.2

rnA

Lallie High
,Supply Current

ICCH

10

nA

IF" OmA, '10" Open, 'ICC" 5V

Input Forward Voltage

VI'"

1.4

V

If''' 1.6mA, TA" 2S C

'Input Reverse
Breakdown VoltsIIII

eVR·

Tentjlerature Coefficient
of Forward Voltage

loVF

Input Capacitance
'nput - Output
InSltlation Leakage
, Current

5

A'iA
CIN

1.7

D

4

IR .. 1()p.A, TA"25°C

V
-1.8

mVfC

60

pI'

f=1 MHz, VI''' 0

pA

45% Reletive HumiditY. TA" 25"C
t - 5 s, V 1-0 "3000Vde

7

IJ..O*

1.0

IF" 1.6mA

'Flesi$tanca
!lftput.OutPut)

RI·O

10"

Cl

'VI..o" 500 'Ide

7

Capacitance
' ,!lnput-OutPutl

C,..o

0.6

pF

f=l MHz

7

··AII typicals at TA = 25°C and VCC = 5V. unless otherwise noted.

Switching Specifications
AT TA= 2SoC
Parameter

Sym.

Propagation Delay Time
To Logic Low at Output tPHL*

r"

Device
6N139
6N13S

Propagation Delay Time
tpLH*
To Logic High at Output

6N139
6N138

Min.

Typ.

M.x.

5
0.2
1

25
1

Its

10,

ps

5
1
4

60
7
35

Fig.

Note

IF = 0.5mA, RL = 4.7kCl
IF = 12mA, RL = 270f!
IF = '.6mA, RL " 2.2kf!

9

6,8

IF" 0.5mA, RL = 4.7kU
'F" 12mA, RI. .. 270n
IF = 1.6mA, RL - 2.2kCl

9

6,8

Units

/1.$

,..

Test Conditions

Common Mode Transient
Immunity at Logic High CMH
Level OutPut

500

V/lts

IF 0mA, RL " 2.2kn, RCC" 0
!vern I " IOVPi'

10

9,10

Common Mode Transient
Immunity at logic Low CML
Level Output

-500

VI,..

IF" 1.6mA, RL " 2.2kCl, RCC =0
!vern l - 10Vp1l

10

9.10

=

NOTES:
1. Derate linearly above 50° C free-air temperature at a rate of 0.4 mAf C.
2. Derate linearly above 50°C free-air temperature at a rate of 0.7 mWf C.
3. Derate linearly above 25°C free-air temperature at a rate of 0.7mAfC.
4. Derate linearly above 25°C free-air temperature at a rate of 2.0mWfC.
5. DC CURRENT TRANSFER RATIO is defined as the ratio of output collector current. 10. to the forward LED input current, IF, times 100%.
6. Pin 7 Open.
7. Device considered a two-terminal device: Pins 1,2.3. and 4 shorted together and Pins 5, 6, 7, and 8 shorted together.
8. Use of a resistor between pin 5 and 7 will decrease gain and delay time. See Application Note 951·1 for more details.
9. Common mode transient immunity in Logic High level is the maximum tolerable (positive) dVcm/dt on the leading edge of the common mode
pulse, Vern, to assure that the output will remain in a Logic High state (;.e.• VO> 2.0V). Common mode transient immunity in Logic Low level
is the maximum tolerable (ntllStive) dVern/dt on the trailing edge of the common mode pulse signal, Vcm • to assure that the output will remain
in a Logic Low state (;.e., Vo < 0.8V).
10. In applications where dV /dt may exceed 50,OOOV/liS (such as static discharge) a series resistor. RCC, should be included to protect
the detector IC from destructively high surge currents. The recommended value is RCC '"
1V
kCl.
0.15 IF {mAl
'JEDEC Registered Data.

73

"E
...I

~
a:
a:

:::>

...u

~
I

J;

Vo - OUTPUT VOLTAGE - V

110 - OUTPUT VOLT AGE - V

Figure 1. SN139 DC Transfer Characteristics.

Figure 2. SN138 DC Transfer Characteristics.

..

100

·L2S.l

I

I

f

,

10

"E
...I

~
a:
a:

~ 1.0

i12

/

I

.!!.1

.0 1

.

1.1

/:

1.2

1.3

VF -

1.4

~

..

1/

IF - FORWARD CURRENT - rnA

Figure 3. Current Transfer Ratio vs. Forward Current.

/ £1-IF

:::>

.•.

1.5

1.6

1.7

1.8

FORWARD VOLTAGE - V

Figure 4. Input Diode Forward Current
Forward Voltage.

Yo.

1oo.. - - - - - _ , - - -_ _ _ _,--_ _ _-""'""1_--.

"

~

E
I

10.1__--~--1__-----f_::".'----_l--'.._l

I

...

ffi

~
a:
a:

a:
a:

:::>
u

1.0 1__-----I----"7.~-r~--~_c__l-_-l

:::>

u

~

~

i!:
:::>
o

0.10

,--~--'..-+_7'#'--_=___:::±:__-'--'-'--+.~-_I

o

~ 0.010 f-------,'-j,i"----c..:..-r-~---1"--_:_':_I
0.0~~0.=1:-0--.L-..LJ'-::-'::"------=':--------:1::-0.--...J

IF - INPUT DIODE FORWARD CURRENT - rnA

IF - INPUT DIODE FORWARD CURRENT - rnA

Figure S. SN138 Output Current vs. Input Diode

Figure 5. SN139 Output Current vs. Input Diode
Forward Current.

Forward Current.

74

100.

D

!I.
I

S
"
w

!I.

I
w

~

~

;:

~

10.

.II!.,.
I

TA - TEMPERATURE -'C

Figure 7. Propagation Delay

VI.

RL - LOAD RESISTANCE -

kn

Figura 8. Non Saturated Rise and Fan Tim.. vs. Load
Resistance.

Tamperatura.

1--.._---0 *,1/

5V

I - -.....- ......-ovo

10'11
If

r
l

Figure 9. SWitching Test Circuit.·

1:

10%

RCC'"

tr,tl=18n.

.::::..__

tf

I - - -.....--ovo
A

110 ----~..::.--;,;_------- 5V
SWITCH AT A: IF- OmA

Vo ----------~IIoL
SWITCH AT B: IF .1.6mA

Figura 10. Test Circuit for Transient Immunity and Typical Waveform••
"See Note 10

'JEDEC Registered Data.

75

DUAL LOW INPUT
HCPl-2730
CURRENT, HIGH GAIN HCPL-2731
OPTOCOUPLERS

FliDW

HEWLETT
a!~ PACKARD

TECHNICAL DATA MARCH 1980

OUTLINE DRAWING
TYPE
NUMSER

OAT'E
CODE

SCHEMATIC

.,---------r.;=;==A
t

~

ICC,

~

t

Q,$3

6,10{.2~

l __
I

8

r---~~----------~--o~C

tOll}

7.88 (10) 6.60 {.260}

5"

rvp,

DIMENSIONS IN Ml-lltMETRES ANO (INCHES)

ANODE1~"
CATHODE 1 2

CATHODE i
ANODE

t

Vee

7 VOl

//

V02

4

GNO

5

L--~~-oGND

Features

Applications

•
•
•
•
•
•

• Digital Logic Ground Isolation

•
•
•
•

HIGH CURRENT TRANSFER RATIO - 1000% TYPICAL
LOW INPUT CURRENT REQUIREMENT - 0.5 mA
LOW OUTPUT SATURATION VOLTAGE - 1.0V TYPICAL
HIGH DENSITY PACKAGING
3000 Vdc WITHSTAND TEST VOLTAGE
PERFORMANCE GUARANTEED OVER O'C TO 70'C
TEMPERATURE RANGE
HIGH COMMON MODE REJECTION
DATA RATES UP TO 200K BIT/s
HIGH FANOUT
RECOGNIZED UNDER THE COMPONENT PROGRAM OF
UNDERWRITERS LABORATORIES, INC. (FILE NO. E55361).

• Telephone Ring Detector
• EIA RS-232C Line Receiver
• Low Input Current Line Receiver - Long Line or Parlyline
• Microprocessor Bus Isolallon
• Current Loop Receiver
• Polarity Sensing
• Level Shilling
• Line Voltage Status Indicator - Low input Power Dissipation

Description
The HCPL-2730/31 dual channel couplers contain a separated pair of GaAsP light emitting diodes optically coupled to a
pair of integrated high gain photon detectors. They provide extremely high current transfer ratio, 3000V dc electrical
insulation and excellent input-output common mode transient immunity. A separate pin forthe photodiodes and first gain
stages (Vee) permits lower output saturation voltage and higher speed operation than possible with conventional
photodarlington type isolators. The separate Vee pin can be strobed low as an output disable. In addition Vee may be as
low as 1.6V without adversely affecting the parametric performance.
Guaranteed operation at low input currents and the high current transfer ratio (CTR) reduce the magnitude and effects of
CTR degradation.
The outstanding high temperature performance of this split Darlington type output amplifier results from the inclusion of
an integrated emitter-base bypass resistor which shunts photodiode and first stage leakage currents to ground.
The HCPL-2731 has a 400% minimum CTR at an input current of only 0.5 mA making it ideal for use in low input current
applications such as MOS, CMOS and low power logic interfacing or RS232C data transmission systems. In addition, the
high CTR and high output current capability make this device extremely useful in applications where a high fanout is
required. Compatibility with high voltage CMOS logic systems is guaranteed by the 18V Vee and Va specifications and by
testing output high leakage (I OH) at 18V.
The HCPL-2730 is specified at an input current of 1.6 mA and has a 7V Vee and Va rating. The 300% minimum CTR allows
TTL to TTL interfacing with an input current of only 1.6 mAo
Important specifications such as CTR, leakage current and output saturation voltage are guaranteed overthe O°C to 70°C
temperature range to allow trouble-free system operation.

76

Electrical Specifications
(Over Recommended Temperature TA =
Parameter
Current Transfer Ratio

LogiC Low
Output Voltage

Sym.

CTR

Logic Low
Supply Current

Device-

Min.

Typ.-

Units

Tfst Condition.

Fig.

2731

400
500

1000
1100

%

IF ~ O.SmA, Vo ~O.4V, Vcc =4.5V
IF: 1.6mA. Vo = OAV, Vee: 4.5V

2

2730

300

1000

%

IF ~ 1.6mA, Vo : O.4V, Vee" 4.5V

2

V

IF = 1.6mA.to ~ 8mA, Vcc:4.5V
IF =5mA,lo" 15mA, Vce=4.5V
I F =12mA,l o =24mA, Vce~4.5V

1

'F = I.SmA,lo =4.SmA, Vce =4.5V

0.1
0.1

2731

10H
ICCL

Logic High
SupplV Current

teCH

Unless Otherwise Specified)

HCPL·

0.2

VOL

Logic High
Output Current

oDe to 70De,

0.1

0.4

V

0;005

100

j./A

IF" 0 mA, Vo· Vee" 18V

2730

0.01

250

p.A

'F=OmA, Vo "Vee =7V

2731

1.2
0;9

mA

5
4

nA

2730
2731
2730

VF
BVR

Temperature Coefficient
of Forward Vollage

AVF
ATA

-1.8

Input Capacitance

CIN

60

1.4

CapaCitance
(lnput·Output)
Input-Input
Insulation Leakago Current

1.7

5

Input·Output Insulation

(Input-Output)

"

2731

Input F.orward Voltage

Resistance

0.4
0.4
,0.4

2730

1nput Reverse Br~kdown
Voltage

Leakage Current

Max.

1.0

1'·0
10 ,2

U

CI-D

0.6

pF

4 ",

6

IF" 1.6mA

6

f= 1 MHz. VF =0

6

45% Relative Humidity. TA "25"C

a

t" 5., Vt-o

=3OO0Vd"

8

f = 1 MHz

8

IlA

45% Relative Humidity, 1=5>,
VI_I; 500Vdc

9

VJ.I =500Vdc

9

f = 1 MHz

9

RJ.I

1011

U

Capacitance
(tnpuI.lnput)

C,.!

0,25

pF

=

6

VI-D ; 500Vdc

Resistance
(lnput·lnput)

*AII typicalsat TA

6

ee ·18V

'R=IOp.A, TA"25"C

j./A

0.005

V

V

RI_o

11.1

Vee -7V

1Ft = I F2 "OmA

V

pF

6,7

Vcc ·l,BV

1Ft = 'F2 "1.6mA
VOl =V02 " Open

VOl "V02 =Open
Vce=7V
IF = I.SmA, TA "25"C

mV/"C

Note

2SoC

Switching Specifications at TA =25°C
ri

\

Parameter
Propagation Delav Time
To Logic Low
at Output

Sym_

Device
HCPl2731

tPHl

Min.

Typ.

Max_

Unit$

25

100

j./I

IF ;0.5mA,

1"

IF
IF

liS

0.5

20
2

2731

20

60

2730/1

10
1

35

I~

10

I~

273011

5.

Propagation Delay Time
To Logic High
.tOutput

tPLH

Common Mode
Transient tmmunity at
Logic High Level Output

CMH

500

CM L

·500

V/JJS

V!j./s

Logic Low Level Output
NOTES: 1. Derate linearly above 50° C free-air temperature at a rate of O.5mA/oC.
2. Derate linearly above 50°C free-air temperature at a rate of O.9mWrC.
3. Derate linearly above 3SoC free-air temperature at a rate of 0.6mArC.
4. Pin S should be the most negative voltage at the detector side.
S. Derate linearly above 3SoC free-air temperature at a rate of 1.7mWrC.
Output power is collector output power plus supply power.
6. Each channel.
7. CURR ENT TRANSF ER RATIO is defined as the ratio of output
collector current, 10, to the forward LED input current, IF, times 100%.
8. Device considered a two-terminal device: Pins 1, 2, 3, and 4 shorted
together and Pins 5, 6, 7, and 8 shorted together.
9. Measured between pins 1 and 2 shorted together, and pins 3 and 4
shorted together.

R~

Fig.

=4.7kl"l

Note
,

= 1.6mA. Rl ~ 2.2kl"l
= 12mA, RL = 270~!

"

9

IF : 0.5mA. R L .. 4.71 2.0Vl. Common mode transient immunity in Logic Low
level is the maximum tolerable (negative) dVCM dt on the trailing edge

of the common mode pulse signal, VCM. to assure that the output will
remain in a Logic Low state (i.e.,

Vo < C.BV).

11. In applications where dV/dt may exceed 50,000 Vllls (such as a static
discharge) a series resistor,

Rce. should be

included to protect the

detector Ie from destructively high surge curredts. The recommended
value is Rce ~ _ _
1V_ _ kn.
0.3 IF (rnA)

77

"

.

Absolute Maximum Ratings
Storage Temperature .......... -55°C to +125°C
Operating Temperature ......... -40°C to +85° C
Lead Solder Temperature ....... 260°C for 10sec
(1.6mm below seating plane)
Average Input Current - IF
(each channel) ..................... 20 mA (1)
Peak Input Current - IF
(each channel) . . . . . . . . . . .. . .. .. .. .... 40 mA
(50% duty cycle, 1 ms pulse width)
Reverse Input Voltage - VR
(each channel) . . . . . . . . . . . . . . . . . . . . . . . . .. 5V

Input Power Dissipation
(each channel) . . . . .. . . .. . . .. .. . . .. 35 mW (2)
Output Current - 10
(each channel) . .. . . . . .. . . . . . .. . . .. 60 mA 13)
Supply and Output Voltage - Vee (Pin 8-5), Vo (Pin
7,6-5)[4)
HCPL-2730 ........................ -0.5to 7V
HCPL-2731 ....................... -0.5to 18V
Output Power Dissipation
(each channel) . . . . . . . . . . . . . . . . . .. 100 mW (5)

~
I

~

8

~

o
I

51

100
IF

Vo - OUTPUT VOLTAGE - V

Figure 1. DC Transfer Characteristics.

FORWARD CURRENT - rnA

Figure 2. Current Transfer Ratio vs.
Forward Current.

j:I
VF -FQAWAROVOLTAGE-V

Figure 4. 'Input Diode Forward Current
Forward Voltage.

VS.

IF - INPUT DIODE FORWARD CURRENT - rnA

Figure 3. Output Current vs. Input
Diode Forward Current.

100

IF - INPUT DIODE FORWARD CURRENT - rnA

Figure 5. Supply Current Per Channel
vs. Input Diode Forward Current.

78

T - INPUT PULSE PERIOD - ms

Figure 6. Propagation Delay To Logic
Low VB. Pulse Period.

70
~2730

Vee .. $V

.. '-

z

~

40

~

30

,

20

!
>-

z
!2

i...

r:- T. -26'1:

60

~0

,

,
~
o
!

RL=~

E

".

o~

10

20

30

40

50

60

10

\
rr,

"

.'",kG

../.. Rc ~hkn

00

70

TA - TEMPERATURE _·C

Figure 7. Propagation Delay
Temperature.

,,",0114- kn

..v. Rc

0

,

HCPI,413t ,

10
IF - INPUT DIODE FORWARD CURRENT - mA

Figure 8. Propagation Detay vs. Input
Diode Forward Current.

VI.

r-----

---~

HCPL·2730

H'8OO1
PIILSE
GeN,

VO---JE-V
1,6V

HCPl·i731

.,- ....

4-600

"---,¥!---5V:::VO

1-1---o+5V

---VOL

'PHL

IF MONITOR

o

1.5V
---

VOL

"'LH

Figure 9, Switching Test Circuli.

[
HCPL·2730
HCPL·2731

VCM

+5V

'f
~----~~~

SWITCH AT A:

_______________ 5V

IF" OmA

VO--------------------~
SWITCH AT 8:

IF = 1.6mA

VOL
HP1900A

·See Note 11.

PULSE GEN.

Figure 10. Test Circuit for Transient Immunity and Typical Waveforms.

79

c

'

~,:~:'

>,

,:, :::' " ;,::: ,

"

HEVtlt~~,.~·•.

PAckARbt
('

"

'

..

"::\,

+
_
ANODE~'
~'O
VF

'F

Vo6

_

CATHODE
2

GND

•

• Va

Schematic

Features
• HIGH CURRENT TRANSFER RATIO 1000% TYPICAL
• LOW INPUT CURRENT REQUIREMENT 0.5 mA
• 3000 Vdc WITHSTAND TEST VOLTAGE
• PERFORMANCE GUARANTEED OVER O°C TO
70°C TEMPERATURE RANGE
• RECOGNIZED UNDER THE COMPONENT
PROGRAM OF UNDERWRITERS
LABORATORIES INC. (FILE NO. E55361)
• INTERNAL BASE-EMITTER RESISTOR
MINIMIZES OUTPUT LEAKAGE
• GAIN-BANDWIDTH ADJUSTMENT PIN
• HIGH COMMON MODE REJECTION

OIAf_IN""U.IAfET~"$ANO (INCHES).

O~Un. Drawing"

Applications
•
•
•
•

Telephone Ring Detector
Digital Logic Ground Isolation
Low Input Current Line Receiver
Line Voltage Status Indicator Dissipation
• Logic to Reed Relay Interface
• Level Shifting
• Interface Between Logic Families

Description
The 4N45/46 optocouplers contain a GaAsP light emitting
diode optically coupled to a high gain photodetector IC.
The excellent performance over temperature results from
the inclusion of an integrated emitter-base bypass resistor
which shunts photodiode and first stage leakage currents
to ground. External access to the second stage base
provides better noise rejection than a conventional
photodarlington detector. An external resistor or capacitor at the base can be added to make a gain-bandwidth or
input current threshold adjustment. The base lead can
also be used for feedback.

Low Input Power

Absolute Maximum Ratings*
Storage Temperature . . . . . . . . . . . . . .. -55° C to +125° C
Operating Temperature ............. -40°C to +70°C
Lead Solder Temperature .............. 260° C for 10 s.
(1.6mm below seating plane)
AveragelnputCurrent-IF ................. 20mA[1]
Peak Input Current -IF . . . . . . . . . . . . . . . . . . . . . . 40 mA
(50% duty cycle, 1ms pulse width)
Peak Transient Input Current -IF ............... 1.0A
(0;; 1 iJs pulse width, 300pps)
Reverse Input Voltage - VR ....................... 5V
Input Power Dissipation .................... 35mW[2]
Output Current -10 (pin 5) ................. 60 mA[3]
Emitter-Base Reverse Voltage (Pins 4-6) ...... . .. 0.5V
Output Voltage - Vo (Pin 5-4)
4N45 ................................... -0.5 to 7V
4N46 .................................. -0.5t020V
Output Power Dissipation ................. 100mW[4]

The high current transfer ratio at very low input currents
permits circuit designs in which adequate margin can be
allowed for the effects of CTR degradation over t:me.
The 4N46 has a 350% minimum CTR at an input current of
only 0.5mA making it ideal for use in low input current
applications such as MOS, CMOS and low power logic
interfacing. Compatibility with high voltage CMOS logic
systems is assured by the 20V minimum breakdown
voltage of the output transistor and by the guaranteed
maximum output leakage (IOH) at 18V.
The 4N45 has a 250% minimum CTR at 1.0mA input
current and a 7V minimum breakdown voltage rating.

See notes. following page

"JEDEC Registered Data.

80

Electrical Specifications
OVER RECOMMENDED TEMPERATURE (TA = O°C TO 70°CI. UNLESS OTHERWISE SPECIFIED

Switching Specifications
ATTA = 25°C

~

I

I.

"JEDEC Registered Data.
""All typicals at TA = 25°C, unless otherwise noted.
NOTES:
Derate linearly above 50° C free-air temperature at a rate of O.4mAf C.
2. Derate linearly above 50° C free-air temperature at a rate of 0.7mWfC.
3. Derate linearly above 25° C free-air temperature at a rate of O.amAf C.
4. Derate linearly above 25° C free-a ir temperature at a rate of 1.5mWf C.
5. DC CURRENT TRANSFER RATIO is defined as the ratio of output collector current, 10, to the forward LED input current, IF, times
100%.
6. Pin 6 Open.
7. Device considered a two-terminal device: Pins 1,2,3 shorted together and Pins 4, 5, and 6 shorted together.
a. Use of a resistor between pin 4 and 6 will decrease gain and delay time. (See Figures 10 and 12).
9. Common mode transient immunity in Logic High level is the maximum tolerable (positive) dVcm/dt on the leading edge of the common
mode pulse, Vcm , to assure that the output will remain in a Logic High state (i.e., Va> 2.5V). Common mode transient immunity in
Logic Low level is the maximum tolerable (negative) dVcm/dt on the trailing edge of the common mode pulse signal, Vcm , to assure
that the output will remain in a Logic Low state (i.e., Va < 2.5V).

i.

81

VF - FORWARD VOLTAGE - V

Vo - OUTPUT VOLTAGE - V

Figure 1. Input Diode Forward Current
Forward Voltage.

VS.

IF - FORWARD CURRENT - rnA

Figure 2. Typical DC Transfer
Characteristics.

Figure 3. Output Current vs. Input
Current.

,

~

~c
z

c

r--C..-+f-±-'-'!t-1=:::±:=T•• 70"C

i..

TA '"'25°(:

r--JH-J'-+---'............c:±= TA #-GOC

TA."'--4O"C

5

10

20

,

1·~50L--_2.1.:5c---'--l25'---50'--'-'7:"'·"'-.c.,..Joo

50 100

IF - FORWARD CURRENT - rnA

TA - TEMPERATURE _ °C

IF - FORWARD CURRENT - rnA

Figure 4. Currant Transfer Ratio vs.
Input Current.

Figure 5. Propegation Delay vs. Forward
Current.

Figure 6. Propagation Delay vs.
Temperature.

,.....---

"

o---~

I

VO---]' •2.-5V ---VOL

'PHJ

"----.,,
o

f=-

,

!-,- - - -

,,
,,,
,

RL - LOAD RESISTOR - kn

Figure 7. Propegation Delay vs load
Resistor.

Figure 8. Switching Test Circuit

~~1'::9::':0%:"""-''_-_,on,
'
Vo

Va ----""~;;;-------- 5V
SWITCH AT A: IF= OmA

Va -----------~VOL

HPl900A
PULSE GEN.

SWITCH AT B: IF = 1.0 rnA

Figure 9. Test Circuit for Transient Immunity and Typical Waveforms.

82

10.000

;,
I

> '000

:l
...
0

z

Q

l

~
g;

'00

I

'0

0

I>

Figure 10. External Ba.
Resistor. RX

IF - FORWARD CURRENT - rnA

Rx - EXTERNAL RESISTOR - kn

Figure 11. Effect of R X On
Current Transfer Ratio

Figure 12. Effect of R X On
Propagation Dalay

Applications
75kn

TELEPHONE{
LINE

1N91.

<>--)~---f

Vo

D,' /JF

NOTE: AN INTEGRATOR MAY BE REQUIRED AT THE OUTPUT TO

ELIMINATE DIALING PULSES AND LINE TRANSIENTS.
·SCHMIDT TRIGGER RECOMMENDED
BECAUSE OF LONG tr. tt.

TTL Interface

Telaphone Ring Detector

v
Vee
RS

ADD FOR /
ACINPUT

Line Voltage Monitor

CMOS Interface
+Vee,

+Vcc,o----..... - - .

CHARACTER ISTICS
RIN "" 3OMn, ROUT"" son
VINtMAX,1 =

l---H~-oVOUT

Vcc,

-1V, LINEARITY BETTER THAN 5%

DESIGN COMMENTS
R, _ NOT CRITICAL

«<

VIN !MAX.) - (-Vcc,) - VBE)hFE Q3

'FIMAX.)
R2 - NOT CRITICAL (OMIT IF 0.2 TO O.3V OFFSET IS TOLERABLE)

R,>

V,N

VIN (MAX.I

+ VaE

'mA
VIN (MAX.I

R6>~

R,
6.8k
NOTE: ADJUST R3

so VOUT .. VIN AT VIN '" VIN (MAXJ
2

.vcc,
0,.02 - 2N3904
03 - 2N3906

Analog Signal Isolation

83

.,~;-'

"

AC/DC TO LOGIC
INTERFACE
,'OPTOCOUPLER

HEWLETT

(hpl PACKARD'

HCPL·3100

TECHNICAL DATA

SCHEMATIC

MARCH 1980

OUTLINE DRAWING

DC+ INPUT

1

Vee

~l:fi

Iec-

DC-INPUT

GND

Features

Applications

•
•
•
•
•
•

•
•
•
•
•
•
•

AC OR DC INPUT
PROGRAMMABLE SENSE VOLTAGE
HYSTERESIS
LOGIC COMPATIBLE OUTPUT
SMALL SIZE: STANDARD 8 PIN DIP
THRESHOLDS GUARANTEED OVER
TEMPERATURE
• THRESHOLDS INDEPENDENT OF
LED DEGRADATION
• 3000V WITHSTAND TEST VOLTAGE
• RECOGNIZED UNDER THE COMPONENT
PROGRAM OF UNDERWRITERS
LABORATORIES, INC. (FILE NO. E55361)

LIMIT SWITCH SENSING
LOW VOLTAGE DETECTOR
5V-240V AC/DC VOLTAGE SENSING
RELAY CONTACT MONITOR
RELAY COIL VOLTAGE MONITOR
CURRENT SENSING
MICROPROCESSOR INTERFACING
HCPL-3700

Description
The HCPL-3700 is a voltage/current threshold detection
optocoupler. This optocoupler uses an internal Light
Emitting Diode (LED). a threshold sensing input buffer IC.
and a high gain photon detector to provide an optocoupler
which permits adjustable external threshold levels. The
input buffer circuit has a nominal turn on threshold of
2.5 mA (ITH+) and 3.8 volts (VTH+). The addition of one or
more external attenuation resistors permits the use of this
device over a wide range of input voltages and currents.
Threshold sensing prior to the LED and detector elements
minimizes effects of different optical gain and LED
variations over operating life (CTR degradation). Hysteresis is also provided in the buffer for extra nOise immunity
and switching stability.

The buffer circuit is designed with internal clamping
diodes to protect the circuitry and LED from a wide range
of over-voltage and over-current transients while the
diode bridge enables easy use with ac voltage input.
The high gain output stage features an open collector
output providing both TTL compatible saturation voltages
and CMOS compatible breakdown voltages.
The HCPL-3700. by combining several unique functions
in a single package. provides the user with an ideal
component for industrial control computer input boards
and other applications where a predetermined input
threshold optocoupler level is desirable.

84

Absolute Maximum Ratings

[ -,

Lead

Soldering

(No derating required up to 70·C)

.......~__

~-.;...-.;...-.;...----.;...

Cycle

Recommended Operating Conditions
Parameter
Supply Voltage

Operating Temperature
Operating Frequency

Switching Characteristics

(

Parameter

at TA = 25·C. Vee = 5.0V

. Symbol

~ !~t~~~~~i~ ~ f;:: .

Propagation Delay Time to
Logic low Output Level

tpHl.

Propegation Delay Time to'
logic High Output Level

tPLH

Common MOde Transient
Immunity at Logic Low
Output Level

CML

Common MOde Transient
Immunity at Logic High
Output Level

CMHH.

"

y;

-,

,~.

Output Rise Time (10-900/0)

tr.

Output Fall Time (90-10%)

If

,

85

w;l~f~~~t;'~~:

Electrical Characteristics
Over Recommended Temperature (0· C:S; TA:S; 70°C) Unless Otherwise Specified

Parameter

Symbol

Min. Typ.' Max. Un",

ITH+

1.96

2.5

3.11

mA

ITH-

1.00

1.3

1.62

mA

Y,N = VTH- ; Vee = 4.5V;
Vo = 2,4V; 10H :s; 100 pA

'3.35

3.S

4.05

V

2.01

2.6

2.86

V

input Threshold Current

,

,

:

~

Fig. Note

Condition.
VIN=VTH+; Vee = 4.5V;
Vo == 0.4V; 10 ~ 4.2 mA

DC
(Pins 2, 3)

VIN = V2 - V3; Pins 1 &4 Open
Vee = 4.5V; Vo = 0.4V;
10~4.2 mA

14

=

VTH-

Y,N Vz -- Va; Pins 1 & 4 Open
Vec == 4.5V; VO'" 2.4V;

2,3

.input Threshold ,r,;.._ _ _-+__---lI--_-I-_-+-_-+_ _+-10:..-~...,.1-oo-.:...p-A_,_----___l
',Voltage
' '.
v,N==lv1-V41;Pins2&30pen
5.1
V
4.23
5.50
Vcc = 4.5V; Vo "" 0.4V;
VTH+
10;:':: 4.2 mA
AC
,,(Pins 1, 4)
Y,N =IV1-V4!; Pins2 &SOpen
4.24
2.87
3.8
V
Vce = 4.5V; Vo "" 2,4V;
VTH10:S; 100 pA
Hysteresis- '

IHYS

1.2

mA

VHYS

1,2

V

VHYS = VTH+ -

V,HCl V2 - Va; V3 = GND;
fiN = 10 mA; Pin 1 &4
Connected to Pin 3

IHYS .. ITH+ -

ITH-

14,15

2

VTH-

=

V,HCl

5,4

6.0

6.6

V

V,HC2

6.1

6.7

7.3

V

12.0

13.4

V

V,HC3 W; - Va GND;
liN = 15 mA; Pins1 & 4 Open

V

V,LC = V2 - V3; V3 = GND;
liN = -10 mA

=

Input Clamp VOlta~e

V,HC3

-0.76
'Input Current

liN

3.0

3.7

4,4

mA

V,HC2 = IV1 - V41; IliNI
10 mA; Pins 2 & 3 Open

=

=

VIN = V2 - Va == 5.0V;
Pins 1 & 4 Open

5

,
VDl,2
0.59
Bridge Diod.• ,Forward Voltaf;jef-...;;,.:..:;:..-I---f--+---+----i liN"" 3 mA (see schematic)
V03.4
0.74
LogiC LowOutp!JtVollage

VOL

Logic High~fpUt OUrrent

IOH

0.1

0,4

V

100

ICCl

1.0

leCH

2

4

11-0

Vee
VOH

=4.5V; IOl == 4.2 mA
= Vcc =l8V

mA

V2 - V3 = 5.0V; Vo = Open
Vcc =5.0V

nA

Vcc

pA

Relative Humidity == 45%,
TA = 25·C, VI-O = 3000 Vdc;
t =: 5 sec.

=18V; Vo == Open

Input-outPut"'$i'~nce

1012

n

V,-O -= 500 Vdc

Input-Output eapicltance '

0.6

pF

50

pF

f = 1 MHz, V,-O = 0 Vdc
1-1 MHz; V,N-OV, Pins 2 & 3,
Pins 1 & 4 Open

Input CapaCitance

CIN

Notes:
1. Measured at a point 1,6 mm below seating plane.
2. Current int%ut of any single lead.
3. Surge input current duration is a ms at 120 Hz pulse repetition rate.
Transient input current duration is 10 pS at 120 Hz pulse repetition rate.
Note that maximum input power, P,N. must be observed.
4. Derate linearly above 70· C free-air temperature at a rate of 4.1 mW/· C.
Maximum input power dissipation of 230 mW allows an input IC
junction'temperature of 125· C at an ambienttemperature of TA = 70· C
with a typical thermal resistance from junction to ambient of 6JA, =
240 CIW. Excessive PIN and T J may result in Ie chip degradation.

5

4

14

14

16

5. Derate linearly above 70· C free-airtemperature at arate of 5.4 mW/· C.
6. Derate linearly above 70° C free-air temperature at a rate of 3.9 mW/o C.

•

Maximum output power diSSipation of 210 mW allows an output IC
junction temperature of 12S·C at an ambienttemperatureofTA=70· C
with a typical thermal resistance from junction to ambient of 6JAo =
26S·C/W.
7. Derate linearly above 70· C free-air temperature at a rate of 0.6 mAl· C.
8. Maximum operating frequency is defined when output waveform (Pin
6) obtains only 90% of Vee with RL = 4.7 kil. CL = 30 pF using a SV
square wave input signal.

0

86

r
l

13. In applications where dVeM/dl may exceed 50,000 V/~s (such as static
discharge), a series resistor, Rce, should be included to protect the
detector Ie from destructively high surge currents. The recommended
value for Aee is 2400 per volt of allowable drop in Vee (between Pin B
and Vee) with a minimum value of 2400.
14. Logic low output level at Pin 6 occurs under the conditions of VIN ;:::
VTH+ as well as the range of VIN > VTH- once VIN has exceeded VTH+.
Logic high output level at Pin 6 occurs under the conditions of VIN:5
VTH- as well as the range of VIN < VTH+ once VIN has decreased below

9. All typical values are at TA = 25° C, Vee = S.OV unless otherwise stated.
10. The tPHL propagation delay is measured from the 2.5V level of the
leading edge of a 5.0V input pulse (1 ~s rise time) to the 1.5V level on the
leading edge of the output pulse (see Figure 9).
". The tPLH propagation delay is measured from the 2.5V level of the
trailing edge of a 5.0V input pulse (1 ~s fall time) to the 1.5V level on the
trailing edge of the output pulse (see Figure 9).
12. Common mode transient immunity in Logic High level isthe maximum
tolerable (positive) dVCM/dt on the leading edge of the common mode
pulse, VCM, to insure that the output will remain in a Logic High state
(Le., Vo > 2.0V). Common mode transient immunity in Logic Low level
is the maximum tolerable (negative) dVCM/dt on the trailing edge 01 the
common mode pulse signal, VCM. to insure that the output will remain
in a Logic Low state (i.e., Vo < O.BV). See Figure 10.

60

I

55

. TAl"

2~'C

t-

50

"
E
I

....

a:
u

'...."

30

~

20

~

15

15a:
~

I

>

,

45

40

VTH-.

15. AC Yoltage is instantaneous Yoltage.
16. Device considered a two terminal device: pins 1, 2, 3, 4 connected
together, and Pins 5, 6, 7, B connected together.

I
w

!

35

25

DC

ri'V

I-

CONNECTED
TOGETHER;

I

o

~

1

2

3

4

5

tft

3~~N)

-r-r

I

6

7

8

9

fTH (AelOC)

VOH

'"oI
~

o.

!

\irK IAC1
i

i!:

Ii·

DC (PINS 2. 3 --I:'~
f'

VTK (DC)

5

'~PINS1&

"'

10

~

§!

ACIPINS1.41--+2
,3 I-- i,
'
OPENI

:
r

PINS3.4

_.... CONNECTED
TOGETHER ..

"'

,I
:::-:

TH_

10 11 12 13

VIN -INPUT VOLTAGE - V

Figure 1. Typic.1 I nput Characteristics, liN vs. VIN'

4.2

i

4.0

>

3.8

90

3.6

:\lrH'1

!l

~a:

"....
"
:;"
w

0

>
I

~

>

!

I

I

'+-

I

I

I
, I

:

, ITH+

3.4
3.2

~-

I

3.0

i
I

I

r- ~ 1.
2.6
2.8

2.4

I-- --LIT~_

2.2

I
I

2.0
1.8

-20

!

I

I

-,--

i

I
I--

I

20

40

TA - TEMPERATURE -

60

I

80

1()O

3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8

"
E

1.4

u

7~

§

'CCtt

Vee -ltv
,,-Vo -OPEN

"ffla:
"........

1.6

::

1

I

90

15a:

1.2
I

Figure 2. Typical Transfer Characteristics.

::

liN -OmA

L

./

~/ V

"''"
I

~

~
~

1.0
10-5

0.8

-25

ac

25

Figure 3. Typical DC Threshold Levels vs. Temperature.

75

50

TA - TEMPERATURE _

100

°c

Figure 4. Typical High Level Supply Current, ICCH vs. Temperature.

87

4.2

240

4.0

220

..

180

f-

160

E
I

iii

It
It

~

I
200 w

!'l.

";:!-'

I

~
w

g

C
2

" 140 ~

3.2

:J

120

~

100

CJ
f-

~
I

80

o

5

I

~
>
w

-'
60 ;:

~

I

0

40

-'
I

J>

I
-20

20

40

60

80

TA - TEMPERATURE -'C

TA - TEMPERATURE _ °C

Figure 5. Typical Input Current, liN, and Low Level Output
Voltage, VOL, vs. Temperature.

Figure 6. Typical Propagation Delay vs. Temperature.

~

5000

I

>

I-

I

:0

..

30

I
.>

20

w

Rt -4.1kO

300

..

~

CM~

a:
~ 2000

I
I

2

-'

~

it

iii

c

200 I

0
:0

'"

z

o

1000

8

500

:0
:0
I

~
TA - TEMPERATURE _

I I

°c

00

,

CMH

\leo

I I

liN -OmA

I I

RL -4.7kO
TA lit 25~C

I
400

!

I

,

!

i
i
! I "l I

I
800

I

I

-S.w

1IoH-21JV

I
11
It

;

I

~ 3000

w

w

Vot. - \UV

," =25'C

I-

:0

;:

4000

:;
~

:;,

I I
i !

tee 15.;

I", -3.11mA

~

1200

1600

2000

VCM - COMMON MODE TRANSI ENT AMPLITUDE - V

Figure 7. Typical Rise, Fall Times vs. Temperature.

Figure 8. Common Mode Transient Immunity vs. Common
Mode Transient Amplitude.

+5V

HCPL-3700

RCC*

PULSE
GENERATOR

1---1I---~;--O

ttP-8OO7B

Vo

1--1-----;--0 Vo

Zo-son

V,N
PULSE AMPLITUDE· 5.0V
PULSE WIDTH'" 1 ms
f= 100 Hz
t, '" t1 '" 1.0ps (10-90%)

-=

PULSE GENERATOR

* CL

** CL IS 30 pF. WlilCH

IS 30 pF, WHICH INCLUDES PROBE

AND STRAY WIRING CAPACITANCE.

* SEE NOTE 13
INCLUDES PROBE

AND STRAY WIRING CAPACITANCE.

r-----------~------5V

INPUT
V,N

----- - - - -

----- 2.5V
OV

.....=---VOH
OUTPUT
Vo

~

~rS---------5V
v ----VOMIN
___
_

Vo

SWITCH AT A,
liN '" OmA

Vo

~SW~'T~C~H~A~T~B-,---~I~

-+----1.5V

VOMAX -

~~~~~~~~~~~----VOL

"

-

-

-/\

'------VOL CMl

liN"" 3.11 rnA

Figure 9. Switching Test Circuit.

Figure 10. Test Circuit for Common Mode Transient
Immunity and Typical Waveforms.

88

CMH

Electrical Considerations

[-

Rx

,.,.,

(

I
V+,(AC)

"'



90

250

l- t-- /-

200

II

a:

...-'

150

and

iliAC VOLTAGE li~NS;A';;:~~NEOUS VALUEI

100

'I

j

Conversely, if the denominator of equation (2) is negative,
then
and

80

120

ITH+
-ITH_

>

VTH_ (V+) - VTH+ (V_ )
Rx = ITH+ (VTH_) - ITH_ (VTH+)

VTH_ (V+).- VTH+ (V_ )
Rp = ITH+ (V_ - VTH_ ) + ITH_ (VTH+ _ V+)

\j -

+

-cof
'i j'

160

200

Ii
y'

0

'TH_ "'-1.3mA

40

ITH+
< -ITH_

I - t--

,;

,

(1 )

For two specifically selected external threshold voltage
levels, V+ and V-, the use of Rx and Rp will permit this
selection via equations (2), (3) provided the following
conditions are met. If the denominator of equation (2) is
positive, then

0

;:;

IE...

(-)

1

tl'VTH •• 3.BV} DC' PINS 2 3
liTH.· 2.•V r ·
j
'/ IiTH"6.1V}AC,PINSI4
If
'/
VTH -3av
50 --,~ _ _ . _ITH.- ·2.5mA

,

I·'

Figure 12, External Threshold Voltage Level Selection.

Rx can provide over-current transient protection by
limiting input current during a transient condition. For
monitoring contacts of a relay or switch, the HCPL-3700 in
combination with Rx and Rp can be used to allow a specific
current to be conducted through the contacts for cleaning
purposes (wetting current).

I

HCPL-3700

ITH+

The HCPL-3700 optocoupler has internal temperature
compensated, predictable voltage and current threshold
points which allow selection of an external resistor, Rx, to
determine larger external threshold voltage levels. For a
desired external threshold voltage, V±, a corresponding
typical value of Rx can be obtained from Figure 11.
Specific calculation of Rx can be obtained from Equation
(1) of Figure 12. Specification of both V+ and V- voltage
threshold levels simultaneously can be obtained by the
use of Rx and Rp as shown in Figure 12 and determined by
Equations (2) and (3).

240

RX - EXTERNAL SERIES RESISTOR -ld1

Figure 11. Typical External Threshold Characteristic, V± vs. Rx.

89

-:

(2)

(3)

6

IF2

~:~*?
· NOTE:

A .01 TO O.lj.!F BYPASS CAPACITOR MUST BE
CONNECTED BETWEEN PINS 15 AND 10.

10
'-----~~-__O GND

Features
• HERMETICALLY SEALED
• HIGH SPEED
• PERFORMANCE GUARANTEED OVER -55°C TO
+125°C AMBIENT TEMPERATURE RANGE
• STANDARD HIGH RELIABILITY SCREENED
PARTS AVAILABLE
• TTL COMPATIBLE INPUT AND OUTPUT
• HIGH COMMON MODE REJECTION
• DUAL-IN-LiNE PACKAGE
• 1500 VDC WITHSTAND TEST VOLTAGE
• EIA REGISTRATION
• HIGH RADIATION IMMUNITY

:iL.;bH.~ ;,,~~~~,
,,-

.~.

."

;-.

/

'< • of

,

~

:-':.,

,

':. ,

:.,'

~',

'"

'.'

.. :.
"

•• ,,-'~ I" -.. .'

.• '--_ _ _

I~.

:O~f~M"L~iMrnI£sANDi~: ...

Recommended Operating
Conditions
TABLE I

Applications
•
•
•
•
•
•

Logic Ground Isolation
Line Receiver
Computer - Peripheral Interface
Vehicle Command/Control Isolation
High Reliability Systems
System Test Equipment Isolation

Absolute Maximum Ratings·

Description

(No derating required up to 125°C)
Storage Temperature ................. -65°C to +l50°C
Operating Temperature ............... -55°C to +125°C
Lead Solder Temperature . . . . . . . . . . . . . . .. 260°C for lOs
(1.6rnrn below seating plane)
Peak Forward Input
Current (each channel) ....... 40 rnA (';;; 1 ms Duration)
Average Input Forward Current (each channel) ..... 20 rnA
Input Power Dissipation (each channel) ........... 35 rnW
Reverse Input Voltage (each channel) . . . . . . . . . . . . . . .. 5V
Supply Voltage - Vee ........... 7V (1 minute maximum)
Output Current - 10 (each channel) ... . . . . . . . . . .. 25 rnA
Output Power Dissipation (each channel) . . . . . . . . .. 40 rnW
Output Voltage - Vo (each channel) . . . . . . . . . . . . . . . .. 7V
Total Power Dissipation (both channels) ......... 350 mW

The 6N 134 consists of a pair of inverting optically coupled
gates, each with a light emitting diode and a unique high gain
integrated photon detector in a hermetically sealed ceramic
package. The output of the detector is an open collector
Schottky clamped transistor.
This unique dual coupler design provides maximum DC and
AC circuit isolation between each input and output while
achieving TTL circuit compatibility. The isolator operational
parameters are guaranteed from -55°C to +125°C, such that a
minimum input current of 10 rnA in each channel will sink a
six gate fanout (10 rnA) at the output with 4.5 to 5.5 V Vee
applied to the detector. This isolation and coupling is achieved
with a typical propagation delay of 55 nsec.
*JEDEC Registered Data.

··12.5mA condition permits at least 20% CTR degradation guardband.
Initial· switching threshold is 10mAor less.

90

TABLE II

Electrical Characteristics
OVER RECOMMENDED TEMPERATURE (TA

= -55°C TO +125°C)

UNLESS OTHERWISE NOTED

[

"AII typical values are at Vee = 5V, TA = 25°e

TABLE III

Typical Characteristics

AT TA = 25°C, Vee = 5V

Sywnbol'

EACH CHANNEL
. figure

Typ.

Note

InputCapaeltanee.

1.

. Input Diode T&n:IPefa'tUre

.-1.9

. Coefficiant:·.,. :
."

r

Capacitin(ie'(lnputo-Output)

Input-::lowilnsqliiil(lO' ..
. LeillcilgeCurterit
.

.'

......

1012

~,.'J

0.5

3
4

11)12.

4

1.7

,0.56
Output Ris&:Fall Time
(11)-90')(,)

4

35

.

Common Mode

10Q

Transiant I!\'IrntJrlity
at Hii:IJ Ot.rqwt lev.el

CommQo:MocIe

','-,

.,;'>'·VCNi"'1Ov (peak);'

.. ' ,/AtC) itnaX.) ,;,O.8V

6

8

.... : R.......'5100,IF ".1OmA

NOTES:
1. Each channel.

6.

2. Measured between pins 1 through 8 shorted together and pins 9

~hee 1!~)j\~:;~:9::I:e ~~I:~t I~u'r::':t.~ f:~~ :~n~'~~!~f~~~I~~

edge of the output pu Iss.

through 16 shorted together.

7. CMH is the max. tolerable common mode transient to assure that

3. Measured between pins 1 and 2 or 5 and 6 shorted together, and

pins 9 through 16 shorted together.

the output will remain in a high logic state (i.e., Vo

4. Measured between pins 1 and 2 shorted together, and pins 5 and 6

> 2.0V).
< O.8V).

8. CML is the max. tolerable common mode transient to assure that

shorted together.

the output will remain in a low logic state (i.e., Va

5. JhheB t~:IrM::=9~ii~e ~~I:~t i~ui.:a:r~~ ~.5~ ~o~n~~~:.~~::~i~;

9. It is essential that a bypass capacitor (.01 to 0.1"F, ceramic) be con·
nected from pin 10to pin 15. Total lead length between both ends of
the capacitor and the isolatol)pins should not exceed 20mm (Fig. 7).

edge of the outPut pulse.

'JEDEC Registered Data.

7

-

V/p.s;

-400

Transient Immunity
at LoW Ou1Ptit level

6

91

100

.

E

I

I

10

....

iiicr
cr

""c
cr

.
cr

i .·

;!;

I

~ 0.01

*

1.0

Vo

1.8

'.6

.01 ).IF

GN-e

BYPASS

"

Tel"

10

~

9

CL is approximately 15 pF, which includes
probe and stray wiring capacitance.

J-----\---

~--

',~PUT

,..

1.2

Rl

13
'2

S

I

5V

15

,.

.f::»

7

I

0.001

vee,

5~~

MONITORING !
NODE
47H

....

~

,.

"".......V
"'-",

3

tR ",50S

I

0.1

Z

2

I

;:

~

HP 8001a

ZO"50H

INPUT

"

1.0

h

GENERATOR

TA -25°C

-----,

~1

PULSe

IF"13mA

IF···5mA

- I tpHL 1-I tplH t--~VOH
~~TPUT
l.5V

2.0

VF' INPUT FORWARD VOLTAGE· V

1 _______ I _____

- - - - - VOL

Figure 1. Input Diode Forward Characteristic

Figure 2. Test Circuit for tPHL and tPLH*

,
IF~

100

AC • S10n .!..RL -4kn

-- ....K...-.
~-

~

>

~c

60

'- --

><: ..... -...

0
j::

'~"

~

•0

g:

tl'<."

8

10

,.

12

"'t-

~-

1I

~

•

>

3

I

:?

IF - PULSE INPUT CURRENT mA

TA."'250'C_

"\ '\\
\\

R,

5100

\~ /~~~~'i

,
0

"::'

vee" S,OV

2

~

0

20

Vo

01.u F

BYPASS

9

5

I

~

Rl

~

8

•

>

tPHL.

18

'5V

'5

"

GND

7

~
16

'-

,.
,.

6

0

•

..

Vee

:~'lf::» ;:

20

0

!Z~

3

-'....- - H'

r-..... :--

z

.

TA _25°C

----

Vee =sv
80

2

.

J/\

\.

0

2

•

8

IF - INPUT DIODE FORWARD CURRENT

Figure 3. Propagation Delay. tPHL and tPLH
ys. Pulse Input Current. IFH

'0
mA

12

Figure 4. Input-Output Characteristics
/.
y

'Z

2
120

VCC-SV'

IF,""13mA

~

100

>-

~

0

z

..
0
j::

'"

/

80

60

V ...k'

I

;t

..-('

0

g:

V

40

IF!

4"

/

'PH.

V

~

3

/

R.Li Ston

16

tpLH

'5V

15

.... ,.

11:+

:~-:/t> ;:
6

.01 "F

BYPASS

Va

"

GNO

7

8

'0
9

VeM

HP 1900A
PULSE GEN.

lOV - - - - -

20

;:.C

"::'

VCM
OV
0
-40

-20

0

20

.0

60

TA - TEMPERATURE

80

100

Va

"c

va

Figure 5. Propagation Delay vs. Temperature
'JEDEC Registered Data,

IF = 0

5V

120

Vo (min.)
Vo (max.)
.5V

1\

IF"'10mA

Figure 6. Typical Common Mode Rejection CharacteristiCS/Circuit

92

High Reliability Test Program
Hewlett Packard provides standard high reliability test programs, patterned after MI L-M-3851 O.
• The TXV suffix identifies a part which has been preconditioned and screened per Table IV .
• The TXVB suffix identifies a part which has been preconditioned and screened per Table IV, and comes from a lot
which has been subjected to the Group B tests detailed in
Table V.
Part Number System

'l'lthTX
.·,$M.e'ning
: f'lusGrollp B
.6N134TXVB

Figure 7. Recommended Circuit Board Lavout.

TABLE IV TXV Preconditioning and Screening -100%

Pre:Cap \ji...al.ln~tlon" .•.. .......:' •...;~;~::t
Electriclol 1':~: jqHiNOi,lcc~lcc~~t~
High. remp,",.wr"~tQr~/'; .' " . / ' ,··).i; \:~~;c.,

Tempsrature Cydlng'.

,.y,"

:.Conditlon 8 . ,,'" , .. '
·,.,PerTeDls 1I,1'A= 25"C
':;·\168 hy&. @l1s(f·C .
:'-65"C to +l50~C
>..'ilSG, y 1

<'~";"':;:)

~~~t~::;e$tY;';<;?;~"'? ";;;~.
GroSl Leak TeS! .
Electrical Test:

.';.";

)\ .Test Cond. A

;:,'

~;TIIli):Cond.C

VoL'

.

.

.. ,> ....

';\Par Table II ;TA~:2" (;.

;.

;~ hrs., TA =126"·9,

Burn-In

VCC"'S;5V, IF..13mA, IO~25mA

10.
11;
12
13.
14.

15.

Electrical Test:, Sam&as S~p2
Evaluate Drift
. .".' . : . . . ,
' .,,,.
Sample Elect,icalTest:.10Hl:VoL,;lcCH; leti.:
Sample Electriclll 'rest: IO'Hi;\lOl.>ICCH,lCCL:.;
Sample Electrical Test.: tI>LH;'PH(
.
Extarnal Visual
. . . ' - .. .

,

."

.

•. Max. AVOL~ ±2O'l(,. , ..•. .
. PorTable II, LTPD =' 7, TA"-55"C
~Table II,LTPO = 7, TA "''':125"C.
!"arTable II,TA" 25"C, LTPD" 7 .

'?

TABLE V, GROUP B
Examination or TeS!

(

LTPD

SubgrOIlP 1
Physical Oimensions
$ubgl"oup2
Solderabilitv

15

. Subgrdup3
.' Tempenlture Cyclii1g.
Thermal ShOek '.. :.,.' •
Herm(ltill Seal; Fine Leak
Hermetic seal; Gross 'teak

15

Subgroup 4
ShOck, non-operatiog

Constant Acceleration'

15

...

E'nd pomts:. Same as Subgra;.up3 ' •.
SubgroupS
. .
.
Terminal Strength,'tanslon ',.>
"1
Subgrqup 6 ' ... ' .. . . » ,
HighTernparatur,~ife\ ...•..
Enll POints: Same.~s SubgrouP 3
Subgroup 7 '
•..•... ::'" :
Stlllldy S15te.Operatin,g LWe
End P<;>lnts: Same as SUbgroup. 3

15

/>

. X=7.

X=7

93

¥?~;,;:;yC'

;~,:~i~:;:

, '... .. . . . .•

HERMETICALLY SEALED,
FOUR CHANNEL,
LOW INPUT CURRENT
OPTOCOUPLER

'

6N140
6N140 TXV
6N140 TXVB

TECHNICAL DATA

:3D
; *---5 -: ; -*----'"

OATECOOE

-::J

CTYPE h

MARCH 1980

v, VBI

hp XXXXYV

.1'.

6N140

I

"

PIN 1 H1ENTIFIER

,6

'"

..

~

12

..----+-+....c:.--<>V03

'4

7D
-8V~
---

,.
DIMENSlONS IN MILLIMETERS

AND (INCHES).
10
'--+---+----oGNO

Outline Drawing"

Schematic

Features

Description

• HERMETICALLY SEALED
• HIGH DENSITY PACKAGING
• HIGH CURRENT TRANSFER RATIO: 500%
TYPICAL
• CTR AND IOH GUARANTEED OVER -55°C
TO 100°C AMBIENT TEMPERATURE RANGE
• STANDARD HIGH RELIABILITY SCREENED
PARTS AVAILABLE
• 1500 Vdc WITHSTAND TEST VOLTAGE
• LOW INPUT CURRENT REQUIREMENT: 0.5 mA
• LOW OUTPUT SATURATION VOLTAGE: 0.1V
TYPICAL
• LOW POWER CONSUMPTION
• HIGH RADIATION IMMUNITY

The 6N140 contains four GaAsP light emitting diodes,
each of which is optically coupled to a corresponding
integrated high gain photon detector. A common pin for
the photodiodes and first stage of each detector IC (Vce)
permits lower output saturation voltage and higher speed
operation than possible with conventional photodarlington type optocouplers. Also, the separate Vee pin
can be strobed low as an output disable or operated with
supply voltages as low as 2.0V without adversely affecting
the parametric performance.
The outstanding high temperature performance of this
split Darlington type output amplifier results from the
inclusion of an integrated emitter-base bypass resistor
which shunts photodiode and first stage leakage currents
to ground.
The high current transfer ratio at very low input currents
permits circuit designs in which adequate margin can be
allowed for the effects of CTR degradation over time.

Applications
•
•
•
•
•
•
•
•
•

The 6N140 has a 300% minimum CTR at an input current
of only O.SmA making it ideal for use in low input current
applications such as MOS, CMOS and low power logic
interfacing or RS-232C data transmission systems.
Compatibility with high voltage CMOS logiC systems is
assured by the 18V Vee and by the guaranteed maximum
output leakage (IOH) at 18V.

Isolated Input Line Receiver
System Test Equipment Isolation
Digital Logic Ground Isolation
Vehicle Command/Control Isolation
EIA RS-232C Line Receiver
Microprocessor System Interface
Current Loop Receiver
Level Shifting
Process Control Input/Output Isolation

Important specifications such as CTR, leakage current,
supply current and output saturation voltage are
guaranteed over the -SsoC to 100°C temperature range to
allow trouble free system operation.

*JEDEC Registered Data.

94

L

Absolute Maximum Ratings*

TABLE I

Recommended operating
Conditions
Symbol
Input Current, Low Level
(Each Channell

IFL

Input Current, High Level
(Each Channel)

IFH

Supply Voltage

Vee

Min.

Max.

Unl1s

2

p,A

0,5

5

mA

2.0

18

V

Storage Temperature ............... -65°C to +150°C
Operating Temperature ............. -55° C to +1 OO°C
Lead Solder Temperature .............. 260°C for 105.
(1.6mm below seating plane)
Output Current, 10 (each channel) ............. 40 mA
Output Voltage, Vo (each channel)
-0.5 to 20 V[1]
Supply Voltage, VCC ................... -0.5 to 20 V[1]
Output Power Dissipation (each channel)
50 mW[2]
Peak Input Current (each channel,
~lmsduration) ............................ 20mA
Average Input Current, IF (each channel) ..... 10 mA[3]
Reverse Input Voltage, VR (each channel)
5V

TABLE II.

Electrical Characteristics
Parameter

Symbol

TA = -55°C to 10QoC, Unless Otherwise Specified

Min. Typ. Max. Units
Te.. Conditions
IF=O.5mA, Vo=0.4V, Vcc-4.5V
%
300 1000
300 750
%
IF=1.6mA, Vo=OAV. Vcc"'4.5V
200 400
%
Ip"SmA, Vo=OAV, Vcc=4.5V
.4
.1
V
IF.SmA, IOL=1.SmA, Vcc=4.5V
.2
V
IFSmA, IOL=10mA, Vcc"'4.SV
.4
IF-.2,uA
.005 250 /loA
Vo=Vec=18V
IF1-IF2-IF3-IF4-1.6mA
4
2
mA
Vee"'18V

Current Transfer Ratio

CTR'

Logic Low Output Voltage

VOL

Logic High Output Current

10H'

LogIc Low Supply Current

lecL'

Logic High Supply Current

lecH'

.010

40

/,A

Input Forward Voltage
Input Reverse Breakdown
Voltage
Input-Output Insulation
Leakage Current
Propagation Delay Time
To Logic High At Output

VF'

1.4

1.7

V

Vec=18V
IF=LElmA, TA'72S·C

V

IfI=10p,A. T A",2So C

tI'LH'

Propagation Delay Time
To Logic Low At Output

tPHL'

Common Mode Transient
Immunity At Logic High
Level Output
Common Mode Transient
Immunity At Logic Low
Level Output

eVR'

5

CMH

500

1000

V/p,s

CML

-500 -1000

V//ioS

IF=1.6mA, RL=1.5kO
IVCM!=50Vp- p , Vcc=5.0V, TA=25°C

25
10
3S
2

1.0

/loA

SO
20
100
5

/loS
/loS
p,s

,,5

Note

3

4,5

2

4
4,6

IF1~lf2~IF3=IF4=0

45% Relative Humidity, TA""2SoC,
t=5s., VI-o=l500 Vdc
IF-O.SmA, Rl=4.7kO, Vcc=5.0V, TA=2S"C
IF-5mA. RL=6800, Vcc-5.0V, TA=25°C
IF=0.5mA, Rl=4.7kO, Vcc=S.OV, TA'''2S"C
IF=SmA, Rl=680n, Vcc=5.0V, TA=2SoC
IF=O, RL"'1.5kn
IVCMI=50Vp- p, Vcc=S.OV, TA'=25·C

11-0'

Fig.

1

4

4
7
8
8

8
8
g

10,12

9

11,12

Fig.

NOle
4,8
4,8

TABLE III.

Typical Characteristics
Pilrameler
Resistance (Input-Outputl
Capacitance (Input-Outputj
Input-Input Insulation
Leakage Current
Resistance (Input-Input)
Capacitance I Input-Input)
Temperature Coefficient
of Forward Voltage
Input Capacitance

Symbol
RI-O
CI-O
II-I
RH
CI-I
AVF
ATA

CIN

T A = 25°C, Vce = 5V Each Channel
Test Conditions
Min. Typ. Max. Units
VI-O=500 Vdc, TA=2S"C
1012
n
1.5
pF
1=1 MHz, T A=2S" C
45% Relative Humidity, VI-I=500 Vdc,
0.5
nA
TA=2S"C, t=5s.
1012
n VI_I=500Vdc, TA-25°C
1
pF
f;IMHz, TA"'25"C
mVI
-1.8
IF=1.SmA
°C
60
pF
f=IMHz, VF=O, TA=2S·C

9
9
9

4
4

8. Measured between each input pair shorted together and all output
pins.
9. Measured between adjacent input pairs shorted together, i.e. between
pins 1 and 2 shorted together and pins 3 and 4 shorted together, etc.
10. CMH is ttle maximum tolerable common mode transient to assure that
the output will remain in a high logic state (i.e. Va> 2.0V).
11. CML is the maximum tolerable common mode transient to assure that
the output will remain in a low logic state (i.e. Va < O.8V).
12. In applications where dV/dt may exceed 50,000 V/jJ.s (suCh as astatic
discharge) a series resistor, Ree, should be included to protect the
detector IC's from destructive Iv high surge currents. The recommended value Is Ree "" __1_V_ kfl.
0.6 IF {mAl

NOTES: 1. Pin 10 should be the most negatIve vOltage at the detector side.
Keeping Vee as low as possible, but greater than 2.0 volts, will provide
lowest total IOH over temperature.
2. Output power is collector output power plus one fourth of total supply
power. Derate at 1.25 mW/"'C above eo°c.
3. Derate IF at 0.25 mArC above 80°C.
4. Each channel.
5. CURRENT TRANSFER RAno is defined as the ratio of output
collector current, 10, to the forward LED input current, IF, times 100%.
6. IF=2.uA for channel under test. For aU other channels, IF=10mA.
7. Device considered a two-terminal device: Pins 1 through 8 are shorted
together and pins 9 through 16 are shorted together.

*JEDEC Registered Data.

95

I .•

1.6

Vo -OUTPUTVOLTAGE-V

IF -INPUT DIODE FORWARD CURRENT - mA

Figure 2. Normalized DC Transfer
Characteristics.

Figure 3. Normalized Current Transfer
Ratio VI. Input Diode Forward
Current.

V F - FORWARD VOLTAGE - V

Figure 1. Input Diode Forward Current
Forward Voltage.

VI.

100

!!.,

120
I1D

~

,

!!.

"



9

~

0

e

l-

>

z

~

0

z

~
~,

~

e

~

~

~

,

IE

j.m 0.01
Figure 4. Normalized Supply Current VI.
Input Diode Forward Current.

T - INPUT PULSE PERIQD

,

40

i!i

~
"0of
IE

,

~

,.---------

---~

I

:5
e

°c

Figure 6. Propagation Delay VI.
Temperature

vo--- J1=-5V
1.5V

>

..

TA - TEMPERATURE -

-ITII

Figure 5. Propagation Delay to Logic Low
VI. Input Pulse Period.

"
!

100

I.

D.l

IF -INPUT DIODE FORWARD CURRENT - mA

30

20

',---

---,

¥~5V===Vo

D

lD

---VOL

'PHl

1.SV
---

IF -INPUT DIODE FORWARD CURRENT - mA

.

VOL

tpLH-

Figure 7. Propagation Delay VI. Input Diode
Forward Current.

Figure 8. SWitching Test Circuit.'
(f. tp not JEDEC registered)

2.4-VF

R2>-~-

VO

R1 '" VCC-VF-IFR2

~_~---------------6V

IF

SWITCH AT A: IF- OmA

+ ILEAl(

r-----...,
I
I
I

~ ,VOL

Vo - - - - - - - - - - - - - - - - - - -..

SWITCH AT B: If'" 1.6mA

-See Nota 12.

HP1900A

PULSE GEN.

Figure 9. Tesi Circuit for Transient Immunity and Typical Waveforms.
• JEDEC Registered Data.

96

~~I~ro~~~~~t~:
IS NOT USED.

~

I
I
I

:

_____ .J

Figure 10. Recommended drive circuitry
using TTL logic.

High Reliability Test Program
Hewlett Packard provides standard high reliability test
programs, patterned after MIL-M-38510 in order to
facilitate the use of HP products in military programs.
HP offers two levels of high reliability testing:
• The TXV suffix identifies a part which has been
preconditioned and screened per Table IV.
• The TXVB suffix identifies a part which has been
preconditioned and screened per Table IV, and comes
from a lot which has been subjected to the Group B
tests detailed in Table V.

Part Number System
" .>WII.It n(V•

$:r~ng

wabTXV'

1::0111"",'cia'

·s.:,~n~
6N14QtxV' '"

"'Product

.6111140

PlUsC,oup It
• 6N14(} TXVB

TABLE IV TXV Preconditioning and Screening - 100%
En mination or Test

t.

5.
6.
7.

Pre-Cap Visual.lnsp&ction
High Temperature StOrage
Temperature Cyoling
ACCeleration
Helium Leak Test
Gross Leak Test
Electrical Test CTR, fOH, ICCL.

8.

ICCH, VF. BVR;
Burn.ln

2.

3.
4.

.• 0 Eo-,~tocildure
,'lQ'

12~,7i..M:
72 hts.@I50"C'"

:65~Ctd,+ti;o~c.\

.'010
2001

5K:a~'1'1

Hn.¢'
10'14

"

. Cond.A
Cond:.C

TA" 25"C;pttrTa\:lle"

VcC""$~.IF,.,5!nA, 10 '" 10mA

101.5

t "'1.68h,s.@'TA "'100·C
9.
1 ().
11.

12.
13.

14.,

TA,~25·C.perTabtell

Electrical Test: same as step 7 and 1'.0
Evaluate Drift
Sample Electrical Test: CTR, 10H, ICCL, tCCH"
Sample Electrical Test: CTR, 'OH, fCCL, tCCH
Sample Electrical Test: tPHL, tPLH, CMH, eM..
External Visual

Mex. ACTR,,!±\l5%@IF":l.6rnA
Per Tatile 11, LTPO"?, TA = :-5S"C
perTabhi II, LTPD ".7;.TA'" +100°C

PerTatik! II~LTPD"7. TA~ 2SoC .
2009

TABLE V, Group B
MIL.sTO-883

Examination or Test

(
I

l

Condition

lTPO

Subgroup 1
Physical Dimensions

2016

See Product Outline Drawiog

16

Subgroup 2
Solderability

2003

Immersion within2.5mm of body.
16 terminations

20

1010

Test ConditioI'! C

15

lall

T est Condition A, S cycles
Test Condition A
Test .Condition C

Subgroup 3
Tempereture Cycling
Therl'fllli $hock
Hermetic Saal, Fine Leek

Hermetic Saal, Gross Leek

1014
10t4

End PoifltS:
CTR, IoH, ICCG 'CCHo VF, eVR
Subgroup 4
Shock; non-operating
Constant Acceleration
End Point.:
Same as Subgroup 3
Subgroup S
Terminal Strength, tension
Subgroup 6
High Temperature Life
End Points:
Safne as Subgroup 3
Subgroup 7
Steady State Operating Life
End PolfltS:
Sa
u
0

w

N

::;

i:ia:

0.5

I

"a:
~

/'

I-

:>
0

J:
OJ

u

m

a

16mA,

9
I

%

2

a:

I-

u

°0.1

1

10

0.1

i

TA.26'1

Z
I

1

:=:>

TA "" +125"C

NORMALIZED TO,

0

1
' " rAj I,

a:

~TA·.55"C

CTR AT IF

10

:>
u

~

I,' '25GpA,I,

1

I-

TA "" 25"'C

1.0

t'

I

'"z

"a:

100

""-

IIcc-5V
Vo -O.4V

0.01

r+

§

IF - INPUT DIODE FORWARD CURRENT - rnA

'DBcrr·:~
V

IF -" {OTHER CHANNELI-

I V ....

~/

~1'

0.001
-60 -40 -20

100

(rH~R C~AN~ELI i 20 j'A

Vj'Vrr
0

20

40

60

80 100 120 140

TA - TEMPERATURE _

°c

Figure 4. Logic High Output Current vs. Temperature.

Figure 3. Normalized Current Transfer Ratio vs. I nput Diode

Forward Current.

100

[

50

1,

...
~

a:
a:

"

$.~6SOC

45
40

!g
/

35

./

u

~

30

";:

25

g

20

u

15

it

V)

C5

g

,

TA -25'C
IF -16mA
-5

/

V....
~ "/

10

V
V

,

TA "'.$"C

w

~+12~'C

/

V)

z

~a:

I'"

00

-15

51

,/

N

:::;

""a:
z

-20

Cl

~~

~

II

-10

15

10

-30
.01

25

20

-25

0.1

IF - INPUT DIODE FORWARD CURRENT - rnA

10

1.0

f - FREQUENCY - MHz

Figure 5. Logic Low Supply Current vs. I nput Diode
Forward Current.
r-~t--<>+15V

+5V

o---~-----,

,-r----~--OVo

4.0
3.6

,

~

2.8

Cl

2.4

~

z

i=

"'"
"
~
IE,

~

=

/
tpLH/

>-

0

f-IF laml

Vcc""5V
3.2 I--RL =8.2kU

V
/'

2.0

./

... ......

1.6
1.2

Figure 8. frequency Response.

0.8

-

0.4

o

i--

-60 -40 -20

0

20

40

~

60

80 100 120 140

TA. - TEMPERATURE _

':--1,

°c

,
I

Figure 6. Propagation Delay vs. Temperature.

Vo

5V

1.5V

o

~

2.

~

1.8 - T . ='25'C
\10 • 2V

......a:"

1.4

a:
C/)

z

~
a:
a:

I. 6

c--'

1.0
0.8

"

0.6

Vee

I

'If;

5V

-

HP8007

f

GEN.

Zo=5Qn.

r-......

r-+--~~-~--<>+5V

tr"'5 os

l"'-

NORM{lllZED TO, _

t

1 iF -jl6m

51

NO.4

16

PULS~

--

1.2

"uj
~

I,

o

I

f--

IF MONITOR

:::;

""a:
~
I

~I~

0.2

o
o

10

15

20

25

IF - QUIESCENT INPUT CURRENT - mA

10"k DUTY CYCLE
l/f<;;; 100,(.(s

Figure 7. Normalized Small Signal Current Transfer Ratio vs.
Figure 9. Switching Test Circuit.

Quiescent Input Current.

101

tf.

VeM

= ans

Vee

~;;;_------- 5V

Vo
SWITCH AT A:

Vo

tf

IF'" OmA

------------~VOL

SWITCH AT B: IF=16mA

r------,,6

lOGIC GATE

lOGIC fAMilY
DEViCe NO.
Vee

'--+----0 Vo

=

'18kfl

a.2k!2j221d!

Ri.. 6%

TOLERANCE

50% DUTY CYCLE
l/f

5V

CMOS
C040106BM
5V 15V

lSTTL
54~S14

100ps
*THE eQUIVALENT OUTPUT LOAD RESISTANCE IS AFFECTED
BY THE LSTTL INPUT CURRENT AND IS APPROXIMATELY B.2kn.

A

VeM

~----~--~J1r'--~--,

This is a worst case design which takes into account 25%
degradation of CTR. See App. Note 1002 to assess actual
degradation and lifetime.

HP1900A
PULSE GEN.

Figure 10. Test Circuit for Transient Immunity and

Figure 11. Recommended Logic Interface.

Typical Waveforms.

High Reliability Test Program
Hewlett-Packard provides standard high reliability test
programs, patterned after MIL-M-38510.
• The TXV suffix identifies a part which has been
preconditioned and screened per Table IV.
• The TVXB suffix identifies a part which has been
preconditioned and screened per Table IV, and
comes from a lot which has been subjected to the
Group B tests detailed in Table V.

-

1

16 I-

-

2

15i---

3

14

270n

-

4

13

f----

-

5

12

t-

-

6

11

f---- f----

>-- 7

10

r--

a

9

200n

With TXV
Screening

With TXV
Screening
Plus Group B

4N55

4N55TXV

4N55TXVB

Vee
+3.5V

200n

Part Number System
Commercial
Product

Vee
+5.5V

-

5.5V~T

102

270n

....

TABLE IV. TXV PRECONDITIONING AND SCREENING - 100%
MIL·STO·883
Methods

Examination or Test

1.
2.

Pre-Cap Visual Inspection
High Temperature
3. Temperature Cycling
4. Acceleration
5. Helium Leak Test
6. Gross Leak Tes!
7. Electrical Test: CTR
8. Burn-In

Conditions

2010
1008
1010
2001
1014
1014

ConditionS
24 Hrs. @150"C
65"Cto+150·C
5kG, Yl
Test Condition A
Test Condition C
Per Table II, TA'"" 25° C
168 Hrs., TA'" 125°C
Vee = 5.5V, IF = 20mA¥ Vac= 3.5V
RL == 2700

1015

9. Electrical Test:
CTR, iOH, ICCL, ICCH, VF. BVA, It-a
10. Evaluate Drift
11. Sample Electrical Test:
IOH, ICCH, leeL, CTR, VF, BVA
12. Sample Electrical Test:
10H, ICCH, leCL, CTR, VF, BVR
13. Sample Electrical Test:
tPHL. tPLH
14. External Visual

Per Table II, TA "" 25"C
Max. ACTR "" ±20%
Per Table II, LTPD = 5, TA = -55'C
Per Table II, LTPD '" 5, T A"" +125" C
Per Table 11, TA

= 25° C,

LTPD

=5

2009

TABLE V. GROUP B
Examination or Test
Subgroup 1

MIL·STO·883
Condition

Method

LTPO

15
2016

See Product Outline Drawing

2003

Immersion within 2.5mm of body, 16
terminations

1010
1011
1014
1014

Test Condition C
Test Condition A
Test Condition A
Test Condition C
Per Table II. T A = 25' C

Shock, non-operating

2002

Constant Acceleration

2001

1500 G, t '" 0.5 ms, 5 blows in each orien.tatlon
Xl, Yl. Y2
5KG, Yl

2004

Test Condition A, 4.5N (1 lb.), 15s

1008

TA

1005

Vce = 5V, IF =: 20mA, TA = 125°C
Vec =: 3.5V. RL = 2700

Physical Dimensions

20

Subgroup 2

Solderability

15

Subgroup 3

Temperature cycling
Thermal Shock
Hermetic Seal, Fine Leak
Hermetic Seal, Gross Leak
End Points: IOH. CTR, ICCH. lecL. VF,
eVR, It-a

15

Subgroup 4

End Points: Same as Subgroup 3
Subgroup 5

Terminal Strength, tension

15

Subgroup 6

High Temperature Life
End Points: Same as Subgroup 3
Subgroup 7

Steady State Operating Life
End POints: Same as Subgroup 3

= 150'C

'A=7

A=7

103
________
.._..._................"""._,...
",....w,.,..,,...... ..,..,.+,
.,._••
,,,.,~

_~~_"~"...,.,.,,,,........~~

________________

~

, 'y,

':!,

104

o

C;>, ;'

.' ·.:'~'isra.tel..amps}iI . . . . .
'. Sel~tio~'GOide

. . • . . . . . • . . .. . .

';;,~·i';,;~.;::[:::.·:~,;i'"

.' • Red, High Effldency Red, Yellow'
and Green· Lamps
• Integrated Lamps.
• Hennetically Sealed lamps
• Panel Mounting Kit
,

,

,

,

,

105

.

'_"l'"
,~.

,)\

High Efficiency Red, Yellow, Green LED Lamps
Device
Package Outline Drawing

Description
Part No.

Color 12]

5082·4550

Yellow
(538 nm)

Package

T·l%i3]

Typical

Lens

Yellow
Diffused

5082·4555

Luminous
Intensity
1.8mOO@10mA

2El'h I1 ]

Typical
Aorward
Voltage

90°

2.2 Volts
@10mA

Page
No.

113

3.0mOO@10mA
Yellow
Non·Diffused

5082·4557

5082·4558

9.0 mOO @10mA

35°

16.0 mOO @10mA

f--;:=5082·4650

5082·4655

v

,

0

-

"01\

"'-'"

,

High
Efficiency
. Red
(635 nm)

Red
Diffused

4.0 moo @ 10mA
Red
12.0mOO@10mA
Non·D iff used

5082·4658

24.0 mcd @10mA

Green
(565 nm)

Green
Diffused

5082·4955

Green
Non·Diffused

5082·4958

5082·4590

I

35°

1.8 mOO @20mA
90°

2.4 Volts
@20mA

3.0 moo @20mA

5082·4957

I

90°

5082·4657

50.82·4950

(\

2.0 mOO @10mA

9.0 mOO @20mA

30°

16.0 mcd @20mA

Yellow
(538 nm)

T·l%
Low Profile

Yellow
Diffused

5082·4592

3.5 moo @ lOmA

50°

2.2 Volts
@10mA

117

6.0 moo @10mA

5082·4595

Yellow
Non·Diffused

5082·4597

6.5 mcd @10mA

45°

11.0mOO@10mA

\

I'

5082·4690

~~
~

,

~

5082·4990
~

I

/,

3.5 mcd@10mA

50°

7.0mOO@10mA

Red
Non·Diffused

5082·4695

0'

--""

Red
Diffused

5082·4694

... - ..... "

0

•

5082·4693

High
Efficiency
Red
(635 nm)

8.0mcd@10mA

45°

11.0mOO@10mA

Green
(565 nm)

Green
Diffused

5082·4992

4.5 mcd @20mA
50°
7.5mcd@20mA

5082·4995

Green

6.5 mOO @20mA

Non·Diffused
5082·4997

11.0mcd@20mA

See Page 111 for Note •.

106

40°

2.4 Volts
@20mA

High Efficiency Red, Yellow, Green LED Lamps (continued)
Device

Package Outline Drawing

r

r-.....

Description

Pa,t No.

HLMp·1300

f"-~-"

HLMp·1301

~

Colo,12]

High
Efficiency
Red
(635 nm)

Package

T·1 14]

Lens

Red
Diffused

e
~

c:::J

Yellow
Diffused

4.0 mcd @10mA

Green
(565 nm)

Green
Diffused

2.0 mcd @10mA

HLMp·1502

3.0 mod @10mA

HLMP-0400

High
Efficiency
Red
(635 nm)

Rectangular

Red
Diffused

Yellow
(583 nm)

Yellow
Diffused

Green

Green
Diffused

HLMP-0501

0

•

0 C
'.

~-'

)

~

~

2.4 Volts
@20mA

,

1.0 mod @25mA

2.5 Volts
@25mA

127

2.2 Volts
@10mA

131

1.2 mod@25mA
100°
2.5 mod @25mA

(565 nm)

r

60°

2.5 mod @25mA

HLMP-0401
HLMP-0500

123

70°

1.2mcd@10mA

HLMp·1501

HLMP·0301

2.2 Volts
@lOmA

Page
No.

1.5 mod@10mA

HLMP·1402

HLMP·0300

r-,-

Yellow
(583 nm)

2.5 mod @10mA

r--

Typical
Forward
Voltage

2.5 mcd@10mA

HLMp·1401

HLMp·1500

... -~

2El'h ll ]

1.5 mod@10mA
2.0 mod @10mA

HLMp·1302

HLMp·140()

Typical
Luminous
Intensity

1.2 mod @25mA
2.5 mcd @25mA

Yellow
Diffused

2.0 mcd @10mA

90°

High
Efficiency
Red
(635 nm)

Red
Diffused

3.0 mod@10mA

80°

Green
(565 nm)

Green
Diffused

1.5 mod @20mA

70°

5082-4150

Yellow
(583 nm)

5082-4160

5082-4190

Subminiature with
Radial Leads

See Page 111 for Notes.

107

2.4 Volts
@20mA

High Efficiency Red, Yellow, Green Light Bar Modules
Device

Package Outline Drawing

Part No.

HLMp·2300

I~I

Color[21

High
Efficiency

Red
(635 nm)

~
II· .. .

Description

~

100001
~

Red
Diffused

7mcd@20mA

Forward

Voltage

Intensity

(Not
Appli·
cable)

1.9 Volts
@20mA

Yellow
(538 nm)

Yellow
Diffused

5mcd@20mA

2.0 Volts
@20mA

HLMP·2500

Green
(565 nm)

Green

3.5 mcd @20mA

Diffused

2.1 Volts
@20mA

Red
Diffused

15 mcd@20mA

1.9 Volts
@20mA

HLMP·2350

DO

4 Pin In·Line; .100"
Centers; .400"L x
.195'W x .240"H

Lens

Typical
28',,1')

HLMp·2400

High
Efficiency

·11

-

Package

Typical
Luminous

Red
(635 nm)

8 Pin In·Line; .100"
Centers; .800"L x
.195'W x .240"H

HLMP·2450

Yellow
(538 nm)

Yellow
Diffused

11 mcd@20mA

2.0 Volts
@20mA

HLMp·2550

Green
(565 nm)

Green

7.5 mcd @20mA

Diffused

2.1 Volts
@20mA

Page
No.

135

r--HLMp·2600

High
Efficiency
Red
(635 nm)

8 Pin DIP; .100"
Centers; .400 L x
AOO'W x .240"H;

Red
Diffused

7 mcd@20mA

139

Dual Arrangement

HLMp·2700

Yellow
(538 nm)

Yellow
Diffused

5mcd@20mA

HLMp·2800

Green
(565 nm)

Green
Diffused

3.5 mcd @20mA

HLMP·2620

High
Efficiency
Red
(635 nm)

Red
Diffused

7 mcd@20mA

2.1 Volts
@20mA

2.2 Volts
@20mA

16 Pin DIP; .100"
Centers; .800" L x
.400'W x .240"H;

2.2 Volts
@20mA

Quad Arrangement

HLMp·2720

Yellow
(538 nm)

Yellow
Diffused

5mcd@20mA

HLMp·2820

Green
(565 nm)

Green
Diffused

3.5 mcd @20mA

See Page 111 for Notes.

108

High Efficiency Red, Yellow, Green Light Bar Modules (continued)
Device
Package Outline Drawing

(

Description
Part No.

HLMp·2635

B
I

Color[2]

High
Efficiency

Red
(635 nm)

I

~

D

Typical

Lens

Package

16 Pin DIP; .100"
Centers; .800"L x
.400''W x .240"H;

Red

Luminous

Typical
28',<,11)

14mcd@20mA

Diffused

Forward

Voltage

Intensity

(Not
App)i·
cable)

2.1 Vo)ts
@20mA

Dual Bar Arrange-

ment

HLMP·2735

Yellow
(538 nm)

Yellow
Diffused

HLMP·2835

Green

Green

(565 nm)

Diffused

HLMp·2655

High

Efficiency
Red
(635 nm)

8 Pin DIP; .100"
Centers; .400" L x
.400"W x .240"H;

10 mcd@20mA

2.2 Volts
@20mA

7 mcd@20mA

Red
Diffused

14mcd@20mA

2.1 Volts
@20mA

Yellow

10 mcd@20mA

2.2 Volts
@20mA

Square Arrange-

ment

~

HLMp·2755

IO[JI

HLMP·2670

D
-

HLMp·2770

Yellow
(538 nm)

HLMp·2870

HLMP·2855

Yellow
(538 nm)

Diffused

Green

Green

(565 nm)

Diffused

High

7 mcd@20mA

14mcd@20mA

2.1 Volts
@20mA

Yellow
Diffused

10mcd@20mA

2.2 Volts
@20mA

Green

Green

7 mcd@20mA

(565 nm)

Diffused

Efficiency

Red
(635 nm)

16 Pin DIP; .100"
Centers; .800"L x
.400''W x .240"H;

Red
Diffused

Dual Square

Arrangement

HLMP·2685

Red
Diffused

28 mcd@20mA

2.1 Volts
@20mA

Yellow

Yellow

20 mcd@20mA

(538 nm)

Diffused

2.2 Volts
@20mA

Green

Green

(565 nm)

Diffused

High
Efficiency

Red
(635 nm)

16 Pin DIP; .100"
Centers; .800"L x
.400''W x .240"H;
Single Bar Arrange-

ment

HLMP·2785

HLMP·2885

Sae Page 111 for Notes.

109

14mcd@20mA

Page
No.

139

Red LED Lamps
Device

Package Outline Drawing

Description
Part No.

5082·4850
1::1)
~=m
c::::::::::J

Red
(655 nm)

Typical
Luminous

Color 12]

Package
T·a,[3]

Lens
Red
Diffused

Typical

2El'h[1[

Forward

Intensity

Voltage

0.8 mcd @20mA

1.6 Volts
@20mA

Page
No.

145

95°

\

5082·4855

1.4 mcd @20mA

5082·4403

1.2 mcd @20mA

5082·4440

0.7 mcd @20mA

~

j

W
e

~

g

147

75°
5082·4415

[4]

1.2 moo @20mA

5082·4444

[4]

0.7 mcd@20mA

5082·4880

0.8 mcd @20mA

58°

r---

e
{(I]]IIII)

5082·4883

Clear
Non·Diffused

5082·4886

Clear
Diffused

5082·4881

Red
Diffused

5082·4884

'_/.

50°

r----65°

1.3 moo @20mA

50°

Clear
Non-Diffused

5082-4887

Clear
Diffused

5082-4882

Red
Diffused

5082·4885

Clear
Non-Diffused

5082-4888

Clear
Diffused

58°

r--r---65°

1.8 moo @20mA

58°

r----50°

r--65°

r--

~~

CD

5082·4790

T-1l4
Low Profile

Red
Diffused

5082-4791

1.2mOO@20mA

117
60°

2.5 mcd @20mA

r---

G§

m

5082-4484

T_1[4[

Red
Diffused

1.4 mcd @20mA

120°

145

5082-4494
~

5082-4480

CI§

a;

0.8 moo @20mA

5082·4483

Clear
Diffusad

5082-4486

Clear
Non-Diffused

149

,------

See Page 111 for Notes.

110

80°

Red LED Lamps (continued)
Device
Package Outline Drawing

Description
Part No.

5082·4487

ern

@

Color[21

Red
(655 nm)

Typical

Lens

Package

T·l

Clear

Low Profile[4]

Non-Diffused

00 ~
~
•

o

Typical
2(:)% [1 [

Page
No.

Forward

Voltage

Intensity

0.8mcd@20mA
120"

1.6 Volts
@20mA

149

1.6 Volts
@10mA

131

Guaranteed Min.
0.3mcd@20mA

5082·4488

=tl= @
ooQFo cfJ

Luminous

5082·4100

Subminiature

Radial Leads

Red
Diffused

5082·4101

0.5 mcd@10mA
45"
10mcd@10mA

HLMP·6203

153

Subminiature Array

Radial Leads
HLMp·6204

0

HLMP·6205

Integrated LED Lamps
Device

Package Outline Drawing

Description

Part No.

HLMP·3600

~

T· BPI

Lens

Red
Diffused

Yellow
(538nm)

Yellow
Diffused

HLMp·3680

Green

Green

(565 nm)

Diffused

Red
(655 nm)

Red
Diffused

HLMp·3105

(CJ[CJ)

High Eff.
Red
(635 nm)

'.

Typical

Typical
Luminous

Package

HLMp·3650

~~

8-

Color[21

28%[11

2.4mcd@5V

m

Q

15mA
@5V

155

20m A
@5V

157

90"

1.5 mcd@5V

0.8mcd@5V

58"

f--T ·1[41

16mA
@5V

159

70"

Clear
Diffused

CD
5082·4732

=90p
=tl=@
NOTES: 1.
2.
3.
4.
5.

No.

14mA
@12V

5082·4860

5082·4468

Page

1.8mcd@5V

HLMP·3112

(II~

Forward

Voltage

Intensity

HLMp·6600

Red
Diffused

Subminiature;

0.7 mcd@2.75V

95'

13mA
@2.75V

161

2.4mcd@5V

90"

9.6mA
@5V

163

Radial Leads

HLMp·6620

0.6mcd@5V

e % is the off-axis angle at which the luminous intensity is half the axial luminous intensity.
Peak Wavelength
Panel Mountable. For Panel Mounting Kit, see page 171.
PC Board Mountable
Military Approved and qualified for High Reliability Applications.

111

3.5mA
@5V

Hermetically Sealed and High Reliability LED Lamps
Device

Package Outline Drawing

Description
Part No.

IN 5765

T

Color 121

Red
(655 nm)

Minimum

Package

Len.

Hermetic/TO·46 14 ]

Red
Diffused

Luminous
Intensity

29%11]

0.5 mod @20mA

70°

Typical
Forward

Voltage

1.6 Volts
@20mA

Page
No.

165

JAN 1 N5765 [5]
JANTX 1N5765 [5]

lN6092

High
Efficiency
Red
(635 nm)

1.0mcd@20mA

2.0 Volts
@20mA

JAN 1 N6092 [51

"..--

I
\

JANTX 1N6092 [5]

.....

I

\

I

o

,

0 ;

I
_/

lN6093

Yellow
(583 nm)

Yellow
Diffused

Green
(565 nm)

Green
Diffused

0.8 mcd @25mA

2.1 Volts
@20mA

Red
Diffused

0.5 mcd @20mA

1.6 Volts
@20mA

JAN 1N6093 [5]

JANTX 1N6093 [5]

lN6094
JAN 1N6094 [5]
JANTX 1 N6094 [5]

5082·4787

I

Red
(655 nm)

. Panel Mount

Version

H LM P.0930 [5]
H LM P·0931 15]
~

5082·4687

High
Efficiency
Red
(635 nm)

1.0 mod @20mA

2.0 Volts
@20mA

0.8 mcd @25mA

2.1 Volts
@20mA

M 19500/519.01 [5]
M 19500/519·02 [5]

0

5082·4587

Yellow
(583 nm)

Yellow
Diffused

Green
(565 nm)

Green
Diffused

M 19500/520.01 15]
M 19500/520.02 15]

5082·4987

M 19500/521·01 15]
M 19500/521.02 15]

See Page 111 for Notes.

112

SOLID STATE LAMPS

['".""~~

HIGH EFFtCIENCVRED· 5082-4660 Series
VELLOW • 6082-4550 Series
GREEN • 5082-4950 Series

L-~____________________~

TECHNICAL DATA

MARCH 1980

Features
• HIGH INTENSITY
• CHOICE OF 3 BRIGHT COLORS
High Efficiency Red
Yellow
Green
• POPULAR T-13I. DIAMETER PACKAGE
• LIGHT OUTPUT CATEGORIES
• WIDE VIEWING ANGLE AND NARROW
VIEWING ANGLE TYPES
• GENERAL PURPOSE LEADS
• IC COMPATIBLE/LOW CURRENT
REQUIREMENTS
• RELIABLE AND RUGGED

Description
The 5082-4650 and the 5082-4550 Series lamps are
Gallium Arsenide Phosphide on Gallium Phosphide
diodes emitting red and yellow light respectively. The
5082-4950 Series lamps are green light emitting Gallium
Phosphide diodes.

Part
Number

General purpose and selected brightness versions of both
the diffused and non-diffused lens type are available in
each family.

(

package Dimensions

I

5082~

.Application

4650

IndicatorGeneral Purpose
Indicator High Ambient
Illuminator/Point
Source
IUuminator/High
Brightness
Indicator
General Purpose
Indicator High Ambient
Inuminator/Point
Source
Illuminator/High
Brightness
Indicator General Purpose
Indicator High Ambient

4655
5.08 (.200)

4657

4.32(.110)

f

PLASTIC

4658

9.47 (.373)

7.i5t:m\

---ti

4550
4555

0.89 (.035)

o:iirn5l

4557

!!S~
0.381.014)

4558
4950
4955
4957
2.64[.10)
NOT~

,.,

2.
3.

NOM.

4958

All.. tHMEN$IONS ARE IN MllL,IMETAES (lNCH£S;_
SIt.V,ER·PLATEO LEADS. SEE AI'PLtCATlON l!UU.:ETIN 3.
AN EPOXY MENISCUSMA't EXTEND ABOur 1Mrn
i.040"t OOWN lHE l~ADS.

113

Lens

Color

Diffused
Wide Angle

High
Efficiency
Non Diffused
Red
Narrow Angle
Diffused
Wide Angle
Non-Diffused

Yellow

Narrow Angle
Diffused
Wide Angle

Illuminator/Point Non-Diffused
Source
Illuminator/High Narrow Angle
Brightness

Green

Electrical Characteristics at TA=25°C
Symbol

IV

Description
Luminous intensity

Included Angle
Between Half
Luminous Intensity
Points

Device
50824650
4655
4657
4658
4550
4555
4557
4558
4950
4955
4957
4958
4650
4655
4657
4658
4550
4555

Min. .Typ.
1.0
2.0
3.0 . 4.0.·. ·
9.0
12.0 .
24.0·· .
15.0
1.0
1.8
3.0
2.2
6.0
9.0
12.0
1.6.0
1,0
1.8
2.2
3.0
9.0
6.0
16.0
~2.0
90
90

C

Capacitance

Thermal Resistance

4958
4650s
45505
49505
4650s

nm

.nm

See Note 2 (FlgJ) \,.
'.

572

'.

"

ns

90
90
200
16

..

pF

VF = O,f = 1 MHz.

18
18
135
135
145
2.2
2.2
2.4

46505

4550s

17v

:

Deg.

585

4950s
46505
4550s
4950s
4650s
4550s
49505
4650s
45505

49505
Reverse Breakdown Volt. All
Luminous Efficacy
4650s
4550s
4950s

mod.
'.

635
583
565
626

49505
Forward Voltage

.

90
90
30
30

4550s
Speed of Response

"

35
35

4957

Dominant Wavelength

.'

90
90

4558
4950
4955
Peak Wavelength

"

35
35

4557

ApEAK

,

5.0

147

570
665

,

,

.Junc;tion to' Ga:tljOde

Lel!d .at$$iti(l{t~~ne'
,c ') \ '

3.0
3.0
3.0

',"~),{,'~)~/

v
V
lumens/watl
.

'

NOTES,
1. 8% is the off-axis angle at which the luminous intensity is half the axial luminous intensity.
2. The dominant wavelength, A.d, is derived from the CI E chromaticity diagram and represents the single wavelength which defines the color of the device.
3. Radiant intensity, Ie- in watts/steradian, may be found from the equation le=lv/Tlv, where Iv is the luminous intensity in candelas and Tlvis the luminous
efficacy in lumens/watt.

114

Absolute Maximum Ratings at TA =25°C
:

Parameter

..•.

High Efficiency Red
4650 Series

4550 Series

Green
4950 Series

Units

120

120

120

mW

POW8\" l)l1lsipation

.

DC ~orwarc;tCummt

..

..

Pe.kQP.eratlng~orwar(f Current

/:;,'

.. '

....

.

....

Yellow

20(11

20(1)

30[2}

60

60

60

(Fig. 5)

Openiling and Storage.iemperatureRange

mA
mA

(Fig. 15)
(Fig. 10)
~55°0 to +100°0

..

Lead Solderiemperatur. (1.6mm(Q.063
inchjbelowpackage base)

260" 0 for 5 seconds

1. Derate from 50° C at 0.2mA/o C
2. Derate from 50° C at 0.4mAI" C

1.0

~

HIGH EFfiCIENCY

enz

REO

w

I-

;!;

w

0.5

>

~

;j
0:

0

500

650

750

WAVELENGTH - nm

Figure 1. Relative Intensity vs. Wavelength.

,.

High Efficiency Red 5082-4650 Series
20

T.

~

~Sl

'.0

~-

)
00

3.0

~

V

3

V

'1---

2.5

3.0

V F - FORWARD VOLTAGE - V

Figure 2. Forward Current vs.
Forward Voltage

00

(

-'"

9

B

.

I

--I--

7

'0

'5

20

'F - FORWARD CURRENT - mA

Figure 3. Relative Luminous Intensity
VS. Forward Current.

!PEAK - PEAK CURRENT - rnA

Figure 4. Relative Efficiency
(Luminous Intensity per Unit
Currentl vs. Peak Current.

tp - PULSE DURATION - loiS

Figure 5. Maximum Tolerable Peak Cur·
rent vs. Pulse Duration. (I DC MAX
as per MAX Ratings.)

Figure 6. Relative Luminous Intensity vs. Angular Displacement.

115

..

0

.,../
2.0

;,

21----

..... ~ i-=

Yellow 5082-4550 Series
20

•r---- 1 -

e 2.0
~

I

0

I

,I

•
0

2.'

I

r) ..·c

.5

1.0

1.5

/

2.0

~

1.'

~
<

1.0

~

~
2.5

141--+~+":""'-'I

1.11--:-r+-+-"..;-t--f---i
1.0 I-'-l~--+-+....c.+_-I---I

..

3.0

VF - FORWARD VOLTAGE - V

IF - FORWARD CURRENT - rnA

Figure 7. Forward Current V50
Forward Voltage.

IpEAK - PEAK CURRENT - mA

Figure 8. Relative Luminous Intensitv
V$. Forward Current.

Figure 9. Relative Efficiency
(Luminous Intensity per Unit
Currentl vs. Peak Current.

-++++~+"'k±+-I.2
90'1--+--+-+---t:~
tp - PULSE DURATION - ps

Figure 11. Relative Luminous Intensity vs. Angular Displacement.

Figure 10. Maximum Tolerable Peak Cur·
rent V50 Pulse Duration. (IDe MAX
as per MAX Ratings)

Green 5082-4950 Series
20

0

~!;( 1.'

/

;

1.'

TA;..,.C
2.0

1.0

/

..
.....
'0

/1/

1.2

~ffi

1. 1

>N
i=~

1.0

~~
a:~

.9

.6
15

20

25

30

IF - Fe,RWARD CURRENT - mA

Figure 13. Relative Luminous Intensity
VS. Forward Current.

~,

;'

1.3

f--j-

\/

f-f
10

i

/

,.

//

: .

....
30

40

1-\-+....+++·-1.4

--If!'I.I-I-H .2

tp - PULSE DURATION - J.II

Figure 16. Relative Luminous Intensity vs. Angular Displacement.

116

60

Figure 14. Relative Efficiency
(Luminous Intensity per Unit
Current) vs. Peak Current .

.6

Figure 15. Maximum Tolerable Peak Cur·
rent vs. Pulse Duration. (lDC MAX
as per MAX Ratings)

50

IpEAK - PEAK CURRENT - mA

TECHNICAL DATA

MARCH 1980

Features
•
•
•
•
•
•
•

HIGH INTENSITY
LOW PROFILE: S.Smm (0.23 In) NOMINAL
T-1I/4 DIAMETER PACKAGE
LIGHT OUTPUT CATEGORIES
DIFFUSED AND NON-DIFFUSED TYPES
GENERAL PURPOSE LEADS
IC COMPATIBLE/LOW CURRENT
REQUIREMENTS
• RELIABLE AND RUGGED
• CHOICE OF 4 BRIGHT COLORS
Red
High Efficiency Red
Yellow
Green

Description
The 5082-4990 Series are Gallium Phosphide Green Light
Emitting Diodes packaged in a Low Profile T-1% outline.

The 5082-4790/4791 are Gallium Arsenide Phosphide Red
Light Emitting Diodes packaged in a Low Profile T-1%
outline with a red diffused lens.

The Low Profile T -1 % package provides space savings and
is excellent for backlighting applications.

The 5082-4690 Series are Gallium Arsenide Phosphide on
Gallium Phosphide High Efficiency Red Light Emitting
Diodes packaged in a Low Profile T-1% outline.
The 5082-4590 Series are Gallium Arsenide Phosphide on
Gallium Phosphide Yellow Light Emitting Diodes packaged in a Low Profile T-1% outline.

r

l

Lens
I ; / , 'General Purpose
'~'~:
Indipator;:" .

package Dimensions

. ',', .
'.

'

'~'

,~!:i

t.

2,
t,

Diffused
Wide Angle

'High Brightness
>

:



u

..

:::;

~

4

~

3

"

1.0

II:

0
~

I

(

1.5

N

0

II:

II:

/'"

E

W

..

/'

2,0

20

Z

II:
II:

1,30

.b-c

.5

-~

1
1.40

1.70

/

VF - FORWARD VOLTAGE -V

Figure 2. Forward Current versus
Forward Voltage.

tp -

1/

/

><

ffis

1.20

j

§~

il:c
WW
w!l!

1"-

1.10

S!
wO

a:~

tftt
.

I

,;

I

1.00

.,
10

20

30

40

50

IF - FORWARD CURRENT - mA

Figure 3. Relative Luminous Intensity
versus Forward Currant.

20

40

60

Figure 4. Relative Efficiency
(Luminous Intensity
per Unit Currentl
versus Peak Current.

PULSE DURATION - p.s

Figure 5. Maximum Tolerable Peak Current versus'Pulse
Duration, (lDC MAX as par MAX Ratingsl

Figure 6. Relative Luminous Intensity versus
Angular Displacement.

119

80

'PEAK - PEAK CURRENT - rnA

100

HIGH EFFICIENCY RED 5082-4690 SERIES
Electrical Specifications atTA =25°C
50$2-::
4690

Axial Luminous Intensity

Iv

'-~

tyPo

,f;~>

.3.5

6.0

.7.0

Max.

..

- j:
_4,

.,SQ.,

50".

4693

. Units .' .Test <;andnions

,,,

:'. mod
,-2"

"

deg.

.~',

-169S '

Peak Wavelength

'~

Oomir1ant Wavelength

1.

Speed of Response

'.'

,~

"

C

Qlpacitance

{lJC

Thermsl Resistance

VF

Forward Voltage

8VA

Reverse Breakdown Voltage

flv

Luminous Efficacy

..

'

2.2

~'

"
,

"

....','~.

16
13Q'

Note 1 (Fig. 111
"

"

,>

~K

"

'IF"; 10mA (Fig.8)

,

&0 H.O

4695

28~

Min·

4.6 ','8;0

,,~,

Included Afl9.le 8etween
Half Luminous Intensity ,
Points

,

'

Q9viile

DellCt'iption

Symbol

·I"!m.

Measurement @Peak (Fig. 1)

'nm ..

Note 2

' :,

"ns
pF

"

°e/W
V

3.0

V

5.0 .

Im/W

147

, \fr. =0; f =1 MHz

,

'

Junction to Qlthoqe Lead 1.6mm " '
,(O.063 in.) from Body
~:"
IF = 10mA (Fig. 7)

IA :

100pA

Note 3

Notes: 1.6% is the off-axis angle at which the luminous intensity is half the axial luminous intensity. 2. Dominant wavelength, Ad. is derived from the CIE
chromaticity diagram and represents the single wavelength which defines the color of the davica. 3. Radiant Intansity la. in wattsTttaradian may be found
from the equation Ie - Ivhlv, whare Iv is the luminous intensity in candelas and '1v is tha luminous efficacy in lumens/watt.
20

TA

~
I

!.;

~26"c

J

10

il0:

fZ
I

0

0

)
1.0

.5

Vf

-

1.5

2.0

2,5

3.0

FORWARD VOLTAGE - V

Figure 7. Forward Cunent _sus
Forward Voltage.

0

V

/

CJ"

1.2

>liI

L

1/

5

~l

r--r--1.3 r---

1.5

/

w

0:

-

1.6

Jc

15

!§

"ca:

I-T....

tE~

V

we

wW

>N

i=:::i

:s~
wa:

1.4

1, 1

.9
8

E"
L

C-

V

1. o

0:0

g

-

.,~,.
",,"

I

I
I

7

10

15

If - FORWARD CURR ENT - mA

Figure 8. Relative Luminous Intensity
versus Forward Current.

20

11l

20

30

40

Figure 9. Relative Efficiency
{Luminous Intensity
per Unit Currentl
versus Peak Cunent.

to - PULSE DURATION-IB

Figure 11. Relative Luminous Intensity versus
Angular Displacement.

Figure 10. Maximum Tolerable P.,k Current _sus Pulss
Duration. {lDC MAX as per MAX Ratingsl

120

50

IpEAK -.PEAK CURRENT - rnA

60

YELLOW 5082-4590 SERIES
Electrical Specifications at TA =25°C

[-

. to'
18,'
-

100
"

..

,

~CIW.

. JUnction to· Cathode Lead 1.6mm
.•. ':, '.(0.063 in.) from Body

2.2· 3~

5.0

. Luminous. Efficacy

571)

. ...

Notes: 1.6% is the off-axis angle at which the luminous intensity is half the 8xialluminous intensity. 2. Dominant wavelength, Ad. is derived from the CIE
chromaticity diagram and represents the single wavelength which defines the color of the device. 3. Radiant Intensity Ie. in watts/steradian may be found
from the equation Ie = Iv/'ly. where Iv is the lumil'\oUS intensity in candelas and f1v is the luminous efficacy in lumens/watt.
20

"
E
I

!i:w

15

It
It

:;)

u
0

~~ ~2\1'~

r
J

..

.

~

1

I

,"'"
00

.5

1.0

1.5

2.0

2.0

""

1.5

~:i
-,"
w:!

V

/

-0

2.5

3.0

Figure 12. Forward Current versus
Forward Voltage.

0

0

/

U
>0

1.4

~!(

1.2

u"
~~
u-

7"

1.3

10

:/

/

wo

WW

1.1

~~

1.0

>!:>!
-':!

V

I

Wit

It~

.9
.8

5

.. .....

1.5

.5

It

VF - FORWARD VOLTAGE - V

/

/.

1.0

>It

~~

1.6

": '> •.

00
zw
-N

y

;'-

~

~;(

~~
.....

?

It

~

...

~A' zJ'c

>

r

10

It

2.5

I

15

20

IF - FORWARD CURRENT - mA

Figure 13. Relative Luminous Intensity
versus Forward Current.

I
10

20

30

40

Figure 16. Relative Luminous Intensity versus
Angular Displacement

121

80

Figure 14. Relative Efficiency
(Luminous Intensity
per Unit Current)
versus Peak Current.

tp - PULSE DURATION - ps

Figure 15. Maximum Tolerable Peek Current versus Pulse
Duration. (lDC MAX as per MAX Ratings).

50

IpEAK - PEAK CURRENT - mA

GREEN 5082 -4990 SERI ES
Electrical Specifications at TA =25°C
Device
5082·

DeSQ'iptioo

Symbol

4990
4992
4995
4997

Axial Luminous Intensity

Iv

Min. Typ. Max.
2.0
6.0

3.5
8.0

4990
4992
4995
4997

Units

Test Conditions

moo

'F '" 20mA (Fig.l81

deg.

Note 1 (Fig.21}

4.5
7.5
6.5
11.0
50
50

2011,

Included Angle Between
Half Luminous Intensity
Points

APEAK

Peak Wavelength

565

nm

Measurement

Ad

Dominant Wavelength

570

nm

Note 2

1'5

Speed of Response

200

ns

C

Capacitance

12

pF

8JC

Thermal Resistance

90

°CIW

VF

Forward Voltage

BVR

Reverse Breakdown Voltage

flv

Luminous Efficacy

40
40

3.0

2.4
5.0
665

@l

Pea k (Fig. 1)

,
VF = 0; f '" 1 MHz
Junction to Cathode Lead 1.6mm
(0.063 in.l from Body

V

IF'" 20mA (Fig. 17/

V

IR = 100pA
Note 3

ImIW

Notes: 1.8% is the off-axis angle at which the luminous intensity is half the axial luminous intensity. 2. Dominant wavelength, Ad. is derived from the CI E

chromaticity diagram and represents the single wavelength which defines the color of the device. 3. Radiant Intensity Ie, in watts/steradian may be found
from the equation Ie = ly/1/y. where Iy is the luminous intensity in candelas and 1/y is the luminous efficacy in lumens/watt.
20

"E.

I
I-

TA~2S'C

I

15

0

"";<
i!"

>-

I-

'"wE

i

-~

1.0

.5
VF

1-0

ZN

~~

~

iJ

1.5

2.0

1.5

~25'C

1.4

I

I

1.5

,,,,-'
-,"
w"

1.0

>"
_0

,,;j
I-Z

"
2.5

3.0

FORWARD VOLTAGE - V

Figure 17. Forward Current versus
Forward Voltage.

U

VI'

00
zw
-N

i/

10

2.0

Z"

I

~

""
""

TA

./

.5

...-V

/

1.3

~"

1.2

"5l
:::;

1.1

""

./

"

0
~

1.0

25

30

IF - FORWARD CURRENT - rnA

Figure 18. Relative Luminous Intensity
versus Forward Current.

"

/

V
10

20

IpEAK -

30

40

PEAK CURRENT

Figure 21. Relative Luminous Intensity versus
Angular Displacement.

122

50
~

rnA

Figure 19. Relative Efficiency
(Luminous Intensity
per Unit Current I
versus Peak Current.

tp - PULSE DURATION -/.IS

Figure 20. Maximum Tolerable Peak Current versus Pulse
Duration. (I DC MAX as per MAX ratingsl.

.'

.-

I

.9

.8

20

.... "

N

Vi

15

/'

I-

V
10

0

60

SOLID STATE LAMPS
HIGHEFFlClENCY RED· HlMP..t300.-1301.-1302
YELLOW • HlMP-14OO,. .1401.-1402
GREEN • HlMP·1500...1601.-1502

L-

TECHNICAL DATA

MARCH 1980

Features
• HIGH INTENSITY
• WIDE VIEWING ANGLE
• SMALL SIZE T-1 DIAMETER
3.1Smm (0.125 inch)
• IC COMPATIBLE
• RELIABLE AND RUGGED
• CHOICE OF 3 BRIGHT COLORS
HIGH EFFICIENCY RED
YELLOW
GREEN

Description
The HLMP-1300, -1301, and -1302 have a Gallium
Arsenide Phosphide on Gallium Phosphide High Efficiency Red Light Emitting Diode packaged in a T-1 outline
with a red diffused lens, which provides excellent on-off
contrast ratio, high axial luminous intensity and a wide
viewing angle.

package Dimensions

The HLMP-1400, -1401, and -1402 have a Gallium
Arsenide Phosphide on Gallium Phosphide Yellow Light
Emitting Diode packaged in a T-1 outline with a yellow
diffused lens, which provides good on-off contrast ratio,
high axial luminous intensity and a wide viewing angle.

[

The HLMP-1500, -1501, and -1502 have a Gallium
Phosphide Green Light Emitting Diode packaged in a T-1
outline with a green diffused lens, which provides good
on-off contrast ratio, high axial luminous intensity, and a
wide viewing angle.

Iv - Axial Luminous Intensity at 25° C
(Figures 3,S,15)
IV (mcd)

t Min. t Typ.ITest Conditions
HIOh Efficiency Red
HLMP- 1300
HLMP-1301 (-4684>
HLMP-f302

I

0.5 11.51
1.0
2.0 Ip10 mA
2.0
2.5

YeUow
HLMP-1400
HLMP-1401 (-4584)
HLMP-1402
Green

I 1.0
0.5 1 1.5 1
2.5 Ip"10 mA
2.5

4.0

HLMP-1500
I 0.5 1 1.2 1
HLMP-1501 (-4984l
0.8
2.0 IF=20 mA
HLMP-1502
2.0
3.0

123

Absolute Maximum Ratings at TA = 2SoC
"
Green
High Efficiency Red
Yellow
HLMP-1300, 1301,1302 HLMP-1400,1401,1402 HLMP-1500,1501,1502 Units '

Parameter
Power Dissipation

120

120

120

DC Forward Current

20 111

20[1)

30(2)

60

Peak Forward Current

60
See Figure 10

See Figure 5
Operating and Storage
Temperature Range

mW '::'

"

rnA

rnA

60
See Figure 15

-55·C to 100"C

'Lead Soldering Temperature
[1.6mm (0.063 inJ from Body1

230· C for 7 Seconds
1. Derate from 50° C at 0.2mA/o C
2. Derate from 50° C at OAmA/o C

Electrical/Optical Characteristics at TA = 2SoC
Symbol
2fl1/2

Description

HLMP-1300, -1301,
-1302

HLMP-1400,-1401,
-1402

Min.

Min.

Included Angle
Between Half
Luminous Intensity
Points

Typ.

Max.

Typ.

Max.

HLMP-1500,-lS01,
-1502
Min.

Typ.

Max.

Units

Test Conditions
Note 1 (Figs. 6,
11, 16)

70

60

60

Deg.

Apeak

Peak Wavelength

635

583

p65

nm

Measurement
at Peak

Ad

Dominant
Wavelength

628

585

572

nm

Note 2

1'S

Speed of Response

90

90

200

ns

C

Capacitance

20

15

8

flJC

Thermal Resistance

95

95

95

pF

VF=O; f=1 MHz

·C/W Junction to
Cathode Lead
at 0.79mm
(0.Oa1 inJ
From Body

VF

Forward Voltage

BVR

Reverse Breakdown
Voltage

'Iv

Luminous Efficacy

2.2

3.0

2.2

5.0

3.0

5.0

2.4
3.0
at IF'" 20mA
5.0

570

147

V

IF=10mA
(Figs. 2.7,12)

V

IR=100!,A

1mIW Note 3

665

1. 01/2 is the off-axis angle at which the luminous intensity

IS half the axial luminous intenSity.
2. The dominant wavelength, Ad, is derived from the CIE chromaticity diagram and represents the single wavelength which defines the
color of the device.
3. Radiant intensity, Ie, in watts/steradian, may be found from the equation le=lv/~v' where Iv is the luminous intensity in candelas and ~v
is the luminous efficacy in lumens/watt.

1.0

GREEN"

0.5

II \j:~'l\
j\
YEllOW

r

II
0
500

TA "" 25'·C

550

I

~~

600

650

WAVELENGTH - nm

Fig"re 1. Relative Intensity vs. Wavelength.

124

700

750

High Efficiency Red HLMP-1300,-1301,-1302

..

1,
~

(

~
"
~

>

"

~l

!-

!j:<

,.

2 .•

00
ZW

•

~~
~c
~I

-"

~-

0:

fZ,

~S!

v, -

1.•

FORWARD VOLT AGE - Y

IF - FORWARD CURRENT - mA

Figure 2. Forward Current VI.
Forward Voltage.

~

3 .•

t:

iI!-

!PEAK - PEAK CURRENT - rnA

Figure 3. Relative Luminous Intensity
vs. Forward Current.

Figure 4. Relat,ve Efficiency
(Luminous Intensity per Unit
Current) VI. Peak Current.

w

e
"
~

"X

~

~~

Ow

4

~~

.. 0:

!~

""is "
!2 "
e

xC

:

il~."

Ell
tp - PULSE DURATION -,'!S

Figure 5. Maximum Tolerable Peak Current VI. Pulse Duration. (lDCMAX
as per MAX Ratings).

F;aure 6. Relative Luminous Intensity

VI.

Angular Displacement.

Yellow HLMP-1400,-1401, -1402
T.~25"C

I

•

r

II

•
•

10

1.5

2.0

~:c

1.'

2

ZW

~j

-:

=i
~S!

,1

1.•

• J.
• _I

~-

25

Figure 7. Forward Current VI.
Forward Voltage.

/

'"

V'

1/

8

7
'01020

3.0

-v

,,~

,3

OQ

)
VF - FORWARD VOLTAGE

1.
2.•

~l
!-

r

•

•
•
•

1.

2.'

~
iI!-

IF - FORWARD CURRENT - mA

30

40

Figure 8. Relative Luminous Intensity
VI. Forward Current.

,4

,2

tp - PULSE DURATION ·Io'S

Figure 11. Relative Luminous Intensity vs. Angular Displacement.

125

80

Figure 9. Relative Efficiency
(Luminous Intensity p.. Unit
Current) VI. Peak Current.

\..-lr-I-H~--t-r-++++-I·6

Figure 10. Maximum Tolerable Peak Current
vs. Pulse Duration. (I DC MAX
as per MAX Ratings.) ')

50

'PEAK - PEAK CURRENT - mA

Green HLMP-1S00,-1501,-1502
20

"

,

T. ~25'C

1.5
'"

1.4

u
>0

E
I

.
~

!iu
51

1.

I!c

I
II

10

;

-"

\:
DO

1.D

.S

1.,

5:5
!t~

I.

..

~

u"

1.1

....
.

1.0

.S
2.'

.7

3.D

v, - FORWARD VOLTAGE - v
Figure 12. Forward Current vs.
Forward Voltage.

I, - FORWARD CURRENT - mA

Figure 13. Relative Luminous Intensity
vs, Forward Current.

..

.

.

~

<:::

',,~

'.

,

'i';~

~" r~(

1.2

j
2.D

,'.
"\'~'

:~

~::l
:l~

~

".

1.3

,.:

r::,.?

:,:>: '/ "
"-,~' ,

'[/:':.:

,:/
i'" :','
\/. " :

D

"

',,","

."".'

10

20

.

30

40

9O"f-:--4-- fo.-+--t>;
PULSE DURATION

-115

Figure 15. Maximum Tolerable Peak Current
VL Pulse Duration. (lDC MAX
as per MAX Ratings.)

Figure 16. Relative Luminious Intensity

126

60

Figure 14. Relative Efficiency
(Luminous Intensity per Unit
Current) vs. Peak Current.

++'+-H·4

tp -

SO

"EAK - PEAK CURRENT - mA

VL

Angular Displacement.

Fli;-

[

HEWLETT

a:~ PACKARD
TECHNICAL DATA

MARCH 1980

Features
• RECTANGULAR LIGHT EMITTING SURFACE
• FLAT HIGH STERANCE EMITTING SURFACE
• STACKABLE ON 2.54 MM (0.100 INCH)
CENTERS
• IDEAL AS FLUSH MOUNTED PANEL
INDICATORS
• IDEAL FOR BACKLIGHTING LEGENDS
• LONG LIFE: SOLID STATE RELIABILITY
• CHOICE OF 3 BRIGHT COLORS
HIGH EFFICIENCY RED
YELLOW
GREEN
• IC COMPATIBLE/LOW CURRENT
REQUIREMENTS

Description
The HLMP-03XX, -04XX, -05XX are solid state lamps encapsulated in an axial lead rectangular epoxy package. They utilize
a tinted, diffused epoxy to provide high on-off contrast and a flat high intensity emitting surface. Borderless package
design allows creation of uninterrupted light emitting areas.
The HLMP-0300 and -0301 have a high-efficiency red GaAsP on GaP LED chip in a light red epoxy package. This lamp's
efficiency is comparable to that of the Gap red, but extends to higher current levels.
The HLMP-0400 and -0401 provide a yellow GaAsP on GaP LED chip in a yellow epoxy package.

{

The HLMP-0500 and -0501 provide a green GaP LED chip in a green epoxy package.

package Dimensions
AXIAL LUMINOUS INTENSITY
MIN.

HER

I
LIGHT EMITTING SURFACE

I
PLASTIC

TOP VIEW

cA,.k,e

1.--26.40

11.00) MIN.

J

SIDE VIEW

YELLOW

GREEN

TYP.

TEST CONDITIONS

moo

IF - 25mA

1.5

2.5mcd

IF - 25mA

.8

1.5 rncd

IF'" 15mA

HLMP·0400

1.0

1.2mcd

IF - 25mA

HLMP-0401

2.0

2.5 mcd

IF - 25mA

1.0

1.5mcd

IF'" 15mA

HLMP·o3OCi

.8

HLMP-0301

1.0

HLMP·0500

1.0

1.2mcd

IF

HLMP·0501

1.5

2.5mcd

IF - 25mA

1.0

1.5mcd

IF = lOrnA

25mA

NOTE: l.uminous :ttBranGt. LV. J{\ toot It'Imberts, mav be fQUnd from the equati(Jf\
LV· t6.7Iv. where Iv Is the IunUf\(ILiSifltef1sityin miUlcaJ\de1M.

NOTES<
1. ALL DIMENSIONS ARE IN

2.54t 100) NOMINAL

MILLIMETRES (INCHES).

2.

SlI.VER·PlATED LEADS.
SEE APPLICATION
BULLETIN 3.

3.

AN EPQXY MENISCUS MAY EXTEND
ABOUT Imm {.040·1 DOWN THE

LEADS.

BOTTOM VIEW

127

Absolute Maximum Ratings at TA =25°C
Parameter

High-Efficiency Red
HLMP·0300/0301

Yellow
HLMP-0400/0401

Green
HLMP-0500/0S01

Unltll

120

120

120

mW

30 \11

30(1)

30(1)

mA

Power Dissipation
DC Forward Current

60
See Figure 10

60
See Figure 5

Peak Forward Current
Operating and Storage
Temperature Range

60
See Figure 15

mA

-55°C to 100°C

Lead Soldering Temperature
[l.6mm (0.063 in.) from body]

260° C for 5 seconds

1. Derate from 50° C at DAmAr C.

Electrical/Optical Characteristics at TA=25°C
HLMP·0300/0301 HLMP·0400/0401 HLMP·0500/0501

Symbol

Description

Units

Test Conditions

2Ell/2

Included Angle
Between Half
Luminous IntenSity
POints, Both Axes

100

100

100

deg.

Note 1. Figures.
6.11,16

APEAK

Peak Wavelength

635

583

565

nm

Measurement at
Peak

Ad

Dominant Wavelength

626

585

571

nm

Note 2

1"5

Speed of Response

90

90

200

ns

C

Capacitance

17

17

17

pF

€lIe

Thermal Resistance

130

130

130

°C/W

VF

Forward Voltage

2.5

BVI{

Reverse Breakdown
Voltage

'7v

Luminous Efficacy

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.

5.0

2.5

3.0
5.0

147

3.0

2.5
5.0

570

665

3.0

VJ':=O; 1'=1 MHz
Junction to Cathode
Lead at 1.6 mm
(0.063 in.) from
Body

V

Ip=25mA
Figures 2,7,12

V

II{ = 100 p.A

Im/W

Note 3

NOTES:
1. 0'/2 is the off-axis angle at which the luminous intensity is half the axial luminous intensity.
The dominant wavelength, Ad, is derived from the CIE chromaticity diagram and represents the single wavelength which defines the
2. color of the device.
3. Radiant intensity, I" in watts/steradian, may be found from the equation 1,=lv/'Iv, where Iv is the luminous intensity in candelas and
'Iv is the luminous efficacy in lumens/watt.

128

[

WAVELENGTH - nm

Figure 1. Relative Intensity vs. Wavelength.

HIGH EFFICIENCY RED HLMP-0300/0301
,

~U:wl:·
i

5

I JI
I I I

-"

,

Ii

,

1

!.

! I
1\

I.

0.5

I

L

I

I

/-

tIlt

. j

II '
I ·11r
I II ,I I·
,
i ! /1
i
II I i
I
I
I
I i i JI !
I
, Ii
! Y
I
I

''Tl"
.i :
0

I

I

I

5

I II 1_

I

1

f

1.0

1.5

2.0

2.5

3.0

VF -FORWARDVOlTAGE-V

Figure 2. Forward Current vs. Forward
Voltage.

{

"'

~

:la: "'

IpEAK - PEAK CURRENT - mA

IF - FORWARD CURRENT - mA

Figure 3. Relative Luminous Intensity vs.
Forward Current.

Figure 4. Relative Efficiency (Luminous
I ntensity per Unit Current) VI. Peak Current.

3.'

~

~~~~
l-ai~2

::!!:a::Qw
:::I

a: 1-0::

!a~§

~~~g

2.'

.~"
o0 "

~

l'!

1.'

~I·
¥"
j]

1

a:
,,~

1
Ip - PULSE DURATION - /-IS

Figure 5. Maximum Tolerable Peak Current VI.
Pulse Duration. (lDC MAX as per MAX Ratings.)

Figure 6. Relative Luminous Intensity

129

VI.

Angular Displacement.

YEllOW HlMP-0400/0401
30

3.0

1.5

~

25

I

I-

:i

~~

2.5

~~

20

U

20

~

~

E

:!!

"
I,,~

""
~

15

~

10

~@

filN

"'''
>'"
0

~-

I

-~

::;

"0~

1.0

I-z

_.

·:we

V

/

~

1.5

~~

~

1.0

I-

"N
,,::;

~

V

C

~E

.. - .
T.

>-

I-

.5

g

0.5

'"
0

10

Figure 7. Forward Current vs. Forward

Voltage.

20

30

40

50

60

IpEAK - PEAK CURRENT - rnA

IF - FORWARD CURRENT - rnA

V F - FORWARD VOLTAGE-V

Figure 8. Relative Luminous Intensitv vs.
Forward Current.

Figure 9. Relative Efficiency (Luminous
Intensitv per Unit Current) vo. Peak Current.

Ip - PULSE DURATION - /1S

Figure 10. Maximum Tolerable Peak Current vs.
Pulse Duration. (I DC MAX as per MAX Ratings.)

Figure 11. Relative Luminous Intensitv vs. Angular Displacement.

GREEN HlMP-OSOO/OS01
30

"E

r-

25

~A ';25i+i±t-~- 1--;1-+,

I

I-

:i

::;

""
'""
''"~"
0

20

15

I '
i

10

I [

I

i

I

II-I-

IJ
II

o

o

I I
I I
0.5

~

"~

I
, II

I

I

2.0

::;

I

""
'"

I,

1.0

1.0

1.6

2.0

2.5

V

g

.5

3.0

v

Figure 12. Forward Current vs. Forward
Voltage.

00

...-V"'"
10

1.3

~d
"N

1.2

"'0

1.1

:E!;t

/

t- TA 1.5'C
/'

./

/

>~

~~

~"
"''''
"'0
g

.'

;'

",",

1.0

I

."

V

.8

I
15

20

25

30

IF - FORWARD CURRENT - rnA

Figure 13. Relative Luminous Intensity vs.
Forward Current.

>-0

""

/

0

i I

V F - FORWARD VOLTAGE -

U

1.5

i

/

1.'

;;
I-

i i

_.

1.5

T):WC

10

20

30

40

50

Figure 14. Relative Efficiency (Luminous
Intensitv per Unit Current) vo. Peak Current.

Ip - PULSE DURATION -!J.S

Figure 15. Maximum Tolerable Peak Current VI.
Pulse Duration. (lDC MAXas per MAX Ratings.)

Figure 16. Relative Luminous Intensitv vs. Angular Displacement.

130

60

IpEAK - PEAK CURRENT - rnA

,...

SUBMINIATURE SOLID STATE LAMPS
FJ3HEWLETT
a!!t.:PACKARO

l

RED • 5082·4100/4101
HIOH EFFICIENCY RED • 5082·4160
YELLOW •. 5082-4150
OREEN • 5082 -4190
TECHNICAL DATA MARCH 1980

Features
• SUBMINIATURE PACKAGE STYLE
• END STACKABLE ON 2.21mm
(0.087 In. ) CENTERS
• LOW PACKAGE PROFILE
• RADIAL LEADS
• WIDE VIEWING ANGLE
• LONG LIFE - SOLID STATE
RELIABILITY
• CHOICE OF 4 BRIGHT COLORS
Red
High Efficiency Red
Yellow
Green

Description
The 5082-4100/4101,4150,4160 and 4190 are solid state lamps encapsulated in a radial lead subminiature package of
molded epoxy. They utilize a tinted, diffused lens providing high on-off contrast and wide-angle viewing.
The -4100/4101 utilizes a GaAsP LED chip in a deep red molded package.
The -4160 has a high-efficiency red GaAsP on GaP LED chip in a light red molded package. This lamp's efficiency is
comparable to that of the GaP red but does not saturate at low current levels.
The -4150 provides a yellow GaAsP on GaP LED chip in a yellow molded papkage.
The -4190 provides a green GaP LED chip in a green molded package.
Tape-and-reel mounting is available on request.

package Dimensions

"

1.21 (.0501
1.40 (.0551

t'-_""",,-.i..

~
=

~~R

~~

\l
292(.115)

j~

If.- fi1
1.98(.077)
I
r.orn ~

TOP VIEW

END VIEW

NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETRES (INCHES).
2. SILVER·PLATED LEADS. SEE APPLICATION BULLETIN 3.
3. USER MAY BEND lEADS AS SHOWN.

SIDE VIEW

131

Absolute Maximum Ratings at TA =25°C
Parameter

Red

High Eff. Red

Yellow

Green

4100/4101

4160

4150

4190

120
20[11

120
20111

120
301 2 J

Power Dissipation

100
50(1)

DC Forward Current

60
See Fig. 10

1000
See Fig. 5

Peak Forward Current

60
See Fig. 15

Operating and Storage
Temperature Range

Units
mW
mA

60
See Fig. 20

mA

-5SoC to 1000C

Lead Soldering Temperature
(1.6mm (0.063 in.) from body]

245 0 C for 3 secon9s
1. Derate from 50° C at 0.2mA/o C
2. Derate from 50° C at O.4mA/o C

Electrical/Optical Characteristics at TA=25°C
symbol

Typ.

Min.

Max.

Min.

Typ.

5082-4190

5082-4150

5082·4160

5082-4100/4101

Descrlpllon

Max.

Min.

Typ.

Max.

Min.

Typ.

Max.

Unlls

Test CondillOns
IF~10mA,

2.0

0.8.11·d
At IF = 20mA

mcd

Figs. 3,8,13,18

80

90

70

deg.

Note 1. Figures
6. 11, 16,21

655

635

583

565

nm

Measurement
at Pea~

640

628

585

572

nm

Note 2

15

90

90

200

ns

Iv

Axial Luminous
Intensity

2B./2

Included Angle
Between Half
Luminous Intensity
Points

45

'\'PEAK

Peak Wavelength

-/0.5 .7/1.0

1.0

3.0

1.0

Ad

Dominant Wavelength

rs

Speed of Response

C

Capacitance

100

11

15

13

pF

SlC

Thermal Resistance

125

120

100

100

°C/W

VF

Forward Voltage

1.6

2.2

2.0

3.0

2.2

3.0

2.4

3.0

V

1,,=10mA.
Figures 2. 7.
12,17

V

IR = 100;tA

At IF =20mA
BVR

Reverse Breakdown
Voltage

~v

Luminous Efficacy

10

3.0

147

55

5.0

5.0

5.0

570

665

V,=O; f=l MHZ
Junction to
Cathode Lead at
O.79mm (.031 in)
from Body

ImIW

Note 3

NOTES:
1. €>1/2 is the off-axis angle at which the luminous intenSity is half the axial luminous intenSity.
2. The dominant wavelength. x". is derived from the GIE chromaticity diagram and represents the single wavelength which defines the color of the device.
3. Radiant intensity, Ie. in watts/steradian, may be found from the equation le=lvhr... where Iv is the luminous intensity in candelas and t]v is the luminous
efficacy in lumens/watt.

1.0

GREEN"

0.5

0
500

If

,\''''0/
YEllOW

~V \
I
550

'\

IRED

TA • 25"C

VG'AsPREO

1\\

PSL~~
650

600

WAVELENGTH - nm

Figure 1. Relative Intensity vs. Wavelength.

132

700

750

i

Red 5082-4100/4101
1I

r

~

rr:

a
c

i
I

~

IF - FORWARD CURRENT - mA

VF- FORWARD VOLTAGE -VOLTS

Figure 2. Forward Current va.
Forward Voltage.

Figure

a

'PEAIC - PEAK CURRENT - rnA

Relative Lumlnoualnlenalty
va. Forward Current.

Figure 4. Relative Elflclency
(luminous IntenSity per Unit
Current) va. Peak Current.

...

w

~~ ;;l"
~!z
w

:0

::>

10

~~

"x ~a
_u
"" xc
""
~
~

0
0

~

I

l

~~ "
~~

tp - PULSE DURATION

-,.s

Figure 6. Relative Lumlnoua Intensity va. Angular Displacement.

Figure S. Maximum Tolerable Peak Current va. Pulse Duration. (IDC MAX
as per MAX Ratings)

1.6

I

-T.-,J.C

I.'
u
>c I.'

/
0

. .'

-"

1.0

.5

I.S

2.0

0

3.0

2.'

VF - FORWAADVOLTAGE-V

100

~=:
wc

V

WW
>~

~! ."
.. I

1000

.7

10

Figure

a

..

15

20

RelativeLumlnoualntenslty
va. Forward Current.

.6 0

,

,~
~,,:,

/

--

"

'.

...
10

20

30

40

~AK - PEAK CURRENT -

10000

Figure 11. Relative luminous Intenaltyva.AngularDllpiacement.

133

50

..

mA

Figure 9. Relative Elflclency
(luminous IntenSity per Unit
Current) va. Peak Current.

tp - PULSE DURATION -/.II

Figure 10. Maximum Tolereble Peak Current va. Pulse Duration. (IDC MAX
as per MAX Ratings)

~,->-

"'!'.

.;",

1.1
1.0

'

\":

'.,,;

1.3
1.2

0:0
~

IF - FORWARD CURRENT - mA

Figure 7. Forward Current va.
Forward Voltage.

10

~§

..

'

j

,
00

/
......-:

u"

."::;'

.' ".

l,',

Yellow 5082-4150
20

'"E
... "

,

I

~

B
e

10

i

"'~

...
I

°0

.5

1.0

2.'

I

T)WC!

1.5

I
!/
A
2.0

2.S

~

h
w~

2.0

/

li_

./

~~ I.'

n
,,~

~'"
2
w
>"'

~~

,j.0

1.0

g

."'~

/

..
00

VF -FORWARDVOLTAGE-V

1.S

/

TA:;,i.e ..

/'

'~"

I.'
I.'
1.3

~
e

1.2

:::
:;

1.1

'~e"

1.0

~

20

15

.7 0

~

~

/

V

I

10

20

30

40

50

60

IpEAK - PEAK CURRENT - rnA

IF - FORWARD CURRENT - mA

Figure 12. Forward CUrrant ¥S.
Forward Voltage.

~

.. .L

.S
10

...

.. ,

Figure 13. Relatlva luminous Intensity
vs. Forward Current

Figure 14. Relative Efficiency
(Lumlnou8 Intan81ty per Unit
Current) V8. Peak Current.

9II"1--l--t-"':"+4:
tp - PULSE DURATION - /.15

Figure 15. Maximum Tolerable Peak Current V8. Pulse Duration. (IDC MAX
a8 per MAX Ratings)

Figure 16. Relative Luminous Inten8Ityvs.AngularDi8placement.

Green 5082-4190
•

20

TA .. ;t5~C

I.

0

1/

•
0

Y

•
00

..

~o

VF - FORWARD VOLTAGE-V

Figure 17. Forward Current ¥S.
Forward Voltage.

0

..;,.

!/

•

L

3

.L

2
I
0

/

•

V

V

8

IL

"

(

I

J
10

15

20

25

30

IF - FORWARD CURRENT - mA

Figure 18. Relative Luminous Inten8ity
¥S. Forward Currant.

7
· 0

10

20

30

Figure 21. Relative Luminous Intensity vs. Angular Displacement.

134

50

60

Figure 19. Relative Efficiency
(Lumlnou8 Intensity per Unit
Current) V8. Peak Current.

tp - PULSE DURATION -~s

Figure 20. Maximum Tolerable Peak Current ¥S. Pulse Duration. (IDC MAX
a8 per MAX Ratings)

40

IpEAK - PEAK CURRENT - rnA

HEWLETT
PACKARD
TECHNICAL DATA MARCH 1960

Features
• LARGE, BRIGHT, UNIFORM LIGHT
EMITTING SURFACE
Typical Luminous Stearance 260 cd/rn2 at
100mA Peak, 20m A Average
Approximately Lambertian Radiation Pattern
• SUITABLE FOR MULTIPLEX OPERATION
LED's in Either Parallel, Series or Parallel/
Series Connection
• CHOICE OF THREE COLORS
High Efficiency Red
Yellow
Green
• CATEGORIZED FOR LIGHT OUTPUT
Use of Like Chip Categories Yields a
Uniform Display

r

• EASILY MOUNTED ON P.C. BOARDS
OR SOCKETS
Single In-Line Package, Leads on Industry
Standard 2.S4mm (0.1 in.) Centers
I.C. Compatible
Mechanically Rugged

Applications

• X-Y STACKABLE

• ILLUMINATED LEGENDS

• FLUSH MOUNTABLE

• INDICATORS

• EASY ALIGNMENT

• BAR GRAPHS

• EXCELLENT ON-OFF CONTRAST

• LIGHTED SWITCHES

Description
The HLMP-2300/-2400/-2500 series light bar modules are 9mm (.35 inch) and 19mm (.75 inch) rectangular light sources
designed for a variety of applications where a large, bright source of light is required. The -2300 and -2400 series devices utilize
LED chips which are made from GaAsP on a transparent GaP substrate. The-2500 series devices utilize chips'made from GaP
on a transparent GaP substrate.

Devices
Part No.
HLMP·
2300
2350
2400
2450
2500
2550

Size of Emitting Area

Color
High Efficiency Red
Yellow
Green

8.89mm x.3.81mm (.350 in. x .150 in.)

Package
Drawing

A

x .150 in.)

B

8.S9mm x 3.S1mm (.350 in. x .150 in.)

A

19.0Smmx 3.81mm(.750 in.

19.05mm x 3.81mm (.750 in. x .150 in.)

B

S.S9mri1 x 3.81mm (.350 in. x .150 in.)

A

19.05mm x3.S,1mm (.750 In. x .150 in.)

B

135

Absolute Maximum Ratings
NOTES: 1. Derate maximum DC
current above TA=50°C
at 0.51 mA/oC per LED
chip, see Figure 2.
2. See Figure 1 to establish
pulsed operating
conditions.
3. For operation above
TA=50o C, see the allowed deratings for
higher temperatures
shown in Figure 2.

Average Power Dissipation Per LED Chip (TA= 50°C) ................ 90mW
Operating Temperature Range ........................... -40°C to +85°C
Storage Temperature Range ............................. -40°C to +85°C
Peak Forward Current Per LED Chip (TA=50°C)12.3) ..................120mA
(Maximum Pulse Width = 1.25ms)
DC Forward Current Per LED Chip (TA= 50°C)ll,3) .................... 30mA
Reverse Voltage Per LED Chip ..................................... 6.0V
Lead Soldering Temperature [1.6mm (1/16 inch) below
seating plane] ...................................... 260°C for 3 Seconds

For a Detailed Explanation on the Use of Data Sheet Information and Recommended
Soldering Procedures, See Application Note 1005, Page 464.

package Dimensions

MRT
NUMBER

LUMINOUS
INTEN$IT'(
CATEGORV.
$.080'

. 1O.200} .

" 2,64 TVP
',10.100)

J bJL:::}
','

,',

S/PEA:'

SIDES.

Internal Circuit Diagram
FUNCTION ' : " ... ; : .
B
A

.2350/-2450· .

PIN

•2300/-2400
-2500

1

Cathode - a,',.

Cathode-a

Anode-a

Anode-:a
Cathode -:. b '., c.

2
3
4

>:

8.

:.' -2550

Cathode-b,·

. Anode..;."b

5. 01
6 ..
7:

A

.

<

:'"
"

:.:

Anode-c
i'

:.

136

;,,'

,AnQde~b ....:
,·Cathode;..,;..'c:--';·:',·

"

Cathode.:....;d
Anode-d

NOTES: 1. Dimensions in millimetres and (inches).
2. Tolerances ± .25 mm unless otherwise indicated.

B

'

Electrical/Optical Characteristics at TA=25°C
HIGH EFFICIENCY RED

HLMP-2300/-2350

Parameter

[

Luminous lntensItY.l
with All LEO's
. JlIUnlinated .

Test Conditions

Symbol

·2300

-2350

. Peak Wavelength

Iv

100mA Pk: 1 of 5
Duty Factor
20mADC

Iv

100mA Pk: 1 of 5
Duty Factor
20mADC

Min.

3

7

Max.

Ad

mcd

7

mcd

21

meet

15

mcd
nm
run

626
Ip=loomA
tF= 20mA

Units

10

635

Apeak

Dominant Wavelengthl $)

Typ.

,3.5,.
2.6

IR

VR=6V

2.5
1.9
10

Temperature CO&fficient of VF Per LED

tNFfC

IF",1OOmA

-1.1

mVl"C

Thermal ReSistance LED Junction-to-Pin

R6J....f>IN

150

·C/W/

,F9fWard ~ Per LED,

' VF

Reverse Current Per LED

V

p,A,

LE,D

YELLOW HLMP-2400/-2450
Parameter
Luminous Intensity(4)

·2400

Symbol

Test Conditions

Iv

100mA Pk; 1 of 5
Duty Factor
20mADC

Iv

100mA Pk: 1 of 5
Duty Factor
20mADC

with All LED's
Illuminated

·2450

Peak Wavelength
Dominant Wavelength(5)
Forward Voltage Per LED

f

Thermal Resistance LED Junction-IOoPin

R6J-PIN

·2500

·2550

Peak Wavelength
Dominant Wavelengthl.)
Forward Voltage Per LED
Reverse Current Per LEO

mcd

18

mcd

11

mcd .'

run

2.6
2,0

VR=6V
tp=l00mA

10

pA

-1.1

mW"C

150

·ClWf
LED

Test Conditions

Iv

loomA Pk: 1 of 5
Duty Factor
20mADC
100mA Pk: 1 of 5
Duty Factor
20mAOC

Iv

nm'

IF-loomA
IF- 20mA

Symbol

with All LED's
Illuminated

5

585

IR

Units

mcd

Ad

I:NFf'C

Luminous Intensity!')

5

Max.

8

583

Temperature Coefficient of VF Per LED

GREEN HLMP-2500/-2550
Parameter

2

Typ.

Apeak

VF

Reverse Current Per LED

Min.

Min.

1.5

Typ.

3.5

2.6

Max.

V

Units

6

mcd

3.5

mcd

13

mcd

7.5

mcd

Apeak

565

nm'

Ad

572

VF
IR

Temperature Coefficient of VF Per LEO

/JNFFC

Thermal Resistance LED Junction-to·Pin

R6J-PIN

3.5

nm.

IF-100mA
iF= 20mA

2.7
2.1

VR""SV
IF=100mA

-1.1

mV/"C

150

·ClWf
LEO'

10

3.S
2.6

V

p.A '

NOTES: 4. Each device is categorized for luminous i ntensity with the intensity category designated by a letter located on the right hand sideofthe package.
5. The dominant wavelength. Ad, is derived from the CIE chromaticity diagram and is that single wavelength which defines the color of the device.

137

Electrical

Optical

The HLMP-2300/-2400/-2500 series of light bar devices are
composed of two or four light emitting diodes, with the light
from each LED optically scattered to form an evenly illuminated light emitting surface. The LED's have a large area P-N
junction diffused into the epitaxial layer on a GaP transparent
substrate.

The radiation pattern for these light bar devices is approximately Lambertian. The luminous sterance may be calculated
using one of the two following formulas:
Lv(cd/m2) = Iv(cd)
A(m2)

The anode and cathode of each LED is brought out by separate pins. This universal pinout arrangement allows for the
wiring of the LED's within a device in any of three possible
configurations: parallel, series, or series/parallel.

Lv(footlamberts) =

These light bar devices are designed for strobed operation at
high peak currents. The typical forward voltage values,
scaled from Figure 4, should be used for calculating the current limiting resistor values and typical power dissipation. Expected maximum VF values for the purpose of driver circuit
design and maximum power dissipation may be calculated
using the following VF models:

+ IPEAK

VF = 2.2V

(130)

VF = 1.9V

71" lvi(cd)

A(ft2)

AREA

SIZE OF
EMITTING SURFACE
8.89mm x 3.81 mm
19.05mm)( 3.81mm

SO. FEET
384.58 X 10-'
781.25 x 10-6

SO. METFIES
33.87 x 10-6
72.58 x 10-0

+ IDe (23.30)

For 10mA::; IDe < 30mA

For IPEAK 2: 30mA

40
35

~

--.-l

~

RoJA .. m"C/w/LEIY'

~

""

15

X

12
10

~

~

AeJA '"

o

DC OPERATION
10000

o

10

tp - PULSE DURATION -/.IS

1.7

......
~

1.5

V' ~ H<.MP·2'" SERlE' .

1.4

V

1.3
1.2

•. ..ii

1.1

.....

...-t'
~

HlMP·2300 SER1ES

120
~ 110
I 100

~

a

.J

.9

90

70

~

60

:r
~

o

10

20 30 40 50 60 70 80 90 100110120

IpEAK - PEAK CURRENT PER LED - rnA

Figure 3. Relative Efficiency
Luminous Intensity per Unit
Current) VS. Peak LED
Current.

I

I

~

2.2

I'"

I

U.I

2.0

liJll

I
I

1-+- ~V
1.5

2.0

i

~

00

70

M

00

1.0

~""

J

f=~

>~

!

3.0

I

1';II
/

~-

a.'
a.•
0.4
0.2

!
3.4

V F - PEAK FORWARD VOLTAGE - V

Figure 4. Peak Forward Current per
LED VS. Peak Forward
Voltage.

138

1.2

~~
w~

I

H1.MP-2-400 AND ~
-lEioo SERIESt--=;

1.4

~~

I

I I

2.5

1.•

I

I

~~

'"-- ,"~-2600 SEll I••

I
I

Z""
WE
0 0

(/1

V.

1.'

~~

III
11:1

If/l
It. II

>
~

;;-

HLMP'2400 SERIE~-fl.

30

10

I

.1 HlMP'23O!)SERI~ ~f11

40

.

_~

.7

m _

Figure 2. Maximum Allowable DC
Current per LED vs. Ambient
Temperature. Deratings
Based on Maximum Allowable Thermal Resistance
Values, LED Junction-toAmbient on a per LED Basis.
T J MAX=100°C.

Pulse Duration

50

Ill!: 20

i: .8

VS.

80

o

..

1.0

~

~;...-

HLMP-2S00 Sf:RIE$

1.•

.....

I
I

TA -AMBIENT TEMPERATURE _oC

Figure 1. Maximum Allowed Peak Current

I
J

.

~

fi5S"CfW/lko"'-

Jl

!--'-.J...J..J..J.J~-----'c....c-I....L.J.1'~,....-JI-"'''''''~~-J''~_\."".I..u.I1~

1.'
1.'

I\:' ,

,
V ~'

AWA "'446"CIW/UP

""
1000

I\, ~~\ ,

20

~

x
I

100

25

~

-1
10

30

~

ag

OPERATION IN THIS
REGION REaUIRES
TEMPERATURE DERATING
OF IDe MAX

00

/

~

/HLMP-2300_
SERIES

V
10

15

20

25

30

35

IF - DC CURRENT PER LED - rnA

Figure 5. Relative Luminous Intensity
VS. DC Forward Current.

LED LIOHT BAR MODULES

SIl\IOLE,TWIN, &OUAD ARRANGEMENTS
. . >,H1OHEFFICIENCY REO-HtMP-2600 SERIES
'.;
'. . . . . YEllOW ·HLMP.·27DOSERIES
i'i~l"\;; ,.... \/y.; : ; t
OREEI\!. ·HtMP-28Qll ...~'J8,.
TECHNICAL DATA

MARCH 1980

Features
• LARGE, BRIGHT, UNIFORM LIGHT EMITTING
SURFACE
Typical Luminous Sterance 160 cd/m2 at
60 mA Peak, 20 mA Average
Approximately Lambertlan Radiation Pattern
• SUITABLE FOR MULTIPLEX OPERATION
LED's In Either Parallel, Series or Parallel!
Series Connection
• CHOICE OF THREE COLORS
High Efficiency Red
Yellow
Green
• CATEGORIZED FOR LIGHT OUTPUT
Use of Like Chip Categories Yields a
Uniform Display
• EASILY MOUNTED ON P.C. BOARDS OR
SOCKETS
Industry Standard 7.62 mm (0.3 in.) DIP
Leads on 2.54 mm (0.100 in.) Centers
I.C. Compatible
Mechanically Rugged

[

Applications
• ANNUNCIATORS WITH ILLUMINATED
LEGENDS
• BACKLIGHTED FRONT PANELS

• X - Y Stackable

• FRONT PANEL INDICATORS

• FLUSH MOUNTABLE

• BAR GRAPHS

• EASY ALIGNMENT

• LIGHTED SWITCHES

• EXCELLENT ON-OFF CONTRAST

• EDGE LIGHT PANELS

Description
The HLMP-2600/-2700/-2800 series light bar modules are rectangular light sources designed for a variety of applications where
a large, bright source of light is required. These modules are configured in packages that contain either a Single, twin or quad
light emitting surface arrangement. The -2600 and -2700 series devices utilize LED chips which are made from GaAsP on a
transparent GaP substrate. The -2800 series devices utilize chips made from GaP on a transparent GaP substrate.

Devices
.

.

Number

. .' ..part Number HLMP.
.··Hlgh .
.Efficl~~Y

Size of Ught Emitting Areas

.

. led:;
L>

of

". .

. Yellow

.>2"655.'

2755

", •. ~;:;.

'. 2700·.

'26.1« . . I

"'<

Gteen
2855.·' 8.89rnm x 8.89

"<2SpO

27702870'·.

'2620'2720>2820.
I . ·.2a~:~·
27:tS'"'
2835

mm (.350 in. x .350 in.)

Light
Emitting
Areas

Package Outline

1

A

[J

8.a9mm x3:S1.mm{.3S0in, x .150 in.)

2
1

B

ill

C

S.89.mm )( 8.89 mm. (.350io. X .3S0 in.)
8.89.mm x 3.81mm (:350 io. x .1.S0 in.)

2
4

E

3.81 mmx 19.0Smm (,150 in. x .7S0 io.l

2

F

139

0

I
ill

-

Absolute Maximum Ratings
Average Power Dissipation Per LED Chip (TA = 50·C) ......... 93mW
Operating Temperature Range ...................•.. -40·C to +85·C
Storage Temperature Range ........................ -40·C to +85·C
Peak Forward Current Per LED Chip (TA = 50·C)13,51 .......... SO mA
(Maximum Pulse Width ~ 2.0 ms)
Time Average Forward Current Per LED Chip
Pulsed Conditions l41 ,........................................ 20 mA
DC Forward Current Per LED Chip (HLMP-2700 Series)
(TA=50·C)12 1 .............................................. 25mA
DC Forward Current Per LED Chip (HLMP-2S00/-2800
Series)(TA= 50·C)ill ......................................... 30 mA
Reverse Voltage Per LED Chip ................................. S.OV
Lead Soldering Temperature [1.S mm (1/16 inch) below
seating plane] .................................. 2S0·C for 3 seconds

NOTES:
1. Derate maximum DC current above
TA = 50°C at 0.57 mA/oC per LED
chip, see Figure 2.
2. Derate maximum DC current above
58°C at 0.56 mA/oG per LED chip,
see Figure 2.
3. See Figure 1 to establish pulsed
operating conditions.
4. Derate maximum IAVG current
above T A = 50° C at 0040 mA
average/o C per LED chip, see
Figure 2.
5. For operation above TA = 50° C, see
the allowed deratings for higher
temperatures shown in Figures 2
and 3.

package Dimensions

--L

~
::~"/ ~
~ •. ~

".;"X

1.016

10.040)~
TYP.

1

10.160 2
I~!c;:') 3

6.223
10.245)

TVr

DATE
CODE

T
-t

0.508' 0.05
10.020)
TYP.

I

8.890
10.350)

A

I
I
I

rr--T

SIDE VIEW C,D,E,F

a

I

----I

ii

I

I

'.

.'

8.890
10.3501

I_
I

10'r O)

13 19.050

,

10

10.160

10.400)
MAX.

....

f

B.890

t

1.270

~10.050)

10.160

10.400)
MAX.

o

C

F

E

NOTES, OUTSIDE WALL THICKNESS 0.50810.020) TYPICAL ALL PACKAGES.
DIMENSIONS IN INCHES AND IMILLIMETRES).

Internal Circuit Diagrams

Pin Function
16

'5
14

12

A,a

11
10

FUNCTION

PIN
A,B

1
2
3

4
13

5
6
7
8
II

C, 0, E, F

CATHODE a
ANODE a
ANODEb
CATHODE b
CATHODEc
ANODEc
ANODEd
CATHODEd

to

11
12 .
13

14

15
16
C,D,E,F

140

6.223
10.245)

END VIEW A,a,C,D,E,F

· ···To
D
·r -IO1- -I

~:T

...••....•.•..•.

T

JL:

I

I

I

I-I

B.890

10.350)

4'064Io~

MIN.
(0.160)

1.270

3.810 10.050)
10.150)

I

11!:::==:o!l.:i:.::

LUMINOUS
INTENSITY
CATEGORY

t Img)
.c]
... '.' I

I

I

T~

7.620

B'.'. '.
-i.J;1:1

L:5

I
I

20.320 4

_I

8890
10'.350)

7

6

-t-~:
----:J

SIDE VIEW A,a
2.540
10.100)

[Js_I

1~ 10.300)

0.254 , 0.05 ---I '-10.010)
-W

.

CATHODE a
ANODEs
ANODEb
CATHODEb
CATHODEc
ANODEc
ANODEd
CATHODEd
CATHODEe
ANODEe.
ANODEf
CATHOOEf.
CATHoDEg
ANODEg'
ANODEh
CATHoDE.h

Electrical/Optical Characteristics at TA=25°C
HIGH EFFICIENCY RED

HLMP-2600 SERIES

Parameter

(

..

Symbol
.-2655

Iv

I"
-2600

I.uminous IntensitylSj
p-erLight Emitting'

SU'rtace .Area '

-2685

~2670
-2620

I

-2635
Peak Wavelength

Iv
Iv

Iv
Iv

Typ.

Max.

16
6

3
12
6
3

6

Units

Test Condition.

mcd

60 mA Pk: .1. of 3: Duty F.actor

.....

';:.~,;'

14

mcd

20 mA DC

8

mcd'

60 mA Pk: 1 ofS DutYf~r:

7

mod

20 mA DC

32

mod

60 mA Pk: 1 of 3 Duty

28

mcd

20 mADC

16

mcd

60 mA Pk: 1 of3.Duty.Fa~qn

14

mcd

20 rM DC

8

mcd

60 mA Pk.: 1 of3.DutyFaotor

·'·-i'.:.::;·.·

.'

.'

Faowr'

.....•...... ;"

/\.

niA DC ......•.. ··.·.·;.·.\its

7

mcd

20

16

mod

60 mA Pk:1of3DiJfYF~~f

14

mcd

20 mA DC

Apeak

635

nm

Dominant Wavelength l11

Ad

626

nm

Forward Voltage Per LED

VF

2.1

Reverse Current Per LED

fR

10

/>A

Thermal Resistance LED
Junction-to-Pin

ROJ-PIN

150

°C/WI
LEO
Chip

YELLOW

2.6

V

.,.,}.,<>
./'<: >.

IF= 20 mA
VR=6V

HLMP-2700 SERIES
Parameter

Symbol
~2755

-2700

(
l

Iv

Min.

Luminous Intensity'·SI
Per Light Emitting
Surface Area

-2785

Iv
Iv

Iv

-2770

Iv

-2720

Iv

-2735

Iv

Min.

Typ.

5.4

6
2.7

Max.

Test Conditions

12

mcd

60 mA Pk: 1 of 3 Duty FElot.or

10

mcd

20 mA DC

mcd

60 mA Pk: 1 of 3 Duty Factor

.

5

mcd

20 mA DC

24

mcd

60 mA Pk: 1 of3 Duty Factor

20

mcd

20 mA DC

12

mcd

60 mA Pk: 1 013 Duty Factor

5.4

10

mcd

20 mA DC

6

mcd

60 mA Pk: 1 of 3 Duty Factor

2.7

5

mcd

20 mA DC

12

mcd

60 mA Pk: 1 of 3 Duty Factor
20 mA DC

10.8

10

mcd

Apeak

583

nm

Dominant Wavelength f71

Ad

585

Forward Voltage Per LED

VF

2.2

Reverse Current Per LED

IR

10

/>A

Thermal Resistance LED
Junction-to-Pin

ROJ-PIN

150

°C!WI
LEO
Chip

Peak Wavelength

c.'

Units

5.4

141

nm
2.6

V

IF = 20 mA
VR =6V

Electrical/Optical Characteristics at TA=25°C
GREEN

HLMP-2800 SERIES
Parameter

Symbol

Min.

;

",

-2855

Iv

Typ. '

Units

Test Condltlona

10

mcd

60 mA Pk: ,1 of 3DutyFactor

Max.

7

'mod

5

mcd

2.5

3.5

mcd
mcd

60 mA Pk: 1 of 3 Duty Factor

10

20
' 14

mcd

.20 mA DC

10

mcd

60 mA Pk: 1 of 3 Duty Factor

7

mcd

20mA DC

5

mcd

60 mA Pk: 1 of 3 Duty Factor

3.5

mcd

20mADC

10

mcd

60 mA Pk: 1 of 3 Duty Factor

7

mcd

20 mA DC

Apeak

565

nm

Dominant Wavelength l7J

Ad

572

Forward Voltage Per LEO

VF

2.2

Reverse Current Per LED

IR

10

Thermal Resistance LED
Junction-to-Pin

RIIJ-PIN

150

I'
-2800

Iv

, i.t:.rn'\lnoos Intensity'S,

-2885

Iv

,PerLightErilifting
Surface Area

-2870

Iv

-2820
-2835

Iv
Iv

"

Peak Wavelength

5

5
2.5

5

20mA DC
' 60 mA Pk: 1 of 3 Duty Factor
20mA DC

nm
2.6

V

j./A

IF'" 20 mA
VR'" 6V

"CiWI
LED
Chip

Notes:
6. These devices are categorized for luminous intensity with the intensity category designated by a letter located on the right hand side of
the package.
7. The dominant wavelength, Ad, is derived from the CI E chromaticity diagram and is that Single wavelength which defines the color of the
device.

Electrical

Optical

The HLMP-2600/-2700/-2800 series of light bar devices
are composed of four or eight light emitting diodes, with
the light from each LED optically scattered to form an
evenly illuminated light emitting surface. The LED's have a
P-N junction diffused into the epitaxial layer on a GaP
transparent substrate.

The radiation pattern for these light bar devices, is
approximately Lambertian. The luminous sterance may
be calculated using one of the two following formulas:
L (cd/m2) = Iv (cd)
v
A (m2)

The anode and cathode of each LED is brought out by
separate pins. This universal pinout arrangement allows
for the wiring of the LED's within a device in any of three
possible configurations: parallel, series, or series/parallel.

11'Iv (cd)
Lv (footlamberts) = A (ft2)

The typical forward voltage values, scaled from Figure 4,
should be used for calculating the current limiting resistor
values and typical power dissipation. Expected maximum
VF values for the purpose of driver circuit design and
maximum power dissipation may be calculated using the
following VF models:
VF = 1.8V + IPEAK (400)
For IPEAK 2: 20mA
VF = 1.6V + IDC (500)
For 5mA :<:; IDC :<:; 20mA

142

Size of Light
Emitting Surface
Area

Area
Sq. Metres

8.89 mm x 8.89 mm

67.74 x 10-6

729.16

8.89 mm x 3.81 mm

33.87 x 10-6

8.89 mm x 19.05 mm 135.48 x 10-6

364.58 x 10-6
1458.32 x lO-s

3.81 mm x 19.05 mm 72.58 x 10-6

781.25

Sq. Feet
X

X

10-6

10-6

Refresh rates of 1 kHz or faster provide the most efficient
operation resulting in the maximum possible time average
luminous intensity.

[

These light bar devices may be operated in ambient
temperatures above +60° C without derating when
installed in a PC board configuration that provides a
thermal resistance to ambient value less than 250°C/WI
LED. See Figure 6 to determine the maximum allowed
thermal resistance for the PC board, R/lPC-A, which will
permit nonderated operation in a given ambient
temperature.

The time average luminous intensity may be calculated
using the relative efficiency characteristic of Figure 3,
'7IPEAK, and adjusted for operating ambient temperature.
The time average luminous intensity at TA = 25°C is
calculated as follows:

To optimize device optical performance, specially
developed plastiCS are used which restrict the solvents
that may be used for cleaning. It is recommended that only
mixtures of Freon (F113) and alcohol be used for vapor
cleaning processes, with an immersion time in the vapors
of less than two (2) minutes maximum. Some suggested
vapor cleaning solvents are Freon TE, Genesolv 01-15 or
DE-15, Arklone A or K. A 60°C (140°F) water cleaning
process may also be used, which includes a neutralizer
rinse (3% ammonia solution or equivalent), a surfactant
rinse (1% detergent solution or equivalent), a hot water
rinse and a thorough air dry. Room temperature cleaning
may be accomplished with Freon T-E35 or T-P35,
Ethanol, Isopropanol or water with a mild detergent.

IAVG J ('7IPEAK) (Iv Data Sheet)
Iv TIME AVG = [ 20mA
Example: For HLMP-2735 series
'7IPEAK

= 1.18 at IpEAK = 48 mA

12mAJ
Iv TIME AVG = [ 20m
A (1.18) (10 mcd) = 7 mcd
The time average luminous intensity may be adjusted for
operating ambient temperature by the following exponential equation:
Iv (TA) = Iv (25°C) e [K(TA·2S"C}[

Device

K

-2600 Series
-2700 Series
-2800 Series

-0.0131/°C
-0.0112/°C
-0.0104/°C

Example: Iv (80°C) = (7 mcd) e [.(l.om (eD-2S}I=3.8mcd

Mechanical

(

These devices are constructed utilizing a lead frame in a
DIP package. The LED dice are attached directly to the
lead frame. Therefore, the cathode leads are the direct
thermal and mechanical stress paths to the LED dice. The
absolute maximum allowed junction temperature, TJ MAX,
is 100°C. The maximum power ratings have been
established so that the worst case VF device does not
exceed this limit. For most reliable operation, it is
recommended that the device pin-to-ambient thermal
resistance through the PC board be less than 250°C/WI
LED. This will then establish a maximum thermal
resistance LED junction-to-ambient of 400° C/W/LED.

143

10

22

9

!

8
7

6

,

\

1\

..

I~ ~

I

1

~

~~
\

~

~

~

\

10

~'\

100
tp - PULSE DURATION -

'~

1000

oo

1

zw

''""
::>

I"

30
25

:I;

~i::E~800-

20

./

I'\.

,
~ ,

:I;

X

«
:I;

15

1

10

"«

11m

-322'ClWILEO/

R('~

-43InPkILEV

F\iJA •

:I;

-

>u
zw
c:;

,
\

o

o

/'" K' ,

/'

w

~

~

~

itw

1.2

>
>=

1.0

.

A',

'"I

~

"

00

ro

00

I--

..iii

50

I-I--

I

'"'"
:>
u
0
«
'"
;:
a:

1t

40

HlJ-2~O

SERIES

~

"HLJ-iJoo c- f..I./
SERIES

j,

10

o

1.0

'&

..~<

'/

>-

~

0.8

V,
1/

0.6

~

~

....
c- c-

LI!II :MP~OO fER1ES I- ' I I /
HLMP-2600 SERIES

I I

I
20

30

I !

I
.0

50

60

j

1.6

#

1.4

~

WE

!Zl<:

~~

HlMP- 2700
SErtlES

00
Zw
-N

:1;-

3.0

1.0

--'

:>-'
w,.
>'"
-0

0.6

SERIES 1"-

S~

0.'

'"

0.2

w

rl

1.2

0.8 -HLMP·2600/-2700

-'«

'L

2.0

m

1.8

(j

VF - FORWARD VOLTAGE -

00

°c

Figure 4. Relative Efficiency (Luminous Intensity per
Unit Current) vs. Peak LED Current.

/,

20

00

(PEAK - PEAK CURRENT PER L.ED - rnA

I 'f

II. "... r[II

ro

00

"

y

--

10

1/

30

I
~

~

~

I

00

Figure 3. Maximum Allowable DC Currant per LED vs.
Ambient Temperature. Deratings Basad on
Maximum Allowable Thermal Resistance Values,
LED Junction-to-Ambient on a Per LED Basis.
TJ MAX =100·C.
60

~

I I ! I

S
w

538"ClWILEc\ /'"

~

~

\

HlMP-2800 SERIES

I.'

TA - AMBIENT TEMPERATURE _ °C

E

~

w

Jl

«

w

,
"

Figure 2. Maximum Allowable Average Current per LED
vs. Ambient Temperatura. Deratlngs Basad on
Maximum Allowable Thermal Resistance Values,
LED Junction-to-Amblent on a Par LED Basi._
TJ MAX =1WC.

~ ~.

0

::>

/~

1.6

HLMP·2600

HLMP-2700
35 _SERIES

u
u

/(,

-430'ClWlLeo

TA - AMBIENT TEMPERATURE _

40

.

RwA ·322"C,wILa>

11m

~s

Figure 1. Maximum Allowed Peak Current vs. Pulse Duration.

«E

V

R.JA ~ 538'"ClWILEtV'

1

10.000

,

\

14
12

,

\

\

16

10

i\~~

i\

~.

18

OPERATION IN
THIS REGION
REQUIRES
OERATING
OF IAVG MAX.

K~

~

20

/

o
o

4.0

v

/'

.A

~

V

~ i'.HlMP-2800 SERli S

10

15

20

25

30

IDe - DC CURRENT PER LEO - rnA

Figure 5. Forward Current vs. Forward Voltage Characteristics.

Figure 6. Relative Luminous Intensity vs. DC Forward Current.

For a Detailed Explanation on the Use of Data Sheet Information and Recommended
Soldering Procedures, See Application Note 1005, Page 464.

144

FliDW

HEWLETT

~~ PACKARD

5082-4860
6082-4855
5082-4484
6082-4494

COMMERCIAL
LIGHT EMITTING
DIODES

TECHNICAL DATA MARCH 1980

5082·4850/4855
~5.'('2001

I( 1

Features

4 3
. (.1701

~:H:*

..~

11.0 (.4501

• LOW COST: BROAD APPLICATION
• LONG LIFE: SOLID STATE RELIABILITY
• LOW POWER REQUIREMENTS: 20m A @ 1.6V
• HIGH LIGHT OUTPUT
0.8 mcd TYPICAL FOR 5082-4850/4484
1.4 mcd TYPICAL FOR 5082-4855/4494

23.0 1.901
MIN.

CATHODE

• WIDE VIEWING ANGLE

~ ~

1.5 (.0401
1.0601
1.0

• RED DIFFUSED LENS

~

Description
The 5082-4850/4855 and 5082-4484/4494 are Gallium Arsenide
Phosphide Light Emitting Diodes intended for High Volume/Low
Cost applications such as indicators for appliances, automobile
instrument panels and many other commercial uses.

5082·448414494

4.70 (.1851

r

1'.G2
I

f

4.19 1:i65)
+

{.DOOI
NOM.

The 5082-4850/4855 are T·' % lamp size, have red diffused lenses
and can be panel mounted using mounting clip 5082-4707.
The 5082-4484/4494 are T·' lamp size, have red diffused len~'.ls
and are ideal where space is at a premium, such as high density
arrays.

25.40 (1.001

l

CATHODE

I

~ 139~
0.64 (.0251

I

2.<'9 (.0901

If.3li(]t5i- -

--*-_/ 1

,~-

V,.

0.51 (.0201

NOTES:
0.41 (.016)
1. ALL DIMENSIONS ARE IN 1111 LlIlilETRES (lNCHESI.
2. SILVER PLATED LEADS. SEE APPLICATIONS
BULLETIN 3.
3. AN EPOXV MENISCUS MAV EXTEND .~BOUT lmm
(.040") DOWN THE LEADS.

Absolute Maximum Ratings at TA=25°C
Power Dissipation .............................. 'OOmW
DC Forward Current (Derate linearly from
50° C at 0.2mA/" C) . • . . . . . . . . . . . . . . . . . . . . . . . ..

50mA

Peak Forward Current. . . . . . . . . . . . . . . . . . . . . . . . . .. 1Amp
(lMsec pulse width, 300pps)
Operating and Storage
Temperature Range ..................... -55°C to +1 OO°C
Lead Soldering Temperature. . . . . . . . . . . . ..

145

230°C for 7 sec.

Electrical Characteristics at TA=25°C
50324484

5032-4855

5082-4850
Symbol

50824494

Units

Test Conditions

1.4

mod

IF = 20mA
Measurement
at Peak

Paramete,,;
Min.

Iv
APEAK

Luminous
Intensity

0.8

Wavelength

1"$

Speed of
Response

C

Capacitance
Forward
Voltage
Reverse
8reakdown
Voltage

VF
eVR

Thermal
Resistance

9JC

Typ. Max. Min.

Typ. Max. Min.

Typ. Max.

1.4

0.8

655

655

655

655

nm

10

10

10

10

ns

100

100

100

100

pF

f

V

IF= 20mA

V

fR

1.6

3

Typ. Max. Min.

0.8

2.0

10
100

1.6

3

1.6

2.0

3

10

0.8

2.0

1.6

3

10

10

100

100

2.0

VF=O.
~ lMHz

Junction to

°CIW

100

=100llA

Cathode Lead

50
40

30'

30
~

E

20

...I
ffi

a:
a:

10

""0
a:
~

;:

a:

:r
I
-~

1

1,40

1.70
V F - FORWARD VOLTAGE - VOLTS

Figure 1. Forward Current Versus Forward Voltage Characteristic For 5082·48501
4855/448414494.

Figure 2. Relative Luminous Intensity Versus

Angular Displacement For
5082·4850/4855.
2.50

I

2.25
2.00

/

-.
/

1.75

/

1.50
1.25

1.00

/

'.'

f-----

/

.50

0/

-

_/

,75

,2 5

/

/

10

20

30

40

50

IF - FORWARD CURRENT - rnA

Figure 4. Relative luminous Intensity Versus
Forward Current For 5082-48501
4855/4484/4494.

Figure 3. Relative Luminous Intensity Versus
Angular Displacement For
5082-448414494.

146

rh~

r _ ~~

HEWLETT

5082-4403
5082-4415
5082-4440
5082-4444
5082-4880 SERIES

SOLID STATE LAMPS

PACKARD

l

TECHNICAL DATA MARCH 1980

I
--dr

Features
• EASILY PANEL MOUNTABLE
• HIGH BRIGHTNESS OVER A WIDE
VIEWING ANGLE

I

/

9.14 (.3.0}
8.13

132~.8.9

!

L

I 5.DB
~ ~~~-

• ~~=:~~:'TION

U~}

II

~D40} ~l

533 (.21O}
4.BY"D}
5B4

I~

(.23)
'2' (.O~l

.j
MIN.

(.

Tl

~ (.240)

1 02 (040)

5.59 (.220)

064 (025) TYP

5082·4415
5082·4444

IDBD}

I ~:~
.l

irl:n oin
,

3051120}--i

2O:i

lmm I D4D"} DOWN THELEADS

are plastic encapsulated Gallium Arsenide Phosphide
Light Emitting Diodes. They radiate light in the 655
nanometer (red light) region.

BASE

/

MIN.

l'"::~ODE'_:-I

NOTE ANEPOXYMINISCUSMAYEXTENDABOUT

The 5082-4403, -4415, -4440, -4444 and the -4880 series

METAL

I ~~! :~~:_: ~ D~ylpD35}

~':~
1.02
0.64 (.025)

PLASTIC

.i--T

(.lO}

• STURDY LEADS ON 2.S4mm (0.10 in.)
CENTERS
• IC COMPATIBLE/LOW POWER

. t·
Descrlp
Ion

(.D35}

0.64 (.025)
2.54

• RUGGED CONSTRUCTION FOR EASE
OF HANDLING

:

'

i

DIA

~

ANODE

~

5082·4403
5082-4440

The 5082-4403 and -4440 are LEDs with a red diffused
plastic lens, providing high visibility for circuit board or
panel mounting with a clip.

DIMENSIONS IN MILLIMETRES AND (INCHES)

~~~~L

The 5082-4415 and -4444 have the added featu re of a 90°
lead bend for edge mounting on circuit boards.

(

5.08 (.200)
4.32 (170)
RED

CATHODE
IDENTIFICATION

-4880 SERIES
PLASTIC

The 5082-4880 series is available in three different lens
configurations. These are Red Diffused, Clear Diffused,
and Clear Non-Diffused.

1 1'40(~)

The Red Diffused lens provides an excellent off/on
contrast ratio. The Clear Non-Diffused lens is designed
for applications where a point source is desired. It is
particularly useful where the light must be focused or
diffused with external optics. The Clear Diffused lens is
useful in masking the red color in the off condition.

Lu

5082-4880
5082-4881
5082-4882

0,3
0.8
0.3
0.8

5082-4440
5082-4403
5082-4444
5082-4415

0.76 (.030)
0.51 (.020)

3.05 (.120)
2.03 (.080)

LONG LEAD (UNBENT)
Clear NonClear
Red
Diffused
Diffused
Diffused
Lens
Lent
Lens

0.5
1,0
1.6

I

15.24
(,600)

LED SELECTION GUIDE
MINIMUM
LIGHT
OUTPUT
(mcd)

t

6.10 (.240)
5.59 (.220)

0.76 (.030)

5082-4883
5082-4884
5082-4885

NOTE: AN EPOXY MENISCUS MAY EXTEND ABOUT
1rnrn (.040") DOWN THE LEADS.

Maximum Ratings at TA=25°C
DC Power Dissipation,., ... ", ... "., .. ", .... 100mW
DC Forward Current ... " .. ', .... , .. , .. ,., .. , .. 50 mA
(Derate linearly from 50°C at 0.2mA/oC)
Peak Transient Forward Current .. , . , , .. , , , .... ,. 1 Amp
(l!-,sec pulse width, 300 pps)
Isolation Voltage (between lead and base) , , , . , ... , 300 V
Operating and Storage
Temperature Range"., ..... ,.,", ... -55°Cto+100°C
Lead Soldering Temperature, .... , ...... 230°C for 7sec

5082-4886
5082-4887
5082-4888

SHORT LEAD
UNBENT
BENT

147

Electrical Characteristics at TA=25°C
5082·4403
50824415
Symbol

Parameter

IV

Luminous
Intensity

APEAK

Wavelength

5082-4880
5082-4883
5082·4886

5082·4440
5082·4444

5082·4881
5082·4884
5082·4887

5082-4882
5082·4885
5082·4888

Test
Conditions

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Units

0.8 1.2

0.3

655

0.7

0.5

655

0.8

1.0

655

1.6

1.3

655

1.8

mcd

655

nm

IF" 20mA
Maasurement

at Peak

'rs

Sp~ed of
Response

15

15

15

15

15

C

Capacitance

100

100

100

100

100

OJC

Tnermal
Resistance

87

87

100

100

100

VF

F0n.vard
Voltage

1.6

1.6 2.0

1.6

BVR

Ro9'verse Break~
down Voltage

3

10

2.0

1.6
3

10

2.0

1.6
3

2.0

10

3

10

3

ns

pF
·C/W Junction to
Ca thode Lead

2.0

10

V

IF = 20mA

V

IR =1001lA

TYPICAL RELATIVE LUMINOUS INTENSITY VERSUS ANGULAR DISPLACEMENT
44XX

4880,4881,4882

FORWARD CURRENT VS. VOLTAGE
CHARACTER ISTICS
50

.e

40

iii0:
0:

30

""

20

...I
::>

..

0:

;:

0:

~
I

90'

10

~

0,8

0,4

1,2

'"

2,0

1,6

FORWARD CURRENT - VOLTAGE CHARACTERISTICS

4883,4884,4885

4886,4887,4888

LUMINOUS INTENSITY VS. FORWARD
CURRENT (IF)
2,50
2,25

L

2,00
1,7 5

1,50
1,25

/

0

1,0

,75

/

,50

/

/

/

,25

0/

10

20

30

40

IF - FORWARD CURRENT - mA

148

50

Fh3

a:~

[~

HEW ....ETT,'"
PACKARD,'

· 5OB2~4480
,"SERIES

~----------------~----~

TECHNICAL DATA MARCH 1980

Features
• HIGH INTENSITY: 0.8mcd TYPICAL
• WIDE VIEWING ANGLE
• SMALL SIZE T-1 DIAMETER 3.18mm (0.125")
• IC COMPATIBLE
• RELIABLE AND RUGGED

Description
The 5082-4480 is a series of Gallium Arsenide Phosphide
Light Emitting Diodes designed for applications where
space is at a premium, such as in high density arrays.
The 5082-4480 series is available in three lens configurations.
5082-4480 - Red Diffused lens provides excellent on-off
contrast ratio, high axial luminous intensity, and wide viewing angle.

',".'

'.

.

,,',"eA~
',;"
-',~

,.,

,

5082-4483 - Same as 5082-4480, but Clear Diffused
to mask red color in the "off" condition.
5082-4486 - Clear Non-Diffused plastic lens provides a
point source. Useful when illuminating external lens, annunciators, or photo-detectors.

Maximum Ratings at TA = 25°C
DC Power Dissipation . . . . . . . . . . . . . . . . . 100mW

I

50mA
DC Forward Current . . . . . . . . . . . . . . . . .
(Derate linearly from 50°C at 0.2mAtC)
Peak Forward Current . . . . . . . . . . . . . . . . . 1 Amp
(1 "sec pulse width, 300 pps)
Operating and Storage
Temperature Range . . . . . . . . . . .. -55°C to +100o C
Lead Soldering Temperature ..... "

230°C for 7 sec.

Electrical Characteristics at TA = 25°C

, PART tIO. "
~'

5082-4483
aoaa......'.

,',

UNS CONFIGURATION
Red Diffused
Untin18Cl Dlfful;8d
Clear PtastIc

5082-4480 AND 5082-4483

5082-4486
30'

100

20"

40"

SO'

60"

60'

70'

700

80"

SO'

90'+---+---"!-..--':

Figure 1. Relqtive Luminous Intensity

Figure 2. Relative Luminous Intensity

vs. Angular Displacement.

vs. Angular Displacement.

50

..

E
I

2.50

t- -

>

~ 1.75
I-

Z
w

~

30

'"0:::J

:::J

u

.."
a:
;:
a:

20

I

10

1.25

:l

1.00

..>

.75

..J

.50

a:

.25

lE
w

~

>=

~

W

o
o

,/
0.4

0.8

1.2

1.6

2.0

YS.

L

/

7

/

V

/

./
10

20

30

40

50

IF - FORWARD CURRENT - rnA

FORWARD CURRENT - VOLTAGE CHARACTERISTICS

Figure 3. Forward Current
Characteristic.

/

1.50

z

L

-

iii 2.00

I-

a:
a:

2.25

I-

40

Voltage

Figure 4. luminous Intensity vs. Forward
Current (I F).

150

HEWLETT

D (hpl PACKARD

LOW PROFILE
SOLID STATE LAMPS

5082-4481

5082~4488

TECHNICAL DATA MARCH 1980

Features
• LOW COST: BROAD APPLICATION
• LOW PROFILE: 4.S7mm (0.18") LENS HEIGHT
TYPICAL
• HIGH DENSITY PACKAGING
24.13 (0.961

MIN.

• LONG LIFE: SOLID STATE RELIABILITY
• LOW POWER REQUIREMENTS:
20mA @ 1.6V

25.40 (1.410)

'-I

• HIGH LIGHT OUTPUT: 0.8mcd TYPICAL

I

!

I
I

I

J

I-l~l:~1
O'64I~eto:3i
1.015)
I--*.
-t

- -,
O.64(mJ

O.38I]ff5J
NOTES:
" ALL DIMENSIONS ARE IN MILLIMETRES (INCItES).
2. SILVER Pl.ATED LEADS. SEE APPLICATIONS
BULLETIN 3.
3. AN EPOXY MENISCUS MAY EXTEND ABOUT lmm
!.04OH ) DOWN llIE LEADS.

Description
The 5082-4487 and 5082-4488 are Gallium Arsenide Phosphide Light Emitting Diodes for High
Volume/Low Cost Applications such as indicators for calculators, cameras, appliances,
automobile instrument panels, and many other commercial uses.
The 5082-4487 isan untinted non-diffused, low profile T-1 LED lamp, and has a typical light output
of 0.8 mcd at 20 rnA.
The 5082-4488 is an untinted non-diffused, low profile T -1 LED lamp, and has a guaranteed
minimum light output of 0.3 mcd at 20 rnA.

Absolute Maximum Ratings atTA=25°C
DC Power Dissipation ................................•......................... 100mW
DC Forward Current [Derate linearly from 50°C at O.2mAtC} ......................... 50mW
Peak Forward Current [1 ~sec pulse width, 300ppsJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1 Amp
Operating and Storage Temperature Range ................................. -55°C to +100 oC
Lead Soldering Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
230°C for 7 sec.
151

Electrical/optical Characteristics at TA=25°C
Symbol

5082-4487
Mex;
Min."" Typ;

Parameters ,

,

"

'.

,

Iv

luminous Intensity

0.8

ApEAK

Wavelength

655,

Ts

Speed of Response

C

Capacitance

,',,'

Min.

5082·4488
Typ.
Max.

Test Conditions

0.8

moo

IF = 20mA

655

nm

Measurement at
Peak

10

ns

100

pF

VF '" 0, f'" 1 MHz

V

IF = 20mA

V

IR = 100tLA

'.
0.3

'

Units

"

,

10
, >

VF

Forward Voltage

BVR

Reverse Breakdown
Voltage

,

1M
..

.

'

1.6<

I

'

,2.0

10

3

2.50
2.25

TA "" Z5(!C

I - I--:

"E 40

-

/'"

2.00

/

"

I

1.75

/

1.50

30

"o
CJ

,-,

a:
~ 20
a:

1.25

I::-

-,

/

1.00

it

.7 5

I
~

2.0

10

3

50

~~

1.6

~,

10

o

.50
.2 5

/
o

0.4

0.8

/

1.2

0./
1.6

2.0

/

----- - -

/

/

10

20

30

40

50

IF - FORWARD CURRENT - rnA

VF - FORWARD VOLTAGE - VOLTS

Figure 2. Typical Luminous I ntensity Versus

Figure 1. Typical Forward Current Versus
Voltage Characteristic.

Forward Current.

Figure 3. Typical Relative Luminous Intensity
Versus Angular Displacement.

152

FliDW

HEWLETT

~r.. PACKARD

MATCHED ARRAYS OF 3- ELEMENT. HlMP - 6203
SUBM INIATURE RED 4- ELEMENT • HlMP - 6204
SOLID STATE LAMPS 5- ElEMENT • HLMP - 6205
TECHNICAL DATA MARCH 1960

Features
• EXCELLENT UNIFORMITY BETWEEN
ELEMENTS AND BETWEEN ARRAYS
• EASY INSERTION AND ALIGNMENT
• VERSATILE LENGTHS -

3,4,5 ELEMENTS

• END STACKABLE FOR LONGER ARRAYS
• COMPACT SUBMINIATURE PACKAGE STYLE
• NO CROSSTALK BETWEEN ELEMENTS

Description
The HLMP-62XX Series arrays are comprised of several
Gallium Arsenide Phosphide Red Solid State Lamps
molded as a single bar. Arrays are tested to assure
uniformity between elements and matching between
arrays. Each element has separately accessible leads and
a red diffused lens which provides a wide viewing angle
and a high on/off contrast ratio. Center-to-center spacing
is 2.54mm (.100 in.) between elements arid arrays are end
stackable on 2.54mm (.100 in.) centers.

{,

Absolute Maximum
Ratings/Element at TA = 25°C
Power Dissipation ............................ 100mW
Average Forward Current (Derate linearly from
50" C at 0.2mAfO /C) .. . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Peak Forward Current (see Figure 4) ......... 1000 mA
Operating and Storage
TemperatureRange ............... -55°Cto+l00°C
Lead Soldering Temperature [1.6 mm
(0.063in.) from body] ............... 245°C for 3sec.

package Dimensions

Notes:
1. Ad dimension..... in mlllil'l\8tn!:$ (inches'.
2. Sitm'1'1ated tetds. See; AoplJcation Bulletin 3.
3. User may bend leach as shown.
4. 0venIU lentth is thenumbet of elementl1i~
2.&4mm (.100 io,.J.

-~ffi

~"i161
1

-:

+

+

+

=

=

=

.76 {'o30l

MAX,

OJ.

I

:--... _' --N{2.54t.100)J MAX. ' _ . _ - - . ,
NOTE 4

153

Electrical SpecificationS/Element at TA=25°C
Description

Symbol

Iv

Axial Luminous Intensity

26 112

Included Angle Between Haff
Luminous Intensity Points
Peak Wavelength

;\PEAK

~

1.0

!llCd

45

Deg.

'F'" 10 rnA; Note 1
Note 2

655

nm

Measurement

640

nm
ns
pF

Note 3

°e/W

C

Capacitance

15
100

ex

Thermal Resistance

125

VF

Forward Voltage

BVR

Reverse Breakdown Voltage

rtv

Luminous Efficacy

Test Colldltions

Typ.

.5

Dominant Wavelength
Speed of Response

Ts

Max;

Min.

V

IF

V

fR = 100 J,IA

55

Im/W

2.0

Figu,. ~.

2
5

@ Peak

VF=O;f'" MHz
Junction to Cathode Lead at
.79mm(.031in)fromthe body

10

1.6
3

Units

=:

10mA

1

Note 4

Notes:
1. Arrays categorized for luminous intensity.
2. 8 1/ 2 is the off-axis angle at which the luminous intensity is half the axial luminous intensity.
3. Dominant wavelength. ~. is derived from the CI.E Chromaticity Diagram and is that single wavelength which defines the color of
the device.
4. Radiant intensity. Ie. in watts/steradian. may be found from the equation Ie = Iv/Tlv. where Iv is the luminous intensity in candelas
and Tly Is the luminous efficacy in lumens/watt.

5.•

f-----T. • ...C

J
I
I

V

1.50

V

4.•

><

<
~

-,.,-,-

-._--..

/
1
1.40

1.30

1/

I

-

iii

~
«

2 .•

"a:
~

1.0

w~

1.10

>~

-«

3~

/

'"

II

wO

V
10

a:~

20

30

40

1.00

50

40

IF - FORWARD CURRENT - rnA

VF - FORWARD VOLTAGE - VOLTS

Figure 1. Forward Current VB.
Forward Voltage.

:::0
ww

V

:

1/1
./
I 1
00

1.70

/

!;B;c

3.•

0

--1.60

!;[

1.20

M~

Figure 2. Relative Luminous Intensity
vs. DC Forward Current.

60

80

100

IpEAK - PEAK CURRENT - mA

Figure 3. Relative Efficiency
(Luminous Intensity per Unit
Current) vs. Peak Current.

80

90 r----r---+----+---~~
'lp - PULSE DURATION - j.!1 _

Figure 4. Maximum Tolerable Peak Current
VB. Pulse Durailon. (loC MAX
as per MAX Ratings).

Figure 5. Relative Luminous Intensity vs. Angular Displacement.

154

( -,

Fli;-,'. HEWLETT
II:I!a PACKARD

5 VOLT LED RESISTOR'LAMPs
HIGH EFFICIENCV":RED~' HLMP..36Dfh

veu:ow .. HlMP~3850' ,•..

"

GREEN -QP .. 3680· .
TECHNICAL DATA

Features
• INTEGRAL CURRENT LIMITING RESISTOR
• INTEGRAL REVERSE PROTECTION DIODE
• TTL COMPATIBLE: REQUIRES NO EXTERNAL
CURRENT LIMITER WITH 5 VOLT SUPPLY
• COST EFFECTIVE: SPACE SAVING
• PANEL MOUNTABLE T-1% PACKAGE
• WIRE WRAPPABLE LEADS
• WIDE VIEWING ANGLE

Description

r

The HLMP-3600 series lamps contain an integral current
limiting resistor and reverse current protection diode in
series with the LED. This allows the lampto bedriven from
a 5 volt source without the need for an external current
limiter. The -3600 and -3650 lamps utilize LED chips which
are made from GaAsP on a transparent GaP su bstrate.
The -3680 lamp utilizes an LED chip made from GaP on a
transparent GaP substrate. These T -1 % lamps are
diffused to provide wide off-axis viewing and may be front
panel mounted using the 5082-4707 Clip and ring. The
leads are wire wrappable.

package Dimensions

Absolute Maximum Ratings

CATHODE

ITA = 25°C unless otherwise specified)

1-

DC Forward Voltage ITA = 25°C)1 1 1 ............. 7.5V
Reverse Voltage ................................ 20V
Operating Temperature Range ....... -40°C to 85°C
Storage Temperature Range ......... -40°C to 85°C
Lead Soldering Temperature ........ 260°C for 5 sec.
11.6 mm (0.063 inch) from body]
Notes:
1, Derate from TA

--+_,.j

1.51.0110)
1.0 (.0401

2.54 {.1001~.
OIMENSlONS IN MlllfMETRES !lNCHESI:. .

= 50

Q

C at O.071V/oC. See Figure 3.

155

MARCH 1980

Electrical/Optical Characteristics at TA =25°C
Symbol

Parameter
Axial Luminous Intensity[4)

Iv
201/2

Included Angle Between Half
Luminous Intensity Points

""Peak

Peak Wavelength

""d

Dominant Wavelength

ROJ-PIN

Thermal Resistance

IF

Forward Current

fR

Reverse Current

l

Device
HLMp·

Min.

Typ.

3600
3650
3680

1.0
1.0
0.8

2.4
2.4

All

All

3600
3650
3680

10
10
12

All

147
570
665

3600
3650
3680

Luminous Efficacy

Units
mcd

1.8
90
635
585
565
626
585
572
90

3600
3650
3680
3600
3650
3680

Max.

Test Conditions
VF = 5 Volts

Note 1 (See Figure 4)

nm

Measurement at Peak

nm

Note 2

°C/W

15
15
15
10

Junction to Lead at
3 mm from Body

mA

VF "" 5 Volts

J1.A

VR = 12 Volts

m/W

Note 3

I

Notes:

1.8112 is the off-axis angle at which the luminous intensity is half the axial luminous intensity.
2. The dominant wavelength, Ad. is derived from the etE chromaticity diagram and represents the single wavelength which defines the color of the device.
3. Radiant intensity, Ie, in watts/steradian, may be found from the equation Ie = Ivi1rv. where Iv is the luminous intensity in can del as and t]v is the luminous
efficacy in lumens/watt.
Device
k
4, The luminous intensity may be adjusted for operatino ambient temperature
-3600
-0.0131/oC
by the following exponential equation: Iv (TA) = Iv (2S 0 C) elk ITA-25°CII
:~~~~
:ggi6~;:g

2.5

,

TA ""25~C

>

I

V

I

•

I

I

~

V5U;-

2.0

I

:ij~
~o

;;'"
0"
20
~~

~~~

w"
!!~

I

1.5

V~

r-'[

i~

r+-

1.0

I

~o

~~

0.5

o

1_
I
[

/

I

[

/1

o

!

/1

I
I

z>

I

I

~

I

I •
7,5

10
Vee - APPLIED FORWARD VOLTAGE - v
Figure 2. Forward Current vs. Applied Forward Voltage

Vee - APPLIED FORWARD VOLTAGE - V

Figure 1. Relative Luminous Intensity vs. Applied Forward Voltage

o
>
I
w

"~

7.5

1'-.

0

>

0

a:
;;:
a:

"

I

:r

'"

fil

::;

~
I

!}
0'

0'

20

40

60

I
80 85

90'

1---+--+---1-

TA - AMBIENT TEMPERATURE _ °c

Figure 3. Max. Allowed Applied Forward Voltage vs. Ambient Temp.

156

Figure 4. Relative Luminous Intensity vs. Angular Displacement

Flin(

RED 5 AND 12 VOLT
LED RESISTOR LAMPS

HEWLETT

a:~ PACKARD

HlMP-3105
HlMP-3112

TECHNICAL DATA

MARCH 1980

Features
• INTEGRAL CURRENT LIMITING RESISTOR
• INTEGRAL REVERSE DIODE PROTECTION
• TTL COMPATIBLE: REQUIRES NO EXTERNAL
CURRENT LIMITER WITH 5 VOLT/12 VOLT
SUPPLY
• COST EFFECTIVE: SPACE SAVING
• PANEL MOUNTABLE T-H4 PACKAGE
• WIRE WRAPPABLE LEADS
• WIDE VIEWING ANGLE

Description

(

The HLMP-3105 and -3112 lamps contain an integral
current limiting resistor and reverse current protection
diode in series with the LED. This allows the lamp to be
driven from a 5 voltl12 volt source without the need for an
external current limiter. Both lamps utilize LED chips
which are made from GaAsP on a GaAsP substrate. The
color is standard red. These T-1% lamps are diffused to
provide wide off-axis viewing and may be front panel
mounted using the 5082-4707 clip and ring. The leads are
wire wrappable.

package Dimensions

Absolute Maximum Ratings

23.01.901
MIN.

ITA = 25°C unless otherwise specified)

DC Forward Voltage

lTA~25°C'

Reverse Voltage

CATHODE

HLMP·310S

HLMP-3112

7.5 Volts' 1 ,

15 Volts l21

20 Volts

20 Volts

Operating Temperature Range

_40· C to 85°C -4Q"C to 85°C

Storage Temperature Range

-40" C to 85 C -4QoC to 85°C

Lead Soldering Temperature
11.13 mm (0.063 inch. from bodyl

~~-~
~
1
.
~~\-"t

~
"- '.._...L

Q

o+n o+n\

260° C for 5 seconds

"f'

___

Notes:
1. Derate from TA = 50°C at O.071V/oC. See Figure 3.

2. Derate from TA

~

.•. 69 (,0271 saUARE TYP.
.59 1.0231

---+---1

"t/

6.1 1·240)
5.6 1.220)

2.54 (.1001 NOM.

01MENSIONS tN MtLUMETRES HNCHES'.

50°C at O.OB6VI"C. See Figure 3.

157

Electrical/Optical Characteristics at TA =25°C
HLMP-3112

HLMP-310S
Symbol

Parameter

Iv

Axial Luminous Intensityl41

2111/2

Included Angle Between Half

Min.

Typ.

0.8

1.5

Max.

Min.
0.8

Max.

Test Conditions

Units

1.5

= 5 Volts

rncd

VF

mcd

VF = 12 Volts
Note 1 (See Figure 21

90

90

Luminous Intensity Points

Typ.

APeak

Peak Wavelength

655

655

nm

Measurement at Peak

Ad

Dominant Wavelength

640

640

nm

Note 2

ROJ-PIN

Thermal Resistance

90

90

oeM Junction to
Lead at 3mmfrom Body

13

IF

Forward Current

IR

Reverse Current

'f/v

Luminous Efficacy

20
14

20
10

10

VF '" 5 Volts

rnA

VF = 12 Volts

If. A

VR = 12 Volts

Im/W

55

55

mA

Note 3

Notes:
1. tl1!2 is the off-axis angle at which the luminous intensity is half the axial luminous intensity.
2. The dominant wavelength, Ad, is derived from the erE chromaticity diagram and represents the single wavelength which defines the color of the device.
Radiant intensity, Ie, in watts/steradian, may be found from the equation Ie -= IV/1]v, where Iv is the luminous intensity in candelas and 1]v is the luminous
efficacy in lumens/watt.
4. The luminOUS intensity may be adjusted for operating ambient temperature by the following exponential equation:
Iv !T A,I = Iv 1,25° C \ el-O,188 !TA - 25°CI i

2.8

in
>>-'
>-0

T~ " 25)C

I

2.4

v;>

2'"
w>>-"

~~
::IN

I

2.0
1.6
HLMP·3105

0::;

""

1.2

>Ui

O.S

22

::J"

/
1

-,0
w2

j::;:

51'?

w'"

,,:5

0.'

~

o

o

t

II

/

V

1.4
1.2

24

v;
':;

"

>0

E
I

!:>
U>N

1.0
0.8

2~

>-

~

16

~~
:IN

""::J
u

2"

0

12

w>>-"

0::;

/1

0.6

hLJp.3112

V

'/

::J"
-,0
w2

>N-

0.2

"'"
~~

f=::

o

0
I 6
5

18
7.5

10

I

12

~ HL~P.3!'2 _

7.5

~

6>

o

V/V

Vi

-"r

p31 2

7!58

10

1
12

14 1!516

Vee - APPLIED FORWARD VOLTAGE - V

Figure 2. Forward Current vs. Applied Forward Voltage

1
1
1

HLMP.31~

0",
,,0

I

~/

~

>

"«>-

I

.co

Figure 1. Relative Luminous Intensity vs. Applied Forward Voltage

w

/

"it"

14 I 16
15
Vee - APPLIED FORWARD VOLTAGE - V
4

!~LM~.31oi

«
"

;;02

0.4

/

20

«~

,,'?
~~

"-i
fa

I

2
~
I

~
o

o

20

40

60

8085

TA - AMBIEN"( TEMPERATURE _ °C

Figure 3. Maximum Allowed Applied Forward Voltage
vs. Ambient Temperature ReJA = 175°C/W

Figure 4. Relative Luminous Intensity vs. Angular Displacement

158

Fliffl

HEWLETT

5082·4860
5082-4468

RESISTOR LEOs

~~ PACKARD

TECHNICAL DATA

MARCH 1980

MeTAL
PLAstiC
SASE /

O.89(.0351~
O.641.025i

-~-

-,1-

1.40 {,05S)

iiT6 to3O.

15.24

1.600)
MIN,

~t030}

0.51 t.020)

1.._~1.120)
I

2.03 COSOI

NOTES,
1. All DIMENSIONS ARE IN MJLlIMETReS (tNCHE$).
2. SIL..VERPtATeC LEADS. SEE APPLICATIONS
BULLETIN 3.
3. AN EPOXV MENISCUS MAY EXTEND ABOUT 1mrn

5082·4860

DIMENSIONS IN MILliMETRES AND (INCHES)

(.040"} DOWN THE lEADS,

5082-4468

NOTE: AN EPOXY MENISCUS MAY EXTEND ABO!)T
1mm (O.040"} OOWN THE LEADS,

Features

(

• TTL COMPATIBLE: 16mA @ 5 VOLTS TYPICAL
• INTEGRAL CURRENT LIMITING RESISTOR
• T-1 DIAMETER PACKAGE, 3.1Smm (.125 in.)
T-H. DIAMETER PACKAGE, 5.0Smm (.200 in.)
• RUGGED AND RELIABLE

Description
The HP Resistor-LED series provides an integral current limiting resistor in series with the LE D. Applications include panel mounted indicators, cartridge indicators, and lighted switches.
The 5082-4860 is a standard red diffused 5.08mm (.200") diameter (T-1 % size) LED, with long wire wrappable leads.
The 5082-4468 is a clear diffused 3.18mm (.125") diameter (T-1 size) LED.

Absolute Maximum Ratings at TA = 25°C
DC Forward Voltage [Derate linearly to 5V @ 1000 C) .................................. 7.5V
Reverse Voltage ................................................................• 7V
Isolation Voltage [between lead and base of the 5082-4860) ............................... 300V
Operating and Storage Temperature Range ................................. , -55°C to +100°C
Lead Soldering Temperature ............................................. 230°C for 7 sec.

159

Electrical Characteristics at TA =25°C
5082-4860/-4468
Min.

Parametars

Symbol

0.3

Typ.

Max.

Units

0.8

mcd

655

nm

Iv

Luminous Intensity

APEAK

Wavelength

Ts

Speed of Response

15

IF

Forward Current

16

BVR

Reverse Breakdown Voltage

Test Conditions
VF =5.0V
Measurement at Peak

ns
20

3

VF~5.0V

mA

IR '" 100MA

V

TYPICAL RELATIVE LUMINOUS INTENSITY VERSUS ANGULAR DISPLACEMENT
4860

30

4468

1000
800

2.50

600

2.25

/

25
400

«

e
I 20

~
cc
cc

:::>

"
occ

15

/

«

s:cc

/

/

'\

200

2.00

I

'\.

1.7 5

1\,

100
80

'\

60

f( 10

/
/

I

o

I
o
VF - FORWARD VOLTAGE - V

Figure 1. Typical DC Forward Current Voltage Characteristic

1.50

40

I,

20

1.25
1.00

/

.75

"\

.50
.25

1
-75

'I

/

/

V

/

/

V

0
-50

-25

25

50

75

Figure 2. Relative Luminosity vs. Case
Temperature

160

10

100

Te - CASE TEMPERATURE - °C

VF - FORWARD VOLTAGE - V

Figure 3. Relative Luminous Intensity
vs. Voltage

Flid8

HEWLETT

a!~ PACKARD

VOLTAGE SENSING LED 5082·4132
TECHNICAL DATA MARCH 1980

OUTLINE DRAWING

~

BLOCK DIAGRAM

v," 0----,..-.---1------,

COMPARATOR

TEMPERATURE
COMPENSATED
REFERENCE

VOLTAGE

~

r-....._.,
LED

DRIVER

---

...............

NOns:

1. ALL. DIMtNSIONSAR£ IN MILLIMETRES {iNCI-fESI.
2. SIlVi;R PLATED LEADS. SEE APPLICATIONS
BULLETIN 3.

GND.o---+-----------

2.0

1.5

"'::>0
z

~

::
I

2
2
1

~5>C

E

/

V

:E....
~

VIN= 2.75V
VIN =$.OV
VIN: 2.75V
Measurement at peak
Note 1

50

«

I

0;

mA
mA
mcd
nm
nm

50

60

3.0

Fig.

1,2

mVfC

-1

Iv

Ten Conditions

10mV
"OFF"TO "ON"

1.0

17

.5

/

I

....

40

:E
a:

bVlN

~

a:
::>
u

30

ir

20

~

t:.VIN

bi';

I
~

-

1\ /

//

....
~

loon -

10

~

A

ao!)

V

ur~

-"

o

o
V 1N -INPUT VOLTAGE - V

Figure 1. Luminous Intensity vs.

Y,N -INPUTVOLTAGE-V

Figure 2. Input Current vs. Input Voltage.

Input Voltage.

Figure 3. Relative Luminous Intensity vs.
Angular Displacement.

Techniques For Increasing The Threshold voltage
V'TH

I

External Component

V~H

EXTERNAl.

COMPONENT

VTH

r----------l

, 3/.
I

-'--

,

'VOLTAGE

I

,,-' I SENSING

:

: Leo

,

,

V~H
'~:

V~H

V'TH

IIV'TH
TC=--lmVrC)
tlTA

Schottky Diode
VTH + 0.45V

-2

VTH +O.75V

-2.5

VTH +1.6V

-2.9

(HP 5082·2835)
P·N Diode
(1 N914)
LED
(HP 5082·4484)

L._ _ _ _ _ _ _ _ _ _ ...l

-:::-

Notes:

~
v
z

V'TH

V

Zener Diode
VTH +VZ

-1 + Zener TC

TH

1. The dominant wdvelength, Ad, is derived from the CI E chromaticity diagram and represents the single wavelength which
defines the color of the device.
2. ITH is the maximum current just below the threshold, VTH. Since both ITH and VTH are variable, a precise value of
V'TH is obtainable only by selecting R to fit the measured characteristics of the individual devices (e.g., with curve traced.
3. The temperature coefficient (TC) will be a function of the resistor TC and the value of the resistor.

162

. Fltlll'·.;I1EWLETT
II:.~

..

SUBMINIATURE RESISTOR LAMPS
HIGH EFFICIENCY RED

PACKARD

5 VOLT, 4mA • HlMP- 6620
5 VOLT. lOmA • HLMP-6600
TECHNICAL DATA

JANUARY 1980

Features
• IDEAL FOR TTL AND LSTTLGATE
STATUS INDICATION
• REQUIRES NO EXTERNAL RESISTORS WITH
5 VOLT SUPPLY
• SPACE SAVING SUBMINIATURE PACKAGE
• TWO CHOICES OF CURRENT LEVEL
• RUGGED INTEGRAL RESISTOR AND
REVERSE PROTECTION DIODE
• EXCELLENT VIEWING ANGLE

Description

(

Absolute Maximum Ratings

The HLMP-6600 and HLMP-6620 provide a Red
Gallium Arsenide Phosphide on Gallium Phosphide Light Emitting Diode together with an
integral biasing resistor and reverse protection
diode. The package has a red diffused lens and
radial leads. Tape-and-reel mounting is available
on request.

DC Forward Voltage
Reverse Voltage
Operating Temperature Range
Storage Temperature Range
Lead Soldering Temperature
[1.6mm (0.063 in.) from body]

HLMP·6800 HLMP-6820
6 Volts
6 Volts
15 Volts
15 Volts
-55°C to 70·C
-55°C to 100·C

245°C for 5 sec.

package Dimensions
BOTH SIDES

.58 (.0221

l

'94{,g;u}
IN[]29J

~

...J

,1.4 1.46) MIN •
,

~~

1-

.76(J!;l!!JR

~~~

:mi\.ll35J

lc::J

~

\

=

T
1.65 f&!ID OIA
1.91 (.075)
.

~HH~~

TOP VIEW

END VIEW

NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETRES (INCHES).
2. SILVER·PLATED LEADS. SEE APPLICATION BULLETIN 3.
3. USER MAY BEND LEADS AS SHOWN.

SIDE VIEW

163

I

2.921.115)

jx.

Electrical/Optical Characteristics at TA =25°C
Symbol
Parameter
Axial Luminous Intensity
Iv

Min.
1.0

HLMp..6600
Typ.
Mh.

-

2.4

. HLMP-662C)
Typ.
Min.
Mh.

Units

0.2

mcd

0.6

29112

Included Angle Between
Half Luminous Intensity
POints

900

90"

APEAK

Peak Wavelength

635

635

-

Note 1
(See Figure 2)
nm

.~

Ad

Dominant Wavelength

628

628

nm

9j

Thermal Resistance

120

120

'etw

IF

Forward Current

9.6

IR

Reverse Current

TJv

Luminous Efficacy

13

3.5

10

147

Teet CondltlOl'l8
VF == 5 Volts
(See Figure 1)

5
10

147

Measurement at
Peak
Note 2
Junction to
Cathode Lead at
0.79rrim (0.031 in,)
From Body

mA

Vp=5 Volts,
(See Figure 3)

p.A

Vt:~=15

Volts

ImlW Note 3

NOTES:
1. fll/2 is the off-axis angle at which the luminous intensity is half the axial luminous intensity.
2. The dominant wavelength, Ad, is derived from the CIE chromaticity diagram and represents the single wavelength which defi.nes the
color of the device.
3. Radiant intensity. I•• in watts/steradian, may befound from theequation Ie; Iv/~v. where Iv istheluminous intensity in candelas and ~v
is the luminous efficacy in lumens/watt.

1.6
1.4

>

~~
i:j ...
!Zg
-.,
"'0-

I

1.2

"'~~
~a:

1.0

/

O.S

/

0.6

...«2-

0-0

w
a:

I

il

=>«

~!il
:EN

I

0.4

/
A'

0.2

i

!
4

. VF - FORWARD VOLTAGE -VOLTS

Figure 1. Relative Luminous Intensity
Forward Voltage.

Figure 2. Relative Luminous Intensity VI.
Anguhir Disphicament.

VI.

16

«E
I

1.0

14

J

12

V

0-

zw

a:
a:

10

'"
Q

~

V

a:

«
;:
a:

I:

f2
I

.!:

!

0;
2

l!!

HLMI'66OOJ

tJ

>
0-

w

0.5

>

./

V /' HL'4'.e620!

ibV

~

a:

0
550

VF - FORWARD VOLTAGE - VOLTS

750
WAVELENGTH - nm

Figure 3. Forward Current vs. Forward
Voltage.

Figure 4. Relative I ntensity

164

VI.

Wavelength.

F/3 HEW

[-

..01....

Features
• CHOICE OF 4 COLORS
Red
High Efficiency Red

Yellow
Green
• DESIGNED FOR HIGH-RELIABILITY
APPLICATIONS
TO-46

• HERMETICALLY SEALED
• WIDE VIEWING ANGLE
• LOW POWER OPERATION
• IC COMPATIBLE
• LONG LIFE
• PANEL MOUNT OPTION HAS WIRE
WRAPPABLE LEADS AND AN
ELECTRICALLY ISOLATED CASE

Description
The 1N5765, 1N6092, 1N6093, and 1N6094 are hermetically sealed solid state lamps encapsulated in a TO-46
package with a tinted diffused plastic lens over a glass
window. These hermetic lamps provide good on-off
contrast, high axial luminous intensity and a wide viewing
angle.

{

HERMETIC PANEL MOUNT

The 1N5765 utilizes a GaAsP LED chip with a red diffused
plastic lens over glass window.

All of these devices are available in a panel mountable
fixture. The semiconductor chips are packaged in a
hermetically sealed TO-46 package with a tinted diffused
plastic lens over glass window. This TO-46 package is
then encapsulated in a panel mountable fixture designed
for high reliability applications. The encapsulated LED
lamp assembly provides a high on-off contrast, a high
axial luminous intensity and a wide viewing angle.

The 1N6092 has a high efficiency red GaAsP on GaP LED
chip with a red diffused plastic lens over glass window.
This lamp's efficiency is comparable to that of a GaP red
but extends to higher current levels.
The 1N6093 provides a yellow GaAsP on GaP LED chip
with a yellow diffused plastic lens over glass window.
The 1N6094 provides a green GaP LED chip with a green
diffused plastic lens over glass window.

G....n

Description
Base Hermetic Part .

1N6Q94 ..

Base Hermetic Part . :
in Panel~Mount
.
JAN Part
.....

5082-4987
• JANtN6093'

JAN Partin
Panel-Mount
"'ANTX1~ .

JANTX Part

JANTX Part in

. J,ANTXtN6094'

Ml9500/521~2

Panel-Mount
*Panel-Mount versions of all of the above are available per the selection matrix on this page.

165

JAN 1N5765:
Samples of each lot are subjected to Group A inspection for parameters listed in Table I, and to Group
B and Group C tests listed below. All tests are to the conditions and limits specified by MIL-S-19500/467. A summary of
the data gathered in Groups A, B, and C lot acceptance testing is supplied with each shipment.
JAN TX 1N5765:

Devices undergo 100% screening tests as listed below to the conditions and limits specified by MI L-

S-19500/467. The JAN TX lot is then subjected to Group A, Group B and Group C tests as for the JAN 1 N5765 above.

A summary ofthe data gathered in Groups A, Band C acceptance testing can be provided upon request. Serialized data can
be gathered, but lead times will be increased accordingly.
Method
MIL·STD·750

Group B Sample Acceptance Tests
Physical Dimensions

2066

Solderability

2026

Thermal Shock

1056A

Temperature Cycling

1051A

Fine Leak Test

1071H

Gross Leak Test

1071C

Moisture Resistance

1021

Mechanical Shock

2016

Vibration

2056

Constant Acceleration

2006

Terminal Strength

2036E

Salt Atmosphere

1041

Temp. Storage (lOOoe, 340 hours)

1032

Operating Life (50mAdc, 340 hours)

1027

Group C Sample Acceptance Tests

Method
MI L·STD·750

Low Temp. Operation (-55°C)
Breakdown Voltage
Temperature Cycl ing

4021
1051A

Resistance to Solvents
Temp. Storage (lOOoC, 1K hours)
Operating Life (50mAdc, 1K hours)

1031
1026

•

Peak Forward Pulse Current
TX Screening (100%)
Temp. Storage (lOOee, 72 hours)
Temperature Cyciing

1051A

Constant Acceleration

2006

Fine Leak Test

1071H

Gross Leak Test

1071C

Burn-in (50mAdc, 168 hours)
Evaluation of Drift
(lV1' VF , IR)

*MIL-STO-202 Method 215

Electrical/Optical Characteristics at TA=25°C
(Per Table I, Group A Testing of MI L-S 19500/467)
Specification
Luminous Intensity (Axial)

Symbol

Min.

Max.

IV1

0.5

3.0
I

Luminous Intensity (off Axis)

IV2

0.3

Wavelength

Av

630

Capacitance

C

300

Forward Voltage

VF

2.0

IR

1

Reverse Current

Units

I

Test Conditions

e = 0°

mcd

IF = 20mAdc,

mcd

IF = 20mAdc, 0 = 30 0 [see Note 1J

---

-

700

NOTES:

1. These specifications apply only to JAN/JAN TX levels.

166

nM
pF

-

I

V

=

0, f = 1 MHz

R
1--------------------

~

/JAde

---

Design Parameter

I

IF =20mAde

-------

VR = 3 Vdc [see Note 1 J

Absolute Maximum Ratings at TA=25°C
Parameter

[

Red
1N5765/4787

High Eff. Red
1N6092/4687

100

120

Power Dissipation
(derate linearly from 50°C at
1.6mW/OC)

50(11

DC Forward Current

1000
See Fig. 5

Peak Forward Current

Yellow
Green
1N6093/4587 1N6094/4987
120

35 121

35 121

60

60

See Fig. 10

See Fig. 15

Operating and Storage
Temperature Range

Units

120

mW

35[21

rnA

60
See Fig. 20

mA

-65°C to 100°C

Lead Soldering Temperature
[1.Smm (0.063 in:) from body]

260° C for 7 seconds.

1. Derate from 50° C at 0.2mAfO C
2. Derate from 50°C at 0.5mAfOC

Electrical/Optical Characteristics at TA =25°C
Symbol

Description

h

Axial Lumtnous
Intensity

2(0)1 ,

1N5765/5082-4787 1N6092/5082-4687 1 N6093/5082-4567
Min.

Typ.

0.5

1.0

Max.

Min.

Typ.

1.0

2.5

Max.

Min.

Typ.

1.0

2.5

Max.

lN6094/5082-4987

Min.

Typ.

osltsJ
At IF

60

Incli.Jded Angle
Between Half
Luminous Interlsity

~

Unitt

T••, Condltlont
IF - 20mA

mcd

Figs. 3,8,13.18

deg.

NOie 1. Figures

25mA

70

70

70

Max.

6.11,16.21

POints

635

ApC\f.",

Peak Wavelength

655

Ad

Dominant WaveJe,lgth

640

626

7S

Speed of Response

10

200

I Capacitance-

565

nm

Measurement
at Peak

585

570

nm

Note 2

200

200

ns

583

200

35

35

35

Hjc

Thermal ResistancE!'"

425

425

425

425

ale

Thermal Resistance*"

550

v,·

Forward Voltage

1.6

C

550
2.0

2.0

550

3.0

2.0

pF

550
3.0

2.1

3.0

Reverse Breakdown-

4

5

50

5.0

5.0

1=1 MHz

Note 3

°C/W

Noie3

V

IF = 20mA
Figures 2. 7.
12. 17

V

IR

At IF =2SmA
BVR

V,~O;

'CIW

= 100~A

Voltage
~,

Luminous Efficacy

56

455

140

600

ImlW

Note 4

NOTES:
1. 81/2 is the off-axis angle at which the luminous intensity is half the axia~ iuminous intensity.
2, The domi'1ant wavelength, Ad, is derived from the CIE chromaticity diagram and represents the single wavelength which defines the color of the device,
3. Junction to Cathode Lead with 3.18mm (0.125 inch) of leads exposed between base of flange and heat sink.
4. Radiant intensity. Ie, in watts/steradian, may be found from the equation Ie = Iv/17v, where Iv is the luminous intensity in candelas and 17'1 is the luminous
efficacy in lumens/watt.
*panel mount.
"TO-46

WAVELENGTH - nm

Figure 1. Relative Intensity vs. Wavelength.

167

package Dimensions

1N5765, 1N6092,1N6093, 1N6094

5082·4787,4687,4587,4987
TINTel) PLASTIC
OVER GLASS LEN$

RED 1NS76S/S082-4787

..

2.5,---,---,-_-,_ _,-_.,

50

1I

..Ci
a:
a:

""a:

T.'~C

20

,.

II

ZN
i::::i

>1:1

r

I

.!"

.5

1/
'

v

00

.

10

20

-.

...

--

.5

~

30

••

50

Figure 3. Relative Luminous Intensity
VI. Forward Current.

Figure 2. Forward Current VIIForward Voltage.

~;!

~"
wa:
a:o

IF - FORWARD CURRENT - mA

VF- FORWARD VOLTAGE - VOLTS

.... ...
-

1.0

wo
wW

• /.

~!E
wa:

~

"2S"J

it~

3 ~ 1.0 i--+---iI''----t--:-:-+-''--l

~
a:

TA

U

>0

U/
"0"_"1il 1.5

0

1.5

.

~/
z _ 2.0 t-'--+--+---t-,-t,.;"'"--l

30

00

50

100

150

200

250

300

360

IpEAK - PEAK CURRENT - mA

Figure 4. Relative Efficiency
(Luminous Intensity per Unit
Currentl vs. Peak Current.

1N5765/4787

\-:::l:-+4-+4-1--1f-+-+-++-I,·0
\.---1--+-+-1-11-+-+-+-++-+--10.75
)....~I-t-+--t\++-+-+--l-HO.5.

""'+-+-f--+-'k:-t--t-i-+-+--;O.25

tp -

PULSE WIDTH - p.s

Figure 5. Maximum Tolerable Peak Current
(lDC MAX as per MAX Ratin9sl

VI.

Figure 6. Relative Luminous Intensity

Pulse Duration.

168

VI.

Angular Displacement.

HIGH EFFICIENCY RED 1N6092 I 5082-4687
80

1.6

2.00

0

1.75

~<

1.50

~

I

(

>

:1

~~

,

~~

1.25

ZW

1,00

00

~j
~.

0

w'

V

0

/

075

>~

I

0

/

3.0

2.5

3.4

1.0

....

~

.6

/

0.25
0.00

2.0

1.2

/

/

~~ 0.50

g-

1.'

/

V
5

10

15

21)

25

30

35

.6

0

IF - FORWARD CURRENT - rnA

VF - PEAK FORWARD VOLTAGE - V

Figure 7. Forward Current VS.
Forward Vo Itage.

60
IpEAK - PEAK CURRENT - rnA

Figure 8. Relative Luminous Intensity
VS. Forward Current.

Figure 9. Relative Efficiency
(Luminous Intensity per Unit

Current) vs. Peak Current.

tp - PULSE DURATION -f.lS

Figure 10. Maximum Tolerable Peak Current vs. Pulse Duration. (lDC MAX
as per MAX Ratings)

Figure 11. R elat ive Lu mino us Intensity vs. Angu lar 0 isplacement.

YELLOW 1N6093/5082-4587
6Q

"

50

~

,.

I

f

~

.

II

1

I

r

I

~

I

I

"

i

,

1

10

o

10

2.25

I I

I

1

2.5

3.0

,/

A

V
0.00
3.4

VF - PEAK FORWARD VOLTAGE - V

Figure 12. Forward Current ys.
Forward Voltage.

5

10

15

20

25

30

35

IF - fORWARD CURRENT - rnA

Figure 13. Relative Luminous Intensity
VS. Forward Current.

6

. 0

1/"1

'/

/

6

0.25

~//

I

0

/

10

1
20

30

50

60

Figure 14. Relative Efficiency
(Luminous Intensity per Unit
Current) vs. Peak Current.

Figure 16. Relative Luminous Intensity ys. Angular Displacement.

169

40

IpEAK - PEAK CURRENT - rnA

tp - PULSE DURATION - /-IS

Figure 15. Maximum Tolerable Peak Cur·
rent YS. Pulse Duration. (lDC MAX
as per MAX Ratings)

J,.-

-I

-

I

II

2

1/

0,50

i!

'

/

1

1,00

0.75

,,

~•• 25'~

/

1,50

1.25

I

1.5

,

/

1,75

J

1

6

2,00

GREEN 1N6094/S082-4987

a~

I

I

40

1/

o

~

30

I

~

i I 1 VI

;.,i

10

o

1.0

15

2.00

II

I

!

,i+

11

1.50

-~

4

/

1.25
1.00

/'

0.50
0.25

I;I

0.00
3.4

VF - PEAK FORWARD VOLTAGE _ V

Figure 17. Forward Current vs.

Forward Voltage.

+..... 6

I

0.75

Il
3.0

1.6

!
I

1.75

V

I
I
0

V
10

15

20

25

30

6
. 0

35

IF - FORWARD CURRENT - rnA

Figure 18. Relative Luminous Intensity
vs. Forward Current.

",'"

.-

/

L_

,/
5

... "

2

/r-

/
10

20

30

20

0

u
u 1.]2

0

1.5
1.4
1.3

~~

~E

12
1.1
1.0

1
tp -

PULSE DURATION -!l$

Figure 20. Maximum Tolerable Peak Cur·
rent vs. Pulse Duration. Ope MAX
as per MAX Ratings)

Fisure 21. Relative Luminous Intensity

170

60

(Luminous Intensity per Unit
Current) vs. Peak Current.

~

l

50

Figure 19. Relative Efficiency

2

~
~

40

IpEAK - PEAK CURRENT - mA

vs. Angular Displacement.

o

c

Flin-

HEWLETT

~~ PACKARD

.CLIP AND RETAINING
RING FOR PANEL 5082-4707
MOUNTED LEOS
TECHNICAL DATA MARCH 1980

Description

NOTES: 1. DIMENSIONS IN MILLIMETERS (INCHES).

1;7." !2BOID'A.N----r

The 5082-4707 is a black plastic mounting clip
and retaining ring. It is designed to panel mount
Hewlett Packard Solid State high profile T - 1%
size lamps. This clip and ring combination is intended for installation in instrument panels up to
3.18mm (.125") th ick. For panels greater than
3.18mm (.125"), counterboring is required to the
3.18mm (.125") thickness.

,~

}';f'

~,j,...---~~~
r
bl -l

I I.-

5.2 (:'OSI

1.--8,00 (,315)

I

]

1J

3. Press the LED into the clip from the
back. Use blunt long nose pliers to push
on the LED. Do not use force on the
LED leads. A tool such as a nut driver
may be used to press on the clip.

4. Slip a plastic retaining ring onto the back
of the clip and press tight using tools such
as two nut drivers.

171

!IJ

1:"--6.86 1.2701 D'A.--I

I

9.53 (.375 J D I A . _

RETAINING
RING

Mounting Instructions

2. Press the panel clip into the hole from
the front of the panel.

III.

DIA.~

CLIP

1. Drill an ASA C size 6.15mm (.242") dia.
hole in the panel. Deburr but do not
chamfer the edges of the hole.

2 TOLERANCES-.25!.O'OI.

,f

..~.

172

·,

-,

,.

~"t;',~'"

'.

~

''..:;

:",'

'.

( J

.L •;

..

:"',

'

"

Solid State Displays
• Selection Guide, '. .'. . . . . . . . . . . . .. 17 '
• Red, HighE{fidency .Red, Yellow
and GreenSe~Segment Displays

c

'. Red Seven s.egment ,Displays'
"

• -.o '

• Integrated, Displays "
• Hermetically Sealed Integrated
Displays
• Alphanumeric Displays

173
•• "

'"

••

d

••

"

•••

_.

"

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....

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..... u ••

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..,_- • • • • _ _ _ _ , , _ . - ,

H'

.~

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•

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".,."~''''.''''''·

..... ,'.. ,,.. _.~''''., ... ~>

•••

Red, High Efficiency Red, Yellow and Green Seven Segment LED Displays
Package
....,......+

+

:0=0;

~O=O.
+

+

-

,....--

+
+

+

+

:£,0:

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+
+
i.--

Device

[fi

5082-7610

High Efficiency Red, Common Anode, LH DP (14 Pin
Epoxy)

5082·7611

High Efficiency Red, Common Anode, RHDP (14 Pin
Epoxy)

5082-7613

High Efficiency Red, Common Cathode, RHDP
(10 Pin Epoxy)

~

5082-7616

7.11mm (.29") High Efficiency Red, Universal Polarity
Overflow Indicator RHDP (14 Pin Epoxy)

5082-7620

Yellow, Common Anode LHDP (14 Pin Epoxy)

5082-7621

Yellow, Common Anode RHDP (14 Pin Epoxy)

R

Green, Common Anode LHDP (14 Pin Epoxy)

5082-7631

Green, Common Anode RHDP (14 Pin Epoxy)

5082-7650

High Efficiency Red, Common Anode, LH DP

5082-7651

High Efficiency Red, Common Anode, RH DP

5082-7653

High Efficiency Red, Common Cathode RHDP

5082-7656

10.36 (.4") High Efficiency Red Universal Polarity
and Overflow Indicator RH DP

5082-7660

Yellow Common Anode LHDP

5082-71161

Yellow Common Anode RHDP

0

5082-7663

Yellow Common Cathode RHDP

0

5082-7666

10.36 (.4") Yellow Universal Polarity and
Overflow Indicator RHDP

5082-7670

Green Common Anode LHDP

~

+

[]

+

0

5082-7630

5082-7636

+

[f.

+c:::::l

5082-7626

Green, Common Cathode RHDP (10 pin Epoxy)

: O=u.
:O=U:l'

+

Yellow, Common Cathode, RH DP (10 Pin Epoxy)
7.11mm (.29") Yellow, Universal Polarity and
Overflow Indicator RH.DP (14 Pin Epoxy)

7.11mm (.29") Green, Universal Polarity and
Overflow Indicator RH DP (14 Pin Epoxy)

+

~

5082-7623

5082-7633

7.62mm (_3")
Dual-In-Line
.75"H x .4"W x .18"D

: a

Description

0

+

+
+
+

5082-7671

Green Common Anode RHOP

5082-7673

Green Common Cathode RHOP

5082-7676

10.36 (,4") Green Universal Polarity and Overflow
Indicator RHDP

HDSP-3530

High Efficiency Red, Common Anode, LHOP (14 Pin
Epoxy)

:0=0:
.0=0.

+a 0+·
:=tfo0:

HDSP-3531

High Efficiency Red, Common Anode, RHDP (14 Pin
Epoxy)

-

-

HOSP-3533

High Efficiency Red, Common Cathode RHOP
(10 Pin Epoxy)

HOSP-3536

7.11mm (.29") High Efficiency Red, Universal Polarity
Overflow Indicator. RH OP (14 Pin Epoxy)

10.92mm (.43")
Dual-In-Line
.75"H x .5"W x .25"0
(14 Pin Epoxy)

+

+

+

+

-

+

+
+

+

~

+

t

+

R

HOSP-4030 Yellow, Common Anode, LHOP (14 Pin Epoxy)
HOSP-4031 Yellow, Common Anode, RHOP

7.62mm (.3")
Oual-In-Line
.75"H x .4"W x .18"0

HOSP-4033 Yellow, Common Cathode, RHOP (10 Pin Epoxy)
HOSP-4036

7.11mm (.29") Yellow, Universal Polarity Overflow
Indicator RHOP (14 Pin Epoxy)

174

Application
General Purpose Market
• Test Equipment
• Digital Clocks
• Clock Radios
• TV Channel Indicators
• Business Machines
• Digital Instruments
• Automobiles
For further information see
Application Notes 941 and 964
beginning on page 332.

Page
No.
180
~, ;

""""1il5

F

~~
190

Red, High Efficiency Red, Yellow and Green Seven Segment LED Displays (Cant.)
Package

[

+

+

:O=~

:0=0:l'

~

Device

[J

,

+

u:

: a

+=0'
a +
+
+

0

+

10.92mm (.43")
Dual-ln·Line
.75"H x .5"W x .25~:D
(14 Pin Epoxy)
~

High Efficiency Red, Common Anode, LH DP

HDSP·3731

High Efficiency Red, Common Anode, RH DP

HDSp·3733

High Efficiency Red, Common Cathode, RHDP

HDSP·3736

10.36mm (.4") High Efficiency Red, Universal
Polarity Overflow Indicator RHDP

HDSp·4130

Yellow, Common Anode LHDP

HOSP·4131

Yellow, Common Anode RHDP

HDSP·4133

Yellow, Common Cathode RHDP

HDSP·4136

10.36mm (.4") Yellow, Universal Polarity
Overflow Indicator RHDP

5082-7730

Red, Common Anode, LHDP
(14 Pin Epoxy)

+

,

+

a O-t

+

~

:0=0:
IiU=O~
+

:0o0:

'---

~

+

5082·7731

Red, Common Anode, RHDP
(14 Pin Epoxy)

I

I

VVVVVVV

5082-7736

7.11 mm (.29") Red, Common Anode, Polarity and
Overflow Indicator (14 Pin Epoxy)

7.62mm (.3")
Dual·ln-Line
.75"H x .4"W x .18"D

5082-7740

Red, Common Cathode, RHOP
(10 Pin Epoxy)

+

+

5082-7750

Red, Common Anode, LH DP

:O=~
:0=0:l'

5082-7751

Red, Common Anode, RHDP

~

5082-7756

10.36mm (.4") Red, Universal Polarity and
Overflow Indicator, RHDP

10.92mm (.43")
Dual-In-Line
.75"H x .5"W x.. 25"D
(14 Pin Epoxy)

5082-7760

Red, Common Cathode, RHDP

HDSP-3400

Red, Common Anode LHDP

HDSP-3401

Red, Common Anode RHDP

HDSP-3403

Red, Common Cathode RHDP

HDSP-3405

Red, Common Cathode LHDP

HDSP-3406

18.87mm (.74") Red, Universal Polarity
Overflow Indicator RHDP

Application

General Purpose Market
• Test Equipment
• Digital Clocks
• Clock Radios
• TV Channel Indicators
• Business Machines
• Oigitallnstruments
• Automobiles

Page
No.
190

For further information see
Application Notes 941 and 964
beginning on page 332.

f-----

..---

+

+

[

HDSP·3730

0

+

,

Description

196

r--200

r--

~D
+0+
+
+

+
+

(it

0

20.32mm (.8")
Dual-I n· Line
1.09"H x .78"W x .33"D
(18 Pin Epoxy)

175

204

Red Seven Segment LED Displays
Description

Device

r;o:m'
~

2.79mm{.II'" Red, 3 Digits
Right,llI Centered D.P.
2.79mm{.II'" Red. 3 Digits
Left,!11 Centered D.P.
2.79mm(.11'" Red, 4 Digits
Centered D.P.
2.79mmI.11'" Red, 5 Digits,
Centered D.P.
2.79mm (.11", Red, 3 Digits
Right,Il1 RHDP
2.79mm (.11", Red, 3 Digits
Left,Il1 RHDP
2.79mm(.II'" Red, 4 Digit,
RHDP
2.79mm(.II'" Red, 5 Digit,
RHDP

12 Pin Epoxy,
7.62mm {.3'" DIP

5082·7432

2.79mm(.II", Red, 2 Digits
Right,!21 RHDP

12 Pin Epoxy,
7.62mm (.3'" DIP

5082·7433

2.79mm(.II'" Red, 3 Digits,
RHDP

5082·7402
5082·7403
5082·7404
5082·7405
5082·7412

A

5082·7413
5082·7414
5082·7415

em
II~II~

14 Pin Epoxy,
7.62mm {'3'" DIP
12 Pin Epoxy,
7.62mm (.3'" DIP

14 Pin Epoxy,
7.62mm (.3'" DIP

5082·7449

2.67mm(.,105", Red, 9 Digits,
Mounted on P.C. Board
2.67mm(.105'" Red, 9 Digits,
Mounted on P.C. Board

50.8mm(2'" P.C. Bd.,
17 Term. Edge Con.
60.3mm(2.375",PC Bd.,
17 Term. Edge Con.
50.8mm(2", PC Bd.,
17 Term. Edge Can.
60.3mm(2.375",PC Bd.,
17Term. Edge Con.

5082·7442

2.54mm(.100'" Red,12 Digits,
Mounted on P.C. Board

60.3mm(2.375",PC Bd.,
20 Term. Edge Con.

5082·7445

2.54mm(.100'" Red, 12 Digits,
Mounted on P.C. Board

59.6mm(2.34S",PC Bd.,
20 Term. Edge Con.

5082·7444

2.54mm(.100'" Red, 14 Digits,
Mounted on P.C. Board

60.3mm(2.37S'" PC Bd.,
22 Term. Edge Can.

5082·7446

2.92mm(.115'" Red, 16 Digits, 69.85mm(2.750",PC Bd.,
24 Term. Edge Can.
Mounted on P.C. Board

5082·7447

2.85mm(.112'" Red,14Digits,
Mounted on P.C. Board

60.3mm(2.375") PC Bd.,
22 Term. Edge Con.

5082·7240

2.59mm(.102") Red, 8 Digits,
Mounted on P.C. Board

50.8mm (2") PC Bd.,
17 Term. Edge Con.

5082·7440
5082·7448
5082·7441

I~II~

Package

2.67mm(.105'" Red, 8 Digits,
Mounted on P.C. Board
2.67mm(.105", Red, 8 Digits,
Mounted on P.C. Board

Page
No.
208

Application
Small Display Market
• Portable/Battery
Power Instruments
• Portable Calculators
• Digital Counters
• Digital Thermometers
• Digital Micrometers
• Stopwatches
• Cameras
• Copiers
• Digital Telephone
Peripherals
• Data Entry Terminals
• Taxi Meters
For further information ask for
Application Note 937.

-

212

r--z;s

r-220

"",""RlOOaaOOPRD

I~I~

2.59mm(.102") Red, 9 Digits,
Mounted on P.C. Board.
4.45mm(.175") Red, 5 Digits,
5082·7265 Mounted on P.C. Board.
Centered D.P.
4.45mml.175") Red, 5 Digits
5082·7285 Mounted on P.C. Board. RHDP
4.45mm(,175") Red, 15 Digits,
5082·7275 Mounted on P.C. Board.
Centered D.P.
4.45mml.175'" Red, 15 Digits,
S082·7295 Mounted on P.C. Board. RHDP

-

5082·7241

laml
."

~

176

50.8mm(2") PC Bd.,
15 Term. Edge Can.

91.2mm(3.59") PC Bd.,
23 Term. Edge Can.

224

r-m

Integrated LED Displays
Devica

,
i

1::1 l::i
~VJ~
m
!~:!

Description

Package

7.4mm (.29") 4x7 Single Digit
Numeric, RHOP, Built·ln
oecover/0 river/Me mory
7.4mm (.29") 4x7 Single Digit
5082·7302 Numeric, LHDP, Built·ln
Decover/Driver/Memory
7.4mm (.29") 4x7 Single Digit
5082·7340 Hexadecimal, Built·ln
Decoder/Driver/Memory
7.4mm (.29") Overrange
5082·7304 Character Plus/Minus Sign
7.4mm (.29") 4x7 Single Digit
5082·7356 Numeric, RHOP, Built·ln
Decoder/Driver/Memory
7.4mm(.29") 4x7 Single Digit
5082·7357 Numeric, LHDP, Built·ln
Decoder/Driver/Memory
7.4mm (.29") 4x7 Single Digit
5082·7359 Hexadecimal, Built·ln
Decoder/Driver/Memory
7.4mm{.29") Overrange
5082·7358
Character Plus/Minus Sign
5082·7300

Application

8 Pin Epoxy,
15.2mm (.6") DIP

General Purpose Market
• Test Equipment
• Business Machines
• Computer Peripherals
• Avionics
For further information ask
for Application Note 934 on
LED Display Installation
Techniques

8 Pin Glass Ceramic
15.2mm (.6") DIP

• Medical Equipment
• Industrial and Process Control
Equipment
• Computers
• Where Ceramic Package IC's
are required.

Page
No.
232

236

Hermetically Sealed Integrated LED Displays
Device

Description

rn ] Q

6.8mm (,27") 5x7 Single Digit
Numeric, LHDP, Built'ln
Decoder/Driver
6.8mm (.27") Plus/Minus
5082·7011
Sign
7.4mm (.29") 4x7 Single Digit
5082·7391 Numeric, RHDP, Built·ln
Decoder/Driver/Memory
7.4mm(.29") 4x7 Single Digit
5082·7392 Numeric, LHDP, Built·ln
Decoder/Driver/Memorv
7.4mm('29") 4x7 Single Digit
5082·7395 Hexadecimal, Built·ln
Decoder/Driver/Memory
7.4mm{.29") Overrange
5082·7393 Character Plus/Minus Sign
5082·7010

I:;j

,;..1.

r

~:::i

0

nmt

Application

Package
8 Pin Hermetic
2.54mm (.100") Pin
Centers

• Ground, Airborne,
Shipboard Equipment
• Fire Control Systems
• Space Flight Systems

8 Pin Hermetic
15.2mm (.6") DIP
with Gold Plated Leads

• Ground, Airborne,
Shipboard Equipment
• Fire Control Systems
• Space Flight Systems
• Other High Reliability
Applications

Page
No.
241

247

Alphanumeric LED Displays
Device
c-,
, , ,+,
, , , , ,+,
, ,
,+,
C-]II

If'

LJ LJ

l~J L_J

Description

Application

Package

3.7mm (.15") 5x7 Four Char·
HDSp·2000 acter Alphanumeric Built·ln
Shift Register, Drivers

1mW
177

12 Pin Ceramic 7.62mm
(.3") DIP. Redglass
Contrast Filter

•
•
•
•
•

Programmable Calculators
Computer Terminals
Business Machines
Medical Instruments
Portable, Hand·held or
mobile data entry, read·
out or communications
For further information see
Application Notes 966 and 1001,
starting on page 368.

Page
No.
253

Alphanumeric LED Displays (Cont.)
Device

[±]
~_2"_J

L_!_J
, + ,

~

Fl

Description
3.7mm (.15") 5x7 Four Char·
HDSp·2001 acter Alphanumeric Built·ln
Shift Register, Drivers

~

HDSP·2010

~~

].,=,,1

-==
0

[]9

r--l

[]9;
[]9!
[Il'

o~

$'

Om )
:

:0.,0

U·

!

BOD

.0

Package

$

•

'..'1

Eb'@o~

fDXXXXA ][
I
I

Single· Line 16 Character
HDSp·2416 Display Panel Utilizing
the HDSp·2000 Display
Single·Line 24 Character
HDSP·2424 Display Panel Utilizing
the HDSP-2000 Display.
Single·Line.32 Character
HDSp·2432 Display Panel Utilizing
the HDSP·2000 Display
Single·Line 40 Character
HDSP·2440 Display Panel Utilizing
the HDSp·2000 Display
HDSP-2000 Display Inter·
HDSP-2470 face Incorporating a 64
Character ASCII Decoder
HDSP-2000 Display Inter·
HDSp·2471 face Incorporating a 128
Character ASCII Decoder
HDSP-2000 Display Inter·
face without ASCII De·
coder. Instead, a 24 Pin
HDSP-2472 Socket is Provided to
Accept a Custom 128
Ch aracter Set from a
User Programmed 1K x
8PROM
3.56mm (.14") Eighteen
HDSP-63M Segment Eight Character
Alphanumeric

12 Pin Ceramic 7.62mm
(.3") DIP Integral
Untinted Glass Lens

257

162.56mm (6.4") Lx
58.42mm (2.3") H x
7.11mm (.28") 0

265

,

26 Pin 15.2mm
(.6") DIP

22 Pin 15.2mm
(.6") DIP
26 Pin 15.2mm
(.6") DIP

178

• Data Entry Terminals
• Instrumentation
• Electronic Typewriters
For further information see
Application Note 1001
beginning on page 398.

261

177.80mm (7.0") Lx
58.42mm (2.3") H x
7.11mm (.28") D
171.22mm (6.74") Lx
58.42mm (2.3") Hx
16.51mm (.65") D

Cc::IClCClClClCCOClc:lClCl

1] ~

•
•
•
•
•

Page
No.

Programmable Calculators
Computer Terminals
Business Machines
Medical Instruments
Portable, Hand·held or
mobile data entry, read·
out or communication
For further information see
Application Notes 966 and
1001, starting on page 368.
12 Pin Ceramic 7.62mm • Extended temperature
(.3") DIP Integral
applications requiring
Red Glass Contrast Filter. high reliability.
• I/D Terminals
• Avionics

ClC"'CClI:I"'::":''''''"'''''

3.8mm (.15") Sixteen
HDSP-6504 Segment Four Character
Alphanumeric
3.8mm (.15") Sixteen
HDSP-6508 Segment Eight Character
AI phanumeric

Application

• Computer Peripherals and
Terminals
• Computer Base Emergency
Mobile Units
• Autom otive Instrument
Panels
• Desk Top Calculators
• Hand·held Instruments
For further information ask for
Application Note 931.

277

282

Alphanumeric LED Displays (Cont.)
Device

[

'"

o~o

o

.";

.".'

Description
HDSP-8716

0

;Ii

i11

HDSP-8724

~

0

0

0

0

i.: i!
~I

lJ

0

218.44mm (8.6")l
x 58.42mm (2.3")H
x 33mm (1.3")0

HDSP-8740

Single·line 4'0 Character
Alphanumeric Display
System Utilizing the
HDSP·6508 Display

269.24mm (10.6") l
x 58.42mm (2.3") H
x 33mm (1.3")D

7.4mm (.29") 5x7 Three
Digit Alphanumeric
7.4mm (.29") 5x7 Four
Digit Alphanumeric
7.4mm (.29") 5x7 Five
Digit Alphanumeric

22 Pin Hermetic
15.2mm (.6") DIP
28 Pin Hermetic
15.2mm (.6") DIP
36 Pin Hermetic
15.2mm (.6") DIP

I

V~~~~~

t

5082-7100
5082·7101
5082·7102

Application

Page
No.

• Data Entry Terminals
• Instrumentation
• Electronic Typewriters

288

General Purpose Market
• Business Machines
• Calculators
• Solid State CRT
• High Reliability Applications
For further information ask for
Application Note 931 on
Alphanumeric Displays.

300

Single-I ine 24 Character
Alphanumeric Display
System Utilizing the
HDSP-6508 Display

Single-line 32 Character
Alphanumeric Display
System Utilizing the
HDSP-6508 Display

0

O[

167.64mm (6.6")l
x 58.42mm (2.3")H
x 33mm (1.3")D

Single·line 16 Character
Alphanumeric Display
System Utilizing the
HDSP-6508 Display

HDSP-8732

I~:

:'

Package

r

179

TECHNICAL DATA

MARCH 1980

Features
• COMPACT SIZE
• CHOICE OF 3 BRIGHT COLORS
High Efficiency Red
Yellow
Green
• LOW CURRENT OPERATION
As Low as 3mA per Segment
Designed for Multiplex Operation
• EXCELLENT CHARACTER APPEARANCE
Evenly Lighted Segments
Wide Viewing Angle
Body Color Improves "Off" Segment
Contrast
• EASY MOUNTING ON PC BOARD OR
SOCKETS
Industry Standard 7.62mm (.3 in.) DIP
Leads on 2.S4mm (.1 In.) Centers

Description

• CATEGORIZED FOR LUMINOUS
INTENSITY; YELLOW AND GREEN
CATEGORIZED FOR COLOR
Use of Like Categories Yields a
Uniform Display

The 5082-7610, -7620, and -7630 series are 7.62mm (.3in.) High
Efficiency Red, Yellow, and Green seven segment displays.
These displays are designed for use in instruments, pOint of sale
terminals, clocks, and appliances.
The -7610, and -7620 series devices utilize high efficiency LED
chips which are made from GaAsP on a transparent GaP
substrate.

• IC COMPATIBLE
• MECHANICALLY RUGGED

The -7630 series devices utilize chips made from GaP on a
transparent GaP substrate.

Devices
':{,

Part No. 508~ .'
,

~7610

":7611.
'. -7613 .
'. ~7616

-7620 .'

Cotot ,.'

",'

,

......~ ..

High Efficiency Red·; .eorrll:nof! Anode left Hand Decimal'
. ". High EffiCiency. Reel' • •Common Mode Right Hand !)$elma'
'. HigllEfficiEmcy Red:: . Common Cathwe Right Hand Decimal
'... ~High effjCienOyRed~:· :1jniversal Overtlow ±1 Right Hand Decimal
.' ,.yellow ,. ..•. . ..:mmonArlOde left Hand Decimal

Package .

Drawing
.A
B

D

C
'0 .., ..
A· '

NOTE: universal pinout brings the anode and cathode of each segment's LED out to separate pins. See internal diagram D.

180

package Dimensions

(

"

..,

o

A,B,C

LUMINOUS
INTENSITY
CATEGORY

_I~

F

.2541.010)
1.52

~

~.:21.04:1
I
~J.- Ll

15.24
1.600)

2.541.100)

-T~t

0.S1
1.020)

A,B,C,O
END

C
SIDE

A,B,O
SIDE
NOTES:

1. Dimensions in millimeters and (inches).
2. All untoleranced dimensions are
for reference only

3. Redundant anodes.

4.
5.
6,
7.

Unused dp posit ton.
See Internal Circuit Diagram.
Redundant cathode.
See part number table for l.H.D.P. and R.H.D.P. designation.

Internal Circuit Diagram

A

C

B

o

Absolute Maximum Ratings
Average Power Dissipation Per Segment or D.P.(1) (TA=SO°C). . .......... 81mW
Operating Temperature Range ................................. -400C to +8SoC
Storage Temperature Range ................................... -400 C to +8So C
Peak Forward Current Per Segment or D.P.(3) (TA=50°C) .................... 60mA
Average Forward Current Per Segment or D.P. (1.2) (TA = SO°C) .............. 20mA
Reverse Voltage Per Segment or D.P ........................................ 6.0V
Lead Soldering Temperature ................................... 260° C for 3 Sec
[1.S9mm (1/16 inch) below seating plane l4 ) I

181

Notes: 1. See power derating curve
(Fig. 2). 2. Derate DC current from
50'C at OAmAI"C per segment
3. See Fig. 1 to establish pulsed
operating conditions. 4. Clean only in
water, isopropanol, ethanol, Freon
TF or TE (or equivalent) and Gene~
sol v 01-15 or DE-15 (or equivalent).

Electrical/Optical Characteristics at TA =2S 0 C
HIGH EFFICIENCY RED 5082-7610/-7611/-7613/-7616
Parameter

Symbol

Luminous Intensity/Segment (5.S,
I,.
(Digit Average)
Peak Wavelength

Test Condition

Mm.
70

5mAD.C.
2DmA D.C.
60mA Pk: 1 of 6
Duty Factor

"d

(M

Forward Voltage/Segment or D.P.

VF
.'.

Reverse Current/Segment or D.P.

Ill..

Response Time,a,

unl~:'r
/-led

Max•.

250
1430

I'/-Ied<
'.).ICd

',1

810
635

. ApEAK

Dominant Wavelength

Typ.

om

626
IF = 5mA
I" =20mA
i F =60mA

1.7
2.0
2.8

'.

om.

1

".

'

..2.5

V

...... >:

10

VI\=6V

t,. tl

90

Temperature Coefficient of VF/Segment or D.P.

IJ,VFioC

~2.0

Thermal Resistance LED Junctlon-to-Pin

ROJ-PIN

282

"-

/-IA
.

rt$

mvrc
'.

·C/Wi·
seg.··•.··.

YE L LOW 5082-7620/-7621/-7623/-7626
Symbol

Parameter
Luminous Intensity/Segment IS."

I.

(Digit Average)
Peak Wavelength
Dominant Wavelength i6.7.

"PEAK
AJ

Forward Voltage/Segment or D.P.

.V,

IH

Reverse Current/Segment or D.P.

Test Condition
5mA D.C.
20mA D.C.
60mA Pk: 1 of 6
Duty Factor

Min.

Typ.

90

200
1200

IF = 5mA
IF -·20mA
IF = 60mA
V~

/.led

/.Icd<

r

740

j.l<;:d

583

nm.

585

nm

1.8
2.2
3.1

= 6V

Untte

Max.

V

2.5

'.'

10

J.tA
..

os

Response Time ia,

t" t,

Temperature Coefficient of V";Segment or D.P.

vFrC

-2.0

mvre

ROJ-PIN

282

·CIW/

Thermal ReSistance LED Junction-to-Pin

90

'

. Seg:.·

GREEN 5082-7630/-7631/-7633/-7636
Parameter

. Symbol

Luminous IntensitylSegment

I5 .,)

i

I,

(Digit Average)
'.

Peak Waveiength
Dominant Wavelength '6,7'

'.

Porward Voltage/Segment or D.P.

Reverse Current/Segment or.D.P..
Response Time ,BJ

..

'

Temperatureeoefficient of.VF1Segment or D.P.
Thermal Resistance LED Junction-to-Pin .

. Test Condition.

Min•
.150
..

lOrnA D.C.
20mAD.C.
60mA Pk: 1. of~ .
Duty.Pactor

'

Typ.

:300· ................
765 I":

•

I'.' .540'

ApEAK

565

AJ

572

Vf

IF

If'" 5mA
IF:" 20mA .
1,"'60mA
VR =6V

.'

.

I,,!, .
AVFf'>C

..

"

"
.'

."

','

..
..

~Cd:>

.. hitt
.'

2.5 . . .

rim··

........•..

,v

..•..............
./,#A·L

90 . ....
":"2:0

• "Acd ......
'>jicd' .

.

1.9
2.2
2:9
10 ..'

.'

.~u..~

.Max •.• ..

;',.118";.'

fJlvrC
.oCIW/
> .
.Seg
.
NOTES: 5. The digits are categorized lor luminous intensity with the intenSity category deSignated by a letter located on the right hand side of the package.
6. The dominant wavelength. Ad. is derived from the C.I.E. Chromaticity Diagram and is that single wavelength which defines the color of !he device.
7. The 5082-7620/-7630 series yellow/green displays are categorized as to dominant wavelength with the category designated by a number
ROJ-PIN

282

'

adjacent to the intensity category letter.

8. Time for a 10% - 90% change of light intenSity for step change in current.

182

'

";:';

,,:

"

"".

20

,,0
",'"

~:
<:> ...

:,,,

~O
......
"''''
"'''

' i
1

---~

10
9

~~!Z
:;ww

r

j

15

8
7

OPERATION IN
THIS REGION

,,0.'"

REQUIRES

!~a
......
:;
02"

l

1\

"'0"
:; ... 0

Ow:;

j:~~

~i3:!:
I

,',

~I «2
~

,

~
1,5

1\

~'
'\

'\l' 'K

'\

X

"

:I .P"

1

_0.

10

1

100
tp -

"\

\

TEMPERATURE
DERATING OF
IocMAx

,

li ~~~
,t\f
R
\\
It
l

'"

1000

_

DC OPERATION

10000

PULSE DURATION - IJ.SEC

Figure 1. Maximum Tolerable Peak Current vs. Pulse Duration

~

22

1.•

I

20

1.8

~
a:
!5

,

16

'RaJA

:;:

14

~

12

~

10

~

8

.
:IE 7.5

~
1

i

~ ~~'

..

18

'.

~; 37O'~JWIS£GM;

~

'1Ie.iA • !I,rCiwiSEa-1Wi

'.

>

"iiiij

.

r-- \ ,
\N

.,

10

20

40

30

50

60

70

80

80
50

40

a:
a:

...0I

ii!

20

.!!-

.0

1.0

..

r

I I.'
'5082 -' 7630
-SI Rles ' .

II.

-I

'm
.

II

--

I II
I I I',

5 10 15 20 25 30 35 40 45 50 55 60 65

Figure 3. Relative Luminous Efficiency (Luminous
Intensity per Unit Current! vs. Peak Segment Current.

1.0

I 'I

r- '(.f

I III

iii. !(.... r[I

«

o

./

,-I

II fl

::>

"ca:

1.1

w

1.2

'"

~

I-:' ~~LJ10 rH ',"
seRIES,
..

I

30

~
..J

~

..-: ~ , . ~.76.;s..RIES

IpEAK - PEAK SEGMENT CURRENT - mA

Figure 2. Maximum Allowable DC Current and DC
Power DIssipation per Segment as a Function of Ambient Temperatura.

w

>

=.

00

90 100

TA - AMBieNT TEMPERATURE -'C

E

~w

.8

o

'"

1.4

.7

o

IZ

.... ~rl

1.5

1.3

'"

6
4
2

{

. 5062-7830 si,ueii

1.6

...1.\

"6.u>. • 484"(:JWISEGMM

50.2>-7620se~ ",,'--

'I 1

1.7

to82·7610

SERIES

II,
J,

rl

'fl.:

:,10 '

2.0

3.0

4.0

VF - FORWARD VOLTAGE-V

Figure 4. For_rd Current

VI.

IF - SEGMENT DC CURRENT - mA

For_rd Vo Itaga Characteristic.

Figure 5_ Relative Luminous Intensity vs. DC Forward Current.

For a Detailed Explanation on the Use of Data Sheet Information and Recommended
Soldering Procedures, See Application Note 1005, Page 464.

183

maximum power dissipation may be calculated using the
following VF models.

ELECTRICAL
The 5082-7600 series of display products are arrays of
eight light emitting diodes which are optically magnified
to form seven individual segments plus a decimal point.

VF = 1.75V + IPEAK (380)
For IPEAK 2: 20mA
VF = 1.60V + IDe (450)
For 5mA ::; IDe::; 20mA
All of the colored display products should be used in
conjunction with contrast enhancing filters. Some
suggested contrast filters: for red displays, Panelgraphic
Scarlet Red 65 or Homalite 1670; for yellow displays,
Panelgraphic Yellow 27 or Homalite (100-1720, 100-1726);
for green, Panelgraphic Green 48 or Homalite (100-1440,
100-1425). Another excellent contrast enhancement
material for all colors is the 3M light control film.

The diodes in these displays utilize a Gallium Arsenide
Phosphide junction on a Gallium Phosphide substrate to
produce high efficiency red and yellow emission spectra
and a Gallium Phosphide junction for the green.
These display devices are designed for strobed operation.
The typical forward voltage values, scaled from Figure 4,
should be used for calculating the current limiting resistor
values and typical power diSSipation. Expected maximum
VF values for the purpose of driver circuit design and

184

[

'".

,-

Features
• LARGE DIGIT
Viewing up to 6 meters (19.7 feet)
• CHOICE OF 3 BRIGHT COLORS
High Efficiency Red
Yellow
Green
• LOW CURRENT OPERATION
As Low as 3mA per Segment
Designed for Multiplex Operation
• EXCELLENT CHARACTER APPEARANCE
Evenly Lighted Segments
Wide Viewing Angle
Body Color Improves "Off" Segment
Contrast
• EASY MOUNTING ON PC BOARD OR
SOCKETS
Industry Standard 7.62mm (.3") DIP
Leads on 2.S4mm (.1") Centers
• CATEGORIZED FOR LUMINOUS
INTENSITY; YELLOW AND GREEN
CATEGORIZED FOR COLOR
Use of Like Categories Yields a
Uniform Display
• IC COMPATIBLE

{

Description
The 508:2-7650, -7660, and -7670 series are large 10.92mm (.43
in,) Red, Yellow, and Green seven segment displays. These
displays are designed for use in instruments, pOint of sale
terminals, clocks, and appliances.
The -7650 and -7660 series devices utilize high efficiency LED
chips which are made from GaAsP on a transparent GaP
substrate.
The -7670 series devices utilize chips made from. GaP on a
transparent GaP substrate.

• MECHANICALLY RUGGED

Devices
Part No. SOQ-

Color

~7650

-7651 '

-7653

,High Efficiency Red

-7656

High Efficiency Red

-7660

Yellow

,-7661

Yellow,

~7663

Yellow

,..7666

Yellow

, -7676

Green

Note: Universal pinout brings the anode and cathode of each segment's LED out to separate pins, see Internal'diagram D.

185

Package Dimensions
'0"

"""_-1_,-+... 8

'0"

...._ _~_+.. 8

3.'8 (.'25)

It
R.H.D.P.

I-~"""~+

A

•. H.D.P.

NOTE 141

•.21 (.206)

D

B,C
FRONT VIEW

1-,2.7.
I

~..1
"

.L.
4.118 (.'80)
MIN.

I
t6.36

','

r

(.2&0)

'6.24

1

-78711 '
CATNOIle..

2

CA_of

3
4

ANODEI3I
fliPPIN

I

:~ .'•
1

,-- I

-111- D.26 (.0'0)

7.82 (.3OD)-j---J

8

2."(.'00)

DATACOOE

10

11
END VIEW

-'_1fIIOI
A

PI"

(.5OD)-I

MAX.

.-

FUNCTION

LUMINOUS
INTENSITY
CATEGORY

'2

SIDE VIEW

13
14

NOTES:

C

B

-1151/·11511 ,-1B63I-1B63I
, -7871'

'

,CA_·.

ANODE..
. CATHOPe-r ' ANODE-I
ANODEIli
CATHODEIfl

NO PI"
NO PIN,
'NO PIN
'CATIfDD£.dp NO CON.... (&!
CATNOIlE-o
CATHODk
,CATHOOBod CATHOOe CA_'"

AN_Ill

ANODIIli

I>
·78fIlIW'.'

CAi~
ANODE'"

NOPfN
CATHODk
,NO PI"
NO,PIN • ,CATHODE..
NOODI'lI'l.(&!' ANODE .. '

ANOoe.. '
ANOOBod
IINoDE.....

ANODE..
ANOOE..
NO PIN
ANOOI!ob
CATHODE(&!

ANODe...
ANODE.....
'i:ATNOIlI.....
'eATHOOE-I>

CATHQ!.lI..
NO PIN

ANOOk
ANOOE-I>

1. Dimensions in millimeters and (inches).
2. All untoleranc:a:l dimensions are for

reference only.
3. Redundant anodes.
4. Unused dp position.

6. See Internal Circuit Diagram.
6. Redundant cathode.

Internal Circuit Diagram

A

B

C

Absolute Maximum Ratings
Average Power Dissipation Per Segment or D.p.I'] (TA)=50°C)
81mW
Operating Temperature Range ........ ,............... .......... -4OOC to +85°C
Storage Temperature Range ................................... -400 C to +850 C
Peak Forward Current Per Segment or D.P(3) (TA=50°C) .................... 60mA
DC Forward CurrentPerSegmentorD.p.(',2) (TA=50°C) ...................... 20mA
Reverse Voltage Per Segment or D.P. . ...................................... 6.0V
Lead Soldering Temperature ................................... 2600 C for 3 Sec
[1.59mm (1/16 inch) below seating plane(4)]

186

D

Notes: 1. See power derating
curve (Fig.2). 2. Derate average
current from 50" C at D.4mAI" C per
segment. 3. See MaxImum Tolerable Segment Peak Current vs.
Pulse Duration curve, (Fig. 1). 4.
Clean only in water, isopropanol,
ethanol, Freon TF or TE; (or
equivalent) and Genesolv 01-15 or
OE-15 (or equivalent).

Electrical/Optical Characteristics at TA =25°C
HIGH EFFICIENCY RED 5082-7650/-7651/-7653/-7656
:~~:

YELLOW 5082-7660/-7661/-7663/-7666

GREEN 5082-7670/-7671/-7673/-7676

·565

.:..nm·

572.

,

2.2 '2.5 .'
. 2.9'

'. . 10·
':,'
",

..

~

:

,"

','.- .: ~

:'

NOTES:
5. Ttle digits are categorized for luminous Intensity with the Intensity category designated by B letter located on the right hand side 01 the-package.
6. The dominant wavelength, Ad. is derived from the CJ.E. Chromaticity Diagram and is the single wavelength which defines the color of the device.
1. The 5082-7680/-7870 series yellow/green displays are categoriZed as to dominant wavelength with the category designated by a number adjaeent to Ihe intensity category letter.
8. Time for a 10..-90% change of light intensity for step change In current.

187

~~~~If~~~~~~~~~~~~!!~~~~~lll~oNIN
~

THIS REGION
REQUIRES
TEMPERATURE
DERATING OF
Ioc MAX

""""!::-.....................~~c'"-"-"............ul~OOOO:'!- DC OPERATION
tp - PULSE OURATION - J.(SEC

Figure 1. Maximum Tolerable Peak Current vs. Pulse Duration.

1.9
1.8
1.7
1.6 .

.
.~
z~

>
>=

~0:

1.5
1.'
1.3
1.2
1.1
1.0
.9
.8
.7
00

TA - AMBIENT TEMPERATURE -'C

IPeAK - PEAK SEGMENT CURRENT - mA

Figure 2. Maximum Allowable DC Current per
Segment vs. Ambient Temperature.
Deratlngs Based on Maximum Allowed
Thermal Resistance Values, LED
Junctlon-to-Ambient on a per Segment
Basis. TiMAX=100·C

Figure 3. Relative Luminous Efficiency (Luminous
Intensity per Unit Currentl vs. Peak Segment
Current.

~
I

I-

nia::
a::

B

I
I

.!!-

VF • FORWARD VOLTAGE - V

IF - SEGMENT OC CURRENT - mA

Figure 5. Relative Luminous Intanslty
DC Forward Current

Figure 4. Forward Current vs. Forward Voltage
Characteristic.

VS.

For a Detailed Explanation on the Use of Data Sheet Information and Recommended
Soldering Procedures. See Application Note 1005. Page 464.

188

ELECTRICAL

following VF models:
VF = 1.75V + IPEAK (380)
For IPEAK ~ 20mA

The 5082-7600 series of display products are arrays of
eight light emitting diodes which are optically magnified
to form seven individual segments plus a decimal point.

r""",

. jl
...

VF = 1.60V + loc (450)
For 5mA Sioc S 20mA

The diodes in these displays utilize a Gallium Arsenide
Phosphide junction on a Gallium Phosphide substrate to
produce high efficiency red and yellow emission spectra
and a Gallium Phosphide junction for the green.

All of the colored display products should be used in
conjunction with contrast enhancing filters. Some
suggested contrast filters: for red displays, Panelgraphic
Scarlet Red 65 or Homalite 1670; for yellow displays,
Panelgraphic Amber 23 or Homalite (100-1720, 100-1726);
for green, Panelgraphic Green 46 or Homalite (100-1440,
100-1425). Another excellent contrast enhancement
material for all colors is the 3M light control film.

These display devices lire designed for strobed operation.
The typical forward voltage values, scaled from Figure 4,
should be used for calculating the current limiting resistor
values and typical power dissipation. Expected maximum
VF values for the purpose of driver circuit design and
maximum power dissipation may be calculated using the

(

189

7.6 /10.9 mm (0.3/0.43 INCH)
SEVEN SEGMENT DISPLAYS· FOR
HIGH LIGHT AMBIENT CONDITIONS
HIGH EFFICIENCY RED· HDSP-3530/3130SERIES
YEllOW·HDSP-4030/4130 SERIES

F/in-

HEWLETT
~e... PACKARD

TECHNICAL DATA MARCH 1980

Features
• HIGH LIGHT OUTPUT
Typically 2300 /-tcd/Segment at 100mA Peak,
20mA Average
Designed for Multiplex Operation
• CHOICE .OF TWO COLORS
High Efficiency Red
Yellow
• EXCELLENT CHARACTER APPEARANCE
Evenly Lighted Segments
Wide Viewing Angle
Gray Body Color for Optimum Contrast
• EASY MOUNTING ON PC BOARD OR SOCKETS
Industry Standard 7.62mm (0.3 in.) DIP Leads
on 2.S4mm (0.1 in.) Centers

Description
The HDSP-3530/4030 and -3730/4130 series are 7.621
10.92mm (0.3/0.43 in.> high efficiency red and yellow
displays designed for use in high light ambient conditions.
These displays are designed for use in instruments,
airplane cockpits, weighing scales, and point of sale
terminals.

• CATEGORIZED FOR LUMINOUS INTENSITY;
YELLOW CATEGORIZED FOR COLOR
Use of Like Categories Yields a Uniform Display
• IC COMPATIBLE

The HDSP-3530/4030 and -3730/4130 series devices
utilize high efficiency LED chips, which are made from
GaAsP on a transparent GaP substrate. The active
junction area is larger than that used in the 50827610176201765017660 series to permit higher peak
currents.

• MECHANICALLY RUGGED

Devices
Part No. HDSP.

Color

3530
3531
3533
3536

High
High
High
High

4030
4031
4033
4036

Efficiency
Efficiency
Efficiency
Efficiency

Description

Red
Red
Red
Red

Package
Drawing

7.6mm
7.6mm
7.6mm
7.6mm

Common Anode Left Hand Decimal
Common Anode Right Hand Decima.
Common Cathode Right Hand Decimal
Universal Overflow ±1 Right Hand Decimal

A
B
C
D

Yellow
Yellow
Yellow
YellOW

7.6mm
7.6mm
7.6mm
7.6mm

Common
Common
Common
Universal

A
B
C
D

3730
3731
3733
3736

High
High
High
High

10.9mmCommon Anode Left Hand Decimal
10.9mmCommonAnodeRight Hand Decimal
10.9mm Common Cathode Right Hand Decimal
10.9mm Universal Overflow ±1 Right Hand Decimal

4130
4131
4133
4136

Yellow
Yellow
Yellow
Yellow

Efficiency Red
Efficiency Red
Efficiency Red
Efficiency ,Red

10.9mm
1O.9mm
10.9mm
10.9mm

Anode Left Hand Decimal
Anode Right Hand Decimal
Cathode Right Hand Decimal
Overflow ±1 Right Hand Decimal

Common
Common
Common
Universal

Anode Left Hand Decimal
Anode Right Hand Decimal
Cathode Right Hand Decimal
Overflow ±1 Right Hand Decimal

E

F
G
H
E

F
G
H

Note: Universal pinout brings the anode and cathode of each segment's LED out to separate pins. See internal diagrams D and H.

190

Absolute Maximum Ratings (All Products)
Average Power Dissipation Per Segment or DP (TA=50° C) . . . . . . . . . . . . . . . . .. 85mW
Operating Temperature Range ...•...........•..•................ _40° C to +85° C
Storage Tem peratu re Range ........•.••.•....................... _40° C to +85° C
Peak Forward Current Per Segment or DP(TA = 50°C)12) ..................... 120mA
(Pulse Width = 1.25ms)
DC Forward Current Per Segment or DP (TA=500 C)11) .....•.•................ 30mA
Reverse Voltage Per Segment or DP ... . . • . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6.0V
Lead Soldering Temperature (1.6mm [1/16 inch]
below seating plane) ........•.........•..........•••..•... 260°Cfor3 Seconds

'"

Notes: 1. Derate maximum DC
current above TA=50o C at 0.51
mAIo C per segment, see Figure 2.
2. See Figure 1 to establish pulsed
operating conditions.

Package Dimensions (HDSP-3530/4030 Series)

T---'
i

7.62

1.300)

~~-,
Note 7

'1~2

r-:

li~

Note4

_ _ 0.25

COlO}

I

7

CATHODE·,
CATHODE-d
NO CONN.l51
CATHOOE.c :

10

11

[ 12

13

o

A,B,C

LUMINOUS
INTENSITY

!

14
-

1
i

CATHODE..
NO PIN

CATHODE·b
.ANOOEI'I

I

D
·3536/-4036

CATHOOEIS)
ANOD€·!
ANODE"
ANODE·.
ANODE-d
CATHOOEI']
ANODE-dp
ANODE ••
ANOOE-b
ANOOE·.

I

8
9

I
i

c

·35331·4033

CATHODE",
CATHODE..
CATHODE·j
CATHODE·!
ANOOEI31
ANODEI']
NO PIN
, NOPIN
NO PIN
! NOP'N
CATHOOE-dp I NO CONN.l51

6

I

+

~.,-_7 ....-+1--'~
5.72
1.225)

Ir~ II~,~~"

3
4
5

19.05 t 0.25
1.750 •. 010)

I

FUNCTlON

CATHODE·.
CATMOOE-d
CATHODE-dp
CATHODE.c

CATHODE"
NO PIN

ANODE-d
"laPIN
CATHODE-d
CATHODE·.
CATHODE .•
ANOOE-e
ANODE·.

I
I ~:~:-dP II
I
I ~CATHODE~
CA THu"~-dp

I

CATHODE·b
: ANODEi'1

CATHODE·a

ANOOE·•.
ANOOE-b

;1'

_~ _ _ _ ~~_~_

0--0

LUMINOUS
INTENSITY
CATEGORY

CATEGORY

~10.16 MAX.I--

R
,(,400)

I~

I

L

4.06(.1601
MIN.

-r-'

DATE CODE

l

I

A,B,O

A,B,C,O
END

C
SIDE

SIDE
NOTES,
1. Dimensions in millimeters and (inches).
2. All untoleranced dimensions are
for reference only.
3. Redundant anodes.
4. Unused dp position.

5. See Internal Circuit Diagram.
6. Redundant cathode.
7. See part number table for L.H.D.P.
and R.H.D.P. designation.
8. For HDSp·403D series product only.

Internal Circuit Diagram (HDSP-3530/4030 Series)

A

C

B

191

(.180)

-1-

~I'I-- 0.25 (,010)

7.621.300)~

6.10
~ (,240)

!-~

o

package Dimensions (HDSP-3730/4130 Series)
7.01 (.276)

-_11--,0·
+

1

14
13

12

t
I

11 10.92 (.430)

~~1

LH.D.P.

l_6
3.18(.125)

-r--I

I

6.35 (.250)

9_~

7.4-_......_ _.J8 Note4

;L._.:..:..o""""=+l,8

,

~

3.18 (.1251

~

5.08 (.200)

R.H.D.P.

-1----1

Note 4

5.21 (.205)

E

H

F,G
FRONT VIEW

_12.70 (.500)
MAX.

FUNCTION·

C~h~R Note 7

LUMINOUS
INTENSITY
CATEGORY

I

~

---..1

PIN

1.02

I

IjOI

1

1

I
0.51

I

_1_s=i6.3{1.2501
4.06 (.160)
MIN.

~I
7.62 (.300)

-111_0.251.°'01

i--

E,F,G,H
END VIEW

19.05

(.750

r

i.0201

± 0.25
± .010)

1

(.600)

DATE CODE

t
2.54 (.100)

1

E,F,G,H
SIDE VIEW

.3730/.4136

·373"·4131

to
11

CATHODE..,

CATHODE'l1

12

NO"f'"
CATHODE·.
ANODE(31

NOPIN
CATHODE.b
ANODel31

3
4

5
6

L

_l

F

CATHOOE~a
CATHODJ;·,
CATHODe-!
CATIIODE·!
ANODel>1
ANODEt31
NO PIN
NO PIN
NOPtN
NO PIN
CATHODE·dO NO CONN."!
.CATIIODE,.
CATHOOE..
CATHODE·d
.CATHODE-d
NOCONN.l5! CATHODe-dp
CA.THODE-t;.
CATHODE.

~

15.24

£

7

a
~

~l
.14

G
·3733/-4133
ANODh
ANODE·f·
CATIiOOef')
N091N
NO PIN
NOCONN."I
ANQOE-e
ANOOE-d
ANODE-dp
ANODe·.
ANODE·g
NO PIN
ANODE-b
CATIiOOEI6,

..

H

<37301-4130
CATHODE·d
ANDDe-d
NOPfN
CATHODE·.
CATHODE..
ANODE·,
ANODE·.
ANODE·tlp
CATHODE-dp
CATHODE.b
CATHODE-a

NDPIN
ANODE·a
ANODE-•

NOTES:

1. Dimensions in millimeters and (inches).
2, All untoleranced dimensions are for
reference only_

3.
4.
5.
6.
7.

Redundant anodes.
Unused dp position.
See Internal Circuit Diagram

Redundant cathode.
For HDSP-4130 series product only.

Internal Circuit Diagram (HDSP-3730/4130 Series)

10

E

G

F

192

H

Electrical/Optical Characteristics at TA=25°C
HI G H EFFI C I ENCY RED H DS P-3530/-3531/ -3533/ -3536/ -3730/ -3731/ -3733/ -3736
Parameter
Luminous Intensity/Segment (3) •....
(Digit Average)
Peak Wavelength
Dominant Wavelength(4)

Reverse Current/Seglllentor D,P,
Response Time, Rise and Fall(SI
Temperature Coefficient ofVF1Segment or D.P.
Thermal Resis'tance LED Junction~to-Pin

P8J-PIN"

YELLOW HDSP-4030/-4031/-4033/-4036/-4130/-4131/-4133/-4136
Parameter
.

. 100mA Pk: 1 015
Duty Factor

tv

Y.

(Digit Averagel
Peak Wavelength

TyP··

Max.

Urnts

1000

2700,

.

. /tCd

.'

20m A DC

"f'tAK

•

Dominant Wavelength I4,$)

Ad

• "..... >."

. Forward Voltage/Segment or D.P.

VF

Reverse Currel)ltSegmento(D.P.

If!

Response Time. Rise and. FaW6)

MIn,..

. Test Condition

Symbol
'.'

Luminous lntensity/Segment(S)

.

'.'

."

2100

.'

585

.

IF = 1.00mA
'.

~(;tt

.lVF/oC

Thermal Resistance LED Junction-to-Pin

R9j":'PIN

'.'

......

nm
..

3.3

V

.

ns... '

-1.1

mV/oC

282

·CfW/
Seg

"

.'

"

nm ..

j.t.A

10
200.

.' 1,,= 100mA
".

583

2.6

.

,

Temperature Cootficientof VF/Segment or D.P.

VR:' 6V

/tcd

NOTES:
3. The digits are categorized for luminous intensity with the intensity category deSignated by a letter located on the right hand side of the
package.
4. The dominant wavelength, Ad, is derived from the CIE chromaticity diagram and is that single wavelength which defines the color of the
device.
5. The HDSP-4030/-4130 series yellow displays are categorized as to dominant wavelength with the category designated by a number adjacent
to the intensity category letter,
6. The rise and fall times are for a 10%-90% change of light intensity to a step change in current.

ELECTRICAL

current limiting resistor values and typical power
dissipation. Expected maximum VF values forthe purpose
of driver circuit design and maximum power dissipation
may be calculated using the following VF models:

The HOSP-3530/3730/4030/4130 series 01 display devices
are composed of eight light emitting diodes, with the light
from each LED optically stretched to form individual
segments and a decimal pOint. The LEOs have a large area
P-N junction diffused into a GaAsP epitaxial layer on a
GaP transparent substrate,

VF = 2.15V
For IPEAK
VF = 1.9V

These display devices are designed for strobed operation
at high peak currents. The typical forward voltage values.
scaled from Figure 4. should be used for calculating the

+ IPEAK (11.501
~

30mA

+ IDe 119.80)

For 10mA:oS IDe:oS 30mA

193

Temperature derated strobed operating conditions are
obtained from Figures 1 and 2. Figure 1 relates pulse
duration (tp), refresh rate (f), and the ratio of maximum
peak current to maximum dc current (lPEAK MAX/IDe
MAX). Figure 2 presents the maximum allowed dc current
vs. ambient temperature. To most effectively use Figures 1
and 2, perform the following steps:
1. Determine desired duty factor, DF.
Example: Five digits, DF = 1/5
2. Determine desired refresh rate, f. Use duty factor to
calculate pulse duration, tp. Note: DF =f-tp.
Example: f = 1 kHz, tp = 200 p'S
3. Enter Figure 1 at the calculated tp. Move vertically to the
refresh rate line and record the corresponding value of
IPEAK MAX/IDe MAX.
Example: Attp = 200ILs and f = 1 kHz, IPEAK MAX/IDe
MAX =4.0
4. From Figure 2, determine IDe MAX. Note: loc MAX is
derated above TA = 50· C.
Example: At TA = 60· C, loc MAX = 25mA
5. Calculate IPEAK MAX from IPEAK MAX/I DC MAX ratio
and calculate IAVG from IPEAK MAX and DF.
Example: IPEAK MAX = (4.0) (25mA) = 100mA peak.IAVG
= (1/5) (100mA) = 20m A average.

MECHANICAL
These devices are constructed utilizing a lead frame in a
standard DIP package. The LED dice are attached directly
to the lead frame. Therefore, the cathode leads are the
direct thermal and mechanical stress paths to the LED
dice. The absolute maximum allowed junction temperature, TJ MAX, is 100·C. The maximum power ratings have
been established so that the worst case VF device does not
exceed this limit. For most reliable operation, it is
recommended that the device pin-to-ambient thermal
resistance through the PC board be less than 320· C/W per
segment. This will then establish a maximum thermal
resistance LED junction-to-ambient of 602·C/W per
segment.

The above calculations determine the maximum allowed
strobing conditions. Operation at a reduced peak current
and/or pulse width maybe desirable to adjust display light
output to match ambient light level or to reduce power
dissipation to insure even more reliable operation.
Refresh rates of 1 kHz or faster provide the most efficient
operation resulting in the maximum possible time average
luminous intensity.

These display devices may be operated in ambient
temperatures above +50· C without derating when
installed in a PC board configuration that provides a
thermal resistance to ambient value less than 602·C/W/
Segment. See Figure6 to determine the maximum allowed
thermal resistance for the PC board, ROpe_A' which will
permit nonderated operation in a given ambient
temperature.

The time average luminous intensity may be calculated
using the relative efficiency characteristic of Figure 3,
17IPEAK' and adjusted for operating ambient temperature.
The time average luminous intensity at TA=25·C is
calculated as follows:

Iv TIME AVG

To optimize device optical performance, specially.
developed plastiCS are used which restrict the solvents
that may be used for cleaning. It is recommended that only
mixtures of Freon (F113) and alcohol be used for vapor
cleaning processes, with an immersion time in the vapors
of less than two (2) minutes maximum. Some suggested
vapor cleaning solvents are Freon TE, Genesolv 01-15 or
DE-15, Arklone A or K. A 60·C (140·F) water cleaning
process may also be used, which includes a neutralizer
rinse (3% ammonia solution or equivalent), a surfactant
rinse (1% detergent solution or equivalent), a hot water
rinse and a thorough air dry. Room temperature cleaning
may be accomplished with Freon T-E35 or T -P35, Ethanol,
Isopropanol or water with a mild detergent.

= ['AVG ] [.17 IPEAK] [IV DATA SHEET]
20mA

Example: For HDSP-4030 series
17IPEAK

= 1.00 at IPEAK = 100mA

- [~J

Iv TIME AVG -

20m A

[1.00] [ 2.7mcd ]

= 2.7mcd/
segmeht

The time average luminous intensity may be adjusted for
operating ambient temperature by the following eXpOn6:1tial equation:
Iv (TA) = Iv (25· C) eD< ITA - 2S'C~
Device

K

-3530/3730 Series
-4030/4130 Series

-0.0131/·C
-0.0112I"C

Example: Iv (70·C)

= (2.7mcd) e[-O.0112 170-2Si] = 1.63mcd/
segment

194

CONTRAST ENHANCEMENT

f"

these display devices are assembled with a gray package
and untinted encapsulating epoxy in the segments.

The objective of contrast enhancement is to provide good
display readability in the end use ambient light. The
concept is to employ chrominance contrast techniques to
enhance readability by having the OFF-segments blend
into the display background and have the ON-segments
stand out vividly against this same background. Therefore,

Contrast enhancement in bright ambients may be
achieved by using a neutral density gray filter such as
Panelgraphic Chromafilter Gray 10. Additional contrast
enhancement may be achieved by using the neutral
density 3M Light Control Film lIouvered filter!.

l.

40

20

15

I

I

II

I

I'

1

10

~

'\

'\

I\~

\~

I

I

~.. ,

~

I

,

1.5
1

" .,.

10

~

'~~~
"\

is

25

~

"X"
«

1

~

I
X

«

A

111

30

"u

~

" Ixil
1000

100

35

~

~

OPERATION I
THIS REGION
REQUIRES
TEMPERATUA
DERATING OF
loc MAX

8

>-

20
15
12
10

.g
0

-OCDPERA TION
10.000

0

tp - PULSE DURATION - jJS

TA - AMBIENT TEMPERATURE _ °C

Figure 1. Maximum Allowable Peak Current vs. Pulse Duration.

--

1. 1

120

~

HOSP-3630/3730 SERIES
1.0

~

.9
.8
.7

.6
.5

/'

V
1/

i

I

80

100

0

~

40

•

20

I

I
60

0-

~

-~

!
40

100

1 I I

120

IpEAK - PEAK SEGMENT CURRENT - rnA

Figure 3. Relative Efficiency (Luminous
Intensity per Unit Currentl vs.
Peak Segment Current.

1.8

I

1.6

HOSP.$30I3130 ~ ~iI'LS

o

I
I

.2
1

ia

f-lOSP40-30/4130 se~n!s

.4

·20

I

'/
~
/ '\

.3

~

Figure 2. Maximum Allowable DC Current per
Segment VB. Ambient Temperature.
Deratlngs Based on Maximum
Allowable Thermal Resistance Values,
LED Junction-to-Ambient on a par
Segment Basis. TJMAX-100·C.

H-i;

IJ

1.4

~ ~

1.2

:t

"z :;:

1.0

::;

.8

> 0~

.6

;;

N

3«

w
I

IU

Iii

~

I~

I
HoSPooI03OII,30 SERIES

II I
2.0

2.5

3.0

3.4

VF - PEAK FORWARD VOLTAGE - V

Figure 4. Peak Forward Segment Current
vs. Peak Forward Voltage.

~
~

/

E

0

n

I

15

~

;;

~

r I
I II
: I
I

0
10

~

\ J
III

I .1

~

/

'.

.4
.2
00

1./

./'1

1< ,: :

'/

10

15

20

25

30

IF - SEGMENT DC CURRENT - rnA

Figure 5. Relative Luminous Intensity vs.
DC Forward Current.

For a Detailed Explanation on the Use 01 Data Sheet Information and Recommended
Soldering Procedures, See Application Note 1005, Page 464.

195

L

/

···HEW~Eff~:C
PACKARD
MARCH 1980

Features
• 5082-7730
Common Anode
Left Hand D.P.
• 5082-7731
Common Anode
Right Hand D.P.
• 5082-7736
Polarity and Overflow Indicator
Universal Pinout
Right Hand D.P.
• 5082-7740
Common Cathode
Right Hand D.P.
• EXCELLENT CHARACTER APPEARANCE
Continuous Uniform Segments
Wide Viewing Angle
High Contrast
• IC COMPATIBLE
1.6V de per Segment
• STANDARD 0.3" DIP LEAD CONFIGURATION
PC Board or Standard Socket Mountable
• CATEGORIZED FOR LUMINOUS INTENSITY
Assures Uniformity of Light Output from
Unit to Unit within a Single Category

Description
The HP 5082-773017740 series devices are common anode
LED displays. The series includes a left hand and a right
hand decimal pOint numeric display as well as a polarity
and overflow indicator. The large 7.62 mm (0.3 in.) high
character size generates a bright, continuously uniform
seven segment display. Designed for viewing distances of
up to 3 meters (9.9 feet), these single digit displays provide
a high contrast ratio and a wide viewing angle.
The 5082-7730 series devices utilize a standard 7.62 mm
(0.3 in.) dual-in-line package configuration that permits
mounting on PC boards or in standard IC sockets.
Requiring a low forward voltage, these displays are
inherently IC compatible, allowing for easy integration
into electronic instrumentation, pOint of sale terminals,
TVs, radios, and digital clocks.

Devices

1731
1736
1740
Note: Universal pinout brings the anode and cathode of each segment's LED out to separate pins. See internal diagram C.

196

package Dimensions

A,B,O

C

LUMINOUS
INTENSITY
CATEGORY

I. '. ~
R
t

1

10. 16 MAX
1.400)
.

L

(.180)

4.061.160)
MIN.

~

i

-+IiI-- 0.25 (.010)

7.621.300)-r----1

A,B,C,O
A,s,C

o

SIDE

SIDE

END

NOTES:

1. Dimensions in millimeters and linches).
2. All untoleranced dimensions are

for reference only
3. Redundant anodes.

4. Unused dp position.
5. See Internal Circuit Diagram.
6. Redundant cathode.
7. See part number table for l.H.D.P. and A.H.D.P. designation.

Internal Circuit Diagram

(

A

C

B

o

Absolute Maximum Ratings
Average Power Dissipation Per Segment or D.p.ll) (TA=50'C) ............. 65mW
Operating Temperature Range ................................. -400 C to +85' C
Storage Temperature Range ................................... -400 C to +85' C
Peak Forward Current Per Segment or D.P.13) (TA=50·C) ................... 150mA
Average Forward Current Per Segment or D.P. 11,2) (TA=50·C) ............... 25mA
Reverse Voltage Per Segment or D.P.. ...................................... 6.0V
Lead Soldering Temperature ................................... 260'C for 3 Sec
[1.59mm (1/16 inch) below seating plane(4) 1

197

Notes: 1. See power derating curve
(Fig.2). 2. Derate DC current from
SO' C at O.43mA/' C per segment.
3. See Fig. 1 to establish pulsed
operating conditions. 4. Clean only in
water, isopropanol, ethanol, Freon
TF or TE (or equivalent) and Genesolv 01-15 or DE-IS (or equivalent).

Electrical/Optical Characteristics at TA =25°C
Min.

Description

Typ.

Luminous Intensity/Segment(2)

200

(Digit Average)
Peak Wavelength
Dominant WavEllerigth(2l
Forward Voltage, any Segment otD,P; .
10

Reverse Current, any Segment
Rise and Fall Time(»)

10
~2:.0

Thermal Resistance LEO Junctlon-Io-Pin

282.

·C/WI
Seg

Notes:
1. The digits are categorized for luminous intensity with the intensity category designated by a letter located on the right hand side of the package.
2. The dominant wavelength, Ad. is derived from the CIE Chromaticity Diagram and is that single wavelength which defines the color of the device.
3. Time for a 10%·90% change of light intensity for step change in current

ELECTRICAL

of driver circuit design may be calculated using the
following VF model:

The HDSP-7730/7740 series of display devices are
composed of eight light emitting diodes, with the light
from each LED optically stretched to form individual
segments and a decimal point. The LEOs have the P-N
junction diffused into a GaAsP epitaxial layer on a GaAs
substrate.

CONTRAST ENHANCEMENT

These display devices are designed for strobed operation
at high peak currents. The typical forward voltage values,
scaled from Figure 4, should be used for calculating the
current limiting resistor values and typical power
dissipation. Expected maximum VF values forthe purpose

The 5082-7730/7740 series display may be effectively
filtered using one ofthe following filter products: Homalite
H100-1605: H 100-1804 (purple); Panelgraphic Ruby Red
60: Dark Red 63: Purple 90; Plexiglas 2423; 3M Brand Light
Control Film for daylight viewing.

...... .

20

.;

VF = 1.55V + IPEAK (70)
For 5mA S IPEAK S 150mA

.....

l

15
10
9
8

OPERATIO NIN
THISREGI ON
REQUIRES
TEMPERA TURE
DERATINGOF

\

~
\

7

IocMAX.

,'\

-

~

11 l>. '

~.

I,.
...•.
1.5

10

C,JiI'

f

:

~

..

I.'
1

~ ~f ~i
1ti'
~~.
I····;·
\ ,I 1\
11\;·.· ':.
\'\i"

I·"'.' 1\

r: I~

I··•..
100

.1·... ·.••.
1000

....

"'

.....-DCQPERATION

10000

tp - PULse DURATION -,uSEC

Figure 1. Maximum Tolerable Peak Current vs. Pulse Duration.

198

C

E
I

r-~

l

!Zw
a:
0:

::>
u

g

14'

::>

12

:E12.5~

IE

~

:E
I

~

:E

j:!
0'
0

10

30

20

40

50

60

70

80

40

90 100

Figure 2. Maximum Allowable DC Current
Dissipation par Segment as a Function
of Ambient Temperature.

.
.ffi

160

."ffi

100

E

":::'"
~

"

""u0

."~

e
I

50

IpEAK - PEAK SEGMENT CURRENT - mA

TA - AMBIENT TEMPERATURE -"C

Figure 3. Relative Efficiency (Luminous Intensity per Unit
Current) versus Peak Current per Segment.

1.4

I

140

iI

120

WN
1-1-

1,2
1.0

/

i!!C
IIIC!
il~

.8

jiil
.... N

.6

Ze

80
60

v

:':~

~~

!CO:
.... 0

40

~~

20

j

~

0
0

,4

,8

1.2

U

2,0

2,'

28

o

3,2

VF - FORWARD VOLTAGE - V

5

10

15

20

25

IF - SEGMENT DC CURRENT - rnA

Figure 4. Forward Current vs. Forward Voltage.

Figure 5. Relative Luminous Intensity vs. DC
Forward Currant

For a Detailed Explanation on the Use of Data Sheet Information and Recommended
Soldering Procedures, See Application Note 1005, Page 464.

199

.. ";';!~~:('

"

\

Features

,

'.

• 5082-7750
Common Anode
Left Hand D.P.
• 5082-7751
Common Anode
Right Hand D.P.
• 5082-7756
Polarity and Overflow Indicator
Universal Pinout
Right Hand D.P.

'--..

• 5082-7760
Common Cathode
Right Hand D.P.
• LARGE DIGIT
Viewing Up to 6 Meters (19.7 Feet)

Description

• EXCELLENT CHARACTER APPEARANCE
Continuous Uniform Segments
Wide Viewing Angle
High Contrast

The 5082-775017760 series are large 10.92mm (.43 in.)
GaAsP LED seven segment displays. Designed for
viewing distances up to 6 meters (19.7 feet), these single
digit displays provide a high contrast ratio and a wide
viewing angle.

• IC COMPATIBLE
• STANDARD 7.62mm (.3 in.) DIP
LEAD CONFIGURATION
PC Board or Standard Socket Mountable

These devices utilize a standard 7.62mm (.3 in.) dual-inline package configuration that permits mounting on PC
boards or in standard IC sockets. Requiring a low forward
voltage, these displays are inherently IC compatible,
allowing for easy integration into electronic instrumentation, point of sale terminals, TVs, radios, and digital
clocks.

• CATEGORIZED FOR LUMINOUS INTENSITY
Assures Uniformity of Light Output from
Unit to Unit within a Single Category

Devices
Part. No.

-7750

Pacbge brawlng

soa2~

C~mmol1 AnoQeL8ft Haod.Decimai

. -7751
-7756

A
B

Unive~&al Overflow ±1 Right Hand DeCimal .

c
o

"':7760
Nole: Universal plnoul brings Ihe anode and calhode of each segment's LED oullo separale pins, See inlernal diagram C.

200

package Dimensions
10'

[
Nolo

4~

6.35(.250)

R.H.D.P.
~......--

5.21 (,205)

c

B,D

A

FRONT VIEW
LUMINOUS

INTENSITY

l(.500)
I
I 12.70MAX.'"
-t

4.06~.'601
MIN.

CATEGORY

·7151

f-:ri"",,';;;"=;:--:'C-,t-.',C';;"A"ThH;;O""OfO

~
",_1

~

f

6.35 (.2501

I

TI
15.24

-111- 0.251.0101

7.621.3OOI-t---l

END VIEW

-t

NO?IN

6
1

cATHOOEd

I

NO PIN
CATHODE>c

~

I'

CATHOOE·e
ANODe...

CATHODE"
CATHODE·.
.NO PIN

ANOOE-dp

CATHODE-b

ANODEIlI

~___

1 CATHODf.b
. CATHOOe..
I NO PIN

I

ANODE·.

I

,7760

ANOOe:;--l.
ANODE.fCATHODE 16'
NO PIN

I

NO PtN
NO CONN. [51

'I ANODE-!;

'CATHODE-dp \ CATHOOE-dp

' CATHODE:.'
cATHODE..

L-~

NO PIN
NO CONN. [51
CATt!.ODE-e
CA'TI-tODE-d

No CoNN. 161

10

"13

SIDE VIEW

ANODe "'
NO PIN

No PIN

4.

I

.T156:
C

CATHOOE·1

5

$'

2.541.1001

DATA CODe:

CATHOOE·f
ANODEI3I

ANOb£-,
ANODE-d
ANODE·dp

I

ANODE·.
ANOOEl1
NO PIN
ANODE·b

ANODE·b
_ ____ I CATHOOE(61
____
~

~

NOTES:

1. Dimensions in millimeters and (inches).
2. All untoleranced dimensions are for
reference only.
3. Redundant anodes.
4. Unused dp position.
5. See Internal Circuit Diagram.
6. Redundant cathodes.

Internal Circuit Diagram

(

A

c

B

Absolute Maximum Ratings
Average Power Dissipation Per Segment or D.P.") (TA=50°C)
.......... 65mW
Operating Temperature Range ................................. -40°C to +85°C
Storage Temperature Range ................................... -40"C to +85°C
Peak Forward Current Per Segment or D.P{3) (TA=50°C) .................... 150mA
DC Forward Current PerSegmentorD.P.ll,2) (TA=50°C) ... , .................. 25mA
Reverse Voltage Per Segment or D.P ........................................ 6.0V
Lead Soldering Temperature ................................... 260°C for 3 Sec
[1.59mm (1/16 inch) below seating plane{4 1]

201

o

Notes: 1. See power derating curve
(Fig.2). 2. Derate average current
from 50° C at 0.43mA/o C per
segment. 3. See Maximum Tolerable Segment Peak Current vs.
Pulse Duration curve, (Fig. 1). 4.
Clean only in water, isopropanol,
ethanol, Freon TF or TE (or
equivalent) and Genesolv DI-15 or
DE-IS (or equivalent).

Electrical/Optical Characteristics at TA=25°C
Luminous Intensity/Segment

Typ.

IPEAK =100mA
12.5% Duty Cycle

Iv

(2)

Min.

Test Condition

Symbol

·oe.criPtiOn

(Digit Average)

350

. APEAK

Peak Wavelength
Dominant Wavelength

Ad

(2)

Units
ped

400

150

IF'" 20m A

Max.

655

nm

645

nm

Forward Voltage, any Segment or .D.P.

VF

IF= 20mA

1.6

Reverse Current. any Segment or D~P~

IR

VR= 6V

10

pA

Rise and Fall Time

tt, tf

10

ns

-2.0

mVrC

282

°C/WI

(3)

l::NrI"C

Temperature Coefficient of Forward Voltage
Thermal Resistance LEO Junction-to-Pin

R8J-PIN

2.0

V

Seg
Notes:
1.
2.
3.

The digits are categorized for luminous intensity with the intensfty category designated by a letter located on the right hand side of the package.
The dominant wavelength, Ad. is derived from the CIE Chromaticity Diagram and is that single wavelength which defines the color of the device.
Time for a 10% - 90% change of light intenSity for step change in current.

ELECTRICAL

of driver circuit design may be calculated using the
following VF model:

The HDSP-7750/-7760 series of display devices are
composed of eight light emitting diodes, with the light
from each LED optically stretched to form individual
segments and a decimal point. The LEOs have the P-N
junction diffused into a GaAsP epitaxial layer on a GaAs
substrate.

CONTRAST ENHANCEMENT

These display devices are designed for strobed operation
at high peak currents. The typical forward voltage values,
scaled from Figure 4, should be used for calculating the
current limiting resistor values and typical power
dissipation. Expected maximum VF values forthe purpose

The 5082-7750/7760 series display may be effectively
filtered using one of the following filter products: Homal'ite
H 100-1605 or H 100-1804 Purple; Panelgraphic Ruby Red
60, Dark Red 63 or Purple 90; Plexiglas 2423; 3M Brand
Light Control Film for daylight viewing.

VF = 1.55V + IPEAK (70)
For 5mA::; IPEAK::; 150mA

j

i

OPERATI ON IN

1\

\

THISREGI ON
REOUIRE S
TEMPERA TURE
DERATIN G OF

\

IocMAX.

\
\.

\
i

-&.
~

'"I

I~~

f\ .>~
-.
N'
,i~

,,- "

~

'I'-

,
\

1

10

1b'

I

s:~

_DeOPER ATJON
10000

tp - PULSE DURATION - pSEC

Figure 1. Maximum Tolerable Peak Current vs. Pulse Duration.

202

t

\
1000

100

~

~
I
....

zw

c::
c::

['-

::J

"15

~ 12.5

14~+-:-l":::""

12

::;

..
..

X

::;
I

X

::;

IpEAK - PEAK SEGMENT CURRENT - rnA

TA -AMBIENT TEMPERATURE _oC

Figure 2. Maximum Allowable DC Current per
Segment VS. Ambient Temperature.
Deratings Based on Maximum Allowed

Figure 3. Relative Efficiency (Luminous Intensity per Unit
Current) versus Peak Current per Segment.

Thermal Resistance ValuBs, LED

Junction-to-Ambient on a per Segment
Basis. T JMAX=100°C

'60

:,'

«

E

.:E
~

~

.~
~

I"'i..'·'·""

'20

:"

'00

i

80

. >.

a:

"
"a:«

,>

'40

,

,"

<.J

60

~

40

I

20

.-

~

:r

..)

.!"

o

o

.4

'.2

1.6

2.0

2.4

28

3.2

V F - FORWARD VOLTAGE - V

IF - SEGMENT DC CURRENT - rnA

Figure 4. Forward Current versus Forward
Voltage.

Figure 5. Relative Luminous Intensity
vs. D.C. Forward Current.

For a Detailed Explanation on the Use of Data Sheet Information and Recommended
Soldering Procedures, See Application Note 1005, Page 464.

203

Features
• 20mm (0.8") DIGIT HEIGHT
Viewing Up to 10 Metres (33 Feet)
• EXCELLENT CHARACTER APPEARANCE
Excellent Readability In Bright Ambients
Through Superior Contrast Enhancement
- Gray Body Color
- Untlnted Segments
Wide Viewing Angle
Evenly Lighted Segments
Mitered Corne,. on Segments
• LOW POWER REQUIREMENTS
Single GaAsP Chip per Segment
• EASY MOUNTING ON PC BOARD OR SOCKETS
Industry Standard 1S.24mm (0.6") DIP with
Lead Spacing on 2.S4mm (0.1") Cente,.
Industry Standard Package Dimensions
and Pinouts

Description

• CATEGORIZED FOR LUMINOUS INTENSITY
Assures Uniformity of Light Output from
Unit to Unit Within a Single Category

The HDSP-3400 Series are very large 20.32mm (0.8 inJ
GaAsP LED seven segment displays. Designed for
viewing distances up to 10 metres (33 feet>, these single
digit displays provide excellent readability in bright
ambients.

• IC COMPATIBLE
• MECHANICALLY RUGGED

These devices utilize a standard 15.24mm(0.6 inJdual in
line package configuration that permits mounting on PC
boards or in standard IC sockets. Requiring a low forward
voltage, these displays are inherently IC compatible,
allowing for easy integration into electronic instrumentation, point-of-sale terminals, TVs, weighing scales, and
digital clocks.

Devices

Note: Universal pinout brings the anode and cathode of each segment's LEO out to separate pins. See internal diagram E.

204

package Dimensions

'i
PACKAGE...!

r

FRONT VIEW A,D
19.98MAX·
(0.786 MAX.)

l

,',"" ' '.,' ." fO:::.
~

6~

' \,

FRONT VIEW B,C

FRONT VIEW E

LUMINOUS
INTENSITY
CATEGORY

" ":" ': ", ":', --;;:;10,25

(0.240 MIN,)

0,010)

(0.040)

r-!

_~ _

0,38 (0.015)

~.24'0.25

(0.600' 0.010)

DATE CODE

SIDE VIEW

END VIEW
NOTES:

1. Dimensions in millimetre. and (inches).
2.· All untoleranced dimensions are "for reference only.
3. Redundant anode •.

4. Unused dp position.
5. See Internal Circuit Diagram.
6. Redundant cathodes.

Internal Circuit Diagram
18

4

A

B

C

o

E

Absolute Maximum Ratings
Average Power Dissipation per Segment or DP (TA= 50· C)[11 ••...••.•.•••..••..••....•.•.....•....•.•...•• , 100mW
Operating Temperature Range •••.•••.••.•••••••.•••••.•.••..••••••••.•••..••...••...•...•••••. -20·C to +85· C
Storage Temperature Range ••••••.••.••...••••••••••••.•.••..••••.••••.••.••.••••••. ,......... -20·Cto+85·C
Peak Forward Current per Segment or DP (TA = 50·C, Pulse Width = 1.2ms)12) ..•••..••.•••...••.•••..••..••. 200mA
DCForwardCurrentperSegmentorDP(TA=50·C)[1!. ..................................................... SOmA
Reverse Voltage per Segment or DP •••.•.•••••••••••••.••••.••••..••..•••.••....••.•••.....•••..•..••••..•• 6.0V
Lead Soldering Temperature (1.6mm [1/16 Inch) Below Seating Plane) ..•••...•.. , ..•••.......••. 260·C for 3 sec.
Notes:
1. Derate maximum DC current above TA = SO·C at 1mAloC per segment, see Figure 2.
2. See Figure 1 to establish pulsed operating conditions.

205

Electrical/Optical Characteristics at TA=25°C
Description

Max.

Symbol

Te.t Condition

MIn.

Typ.

LuminoUS Intensity/Segment
=100·C.

1I

200

2.4

180

2.2

1=

0:
0:

140

wE

1.6

"

120

.,>-

1.4

;:

100

00

2w

1.2

=>~

1.0

w"

0.8

~

=>

.

0
0:

80

"~

60

I

...
~

~~

=>"
~~

Ir'"
~

~<

~"

>'"
-0

I I

. 'r

2.0

160

1.8

~g

0."

40

20

'"

0."

!

:

I

1.2

1."

1.6

1.8

2.0

V

I

/

/,

I

: .

V

/i

I

/

L

J
I

/

0.2

o

VF - FORWARD VOLTAGE - V

I I V
! I VI

I

I

o
1.0

I

10

20

30

40

50

60

IF - SEGMENT DC CURRENT - rnA

Figure 4. Peak Forward Segment
Current VB. Peak Forward Voltage.

Figure 5. Relallve Luminoul Intenlily VI.
DC Forward Currant.

f
For a Detailed Explanation on the Use of Data Sheet Information and Recommended
Soldering Procedures, See Application Note 1005, Page 464.

207

TECHNICAl. DATA MARCH 1980

Features
• ULTRA LOW POWER
Excellent Readability at Only 500 IJA
Average per Segment
• CONSTRUCTED FOR STROBED OPERATION
Minimizes Lead Connections
• STANDARD DIP PACKAGE
End Stackable
Integral Red Contrast Filter
Rugged Construction
• CATEGORIZED FOR LUMINOUS INTENSITY
Assures Uniformity of Light Output from
Unit to Unit within a Single Category
• IC COMPATIBLE

Description
The HP 5082-7400 series are 2.79mm (.11"), seven
segment GaAsP numeric indicators packaged in 3,
4, and 5 digit end-stackable clusters. An integral
magnification technique increases the luminous intensity, thereby making ultra-low power consumption possible. Options include either the standard
lower right hand decimal'J>Oint or a centered decimal point for increased regibility in multi-cluster
applications.
Applications include hand-held calculators, portable instruments, digital thermometers, or any other
product requiring low power, low cost, minimum
space, and long lifetime indicators.

Device Selection Guide
Part Number

Digits,';;';'

Cluster ,,'

, ~I!,eftl :
4

208

Center Decimal Point

Right Decimal Point

5082·7402

5082-7412

,5082-7403

5082·7413

5082·7404

5082-7414

5082·7405

5082-7415

Absolute Maximum Ratings
•......

y;.~

Symbol

. t.~)!~rd Current per Segment (Duration

Min.

Max•

Units

110

mA

.5

mA

tro

mW

75

oc

100

°C

5

V

< 1 msec) .

[-

~ ..

NOTES: 1.

At 25°C; derate 1 mWfC above 25°C ambient.

2. See Mechanical Section for recommended flux removal solvents.

Electrical/Optical Characteristics at TA = 25°C
Min;·

M.ax.

Typ. .

Units

I.I\VG'" tmA .

Iv

(lp!( .. 10.mA
duty eycl&= 10%)

5

20
.655

XPEAK

VF-.
~\.;.~ CUrrent/Segment or dp

nm

1.6

IF=10mA
~"'5V

IR
t"

Sled

2.0

V

100

SlA

10

t1

os

NOTES: 3. The digits are categorized for luminous intensity. Intensity categories are designated by a letter located on the back side of
the package. 4. Operation at Peak Currents less than 5mA is not recommended. 5. Time for a 10%-90% change of light intensity for step change in current.
6%/
10%v.

///

~

20%

///

.. riuTv· CVCLE •

h {/

vW

/1/

f

0~-.4~-.~B~'~2~'~6~2~.0~2~4~2~.B-732·

Forward Voltage.

.....

~~

in

1E
I~

z

:E
:::>
-'

~

STORAGE AND
OPERATING
b=

1. 0

1.6

I

,

1.4

!

I

~

1.0

.B

'""4
-60

-40

-20

0

20

40

TC - CASE TEMPERATURE -

-

1.2

I
I
I

.6

a:

2.0

4.0

1.B

Ho-! .

RANGE

'~

"':::>o

0.6 0.8 1.0

6.0

Figure 2. Typical Time Averaged Luminous Intensity per Sagment
(Digit Average) vs. A_age Current per Segment.

Figura 1. Forward Current vs.

5. 0

0.4

I.... - AVERAGE CURRENT PER SEGMENT - rnA

VF - FORWARD VOLTAGE - V

>
I-

~
~ ~V

1

I

I

I

V

~
k::'::: r--

--

.4

.2
60

20

BO

°c

40

80

100

IpEAK - PEAK CURRENT PER SEGMENT - mA

Figure 3. Relative Luminous Intensity vs. Case
Temperature at Fixed Current Level.

Figure 4. Relative Luminous Efficiency
Peak Current per Segment.

209

VI.

package Description

NOTES: 1. Dimensions in millimeters and (inches).
2. Tolerances on all dimensions are ±O.038mm (±.015 in.) unless otherwise noted.

1

1... 1.27,0.13
I - (.050, .005)
12

1.90

±O.13l

1.075' .005)

--r-~~~~~
(~2:: ~O~~)P"'-"r""·.".4"'4""·1'

~--~~~~~~~~
1

1537

1+--1.605)}~EF

I

~~J5=

4.83

r'

1.190)

~ l n. ,,:

,," '"

MAX

1070)

051 _ II
(.020)--, r-

~

TYP

~

4.43'0.51
2.54 1.175' .020)
1.100)
TYP.

Figura 5. 5082-7402/-7403/-7404/
-7412/-7413/-7414

Figure 6. 5082-7405n415

Magnified Character Font Description
DIMENSIONS INMILI.lMETERS AND IINCHES!.

~57~~.~21.

D.EVICES
2.7!l4 1.111

5082-7402
5082-7403
5082-7404
5082-7405.

REF.

dp.~8
d

Figure 7; Center Decimal Poiltt ConfiQu;.tion.

Device Pin Description
PIN NO.

1

5082-7402n412
FUNCTION
SEE NOTE 1..

2

ANODEe

3

. ANODEc

4

CATHODE 3

5

ANODE dp

6

CATHODE

7

ANODEg

8
9

ANODEd

10

. 5082-7403n413 .
FUNCTION

ANODEe

4

ANODEf
CATHODE 2 .

11

ANODEb

12

ANODE a

13
14
NOTE 1. Leave Pin unconnected

210

All Devices

Electrical/Optical
r

l"

construction allows use of standard DIP insertion tools
and techniques. Alignment problems are simplified due to
the clustering of digits in a single package. The shoulders
of the lead frame pins are intentionally raised above the
bottom of the package to allow tilt mounting of up to 20·
from the PC board.

The 5082-7400/-7410 series devices utilize a monolithic
GaAsP chip of 8 common cathode segments for each
display digit. The segment anodes of each digit are
interconnected, forming an 8 by N line array, where N is
the number of characters in the display. Each chip is
positioned under an integrally molded lens giving a
magnified character height of 2.79mm (0.11) inches.
Satisfactory viewing will be realized within an angle of
approximately ±30· from the center-line of the digit.

To improve display contrast, the plastic incorporates a red
dye that absorbs strongly at all visible wavelengths except
the 655 nm emitted by the LED. In addition, the lead
frames are selectively darkened to reduce reflectance. An
additional filter, such as Plexiglass 2423, Panelgraphic 60
or 63, and SGL Homalite 100-1605, will further lower the
ambient reflectance and improve display contrast.

The decimal point in the 7412, 7413, 7414, and 7415
displays is located at the lower right of the digit for
conventional driving schemes.

To optimize device optical performance, specially
developed plastics are used which restrict the solvents
that may be used for cleaning. It is recommended that only
mixtures of Freon (F113) and alcohol be used for vapor
cleaning processes, with an immersion time in the vapors
of less than two (2) minutes maximum. Some suggested
vapor cleaning solvents are Freon TE, Genesolv DI-15 or
DE-15, Arklone A or K. A 60·C (140·C) water cleaning
process may also be used, which includes a neutralizer
rinse (3% ammonia solution or equivalent), a surfactant
rinse (1% detergent solution or equivalent), a hot water
rinse and a thorough air dry. Room temperature cleaning
may be accomplished with Freon T-E35 orT -P35, Ethanol,
Isopropanol or water with a mild detergent.

The 7402, 7403, 7404 and 7405 displays contain a centrally
located decimal point which is activated in place of a digit.
In long registers, this technique of setting off the decimal
point significantly improves the display's readability. With
respect totiming, the decimal point is treated as a separate
character with its own unique time frame.

Mechanical
The 5082-7400 series package is a standard 12 or 14 Pin
DIP consisting of a plastic encapsulated lead frame with
integral molded lenses. It is designed for plugging into
DIP sockets or soldering into PC boards. The lead frame

211

Flin-

SOLID STATE
NUMERIC INDICATOR
(7 segment Monolithic)

HEWLETT

~a PACKARD

5082-7430
SERIES

TECHNICAL DATA MARCH 1980

Features
• MOS COMPATIBLE
Can be Driven Directly from many
MOS Circuits
• LOW POWER
Excellent Readability at Only 250 itA Average
per Segment
• CONSTRUCTED FOR STROBED OPERATION
Minimizes Lead Connections
• STANDARD DIP PACKAGE
End Stackable
Integral Red Contrast Filter
Rugged Construction
• CATEGORIZED FOR LUMINOUS INTENSITY
Assures Uniformity of Light Output from
Unit 10 Unit within a Single Category

Description
The HP 5082-7430 series displays are 2.79mm (.11
inch, seven segment GaAsP numeric indicators packaged in 2 or 3 digit end-stackable clusters on 200
mil centers. An integral magnification technique increases the luminous intensity, thereby making ultra-low power consumption possible. These clusters

have the standard lower right hand decimal points.
Applications include hand-held calculators, portable
instruments, digital thermometers, or any other
product requiring low power, low cost, minimum
space, and long lifetime indicators.

Device Selection Guide
Digits per
Cluster

Configuration
Part Number
Device

Package

2(righd

I lalal

(Figure 5)

5082-7432

3

lalalal

(Figure 5)

5082·7433

212

Absolute Maximum Ratings
,SymbOl

Parameter

r

,Min.

Max. '

Peak Forward Current per Segment Or dJ), (D,!rlltion <~~r

-40

Storage Temperature

.~'

ReverseVoltage
NOTES: 1. Derate linearly@ 1 rrNVfc above 25°C ambient.

mA
mA··

75

"".,~."

POwlw' Dissipation !lei' Digit {U

Operating Temperature, Ambient

Unlt$

50
',5

100

"C

5

v

2. See Mechanical section for recommended flux removal solvents.

Electrical/optical Characteristics at TA =25°C
Parameter
. Luminous IntensitylSegll'l$flt or dp[3Al

symbOL, .' ;T~.~tiOn

"

··.IV .-

<,,: -':'lAVG .. 5Oi\IA

' Min.

Typ,

10

40

"UPK,,:5mA
. &ity cycle" 10%)
Peak Wavelength

'ApEAK

Forward Voltage/Segment or dp

,VF'

Reverse CurrentlSegment or dp
Rise and Fall Time [5)

~,

,Max, ,

JACd .

655

1.55

IF=5mA
VR =5V

Units

nm
2.0

V

100

vA

10
n$'
t r • t1
NOTES: 3. The digits are categorized for luminous intensity. Intensity categories are desi~nated by a letter located on the back side of
the package. 4. Operation at Peak Currents less than 3.5mA is not recommended. 5. Time for a 10%-90% change of light in·
tensity for step change in current.

..

50
E

I-

40

~

a:
a:

3S

"ca:

30

:::>

{

'B

"

4S

";;:a:

2S

12

20

"~

1S

I

I
I2

cWW
"':;

"",
a: w

1000

500
400

, OUTV eycLe • 5% ~

300

,,;~

w" 200
>"'
"w
w> 100

.

!!il-

~~

1-0;
-,2

"W
ul-

i:~

> ..

1-:::>

10

z
!!

1I
.2

.4

.6

.8

20

:::>

...I

/. q I

.~ ~

10
0.1

1.0 1.2 1.4 1.6 1.8 2.0

v,: - PEAK FORWARD VOLTAGE - v
Figure 1. Peak Forward Current VI.
Peak Forward Voltage

I

',/

C

I

:J.

50
40
30

~/

0.2 0.3

1/
/"
0.5

2

1.0

10

3

IAVG - AVERAGE CURRENT PER SEGMENT - rnA

Figure 2. Typical Time Averaged Luminous Intensity
per Segment vs. A_ege Current per Segment

10
1.4

>u

>

I-

0;

~~

~

.
I-

~

:::>
0

z

~

:3

w

>

;::

"u:la:

o.S
0.4
0.3

/
!1
......
.. I
!!
iJ.
2

w

"",.

,

w

-20

20

40

..

1.0

:::>
0

.8

ill'!!..

:::>

.6

...I

w

>
;::
«
...I
w
a:
-40

V

2

0.2
0.1
-60

1.2

60

~

.

.4
.2

10

80

°c
Figure 3. Relative Luminous Intensity VI. Ambient
Temperature at Fixed Current Level

20

30

40

50

IpEAK - PEAK CURRENT PER SEGMENT - rnA

TA - AMBIENT TEMPERATURE -

Figure 4. Relative Luminous Efficiency vs. Peak
Current per Segment

213

package Description
5.0~~:00)

1---1
,
,
NOTES: 1. DIMENSIONS IN MilLIMETERS AND (INCHES).
2. TOLERANCES ON ALL DIMENSIONS ARE 0.038 ± (.015)
UNLESS OTHERWISE SPECIFIED.

I--+-___

1.40 J I
1.0~5)

PIN 1 KEY
1.22'.178
10.48' .007)

7.621.3

MAX.

(.300

2.03

(,080)

~

1.78
--.--F(.070)

6.60 (.260)
MAX.

W

I
1
L:,

15.37 (,605) ~I

-t-:

f

'j
1"-

, ,

~
-i

I

4.06
1.160)

~~ING PLANE

1

432.051
'(,170;.020)

---.T

I ---..
-i-2.54 1.100)
1.27 (.050)

.510 ±.125
(.020 ± .005)

REF.

Figure 5.

Magnified Character Font Description
DEVICES
5082-7432
5082·7433

DIMENSIONS IN MILLIMETERS AND (INCHES).

Figure 6.

Device Pin Description
PIN
NUMBER

5082-7432

5082-7433

FUNCTION

FUNCTION

1

SEE NOTE l.

CATHODE 1

2

ANODEe

ANODEe

3

ANODEd

ANODEd

4

CATHODE 2

CATHODE 2

5

ANODEc

ANODEc

6

ANODEdp

ANODEdp

7

CATHODE 3

CATHODE 3.

8

ANODEb

ANODEb

9

ANODEg

ANODEg

10

ANODE a

ANODE a

11

ANODEf

ANODEf

12

SEE NOTE 1.

SEe NOTE 1.

NOTE 1. Leave Pin unconnected.

214

~

.010) - -

I

Electrical/Optical

Mechanical

The 5082-7430 series devices utilize a monolithic GaAsP
chip of 8 common cathode segments for each display
digit. The segment anodes of each digit are interconnected, forming an 8 by N line array, where N is the
number of characters in the display. Each chip is
positioned under an integrally molded lens giving a
magnified character height of 2.79mm (0.11) inches.
Satisfactory viewing will be realized within an angle of
approximately ±20o from the center-line of the digit.

The 5082-7430 series package is a standard 12 Pin DIP
conSisting of a plastic encapsulated lead frame with
integral molded lenses. It is designed for plugging into
DIP sockets or soldering into PC boards. The lead frame
construction allows use of standard DIP insertion tools
and techniques. Alignment problems are simplified due to
the clustering of digits in a single package.
To optimize device optical performance, specially
developed plastics are used which restrict the solvents
that may be used for cleaning. It is recommended that only
mixtures of Freon (F113) and alcohol be used for vapor
cleaning processes, with an immersion time in the vapors
of less than two (2) minutes maximum. Some suggested
vapor cleaning solvents are Freon TE, Genesolv DI-15 or
DE-15, Arklone A or K. A SO°C (140°C) water cleaning
process may also be used, which includes a neutralizer
rinse (3% ammonia solution or equivalent), a surfactant
rinse (1% detergent solution or equivalent), a hot water
rinse and a thorough air dry. Room temperature cleaning
may be accomplished with Freon T -E35 or T -P35, Ethanol,
Isopropanol or water with a mild detergent.

To improve display contrast, the plastic encapsulant
contains a red dye to reduce the reflected ambient light.
An additional filter, such as Plexiglass 2423, Panelgraphic
60 or 63, and SGL Homalite 100-1605, will further lower the
ambient reflectance and improve display contrast.
Character encoding on the 5082-7430 series devices is
performed by standard 7 segmentdecoder/drivercircuits.
Through the use of strobing techniques only one
decoder/driver is required for very long multidigit
displays.

(
Figure 7. Block Diagram for Calculator Display

215

TECHNICAL DATA MARCH 1980

Features
• MOS COMPATIBLE
Can be driven directly from MOS circuits.
• LOW POWER
Excellent readability at only 250IJA
average per segment.
• UNIFORM ALIGNMENT
Excellent alignment is assured by design.
• MATCHED BRIGHTNESS
Uniformity of light output from digit to
digit on a single PC Board.
• AVAILABLE IN 50.8mm (2.0 Inch) AND
60.325mm (2.375 Inch) BOARD LENGTHS

Description
The HP 5082-7440 series displays are 2.67mm (.105")
high, seven segment GaAsP Numeric Indicators mounted
in an eight or nine digit configuration on a P.C. Board.
These speCial parts, designed specifically for calculators,
have right hand decimal pOints and are mounted on

5.0Bmm (200 mil) centers. The plastic lens magnifies the

digits and includes an integral protective bezel.
Applications are primarily portable, hand-held calculators
and other products requiring low power, low cost and long
lifetime indicators which occupy a minimum of space.

Device Selection Guide
Digits

Configuration

, Per
" PC Board

Part No.
Package

5082·7440
(Figure 51

5082·7448
5082-7441
(Figure 5)

5082·7449

216

Absolute Maximum Ratings
..•..

Parameter
Peak Forward Current per Segment or dp (DuratiOn < 500~sl
Average Current per Segment or dp[1 J
Power Dissipation per Digit

..

Operating Temperature, Ambient

-~"

SVnmol

Min.

' . .. J~aAK..

.....

....

Ts

Reverse Voltage

VA

3

mA

50

mW

-20

TA

Storage Temperature

Units
mA

. ..

Po

:

..

Max.
50

.....

....·I.,v~

...............

.

...

'

~20

Solder Temperature at connector edge (t"';;3 sec.) [2)
NOTES: 1. Derate linearly

@

0.1 mAtC above 60°C ambient.

+85

"c

+85

¢C

5

V

230

"c

2. See Mechanical section for recommended soldering techniques
and flux removal solvents.

Electrical/Optical Characteristics at TA =25°C
Parameter
luminous Intensity/Segment or dp[3,4]

Symbol

Iv

Peak Wavelength

Apeak

Forward Voltage/Segment or dp

VF

TestCondi.tlon

Min.

Typ.

lAva = 500llA
(lpK = 5mA
duty cycle'" 10",{,)

9

40

J,lcd

655

nm

1.55

V

IF : SmA

Max.

NOTES: 3. See Figure 7 for test circuit.
4. Operation at Peak Currents of less than 3.5mA is not recommended.

,

50

'"

E

45

I-

40

iE
a:

35

a:

::>

"a:
;:
'a:"

30

~

20

'"
~

15

~

~ 400,,",
500r:~~+=:t~:t~:t~~~~~
...L'
II"
~ffi ~~ 300
OUTY CY.C.:L.E •.6'l_'~"~' ~vl/
200
>a:

"'::'
~~

25

~~

u~

I

o
o

.2

.4

.6

.8

~

20

0.1

;;;

>

~
cr.

~
1

0.5

"

........

U

1.2

~
'"::>

1.0

Z

.8

Cl

;;;

---- ~ IiIh.

::>
..J

w

>
;::

.6

'ula:" ."
.2

0.3

0.2

-60

>-

1.4

"iE

0.4

o. 1

0.5

2

1.0

3

10

1.6

'3
w

0.2 0.3

Figure 2. Typical Time Averaged Luminous Intensity
per Segment vs. A verage Current per Segment

>I-

l!

V,V/ /

'AVG - AVERAGE CURRENT PER SEGMENT - rnA

10

~

~ry

~ ,oh~ ,V

'/

1:0 1.2 1.4 1.6 1.8 2.0

Figure 1. Peak Forward Current vs.
Peak Forward Voltage

~

f--f-+--+--nq..-A:'--i--t---i

sor:~~f;~~~t::t~~4=~~
t1/.

430
0

VF - PEAK FORWARD VOLTAGE - v

iE
I-

100

ii: ~

~~

10

~

;;

r:--.-.----r---r--..-,-,..-..,

@~

Cl

(

1000

-40

-20

20

40

60

...... l-

V
J

I

II

5

80

TA - AMBIENT TEMPERATURE - °c

10

15

20

25

30

35

40

45

50

IpEAK - PEAK CURRENT PER SEGMENT - rnA

Figure 3. Relative Luminous Intensity vs. Ambient
Temperature at" Fixed Current Level

Figure 4. Relative Luminous Efficiency vs. Peak
Current per Seg ment

217

Units

package Description

Figure 5.

Magnified Character Font Description
:,'OeVICES, "
. ,'f;0s2-7440 ,.
,!i082·744t ..
"6082-7448 " '

:~~~~~0;;:<~!Ji~"·:,;,:, ))im, B'

~;,~l..o5&~.2bfiO) ~O.7~{.~) ,5,b8(~2.00} ,

.:_2-7449
--:
-",',

,~

,

"~;.' ~ ,-,;

'Dim;C \

.'

Tolerances: ±.381 (.015)

Table 1.

Figure 6.

Device Pin Description
,p'j~

:'",~.'

,1': '
2
, 3,:

5' ,

,'6': '

,t~,
;;8"

218

Electrical/Optical
The HP 5082-7440 series devices utilize a monolithic
GaAsP chip containing 7 segments and a decimal point for
each display digit. The segments of each digit are interconnected, forming an 8 by N line array, where N is the
number of characters in the display. Each chip is positioned
under a separate element of a plastic magnifying lens, producing a magnified character height of 0.105" (2,67mm).
Satisfactory viewing will be realized within an angle of approximately ±20° from the centerline of the digit. The secondary lens magnifier that will increase character height
from :;:.67mm (0.105") to 3.33mm (0.131 ") and reduce
viewing angle in the vertical plane only from ±20° to approximately ±18° is available as a special product. A filter, such
as Plexiglass 2423, Panelgraphic 60 or 63, and Homalite 1001600, will lower ambient reflectance and improve display
contrast. Character encoding of the -7440 series devices is
performed by standard 7 segment decoder driver circuits.

through holes at the connector edge of the board or by insertion into a standard PC board connector.
The devices may be soldered for up to 3 seconds per tab at
a maximum solderihg temperature of 230°C. Heat should
be applied only to the edge connector tab areas of the PC
board. Heating other areas of the board to temperatures in
excess of 85°C can result in permanent damage to the display. It is recommended that a rosin core wire solder or a
low temperature deactivating flux and solid core wire
solder be used in soldering operations.

Special Cleaning Instructions
For bulk cleaning after a hand solder operation, the following process is recommended: Wash display in clean liquid
Freon TP-35 or Freon TE-35 solvent for a time period up
to 2 minutes maximum. Air dry for a sufficient length of
time to allow solvent to evaporate from beneath display
lens. Maintain solvent temperature below 30°C (86°F).
Methanol, isopropanol, or ethanol may be used for hand
cleaning at room temperature. Water may be used for hand
cleaning if it is not permitted to collect under display lens.

The 5082-7440 series devices are tested for digit to digit
luminous intensity matching using the circuit depicted in
Figure 7. Component values are chosen to give an IF of
5mA per segment at a segment V F of 1.55 volts. Th is test
method is preferred in order to provide the best possible
simulation of the end product drive circuit, thereby insuring excellent digit to digit matching. If the device is to
be driven from Vee potentials of less than 3.5 volts, it is
recommended that the factory be contacted.

Mechanical
The 5082-7440 series devices are constructed on a standard
printed circuit board substrate. A separately molded plastic
lens containing 9 individual magnifying elements is attached
to the PC board over the digits. The device may be mounted'
either by use of pins which may be soldered into the plate

Solvent vapor cleaning at elevated temperatures is not recommended as such processes will damage display lens. Ketones, esters, aromatic and chlorinated hydrocarbon solvents
will also damage display lens. Alcohol base active rosin flux
mixtures should be prevented from coming in contact with
display lens.
These devices are constructed on a silver plated printed circuit board. To prevent the formation of a tarnish (AQ2S)
which could impair solderability, the boards should be stored
in the unopened shipping packages until they are used. Further information on the storage, handling and cleaning of silver-plated components is contained in Hewlett-Packard Application Bulletin No.3.

f

Figure 7. Circuit Diagram used for Testing the Luminous Intensity of the HP 5082-7440

219

.',

r/in-

HEWLETT

~I:. PACKARD

SPECIAL PARTS FOR
SCIENTIFIC AND
BUSINESS CALCULATORS
TECHNICAL DATA MARCH 1980

Features
• 12, 14, AND 16 DIGIT CONFIGURATIONS
• MOS COMPATIBLE
Can be driven directly from most
MOS circuits.
• LOW POWER
Excellent readability at only 250JlA
average per segment.
• UNIFORM ALIGNMENT
Excellent Alignment is assured by
design.
• MATCHED BRIGHTNESS
Uniformity of light output from digit
to digit on a single PC board.

Description
The HP 5082-7442, 7444, 7446, and 7447 are seven segment GaAsP Numeric indicators mounted in 12, 14, or 16 digit
configurations on a P,C. board. These special parts, designed specifically for scientific and business calculators, have
right hand decimal points and are mounted on 175 mil (4.45mm) centers in the 12 digit configurations and 150 mil
(3.81 mm) centers in the 14 and 16 digit configurations. The plastic lens magnifies the digits and includes an integral
protective bezel.
Applications are primarily portable, hand held calculators, digital telephone peripherals, data entry terminals and other
products requiring low power, low cost, and long lifetime indicators which occupy a minimum of space.

Device Selection Guide
Digits
Per PC
Board
12

Configuration

2.54

Eit='
n D.
n D.
n D.
n D.
n D.
n Cl.
n r'
n D.
n
_1• ..:.1. CI.
=1. D.
8

2.92
(.115)

P

Figure 4
J'

P

C'

f3 D

n r'
CJ ,--/ n n n n n n
L .CJ. D.
=1. =1. D.
D. D. Ct. D.O. Ct. Ct.

2.84

(.112)
16

,

C/CI
D Lt.
CI Lt.
Cl '-. Lt.
D Lt.
CI Lt.
Cl _I. Lt.
CI L.
CJ _I. Lt.
D
'.CJ. Lt.

2.54
(.100)

14

Package, 'NO."

DEVICE

(.100)

14

Part'

Digit
Height
mm (inches)

B

P

C'=1.

ClC/D
D D DD CI CI D D CI DD
C • Lt. '- • Lt. _I. Lt. Lt. Lt. Lt. Lt. Lt. Lt. Lt. Lt. Lt. CJ.

'5082-7447 is a 5082-7444 with a slide-in cylindrical lens to provide added magnification.

220

Figure 5

5082~!'

74~
anct:

,7445
7444

;';

Figure 5

.7447
.,'

Figure 6,

:',,'

7446 '
,

Maximum Ratings
Parameter

(
Storage Temperature
Reverse Voltage
Solder Temperature at connectoredge(t "'3,SeC:)
NOTES:

1. Derate linearly at O.1mAfOC above 600C ambient.
2. See Mechanical section for recommended soldering techniques and flux removal solvents.

Electrical/Optical Characteristics at TA=25°C
Part No.

Parameter

744217445
Luminous Intensityl
Segment or dp(ll'
(Digit Average)

744417447

7446
Peak Wavelength

7442/7445
7444/7447
7446
NOTE:

Forward Voltagel
Segment or dp

3. Operation at Peak Currents of less than 3.5mA is not recommended.

50

E

"

45

I-

40

~
~

35

u

30

:0

>
Iin

~

I-

~

I

0

a:

(

"a:f2"

25

'"~

15

I

-..,...-,.

20

==....

-

o

:3
w

~

a:

J
o

Z

;;
>

10

:t

'"o

:0

.I
.2

.4

.6

.8

1.0 1.2

1.4

1.6 1.8 2.0

VF - PEAK FORWARD VOLTAGE -

Figure 1. Peak Forward Current vs.
Peak Forward Voltage

v

T A - AMBIENT TEMPERATURE -

°c

Figure 2. Relative Luminous Intensity vs.
Ambient Temperature at Fixed
Current Level.

IpEAK - PEAK CURRENT PER SEGMENT - rnA

Figure 3. Relative Luminous Efficiency vs.
Peak Current per Segment.

Electrical/Optical
The HP 5082-7442, 7444, 744S, 7446 and 7447 devices
utilize a monolithic GaAsP chip containing 7 segments
and a decimal point for each display digit. The segments
of each digit are interconnected, forming an 8 by N line
array, where N is the number of digits in the display. Each
chip is positioned under a separate element of a plastic
magnifying lens, producing a magnified character.
Satisfactory viewing will be realized within an angle of
approximately ±20o from the centerline of the digit. A
filter, such as plexiglass 2423, Panelgraphic 60 or 63, and

Homalite 100-1600, will lower the ambient reflectance and
improve display contrast. Digit encoding of these devices
is performed by standard 7 segment decoder driver
circuits.
These devices are tested for digit-to-digit luminous
intensity matching. This test is performed with a power
supply of 5V and component values selected to supply
SmA IPEAK at VF = 1.SSV. If the device is to be driven from
Vee potentials of less than 3.Svolts, it is recommended that
the factory be contacted.

221

Mechanical Specifications

Special Cleaning Instructions

The 5082-7442, 7444, 7445, 7446, and 7447 devices are
constructed on a silver plated printed circuit board
substrate. A molded plastic lens array is attached to the PC
board over the digits to provide magnification.

For bulk cleaning after a hand solder operation, the
following process is recommended. Wash display in clean
liquid Freon TP - 35 or Freon TE - 35 solvent for a time
period up to 2 minutes maximum. Air dry for a sufficient
length of time to allow solvent to evaporate from beneath
display lens. Maintain solvent temperature below 300 C
(86° F). Methanol, isopropanol, or ethanol may be used for
cleaning at room temperature. Soap and water solutions
may be utilized for removing water-soluble fluxes from the
contact area but must not be allowed to collect underthe
display lens.

These devices may be mounted using anyone of several
different techniques. The most straightforward is the use
of standard PC board edge connectors. A less expensive
approach can be implemented through the use of stamped
or .etched metal mounting clips such as those available
from Burndy (Series LED-B) or JAV Manufacturing
(Series 022-002). Some of these devices will also serve as
an integral display support. A third approach would be
the use of a row of wire stakes which would first be
soldered to the PC mother-board and the display board
then inserted over the wire stakes and soldered in place.

Solvent vapor cleaning at elevated temperatures is not
recommended as such processes will damage display
lens. Ketones, esters, aromatic and chlorinated hydrocarbon solvents will also damage display lens. Alcohol
base active rosin flux mixtures should be prevented from
coming in contact with display lens.

The devices may be soldered for up to 3 seconds per tab at
a maximum soldering temperature of 230°C. Heat should
be applied only to the edge connector tab areas of the PC
board. Heating other areas of the board to temperatures in
excess of 85°C can result in permanent damage to the
lens. It is recommended that a rosin core wire solder or a
low temperature deactivating flux and solid core wire
solder be used in soldering operations. A solder
containing approximately 2% silver (Sn 62) will enhance
solderability by preventing leaching of the plated silver off
the PC board into the solder solution.

These devices are constructed on a silver plated printed
circuit board. To prevent the formation of a tarnish (Ag,S)
which could impair solderability, the boards should be
stored in the unopened shipping packages until they are
used. Further information on the storage, handling and
cleaning of silver-plated components is contained in
Hewlett-Packard Application Bulletin No.3.

Device Pin Description
5082·7442
5082·7444

Pin
No.
1

2
3
4
5

6
7

8
9
10
11
12
13
14
15
16
17
18
19
20
21

22

5/)82~7447
Fun~ion

.

Cathode-DlgR 1,,)AriO(j!7S.~~Al~~r:!l'

';lil~~:m~~~~('

:CA ~:toh:d0~·s;e~. Dgil:mg li,e·t:.n 5It ·.~A :.O~_·. :~"e.·d · .·; ~ ·. ~p ~.': r;~~~~=;f,J:t;~l:;

calh~..Oi~t'~d"'~~;.~-"u •·.•:.·,•;.•'·.: ~A.~:on~1. ~.:~m·~nt~.~·a~.i.•,.-•,·~:•.·.~,.;:.•
'a'.

;i.·;•'. ·.: ·.•: •.• nn.•.••n.:•n.
. :..•..

•.•.•.•...

[.eg
. •.

·.s·.t
·. .·.•·... :".'.rne,··.·
.•• .•,•.
s

...·•. .•.•·.... ·.:.•."._·.;;·
.•·.·.•.•.

.•..·..•

:De:
.• .• •. . •. •.'.:. . •."•.•,.• . . •.•.•'. ..;. .:..;.,.•. .;. . . .

·t
...
...
' ·.•..
i .• ·.•...
.•.
·
•

.•...

Anode-Segmente
'· •.. 'Cat~6{git.2;·
Cathode-Digit 7 .,Cathode:.Q1gf~".t·) •
"." .
Anode-Segment d ' . 'C;attlod~Di91t{.~).·' ",
Cathode-Digit 8
: Cl;\thod~Digl~5 :.~;.::
Anode-Segmentg:Cath()dEt[)igit-l2>"
Cathode-Digit 9
.. yath~Dig1t6.';'·
Anode-Segmentb
.. c.athod.:Dfglt 11" .
Cathode~Digit1 0
.' ·.:·cath~~wDigJt1iJ·: ~f
Anode-8egment
:~.b.at.~()d~Digi~;O·,:i·
CathodewDigit 11
Cat,h.o~e~Qiglt.~';,c; '.."

':1:.'.:.. ..

.•.•

""""'"

.••.• .

,,'

.

f

~::~~::~:~:i ~;: C~thOd~D~i~r:~X;.~C~~h~ie:Oi9itJ~, .

"i;

CathodewD i g i t 1 4 ' / ;

..• '

23
24

·i,(·.'

222

'S.Oatno(j..:'Digit14

c.::,

.;rjB:::6i~:;j:··'

package Dimensions

-==1

1-----56.812:~-)
4.5 (.175) (11 PlCSEQLSP.
NON-ACCUM TOLERANCES)

1.9 (.075)

j

"::~:~:~~L~)~

1.160:t .005)

~IAMETEA

r

PROTECTIVE
BEZEL

THROUGH
20 PLACES
;,13 (.005)

Figure 4.

60.3 (2.375)

1-~~~~~~~~~-56.8

_~~~~~~~~~~'I

12.235)-

3.8 (.150) (13 PlCS EQL SPC.
I ~...~~~~+-~

NON·ACCUM. TOLERANCES)

1.02± .13
(.040 ± .005)

4.72 ± .13
(.186 ± .005)

50827444

50827447

Figure 5.

t--~~~~~~~~~~- 1~9.;~: °O~~)~~~~~~~~~~~~~--+I

[

(.248±.015)
~6'30'0'3B

-

r

t--~~~~~~~~~- I~.~: ~~~) ~~~~~~~~~~~~-

11

l

~ ,~.,

__

5.64 (.2221

1.SS± .25

13.34 ± 0.38

t

11.18

1.440)

~~:'-':"-':~~~~~~~~~-~-

1.021.040IOIA
PLATED THRU
24 HOLES

1. 525 l'oI5)

I

~1.'B6'

4.061.160)
4.72 ± 0.38

Figure 6.

DEVICE

5082·7442

2:54
1.100)

5082·7445

.-5082·1447

y
1.42
(.056)
1.40

(.100)

508z.?444

5062·7446

X

2.54

(.065)

2.54

1.42

(.I00r

(.()56)

2.92

!.40

(.115)

f~

2.84
(.112)

223

tAO

(.()55)

NOTES: 1. ALL DIMENSIONS IN MILLIMETRES AND
(INCHES).
2. TOLERANCES ON ALL DIMENSIONS ARE
:to.3S (.0,.5) UNLESS OTHERWISE
SPECIFIED.

.015)

:~r,;;~:,':,::L'"

,\'<'

~',

'-'

10:'<~:·'~~',::,\< ..;~:\

~",t~ ~ji.,.TS

">: .:.~~"',.:.,: :,', >');:,':,,:;' ,

'(hpj HEWLETT
PACKARD

;g~'~Al~AmRS ..

·5082-1240
SERIES

TECHNICAL DATA MARCH 1980

Features
• MOS COMPATIBLE
Can be driven directly from MOS circuits.
• LOW POWER
Excellent readability at only 250IJA
average per segment.
• UNIFORM ALIGNMENT
Excellent alignment is assured by design.
• MATCHED BRIGHTNESS
Uniformity of light output from digit to
digit on a single PC Board.
• STATE OF THE ART LENS DESIGN
Assures the best possible character
height, viewing angle, off-axis
distortion tradeoff.

Description
The HP 5082-7240 series displays are 2.59mm (.102")
high, seven segment GaAsP Numeric Indicators mounted
in an eight or nine digit configuration on a P. C. Board.
These special parts, designed specifically for calculators,
have right hand decimal points and are mounted on
5.08mm (200 mil) centers. The plastic lens over the digits
has a magnifier and a protective bezel built-in. A

secondary magnifying lens, available on special request,
can be added to the primary lens for additional character
enlargement.
Applications are primarily portable, hand-held calculators
and other products requiring low power, low cost and long
lifetime indicators which occupy a minimum of space.

Device Selection Guide
Oigits
Per
PC Board

Configu~ation
Part No.
Package

Oevice
"

•••

8

B. B. B. E1.E1.8jB.
B.
..
B. B. B. B. B. B. B.B. B.

5082·7240

{Figure 51

5082·7241

..

'.'

9

(Figure 5)

.

224

Absolute Maximum Ratings
.. ~

Max. .

. Min•

. I,;,vt ...... .

··3'···

l

Units

.

..
fZ
...."

t;;
zw

5
4

3

t~

U)

:>

1.6

-- ....

a
z

iii:

:>
..J

w

>

;::

'"

..J

w


1.0

:>

.8

c
z
iii:
..J

w

>

~

/

-

. / f.-

V
1

['

.6

..J

w

0.2

;~ '.'

NOTE 4: Leave pin 1 unconnected on the 5082-7240.

226

Electrical/Optical
,..

The HP 5082- 7240 series devices utilize a monolithic
GaAsP chip containing 7 segments and a decimal point for
each display digit. The segments of each digit are inter·
connected, forming an 8 by N line array, where N is the
number of characters in the display. Each chip is positioned
under a separate element of a plastic magnifying lens, producing a magnified character height of 2.59mm (0.102").
Satisfactory viewing will be realized within an angle of approximately ±20° from the centerline of the digit. A secondary lens magnifier that will increase character height from
2.59mm (.102") to 3.56mm (.140") is available as a special
product. Character encoding of the 7240 series devices is per·
formed by standard 7 segment decoder driver circuits.

mounted either by use of pins which may be soldered into
the plate through holes at the connector edge of the board
or by insertion into a standard PC board connector.
The devices may be soldered for up to 3 seconds per tab at
a maximum soldering temperature of 230°C. Heat should
be applied only to the edge connector tab areas of the PC
board. Heating other areas of the board to temperatures in
excess of 85°C can result in permanent damage to the display. It is recommended that a rosin core wire solder or a
low temperature deactivating flux and solid core wire
solder be used in soldering operations.

Special Cleaning Instructions

The 5082-7240 series devices are tested for digit to digit
luminous intensity matching using the circuit depicted in
Figure 7. Component values are chosen to give an I F of
5mA per segment at a segment VF of 1.6 volts. This test
method is preferred in order to provide the best possible
simulation of the end product drive circuit, thereby in·
suring excellent digit to digit matching. If the device is to
be driven from Vee potentials of less than 3.5 volts, it is
recommended that the factory be contacted.

For bulk cleaning after a hand solder operation, the following process is recommended: Wash display in clean liquid
Freon TP-35 or Freon TE-35 solvent for a time period up
to 2 minutes maximum. Air dry for a sufficient length of
time to allow solvent to evaporate from beneath display
lens. Maintain solvent temperature below 30°C (86°F).
Methanol, isopropanol, or ethanol may be used for hand
cleaning at room temperature. Water may be used for hand
cleaning if it is not permitted to collect under display lens.

Mechanical

Solvent vapor cleaning at elevated temperatures is not recommended as such processes will damage display lens. Ketones, esters, aromatic and chlorinated hydrocarbon solvents
will also damage display lens. Alcohol base active rosin flux
mixtures should be prevented from coming in contact with
display lens.

The 5082-7240 series devices are constructed on a standard
printed circuit board substrate. A separately molded plastic
lens bar containing 9 individual magnifying elements is attached to the PC board over the digits. The device may be

(

Circuit Diagram used for Testing the Luminous Intensity of the HP 5082·7240

227

.

Fli;-

.

.

'

.

~

.

.LAROE MONOLITHIC
NUMERIC INDICATORS

HEWLETT

~~ PACKARD

5082-7265
5082-1275
5082-7285
5082-1295

TECHNICAL DATA

MARCH 1980

Features
• LARGE 4.4Smm (.17S") CHARACTER HEIGHT
• LOW POWER
Satisfactory Readability can be Achieved with
Drive Currents as Low as 1.0-1.SmA Average
per Segment Depending on Peak Current
Levels
• MOS COMPATIBLE
Can be Driven Directly from MOS Circuits
• COMPACT INFORMATION DISPLAY
S.S4mm (.23") Digit Spacing Yields Over 4
Characters per Inch.
• HIGH AMBIENT READABILITY
High Sterance Emitting Areas Mean
Excellent Readability in High Ambient
Light Conditions

Description
The HP 5082-7265, 7275, 7285, and 7295 displays are 4.45
mm (.175") seven segment GaAsP numeric indicators
mounted in 5 or 15 digit configurations on a PC Board.
The monolithic light emitting diode character is magnified
by the integral lens which increases both character size
and luminous intensity, thereby making low power
consumption possible. Options include both a right hand
decimal point and centered decimal version for improved
legibility. The digits are mounted on 5.84 mm (230 mil)
centers.

• HIGH LEGIBILITY AND
NUMBER RECOGNITION
High OnlOff Contrast and Fine Line Segments
Improve Viewer Recognition of the
Displayed Number
• UNIFORM ALIGNMENT
Excellent Alignment is Assured by Design
• MATCHED BRIGHTNESS
Provides Uniform Light Output from Digit
to Digit on a Single PC Board

These displays are attractive for applications such as
digital instruments, desk top calculators, avionics and
automobile displays, P.O.S. terminals, in-plant control
equipment, and other products requiring low power,
display compactness, readability in high ambients, or
highly legible, long lifetime numerical displays.

• EASY MOUNTING
Flexible Mounting in Desired Position
with Edge Connectors or Soldered Wires

Device Selection Guide
Digits
Per PC
Board

5

15

5

Configuration
Device

Package

Character

7265

[ IEIIEI!ElIEI!I=I! I
ICIILIILr!Llli~II' IIH\LIIClI,LrIH1HiFII,Crlnl
I IElII3IE1IE1IE1I I

(Figure 5)

Center Decimal
POint
(Figure 7)

(Figure 6)

Center Decimal
POint
(Figure 7)

7275

(Figure 5)

Right Decimal
Point
(Figure 7j

7285

1~1!~J!13i~Ii~IjEliEII~fiI31~/iBI~lfI~181~1l

(Figure 6)

Right Decimal
POint
(Figure 7)

7295

UUUUUClUUI_ILIU _I_IuD

..

15

Part
No.
5082-

228

Absolute Maximum Ratings

[

NOTES: 1. Derate linearly at 0.12 mArC above 25°C ambient.
2. Derate linearly at 2.3 mWr C above 25° C ambient.
3. See Mechanical section for recommended soldering techniques and flux removal solvents.

Electrical/optical Characteristics at TA =25°C
Parameter
Luminous Intensity/Segment or clp
(Time Averaged) 15 digit clisplay
5082-7275.5082-7295(4,.)
luminous Intensity/Segment or dp
(Time Averaged).5 digit display
5082-7265, 5082-7285 (4,6)
Forward Voltage per Segment or dp
5082-7275,5082-729515 digit display
Forward Voltage per Segment 0( dp
5082-7265, 5082-7265 5 digit display,

Peak Wavelength
Dominant Wavelength{S)
Reverse Current per 'Segment or dp
Temperature Coefficient of Forward
Voltage
NOTES: 4. The luminous intensity at a specific ambient temperature, Iv(TA). may be calculated from this relationship:

(

Iv(T A) ; IV125° C) (.985) IT A - 25 ° q
5. The dominant wavelength Ad. is derived from the C.I.E. Chromaticity Diagram and represents the single wavelength which

defines the color of the device.
6. Operation at peak currents of less than 6.0 rnA is not recommended.

200

«

180

>-

160

a:

140

E
I

~

""

~
«
;:
a:

:r

"~

.
I

I

],
I

>-

2

Ow
w:o;

«w
"''''
a:'"
wa:

120

>w
«o.
w>
:0;>-

100

j::li5
-,2

80

()~
ii:~

60

>'"

,.:3

>-"
o

40

2

~

-~

20

o

.8

j
1.0

1.2

1.4

1.6

1_8

2.0

2.2

2.4

2.6

VF - PEAK FORWARD VOLTAGE - V

IAVG - AVERAGE CURRENT PER SEGMENT - mA

Figure 2. Typical Time Averaged Luminous Intensity
per Segment vs. A_age Current par Segment.

Figure 1. Peak Forward Current vs.
Peak Forward Voltage.

229

2,0 r--r--'--r--r~r-.,.."..-r:--'-"",,---'
',91---+---+-+.......f~·1--'--1-+-"'c+--

r

l,a I---+-+-+-+---~'-"--+--+--+--+---I
1,7
1.6
1,5

r:t!t=t::l::t;:;t.:~:e=1
i-

~r+"""'-9-'-,.-..j-t-+-+--+--l

~ri/<--"-l--+-+--+--l----Ii---t--1
',31---+>:.

Min.

Max.

Unit

Ts

-40

+100

·C

Tc

-20

+85

°C

Vee
Vt,Vop,Vu

-0.5

+7.0

V

-0.5

+7.0

V

Va

-0.5

Vee

V

230

°C

.

..'

Voltage applied to input.Joglc:dp 8Ildenabtepirl$
Voltage applied to blankih9 inPut I?)

SymbOl

.' . . . . . \

.•.. ' ..
."

Maximum solder temperature at1.59mm(.062.lncb)> .
below seating plane; t ~ 5 seconds
..... .

Recommended Operating Conditions
Description

Min.

Nom.

Max.

Vee

4.5

5.0

5.5

V

Tc

-20

+85

SymbOl
.

Supply Voltage

.

Operating temperature, case

Unit

tw

120

°C
nsee

Time data must be held before positive transition
of enable line

tSETUP

50

osee

Time data must be held after positive transition
of enable line

tHOLD

50

;

......

Enable Pulse Width

..

..

Enable pulse rise time

hLH

Electrical/Optical Characteristics
Description

osee
200

Symb()t

nsee

(Tc = -200C to +85°C, unless otherwise specified).

Teat Conditions

Typ.!'1

Max.

Unit

Supply Current

Icc

Vcc""5.5V (Numeral

112

170

mA

Power dissipation

PT

S and dp lighted)

560

935

mW

Luminous intensity per LED
(Digit average) 15,61

I,

Vcc=5.0V. Tc=2SoC

Logic low-level input voltage
Logic high-level input voltage

Min.

32

j.lcd

70
0.8

. V!L
V IH

2.0

V
V

Enable low-voltage; data being
entered

VEl.

Enable high-voltage; data not
being entered

VFH

Blanking low-voltage; display
not blanked m

VBl

Blanking high-voltage; display
blanked (71

VaH

Blanking low-level input currentl?1

lal

Vcc=5.5V. VaL=0.8V

20

j.lA

Blanking high-level input current (?I

11IH

Vcc=5.5V. V8H=4.5V

2.0

rnA

Logic low-level input current

0.8

Vcc=4.5V
2.0

V
V

0.8
3.5

V
V

I,L

Vcc=5.5V, V'L=O.4V

-1.6

mA

Logic high-level input current

It"

Vcc=5.5V. VIH""2.4V

Enable low-level input current

IkL

Vcc""5.5V. VeL"'O.4V

+250
-1.6

mA

Enable high-level input current
Peak wavelength
Dominant Wavelength lSI

IEH

XPEAK
X.

Vcc""5.5V, VEH=2.4V

+250

j.lA
j.lA

Te=25°C

655

Tc=25"C

640

nm

0.8

gm

Weight

nm

Notes: 1. Nominal thermal resistance of a display mounted in a socket which is soldered into a printed circuit board: 0 JA =5(J'CIW;
flJc=15° CIW; 2. 0CA of a mounted display should not exceed 35° CIW for operation up to Tc = +85° C. 3. Voltage values are with respect to
device ground. pin 6. 4. All typical values at Vcc=5.0 Volts, Tc=25° C. 5. These.displays are categorized for luminous intensity with the intensity category designated by a letter located on the back of the display contiguous with the Hewlett-Packard logo marking. 6. The
luminous intensity at a specific case temperature, Iv(T c) may be calculated from this relationship: Iv{Tc}=lv (25° C) e[ -.0188I'C lTc -25°C IJ
7. Applies only to 7340. 8. The dominant wavelength. Ad. is derived from the CIE chromaticity diagram and represents the single wavelength which defines the color of the device.

233

Pin.
tSETUPto---+~-'-<·t~OlD

DATA INPUT
(LOW LEVEL DATA)

Vee
ENABLE

";~

LOGIC
INPUT
Dp(2)

..

DATA INPUT
(HIGH LEVEL DATA)

BLANKING I31
CONTROL
..

GROUND

Figure 1. Timing Diagram of 5082·7300
Series Logic.

6~

VB - BLANKING VOLTAGE - V

Figure 3. Typical Blanking Control
Current VI. VA Itage for
5082·7340.

Figure 2. Block Diagram of 5082·7300
Series Logic.

1
I

Iii

~

-1.2,.".+.,..;'-"'-,..-'+"....,*"+=-=+""....,-1

aor -1.0r-++"i.....-'--'+c-'.-:"'+"-~+:.......-1

II

§
I

.§.

4.0
TC - CASE TEMPERATURE _ °c

Figure 4. Typical Blanking Control
Input Current vs.
Temperature 5082·7340.

VE - LATCH ENABLE Y '.'. ,rnA,
Logic high-leVel input current
Enable low-level input current,
Enable high-level input current '
Peak wavelen tti
Dominant Wavelength (j)
Weight,
1

','

'+100.

, ..."PA

-1.6
+130

"/JA

,triA

655

nm

,1.0

,",gm

Notes: 1, Nominal thermal resistance of a display mounted in a socket which is soldered into a printed circuit board: 9'A=5rY'CIW;
9,c=15° C/W; 2. SCA of a mounted display should not exceed 35°CIW for operation up to T A=+1 OrY'C. 3. Voltage values are with respeclto
device ground, pin 6. 4. All typical values at Vcc=5.0 Volts. T A=25°C. 5. These displays are categorized for luminous intensity with the intensity category designated by a letter located on the. back of the display contiguous with the Hewlett-Packard logo marking. 6. The
luminous intensity at a specific ambient temperature, Iv(TA), may be calculated from this relationship: Iv(TA)=lv(2S· C) (.985) [T.-25"CI
7. Applies only to 7359. 8. The dominant wavelength, Ao, is derived from the CIE chromaticity diagram and represents the single wavelength which defines the color of the device.
I

237

tSETUP;.---r_~~'''''LO

TR\ITtJ TABLE
&cODATA/I/.'

DATA INPUT

(LOW LEVEL DATAl

X.

1.6.V

DATAfNPUT

III'ii

IHIOH LEVEL DATA) , ..5V

1tTL"

ENABLE
INPUT
1.5V

10%j 1.5V

~I--'w-,~-=~I

~

90%

LOGIC
INPUT
DpE21

N;~
5~

"',
l=; e,'
LATelt'
~=:

4 - Of

MEMORV
.

•,

-

MAT~IX

DECOO~

GROUND

LED

MA~IX

DRtvER

,.

X"

~",

'1-

fi;

L

:I;

-H

'l

I.

C

H

"1\

I.

H

'\

'I.

" H:

"

l

H

I.

Ii'

:

'I."

I]

(I

I

i::'

'~:

:-.;:

::::

' ':;

'lvi,

I'

"

Ii

~

,~~;

~.

,H"

'I::,
:':1

L

\;3':

'(..,

:"~ '. L\' "'l' I"

' ',~'

I:i

Ii

,L

'H

H

H"

'L:

H

H';

L

H'

...

H

H

Hc

'1:"

fBLANKI

H

II.

H :

,H

fBLANKI

,:',t

!~\ANKl

,It
L'

(BLANKl

, f)'
f.,',

Figura 2. Block Diagram of 5082-7350
Series Logic.

~.

VDfI"#l.

OFf

VQP#!i
Vi '*ilL

V. -H
V. o\.
Va ~~"

MATRIX

6~

E

ON
LDADDATA,
LATCtlDATA
OISPLAY.()N
DISPLA .Off

BLANKINOI31

'l
ft,
'f:l
C

f:.l '

',\..

, LEO

·'1
"8'

9

~

H

"

.

.,)

,:"

I.:

t1,'

ENABLe"'

-

,508H3159

i-f'

L:'

::H:

um-~'
' '~',

I:

DECIMAl.PT. III

UP"
BLANKING (3)
CONTROL
4_

\""

L"

: H','

Pin,

Vee
ENABLE

L

~

.<11

Figure 1. Timing Diagram of 5082-7350
Series Logic.

JmA
......• IF~ 10.l1'IA .
....... ai, diodeS·,h

'v

lumil'lOll.11 ntemity per LEO (digit average)
.

Peak' wave'ength

TEST CONOITION,S

SYMBOL

Forward VOltage per LED
Power di~;pation

Absolute Maximum Ratings

MAX UNIT
5.6

V

10

mA

DESCRIPTION
Stoni~t1llT\pe(ature.

ambient
Operating temperature, ambient

NOTE:
LED current must be externally limited. Refer to Figure 9
for recommended resistor values.

240

SYMBOL MIN. MAX. UNIT
'C
-65 +125
TS

-66

Forward current; each LED

'F

+100
10

Reverse voltage, each lEO

VR

4

TA

·c

mA
V

SOLID STATE
NUMERIC
INDICATOR

HEWLETT
PACKARD

[',";,

~__~__________________-w

5082· 7010
5082· 7011

,.I' ,

TECHNICAL DATA MARCH 1980

Features
• RUGGED, SHOCK RESISTANT, HERMETIC
• DESIGNED TO MEET MIL STANDARDS
• INCLUDES DECODER/DRIVER
BCD Inputs
• TTL/DTL COMPATIBLE
• CONTROLLABLE LIGHT OUTPUT
• 5 x 7 LED MATRIX CHARACTER

Description
The HP 5082-7010 solid state numeric indicator with
built-in decoder/driver provides a hermetically tested
6.8mm (0.27 in.) display for use in military or adverse
industrial environments. Typical applications include
ground, airborne and shipboard equipment, fire control systems, medical instruments, and space flight
systems.

displayed for invalid codes. A left-hand decimal point
is included which must be externally current limited.

The 5082-7010 is a modified 5x7 matrix display that
indicates the numerals 0-9 when presented with a
BCD code. The BCD code is negative logic with blanks

Both displays allow luminous intensity to be varied
by changing the DC drive voltage or by pulse duration
modulation of the LED voltage.

The 5082-7011 is a companion plus/minus sign in the
same hermetically tested package. Plus/minus indications require only that voltage be applied to two input pins.

Package Dimensions
6082-7010

5082·7011

I

13.4

{]~

...,.-2,3

/.091

P'N

FUNCTION

P'N

FUNCTION

P'N

FUNCTION

P'N

FUNCTION

1
2

IlPput 1

5
6
7
8

Input 4

1
2
3
4

NC
NC

5
6
7
8

NC
Ground

3
4

VDP
VLED

Input 8

Notes:

Ground

Vee
Input 2

Plu.
NC

Minus/Plus
NC

1. Unless otherwise specified, the tolerance on all dimensions Is :to.38 mm. (±0.015 inchesl.
2. All dimensions in millimetres and !inchesl.
3. The package and mounting pins are tin plated Kovar.

241
----~,-,

-~-

'---

Absolute Maximum Ratings
. Unit

Symbol

Min,

Max•..

Storage Temperature, Ambient

TS

.-65

+100

Operating Temperature, Case

Te

. -55

+95

···.·.~C

Logic Supply Voltage to Ground

Vee

-0.5

+7.0 .

c.

Logic Input Voltage

VI

";0.5

+5.5

LED Supply Voltage to Ground

VLEO lll

-0.5

Decimal Point Current

lOp

Description

°c

V
V

+5.5

V

-10

mA

Max•...•

Unit

Note: 1. Above T e = 65°e derate V LED per derating curve in Figure 10.

Recommended operating Conditions
Symbol

Min.

Nom.
5.0

5.5

V

LED Supply Voltage, Display Off

Vee
VLEO

4.5·
-0.5

0

+1.0

V.

LED Supply Voltage, Display On

VLEO

3.0

4.2

Decimal Point Current

IOp[2!

0

-5.0

5.5
-10.0 .

Description
Logic Supply Voltage

•

V
mA

Logic Input Voltage, "H u State

VIH

2.0

5.5

V

Logic Input Voltage, "L" State

VII..

a

0.8

V

Note: 2. Decimal point current must be externally current limited. See application information.

Electrical/optical Characteristics

Truth Table

Case Temperature, Te = O°C to 70°C, unless otherwise specified
Description
Logic Supply CUrrent

LED Supply Current
Logic Input Current,
"H" State (ea. input)
Logic Input CUrrent,
"L"State (ea. inputl
Decimal Point
Voltage Drop
Power Dissipation

Luminous Intensity
per LED (digit avg.)
Peak Wavelength
Spectral Halfwidth
Weight
Notes:

Symbol
lee
ILEO
[3]
[5]

Test
Conditions

Typ.141 Max.

Min.

Vee=5.5V

45

75

mA

Vee
5.5V
5.5V
5.5V

255
170
125

350
235

mA

100

p.A

VLEO
5.5V
4.2V
3.5V

Vee"' 5.5V
VIH"'2.4V
Vee'" 5.5V
VIL= O.4V

IIH
IlL
VLED
-Vop

'op'" -10mA

Pr

Vee
5.5V
5.5V
5.5V

VLEO
5.5V
4.2V
3.5V

VLeo
5.5V
4.2V
3.5V

Te
25°C
25°C
25°C

[3]
[5]

Iv

Unit

-1.6
1.6
1.7
1.0
0.7
60
40

115
80
50
655
30
4.9

Aoesk
AAy,

3. With numeral 8 displayed.
4. All typical values at T = 25°e.
5. Te = DOe to 65°e for "LED =5.5V.

2.0
2.3

1.4

logic
Charactar X8 X4 X2 X1

H H H H

1

H

2

H H L H

3

H H L

4

H L H H

5

H L H L

6

H LIL H

7

H L

8

L

HIH H

I ......

9

L

H H L

.,
I"~J

Blank

L

H

L

H
L

H

H L

V

W

p.ed

l

Blank

t

HIL

nm

Blank

L

l

nm
gram

Sfank

L

I-

Srank

L

Blank

L

VIL
VIH

i

~

L

rnA

e

242

......
I_I'

0

L

:-'
I..,
.......'

a._I

I,t
i-a

-I

·::i-

b.
-..,
I"

R

H H

iH

Jd

'~':"'"

LILWL~r
L iL

= 0.0 to 0.8V
= 2.0 to 5.5V

[1

Figure 1. Equivalent input circuit of the 5082·7010 decoder.
Note: Display metal case is isolated from ground pin #6.

Figure 2. Equivalent circuit of the 5082·7010 as seen from
LED and decimal point drive lines.

-1.0

.

-0.9

"E -0.8 "•......
I

I-

iii

'"

-0.7

.

CJ
I-

rx
.c

-0.6

"'" -0.5

'"

.........

ir

.

I'

(;

g

I···.·

.......

-0.3

I

-0.1

ZS"C

.c'

"

CJ

.: -0.2

,

1\

'i'

..•.....

~ -0.4

.'.
Tc~

Vcc·5.5Y

,

:;.:. <'"

.

:

.

o
o

1.0

2.0

3.0

4.0

5.0

VI - LOGIC INPUT VOLTAGE - V

Figure3. Equivalent circuit of 5082·7011 plus/minus
sign. All resistors 345!1 typical. . Note: Display
metal case is isolated from ground pin #6.

r-

100

:

90

""

80

.1 .. '

f---

I

I-

iii

'"
"'"

.'

ir
~

CJ

'.

<. -1,00

70

~ -0.90

. J
II

.

:

'.

40

a''""

g

CJ

(;

30

I

-=

20

.,..,

10

o

-55 -40

-20
Tc

20

-

40

.'~

V

60

I

I: .

~ r-......

-0.80

~~ -0.70

(;

1
I •• I.:,

J.<

9 -0.60

/

.

'1<;,,\6.6'1
Ylc· Q.4Y.
-:-:"'

E
I

60

'

.

'

V,"·2.4V

50

.

-1.10

..•... .

Vee:=- 5.SV

CJ

I-

Figure 4. Input current as a function of input voltage,
each input.

..

.........

r-.......
"-.

'

.

K

..

I
~

..: -0.50

80

-0.40
-55 -40

95

CASE TEMPERATURE _ °C

-20

20

40

60

80

95

Tc - CASE TEMPERATURE - °C

Figure 5. Logic "H" input current as a function of case
temperature, each input.

Figure 6. Logic ilL" input current as a function of case
temperature, each input.

243

I

280

I

I

Vcc=5.5V

"E

240

/.

!----- ~C';;"~~~L 8 OISPLAYEO

I

iiia:

200

"::;
<.>

160

/

II:

i>l

~
I

~

120

/
40
0

1

3

2

.'

60r----f----+~-+---~r_-~--~~

·1
I

40rl-~----+_-~/~-~--+~:~

ReCOMMENOEr:,

I

I

I

I

4

5

20r-_-f____

a

5.5 6

~

~
1i

"
g
I

,£

__J __ _

': T

1

~_~~

2

__

3

""~
g

r\

'\

I

1.0

~

.1

Vee
4.2 '"
4 -

"'1

5.SV

1

I

I.

Q

.;

I

20

40

60 65

6

~

:

3

I
I
I

2

I
I
1

;
0

5.5

I

3.5

I
I

I
0

'\

I

NUMERAL 8 AND
DP DISPLAYED

I

I
I

.5

5

I'\.

5
I
w

I
1.15

I:

_L~~

6

>

1.5

__

Figure 8. Luminous intensity per LED (digit average)
as a function of LED supply voltage.

--

NUMERAL 8 AND DP OISPLA YEO

2.0

~

4

5.5

ffi

~...

-+_~~~I___R~~~i~E~~

VLEO - LED SUPPLY VOLTAGE - V

Vee '"-5.5V

i".
I \
I

i

GE

0~

3.0,----,----r---.---..----.

~

I

I
I

Figure 7. LED supply current as a function of
LED supply voltage.

:::-

I :

I

VLED - LED SUPPLY VOLTAGE - V

~

+-_-+__JIIj~1·1,..,.j

~c<;~lm

iOP~~rENG~_
I

..J
0

I

Te' ;I6'C ___

I

V

80

I I

f..--;.

80r---f---+--+----~~-i~~-T:-4

/

a:

r. .

100

I
I

j

I-

120

80

0

95100

0

20

40

60 65

80

95100

Tc - CASE TEMPERATURE _ °C

Tc - CASE TEMPERATURE _ °C

Figure 9. Maximum power derating as a function of
case temperatura.

Figure 10. LED voltage derating as a function of
case temperature.

4.0

6.0

,

">-

I-

0;

iii
I~

"'"0z

;;

1.0

'3
w

>
>=

~

""-

~

5.0

,
1-........
I

""

a:

>

I

I

I
w

4.0

g

3.0

"~
0

I

~

'" '.'\...

\

I

2.0

I
I

>

"-

0.4

,
,
I

:!l

"'-

"""" ~

I
Vee .. S.5V
I
NUMERAL 8 AND DP DISPLAYED

1.0

I
I
I
I

'"

0.3 '-_'-_.1-__-'-_-'-_..1-_......_-'-__-'
-60 -40 -20
20
40
60
80
lOa
Tc

-

TA - AMBIENT TEMPERATURE _

CASE TEMPERATURE _ °C

Figure 11. Relative luminous intensity as a function of case
temperature at fixed current level.

°c

Figure 12. LED voltage derating as a function ofambienttemperature.display soldered into P.C. board without heat sink.

244

SOlid state PIus/Minus Sign

(-

Truth Table

For display applications requ iring ± designation, the 5082·
70.11 solid state plus/minus sign is available. This display
module comes in the same package as the 50.82·70.10. nu·
meric indicator and is completely compatible with it. Plus
or minus information can be indicated by supplying voltage
to one (minus sign) or two (plus sign) input leads. A third
lead is provided for the ground connection. Luminous in·
tensity is controlled by changing the LED drive voltage.
Each LED has its own built·in 3450 (nominal) current
limiting resistor. Therefore, no external current limiting
is required for voltages at 5.5V or lower. Like the numeric
indicator, the·7O.11 plus/minus sign isTTL/DTL compatible.

",,+,,>
....
. , • Blank

......... ..
'. ,,1:.",

:H

. L

.L

VL = -0..5 to 1.DV
VH = 3.0. to 5.5V

Electrical/Optical Characteristics
Case Temperature, Tc"

ooc to 7DoC. unless otherwise specified

" L£D Supply Current ..

.TY~[U

.,Max.

Unit

106

.1:50
100

rnA.

70.
. 0..6
0..3

0..9
0.6

W

.'

115

80

j.tCd .

50.
655

Spectral Halfwidth

30'

Weight

4.9

Notes:

(

1. All typical values at TC = 25°C
2. At TC = 25°C

AbSOlute Maximum Ratings
Oescription

. .SymboI.,

Stonige Temperature, Ambient
Operating Tempe;.atur., Case

Plus. PlustMlnus Inwt
Potential to Ground

1&'
.. Tc.
..·-a5···· 5.5

VI.ED, .. '

V

Recommended Operating Conditions
Syrnt.l

Description

LED Supply Volt8ge,
DisPlay Off
LED Supply Voltage,
DI$pIayOn

VI.ED

Min.

.-0.5

Nopl.'

.0.' .'

Max.

uftit

1.0.

V

5.5

.V

..
.

"

VI-ED

·'3.0.

4.2,

245

nm
nm

gram

Applications
Decimal Point Limiting Resistor
The decimal point of the 5082-7010 display requires an external current limiting resistor, between pin 2 and ground.
Recommended resistor value is 2200, 1/4 watt.
Mounting
The 5082-7010 and 5082·7011 displays are packaged with
two rows of 4 contact pins each in a DIP configuration
with a row center line spacing of 0.890 inches.
Normal mounting is directly onto a printed circuit board.
If desired, these displays may be socket mounted using
contact strip connectors such as Augat's 325-AGI or AMP
583773-1 or 583774·1.
Heat Sink Operation
Optimum display case operating temperature for the 5082·
7010 and 7011 displays is Tc=OoC to 70°C as measured
on back surface. Maintaining the display case operating
temperature within this range may be achie.ved by mount-

ing the display on an appropriate heat sink or metal core
printed circuit board. Thermal conducting compound such
as Wakafield 120 or Dow Corning 340 can be used between
display and heat sink. See figure 10 for VLED derating vs.
display case temperature.
Operation Without Heat Sink
These displays may also be operated without the use of a
heat sink. The thermal resistance from case to ambient
for these displays when soldered into a printed circuit
board is nominally ()cA=30oCIW. See figure 12 for VLED
derating vs. ambient temperature.
aeaning
Post solder cleaning may be accomplished using water,
Freon/alcohol mixtures formulated for vapor cleaning processing (up to 2 minutes in vapors at boiling) or Freon/
alcohol mixtures formulated for room temperature cleaning.
Suggested solvents: Freon TF, Freon TE, Genesolv 01-15,
Genesolv 0 E-15.

246

5O~ ·1391 (4N51)
5082 ,1392 (4N52)
5082 ·1393 (4N53I
~2.1395(4Mi4)
TECHNICAL DATA MARCH 1960

Features
• PERFORMANCE GUARANTEED OVER
TEMPERATURE
• HERMETICITY GUARANTEED
• TXV SCREENING AVAILABLE
• GOLD PLATED LEADS
• HIGH TEMPERATURE STABILIZED
• NUMERIC
5082·7391 Right Hand D.P.
5082·7392 Len Hand D.P.
• HEXADECIMAL
5082·7395
• TTL COMPATIBLE
• DECODER/DRIVER WITH 5 BIT MEMORY
• 4 x 7 DOT MATRIX ARRAY
Shaped Character, Excellent Readability
• STANDARD DUAL·IN·LINE PACKAGE
• CATEGORIZED FOA LUMINOUS INTENSITY
Assures Uniformity of Light Output from
Unit to Unit within a Single Category

pattern, and four blanks in the invalid BCD states. The unit
employs a right-hand decimal point. Typical applications
include control systems, instrumentation, communication systems and transportation equipment.
The 5082-7392 is the same as the 5082-7391 except that
the decimal point is located on the left-hand side of the
digit.

Description

(

The HP 5082-7390 series solid state numeric and
hexadecimal indicators with on-board decoder/driver and
memory are hermetically tested 7.4mm (0.29 inch)
displays for use in military and aerospace applications.

The 5082-7395 hexadecimal indicator decodes positive
8421 logic inputs into 16 states, D-9and A-F. In placeofthe
decimal point an input is provided for blanking the display
(all LED's off). without losing the contents of the memory.
Applications include terminals and computer systems
using the base-16 character set.

The 5082-7391 numeric indicator decodes positive 8421
BCD logic inputs into characters 0-9, a " -" sign, a test

The 5082-7393 is a "±1." overrange display, including a
right hand decimal point.

package Dimensions*
I-l0.2MAX'j
1..(.400J

7395

-1

13.5

PIN
1
,2

3

'r-I...............r i
I I I 4.•

.·:r

r------I (.19)

5

6

7

8

REAR VIEW
LUMINOUS
INTENSITY
CATEGORY

81 DE VI EW

i .-1--0. ,0,

......-.4.....-,

1.'
1.06)

PIN 1 KEY
4

3

2

1

j ..

1.012 '.003)

2·~-1-1 ~
r

(.11)

(10 + 005)

4.3

(.17) ---

• JEDEC Registered Data.

Input 2
Input 4
Input a
Decimal
point
latch:
enable

Ground

Vee
Input 1

Input 2
InP\lt4
'Input
Blanking:
rontrot
LatOO
enable
,GfQund

a---

Vee
lnput 1

NOTES:
1. Dimensions in millimetresand (inches).

2. Unless otherwise specified, the tolerance
on all dimensions is ±.38mm (±.015")
3. Digit center line is ±.25mm (±.O''')
from package center line.
4. Lead material is gold plated copper
allov.

15.2

(.600)
DATE CODE

5
6
7
8

END VIEW

IT

4

FUNCTION
5082-7395
5OlI2·1391
AND 7392
HEXA·
DeCIMAL
NuMERIC

247

Absolute Maximum Ratings *
Min.

Max.

UnIt

.. ~ .

+125

.-55

+100
+7.0
+7.0

;·C·
,OC

Symbol .
. Ts·

Descriptlof!.
Storage temperatura, ambient
Operating temperature• .ambient 11.2)

.TA·

Supply voltage tl1

. ,"Icc

.,

, Voltage applied to input logic, dp and enable pins ...

. -()'5

-0.5
-0.5

VI;VDP,VIl

. Voltage applied to blanking Input (1)

Va

Maximum solder temperature at 1.59mm (;()~2inph)
below seating plane; t :\!b 5 seconds

V

V

Vee

V

260

°C

Recommended Operating Conditions*
'

Descttptlon

~,

Symbol
. Vee.

Supply Voltage
Operating temperature, ambient tIo2)

,

,\

,

Min.

Nom.

Max.

4.5

5.0

5.5

V

+1.00

"C

TA

-55

UnIt

tw

100

~

Time data must be held before poSitive transition
of enable line

tSllTlJP

50

nsec

Time data must be held after positive transition
of enable line

tROID

50

nsfW

Enanle Pulse Width .

Enable pulse rise time

200

trLR

nsec

Electrical/Optical Characteristics (TA = -55°C to +100"C, unless otherwise specified)
. DescriptIon

Symbol

Teet Conditions

MIn.

Typ.141

Max.

Unit

Supply Current

Icc

Vcc=5.5V (Numeral

112

170

mA

Power dissipation

PT

5 and dp lighted)

560

935

mW

Luminous intenSity per LED
(Digit average)'S,6)

Iv

Vcc=5.0V, TA=25"C

Logic low-level input voltage

VIL

Logie high-level Input voltage

VIH

Enable low-voltage; data being
entered
Enable high-voltage; data not
befng entered

VEIl

Blanking low-voltage; display
not blanked (1)

VOt

Blanking high-voltage; display
blanked (1)

VBH

VIlL

0.8

3.5
Vcc=S.SV, VSL...o.8V
Vcc=5.5V, V8lI=4.5V

logiC low-level input current

hL

Logic high-level input current
Enable low-level Input current

IIR

Peak wavelength
Dominant Wavelength

IS)

lEN
APEAK
Ad

V
V

0.8

IpL.

Enable high-level input current

0.8

2.0

ISH

V
V

Vcc=4.5V

Blanking lOW-level input current i1I

IBt

ped

85

2.0

Blanking high-level input current

(7)

40

V
V

p.A

50
1.0

mA

Vcc=5.5V, VIL=O.4V

-1.6

rnA

Vcc=O.5V. VIH=2.4V
Vcc=5.5V, Vu=O.4V

+100
-1.6

mA

+130

V.cc=S.5V. Vf-H=2.4V

TA =25"C
TA =25"C

nm

640

nm
gm
5x 10-1

Leak Rate

p.A

655

1.0

Weight"

pA

cc/sec

Notes: 1. Nominal thermal resistance of a display mounted in a socket which is soldered into a printed circuit board: fiJJA=5a'OIW;
fiJJc=15° CIW. 2. @cA of a mounted display should not exceed 35"CIW foroperation up to T A=+100"C. 3. Voltage values are with respect to
device ground, pin 6. 4. All typical values at Vcc=5.0 Volts, T A=25° C. 5. These displays are categorized for luminous intensity with the intensity category designated by a letter located on the back of the display contiguous with the Hewlett-Packard logo marking. 6. The
luminous intenSity at a specific ambient ~mperature, Iv(TA), may be calculated from this relationship: Iv(TA)=lv("o C) (.985) IT.-25"CI
7. Applies only to 7395. 8. The dominant wavelength, A", is derived from the CIE chromaticity diagram and represents the single wavelength which defines the color of the device.
"JEDEC Registered Data.

""Non Registered Data.

248

(

. , •.

tsETUP-j.---i-o---<.f-tHOLD

. TRU

T""",,

DATA INPUT
(LOW' LEVEL DATAl

()

UV

ye'

DATA INPUT
(HIGH LEVEL DATAl

,

:.~',~

:,,,',

.
'.

1.

,.",

Ii

",
··f

:L'

,

f.ol

,lj

,"!I

.:If;•.

",I.."

.3

II'

'.Ii

Ji.":" ::'::W': >£.
..
':,1- .; :iI:., ''\: ,:
."

I,.

:i)

II

1

",

Figure 1. Timing Diagram of 5082-7390
Series Logic.

H
Ii

"

'11

Pin.

~~

Vee

.I.:..' " Ii

H:.

L.

Ii.

H

I.'

.'11

-l.

ENABLE

,H

H'

Ii

LOGIC

1.1

H

H"

tlllANKI

,If

c

(BLANK)

.[1

II

F
I··

(BLANK'

II

(BLANK)

O~C(MAlPT.l2l·I-'-:ON=..., _ _ _ _ _...,V.;:."":!:......7"Ol_~

INPUT

OFF

DpI21 4

VOP -H

BLANKING I3 )
CONTROL

4

6~

GROUND

Figure 2. Block Dlagrem of 5082-7390
Series Logic.

Notes:
1. H = Logic High; L = Logic Low. With the enable input at logic high
changes in BCD Input logic levels or D.P. Input have no effect upon
display memory, displayed character, or D.P.
2. The decimal point input, DP, pertains only to the 5082-7391 and
5082-7392 displays.
3. The blanking control input, B, pertains only to the 5082-7395
hexadecimal display. Blanking Input has no effect upon display
memory.

(

,

5

-1.8
E -1 .

~c·26.cl_
Vcc·S.OV

I

I

Vcc"'6.OV

"'·~C

1/

2

./

1

0

..".

V

/

iii

I

§u -" 2
~

-1.0

~

-.S

~
I

w

V

Figure 3. Typical Blanking Control
Current ¥S. Voltage for 50827395.

•

-1.4

II:

'/

VB - BLANKING VOLTAGE - V

,

I-

00(

...... .....

-A

-.2
00
TA -AMBIENT'rEMPERATURE _oC

Figure 4. Typical Blanking Control
Input Current ¥S. Ambient
Tempereture for 5082-7395.

'JEDEC Registered Data.

249

\
1.0

2.0

3.0

4.0

5.0

V E - LATCH ENABLE VOLTAGE - V

Figure 5. Typical Latch Enable Input
Current ¥S~ Voltage.

IT ->S'C

1I -1.4
~

~ I-

I

e-

-1.6

~

1.0

I

-1.8

Vee ·S.OV

-

-1.2

SI

'1\

I -.6
~

2

00

~

r-

V'L .. O.8V

9 -8 I'\'

i\

VE -

err\.
0.5

1.0

~~

20

i",0;~

14

~~

10

~ ~

8

f- c-~ 18
... !3 f£ (J 16

a

~9
_w
" _!:.
'.0

V1N - LOGIC VOLTAGE

5.0

o

-55

-v

Figure 6. Typical Logic and Decimal
Point Input Current vs.
Voltage.

~

v." -2.4V

/

4

-20
0
20
40
60
80
TA - AMBIENT TEMPERATURE - °c

,00

Figure 7. Typical Logic and Enable
Low Input Current VB.
Ambient Temperature.

o

/

/
/

6

2
3.0

-

/

/

Vee !s.ov

i:t: 12

V

2.0

I

I

~

lice -s.ov

'" -1.0
G

-.'

-

26

...Z "I 2.22

--.

/
./

20
40
60
-55 -40
-20
TA - AMBIENT TEMPERATURE -

80

100

°c

Figure 8. Typical Logic and Enable
High Input Current vs.
Ambient Temperature.

operational Considerations
These displays may be mounted by soldering directly to a
printed circuit board or inserted into a socket. The leadto-lead pin spacing is 2.54mm (0.100 inch) and the lead
row spacing is 15.24mm (0.600 inch). These displays may
be end stacked with 2.54mm (0.100 inch) spacing between
outside pins of adjacent displays. Sockets such as Augat
324-AG20 (3 digits) or Augat 508-AG80 (one digit, right
angle mounting) may be used.

ELECTRICAL
The 5082-7390 series devices use a modified 4 x 7 dot
matrix of light emitting diodes (LED's) to display
decimal/hexadecimal numeric information. The LED's are
driven by constant current drivers. BCD information is
accepted by the display memory when the enable line is at
logic low and the data is latched when the enable is at
logic high. To avoid the latching of erroneous information,
the enable pulse rise time should not exceed 200
nanoseconds. Using the enable pulse width and data
setup and hold times listed in the Recommended
Operating Conditions allows data to be clocked into an
array of displays at a 6.7MHz rate.

The primary thermal path for power dissipation is through
the device leads. Therefore, to insure reliable operation up
to an ambient temperature of +100°C, it is important to
maintain a case-to-ambient thermal resistance of less
than 35°C/watt as measured on top of display pin 3.
Post solder cleaning may be accomplished using water,
Freon/alcohol mixtures formulated for vapor cleaning
processing (up to 2 minutes in vapors at boiling) or
Freon/alcohol mixtures formulated for room temperature
cleaning. Suggested solvents: Freon TF, Freon TE,
Genesolv 01-15, Genesolv OE-15.

The blanking control input on the 5082-7395 display
blanks (turns off) the displayed hexadecimal information
without disturbing the contents of display memory. The
display is blanked at a minimum threshold level of 3.5
volts. This may be easily achieved by using an open
collector TTL gate and a pull-up resistor. For example,
(1/6) 7416 hexinverter buffer/driver and a 120 ohm pull-up
resistor will provide sufficient drive to blank eight
displays. The size of the blanking pull-up resistor may be
calculated from the following formula, where N is the
number of digits:
Rbl• nk

= (Vee -

PRECONDITIONING
5082-7390 series displays are 100% preconditioned by 24
hour storage at 125° C.
CONTRAST ENHANCEMENT

3.5V)/[N (1.0mA)]

The 5082-7390 displays have been designed to provide the
maximum posible ON/OFF contrast when placed behind
an appropriate contrast enhancement filter. Some
suggested filters are Panelgraphic Ruby Red 60 and Dark
Red 63, SGL Homalite H100-1605, 3M Light Control Film
and Polaroid HRCP Red Circular Polarizing Filter. For
further information see Hewlett-Packard Application Note
964.

The decimal point input is active low true and this data is
latched into the display memory in the same fashion as is
the BCD data. The decimal point LED is driven by the onboard IC.
MECHANICAL
5082-7390 series displays are hermetically tested for use
in environments which require a high reliability device.
These displays are designed and tested to meet a helium
leak rate of 5 x 10.7 cc/sec and a standard dye penetrant
gross leak test.

• JEDEC Registered Data.

250

High Reliability Test Program

Standard Product With TXV Screening
PREFERRED PART NUMBER SYSTEM
4N51
4N51TXV
4N52
4N52TXV
4N54
4N54TXV
4N53
4N53TXV
ALTERNATE PART NUMBER SYSTEM
5082-7391
TXV-7391
5082-7392
TXV-7392
5082-7395
TXV-7395
5082-7393
TXV-7393

Hewlett-Packard provides standard high reliability test
programs, patterned after MIL-M-38510 in order to
facilitate the use of HP products in military programs.
HP offers two levels of high reliability testing:
The TXV prefix indentifies a part which has been
preconditioned and screened per Table 1.
The TXV8 prefix identifies a part which has been preconditioned and screened per Table 1, and comes from
a lot which has been subjected to the Group 8 tests
described in Table 2.
Table 1. TXV Preconditioning and Screening -

'ex~rtaiI;;n or Test : ..

"C,

; ,'.
12ilnternaf Vls~1 In$pection

i~'~llCtrli:~li~st:1Y!1cc,

fiL.

.

:.

IB~; I~L"tR.ll~ h".

3. High Temperature StoragE!
4..' 'fEtmpel1ltureCycling
5.;,A.cceleration
6.fi!!liurn Leak.T~st
7. Gross Leak Test
8.EleQlrical Test: Same lIS Step 2
.9~ ,Burn-in

,

4N51TXVB
4N52TXVB
4N54TXVB
4N53TXVB
TXVB-7391
TXVB-7392
TXVB-7395
TXVB-7393

100%.

MIL-STD-883
Methods
HP Procedure
A-5956-7572-52

CondltlollS

Per Electrical/Optical Characterstics.
125" C, 168 hours.
-65·C to +125°C, 10 cycles.
2,000 G, Y1 orientation.
Condition A
Condition 0

1008
1010
2001
1014
1014
1015

10. 'Electrical Test as in Step 2
11; Sample Electrical Test Over Temperature:
lc~t'~tBt~ IBH' In" fBt, Ill" JfH
12. Sample Electrical Test Over Temperature
Icc. 1st, InB, IEL~ tEll, hLI lUI
13. Extllmal Visual

Plus Group B

T A=1000C, 1=168 hours, at Vcc='5.0V and cycling through
logic at 1 character per sec.
Per Electrical Characteristics, TA = -55· C, L TPD = 7
Per Electrical Characteristics, TA = +100° C, LTPD = 7

2009

Table 2. Group B.

.

MIL·STD-883

Examination or Test
Subgroup 1
Physical Dimensions
Subgroup 2
Soldefabllity
Temperature Cycling
Th~mal Shoc,k
Henmetic Seal'
Moisture Resistance
End Points: Electrical Test
Subgroup 3
Shock - Non-operating
Vibration Variable Freql.lency
Constant Acceleration
End Points: Electrical Test
Subgroup 4
Terminat Strength
End Points: Hermetic Seal
Subgroup 5
Salt Atmosphere
Subgroup 6

HighT~perature Life

, End:Points: Electrical Test
SubgrOUp,.7
' , . " .'
Steady $tate Operating Life
 Vj, YJ..
Non-operating.
2.000 G, Y 1 orientation.
Same as Step 2, Table 1.

2004
1014

Test Condition 82.
Condition A and Condition 0

1009

Test Condition A

15

"

,.'

15

15

15
X-7
,',1008

T,=125°C, non-operating, t=1000 hours.
Seme as Step 2, Table 1.
X=5

1005

T.,=1000C, 1'=1000 hours, at Vcc=5.0vand cycling through logic at
1 character per second.
Seme as Step 2, Table 1.

'JEDEC Registered Data.

251

Solid State Over Range Character
For display applications requiring a ±, 1, or decimal point designation, the 5082-7393 over range character is available.This
display module comes in the same package as the 5082-7390 series numeric indicator and is completely compatible with it.

package Dimensions *

,I

7.4

r---------- ----------,
#1

V(I;.

M~S

NUMf-RAt..ON€

I
I
I
I
I

~

d..

4.8

~SeAT'NG

1.29) (.,91

Ll

PLANE

0.3 'to.08 TYP.

(.012'.0031

I~~,-I
.rl-l1.17)r-

FRONT

+

4..

;j

-

-- -,,1

-

-

-

-;..

SIDE
5

6

7

8
1.5

.1 3.'

,.4--1--.,

(.06'

....-t.-,..,-.,.If

Figure 9. Typical Driving Circuit.

T'lt•

DATE CODE

l.3TYP'~
I f-~- II o.s,o.oIlTVP.
(O!." - i
'1 t-' 1.020 '.003'

PINt Kev

TRUTH TABLE

2.5 ±o.13 TYP.
1.10 ;.0051

REAR

PIN

FUNCTION

NOTEs:

2

" DrNlEN$IONS IN Mll..lIMETRES AND (INCHES).

a

Numeral One
Numeral One

1-

-1

Plus

2. UNLESS OTHERWISE sPECIFIED, THE TOLERANCE

Decimal Point
Blank

DP

ON ALL OIMfNSIONS IS ~.38 MM {t ,015 tNCHES ••

PIN

CHARACTER

END

Open
Open

NOTES:

MinuS/l"'lus

1

2,3

4

8

H
L
X
X

X

X
X
X

H
H.
X

H

X

L

L

L

L~,

X
H
X

",.,,'

L: line switching transistor in Figure 9 cutoff.
H: line switching transistor in Figure 9 saturated.
X: 'Oon't care'

Electrical/Optical Characteristics *
5082-7393

(TA = -55°C to +100°C, Unless Otherwise Specified)
SYMBOL

DESCRIPTION

TEST CONDITIONS

MIN

TVP

1.6

MAX

UNIT
V'

Forward Voltage per LEO

VF

IF~10mA

Power dissipation

PT

'F;10mA
all diodes lit

Luminous Intensity per LEO (digit average)

Iv

'F

Peak wavelength

Apeak

TC:: 25°C

655

Itc;cl·
tim',

Ad

Tc~25OC

640
1.0

gm

~ 6mA

Weight * *

Recommended Operating
Conditions *

40

280
85

Vee

4.5

5.0
5.0

5.5

for recommended resistor values.

"Non Registered Data.

mW·' ,

,

nm

DESCRIPTION
SYMBOL MIN_ MAX. UNIT
Stordge temperature, ambient
-65 +125 ,,·C
TS
Operating temperature, ambient
~C.
-55 +100
TA
10'/ rnA
Forward current, each LED
IF
Reverse voltage, each LEO
VR
4·,' .V',

V

Forward c;;:unent. each LEO
10
rnA
IF
NOTE:
LED current must be externally limited. Refer to Figure 9

'JEDEC Registered Data.

320

Absolute Maximum Ratings *

SYMBOL MIN NOM MAX UNIT
LE 0 supplV yoltage

'.
P"

Tc ~ 25°C

Dominant Wavelength

2.0

252

FA'3

HEW L.ETT

a:~. PACKARD

Features
• INTEGRATED SHIFT REGISTERS WITH
CONSTANT CURRENT DRIVERS
• CERAMIC 7.62 mm (.3 in.) DIP
Integral Red Glass Contrast Filter
• WIDE VIEWING ANGLE
• END STACKABLE 4 CHARACTER PACKAGE
• PIN ECONOMY
12 Pins for 4 Characters
• TTL COMPATIBLE
• 5x7 LED MATRIX DISPLAYS FULL ASCII
CODE
• RUGGED, LONG OPERATING LIFE
• CATEGORIZED FOR LUMINOUS INTENSITY
Assures Ease of Package to
F!iJckage Brightness Matching

Description
The HP HDSP-2000 display is a 3.8mm (0.15 inch)'5x71.~D array for display of alphanumeric information. The device is
available in 4 character clusters and is packaged in a 12-pin dual-in-line type package. An on-board SIPO (serial-inparallel-out) 7 bit shift register associated with each digit controls constant current LED row drivers. Full character display
is achieved by external column strobing. The constant current LED drivers are externally programmable and typically
capable of sinking 13.5mA peak per diode. Applications include interactive I/O terminals, pOint of sale equipment, portable
telecommunications gear, and hand held equipment requiring alphanumeric displays.

(

Package Dimensions
I~l MAX'.=-1.

I

SfE~OTE~

r-,

I

I

r'

I

I

r-,
I

I

PIN
1
2
3
4
5
6

r-,

I

I

,+H+j+t+H+:
L
L
~

/

'IN 1 MARKED IW
DOT ON SACK Of

~

L_~

L_~

~oo

FUNCTION
COLUMN 1
COLUMN 2
COLUMN 3
COLUMN 4
COLUMNS

PIN
7

••
"

INT. CONNECT"

FUNCTION
DATA OUT

10

V.
Vee
CLOCK

12

DATA IN

GROUND

NOT OONNe<:T OR USE

4.44:!';.13

t.175 ±: ..005'--

PACKAGE.
NOTES,

.

1. OfM'ENSt9NS iN ~ (incb_,).,

2. IINLE$$OTH£RwlSI! 8I'EClfIEO THE

TOLERANCE ON All DIMeNSIONS
lh.38 rnm (t .016""
3. lEAD MATERIAl,S GOLD l'lATEP
COPPER ALLOY. .
4. CHARACTERS ARE CENTERro

WITH RESPECT TO lEAOS \\'ITIIIN
~.13mtn

1.27 -....
{.II'"

253

hJ)06").

Absolute Maximum Ratings
Supply Voltage Vee to Ground .......... -0.5V to 6.0V
Inputs, Data Out and VB ................ -0.5V to Vee
Column Input Voltage, VeOL .......... -0.5V to +6.0V
Free Air Operating Temperature
Range, TP) ........................ -20"C to +70"C

Storage Temperature Range, Ts ..... -55°C to +100°C
Maximum Allowable Package Dissipation
atTA =25°CI I ,2"1 ••••••••••••••••••••••••• 1.70 Watts
Maximum Solder Temperature 1.59mm (.063")
Below Seating Plane t<5 secs ............... 260°C

Recommended operating Conditions
Parameter
Supply Voltage
Data Out Current. Low State
Data Out Current. HighS!ate
COlumn Input Voltage. Column On
Setup Time
Hold Time
Width of Clock
Clock Frequency
Clock Transition Time
Free Air Operating Temperature Range

Symbol

Min.

Nom.

Max.

Vee

4.75

5.0

5.25
1.6
-0.5

10L

10"

fdock

2.6
70
30
75
0

ImL
TA

-20

VeoL
tsctup

thold
tw(C)".-kt

Units
V
mA
rnA

Vc~

V

45

ns

0

ns
ns
MHz
ns

3
200
70

°C

Electrical Characteristics Over Operating Temperature Range
(Unless otherwise specified.)
Symbol

Description

Icc

Supply Current

Typ.'

Max.

Units

VB = OAV

45

60

mA

2.4V

73

95

mA

1.5

rnA

Min.

Test Conditions
Vee = 5.25V
Vnocl< = VOMA = 2AV
All SR Stages =
Logical 1

Va

Column Current al any Column Input

Icot.

VCC= 5.25V
Veol.;: 3.5V

VB=O.4V

Column Current at any Column Input

leOI.

All SR Stages'" Logical 1

Ve"'2.4V

t,PCAK

Vn' - S.OV. Veo/. -3.5V
T, ;:2S·C(~)
Ve=2.4V

Peak Luminous Intensity per LED(3.7)
(Character Average)
Ve. Clock or Data Input ThreshOld High

Ve. Clock or Data Input Threshold Low
Ve. Clock
Input Current Logical 1
Data In
VB,Clock
Input Current Logical 0
Data In

""

Vec '" 5.25V.VIH = 2.4V

IlL
IlL
VOl!
VOl.

Vee

= S.2SV, VII.

~

105

20
10

2.4

rnA
!,cd

200

2.0

OAV

Vee = 4.75V, lOll '" -0.5mA. VUH = OV
Vee - 4.75V. lot - I.SmA. Vco!. ;: OV
Vee '" 5.0V, V~OL '" 2.SV.
15 LEOs on per character. V. ~ 2.4V

410

0.8
80
40

V
V

-500

·800

·250
3.4
0.2

-400

!'A
p.A
p.A
p.A

0.4

V
V

0.66

W

APEAK

655

Ad

639

nm
nm

Power Dissipation Per Package"

=

Vee = Vco!. = 4·.7SV

1m

Data Out Voltage

Peak Wavelength
Dominant Wavl1length<'i

VIH
VIt.

335

Po

=

, All typical values specified at Vee 5.0V and T A 25'C unless otherwise noted.
"Power dissipation per package with 4 characters illuminated.
NOTES:

1. Maximum absolute dissipation is with the device in a socket having a thermal resistance from pins to ambient of 35°C/watt.
2. The device should be derated linearly above 25'C at 16mWI"C (see Electrical Description on page 3).
3. The characters are categorized for Luminous IntenSity with the intenSity category deSignated by a letter code on the bottom of the
package.
4. T) refers to the initial case temperature of the device,immediately prior to the light measurement.
5. Dominant wavelength Ad, is derived from the CtE chromaticity diagram, and represents the Single wavelength which defines the color
of the device.
6. Maximum allowable dissipation is derived from Vee = VB = VeOL = 5.25 Volts, 20 LEDs on per character.
7. The luminous stearance of the LED may be calculated using the following relationships:
L, (Lux) = Iv (Candela)/A (Metre)'
Lv (Footlamberts) = "I, (Candela)/A (Foot)'
A = 5.3 x 10-' M' = 5.8 x 10-' (Foot)'

254

Post solder cleaning may be accomplished using water,
Freon/alcohol mixtures formulated for vapor cleaning
processing (up to 2 minutes in vapors at bOiling) or
Freon/alcohol mixtures formulated for room temperature
cleaning. Suggested solvents: Freon TF, Freon TE,
Genesolv DI-15, Genesolv DE-15.

Electrical Description
·ConcRtiori MIn.

Parameter
fCiock
CLOCK Rate .
tt'LI!. tl'llL
Propagation
delay CLOCK
to DATA OUT

Typ.

-~
3

Unite

125

ns

CL '" 15pF
RI..=2.4I(fi

Figure 1. Switching. Characteristics. (Vee
TA = _20°C to +70" C)

The HDSP-2000 four character alphanumeric display has
been designed to allow the user maximum flexibility in
interface electronics design. Each four character display
module features Data In and Data Out terminals arrayed
for easy PC board interconnection such that display
strings of up to 80 digits may be driven from a single
character generator. Data Out represents the output of the
7th bit of digit number 4 shift register. Shift register
clocking occurs on the high to low transition of the Clock
input. The like columns of each character in a display
cluster are tied to a single pin. Figure 5 is the block
diagram for the HDSP-2000. High true data in the shift
register enables the output current mirror driver stage
associated with each row of LEOs in the 5x7 diode array.

MHz

=SV.

Mechanical and
Thermal Considerations

The reference current for the current mirror is generated
from the output voltage of the VB input buffer applied
across the resistor R. The TTL compatible VB input may
either be tied to Vee for maximum display intensity or pulse
width modulated to achieve intensity control and
reduction in pow!!r consumption.

The HDSP-2000 is available in a standard 121ead ceramicglass dual in-line package. Itis designed for plugging into
DIP sockets or soldering into PC boards. The packages
may be horizontally or vertically stacked for character
arrays of any desired size.

The normal mode of operation is depicted in the block
diagram of Figure S. In this circuit. binary input data for
digit 4, column 1 is decoded by the 7 line output ROM and
then loaded into the 7 on board shift ·register locations 1
through 7 through a parallel-in-serial-out shift register.
Column 1 datafordigits3.2and1 iss:milarlydecodedand
shifted into the display shift register locations. The
column 1 input is now enabled for an appropriate period of
time, T. A similar process is repeated for columns 2. 3. 4
and 5. If the time necessary to decode and load data into
the shift register is t. then with 5 columns, each column of
the display is operating at a duty factor of:

The -2000 can be operated over a wide range of
temperature and supply voltages. Full power operation at
TA = 25°C (Vee = VB = VeOL = 5.25V) is possible by
providing a total thermal resistance from the seating plane
of the pins to ambient of 35°C/w/cluster maximum. For
operation above T A = 25° C, the maximum device
dissipation should be derated above 25°C at 1SmWfOC
(see Figure 2). Power derating can be achieved by either
decreasing VeoL or decreasing the average drive current
through pulse width modulation of VB.
The -2000 display has an integral contrast enhancement
filter in the glass lens. Additional front panel contrast
filters may by desirable in most actual display applications. Some suggested filters are Panelgraphic Ruby Red
SO, SGL Homalite H100-1605 and Plexiglass 2423.
Hewlett-Packard Application Note 964 treats this subject
in greater detail.

0

2.0

"-

i!

"'~

1.5

f\

!!l

!1
~

1.0

t--"

mI-. 11

~

RECOIIMENOEO
OPERATING
IISGION '--:-

" ~"

~

S
w

T
D.F. = 5It+T)
The time frame, t + T, allotted to each column of the
display is generally chosen to provide the maximum duty
factor consistent with the minimum refresh rate necessary

0.5

a:

i7
0

-20

+20

+40

+60

+80

+100

TA - AMBIENT TEMPERATURE - °C

Figure 2. Maximum Allowable Power
Dissipation VB. Temperature.

-20

0

+20

+40

+60

+80

+100

TA - AMBIENT TEMPERATURE - °C

Figure 3. Relative Luminous Intensity
VB. Temperature.

255

,.....,..

1.0

2.0

3.0

4.0

6.0

&.0

VCOL -COLUMN VOLTAGE-V

Figure 4. Peak Column Currant
VB. Column VoHage.

7.0

to achieve a flicker free display. For most strobed display
systems. each columr1 of the display should be refreshed
(turned on) at a minimum rate of 1000times per second.

If the device Is operated at 3.0 MHz clock rate maximum. It
is possible to maintain t -< T. For short display strings. the
duty factor will then approach 20%. For longer display
strings operation at column duty factors of less than 10%
will still provide adequate display intensity in most
applications. For further applications information. refer to
HP Application Note 966 and Application Note 1001.

With 5 columns to be addressed. this refresh rate then
gives a value for the time t + T of:
1/[5 x (100)] = 2 msec.

:=

_-'N

DATA

_

Vee

CLOCK

DATA
OUT _

-

-

I
I

~~
CLOCK
'IN

REstTiN

C1.Qa(.1N

+7

,

t!NCO\.lNTER
ClOCK iii" No. Of DtGl'fS
tNDISPLAV
IN

OUT

INTER:

COLS

C OL.

Figure S. Block Diagram 01 the HDSP-200o..

CONNECTION
(DO NOT CONNECT)

I.

CLOCt(1N
STAJIT O.lSPt.AYTtMEfn

OUT

I"

~'TRtNG

COUNTER

OUTr

IIII
0--

ASCII,~
IN

I

R£f:AESH

DATA~

MEMORY

0-0--

~

-++
•
..!..

-+.,

l

COLUMN SElEcT
COUNTER

-.

OUTPUTS

f:~

IIIIII

CLOCl<:tN

}

,.aor·

_"DATAIN
COLIlMII
COLIlMII

OATA
OUT

AAftAU.ElIN

N.tNE

SEU;CT

fCOLlJMNI DATA IN
CHARACTER GENERAToR

S£RfALOUT

SHIFT
REQtsnR

I COLUM~NASLE!

Q

I

I

DATA

CI.OCl(

IN

IN

COllJMN seLECT

TRANSISTORS

- .r
DATA

\

OUT

tNPVT~

I I I I I
Figure 6. Block Diagram of a Basic Display System.

256

'15=.

ENA8L!~

YELLOW FOUR
CHARACTER SOLID HDSp·2001
STATE ALPHANUMERIC
DISPLAY

· · · ......wtJiTT
'PACk'ARD

TECHNICAL DATA MARCH 1980

Features
• INTEGRATED SHIFT REGISTERS WITH
CONSTANT CURRENT DRIVERS
• CERAMIC 7.62 mm (.3 in.) DIP
• WIDE VIEWING ANGLE
• END STACKABLE 4 CHARACTER PACKAGE
• PIN ECONOMY
12 Pins for 4 Characters
• TTL COMPATIBLE
• 5x7 LED MATRIX DISPLAYS FULL ASCII
CODE
• RUGGED, LONG OPERATING LIFE
• CATEGORIZED FOR LUMINOUS INTENSITY
AND COLOR
Assures Ease of Package to
Package Brightness and Color Matching

Description
The HP HDSP-2001 display is a 3.8mm (0.15 inch)5x7 yellow LED array for display of alphanumeric information. The
device is available in 4 character clusters and is packaged in a 12-pin dual-in-line type package. An on-board SIPO (serialin-parallel-out) 7-bit shift register associated with each digit controls constant current LED row drivers. Full character
display is achieved by external column strobing. The constant current LED drivers are externally' programmable and
typically capable of sinking 13.5mA peak per diode. Applications include interactive 1/0 terminals, avionics, portable
telecommunications gear, and hand held equipment requiring alphanumeric displays.

(

package Dimensions
rpjN~

1
2
3
4
5
6

t

IT
1.25

.~.--

FUNCTION
COLUMN 1
COLUMN 2
COLUMN 3
COLUMN 4
COLUMN 5
INT. CONNECT-

~~~
7
CATAOUT
8

• "
"

Vr~

10

12

CLOCK
GROUND
DATA IN

·00 NOT CONNECT OR USE

Nons:
1. DIMENSIONS ,N nun {inch..}.
2. UNlESS OTHERWISE SPECIFIEO THE
TOLERANCE ON ALL DIMENSIONS
tS 1.38 mm (!.01S"'j
3. LEAD MATER1AL IS GOLD pLATEO

-COPPER ALLOY.
4. CHARACTERS ARE CENTERED

WJTH RESPECT "'TO l.EADS WITHIN

I

±.13rnm {:dJ05"L

,l.$4t.13TVP.

~' (.101) ~ .006}
, NQNACCOM.

257

Absolute Maximum Ratings
Supply Voltage Vee to Ground .......... -0.5V to 6.0V
Inputs, Data Out and VB
... -0.5V to Vc<
Column Input Voltage, VeO!.
-0.5V to +6.0V
Free Air Operating Temperature
Range,

Storage Temperature Range, Ts ..... -55°C to +100°C
Maximum Allowable Package Dissipation
atT,,=25°C""'0I ......................... 1.70 Watts
Maximum Solder Temperature 1.59mm (.063")
Below Seating Plane t<5 secs ............... 260° C

T.r' ..... .

Recommended operating Conditions
.... Parlll)'Mter
. , Supply Voltage

.

01,111,1 Oat. Current, Lell.k Luminous IntenSity perLEO!3.71
(Character Average)
Va, Clock or Data. Input Threshold High
Va, Clock or Data Input Threshold Low
VB, Clock
Input Cllrrent Logical 1

.

"lnput:Current logical 0

.,

Data In
Va,Clock
Data In

O~t~~~tV~ft1ge .•

f~PI \l

VllI
VII
1111

I".
I"
Vor

"f>l*Ik Wavelength
Dominant wawlength'"

Vce = 5.25V
VCIOlf....
V"\I·\" 2AV
All SR Stages
Logical 1

60

rnA

V"

2AV

73

95

rnA

1.5

rnA

At! SR Stages'" Logical 1

V8=2.4V

.

S.OV. V"", .~ 3.SV
25°C'"
V8~2.4V

=

V..,,,

V"

~

~

335

SOO

PI)

V"

~.

2.4V

5.25V, VI!. = O.4V

OV
Vn = 4.75V, 1,,,, = -a.SmA, V( oj
V( (' = 4.75V, 10 , = 1,6mA, V, ,,' "" OV
Vn ,5.0V, VC(l!. 2.75V,
15 LEOs on per character, V. = 2.4V

)\1'1'.\'"

AJ

410

750

2.4

20
10
-500
-250
3.4

0.2

rnA
/Jcd

2.0

4.7SV

Vee '" 5.25V, Vn,

Units

45

V8~OAV

T,

Max.

0.4V.

Vce = S.25V
VeOl" 3.5V

V(,e'

Typ:

VI<

IHI

V(H-I

f>oWerOissipation Per PaCkage"

Min.

Test Conditions

0.8
80
40

-800
-400
0.4

V
V
I'A

v. A
JJ.A
/J A
V
V

0.68

W

583
585

nm
nm

• All typical values specified at Vee = S.OV and T A = 25°C unless otherwise noted.
uPower dissipation per package with 4 characters illuminated.
NOTES:

1. Maximum absolute dissipation is with the device in a socket having a thermal resistance from pins to ambient of 35°C/wattldevice.
2. The device shuuld be derated linearly above 25°C at 16mWrC (see Electrical DeSCription on page 3).
3. The chao-acters are categorized for Luminous Intensity and color with the category deSignated by a letter code on the bottom of the
package.
4 TI refers to the initial case temperature of the device immedIately prior to the light measurement
5. Dominant wavelength
is derived from the GIE chromaticity diagram, and represents the single wavelength which defines the color
of the device.
6. Maximum allowable dissipation is derived from V( ( "" VH "'" V( 01 = 5.25 Volts, 20 LEOs on per character.
7. The luminous stearance of the LED may be. calculated uSing the following relationships:

"d.

L, (Lux) = h (Candela)/A (Metre)'
L, (Footlamberts) ~ ".1, (Candela)/A (Foot)'
A = 8.02 x 10.8 11.1 2 = 8.64 x 10.7 (Foot)2

258

Post solder cleaning may be accomplished using water.
Freon/alcohol mixtures formulated for vapor cleaning
processing (up to 2 minutes in vapors at boiling) or
Freon/alcohol mixtures formulated for room temperature
cleaning. Suggested solvents: Freon TF. Freon TE.
Genesolv DI-15. Genesolv DE-15.

Electrical Description

i.

The HDSP-2001 four character alphanumeric display has
been designed to allow the user maximum flexibility in
interface electronics design. Each four character display
module features Data In and Data Out terminals arrayed
for easy PC board interconnection such that display
strings of up to 80 digits may be driven from a single
character generator. Data Out represents the output of the
7th bit of digit number 4 shift register. Shift register
clocking occurs on the high to low transition of the Clock
input. The like columns of each character in a display
cluster are tied to a single pin. Figure 5 is the block
diagram for the HDSP-2001. High true data in the shift
register enables the output current mirror driver stage
associated with each row of LEDs in the 5x7 diode array.

Figure 1. Switching Characteristics. (Vee = 5V,
TA = -20·C to +70·C)

Mechanical and
Thermal Considerations

The reference current for the current mirror is generated
from the output voltage of the VB input buffer applied
across the resistor R. The TTL compatible VB input may
either be tied to Vee for maximum display intensity or pulse
width modulated. to achieve intensity control and
reduction in power consumption.

The HDSP-2001 is available in a standard 121ead ceramicglass dual in-line package. It is designed for plugging into
DIP sockets or soldering into PC boards. The packages
may be horizontally or vertically stacked for character
arrays of any desired size.

The normal mode of operation is depicted in the block
diagram of Figure 6. In this circuit, binary input data for
digit 4, column 1 is decoded by the 7 line output ROM and
then loaded into the 7 on board shift register locations 1
through 7 through a parallel-in-serial-out shift register.
Column 1 data fordigits3. 2and 1 is similarly decoded and
shifted into the display shift register locations. The
column 1 input is now enabled for an appropriate period of
time, T. A similar process is repeated for columns 2. 3. 4
and 5. If the time necessary to decode and load data into
the shift register is t, then with 5 columns, each column of
the display is operating at a duty factor of:

The HDSP-2001 can be operated over a wide range of
temperature and supply voltages. Full power operation at
TA = 25°C (Vee = VB = VeOL = 5.25V) is possible by
providing a total thermal resistance from the seating plane
of the pins to ambient of 35°C/W/device maximum. For
operation above TA = 25°C, the maximum device
dissipation should be derated above 25°C at 16mWrC
(see Figure 2). Power derating can be achieved by either
decreasing VeoL or decreasing the average drive current
through pulse width modulation of VB.

(

The HDSP-2001 display has an integral untinted glass
lens. A front panel contrast filter is desirable in most actual
display applications. Some suggested filters are Panelgraphic Gray 10, SGL Homalite H100-1266 Gray and 3M
Light Control Film (louvered filters).

T
D.F. = 5(1+T)
The time frame, t + T, allotted to each column of the
display is generally chosen to provide the maximum duty
factor consisten! with the minimum refresh rate necessary

500

2.0
400
w

....
'"
0)0-

i

~

"-

1.5

jl

<2

~~

!~
~Hj

"c
I
x
~

•.0

1,0

K~

, I

300

-

I-

r::

I I

200

:1
•

I

FlECOMMENDED- I--

rat, ,OPERATING

0.5

100

I

-20

~
I--

e--

11
+20

+40

+60

+80

1.0

+100

Figure 2. Maximum Allowable Power
Dissipation vs. Temperature.

2.0

3.0

'.0

VCOL - COLUMN VOLTAGE - V

TA - AMBIENT TEMPERATURE - °C

Figure 3. Relative Luminous Intensity
vs. Temperature.

259

Figure 4. Peak Column Current
VS. Column Voltage.

5.0

to achieve a flicker free display. For most strobed display
systems, each column of the display should be refreshed
(turned on) at a minimum rate of 100 times per second.

If the device is operated at 3.0 MHz clock rate maximum, it
is possible to maintain t-< T. For short display strings, the
duty factor will then approach 20%. For longer display
strings operation at column duty factors of less than 10%
will still provide adequate display intensity in most
applications. For further applications information, refer to
HP Application Note 1001.

With 5 columns to be addressed, this refresh rate then
gives a value for the time t + T of:
1/[5 x (100)) = 2 msec.

-

- v,

GND

OATA'
_IN

_CLOCK

DATA
OUT _

II:~:m"L~';;T
··.IE*~·'~I~
A~~~ "'i~ •
SHIFT REciS
MATR>J<
~~.
G~ 7
.~ "~,, .. ~
t=~~'~J~
.
t
f!fl,c,c
+flf flf
ff~tf %
.. . .
~
,
• -=t:
.~. ~~' ~.~..
:t: ... IfJlfft
f~ ~l} ~
~~r ff 'flf 'f
tli7'
S , ,
~2
.~ lflfft
~:'
Jf'fit 'r .~.~~.~~ '~'1
l~ ~ll ~
..

E"

SlI; 7 LEO

MATRIX

Slt1UD

.

s

0:;:.:>
'

l~ ~l}

?
b:::::-'-

~.

lQ, 111 ~
¢
f}11~

,

-

f-'-- •
~vi

S

t-'- •

rtllit

~7

t-"--

tli7' .
9

?

c.:,:.l

~

=-

.:r~

~

•

.~ iflff ~f

~

•

..

Iflfffif

-

-

-

COL,

COLl

'If'flfff

'~
." ~~~l~

7

-

COL2

?

lli7

~'

'---

~

-

_.

COL 1

.~.~~.~~

~~r ff If!.f J
Lo:;:.:>
ff IffF l}l~~
~~
'l.y
JfIf11+ l II ~*
r;.
r:-::-Itif tffl
,

MATR.X

~ .:.i

'

S
~r
S

..

. 6K7lEb'

'.7LEO
MATRiX'

INTERNAL

COLS

Figure 5. Block Diagram of the HDSP·2001.

CONNECTION
(DO NOT CONNECT)

I

~~

Ll

I

IN

RESET IN

CLOCK IN

.. 7

i/N COUNT!P. .
LOCK H .. No. Of Q1G1T$
OUT
IHOlsP(.A.Y
IN

OUT

$TRING

I
I· .

CI.OCi'•• ,

r'

I. I

'm;~ ~T£4,'

r-,

I

Description
The HP HDSP-2010 display is designed for use in
applications requiring high reliability. The character font
is a 3.8mm (0.15 inch r~~d LED array for displaying
alphanumeric information. The device is available in 4
character clusters and is packaged in a 12-pin dual-in-line
type package. An on-board SIPO (Serial-in-parallel-out)
7-bit shift register associated with each digit controls
constant current LED row drivers. Full character display is
achieved by external column strobing. The constant
current LED drivers are externally programmable and
typically capable of sinking 13.5mA peak per diode.
Applications include interactive I/O terminals, avionics,
portable telecommunications gear, and hand held
equipment requiring alphanumeric displays.

", •. >, •

r-,

1·1

COLUMN 3

I

COLUMN 4

10

I

COLUMN 5
INT. CONNECT-

11
12

-,1--+2 ~-3 1--+ 4 I
I

~

I
L

I

~

I

I

L_J

I

6

L_~

'~f*.>T~~~I.!~ >,
::# '.'
,,'J;..;

'

>;"

:~;-:~::

261

';"'.

.v

•

"; :,

',,' ,',:. ~<

Absolute Maximum Ratings
Supply Voltage Vee to Ground .......... -O.SV to 6.0V
Inputs, Data Out and VB ................ -O.SV to Vee
Column Input Voltage, VeOl. .......... -O.SV to +6.0V
Free Air Operating Temperature
Range, TYI........................ -40·C to +70·C

Storage Temperature Range, Ts ..... -SS·C to +100·C
Maximum Allowable Package Dissipation
at T A =25· CII,,,.1 ......................... 1.70 Watts
Maximum Solder Temperature 1.59mm (.063")
Below Seating Plane 1<5 sees ............... 260·C

Recommended Operating Conditions
Parameter

Symbol

Supply Voltage

. Vee

Data Out Current. Low State
Data Out Current HighState

Nom.

Min.
4.75

5.0

IOL

h}H

Column Input Voltage. Column On

VeoL

Setup Time
HOld Time
Width of Clock
Clock Frequency

tsetu.p

2.6
70

45

' t-hold

30

0

t.,.,fClockl

75
0

f dud•

Clock Transition Time
Free Air Operating Temperature Range

Unlls

1.6

mA

-0.5

mA

V

V

Vee

ns
ns
ns

t/Hc

TA

Max.
5.25

-40

3

MHz

200

ns
·C

70

Electrical Characteristics Over Operating Temperature Range
(Unless otherwise specified.)
Description

Symbol

Supply Current

Icc

Column Current at any Column Input

leol

Column Current at any Column Input
Peak Luminous Intensity per LED'3.71
(Character Average)

leol

Ve. Clock or Data Input Threshold High
VB. Data Input Threshold Low
Clock Threshold Low
Input Current Logical 1
Input Current Logical 0

VB. Clock
Data In
Va, Clock
Data In

Data Out Voltage
Power Dissipation Per Package"
Peak Wavelength
Dominant Wavelength lS )

IvPEAK

Test Conditions

=

Vee = 5.2SV
VeOl = 3.5V
All SR Stages = Logical 1
Vee

Typ.'

Max.

Units

Va'" OAV

45

60

mA

Va

= 2AV

73

95

mA

Va

= OAV
= 2AV

1.5

mA

350

435

mA

Min.

Vee'" 5.25V
VeLoeK = VVATA "" 2AV
All SR Stages
Logical 1

Va

= 5.0V, VeOl = 3.5V

T, '" 25°C: 4 1 Va = 2.4V

VIH
VIL
VIL
hH
IIH
IlL
Itl
VOH

105

200

~cd

2.0
Vee'" Veal = 4.75V

Vee = 5.25V. VII-!

~

0.8
0.6

2AV

Vee ~ 5.25V, VIL '" OAV
Vee; 4.75V.loH = -a.5mA. VeOl ; OV

2A

V
V
V

20
10

80

fLA

40

~A

-500
-250

-800

I'A

-400

~A

004

V
V

VOL

Vee"" 4.75V, IOl = 1.6mA, VeOl = OV

3.4
0.2

Po

Vee z 5.0V, Veal 2.6V,
15 LEOs on per character, Vs = 2.4V

=

0.66

W

655

nm

APEAK
Ad

nm

640

Leak Rate

5 x 10-7

eels

-All typical values specified at Vee::= S.OV and TA == 25°C unless otherwIse noted.
··Power dissipation per package with 4 characters illuminated.
NOTES:

1. Maximum absolute dissipation is with the device in a socket having a thermal resistance from pins to ambient of 35° C/watt/device.
2. The device should be derated linearly above 25°C at 16mWrC (see Electrical Description on page 3).
3. The characters are categorized for Luminous Intensity and color with the category deSignated by a letter code on the bottom of the
package.
4. T, refers to the initial case temperature of the device immediately prior to the light measurement.
S Dominant wavelength Ad, is derived from the elE chromaticity diagram, and represents the single wavelength which defines the color
of the device.
6. Maximum allowable diSSipation is derived from Vee::::: Va ::::: VeOl = 5.25 Volts. 20 LEOs on per character
7. The luminous stearance of the LED may be calculated using the following relationships:
L, (Lux) = I, (Candela)/A (Metre)2
L, (Footlamberts) = ".1, (Candela)/A (Foot)2
A = 5.3 X 10-8 M2 = 5.8 X 10-7 (Foot)2

262

3M Light Control Film (louvered filters). OCLI Sungard
optically coated glass filters offer superior contrast
enhancement.
Post solder cleaning may be accomplished using water,
Freon/alcohol mixtures formulated for vapor cleaning
processing (up to 2 minutes in vapors at boiling) or
Freon/alcohol mixtures formulated for room temperature
cleaning. Suggested solvents: Freon TF, Freon TE,
Genesolv DI-15, Genesolv DE-15.

Electrical Description
Parameter
ferock
eLOCKRate

['3"

:':

'"",Hi
':,

tPUh hH(

,-Propagation

,delay, CLOCK
to DATA OUT

The HDSP-2010 display provides on-board storage of
decoded column data and constant current sinking row
drivers for each of 28 rows in the 4 character display. The
device consists of four LED matrices and two integrated
circuits that form a 28-bit serial input-parallel output
(SIPO) shift register, see Figure 5. Each character is a
5 x 7 diode array arranged with the cathodes of each row
connected to one constant current sinking output of the
SIPO shift register. The anodes of each column are
connected together, with the same column of each of the
4 characters connected together (I.e. column 1 of all four
characters are connected to pin 1). Any LED within any
character may be addressed by shifting data to the
appropriate shift register location and applying a voltage
to the appropriate column.
Associated with each shift register location is a constant
current sinking LED driver, capable of sinking a nominal
13.5 mAo A logical 1 loaded into a shift register location
enables the current source at that location. A voltage
applied to the appropriate column input turns on the
desired LED.
The display is column strobed on a 1 of 5 basis by loading
7 bits of row data per character for a selected column. The
data is shifted through the SIPO shift register, one bit
location for each high-to-Iow transition of the clock. When
the HDSp·2010 display is operated with pin 1 in the lower
left hand corner, the first bit that is loaded into the SIPO
shift register will be the information for row 7 of the right
most character. The 28th bit loaded into the SIPO shift
register will be the information for row 1 of the left most
character. When the 28 bits of row data for column 1 have
been loaded into the SIPO shift register, the first column is
energized for a time period, T, illuminating column 1 in all
four characters. Column 1 is turned off and the process is
repeated for columns 2 through 5.

Condition Min. Typ, ,Max. Uhi.

I

CL c;,15pF
Rl,;=;2.4Kn

'

,< :

,<,'

'

:'"
ns"

125

I"',, "" I '

Figure 1. Switching Characteristics. (Vee = 5V,
TA = ·40°C to +70° C)

Mechanical and
Thermal Considerations
The HDSP-2010 is available in a standard 121ead ceramicglass dual in-line package, It is designed for plugging into
DIP sockets or soldering into PC boards. The packages
may be horizontally or vertically stacked for character
arrays of any desired size.
The HDSP-2010 can be operated over a wide range of
temperature and supply voltages. Full power operation at
TA = 25°C (Vee = VB = VeOl = 5.25V) is possible by
providing a total thermal resistance from the seating plane
of the pins to ambient of 35°C/W/device maximum. For
operation above TA = 25°C, the maximum device
dissipation should be derated above 25°C at 16mW/oC
(see Figure 2). Power derating can be achieved by either
decreasing Veol or decreasing the average drive current
through pulse width modulation of VB.
The HDSP-2010 display has an integral red glass lens. A
front panel contrast filter is desirable in most actual
display applications. Some suggested filters are Panel
graphic Ruby Red 60, SGL Homalite H100-1605 Red and
4,0

500
TA '" 25~C

"
E

0

"

3,0

" f',

5

0

0

-40

-20

+20

+40

+60

TA - AMBIENT TEMPERATURE _

+80

°c

Figure 2. Maximum Allowable Power
Dissipation vs. Temperature.

o

-40

z

-

:;;

'" "-20
TA

300

::0

I\.

u

5

'"'"
u

iii

\.

2,0

>-

400

~

+20

30
u

-.....

I

............

+40

I J
)

ReCOMMENDED

O~~l~NG ~

100

II

+60

AMBIENT TEMPERATURE _

+80

°c

Figure 3. Relative Luminous Intensity
vs. Temperature.

263

I

200

~"
o
o

u

2.0

2.6 3.0

4,0

VeOl - COLUMN VOLT AGE - V

Figure 4. Peak Column Current
vs. Column Voltage.

5,0

The time frame allotted per column is (t + T) and the
minimum recommended refresh rate for a flicker free
display is 100 Hz, so that (t + T) S 2 ms. If the display is
operated atthe 3 MHz maxi m um clock rate, itis possi ble to
maintain t« T. Fordisplay strings of 24 characters or less,
the LED on time OF will be approximately 19.4%. For
longer display strings, operation of the display with OF
approximately 10% will provide adequate light output for
indoor applications.

"",

28 BIT SIPO SHIFT

REGISTER

lIEFllAl'"

, 'DECODEO

!>ATA,

,0lJ,Tl'UT,

The 28th stage of the SIPO shift register is connected to
the Data Output, which is designed to interface directly to
the Data Input ofthe next HDSP-2010 in the display string.
The VB input may be used to control the apparent
brightness of the display. A logic high applied to the VB
input enables the display to be turned ON, and a logic low
blanks the display by disabling the constant current LED
drivers. Therefore, the time average luminous intensity of
the display can be varied by pulse width modulation of VB.
For application and drive circuit information refer to HP
Application Notes 966 and 1001.

,: ,"

High Reliability Test program
Hewlett-Packard provides standard high reliability test
programs in order to facilitate the use of HP products in
military programs. The TXV prefix identifies a part which
has been preconditioned and screened per Table 1.

Figure 5. Block Diagram of the HDSP-2010 Display

Knowing the time period, t, to load the data into the
display, the LED on time duty factor, OF, may be
determined

PART NUMBER SYSTEM

T
OF = 5(HT)

TABLE 1. TXV Preconditioning and Screening - 100%

MIL.-tTD-883

Methods
oeD Procedure

" , ',>2:, ,High Te-lnPtrature Storage :
: 3'.' Temperature Cycling

1010

, 1oo·c. 24 firs, '
-55·C 'to +1oo"C, 10 Cycles
2~OOO

" ,~ "

G's. Y1 Orien~tlcjJi

1()14 ,

,Condition A,

1014

Condition C"Inspect at 100"C

,-",';','

-

6.~-Qross Leak", '.'"

:1. :~,~"

,~

EleClbL;'; 1.6mA .

.vco = 4.75V

"

.

Clock OulputYoItaQe . .

'Reset Input Our~~
.,

Chip SeleCt,

',\",,,'

Vee ",,4.75V

.. 'mA VIH= 3,OV

rnA

"'.:',

07 Inplit :Current .•

}ill..

Column OutpUt Voltage' ,;

.\IlL

=o:sv'"

O 100Vls.
3. Momentary peak surge currents may exist on these lines. However, these momentary currents will not interfere with
proper operation of the HDSP-2470/1/2.

266

HDSP-2416/-2424/-2432/-2440

Recommended
Operating Conditions

Absolute Maximum Ratings
··1

Supply Voltage Vee to Ground ......... -0.5V to 6.0V
Inputs, Data Out and VB

............... -0.5V to Vee

Column Input Voltage, VeOl

.........

-0.5V to +6.0V

Free Air Operating Temperature
Range, TAI11 ....................... O°C to +55°C
Storage Temperature Range, Ts .... -55°C to +100°C

Electrical Characteristics OVer operating Temperature Range
(Unless otherwise specified)

"All typical values specified at Vee = 5.0V and TA = 25°C unless otherwise noted.
NOTES:
1. Operation above 55° C (70° C MAX) may be achieved by the use of forced air (150 fpm normal to component side of
HDSP-247X controller board at sea level). Operation down to -20° C is possible in applications that do not require the
use of HDSP-2470/-2471/-2472 controller boards.
2. n = number of HDSP-2000 packages
HDSP-2416 n = 4
HDSP-2424 n = 6
HDSP-2432 n = 8
HDSP-2440 n = 10
3. Tj refers to initial case temperature immediately prior to the light measurement.
4. Power dissipation with all characters illuminated.

267

System Overview
The HDSP-2470/-2471/-2472 Alphanumeric Display
Controliers provide the interface between any ASCII
based Alphanumeric System and the HDSP-2000
Alphanumeric Display. ASCII data is loaded into the
system by means of anyone of four data entry modes Left, Right, RAM or Block Entry. This ASCII data is stored
in the internal RAM memory of the system. The system
refreshes HDSP-2000 displays from 4 to 48 characters
with the decoded data.
The user interfaces to any of the systems through eight
DATA IN inputs, five ADDRESS inputs (RAM mode), a
CHIP SELECT input, RESET input, seven DATA OUT

outputs, a READY output, DATA VALID output, and a
COLUMN ON output. A low level on the RESET input
clears the display and initializes the system. A low level on
the CHIP SELECT input causes the system to load data
from the DATA I N and ADDRESS inputs into the system,
The controlier outputs a status word, cursor address and
32 ASCII data characters through the DATA OUT outputs
and DATA VALID output during the time the system is
waiting to refresh the next column of the display, The
COLUMN ON output can be used to synchronize the
DATA OUT function, A block diagram for the HDSP2470/-2471/-2472 systems is shown in Figure 1.

OATAOUT
DATA VALID
COLUMN ON
VB, DISPLAY
BLANKING

t-t---

-C
RAM ADDRESS

~

DATA IN

---l-

CHIP SELECT

-C

READY

,

7
r3J_
DISPLAY
COIIITROLLER

I
I *
I
L __

,3

~

1110

DECOOER

-A

DRIVE
TAAI\IS

COLUMN 1-5

I
I
I
_.J
,7

-

DISPLAY DATA

"ISO

CLOCK

* CHARACTER GENERATOR FOR HDsp·2471,
SOCKET FOR lK X 8 PROM FOR HOSP·2472.

Figure 1. Block Diagram for the HDSP-2470/-2471/-2472 Alphanumeric Display Controller.

20

The system interfaces to the HDSP-2000 display through
five COLUMN outputs, a CLOCK output, DISPLAY DATA
output, and the COLUMN ON output. The user should
connect DISPLAY DATA to DATA IN of the leftmost
HDSP-2000 cluster and cascade DATA OUT to DATA IN
of ali HDSP-2000 clusters. COLUMN outputs from the
system are connected tothe COLUMN inputs of ali HDSP2000 clusters. The HDSP-24XX Series display boards are
designed to interconnect directly with the HDSP-247X
Series display controliers. The COLUMN outputs can
source enough current to drive up to 48 characters of the
HDSP-2000 display. Pulse width modulation of display
luminous intensity can be provided by connecting
COLUMN ON to the input of a monostable multivibrator
and the output of the monostable multivibrator to the VB
inputs ofthe HDSP-2000 displays. The system is designed
to refresh the display at a fixed refresh rate of 100 Hz.
COLUMN ON time is optimized for each display length in
order to maximize light output as shown in Figure 2.

18
w
:IE

;::
z
0
z

:IE

::>
....
0
C.>

~

.", ~

~

16

r-...: i'-...'iDSP·24111.2472

N"

14

HDSP·2470.....

"~
~

12

i'..

""

...

"

10

00

r.....

4

8

12 16 20 24 28 32 36 40 44 48
DISPLAY LENGTH

Figure 2. Column on Time vs. Display Length for the
HDSP-2470/-2471/-2472 Alphanumeric Display Controller.

268

Control Mode/Data Entry

fO

User interface to the HDSP-247X Series controller is via an
8 bit word which provides to the controller either a control
word or standard ASCII data input. In addition to this user
provided 8 bit word, two additional control lines, CHIP
SELECT and READY, allow easily generated "handshake"
signals for interface purposes.

CONTROL
WORD: D7D6D5D4D3D2D1DO
I 11X xl-IV V V Vi
VVVV

o0

A logic low applied to the CHIP SELECT input (minimum
six microseconds) causes the controller to read the 8
DATA IN lines and determine whether a control word or
ASCII data word is present, as determined by the logic
state of the most Significant bit (07). If the controller
detects a logic high at 07, the state of 06-00 will define the
data entry mode and the number of alphanumeric
characters to be displayed.

0 0
000 1
001 0

o0
o1
o1
o1
o1

1
0
0
1

1
0
1
0

1 1
1 000
100 1
101 0
1 0 1 1

The 8 bit control data word format is outlined in Figure 3.
For the control word (07 high), bits 06 and 05 define the
selected data entry mode (Left entry, Right entry, etc.) and
bits 03 to Do define display length. Bit 04 is ignored.

DISPLAV LENGTH:
4 DIGITS

8
12
16
20

24
28
32'
36
40

"

44
48

'maximum for RAM data entry mode

Control word inputs are first checked to verify that the
control word is valid. The system ignores display lengths
greater than 1011 for left block or right, orOlll for RAM. If
the word is valid, the present state-next state table shown
in Figure 4 is utilized to determine whether or not to clear
the display. For display lengths of up to 32 characters,
RAM entry can be used as a powerful editing tool, or can
be used to preload the cursor. With other transitions, the
internal data memory is cleared.

x X

DATA ENTRV MODES

o0
o1

RAM DATA ENTRV
LEFT DATA ENTRV
RIGHT DATA ENTRV
BLOCK DATA ENTRY

1 0
1 1

Figure 3. Control Word Format for the HDSP-2470/-2471/-2472
Alphanumeric Display Controller.

11)

RAM ENTRY MODE IS VALID FOR DISPLAYS OF

32 CHARACTERS OR LESS IN LENGTH.
12)

r

FOLLOWING A TRANSITION FROM RAM TO
BLOCK. WHEN THE CURSOR ADDRESS IS 48
130,.) DURING THE TRANSITION. THE FIRST
VALID ASCII CHARACTER WILL BE IGNORED
AND THE SECOND VALID ASCII CHARACTER
WILL BE LOADED IN THE LEFT· MOST DISPLAY
LOCATION.

WHERE BEGIN IS DEFINED AS FOLLOWS:
DISPLAY
LENGTH

8
12
16
20
24
28
32
36

CLEAR,
B~INKII!/C

CURSOR. BEGIN'

40

44
48

CURSOR ADDRESS
OF BEGIN

2C, •• 44,0
28, •• 4010
24, •• 36,0
20, •• 3210
1C, •• 2&,0
18, •• 24,0
14, •• 20,0
10,6. 16,0
0C, •• 12,0
08, •• &'0
04, •• 4,0
DO,.

Figure 4. Present State-Next State Diagram for the HDSP-2470/-2471/-2472 Alphanumeric Display Controller.

269

If 07 is a logic low when the DATA IN lines are read, the
controller will interpret De-Do as standard ASCII data to be
stored, decoded and displayed. The system accepts seven
bit ASCII for all three versions. However, the HDSP-2470
system displays only the 64 character subset [2016

(space) to 5F16 L.)] and ignores all ASCII characters
outside this subset with the exception of those characters
defined as display commands. These display commands
are shown in Figure 5. Displayed character sets for the
HDSP-2470/-2471 systems are shown in Figure 6.

DATA WORD:

D7 D6 D5 D4 D3 D2 Dl DO

ASCII ASSIGNMENT

1 0 I A A A A A A AI

LF
BS

HT
US
DEL

0
0
0
0
1

0
0
0

0
1

0
0
0

0
0
0

0
0
1

1

1

1

1

1

1

DISPLAY COMMAND

I"·· 1

CLEAR
Right Entry
BACKSPACE CURSOR
Modo
FORWARDSPACE CURSOR
INSERT CHARACTER
DELETE CHARACTER

Volid in

~~oEntry

Figure 5. Display Commands for the HDSP-2470/-2471/-2472 Alphanumeric Display Controller.

128 CHARACTER ASCII SET
(HDSP-2471)
84 CHARACTER ASCII SUBSET
(HDSP·2470)

0001

DOlO

00'1

0100

0101

0'10

0111

1000

1001

1010

101'

1100

1101

1110

1111

*DISPLAY COMMANDS WHEN USED IN LEFT ENTRY
+DISPLAY COMMANDS WHEN USED IN RIGHT ENTRY

Figure 6. Display Font for the HDSP-2470 (64 Character ASCII Subset), and HDSP-2471 (128 Character ASCII Set) Alphanumeric
Display Controller.

270

Regardless of whether a control word or ASCII data word
Is presented by the user. a READY signal is generated by'
the controller after the input word is processed. This
READY signal goes low for 25/o1s and upon a positive
transition. a new CHIP SELECT may be accepted by the
controller. Data Entry Timing is shown in Figure 7.

DATA ENTRY TIMING

I.

RAM ADDRESS

I---l0~S MAX.

~"M'l1..

CHIPSELECT

·1

ADDRESS HOLD TIME

E D A T A HOLD T I M E 3

-+1_______________________..

-1-1.

_1-_6jt_S_'MI_N._ __
DATA ENTRY TIME

READY

----------1.11- 2.6~s·
II- -IL
26jts

IF'CHIP SELECT. 0
AFTER THIS TIME,
CONTROLLER WILL
ENTER NEXT CHARACTER.

MAXIMUM DATA ENTRY TIMES OVER OPERATING TEMPERATURE RANGE
DATA ENTRY MODE
DATA HOLD TIME"

BACK
SPACE

CLEAR

FORWARD
SPACE

DELETE

INSERT

LEFT (2471/2)
LEFT (2470)

1351's
1501's

2351's
2451's

1951's
2151's

5051'5
5301'5

2051'S
2251's

7251'5
7451'5

7251'5
7351'5

RIGHT (2471/2)
RIGHT (2470)

851'5
1051's

4801'5
4901'5

4701'5
, 4901'5

4651'5
4851'5

HDSP-

(

FUNCTION
DATA
ENTRY

RAM (2471/2)
RAM (2470)

551'5
551'5

8LOCK (2471/2)
8LOCK (2470)

551'5
551'5

1201'S
1301's

LOAD CONTROL (2471/2)
LOAD CONTROL (2470)

501'5
501'5

5051'5
5051'5

1201's"
1301's"

1901's
2001's
(1551'S FOR RIGHTMOST CHARACTER)
(1651'S FOR RIGHTMOST CHARACTER)

"Minimum time that data inputs must remain valid after Chip Select goes low.
"Minimum time that RAM address inputs must remain valid after Chip Select goes low.

Figure 7. Data Entry Timing and Data Entry Tim.. for the HDSP-2470/-2471/-2472 Alphanumeric Display Controller.

271

Left Entry Mode

for displays less than or equal to 32 characters.
Regardless of display length, address 00 is the leftmost
display character. Out of range RAM addresses are
ignored. While RAM entry has a non-visible cursor, the
cursor is always preloaded with the address to the right of
the last character entered. This allows the cursor to be
preloaded with an address prior to going into any other
entry mode. In RAM entry, the system can display the
complete 128 character ASCII set because it does not
interpret any of the characters as control functions. The
display can be cleared by loading in a new RAM control
word.

With Left entry, characters are entered in typewriter
fashion, Le., to the right of all previous characters. Left
entry uses a blinking cursor to indicate the location where
the next character is to be entered. CLEAR loads the
display with spaces and resets the cursor to the leftmost
display location. BACKSPACE and FORWARDSPACE
move the cursor without changing the character string.
Thus, the user can backspace to the character to be
edited, enter a character and then forward space the
cursor. The DELETE function deletes the displayed
character at the cursor location and then shifts the
character string following the cursor one location to the
left to fill the void of the deleted character. The INSERT
CHARACTER sets a flag inside the system that causes
subsequent ASCII characters to be inserted to the left of
the character at the cursor location. As new characters are
entered, the cursor, the character at the cursor, and all
characters to the right of the cursor are shifted one
location to the right. The INSERT function is terminated
by a second INSERT CHARACTER, or by BACKSPACE,
FORWARDSPACE, CLEAR or DELETE. In Left entry
mode, after the display is filled, the system ignores a'll
characters except BACKSPACE and CLEAR. The system
allows the cursor to be positioned only in the region
between the leftmost display character and immediately
to the right (offscreen) of the rightmost display character.

Data Out

For display lengths of 32 characters or less, the data
stored in the internal RAM is available to the user during
the time between display refresh cycles. The system
outputs a STATUS WORD, CURSOR ADDRESS, and 32
ASCII data characters. The STATUS WORD specifies the
data entry mode and the display length of the system. The
STATUS WORD output differs slightly from the CONTROL WORDinput. This difference is depicted in Figure 8.
Regardless of display length, the CURSOR ADDRESS of
the rightmost character location is address 47 (2F16) and
the offscreen address of the cursor is address 48 (3016).
The CURSOR ADDRESS of the leftmost location is
defined as address 48 minus the display length. A general
formula for CURSOR ADDRESS is:

Right Entry Mode

In Right entry mode, characters are entered at the right
hand side of the display and shifted to the left as new
characters are entered. In this mode, the system stores 48
ASCII characters, although only the last characters
entered are displayed. CLEAR loads the display with
spaces. BACKSPACE shifts the display one location to the
right, deleting the last character entered and displaying
the next character in the 48 character buffer. Right entry
mode is a Simple means to implement the walking or
"Times-Square" display. FORWARDSPACE, INSERT,
and DELETE have character assignments in this mode
since they are not treated as editing characters. In this
mode, the cursor is located immediately to the right
(offscreen) of the rightmost displayed character.

CURSOR ADDRESS =
(47 - Display Length)

+ Number of Characters from

Left.

For example, suppose the alphanumeric display is 16
characters long and the cursor was blinking at the third
digit from the left. Then the CURSOR ADDRESS would be
47 -16 + 3 or34 (2216) and the 18th ASCII data word would
correspond to the ASCII character at the location of the
display cursor. In Left and Block entry, the CURSOR
ADDRESS specifies the location where the next ASCII
data character is to be entered. In RAM entry, the
CURSOR ADDRESS specifies the location to the right of
the last character entered. In Right entry, the CURSOR
ADDRESS is always 48 (3016). The negative edge of the
DATA VALID output can be used to load the 34 DATA
OUT words into the user's system. The DATA OUT timing
for the HDSP-247X systems are summarized in Figure 8.
For displays longer than 32 characters, the system only
outputs the STATUS WORD between refresh cycles.

Block Entry Mode

Block entry allows the fastest data entry rate of all four
modes. In this mode, characters are loaded from left to
right as with Left entry. However, with Block entry, after
the display is completely loaded, the next ASCII character
is loaded in the leftmost display location, replacing the
previous displayed character. While Block entry has a
nonvisible cursor, the cursor is always loaded with the
address of the next character to be entered. In this entry
mode, the system can display the complete 128 character
ASCII set. The display can be cleared and the cursor reset
to the leftmost display locati()n by loading in a new
BLOCK control word.

Master/Power On Reset

When power is first applied to the system, the system
clears the display and tests the state of the DATA INPUT,
D7. If D7 > 2.0V, the systems loads the control word on the
DATA INPUTS into the system. If D7:S .8V or the system
sees an invalid control word, the system initializes as Left
entry for a 32 character display with a flashing cursor in
the leftmost location. For POWER ON RESET to function
properly, the power supply must turn on at a rate> 100 Vis.
In addition, the system can be reset by pulling the RESET
input low for a minimum of 50 milliseconds. POWER
ON/MASTER RESET timing is shown in Figure 9.

RAM Entry Mode

In RAM entry, ASCII characters are loaded at the address
specified by the five bit RAM address. Due to the limitation
of only five address lines, RAM data entry is allowed only

272

2OCIOjt.

--,---------------1-1

HDSP·
2470

ASCII DATA

HDSP-

COLU~=..J

2470

--It-2501
ASCII
DATA

STATU~.
CURSOR I
DATA
I. DATA
WORD
ADDRESS...j-WORD -+-WORDS

I IA)·
I---

6OOn. MIN

liB)

!-5OOn, MIN

11 - 311

(0)

HDSP-

--11- 1.211'

ON--l!-11'1
HDSP247112472

Jl:L1~
ASCII
DATA

&DOns MIN

e.

-,""__--' !-_ _ n
....I

STATUS WORD FORMAT IWORD A)
0 6 Os D4 D:! D:! 0, Do

l

0

0

0

0

0

1

0

1

0

1

0

0

n"'_______

35,..--1-- 35ps --I

= 30.5•• + 20•• X Displav Length
= 17.5•• + 17.5•• X Display Length

Y, DATA VALID TO COLUMN OFF TIME
IDispiay Length <32 ChlrllC18rs)
IHDSp·2470)
- 813.5•• - 20.. X Display Length
IHDSp·24711·2472) = 826.2•• - 17.5•• X Display Length

COLUMN--,"'__________________________________

2471/·2472

Figure

X, COLUMN OFF TIME
IHDSp·2470)
IHDSP·24711·2472)

Jl:'?;~ ....,"'___~

HDSP·
2470

RAM ENTRY
Y

Y

Y

Y

BLOCK ENTRY
LEFT ENTRY
RIGHT ENTRY

YYYY = DISPLAY LENGTH
CURSOR ADDRESS FORMAT !WORD B)
CURSOR ADDRESS = 147 - Display Length) + No. of
Characters from Left

I

I

STATrJis CURSOR +DATA
DATA
WORD
ADDRESS
WORD-+--WORDS
--IA)
I-IB)
(0)
11 - 311
500n. MIN

I--

.

DATA WORD FORMAT IWORDS 0-31)
STANDARD ASCII DATA Where Word (31) i. Rightmost
Displayed ASCII Character

Data Out Timing and Format for the HDSP-2470/-2471/-2472 Alphanumeric Displa, Controller.

1 •..---------

·1

5 O m . M I N I - - - - - - - - -. .

l~~.

READY

DATA INPUT, D7
INITIALIZES AS LEFT ENTRY
MODE, 32 CHARACTER· DISPLAY
LENGTH

Figure •• P_er-OnlMuter Reaet Timing lor the HDSP-2470/-2471/·2472 Alphanumeric Displa, Controller.

273

Custom Character Sets
The HDSP-2472 system has been specifically designed to
permit the user to insert a custom 128 ASCII character set.
This system features a 24 pin socket that is designed to
accept a custom programmed 1K X 8 PROM, EPROM, or
ROM. The read only memory should have an access time::;
500ns, ilL ::;1-.4mAI and IIH ::;40~A. A list of pin compatible
read only memories is shown. in Figure 10. Jumper
locations are provided on the HDSP-2472 P.C. board
which allow the use of ROM's requiring chip enables tied
either to 0 or 5V. For further information on ROM
programming, please contact the factory.
Power Supply Requirements
The HDSP-247X Alphanumeric Display System is
designed to operate from a single 5 volt supply. Total Icc
requirements for the HDSP-247X Alphanumeric Display
Controller and HDSP-24XX Display Panel are shown in
Figure 11. Peak Icc is the instantaneous current required
for the system. Maximum Peak Icc occurs for Vee = 5.25V
with 7 dots ON in the same Column in all display
characters. This current must be supplied by a
combination of the power supply and supply filter
capacitor. Maximum Average Icc occurs for Vee = 5.25V
with 21 dots ON per character in all display characters.
The inclusion of a 375 X microfarad capacitor (where X is
the number of characters in the display) adjacent to the
HDSP-247X Alphanumeric Display System will permit the
use of a power supply capable of supplying the maximum
average Icc.

DISPLAY LENGTH

Figure 11. Maximum Peak and Average Icc for the HDSP-

2470/71n2 Alphanumeric Display Controller and HDSP-2000
Display.

CONNECTORS

Amp PIN 1-5301S01i-1; iII$o'-::'
availoblo in bQaid tt'llib!.' ',, iInd ou.ed:oilflgUn.t!oi\s' ,:',,'
NOTES:

(1) Power leads should be 18-20 gauge stranded wire,
(2) The maximum lead length from ·the controller board to the

display should not exceed 1 metre,
(3) The suggested Amp connector is supplied with the conlroller,

EXTERNAL CONNECTION·
PART NUMBER
2758

K

y

GND

GND

+5

NC

NC

NC

+5

+5

GND

NC

NC

NC

8IPOLAR-NiCr

+5

+5

GND

BIPOLAR-NiCr

NC

NC

NC

BIPOLAR-TiW

+5

+5

GND

PROM

BIPOLAR-NiCr

+5

+5

GND

ROM

NMOS

NC

NC

Signetics

ROM

NMOS

NC

NC

Mostek

ROM

NMOS

+5

NC

MANUFACTURER

TYPE

CONSTRUCTION

Intel

EPROM

NMOS

7608

Harris

PROM

8IPOLAR·NiCr

3628·4

Intel

PROM

8IPOLAR·Si

8252708

Signetics

PROM

8IPOLAR-NiCr

6381

Monolithic Mem.

PROM

6385

Monolithic Mem.

PROM

87S228

National

PROM

93451

Fairchild

68308

Motorola

2607
30000

~

'Board jumpers correspond
to pins 18, 19 & 21 of ROM •
•• As defined by customer

Figure 10. Pin Compatible 1K x 8 Read Only Memories for the HDSP-2472 Alphanumeric Display Controller.

Display Boards/Hardware

Included with the controller board are: 1 each Amp PIN 1530500-7 board to board connector, and 4 each locking
circuit board support nylon standoffs (Richco LCBS-4).
This hardware allows the controller board to interconnect
with any of the standard display boards. Figure 12 depicts
correct assembly technique.

The mechanical layout of the HDSP-247X Series allows
direct mating of the controller P.C. board to a compatible
series of display boards available from Hewlett-Packard.
These display boards consist of matched and tested
HDSP-2000 clusters soldered to a P.C. board.

274

Assembly Steps
1.

Insert the standoffs into .151 diameter holes (noted as
"S" on Figure 12. The long end of the standoffs should
protrude through the controller board side.

2.

Position the controller board and display board with
the components and displays facing out. The HP logo
should be in the upper left corner when viewed facing
the boards. Insert the standoffs through the mating
holes on the display board and press the boards together so that the standoffs.lock in place.

3.

After the standoffs are secured, the Amp connector
should be placed on the edge connect pads (marked
"A" through "Q" Figure 12) at the top of the boards.
Visual alignment of this connector may be done on the
controller board by determining that the first connector contact finger is centered on the pad labeled "A".

AMP Connector
(AMP pin 1-5:!OSIIO-~n'
3M Connector
(3M pin 3429-1002)

,~

MOLEX Connector
(MOLEX pIn 09-65-1031)

I
HDSP-2416/24/32/40
-'''----Dllf)lay Board

f
HDSP-2470mnz ----1HController Board

S

Figure 12. Assembly Drawing.

275

package Dimensions
3..DIATHRU

HDSP-Z4N/Z4711Z47Z
DESCRIPTIO'

""•
••
••
,,,•
1D

DATAYALID
RMADDREII..At
DATA IN. 0,
RAMADDREIS,A,

IIEIIT

RAM ADDREss. AI

DATA OUT, DO.
RAM ADORE" A3
DATA OUT, DO,

DATAIN,Do

""
""
."
Z1
"..

DATA OUT' DO.
OA1A III, 0,
DATA OUT, 003

17

.
.
...

r.mJeHDLES

emmmT

n

14

UNLESSDTHERWIS£ SPltlFlEO, DIMENSiONS ARE II . . AND fiNCHES)

BATA IN, DI
DATA OUT, Doz
DATA IN,03
. DATA OUT, DD,

a.

DATA IN.
DATA OUT. DO,
DATA II. Os
READY

DAT.'I,O,
COLUMI.I
RAM ADDREss. A..

1+---------=:~~---------"1

I

'·'-1

DI.LAY BLANK. V,

T.liIl

I+-----~t~::·----------------I

1------------f.f,fREF----------~

Figure 13. HDSP-2470/-2471/-2472

.i:',
r/'A 1it"
Wl''''l-=ill
TY'- --'-

HO..Z411J.2424I-2432/.J440
HDIN4701.z47t/-2472
DEICRIPTION
DtlPLAY BLANK, V,
A
•.e COLUMN,
COLUMNz
F.G
COLUMNa
COLUMN.
COLUMN,
tK
L
CLOCK
DI.LAY DATA
Vee

(.tI<M'

""

TlidM

D.'

lDHI:~':J t

H.'

...•
'.Q

iliii"t·.I'D

II...

.547

+

.....

~-T

~._I

I

I

~:::-

U5DDIATHRU
r.rm'HDlES

TV'

HI ~IAH:lHR.
ES

r

.

-[:=r==J

W

I - - 1---

T

!

,"Le.

-----.,'

UMLKJ Ifl8FEDClA

I

I

t·DI.U,Y

l1Ji1
11.1G4±.518
T.IRr:l:.12O

a

,

~
(1.115:1:.110 ~

.N.

f.iiir

TV'

.,j,0

J~

E

r42.114:1:.214
' - - 1f.iiij±.II'

A~'~C

Ii.

,.....

DISPLAYS

~::~~1~-- I--

LUIlt.

153.122±,Z54
1I.o5l)±.Gl0

'U.aIl±.5II1

".

1lI!I, .

•1

1iiiil

l

.

'"

Figure 14. HDSP-2416/-2424/-2432

!JH.DIA THRU
{.II1)"HOLES
2,51 t'lPlCS
i]ii) TYP

=,------1,

lr.

r!

(.125)

ATVP

UI2 DIATHRU
{,lOll 4 HOLES

,....

T.3tiDJ

1&.104:1: ....

lDiT .....

!Ut!:t.214
{.4Mf:t.110

8.715:1:,254
T.B4J:t ,01'
I.l10:1:,501

Uii/ .....

=____

IH~--JU--.....
----------~---+,-----------------t+---~I
(.IB) :1:,010

I-_ _ _ _

t DISPLAYS

~II

4.343:t.2M
f.ffi):t.Ol.

~-----------------------~:~:-----~

1--------=:::-------------

Figure 15. HDSP-2440

276

r

7.112

T.iiII

Fli;'

HEWLETT

~~ PACKARD

18 SEGMENT
SOLID STATE
ALPHANUMERIC
DISPLAY

HtlSP-6300

TECHNICAL DATA MARCH 1980

Features
• ALPHANUMERIC
Displays 64 Character ASCII Set and
Special Characters
• 18 SEGMENT FONT INCLUDING CENTERED
D.P. AND COLON
• 3.S6mm (0.140") CHARACTER HEIGHT
• APPLICATION FLEXIBILITY WITH
PACKAGE DESIGN
8 Character Dual-In-Line Package
End Stackable
Sturdy Leads on 2.S4mm (0.100") Centers
Common Cathode Configuration

Description
The HDSP-6300 is an eighteen segment GaAsP red
alphanumeric display mounted in an 8 character dual-inline package configuration that permits mounting on PC
boards or in standard Ie sockets. The monolithic light
emitting diode character is magnified by the integral lens
which increases both character size and luminous
intensity, thereby making low power consumption
possible. The eighteen segments consist of sixteen
segments for alphanumeric and special characters plus
centered decimal point and colon for good visual
aesthetics. Character spacing yields 5 characters per
inch.

• LOW POWER
As Low as 1.0-1.SmA Average
Per Segment Depending on Peak
Current Levels

f (·

EXCELLENT CHARACTER APPEARANCE
Continuous Segment Font
High OnlOff Contrast
S.08mm (0.200") Character Spacing
Excellent Character Alignment
Excellent Readability at 1.S Metres

• SUPPORT ELECTRONICS
Can Be Driven With ROM Decoders and Drivers
Easy Interfacing With Microprocessors and
LSI Circuitry

Applications
These alphanumeric displays are attractive for applications such as computer peripherals and mobile terminals,
desk top calculators, in-plant control equipment, handheld instruments and other products requiring low power,
display compactness and alphanumeric display capability.

• CATEGORIZED FOR LUMINOUS INTENSITY
Assures Uniformity of Light Output From Unit
to Unit Within a Single Category

277

Absolute Maximum Ratings
Parameter

R~verse Voltage
Solder Te';"m~'-p~ef:.c,a':"tu-'.r-'e-a-t"-1"',5-:,9..;cm~,m-'"-~-'--+--'-----+~~~"""---!~-""''''''''-------!
(1116 inch) bel.owseating plane,
t 5 5 SeConds
'
'

NOTES:
1, Maximum allowed drive conditions for strobed operation are derived from Figures 1 and 2, See electrical section of operational
considerations,
2. Derate linearly above TA = 50°C at 2.47 mWrC. PD Max. ITA = 85°CI = 47 mW.

Electrical/Optical Characteristics at TA =25°C
'S~~bOr
.,

Parameter
Luminous Intensity, Time
Average, Character Total with
16 Segments lIIuminated [3.4]

'.

FOrward Voltage Per
Segment or DP
Peak Wavelength
Dominant Wavelength [5J
Reverse Current Per
Segment or DP

",tv""

"

VF
APEAK

Ad

IR

,",

,

',:

".'.

",

·Mln., Typ;

Test Condition
IpE'AK 1"'24mA'
1/16 Duty Faclor

400

",'"

..

:

1200
"

IF"'" 24mA
(One Segment On)

1.6

,;lied'
,

V
nm

1.9

655

640

.':. nm

10

",.,' ';uA

VR "".5V·

','

·C/W/
Char.

250

niermal Resistanc.e LED
Junction-to-Pin per Character

ROJ-PIN

Max. ""UnltS'

NOTES:
3, The luminous intensity ratio between segments within a digit is designed so that each segment will have the same luminous
sterance. Thus each segment will appear with equal brightness to the eye.
4. Operation at peak currents of less than 7mA is not recommended.
5. The dominant wavelength, Ad, is derived from the C.I.E. chromaticity diagram and represents that single wavelength which defines
the color of the device, standard red.

~:

"
E
I

>~
~

I

-+

1.0

I

0.9

.,

200
150

'\

100

a::

'\

I

::J
()

"

~

50

-

I

'\

~

~

20
10
7

"",J,-

I
1

t r\ "~11

'0

'Y,. -

i II
10

100
tp

7'""

'Y,.

1000

:"t

0.7

~

0.6

~

0.5

-

.

"- f'\

,

"'-

'"

R'UIN =390'CIW/CHAR"

'\ "

ffio

~~

~~

§

0,8

0.4
0.35
~
0.3

I

0.2

-

0, 1

-DC
10000

50

60

70

80

TA - AMBIENT TEMPERATURE _

PULSE DURATION - /15

Figure 1. Maximum Allowed Peak Current vs. Pulse Duration. Derate derived
operating conditions above TA = 50°C using Figure 2.

278

85

°c

Figure 2. Temperature Derating Factor
For Peak Current per Segment vs.
Ambient Temperature. TJMAX =110°C

~

.

~0r-'--r-'~~~~~r-'--r-'

'801-+-t-t-'+-:-l-'-t-''_"!-"".l"i"_+-'-t

I

~

0:
0:

ao
0:,

~

0:

:!

"

~
I

20 I--+-+-+--+--+--+-~r­

or.
j~LL
1';:,0.J-J--':'"':,2:-'-'-i.:",,':......"":,~.6
1.8
2.0

IpEAK - PEAK SEGMENT CURRENT - rnA

VF - PEAK FORWARD VOLTAGE - V

Figure 3. Relative Luminous Efficiency

Figure 4. Peak Forward Segment
Current VS. Peak Forward Voltage.

(Luminous Intensity Per Unit Current)

vs, Peak Segment Current.

For a Detailed Explanation on the Use of Data Sheet Information and Recommended
Soldering Procedures, See Application Note 1005, Page 464.
A3 A2 A1 Ao

1

A4

0

0

As

•

0

4

3

2

5

7

6

8

9

B

A

C

0

E

F

~RJ3C1JEFGHIJkLMND

PQR5TUVWXYZ[
±9J%~
< > *+

0

J.l'

\

/I

0

2 3 Y5 5 1 B 9

0

Figure 5.

/

~

/

/

L

~

?

Typical 64 Character ASCII Set.

o

f

Additional.Character Font

~4Ii'513MAX~
"

,

,.,'

(1.5951'

~)TYp.

,

I~ITYP.,

"
,

"', f

'

"

'

18.3 • .381
, (.120, .016)

1
16,24. ,254
1.600 • ,010)

NOTES:
1. ALL DIMENSIONS IN MILI-IM£1RES AND fiNCHES),
2. ALL UNTOLERANCEIl DIMENSlONS ARE FOR RE~ERENCE ONLY.
3. PIN 1 IDENTIfiED BY DOT ADJACENT TO LEAD.

2.54'

,.100) TYP.

Figure 6.

279

Magnified Character
Font Description

Device Pin Description
Pin
No.
1
2

3
4

r:2'~9R6~F'~

5
6

7

,~~~7?~t

8
9

10
11
12
13
14

'~5J:l'
d2

15
16
17
18
19
20
21
22

d,

23

Figure 7.

24

25
26

Function
Anode
Anode
Anode
Cathode
Cathode
Cathode
Cathode
Anode
Anode
Anode
Anode
Anode
Anode
Anode
Anode
Anode
Cathode
Cathode
Cathode
Cathode
Anode
Anode
Anode
Anode
Anode
Anode

Segment K
Segment 01
Segment C
Digit 1
Digit 2
Digit 3
Digit 4
Segment L
Segment G2
Segment E
Segment M
Segment 02
Segment DP
Segment A2
Segment I
Segment J
Digit 8
Digit 7
Digit 6
DigitS
Segment Co
Segment Gl
Segment B
Segment F
Segment H
Segment Al

Operational Considerations
ELECTRICAL
The HDSP-6300 device utilizes large monolithic 18
segment GaAsP LED chips including centered decimal
point and colon. Like segments of each digit are
electrically interconnected to form an 18 by N array, where
N is the quantity of characters in the display. In the driving
scheme the decimal point or colon is treated as a separate
character with its own time frame. A detailed discussion of
character font capabilities, ASCII code to 18 segment
decoding, and display drive techniques wlll appear in a
forthcoming application note.

information presented in this data sheet is for a maximum
of 10 segments illuminated per character!
The typical forward voltage values, scaled from Figure 4,
should be used for calculating the current limiting resistor
values and typical power dissipation. Expected maximum
VF values for the purpose of driver circuit design may be
calculated using the following VF model:

VF = 1.8SV + IPEAK (1.80l
For 30mA:::; IPEAK :::; lS0mA
= 1.S8V + IPEAK (10. 70l
For 10mA:::; IPEAK :::; 30m A

VF

This display is designed specifically for strobed
(multiplexed) operation, with a minimum recommended
peak forward current per segment of 7.0 mAo Under
normal operating situations the maximum number of
illuminated segments needed to represent a given
character is 10. Therefore, except 'where noted, the

'More than 10 segments may be illuminated in a given character,
provided the maximum allowed character power diSSipation.
temperature derated, is not exceeded.

280

OPTICAL AND CONTRAST
ENHANCEMENT

)

MECHANICAL
This device is constructed by LED die attaching and wire
bonding to a high temperature PC board substrate. A
precision molded plastic lens is attached to the PC board.

Each large monolithic chip is positioned under a separate
element of a plastic aspheric magnifying lens producing a
magnified character height of 3.56mm (0.140 inch). The
aspheric lens provides wide included viewing angles of60
degrees horizontal and 55 degrees vertical with low off
axis distortion. These two features, coupled with the very
high segment luminous sterance, provide to the user a
display with excellent readability in bright ambient light
for viewing distances in the range of 1.5 metres. Effective
contrast enhancement can be obtained by employing an
optical filter product such as Panelgraphic Ruby Red 60,
Dark Red 63 or Purple 90; SG L Homal ite H 100-1605 Red or
H100-1804 Purple; or Plexiglas 2423. For very bright
ambients, such as indirect sunlight, the 3M Red 655 or
Neutral Density Light Control Film is recommended.

The.HDSP-6300 can be end stacked to form a character
string which is a multiple of a basic eight character
grouping. These devices may be soldered onto a printed
circuit board or inserted into 28 pin DIP LSI sockets. The
socket spacing must allow for device end stacking.
Suitable conditions for wave soldering depend upon the
specific kind of equipment and procedure used. For more
information, consult the local HP Sales Office or HewlettPackard Components, Palo Alto, California.

281

.

18 SEGMENT,
SOLID STATe

·ALPHANUME~tC;

··DISPlAY·.
TECHNICAL DATA MARCH 1980

Features
• ALPHANUMERIC
Displays 64 Character ASCII Set and
Special Characters
• 16 SEGMENT FONT PLUS CENTERED D.P.
AND COLON
• 3.81mm (0.150") CHARACTER HEIGHT
• APPLICATION FLEXIBILITY WITH
PACKAGE DESIGN
4 and 8 Character Dual-In-Llne Packages
End Stackable-On Both Ends for 8 Character and
On One End for 4 Character
Sturdy Gold-Plated Leads on 2.54mm (0.100")
Centers
Environmentally Rugged Package
Common Cathode Configuration

Description
The HDSP-6504 and HDSP-650B are 3.B1mm (0.150")
eighteen segment GaAsP red alphanumeric displays
mounted in 4 character and B character dual-in-line
package configurations that permit mounting on PC
boards or in standard IC sockets. The monolithic light
emitting diode character is magnified by the integral lens
which increases both character size and luminous
intensity, thereby making low power consumption
possible. The rugged package construction, enhanced by
the back fill design, offers extended environmental
capabilities compared to the standard PC board/lens type
of display package. Its temperature cycling capability is
the result of the air gap which exists between the
semiconductor chip/wire bond assembly and the lens. In
addition to the sixteen segments, a centered D.P. and
colon are included. Character spacing yields 4 characters
per inch.

• LOW POWER
As Low as 1.0-1.5mA Average
Per Segment Depending on Peak
Current Levels
• EXCELLENT CHARACTER APPEARANCE
Continuous Segment Font
High On/Off Contrast
6.35mm (0.250") Character Spacing
Excellent Character Alignment
Excellent Readability at 2 Metres

Applications

• SUPPORT ELECTRONICS
Can Be Driven With ROM Decoders and Drivers
Easy Interfacing With Microprocessors and
LSI Circuitry

These alphanumeric displays are attractive for applications such as computer peripherals and terminals,
computer base emergency mobile units, automotive
instrument panels, desk top calculators, in-plant control
eqUipment, hand-held instruments and other products
requiring low power, display compactness and alphanumeric display capability.

• CATEGORIZED FOR LUMINOUS INTENSITY
Assures Uniformity of Light Output From Unit
to Unit Within a Single Category

282

Device Selection Guide

NOTES:
1. Maximum allowed drive conditions for strobed operation are derived from Figures 1 and 2. See electrical section of operational
considerations.
2. Derate linearly above TA = SO°C at 2.17mWfOC. Po Max. (TA = 8S0C) = 62mW.

Electrical/Optical Characteristics at TA ==25°C

NOTES:
3. The luminous intensity ratio between segments within a digit is designed so that each segment will have the same luminous
sterance. Thus each segment will appear with equal brightness to the eye.
4. Operation at peak currents of less than 7mA is not recommended.
S. The dominant wavelength, Ad, is derived from the C.I. E. chromaticity diagram and represents that single wavelength which defines
the color of the device, standard red.

283

1J

200

I-

Z

W

II:
II:

100

""

50

::>

'"
ll'

.
J

1-

20

10

DC
TA - AMBIENT TEMPERATURE - QC

tp -:- PULSE OURATION -p.s

Figure 1. Maximum Allowed Peak Current vs. Pulse Duration. Derate derived
operating conditions above TA =500 C using Figure 2.

Figure 2. Temperature Derating Factor
For Peak Current per Segment vs.
Ambient Temperature. T JMAX =1100 C

,.

'~

<;

~

w
w

>

;::

~

II:

..
I

~

'"

v, -

(PEAK - PEAK SEGMENT CURR ENT - rnA

Figure 3. Relative Luminous Efficiencv
(Luminous I ntensity Per Unit Current)
vs. Peak Segment Current.

PEAK FORWARD VOLTAGE - V

Figure 4. Peak Forward Segment
Current vs. Peak Forward Voltage.

For a Detailed Explanation on the Use of Data Sheet Information and Recommended
Soldering Procedures, See Application Note 1005, Page 464.

o

o

0

2

3

5

4

7

6

8

9

A

C

B

o

E

F

C9RBClJEFGHIJf-

:Eg]%1J

Typical 64 Character ASCII Sat.

o
Additional Character Font

284

*+/
/

L

/

~?

package Dimensions

r

(I~~3~) M A X ' 1 J (.125)
3.18

22

12 _ - , _ - - ,_ _, . ....

r

I

t

10.67
(0.42)

L

21.3'.4
(.840 .02)

(~)TYP.

PIN 1
(NOTE 3)

3,81 ± .25
(.150' .011

3.81 •. 25
(.150' .01)

NOTES,
1. ALL OIMENSIONS IN MILLIMETRES ANO (INCHES).

2. ALL UNTOLERANCED DIMENSIONS ARE FOR REFERENCE ONLY.
3. PIN 1 IDENTIFIED BY INK DOT ADJACENT TO LEAD.

Figure 6. HDSP-6504

Figure 7. HDSP-650S

Magnified Character
Font Description

Device Pin Description
Function

Pin
No.

DEVICES

1

HDSP-6504
HDSP-6508

f

2
3
4

5

r-2.77REF.~

I

"I

(0.109)"2

'~~~A

I

6
7
8
9
10

t

-----rb

·~~~~~~~r
Figure S.

11

12
13

14
15

16
17

18
19
20
21

22
23
24

25
26

285

HDsP~65G8. •

HDSP-6504

Anode
Anode
Segment 91
889mentg,
Anode
Segment DP Anode: .·~ntDP
Cathode Digit 1 ..
Cathode Digif1.
Segment d2
Segment d2
Anode
Anode
Anode' Segment I
Anode
Segment I
Cathode Digit 3
Cathode Digit 3
Anode . Segment e
Segmente
Anode
Anode
Anode
Segment m
Segmenttn
Anode·
Segment k
. Anode'
Segmentl<.
Cathode Digit 4
Cathode Digit 4
Anode
Segment d1
Segment d1
Anode
Anode
Cathode Digit 6
SegmentJ
Anode
Segment Co Cathode . DigitS
Anode
Segmentg2
Cathode Digit 7
Anode
Segment 82 .Cathode DigitS
Segment j
Anode
Segmentj
Anode
cathode Digit 2
Anode
Segment Co
Anode
Segment b . Anode
Segment 92
Segment
Anode
Anode
Segment 82
Anode
Anode
Segment i
Segmentc
Anode
Segment h
Cathode Digit 2
Anode
Segment b
Anode
Segmentf
Anode
Segment al
Anode
Segmentc
Anode
Segment h
Anode
Segment f.

8,

Operational Considerations
ELECTRICAL
The HDSP-6504 and -6508 devices utilize large monolithic
16 segment GaAsP LED chips with centered decimal point
and colon. Like segments of each digit are electrically
interconnected to form an 18 by N array, where N is the
quantity of characters in the display. In the driving scheme
the decimal point or colon is treated as a separate
character with its own time frame. A detailed discussion of
character font capabilities, ASCII code to 18 segment
decoding and display drive techniques appear in
Application Note 1003.
These displays are deSigned specifically for strobed
(multiplexed) operation, with a minimum recommended
time peak forward current per segment of 7mA. Under
normal operating situations the maximum number of
illuminated segments needed to represent a given
character is 10. Therefore, except where noted, the
information presented in this data sheet is for a maximum
of 10 segments illuminated per character:

with the very high segment luminous sterance, provide to
the user a display with excellent readability in bright
ambient light for viewing distances in the range of 2
metres. Effective contrast enhancement can be obtained
by employing any of the following optical filter products:
Panelgraphic: Ruby Red 60, Dark Red 63 or Purple 90;
SGL Homalite: H100-1605 Red or H100-1804 Purple,
Plexiglas 2423. For very bright ambients, such as indirect
sunlight, the 3M Light Control Film is recommended: Red
655, Violet, Purple or Neutral Density.
For those applications requiring only 4 or 8 characters, a
secondary barrel magnifier, HP part number HDSP-6505
(four character) and -6509 (eight character), may be
inserted into support grooves on the primary magnifier.
This secondary magnifier increases the character height
to 4.45mm t 175 inch) without loss of horizontal viewing
angle (see below).

MECHANICAL

The typical forward voltage values, scaled from Figure 4,
should be used for calculating the current limiting resistor
values and typical power dissipation. Expected maximum
VF values for the purpose of driver circuit design may be
calculated using the following VF model:

These devices are constructed by LED die attaching and
wire bonding to a high temperature PC board substrate. A
precision molded plastic lens is attached to the PC board
and the resulting assembly is backfilled with a sealing
epoxy to form an environmentally sealed unit.

VF = 1.85V + IPEAK (1.80)
For: 30m A :S IPEAK :S 200mA
VF = 1.58V + IPEAK (10.70)
For: 10mA :S IPEAK :S 30m A

The four character and eight character devices can be end
stacked to form a character string which is a multiple of a
basic four character grouping. As an example, one -6504
and two -6508 devices will form a 20 character string.
These devices may be soldered onto a printed circuit
board or inserted into 24 and 28 pin DIP LSI sockets. The
socket spacing must allow for device end stacking.

OPTICAL AND CONTRAST
ENHANCEMENT
Each large monolithic chip is pOSitioned under a separate
element of a plastic aspheric magnifying lens, producing a
magnified character height of 3.810mm (.150 inch). The
aspheric lens provides wide included viewing angles of
typically 75 degrees horizontal and 75 degrees vertical
with low off axis distortion. These two features, coupled

Suitable conditions for wave soldering depend upon the
specific kind of equipment and procedure used. For more
information, consult the local HP Sales Office or HewlettPackage Components, Palo Alto, California.

'More than 10 segments may be illuminated in a given character,
provided the maximum allowed character power dissipation,
temperature derated, is not exceeded.

286

OPTIONAL

4 DIGIT MAGNIFIER
HDSP-6505

OPTIONAL
8 DIGIT MAGNIFIER
HDSP-6509
END VIEW
(BOTH)

MOUNTEO ON HDsp·6504

MOUNTED ON HDSP-6508

1. ALL DIMENSIONS IN
MILLIMETRES AND (INCHES).

2. THIS SECONDARY MAGNIFIER
INCREASES THE CHARACTER
HEIGHT TO 4.45mm (.175 in.)

Figure 9. Design Data for Optional Barrel Magnifier in Single Display Applications.

(

287

HEWLETT

PACKARD

18 SEGMENT
ALPHANUMERIC
DISPLAY SYSTEM

I

HDSP-8716
HDSP·8724
HDSP-8132
HDSP-8140

TECHNICAL DATA MARCH 1980

Features
• COMPLETE ALPHANUMERIC DISPLAY
SYSTEM UTILIZING THE HDSP-6508 DISPLAY
• DISPLAYS 64 CHARACTER ASCII SET
• CHOICE OF 16, 24, 32, OR 40 ELEMENT
DISPLAY PANEL
• MULTIPLE DATA ENTRY FORMATS
Left, Right, RAM, or Block Entry
• EDITING FEATURES THAT INCLUDE
CURSOR, BACKSPACE, FORWARDSPACE,
INSERT, DELETE, CARRIAGE RETURN,
AND CLEAR
• DATA OUTPUT CAPABILITY
• SINGLE 5.0 VOLT POWER SUPPLY
• TTL COMPATIBLE
• EASILY INTERFACED TO A KEYBOARD OR
A MICROPROCESSOR

Description
The HDSP-87XX series of alphanumeric display systems
provides the user with a completely supported 18 segment
display panel. These products free the user's system from
display maintenance and minimize the interaction
normally required for alphanumeric displays.

Part Number

Each alphanumeric display system consists of a
preprogrammed microprocessor plus associated logic,
which provides decode, memory, and drive signals
necessary to properly interface a user's system to an
HDSP-6508 display. In addition to these basic display
support operations, the controller accepts data in any of
four data entry formats and incorporates several powerful
editing routines. This microprocessor controller is
mounted behind a Single line display panel consisting of
HDSP-6508 displays matched for luminous intensity.

Description

HOSP-8716

Single-line 16 Character Alphanumeric
Display System utilizing the
HDSP-6508 Display

HDSP-8724

Si ngle-line 24 Character AI phanumeric
Display System utilizing the
HDSP-6508 Display

HDSP-8732

SI ngle-I i ne 32 Character Alphanumeric
Display System utilizing the
HDSP-650B Display

HDSP-8740

These alphanumeric display systems are attractive for
applications such as data entry terminals, instrumentation" electronic typewriters, and other products which
require an easy to use 18 segment alphanumeric display
system.

288

SI ngle-I Ine 40 Character Alphanumeric
Display System utilizing the
HDSP-650B Display

HDSP-8716/-8724/-8732/-8740

Absolute Maximum Ratings

Recommended
Operating Conditions

Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -O.5V to 6.0V
Operating Temperature Range,
Ambient ITA) .........................
Storage Temperature Range ITS) ......

ooe to 70°C
-40°C to 85°C

Voltage Applied to any
Input or Output ...................... -O.5V to 6.0V

Electrical Characteristics OVer operating Temperature Range
I Unless otherwise specified i

NOTES:
1. The luminous intensity ratio between segments within a
digit is designed so that each segment will have the same
luminous sterance. Thus, each segment will appear with
__
equal brightness to the eye.
2. External reset may be initiated by grounding Reset with either
a switch or open collector TTL gate for a minimum time of
50ms. For Power On Reset to function properly, Vee power
supply should turn on at a rate> 100V/S.

3. Momentary peak surge currents may exist on these lines.
However, these momentary currents will not interfere with
proper operation of the HDSP-8716/-8724/"8732/-8740.
4. The dominant wavelength, Ad, is derivedf.rom theC.I.E.
chromatiCity diagram and represents that single wavelength
which defines the color of the device, standard red.
5. All typical values at Vee = 5.0V and TA = 25°C unless
otherwise noted.

289

System Overview
The HDSP-8716/-8724/-8732/-8740 Alphanumeric Display Controllers provide the interface between any ASCII
based Alphanumeric System and the HDSP-8508 Alphanumeric Display. ASCII data is loaded into the system by
means of anyone of four data entry modes - Left, Right,
RAM, or Block Entry. This ASCII data is stored in the
internal RAM memory of the system. The system may also
be expanded to form multiple line panels with system to
system control signals.
The user interfaces to any of the system through eight
DATA IN inputs, six ADDRESS inputs IRAM mode), a
CHIP SELECT input, RESET input, BLANK· input,
EXPAND input, six DATA OUT outputs, a READY output,
DATA VALID output, REFRESH output, and CLOCK
output. A low level on the RESET input clears the display
and initializes the system. A low level on the CHIP

SELECT input causes the system to load data from the
DATA IN and ADDRESS inputs into the system. A special
control word causes the controller to output a STATUS
WORD, CURSOR ADDRESS, and a string of ASCII
characters through the DATA OUT outputs and DATA
VALID output. A low level on the EXPAND input allows
two or more systems to be configured for multiple line
display panels. Pulse width modulation of display
luminous intensity can be provided by connecting
REFRESH to the input of a monostable multivibrator and
the output of the monostable multivibrator to the BLANK
input. A 400kHz clock is provided on the CLOCK output. A
system block diagram for the HDSP-8716/-8724/-8732/8740 systems is shown in Figure 1. The system is designed
to refresh the display at a fixed refresh rate of 100Hz. The
display duty factor is optimized for each display length in
order to maximize light output.

4-------F-------------.

DATA OUT
DATA VALID 4-__________________

~

~:::::::::::::::::::~t-t--I~~~~J

REFRE~4-------------~--~

.iiEiE'f -----_+(
DATA
ENTRY

RAM ADDRESS
DATA IN
CHIP SELECT

----,oL.;..---,F-

-----_+(

READY 4-______

CLOCK - - - - - - -

mANi5 -----_+(
EXPANSION
CONTROL

mT-----_+(
EU-----_+(
Eiii ------<
Arniif

-------<

Figure 1. Block Diagram of the HDSP-8716/-8724/-8732/-8740 Alphanumeric Display System.

Control Mode/Data Entry
User interface to the HDSP-87XX series controller is via an
8-bit word which provides to the controller either a control
word or standard ASCII data input. In addition to this user
provided 8-bit word, two additional control lines, CHIP
SELECT and READY, allow easily generated "handshake"
signals for interface purpo",s,.,.e",s=:.-=:::-::=
A logic low applied to the CHIP SELECT input (minimum
six microseconds) causes the controller to read the 8
DATA IN lines and determine whether a control word or
ASCII data word is present, as determined by the logic
state of the most significant bit (07). If the controller
detects a logic high at 07, the state of Os-Do will define the
data entry mode and appropriate display length.

The 8 bit control data word format is outlined in Figure 2.
For the control word (07 high), bits 05 and 04 define the
selected data entry mode (Left entry, Right entry, etc.) and
bits 03 to Do define display length. Bit Os is ignored.
Control word inputs are first checked to verify that the
control word is valid. If the word is val id, the present state
- next state table shown in Figure 3 is utilized to
determine whether or not to clear the display. RAM entry
can be used as a powerful editing tool or can be used to
preload the cursor. With other transitions, the internal
memory is cleared. The CONTROL WORD 1XXX11 XX2 is
used by the controller to initiate the DATA OUT function.

290

07 °6 0 5°4°3°2°1

DATA ENTRY CONTROL WORD:

x

X

Do

y y Y V DISPLAY LENGTH
1 16 DIGITS
1 24 DIGITS
1 32 DIGITS
1 40 DIGITS

DATA ENTRY MODES
RAM DATA ENTRY

lEFT DATA ENTRY
RIGHT DATA ENTRY
BLOCK DATA ENTRY

0, 0. Os 0, 0, 0,

DATA OUT CONTROL WORD:

HDSP·8716
HDSP-8724
HOSP-8732
HOSP-8740

0, Do
DATA QUT

Figure 2. Control Word Format for the HDSP·8716/-8724/·8732/-8740 Alphanumeric Display System.

R:~~it~ 1------------~~lEAR, OFFSCREEN CURSOR
CLEAR. BLINKING
CURSOR

<=

==

DISPLAY LENGTH

~

CLEAR,OFFSCREEN

0016

CLEAR,

CURSOR = DISPLAY LENGTH

BLINKING CURSOR = 00'6
CURSOR BECOMES INVISIBLE

CLEAR,

BLINKING
CURSOR =
00 16
HOME CURSOR
AND CLEAR

(

CLEAR, INVISIBLE
CURSOR = 00"

Figure 3. Present State-Next State Diagram for the HDSP-8716/-8724/·8732/-8740 Alphanumeric Display System.

DATA WORD:
ASCII ASSIGNMENT

as
LF
HT
CR
US
DEL
VT
FF
RS

0, D. Os 0, 0 3 0,
1 01 X X
0
0
0
0
0
1
0
0
0

0
0
0
0
0
1
0
0
0

0, Do

xxxxxi
0
0
0
0
1
1
0
0
1

0
0
0
1
1
1
0
1
1

0
0
1
1
1
1
1
0
0

BACKSPACE

CLEAR (NEW LlNE*j
FORWAROSPACE
CARRIAGE RETURN
INSERT CHARACTER
DELETE CHARACTER
CURSOR DOWN
HOME & CLEAR
CURSOR UP

}RIGHT

}'"

OTHERWISE, THE 7 BIT ASCII CODE

Figure 4. Display Commands for the HDSP-8716/-8724/·8732/·8740 Alphanumeric Display System.

291

SINGLE

}'"

EXPAND·

If 07 is a logic low when the DATA IN lines are read, the
controller will interpret 06-00 as standard ASCII data to be
stored, decoded, and disp'iayed. The system accepts the
standard 7-bit ASCII code. However, the HDSP-87XX
system displays only the 64 character subset 12016 I space I
to 5F16 1111 and ignores all ASCII characters outside this
subset with the exception of those characters defined as
display commands. These display commands are shown
in Figure 4. The displayed character set for the HDSP87XX system is shown in Figure 5.

BITS

06 05 04

o ,
o ,

D,
D,
D,
Do

0
0
0
0

HEX

0

,
, , 0

(space)

0

0
0
0

,

,
I

I

[E R

,

0

0

4

,

0

,

• P Q

Regardless of whether a control word or ASCII data word
is presented by the user, a READY signal is generated by
the controller after the input word is processed. This
READY signal goes low for 35",s and upon a positive
transition, a new CHIP SELECT may be accepted by the
controller. Data Entry Timing is shown in Figure 6.

,, , ,, ,,
, ,
• •
I 9] % l
[1 j y 5 6
B [ IJ E F
R 5 T U V
0
0

,
0

0
0

0

0

0
0

0

0

0

,, , , ,, ,, ,, ,, ,,, ,,,
,
,
,
,
,
0

4

II

0
0
0

0
0

7

8

9

I

< >

0

0

0

•

A

+
9 *

l

8

G

H I

I

0
0

0

C

D

0

I

-

L

--

E

-'

F

/
?

J k L M N 0

WX Y Z

[

J 7'

\

~

Figure 5. Display Font for the HDSP-B716/-B724/-B732/-B740 Alphanumeric Display System_
DATA ENTRY TIMING

RAM ADDRESS

I·

-I

ADDRESS HOLD TIME

~10MSMAX.

E::

DATA HOLD TIME-::-3

.'Il--

DATA ENTRY TIME

II

READY

i+-35ps

2.Sps

*

-l

CELECT=O
AFTER THIS TIME,
CONTROLLER WILL
ENTER NEXT CHARACTER.

MAXIMUM DATA ENTRY TIMES OVER OPERATING TEMPERATURE RANGE

DATA ENTRY O:cMA"=0TD:c:'--+=-:-.----_7"'"_,;;;...;=~_,_c:-__,__,_"-=--'---____1
HOl.O tIME"

LH'r,
SING.t.E
LHT,

""',

E){PANDItD 25u$

RIGHT

2';'''

"AM
BLOCK
CONTROl.

~}l$

DATA OUT

2'",

25M 145#:lH
2!;;"

"MINIMUM TIME THAT DATA INPUTS MUST REMAIN VALlO AFTER CHIP SELECT GOES LOW.
HMINIMUM TIME THAT RAM ADDRESS INPUTS MUST REMAIN VALID AFTER CHIP SELECT GOES LOW.

Figure 6. Data Entry Timing and Data Entry Times for the HDSP-B716/-B724/-B732/-B740 Alphanumeric Display System_

292

Left Entry Mode

allows several HDSP-87XX systems to be connected in~
multiple line panel. Expanded Left entry uses the ERI
input, ELI input, LEFT input, and ACTIVE output to
provide a handshake between each system as shown in
Figure 7. With the proper connections, the cursor can be
moved in a circular fashion from the end of the last line to
the beginning of the first line, or such that it shifts
offscreen and is lost until the next CLEAR/HOME display
command. Expanded Left entry adds three display
commands: CURSOR UP moves the cursor to the same
location in the preceeding line; CURSOR DOWN moves
the cursor to the same location in the following line;
CLEAR/HOME loads all displays with spaces and resets
the cursor to the leftmost display location in the first line.
The CLEAR command in Left entry mode is replaced by
the LINE FEED function. LINE FEED moves the cursor to
the leftmost display location in the following line leaving
the current line unchanged.

With Left entry, characters are entered in typewriter
fashion, i.e., to the right of all previous characters. Left
entry uses a blinking cursor to indicate the location where
the next character is to be entered. CLEAR loads the
display with spaces and resets the cursor to the leftmost
display location. BACKSPACE and FORWARDSPACE
move the cursor without changing the character string.
Thus, the user can backspace to the character to be
edited, enter a character and then forwards pace the
cursor. CARRIAGE RETURN resets the cursor to the
leftmost display location leaving the display unchanged.
The DELETE function deletes the displayed character at
the cursor location and then shifts the character string
following the cursor one location to the left to fill the void
of the deleted character. The I NSERT CHARACTER sets a
flag inside the system that causes subse'quent ASCII
characters to be inserted to the left of the character at the
cursor location. As new characters are entered, the
cursor, the character at the cursor, and all characters to
the right of the cursor are shifted one location to the right.
The INSERT function is terminated by a second INSERT
CHARACTER, or by BACKSPACE, FORWARDSPACE,
CLEAR, CARRIAGE RETURN, or DELETE. In Left entry
mode, after the display is filled, the system ignores all
characters except BACKSPACE, CARRIAGE RETURN,
and CLEAR. The system allows the cursor to be
positioned only in the region between the leftmost display
character and immediately to the right loffscreen I of the
rightmost display character.

Right Entry Mode
In Right entry mode, characters are entered at the right
hand side of the display and shifted to the left as new
characters are entered. I n this mode, the system stores 48
ASCII characters, although only the last characters
entered are displayed. CLEAR loads the display with
spaces. BACKSPACE shifts the display one location to the
right, deleting the last character entered and displaying
the next character in the 48 character buffer. Right entry
mode is a simple means to implement the walking or
"Times-Square" display. In this mode, the cursor is
located immediately to the right I offscreen) of the
rightmost displayed character.

Expanded Left entry is selected by grounding the
EXPAND input prior to RESET. Expanded Left entry mode

FIRST LINE

LAST LINE

U

U
ALLOWS DATA ENTRY, HT, LF, INSERT, VT
TO GO FROM LAST LINE TO FIRST LINE

I-----------~--------------l

(

I

j-----------------r-------------i

ALLOWSBS, RS TO GO FROM

I

I

FIRST LINE TO LAST LINE

i

~

I

I

I

I
I
I
1

I
I

I

I

L -

9

rn

ACT

'3

ACT

r - 4 - + - " ' - - I ERI

9

13

_
ERI

ACT t-'3-4_,1_9-t rn

ACT' ~

~m

f :::r
11

01

DATA

vee...22... LEl'T

.---

0:00V

t_2

CS R'

EXP
01

vee.....22..
DO

t---

C'S D~ t--

t

-=-

vee.....22.. LEl'T

lEFT

100'
01

CS

DO

r--

t

Ow

t--

-=-

EXP
01

,N--4-+11-+-+-+--41_t-+I-t-+---+-l-tl---t---r--t-~J
1
1

DO

t--- DATA OUT

CS O~ t--- OATAVAliO

J

CHIP SELECT
RESET

DATA OUT
DATA VALID

DATA OUT
DATA VALID

DATA OUT
DATA VALID

Figure 7. External Connections for Expanded Left Entry Mode for the HDSP-8716/-8724/-8732/-8740 Alphanumeric Display System_

293

Block Entry Mode
Block entry al!ows the fastest data entry rate of all four
modes. I n this mode, characters are loaded from left to
right as with Left entry. However, with Block entry, after
the display is completely loaded, the next ASCII character
is loaded in the leftmost display location, replacing the
previous displayed character. While Block entry has a
non-visible cursor, the cursor is always loaded with the
address of the next character to be entered. The display
can be cleared and the cursor reset to the leftmost display
location by loading in a new BLOCK control word.

RAM Entry Mode
In RAM entry, ASCII characters are loaded at the address
specified by the six bit RAM address. Regardless of
display length, address 00 is the leftmost display
character. Out of range RAM addresses are ignored. While
RAM entry has a non-visible cursor, the cursor is always

preloaded with the address to the right of the last
character entered. This allows the cursor to be preloaded
with an address prior to going into any other entry mode.
The display can be cleared by loading in a new RAM
control word.

Power-On Reset/Re;;;!
When power is first applied to the system, the system
clears the display and tests the state of the DATA INPUT,
D7. If D7 > 2.0V, the system loads the control word on the
DATA INPUTS into the system. If D7  100 Vis. In addition.
the system can be reset by pulling the RESET input low for
a minimum of 50 milliseconds. POWER-ON RESET/
RESET timing is shown in Figure 9.

appropriate control word or provide a control word during
POWER-ON RESET/RESET. The circuit shown in Figure
10 can be used to load any desired preprogrammed
control word into the HDSP-87XX Series Display
Controller during POWER-ON RESET/RESET.

If some entry mode or display length is desired other than
40 character Left entry, it is necessary to either load the

I"'''''

--------50m'MIN---------,

READY

I
-+....I

L.._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

t:

2 .5 iJ. S *
'IF CHIP SELECT

=

0

AFTER THIS TIME,
CONTROLLER WILL
,.~_....;;EN;,;.;TER A CHARACTER.
READS IN CONTROL WORD

DATA INPUT, D7

INITIALIZES AS LEFT ENTRY
MODE. 40 CHARACTER DISPLAY
LENGTH

Figure 9. POWER-ON RESET/FiESE'f Timing for the HDSP-8716/-8724/-8732/-8740 Alphanumeric Display System.

DESIRED MODE, XX [

------...:;:-

DI7------.:.::.
DI6------=
DI5------...:;:DI 4 - - - - - - : " -

(
DESIRED [

L;~~~H.

++...:;:-

____

----if--+.,:;DI 3
DI 2
DI 1

----++.:.::.

----f-+-'-=-

----++-::-

xx
00
01
10
11

RAM
LEFT
RIGHT
BLOCK

YYYY
0011
0101
0111
1001

16 DIGITS
24 DIGITS
32 DIGITS
40 DIGITS

Figure 10. External Circuitry to Load a Control Word into the HDSP·8716/-8724/·8732/-8740 Alphanumeric Display System
Upon POWER·ON RESET/RESET.

295

Data Out

Luminous Intensity Modulation

Data stored in the HDSP-87XX system is available to the
user upon command. Data Out is initiated by the control
word 1 XXXll XX2. Following this control word, the system
outputs a STATUS WORD, CURSOR ADDRESS, and a
string of ASCII data characters. The STATUS WORD
specifies the data entry mode and the display length of the
system. The STATUS WORD is the same format as a valid
control word with 07 and 06 deleted. The CURSOR
ADDRESS specifies the location of the cursor within the
display. The CURSOR ADDRESS of the leftmost display
location is address 00. In Expanded Left entry mode, a
CURSOR ADDRESS of 63 (3F161 is used to indicate a nonactive line. The system outputs the same numberof ASCII
data characters as the display length specified by the
control word. The first ASCII data character is always the
leftmost display character. The positive edge of the DATA
VAll 0 output can be used to load the DATA OUTPUT
words into the user's system. The DATA OUT timing for
the HDSP-87XX systems is summarized in Figure 11.

Pulse width modulation of display luminous intensity can
be provided by connecting the REFRESH output of the
system to the input of a monostable multivibrator. The
output of the monostable multivibrator should then be
connected to the BLANK input of the system. Modulation
of display luminous intensity is then achieved by varying
the delay of the monostable multivibrator with a
potentiometer or photoresistor. REFRESH is repeated at a
rate of 10ms divided by the configured display length. For
example, an HDSP-8732 system, when configured for a 32
character display length, would pulse the REFRESH
output every 312.5I's. The circuit shown in Figure 12 may
be utilized to provide manual control of display luminous
intensity. Automatic control may be achieved by
substituting an appropriate value photoconductor for
potentiometer R1. If luminous intensity modulation is not
desired, BLANK should be left open.

CHIP SELECT

L
---j 1---2.5P'-

i-S"'MIN
READY

DATA VALID

* IF CHIP SELECT'" 0 AFTER THIS TIME,
CONTROLLER WILL ENTER NEXT
CHARACTER

DATA OUT

WORD

ADDRESS

(AI

(BI

STATUS WORD FORMAT (A)

CHARACTER

(11

CHARACTER (N)

CURSOR ADDRESS FORMAT (8)
CURSOR ADDRESS,;: NO. OF CHARACTERS
FROM THE LEFT

RAM ENTRY
LEFT ENTRY
RIGHT ENTRY
BLOCK ENTRY

y y y Y = DISPLAY LENGTH

DATA WORD FORMAT (1 - N)
LOWEST 6 BITS OF ASCII CODE
WORD (1) '" LEFTMOST DISPLAY CHARACTER
WORD (N) = RIGHTMOST DISPLAY CHARACTER

HOSP

N

-8716

16

-8724

24

-8732

32

-8740

40

Figure 11. Data Out Timing and Format for the HDSP-8716/-8724/-8732/-8740 Alphanumeric Display System.

296

vee

Microprocessor Interface

Interfacing the HDSP-87XX Series Display System to
microprocessor systems depends on the needs of the
particular application. Figure 13 shows a latched interface
between the host microprocessor and the HDSP-87XX
system. The latch provides temporary storage to avoid
making the host microprocessor wait for the system to
accept data. Data from the host microprocessor system is
loaded into the 74LS273 octal register on the positive
transition of the clock input I pin 11 '. At the same time, the
CHIP SELECT input is forced low. The CHIP SELECT
input stays low until READY goes low. The host microprocessor should avoid loading new data into the 74LS273
as long as BUSY is high. The latched interface can be
implemented with an octal register and SR flip-flop if the
HDSP-87XX system is operated in Left, Right, or Block
entry. RAM entry requires an additional register for the
RAM address inputs. Additional flexibility can be achieved
by using a peripheral interface adapter I PIA, to interface
the HDSP-87XX system to the host microprocessor
system. The PIA provides a data entry handshake between
the host microprocessor system and the HDSP-87XX
system and allows the host microprocessor system to read
the Data Output port of the HDSP-87XX system.

50K
R1

4.7K

C '" .033J.jF
C
,022jJF

=

C '" .015J1F

HDSP-8716
HOSP-8724
HDSP-8732/-B740

Figure 12. External Circuitry to Vary the Luminous Intensity of the
HDSP-8716/-8724/-8732/-8740 Alphanumeric Display System.

aOSOA INTERFACE

6800 INTERFACE

VMA

(

3

"2

cs'

[

v"
01 7
O.le

Os

",

DATA
BUS

05

P'!;'.

D.
03

0'4
013

O2

0,

DO

*CS IS A LOGICAL COMBINATION OF HIGH ORDER ADDRESS BITS THAT DISTINGUISH
THE ADDRESS OF THE HDSP-8716/-S724/-8732/-8740 FROM THE REST OF THE
MICROPROCESSOR SYSTEM.

Figure 13. Latched Interface to the HDSP-87XX Series Alphanumeric Display System.

297

package Dimensions
1 _ - - - - - - - - - ' 4 8 . 5 9 '.254 _ _ _ _ _ _ _-<
15.8501 '.010

/-TIBBi

!r~
(.4!iO)±.Ol0

4.175

DIA 4 PLC

t.

1
I

50.08 '.254

IT

58.42 '.508
12.3001 ,.020

!

:.~:;I DIA 4 PLC

1.0--_ _ _ _ _ _ _ _ _ _ _ '6'.64'.508 _ _ _ _ _ _ _ _~
16.6001 L020

HDSP-8716

~---------:::.~::.~~--------~
~--------::~~:.~~------~~
~-~~~~----~!:~------~-4-~

58.42 ±.50'
(2.300 ± .020

1
~

:.',0,2;1 DIA 4 PLC

~----I;~~!I-----.j·1

1--_ _ _ _ _ _ _ _ _ _ '6'.64 '.508 _ _ _ _ _ _ _ _ _-.
16.6001 ±.020

HDSp·8724

~------------~~:~:~%-------------~

;:,'::1 DIA 4 PLC

58.42 .. 508
12.3001 •.020

i
~

_ _ _ _ _ _ _ _ _~_ _ _ _ _ 218.44 _.508 _ _ _ _ _ _ _ _ _ _ _ _ _..1
18.6001' .020

HDSp·8732

298

Package Dimensions

j.m u..,
281.62<.254
(10.31101,.010

148.59 ±.254
16.B60It.Ol0

3.Bl'.50B
(.,501t'.OID

-,

I

r9~05
1.1501

--

~-

50.0B ,.254

01'.010
~

_

(.1111

137.16 :1:.254
(6AOOI,.010-

_11.43'.254
1.4501'.010

(.1111
3.123 DIA BPLC: \

~~

~
~
r, .
~..J

l

---<

,

.~~

--(0

I

58.42,.501
(2.3001 ••D20

1

I.

.

t

136.13
1 - - - 1 ._ ( 5 . 3 2 1 _

"

_ _

~

(!:~1~.1.1

I---------------(~:~~:I±;~~----------------------..I
..

HDSP-8740

r-~-A

B.l

Uc::
(~!j~1 ~:~~~m~J~oo
~
i

f

i'

l

'0.1J

i

~_~IA~21____________________________~U

_

..

A

~----------~~;:::~~-------~~--11-~-±2-54-----:~~1:~~-------~

~:I DIA4PLC

HDlINl1B
HDIIN124

161.14
(&.1001
218A4

B

HDSP-1132

C

289.24
HDIP·8140 (li.iii)

lB.iii)

(.4501t .01 D

-0

f
~------------~~.=)----------~
_ _ _ __

1~_ _ _ _ _ _ _ _ _ _ _·,81.84t.5D9

,..

(8.Bl1Dl,.lZO

PIN
1
2
3
4
6
8
1

CONNECTORS
fUNCTION
CONTROL/DATA
ENTRV
PDWERIII

TVPE OF
CONNECTOR
34 PIN
RIB90N CABLE
3 PIN WITH
LOCKING RAMP

SUGGESTED
MANUfACTURER
3M PIN 3414·XOOO SERIES

••

MOLEX PIN 09·50·3031
WITH 08·60·01 DB
TERMINALS

'0
11
12
13
14
11
18

NOTES: (1IPOWER LEADS SHOULD IE '8-20 GAUGE STRANDED MRE.

17

H DSP-8716/-8724/-87321-8740

299

DESCRIPTION
RAM ADDRESS. A.
EXPAND
RAM ADDREss, A,
CHIP SELECT
RAM ADDREss, A,
DATA IN. Do
RAM ADDREss, A3 (ELI)
DATA IN. 0,
RAM ADDREss, As (ERl)
DATA IN. 0,
RAM ADDREss, As (LEFT)
DATA IN. 0,
ACTIVE
DATA IN.

PIN
II
11
28
21·
22

iiEI£f

32

a.

DATA IN. lis
NO CONNECTION

23
24
25

ZB
27
21
29

30
31

33
34

DESCRIPTION
DATA IN. lit
NO CONNECTION
DAtA IN. 0,
NO CONNEcnDN
DATA OUT. DO.
DATA OUT. DO,
DATA OUT. DO,
DATA OUT. DO,
DATA OUT. DOc
DATA OUT. Oils
READY
DATA VALID
400 kHz CLOCK OUT
. REFRESH
NO CONNECTION
DISPLAY 8LANK
NO CONNECTION

TECHNICAL DATA MARCH 1980

Features
• 5

x 7 LED

MATRIX CHARACTER
Human Factors Engineered

• BRIGHTNESS CONTROLLABLE
• IC COMPATIBLE
• SMALL SIZE
Standard 1S.24mm (.600 Inch) Dual In-Line
Package; 6.9mm (.27 Inch) Character Height
• WIDE VIEWING ANGLE
• RUGGED, SHOCK RESISTANT
Hermetically Sealed
Designed to Meet MIL Standards
• LONG OPERATING LIFE

Description
The Hewlett·Packard 5082-7100 Series is an X-V addressable, 5 x 7 LED Matrix capable of displaying the
full alphanumeric character set. This alphanumeric indicator series is available in 3, 4, or 5 character endstackable clusters. The clusters permit compact presentation of information, ease of character alignment,
minimum number of interconnections, and compatibility with multiplexing driving schemes.
Alphanumeric applications include computer terminals, calculators, military equipment and space flight
readouts.
The 5082-7100 is a three character cluster.
The 5082-7101 is a four character cluster.
The 5082-7102 is a five character cluster.

Absolute Maximum Ratings
·"'ameter
Peak Forward Cun'entPer LED.
U)"ration
.

<: 1 ms)

Averag&c~ent Per LED
Power Dissipation Pel'
. Charaeter(p,lIdiodes lit) (1)
Operating T.emperature, Case

Reverse Voltage Per LED
Note 1: At 25°C Case Temperature; derate 8.5mWf'C above 25°C.

300

Electrical/Optical Characteristics at Tc =25°C
Parameter
Peak Luminous I ntensity Per LED
(Character Average) @ Pulse
Current of 100mA/LED

Symbol

Mj".Typ.

I" {PEAKl

1.02.2

Reverse Current Per LED @ VR = 4V
Peak Forward Voltage @ Pulse
Current of SOmA/LEO
Peak Wavelength
Spectral Line Halfwidth



Description

'.""~"

ANODEI Z
1

::-... Va:

15
'4 VOl

~

4

CATMODE! 5
ANODE;.
}

•

"

~

12 V02

":/
GNU

11
10

•

:::-....

3
4
5
6
1
8

":

14

. . . . . . ::
/

13
12
11

Vet

~

~,~

15

10
9

//

-;.

15
14
13
12
11
10
9

Withstand
Test
Vohage

Page
No.

10mA

1500Vdc

90

Hermetically Sealed
Package Containing
4 Low Input Current,
High Gain Optocouplers
SN140TXV TXV - Hi· Rei
Screened
TXVB - Hi· Rei
SN140TXVB Screened with
Group B Data

Line Receiver, Low
Power Ground
Isolation for High
Reliability Systems

300k bit/s

300% Min.

0.5mA

1500Vdc

94

Dual Channel
Hermetically Sealed
Analog Optical
Coupler
4N55TXV TXV - Hi· Rei
Screened
TXVB - Hi·Rel
4N55TXVB Screened with
Group B Data

Line Receiver,
Analog Signal
Ground Isolation,
Switching Power
Supply Feedback
Element

700k bit/s

7% Min.

16mA

1500Vdc

98

4N55

.~"

2
3
4
5
6
1
8

Specified
Input
Current

Line Receiver,
Ground Isolation for
High Reliability
Systems

6N140

'~"

2

Current
Transfer
Ratio

Dual Channel
Hermetically Sealed
Optically Coupled
Logic Gate .
TXV - Screened
SN134TXV
TXVB - Screened
with Group B
Data
SN134TXVB
SN134

.

Typical
Data Rate
(NRZ)

Application

10M bit/s 400% Typ.

Hermetically Sealed Integrated LED Displays
Device

rn
.EH

ITD

[
[

5082·7010
5082·7011
5082·7391

5082·7392

5082·7395
5082·7393

Application

Description

Package

S.8mm (.27") 5x7 Single Digit
Numeric, LHDP, Built·ln
Decoder/Driver
S.8mm (.21") Plus/Minus
Sign

8 Pin Hermetic
2.54mm (.100") Pin
Centers

• Ground, Airborne,
Shipboard Equipment
• Fire Control Systems
• Space Flight Systems

7.4mm (.29") 4x7 Single Digit
Numeric, RHDP, Built·ln
Decoder/Driver/Memory
7.4mm(.29") 4x7 Single Digit
Numeric, LHDP, Built·ln
Decoder/Driver/Memory
7.4mm(.29") 4x7 Single Digit
Hexadecimal, Built·ln
Decoder/Driver/Memory

8 Pin Hermetic
15.2mm (.S") DIP
with Gold Plated Leads

• Ground, Airborne,
Shipboard Equipment
• Fire Control Systems
• Space Flight Systems
• Other High Reliability
Applications

7.4mm(.29") Overrange
Character Plus/Minus Sign

247

I

NOTES: 1. 8% is the off-axis angle at which the luminous intensity is half the axial luminous intensity.
2.
3.
4.
5.

Page
No.
241

Peak Wavelength.
For Panel Mounting Kit, see page 171.
PC Board Mountable.
Military Approved and qualified for High Reliability Applications.

309

For Applications Information,
see page 311.

,:. ..

·310

';~pJ,icatipns

Information·.
.

....

'.

'.

:

..

Below is a complete listing of al/ of the Optoelectronic Applications Information available. For those items
which were not included in this catalog, a brief abstract is shown. These are available in their entirety from your
local HP Sales Office or nearest HP Components Franchised Distributor or Representative.

Model/Pub. No.
(Date)

(-

APPLICATION NOTES

APPLICATION BULLETINS

Model/Pub. No.
(Date)

DeSCription

Ref.

Description

Ref.

AB-l/5952-8378
(1/75)

Construction and Performance
of High Efficiency Red, Yellow
and Green LED Materials

Abs!.

AN-915/5953-0431
(4/80)

Threshold Detection of Visible
and .Infrared Radiation with
PIN Photodiodes

P. 326

AB-3/5952-8380
(3/75)

Soldering Hewlett-Packard
Silver Plated Lead Framed
LED Devices

P. 315

AN-931/5952-0235
(11/70)

Solid State Alphanumeric
Display, Decoder/Driver
Circuitry

Abs!.

AB-4/5952-8381
(4/75)

Detection and Indication of
Segment Failures in 7-Segment
LED Displays

Abs!.

AN-934/5952-0337
(11172)

5082-7300 Series Solid State
Display Installation
Techniques

Abst.

AB-52/5953-0330
(3/77)

Large Monolithic LED
Displays

Abs!.

AN-937/5952-0396
(5/73)

Abs!.

AB-54/5953-0363
(7/77)

Mechanical Handling of Subminiature LED Lamps and
Arrays

Abst.

Monolithic 7-Segment LED
Display Installation
Techniques

AN-939/5952-0331
(11172)

High Speed Optically Coupled
Isolators

Abs!.

AB-56/5953-0415
(11179)

Interface Timing and Display
Length Expansion Information
for the HDSP-2000 Coded
Data Controller

P. 319

AN-941/5952-0418
(9173)

5082-7700 Series 7-Segment
Display Applications

P. 332

AN-945/5952-0420
(10173)

Photometry of Red LEDs

Abs!.

Flux Budget Considerations
for Fiber OptiC Link Design

P. 323

AN-946/5952-0429
(11173)

5082-7430 Series Monolithic
7-Segment Displays

Abs!.

AN-94 7/5952-8497
(7/76)

Digital Data Transmission
Using Optically Coupled
Isolators

Abs!.

AN-948/5952-0458
(3/74)

Performance of the 50824350/51/60 Series of Isolators
in Short to Moderate Length
Digital Data Transmission
Systems

P.343

AB-57/5953-0418
(1/80)

APPLICATIONS MANUAL
Model/Pub. No.
(Date)
HPBK-l000
McGraw-Hili
(No. 0-07-028605-1)
(1977)

Description
Optoelectronics Applications
Manual

Ref.
Abs!.

312

AN-951-1/5953-0413 Applications for Low Input
(11/79)
Current, High Gain Optically
Coupled Isolators

P.352

AN-951-2/5952-8451
(5/76)

Linear Applications of
Optically Coupled Isolators

P. 356

AN-964/5952-8345
(3/75)

Contrast Enhancement
Techniques

P.

AN-966/5953-0427
(2/80)

Applications of the HDSP-2000
Alphanumeric Display

P.368

AN-l000/5953-0391
(11178)

Digital Data Transmission
with the HP Fiber Optic
System

P.380

AN-l00l/5953-0384
(10/78)

Interfacing the HDSP-2000
to Microprocessor Systems

P.398

AN-l002/5953-0385
(6/79)

Consideration of CTR
Variations in Optically Coupled
Isolator Circuit Designs

P. 414

AN-l003/5953-0405
(9/79)

Interfacing 18-Segment
Displays to Microprocessors

P.430

AN-l004/5953-0406
(11179)

Threshold Sensing for Industrial Control Systems with the
HCPL-3700 Interface
Optocoupler

P. 450

AN-l005/5953-0419
(3/80)

Operational Considerations
for LED Lamps and Display
Devices

P.464

360(-~'

Abstracts
APPLICATION BULLETIN 1
Construction and Performance of High Efficiency Red, Yellow and Green LED Materials
The high luminous efficiency of HewlettPackard's High Efficiency Red, Yellow and
Green lamps and displays is made possible by
a new kind of light emitting material utilizing a
GaP transparent substrate. This application
bulletin discusses the construction and
performance of this material as compared to
standard red GaAsP and red GaP materials.
APPLICATION BULLETIN 4
Detection and Indication of Segment Failures
in Seven Segment LED Displays
The occurrence of a segment failure in certain
applications of seven segment displays can
have serious consequences if a resultant
erroneous message is read by the viewer. This
application bulletin discusses three techniques
for detecting open segment lines and
presenting this information to the viewer.
APPLICATION BULLETIN 52
Large Monolithic LED Displays

(

The trend to incorporate more complex
functions into smaller package configurations
that are portable and battery powered is
reaching a point where the limiting items are
the space and power constraints imposed upon
the display at the operator-to-machine
interface. The large monolithic LED display
nas been designed to meet many of these
constraints. This application bulletin describes
the beneficial features of a large monolithic
LED display and presents circuits which
interface the display to CMOS logic and to a
microprocessor.
APPLICATION BULLETIN 54
Mechanical Handling of Subminiature LED
Lamps and Arrays
The Need for Careful Mechanical Handling
Hewlett-Packard manufactures a series of
individual LED lamps and lamp arrays that are
very small epoxy encapsulated devices. These
devices are classified as having a
SUBMINIATURE package configuration. When
carefully installed on a printed circuit board,
these devices will reliably function with a long
predictable operating life.

To obtain long operating life, these
subminiature devices must be carefully
installed on the printed circuit board in such a
manner as to insure the integrity of the
encapsulating epoxy. This will in turn maintain
the integrity of the device by not permitting
mechanical and thermal stresses to induce
strains on the LED die attach and wire bonds
which may cause failure.
This application bulletin describes the
subminiature package assembly, the package's
mechanical limitations and offers specific
suggestions for proper installation.
APPLICATION NOTE 931
Solid State Alphanumeric Display ... Decoderl
Driver Circuitry
Hewlett-Packard offers a series of solid state
displays capable of producing multiple
alphanumeric characters utilizing 5 x 7 dot
arrays of GaAsP light emitting diodes (LED's).
These 5 x 7 dot arrays exhibit clear, easily read
characters. In addition, each array is X-Y
addressable to allow for a simple addressing,
decoding, and driving scheme between the
display module and external logic.
Methods of addressing, decoding and driving
information to such an X-Y addressable matrix
are covered in detail in this application note.
The note starts with a general definition of the
scanning or strobing technique used for this
simplified addressing and then proceeds to
describe horizontal and vertical strobing.
Finally, a detailed circuit description is given
for a practical vertical strobing application.
APPLICATION NOTE 934
5082-7300 Series Solid State Display
Installation Techniques
The 5082-7300 series Numeric/Hexadecimal indicators are an excellent solution to most
standard display problems in commercial, industrial and military applications. The unit
integrates the display character and associated
drive electronics in a single package. This
advantage allows for space, pin and labor cost
reductions, at the same time improving overall
reliability.
The information presented in this note
describes general methods of incorporating the
-7300 into varied applications.

313

1. What to measure (definitions of terms)
2. How to measure it (apparatus arrang'ement)
3. Whose equipment to use (criteria for
selection)

Abstracts
APPLICATION NOTE 937
Monolithic Seven Segment LED Display
Installation Techniques

APPLICATION NOTE 947
Digital Data Transmission Using Optically
Coupled Isolators

The Hewlett-Packard series of small endstackable monolithic GaAsP displays are
designed for strobing, a drive method that
allows time sharing of the character generator
among the digits in a display.

Optically coupled isolators make ideal line
receivers for digital data transmission
applications. They are especially useful for
elimination of common mode interference
between two isolated data transmission
systems. This application note describes
design considerations and circuit techniques
with special emphasis on selection of line
drivers, transmission lines, and line receiver
termination for optimum data rate and
common m-ode rejection. Both resistive and
active terminations are described in detail.
Specific techniques are described for
multiplexing applications, and for common
mode rejection and data rate enhancement.

This Application Note begins with an
explanation of the strobing technique, followed
by a discussion of the uses and advantages of
the right hand and center decimal point
products.
Several circuits are given for typical applications. Finally, a discussion of interfacing to
various data forms is presented along with
comments on mounting the displays.
APPLICATION NOTE 939
High Speed Optically Coupled Isolators

Often designers are faced with the problem of
providing circuit isolation in order to prevent
ground loops and common mode signals.
Typical devices for doing this have been
relays, transformers and line receivers.
However, both relays and transformers are low
speed devices, incompatible with modern logic
circuits. Line receiver circuits are fast enough,
but are limited to a common mode voltage of 3
volts.

OPTOELECTRONICS APPLICATIONS
MANUAL (HPBK-1000)

The commercial availability of the Light
Emitting Diode has provided electronic system designers with a revolutionary component
for application in the areas of information
display and photocouplers.

In addition, they do not protect very well
against ground loop signals. Now Optically
Coupled Isolators are available which solve
most isolation problems.

Many electronic engineers have encountered
the need for a resource of information about .
the application of and designing with LED· _._
products. This book is intended to serve as an
engineering guide to the use of a wide range of
solid state optoelectronic products.

This Application Note contains a description of
Hewlett-Packard's high speed isolators, and
discusses their applications in digital and
analog systems.
APPLICATION NOTE 945
Photometry of Red LEOs

The book is divided into chapters covering
each of the generalized LED product types.
Additional chapters treat such peripheral
information as contrast enhancement techniques, photometry and radiometry, LED
reliability, mechanical considerations of LED
devices, photodiodes and LED theory.

Nearly all LEOs are used either as discrete
indicator lamps or as elements of a segmented
or dot-matrix display. As such, they are viewed
directly by human viewers, so the primary
criteria for determining their performance is
the judgment of a viewer. Equipment for
measuring LED light output should, therefore,
simulate human vision.

This book can be purchased from a HewlettPackard franchised distributor or from the
McGraw-Hili Publishing Company. A complete listing of all HP Components franchised
distributors can be found on pages 472-474.

This Application Note will provide answers to
these questions:

314

:SOId8ri09

PIU11U

··'SilwrJ>tated·le(){rF_,~ .'_. '~j'.
INTRODUCTION

the solderability. As the density of the tarnish increases,
the more active the flux must be to penetrate and remove
the tarnish layer. Some recommended fluxes and
cleaner/surface conditions are discussed in the "Solder,
Flux and Cleaners" section.

Since the price of gold has increased several times over
past years, the cost of a gold plated lead frame has
increased substantially above the cost of a silver plated
lead frame. The impact of this increase in cost has been
industry wide.

STORAGE AND HANDLING

By using silver plating, no additional manufacturing
process steps are required. Silver has excellent electrical
conductivity. LED die attach and wire bonding to a silver
lead frame is accomplished with the same reliability as
with a gold lead frame. Also, soldering to a silver lead
frame provides a reliable electrical and mechanical solder
joint. Soldering silver plated lead frame LED devices into a
printed circuit board is not more complicated than
soldering LED devices with gold plated lead frames. This
application bulletin offers some suggestions on how to
solder HP silver plated lead frame LED devices.

The best technique for insuring good solderability of a
silver plated lead frame device is to prevent the formation
of tarnish. This is easily accomplished by preventing the
leads from being exposed to sulfur and sulfur compounds.
The two primary sources of sulfur are free air and most
paper products such as paper sacks and cardboard
containers. The best defense against the formation of
tarnish is to keep silver lead frame devices in protective
packaging until just prior to the soldering operation. One
way to accomplish this is to store the LED devices
unwrapped in their original packaging as received from
HP. For example, Hewlett-Packard ships its seven
segment display products in plastic tubes which are
sealed air tight in polyethylene. It is best to leave the
polyethylene intact during storage and open just prior to
soldering .

THE SILVER PLATING
The silver plating process is performed as follows: The
lead frame base metal is activated (cleaned) and then
plated with a copper strike, nominally 50 microinches
'(0.00127mm) thick. Then a minimum 150 microinch
(
.. . '(0.00381mm) thick plating of silver is added. A
"brightener" is usually added to the silver plating bath to
insure an optimum surface texture to the silver plating.
The term "brightener" comes from the medium bright
surface reflectance of the silver plate.

Listed below are a few suggestions for storing silver lead
frame devices.
1. Store the devices in the original wrapping unopened
until just prior to soldering.
2. If only a portion of the devices from a single tube are to
be used, tightly re-wrap the plastic tube containing the
unused devices in the original or a new polyethylene
sheet to keep out free air.
3. Loose devices may be stored in zip-lock or tightly
sealed polyethylene bags.
4. For long term storage of parts, place one or two
petroleum napthalene mothballs inside the plastic
package containing the devices. The evaporating
napthalene creates a vapor pressure inside the plastic
package which keeps out free air.
5. Any silver lead frame device may be wrapped in "Silver
Saver" paper for positive protection· against the
formation of tarnish. "Silver Saver" is manufactured by:

Since silver is porous with respect to oxygen, the copper
strike acts as an oxygen barrier for the lead frame base
metal. Thus, oxide compounds of the base metal are
prevented from forming underneath the silver plating.
Copper readily diffuses into silver forming a solution that
has a low temperature eutectic point. The interdiffusion
between the copper strike and the silver overplate
improves the solderability of the overall plating system. If
basic soldering time and temperature limits are not
exceeded, a lead frame base metal-copper-silver-solder
metallurgical bonding system will be obtained.

THE EFFECT OF TARNISH
Silver reacts chemically with sulfur to form the tarnish,
silver sulfide (Ag2S). The build-up oftarnish is the primary
reason for poor solderability. However, the density of the
tarnish and the kind of solder flux used actuallydetermine

The Orchard Corporation
1154 Reco Avenue
St. Louis, Missouri 63126 (312) 822-3888

315

6. To reduce shelf storage time, it will be worthwhile to
use inventory control to insure that the devices first
received will be the first devices to be used.
One caution: The adhesives used on pressure sensitive
tapes such as cellophane, electrical and masking tape
can soak through silver protecting papers and may
leave an adhesive film on the leads. This film reduces
solderability and should be removed with freon T -P35,
freon T-E35 or equivalent prior to soldering.

conditioner must be used. Some possible cleaner/surface
conditioners are Alpha 140, Alpha 174, Kester 5560, and
Lonco TL-1. The immersion time for each cleaner/surface
conditioner will be just a few seconds and each is used at
room temperature. For example, Alpha 140 will remove
severe tarnish almost upon contact; therefore, the
immersion time need not exceed 2 seconds. These
cleaner/surface conditioners are acidic formulations.
Therefore, thoroughly wash all devices which have been
cleaned with a cleaner/surface conditioner in cold water.
A hot water wash will cause undue etching of the surface
of the silver plating. A post rinse in deionized water is
advisable.

SOLDER, FLUX AND CLEANERS
The solder most widely used for soldering electroniC
components into printed circuit boards is Sn60 (60% tin
and 40% lead) per federal standard 00-S-571. Two
alternates are the eutectic composition Sn63 and the 2%
silver solder Sn62.

CAUTION: These cleaner/surface conditioners may etch
exposed glass and may have a detrimental effect upon the
glass filled encapsulating epoxies used in optoelectronic
devices. Complete immersion of an optoelectronic device
into a surface conditioner solution is NOT recommended.
For best results, immerse only the tarnished leads and do
not expose the encapsulating epoxy to the solutions.

As the device leads pass through the solder wave of a flow
solder process, the tin in the solder scavenges silver from
the silver plating and forms one of two silver-tin
intermetallics (AgsSn or Ag3Sn). This silver in the molten
solder should not be considered a contaminant. As the
silver content increases, the rate of scavenging decreases
and the probability of obtaining the desired base metalcopper-silver-solder metallurgical system is improved. The
result is that the silver content in solder, which reaches a
maximum of 2-1/2% in Sn60 at 230°C, aids in producing
reliable solder joints on silver plated lead frames.

The cleaning of printed circuit boards after soldering is
important to remove ionic contaminants and increase
circuit reliability. When a Type RMA or Type RA flux is
used, vapor clean with an azeotrope of fluorocarbon F113
and approximately 15% alcohol by weight. Some
equivalent products are Allied Chemical Genesolve
DI-15/DE-15, Blaco-Tron DE-15/DI-15 and Arklone K. A
Type RMA or Type RA flux is a mixture of basic Type R
rosin flux and an organic acid. The fluorocarbon F113
removes the residual rosin and the alcohol removes the
residual active ions. Room temperature cleaning may be
accomplished by using Freon T-E35, T -P35 or equivalent.
When a Type AC flux is used, wash thoroughly with water.
Specific cleaning processes are suggested in the
soldering process section.

Solder flux classifications per federal standard 00-S-571,
listed in order of increasing strength, are as follows:
Type
Type
Type
Type

R: Non-Activated Rosin Flux
RMA: Mildly Activated .Rosin Flux
RA: Activated Rosin Flux
AC: Organic Acid Flux, Water Soluble

Suggested applications of these flux types with respect to
various tarnish levels are as follows:

SOLDERING PROCESS

Silver plated lead' frames that are clean, contaminant and
tarnish free may be soldered using a Type R flux such as
Alpha 100.

Before the actual soldering begins, the printed circuit
boards and components to be soldered should be free of
dirt, oil, grease, finger prints and other contaminants.
Fluorinated cleaners such as Freon T -P35 may be used to
preclean both the printed circuit boards and LED devices. ,
Operators may wear cotton gloves to prevent finger
prints when loading components into the printed circuit
boards.

Minor Tarnish

Since some minor tarnish or other contaminant may be
present on the leads, a type RMA flux such as Alpha 611 or
611 Foam, Kester 197 or equivalent is recommended.
Minor tarnish may be identified by reduced reflectance of
the ordinarily medium bright surface of the silver plating.
Type RMA fluxes which meet MIL-F-1425.6 are used in the
construction of telephone communication, military and
aero space equipment.

If the silver lead frames have acquired an unacceptable
layer of tarnish, remove this tarnish layer with a
cleaner/surface conditioner just prior to soldering. Since
a cleaner/surface conditioner does slightly etch the
surface of the silver plating, the silver leads are now more
susceptible to tarnish formation. Therefore, use a
cleaner/surface conditioner only on those silver lead
frame devices which will be soldered within a four hour
time period. The effect of various tarnish levels on the
choice of flux is discussed in the previous section.

Mild Tarnish

For a mild tarnish, a type RA flux such as Alpha 711-35,
Alpha 809 foam, Kester 1544, Kester 1585 or equivalent
should be used. A mild tarnish may be identified by a light
yellow tint to the surface of the silver plating.

Many of Hewlett-Packard's LED Lamps and Display
products have a soldering specification of 230° C.( 446° F)
for a maximum time period of 5 seconds. Therefore, in a
flow solder operation adjust the solder temperature and
belt speed to conform to this specification, or as is
specified on the device data sheet. The flow solder
operation may now proceed in a normal fashion. For best
results, anyone single lead should be immersed in molten
solder for as short a time period as possible. At a solder

Moderate Tarnish

A type AC water soluable flux such as Alpha 830, Alpha
842, Kester 1429 or 1429 foam, Lonco 3355 or equivalent
will give acceptable results on surface conditions up to a
moderate tarnish. A moderate tarnish may be identified by
a light yellow-tan color on the surface of the silver plating.
If a more severe tarnish is present, such as a heavy tarnish
identified by a dark tan to black color, a cleaner/surface

316

temperature of 230°C (446°F), Sn60 solder will dissolve
silver at the rate of 60 microinches per second. Therefore,
with an initial silver plating thickness of 150 microinches,
an immersion time of 2 seconds will provide the desired
lead base metal-copper-silver-solder metallurgical sys_. tem. At a solder temperature of 260°C (500° F), Sn60
. solder will dissolve silver at the rate of 80 microinches per
-second. These dissolving rates decrease as the silver
content increases in the molten solder bath.

A WORD ABOUT PRINTED CIRCUIT BOARDS
Printed circuit boards, either single sided, double sided or
multilayer, may be manufactured with plated through
holes with a metal trace pad surrounding the hole on both
sides of the printed circuit board. The plated through
hole is desirable to provide a sufficient surface for the
solder to wet, and thereby be pulled up by capillary
attraction along the lead through the hole to the top of the
printed circuit board. This provides the best possible
solder connection between the printed circuit board and
the leads of the LED device.

Post cleaning of soldered assemblies when a type RMA or
Type RA flux has been used may be accomplished via a
vapor cleaning process in a degreasing tank, using an
azeotrope of fluorocarbon F113 and alcohol as the
cleaning agent. A recommended method is a 15 second
suspension in vapors, a 15 to 30 second spray wash in
liquid cleaner, and finally a one minute suspension in the
vapors. When a water soluable Type AC flux such as Alpha
830 or Kester 1429/1429F is used, the following post
cleaning process is suggested: thoroughly wash with
water, neutralize using Alpha 2441 or Kester 5760 or
Kester 5761 foaming, then thoroughly wash with water
and air dry.

SOLDERED LEADS
Figure 1 illustrates an ideally soldered lead. The amount of
solder which Has flowed to the top of the printed circuit
board is not critical. A sound electrical and mechanical
joint is formed.
Figure 2 illustrates a soldered lead which is undesirable.

CAUTION: The use of tetrachloro-di-fluoroethane (F112),
acetone, trichloroethylene, MEK, carbon tetrachloride
and similar solvents as cleaning agents is NOT
recommended, as these cleaners will attack or dissolve
the epoxies used in optoelectronic devices.

LEO DEVICE

~:riALLIZATION

PRINTED CIRCUIT BOARD

_ _ _ _ _--....

"F~~~~~==~~

___

P.C.BOARD
METALLIZATION

SOLDER HAS WETTED LEAD AND PLATED
THROUGH HOLE AND HAS FLOWED TO
TOP OF P.C. BOARD. EXPOSED LEAD
SHOWS 95% SOLDER COVERAGE.
INDICATING PROPER WETTING.

(
Figure 1. Ideally Soldered Lead

LED DEVICE

~:6AlllZATION

~----- ~~~ri6D CIRCUIT

_ _ _ _ _ ____

~~~

.._____

I[,~• • •;=~;:;;~

~-------

Figure 2.

Undesirable Soldered Lead

317

P.C.
BOARD
METALLIZATION

MENISCUS TURNS INWARD

LIST OF MANUFACTURERS

REFERENCES

Alpha Metals, Inc.
56 G Water Street
Jersey City, New Jersey 07304
(3021 434-6778

Manko, Howard H. Solders and Soldering. New York:
McGraw-Hill,1964.
Coombs, Clyde F. Printed Circuits Handbook. New York:
McGraw-Hili, 1964.

London Chemical Co. (Lonco® 1
240 G Foster
Bensenville, Illinois 60106
(3121287-9477

Flaskerud, Paul and Rick Mann. "Silver Plated Lead Frames for
Large Molded Packages," IEEE Catalog No. 74CH0839-1 PHi
(19741, pp. 211-222.

E.I. DuPonte De Nemours & Co.
Freon Products Division
Wilminton, Delaware 19898
(3021 774-8341

Frank Curran Co. (Petroleum Napthalene Mothballs 1
8101 South Lemont Road
Downers Grove, Illinois 60515
(3121 969-2200
Kester Solder Co.
4201 G Wrightwood Avenue
Chicago, Illinois 60639
(3121 235-1600
Allied Chemical Corporation
Speciality Chemicals Division
P.O. Box 1087R
Morristown, New Jersey 07960
(2011 455-5083
Baron-Blakeslee (Blaco-Tron)®
1620 S. Laramie Avenue
Chicago, Illinois 60650
(3121 656-7300
Imperial Chemical Industries, Ltd. (Arklonel®
Imperial Chemical House, Millbank
London SW1 P3JF, England

318

,Application ..'5"6""""""";;"
,~.ic,
Bulletin
,

,;

.

~,'

"

INTERFACE TIMING AND DISPLAY LENGTH EXPANSION
INFORMATION FOR THE HDSP-2000 CODED DATA CONTROLLER
The HDSP-2000 CODED DATA CONTROLLER shown in
Application Note 1001 is a versatile circuit and is easily
modified to multiplex any display length, This Application
Bulletin contains the key timing information and a detailed
explanation of how the circuit' operates, With this
information, it should be a straightforward exercise to
expand the display to any desired length, Included in this
Application Bulletin are designs for 32, 64, and 128
character displays, The ASCII to 5x7 decoder table within
the Motorola MCM6674 ROM has also been shown, This
decoder table can be stored within a Bipolar PROM if
faster speeds are required,

by the Motorola 6674 128 character ASCII decodeL The
6674 decoder has five column outputs which are gated to
the Data Input of the display via a 74151 multiplexer.
Strobing of the display is accomplished via the 74197,
74393, and 7490 counter string. The 74197 is connected as
a divide by 8 counter that sequentially selects the seven
rows within the 6674. As shown by waveform ® ,the
74197 also enables seven clock cycles to be gated to the
clock input of the display. The 74393 is a divide by 256
counter connected so that the five lowest order outputs
select each of the 32 ASCII characters within the RAM.
The three highest order outputs determine the relationship between load time and column on time. When 206 =
20c = 20D = 1 of the 74393, waveform @ goes to a
logical 1. The circuit then scans 32 characters from the
RAM and serializes the column data by counting through
each of the seven rows of the 6674 and gating the
appropriate column of the display. During the seven
counts when 206, 20c, and 20D of the 74393 are notequal
to a logical 1, the column data is displayed, as shown in
waveform @ . Since only one column can be on at a
single moment, the highest possible column on time is 1/5
or 20%. Thus, the column on time of the display in Figure 2
is (20%) (7/8) or 17.5%.

The circuit shown in Figure 2 shows a CODED DATA
CONTROLLER designed for a 32 character HDSP-2000
alphanumeric display, The key waveforms shown in
Figure 1, labeled CD
®, and @ , are shown to
simplify the analysis of this circuit Label CD is the 1 MHz
clock, Label ® is the output of 7404 pin 2 which is the
inverted OD output of the 74197, Label @ is the output
of the 7404 pin 6 which is the ANDed output of 206, 20c,
and 20D of the 74393, The Motorola 6810 RAM stores 32
bytes of ASCII data which is continuously read, decoded,
and displayed, The ASCII data from the RAM is decoded

(
DISPLAY
CLOCK

ROW 'IROW 21ROW 31 ROW 41ROW SIROW SIROW 7

....- - - - CHARACTER 1 - - - + I

224 CLOCK CYCLES

@---.~
LJ~s
------I COLS.j.

~

OFF
ILOAO)

COLUMNS ON ----~-t

~----COLUMNSON----+I

Figure 1. Timing Information for the 32 Character HDSP-2DDD CODED DATA CONTROLLER

319

Z 80 INTERFACE:

: e: ~
8060A, 6800 INTEAFACE:

74LS367

r
03

D2
D,
DO

l

r

-=-

5V
4Y 11

3V •
2Y 7
'Y 5
3

6 2A
4 'A
2

"5
~ 6A

A3

12::
10 3A
6 2A

A4

1A

A2

~

MCM6810

.

A

vee:

B

:~

23 As
22 A,

11
3Y 9
2y7
1Y

21 A2
20 A3

~

,. A4

'iii A5
As
~ A/W

~ A
r;i) B
PaC
~ 0

~

DAs---'
DB
DctDO

CLEAR

Gf!?c
-=-' -

C/l

t12

"9 7 5 3

~

3 ....

4

l' J

74lS367

15

5A4A3A2A1A

.1

~2J642

~

iV2

~

1

1A 10B 3

T

Cl

'Dc 4
'Do 5

1'f

2A 2Do 11
2Dc '0
Cl 2Do 9

'i2

-=-

MCM6674

6Y 13

~5

C

~~

S

°5

:~

J

12

K

S

:

•

a

8

~

~

CS (NOTE 21

~

B

IMHz
CLOCK
INPUT

J

K

74LS113

A

~
o

~

2

"¢{NOTE 11

A,

ADDRESS BUS

6Y 13

14 : :
12 4A
10 3A

D5
D4

DATA BUS

74532

r---

~
~
~

~

"
-=-

ell
ell
ell
CS

DO
D,
D2
03
04
05
06

2
3
4
5
6
7
8

7
6
5
4

AO
A,
A2
A3

3 A4
2 A5
, AS

Vcc
CSW'

f;j---a

~
DO
0,

D2~ 02

o,tw-;

----;;

r---i

AS,
AS,
ASa

03

HO~:~~~~I:fLAY
V

•

12 01

5

C1 C2C3C4C5

, 2 3 4 5

J!
-=

7 ST
ABC
11109

V C
MA75°'SZ

~

20A 6

_8

r,,----.

D,

D4~ D4

;---iii

CS 10

DO

NOTE 1: ¢ IS MICROPROCESSOR CLOCK
NOTE 2: CS IS fOml ANDED WITH THE I/O ADDRESS OF THI
DISPLAY

7490

~'741~ 12
'3

7404'f..

5

7
6

If
3
6
7

AO
A.
A9

'OK
(TVPI

..;:

............

0
DB 9
Dca
Do"

'5 A
'4 B

~~
'2

-

f
2

"..,......

' 39n
2agn
3 agn

3"

4 39n

"'- I--

"

5 agn

..,......
........
""-

~

-~

~~~74'~ 8
-

Figure 2. 6800, 8080A, and Z-80 Interface to the 32Character HDSP-2000 CODED DATA CONTROLLER

He
~E2'O(TYPI

*OISPLAY
_n. _ .ao _..IS_ OPERATED
.. _____ ._ ..WITH
_

I

I

CKi
'0

Changing the display length to 64 characters is a simple
modification. This configuration can be easily realized by
disconnecting 2QB of the 74393 from the 7410 and
connecting it through the remaining tri-state buffer on the
74LS367 and using the 6810 RAM to store 64 ASCII
characters. By leaving only 2Qc and 2QD attached to the
7410, the column on time of the display is reduced from
17.5% to 15%. This reduction is caused because the
relationship between actual column on time and
theoretical column on time is 3/4 as opposed to 7/8 for the
32 characters. Since the display length has been doubled,
the drive transistors must be upgraded to handle the
higher column currents.

82S2708. The 74393 is a divide by 256 counter connected
so that the seven lowest outputs select each of the 128
ASCII characters within the RAM. The previously unused
input A/output QA of the 7490 has been used as an
additional divide by 2 counter. Thus, when the highest
output of the 74393, 2QD, and the QA output of the 7490 are
NANDed through 7437, the basic relationship between
load time and column on time is established. However, the
external gating that has been added does affect the
column on time slightly. Although these additional gates
increase the total package count by one, they perform the
necessary function of ensuring that the column drivers are
turned off before the clock is gated to the display. This
prevents noise from bei ng generated on the clock of the
display and eliminates erroneous display data. The
resultant column on time is (23/32) (1/5) or 14.4%. The
final modification made concerns the necessary column
current needed to drive the display. Since the HDSP-2000
is rated at Icol(max) = 410 mA and there are 32 modules of
four digits each, the transistors must source up to (32)
(410 mAl or approximately 13A. Darlington PNP power
transistors (2N6285) with the proper resistors have been
used to accomplish this task.

To implement a 128 character display, several modifications are needed. These changes are incorporated into
the circuit in Figure 5. First, the input clock frequency has
been increased tQ 2 MHz. This has been done to maintain a
refresh rate of approximately 100 Hz for each digit, thus
providing a flicker-free display. This higher speed of
operation causes propagation delay problems within the
MCM6674 (NMOS) whose maximum accesstimeis350ns.
For this reason, the MCM6674 must be replaced by a faster
Bipolar PROM. Refer to Figure 3 for a list of 1Kx8 PROMs
that will function correctly in the circuit. From this list, the
82S2708 (maximum access time of 70ns) has been
implemented. If this PROM is programmed with the code
listed in Figure 4, it will decode a character font identical to
the MCM6674. This same propagation delay problem is
present with the MCM6810 RAM. Following worst case
design procedures, the MCM68A10 1.5 MHz RAM should
be used. To accommodate the additional address line
made necessary by the display length expansion, the two
74LS367 tri-state buffers have been replaced with the
74LS244 octal version. Strobing of the display is
accomplished using the 74197, 74393, and 7490 counter
string. The 74197 is connected as a divide by 8 counter
that sequentially selects the seven rows within the

f

PROM
ADDRESS

080
090
OAO
OBO
OCO
000
OED
OFO
100
110
120
130
140
150
160
170
180
190
lAO
lBO
lCO
100
lEO
lFO

FF
FF
EO
EE
EE
FE
E6
F6
Fl
Fl
EO
Fl
Fl
Fl
E6
F9
Fl
Fl
EO
F3
El
Fl
E4
Fl

Pari
Number

Manufacturer

7608
3628-4
82S2708
6381
6385
825228
93451

Construction

Harris
Intel
Signetics
Monolithic Memory
Monolithic Memory
National
Fairchild

Bipolar
Bipolar
Bipolar
Bipolar
Bipolar
Bipolar
Bipolar

- NiCr
- Si
- NiCr
- NiCr
- NiCr
- TiW
- NiCr

Figure 3. 1Kx8 PROMs lor Use in the HD5P-2000 CODED
DATA CONTROLLER

200
210
220
230
HEXIDECIMAL DATA
240
250
260
270
FF E4 El E8 FF EO EE E4 EO FF EO E4 EO EE EE ROW 1 280
EE EE EE EE EO EE El FF E4 EE EE FF FF FF FF
290
E4 EA EA E4 F8 E8 EC E2 E8 E4 EO EO EO EO EO
2AO
E4 EE EE E2 FF E6 FF EE EE EO EC E2 EO E8 EE
2BO
E4 FE EE FE FF FF EF Fl EE El Fl FO Fl Fl EE
2CO
200
EE FE EE FF Fl Fl Fl Fl Fl FF EE EO EE E4 EO
2EO
EO FO EO El EO E2 ED FO E4 El FO EC EO EO EO
ED EO EO E4 EO EO EO EO Fl EO E2 E4 E8 E8 EA
2FO
FO E4 El E4 Fl El F1 E8 E4 EO E4 F5 E4 Fl Fl ROW 2 300
F5 Fl Fl F5 E5 EA El Fl E4 Fl Fl F5 Fl Fl F5
310
E4 EA EA EF F9 F4 EC E4 E4 F5 E4 EO EO EO El
320
EC Fl Fl E6 FO E8 El Fl Fl EC EC E4 EO E4 Fl
330
340
EA E9 Fl E9 FO FO FO Fl E4 El F2 FO FB F9 Fl
Fl Fl Fl E4 Fl Fl Fl Fl Fl El E8 FO E2 EA EO
350
360
EO FO EO El EO E5 F3 FO EO EO FO E4 EO EO EO
F3 EO EO E4 EO EO EO EO Fl EO E4 E4 E4 F5 F5
370
FO E4 El E2 FB E2 Fl FE E2 EO E4 EE E8 FB Fl ROW 3 380
390
F5 Fl Fl F5 E2 EA El EA EE FO Fl F5 Fl Fl F5
3AO
E4 EA FF F4 E2 F4 EB EB E2 EE E4 EO EO EO E2
E4 El El EA FE FO E2 Fl Fl EC EO E8 FF E2 El
3BO
3CO
Fl E9 FO E9 FO FO FO Fl E4 El F4 FO F5 F5 Fl
300
Fl Fl FO E4 Fl Fl Fl EA EA E2 E8 E8 E2 Fl EO
3EO
EE F6 EE ED EE E4 F3 F6 EC El F2 E4 FA f6 EE
3FO
Fl F6 EF FF Fl Fl Fl F1 Fl FF E4 E4 E4 E2 EA

Figure 4. 8252708 PROM Listing

321

Fl
FF
EO
F5
ED
FE
E2
F9
Fl
Fl
EO
F9
F5
FO
EO
F6
Fl
Fl
EO
Fl
F5
FO
EO
FO
FF
FF
EO
EE
EE
FO
EO
FO

FO
F7
E4
E4
Fl
Fl
El
F3
FO
Fl
E4
E4
FF
F5
EF
ED
FO
Fl
EO
E4
Fl
F2
Fl
El
FO
EE
E4
EE
Fl
ED
EF
El

E4
F7
EO
EE
EE
FE
F9
F9
E4
F5
EO
FO
E9
F4
Fl
FO
E4
F5
EO
FO
E9
F2
F9
FO
FF
EE
EO
FF
FE
Fl
F6
FO

El
FD
EA
E6
FO
EE
Fl
FO
El
F5
FF
El
FO
El
FO
EE
El
F5
EA
Fl
Fl
Fl
Fl
El
FF
EE
EA
EE
EE
EE
EE
FE

EF
FD
EE
F2
E9
E4
F3
E4
E4
Fl
E5
FF
E9
E4
Fl
E4
E2
Fl
FE
E2
E9
E4
F3
E5
El
EE
E4
E2
FE
E4
ED
E2

F5
F5
E4
El
FC
Fl
Fl
Fl
FB
F8
E8
El
FO
Fl
FF
Fl
Fl
FO
F3
Fl
FO
Fl
FO
F3
FF
EO
E3
EE
FF
EE
EE
ED

F4
EA
EB
FE
FC
EA
EE
Fl
F8
EA
F5
Fl
FO
EA
E4
Fl
FO
EA
F2
Fl
FO
E4
E4
EA
EO
FB
ED
EE
FO
E4
E4
E4

FF
FF
FO
E4
F3
Fl
ED
Fl
EA
El
EO
E8
Fl
F5
El
F5
EA
El
EO
FO
Fl
FB
Fl
F5
FB
El
EO
FO
EF
Fl
EE
EA

E9
E4
EB
EE
FF
E4
F9
EA
E5
EA
E8
Fl
Fl
EA
Fl
E4
El
Fl
E4
Fl
Fl
Fl
Fl
EA
El
FF
E2
EE
Fl
Fl
Fl
Fl

FF
EE
E2
EF
E4
E4
E4
EF
E2
E4
E2
El
E4
E4
E4
El
E4
E4
E4
E2
E4
E4
E4
Fl
EO
E4
E8
EC
EE
E4
EE
EE

FF
EB
FF
EO
El
E4
El
E2
EO
E4
EE
EC
El
E8
El
E4
EO
EO
F5
EC
Fl
FO
Fl
E8
FF
E4
E4
EO
EE
FF
EE
FF

F5
FF
FF
EC
F8
E8
F4
E8
EE
Fl
E4
EC
F4
E8
F8
E4
E4
Fl
E4
E8
F2
E8
F4
E4
EO
EE
EO
FO
Fl
EE
F2
E2

E4
FD
EC
FO
FO
E4
E4
EO
F5
Fl
EC
E8
FO
E2
E4
E4
EE
Fl
E8
E4
FO
El
E4
E4
E4
FF
FO
E2
FF
EO
EE
E4

FF
FD
FF
EO
F5
E2
F5
E2
E8
F5
EO
FF
Fl
E2
F5
E4
E4
F5
EO
EO
Fl
E2
F5
E4
EO
FF
EO
EO
Fl
EE
F5
E8

F5
F7
EO
El
F3
EO
F9
EO
FB
F5
EO
E2
Fl
EO
Fl
EO
Fl
F5
EC
E4
Fl
EO
Fl
EO
EE
FF
EC
E8
Fl
EO
Fl
EO

F5
F7
E4
E2
Fl
EO
Fl
F5
Fl
Fl
E8
E4
Fl
EO
Fl
EA
Fl
Fl
FO
EO
Fl
EO
Fl
F5
EE
FF
EO
E4
EE
FF
EE
EA

ROW 4

ROW 5

ROW 6

ROW7

8OBOA. 6800 INTERFACE:

r
r

DATA.BUS

1 4 : - - ; 13

,2 SA

~

5Y 11

,0 ...

L-~

>Y"

• '02
16
243
• 1A3
13 242

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11 241

3~
.....
7404

'to.

,

00 t2

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,

V

~

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CLEAR

: : Ao
:

IV. 7
lY4 12

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;

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11

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1A

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cs 10

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5

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,

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36n

30n

C

rED

-=
• 7431

•

3

36n

•

36n

3

•

4

5

36n

'---

5

1274'n

H ;01

'!L

12 7440

""p!.

Cl C2C3C4 C5

-=

~A.

tOe 6

• 7437

HDSP-2000 DISPLAY
I128CHAR.J

11109

~As

'Oo~r---

2Oc:

01

7 ST

-=

1" ...
ZOe

, 7437

,

82S2708

Do 2
3
D, •

"
,"

2V3 6
1Y3 14

;!;!i~::S;!~;!

~
•

~ D

0

NOTES: 1., IS MICROPROCESSOR CLOCK
2.
IS iOiiii ANDED WITH THE I/O ADDRESS
OF THE DISPLAY

16 RIW

NPUT

P:!c:

i..

lYt-!:!2Y4 3
lY2 16

C

Ocf!-

K

ilNOTEn

~.
•
•

~B
~C

12

~INOTE2)

~

lAl
17 2A4

"

1j: ~'-

K

a

..

8

2

74LS113

,V 3

~

tMHil
:LOCK

-

\.V

, ,"

"

~

a.
~~

r::..

3Y 7

'M
2 ,.

D,
D,

.

iii

,v •

03A

Do

ADDRESS BUS

~~

74LS367

~

kSr~

~
~
2N6285fTYP.J

11

8

9

.. DISPLA V IS OPERATED WITH
PIN 1 IN THE UPPER RIGHT
HA.NDCORNER

Figure 5. 6800, 8080~~~nd Z-80 Interface to the 128 Character HDSP-2000 CODED DATA CONTROLLER

3

••

,.

CK

System Insertion Loss

This application bulletin is intended to supplement Application Note 1000. Basic information on flux budgeting
with specific examples using the Hewlett-Packard HFBR1002 Fiber Optic Transmitter, HFBR-2001 Fiber Optic
Receiver, and HFBR-3000 Series Fiber Optic Cable/Connector Assemblies is presented.

The system insertion loss is defined as the total of all
losses of optical flux in the transmission path. The losses
at the connector interfaces are caused by reflections,
differences in fiber diameter, N.A., and fiber alignment.
The system insertion loss also includes losses in the fiber
due to scattering and absorption. Each loss is subscripted
to correspond to its location in the system and the loss is
expressed in decibels. For a worst case design, values
should be used taking temperature, humidity, etc. into
account for the maximum loss.

To determine the performance of a fiber optic system,
three main areas must be considered:
Transmitter Output Optical Flux
Receiver Input Sensitivity
System Insertion Losses

A typical system insertion loss includes:

When designing a fiber optic system, an analysis that
includes temperature, humidity, and voltage variations
will require using the minimum transmitter output flux
and corresponding minimum receiver input sensitivity to
ensure the performance of the fiber optic system for the
environmental conditions of the system.

TransmlHer Output Optical Flux

ao'!I. (dB/km • length)

Connector to Connector

aCR (dB)
acc (dB)

Splice

as

Directional Coupler

aoc (dB)
aSC (dB)

Star Coupler

Flux Budget

r(p,W)

~

The System Flux Ratio is the ratio of transmitter output
flux to the receiver input sensitivity and is expressed in
decibels.

(4)0 = 1000J./W)

.

r(p,W)

System Flux Ratio, aFR(dB) = 10 log R(p,W)

Receiver Input Sensitivity

If the transmitter output flux and receiver sensitivity are
already expressed in dBm, the System Flux Ratio is merely
the difference between 4>r and 4>R'

The receiver input sensitivity is the minimum input flux
that will produce a particular Bit Error Rate (BER) at a
specified baud rate. The receiver sensitivity is a function of
its internal noise and bandwidth. The receiver sensitivity,
4>R ' may be expressed in microwatts or in dBm for
convenience in system calculations.
Receiver Input Sensitivity, 4>R(dBm) = 10 log

(dB)

The flux budget calculation is a method of comparing the
ratio of transmitter optical flux and receiver sensitivity to
the total loss of the system.

When changing microwatts to dBm, the output optical flux
Is referenced to one milliwatt (1000J./W).
.

arc (dB)

Steady State Fiber Losses
Cable/Connector Assembly
to Receiver

(IThe transmitter output optical flux, (4)r). is usually ex~. pressed in microwatts (J./w). For convenience in system
calculations, the output flux can be expressed in dBm,
allowing all system calculations to be algebraic summations.

Transmitter Output Flux, 4>r(dBm) = 10 log

Transmitter to Cable/
Connector Assembly

System Flux Ratio, aFR(dB) = 4>r(dBm) - 4>R(dBm)
The System Insertion Loss, asddB), is then computed by
summing the individual element losses in the transmission
path.

R~W)

(4)0 = 1000J./W)

aSL(dB)

323

= Iaj(dB)

For a system to work satisfactorily, the losses must not
exceed the System Flux Ratio. The Flux Margin, "'M, is the
difference between the System Flux Ratio, "'FR, and the
System Insertion Loss, "'SL. For a system to operate, the
flux margin must be greater than zero.

Some designs may require a specific flux margin to
account for losses that may increase with time, or to
"design-in" a safety margin.

"'M(dB) = "FR(dB) - "'sddB)

.(

"'M(dB) > 0

Sample Flux Budget Calculation
DATA SHEET PARAMETERS

MIN

TVP

MAX

UNITS

HFBR·1oo2
Transmitter

Output Optical
Flux

50

100

J.lW

-13

-10

dBm

HFBR-2001
Receiver

Input Optical
Sensi tivity

0.8

0.5

/iW

-31

-33

dBm

HFBR-3000 Series
Cable/Connector

Insertion
Loss

Length
Dependent
Fixed

7

10
8.4

5.4

NOTES

.
*

dB/km
dB

',iI '" 820nm
*,iI
820nm

=

9. > 300m
Q

s: 300m

'NOTE: Guaranteed specifications 0°C-70°C, ±5% Voltage, 10-9 BER @ 10 Mbaud.
A sample "flux budget" calculation is presented for a
Hewlett-Packard 1000 metre point-to-point fiber optic
system. The system uses a Hewlett-Packard HFBR-1002
Transmitter, HFBR-2001 Receiver, and an HFBR-3000
series 1000 metre Cable/Connector Assembly with no
intermediate connector or splice.

The insertion loss "'TQ may be easily expressed as the
difference between two measurable quantities:
¢T - Transmitter Output Flux
¢Q- Flux Measured at the end of a cable of length,Q

I

£=1000m
I

I

pI

¢T HFBR·3000 SERIES CABLE/CONNECTOR

HFBR·l002

I

aTe

ao e £

¢~

aeR

HFBR·2001

HFBR·3000 SERIES CABLE/CONNECTOR

t-' I

"'TQ·

' -_ _- '

I

I'" _ FLUX METER

arc

I

1. System Flux Ratio

OICR'------'

"Oe£

(dB)

= ¢T(dBm) -

¢Q(dBm)

Using this measurement method, under worst-case
conditions, the maximum insertion loss is 15.4dB for a
Hewlett-Packard 1000 metre fiber optic system.

The System Flux Ratio is the ratio of the transmitter
output flux to the receiver input sensitivity.
System Flux Ratio, "'FR

~

_ HFIIR·1002

=
The System Insertion Loss can then be expressed JlS:

50/J'w _
10 log cJ>R(/lW) - 10 log 0.8/lW - 18dB
t!rr(/lW) _

OR "'FR '" ¢T(dBm) - ¢R(dBm) = -13dBm - (-31dBm)

"'SL = "'TQ = 15.4dB

= 18dB
2. System Insertion Loss

3. System Flux Margin

"'SL = ~"'i = "'TC + "'0 • Q + "'CR

Flux Margin, "'M, is the difference between the System
Flux Ratio and the System Insertion Loss.

The loss from the Transmitter to Cable, "'TC, is not
directly measurable and is shown as a "typical" value
on the HFBR-1002 data sheet.

Flux Margin = System Flux Ratio-System Insertion
Loss

More easily measurable and convenient to state is a
maximum insertion loss from the Transmitterto the end
of a connectored cable of length,Q,calied "'TQ, for use in
system flux budgeting calculations. The insertion loss
then includes "'TC, the loss of the cable, and "'CR. This
approach is convenient for systems where the propagation characteristics of the cable have not reached a
steady state, and values of both "'TC and "'0 are a
function of the cable length.

"'M = "'FR - "'SL
"'M = 18.OdB - 15.4dB

"'M = +2.6dB
In this example, the Flux Margin, "'M' represents the
worst case margin: 0-70°C, 10-9 BER@ 10Mbaud for
a 1000 metre system.
324

600

600

1000

1200

1400

1600

20- CABLE LENGTH -

1800

2000

2200

2400

2600

2800

3000

METRES

Graphical Representation
The insertion loss for a Hewlett-Packard pOint-to-point
system (using the HFBR-1002, HFBR-2001, and HFBR3000 Series Cable/Connector) can be represented graphically. The graph is a convenience for readily determining
the flux margin for systems less than 1000 metres and also
is a guide for determining the flux margin available when
splices, connectors, and couplers are a proposed part of a
fiber optic system.

2. Typical Flux Ratio
_
100/LW
O!FR - 10 log 0.5/L W = 23dB
3. Worst Case Insertion Loss
O!SL = O!F (max), (20:5 300m)
O!SL = 8.4dB

For the HFBR-1 002 Transmitter and the HFBR-3000 series
Cable/Connector Assembly steady state propagation occurs at distances greater than 300 metres from the
transmitter. Therefore the system insertion loss for a
Cable/Connector Assembly less than or equal to 300
. "' metres is defined as a single insertion loss, O!F(dB). For
rengths greater than 300 metres. the system insertion loss
(
is composed of two parts: 1) the fixed loss, O!F(dB), 20:5 300
. metres; and 2) a length dependent loss, O!o(dB/Km), the
linear cable attenuation, valid where optical flux is in
equilibrium (20) 300m).

O!SL = O!F (max) + O!o (max) • (2o~ 300)

4. Worst Case Flux Ratio
50/LW
O!FR = 10 log 0.8/LW = 18dB
As shown on the graph, the Flux Margin is the number
of dB between the System Flux Ratio line and the
System Insertion Loss. Hewlett-Packard system performance (worst case*) guarantees a minimum Flux
Margin at 1000 metres of 2.6dB, while typical performance is greater than 12dB. For a 300 metre system
worst case Flux Margin is 9.6dB and typical performance is greater than 17dB.

Two cases will be graphed, one using typical data sheet
values, the second using worst case insertion losses.
1. Typical System Insertion Loss
O!SL

= O!F (typ)

, (20:5 300m)

As demonstrated by the graph, the H-P system can be
expected to function at distances considerably beyond
1000 metres under typical operating conditions.

O!SL = 5.4dB
O!SL

= O!F (typ)

+ o!o (typ)' (20-300)

,(20) 300m)

O!SL = 8.4dB + 0.010 (dB/m) [20 (m) - 300)

,(2o>300m)
*0-70·C, 10-9 BER @ 10Mbaud

O!SL = 5.4dB + 0.007 (dB/m) • [ 20 (m) - 300)

325

"

":', ,,',:- ,/',

"

",

"~,

,'"

~ ,

ThreShOJd"Dete&tioo .of Visible
ar1(f1~dRadiation
.with PIN Photodiodes

Traditionally, the detection and demodulation of ex- •
tremely low level optical signals has been performed with
multiplier phototubes. Because of this tradition, solid-state
photodetectors are often overlooked even though they have
a number of clear functional advantages and in some applications provide superior performance as well. Some of these
advantages are summarized below and become even more
apparent in the following discussion.

ADVANTAGES OF PIN PHOTODIODES VERSUS
MULTIPLIER PHOTOTUBES
1. Size and weight:

2.

3.

4.

5.

PIN photodiodes are approximately three orders of
magnitude smaller and lighter. This greatly simplifies
and reduces the cost of mounting.
Power Supply:
Multiplier phototubes require more than 1000 volts,
which must be precisely regulated and divided among
the dynodes. By comparison, PIN photodiodes and associated amplifiers operate stably on less than 20 volts,
which does not require precise regulation.
Cost:
The cost, including that of the necessary amplifier, is
lower for the PIN photodiode because of lower power
supply requirements.
Spectral Response:
Broad skirts of the PIN photodiode make it useful
from the ultra-violet, through the visible, and well into
the infrared region. This exceeds the range of any
other device of comparable sensitivity.
Sensitivity:
Noise equivalent power of the PIN photodiode is
lower than that of any other type of photodetector.
The signal levels are extremely low, however, and to
achieve low level performance they require a high gain,
high input resistance amplifier. Multiplier phototubes
have built-in gain and do not require additional lownoise amplification. Moreover, the high input resistance
needed for sensitive performance precludes fast response, whereas the response time of multiplier phototubes may be in the nanosecond region even in the
sensitive mode.

6. Stability:
The characteristics of noise, responsivity, and spectral
response of the PIN photo diode are not dependent on
time, temperature, or other environmental considerations. The same conditions may be hazardous to multiplier phototubes.
7. Overloading:
In the presence of excessive signal, multiplier phototubes of comparable sensitivity are capable of destroying themselves as a result of excessive output current.
The PIN photodiode is unaffected by exposure to room
light or even direct sunlight.
8. Ruggedness:
PIN photodiodes can tolerate exposure to extreme levels of shock and vibration. Typical shock capability is
1500 G's for 0.5 millisecond.
9. Magnetic Fields:
Multiplier phototube gain is affected by fields as small
as one gauss. If the interfering field is fluctuating, the
output will be modulated by it. The PIN photodiode
is insensitive to magnetic fields.
10. Precision:
The responsivity of the PIN photodiode is inherently
precise and repeatable. Within a given type, the characteristics agree (from unit to unit) within plus or
minus 0.1 decade. Responsivity of multiplier phototubes may vary over more than a decade from one unit
to another.
11. Sensitive Area:
The small sensitive area of the PIN photo diode makes
it unnecessary to establish an aperture which may be
required for some applications. However, in some applications good optical alignment is imposed by the
small area.

PIN PHOTODIODE DETECTORS
At the present time a variety of different types of solidstate photodetectors are available. Of these, the Silicon PIN
Photodiode has the broadest applicability and is the subject
of this note. The PIN photodiode's main advantages are:
broad spectral response, a wide dynamic range, high speed,
and extremely low noise. With appropriate terminal circuits it is well suited for many applications that require
converting an optical signal to an electrical signal. The

326

present discussion, however, will be limited to the description of the PIN photodiode's threshold detection sensitivity
and the design of suitable terminal circuits that will realize
this capability.

PHOTODIODE DESCRIPTION
Construction

A brief description of the PIN photodiode will be helpful in understanding its performance and the principles for
designing appropriate circuits to be used with it. Figure 1
shows a typical construction of the PIN photodiode. This
figure is for the purpose of explanation only and is not to
scale. The relative proportions have been deliberately distorted for the sake of clarity.
The PIN structure is produced by diffusion through an
oxide (SI02) mask which also serves to protect the surface.
Since most metals are very opaque to optical radiation, especially at infrared wavelengths, the gold contact is deposited only around the perimeter of the P-layer, and the
gold contact pattern provides for lead attachment a short
distance away from the junction region, so the lead is not in
the light path.

i,

...L

R,

R,

Mode of Operation

(

When a photon is absorbed by the silicon it produces a
hole and an electron. If the absorption of the photon occurs in the I layer, as shown in Figure 1, the hole and the
electron are separated by the electric field in the I-layer.
For the highest quantum conversion efficiency (electrons
per photon) it is desirable to have the P-layer as thin as
possible and the I-layer as thick as possible. The thickness
of the P-layer also determines the value of the parasitic
series resistance (Rs in Figure 2). The thinner the P-layer
the higher the Rs. Since Rs affects high frequency performance there is therefore a design trade-off between quantum
efficiency and bandwidth. Once the trade-off is settled, the
desired thickness is then controlled during the diffusion
process. The effective thickness of the I-layer is controlled
partly by the manufacturing diffusion process and partly by
the magnitude of the electric field applied to the diodethe higher the field, the thicker will be the effective I-layer.
It is therefore desirable to operate the diode with an
external reverse bias, as shown in Figure 2. As the reverse
bias voltage is increased from zero, there are three beneficial effects: hole and electron transit time decreases; conversion efficiency increases slightly; and most importantly,
the capacitance decreases sharply with bias up to about ten
volts and continues to decrease slightly up to about twenty
volts reverse bias.

C

J1 '\

- II +
Figure 2. PIN Photodiode Schematic Symbol, and
Equivalent Circuit
In the presence of optical signals there is a slight modulation of the shunt conductance as the presence of photonproduced holes and electrons in the I-layer modulate its
conductivity. This effect can be quite significant at very high
levels of illumination since the I-layer may become saturated,
resulting in a decrease in quantum efficiency and an increase
in rise time. Saturation can be prevented by applying a very
high reverse bias voltage (up to 200 volts). However, such
a high voltage, applied over a long period of time, may
cause a degradation of the diode's leakage properties. Since
our present concern is with threshold performance, reverse
bias voltages greater than twenty volts need not be considered.
Equivalent Circuit

When properly biased, the PIN photodiode can be accu-rately represented by the equivalent circuit shown in Figure
2. Here ip is the external current resulting when the diode is
illuminated. It has a time constant of 10 picoseconds and
a value of approximately 0.5 amp per 'watt of input at a
wavelength of 8000 angstroms (800 nanometers). This
corresponds to a quantum efficiency of 75%, that is, 0.75
electrons per photon. The quantum efficiency is constant
from 500 nanometers to 800 nanometers (5,000 A to
8,000 A).
iN is the noise current of the; PIN photodiode. Since the
diode is reverse biased, the shot noise formula is applicable,
so that the noise current can be computed from:

PHOTON

• 2

l.v

S= 2q 1dc
where

NOT TO SCALE

Figure 1. PIN Photodiode Cutaway View

B
q
Ide

327

(1)

= system output bandwidth, Hz
=

electron charge, 1.6 X 10- 19 coulombs

= dc current, Amp.

In the case of the photodiode, Ide is simply the dark current, la, which has a value determined by the construction
and dimensions of the particular diode type. Maximum values are: 100 picoamps for 5082 -4204, 150 picoamps for
5082 -4205 and 2 nanoamps for 5082-4203.
Shunt resistance, Rp, is very large, being usually greater
than 10 gigaohms (10,000 megohms), and its noise current
may therefore be neglected. Shunt capacitance, Cp, has a
value from two to five picofarads, depending upon the diode
type and reverse bias. For high frequency operation it is important to minimize Cp because the cutoff frequency is determined by:

£=_1_
<
21TR.C"

..

70

II-

60

I:::l

'a:"

i:

0

!1
:I;

\.

40

1/

w

~

I

5062-

iii

:!!

(2)

0

4~

30

....

~

.
w

Although our present concern is with low frequency
threshold operation, there is another reason for minimizing
Cpo This will be discussed later, when circuit design principles are presented.

4205
20
5082·

42~

10

I-

~

I:::l

0

-10

V -----

~

.......

~
"

.........
-........

f\

'"
iii
"
z

Performance
Threshold performance can and has been specified in a
number of different ways. The most commonly understood
and usable expression takes the form of a noise equivalent
input signal. This is the input signal which produces an output signal level that is equal in value to the noise level that
is present when no input signal is applied. The noise equivalent input in watts is called Noise Equivalent Power
(NEP) and is defined by:

-~

~

~5062.

is
z

~

'\\
, --..-;:::': bJr,

~

a:

-120

\\

RCA
6199

~

Z

f2

\~;:.

,,

50

0

a:

i'

I

~

I

if \

-20
300

-90

\ RCA
7102

400

L

/
500

600

AVELENGTH
~
ULTRA·
VIOLET

.--1-. ......

VISIBLE

700

BOO

"'"

900

- NANJMETERS (nm)

-I.

-........
-80
1000

~

INFRARED

Figure 3. Spectral Sensitivity Comparisons of Photodetectors
NEP =

NOISE CURRENT (amps per root hertz)
(3~
CURRENT RESPONSIVITY (amps per watt)

has a corresponding slope. Notice how the inherently broad
response of silicon, enhanced by the thick I-layer construction, extends the range of useful performance over the response ranges of two types of photocathodes.

which has the units of watts per root hertz. Devices for
photo-detection could then be compared on the basis of
NEP. The lower the NEP the more sensitive is the device.
Another method of defining threshold sensitivity is on the
basis of signal-to-noise ratio for given input signal power
levels. Taking a power level of one picowatt, for example,
the signal-to-noise ratio at the output can be obtained from:
SNR

Although the threshold sensitivity of multiplier phototubes is superior in the visible region, nevertheless for many
applications the advantage is not significant enough to outweigh the disadvantages of generally unstable and temperature-sensitive gain, large size and weight, and the need of
very high and stable power supply voltages. On the other
hand, the superior red and infrared threshold performance
of the PIN photodiode does not necessarily mean it is better
in any application, because one must take into account its
small sensitive area and low signal levels. Realization of the
performance capability described in Figure 3 also requires
fairly careful attention to the design of the terminal circuits
into which the PIN photodiode operates.

RESPONSIVITY (:~:) x INPUT (watts)
NOISE CURRENT (amps)
(4)

This is a ratio of currents. To express it in dB we would
take twenty times its log to base ten, even though the expression converts linearly to a power ratio. This is because
the devices respond linearly to input power.
Figure 3 shows spectral sensitivity cha.racteristics of several PIN photodiodes and multiplier phototubes. Sensitivity
is given in terms of SNR and NEP. The latter is in terms of
dBm. Several interesting features are evident in Figure 3.
Although the quantum efficiency for PIN photodiodes is
constant from 500 to 800 nanometers, the sensitivity curve
is not. This is due to the fact that the energy per quantum
(photon) of radiant energy varies with wavelength.
The curves for the three different PIN photodiodes also
show the dependence of sensitivity on leakage current. Here
the highest. sensitivity is obtained with the 5082 - 4204
which has a maximum leakage current of 100 picoamps.
Next is the 5082-4205 with 150 picoamps and finally
the 5082-4203 with maximum leakage of 2 nanoamps. The
three curves are in effect displaced by the magnitude of the
noise current difference because quantum efficiency is equal
for all. These curves also show the inherent broad response
of PIN photodiodes with respect to multiplier phototubes.
Therefore, the power re~ponsivity of the PIN photodiode

TERMINAL CIRCUIT DESIGN PRINCIPLES
The design of the terminal amplifier must consider the
usual design objectives of low noise, broad band, wide dynamic range, etc. In addition, there are two fundamental
considerations which are dictated by the PIN photodiode:
1. High Reverse Voltage:
The diode must be operated at ten to twenty volts of
reverse bias to reduce shunt capacitance.
2. High Input Resistance:
This is a fundamental consideration in the sensitivity/rise
time trade-off.
The effects of reverse voltage on capacitance have been
discussed earlier. However, the effect is sufficiently important to deserve a re-emphasis here.
A high input resistance is necessary in order to maintain
a high signal-tD-noise ratio. Since the output signal from the
photodiode is a current, and its own internal noise is repre328

gives the necessary range without appreciably attenuating the
feedback current. As the photocurrent, 12 , increases, the
amplifier causes the voltage at the emitter of Q3 to decrease,
which causes a current in Rl to flow out of the node (base of
Ql) into which 12 flows.

sented by a current, it is appropriate to represent the noise
of the terminal amplifier as an equivalent noise current at
tile input. The smallest value of resistor which may be connected to the input is then limited by its noise current according to the formula for thermal noise:

V

(thermal)

B

4kT

R

(5)

BasiC Ampllller Arrangements
For linear operation, the photodiode should be operated with as
small a load resistance as possible. Figure 5 shows the
recommended amplifier arrangement. The negative-going input
is at virtual ground; the dynamic resistance seen there by the
photodiode is R I divided by loop gain. If the op-amp has
extremely high input resistance, loop gain is very nearly the
forward gain of the op-amp. R2 can be omitted if the
photocurrent is reasonably high - its purpose is only to balance
off the effect of offset current. As shown, the output voltage will
rise in response to the optical signal. Hit is preferable to have the
output drop in response to optical input, then both the
photodiode and Ec should be reversed. Ec may, of course, be
zero. Speed of response is usually limited by the time constant of
RI with its own capacitance, so it is improved by using a string of
two or more resistors in place of a single R I.
Logarithmic operation requires the highest possible load
resistance - at least IOGn. With an FET -input op-amp, this is

By comparing eq (1), relating diode noise current to leakage current, with eq (5), relating resistor noise current to its
resistance value, it is clear that there is some value of resistance below which the NEP of the system, i.e., threshold
sensitivity, would be degraded at the rate of 5 dB per decade
of decreasing resistance. For example, in the case of the
5082 - 4203, assuming a maximum leakage current of 2 nanoamps, the value of resistance should be greater than 25
megohms, to avoid degrading the threshold sensitivity.

TRANSISTOR AMPLIFIER
In addition to keeping the input noise current low by
using large values of input resistance, it is also important to
keep other sources of noise in the amplifier at a minimum.
Using ordinary transistors (PNP or NPN) it is not possible
to approach the ultimate sensitivity of which the PIN photodiode alone is capable, even when low-noise transistors, such
as the 2N2484, are used. However, in those applications
where it is possible to sacrifice sensitivity for simplicity,
transistors may be used. A typical transistor circuit is shown
in Figure 4. With this circuit, a sensitivity corresponding to
an NEP of - 95 dBm was obtained. In this case, Ql was
operated at the lowest possible collector current which would
still give adequate gain. A high loop gain was desired in
order to compensate, with negative feedback, for the long
open-loop rise time produced by the high input resistance.
A resistance higher than 10 megohms was not necessary here,
since the transistor itself sets the fundamental noise limitation. A PNP transistor was selected for Q2 in order to balance out most of the base-to-emitter voltage of Ql, so that
the output would tend to be near zero without any zero adjustment. A slight zero adjustment, provided by R2 and R3,

Figure 5. Linear Response; Photodiode and Amplifier

Circuit Arrangement

(
R6
lOOK

Ql

2N2484

OUTPUT

400 uV lem x 1 msec/cm

R5
470K{]

CI

pi TO
REDUCE
OVERSHOOT

NEP = -95 dBm

~ ~.5

TR = 19 14sec
ZOUTPUT
TRANSRESISTANCE =

VERTICAL: (UNSPECIFIED)
HORIZONTAL: 20 usee/em

=

30 n

~= lOrn

~I.l

Figure 4. Transistor Photodiode Amplifier Schematic

329

0.1 s. If high speed logarithmic operation is required, it is best
to use the linear amplifier of Figure 5 followed by a logarithmic
converter.

T ~

easily achieved as in Figure 6. If the offset current of the
amplifier poses a problem, a resistor can be added between the
positive- and negative-going inputs. Its value should not be less
than lOGS"! divided by loop gain. If the amplifier has a very high
input resistance, loop gain is equal to the forward gain of the
amplifier divided by (I + R2/ RI) so making R2 =0 allows the
smallest possible resistance between the inputs. The speed of
response of this amplifier will be very low, with a time constant

VOUT"'(l+~)lltog
R,

!a. "'"
q

q

High Speed Photodlode Amplifier
Applications that call for high speed data signaling, such as
CRT light pens, require amplifiers that have a wider bandwidth
than the circuit shown in Figure 5.
Using a five transistor array (RCA CA3127E) it is possible to
construct a high speed, high gain photodiode amplifier. This
circuit is shown in Figure 8. It is configured as a two stage
amplifier. The first stage is composed of transistors QI-Q3,
where QI is an input emitter follower with feedback obtained
from the emitter of Q3. Q2 functions as an inverting amplifier
interconnecting Q I to Q3. The second stage consists of Q4 and
Q5 which provide additional gain and output buffering, of the
first stage. These two stages provide an equivalent transresistance of 420K ohms. This means that the output voltage Vo is
equal to the photocurrent, Ip, times 420K ohms.

(1+.!f..)
f

IS

When high speed circuit layout techniques are used it is possible
to obtain the rise and fall time performance shown in Figure 7.
This speed is equivalent to a bandwidth of 9.5MHz with an
input flux of 1.9pW. This flux level can be obtained from a
HEMT-6000 700nm High Intensity Subminiature Emitter when
it is operated at lOrnA, at a distance of Icm from the 5082-4207
PIN photodiode.

25 mV

18=-'_F-

!IlL

AT

OI
SEGMENT
DECODeR

•I

J

+5V

1SO!! HI' 5Q8z·n30

D,P,

Figure 1a. Direct Drive Circuit for the 5082·7130/7131
Common Anode Display.

The 5082-7730 and the 5082-7731 are common
anode displays employing a left hand or a right
hand decimal point respectively. Typical applications would be found in electronic instrumentation,
computer systems, and business machines. The
5082-7740 is the common cathode version featuring
a right hand decimal point for applications that
include electronic calculators and business terminals
such as credit card verifiers.

A4 LINE B-

~~~A c0-

•

COMMON

o

CATIIODE

b

·•

.J,.' "

d

SIGN.TlCS

8T53

I

~t 17011

D,P.

,,'

,

tw5082· 7740

Figure 1b. Direct Drive Circuit for the 5()82·77 4()
Common Cathode Display.

This Application Note begins with DC drive techniques and circuits. Next is an explanation of the
strobe drive technique and the resultant increase in
device efficiency.
This is followed by general
strobing circuits and some typical applications such
as clocks, calculators and counters.

An analogous circuit is shown in Figure 1b for a
common cathode DC drive system utilizing a current sourcing decoder/driver instead of a standard
decoder/driver and external resistors.
See Table I for a list and comparative ratings of
some of the commercially available seven segment
decoder/driver circuits.

Finally, information is presented on general operatingconditions, including intensity uniformity, light
output control as a function of ambient, contrast
enhancement and device mounting.

STROBING DRIVE CIRCUITS
DC DRIVE

In strobing, the decoder is timeshared among the
digits in the display, which are illuminated one at a
time. The digits are electrically connected with
like segments wired in parallel. This forms an 8
(7 segments and decimal point) x N (number of
digits) array. In operation, the appropriate segment
enable lines are activated for the particu lar character to be displayed. At the same time a digit enable
line is selected so that the character appears at the
proper digit location. The strobe then progresses
to the next digit position, activating the proper segments and digit enable line for that position.

I n DC or non-strobed drive the display is operated
with each character continuously illuminated, usually with one decoder per character. This technique
is commonly used for short character strings where
the cost of the decoders for DC drive is less than
that for the timing and drive circuits for strobed
operation.
The LE Ds are more efficient when
strobed; however, in DC operation the drivers need
not handle high current levels. The DC drive circuit
for the common anode display is shown in Figure
1a. The current level, set here at 20mA per
333

Since the eye is a relatively slow sensor, a viewer
wi II perceive as continuous a repetitive visual phenomena which occurs at a rate in excess of about 60
events per second. Therefore, if the refresh rate for
each digit is maintained at 100 times or more per
second, the perceived display will appear flickerfree and easy to read. I n displays subject to vibration, a minimum strobe rate of 5 times the vibration
frequency should be maintained.

Figure 2b, a typical device operated at 10 mA DC
would produce a luminous intensity of approximately 120 microcandelas. The same device operated at 50mA peak, 20% duty cycle (as if in a 5 digit
strobed display) will produce approximately
145mcd time averaged luminous intensity.
For common decoder/driver circuits, a series resistor
is placed in each segment enable line to limit the
light emitting diode current. They are placed in the
segment enable lines to prevent uneven current
distribution among segments, commonly referred
to as "current hogging". The resistive current
limiting approach for LE Ds outlined above is compact and easy to implement. However, the resistor
consumes power.

In addition to reducing the number of decoders
and drivers, strobing requires less power than DC
drive to achieve the same display intensity. This is
due to a basic property of GaAsP where luminous
efficiency (light output/unit current) increases with
the peak current level (see Figure 2a). Thus, for the
same average current, use of lower duty cycles
(and higher peak current levels) results in increased
light output (see Figure 2b). For example, from

".1 >.

1.0

.
>

ffi"
u
~

.8

.6

I

:/

V

Various techniques for driving LE D displays from
energy storage devices (such as inductors or capacitors) are quite practical though generally somewhat
higher in cost and bulkier. However, power savings
of as much as 50% over the resistive drive techniques
are attainable. SCR switches may be attractive in
circuits utilizing energy storage devices.

--

Figures 3 and 4 illustrate two possible memory
buffer and display drive techniques used in strobed
applications. Both memory techniques assume a
bit-parallel!character-serial data entry format. If
the system memory is available to supply data to the
decoder, the buffer portion of these circuits may
be deleted.

w
w

>

""
~

.4

0:

.2

50

200

150

100

IpEAK - PEAK CURRENT PER SEGMENT - rnA

Figure 2a.

Relative Efficiency (Luminous Intensity per Unit
Current) versus Peak Current per Segment.

Figure 3 depicts a 5-digit strobed display employing
a recirculating shift register memory. One shift
register is used for each bit of the 4-bit BCD code.
Four lines of data from the shift registers drive an
SN 7447 A seven-segment decoder. The va Iue of the
current limiting resistors is calculated to provide
40 mA per segment peak drive current. The resistor value may be calculated using the following.
formula:
R = VCC -VLED -VCEl -VCE2
N lAVE

500

where VCC = voltage supply potential,
VLED = forward voltage of LED at peak
ISEGMENT (N lAVE ), VCEl = "ON" voltage of
segment switch at peak ISEGMENT ,
VCE2 = "ON" voltage of digit switch at 8 times
peak ISEGMENT , lAVE = desired average operating
current per segment, and N = number of digits in
the display.

~
400
> "0 300
~ §. 250
I

200

~~

150

g~

100

2

~w

;!;"

35
@§

50

~~

40

ffi~
>(.!)

25
20

1=

15

'"

Data for each digit of the display is sequentially
shifted to the QE output of the shift register by the
display scan clock. The scan clock also drives an
SN7496 shift register set up as a ripple scanner.
The scan shift register outputs are buffered to source
the 320mA peak digit current. Data entry to the
storage registers is controlled by the system clock
of the data source. During data entry, the display
is blanked and the scan shift register is reset to the

30

~~

4

6

8 10

20 25

40

60

IF - AVERAGE CURRENT PER SEGMENT - rnA

Figure 2b. Typical Time Averaged Luminous Intensity
per Segment versus Average Current.

334

-

'SERi'AL
fIN
SN7496

.'

-' "

,=:T=-::-:-

-

b

,

IFr g

I
SERIAL
~
IN
Qe
I

a...2!.2.!!..!l

7 x56n

.
d

8N 7447 A

--!L--

f

HP 5082·
773017731

'-=~~==;!~
Id

BCD
DATA

>---+-I~

~-

- - B,

>----I~1
o>---t-r~o:

0
74157

2N822~

~

--,rl-+----------;
L 'SERi'AL f IN

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":"

J, ~.r-----+-------i-h

s~~~~

y"......--------1-+-+----;

L----;;O"'IG"'IT"'O"'R"'IV"'E"R;---j-t-t---+-----1

SN74ge

=-

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'SERi'AL I I
IN

Qe

~-l"
I
MDT,

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T
2.5k

DECIMAL

0,

L--

r-

..!2!2!.!.:!.

-

I-I-I-I--

I-I-I-I--

~r_1_____J_~_____¥-~____k_~_____J

4m
~

~

...2.!.2.!!..:!

...--

• ____ --

r---~

SN7496

A

------

1-£

-=-

r+--

+5V

~
t---. _

SN7498

1/8 SN7404

r-~=~.,
PRE~~~4:.eQA
PRESET B Q B
PRESET C
PRESET 0 Q c

I

41n

MPS !354

L_____ ..J

1---1

DIGIT DRIVER

1---1

DIGIT DRIVER

I----

~~~O~IG~'~T~O~RI~V~ERa~=====:----J
r~=~:~~ IP
ENABLE E CD

SERI~ILJN

De

DIGIT DRIVER

I
r

'"1

I

.A

.A

.t1.-J

1"2

L---~-Gp--~_J

8N7404

.1/JF

Figure 3.

(

WRITE
LOCATION
SELECT

Five Digit Strobed Display with Recirculating Shift Register Memory.

A
B
DIGIT #8

""'4
Gw5.B

SN7448

A
BCD
DATA
IN

SN74170

B

0

10
20

3D

3D

40

40

A

D

DIGIT ENABLE
LINES DIGITS 3·7

t;::::=:~
10
20
3D

L------I40

10
SN74170

2Q
3D 1------'

401------'

+5V
MOTOROLA
MPS 4354

A
B

C
SIGNETICS

82Bl

SN7442

.

,..--------,

L ._ _"--'L._~G~ ~R~~_

Figure 4.

..JJ------------'

Strobed Eight Digit Common Anode Display with Static Memory Buffer.

335

first digit position by a logic "0" at DATA ENTER.
The DATA SOURCE SYSTEM CLOCK and the external BCD lines are also enabled by DATA ENTER.
The 5 digits of new data will be entered into the
shift registers on each positive transition of the
system clock. After data entry, DATA ENTER is
returned to a high state, and scanning begins at
position" A" under control of the SCAN CLOCK.

",,'+!IVI

Figure 4 depicts an eight digit strobed displayemploying a static 4 x 8 bit memory. Data from the
memory buffer is selected by the read lines under
the control of the scan counter. This data is decoded by an SN7448 to drive the display segment
lines. In this case the 80mA per segment peak current is beyond the current sinking capability of any
common decoder/driver so an output buffer transistor must be used. Current limiting resistor values
are calculated as before. The digit scan counter
uses a Signetics 8281 binary counter in the divide
by 8 mode. Data entry to the memory buffer can
occur simultaneously with data read and anyone of
the eight digits may be selected or written independently.

··

r-----'

The display length illustrated in either of the above
schemes may be changed by simply providing the
additional memory requirements and extending the
capacity of the digit scanner. Displays of up to 16
digits are practical.

' - - - - - - - - - 11.. _
OIGIT
DRIVER
__
_ _ .11 - - - - - - - - '

Figure 5.

Typical Single Chip Calculator Circuit.

CLOCKS
Figures 6 and 7 depict the complete circuitry for
6-character digital clocks using monolithic clock
chips from two different manufacturers. Both
clocks use the 60Hz AC line as a time base and
derive power from unregu lated bridge rectifier
power supplies.

Numerous manufacturers are now supplying transistor arrays and buffer drivers which offer the advantages of lower costs and improved packing densities
over discrete segment and digit drivers. See Table
II for a list of some of the presently available
products. See Table III for other useful display
circuits.

Figure 6 illustrates a 6-digit clock circuit using the
National Semiconductor NM5314 clock chip. This,
chip uses a strobed technique with all scanning logic
and memory buffers on board. Scan freq uency is ,established by an external RC network and should
be maintained between 60Hz and 10kHz. The
values shown should generate approximately a 1 kHz
scan rate. Each of the P-channel MOS outputs is
buffered to provide adequate drive current to the
individual segment and digit enable lines.

CALCULATORS
The display circuit for a 1O-digit calculator is given
in Figure 5. A MOSTEK MK5010P single chip
calculator circuit provides the calculating, decoding,
and timing for a four function (+, -, x, +), 10-digit
calculator. The displays are strobed at 100 mA
peak on a 1 of 10 duty cycle. The Darlington segment drivers source 100 mA whi Ie the digit drivers
sink 800mA peak. The MOS output transistor connecting the output to VSS is "OFF" when the segment (or digit) is to be activated. In this state, the
pull-down resistor connected to VGG sinks the
current necessary to turn on the PNP drive stage.
When the MOS transistor is "ON", the 1 mA output
current through the pull-down resistor biases the
PNP drive stage "OFF".

Figure 7 illustrates a 6 digit clock radio circuit
using the MOSTEK MK5010PAN clock chip and
HP 5082-7740 common cathode displays. Since
the MK5010P series chips provide a 12.85% duty
cycle digit enable, the component values shown will
supply approximately 10 mA average or 77 mA
peak current to each segment of the strobed display.
The base inputs of the MPSA-13 segment drivers
and the MPSU 45 digit drivers each have series current limiting resistors and pull-down resistors to limit
maximum drain current and assure cut-off in the
"OFF" state. In this circuit, the digit drive lines
are multiplexed to accept input data for alarm set,
time set, and other functions.

There are a variety of calculator chips for 8, 10,
and 12-digit applications with varying voltage supply
requirements and features. These include circuits
from companies such as AMI, Cal-Tex, MOSTEK,
NORTEC, Rockwell Int'!., and TI. Output stages
vary although the P-channel, open-drain approach
used in the MK501 OP example is the most common.
336

12.6VAC
5O~~H~ _ _ _ _ _ , MDA 920.1

I
I

I
I

I
I

lOOk

HRS x 10

HRS X 1

MIN X10

MIN Xl

SEC X 10

SEC X 1

r-------,

DRIVER J~""",--_ _J"""1-_ _~'---_ _.r-<-_ _. r l L -_ _"
" SEGMENT
_______

_ _---'

1. GND FOR 60Hz LINE FREOUENCV
OPEN FOR 50Hz LINE FREOUENCY
2. GND FOR 12 HR. CLOCK
OPEN FOR 24 HR. CLOCK
3. GNO FOR 6 DIGIT DISPLAY (Seconds)
OPEN FOR 4 DIGIT DISPLAY (Minutes
and hours only)

Figure 6.

Strobed Drive for a Six Digit Clock.

12.6VAC

100K
1 Hz 20 TO 1 Hz INDICATOR DRIVER
AN 16 TO AM/PM INDICATOR DRIVER

9 REF 19

10
\
20

MK 5017P AN

¢ 18
TONE,,2=2~_ _

30

+ __..,o

RADIO

WAKEISLEEP~~~!:::;;;:=:j::h
RADIO

SL~~~th

SA SB SCSD SE SF SG
1514131211 10 9

DISPLAY
INHIBIT

!~SPEAKER
TRANSISTOR

~VER
I

I
:
:
:
I

5082·7740 (6)

HRS.
X 10

3K 161

56.
161

I
I

NOTES:
I
56k
1. SLEEP SELECT SW. IS 3P·8 POS. SW. EOUIV. TO GRAYHILL 5003-8.
I
(6)
2. RADIO SELECT SW. IS 2P-4 POS. SW. EOUIV. TO GRAYHILL 71830-02·01·4N.
.J
3. ALL SWITCHING DIODES ARE 1N914, UNLESS OTHERWISE SPECIFIED.
'---:=-::-:::-~
4. ALL RESISTORS ARE ¥IW, UNLESS OTHERWISE SPE:CIFIED.
5. INPUTS:
SL - SLEEP
AE - ALARM ENABLE
TS - TIME SET
H, M - USED TO SET HRS, 10M. 1M
AS - ALARM SET
24 - 24 HRS DISPLAY
SL " SL2, SL4 - SLEEP CODe 50 - CONVERTS COUNT TO 50Hz INPUT
SN - SNOOZE 7 MIN.

Figure 7.

Six Digit Clock Radio.
337

HRS.

MIN.

MIN.

sec.

Xl

X 10

Xl

Xl0

SEC.

Xl

COUNTERS

General Instrument's AY-5-4007 series, which have
the additional feature of a 25 rnA sourcing capability
at each segment output line.

The strobe display circuit for a 4% digit counter
is shown in Figure 8 utilizing the 7730 common
anode display (left hand decimal point) and the
MOSTE K MK5007P four decade counter. Available
in a 16·pin package, this circuit is a less expensive
version of the familiar MK5002P, and includes
latches, decoding and multiplexing functions. In
addition to counting, this circuit can be used with
its internal clock for DVM, timer and other measuring applications. I n this example, the M K5007P's
BCD outputs are converted to a seven segment format by the SN7447 A decoder/driver which can
sink 40mA per segment. A flip-flop is used to implement an overflow digit "1", providing a 4% digit
display. The average light level of the display is
controlled by two factors. First, R controls the
peak current per segment, set here for 40 rnA. The
second factor is the duty cycle of the counter's
SCAN INPUT signal. The internal multiplexing
circuit for scanning the digits is triggered on the
falling edge of the scan clock. While this signal is
low, the segment and digit outputs are blanked.

A DC drive circuit for a 5 digit counter is outlined
in Figure 9. This combines the -7730 common
anode display (left hand decimal point) with the
TI SN74143, a 4-bit counter/latch/decoder having
15 rnA constant current outputs. For applications
requiring counting up to 12MHz, the use of this
circuit greatly reduces the component count (even
the current limiting resistors are eliminated). The
LATCH STROBE INPUT allows the display to
operate in a data sampling mode while the counter
continues to function. The BLANKING INPUT
allows total suppression or intensity modulation of
the display. The stored BCD data is available for
driving other logic via the LATCH OUTPUTS
(QA, Qs, Qc, QD)' For higher current drives, the
SN74144 with its open-collector outputs can sink
25 rnA per segment.

INTENSITY UNI FORMITY

Therefore, a duty cycle greater than 80% of the
SCAN INPUT signal is desirable for efficient operation. In this circuit, use has been made of the
MK5007P's internal scan clock; a timing capacitor
at the SCAN INPUT sets the frequency. The MOSTE K units can be cascaded for greater than 4 decades of readout. Similar circuits in function are

The 5082-7700 series devices are categorized for
light output intensity to minimize the variation
between digits or segments within a digit. Luminous
intensity categories are designated by a letter located
on the right hand side of the package. Display
appearance will be optimized when a group of
display digits uses devices from a single category.

DIGIT #2

DIGIT #3

4m
HP
5082·7730
{51

+5V GND -12V

/----'IN'v-----f,
DIGIT#l

SCAN INPUT

dp ANODE

TRANSFER INPUT

+5V

r-----'

Figure 8.

Four and One-half Digit Strobed Counter
338

DIGIT #4

OIGIT #5

INTENSITY MODULATION
It is often desirable to vary the intensity of a display to provide improved readability under varying
ambient lighting conditions. Intensity control can
be achieved using either amplitude or pulse width
modulation techniques. The latter is recommended
for broad dynamic range of intensity control. Pulse
width modulation offers the advantage of good
tracking between segments as the intensity is decreased, and also allows the LE Ds to operate with
a high peak current where they are more efficient.
Figures 10 and 11 illustrate two possible techniques
of control.

r

S,
PHOTO'RESIS1"OR

C'-i" REX C!.S05
PULS£W'PTH.

MQDtJLA'TliO '

rc--...,--- SLANKIN/;
OUTPUT TO.
,
CONTRO~

Figure 10. Multivibrator Modulation Circuit.

In Figure 10 a monostable multivibrator is triggered
by the scan clock. Photo-resistor R 1 tracks with
ambient light intensity and causes the monostable
multivibrator to produce an output pulse width proportional to ambient lighting. This method will
provide duty cycles ranging from approximately
20% to 100%.

lkn PUl-SE WlD'rti
MODUlA1ED
OUTPUT TO
BLANKiNG
CONTROL

11&SN7404

Figure 11 depicts another intensity modulation
technique. The scan clock input square wave is
integrated by R1 and C 1 to form a triangular wave.
Ambient light is monitored by a phototransistor
and an amplified output voltage proportional to
ambient lighting is produced by A 1 . These two
signals are presented to the comparator A 2. The
output of A2 will be true only as long as the triangle
wave voltage is greater than the ambient light signal.
The LM311 amplifier used in this circuit can be
replaced with any medium to high gain amplifier
which will give adequate swing with a single 5 volt
supply. This technique offers a 0 to 100% dynamic
range of modulation.

Figure 11. Wide Dynamic Range Intensity Control Circuit.

of the display driver. The display duty cycle is then
controlled by the modulated signal which is proportional to the ambient intensity. If the scan
frequency is substantially greater or less than 1 kHz
in either of the above circuits, timing and integrating
component values will have to be changed to produce satisfactory results.
CONTRAST ENHANCEMENT
The quality of the perceived display is a function
not only of light intensity but also of contrast to
the background. To improve display contrast, the

In both of the above examples, the pulse width
modulated signal is connected to the blanking input
339

entire front surface of the display, except for the
light emitting areas, is finished in a uniform flat
black. The plastic encapsulant in the light emitting
areas contains a red dye to further reduce the reflected ambient light. The display's background and the
type of contrast enhancing filter used affect the display quality. Typically, PC board mounting and
an inexpensive red filter (e.g., Plexiglass 2423 or
materials having similar transmission characteristics)
are used. Under strobe drive conditions of 10 mA/
segment average, the display is easily readable to
distances of ten feet and will retain good contrast
under relatively high ambient lighting conditions.
There are several additional contrast enhancing
measures that can be implemented to allow lower
display intensity and power levels. With respect to
PC board design, keep as many metallized lines as
possible out of the normal viewing area. These
surfaces reduce contrast by reflecting ambient light.
Whenever possible, the lines running to the displays
should be placed out of sight on the board's back
side. You can also hide metal traces by placing
them beneath the display package. To minimize the
light reflected from the PC board, the area surrounding the display can be darkened either through use
of a screened black epoxy ink (e.g., WORNOW
W-O-N black ink) or a black piece of material cut
as a collar to fit around the display. Circular
polarizing filters (such as Polaroid HRCP-red) or

3M Display Film are particularly effective in enhancing contrast in high ambient light although
they may be more expensive. Antiglare coatings
are available from firms such as Panelgraphic Corp.
to reduce front filter reflections. An antiglare
surface finish may also be incorporated into the\
molds used to manufacture the filters.
.
MOUNTING CONSIDERATIONS
The 5082-7700 series devices are constructed utilizinga lead frame in a standard DIP package. In addition to easy PC board mounting, the standard pin
spacing of 0.1 00" between pins and 0.300" between
pin rows allows use of the familiar 14-pin IC sockets. See Table IV for a list of some of the avai lable
display sockets. The displays may be end-stacked
as close as 0.400" center-to-center. The lead frame
has an integral seating plane which holds the package approximately 0.035" above the PC board
during standard soldering and flux removal operations. The devices can be soldered for up to 5
seconds at a maximum solder temperature of 230°C
(1/16" below the seating plane). To optimize
device performance, materials are used that are
limited to certain solvents for flux removal. It is
recommended that only Freon TE,Freon TE-35,
Freon TF, Isopropanol, or soap and water be used
for cleaning operations.

Note: See following pages for Tables I, II, 11/ and I V.

340

Table I. Decoder/Driver Circuits for Seven Segment Displays
Manufacturer's
Product N~.

Manufacturar

9600

Fairchild

Rated Maximum
Output Current
[mAl

Comm~

Anode or
Common Cathode

Other Features

Other

PtOr;ye,
MC14511

Motorola

CC

25

MC4039

Motorola

CA

20

NST51 B
NST59 B

Signetics

CA,CC

MOSCompatible Inputs

NST74 B
N8T75 B

Signetics

CA.CC

Quad latch MOS
Compatible Inputs

8140

Harris

1001/1002

SCS Microsystems

·with external pull-up resIstance

CA

""constant current supply

CMOS

40

Quad latch

120'

Quad latch, some
versions available
w/resistors on
board

"'·current limit resistors on board

I
Table II. Driver Arrays for LED Displays
Manufacturer
and Product No.
ITT Semiconductor
502
503
National Semiconductor
OMSS6!
OMaB63
Sprague Electronics
ULN 2031A
ULN 2032A
Series 400
Texas Instruments
SN75491*
SN75492*

Maximum Output Current

'

'.

Drivers Par, Pac:kage

Typical Application

,,'

200mASink
34mA Source

6
4

Digit Drive
Segment Drive

50mA Source or Sink
500mA Sink

5
S

Segment Drive
Digit Drive

7
7
4

Segment Drive
Segment Drive
Digit Drive

4
6

Segment Drive
Digit Drive

SOmA Sink
SOmA Source
250mASink

50mA Source or Sink
250mASink

341

Table III. Circuits for Seven Segment Displays

Table IV. 14 Pin DIP Sockets for 7700 Series Displays
.Mariufactufet .

ancf PrdducfNo~
AmphenoH3atnes .
. . 821·20011-144
821-20013,..144
82H5()11-144
821·25012·144

WfreWrap

342

~if11fil6rs"b:v(fej,:rllti;,'1!f,' .t1,'te', performance
aFTL"FTL ~cOmpatiQle
', •• " . ," " .' , . "", ,'., ,,' ., '> '. iQcludif]g Iinedriwir,CJfhle;t8rminations, .' t.,·,~'~Orir/iil'~;~"'.;c.,i'Ii
'TI!ftl>'(stems;described 1Jtilize inexpenSive CJfb/e and operate SfJtisfactorily over the ranfJ/iF of tranM'liilljf(Jj"i
fFOm' 1 (t,'.' 1'0.•~. ft.OwIr ,thlsirrmgeof distences, the data rate varies from 0.6 megabits
.~'g(I/l~':.::
per~ond larl1!#'1limit8d by coupler performance at short 

VOIlT

Illustration of tPLH Waveforms
Horizontal 100 ns/div.

Illustration of Max. Clock Data Rate
Waveforms. Horizontal 200 ns/div.

Illustration of tPHL Waveforms
Horizontal 20 ns/div.

Figure 5. TTL Compatible Passive (Resistive) Termination for the 6N137 and Photographs Indicating Measured Performance at the End of the
300 Ft. Transmission Cable.

VOLTAGe TO CURRENT
REG\!lATOR
A

lVaU>

Figure 8. TTL Compatible Active Termination for the 6N137.

Table 4. Summary of Performance of 6N137 Data Transmission Systems at 1. 100, and 300 ft .

tPHL
. (liS)

.Step .Transiant

Clock Data

o.rta Rata Max.

Rata Mex.

IMb/t.I.)

IMbltslS)

Worst Case

Sinusoidal ;.

70

9.5

19.0

10

5:S

8.0

70

1.6

2.0

8MHz: 22V

65.

5.3

11.0

Ilk,pkmin.

10

5.3

13.2

SO

3.$

8.2

350

,,10kHZ:
·5.OkV
pk,pk

Figure 9. High Output Voltage Swing, High Current, Wide
Bandwidth Line Driver that Operates From a 5 Volt Supply
and Produces a >8.5V Pk to Pk Pulse into 300 Ft. of Belden
8717 at 10 MHz.

Figure 10. An Example of Circuit Peaking to I mprove the
Performance of the Passive Termination. C, is Chosen for the
Minimum Value that Significantly Reduces Input to Output
Delay Time. In General, C, Must be Selected Individually
For Each System.

SvmMOR '

, OPTOCOOI'U!A ,c'>

, , -:.....:......-'1"....,.."'"

r

-,:

Figure 11. Common Mode Measurement Circuit.

351

','~,

:F/i;'l

a!a.

,APPLICADNtrrE 951~1

HEWLETT

PACKARD

"

','

Applications for LowIriplrtCurrent
High Gain OptocouplE!rs' ,
Optically coupled isolators are useful in applications where
large common mode signals are encountered. Examples are:
line receivers, logic isolation, power lines, medical equipment and telephone lines. This application note has at least
one example in each of these areas for the 6N 138/9 series
high CTR couplers.

fer ratio (CTR) of 300% at input currenU of 1.6 rnA for
the 6N138 and 400% at O.S rnA for the 6N139. The excellent low input current CTR enables these devices to be used
in applications where low power consumption is required
and those applications that do not provide sufficient input
current for other couplers. Separate pin connections for
the photodiode and output transistor permit high speed
operation and TTL compatible output. A base access terminal allows a gain bandwidth adjustment to be made.

HP's 6N 138/9 series couplers contain a high gain, high
speed photodetector that provides a minimum currenttran&-

RS-232C COMPATIBLE LINE RECEIVER
• 2500V 60Hz Common Mode Rejection

~------~--~o+w

• Allows use of low Cost Line
•

Full 40kbs Data Rata for Line Lengths
up to 5000'

•

Hysteresis for Increased Noise Immunity

.3 TO

26V

*ANTIPARALLEL DIODE IS NEEDED ONLY IF REVERS!! LINE
VOLTAGE EXCEEDS 15V ITO PREVENT HI DUTY FACTOR AT THE INPUT
IS PEGENIiRATED TO 1~% D< _ DUTY
FACTOR AT THE OUTPUT.

f MAx (kHz)

R,Ill)

RL(U)

ILlmA)

NONE

100

46

250

820

1000

4.6

650

1-6000 FT. LINE RECEIVER
• Drive with Standard TTL Buffer Gate
• 2500V 60Hz: Common Mode Rejection
• . All9wS Use of Low Cost Line
• it 40lcbs Data Rate

.• Trl.. ~patible Output
+5V

1 + - - - - 2 2 GA TWlsnD PAIR - - - " ' 1

{DEARBORN 8622061

PROPAGATION PE:LAY, WITHOUT Cx.ox •
WiTH

.., 7ps

v

HIGH VOLTAGE STATUS INDICATOR
•

'Pl." • 2 to 5 .. ; ..... • 25JA,

Oxl ex ; ;. a.G02pF. tpLtt '* 2;1S; tPHL

Low Power Consumption

!----<>V"" - +5 to 15V

• TTL Compatible Output
.• High Speed

• use for Power Turn On Anticipation

Circuit, 117V Line Monitor or Other
High Voltage Sensing

354

V(Vdc or Vrms)

R,

24

47kll

11

48

100kn

22

117

220kn

62

230

470kn

113

V.IF(mW)

MEDICAL EQUIPMENT ISOLATION
•.. t.ow Powet c9l1$l$ption
• SOV 6OHr:I$Olation
at:)igital or AnalogOpjlration
BATTERY

POWERED
EQUIPMENT

CONVENTIONAL DARLINGTON
. .• No Bias Supply Required

+SV

a Base Lead available for GainlBandwidth
Adjust

a Data Rates of 2kbs

"'\

/"\

V

Jlf

",-5V

V_-- lV

...."<1_.
tpHl < 300ps
'lptIl. tPlH OUTPUT

REFERENCE ~ I.W

(

355

HEWLETT

MJ PACKARD

APPLICATION NOTE 951-2

COMPONENTS

linear Applications of
Optocouplers
Optocouplers are useful in applications where analog
DC signals need to be transferred from one module
another in the presence of a large potential difference
induced noise between the ground or common points
these modules.

For the 6N135 series optocoupler, n varies from
approximately 2 at input currents less than 5mA to
approximately 1 at input currents greater than l6mA. For
AC coupled applications, reasonable linearity can be
obtained with a single optocoupler. The optocoupler is
biased at higher levels of input LED current where the ratio
of incremental photodiode current to incremental LED
current (aiD/alp) is more nearly constant.

or
to
or
of

Potential applications are those in which large transformers, expensive instrumentation amplifiers or complicated AID conversion schemes are used. Examples are:
sensing circuits (thermocouples, transducers ... ), patient
monitoring equipment, power supply feedback, high
voltage current monitoring, adaptive control systems,
audio amplifiers and video amplifiers.

For better linearity and stability, servo or differential
linearization techniques can be used.
The servo linearizer forces the input current of one optocoupler to track the input current of the second optocoupler by servo action. Thus, if n1"'n2 over the excursion
range, the non linearities will cancel and the overall
transfer function will be linear. I n the differential
linearizer, an input signal causes the input current of one
optocoupler to increase by the same amount that input
current of the second optocoupler is decreased. If
n2"'n2"'2, then a gain increment in the first optocoupler will
be balanced by a gain decrement in the second
optocoupler and the overall transfer function will be
linear. With these techniques, matching of K will not effect
the overall linearity of the circuit but will simplify circuit
realization by reducing the required dynamic range of the
zero and offset potentiometers.

HP's optocouplers have integrated photodetector/amplifiers with speed and linearity advantages over conventional phototransistors. In a photo transistor, the
photodetector is the collector-base junction so the
capacitance impairs the collector rise time. Also,
amplified photocurrent flows in the collector-base
junction and modulates the photo-response, thereby
causing non-linearity. The photodetector in an HP
optocoupler is a separately integrated diode so its
photoresponse is not affected by amplified photocurrent
and its capacitance does not impair speed. Some linear
isolation schemes employ digital conversion techniques
(A/D-D/A, PWM, PCM, etc.) in which the higher speed of
the integrated photodetector permits better linearity and
bandwidth.

Gain and offset stability over temperature is dependent on
the stability of current sources, resistors, and the optocoupler. For the servo technique, changes of Kover
temperature will have only a small effect on overall
gain and offset as long as the ratio of Kl to K2 remains
constant. With the differential technique, changes of K
over temperature will cause a change in gain of the circuit.
Offset will remain stable as long as the ratio of Kl to K2
remains constant. In the AC circuit, since (aiD/alp) varies
with temperature, the gain will also vary with temperature.
A thermister can be used in the output amplifiers of the
Differential and AC circuits to compensate for this change
in gain over temperature.

The 6N135/6N136 is recommended for single channel AC
analog designs. The HCPL-2530/31 is recommended for
dual channel DC linear designs. The 6N135/6 series orthe
6N137 series are recommended for digital conversion
schemes.
If the output transistor is biased in the active region, the
current transfer relationship for the 6N135 series
optocoupler can be represented as:
IF
Ie ~ K (IF')n
where Ie is the collector current; Ip is the input LED
current; Ip' is the current at which K is measured; K is the
collector current when IF = IF'; and n istheslopeof levs.lp
on logarithmic coordinates.

There are also several digital techniques to transmit an
optocoupler analog signal. Optocouplers can be used to
transmit a frequency or pulse width modulated signal. In
these applications, overall circuit bandwidth is determined by the required linearity as well as the propagation
delay of the optocoupler. The 6N137 series optocoupler
features propagation delays typically less than SOns and

The exponent n varies with IF, but over some limited range
of ~Ip, n can be regarded as a constant. The current
transfer relationship for an opto isolator will be linear only
if n equals one.
356

After zero adjustment, this transfer function reduces to:

the 6N135 series optocoupler features propagation
typically less than 300ns.

VIN
] wherex=R,lcc,
VOUT=R4IcC2 [ (l+x)n-l,

In several places the circuits shown call for a current
source. They can be realized in several ways. If Vee is
stable, the current source can be a mirror type circuit as
shown in Figure 1.

",
,n=02

The non linearities in the transfer function where n I ,.. n2
can be written as shown below. For example, iflxl ~.35, n =
1.05, then the linearity error is 1% of the desired signal.
linearity error

(1

+ x)n

- nx- 1

desired signal

""1 :""

""1 ~

10

-VEE

~

Vee + VEE -Vbe
R

-VEE

Figure 1.

~======::;::==::;:=::::;:====;;;.

U',1h LM307

If Vee is not stable, a simple current source such as the
ones shown in Figure 2 can be realized with an LED as a
voltage reference. The LED will approximately compensate the transistor over temperature since a Vb, /aT ""
aVF/aT = -2mVI"C:

["'"I"'

c, ~ K '1'

,

+Vcc

Figure 3. Servo Type DC Isolation Amplifier.

+

""1
f

HP5082· __

~'o

R

V,

OR

~

VEE HP 5082.4484
OR

EOUIVALENT

-VEE

Typical Performance for the Servo Linearized
DC Amplifier:

RE

448.
EaUIVALENT
R=Vcc

V,

RE

10

=

+ VEE

-VF

1% linearity for 10V p-p dynamic range
Unity voltage gain
25 kHz bandwidth (limited by U" U,)
Gain drift: -.03%I"C
Offset drift: ±1 mVI"C
Common mode rejection: 46dB at 1 kHz
500V DC insulation (3000V if 2 single couplers are used)

fO

lmA
VF -Vbe
RE

V F 2lf: 1.5V at IF ::: 1mA

-VEE

Figure 2.

DIFFERENTIAL ISOLATION AMPLIFIER

SERVO ISOLATION AMPLIFIER

The differential amplifier shown in Figure 4 operates on
the principle that an operating region exists where a gain
increment in one optocoupler can be approximately
balanced by a gain decrement in the second optocoupler.
As IF, increases due to changes in V'N, 1F2 decreases by an
equal amount. If nl = n, = 2, then the gain increment
caused by increases in IF! will be balanced by the gain
decrement caused by decreases in 1F20 The constant
current source biases each IF at 3mA quiescent current. RI
and R2 are deSigned so that I F varies over the range of
2mA to 4mA as VIN varies from -5V to +5V. RI. and R, can
be adjusted to accommodate any desired dynamic range.
UJ and U. are used as a differential current amplifier:

The servo amplifier shown in Figure 3 operates on the
principle that two optocouplers will track each other if
their gain changes by the same amount over some
operating region. U2 compares the outputs of each optocoupler and forces IF2 through D2 to be equal to IFl
through D1. The constant current sources bias each IF at
3mA quiescent current. R1 has been selected so that IF1
varies over the range of 2mA to 4mA as V,N varies from
-5V to +5V. R1 can be adjusted to accommodate any desired range. With V'N=O, R2, is adjusted so that VOUT=O.
Then with V,N at some value, R4 can be adjusted for a gain
of 1. Values for R2 and R4 have been picked for a worst
case spread of optocoupler or current transfer ratios. The
transfer function of the servo amplifier is:

VO UT ~ R5 [(RJIR4) IC1 - IC21

RJ, R., Rs have been picked for an amplifier with a gain of 1
for a worst case spread of coupler current transfer ratios.
The transfer function of the differential amplifier is:

357

The non linearities in the transfer function when n I "c n2"c
2 can be written as shown below, For example, iflxl';;; ,35,
nl = 1,9, n2 ';' 1,8, then the linearity error is 1,5% of the
desired signal.

After zero adjustment, this transfer function reduces to:

, K, R3 '( Icc )n,

where K =

R4 W,

= K2

(. Icc )n2

linearity error

\2!F;

desired signal

(1

+ xl n1 - (1 - X)n2 - (n, + "2) x where x
(n, + "2) x

'

=

~
R,lcc

V,N

>------4----OVOUT

Figure 4. Differential Type DC Isolation Amplifier.

operating conditions, the 6N136 operates in a region
of almost constant incremental CTR. Linearity can be
improved at the expense of signal-to-noise ratio by
reducing IF excursions, This can be accomplished by
increasing R3, then adding a resistor from the collector of
01 to ground to obtain the desired quiescent IF of 20mA,
02 and 03 form a cascade amplifier with feedback applied
through R, and R6, R6 is selected as Vb,!" with I, selected
for maximum gain bandwidth productof 0 3, R7 is selected
to allow maximum excursions of VOUT without clipping, R,
provides DC bias to 03, Closed loop gain (!:.vour! ~VIN) can
be adjusted with R" The transfer function of the amplifier
is:

Typical Performance of the Differential linearized
DC Amplifier:
3% linearity for WV p-p dynamic range
Unity voltage gain
25 kHz bandwidth (limited by U1, U2, u" U4)
Gain drift: -,4%!OC
Offset drift: ±4mVrC
Common mode rejection: 70dB at 1 kHz
3000V DC insulation

AC COUPLED AMPLIFIER
In an AC circuit, since there is no requirement for a DC
reference, a single optocoupler can be utilized by biasing
the optocoupler in a region of constant incremental CTR
(oID!oIF), An example of this type of circuit is shown in
Figure 5. 0 1 is biased by R1, R, and R3 for a collector
quiescent current of 20mA, R3 is selected so that IF varies
from 15mA to 25mA for V1N of W p-p. Under these

Typical Performance of the Wide Bandwidth
AC Amplifier:
2% linearity over 1V p-p dynamic range
Unity voltage gain
10 MHz bandwidth
Gain drift: -,6%!OC
Common mode rejection: 22dB at 1 MHz
3000V DC insulation

DIGITAL ISOLATION TECHNIQUES
Digital conversion techniques can be used to transfer an
analog signal between two isolated systems, With these
techniques, the analog signal is converted into some
digital form and transmitted through the optocoupler,
This digital information is then converted back to the
analog signal at the output. Since the optocoupler is used
only as a switch, the overall circuit linearity is primarily
dependent on the accuracy by which the analog signal
can be converted into digital form and then back to the
analog signal. However, the overall circuit bandwidth is
limited by the propagation delays of the optocoupler,

Figure 5. Wide Bandwidth AC Isolation Amplifier.

358

Figure 6 shows a pulse width modulated scheme to isolate
an analog signal. The oscillator operates at a fixed
frequency, f, and the monostable multivibrator varies the
duty factor of the oscillator proportional to the input
signal, VIN • The maximum frequency at which the
oscillator can be operated is determined by the required
... linearity of the circuit and the propagation delay of the
opto isolators:

accomplished with an integrator circuit followed by a low
pass filter or through some type of demodulator circuit
that gives an output voltage proportional to the duty factor
of the oscillator.
Figure 7 shows a voltage to frequency conversion scheme
to isolate an analog signal. The voltage to frequency
converter gives an output frequency proportional to VIN •
The maximum frequency that can be transmitted through
the optocoupler is approximately:

(tmax - tmin) (required linearity) ;;;'ltPLH - tPHLI

f max

At the output, the pulse width modulated signal is then
converted back to the original analog signal. This can be

,,"1.,
where t = tpLH or tPHL, whichever is larger.
t

...

~,---

..

I OPTIONAL I
IL.,P.
FI~T£R..--ovOUT
L
____
;.J

Figure 6. Pulse Width Modulation.

Another scheme similar to voltage to frequency conversion is frequency modulation. A carrier frequency, f 0, is
modulated by af such that f ± af is proportional to VIN •
Then at the output, VOUT is reconstructed with a phase
locked loop or similar circuit.
0

H-_-

~
a:

'"

«
l-

.70

z

iE
«
a:

.60

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.50

(II

I

>.

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.01

>

f-o_o-/---

j:::

«
...J

.40

W

---- ---LOW TRANSMITTANCE
FOR BRIGHT AMBIENTS
.35" T (ApI" .50

---- ----

a:
I

.30

::<

;::
.20
.10
.001 L--LL_l..:......!-..:L--'-c.:..:;+"......,:-.l_-l.....I..-l.--.J
700
750
370 400
450
500
550 i 1600
650
572 I 626 I
Ad FOR HP DISPLAYS
585
639

I

0
500

550

600

650

A - WAVELENGTH (nm)
i\ - WAVELENGTH (nm)

Figure 2. CIE Standard observer eye response curve (photopic
curve), including CI E vivid color ranges.

Figure 3. Typical transmittance curve for filters to be used with
HP standard GaAsP red displays.

361

700

1.00

1.00

.90

.90

w
u

.90

>>-

.70

'"Z

.60

z
<{
~

.50
.40

w
a:
I

'"Z

.60

a:
>w

.50

...w~

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.30

'--"-"~

HIGH TRANSMITTANCE
FOR DIM AMBIENTS
.40" T Glp) " .50

>

j:
<{

>>-

.70

<{

>

...

.80

~

<{

a:
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w
u

z<{

a:

.30

:;;

:;;

j:

j:'
.20
.10

.10

0
500
A - WAVELENGTH (nml

A - WAVELENGTH (nm)

Figure 4. Typical transmittance curves for filters to be used with
HP high-efficiency red displays.

Figure 6. Typical transmittance curves for filters to be used with
HP green displays.

1.00

[y(A)]. Thus, photometric spectrum = f(A)·y(A). Figures
7b through 10b demonstrate the effect of a wavelength filter. The filtered photometric spectrum is what the eye perceives when viewing a display through a filter (shaded curve) .
Thus, filtered photometric spectrum = f(A)·y(A)·T(A). The
ratio of the area under the filtered photometric spectrum to
the area under the unfiltered photometric spectrum is the
fraction of the visible light emitted by the display which is
transmitted by the filter:
J f(A)oy(A)'T(A)'dA
Fraction of Available

.90

w
u

HIGH TRANSMITTANCE
FOR DIM AMBIENTS
.40 " T (Ap) " .50

•SO

z

<{

>>-

.70

'"Z

.60

a:
>w

.50

~

<{

>

j:

...w

.40

I

.30

<{

Light from Filtered Display
J f(A)'y(A)'dA
In addition to attenuating a portion of the light emitted by
the display, a filter also shifts the dominant wavelength, thus
causing a shift in the perceived color. For a given display
spectrum, the color shift depends on the cut-off wavelength
and shape of the filter transmittance characteristic. A choice
among available filters must be made on the basis of which
filter and LED combination is most pleasing to the eye. A
designer must experiment with each filter as he cannot tell
by transmittance curves alone. The filter spectra presented
in Figures 3,4, 5 and 6 are suggested starting points. Filters
with similar characteristics are commercially available.

a:

:;;
j:'

.20
.10

,
0
500

I
550

550

600

650

700

A - WAVELENGTH (nm)

Figure 5. Typical transmittance curves for filters to be used with
HP yellow displays.

Filtering Red Displays (Ap = 655 nm) Filtering out reflected
ambient light from red displays is easily accomplished with
a long wavelength pass filter having asharp cut-off in the 600
nm to 625 nm range (see Figures 3 and 7b). Under bright
flourescent light, a red filter is very effective due to the low
concentration of red in the flourescent spectrum. The spectrum of incandescent light contains a large amount of red,
and therefore, it is difficult to filter red displays effectively
in bright incandescent light.

Wavelength Filtering
The application of wavelength filters as described in the
previous section is the most widely used method of contrast
enhancement under artificial lighting conditions. Wavelength
filters are very effective in artificial lighting. However, they
are not very effective in daylight due to the high level ambient light. Filtering in daylight conditions is best achieved
by using louvered filters (discussed in a later section).

Filtering High-Efficiency Red Displays (Ap = 635 nm) The
use of a long wavelength pass filter with a cut-off in the 570
nm to 590 nm rang~ gives essentially the same results as is
obtained when filtering red displays (see Figures 4 and 8b).
The resulting color is a rich reddish-orange.

Figures 7, 8, 9 and 10 show the relationship between artificial lighting and the spectra of LED displays, both unfiltered and filtered. Figures 7a through 10a show the relationship between the various LED spectra and the spectra
of daylight flourescent and incandescent light. The photometric spectrum (shaded curve) is obtained by multiplying
the LED radiated spectrum [f(A)] by the photopic curve

Filtering Yellow Displays (Ap = 583 nm) The peak wavelength of a yellow LED display is in the region of the

362

...

1.00

1.00

.90

.90

.80

.80

.70

~
::>

.SO

w

.50

~

.40

...

~

0

>
a:

.70

...
::>

.SO

w

>
;::

.50

"a:~

.40

0

.30

.30

.20

.20

.10

.10

A - WAVELENGTH (nm)

A. - WAVELENGTH (nm)

Figure 7A. Relative relationship between standard GaAsP red LED
display spectrum. photopic curve and artificial lighting.

Figure 7B. Effect of a long pass wavelength filter on red
LED displays.

1.00

1.00

.90

.90

.80

...
...::>~

.70

w

.50

"a:~

.40

.SO

.80

I
I
I

I

.70

~

0

>
;::

...

...::>

.60

w

.50

~

.40

0

>

w
a:

.30

HIGH EFFICIENCY RED LED..., \
PHOTOMETRIC SPECTRUM

J

I \

:::~~Ns~II~~~~CE ~

-----t---- ~
FILTERED PHOTOMETRIC
SPECTRUM

J

""

AMOUNT OF DISPLAY

.30

t- ~~~~~NEg i~~~1GH

.10
0
400

.10
500

550

600

650

o

700

500

1.00

1.00

.90

.90

.80

.80

.70

...

~

.60

650

700

635

- WAVELENGTH {nm}

w

>
;::

...

.60
.50

~
....

.40

>

.40

.70

w

::>
0

0

"a:

~
~~

Figure S8. Effect of a long pass wavelength filter on high·
efficiency red LED displays.

::>

~

I

550

~

. Figure SA. Relative relationship between high-efficiency red LED
display. photopic curve and artificial lighting.

11

J Jl
1IIIJIlfysoo LJ ..lllI
~p =

A - WAVELENGTH (nm)

:0

Jj'

I

I\p = 635

.......

,

--

J i\

I

FILTER =51%

.20

.20

V

w
a:

.30

.30

.20

.20
.10
0
500

I

}..p "" 583
~

A - WAVELENGTH (nm)

Figure 9A. Relative relationship between yellow LED displays.
photopic curve and artificial lighting.

- WAVELENGTH {nm}

Figure 98. Effect of a long pass wavelength filter on yellow
LED displays.

363

1.00 r------,-:.....:--,----"""'....r--,----,----...,

/ ...... 1-... / 'N "

-

/"

.90 f----~-=-==--+-=._.,.,f_-+--m~'--p..__--f--_--l
/
DAYLIGHT
. ...,.... _
1)(
,
)/
.-- FLOURESCENT

I

-

I\

'

~

\h.--../<......c'... ~:~~~T~~D

I
.70 t---:'L..'-;:-:--'-----I----c=If----t1I-HI--\
I Y(AI
-'""1
,'
\ SPECTRUM
.60 f--L...
i....:C:;:IE::.;Pc;.H:::O.:..TO::.:P.:..IC=-C::.:U::.Rj.-'V.::EE+1--I-I-'f--"""/'-j1t---.:..'b-L-/---l
/PHOTOMETRIC

/

i'

\

/

\

1.00 r------,---..---r===-,...----,

.80

~----I-+_+--+---._+--__j

.70 f----I+-\~~===-+----__l
.601-----1-1--t-.,..:.;:==="'F=----__j

==I=1f::::=::::::!FJ.-l---\\--J....\----:/.--t-~---I

.50

.40 1---__t----tJf---:-.L...-+t+-\\--b-"-\--t--\-----1

.40

t----liI-lfi>W+f+==""-,..---l

.30

f-----I4-ii-\-\4_+_

.20

t-----Ht-f-''--1r-\-\-I-

.50

rr-- SPECTRUM
If

.30

.20

1./:

Ad=5ynm

1/ /'"

INCANDESCENT"

:

\J'

y

\

,

' ,

I------+.r/"--J:t'-t----f-tl---\"\\~-~\+__-""""d'
__ ~ /
I I \:\. \

t------ff----¥---I:-==-=-=±==:=1

.10 ~---"'==-__t--:r---+--_j4---t----k'....-~~-----1

I

.l ......

~

450

I

L~ ii"

I
500

I

l~l~1

550
AP = 565

600

650

700

A - WAVELENGTH (nm)

i\ - WAVELENGTH (nm)

Figure 10B. Effect of a bandpass wavelength filter on green

Figure 10A. Relative relationship between green LED displays,
photopic curve and artificial lighting.

LED displays.

Louvered Filters

photopic curve where the eye is most sensitive (see Figure
9a). Also, there is a high concentration of yellow in the
spectrum of flourescent light and a lesser amount of yellow
in incandescent light. Therefore, filters that are more opti·
cally dense than red filters at the peak wavelength are required to filter yellow displays. The most effective filters
are the dark yellowish-orange (or dark amber) filters as
shown in Figure 5. The use of a low transmittance
yellowish-orange filter, as shown in Figure 9b, results in a
similar color to that of a gas discharge display. Pure yellow
filters provide very little contrast enhancement.

Louvered filters are very effective in reducing the amount
of bright artificial light or daylight reflected from the face
of a display, without a substantial reduction in display
emitted light. The construction of a louvered filter is
diagrammed in Figure 11. Inside a plastic sheet are thin
parallel louvers which may be oriented at a specific angle
with respect to the surface normal. The zero degree lou·
vered filter has the louvers perpendicu~ar to the filter
surface.
The operation of a louvered filter is similar to a venetian
blind as shown in Figure 12. Light from the LED display
passes between the parallel louvers to the viewer. Off-axis
ambient light is blocked by the louvers and therefore is not
able to reach the face of the display to be reflected back to
the viewer. This results in a very high contrast ratio with
minimal loss of display emitted light at the On·axis viewing
angle. The trade-off is a restricted viewing angle. For
example, the zero degree louvered filter shown in Figure 11
has a horizontal viewing angle of 180°; however, the verti' .
cal viewing included angle is 60°. The louver aspect ratio
(louver depth/distance between louvers) determines viewing
angle. A list of louver option possibilities is given in Table 1.

Filtering Green Displays (A.p = 565 nm) The peak wavelength of a green LED display is only 10 nm from the peak
of the eye response curve (see Figure 10a). Therefore, it is
very difficult to effectively filter green displays. A long
wavelength pass filter, such as is used for red and yellow
displays, is no longer effective. An effective filter is ob·
tained by combining the dye of a short wavelength pass
filter with the dye of a long wavelength pass filter, thus
forming a bandpass yellow-green filter which peaks at 565
nm as shown in Figure 6. Pure green filters peak at 520 nm
and drop off rapidly in the 550 nm to 570 nm range and
are not recommended. The best possible filters for green
LED displays are those which are yellow-green bandpass,
peaking at 565 nm and dropping off rapidly between 575
nm and 590 nm. As shown in Figure 10b, this filter passes
wavelengths 550 to 570 while sharply reducing the longer
wavelengths in the yellow region. To effectively filter green
LED displays in flourescent light would require the use of a
filter with a low transmittance value at the peak wavelength. This is due to the high concentration of green in the
flourescent spectrum. It is easier to filter green displays in
bright incandescent light due to the low concentration of
green in the incandescent spectrum, see Figure 10a.

Some applications require a louver orientation other than
zero degrees. For example, an 18 degree louvered filter may
be used on the sloping top surface of a point of sale terminal. A second, is the use of a 45 degree louvered fi Iter on
overhead instrumentation to block out ambient light from
ceiling mounted lighting fixtures.
Louvered filters are effective filters for enhancing the viewing of LED displays installed in equipment operating under
daylight ambient conditions. In bright sunlight, the most
effective filter is the crosshatch louvered filter. This is
essentially two zero degree neutral density louvered filters
oriented at 90 degrees to each other. Red, yellow and green
digits may be mounted side by side in the same display.
Using only the crosshatch filter, all digits will be clearly
visible and easily read in bright sunlight as long as the sunlight is not parallel to the viewing axis. The trade-off is
restricted vertical and horizontal viewing. The effective
viewing cone is an included angle of 40° degrees (for a filter
aspect ratio of 2.75: 1).

Three manufacturers of wavelenuth filters are Panel graphic
Corporation (Chromafilter®). SGL Homalite and Rohm &
Haas Company (Plexiglas). The LED filters produced by
these manufacturers are useable with all of HewlettPackard's display and lamp products. Table 2 lists some of
the filter manufacturers and where to go for further information. Table 3 lists some specific wavelength filter products with recommended applications.
364

80% TRANSMISSION
40% TRANSMISSION

100
80

/ [\

60
40

20

-t

/

V

-30

-20

/
-10

VISIBLE

l\

\

DIS1LAY

10

20

'\

30

VIEWING ANGLE - DEGREES

Figure 11. Construction characteristics of 0° neutral density louvered filter.
Table 1. Available Options for Louvered
Filters - Any Combination is Possible
Aspect Ratio and
Viewing Angle
2.75:1 = 60°
2.0:1 = 90°
3.5:1 = 4So

Louver

Angle
0°
1So
30°
45°

Louver Color
Opaque Black
T ra nsl ucent Gray
Transparent Black

Example: 2.75:1 -1So - Transparent Black

r
LED SOURCE

Figure 12. Operation of a louvered filter.

LOUVERED CONTRAST
FILTER

Neutral density louvered filters are effective by themselves
in most bright ambient lighting conditions without the aid
of a secondary wavelength filter. However, colored louvered
filters may be used for additional wavelength filtering at the
expense of display emitted light.

ular reflecting surfaces reflect light without scattering. Displays that have polished glass or plastic facial surfaces
belong to this category. Circular Polarizing Filters are effective when used with Hewlett-Packard's 5082-7010, -7100
and -7300 series displays.

3M Company, Light Control Divison, manufactures louvered filters for LED displays. Their product trade name is
"Light Control Film", which is useable with all of HewlettPackard's LED display and lamp products.

The operation of a circular polarizer may be described as
follows. As shown in Figure 13, the filter consists of a
laminate of a linear polarizer and a quarter wave plate. A
quarter wave plate has its optical axis parallel to the flat
surface of the polarizer and is oriented at 45° to the linear
polarization axis. Non-polarized light is first linearly polarized by the linear polarizer. The linearly polarized light has
x and y components with respect to the quarter wave plate.

Circular Polarizing Filters
Circular Polarizing Filters are effective when used with LED
displays that have specular reflecting front surfaces. Spec·

365

LIGHT
UNPOLARIZED

o

LINEAR POLARIZER

+

QUARTER WAVE PLATE

CIRCULAR POLARIZER

Figure 13. The operation of a circular polarizer.

Panelgraphic Chromafilters® come standard with an antireflection coating. SGL Homalite offers two grades of a
mol ded anti-reflection surface. 3M Company and Polaroid
also offer anti-reflection surface options. Optical coating
companies will apply anti-reflection coating for specialized
applications, though this is usually an expensive process.
Three companies of many which do commercial filter coating are: Optical Coating Labs, Inc., Santa Rosa, California;
Optics Technology, Inc., Redwood City, California; Valpey
Corporation, Holliston, Massachusetts.

As the light passes through the quarter wave plate, the x
and y components emerge 90 0 out of phase with each
other. The polarized light now has x and y forming a helical
pattern with respect to the optical path, and is termed cir·
cular polarized light. As this circular polarized light is reo
flected by the specular reflecting surface, the circular polar·
ization is reversed. When the light passes back through the
quarter wave plate it becomes linearly polarized at 90 0 to
the linear polarizer. Thus reflected ambient light is blocked.
The advantage of a circular polarizer is that reflected ambi·
ent light is reduced more than 95%. However, the trade-off
is that display emitted light passing through the circular
polarizer is reduced by approximately 65% at the peak
wavelength. This then necessitates an increased drive current for the display, more than that required for a wavelength filter.

Mounting bezels: It is wise to take into account the added
appearance of a front panel that has the display set-off by a
bezel. A bezel of black plastic, satin chrome or brushed
aluminum, as examples, will accent the display and attract
the eye of the viewer. The best effect can be achieved by a
custom bezel. Commercial black plastic bezels for digits up
to.3 inch (7.62 mm) tall are available, see Table 2.

Circular polarizers are normally colored to obtain additional selected wavelength filtering. One Caution: outdoor
applications will require the use of an ultraviolet, uv, filter
in front of the circular polarizer. Prolonged exposure to
ultraviolet light will destroy the filter's polarizing properties.

Other suggestions: When designing the mounting configuration of a display, consider recessing the display and filter
0.25 inch (6.35 mm) to 0.5 inch (12.7 mm) to add some
shading effect. If a double sided printed circuit board is
used, keep traces away from the normal viewing area or
cover the top surface traces with a dark coating so they can
not be seen. Mount the display panel in such a manner as to
be easily removed if service should become necessary. If
possible, mount current limiting resistors on a separate
board to reduce the ambient temperature in the vicinity of
the displays.

Po Iaroid Corporation manufactures circular polarizing
filters in the United States. In Europe, E. Kaseman of West
Germany produces high quality circular polarizers.

Anti-Reflection Filters, Mounting Bezels
and Other Suggestions
Anti-reflection filters: A filtered display still may not be
readable by an observer if glare is present on the filter
surface. Glare can be reduced by the addition of an antireflection surface as part of the filter. Both sections of the
display shown in Figure 14 are filtered. The left hand filter
has an anti-reflection surface while the right hand filter
does not.
An anti-reflection surface is a mat, or textured, finish or
coating which diffuses incident light. The trade-off is that
both incident ambient and display emitted light are diffused. It is therefore desirable to mount the filter as close
to the display as possible to prevent the display image from
appearing fuzzy.

Figure 14. Effect of anti-reflection surface on an optical filter.

366

Table 2. List of Filter and Be.el Product Manufacturers
Manufacturer

-.

Panelgraphic Corpora'tion
10 Henderson Drive
West Caldwell, New Jersey 07006
Phone: (201) 227-1500

~SGL Homalite

,)

11 Brookside Drive
Wilmington, Delaware 19804
Phone: (302) 652-3686

Table 3. Specific Wavelength Filter Products
Filter Product

Product
Chromafilter® - Wavelength filters with
anti-reflective coating;
Red, Yellow, Green

Ruby Red 60
Dark Red 63
Scarlet Red 65

Wevelength filters; two
optional anti-reflective
surfaces; three plastic
grades; Red, Yellow,
Green

3M - Company
Visual Products Division
3M Center, Bldg. 235-2E
Saint Paul, Minnesota 55101
Phone: (612) 733-5747

3M - Brand
Light control film;
louvered filters

G larecheq, Ltd.
1-4 Christina St.
London EC2A 4PA
England
Phone: (44) 1-739-6964

Spectrafilter

Rohm and Haas
Independence Mall West
Philadelphia, Pennsylvania 19105
Phone: (215) 592-3000

Plexiglass; sheet and
molding powder;
wavalength filters,
sold as Oroglas in
Europe

Type of LED Display

Standard Red
High -Efficiency Red

Circular polarizing
filters

E. Kllsemann GmbH
o 8203 Oberaudorf
West Germany
Phone: (08033) 342

Circular polarizing
filters

Norbex Division
Griffith Plastics Corporation
1027 California Drive
Burlingame, California 94010
Phone: (415) 344-7691

DIGIBEZEL®; Plastic
bezels for LED displays

Industrial Electronic Engineers, Inc.
7720-40 Lemona Avenue
Van Nuys, California 91405
Phone: (213) 787-0311

Plastic bezels for .30
inch (7,62mm) tall
LED displays

Rochester Digital Displays, Inc.
120 North Main Street
Fairport, New York 14450
Phone: (716) 223-6855

Complete mounting kits
for H.P. 5082-7300,
-7700 and -7600
displays.

Moderate
Bright
Moderate

Yellow 27

Yellow

Moderate

Green 48

Green

Moderate

Gray 10

All Colors

Sunlight

SGL Homalite, Grade 100
Hl00-1605

Standard Red

Moderate

Hl00-1670

High-Efficiency Red

Moderate

Hl00-1726
Hl00-1720

Yellow

Dim
Moderate

Hl00-1440
Hl00-1425

Green

Dim
Moderate

All Colors

Sunlight

Hl00-1266 Gray

Polaroid Corporation
Polarizer Division
549 Technology Square
Cambridge, Massachusetts 02139
Phone: (617) 864-6000

Ambient Lighting

Panelgraphic Chromafilter® With Anti-Reflection

Anti-Reflection
LR-72: 0.5 inch (12.70mm) Mounting Distance From Display
LR-92: Up to 3.0 inch (76.20mm) Mounting Distance From Display
Rohm & Haas
Ple>ClK"O"

C

.J

WRITE
ADDRESS

"REFER TO TIMING DIAGRAM. FIGURE 4.

ClK

FJ=la

A

ClK

AQ1Al--+~~f-L------~t:t:::::J=+-I-l-l-++~t:t=+~--~t::t:=+~+t-l-l-++~rt"T'"

CD4022

...

1/4

W

ri~~!.

~

~:'IN

I

LJ

y f f f r f Ln
I'TTdllllll'TT,~

~

CD4011

1/4CDoIOOl
NODE-

I/8CD4060

B

1/8CD4049

ClK

VB

HP HDSP·2000 (4)

..----to.,

18 DIGITS

-=

2345818
1
CD4014
SER.
PIS
IN
CONrROl ~K

c:a

1/8CD4049V

Vee

=9

--f)f-7-'

Figure 3. 16 Clmrac:t.. CMOS logic Interface to the HP HDSP·2OQO.

.

supply costs and improve efficiency, this supply may be a
fullwave rectified unregulated DC voltage as long as the
PEAK value does not exceed the value of Vee and the
minimum value does not drop below 2.6 volts.

D.F. =
and the refresh period is

Since large current transients can occur if a column line is
enabled during data shifting operations, the most
satisfactory operation will be achieved if the column
current is switched off before clocking begins. Icc will be
reduced by about 10-15% if the clock is held in the logical
1 state during the display period, T.

5 (8 X 27)

where

T

=

T,

clock period.

The four least significant bits of the CD4520 counter are
used to continually address the CD4036 refresh memory.
Data can be written into the desired memory address by
strobing the WRITE ENABLE line when the appropriate
memory address appears on the WRITE ADDRESS lines.
This function can occur simultaneously with a read from
memory.

INTERFACE CIRCUITS FOR THE HP HDSP-2000
There are many possible practical techniques for
interfacing to the HP HDSP-2000 alphanumeric display.
Three basic approaches will be treated here.

Two counters, a CD4029 and a CD4022, are used for the
column data generator and the column select decoder,
respectively. Note that the Signetics 2516 character
generator requires column select inputs of binary codes 1
to 5 instead of binary 0 to 4. For this reason, the CD4029 is
preset to a binary 1 by the same pulse which is used to
reset the CD4022 column select decoder. To minimize Icc,
the VB terminal is held low during data load operations.
turning "OFF" the current mirror reference current. The
column current switch is a PNP Darlington transistor
driven from a buffered NAND gate. The 1N4720 serves to
reduce the column voltage by approximately 1 volt,
thereby reducing on board power dissipation in the HP
HDSP-20GO devices. Due to maximum clock rate limitations of the CMOS logic, clock input should not exceed
1 MHz.

Instrumentation Interface Circuit
The circuit shown in Figure 3 is for a 16 character display
and is designed to function primarily as a readout for
general instrumentation systems. CMOS logic circuitry is
utilized in this design, however, it should be a simple
exercise to substitute TTL functions if CMOS is not
desired. In this circuit, a CD4022 and CD4520 are
combined to perform the functions of the divide by 7,
divide by 16 (1 IN) and display time counters as depicted in
Figure 2. The timing diagram, Figure 4, demonstrates the
relationship of the various critical outputs and inputs. The
CD4022 actually acts nere as a divide by 8 counter with the
first count used to latch data into the parallel-in-serial-out
(PISO) shift register and the other 7 counts shifting data
out of the PISOand into the HPHDSP-2000. The CD4520 is
a dual4 bit counter wired as an 8 bit binary ripple counter.
The NAND gate, U 10 establishes the ratio of loading time to
display time. In this case, loading will occur once in every
8 x 2 7 clock counts for a period of 8 x 24 clock counts. Duty
factor is then from (1)

32 Character Keyboard Interface Circuit
The circuit shown in Figure 5 will directly interface the HP
HDSP-2000 display to most standard keyboards. Interfac-

+1

+2

+3

+4

+5

+6

+7

+8

ClK

---lnL-------"

PARALLEL LOAD
CD 4014 WHEN HIGH

r----_ _
NODE B

DISPLAY TIME

LOAD TIME

REPEAT

FROM
ZERO

NODEC

NODE 0

REPEATS 16 TIMES
TO LOAD 16 COLUMNS
OF 7 BITS EACH

Figure 4. Timing Diagram for Display Interface.

372

Ing to a keyboard without a "smart" system to generate
some of the special functions required can result in some
unique problems which must be considered. This system
provides the following special features:

write pulse. The write pulse also clears the load control
flip-flops on the next clock cycle so that a new arriving
Signal can be recognized. The Q output of Us is also used
to decrement the position counter.

• Provides a cursor to indicate the position in the line of
the next character to be entered.

The other special functions which are added to the circuit
of Figure 3 are an intensity control and a blanking input.
Intensity control is realized through the 74122 retriggerable monostable multlvlbrator, U,. This circuit controls
the time that the column select decoder is enabled during
the display time, T. The display is externally blanked by
holding the "RESET" input of the column select counter at
a logical "0".

• Blanks all data to the right of the cursor in the display.
• Provides for external display blanking and intensity
control.
• Implements "Return" and "Backspace" functions.

r-

The timing and data scan portions of this circuit are
similar to those of the circuit shown in Figure 3 and will not
be reviewed in detail. These portions of the circuit are
enclosed in the dashed line. The major addition to the
circuit which allows simple implementation of the special
functions is a position counter and comparator. The
position counter is an up-down counter which is preset to
n-1 (n = number of characters in the display string) by
"RETURN". The counter is decremented for each
keystroke representing a valid display character and
incremented for a "BACKSPACE" input code. A Fairchild
9324 five bit comparator compares the position counter
output to the memory scan address. The memory scan
begins at zero and represents the data for the right most
(32nd) character in the display. The position count is
indicative of the number of character keystrokes which
have decremented the pOSition counter from 31. The
comparator senses two conditions of the relative values of
the two counters. For memory scan equal to pOSition
count, the A=B output of the comparator will be a logical
"1". For all other conditions of the two counters, A=B is a
logical "0". This signal is inverted and is used to gate data
from the PISO via Ul into the HP HDSP-2000. For the
condition A=B, the gating input is a logical "0" and the
output of NAND gate U2 is therefore held at a logical "1".
This will cause all of the diodes associated with the
character position A=B to be iIIumi nated, thus forming the
"cursor". The second condition which is sensed by the
comparator is for a memory scan count less than position
count, (A>B). This condition represents all character data
to the right of the cursor and results in a logical "1" at the
"A>B" output of the comparator. It is normally desirable
for these characters to blank, hence a logical "0" should
be loaded into the corresponding HP HDSP-2000 shift
register locations. This is implemented by inverting the
"A>B" output and applying the resulting signal to one
input of NAND gate, Ul. For "A>B" at a logical "1", the
output of Ul will be a logical "1". This signal will then be
inverted by U2, causing logical "0" data to be loaded into
the HP HDSP-2000 shift register for all characters to the
right of the cursor. For "A=B" and "A-----t:

I""

J

O ClK A=B>-r-"\.
... _
----L..J""V'"

PR

Q

K

cy-

J

'/47400 '/67406

Us
7476

Q

f-7

DECREMENT.C

K

Cl!K

A~.-:B~=[:~--i~.

Q~
U.
7476

iWNEE

'/47400

}R

1/6~6

I

BlANKO~------------------------------------------------------------------------

50K

~c~O------------------------------------------------------------------BRIGHTNESS
CONTROL
1/27413

BUSY

U3 Q

O)-----"I{(:J:~h~=====:~: g

Figure 5. 32 Character Kevboard Interface Circuit.

374

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9324

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1/6 7406

I

r--J~A~Q.B.~lJ-~QD--,'('----J-A~QB--

BACK SPACE

UP

CARRY

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DN
..,

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74193

DN

A

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F

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elK

SHIFT LOAD

1/47400

B

LOAD

IJ-

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74193

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1/37410

=====·iL-,=j~~~~------~,~p----------------------.
J

1/47400

ClK

DATA

HP HDsp·2000

(-

8 CLUSTERS - 32 DIG ITS

__

COL. 1 COL 2 COL. 3 COL. 4 COL. 5

1 ___ =_~~~
VLCC

f_

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A A

P
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375

~

the shift registers always start synchronous with the
beginning of a full clock cycle so that erroneous clocking
will not occur. U3 is utilized to give intensity control for the
HP HDSP-2000. if desired. It can be overridden by
connecting tne U4(1-5) input to the output of Ul instead
of U3.

applications maximum achievable power dissipation is
considerably less than the maximum allowable package
dissipation of 1.7W. Calculation of power dissipation in
the HP HDSP-2000 can be made using the following
formula:

The shift register memory utilized in this circuit is only one
of several forms of memory which could be chosen.
Another possibility would bethe useof a512x 1 bit or 1024
x 1 bit RAM. The counter outputs would then be used to
select the RAM address.

where

a

Po = P(lee)

(7)

P(lee) = Icc (VB = O.4V) x Vee

(8)

P(IREF) = [Icc (VB =2.4V) - Icc (VB=O.4V)] x Vee x (n/35)
x 5 x D.F.
(9)
(10)

P(leoL) = leol x Veol x (n/35) x 5 x D.F.

POWER DISSIPATION/JUNCTION TEMPERATURE
CALCULATIONS

where
Icc is measured with all S.R. stages equal to logical 1.
n = average number of diodes illuminated per character.
D.F. = Column On Time from equation (1) or the
Column On Time due to pulse width modulation of VB,
whichever is lower.

The HP HDSP-2000 combines a significant amount of
logic and display capability in a very small package. As
such, on board power dissipation is relatively high and
thermal design of the display mounting becomes an
important consideration. The HP HDSP-2000 is designed
to permit operation over a wide range of temperature and
supply voltages. Full power operation at T A = 25° C (with
Vee = VB = Veol = 5.25V) is acceptable if the thermal
resistance from pins to ambient, ()eA, is no greater than
35°C/watt/cluster. This value assumes that the mounting
surface of the display becomes an isothermal plane. If
only one display is operated on this isothermal plane at 1.7
watts maximum, then the temperature raise above
ambient is:
TRISE = [35° C/watt] x 1.7 watts = 42.5° C.

+ P(IREF) + P(leol)

As can be seen from formulas (8), (9) and (10), there are
several techniques by which total power dissipation can
be derated:
• Lower Vee to minimum
• Lower Veol to minimum
• Lower D.F.
Maximum and typical power dissipation can be calculated
from the maximum and typical values of Icc and leol
published in the HP HDSP-2000 data sheet. While it is
possible to operate the columns of the HDSP-2000 display
using fullwave rectified unregulated DC, lower power
dissipation can be achieved by using the regulated Vee
supply. Then, Veol is equal to Vee minus the collector to
emitter saturation voltage across the column switching

(6)

If a second display is placed on this same thermal plane,
with no increase in thermal dissipation capability the
temperature would be doubled (Le., 85°C) - reaching
catastrophic levels very quickly. However, in most

DATA ENTRY

~----~~----I>o-----~--------------------------------------------~-,
1/67406
READY-------+------------,

OATA ENTRY
CLOCK

r-------~Q

a

0

1/27474
ClK

DISPLAY
CLOCK

ClK

1/67400

a

112 7474
U2

0

7N SYNCHRONOUS
COUNTERS
L-~----------~--i>ClK

EN

74163

at-----.....

ClR

Figure 6. Display InterfaCtfDes;gnedto Accept Decoded Data.

376

transistors. Since the minimum recommended VCOL is
2.6V. PNP Darlington transistors with a silicon diode in
series with the emitter can be used to lower the power
dissipation within the display. In most implementations of
the ASCII character set the maximum number of diodes
illuminated within a display character. n. is 21 while a
typical character has 15 dots illuminated. While the
:., maximum D.F. is 20%. in most applications D.F. :5 17.5%
duetotherequired timeto load the display. A D.F. of 17.5%
represents a (7/8) ratio of display timeto total time such as
illustrated in the circuit shown in Figure 3. Many
applications achieve a D.F. much lower than 17.5%. For
example. the HDSP-2470 alphanumeric display system
when configured for 40 characters has a D.F. of 11.6%.

HDSP-2432 DISPLAY BOARD

As an example. the maximum power dissipation can be
calculated for the circuit shown in Figure 3. In this circuit
VCOL(MAX) = 5.25V - 1.3V (MPS-U95 @ 1.6A) - .85V
(1N4720 @ 1.6A) = 3.10V. Thus maximum achievable
power dissipation can be calculated as shown below:
P(lcc) = 60mA x 5.25V
= 315 mW

25 Mil INSULATING "TRACES" TO
SEPARATE METAL CONDUCTORS.

(11)

P(IREF) = (95mA - 60mA) x 5.25V x (21/35) x 5 x 0.175
(12)
= 96.5 mW
P(ICOL) = 410mA x 3.1V x (21/35) x 5 x 0.175
=667 mW

(13)

Po = P(lcc) + P(IREF)
= 1079 mW

(14)

+ P(lcOL)

Figure 7.M.ximum Met.llzed Printed Circuit for the HP HOSP-2000.

THERMAL
CONOUCTING
COMPOUND

Similarly. typical power dissipation can be calculated as:
P(lcc) = 45mA x 5.00V
=225 mW

(15)

P(IREF) = (73mA -45mA) x 5.00V x (15/35) x 5 x 0.175
= 52.5 mW
(16)
P(ICOL) =335mAx (5.00V -1.3V -.85V) x (15/35) x5xO.175
= 358 mW
(17)
Po = P(lcc) + P(IREF)
=636 mW

+ P(ICOL)

METAL CHASSIS
DISPLAY BEZEL AND
CONTRAST ENHANCEMENT
FILTER

(18)

For operation at the maximum temperature of 70°C. it is
important that the following criteria be met:
(

" -', a. TCASE :5100°C.
where TCASE = hottest pin temperature
HDSP-2000 DISPLAY

b. TIC JUNCTION :5 125°C
Thermal resistance from junction to case. OJc. is typically
25° C/watt. USing these factors. it is possible to determine
the required heat sink power dissipation capability and
associated power derating through the following assumptions:
, (19)
TIC JUNCTION = (OCA x Po) + OJC (Po - 015n )

2

TCASE = (8CA) Po

PRINTED CIRCUIT BOARD
UTILIZING LARGE
METALIZATION PATTERN

(20)

2

where (Po - 015n ) is the power dissipated fn each IC.
Figure 8. Two-Pert Heat Sink for the HP HDSP·2000.

HEAT SINKING CONSIDERATIONS
In practice. heat sink design for the HP HDSP-2000
involves optimization of techniques to diSSipate heat
through the device leads. Figures 7 and 8 schematically
depict two possible heat sink designs, In many
applications. a maximum metalized printed circuit board
such as shown in Figure 7 can provide adequate heat
sinking for the HDSP-2000 display. For example. the
HDSP-2416/-2424/-2432/-2440 display boards consist of

a 16.24.32 or 40 character HDSP-2000 display mounted
on a maximum metalized printed circuit board. These
display boards are designed for free air operation to 55° C
and operation to 70°C with forced air cooling of 150 fpm
normal to the component side of the board. A free air
operating temperature of 70°C can be achieved by heat
sinking the display. Figure 8 depicts a two part heat sink
which can be assembled using two different extruded

377

parts. In this design, the vertical fins promote heat transfer
due to naturally induced convection. Care should be
taken to insure a good thermal path between the two
portions of the heatsink. To optimize power handling
capability, the metal heat transfer contact area between
the PCB metalization and the heat sink should be
maximized. A surface area of approximately 8 square
inches per cluster will permit operation at 1.1 watts/
cluster at the maximum operating temperature of 70°C
ambient. The value of 1.1 watts/cluster is easily achieved
by reduction of VCOL to 3 volts. Next to increasing total
heat sink area, a provision for at least some forced airflow
is probably the most effective means of improving heat
transfer. Thermal design for the HP HDSP-2000 must be
carefully considered as operation at excess temperatures
can lead to premature failure.
The HP HDSP-2000 displays may also be mounted in
standard DIP sockets which are cut down to accept the 6
pin devices in end-to-end strings. Another alternative for
socket mounting is the stripline socket such as the Augat
325-AG1 D or AMP 583773. These sockets will allow
enough space bewteen the PCB and the HP HDSP-2000
to permit a heat sink bar to be inserted to conduct heat to
an external sink. Most sockets add a thermal resistance of
about 2° C/watt bewteen the device leads and the PCB.

>--:TC=R:-::IG""GE::::R:--~CLR

U_ r

1

FOR DECREASING
AMBIENT

ILLUMINATION

Figure 9. Intensitv Modulation Control Using a One Shot
Multivibrator.

DISPLAY INTENSITY MATCHING AND CONTROL
In the circuit shown in Figure 9, the photocell may be
replaced by a 50K potentiometer to allow manual control
of display intenSity.

The luminous intensity of LED displays in general has a
fairly wide dynamic range. If there is too great a difference
between the luminous intensity of adjacent characters in
the display string, the display will appear objectionable to
the viewer. To solve the problem, the HP HDSP-2000
displays are categorized for luminous intensity. The
category of each display package is indicated by a letter
preceding the date code on the package. When
assembling display strings, all packages in the string
should have the same intensity category. This will insure
satisfactory intensity matching of the characters. The HP
HDSP-2000 displays are categorized in 8 overlapping
intenSity categories. All characters of all packages
designated to be within a given letter category will fall
within an intensity ratio of less than 2:1. For dot matrix
displays, a character-to-character intenSity ratio of 2:1 is
not generally discernable to the human eye.

Contralt Enhancement
Another important consideration for optimum display
appearance and readablity is the contrast between the
display "ON" elements and the background. High contrast
can be achieved by merely dril(ing the highest possible
power into the display. This, of course, is feasible in some
situations as long as ambient lighting is not too intense
and power dissipation is not a consideration. A much
more practical technique is the use of an effective contrast
enhancement filter material. The following materials,
Panelgraphic Ruby Red 60 and Dark Red 63 or SGL
Homalite Hl0Q-1605 and Hl00-1670 will all provide
improved contrast for the HP HDSP-2000 display. Other
good practices to enhance display contrast are to avoid
PCB traces in the visible areas around the display and, if
possible, the utilization of a black silk screen over the
relatively light PCB areas around the display. The Subject
of contrast enhancement is treated in greater detail in HP
Application Note 964. Microprocessor interfaces to the
HDSP-2000 display are shown in HP Application Note
1001.

A more important consideration regarding display
intensity is the control of the intensity with respect to the
ambient lighting level. In dim ambients, a very bright
display will produce very rapid viewerfatigue. Conversely,
in bright ambient situations, a dim display will be difficult,
if not impossible, to read and will also produce viewer
fatigue and high error rates. For this reason, control of
display intenSity with respect to the environment ambient
intensity is an important consideration. Figure 9 depicts a
scheme which will automatically control display intenSity
as a function of ambient intensity. This circuit utilizes a
resettable one shot multivibrator which is triggered by the
column enable pulse. The duration of the multivibrator
output is controlled by a photoconductor. At the end of a
column enable pulse, the multivibrator is reset to insure
that column current is off prior to the initiation of a new
display shift register loading sequence. The output of this
circuit is used to modulate either the VB inputs of the HP
HDSP-2000 displays or the column enable input circuitry.
For maximum reduction in display power, both inputs
should be modulated.

KEY POINTS REGARDING THE HP HDSp·2000:
• A logical "1" in the display shift register turns a
corresponding LED "ON".
• Clocking occurs on the high to low transition of
the clock input.
• A character generator which produces 7 bit
"COLUMN" data should be utilized.
• The internal shift register is 28 bits in length.
• Each column should be refreshed at a minimum
rate of 100 Hz.

378

The following is a list of commercially available character generators which can be used in conjunction with the HP HDSP2000. These devices are all programmed to convert from ASCII input code to 5 sets of 7 bits each for a 5 x 7 display format.
Any desired input-output coding can be utilized in custom programmed ROMs.

Manufacturer

Part Number

Texas Instruments

TMS 4100

Typical
Access Time

Required
Power Supplies

Typical
Power Dissipation

500 nsec

±12V

450 mW

National

5241 ABL

700 nsec

±12V

Signetics

2513

450 nsec

290mW

2516

500 nsec

±5V
-12V
±5V
-12V

AMI

S8773B

450 nsec

+5V
-12V

625 mW (max)

Mostek

2002
2302

±14V
+5V
-12V

320mW
200mW

280 mW

Electronic Arrays

40105

750 nsec

±12V

430mW

Fairchild

3257

500 nsec

+5V
-12V

360mW

Figura 10. Column Output Character Generators Suitable for Use with the HP HDSP·2000.

The refresh memory for the HP HDSP-2000 display can take anyone of sever,al different forms. The following table lists a
few of the devices which the display system designer may find convenient.

Type

Organization

Bipolar RAM
*7489
*7481 A
*7484A
Fairchild 93403
Intel 3101
Intel 3104

Words x Bits
16 x 4
16 x 1
16 x 1
16 x 4
16 x 4
4x4

MaS RAM
TI TMS 4000 JC/NC

16 x 8

CMOS RAM
RCA CD 4036
RCA CD 4039
National 74C89
Motorola MCM 4064

4x8
4x8
16 x 4
16 x 4

Shift Register
TI TMS 3112
Signetics 2518
Signetics 2519
Fairchild 3348
Fairchild 3349

32
32
40
32
32

x
x
x
x
x

6
6
6
6
6

'Standard 7400 Series TTL logic parts available from most Integrated
Circuits manufacturers.

Figure 11. Memory Elements Which cen be Utilized in HDSP·2000 Display Systems.

379

Flin-

HEWLETT

a!~ PACKARD

APPLICATION NOTE 1000

Digital Data Transmission
With the HP Fiber Optic System
Fiber optics can provide solutions to many data
transmission system design problems. The purpose of this
application note is to aid designers in obtaining optimal
benefits from this relatively new technology. Following a
brief review of the merits, as well as the limitations, of fiber
optics relative to other media, there is a description of the
optical, mechanical, and electrical fundamentals of fiber
optic data transmission system design. How these
fundamentals apply is seen in the detailed description of
the Hewlett-Packard system. The remainder of the note
deals with techniques recommended for operation and
maintenance of the Hewlett-Packard system, with
particular attention given to deriving maximum benefit
from the unique features it provides.

bandwidth varies inversely as the square of the length,
while in fiber optic cable it varies inversely as only the
FIRST power of the length. Here are some typical values
for length, £ , in metres:
(1) f3dB= 12'gOO MHz for HFBR-3001 to 3005 cables

(2) f3dB= 225,000 MHz for typical

£2

son coax (RG-59)

For example, if Q = 100m, the 3dS frequency is only
22.5MHz for the coax cable, but for the fiber optic cable it
is 120MHz.
The limitations of fiber optics arise mainly from the means
for producing the optical flux and from flux losses. While
the power into a wire cable can easily and inexpensively
be made several watts, the flux into a fiber optic cable is
typically much less than a milliwatt. Wire cable may have
several signal "taps"; multiple taps on fiber optic cables
are economically impractical at present.

ELECTRICAL WIRE VS. FIBER OPTICS
I n fiber optic cables, the signals are transmitted in the form
of energy packets (photons) which have no electrical
charge. Consequently, it is physically impossible for high
electric fields (lightning, high-voltage, etc.) or large
magnetic fields (heavy electrical machinery, transformers, cyclotrons, etc.) to affect the transmission.
Although there can be a slight leakage of flux from an
optical fiber, shielding is easily done with an opaque
jacket, so signal-bearing fibers cannot interfere with each
other or with the most sensitive electric circuits, and the
optically-transmitted information is, therefore, secure
from external detection. In some applications, optical
fibers carry signals large enough to be energetically
useful (e.g., for photocoagulation) and potentially
harmful, but in most data communication applications,
economy dictates the use of flux levels of 100l'W or less.
Such levels are radiologically safe and in the event of a
broken or damaged cable, the escaping flux is harmless in
explosive environments wherea spark from a broken wire
could be disastrous. Jacketed fiber optic cables can
tolerate more mechanical abuse (crush, impact, flexure)
than electrical cables of comparable size; moreover, fiber
optic cables have an enormous weight and size advantage
- for equivalent information capacity. Properly cabled
optical fibers can tolerate any kind of weather and can,
without ill-effect, be immersed in most fluids, including
polluted air and water.

The losses in a point-to-point fiber optic system are
insertion loss at the input and output, connector loss, and
transmission loss proportional to cable length. Variations.
in these losses require a receiver with a dynamic range'
capable of accommodating these variations and yet able
to provide adequate BW (bandwidth) and SNR (signalto noise) ratio at the lowest flux level. Fortunately, no
noise is picked up by a fiber optic cable so the receiver
SNR at any SW is limited only by the noise produced
within the receiver.
Fiber optics is not the best solution to every data
transmission problem; but where safety, security, durability, electrical isolation, noise immunity, size, weight,
and bandwidth are paramount, it has a clear advantage
over wire.

FIBER OPTIC FUNDAMENTALS
Flux coupled into an optical fiber is largely prevented from
escaping through the wall by being re-directed toward the
center of the fiber. The basis for such re-direction is the
index of refraction, n1, of the core relative to the index of
refraction, n2, of the cladding.

Bandwidth considerations clearly give the advantage to
fiber optics. In either parallel- or coaxial-wire cable, the

Index of refraction is defined as the ratio of the velocity of
light in a given medium to the velocity of light in a vacuum.
380

SNELL'S LAW n,sinU, '" n2sinU2

sinVc =~ n2 < n,

NUMERICAL APERTURE

nOsinOA

n15in(90'- - Oel
n,cosOC
"' n, J1 - 5in20C

=

=

sinGe

=

N.A. = sinOA WHEN no = ,

~

N.A. '"
8e = CRITICAL ANGLE

=

v'n .,f2Xn
.

n, JT=Tn2Tn1T2

=~

FOR SMALL N.A.

N.A. DEPENDS
/MAINLYON
t.n=n,-n2

SinOA=~~=dov'n1+n2 ~

Figure 1. Snell's Law.

Figure 2. Tolal Inlernal Rellecllon.

As a ray oflight passes from one medium into another of a
different index of refraction, the direction changes
according to Snell's Law:

radiation patterns of optical fibers are not perfect step
functions at the acceptance angle. For this reason, the
practical definition of N.A. is somewhat arbitrary.

(3) n1 sin01 = n2 sin02

S-N-E-L-L'-S-L-A-W-'I

r"1

Modes of Propagation

This is illustrated in Figure 1. Notice that the relationship
between the angles is the same, whether the ray is incident
from the high-index side (n1) or low-index side (n2). For
rays incident from the high-index side, there is a particular
incidence angle for which the exit angle is ni nety degrees.
This is called the critical angle. At incidence angles less
than the critical angle, there is only a partial reflection, but
for angles greater than the critical angle, the ray is totally
reflected. This phenomenon is called TOTAL INTERNAL
REFLECTION (TIR).

Within the limits imposed by the N.A., rays may propagate
at various angles. Those propagating at small angles with
respect to the fiber axis are called LOW-ORDER MODES,
and those propagating at larger angles are called HIGHORDER MODES. These modes do not exist as a
continuum. At any given wavelength, there are a number
of discrete angles where propagation occurs. SINGLEMODE fibers result when the core area and the N.A. are so
small that only one mode can propagate.
In addition to high- and low-order modes, there are others,
called LEAKY MODES, which are trapped as skew rayspartly in the core, but mostly in the cladding where they
are called CLADDING MODES. As implied by the term,
leaky modes do not propagate as well as the more nearly
meridional modes; their persistence, depending mainly on
the structure of the optical fiber, ranges from less than a
metre to more than fifty metres. The presence of leaky
modes will, of course, affect the results obtained in
measurement of N.A. and transmission loss, making them
both artificially high. For this reason, N.A. is usually
specified in terms of the EXIT N.A. for a fiber of length
adequate to assure that leaky modes have effectively
disappeared.

Numerical Aperture.

Rays within the core of an optical fiber may be incident at
various angles, but TIR applies only to those rays which
are incident at angles greater than the critical angle. TlR
prevents these rays from leaving the core until they reach
the far end of the fiber. Figure 2 shows how the reflection
angle at the core/cladding interface is related to the angle
at which a ray enters the face of the fiber. The acceptance
angle, OA, is the maximum angle, with respect to the fiber
axis, at which an entering ray will experience TIR. With
respect to the index of refraction, no, of the external
medium, the acceptance angle is related to the indices of
refraction of the core and cladding. When the external
medium is air (no ~ 1 ), the sine of the acceptance angle is
called the NUMERICAL APERTURE (N.A.) of the fiber:

Since most leaky mode propagation is in the cladding, it
can be "stripped." Such cladding mode stripping is done
by surrounding the unjacketed fiber with a material having
a refractive index higher than that of the cladding. EXIT
N.A. is defined as the sine of the angle at which the
radiation pattern (relative intensity vs. off-axis angle) has
a particular value. This value is usually taken at 10% olthe
axial (maximum) value.

(4) NUMERICAL APERTURE, N.A. = sinOA
The derivation in Figure 2 applies only to meridional rays,
i.e., rays passing through the axis of the fiber; skew rays
(non-meridional) can also be transmitted, and these
account for the observation that the reception and

381

Transmission Loss

deliberately inserted to prevent scratch damage to the
fiber face and to reduce the variability of misalignment
loss; i.e., it is sometimes more important to make the
connector loss be consistent rather than low.

Regular core (non-leaky) modes also exhibittransmission
losses. These are due to (1) scattering by foreign matter,
(2) molecular (material) absorption, (3) irregularities at
the core/cladding interface, and (4) microbending of the
optical fiber by the cable structure. The first two loss
mechanisms depend on the length of path taken by a ray;
the third depends on the number of reflections of the ray
before it emerges. It is clear from Figure 2 that the higher
order modes have longer paths and more reflections with
consequently higher loss. Larger N.A. fibers permit
higher-order-mode propagation and, therefore, exhibit
generally a higher transmission loss. Transmission loss is
exponential and is, therefore, usually expressed in "d B per
km." Coupling loss consideration usually favors larger
N.A.

The use of a coupling medium is more significant when a
fiber is coupled to an LED or IRED source. These sources /
are usually of gallium arsenide, or related substances,
with a refractive index of 3.6. With such a high index of
refraction, the use of an epoxy cement can reduce
coupling loss by approximately 1dB. Figure 3 shows how
the flux coupling is derived. If the size of the LED is much
less than that of the fiber, a more effective technique is the
use of a tiny lens over the LED. If the size of the fiber is
smaller, the lens should be on the fiber, rather than the
LED.
Rise Time Dispersion

The three main loss mechanisms for coupling between
fibers or between fibers and the optical ports of other
devices are: (1) relative N.A.'s, (2) relative area of the
optical ports, and (3) Fresnel (reflection) loss. In addition
to these, there may be coupling loss due to misalignment
and/or separation of optical ports. Relative N.A. loss can
be ignored (~zero dB) whenever the N.A. of the receiving
port (fiber or detector) is larger than the N.A. of the source
port (flux generator or fiber), otherwise:

Bandwidth limitation in fiber optics is the result of a
phenomenon called DISPERSION, which is a composite
of MATERIAL dispersion and MODAL dispersion. Both of
these relate to the velocity of flux transmission in the core.
Velocity varies inversely as the index of refraction, and if
the index of refraction varies over the wavelength
spectrum of the source, the flux having a wavelength at
which the refractive index is lower will travel faster than
the flux having a wavelength at which the index is higher.
Thus, all portions of the spectrum of flux launched
simultaneously will not arrive simultaneously, but will
suffer time dispersion due to differences in travel time.
This is MATERIAL DISPERSION. It is reduced by using
sources of narrow spectrum (e.g., lasers) or fibers with a
core index of refraction which is constant over the source
spectrum.

N.A. of Source Port
(5) NA LOSS (dB) = 20 log N.A.of Receiver Port
Relative area loss can be ignored whenever the area of the
receiver port is larger than the area of the source port,
otherwise:
Diameter of Source
(6) AREA LOSS (dB) = 20 log Diameter of Receiver

In Figure 2, notice that rays moving parallel to the axis
travel a path length which is shorter than that of rays which
are not paraxial. Those rays propagating in the
higher-order modes will, therefore, have a longer travel
time than those in lower-order modes, and simultaneously
launched rays will suffer dispersion of their arrival iimes.
This is MODAL DISPERSION. It can be reduced only by
reducing the N.A. (smaller acceptance angle) to allow
only lower-order modes to propagate.

In applying equation (6) to coupling between Single fibers,
the diameter to be used is the CORE DIAMETER. If the
receiver port is a FIBER OPTIC BUNDLE, the "packing
fraction" loss must be added to the area loss, even when
the area of the bundle is larger than the area of the source
port.
(7) PACKING FRACTION LOSS (dB)=10 log Active Area
Total Area

LAMBERTIAN EMITTING PLANE WITHIN LED, STERANCE Le
SURFACE OF LED

"Active area" is the sum of areas of the cores of individual
fibers, and "total" area is that of the bundle.

/ r A I R ' OR OTHER MATERIAL

Fresnel loss occurs when a ray passes from one medium
to another having a different index of refraction. Part of the
flux is reflected; the fraction transmitted is described by
the transm ittance, r, so the loss is:

no

"2

CLADDING

",

CORE

sinBA '"

..Jnl~~ 02 2 =!'J~

(8) FRESNEL LOSS(dB)=10 log += 10 log
ne sinBe '" nosinliA '" N.A.

nx = index of refraction of medium x
ny = index of refraction of medium y

sinBe

=:

N~:.

INDEPENDENT OF no

FLUX COUPLED, ¢ '" 1TTLeAFsin20e

It is clear from equation (8) that the loss is the same in
either direction. If two fibers are joined with an air gap
between their faces, taking nx = 1 for air and ny = 1.49 for
the cores of the fibers, the fiber-to-air Fresnel loss is
0.17dB. The air-to-fiber loss is the same, so the total airgap
loss is 0.34dB. If several such connections are made, the
loss could be high enough to make it worthwhile to use a
coupling medium, such as silicone, to remove the air gap.
Often, however, connector loss comes mainly from a gap

LED-TO-CORE
TRANSMITTANCE
WITH AIR,

no =:

WITH EPOXY,

_(
T-

1.0,

no '"

4

2+~+~

r, '"

nO

ne

0.65

)(

4

2+~+~
"1

) _, (FRESNEL)
- LOSS

nO

10 log ~ '" 1.03 dB

1.5, 72 '" 0.83

EPOXY DOES NOT AFFECT ACCEPTANCE ANGLE BUT DOES REDUCE
FRESNEL LOSS

Figure 3. Acceptance Angle and Fresnel Loss Effects.

382

Construction of Fiber Optics

.'NLE;'

Fibers having a sharp boundary between core and
cladding. as in Figure 2. are called STEP INDEX fibers.
The reflection at the boundary is not a "zero-distance"
phenomenon - the ray. in being reflected. is actually
entering a minute distance into the cladding and there is
some loss. This loss can be seen as a faint glow along the
length of unjacketed lossy fibers carrying visible flux. To
reduce such reflection loss. it is possible to make the rays
turn less sharply by reducing the index of refraction
gradually. rather than sharply. from core to cladding. A
fiber of such a form is called a GRADED INDEX fiber and
the rays propagate as shown in Figure 5. Graded index
fiber has not only a very low transmission loss. but modal
dispersion is also very low. Higher-order modes do travel
longer paths. but in the off-axis. lower-index regions they
travel faster so the travel time differential between
high-order and low-order modes is not as large as it is in
step index fibers.

¢OUT

----90%

-

----10%

t

- - - 90%

----10%

.,N -(dBm) = 10 log (tP(mW)\ = 10 log (cJ> (j.lW) \
I: 1 mW;
\1000 j.lW)
Here is an example of how the flux budget works:

From the receiver flux requirement (for given Pel. the flux
which the transmitter must produce is determined from
the expression for a pOint-to-point system:

1. Transmitter
2. Receiver

cJ>T = 44j.1W
cJ>R = 1.6j.1W

Transmitter optical port:

>

10 log

3. aTC

tPR

diameter = 200j.lm. N.A. = 0.5

Optical fiber (in connector): core diam.
0.3

where tPT is the flux (in j.lW) available from the transmitter
tPR is the flux (in j.lW) required by the Receiver at Pe
"'0 is the fiber attenuation constant (dB/km)
Q is the fiber length (km)
"'TC is the Transmitter-to-Fiber coupling loss (dB)
"'cc is the Fiber-to-Fiber loss (dB) for in-line
connectors
n is the number of in-line connectors; n does not
include connectors at the transmitter and
receiver optical ports
"'CR is the Fiber-to-Receiver coupling loss (dB)
"'M is the Margin (dB). chosen by the deSigner, by
which the Transmitter flux exceeds the system
requirement

(cJ>T)= 14.39dB
= 100j.lm.

N.A.

=

= aA + aNA = 20 log ~~~~1 + 20 log (~:~)

= 6.02dB + 4.44dB = 10.46dB
Receiver optical port:

diameter = 200j.lm. N.A.

= 0.5

4. Because the diameter and N.A. of the receiver are both
larger than those of the fiber. there is only a small
amount of Fresnel loss. making aCR ~ 0.34dB
5. Apply equation (11) to see what the flux budget allows:
14.39dB = aoQ + 10.46dB
aOQ+ naCC

Equation (11) is called the FLUX BUDGET and it is
represented graphically in Figure 7. The same basic units
(watts) are used for flux and for power. so it is correct and
convenient to express flux in "dBm".

+ aM =

+ nacc + 0.34dB + aM

(14.39 -10.46 - 0.34)dB = 3.59dB

6. Assume a transmission distance of 35 metres at
20dB/km

384

If cable length selections are 10-, 2S-, and SO-metre
lengths and connector loss is ace = 2dB, then either of two
options may be chosen:

single +S-volt supply. All inputs and outputs function at
TTL logic levels. No receiver adjustments are ever
necessary because the dynamic range of the Receiver is
21dB or more, accommodating fiber length variations as
well as age and thermal affects. When the system is
operated in its internally coded mode, it has NRZ
(arbitrarily timed data) capability and is no more
complicated to operate than a non-inverting logic
element. Built-in performance indicators are available in
the Receiver; the Link Monitor indicates satisfactory
Signal conditions and the Test Point allows simple
periodic maintenance checks on the system's flux margin.

7. a) Use a 10m and 2Sm length with one connector:
ao~+ aee = (3Sm x 0.02dB/m) + 2dB = 2.7dB
This leaves aM = (3.S9 - 2.7)dB = 0.89dB
7. b) Use a 50m length and no connector:
ao~=

(50m x 0.02dB/m) = 1.0dB leaving aM =2.59dB

Unless there is some good reason (cost, convenience,
etc.) for choosing the 10m/2Sm option, it would be better
to select the 50-metre option because it allows a larger aM.
In flux budgeting, aM should always be large enough to
allow for degradation of the efficiency of the flux
generator in the transmitter (LED, IRED, laser, etc.). On
the other hand, in dealing with more powerful transmitters, aM must not be so large that it exceeds the
dynamic range of the receiver.

There are also several optical and mechanical convenience features. The optical ports of the Transmitter and
Receiver are well defined by optical fiber stubs built into
receptacles that mate with self-aligning connectors.
Low-profile packaging and low power dissipation permit
the modules to be mounted without heat-sink provision on
P.C. boards spaced as close as 12.5mm (0.5 in.).
The internally-coded mode of operation is the simplest
way to use the Hewlett-Packard system. This mode places
no restriction on the data format as long as either positive
or negative pulse duration is not less than the minimum
specified. The simplicity is achieved by use of a 3-level
coding scheme called a PULSE BI-POLAR (PBP) code.
This mode is selected simply by applying a logic low (or
grounding) to the Mode Select terminal on the Transmitter
- no conditioning Signal or adjustment is necessary in the
Hewlett-Packard Receiver because it automatically
responds to the PBP code.

Dynamic Range

The dynamic range of the receiver must be large enough
to accommodate all the variables a system may present.
For example, if the system flexibility requirement is for
transmission distances ranging from 10 metres to 1000
metres with 12.SdB/km cable, and up to two in-line
connectors, the dynamic range requirement is:
ao~=

r

1km x 12.SdB/km =
naee = 2 x 2dB =
aM =
thermal variations =

12.SdB
4.0dB
3.0dB
1.0dB(estimated)
20.5dB

Transmitter Description

Figure 8 shows symbolically the logical arrangement of
the Transmitter, waveforms for the signal currents IA and
IB, and the resulting waveforms for the output flux. The
arrangement shown is logically correct but circuit details
are not actually realized as shown. For example, the
current sources actually have partial compensation forthe
negative temperature coefficient of the LED (or IRED).ln
Figure 8, there are five important things to notice.

Accommodating a 20dB optical power dynamic range
plus high sensitivity requires the receiver to have two
important features: automatic level control, and a-c
coupling or its equivalent. The a-c coupling keeps the
output of the amplifier at a fixed quiescent level, relative to
the logic thresholds, so that signal excursions as small as
the specified minimum can cause the amplifier output to
exceed the logic threshold. This function can also be
called doc restoration.

First, notice that the bias current, Ie, is never turned offnot even when the Transmitter is operated in the
externally coded mode (Mode Select "high"). This is done
to enhance the switching speed of the LED (or IRED) in
either internally- or externally-coded mode. The bias
current also stabilizes the flux excursion ratio (k in
Equation 14) symmetry in the internally-coded mode.

ALC (automatic level control) adjusts the gain of the
amplifier. Low-amplitude excursions are amplified at full
gain; high-amplitude excursions are amplified at a gain
which is automatically reduced enough to prevent
saturation of the output amplifier. Saturation affects
propagation delay adversely so ALC is needed to allow
high speed performance at high, as well as low, Signal
levels.

Second, notice that

This procedure also yields the proper value of the highlevel flux,  )
Step 2
Step 1
It appears, from the waveforms in Figure 8, that the 500kHz
signal prescribed in Step 2 is not necessary; that is, with
Data Input at a steady-state high, the flux meter would
read -___+-{)6~T~~TONITOR

________

I

~

flux. With respect to the Receiver optical port, the
responsivity of the PIN photodiode is approximately
O.4A/W, leading to the expression:
rVTMAX - VTJ (mV)
(17)AVERAGE INPUT FLUX,ci>AV(I'W)= .
10

Flux budgeting, using the Hewlett-Packard Transmitter,
Receiver, Connector, and Cable components is very
straightforward for most applications. It is necessary only
to use the data sheet information correctly in making the
coupling loss and transmission loss allowances.

where VTMAX = Test Point Voltage with no optical input
signal.

When used with other Hewlett-Packard components, the
characteristics of the Receivers are not critical. Their
optical ports have a diameter and N.A. which are both
greater than the size and N.A. of the Hewlett-Packard
Cable. The Receivers also have a high responsivity and the
spectral response is nearly constant over the spectrums
radiated by Hewlett-Packard Transmitters.

The instrument for observing VT must not load the Test
Point significantly, so an input resistance of 10MO is
recommended.
As described above, when the input flux is at the average
level, the positive-going and negative-going output
voltages VP1 and VN1 are approximately equal. Notice that
this makes the outputs of both logic comparators low. A
positive flux excursion, rising faster than the dc restorer
(with its long time constant) can follow, will cause VP1 to
rise and VN1 to fall. If the positive flux excursion is high
enough, the LOGIC. HIGH COMPARATOR input voltage
(VP2 - VN1) becomes positive, and a SET pulse is produced
for the R-S flip-flop. [Similarly, a negative flux excursion
of such amplitude would make (VN2 - VP1) become
positive and a RESET pulse would be produced.J A larger
amplitude of positive flux excursion would make the
POSITIVE PEAK DETECTOR input voltage (VP3 - VN1)
change from negative to positive and cause current to flow
into the ALC FILTER capacitor. When the voltage VA
starts to rise above VREF, the ALC AMPLIFIER output will
operate on the GAIN CONTROL AMPLIFIER to limit the
Receiver's forward gain. Notice that the ALC action is the
same for a negative flux excursion, so that the Receiver's
gain limitation is determined EITHER by positive flux
excursion OR by negative flux excursion - whichever is
the larger. For this reason, the positive and negative
excursions must be nearly balanced with respect to the
average flux. The allowable imbalance is determined by
the values of the resistors in the negative and positive
voltage dividers. The ALC action limits the maximum
excursion to a voltage 10 (R1 + R2), whereas the logic
threshold is only 10 R1. Actual limits are established by the
tolerances on the resistors and current sources. Notice
that the ALC voltage, VA, activates both the ALC
COMPARATOR and the LINK MONITOR COMPARATOR. Therefore, a "high" LINK MONITOR signifies two
conditions:

With Components From Other Manufacturers

When using the Hewlett-Packard Receivers with other
cables, it may be necessary to account for N.A.loss and/or
area mismatch loss. When other sources are used, it may
be necessary to compute an effective flux ratio:
(18) EFFECTIVE FLUX RATIO, EFRs=
(Source Spectrum)

J ci>)..Rr)..dl\
J
ci>)..d)..

where Rr).. is the relative response of the Receiver (from
data sheet)
ci>1\ is the spectral flux function of the source
If the transmission loss of the cable varies sharply overthe
wavelength range of the source spectrum, then the
spectral transmittance of the cable should be included in
the computation of EFR. The spectral transmittance varies
with cable length, so the integration must be performed
using the cable length required in a particular installation:
JT)..ci>I\Rr)..d)..
(19) EFFECTIVE FLUX RATIO, EFRcs
JT'ci>'d'
(Cable and Source)
A
1\ A
where T).. is the spectral transmittance of a particular
length of fiber optic cable, computed as:
(20) T).. =10

-r ~10 lao)..

where ao).. is the spectral function in (dB/km) of the fiber
optic cable and Q is the particular cable length (km)
Notice that as the length is reduced, T).. becomes more
nearly a constant and may be factored out of both
numerator and denominator of Equation (19). When EFR
is significantly less than unity, it enters the flux budget
expression, Equation (11).

1. The input flux excursions are high enough to cause
ALC action (gain limitation).
2. The excursions are more than adequate for operation
of the logic comparator.

(21) 10 log ~:T ) = aTC + aCR + nacc + aoQ+ aM
R
-10 log (EFR)

Notice that the LINK MONITOR could be "high," but k
could be outside the specified limits such that Pe exceeds
10-9 . Conversely, because of safety margin in the Receiver
design, it is also possible to have Pe < 10-9 when the flux
excursions are too small to make the LINK MONITOR
"high".

See Equations 11, 18, and 19 for definition of terms.
The optical ports of Hewlett-Packard Transmitters are
designed for mating with Hewlett-Packard Cable/
Connector assemblies, but their characteristics require a
little more attention than do the Receiver optical ports.
The Transmitter and Cable/Connector data sheets should
be consulted for the correct values of size and N.A., or for
the directly-given value of transmitter-to-fiber coupling
loss, arc, to use in flux budgeting. In applications having
very short transmission distances, but requiring a number
of in-line (cable-to-cable) connections, it is likely to be
advantageous to use fiber optics of larger core diameter

OPERATION OF THE HEWLETT-PACKARD
SYSTEM
With Hewlett-Packard Components Exclusively

The main concern in a fiber optic link is the flux budget.
Other areas of concern are: data rate, data format, and the
interface with other elements of a data transmission
system.

388

at the "1" level; similarly, the signal remains althe "O"level
for consecutive "O's". With RZ (Return-to-Zero) codes, the
level periodically changes from high level to low level or
back, never remaining at either level for a period of time
longer than one bit interval. Some examples of codes are
given in Figure 10. Notice that NRZ code uses the channel
capacity most efficiently since it requires only one code
interval per bit interval. The RZ codes illustrated use two
code intervals per bit interval while other codes may
require an even higher channel capacity for a given data
rate. NRZ code requires a clock signal at the receiving end
to define, for each interval, the point in time at which the
data is valid. The time at which the data is clocked must be
sufficiently clear of the interval edges to avoid phase-shift
errors due to jitter, rise time, or propagation delay. Since
the clock signal is separately transmitted, phase shift in
the clock channel can contribute to the phase-shift error
unless it is equal, in direction and magnitude, to the
phase shift in the data channel. For this reason, fiber optiC

and N.A., such as some of the plastic types. The larger
core diameter reduces the likelihood of losses in
connectors due to misalignment. Depending on the size
and N.A. of the Transmitter optical port, a larger core
diameter and N .A. in the fiber optic cable may also reduce
arc, but if the cable core diameter is too large, the cable.. to-receiver loss, "'CR, may be excessive.

Data Rate and Format
The other areas of concern (data rate, data format, and
interface) are interactive, depending on system requirements. In any single transmitter-to-receiver link, the flux
budget along with probability of error Pe, establish the
signaling rate, in baud units, while the data rate, in bits per
second, depends also on the data format, or transmission
code. NRZ (Non-Return-to-Zero) is the term for a
transmission code in which the signal does not
periodically return to zero. If a stream of NRZ data
contains a series of consecutive "1's", the signal remains

I

I

I

LHJ

r

o

DESCRIPTION

CHANNEL
REOUIRED

REQUIRES
DC?

REQUIRES
CLOCK?

High during entire "mark". low

1 Mbaud per Mb/s

YES

YES

2 Mbaud per Mb/s

NO

YES

CODe

A
B

NON-RETURN TO
ZERO (NRZI
RETURN TO ZERO
(RZI

during entire "space" interval
low during entire "space",
momentarily high during "mark"

interval
C

MANCHESTER
(SELF·CLOCKING RZ)

Positive transition for "space",
negative transition for "mark"

2 Mbaud per Mb/s

NO

NO

0

BIPHASE MARK
(MANCHESTER II)

Each bit period begins with a
transition. "Space" has NO
transition during bit period -

2 Mbaud per Mb/s

NO

NO

2 Mbaud per Mb/s

NO

NO

"mark" has one transition during

bit period

BIPHA$E SPACE

Same as Biphase Mark except
"mark" and "space" reversed

NOTE THAT C, 0, E HAVE 50% DUTY FACTOR (k = 1.00)

Figure 10. Examples of NRZ and RZ Code Patterns.

389

channels carrying clock signals should use the same type
of cable and the same length, unless the transmission
distance is very short. Note that the transmission time
delay in an optical fiber depends on the core index of
refraction:
(22) TRANSMISSION DELAY, t£ =

System Configuration
The simplex arrangement in Figure 11 allows data in one
direction only, and the format should, therefore, include
error checks, such as parity bits. The full duplex
arrangement requires two Transmitter/Receiver (T/R)
pairs and two cables but allows data to go in both
directions simultaneously. If, at a given time, Station 1 is
transmitting, the return transmission from Station 2 can be
unrelated to the information from Station 1, but could also
be a relay or re-transmission of the data received by
Station 2, so a logic delay and comparator circuit in
Station 1 can check for errors and allow corrections. The
same is true for the full triplex arrangement. Extension to
larger numbers of stations is possible and the benefits are
the same, but the number of T/R pairs increase rapidly, as
shown by the series in Figure 11, requiring n (n-1) T/R
pai rs for n stations.

(+ )£ n

where c is the velocity of light in a vacuum, c=3x108m/s
£ is the fiber optic cable length (m)
n is the core index of refraction
and differential delay between a data channel and a clock
channel is:
(23) DIFFERENTIAL DELAY, t =H-) [£2n2 -£m1J

Some RZ codes are self-clocking - i.e., a separate
channel to transmit the clock signal is not required, so
there is no problem with differential delay. Forthis reason,
RZ codes may be preferred even though the data rate is
less than that of NRZ. Note that in its internally coded
mode, the Hewlett-Packard fiber optic system transmits
either NRZ or RZ codes of arbitrary format and duty factor.
In the externally coded mode, the system requires the
code to be RZ; moreover, the duty factor of the code must
be SO% and the signal must remain LESS than S!-,s in either
high state or low state.

Half-duplex (not illustrated) is a means for allowing two
stations to alternately use the same transmission medium.
With a wire cable, half-duplex operation is commonly and
easily done; it can also be done with fiber optic cable but
the fiber-furcating couplers for accomplishing it are very
lossy, are not commonly available, and will not be
discussed.
Data interchange among a large number of stations can be
accomplished with fewer T/R pairs by using the Master
Station Multiplex (MSM) arrangement in Figure 12. The
MSM arrangement requires only 2(n-1) T/R pairs for n
stations (master + (n-1) slaves). Its operation differs from
the full n-plex arrangement of Figure 11 in that only the
master station transmits directly to all other stations. Data
from any slave station is transmitted to master and retransmitted to all slave stations according to the "retransmit enable" (E, ... Ex) selection made in the master
station. Thus, a complete error check is possible.
Regardless of how many slave stations are added, the
transmission delay from any slave to any other slave is just
the delay of two fiber optic links plus the propagation

The Hewlett-Packard system is capable of a 10 Mbaud
signaling rate. If a higher data rate is required, the data
stream can be divided among additional channels. If each
channel is RZ coded, such as with Manchester code, the
capacity of each channel is 5Mb/s and if the total data rate
requirement is 20Mb/s, four channels are required. Using
NRZ, the 20Mb/s data can be transmitted on two channels,
with a third channel for the clock signal. Thus, if the data
rate requirement exceeds 1SMb/s, the NRZ format
requires fewer fiber optic channels.

NO. OF
STATIONS

NO. OF

T/R PAIRS
2

SIMPLEX

12
20
n(n-1)

FULL DUPLEX

FULL TRIPLEX

Figure 11. Simplex, Full-Duplex, Full Triplex, Full-n-plex Fiber Optic Links.

390

MASTER TRANSMIT ENABLE
MASTER DATA IN

SLAVE

EM

STATIDNS

DM
R
E,

E, ... Ex SLAVE
RE - TRANSMIT
ENABLE

T

D,
E2

R

D2

T

D, . . Ox DATA OUT
{FROM SLAVES}

E3

D3
MASTER STATION

T

FOR n STATIONS. NO. OF T/R PAIRS'" 2(n-1)

Figure 12. Master Station Multiplex Arrangement for Fiber Optic Links.

(

delay in the master station's relay circuit. The time delay
between re-transmission from the master and the
error-check return transmissions from the slaves is the
same if each link length is the same, i.e., two links plus
relay time. Notice that a complete error check requires
an error check in the master, plus an error check in the
station where the data originated. Another feature of the
MSM system is that any slave station can be disconnected
or turned off without affecting the other stations. With
slightly more complicated relay control logic in the master
stations, the MSM system can provide even more
flexibility in the control of data movement - the
schematic in Figure 12 is intended only to illustrate the
potential flexibility of MSM.

that an error check is required only at the station from
which the data originates. There are some disadvantages.
A relatively minor disadvantage is the data delay around
the loop to where the data originated. A less minor
disadvantage is the fact that, even if one of the stations in
the loop is desig nated for loop control, it does not have
control as absol ute as that of the master station in MSM. A
major disadvantage is that removal of one or more stations
from the loop may require a re-run of the fiber optic cable
unless the flux budget allows insertion of a connector to
replace the station(s) removed. There is some error
accumulation around the loop, but this is not a
disadvantage if error correction is applied.

At the expense of less flexibility and longer transmission
delay, multiplex operation can be done with an even
smaller number of T fR pairs by means of Looped-Station
Multiplexing (LSM) as in Figure 13.ln addition to requiring
only n TfR pairs for n stations, LSM offers the advantage

Where error correction is inconvenient or impossible, the
accumulation of error through data relay units may be
significant. With Hewlett-Packard components operated
within the limits prescribed by the data sheet parameters
and the flux budget, any pOint-to-point link has a

Error Accumulation

WHEN 'TRANSMIT ENABLE' IS HIGH,
THE SIGNAL AT 'DATA OUT' IS
RE·TRANSMITTED WITHOUT INVERSION.

DATA IN/OuT-------~

r-------~~---~DATAOUT

->.::--;

DATA OUT_...._ _ _ _ _

OPEN - COLLECTOR

..........- - - - - - - D A T A IN

OUTPUT IS ReQUIRED

FOR n STATIONS. NO. OF r/R PAIRS::; n

Figure 13. Looped-Stations Multiplex Arrangement lor Fiber Optic Links.

391

probability of error Pe < 10-9 . This means that Pe < 10-9 as
long as the loss margin, "'M(dB) is above zero. With a
number, n, of repeater links, the worst case estimate of
cumulafive probability of error is the RMS value:

Figure 14. Lock Nut clearance could also be provided by
an opening in the board, or by using washers of 1mm
thickness on the #2-56 mounting screws to space the
Module bottom 1mm from the board. Screws entering the
#2-56 tapped holes MUST NOT TOUCH BOTTOM AS
THIS MAY DAMAGE THE MODULE. The #2-56 tapped
hole is 5.6mm (0.22 in.) deep, which provides an ample
purchase on the thread.

(24)CUMULATIVE PROBABILITY
OF ERROR,
n
n
Pe,n = 1 (1 - Pe,;) ~
Pe,;
;=1
;=1
where Pe,; is the probability of error in link "i"

L:

IT

P.C. Board
Thickness

Recommended
Screw Length - mm (In.)

If each link has the same probability of error, Pe, then the
cumulative value of Pe is estimated at:

mm

in.

W/O Spacer

W/1-mm Spacer

(25) CUMULATIVE PROBABILITY OF
ERROR FOR EQUAL Pe'S

0.79
1,59
2.38

1/32
1/16
3/32

4.78 (.188)
6.35 (.250)
6.35 (.250)

6,35 (.250)
6.35 (.250)
6.35 (.250)

Pe,n

~

nPe

However, as in any chain, the probability of error is usually
just that of the "weakest link," that is, the link having the
highest probability of error.

The #2-56 holes near the front of the package are the only
screw holes that may be used for mounting the module.
UNDER NO CIRCUMSTANCES MAY THE SCREWS
ALREADY INSTALLED OR THE SET SCREW BE
DISTURBED. Disturbing these may cause interior
damage.

Measuring the probability of error can be very timeconsuming if Pe has a very low value. For instance, if Pe =
10-9 at 10 Mbaud (BER = 10-9), this suggests that if the
system is operated for 100 seconds at 10 Mbaud
(accumulate 109 bits) with one error, the Pe = 10-9 is
verified. This is not necessarily true. The significance of Pe
= 10-9 is that over several such periods the average error is
one per 100 seconds. A less time-consuming procedure is
to lower the signal (flux) level until the error rate, Pe,N is
measurably high in a comfortable period of time, and note
this flux level as cPN' the Noise measurement flux level. The
operating flux level is deSignated cPo, and is found from the
ratio:

For additional support, the electrical leads may be bent
down and soldered into the P.C. board. In bending the
leads, care must be taken to avoid strain at the point where
the leads enter the glass seal. This can be done by
applying mechanical support between the module and the
bending point which should be at least 1.0mm (0.04 in.)
from the end of the module. A needle-nose pliers can also
be used to bend the leads individually, providing no
bending moment is transferred to the seal. See Figure 14
for details fo these techniques.

26. Xo = cPo and Xo = XN cPo
XN
cPN
cPN
and from the complementary error function:

Panel mounting can also be used. This is an especially
attractive mounting when R.F. shield integrity must be
maintained. As seen in Figure 15, the panel thickness must
be less than 4mm (5/32 in.) and have a counter-bore to
receive the Lock Nut. This will make the mounting secure
and leave enough of the Barrel outside the panel to permit
installation of an external mounting nut as well as the
Cable Connector.

Pe = erfc (Xo) = 1 - erf(Xo) calculated for cPo
Pe,N = erfc(XN) = 1 - erf(XN) measured at cPN
erfc(X) ~ .54 (f-X 2 ) for Pe < 10-4
X
This measurement and relationship can be useful in
evaluating the relative merits in the tradeoff between
running a single link over a long distance versus operating
with one or more repeaters. The use of repeaters usually
yields the lower Pe, but may be "overkill" in some cases.

Fiber OptiC Cable Connections
The data sheet cautions against disturbing the Lock Nut.
and Barrel. This is to prevent damage by someone who
has not read the following material:
As seen in Figure 16, there is a clearance between the
interior end of the Barrel and a shoulder on the Fiber
Alignment Sleeve. If this clearance is not maintained,
there is a risk that a force applied to the Barrel may be
transmitted by the Fiber Alignment Sleeve to the optical
fiber stUb, forcing the stub against the face of the source
or detector. The source (or detector) is an extremely
fragile semicondUctor device and even a very small force
can cause severe damage. Should it be necessary to
remove the Lock Nut and Barrel, they should be
reinstalled with this procedure:

INSTALLATION, MEASUREMENT, AND
MAINTENANCE
The shielded metal packages of Hewlett-Packard Fiber
Optic Modules are very sturdy and can be mounted in any
position. Both Transmitter and Receiverdissipate very low
power, so heat Sinking is not required. A cool location is
preferred, especially for the Transmitter. The main
concern in selecting the locations of both modules is
accessibility of the optical ports.

1. Lightly and carefully thread the Barrel into the Module
body until it comes against the shoulder of the Fiber
Alignment Sleeve.

Mounting
The preferred mounting is with two #2-56 screws on a
printed circuit board. Clearance must be provided for the
Lock Nut, which protrudes 0.5mm to 1.0mm (depending
on angular pOSition) beyond the plane of the module's
bottom surface. The usual way to deal with this is to allow
the Lock Nut to overhang the edge of the P.C. board as in

2. Back the Barrel OUT ONE FULL TURN, then HOLD
THE BARREL FROM TURNING while seating the Lock
Nut securely against the body. During final tightening
of the Lock Nut, the Barrel may be allowed to enter no
more than HALF A TURN.

392

ANDL~~=~

~

DO NOT BEND WHERE
LEAD ENTERS

II ......--------~~

SUPPORTS FOR"",
LEAD BENDING
~

--I ~>1mm

NEEDLE
NOSE
PLIERS

WAW""~w.~~l'J~
I I
- - . 11 mm
MAX

__

EDGE OF
BOARD

p.e.

4~I Ir--

'mm
SPACER

5mm
MIN

--j

Figure 14. Lead Bending and P.C. Board Mounting.

opposite ends of the sleeve to have slightly different
diameters and yet be firmly aligned by the curved interior
wall. A chamfer on the edge ofthe Ferrule aids insertion. In
making temporary Cable-to-Cable connection, it is
permissible, and often convenient. to omit the Barrel.
since it does not perform an alignment function. When the
Barrel is used for a more sturdy jOint. the connection
procedure is:

LOCK NUT
CLEARANCE COUNTERBORE
FROM REAR

7.5mm DIA. x 2.Omm DP

#10 - 32
EXTERNAL

~"'--'--- MOUNTING NUT

1. Install the Sleeve and Barrel on one Connector. using
only FINGER TIGHTNESS of the Coupling on the
Barrel.

(NOT SUPPLIED
WITH UNIT)

2. Start the Ferrule of the second Connector into the
Sleeve.

4.1mm (.16 in.)
MAX

Figure 15. Panel Mounting.

3. Engage the Coupling on the Barrel threads and tighten
FINGER TIGHT.

When Hewlett-Packard Cable Connectors are jOined,
either to each other or to the optical port of a Transmitter
or Receiver, there is a cylindrical spring Sleeve that aligns
the Ferrules. This is shown in Figures 16 and 170lt may be
difficult to see, but the Sleeve does have a slightly
flattened "leaf" on either side of a notch. The notch makes
the leaves spring separately, allowing the Ferrules at

Alignment of the Ferrules (and hence the fiber optics) is
performed by the Sleeve; the Barrel and Couplings are
intended only for tensile support. but if they are OVER
tightened, they may cause misalignment. Loss of coupling
due to misalignment can be observed at the VT (Test
Point) on the Receiver when the System is active:
t!.VTlt!. ~ 10mVlp.W.

BARREL
BARREL

SOURCE OR DETECTOR·

INTERNAL11CLEARANCE

FIBER ALIGNMENT SLEEVE
SHOULDER (BARREL MUST NOT
APPL V PRESSURE HEREI

Figure 16. Opto-Mechanical Structure of T/R Module••

393

COUPLINGS

BODIES

Figure 17. In-Line Connector Arrangement.

The procedure above applies also to making Cable
connection at the Receiver and Transmitter, except that
the Sleeve and Barrel are already installed. In manufacture, the Sleeve in the Module is pre-stressed for a
tighter fit on the Ferrule in the Module than on the Ferrule
in the Connector. The Sleeve is not likely to be pulled out
when the Module is disconnected, but if that does happen,
it can be reinstalled without removing the Barrel by using
the Connector Ferrule to guide and support it.

and 750) inputs and outputs. The outputs have adequate
voltage swing to drive the Fiber Optic Transmitter Data
Input, but ringing may occur unless the signal line is
properly terminated. The low-impedance inputs require a
buffer amplifier between the Receiver output and the Error
Detector input. Here also the voltage swing is ample, so a
simple emitter follower will do as a buffer.
With Mode Select "low" (on the Fiber Optic Transmitter),
the Word Generator may be set for either NRZ or RZ code,
and there is no restriction of any kind on word length or
composition (pseudo random or selected). With Mode
Select "high", the code selection can be either NRZ or RZ
but in either code the word composition must be such that:

In connecting fiber optics other than those from'HewlettPackard to a Hewlett-Packard module, it is necessary to
center the fiber in a cylinder with the same outside
diameter as the Hewlett-Packard Ferrule over a length (to
first shoulder) equal to half the length of the Sleeve, i.e.,
3.5mm. This is adequate for a temporary connection. For a
more permanent connection, add a coupling to fit the
#10-32 thread on the Barrel.

2. Duty factor: .44 < OF < .57 or .75 < k < 1.25

Power Supply Requirements

The first condition can be examined with an oscilloscope,
but if word length is such that:

1. No interval> 51'S of consecutive marks or consecutive
spaces

Power supply lines for the Transmitter and the Receiver
should each have a pi filter of two 60l'F shunt capacitors
and a 2.21'H «10) inductor. The Transmitter needs this
filter to prevent transients from reaching other equipment
when the LED (or IRED) currents are switched. The
Receiver needs the filter to keep line transients from
interfering with its extremely sensitive amplifier. In
addition, the Receiver may need its own regulator, as
shown in the data sheet, to prevent low-frequency
transients or ripple from interfering with the data stream. If
a regulator is used, the pi filter should be between the
regulator output and the Receiver supply terminal. The
Transmitter needs no regulator if the supply voltage is in
the specified range.

word length (bits)
data rate (bits/second)

< 5 microseconds

then there is no way that any consecutive marks or spaces
can extend over 51'S.
The easiest way to check duty factor is by observing k
directly on an ac coupled oscilloscope: first establish the
baseline position (e.g., center of scope face) with zero
signal input, then with the data signal applied:
k = excursion above baseline position
excursion below baseline pOSition
where the oscilloscope deflects upward for positive input.
For this observation, the oscilloscope need not be
synchronized - it could be free-running. The word
composition should be adjusted to bring k within the
specified limits. The word composition can be adjusted by
adding zeroes, changing word length, or by handselecting
the bit sequence.

System Performance Evaluation

System performance checks may be done by using errordetection equipment, such as the Hewlett-Packard Mod.
3760A Word Generator and 3761 Error Detector as
indicated in Figure 18. The Mod. 3780A Pattern
Generator/Error Detector which contains both word
generator and error detector is also usable, although it has
less flexibility in word generation and a lower data rate
capability. These instruments have low-impedance (500

Either error detector has two modes of operation:
BER (Bit Error Rate) mode and "count" mode. The count
mode is simplest to use and gives an earlier indication of
the result of any system adjustment.
.

394

r--

1--0 CLOCK

/101:. COUPLED
OSCILLOSCOPE
TO CHECK ON
DUTY F/IoI:.TOR

HP 3761A
ERROR DETECTOR

DATA

~

HP 3760A
PATTERN GENERATOR

'--

1--0 OUTPUT

HP 3780A
PATTERN
GENERATOR

HP 1740A

VERT

ERROR
DETECTOR

GENERATOR

RCVR

~---'---~I

~

CLK

CLK DATA

DATA

+5V

+5V

....
I"'lDATA
50n

lOOn

-:....
-

L
RECEIVER I

11m

D

~

_

J

J

~ ~TRANSMITTER

DATA
]

GENERATOR AND DETECTOR MUST
HAVE MATCHED WORD LENGTHS
AND DATA/DATA SELECTION.

lson

7sn

-

Figure 18. Bit Error Rate Measurement Arrangement.

With the System at normal operating flux level, the error
rate is so low that it would take several hours or even days
to make an accurate BER measurement. If the flux level is
reduced, SNR falls and BER rises until it becomes
measurable. Then the error function [see Equation (26)]
can be applied to determine the BER at the normal flux
level in terms of the ratio OIN where <1>0 is the operating
flux level and N is the flux at the reduced level where the
BER was measured. The problem now is that N may be
too low to measure with equipment at hand. The solution
is in the Receiver Test Point voltage, VT, which varies
linearly as Receiver input flux - see Equation (17). But
even this method has limits; when the flux becomes a
small fraction of a microwatt, the voltage difference
(VTMAX - VT) cannot be accurately observed. The solution
to this problem is in the Transmitter-to-Cable connection.
Just back off the Coupling, noting the number of turns
while observing VT, then plot a curve like that of Figure 19.
The curve is quite repeatable if care is taken to avoid
backlash and rotation of the Connector Body (rotate
Coupling only) but the curve is not the same for each
System.

(27) aM(dB) = aN - 10 log 25!FOR GIVEN Pe
XN
Absolute flux levels at "N" turns can be found by
measuring the flux level when N =0 and applying a ratio. A
rough measurement can be made using the Test Point
voltage, VT, and Equation (15). A more precise
measurement requires a calibrated radiometer, such as
the EG&G Mod. 550, used as shown in Figure 20a. With its
"fiat" filter instaliE/d, the EG&G Mod. 550 reads the radiant

20r------r-----.-----~

18
16

14
•

12

iii
3

I

~;; 10 log VTMAX - 'Ira
V,MAX -VTN

10~---------4~---------+----------~

Operating Margin Measurement
The flux budget margin, aM' for a given Pe can be found
using the Connector on the Transmitter as an adjustable
attenuator as described above, proceeding as follows:

4

1. Prepare a curve similar to Figure 19.
2. Count the turns, N, needed to get measurable error,
PeoN.

N - NUMBER OF COUPLING TURNS

3. Find aN(dB) from N and the curve from Step 1.
4. Find XN from eric (XN) = PeoN (measured).
Figure 19. Flux Decoupllng by Rotation of Connector Coupling.

5. Find Xo from eric (Xo) = Pe (given).

395

J

" " - - - - - - - - - - - - - - d (> 100mm)

LOCATION
OF FERRULE
FACE

7mmr

REMOVABLE 'FLAT'
'\
550-2 PROBE
FILTER~rl-+_--'-==;_--., ASSEMBLY

TRANSMITTER

{

REF. MARK

~---~~ ---I~.~(.-W-h-d-.-E~.~(~.W-I-.-m-2)-X-d-2-(-.m_2_)
__

_ _ _ _ _ __

GENERAL PROCEDURE:
USE SUBDUED AMBIENT. FOR EACH OBSERVATION Ea

=

DifFERENCE IN READINGS

OBTAINED WITH TRANSMITTER POWER SUPPLY ON AND OFF,

I, OBSERVE E, (.W/.m21 WITH 'FLAT' FILTER IN PLACE
2. OBSERVE E2 (.W/.m21 WITH 'FLAT' FILTER REMOVED
FILTER TRANSMITTANCE:

1'F' E, I E21

'-'---'~r - - - - - - - - ,

AVERAGE FLUX FROM TRANSMITTER:

rp (,uW) '"

[E1(~J [d2(Cm2~

[(t)MAX]

(fJMAX IS THE MAXIMUM VALUE OF THE RADIATION PATTERN INTEGRAL:

rlgl

(SEE DATA SHEET)

(a) MEASUREMENT OF TRANSMITTER AVERAGE FLUX

COUPLING

{'_'rr~~

PROTECTIVE GLASS
OVER DETECTOR
DETECTOR AREA

r

A o "'1cm2

REF.
MARK

TRANSMITTER
CONNECTOR

GENERAL PROCEDURE SAME AS ABOVE

3. WITH TRANSMITTER CONNECTOR SEATED, CENTER RECEIVER CONNECTOR OVER DETECTOR,
THEN POSITION AGAINST GLASS. (DO NOT SLIDE - SLIDING MAY CAUSE SCRATCH DAMAGE.)
OBSERVE Eo (pW/cm2 ),
4. WITHOUT ROTATING THE BODY, ROTATE THE COUPLING BY SMALL INCREMENTS Of TURNS,
NOTING THE NUMBER OF TURNS."N, AND FOR EACH VALUE OF N: OBSERVE EN I,uW/cm2),

RECEIVER INPUT FLUX, AT OPERATING LEVEL

4>0 ,"W). [Eo

FLUX f)ECOUPLING (SEE FIG. 191

I

~W{;;:I!~~'l,~)m211

.N· 10 109,o(Eo I EN I

(b) MEASUREMENT OF AVERAGE RECEIVER INPUT FLUX AND FLUX DECOUPLING AT TRANSM[TTER CONNECTOR.

Figure 20. Flux Measurement with EG&G Mod 550 Radiometer.

396

incidance, E, in W/cm2 on an aperture area, AD = 1 cm2
and N.A. = 1. With the filter removed, a fiber optic cable
can be placed so close to the aperture that there is no flux
loss, and since the radiometer N.A. exceeds the fiber N.A.,
the radiometer will have a reading in W/cm2 which is
numerically equal to the flux in watts. However, a
correction must be made for the removal of the filter.

Equation (15). The upper and lower margins on k for a
particular Receiver can be found by operating the
Transmitter with Mode Select "high" and a rectangular
signal (f = 500kHz) at Data Input. As the duty factor of the
signal is varied, the limits on k are found as those at which
the Receiver fails to follow the Data Input signal.

The insertion loss of the filter must be evaluated at the
measurement wavelength because it varies with wavelength to compensate for spectral variation in the
response of the silicon detector. The arrangement shown
in Figure 20 for measurement of radiant intensity is a good
one for measuring insertion loss of the filter. Two
observations are made - one with and one without the
filter. Error due to ambient radiation is avoided by working
in subdued ambient and for each observation taking two
radiometer readings (source off and source on); the
difference in readings is the observation of the radiant
incidance, Ee, produced by the radiant intensity, Ie, of the
source. The ratio of the two observations gives:

(31) k=(..!..)-1=
ftp
ftN

- 1

where ftp is the positive-pulse duty factor
ftN is the negative-pulse duty factor
Changes in k do not affect externally-coded mode
performance, and if this mode is used, then flux margin,
aM' is the only concern.
Corrective Maintenance

(28) FILTER INSERTION LOSS, a

= 10 log Ee(filter out)
F
Ee(filter in)

Trouble in the System may range from complete
breakdown to excessive BEA. The flux used in the
Hewlett-Packard System is visible so the cause of
complete breakdown can sometimes be localized by
Simply looking at the output of the Cable and the
Transmitter. If there is visible output from the cable, then,
when the Cable is connected to the Receiver, there should
be an 8mV change in Test Point voltage, Vr, as the
Transmitter (Mode Select "low") is turned on and off by
switching Vee. If 6.Vr is more than 8mV but the system is
not working, then either the Receiver logic is not
functioning properly or the flux excursion ratio, k, is either
too high or too low. Excursion ratio can be checked as
described above, using Vr. If k is satisfactory, the logic
malfunction could be due to incorrect supply voltage or
output loading.

This same arrangement can be used to measure the
average flux of the Transmitter as shown in Figure 20b.
From the observation of Ee with the filter IN:

(29) AVERAGE INTENSITY,

le~)=Ee~:~x d2 (cm2)
~

(30) AVERAGE FLUX, 8 mV by
the method described above indicates normal flux level).

SYSTEM MAINTENANCE

r

Preventive Maintenance

Long-term degradation occurs in any LED and LED
degradation affects the Hewlett-Packard Fiber Optic
System in two ways: reduced average flux, affecting either
externally- or internally-coded mode, and altered flux
excursion ratio, affecting only the internally-coded mode.
Significant degradation of either the flux or the flux
excursion ratio can be detected by regular observation of
the flux margin, aM, and of k.
is evaluated as explained under Operating Margin
Measurement from Equation (27). A plot of aM against the
logarithm of the cumulative hours of operation will allow
an estimate to be made of the operating time remaining
until aM = 0 FOR THE Pe DESIRED.

aM

k must be evaluated by measuring 1 and 2. DBIN and
iNA are used to specify a memory read or write. The 8080A
microprocessor provides several other control lines which
are usually decoded with DBIN and WR to generate compOSite control signals MEM R (Memory Read), MEM W
(Memory Write), I/O R (I/O Read), and I/O W (I/O
Write). Since the alphanumeric display subsystem is an

399

output of the microprocessor system, the timing between
the Address Bus, IData Bus, and WR is of particular
significance. This timing is generalized in Figure 2.
I

I':

.-----tcvc

foo:

.'...1
:.

:

.2

I

I

__

I

twA

I

I

DATA BUS

L

r-

r
I

I
I

~!~:______

~

I

:.

:"

I
.1

i

!

!I II

VALID ADDRESS

I

VALID ADDRESS
i
tAW - - - - - - . ,

I'4"-'-tEH~
I

'
I !;

ADDRESS BUS

,.

I

~r- '_AD_~~I____~I

., ' ..._ - - !

ADDRESS BUS

1':

tUT

VALID DATA

I

----J

DATA BUS
10BE·"1

l+-

! II

r-r-

~tDW~

two-...l

------il
I

I

6800 MICROPROCESSOR

.,

'AH

'2

tcvc '" 1000

630

30

225

,0

80

68AOO. 'eve' 668

420

30

80

10

70

68800. 'eve' 500

2S0

30

60

,0

MINIMUM TIMES (ns)

8080 MICROPROCESSOR
WITH 8228 CLOCK

MINIMUM TIMES (ns)
tAW
twA
twD
'DW

8080A, tCY- 480

740

90

230

90

6800.

8080A·2, tey '" 380

560

80

,40

8080A-'. fev' 320

470

70

"0

tAW' 2'eV-'D3-1'40(AI. '30IA-21. "O(A-lII

t, (MINI- 'IJT(MINI- 'AD(MAXI

tWA = two

'2(MINI • 'EH (MINI- 'DDW (MAXI

'" t03 + 10

tow • 'ev -'D3 -1'70(AI. '70(A-21. ,So(A-,1I

From MOTOROLA Semiconductor MC6800 Data Sheet

From INTEL Component Data Catalog, 1978

(OS94711.1978

Figure 2. Memory Write Timing for the Intel 8080A
Microprocessor Family

...

Figure 3. Memory Write Timing for the Motorola 6800
Microprocessor Family

The 6800 microprocessor has a 161ine Address Bus, 81ine
Data Bus, and a Control Bus that includes the signals VMA
(Valid Memory Address), R/W (Read/Write), DBE (Data
B.us Enable), and clock Signals q,1 and q,2. R/W specifies
either a memory read or write while VMA is used in
conjunction with R/W to specify a Valid Memory Address.
DBE gates the internal data bus of 6800 into the Data Bus.
In many applications, DBE is connected to q,2. The timing
between the Address Bus, Data Bus, VMA, and R/W (when
DBE = q,2) is shown in Figure 3. Additional data hold time,
tH, can be achieved by delaying q,2 to the microprocessor
or by extending DBE beyond the falling edge of q,2.

REFRESH CONTROLLER
The REFRESH CONTROLLER circuit depicted in Figure4
is designed for interface to either 6800 or 8080A
microprocessors. This circuit operates by interrupting th€;'''
microprocessor every two milliseconds to request a new
block of display data and column select data. Display data "
is loaded from the data bus into the serial input of the
HDSP-2000 via a 74165 paraliel in, serial out shift register.
The 74LS293 counter and associated gates insure that
only seven clock pulses are delivered to the shift register
and the HDSP-2000 for each word loaded. Column Select
data is loaded into a 74174 latch which, in turn, drives the
column switch transistors. The circuit timing relative to
the microprocessor clock and I/O is depicted in Figure 5.

The ASCII to 5 x 7 dot matrix decoder used by the
REFRESH CONTROLLER and DECODED DATA CONTR,oLLER is located within the microprocessor program.
ThiS decoder requires 640 bytes of storage to decode the
128 character ASCII set. The decoder used by these
controllers is formatted so that the first 128 bytes contain
column 1 information; the next 128 bytes contain column 2
information, etc. Each byte of this decoder is formatted
s~ch that D6 through Do contain Row 7 through Row 1
display data respectively. The data is coded so that a
HIGH bit would turn the corresponding 5 x 7 display dot
ON. This decoder table is shown in Figure 20. The
resulting 5 x 7 dot matrix display font is shown in the
HDSP-2471 data sheet.

The 6800 software necessary to support this interface is
divided into two separate subroutines, "RFRSH" and
"LOAD" (Figure 6). This approach is desirable to minimize
microprocessor involvement during display refresh. The
subroutine "RFRSH" loads a new set of decoded display
data from the microprocessor scratch pad memory into
the interface at each interrupt request. The subroutine
"LOAD" is utilized to decode a string of 32 ASCII
characters into 5 X 7 formatted display data and store this
data in the scratch pad memory used by "RFRSH".

400

,~

Vee

Vee

Vee

~,.~ ~ I!II 1,)j

8080A -----+~
4>2
1/0 WRITE

8080

>
'6800 1

A3

I

A4-~;;i.'I>C~

~

1

'-'

I

4>1

4>1

TO 6800

6800

1

VMA
A12
A13
A15

r!
--------;.!jpJ}
=

"

A14

vee!

74LSI38

1
Ao 2

----...

Vee~

4>2

,~

~"~-~
8

AI 3
A2

~

4

3
TO

INTERRUPT
REQUEST

~

8

220K

7
NE

555
TIMER

27K

---0

.01,...1

MC3459

2211

lK

TO~~vee

Figure 4. 6800 or B080A Microprocessor Interface to the HDSP-2000 REFRESH CONTROLLER

-=
500 HZ ASTABLE MULTIVIBRATOR

B080A MICROPROCESSOR TIMING

DATA BUS

I

I

I-_ _ _...J

S/L74165

:

~~~---~---~----~---~I-----~--------~-------------I

I

6BOO MICROPROCESSOR TIMING

I

.

.

I

ADDRESS BUS

~'I

DATA BUS

SIL 74165

~-----r------r-----~----~--~--+------r-----------1

I

1
1

I
1

1
_ _ _..,'

HDSP-2000CLOCK
HDSP-2000 DATA

I

I
I

DATA ENTRY TIMING
1

I

1

I

~r--

R
I

O

I

I

I

f

I

r--

i~

Figure 5_ REFRESH CONTROLLER Timing

Figures 7a and 7b depict two different software routines
for interfacing the REFRESH CONTROLLER to an 8080A
microprocessor. The two subroutines shown in Figure 7a
are functional replacements for the 6800 program shown
in Figure 6. The programs shown in Figures 6 and 7a
require a Sn byte scratch pad memory where n is the
display length_ The routine in Figure 7b eliminates this
scratch pad memory by decoding and loading data each
time a new interrupt request is received.

in-line code to access data from the buffer and output it to
the display. This program requires 3.7% + .SOn% of the
available microprocessor time for a. 1MHz clock. Th£
program shown in Figure 7a is similar to the one shown in~'
Figure 6, except that it uses a program loop instead of the
in-line code. This program uses S.4% + .93n% of the
microprocessor time for a 2MHz clock. These programs
utilize a subroutine "LOAD" which is called whenever the
display message' is changed. This subroutine executes in
10.2ms and 7 _Sms respectively for Figure 6 and Figure 7a_
The program in Figure 7b uses 7.6% + 1.3Sn% of the
microprocessor time for a 2MHz clock. A SO% reduction in
the previously described microprocessor times can be
achieved by using faster versions of the 6800 and 8080A
microprocessors.

Because the microprocessor system is interrupted every
2ms, proper software design is especially important for
the REFRESH CONTROLLER The use of the scratch pad
memory significantly reduces the time required to refresh
the display. The fastest program, shown in Figure 6, uses

402

LOC

OBJECT
CODE

BF 05
BF 04
06 00

SOURCE STATEMENTS

0000
0002
0003

CDVR
RDVR
DECDR
POINT
COLMN
COUNT

EQU
EQU
EQU
RMB
RMB
RMB

$BFOS
$BF04
$0600
2
I
2

0005 00 AD
0007
0009
OOOB
OOOC

ASCII
DISPNT
DCRPNT
COLCNT
DIGCNT

FDB
RMB
RMB
RMB
RMB

DATA
2
2
I
I

OOOD
OOAD

BUFFR
DATA

RMB
RMB

160
32

0400
0400 86 FF
RFRSH
0402 B7 BF 05
0405 DE 00
0407 A6 00
LOOPHH
0409 B7 BF 04
040C A6 01
040E B7 BF 04

(

(

04A2
04A4
04A7
04A9
04AC
04AE
04BO
04B2
04B4
04B6
04B8
04BB
04BC
04BF
04CO
04C3
04C5
04C7
04C8
04CA
04CC
04CE

A6
B7
96
B7
81
27
D6
CB
D7
24
7C
OD
79
3B
CE
DF
DE
09
DF
86
97
3B

IF
BF 04
02
BF 05
EF
10
00
20
00
03
00 00

04CF
04DO
04D3
04D5
04D7
04D9
04DB
04DD
04DF
04EI
04E3
04E5
04E8
04EA
04EC
04ED
04EF
04FI
04F2
04F4
Q4F6
04F8
04FA
04FC
04FD
04FF
OS02
0504
0506
0508
050B
OIOE
OSlO

SF
CE
DF
86
97
86

LOAD
00 OD
07
06
09
05
OB
20
LOOP I
OC
06
03
00 05
06
LOOP2
LOOP3
05

97
86
97
9B
24
7C
97
DE
09
A6
DF
IB
97
DE
A6
DE
A7
08
DF
7A
26
CB
24
7C
7A
26
39

LOOPA
00 02

ORG
LDA
STA
LOX
LDA
STA
LDA
STA

LDA
STA
LDA
STA
CMP
BEQ
LDA
ADD
STA
BCC
INC
SEC
ROL

A
A
A
A
A
A

.
A
A
A
A
A

B
B
B

LOC

03
FE
02

00
05
OA
09
00
07
00
07
00 OC
E6
80
03
00 09
00 OB LOOP4
CD

CLR
LOX
STX
LDA
STA
LDA
STA
LDA
STA
ADD
BCC
INC
STA
LDX
DEX
LDA
STX
ABA
STA
LDX
LDA
LDX
STA
INX
STX
DEC
BNE
ADD
BCC
INC
DEC
BNE
RTS

$0400
I, $FF
E, CDVR
D, POINT
X,O
E, RDVR
X, I
E, RDVR

X,31
E, RDVR
D,COLMN
E, CDVR
I, $EF
LOOPB
D, POINT +1
1,32
D, POINT +1
LOOPA
E, POINT

I, BUFFR
D, POINT
D, COUNT
D,COUNT
I, $FE
D,COLMN

B
A
A
A
A
A
A
A
A
A
A
A
A

B

RDVR
CDVR
DECDR

EQU
EQU
EQU

0004H
OOOSH
OE500H

POINT
COLMN
COUNT
BUFFR

ORG
DW
DB
DW
DS

OEOOOH
BUFFR
OFEH
OFFFFH
160

EOAS A7 EO
EOA7 00

ASCII
DATA

ORG
DW
DS

OEOA5H
DATA
32

E400
E401
E402
E403
E406
E408
E40A
F40C
E40D
E40F
E410
E411
E414
E417
E4I9
E41B
E41E
E421
E422
E425
E428
E42B
E42E
E430
E433
E436
E437
E43A
E43B
E43C
E43D

F5
C5
E5
2A
06
3E
D3
7E
D3
23
05
C2
3A
D3
FE
CA
22
07
32
C3
21
22
3E
32
2A
2B
22
EI
CI
FI
C9

RFRSH

ORG
PUSH
PUSH
PUSH
LHLD
MVI
MVI
OUT
MOV
OUT
INX
DCR
JNZ
LDA
OUT
CPI

OE400H
PSW
B
H
POINT
B,32
A,OFFH
CDVR
A,M
RDVR
H
B
LOOP
COLMN
CDVR
OEFH
FIRST
POINT

E43E
E441
E443
E446
E447
E448
E44B
E44D
E44E
E450
E451
E452
E453
E455
E456
E459
E45A
E45B
E4SD
E45E
E45F
E462
E463
E46S
E466
E467
E46A

II
OE
2A
7E
23
22
26
6F
06
7E
12
7D
C6
6F
D2
24
7B
C6
SF
05
C2
7B
C6
SF
OD
C2
C9

EOOO
E002
E003
E005

E,COLMN

LDX
STX
LOX
DEX
STX
LDA A
STA A
RTf

SOURCE STATEMENTS

0004
0005
E500

RTI
00 OD LOOPB
00
03

OBJECT
CODE

I, BUFFR
D, DISPNT
I, 

~

aB '3

5 C

""Is

INTEL
2102A-4

~CE:f

101
AET E'Q ,.

• B

As
As

,.110
~

74LS162

en

1:

~

16 A7

-=,~CO
-=-.~'5
9

I

5 A2

3 AET EP

C ~B

ADDRESS BUS

D'N DOUT""

3 R/W
ud~

9,~L

I

INTEL
2102A-4

,~ A7

T7

flO

~

A3

~

~

~'

74LSOO

J

S

a

'2 K

C

(I

74LS04

-KS
-KS
-KS

j

'30

•
12

°

<::

9
L-

7

~

14

7.LSll,

~7'LS04
~~

~"

12"-74lSOO

NOTE: ADDRESS BUS DECODING
A7

A6

0

0

, ,
-

Figure B. BOBOA Microprocessor Interface to the HDSP-2000 DECODED DATA CONTROLLER

As A4 AJ A2 AI At)

-

, ,
0

0

-

-

-

0
0
0
0

,

-

-

-

RIGHTMOST CHARACTER LOCATION

LEFTMOST CHARACTER LOCATION
COLUMN
COLUMN
COLUMN
COLUMN
COLUMN

1
2
3
4
5

J

., L1LJLJL1L
ADDRESS BUS

DATABUS _______

ME'Mi'iR

!:~--~~----~--------~--------L--------1--------4_--------~------~~
L..J
I~

74100CLOCK _________
DATA OUT 74165,
RAM DATA IN

RAM

-;::::::~::~~--~::~--~::::~--~::~~--!:::~--~::::~--~::~

WRi'TE
ADDRESS BUS DECODING:

A,
0
0
0
0
1

A,
0
0
1
1
0

AO
0 COL 1
1 COL 2
0 COL 3
1 COL 4
0 COL 5

A,
0
1

A,
0
1

As A, A,
0
1

0
1

RIGHTMOST CHARACTER
LEFTMOST CHARACTER

Figure 9. Data Entry Timing lor DECODED DATA CONTROLLER

LOC

OBJECT
CODE

SOURCE STATEMENTS

BOOO
E500

DlSPL
DECDR

EQU
EQU

OBOOOH
OE500H

ASCII
DATA

ORG
DW
DS

OEOOOH
DATA
32

ORG
LXI
MVI
LHLD
MOV
INX
SHLD
MVI
MOV
MVI
MOV
STAX
INX
MOV
ADI
MOV
JNC
INR
DCR
JNZ
MOV
SUI
MOV
DCR
JNZ
RET

OE400H
D, DISPL+00F8H
C,32
ASCII
A,M
H
ASCII
H, DECDR/256
L,A
B,5
A,M
D
D
A,L
80H
L,A
LOOP3
H
B
LOOP2
A,E
13
E,A
C
LOOPI

EOOO
E002

02
00

EO

E400
E403
E405
E408
E409
E40A
E40D
E40F
E410
E412
E413
E414
E415
E416
E418
E419
E41C
E41D
E41E
E421
E422
E424
E425
E426
E429

11
OE
2A
7E
23
22
26
6F
06
7E
12
13
7D
C6
6F
D2
24
05
C2
7B
D6
SF
OD
C2
C9

F8 BO LOAD
20
00 EO LOOPI
00 EO
E5
05
LOOP2

80
ID E4
LOOP3
12 E4
OD

05

These controllers have been designed to eliminate the
burden of data handling between keyboard, display, and
microprocessor, The product data sheet describes the
technical function of the controllers in detail,

E4

Interfacing the controller to microprocessor systems
depends on the needs of the particular application.
Figures 13a and 13b depict latched interfaces from a
master microprocessor to the HDSP-247X series of
controllers, These interfaces are utilized to avoid having
the master processor wait for the controller to accept data,
In sophisticated systems, it may be desirable to have the
HDSP-247X controller handle all of the keyboard/display
interface while the microprocessor reads edited messages
from the controller DATA OUT port. This function can be
achieved through the use of peripheral interface adapters
(PIA) available from the microprocessor manufacturers,
Figure 14 depicts a 6800 based system in which data may
enter the display from either a keyboard or a
microprocessor. This interface uses a 6821 PIA configured so that PB7 controls whether the microprocessor
or keyboard enters data into the controller. The 6800
program is shown in Figure 15. Subroutine "LOAD" uses
CA1 and CA2 to provide a data entry handshake that
allows the 6800 to load data into the controller as fast as
the controller can accept it. After the prompting message
has been loaded, the microprocessor turns the control of
data entry over to the keyboard. A signal from the
keyboard ("ER" in the example) setsa flag within the6821.
Depending on how the 6821 is configured, the
microprocessor can either test the flag or allow the flag to
automatically interrupt the microprocessor. Subroutine
"READ" would then be used to read the DATA OUT

Figure 10. 8080A Microprocessor Program that Decodes a
32 Character ASCII String Prior to Loading inlo the
DECODED DATA CONTROLLER

406

,-'

Z 80 INTERFACE:
808OA,. 6800 INTERFACE:

74LS3B7

DATA

74532

8Us1~~=====~

WR~
cs

D2 ______________~~

~============~~~

;p INDTE 11_~--------------J

@

CS(NOTE2)

ADDRESS BUS

{~

2""0

Do.

1

111

NOTE 1: (/) IS MICROPROCESSOR CLOCK

'

MCM
NOTE 2:

A2

~.

~

~

I

CS IS iORQ ANDED WITH THE I/O ADDRESS OF THE
DISPLAV

I

HDSP(32
2000
D'SPLAY
CHAR)

*

12 01

'"

C1 C2C3C4CS
112131415

I!.!I!.I!..l!.I

ACK
Y10

~
~

74197

IMHz

7404

Vr:c

CLOCK
INPUT
MR750

10K

74145

2

(TVP)

-C

CL

~tl:3r'-t--

~741".r8

Figure 11a. 80BOA Microprocessor Interface to the HDSP-2000 RAM CONTROLLER

~

*DlSPLAY IS OPERATED WITH
PIN 1 IN THE UPPER RIGHT
HAND CORNER

I

l

OOs
DOs

DATA
OUT

004

~
00,
000

(8)

(10)
(12)
1141
(16)
(181
(20)

(2)
(24)

DATA VALID
COLUMN ON

(AI

(26)

Va. DISPLAY
BLANK

vee~

0, 9";

26

20pF

=

(6)

'K

P
4

'"F

40

Vee

VDD
XTAL,

18
BUSs
17
BUSs
16
BUs..
BUS3 '5
'4
BU~
BUS, '3
'2
BUSg

XTAL2

RESET
EA

38
P27
37
P26
36
P25

'3

'4

~

00

(25)
(9)
(7)
(5)
(3)

35
24
23
22
21

01 6
01 5
01 4

(4)
(23)
(2')
(19)

1
33
32

Dl3

(17)

30

01 2
01,
01 0

(15)
(13)
(11)

29
28
27

1'4
RAM
ADDRESS

[

A3
A2
A,

I
I
I
•

Ao

017

DATA
IN

~

3'

6

(,)

CHIPSECEeT

READY

~

"24
P23
P22
P21
P20

~~~!.~~3.

.

P:

"4

"3

AsA7A sAfJ I
MeM
I
683080R I

HDSP-2470

74 "2
LS'45 _

-=

'68 b'98'20

HDSP-

36n

5

(TYP.)

(0

t

0-0-0--- vee
6

'--------;r

2

lK
Vee

G
4 F
3 E

HOSP
2471/2
HDSP·
2470
_
'0
WR 11
ALE
HOSP
2470

IRQ

4_ 6
-

'9

~
74LS37

11

9
eLK

eOLUMN4

COLUMN3

(D)

eOLUMN2

ri*-

COLUMN,

(B)

(K)

rtl

eOLUMN5

TIP 105
(TYP.)

'2 B
, S1L

12
BUS 7

P17

HcS:

lC

74
'4 0
'3 e LS165

HOSP-2471/2

(H)

(G)

3

'--

r;;--

r*-

~ liFI
~ r*

4

, ,
0

It::
247'12 "---

DC o
p~ o O~ 06 EQUIV csl
9 01 113 14 5
S

f~t
'2,

(M)

DH

DISPLAY DATA

rei
(LI

-

CLOCK

'3
74LS37

74LS37
HDSP-247'/2

~2470

S 7 6 5 4 3

6

Vee

,oon

GNO

To
P'6
P'5
P'4
P'3
P'2
P11
P'0

Vee----<>-~ T,

7"""""""=5

'5!

INTEL 8048

o"'"

VB. DISPLAY BLANK

Vss
on

(N)

..

[iO)

oc~

-=-

L
-=Figure 12. HDSP-2470/-2471/-2472 DISPLAY PROCESSOR CONTROLLER

~

i~
m
~I

twe
ADDRESS

I
r===:AW--

leH~_

-

lew

_t:=.-

tow

-----00

I

DATA

PARAMETER
WRITE CYCLE
WRITE DELAY
CHIP ENABLE TO WRITE

r

CHIP SELECT

-~~
I

_

twp

tWR _

VIR (6800 OR
8080A INTERFACEI

8 (2·80

f

INTERFACE ONLYI

f

SYMBOL

MIN.

twe
tAW
lew

390ns
65ns
65nl
220nl
20n5
310n5
10nl

DATA SETUP

~W

DATA HOLD
WRITE PULSE
WRITE RECOVERY
CHIP ENABLE HOLD

tOH
twP
tWR
leH

f

Figure 11b. Memory Write Timing for the HDSP-2000 RAM CONTROLLER

ADDRESS
BUS

r

~

A3
A2

I

A,

I
I

A.

ONLY REOUII1EO-FOR RAM-MODE
14
13

I
I
I

~

r
I

60 15

50

20

50 12
40
10
30
7
20 5

10

10

40

11

3D

6
4

Vee

6D

3
9

CL 74LS174

DATA
BUS

~4LS10

12

06

17 7D

80 '9
70 ,6

Os

14 60

60 15

D.
03

13 50

50 12

8 40

40 9

7 3D
20

30 6
20 5

10

10 2

Do

_I

i

(22)

READY

,.

cs
~
I ~,)
I
:

__''--C~N~GU!,A.!I~'!... _ _ J

CL
1
18 80

02

HDSP

2470/1/2

I
I

I

0.,

0,

_

LEFT. RIGHT OR BLOCKMOOEs

I~.
1
74LS10

Vee

1374LS10

__Cq!.II:lG~A.!I~ a_

I

~

__

~

I

I

A.
I (251
A3
I (91
I (71 A2
A,
(51
I
(31 Ao
12

r1

: r+l
I

i

4

3
11

01,

(41
(231 01 6
Dis
(211
(191 01.
(17) 01 3
01 2
(15)
(131 01,
01.

(111

74LS273

80BOA INTERFACE

CS~
74ls10
6800 INTERFACE

VMA~IDs
.2

*CS IS A LOGICAL COMBINATION OF HIGH ORDER ADORE SS BITS
THAT DISTINGUISH THE ADDRESS OF THE HOSP 2470/1/2 FROM THE
REST OF THE MICROPROCESSOR SYSTEM.

CS* 4
6
5 74LS10

Figure 13. Latched Interface to the HDSP-2470/-2471/-2472 DISPLAY PROCESSOR CONTROLLER

409

2On.

6

RESET

PB7
PB6
PB5
PB.

-

r----,.-

- I---v
- r---,;;

-

f-;g

- f--ao
- f---a;
- I---;;"
- '33
- r---;,
- ~
- ~

BUS
OATAj

AO

RIW

.2

- f--Js
- f--a5
- r---,,- I-;s
-~

---;;

07
06
05
D.
03

PB3
PB2
PB,
P·O
C.,

'7
'6

8

,.

'5

'0

'3

,.
'2

'2
11

'6

HDSP-

005
DO.

2416/24/32/40
ALPHANUMERIC
DISPLAY·

003
002

DO'
'8
000
20

'0

2

02
0,

C·2 J<""ro.':ll2M

00

PA7

CSo

PAs
PA5
PA4

CS,

008

'97~10

1K

74LS157

-=t;:"

,.

9
B
7

DISPLAY
PROCESSOR
CONTROLLER

CS2

3

RS,

3Y 9
2Y
7
'Y 4

3B

6

RSO

017
4
016
23
01 5
2'
0 14

4Y 12

••
,
,.
,
'3

HDSP-

2410n1/72

4A

3A
11
5 2A
2 ,A

6

A

DATA VALID

2B

,.

SEL
ST

'5

RIW

74LS151

"::"

E

PA3

RESET PA2

__
IROB

PA,
PAO

14 4A

5

11
2A
5
2 'A
48
'3

4
3
2

40

4Y 12

3Y

10 3B

2Y

28
,8

9
7

'Y

4

~

CA,

MOTOROLA
6821

~
C

~C

~
E

~E

~
G

~G

~
I

~

~
K

~K

L

L

M

M

~
0

~0

~
Q

L;Q

VB
COLUMN,
COLUMN2
COLUMN3

COlUMN4
COLUMNS
CLOCK
DISPLAY DATA

VCC
GNO

3A

r-- ~

CA2

A

0 13
012
01,

'3
0 10
11

SEL

~
~2
5

22

'OOOpF

~

39

_

8,
82

fi 6

A,
A2
CL

If J

2

3 S
14lS132

6

READY

OS

·16,24,32, OR 40CHARACTER HDSP-2000 DISPLAY
BOARD DESIGNED TO INTERFACE TO THE
HDSP-2470/71/72 DISPLAY PROCESSOR CONTROLLER

7 74LS122

l\'OOOpF

I

'5

ST

ff~

VCC

'7

-=i::-

ER 06 DS 04 03 02 01 DO ST
MICROSWITCH 61SW12-' KEYBOARD

Figure 14. 6800 Microprocessor Interface Utilizing a 6820 PIA lor an HDSP-2470/-2471/-2472 Alphanumeric Terminal

outputs from the controller into the microprocessor
system. The microprocessor uses the CB1 input of the
6821 PIA to determine when to read each of the 34 data
output words into the system.

will read the DATA IN lines during RESET and interpret
the contents as the control word. The circuit depicted in
Figure 18 can be utilized to load any desired preprogrammed word into the HDSP-247X controller, during
power on.

A similar PIA interface for the 8080A microprocessor is
depicted in Figures 16 and 17.

Under certain operating conditions, it may be desirable to
vary the brightness of displays controlled by the HDSP247X controllers. The circuit depicted in Figure 19 may be
utilized to provide manual brightness control of the
display through pulse width modulation. Automatic
control may be achieved by substituting an appropriate
value photoconductor for potentiometer R1.

The HDSP-247X series of controllers are programmed to
default to "Left Entry" mode for a 32 character string of
displays. If some other entry mode or string length is
desired, it is necessary to either load the appropriate
control word from the microprocessor or to provide a
control word during POWER ON RESET. The controller

410

• PORT CONFIGURATION:
PORTA,
I.
PAO-PA7 OUTPUTS TO DATA IN OF HDSP-247X
CAl (INPUT) MODE 00 SET FLAG NEG EDGE OF READY
CA2 (OUTPUT) MODE 100 CLEARED MPU READ PRA, SET
NEG EDGE OF READY
PORTB,
• I.
PBO-PB6INPUTS DATA TO 6800 FROM DATA OUT OF HDSP-247X
CBI (INPUT) MODE 00 SETS FLAG NEG EDGE OF DATA VALID
CB2 (INPUT) MODE 000 SETS FLAG NEG EDGE OF ER KEY
CB2 (INPUT) MODE 001 SETS FLAG NEG EDGE OF ER KEY
CAUSING IRQ

• PORT CONFIGURATION,
PORT A (MODE I OUTPUT),
• I.
PAG-PA7 OUTPUTS TO DATA IN OF HDSP-247X
PC7 (OBF) OUTPUT; TO CHIP SELECT
PC6 (ACK) INPUT; TO READY
FLAG PC7 (OBF) CLEARED BY OUTPUT; SET BY READY

•

PB7 (OUTPUT) LOW ENABLES PAG-PA7 TO MUX
HIGH ENABLES KEYBOARD TO MUX

PORT B (MODE I INPUT),
PBO-PB6INPUTS DATA FROM DATA OUT OF HDSP-247X
PC2 (STB) INPUT; LOADS DATA ON NEG EDGE OF DATA VALID
FLAG PCO (lNTR) CLEARED BY INPUT; SET BY DATA VALID

• 3.

PORTC,
PC4 OUTPUT; LOW ENABLES PAO-PA7 TO HDSP-247X
HIGH ENABLES KEYBOARD TO HDSP-247X
OBJECT

OBJECT

CODE

SOURCE STATEMENT

LOC

CODE

SOURCE STATEMENTS

8008
800S
8009
800A
800A
800B

PRA
DRA
CRA
PRB
DRB
CRB

EQU
EQU
EQU
EQU
EQU
EQU

58008
$800S
$8009
5800A
5800A
S800B

OOOC
OOOD
OOOE
OOOF

PA
PB
PC
CNTRL

EQU
EQU
EQU
EQU

OCH
ODH
OEH
OFH

0000

ORG
MESSAGE RMB

50000
2

EooO 02 EO
E002 00

ASCII
TEXT

ORG
DW
DS

OEOOOH
TEXT
32

0100
0101
0102

STATUS
CURSOR
DATA

ORG
RMB
RMB
RMB

$0100
I
I
32

EIOO 00
EIOI 00
E102 00

STAT
ADDR
DATA

ORG
DB
DB
DS

OEIOOH
0
0
32

E400
E401
E402
E403
E404
E406
E409
E40B
E40D
E40F
E410
E411
E414
E416
E417
E419
E4IC
E410
E41E
E420
E421
E424
E426
E427
E42A
E42B
E42C
E42D
E42E
E42F

F3
FS
ES
CS
OE
21
DB
06
DB
04
IF
D2
3E
BS
DB
D2
77
23
DB
IF
D2
DB
OD
C2
77
CI
EI
FI
FB
C9

READ

E430
E433
F434
E436
E439
E43B
E43C
E43E
E43F
E442
E44S
E446
E449

2A
7E
FE
CA
D3
23
DB
17
D2
C3
23
22
C9

E44A
E44C
E44E
E450
E452
E454

3E
D3
3E
D3
3E
D3

LOC

r

• 2.

0400
0403
0406
0407
0408
040B
040D
040F
0411
0413
0416
0418
041A
O4ID
114IF
0420
0421
0423
0426
0428
042A

CE
B6
SF
SC
B6
2A
CI
23
C6
B6
84
A7
B6
2A
08
SA
26
B6
84
A7
39

042B
042D
042F
0430
0432
0434
0437
043A
043D
043F
0441
0443

DE
A6
08
81
27
B7
7D
B6
2A
20
DF
39

0500
0503
0506
0508
OSOB
OSOD
OSlO
0512
0515
0517

7F
7F
86
B7
86
B7
86
B7
86
B7

0100
800A

LOOP2
800B
FA
OA
F2
21
800A
7F
00
800B
FB

7D
S6
B7
86
B7
OF

LOOP3
LOOP4

FO
800A
7F
00
00
00
FF
00
8008
8008
8009
FB
EC
00

8009
800B
FF
8008
24
8009
SO
800A
04
800B

OSIA OE
'OSIB 7F 800A
051E BD 042B
0521
0524
0526
0529
042B
052E

READ
LOOP I

800A
SO
SOOA
OC
800B

LOAD
LOOPIO

LOOPII
ENDL

START

ORG
LDX
LDA
CLR
INC
LDA
BPL
CMP
BLS
LDA
LDA
AND
STA
LDA
BPL
INX
DEC
BNE
LDA
AND
STA
RTS
LDX
LDA
INX
CMP
BEQ
STA
TST
LDA
BPL
BRA
STX
RTS

A
B
B
A
B
B
A
A
A
A

$0400
I, STATUS
E,PRB
E,CRB
LOOP2
1,10
LOOPI
1,33
E,PRB
I, $7F
X,O
E,CRB
LOOP4

CLEAR CBI AND CB2

WAIT FOR DATA VALID

READ AND CLEAR CB I
STORE IN RAM
WAIT FOR DATA VALID

B
A
A
A

LOOP3
E,PRB
I, $7F
X,O

A

D, MESSGE
X,O

A
A
A

ORG
CLR
CLR
LDAA
STA A
LDA A
STA A
LDAA
STA A
LDA A
STA A

I, $FF
ENDL
E,PRA
E, PRA
E,CRA
LOOP I I
LOOPIO
D, MESSGE

READ DATA

LAST WORD IN STRING
JUMP WHEN DONE
CLEAR CAl AND CA2
WAIT

$0500
E,CRA
E,CRB
I, $FF
E,DRA
1,524
E,CRA
1,580
E, DRB
I, $04
E,CRB

• PROCEDURE TO LOAD HDSP-247X SYSTEM
CLI
DISABLE KEYBD FROM MUX
CLR
E,PRB
E, LOAD
JSR
• PROCEDURE TO READ DATA OUT OF HDSP-247X SYSTEM
E, PRB
CLEAR CBI, CB2
TST
LDA A I, $SO
STA A E, PRB
ENABLE KEYBD TO MUX
LDAA I, SOC
ENABLE IRQ,
STA A E,CRB
IRQ CAUSE JSR TO READ
SEI

Figure 15. 8800 Mlcroproce..or Progrem
Clrcultahown In Figure 14.

20
00 EI
OD
00
OE

LOOP I
LOOP2

OD E4
OA
OD
OB E4
LOOP3
OE

LOOP4

IE E4
OD
IC E4

00 EO

LOAD
LOOPS

FF
45 E4
OC
LOOP6

OE
3C E4
33 E4

ENDL
00 EO
A7
OF
OC
OF
05
OF

E4S6 3E 08
E458 03 OF
E45A CD 30 E4

START

.
•

E45D 3E 09
E45F 03 OF
E461 FB

that Interface. to the

ORG
DI
PUSH
PUSH
PUSH
MVI
LXI
IN
MVI
IN
INR
RAR
JNC
MVI
CMP
IN
JNC
MOV
INX
IN
RAR
JNC
IN
DCR
JNZ
MOV
POP
POP
POP
EI
RET

OE400H
PSW
H
B
C,32
H. STAT
PB
B,O
PC
B

FIRST WORD
CLEARINTR

LOOP2
A,1O
B
PB
LOOP I
M,A
H
PC

WAIT UNTIL INTR IS SET

LOOP4
PB
C
LooP3
M,A
B
H
PSW

WAIT UNTIL INTR IS SET

LHLD
MOV
CPI
JZ
OUT
INX
IN
RAL
INC
lMP
INX
SHLD
RET

ASCII
A,M
OFFH
ENDL
PA
H
PC

MVI
OUT
MVI
OUT
MVI
OUT

A,OA7H
CNTRL
A,OCH
CNTRL
A,05H
CNTRL

LOOP6
LOOPS
H
ASCII

WAIT UNTIL STATUS WORD
STORE IN RAM

STORE LAST WORD

FIRST WORD OF MESSAGE
CHECK TO SEE IF DONE
OUTPUT TO DISPLAY

WAIT
NEXT WORD

PA OUTPUT, PB INPUT
CLEAR INTE A
SET INTE B

PROCEDURE TO LOAD HDSP-247X SYSTEM
MVI
A,08H
ENABLE A SIDE OF MUX
OUT
CNTRL
CALL
LOAD
PROCEDURE TO READ DATA OUT OF HDSP,247X SYSTEM
MVI
A,09H
ENABLE B SIDE OF MUX
OUT
CNTRL
INT MUST CALL READ
EI

Figure 18. 8080A Mlcroproce..or Program that Interface. to
the Circuit .hown In Figure 17.

411
._----

4
PII,
PII,;

~

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PB.

- I-ai
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14
16
18
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PC 2

PAs 38
PAs 39

2

~4lS132 10

INTEL
8255A
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1
PA, 2
PA,
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4

14

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11
5

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2

6
3

pc.

PC.
PC7

DO.
DO,

Oa.

HDSP2416124132140
ALPHANUMERIC

DO,
000

DISPLAY·

DATA VALID

DISPLAY

PROCESSOR
4 017
23 01.
01,
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01.
19

13

11
(ACK)

1

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4A
3A
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4A
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24
23

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21
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18

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- I-Ta O.
- 7e O.
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DATA
BUS

8

8
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-b 1

B1
B2
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4

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~

61

5 74LSOO

.16,24,32, OR 40 CHARACTER HDSP·2000 DISPLAY

A2
CL

0>&

BOARD DESIGNED TO INTERFACE TO THE HOSP·
2470/71/72 DISPLAY PROCESSOR CONTROLLER.

17

~

ER 0 6 0 5 04 0 3 02 0, Do ST
MICROSWITCH 61SW12·' KEYBOARD

Figure 17. 8080A Microprocessor Interface Utltlzlng an 8255 PIA for an HDSP-2470/·2471/-2472 Alphanumeric Terminal

412

[~•
~~

DESIRED {
MODE, XX·

2

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01,

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13

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*SEE HDSP·2470/1/2 DATA SHEET

Figure 18. External Circuitry to Load a Control Word lI,to the
HDSP-2470/-2471/-2472 Alphanumeric System upon Reset

Figure 19. External Circuitry to Vary Luminous Intensity of the
HDSP-2470/-2471/-2472 Alphanumeric Display System

DECODER DECODER
ADDRESS ADDRESS HDSP·2411
FOR FIG.
FOR
ROM
la.lb,1D
FIG.6
ADDRESS

HEXIDECIMAL DATA

E5DO

0600

080
090
DAD
080
OCO
000
OED
OFO

08
10
00
3E
3E
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30
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45
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62
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14
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38
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38
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0680

100
110
120
130
140
150
160
110

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51
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48
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42
09
41
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29
61
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30
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63
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55

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0100

160
190
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180
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100
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49
50
09
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29
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80
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49
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54

08
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36

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38
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04
15
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18
36

44
49
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04
08

55
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08
51
41
40
44
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COLUMN3

E680

0160

200
210
220
230
240
250
260
210

1F
06
00
45
55
09
00
24

40
24
00
40
09
21
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1C

29
61
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49
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21
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41
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05
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38
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64
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20
49
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51
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280
290
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00
04
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06
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30
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40
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46
36
46
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18
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32
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20

19
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44
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39
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10
40
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60
38
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02
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04
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41
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COLUMNS

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60
38
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3F
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08
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41
41
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Figure 20. 128 Character ASCII Decoder Table Used by the 6800 Refresh Program in Figure 6, 8080A Refresh Programs In Figures
7a, 7b, and 10, and the HDSP-2471 DISPLAY PROCESSOR CONTROLLER. Decoded 5x7 Display Font Is shown In the HDSP-247X
Data Sheet

413

.APPLICATION NOTE·1002

HEWLETT' PACKARD
COMPONENTS

Consideration ofCTR Variations in
Optically Couple~ Isolator
. Circuit Designs
INTRODUCTION - Optocouplers Aging Problem

charge, k is Boltzmann's constant, T is temperature in
degrees Kelvin, and V F is the forward voltage across
the light emitting diode.

A persisten t, and sometimes crucial, concern of designers
using optocouplers is that of the current transfer ratio,
CTR, changing with time. The eTR is defined as the ratio
of the output current, 10 , of the optocoupler divided by the
input current, IF' to the light emitting diode expressed as a
percentage value at a specified input current. The resulting
optocoupler's gain change, ~CTR+, with time is referred to
as eTR degradation. This change, or degradation, must be
accounted for if long, functional lifetime of a system is to
be guaranteed.

The diffusion current component is the important radiative
current and the non-radiative current is the space-charge
recombination current. Over time, at fixed V F' the total
current increases through an increase in the value of B.
From another point of view, with fixed total current, if the
space-charge recombination current increases, due to an
increase in the value of B, then the diffusion current, the
radiative component, will decrease. The specific reasons for
this increase in the space-charge recombination current
component with time are not fully understood.

A number of different sources for this degradation will be
explained in the next section, but numerous studies have
demonstrated that the predominant factor for degradation
is reduction of the total photon flux being emitted from
the LED, which, in turn, reduces the device's CTR. This
degradation occurs to some extent in all optocouplers.

+~CTR

= CTRfinal -

CTRinitial

The reduction in light output through an increase in the
proportion of recombination current at a specific IF is due
to both the junction current density, J, and junction
temperature, TJ . In any particular optocoupler, the emitter
current density will be a function of not only the required
current necessary to produce the desired output, but also of
the junction geometry and of the resistivity of both the P
and N regions of the diode. For this reason, it is important
not to operate a coupler at a current in excess of the manufacturer's maximum ratings. The junction temperature is
a function of the coupler packaging, power dissipation
and ambient temperature. As with current density, high TJ
will promote a more rapid increase in the proportion of
recombination current.

(1)

Causes
The main cause for CTR degradation is the reduction in
efficiency of the light emitting diode within the optocoupler. Its quantum efficiency, 1"/, defined as the total
photons per electron of input current, decreases with
time at a constant current. The LED current is comprised
primarily of two components, a diffusion current component, and a space-charge recombination current:

The junction and IC detector temperature of HewlettPackard optocouplers can be calculated from the following
expressions:

(2)

A e

qV F/kT

+ B e

qV F/2kT

~~

Diffusion

Space-Charge Recombination
(3)

where A and B are independent of V F , q is electron
414

efficiency of the emitter defined as the photons emitted per
electron of input current and depends upon the level of

where the T J is the junction temperature of the LED
emitter, T D is the junction temperature of the detector
IC, T A is ambient temperature, and the thermal resistances
are the emitter junction to ambient, BJA = 370°C/W =BDA
detector to ambient, and the detector to emitter thermal
resistance is BD_E = 170°C/W = BE_D' V F , IF are the
forward LED voltage and current; V 0' 10 are the output
stage voltage, and current and V cc' Icc are the power
supply voltage and current to the device. In general, it is
desirable to maintain T J';;; 125°C.

input current, IF' and upon time. Finally, {3 is the gain of
the output amplifier and is dependent upon I p , the
photocurrent, and time. Temperature variations would, of
course, cause changes in 17, {3 as well.
From Equation (4), a normalized change in CTR, at
constant IF' can be expressed as:
(5)

A useful model can be constructed to describe the basic
optocoupler's parameters which are capable of influencing
the current transfer ratio. The 6N13S optocoupler, Figure I
is the simplest device and one which is easily accessible for
needed parameter measurements. However, any optocoupler can be modeled in this fashion within its linear
region. Figure I shows the system block diagram which
yields the relationship of input current, IF' to output
current, 10 , The resulting expression for CTR is:
10
eTR = - (100%)
IF

The first term, tJ.17/17, represents the major contribution to
tJ.CTR due to the relative emitter efficiency change;
generally, over time, tJ.17 is negative. This change is strongly
related to the input current level, IF' as discussed earlier
and more elaboration will be given later. The second term,
(tJ.T)/T)IF (Clln{3/Cllnl p )t' represents a second order effect
of a shift, positive or negative, in the operating point of the
output amplifier as the emitter efficiency changes. The
third term, (tJ.{3/{3)Jp, is a generally negligible effect which
represents a positive or negative change in the output
transistor gain over time. The parameters K and Rare
considered constants in this model.

(4)

where K represents the total transmission factor of the
optical path, generally considered a constant as is R, the
responsivity of the photodetector, defined in terms of
electrons of photocurrent per photon. 17 is the quantum

I£...

r

....'0
ELECTRICAL CIRCUIT

INPUT
CURREN

IF

~

Figure 1.

TOTAL LED
EFFICIENCY
n OF,t)

TRANSMISSION

OPTICAL
~ OF
INTERFACE

Ie

K

RESPONSIVITY
OF PHOTO·
DETECTOR
R

System Model for an Optocoupler

415

Ip

GAIN OF
OUTPUT
AMPLIFIER
POp)

10

OUTPUT

~URRENT

Figure 2 displays the mean and mean plus 2a values
of emitter degradation versus R for lK, 4K, and 10K hours
at 25°C. Accelerated degradation can be seen at larger R
values.

Degradation Mode'

In this section, an extensive test program conducted at
Hewlett·Packard to characterize the CTR degradation
of optocouplers is discussed. The development which will
follow is mainly of interest to those concerned with
reliability and quality assurance. From the basic data, the
CTR degradation equations will be developed in order to
predict the percentage change in CTR with time. Complete
data and analysis of CTR degradation will be found in an
internal Hewlett·Packard report.

The data of Figure 2 can be replotted to illustrate the
percentage degradation versus time as a function of R.
Figure 3 illustrates the mean and mean plus 2a distribution
with R = 1 and 50.
From this curve, a useful expression which relates the
average degradation in emitter efficiency to time is
obtained for the mean or mean plus 2a distributions. [The
symbol "D" will refer to CTR degradation due solely to
emitter degradation, Art/r/, whereas ACTR/CTR will refer
to total CTR degradation as expressed in Equation
(5)].

This study is based on a total of 640 optocouplers of the
6N135 type (Figure 1) with 700nm GaAs. 7P. 3 LEDs
from twenty different epitaxial growth lots representing a
range of n·type doping and radiance. The 6N135 allows
access to measurement of the emitter degradation via the
relative percentage change in photodiode current, AIp/Ip,
as well as output amplifier (3 change. Stress currents of
I FS = .6, 7.5, 25 and 40 rnA were applied to different
groups of optocouplers, and at each measurement time of
t = 0, 24, 168, 1000, 2000, 4000 and 10,000 hours,
measurement currents of IFM = .5,1.6,7.5,25 and 40 rnA
were used to determine the CTR.

(6)

.Al p
OJ( or Ox + 2a

== - , - = AoRQtn(R) for I FS = 'FS in %
p

where t is in 103 hours and Ao and Q differ for mean or
mean plus 2a. Equation (6) represents an average
degradation corresponding to a specific R, t, and an average
stress current I FS ' A knowledge of I FS and the actual
device operating stress IFS can be utilized to correct D to
reflect the absolute magnitude of IFS' This will be shown in
the development of· Equations (11) and (13). The data
shows that IFS increases with R and can be represented as
follows:

The important results to be noted are the following. First, a
factor of major significance in the study of CTR
degradation is the ACTR varies as a function of the ratio of
I FS/I FM == R. Large values of R will result in greater CTR
degradation than at lower R values with the same
magnitude of I FS ' However, knowledge of the ratio of
IFS/IFM alone
does not give a complete picture of
degradation because ACTR is also dependent upon the
absolute magnitude of the stress current, IIFSI. The
following data will allow the derivation of the necessary
equations with which to predict ACTR as a function of
I FS ' IFM and time.

(8)

10.5 + 5.76'0910R

50

R

Figure 2. Emitter Degradation vs. R (Ratio of Stress Current to Measurement Current! for 1k, 4k, and 10k Hours,
Mean, Mean +20 Distribution, TA = 25°C.

416

TIME (hours)

Figure 3. Degradation VI. Time at R = 1 and R = 50 for Mean, Mean + 20 Distributions, TA = 25°C.

or substituting Equation (6),

These equations are obtained from averaged degradation
data versus I FS at different measurement times.

[),.,. = A Ratn(R) + S [I

x

The expression for n(R) was found to obey the relationship
nCR)

=

.0475 10910R + .25

aD

= aIR) log10t + /l(R)

%/mA

I

Equation (12) gives the mean distribution degradation
by using a degradation value, D (first term), corresponding
to th~ ratio of IFS./I FM , or a stress current, TFS ' ~nd then
applYing a correction quantity (second term) to due to
the magnitude of the actual stress current, IFS ' yielding the
actual degradation O.

°

The expression for the mean + 20 distribution degradation,
Ox + 20' (worst case) is almost of the same form as
Equation (12). The dissimilarity arises from the fact
that the standard deviation, 0, is dependent upon the stress
current, I FS ' the ratio R, and upon time. This complex
dependency was analytically deduced from the data to be
the fol1owing expression:

(10)

where t is in 103 hours, the coefficients a(R) and /l(R) can
be found on Figure 7.

(13)

or substituting Equation (6)

Along with Equation (10), the mean distribution
degradation, Ox' can be estimated for any specific stress
current, I FS ' ratio R, and time t via the subsequent
expression:
%

(12)

%

°

Equation (6) gives.!... direct relationship between the
average degradation, 0, and time. As mentioned earlier
the magnitude of the stress current also determines th~
amount of degradation. In order to allow for the effect
of IIFSI, empirical observations were made on 0 at
different I FS and at different times for several values of R.
The dependence of degradation on stress current is linear
up to IFS = 40 rnA, for all values of R. From these
observations, the average rate of change, or slope, S(R,t), of
degradation 0 with IFS over time was found to behave in
the following fashion for any R:
S == - al FS

"I

FS - FS

w~ere, againj Ox is the average degradation at time t, in
!!mts of 10 hours, corresponding to a stress current,
I FS ' given by Equations (7) and (8); I FS is the actual stress
current and R=IFsfIFM; S is the expression (10) for the
change of slope of versus IFS with time; n(R) is a power
of t, given by Equation (9), and Ao,a are found in Figure 7.

(9)

Ao and a were determined from degradation data versus R
and are found in Figure 7, "Matrix of Coefficients."

c

0

Dj( + 20 = AoRatn(R) + [S + 2Pl II FS - TFSI

x

(14)

where Ox + 20 is the degradation for + 20 distribution
corresponding to the stress current I FS ' Equations (7)

(,,)

417

and (8). Ao and a are found in Figure 7 under the Y+ 20
category. S [Equation (10)] represents the slope to cprrect
for actual I FS versus I FS current levels, and P [Equation
(15)] is the new term which is a slope to correct for the 0
variation with I FS ' Rand t. The coefficients -y(R), 8(R) in
P are found in Figure 7.
P = -y(Rllog 10t + /HRI

%/mA

The actual lifetime for an optocoupler is greater than
Figures 4a and 4b would indicate since the majority of
units will be centered around the mean distribution lifetime.
Secondly, the optocoupler which is operated at some
signal duty factor less than 100%, for example 50%, would
increase the optocoupler's life by a factor of two. Third,
the fact that an optocoupler is used within equipment
which may have a typical 2000 hours per year (8 hours/day
- 5 days/week - 50 weeks/year) instrument or system
operating time, could expect to increase the optocoupler's
life by another factor of 4.4 in terms of years of useful life.

(151

where t is in 103 hours.
The degradation Equations (11) and (13) are considered
accurate for the ranges of IFS .;;; 40 rnA and R .;;; 20;
outside this range, the model does not predict degradation
as well. Hence, check to see if I FS and R satisfy the
above conditions. If IFS or R exceed these limits,
predition of D will be, in general, greater than the
actual degradation due to large values for Sand P which do
not reflect actual Sand P. IffFS is approximately equal to
the actual I FS ' then the second term in the degradation
equations need not be determined. Otherwise, the second
term needs to be determined to obtain true emitter
degradation, D. If I FS < IFS,..!hen the degradati0l!.> D, will
be less than the ~egrad~tion, D, corresponding to I FS ' and
vice versa w~n I FS > I FS ' A qUick and~oarse estimate for
degradation D can be obtained by using D =AoRatn(R) for
a specific R with approximate values for a "'" 0.4 and
n"'O.3. Figure 4 represents plots of Equations (I I) and
(13) for R = I and IFS = 1.6, 6.3, and 16mA at both
TA = 25°C and TA = 85°C. These plots are very useful in
making a quick approximation of D for the specific conditions for which the plots have been made. These conditions represent the recommended operating conditions for
the three HP optocoupler families.

'.0

:;::0
E
~

0.8

(j

0.7

ffi

0.6

~
~

~

~

,J.A

0.5

r--TA·~5°C.R·.,

~a:

0.4

--t-l<
r-- --t"l<+2.

I

. ·"t-- t.6tttA.........

1SmA

I

I

I

i I

0.3
103

..61 LU

H::::~~
rb-_
--L. -r-rUm~
...... ...

I
I
I

w

>
;::

II

--- -.-- -- -'_.

f.:-::,':::=.

0.'

.04

10'

TIME (hours)

a

'.0

- ±. .:=::::::----- ~er-.. -.. _g'Sm}1
... .
....
J~..J.

J

This discussion of reliability data and its interpretation with
model equations is qualified to specific optocouplers,
6NI35 and 6N138, where continuous LED operation was
maintained, and extrapolation of data for times beyond
10,000 hours is assumed to be valid. Different types of
LEDs or preparation processes may produce different
results than those presented in this section. These
expressions only incorporate the first order effect, emitter
degradation AT}/T}, whereas comments about higher order
effects upon total CTR degradation will be given in the
following section. With these expressions for degradation,
accelerated testing may be accomplished by employing
large values of R. Such testing can provide a means by
which to determine acceptable emitter lots for optocoupler
fabrication, acceptable degradation performed for lot selection, or p'redict functional lifetime expectance for
optocouplers under specific operational conditions.

sf
"
>
u

0.'

$

0.1

E

~
U

ffi

II-

0.8

==::t--l....- :: ...

~.,,_ 1-- "j-"-

I

I

~

w

>

;::

~a:

0.'

'-

~.

......

I

0 .•

••3mA

,

I

0.3

1.6mA

-. .. . J11r-··t
6.,3mA.....

....

TA -85"C. R "" 1
0.'

"-

=:±"

t-----:._~ X'" 20

!

[
,04

103

10'

TIME (hours)

b

Figure 4. Calculated Curves of Relative Emitter Efficiency
vs. Time for P = 1: 'FS = I FM = 1.6,6.3, and
16mA which are Recommended IF for 6N138,
6N137, and 6N135 Optocouplers Respectively.
Mean, Mean + 20 Distributions. al T A =25°C,
b) TA =85°C.

An important point to note is that the total operational life
of an optocoupler is greater than the worst case mean plus
20 distribution implies. Specifically, the worst case
degradation given in Figures 4a (2S oC) and 4b (85°C)
are for the continuous operation of the 6N 135 optocoupler.

418

gain is j3 = 26,000; hence, 31n{3/3lnIp "" -0.25. If, for
instance, the emitter degradation 1),.71/71 is -10%, then
the second order term would improve the overall CTR
degradation, i.e.,

The appropriate operating time considerations will vary
depending upon the designer's knowledge of the system
in which the optocoupler will be used. The operating lifetime of an optocoupler can be expressed, for a maximum
allowable degradation at a particular IFS, by using Figures
4a and 4b for tcontinuous lifetime and the following
expression:

1

J

(171
= -10% + 2.5% = -7.5%

(161

This improvement is what was expected while operating on
the right side of the j3 maximum. In fact, with an IF =4 rnA
or Ip "" 4/lA, the term 3lnj3/3lnIp = -0.8, and again, if
1),.71/71 = -10%, the resulting 1),.CTR/CTR = -2%, nearly
cancelling the emitter's degradation.

tcontinuous = [tsystem fData Duty] fSystem Use
lifetime
lifetim~ L Factor
LData Factor

Another equally important point to observe is that of the
worst case conditions under which the optocoupler is used.
As will be illustrated in the design examples, the worst
possible' combination of variations in Vcel' Vec2 ' Rin ,
CTR, R L , Ill' and temperature still result in the optocou~ler functioning over an extended length of time
(10 hours) for a particular maximum allowable degradation. However, the likelihood of seven parameters all
deviating in their worst directions at the same time is
extremely remote. A thorough statistical error accumulation analysis would illustrate that this worst-worst ease is
not a representative situation from which to design.

30.000

l:l

ill

20,000 ;

~
~

a:

10,000 ~

Higher Order Effects

'0

"

Ip - PHOTOCURRENT -IIA

a

The first order effect of emitter degradation, 1),.71/71, has a
pronounced influence upon the 1),.CTR as explained in
the previous sections; however, consideration of higher
order effects is important as well.

I

2

ANODE~

Consider the second term in Equation (5) (1),.71/71)IF
(3In{3/3InIp)t, the emitter degradation part has been
explained; however, (3In{3/3InIp)t represents a shift in
the operating point of the output amplifier of an optocoupler. The term (3ln{3/3lnIp) can be rewritten as
(l/2.3j3)(3j3/3log IOIp) which is more convenient to use
Nith the accompanying typical curves of j3 versus 10g1OIp
for the two optocouplers 6Nl35 and 6N138, given in
Figure Sa.

CATHODE

~ 8
.----:----=---0
Vee

¥

~

~_ _ _ _ _..J

6

~-..:==---OVo

3

TYPE6N135
TYPICAL 'F = 16 mA
TYPICAL CTR = 20%

t

6
'------oGND
I.

7

V.

b

lice

If the operating photocurrent, Ip, is to the right of the
maximum j3 point of either curve, then with reduced
emitter efficiency over time, Ip will decrease, but the
increasing j3 will tend to compensate for this degradation.
However, if the operating Ip is to the left of the maximum
j3 and then Ip decreases, the j3 change will accentuate the
emitter's degradation, yielding a larger CTR loss. The
magnitude of the contributions of 3Inj3/3lnI p to overall
CTR degrll.dation can be illustrated by the following
examples.

r--~

'!:.....

ANO
+ DE]2

\If

~

10

6

r-=--<> 110
CATHODE -

3
TYPE6N138
TYPICAL 'F = 16 mA
TYPICAL CTR = 600%

I.

t
5
'-----oGND

c

Consider a 6N138 optocoupler of Figure 5c operating
at its recommended IF = 1.6 rnA which corresponds to
an Ip "" 1.6/lA. (An IF to Ip relationship for HewlettPackard optocouplers is I rnA input current yields approximately I/lA of photodiode current.) At Ip = 1.6/lA,
the slope of the VCE = 5V curve is equal to -15,000 and the

Figure 5. al DC Current Gain, j3, vs. Photocurrent, Ip, for
6N135 and 6N138 Optocouplers. Current Diagrams and Typical Values of IF a"nd CTR for
Hewlett-Packard Optocouplers, bl6N135,
cl6N138.

419

With the 6N135 optocoupler, Figure 5b operating at
IF = 10 rnA, or Ip "'" lO~A, which corresponds to the
maximum {3 point on the VCE = .4V curve, the slope is zero
and the total CTR degradation is basically the emitter's
degradation.

For the optocouplers containing an output amplifier, such
as the 6NI37, which switches abruptly about a particular
threshold input current, the actual emitter degradation can
be determined from Equations (11) and (13). An appro·
priate IFinitial can be determined to provide for ade·
quate guard band current which will allow the optacoupler emitter to degrade while maintaining sufficient
Ip to switch the amplifier. An actual design procedure to
determine the needed IFinitial for proper operation of
Hewlett-Packard optocouplers is given in the design
examples section.

Another subtle effect is seen from the third term in
Equation (5), (A{3/{3)Ip, over time. At constant Ip, (3
can increase or decrease by a few percent over 10,000
hours. This change is so small that the third term is generally
neglected.

MATRIX OF COEFFICIENTS
8SoC

25°C

X

X+2u

Ao

4.95

a

.388

..

X+2a

X

R<6

6"R

R<8

8"R

9.7

6.8

5.0

15.0

11.0

.428

.302

.467

.284

.430

E
I

...
iiiIX:
IX:

:0
U

85°C

25°C

IX:

~

R,,1

R,,1

R;>1

.19 R .32

.32 R .08

.32 R .30

.055 R· 68

.11 R .25

R;>1

oJ

8

aiR)

.19 R .052

9

PIR)

.055

I

8SoC

~IR)

.063 R .30

.154 R .26

SIR)

.091 R .38

.196 R .39

Ip - PHOTOCURRENT -IJ,A

a
Figure 7. Matrix of Coefficients.

Typical IF = 6.3 mA
Typical eTR = 700%

b

Figure S. a) Output Current, 10, vs. Photocurrent, Ip, for
SN1370ptocoupler.
b) Circuit Diagram and Typical Values of I F and
CTR for SN137 Optocoupler.

420

.11 R .65

25°C

Procedure for Calculation of CTR Degradation

Degradation Model Equations (11) and (13) Valid

3.

First Approximation of Degradation
(%1
or
i+2a

4.

Calculate

with a"'" .4, Ao (Figure 7)
n "'" .3, t in 103 hours
(D corresponds to I FSI

~ 14.13 + 9.0610g10 R @ 25°C

Equation (7)

{10.5 + 5.76 10910R @ 85°C

Equation (8)

If I FS "'" I FS' Step 6 and the second terms in
Equations (11) and (13) do not need to be calculated.
5.

Calculate

n(R) = .0475 10910R + .25

6.

Calculate

S = aIR) 10910t + (i(R)

"'.I.PC.ll

Figure 7

P = 'Y(R) log10t + ,sIR)

'Y(R), ,sIR)

t in 103 hours

7.

Calculate

Mean, Mean + 2a Degradation

Ox =

AoR~n(R) + S [I FS - IFSI

Dj( + 2a = AoRatn(R) + [8+ 2Pl [lFS -IFSI

%

Equation (11)

%

Equation (13)

(Ao ' a via Figure 7, t in 103 hours)
8

For Second Order Effect, Determine Slope
illnfi = _

[

illnlp
9a.

il(i

2.3fi illog 10 l p

Total CTR Degradation for Mean Distribution
ACTR
CTR

9b.

Figure 5a - typical curves with an approximation
for HP optocouplers of IF =1 mA yields Ip "'" 1/lA

illn(i
= Dj(+Dj(

illnlp

Total CTR Degradation for Mean + 2a Distribution
ACTR
CTR

illn(i
Dj( + 2a + Dj( + 2a --.illnlp

421

Practical Application

A very common application of an optocoupler is to
function as the interfacing element between digital logic.
In this section, the designer will be shown an approach
which will insure the initial and long term performance
of such an interface, and take into account the practical
aspects of the system that surrounds it. These system
elements include the data rate, the logic families being
interfaced, the variations of the power supply, the
tolerances of the components used, the operational
temperature range, and lastly the expected lifetime of the
system.

IF 10 ~ IR -IlL' THEN OUTPUT

TRANSISTOR WILL BE IN
SATURATION

Figure 8. Typical Digital Interface Using an Optocoupler.

The system data speed can be considered as the primary
selection criteria for selecting a specific optocoupler family.
Figure 9 lists the ranges of data rates for four HewlettPackard optocoupler families when driven at specified
LED input current, IF. With this table, and the knowledge of the system data rate requirements, it is possible to select an optimum coupler.

V cc1 (MIN) - V F (MAX) - Val
Rin (MAX)

Vcc1 (MAX) - V F (MIN) - Val
Rin (MIN)

7
~~

."'.E',

6N135/6
SINGLE
CA'IIl.E"
TRANSISTOR
•

•

v,
v,

5 GNO

~~~v"

6N138/9
''''DE~~'i
~v,
SPLIT
CATIfODE~
~vo
DARLINGTON
i!,---~D'"

~..

= CTR(MIN)
V cc1 - V F - Val
(21)

\\

1.6mA

7.5mA

10mA

12mA

16mA
333k

TYP

2M

MIN

12k

22k

125k

TYP

100k

200k

840k

MIN

1.8k

5 Vo

•• N.

6N137
llr-v;;-~
OPTICALL Y ANODE 1Z~"1>ifD v,
COUPLED CATlIODE~ "
IIDv,UT
GATE
I!~IID

Figure 13.5-2.

1.0mA

MIN

TYP

Figure 9.

'F

(20)

x 100

INPUT CURRENT - IF
.5mA

-..

'0

NRZ DATA
RATE BITS/S

FAMILY

(19)

'F (MAX)

An example of an optocoupler interconnecting two logic
gates is shown in Figure 8. A logic low level is insured
when the saturated output sinking current, 10 , is greater
than the combined sourcing currents of the pull-up resistor,
and the logic low input current, IlL' of the interconnecting
gate. Using the coupler specifications selected from Figure
9 and the corresponding eTR (MIN) from Figure 10,

4N45/6
CATHODE 2
DARLINGTON,

(18)

'F (MIN)

6,5k

640

MIN

6.7M

TYP

10M

Optocoupler Data Rates Specifications.

422

%CTR@I F = (mA)

TEMP

FAMILY
.5

SINGLE
TRANSISTOR

VOL

25

0.4

300

0-70

0.4

500

0-70

0.4

1.6

10

5

16

6N135

7

6N136

19

6N138
SPLIT
DARLINGTON

°c
1.0

6N139

400

4N45

250

200

0-70

1.0

500

200

0-70

1.0

0-70

0.6

DARLINGTON
4N46
OPTICALLY
COUPLED
GATE

350

400

6N137

Figure 10.

Optocoupler CTR (MIN).

choosing a value of RL which is consistent with

it is possible to determine from Equation (20) the
minimum initial value of IF for the coupler. The design
criteria is that 10 ;;' IlL + IR for the VIL specified in Figure
11.

r

10 (MIN) - milL at the end of system life. Equation

(22) describes this worst case calculation.
(22)

Using Equation (21), the typical value of Rin can be
calculated for the selected IF and the logic low output
voltage, VOL' of the driving gate. The VOL of the logic
family is given in Figure 11. The next step is to determine the worst case value of the LED input current,
IF' resulting from the tolerance variations of the LED
current limiting resistor, Rin , and the power supply voltage,
V cel' The conditions of IF (MIN) and the initial
CTR (MIN) are then used to determine {he initial worst case
value of 10(MIN)' Conversely, the worst case CTR
degradation will occur when the LED is stressed at
IF (MAX) conditions; thus, IF (MAX) will be used to
determine the worst case degradation of the optocoupler
performance. Using the maximum Vcel and the minimum
Rin will accomplish this worst case calculation, as shown in
Equation (19).

TTL FAMILY

IlL

V IL

IIH

74S
74H
74
74LS
74L

-2mA

.SV
.SV
.SV
.SV
.7V

50~A

Figure 11.

-2mA
-1.6mA

-.36 rnA
-.18 rnA

50~A
40~A

20~A
10~A

V IH

IOL

VOL

IOH

V OH

2V
2V
2V
2V
2V

20mA
20mA

.5V
.4V
.4V
.5V
.4V

-1000~A

- 500~A
- 400~A
- 400~A
- 200~A

2.7V
2.4V
2.4V
2.7V
2.4V

l6mA
SmA
3,6mA

V cc2 (MAX) - VOL
RL (MIN)

;;.~

IF(MIN) • CTR(MIN) .1-

~;:a

D

)

]

------:;1"0"0---4--- - mil L

Dx + 2a = worst case CTR degradation
The selection of the maximum value of RL is also of
important in that its value insures that the collector is
pulled up to the logic one voltage conditions, Vm, under
the conditions of maximum IOH of the coupler, and the
1m of the interconnecting gate.
(23)

V cc2 (MIN)- V IH
RL (MAX) ..; - - - - - - IOH (MAX) + m 'IH

The selection of the value of RL between the boundaries of
RL (MIN)' and RL (MAX) has certain trade offs. As in any
open collector logic system, TPLH increases with increasing
RL · Conversely, as RL is increased above RLMIN' a larger
guardband between IOMIN and IlL + IR is achieved.
Engineering judgement should be employed here to achieve
the optimum trade off for desired performance.

Logic I nterface Parameters.

The change in CTR from the initial value at time t =0 to a
final value at some later time can be compensated by

423

Using the coefficient Figure 7 and Equations (11) and
(13), the following examples are developed to demon·
strate the methods of optocoupler system design in the
presence of the mean and mean plus two sigma CTR
degradation.

4.75 - 1.7 -.4
IF (MIN) = - - - - 1890n

Step 3.

1.4mA

I F (MAX)

Example 1.
Vcc1 (MAX) - V F (MIN) - VOL
IF (MAX) =---~-----­
Rin(MIN)

System Specifications
20 k bit NRZ
Standard TTL
5V ± 5
±5%
o-70°C
350 k hr (40 yr) at 50%
system use time and
50% Data Duty Factor

Data Rate
Logic Family
Power Supply I & 2
Component Tolerances
Temperature Range
Expected System Lifetime

IF (MAX)

Step 4.

=

5.25 - 1.4 - .4

(26)

2.02 rnA

1710n

Determine continuous operation time for LED
emitter.

Interface Specifications
Coupler 6N139
CTR (MIN)
VOL (MAX)
IOH (MAX)
VF (MAX)
VF (MIN)
VF(TYP)

tcontinuous
lifetime

= 500% @ IF = 1.6 rnA
= .4V @ IF = 1.6 rnA
= 250~A @Vcc2 = 7V
1.7V@I F = 1.6 rnA

tcontinuous
lifetime

= 40~A
= 2V
= 400~A
= 2.4V

87.60K hr

Step 5.

Obtain the mean and mean + 20 CTR
degradation at IF (MAX) and
tcontinuous lifetime either as an
approximation from Figure 4 or by
calculations as shown below.

Step 5a.

Determine Dj(

Logic Standard TTL
IIH
VIH
IOH
VOH

1

f Data DUty] fsystem use]
lifetimeJ L Factor
LDUty Factor

(40 yr x 8.76 k hr/yr)(50%)(50%)

1.4V @ IF = 1.6 rnA
1.6V@I F = 1.6rnA

IlL = 1.6 rnA
VIL
.BV
16mA
IOL
VOL = .4V

= [tsystem

(27)

Dx = Aot· 25 + S [IFS - I FS ]
Step 1.

Rin (TYP)
Dj(

Vcc1 - V F (TYP) - VOL
Rin = - - - - - - - - IF (TYP)
5.0 -1.6 -.4
R· = - - - - : - In
1.6 x 10.3

[IF (MAX) -14.13 rnA]
Dj(

I F (MAX)

IF (MIN)

= ----=------

\

(' r',

1.87kn, select 1.8kn ± 5%
R(MIN) = 1710n
R(MAX) = 1890n

Step 2.

= 4.95t(k hr) .25 + [.186 log t(k hr) + .055]

(24)

= 4.95 (87.6)·25 + (.186 log 87.6 + .055)
(2.02 rnA -14.13 rnA)

Dj( = 10.10% for 40 yr system operation
Step 5b. Determine Dx + 20

Vcc1 (MIN) - V F (MAX) - VOL
Rin(MAX)

(25)

Dx+2u

= Aot· 25 + [S+2P]

Dx + 20

= 9.7t(k hr!'25 + [2 (.063 log t(k hr) + .081)

424

II FS +IFS ]

(28)

The range of RL is from 1.32kn to 8.lkn. It is desirable to
select a pull-up resistor which optimizes both speed
performance and additional 10 guardband. This criteria
leads to a tradeoff between a value close to RL (MIN) for
speed performance and one bordering near RL(MAX) for
10 guardbanding. In this design example, the system's
lifetime has a higher priority than does the moderate speed
performance demanded from the optocoupler. An RL of
3.3kn ± 5% is selected under this condition.

+ (.186 log t(k hr) + .055))
x [IF (MAX) -14.13 mAl
OJ( + 2a = 9.7 (87.6)·25 + [2 (.063 log 87.6 + .081)

+ (.186 log 87.6 + .055)]
x [2.02 mA -14.13 mAl
OJ( +

2a

Step 6.

= 19.71%

An additional guardband of 5% was added to the worst case
Dx: + 2a eTR degradation guardband to insure that even a
greater percentage of the distribution would be accounted
for. The actual percentage difference between IOL (MAX)
and 10 (MIN) at the end of system life is shown below:

Guardband the worst case value of CTR
degradation.

It is often desirable to add some additional operating
margin over and above conditions dictated by simple worst
case analysis. The use of engineering judgement to increase
the worst possible eTR degradation by an additional 5%
margin would insure that the entire distribution would fall
within the analysis. Thus,
OJ( +

2a + 5%

Step 7.

(30)

I
1
CTR(MIN) • F (MIN)' 10 (MIN)

(OJ(
+ 2a\
-;00-;

= -----1-00--....:..----L

= 24.71%
(31)

Selecting RL (MIN) for guardbanded worst case
V cc2 (MAX) - VOL

• m= 1

10L (MAX) =

+ mUlL'
RL (TYP -5%)

(22)
% Guardband = [ 1 -

Vcc2 (MAX) - VOL

10L (MAX)]

(32)

X 100

10 (MIN)

For the example shown, the additional end of system life
10 guardband results from the selection of an RL greater
than the RL (MIN) as shown in Steps 9, 10, and II.

r

Step 9.
RUMIN);;;'

10 (MIN) at end of system life

5.25 -( .4
)
1.4x10-3 .500%·1- ~
_ _ _ _ _-nn~---'_.......t...
OO.... -1 1.6 mA

500% ·1.4 mA • (1 _

100

10 (MIN) ..

-

1~.~~,*')
= 5.65 mA

100
RL (MIN) • 1.32kn
Step 10. 10L (MAX) for worst case of IR (MAX) + IlL
Step 8.

Select RL (MAX)

(33)

V cc2 (MAX) - VOL
RL (MAX) .;;; - - - - - - : - 10H (MAX) +mlIH

(29)

10L (MAX)

=

5.25 -.4
3.13kn

+ 1.6 mA

= 3.14 mA

Step 11. % Guardband
4.75 -2.4
RL (MAX) .;;; 250llA + 40llA

..

3.14mA

8.1k

% -

426

1

5.65mA

100 = 44.4%

(34)

Thus, this, circuit interface design offers an additional
44.4% 10 guardband beyond the 19.71% required to
compensate for the CTR change caused by B6.7k hr of
continuous operation at an IF (¥AX) of 2mA. This extra
guardband results from having chosen an RL =3.3k rather
than the lowest allowable value of RL plus the engineering
guard band chosen in Step 6.

Step 4.

System lifetime
t

= 43.8k hr

OJ( and Ox + 2u for I F (MAX) of 19 mA

Step 5.

by calculation or from Figura 4

Ox = 14.5%

t

43.8k hr

Ox + 2u .. 28.5%

~

continuous lifetime

Example 2.
System Specifications
Step 6.

Data Rate
Logic Family
Power Supply I and 2
Component Tolerance
Temperature Range
Expected System Lifetime

250K bitNRZ
TTL to LSTTL
5V±5%
±5%
25°C
175 khr(20yr) at
50% System Use Time
and 50% Data Duty
Factor

Engineeriog Guardband of 5%,
0x+2u+5% = 33.5%

Step 7.

Rl selection with guardbanding of Ox + 2u + 5%
RL (MIN) .. 3.44kO

= 50kO

Step 8.

Rl (MAX)

Step 9.

Rl (TVP) .. 5.1kO ± 5%, RL (TVP - 5%)

Interface Conditions
= 4.84kO, R l (MAX + 5%)

Coupler 6N136
" CT~IN) =
} VOL
=
l}OH
=..
YF(TYP) =
VF(MIN) =
VF(MAX) =

= 5.35kO

19% @ IF = 16 mA
.4V .
500nA @ Vcc2 = 5.0V
1.6V @ IF = 16 mA
1.5V @ IF '" 16 mA
1.7V @ IF = 16mA

Step 10. End of System Life 10 (MIN)
10 (MIN) = 1.5 mA
Step 11. 10l (MAX) = 1.36 mA
Step 12. Engineering % Guardband of 10 (MIN) = 9.3%

Logic LSTTL
IlL = .36mA
V IL = .BV
IIH = 401LA
VIH = 2V

Example 3.

10L = BmA
VOL = .5V
10H = 4001LA
VOH = 2.7V

If a particular design requirements specifies a maximUF
tolerable degradatioll over a system lifetime, the optimun.,
value of IF(TYP) can be obtained from Figure 12.
For example, if a maximum acceptable degradation,
Ox + 2u' is 40%, and a continuous operation of 400k hr is
desired, this curve specifies that IF (TYP) should be less
than or equal to 10 mAo A 400k hr continuous operation
with 100% system duty factor as might be encountered in
telephone switching equipment is equivalent to 45 years of
system lifetime.

Again using Figure 7, the data rate dictates the use of
a 6NI36 at an IF (D1» of 16 mAo Using the same 12 step
worst case analysis, it is possible to determine the values of
R in , RL and the degree of guardbanding of 10 at end of
system lifetime.
Stap 1.

Rin

= 1870, select 1800 ±

5%

Rl (MIN) .. 1790
Rl (MAX) .. 1890
Step 2.

IF (MIN) - 14.02·mA

Step 3.

IF (MAX) - 19 mA

If a 6N 139 split Darlington were used to interface an
LSTTL logic gate with the system specifications stated, a
collector pull·up resistor of as low as 1600 could be used.
If an RL of Ik were selected, this optocoupler would
offer an additional end of life guardband of B1.B%. This
worst case analysis points out that with the knowledge of
selecting proper values of RV the CTR performance of the

426

<
.s
f-

zW

II:
II:

:::>

10

u
en
en
w

II:

f-

en

TIME (hours)

Figure 12.

Stress Current (lfS) vs. Time vs. % Degradation.

coupler far exceeds the normal MTBF requirements for
most commercial electronic systems.
Consideration of the Optically Coupled Gate

r

System data speed requirements in the multi·megabit range
can also be communicated through an optocoupler. The
first three coupler families listed in Figure 9 are not
applicable in these very high speed data interface applications; however, the optically coupled gate, 6N137, will
function to speeds of up to 10 MHz. This type of coupler
differs in operation from the single transistor and
Darlington style units in that it exhibits a non-linear
transfer relationship of IF to Ia. This is shown in Figure
13. The relationship is described as a minimum threshold of LED input current, IFth which is required to
cause the output transistor to sink the current supplied by
the pull-up resistor and interconnected gate. As the LED
degrades, the effect is that a larger value of IF th is required
to create the same detector photo diode current necessary
to switch the output gate.

~----~-----,----o+5V

.01

.F

In the previous interface examples, the worst case analysis
and guardbanding is based on the output collector current,
Ia. With the optically coupled gate, worst case guardbanding is concerned with the selection of the initial value
of the IF' which at end of system lifetime will generate the
necessary threshold photocurrent demanded by the gate's
amplifier to change state.

Figure 13. 6N137 Input - Output Characteristics.

427

The calculation of the required IF to allow for worst case
LED degradation is approached by guardbanding the
guaranteed minimum isolator input current, I FH , for a
specif1ed IOL and VOL interface. Equation (35) shows
the relationship of the Ip to IF for this coupler.
Ip Q (IF)n

• where 1.1 .;; n .;; 1.3

Step 2.

Calculate the worst case LED degradation

97 t
.25
Ox + 20 ~
~
. (k hr)

ox+20

(35)

~
9.7 (50.3)·25
~

Ox +20"" 26%
Step 3.

Using the concept that the guardbanding of the initial value
of IF will result in a similarly guardbanded Ip, the
relationship presented in Equation (36) results:

Calculate the first approximation of guard banded
IF' n=1.2
5mA

[

1 _ °H20l = [lpH l

J

100

=

[lpJ

[IFH l n

(36)

.78

6.41 mA

IF J

(37)
Step 4.

OX+.20]n
[1---

Calculate input resistor R in

100

V cc1 (MIN) - V F (MAX) - VOL

The previous interface example showed that the first term
of the Dx + 20 equation dominated the magnitude of the
worst case degradation. This term, AoRQtn(R), i.e.,
(9.7 t(k hr)"25), does not contain an IF current dependent
term; thus, an approximation of the worst case LED
degradation can be made that relates to the system's
lifetime. This initial value of Dx + 20 can be used in
Equation (37) to calculate the initial value of the IF.
With this initial IF, a more accurate degradation value
can be calculated using Equation (28). This procedure
results in an iterative process to zero in on a value of IF
that will insure reliable operation.

Rin .;; ------------------------IF

4.75 - 1.7 -.4
Rin .;; - - - - - .00641
R in .;; 413n select' Rin

390n ± 5%

Rin (MAX)
R in (MAX) = 409n
Rin (MIN) = 370n

The following example will illustrate this approach.
Example 4.

Step 5.

System Specifications
6MHzNRZ
LSTTL to TTL
5V± 5%
±5%
o -70°C
203k hr (23 yr) at 50%
System Use Time and
50% Data Duty Factor

Data Rate
Logic Family
Power Supply 1 and 2
Component Tolerance
Temperature Range
Expected System Lifetime

Step 1.

Vccl (MAX) - V F (MIN) - VOL
IF (MAX)

=

[ts!st~m
hfetlme

Rin (MIN)

5.25 - 1.4 - .4
370

Determine the continuous operation time for
LED emitter

tcontinuous
lifetime

Calculate the I F (MAX)

] [Data Duty] System use]
Factor
Factor

L

9.32 mA

Step 6.

Calculate the worst case OJ( + 20 for I F (MAX)

OJ( + 20 = 25.8"'{' + .747 (9.32 mA - 14.13 mAl

[23 yr 8.76k hr/yr] [50% ] [50%]

OJ( + 20

50.3k hr
428

22.2%

Step 7.

Calculate the new minimum required 'F at end
of life based on degradation found in Step 6.
'FH

I

F(EOl)

[ - 22.2
100

Step 8.

T

11.2

5
.81

Step 11.

Minimum % Emitter Degradation Guardband

J

'F (EOl)
%(MIN) = [ 1 - - - 'F (MIN)

6.16mA

6.16mA
4.8% = [ 1 - - - 6.47 mA

Calculate 'F (MIN)

100

100

(38)

]

Vcc1 (MIN) - V F (MAX) - VOL
'F (MIN)

where IF (EOl) represents the switching threshold at the
end of life.

Rin (MAX)
4.75 - 1.7 - .4

'F (MIN) =

'F (MIN)

=

Step 12. Maximum % Emitter Degradation Guardband

409
6.47 mA

%(MAX)

=

[1-

'F (EOl)]

100

(39)

'F (MAX)
Step 9.

Rl (MIN)

• m = 1

J

6.16mA
34% = [ 1 - - - 100
9.32 mA
Vcc2 (MAX) - VOL
Rl(MIN)

'Ol (MIN)- mi,l
5.25 -.6

The conclusions that are to be drawn from this analysis are
that as long as the IF (MAX) is less than I FS = 14. I 3 rnA,
the worst·worst case CTR aegradation may be calculated
using only the first term, AoRO!tn(R), of the Dx + 20 case.
In the example presented, 26% degradation was determined
from the first term, and when the more accurate calculation
using Equation (28) was used, a 22% degradation resulted. The end of life IF guardband may be calculated
using Equations (38) and (39). Using Equation (38),
the minimum guardband is 5.7%, and with Equation (39),
the maximum guardband is 35%.

.016 - .0016
332n

Rl(MIN)
Step 10.

Rl (MAX)

• m = 1

Vcc2 (MAX) - VOH
Rl (MAX)

(

'OH (MAX) + ml'H
4.75 -2.4

Rl (MAX)

250llA + 40llA

Rl (MAX) = 8.1kn

429

Fli;'

HEWLETT

~r.. PACKARD

APPLICATION NOTE 1003

Interfacing 18 Segment Displays
to Microprocessors
INTRODUCTION

1b. The DECODED DATA CONTROLLER refreshes a
multiplexed LED display independently from the
microprocessor system. A local RAM stores decoded
display data. This data is continuously read from the
RAM and then used to refresh the display. Whenever
the display message is changed, the microprocessor
decodes each character in software and writes the
decoded data into the local RAM.

Over the past four years, the need for alphanumeric
displays has grown very rapidly due to the extensive use of
microprocessors in new system designs. The HDSP-6508
and HDSP-6300 alphanumeric displays were developed to
provide a low cost, easy-to-use alternative to 5x7 dot
matrix displays. These displays use an 18 segment display
font that includes a centered decimal point and colon for
increased readability. This font is capable of displaying
the 64 character ASCII subset (numbers, punctuation
symbols, and upper case alphabet) as well as many
special purpose symbols" The HDSP-6504 and HDSP6508 are 3.81 mm (0.150") red 4 or 8 character displays in a
dual-in-line package. The HDSP-6300 is a 3.56 mm
(0.140") red 8 character display in a dual-in-line package.
The HDSP-6508 has character-to-character spacing on
6.35 mm (0.250") centers while the HDSP-6300 has
character-to-character spacing on 5.08 mm (0.200")
centers. Paralleling the development of these alphanumeric displays have been the introduction of several
new display interface circuits that simplify the use of the
18 segment display. These circuits include an ASCII to 18
segment decoderldriver and improved NPN Darlington
digit drivers that are designed to interface directly to 5 volt
digital logic. This Application Note deals with several
techniques to interface the 18 segment display to
microprocessor systems. Depending upon the overall
system configuration, microprocessor time available to
dedicate to display support, and the type of information to
be displayed, the system designer would choose the best
interface technique to drive an 18 segment display.

1c. The CODED DATA CONTROLLER also refreshes a
multiplexed LED display independently from the
microprocessor system. The local RAM stores ASCII
data which is continuously read from the RAM,
decoded, and used to refresh the display. The display
message is changed by writing new ASCII characters
within the local RAM.
1d. The DISPLAY PROCESSOR CONTROLLER uses a
separate microprocessor to drive the LED display.
This microprocessor provides ASCII storage, ASCII
decode, and display refresh independently from the
main microprocessor system. Software within the
dedicated microprocessor provides many powerful'
features not available in the other controllers. The
main microprocessor updates the LED display by
sending new ASCII characters to the slave microprocessor.

COMPARISON OF INTERFACE TECHNIQUES
The choice of a particular interface is an important consideration because it affects the design of the entire microprocessor system. Each interface requires one or more
memory or 1/0 addresses. These addresses are generated
by decoding the microprocessor address bus. The display
decoder can be located within the microprocessor
program or as circuitry within the display interface.
Location of the display decoder within the microprocessor program gives the designer total control of the
display font within the program. This feature can be
particularly important if the display will be used to display
different languages and special graphics symbols. The
interface technique chosen may limit or interfere with
some programming techniques used in the rest of the
microprocessor program. For example, the use of an

DISPLAY INTERFACE TECHNIQUES
This application note will deal with four different
techniques, as shown in Figure 1a-d, for interfacing the
HDSP-6508 and HDSP-6300 displays to microprocessor
systems.
1a. The REFRESH CONTROLLER interfaces the microprocessor system to a multiplexed LED display. The
controller periodically interrupts the microprocessor
and after each interrupt, the microprocessor supplies
new display data for the next refresh cycle of the
display.
430

_ _ _ ~E~~~D..EI~L~Y!.._

SEGMENTED DISPLAYS

REFRESH CONTROLLER

I--___-----....--.;.,---+-I-I""-DECODEDDATACONTROLLER----l
I

I

I

I

I
I
I
I
I
I
I
I
I
I
I
I

I

I

I

I
I

INTERRUPT REQUEST

I

SYSTEM CLOCK

I

I

I

I

·PROGRAM + ASCII LOOKUP TABLE
"SCRATCHPAD WITH OR
WITHOUT DECODED
ASCII LOOKUP TABLE

IL ______________ ..J:

SEGMENTED DISPLAYS
-COOEDDAr';-CONT-;OUER -

~

Figure lb. DECODED DATA CONTROLLER Display Interface

Figure la. REFRESH CONTROLLER Display Interface

1- - - - -

IL _______________ I

·PROGRAM + ASCII
LOOKUP TABLE
··SCRATCHPAD

-

--I
I

r - - - DISPL;Y

SEGMENTED DISPLAYS

I

PROC'EUoR'CONTROlLER -

-1

~~~~~~I~

I

1--_..1-_ _..1-_--..1

:
I
I
I

SLAVE
MICRO·
PROC·
ESSOR

I
I

I
I
I

I
I

SYSTEM CLOCK

[

• PROGRAM
.. SCRATCHPAD

I

I
IL _________________ _

·PROGRAM
··SCRATCHPAD

I _______________ _
L

Figure lc. CODED DATA CONTROLLER Display Interface

Figure ld. DISPLAY PROCESSOR CONTROLLER Display
Interlace

interrupt may restrict the use of some programming
techniques used in the interruptable portions of the
microprocessor program.

The DECODED DATA CONTROLLER and CODED DATA
CONTROLLER require microprocessor interaction only
when the display message is changed. Both techniques
employ a local RAM memory that is continuously scanned
by the display interface electronics. For the DECODED
DATA CONTROLLER, the display decoder is located
within the microprocessor software and the local RAM
stores decoded display data. The CODED DATA
CONTROLLER includes the display decoder within the
display interface circuitry and the local RAM stores ASCII
data. Since ASCII data is more compact than decoded
display data, the CODED DATA CONTROLLER uses a
smaller RAM than the DECODED DATA CONTROLLER.
Both techniques allow the microprocessor to individually

The REFRESH CONTROLLER requires continuous interaction from the microprocessor system. Since the microprocessor actively strobes the LED display, the display
interface circuitry is reduced. Generally, this technique
provides the lowest hardware cost for any given display
length. The display decoder can be located either within
the microprocessor program or as circuitry within the
interface. Display strobing is accomplished through use
of the microprocessor interrupt circuitry. Demands upon
microprocessor time are directly proportional to display
length.

431

change each display character by a memory or I/O write to
a specific display address. These interface techniques can
accept new data at a very high rate.

through an address bus. data bus. and control bus. The
address bus consists of several outputs (Ao. A1 •... An) from
the microprocessor which collectively specify a binary
number. This number or "address" uniquely specifies
each word in the ROM memory. RAM memory. and I/O
interface. The data bus serves as an input to the
microprocessor during a memory or input read and as an
output from the microprocessor during a memory or
output write. The control bus provides the required timing
and signals to the microprocessor system to distinguish a
memory read from a memory write. and in some systems
an I/O read from an I/O write. These control lines and the
timing between the address bus. data bus. and control bus
vary for different microprocessors.

The DISPLAY PROCESSOR CONTROLLER. like the
previously defined CODED and DECODED DATA
CONTROLLERS. requires microprocessor interaction
only when the display message is changed. By using a
dedicated microprocessor. the DISPLAY PROCESSOR
CONTROLLER provides many additional display features. These features include multiple entry modes. a
blinking cursor. editing commands. and a data output
function. The software with the DISPLAY PROCESSOR
CONTROLLER further reduces microprocessor interaction by providing more sophisticated data entry modes
compared to the RAM entry mode provided by the
DECODED DATA and CODED DATA CONTROLLERS.
The display decoder can either be designed into the
dedicated display microprocessor or can be located
within a separate PROM. The use of a PROM allows the
user to provide a special character font with additional
circuitry. The DISPLAY PROCESSOR CONTROLLER
does not allow as high a data entry rate as either the
DECODED DATA or CODED DATA CONTROLLERS.

The address. data. and control buses provide the flow of
instructions and data into the microprocesor. Program
execution consists of a series of memory reads
(instruction fetches) which are sometimes followed by a
memory read or write (instruction execution). The
microprocessor performs a memory read by outputting
the memory address of the word to be read on the address
bus. This address uniquely specifies a word within the
memory system. The microprocessor also outputs a
signal on the control bus. which instructs the memory
system to perform a memory read. The address selects
one memory element. either RAM or ROM. within the
memory system. Then. the desired word within the
selected memory element is gated on the data bus by the
read signal. Meanwhile. the unselected memory elements
tristate their output lines so that only the selected memory
element is active on the data bus. After sufficient delay. the
microprocessor reads the word that appears on the data
bus. Similarly. for a memory write. the microprocessor
outputs the memory address of the word to be written on
the address bus. After sufficient delay. the microprocessor outputs a signal on the control bus. which
instructs the memory system to perform a memory write.

MICROPROCESSOR OPERATION
In order to effectively utilize the interface techniques outlined in the following sections. an understanding of microprocessor fundamentals is required. A brief description of
microprocessor fundamentals is included in the following
section. A microprocessor system usually consists of a
microprocessor. ROM memory. RAM memory. and a
specific I/O interface as outline in Figure 2. The microprocessor performs the desired system function by
executing a program stored within the ROM. The RAM
memory provides temporary storage for the microprocessor system. The I/O interface consists of circuitry
that is used as an input to the system or as an output from
the system. The microprocessor interfaces to this system

ADDRESS BUS, CONTROL BUS

INPUT

MICRO·
PROCESSOR

RAM

DATA BUS

Figure 2. Block Diagram of a Typical Microprocessor System

432

ROM

OUTPUT

PORT

OUTPUT

The microprocessor also outputs the desired memory
word on the data bus. The address selects one RAM
memory element within the memory system. The write
signal causes the memory element to read the word on the
data bus and store it atthedesired location. Afterthewrite
cycle has been completed, the new word will have
replaced the previous word within the RAM memory.
During the memory write, outputs from the unselected
memory elements remain tristated so that only the
microprocessor is active on the data bus. These control
lines and the timing for the address bus, data bus, and
control bus vary for different microprocessors.

MEMORY WRITE BUS TIMING lOBE -<1>2'
i"'1'~~~~~-'CYC ~~~----.(·I

~

~:'~-----'u~T~::::::::::~'Ir---1:

:!
IA 15 ..;. AO'

VMA

I :!
!
! i
_~;:::=~:
"I"
, =:;;-:===::;t-:
t,
", ----t:;o:-;:~
~ tEH -----+01

ADDRESS BUS :

Some microprocessors, such as the Motorola 6800 microprocessor family, handle memory and I/O in exactly the
same way. Memory and I/O occupy a common address
space and are accessed by the same instructions. With
this type of microprocessor, the hardware decoding of the
address bus determines whether the read or write is to a
memory or I/O element. Other microprocessors, such as
the Intel 8080A, Intel 8085A, and the Zilog Z-80 have
separate address spaces for memory and I/O. These
microprocessors use different instructions for a memory
access or an I/O access and provide signals on the control
bus to distinguish between memory and I/O. One
advantage of this approach is that the I/O address space
can be made smaller to simplify device decoding.
However, the I/O instructions that are available are usually
not as powerful as the memory reference instructions. Of
course, the user can always locate specific I/O devices
within the memory address space through proper
decoding of the address and control buses. This would
allow these I/O devices to be accessed with memory
reference instructions.

(

i - - I-

VALID ADDRESS

I

~tAD

:

I+tAH~

~1--~i----------~!r---4!----;~
I
I
I

R/W

,I
I
I
I
I

r-I

~--~:-----------;Ir---4:-----'
DATA BUS

107 - Dol

I

I

I

I
I

:

I

I

I

MEMORV WRITE BUS TIMING lOBE. <1>21

I

I

I

~'DDW-+--'2--l

I

'H

I

tEH

I
I:
l+,-

i

! .,

:L-

DBE

I

I

DATA BUS
(07 - Dol

I

I

VALID DATA

I
!.-'DDW-+!
I

MINIMUM TIMES (nS)

6800 MICROPROCESSOR

The 6800 microprocessor family has a 161ine address bus,
81ine data bus, and a control bus that includes the signals
VMA (Valid Memory Address), R/W (Read/Write), DBE
(Data Bus Enable), and clock signals 1 and 2. R/W
specifies either a memory read or write while VMA is used
in conjunction with R/W to specify a valid memory
address. DBE gates the internal data bus of the 6800 to the
external data bus. I n many applications, DBE is connected
to 2. Additional data hold time, tH, can be achieved by
delaying 2 to the microprocessor or by extending DBE
beyond the falling edge of 2. The timing between the
address bus, data bus, VMA, and R/W for a memory write
is shown in Figure 3.

DDW
(MAX

"

'AH

'2

30

22.

42.

30

ao

290

3.

ao

22.

63.

teye '" 666

200

68800, tcVC· 500

'6.

6800.

t CYC·

68AOO.

1OOO

'H

,.
,.
,.

t, (MIN) • tUTIMINI - tAolMAXI
t21MINI .. tEHIMINI- tODwlMAXl
From MOTOROLA SEMICONDUCTOR MC6800 Data Sheet
(059471),1978

Figure 3. Memory Write Timing for the Motorola 6800
Microprocessor Family.

for both a memory write and an I/O write is shown in
Figure 4. The 8080A also provides an input, READY, which
allows the memory system to extend the time the address
and data bus is valid by integral clock cycles.

For the 8080A microprocessor, the address bus consists
of 16 lines, the data bus consists of 8lines, and the control
bus consists of several lines including DBIN (Data Bus In),
WR (Write), SYNC (Synchronizin~gnal), READY, and
clock signals 1 and 2. DBIN and WR are used to specify
a read or write operation. The 8080A microprocessor
distinguishes memory from I/O through the use of a status
word that precedes every machine cycle. When SYNC is
high, the status word should be loaded into an octal latch
on the positive edge of 1. The outputs from the latch can
then be decoded to specify whether the machine cycle is a
memory write, memory read, I/O write, or I/O read. The
Intel 8228 or 8238 System Controller provides this status
latch and additionall~codes the outputs of the status
latch with DBIN and WR to generate four timing signals
MEM R (Memory Read), MEM W (Memory Write), I/O R
(I/O Read), and I/O W (I/O Write). However, the 8228 and
8238 do not provide the outputs of the status latch. The
timing between the address bus, data bus, WR, and SYNC

REFRESH CONTROLLERS
Figure 5 shows a REFRESH CONTROLLER for a 16
character 18 segment alphanumeric display. The circuit
operates by interrupting the microprocessor at a 1600 Hz
rate. Following each interrupt, the microprocessor
responds by outputting a new ASCII character to the
Texas Instruments AC5947 ASCII to 18 Segment
Decoder/Driver and a new digit word to the 74LS174. The
character font for the AC5947 is shown in Figure 6. The
outputs of the 74LS174 are decoded such that digit word
0016 turns the leftmost display character on, digit word
OF16 turns the rightmost display character on, and digit
word 1F16 turns all digits off. The interface can be
expanded to 24 characters with an additional Signetics
NE590 driver. This change would also require modifications in IF peak, and the interrupt rate.

433

MEMORY AND liD WRITE BUS TIMING

MINIMUM TIMES (nS)

8080 MICROPROCESSOR
WITH 8228 CLOCK

,tAW

twA

'OW

740

90

230

90

380

560

80

'40

80

8080A-l, tCY = 320

470

70

110

70

soaOA, tcy = 480

BoaOA-2, tCY

--.I

'03

I

l.I

tAW'" 2tcy - t03 - t140(A), 130(A-2), '10(A-l1}

I

I
twA

I

!

(A'5 - A O ' .

J

SYNC

II

VALID ADDRiESS

~

I

:

I

:

I

I

:____ NOTE'

I

~ NOTE 2

I

.

I

=

two

I-- 'OW -+lI

NOTE 1:

NOTE 2:

Additional wait cycles can be

low prior to the falling edge
of 1->2 during the clock cycle
pteceeding the falling edge of

I

I

i

Status Word should be loaded
into an octal latch when
SYNC'" 1 on positive edge
of ¢,.
inserted here, A wait cycle is
added by forcing READY

!.'WO..J
I

I

----1r-------i1

103 + 10

From INTEL Component Data Catalog, 1978

~AlIoo8 I

L.._-l.---'

=

tow'" tCY - t03 - [170IA), 170(A-2), 150(A-1)!

iI :
tl.:-=--=--=-~-=--=--'A-W--_
---I---+:
_
_ ....!.-r-'W-A-.j.J

ADDRESS BUS

=

'wO

WA.

I

Figure 4. Memory and I/O Write Timing lor the Intel 8080A Microprocessor Family

,

33\1 T'fP

A,
A,

23

19

, ,•

C

~,,[
'US

10

DO

A,
13
A,
A,
16
A,
17 A,

0,

D,

ADDRESS [
'US

.,

AO

"

.
-l-L";:J 1i1:
r
74LS04

"V

VM.

A"
A13
A15

6800

.]

--'-f

",
,,
•

28

L

Co

~C345~

1

IRa

'K

V"

'

,

1600 Hz

C

0,

E
F

0,
0,

17

HDSP6508

.,
E

"
,

H

H

LEFT

J

J

K

K

L

L

M

M
DP
Co

DP
Co

I:

HDSP650B

F

345678

21610

RIGHT

, ,,,

1]:1::1:' 1:

4 5 6 7 9 10" 12
0 0 0 1 02 Q3 Q 4 0S0607

4~
5~

4

5

6 7 8

2161015
5 6

11'

7 9 10 11 12

CloQ,Q2Q3Q40sQSQ7

am

, , , ,3~

V"

2Q

,a
,a

~ 4D
13

r'--

•

50

AoA,

,,

A2 0CECLR

,

13

~

,a ,,

~ 10
~2D
L...-..! '0

220K

NE590

NES90

AOA,AZ 0

NE 555

TIMER

C

14L8138

V"

, ..-1-1

25

¥

<2-r-;:--

~

6800

<..t<".I

9

M "

,

,,"

25
20
16

DP 21

CK

~.,
I
~

0

5

24

,

", .,
18
"
,
,
,
,
,,

20

AC5947N J

~,

"

"

7

23

DE

V"

---Lc
I --+=:2

A,.

11

K 3

I
I

6

24

7

H

--<> 1""<>-

I

F

I

8080A

....

E

A,
A,

A,
A,

" ,
, D,

0, 6
02 27

Ao

,."

0,
0,
0,

19

50
74LS174

7
10

"

' V.... ,

7,LS04

CK

•

27K

.0033J,1F

Figure 5. 6800 or 8080A Microprocessor Interlace to the HDSP-6508 REFRESH CONTROLLER Utilizing the Texas Instruments
AC5947 ASCII to 18 Segment Decoder/Driver

434

0,
DO

0
0
0
0

HEX

0
(space)

03
O2

BITS

D6 05 04

o

1

0

2

o

1

,

3

,

0

0

4

1

0

1

5

0
0
0

,
,

0
0

0
0

0

,,

2

3

,

0

0

0
0

,
,
,

0

,

A

B

C

°

E

F

1
0
6

7

0
0

0

4

5

,

,, ,, ,,
, ,

,
,0

0

0

,
,

,, , ,
,
,

, ,

0

,

0

0
0

0
0
0

8

9

,
0

/
I 9] % 1: I < >
+ ?
0 I [1 3 Y 5 6 1 B g
L
[!:! R B [ ] E F G H I J I-< L M N 0
P Q R 5 T U V WX YZ [ \ J / ~
I

1/

*

/

~

/

Figure 6, 18 Segment Display Font for the Texas Instruments AC5947 ASCII to 18 Segment Decoder/Driver

delay, the next digit is turned on. Registers "POINT" and
"DIGIT" are then updated by the program. Following
execution of the "RTI" instruction, execution of the main
program is resumed. A similar program written for an
8080A microprocessor is shown in Figure 8. The 6800
microprocessor program shown in Figure 7 operated with
a 1 MHz clock requires 0.11% + 0.72n% of the available
microprocessor time to refresh the display at a 100 Hz
refresh rate, where n is the display length. The 8080A
microprocessor program shown in Figure 8 when
operated with a 2 MHz clock requires 0.31% + 0.96n% of
the available microprocessor time to refresh the display at
a 100 Hz refresh rate, where n is the display length. For
example, the 16 character display shown in Figure 5

A 6800 microprocessor program that interfaces to this
REFRESH controller is shown in Figure 7, Following each
interrupt, the program "RFRSH" is executed. The program
uses a scratch pad register "POI NT" that points to the
location within a 16 byte ASCII message of the next ASCII
character to be stored in the display interface. The scratch
pad register "DIGIT" contains the next digit word to be
loaded into the display interface. The program interfaces
to the circuit through two memory or I/O addresses. A
memory write to address "SEG" writes a six bit word into
the AC5947, and a memory write to address "DIG" writes a
five bit word into the 74LS174. To prevent undesirable
ghosting, the digit drivers are turned off prior to loading
the next ASCII character into the AC5947. After sufficient

LOC

r

0000
0002
0003
0400
0400
0402
0404
0406
0409
040C
040E
0410

OBJECT CODE
SEG
DIG

EQU
EQU

SBF04
$BF05

0003
00

POINT
DIGIT
DATA

FDB
FCB
RMB

DATA
0
16

ORG
LDX
LDAB
LDAA
STA A
STA B
LDAA
CMPA
BEQ
INC
INX
STAA
STX
RTI
CLR
LDAB
STAA
SUB B
STA B
BCC
DEC
RTI

$0400
D,POINT
X,D
I.SIF
E,DIG
E,SEG
D,DIGIT
1,15
LOOP I
E.DlGIT

DE
E6

86
B7
F7

96

0422
0425

81
27
7C
08
B7
DF
3B
7F
F6
87
CO

0427
0429
042B
042E

24
7A
3B

0412
0415
0416
0419
041B
041C
041F

SOURCE STATEMENTS

BF04
BF05

D7

00
00
IF
BF05
BF04
02
OF
OA
0002

RFRSH

BF05
00

0002

LOOP I

0001
BF05
OF
01
03
0000
LOOP2

A

=

157

YES

E.DlG
D,POlNT
E,DlGIT
E,POINT+I
E.DlG
1.15
D,POINT+I
LOOP2
E,POINT

e
Figure 7. 6800 Microprocessor Program and Flowchart that Interfaces to the REFRESH CONTROLLER Shown in Figure 5

435

LOC

OBJECT CODE

OOIC
OOID
EOOO
E002
E003

03
00
00

F5
E401 E5
E402 2A
E405 3E
E407 D3
E409 7E
E40A D3
E40C 3A
E40F D3
E411 FE
E413 CA
E416 3C
E417 32
E41A 23
E41B 22
E4IE EI
E4IF FI
E420 C9
E421 3E
E423 32
E426 7D
E427 D6
E429 6F
E42A D2
E42D 2S
E42E C3

EO

EQU
EQU

OOICH
OOIDH

POINT
DIGIT
DATA

ORG
DW
DB
DS

OEOOOH
DATA
OOH
16

ORG
PUSH
PUSH
LHLD
MYI
OUT
MOY
OUT
LDA
OUT
CPI
JZ
INR
STA
INX
SHLD
POP
POP
RET
MYI
STA
MOY
SUI
MOY
JNC
OCR
JMP

OE4ooH
PSW
H
POINT
A,IFH
DIG
A,M
SEG
DIGIT
DIG
15
LOOP I
A
DIGIT
H
POINT
H
PSW

RFRSH

E400

ooEO
IF
ID
IC
02EO
ID
OF
21E4
02EO
OOEO

LOOP2

00
02EO

LOOPI

OF
IBE4
IBE4

SOURCE STATEMENTS

SEG
DIG

A,O
DIGIT
A,L
IS
L,A
LOOP2
H
LOOP2

Figure S. SOSOA Microprocessor Program and Flowchart that Interfaces to the REFRESH CONTROLLER Shown In Figure 5

requires 11.6% of the 6800 microprocessor time or 15.7%
of the 8080A microprocessor time to refresh the display at
a 100 Hz refresh rate. Faster versions of the 6800 and
8080A microprocessors can reduce this microprocessor
time by 50%.

(3/4) or 1/42.6. For values of Rand C specified. the display
is strobed at a 130 Hz refresh rate.

Data is entered into the RAM from the address and data
bus of the microprocessor via two control lines. Chip
Select and Write. When Chip Select goes low. the address
generated by the counter is disabled and the microprocessor address and data bus ~ted to the RAM.
Then. after sufficient delay. the Write input is pulsed.
which stores the data within the RAM. The data entry
timing for the 18 segment DECODED DATA CON-.
TROLLER is shown in Figure 11. Because of the
requirement that the address inputs of the 6810 RAM must
be stable prior to the falling edge of Write. Chip Select
should go low for time tcw prior to the falling edge of
Write. To guarantee thatthe address and data inputs of the
RAM remain stable until after Write goes high. Chip Select
should remain low fortime tCH following the rising edge of
Write. This requirement for two separate timing signals is
also required for the CODED DATA CONTROLLER
shown in Figure 15. Because this interface timing is
somewhat more difficult than the previously described
circuits. the following methods are presented for
interfacing to commonly used microprocessors.

DECODED CONTROLLERS
Figure 9 shows a DECODED DATA CONTROLLER
designed for a 32 character 18 segment alphanumeric
display. To simplify the circuitry. the display is configured
as a 14 segment display with decimal point and colon. This
allows each display character to be specified by two 8 bit
words. One possible display font is shown in Figure 10.
The Motorola 6810 RAM stores 64 bytes of display data
that are continually read and displayed. The display data
is organized within the RAM such that addresses As. A4.
A3. A2. and A1 specify the desired character and address
Ao differentiates between the two words of display data for
each character. The display data is formatted such that
word 0 (07-00) is decoded as G2. G1. F. E. D. C. B. and A;
and word 1 (07-00) is decoded as COLON. DP. M. L. K. J.
I. and H. The display data is coded low true such that a low
output turns the appropriate segment on. Strobing of the
display is accomplished with the 74LS14 oscillator and
74LS393 counter. The counter continuously reads display
data from the RAM and enables the appropriate digit
driver. The time allotted to each digit is broken into four
segments. During the first segment of time. the display is
turned off and work 0 is read from the RAM and stored in
the 74LS273 octal register. During the next three
segments of time. word 1 is read from the RAM and the
display is turned on. Thus. the display duty factor is (1/32)

Interface to the 6800 microprocessor family is accomplished by NAN Ding together VMA and some specified
combination of high order address lines to generate Chip
Select and using cf>2 to generate Write.
For the 8080A and 8085A microprocessor families. the
limited flexibility of the output instruction requires that the
18 segment DECODED DATA CONTROLLER must be
addressed as memory instead of 1/0. The 8080A micro-

436

""'"

~

n~'
"

o0 67

~,
~

~:6'

,.

[
BUS'
0,
0,

7Y'

'.7

:H,

'"

kim,

lTV"
.

~'"
11
~

6y7
,y'

,.
••
,,"
',." "

"

'g n"
">..W"
"'; '"

o.

6
"tI

10!) (TYP)

V

I"
•
OP

U'N20"

r,

_

~:

70'

ADDRESS[::
BUS
A3------I-"-I

"

2:

DO
,

11

•)

I I I I I I

10

I

I~;

.a,

0'

LJ

LJ

LJ

:H
7a

74LS273

hi

~

B>-------+

HOSP-6508

" c

'0 Po

.,----+~

"

HDSP-6508

2·

,a'

.,------1-....

.
"' .

"
~H

""

80 119
16

II

HOSP-6508

v.

'234561

J

45618

I_Li_Li

i

i ,j.d._I .. \

i

i

Vee 10

774LS14

...

I

~

Vee 16100Q1Q2QJu....." .... u

1

4

laB
10

2

Ice

r

2a~

~

' '1'2 10 6

4

2

5

~

9
~8

9
8

1'~

74LS32

....

WRm~
14LS32
B

L..!!.-.

_

~31

>

II
I

10

14LS14
14LS14
1!.f'..._12

VMA

A,S

I

I

II

V

11

8080A MICROPROCESSOR INTERFACE (UTILIZING 8233 SYSTEM CONTROLLER)

6800 MICROPROCESSOR INTERFACE

GENERAL INTERFACE

CHWruECT

14LS14

T

I

112IJll~~5

•

g ........ _ 8

~~

ABCDGCL

4

-11

7ac0 11
6

20
2CL

74LS32
4

5 5" ,

132A:~:'0
12

.'l1 f

i1j2 IJ r'1~5

74LS361

ISA5A4A 3A 2A lA

14LS393
1 ,...-.:..:..:.lA
4

3

~5Y4Y 3Y 2Y ' ]

~~
~G2

" ''u""i£,.
":'r-

00Q'02030405 0607

......

1,,1111.171, "

.,,---=----'1

21
_

A14

---t-:-:-r"""

A"
A"
AU

"I

0D
5

A 13

A12

:1

•

MEMW----------------~
FROM INTEL 8238 SYSTEM CONTROllER

2~
TO 6800

FROM INTEl 8224 CLOCK GENERATOR

Figure 9. 6800, 8080A, and General Interface to the HDSP-6508 DECODED DATA CONTROLLER

J-======J------.J

"2 (TTll _ _ _ _ _ _ _ _ _ _ _ _

I

03

0
0
0
1

0
0
1
0

0
0
1
1

0
1
0
0

0
1
0
1

0
1
1
0

0
1
1
1

1
0
0
0

1
0
0
1

1
0
1
0

1
0
1
1

1
1
0

DO

0
0
0
0

HEX

0

1

2

3

•

5

6

7

B

9

A

B

C

2

(space)

I

I

< > *-

O2

BITS

01
0 6 0 5 D.

o

1

0

o

1

1

1

0

0

1

0

1

" I :E % .E

0

+

/

1
1
0
1

1
1
1
0

1
1
1
1

°

E

F

/

-

L 0 I 2 =:I y ~ 5 l B 9
?
• [E R B [ lJ E F G H I J I-< L M N 0
P Q R 5 T U V W X Y Z ~ \ 1 1\ -3

~

/

5

Figure 10. One Possible 16 Segment Display Font (14 Segments Plus Decimal Point and Colon) lor the DECODED DATA CONTROLLER
Shown In Figure 9.

processor requires an external status latch to hold status
information provided during program execution. This
status latch function can be implemented with an octal
register such as the Intel 8212 or 74LS273. A Memory
Write signal can be generated by NORing together all
outputs of this status latch. This signal can then be
NANDed with some specified combination of high order
address lines to generate Chip Select. The 8080A WR
output can then be connected to Write. The Intel 8238
System Controller, which is commonly used with the
8080A microprocessor, prevents direct access to the
outputs of the status latch. An example of an interfacing to

a system utilizing the 8238 is illustrated in Figure 9. MEM

IN from the 8238 is inverted and then NANDed with some
specified combination of high order address lines to
generate Chip Select. The 74LS113 generates Write from
the microprocessor clock, <1>2 (TTL).
Interface to the 808SA microprocessor family can be
accomplished by inverting the IIOIM output and
NAN Ding the resulting signal with the So output and some
specified combination of high order address lines to
generate Chip Select. The WR output from the
microprocessor is connected directly to Write.

GENERAL INTERFACE

'wc

7'cw----

tWR -----

X

ADDRESS

X

-

-I='AW"'\

t=

•

PARAMETER

X

'w.

425n5

'cw
'ow

65n5

WRITE DELAY

DATA seTUP

'I

DATA

MIN.

'WC
'AW

~·ENAB·LE TO WRITE

'CH}=t-

tow - - - - - - .

SYMBOL

WRITE CYCLE

-l-

I-- 'OH_

.

65n5

21005

DATA HOLD

'OH

35ns

WRITE PULSE

'wp

325m

WRITE RECOVERY

'WR

25m

CHIP ENABLE HOLD

'CH

35m

WAITE

8080A MICROPROCESSOR INTERFACE

I
I

1>2 ITTLI
6800 MICROPROCESSOR INTERFACE

ADDRESS

I:

VALID ADDRESS

FROM 8224

I:

ADDRESS

~------------~I

I

DATA

o

:VALlOO+

DATA

I
I

(CHiPSELEcT,

I

~_ _--r-.....

MEM W (CHIP SELECT)
FROM 8238

o

:

: I

1
...._ _ __ _

I

------~~r------

Figure 11. Data Entry Timing lor the DECODED DATA CONTROLLER Shown in Figure 9

438

I

1

(WRITE)

iI

I

9

PAD'''''' ADDRE'SS OF DISPLAY

LOC

0000
0002
0004
0006
0400
0400
0403
0405
0408
040A
040C
040E
040F

0411
0412
0414
0416
0418
04IA
041C
041E
04lF
0421
0422
0424
0427
0429

OBJECT CODE

SOURCE STATEMENTS

BFOO
0600

DSPLY
DECDR

EQU
EQU

IBFOO
10600

0006
BFOO
0600

ASCII
PADI
PAD2

FDB
FDB
FDB
RMB

MESSGE
DSPLY
DECDR
32

ORG
LOX
STX
LOX
STX
LDX
LOA A
INX
STX
ASLA
STAA
LOX
LOA A
LDAB
LOX
STAA
INX
STA B
INX
STX
CPX
BNE
RTS

10400
I,DSPLY
D,PADI
I,DECDR

MESSGE
CE
DF
CE
DF
DE
A6
08
DF
48
97
DE
A6
E6
DE
A7
08
E7
08
DF
8C
26
39

BFOO
02
0600
04
00
00
00
05
04
00
01
02
00
00
02
BF40
EI

LOAD

LOOP I

D,PAD2

D,ASCII
X,O

NOT DONE

D,ASCli

D,PAD2+1
D,PAD2

X,D
X,I
D,PADI
X,O
X,O
D,PADI
I,DSPLY+64
LOOPI

PAD1 ,. ADDRESS OF
OISPlA Y + 64?

NO

(lOOP1)

Figure 12. 6800 Microprocessor Program and Flowchart that Interlaces to the DECODED DATA CONTROLLER Shown In Figure 9

L

The simplest interface to the Z-80 microprocessor family
is accomplished by addressing the 18 segment DECODED DATA CONTROLLER as 1/0 instead of memory,
An example of this interface is shown in Figure 15, The
lORa output is inverted and NANDed with some specified
combination of address lines to generate Chip Select. The
74LSl13 circuit generates Write from the inverted microprocessor clock ~,

DECODED DATA CONTROLLER, The corresponding
8080A microprocessor program is shown in Figure 13,
This program requires 1.4 ms for a 2 MHz clock to decode
and load 32 ASCII characters into the 18 segment
DECODED DATA CONTROLLER.
The 64 character ASCII font shown in Figure 10 can be
generated using the table shown in Figure 14. This ASCII
decoder uses two 8 bit words to represent each ASCII
character. The format of the decoder is consistent with
either the 6800 microprocessor program shown in Figure
12 or the 8080A microprocessor program shown in Figure
13.

A 6800 microprocessor program that interfaces to the 18
segment DECODED DATA CONTROLLER is shown in
Figure 12. This program decodes 32 ASCII characters and
stores the resulting decoded display data within the
display, The scratch pad register "ASCII" points to the
location of the next ASCII character to be decoded, The
program reads the first ASCII character, increments the
point, "ASCII," and then looks up two words of display
data within the 64 character ASCII look-up table
"DECDR," These words of display data are then stored at
the two addresses for the leftmost display location,
Subsequent ASCII characters are decoded, and stored at
the appropriate address within the display until all 32
characters have been decoded, After the program is
finished, the pOinter "ASCII" will have been incremented
by 32, This program requires 2,4 ms for a 1 MHz clock to
decode and load 32 ASCII characters into the 18 segment

CODED DATA CONTROLLERS
Figure 15 shows a CODED DATA CONTROLLER
designed for a 32 character 18 segment alphanumeric
display, Operation of this circuit is similar to the
DECODED DATA CONTROLLER shown in Figure 9
except that the Motorola 6810 RAM stores 32 six bitASC11
words and the Texas Instruments AC5947 decodes this
ASCII data into 18 segment display data, The resulting
display font is shown in Figure 6, Strobing of the display is
accomplished by the 74LS14 oscillator and 74LS393
counter. Because the long propagation delay through the
AC5947 tends to cause display ghosting, the display is

439

we

OBJECT CODE

EOOO
E002

02
00

E400 01
E403 II
E406 2A
E409 7E
E40A 23
E408 07
E40C SF
E40D IA
E40E 02
E40F 13
E410 03
E411 IA
E412 02
E413 03
E414 79
E415 FE
E417 C2
E4IA 22
E4ID C9

SOURCE STATEMENTS

DSPLY

EQU

OBFOOH

EO

ASCIJ
DATA

ORG
DW
DS

OEOooH
DATA
32

ooBF
ooE5
ooEO

WAD

ORG
LXI
LXI
LHLD
MOY
INX
RLC
MOY
LDAX
STAX
INX
INX
LDAX
STAX
JNX
MOY
CPI
JNZ
SHLD
RET

0E400H
B,DSPLY
D,DECDR
ASCIJ
A,M
H

BFoo

WOPI

40

O9E4
ooEO

E,A
D
B
D
B
D
B
B
A,C

NOT DONE

64

WOPI
ASCII

(lOOP1)

Figure 13. 8080A Microprocessor Program and Flowchart that Interfaces to the DECODED DATA CONTROLLER Shown In Figure 9

ASCII SYMBOL WORD 0
FF
20 (SPACE)
FF
21
DF
22
23
36
#
$
24
12
25
IB
%
26
F2
~
27
FF
FF
28
FF
29
2A
3F
2B
3F
FF
2C
2D
3F
2E
FF
2F
FF
CO
30
0
FF
31
I
32
2
24
33
3
30
34
4
19
35
5
96
36
6
02
37
7
F8
38.
8
00
18
39
9
3A
FF
FF
3B
7F
3C
~
3D
37
3E
BF
>
3F
7C

,

"

i

WORD I
FF
BD
FD
ED
ED
D2
CA
FD
F3
DE
CO
ED
DF
FF
BF
DB
DB
ED
FF
FF
FF
F7
FF
FF
FF
FF
3F
SF
FB
FF
FE
EF

ASCII SYMBOL WORD 0
40

@

44

41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
SA
5B
5C
5D
5E
SF

A
B
C
D
E
F
G
H
I
J

08
70
C6
FO
86
8E
42
09
F6
EI
8F
C7
C9
C9
CO

K

L
M
N
0
P

Q

R
S
T
U
Y
W
X
Y
Z
[

\

~

oc
CO
oc

12
FE
CI
CF
C9
FF
FF
F6
7F
FF
BF
FF
F7

WORD I
FD
FF
ED
FF
ED
FF
FF
FF
FF
ED
FF
F3
FF
FA
F6
FF
FF
F7
F7
FF
ED
FF
DB
D7
D2
EA
DB
F3
F6
DE
D7
FF

Figure 14. 64 Character ASCII Decoder Table for the Microprocessor Programs Shown In Figures 12 and 13. 18 Segment
Display Font Is Shown In Figure 10.

440

,.....~

GENERAL INTERFACE

2

74LS02

74LS14

~~.
~

74LS368

~~~.[~~:
~

[

AD~~SS ~

A3
~

i"(NOTE 1) ~~--------'

III
II

I

--l!-Y" .~:

SA

v"

-r:-L"
-I

SV l'

2.
"i-I

6:::~

17
15
14

DO

A2

01

12

1-::V"

~

D6

~
CS1

CS3

LEFT

=
R/W
25

17

0......
c

,a A

_.

74LS02
S

10.

'"C
tao"

,aA
20 B

10

~10

2ac
,aD

"J.lF~

74LS14
9-", _ 8

74LS02

-::-

I I

HOSp·6S08

I I

M

Co

~47'LS14

II

DP~t===~~~==~~~~~~~~
J"
'T:-i'::i':-i::T.=T.±i:'. 'i-ri.::T:;r.-::T:±."i:-:T! 'T:-T.::T:-i::~±i:'

MCM6810

6

HOSP·6508

HOSP..6508

HOSP.fi508

~5

,.

'6

~:
D.

""

A6
_

11
13

0

1. tf> IS MICROPROCesSOR CLOCK
2. CS IS i'O'R'Q ANOEO WITH THE 1/0 ADDRESS
OF THE DISPLAY
23

A.
A1

,.~I:

2Vr.-+++-<,----.!!!.l
1,
74LS367

....
....
....

B_n.

74LS02

';~S~~2~13
v

Figure 15. General Interfaces to the HDSP-650a CODED DATA CONTROLLER

74LS14
1!Jt.... 10

v

v

17. This circuit is designed around the Intel 8279
Programmable Keyboard/Display Interface. This LSI chip
contains the circuitry necessary to interface directly to a
microprocessor bus and provides a 16 x 8 RAM. programmable scan counter, and keyboard debounce and
control logic. While the 8279 is specifically deSigned for 7
segment displays, inclusion of the Texas Instruments /
AC5947 ASCII to 18 segment decoder/driver allows the \"
use of an 18 segment alphanumeric display. The 8279 .
Keyboard/Display Controller interfaces to a microprocessor via an eight line bidirectional Data Bus, control
lines RD (Read), WR (Write). CS (Chip Select), Ao
(Command/Data). RESET. IRQ (Interrupt Request). and a
clock input, CLK. The display is scanned by outputs AO-3
and BO-3 which are connected to the inputs of the AC5947,
and outputs SLO-3 which are connected to the digit
scanning circuitry. The 74LS122 is used to provide
interdigit blanking to prevent display ghosting. In addition
to display scanning. the 8279 also has the ability to scan
many different types of encoded or decoded keyboards,
X-Y matrix keyboards, or provide a strobed data input to
the microprocessor. The 8279 provides for either block
data entry, where data enters from left to right across the
display overflowing to the leftmost display location; right
data entry, where data enters at the righthand side of the
display and previous data shifts toward the left; and RAM
data entry, where a four bit field in the control word
specifies the address at which the next data word will be
written. The 8279 allows data written into the display to be
read by the microprocessor, and provides commands to
either blank or clear the display.

GENERAL INTERFACE
twc
I+--tcw--'

twR_

X

ADDRESS

-

. !=="tAW ____

""

.'=X
tCH

}=r
'I

tow

tOH .....

X

DATA

.

twp

WRITE
Z-BO INTERFACE

-~

I

SYMBOL

MIN.

WRITE CYCLE

PARAMETER

twc

455••

65..

WRITE DELAY

tAW

CHIP ENABLE TO WRITE

tew

65 ..

DATA SETUP

tow

215n,

DATA HOLD

tOH

50ns

WRITE PULSE

twp

340ns

WRITE RECOVERY

tWR

40••

CHIP ENABLE HOLD

tCH

SOns

Figure 16, Data Entry Timing for the CODED DATA
CONTROLLER Shown In Figure 15

The HDSP-8716/-8724/-8732/-8740 DISPLAY PROCESSOR CONTROLLER shown in Figure 18 is designed to
provide a flexible 18 segment display interface for displays
up to 40 characters in length. This circuit utilizes a
dedicated Intel 8048 Single chip microprocessor to
provide features such as a blinking cursor, display editing
routines, multiple data entry modes, variable display
string length. and data out. This controller is available as a
series of printed circuit board subsystems of 16, 24, 32,
and 40 characters in length. The user interfaces to the
8048 microprocessor through eight Data In inputs. six
Address inputs, a Chip Select input, Reset input, Blank,
input, six Data Out outputs. Data Valid output. Refresh
output, and Clock output. The software within the 8048
microprocessor provides four data entry modes - Left
Entry with a blinking cursor, Right Entry. Block Entry, and
RAM Entry. The Data Out port allows the user to read the
ASCII data stored within the display, determine the
configured.data entry mode and display length, and locate
the position of the cursor within the display. Since the
Data Out port is separate from the Data In port, the 18
segment DISPLAY PROCESSOR CONTROLLER can be
used for text editing independent of the main microprocessor system. In Left Entry mode. the controller
provides the Clear, Carriage Return, Backspace, Forwardspace, Insert, and Delete editing functions; while in Right
Entry mode, the controller provides Clear and Backspace
editing functions. The controller can also be expanded
into multiple line panels.

blanked momentarily after each new character is read
from the RAM. This is accomplished by breaking the total
time allotted for each digit into four segments. During the
first segment, the display is turned off to allow data to
ripple through the AC5947 and during the next three
segments. the display is turned on. The resulting display
duty factor is (1/32) (3/4) or 1/42.6. The display is strobed
at a 130 Hz refresh rate.
Data is entered into the RAM from the address and data
bus of the microprocessor via two control lines Chip
Select and Write. When Chip Select goes low, the address
from the counter is tristated and the microprocessor
address bus and data bus is gated to the RAM. Then after
sufficient delay, the Write input is pulsed, which stores the
data within the RAM. Data entry timing for the. 18segment
CODED DATA CONTROLLER is shown in Figure 16.
Since this timing is very similar to the DECODED DATA
CONTROLLER shown in Figure 9, interface to the various
microprocessor families is the same as described in the
section on DECODED DATA CONTROLLERS.

DISPLAY PROCESSOR CONTROLLERS
The DISPLAY PROCESSOR CONTROLLER provides a
powerful. smart interface which performs many of the
functions normally found in a small terminal. The
DISPLAY PROCESSOR CONTROLLER is designed
around a slave microprocessor or custom LSI integrated
circuit that provides display storage and multiplexing with
a very minimum of circuit complexity. The simplest
DISPLAY PROCESSOR CONTROLLER deSigned for a 16
digit 18 segment alphanumeric display is shown in Figure

The 8048 microprocessor interfaces to the display via the
Port 2 output. The output is configured to enable the
microprocessor to send a six bit word to one of three
destinations as selected by P26 and P27. The PROG output
442

v"

..•" ,.••
..'. ·
" "
.,., 6
" "".
•
,
I,

V"

1;0

UK

V"
QUlA,

OUTAg
DUTB3
DUTB Z

OUTB,
DUlBo

,.

7

C
AC5947 D,

fTYPI

Z1

17

0,

1&

E

Z1

22

20

F

28
28

23

13

30

'0

31

24

H

I

28

J

~

INTEL

9279

DATA

BUS

f

[-----;j~;.t ~~
~:

,

K
L
M

DE

CK

':"

*6

28

21

DP
Co

25

'0

11
22

..,

23

22

24
11

·, .,
E

20

H
I

,.,. .,
"•
,•

·

17

t----;;
t-----f,

C
0,
0,

7
26

.

r--;,
t-----ii" ""

" "•

~
t----;-

C
0,
0,

r----=;-

~

F

~

H
I

E

.,
t---t." .,
~

F

HDSP-6508

----To"
---..:;-

J
K

HaSP·650B

J

-;
-;
~
--1!. ~2
'1211'
K

L

L
M

M

DP
'?OZ

DP

3 4

5

8

7

B

3 4 5

6

7 •

. . 0, . . 0,0. . . . . 0,

DBa

NE590

HE 590

Ao A,AZ 0 am

DBO
RD

''0

",

WR

..
•

.0

RESET

A, AZ 0

CE CLR

33

", ,.
'"

cs

At>

32
34

V"

, •

21

•
,

23

,0 '6 "1141"
16 ~1 8 " 1~!b4

=====t"~:~
12

47n1TVP)

,

vi:: ::

23

IRO

B1 Aint

'A2

0

eLR C.xt

CLK

-=-

13

14LS1Z2

"

4700pF
':"
RL7~r--

~~
~~
~~
~~

---------------------,

~~

I
I
I
I
I
I

I

I

RL Z ~

KEYBOARD

RLon
I
r-L- _________ _______________ J
36

I

SHIFTn

[

CNTL/STB

L---,=.... v..

1:

0

Figure 17. HDSP-6508 DISPLAY PROCESSOR CONTROLLER Ullllzing Ihe Inlel 8279 Programmable Keyboard Display Inlerface

is then used to store this word at the specified destination.
Destinationo is the 74LS174 hex register. The outputs of
this register are decoded by the 74LS259 addressable
latches and Sprague ULN 2815 digit drivers. Output 3F16 is
decoded to turn on the rightmost' aisplay digit while the
address of the leftmost display digit varies from 1816 for a
40 character display to 3016 for a 16 character display.
Destination1 is the AC5947 18 segment decoder/driver.
The positive edge of PROG stores a six bit ASCII code
within the AC5947. Because destination1 is pulsed once
every time a digit is refreshed, this output is also used as
the Refresh output. Destination2 is the Data Valid output
of the Data Out port. Thus, Data Out actually consists of a
series of six bit words that are sentlo Destination2. Display
refresh is accomplished by first turning off the digit drivers
by outputting a 016 to the 74LS174. Then a new ASCII
character is stored within the AC5947. Finally, a new digit

word is stored within the 74LS174. The actual time that
each digit is on varies according to the configured display
length so as to provide a fixed 100 Hz refresh rate.
Interfacing the DISPLAY PROCESSOR CONTROLLER
shown in Figure 18 to microprocessor systems depends
on the needs of the particular application. Since the
information on the Data In and Address inputs is loaded
into the controller through a program within the 8048
microprocessor, the time required to read these inputs
varies from about 100 to 700 microseconds. A latch as
shown in the HDSP-8716/-8724/-8732/-8740 Data Sheet
can be used as a buffer between these inputs and the data
bus and address bus of the main microprocessor system.
The latch provides temporary storage to avoid making the
main microprocessor wait for the DISPLAY PROCESSOR
CONTROLLER to accept data.

443

121! (TVP) HDSP-8732/-8740
22S1ITVP) HDSP.8716/-8724

v"

I,

Co

O'T'OUT[~~;~~~:~::~~~
J1

00

2

001

(23)

DOD

(221

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19

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I"

tI/

M

II~

E

"

m

I"
I"

2.
22

~....I~2·~'----------------l

R''''''''H'''"
_~

,I

(33)

•
'4 "

U

HDSP·6508

HOSP·6508

Hasp·65GB

HOSP·6S08

{LEFT!

(RIGHT!

23

(13)

25

,al

BLANK

HDSP·65GB

K

L

(12)

T

0,
E

(10)

"

111111'1leK

.,
M

(11)

DATA VALID

Co

18 G
2

141

0,

I A4
IIAJ

_ (24)

121

"I

I •

"

(1)

25

G2

*l"
~

J3

28

0,

\ll'~Op

10K

~-~~~:
---

E:II

''''!I.-~~--=-I

RESET -.:.:""'''-.....

111111

11~12

(181

..

Vee...!!

r - - - - -.....-~E.

AS

M>M>M>-

[

ADDRESS

!LEfn

32

P'5

A4

(9)

tERI)

31

P'4

171

CElli

30

P13

A2
A

(5)
(31

29 P'2
28 P

01

1201

,. BUS,

01:

(18)

18 BUSe

,

111

11

P,o

01

1161

17 BUSs

1141
1121

01:
01,

110)
(8)

16 BUS.
15 BUS 3
14 BUS 2
13 BUS,

010

161

12 BUSo

~

(41

SIRO

READY

ACTIVE

EXPAND

1281

Vr;c 16100 0102 Q3~----.
74LS259

01:
01

DATA IN [

3~

J4
74LS174

:27 :
26

33

24

6Y

24

5Y

P23 23

4V

P22 22

3Y

::~

~~

(61

)O"'-""c.I~>--t---~f--7-----*+--+----f--+----'
74LSOO

",=,---,I~al~:~_+_ _--.J

"'",O-;:I::s:,~'~_+_____+-___--4_-I_ _ _--'

~~

21

_ t

-

CLOCK OUT ....,.,I30::::!..'_ _---"-"-_ _---''-1
PROG· 25

7
1. I
I
!.L
!.L
YL1 jJFI "*1 $AFT PFT jJFI l
.01

Vee

J[::;::~::T
,
:

-=-

~

74LSl39

-=-

.1.20

J2

33

2Q~==;:;:==j::~:E~==E~~tE=E=~S~=:1=~~tE=t=~~~===~~J

P'6

-'-I

33

(31

17+---'

---'I~21'---_.,..._ _ _ _

121

~

r;c~

~

74LS367

:25 ::

34

74LSOO

V

30

~P17

(13)

111

ULN28r5

-

8048

A3

Ao

1111

ULN28IS

ULN28IS

XTAL 2

RAM

6 78

-=-

+--II---....-..!.lXTAl,

-=-

34 5

.01

Vr;c

.01

CONTROLLER

BO~D fOR HDSP-8716/8724/8732/8740

Figure 18. HDSP-8716/-8724/-8732/-8740 DISPLAY PROCESSOR CONTROLLER

' - - - - - DISPLAY BOARD FOR HDSP-8716

t

:

I

I

1 :

:,
1\

\

--.J

DISPLAY BOARD FOR HDSNI124 _ _ _ _- J
DISPLAYBOARDFORHDSP-8132---------'

DISPLAY BOARD fOR HDSP-8740 _ _ _ _ _ _ _ _ _ _ _ _--.J

ation, the main processor could output a prompting
message to the user via the DISPLAY PROCESSOR
CONTROLLER. The user could then enter data from the
keyboard into the display utilizing the controller's editing
capability. Afterthe message has been entered and edited,
the user would instruct the main microprocessor to read
the final edited message from the Data Out port. One port
from the PIA can be used to control the Data In inputs of
the DISPLAY PROCESSOR CONTROLLER and another
port of the PIA can be used to read the Data Out port.
Figure 19 shows a 6800 microprocessor system using a
Motorola 6821 PIA to control the DISPLAY PROCESSOR
CONTROLLER shown in Figure 18. The PB7 output of the
PIA determines whether data is entered into the controller

The 18 segment DISPLAY PROCESSOR CONTROLLER
shown in Figure 18 can also be interfaced to the main
microprocessor system through a Peripheral Interface
Adapter (PIA). The Data In inputs of the controller would
be connected to an output port of the PIA. In RAM Entry
mode, the Address inputs of the controller would be connected to another output port of the PIA. The PIA provides
a handshake back tothe main microprocessor system that
tells when the DISPLAY PROCESSOR CONTROLLER is
ready to accept another data input word from the main
microprocessor. This allows the microprocessor to load
data into the controller at the highest possible rate. A PIA
can also be used to allow the 18 segment DISPLAY
PROCESSOR CONTROLLER to act as a buffer between a
keyboard and the main microprocessor. In this configur-

15

PB,
PB,

- f2L
- ~
- r2L
- r1L
- r1L
- r1L
- r1L
- rE- r1L
- ~

BUS
DATAt

VMAA15

A,

PBs
Ps..
PB,

0,
0,

PB,
PB,

05
0,

PBo
CB,

0,
0,

C8,

0,

Do

PA,

CSo

PAs
P,,"

CS,

PA,

~

27

14
13

26
25

12
11
10

2.
23
22
2.

18

~SI3'-1Kee
198
9
+
•

10

20,uF

lK

-=

14

8
7

11
5

6

2

P10

- f-llc CS,
Ao ~ RSo

A"

A,
R/W

-

elL RS,

-

..1L

R/W

.2L

E

RESET -..1!<:

[

IRa

~

6
3

c..!...

iffiEj'
TRQij

PA,
PA,
PA,
PA o

----=fl2...

5
4
3

14
11

5

2

2
13
10

MOTOROLA

6821

6
3

.-....!....

t-

CA,

4V
3V

3B
2B
lB

2V
IV

12
9

20
18

7
4

16
14

DISPLAY
PROCESSOR
CONTROLLER

4A
2A
lA

4V

12

12

9
7
4

10
8

3V

4B
3B
2B
lB

2V
lV

6

01,

01,
01,
01 0

SEL
ST

READY

lJ xcr-

If 1000pF
11

~I>A,

ER 0 6 050403 02 D1 Do ST

01 5
01,

3A 74LS157

r.-":,
"u'"
r.:< I>A~

MICROSWITCH 61SW12-1 KEYBOARD

DI,
01,

HDSP8716/87241
873218740

13

l000pF

DATA VALID

SEL
ST

Vee

H(

DO,
DO,
00 0

2A
lA
4B

28

'--~

DO,
DO,

4A

40

39

005

3A 74LS157

22K
CA,

RESET

17

_
a

CL

-=

1

J

5

CS

74LS132

6

,
-:!:-

I

Figure 19. 6800 Microprocessor Interface to the DISPLAY PROCESSOR CONTROLLER Shown in Figure 18 Utilizing a Motorola 6821 PIA

445

• PORT CONFIGURATION:

"I. PORTA:

"

PAO-PA7 OUTPUTS TO DATA IN OF HDSP-S7XX
CAl (INPUT) MODE 00 SETS FLAG NEG EDGE OF READY
CA2 (OUTPUT) MODE 100 CLEARED MPU READ PRA, SET
NEGATIVE EDGE OF READY
" 2. PORTB:
PBO-PB5
INPUTS DATA TO 6S00 FROM DATA OUT OF HDSP
"
CBI (INPUT) MODE 10 SETS FLAG POS EDGE OF DATA VA
CB2 (INPUT) MODE 000 SETS FLAG NEG EDGE OF ER KEY
CB2 (INPUT) MODE 001 SETS FLAG NEG EDGE OF ER KEY
CAUSING IRQ
PB7 (OUTPUT) LOW ENABLES PAO-PA7 TO MUX
HIGH ENABLES KEYBOARD TO MUX AND KEY
SOOS
S008
S009
SOOA
SOOA
800B
0028
0000
0000

0002

0100
0100
0101
0102
0400
0400
0403
0406
040S
040B
040E
0411
0413
0416

0418
041B
0410
041F
0420
0421
0423
0426
0429
042B
042C
042E

0430
0431
0433
0435
043S
043B
043E
0440
0442
0444
0500
0500
0503
0506
050S
050B
050D
0510

0512
0515
0517
051A
051B
051E
0521
0524
0526
0529
0528
052E

CE
7F
S6
B7

7D
7D
C6
B6
2A
B6
S4
A7
OS
5A
26

7D
B6
2A
39
DE
A6
08
81
27
B7
7D
B6
2A
20
DF
39
7F
7F
S6
B7
S6
B7
86
B7
S6
B7
OE
7F
BD
7D
86
B7
S6
B7
OF

0100
800A
FF
S008
800S
SOOA
2A
800B
FB
SOOA
3F
00
FO
800S
8009
FB
00
00
FF
OD
800S
SOOS
S009
FB
EC
00

8009
SOOB
FF
8008
24
8009
80
SOOA
06
800B

PRA
DRA
CRA
PRB
DRB
CRB
LENGTH

EQU
EQU
EQU
EQU
EQU
EQU
EQU

$SOOS
$SOOS
$S009
$SOOA
$800A
SSOOB
40

MESSGE

ORG
FDB

$0000
TEXT

STATUS
CURSOR
DATA

ORG
RMB
RMB
RMB

$0100
I
I
40

ORG
LDX
CLR
LDAA
STAA
TST
TST
LDAB
LDAA
BPL
LDAA
AND A
STAA
INX
DEC B
BNE
TST
LDAA
BPL
RTS

$0400
I,STATUS
E,PRB
I,SFF
E,PRA
E,PRA
E,PRB
I,LENGTH+2
E,CRB

READ

LOOPI

LOOP2

LOAD
LOOP I 0

LOOPII
ENDL

START

MAIN
SOOA
042C
800A
80
800A
OE
800B

LDX
LDAA
INX
CMPA
BEQ
STAA
TST
LDAA
BPL
BRA
STX
RTS
ORG
CLR
CLR
LDAA
STAA
LDAA
STAA
LDAA
STAA
LDAA
STAA
CLl
CLR
JSR
TST
LDAA
STAA
LDAA
STAA
SEI

FORCE CA2 LOW; CLEAR CB1 FLAG
CLEAR INTERRUPT REQUEST
FROM'iRciB

B

+-

DISPLAY LENGTH + 2

A7 ....· GB1 FLAG

SET ON POSITIVE EDGE
OF DATA VALID

WAIT FOR DATA VALID

MUST BE SAME AS LENGTH

NOT DONE

(Xl ----A
STORE DATA OUT WORD

X

<-

X

+1

ENABLE PORT A TO MUX
BEGIN DATA OUT SEQUENCE
CLEAR CAl AND CA2
CLEAR CHI AND CB2
B '" O?

LOOP!

WAIT FOR DATA VALID

E,PRB
I,$3F
X,O

STORE IN RAM

LOOPI
E,PRA
E,CRA
LOOP2

PAA <-- FFH
OUTPUT DATA OUT
CONTROL WORD TO DISPLAY

NO

(LOOP1)

YES

NEXT DATA OUT WORD
CLEAR CAl AND CA2
WAIT UNTIL READY
CAl fLAG CLEARED?

WAIT FOR READY

(lOOP2)

D,MESSGE
X,O
I,SFF
ENDL
E,PRA
E,PRA
E,CRA
LOOPII
LOOPIO
D,MESSGE

JUMP WHEN DONE
CLEAR CAl AND CA2
WAlT

NOT DONE

$0500
E,CRA
E,CRB
I,$FF
E,DRA
1,$24
E,CRA
I,SSO
E,DRB
1,$06
E,CRB
E,PRB
E,LOAD
E,PRB
1,$80
E,PRB
I,$OE
E,CRB

A +--(Xl

READ ASCII CHARACTER

X +-- X + 1

e

DISABLE KEYBOARD FROM MUX

CLEAR CB I, CB2
ENABLE KEYBOARD TO MUX
ENABLE IRG
IRQ CAUSES JSR TO READ

WAtT FOR READY

NO
(LOOP10)

Figure 20, 6800 Microprocessor Program and Flowchart that Interfaces to the Circuit Shown in Figure 19

446

from the microprocessor system or from the keyboard.
Control lines CAl and CA2 are used to provide a data entry
handshake to allow data to be loaded into the controller at
the highest possible rate. Data is read into the main
microprocessor system through Port B of the PIA using
the CBl input as a data strobe.

Subroutine "LOAD" then loads a series of eight bit words
into the controller. "LOAD" continues to output words
until it reads an FF16 to denote the end of the prompting
message. The instruction sequence LOA A I, $80 and STA
A E, PRB at location 052616 forces PB7 high to connect the
output of the keyboard to the Data In inputs of the
controller. In this mode, the user can enter or edit data into
the DISPLAY PROCESSOR CONTROLLER. The 4B input
of the 74LS157 has been grounded to prevent the
keyboard from loading a control word into the DISPLAY
PROCESSOR CONTROLLER. The instructions LOA A I,
$OE and STA A E, CRB at location 052B16 enables the
"ER" key on the keyboard to interrupt the microprocessor
when the edited message is complete. Subroutine "READ"
would then be used to read data into the 6800 system.
First, subroutine "READ" outputs a special control word,

The 6800 microprocessor program shown in Figure 20 is
used to operate the PIA interface described in Figure 19.
The microprocessor program following "START" is used
to initialize the 6821 PIA. Once initialized, the PIA can be
used either to load data into the controller via the main
microprocessor, allow data to be loaded into the
controller via the keyboard, or to read data from the Data
Out port into the main microprocessor. The instruction
CLR E, PRB at location 051 B16 forces PB710w to connect
the outputs of Port A to the Data In inputs of the controller.

4

,
PB,
PBs
PBs

PI

"",{~
BUS

_

r1.!...

04
0,

f2!!-

- ~
- r-#-

-

A4-

~

27
26

21

25

,.

24
23

20

0,

PA,
PAs
PAs

0,
01

14

3B

11

3'
40

5
2

PA4

,...--E.
10

INTel

6
3

8255A

1

Al-~ A,
A o - - ; - Ao

IIORD-~
IIOWR-~

SYSTEM-~

~

RD
\lirA
RESET

RESET

[

*

1

PA,
PA,
PA,

2

14

3

3A

DO,
DO,
000

4V

4B

3V

3B

2V

2B
lB

lV

12

20

•

01,

lB

7

01,

16
,4

4

01,
Dl4

SEL

HDSP-

ST

8716/8724/
8732/8740
DISPLAY
PROCESSOR
CONTROLLER

4A

3A
5 2A
2 lA

74LS157

13 48

3V
2V

6 2B
3
lB
1 SEL

13

DATA VALID

74LS157

2A
lA

10 3B

PC4

DO,

4A

11

4

PAo

005
004

2'

37

Do

f-i-c os

RESET

22

'B
,6
PC,
iSlB)
PBo

0,
05

-=-

22

23

PB,
PB,
PB,

~
~

'5

74lS132

24

PB4

~

6

12

4V

12

•

10

•

7

4

lV

6

01 3

DI,
01,
01 0

rST
2.

11

PC,

tACK)

22K

10

PC,

(OBF)

r+

-Vee

.l:

20j..tF

~~
REQUES:

11

74lS00 2

~

13t--

74LS132

5

131

11

l> B,
B,
A,
l>A,
CL



~
g

§
~

46

I

40

ia:i
a:

G

30

~

25

!!!!
I

~

2o
5

oc

r'V

ACI~:~:U

t1

5
0

The hysteresis of the device is given in voltage terms as
VHyS = VTH + - VTH _, or in terms of current as IHyS =
ITH+ - ITH _· The optocoupler output is in the high state
until the input voltage (current) exceeds VTH+(lTH+)' The
output state will return high when the input voltage
(current) becomes less than VTH-(lTH-)'
As is shown in Figure 3, the HCPL-3700 has preprogrammed ac and dc switching threshold levels. Higher input
switching thresholds may be programmed through the use
of a single series input resistance as defined in Equation (1).
In some cases, it may be desirable to split this resistance in
half to achieve transient protection on each input lead and
reduce the power dissipation requirement of each of the
resistors.

2

3

4

+-

r-

Figure 4 illustrates three typical interface situations which a
designer may encounter in utilizing a microprocessor as a
controller in industrial environments.

±::::t:I

~
1

OPEN~

I

6

6

7

8

9 10 11 12 13

Y,N -INPUT VOLTAGE -v

Figure 2.

Ty~ical Input Characteristics, liN

Example 1.
¥S.

- -

The transfer characteristic displayed in Figure 3 shows how
the output voltage varies with input voltage, or current,
levels. Hysteresis is provided to enhance noise immunity, as
well as to maintain a fast transition response (tr, 1) for
slowly changing input signals.

t f t N I f- TI I
t- DC (PINS 2, ~.;:::: ~
PINS1,4--c

0

1

The ac input appears similar to the dc input except that the
circuit has two additional diode forward voltages. The ac
input voltage will clamp at 6.7V (one Zener diode voltage
plus one forward biased diode voltage), and is symmetric
for plus or minus polarity. The ac voltage clamp level can
not be changed with different possible dc pin connections.

r-

-

OR
PINS 1,4

to the device during large voltage or current transients in
the industrial control environment. The internal limiting
will in some cases eliminate the need for additional protection components.

I

CONNECTED
TOGETHER;
PINS 3,4
CONNECTED
TOGETHER

PINS 2, 3

Figure 3. Typical Transfer Characteristics of the HCPL-3700

!
J.

35

PINS 2, 3
PINS 1,4

1.3mA

2

r- VOL

50

50

TH_

2.6'ii
3.8V
I

VOH

0

The dc input of the HCPL·3700 appears as a 10000 resistor
in series with a one volt offset. If the ac pins (1,4) are left
unconnected, the dc input voltage can increase to 12V (two
Zener diode voltages) before the onset of input voltage
clamping occurs. If the ac pins (1, 4) are connected to
ground or to dc pins (2, 3) respectively, the dc input
voltage will clamp at 6.0V (one Zener diode voltage). Under
clamping conditions, it is important that the maximum
input current limits not be exceeded. Also, to prevent ex·
cessive current flow in a substrate diode, the dc input can
not be backbiased more than -0.5V. The choice of the
input voltage clamp level is determined by the requirements
of the system design. The advantages of clamping the input
at a low voltage level is in limiting the magnitude of for·
ward current to the LED as well as limiting the input power

1

l00~A

I

The function of the HCPL·3700 can best be understood
through a review of the input VII function and the input to
output transfer function. Figure 2 shows the input char·
acteristics, liN (mA) versus VIN (volts), for both the ac and
dc cases.

TAI.J·C

4.5V
4.2mA
0.4V
2.4V

TH+
4-.
3.8ii
VTH IDC)
-VrH lAC)
5.W
3 t--I ITH IACIDCI 2.5mA

!;

Device Characteristics

55

t--IOH

I

w

The HCPL·3700 meets the requirements of the industrial
control environment for interfacing signals from ac or dc
power equipment to logic control electronics. Isolated
monitoring of relay contact closure or relay coil voltages,
monitoring of limit or proximity switch operation or sensor
signals for temperature or pressure, etc., can be accom·
plished by the HCPL·3700. The HCPL·3700 may also be
used for sensing low power line voltage (Brown Out) or loss
of line power (Black Out).

r

t-- vee
IOL
5r- VOL
VOH

V,N

451

A dc voltage applied to the motor is moni·
tored .as an indication of proper speed andl
or load condition.

1----.----0

MPU

HCPL·3700

HCPL·3700

115VAC
OR

CONTROL UNIT

I--+-~-O 220VAC

HCPL-3700

HCPL·3700

AC LINE
MONITOR

THERMOCOUPLE

Figure 4. Applications of the HCPL-3700 for Interfacing AC and DC Voltages to a Microprocessor
Example 2.

A limit switch uses a 115V ac or 220V ac
control loop to improve noise immunity
and because it is a convenient high voltage
for that purpose.

Example 3.

An HCPL-3700 is used to monitor a computer power line to sense a loss of line power
condition. Use of a resistive shunt for improvement of threshold accuracy is analyzed
in this example.

235.Q

v(

V ,N

\

MPU

235n
5%

Also illustrated is an application in which two HCPL-3700's
are used to monitor a window of safe operating temperatures for some process parameters. This example also
requires a rather precise control of the optocoupler
switching threshold. An additional dedicated leased line
system example is also shown (Example 4).
Example 1.

5%

Rx/2

Figure 5. Interfaeing a DC Voltage to an MPU using the
HCPL-3700
NOTE: See Appendix for a definition of terms and
symbols for this and all other examples.

DC Voltage Sensing

The following conditions are given for the external voltage
threshold level and input requirements of the HCPL-3700:

The de motor monitor function is established to provide an
indication that the motor is operating at a minimum desired
speed prior to the initiation of another process phase. If the
applied voltage, VM , is greater than 5V, it is assumed that
the desired speed is obtained. The maximum applied
voltage in the system is 10V. The HCPL-3700 circuit
configuration for this de application is shown in Figure 5.

External Voltage Levels - V M
5V de (50%)

V peak

452

10V de

HCPL·3700 Input Levels

V+

VTH +

V peak

V IHC

--<-VTH +

3.8V

V TH _

2.SV

V ICH3

12V

ITH+

2.5mA

ITH_

1.3mA

where V IHC is the particular input clamp voltage listed on
the data sheet.
For this de application with ac pins (1, 4) open, input
voltage clamping will not occur, i.e.,

(1)

= 480n

V TH +

V peak

V IHC3

5V

3.8V

10V

12.0V

->--

5V - 3.8V
2.5mA
Rx

V+

-->--

For the 5V threshold, Rx is calculated via the expression:

Rx '=

(4)

(V IN will clamp)

Consequently, a conservative value for the maximum power
dissipation in Rx for the unclamped input voltage condition
ignoring the input offset voltage is given by:
(470n ± 5%)

The resultant lower threshold level is formed by using the
following expression:
(Unclamped Input)

(2)

(5)

(1.3mA) 470n + 2.S0V
f,OV( 470n ~2
1470nll

V_ = 3.21V

l

L

With the possible unit to unit variations in the input
threshold levels as well as ±5% tolerance variations with Rx '
the variation of V+ is +12.4%, -15% and V_varies +14%,
-23.5%. (NOTE: With a low, external, voltage threshold
level, V+, which is comparable in magnitude to the VTH +
voltage threshold level of the optocoupler (V +..;; 10VTH +)
the tolerance variations are not significantly improved by
the use of a 1% precision resistor for Rx' However, at a
large external voltage threshold level compared to VTH +
(V + > 10VTH +), the use of a precision 1% resistor for Rx
does reduce the variation of V+.)

470n
PR x = 21.8mW
If V+lVpeak < VTH+IVIHC was true (clamped .input
voltage condition), then the formula for the maximum
power dissipation in Rx becomes:

(Clamped Input)

For simultaneous selection of external upper, V+, and
lower, V _, voltage threshold points a combination of a
series and parallel input resistors can be used. Refer to the
example on "ac operation with improved threshold control
and accuracy" for detailed information.

The maximum input current or power must be determined
to ensure that it is within the maximum input rating of the
HCPL·3700. For the clamped input voltage condition,

(7)

Calculation of the maximum power dissipation in Rx is
determined by knowing which of the following inequalities
is true:
V+

V TH +

V peak

V IHC

-->--

IV IN will not clamp)

(S)

or

(3)

Clamped
Condition
(8)

453

>

Vee

,(

lB.7k
1%

w

~

Rxl2

300

I

'"....-'

250

c

200

'

V

J
IJ'

40

BO

120

160

200

240

Rx - EXTERNAL SERIES RESISTOR - kG

For the unclamped input voltage condition, the maximum
input current, or power will not be exceeded, because
maximum input current and power will occur only under
clamp conditions.

Figure 7. Typical External Threshold Characteristic, V± vs. Rx
98V -5.1V

An output load resistance is not needed in this application
because the peripheral interface adapter, such as MC6821,
has an internal pullup resistor connected to its input.
Example 2.

2.5mA
37.2kn

(use Rx/2 = 18.7kn, 1% resistor
for each input lead)

AC Operation
The resulting lower threshold point is

As shown in Figure 6, an ac application is that of a moni·
tored 115V ac limit switch. Ac sensing is commonly used
and the HCPL·3700 conveniently provides an internal
rectification circuit. With the HCPL·3700 interfacing to the
P.I.A., a choice can be made not to filter the ac signal or to
filter the ac signal at the input or output of the device. All
three conditions will be explored. Simplicity is obtained
with no filtering at all, but software detection techniques
must be used. Output filtering is a standard method, but
may present problams with slow RC rise time of the output
waveform when TTL logic is used. Input filtering avoids the
RC rise time problem of output filtering, but introduces an
extra time delay at the input.

(10)

ITH_Rx +VTH _

= (1.3mA)(37.4kn) + 3.8V
V_

.. 52.4V

(32% of peak input voltage)

Figure 7 provides a convenient, graphical choice for the ex·
ternal series resistor, Rx ' and a particular external threshold
voltage V±.
The corresponding Rx value and output waveform of the"\..
HCPL·3700 for a V+ = 98V (60% of peak) is shown in
Figure 8.

AC Operation With No Filtering
in this example, a V+ value of·98V is selected based on a
criteria of 60% of Vpeak' Monitoring a limit switch for a
60% level of the signal will give sufficient noise immunity
from an open 115V ac line while allowing the HCPL·3700
to turn on under low line voltage conditions of -15% from
npminal values when the limit switch is closed.

_ _ _ V ak = 163V

_ ,_\ _ v: .
- r; _'-I V_·

9BV 160%1
52V 132%1

OV

OUTPUT
HCPL-3700

The value of Rx for the upper threshold detection level
without the filter capacitor, C, across the de input, can be
obtained from the following expression.

VOHllJUlJULrvee
VOL

-

~.85ml
B.33ms

VTH + .. 5.1V
(ac instantaneous)
ITH+ - 2.5mA

OV

b

(9)
Figure 8. Output Waveforms of the HCPL·3700 Design in
Figure 7 with no Filtering Applied
454

rI

--V\lI,.------i'

OFF STP.TE TIME

__-;;;:c----

AC

V peak

I

T!2

Figure 10. Input Filtering with the HCPL-3700
The application of ac input filtering is illustrated in Figure
10 and is described in the following example. The ac input
conditions are the same as in the previous example of the
115V ac limit switch.

Figure 9. Determination of Off/On State Time
To determine the time in the high state, refer to Figure 9
and Equation (11).

The minimum value of capacitance C to ensure proper ac
filtering is determined by the parameters of the optocoupler. At low ac input voltage, the capacitor must charge
to at least VTH + in order to turn on, but must not discharge to VTH - during the discharge cycle. A conservative
estimate for the minimum value of C is given by the following equations.

Due to symmetry of sinusoidal waveform, the high state
time is t_ + t+ where t± is given by;

(11 )

V TH + - V TH _ = VTH+e -t/r,

where arc sine is in degrees and T = period of sinusoidal
waveform.

[

- RIN Cmin

T -

(12)

where R I N is the equivalent input resistance of the HCPL3700.

In the unfiltered condition, the output waveform of Figure
8 must be used as sensed information. Software can be
created in which the microprocessor will examine the waveform from the optocoupler at specific intervals to deter·
mine if ac is present or absent at the input to the HCPL3700. This technique eliminates the problem of filtering,
and accompanying delays, but requires more sohpisticated
software implementation in the microprocessor.

(13)

with RIN = lkn, VTH + = 3.8V, VTH_ = 2.6V and t =
8.33ms for 60 Hz or t = 10ms for 50 Hz.

Input Filtering for AC Operation
A convenient method by which to achieve a continuous
output low state in the presence of the applied ac signal is
to filter the input dc terminals (pins 2-3) with a capacitance C while the ac signal is applied to the ac input (pins
1-4) of the full wave rectifier bridge. Input filtering allows
flexibility in using the HCPL-3700 output for direct interfacing with TTL or CMOS devices without the slow rise
time which would be encountered with output filtering. In
addition, the input filter capacitor provides extra transient
and contact bounce filtering. Because filtering is done after
Rx ' the capacitor working voltage is limited by the V 1HC2
clamp voltage rating which is 6.7V peak for ac operation.
The disadvantage of input filtering is that this technique
introduces time delays at turn on and turn off of the optocoupler due to initial charge/discharge of the input filter
capacitor.

Cmin

7.23/lF for 60 Hz

Cmin

8.68/lF for 50 Hz

To ensure proper filtering, the recommended value of C
should be large enough such that with the tolerance variation, C will always be greater than Cmin (C should otherwise be kept as small as possible to minimize the inherent
delay times which are encountered with this technique).
Since the filter capacitor affects the input impedance, a
slightly different value of Rx is required for the input
filtered condition. Figure 11 shows the Rx versus V±
threshold voltage for C = 10/lF, 22/lF, and 47/lF. For an
application of monitoring a 115V RMS line for 65% of
nominal voltage condition (75V RMSl, an Rx = 26.7kn ±
1% with C = 10/lF will yield the desired threshold. The
power dissipation for Rx is determined from the clamped

455

selection with 115V line application would be to determine
Rx for a lower threshold level of 50% of nominal peak
input voltage, only to find that the upper threshold level is
90% of peak input voltage. With the possible ac line voltage
variations (+10%, -15%), it would be possible that the
optocoupler could never reach the upper threshold point
with an ac line that is at -15% of nominal value. To give
the designer more control over both threshold points, a
combination of series resistance, Rx ' and parallel resistance,
Rp ' may be used, as shown in Figure 12.

I>

,

w

'>-"
"g
9
o

~0:

l:

>-

-'

"z~

Two equations can be written for the two external thresh·
old level conditions. At the upper threshold point,

>-

~

,

';'
Rx - EXTERNAL RESISTOR -

kn

(14)

Figure 11. External Threshold Voltage versus Rx for
Applications Using an Input Filter Capacitor C (Figure 10)

and at the lower threshold point,

condition (V+/V peak < VTH+/V ICH2) and is 455mW (see
Figure 6) which suggests Rx/2 of 1/2 watt resistors for each
input lead.
Example 3.

(15)

Solving these equations for Rx and Rp yield the following
expressions:

AC Operation with Improved Threshold
Control and Accuracy

Some applications may occur which require threshold level
detection at specific upper and lower threshold points. The
ability to independently set the upper and lower threshold
levels will provide the designer with more flexibility to
meet special design criteria. As illustrated in Figure 12, a
computer power line is monitored for a power failure con·
dition in order to prevent loss of memory information
during power line failure.

(17)

Equations (16) and (17) are valid only if the conditions of
Equations (18) or (19) are met. The desired external voltage threshold levels, V+ and V_, are established and the
values for VTH ± and ITH ± are found from the data sheet."
With the VTH ±, ITH± values, the denominator of Rx ' '
Equation (16) is checked to see of it is positive or negative.
If it is positive, then the following ratios must be met:

In this design, the HCPL·3700 optocoupler monitors the
computer power line and the output of the optocoupler is
interfaced to a TTL Schmitt trigger gate (7414).
In the earlier ac application of the HCPL·3700 (limit switch
example), a single external series resistor, Rx ' was used to
determine one of the threshold levels. The other threshold
level was determined by the hysteresis of the device, and
not the designer. A potential problem of single threshold

Conversely, if the denominator of Rx Equation (16) is
negative, then the following ratios must hold:

"N

Rx/2

Rp

vI

(18)

,,(

2 DC+
HCPl-3700

(19)

Rx/2

Consider that the computer power line is monitored for a
50% line drop condition and a 75% Iine presence condition.
The 115V 60 Hz ac line (163V peak) can vary from 85%
(139V) to 110% (179V) of nominal value.

Figure 12. An AC Power Line Monitor with Simultaneous
Selection of Upper and Lower Threshold Levels and Out·
put Filtering

456

f

Require:
V_

81.5V

(50%)

Turn off threshold

V+

122.5V

(75%)

Turn on threshold

(22)

Output Filtering

Given:
VTH +=5.1V

ITH+= 2.5mA

VTH _ =3.8V

ITH_ =1.3mA

The advantages of filtering at the output of the HCPL·3700
are that it is a simple method to implement. The output
waveform introduces only one additional delay time at turn
off condition as opposed to the input filtering method
which introduces additional delay times at both the turn on
and turn off conditions due to initial charge or discharge of
the input filter capacitor. The disadvantage of output filtering is that the long transition time, t r , which is introduced by the output RC filter requires a Schmitt trigger
logic gate to buffer the output filter circuit from the sub·
sequent logic circuits to prevent logic chatter problems. The
determination of load resistance and capacitance is illus·
trated in the following text.

Using the Equations (16, 17) for R , Rp with the condi·
tions of Equations (18, 19) being metXyields

=17.4 kn

use 18 kn

5%

Rp = 1.2 kn

use 1.2 kn

5%

Rx

To complete the input calculations for maximum input
current, liN' to the device and maximum power dissipation
in Rx and Rp , a check must be made. to determine if the
input voltage will clamp at peak applied voltage. Using
Equations (3) and (4) to determine if a clamp or no clamp
exists, it is found that the ratios

0.75

V+

V TH +

V peak

V IHC2

The following given values specify the interface conditions.
HCPL·3700

=- - "" - - = 0.76

indicate that V IN slightly entered clamp condition. In this
application, the operating input current, liN' is given approximately by
V IHC2
VliN

L

Vi
Rx

6.7V

115V -

Vi

18 kn
liN

.. 2.18mA RMS

VOL

= O.4V

IOL

= 4.2mA

IOH

= 100ILA max

VCC

= 5.0V ± 5%

V IHC2

v'2
--<
Rp

VT+ (min)
liN (max)

= 1.5V

}

(20)
VT+ (max) = 2.0V
IIH

40llA max

III

-1.2mA max

Schmitt trigger upper
threshold level

6.7V

v'2
--1.2 kn

With the current convention shown in Figure 12, the mini·
mum value of RL which ensures that the output transistor
remains in saturation is:

< 34.3mA

Power dissipation in Rx is determined from the following
equation,

RL (min)

~

O.:.
L
_..:,C..:,C....:.(m:.:..:.::ax.:,:)_-_V--:.
V

5.25V -O.4V
(21)

(23)

IOL + IlL

4.2mA - 1.2mA

1.62 kn

The maximum value for RL is calculated allowing for a
guardband of O.4V in VT+ (max) parameter, or V IH =
VT+ (max) + O.4V.

which yields o.6i5W. With the clamp condition existing,
the maximum power dissipation for Rp is 18.7mW which is
determined from

457

(27)

r
/WITHOUTC l

rl
(LlVOL )

VTtmio_ - - :

MAXIMUM RIPPLE - - - - ' - -

AMPLITUDE

VOL -

r--------

rl

rl

: - - : : - - : :_ _

--

--1 I~
r:-::--I

I

--

'~
~

4.58 ms

WITH CL

and substituting previous parameter values and using
VOH =VCC - (lOH + IIH) RL results in

8.33 ms

4.58ms

Figure 13. Output Waveforms of the HCPL·3700
In

(

4.8V - O.4V )
4.8V _ O.4V _ 0.6V

(24)
r
4.75V - 2.4V
0.1 mA + 0.04mA

31.24ms

C L can be calculated directly,

16.8 kn

(28)

R L is chosen to be 1650n.
C L can be determined in the following fashion. As illus·
trated in Figure 8, the output of the optocoupler will be in
the high state for a specific amount of time dependent
upon the selected V+ levels. In this example, V+ = 122.5V
(75%) and V_ = 81.5V (50%) and allowing for a minimum
peak line voltage of 138V (-15%), the high state time
(without C L) is from Equation (11 I, 4.58ms. With the
appropriate C L value, the output waveform (solid line)
shown in Figure 13 is filtered.

31.24ms
1.29 kn
24.2MF

use 27MF ± 10%
or 33MF ± 20%

With this value of C L, the time the R' LC L filter network
takes to reach VT+ of the TTL gate is found as follows.
(29)

The maximum ripple amplitude above VOL is chosen to be
0.6V; that is, VOL + AV OL = 1.0V. This gives a 0.5V noise
margin before VT+ (minI = 1.5V is reached. The exponen'
tial ripple waveform is caused by the C L being charged
through RL and input resistance, RINTTL' of TTL gate. An
expression for the allowable change in VOL can be written:

Solving for t,

(30)

(25)
and substituting VOH = 4.8V, VOL = O.4V, VT+ (min) =
1.5V, and r = 31.24ms yields

where r = R' LC L with R'L equal to parallel combination of
RL and RINTTL'

9.0ms
Below VT+ = 1.5V (min). RINTTL is constant and nom·
inally 6 kn. Hence:

R' L

This is the delay time that the system takes to respond to
the ac line voltage going below the 50% (V ) threshold
level. In essence, the response time is slightly more than a
half cycle (8.33msl of 60 Hz ac line with worst case line
variation taken into account. This delay time is acceptable
for system power line protection. In this example, a com·
plete worst case analysis was not performed. A worst case
analysis should be done to ensure proper function of the
circuit over variations in line voltage, unit to unit device
parameter variations, component tolerances and tempera·
ture.

(26)

(1.65 kn) (6 kn)
1.65 kn + 6 kn

Solving Equation (25) for r yields

458

Threshold Accuracy Improvement

Solving for Ip+ yields

In the above example on output filtering, the two external
threshold levels were selected for turn on conditions at
V+ = 122.5V (75%) and turn off at V_ = 81.5V (50%). The
calculated external resistor values were Rx = 17.4 kn and
Rp = 1.2 kn. Using standard 5% resistors of 18 kn and
1.2 kn respectively, the upper threshold voltage was
actually 126.6V nominal.

Ip+

= 11.2mA,

and

(33)

Examination of the worst possible combination of varia·
tions of the HCPL·3700 optocoupler VTH +, ITH +, levels
from unit to unit, and the ± 5% variations of Rx and Rp
can result in the V+ level changing +23% to -25% from
design nominal.

11.2mA
(use 453n, 1% resistor)
This new value of Rp replaces the earlier Rp = 1.2 kn, and
the circuit requires a new Rx value to maintain the same V+
threshold level.

If higher threshold accuracy is desired, it can be accomplished by. decreasing the value of Rp in order to allow Rp
to dominate the input resistance variations of the optocoupler. Using a 1% resistor for Rp and resistance of suf·
ficiently small magnitude, the V+ tolerance variations can
be significantly improved. The following analysis will allow
the designer to obtain nearly optimum threshold accuracy
from unit to unit. It should be noted that the HCPL-3700
demonstrates excellent threshold repeatability once the
external resistors are adjusted for a particular level and unit.
The compromise which is made for the added control on
threshold accuracy is that more input power must be con·
sumed within the Rp , Rx resistors.

11.2mA + 2.5mA
122.5V - 5.1V
13.7mA
8.57 kn

With the possible variation of ± 1% in Rp and Rx ' as well as
unit to unit variations in the optocoupler VTH +, ITH+ the
upper threshold level V+ will vary significantly less than in
the 5% resistor design case. The variations in V+' which is
given by V+ = Rx 1+ + VTH +, where 1+ = Ip+ + ITH +, are
compared in Table 1.

In Figure 14, assume the circuit is at the upper threshold
point. At constant VTH +, it is desired to maintain 1+ to
within ± 5% variation of nominal value while allowing ± 1%
variation in Ip+' With this requirement, Equations (31) and
(32) can be written and solved for the magnitude of Ip+
which is needed to maintain the desired condition on 1+. 1+
is the sum of Ip+ and ITH +.
1.051+ = 1.01 Ip+ + ITH+ (max)}

Table 1 illustrates the possible improvements in V+ tolerance as Rx and Rp are adjusted to limit the variation of the
external input threshold current, 1+, to the resistor network
and optocoupler. This table is centered at a nominal external input threshold voltage of V+ = 122.5V. It is the
designer's compromise to keep power consumption low,
but threshold accuracy high.

(31)
at constant V TH +

0.99 Ip+ + ITH+ (min)

(use 8.66 kn, 1% resistor)

(32)

where

NOTE:

ITH+ (max) = 3.11mA
ITH+ (min) = 1.96mA

The above method for selection of Rp and Rx
can be adapted for applications where larger
sense currents (wet sensing) may be appropriate.

Example 4. Dedicated Lines for Remote Control
In situations involving a substantial separation between the
signal source and the receiving station, it may be desirable
to lease a dedicated private line metallic circuit (dc path)
for supervisory control of remote equipment. The HCPL3700 can provide the interface requirements of voltage
threshold detection and optical isolation from the metallic
line to the remote equipment. This greatly reduces the expense of using a sophisticated modem system over a convention telephone line.

HCPL-3700

Figure 14. Threshold Accuracy Improvement through the
Use of External Rx and Rp Resistors

459

Rx

T
0
L.

Rp

T
0
L.

18 kn

5%

1.2 kn

5%

8.66 kn

1%

453n

1%

4.32 kn

1%

205n

2.15 kn

1%

97.5n

1+ TOLERANCE

+17.5%

MAXIMUM TOTAL
POWER IN
Rx + Rp (RMS)

V+ TOLERANCE

+ 23%

-

25%

0.69W

±5%

+12.7%

-19.3%

1.45 W

1%

±3%

+11.2%

-18.9%

2.92W

1%

±2%

+10.6%

-18.8%

5.89W

-21.2%

Table 1. Comparison of the V + Threshold Accuracy Improvement versus Rx and Rp and Power Dissipation for a Nominal
V+ = 122.5 V
In this application, a 48V dc floating power source supplies
the signal for the metallic line. The HCPL-3700 upper
voltage threshold level is set for V+ = 36V (75%). Consequently, Rx is

Figure 15 represents the application of the HCPL-3700 for
a line which is to control tank levels in a water district.
Some comments are needed about dedicated metallic lines_
The use of a private metallic line places restrictions upon
the designer's signal levels. The line in this example would
be used in the interrupted dc mode (duration of each interruption greater than one second), the maximum allowed
voltage between any conductor and ground is .;; 135 volts.
Maximum current should be limited to 150mA if the cable
has compensating inductive coils in it. Balanced operation
of the line is strongly recommended to reduce possible
cross talk interference as well as to allow larger signal
magnitudes to be used. Precaution also should be taken to
protect the line and equipment. The line needs to be fused
to ensure against equipment failure causing excessive current to flow through telephone company equipment. In
addition, protection from damaging transients must be
taken via spark gap arrestors and commercial transient
suppressors. Details of private line metallic circuits can be
founded in the American Telephone and Telegraph
Company publication 43401.

RESERVOIR
CONDITION

V+-VTH+
(35)
ITH+
36V -3.8V
2.5mA
(use Rx/2 = 6.49 kn, 1%
resistor in each input levell

12.9 kn

The resulting lower voltage threshold level is
(36)
13 kn (1.3mA) + 2.6V
19.5V

=:J

SWITCH
CONDITION

FULL

OPEN

LOW

CLOSED

15VAC

.WATER

PUMP

--o-f

r---------<'~----,>-- Vee
R~~_R

~.

FLOAT SWITCH

1------'

~~~

48VDC

-=-

BALANCED
SUPPLY

D1, 02 == lN5658A
FLOAT SWITCH AND WATER PUMP ARE REMOTELY LOCATED WITH RESPECT TO EACH OTHER.

Figure 15_ Application of the HCPL-3700 to Private Metallic Telephone Circuits for Remote Control
460

yielding VHYS = 16.5V. The average induced ac voltage
from adjacent power lines is usually less than 10 volts (reference ATT publication 43401) which would not falsely
turn on, or off, the HCPL-3700, but could affect conventional optocouplers.

input surge current is 140mA for 3ms at 120 Hz pulse
repetition rate, and the maximum input transient current is
500mA for 10J,ls at 120 Hz pulse repetition rate. The use of
an external series resistor, Rx ' provides current limiting to
the device when a large voltage transient is present. The
amplitude of the acceptable voltage transient is directly
proportional to the value of Rx'

Under normal operation (full reservoir). the optocoupler is
off. When the float switch is closed (low reservoir), the
optocoupler output (VOL) needs inversion, via a transistor,
to drive the power Darlington transistor which controls a
motor starting relay. The relay applies ac power to the
system water pump. With VCC = 10V, IB2 = 0.5mA, IBl =
0.5mA.

However, in order to protect the HCPL-3700 when the
input voltage to the device is clamped, the maximum input
current must not be exceeded. An external means by which
to enhance transient protection can be seen in Figure 16.
A transient RxCp filter can be formed with Cp chosen by
the designer to provide a sufficiently low break point for
the low pass filter to reduce high frequency transients.
However, the break point must not be so low as to attenuate the signal frequency. Consider the previous ac application where no filtering was used. In that application, Rx =
37.4 kn, and if the bandwidth of the transient filter needs
to be 600 Hz, then Cp is:

VCC - 2V BE
(37)
IB2
10V -1.4V
0.5mA
17.2 kn
18kn)

Cp

(39)

VCC-VBE
(38)
10V - 0.7V

Should additional protection be needed, a very effective
external transient suppression technique is to use a commercial transient suppressor, such as a Transzorb ® ,or
metal oxide varistor, MOV ® ,at the input to the resistor
network prior to the optocoupler. The Transzorb ® will
provide extremely fast transient response, clamp the input
voltage to a definite level, and absorb the transient energy.
Selection of a Transzorb ® is made by ensuring that the
reverse stand off voltage is greater than the continuous
peak operating voltage level. Transzorbs ® can be stacked
in series or parallel for higher peak power ratings. Depending upon the designer's potential transient problems, a
solution may warrent the expense of a commercial suppression device.

O.SmA
RL
(R L

(use 0.0068J,1F capacitor @ SOV dc)

0.0071J,1F

IB1

18.6 kn

= 18kn)

For this application, the ac inputs could also be used, which
would remove any concern about the polarity of the input
signal.
General Protection Considerations for the HCPL-3700
The HCPL-3700 optocoupler combines a unique function
of threshold level detection and optical isolation for interfacing sensed signals from electrically noisy, and potentially
harmful, environments. Protection from transients which
could damage the threshold detection circuit and LED is
provided internally by the Zener diode bridge rectifier and
an external series resistor. By examination of Figure 1, it is
seen that an input ac voltage clamp condition will occur at
a maximum of a Zener diode voltage plus a forward biased
diode voltage.

Thermal Considerations
Thermal considerations which should be observed w!th the
HCPL-3700 are few. The plastic 8 pin DIP package is
designed to be operated over a temperature range of - 2SoC
to 85°C. The absolute maximum ratings are established for

Rx/2

At clamp condition, the bridge diodes limit the applied
input voltage at the device and shunt excess input current
which could damage the threshold detection circuit or
cause excessive stress to the LE D.

(v

cp

HCPl-3700

Rx/2

The HCPL-3700 optocoupler can tolerate significant inpl,lt
current transient conditions. The maximum dc input
current into or out of any lead is 50mA. The maximum

Figure 16. RxCp Transient Filter for the HCPL-3700
461

a 70°C ambient temperature requiring slight derating to
85°C. In general, if operation of the HCPL·3700 is at
ambient temperature of 70°C or less, no heat sinking is required. However, for operation between 70°C and 85°C
ambient temperature, the maximum ratings should be derated per the data sheet specifications.

through air (bare wire). These separations are between any
uninsulated live part and un insulated live part of opposite
polarity, or un insulated ground part other than the enclosure or an exposed metal part.
An uncontrolled environment is an environment which has
contaminants, chemical vapors, particulates or any substances which would cause corrosion, decrease resistance
between PC board traces or, in general, be an unhealthy
environment to human beings.

Mechanical and Safety Considerations
Mechanical Mounting Considerations
The HCPL-3700 optocoupler is a standard 8 pin dual-inline plastic package designed to interface ac or dc power
systems to logic systems. This optocoupler can be mounted
directly onto a printed circuit board by wave soldering.

For 0 - 50 volts RMS, the spacing is 1.6mm (0.063 inches)
through air or over surfaces.
Electrical Connectors
The HCPL-3700 provides the needed isolation between a
power signal environment and a control logic system. However, there exists a physical requirement to actually interconnect these two environments. This interconnection can
be accomplished with barrier strips, edge card connectors,
and PCB socket connectors which provide the electrical
cable/field wire connection to the I/O logic system. These
connectors provide for easy removal of the PC board for
repair or substitution of boards in the I/O housing and are
needed to satisfy the safety agency (U.L., V.D.E., I.E.C.)
requirements for spacing and insulation. Connectors are
readily available from many commercial manufacturers,
such as Connection Inc., Buchanan, etc. The style of connector to choose is dependent upon the application for
which the PC board is used. If possible it is wise to choose a
style which does not mount to the PC board. This would
enable the PC card to be removed without having to disconnect field wires. The use of connectors which are called
"gas tight connectors" provide for good electrical and
mechanical reliability by reducing corrosion effects over
time.

Electrical Safety Considerations
Special considerations must be given for printed circuit
board lead spacing for different safety agency requirements.
Various standards exist with safety agencies (U.L., V.D.E.,
I.E.C., etc.) and should be checked prior to PC board layout. The HCPL-3700 optocoupler component is recognized
under the Component Program of Underwriters
Laboratories, Inc. in file number E55361. This file qualifies
the component to specific electrical tests to 220V ac
operation.
The spacing required for the PC board leads depends upon
the potential difference that would be observed on the
board. Some standards that could pertain to equipment
which would use the HCPL-3700 are UL1244, Electrical
and Electronic Measuring and Testing Equipment, U L1092,
Process Control Equipment, and IEC348, Electronic
Measuring Apparatus. Spacing for the worst case in an uncontrolled environment with a 2000 volt-amperes maximum supplying source rating must be 3.2mm (0.125
inches) for 51 - 250 volts RMS potential difference over a
surface (creepage distance), and 3mm (0.118 inches)

462

APPENDIX I.

List of Parameters

v
- Externally Applied Voltage
- External Upper Threshold Voltage Level
V+
V
- External Lower Threshold Voltage Level
Device* Input Voltage Clamp Level; Low
- VIHC1
Voltage DC Case
Low Voltage AC Case
V IHC2
High Voltage DC Case
VIHC3
Device Input Current
liN
Device Input Voltage
V IN
Device Upper Voltage Threshold Level
VTH +
Device Lower Voltage Threshold Level
VTH_
Device Upper Input Current Threshold Level
ITH+
Device Lower Input Current Threshold Level
ITHExternal Series Resistor for Selection of
Rx
External Threshold Level
External Parallel Resistor for Simultaneous
Rp
Selection/Accuracy Improvement of External
Threshold Voltage Levels
Total Input Current at Upper Threshold Level
1+
to External Resistor Network (R x' Rp) and
Device
Current in Rp at Upper Threshold Levels
Ip+
Peak Externally Applied Voltage
Vpeak
Output Voltage of Device
Vo

VOL
VOH
10H
10L
IIH
IlL
VCC
RIN
VT+

= Output Low Voltage of Device
= Output High Voltage of Device
= Output High Leakage Current of Device
= Output Low Sinking Current of Device
= Input High Current of Driven Gate
= Input Low current of Driven Gate
= Positive Supply Voltage
Input Resistance of HCPL·3700

== Schmitt Trigger Upper Threshold Voltage of
TTL Gate (7414)

{

463

RL
CL
C
TH+
TH
PR x
PIN
PA
t+
tT
Cp

= Output Pullup Resistance
= Output Filter Capacitance

*Device

= HCPL·3700

Input Filter Capacitor
Upper Threshold Level
Lower Threshold Level
Power Dissipation in Rx
Power Dissipation in HCPL·3700 Input IC
Input Signal Port to P.I.A.
Turn On Time
Turn Off Time
Period of Waveform
Similar to Rp

rh~

~~

HEWLETT
PACKARD

APPLICATION NOTE 1005

Operational Considerations. for
LED Lamps and Display Devices
The data sheet also provides an equation to calculate the
expected maximum forward voltage at a given current.

In the design of a display system, which incorporates LED
lamps and display devices, the objective is to achieve an
optimum between light output, power dissipation, reliability, and operating life. The performance characteristics and capabilities of each LED device must be known
and understood so that an optimum design can be
achieved. The primary source for this information is the
LED device data sheet.

Design Criteria
This application note assumes that the objective of a
specific design is to achieve a maximum light output from
a display that is operated in an elevated ambient temperature. The two crrteria that establish the operating limits
are the maximum drive current and the maximum LED
junction temperature. The maximum drive current has
been established to ensure a long operating life and the
maximum LED junction temperature is governed by the
device package. The data sheet will list the maximum
allowed drive currents for a specific device. The absolute
maximum allowed LED junction temperature (TJ MAX)
differs for the various device package configurations. For
most plastic display devices, TJ MAX = 100°C; for most
plastic lamps, TJ MAX = 110° C; and for alphanumeric PC
board monolithic displays, TJ MAX = 110° C (for some PC
board monolithic displays, TJ MAX = BOO C).

The data sheet typically contains Electrical/Optical Characteristics that list the performance of the device and
Absolute Maximum Ratings in conjunction with characteristic curves and other data which describe the
capabilities of the device. A thorough understanding of
this information and its intended use provides the basis for
achieving an optimum design.
This application note presents an in-depth discussion of
the theory and use of the electrical and optical information
contained within a data sheet. Two designs using this
information in the form of numerical examples are presented, one for dc operation and one for pulsed (strobed)
operation. The calculated results for each example are
underlined and accented by an arrow (-) for each
identification. Specific information on operation without
derating and the soldering of plastic LED devices is also
presented.

Thermal Resistance
The LED junction temperature is the sum of the ambient
temperature (TA) and the temperature rise above ambient
(L':. T J), which is the product of the power dissipated within
the junction (PD) times the thermal resistance LED
junction-to-ambient (ROJA ).

Typical Data Sheet Information
A data sheet typically contains Absolute Maximum Ratings, Electrical/Optical Characteristics, and typical operating graphs. The Absolute Maximum Ratings list such
items as the maximum allowed forward currents, power
dissipation, and operating ambient temperature range.
The Electrical/Optical Characteristics list such data as the
luminous intensity specification (Iv). forward voltage (V F ),
peak wavelength (APEAK), dominant wavelength (Ad), and
the device thermal resistance LED junction-to-pin on a per
LED element basis (ROJ_PIN )'

TJ (OC)
T J (0C)

1:
2:
3:
4:
5:

(1 )

The cathode pins of an LED device are the primary thermal
paths for heat dissipation from the LED junction into the
surrounding environment. The data sheet lists the thermal
resistance LED junction-to-pin (ROJ-PIN) for the device.
This device junction-to-pin thermal resistance is added to
the thermal resistance-to-ambient of the PC board
mounting assembly (ROPC _A) to obtain the overall value of
ROJA on a per LED element basis. (NOTE: For monolithic
displays, thermal resistance is calculated on a per digit
basis.)

The five graphs that are usually contained within a data
sheet are:
Figure
Figure
Figure
Figure
Figure

= TA + L':.TJ
= TA + PD ROJA

Pulsed Mode Operating Curves
Current Derating vs. Temperature
Relative Luminous Efficiency
Forward Voltage Characteristic
Light Output vs. DC Drive Current

ROJA = ROJ-PIN + ROPC-A
= ° C/W/LED Element

464

(2)

I
I

I

,

\

1:

~'l>~

..

I~

~

~~
:f~
1,-. .

\

\'
100

10

OPERATION IN
THIS REGION
REQUIRES
DERATING
OF IDe MAX.

~

\
1>

!

I

;1

250

1

~'I

:\
1000

10,000

DC OPERATI ON

tp - PULSE DURATION -115

Figure 1. Maximum Tolerable Peak Current vs. Pulse Duration



14

g

12

"X
"<
"x

10

a:

110,1' • 370"C/W1$
R'JA

",f\"" "
~\

GMENT .....

I

1-"\

IIoJA • 494'C/Wi$EGMENT"

~ 617"C/W~GMENT"'"

'I

iu

10

20

30

40

50

606570
0

60

50

...z

40

I

1.2

~

1.1

w

1.0

~;Itf

l/

1-

I

;

'.
,.
o

5 10 15 20 25 30 35 40 45 50 55/60 65
•
57.8

C

IpEAK - PEAK SEGMENT CURRENT - rnA

Figure 3. Relative Luminous Efficiency (Luminous Intensity
per Unit Current) vs. Peak Segment Current

I-

I!

a:
a:

::>

30

I

a:

~

1.3

~

',/

II"

If

l<

a:

~

o

808590

Figure 2. Maximum Allowable DC Current per Segment vs.
Ambient Temperature. Deratlngs Based on Maximum
Allowed Thermal Resistance Values, LED Junctlon-toAmbient on a per Segment Basis. T JMAX _100°C

0

1.4

.7

T. - AMBIENT TEMPERATURE _

CJ

1.5

c:;
u:

.8

o
o

w

1$

I

J I

.9

_0

E

>
~
w

a:

I

r-

!

1.61,·7

\

i\

CJ

::>

,

\.

17.5

iiia:

1.9
1.8

1\

e

20

-~

10

J

I

o

:;
o

l/
o

0.5

1.0

1.4

1.8

2.2

2.6

3.0

V F - FORWARD VOLTAGE - V

Figure 4. Forward Current

VB.

/"

o

V

/

V

10

/

/

15

L

20

IF - DC CURRENT PER LED - mA

Figure 5. Relative Luminous Intensity vs. DC Forward Current

Forward Voltage Charecteristlc

465

For reliable operation, it is recommended that the value of
Rllpc-A be designed low enough to ensure that the LED
junction temperature does not exceed the maximum
allowed value.

Light Output
The time averaged luminous intensity (Iv) at TA = 25°C for
a particular drive condition may be calculated using the
relative luminous intensity characteristic of Figure 5 fordc
operation or the relative efficiency characteristic (IJIPEAK)
of Figure 3 for pulsed operation. For dc operation, Iv (TA =
25° C) is equal to the product of the data sheet luminous
intensity specification times the relative factor for a
specific dc current from Figure 5.

Derating vs. Temperature
The derating vs. temperature, Figure 2, is derived from the
LED junction temperature rise above ambient as estabby the maximum allowed power dissipation (Po MAX)
which is derated linearly to zero power when TA = TJ MAX.
The values of RBJA shown on Figu re 2 are derived from the
quotient of t, TJ and Po MAX for a specified operating
temperature.
RJA (OC/W/LED) =
AT~

m

~OC=

(Iv DATA SHEET)(FACTOR FROM FIGURE 5)

(3)

TJ MAX - TA OPERATING

For pulsed operation, the time averaged luminous at TA =
25°C is calculated using the following equation:

Po MAX

Po MAX (W)

The value of Po MAX is the power dissipation within a
maximum forward voltage device when driven at the
maximum data ·sheet current. Thus, ROJA is determined on
the basis of worst case power dissipation.

(8)

Iv TIME AVG =

[IAVG

The derating curve with the largest ROJA value in Figure 2,
normally a derating from TA = 50°C, represents a mandatory derating for a typical application that utilizes a
single sided PC board with 0.51 mm (0.020 inch) wide
traces, assuming that no other provision is provided for
heat dissipation. The other derating curves from higher
ambient temperatures, shown as dashed lines on Figure 2,
represent allowed increased drive currents when the
design incorporates a more elaborate PC board mounting
assembly to obtain a lower ROJA value for increased heat
dissipation. The temperature deratings of Figure 2 ensure
reliable operation for both dc and pulsed mode operation.

D~~V: SHEET] [IJIPEAK]

[Iv DATA SHEET]

Where: IAVG = The average forward current through an
LED element
IAVG DATA SHEET= The average current ai
which Iv DATA SHEET is measured
The luminous intensity value at TA = 25°C is adjusted by
the following exponential equation to obtain the light
output value at the operating ambient temperature.
Iv (TA OPERATING) = Iv (25°C)e lk (TA

- 25'C))

(9)

Worst Case Power Calculation
The worst case power is that power dissipated within the
junction of a maximum forward voltage device. The worst
case power is used for determining the worst case T J that
will result from a specific drive current and thermal
resistance, see Equation 1. The expected maximum forward voltage (VF MAX) at a selected drive current is
determined by an equation on the data sheet of the form:
VFMAX = VON + (lPEAK) (LED Dynamic Resistance)

Standard Red

-.0188/°C

High Efficiency Red

-.0131/"C

Yellow

-.0112/°C

Green

-.0104/°C

Pulsed Mode vs .. DC Operation
When operating an LED device under dc drive conditions,
the junction temperature is a linear function of the dc
power dissipation multiplied by ROJA. The light output is
proportional to the dc drive current as expressed in
Equation 7.

(5)

PWORST CASE = (lPEAK) (DUTY FACTOR) (VF MAX at IPEAK);
For Pulsed Operation

Current Limiting

The use of a 50 or 60 Hertz half or full-wave rectified ac as
the drive current for LED devices is not recommended,
since the rms power in a rectified sine wave is greater than
the time averaged power of a rectangular waveform of an
equivalent peak value. Pulsed drive conditions are based
on the assumption that the drive current pulses are a
rectangular waveform. If a rectified sine wave is to be
used, in no case should the value of the peak current
exceed the maximum allowed dc current value.

An LED is a current operated device and some kind of
current limiter must be incorporated as part of the drive
circuitry. This current limiter usually takes the form of a
resistor placed in series with the LED. The typical forward
voltage characteristic of Figure 4 is used to calculate the
series current limiter for each LED element.
RUMITER =

k

(4)

The worst case power is the product of the time average
current under pulsed operation (dc current for dc operation) times VF MAX:
PWORST CASE = (Ioc) (VF MAX); For DC Operation

LED

(6)

VCC(POWER SUPPLY) -VSAT(ORIVE TRANSISTORS)-VF(FIGURE

4)

IpEAK CURRENT PER LEO ELEMENT

466

When operating an LED device in a pulsed mode, it is the
peak junction temperature (not the average) that governs

the performance of the device as to the allowed time
average power dissipation and light output. The lower the
peak junction temperature (TJ PEAK) is in relationship to
the time average junction temperature (TJ AVG), the
greater is the light output of the device. At slow refresh
rates (the number of times per second a device is pulsed)
" in the range of 100 Hz, TJ PEAK is greater than TJ AVG. As
the refresh rate approaches 1000 Hz, the value of TJ PEAK
approaches the value of TJ AVG. Therefore, it is recommended that whenever possible LED devices be refreshed
at a 1 KHz rate or faster, since at these faster pulse rates TJ
PEAK is assumed to be equal to TJ AVG and the light
output is a function of TJ AVG.

From Equation 6 and assuming Vcc = 5.0V:
RLiMITER = 5.0V - O.4V - 2.0V = 1490 -RLIMITER
0.0175A
=
Use a 1500 standard value resistor.
Step 4.
From Figure 5, the normalized lightat 17.5mA is a factor of
4.4 x the light output at 5mA.
From Equation 7:
Iv (25° C) = (300J,lcd)(4.4) = 1320 J,lcd/segment
Using Equation 9 to adjust the light output for TA = 65° C:
Iv (65°C) = (1320J,lcCl)e[-·0131/'C (65-25)'C]

Design Steps

Iv (65°C) = (1320)(0.592) = 782J,1cd/segment •

In order to determine the derated drive conditions from
the data sheet for an elevated ambient temperature, a
value for RliJA must be selected. Once a value for RliJA has
been selected, the required current derating can be
determined for the operating ambient temperature directly from Figure 2. As illustrated in the pulsed mode design
example, the dc derating is used to determine the pulsed
current derating.

A four digit display using the same high efficiency red
seven segment display described in the DC Design Example is to be operated in a pulsed mode in an ambient of
TA = 65°C. Additional pertinent data for this device are:

Pulsed Mode Design Example

Maximum Peak Current per Segment
(TA = 50°C, Pulse Width = 2ms) = 60mA

The four basic design steps are:

VF MAX = 1.75V + IPEAK (380); for IPEAK

1. Determine derated drive currents.

4. Calculate the light output.

DC Design Example
A high efficiency red seven segment display is to be
operated in an ambient ofTA = 65° C. Pertinent data forthis
device are:
Maximum DC Current per segment (TA = 50°C) = 20mA
Maximum Average Power Dissipation (TA =50°C) =81 mW

= 300pcd

per segment at loc

20mA

Figure 1 is used to select the refresh conditions for pulsed
operation. These refresh conditions are junction temperature related to the dc current deratings of Figure 2.
Figure 1 relates the ratio of maximum-peak current to
temperature derated maximum de current (lPEAK MAX/I DC
MAX) and pulse duration (tp) as a function of refresh rate
(f). The allowed average power dissipation decreases
below f = 1kHz since the difference between TJ PEAK and
TJ AVG increases with decreasing refresh rates. This
condition is illustrated by the dashed line shown on Figure
1, which shows the ratio of IPEAK MAX to loc MAX
decreasing with slower refresh rates with the duty factor
fixed at 1 of 4.

3. Calculate the value of the current limiting resistor. Use
the nearest standard value resistor larger than the
calculated value.

Iv TYPICAL

~

It is assumed that a value of RliJA = 494° CIW/segment or
less will be incorporated into the display system design.

2. Calculate the required value of Rlipc-A forthe PC board
mounting configuration.

r

Iv

= 5mA

RliJ-PIN = 282°C/W/Segment

Step 1.
For best performance, a refresh rate of 1kHz will be used:

VF MAX = 1.60V + loc (450); for 5mA :S loc :S 20mA

~.

TJ MAX = 100°C

A four digit display sets the duty factor (D. F.) at one of
four:

The data sheet curves on page 2 apply to this device. It is
assumed that a value of RliJA = 494°CIW/Segment or less
will be incorporated into the display system design.
Step 1.
The derated dc drive current is determined from Figure 2.

D.F.
tp

From Figure 1:
IPEAK/loC MAX = 3.3; for tp = 250J,ls and f = 1kHz

At TA = 65°C and RliJA:S 494°C/W/Segment,
loc MAX = 17.5mA ..

D.F. = 1/4 ..
tp = (1/f)(D.F.) = (1/1000 Hz)(1/4) = 250J,ls ..

loc MAX

From Figure 2:
loc MAX, at TA
17.5mA

Step 2.
The required maximum thermal resistance for the PC
board assembly is calculated from Equation 2:

= 65°C and RliJA = 494°C/W/Segment, is

IPEAK = (lPEAK MAX/I DC MAX)(loc MAX from Figure 2)

= 212°C/W/Segment_ Rlipc-A

IPEAK = (3.3)(17.5mA) = 57.8mA per Segment -IPEAK

Step 3.
A value of VSAT = 0.4 volts is assumed for the LED drive
transistors. From Figure 4,

IAVG = (lPEAK)(D.F.) = (57.8mA)(1/4) = 14.5mA_IAVG

Rlipc-A

5: (494-282)

These are the maximum pulsed mode drive currents for
this design as defined by TA = 65°C and RliJA :S 494° C/W/
segment.

VF TYP (17.5mA) = 2.0V

467

Step 2.
The required maximum thermal resistance for the PC
board assembly is calculated from Equation 2:

For this example:

RlJpC-A ~ (494-282) =
212°C/w/segment ..

The particular LED display device used in this example
may be operated at maximum power dissipation in an
ambient of TA = 65°C without derating as long as the PC
board mounting configuration is designed to have RlJpC-A
~ 150° C/W/Segment.

RlJpC-A

RllpC-A MAX

Step 3.
A value of VSAT = 1.2 volts is assumed for the LED drive
transistors. From Figure 4,

5.0V - 1.2V - 2.85V
RLIMITER =
0.578A

(432-282) = 150°C/W/segment __ RlJpc_A MAX

CAUTION: Since these calculations are based on
only TJ AVG and exclude the consideration of TJ PEAK, pulsed operation
without derating is only recommended
for refresh rates of 1kHz or faster.

VF TYP (57.8mA) = 2.85V
From Equation 6 and assuming VCC

~

= 5.0V:

=160
....I----RUMITER
=

Use a 170 standard val ue resistor.

Soldering Plastic LED Devices

Step 4.
From Figure 3, the relative efficiency for IPEAK = 57. SmA is:

Because plastic LED devices utilizing a lead frame construction have the LED dice attached directly to the
cathode lead, the cathode lead is the direct thermal and
mechanical stress path to the LED dice. For this reason, it
is necessary to carefully control the solder temperature
and dwell time in the solder wave to ensure subsequent
reliable operation. LED devices can be effectively wave
soldered with a wave temperature of 245°C and a dwell
time of 1% to 2 seconds.

1]IPEAK = 1.61
From Equation!t
Iv(25°C) = r14.5mAl [1.61J[300J,lcd] =
5mA
1401pcd per segmen,t

J

l

Using Equation 9 to adjust the light output for TA = 65°C:
Iv(650C) = (1401J,1cd)e[-.o131/'c (6S-2S)'C)

The post solder cleaning process is also crucial to
ensuring reliable performance. In order to optimize device
optical performance, specially developed plastics are
used which restrict the solvents that may be used for
cleaning. It is recommended that only mixtures of Freon
(F113) and alcohol be used for vapor cleaning processes,
with an immersion time in the vapors of less than two (2)
minutes maximum. Some suggested vapor cleaning solvents are Freon TE, Genesolv DI-15 or DE-15, Arklone A
or K. A 60°C (140°C) water cleaning process may also be
used, which includes a neutralizer rinse (3% ammonia
solution or equivalent), a surfactant rinse (1% detergent
solution or equivalent), a hot water rinse and a thorough
air dry. Room temperature cleaning may be accomplished
with Freon T -35 or T -P35, Ethanol, Isopropanol or water
with a mild detergent.

Iv (65° C) = (1401 )(0.592).= 829J,1cd per Segment~ Iv

Operation Without Derating
LED lamp and display devices may be operated in elevated
ambient temperature environments without derating only
when the PC board mounting configuration is designed
for a sufficiently low thermal resistance. The critical
criterion is that the LED junction temperature must not
exceed the TJ MAX value for the device. This low thermal
resistance design will typically include such items as a
maximum metallized PC board and possible heat sinking
to ensure adequate heat dissipation. In no situation
should the absolute maximum current limitations be
exceeded.
The necessary thermal resistance requirements for operation without derating are calculated using the value for
worst case power dissipation. A numerical example using
the LED display device from the above two examples will
illustrate the calculation procedure.

Some LED devices may require special handling during
soldering, during post solder cleaning, or may not lend
themselves to a wave soldering process. Three specific
considerations are:
1. Plastic LED Lamps: The plastic encapsulant that forms
the lamp package is the only supporting element forthe
leads. It is important to prevent stresses from entering
the device package which could damage the LED die
attach and wire bonds. The leads of a lamp may be bent
to a desired angle by observing the following procedure. Firmly grasp the leads at the base of the lamp
package with a pair of needle nose pliers to supportthe
lamp while bending the leads. Overheating during
soldering will cause melting of the plastic, ~lIowing
possible lead movement to occur which may result in
the catastrophic failure of the die attach or wire bonds.
Care should be taken to ensure that no stresses are
applied to the leads during the soldering process.
External stresses applied to the leads during soldering
could induce strains within the device package that
may induce latent failure. Once properly soldered in
place, an L~D lamp will typically exhibit a very high
degree of reliability.

Step 1.
Determine the maximum permissible value for RIIJA.
The absolute maximum power dissipation as listed on the
data sheet for this particular LED device is 81 mW. The
operating ambient temperature is to be 65° C.
Referring to Equation 3
RIJJA MAX ~ TJ MAX - TA OPERATING
PMAX DATA SHEET
For this example:
RIIJA MAX

~

10ifC-6~C
.081W

•
= 432° C/W/Segment

The required limit on the thermal resistance for the PC
board mounting configuration is derived by rewriting
Equation 2:
ROPC-A MAX

~

RIJJA MAX - ROJ-PIN

468

2. PC Board Monolithic Displays: Many PC board monolithic displays do not lend themselves to a wave
soldering process. The plastic lens that covers the LED
chips and wire bonds is attached to the PC board
without forming a seal. The chemicals used in a wave
soldering process can collect underneath the lens. The
post solder cleani ng process may not remove all of the
trapped chemicals and prolonged exposure of the LED
dice and wirebonds to these chemicals can cause
permanent damage. Also, the plastic used to make
some of the lenses is suscepti ble to damage from rosin
fluxes and hydrocarbon cleaners. The two recommended installation procedures are either to hand
solder flexible cable to the display contacts or use
solderless connector pins such as the 022-002 series

supplied by JAV Manufacturing, 125 Wilbur Place,
Bohemia, NY 11716. Effective room temperature cleaning may be accomplished using Freon TP-35 or TE-35,
solvent temperature ::; 30 0 C and an immersion time::; 2
minutes.
3. Silver Lead Frames: Many plastic LED devices utilize a
silver plated lead frame. Silver plating provides excellent solderability as long as the leads are kept free
from tarnish buildup due to coming in contact with
sulfur compounds. Application Bulletin 3 offers specific information on the effective use and soldering of
si Iver lead frame devices.
It is suggested that the device data sheet be consulted
for specific information on wave soldering.

c

-

469
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........ ;.:0.... $ .... ·., ............... V·i._

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HP Components
Franchised· Distributor
And Representative
Directory
March 1980

United States
Alabama
Hall-Mark Electronics
4733 Commercial Drive
Huntsville 35805
(205) 837-8700

Hamilton/Avnet
4692 Commercial Drive
Huntsville 35805
(205) 837-7210
Arizona
Hamilton/Avnet
505 South Madison
Tempe 85281
(602) 894-2594

Wyle Distribution Group
8155 North 24th Avenue
Phoenix 85021
(602) 249-2232
In Tucson (602) 884-7082
California
Hamilton/Avnet
4545 View ridge Avenue
San Diego 92123
(714) 279-2421

Hamilton/Avnet
1175 Bordeaux Drive
Sunnyvale 94086
(408) 743-3355
Hamilton Electro Sales
3170 Pullman Street
Costa Mesa 92626
(714) 641-4120
Hamilton Electro Sales
10950 Washington Boulevard
Culver City 90230
(213) 558-2121

Wyle Distribution Group
17872 Cowan Avenue
Irvine 92704
(714) 641-1600

Schweber Electronics
2830 N. 28th Terrace
Hollywood 33020
(305) 927-0511

Schweber Electronics
9218 Gaither Road
Gaithersburg 20760
(301) 840-5900

Wyle Distribution Group
9525 Chesapeake Drive
San Diego 92123
17141565-9171

Georgia
Hamilton/ Avnet
6700 1-85 Suite IE
Norcross 30071
(404) 448-0800

Wilshire Electronics
1037 Taft Street
Rockville 20850
(301) 340-7900

Wyle Distribution Group
3000 Bowers Avenue
Santa Clara 95052
(408) 727-2500
Colorado
Hamilton/Avnet
5921 N. Broadway
Denver 80216
(3031 534-1212

Wyle Distribution Group
6777 E. 50th Avenue
Commerce City 80022
(303) 287-9611
Connecticut
Hamilton/Avnet
643 Danbury Road
Georgetown 06829
1203) 762-0361

Schweber Electronics
Finance Drive
Commerce Industrial Park
Danbury 06810
(203) 792-3500
Wilshire Electronics
Village Lane
P.O. Box 200
Wallingford 06492
(203) 265-3822

Schweber Electronics
4126 Pleasantdale Road
Atlanta 30340
(404) 449-9170
Indiana
Pioneer-Standard
6408 Castleplace Drive
Indianapolis 46250
(317) 849-7300
Illinois
Hall-Mark Electronics
1177 Industrial Drive
Bensenville 60106
(312) 860-3800

Hamilton/Avnet
3901 N. 25th Avenue
Schiller Park 60176
(312) 678-6310
Schweber Electronics
1275 Brummel Avenue
Elk Grove Village 60007
(312) 364-3750
Kansas
Hall-Mark Electronics
11870 West 91 st Street
Shawnee Mission 66214
(913) 888-4747

Schweber Electronics
3110 Patrick Henry Drive
Santa Clara 95050
(408) 496-0200

Florida
Hall-Mark Electronics
1302 W. McNab Road
Ft. Lauderdale 33309
(305) 971-9280

Hamilton/Avnet
9219 Quivira Road
Overland Park 66215
(913) 888-8900

Schweber Electronics
17811 Gillette Avenue
Irvine 92714
( 714) 556-3880

Hall-Mark Electronics
7233 Lake Ellenor Drive
Orlando 32809
(305) 855-4020

Maryland
Hall-Mark Electronics
6655 Amberton Drive
Baltimore 21227
(301) 796-9300

Wyle Distribution Group
124 Maryland Street
EI Segundo 90245
(213) 322-8100

Hamilton/Avnet
3197 Tech Drive No.
SI. Petersburg 33702
1813) 576-3930

Hamilton/Avnet
7235 Standard Drive
Hanover 21076
(301) 796-5000

472
-~--

----_.

Massachusetts
Hamilton/Avnet
50 Tower Office Park
Woburn 01801
(617) 273-7500

Schweber Electronics
25 Wiggins Avenue
Bedford 01730
(617) 890-8484
Wilshire Electronics
One Wilshire Road
Burlington 01803
(617) 272-8200
Michigan
Hamilton/Avnet
32487 Schoolcraft Road
Livonia 48150
(313) 522-4700

Schweber Electronics
33540 Schoolcraft Road
Livonia 48150
(313) 583-9242
Minnesota
Hall-Mark Electronics
9201 Penn Avenue, So.
Suite 10
Bloomington 55431
(612) 884-9056

Hamilton/ Avnet
7449 Cahill Road
Edina 55435
(612) 941-3801
Schweber Electronics
7402 Washington Avenue, So.
Eden Prairie 55343
(612) 941-5280
Missouri
Hall-Mark Electronics
13789 Rider Trail
Earth City 63045
(3141291-5350

,f~"

""-

Hamilton/Avnet
396 Brookes Lane
Hazelwood 63042
(314) 731-1144

Schweber Electronics
Jericho Turnpike
Westbury 11590
(516) 334-7474

New Jersey
Hamilton/Avnet
1 Keystone Avenue
Cherryhill 08003
(609) 424-0100

Wilshire Electronics
10 Hooper Road
Endwell 13760
(607) 754-1570

HamiltonlAvnet
10 Industrial Road
Fairfield 07006
(201 ) 575-3390
Schweber Electronics
18 Madison Road
Fai rfield 07006
(201) 227-7880

l

Wilshire Electronics
110 Parkway So. Drive
Hauppauge, L.I. 11787
(516) 543-5599

Pennsylvania
Hall-Mark Electronics
458 Pike Road
Huntingdon Valley 19001
(215) 355-7300

Wilshire Electronics
1260 Scottsville Road
Rochester 14624
(716) 235-7620

Pioneer-Standard
560 Alpha Drive
Pittsburgh 15238
(412) 782-2300

Wilshire Electronics
1111 Paulison Avenue
Clifton 07015
(201) 340-1900

North Carolina
Hall-Mark Electronics
1208 Front Street, Bldg. K
Raleigh 27609
(919) 832-4465

Wilshire Electronics
102 Gaither Drive
Mt. Laurel 08057
(609) 234-9100

Hamiltonl Avnet
2803 Industrial Drive
Raleigh 27609
(919) 829-8030

New Mexico
HamiltonlAvnet
2524 Baylor S.E.
Albuquerque 87106
(505) 765-1500

Ohio
Hall-Mark Electronics
6969 Worthington-Galena Road
Worthington 43085
(614) 846-1882

New York
HamiltonlAvnet
16 Corporate Circle
East Syracuse 13057
(315) 437-2641

Pioneer-Standard
4800 East 131st Street
Cleveland 44105
(216) 587-3600

Hamiltonl Avnet
5 Hub Drive
Melville 11746
(516) 454-6000

r

Oregon
Representative
Northwest Marketing
Associates, Inc.
9999 S.W. Wilshire Street
Suite 211
Portland 97225
(503) 297-2581
(206) 455-5846

Hamiltonl Avnet
167 Clay Road
Rochester 14623
(716) 442-7820
Schweber Electronics
2 Townline Circle
Rochester 14623
(716) 424-2222

Schweber Electronics
101 Rock Road
Horsham 19044
(609) 964-4496
(215) 441-0600
Texas
Hall-Mark Electronics
10109 McKalia Road
Suite F
Austin 78758
(512) 837-2814
Hall-Mark Electronics
11333 Pagemill Drive
Dallas 75222
(214) 234-7400

Pioneer-Standard
1900 Troy Street
Dayton 45404
(513) 236-9900

Hall-Mark Electronics
8000 Westglen
P.O. Box 42190
Houston 77042
(713) 781-6100

Schweber Electronics
23880 Commerce Park Road
Beachwood 44112
(216) 464-2970

Hamiltonl Avnet
10508 A. Boyer Boulevard
Austin 78757
(512) 837-8911

Oklahoma
Hall-Mark Electronics
5460 South 103rd E. Avenue
Tulsa 74145
(918) 835-8458

Hamilton/Avnet
4445 Sigma Road
Dall!is 72540
(214) 661-8661

473

Hamilton/Avnet
3939 Ann Arbor
Houston 77063
(713) 780-1771
Schweber Electronics
14177 Proton Road
Dallas 75240
(214) 661-5010
Schweber Electronics
7420 Harwin Drive
Houston 77036
(713) 784-3600
Utah
Hamiiton/Avnet
1585 West 2100 South
Salt Lake City 84119
(801 ) 972-2800
Washington
Hamilton/Avnet
14212 N.E. 21st Street
Bellevue 98005
(206) 746-8750
Wyle Distribution Group
1750 132nd Avenue, N.E.
Bellevue 98005
(206) 453-8300
Representative
Northwest Marketing
Associates, Inc.
12835 Bellevue-Redmond Road
Suite 203E
Bellevue 98005
(206) 455-5846
Wisconsin
Hall-Mark Electronics
9625 South 20th Street
Oakcreek 53154
(414) 761-3000
Hamiiton/Avnet
2975 Moorland Road
New Berlin 53151
(414) 784-4510

International
Australia
Representatives
CEMA ELECTRONICS PTY. LTD. Cantec Reps, Inc.
170 Stu rt Street
28 Eastmoor Cresent
Adelaide, S.A.
Dollard Des Ormeaux
(61) 8516483
Montreal, Quebec H9G 2Nl
(514) 620-6313
CEMA ELECTRONICS PTY. LTD.
208 Whitehorse Road
Cantec Reps, Inc.
Blackburn, Victoria
83 Galaxy Boule·vard
(61) 3 8775311
Unit lA
CEMA ELECTRONICS PTY. LTD. Toronto (Rexdale)
Ontario M9W 5X6
22 Ross Street
(416) 675-2460
Newstead, Queensland
(61) 72524261
CEMA ELECTRONICS PTY. LTD.
21 Chandos Street
St. Leonards, N.S.W. 2065
(61) 2 4394655

Cantec Reps, Inc.
1573 Laperriere Avenue
Ottawa, Ontario K1Z 7T3
(613) 725-3704

RTG E. Springorum Kg
GmbH & Co.
Bronnerstrasse 7
4600 Dortm und
(49) 231 54951

Ryoyo Electric Corporation
Konwa Building
12-22 Tsukiji, 1-Chome
Chuo-Ku, Tokyo
(81) 3 5437711

RTG Distron
Behaimstr. 3
Postfac h 100208
1000 Berlin 10
(49) 303421041/45

New Zealand
CEMA ELEKON LTD.
7-9 Kirk Street
Grey Lynn, Auckland
(64) 4 761169

Holland
Diode B.V.
Hollant Laan 22
3526 Am Utrecht
(31) 30884214

Norway
Ola Tandberg Elektro A/S
Skedsmogt. 25
Oslo 6
(47) 2 197030

India
Blue Star Ltd.
Blue Star House
11/11 A Magarath Road
Bangalore
560025

Spain
Diode Espana
Avda de Brasil 7
Edif. Iberia Mart
Madrid 20
(34) 1 4550139/40

Austria
Transistor V.m.b.H.
Auhofstr.41a
1130 Wien
(43) 222829451

Denmark
Distri butoeren
Interelko A.P.S.
Hovedgaden 16
4622 Havdrup
(45) 3 385716

Belgium
Diode Belgium
Rue Picard 202
1020 Bruxelles
(32) 2 4285108

Finland
Field OY
Veneentekijantie 18
00210 Helsinki 21
(90) 6922577

Blue Star Ltd.
Silhas
414/2 Viv Savarkar Marg
Prabhadevi
Bombay 400 025
457887

So. Africa
Fairmont Electronics (Pty.) Ltd.
P.O. Box 41102
Craig hall 2024
Transvaal
(27) 11 7891230

Brazil
Datatronix Electronica LTDA
Av. Pacaembu, 746-Cl1
Sao Paulo, Brazil
(55) 11 8260111

France
Almex
Zone Industrielle d'Antony
48, rue de l'Aubepine
92160 Antony
(33) 1 6662112

Blue Star Ltd.
Bhandari House
7th and 8th Floor
91 Nehru Place
New Delhi 110024
634770
635166

Sweden
Distributoeren
Interelko A.B.
Box 32
122 21 Enskede
(46) 8 132160

Canada
Hamiltonl Avnet
3688 Nashua Drive
Units G & H
Mississauga, Ontario L4V 1 M5
(416) 677-7432
Hamilton/Avnet
2670 Sabourin Street
St. Laurent
Montreal, Quebec H4S 1 M2
(514) 331-6443
Hamiltonl Avnet
1735 Courtwood Crescent
Ottawa, Ontario K2C 3J2
(613) 226-1700
Zentronics, Ltd.
1355 Meyerside Drive
Mississauga, Ontario LST lC9
(416) 676-9000
Zentronics, Ltd.
5010 Pare Street
Montreal, Quebec H4P 1P3
(514) 735-5361
Zentronics, Ltd.
141 Catherine Street
Ottawa, Ontario K2P 1C3
(613) 238-6411

ETS. F. Feutrier
rue des trois Glorieuses
42270 St-Priest-en-Jarez
St. Etienne
(33) 77 746733
F. Feutrier
29 rue Ledru Rollin
92150 Suresnes
(33) 1 7724646
S.C.A.I.B.
80 rue d'Arcueil
Zone-Silic
94150 Rungis
(33) 1 6872313
Germany
EBV Elektronik
Vertriebs GmbH
Oberweg 6
8025 Unterhaching
(49) 89 611051
Ingenieurbuero Dreyer
Flensburger Strasse 3
2380 Schleswig
(49) 4621 23121
Jermyn GmbH
Postfach 1180
6277 Cam berg
(49) 6434/23-1

Israel
Electronics and Engineering
Div. of Motorola Israel Ltd.
16 Kremenetski Street
P.O. Box 25016
Tel Aviv 67899
(97) 23338973
Italy
Celdis Italiana S.p.A.
Via F. IIi Gracchi, 36
20092 Cinisello B.
(39) 26120041

Switzerland
Baerlocher AG
Forrlibuckstrasse 110
8021 Zurich
(41) 1 429900
United Kingdom
Celdis Ltd.
37 -39 Loverock Road
Reading
Berkshire RG3 1 ED
(44) 734 585171

Eledra S.p.A.
Viale Elvezia 18
20125 Milano
(39) 3493041

Jermyn-Mogul Distribution
Vestry Estate
Seven Oaks
Kent TN14 5EU
(44) 732500144

Japan
Ryoyo Electric Corporation
Meishin Building
1-20-19 Nishiki
Naka-Ku, Nagoya, 460
(81) 522030277

Macro Marketing Ltd.
396 Bath Road
Oippheham
Slough
Berkshire SL1 6JD
(44) 6286 4422

Ryoyo Electric Corporation
Taiyo Shoji Building
4-6 Nakanoshima
Kita-Ku, Osaka, 530
(81) 6 4481631

474

Sales/Service Offices
Arranged alphabetically by country

r

ANGOLA
Telectfa
Empresa T6cnica de
Equipamenlos
El6ctricos, S.A.A,L.
R. Barbosa Rodrigues,
41-1"0T."
Cai,a Postal, 6487
Luanda
Tel: 35515/6
ARGENTINA
HewleU·Packard Argentina S.A.
Santa Fe 2035, Martinez

BAHRAIN
Medical Only
Wael Pharmacy
P.O. Bo, 648
eahraln
Tel: 54886, 56123
Telex: 8550 WAEL GJ
AI Hamidiya Trading and
Contracting
P.O, Box 20074
Manama
Tel: 259978, 259958
Telex: 8895 KALOIA GJ

6140 Bueno. Air••

BANGLADESH
The General Electric Co. 01
Bangladesh Ltd,
Magnel House 72
Dilkusha Commercial Area
MotlJheU, Dacca 2
Tel: 252415, 252419
Telex: 734

Tel: 792-1239, 798-6086
Telex: 122443 AA CIGY
Biotron S.A.C.l.y M.
Avda. Paseo Colon 221
9 piso
1399 Bueno. Alre.
Tel: 30-484611B5118384
34-9356/0460/455 I
Telex: (33) 17595 BID AA
AUSTRALIA
AUSTRALIA CAPITAL
TERR_
Hewletl-Packard Australia Pty.
Lid.
121 Wollongong Streel
Fyahwlck, 2609
Tel: 804244
Telex: 62650
NEW SOUTH WALES
Hewlett-Packard Australia Ply.
Ltd.
3 I Bridge Sireel
Pymble, 2073
Tel: 4496586
Telex: 21561
QUEENSLAND
Hewlett Packard Australia Pty.
Ltd.
5th Floor
Teachers Union Building
495-499 Boundary Streel
Spring Hili, 4000
Tel: 2291544
SOUTH AUSTRALIA
Hewlelt-Packard Australia pty.
Ltd.
153 Greenhill Aoad
Parkalde, 5063
.. Tel: 272591 I
Telex: 82536
VICTORIA
Hewlett-Packard Australia Ply.
Lid.
3 I -4 I Joseph Streel
Blackburn, 3130
Tel: 89-6351
Telex: 31024 MELB
WESTERN AUSTRALIA
Hewleli-Packard Auslralia Ply.
Lid.
14 I Stirling Highway
N.dlanda, 6009
Tel: 3865455
Telex: 93859
AUSTRIA
Hewlelt-Packard G~s,m.b.H.
Wehlistrasse 29
P.O, Box 7
A- 1205 VI.nna
Tel: 35- 16-21-0
T.~"

135821135066

HelltleH·Packard Ges.m.b.H.
Weh1181r88se, 29
A·I205 WI.n
1.,: 35- 16-21
1elex: 135066

BELGIUM
Hewlett-Packard Benelux
S,A.lN.V.
Avenue du Col-Vert, 1,
(Groenkraaglaan)
B- I 170 Brullela
Tel: (02) 660 50 50
Telex: 23-494 paloben bru
BRAZIL
Hewletl-Packard do Brasil
l.e.C. Ltda.
Alameda Aio Negro, 750
Alphaville
06400 Bar.erl SP
Tel: 429-3222
Hewlett-Packard do Brasil
l.e.C. Llda.
Aue Padre Chagas, 32
90000-P6rto Alegre-AS
Tel: 22-2998, 22-5621
Hewlett-Packard do Brasil
l.e.C. Llda,
Av. Epilacio Pessoa, 4664
22471-Rlo de Janelro-AJ
Tel: 286-0237
Telex: 021-21905 HPBR-BA
CANADA
ALBERTA
Hewlett-Packard (Canada) Lid.
I 1620A - 1681h Sireel
Edmonton T5M 3T9
Tel: (403) 452-3670
TWX: 610-831-2431
Hewlett-Packard (Canada) Lid.
210,7220 Fisher SI. S,E.
Calgary T2H 2H8
Tel: (403) 253-2713
TWX: 610-821-614 I
BRITISH COLUMBIA
Hewlett-Packard (Canada) Lid.
10691 Shellbridge Way
Richmond V6X 2W7
Tel: (604) 270-2277
TWX: 6 I 0-925-5059
MANITOBA
Hewlett-Packard (Canada) Lid.
380-550 Cenlury SI.
St. Jam •• ,
Winnipeg R3H OY I
Tel: (204) 786-6701
TWX: 610-671-3531
NOVA SCOTIA
Hewlelt-Packard (Caneda) Lid.
P.O. Box 931
800 Windmill Aoad
Dartmouth B3B tL I
Tel: (902) 469-7820
TWX: 610-27 I -4482

ONTARIO
Hewlett-Packard (Canada) Ltd.
1020 Morrison Or,
Ottawa K2H 8K7
Tel: (613) 820-6483
TWX: 610-563-1636
Hewlett-Packard (Canada) Ltd.
6877 Gareway Drive
Mlllillaug. L4V IM8
Tel: (416) 678-9430
TWX: 610-492-4246
Hewlett-Packard (Canada) Ltd.
552 Newbold Sireel
London N6E 2S5
Tel: (519) 686-9181
TWX: 610-352-1201
QUEBEC
Hewlett-Packard (Canada) Ltd.
275 Hymus Blvd.
Pointe Cilire H9A IG7
Tel: (514) 697-4232
TWX: 610-422-3022
FOR CANADIAN
AREAS NOT
LISTED:
Coniaci Hewlett-Packard (Canada) Lid, in Mississauga,
CHILE
Jorge Calcagni y Cia. Llda,
Arluro Burhle 065
Casilla 18475
Correo 9, Santiago
Tel: 220222
Telex: JCALCAGNI
COLOMBIA
Instrumentaci6n
Henrlk A, Langebaek & Kler
SA
Carrera 7 No. 48·75
Apartado Mreo 6287
B090t', I O.E.
Tel: 269-8877
Telex: 44400
Instrumentaci6n
H.A. Langebaek & Kier SA
Carrera 63 No. 49-A-31
Aparlado 54098
Medellin
Tel: 304475
COSTA RICA
Cienlifica Coslarricense SA
Avenida 2, Calle 5
San Pedro de Montes de Oca
Aparlado 10159
San Jo ••
Tel: 24-38-20, 24-08- 19
Telex: 2367 GALGUA CR
CYPRUS
Kypronics
19 Gregorios Xenopoulos
Streel
P.O. Box 1152
Nlcolla
Tel: 45628/29
Telex: 3018
CZECHOSLOVAKIA
Hewlett-Packard
Obchodni zastupitelstvi v CSSR
Pisemny styk
Post. schranka 27
CS 11801 Praha 01 I
CSSA
Vyvojova a Provozni Zakladna
Vyzkumnych Ustavu v
Bechovicich
CSSR-25097 Bechovlce u
Prahy
Tel: 89 93 41
Telex: 12133

475

Institute of Medical Bionics
Vyskumny Uslav lekarskej
Bioniky
Jedlova 6
CS·88346 Bratislava"

Kramar.
Tel: 44-551
Telex: 93229
DENMARK
Hewlett-Packard AlS
Oatavej 52
OK-3460 Blrkerod
Tel: (02)81 86 40
Telex: 37409 hpas dk
Hewlett·Packard AJS
Navervej 1
OK-8600 SUkeborg
Tel: (06) 82 71 66
Telex: 37409 hpas dk
ECUADOR
CYEOE Cia. Llda.
P,O. Box 6423 CCI
Av. Eloy Maro 1749
Oulto
Tel: 450-975, 243-052
Telex: 2548 CYEDE ED
Medicel Only
Hospitalar SA
Casilla 3590
Aobles 625
QUito
Tel: 545-250
EGYPT
I.EA
International Engineering
Associates
24 Hussein Hegazi Street
Kasr-el-Aini
Cairo
Tel: 23 829
Telex: 93830
SAMITAO
Sami Amin Trading Office
18 Abdel Aziz Gawish
Abdlne·Calro
Tel: 24932
EL SALVADOR
IPESA
Bulevar de los Heroes I 1-48
Edilicio Sarah 1148
San Salvador
Tel: 252787
ETHIOPIA
Abdella Abdulmalik
P.O. Box 2635
Addl, Abab.
Tel: II 9340
FINLAND
Hewlett-Packard Oy
Revontulenlie, 7
SF-02100 Eapoo 10
Tel: (90)455 021 I
Telex: 121583 hewpa sl
FRANCE
Hewlett-Packard France
Zone d'activiles de
Courlaboeuf
Avenue des Tropiques
Bolle Postale 6
91401 Or••y-C6dex
Tel: II) 907 78 25
TWX: 600048F
Hewlelt-Packard France
Chemin des Mouilles
8.P.I62
69130 EcuUy
Tel: (78)33 81 25
TWX: 310617F

Hewlett-Packard France
20, Chemin de La C6pi~re
3t081 Toutou••
L. MlrIU-GMe,
Tel: (61) 40 II 12
HewleU·Packard France
Le Ligoures
Place Rom6e de Villeneuve
13100 Alx-en·Provence

Tel: (42) 59 4 I 02
TWX: 410770F
Hewlett·Packard France
2, Allee de la Bourgonette

35100 Renne.
Tel: (99) 5 I 42 44
TWX: 740912F
Hewletl-Packard France
18, rue du Canal de la Marne
67300 SchUtlgh.'m
Tel: (88) 83 08 10
TWX: 89014 IF
Hewletl-Packard France
Immeuble pMcentre
rue van Gogh
59650 Villeneuve O'Ascq
Tel: (20) 914125
TWX: 160124F
Hewlett-Packard France
BAlimenl Amp~re
Rue de la Commune de Paris
B.P.300
93153 Le Blanc Me.nllC6dex
Tel: (01) 931 88 50
Telex: 21 l032F
Hewlett-Packard France
Av. du Pdl. Kennedy
33700 Marlgnac
Tel: (56) 97 01 81
Hewlett-Packard France
Immeuble Lorraine
Boulevard de France
91035 Evry-CMex
Tel: 077 96 60
Telex: 692315F
Hewlett-Packard France
23 Rue Lolhaire
57000 Met.
Tel: (87)65 53 50
GERMAN FEDERAL
REPUBliC
Hewlett-Packard GmbH
Vertriebszentrale Frankfurl
Berner Strasse 117
Posttach 560 140
0-6000 Frankfurt 56
Tel: (060lt) 5004 I
Telex: 04 13249 hpffm d
Hewlett-Packard GmbH
Technisches aUro Bt5blingen
Herrenberger Strasse 110
0-7030 B~bllngen,
WUrttemberg
Tel: (07031)667-1
Telex: 07265739 bbn
Hewleli-Packard GmbH
Technisches BUro OUsseldort
Emanuel-LeulZe-Slr, I
(Seeslern)
0-4000 DU..eldorl
Tel: (0211) 5971-1
Telex: OB5/86 533 hpdd d
Hewlelt-Packard GmbH
Technisches BUro Hamburg
Kapsladlrlng 5
0-2000 Hamburg 60
Tel: (040) 63B04- I
Telex: 2 I 63 032 hphh d

Hewlett·Packard GmbH
Techni$ches BUro Hannover
Am Grossmarkl 6
0·3000 Hannover 9I
Tel: (05111466001
Telex: 0923259
Hewlett·Packard GmbH
Technisches BUro NUrnberg
Neumeyerstrasse 90
D·85oo NUrnbarg
Tel: (09111522083
Telex: 0623 860
Hewlett·Packard GmbH
Techni.cheo BUro MUnchen
Eschenslra"e 5
D·8021 Taulklrchen
Tel: (08916117·1
Telex: 0524985
Hewlett·Packard GmbH

Technisches BUro BerHn
Kailhstrasse 2-4
D· 1000 Btrltn 30
Tel: (030124 90 86
Telex: 0183405 hpbln d
GREECE

Kostas Karayannls
8 Omlrou Streel
Athena 133
Tel: 32 30 303/32/37731
Telex: 2I 59 62 RKAR GR
GUAM

Guam Mellcal Supply, Inc.
Suite C, Airport Plaza
P.O. Box 8947
Tamunlng 9691 I
Tel: 646·4513

Calcutta 700 00 I

ISRAEL

Tel: 23·0131
Telex: 021-7655
Blue Slar Lid.
Bhandari House

Electronics Engineering Div.
of Maloro'a Israel lid,
16, Kremenelski Street
P.O. Box 25016

91 Nehru Place
Naw Dalhl 110024

Tel: 682547
Telex: 031-2463
Blue Slar Lid.
T.C. 7/603 'Poornime'
Marulhankuzhi
Trlvandrum 695 0 I 3
Tel: 65799
Telex: 0884-259
Blue Star Lid.
I I Magarath Road
Bangalor. 560 025
Tel: 55668
Telex: 0845·430
Blue Star Ltd.
Meeakshi Mandlram
XXXXVI1379·2 Mahalma
Gandhi Rd.
Cochln 682 016
Tel: 32069
Tetex: 085·514
Blue Slar Ltd.
1·1·11711 Sarojinl Devi Road
Sacundorobad 500 033
Tel: 70126
Telex: 0155·459
Blue Star Ltd.
133 Kodambakkam High Road
Madra. 600 034
Tel: 82057
Tele" 041·379

GUATEMALA

ICELAND

IPESA
Avenida Reforma 3-48
Zona 9

Medical Only
Eldlng Trading Company Inc.
Hafnarnvoli • Tryggvagolu
P.O. Box 895

Guatemala City

Tel: 316627, 314786,
66471·5, ext. 9
TeleX: 4192 Telelro Gu

IS-ReykJavik

HONG KONG

BERCA indonesia P.T.
P.O. Sox 496/Jkt.
Jln. Abdul Muis 62

Hewlelt-Packard Hong Kong
Lid.
11th Floor, Four Seas Bldg.
212 Nathan Rd.
Kowloon

Tel: 3·697446 (5 linesl
Telex: 36678 HX
Medic.VAnalytical Only
Schmidl & Co. (Hong Kongl
Ltd.
Wing On Cenlre, 281h Floor
Connaughl Road, C.
Hong Kong

Tel: 5·455644
Telex: 74766 SCHMX HX
INDIA

Blue Slar Lid.
Sahas
41412 Vir Savarkar Marg
Prabhadevi
Bombay 400 025
Tel: 45 7887
Telex: 011-4093
Blue Slar Lid.
Band Box House
Prabhadevi
Bombay 400 025
Tel: 45 7301
Telex: 011·3751
Blue Star Ltd.
Bhavdeep
Stadi"" Road
Ahmedabad 380 014
T~: 43922
Telex: 012·234
Blue Star Lid.
7 Hare Street

Tel: I 58 2011 6303
INDONESIA

Jakarta

Tel: 349255, 349886
Telex: 46748 BERSIL IA
BEReA Indonesia P.T.
P.O. Box 174/Sby.
23 Jln. JimeNo
Surabaya

Tel: 42027
IRELAND

Hewlell·Packard Lid.
Kestrel House
Clanwilliam Place
lower Mount Sireet
Dublin 2, Eire
Hewlell·Packard Lid.
2C Avongberg Ind. Est.
Long Mile Road
Dublin 12
Tel: 514322/514224
Telex: 30439
Medical Only
Cardiac Services (Ireland) ltd,
Kilmore Road
Arlane
Dublin 5, Eire
Tel: (011315820
Medical Only
Cardiac Services Co.
95A Finaghy Rd. South
Belfast BTtO DBY
GB·NoNhern Ireland
Tel: (02321 625566
Telex: 747626

Yokogawa·Hewlel1-Packard
Lid.
Inoue Building
1348·3, Asahi-cho, 1·chome

Ataugl, Kanagawa 243
Tel: 0462·24·0452

Tel~Aylv

Tel: 38973
Telex: 33569, 34164

Yokogawa-Hewlett·Packard

ITALY
Hewlett·Packard Italiana S.p.A.
Via G. Oi Vittorio, 9
20063 Cornuaco Sui
Navlglto (Mil

Kumagaya Asahi
Hachijuni Building

Tel: (21903691
Telex: 334632 HEWPACKIT
Hewlelt·Packard Italiana S.p.A.
Via Turazza, 14
35100 Padova
Tel: (491664888
Telex: 430315 HEWPACKI
Hewlett·Packard Italiana S.p.A.
Via G. Armellini 10
1·00143 Roma

Tel: (061 54 69 6I
Telex: 610514
Hewlett·Packard Italiana S.p,A.

Lid.
41h Floor
H. Tsukuba
Kumagaya, Sailama 360
Tel: 0485·24·6563
JORDAN

Mouasher Cousins Co.
P.O. Box 1387
Amman

Tel: 24907/39907
Telex: SABCO JO 1456
KENYA

ADCOM Lid., Inc.
P.O. Box 30070
Nairobi

Tel: 331955
Telex: 22639

Corso Giovanni Lanza 94
1·10133 Torino
Tel: (0111659308
Telex: 221079

P.O. Box 19012
Nairobi Airport

Hewlett·Packard Italiana S,p,A.

Nairobi

Via Principe Nicola 43 GlC
1·95126 Catania
Tel: (095137 05 04
Telex: 970291
Hewlelt·Packard Ita~ana S.p.A.
Via Nuova san Rocco A
Capadimonte,62A
80131 Napott
Tel: (0811710698
Hewlett·Packard lIaliana S.p.A.
Via Marlin Luther King, 381 I I I
1·40132 Bolovna
Tel: 10511402394
Telex: 511630

Tel: 336055/56
Telex: 22201122301
Medical Only

JAPAN

AI·Kh.ldiya Trading &
Contracting
P.O. Box 830·Salal

Yokogawa·Hewlett·Packard
Ltd.
29·21, Takaido·Hlgashi
3·chome
Suginami·ku, Tokyo 168
Tel: 03·331-611 I
Telex: 232·2024 YHp· Tokyo
Yokogawa·Hewlell·Packard
Ltd.
Chuo Bldg .. 4th Floor
4·20, NishlnakaJima 5·chome
Yodogawa·ku, Osaka·shi
Oaaka, 532
Tel: 06·304·6021
Telex: 523·3624
Yokogawa·Hewlell·Packard
Ltd.
Sunllomo Seimei Nagaya Bldg.
I 1·2 Shimosa••jlma·cho,
Nakamura·ku, Nagoya, 450
Tel: 052 571·5171
Yokogawa·Hewlell·Packard
Lid.
Tanigawa Building
2·24· I Touruya·cho
Kanagawa-ku
Yokohama. 221

Tel: 045·312·1252
Telex: 382·3204 YHP YOK
Yokogawa-Hewletl-Packard
Ltd.
Mito Mitsui Building
105, 1-chome, San-no-maru
Milo, Ibaragi 310
Tel: 0292·25·7470

476

Medical Only
International Aeradio (E.A.) Lid.

MOROCCO

Dolbaau
81 rue Karalchi
C••ablanca

Tel: 304 I 82
Telex: 23051/22822
Gerep
2, rue d'Agadir
Baile Po,lal 156

C•• ablenc.
Tel: 272093/5
Telex: 23 739
MOZAMBIOUE
A.N. Goncalves, Ltd.

162, l' Api. 14 Av. D. Luis
Calxa Postal 107
Maputo

Tel: 27091, 27114
Telex: 6·203 NEGON Mo
NETHERLANDS

Hewlett·Packard Benelux N.V.
Van Heuven Goedhartlaan 121

P.O. Box 667
11 8I KK Amatolv ••n
Tel: (20147 20 21
Telex: 13216
NEW ZEALAND

Hewlelt·Packard (N.Z.I Ltd.
4·12 Cruickshank Sireet

Kilbirnie, Wellington 3
P.O. Box 9443
Courtney Place
Wellington

P.O. Box 95221
Mombas.

Tel: 877·199
Hewlelt·Packard (N.Z.I Ltd.
P.O. Box 26·189
169 Manukau Road

KOREA

Epsom, Auckland

Samsung Electronics Co., ltd.
4759 Shingil·6·Dong
Yeong Deung POU

Tel: 687·159
Analytical/Medical Onty
Northrop Instruments &
Systems Lid.,
Slurdee House
85-87 Ghuznee Street
P.O. Box 2406

International Aeradio (E.A.) ltd.

Seoul

Tel: 833·4122, 4121 ,
Telex: SAMSAN 27364
KUWAIT

Kuwait

Tel: 42 4910/41 1726
Telex: 2481 Areeg kl
LUXEMBURG

Hewlett-Packard Beneluz
S.A.lN.V.
Avenue du Col· Vert, I
(Groenkraaglaanl
B· 11 70 Bru..ol.
Tel: (021660 5050
Telex: 23 494
MALAYSIA

Hewlelt-Packard Sales
(Malayslal Sdn. Bhd.
Suile 2.2112.22
Bangunan Angkasa Raya
Jalan Ampang
Kuala Lumpur

Tel: 483680, 485653
Protei Engineering
P.O. Box le17
Lot 259, Salak Road
Kuching, Sar,wek
Tel: 53544
MEXICO

Hewlett-Packard Mexicans,
S.A. de C.V.
Av. Perlf6rico Sur No. 6501
Tepepan, Xochlmilco
Mexico 23, D.F.
Tel: 805·676·4600
Telex: D17-74·507
Hewlett-Packard Mexicans,
SA de C.V.
Rio Volga #600
Col. Del Valle
Monterrey, N.l.
Tel: 78·32·10

Wellington

Tel: 850·09 I
Telex: NZ 31291
Northrup Instruments &
Syslems Lid.
Eden House, 44 Khyber Pass
Rd.
P.O. Box 9682, Newmarket
Auckland 1

Tel: 794·091
Northrup Instruments &
Systems Lid.
Terrace House, 4 Oxford
Terrace
P.O. Box 8388
Christchurch

Tel: 64·165
NIGERtA

The Electronics
Instrumentations ltd,
N6B/770 Oyo Road
Oluseun House
P.M.B.5402
Ibadan

Tel: 461577
Telex: 31231 TElL NG
The ElectroniCs
Instrumentations lid.
144 Agege Motor Road, Mushin
P.O. Box 481
Mushin, Lagol
NORWAY

Hewlell·Packard Norge AlS
Oslendalen 18
P.O. Box 34
1345 Oatera••
T,I: (0211711 80
Telex: 16621 hpnas n

L

Hewlen·Plckard Norge AlS
Nygaardsgalen I 14
P.O. Bo.4210
5013 Nygaardsgalen,
Bargln
Tel: 1051 2 I 97 33

QATAR
Nasser Tradllg & Conlracling
P.O. Bo. 1563
Doha
Tel: 22170
Tele.: 4439 NASSER

PANAMA
Electr6nlco Bllboa, S.A.
Aparolado 4929
Panama 5
Galla Samuel Lewis
Edillcio "Afta,. No.2
Cludad dl Panama
Tel: 64-2700
Tele.: 3483103 Curundu,
Canal Zone

ROMANIA
Hewlell·Packard
Reprezentanta
8d.n. Balcescu 16
Bueur••tl
Tel: 1580 23/13 88 85
Tele.: 10440

PIRU
Companla Eleclro MAdica S.A.
Los Flamencos 145
San Isidro Casillo 1030
Lima I
Tal: 41·4325
Telex: Pub, BOOlh 25424
SlSIORO
PAKISTAN
MuShko & Company lid.
Cosman Chambers
Abdullah Heroon Road
Karachl·3
Tel: 511027, 512927
Tolex: 2894
Mushko & Company, Lid.
10, Bazar Rd.
Seclor G·614
lalamabad
Tel: 28264
PHILIPPINES
The Onine Advanced Syslems
CorpOration
Rico House
Amorsolo cor. Herrera Str.
Legaspi Village, Makali
P.O. Bo, 1510
Metro Manila
Tel: 85·35·81, 85-34·91,
85·32·21
Telex: 3274 ONLINE
RHODESIA
Field TecMicai Sales
45 Kelvin Road Nonh
P.O. Bo, 3458
Sansbury
Tel: 705231 (5 ....sl
Telex: RH 4122
POLAND
Buo Inlormacji Technicznej
Hewlett-Packard
UI Slawki 2, 6P
PLOO·950 Warozawa
Tel: 39 59 62,3951 87
Telex: 81 24 53
PORTUGAL
Teleclra·Empresa nCnica de
Equipamenlos EI6Clricos
S.a.r.1.
Rua Rodrigo do Fonseca 103
P.O. Bo, 2531
P·Llobon 1
Tel: (19168 60 72
Telex: 12598
Medical Only
Mundinter
Inlercarnbio Mundial de
C0rn6rcio S.a.r.l.
P.O. Bo, 2761
Avenida Antonio Augusto
de Aguiar 138
P·L1lbon
Tel: 119153 213117
Telex: 16691 munler p
PUERTO RICO
Hewlell-Packard Inter·
Americas
Puerto Rico Branch Office
Calle 272,
#203 Urb. Counlry Club
Carolina 00630
Tel: (8091762·7255
Telex: 345 0514

SAUDI ARABIA
Modern Electronic
EslablishmenllHead Officel
P.O. Bo, 1228, Baghdadiah

Street
Jeddah
Tel: 27 798
Telex: 40035
Gable: ELECTA JEOOAH
Modern Electronic
EslablishmenllBranchl
P.O. Bo, 2728
Riyadh
Tel: 62596166232
Telex: 202049
Modern Eleclronic
Eslablishmenl (Branchl
P.O. Bo, 193
A~Khobar

Tel: 44678·44813
Telex: 670136
Gable: ELECTA AL·KHOBAR
SINGAPORE
Hewlett·Packard Singapore
(Ple.1 Lid.
61h Floor, Inchcape House
450·452 AIe,andra Road
P.O. Bo, 58
Alexandra POSI Office
Singapore 91 15
Tel: 631788
Telex: HPSG RS 21486
SOUTH AFRICA
Hewlett-Packard South Africa
(PlY.I, Lid.
Private Bag Wendywood,
Sandlon, Transvaal, 2144
Hewlett-Packard Centre
Daphne Slreel, Wendywood,
Sandton, 2144
Tel: 802·5111125
Telex: 8·4782
Hewleli·Packard Soulh Africa
(Ply.l, Lid.
P.O. Bo, 120
Howard Place,
Gape Province, 7450
Pine Pari< Centre, Forest Drive,
Plnelanda,
Cape PrOVince, 7405
Tel: 53·795511vu 9
Telex: 57·0006
SPAIN
Hewlett-Packard Espanola,
S.A.
Calle Jerez 3
E·Madrld 16
Tel: (114582600 (10 linesl
Telex: 23515 hpe
Hewlell·Packard Espanola S.A.
Colonia Mirasierra
Edificla Juban
clo Costa Brava, 13
Madrid 34
Hewleli·Packard Espanola,
S.A.
Milanesado 21·23
E·Sarcelona 17
Tel: (31203 6200 (5 Hnesl
Telex: 52603 hpbe e
Hewlell·Packard Espanola,
S.A.
Av Rem6n y Cojal, 1
Edificio Sevilla, planta go
E·Sevllla 5
Tel: 64 44 54/58

Hewlen· Packard Espanola S.A.
fdilicio Albia 117° B
E·Bllbao I
Tel: 23 83 06123 82 06
Hewlell·Packard Espanola S.A.
GlRamon Gordillo 1
IEnlla·1
E-Va.encla 10
Tel: 96·361.13.54/361.13.58
SRI LANKA
Melropolilan AgencieS Lid.
209/9 Union Place
Colombo 2
Tel: 35947
Tele.: 1377METROLTO CE
SUDAN
Radlson Trade
P.O. Bo, 921
Khartoum
Tel: 44048
Telex: 375

TANZANIA
Medical Only
International Aeradio (EAI,lId.
P.O. 80' 861
Dar
Salaam
Tel: 21251 E,1. 265
Telex: 41030

SURINAM
Surlel Radio Holland N.V.
GrOle Holslr. 3·5
P.O. Bo, 155
Paramaribo
Tel: 72118, 77880

THAILAND
UNIMESA Co. Lid.
Elcom Research BuHding
2538 Sukumvil Ave.
Bangchak, Bangkok
Tel: 39·32·387, 39·30·338

SWEDEN
Hewlell·Packard Sverige AB
Enighelsvlgen 3, Fack
S·I61 Bromma 20
Tel: (081730 05 50
Telex: 10721
Cable: MEASUREMENTS
Siockholm
Hewleli·Packard Sverige AB
Fr61a11sgalan 30
S-421 32 vastra
FrOlunda
Tel: (031149 09 50
Telex: 10721 via Bromma
office

TRINIDAD &
TOBAGO
CARTEL
Caribbean Telecoms ltd.
P.O. Bo, 732
69 Frederick Street
Port·ol·Spaln
Tel: 62·53068

SWITZERLAND
Hewlett·Packard (Schwezl AG
ZUrcherstrasse 20
P.O. Bo. 307
CH·8952 Schllere..
ZUrich
Tel: (011 7305240
Telex: 53933 hpag ch
Gable: HPAG CH
Hewlett·Packard (Schweizl AG
CllAleau Bloc 19
CH·1219 Le Llgnon·
Geneva
Tel: (022196 03 22
Telex: 27333 hpag ch
Cable: HEWPACKAG Geneva
SYRIA
General Electronic Inc.
N.-i Basha·Ahnal Ebn Kays
Sireel
P.O. Bo, 5781
Dam.acul
T~I: 33 24 87
Telex: 112151TIKAL
Cable: ELECTROBOR
DAMASCUS
Medical only
Sawah & Co.
Place AlmA
B.P.2308
Damaacua
Tel: 16367·19697·14288
Telex: 11304 SATACO SY
Cable: SAWAH, DAMASCUS
Suleiman Hilal EI Mlawi
P.O. Bo' 2528
Mamoun Bilar Slr..l, 56·58
Dam.Bcua
Tel: 114663
Telex: 11270
Cable: HILAL DAMASCUS
TAIWAN
Hewlell·Packard Far Easl Lid.
Taiwan Branch
Bank Tower, 5th Floor
205 Till Hau Nonh Road

477
.~

Taipei
Tel: (02) 751·04041151inesl
Hewlell·Packard Far Easl Lid.
Taiwan Branch
68·2, Chung Cheng 3rd. Road
Kaohllung
Tel: (07) 242318·Kaohsilllg
Analylical Only
San Kwang Instruments Co .•
Lid.
20 Yung Sui Road
Talpal
Tel: 3615446·914Iinesl
Tele.: 22894 SANKWANG

8.

TUNISIA
Tunisie Electronique
31 Avenue de la Liberle
Tunis
Tel: 280 144
Corema
1 ler. Av. de Canhage
Tunl.
Tel: 253 821
Telex: 12319 CABAM TN
TURKEY
TEKNIM Company Lid.
Aiza Soh Pohievi
Gaddesl No. 7
KavakUdere, Ankara
Tel: 275800
Telex: 42155 \
Teknim Com., ltd.
Barbaros Bulvari 55/12
Besikyas, latanbul
Tel: 613 546
Telex: 23540
E.M.A.
Muhendisli< Kollekl~ Sirkeli
Mediha Eidem Sokak 4116
YUksel Caddesi
Ankara
Tel: 17 56 22
Yilmaz Ozyurek
Milli Mudalaa Cad 1616
Kizilay
Ankara
Tel: 25 03 09 • 17 80 26
Telex: 42576 OZEK TR
UNITED ARAB
EMIRATES
Emilac Lid. (Head Officel
P.O. Bo, 1641
Sharjah
Tel: 35412113
Telex: 8136
Emitac lid. (Branch Office)
P.O. Bo, 2711
Abu Dhabi
Tel: 33137011
UNITED KINGDOM
Hewleli·Packard Lid.
King" Street lane
Wlnner.h, Wokingham
Berkshire RG 11 5AR
GB·England
Tel: (07341764774
Telex: 84 71 7819

Hewlett-Packard lid.
FOlJ'ier House,
257·263 High Slreel
london Colney
St. Albans, Herls
GB·England
Tel: 10727124400
Tele.: 1·8952716
Hewlell·Packard Lid.
Trafalgar House
Navigation Road
Altrlncham
Cheshire WA 14 INU
GB·Engiand
Tel: (061) 928 6422
Tele.: 668068
Hewlett-Packard Ltd.
Lygon Coun
Hereward Rise
Dudley Road
Hal••owen,
Wesl Midlands, B62 8S0
GB·England
Tel: (0211501 1221
Telex: 339105
Hewlell·Packard Lid.
Wedge House
799, London Road
Thornton Heath
SUrrey, CR4 6XL
GB·Engiand
Tel: (011684·0103/8
Telex: 946825
Hewleli·Packard Lid.
14 We~ey SI
Caatleford
Yorks WF 10 1AE
Tel: (0977) 550016
TWX: 5557335
Hewlell·Packard Lid.
Tradax House
SI. Mary's Walk
Maidenhead
Berkshire, SL6 1ST
GB·England
Hewlett·Packard Lid.
Mo~ey Road
Staplehiff
8risl0l, BS 16 40T
GB·England
Howleli·Packard Lid.
South Que.naferry
Wesl Lolhian, EH30 9TG
GB·Scolland
Tel: (031) 331 1188
Telex: 72682
UNITED STATES

ALABAMA
700 Cenlury Park
Suile 128
Blrmlnaham 35226
Tel: (2051 822·8802

-,

P.O. Bo, 4207
8290 Whllesburg Dr.
Huntsville 35802
Tel: (2051881·4591
ARIZONA
2336 E. Magnolia SI.
Phoenix 85034
Tel: 16021273·8000
2424 Easl Aragon Rd.
Tucoon 85706
Tel: (6021 273·8000
'ARKANSAS
Medical Service Only
P_O. Bo, 5646
Brady Sialion
Lilli. Rock 72215
Tel: (5011376·1844
CALIFORNIA
1579 W. Shaw Ave.
Fr.sno 93771
Tel: (2091224·0582
14JO Easl Orangelhorpe Ave.
Fullarton 92631
Tel: 17141 870·1000

5400 West Rosecrans Btvd.
P.O. 80' 92105
World Way Postal Center
Los Angel.s 90009
Tel: 1213)970-7500
TWX: 910-325-6608
3939 Lankershim Boulevard
North HOllywood 91604
Tel: (213)877-1282
TWX: 910-499-2671
3200 Hillview Av
Palo Alto, CA 94304
Tel: 1408)988-7000
646 W. Norlh Markel 8lvd.
Sacramento 95834
Tel: 1916)929-7222
9606 Aero Drive
P.O. Bo, 23333
San Diego 92123
Tel: (714) 279-3200
363 Brookhollow Dr.
Santa Ana, CA 92705
Tel: 1714)641-0977
3003 Scotl Boulevard
Santa Clara 95050
Tel: 1408)988-7000
TWX: 910-338-0518
454 Carlton Court
So. San Francisco 94080
Tel: 1415)877-0772
"Tarzana
Tel: 1213)705-3344
COLORADO
5600 DTC Parkway
Englewood 80110
Tel: 1303)771-3455
CONNECTICUT
47 Barnes Induslrial Road
Barnes Park South
Wallingford 06492
Tel: 1203)265-7801
FLORIDA
P.O. Bo, 24210
2727 N.W. 62nd Sireel
Ft. Lauderdale 33309
Tel: 1305) 973-2600
4080 Woodcock Drive # 132
Brownetl Building
Jacksonville 32207
Tel: 1904)398-0663
P.O. 80' 13910
6177 Lake Ellenor Dr.
Orlando 32809
Tel: 1305)859-2900
P.O. 80' 12826
Suile 5, Bldg. 1
Office Park North
Pensacola 32575
Tel: 1904)476-8422
110 South Hoover Blvd.
Suile 120
Tampa 33609
Tel: 1813)872-0900
GEORGIA

P.O. 80, W5005
450 Interstate North Parkway
Atlanta 30348
Tel: 1404) 955-1500
TWX: 810-766-4890
Medical Service Only
•Augusta 30903
Tel: 1404) 736-0592
P.O. 80' 2103
1172 N. DaviS Drive
Warner Robins 31098
Tel: 1912) 922-0449
HAWAII
2875 So. King Slreel
Honolulu 96826
Tel: 1808) 955-4455

ILLINOIS
211 Prospecl Rd.
Bloomington 61701
Tel: 1309)663-0383
5201 Tollview Dr.
Roiling Meadows
60008
Tel: 1312)255-9800
TWX: 910-687-2260
INDIANA
7301 Norlh Shadeland Ave.
Indianapolis 46250
Tel: 1317)842-1000
TWX: 810-260-1797
IOWA
24 15 Heinz Road
Iowa City 52240
Tel: 1319)351-1020
KENTUCKY
10170 linn Station Road
Suile 525
Louisville 40223
Tel: 1502)426-0100
LOUISIANA
P.O. Bo, 1449
3229-39 WliHams Boulevard
Kenner 70062
Tel: 1504)443-6201
MARYLAND
7121 Standard Drive
Parkway Industrial Center
Hanover 21076
Tel: 1301)796-7700
TWX: 710-862-1943
2 Choke Cherry Road
Rockville 20850
Tel: 1301) 948-6370
TWX: 710-828-9684
MASSACHUSETTS
32 Hartwell Ave.
Lexington 02173
Tel: 1617)861-8960
TWX: 710-326-6904
MICHIGAN
23855 Research Drive
Farmington Hills 48024
Tel: (313)476-6400
724 West Centre Ave.
Kalamazoo 49002
Tel: (616) 323-8362
MINNESOTA
2400 N. Prior Ave.
St. Paul 55113
Tel: (612)636-0700
MISSISSIPPI
322 N. Mart Plaza
Jackson 39206
Tel: (601) 982-9363
MISSOURI
11131 Colorado Ave.
Kansas City 64137
Tel: (816)763-8000
TWX: 910-771-2087
1024 Executive Parkway
St. Louis 63141
Tel: (314)878-0200

NEW MEXICO
P.O. 80' 11634
Station E
11300 Lomas 8Ivd., N.E.
Albuquerque 87123
Tel: (505)292-1330
TWX: 910-989-1185
156 Wyall Drive
Las Cruces 8800 1
Tel: 1505)526-2484
TWX: 910-9983-0550

TENNESSEE
a906 Kingston Pike
Knoxville 37919
Tel: 1615)691-2371
3070 Directors Row
Directors Square
Memphis 38131
Tel: 1901) 346-8370
"Nashville
Medical Service Only
Tel: 1615)244-5448

NEW YORK
6 Automation lane
Computer Park
Albany 12205
Tel: 1518)458-1550
TWX: 710-444-4961
650 Perinton Hill Office Park
Fairport 14450
Tel: 1716) 223-9950
TWX: 510-253-0092
NO.1 Pennsylvania Plaza
551h Floor
34th Street & 8th Avenue
New York 10001
Tel: 1212)971-0800
5858 Easl Molloy Road
Syracuse 13211
Tel: 1315)455-2486
1 Crossways Park West
Woodbury 11797
Tel: 1516)921-0300
TWX: 510-221-2183
Tel: 1513) 671-74DO

TEXAS
4171 North Mesa
SuiteC110
EI Paso 79902
Tel: 1915)533-3555
P.O. 80' 42816
10535 Harwin S1.
Houston 77036
Tel: 1713)776-6400
"Lubbock
Medical Service Only
Tel: 1806)799-4472
P.O. Bo, 1270
201 E. Arapaho Rd.
Richardson 75081
Tel: 1214)231-6101
205 Billy Milchell Road
San Antonio 78226
Tel: 1512)434-8241

NORTH CAROLINA
5605 Roanne Way
Greensboro 27409
Tel: (919)852-1800
OHIO
Medical/Computer Only
9920 Carver Road
Cincinnati 45242
Tel: 1513)891-9870
16500 Sprague Road
Cleveland 44130
Tel: 1216) 243-73DO
TWX: 810-423-9430
962 Crupper Ave.
Columbus 43229
Tel: (614)436-1041
330 Progress Rd.
Dayton 45449
Tel: 1513) 859-8202
OKLAHOMA
P.O. Box 32008
6301 N. Mendan Avenue
Oklahoma City 73112
Tel: (405)721-0200
9920 E. 42nd Sireel
Suite 121
Tulsa 74145
Tel: 1918)665-3300
OREGON
17890 S.W. Lower Boones
Ferry Road
Tualatin 97062
Tel: (503)620-3350

NEBRASKA
Medical Only
7101 Mercy Road
Suite 101
Omaha 68106
Tel: (402)392-0948

PENNSYLVANIA
1021 8th Avenue
King of Prussia Industrial Park
King 01 Prussia 19406
Tel: (215)265-7000
TWX: 510-660-2670

NEVADA
'Las Vegas
Tel: 1702)736-6610

111 Zeta Drive
Pittsburgh 15238
Tel: 1412)782-0400
SOUTH CAROLINA
P.O. Bo, 6442
6941-0 N. Trenholm Road
Columbia 29206
Tel: 1803)782-6493

NEW JERSEY
Crystal Brook Professional
Building
.Route 35
Eatontown 07724
Tel: 1201)542-1384
W. 120 Cenlury Rd.
Paramus 07652
Tel: 1201) 265-5000
TWX: 710-990-4951

478

UTAH
2160 Soulh 3270 Weol Sireel
Salt Lake City 84119
Tel: (801) 972-4711
VIRGINIA
P.O. Bo' 9669
2914 Hungary Spring Road
Richmond 23228
Tel: 1804)285-3431
Computer Systems/Medical
Only
Airport Executive Center
Suile 302
5700 Thurston Avenue
Virginia Beach 23455
Tel: (804)460·2471
WASHINGTON
Bellelield Office Pk.
1203 - 1141h Ave, S.E.
Bellevue 98004
Tel: 1206)454-3971
TWX: 910-443-2446
P.O. 80x 4010
Spokane 99202
Tel: 1509) 535·0864
'WEST VIRGINIA
Medical/Analytical Only
4604 Mac Corkle Ave" S.E.
Charl.ston 25304
Tel: 1304) 925-0492
WISCONSIN
150 Soulh Sunny Slope Road
Brooklleld 53005
Tel: 1414)784-8800

FOR U.S. AREAS
NOT LISTED:
Contact the regional office
nearest you:
Atlanta, Georgia .. North
Holly-wOOd, California.
Rockville, Maryland
Roiling Meadows, Illinois.
Their complele addresses
are listed above.
USSR
Hewlell·Packard
Representative Office
USSR
Pokrovsky Boulevard
4117-kw 12
Moscow 101000
Tel: 294.20~4
Telex: 7825 hewpak su

YUGOSLAVIA
Iskra Commerce, n.sol.o.
Zaslopstvo Hewlett·Packard
Obilicev Venac 26
YU 11000 Beograd
Tel: 636-955
Telex: 11530
Iskra Commerce, n.sol.o
Zastopstvo Hewlett·Packard
Miklosiceva 381V1I
YU-61000 Ljubljana
Tel: 321-674, 315-879
Telex: 31583
URUGUAY
Pablo Ferrando S.A.C.el.
Avenida Italia 2877
Casilla de Correo 370
Montevideo
Tel: 40-3102
Telex: 702 Public Booth
Para Pablo Ferrando
VENEZUELA
Hewletl·Packard de Venezuela
C.A.
P.O. Bo, 50933
Caracas 105
Los Ruices Norte
3a Transversal
Edificio Segre
Caracas 107
Tel: 239-4133120 lines)
Telex: 25146 HEWPACK
ZAMBIA
R.J. Tilbury IZambia) Lid.
P.O. 80' 2792
Lusaka
Tel: 76793
MEDITERRANEAN AND
MIDDLE EAST
COUNTRIES NOT
SHOWN, PLEASE
CONTACT:
Hewlett·Packard SA
Mediterranean and Middle East
Operations
35, Kolokolroni Street
Platia Kefallariou
GR·Kifissia-Athenl, Greece
Tel: 8080359/429
Telex: 21-6588
Cable: HEWPACKSA Alhens
SOCIALIST
COUNTRIES NOT
SHOWN, PLEASE
CONTACT:
Hewlett·Packard GeS.m.b,tl
Handelskai 52
P.O. Bo' 7
A·120S Vienna, Austria
Tel: 10222)35 1621 1027
Cable: HEWPAK Vienna
Tel,,: 75923 hewpak a
OTHER
AREAS
NOT
LISTED, CONTACT:
Hewlett·Packard
Intercontinental
3495 Deer Creek Road
Palo Alto, California 94304
Tel: 1415)856-1501
TWX: 910-373·1267
Cable: HEWPACK Palo Alto
Tel,,: 034-8300, 034-8493
Hewlell-Packard SA
7, rue du Bois·du·lan
P.O. 80'
CH-1217 Meyrin 2 - Ganeva
Switzerland
Tel: 1022) 82 70 DO
Cable: HEWPACKSA Geneva
Tel" 22486

'Servlce Only
2-15-80

Fli;-

HEWLETT

~~ PACKARD

For more information call your local HP Sales Office or East 301 9486370, Midwest 1312 255-9800, South 404 955-1500, West 213 9707500. Or write: Hewlett-Packard Components, 640 Page Mill Road,
Palo Alto, California 94304. In Europe, Hewlett-Packard GmbH, P.O.
Box 250, Herrenberger Str. 110, 0-7030 Boeblingen, West Germany.
In Japan, YHP, 3-29-21, Takaido-Higashi, Suginami-Ku, Tokyo 168.
Printed in U.S.A.

Revised from 5953-0400
Data Subject to Change

5953-0429 D
April 1980
Source Exif Data: 
File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37
Create Date                     : 2013:08:03 13:53:58-08:00
Modify Date                     : 2013:08:03 13:50:16-07:00
Metadata Date                   : 2013:08:03 13:50:16-07:00
Producer                        : Adobe Acrobat 9.55 Paper Capture Plug-in
Format                          : application/pdf
Document ID                     : uuid:4265b2a1-ded1-ba4d-9c3c-646a17531f5d
Instance ID                     : uuid:fd3a4cb7-68b3-d049-bc80-dc5cf7603414
Page Layout                     : SinglePage
Page Mode                       : UseNone
Page Count                      : 498
EXIF Metadata provided by EXIF.tools

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