1980_Plessey_Radar_and_Radio_Communications_IC_Handbook 1980 Plessey Radar And Radio Communications IC Handbook

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Radar & Radio
Communications
ICHandbook

.Plessey

Semiconductors

RADAR & RADIO
COMMUNICATIONS
IC HANDBOOK

JUNE 1980

_
Plessey
. . Semiconductors
1641 Kaiser Avenue,
Irvine, CA. 92714
1

This publication is issued to provide outline information only and (unless specifically agreed to the contrary by
the Company in writing) is not to form part of any order or contract or be regarded as a representation relating to
the products Or services concerned. We reserve the rignt to alter without notice the specification, design. price or
conditions of supply of any product or service.

2

3

4

Contents
1 - PRODUCT RANGE INFORMATION

9-26

2 - RADIO APPLICATION NOTES
Section 1 SL600/1600 Circuit Description
2 AM Receiver- _ . . . . .
3 SSB Transceiver . . . . . . . . .
4 Multimode Transceiver . . . . .
527 MHz AM/SSB Transceiver.
6 SL6000 Circuit Description and Applications.
7 High Speed Dividers and Characteristics ..
8 Synthesizer System . . . . . . . . . . . . . . . .

27 -46
47 - 51
52 - 63
64 -82
83 - 86
· .87 - 102
.103-117
· 119· 136

3 - RADAR APPLICATION NOTES
1 Plessey I Cs for radar I Fs ..
· 138 - 142
2 A wide dynamic range preamplifier.143 - 148
3 A 120MHz log using SL1521s . . . .
.149 - 154
4 A Swept Gain I F Strip and Detector.
. . 155 - 160
5 Low Noise Amplifier . . . . . . . . .
. . . . . . . . . . . 161-164
. . . . . . . . . . . 165 - 174
6 Low Cost I F Strip . . . . . . . . . . .
7 Digital Signal Processing Apliications . . . . . . . . . . . . . . . . . . . . . . 175 - 207

TECHNICAL DATA.

.209 - 426

PACKAGES . . . . . .

.427 - 435

PLESSEY SEMICONDUCTORS WORLD WIDE . . . . . . . . . . . . . . . . . . . . . . . . . 437

5

PRODUCT INDEX
MODULATORS
SL355C
SL1496C
SL1596C

4-Transistor modulator/demodulator __
Double balanced modulator/demodulator _
Double balanced modulator/demodulator.

219
333
333

LINEAR RF AMPLIFIERS
SL501A&B
SL502A&B
SL503A&B
SL510C
SL511C
SL541A&B
SL541C
SL550C&D
SL560C
SL561C
SL1550C

Linear wideband amplifier _
Linear wideband amplifier . . . .
Linear wideband amplifier . . . .
DC-24MHz R F dectector/video amplifier
DC-14MHz RF dectector/video amplifier
High slew rate - operational amp . . . . . .
High speed video amplifier . . . . . . . . . .
Low noise amp. with external gain control
300MHz low noise amplifier . . . . . . . . .
Low noise preamplifier . . . . . . . . . . . .
Low noise amp. with external gain control

229
229
229
235
235
257
261
265
271
275
341

PHASE-LOCKED LOOP CI RCUITS
SL650B&C
SL651B&C
SL652C

303
303
307

Modulator/PLL ..
Modulator/PLL ..
Modulator/PLL ..

LIMITING WIDEBAND AMPLIFIERS
SL521A,B&C
SL525C
SL530C
SL531C
SL532C
SL 1521A,B,C
SL1522C
SL1523C

Wideband log, amplifier ..
Wideband log. If strip amplifier.
True log. amplifier
True log. amplifier . . . . . .
True log. amplifier . . . . . .
200M Hz wideband amplifier.
200MHz wideband amplifier.
200MHz wideband amplifier.

MATCHED NPN TRANSISTORS & ARRAYS
SL301K&L
SL303L
SL360C
SL362C
SI2363C
SL2364C
SL3045C
SL3046C
SL3081D
SL3082D
SL3083D
SL3127C
SL3145C
SL3146A&C
SL3183A&C

6

Dual NPN transistors . . . . . . .
Matched pair + tall transistor ..
2.5CHz matched transistor pair.
Low noise transistor pair . . . . .
High performance transistor array
High performance transistor array
General purpose transistor array .
General purpose transistor array .
High current, common emitter array ..
High current, common emitter array ..
High current, five transistor array ..
High frequency transistor array . . . . .
2.5GHz transistor array . . .
High voltage transistor array.
High voltage transistor array.

239
243
247
251
255
337
337
337

......
......

211
215
223
225
369
369
371
371
375
375
377
379
383
385
385

RADIO COMMUNICATIONS CIRCUITS
SL610C
R F amplifier. . . . . . . . . . . . . . . . . .
RF amplifier . . . . . . . . . . . . . . . . . . . . . . . . . .
SL611C
I F amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SL612C
SL613C
Limited wideband amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . .
VOGAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SL620C
AGC generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
SL621C
AF amp./VOGAD/sidetone . . . . . . . . . . . . . . . . . . . . . . . . . . .
SL622C
AM det.iAGC amp./SSB demodulator . . . . . . . . . . . . . . . . . . . . .
SL623C
Multimode detector . . . . . . . . . . . . . . . . . . . . . . . . . .
SL624C
AF amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SL630C
Double-balanced modulator . . . . . . . . . . . . . . . . . . . . .
SL640C
Receiver mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SL641C
RF/IF amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SL 1610C
SL1611C
RF/IF amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RF/IF amplifier . . . . . . . .
SL1612C
Limiting amplifier/detector .
SL1613C
AG C generator . . . . . . . .
SL1620C
AGC generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SL1621C
AM detector, AGC amplifier and SSb demod . . . . . . . . . . . . . . . . . .
SL1623C
AM dectector & AGC amplifier . . . . . . . . . . . . . . . . . . . . . . . . .
SL1625C
Audio amplifier and VOGAD . . . . . . . . . . . . . . . . . . . . . . . . . .
SL1626C
SL1630C
Microphone/headphone amplifier . . . . . . . . . . . . . . . . . . . . . . . .
Double balanced modulator . . . . . . . . . . . . . . . . . . . . . . . . . . .
SL 1640C
Double balanced modulator . . . . . . . . . . . . . . . . . . . . . . . . . . .
SL1641C
Gain controlled preamplifier . . . . . . . . . . . . . . . . . . . . . . . . . . .
SL6270C
VOGAD transmit circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SL6290C
SL6310C
Switchable audio amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High level mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SL6440C
SL6640C
Low power IF/AF circuit for narrow band FM . . . . . . . . . . . . . . . .
Low power IF/AF circuit for narrow band FM . . . . . . . . . . . . . . . .
SL6550C
Low power IF/AF PLL circuit for narrow band FM . . . . . . . . . . . . .
SL6600C
I F amplifier and AM detector . . . . . . . . . . . . . . . . . . . . . . . . . .
SL6700C
TELEPHONE COMMUNICATIONS CIRCUITS
200M Hz wideband amplifier.
SL1030C

279
279
279
283
285
285
289
291
293
295
299
299
345
345
345
349
351
351
355
357
359
361
365
389
389
393
397
401
311
311
407
411

. . . . . . . . . . 319

THERMAL IMAGING CIRCUITS
Low noise preamplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
SL1202C
Low noise preamplifier ..
325
SL1203C
Low noise preamplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
SL1205C
SPECIAL FUNCTIONS
Crystal oscillator maintaining circuit . . . . . . . . . . . . . . . . . . . . . . 315
SL680C
Crystal oscillator maintaining circuit . . . . . . . . . . . . . . . . . . . . . . 315
SL1680C
DATA COVERSION PRODUCTS
SP9685
Ultra fast comparator . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . 415
SP9687
Ultra fast dual comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
High speed comarator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
SP9750

7

8

PRODUCT RANGE
. INFORMATION

9

10

Building Block Ie's
Plessey integrated circuits are on the leading edge of
technology without pushing the ragged edge of capability.
We developed the first 2 GHz counter. And a
family of prescalers and controllers for your TV, radio
and instrumentation frequency synthesizers.
We have a monolithic 1 GHz amplifier. And a
complete array of complex integrated function blocks for
radar signal processing and radio communications.
We can supply data conversion devices with propagation delays of just 2V2 nanoseconds.
And a range of MNOS logic that stores data for a
year when you remove the power, yet uses only standard
supplies and is fully TTL/CMOS-compatible.
To develop this edge, we developed our own
processes, both bipolar and MOS. The processes were
designed for quality and repeatability,then applied to our
high volume lines. Most of our IC's are available screened
to MIL-STD-883B, and our quality levels exceed the
most stringent military, TV and automotive
requirements.
Millions of Plessey complex function building block
IC's are being used in TV sets and car radios; CATV,
navigation and radar systems; frequency synthesizers
and telecommunications equipment.
Our global scope of operations, our high volume
manufacturing facilities, our proprietary processes ensure
that we will continue to deliver state-of-the-art technology
and reliability in IC devices at the appropriate prices and
in the required volumes. Day after day. Week after
week. Year after year.

Plessey Semiconductors
1641 Kaiser Avenue, Irvine, CA 92714. (714) 540-9979

11

Radar Signal Processing
Since the perfonnance of a radar receiver
is critically dependent on the performance
of its I.F. strip, we offer a range of "building block" IC's that can be used in systems
with different perfonnance requirements
and configurations.
The logarithmic I.F. strip shown is an
example of a low cost, high perfonnance
strip fabricated with Plessey IC's. It uses
only five devices and a single interstage
filter to achieve a logging range of 90 dB,
± 1 dB accuracy, -90 dBm tangential
sensitivity and a video rise time of

I.F.
INPUT

•

minimum of external components (one
capacitor, one resistor per stage), yet has
a band-width of 500 MHz, a dynamic
range of 70 dB and has a phase shift of
only ±3° over its entire range. As with
most of our other devices, it operates over
the full MlL-temp range and is available
screened to MlL-STD-883.
The chart summarizes our Radar Signal
Processing IC's. Whether you're working
with radar and ECM, weapons control or
navigation and guidance systems, our IC's
are a simpler, less expensive, more flexible alternative to whatever you're
using now for any I.F. strip up to
160 MHz.
For more details, please use the
postage-paid reply card at the back
of this book to order our RADAR
AND RADIO COMMUNICATIONS IC HANDBOOK, or
contact your nearest Plessey
Semiconductors representative.
VIDEO

OUTPUT

20 ns or less.
Three other Plessey IC's
complete the system simply
and economically. The AGe
able S11550 on the front end
improves noise figure, dynamic range and sensitivity.
The SL541 lets you vary video
output levels, with on-chip
compensation making it easy
to use. And the SL560 is a
"gain block" that replaces
your hybrid and discrete
amplifiers, usually with no
external components.
Another advanced system
function block is the Plessey
SL531 True Log Amplifier. A
6-stage log strip requires a

PLESSEY IC'S FOR RADAR I.P'S
Wideband Amplifiers for Successive Detection Log Strips
SL521 30 to 60 MHz center frequency, 12 dB gain.
SL523 Dual SL521 (series).
S11521 60 to 120 MHz center frequency, 12 dB gain.
S11522 Dual SLI521 (parallel).
SLI523 Dual SLI521 (series).
Low Phase Shift Amplifiers
SL531

True log I.F. amplifier, 10-200 MHz, ±0.5D /IO dB max
phase shift.
SL532 400 MHz bandwidth limiting amplifier, 10 phase shift
max. when overdriven 12 dB.
Linear Amplifiers
SL550

microwave mixers.
S11550 320 MHz bandwidth version of SL550.
SL560 300 MHz bandwidth, 10 to 40 dB gain, 1.8 dB noise
figure drives 50 ohm loads, low power consumption.
Video Amplifiers and Delectors
SL510
SL511
SL541

12

125 MHz bandwidth, 40 dB gain, 25 dB swept gain
control range, 1.8 dB noise figure, interfaces to

Detector (DC to 100 MHz) and video amplifier (DC to
24 MHz) may be used separately, 11 dB incremenlal
gain 28 dB dynamic range.
Similar to SL510 with DC to 14 MHz video amplifier,
16 dB incremenlal gain.
High speed lOP amp configuration, 175 VII'S slew
rate 50 ns seliling time, slable 7() dB gain, 50 ns
recovery from overload.

Radio Communications
peak deviation. The SL6600 can be used
at I.F. frequencies up to 50 MHz, with
deviations up to 10 kHz.
r------------------,
If any of the Plessey devices appear interesting, use the postage·
paid reply card at the back of this
book to order our RADAR AND
RADIO COMMUNICATIONS IC
HANDBOOK. The Handbook in·
cludes full details on our integrated
circuits, along with a number of ap·
plications circuits and design tips
that will help you get the maximum
system benefits from Plessey
products.
Or if your need is more urgent,
contact your nearest Plessey Semiconductors representative.
in applications that range from
commercial communications
PLESSEY RADIO Ie's
Amplifie~
to military manpack radios.
Sl610 Sl!610 140 MHz bandwidth, 20 dB gain, 50 dB AGe
Using our bipolar Process I,
range, low 4 dB N.F.. low distortion.
the Plessey SL600 Series
Sl611 Sl!611 100 MHz bandwidth, 26 dB gain, sim. to Sl61O.
Sl612 Sl!612 15 MHz bandwidth, 34 dB gain, 70 dB AGe
(hermetic) and SL1600 Series
range, 20 mW power consumption.
(plastic DIP) feature a high
Sl613
145 MHz bandwidth, 12 dB gain, limiting
amp/detector.
degree of integration, low
Mixers
power consumption and exSl640 Sl!640 Double balanced modulator eliminates diode
ceptional system design flexrings up to 75 MHz, standby power 75 mWtypical.
ibilityfor I.F.'s up to 10.7 MHz.
Detectors and AGe Generators
Our SL6000 Series uses our
Sl620 Sl!620 AGe with VOGAD (Voice Operated Gain
Adjusting Device).
bipolar Process III to extend
Sl621 Sll621 AGe from detected audio.
our building block concept
Sl623 Sl!623 AM SSB detector and AGe from carrier.
Sl!625 AM detector and AGe from carrier.
even further. Devices all feaSl624
AM/FM/SSB/CW detector with audio amplifier.
ture advanced circuit design
Audio Amplifiers
techniques that permit higher
Sl622
Microphone amp. with VOGAD and sidetone amp.
levels of integration, lower
Sl630 Sl!630 250 mW microphone/headphone amplifier.
I.F. Amplifiers/Detectors
power consumption and
Sl6600
FM double conversions with Pll detector.
exceptional performance.
Sl6640
FM single conversion, audio stage (10.7 MHz).
Typical is our SL6600, a
Sl6650
FM single conversion (10.7 MHz).
Sl6690
FM single conversion, low power for pagers
monolithic IC that contains a
(455 kHz).
complete IF amplifier, deSl6700
AM double conversion.
tector, phase locked loop and
Audio Amplifiers
Sl6270
Microphone amplifier with AGe.
squelch control. Power conSl6290 Sl6270 with speech clipper, buffer and relay driver.
sumption is a meager 1.5 rnA
Sl6310
Switchable audio amplifier (400 mW/9V/8 ohms).
at 6 V, SIN ratio is 50 dB,
Sl6440
High·level mixer.
dynamic range is 120 dB and
THD is just 1.3% for 5 kHz
Our comprehensive line of radio system
function blocks is cutting costs, increasing
reliability and reducing the size of systems

13

R.EHybrids
To enhance your systems even further, we have established an R. F_ hybrid manufacturing facility in our Irvine,
California, U_S.A. headquarters.
For small production quantities or extremely complex
functions, our hybrid capabilities can save you time and
money while improving your system performance, reducing system size and increasing system reliability. We
can help with your I.F. strips, instrumentation front ends,
synthesizer subsystems, high speed A-to-D and D-to-A
converters and other complex high-frequency functions.
They can be fabricated to MIL-STD-883 using thick
and thin film techniques, using our own integrated circuits in combination with discrete transistors, diodes and
other components.
Our IC functions represent the state-of-the-art in high
frequency integration, with fts as high as 5 GHz. The
chips are backed by an in-depth in-house systems knowledge that encompasses radar, radio communications, telecommunications analog and digital conversion, frequency
synthesis and a broad range of applications experience.
We can work to your prints, or we can design a full system based on your "black box" specifications. For more
information, please contact: Plessey Semiconductors,
1641 Kaiser Avenue, Irvine CA 92714, (714) 540-9979.

14

15

Frequency Synthesis
Plessey's Ie's offer a quick and easy way to lower
synthesizer costs while increasing loop response and
channel spacing all the way from dc through the HF,
VHF, UHF, TACAN and satellite communications bands.
Our single-modulus prescalers operate at frequencies
all the way up to 1.8 GHz. They feature self-biasing clock
inputs, TTL/CMOS-compatibility and all guaranteed to
operate to at least the frequencies shown, most of them
over the temperaturerange from -55°C to + 125°C.
Our 2-modulus and 4-modulus dividers expand your
system flexibility and allow even tighter channel spacing.
All of them provide low power consumption, low propagation delay and ECL-compatibility.
To simplify your systems even further, we also offer
highly integrated control chips. Our NJ8811, for example,
includes a crystal oscillator maintaining circuit, a programmable reference divider, a programmable divider to
control the four-modulus prescaler and a high performance
phase/frequency comparator so that you can phase lock
your synthesizer to a crystal with none of the usual headaches and hassles.
We've put together a FREQUENCY SYNTHESIZER
IC HANDBOOK that details all of the Plessey Ie's and
includes a number of applications circuits, practical
examples of how Plessey integrated circuits can simplify
your designs and improve system performance.
For your copy of the Handbook, please use the postagepaid reply card at the back of this book, or contact your
nearest Plessey Semiconductors representative.

Reference
Oscillator

Charge
Phase
Pump &
Comparator Filter

~

NP

Program Inputs

16

Frequency (MHz)

o

100 290 300 400

500

600

700 890 990 10,00 1100 12,00 1300 14p60 volts
BV DSS >60 volts

~o=4 to 12 fJ.NV'

V T (MNOS)= Electrically
alterable between 0 and
-16 volts typo

CUSTOM DESIGNS

MN9000 SERIES

Vi- = >20 volts

24

CUSTOM DESIGNS.
AUTOMOTIVE AND
MICROCEll

TELECOMMUNICATIONS
SYNTHESIZER CONTROLLERS
TY SYNTHESIZERS

Plessey Bipolar Processes
Bipolar Process I is a conventional
buried + N layer diffusion process with
f t =600 MHz and other characteristics
similar to industry-standard processes.
Applications range from high reliability
military devices to high volume consumer products.
Process Variant
Application

BVCBO 0! IOIIA
BVEBO @lOflA
lVCEO
VCE (SAT) @
IB=lmA,
IC=lOmA
hFE@ IC=SmA,
VCE=5V
IT @ IC=5mA,
VCE=5V

D

A

B
Non

G

General
Purpose
20V min.

Saturating
Logic

Saturating

S.3V to
S.BSV

lOV min.
S.ISV min.

Linear
Logic
Consumer
lOV min. 4SV min.
S.ISV min. 6.BVto
7.4V
8Vmin.
20V min.

12Vmin.

8Vmin.

O.43V

O.32V

O.43V

0.6V

max.

max.

max.

40 to 200

50 min.

max.
50 min.

500
MHz

500

500

3S0

MHz min.

MHz min.

MHz min.

SO to 200

Bipolar High Voltage (HVI Process is

a variant of Process I that yields an LVeeo
greater than 45 volts. Doping levels can
be controlled and an extra diffusion used
to fabricate a buried avalanche diode with
a 40 V breakdown for absorbing powerful
noise transients without being destroyed.
Process Variant

BVCBO @ lOflA
BVEBO @ IOflA
lVCEO
VCE (SAT)@ IB=lmA,
IC=lOmA

CA
BOV min.
7.2V to B.OV
45V min.
O.4V max.

hFE@ IC=5mA

VCE=SV,
IT. @ IC=5mA, VCE=5V

BO to 300

2S0 MHz min.

Bipolar Process III uses very shallow
diffusion and extremely narrow spacing
for high frequency integrated circuits with
unusually low power consumption and
high packing densities. An f t of 2.5 GHz
allows us to routinely produce analog
amplifiers with bandwidths as high as
300 MHz and low power dividers and
prescalers that operate at frequencies up
to 1.2 GHz. Process variants allow us to
produce devices with an extended [3,
higher breakdovvn voltages and very
small geometries.
Process Variant
Application

BVCBO @ 1O,IA
BVEBO @ IOflA
lVCEO
VCE (SAT) 0! IB=lmA,
IC=lOmA
hFE @ IC=SmA, VCE=2V
IT @ IC=SmA, VCE=2V

WE
Digital
lOV min.
S.IV to S.8V
7V min.

O.SV max.
40 to 200
I.B GHz

Bipolar Process 3V is an extension
of our Process Ill. Ion implantation and
washed emitters have given the process
an ft~6.5 GHz, allowing us to produce
dividers working at 2 GHz, logic gates
with delays of less than 500 picoseconds
and linear amplifiers at 1 GHz.
Process Variant

Application
BVCBO @ IOflA
BVEBO @ IOflA
lVCEO@ SmA
VCE(SAT) @ IB=lmA,
IC=lOmA
hFE@ IC=IOmA, VCE=SV
IT @ IC=SmA, VCE=2V

wv

Digital
8V min.

3.0V to S.OV
6V min.
O.SV max.

40 to 120
6.S GHz

25

Testing and Quality Control
A major thrust of our development
work is to ensure that our processes will
routinely produce reliable devices. Our
Process III has a projected MTBF of
400,000 hours while our Process I is
even better.
Our facilities include the latest test
equipment (such as the Macrodata MD50l,
Teradyne }324 and Fairchild Sentry VII
and Sentinel) to allow us to perform all the
necessary functional and parametric test·
ing in· house. We have an internal capability
to provide specific applications-oriented

screening, and most Plessey Ie's are available screened to MIL-STD-883 and other
international specifications. Our quality
levels exceed the most stringent military,
TV and automotive requirements as a
matter of course.
But the best proof of all these claims
is our products themselves. After you've
reviewed the products that could help you
with your systems, use the postage-paid
reply card or contact your nearest Plessey
representative for complete details.

ASSEMBLY OF INTEGRATED CIRCUITS
QUALITY ASSURANCE

o
D
<>

26

KEY
PROCESS OPERATION

IN·lINE INSPEcnON

MONITOR OR QUALITY
CHECK

, RADIO
APPLICATION
NOTES

27

Radio Linear Circuits
INTRODUCTION TO SL600 AND SL1600 SERIES
Plessey Semiconductors originally developed the SL600 series for use in
military SSB systems. For such applications, hermetic packages and fulltemperature operation are necessary: the SL600 series devices meet such
specifications. As the range expanded, requirements arose for less expensive
versions of SL600 devices and the SL 1600 series was introduced. The SL 1600
series consists of the same chips as are used in the SL600 series but packaged
in plastic DIL packages (mostly 8-lead minidips) tested to less stringent
specifications, and supplied with a -30 C to + 70°C temperature specification.
In a few cases some of the pins present in the SL600 devices are omitted in the
SL 1600 devices in order to allow a chip previously supplied in a 10-lead TO-5
to be encapsulated in an 3-lead minidip.
SL600 and SL 1600 type numbers are used in section headings but to avoid
tedious repetition, only the SL600 type numbers will be used in the text
unless there are significant differences between the SL600 and SL 1600
devices. Pin numbers generally refer to both types; in cases where pin
numbers differ, the pin numbers for the SL 1600 device is given in brackets,
e.g. Pin 6(7).
D

SL600/1600 PRODUCT RANGE

28

AMPLIFIERS

SL610
SL611
SL612

SL1610 140MHz,2OdB
SL 1611 100MHz, 26dB
SL 1612 15MHz,34dB

MIXERS

SL640
SL641

SL1640
SL1641

DETECTORS
AND
AGC
GENERATORS

SL621
SL623

SL 1621 AGC from detected audio
SL 1623 AMSSB detector and AGC from carrier
SL1625 AM detector and AGC from carrier

AUDIO

SL630

SL1630 200mW headphone amplifier

SL610C, SL611C,SL612C,
SL1610C, SL1611C & SL1612C
RF/IF amplifiers
The SL610C, SL611C and SL612C integrated RF amplifiers are similar
circuits, having typical voltage gains of 10, 20 and 50 and upper 3dB gain
points at 140MHz, 100MHz and 15MHz respectively. The first two draw a
supply current of about 15mA at 6V and have some 50dB AGC range while
the SL612C draws 3.5mA and has 70dB of AGC. All three are intended to use
with +6V supplies and have internal decoupling. They will drive an output
signal of about 1V rms.
The cross-modulation of the circuits is 40dB down on signal at lV rms
output with no AGC, and at 250mV rms input with full AGC. The input and
output admittances of the circuits are not greatly affected by AGC level.

CIRCUIT APPLICATIONS
There are seven connections to each circuit: an input, an input bias point,
an AGC input, the output, the positive supply pin and two earths - for input
and output respectively.
The positive supply should be 6V, but the devices will function at supplies
of up to 9V. Since internal HF supply decoupling is incorporated a certain
amount of HF ripple can be tolerated in the supply. LF ripple should be kept
down as it can cause intermodulation especially at large HF signal
levels - and 10mV rms of LF ripple should be considered a maximum.
The AGC characteristic is shown in Fig. 1. It is temperature dependent, so
that while a potentiometer may be used to provide a gain control voltage the
gain so defined will not be temperature stable to better than ± 2dB. The
AGC terminal will normally draw about 200 microamps at 5V - in some
SL610C and SL611C devices this may be as high as 600 microamps.
There are two earth connections: pin 4 is the input earth and pin 8 the
output earth. When several devices are cascaded pin 8 of one stage and pin 4
of the next should have a common earth point - also high common earth
impedances to pin 4 and pin 8 of the same device should be avoided. Fig.
2a shows a circuit where common earth impedance could cause instability
and Fig. 2b shows one where the input and output signals have correct point
earthing. If extra supply decoupling is used the capacitor should ground to
the output earth point. The can should be separately earthed in applications
at VHF or in the presence of a large RF field.
The input bias point (pin 6) is normally connected directly to the input(pin 5)
and the signal applied through a capacitor but occasionally, when the signal
is obtained from a tap on a coil, the arrangement in Fig. 2b may be used to
give slightly improved noise performance. CD is a decoupling capacitor. The
SL610/611 noise figure is approximately 4dB at 300 ohms source impedance
and 6dB at 50 ohms and at 2.5 kilohms the noise figure for the SL612 is 3dB at
800 ohms source impedance.

29

..... ......:

,,
~,

-10

'\

-20

i\.

\

Z -30



~
...J

LOAO
RESISTANCE

1\
SL 612C

----U-

7

5

SL64 1C

+v

:!
!l

R

3

LOCAL OSC

liP

LOCAL OSC liP

,",-,lOOmV rrr.s

"",lOOmV rms

(a) SL641C with LC IF filter

(b) SL641C with crystal filter
FILTER

(c) SL640C with crystal filter
Fig. 9 SL640/41C receiver mixer circuits

35

150MHz with reduced performance. To use them at frequencies below 100Hz
precautions must be taken to prevent leakage in the input coupling capacitor
from altering the device bias.
Some applications of the SL640C and SL641C are shown in Figs. 9 and
10 Power, decoupling, and earth connections are not shown.
Fig. 9a shows the SL641C used as a receiver mixer driving a wound IF
coil. Fig. 9b shows it driving a crystal filter. Rand C must be selected to
match the filter. If R is less than BOO ohms it may be connected to the +6V
line supplying power to the SL641C; if it is between BOO ohms and 1.B kilohms
it should be connected to +9V (while the SL641C supply must remain at
+6V). If R is greater than 1.B kilohms the circuit in Fig. 9 b is unsuitable and
the SL640C circuit illustrated in Fig. 9 c should be used.
The SL640C and SL641C have a noise figure of about 10dB at 100 ohms
source impedance. When used as receiver mixers they have better than
-40dB intermodulation products so long as unwanted signals do not exceed
30mV rms. Thus, either can be used as a receiver mixer at HF without an RF
amplifier since atmospheric noise will far exceed device noise at these
frequencies if the antenna is reasonably good. If an SL610C RF amplifier is
used the intermodulation threshold will be reduced to 3mV rms (since the
SL610C has a gain of 10). The SL640/41 is then less attractive as a mixer and a
diode ring mixer should be used.
Fig. 10a shows the SL640C used as an SSB detector. The capacitor connected to output pin 5 decouples the sum frequency If1 +-121, while the audio
difference frequency If1 - 121 is taken from pin 6. The phase comparator
shown in Fig. 10b is more useful - it may be used as a detector for phase
modulated signals or as a comparator in phase-locking systems such as
frequency synthesisers.

SIGNAL liP
LIMITED AT ~

~'
SL640C
alP

200mV rms
J

1k

t

REF. liP

BFa

200mV rms

,,-,IOOmV rms

(a) SL640C SSB detector

(b) SL640C phase comparator

r-------~--------~---t6V

R2
10k

CARRIER
liP

Rl
10k

-+--t---t

(c) Signal and carrier leak adjustment
Fig. 10 SL640141C detector circuits

36

Signal and carrier leak may be reduced by altering the bias on the carrier
and signal input pins, as shown in Fig. 10c. With carrier but no signal R1 is
adjusted for minimum carrier leak. A similar network is connected to the
carrier input and with signal and carrier present, signal leak is minimised by
means of R2.
Fig.11a shows the SL640C or SL641C used as a sideband generator. Both
sidebands are produced so that if a single sideband is required it must be
obtained by subsequent filtering (Fig. 11b). If pin 2 is earthed by a resistor of
about 15 kilohms (its actual value may need to be selected) the device's
carrier leak is increased to a point where the DSB signal becomes AM.
This is useful where it is desired to select sideband or AM. In the circuit
shown in Fig. 11c a single sideband only is produced. It is important that both
the audio and carrier reference and quadrature signals should be accurately
90 degrees out of phase. The amplitude of one phase of audio should be
adjusted to obtain maximum second sideband rejection.
If the carrier reference is connected to input A, and the carrier quadrature
to input B, LSB output results. If the carrier quadrature is connected to input A,
and reference to input B, USB output results.

DSB

AUDIO IIP----3>-I

alP

85mVrms

CARRIER liP
200mV rms

CARRIER liP
200mVrms

(a) DSB

(b) SSB

T.

CARRIER liP
........ 200mV EACH
(SEE TEXT(

SSB

alP

J:

(e) SSB
Fig. 11 Sideband generators

37

SL621C & SL1621C
AGe generators
The SL621C is an audio-operated AGC generator designed for use with the
SL61 0/11 /12 RF amplifiers in SSB receivers. i
An ideal single sideband AGC generator must set the AGC rapidly when a
new signal appears and follow a rising or fading signal but, if the signal
disappears altogether (as in pauses in speech), retain the AGC level until
the signal recommences. If the signal remains absent for more than a preset
time, however, the system should rapidly revert to full gain. The SL621C will
perform these functions and will also produce short-lived pulses of AGC
to suppress noise bursts.

CIRCUIT DESCRIPTION
The operation of the circuit is described with reference to Fig. 12, which
also illustrates the dynamic response of a system controlled by an SL621C
AGC generator.
The SL621C consists of an input AF amplifier, TR1-TR4, coupled to a DC
output amplifier, TR16-TR19, by means of a voltage back-off circuit, TR5, and
two detectors, TR14 and TR15, having short and long. rise and fall time
constants respectively.
An audio signal applied to the input rapidly establishes an AGC level, via
TR14, in time fl. Meanwhile the long time constant detector output (TR15) will
rise and after f3 will control the output because this detector is the more
sensitive. If the signals at the SL621C input are greater than approximately
4mV rms they will actuated the trigger circuits TR6-TR8 whose output pulses
will provide a discharge current for C2 via TR10, TR13.
By this means the voltage on C2 can decay at a maximum rate which
corresponds to a rise in receiver gain of 20dB/sec. Therefore the. AGC system
will smooJhly follow signals which are fading at this rate or slower. However,
should the receiver input signals fade faster than this, or disappear completely
as in pauses in speech, then the input to the AGC generator will drop below
the 4mV rms threshold and the trigger will cease to operate. As C2 then has
no discharge path, it will hold its charge (and hence the output AGC level)
at the last attained value. The output of the short time constant detector
(TR14) falls to zero in time 12 after the disappearance of the signal.
The trigger pulses also charge C3 via TR9, thus holding off TR12 via TR11.
When the pulses cease, C3 discharges and after t5 turns on TR12, rapidly
discharging C2 (in time t4) thus restoring full receiver gain. The hold time,
t5, is approximately one second with C3= 100 microfarads. If signals reappear
during t5, then C3 will re-charge and normal operation will continue. The
C3 re-charge time is made long enough to prevent prolongation of the hold
time by noise pulses. Fig. 12 also shows how a noise burst superimposed
on speech will initiate rapid AGC action via the short time constant detector
while the long time constant detector effectively remembers the pre-noise
AGC level.

38

TR9

300

I NP UT 1 ~--c:J---r-t'

450

7·6k

C3
1(Xl>

OUTPUT 2

PAUSE IN SPEECH
NOISE

BURST

NOISE BURST

FADE
SIGNAL I AUOIO

SPEECH

E~~DS

INPUT
ENVELOPE

MO,h

OUTPUT
ENVELOPE

~

I

1'1

NOISE
(SYSTEM AT FULL GAIN)

,.L,"""""

SHORT TIME CONSTANT
DETECTOR OUTPUT (e1)

LONG TIME CONSTANT

DElEe TOR OUTPUT (e2)

:
,, ,,
,, ,,
,, ,,
"

,
"

t5

Fig. 12

(C3)

Circuit diagram of SL621C and dynamic response ofanAGC system
controlled byan SL621C

39

SL630

RF

AF

INPUT

OUTPUT
MIXER

PRODUCT
DETECTOR

5~

Fig. 13

An SL621C used to control an SSb receiver

10 ~

'"

20
30
~ i.0

Z

g
«

~

...........

.................. SL610
I'- ........ .........

"

CD

50
60
70
80

."\.

"

:-.......

SL612

'\.

SUM TOTAL

'\.

~ 90
~ 100

"\.

110
120
130

'\.

2

3

4

AGe SIGNAL (V)

Fig. 14

A ttenua tor AGC signal

The various time constants quoted are for C1 . 50 microfarads and C2=C3=
100 microfarads. These time constants may be altered by varying the appropriate capacitors.

CIRCUIT APPLICATIONS
The SL621 is used in an SSB receiver as shown in Fig. 13. AGC need only
be applied to two of the gain stages even if there are more than two such
stages in the receiver since AGC applied to two stages only will result in over
120dB AGC range. It is usual to apply AGC to the first RF stage and the first
IF stage and it will be seen from Fig. 14 that an SL612 IF amplifier reacts
earlier to an increasing AGC voltage than an SL610C RF amplifier. This has
the effect of delaying the AGC to the input stage, thus improving the receiver
signal to noise ratio at low AGC levels.

40

Fig. 14 also shows the total attenuation to be expected at any AGC voltage
when AGC is applied to one SL610C and one SL612C in a system; from this
one can calculate the calibration of an'S' meter for use with the SL621C.
Such a meter, as shown in Fig. 13, should have a sensitivity of 2.6V FSD and
be calibrated linearly from 0 to 120dB.
The output current capability of the SL621 is not high and it should not be
expected to drive more than three SL610/11/12 devices in addition to an'S'
meter circuit similar to that shown in Fig. 13.
There are two other important points to observe when using the SL621C:
supply de-coupling and input coupling. Since capacitors C1 and C3 may
need to charge very quickly, the source impedance of the 6V supply line at
low frequencies should be very low, if necessary being decoupled by a low
impedance 1000 microfarad capacitor placed near the SL621C.
The input should be applied to pin 1 via a capacitor of not more than
470 ohms reactance at the lowest input frequency encountered, and should
never exceed 1Vrms. Input voltages in excess of this level may cause the
internal amplifier to block, with consequent failure of the AGC voltage. The
condition can be avoided, if necessary, by using a diode limiter at the input.
In the presence of RF fields the AGC line may need to be decoupled: a
5000pF capacitor from pin 7 of each RF amplifier to earth and a 100 ohm
resistor from each pin 7 to the AGC line should be adequate. It is, however,
important not to use a capacitance greater than 15000pF, otherwise the
impulse suppression characteristic of the circuit will be degraded.
The SL621 may be used with supply, voltages between +6Vand +9V.

41

SL623C, SL1623C & SL1625C
AM detector, AGe amplifier and SSB demodulators
The SL623C consists of an AM detector, an SSB detector and an AGC
generator designed for use with AM. The SL623C was introduced to enable
the small-signal sections of an HF AM/SSB transceiver to be completely
integrated - all functions with the exception of the power amplifier can be
realised with SL600 series integrated circuits. The outputs of the SL623C will
drive most audio output stages with input impedances over 10 kilohms, and
are particularly suitable for driving the SL630C .
In addition to its audio outputs, the SL623C AGC generator is designed to
control SL610/11/12 RF/IF amplifier strips, but, unlike the SL621C AGC
generator, which operates from an audio signal, the SL623C control voltage is
carrier-derived. It is therefore less suitable for use with SSB or CWo However,
the AGC output pins of an SL621C and an SL623C may be connected together
for an SSB/ AM receiver, the gain then being controlled by the device with
the higher output voltage.
The SL1625C is an SL1623C without its SSB detector.

CIRCUIT DESCRIPTION (Fig. 15)
The IF input is applied directly to one input of a full-wave detector and, via
a unity-gain inverting amplifier, to the other input of the full-wave detector and
to the signal input of a balanced demodulator. Two outputs from the full-wave
detector are brought out of the package: audio and AGC. The AGC signal is
used as the input to the AGC amplifier of the device. The AGC amplifier
consists of two amplifiers in series. The first has a gain which may be varied
between -0.25 and -5 by an external resistor and the second has a fixed
gain of -20 and a frequency compensation point. The SSB detector, which
requires a carrier input of 100mV rms, consists of a simple balanced demodulator.
A single positive supply of between +6V and +9V is required. The supply
should be decoupled close to the can by a 0.1 microfarad capacitor. Current
consumption is approximately 10mA at 6V supply and zero AGC voltage, but
rises with both supply voltage and AGC output level.

CIRCUIT APPLICATIONS
AM Detector

The detected AM output has an output impedance of about 1 kilohm and
should be decoupled at RF with a 0.01 microfarad capacitor (C1). It should be
connected to the audio stage via a dc blocking capacitor. The other detector
output is similar but should be decoupled with a 50 microfarad capacitor
(C2) to remove AF, and connected via a preset potentiometer R28 to the AGC
amplifier input to provide rectified carrier for amplification as AGC. C1 and
C2 should be connected directly to the earth pin via the shortest possible
leads, which should not be common to any other components. C2 should have
an AF series resistance of under 1 ohm and, if it does not also have a low RF
impedance, should be shunted by a 0.01 microfarad RF bypass capacitor
(C3). These measures prevent instability due to possible RF current loops.

42

Fig. 15

SL623C circuit diagram

AGe Generator
Pin 3, the AGC amplifier phase correction point, should be decoupled to
ground by a 1 microfarad capacitor (C4) ,keeping leads as short as possible.
The value of C4 is quite critical, and should not be altered: if it is increased the
increased phase shift in the AGC loop may cause the receiver to become
unstable at LF and if it is reduced the modulation level of the incoming signal
will be reduced by fast-acting AGC.
A capacitor connected to the phase correction point and the output of the
AGC amplifier helps to reduce the ripple on the AGC output. Its value varies
from system to system and with intermediate varying frequencies. Normallyused values vary between 0.1 and 10 microfarads. As there is no easy way
to predict suitable values for particular systems, this component must be
'selected on test'.
The AGC output (pin 4) will drive at least two SL610/11/12 amplifiers and the
'S' meter circuit shown in Fig. 13. The SL623 AGC output is an emitter follower
similar to that of the SL621C. Hence the outputs of the two devices may be
connected in parallel when constructing AM/SSB systems.
Less signal is needed to drive the SSB demodulator than the AM detector.
In a combined AM/SSB system, therefore, the signal will automatically
produce an SSB AGC voltage via the SL621C as long as a carrier (BFa) is
present at the input to the SSB demodulator of the SL623C. The AGC generator
of the SL623C will not contribute in such a configuration.
For AM operation the BFa must be disconnected from the carrier input of
the SSB demodulator. In the absence of an input signal, the SL621 C wi!1 then
return to its quiescent state. To switch over a receiver using the SL623C
from SSB to AM operation it is therefore necessary to turn off the BFa and
transfer the audio pick-off from the SSB to the AM detector.

43

Neglecting to disconnect the SSB carrier input during AM operation can
result in heterodyning due to pick-up of carrier on the input signal. In some
sets different filters are used for AM and SSB; these will also need to be
switched.
The 10 kilohm gain-setting preset potentiometer R28 is adjusted so that a
DC output of 2 volts is achieved for an input of 12SmV rms. There will then be
full AGC output from the SL623C for a 4dB increase in input. A fixed resistor
of 1.S kilohms can often be used instead of the potentiometer.

SSB Demodulator
The carrier input is applied to pin 6, via a low-leakage capacitor. It should
have an amplitude of about 100mV rms and low second harmonic content to
avoid disturbing the DC level at the detector output.
Pin 8 is the SSB output and should be decoupled at RF by a 0.01 microfarad
capacitor. The output impedance of the detector is 3 kilohm and the terminal
is at a potential of about +2V which may be used to bias an emitter follower
if a lower output impedance is required. The input to the audio stage of a
receiver using an SL623C should be switched between the AM and the SSB
outputs - no attempt should be made to mix them. Since the SL621C is
normally used in circumstances where low-level audio is obtained from the
detector, the relatively high SSB audio output of the SL623C must be attenuated before being applied to the SL621C. This is most easily done by connecting the SL623C to the SL621 C via a 2 kilohm resistor in series with a O.S
microfarad capacitor.

Input Conditions
The input impedance is about 800 ohms in parallel with SpF. Connection
must be made to the input via a capacitor to preserve the DC bias. An input of
about 12SmV rms is required for satisfactory carrier AGC performance and
20mV rms for SSB detection. Normally, the AGC will cope with this variation
but in an extreme case a receiver using an SL623C and having the same gain
to the detector in both AM and SSB modes will be some 10dB less sensitive
to AM.

44

SL630C & SL1630C
Microphone/headphone amplifier
The SL630C is an audio amplifier having 40dB gain and an internal gain
control of approximately 60dB, and an output capability of 200mW into a
40 ohm load when used with a 12V supply.

CIRCUIT DESCRIPTION AND APPLICATIONS
To maintain HF stability - particularly on negative half-cycles - the
output (pin 1) should be decoupled by a 1,000pF, low series inductance,
capacitor placed directly between pins 1 and 10 (8) with leads cut as short as
possible. This component must be on the integrated circuit side of the output
coupling capacitor. At high supply voltages and/or low temperatures 10 ohms
must be placed in series with this capacitor and 100pF connected from pin 4
to earth. The output is coupled to its load with a capacitor of a low impedance
relative to the load at the lowest frequency to be used. The load may be
resistive or reactive and, for maximum power output, should lie on the
load/supply voltage line. Any higher value of load impedance is quite safe
but the device will over-dissipate and eventually destroy itself by overheating
if the output is short-circuited. The optimum load therefore, at any rate with
supplies of over 9V, can be regarded as a safe minimum. The circuit shown
in Fig. 16 which shows the SL630C used as a headphone amplifier, may also
be used with loudspeakers having suitable impedances. The distortion is
about 0.5 per cent at full output.
The power supply, to pin 2, should be between +6V and +12V and adequately decoupled both at HF and LF. The quiescent power consumption at
various supply voltages is shown in the Power characteristics, as is the
relation of the supply voltage to the optimum load and the maximum power
available.

,----~---+6-12V

IO~

4·7k TO 10k
RISES WITH
SUPPLY VOLT AGE

lk LIN.
GAIN

CONTROL

o--I

511

•

liP {

Fig. 16 Headphone amplifier using the SL630C

45

5

30 0
~

~

0

I'\.

30

~

~

-"'.

40

~

o ~iTlhlUM

50

'\.

60
08

, 6

'·2

~

LOiD

POWER OUTPUT
INTO OPTIMUM LOA.D

QUlESiCENT

04

~

~

'\.

20

v:
V
~

I\.

10

~

20

0

POW~R

I

AGe VOLTAGE

Fig. 17 AGe characteristics

I

./

/

/'

/,

/

,

./

/'

SUPPLY VOLT A.GE (V)

Fig. 18 Power characteristics

A capacitor connected to pins 3 and 4 defines the high frequency response
of the amplifier. The upper 3dB frequency, f, is given by the formula:

f=

~~~~ kHz.

(C is in picofarads)

Pins 5 and 6 are input terminals. They may be used together as a differential
input, in which mode they present an impedance of approximately 2 kilohms
and result in a voltage gain (without gain control) of 100 (40dB). When the
input is obtained from a magnetic transducer or a transformer it is desirable
to use·the differential input mode since the signal winding may be connected
directly between pins 5 and 6 and no other components are required.
An input may also be applied between pin 5 and earth. In this case the gain
is 200 (46dB) and the input impedance 1 kilohm. Pin 6 should be earthed by
1500pF. A coupling capacitor is required between the input and pin 5.
The circuit is muted by earthing pin 7. A muted circuit attenuates an input
by about 100dB. There is no mute facility on the SL 1630.
Gain control is applied to pin 8, (7) which has an input impedance of 3.6
kilohms. It must be appreciated that even with full gain control the input
cannot exceed 50mV rms without clipping so that at high control levels the
output level is limited. The AGC characteristics will vary with temperature
but, as shown in Fig. 16 a potentiometer to give manual gain control can be
connected to the internal bias point at pin 9 which provides a temperaturecompensated reference at the voltage at which gain control commences.
This reference pin is omitted on the SL1630C. Pin 10 (8) is the signal earth
and negative power supply connection.

46

Applications
The first part of this handbook describe Plessey Semiconductors' range
of integrated circuits for Radio Communications and general techniques
of using them. This section describes a number of specific applications of
these circuits which have been developed at various times in our Applications
Laboratory.
These applications cover receivers and transceivers of several types and
some frequency synthesisers. Some of these applications have been developed in great detail and are engineered practically to pre-production
status, others are merely ideas which have been shown to be practical but
have not been taken further.

An AM receiver using St1600 circuits
This receiver is a single conversion superhet using SL 1600 devices with
an IF of 455kHz. It was designed for use in 27MHz CB receivers, possibly
following another conversion to a first IF of about 10.7MHz. The receiver has a
sensitivity of about 1 microvolt and delivers 3 watts to an 8 ohm loudspeaker.
The block diagram of the receiver is shown in Fig. 60. It consists of a normal
single conversion superhet with a 455kHz intermediate frequency. An SL 1641
double-balanced modulator acts as a mixer and is followed by a ceramic
ladder filter with a ±3kHz passband.
The intermediate frequency amplifier consists of three SL 1612 amplifiers
with a simple interstage ceramic filter between the second and third stages.
This amplifier has a gain of over 100dB and AGC is applied to all three stages.
It is followed by an SL 1623 detector which also provides AGC.
The AGC line may be fed to an external'S' meter and also goes to an SL748
used in a squelch system. After passing the squelch gate the audio goes to a
TBA800 3-watt amplifier.
Fig.61 is a detailed circuit diagram of the receiver.

THE MIXER
The mixer consists of an SL 1641 double-balanced modulator. The SL 1641
has a free collector output which is used to drive a 2 kilohm resistive load to
provide the correct match to the Murata CFR 455H ceramic filter.
The SL 1641 is intended to drive a load with a DC resistance which does not
exceed 800 ohms. To prevent saturation of the output transistors of the SL 1641,
the 2 kilohm resistor must be connected to a +12V supply while the SL1641
itself runs from +6V. Furthermore, it is essential to decouple the supply to the
2 kilohm load most throroughly to prevent IF feedback via the supply line.
This mixer has several advantages - it has a conversion gain of 9dB
(which is sufficient to overcome the loss of a CFR 455H filter), a low noise
figure, and it requires only 200mV rms of local oscillator injection. It has a
signal input impedance of 1 kilohm in parallel with 5pF, which means that it
can be driven from a ceramic filter in dual conversion receivers. The local
oscillator port also has a high input impedance: 1 kilohm in parallel with 4pF.

47

The other feature important in a receiver mixer is intermodulation. While
the SL 1641 cannot compete with hot carrier diode or FET ring mixers, it has
considerably better performance than the transistor or FET mixers generally
used in Citizens' Band receivers. Its third order intercept point is around
+8dBm.

SL 1641
MIXER

CFR 455H
CERAMIC
FILTER

Fig. 60

SFD455
CERAMIC
FILTER

SL 1623

27MHz Citizens' Band AM
receiver block diagram

THE IF AMPLIFIER
The IF amplifier consists of three cascaded SL 1612s, giving a maximum
gain of over 100dB. Since SL 1612 amplifiers are broadband devices, a 100dB
untuned strip would have over 20mV of broadband noise at its output, and any
local oscillator signal getting through the first filter would be amplified.
Extra filtering is therefore necessary, and is provided by a simple SFD 455
between the second and third stages.
Although the three SL 1612s have a maximum gain of over 100dB, the IF
strip is stable without any particular precautions - provided that the supply
rail is adequately decoupled and the ground layout is adhered to. The receiver
may be built on single-sided circuit board without trouble or it may be built
on ground-plane double-sided board, in which case both sides of each
integrated circuit ground connection must be soldered.
AGC is applied to all three stages. This is not absolutely necessary since
two stages will give 140dB gain control range but it is better to have distributed AGC. If AGC is applied to only two stages it should be applied to the
first two.
This IF amplifier has excellent performance and uses few discrete components. Although the integrated circuits are more complex than the discrete
transistor equivalent, the saving in tuned circuits, discrete components, and
adjustment makes the integrated circuit amplifier far superior in both performance and cost.

THE DETECTOR AND SQUELCH
The detector consists of an SL 1623. The circuit detects AM and provides
carrier-derived AGC which may also be used to drive an 'S' meter. The'S'

48

CI1~

..be12

,n

O.IJ,1Yl00J,l

".

Resistor values are in ohms, capacitor values in microfarads unless otherwise stated.
IC1
IC2
IC3
IC4
IC5
IC6
IC7
IC8
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
~

co

SL 1641C
SL1612C
SL 1612C
SL 1612C
SL1623C
SL748C
TBA800
78L06
2k
3.3k
100
100
330
100
1.5k
10k
1M
10k
6.8k
10k

R13
R14
R15
R16
Rl7
R18
R19
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
Fig. 61

10k
10k
1k
56
1
100
10k
0.1
0.01
0.01
0.1
10 TANT
1000pF
0.01
1000pF
0.01
0.1
0.1
100 TANT
56pF

C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32

0.Q1
1000pF
47 TANT
0.1
0.1 TANT
1 TANT
0.01 TANT
30pF
10 TANT
1 TANT
100 TANT
100 TANT
1000pF
0.1
0.1
100 TANT
10 TANT
0.1 TANT
10 TANT

SKT1 Signal input
SKT2 LO input (200mv)
P1
P2
P3

+12V supply
Ground
Audio output

P4}
P5

Volume control

P6}
P7
P8
P9
VR1
VR2
T1
F1

Squelch control

F2

AGC line
25k lin squelch control
25k log volume control
Small sjgnal audio si NPN
455kHz Murata ladder filter boards
will accept CFS, CFR or CFM types.
Recommended is CFR 455H.
Murata SFO 4550

27MHz Citizens' Band AM receiver circuit diagram

meter should consist of a voltmeter with a 2V offset reading from 2V (no
deflection) to 3.5V (full deflection). It should not draw more than 600 milliamps
and should be calibrated linearly.
The AGC is also applied to an SL748 operational amplifier which is used
as a squelch circuit. The SL748 is connected as a trigger circuit with a variable
threshold so that, as the AGC output rises past the threshold, the squelch
output goes high. This high output applies bias to an emitter follower in the
audio line which allows the detected audio to pass, via the volume control,
to the output stage.
The squelch output may also be used to turn on a lamp to indicate the
presence of a signal.
The SL 1623 is an AM and SSB detector and has 1.4 pins. As the SSB facility
is not needed it may be replaced by the SL 1625 - a version of the SL 1623
without the SSB facility and encapsulated in an-8-lead minidip.

THE OUTPUT STAGE
The output stage uses standard 3 watt integrated circuit output stage which
will drive an 8 ohm loudspeaker.

POWER SUPPLIES
The mixer and the output stage require a + 12V supply, the rest of the
circuits a +6V supply. The +6V supply is obtained from the + 12V supply
with a 78L06 voltage regulator.

LAYOUT
The layout and component placing of the prototypes of this receiver are
shown in Figs. 62a and 62b. Other layouts may be used to occupy available
space, but two considerations are necessary - the mixer and IF strip should
be separated as much as possible (at least 2cm), and the topology of the IF
strip layout should be retained to prevent ground loop instability.

PERFORMANCE
The overall performance of this receiver depends on the system in which it is
used. Dual conversion systems have good image and spurious performance
but single conversion systems have better intermodulation performance.
In this performance summary parameters influenced by the external design
are therefore ignored.
In the Citizens' Band service at 27MHz the noise figure of a receiver is less
important than its strong signal performance. This receiver has a sensitivity
of 1 microvolt at the SL1641 input for a 20dB SIN ratio, which is adequate,
and a third order intercept point of +8dBm. Its dynamic range is well over
100dB.
On standby the power consumption is about 600mW, although this rises
during periods of high audio output.
Receiver passband and adjacent channel rejection depend on the filter
used - with a CFR 455H the passband is ±3kHz and adjacent (± 10kHz)
channel rejection is 65dB.

50

SL 1600

CB Rx

Fig. 62a Printed circuit layout for SL1600C
AM Citizens' Band receiver.
Scale 1:1

E B C

o

TRI
2N390'

Fig. 62b Component layout for SL1600C
AM Citizens' Band receiver.
Scale 1 :1

51

Simple SSB transceiver
SL600 VERSION
This transceiver, shown in Fig.63, consists of a single conversion superhet
receiver with a 9MHz IF and a very efficient audio-derived AGC system, and a
filter type 55B generator, also working at 9MHz. Audio AGC in themodulator
path gives constant level output. The transmitter and receiver are arranged so
that no signal switching is required between transmit and receive, and the
RF components are common to both.
The RF input is direct to an Anzac MD-108 (or similar) hot carrier diode
ring mixer. This has 50 ohm ports and is also driven by the local oscillator,
at about -r 7dBm (500mV). The output is connected via a 3: 1 step-up transformer to a 9MHz crystal filter. This filter has the 2.4kHz bandwidth required
for 55B and a 90dB stopband. Filters with 60dB stopband can be used, but
additional filters may be required at low local oscillator frequencies to keep
the local oscillator signal out of the IF amplifier (and the overall receiver
performance will, of course, be degraded).

TR.6.NSMIT

GAIN
CONTROL

J.!-~-----{

SAL

h r - l - - - - - { ,~~ET

- AUOIO
OUIPUl

VOLUME
CONTROL

Fig. 63

52

Simple SSB transceiver circuit diagram

The filter used, an SEI QC1246AX or a KVG XF9-B, has a terminating
impedance of 500 ohms, but only within the passband of the filter. At frequencies outside the passband it may be very different, which means that the
impedance that the filter presents to the diode ring mixer via the transformer
will vary from 50 ohms. Such a mismatch will degrade the cross-modulation
and carrier leak performance of the diode ring. However, it was decided on
balance, that it was better to tolerate such degradation - which is not excessive-than to complicate the design by incorporating a broadband impedance
match (which would probably not be bidirectional and hence would have to be
switched between transmit and receive).
The present design allows the same arrangement to operate in opposite
directions during receive and transmit without any switching. On the other
side of the crystal filter the transmit and receive signal paths diverge but
are still not switched.

The Receiver
The incoming RF signal is mixed with the local oscillator in the mixer
described above and then passes through an SSB bandwidth 9MHz crystal
filter. It is then amplified by three cascaded SL612C IF amplifiers, IC2, 3 and 4.
These amplifiers are untuned and since the strip has a maximum gain of
102dB careful attention must be paid both to noise and to stability. The
SL612C has a 3dB noise figure which means that the broadband noise at the
output of the three-stage strip is about 10mV RMS. This is not sufficient to
affect a product detector, which is only concerned with the component within
a few kHz of the BFO frequency, but would cause trouble if a diode detector
were to be used.
A broadband amplifier with 102dB gain is a likely candidate for stability
problems. The three-stage strip used in this receiver is less liable to power
supply feedback than most since the SL612C has internal supply decoupling.
Nevertheless it must be carefully laid out to minimise earth loops and input!
output feedback. The simplest way to do this is to use a double-sided printed
circuit board with the components side a continuous ground plane to which all
earth connections are made. If this is done the layout on the conductor side of
the board is not very critical but if single-sided board is used with the earth
conductors on the same side as the other conductors then it does become so.
The design of board in Fig. 64 is the most stable layout yet developed for such
strips on single-sided board, and it is strongly recommended that it be copied
exactly.
There are two other possible causes of instability in this transceiver: inadequate supply switching and inadequate supply decoupling. Since the only onboard transmit/receive switching is by means of power switching it is essential
that the transmit supply be not only isolated but earthed during receive, and
vice versa. Both supplies should also be well decoupled at RF.
The IF strip has AGC applied to it by an SL621C audio AGC circuit, ICB.AGC
is applied via an emitter follower, which has the effect of reducing the AGC
range of each SL612C by 0.7V. The overall AGC range could be reduced to less
than 90dB were only two SL612Cs to have AGC applied to them. AGC is
therefore applied to all three to give 130dB, of which the usable AGC range is
about 115dB.
The IF output is applied to an SL640C double-balanced modulator (IC6),
used here as a product detector. When AGC is operating, the audio output of

.53

the detector is about 10mV RMS. The audio is fed to IC7, an SL630C audio
amplifier which has a voltage gain control. The SL630C can supply up to about
60mW to headphones, to a small loudspeaker or to an external amplifier.
The detected audio also goes to the SL621C audio AGC system (IC8). This
has an ideal characteristic for SSB reception. It operates from the receiver
audio, not from RF, and it has fast attack and fast decay unless a signal
disappears altogether-as in speech pauses-when itdoes not decay at all
for a second and then, if the signal has not reappeared, decays quickly. This
enables it to track rising or fading signals but prevents it overloading after
each brief speech pause. The circuit also incorporates very fast AGC action
to suppress brief noise bursts.
An FET oscillator is used to supply carrier to the product detector and to the
double-balanced modulator in the transmitter. The voltage applied to the 'sideband select' terminal determines which crystal is used - upper or lower sideband - but the terminal must not be left unconnected: it must either be connected to +6V or to earth. The oscillator is supplied via diodes from both the
transmit and receive lines so that it continues to operate on transmit or receive.
The most basic receiver does not have an'S' meter but if one is required it
may be connected to the emitter of the AGC buffer transistor. It should consist
of a moving coil meter connected in series with a resistor such that FSD corresponds to 2.SV and three forward biased silicon diodes. This 'S' Meter circuit
has a rather compressed scale for signals more than 40dB above the AGC
threshold. If a more linear scale is necessary the more complex system described in the multi mode transceiver should be used.
This receiver has a sensitivity of 1.0 microvolts for 10dB SIN. This means
that at HF with adequate antennas no RF amplifier is required since atmospheric noise will limit system performance. At higher frequencies, or in
systems where small antennas are used, RF gain may be necessary to prevent the performance being gain-limited rather than noise limited. Such
amplifiers increase gain but degrade intermodulation performance. In general,
without the RF amplifier, the receiver will tolerate about 200mV of adjacent
channel signal on the mixer without significant intermodulation. This is, of
course, a property of the mixer rather than of the rest of the circuit, although
the filter characteristics are also involved.

The Transmitter
The transmitter uses the standard filter method of generating SSB. Audio
from the microphone is fed to an SL622C microphone amplifier (IC9), which has
AGC giving a constant 100mV output over 60dB of input. The AGC ensures
an almost constant output from the transmitter, but can be inconvenient in
noisy environments when the transmitter will give full modulation on noise in
the absence of a speech input. Such noise modulation is avoided by the
addition of a single extra resistor (RS, between pins 8 and 9 of the SL622C)
which reduces the dynamic range of the AGC.
The constant-level audio from IC9 is applied to the signal input of an SL640C
double-balanced modulator (ICS). The output of the FET carrier oscillator is
applied to the carrier input of ICS and a double sideband suppressed carrier
signal appears at its output. Carrier suppression is of the order of 40dB.
This DSB signal is amplified in an SL610C (ICI). The AGC pin of ICI is
brought out from the board and may be used either to preset the system gain
or as an ALC connection. The amplified DSB from ICl is then passed through

54

the crystal filter, which removes one sideband, leaving SSB. The SSB is mixed
to the final transmitter frequency in the diode ring mixer and then goes to a
linear amplifier which raises it to the transmitter output level. The output from
the diode ring is, of course. lower than the input to the filter and is about
100mV or less into 50 ohms.
The output of IC5 and the input of the first SL612C (IC2) are connected to the
same point on the filter via resistors. R6 is merely a buffer resistor but R2 and
R1 set the impedance which the filter sees in operation. This varies from 480
ohms on transmit to about 530 ohms on receive, but this small variation does
not affect filter performance. The loading effects of a turned-off SL612C during
transmission and a turned-off SL610C during reception are similarly insignificant.
The transmitter output (atthe diode ring) consists of an SSB signal with carrier
below - 55dB and opposite sideband below - 60dB, provided that the carrier
oscillator is at the correct frequency. The degree of off-channel spurious
signals depends on the crystal filter used: 90dB stopband type gives excellent performance but a cheaper one can sometimes cause trouble.

The Transceiver
The transceiver board needs few extra sub-systems to make a complete
transceiver. They are: a power supply, microphone, volume control and loudspeaker and also a filter, local oscillator and linear amplifier. These are connected as shown in Fig. 65.
Much of the performance of the final system will depend upon the standard
of design of the local oscillator, pre-selector, RF amplifier (if used) and linear
amplifier, but the performance of the transceiver board itself is excellent. The
Anzac MD-108 mixer used is capable of the required performance between
10kHz and 500MHz. If other diode rings were used the transceiver might be
used over an even wider range. Its power consumption is about 400mW on
either transmit or receive.
The most attractive feature of this transceiver, despite its high performance,
is its simplicity. It uses only 80 components and contains no tuned circuits or
other components requiring adjustment. It was designed for two purposes: (a)
to demonstrate the usefulness and versatility of the SL600 Series in SSB
applications and (b) as a ready-engineered SSB transceiver suitable for
those inexperienced in SSB design. It is capable of giving good performance
but can be constructed and commissioned by relatively inexperienced
personnel.

Physical Construction
The board and component layouts are shown in Fig. 64. The board is singlesided and there are two jumper links on it carrying power supplies. As mentioned above the layout on a single-sided board carrying such a high gain
broadband IF strip is critical and it should not be changed. All passive component leads should be as short as possible and integrated circuits should
not be mounted more than 6mm above the board.
The two transformers T1 and T2 are both wound on small toroids of high
frequency ferrite. The exact size and material are not important but the
material must be low loss up to at least 45MHz and it is essential that it has a
linear BtH characteristic, otherwise it will cause intermodulation at the receiver

55

'"?l E!J .

'U
In G:

~ •

(J)

r-

8
(J)

m

:D

;;;

(J)

I

-t

~.

I.

•

~ .....~

I·

·1

·1

o·
E3

~
. .

E3 ;::m
m

:D

Fig. 64a Copper side of PCB for simple
SSB transceiver

56

Fig. 64b PCB for simple SSB transceiver

57

input. T2 is a simple transformer with a six-turn primary and a single turn
secondary but T1 is more complex. T1 is made from four 5cm lengths of 26
SWG (0.46mm dia.) enamelled copper wire twisted together. The length of
twist is used to wind two turns on the toroid and the ends are separated.
Three lengths are then connected in series in the same sense to form the
filter winding and the last length is used as the diode ring winding.
There are few other constructional details that need mentioning, but if a
receiver without a transmitter is required one may be built by omitting the
three transmitting integrated circuits (SL610C, SL622C and the SL640C)
between them), R1 to R5 inclusive and C1 to C13 and C40. To preserve the
filter impedance match a 500 ohm resistor should be connected from the filter
side of R6 to earth.

Component

Value

Rating

Type

R1
R2
R3
R4
R5
R6
R7-R9
RiO
R11
R12
R13
01-06
TR1
TR2
T1, T2
Mixer

100
430
100
6S0K
1K
SO
100
330
10
100K
330

1/S W
1/S W
1/S W
1/S W
1/S W
1/S W
1/S W
1/S W
1/SW
1/S W
1/S W

Hi-Stab.
Hi-Stab.
Hi-Stab.
Hi-Stab.
Hi-Stab.
Hi-Stab.
Hi-Stab.
Hi-Stab.
Hi-Stab.
Hi-Stab.
Hi-Stab.
1N414S}
2N3S19
2N706

Crystals
IC1
IC2-IC4
ICS-IC6
IC7
ICS
IC9
C1-C4
CS
C6
C7
CS
C9
C10
C11-C12
C13
C14-C1S
C16

See text.
Anzac
MO-10S
9.001S MHz &
S.99SS MHz
SL610C
SL612C
SL640C
SL630C
SL621C
SL622C
1nF
10llF
100pF
471lF
10llF
4.7nF
21lF
1nF
100nF
100pF
4.7nF

Or similar
devices

Parallel (30p) resonant

SOV
6.3V
50
6.3V
6.3V
SOV
6.3V
SOV
SOV
SOV
SOV

Weecon (Min Ceramic)
Min. Tantalum
Ceramic
Min. Tantalum
Min. Tantalum
Weecon
Min. Tantalum
Weecon
Weecon
Ceramic
Weecon

Table 4 Components list for the Simple SSB Transceiver (Fig. 63)

58

Component

Value

Rating

Type

C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35-C36
C37-C38
C39-C41
C42

100pF
4.7nF
100pF
4.7nF
100pF
1nF
10IJF
4.7nF
100nF
10IJF
100IJF
10nF
1nF
1IJF
100IJF
47IJ F
100IJ F
400IJ F
68pF
10nF
100nF
100pF

50V
50V
50V
50V
50V
50V
6.3V
50V
50V
6.3V
6.3V
50V
50V
6.3V
6.3V
6.3V
6.3V
16V
50V
50V
50V
50V

Ceramic
Weecon
Ceramic
Weecon
Ceramic
Weecon
Min. Tantalum
Weecon
Weecon
Min. Tantalum
Min. Tantalum
Weecon
Weecon
Min. Tantalum
Min. Tantalum
Min. Tantalum
Min. Tantalum
Min. AI. Elect.
Ceramic
Weecon
Weecon
Ceramic

TX +6V

2K

5K

ALC

PRE-SELECTOR
FILTER

~'_______
iS2 _

TX OIP
RX liP

TRANSCEIVER
BOARD

MIC
LS 100mW

L-.j>---.......~...........J

II NEAR
AMPLIFIER

L----lS4

Fig. 65

1

~~--~------------+6VHT

Block diagram of complete SSB transceiver

SL1600 VERSION OF THE SSB TRANSCEIVER

Figs. 66 and 67 show the circuit diagram and board layout respectively of
a version of the SSB transceiver which has been designed to use the SL 1600
devices. In addition to the use of the SL 1600 series circuits a single PNP
transistor is used in place of the SL610 in the transmitter and has only one
BFO crystal on the board.

59

RF

_

SKTl

INPUTI
OUTPUT
LO
INPUT

+6V TX P7 C>---_..--~-~~_..--+_,

P11

t6V COMMON
SUPPLY

R13

lR3

BAlANCEO{P8
MIC INPUT

e37

(180A)

pg

~o-T"-

_ _'----'"

Resistor values are in ohms, capacitor values in microfarads
unless otherwise stated.
IC1
IC2
IC3
IC4
IC5
IC6
IC7
IC8
TR1

SL1612C
SL 1612C
SL 1612C
SL1640C
SL 1621C

SL1630C
SL 1622C
SL 1640C
Si NPN - 2N706,
BC108 etc.
TR2 High frequency Si
PND - 2N3906 etc.
TR3 High frequency
N-channel FET 2N3819, BF244B etc.
Almost any small
D1
Si diode - 1N914
D2
etc.
Diode ring - ANZAC MD-108

60

Filter - KVG Xf9-B
X1
30pF parallel resonant
8998 5kHz in HC18 or HC25
T1
P 2 turns
2 hole
ferrite bead
S 5 turns
R1
470
R2
47
120
R3
R4
120
120
R5
R6
10
R7
470k
R8
100
R9
100
R10
100k
R11
1k
R12
Select to give 200mV rms
at pin 4 of IC4
2.7k
R13
R14
8.2k

------------r----r-------r-----r--r----()PI

"

5

I ,

le3

Fig.66

P1
P2
P3
P4
P5
P6
P7
P8}
P9
P10
P11

16V receive supply
Ground
Audio output
Audio ground
Audio gain control
'S' meter (if used)
+6V transmit supply
Balanced microphone
input (180 ohms)
Ground
+6V common supply

All resistors 5 per cent

tw

All capacitors miniature ceramic
except ones marked TANT which are
bead tantalum.
C1
C2
C3
C4
C5
C6

22pF
0.01
1000pF
1000pF
0.01
1000pF

+6v RX

C31
C32
C33
C34
C35
C36

5000pF
2 TANT
10 TANT
0.1
1000pF
0.1

SL1600 SSB transceiver
circuit diagram

C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30

0.01
1000pF
0.1
1 TANT
1 TANT
10 TANT
0.1
1000pF
100 TANT
47 TANT
100 TANT
1000pF
100pF
5000pF
100 TANT
0.01pF
100 TANT
0.1pF
1000pF
1000pF
47 TANT
0.1
0.1pF
1 TANT

C37
C38
C39
C40

0.1
56pF
56pF
0.1

61

Fig.67a SL1600 SSB transceiver printed
circuit layout. Scale 2:1

62

uD

aJ •
w •

'3

"'OL
0I

"'W
Z
0"
Z~

,,"-

'"~

u

ODD

zzw

::>::>'"
00::>

"''''",
""- II""
~

~

Z
W
Z
0

"-

:>:

:3

~~O

:Z
ZW
"'O~
WU aJ
~
OWO
"'aJO

'"

Fig. 67b SL1600 SSB transceiver componentiocations.
Scale 1 :1. Holes marked X are ground and should
be connected to the ground plane if double sided
board is used

63

MULTIMODE TRANSCEIVER
Like the simple sse transceiver this multi mode transceiver consists of a
single printed circuit board and requires the addition of a local oscillator, preselector, power amplifier, microphone, loudspeaker and volume control, as
well as power supplies and possibly an RF amplifier, to make a complete
transceiver.
The board, the block diagram of which is shown in Fig. 68, contains nearly
all the signal processing of the transceiver, including a noise blanker, VOX,
dual time constant AGe, an'S' meter/squelch control and RF compression
during transmission. Since most SUb-systems work independently the board
may be built without such refinements and used - either temporarily as a
stage in construction and evaluation, or permanently if particular functions
are not required. Thus the board may be used to build many different receivers
or transceivers.

*

TO TR

Fig. 68

64

RELAY CONTROL

DISCRETE DEVICES

Multimode transceiver block diagram

RECEIVER DESIGN CONSIDERATIONS
The major problem of receiver design is that of strong signal handling
during weak signal reception. There is no single cure for it but designs of high
performance receivers usually have as little RF gain as possible, followed by a
mixer with good strong signal performance followed at once by a crystal filter.
The crystal filter removes the majority of unwanted signals and the rest of the
receiver is unlikely to be troubled by them.
The crystal filters do not follow the mixer directly in this receiver, for two
reasons: first, to improve the impedance match between the mixer and the
filter, and secondly to permit the use of a noise blanker to suppress impulse
interference.
A suitable mixer for high performance receivers must have low noise, as
littLe conversion loss as possible, and be able to handle strong unwanted
signals without intermodulation. In this transceiver (as a reasonable compromise between cost and performance) a hot carrier diode ring mixer, the MO108 has again been chosen. Such ring mixers perform best when they are
terminated in 50 ohm resistive loads at all ports, but the input impedance of
crystal filters, besides being generally higher than 50 ohms, is reactive at
frequencies away from the filter passband.
In the Simple SSB Transceiver a transformer matching system was used
between the mixer and the filter and the reactive mismatch was ignored.
In this system a buffer amplifier, which is in fact also part of the noise blanker,
is used to terminate both the mixer and the filter correctly.
A major reason for the failure of receivers to produce weak AM and SSB
signals is man-made noise, typically ignition interference, at the antenna. This
noise is frequently in the form of very narrow pulses of very high amplitude
which can cause the crystal filter to ring at its resonant frequency. Once the
filter has been thus stimulated it will stretch the pulse so that it cannot be
distinguished from the wanted signal, which it swamps. Only by stopping the
ignition pulse before it reaches the filter can this interference be suppressed.
The noise blanker must therefore be somewhere in the receiver before the
crystal filter and the best place is between the mixer and the filter.
After the crystal filters the receiver design is quite conventional. There are
two filters, each feeding its own IF strip. One has a 12kHz passband and feeds
the FM IF system, which is a double conversion system with a 455kHz second
IF and a quadrature detector. This receiver was designed before the introduction of the SL665, which would allow the use of a single 9MHz IF.
The other biter has a 2.4kHz passband and its output goes to the CW/SBBI
AM IF strip. This strip has a broadband gain of about 70dB followed by another
crystal filter, which is of 2.4kHz bandwidth for AM and SSB and 500Hz for
CWo There is then another IF amplifier stage followed by two detectors. For
SSB and CW there is a product detector and for AM there is an envelope
detector.
On AM the envelope detector provides carrier AGC to the system but on CW
and SSB an audio derived AGC system is used. Squelch and '5' meter signals
are derived from the AGC line.
The decision to use a 2.4kHz filter for AM, removing one sideband, was
taken on cost grounds, as was the decision to use only one 500Hz CW filter
halfway down the IF strip, whereas two such filters, one at the input to the
strip, would certainly improve strong signal rejection in the CW mode. Ideally

65

there should be four filters at the input (with bandwidths of 12, 6, 2.4 and
O.5kHz respectively for NBFM, AM SSB andGW) and a further three filters
halfway down the AM/SBB/GW IF strip to reduce IF noise to a minimum. This
would entail an extra three expensive crystal filters compared with the
present system - for only a marginal increase in system performance.
The use of two filters halfway down the IF strip is well justified, however.
The GW filter in this position removes both unwanted GW signals in the 2.4
kHz passband and also much of the broadband noise which can cause
difficulty in copying very weak signals. The 2.4kHz filter is essential to
remove the broadband noise between 100kHz and 30MHz generated by the
first two IF stages which, if allowed into the AM diode detector, would greatly
degrade its performance.
The improvement due to this filter on the SSB product detector is much less,
since product detectors produce supersonic outputs from broadband noise
and these can be filtered without loss of wanted signal. There is nevertheless
a 3dB improvement in SIN ratio in systems where IF noise is the limiting
factor on system performance.

TRANSMITTER DESIGN CONSIDERATIONS
The transmitter has to generate all the modes that the receiver has to
receive. This is not particularly difficult, but several complexities have been
introduced to minimise spurious outputs and broadband noise while making
the transmitter as effective as possible.
The modulation envelope ofSSB does not resemble the audio producing it
and normal audio speech processing techniques do not greatly improve the
SIN ratio atthe receiver. RF clipping, however, reduces the peaklmean power
ratio of the signal and hence improves its mean power and readability.
It is also convenient to use the RF clipper for NBFM and AM, these signals
being demodulated from clipped SSB back to audio and the audio signal
applied to the NBFM or AM modulators. This technique gives up to 12dB
apparent signal to noise ratio improvement and the resulting received audio,
while obviously 'processed', is not unpleasant.
The audio input to the transmitter passes through an audio preamplifier
with AGG to ensure a roughly constant modulation signal regardless of microphone or audio level. It is converted to DSB in a double-balanced modulator
and filtered to SSB which is then applied to a limiting amplifier which removes
all amplitude variations. This clipped signal is, of course, rich in both harmonics
and intermodulation products and must be filtered in a 2.4kHz bandwidth
filter to remove them. The quality of this filter determines the spectral purity
of the resulting clipped SSB and is more important than the first filter producing
the sideband.
The 2.4kHz bandwidth filter reintroduces amplitude variations into the
signal which must be amplified by a linear amplifier. The signal is then either
further amplified and mixed to the final transmitter frequency or demodulated
to yield processed audio which can be applied to the AM or FM modulators.
The FM system uses this audio to modulate the external VFO while the
transceiver board supplies a steady 9MHz output to the transmitter mixer. The
AM modulator - which also supplies this unmodulated carrier during FM
transmission - consists of a double-balanced modulator with deliberate carrier
leak. All transmitted signals pass through a 12kHz filter as they leave the
board - this costs nothing since the filter is already present in the FM receiver,

66

and removes any broadband noise which the buffer amplifiers may have
introduced.
The CW transmitter uses the complete SSB system except that a keyed tone
is used as the audio input and the 500Hz filter is used instead of the 2.4kHz
filter in the SSB generator. This allows only a single frequency to go to the RF
clipper, rather than the several frequencies caused by harmonics from the tone
generator, which would result from the use of the 2.4kHz filter.
Like the simple SSB transceiver the majority of the transmit/receive switching is performed by switching power supplies and not signal lines. The power
switching itself, however, is performed by a relay which can be driven either
from a transmit/receive switch or by the VOX system. Mode switching, however, is performed by relays, so that when the transmitter and receiver are in
different modes some relays change state between transmission and reception.

TRANSCEIVER SYSTEMS
To use the transceiver board it is built into a system very similar to that used
for the Simple SSB Transceiver illustrated in Fig. 65. A small difference is that
if FM transmission is required provision must be made for the processed audio
from the board to modulate the VFO. Otherwise the two systems are identical except that rather more power supplies and function switching are required
with the multi mode transceiver.
Sub-systems may be omitted if a simple transceiver, or just a receiver, is
required. Similarly, the board may be built and operated as an SSB receiver,
then expanded to an SSB transceiver without RF clipping, then RF clipping
added, etc., as required.

CIRCUIT DETAilS
The circuit diagram of the complete transceiver board is shown in Fig. 69.
The whole circuit will be described but where SUb-systems are built entirely of
SL600 devices conventionally used no explanation of circuit configuration wilt
be given. If this is required the reader is referred to Section 1.
The SUb-systems into which the board has been divided are described
below.

The Mixer
The Anzac MD-108 mixer was chosen for its performance coupled with its
low price, but any hot carrier diode ring modulator with 50 ohm ports and adequate strong signal performance (the MD-108 wilt handle over 200mV RMS
adjacent channel signal) combined with low noise and under 7dB conversion
loss could be used euqally welt. The MD-108 has two ports with 5-500MHz
bandwidth and one with DC to 500MHz bandwidth. If the transceiver is used
with signals or VFO of under 5MHz it is important to ensure that this signal is
applied to the correct port.
It might be thought that the receiver performance on strong signals would be
improved by using a better diode ring, able to handle larger signals. This is not
in fact so: if the mixer is imp.roved the noise blanker and filter become the
limiting factors in the strong signal performance. A mixer with better high
or low frequency performance may, however, be substituted if required.

67

I
I
I

_____ -1

r------------I

Fig. 69

68

Multimode transceiver circuit diagram

--+-t----+..J

I
L _____________ _

- - ,,",Ss.DEMODULATOR
AM AGe

,---------~--------------------­

l

IOSQIJfLCH
IMUTING SIGIU,lIITRSI

I
1

I
I

I

I
I
I
I

I
-----4
I
I

I
I
I
I
I

SSB AGe

L _________

I

~

lOW

''''P~OANCE I
I
I

!~~A,~~~~

I

I

I
I
----- ~
I
vo,
I
I

I

I
I

10 Till

"HAT

I
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A"'IF'" MODULATOR
I ___________________
'''''.,~ :~:::
_______________________________ L

I

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~

69

The Noise Blanker
Probably as much work went into the development of this noise blanker as
into the rest of the receiver. It has excellent performance and causes very little
degradation of the receiver strong signal characteristics.
A noise blanker is a receiver which receives noise pulses, amplifies and
shapes them, and uses them to turn off the main receiver while noise is
present. As noise is not evenly distributed throughout the frequency spectrum
the noise blanker receiver should be operated in the same frequency band as
the main receiver.
This in turn suggests that the noise receiver and the main receiver be
common and that the blanking pulse be applied late in the main receiver.
However if a noise pulse is applied to a crystal filter it is stretched from its
original length of a few microseconds to as much as several milliseconds.
Blanking must therefore be applied before the crystal filters.
The noise blanker must therefore stop a noise pulse before it can reach the
crystal filter from the mixer. Furthermore if a blanking pulse has sharp (large
dV/dt) edges these will themselves act as noise pulses, negating the effect of
blanking the received noise.
There are therefore two conflicting requirements: the noise blanker must
act very quickly to prevent the leading edge of a noise spike from reaching the
crystal filter, and it must apply a blanking pulse with a slow rise time to the
noise gate to prevent the blanking pulse from acting as a noise pulse. The
only way these requirements can be met is to delay the signal between the
mixer and the filter in a linear delay line and to place the noise gate between
the delay line and the crystal filter.
Various forms of blanking gate were tried during the development of the
noise blanker - including diode modulators and single and balanced FETs but none of them gave better performance than an SL 1496 double-balanced
modulator. The circuit diagram of an SL 1496 is shown in Fig. 70 and a diagram
of the noise gate in Fig. 71. Transistors designated TR followed by a lower case
letter subscript are those internal to the SL 1496. Transistor designations using
numerals are employed for all other devices.
In this application pins 5 and 14 of the SL 1496 (IC1) are connected together
and the emitters of TRa and TRb are thus open-circuited. They are then connected externally to the rest of the circuit. When there is no blanking pulse
TR10 is turned off and TRc and TRf are turned hard on. With TRc hard on TRa
acts as an amplifier to signals on its base and its output goes, via TRc to the
XF9-B crystal filter. Since TRdand TRe are off no signal is applied to the
XF9-E filter.
When a blanking pulse is applied to TR10 it is turned on and TRc and TRf
turn off (slowly because of the resistor in TR10 collector and the 1 nF capacitor
between inputs 8 and 10 of the SL 1496) and TRd and TRe turn on. The signal
path is now to F4 and the F1 is isolated - noise cannot pass to the CW/SSB/AM
IF strip.
The noise blanker is not effective during FM reception and is not used.
Instead TR8 is turned on and this balances the modulator so that TRc, TRd,
TRe and TRf are turned on and Signals go to both IF strips. This is necessary
because the squelch is derived from the CW/SSB/AM strip in all modes,
including FM.

70

12

lOo-----+------+--------~

14o-----~------~--------------------~--------

Fig. 70

SL 1496C circuit diagram

1k
Fl
X F9- B

F4

'I-----iL__XF_9_-_E~~--------.-----+----

10k

;tf-.---{=:::J-- +12 V F M

Fig. 71

The noise gate

71

The diodes between pins 8 and 10 of the SL 1496 ensure that the switching
drive is at the correct level and the preset current source TR8 keeps the DC
current in the filter loads constant as the system switches from the unblanked
to the blanked condition.
The whole system is shown in Fig. 72. The noise receiver has its input via a
tuned circuit to prevent local oscillator leak from the mixer triggering the
system. The noise IF amplifier consists of an SL612C (IC2) and an SL613C (IC3)
which acts as a detector. Gain control is applied to IC2 to set the blanking level.
Pulse outputs from the detector in IC3 are buffered by a PNP transistor
TR18 to a simple monostable (TR6, TR7 and TR9) with a 10 microsecond
pulse. This pulse operates the noise gate. A 400 ns delay line between the
mixer and the noise gate ensures that the system is blanked before the pulse
that triggers the monostable arrives at the noise gate.
Lastly, a feature of the system is that it acts as a matching amplifier between
the 50 ohm mixer and the 500 ohm filters.
5,5FB

---1
_ !

H

ln

XF-9B

XF-9E

rL..F'FM
--~

+12V RX

560

lk

lk

10k

FROM
MIXER

330

r---1:=:::J..!..+12V FM

10k

4·7n

10k

4·7k

TR6- TRIO ARE

4·7k

Fig. 72

72

AN SL3046

The noise blanker

The AGC 'S' Meter and Squelch Circuit
As mentioned above the SL623C (IC14) operates as a carrier AGC system
during AM reception. It also operates in the same. mode during FM reception
but does not apply AGC to the FM IF, the AGC line being used only for squelch
and to drive the'S' meter. When the carrier oscillator is turned on, the' product
detector in IC14 operates and a signal is applied to an SL621C (IC12) connected to its output. The SL621 C is more sensitive than the SL623C and so it
takes over as AGC source to provide an audio derived AGC system for CW and
SSB reception. Since the output impedance of both the SL621C and the
SL623C AGC systems are high when they have no input they are both connected to the AGC line and do not load each other.
If fast AGC is required during tuning in the SSB and CW modes, the ICI2
may be turned off and control restored to the IC14. This will result in higher
outputs but faster decay when tuning from a strong signal. Some professional
receivers using SL621C circuits have facilities for dumping AGC from the
timing capaCitors but it was felt unnecessary to this design.
The AGC line from these two devices drives the second SL612C (ICB) in the
CW/SSB/AM IF strip directly and also goes to the squelch and'S' meter
circuitry shown in Fig. 73. TR3 acts as a buffer to drive the squelch circuitry,
and also as a diode drop (0.7V) to delay the AGC to IC7. The output of TR3 is
filtered by 1 kilohm and 100 nF and applied to a potentiometer ('Squelch
Level') and thence to the base of TR4, which acts as an inverter. The inverter
output drives TR5 which mutes the SL630C audio amplifier (IC15), by connecting pin 7 of IC15 to earth. A three-position switch which earths either TR4
collector (to disable the Squelch) or TR5 collector (to mute the receiver) is
included. Its centre position neither mutes the receiver nor disables the
squelch. If a mute position is not required, a single pole on/off switch may be
used.
As the AGC characteristic of SL600s is somewhat non-linear, a simple voltmeter on the AGC line does not make a good'S' meter since it tends to be too
sensitive to signal changes near the AGC threshold and not sensitivie enough
to large signals. The long-tailed pair TR1 and TR2 with the diode 012 form a
compensating circuit. All five transistors in this block of circuitry are on a single
chip, the SL3046, in a 14-lead OIL package. This saves board space and gives
a good match between TR1 and TR2.

The FM IF Strip and Detector
Double conversion is used in the FM receiver because of the difficulty of
providing adequate 'Q' at 9MHz for an NBFM quadrature detector. The 9MHz
output from the 12kHz-wide XF9-E filter F4 is amplified by an SL612C (IC17)
and is then mixed to 455kHz in an SL640C (IC20). A single tuned circuit is
used to remove the image and the signal is then passed to an SL624C working
as a limiting amplifier/quadrature detector. This receiver was developed
before the SL665 became available - otherwise a single 9MHz filter would have
been used and the SL624C replaced by an SL665C.

The CW SSB AM IF Strip
The IF strip is quite conventional. The output of the XF9-B 2.4kHz filter F1 is
applied to two cascaded SL612C amplifiers. The output of the second SL612C
(ICB) goes either to a 2.4kHz XF9-A or to a 500Hz XF9-M filter, (F3), depending

73

on whether the receiver is in SSB/AM or in CW mode. The filters are switched
by two small relays. After the filter there is another SL612C (IC12) and an
SL623C detector (IC14). Without a carrier oscillator IC14 acts as an envelope
detector for AM and generates carrier-derived AGC in this mode. When the
carrier oscillator is applied IC14 acts as a product detector for SSB and CW
and an SL621C (lC12) at the product detector output takes over the AGC.
The audio output line must be switched between the two detectors.

TO ICIS
ISL630,
MUTE

lRS

012
IN914

o1~

TO FIRST

L

TRl ~ lRS ARE
AN SL3046 IIC 20,

Fig. 73a AGe

SL612 AGe

ACG FROM
SL621C AND SL623C

"S" meter and squelch circuit

100
+12V. COM

TO

vox

+6V. COM

TR16

I.
TR16 AND TRl? ARE

AN

Fig. 73b Sidetone oscillator

74

SUOI ARRAY

The Carrier Oscillator
The carrier oscillator has four different frequencies: 8545kHz for the second
mixer in the FM IF system, 8998.5kHz for USB, 9001.5KHz for LSB and 9001
kHz for CWo The circuit is a conventional FET Colpitts oscillator (TR19) and
uses diode switching to select one of four crystals.
The output of the oscillator is about 1 volt RMS and is therefore reduced in a
potentiometer to the 200mV RMS required by SL640Cs. This potentiometer
acts as a virtually constant load to the oscillator and an output buffer is not
required.
If the crystals used do not oscillate at their nominal frequency, either the two
47pF capacitors between gate and source and source and ground may be
changed in value while remaining equal. Alternatively, where only one or two
crystals need trimming, provision is made for crystal trimming by a varicap and
a potentiometer for each sideband crystal.

The Audio Amplifier and Sidetone Oscillator

+

The SL630C audio amplifier (IC15) is driven from a 12V line. It is capable
of providing up to 200mW to a small loudspeaker but if a greater output is
necessary an additional audio amplifier should be provided. The output of
the SL630C is also applied to the VOX circuitry, TR11 to TR15. Gain is controlled by a voltage applied to pin 8 of IC15.
Since the output impedance of the SL630C is quite high when it is turned off,
and likewise that of the sidetone oscillator, the loudspeaker is connected
directly to both. The sidetone oscillator shown in Fig. 73, is an emitter-coupled
multivibrator keyed in the emitter of TR16. A signal is taken from the collector
of TR17 and applied to the transmitter audio input.
The sidetone frequency is 1kHz and the system relies on the CW filter to
produce a single tone output from the transmitter. If the 500Hz CW filter is
omitted the frequency should be raised to about 1750Hz to place the second
harmonic well down the SSB filter characteristic. In amateur transceivers an
accurate 1750Hz may have an additional use as a repeater access tone.

The Microphone Amplifier and SSB Generator
The audio from the microphone (or the CW from the sidetone oscillator) is
amplified by an SL622C (IC4). The SL622C contains its own AGC circuitry with
fast attack and slow decay so that its output is around 100mV RMS for over
60dB range of input. There is also a sidetone output which is not affected by
the AGC and is used to operate the VOX. R57 sets the microphone AGC
threshold and dynamic range. If R57 is open circuit, the threshold is 100
microvolts and the dynamic range is 60dS; if it is 1 kilohm the values are 1mV
and 40dB, and if it is 330 ohms they are 3mV and 30dB. C63 should be increased
to 0.05 microfarad if R57 is 1 kilohms and to 0.15 microfarad if it is 330 ohms.
The output from the SL622C is applied to the signal input of an SL640C
double-balanced modulator (IC9) whose carrier input is 8.9985 MHz or 9.0015
MHz from the carrier oscillator. The output is DSB which is applied to the
2.4kHz bandwidth 9MHz filter (F2) and one sideband removed to produce
SSS (USB if 8.9985 MHz is used, LSB if 9.0015).

75

The RF Compressor
The SSB produced in the system above is normal SSB. Its peak/mean power
ratio is fairly large, even though its mean power level is quite constant as a
result of the audio AGC. It is therefore amplified in a three-stage amplifier
consisting of an SL610C (IC11) followed by two SL613Cs (IC10 and IC13). The
SL610C is merely to provide gain but the SL613Cs are high performance
limiting amplifiers with symmetrical limiting. The signal emerging from this
limiting amplifier preserves its phase information but has had practically all
amplitude variation removed from it.
Such a clipped signal is rich in both harmonics and intermodulation
products, so it i~ immediately filtered in another 2.4kHz bandwidth filter (F1)
which removes both, but reintroduces some amplitude variation.
The above system is used to process all signals which are to be transmitted,
in whatever mode the transmitter is operating. However if a CW signal is being
sent, the first 2.4kHz filter (F2) is replaced with a 500Hz filter (F3) to ensure
that a single tone is applied to the clipper. After the second filter, however,
different modes are processed in different ways.
Single-sideband and CW signals are amplified in a two stage linear amplifier,
applied to a 12kHz filter to remove noise and sent to the mixer via the transmit
buffer.
When the transmitter is operating in AM or FM mode the clipped SSB is
demodulated in an SL640C product detector (IC6) to yield clipped audio, which
is then applied to the AM or FM modulators. The SSB clipping produces audio
with a slightly artificial sound which, however, is not unpleasant under strong
signal conditions, and is particularly easy to copy through noise.
The AM modulator is another SL640C (IC5) with carrier leak deliberately
introduced so that the output is AM rather than suppressed carrier DSB. This
modulator is used both in the AM and FM modes, but in the FM mode no signal
is applied to the signal input and the output is an unmodulated carrier. In
either case the output is amplified, filtered in the 12kHz filter (F4), and sent to
the transmitter via the transmit buffer and the mixer.
In FM mode the circuit transmits an unmodulated carrier. Frequency modulation is performed off the board by using the processed audio to modulate the
transceiver VFO during transmission.
The carrier on AM and FM is not, as one might expect, 9MHz. There is only
one carrier oscillator on the board and it is used during transmission to produce
clipped 8SB. It is therefore working at 9001.5kHz or 8998.5kHz, depending on
the position of the sideband selector. The AM or FM carrier is at the same
frequency.

The Buffer Amplifiers
The buffer amplifiers used between the various parts of the transmitter are
simple transistor or FET circuits. The first designs of the transceiver used
integrated circuits to perform these functions but this led to unnecessary
complexity and cost with no corresponding increase in performance.

The VOX (Voice Operated Transmit Relay)
A VOX circuit is one which switches a transceiver from receive to transmit
when it detects speech at the microphone. The obvious problem with such
circuits is to prevent them from reacting to signals from the loud speaker.

76

+12V. COMMON

R6l*

lOOk

lOOk
lk
TR15

FROM
LOUD
SPEAKER

10~

"

--..±..j]

+
lk

10
20~

TRT2 - TRIS ARE
AN- Sl3046

Fig. 74

VOX circuit

The simplest way to do this is to feed the loudspeaker signals to the VOX
circuit so that only microphone signals which are not also present in the
loudspeaker circuit affect its operation. This is quite difficult and is often liable
to cause spurious switching unless the system is carefully adjusted by the
operator to compensate for the microphone and the acoustics of the surroundings.
The system used in this transceiver is slightly different. The signal from the
microphone is gated by the internal signal to the loudspeaker so that no input
to the microphone will affect the VOX while there is a signal to the loudspeaker.
The only drawback to this system is that the VOX cannot operate during the
reception of non-syllabic noise. Such conditions are, however, unusual.
The circuit is shown in Fig. 74 and uses another SL3046 five transistor monolithic array. Positive half-cycles from the microphone amplifier SL622C
(which is powered during reception} turn on TR13 unless prevented by the
presence of a loudspeaker signal on TR11. The time constant of the gate
circuit is such that VOX action can occur in the spaces between words in
normal speech.
TR13 turns on TR15 via TR14. An integrator consisting of R61 and C98
controls the time which elapses between the cessation of speech and the
reversion to reception. For breakthrough CW operation (when the operator
listens between the dots and dashes of his own transmission) the time constant may be reduced. If the relay is a low power one it may be connected
between TR15 collector and + 12V, otherwise a PNP driver should be used with
an input resistor in its base circuitry.

Power Supplies and Switching
The transceiver board uses three +12V supplies. One is present during
reception, one during transmission, and one is common. There are three
+6V integrated circuit regulators on the board, one for each + 12V line, to
supply the appropriate SL600s. This type of regulation greatly reduces crosstalk via the supplies.
Mode switching is accomplished by applying + 12V to the relevant one of
the three mode lines: CW, FM, or SSB. The two unwanted lines are earthed.

77

Construction
The transceiver board is constructed of double-sided printed circuit material
and earth connections are made on both sides of the board - plated through
holes would remove this necessity but were not used in the prototype for
reasons of cost and ease of modification. As the board is very small for the
complexity of circuitry it carries some of the relay connections were wired.
The board diagram is Fig. 75a and the component location is given in Fig. 75b.
It would be almost impossible to make such a system stable on singlesided board but systems derived from this one and built on double-sided
board should not present any particular layout problems.
Table 5 Components for the multimode transceiver (Fig. 69)

INTEGRATED
CIRCUITS
ICl
IC2
IC3
IC4
IC5
IC6
IC7
IC8
IC9
IC10
IC11
IC12
IC13
IC14
IC15
IC16
IC17
IC18
IC19
IC20
IC21
IC22

SL 1496
SL612C
SL613C
SL622C
SL640C
SL640C
SL612C
SL612C
SL640C
SL613C
SL610C
SL621C
SL613C
SL623C
SL630C
SL612C
SL612C
78L06
78L06
SL640C
78L06
SL624

RESISTORS (ohms)
Rl
R2
R3
R4
R5
R6
R7
R8
R9
Rl0
Rll
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22

7R

470(NOB)
100(NOB)
56K
100
47K
lK
10K
5.6K
4.7K
680
4.7K
10K
lK
10K
4.7K
lK
220
220
560
lK
50
4.7K

R23
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
R64*
R65*
R66
R67t

*

t

33K
4.7K
lK
2.7K
lK
330
10K
560
10K
560
lK
10K
lK
lK
10K
lK
lK
lK
lK
4.7K
330
100
470
100
470
lK
10K
10K
82
10
560
lK
lK
2.2K
See text
470K
lK
lOOK
lOOK
1.8K
15K
lK
lK
4.7K(NOB)
15K

Vertical on board
May need selection

VARIABLE RESISTORS
RVl
RV2
RV3
RV4
RV5
RV6
RV7
RV8

10K
lK
lK
lK
10K
5K Lin.(NOB)
10K Lin.(NOB)
25K Lin.(NOB)

CAPACITORS
Cl
C2
C3
C4
C5
C6
C7
CB
C9
Cl0
Cll
C12
C13
C14
C15
C16
e17
C1B
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C3B

47p
O.lIlF
O.lI.1F
47pF
O.lIlF
O.lI.1F
O.lI.1F
4700pF
O.lIlF
O.lI.1F
1000pF
O.lI.1F
10pF
100pF
1000pF
O.lI.1F
1000pF
1000pF
O.lIlF
1000pF
O.lIlF
1000pF
1000pF
O.lIlF
1000pF
O.lIlF
1000pF
1000pF
1000pF
1IlF(T)
1000pF
O.lIlF
1000pF
lOIlF(T)
1000pF
O.lIlF
1000pF
1000pF

C39
C40
C41
C42
C43
C44
C45
C46
C47
C48
C49
C50
C51
C52
C53
C54
C55
C56
C57
C58
C59
C60
C61
C62
C63
C64
C65
C66
C67
C68
C69
C70
C71
C72
C73
C74
C75
C76
C77
C78
C79
C80
C81
C82
C83
C84
C85
CB6
C87

1000pF
1000pF
O.lIlF
4700pF
1000pF
1000pF
220pF
50pF
O.lIlF
1000pF
4700pF
O.OlIlF
O.lIlF
100I.lF(T)
O.lIlF
1000pF
O.lllF
1000pF
O.lIlF
10pF
10pF
1000pF
O.lI.1F
lOI.lF(T)
4700pF
330pF
1000pF
1000pF
1000pF
1IlF(T)
47IlF(T)
O.lIlF
1000pF
lOOIlF(T)
lOOI.lF(T)
1IlF(T)
lOOIlF(T)
47IlF(T)
O.OlIlF(T)
lOOIlF(T)
O.lIlF
1IlF(T)
4700pF
100pF
1000pF
lOIlF(T)
47IlF(T)
1000pF
0.5Il F(T)

Table 5 (continued)
C88
C89
C90
C91
C92
C93
C94
C95
C96
C97
C96
C99
ClOO
C101
Cl02
C103
Cl04
Cl05
Cl06
C107

O.lIJF
1000pF
lOOIJF(T)
2.2IJF(T)
lOIJF(T)
1000pF
1000pF
1000pF
lOIJF(T)
0.11JF
201JF(T)
101JF(,T)
O'lIJF(NOB)
10001JF(NOB)
1001J F(T)
1000pF
1000pF
101JF(T)
15pF(SOT)
4.7nF

NOB = Not on board
All !rW film types
Tolerance 5%
SOT = Select on test
All capacitors except Cl01
(which is aluminium electrolytic)
are either bead tantalum
(marked T) or miniature ceramic;
tolerance 20%

TI

6:1 Toroidal RF transformer

L1
L2
L3

3.11JH Nominal, slug tuned screened RF coil.
550IJH Nominal, slug tuned screened RF coil.
370IJH Nominal, slug tuned screened RF coil.

F1
F2
F3
F4

XFll-B
XF9-B
XF9-M.
XF9-E

Xl
X2
X3
X4

8545KH
9001.5KHz
8998.5KHz
9001Khz

KVG crystal filters

Parallel (30p) resonant
HC16 or HC25 crystals

RL1--6 National R5-12V miniature relays
Diode ring - Anzac MD108

TRANSISTORS
TRl-5
TR6-1 0
TR11-15
TRl6-17
TR18
TR19
TR20
TR21
TR22

SL3046C
SL3046C
SL3046C
SL301 C Dual transistor
2N3906 or similar PNP
2N3819 or similar N-FET
2N3819 or similar N-FET
2N918 or similar fast NPN
2N706 or similar NPN

Dl-8

lN914 or similar low capacity Si
switching diode
MV1 1
MBD101
1N914

D9
D10-11
D12

Delay line
Belfuse 0420-0400-05, or any delay line with
500 ohm ports, 300 to 800ns delay and less than
8dB insertion loss at 9MHz.

79

80

EXTERNAL CONNECTION
PIN 5, IC4, VIA Rl t Cl00

W9uodwoa J911!9aSUeJj apow!lInw qgL '[j!:J

+12V
SSB

AFGAIN~~

LOUDSPEAKER
(MUST BE
I(IIASED POSITIVE,
SEE CCT DIAGRAM I

NOTES' FH = FIXING HOLES
• LINK MAY BE BROKEN DURING
FAST TUNING TO DISABLE A G C

,...
CO

82

27MHz AM/SSB transceiver
Fig. 76 shows the circuit diagram of a dual converion AM/SSB transceiver
intended for use on 27MHz Citizens' Band. It has evolved from the versatile
multi mode transceiver described above but where the multi mode transceiver
is optimised for performance, this transceiver, being primarily intended for the
CB market, is optimised for economy.
Like the multi mode transceiver, this system is equipped with a noise blanker
but instead of a delay line uses a low-cost ceramic 10.7MHz IF filter (which
also acts as the first IF filter) as the delay element. The filter has a delay of
about 1.5 microseconds.
The receiver is conventional. A 27MHz tuned circuit is followed by an
SL 1610C RF amplifier and an SL 1641C mixer to the first IF of 10.695MHz.
After a 10.695MHz filter (which also acts as a noise blanker delay) the signal
passes through an SL1496C noise gate and on to the SL 1641C second mixer.
The noise blanker receiver is driven at 27MHz by the SL1610C RF amplifier
and consists of an SL 1613C amplifier and detector followed by a CMOS 4011
acting as a monostable to generate the blanking pulse to the SL 1496C.
The output from the second mixer, at 455kHz, is switched by diode switches
to one or other of two ceramic ladder filters - one with 2.4kHz bandwidth for
SSB and the other with 6kHz bandwidth for AM. The IF strip following the
filter consists of an SL 1611C and two SL 1612Cs and contains a simple ceramic
filter to minimise broadband noise. An SL 1623C AM/SSB detector is used
which generates AGC during AM reception and an SL 1621 C generates AGC
during SSB reception.
Squelch is obtained from the AGC line by an SL748C op. amp. acting as a
threshold switch. Its output switches the audio path by turning on and off the
bias to a transistor amplifier. The audio output stage uses a TBA800 3 watt
integrated circuit audio amplifier.
The transmitter uses an SL 1626C as a microphone AGC ampli.fier and an
SL 1641C as either an AM modulator or as a DSB generator, depending on
switching. The 455kHz AM or DSB is passed through the appropriate filter and
mixed to 10.695MHz, where it is refiltered and mixed again to its final 27MHz
frequency. Both mixers are SL 1600 devices - the SL 1640C and the SL 1641C
respectively:
The transceiver, like the others described above, requires the addition of
oscillators, an RF power amplifier and power supplies. It is intended for use
with the Plessey SP8921/8922 CB synthesiser but also requires an oscillator
which may be switched between 453.5kHz, 455kHz and 456.kHz for use as the
receiver BFO and the carrier oscillator in the transmitter.
Power supplies of +6V and +12V are required, which are switched in
various ways during transmission and reception. All supplies must be well
decoupled at HF and LF.

83

12VRX~~__________________~==========

CFS455J

10

~~5 ~~Z -::::;:1l--..---------------------IAMI

6V TX ~~---j--~.

L--------------+--r--

~1

Fig. 76

84

Dual conversion AM/SSB Citizens' Band transceiver

1---------------------------------------------------,
I
I

I
-+12V AM
I~

i

~VSSB

I

J

- - - - - - + -I- - - - - - - - + - - -------------;-+--____________________ J

----------l--

lOOk

~r---I~---~~-10~

J;01~

5VRX~r__t--~~---~-t_-~~r_---~-----~

I

220~ll

.--~~~IQ~
I

ALL CERAMIC

FILTERS

LOUDSPEAKER
OUTPUT

h40RATA

Oc:.

Introduction to SL6000 Series
The Plessey Semiconductors SL6000 series of radio linear circuits extends the
concept of the 'building block' approach to wider systems. Each device features
advanced circuit techniques which result in higher levels of integration, lower
power consumption or exceptional performance. All products are available in
plastic and metal can or ceramic packages.

SL6000 PRODUCT RANGE
IF AMPLIFIERS/DETECTORS
SL6600
SL6640
SL6650
SL6690
SL6700

FM
FM
FM
FM
AM

Double Conversion with PLL Detector
Single Conversion, audio stage (10.7MHz)
Single Conversion (10.7MHz)
Single Conversion, low power for pagers (455kHz)
Double Conversion

AUDIO
SL6270
SL6290
SL6310

Microphone Amplifier with AGC to give 'constant' output
SL6270 plus speech clipper, buffer and relay driver
Switchable audio amplifier (400mW/9V/80hms)

SL6600C
LOW POWER IF/AF PLL CIRCUIT FOR NARROW BAND FM
The SL6600 is a single or double conversion IF amplifier and detector for FM
radio applications. Its minimal power consumption makes it ideal for hand held and
remote applications where battery conservation is important. Unlike many FM
integrated circuits the SL6600 uses an advanced phase locked loop detector
capable of giving superior signal-to-noise ratio with excellent co-channel interference rejection, and operates with a second IF frequency of less than 1MHz.
Normally the SL6600 will be fed with a first IF signal of 10.7 or 21.4MHz; there is a
crystal oscillator and mixer for conversion to the second IF amplifier, a PLL detector and squelch system.
IF Amplifiers and Mixer
The SL6600 can be operated either as a single conversion circuit with a maximum recommended input frequency of 800kHz or in a double conversion mode
with a first IF of the inputfrequency(50MHz max.)and a second IF of 100kHzorten
times the peak deviation, whichever is the larger. The crystal oscillator frequency
can be equal to either the sum or difference of the two IFs; the exact frequency is
not critical.
The circuit is designed to use series resonant fundamental crystals between 1
and 25 MHz.

87

When a suitable crystal frequency is not available a fundamental crystal of one
third of that frequency may be used.
When a single conversion circuit is required a 6.ak resistor should be connected
in place of the crystal and a further 2.7k resistor connected between pin 1 and
earth. The overall gain of the circuit will be reduced by 12dB with this technique.
A capacitor connected between pin 4and ground will shunt the mixer output and
limit the frequency response of the input signal to the second IF amplifier. A value
of 33pF is advised when the second IF frequency is 100kHz.

NOTE ~ RESISTIVE
AT PIN 4

IMPEDANCE

= 25kn. (TYP),

36k.n (MAX)

AUDIO

OUTPUT

SQUELCH
OUTPUT

Fig. 22 SL6600 Block diagram

Phase Locked Loop.
The Phase Locked Loop detector features a voltage controlled oscillator with
nominal frequency set by an external capacitor according to the formula (30/f)pF
where f is the VCO frequency in MHz. The nominal frequency may differ from the
theoretical but there is provision for a fine + 10% frequency adjustment by means
of a variable resistor between the VCO output pins; a value of 470k has negligible
effect while 47k (recommended minimum value) increases the frequency by
approx. 10%.
The loop filter is connected between pins 11 and 12; a 33k resistor is also
required between pin 11 and Vcc.
The values of the filter resistor R2 and capacitor C1 must be calculated so that
the natural loop frequency fn and damping factor ~ are suitable for the FM deviation and modulation bandwidth required. Values of 6.2k and 2.2nF are recommended for ±5kHz maximum deviation and 3kHz audio bandwidth when the
second IF frequency is 100kHz. These give fn = 20kHz ~ = 0.707.

88

Squelch Facility

When inputs to the product detector differ in phase a series of current pulses will
flow out of pin 7. This feature can be used to adjust the VCO; when a 1mV unmodulated input signal is applied to pin 18 the VCO frequency should be trimmed
to maximise the voltage on pin 7.
The squelch level is adjusted by means of a preset variable resistor between pin
7 and Vcc to set the output signal to noise ratio at which it is required to mute the
output. The capacitor between pin 7 and ground determines the squelch attack
time. A value between 10nF and 10f.LF can be chosen to give the required
characteristics.
Outputs

High speed data outputs can be taken directfrom pins 11 and 12 but normally for
audio applications pin 8 is used. A filter network will be needed to restrict the audio
bandwidth and an RC network consisting of 4.7k and 4.7nF may be used.

0·1).1

1QOk

S~~~i~H
ADJUST

10-8 MHz

OR
10·6 MHz

'---c==}----<~--<> OU~~UT

'--+-----'-'-''---+----0 ~~~~~~H

POSSIBLE FREQUENCIES
IN RANGE 455kHz-25MHz

Fig. 23 SL6600 application diagram (lstlF= 10.7MHz, 2nd IF= 100 kHz)

LOOP FILTER DESIGN

The design of the loop filter determines the allowable deviation of the
received FM, the bandwidth of the modulating audio and the signal-to-noise
ratio which may be achieved. With wide-deviation signals the filter may be
omitted altogether and the system will work perfectly well, but with a somewhat reduced signal-to-noise ratio which is nevertheless quite acceptable
in many applications. The filter (Fig.24) iconsists of a resistor and capacitor
(R2 and Cl) in series between pins 11 and 12. The external 30 kG resistor
mentioned above produces a composite resistor, R1, of 20 kG formed by the
series connection of the two resistors on the chip and the external resistor in
parallel with one of them.

89

---------,
INTERNAL
CIRCUITRY

I

Rl
20k

lVCC

I
[}Ok

RA
[ 15k

I
I
I
I

IT"

15

r RS

-

[133k

T,

R2

R2

11

27rfn = ( Ko Ko

Cl

I

Cl

112

_

1-

-

2

012

I
I

+ T2

)~

( r( )
Ko Ko

+ T2

T1

2"

+ 1

T

2

Ko Ko

I
_______ --1

Fig. 24 SL6600 loop filter circuit

The loop constants of the SL6600 are:Ko
= 2.4fo Radian.slVolt second
KD
=~ 2.8 Volts/Radian
R1
==20kO
KoKD = 6.7fo sec- 1
Other variables used
fo
i.lf
fn
fm

in driving the loop filter are:The VCO centre frequency
The peak deviation
The natural frequency of the loop
The maximum modulation frequency
~e The maximum phase error in the loop
~
The damping Factor

The values of fm and i.lf are part of the system specification and together
with fo specify ¢e. The VCO centre frequency is generally chosen to be
100kHz or 10i.lf, whichever is the greater. Maximum frequency is 1MHz. The
damping factor, ~, is usually chosen to be 0.707. Fig.25 shows the relationship
between ¢e, fm and i.lf for ~ = 0.707.
10

09

I

08
07

"'" "'-

/"

I
/V

/

04
03

/'

0·2

0-2

/

0-3

i
0-4

0·5

0-7

t - c-

'"

"-

'-0

"'"',

1m

t;;Fig. 25 Phase error for damping factor

90

=

0.707

EXAMPLE

t,f

5kHz; fm

=

=

3kHz, fa

Therefore rPe max

100kHz

=

o 93t,f

0.93 x 5 x 103

fo

100 x 10

= --- =

3

=

0.046 radians

The problem now is to deduce the value of fn from Fig. 4; this is an iterative process
(i) Putfn

=

fm
10kHz. Thereforefn

from Fig. 4 (/)e

(Ii) Putfn

=

3

10

0.3x5x103
10 x 103

=

fm
20kHz. Thereforefn

from Fig. 4 rPe

= -

20 x 103

0.3

0.15 radians (too large)

=

= -

3

20

0.17 x 5 x 103
=

=

=

=

0.15

0.043 radians,

which agrees closely with the required value. Knowing the natural frequency the loop
time constants can now be evalualed1

+t

1

2

2D
t2 = 2rrfn

1,

=

6.77

K KD
(2rrfn)2

=_0
__

=

317psC

X

10 3

0.707
rr x 20 x 103 = 11.2ps

= -

1,

R,

=

1.6nF

91

SL6640 and SL6650
for single conversion receivers with quadrature detectors
The SL6640 and SL6650 are illustrated in Fig.26. Each consists of an IF
limiting preamplifier, a main limiting amplifier, a quadrature detector, a
squelch system, and a DC audio gain control. In addition, the SL6640 contains
a low-power audio output stage.

MAIN

r-;;;o-;;, --,

~--l

L_-.__ ...l1---0
POWER

AMP

I ___ I ___________ JI

~

~

I
I

Fig. 26 Block of SL6640 and SL6650 (broken line applies to SL6640 Only)

The IF preamplifier has a bandwidth of 25 MHz, a gain of about 46 dB
(200 times), and an input impedance of 5 kG shunted by 2 pF. It consists of
five cascaded long-tailed pairs and has excellent limiting characteristics.
The main IF amplifier also has a bandwidth of 25 MHz but its gain before
limiting is about 60 dB (1000) and it consists of six long-tailed pairs. The third
and sixth of these stages conta.in detectors, the outputs of which drive the
squelch system. The output of the limiting amplifier feeds a double-balanced
modulator and also an external phase-shift circuit which in turn feeds the
other port of the double-balanced modulator. This double-balanced modulator
thus acts as a quadrature detector. The quadrature detector in the SL6640
and SL6650 has very good performance when demodulating narrow band
FM signals, even when working with intermediate frequencies of up to 21.4
MHz. This is because at over 50 kG, the impedance of the quadrature port is
high and so the Q of the quadrature circuit is not impaired by being loaded,
as is so often the case with integrated, circuit quadrature detectors.
The external phase shift circuit is fed via internal capacitors of only 2 pF
and so the quadrature circuit works well only at about 4.5MHz and above.
The SL6640 and SL6650 cannot, therefore, be used at the common 455kHz IF.
The SL6690 (see below) works very well at this frequency, however, and
should be used when 455kHz operation is required.
The audio output from the quadrature circuit goes to an audio amplifier
which is DC-controlled to allow the use of remote gain control. The output of
the SL6650 is taken from this gain control, but the SL6640 has an extra audio
amplifier capable of driving a small 80 loudspeaker.
The squelch system is driven by the detectors in the IF strip and contains a
comparator which requires an input to set the squelch level. A resistor between

92

this programming input and the squelch output provides hysteresis to the
system. In the SL6650 the squelch system merely provides a DC output to
indicate the presence of a signal larger than the squelch threshold but in the
SL6640 the squelch controls the power supply to both the detector and the
audio stages. The standby power of the SL6640 is thus the lower even though
it is the more complex circuit.
The SL6640 is manufactured in an 18 lead DIL package and the SL6650 in a
16 lead DIL. The devices are designed so that as many as possible of their
pins are common i.e., pins 1 to 6 are identical and pins 13 to 18 of the SL6640
are equivalent to pins 11 to 16 of the SL6650 and only the pins around the
audio stages differ. This allows similar board layout to be used in radios using
the SL6640 or the SL6650. In the pin-by-pin description which follows, pin
numbers are given for the SL6640, those of the SL6650, where they differ,
are given in brackets e.g., pin 18 (16).
Pin 1 is the bias point for the main IF amplifier. It must be decoupled
effectively by an RF capacitor to ground and connected by a coil or resistor
to the IF input, pin 14 (12). If a resistor is used, it should provide the correct
match for the interstage filter; if a coil is used it will probably be part of the
filter and must not have any DC connection to ground. The decoupling capacitor must be at least 0.01 ~F.
Pin 2 is the squelch programming point and pin 3 the squelch output pin.
The squelch level is set by a 470 kG variable resistor (which should be increased to 1 MG if supplies of over 6V are used) in series with a 47 kG resistor
between pin 2 and ground. Squelch sensitivity increases with the value of the
variable resistor. Pin 3 is at a high potential when no signal is present and
drops to near ground potential when a signal is detected. The output current
from pin 3 is less than 2 mA but it may, of course, be buffered if necessary.
The decoupling capacitor of 0.33 ~F on pin 3 prevents brief breaks in signal
(such as mobile flutter) from squelching the circuit. Hysteresis in the squelch
is obtained by a resistor connected between pins 2 and 3. The amount of
+5V

---.,
!
SL6650

!
!

I

" 7k

I
I
I

SQUELCh
PROGRAM

I
I

L ___

6k

SL3046
E __________
JI
2k

Fig. 27 . S' meter circuit for use with SL6650

93

hysteresis depends on the squelch threshold, the resistor value and the
supply voltage. At 6V supply a 390 kO resistor gives 3 to 4 dB hysteresis at
10 I1V squelch level and about 10 dB at 100 I1V squelch level. Larger resistors
are necessary at higher supply voltages and the minimum possible hysteresis
rises to about 7 dB with a 1.5 MO resistor and a 9 V supply. Despite its variation with supply voltage, the squelch is quite stable with temperature and
alters by only 1 to 2 dB as the circuit is temperature cycled. If squelch is not
required the SL6650 squelch pins may be used, with an SL3046 transistor
array, to drive an S meter as shown in Fig.27. The system consists of a
negative feedback amplifier and is not possible with an SL6640, where the
internal squelch must always be used.
The quadrature circuit is connected between pins 4 and 5. This can consist
of an LC tuned circuit resonant at the centre of the IF passband, or one of the
commelcial crystal quadrature circuits for NBFM, or even a ceramic interstage
filter such as is made for broadcast receiver applications. Ceramic filters
usually need to be tuned by a parallel trimmer capacitor and their efficiency
as quadrature elements can vary widely from batch to batch. They are not,
therefore, the best quadrature elements to choose although they are nonmicrophonic and smaller than most coils. The resistive element of the impedance between pins 4 and 5 is over 50 kO and so has little effect on the Q of a
wound quadrature element. Narrow FM can thus be demodulated, even with
an LC quadrature element, with an excellent signal-to-noise ratio - 50 dB or
better. If a lower Q is required the resistance between the pins may be reduced
by the use of an external resistor.
No DC path must exist between pins 4 and 5 and any other point, but they
themselves may be connected together if required. It is better to have a DC
path between them than not, so long as it is not at the expense of the Q of the
quadrature element.
The DC volume control consists of a fixed resistor of 47 kG in series with a
variable resistor of 470 kG connected between pin 6 and ground. The gain
range is typically 70 dB (3000:1) and gain is minimum when resistance is
minimum.
Pins 12 and 13 of the SL6640 and pin 11 of the SL6650 are the supply pins.
SL6640 pin 12 is the audio output stage supply while pin 13 supplies the
remainder of the circuit. In the case of the SL6650 pin 11 is the supply connection for the entire circuit. The supply voltage is normally +6V but the
circuits will work with supplies between +5V and +9V. Consumption of
the SL6640 at 6V is 3.5mA (squelched) and 10mA (unsquelched), or more if
audio power is being supplied, while the SL6650 draws 6mA in either case.
Pin 12 of an SL6640 may be left unconnected if for any reason the aUdio
stage is not required but it must not be used with more than 0.5V difference
in potential between pins 12 and 13.
The power supplies must be well decoupled at RF with at least 0.111F
having low inductance and short leads. The supplies should also have low
audio ripple and it is necessary to decouple the SL6640 supply very thoroughly
at LF if the audio stage is to operate at its highest powers and retain its AM
rejection.
Pin 14 (12) is the input of the main IF amplifier and should be biased by
being connected to pin 1 as described above. The input impedance is 5 kO
shunted by 2 pF.

94

Pins 15 (13) and 17 (15) are decoupling points within the circuit and should
be decoupled to earth by good RF capacitors, preferably 0.1 IJF and at least
0.01 IJF. Inadequate decoupling of these pins causes poor AM rejection and
can cause instability.
Bias circuitry for both the main amplifier and the preamplifier is shown in
Fig.2R The preamplifier input is pin 16 (14). It is not self biased but is fed with
bias from pin 18 (16) via a total of about 15 kO. The input impedance of the
preamplifier is 5 kO shunted by 2 pF. If, as is common, the preamplifier is fed
from a filter requiring a precise match, the value of resistor R2 should be
chosen to provide this. The source impedance driving the preamplifier should
be 7500 or less to prevent instability. The input signal should be fed to pin 16
(14) via a capacitor or other DC block. The sum of resistors R1 and R2 should
be 15 kO and their junction well decoupled at HF. The noise figure of the
preamplifier is 7 dB when driven by 350 O.
The preamplifier output is pin 18 (16) and it has an output impedance of
300 O. Signal is taken from the output of the preamplifier to the input of the
IN~ll-o~OI_ _ _ _ _ _ _~

Fig. 28 Bias circuit for SL6640 and SL6650

main amplifier via an interstage filter. This is a roofing filter to provide some
limitation of noise bandwidth, not the primary selectivity of the receiver which
must be provided by a high performance filter placed before the preamplifier.
This filter, therefore, need have neither a good shape factor nor large stopband attenuation. Any simple filter is suitable but at 10.7 MHz, cheap ceramic
filters are particularly useful since they are small and require no setting-up.
Much work with the SL6640 and SL6650 has used Murata SFE 10.7 MA filters
since they match the output impedance of the preamplifier.
The final part of this section deals with those pins whose functions differ
between the SL6640 and the SL6650. First the SL6640. Pin 7 is the output of
the DC controlled audio preamplifier and is an emitter follower with a low
current tail. It will only drive high impedance loads and needs an HF rolloff
0.01 IlF
capacitor to earth of
where f is the desired rolloff frequency in kHz.
f

95

In normal use pin 7 is connected to pin 8, the input to the output stage, by a
0.1 IJF capacitor. Pin 8 is biased by connecting it to the centre of two 220 kO
resistors connected between the positive supply and ground! in series.
Pin 9 of the SL6640 is the inverting input to the output stage and is used
to provide negative feedback to define both DC operating point and
stage gain. The feedback resistor from the output pin 11 is 120 kO and the
gain-defining resistor (which is connected from pin 9 to ground via an isolating
capacitor of 1 IJF) can be any value greater than 1.2kO. The gain is equal to
the ratio of these two resistors, and hence when the smaller is 1.2 kO the gain
is 40 dB (100). Attempts to achieve higher gain leads to instability and, more
important, excessive distortion since the open loop gain of the output stage
is only some 55 dB.
Pin 10 is earth and pin 11 is the audio power output. Pin 11 is decoupled to
earth with 0.22 IJF to ensure HF stability and drives its load via a 100 IJF
capacitor. With care, and a 9V supply, the SL6640 will drive an 80 loudspeaker
at 250mW but a more practical figure is around 175mW. A complete circuit
diagram of an SL6640 in use is shown in Fig.29.

1O~~ :UOIO

lJ""

* Rf

CHOSEN TO MATCH SOURCE

Rf max

= 1 k .n.

Fig. 29 10.7MHz application of SL6640

Pins 7 and 9 of the SL6650 are unused. Pin 8 of the SL6650 is earth and
pin 10 is the audio output. This output appears on the open collector of a
transistor and so must be connected to the positive supply by a resistor generally 10kO. Audio is taken through a capacitor and the pin is also decoupled at HF.
by a capacitor of

96

0.015 IJF

where f is the cutoff frequency in kHz.

SL6690
ultra-low power consumption quadrature detector system
The SL6690 block diagram is shown in Fig. 30. The circuit consists of a limiting IF
amplifier which drives a quadrature detector, an LF amplifier and Schmitt trigger
(which can be used either as a signal-ta-noise squelch system orasa squarer when
the circuit is used in a pager), and a voltage regulator which uses an external PNP
transistor.

~.~_l'>-...

13

~

~-V-~'

12

15

TONE

SCHMITT

AMPLIFIER

TRIGGER

DEMODULA TOR

14

16

11

Fig. 30 SL6690 block diagram

The IF amplifier has a bandwidth of 1.5 MHz, making the circuit particularly
useful at the popular communications and paging IF of 455 KHz. Its input
impedance is 20 kO shunted by 2 pF and its output impedance is about 2 kO.
Bias is obtained by DC feedback from the outputs to the inputs.
The quadrature detector is a conventional double-balanced modulator using
transistor tree techniques. The quadrature circuit is an external LC tuned
circuit and the capacitors driving the quadrature circuit are also external,
which allows the detector to be used down to VLF as well as up to about
1.5 MHz.
The LF amplifier has a gain of 54 dB and is biased by a DC connection
from its output to its input. It is an inverting amplifier so its gain and frequency
characteristics may be defined by negative feedback. The Schmitt trigger is
driven directly by the LF amplifier. Its output is a free collector which may be
connected to either Vee (the regulated supply) or the unregulated supply rail.
In its ON state it will sink up to 150 IlA.
The regulator, which requires an external series PNP transistor, allows the
SL6690 to work from supplies between +2.5 and +6V. The external transistor
is necessary because monolithic PNP transistors have poor h'e at very low
current levels.
Pin 1 is the Schmitt trigger output, a free collector which can sink up to
150 IlA when the transistor is turned on and can rise to either Vee or some other
positive rail up to +6V when turned off. The input to the Schmitt trigger and
the output of the LF amplifier are connected internally and the node brought
out to pin 2. Bias must be taken from this pin to the LF amplifier input, pin 3,

97

via a resistance of 50 kG or less. The LF amplifier inverts and its gain and
passband may be defined by negative feedback. An output may be taken from
pin 2 and the Schmitt trigger left unused in which case no connection need be
made to pin 1. The bias of the amplifier/Schmitt combination is sufficiently
accurate to give the Schmitt an output mark-space ratio of between 0.9:1 and
1.1:1 with a sine wave input to the amplifier. The LF amplifier input impedance
is 50 kG and its open loop gain roughly 54 dB.
No DC connections should be made from pin 3 except the bias connection
to pin 2; all inputs should be coupled via capacitors. To prevent HF instability
2.2 kG in series with 120 pF should be connected from pin 2 to ground.
The output of the quadrature detector is pin 4 and its output impedance is
1 kG. The detector will give an output of 10 mY/Degree phase change and
distortion of about 3 per cent (more if a ceramic resonator is used as a
quadrature element). A single filter capacitor removes RF from the detected
output.
The quadrature circuit is connected between pins 5 and 6 and may be a
parallel tuned LC circuit or a ceramic resonator. The port has an input impedance of 50 kG shunted by 2 pF. The quadrature circuit mayor may not present
a DC path between the two pins. Use of ceramic quadrature elements usually
results in greater distortion than the use of LC elements but such ceramic
elements occupy less space and do not require adjustment. The quadrature
circuit is driven by the output from pins 7 and 8 via two capacitors. Pin 7 drives
pin 5 and pin 8 drives pin 6. The value of the capacitors depends on the
frequency of operation and the quadrature circuit used.
Pins 9 and 10 are the outputs of the IF amplifier and are used to provide
bias to its inputs. A 100 kG resistor is connected from pin 10 to pin 12 and pin
12 is grounded at AC by a capacitor. Pin 9 is connected to pin 13, the signal
input pin, by another 100 kG resistor in series with a resistor of the correct
value to terminate the IF source. The junction of the two resistors is decoupled
at RF by a low inductance capacitor. The IF input is applied to pin 13 from the
IF filter, via a coupling capacitor if necessary to isolate pin 13 at DC.
Pin 11 is earth and pins 14, 15, and 16 the supply/regulator pins. The supply,
which may be between 2.5V and 6V is applied to pin 16 and to the emitter of a
high gain PNP transistor whose base is connected to pin 15 and collector to
pin 14. Pin 14 is stabilised at 2V and must be thoroughly decoupled at RF by a
0.1JlF capacitor. The SL6690 may be turned on in 12 milliseconds or less so
the power supply may be strobed in paging applications so that the mean
power dissipation in the circuit is an order of magnitude lower than its
normal 2mW (1 mA @ 2V).

FM RECEIVERS USING SL6000 SERIES
The SL6600, SL6640, SL6650 and SL6690 are intended for use in NBFM
receivers - mobile, hand-portable, base station and paging. They are all
intended for use as IF Amplifier/Detector/Squelch modules and, of course,
the SL6640 has a low power audio output stage.
The circuits, having low power consumption and, indeed, limiting amplifiers,
have low resistance to intermodulation (although they have excellent dynamic
range) and must be used after the main selectivity of the receiver. Modern
receiver design emphasises strong signal performance even at the expense
of sensitivity and hence front ends having much gain are not popular. This can

98

leave an uncomfortable gap between the 2 to 41lV output from a receiver filter
and the 10 IlV or so that these circuits require to give an adequate signal-tonoise ratio. Redesign of the front end to give slightly more gain is possible
and certainly the easiest solution but it may produce an unacceptable reduction in intermodulation performance. An amplifier is therefore needed between
the filter and the SL6600/40/50/90.
This amplifier can be a convenience (some filters have matching impedances so high that even the input impedances of these circuits are embarassingly low) but, preceeding as it does a very high gain integrated circuit, it
can suffer from stubborn instability. It also increases the power consumption
of the receiver which is annoying in a hand-portable, although a handportable with its limited antenna is most likely to be able to tolerate a higher
gain front end and hence least likely to need an extra stage of IF gain.
Suitable amplifiers may be made with a single transistor or FET and two
circuits are shown in Fig.31. The FET circuit uses more current and an FET
with a good performance at 1 mA and a low pinch-off voltage is required. The
transistor circuit is far less demanding but has a lower input impedance
(which depends on hfe and Cob and will vary from device to device). These
amplifiers must be very well isolated if the receiver is to be stable and the
powerful decoupling of the transistor circuit is a point in its favour.

100

10k

,----+-c::::Jr- +6V
1k
~

r-----....-

TO INTEGRATEO·
CIRCUIT

L __ . . . TO INTEGRATED
~

2N3819

CIRCUIT

200

Fig. 31 FET and bipolar buffer amplifier

Apart from the occasional necessity for a low-gain preamplifier these
circuits present few problems and are very easy to use. As mentioned above,
some attention must be paid to layout to isolate input and output, particularly
at the same frequency, as much as possible. Other points to be remembered
are the use of non-inductive capacitors (many capacitors are inductive at
frequencies as low as 5 MHz) and adequate decoupling of all bias points and
power supplies - in connection with this it is worth remembering that it is
useless to use a good RF capacitor with short leads if the printed connection
to it is long and narrow.
It is not intended to describe in detail the design of any complete receivers
using these circuits. However, a review of the various types of receiver where
these circuits may be used and the considerations affecting such use is given
below.

99

LAND MOBILE RADIOS

In the VHF or UHF bands land mobiles use narrow deviation FM (between 1.5
and 12kHzM) and generally use a first IF of 10.7 or 21.4MHz. Transceivers can be
hand-held or vehicle mounted. For hand-held transceivers the choice is between
the SL6600 which has low power consumption and can be strobed and the SL6640
which has an integral output stage. The signal-to-noise ratio of either circuit is
adequate when used with the recommended circuitry but there is a performance
difference. The capture effect of a PLL detector is much better than that of a
quadrature detector: a receiver using an SL6600 will capture the stronger of two
co-channel signals even if it is only stronger by 2 to 4dB. The SL6640 will be
affected by a co-channel interfering signal until it is 20dB or more below the
wanted signal. Both features can be valuable; some (including military) users need
to know of other signals on-channel while others, particularly in' areas where
channels are shared with space diversity, prefer systems which ignore lOW-level
co-channel interference.
An advantage of the SL6640 is that it has only one conversion, saving a
crystal (although the crystal used with the SL6600 need not be expensive
since the main selectivity of the receiver preceeds the SL6600 and slight
frequency drift in the second crystal oscillator will not move the signal out
of the detector or squelch passband) and eliminating the possibility of
'birdies'from a second oscillator. Most manufacturers' quadrature detectors,
having been designed primarily for TV use, require a low IF if they are to
give an adequate signal-to-noise ratio at low deviations but the SL6640 and
SL6650 are capable of giving over 50dB signal-to-noise ratio with deviations
as low as 1.5kHz at an IF of 10.7MHz.
In land mobile applications with FM deviations in the range 1.5 to 12kHz
the SL6600 is used with a second IF of 100kHz. The design of the loop filter
depends on the deviation and audio bandwidth (generally 3kHz for speech)
as mentioned above. The double conversion can ease problems of instability
if it is necessary to use an amplifier between the quartz filter and the SL6600
since the total gain of the first IF is not so high.
PAGING RECEIVERS

Using the SL6690 a paging receiver can run on only two cells and consumes
only 2 mW, which may be further reduced to as little as 100llW if the receiver
is strobed. Such pagers are small, simple, inexpensive, and use few components.
BROADCAST F.M. RECEIVERS AND TV SOUND IF SYSTEMS
These can use the SL6640/50 merely by using a quadrature element with
lower Q to accommodate the wider deviation. The circuit alteration can be as
simple as the addition of a resistor between pins 4 and 5 to load the quadrature coil, although the main selectivity of the receiver must be suitable for the
bandwidth of the new type of Signal. The SL6640 is especially useful in
portable FM receivers in that it will supply adequate power to a loudspeaker
but consumes only a few milliamps, porlonging battery life.
The SL6600 is less suitable for broadcast applications, although it works
very well when it is used with a second IF around 800kHz and gives particularly low distortion due to its PLL detector. Its disadvantage is the cost of the
crystal in the second converter although this is not too great and might be
overcome by the use of a series resonant LC tuned circuit.

100

OTHER APPLICATIONS
These circuits can be used in various applications, including microwave
and telemetry receivers and, with the SL6640/50, simple SSB receivers
requiring very low power.
The choice of circuit in any application depends on a number of factors
including deviation and type of modulation. In general, providing the shift is
not too great, the SL6600 is better for RF FSK, although the loop filter design
requirements will differ from those described above when the modulation
departs so far from sinusoidal. On the other hand the SL6640/50 will cope
with deviations of 2 to 3MHz providing an IF of twenty-odd MHz is used and
the quadrature element has low enough Q.
Using the SL6640/50 as an SSB receiver involves replacing the quadrature
circuit with a BFO so that the detector works as a product detector, and
applying the AGe, preferably audio-derived with an SL621 or similar system,
to an amplifier preceeding the SL6640/50 to prevent its IF amplifier from
limiting.

101

102

HIGH
SPEED
DIVIDERS

103

Introduction to SP8000 series
The SP8000 Series is a range of high speed digital dividers using Eel
techniques. Devices with division ratios from --:-2 to --:-256 are available and
some types operate at frequencies up to 1.5GHz. To describe the various
types in full is outside the scope of this book. However, since high speed
dividers have numerous applications in radio systems, a brief description of
the range and some notes on applications for the circuits will be given.

SP8000 PRODUCT RANGE
N

<'

J:

:=;

:;;

Temperature
Range (OC)

":>c:
"

'"

.Q

~"

is

Product

~ SP8720A

%

SP8692A
SP8692B
SP8740A
SP8740B
SP8741A

9) SP8741B

%

SP8691A
SP8691B
SP8743A
SP8743B

~
11

SP8690A
SP8690B
SP8647A
SP8647B
SP8643A
SP8685A
SP8685B
SP8680A
SP8680B

~
22

SP8785M
SP8785B
SP8786M
SP8786B

-55 -40
+125 +85

•
•
•
•
•
•
•
•
••
•

-30
+70

0
+70

..
><

:=;

•
•

200
200
300
300
300
300
200
200
500
500
200
200
250
250
350
500
500
600
600
1000
1000
1300
1300

§.
C

~

Control
input

Output

"'"
Q.
:>
'"
Co

5.0 5.2 6.8 7.4

•
••
••
••
•• •
•
••
•• ••
• ••
••
•
••
••

40
14
14
45
45
45
45
14
14
45
45
14
14
50
50
50
45
45
90
90
85
85
85
85

·11"
-I

II-

-I

0

W

-I

II-

-I

0

W

• •
•• ••• •• •••
• •
•• ••
••• ••• •• •••
•• •
•• •• •• ••
•• •• ••
•• ••• •••
•• •• •• ••
•• ••
•• ••

Table 2 Two-Modulus SP8000 series high speed dividers

104

Package

:>

'"

~

300

•
•
•
•
•
•
•
•
•
•
•

Supply
voltage (V)

.!!

.

!!

u;

0

0::

"

•
••
••
••
•••
•
••
•••
•••
•
••
••

N

,..

:;;
c
II

II

""-;:
is

2

4

Product

SP8604A
SP86048
SP8602A
SP86028
SP8607A
SP86078
SP8605M
SP86058
SP8608M
SP86088
SP8606M
SP86068
SP8609M
SP86098
SP8790A
SP87908
SP8601A
SP86018
SP8600A
SP86008
SP8610M
SP86108
SP8617M
SP86178
SP8611M
SP86118
SP8619M
SP86198

•
•
•

•
•
•

•
•
•
•

8

1

•
•

•

0
+70

•
•
•
•
•
•
•
•
•
•
•
•
•
•

•
•
•
•

1.1
SP86208
I s lSP8620A
SP8794A
SP87948
SP8670A
SP86708
SP87358
SP8677M
SP86778

-30
+70

Supply
voltage (V)

u

.a

-55 -40
+125 +85

C

::r::
::E

Temperatura
Range ("C)

1•

•
••
•

'a-"
•"
::E

60
60
150
150
250
250
1000
1000
1300
1300
1500
1500
1500
1500

400

1:
~

Output

Package

,..'"

u

~

300
300
500
500
600
600
1000
1000
1000
1000
1300
1300
1300
1300

§.

... ....... ...

·eI!!u

•••
••
••
•••
••
••

••
•••
••
•••
••
••
•••
•••
••
•••
••
•

"li

5.0 5.2 6.8 7.4

••
••
••
••

••
••
••
•• ••
•••
••
••
•• •
••

'"

III

....

12
12
12
12
14
14
70
70
70
70
70
70
70
70
8
8
18
18
16
16
70
70
80

801
70
70
80
80

()

W

••
••• •••
• ••
••
••
••
•

II
()

I:III~~II:I 1:1
•• ••
•• ••
••
•• ••
• ••
••
•
•
• •

1400 1
120
120
600
600
600
1200
1200

u

~

;;:•

1

10
10
45
45
70 0
70
70

Table 3 Fixed-Modulus SP8000 high speed dividers

105

N

..:

:I:

::E
-;;
c

Temperature
Range (Oc)

..,..

.."

>.c

">
i5

:::I

a-

Product

SP8660B

-55
+t25

-40
+85

•

SP8660

16

SP8659A
SP8659B
SP8650A
SP8650B
SP8657A

20

64

SP8657B
SP8658

SP8755A
SP8755B
SP8750B
SP8752M

laol sP 8627

0
+70

• ••
•
••
•••
•
•
• •

SP8632B
SP8637B
SP8630A
SP8630B
SP8635B
SP8634B
SP8665B
SP8667B

-30
+70

•
•
•
•

•

•

••

.

200
200
200
400
400
600
600
600
700
1000
1200

200
200
600
600
200
200
200

1200
1200
1000
1200

5.0 5.2 6.8 7.4

•• ••
• ••
••
••
••
•
•• ••
••
•• ••
•
•• •
•

Package

Output

~:::I

a.
:::I

til

10
10
10
70

.....

....
....

75 0
70
70
75 0

75 0
80
80
10
10
45
45
10
10
20

45
45
68
68

••
••

150

33

·S"

.2

.. ..

.....

()

w

••
••
••
••
••
•
••
••
••
•

• 1 1.1.1 1 1.1
Table 3 (continued)

106

'E

Q.

;c
::E

S

">-

i!!

SP8660A

10

Supply
voltage (V)

••

l!

0;

()

0:

•• •
••
••
••

••
••
••

•

••
••
•

CIRCUIT DESCRIPTIONS
Table 3isummarises the SPBDDD range of fixed modulus dividers (i.e. those
which divide by a single ratio) and Table 2 summarises the two-modulus
programmable dividers (i.e. those dividing by N or N
1 depending on the
state of a control input). It will be seen that there are a wide number of division
ratios and input/output interfaces but all the devices in the SPBDDD range use
emitter coupled logic (ECl) chip circuitry.
The signal inputs of SPBDDD devices can be differential or single-ended and
DC or AC coupled depending on the particular device. Signal is supplied to
AC coupled devices via an isolating capacitor (usually about 1DDDpF) but
DC coupled devices have no internal bias circuitry and may be driven either
from ECl II or ECl III or be driven with AC via a capacitor and biased by a
separate external resistor network.
The datasheet for each device states which of the two ECl families is
appropriate and also describes the bias network. Devices with balanced
inputs may be driven with a differential signal, or a single signal may be applied to one input and the other decoupled to ground by a 1DDDpF capacitor.
If no signal is applied to a balanced input the device will tend to oscillate
at some ill-defined but high frequency. This may be prevented by applying a
bias to one of the inputs by means of a resistor connected from the input to
one or other of the supplies. This has the effect of desensitising the input but
preventing oscillation - the exact value of the resistor depends on the device
used but is generally around 1D kilohms. SPBDDD series devices will operate
with sinewave inputs at high frequencies but low frequency sine inputs may
cause malfunction.
Dividers specified to have maximum operating frequencies of 700 MHz or more
should not be used with sine inputs under 80MHz. At frequencies lower
than this they should be driven with square wave inputs having rise and fall
rates in excess of 200V /microsecond. lower frequency dividers may be used
with sine inputs down to 4DMHz and then with square waves with 1DD microsecond rise and fall times. Some SPBDDD circuits are less demanding details are given in their respective data sheets.
The input signal required by SPBDaa series circuits for satisfactory operation
is between 4DD and BDDmV peak-to-peak except in the case of one or two of the
very high speed dividers which require a minimum of 600mV. Many dividers
will operate with inputs well outside this range but it is unwise to allow them
to do so as the circuit configurations used in the counters can lead to miscounting at certain frequencies if too high or too Iowan input level is used.
The control inputs of the two-modulus dividers are ECl-compatible.
The majority of SPBDDD outputs are emitter followers, usually ECl-compatible, but some of the series have free collector or TTL compatible outputs.
Many of the devices have both Q and Q and some of the decades have BCD
outputs.
No particular problems arise in the output circuitry although the emitter
follower outputs should not be used to drive capacitivie loads.
The SPBDDD series circuits require 5.2V supplies except a few of the faster
circuits, which require higher voltages such as 6.BV or 7.4V. The data sheets
suggest the use of positive ground supplies; this has the advantage of
minimising the risk of damage due to output short circuits but can be inconvenient if the dividers are to be used in conjunction with other integrated

+

107

circuits using the more conventional negative ground. But whether positive or
negative ground is used it is most important that the power supplies be
adequately decoupled. Quite small capacitors may be used - 100pF is more
than ample and in some applications as little as 15pF has been shown to
be sufficient.
The capacitors used must, however, be RF types having minimal lead and
package inductance. The capacitors should be sited as close to the integrated circuits as possible and leads kept short. It is not use ensuring that a
capacitor lead is short if the printed track to it is long and thin - board tracks
must also be kept short and as wide as possible. A ground plane on one side
of the circuit board with all ground connections made to it minimises lead
inductance problems and is the best way to ensure satisfactory operation
of any high speed or high frequency circuitry.
Similar care to that spent on decoupling should be lavished on the bias
points in the circuit and the unused inputs. Capacitors need not be particularly
large but must have good high frequency performances and very short leads
and tracks.

MODULUS EXTENDERS FOR TWO-MODULUS DIVIDERS
THE SP8790 AND SP8794
The SP8790 and the SP8794 are designed for use with two-modulus dividers
to extend their division ratios and hence make them more suitable for use
with CMOS and low power TTL: The SP8790 converts a -;-N/N+ 1 counter to a
-;-4N/4N+ 1 counter and the SP8794 converts it into a -;-8N/8N+ 1 counter.
Each device consists of a counter with a balanced AC-coupled input, a
CMOS or TIL compatible output, and a control output designed to drive the
control inputs of the SP8000 series of two-modulus dividers. There is also a
control input which is CMOS or TTL compatible (but needs a 5 kilohm pullup
resistor when used with TTL) ..
In use, the control input from the programmable divider goes to the control
input of the SP8790 (or the SP8794) and is gated to the two-modulus divider
once every four (or eight) counts. Fig. 32 shows an SP8790 used with an
SP8690 to give a -;-40/41 counter; similar systems may be used with any of
the SP8000 two-modulus dividers.

CMQS/TTL
COMPATIBLE O/P

Fig. 32 SP8790 with SP8690 to give a -';-40/41

108

The SP8790 and SP8794 will normally be driven by SP8000 high speed
dividers which have fast output edges. If other sources are used, however,
the notes on input waveform slew rate in the preceding section should be
observed. Again, the input should be biased if there is likelihood of instability
in the absence of a signal, and the unused input should be decoupled to
ground if only one input is required. The input level should be between
300mV and 1V peak-to-peak.
The internal delays in the SP8790 and the SP8794 do not allow their operation at input frequencies (to the SP8790 or SP8794) of over 40MHz as a controller. However, if the SP8790 or SP8794 are used as simple dividers they will
work at over 60MHz and 120MHz respectively.
Both devices require a single 5V supply which must, as usual, be well
decoupled. Neither device has any other points which need to be decoupled
with the possible exception of unused inputs.

Input characterisation for the SP8000 series
Because of the wide frequency range of the SP~O series emitter-coupled
logic dividers, the input drive and impedance should be optimized.
The input impedance from 50MHz to 600MHz is mostly capacitive. Beyond
600MHz it becomes inductive.
To optimize the circuit to handle large overloads, small signals, and changes
of input impedance versus operating frequency some suggestions are offered
in Figs.33, 34 and 35.
Where the frequency range to be used covers an impedance change of
greater than three to one, a circuit shown in Fig. 33 could be added to the
input. By using the appropriate input impedance curve and calculating the
value of R & L, the total input impedance would be more constant over the
required frequency range.

---I

-1~T~i

T

l·Sn

~10~

Fig. 34

Fig. 33

--I

Fig. 35

C-AR-RIE-R-

DIODES (2)

In the case of large overloads the circuit shown in Fig. 34 could be used.
When using this circuit there is typically a 3dB loss in sensitivity but the
dynamic range would be increased from two to one to over four to one. The
value of R depends on the maximum overdrive voltage and the hot carrier
diodes used.
For low level inputs an SL 1521 wideband amplifier could be used as a
preamplifier for a divider as shown in Fig. 35.
By using the SL 1521 and the SP8690 low power 200M Hz divide by 10/11
divider, as shown in Fig.35, the minimum sensitivity is reduced from 143mV
RMS to 36mV RMS. Both units are self biased and require only coupling
capacitors for interconnections. Also both parts operate from the same +5V
supply at 145mW total power.
When using the SP8600 series it is recommended that good low inductance
RF capacitors be used on all bias and power supply decoupling paints.
The printed circuit board should be laid out with all input leads as short as
possible, ample ground plane around the device and using other normal RF
techniques.

110

SP8602,4,7
INPUT IMPEDANCE
The input impedance is shown in Fig.36 for the frequency range of 50MHz
to 700MHz.

INPUT CAPACITANCE
The capacitance at 50MHz is 3.1pF.

TEST CIRCUIT
The test circuit is shown in Fig.37. All tests were made at 25°C.
-S·2V
500

400

'\.

~
"- r---....

200

"""""""-

100

100

200

300

-

400

sao

600

700

FREQUENCY (MHz)

Fig. 37

Fig. 36

SP8630,2
INPUT IMPEDANCE
The input impedance is shown in Fig.38 for the frequency range of 50MHz to
600MHz.

INPUT CAPACITANCE
The capacitance at 50MHz is 3.9F.

TEST CIRCUIT
The test circuit is shown in Fig. 39. All tests were made at 25°C.
-S·2V
500

40 0

io

300

'DO

'I.

\
1\

100

100

'"

200

300

400

500

600

FREQUENCY (MH:z:)

Fig. 38

Fig. 39

111

SP 8634, 5,7
INPUT IMPEDANCE
The input impedance is shown in Fig. 40 for the frequency range of 50MHz to
700MHz.

INPUT CAPACITANCE
The capacitance at 50MHz is 4.1pF.

TEST CIRCUIT
The test circuit is shown in Fig. 41 . All tests were made at 25°C.
-S'2V
1000

........
800

\

E600

S

\

400

200

100

200

"- .......
300,

400

500

FREQUENCY

600

700

(MHz)

Fig. 41

Fig. 40

SP8643,7
INPUT IMPEDANCE
The input impedance is shown in Fig.42 for the frequency range of 50MHz to
350MHz.

INPUT CAPACITANCE
The capacitance at 50MHz is 2.4pF.

TEST CIRCUIT
The test circuit is shown in Fig.43. All tests were made at 25°C.

5'
4k

E

3k

S
2.

'" '"

1k

50

100

'"

150

~

200

r- -

250

FREQUENCY

Fig. 42

112

300

(MHzl

350

400

Fig. 43

SP8650
INPUT IMPEDANCE
The input impedance is shown in Fig.44 for the frequency range of SOMHz to
600MHz.

INPUT CAPACITANCE
The capacitance at 50MHz is 6.0pF.

TEST CIRCUIT
The test circuit is shown in Fig.4S. All tests were made at 2SoC.
-S'2V

500

400

j
o

300

"\

r..

\

200

~

100

100

200

300

400

500

600

FREQUENCY (MHzl

Fig. 45

Fig. 44

SP8655,7,9
INPUT IMPEDANCE
The input impedance is shown in Fig.46 for the frequency range of SOMHz to
100MHz.

INPUT CAPACITANCE
The capacitance at SOMHz is 3.6pF.

TEST CIRCUIT
The test circuit is shown in Fig. 47. All tests were made at 2SoC.
600

500

'-

400

j

'-..

............

300

-

o
200
100

50

100

150

FREQUENCY (MHzl

Fig. 47

Fig. 46

113

SP8685
INPUT IMPEDANCE
The input impedance is shown in Fig.48 for the frequency range of SOMHz to
SOOMHz.

INPUT CAPACITANCE
The capacitance at SOMHz is 8.7pF.

TEST CIRCUIT
The test circuit is shown in Fig. 49. All tests were made at 2S0C.
+s-ov

400

i

300

o

\

'\

200

100

"'"

100

I---.

200

300

400

50{)

FREQUENCY

(MHz l

Fig. 49

Fig. 48

SP8690
INPUT IMPEDANCE
The input impedance is shown in Fig. SO for the frequency range of SOMHz to
200M Hz.

INPUT CAPACITANCE
The capacitance at SOMHz is 6.4pF.

TEST CIRCUIT
The test circuit is shown in Fig. S1. All tests were made at 2SoC.
+S'2V

2'Ok

]"5k

~

o

'-Ok

'-.,

16

1--....

1--1-

05.

50

100

150

FREQUENCY I MHzl

Fig. 50

114

200

Fig. 51

Preamplifiers for

spaooo series

The availability of low-cost hybrid amplifiers with a performance extending
to 1GHz, coupled with SP8000 High Speed Dividers, allows an unparalled
increase in instrument performance.
For example, using an Amperex ATF 417 as a preamplifier for an SP8610
(with a Schottky barrier diode limiter), the divider's sensitivity can be improved
by at least 15dB. The circuit diagram isshown in Fig.52. Typical room temperature performance is shown in Fig.53, and a suitable PCB layout is given in
Fig 54.
Low end performance is limited by signal rise time requirements for the
SP8610, whilst high end sensitivity is limited by the amplifier limiter performance. This can be improved by operating the ATF 417 off a higher supply. By
increasing the supply to, say, +20V, a gain in sensitivity of, typically, 5dB
would be expected at 1GHz.
Similar results can be obtained using the ATF 417 with other dividers such
as the SP8667, 1.2GHz decade divider.
+ lSV

liP
(lOa Mhz
-1 GHz)

Fig. 52 UHF instrumentation -:- 20 prescaier

COMPONENTS

01 - 04
A1
IC1
IC2
05,06
R6, R10
C1 - C12
C13

CIRCUIT

Schottky barrier diodes, HP5082-2811
Hybrid amplifier, Amperex ATF417 or Philips OM185
Plessey Semiconductors SP86l0B
Plessey Semiconductors SP86Z0B
1 Watt, 5.1V Zener diode
100 ohms, 5 Watt, e.g. Plessey GWT-5
1nF ceramic, e.g. ITW EMCAPS
0.33 microfarad

DETAILS

The signal input (100MHz-1GHz) is AC-coupled to a Schottky barrier diode
bridge which limits at 100mV pIp. The signal is then amplified by the hybrid

115

A1. This combination gives about 15dB of gain with a supply of 15V. The
amplifier is AC coupled, via C3, to an SP8616 -:--4 circuit (IC1). R7 provides an
input offset to prevent 'no signal' oscillation. The drive capability of IC1, is
increased by R8 and its output capacitively coupled to IC2 via C4 R9 provides
the input offset for IC2. The output of IC2 is suitable for driving ECl II.
+10

J
-10

-20

,\~

-30

"""

D

I
..........."

V

/

/

V

-40

o

200

400

600

INPUT FREOUENCY

800

1000

(MHz)

Fig. 53 Typical performance of UHF prescaler

Fig. 548 Component side of board

116

1200

Fig. 54b Solder side of board

O+VE

O-VE
EARTH

~

f- ~

~

__
R6

t- ___

L....::..:.:... -1 -

~

-1

-Q:CJ-R

1

IIPD

(if ~~
liJ'
<:)

3

5

A

R.

~U W

~

~\.

@]

R

R

~

Rl0_

1~

R

~.
§]

--F·Ig. 54c Component location

117

118

SYNTHESISER
CIRCUITS

119

Synthesiser Circuits
INTRODUCTION TO SYNTHESISER SYSTEMS
Fig. 55 shows a typical frequency synthesiser. It consists of a voltage
controlled oscillator, a variable divider and a phase comparator. The output
frequency of the VCO is a function of an applied control voltage. In frequency
synthesisers the function is always monotonic and is generally as near linear
as possible.
QUTPl)T

~----_--...

fa

I~ N. fRI

PROGRAMMABLE

DIVIDER
REFERENCE

fa

PHASE
COMPARATOR

Fig. 55 Basic frequency synthesiser

The output of the phase comparator is a voltage which is proportional to
the phase difference between the signals at its two inputs. This output controls
the frequency of the VCO so that the phase comparator input from the VCO
via the variable divider (--:-N) remains in phase with the reference input, fR,
so that the frequencies are equal. The VCO frequency is thus maintained at
NfR, Such a synthesiser will produce a number of frequencies separated by
fR and is the most basic form of phase locked synthesiser. Its stability is
directly governed by the stability of the reference input fR, although it is also
related to noise in the phase detector, noise in any DC amplifier between
the phase detector and the VCO and the characteristics of the low-pass filter
usually placed between the phase comparator and the VCO.
The design of frequency synthesisers using the above principle involves
the design of various sub-systems; including the VCO, the phase comparator
any low-pass filters in the feedback path, and the programmable dividers.
The following deals mainly with the design of dividers.

PROGRAMMABLE DIVISION
A typical programmable divider is shown in Fig. 56. It consists of three
stages with division ratios K 1, K2 and K3 which may be programmed by
inputs Pl, P2 and P3 respectively. Each stage divides by Kn except during the
first cycle after the program input Pn is loaded when it divides by P (which may
have any integral value from n to K). Hence the counter illustrated divides by
P3(K1K2)
P2Kl
Pl and when an output pulse occurs the program inputs
are reloaded. The counter will divide by any integer between 1 and

+

(K1K2K3 -

+

1).

The commonest programmable dividers are either decades or divide-bysixteen counters. These are readily available in various logic families, including
CMOS and TTL. It is possible to buy quad decades in CMOS in a single package.

120

Fig. 56 Typical programmable divider

Using such a package one can program a value of N from about 3 to 9999. The
theoretical minimum count of 1 is not possible because of the effects of circuit
propagation delays. The use of such counters permits the design of frequency
synthesisers which are programmed with decimal thumbwheel switches and
use a minimum of components. If a synthesiser is required with less obvious
frequencies and steps a custom programmable counter may be made using
some custom logic family such as PMOS, NMOS, CMOS or 12L.
The maximum input frequency of such a programmable counter is limited
by the speed of the logic used, and more particularly by the time taken to load
the programmed count. Few programmable counters of the type discussed
will operate with test frequencies much above 5MHz. The faster types,
operating perhaps 25 or 30M Hz, use Shottky TTL which consumes considerable power and has a tendency to inject HF and VHF noise into supply lines.
The output frequency of the simple synthesiser in Fig. 55 is of course limited
to the maximum frequency of the programmable divider.
There are many ways of overcoming this limitation on synthesiser frequency.
The VCO output may be mixed with the output of a crystal oscillator and the
resulting difference frequency fed to the programmable divider; the VCO
output may be multiplied from a low value in the operating range of the
programmable divider to the required high output frequency. Alternatively,
a fixed ratio divider capable of operating at a high frequency may be interposed between the VCO and the programmable divider. These methods are
shown in Figs 57a., 57b and 57c respectively.
All the above methods have their problems although all have been used
and will doubtless continue to be used in some applications. Method (a) is
the most useful technique since it allows narrower channel spacing or higher
reference frequencies (hence faster lock times and less loop-generated
jitter) than the other two but it has the drawback that since the crystal oscillator
and the mixer are within the loop, any crystal oscillator noise or mixer noise
appears in the synthesiser output. Nevertheless, this technique has much to
recommend it.
The other two techniques are less useful. Frequency multiplication introduces noise and both techniques must either use a very low reference
frequency or rather wide channel spacing. What is needed is a programmable
divider which operates at the VCO frequency - one can then discard the
techniques described above and synthesise directly at whatever frequency
is required.

121

VCO

f------_._--

OUTPUT

fO

+ N.fR)

(:: fX

PROGRAMMABLE
DIVIDER

PHASE

REFERENCE
fR

COMPARATOR

Fig. 57a Mixer synthesiser
FREQ. MULl
OUTPUT

to
(, K.NfRi

REFERENCE

fR

PROGRAMMABLE
DIVIDER

Fig. 57b Synthesiser with ouput multiplication
OUTPUT

to
(, tRMNi
PRES CALER

REFERENCE
fR

PROGRAMMABl E
DIVIDER

Fig. 57c Synthesiser with prescaler

TWO-MODULUS DIVIDERS
Considerations of speed and power make it impractical to design programmable counters of the type described above, even using ECl, at frequencies
much into the VHF band (30 to 300MHz) or above. A different technique
exists, however, using two-modulus dividers.
Fig. 581 shows a divider using a two-modulus prescaler. The system is
similar to the one shown in Fig. 57c but in this case the prescaler divides
either by N or N + I depending on the logic state of the control input. The
output of the prescaler feeds two normal programmable counters.
Counters 1 controls the two-modulus prescaler and has division ratio A.
Counter 2, which drives the output, has a division ratio M.
In operation the -7-N/N + I prescaler (Fig. 58) divides by N+I until the count
in programmable counter 1 reaches A and then divides by N until the count
in programmable counter 2 reaches M when both counters are reloaded, a
pulse passes to output and the cycle restarts. The division ratio of the whole

122

system is A(N+1) + N(M-A), which equals NM+A. There is only one constraint on the system - since the two modulus prescaler does not change
modulus until counter 1 reaches A the count in counter 2 (M) must never be
less than A. This limits the minimum count the system may reach to A(N+1)
where A is the maximum possible value of count in counter 1.

OUTPUT DIVISION

RATIO
N M

~

+A

N8 (Mi:AI

Fig. 58 Divider system with 2 modulus prescaler

The use of this system entirely overcomes the problems of high speed
programmable division mentioned above. Plessey Semiconductors make a
number of -;-10/11 counters working at frequencies of up to 500MHz and
also-;-5/6, -;-6/7 and -;-8/9 counters working up to 500MHz. There is also a
pair of circuits intended to allow -;-10/11 counters to be used in -;-40/41 and
-;-80/81 counters in 25kHz and 12.5kHz channel VHF synthesisers.
It is not necessary for two-modulus prescalers to divide by N/N+ 1. The same
principles apply to -;-N/N+Q counters where Q is any integer but -;-N/N+ 1
tends to be most useful.
If the limitation that M must not be less than A is unacceptable the system
may be extended to use three or four modulus division. For example if a
-;-10/11 prescaler is used in a VHF synthesiser to be programmed in decades
the maximum value of A will be 9 and so the minimum frequency will be
99MHz (=A(N + 1)). Suppose instead that a -;-100/101/110 counter (which may
be made as shown in Fig. 59) is used in the system in Fig. 60. At the start of a
cycle the counter divides by 110 until the programmable counter reaches A.
This releases the inhibition on programmable counter 2 and the prescaler
divides by 101 until counter 2 reaches Az, at which point the prescaler divides
by 100 until counter 3 reaches N and the cycle restarts. The division ratio is
therefore 110A1 + 101Az+ 100(N-A1-A2) which, by a bit of algebra, is equal to
A2+10A1 +100N.
This system allows a minimum count in the programmable counter 3 of
A1 +Az. Since the system is decimal the maximum value of A1 and A2 is 9.
The minimum value of N is therefore 18 and if the earlier system is replaced
with this system it will work down to 18MHz. A similar, but more complex
system involving -;-100/101/111 prescaler allows operation down to 10MHz.

123

LOGIC
INPUT

COUNT

101

110

L
H
L
H

L
L
H
H

100
101
110
110

Fig. 59 Basic 10011011110 prescaler

1001101/110
COUNTER

101
INPUT

110
INPUT

OUTPUT

OIVISICN

RATIO:: A2+ lOA

+ lOON

Fig. 60 Divider system with 10011011110 prescaler

124

SYNTHESISER PRODUCT RANGE
CRYSTAL OSCILLATORS
SP705

1 to 10MHzcrystal, outputs at +2, +4

CRYSTAL OSCILLATORS WITH DIVIDERS
SP8760
SP8921

also includes phase comparator
also includes part of control circuit

CITIZENS BAND 27MHz PRODUCTS
SP8921
SP8922
SP8923
UNIVERSAL SYNTHESISER
SP8901
SP8906
NJ8811

4 modulus divider 1GHz
4 modulus divider 500MHz
Control circuit for use with SP8901 or SP8906

LOWER POWER SYNTHESISER
NJ8812

Control circuit for use with +40/41 or +80/81

SP705B
CRYSTAL OSCILLATOR
The SP705B is a square wave oscillator circuit designed to operate in conjunction with an AT cut quartz crystal of effective series resistance less than 300
ohms. Four TIL outputs are provided, related in frequency to the crystal frequency
f as follows: f/2, f/4. f/2 and f/4. The SP705B is therefore ideally suited to either
single or multi-phase TIL clock applications.
The crystal maintaining circuit consists of an emitter-coupled oscillator, with the
emitter resistors replaced by constant-current generators. The crystal is connected, usually in series with 20pF capacitor, between pins 5 and 6. The 20pF
capacitor can be replaced with a mechanical trimmer to allow small changes in
frequency to be made, as shown in Fig. 62.
The circuit is designed to provide low crystal drive levels - typically, less than
0.15mWat 5MHz. This is well within crystal manufactures' limit of 0.5mW.
The compensation point, pin, 4 is made available so that the compensation capacitance can be increased if necessary. However the 14pF capacitor included on
the chip is usually sufficient to prevent spurious oscillation at high frequencies.

125

DIVIDER

f 11

..J1..JlJL

FIRST

STAGE

f/1~

f H,

DIVIDER

f/'

s-LJL

SECOND
STAGE

, 1.OV

CRYSTAL

Fig, 61

lLp

3·6k

SP705B block diagram

500

3·6k

1k

Fig, 62

TO
DIVIDER
STAGES

Circuit diagram of SP705B oscillator

CRYSTAL FREQUENCY (MHz)

10

z

o

~ -30

~

-40

Cl

-50

TYPICAL CIRCUIT COEFFICIENTS

-60

TEMPERATURE COEFFICIENT OF CURCUIT 0'1 P pm pe, 'c (ii) 10MHz
VOLTAGE COEFFICIENT OF CURCUIT 1'4 P pm pe, VOLT (ii) 1'4 MHz

Fig, 63

126

Deviation from nominal crystal frequency

SP8760
General purpose synthesiser
The SP8760 is a general-purpose circuit intended for use in conjunction
with CMOS or TTL programmable counters, and with high speed prescalers,
in frequency synthesisers. It consists of a crystal oscillator with two-stage
divider, a -:.-15/16 two-modulus counter, and a high performance type II
phase/frequency comparator. All three sections of the device have CMOS/TTL
interfaces and the phase/frequency comparator offers better zero error and
phase jitter characteristics than other such integrated circuits.

CIRCUIT DESCRIPTION (Fig.64)
The crystal oscillator uses an emitter-coupled circuit with a series resonant
crystal connected between pins 4 and 5. It is internally rolled off to prevent
overtone operation and will not work at frequencies much above 10MHz.
This oscillator has a series resonant crystal and has a stability of about
0.2ppm/degree C, excluding the crystal itself.
If the divider is required but not the crystal oscillator, an external signal may
be applied to pin 4 via a small capacitor in series with 220 ohms. Pin 5 may,
in that case, either be decoupled or left open depending on the frequency and
amplitude of the signal on pin 4.
The output of the oscillator is not available externally but only via a -:.-4
circuit. This circuit, like the rest of the logic interfaces on the SP8760, has a
CMOS/TTL compatible output, which is connected to pin 11.
The two-modulus divider (-:'-15/16) has a CMOS/TTL ciock input on pin 6
and its output appears on pin 9. When the control input, pin 8, is high the divider
divides by 16 and when it is low it divides by 15. The standard TTL fan-in of the
clock input is 1 and the output fan-out is 3.

OUTPUT'C'
~

INPUT 'A'

PHASE/FREQUENCY
COMPARATOR

XT AL

~

INPUT'S'

LJ-::-l

o

~O_S_C~I ~ ~

CLOCK 0>----1._---1

-;- 16115

OUTPUT

•

:

~ OUTPUT
CONTROL

Fig, 64 SP8760 block diagram

127

The maximum clock frequency of the SP8760 is at least 12MHz (typically
18MHz). Hence the use of almost any family of low speed logic is permissible
in the main divider of a synthesiser using the SP8760 since its output will never
exceed 1MHz under proper operation.
The comparator has an infinite pull-in range (subject, of course, to an input
frequency response of about 10MHz) and zero phase shift at phase-lock. The
comparator pulse width at zero phase shift is under 30ns, giving minimum
noise and jitter.
In operation the comparator triggers on the 1 to 0 transition of each input
and gives outputs on pins 1 and 2 proportional to the phase difference between
the two transitions. When the edge on pin 14 occurs before the edge on pin
13 the output on pin 1 will be low during the interval between the two transitions and the output on pin 2 will remain low whereas if the edge on pin 14
occurs after the edge on pin 13 the output on pin 2 will be high between
the two transitions and pin 1 will remain high. The decision as to which is the
'first' transition is made by counting pulses at each input - if two pulses occur
at one input without any ocurring at the other the second of the two is considered to be the 'first' and the relevant output changes state until a 1 to 0
transition occurs on the other input. Once an input has counted two in this
way it remains the 'first' input until two transitions occur on the other input
without one ocurring on it, when the other input becomes the 'first' input.
The SP8760 phase comparator timing diagram is shown in Fig.65.

PIN 14

INPUTS
PIN 13

PIN I
OUTPUTS
PIN 2

_______________

rLJrlLJl~

_______

Fig. 65 Phase comparator timing diagram

The output on pin 1 consists of the collector of an NPN transistor with a
10 kilohm resistor to Vee. Three ways of driving the varactor line of a voltage
controlled oscillator from these outputs are shown in Fig. 66. The simplest
way, shown in Fig. 66(a), is only suitable for use when the varactor voltage
change is very small - say, less than 1V from 2 to 3V. The low voltage charge
pump in Fig. 66(b) can be used with varactor voltages between 1V and 4V
and the high voltage charge pump in Fig. 66(c) is used where large varactor
voltage swings are necessary. The transistors and diodes used in these circuits should be silicon types with a fast switching speed to avoid degrading
the performance of the phase comparator. The transistors used in the circuit
in Fig. 66;(c) need also a Vceo of at least 35V.
The leakage on the varactor line must be as low as possible since any
leakage leads to jitter as the charge pump replaces the lost charge. A high
impedance buffer may be placed between the output of the charge pump and
the varactor line and indeed is essential if varactor line losses are high.

128

Since noise in this buffer will itself cause oscillator jitter, it is better to use a
non-leaky varactor line and no buffer if at all possible.
The SP8760 uses a single 5V supply, which must be well decoupled at HF
and LF and draw about 45mA.

PIN 2

--H>~-.----.--- TO VARACTOR

PIN 1

Fig. 66a Simple charge pump

OUTPUT

'c'

o-c=:J-+-i1--£

sv
OUTPUT

'C'D--r-f-l

--___"--i---+--oV

Fig. 66b Low voltage
charge pump and
filter. Divider clock input

----<~---4-~-OV

Fig. 66c High voltage
charge pump and
filter

129

SP8921/2
CITIZENS' BAND SYNTHESISER
The SP8921/22 combination is intended to synthesise the frequencies
required in a 40-Channel Citizens' Band transceiver. The 40 channels are
spaced at 10kHz intervals (with some gaps) between 26.965 and 27.405MHz.
Local oscillator frequencies for the reception of these channels with intermediate frequencies of 455kHz, 10.240MHz, 10.695MHz and 10.700MHz are
also synthesised. Table 4 shows the relationship between the program input
and the channel selected. By using a program other than one of the 40 given
other frequencies may be selected - in fact there are 64 channels at 10kHz
separation available from 26.895 to 27.525MHz and programming starts at all
zeros on inputs A through F for 26.895 and each increase of one bit to the
binary number on these inputs increases the channel frequency by 10kHz until
all '1's give 27.525MHz. The A input is the least significant bit, F the most
significant. The programming input on pin 16 of the SP8922 is normally kept
high but making it low increases the programmed frequency by 5kHz. Table 5
shows the programming required to obtain various offsets.
The circuit diagram of a CB synthesiser is shown in Fig. 67. It is intended
for use in double conversion receivers with IFs of 10.695 and 455kHz and
generates either the frequency programmed or the frequency programmed
less 10.69SMHz.

If other offsets are programmed the connections to pin 15 of the SP8921
and pin 2 of the SP8922 must be altered according to Table:5.
The synthesiser consists of the SP8921 and the SP8922 plus an SP1648
voltage controlled oscillator.
The programming inputs to the SP8922 are as shown in Table 4. Logic '1' is
+3V or more, logic '0' is either ground or an open circuit. The circuit diagram
of a programming input port is shown in Fig. 68. If a switch, constructed so as
to select the correct combination for each channel, can be obtained this is the
obvious way to program the synthesiser; otherwise a ROM may be suitably
programmed and placed between the switch and the SP8922.
The crystal oscillator in the SP8921 is trimmed by a small variable capacitor,
C3, which must be set up during alignment of the synthesiser so that the output
frequency on pin 4 is 10.240000MHz. The only other adjustment is to set the
core of L 1 so that the varicap control voltage is 2.85V when the synthesiser is
set to channel 30 transmit. Since the difference between transmit and receive
frequencies is over 10MHz it is not possible to tune both with the same tuned
circuit and an extra capacitor is switched by means of a diode during reception.
The phase/frequency comparator of the SP8921 can have an output swing
from 0.5V to 3.8V but it is better to work in the range 1.5V to 3.0V as the phaseerror output voltage is more linear in this region. The ZC822 tuning diode
specified for this synthesiser may be replaced by any other tuning diode
provided it will tune the VCO over the required range, or a little more, as the
control voltage goes from 1.5 to 3.0V. With slight coil changes the MV2105
has been used successfully in this synthesiser.

130

Channel
No.

Input Code
FEDCBA

Output frequency
with RfT = 0 (MHz)

1

000 1 1 1
001 000
0 1 001
1 1
0 1
0 1 100
0 1 1 0 1
0 1 1 1 0
010 000
1 0 001
1 0 010
1 0
1 1
1 0 1 0 1
1 0 1 1 0
1 0 1 1 1
1 1 000
1 1 010
1 1
1 1
1 1 100
1 1 1 0 1
011 1 1 1
100 o 0 0
0 1
100
100 100
100010
100011
100101
100110
100111
101000
10 1 0 0 1
101010
101011
101100
101101
101110
101 1 1 1
110000
110001
110010
110011

26.965
26.975
26.985
27.005
27.015
27.025
27.035
27055
27.065
27.075
27085
27.105
27.115
27.125
27.135
27.155
27.165
27.175
27.185
27.205
27.215
27.225
27.255
27.235
27.245
27.265
27.275
27.285
27.295
27.305
27.315
27.325
27.335
27.345
27.355
27.365
27.375
27.385
27.395
27.405

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o

o

o

o

o

Table4 SP8922/1 OjP frequencies with 10.240 crystal (0 =
contact open. 1 = contact closed to Vee)

131

+5V

1611------

10·24 MHz

OUTPUT

0------1

IC2
SP8922

R1
R2

i-----+svl
I
I

I
I

R4

LOCK
'INDICATOR
R3

R6

I

I
I

L ______

01

132

C8

+5V

,
,
,
,

:::1

,

-.J

C7

INPUTS

All resistors are in ohms and iW ± 10% unless otherwise stated. Capacitor values are
in microfarads unless otherwise stated.
ICl
IC2
IC3
Tl
Dl
D2
D3
Xl
L1
L2
L3
Rl
R2
R3
R4
R5
R6
R7
R8
R9
Cl
C2
C3
C4
C5
C6
C7
C8
C9
Cl0
Cll
C12
C13
C14
C15
SWl

SP8921
SP8922/SP8923
SP1648
2N 3906
ZC822, Ferranti varactor diode
lN4148 Silicon diode
LED lock indicator
10.240MHz crystal, series mode
11 turns 30 gauge cotton covered wire on Neosid A7 assembly
100 microhenries RF choke
100 microhenries RF choke
1.0k ± 5%
1.0k ± 5%
8.2k ± 5%
33k
10k
150 (adjust for LED brightness)
lk
lk
470 (adjust for required output level)
0.1
100, 10V solid tantalum
2 - 22pF variable
100 10V solid tantalum
110V solid tantalum
0.1
1000pF
22pF + 10%
0.01
100pF ± 10%
0.01
0.1
10 solid tantalum
0.1
1000pF
2 pole, 1 way switch,
(receive/transmit)

133

Offset

SP8921

SP8922

0

0

0

-455kHz

0

1

-10.240MHz

1

0

-10.695MHz

1

1

~
Ok

10k

VEE

Fig. 68 Program input circuit
Table 5

The low pass filter of the PLL consists of C5, C6 and R3. If faster lock (at the
expense of larger noise and reference sidebands) is required the filter may be
redesigned. If the synthesiser is used in a scanning receiver, a switched filter
should be used to give fast lock during scanning but a slower lock and cleaner
signal during normal operation. The lock output on pin 8 of the SP8921 is
used to light an indicator when the loop is not locked and should also be used,
in a transmitter or transceiver, to prevent transmission when the loop is
unlocked.
Fig. 69 shows the circuit board layout and component placing of this synthesiser.
It requires a single +5V supply and draws about 60mA. The performance is improved if double-sided board is used with a ground plane on one side. A small
further improvement would come from the use of a grounded screening can over
the whole system.

Fig.69a Printed circuit layout for CB synthesiser

134

Fig. 6gb PCB component layout for CB synthesiser

The synthesiser has reference frequency sidebands 50dS down at 1.25kHz
from the carrier. All output over 5kHz from the carrier is over 70dS down. Lock
time for a change from channel 0 to channel 40 (a frequency change of
440kHz) is around 35ms. Photographs of the output spectrum and the change of
control voltage with time during a step from channel 0 to channel 40 are shown
in Fig. 70. Stepping from transmit to receive or vice versa takes somewhat
longer because of the much larger change of frequency but is generally
complete within 75ms.
This synthesiser is quite basic but has adequate performance for the
majority of CS applications. If improved performance is required there
are two possibilities; an improved FET oscillator having lower floor noise
instead of the SP1648 or an improved low pass filter to reduce reference
frequency sidebands.

135

Fig. 70a Typical output spectrum of basicsynthesiser (Vert. :16dBldiv.,Horiz.: 2kHzldiv.,)
BW:300Hz, fo :27.065MHz

Fig. 70b Typical transient response of basic synthesiser. Response of varactor line to
step program change 1-40. Vert. :200mVldiv.,Horiz. :5msldiv.
N.B. Droop of response is due to the measuring instrument being AC-coupled.

136

RADAR
APPLICATIONS

137

Introduction
The performance of a radar receiver depends very much on the performance
of its IF strip. It must provide enough gain and dynamic range to allow for the
expected variations in echo signal power, and without saturation. It must have
a low noise figure, especially as this affects the overall noise performance of
crystal mixer/amplifier combinations. The bandpass characteristic is also
important: the overall receiver bandwidth is essentially determined by that of
the IF stages. In addition, the IF amplifier must have a high centre frequency
compared with the signal bandwidth if IF signal spectral components are not
to appear within the passband of the video amplifier.
Plessey Semiconductors contribution to the design of radar IF amplifiers
is a range of integrated circuits which may be regarded as building blocks
from which IF systems of different requirements and configurations can be
built. These circuits are summarised in Section 2, followed by detailed
application information given in the remaining sections of this handbook.
Table 1 summarises the range of integrated circuits for radar applications
available from Plessey Semiconductors. Full technical data for each of these
circuits is given in Section 6.

1 Plessey ICs for radar I Fs
Successive detection log. amplifier
SL521
SL523
SL1521
SL1522
SL1523

30 to 60MHz centre frequency, 12dB gain
Dual SL521 (cascade)
120 to 160 MHz centre frequency, 12dB gain
Dual SL 1521 (parallel)
Dual SL1521 (cascade)

Linear amplifiers
SL550

125MHz bandwidth ,40dB gain, 25dB gain control range, 1.8dB
noise figure

SL560

300MHz bandwidth, 10 to 40dB gain, 1.8dB noise figure

Video amplifiers and detectors
SL510
SL541

Detector (DC to 100MHz), video amp. (DC to 24MHz)
Op. amp. configuration, slew rate 175V/IlS, settling time SOns,
recovery from overload SOns.

A to 0 conversion
SP750B

High speed latched comparator, min. set-up time 2ns, propagation delay 3.5ns (typ.)
Table 1

138

Plessey ICs for radar IF systems

SUCCESSIVE: DETECTION LOGARITHMIC IF STRIPS
The well established SL521 integrated circuit has been widely used in
logarithmic IF strips for many years. New products have been introduced in
recent years to satisfy the needs of higher IF frequencies and reduced weight!
volume. The first of these, the wide bandwidth SL 1521, is described in detail
(together with the design for a log. strip) in Section 4.

SL1523

VIDEO OUTPUT

SL1521

RF INPUT

"
GROUND-

VIDEO OUTPUT

SL1522
Fig. 1

Log IF amplifiers SL15211213

More recently, products have been introduced which combine two SL521
or SL 1521 chips in a single encapsulation. The SL523 and SL1523 contain two
stages in cascade; the SL523 is pin compatible with the SL521 (see data
sheet page 41). The use of the SL 1523 or SL523 enables the user to obtain a
major size reduction in the IF strip; for example a high performance 60MHz
strip with a 90dB log. range can be built using only four SL523 packages (see
Fig. 2).

139

,-------r----~~r__---_,_-~---o EARTH

.-__

+--~_..--

__+-_+---,--'--O +6V

RF INPUT

"---t---<> RF

OUTPUT

t - - - + - - - o V I O E O OUTPUT

16: 1
ATTENUATOR

~
Ik

L--~-------+------~----I~~-_OE4RTH

Fig. 2

Wide dynamic range IF strip

The SL 1522 also contains two SL 1521s, but this time they are essentially
connected in parallel. It is intended that the SL 1522 should be used in the first
stage of a log strip; when included in this way the strip maintains its log
characteristic for input signals 12dB larger than the simple strip. This is a
simple example of the 'lift' technique described for the SL 1521 strip below.
The SL 1522 can be substituted in most cases for the first SL521 or SL 1521 in an
existing strip with only minor changes to the board being necessary.

LINEAR AMPLIFIERS
The two most important linear radar IF amplifiers are the SL550 and SL560.
The SL550 is ideal for use where variable gain is required up to 100MHz.
Strips incorporating STC (sensitivity time control) or swept gain are easily built
with this device. Section 3 describes the practical details of a simple strip of
this type.
The versatility and high performance of the SL560 makes it ideal for fixed
gain pre-amplifiers. Section 3 describes the design of a wide dynamic range,
low-noise, preamplifier suitable for interfacing between a microwave mixer
and an SL521 or SL 1521 log strip.

VIDEO AMPLIFIERS AND DETECTORS
Two circuits are available for use in the video sections of a radar. The SL510
is a general purpose detector and video amplifier and is described in more
detail in Section 5. The SL541 is a high speed video amplifier, the configuration of which follows that of an operational amplifier. Apart from the high slew
rate (175 volts per microsecond) the important features of the SL541 are its
fast settling time and its ability to deliver a clean video pulse with a minimum
of overshoot and ringing even when severely overdriven. Positive and negative
output swings are limited to ± 3 volts without saturating any transistor in the
circuit so that the circuit can recover from a 10 times overload in less than
50ns.

140

A TO 0 CONVERSION
Two conversion methods dominate the field of fast analogue-to-digital
conversion: the all-parallel and the parallel-series-parallel converter.
The all-parallel conversion technique provides the highest rate of conversion
available. For an N-bit converter, (2N_1) comparators compare the input with a
linearly divided reference voltage. The decisions of the comparators are held
by the application of a latch signal until the comparators are unlatched
to receive new data. The conversion rate is therefore determined by the
response time of the comparators. Fig. 3 shows the block diagram of such a
converter. Using the SP750B a conversion rate of 100 Megasamples per
second or more can be obtained.

CO~PARATORS

,--A--."

DECODER

VREF -VE

Fig. 3

3-BIT
BINARY
OUTPUT

LATCH
INPUT

3-bit all parallel A-O converter

The all-parallel converter becomes rather expensive in comparators if more
than 5 or 6 bit accuracy is required, where the parallel-series-parallel technique illustrated in Fig. 4 may be preferred. Sampling rates of up to 30 Megasamples per second can be achieved with 8-bit accuracy using the SP750B.

141

SUBTRACTOR

0-

ANALOGUE
INPUT
MSB

LSB

~

,....--I'------

-

'--

DC REF
VOLTAGE

4-BIT

AID
CONVERTER

-

'-4-BIT

DIA
CONVERTER

r-

4-BIT

~gL~E:E~

AID
CONVERTER

I

I III
OUTPUT
LATCHES

111111
'---v---'
8-BIT BINARY
OUTPUT

Fig. 4

4

X 4-bit parallel-series-parallel

15LSB
COMPARATORS

6BITO/P

~

OUTPUT
LATCHES

Fig. 5

142

Block diagram of 4 x 4-bit parallel series A-O converter

The SP750 has several features which make it more suitable for use in A-D
converters of these types than other fast comparators. The basis of the SP750
is a fast comparator with a latch facility, which allows the device to be used in
the sample-and-hold mode. The comparator has a relatively low gain in the
follow (i.e. unlatched) mode, which assists in achieving an extremely fast
response. However, due to the positive feedback action of the latch facility,
the gain approaches infinity during the latch cycle, thereby permitting high
resolution to be achieved.
In addition to the basic comparator, functions are included which are
purpose designed to aid in optimising the design of parallel and parallelseries-parallel converters.
They are:
1. A two-input gate for simplified comparator output logic.
2. Four emitter follower outputs from the gate to provide wired OR decoding
for up to 4 bits.
3. A precision current source set by an external resistor and a reference
Voltage.
4. A high speed switch for the current source to provide a fast and convenient reconstruction of the analogue input.
Fig. 6 shows a block diagram of the SP750 illustrating these functions.
Q.
LATCHED

COMPARATOR

MULTI- COMPARATOR
GAII~G

-5.2V
REF

.LATCH liP

LATCH
INPUT

00
0,

(fIT

W'RED:t:cn I
DECDD""

0,
OV ANALOGUE
10

(..3

o~

ANALOGUE CURRENT
OUTPUT 10

Fig. 6

SP750B block diagram

2 A wide dynamic range preamplifier
SL560 GENERAL DESCRIPTION
The SL560, containing three very high performance transistors and associated biasing components, forms a 300M Hz low noise amplifier. The configuration employed permits maximum flexibility with minimum use of external
components.

143

A common base configuration is obtained when pin 6 is decoupled (see
Fig. 7). In this form a well-defined low input impedance is obtained, which
could be utilised either for a low noise/low source operation (pin 7 input) or
for 500hms input impedance (pin 8 input).
~-_-----1>---_---O

GAIN

4 Vcc

SET 5 o----+--~

INPUT
ICOMMON EMITTER
CONFIGURATION I 6 o--..--~-I"

+----03

INPUT
{COMMON BASE
CONFIGURATION I

OUTPUT

200
OUTPUT CURRENT
SET

2k

L----+--------<>----+---D 1
Fig. 7

EARTH

SL560 circuit diagram

Operating the circuit with the input transistor in the common emitter configuration can be achieved by decoupling pin 7 and using pin 6 as the input.
A gain of 35dB with a bandwidth of 75MHz and with a noise figure of 2dB can
be achieved with this configuration.
To obtain maximum bandwidth from the circuit, the capacitance at the
collector of the input transistor must be kept to minimum. To give some
flexibility in the choice of collector loading and meet the above requirement, a
split collector load has been introduced. This minimises the influence of can
and bonding pad capacitances on the frequency response of the amplifier.
If shaping of the amplifiers roll-off is required, then external capacitance can
be connected to pin 5.
The output is taken from the emitter follower stage, pin 3; this gives a low
output impedance and maximum voltage swing. If higher current swing is
required, then pin 2 is earthed. Depending on the configuration, the amplifier
can be operated from a supply of 2V to 15V. Additional flexibility in the selection of biasing condition of the first transistor is available by paralleling
external resistors with the internal 10k bias resistors. With all the options
available, care must be taken to ensure that the temperature rating of the
circuit is not exceeded. The chip-to-ambient thermal resistance is 225°C/
Watt, chip-to-case is 65°C/Watt, and the permitted maximum junction temperature is 150°C.
To obtain best noise performance, the SL560 would normally be operated in
common emitter mode, with pin 6 as input and pin 7 decoupled; it is also
important to operate the input transistor at the correct quiescent current. For a
typical device, the optimum first stage current is given by lopt = 200/Rs,
where Rs is the source impedance in ohms and 'opt is in mAo The desired

~4

current can be achieved by a suitable choice of supply voltage or by changing
the bias voltage of pin 6 by external resistors to earth or to the positive supply.
The noise figure of the SL560 is given by the standard equations for bipolar
transistors. If operated under optimum conditions a useful formula is that the
noise figure will be approximately 10 log (1.3 + 20IRs). For more detailed
calculations, typical data on the transistor is given in Table 2.

Parameter

Value

hie

40 to 120

rbb
fr (@ 2mA)
fr (@ 10mA)

1.0GHz
2.0GHz

Table 2

170

SL560 Typical transistor data

As the SL560 employs transistors with high fr, care must be taken to avoid
high frequency instability. Capacitors of small physical size and good electrical quality must be used; the leads must be as short as possible to avoid
oscillation induced by stray inductances. The use of a ground plane is recommended when using printed circuit boards.

PREAMPLIFIER CIRCUIT DESCRIPTION
The SL560 is a general purpose, low noise, high performance amplifier and
as such it has numerous applications, some of which are listed in the Data
Sheet (see Section 6).
An example of its uses and ease of application is best appreciated by
construction of the wide dynamic range pre-amplifier shown in Fig. B. The
circuit is designed to the performance specification given in Table 3.

Characteristic

Gain

35dB

Bandwidth
Noise figure (Rs

=

2000)

Dynamic range (BW = 1 MHz)
Current consumption
Output voltage

Table 3

Performance

>
<
>
<
>

150MHz
2.0dB
BOdB

50mA
1.0Vrms
into 1000
(resistive)

Performance specification of SL560 preamp. (Fig. 8)

145

Vee

330

Fig. 8

Wide dynamic range preamp. (2

x SL560)

The circuit consists of 2 stages of SL560, both in common emitter configuration, with the first stage giving 20dB gain and the second 15dB. The
input transistor of the first device is operated at 1.5mA, which gives a low
noise figure for a source impedance around 200 ohms. The input transistor
of the second SL560 has a feedback resistor in its emitter, which reduces the
stage gain and degrades slightly the noise figure, but increases the bandwidth and signal handling ability.
At high frequencies, the layout of the PCB has a considerable effect on the
overall frequency response of the amplifier. This is mainly due to-the high h
chip transistors and also to stray capacitance. The PCB to use, in this case,
is one with the minimum of copper track removed from the reverse side and
a continuous ground plane on the components side. The response is also
affected by supply line decoupling and for smooth frequency-apmlitude
response each stage of amplification is individually decoupled by high grade
ceramic capacitors. The layout of a suitable PCB for this amplifier is shown
in Fig. 9.
The influence of variations due to the PCB and the devices can be compensated by incorporating a trimmer capacitor across the second stage feedback resistor. This allows variation of emitter peaking and helps to achieve
an amplitude-frequency response within cI 0.5dB up to 200MHz. Fig. 10 shows
frequency response obtained with this amplifier, and Fig. 11 the power output
v. frequency.
When satisfactory frequency response is obtained other characteristics of
the amplifier can be measured. Typical figures obtained are given in Table 4.

Characteristic
OutP.ut power for 1dB compression
Noise Figure
Output voltage (supply 6V)
Current consumption
Table 4

146

Typical Performance
10mW
1.8dB
1.1V rms
35mA

Typical performance figures for Fig. 8

0)

•

•
0.
.•

• ••

_0

.I~o

Rl
RS

OUTPUT

INPUT

Fig. 9

Printed circuit board for 2 stage SL560 preamplifier

147

I
Vc

I I

= BV

R:.. :: 120A
37

36

-.;;;:::

5
34

-

...--.....

f--

I

r--...

\

MIN PEAKING6\
CAPACITOR

3
2

iii

3I

Y

OPTIMUM PEAKI-JG
CAPACITOR

\ \
\ \
\
\ 1\

0

~

29

8

,\

7

\ \

•
5

~

4

\

\
\

3
2
10

20

30

40

50

60

Fig. 10

\

\ 1\

10 10 90 100

FREQUENCY

200

300

400

SOD

(MHz)

Preamplifier frequency response

lOAJ
5

l"- f-

•

r-t--

'"

3

'\

",12

o

:.
8

1

1U

cr

r--:-.-..

0..10

9

...

III

8

I'\.
'\.

'\.

\
\

7

'\.

•
5
4

3

'

'\.

VCC·9V

r\
\
\

2
1

Vee ,6V

0
10

20

30

40

50

6!J

10 80 go 100

FREQUENCY

Fig. 11

148

-

\
1\ \

~

z

-

200

300

400

(MHz)

Preamplifier power and frequef!cy response

It

3 A 120MHz log strip using SL1521s
SL1521 GENERAL DESCRIPTION
The SL1521 is a wideband Ie .'3.mplifier intended for use in successive
detection logarithmic IF strips operating at centre frequencies up to 200M Hz.
Many radar systems use logarithmic IF amplifiers as a simple means of
compressing the dynamic range of the received signal from gOdS at the input
to a more manageable range for the processing circuit. This system was
chosen because in it the maximum output signal is provided by all stages
working in parallel.
150

2

.-------r--..--H==J-----OHV
.-_-+--<>4 Y~O
1000,

BIAS

INPUT

250

87

300

4·7\r

240

~NO~~-~~~+---~~-~--~

SOOp

Fig. 12

'--_-*_ _ _ _-+---<)8 GROUND

SL1521 circuit diaaram

A single stage of SL1521 is capable of 1mA (typ.) output when driven into
saturation with O.5V rms signal as shown in Fig. 14. The device has a defined
gain and frequency response, it provides a limiting characteristic, rectified
and non-rectified outputs and has a sensibly low noise figure (3dS typ.). It
is also capable of handling an overload input signal of t.5V rms without being
paralysed.

INPUT

4'1 POTENTIAL
DIVIDER
OUTPUT

470pF DC BLOCKING
CAPACITOR

Fig. 13

Simplified circuit diagram of SL1521

14~

The circuit, Fig. ~2, consists of an emitter coupled pair amplifier-limiter
with an emitter follower completing the amplifier section. The gain and
frequency response are controlled by series voltage feedback; a second
emitter coupled pair provides a low level detector with a current output.
Fig. 13 shows a simplified equivalent circuit of the SL1521. The potential
divider defines the gain of 4 and an amplitude-frequency response of 350MHz
(typ.) The 470pF blocking capaCitor defines the low frequency cut-off (6MHz
typ.). Careful design of both the long tailed pairs, the bias and the feedback
circuitry ensures that the amplifier limits symmetrically.
The supply line is internally decoupled by a single RC network consisting
of a 78 ohm resistor and 1000pF capacitor; this minimises problems of supply
line decoupling when devices are cascaded.
The long tailed pair input and emitter follower output forms an amplifier
with high input and low output impedances. This arrangement gives a flat
frequency response when the devices are cascaded because it stimulates
the condition of a voltage (low impedance) source feeding a high impedance
load.

6

4

J-

1·2

::J

~

::J

o

o
W
o

;;
~

u::
;:::

.......

1·0

r----..

o· ,

~

u

W
0::: 0-6

..

" '\

\

)(

~

l"'"

0-4

0-2

10

20

30

40

50

60

70

80 90 100

200

300

FREQUENCY (MHz)

Fig. 14

Video output of SL1521 series

Some problems may occur if very fast edge IF pulses are applied to an
SL521 or SL1521 strip. Fast leading edges, in general, do not cause problems
but a trailing edge faster than about 30ns may give rise to a small spike on
top of the video pulse just before it falls (see Fig. 15). The maximum amplitude
of this spike should not exceed 5% of the pulse height under worst case

150

conditions. In the event of this spike being troublesome it can be eliminated
by one or more of the following methods:1. Slowing down the trailing edge of me IF pulse.
2. Raising the low cut-off frequency of the strip by AC coupling or including
a filter.
3. Video filtering
If an IF filter is used to eliminate this spike, not more than three stages
should be cascaded before or after the filter.

Fig. 15

Response of10g amp. to a very fast pulse input

LOG IF STRIP DESCRIPTION
The circuit diagram design of an IF strip using the SL 1521 is shown in Fig.
16. This amplifier consists of six stages of cascaded SL 1521 integrated
circuits and two additional units are employed as 'lift' stages to extend the
dynamic range to over BOdS.
The IF signal is amplified by each stage in turn until a point is reached where
the input to the last stage is sufficient to drive it into saturation. It then contribute no more to the video summation line. With increasing input the preceeding stage saturates and so on until all stages are saturated and there
is no further increase in video output. It is this multiplying and subsequent
summation that constitutes the logarithmic action. The first amplifier in the
casC{ade gives its full output current at an input signal of about 100mV rms.
The input signal could be increased to 1.BV rms without overload. This feature
can be used to extend the dynamic range. If the input, as well as being applied
to the first device of the main amplifier, is attenuated and fed to one or more
additionaHCs in such a manner as to ensure that they do not add to the output
until the main amplifier is about to go into saturation, then we have a means by
which the dynamic range can be extended. The limiting criterion is the maximum input signal before overload which would paralyse the main amplifier.

151

Fig. 16

r--

r--... t--.....
...........

w

Circuit diagram of log strip

~

"'"'"

8

'"
~
o

.........

>

'"g
u
w
:::o

~

7

............

~ I---

u

6

-80

-70

-60

-so

-40

-30

-20

INPUT

Fig. 17

152

-10

10

(dBmJ

Dynamic range of log strip

20

60 MHz

Included in series with each video output is a 1k ohm resistor to prevent
instability caused by feedback along the summation line. A grounded base
transistor stage is also used to buffer the summation line and it can be followed
with a simple low pass LC filter in order to reduce IF breakthrough to a subsequent video amplifier.
The strip described above includes 'stopper' resistors in the supply line
which reduce unwanted feedback along the supply line and improve stability.
Interstage resistors are also included which improve the overall frequency
response of the amplifier. The measurements made on the above amplifier
indicate an IF bandwidth of 10 to 120MHz, with less than 3dB ripple in the
passband (see Fig. 18). The dynamic range is in excess of 80dB and the log
linearity ·O.75dB (see Fig. 17). The amplifier uses SL 1521 B devices; with
A grade devices a slight improvement in bandwidth (7.5MHz to 130MHz),
dynamic range (85dB) and log law ( 0.5dB) can be expected.
Layout of the SL 1521 strip is not critical as long as short earth leads are
used - a suitable printed circuit board is shown in Fig. 19.

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20

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FREQUENCY

Fig. 18

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400

500

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Frequency response of log strip

153

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input

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Fig. 19

154

Printed circuit board for log strip

••
•

4 A swept gain IF strip and detector
SL550 GENERAL DESCRIPTION
The SL550 is a general purpose wideband amplifier with an external remote
gain control facility. It has been designed to operate from a 200 ohm source
and it is therefore suitable for use with microwave mixers. The gain of 40dB
over the band of 125MHz is obtained with good noise figure (2dB). The external
gain control facility can be used to obtain a swept gain function; the SL550
is thus ideal for linear IFs or low noise pre-amplifiers in logarithmic strips.
The SL550 consists of a fixed gain amplifier, a variable amplifier together
with input and output buffer stages (see Fig. 20). External gain control is
performed in the feedback loop, hence the noise figure and output swing are
only slightly affected as the gain is reduced. The gain is specified with an
accuracy of c::1dB for a given input control current, hence a defined gain-time
law can be achieved.
The input transistor can be used in either common emitter or common
base and the output current of the emitter follower can be increased with the
addition of an external resistor to enable a low impedance load to be driven.

155

VARIABLE
GAIN AMP

LOW
11

NOISE
INPUT
DEVICE

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g

VARIABLE ATTENUATo~ TRACKING WITH VARIABLE
GAIN AMP

-

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13

Fig. 20

Schematic of SL550

SL510 GENERAL DESCRIPTION
The SL510 consists of a detector, a voltage regulator and a video amplifier.
The long tailed pair detector has both input bases accessible so it can be used
as a full-wave or half-wave detector. The detector can be used either on its
own or with the internal video amplifier, which in conjunction with the detector
will give 5.5dB gain in the half-wave mode of operation. The detector band
width is 100MHz and the video is 24MHz. The device can handle pulses as
short as 16ns, has a dynamic range of 25dB and can develop 0.5V across 50
ohms.

DESrGN OF STRIP
Fig. 21 shows an amplifier using two SL550s plus an SL510 detector. The
first stage is connected in the common emitter configuration which gives low
noise performance when driven with a 200 ohm source which simulates a
typical microwave mixer.
The second stage is connected in the common base configuration with 750
ohms at pin 7. The AGC current inputs are obtained through 3k ohm resistors.
These resistors were chosen to give 30dB of gain control with optimum
dynamic range.
Careful layout of circuit and selection of resistors for the AGC control lines,
together with the use of physically small ceramic capaCitors, ensures stable
operation of the amplifier. A gain of 80dB at 30MHz is obtained with a gain
reduction of 32dB with 6V control voltage.
An SL510 has been added to this strip to provide detection and video
amplification. The SL510 is connected in its half-wave rectified mode using
RC input coupling. The RF input is connected to pin 4, the base of the long
tailed pair. The other base is earthed through a capaCitor.
The positive-going half cycle of the input voltage is detected by the long
tailed pair and appears as a change in the voltage at pin 8, which is connected
through pin 9 to the input of the video amplifier. Due to the DC coupling
between pins 8 and 9, the output quiescent voltage depends on the current
flowing in the detector load. To make this less dependent on the beta of the

156

input pair, extra current is injected into pin 8 through a resistor R which is
connected to the internal supply line.
The amplifier-detector combination will handle linearly input signals up to
2.5mV peak to peak when the gain is reduced by the AGe. The minimum
input signal for a detectable video input is 2 microvolts peak to peak with maximum gain on the SL550s. Hence, the total dynamic range when used with
swept gain is 62dB.
With the component values shown on the circuit diagram the minimum RF
frequency is about 1MHz. At frequencies below this, the RF breakthrough
would be excessive.
A printed circuit board suitable for the construction of this circuit is shown
in Fig. 22 and the frequency response in Fig. 23.

YIDEO

OUTPUT

AGe

Fig. 21

ALL CAPACITORS = IOn"

AGe

Circuit diagram of variable gain amplifier

157

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RF OUTPUT

Fig. 22

158

Printed circuit board for variable gain amplifier

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10

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10

20

30

40

50

60

70 80 90 100

FREo.UENCY

Fig. 23

200

-

f-

300

(MHz)

Frequency response of variable gain amplifier

159

160

161

The SL362C is a bipolar integrated circuit consisting
of a pair of NPN transistors with exceptionally good noise
performance and an fT in excess of 1.6 GHz. It is in the
same family as the SL360C, with the same close tracking of
parameters inherent in a monolithic circuit, and is therefore

parameter contributing to noise in the transistor is base
resistance. The base resistance inherent in a particular
transistor process can be reduced by connecting a number
of elementary transistors in parallel to form a larger

suitable for use in circuits requiring a pair of well matched,

technique, the base resistance of the SL362C has been
reduced to 3012 compared with 25012 for the SL360C.
Fig.l shows a typical noise figure for the SL362C versus

transistor with much reduced base resistance. Using this

high frequency, low noise transistors. A typical application
in a DC to 200 MHz low noise amplifier is described in
detail, but some general data on the noise performance of
the SL362C is given first.

emitter current at the optimum source resistance for each
current. This optimum source resistance is shown against
emitter current in Fig.2.

LOW NOISE TRANSISTOR STRUCTURE

The major trade-off in the design of this type of low
At frequencies between the low frequency flicker

noise transistor structure is noise performance against high

noise region and the high frequency region in which the

frequency performance. However, the high fT of the
SL362C (see Fig.3) makes it possible to use the device at
frequencies well in excess of 60 MHz.

noise increases due to gain fall off effects, the dominant

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Fig.2 Optimum source resistance

optimum source resistance

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The frequency response of the amplifier shown in

SIMPLE FEEDBACK AMPLIFIER (FIG.4)

The amplifier has a response down to DC achieved by
the use of a long-tailed pair in the input stage, which also
gives low offset voltages and a convenient method of
applying negative feedback. The input is applied to Tf 1
and negative feedback applied to Tr 2 via resistors R 6 and
A 7. Tr 3 is current-driven from the long-tailed pair and
gives the output voltage across R 3. It is important to keep
the stray capacitance from R 3 to ground as small as
possible for the best high frequency performance. By the
use of the very high fT transistor pair SL360C for Tf 3 and
Tr 4 any shunting effect of transistor capacitances across

Fig.5 is flat to within ± 1 dB from DC to 240 MHz. The
small peak at 200 MHz is not layout dependent but is due

to parasitic lead inductance in the transistor packages.
Measurements were made with a son source impedance
and a load of 0.1 Mn + 2.5 pF. The amplifier will drive a
50n load up to 150 MHz if required. For simplicity the

noise figure was measured with a son source impedance
and a spot noise figure of 4.2 dB was measured at
frequencies of 30 to 200 MHz. The calculated variation of
noise figure with source impedance is shown in Fig.6, which
indicates an optimum noise figure of 2.5 dB at 200n source
impedance.

R 3 is reduced.
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163

LAYOUT

optimum of 200n. The other method is to connect two
transistors in parallel as shown in Figure 7. The effect of

It has been found that the circuit is not particularly
sensitive to layout change, but the obvious precautions in
constructing VHF circuits should be observed. Tran·sistor
leads should be kept as short as possible, in particular the
emitters of Tr 1, Tr 2 and Tr 3. The leads of R 7 should
also be short and if accurate gain stability is not required, a

this combination is compared with a single transistor in

Figure 8. The graph shows the calculated noise figure versus
emitter current with a 50n source impedance for both long
tailed pair and common emitter configurations. As can be

seen, a noise figure of 1.6 dB at 50n source can be achieved
with the arrangement of Figure 7 in a grounded emitter
configuration. The parallel connected combination will, of
course, have double the output capacitance of the single
device, but the effect of this on the high frequency
performance can be reduced by feeding into a low

carboncomposition resistor will give minimum inductance.

NOISE REDUCTION

Two techniques are available to reduce the noise
figure at low source impedances. One is to use a
transformer to produce a source resistance nearer to the

impedance. Also, the combination will have a lower fT than
a single transistor at a given operating current. However, if

the current is doubled
degradation wi II occur.

in

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EMITTER

CIRCUIT DIAGRAM

PIN CONNECTIONS

Fig.7 Parallel connection of two transistors

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164

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little

LOW COST
LOG IF STRIP

165

,

1. INTRODUCTION
Successive detection logarithmic IF Strips have held
a dominant place in professional and military pulse
radars for many years. Their ability to handle signals in
a very wide dynamic range without losing amplitude information is very difficult to better with other
techniques.
The advantages of log I F Strips have not been available in the past to manufacturers of low cost radars
due to the high price of the components required.
Now Plessey is offering low cost ICs which can be
used to make a very wide dynamic range strip at a
component cost below £10.
This major cost reduction has been possible by our
experience in manufacturing the SL521 series of
military grade log amplifiers, by the use of

sophisticated automatic test equipment and the choice
of an eight lead plastic package for the integrated cir-

cuit.
This note contains a brief introduction to the operation of successive detection IF Strips, a description of
the circuitry used in the Plessey integrated circuits and
practical details of a strip which can be used at 30 or
60 MHz. The main features of the Strip are:-

Centre Frequency
Bandwidth
Input Signal Range
Output Voltage Range
Current Consumption
Video Rise Time
Noise Figure

30 or 80M Hz
up to 15MHz
-60to +15dBm
20 ~ V to 1.2 volts rms
0.1 to 2.0 volts
140mA
20ns
4dB

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2. SUCCESSIVE DETECTION LOG STRIPS

Fig. 2 SL521 transfer function

The basic stage used in a log strip is shown in Fig. 1.
A limiting amplifier with a gain of around 10dB is
followed by a low level detector. One input and two

outputs are provided, an RF output and a detector output which is commonly referred to as the video output.

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VIDEO
OUTPUT

Fig. 1 Basic log stage
The responses, RF in to RF out and RF in to video out,
for a typical member of the SL521 family are shown in
Fig. 2. An important feature is that the video and RF
outputs limit at a particular input level.

166

Fig. 3 Three stage strip

Consider a 3 stage strip built with circuits of this
type as shown in Fig. 3. The first stage will clearly give
a video output identical to the single device. The
second stage receives an input signal increased by the
gain of the first stage. Over the range of the detector
this gain is constant so when a logarithmic scale is
used for the RF input the second stage video output
will be identical to that of the first stage just displaced
to the left by the stage gain, as shown in Fig. 4.

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3. THE SL521 SERIES CIRCUITRY

STAGE 1

VSTAGE 2-

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The Limiting Amplifier

IITI!

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Thus, using the techniques outlined above with a
simple stage of the type shown in Fig. 1, a log IF Strip
can be built with a dynamic range limited at one end
by the noise and at the other by the overload level of
the first stage. With well matched stages the strip will
give an accurate log law and video detection is an integral part of the strip.

INPUT VOLTAGE

Fig. 4 Video outputs from 3-stage strip

The final step in making a log strip is to sum the
video outputs from each stage. The schematic and
corresponding response is shown in Fig. 5.
We now have a log response. For each increase in
input level corresponding to the stage gain, a contribution equal to the maximum video output from a single
stage is added to the summed video output. It is interesting to see from rig. 5 that by careful shaping of
the detector turn on characteristic (such that it goes
from minimum to maximum output for an input
change equal to the stage gain) a very accurate log law
can be obtained.

The circuit diagram of the SL521 is shown in Fig. 6.
This Ie contains all the components necessary for a
single stage of the type described above. Voltage
amplification is provided by the long-tailed pair TR 1,
TR2.
The gain ( x 4 or l2dB) is defined by feedback derived directly from the RF output and applied to the base
of TR2. This feedback also controls the RF output
quiescent voltage. The difference between the input
and output quiescent voltages is kept low so that
cascaded stages can be directly coupled.
The Detector
TR4 and TR5 form a simple half wave detector with
,an open collector, current output.

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INPUT VOLTAGE

Fig. 5 Output from strip

The dynamic range of a log strip can be extended by
simply increasing the number of stages. The limit is
reached when the last stage in the cascade reaches full
video output solely on the noise produced by the first
stage.
The number of stages can then only be increased if
the bandwidth of the strip is reduced. It is common
practice to insert a bandpass filter in the centre of the
log strip for this purpose. Another technique for increasing the dynamic range is to attenuate the input
signal and apply it to another short strip operating in
parallel to the main strip. The video output from this
subsidiary strip is added to that from the main strip.
Normally the log response limits when the input signal
exceeds that necessary to produce full video output
from the first stage. However the subsidiary strip is
being fed with an attenuated signal so will continue to
give an output change. The limit to this technique is
reached when the input voltage is sufficient to cause
damage to, or overload in, the first stage of the main
strip.

Fig. 6 SL 521 circuit diagram

In the quiescent state the base of TR5 is biased at a
voltage approximately l00mV lower than the base of
TR4. Hence TR5 is off and virtually no current is drawn
by the detector output. When an RF voltage is applied
to the input of the SL521 the base of TR4 is driven
with the RF output voltage by the emitter follower
TR3.
Since the base of TR5 is decoupled by the 350pF
capacitor, no RF voltage will be present.
On the negative going half cycles of the RF, TR4 will
switch off and TR5 will conduct.
The l00-ohm resistor between the emitter of TR4
and TR5 causes the video output current to increase
gradually with increasing RF input over a l2dB range
so that a straight line log characteristic can be
obtained.
The open collector video output enables the video
outputs to be summed by just connecting all the outputs to a common load resistor.

167

There is no smoothing of the video output provided
internally and the video output at frequencies up to
60MHz follows closely the negative half cycles of the
RF waveform. There is no internal limit on video rise
time. Obviously there must be some video filtering to
remove the RF component present on the video line
and this can be an important part of the strip design
when very fast rise times are involved. However in
most cases simple R~C filtering is sufficient.

Oscillations caused by earthing problems do not occur as long as the earth pins are connected by short
leads to a good ground plane.

4. SELECTION GUIDE
The table above. describes the current
Plessey Semiconductors devices suitable for building
successive detection log strips. The general feature of
the devices is that the cost of a device depends mainly
on the tightness of its specification. The premium
device, the SL521A has a gain specification of 11.5dB
min. and 12.5dB max. at 30MHz and the device we
have used in the low cost strip is the SL 1613 which has
a specification of 10.4 min. to 13.3dB max.

Cascading Stages
Several features of the design have been included
specifically to ease problems of cascading many
stages. The low input·output differential voltage
means that the amplifiers can be cascaded without
coupling capacitors. Internal supply line decoupling is
provided by the 150-ohm resistor in series with the
supply and the 500pF internal capacitor. This is suffi·
cient to largely eliminate the problem of feedback from
output to input along the supply lead. Another poten·
tial source of oscillations is feedback along the video
line. The simplest way of preventing this without
sacrificing video response time is to put a resistor in
series with each video output and then sum the currents in a stage with a low input impedance. Fig. 7
shows a simple method of achieving this with a common base summing transistor.

5. GENERAL DESCRIPTION OF lOW COST
STRIP
The low cost strip using the SL1613 is shown in Fig.
8. The strip basically follows the concepts outlined in
previous sections. The most unconventional feature is
the use of a negative supply. This feature makes
decoupling and earthing a little more difficult but has
been used to simplify the video output. A conventional
strip will have a positive supply and the video output
will be generated in a resistor connected to this supply.
In many systems it is undesirable to have the output
referred to the supply and a high slew rate OP amp has
to be used to obtain an output voltage referred to
ground. This works very satisfactorily and a circuit using the SL541C video amplifier is shown in Fig. 9.
However the cost of this circuitry is significant and can
be eliminated by using a negative supply and
generating the video output in a resistor connected to
ground. The video output is then a negative going
voltage referred to ground which can be easily processed by succeeding circuits.
A detailed circuit description and constructional
details are given below. Typical performance graphs
are also given. Since the Sl1613 has wide gain and
video output variations the accuracy of the log law will
be quite variable. However several strips have been
built here and they all lie well within the expected
± 3.5dB accuracy.

"

INPUT

Fig. 7 Use of common base summing stage

SELECTION GUIDE
Frequency Range

Grade

Gain
Accuracy

Typical
log Accuracy

T05

20 - 60MHz

Dual
Stage
Single
Stage
Single
Stage
Single
Stage

T05

20 - 60MHz

T05

30 - 60MHz

A
B
C
B
C
C

±0.5dB
±0.7dB
±1.0dB
±1.5dB
±2dB
± 1.5dB

±ldB
±1.5dB
±2db
±1.5dB
±2dB
±3dB

Very small/lightweight
Log Strips
Low Cost Strips

8 Lead DIL
Plastic
T05

30 - 60MHz

C

± 1.7dB

±3.5dB

Very Low Cost Strips

20 - 200MHz

T05

20 - 200MHz

±O.5dB
±O.8dB
± 1.2dB
±2dB

± 1db
±1.5dB
±2.5dB
±2dB

Wide Band IF Strips

Dual
Stage

A
B
C
C

Number

Type

Package

SL521

Single
Stage

SL523
SL525
SL1613
SL1521

SL 1523

168

Application
Military / Professional
Log Strips

Small/lightweight
Wideband Strips

Fig. 8 Circuit diagram of low cost strip

10k
10,
10k

OFFSET
ADJ

Fig. 9 Video output stage

6. CIRCUIT DESCRIPTION
The connection to each of the IC's is very similar.

Pins 1, a and 5 are joined together and connected to
the negative supply, Pin 2 is earthed and the input is
applied to Pin 6. IC's 1, 5 and 8, being the first devices
in directly coupled cascades, have the bias Pin 7 can·
nected to Pin 6. The video output is taken from Pin 4
and the RF output from Pin 3. The resistors R1 to R9
prevent feedback along the video line which is
decoupled by C7 and feeds into the output transistor
TR 1. R14 and R15 provide bias for the base of TRl
which is decoupled by C6.
The output voltage is generated across R13 which
could be varied to adjust the slope of the log

The resistor network at the input to the strip R10 and
R16 provide a 50-ohm input impedance and attenuate
the input signal for application to the subsidiary strip
Ica and 9. The value of R10 should be in theory be 15
times R 11 but in practice it is chosen to give a straight

log law at input signals greater than OdBm. The filter
between IC's 4 and 5 defines the IF bandwidth. The
values given are for 60MHz operations with a band-

width of about 15MHz. The bandwidth of the filter is a
compromise between sensitivity and response time. If

the bandwidth is too wide IC7 will produce full video
output on the noise produced by the first stage and the
dynamic range will be reduced. Another important requirement on the filter is that it should, at resonance,

characteristic. The video response time is determined
by C7. Lower values for this capacitor would improve

duce a kink in the log characteristic at input level bet-

the response time at the expense of IF breakthrough.

ween - 50 and - 6OdBm.

have unity voltage gain. Any errors in the filter will pro-

169

Th~ log strip is not designed to drive long lines on
the video output. To prevent a degradation in video
response time the load capacitance should be kept
below 2OpF.

7. CONSTRUCTIONAL DETAILS
The schematic of a printed circuit board is given in
Fig. 10.
Double sided PCB has been used with a minimum
8":lount,of copper removed from the component side.
It IS advisable to solder all earth connections to both
sides of the board.
The resistors used on the prototypes were 0.125W
moulded carbon throughout and the capacitors were
general purpose radial lead ceramic types similar to
'Erie Redcaps'. The inductor is a fixed Cambion type.
The component overlay shows recommended supply
line decoupltng components. Provision has been made
on the PCB for additional decoupling capacitors but
they have not been necessary on the prototype strips.
Two negative supply points are marked on the PCB
which can simply be connected to a common supply,

8. PERFORMANCE
The input output characteristic of a typical SL 1613
strip is shown in Fig. 11. The BOMHz input power in
dBm. (dB with respect to 1 milliwatt in 50 ohmsl is
plotted on the X axis and the negative output voltage
on the Y. It can be seen that a log range greater than
90dB is obtained from + 15dBm -75dBm and that all
the points are within 3dB of a best straight line. This

response was measured at 60MHz with a CW source.
Figure 12 shows the input/output characteristic of a
typical strip as the supply voltage. The only effect over
a voltage range of - 5.5 to - 7.0 volts is a small variation in the slope of the log characteristic.
The pulse performance of the strip is shown in Figs .
.13 and 14. Figure 13 shows the pulse response with an
Input pulse at 60MHz of 0.5~s varying in amplitude
from OdBm to - 8OdBm. Figure 14 illustrates the effect
of input pulse lengths from 0.1 ~s to 0.6~s. The video
rise and fall times are about 0.05 s and the pulse is
stretched by about 0.05~s at the 50% points. If these
rise and fall times are not fast enough then the video
smoothing capacitor can be removed, which increases
the BOM Hz breakthrough but approximately halves the
rise and fall times. Figure 15 (a) shows the response of
the normal circuit to a 0.1 ~s pulse and Figure 15 (bl
shows the effect of removing C7. Figure 15 (c I shows
the response of a strip with C7 ~ a to 60MHz pulses
With Widths of 0.050, 0.1 and 0.15 ~s. The peak video
response to a 0.05~s pulse is about 20% less than that
of a CW signal.

170

9. A FEW HINTS ON TESTING LOG STRIPS
The log characteristic such as Figure 11 is one of the
most important measurements to be carried out on a
log strip. This is most easily measured with a CW
source, a digital voltmeter and an attenuator. A high
quality attenuator is, of course, needed for measuring
strips with an accurate log law. It is not uncommon to
find a previously unknown fault on a lab attenuator
when testing an accurate log strip.
As explained in Section 6 the log characteristic can
highlight several possible faults, for instance a change
In slope above OdBm indicates an error in the input attenuator (RIO-RIll and a kink around - 50 to BOdB
suggests problem with the filter. Measuring log
responses by a manual point by point method can be
rather tedious and a commercial log test set can be
used to speed this up. It is also possible to use a signal
generator which includes a programmable attenuator
linked to a X Y plotter. The block diagram of the
simple test system is given in Figure 16.

·

...

. ..

.

L
Printed circuit layout

Component location

PCB ground plane

Fig. 10 Printed circuit board Scale 2:1

171

,
,
,
,
,
,

,.,

v

/'
)"

I-- ,....... V

/.

v: 'l L,.... '--

,
.,
.,
.,
.,
.,

/'

VINPUT POWER (dBm)

,..--"
.--,..--

co

.,
,
,

~ 'l /

~ I/::

= F'"" I"""

~

Fig. 11 Dynamic range for SL 1613 strip

~~
~V

-60

-40

INPUT IdBm)

Fig. 12 Effect of supply voltage

INPUT60MHz .....
VIDEOO/PO.2V/cm . . . . .

(;",._ _ _ _ INPUT PEAK POWER

Fig. 13 Pulse response v. input power

INPUT60MHz ........
VIDEOO/PO.2V/cm ----..

...... INPUT PULSE WIDTH

Fig. 14 Pulse response v. input width

172

--.
lOOnS

Flg.75a Response to narrow pulses

INPUl

~

r

(input 700ns/

20dBm, C7 =

l000pF)

Fig.15b Response to narrow pulses
(input l00ns/ -20dBm,

"nput

50, 100,

/filii

C7

,':jOns. C7

0::

0)

OJ

173

The measurement of bandwidth can also be carried
out with the equipment shown in Figure 16 but turning
of the filter is more easily achieved with a swept tuning

system such as that in Figure 17.

Bandwidths can be measured by using the input attenuator and reading 3dB, 20dB widths etc. from the
oscilloscope. It is much easier to measure IF to video
characteristic as above than to measure from I F input
to IF output. The IF output of the strip limits at just 10
to 20dB above the noise and the combination of the
high IF gain and this small dynamic range makes it a
rather difficult measurement.

Once the log characteristic and the bandwidth have
been measured the only important characteristic left is

the pulse response. The only difficulty with this
measurement is the generation of a suitable IF pulse.
The best method is to generate a pulse at a microwave

frequency (say 2GHz) with a PIN diode modulator and
then mix this down to IF. In this way a pulse with a
high on-off ratio and with very small video breakthrough can be generated. This however involves a lot
of expensive test equipment and simpler methods can

Fig. 16 Log characteristic measurement

be used to generate a usable pulse directly at IF. It
should be remembered that the log amp will exaggerate any small imperfections in the pulse. An on-off
ratio of aO-90dB is needed and breakthrough of the
video pulse edges must be kept very low. Two cascaded double balanced mixers can generate a pulse with a
high enough on-off ratio but will generally have a video

breakthrough level which is too high for most measurements. High isolation solid state switches are available

which will generate an adequate pulse at IF frequencies and such a switch was used for Figures 13 and 14.

A log amp will have a strange effect on a pulse with
exponential rise and fall shapes as shown in Figure 18.

The log amp will apparently sharpen the leading edge
and slow down the trailing edge of such a pulse. This
effect is not caused by any deficiencies in the log amp

Fig. 17 Bandwidth measurement

but happens for a theoretically perfect amplifier.

0

0

"
z

;;

"

,

V

\
\

I

I

INPUT PULSE

/

YOUT'"

,

LOG (1 +bYIN)

:::00 I

,

\

,

I

OUTPUT PULSE

,
TIME

Fig. 18 Effect of log. amp on pulse response

\
1\

,

TIME

174

\

1/

_. I---

\

DIGITAL SIGNAL
PROCESSING
APPLICATIONS

175

Introduction
Most variables encountered in electronic systems change in a continuous
or analogue fashion, and indeed most transducers provide analogue outputs.
Nevertheless, there is a growing trend to apply more and more digital control
and computation hardware to commercial, industrial and military equipment.
One reason for this is the increasing availability of digital logic and memory
integrated circuits at very attractive prices. Recently, the high speed capability of the ECl logic family has extended the range of frequencies for which
digital processing is possible. The advantages of digital processing techniques are well known, and include such benefits as high accuracy and high
noise immunity in environments which could seriously impair the performance of an equivalent analogue system. Analogue to digital converters
(ADCs) are an essential part of all such systems.
Digital signal processing is now practical at video and IF frequencies and
is consequently being applied to television and radar systems. Other areas
in which high speed analogue to digital conversion is being used are fast
transient analysis, fast data transmission and secure speech transmission.

1 A to D conversion
CONVERSION METHODS
There is a great variety of conversion techniques which are at present
being pursued. It is fair to say that the majority of these are more suitable for
lower speeds where they have achieved low cost, low power consumption,
or extremely high accuracy up to at least 14 bits. When the highest possible
conversion speed is essential the choice of techniques is narrowed down
considerably.
The majority of ADCs accept an AC input signal, which can occupy an
equal positive and negative range, and the input/output function is usually
linear. The output code is normally a binary N-bit code in which the all 'D's
state corresponds with the most negative input voltage and the all '1 's state
corresponds with the most positive input voltage. In some cases the outputs
may be presented as an N-bit output code plus a sign bit, giving the converter
effectively N + 1 bit accuracy. ADCs do exist which differ from these formats
to fit special needs, such as a Gray coded output or logarithmic transfer
characteristic.
All parallel
The fastest known conversion method is the all parallel converter shown
in Fig. 1. It is so called because 2n-1 comparators compare the analogue
input with an equal number of reference voltages. The reference voltages are
uniformly spaced, and span an equal positive and negative range. The centre
reference voltage is therefore zero. The outputs of the comparators are
encoded by logic circuitry to give an N-bit logic code. A latch signal is fed to
the comparators which forces them to make an unambiguous decision, i.e.

176

give a true logic '0' or '1' at the output, so preventing spurious output codes.
In this way, a synchronous output is obtained. This is a very basic converter
schematic and a practical ADC may include refinements such as output
latches to re-time the output bits, an input sample and hold circuit, or the
provision of a "conversion complete" timing signal. The speed of this type
of converter is in principle only limited by the time the comparators take to
make an unambiguous decision. There is also the advantage that if the
"acquisition times" of the comparators are well matched, the system can be
operated without an input sample and hold circuit.

VREF t VE

2 n -1
COMPARATORS

r---A----.,
ANALOGUE
INPUT

o--+--.r-l "~>-----J---'
.)

ENCODING
LOGIC

l'

PARALLEL
BINARY
OUTPUT

VREF -VE
LATCH INPUT

Fig. 1 The all parallel conversion method

All parallel, or "flash" converters as they are sometimes called, can be
conveniently constructed using discrete comparators up to four or five bits.
Beyond this it is highly desirable to have more than one comparator integrated into a single monolithic chip, to offset the problem of increasing size
and cost. It is difficult to distribute the analogue input signal to a large array
of discrete comparators with sufficient amplitude and phase accuracy, and
to provide adequate latch timing accuracy. In addition, the output encoding
gives rise to timing problems for higher bit accuracies. An integrated circuit
which offers four or more comparators in a single package will considerably
ease the above problems.
All-parallel converters have been built which are capable of clocking at
up to 100 million samples per second, and with accuracies of up to 6 bits.

177

Parallel/series
The parallel/series conversion method is a hybrid form which is a compromise between the characteristics of all-parallel and all-series converters.
A variety of designs are possible using 2, 3 or even more stages of conversion.
Fig. 2 shows a converter in which two four-bit stages are connected in series
to give eight-bit conversion accuracy. The analogue input is fed into a fourbit all-parallel converter of the type previously described, after first being
sampled by a sample and hold circuit. Here, a coarse quantisation is performed which provides the four most significant bits (MSBs) of the output
code. The output is fed into a four-bit digital to analogue converter (DAC),
having eight-bit accuracy. The result is an analogue level which is an approximation of the input to the nearest four-bit code below the original signal.
This is then fed into a subtractor circuit element together with the sampled
analogue input.
ANALOGUE
INPUT

'---'---'--'----'-,vr--'--'--'-~

3 BIT BINARY OUTPUT

Fig. 2 The parallel series conversion method

The difference voltage will come within the range of the second four-bit
ADC stage, which is again an all-parallel converter. The quantised output
provides the four least significant bits (LSBs). Since the analogue Signal has
to propagate through an ADC and a DAC, and be compared with the input,
the sample and hold is required to store the analogue signal for approximately one clock period to the full eight-bit accuracy. The outputs from the
two stages are re-timed in a group of latches to give synchronous outputs.
The parallel-series converter has the advantage over the all-parallel of
using less hardware, and hence less power is consumed. For example, an
eight-bit all-parallel ADC uses 255 comparators, whereas a 4 x 4 bit parallel!
series converter uses only 30 comparators. However, because the analogue
signal has to propagate through several stages, conversion rate is lower than
is possible with the all-parallel converter. The parallel/series ADC therefore
provides a compromise between cost, power consumption, size and conversion speed. Other versions of the parallel/series converter may have more
stages, for instance, 3 x 3 x 3 bit stages could be used to give nine-bit
accuracy using 21 comparators, at correspondingly lower speed.

178

Successive approximation
The third converter to be described is the successive approximation type.
It has been hitherto regarded as a slow conversion method, but with today's
technology - ultra fast comparators, fast current switching, etc.- a very useful
performance is obtainable. An attractive feature of the successive approximation technique is that it requires very little hardware. It is consequently
possible to integrate an ADC of this type onto a single chip with eight-bit or
higher accuracies. The successive approximation converter, shown in block
form in Fig. 3 uses a. DAC in a feedback loop. In operation, the shift register
sets a 1 in the MSB latch, all other latches being in the logic 0 state. The DAC
output is compared with the analogue input and the MSB latch remains set
or is reset to 0 depending on whether the analogue input is greater or less
than the DAC output. During successive clock periods this process is repeated
with bits of diminishing significance. The DAC output therefore becomes a
progressively more accurate approximation to the analogue input, taking N
clock periods to achieve N-bit resolution. As with the parallel/series ADC a
sample and hold is essential, although it may not be included in a monolithic converter. Using present-day teChnology, a monolithic successive
approximation converter of eight-bit accuracy and a sample rate of 15MHz
is feasible.

ANALOGUE
INPUT
0----.,

PARALLEL
BINARY
OUTPUT

CONVE RSIO N r--....I....--,
COMMAND

I--_ _ _ _ _ _ _.. CONVERSION
COMPLETE

CLOCK INPUT

Fig. 3 The successive approximation conversion method

179

SPEED, RESOLUTION AND ACCURACY
The most important parameters when designing an A-O converter system
are speed, resolution and accuracy. Speed is usually expressed as maximum
sample rate and the maximum input frequency is limited by the Nyquist
theorem to half of the maximum sample rate. In most converters, it is essential
that this input limit does physically exist in the form of a low pass filter.
Furthermore, the Nyquist limit point is actually 3db down, so for a flat response,
the input should be rather less than half the sample rate.
Resolution of a converter is defined by. the number of bits available, e.g.
an eight-bit converter has a resolution of 1 part in (2 8 - 1) or 1 in 255 (zero is
also a step, so 256 levels are defined).
Accuracy may be equal to, or better than, the resolution, i.e. the converter
may be specified as L~LSB or evend~LSB, or, exceptionally, . ,bLSB.
WhileI,~LSB is the minimum accuracy that will guarantee monotonicity,
drLSB may be useful when, for instance, the temperature coefficient is
,l:~LSB over the range. In this case, the sum of a ±~LSB basic accuracy,
plus a ±~LSB temperature shift will give adLSB accuracy over the temperature range. Many converters are not specified to the most desirable degree of
accuracy. A common specification on eight-bit conversion is 1 % i.e. ±0.5%
when the resolution is 1 in 255, i.e. the resolution is greater than the accUlacy.
Usually, this type of converter will be monotonic over the full range, but
departs from the ideal linearity in the mid-range; the error occurs at the midrange, because the start and end pOints are defined by scale and offset
factors. At lower speeds, specific systems may demand a higher resolution
(i.e. number of bits) than can be achieved with a matching accuracy and
linearity. A typical example is high quality audio in which quantisation noise
and hence dynamic range is of extreme importance, but absolute accuracy
is of less importance.
At video speeds, resolution and accuracy are usually equal except under
transient conditions, when small inaccuracies are tolerable - an example is
in video processing when the interval between fields may be used for programme source change.
THE COMPARATOR-AN IMPORTANT CIRCUIT ELEMENT
The AOCs described above use at least one comparator. Indeed all conversion techniques use a comparator of some kind. The speed performance
in most, if not all, conversion systems is dependent on the response time of
the comparator(s). Even low speed converters can require fast comparators,
especially when very high resolution is required.
To achieve the highest possible conversion rates, a comparator with an
extremely fast response is needed. To make an impact on the attainable
performance of high speed converters it is essential to start with the comparator design.
Until recently, commercial comparators have used high gain (greater than
1000) to obtain the mV resolution necessary in A-O conversion. .
When the converter operates in a synchronous mode (which is invariably
the case in present-day converters) there will be a clock pulse available to
enable the comparators to operate in the latching or sample and hold mode.
In essence a latch is a positive feedback circuit: during the latch cycle, the
gain tends towards infinity. This feature ensures that a comparator of even

180

very low gain in the sample mode will resolve a 1mV signal. By accepting a
low gain, the comparator design can be optimised for a very wide bandwidth
and extremely fast response time.
Later sections of this handbook describe the Plessey high speed comparators which use this principle to achieve set up times of 2ns and input to output
delays of less than 3ns.

2 Practical system design
MICROSTRIP TECHNIQUES
Microstrip techniques have been used in the microwave field for many
years and are now well characterised. Relatively recently, the advantages of
accurate matching and minimisation of reflections associated with microstrip
have been adopted for high speed digital circuitry. When the edge speed in a
circuit is comparable with the propagation delay down the lines in use,
microstrip is needed.
A cross-section diagram is shown in Fig. 4. Points to note are that the
devices are usually mounted on the ground-plane side of the double-sided
board; the presence of the ground plane accurately defines the line impedances, provides low impedance current path for the ground supply and
convenient decoupling for the other rails.

iWi

7-!--------------- .---,

r-~------------O-IE-LE-[T-R-I[-E-r----------~~.
GROUND PLANE

Fig. 4

The characteristic impedance, Zo, of a microstrip line is

Zo
r

=

j

~ :~.41
r

in

(0.:·: : t)

relative dielectric constant of the board, typically r
for glass-epoxy.
w, hand t are defined on Fig. 4.

=

5

Standard tables and graphs are available in the literature on microstrip to
calculate the line width needed for a given Zo (Fig. 5).
In practice, line impedances greater than about 150 ohms are not realisable
in the copper-glass-epoxy system.

181

The technology of microstrip board is relatively straightforward and follows
good printed circuit board practice. 'he use of double-sided board is strongly
recommended.
_15

.s.

O~~t-...'l"""""

~

<>

N

.....
w

0-8

z

0..

I I

. . . . :::-i-..o> =

r---....~

['-.0 ....... ~
~ 1'-,.......
~

:'-....

t-......'"""
..........

1"- 1"-...

I

I

I

,
1'-..,

::-....... ........ )"'0.,

l'.: J'.....~ ~........ I:"

~ t-...~ ~t-...

! .......

MICROSTRIP LINE WIDTH

2-0

I--

i'..

~~

15

I
~
l'

'" ~ t-..r-I': 1'-.. t-... ~

~~ ~

10

'
I

, """"
.......................

~.......

r--.....

,

i

i
i
c...... --+-

I

~ 1"t-..

3-0

4-0

I--

~

50

10

W (mm)

Fig. 5 Characteristic line impedance as a function of the line width for microstrip
lines (Parameter is board thickness h(mm) ~r ~ 5, t ~ 351J)

The choice of board thickness and specification depends primarily on the
application; best results are obtained with good quality board of reproducible
characteristics. The capacitance per unit length of conductor is predictable
from modified parallel-plate capacitor formulae; in practice, the graph of
Fig. 6 is a good guide. Variations in dielectric constant of the board change
Zo in the ratio of about :.L2% in Zo for :.1::5% in ~r.
Zo (n)

C (pF/cm)
30

20

t

2-5

30

40

2-0

1·5

50
1-0

100

0-5

150
0

0-1

1-5

MICROSTRIP LINE WIDTH

2-0

IO

"0

5-0

10

W (mm)

Fig. 6 Intrinsic line capacitance as a function of line width for microstrip lines.
(parameter is board thickness ~r = 5, t = 351J)

182

The inductance per unit length of the line may be calculated from the
formula:
Lo
where Zo
Co

=
=

=

Z02. Co
characteristic impedance
capacitance per unit length

The propagation delay of the line is approximately
tpd

=

3.3 X 10 2. J0.475 ~r

+ 0.67

Must glass-epoxy board has ~ r~ 5, so tpd
between tpd and h is illustrated in Fig. 7.

=

ns/cm

0.05£ ns/cm. The relationship

E

~

0-06

u1

c

"D

"""- 0 ·05

I

/~

/

V

......-

~

V

./

'/
\

RELATIVE

DIELECTRIC

CONSTANT

lUi

Fig. 7 Propagation delay as a function of the relative di'electric constant of the
board material for microstrip lines

Line loading
Most devices connected to the microstrip load the lines capacitively. In
some cases, such as logic inputs, there is only a single load capacitance on
a relatively long I ine, and the effect can be ignored. On parallel outputs,
especially where settling times are important, the effect of loading on the line
must be compensated for. Basically, this means that the total load capacitance
per unit length of line must be calculated and then the line designed in such a
way that the loaded impedance matches the actual working impedance
desired. Load capacitance per device is taken from the manufacturer's data
or by measurement from the devices.
A fairly accurate assessment of the inter-device spacing is needed, and
the types of device must be considered. Eventually, some figure of Co, the

183

load capacitance per unit line length, can be derived. The standard equation
for loaded lines is
Zo'

Zo

)1 +Co
Co
where Zo' is the
Zo is the
Co is the
Co is the
Tables and graphs for this

characteristic unloaded impedance
loaded impedance
load capacitance in pF/cm
line capacitance in pF/cm
function are shown in Fig. 8.

Zo (UNLOADED);;. 50 n

Zo

LOADED

Fig. 8

Tables and graphs for this function are shown in Fig. 8.
Loading in most systems is distributed, in the way described, along the
lines but, in reality, does represent discrete 'lumps' of capacitance at finite
points, and so any compensation scheme cannot be perfect, but practical
systems if well-designed show minimal line impedance disturbance. Of
course, the propagation delay is increased by capacitive loading, in the ratio
tpd

=

t' pd

l

+C0
Co

where tpd
t' pd

=
=

final delay
delay of unloaded transmission line

This function is illustrated in Fig. 9.

184

tpd = 58 (psicm)

_Nr---,---,---.-r----"",..---,..---,..---.,..-----.

E
u

LL
0-

"02·0

LJ

1---f---f-----l.+----i----I-tl--I--11-+4I----/-+----I

r-r--fI

L.W

:z
-'
I--

12

.

----r--

-i--I!

~

I

I
I
I
- I -----I
I

04 j - - - - j - - - - - t _

~
LJ

Cf

«

LJ

00~-~2~0--~470--~--~B~0--~1~00--~1~20~-~1~40~-~160

MICROSTRIP PROPOGATION DELAY WITH CAPACITIVE LOADS. tpd (ps/em)

Fig. 9 Variation of the propagation delay line of a microstrip line as a function of
the capacitive load per unit length. ~ r = 5, Parameter is Z 0

ECl IN ANALOGUE TO DIGITAL CONVERTER SYSTEMS
Plessey A-O products are ECl compatible in terms of input and output
logic levels. If full use is to be made of the advantages of ECl, proper transmission line design rules must be observed. Fig. 10 shows a simple line with
driver and load. Initially, we assume that the line delay is appreCiably longer
than the rise and fall times, so that reflections occur at full amplitude. The
output voltage swing at point A is a function of the internal device voltage
swing, the output impedance, and the line impedance
Zo
VA =VINTX - - - -

Ro
Normally, Ro is small, so

+ Zo

VA ~ VINT.

This signal arrives at point 8 after time t. The voltage reflection coefficient
at the distant end of the line is pl, which is given by the formula
RL-ZO
pl=--RL +Zo
If RL = Zo there is no reflection; even if RL is an approximation to Zo, the
reflections will not be large, as a 1 % change in RL changes pl by only 0.5%.

185

When a reflection occurs, however, it will return to A, arriving at a time 2t,
and be reflected with a reflection coefficient
Ro -Zo
ps=----

Ro

+ Zo

RL MAY BE COMPOSITE
(OMPONEN T

Fig. 10 Transmission line in EeL

In the worst case conditions, the signal will suffer many reflections of
significant amplitude: clearly this is not permisSible, as it represents 'ringing'
on the line. In ECL practice, ringing should be maintained below 15% undermaintained for short runs; Table 1 illustrates the maximum lengths allowed,
assuming 20%-80% rise/fall times of 3ns.
Fanout

Line
impedance

1

2

4

8

50
68
75
82
90
100

21.1
17.8
17.5
16.8
16.5
16.0

19.1
15.7
15.0
14.5
13.7
13.0

17.0
12.7
11.7
10.7
9.9
9.1

14.5
10.2
9.1
8.4
7.6
6.6

Permissible unterminated line lengths (em)
Table 1

The simplest termination scheme is shown in Fig. 11a. Since the input
impedance of ECL parts is relatively high, RL is made equal to Zoo Then pL = 0
and the voltage on the line is the full ECL swing. In large systems, this technique is used extensively bufhas the disadvantage of requiring a -2 volt
rail in addition to the normal supply. Fig. 11 b shows a convenient realisation
of the same circuit using 0 and -5.2 volt rails only. With parallel terminated
lines, the load provides the pulldown for the driving device. This termination
is the fastest form for ECL. The full amplitude signal is progapated down the
line, undistorted and, as pL ~ 0, overshoot and ringing are practically eliminated. The Thevenin form (Fig. 11 b) is fully equivalent to the system of Fig. 11 a
but operates on more convenient power rails. Clearly, the parallel combination

186

la)

SINGLE

RESISTOR

-2V RAIL NEEDED
-2V RAIL

Zo

(b) DUAL RESISTOR -SV RAIL ONLY

Fig. 11 Terminated line parallel termination
(a) Single resistor -2V rail needed
(b) Dual resistor -5V rail only

of Rl and R2 must be equal to Zo, while the defined voltage at the input must
be the -2v used in Fig. 11a (when the driver output is 'low'). These conditions
lead to:
for Zo = 500
Rl = 810
and R2 = 1300
General results are given in Fig. 12.
When driving a large fanout, loads may be
of a parallel terminated line, although only
500.
The other major form of line termination
Reflections are eliminated at the driving end
Rs

+ Ro

=

distributed along the full length
a single line is permissible at
is the series system (Fig. 13).
of the line by making

Zo

The reflection coefficient of the load is -1.

187

360

R~ITO 5.2~~

320

/

280

I

2240

a:
Vl

w

=>

--'

a:
a

160

I-

Vl
Vl

w

a:

120

/

80

/

~

40

/

v

/

I

V

II /fl.v
J

200

V

/

1 ITO OVI

/

/

o

o

20

40

60

80

100

CHARACTERISTIC LINE IMPEDANCE

120

140

Zo (.a.)

Fig. 12 Thevenin equivalent resistors for parallel line-termination

Zo

Fig. 13 Series t€!rmination

188

i

This represents a 100% reflection at the load end of the line. As the propagated signal is of only half amplitude, the 1800 phase change at the load
interface is essential to provide the full logic swing at this point.
Typically, Ro for Eel10k devices is 70, so in 500 systems, Rs = 430. RE is
fanout dependent, and is given by
REMAX =

10Zo - Rs

n

where n = fanout.

The advantage of series termination is in simplicity, both in configuration
and power supplies. Disdavantages are that distributed loading is not permissible, although lumped loading at the line end is satisfactory.
Voltage drops across Rs limit loading to less than 10. However, multiple
Zo lines, with separate Rs resistors may be used. Overall slower propagation
delay in series terminated mode may be a disadvantage, partly overcome by
multiple transmission lines. This leads to the final line termination form,
Fig. 14.

Zo

Fig. 14500 line driver

It can be seen from Fig. 14 that the driver is doubly terminated, and resembles both series and parallel systems. At the distant (8) end of the line,
Rs = Zo
so there is no reflection.
At the driving end, Rs acts as a series damping resistor, and, although it is
not generally possible to accurately match Zo at this point, any residual
reflections on the line are further attenuated. The chief advantage of this
scheme is the ability to drive a 50 ohm line terminated directly to ground,
while using the conventional OVand -5.2V supplies. Another advantage is
the ability to drive long lines with low reflections; the disadvantage is that
the effect of Rs and Rs is to reduce the signal amplitude on the line; the device
at 8 should be some form of line receiver or comparator.
At the driving device output, the 'low' level must be pulled down to -2 volts.
Therefore
Rs
Rs

+ Rs
+ RE + Rs

2
5.2

and Rs = Zo (usually 500 for output line driving)
and RE may be set within limits, arbitrarily, to provide an adequate 'pull-down'
current.

189

Convenient practical values are

RB = 500
Rs = 270}
RE = 1300 Nearest preferred values.
Further information can be obtained from ECl data and applications handbooks.

A TYPICAL SYSTEM
Modern equipment practice is heavily weighted in favour of 500 systems,
and in key items such as coaxial cable and connectors it may not be easy to
procure a wide range of alternatives. In this environment, where board-toboard, or board-to-external facility connections are used, coaxial 500 design
is strongly advised. On an individual board, interconnection at 500 is commonly used for analogue lines, although digital signals may be conveniently
operated at higher impedances. For the ultimate in performance, however,
500 (loaded) systems are preferred.
System design demands a range of component blocks with, desirably, a
high state of integration. However, two circuit blocks currently not economically available in integrated form are the buffer amplifier and the sample-andhold. Typical applications of the buffer amplifier are high speed driving of 500
analogue lines, DAC output buffering, and sample-an{l-hold buffering. A
commercially available hybrid buffer amplifier (lH0063) has been used with
success. Discrete buffer amplifiers can be constructed, the main parameters
being slew rate and phase distortion. The ability to drive 500 lines is essential.
A sample-and-hold is needed in those video systems where the aperture
time must be short compared with the time taken for the A-D to perform the
conversion. Typical examples are systems where series-parallel type converters are used; an input analogue sample-and-hold is essential, as the
lSB's are encoded some time after the MSB's. Fully parallel analogue to
digital converters can operate without sample-and-hold; this is sometimes
known as 'sampling-on-the-fly'. In this case, the parallel converter, by virtue
of its latch action, performs an effective sample-and-hold function on the
digital output word.
One measure of a sample-and-hold 'quality' is the aperture time, which is
the uncertainty in the time at which the sample is taken. The best analogue
sample-and-holds have taperture = 20 ps rms. Digital sample and holds are
more difficult to measure, but should be approaching this figure. The aperture
time requirement of a sample-and-hold is calculated from the maximum input
slew rate and the accuracy required. If the maximum input frequency is f, and
the number of bits is n, then:taperture

1

< --1-2n+ . n.f.

In an 8-bit system, if the input bandwidth is 10 MHz, and therefore the sample
rate> 20 MHz, the required aperture time is calculated to be 62 ps or better.
Current analogue high speed sample-and-hold circuit design is discrete,
using a ring of Schottky diodes for fast switching, usually transformer driven,
The basic circuit is shown in Fig.15,A long tailed pair of very fast transistors
is driven by a narrow ECl-derived pulse.

190

HIGH SPEED ,-----~~.J"
SWITCHING
TRANSISTORS
BALANCED
INPUT PULSE

Eel lEVELS

BUFFER

AMP

Fig. 15 Sample-and-hold

Normally, the diode ring is biased 'off' but, during the pulse, a relatively large
forward current, of the order of 20-30 mA, is driven through the ring. The 'hold'
capacitor charges to the voltage present at the output of the driver stage.
After the pulse, the only discharge paths for the capacitor are the internal
leakage, the diode ring reverse leakage, and the input current of the buffer
amplifier. Low discharge rates imply low 'droop' of the signal output from the
buffer amplifier; an FET input for the buffer is usually necessary. An advantage
of this type of circuit is the full balance, which tends to cancel out feedthrough
of the sampling pulse. The limiting factors are the time taken for the input
pulse to switch the diodes, the parasitic capacitances of the diodes, and the
finite input current and bandwidth of the buffer amplifier.
Digital sample-and-hold facilities are sometimes provided in all-parallel
converters, by supplying a latch signal to all comparator stages in precise
synchronism with the input analogue voltage. This means that the propagation
delays of the lines must be accurately designed. When properly designed,
digital sample-and-hold will compare favourably in aperture time with the best
analogue circuits, and have the additional advantage of an indefinitely long
'hold' time, making them ideal for fast sample, long hold applications.

Testing the assembled system
The usual test instrument for high speed A-D systems is'the oscilloscope,
either real-time or sampling. Certainly, the oscilloscope display will illustrate
whether the device is operating, and give some idea of the accuracy, limited
to about six bits or so in dynamic range by the on-screen resolution. A fast D
to A converter can help in A-D projects by reconverting the digital output so
the difference between signals can be examined, either in the analogue mode
by D-A converting the A-D output, or digitally, by D-A converting a digital input
and reconverting in the A-D. In either case, the permiSSible error function i is
relatively easily described and is amenable to calculation.

191

The A-O and O-A test method was appl ied to a 5-bit A-O converter with the
results shown in Figs. 16 and 17. The first of these shows the digitising of a
300 kHz ramp to 5 bits resolution; there are no missing codes and no significant glitches. Sampling near the Nyquist rate is shown in Fig. 17. The technique here is to set up for a small difference frequency between the input
signal and half the clock frequency. The oscilloscope timebase is set to a
relatively low sweep rate, and the output waveform observed is the 'beat'
frequency between the input and half the clock rate. If the clock were to be
set at precisely twice the input frequency, the display would consist of only
two sample points per cycle of the input, positioned according to the phase
separation between the input and the clock. With a small difference in
frequency, successive conversions produce an output waveform in a manner
similar to a sampling oscilloscope.
No sample-and-hold was used on the A-O; the on-chip latches proved
satisfactory to a clock rate of 125 MHz.
One of the major problems in practical systems is ripples caused by
reflections. A useful tool in checking line impedances is the time domain
reflectometer; accuracies of 1 % in line impedance measurement can be made,
and line discontinuities are detected as distances in physical dimensions, so
positive location is possible. Redesign of the defective components may
significantly help the overall system performance.

Fig. 16

192

Fig. 17

3 The SP9750 comparator
GENERAL DESCRIPTION
The SP9750 is a high speed comparator tailored to the needs of the parallel!
series type of converter described in Section 1.
Its most important features are:
1. The response is faster than other commercially available comparators
2. Integrated onto the comparator chip are additional features relevant to
the construction of fast A-D converters.
The addition of the extra features on to the comparator not only reduces
the system cost and complexity but also allows higher performance systems
to be built.
Using the low gain principle already discussed, the comparator design
could follow the latest high frequency amplifier practice. Fig. 18 shows the
schematic diagram of the comparator section of the SP9750. It consists of a

TRANS(ONDUCT A NeE

TRANSRES 1ST ANCE
STAGE

STAGE

ECL
OUTPUT STAGE

Rf

INPUT
OUTPUT
VREF

LATCH INPUT

0

I

Fig. 18 Schematic diagram of the comparator section of SP9750

193

mutual conductance or "gm" stage, a trans-resistance second stage, finally
feeding an ECl logic output stage. The trans-resistance stage is a shunt
feedback amplifier in which the transfer resistance is approximately equal
to the feedback resistor value. The input impedance of this stage is low and
so the effect of shunt capacitance on this point is minimised. Output impedance is also low giving similar advantages. The resulting circuit has a
300MHz bandwidth in the sample mode and can acquire an input signal
change in 2ns. The input offset voltage is :J:5mV and the resolution is 1mV,
i.e. ±0.5mV.
In the design of very high speed converters, the propagation delays between
IC packages have a strong influence on the maximum conversion speed
attainable. By including additional system functions on the comparator chip
these are minimised, and the bonus of a lower package count and lower
power dissipation also ensues. The following four functions are available:
1. A two-input gate
2. Four emitter follower outputs from (1) for wired "OR" decoding
3. A precision current source set by an external resistor
4. A high speed precision switch for (3)

LATCH
INPUT

ANALOGUE CURRENT
OUTPUT ID

Fig. 19 SP9750 complete schematic diagram

These are shown in block form in Fig. 19. Fig. 20 shows how fifteen SP9750s
can be interconnected in a four-bit converter stage. The comparators are
connected to form a four-bit all-parallel ADC similar to Fig. 1. The two input
gates decode the comparator outputs by detecting the highest level comparator
with a logic '1' at the output. The gate at this level puts out a unique '1' to
the four emitter followers which can be wired "OR" connected to give a
four-bit binary code. Also shown in the diagram is the function of the precision
current output. These currents, which are equally weighted for all comparators, turn on when the comparator input is above the reference voltage.
Therefore by summing all of these currents, an analogue reconstruction of the
input signal to the nearest four bits below the input is obtained. Only fifteen
comparators are required to construct a 4-bit ADC and a 4-bit DAC. Such a
stage can be used as the MSB stage of a parallel/series type converter. The
temperature compensation of the current output is sufficient to allow its use
in converters of at least eight-bit accuracy. Similar stages can form the lSB
stage of a parallel/series system, only in this case the current output would
not be used.

194

ANALOGUE
INPUT

VREF

C>--..--+-----lt~-::.f---+_::::::==__

EACH BLOCI<
REPRESENTS SP9750

_ _+-+-l__+....:===-J

2
TO LOWER
LATCH INPUT
LEVELS
(ALL COMPARATORS)

2

2

2°

'---y-------/
I.

BIT WIREO 'OR'
DECODING

ANALOGUE
CURRENT
OUTPUT

Fig. 20 A 4-bit converter using SP9750 showing the top 6 levels only

The SP9750 has been optimised for use in a four by four bit parallel/series
converter system, but it is by no means limited in its application. It is not only
being designed into a variety of other systems, but also its extremely fast
response has found it a place in such areas as fast pulse detection and
instrumentation.
Circuit description
Fig. 21 shows the complete circuit diagram of the SP9750. The inputs are
buffered with emitter followers to avoid the switching effect of input currents
which would exist with a direct connection to the long-tailed pair first stage,
The diodes in the collectors of the first stage are for DC level shifting. The
DC conditions are arranged so that for a perfectly matched circuit with the
inputs shorted together, there is zero voltage across the feedback resistors (Rf).
The output from the second stage which is a swing of about 400mV is fed
into the current switch via an attenuator. This direct route to the current switch
gives the fastest possible D to A function. The attenuator avoids using excessive drive to the switch which would increase the settling time of the analogue
current output. The analogue current source transistor uses a novel connection of transistors which minimises the effect of temperature and Hfe etc,
on the output current stability.

195

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The ECl output stage is conventional but an unusual circuit is used to
provide the coror::arator output gating. The Boolean function required is:
gate output = AB, which might be described as a partial exclusive 'OR'
function. It is achieved by level shifting the B input by one half of an ECl
output voltage swing, and feeding this into a single ECl gate structure. This
circuit uses minimal chip area. Four emitter follower outputs from the gate
are provided which can be wire OR-ed as previously described.
Conversion rate/Hardware tradeoffs
An 'n' bit converter can be arranged in a number of ways using parallel
and series parallel techniques. For example, three stages could be used,
each resolving some of the bits.
i.e. a + b + c = n
In an 'a' bits conversion, the number of comparators needed is (2 a - 1).
Thus the total number of comparators is:(2 a -1) + (2 b -1)., (2 C -1)
In some circumstances, under and over-ranging may be needed, which will
require two extra comparators.
Typical examples are the 4 x 4, two stage converter for eight bits, where:a+b=n

4 +4 =8
Number of comparators = 24 + 24 - 2 = 30
When stages are cascaded in this way, the interstage delay must be taken
into account. Of pri mary interest is the 0/ A current output settl ing to the desired
accuracy.
Each SP9750 contributes one fifteenth of the full scale current, and only
one or two comparators are likely to be in a critical settling condition when the
latch closes. Therefore if settling to ~ lSB is required (0.2%) two comparators
need to settle to 3% or 1.5% for individual comparators. This takes place in
less than 10ns. Allowing 10ns for the interstage difference amplifier to settle
and a further 10ns for the sample and hold function and logic timing errors, the
total conversion period is 30ns or a sampling rate of 33MHz. The corresponding figure for 3 stage is 20-25MHz.
Improved circuit design techniques would increase these figures. For
instance, analogue delay could be used between stages to equalise the
settling delay of the O/A current output. Perfect cancellation would reduce the
conversion period by 10ns bringing the sampling rate to 50MHz. Another
technique which has been used is additional comparators in the second or
subsequent stage to correct errors from the first stage brought about by
latching the first stage before the sample and hold has fully settled. The
improved performance offered by such circuit innovations is traded against
increased circuit complexity and hence cost.

o TO

A CONVERTER USING THE SP9750

When used as originally intended, in a 4 x 4 parallel-series AOC, the output
currents from the first four bits of conversion are summed to produce the
interstage digital-to-analog function. It is this O-A facility which is used here,
but with a binary weighting for the output currents instead of the equal
weighting of the A-O system.

197

A total of 'n' devices only are needed for the 'n' bit conversion, unless the
MSB current needed is more than 10mA. If, say, 20mA MSB current is needed,
two devices will run in parallel, as in the scheme to be described, giving a
total of 'n + l' devices. The D-A system block diagram is Fig. 22.
VREF - LOGIC MIOPOINT

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Fig. 22 8-bit DAC using SP9750s

198

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In the D-A application, the 'analog' inputs are switched by logic signals
from the 'n' bits of incoming data, giving a marginal improvement in the
operating speed compared with normal analog operation. The ancillary
facilities (00 - 04 outputs) which are used in the ADC encoding matrix are not
used in the DAC. The SP9750 incorporates a latch, as is becoming standard
in high speed comparators, and this feature is exploited here to provide a fast
digital sample-and-hold. The current output settling time (10ns to 0.2% for the
SP9750) is the main limiting factor in this type of DAC; eight-bit accuracy
should be available in about 10-15ns from the input command.
The comparator has a maximum input current of 251lA, which allows it to be
set up to receive logic input swings (ECl or TTL) by connecting the reference
input to the appropriate Voltage. The ECl input to the latch stage is made low
for follow or high for hold.
The output current is set by an external resistor and the -8 volt rail, which
should be stable enough for the accuracy needed. The maximum output
currsnt from a single device should not be much more than 10mA; the relationship of output current to negative reference rail is nominally
Vrail
lout=--

2 x Rex!

In practice, deviations from this rule are found at low output currents, due
to on-Chip bias conditions, and a table has been drawn up (Table 2) which
illustrates the values of Rex! for given output currents.
Output current
(rnA)
(rnA)
10
5
2.5
1.25
0.625
0.312
0.156

Tail resistor (Rext)
Variable
Fixed
(0)
(0)
100
330
680
220
1.5k
470
3k
1k
7.5k
2.2k
22k
10k
180k
100k
Table 2

System Aspects
The most used type of high-speed DAC is probably the eight-bit system, so
the description here is for eight bits, with an MSB of 20mA, which requires
two SP9750s in parallel. No problems are encountered in parallel device
operation. The total of nine comparators are laid out in a U-shaped configuration on -to" PCB with a top surface ground plane. The design value for the
transmission line signal paths is 500, enabling the DAC to directly drive
500 systems, or the 500 input of a fast real time or sampling scope. The
option of terminating the board end of the transmission line or leaving it
open is available. The latter case provides a full-scale swing of 2 volts (40mA
into 500) while termination of the line on the PCB halves the output voltage
swing by giving an effective 250 load, but gives better settling time by reducing reflections on the summing line.

199

The device input capacitance is small, and 500 nominal lines are used
with 500 terminations. The two MSB devices are fed through 1000 lines with
1000 terminations in parallel. Drive from ECl matched to 500 by terminating
networks optimises the switching speed, although TTL-level (lS or S) is also
possible by resetting the Viel inputs rail to a mid-level point.
On the output current summing line, the typical output capacitance per
device is 2pF. The line is fed from both sides, so an unloaded line impedance
of 1100 is predicted for the 500 loaded condition. All input lines are made of
equal lengths, although some advantage may be gained by equalising the
input .to output delays; in either case, the MSB should be located furthest
from the output connector and as close as possible to the end termination of
the line.
Testing the DAC
Each comparator is configured as in Fig. 23 and the potentiometers have
to be 'set up' to provide eight-bit accuracy. There are two ways to do this:
either DC, using a DVM and setting each current independently of the others
or dynamically, driving the inputs with a digital code. The dynamic method
provides 'hands-on' practical feel for the DAC operation at high speed, and
is recommended if a fast real time scope is available. A simple drive circuit
uses two ECl10k Hexadecimal counters (MC10136s) in synchronous count
mode, overflowing at the 256 count. For the eight-bit converter, this gives a

INPUT

>---;

PRECISION
SWITCHED
CURRENT
CURRENT ~-- SUMMING
SOURCE
LINE

MID POINT OF
LOGIC FAMILY USED
eg EC L OR TTL

VALUES FROM
TABLE 1

LATCH INPUT (ECLI

-8V

Fig. 23 Comparator configuration

full-scale ramp output, which is easily trimmed for linearity. The system
diagram is shown in Fig. 24. Nominal MSB is 20mA, bit 7 is 10mA and so on
down. A small overall scaling error can be trimmed out using the -8 volt
rail. Independent setting of the current sources instead of the conventional
R-2R ladder improves speed performance and prevents interaction between
sources.

200

FAST SCOPE OR SAMPLER

RAMP OUTPUT
LINEARITY DEPENDS ON
ACCURACY OF CURRENT
SOURCE SETTING

=::;;:==t--::-:-~

r;:::=D=A=C=B=oA::;R;:D

501\ LINE

OUT

B DRIVE LINES

CLOCK
>IOOMHz

1+--1---50A TERMINATED LINES

ECL 10k DRIVER
2X HEXADECIMAL
COUNTERS (MC 101361

Fig. 24 Setting up the DAC

Fig. 25 shows the full-scale ramp maintaining linearity at more than 50MHz
input to the lSB. The full-scale transition (Fig. 26) at the end of the ramp,
takes less than 15ns, dominated of course by the MSB transition, shown
clocked at about 14MHz in Fig. 27.
The limiting factor in the DAC testing is the ECl10k drivers; output glitches
are seen at the MSB transition (0111 1111 to 1000 0000) and at the lower
counter fUll transition (0000 1111 to 0001 0000); these are attributed to timing
errors caused by internal 'counter full' to 'carry out' delay. The manufacturer's
figures put this at 5ns, although the glitches seen are shorter, about 3ns
overall. The minimum clock period accepted by the counters is 9ns so the
DAC lSB state changes occur at this interval, comparable to the lout settling
time of the SP9750 (typically 10ns to 0.2%) indicating a maximum data rate
of more than 50MHz.

201

Fig. 25

Fig. 26

202

Fig. 27

4 The SP9685 comparator
GENERAL DESCRIPTION
The SP9685 is a high speed latched comparator, the circuit diagram for
which is shown in Fig. 28. The unlatched gain is approximately SOdB at
frequencies up to over 200M Hz. The main differences between the SP9685
and the SP9750 are as follows:1. The SP9685 is a simple comparator and does not include the gates and
precision current sources of the SP9750.
2. The unlatched gain of the SP9685 is greater than that of the SP9750.
3. The latch enable control of the SP9685 has the opposite phase of operation
to that of the SP9750 latch control.
4. Two gain stages follow the latch of the SP9685 whereas only one is used
on the SP9750.
5. Q and Q outputs are provided on the SP9685.
Short pulse detector
This simple circuit for the SP9685 has applications in nucleonics and high
energy physics. In its simplest form, the circuit is shown in Fig. 29.
A positive going pulse of any width, down to the minimum defined by the
propagation delay plus the setup time, and of any height between the maximum common mode signal and the minimum overdrive that will reliably
switch the comparator can be quickly detected and will cause the circuit to

203

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204

latch, ignoring further inputs. Practical minimum values are a 3ns pulse
width and a 10mV amplitude for reliable latching. The input biasing should
be set for a mid input range threshold. Alternative forms of the same basic
circuit could be used to detect negative going pulses, by feeding Q back to
the latch, or detect pulses greater than a preset height, by shifting the
threshold bias point.
Resetting the simple circuit can only be achieved by removing the power
supplies. It is possible to produce an external resettable latch using ECLlII
which will not degrade the performance if powering down is not an acceptable
method.

2B
~~=~-+--_-L==r--i©50.n LOAD

150
' - - -........- - - 5'2V

10 k

-5'2V

Fig. 29 Short pulse detector

An Eel two-phase clock oscillator
This simple oscillator circuit is capable of relatively high stability and wide
frequency range (up to 200MHz). The maximum frequency limit is determined
by the device propagation delay (typically 2ns) and the external strays. At low
frequencies (below 5MHz) operation is possible, but high frequency instability
on the clock edges may be seen. In practice, this is unlikely to be a restriction
on the use of the device. An empirical relationship between Rand C values
and frequency is shown in Table 3. In the circuit shown (Fig. 30) output
matching networks are included so that the device can drive 500hm lines
terminated to ground. Where higher impedance lines or short runs are used
the output networks may be omitted. However, because the device edge
speeds are comparable with ECLlII, good ECl practice in line matching and
termination, preferably with a ground plane structure, should be employed
as described in Section 3. The input bias conditions are determined by the
output potentiometer Rl :R2. It can be shown that a ratio of 3.6:1 will give a
minimum of HF instability when operating at low frequency.

205

C, pf

Fosc(R3 = 1KO)MHz
161
64
59
54
46
42
38
33
30
28

0
2.2
2.7
3.3
3.9
4.7
5.6
6.8
8.2
10

Fosc(R3 = 3300)MHz
190
160
156
152
140
132
120
103
88

77

Table 3

One side of the capacitor Cl is grounded, and all or part of the effective
capacitance can be made voltage variable, producing a high frequency
voltage controlled oscillator with direct ECl drive. Spectral analysis indicates
that the noise sidebands from this type of oscillator are 40dB down at 50kHz
away from the carrier.
OPTIONAL
VOLTAGE
(ONTROL

OV

so

100k

~+-----4....r-l-.---.......---r-t---C OUT

OV

so

Fig. 30 EeL clock oscillator

OV

A HIGH SPEED WINDOW DETECTOR

The SP9685 can be used to detect whether an input is within a specified
voltage range. The basic circuit is well known and is shown in Fig. 31 in a
form to give ECl levels. The output drives a 500 load to ground or, without
the 270 series resistor, further ECl stages.
Fig. 32 illustrates the operation of the circuit which has been set up to detect
a window of ±20mV about 0 volts. As the input voltage crosses zero the
output changes from high to low and back again in a time mainly determined
by the ECl rise and fall times. This circuit is thus detecting the crossing of the
40mV window by a signal slewing at 50V/Il sec.
Applications of the high speed window detector are in fast tracking A-O
converters and high speed zero crossing detectors. The operational limit is
the device propagation delay (typically 2ns) which defines the minimum
width of the threshold crossing pulse.

206

t20mV 0 - - - - - - 1

27
INPUT

±50mV @~--.--....
OR MORE

- 20m V 0-------1
150

150

150

Fig. 31 High speed window detector

5ns/division
50mV
Idivision
INPUT

+50mV

-50mV
200mV
/division
OUTPUT

ECl HIGH

ECl lOW

Fig. 32 Performance of high speed window detector

207

208

TECHNICAL
DATA

209

210

SL301 K&L

OPLESSEY

SL300 SERIES

SEMICONDUCTORS

MATCHED TRANSISTORS

SL301K

SL301L

DUAL NPN TRANSISTORS
The SL301 K and SL301 L are dual NPN transistors
manufactured as monolithic integrated circuits. Their
close parameter matching and thermal tracking are
considerably better than conventional 'two chip' duals;
the frequency response is equally superior.
The SL301 K and L have identical electrical'specifications but differ in packaging. The SL301 is pin compatible with existing SL300 series products and available
in both metal can (CM) and ceramic dual-in-line (OG)
packages. The SL301 K is available only in metal can
(CM) and is pinned to be compatible with conventional
discrete 'two chip' products. Note, however, that an
extra connection is required to allow the substrate to be
connected to the most negative part of the circuit.

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(eM8)

eM8

[3] -8 LEAD TO-5 (SL301 K ONLY) {eMS)

DG14
Fig. 1 SL301 circuit diagram

ORDERING CODES:
SL301 K - CM
SL301 L - CM
SL301 L - OG

QUICK REFERENCE DATA
•
•

Max voltage
12Vto 20V
Operating temperature range - 55°C to
+175°C

VOLTAGE RATING
The maximum voltage allowed between collector and
emitter of each transistor is limited by dissipation and
voltage breakdown. Assuming dissipation is low the
rating may be determined from the following details:
(a) Forward bias condition
If the transistor is conducting the maximum collectoremitter voltage allowable is at least equal to VCEO
(12V). In cases where the collector current does not
exceed 5mA and a resistor R is connected between base
and emitter the VCER rating may be determined from
Fig. 8; this voltage lies between 12V and 20V depending
on the value of R.
(b) Unbiased condition
If the transistor is operated with no connection to the
base the maximum safe collector-emitter voltage is
VCEO (12V). In cases where the base emitter voltage
has been reduced so the transistor is conducting at a low
level it is generally permissi ble to increase this towards
VCBO (20V).
(c) Reverse biased condition
If the base of the transistor is connected via the resistor to a supply voltage equal to, or more negative
than, the emitter voltage the maximum collector-emitter
voltage VCEX allowable (assuming negligible collector
current) is limited by VCBO (20V). For example, if the
base is at -5V with respect to the emitter, the maximum
collector voltage will be + 15V.

FEATURES
•
•
•
•

Close VSE Matching
High Gain
Good Frequency Response
Excellent Thermal Tracking

APPLICATIONS
•
•
•

Differential Amplifier
Comparator
Stable Current Source

ABSOLUTE MAXIMUM RATINGS
All electrical ratings apply to individual transistors:
thermal ratings apply to total package dissipation.
The isolation pin must always be negative with respect
to the collectors.
No one transistor may dissipate more than 75% of the
total power.
-55'C to + 175'C
Storage temperature
Chip operating temperature + 175°C
Chip-to-ambient thermal resistance:
TO-5 (CM)
250°CjW
Ceramic OIL
106°CjW
Chip-to-case thermal resistance:
TO-5 (CM)
80'C/W
Ceramic OIL (OG)
39'CjW
VCBO
20V
VCEO
12V
VCER
12V to 20V (see graph)
VEBO
5V
VCIO
25V
ICM
50mA

211

SL301K&L

ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise stated):
Tamb ~ +25°C

Value

Characteristics
Min.

Typ.

Conditions

Units
Max.

Each Transistor
20
12
5
25
30
40
60
50

BVCBO
BVCEO
BVEBO
BVclo
hFE

VeE (SAtl
VBE (SAT)
ICBo
lEBO
IClo
COB
C,B
CCI

0.7

MHz

Ic ~ 1 0 ~A
Ic ~ 5mA
IE ~ 10 ~A
Ic ~ 10 ~A
VCE ~ 5V, Ic ~ 1 0 ~A
VCE ~ 5V, Ic ~ 100 ~A
VCE ~ 5V, Ic ~ 1mA
VCE ~ 5V, Ic ~ 10mA
Ic ~ 10mA, IB ~ 1mA
Ic ~ 10mA, IB ~ 1mA
VCB ~ 10V
VEB ~ 2V
VCI ~ 10V
VCB ~ 5V
VBE ~ Ov
VCI ~ 5V
VCE ~ 5V, Ic ~ 5mA

1.1
1.1
3
3

mV
mV

VCE
VCE
VCE
VCE

10

~V/oC

VCE

V
V
V
V
50
70
100
80
0.36
0.8

0.6
0.9
10
10
10

V
V
nA
nA
nA
pF
pF
pF

2
4
6

h

400

680

Matching
0.9
0.9

hFEI/ hFE2
~ VBE
a~VBE

a Tomb

,

0 \
1
1,'

100 0

•

\

\\
\

"
'r----

T= ..

c',~"

z

0

~

"'+'"'

~

~

"

:::- -

,
vOLTAGE (V)

Fig. 2 Output capacitance (Cob) v. voltage

40 0

-20

~

100 ~A
1mA
100 ~A
1mA

~

100

~

~A

i

i
I

\

\

L';B'~'H RATI""""" "",\
i

'0 0

o

5V, Ic

~
~

CASE RATING

ReG'"

I~

~
~

10

212

60 0

~

~

Ic
Ic
Ic
Ic

1\

80 0

E-

,oo·c

~

5V,
5V,
5V,
5V,

1\

1200

'\

~
~

'l~

0

+20

60

100

140

180

220

TEMPERATURE (·C)

Fig. 3 Power dissipation derating curves (TO-5 package)

SL301K&L
0

80 0

- i'-.,

/"

0

V.

70 0

tlhV ..- f-...

60 0

V
v

~ ~~ r-..

50 0

JV

0

0/

~~

300

""""

!'ov

'tIce!sv

IIcel,zv

\

\."!,,

20 0

0
10 0

0

0

0710,

03

10}JA

100jJA
CURRENT

10mA

1mA

7

Fig. 4 Typical variation of hFE with collector current

Fig.

5', v.

col/ector current (', ~

A

,JA "7mVl"C

i'"'--,

i""-.00

~ I'- .......

O'lrnAl'87rri1!-C

r-......

r--

f100 A

.........

i""--

'"

"",

r--....

!

I

lOOn A

......... i""-- r-.....

70

2030

'lh,.1 . , ~

A
VC[=2OV

\/C\,5\/

i'"'--,

100 MHz)

/. ?:::

I
I

VCEisV

.........

10

CURRENT (rnA)

l00mA

!

~ y--

~~

-t a ~
/:
~~
//

I

~

I
r--

\lCI='V

lOOp A

30'

..

2'"-

o

+20

+40

+60

+10

+100

+120

+140

lOp A 0

-+160

20

40

Fig. 6 VBE

V.

80

100

120

140

160

Fig. 7 Typical/clo v. temperature

temperature

0

60

TEMPERATURE ("CI

TEMPERATURE (eel

--

r---

I----

•

-I---i

•w.

10k
R (OHMS)

Fig. 8 Relationship between VeER and RSE

213

214

SL303L

o PLESSEY

SL300 SERIES

SEMICONDUCTORS

MATCHED TRANSISTORS

SL303L
TRIPLE NPN TRANSISTORS
The SL303 is a silicon monolithic integrated circuit
comprising three separate transistors, two of which have
closely matched parameters; the third transistor may be
used as, for example, a tail transistor. The SL303
devices are available in 10-lead TO-5 (CM) and 14lead dual-in-line (OG) packages.

----09171

ORDERING CODES:
(1315

~

611ll

TR3

4

SL303L -

CM

SL303L -

OG

[141

DG14 CM10
Fig. 1 Circuit diagram

FEATURES
•
•
•
•

Close VBE Matching
High Gain
Good Frequency Response
Excellent Thermal Tracking

VOLTAGE RATING
The maximum voltage allowed between collector and
emitter of each transistor is limited by dissipation and
voltage breakdown. Assuming dissipation is low the
rating may be determined from the following details;
(a) Forward bias condition
If the transistor is conducting the maximum collectoremitter voltage allowable is at least equal to VCEO
(12V). In cases where the collector curredt does not
exceed 5mA and a resistor R is connected between base
and emitter the VCER rating may be determined from
Fig. 8; this voltage lies between 12V and 20V depending
on the "Iue of R.
(b) Unbiased condition
If the transistor is operated with no connection to the
base the maximum safe collector-emitter voltage is
VCEO (12V). In cases where the base emitter voltage
has been reduced so the transistor is conducting at a low
level it is generally permissi ble to increase this towards
VCBO (20V).
(c) Reverse biased condition
If the base of the transistor is connected via the resistor to a supply voltage equal to, or more negative
than, the emitter voltage the maximum collector-emitter
voltage VCEX allowable (assuming negligible collector
current) is limited by VCBO (20V). For example, if the
base is at -5V with respect to the emitter, the maximum
collector voltage will be ,15V.

APPLICATIONS
•
•

Differential Amplifier
Comparator

QUICK REFERENCE DATA
•
•

Max voltage
12V to 20V
Operating temperature range - 55°C to
+175°C

ABSOLUTE MAXIMUM RATINGS
All electrical ratings apply to indIvidual transistors
thermal ratings apply to total package dissipation.
The isolation pin must always be negative with respec'
to the collectors.
No one transistor may dissipate more than 75% of thE
total power.
Storage temperature
-55'C to + 175'C
Chip operating temperature + 175'C
Chip-to-ambient thermal resistance:
TO-5 (CM)
250'C/W
Ceramic OIL
106'C/W
Chip-to-case thermal resistance:
TO-5 (CM)
80'C/W
Ceramic OIL (OG)
39'C/W
VCBO
20V
VCEO
12V
VCER
12V to 20V (see graph)
VEBO
5V
VCIO
25V
ICM
50mA

215

SL303L

ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise stated):
Tomb ~ +25 oC

Value

Characteristics
Min.

Typ.

Conditions

Units
Max.

Each Transistor
20
12
5
25
30
40
60
50

BVCBO
BVCEO
BVEBO
BVclo
hFE

VCE (SAT)
VBE (SAT)
leBO
lEBO
IeIO
COB
C'B
CCI

0.7

400

fr

pF
pF
pF
MHz

Ic ~ 10 ~A
Ic ~ 5mA
IE ~ 10 ~A
Ic ~ 10 ~A
VCE ~ 5V, Ic ~ 1 0 ~A
VCE ~ 5V, Ic ~ 100 ~A
VCE ~ 5V, Ic ~ 1mA
VCE ~ 5V, Ic ~ 10mA
Ic ~ 10mA, Is ~ 1mA
Ic ~ 10mA, IB ~ 1mA
VCB ~ 10V
VES ~ 2V
VCI ~ 10V
Vcs ~ 5V
VB' ~ Ov
VCI ~ 5V
VCE ~ 5V, Ie ~ 5mA

1.1
1.1
3
3

mV
mV

VCE ~ 5V,
VCE ~ 5V,
VeE ~ 5V,
VCE ~ 5V,

10

~V/oC

VCE

V
V
V
V
50
70
100
80
0.36
0.8

V
V
nA
nA
nA

0.6
0.9
10
10
10
2
4
6

680

Matching(TR1, TR2 only.
0.9
0.9

hFEI/hFE2

tl. VBE

~~VBE
amb

4

120 a

'\
\
\\

:\

2·

\
4

2-

o

~

."'- "-....
,~

-............: t:-

Fig. 2 Output capacitance (Cob> v. voltage

0

~

60 a

)-

:;i
0

40 a

AMBI~I

\

100

~A

CAS; RATING

\

"-

RAII.V,""'-

",,\

20 a

a-20

~

\
op";,,,o ',",0'

z

1:+IOO·C

5V, Ic

i

80 a

i

2
VOLTAGE (V)

216

\

100a

~

Ic ~ 100 ~A
Ic ~ 1mA
Ic ~ 100 ~A
Ic ~ 1mA

"0

+20

60

100

~

140

!So

220

) TEMPERATURE ("C)

Fig. 3 Power dissipation derating curves (TO-5 package)

SL303L
80

800

10 0

i--

i'-.

/'

60

°v

II

/-

60 0

/

r-

V

V,.,,!,ov

'"

j .?~ r-... ""1\
IA ~

50 0

0

~~

300

I

IIce: 5Y

I

II CE :2V

\

I
IICE·IV

20 0

0
10 0

I
0·7

,.A
0

10pA

100J,lA
CURRENT

lOrnA

1mA

10

7

10

20

10

30

CURRENT (rnA)

loomA

Fig. 5 fT

Fig. 4 Typical variation of hFE with collector current

...
...

v. col/.c/or curr.n/ (fT = flh,.1 . f

=

100 MHz)

,

'.A
.........

!

w

:

r---. i'r--...

...

i"'-

/.~

I

Vc~iSY

.........

~ ;;Y

100nA

IJ"t''''YI-c

~

o-lrnA '·I7M/....e

.........

.......

sao

......

.......

.........

.........

.......

.,.

~

lanA

.P

r-.....

'oA

I

I

/. ~

VCl ·2OY
II C1 =5V

r.......

/ / '/
{/

V

ef

.;; ~

7/

1Y

IOOpA

.OG

2,.

-10

-40

20

0

20

+20+",+10+10+1110+110+1'11+110

100

60

100

120

"0

160

Fig. 7 Typicallclo v. temperature

Fig. 6 VBE v. temp.tII/ure

-- ----

20

&0

TEMPERATURE I-C)

TEWERATlIf':! I"CI

-....

o
lOG

..

..........

r--- -

10k

R (OHMSI

217

218

SL355C SL1796C

ePLESSEY
SEMICONDUCTORS

MODULATOR
DEMODULATOR

SL355C TBA673C
4-TRANSISTOR MODUlATOR/DEMODUlATOR

The TBA673 and SL355 are monolithic integrated
4-transistor modulator/demodulator circuits. Featuring
close similarity in the characteristics of the individual
transistors and optimal tracking of parameters with
temperature, these devices give better balancing (and
therefore less carrier leakage) than discrete circuits. The use
of transistors instead of the more conventional diodes
results in an improved isolation between input and output

circuits.
The choice between TBA673 and SL355 will depend
largely on the application. For example, the TBA673 has
higher voltage characteristics than the SL355, but the
SL355 would be used where high frequency performance is
the prime consideration.

APPLICATIONS

FEATURES
•
•
•

CM10
Fig. 1 Circuit diagram

D.VsE=±5mVMax.
Close hF E Matching
High fT : 250 MHz (TBA673)
600 MHz (SL355)

•
•
•
•
•
•

DSB/DSBSC/AM Modulation
Synchronous Detection
FM Detection
Choppers
Signal Routeing
Telephone Transmission (TBA673)

ABSOLUTE MAXIMUM RATINGS
Electrical (Each Transistor)
Rating
Collector-emitter voltage
Collector base voltage
Emitter-base voltage
Collector-isolation voltage
Collector current

Symbol

VCEO
VCBO
VEBO
VCI
Ic

TBA673

SL355

Units

45
80
7.2
80
100

12
20
5
25
20

V

V
V
V
mA

Power
Total power dissipation: See Fig. 3
Temperature
Storage temperature, Tstg : _35° to +125°C
Operating temperature, Tomb: See Fig. 3 •
NOTE

The substrate pin must be more negative than each of the collectors.

219

Sl355C TBA673C

ELECTRICAL CHARACTERISTICS - TBA673
Test conditions (unless otherwise stated):
Tamb = +25°C
Characteristics apply to each transistor
Value
Characteristic

Symbol

Units

Condition

Min. Typ. Max.
Each transistor
Collector-base breakdown voltage
Collector-emitter sustaining voltage

Emitter-base breakdown voltage
Collector-isolation breakdown voltage
Collector-base leakage current
Emitter-base leakage current
Collector-isolation leakage current
Large signal current transfer/ratio
Transition frequency
Collector-isolation capacitance

80
45
7.2
80

BVCBO
LVCEO
BVEBO
BVCIO
ICBO
lEBO
ICIO
hFE
fT
CCI

8.0
10
1
3
300

80
250

V
V
V
V
nA
nA
nA

6.5

MHz
pF

5.0
5.0

mV
mV

Ic = 1DIlA, IE = 0
Ic = 5mA, IB = 0
IE = 10llA,Ic =0
Ic = 10llA
VCB = 10V,IE =0
VEB = 2V, Ic = 0
VCI = 10V
Ic = 5mA, VCE = 5.0V
Ic = 5mA, VCE = 5.0V
Vcs =OV

Matching characteristics
Base-emitter voltage difference

TR1-TR2
TR3-TR4

2_0
2_0

VBE1- V BE2
VBE3 -VBE4

V CE (all transistors) = 5.0V

Large signal current ratio matching

TR1/TR2
TR3/TR4

hFE1/hFE2
hF E3/hF E4

0.9
0.9

IE (all transistors) = 100llA

1--1---

"'1,\

0

'00

~

o

-2S
T amb I"CI

Fig. 2

220

Power dissipation

TBA673C SL355C

ELECTRICAL CHARACTERISTICS - SL355
Test conditions {unless otherwise statedl:
Tomb ~ +25°C
Characteristics apply to each transistor
Value

Characteristic

Uniu

Symbol

Condition

Min. Typ. Max.
Each transistor
Collector·base breakdown voltage
Collector·emitter sustaining voltage
Emitter·base breakdown voltage
Collector·isolation breakdown voltage
Collector· base leakage current
Emitter·base leakage current
Collector·isolation leakage current
Large signal current transfer ratio
Transition frequency
Collector·isolation capacitance

BVCBO
LVCEO
BVEBO
BVCIO
ICBO
lEBO
ICIO
hFE
fT
CCI

25
12
5
25

10

1
10
10

V
V
V
V
nA
nA
nA

6.5

MHz
pF

5.0
5.0

mV
mV

18

0.3
1
1
55
600

Ic~ 10/LA,IE ~O
Ic = 5mA, IB = 0
IE = 10/LA,lc ~O
Ic = 10/LA
VCB = 10V, IE = 0
VEs=2V,lc=0
VCI ~ 10V
Ic = 100/LA, VCE ~ 5.0V
Ic = 5mA, VCE ~ 5.0V
Vcs =OV

Matching characteristics

Base-emitter voltage difference
TR1-TR2
TR3-TR4
Large signal current ratio matching
TR1/TR2
TR3/TR4

2.0
2.0

VBE1- V BE2
VBE3- V BE4
hFE1/hFE2
hFE3/hFE4

0.9
0.9

VCE {all transistorsl ~ 5.0V
IE (all transistors) = 1001LA

221

222

Sl360C

•

Plessey
Semiconductors

SL300 SERIES
MATCHED TRANSISTORS

SL360C
2· 5GHz MATCHED TRANSISTOR PAIR

eMS

NC
BOTTOM 'VIEW

The SL360C is a bipolar monolithic chip comprising a pair of integrated circuit transistors designed for
applications where close parameter matching and thermal tracking are of prime importance. They have a
very high ft (typically 2.5 GHz) and low capacitances.

ELECTRICAL CHARACTERISTlCS@Tamb = +25°C
Value

Characteristic

BVCBO
BVCEO
lVCEO
BVCIO
BVEBO
h FE
IT
VBE 1 - VBE2 (note 11
hFE1/hFE2 (note 11
VCE (Sat)
Cob (note 2)
CTE (note 2)
CCI (note 3)
Vbe (on)
ICBO
ICIO
lEBO

Conditions

Min.

Typ.

15

32
15
14
60

8
8
30

Max.

V
V
V
V
V

4.8
30
1.6

65
2.5
3.2
3
1.1
0.25
0.7
1.5
2.7
720

Units

GHz
GHz
10

mV

0.4

V
pF
pF
pF
mV
nA
nA
nA

1
1
1

IC

~

1O!1A
10!1A
IC ~ 5mA
IC~ 10!1A
IE ~ 10!1A
VCE ~ 2V.IE ~ 5mA
VCE ~ 2.5V.IE ~ 5mA, I
VCE ~ 5V,IE ~ 25mA
VCE ~ 2V,IE ~ 1mA
VCE ~ 2V,IE ~ 5mA
IE ~ 10mA, Ib ~ 1mA
VCB= OV
VBE=OV
VCI ~ OV
IE ~ 1mA, VCE ~ 2V
VCB ~ 10V
VCE ~ 10V
VEB ~ 2V
IC~

~

200M Hz

NOTES
1.
2.

It is assumed here that device suffixed 1 has the greater numerical value.
These capacitances include stray header capacitance which is about 0.1 pF.

3.

These capacitances include stray header capacitance which is about 0.9pF.

223

SL360C

ABSOLUTE MAXIMUM RATINGS (Note 4)
Storage temperature
Operating junction temperature

-55°C to +175°C
+175°C max.

Maximum Dissipation (Note 5)
Dissipation at 25°C free air temperature
Dissipation at 100°C free air temperature

'tjOOmW
300mW

Maximum Voltages
BVCBO: 15V
BVCEO: BV
BVEBO: 4.BV
BVCIO : 30V (note 6)
4
5.
6.

224

The maximum ratings are limiting absolute values above which life or satisfactory performance may be impaired.
These ratings give a junCtion temperature of 175° with a junction·to·ambient thermal resistance of 250°C/W (deratine
factor 4 mWfC.)
The isolation pin should be negative with respect to the collectors.

SL362C

•

Plessey
Semiconductors

SL300 SERIES
MATCHED TRANSISTORS

SL 362C LOW NOISE TRANSISTOR PAIR
eMU
Fig. 1 Pin connections

The SL362C is a bipolar monolithic integrated circuit comprising a pair of transistors designed for
applications where low noise and very high frequency operation are of prime importance. A typical noise
figure at 60MHz is less than 1.6dB.
ELECTRICAL CHARACTERISTICS @ Tamb = 25°C
Value
Characteristic

Min.

Typ.

12

24
15
40

BVCBO
BVCEO
BVclO
BVEBO
hF E

8
20
5
30

70
60
1.6
2.2
5
1.6
1.0
0.9
15.0

1
1.4

fT
VBE1 - VBE2
Noise figure (note 1)
COB
CCI
CTE

Max.

Units

Conditions

V
V
V
V

2.0

IE = lOIlA
IC = lOIlA
Ic = 1Oil A
IC = 10llA
IE = lmA, VCE = 2V
IE = 10mA, VCE = 2V
IE = 2mA, VCE = 2V
IE = 10mA, VCE = 10V
IE = lmA, VCE = 2V
IE = lmA, Rs =20012 f = 60MHz
V=O
V=O
V=O

GHz
GHz
mV
dB

pF
pF
pF

Note 1, The noise figures are quoted at 60MHz. Typically, they are constant from 10kHz to 200MHz.

I
t~50~Hl

l

COLLECTOR

COLLECTOR

*L,

:f'--...
so
l

i'--..I

/
...............

"COB

f-""'"'

,
fMITTER

ISOLAT ION

EMITTER

,;;;--,OC;--

-----

V-

I

V
~

;--

V

l

Fig. 2 Equivalent circuit
Fig.3 Tvpical noise figure v. emitter current

225

SLJ62C

-:::---

'8'

..-

"

r-- '"

if
c

I
o

I
IE ImAI

Fig.4 Tvpical fT v. emitter current

~I~

,

~
I

Storage Temperature
Operating Junction temperature

I

i \

!

ABSOLUTE MAXIMUM RATINGS

,J",

'"

~V

k;::::
i ' -~

Total Dissipation

V

/'

/'

Fig. 5 Tvpical noise figure v. source impedance

226

-55°C to +150°C
150°C
300mW
50mA

Collector current
BVCBO
12V
BV CEO
8V
BVEBO
5V
BV clO
20V
Note: The isolation pin should be negative with respect to
the collectors.

SL362C
SIMPLE FEEDBACK AMPLIFIER (FIG.6)

The frequency response of the amplifier shown in
Fig.7 is flat to within ± 1 dB from DC to 240 MHz. The
small peak at 200 MHz is not layout dependent but is due
to parasitic lead inductance in the transistor packages.

The ampl ifier has a response down to DC achieved by
the use of a long-tailed pair in the input stage. which also

Measurements were made with a

gives low offset voltages and a convenient method of

50n source impedance

and a load of 0.1 Mn + 2.S pF. The amplifier will drive a
load up to lS0 MHz if required. For simplicity the
noise figure was measured with a
source impedance
and a spot noise figure of 4.2 dB was measured at
frequencies of 30 to 200 MHz. The calculated variation of
noise figure with source impedance is shown in Fig.B. which
indicates an optimum noise figure of 2.5 dB at 200n source
impedance.

applying negative feedback. The input is applied to Tr 1
and negative feedback applied to Tr 2 via resistors R 6 and
R 7. Tr 3 is current-driven from the long-tailed pair and
gives the output voltage across R 3. It is important to keep

son

the stray capacitance from R 3 to ground as small as
possible for the best high frequency performance. By the
use of the very high fT transistor pair SL360C for Tr 3 and
Tr 4 any shunting effect of transistor capacitances across
R 3 is reduced.

son

r-----~----~~----~----------+9V

04

100

R2

R3

39k

22k

T03

Cl

01

'1-+---O

;;

\

"
o
5

'0

(,

789100

\
~

6

7

a

'J 1000

FREaUENCY -MHz

Fig. 7 FrequencV response of,wide band amplifier

t--..

'1)'

........

~

r--..

w

!---

~

oZ

2

o

"

5

V

6789100

SOURCE

RESISTANCE

2

RS OHMS

Fig. 8 Calculated noise figure

v. source impedance

227

SL362C
LAYOUT

optimum of 200n. The other method is to connect two
transistors in parallel as shown in Figure 9. The effect of
this combination is compared with a single transistor in
Figure 10. The graph shows the calculated noise figure versus
emitter current with a 50n source impedance for both long
tailed pair and common emitter configurations. As can be
seen, a noise figure of 1.6 dB at 50n source ca~ be achieved
with the arrangement of Figure 9 in a grounded emitter
configuration. The parallel connected combination will, of
course, have double the output capacitance of the single
device, but the effect of this on the high frequency
performance can be reduced by feeding into a low
impedance. Also, the combination will have a lower fT than
a single transistor at a given operating current. However, if
the current is· doubled in the combination, little
degradation will occur.

It has been found that the circuit is not particularly
sensitive to layout change, but the obvious precautions in
constructing VHF circuits should be observed. Transistor
leads should be kept as short as possible, in particular the
emitters of Tr I, Tr 2 and Tr 3. The leads of R 7 should
also be short and if accurate gain stability is not required, a
carboncomposition resistor will give minimum inductance.
NOISE REDUCTION

figure

Two techniques are available to reduce the noise
at low source impedances. One is to use a

transformer to produce a source resistance nearer to the

COLLECIOR

BASE

EMITTER

CIRCUIT DIAGRAM

PIN CONNECTIONS

Fig. 9 Parallel connection of two transistors

,
)

---

I--...

,

1-),,"

r--

I

-- --- ----

--- --- ---

/
~

I
I

PAIR

f---

I

I

/CO,",,",ON EMITTER

__ L'..

----

I
l"ILI;O

J

'I-

I

--SINGLETRANSIS'OR

-

0

-

--PARALLELED

,
IE(mA)

Fig. 10 Noise figure at 50f'lsource impedance

228

PAIR

,

SL501/2/3

SL551/2/3

OPLESSEY

SL500 SERIES

SEMICONDUCTORS

WIDEBAND AMPLIFIERS

A&B

SL501 A&B SL502A&B SL503A&B
SL551A&B SL552A&B SL553A&B
The SL500 series are bipolar integrated circuit wideband

FEATURES

RF amplifiers, developed for use in linear radar I F strips

operating at centre frequencies between 10 and 60 MHz.

• Upper Cut-off Frequency 100 MHz Typ
• MidBand Current Gain 26 dB Typ
.AGe Input

AGe facilities and supply line decoupling are incorporated
in the circuits. The mid-ban~ current gain is typically 26dB.
The SL501A and SL5018 differ only in current gain and
cut-off frequency tolerance:.. Both are supplied without an

• On-chip Supply Decoupllng

output load resistor (free collector). Flatpack versions are
SL551A and SL551B, respectively. The SL502A and
SL502B are simila. to the SL501A and SL501B but
incorporate a 1kn output load resistor. Flatpack versions
are SL552A and SL552B, respectively.
The SL503A and SL503B are similar to the SL501A and
SL501 B except that the output current swing is typically
5mA. Flatpack versions :>f SL503A and SL503B are
SL553A and SL553B, respectively.

APPLICATIONS
• R

.~ -.

,

0

0

"

'0

... L.e. VOLTAGE

'0
(V)

"

'0

--

'-

i

0

0'

,

.\
\

,

0 - - ___

I

f-I

0

I

0

-

2S~C

,

1\

I

,1..0L-

\

0

.2SOC

!

o-~-I

-40

TEMPERATURE (OCt

FREQUENCY (104Hz)

0

0>

'0

A,GC

"

"

'0

CURRENT (", ... )

'0

Fig. 5 A.G.G. characteristics

Characteristics of the SL500 series amplifiers expressed
in Y parameters are given in Fig. 6 to 9; The parameters are
defined as follows:

---0

0

., t :j,-------,t: i "

0
T-.2S"C

0

0

V

0

and

f--

Y" = G" + jB"

Y,.

=

IY,. lei'l,.

/

v.

0

Where

V

:/

w

'0

'"

00

'00

FREQUENCY '104Hz I

Fig. 7 Feedback admittance (Y 12)

231

SL501/2/3 SL551/2/3 A&B

FREOUENCY IMH,)
.0

'00

0

r-+l00":;""-

- .--

0

r-+25"C

--

1--.....-

/'

/'

~-500C
'I

V

T'+25°~ ['-,

r--

----/' ---- V

;;

r-...:

I

::-----..T_.50 0 C

r-+100"C

--.: ~--

°

i-- r-

I
1
1

'0

0

1
'0
FREQUENCY (MH:!

.0

~~~

'00

'0

Typical input admittance v. frequency and temperature (without A.G.C.)

'0

FREQUENCY (MHz)
'0

'0

'0

'00

0

'-

.."". r---

I

...-:;?'
I

or- r-

r_ + 25"C

I

~o;p

0
FULL .... GC

~LL.GC

r- r- r-

'\l

"'l'\,
,..0 A,G.C

/ ' /'
,/

;;

~

""'::0-

0

T- +25"C

or-

- --

r- r-

0

0,0

'"

'"

FREQUENCY

'0

'0
(MHz)

Typical input admittance v. frequency, with and without A.G.G.
Fig.

'00

100

'00

"0

"\

'00

~

!
-

6 Input admittance (Y 11)

500

\

400

'00

wo

,w

\.

i"
1"'-

'\,

;

1'..

I"

r-+l00·C

'0

'00

r-/

!-

\

'00

0'0

.

' \ T- -SO-C

'-

l"'-

r-....

--

'0/

T· ... 2S"C

\.

"

'0

r--.

i"--

r--

T-'" 25"C

........

t--

.0

-

'0

''-

r--I-I--r'00

'0

.......
'0

Ow

I'A£QUENCY 1101Hz)

Fig. 8 Fo!'w8rd transfer admittance (Y 21)

232

1\

'0

.0

FREOUENCY (MHz)

.0

'00

SL501/2/3 SL551/2/3 A&.B

v

v
I~

0",

60

10

FREOUE.NCY [MHzl

FREOUENCY

'"

[~Hz)

Typical output admittance v. frequency and temperature

2

!20'~~-+-+~~4-~+-+-~~~-T-+~4-~

3
/

1"00~r'

mE±3miB.

~_"""H~'
~'

°0

01

'0

'2

°o~~~~~~-L~o.~~.~o-L~.~,~~~~~~~
A.G.C. VOLTAGE Ivl

AGe VOLTAGE 'v,

Typical output admittance v. A.G.C. voltage
Fig.9 Outputadmittance (Y'l2)' These curves apply to SL501A and B, SL503A and 8. SL551A and 8 and SL553A ltnd B. To obtain Y22 for

SL502A and 8 and SL552A and B. increase output conductance fG 22 J by 1mmho and output capacitance by 1pF.

ABSOLUTE MAXIMUM RATINGS
COIIREeT

/

OPEltATlNG

"EGlON

>"'~--~d---f--+------~----4-------1

Storage tern peratu re
_55° to +175°C
Chip operating temperature
+ 175°C
Chip·to-ambient thermal resistance
250°CIW
Chip-to-case thermal resistanc
BO°CIW
Maximum AGC signal
+3.5V or 20mA
Maximum instantaneous voltage (pin 4)
+12V

OPERATING NOTES

~~----~----~.~o----~.~,----~~~----!
NEGATIVE SUPPLY

Fig. 10

VOLTAGE (VI

Absolute maximum supply vo/tagtls.

The amplifiers are provided with two earth connections
to avoid the introduction of common earth lead inductance
between input and output circuits. The equipment designer
should take care to avoid' the subsequent introduction of
such inductance.

233

Sl501/2/3 Sl551/2/3 A&B

The positive supply decoupling capacitor Cl has a series
resistance of, typically, 10 ohms. The capacitor is a
junction type having a low breakdown voltage and
consequently the positive supply current increases rapidly
as the supply voltage exceeds 7.5V.
AGC sl )uld not be applied to stages required to give
output swings in excess of ±0.2mA unless substantial
distortion can be tolerated.

234

SL501 and SL503 devices must be provided with a DC
path between pins 3 and 4 for the collector current of the
output stage. The DC resistance of this path should not
exceed 1000 ohms for the SL501 and 400 ohms for the
SL503. The AC load may be connected between pins 3 and
4, or pins 3 and 1. Similar conditions apply to the flatpack
versions of these devices: SL551 and SL553, respectively.

SL510C SL511 C

•

Plessey
Semiconductors

SL510 SERIES
RF DETECTORNIDEO AMPLIFIFR

SL510C
INCREMENTAL GAIN 11 dB. DC-24MHz

SL511C
INCREMENTAL GAIN 16 dB. DC-14MHz
The SL~lOC is a bipolar integrated circuit combining the
functions of r. f. detection and video amplification. The
device is sectiom;lised to enable the r. f. detector to be used
with or without the accompanying video amplifier.
The detector will accept carrier wave signals over a

bandwidth from d.c. to 100 MHz. The incre'-,ental gain is
typically lldB with a video bandwidth of d.c. to 24 MHz.
The Ci[Fuit will handle pulse widths down to 16ns and the
dynam ic range is 31 dB.

DIiTECTOR

,

INPUT

CM10

.

VIDEO

",IIoIPLIFIER BIAS

Fig, 1 Pin connections

The primary area of application is in the radar field fa
r. f. pulse detection, and video outputs of 6 volts and O.!
volts can be driven into 600n and 50n loads respectively
However, the wide dynamic range of the SL510C aisl
makes it suitable for detection of sine wave amplitud
modulation.

,
INTERNAL
81AS SUM-LV

.

OfTEClOR

The SL511C is of similar design, but has an increment,
gain of typically 16dB over a bandwidth of d.c. to 14 MHl
The dynamic range is maintained at 28dB.
The circuits have been allocated the following NAT(
Stock Numbers:

,

,
VIDEO

AI.U"lIFIER INPUT

,

lINI(

Type

NATO Stock No.

SL510C
SL511C

5962-99-038·0470
5962-99-038-0471

"'''0£ FOR SLSIOC

1+4\11

Fig. 2 Circuit diagram

---J.,

RF

..,... FillER

"'"
_

'Fig. 3 FulJ-wave recfification

~

VIDEO
OUTPUT

Fig. 4 Half-wave rectification

235

SL510C SL511C

Electrical Characteristics
Test conditions (unless otherwise stated):
Temperature = +22°C ±2°C
Supply voltage = +9V
External connections:
Pin 2 decoupled via 10nF capacitor to earth.
Pin 6 connected to pin 7.
Pin 8 connected to pin 9.

Value
Characteristic

Overall incremental gain (1)
Half·wave
Full-wave

Pulse response
Rise time

Type

SL510C
SL511C
SL510C
SL511C

Units

Min.

Typ.

Max.

3.5
8.0

5.5
10.0
11.5
16.0

7.5
12.0

16.0

35.0

ns

16.0

35.0

ns

dB
dB
dB
dB

Test Conditions

See Fig. 3 Detected r.f. is
See Fig. 4

smoothed; centre
frequency = 60 MHz

Both

Fall time
Positive limiting level at
video outputs

Both

Quiescent d.c. output voltage

SL510C
SL511C

5.0

6.0
0.5
0.6

V
1.0

1.0

Output pulse height with respect
to OV = +5V.
Measurements are from 10% to
90% points on wave form
Load impedance
input at GO MHz

= 600n; r.f.

V
V

Upper cut-off frequencies

Detector circuitry

Both

Video circuitry

SL510C
SL511C

100

MHz

24
35
14
21

MHz
MHz
MHz
MHz

R, = 25n, ZL = Video input.
Yin = 150mV r.m.s., 30%
modulated. Output is -ldB
with respect to an output at
10 MHz.
Output -3dB R, = 25nZ L =
Output -6dB GOOn in parallel
Output -3dB with 10pF.
Output -6dB Measured with

respect to an
output at 2 MHz.
Overall dynamic range (2)
Half·wave
Full-wave
Current consumption
I nput impedance to
detector (3)

SL510C
SL511C
SL510C
SL511C

25
22
31
28

Both
Both

20

Real part
I maginary part

dB
dB
dB
dB
30

See Fig. 3
See Fig. 4

mA
Measured between pins 4 and 5
input level = 600mV r.m.s.;
centre frequency = 60 MHz.

3

Kn
pF

Output impedance from video SL510C
amplifier
SL511C

6
12

n
n

Measured at 2 MHz.

Video amplifier small signal

27
33

dB
dB

Measured at 2 MHz. See Fig. 5

gain

10

SL510C
SL511C

~.OTE6efined as d{video out)
d(r.f, in)

2.
3.

236

Defined as a variation of ±5% in the incremental gain.
This parameter is not guaranteed

SL510C SL511C

lilDEO

VIrI:O

OUTPUT

OUTP'UT

Fig. 5 Video amplification without detection

OPERATING NOTES
Tuned circuit coupling

There are two basic methods of driving the
Detector/Video when used in its normal mode; i.e. from a
tuned circuit or via an R-C network. In the former case
both full-wave and half-wave rectification are possible using
the configurations shown in Figs. 3 & 4 respectively. When
the internal bias supply is being used, as illustrated, the
quiescent current level of the current source will be drawn
from the supply, and the current level in the output stage
of the video amplifier will be reduced accordingly. For
connection to an external bias supply allowance must be
made for 2mA required to drive the video amplifier bias,
(pin 6).

Fig. 7 R-C coupled combination (half-wave), with RF amplification.

Fig. 5 illustrates this technique applied to the use of
the circuit for video amplification without detection, where
it may be necessary to set the output qu iescent voltage
midway between the internal supply line and earth. Input
coupling is via Co/R2, where the reactance of Co is chosen
to be low compared with R2. Since the video amplifiel
response extends down to d.c. R2 must be small to limi1
the input voltage error due to the base current flowing ir
R2. This can be overcome by using an r.f. choke with lOlA
d.c. resistance.
SL610/11/12 - SL51 0/11 Combination
The simplest method of connection is shown in Fig.
using R·C coupling. In view of the bandwidths involved duo
care in layout must be observed (note that the output eartt
of the SL51 0 is taken forward to the video-detector earth)
For tuned coupling refer to the SL61 0111 /12 data sheet.

VIDEO
OUTPUT

Absolute Maximum Ratings
Storage Temperature
Operating Temperature
Supply Voltage

_55°C to + P5°C
_55°C to + 125°C
+12 Volts

Fig. 6 R-C coupling mode (half-wave)

R-C coupling
R-C input coupling is illustrated in Fig. 6. Decoupling
capacitors, Co, should offer low a.c. impedances relative to
the series resistors, R1, at the frequency of the input.
Voltage drops arising through input base currents flowing in
the series resistors will be amplified and will depress the d.c.
quiescent output of the video amplifier. For low p devices
this can be excessive and should be offset by introducing
resistor R2 which injects current into pin 8 to raise the
output level. With R2 connected to the internal supply line,
as shown, the d.c. output voltage will be 52/R2 (±25%) for
the SL510C and 26/R2 (±25%) for the SL511C where R2 is
in kil.

CIRCUIT DESCRIPTION
The circuit (Fig. 2) incorporates a long tailed pa
detector, with both input bases (pins 4 and 5) accessible s
that it can be driven either full-wave or half-wave, <:
illustrated in the application no'es. The output (pin 8)
taken from an attenuation chain at a level suitable to dri\
the video amplifier (input pin 9). With r.f. filtering betwee
pins 8 and 9 (the usual mode of operation) the input lev,
to the video amplifier will reduce to the mean value of It
detected r.f. i.e. (2/11 x peak output) for full·wal
rectification and (1111 x peak output) for half·wal
rectification_

237

SL510C SL511C
The video amplifier is directly coupled throughout and
essentially consists of two stages of gain TR4 and TR5, and
an emitter follower output stage TR 7 with overall feedback
to the emitter of TR4. Pin 6, the video amplifier bias,
should be taken to the same d.c. potential as pins 4 and 5

to ensure that ~he quiescent output level is tolerant of
variations in this potential. I n this condition the output is
at a 'zero' quiescent level (nominally +600 mY), which
allows direct coupling to the load, a convenient feature
since output pulses are uni-directional when driving from
the detector.
The internal bias supply at pin 7 is an emitter follower
biased from the supply line and an external current drain is
required to establish its quiescent current.

I

s~r'c

os

..-

s+c

..-

I

-

l - I-I-- I--

I
Fig. 8 Change in quiescent d.c. output voltage v. temperature

I'--'--,
............ t'---SL51OC

SlSl1C

---SL510C(-

r-- ~"l

V
o

+25

+50 +75

+100 +125

-so
Fig. 10

-25

0

+25

+50

+75 +100 +125

Change in overall incremental gain v. temperature
Fig. 9 Change in upper 3dB point for video amplifier v. temperature

I
I

V

Sls\'C

V
---'

~"c

-so
Fig. 11

~238

-25

I

~',,,o}-

---- ----

+25

+50

'--

----I---.

Si S1 ,cr--

r---

I
I
0

JI

r-

S~1510C
1
SL SllC

"j
I

-

+75 +100 +125

Change in rise/fall time with temperature

Fig. 12

Change in dynamic range (half-wave) with temperature

SL521A,B&C

•

Plessey
Semiconductors

SL521 SERIES
WIDEBAND AMPLIFIERS

SL521A,B&C
The SL521 A, Band C are bipolar monolithic integrated
circuit wideband amplifiers, intended primarily for use in
successive detection

logarithmic

I F strips, operating at

centre frequencies between 10M Hz and 100MHz. The

OUTPUT
EARTH

devices provide amplification, limiting and rectification, are

I

suitable for direct coupling and incorporate supply line
decoupling. The mid-band voltage gain of the SL521 is
typically 12 dB (4 times). The SL521A, Band C differ
mainly in the tolerance of voltage gain and upper cut·off
frequency. The SL521A, Band C versions have TO-5

eM8

encapsulation.

FEATURES

••
••
••
•

Well-defined Gain
4dB Noise Figure
High liP Impedance
Low alP Impedance
165MHz Bandwidth
On-Chip Supply Decoupling
Low External Component Count

Fig. 1 Pin connections

ABSOLUTE MAXIMUM RATINGS
(Non-simu ltaneous)
Storage temperature range

-55°C to +175°C
+175°C

Chip operating temperature

Chip·to·ambient thermal resistance
Chip-to·case thermal resistance
Maximum instantaneous voltage at
video output
Supply voltage

APPLICATIONS
•
Logarithmic I F strips with Gains up to 108 dB
and Linearity Better Than 1 dB.

250°CIW
BO°CIW
+12V
9V

~~_~__~___"-___-rCy2 ~~~PLY

~-1--~' g~:;~T/D

W 10-0

~~

6, 0

f--+-+-H.ISI'f+I--1-

\
f--l--C+-H-I-t-l-l-l-- +-+-+++-I-l-Ic+--+1i1-1--+-+-+i

f----+--++++I+++--+-++-+-+++++--- f---+-++-+-ffi-l+---'----I-++f++fL-- 30

FREQUENCY

Fig. 2 SL521 Circuit diagram

Fig. 3

60

I MHz)

Volrage gain v. frequency

239

SL521A,B&C

ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Temperature
"" +22°C ± 2°C
= +6V
Supply voltage
DC connection between input and bias pins.
Value
Characteristic

Circuit

Min.

Typ.

Units

Conditions

10 ohms source, SpF load

Max.

Voltage gain, f

= 30MHz

SL521A,
SL521 B,
SL521C,

11.5
11.3
11.0

12.5
12.7
13.0

dB
dB
dB

Voltage gain, f

= 60M Hz

SL521A,
SL521B,
SL521C,

11.3
11.0
10.7

12.7
13.0
13.3

dB
dB
dB

(Fig. 3)

SL521A,
SL521B,
SL521C,

150
140
130

I Upper cut·off frequency
I

170
170
170

MHZ!
MHz 10 ohms source, SpF load
MHz
MHz

Lower cut· off frequency (Fig. 3)

All types

5

Propagation delay

All types

2

Maximum rectified video output
current I Fig. 4 and 5)

SL521A,
SL521B,
SL521C,

Variation of gain with supply v'lltage

All types

0.7

db!V

Variation of maximum rectified

All types

25

%!V

7
1.10
1.15
1.20

1.00
0.95
0.90

10 ohms source, SpF load

ns
mA}
mA f
mA

= 60MHz, 0.5V

rms input

output current with supply voltage
All types

Maximum input signal before overload

1.S

SL521A,
SL521 B,
SL521C,

Supply current

V rms See note below

1.9
4

5.25

dB

12.5

15.0

18.0

mA

11.5

15.0

19.0

Noise figure (Fig. 6)

1.2

Maxiumum RF output voltage

f

= 60MHz,

Rs

mA
Vp·p

Note: Overload occurs when the input signal reaches a level sufficient to forward bias TRl base-collector junction on peaks

INPUT SIGNAL IVrmsJ

240

Fig. 4

Rectified output current v. input signal

= 450 ohms

SL521A,B&C
The 500pF supply decoupling capacitor has a resistance
of, typically, 10 ohms. It is a junction type having a low
breakdown voltage and consequently the positive supply
current will increase rapidly if the supply voltage exceeds
7.5V (see ABSOLUTE MAXIMUM RATINGS).

II-r-

r+I . ~I

_v--J-

c----.

I

lo,OMH,

I
I

I

i

;

;0
AMBIENT TEMPERATURE lOCI

20

R"

Fig. 6

r--.- r---

'SOA

I
'C

00

TEMPERATURE

Fig. 5 Maximum rectified output current v. temperature

-;v-

1°C)

Tvpical noise figure v. temperature

OPERATING NOTES
The amplifiers are intended for use directly coupled, as
shown in Fig. 8 (This figure shows the TO-5 version.)
The seventh stage in an untuned cascade will be giving
virtually full output on noise.
Noise may be reduced by inserting a single tuned circuit
in the chain. As there is a large mismatch between stages a
simple shunt or series circuit cannot be used. The choice of
network is also controlled by the need to avoid distorting
the logarithmic law; the network must give unity voltage
transfer at resonance. A suitable network is shown in Fig. 9.
The value of C1 must be chosen so that at resonance its
admittance equals the total loss conductance across the

FREQUENCY

Fig. 7

I MHz)

Input admittance with open-circu;t output

tuned circuit. Resistor R 1 may be introduced to improve
the symmetry of filter response, providing other values are
adjusted for unity gain at resonance.

A simple capacitor may not be suitable for decoupling
the output line if many stages and fast rises times are
required. Alternative arrangements may be derived, based
on the parasitic parameters given.

Values of positive supply line decoupling capacitor
required for untuned cascades are given below. Smaller

values can be used in high frequency tuned cascades.

Fig. 8

Direct coupled amplifiers

Number of stages

6 or more I

I Minimum capacitance

30nF

5

110nF

I4 I3
I 3nF 11nF

The amplifiers have been provided with two earth leads
to avoid the introduction of common earth lead inductance

between input and output circuits. The equipment designer
should take care to avoid the subsequent introduction of
such inductance.

Fig. 9

Suitable interstage tuned circuit

241

SL521A.B&C

Parasitic Feedback Parameters (Approximate)
The quotation of these parameters does not indicate that
elaborate decoupling arrangements are required; the
amplifier has been designed specifically to avoid this
requirement. The parameters have been given so that the
necessity or otherwise of further decoupling. may become a
matter of calculation rather than guess·work.
14 _ R F current component from pin 4

V6

-

Voltage at pin 6

20 mmhos

(This figure allows for detector being forward biased by
noise signals)
V 6 ~ Effective voltage induced at pin 6 ~ 0.003
V4
Voltage at pm 4
12 _ Current from pin 2

V6

-

Voltage at pin 6

6mmhos (f

~ Voltage induced at pin 6
[~
V~a
Voltage at pin 2

~

10MHz)

0.03 (f ~ 10M Hz)

Voltage at pin 2
(pin 6 joined to pin 7 and
fed from 300 ohms source)
[V6b Volt~ge induced.t pin 6 ~ 0.01 (f ~ 10M Hz)
LVJb
Voltage at pm 2
Voltage at pin 2
(pin 7 decoupled)

12

[V;] [V6l

V. L\t;J a [V2.J b decrease with frequency above 10MHz
at 6 dB/octave.

242

SL52

•

Plessey
Semiconductors

SL500 SERIES
WlDEBAND AMPUFIERS

SL525C
WIDEBAND LOG IF STRIP AMPUFIER

The SL525C is a bipolar monolithic integrated circuit
wideband amplifier, intended primarily for use in successive

detection logarithmic I.F. strips, operating at centre
frequencies between 10MHz and 60MHz. The devices
provide

amplification,

limiting

and

rectification,

are

suitable for direct coupling and incorporate supply line
decoupling. The mid-band voltage gain of the SL525C is
typically 12dB.

eMI
Fig. 1 Pin connections

FEATURES

••
••
•••

Well-defined Gain
4dB Noise Figure
High liP Impedance
Low alP Impedance
150 M Hz Bandwidth
On-Chip Supply Decoupling
Low External Component Count

ABSOLUTE MAXIMUM RATINGS
Storage temperature range

Operating Temperature range

_55°C to +17
_20°C to +lU

Maximum instantaneous voltage at

+

video output
Supply voltage

APPLICATIONS
•
Logarithmic I F strips with Gains up to 108 dB
and Linearity Better Than 1 dB.

18-11 ~~~-\-+-+++++t~-j~~I-+W++~-+~H-

r-~~-;!;"~-r--~~-t~~~-r<=:J-'>2 s0~PLY

,--+-,---,,' g~i~~~EO
SOOp

,

BI/I,S

I"IPur

.

t--t~~-++~---<>J ~t:TPUT

'~,--~~~~~~w,-~~,~,-L~~~~.--d.-~
FREQUENCY 'MHz I

Fig.

2 Circuit diagram

Fig.

3

VoltagB gain v. frequency

24

SL525C

ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):T A ~ +22°C ±2°C
Supply voltage ~ +6V
DC connection between input and bias pins
Value
Min.
Voltage gain
Upper cut·off frequency (Fig. 3)
Lower cut·off frequency (F ig. 3)
Propagation delay

Max. rectified video output
current (Figs. 4 and 5)

Conditions

Units

Characteristic
Typ.

Max.

10.5
10.0
120

150
5
2

0.S5

~

dB
dB

7

MHz
MHz
ns

Rs
Rs

mA

f

1.25
0.7

Variation of gain with supply voltage

f
f

13.5
14.0

~

~

~

30MHz, Rs
60MHz, Rs
~
~

10r!, CL
10r!, CL

1Or!, CL
10r!, C L

~
~
~

60MHz, V in

Maximum liP signal before overload

1.S

~

Noise figure (Fig. 6)

25

%iV
Vrms

4

5.25

dB

Maximum R F output voltage

1.2

Vp-p

Supply current

15

mA

See note 1
f

~

60MHz, Rs

~

450r!

NOTE
Overload occurs when the input signal reaches a level sufficient to forward-bias the base-collector junction of TRl on peak.

0;

INPUT

Fig. 4

244

SIGNAL IVlmsl

Rectified output current v. input signal

8pF
8pF

500mV rms

dBiV

1.9

~

SpF
SpF

Variation of maximum rectified
output current with supply voltage

~

f

SL525C

--1---

I
--;--.--+

The 500pF supply decoupling capacitor has a resistance
of. typically. 10 ohms. It is a junction type having a low
breakdown voltage and consequently the positive supply
current will increase rapidly if the supply voltage exceeds
7.5V (see ABSOLUTE MAXIMUM RATINGS).

-

--I

I

--

f.-- r-

lOMHz

,

..-

---+=-~

--

,

---

---

I~PUI

-

tHZ
~!DMH.

-

V

o,O-SV R MS

-[--------+----

---1

I , bOMHz
R"I.50fL

-.

i

-;0

Fig. 5

i

V

I

.-

.

-

r-T:=:7

;0
AMBIENT TEMPERATURE I"Cj

"

.""

20

1.8

60

TEMPERATURE

Fig. 6

Maximum rectified output current v. temperature

IQC)

Typical noise figure v. temperature

OPERATING NOTES
The amplifiers are intended for use directly coupled. as
shown in Fig. 8
The seventh stage in an untuned cascade will be giving
virtually full output on noise.
Noise may be reduced by inserting a single tuned circuit

in the chain. As there is a large mismatch between stages a
simple shunt or series circu it cannot be used. The choice of
network is also controlled by the need to avoid distorting
the logarithmic law; the network must give unity voltage
transfer at resonance. A suitable network is shown in Fig. 9.

FREQUENCY

Fig. 7

IMHz)

Input admittance with open-circuit output

The value of Cl must be chosen so that at resonance its
admittance equals the total loss conductance across the
tuned circuit. Resistor R 1 may be introduced to improve
the symmetry of filter response, providing other values are
adjusted for unity gain at resonance.

A simple capacitor may not be suitable for decoupl ing
the output line if many stages and fast rises times are
required. Alternative arrangements may be derived. based
on the parasitic parameters· given.

Values of positive supply line decoupling capacitor
required for untuned cascades are given below. Smaller
values can be used in high frequency tuned cascades.

Fig. 8

Direct coupled amplifiBrs

Nu mber of stages

6 or more

I Minimum capacitance

30nF

I

5

110nF

I4l
I 3nF

3

11nF

The amplifiers have been provided with two earth leads
to avoid the introduction of common earth lead inductance
between input and output circuits. The equipment designer
should take care to avoid the subsequent introduction of
such inductance.

Fig. 9

Suitable interstage tuned circuit

245

SL525C
Parasitic Feedback Parameters (Approximate)
The quotation of these parameters does not indicate that
elaborate decoupling arrangements are required; the
amplifier has been designed specifically to avoid this
requirement. The parameters have been given so that the
necessity or otherwise of further decoupling, may become a
matter of calculation rather than guess-work.
14 _ RF current component from pin 4

Ii 6

Voltage at pin 6

-

20 mmhos

(This figure allows for detector being forward biased by
noise signals)
V 6 ~ Effective voltage induced at pin 6 ~ 0 003
Voltage at pin 4
.
V4

I z _ Current from pin 2
Voltage at pin 6

Ii 6

[~a

6mmhos (f

~

10M Hz)

Voltage induced at pin 6 ~ 0.03 (f ~ 10MHz)
Voltage at pin 2
Voltage at pin 2
(pin 6 joined to pin 7 and
fed from 300 ohms source)

l

IV6 Voltage inducedot pin 6 ~ 0.01 (f ~ 10MHz)
LVzJb
Voltage at Pin 2
Voltage at pin 2
(pin 7 decoupled)

I z IV.;]

[V6l

Ii. L\t;J a [VzJ b decrease with frequency above 10MHz
at 6 dB/octave.

246

SL530C

•

Plessey
Semiconductors

SL530C
mUE LOG. AMPUFIER

GENERAL DESCRIPTION

Dynamic Range

The SL530C is a monolithic non-linear integrated

circuit designed to realise a logarithmic transfer function in
high-gain amplifier strips at frequencies between 4 and
80 MHz. THE DEVICE IS SO OESIGNED THAT INPUT
SIGNAL PHASE INFORMATION IS RETAINED. A
typical dynamic range of 70 dB can be achieved over a
bandwidth of 10M Hz.
The operation of the SL530C relies upon the
principle that amplifiers with an input/output characteristic
as shown in Fig. 1 can be cascaded to produce the straight
line approximation to a logarithmic law shown in Fig. 2.
This may be represented by the expression:

When Vin ;;. VLO then all stages of the strip are
operating in the unity gain mode. As n (the number of
stages in the strip) is increased, the minimum input voltage
for the onset of the logarithmic law is VLO/An The input
dynamic range is therefore An or n20 10gA dB. In other
words, the dynamic range equals the low level strip gain.
If this level is as low as the effective noise input
voltage, the addition of further stages does not result in any
increase in dynamic range. For Rs= 50n the effective noise
input voltage is approximately 3nV 1y'HZ The maximum
dynamic range is thus given by:
Dynamic Range =

V LO
Where B
3 x 10 9y'B
15

X

106

'" y'B(Hz)
Where Kl, K2, K3 are scaling constants.

II oul

SLOPE

0'

Bandwidth

(VLO "'45mV)

Hence for a bandwidth of 10 MHz, dynamic range
73 dB, and the number of amplifier stages is six.

The logarithmic law remains true for any value of A
or VL (the breakpoint with respect to input or output)
providing cascaded units are similar; It depends only upon
the slope gain after limiting: this must be unity. Differences
in this slope gain between the devices used in the strip will
cause ripples in the log response, whilst the values of A, VL
and n determine the dynamic range available.

II out'

=

Unity Gain Slope

The logarithmic accuracy of a strip is dependent upon
the consistent accuracy of this slope from deviCe! to device.
The frequency response of the IC shows some peaking
above 50 MHz but this may be reduced by a resistor in
series with the output from pin 6. A typical value is
between 0 and 50n.

nth STAGE

~--f~

GAIN

~-~------.-------

'"
Fig. 1 Device transfer characteristic

=

Fig. 2 n-stage strip·transfer characteristic

247

SL530C

ELECTRICAL CHARACTERISTICS
Test Conditions: Positive supply
6 volts
Ambient temperature
+22°C ± 2°C (unless otherwise stated)
D.C. connection Pin 4 to Pin 5
Output 01 each device loaded by input 01 next.
Value

Test Conditions

Characteristic

Min.

Typ.

Max.

Units

Midband gain low level

11.6
-1
60

13.6
0
90

15.6
+1

Phase change
Gain change

±5.5
±0.5

±12

db
dB
MHz
MHz
Degrees
dB

Voltage at Pin 4 and Pin 5
Supply current

1.75
20

Slope gain high level
Upper cut·off Irequency

4

Lower cut-off frequency.

25

Vin = 2 mV rms, f = 30 MHz
Vin = 100 mV rms, 1 = 30MHz
-3dB w.r.t. 1 = 30 MHz
-3dB w.r.t. f = 30 MHz
f = 30 MHz, Vin = 2 - 600mV rms.
Vin = 100 mV,
1 = 30 MHz,
T A = _55° C to 125 0 C
Measured W.r.t. earth

V
mA

Note: Pins 3, 7, 8 are intended to enable system currents to be directed to their proper location, thus avoiding earth loops.
All these pins must be at the same d.c. potential.

OPERATING NOTES
The layout should be in·line and compact, using
physically small components. Provided this is the case an
earth plane is not necessary even though the strip is boxed
eventually. It may be necessary to use an input isolating
transformer of 1: 1 turns-ratio in which instance the box
should only be connected to the outer screens of the
co-axial connectors at input and output and to pin 7 of the
output stage.
Fig.

3 Tvpical circuit connection

62

Fig. 4 TVPiCaI 4-stage strip

ABSOLUTE MAXIMUM RATINGS
_55°C to +125°C
Operating temperature range
_55°C to +175°C
Storage temperature range
+175°C
Chip operating temperature
Chip-to-ambient thermal resistance 250°C/W
Chip-to-case thermal resistance
80°C/W
Operating voltage Pin 2
3V
FREQUENCY 1M Hz)

248

Fig. 5 Frequency response

SL530C
~-

I
r-- f----

~---

v

-

~

v

~

1

-

~

r----

,......-

........ ~

.............

.........

-

......

,

-

30MHz

f

~

30MHz

II
;00

INPUT

;00

LEVEL {mV rmsl

INPUT LEVEL {mV rmsl

Fig. 6 Transfer characteristic

Fig. 7. Phase shift v. input

'"

/'

V

D'

/'

'"

./

V-

r-- -

'"

I

1- -

-

I

f =30MHl

L._L-C I

r--

>co
f= 30MHz

90
30

20

"0

INPUT LEVEL {mY rms)

INPUT 2mV

ANO

.......
o

""

r-......

'=rJ"

IOOmV

'\
i'-.

RESISTANCE

"

,\
\

rmsl

Fig. 9 Phase shift v. input

REACT ANCE

500

30

INPUT LEVEL (mV

Fig. 8 Transfer characteristic

o

I---- .......

r--...

'"

1

I

1"-

INPUT lmV

"\j

i". I"
'i-INPUT

---

100mY

1

"

~~

r-;::: .....

1

o

;0

;0

FREQUENCY (MHz]

FREQUENCY (MHz)

Fig. 10 Input impedance v. frequency
0
RESIS-~NCE

REACTANCE

0

.......

V
f--~

r-, 1--=
0
0

/

--+f- ,/

V

---

~-

V
t--

- - I-I--

+j X

Coo
R

V

/
/

-

I-

-

co

"0

FREQuENCY ·,MHz!

I'

V
',Il

~f~-

r-'00

FREQUFNCY :M"izi

Fig. 11 Output impedance v. frequency

249

Sl530C
1

~..,....--~---.--.-----------------.--r-C::Jf--<>+6V

6

f--+---o

OUTPUT

7 }
B

Fig. 12 SL530C circuit diagram
(equivalent only)

250

SUPPLY

OUTPUT EARTH
AND
-VE SUPPLY

SL 500 SERIES
RADAR CIRCUITS

SL531C
TRUE LOG IF AMPLIFIER
The SL531C is a wide band amplifier designed for use
in logarithmic IF amplifiers of the true log type. The input
and log output of a true log amplifier are at the same frequency i.e. detection does not occur. In successive detection log amplifiers (using SL521, SL 1521 types) the log
output is detected.
The small signal gain is 10dB and bandwidth is over
500MHz. At high signal levels the gain of a single stage
dropsto unity.Acascade of such stages giveaclose approximation to a log characteristic at centre frequencies
between 10 and 200M Hz.
An important feature of the device is that the phase shift
is nearly constant with signal level. Thus any phase information on the input signal is preserved through the strip.

eM8
Fig 1 Pm connections

FEATURES

•
•
•

Low Phase Shift vs Amplitude
On-Chip Supply Decoupllng
Low External Components Count

APPLICATIONS

True Log Strips with: ~
•
•
•

Log Range
Centre frequencies
Phase Shift

70 dB
10 ~ 200 MHz
± 05 degrees /10 dB

ABSOLUTE MAXIMUM RATINGS
Supply voltage
Storage temperature range
Operating temperature range

+15 volts
150°C
125°C
See operating notes
~55°C to +
~55°C to +

Max junction temperature
Junction ~ ambient thermal resistance
Junction - case thermal resistance

Fig. 2 Circuit diagram

150°C
220°C/Watt
BOoC/Watt

CIRCUIT DESCRIPTION
The SL531 transfer characteristic has two regions For
small input signals it has a nominal gain of 10 dB, at large
signals the gain falls to unity (see Fig 7). This is achieved by
operating a limiting amplifier and a unity gain amplifier in
parallel (see Fig 3). Tr1 and Tr4 comprise the long tailed
pair limiting amplifier, the tail current being supplied byTr5,
see Fig 2. Tr2 and Tr3 form the unity gain amplifier the gain
of which is defined by the emitter resistors. The outputs of
both stages are summed in the 300 ohm resistor and Tr7
acts as an emitter follower output buffer. Important
features are the amplitude and phase linearity of the unity
gain stage which is achieved by the use of 5GHz transistors
with carefully optimised geometries.

UNITY GAIN

'M'

Fig. 3 Block diagram

251

ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise stated):
Test circuit Fig (4)
Frequency 60 MHz
Supply voltage 9 volts
Ambient temperature 22± 2°C

Value

Characteristic

Small signal voltage gain
High level slope gain
Upper cut off frequency
Lower cut off frequency
Supply current
Phase change with input amplitude
Input impedance
Output impedance

Units

Min

Typ

Max

8

10
0
500
3
17
1.1

12
+1

~1

250

Conditions

Vin = -30dBm

dB
dB
MHz
MHz

10
25
3
2.5pf parallel with 1 k

-3d8 w.r.t.:t. 60 MHz

mA
Vin - 30 dBm to + 10 dBm

degrees

10 - 200MHz

1S0series with 25nh

OPERATING NOTES

3.

1.

The LF response is determined by the on chip capacitors
It can be extended by extra external decoupling on pins 5

SUPPly Voltage Options

An on chip resistor is provided which can be used to drop
the supply voltage instead of the external 180 ohms shown
in the test circuit. The extra dissipation in this resistor reduces the maximum ambient operating temperature to
100°C. It is also possible to use a 6 volt supply connected
directly to pins 1 and 2. Problems with feedback on the
supply line etc may occur in this connection and RF chokes
may be required in the supply line between stages.
2.

Low Frequency Response

and 1

Layout Precautions

The internal decoupling capacitors help prevent high frequency instability, however normal high frequency layout
precautions are still necessary. Coupling capacitors should
be physically small and be connected with short leads. It is
most important that the ground connections are made with
short leads to a continuous ground plane

"

I

f--

f---- f

f-

1----

I-

0

V,N"

=t

---

--::: p

::::::-

,-

40dBm

I

Fig 4 Test clrcwt

I

f-/')~.t-:L

55°C

I

'I

I
I
I

--

I

-k:;:
/'/

I

r---

,

\

,

1--!\

' i

I

,
,

0

I
I

I
I

Fig. 5 Small signal frequency response

252

--

I'

I

:lftfU

6O"'H,
\Icc ~ 9V

-LOW~

VIN IdBml

,

Fig 6 Phase v. Input

TYPICAL APPLICATION - 6 STAGE LOG STIP
Input log range OdBm to -70dBm
Low level gain 60dB (- 70dBm in)
Output dynamic range 20dB
Phase shift (over log range) ±3°
Frequency range 10 - 200MHz

if

/

/

/

/

/

/

V
-

I
-

VIN VOLTS Irms)

Fig. 7 hans/el cl7aracleflstlcs Imear plol

The circuit shown in Fig 9 is designed to illustrate the use
of the SL531 in a complete stnp. The supply voltage is fed
to each stage via an external 1800 resistor to allow operation to 125°C ambient. If the ambient can be limited to
+ 100 Q C then the Internal resistor can be used to reduce
the external component count. Interstage coupling is very
simple with just a capacitor to isolate bias levels being
necessary_ No connection is necessary to pin 5 unless operation below 1OMHz is required It is important to provide
extra decoupling on pin 1 of the first stage to prevent POSItive feedback occuring down the supply line. An SL560 is
used as a unity gain buffer. the output of the log strip being
attenuated before the SL560 to give a nominal OdBm output into 500.

!

I-~

+- -I~
VIN IdBm)

Fig 8 Transferctiaraclensllcs logarithrmc IIl!)UI scale

Fig. 9 CircUit diagram 6 stage sin;;

253

~'
60MHz

V

/

-00

/

I

/

II
'0

-w
"INPUT (dBm)

0

Fig. 10 Transfer function of log strip

254

•

SL500 SERIES

PLESSEY

RADAR CIRCUITS

SEMICONDUCTORS

SL532C
LOW PHASE SHIFT LIMITER
The SL532C is a monolithic integrated circuit designed for use in wide band limiting IF strips. It offers
a bandwidth of over 400MHz and very low phase shift
with amplitude. The small signal gain is 12dB and the
limited output is 1 volt peak to peak. The use of a
5GHz Ie process has produced a circuit which gives
less than 1 phase shift when overdriven by 12dB.
The amplifier has internal decoupling capacitors to
ease the construction of cascaded strips and the num-

INPUT
GROUND

ber of external components required has been minimised.

BIAS

FEATURES
•

Low phase shift vs Amplitude

•
•

Wide bandwidth
Low external components count

Vee 2

APPLICATIONS
•
•

Phase recovery strips in Radar and ECM systems
Limiting Amps for SAW paulse compression
systems

•

Phase monopu Ise radars

•

Phased array radars

Fig I. Pin connections

ABSOLUTE MAXIMUM RATINGS
•
•
•

Supply voltage
Storage te,mperature range
Operating temperature range

+ 15 volts

+

-55·C to
150·C
-55·C to + 125·C

vee

vee

2

CIRCUIT DESCRIPTION
BIAS

The SL532C uses a long-tailed pair limiting amplifier which combines low phase shift with a symmetrical limiting characteristic. This is followed by a
simple emitter follower output stage. Each stage of a
strip is capable of driving to full output a succeeding
SL532 but a buffer amplifier is needed to drive lower
impedance loads. No exteranl decoupling capacitors
are normally required but for use below lOMHz extra
decoupling can be added on pins 1 and 5. Bios for the
long-tailed pair is provided by connecting the bios
(pi n 2) to the deeouple,d supply (pin 1),

2

,I P
'o-__

,K

5K

GROUND

~

____L-____L-__- J

0 1P
GROUN D

7

Fig 2. Circuit diagram

255

ELECTRICAL CHARACTERISTICS
T est conditions (unless otherwise stated)

Temperature (Ambient) 25°C
Frequency 60MHz

Vee
RL

=

+9V
IK

Characterist ic

Min

Small signal voltage gain
Limited OP voltage

Value
Typ

10

Max

14

Lower cut off frequency

12
1
400
10

Supply current

10

15

Upper cut off frequency

Units

Conditions

dB
Vpk-pk

MHz
MHz

C on be lowered with external

capacitors

mA

Phase variation with signal

level

±1

degree

+20
1

dBm
dB

Vin

= 60dB - +10 dBm

Input Impedance
Output Impedance
Max Input Signal before overload

Gain variation with temperature

55'( to + 125'C

TYPICAL APPLICATION - 5 STAGE STRIP

300 ~V rms
-57 dBm

Input signal for full limiting

Limited output

y pk -

Phose shift (Vin -57-.. 4- 19dBm

pk

+ 3'typ

GROUND
10 nF

'"""'"., t0 0

o------j

1 GnF

,',
532

I

[J,

SL

5~2

I

~0
[3,
SL

,-

5~2

,-

I
FIve <;tage IF strip

256

10 "F

1-,

Q,

SL
532

;~0
,

- 0-

532

"

I

-

OUTPUT

f-lON-INV,IW

FEATURES
High Slew Rate: 1l5V/~s

1

/"

the SL541A; and SL541B hove a guaranteed input offset
voltage of ±5V maximum.

•

/-""S"PP,"

10

!-V" SUPPLY

SUPPLY [

COMPENSATION

Ne[

P

NO [

P

FIg. 1

NO

OUTPUT

Pm connectIOns

14 Lead OIL Ceramic

APPLlCATIONS
•

Wideband IF Amplification

•

Wideband Video Amplification

•
•
•
•

Fast Settling Pulse Amplifiers
High Speed Integrators
O/A and A/D Conversion
Fast Multiplier Preamps

ABSOLUTE

MAXIMUM RATING

Supply voltage (V + to V -)

24V

Input voltage (Inv. liP to non inv. liP)
9V
Storage temperature
-55"C to +175' C
Chip operating temperature
+175 'C
Operating temperature'
TO-5: -55"C to +85 'C
OIL: -55"C to +125'C
Thermal resistances
Chip-ta-ambient: TO-5
DIL
Chip-ta-case:
TO-5
DIL

220'C/W
125'C/W
60'C/W
40C/W
Fig. 2

SL541 circuit diagram (TO-5 pin nos.)

257

ELECTRICAL CHARACTERISTICS
Test conditions

(unless otherwise stated)

Tamb=25"C
SL541A
+VCC=15V
-VCC= -4V
Pins 7 and 8 ITO-5) Short circuit
13 ond 1 (DIL)
lUI pin 10 to 3 (T0-5)
lHl pin 4 to 8 (DIL)

SL541B
+VCC=12V
-vce =-6V
Pins 7 ond 8 (T0-5)
13 and 1 (OIL)
Pin 10 ITO-5) Earth
Pin 4 IDIL) Forth

Characteristic

Circuit

Stactic nominal supply current
Input bias current
Input offset voltage
Dynamic open loop. gai n
Open loop temperature coefficient
Closed loop bandwidth (-3d8)
Slew rate (4V peak)
Settling time to-l%
Maximum output voltage

A.S
A,S
A.B
A
A,S
A,B
A,B
A,S

( +ve)

( -vel
( +ve)

-vel

(

Maximum output current
Maximum input voltage

( +ve)

( -vel
( --vel
( +ve)
Supply line' rejection
(

+vP.)

(

-vel

Short circuit

Value
Min.

45

100

5.5

A
A
B
B
A,B

Typ.

Max.

16
7

21
25
5

54
--002
100
175
50
57
-1.9
3.0
-3.0
6.5

2.5
4

A
B
B

-1

A.B
AS

54
46

mA
uA

mY

600 uload

dS

XlO gain
XIO gain

MHz
V!~s

100
-1.5
-2.5

ns

Y
Y
Y
Y
rnA

3

-3

Conditions

dB/"C

5

A

Units

66
54

Y
Y
Y
Y

J

Non
inverting
modes

dB
dB

OPERATING NOTES

Xl0 NON

INVERTING

The SL541 may be used as a norma I, but non
saturating operational amplifier, in any of the usual
configurations (amplifiers, integrators ect.), provided
that the following points are observed:

X3 NON
INVERTING

I

m

;~c~g\J:;'

,

I

,

>0

L- - - '- '- - - .L -~- "- LT t
I

Fig. 3

258

I
I
I

1. Positive supply line decoupling back to the output
load earth should always be provided close to the
device terminals.
2. Compensation capacitros should be connected
between pins 4 and 5. These may have any value
greater than that necessary for
stability without
causing side offsets.
3. The circuit is generally intended to be fed from a
fairly low impedance «lkrJ), as seen from pins 6
and 9-100,Q or less results in optimum speed.
4. The circuit is designed to withstand a certain
degree of capacitive loading (up to 20pF) with
virtually no effect·. However, very high capacitive
loads wi II cause loss of speed due to the extra compensation required and asymmetric output slew rates.
5. Pi n 10 does not need to be co~nected to zero volts
except where the clipping levels need to be defined
accurately w.r.t. zero. If disconnected, an extra ·to.S
volt uncertainty in the clipping levels results, but the
sperotionn remains. However, the supply line rejection
is improved if pin 10 can be left open-circuit.

(

\ !
>::>
o

\V

SLEW RATE OVER
10% TO 85% POINTS
175 Vjus

/~

Cc = Op F
RC=O.f\. -

~

o
>

J \

>

If

l\
\

VOUT

II
VIN

1\.1\

I

I
I)

\
\

t (20ns/DIV)

Fig. 4 Slew fate -XIO non-inverting mode
Input square wave D.4V pip

t (20n s/DIV)
Fig.6

1\
\

J

I

INPUT STEP-

Cc =Op F _
RC =0

I\.

Output clipping levels -XlQ noo- inverting mode
Input moderately overdriven, so thot output goes
into clipping both side

r"\

\

.n

V
~

I

~
o

>

,V

VE

_VEl

1\

tVE (

I

*

t.....

~
o
>

/
/

f-/

+VE

j

V
t (20ns/DtV)
Fig.5 Settling time -XIO non-inverting mode

t (20ns/OIV)
Flg.7 Output clippings levels -X 10 non-inverting mode.
Output goes from clipping to zero volts. Vin=3V

peak step, offset +ve or -ve,

J
Fig.8 Non-ioveniog high speed

x/a amplifier

I

test drcuit., (TO-5 pin nos)

259

Both slew rate and settling time are measures of an
amplifier's speed of response to an input. Slew rate is an
inherent characteristic of the amplifier and is generally
less subiect to misinterpretation than is settling time
which is often more dependent upon the teat circuit
than the amplifier's ability to perform.
Slew rate defines the maximum rate of change of
output voltage for a large step input change and is
related to the full power frequency response (fp) by the
relationship.

s~

2nf,E,

where Eo is the peak output voltage

Settling time is defined as the time elapsed from
the application of a fast input step to the time when the
amplifier output has entered and remained within a
specified error band that is symmetrical about the final
value. Settling time, therefore, is comprised of on initial
propagation delay, an additional time for the amplifier
to slew to the vincinity of some value of output voltage,
plus a period to recover from overload and settle within
the given error band.
The SL541 is tested for a slew rate in a X10 gain
configuration.

260

Fig. 9 Non-saturating sense amplifier (30VI/1s for SmV)
Note: the output may be caught at Q pre-determined
level. (TO-S pin nos.)

•

SL541C

P1essey

SL500 SERIES

Semiconductors

WlDEBAND AMPUFIERS

SL541C & 0
HIGH SPEED VIDEO AMPUFIER

The SL541 C is a monolithic amplifier designed for optimum
pulse response and applications requiring high slew rate with
fast settling time to high accuracy. The high open loop gain
(70dB) is stable with temperature, allowing the desired closed
loop gain to be achieved using standard operational amplifier
techniques. The device has been designed for optimum response
ata gain of 20dB when no compensation is required. The package of the C varient is internally connected to the negative
supply. The 0 varient package (CM10 only) is isolated.

CASE

/' (-VE SlI"Plv)

••
••
•
•

INPUT

Wideband I F Amplification
Wideband Video Amplification
Fast Settling Pulse Amplifiers
High Speed Integrators
DIA and AID Conversion

•••
•

."
SUPPLY

eMl0

Ae

1.

NC2
INVERTINGI!P

3

EARTH

4

-VESUPPlY(V-)

5

10

COMPENSATION

NC

,

,

NC

Fast Multiplier Preamps

FEATURES
•

\

NOhl-lNV

APPLICATIONS

High Slew Rate: 175V/p.s
Fast Settling Time: 1% in 50ns
Open Loop Gain. 70dB
Wide Bandwidth' DC to 100MHz at 20dB
Gain
Very
Low Thermal
Drift:
O.02dB/"C
Temperature Coefficient of Gain

VESUPPLY(V·)

"'1.'__......:'.t OUTPUT
DG14
Fig. 1

Pin connections

5
)(10 NON
INVERTING

-- r- t-N
V

o~

SLEW SETTLING
R~
Cc RATE
1(11 (pFI (V/jJ5)
(ns)

"'E

r-~

"

--

-

lC3 NON
INVERTING

,

*
0

0

"

0

i'.

0

5

0
22

."--

1'-...

I- V k~

.........

,

"

?C

"

50

,

\'\ K

5

'"
'"

,001" '"
"

~

50

5

2210

"

50

5
Xl VOLTAGE
FOLLOWER

--~f--'''''-\

,

\-

5

20

50

50

100

zoo

FREQUENCY (MHz)

Fig. 3

Fig. 2 SL541 circuit diagram (TO - 5 pin nos.)

.

\

.,,

"

15010

Performance graphs - gain v. frequency
(toad - 2kr!//IOpF1
* See operating note 2

261

SL541 C

ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Pin5:+12V
Pin 1: -6V
Pins 7 & 8: Connected together
T amb :25°C
Value

Characteristic

Units

60

Static nominal supply current

Input bias current
Dynamic open loop gain

Open loop temp. co-efficient
Closed loop bandwidth (-3dBI
Slew rate (4V peakl
Settling time to 1%

100
±2.5
4

Maximum input voltage

-

Supply line rejection (pin 51
(pin 11

54
46

Test Conditions

Typ.

Max.

16
7
71
-0.02
100
175
50
±3.0
6.5

21
15

rnA

-

dB
dBtC
MHz
V//ls
ns
V

/lA

100

600>1 Load
xl0gain
x 10 gain

rnA

±3

V
dB
dB

66
54

Non-inverting mode

tVE

\
(',ylR

f----

PQ,,,1,,

~~,F~

/

/

1\
\

''"

1\ \

/
/

"

1\

I)

120n~/DIV!

t

Fig.4

\1/
11\

i

)

'0".

(

(

\

Slew rate - X1D non-inverting mode
t 120ns/OIVj

Fig. 6

Output clipping levels - X 10 non-inverting mode
Input moderatelv overdriven so that ouput goes into
clipping both sides

;NPUl SITEP-----1

i,,"",

f\

I \
\

I"

00

0;

o

o

f\..

>

He

>
o

V
~

V

I

J

V
Settling time - X1D non-inverting mode

'"

t 120ns/DIVj

t 120ns/DIY)

Fig.5

~ r--

/

"

I

Fig. 7

Output clipping levels -- Xl0 non-inverting mode.
Output goes from clipping to zero volts_ Vin = 3V peak

step, offset +ve or -ve.

262

-liE

1\

C.pf

SL541 C

TEST CONDITIONS AND DEFINITIONS
Both slew rate and settling time are measures of an
amplifier's speed of response to an input. Slew rate is an

inherent characteristic of the amplifier and is generally less
subject to misinterpretation than is settling time, which is
often more dependent upon the test circu it than the
amplifier's ability to perform.

5. Pin 10 does not need to be connected to zero volts
except where the clipping levels need to be defined
accurately w.r.t. zero. If disconnected, an extl~ ±0.5 volt
uncertainty in the clipping levels results, but the
separation remains. However, the supply line rejection is

improved if pin 10 can be lett open·circuit.

Slew rate defines the maximum rate of change of output

voltage for a large step input change and is related to the
full power frequency response (fp) by the relationship.
S=21Tf~Eo

where Eo is the peak output voltage

Settling time is defined as the time elapsed from the
application of a fast input step to the time when the
amplifier output has entered and remained within a
specified error band that is symmetrical about the final
value. Settling time, therefore, is comprised of an initial
propagation delay, an additional time for the amplifier to

::r
::r

slew to the vicinity of some value of output Voltage, plus a
period to recover from overload and settle within the given
error band.

The SL541

is tested for slew rate in a X 10 gain

configuration.

Fig.9

Non-saturating sense amplifier (!30Vlp.s for 5mV).
.Note: the output ~ay be caught at a pre-determined level.

(TO - 5 pin nos.)

ABSOLUTE MAXIMUM RATINGS
Supply voltage (V+ to V-)
24V
Input voltage (Inv.i/P to non inv.I/P)
±9V
Storage temperature
-55°C to -+-175 °C
Chip operating temperature
-L 175°C
Operating temperature:
TO - 5 -55°C to +85°C
DIL-55°Cto +125'C

Thermal resistances
Chip-to-ambient: TO DIL
Chip-to-case: TO - 5
DIL

Fifl. 8

5

220 C/W
125'C/W
60'C/W
40'C/W
C

Non-inverting hiqh speed Xl0 amplifier test circuit.

(TO - 5 pin nos.;

OPERATING NOTES
The SL541 may be used as a normal, but non saturating
operational amplifier, in any of the ,usual configurations

(amplifiers, integrators etc.l, provided that the following
points are observed:

1. Positive supply line decoupling back to the output
load earth should always be provided close to the device
terminals.
2. Compensation capacitors should be connected
between pins 4 and 5. These may have any value greater
than that necessary for stability without causing side

offsets.
3. The circuit is generally intended to be fed from a

fairly low impedance (';;;1 kll), as seen from pins 6 and 9
- 100ll or less results in optimum speed.
4. The circuit is designed to withstand a certain degree

of capacitive 10iding (up to 20pF) with virtually no
effect. However, very high capacitive loads will cause
loss of speed due to the extra compensation required
and asymmetric output slew rates.

263

264

Sl550C&D

•

Plessey
Semiconductors

SL500SERIES
WIDEBAND AMPLIFIERS

SL550C &0
LOW NOISE WlDEBAND AMPLIFIER
WITH EXTERNAL GAIN CONTROL

The SL650 is a silicon integrated circuit designed for use

FEATURES

as a general-purpose wideband linear amplifier with remote

gain control. At a frequency of 60 MHz, the SL550C noise
figure is 1,8dS (typ.) from a 200 ohm source, giving good
noise performance directly from a microwave mixer. The

SL550 has an external gain control facility which can be
used to obtain a swept gain function and makes the
amplifier ideal for use either in a linear I F strip or as a low
n~ise

preamplifier in a logarithmic strip.

•
•
•
•

200 MHz Bandwidth
Low Noise Figure
Well-Defined Gain Control Characteristic
25dB Gain Control Range

•
•

40dB Gain
Output Voltage O.8Vp-p (Typ)

External gain control is performed in the feedback loop
of the main amplifier which is buffered on the input and
output, hence the noise figure and output voltage swing are

only slightly degraded as the gain is reduced. The external
gain control characteristic is specified with an accuracy of

±ldS, enabling a well-defined gain versus time law to be
obtained.
The input transistor can

be connected in common

emitter or common base and the quiescent current of the
output emitter follower can be increased to enable low
impedance loads to be driven.

APPLICATIONS
•
•

Low Noise Preamplifiers
Swept Gain Radar I Fs

VARIABLE
GAIN A~P

\fout

I

I

VARIABLE ATTENUATo~- TRACKING WITH ~ARIABLE
GAIN AMP

,

-

-E- -

Ie

5

~ '--v-"
GAIN
CONTROL

CAPACITIVE

LINK

Fig. 1 Pin connections (top view)

lie 16
Fig. 2 Functional diagram

265

SL550C&D

ElECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise stated):
f=30MHz Vs
c 6V, RL
2000, Ie ~ 0, R1
c

c

7500,

Tamb

c.

+

25 C
c

Value
Characteristic
Voltage gain
Gain control characteristic

Gain reduction at mid-point
Max. gain reduction
Noise figure

Output voltage
Supply current

Gain variation with supply
voltage
Upper cut-off frequency
(-3dB wrt 30MHz)
Gai n variation with temperature (see note 2)

Circuit

Min.

SL550C
SL550D
Both
SL550C
SL550D
SL550C
SL550D
SL550C
SL550C
SL550D
Both
Both
SL550C
SL550C
SL550D

39
35

Typ.

Max.

42
44
40
45
See note 1
11
9
10
9
20
25
25
2.0
2.7
3.5
3.0
0.15
0.3
11
13
15
11
20

Units

Conditions

dB
dB
db
dB
dB
dB
dB
dB
dB
Vrms
Vrms
mA
mA
mA

Ie ~ 0.2mA
Ie ~ 0.2mA
Ie ~ 2.0mA
Ie - 2.0mA
Rs ~ 2000
Rs ~ 500
Rs .c 2000
00
R1
R1 - 7500
R1 ~OO
R1 ~. 7500
R1 ~CO
Vs

Both

0.2

dBN

Both

125

MHz

Both

::,:3

dB

~

6 to 9V

Tamb ... -55 to

~ 1 25'C

NOTES
1. The external gain control charactenstic IS specified In terms of the gain reduction obtained when the control current (I c)
zero to the
current
2. This can be
by uSing an alternative Input configuration (see operating note 'Wide Temperature Range')

t'WEECON" TYPE CAPACITORS)
SEE OPERATING NOTE

Fig. 3

266

Test circuit

Fig. 4

Frequency response

IS

increased frorn

Sl550C&D

OPERATING NOTES
Input Impedance
The input capacitance, which is typically 12pF at
60MHz, is independent of frequency. The input resistance, which is approximately 1.5k at 1 OMHz, decreases
with frequency and is typically 500 ohms at 60MHz
Control Input

Maximum output current is 2 mA peak and the output
impedance is 350U.
Wide Temperature Range
The gain variation with temperature can be reduced at
the expense of noise figure by including an internal 30U

resistor in the emitter of the input transistor. This is

Gain control is normally achieved by a current into pin
2. Setween pin 2 and ground is a forward biased diode and
so the voltage on pin 2 will vary between 600 mV at Ie =
1 IlA to 800 mV at Ie = 2 mAo The amplifier gain is varied
by applying a voltage in this range to pin 3. To avoid
problems associated with the sensitivity of the control

achieved by decoupling pin 13 and leaving pin 12
open·circuit. Gain variation is reduced from ±3dB to ±1dB
over the temperature range -55°C to +125°C (Figs. 6 and 7)
low Input Impedance

voltage and with operation over a wide temperature range
the diode should be used to convert a control current to a
voltage which is applied to pin 3 by linking pins 2 and 3.

A low input impedance (~25U) can be obtained by
connecting the input transistor in common base. This is
achieved by decoupling pin 11 and applying the input to
pin 12 (pin 13 open-circuit).

Minimum Supply Current

High Frequency Stability

If the full output swing is not required, or if high
impedance loads are being driven, the current consumption
can be reduced by omitting R, (Fig. 3). The function of R,

Care must be taken to keep all capacitor leads short and
a ground plane should be used to prevent any earth

is to increase the quiescent current of the output emitter

The 30U resistor (pin 14) shown in the test circuit
eliminates high frequency instabilities due to the stray
capacitances and inductances which are unavoidable in a
plug·in test system. If the amplifier is soldered directly into
a printed circuit board then the 30U resistor can be
reduced or omitted completely.

follower.
High Output Impedance
A high impedance current output can be obtained by
taking the output from pin 6 (leaving pin 7 open-circuit).

--

inductance common between the input and output circuits.

T
9dS min
11dB max

~9dB

rr"

0

z "r-----4_--i__t_t-t_rrr~----_r--4__i_i_t_rrr~~~~~---i--i-i-'~'"~B~mfO'n

:;

.....

I
IOyA

CONTROL CURRENT

(Ie)

/267

SL550C&D

p

;;4'0

I

I+----1--t----+------+--f-------I--

"

1-+-+1

Fig. 7

Voltage gain v. temperature (pin 13 decoup/ed for improll

gain variation with temperature - see operating notes).
Fig. 6 Voltage gain v. temperature (pin 12 decoupled, standard
circuit configuration).

Fig.S Typical noise figure (SL550C)

Fig. 9

Input and output impedances (Vs
e

~oo

jwo
,e;

'"

~

;co

'-1";

,e;

'"

0>

."

"

5

'Ie
lR12

'-----

~

CO

TRfI

f--<>'

~

,eo

9

TRV

",Y
30

"

5<"

'"'

"

"

"

TR13

'c

fe;,
t
"

Fig. 10 Circuit diagram

268

"

c;

TRII.

H}

l

;0

" "

~

J;oo

0;

'"

"

.---

f----

eoo

5

,

c<

,

=6VJ

Sl550e&D

APPLICATION NOTES
A wideband high gain configuration using two SL550s
connected in series is shown in Fig. 11. The first stage is
connected in common emitter configuration, whilst the

second stage is a common base circuit. Stabl!: gains of up to
65 dB can be achieved by the proper choice of Rl and R2.
The bandwidth is 5 to 130 MHz, with a noise figure only
marginally greater than the 2.0 dB specified for a single

stage circuit.

"
Fig. 13 Linear swept gain circuit

CAIN

VOLTAGE
GAIN

L~?
Fig. 14 Square law swept gain circuit.
ALL CAPACITORS

1000 I'F

Fig. 11 A two-stage wideband amplifier

A voltage gain control which is linear with control
voltage can be obtained using the circuit shown in Fig. 12.
The input is a voltage ramp which is negative going with
respect to ground. The output drives the control current
pins 2 and 3 directly (see Fig. 13). If two SL550s in the
strip are controlled as shown in Fig. 14, with a linear ramp
input to the linearising circuit, a fourth power law (power
gain v. time) will be obtained over a 50 dB dynamic range.

h--,---=---<>'1S .. +6\1

All capacitors 10nF
Gain 46dB
Noise figure 2.0dB (RS = 2000)
Output power I 5dBm (Rl = 500)
Frequency response as SL550C
Dynamic range 70dB (1 MHz bandwidth)
Fig.15 Applications example of wide dynamic Tange: 50 0

load amplifier with AGe using SL500 series integrate a
ClfGuit.

ABSOLUTE MAXIMUM RATINGS

Fig. 12 Gain controllinearising circuit.

Storage temperature
Ambient operating temp.
Max. continuous supply
Voltage wrt pin 1
Max. continuous AGe current
pin 2
pin 3

_55°e to +150 o e
-40o e to +125°e
+9V
10mA
lmA

269

270

SL560C

•

Plessey
Semiconductors

SL500 SERIES

1641 Kaiser Avenue,
Irvine, CA. 92714

WIDEBAND AMPUFIERS

SL560C
300 MHz LOW NOISE AMPUFIER
This monolithic integrated circuit contains three very
high performance transistors and associated biasing
components in an eight-lead TO-5 package forming a
300 MHz low noise amplifier. The configuration employed permits maximum flexibility with minimum use of
external components. The SL 560C is a general-purpose
low noise, high frequency gain block.

INPUT-

51lnAPPlJCATIONS

I

INPUJ-

COMMON EMITTER
CONFIGURATION

FEATURES
(Non-simultaneous)

GAIN SET

20

0"

-OUTPUT CURRENT SET

/

I

'cc

•
•

Gain up to 40 dB
Noise Figure LessThan 2 dB (RS 200ohm)

•
•

Bandwidth 300 MHz
Supply Voltage 2-15V (Depending on
Config u ration)

•

Low Power Consumption

eM8
Fig. 1 Pin connections (viewedfrombeneath)

APPLICATIONS
•
•
•
•
•

Radar I F Preamplifiers
Infra-Red Systems Head Amplifiers
Amplifiers in Noise Measurement Systems
Low Power Wideband Amplifiers
Instrumentation Preamplifiers

•
•
•

50 ohm Line Drivers
Wideband Power Amplifiers
Wide Dynamic Range RF Amplifiers

Fig. 2 SL560C circuit diagram

+Vcc

/'''-"
I
I

'-~
'IP

Fig. 3 PC layout for 50-

o line driver (see Fig. 6)

271

SL560C

ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise stated):
Frequency 30 MHz
Vee 6V
Rs ~ RL ~ 500
TA ~ 25'C
Test Circuit: Fig. 6

Value
Characteristic

Small signal voltage gain
Gain flatness
Upper cut-off frequency
Output swing

Units
Min.

Typ.

Max.

11

14
:1:1.5
250
+7
+11
1.8
3.5
20

17

,5

Noise figure (common emitter)
Supply current

30

dB
dB
MHz
dBM
dBm
dB
dB
mA

Conditions

10 MHz - 220 MHz
Vee ~ 6V 1
See Fig. 5
Vee ~ 9V J
Rs ~ 2000
Rs ~ 500

CIRCUIT DESCRIPTION
Three high performance transistors of identical geometry are employed. Advanced design and processing
techniques enable these devices to combine a low base
resistance (Rbb') of 17 ohms (for low noise operation)
with a small physical size - giving a transition frequency, fT, in excess of 1 G Hz.
The input transistor (TR1) is normally operated in
common base, giving a well defined low input impedance. The full voltage gain is produced by this transistor and the output voltage produced at its collector is
buffered by the two emitter followers (TR2 and TR3).
To obtain maximum bandwidth the capacitance at the
collector of TR1 must be minimised. Hence, to avoid
bonding pad and can capacitances, this point is not
brought out of the package. The collector load resistance
of TR1 is split, the tapping being accessible via pin 5. If
required, an external roll-off capacitor can be fixed to
this point.
The large number of circuit nodes accessible from the
outside of the package affords great flexibility, enabling
the operating currents and circuit configuration to be
optimised for any application. I n particular, the input
transistor (TR1) can be operated in common emitter
mode by decoupling pin 7 and using 6 as the input. In
this configuration, a 2 dB noise figure (Rs 2000) can
be achieved. This configuration can give a gain of 35dB
with a bandwidth of 75 M Hz (see Figs. 8 and 9)or, using
feedback, 14 dB with a bandwidth of 300 M Hz (see Figs.
10 and 11).
Because the transistors used in the SL 560C exhibit a
high value of fT, care must be taken to avoid high
frequency instability. Capacitors of small physical size
should be used, the leads of which must be as short as
possible to avoid oscillation brought about by stray
inductance. The use of a ground plane is recommended.

272

-I
_

m

0,

--IJ---o

INPUT

T -

--II
Gain 13dB
Power supply current 3mA

Bandwidth 125 MHz
Noisefigure2.5dB (RS=200Q)
FREQUENCY

(MHz)

Fig. 13 Frequency lesponse of circuit shown in Fig. 12

ABSOLUTE MAXIMUM RATINGS
Supply Voltage Vee
(Pin4 w.r.t. Pin 1)
Storage Temperature
Operating Temperature

274

+15 volts
-55"C to + 150"C
-55'C to +125'C

Fig. 14 Low power consumption amplifier

SL561C

•

Plessey
Semiconductors

SL500 SERIES

1641 Kaiser Avenue,
Irvine, CA. 92714

WIDEBAND AMPUFIERS

SL561C
ULTRA LOW NOISE PREAMPLIFIERS
This integrated circuit is a high gain, low noise
preamplifier designed for use in audio and video systems
at frequencies up to 6M Hz. Operation at low frequencies
is eased by the small size of the external components
and the low 111 noise. Noise performance is optimised
for source impedances between 200 and 1 kO making
the device suitable for use with a number of transducers
including photo-conductive I R dete'ctors, magnetic tape
heads and dynamic microphones.

DP8
Fig. 1 Pin connections (viewed from the top)

APPLICATIONS
•

Audio Preamplifiers (low noise from low
Impedallce soulce)

•
•

Video Preamplifier
Preamplifier for use
Systems

In

FEATURES
•

Low Cost Infra-Red

••
•

60dB
High Gain
Low noise
0.8nV NHz (Rs 500)
Bandwidth
6MHz
Low Power Consumption 1 OmW (Vcc~ 5V)

ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Vcc
5V
Source impedance 500
Load impedance 10kO

25°e

Tamb

Characteristic
Min.
Voltage gain

57

Equivalent input
noise voltage

Supply current
Bandwidth

60

Units
63

3
15
50
2

3
2
6

Conditions

Max.

0.8

Input resistance

Input capacitance
Output impedance
Output voltage

Value
Typ.

Pin 6

nVv'Hz
kO
pF

100Hz to 6MHz

0
V pop
3

Ole

dB

See note 4

mA
MHz

275

SL561 C

OPERATING NOTES
1. Upper cut-off frequency
The bandwidth of the amplifier can be reduced from
6MHz to any desired value by a capacitor from pin 6 to
ground. This is shown in Fig. 5. No degradation in
noise or output swing occurs when this capacitor is
used. The high frequency roll off is approximately 6dB/

octave.
2. Low frequency reponse
The capacitors C2 and C3 (Fig. 4) determine the
lower cut-off frequency. C2 decouples an internal
feedback loop and if its value is close to that of C3 an
increase in gain at low frequencies can occur. For a
flat response make 0.05 C3 > C2> 5C3.
3. Gain set facility
Provision is made to adjust the gain by means of a
resistor between pin 6 and the output. Gains as low as
1 OdB can be selected. This resistor increases the feedback around the output stage and stability problems can
result if the bandwidth of the amplifier is not reduced as
indicated In Note 1. Fig.6 shows recommended values
of Cl for each gain range. Since the input stage is a

common emitter stage without emitter degeneration
(for best noise) at values of gain less than 40dB this
input stage, rather than the output stage, determines
the maximum output voltage swing. For a distortion of
less than 10% the input voltage should be restricted to
less than 5m V.
4. Driving low impedance loads
The quiescent current of the output emitter follower
is 0.5mA. If larger voltage swings are required into low
impedance loads this current can be increased by a
resistor from pin 8 to ground. To avoid exceeding the
ratings of the output transistor the resistor should not
be less than 2000.
5. Noise performance
The equivalent input voltage for the amplifier is
shown in Fig.7. From this the input noise voltage and
current generators can be derived. They are:en- 0.8nV/VHz
in 20pA/VHz
Flicker or 11f noise is not normally a problem, the knee
frequency being typically below 100Hz.

r---r--~---r--~----<>'CC

8
OUTPUT

3
'---.4---J_ _--4._+--J+_--<_~EARTH

6
GAIN seT

Fig. 2 Circuit diagram

Lr-,IIr--'C--'" OUTPUT
C3
INPUT

~

RSET

'"
'----------+---<>
Fig. 3 Test circuit

276

Fig. 4 Typical application

GNO

SL561C

+ffi
l.L c; =~ 1,61~F

60

f-

56

C3

ljJF

52

III

48

lill

100

Ik

Cl=4-7nF

Jill
10k

50

Fffl
~\~l~"O~F
~riffi
lOOk

I

l-

50

O,F

V

20pF

U

,
z

30

I OM

O~

FREQUENCY (Hz)

Fig. 5 Gain v. frequency

47 pF

t-H

0

LIMITED DIP VOLTAGE

--I

AND BANDWIDTH) ~~OTE 31

200pF
_

--

1

0
10k
RSET (Ohms)

Ik

100

lOOk

1M

Fig. 6 Gain v. R set

I

~J

---

~

c---

-

---

II

I
---

r--=

/

~
I

f------ ----I

I
SOURCE

RESISTANCE 1.0.1

Fig. 7 Noise v. source impedance

277

278

SL611C SL610C SL612C

•

Plessey
Semiconductors

SL600 SERIES
COMMUNICATIONS CIRCUITS

SL610C, SL611C & SL612C
RF/IF AMPLIFIERS
The SL610C and SL611 C are low noise, low distortion, R F voltage amplifiers with integral supply line
decoupling and AGC facilities. The SL610C has a voltage gain of 10 and a bandwidth of 140MHz, while the
SL611C has a voltage gain of 20 and a bandwidth of 100MHz. Both circuits have a 50dB AGC range with
maximum signal handling of 250mV rms. As they are voltage amplifiers they have high input impedance
and low output impedance.

r----------r--------r---...,...--r-----!:=---,----02 SUPPLY
100

'0

1000,

7.0

"25k

t----+-----~f--<> 1 OUTPUT

SO.

"2p
(ZERO)

I.
INI'UT

•

1 AGe

m

110

P'2k)

BIAS

•

"

so

,
EARTH 1

200,

100
t621

.00
L . - - - - -_ _ _ _ _ _ _ _ _ _ _

~

_ _ _ _ _ _ _ _-<>8 EARTH 2

F;g. 1 Circuit diagram of SL610Cand SL611C
(Component values in parentheses refer to 5L611 C)

The SL612C is a low noise,low distortion,lF voltage amplifier similar to the SL610C and SL611C bul
having a voltage gain of 50, a bandwidth of 15MHz and only 20mW power consumption. It has a 70dB
AGC range with maximum signal handling of 250mV rms.

279

Sl610C SlS'11C SlS12C

,..

4-lk

J

.

.)

11"k

U

2 SUPPLY

10000

---

100

~

,
EARTH'

17k

51

~

8 EARTH 2

Fig. 2 Circuir diagram of SL612C

ELECTRICAL CHARACTERISTICS
Test conditions:

Supply voltage = 6V
Temperature = +25°C (unless otherwise stated)
Pins 5 and 6 strapped together
AGC not applied unless specified.

Value

Characteristic
Voltage galO

Cut·off frequency
(-3dB)
(See Fig. 9)
Noise Figure

Max. input signal
(1% cross modulation)

No AGC appl ied
Max. input signal
(1 % cross modulation)
Full AGC applied
AGC range
(See Fig. 10)

AGe current

Qu iescent current
consumption

Change of voltage

.
.

gain with temperature

Change of AGC range
with temperature

Circuit

Min.

TVp.

Max.

Units

SL610C
SL611C
SL612C
SL610C
SL611C
SL612C
SL610C
SL611C
SL612C
SL610C
SL611C
SL612C
SL610C
SL611C
SL612C
SL610C
SL611C
SL612C
SL610C
SL611C
SL612C
SL610C
SL611C
SL612C
All
types
All
types

18
24
32
85
50
10

20
26
34
140
100
15
4
4
3
100
50
20
250
250
250
50
50
70
0.15
0.15
0.15
15
15
3.3

22
28
36

dB
dB
dB

40
40
60

0.6
0.6
0.3
20
20
5

Test Conditions

MHZ}
MHz
MHz
dB
dB
dB
mVrms
mVrms
mVrms
mVrms
mVrms
mVrms
dB
d8
dB
mA
mA
mA
mA
mA
mA

}
}

30MHz } Source = 25n
30M Hz
Load R;;' 500n
1.75MHz
Load C< SpF
Source = 25n
Load R;;' 50 on
Load C< 5pF
Source = 300n, f = 30MHz
Source = 300n, f = 30MHz
Source = 800n, f = 1.75MHz
Load 150n, f = 10MHz
Load 150n, f = 10MHz
Load 1.2kn, f = 1.75MHz
f = lOMHz
f = 10MHz
f = 1.75MHz

AGC Voltage

= 5.1V

Output open circuit

±1

dB

-55°C to +125°C

±2

dB

_55°C to +125°C

*from nominal

Gain and frequency response of these circuits are relatively independent of supply voltage within the range 6 -

280

9V

SL610C SL611C SL6121

OPERATING NOTES
The SL610C, SL611C and SL612C are normally used
with pins 5 and 6 strapped. A slight improvement in noise
figure, and an increase in the LF input impedance may be
obtained by making the necessary AC connection via the
earthy end of an input tuned circuit in the conventional
manner.

v,

I, _
0" t 12 °12
\'2 - \'1 021 t 12 G22

Fig. 3 Defin;tion of G par.",.ters

The characteristics of these units have been expressed
in G parameters which are defined as shown in Fig. 3.
These parameters oorrespond to the normal operation
of a voltage amplifier which is usually operating into a load
much higher than its output impedance and from a source
much lower than its input impedance. Hence the input
admittance (Gil) and voltage gain (G'I) are measured with
open circuit output, and the output impedance (G,,) with
short circuit input. The parasitic feedback parameter is the
current transfer (G 12) i.e. the current wh ich flows in a
short circuit across the input for a given current flowing in
the output circuit.
Since the effects of G" are small for reasonable
values of load and source impedance, the approximate
equivalent circuit given in Fig. 4 may be used.
Hence the typical effects of applying finite load and
source impedances, real or complex, may be evaluated by
the use of the graphs showing the values of the major
parameters versus frequency. At lower frequencies the
limitation on ZL is dependent upon output signal; for
maximum output Z L = 100rl.

F;g_ 4 Amplifier equivalent circuit

Stability
Both the input admittance G I I and the output
impedance G 22 have negative real parts at certain
frequencies. The equivalent circuits of input and output
respectively are shown in Fig. 5 and 6 and the values of
Rin, Rout, Cin and Lout may be determined for any
particular frequency from the graphs Fig. 7 and B. It will be
seen that, for the SL610C and the SL611C Rin is negative
between 30 and 100MHz, and Rout is negative over the
whole operating frequency range. For the SL612C, Rin is
not negative and Rout is negative only below 700KHz.
It is evident that if an inductive element having
inductance L1 and parallel resistance R 1 is connected
across the input, oscillation will occur if Rin is negative at
the resonant frequency of Cin and L1, and R 1 is higher
than Rin.
Similarly, if a capacitor C1 in series with a resistance
R2 is connected across the output oscillation will occur if,
at the resonant frequency of Lout and C1, Rout has a
negative resistance greater than the positive resistance R2.
Where the input may be inductive, therefore, it may be
shunted by a resistor and where the load may be capacitive
47r2 should be placed in series with the output.
These devices may be used with supplies up to .+9V
with increased dissipation.
The AGC characteristics shown in Fig . . 8 vary
somewhat with temperature: a preset potentiometer should
not, therefore, be used to set the gain of either of these
circuits if gain stability is required.

Fig. 6 Output circuir

Fig. 5 Input circuit

Uill

I
~'"

CONOUCT ANeE

,

SUSCEPTANCE - - -

ru"

ILlIG(

,

SUIZC

"

l--

sun

~

SUI2'C

ABSOLUTE MAXIMUM RATINGS
Storage temperature range
Operating temperature range
Chlp-to-ambient thermal resistance
Chip-ta-case thermal resistance
Supply voltage

_55°C to +150°C
_55°C to +125°C
220 u C/W
60°C/W
12V

"

..

FREQUENCY (MHz,

Fig_ 7 Input admittance with ole output (G 11)

281

SL610C SL611 C SL612C

IlIlOt

--

L'"C

RESIstANCE - -

,

"'"crANCE - - -

"

.....

1'.
V

.

,

1111 !

1 1Ulll1

"'112<:

'\.

o

IllllC

"

IlInc

--

:

I'\.
,,-,

I/SL61O,,1,e

Sl612CI\

7

a'Mlc

,

I

'- 1-1-'

,

,I

FREQUENCY (MHz)

Fig. 11 Reverse current transfer ratio fG 12)

FREQUENCY (MHz)

Fig. 8 Output impedance with sic input fG 12 )

iii

"

30

Z

~

-

SL&12C

"\.
Slll1C

,

.....

SL'lac

\
\

,,

"

FREQUENCY (MHz)

Fig. 9 Voltage gain f6 21)

r--.,

\
\
SL,,2

SLIIO,llI

\

TYPICAL
MAX.
TEMPERATURES rC)

FREE

AIR

OPERATING

Supply

Voltage

-00

9V

6V

12V

AGC

"I
20

AGe

Full

None

Full

153

129

118

58

SL612C

171

158

165

129

Voltage

None
-

Full

-

SIGNAL (VI

Fig. 10 AGe characteristics

282

None

SL610C/611C

149

69

SL613C

•

Plessey
Semiconductors

SL600 SERIES
COMMUNICATIONS CIRCUITS

SL613C
LIMITING AMPLIFIER/DETECTOR

The SL613C is a low noise limiting amplifier intended
for use as an RF clipper, a limiting stage in IF amplifiers, or
an RF Compressor in SSB transmitters. It contains a
detector which may be used to detect AM but is
particularly intended for use as an AGe detector. The
amplifier, which has a gain of 12 dB when not limiting, has
upper and lower 3 dB points of 150 MHz and 5 MHz
respectively. It limits when its input exceeds 120 mV r.m.s.
The detected output during limiting is 1 mAo

FEATURES
•

Wide Bandwidth

•
•
•

Low Noise
Highly Symmetrical Limiting
Large Signal Handling Capability

APPLICATIONS
•
•
•
•

RF Clippers
AGC Systems
AM Detectors
RF Compression in SSB Transmitters

eM8
Fig. 2 Pin connections

Fig. 1 Circuit diagram

ELECTRICAL CHARACTERISTICS
Test Conditions
Supply
+6V
Temperature
+25°C
Pins 6 & 7 strapped together

Value
Characteristic

Voltage gain
Upper 3 dB frequency
Lower 3 dB frequency

Min.

Typ.

3.3
120

4
150
5
4.5
15
1.25
1
1.75
5kn + 6pF

Noise ,figure
Supply current

Limited R F alp
Detector current
Maximum input before overload

Input impedance

11
0.85
1.5

Max.
4.6
8
5.5
20
1.25

Conditions

Units

MHz
MHz
dB
mA
V p.p
mA
V r.m.s.

30 MHz

60 MHz 500n sou rce
No signal

0.5 V input, 30 MHz
0.5 V input, 30 MHz
30 MHz
60 MHz. Open circuit alp

283

SL613C

OPERATING NOTES
The SL613C, like the SL610/11/12, is normally used

is envisaged a resistor should be connected between the

with the input and bias pins connected directly together

output pin and the load. Normally 50r! is sufficient. The
output should be isolated at DC by a capacitor.

and the input applied through a capacitor. However, and

again like the SL610(11/12, the bias may be decoupled and
connected to the 'cold' end of a coil or tuned circuit, the
input pin being connected to its 'hot' end or to a tap.

The supply rail is decoupled internally at RF but as
the gain is dependent on supply voltage there should no
appreciable LF ripple on the supply. Two separate earth
connections are made in order to minimise the effects of
common earth-lead inductance - such common earth-lead

inductance can cause instability and care should be taken
not to introduce it externally.

The RF output is capable of driving a load of 1 kr! in
parallel with 10pF. If a capacitive load of more than 10pF

284

The detected output consists of a current out of
pin 4, ~hich is an NPN transistor collector. This pin must
always be more than 3 volts more positive than earth, even
if the detected output is not required (in which case it is

best to strap pins 2 and 41.

ABSOLUTE MAXIMUM RATINGS
Storage temperature

~30oe to

Operating temperature

-30o e to +70 e

Supply voltage (pins 2 or 4)

+9V

+85'e
0

SL1620C SL1621C

•

SL600 SERIES

Plessey
Semiconductors

COMMUNICATIONS CIRCUITS

SL620C & SL621C
AGC GENERATORS
The SL621C is an AGC generator designed specifically for use in SSB receivers in conjunction with the
SL610C, SL611C and SL612C RF and IF amplifiers. In common with other advanced systems it generates
a suitable AGC voltage directly from the detected audio waveform, provides a 'hold' period to maintain the
AGC level during pauses in speech, and is immune to noise interference. In addition it will smoothly follow
the fading signals characteristic of HF communication.
When used in a receiver comprising one SL610C and one SL612C amplifier and a suitable detector, the
SL621C will maintain the output within a 4dB range for a 110dB range of receiver input signal.
The SL620C VOGAD (Voice Operated Gain Adjusting Device) is an AGC generator designed to work
in conjunction with the SL630C audio amplifier (particularly when the latter is used as a microphone
amplifier) to maintain the amplifier output between 70mV and 87mV rms for a 35 dB range of input. A
one second 'hold' period is provided which prevents any increase of background noise during pauses in
speech.
1 - - - - - - - - - - - - - - - - - - - - - - - - - - - -------,+6V
4
165.,

10k

95k

I NP UT 1 c----C::J--T~

I

(/'j~kJ

I
I
I
I

I
I
I
I

(111k)

+6k

TRlO
TRIS

TRlt.

I

10k

I

(25k)

llk

I
I
I

7·5k

200

J. CJ

OUTPUT 20-----------

I

D3

I
I

10 10k

T' OO "

TR11

TR13

D'

200

800

I

I

L _____________ _
C1

(2

TSO\.!

T1Oo\.!

eMS

Fig. 1 Circuit diagram of SL620C and SL621 C (Component values in brackets refer to SL620C)

285

SL620C. SL621 C

DESCRIPTION
The operation of the SL621C is described with
reference to the circuit diagram, Fig. 1, and Fig. 2 which
illustrates the dynamic response of a receiver controlled by

the SL621C.
The SL621C consists of an input AF amplifier TR1 TR4 (3 dB point: 10KHzI coupled to a DC output
amplifier, TR16 - TR19, by means of a voltage back-off
circuit, TR5 and two detectors, TR14 and TR15, having
short and long rise and fall time constants respectively.

The detected audio signal at the input will rapidly
establish an AGC level, via TR 14, in time t, (see Fig. 21.
Meanwhile the long time constant detector output will rise
and after 13 will control the output because this detector is
the more sensitive.
Fig. 2 Dynamic response of a system
controlled by SL620C or SL621C AGC generator

If signals exist at the SL621 C input which are greater
than approximately 4mV rms they will actuate the trigger
circuit TR6 - TR8 whose output pulses will provide a
discharge current for C2 via TR 10, TR 13.
By this means the voltage on C2 can decay at a

OPERATING NOTES
The various time constants quoted are for C1 ~ 50llF
and C2 ~ C3 ~ 1OOIlF. These time constants may be altered

maximum rate, which corresponds to a rise in receiver gain

of 20 dB/s. Therefore the AGC system will smoothly follow

by varying the appropriate capacitors.
An input coupling capacitor is required. This should

signals which are fading at this rate or slower. However,

input to the AGC generator will drop below the 4mV rms

normally be 0.331lF for an SL621C and about 11lF for an
SL620C.
Fig. 3 shows how the SL621C may be connected into

threshold and the trigger will cease to operate. As C2 then

a typical SSB receiver.

has no discharge path, it will hold its charge (and hence the
output AGC levell at the last attained value. The output of

Fig. 4 shows how the SL620C is used to control the
gain of the SL630C audio amplifier. The operation of the
SL620C is exactly the same as that of the SL621 C and the

should the receiver input signals fade faster than this, or
disappear completely as during pauses in speech, then the

the short time constant detector will drop to zero in time

t2 after the disappearance of the signal.
The trigger pulses also charge C3 via TR9, so holding
off TR12 via TR11. When the trigger pulses cease, C3

diagram showing the dynamic response of the closed loop

system, Fig. 2, is equally applicable to the SL630C/SL620C
combination. Again, the time constants may be altered by
varying the capacitor values.
The supply must either have a source resistance of

discharges and after t5 turns on TR 12. Capacitor C2 is

discharged rapidly (in time t41 via TR12 and so full receiver

less than 2D. at LF or be decoupled by at least 500llF so

gain is restored. The hold time, ts is approximately one

second with C3

~

1001lF. If signals reappear during t s , then

that it is not affected by the current surge resulting from a

C3 will re-charge and normal operation will continue. The
C3 re-charge time is made long enough to prevent

sudden input on pin 1. The devices may be used with a
supply of up to +9V.
In a receiver for both AM and SSB using an SL623C
detector/Carrier AGC generator, the AGC outputs of the
SL621C and SL623C may b,e connected together provided
that no audio reaches theSL621 C input while the SL623C

prolongation of the hold time by noise pulses.
Fig. 2 shows how a noise burst superimposed on
speech will initiate rapid AGC action via the short time
constant detector while the long time constant detector
effectively remembers the pre-noise AGC level.

is controlling the system.

AGC lines may require some RF decoupling but the
total capacitance on the output of an SL620 or SL621
should not exceed 15000pF or the impulse suppression will
suffer.

RF

AF

INPUT

OUTPUT

:,
L ________________

,

~

Fig. 3 SL621C used to control SSB receiver

286

SL620C SL621 C

0'0021-1
,----------r-----~~+6V

C2
400 TO

MICROPHONE OR

TRANSFORMER

1000~

L..,.",---r..J'iDl-

289

Sl622C

OPERATING NOTES
The SL622C incorporates a series regulator which will
accept supply voltages between 6V and 12V and provides a
supply line rejection of approximately 26 dB when
operated from a 6V supply The supply line immunity
increases with supply voltage.
The input stage is a differential class A-B stage with
an AGe terminal. The accurate balance of the input stage
give an overall common-mode rejection ratio of greater than
30 dB.
Typically the amplifier will handle differential input
signals of up to 375mV pop and unbalanced signals of up to
50mV Pop. When used in the unbalanced mode either pin 5
or pin 6 may be used as the input, the other being
decoupled to earth.

y- /
10

>"

/

/

V

/

(m .... )
RG - JOOchmS

Fig. 3 Sidetone output characteristics.

r-------------~~~~~
r--------+--~
4-7 VOLT

~---r---~ STABILISED

LINE

f---o

cs

SIDE TONE
OUTPUT

/

V

1/
10
100

0'01

1000

tmV)

Fig. 2 Connection diagram for SL622C used as a microphone
amplifier.

Fig. 2 shows the SL622C when used as a balanced
microphone amplifier. The LF cut-off of the amplifier is set
by C1 - and also by the values of coupling capacitors to
the input pins (pin 5 and pin 6); coupling capacitors should
be used if the d.c. potential of the input is not floating with
respect to earth.
The HF cut-off is set by C2_ The VOGAD threshold
may be increased by connecting an external conductance
between pins 8 and 9. The threshold is increased by
approximately 20 dB for I millimho of conductance, the
value of C2 should be adjusted in conjunction with any
threshold alteration in order to obtain the desired
bandwidth.
C3 and R I set the attack and decay rates of the
VOGAD. C3 = 47.uF and Rl = IMohm gives an attack time
constant (gain increasing) of 20 millisecs and a decay rate
of 20 dB/sec. Cl = 2.2.uF and C2 = 4.7nF give a 3 dB
bandwidth of approximately 300Hz to 3kHz.
The amplifier can be muted by applying +4V to pin
10, but when the voltage is removed either C3 must be
discharged or there will be an appreciable delay before the
circuit functions normally again.
C4 is used for R F decoupling of the stabilised line_
AF decoupling may be applied to improve supply line
rej!j!ction and sidetone linear ity.
The VOGAD and sidetone steady-state transfer
characteristics are shown in Figs. 3 and 4.

290

RIO .. 300 ohms

Fig. 4 VOGAD - output characteristics (1kHz sinewave input).

Pin
1
2
3
4

~}
7
B

9
10

Function
+6 volts supply
AC_ coupling
+4.7V decoupling
Sidetone o/p
Balanced signal input
OV
HF Roll off
AF o/p
VOGAD time constant.

ABSOLUTE MAXIMUM RATINGS
Continuous supply voltage (positive)

Storage temperature
Ambient temperature

(6Voperating)
( 12Voperating)

12V ± 0.5V
_55°C to + 175°C
-55°C to + 125°C
_55°C to + 100°C

SL623C

•

Plessey
Semiconductors

SL600 SERIES
COMMUNICATIONS CIRCUITS

SL623C
AM DETECTOR, AGC AMPLIFIER & SSB DEMODULATOR
The SL623C is a silkon integrated circuit combining
the functions of low level, low distortion AM detector and
AGe generator with SSB demodulator. It is designed
specially for use in SSB/AM receivers in conjunction with

5"
AUDIO

SL610C, SL611C and SL612C RF and IF amplifiers. It is
complementary to the SL621 C SSB AGC generator.
The AGC voltage is generated directly from the

6 VOLT

detected carrier signal and is independent of the depth of
modulation used. Its response is fast enough to follow the
most rapidly fading signals. When used in a receiver

comprising one SL610C and one SL612C amplifier, the
SL623C will maintain the output within a 5 dB range for a
90 dB range of receiver input signal.
The AM detector, which will work with a carrier level
down to 100 mV, contributes negligible distortion up to

90% modulation. The SSB demodulator is of single
balanced form. The SL623C is designed to operate at
intermediate frequencies up to 30MHz. In addition it
functions at frequencies up to 120MHz with some
degradation in detection efficiencies. The encapsulation is a
10 lead TO-5 package and the device is designed to operate
from a 6 volt supply, over a temperature range of _55°C to

eM10
Fig. 1 Block Diagram

+125°C.

ELECTRICAL CHARACTERISTICS@ SUPPLY

=

+6V, Tamb

=

+ 25°C

I

Value
Characteristic

SSB Audio Output

Min.

Typ.

Max.

Units

25

30

42

mVrms

Test Conditions

Signal Input 20mV rms @ 1.748
MHz. Ref. Signal Input 100mV rms
1.750 MHz
Signal Input 125mV rms @ 1.75
MHz. Modulated to 80% @ 1 kHz.
Initial signal input 125mV rms at
1.75 MHz. Mod. to 80% at 1 kHz
Output Set with 10Ut pot
between pins 2 !'-. 5 to 2.0V.

@

AM Audio Output

45

55

AGC Range (change in input

64

mV rms

5

dB

11

mA

level to increase AGC output

voltage from 2.0V to 4.6V)
Quiescent Current
Consumption
Max. operating frequency

9

30

MHz

-0.5
+0.5

dB
dB

Signal Input 20mV rms @ 1.784
MHz. Ref. signal input 100mV rms
@ 1.75 MHz.

-0.25
-0.25

dB
dB

Signal Input 125mV rms @ 1.75
MHz Modulated to 80% @ 1 kHz.

Change of SSB audio output
with temperature +85° C

-40°C
Change of AM audio output
with temperature +85° C

_40°C

Output open circuit

291

Sl623C

r-------oO~;;UT

J2------T-It-o OIJ~~UT
I-'--.-U-+---o O~i~UT

EART::."_ _ _"-J.-L_

_'__

_'__ __

Fig. 2 TVPical circuit using the SL623C as signal detectqr and AGe
generator.

ABSOLUTE MAXIMUM RATINGS
Storage temperature
Ambient operating temperature
Supply voltage

292

-55'C to +150'C
_55' C to +125' C
-O.5V to +12V

S1.624C

•

Plessey
Semiconductors

SL600 SERIES
COMMUNICATIONS CIRCUITS

SL624C
MULTI MODE DETECTOR

The SL624C is a complex integrated circuit designed
for use as a detector of AM, FM, SSB or CW, acting
respectively

as

a synchronous

detector,

a

quadrature

detector and a product detector with built-in oscillator. It
also contains a voltage-controlled gain system and a
separate audio amplifier capable of driving a single

transistor output stage.

A major advantage of the SL624C as an AM detector
is that unlike an envelope detector, it does not give an

output on broad band IF noise when used in a typical
receiver following a block filter and a broadband IF
amplifier.

FEATURES
•
•
•
•

Demodulates FM, AM, SSB and CW
Operates up to 30 MHz (Typ)
Voltage-Controlled Audio Gain
Separate Audio Driver

APPLICA TlONS
•

Mobile Transceivers

•
•

HF Transceivers
VHF Transceivers

AF AMP +VE

Fig. 2 Block diagram and pin connections (top)

Fig. 1 Circuit diagram

ELECTRICAL CHARACTERISTICS
Test Conditions: Supply +12V
Temperature +25°C (unless otherwise stated)
Value
Characteristic
Supply voltage

Min.
9

Current drain

Typ.
12
23

Max.
15

Units

Conditions

V
mA

Minimum input for synchronous AM detector

+25°C
_55°C to +125°C

1
5

mV r.m.s.

9 MHz input

100
300
80
50
4
30

pVr.m.s.

9 MHz input

Minimum input for limiting

+25°C
_55°C to +125°C
Detector audio gain range

Audio amplifier input R
Audio amplifier voltage gain
Maximum operating frequency
(limiting amplifier)

20

dB
kr2
MHz

293

SL624C

OPERATING NOTES
Figs. 3,4 and 5 show the SL624C used, respectively,
as a synchronous AM detector, a quadrature FM detector
and a self-oscillating product detector. It is evident that a
multi mode receiver may be made either by switching the
components around one SL624C with relays or diodes, or
by using three SL624Cs, one per mode.
The supply to the SL624C should be decoupled at
HF by a 0.1 flF capacitor sited as near as possible to pins 2
and 5.

Fig. 4 FM quadrature detector

TO +12V
DIRECTLY c.»I 'II" I14UTE

SYSI'EIoI"'~IATE

47k LOG

10k

T
INPUT

Fig. 3 Synchronous AM detector

ABSOLUTE MAXIMUM RATINGS
Storage temperature:
Operating temperature:
Supply voltage ipin 2):

294

_55°C to +150°C.
_55°C to +125°C.
+lBV.

Fig. 5 Self-oscillating product detector

SL630C

•

Plessey
Semiconductors

SL600 SERIES
COMMUNICATIONS CIRCUITS

SL630C
MICROPHONE/HEADPHONE AMPLIFIER
The SL630C is designed specifically for use as a microphone or headphone amplifier. It has a voltage
gain of 100, will accept balanced or unbalanced inputs, and can deliver up to 250mW output from a cI"$~
AB push-pull output stage.
A gain control facility with a logarithmic law allows a.g_c. to be applied when the device is used as a
microphone amplifier, and also allows remote volume control with a linear potentiometer. Gain reduction
of 100 dB may be obtained

EXTERNAL

CAPACITOR

~

MUTE

7

<>---+-----1

A.G C,

8

<>-_-+=-+-(.

OFFSET
REF

9

'--_ _+--+----I_-+--_ _+---+-_ _ _+-_ _ _+-_ _ _

~--__+_--_+__<>,o

EARTH

Fig 1 Circuit diagram

CM10

295

SL630C
ELECTRICAL CHARACTERISTICS
Test conditions: Temperature = +25°C
Signal Frequency = 1kHz
Supply = 12V (unless otherwise stated)

Value

Characteristic
Differential input voltage gain
Single ended input voltage gain
Maximum output voltage

Min.

Typ.

Max.

Units

38
43

40

42
49

dB
dB
Vrms
Vrms

5
13
3.6
1.8
3.0

mA
mA
kn
kn
n
dB
mVrms
mA

2.5
Maximum output power
Quiescent current (See also Fig. 6)
Differential input impedance
Single ended input impedance
Output impedance
Gain control range (See Fig. 5)
Maximum input (with gain reduced)
Short circuit output current

1.0

60

46
1.2
2.8
See Fig. 6

2.0
1.0
1.5
100
50

110

200

Test Conditions
Input lmVrms
Input 1mVrms
6V supply
12V supply
0.5% distortion
6V supply
12V supply

10% distortion
Irrespective of supply

OPERATING NOTES
Frequency Response
As with most small-signal integrated circuits, the inherent bandwidth of the SL630C is quite large. It
extends from low audio frequencies up to approximately 0.5 MHz, unless restricted by a roll-off capacitor
(C1) connected between pins 3 and 4. The approximate upper cut-off frequency is then given by
108

wc""Ci
where Cl is in picofarads
Muting

This can be achieved, in any application, by switching pin 7 directly to the negative rail
Microphone Amplifier
Fig. 2 shows the SL630C used with a balanced input on pins 5 and 6. If the load resistance increases
with frequency it is necessary to stabilize the output circuitry. This is accomplished with 10n in series with
1nF connected between pin 1 and earth. The earth return to pin 10 must not share any common leads,
particularly with the input. Decoupling pins 2 and 6 should follow normal engineering practice.
Headphone Amplifier
Fig. 3 shows the SL630C in a circuit suitable for powering a headset. The input is an unbalanced
source connected to pin 5 and the device is decoupled at pins 1, 2 and 6 in the same manner as the
microphone amplifier.
Manual gain adjustment using the remote gain control facility is also shown. It shol,Jld be noted that
the connection to pin 9 eliminates the 'dead' portion of the volume control range caused by the delayed
attenuation characteristic shown in Fig. 5. R1 and R2 are chosen with regard to Fig. 5 to give the desired
control range.
The input impedance at pin 8 is 3.6 kn.

296

Sl630C

''''''''

Fig 2 SL630C used as a microphone amplifier

Fig 3 SL630C used as a headphone amplifier

Automatic Gain Control
To apply a.g.c., an SL620C should be used as shown in the circuit of Fig 4. This will give effective
gain control with a low audio-frequency cut-off of 200 Hz and a control response time of approximately 20
ms.
To preserve low-frequency stability and prevent motor-boating, C4 should not exceed the value given
and, whilst R1 should not exceed 300n ,the time constant C3R1 must not be greater than 800 MS.
R2 is non-essential, but is useful if the input is likely to contain a large component below 300 Hz
C2 should be used if the power supply has a source impedance of more than a few ohms or is
connected by long wires.
The system should not be tested with sinewave inputs .below 300Hz as such signals can give rise
to delay effects not produced by speech waveforms.

0,0021-1
r--------~-----_r- tSV

C2
1.00 TO
10001-1

R2
l-Sk

Fig 4 SL630C used with SL620C to achieve automatic gain control

~'

I'\.

!

t\.

~'

V
OPTIWW L.OAO

VV

~r:w:UM~~ INTO,/

~::~~~~I!TlON
,·0

A.G,C. VOLTAGE (V)

Fig 5 AGC characteristics

V

w

U

Z

15

~

if>

ffi

" o'"
15

9
::;
::>
::;

iio

SUPPLY VOLTAGE (V)

Fig 6 Power characteristics

297

SL630C

ABSOLUTE MAXIMUM RATINGS
Storage temperature
Free-air operating temperature range
6V supply
12V supply
Supply voltage

298

-55°C to +150°C
-55°C to +125°C
_55° C to + 100° C
+18V

SL640C

•

Plessey
Semiconductors

SL641C

SL600 SERIES
COMMUNICATIONS CIRCUITS

SL640C & SL641C
DOUBLE BALANCED MODULATORS
The SL640C is designed to replace the conventional diode ring modulator, in RF and other communications systems, at frequencies of up to 75MHz. It offers a performance competitive with that of the
diode ring while eliminating the associated transformers and heavy carrier drive power requirements.
At 30 MHz, carrier and signal leaks are typically -40dB referred to the desired output product
frequency. Intermodulation products are -45dB with a 60 mV rms input signal
The SL641C is a version of the SL640C intended primarily for use in receiver mixer applications for
which it offers a lower noise figure and lower power consumption. No output load resistor is included and
signal leakage is higher, but otherwise the performance is identical to that of the SL640C

CARRIER
INPUT

3

'L--f----l----I-----l---+-+--+---'i-+~6 OUTPUT 2
f----+--I--+--+-+-+----+---+-+------9s OUTPUT 1

SIGNAL
INPUT

eM8
Fig. 1 Circuit diagram of SL640C

299

SL640C SL641 C

ELECTRICAL CHARACTERISTICS SL640C & SL641C
Test conditions:

Supply voltage = +6V
Temperature = +25°C unless otherwise stated
Value

Characteristic
Conversion gain
Signal leak

=~igna I output

j
j

Circuit

Min.

Typ.

Max.

Units

SL640C
SL640C

-2

0
-40

+2
-20

dB

SL640C

-40

-20

"}

SL640C

-45

-35

dB

2.5

3.5

mmho

Desired sideband
output

Carrier leak

-Earrier output
- Desired sideband
output
Intermodulation
products

SL641C
SL641C

-18

-12

dB

Carrier leak
I ntermodulation

SL641C
SL641C

-25
-45

-12
-30

dB
dB

Both

1kn & 4pF

SL640C
SL641C
SL640C
SL641C
SL640C
SL641C
SL640C
SL641C
SL640C
SL641C
Both
Both
Both

500n & 5pF
1kn & 4pF
350n & 8pF
8
210
250
12
10
15
12
±2
±2
±1

products

Carrier input
impedance
Signal input
impedance
Output impedance
(see Operating Notes)
Max. input before
limiting
Quiescent current
consumption

Noise figure
Signal leak variation
Carrier leak variation
Conversion gain
variation

300

Signal 1: 42.5mVrms, 1. 75MHz
Signal 2: 42.5mVrms. 2MHz
Carrier: 100mVrms, 28.25MHz
Output: 29.75MHz
{;Signal: 70mVrms, 30MHz
Carrier: 100mVrms, 28.25MHz
Output: 1.75MHz
Signal 1: 42.5mVrms, 30MHz
Signal 2: 42.5mVrms, 31MHz
Carrier: 100rnVrms, 28.25MHz
Output: 3.75MHz

Output 1

16
13

ABSOLUTE MAXIMUM RATINGS
Storage temperature range
Chip-te-ambient thermal resistance
Chip-ta-case thermal resistance
Supply voltage
Free air operating
temperature range

Signal: 70mVrms. 1.75MHz
Carrier: 100mVrms, 28.25MHz
Output: 30MHz

dB

Conversion
transconductance
Signal leak

2.2

Test Conditions

_55°C to +175°C
250°C/W
80°C/W
+9V

pF
mVrms
mVrms
rnA
rnA
dB
dB
dB
dB
dB

}-550 C to +125°C

SL640C SL641

CARRIER
INPUT

3

,

...

Hk

r~(,)
SIGNAL
INPUT

)
7

216

1-1~

~'"

F

lp

,

~

>- r--r:_ . .
'"

>SO

'?)--

"

~07p

'"'

L-ilk

S'Lk

'p

Itl

~

'"

1·1k

-

O·7p

-

'p

'p

'"

"6

H,k

.

L,lk

2'8k

4·1k

6

,
BASE
DECOUPLING

Fig. 2 Circuit diagram of SL641 C

OPERATING NOTES
The SL640C circuit requires input and output coupling capacitors which normally should be chosen
present a low reactance compared with the input and output impedances (see electrical characteristic
However, for minimum carrier leak at high frequencies the signal input should be driven from a Ie
impedance source, in which case the signal input capacitor reactance should be comparable with t
source Impedance.
Pin 2 must be decoupled to earth via a capacitor which presents the lowest possible impedance at bo
carrier and signal frequencies. The presence of these frequencies at pin 2 would give rise to poor rejecti,
figures and to distortion.
If the emitter folluwer IS used, an external load resistor must be provided to supply emitter currel
The qUiescent output voltage from the emitter follower (pin 6) is +4.6V. To achieve maximum rejecti
figures at high frequencies. pin 1 (which is connected to the header) should be connected to earth a
effective HT decoupllng should be employed. The DC impedance should not exceed 800 ohms.
The SL641 C is very similar to the SL640C but has, instead of a voltage output, a current output
enable a tuned circuit to be directly connected.
It both output sidebands are developed across the load (i.e. wideband operation), the AC impedar
of the load must be less than 800n If the output at one sideband frequency is negligible, the I
Impedance may be raised to 1.6kn. It may be further raised if it is not desired to use the maximum in,
swing of 210mV rlns
The S L640C/641 C may be used with supply voltages of up to +9 volts with increased dissi pation.
Signal ancJ earlier leaks may be minimised with 10kn potentiometers and 330kn resistors connect
as shown in Ilg.3. Rl IS adjusted to minimise signal leak; R2 to minimise carrier leak.

- ].C.].::~R2

R'
10k

Hi

.ok

H-- -,--+i T
'l~-

Fig. 3 Signal and carrier leak adjustments

301

302

SL650B8tC SL651 B8tC

•

Plessey
Semiconductors

SL600 SERIES
COMMUNICATIONS CIRCUITS

SL650B &. C SL651B &. C
MODULATOR/PHASE LOCKED LOOP CIRCUITS

The SL650/1 are versatile integrated circuits capable of
performing all the common modulation functions (AM,
PAM, SCAM, FM, FSK, PSK, PWM, tone·burst,
delta·modulation, etc.!' A wide variety of phase·locked
loops can be realised using the SL650 or SL651, with all
parameters accurately controllable; they can also be used to
generate precise waveforms at frequencies up to 0.2MHz.
The highly accurate and stable variable frequency
oscillator is programmable over a wide range of frequency
by voltage, current, resistor or capacitor. In addition direct

selection of one of four spot frequencies is facilitated by
using the on·chip binary interface, which accepts standard
logic levels at very low logic 'I' input currents.

FEATURES
•
VFO Frequency Variable Over 100: 1 Range
With Same Capacitor: Linearity 0.2%
•
VFO Temperature Coefficient:
'B' Types 20 ppm/"C Max.
'C' Types 20 ppm/"C Typ.
•
Supply sensitivity 20 ppm/% Typ.
•
VFO Phase·Continuous at Transitions
•
Bi nary Interface
Phase Comparator alP Can Swing to Supply
•
Voltages
•
On·Chip Auxiliary Amplifier (SL650)

The differential input phase comparator has a wide
common mode input voltage range. It has a high gain

limiting amplifier at its input requiring only 1mV input to
maintain lock range in a typical phase·locked loop. The
current output is programmable from zero to over 2mA by
an external resistor or current input, and the gain is
voltage -, current -, or resistance - programmable from

zero to greater than 10,000.
An auxiliary amplifier with a voltage gain of, typically,
5000 is incorpated in the SL650 for use when it is required
to interface to specified levels and impedances. The
auxiliary amplifier features low bias current (typically
25nA), fast recovery from overload, and a short·circuit
output current of ±7.5mA.
The auxiliary amplifier is omitted from the SL651,

APPLICATIONS
•
•
•
•
•
•

Modems
Modulators
Demodulators
Tone Decoders
Tracking Filters
Waveform Generators

AUX AMP
Sl6~O

ONLY

rO'~ -~Ul;'

QUICK REFERENCE DATA
TIMING
CAPACIlOR

OG24

Fig. 1 Pin connections (top view)

•
•

Supply Voltages
±6V
Operating Temperature Range -55°C to +12!

E3t>

303

Sl650B&C Sl651 B&C

ELECTRICAL CHARACTERISTICS
Test Conditions
Supply voltage: ±6V
Supply currents: 1.5mA
T A: +25°C ±5°C
Value
Characteristics
Variable frequency oscillator
Initial frequency offset error
Normal mark/space ratio
Temp. coefficient of frequency
Frequency variation with supplies
Voltage at timing current inputs
VFO output, 'low' state
VFO output, 'high' state

Pins

Min.

Typ.

Max.

-3
0.98

±1
1.00
±20
±20
±10
0
+1.3
0.5

+3
1.02

17,19
6,7,8,9
2
+1.1
2

Max. freq. of oscillation
Binary inputs
Yin to guarantee logic 'low'
Yin to guarantee logic 'high'
Input current
Phase comparator
Differential I/P offset voltage
Input bias current
Differential input resistance
Common mode I/P voltage range
Differential I/P to limit (AC)
Output current
Current gain (pin 22 to pin 21)
Transconductance,O/P/diff.I/P
Output voltage, linear range
Output current

Phase comparator I/P 'low
Phase comparator I/P 'high'
Auxiliary amplifier (Sl650 only)
Differential I/P offset voltage
Input bias current
Differential I/P resistance
Common mode I/P voltage range
Voltage gain (13-14) to 15
Output voltage range
Output current limit

10.11
10,11
10,11

0.2

+0.6
+2.4

23,24
23,24
23,24
23,24
±4
23,24
21,22 .±1.0
±4
21,22
21,23,24 ±100
±5
21
21
-4
1
1
+1.9
13,14
13,14
13,14
0.2
13,14
±4
13,14,15 1000
15
±4
±4
15

0.05

0.25

±2
0.05
100

2.5

1.0
±2.0
±10
±250
±5.5

10
±5.0

±2
-0.2
+5.3
±2
0.025
3
5000
±4.8
±6.5

0.5

Units

%
ppm/oC
ppm/%
mV
V
V
MHz

Conditions

See note 1
See note 2
RL;;> 10k!1

V
V
mA

See note 3

mV
I1A
k!1
V
mV
mA
mAN
V
I1A
V
V

V out = OV
Yin = OV

mV
I1A
M!1
V

Yin = +3.0V

See note 4
122 = 25Ol1A
See note 5
See note 5
122 = 0

Vout=OV
V in = OV

±12

V
mA

RL;;> 2k!1

NOTES
= O.01EF, R = 100kn, supply voltages
the SL650C is typically ±2.5ppm/vC over the range 0 eta +40oC.

1.

With a timing current of 601lA and f = 1kHz (C

2.

This-voltage applies for timing currents in the range 20J.1A to 2mA and with the relevant input selected. In the unselected state the voltage
is typically +O.6V.
The 'low' state is maintained when the inputs are open·circuited.
Limiting will occur earlier if the output (pin 21) voltage-limits first.
For a control current input to pin 22 of 250J1A The sign of the transconductance is positive when the signal input is positive and the VFO
output (or phase comparator input) is 'high'.

3.
4.
5.

=

±6V), the temperature coefficient of frequency of

ABSOLUTE MAXIMUM RATINGS
Supply voltages
Storage temperature
Operating temperature
In put va Itages

± 7.5V
_55° to +175°C
_55° to +125°C
Not greater than supplies

-O·~·':;O";-A----;;;""";::A;------:"C:-------'!
TIMING CURRENT

304
Fig.3 VFO linearity

Fig. 2 CircUIt diagram of SL650/SL651

OPERATING NOTES

negative supply tf ,n the VFO can be voltage-controlled
and the VFO frequency will be:

Basic VFO RelatIonships

1 Vf=-·CR Vc

The VFO free-running frequency is inversely
proportional to the value of the tuning capacitor C,
connected to pins 4 and 5, and directly proportional to the
VFO timing current (see Fig.4l. Four current switches,
controlled by TTL-compatible logic inputs on pins 10 and
11 select a combination of external resistors (connected to
pins 6, 7, 8 and 91 which determine the VFO timing
current. When both logic input

where V- is the chip and timing resistor negative supply
and V c is the control voltage connected to pin 3

dre low, open-circuit, or

connected to OV however, then only the current switch
associated with pin 7 is closed. The VFO timing current is
then determined solei" by the value of one resistor (R2 in
Fig.41, and by the negative voltage connected to that

."LQ"p

(Typ)
Maximum R.F. output
voltage

F~120MHz

NOTE: Overload occurs when the input signal reaches a level suffiCient to forward bias the base oollector junction on T1 on peak.

14

1.4

I

1. 2

12

I

V

10

1/

0

i

8

,

I

I

\
\

6

-r--

~

l.'l:

I
60MHz
120MHz
160MHz

"...

V

4

2~
o

1

10

50

100

200 300 500

FREQUENCY (MHz)

Fig 4: SL 1521 Voltage gain vs. frequency.

338

-2

·3

·4

·5

·7

·8

·9

1-0

INPUT SIGNAL V RMS

Fig 5: SL 1521 rectified output current vs. input signal

1.2

--

---.....-.....

--

~

~

1,0

i

S

.8

i!c

is

~

@
u:

~

'60~Hz

12(lMH~
'00 104Hz

_v

au: 9
~

INPUT a-5V AMS

~

4

_60_40 _20

"
~w10

a:

0
20
40
60
80
AMBIENT TEMPERATURE (0G)

100

120

--

8

F~120

MHz

RS""jC
-40 -20

20

40

60

80

100

120

TEMPERATURE (0C)

Fig 6: SL 1521 maximum rectified output current vs.
temperature

Operating Notes
The amplifiers are intended for use directly
coupled, as shown in Fig. 8. (This figure shows the
TO-5version.)
The seventh stage in an untuned cascade will be
giving virtually full output on noise.
Noise may be reduced by inserting a single tuned
circuit in the chain. As there is a large mismatch
between stages a simple shunt or series circuit
cannot be used. The choice of network is also controlled by the need to avoid distorting the
logarithmic law; the network must give unity voltage
transfer at resonance. A suitable network is shown
in Fig. 9. The value of C1 must be chosen so that at
resonance its admittance equals the total loss
conductance across the tuned circuit.

20

40

60

80

100

120

140:

' - - - - " - - - - - - ' - - - - . , - - - QUT!:'.UT

19~~~~LlNG

c3

C1

c1

FRo~1lll-'>

I 5 I4 I3
11 onFf 3nF11 nF

STAGE

C
L,

The amplifiers have been provided with two earth
leads to avoid the introduction of common earth
lead inductance between input and output circuits.

1
':'"

FR~t(-h~--,---,---o6-')TO
STAGE

2

R

60rmare

30nF

200

5.2V

Values of positive supply line decoupling
capaCitor required for untuned cascades are given
below. Smaller values can be used in high frequency tuned cascades.

Minimum capacitance

180

Fig 7: SL 1521 input admittance with open-circuit output.

A simple capaCitor may not be suitable for
decoupling the output line ~ many stages and fast
rise times are. required.

Number of Stag••

160,

FREQUENCY (MHz)

C2

ij

TO (n+l) STAGE
(PINS 6 8 7 LlNKEct

Rl

Ll
th
(n+1)
STAGE

C

3

Fig. 9: Interstage filter designs (including damping
resistors)

339

GND
I

INPUT -

- +5.2

'0 ,
GND

RF OUTPUT

VIDEO OUTPUT

Fig 10: SL 1521, bottom view

Fig 11: SL1522, bottom view

Fig 12: SL 1523, bottom view

+5.2V

~'----""""-I
VIDEO I

lKO

~

MONITOR

<>------i

VIDEO

1.5nF

I/P~

H .....--II/P

1.5nF

Vee
1.5nF (10:1 PROBE)

OIP
BIAS

(O.U.T.)

RF

OIP

~""--I ......--ofII>NWI--e---.
4500

510

r
Test Circuit

340

500
8PF

SL1550

•

Plessey
Semiconductors

SL1550
WIDEBAND AMPLIFIER

SL1550
LOW NOISE WIDEBAND AMPUFIER
WITH EXTERNAL GAIN CONTROL
The SL 1550 circuit is designed for use as a general
purpose wideband linear amplifier with remote gain
control. At an operating frequency of 60MHz the noise
figure is typically 1.8dB from a 2000 source - giving
good noise performance directly from a microwave
mixer. The SL 1550 has an external gain control
facility which can be used to obtain a swept gain
function and makes the amplifier ideal for use either in a
linear I F strip or as a low noise preamplifier in a
logarithmic strip.
External gain control is performed in the feedback loop
of the main amplifier which is buffered on the input and
output, hence the noise figure and output voltage swing
are only slightly degraded as the gain is reduced. The
external gain control characteristic is specified with an
accuracy of ·-1 dB, enabling a well-defined gain versus
time law to be obtained.
The input transistor can be connected in common
emitter or common base.

GNO

I

CM8 (8 - lead TO - 5 5.84mm PCD with stand -off)
Fig. 1 Pin connections

APPLICATIONS
•
•

Low Noise Preamplifiers
Swept Gain Radar I Fs

FEATURES
•

••
••

Wide Bandwidth
Low Noise
Gain Control Range
Gain
Output Voltage

320 MHz
2.0 dB at 100 MHz
25 dB
38 dB
0.5 V r.m.S.

ABSOLUTE MAXIMUM RATINGS
Storage temperature
Ambient operating temp.
Max. continuous supply
Voltage wrt pin 1

-55°C to ~-150°C
-55°C to -125°C

+9V

·6V

Fig. 2 Functional diagram

Fig. 3 Test circuit

341

SL1550

ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise stated):
Frequency = 30 MHz
Ec = 0
lis = 6 volts
RL = 5000

Characteristic

Voltage gain
Gain control characteristic (note 1)
Gain reduction at mid-point
Max. gain reduction
Noise figure
Output voltage
Supply current
Gain variation with supply voltage
Upper cut-off frequency
(-3dB wrt 60 MHz)
Gain variation with temperature
(note 2)

Value

Units

Min.

Typ.

Max.

34

38
See Fig. 5
10
25
2.0
3.5
0.3
15
0.2
125

42

20

12

2.7
18

Conditions

dB
dB
dB
dB
dB
Vrms
mA

Ec
Ec
Rs
Rs

=
=
=
=

dBN

Vs

= 6 to 9V.

1.3V
5V
2000
500

MHz

T,mb -55°C to -,-125°C

dB

±3

NOTES
1. The ext~rnal gain control characteristic is specified In terms of the gain reduction obtained when the control voltage (Ec)
from zero to the specified voltage.
2. This can be reduced by an alternative, input configuration (see operating note: 'Wide Temperature Range').

IS

increased

OPERATING NOTES
Input impedance
Typical input impedance at 60 MHz is 5000 in
parallel with 12 pF. The capacitance is independent of
frequency but the resistance increases to approximately
1.5kO at 10 MHz.
Control input

10

20 40

FREQUENCY

Gain control is achieved by applying a positive
voltage to pin 2.

100

(MHz)

200 400

Fig. 4 Frequency response

Wide temperature range
The gain variation with temperature can be reduced
at the expense of noise figure by including an internal
300 resistor in the emitter of the input transistor. This is
achieved by decoupling pin 7 and leaving pin 6 opencircuit. Gain variation is reduced from ±3dB to ±1dB
over the temperature range -55°C to + 125°C (Figs. 6
and 7)
Low input impedance
A low input impedance (: 250) can be obtained by
connecting the input transistor in common base. This is
achieved by decoupling pin 5 and applying the input to
pin 6 (pin 7 open-circuit).
High frequency stability
Care must be taken to keep all leads short and a
ground plane should be used to prevent any earth
inductance common between the input and output
circuits.

342

-IS

t=tttt::ttj:j::jtt~sj::tt=t::tjj:tttj

-20~1Emlllll§
-25~
10

01
CONTROL VOLTAGE lEe I (V)

Fig. 5 Gain control characteristic

SL 1550

,

:--

H--+---!

0

Eco O

I-t-- r-1---_
Ec~15V

I
-,"

~

-- 'S,H

:~!::;":O":O~;;,,OC"'"'' -C---

I

0'-

" I

I---

...
'"

Ec=6V

I

'"

0

.,0

------

HO

HO

"I

t-I- j ~ I -.
I

I

,

i

!

i
Ec =6V

I---I---

,"0

+'00

+110

Fig. 7 Voltage gain v. temperature (pin 7 decoup/ed for improve!

Fig. 6 Voltage gain v. temperature (pin 6 decoup/ed, standard

gain vatiation with temperaturpe-see operating notes).

circuit configuration).

1

l
~-l

-+ ~

-":-----'---------c;----":-i~--.L~
Fig.S Tvpical noise figure v. temperature.

Fig. 9 Input and output impedances (Vs = 6Vj

Fig. 10 Circuit diagram

343

344

SL1610C SL1611C SL1612C

•

Plessey
Semiconductors

SL1600 SERIES
COMMUNICATIONS CIRCUITS

SL1610C, SL1611C & SL1612C
RF/IF AMPUFIERS

The SL1610C and SL1611C are low noise, low
distortion, RF voltage amplifiers with integral supply line
decoupling and AGC facilities. The SL1610C has a voltage
gain of 10 and a bandwidth of 140M Hz, while the SL 1611 C
has a voltage gain of 20 and a bandwidth of 100M Hz. Both
circuits have.a 50dB AGC range with maximum signal
handling of 250mV rms. As they are voltage amplifiers they
have high input impedance and low output impedance.
The SL 1612C is a low noise, low distortion, IF voltage
amplifier similar to the SL 1610C and SL 1611C but having
a voltage gain of 50, a bandwidth of 15M Hz and only
20mW power consumption. It has a 70dB AGC range with
maximum signal handling of 250mV rms.

APPLICATIONS
•
•
•

IF Ampl ifiers
RF Amplifiers
AGC-Controlled Ampl ifiers

v+
OUTPUT
lIP EARTH

,0

a

O!~ e,",~

7

AGe

~

6

BIAS

4

5

INPUT

2

OP8
Fig. 1 Pin connections (top view)

FEATURES
•
•
•
•
•

Low Noise
Low Distortion
1V rms Output
Wide AGC Range
On-Chip Decoupling

Fig. 2 CircuitdiagramofSL1610CandSL1611C
(Component values for SL 161TG are shown in brackets)

Fig. 3 Circuit diagram of SL 1612C

345

SL1610C SL1611C SL1612C

ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Supply voltage = 6V
Temperature = +25°C (unless otherwise stated)
Pins 5 and 6 strapped together
AGC not applied unless specified.
Characteristic

Circuit

Typical Value

Units

Voltage gain (see notel)

SL1610C
SL1611C
SL1612C

dB
dB
dB

Cut-off frequency
\
(-3dB)
(See Fig. 9 and notel)

rL1610C
SL1611C
SL1612C
SL1610C
SL16llC
SL 1612C

20
26
34
120
80
12
4
4
3
100
50
20
250
250
250
50
50
70
0.15
0.15
0.15
15
15
3.3

Noise Figure

Max. input signal
\
(1% cross modulation)
No AGC applied
Max. input signal
(
(1 % cross modulation)
Full AGC applied
AGC range }
(See Fig-1O)
AGC current

Quiescent current

consumption

rL1610C
, SL 1611C
SL 1612C
rL1610C
SL1611C
SL1612C
rL1610C
SL1611C
SL1612C
SL1610C
SL1611C
SL1612C
SL1610C
SL1611C
SL1612C

ir

Test conditions
30MHz
30MHz
1.75MHz

ource = 25n
Load R;;;' 500n
Load C';; 5pF

rource = 25n
Load R;;;' 500n
Load C.;; 5pF
Source = 300n, f = 30MHz
Source = 300n, f = 30MHz
Source = BOOn, f = 1.75MHz
Load 150n,f= 10MHz
Load 150n, f = 10MHz
Load 1.2kn, f = 1.75MHz
f = 10MHz
f = 10MHz
f = 1.75MHz

MHz \
MHz
MHz
dB
dB
dB
mVrms
mVrms

mVrms
mVrms
mVrms
mVrms
dB
dB
dB
rnA
rnA
rnA
rnA
rnA
rnA

,

(AGC Voltage = 5.1V

(output open circuit

NOTE
1 Gain and frequency response of these circuits are relatively independent of supply voltage within the range 6 to 9V

OPERATING NOTES
The SL1610C, SL1611C and SL1612C are normally
used with pins 5 and 6 strapped. A slight improvement in
noise figure, and an increase in the input impedance,may be
obtained by feeding the device from a coil or tuned circuit,
bias from pin 6 being decoupled and applied to one end of
the coil and the signal being taken either from the other
end or from a tap.
The characteristics of these units have been expressed in
G parameters which are defined as shown in Fig. 4.

Thes. parameters correspond to the normal operation of
a voltage amplifier wh ich is usually operating into a load
much ~igher than its output impedance and from a source
much lower than its input impedance. Hence the input
admittance (G I I ) and voltage gain (G 2 I ) are measured with
open circuit output, and the output impedance (G 22 ) with
short circuit input. The parasitic feedback parameter is the
current transfer (G 1 2) i.e. the current" which flows in a
short circuit across the input for a given current flowing in

the output circuit.
Since the effects of G 12 are small for reasonable values
of load and source impedance, the approximate equivalent
circuit given in Fig. 5 may be used.

CJt, +~}
1

I

I

Fig. 4 Definition of G parameters

346

Fig. 5 Amplifier equivalent circuit

Gn

I

I tOAD

SL1610C
Hence the typical effects of applying finite load and
source impeuances, real or complex, may be evaluated by
the use of the graphs showing the values of the maior
parameters versus frequency. At lower frequencies the
limitation on ZL is dependent upon output signal; for

maximum output ZL

~

lOOn.

SL1612C

These devices may be used with supplies up to +9V with
increased dissipation.
The AGe characteristics shown in Fig. 8 vary somewhat
with temperature: a preset potentiometer should not,
therefore, be used to set the gain of either of these circuits
if accurate gain is requireri

Stability
Both the input admittance Gil and the output
impedance G 22 have negative real parts at certain
frequencies. The equivalent circuits of input and output are

I
I

--

,

shown in Fig. 6 and the values of R in , Rout. C in and Lout
may be determined for any particular frequency from the

graphs Fig. 7 and 8. It will be seen that, for the SL 1610C
and the SL 1611 C R in is negative between 30 and 100M Hz,
and Rout is negative over the whole operating frequency
range. For the SL1612C, Rin is not negative and Rout is
negative only below 700KHz.

SL1611C

II IIII
II IIII

SL '~'OC1

1111'
SL1611C

RESISTANCE - REACTANCE

---

,

SLI612C

.....-

SL1612C

,,

V

,

,

SL1611C

S

~-

-

-::,--SL1610C

/

~

..

I
I

I

Fig. 6 Input and output equivalent cirCUits
FREQUENCY

~~~-+~'c~~-;,-"cc,~~-H~~--~~-H~~s,-,,-,c~c

{MHzl

Fig. 8 Output impedance with SIC input (G 22 )

~r~~=-~T-r~T_+ffi*~-44~~*m-~

0

SUSCEP1ANCE - - -

I:
0

~--+--4-t+

"
SL1611C

H+H---+--++++Iffi-·-- --l-+-h\-+++sl-c~,,-:"c~

.....-

~ 2~~~-+*+H+-~--~~*j+---+---+~+Hrr~
0
~

SL 1612C

,...-

SLlBIIC

I

.-

SLlliiOC

\

I

\

SLI612C

0

FREQUENCY (MHz)

Fig. 9 Voltage gain (G 21 )
0

FREQUENCY (MHz)

~

0

"\

Fig. 7 Input admittance with OIC output (G II)
0

It is evident that if an inductive element having
inductance L 1 and parallel resistance R 1 is connected
across the input, oscillation will occur if R in is negative at
the resonant frequency of C in and L1, and R 1 is higher
than R.n.
Similarly. if a capacitor C1 in series with a resistance R2
is connected across the output oscillation will occur if, at
the resonant frequency of Lout and C 1, Rou t has a negative
resistance greater than the positive resistance R2. Where the
input may be inductive, therefore, it may be shunted by a
resistor and where the load may be capacitive 47n should
be placed in series with the output.

"\
SLI612C

AGC

SIGNAL

SLI610C
\:LI611C

(V)

Fig. 10 AGC characteristics

347

SL1610C SL1611C SL1612C

,

.'-

"- 1\

SL1610C

SL1612C

/

SLI611C

l

V

'\.

,

"'- t- V
FREQUENCY (MHz)

Fig. 11 Reverse current transfer ratio (G 12)

ABSOLUTE MAXIMUM RATINGS
Storage temperature range
Supply voltage
Operating temperature

348

-30 o e to + 85°C
+10V.
-30 o e to +70°C

SL1613C

•

Plessey

SL1600 SERIES

Semiconductors

COMMUNICATIONS CIRCUITS

SL1613C
UMmNG AMPUFIERIDETECTOR

The SL 1613C is a low noise limiting amplifier intended
for use as an RF clipper, a limiting stage in IF amplifiers, or
an R F Compressor in SSB transmitters. It contains a
detector which may be used to detect AM but is
particularly intended for use as an AGC detector. The
amplifier, which has a gain of 12dB when not limiting, has
upper and lower 3dB points of 150MHz and 5MHz
respectively. It limits when its input exceeds 120mV rms.
The detected output during limiting is lmA.

OIPEARTHD'
8
DIP EARTH
v+

2

7

alAS

RFQUTPUT

3

6

INPUT

DEl OUTPUT

4

5

liP EARTH

DPS
Fig. 1 Pin connections (top view)

FEATURES
•
•
•
•

Wide Bandwidth
Low Noise
Highly Symmetrical Limiting
Large Signal Handling Capability

APPLICATIONS
•
•
•
•

Fig.2 -Circuit diagram SL 1613C

RF Clippers
AGC Systems
AM Detectors
RF Compression in SSB Transmitters

ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise stated):
Supply +6V
Temperature +25°C
Pins 6 & 7 strapped together
Value
Units

Characteristic

Voltage gain
Upper 3dB frequency
Lower 3dB frequency
Noise figure
Supply current
Limited RF olp
Detector current
Maximum input before overload
Input impedance

Min.

Typ.

Max.

10

12
150
5
4.5
15
1.25
1
1.75
5kQ#6pF

14

0.8

20
1.3

dB
MHz
MHz
dB
mA
Vp-p
mA
V rms

Conditions

30MHz

60MHz 500Q source
No signal
0.5V input, 30MHz
0.5V input, 30MHz
30MHz
60MHz Open circuit output

349

SL1613C

OPERATING NOTES
The SL1613C, like the SL1610/11/12, is normally used
with the input and bias pins connected directly together
and the input applied through a capacitor. However, and
again like the SL 1610/11/12, the bias may be decoupled
and connected to the 'cold' end of a coil or tuned circuit,
the input pin being connected to its 'hot' end or to a tap.
The supply rail is decoupled internally at RF but as the
gain is dependent on supply voltage there should be no
appreciable LF ripple on the supply. Two separate earth
connections are made in order to minimise the effects of
common earth-lead inductance - such common earth-lead
inductance can cause instability and care should be taken

not to introduce it externally.
The R F output is capable of driving a load of 1 kQ in
parallel with 1OpF. If a capacitive load of more than 10pF

350

is envisaged a resistor should be connected between the

output pin and the load. Normally 50Q is sufficient. The
output should be isolated at DC by a capacitor.
The detected output consists of a current out of pin 4,
which is an NPN transistor collector. This pin must always
be more than 3 volts more positive than earth, even if the

detected output is not required lin which case it is best to
strap pins 2 and 4).

ABSOLUTE MAXIMUM RATINGS
Storage temperature
Operating temperature

Supply voltage Ipins 2 or 4)

-30°C to +85°C
-30°C to +70°C

+9V

SL1620C SL1621C

•

Plessey
Semiconductors

SL1600 SERIES
COMMUNlCAll0NS CIRCUITS

SL1620C & SL1621C
AGC GENERATORS

The SL1621C is an AGC generator designed specifically
for use in SSB receivers in conjunction with the SL1610C,
SL1611C and SL1612C RF and IF amplifiers. In common
with other advanced systems it generates a suitable AGC
voltage directly from the detected audio waveform,
provides a 'hold' period to maintain the AGC level during
pauses in speech. and is immune to noise interference. In
addition it will smoothly follow the fading signals
characteristic of HF communication.
When used in a receiver comprising one SL1610C and
one SL1612C amplifier and a suitable detector, the
SL1621C will maintain the output within a 4dB rang. for a
110dB range of receiver input signal.
The SL 1620C VOGAD (Voice Operated Gain Adjusting
Device) is an AGC generator designed to work in
conjunction with the SL 1630C audio amplifier (particularly
when the latter is used as a microphone amplifier) to
maintain the amplifier output bet>':,en 70mV and 87mV
rms for a 35dB range of input. A one second 'hold' period
is provided which prevents any increase of background

01'!
Fig. 1 Pin connfICtions (top lIiew)

FEATURES
•
•
•
•

Wide Dynamic Range
Speech Pause Memory
Fast Attack/Adaptive Decay
Only 4 External Components

noise during pauses in speech.

ABSOLUTE MAXIMUM RATINGS
APPLICATIONS
•

Speech-Derived AGC Systems

Storage temperature
Supply voltage
Operating temperature

-30'C to +85' C

-9V
-30°C to +70°C

'NPUT 1 0----=-

""

Ul)k)

"

100~

Fig. 2

Circuit diagram ofSL1620C and SL 1621C (component values for SL 1620C are shown in brackets)

351

SL1620C SL1621C

ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Supply voltage = 6V
Temperature = +25°C
Input signal frequency = 1kHz
Characteristic
Input for 0.65V DC output
Input for 1.5V DC output
Input for 2.2V DC output
Input for 4.6V DC output
"Fast rise time, t,
"Fast decay time, t.

Circuit

Typical Value

Units

SL1620C
SL1620C
SL1621C
SL1621C
Both
Both

70
87
7.0
11.0
20
200

mVrms
mVrms
mVrms
mVrms
ms
ms

'Slow rise ti me, t,

Both

200

ms

Input 3 d& point
Maximum fade rate

Both
SL1620C
SL1621C
Both
Both
Both
SL1620C
SL1621C
Both
Both
SL1620C
SL1621C
SL1620C
SL1621C

10
0.22
0.45
200
1.0
12
2
5
3
30
1.4
500
1.7
2.5

kHz
VIs
vIs
ms
s
mVp·p
V
V
mA
mA
kn
n
mA
mA

Test conditions
See Fig. 61
Measurement
See Fig. 6
accuracy
See Fig. 7
1 dB
See Fig. 7
0-50% full output ~
100%-36% voltage
C, = 50JLF
on C,
Time to output
transition point

"Hold collapse time, 4
"Hold time, t,
AC ripple on output
Maximum output voltage
Quiescent current consumption

Surge current
Input resistance
Output current

"See Fig. 3

352

C.

= 100JLF

Full·zero output
C3 = 100JLF
1kHz. Output open circuit

@+2V output
@+ 5.1V output

Sl1620C Sl1621(

DESCRIPTION

OPERATING NOTES

The operation of the SL1621 C is described with
reference to the circuit diagram, Fig. 2 and Fig. 3 which
illustrates the dynamic response of a receiver controlled by
the SL1621C.
The SL1621 C consists of an input AF amplifier
TR1·TR4 (3dB point: 10KHz) coupled to a DC output
amplifier, TR16·TR19, by means of a voltage back·off
circuit, TR5 and two detectors, TR 14 and TR 15, having
short and long rise and fall time constants respectively.
The detected audio signal at the input will rapidly
establish an AGC level, via TR 14, in time t, (see Fig. 3).
Meanwhile the long time constant detector output will rise
and after t3 wi II control the output because th is detector is
the more sensitive.
If signals exist at the SL 1621C input which are greater
than approximately 4mV rms they will actuate the trigger
circuit TR6·TR8 whose output pulses will provide a
discharge current for C2 via TR 10, TR 13.
By this means the voltage on C2 can decay at a
maximum rate, which corresponds to a rise in receiver gain
of 20 dB/so Therefore the AGC system will smoothly follow
signals which are fading at this rate or slower. However,
should the receiver input signals fade faster than this. or
disappear completely as during pauses in speech, then the
input to the AGC generator will drop below the 4mV rms
threshold and the trigger will cease to operate. As C2 then
has no discharge path, it will hold its charge (and hence the
output AGC level) at the last attained value. The output of
the short time constant detector will drop to zero in time
t2 after the disappearance of the signal.
The trigger pulses also charge C3 via TR9, so holding off
TR 12 via TR 11. When the trigger pulses cease, C3
discharges and after ts turns on TR 12. Capacitor C2 is
discharged rapidly (in time t4) via TR 12 and so full receiver
gain is restored. The hold time, ts is approximately one
second with C3 = 10011F. If signals reappear during t s , then
C3- will re-charge.and normal operation will continue. The
C3 re-charge time is made long enough to prevent
prolongation of the hold time by noise pulses.
Fig. 3 shows how a noise burst superimposed on speech
will initiate rapid AGC action via the short time constant
detector while the long time constant detector effectively
remembers the pre'noise AGC level.

The various time constants quoted are for C1 = 50111
and C2 = C3 = 1OOIlF. These time constants may be altere.
by varying the appropriate capacitors.
An input coupling capacitor is required. This shaull
normally be 0.3311F for an SL 1621C and about 111F for a.
SL1620C.
Fig.4 shows how the SL 1621C may be connected into i
typical SSB receiver.
Fig. 5 shows how the SL1620C is used to control thl
gain of the SL1630C audio amplifier. The operation of th.
SL1620C is exactly the same as that of the SL1621C an,
the diagram showing the dynamic response of the close,
loop system, Fig. 3, is equally applicable to th.
SL1630C/SL 1620C combination. Again, the time constant:
may be altered by varying the capacitor values.
The supply must either have a source resistance of les'
than 2[2 at LF or be decoupled by at least 500ilF so that i'
is not affected by the current surge resulting from a sudder
input on pin 1. The devices may be used with a supply o'
up to +9V.
In a receiver for both AM and SSB using an SL623C
detector/carrier AGC generator, the AGC outputs of thE
Sl1621 C and SL623C may be connected together providec
that no audio reaches the SL1621C input while the Sl623C
is controlling the system

RF
INPUT

Fig. 3

Dynamic response

AF
OUTPUT

Fig. 4 SL 1621C used to control an SSB receiver

353

S L 1620C S L1 621 C

o 002iJ.

,-------r------r--'"

Fig. 5 SL 1620C used to control an SL 1630C audio amplifier

,,

II

v

°oL-L-L-L_L-I;Lo~lL-L-L-L-~
INPUT (mY rms)

Fig. 6

354

Transfer characteristic of SL 1620C

INPUT (mY rms)

Fig. 7

Transfer characteristic of SL 1621C

SL1623C

•

Plessey
Semiconductors

SL1600 SERIES
COMMUNICATIONS CIRCUITS

SL1623C
AM DETECTOR. AGe AMPLIFIER & SSB DEMODULATOR
The SL 1623C is a silicon integrated circuit combining
the functions of low level, low distortion AM detector and
AGC generator with SSB demodulator. It is designed
specially for use in SSB!AM receivers in conjunction with
SL1610C, SL1611C and SL1612C RF and IF amplifiers. It
is complementary to the SL1621C SSB AGC generator.
The AGC voltage is generated directly from the
detected carrier signal and is independent of the depth of
modulation used. Its response is fast enough to follow the
most rapidly fading signals. When used in a receiver
comprising one SL 1610C and one SL 1612C amplifier, the
SL 1623C will maintain the output within a 5 dB range for a
90 dB range of receiver input signal.
The AM detector, which will work with a carrier level
down to 100 mV, contributes negligible distortion up to
90% modulation. The SSB demodulator is of single
balanced form. The SL1623C is designed to operate at
intermediate frequencies up to 30MHz. In addi,tion it
functions at frequencies up to 120MHz wit~ some
degradation in detection efficiencies. The encapsulation is a
14 lead DIL package and the device is designed to operate
from a 6 volt supply, over a temperature range of-30°C
to +70 0 C.

ELECTRICAL CHARACTERISTICS @ SUPPLY

AM AGC THRESHOLD SET

I

PHASE CORRECTION

AGC OUTPUT

3

AM AGC THRESHOLD SET

4

I~

AM AUDIO OUTPUT

Il

OV

1.'

SIGNAL INPUT

'[1

sse AUDIO OUTPUT

'I

+6VSUPPLY

"L_ _ _"r REFERENCE SIGNAL INPUT

DP14
Fig. 1 Pin connection

ABSOLUTE MAXIMUM RATINGS
Storage temperature
Ambient operating temperature
Supply voltage

-300C to + 85 °c
OoC to + 80 0C
-0.5V to +12V

=+6V, Tamb = +250 C

Value
Characteristic

Units
Min.

Typ.

Test Conditions

Max.

SSB Audio Output

30

mVrms

AM Audio Output

55

mVrms

AGC Range (change in input
level to increase AGC output
voltage from 2.0V to 4.6V)

5

dB

Quiescent Current
Consumption
Max. operating frequency

9

rnA

30

MHz

Signal Input 20mV rms @ 1.748
MHz. Ref. Signal Input l00mV rms
@ 1.750 MHz
Signal Input 125mV rms @ 1.75
MHz. Modulated to 80% @ 1kHz.
Initial signal input 125mV rms at
1.75 MHz. Mod. to 80% at 1 kHz.
pot
Output Set with 10kO
between pins 1&4 to 2.0V.
Output open circuit.

355

SL1623C

.

CARRtER

'"

AUDIO
OUT

"

6 VOLT
SUPPLY

HV

9

REFERENCE
SIGNAL

INPUT

1"------..-1 l---oOU~~UT
.J"-.HI-+----Oo~f~UT

"
0"'

A"
AUDIO

~

AM i. AGe

EARTHo----L-J-I--I--~_ _

'"

Fig. 2 Block Diagram

356

,
PHASE

CORRECTION

THRESHOLD

Fig. 3 Typical circuit using the SL 1623C as signal detector and AGe

SL1625C

•

Plessey
Semiconductors

SL1600 SERIES
COMMUNICATIONS CIRCUITS

SL1625C
AM DETECTOR & AGC AMPLIFIER
The SL 1625 is a silicon integrated circuit combining
the functions of low level, low distortion AM detector and
AGC generator. It is designed specially for use in SSB/AM
receivers in conjunction with SL1610C, SL1611C and
SL1612C RF and IF amplifiers.
The AGC voltage is generated directly from the
detected carrier signal and is independent of the depth of
modulation used. Its response is fast enough to follow the
most rapidly fading signals. When used in a receiver
comprising one SL1610C and SL 1612C amplifier, the
SL 1625 will maintain the output within a 5 dB range for a
90 dB range of receiver input signal.
The AM detector, which will work with a carrier level
down to 100 mV, contributes negligible distortion up to
90% modulation.
The SL 1625 is designed to operate at intermediate
frequencies up to 30M Hz. In addition it functions at
frequencies up to 120MHz with some degradation in
detection efficiencies. The encapsulation is an 8 lead DIL
package and the device is designed to operate from a 6
volt supply, over a temperature range of 300 C to+700C.

ELECTRICAL CHARACTERISTICS

@

ov

0

AM AUDIO OUTPUT

2

7

+6V SUPPLY

AM AGe THRESHOLD SET

J

6

AM AGe THRESHOLD SET

L.J

8

SIGNAi...INPUT

PHASE CQRRECTION ...'_ _--C.SrAGC OUTPUT

DP8
Fig. 1 Pin connection

ABSOLUTE MAXIMUM RATINGS
Storage temperature
Supply voltage

-30 oC to + 85 0 C
-0.5V to +12V

SUPPLY =+6V, T amb = +250 C

Value
Characteristic

AM Audio Output

Min.

Typ.

Max.

40

55

70

AGC Range (change in input
level to increase AGC output
voltage from 2.0V to 4.6V)

5

Quiescent Current
Consumption
Max. operating frequency

9

30

Units

Ta.t Conditions

mVrms

Signal Input 125mV rms @ 1.75
MHz. Modulated to 80% @ 1 kHz.
Initial signal input 125mV rms at
1.75 MHz. Mod. to 80% at 1 kHz.
Output Set with 10k
pot
between pins 3 & 6 to 2.0V.
Output open circuit.

dB

15

rnA
MHz

357

SL1625C

,.,

AUDIO

CUT

~

At.! 'AGe

E~H~------~~----~~---

seT

Fig. 2 Block Diagram

358

,
PHASE

CORRECTION

THRESHOlD

Fig. ·3 Typical circuit using the SL 1625 as signal detector
and AGe generator.

Sl.1tl26C

•

Plessey
Semiconductors

SL1600 SERIES
COMMUNICAllONS CIRCUITS

SL1626C
AUDIO AMPLIFIER AND VOGAD
The SL1626C is a silicon integrated circuit combining the functions of audio amplifier with voice operated
gain adjusting device (VOGAD).
It is designed to accept signals from a low-sensitivity
microphone and to provide an essentially constant
output signal for a 60dB range of input.
The encapsulation is an 8-lead plastic dual-in-line
package and the device is designed to operate from a
6V ±O.5 volt supply, over a temperature range of
-30°C to ~ 70°C

\/OGAOT'MECONSTANTD8 AfOUTPUT

o

ACCQUPLING

2

7

6\1

3

5

HF ROLL Off

0\1

BALANCED SIGNALINPUT

,

;

BALANCED SlGNALINPUT

DPB
Fig. 1 Pin connections (top)

FEATURES

APPLICATIONS

•
•
•
•

•
•
•
•

Constant Output Signal
Fast Attack
Low Power Consumption
Simple Circuitry

Audio AGC Systems
Transmitter Overmodulation Prevention
Speech Recording
Level Setting Systems

ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
I nput frequency
Supply voltage
Temperature

1kHz
+6V
+25'C

Characteristic
VOGAD output level
AF amplifier voltage gain
Quiescent current consumption
Decay time (see note 1)
Attack time (see note 2)
Total harmonic distortion of VOGAD output
Differential input impedance
Single-ended input impedance
AF amplifier output resistance
Minimum load resistance - AF amplifier olp
VOGAD operating threshold (whisper threshold)
at input
Input for 10% distortion
Supply line rejection at VOGAD alp
Common mode signal handling

Value
Min.

Typ.

Max.

55

90
52
14
1.0
20
2
300
180
50
1000

140

100
130
15
50

20

Unit

Conditions

mV rms
dB
mA
s
ms

Balanced signal input 18mV rms
Balanced signal input 72uV rms
6V supply
Original balanced signal input 18mV rms
Original balanced signal input 1.8mV rms
Balanced signal input 90mV rms

%
II

a
a
a
IlV rrns
mV rms
dB
mV p-p

NOTES

1.

Decay time IS the time for VOGAD output to return within 10% of original absolute level when signal Input voltage IS sWitched down
20dB.
Attack time is the time for VOGAD output to return to within 10% of anginal absolute level when slglli1llnput voltage IS sWitched up
20dB.

359

SL1626C

OPERATING NOTES
The SL1626 will operate from a range of supply
voltages from 4V up to 12V.
The input stage is a differential class A-S stage with
AGC terminal. The accurate balance of the input stage
and high common-mode rejection ratio of the second
stage gives an overall common-mode rejection ratio
of greater than 30dS.
Typically, the amplifier will handle differential input
signals of up to 375mV p-p. When used in the unbalanced mode either pin 4 or pin 5 may be used as the
input, the other being decoupled to earth.
The LF cut-off of the amplifier is set by C1 and also
by the values of coupling capacitors to the input pins
(pin 4 and pin 5). Coupling capacitors should be used
if the DC potential of the input is not floating with
respect to earth.
The HF cut-off is set by C2 (see Fig. 3). The VOGAD
threshold may be increased by connecting and external
conductance between pins 7 and 8. The threshold is
increased by approximately 20dS for 1 millimho of
conductance; the value of C2 should be adjusted in
conjunction with any threshold alteration in order to
obtain the desired bandwidth.
C3 and R1 set the attack and decay rates of the
VOGAD. In Fig. 3, C3=47uF and R1 =1 Mohm which
give an attack time constant (gain increasing) of
20ms and a decay rate of 20dS/s. C1 =2.2uF and C2
=4.7nF give a 3dS bandwidth of approximately
300Hz to 3kHz.

j-----------------=i3 t6V

BALANCED {
INPUT

,

I

---Q60V

I

I

I

I

I

I

I

I

I

5

I

I

I

I

I
2
AC
COUPLING

____ JI

,

,

HF
ROLL OFF

VOGAD
TIME
CONSTANT

Fig. 2 Block diagram

ABSOLUTE MAXIMUM RATINGS
Continuous supply voltage (positive) 12V
' - 30°C to +85°C
Storage temperature
Ambient operating temperature -30°C to
70°C

+

360

Fig. 3 Connection diagram for SL1626C used as a microphone
amplifier

Sl1630C

•

Plessey
Semiconductors

SL1600 SERIES
COMMUNICAllONS CIRCUITS

SL1630C
MICROPHONE/HEADPHONE AMPUFIER

The S L 1G30e is designed specifically for use as a
microphone or headphone amplifier. It has a voltage gain of
100, will accept balanced or unbalanced inputs, and can
deliver up to 200 mW output from a class AB push-pull
output stage .
. A gain control facility with a logarithmic law allows
AGe to be applied when the device is used as a microphone
amplifier, and also allows remote volume control with a
linear potentiometer. Gain reduction of GOdB may be
obtained.

DP8

FEATURES

Fig. 1 Pin connections (top view)

•
•

40dB Gain
Voltage-Controlled Gain

•
•

200 mW output
Low Output I mpedence

ABSOLUTE MAXIMUM RATINGS
Storage temperature
Operating temperature

APPLICATIONS
•
•

Low-Power Audio alP Stages
Preamplifiers (with or without AGC)

Supply voltage

_30°C to + 85°C
GV supply _30°C to +70o e
12V supply -30 0 eto +70 o e
+15V

EXTERNAL C"PACITOR

~

-+-+-.....--~~--r-<

~-'-""'---1~----.....-~-.....- - -.....

AGe

7

2

POSITIVE
SUPPLY

o---+--=~t'

'----"-......--<-......__I---+-_ _ _

~

___

~

_ _ _......_ _......_ _

~

8 EARTH

Fig. 2 Circuit diagram

361

SL1630C

ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Temperature = +25°C
Signal Frequency = 1 kHz
Supply = 12V
Characteristic
Differential input voltage gain
Single ended input voltage gain
Maximum output voltage

Maximum output power
Quiescent .current ISee also Fig. 7)

Differential input impedance
Single ended input impedance
Output impedance
Gain control range (See Fig. 6)
Maximum input (with gain reduced)
Short circuit output current

Typical Value

Units

40
46
1
2
See Fig. 7
5
12
2.0
1.0
1.5
60
50
110

dB
dB
Vrms
Vrms
mA
mA
kn
kn
n
dB
mVrms
mA

Test cond itions
Input lmVrms
Input lmVrms
6V supply
12V supply
0.5% distortion
6V supply
12V supply

10% distortion
Irrespective of supply

OPERATING NOTES
Frequency Response

Headphone Amplifier

As with most small·signal integrated circuits, the
inherent bandwidth of the SL 1630C is quite large. It
extends from low audio frequencies up to approximately
0.5 MHz, unless restricted by a roll-off capacitor (Cl)
connected between pins 3 and 4. The approximate upper
cut-off frequency is then given by

Fig.4 shows the S1.1630C in a circuit suitable for
powering a headset. The input is an unbalanced source
connected to pin 5 and the device is decoupled at pins 1, 2
and 6 in the same manner as the microphone amplifier.
Manual gain adjustment using the remote gain control
facility is also shown; R 1 and R2 are chosen with regard to
Fig. 6 to give the desired control range.

108

Wc"'CT
Where Cl is in picofarads

Microphone Amplifier
Fig.3 shows the SL 1630C used with a balanced input on
pins 5 and 6. If the load resistance increases with frequency
it is necessary to stabilize the output circuitry_ This is
accomplished with 10n in series with 1 nF connected
between pin 1 and earth. The earth return to pin 8 must
not share any common leads, particularly with the input.
Decoupling pins 2 and 6 should follow normal engineering
practice.

Fig. 4 SL 1630C used as a headphone amp/dier

Automatic Gain Control

362

Fig. 3

SL 1630C used as a microphone amplifier

To apply AGC, an SL 1620C should be used as shown in
the circuit of Fig. 5. This will give effective gain control
with a low audio-frequency cut-off of 200 Hz and a control
response time of approximately 20 ms.
To preserve low-frequency stability and prevent
motor-boating, C4 should not exceed the value given and,
whilst R 1 should not exceed 300n, the time constant
C3R 1 must not be greater than 800 ps.
R2 is non-essential, but is useful if the input is likely to
contain a large component below 300 Hz. C2 should be
used if the power supply has a source impedance of more
than a few ohms or is connected by long wires.

SL1630C

0-002~

,-------------~--------~--t6V

6
M ICROPHON E OR

TRANSFORMER
INPUT

C'

C2
400 TO

SL1620C

10001>

0-51-1t

L-,.,__j'-Tn-r''1~---,-::-,)
CI

50"
10

Fig. 5 SL 1630C used with SL 1620C to achieve automatic gain control

I

I
I

i

~

I

- --r--I

r--H~----c.-

'"

--

i'\.

"-

+

~'

I
OPTIMUM LOAD

I

I

I
I

6~~I~u3UI~ATOINTO . /

"

1/
1/

V

u
Z

35

/

;/'

~::~~Ec"rINS~MPITIO('

~
~

25

~

o

15

9
~

~

o
AGe VOLTAGE (v)

Fig. 6 AGe characteristics

SUPPLY VOLTAGE (V)

Fig. 7 Power characteristics

363

364

SL1640C

•

Plessey

SL1641C

SL1600 SERIES

Semiconductors

COMMUNICATIONS CIRCUITS

SL1640C & SL1641C
DOUBLE BALANCED MODULATORS

The SL 1640C is designed to replace the conventional
diode ring modulator, in RF and other communications
systems, at frequencies of up to 75MHz. It offers a
performance competitive with that of the diode ring while

'
D
'D

CAR'"

eliminating the associated transformers and heavy carrier
drive power requirements.

BASE OECOUPLING

CARRIER INPUT

At 30M Hz, carrier and signal leaks are typically -40dB
referred to the desired output product frequency.
Intermodulation products are -45dB with a 60 mV rms
input signal.
The SL1641 C is a version of the SL 1640C intended
primarily for use in receiver mixer applications for which it

V+

2

7

3

6

SIGNAL INPUT

OUTPUT 2

,

5

OUTPUT 1

'E"'~

offers a lower noise figure and lower power consumption.

BASE DECOUPLING

No output load resistor is included and signal leakage is
higher, but otherwise the performance is identical to that of
the SL 1640C.

CARRIER INPUT
V+

2

7

3

6

L

5

SIGNAL INPUT

OUTPUT

DPB
Fig. 1 Pin connections (top view)

FEATURES
•
•
•
•
•
•

Low Carrier Leak
Low Signal Leak
Low Intermodulation Products
Low Carrier Power Requirement
Wide Bandwidth
Minimal External Components

APPLICATIONS
•

SSB and DSB Generators

•
•

Detectors
Phase Comparators

•

Mixers

Fig.2 Circuit diagram of SL 1640C

365

SL1640C SL1641C

I

u
r .•. jllrii
t ':t-.

•• , l..
1 J~
I

I /

-'~' I'I

l

I

1

Fig.3

I

'

"

"II

1

Circuit diagram ofSL1641C

OPERATING NOTES
The SL 1640C circuit requires ihput and output coupling
capacitors which normally should be chosen to present a
low reactance compared with the input and output
impedances (see electrical characteristics). However, for
minimum carrier leak at high frequencies the signal input
should be driven from a low impedance source, in which
case the signal input capacitor reactance
comparable with the source impedance.

should

r-------~--------~---+6V

be

Rl
10k

Pin 2 must be decoupled to earth via a capacitor which
presents the lowest possible impedance at both carrier and
signal frequencies. The presence of these frequencies at
pin 2 would give rise to poor rejection figures and to
distortion.
If the emitter follower is used, an external load resistor

must be provided to supply emitter current. The quiescent
output voltage from the emitter follower (pin 6) is +4.6V.

Fig. 4

Signal and carrier leak adjustments

To achieve maximum rejection figures at high frequencies,

pin 1 (which is connected to the header) should be
connected to earth and effective HT decoupling should be
employed. The DC impedance should not exceed
800 ohms.
The SL1640C/1641 C may be used with supply voltages
of up to +9 volts with increased dissipation.
Signal and carrier leaks may be minimised with 10kn
potentiometers and 330kn resistors connected as shown in
Fig. 4. R 1 is adjusted to minimise signal leak; R2 to
minimise carrier leak.

366

The SL 1641C is very similar to the SL1640C and similar
operating notes apply. A current output is provided in the
SL 1641C to enable a tuned circuit to be directly
connected. If both output sidebands are developed across
the load (i.e. wideband operation), the AC impedance of
the load must be less than BOOn. If the output at one
sideband frequency is negligible, the AC impedance may be
raised to 1.6kn. It may be further raised if it is not desired
to .use the maximum input swing of 210mV rms. The DC
resistance of the load should not exceed BOOn.

SL 1640C

SL 1641 C

ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Supply voltage = +6V
Temperature = +25°C
Characteristics
Conversion gain

Signal leak

Circuit

Typical Value

Units

SL1640C
SL1640C

0
-40

dB
dB
Signal: 70mVrms, 1.75MHz
Carrier: 100mVrms, 28.25MHz
Output: 30MHz

]
[Signal output
Desired sideband output
SL 1640C

-40

dB

I ntermodulation products

SL 1640C

-45

dB

Conversion gain

SL1641C

0

dB

Signal leak

SL1641C

-18

dB

Carrier leak
I ntermodulation products

SL1641C
SL 1641C

-25
--45

dB
dB

Carrier input impedance

Both
SL 1640C
SL 1641C
SL 1640C
SL 1641C
SL1640C
SL 1641C
SL1640C
SL 1641C
SL 1640C
SL1641C
Both
Both
Both

1k£2#4pF
500£2115pF
1k£2114pF
350£2#8pF
8pF
210
250
12
10
15
12
±2
±2
±1

Carrier leak

J

Test conditions

Ucarrier output
Desired sideband output

Signal input impedance

Output impedance
(see Operating Notes)
Max. input before limiting
Quiescent current consumption

Noise figure
Signal leak variation
Carrier leak variation
Conversion gain variation

Signal 1: 42.5mVrms, 1.75MHz
Signal 2: 42.5mVrms, 2MHz
Carrier: 100mVrms, 28.25MHz
Output: 29.75MHz
400£2 load
Signal: 70mVrms, 30MHz
Carrier: 100mVrms, 28.25MHz
Output: 1.75MHz
Signal 1: 42.5mVrms, 30MHz
Signal 2: 42.5mVrms, 31MHz
Carrier: 100mVrms, 28.25MHz
Output: 3.75MHz

Output 1

mVrms
mVrms
mA
mA
dB
dB
dB
dB
dB

O°C to +70°C

with temperature

ABSOLUTE MAXIMUM RATINGS
Storage temperature
Operating temperature

Supply voltage

-55°C to +175°C
O°C to +70°C
+9V

367

368

SL2363C & SL2364C
VERY HIGH PERFORMANCE TRANSISTOR ARRAYS
The SL2363C and SL2364C are arra"3 of tranSistors
internally connected to form a dual long-tailed pair with tail
transistors. They are monolithic integrated circuits manufactured on a very high speed bipolar process which has a
minimum useablefTof 2.5 GHz, Itypically 5GHzI
The SL2363 is in a 10 lead T05 encapsulation
The SL2364 is in a 14 lead DIL ceramic encapsulation

FEATURES
•

Complete Dual Long Tailed Pair In One Package

•
•

Very High fT - TYPically 5 GHz
Very Good Matching Including Thermal Matching

SL2363C

CM10

SL2364C

DG14

APPLICATIONS
•

Wide Band Amplification Stages

•

140 and 560 MBlt PCM Systems

•
•

Fibre OptiC Systems
High Performance Instrumentation

•

Radio and Satellite Communications

Fig 1 Pin connections (top view)

ELECTRICAL CHARACTERISTICS
Test condillons (unless otherwise stated I:
Tamb = 22°C ±2°C

Characteristics
BVCBO
LVCEO
BVEBO
BVCIO
hFE

IT

LWBE (See note 1)
l>VBE/TAMB
CCB
CCI

Value
Min,

Typ.

10
6
2.5
16
20
2.5

20
9
5.0
40
SO
5
2

Max.

Units
V
V
V
V

5
0.5
1

GHz
mV
pF
pF

Conditions
IC= lOIlA
IC = 5mA
IE = lOIlA
IC = lOIlA
IC = SmA VCE = 2V
IC (Tall) = SmA VCE = 2V
IC (Tail) = S rnA VCE = 2V
IC (Tail) = S rnA VCE = 2V
VCB = 0
VCB = 0

369

TYPICAL CHARACTERISTICS

!

I

'---t
~

I

-J

~

,

,

,
I!,.- -

I

I
I

0

------

I
"-

--

~

9
fT NORMALISED AT .20 oC
VCE

,

I

Ie

~

= 2\1
45mA

I
\

0

I

I

,
lelmA)

Fig. 2 Collector current

I

,
\

I
TEMPERATURE (OC)

Fig. 3 Chip temperature

370

"'-

""

~

SL3045C SL3046C

•

SL3000 SERIES

Plessey
Semiconductors

TRANSISTOR ARRAYS

SL3045C SL3046C
TRANSISTOR ARRAYS
The SL3045 and SL3046 are monolithic arrays of five
general purpose high frequency transistors arranged as
a differential pair and three isolated transistors. The
transistors feature a VBE matching of, typically, better
than
5mV between any pair, an fr of 300M Hz and a
low noise figure.
The SL3045 is available only in a ceramic.dual-in-line
package; the SL3046 is packaged in plastic dual-in-line.

V 1~ 1i ~
2

1

5

4

6

e

':I

3

11

12

10

I/,.

13 SUBSTRATE

DG14
Fig. 1 Pin connections

ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated)

Static Characteristics

Symbol

Value

Characteristic

Min,
BV EBO

Emitter-base breakdown

BVCEO
BVCBO
BV clO
ICED
ICBO
VBE(ONI

Collector-emitter breakdown
Collector-base breakdown
Collector-substrate ireakdown
Collector cut off current
Collector cut off current
Base emitter voltage

VCE(SATI
hF E

Collector-emitter saturation
Static forward current-transfer
ratio

110

L\ 'BE 1

Input offset current-

differential pair

I nput offset voltagedifferential pair

L\ VBE2
a L\ BE
~
aVBE(ONI
a-T---

Input offset voltage-isolated
transistors
Temperature co-efficient of
input offset voltage
Temperature co-efficient of
base emitter-voltage

Typ,

Units

V

0,5
4
0.71
0.78
0.3
120
100
50
0.2

V
V
V
IlA
nA
V
V
V

2

IlA

IE ~
Ic ~
Ic ~
Ic ~
VCE
VCB
VCE
VCE
IB ~
VCE
VCE
VCE
VCE

0.35

5

mV

VCE

~

3V Ic

~

lmA

0.45

5

mV

VCE

~

3V Ic

~

lmA

IlVtc

VCE

~

3V Ic

~

lmA

mVtC VCE

~

3V Ic

~

lmA

5
15
20
20

40

Test conditions

Max.

50
70

2
1.8

10ilA
lmA
10ilA
10ilA
~ 10V,I B ~ 0
~ 10V, IE ~
~ 3V Ic ~ lmA
~ 3V Ic ~ lOrnA
lmA Ic ~ lOrnA
~ 3V Ic ~ lOrnA
~ 3V Ic ~ lmA
~ 3V Ic ~ 10ilA
~ 3V Ic ~ lmA

a

371

Sl3045C

Sl3046C

Dynamic Characteristics
Value

Characteristic

Symbol

Min.
N.F.

Wide band noise figure

Y le

Forward transfer admittance
Input admittance
Output admittance
Reverse transfer admittance
Forward current transfer ratio

Vie

Y oe
Y re
hie
hie
hoe
h re

3.5

31-i1.5
O.3-jO.04
0.003+jO.04
0.000-jO.003
110
3.5
15.6

Short eet. input impedance

Open ect. output admittance
Open circuit reverse voltage

transfer ratio
Gain·bandwidth product
Emitter-base capacitance
Collector-base capacitance
Collector-substrate capacitance

I,
CIB
COB
CCI

Typ.

Units

Test conditions

dB

1 = 10Hz to 10kHz
VCE = 3V Ic = 100l1A
Source resistance == 1 kn

Max.

mmho

mmho
mmho
mmho

1 = 1MHz
VCE = 3V Ic = 1mA

kQ
I1mho

1 = 1kHz
VCE= 3Vl c=lmA

1.8x10- 4
500

600
1.7
1.5
3.0

MHz
pF
pF
pF

V CE = 3V
V EB = 3V
VCB = 3V
Vcs = 3V

CHARACTERISTIC GRAPHS

RI:

I,

~----------+-----~-------~

,

ol~____
Ie

Ie I mAl

5

,/

/'

VCE"'W

/
/

/

V

/

/

/
Ie (mAl

372

(mAl

Ie
'E
IC
Ie

= 3mA
=0
=0
=0

SL3045C

V

7

VCE"'W

'Be

~
w

06

p

/

./'

I
I

/

II

m

----

",I
v

+-!e

/

ABSOLUTE MAXIMUM RATINGS
All electrical ratings apply to individual transistors.
The isolation pin must always be negative with respect
to the collectors.
VCBO = 20V VEBO - 15V Ic
50mA I B ~. 25mA
VCEO
15V VCIO
20V IE
50mA
SL3045C- DG
Storage temperature
-55 Cto ·175 C
Junction temperature
·175 C
Package dissipation
750mW (derate linearly
from 55 C to
175 C)
SL3046C - DP
Storage temperature
Junction temperature
Package dissipation

-55 C to
125 C
125 C
500mW (derate linearly
from 55 C to . 125 C)

(rnA)

373

374

S L3081 D S L3082 D

•

Plessey
Semiconductors

SL 3000 SERIES
TRANSISTOR ARRAYS

S L3081 0 S L3082 0
GENERAL PURPOSE HIGH CURRENT NPN TRANSISTOR ARRAYS

The SL3081 and SL3082 consist of seven high current
(100mA

max)

silicon

N PN transistors on a common

monolithic substrate. The SL3081
common

emitter

configuration

and

is connected in a
the

SL3082

is

connected in a common collector configuration.
The SL3081 and SL3082 are capable of directly driving
both incandescent seven segment displays and LED seven
segment displays.
A separate substrate connection is provided, for
Fig. 1 SL3081 pin connections

maximum flexibility in circuit design.

FEATURES
•

Seven Transistors Permit a Wide Range of
Applications

•

Common Emitter (SL3081) or
Collector (SL3082) Configuration

Common

•

High Ic 100mA max (each transistor)

•

LowVCESAT0.4VTyp@50mA

APPLICATIONS
•
•

Drivers for Incandescent Display Devices
SL3081
Driver
for
Common
Anode
7-Segmenl LED Displays

•

SL3082
Driver
for Common Cathode
7-Segment LED Displays
MOS Clock and Calculator Display Interface
Circuits

•
•
•

Relay and Solenoid Drivers
Thyristor and Triac Control Circuitry

5

o

SUBSTRATE

Fig. 2 5L3082 pin connections

ABSOLUTE MAXIMUM RATINGS

All electrical ratings apply to individual transistors;
termal ratings apply tu total package dissipation.
The collector of each transistor of the SL3081 and
SL3082 is isolated from the substrate by an integral diode.
The substrate must be connected to a voltage which is more
negative than any collector voltage in order to maintain
isolation between transistors and to provide normal
transistor operation. To avoid undesired coupling, the
substrate (pin 5) should be ma;ntained at either DC or
signal lAC) earth.
Electrical Ratings
V CEO = 12V, V CBO = 20V,\VEBO = 5V, VCIO = 20V,

Ic = IE = 100mA
Power dissipation

500mW

Thermal Ratings
Storage temperature
Junction operating temperature

_55° C to + 175° C

+175°C

375

S L3081 D S L3082 D

ELECTRICAL CHARACTERISTICS

@

T A = 22°C ±2°C
Value

Symbol

Characteristic

Collector-base breakdown
Collector-substrate breakdown
Collector-emitter breakdown
Emitter-base breakdown
DC forward current transfer ratio

l

C,,",",""m
"'" """,""0
SL3081, SL3082
SL3081
SL3082
Collector cut-off current

Collector cut-off current

376

I

BVCBO
BV clO
BV CEO
BV EBO
hF E

Min.

Typ.

20
20
12

50
70
20
5.6
68
70

5
30
40

Units

Conditions

V
V
V
V

IC ~ 500/lA, IE ~ 0
ICI ~ 500/lA IB ~ 0
I C ~ 1 mA, I B ~ 0
IE ~ 500/lA
VeE ~ 0.5V, Ic ~ 30mA
VCE ~ 0.8V, Ic ~ 50mA

Max.

iVCEISATI
0.27
0.4
0.4
CEO
'
'CBO

0.5
0.7
0.8
10
1

V
V
V
/lA
/lA

Ic ~ 30m A, 'B ~ 1mA
Ic ~ 50mA, IB ~ 5mA
Ic ~ 50mA, 'B ~ 5mA
VCE ~10V,IB ~O
VCB ~ 10V, IE ~ 0

SL3083[

•

Plessey
Semiconductors

SL 3000 SERIES
TRANSISTOR ARRAYS

SL3083D
GENERAL PURPOSE HIGH CURRENT NPN TRANSISTOR ARRAY

The SL3083 is an array of five independent high current
(100mA max) NPN transistors on a common monolithic

substrate. I n addition, two of the transistors (TR 1 and
TR2) are matched at low currents (i.e. lmA) for
applications in which offset parameters are of special

importance.
Independent connections for each transistor plus a
separate te'rminal for the substrate permit maximum
flexibility in circuit design.

OG16 OP16
Fig. 1 SL3083 pin connectiorls

FEATURES

••
•

ABSOLUTE MAXIMUM RATINGS
lClOmA Max
LuwVCESAT
Cl7VMax@50mA
Matched Pair (TRl dwl TR21
f\,

VB t ±5mV Max

110 L'':JpA Max@ lmA

•

c, Independent T rcH1S1St ors
Substrale Cor1l18ctlon

pi us

Scpara te

Electrical Ratings
VCEO = 12V VCBO = 20V, VEEO = 5V, VCIO = 20\
Ic = IE = 100mA
Power dissipation
500m'
Thermal Ratings
Storage temperature

Junction operating temperature

APPLICATIONS
•

Siqnill Processtnc] and SWllchlng
Operating From DC to VH F

•

Lamr, ReidY, SolcIlClld Driver

•
•

Differential Amrlifier
T(]mperalure Compensated Amplltler

•

Thyristor Flrlnc]

Syslems

_55°C to +175°
+175 0

All electrical ratings apply to individual transistor
thermal ratings apply to total package dissipation.
The collector of each transistor of the SL3083 is isolat!
from the substrate by an integral diode. The substrate mu
be connected to a voltage which is more negative than ar
collector voltage in order to maintain isolation betweE
transistors and to provide normal transistor operation. 1
avoid undesired coupling, the substrate (pin 5) should I
maintained at either DC or signal (AC) earth.

377

Sl3083D

ELECTRICAL CHARACTERISTICS @ TA

= 22°C ±2°C
Value

Characteristic

Units

Symbol

Collector-base breakdown
Collector-emitter breakdown
Collector-substrate breakdown
Emitter-base breakdown

BVceo
BV CEO
BVclO
BVEeo
Collector cut off current
ICEO
Collector cut off current
Iceo
DC forward current transfer ratio
hFE
DC forward curreht transfer ratio
hFE
Base emitter voltage
VeE (ON)
Collector emitter saturation
~CE (SAT)

Min.

Typ.

20
12
20
5

50
20
70
5.6

40
40
0.65

Condition

Max.

10
1

V
V
V
V
Il A
Il A

120
80
0.74
0.4

0.85
0.7

V
V

1.2
0.7

5
2.5

mV
Il A

Ic = 1001lA, IE = a
Ic = lmA, Ie =0
ICI = 1001lA, IE = a Ie = 0
IE = 500IlA, Ic = a
'ICE = 10V.le =0
Vce =lOV,IE=O
VCE = 3V Ic = lamA
VCE = 3V Ic = 50mA
VCE = 3V Ic = lamA
Ic = 50mA, Ie = 5mA

FOR TRANSISTORS T1 AND T2 (As a differential amplifier)
I nput offset voltage
I nput offset current

378

1I VeE
110

VCE = 3V
Ic = lmA

Sl3127C

•

Plessey
Semiconductors

SL3000 SERIES
TRANSISTOR ARRAYS

SL3127C
HIGH FREQUENCY NPN TRANSISTOR ARRAY

The SL3127 consists of five general-purpose silicon NPN
transistors on a common substrate. The monolithic
canstruction provides close electrical and thermal matching
of the five transistors. Each of the transistors exhibits a low
noise figure (3.6 dB typo @ 60 M Hz) and a value of fT
greater than 1.5 G Hz. Each of the transistors is individually
accessible and a separate substrate connection is provided,
which is used to ensure isolation between each transistor.
The SL3127 is pin compatible with RCA CA3127E.
DG16

ABSOLUTE MAXIMUM RATINGS at TA = 25°C
Fig. 1 Pin connections, top view

Power dissipation
Anyone transistor
Total package
Ambient temperature range
Storage
Operating

150mW
300mW
-55 to +150°C
-55 to 125°C

The following limiting values apply to each device:

A~~IENT!

,

,

V

N

§I ;

Collector to emitter voltage V CEO
Collector to base voltage VCBO
Collector to substrate V C I 0 •

15V
20V
20V
20mA

Collector current Ie

,

/

I

/:

I'---

........

V
,

0

*The collector of each transistor is isolated from the
substrate by an integral diode. The substrate (pin 5) must
be connected to the most negative point in the external
circuit to maintain isolation between the transistors.

i

TEJPERATURE 't2S1o c
COLLECTOR -E~ITlER YOLTA(,-E ,6V

.

COLLECTOR CUARENT (Ie) 1m A)

Fig. 2

Typical gain-bandwidth product (fr)
V. coJ/ector current

II II
II II

0
.~BIENl

TE~PER"TURE 0 +M·C
COLLECTOR-EMITTER VOLTAGE" 6'1

0

-0

t-

o

0

0

COllECTOR CURRENT-(Ie) (mA)

Fig. 3

DC forward current transfer
ratio v. collector current

379

SL3127C

ELECTRICAL CHARACTERISTICS at TA = +25°C for each transistor
Static characteristics
Value
Characteristic

Symbol

Collector·base breakdown voltage
Coliector-emitter breakdown voltage
Collector·substrate breakdown voltage
Emitter·base breakdown voltage
DC forward current transfer ratio

Base-emitter voltage
Collector-emitter saturation voltage
Magnitude of difference in VB E
Magnitude 01 difference in 18

Conditions

Units

BV C8 0
BV CEO
BVclO
BVE80
hFE

V8E
VCEISAT)
"V 8 E

Min.

Typ.

20
15
20
4.5

30
18
55
5.5

40
40
40
0.64

95
100
100
0.74
0.26
0.5
0.02

"'8

Max
Ic
Ic
Ic

V
V
V
V

0.84
0.5
5
3

~

~
~

lJ1A, IE
1J1A, 18
lJ1A, 18

~

0

~O
~O,

IE

~O

IE~10J1A,lc~0

VCE ~ 6V
Ic ~ 5mA
Ic ~ lmA
Ic ~ O.lmA
VCE ~ 6V, Ic ~
Ic ~ 10mA, 18~
VCE ~ 6V, Ic ~
VCE ~ 6V, Ic ~

V
V
mV
J1A

lmA
lmA
lmA
lmA

Dynamic Characteristics
Value
Units

Symbol

Characteristic

Min.
Gain-bandwidth product
Noise Figure
Knee of Ilf noise figure curve

Typ.

IT
NF

1.6
3.6

GHz
dB

-

<1

kHz

c

II

~--

,

TA:-SSOC

I-- 1-1-==
l-- l-- l-

e

11

n

- I--

TA- +25°C

,

,->-

>---

,r.:::::::===:

---

H11
II

~12S0C

,
~

-

..-

(.- ~

COlLECTOR CURRENT (Ie) (rnA)

Fig.4 Base-emitter voltage (VBE) v. collector
current

380

Conditions

Max.

-

VCE ~ 6V, Ic ~ 5mA
VCE ~ 6V, Rs ~ 20011
I ~ 60MHz, Ic ~ 2mA
VCE ~ 6V, Rs ~ 20011
Ic ~ 2mA

1-1-

I - l-

1--- f.-

SL3127C

I - - - f-

I

= t2S"C
COLLECTOR-EMITTER

rA,

I

I

I

VOLTAGE: 6 ..

SOURCE IMPEDANCE RS
FREQlJENCY o60MHz

0

200n

01\

-m

;

~

6-0

0\

"'-

U-

Z

0
01---

f-

""----

---

--

I-

0
o

"'

,·0
COLLECTOR CURRENT (It) (mA)

Fig. 5

Noise figure v. collector current

381

382

SL3145C

•

Plessey
Semiconductors

SL300 SERIES
MATCHED TRANSISTORS

SL3145C
2·5GHz TRANSISTOR ARRAY

The SL3145 is a monolithic array of five general purpose
high frequency transistors arranged as a differential pair and

V 1~ 1~ ~

three isolated transistors.

2

FEATURES
•
•
•
•

fT~2.5GHZ
Wideband NOise Figure ~ 3dB
V BE Matching ~ Better than 5 mV
Pin Compatible with SL3045

1

5

I.

~

e

9

11

12

11.

10

13 SUBSTRATE

DG14
Fig. 1 Schematic and pin diagram

ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise stated):
T amb ~ +25°C ±5°C

Characteristic

Base-I solation Voltage
Emitter-base breakdown

Collector-emitter breakdown

Collector-base breakdown
Collector-substrate breakdown

Min.
10
5
8
12
20

Base-emitter voltage
Static forward current
transfer ratio
Input offset current

30

Value
Typ.

Max.

Units
V
V
V
V
V
V

15
24
40
0.73
80

Conditions
Is = lilA
Ie = lOIlA
Ie = 1Oil A
IE = 1Oil A
IC = lOIlA
VCE = 2V, Ic
VCE ~ 2V, Ic

= lmA
= lmA

0.2

2

I1A

VCE

= 2V,

Ic

= lmA

0.35

5

mV

VCE

= 2V,

Ic

= lmA

0.45

5

mV

VCE

= 2V,

Ic

= lmA

2

I1VtC

VCE

~

1.6

mVtC

VCE

= 2V,

Wideband noise figure

3.0

~dB

Gain-Bandwidth product

2.5
0_35
0_95
0_3
0.6
1.2

(differential pair)
Input offset voltage
(differential pair)
Input offset voltage
(othersl
Temperature coefficient
input offset voltage
Temperature coefficient

base emitter voltage

VCEISATI
VSEISATI
Icso
ICIG
Isio
Ceb
Ceb
Cel

OA
0.4
0.8

GHz
V
V
nA
nA
nA
pF
pF
pF

2V, Ic
Ic

~

lmA

~

lmA

VCE = 2V, Ic = 100l1A
Rs = lkn
VCE ~ 2V, Ic = lOrnA
Ic = lOrnA, Is = lmA
Ic = lOrnA, Is ~ lmA
Vcs = 16V
VCI ~ 20V
VSI ~ 10V
Bias = OV
Bias = OV
Bias = OV

383

SL3145C

I
I

1

~+-

VCE =2V

i<-:"

I

'\

I

I

Fig. 2 Tvpical variation of hfe with Ie

i

I

~-t-

'" "

+-

I--

,,- +-- I--

\

r--V

Fig. 4 Typical V BE mismatch v.

384

I

i

i

I

I

.

I

2';

!

,

I

1

l_

Fig. 3 Typical fr v. collector current

(IT

~

I/h le , I

~

200M Hz)

Junction operating temperature:
V CBO : 12V
V EBO : 5V
V CEO : 8V
VCIO: 20V

-55°C to +150°C
150°C
IC :20mA

Maximum individual transistor dissipation:
ves

I

,

1 1
,

~

Storage temperature:

-,l

N

I---+---l

ABSOLUTE MAXIMUM RATINGS

i

I

E

)

I

- I,
>

vCB

V

.

_L_

1

!

/1

ld
-f--

I

Ie

1/

~

Total package dissipation:

200mW
350mW

SL3146A&C

•

SL3183A&C

SL3000 SERIES

Plessey
Semiconductors

TRANSISTOR ARRAYS

SL 3146A, SL 3146C
SL3183A, SL3183C
HIGH VOLTAGE TRANSISTOR ARRAYS

Y'5]

The Plessey Semiconductors SL3146A, SL3146,
SL3183A and SL3183 are general·purpose high·voltage
silicon NPN transistor arrays on a common monolithic

substrate.

SL3146A and SL3146 (high voltage versions of SL3046)
each consist of five transistors with two of the transistors
connected to form a differential pair. These types are

TRI

recommended for use in the DC to VHF range. The
SL3146A and SL3146 are supplied in either 14 lead plastic
DIL package (temperature range _40°C to +85°C) or
14·lead ceramic DIL package (temperature range _55°C to
+125°C).
SL3183A and SL3183 consist of five high·current

TR2

3

'r~5~"~"
TR3

6

7

TRI,

9

10

TRS

12

13

IOPt6
Fig. 1 SL3146/A pin connections

transistors with independent connections for each
transistor. In addition, two of these transistors (TR1 and

TR2)

are

matched

at

low current

(i.e.

1rnA)

for

applications

where offset parameters are of special
importance. A special substrate terminal is also included for

greater flexibility in circuit design. The SL3183A and
SL3183 are high·voltage versions of the SL3083 and are
supplied in either 16·lead plastic DIL package (temperature
range _40°C to +85°C) or 16·lead ceramic package
(temperature range _55°C to +125°C).

IOG16
Fig. 2

SL3183/A pin connections

FEATURES
APPLICATIONS
•
•
•
•
•

Matched General Purpose Transistors
VBE Matched to ±5mV Max.
Operation from DC to 120MHz (SL3146/A)
Low Noise Figure: 3.2dB Typ. @ 1kHz
(SL3146/A)
High Ie 75mA Max. (SL3183/A)

•
•
•
•

iii

Signal Processing Systems, DC - VHF
Custom Designed Differential Amplifiers
Temperature Compensated Amplifiers
Lamp and Relay Drivers (SL3183/ A)
Thyristor Firing (SL3183/ A)

385

C/)

ELECTRICAL CHARACTERISTICS@TA = +25°C (SL3146/A)

w

ex>

r-

!::l

'"~""

Static Characteristics

0>
Value
Characteristic

Collector-base breakdown

BV CBO

Collector-emitter breakdown

BVCEO

Collector-substrate breakdown

BVvlO
BVEBO

Emitter-base breakdown
Collector cut-off current
Collector cut-off current
DC forward current transfer ratio

Min.

Typ.

50
40
50
5

72
56
72
7.5

ICBO

VCE(SAT)

85
100
90
0.73
0.33

.6.VSE

0.48

hFE
30
0.63

VSE(ON)

Collector-emitter saturation

Max.

Min.

Typ.

40
30
40
5

72
56
72
7.5

0.83

0.63

(1
C/)

r-

!::l

V
V
V
V
pA
nA

5
100
85
100
90
0.73
0.33

30

i2"

Test Conditions

I

Max.

5
100

'CEO

8ase-emitter voltage

SL3146C

SL3146A

Symbol

I
Units I

Ie = lOpA, IE =0
Ie == lmA, Ie =0
lei'" 10,uA, Ie = 0, la =
Ie = lO,uA, Ie =0
VeE = lOV, Ie =0
VeE = lOV, Ie =0
Ie = lOrnA
Ie'" 10,uA
VeE = 5V
Ie'" lmA
VeE = 3V, Ie == lmA
Ie = lOrnA, Ie '" lmA

-

0.83

V
V

'"i2"'"
~

a

(1

For Transistors TR 1 and TR2

(as a Differential Amplifier)
Input offset voltage
Base-emitter temperature coefficient

3V SE (ON)

0.5

0.48

0.5

1.9

1.9

~-aT~-

I

mV
ImV/:C

VeE =5V, IE = lmA
VeE

0

5V, IE

0

lmA

1

allVBE

Input offset voltage temperature

~

coefficient
Input offset current

I

110

I
I

Low frequency noise figure

NF

3.25

h"

100
2.7
15.6

Equivalent Circuit Characteristics
Forward current transfer ratio

hie

Open-circuit output admittance
Open-circuit reverse voltage transfer

ho,

I

CI

VCE "" 5V, IC1 "" 1C2 "" lmA

I

VCE == 5V, IC1 == IC2 == lmA

IJ.A

i-r
•

100
3.5
15.6
1.8

1.8 x 10- 4

h"

I

2

325

I

Short-circuit input impedance

ratio

-T

lilVI

I

0.3

2

Dynamic Characteristics

Low Frequency Small Signal

I

1.1

1.1
0.3

X

10-4

I

f"" 1kHz, VCE '" 5V, Ie == lDDvA, Rs

:=

lkil

I

I krl-

I"~O

f'" 1kHz, VCE == 5V, Ie = lmA

Admittance Characteristics
Forward transfer admittance

Y"

31~j1.5

31~j1.5

mmho

Input admittance
Output admittance

Vie

0.35+jO.04

0.35+jO.04

mmho

Yo,
Yeo
f,
C BE
COB
Ce1

0.001·jO.03
0.001-jO.001
500
0.7
0.37
2.2

0.001+jO.03
O.OOl-jO.OOl
500
0.7
0.37
2.2

mmho

Reverse transfer admittance
Gain bandwidth product
Emitter-base capacitance
Collector-base capacitance
Collector-substrate capacitance

300

300

f'" lMHz, Vee'" 5V, Ic == 1mA

mmho

MHz
pF
pF
pF

VeE = 5V, Ie '" 3mA
VES =5V, Ie =0
Vcs=5V,lc"'O
Vel =5V, Ic =0
--------

SL3146A&C SL3183A&C
ELECTRICAL CHARACTERISTICS@ TA

~

+25°C (SL3183/A)

Static Characteristics

~h:="~:'~C--~ TsVmbol 1-

[-------- --- -r----t~ TVPr'x
I

--

-~_-~~O=d;t;ons~~,

SL3183A _+-_--,-_---,-_--1'---j__

,

For each transistor

Collector-base breakdown voltage
/
Collector-emitter breakdown voltage
Col~ector.substrate breakdown voltage '/
Emitter-base breakdown voltage
Collector cut-off current
Collector cut-off current
DC forward current transfer ratio

BVCBO
BV CEO
BVCIO

50
40
50

40
30
40

V
V
V

IV

I

BVEBO

10

ICEO

i

'CBO
hFE

Base-emitter voltage
Collector-emitter saturation voltage

I

\0

0.75 ' 0.85
1.7
3.0

I

40
40
0.65

0.75
1.7

Absolute input offset voltage
Absolute input offset current
• A maximum dissipCltion uf 5 trClnslstors x 150mW

V
V

IE == SOO/1A, Ie " 0
VeE == lOV, 18 =0
VeE = 10V, IE =0
VeE" 3V, Ie == lOrnA
VeE = 5V, Ie = SOmA
VCE=3V,l c =10mA
Ie'" SOmA, 18 = SmA

veE = 3V, Ie = lmA
VeE = 3V, Ie = lmA
~

750mW is possible for d pdr1icular appliCation

ABSOLUTE MAXIMUM RATINGS@TA

Power dissipation (per transistor)
Power dissipation (total package)
Up to +55°C
Above +55°C
Operating temperature range
Plastic package
Ceramic package

.uA
/ pA

Ie'" 100.uA, IE'" 0
Ie = lmA, '8 = 0
lei" lOO.uA,IB =D,IE =0

= 25°C

SL3146C

SL3146A

SL3183C

SL3183A

300

300

500

500

mW

750
750
Derate linearity 6 - 67

750

mW
mW/oC

750

to +85
to +125

~40

~65 to +150
-65 to +175

~65

~40

~55

~55

to +85
~40 to +85
~40 to +85
to +125 -55 to +125 -55 to +125

°c
°c

Storage temperature range

Plastic package
Ceramic package

~65

to +150
to +175

~65
~65

to +150 -65 to +150
to +175 ~65 to +175

°c
°c

The foliowing ratings apply to individual transistors
Coliector-emitter voltage, V CEO
Coliector-base voltage, VCBO
Coliector-substrate voltage, V C 10
Emitter-base coltage, VEBO
Coliector current, Ic

30
40
40
5
50

40
50
50
5
50

Base current, I B

30
40
40
5
75
20

40
50
50
5
75
20

V
V
V
V

mA
mA

"*The collector of each transistor is isolated from the substrate by an integral diode.
NOTE: The substrate pin must always be negative with respect to the collectors.

387

388

Sl6000 SERIES
COMMUNICATIONS CIRCUITS

Sl6270C
GAIN CONTROLLED PREAMPLIFIER
The SL6270C is a silicon integrated circuit combining
the functions of audio amplifier and voice operated
gain adjusting device (VOGAD).
It is designed to accept signals from a low sensitivity
microphone and to provide an essentially constant
output signal for a 60dB range of input. The dynamic
range, attack and decay times are controlled by external

MAIN AMP
OUTPUT

components.

PAEAMPINPUI

eMS

FEATURES
•
•
•
•

Fig. 1 Pin connections, SL6270C - eM

Constant Output Signal
Fast Attack
Low Power Consumption
Simple Circuitry

AGC TIME CONST
PREAMPOUTfUT

Audio AGC Systems
Transmitter Overmodulatlon Protection
Tape Recorders

QUICK REFERENCE DATA
•
•

Supply Voltage: 4.5V to 10V
Voltage Gain: 52dB

MAIN AMP OUTPUT

2

1

MAIN AMP INPUT

Vee

J

{';

OV

PREAMP INPUT

4

5

PREAMPINPUI

APPLICATIONS
•
•
•

Os

UPS
FIg. 2 Pm connectIons, SL6270C - DP

"o,~c

~~_~~~~

:I

1
2_ 7

~;T~M~~

_ _ _ _ -,

~"":
I

I
B

Supply voltage: 12V
Storage temperature: -55 c C to +15OCC
Operating temperature: -55 c C to +85 c C

MAIN AMP
OUTPUT

I (lkn MIN

ABSOLUTE MAXIMUM RATINGS

LOADI

I
I
I
I

________ J
AGe TIME
CONSTANT

Fig. 3 SL6270C block diagram

389

ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Supply voltage Vee: 6V ct 0.5V
Input signal frequency: 1kHz
Ambient temperature: -30 c e to +85 c e
Test circuit shown in Fig. 4

Value
Characteristic

Min.

Supply current
Input impedance
Differential input
impedance
Voltage gain
Output level
THD

Typ.

5
100

180

200
40
55

300
52
90
2

Max.

Units

10

mA
0

140
5

0
dB
mVrms
%

Conditions
Pin 4 or 5
72~V rms balanced input
18mV rms balanced input
90mV rms balanced input

.(]--+-----jl~
10"

OUTPUT
(1k.n. MIN LOAD)

.
10kO
Voltage gam ~ 6800
Upper frequency response 10kO/4.7nF = 3kHz
Lower frequency response 6800/2.2~F ~ 300Hz
Fig. 4 SL6270C test and application circuit

APPLICATION NOTES
Voltage gain
The input to the SL6270e may be single ended or
differential but must be capacitor coupled. In the

single-ended mode the signal can be applied to either
input, the remaining ipput being decoupled to ground.
Input signals of less than a few hundred microvolts
rms are amplified normally but as the input level is
increased the AGe begins to take effect and the output
is held almost constant at 90mV rms over an input
range of 50dB.
The dynamic range and sensitivity can be reduced by
reducing the main amplifier voltage gain. The connection of a 1 k resistor between pins 7 and 8 will reduce
both by approximately 20dB. Values less than 6800
are not advised.
Frequency response
The low frequency response of the SL6270e is
determined by the input, output and coupling capacitors. Normally the coupling capacitor between pins 2
and 7 is chosen to give a -3dB point at 300Hz,

390

Fig. 5 SL6270C frequency response

corresponding to 2.2~F, and the other capacitors are
chosen to give a response to 100Hz or less.
The SL6270e has an open loop upper frequency
response of a few MHz and a capacitor should be
connected between pins 7 and 8 to give the required
bandwidth.
Attack and decay times
Normally the SL6270e is required to respond
quickly by holding the output level almost constant as
the input is increased. This 'attack time', the time taken
for the output to return to within 10% of the original
level following a 20dB increase in input level, will be
approximately 20ms with the circuit of Fig. 4. It is
determined by the value of the capacitor connected
between pin 1 and ground and can be calculated
approximately from the formula:
Attack time

~ O.4ms/~F

.The decay time is determined by the d;scharge rate of
the capacitor and the recommended circuit gives a
decay rate of 20dB/second. Other values of resistance
between pin 1 and ground can be used to obtajn
different results.

11111111
11111111

,,'.,

VS' +6'0', TA ,= .2SoC, ! ·lkHz

0

~

>

~. 0

= ,,
~50
~4

,

II

/

~. 0

,

0,

,
0

INPUT

(RMS)

Fig. 6 Voltage gain (single ended input)

0

0

0

J'

"'5.11'0', h1kHz

0

./

0

Of--0

/

......-

SECONO HARMONIC

/

THIRD HARMONIC

-

II

,

"

SINGLE ENDED INPUT I mV RMS)

Fig. 7 Overload characteristics

0

0

0

I

0

/

VS· 6'0'

/
0

/

THIRD ORDER

!40r--r~.+t~--4-+
w
"~30r--r~-K~--4-+4++~--+-~+H~-­

S
~

FfFTI1 ORDER

I
0

II
II

I·
FREQUENCY

SINGLE ENDED INPUT (mV RMS)

Fig. 9 Open loop frequency response

Fig. Blntermodulation distortions (1,55 and '-85kHz tones)

381

392

•

SL6000 SERIES

PLESSEY

SEMICONDUCTORS

COMMUNICATIONS CIRCUITS

SL 6290C
TRANSMIT CIRCUIT
The SL6290 is a bipolar integrated circuit combining the functions of audio amplifier, voice operated
gain adjusting device (YOGAD) and audio limiter; also
included are on RF buffer and. relay driver.
It is designed to accept signals from a low sensitivity microphone and to provide an essentially constant output signal for a 60dB range of input.
The out'put can be adjusted to provide varying
degrees of clipping of the audio signal. This, when
fi Itered to remove the edges, gives varying degrees of
audio c;ompression. The limiter has on open-collector
output so that a present resistor can be used to set the
maximum modulation required at the transmitter output.
The RF buffer is incorporated to provide isolation
betwwen the synthesiser and RF power amplifier used
in a typical complete transceiver.
The relay driver can be used as a receive/transmit
relay driver.

MICROPHONE

~16

1

INPUTS
INPUT GROUND

P
Pvec
~
P
P
P

1ST STAGE Olp

ole

RF BUF'FER lip

RF BUFFER alp

2ND STAGE lip

OUTPUT GROUND

UNLIMITED Olp

p

LIMITED alp

P

AGC LEVEL ADJUST

RELAY DRIVER olp
RELAY DRIVER lip
AGC TIMING

Fig. I Pin Connections (top view)

ABSOLUTE MAXIMUM RATINGS

-30' to C + 85' C
-30' to C + 70' C

Storage temperature
Operating temperature

FEATURES
APPLICATIONS

•

Fast Attaek

•
•
•

Speech Compression
Maximum Modu lotion Adjustment
Constant Output Signal

•

Relay Driver

•

RF Buffe,
INPUT
GROUND

•
•
•
•

Audio AGe Systems
Transmitter Overmodulation Prevention
Speech Recording
Level Setting Systems

OUTPUT
GROUND

rr r

INPU~OUTPUT
,

13

"

~

DECOUPL\NG

Mle
INPUT
RELAY DRIVER

~.~~-~,

INPUT~

Fig, 2 SL6290 block diagram

393

ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated);
Vee = +5V
Tomb = +25 C
Input frquency = 1 kHz
Value
Characteristic
Current into pin 15
Supply voltage pin 15
Output pin 6

Min

Typ.

Max.

4.5

15
5
150

5.5

25

Units
rnA
V

Conditions
5V on pin

mY rms

15

2.2 pin 8 to earth
20mV rms signal

Output pin 6

mY rms

AF amp voltage gain

54
1.0
20
1.0
300
180
50
1.0

Decoy time

Attack time

THD
Diff. input impedance
Single ended I/P impedance
AF amp DIP impedance
Limiter Q/P level
Limiter D.SdB compression point
Pin 6 DIP change with temp
Pin 7 DIP change with temp

dB

See note 1
See note 2
%

70

±O.6

Relay driver DIP current'
Relay driver I/P current

50

4,7k pin 7 to Vce
20mV rms signal riP

rnV
%/"(.

4, 7k pin 7 to Vcc
-30"C to +70(1 C
_30°C to +70 o C

·c

dB

500 ~6 alP load

dB

50 QI/P
500 Q DIP
50 QI/P

dB
rnA
rnA

_30 G C to +70"C
PinlOto5VVcc
No external resistor
on pin 10
Pin 11 sinking SOmA

Vsot relay DiP
Change of Vsot wi th temp
Voltage on pin 11

Vp-p

%1

Buffer gain @27MHz

Change of voltage gain from
nominal with temp

lmV liP

"

Q
Q

64
0.2
O. 12

Reverse gain (iiJ 27MH z

riP

Pin 8 connected to
earth. 20mY rms
signal liP

0.1

-30

° C.to..J.70·C

20

Note 1.

Decay time is the time for the VOGAD output to return to within 10% of its original absolute level when the
signal input voltoge is switched down by 20dB.

Note 2.

Attock time is the time for the VOGAD output to return to within 10% of ds original absolute level when the

OPERATI NG NOTES
The microphone input stage is different and the
accurate balance of this stage and the high commonmode rejection of the second stage gives an overall
common mode rejection ratio of greater than 30dB,
Typically, the amplifier will handle differential
and single-ended signals of up to 375mV peak to
peak. When used in the unbalanced mode either pin 4
or pin 5 may be used as the input, the other being decoupled to earth,
The LF cut-off of the amplifier is set by the
coupling capacitor between pin 16 and pin 5 and also
by the values ,Of coupling capacitors to the input pins
(pin 1 and pin 2). Coupling capacitors should be used

394

if the input is not floating with respect to earth.
The HF cut- off is set by the capacitor between
pin 5 and pin 6. In addition I the gain of the circuit may
be redl,lced by putting a resistor between these pins.
The HF cut -off capacitor should be adjusted in conjunction with any gain alteration in order to obtain the
des ired bandwi dth.
The resistor and capacitor on pin 9 set the attack
and decay rates of the VOGAD.
The values of external components shown in Fig.
3 give an attack time better than 20ms, a decay rate
of 20d6/s and a 3dB bandwidth of approximately
300Hz to 3kHz.

NOMINAL DC PIN VOLTAGES
(-l-SV ;(EGULATEDl

Pin
1
2

Voltage
IVDCI

Voltage
IVDCI

Pin

4

1.6V
1.6V
OV
1.5V

5

1.4V

11
12
13

6
7

1.4V

14

4V

4.5V

15

5V

8

OAV

16

2.5V

3

9
10

OV (no si gnal)
OV (no input)

5V
OV
1.7V

Table I. Nominal DC pin voltages

Fig. 3 SL6290 external connections

395

396

SL6000 SERIES
COMMUNICATIONS CIRCUITS

SL6310C
SWITCHABLE AUDIO AMPLIFIER
The SL631 OC is a low power audio amplifier which
can be switched off by applying a mute signal to the
appropriate pin. Despite the low quiescent current
consumption of 5mA (only O.6mA when muted) a
minimum output power of 400mW is available into an
80 load from a 9V supply.

FEATURES

eMB
•
•
•

Can be Muted with High or Low State
Inputs
Operational Amplifier Configuration
Works Over Wide Voltage Range

Fig 1 Pin connections, SL6310C -

eM

APPLICATIONS
•

Audio Amplifier for Portable Receivers

•
•

Power Op Amp
High Level Active Filter

"'''''''"'"'0''"
'''''"''

,

3

6

OUTPUT

lARTH

4

5

,'un

NC

8

,Mur "' _ _ _
v

J
I

DPB
"----F::c
ig-.C:2 'CCPiCn -co-nn-e-c,C-io,-rs, SL6310C _ DP

QUICK REFERENCE DATA
•
•
•

Supply Voltage: 4.5V to 13V
Voltage Gain: 70dB
Output into 80 on 9V Supply: 400mW

ABSOLUTE MAXIMUM RATINGS
Supply voltage: 15V

Storage temperature: --55"C to +150"C

nco

Y720k

,NPUTo---lH

Chip temperature: +175 C
Dissipation (CM): 0.45W (85 C)
(DP): O.50W (85 C)

Fig. 3 SL6310C test circuit

397

ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Supply voltage Vee: 4.5V to 13V

Ambient temperature: _30 o e to +85 c C
Mute facility: Pins 7 and 8 open circuit

Value

Characteristic

Min.

Typ.

Supply current

Supply current muted (A)
Supply current muted (B)
Input offset voltage
Input offset current
Input bias current (Note 1)
Voltage gain
Input voltage range

40
1.5
10
40
400

CMRR
Output power

THD

5.0
0.55
0.6
2
50
0.2
70
2.1
10.6
60
500
0.4

Conditions

Units

Max.

mA
mA
mA
mV
nA

7.5
0.7
0.9
20
500
1

Vee

9V
9V, Pin 7 via 1 OOk to earth
=- Vee

9V, Pin 8
Rs:(10k

~A

Vee =
Vee =
Vee

dB

V
V

0-=

9V
4.5V
13V

Rs:(10k
Vee = 9V, RL = 80
400mW, VeePOUT

dB

mW

3

=
=

%

~

9V, Gain

28dB

NOTE
1. The Input bias current flows out of pins 1 and 2 due to PNP Input stJgc

ID
-T-

22k

T"'"

(V'2VlAMP

INPUT~_,.5

22: -

3

,.

12V lAMP

'"'"'~"'"O
M'''"
,
R2

2_

"'
~-_VS75VMAX

Fig. 4 SL6310C lamp dover

OPERATING NOTES
Mute facility
The SL6310C has two mute control pins to allow
easy interfacing, to inputs of high or low levels. Mute
control 'A, pin 7, is left open circuit or connected to a
voltage within one volt of Vcc (via a 100kO resistor)
for normal operation. When the voltage on pin 7 is
reduced to within 1 volt of earth (via a 100kO resistor)
the SL631 DC is muted.
Mute control '8', pin 8, is left open circuit or connected to a voltage less than 1 volt for normal operation: a
voltage greater than 2.5V on pin 8 mutes the device.
The input resistance at pin 8 is around 10DkO and is
suitable for interfacing with CMOS.
Only one mute control pin may be used at any time;
the unused pin must be left open circuit.
Audio amplifier
As the SL6310C is an operational amplifier it is easy
to obtain the voltage gain and frequency response
required. To keep the input impedance high it is wise
to feed the signal to the non-inverting input as shown

398

Fig. 5 SL6310C servo amplifier

in Fig. 3. In this example the input impedance is
approximately 100kO. The voltage gain is determined
by the ratio (R3 +R4)/R3 and should be between 3 and
30 for best results. The capacitor in series with R3,
together with the input and output coupling capacitors,
determines the low frequency rolloff point. The upper
frequency limit is set by the device but can be restricted
by connecting a capacitor across R4.
The output and power supply decoupling capacitors
have to carry currents of several hundred milliamps and
should be rated accordingly.
Applications include hand-held radio equipment,
hi-fi headphone amplifiers and line drivers.
Operational amplifier
It is impossible to list all their application possibilities in a single data sheet but the SL6310C offers
considerable advantages over conventional devices in
high output current applications such as lamp drivers
(Fig. 4) and servo amplifiers (Fig. 5).
Buffer and output stages for signal generators are
another possibffity together with active filter sections
requiring a high output current.

FREOUENCY IHzl

Fig, 6 Gain v frequency

VOLTAGE Ivi

Fig. 8 Supply current v. supply voltage

Fig. 7 Gain v. supply voltage

VOLTAGE Ivl

Fig. 9 Output power v. supply voltage

at 5'/0 (max) distortion

399

400

o PLESSEY

SL6000 SERIES

SEMICONDUCTORS

COMMUNICATIONS CIRCUITS

SL6440C
HIGH LEVEL MIXER
The SL6440 is a high level mixer designed for use
in Radio Communications and in applications requiring
linear mixers. The linearity can be programmed using

the Ip pin.

FEATURES
•

30 dBm Intercept Point

•

Low Noise

•

+ 15 dBm Compression Point (1 dB)
-55'C to + 125'C Temperature Range

•
•

Performance Programmable

•

Gain Programmable

ABSOLUTE

O/p

O/P

Vcc2

liP

L.O.

liP

E'

Ip

MAXIMUM RATINGS
Pin connections

•

••
•
••

Supply voltage Pins 3, 4 and 14

15V

Pawer Dissipation (package limitation)

1200 mW

Derate above 25'C

8 mW I C

Operating Temp Range

-55 to

+ 125°C

-30 to

+ 85°C

ceramic

,T T 10uF

O.lu~

plastic
50

Storage Temp range

-65 to 150'C

Programme current

50 mA

alP

50

O.luF

VCC2~
--"--1"::--:14
10uF T TO. l
rl7'7uF

Figure I.

14
SL6440

11

~

O.luF

13

Typical Applications & Test (iret/lit

401

ELECTRICAL CHARACTERISITCS
Test conditions unless otherwise stated:

Local Oscillator input level =

a dBm
Value

Characteristic

Signal Frequency 3 dBm point
Oscillator Frequency 3 dB point

Units

Typ.

100
100
70

150
100

MHz

30

dBm

-60
-75

dB

2

dB

Signa Is

11

dE'.

-1

dB

500

dB

Test circuit Fig. 10

dSrn

See applications information

mA

IP'"

Intercept point

Third order intermodulation distortion
Second order intermodulation distortion
Noise Figure

Conversion Gain
Carrier Leak to

5

igna I input

Conditions

Min.

Max.

flAHz

-40

Level of carrier at r.f. output

-25

Supply current

7

=

Vccl
Vcc2
Vccl
V cc2

=
==
=:

12V
10V
6V
5V

Vccl = lOV
Vcc2
BV
Ip=25 mA

=

a dB",

liP

Ip =: 25 mA

Load Fig 1

a

Vcel ~20
Vcc2 = 10
Supply current
L cea I as c i Hotor input

1 dB

100

compression point

Single liP impedance

70
250

IP = 30 mA

rnA
500

mVrms

IP = 35 mA
Vccl
15V
Vcc2 = 12V

dBm

15

=

500

Single ended

1000
Local oscillator I/P impedance

CIRCUIT DESCRIPTION
The SL6440 is a high level mixer designed to
have a linear R.F. performance. The linearity can
be programmed using the IP pin 11. The programmed

Dilferencial
K s:l

1.5
Vee 1

where

Ip =: programmed current
RI =:De load resistance
Vs= max signal swing at output

current in the mixer, and flowing into the output pins

(3, 14), is twice the value programmed in on Pin 11.
The output pins are open collector outputs so the
conversion gain and output loads can be chosen for

the application.
The device has a supply pin for the local oscillator circuitry Vee 2 pin 4. Since the outputs are
open collectors they should be returned to a supply
Vee 1 through a load.
The choice of Vee 1 is important since it must

be ensured that the voltage on pins 3, 14 is not low
enough to saturate the output transistors and so limit
the signal swing unnecessarily. If the voltage on pins
3, 4 is always greater than Vee 2 under all conditions
the outputs wi II not saturate but the output frquency
response may reduce

402

if

the output is near saturation.

= (IP x Rlj" + Vs + Vcc2

Minimum

if the signal swing is not know:miniumum Vee 1 = 2 (IpxRI) +Vcc2
In this case the signal will be limiting at the input
before the output saturates.
The current (Ip) p"ogrammed into pin 11 can be supplied
via a resistor from Vccl or from a current sOtJrce.
The conversion gain is equal to:-

GdB =

20 Log

GdB

20 Log

for singleRL Ie
56.6 Tp +0.0785 ended output
2

RL Ip

56.6

for differential
output

Ip+0.0785

Device dissipation is calculated using the formula

-t

OIP

# 3.d
W diss

2

where

Va

voltage on pin 3 or pin 14

Vp

voltage on pin 11

Ip

Programming current

Ip Vp -Vplp -Vcc2 Diss

Vcc2 Diss

II 2nd

_10

DBM

-10

Dissipation obtained from graph
(Fig 8)

-20

As an example Figure 9 shows typical dissipations assuming Vee 1 and Vo are equal. This
may not be the case in practice and the device dissipation will have to be calculated for any particular
application.

/

V

30.01

I~h

1\ \

1\

-40

"\'\

-50

-60

\

-70

shown are the examples of what performance can be

expected.

20
NA

1 dB

COMPRESSION POINT

-10

+10

#

""

'- -""

V
/t

.-/

-80
10

DBM

I----

MH,

\ \

-30

Figure 3 shows the intermodu lotion performance
against Ip. The curves are independant of Vcc 1 and
Vcc 2 but if Vcc 1 becomes too low the output signal
swing cannot be accommodated, and if Vee 2 becomes
too low the circuit will not provide enough drive to
sink the programmed current. The supply voltages

-+-

L.O,='31. 4 MHz OdBm
R.F. I/P;30 MH,
,_/

"-

30

40

50

60

TOTAL OUTPUT CURRENT

v,,11=15:~

70

(2 Ip)

Figure 3'

Vee 2=-12 ....
Vee 1=12 ....
Vcc2=lO ....

LOCAL OSCILLATOR LEAK

~ 1-~

10

20

30

40

Figure 2.

50

r60

70

TOTAL OUTPUT
CURRENT (2Ip)

APPLICATION NOTES
The SL6440 can be used with differential or single-ended inputs and outputs. A ba lanced input will
give better carrier leak. Figures 4, 5 and 6, show
the performance with variour in pt configurations.
The high input impedance allows step-up transformers
to be used if deSired, whilst high output impedance
allows a choice of output impedance and conversion
gain.
Figure 1 shows the simplest application circuit.
The input and output are single ended ani Ip is supplied from Vcc 1 via a resistor. Increasing RL will
increase the conversion gain, care being taken to
choose a suitable value for Vcc 1.
Figure 10 shows an application with balanced
input, for improved carrier leak, and balanced output

I

LO 3~,4M,Hz,
Veel

-30

0IBm,

15v

I

,

-20

1\II

-10

1\

I

1\

I
1'-.

1v

2

3

4

5

7
vee 2

i

8

1
1

91011121314

for increased conversion gain. A.lower Vee 1 giving

lower device dissipation can be used with this ar-

Figure 4'

rangeme nt.

403

LOCAL OSCILLATOR LEAK

-60

31. 4 MHz

L.O.

OdBi

Veel =15v
-50

-so

I

r--.
I

-30

-30

I

V

<

\

.-20

I I

\

-40

1\

'"

-20

\

II

-10

I

-10

:.-5

-0

Iv

2

3

4

5

6

7

8

9

Iv

10 II 12 13 14

3

2

4

5

6

VCC 2

Figure 6

SUPPLY CURRENT AGAINST VCC2 WITH Ip=O

FRQUENCY RESPONSE WITH CONSTANT OUTPUT I.F.

o

(mA )

I I

......

lOMHz

-I

r-n

WANTED

-2
-3

-4

-6

-7

-8
-9

-10
-II
-12

......

11

""

I I

-5

\

.. - rCT 2'1

-t-+NPUT LEVEL"ODBM

vee 1=6;1

vee

2=5v
IP=24mA

9 10 11121314

8

7

VCC 2

Figure 5.

DB

i
i

i

-40

vce

~

1= 12v
1p

I I
I I

L -t

10

!\

;/

\

V

~

t-

,,*\

I

/'

\ \"

I"'

V

V

V

1/

LOCAL OSCILLATOR INPUT LEVEL=ODBM \

I

I I
I I
Fig(.He7.

404

4

5

6

7

8

9

10 II

I I I I

12 13 14 15
VCC 2 (VOLTS)

Figure 8.

vee

1

I/P
Figure 9

RF

liP

rm
Figure

fa

405

406

•

PLESSEY

SL6000 SERIES

SEMICONDUCTORS
1641 Kaiser Avenue
Irvine. CA. 92714

COMMUNICATIONS CIRCUITS

SL6600C
LOW POWER IF/AF Pll CIRCUIT FOR NARROW BAND FM
The SL6600 is a single or double conversion IF
amplifier and detector for FM radio applications. Its
minimal power consumption makes it ideal for hand
held and remote applications where battery conservation is important. Unlike many FM integrated circuits
the SL6600 uses an advanced phase locked loop
detector capable of giving superior signal-ta-noise ratio
with excellent co-channel interference rejection, and
operates with a second I F frequency of less than 1 MHz.
Normally the SL6600 will be fed with a first IF signal
of 10.7 or 21.4M Hz; there is a crystal oscillator and
mixer for conversion to the second IF amplifier, a PLL
detector and squelch system.

CRYSTAL

16

"I
-

TOP VIEW

•

8

.,
"0""
:~
!

""

12

,

11

m

9

Ge18

Fig. 1 Pin connections

QUICK REFERENCE DATA
•
•

Low Power NBFM Receivers

d '"

10 11

CONNECTIONS AS DG/OP 18 PACKAGE

APPLICATIONS
•

9

OG18
OP18

BOTTOM VIEW

10':":1

High Sensitivity: 5~V minimum
Low Power: 1.5mA typical at 7V
Advanced PLL Detector
Available in Miniature 'Chip Carrier'
Package
50dB SIN Ratio

lOOP
FILTER

'-L.._ _.....;.,O~VCOTIMINGRESISTOR

FEATURES
•
•
•
•

DECOUPLE

Supply Voltage 7V ± O.5V
Input Dynamic Range 100dB min.
NOTE; RESlsnVE

IMPEDANCE

AT PIN 4" 25k.n(TYP), 36kn.(MAX)

".'OG

;;;,'00"

C

,---------~-----I

I
I
I
I
I

,st
I~

IFAMP
50MHz

.20dB

AUOIO
OUTPUT

'I
I
I
I
L - - -EART!17 - "liER"

DECOUPLE

1 SaUElCH - - - - - - _..J
....OJUST

3 - - 4 FILTER 5 IF---:--16YDEcciiPt.e DECOUPLE.l

rm,oon ;;n33P

nrn'K'ICn

nrn loon

l}l
;;;

lOOk

"Cc

Fig. 2 SL6600 block diagram

407

ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Supply voltage Vcc : 7V ±0.5V
Input signal frequency: 10.7M Hz, frequency modulated with a 1 kHz tone with ± 1.5kHz frequency deviation.
Ambient temperature: -30'e to +S5'e
Value
Characteristic
Supply current
First IF input impedance
I nput dynamic range
Maximum input level
Input sensitivity
Audio output
Audio THD
S + N/N
AM rejection
Squelch low level
Squelch high level
Squelch hysteresis

Min,

100
2
5
20
30
30
0
Vcc-O.5

Typ.
1.5
910
120

Units

Max.
2.5

mA
0
dB
Vrms
~V rms

3
50
1.3
50
40
0.2
Vcc-O.1
2

SO
3

mVrms
%
dB
dB
V
V
dB

0.5
Vcc

Conditions

1dB change in AF output
500 source,
S + N/N ~ 20dB
1 mV rms input level
1 mV rms input level
1 mV rms input level
30% AM, 100~V rms Input
20~V rms input
No inpu.t

APPLICATION NOTES
IF Amplifiers and Mixer
The SL6600 can be operated either as a single conversion circuit with a maximum recommended input
frequency of 800kHz or in a double conversion mode
with a first IF of the input frequency (50 MHz max.)
and a second I F of 100kHz or ten times the peak
deviation, whichever is the larger. The crystal oscillator
frequency can be equal to either the sum or difference of
the two IFs; the exact frequency is not critical.
The circuit is designed to use series resonant
fundamental crystals between 1 and 25M Hz.
When a suitable crystal frequency is not available a
fundamental crystal of one third of that frequency may
be used.
When a single conversion circuit is required a 6.8k
resistor should be connected in place of the crystal and
a further 2.7k resistor connected between pin 1 and
earth. The overall gain of the circuit will be reduced by
12dB with this technique.
A capacitor connected between pin 4 and ground will
shunt the mixer output and limit the frequency response
of the input signal to the second I F amplifier. A value
of 33pF is advised when the second I F frequency is
100kHz.

Squelch Facility
When inputs to the product detector differ in phase
a series of current pulses will flow out of pin 7. This
feature can be used to adjust the veo; when a 1 mV
unmodulated input signal is applied to pin 18 the
veo frequency should be trimmed to maximise the
voltage on pin 7.
The squelch level is adjusted by means of a preset
variable resistor between pin 7 and Vcc to set the output
signal to noise ratio at which it is required to mute the
output. The capacitor between pin 7 and ground
determines the squelch attack time. A value between
10nF and lO~F can be chosen to give the required
characteristics.

Outputs
High speed data outputs can be taken direct from
pins 11 and 12 but normally for audio applications pin
8 is used. A filter network will be needed to restrict the
audio bandwidth and an Re network consisting of
4.7 k 0 and 4.7nF may be used.

Phase Locked Loop.
The Phase Locked Loop detector features a voltage
controlled oscillator with nominal frequency set by an
external capacitor according to the formula (1f)pF,
where f is the veo frequency in MHz. The nominal
frequency may differ from the theoretical but there is
provision for a fine + 10% frequency adjustment by
means of a variable resistor between the VCO output
pins; a value of 470k has negligible effect while 47k
(recommended minimum value) increases the frequency
by approx. 10%.
The loop filter is connected between pins 11 and 12;
a 33k resistor is also required between pin 11 and Vcc.
The values of the filter resistor R2 and capacitor C,
must be calculated so that the natural loop frequency
fn and damping factor i; are suitable for the FM deviation
and modulation bandwidth required. Values of 6.2k 0
and 2.2nF are recommended for '5kHz maximum
deviation and 3kHz audio bandwidth when the
second I F frequency is 100kHz. These give fn ~
201:4z, f; ~ 0.707.

408

IF INPUT

10n

R:~~~ER o---J
FREQUEI+CIES

455k~~'~::~~

lOilMHz

0'

100k

S~~;~~H
ADJUST

'----c=f--1~~ au~~UT
L...+--~~=~+--~ ~~~~tc:

Fig. 3 SL6600applicalion diagram (1 stlF= 10. 7MHz, 2ndlF= 100kHz

--------,
INTERNAL
CIRCUITRY

\

Vee

\,f,

JSk :11

A,,',

*"

t--t-~"-------'

:

:a. "
"'

"

K, = 2.4f, radians/volt-second
Ko = 2.8 volts/radian
2nd IF frequency
-~ natural loop frequency

fo
f,

-0

From theory:

"

I

-------~

Damping factor~· ~

, ( Ko Ko )
"2

T \ +T2

~

(T

1)

2 + Ko

Ko

Fig. 4 Loop filter

TYPICAL CHARACTERISTICS

a
I

~

,

D,~-~-~7--L--"--_~_~"L._~_~

INPUT VOLTAGE (jJlI)

INPUT VOLTAGE (/Jvl

Fig. 5 Typical SINAD (Signal In/Noise & Distortion) Chacteristics

Fig. 6 Typical audio total harmonic distortion v. input signal voltage

t--"----l.85"

J

-1+-

Ir
SUPPLY IIOLTAGE (\II

Fig. 7 Supply voltage v. temperature

veo

FREQUENCY DRIFT ('Yo)

Fig. 8 Stability of VCO

409

ABSOLUTE MAXIMUM RATINGS
Supply voltage: 9V
Storage temperature: -55°C to +150°C
Operating temperature: -55°C to +85°C

410

.PLESSEY

Sl6000 SERIES

SEMICONDUCTORS

COMMUNICATIONS CIRCUITS

SL6700C
IF AMPLIFIER AND AM DETECTOR
The SL6700C is a single or double conversion IF
amp] Hier and detector for AM radio applications. Its
low power consumption makes it ideal for hand held
applicatians. Narmally the SL6700 will be fed with a
first IF signal of 10.7 or 21.4 MHz; there is a mixer
for conversion to the first or second IF I a detector, an
AGe generator with optional delayed output and a
noise blanker monostable.

AGe

OECQUPLlNG

AGe

I F'

INTERSTAGE
{

IN P UT

GROUND

BIAS

AGe DECQUPLING

COUPLING
AUDIO

TERMINALS

DELAYED OUTPUT

ou TPUT

DECOU PLING POINT

IF OUTPUT

Nt B OUTPUT

LOCAL

osc

lip

.t"

~_ _ _

FEATURES
Fig.

•

High Sensetivity:

•

Law Pawer:

•

Linear Detector

Pin Connections

QUICK REFERENCE DATA

SmA typied at 6v

APPLICATIONS
•

J

10 IJV minimum

•

Supply Valtage

•

Input Dynamic Range 100dB typ

4.5v

ABSOLUTE MAXIMUM RATINGS

Low Power AM Receivers

•

Supply Voltage:

•

Starage temperature:-

7.5v
-55 C to + 125 C

NOISE
A UOIO
BLANKER
NOISE
AGe
OUTPUT
POINT
DETECTOR
TIMING
BLANKER
DECOUPLING
DECOUPLING INPUT CAPACITOR OUTPUT

IF
INPU T

SU PP L Y

AGC

AGe
DECOUPLING

AGe
BIAS

~

INTERSTAGE
COUPLING
TERMINALS

IF

AGe
OUTPUT

OUTPUT

MIXER
I/~

MIXER
01 p

LOCAL

esc

Fig. 2 SL6700 block diagram

411

ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):

Supply voltage 4.5V
Tomb _30' C to +85' C
Value
Characteristic

Units

Min

Supply voltage

Max

4.5
40
1

6

7

3

Supply current

SIN ratio
TH distortion
Sens itivity

Typ

10

Audio O/P level change
AGC threshold

V
mA
dB
%

5

~V

6

dB

Cond it ions

Optimum

performance

1mV liP 80% mod .~ 1kHz
lmV liP 80% mod 1kHz
10dB S + NIN ratio, 30% mod 1kHz
1 OpV to 50mV liP 80% mod 1kHz

5

~V

dB

AF O/P level
Delayed AGC threshold

80
60
10

mY rms

80% mod

Dyne mic range

100

dB

Noise floor to overload

I F frequency response

50
50
46
4

MHz

3dB gain reduction

dB
dB
Ul
krl

10.7MHz
455kHz 80% AM 1kHz

v

Logic 1
Logic 0

AGe range

IF amplifier gain

Detector go i n
Detector Z IN Pin 13

IF amplifier ZIN Pin 18
Noi se blank level

3

Noise blank duration

300

1.2R
3
5
50

Mixer Z IN (Signal)
(I_.C.)

~lixerZIN

Mixer L.O. injection

20

Detector output voltage
change

6

OPERATING NOTES
The noise blank duration can be varied from the
suggested value of 300ps using the formula: Duration
time = O.7eR, where R is value of resistor between
pins 11 and 12 and C is value of capacitor from pin 12
to ground.
There is no squelch in the SL6700C and the delay
in the delayed AGe is too large to make this output
suitable. Squelch is best obtained from a comparator
on the AGe decoupling point, pin 16.
The IF amplifiers may be operated at 455kHz
giving a single conversion system. To keep the some
sensitivity the mixer must be used as a linear amplifier by connecting a 20kn resistor between pin 9 and
earth.

412

mV

2.7

Mixer conversion gain

at 4.5V

0.6

V

70

ps
krl
krl
krl
mV rms
dB

C Pin 12

30nF

R is load resistor in kO

Ic = 10.245 MHz
lmV rms input, 1kHz modulation increased
from 30% to 80%

TYPICAL DC PIN VOLTAGES
(Supply 4.5V, Input 1 mY)
Pin

1
2
3
4
5
6

7
8
9

Voltage

Pin

Voltage

0.25V
O.09V
3.68V

10

4.5V
3.7V
OV

0.7V
0.6V
3.7V
l.5V
4.3V
1.5V

11
12
13

14
15

0.77V
l.5V
1. OV

16
17
18

0.7V
OV
O.7V

Voo

IFINPUT~n
10.7MHz

1n

L.O.

~10.245MHz

DELAYED
AGe

Fig. 3 SL67QO C AM double conversion receiver noise blanker

+50

2.00

VOL TS

eo

"'"w

I-

~

1.5

PIN 5 1KQ LOAD

Z

u
~ 1.0

0

r- +30
w

n

w

0
z

>-

~
n

+40

0

is

+
..J

0.5

dB

+20

"
Z

'"v;

+ 20

+40
dBjJV

Fig. 4

I

I

+60

+,0

I

+ 100

R.M.S.

Typied OAGC output variation with input
signal (f:::::. /O.7MHz, 30% modulation

~

+ 10

r-

::J

0

+20

+ 40
dBpV

+60

+80

+ 100

R.M.S.

Fig 5 Typied Signal to Noise raUo (~)
N
with input signal (f=IO.7MHz, 30% modulation)

413

414

SP9000 SERIES
DATA CONVERSION PRODUCTS

SP 9685

SP 9687

ULTRA FAST COMPARATOR

ULTRA FAST DUAL COMPARATOR

The SP 9685 is an ultra-fast comparator, and the SP 9687 is an
ultra-fast dual comparator, both manufactured with a high
performance bipolar process which makes possible very short

GROUND 1

propagation delays 2.2 nS typ .! 2.7 nS typo respectively. The
circuits have differential inputs and complementary outputs fully
compatible with Eel logic levels. The output currents capability
are adequate for driving 50 ohm terminated transmission lines.
The high resolution available makes the devices ideally suited to
analogue-ta-digital signal processing applications.

With the SP 9685 a latch function is provided to allow the

CM10

comparator to be used in a sample-hold mode. When the latch
enable input is Eel high, the comparator functions normally.
When the latch enable is driven low, the outputs are forced to an
unambiguous Eel logic state dependent on the input conditions
at the time of the latch input transition. If the latch function is not
used the latch enable may be connected to ground.
With the SP 9687 a latch function is provided to allow the
comparator to operate in the follow-hold or sample-hold mode.
The latch function inputs are intended to be driven from the
complementary outputs of a standard Eel gate. If [E is high, and
IT is low, the comparator function is in operation. When LE is
driven low and IT high, the outputs are locked into the logical
states at the time of arrival of the latch Signal. If the latch function
is not used, IE Must be connected to ground.
Both devices are compatible with the AM 6851 AM 687
respectively but operate from conventional + 5V and- 5.2V rails.

16

GAOUN02

OC16
OG16

FEATURES
•

Propagation Delay 2.2 ns typ/2.7 ns typ
respectively.
latch Set·up Time 1 ns max./0.5 ns typ
Complementary ECl Outputs
50 Q line Driving Capability
Excellent Common Mode Rejection
Pin Compatible with AM 685/687 but faster

•
•
•
•
•

On metal package, pin 5 is connected to case. On DIP
pin 8 is connected to case

Fig. 1 Pin connections
PIN DIAGRAM
QQUTPUT 1 -.~r-

16 Q OUTPUT

OOUTPUT 2

15 QOUTPUT

GND 3
LE 4

QUICK REFERENCE DATA

••

U5
-VE 6

Supply voltages +5V, -5.2V
Operating tempurature range
-30°C to +85 0 C

14 GND

IA IA

i"-

13 LE

n

1'ili

'--

9

11 +VE
10 -INPUT

-INPUT 7
+INPUT 8 )--

+INPUT

Fig.IA

ABSOLUTE MAXIMUM RATINGS
Positive supply voltage
Negative supply voltage
Output current
Input voltage
Differential input voltage
Power dissipation

Storage
Lead temperature (soldering 60 sec)

6V
-6V
30mA
±5V
±5V
500mW
_55° to 150°C
300°

.......r----..-~

ij OUTPUT

'iNVERTING
INPUT

LATCIi

ENABLE

ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated) :
TAMS ~25°C

VCcc +5.0VL.25V
VEE
-5.2V ± .25V
RL ~·50Q

The outputs are open emitters, therefore external pulldown
resistors are required. These resistors may be in the range
of 50-2000 connected to -2.0Vor 200-20000 connected
to -5.2V

SP 9685 is a dual without latch enable.
Fig. 2 Functional diagram

415

Value

Characteristic
Input offset voltage
Input bias current
Input offset current
Supply Currents Icc
lEE

-5

Both
Both
Both
SP 9685

19
23
30
54
210
430
0.5
0.5
2.2
2.7
2.2
2.7
2.5
2.7
2.5
2.7
2

"SP 9687
Total Power Dissipation

Min. Latch Set·up Time
Input to

a Output Delay

Input to Q Output Delay
Latch to Q delay
Latch to Q delay
Min. latch pulse width
Min. hold time
Common Mode Range
I nput Capacitance
I nput Resistance

Output Logic Levels
Output High
Output Low
Common Mode Rejection
Ratio
Supply Voltage Rejection
Ratio

+5
20
5
23
34

10

SP 9685
SP 9687
SP 9685
SP 9687
SP 9685
SP 9687
SP 9685
SP 9687
SP 9685
SP 9687
SP 9685
SP 9687
Both
Both
Both
Both
Both

300
1
3
4
3
4
3
4
3
4

3
1
+2.5

-2.5
3
60

Both
Both·
Both

-.96
-1.85
80

Both

60

Conditions

Units

Max.

TVp.

Min.

TVpe

-.81
-1.65

100 ohms

mV
uA
uA
mA
mA
mA
mA
mW
mW
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
pF
t< ohms

Rs

V
V
dB

At Nominal Supply
Voltages.
See Fig. 4

Nominal Conditions

100 mV pulse
10 mV Overdrive

dB

LATCH
ENABLE

DIFFERENTIAL
INPUT
----...--VClLTAGE
'p~

'"

·a

e

------:-t---__
1\

V'
__-_-___-_-_-_- t - - - '\
!\
Fig. 3_ Tlmmg dIagram

OPERATING NOTES
Timing diagram
The timing diagram, Figure 3, shows in graphic form
a sequence oj,events in the SP9685. It shou:d not be
interpreted as 'typical' in that several parameters are
multi-valued and the worst case conditions are
illustrated. The top line shows two latch enable pulses,
high for 'compare', and low for latch.· The first pulse
is used to highlight the 'compare' function, where part
of the input action takes place in the compare mode.
The leading edge of the input signal, here illustrated as
a large /lmplitude, small overdrive pulse, .switches

416

the comparator over after a time tpd. Output Q and Q
transitions are essentially similar in timing. The input
signal must· occur at a time t. before the latch falling
·edge, and must be maintained for a time th after ·the
latch falling edge, in order to be acquired. After th, the
output ignores the input status untiL·the latch is again
strobed. A minimum latch pulse with towlE) is required
for the strobe operation, and the output transitions
occur after a time todIE).

Definition of terms
Vos

los

Input offset voltage - The potential difference
required between the input terminals to obtain
zeto output ootential difference.
Input offset current - The difference between

the currents into the inputs when there is
zero potential difference between the outputs.

solder the device directly into the circuit board.. The output lines
should be designed as microstrip transmission lines backed by
the ground plane with a characteristic impedance between 500
and 150
Terminations to -2V, or Thevenin equivalents,
should be used.

n.

18

RIN
CIN

Input bias currents - The average of the two input
currents. IS is a chip design trade-off parameter;
externally, it is desirable to have I B as low as possible,
while internally, circuit peliormance requirements
demand higher IS.
Input resistance
The resistance looking into either
input with the other grounded.
Input capacitance - The capacitance looking into either
input pin with the ot~er grounded.

Switching terms (refer to Fig. 3)
tpd+
Input to output high delay - The propagation
delay measured from the time the input signal
crosses the input offset voltage to the 50%
point of an output LOW to HIGH transition.
tpdInput to output low del3Y - The propagation
delay measured from the time the input signal
crosses the input offset voltage to the 50%
point of an output HIGH to LOW transition.
tpd HE)
Latch enable to output high delay - The
propagation delay measured from the 50%
point of the latch enable signal LOW to HIGH
transition to the 50% point of an output LOW
to HIGH transition.
tpd.-(E) Latch enable to output low delay - The
propagation delay measured from the 50%
point of the latch enable signal LOW to HIGH
transistion to the 50% point of an output
H IG H to LOW transition.
t5
Minimum set-up time ~ The minimum time
before the negative transition of the latch
enable signal that an input signal change must
be present in order to be acquired and held at
the outputs.
th
The minimum time after the negative transition
of the latch enable signal that the Input signal
must remain unchanged in order to be acquired
and held at the outputs.
tpw(E)
Minimum latch enable pulse width - The
minimum time that the latch enable signal
must be HIGH in order to acquire and hold an
input signal change.
VCM
Input voltage range - The range of input
voltages for which the offset and propagation
delay specifications are valid.
CMRR Common mode rejection ratio - The ratio of
the input voltage range to the peak-to-peak
change in input offset voltage over this range.
Latched and unlatched gain
The gain of a high speed. high gain comparator is
difficult to measure, because of input noise and the
possibility of oscillations when in the linear region.
For a full ECL output level swing, the unlatched input
shift required is approximately 1 mV. In the latched
mode, the feedback action in effect enhances the
gain and the limitation in the noise/oscillation level;
under these conditions the usable resolution is 1 OO~V,
although this is only achieved by careful circuit'design
and layout.
Interconnection techniques
High speed components in general need special precautions in
circuit board design to achieve optimum system performance.
The SP 9685/SP9687, with around 50 dB gain at 200M Hz, should
be provided with a ground plane having a low inductance ground
return. All lead lengths should be as short as possible, and RF
decoupling capacitors should be mounted close to the supply
pins. In most applications, it will be found to be necessary to

Measurement of propagation and latch delays
A simple test circuit is shown in Figure 4. The
operating sequence IS:
1. Power up and apply input and latch signals.
Input
100mV square wave, latch EeL levels.
Connect monitoring scope(s).
2. Select 'offset null'.
3 Adjust offset null potentiometer for an output
which switches evenlv between states on clock
pulses
4. Measure input/output and latch/output delays at
5mV offset, 1 OmV offset and 25mV offset.

Note: The SP 9687 has no Latch
input

Fig. 4 SP968519687 test c"cuit

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Fig. 5 Open loop gam as a function of frequency

417

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TEMPERATURE (OCI

Fig. 9 Set-up time as a function of temperature
2S

OVERDRIVE (mVI

Fig. 8 Propagation delay. input to output as B function overdrive

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TEMPERATURE (OCI

Fig. 11 Propagation delay. input to output as a
Fig. 10 Set-up time as a function of input overdrive

418

funCtion of temperature

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Fig. 13 Output nse and fall limes as a function of temperature
TEMPERATURE (DC)

Fig. 72 Propagation delay. latch to output as a functIOn of
temperature

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Fig 14 Input bias currents as a function of temperature

Fig 15 SupplV current as a function of temperature

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Fig. 16 Output levels as a function of temperature

2ns PER/DIV

Fig. 17 Response to various input signal levels

419

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420

SP9000 SERIES
DATA CONVERSION PRODUCTS

SP9750
HIGH SPEED COMPARATOR
The SP9750 is a high speed comparator with a latch
circuit and other facilities intended for use in the construction of fast A-D converter systems. The speed
capability of the device is compatible with conversion
rates of up to 100 Mega-samples per second. Input and
output logic levels are ECl compatible.

II,

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FEATURES

i,

OVANAlOGU£ [

•
•
•
•
•
•
•

latch Set up Time
2ns Max.
Max. Input Offset Voltage
5mV
Propagation Delay
3ns (Typ)
ECl Compatible
Comparator Output Gating
Wired OR Decoding for 4 Bits
Current Output Settling to 0.2% in 8ns

OVLOGIC

1'[~RSlT

DG16

Fig. 1 Pin connections

ABSOLUTE MAXIMUM RATINGS
Positive supply voltage
Negative supply voltage
Reference supply voltage
Reference current output
Input voltage
Differential input voltage
Power dissipation
Operating temperature range
Storage temperature range
lead temperature (soldering 30

+5.5V
-5.5V
-8.5V
15 mA
±4V
-le 6V
500 mW
-30°C to +85 'c
-65°C to + 150'C
sec)
300'C
logic input voltages to gate and latch VEE to 0
Fig. 2 Block diagram of SP9750

LATCH

LATCH

INPUT
COMPARE

SIGNAL
INPUT

INPUT VIN
______
1. __ _

------T----,

DEFINITION OF TERMS

- - -- - - - - - Vas

t.

Mimmum set up lime - the minimum time
before the latch positive edge that the input
must be in a given slate for acquisition to take
place

th

Minimum hold time -the minimum time after
the latch positive edge that the input must
remain in one state for acquisition to take
place

tl

Minimum latch enable pulse width - the
minimum time tor which the latch must
remain low tor acquisition to take place

OVERDRIVE VOD

00 OUTPUT
-

IO OUTPUT - - - - - - - - j - - - - ,

50"/"

tpd (ll

Fig. 3 Timing diagram SP9750

421

ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
TAMB ~ +25 D C
Vee ~ +5V ±0.25V
VEE ~ -5.2V ±0.25V
VREF ~ -8V -Value

~haracteristic

Min.

Typ.

-5

Input offset voltage
Input bias current
Input offset current
Supply currents Vee
VEE
VREF
Total power dissipation
Analogue O/P current 'on
Analogue O/P current 'off'

16
35
14
390
5

Units
+5
25
5
20
42
18
470

Min. latch set-up time (t,)
Input to OD O/P delay (tpd (00

»

Input to 10 delay (tpd (10»
Delay gate input to 0,-4 high
Delay gate input to 0,-4 low
Latch to 10 (tpd (Llo»
between 50% points
to 1 % settling
to 0.2% settling
Min. hold time th
Min. latch pulse width (tl)
Common mode range
Diff. mode range
Node capacitance 10
Node capacitance analogue input
Input resistance
Output logic levels
Logic '1'
Logic '0'

mV
~A

~A

mA
mA
mA
mW
mA

3

2
4.5

ppm;oC
ns
ns

3
1.5
1.5

4.5
2.5
2.5

ns
ns
ns

3
4
8
1
2

4.5
8
12

ns
ns
ns
ns
ns
V
V
pf
pf
KO

-2.5V

+2.5V
5
3.5
3

60
-.98
-1.85

See operating note 1
+5Von pin 8
Also depends on REXT
See operating note 2
VIN = 100 mV, 25 mV
over drive, 500 load
on 10 to 0 volts (Note 3)

~A

5

020

Precision current stability

Conditions

Max.

-0.78
-1.6

!l

See operating note 4

} See operating note 5

Vcc = +5V, VEE ~ -5.2V
Rl ~c 2200 to -2V

V
V

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2

4 ALL

ll° lZ

+

SAME lENGTH

50 .... TRACK

L)

ALL OUTPUTS OF 00'4 {PINS 4,5,6,11,121

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-5-21'

lAT(1i

Fig. 4 Test circuit

422

GENERAL DESCRIPTION
The SP9750 is a fast comparator combined with a
latch facility which allows the device to be operated in
the sample and hold mode.
When the latch is 'low' the comparator is in the
'follow' mode, and when the latch is driven 'high' the
output is locked in the existing state. The latch cirC!Jitry
will therefore always produce a decision on the input
state.
The comparator has a relatively low gain in the follow
mode, which assists in achieving an extremely fast
response. However, due to the positive feedback action
of the latch function, the gain approaches infinity
during the latch cycle, thereby ensuring high resolution.
In addition to the basic comparator, the following
functions are provided on the chip to optimise the
performance of high speed parallel-series-parallel A to
D converter systems.
1. An ECl compatible gating function for simplified
mUlti-comparator output logic.
2. Four emitter follower outputs from the gate to
provide wired OR decoding for four bits.
3. A precision current source, set by an external
resistor.

4. A high speed switch for the precision current
to provide a fast and convenient reconstruction of the
analogue input. Summing the currents in a multi-level
comparator chain provides the D to A conversion

directly for the construction of converters of the parallelseries-parallel type.
The philosophy adopted in the SP9750 makes
possible the construction of ultra-fast, high accuracy
parallel-series-parallel converters by integrating a
significant portion of the system function on the same
chip as the comparator. The result is not only to reduce
considerably the total hardware count but to reduce the
propagation delays where they are most critical, and
eliminate redundant operations.

OPERATING NOTES
1. The analogue output current (10) is set by means
of an external setting resistor (REXT) and is equal to the
reference voltage on Pin 9 ( ---8V nominal), divided by
2 x REXT. The accuracy of this reference voltage must
be consistent with the conversion accuracy required.
The output (Pin 8) compliance is -0.8V to +5.0 Vults
for correct operation.

2. This parameter is defined with + 100 mV input
and -~ 10 mV overdrive, corrected to take account of the
comparator offset, i.e. the switching threshold effectively is at OV on the input waveform. The relationship
between setup time and overdrive is shown in Fig. 7c.

devices onto the 0, - 04 rails.
5. Output settling times are measured at 10 mV
overdrive conditions; larger overdrives produce shorter
delays.
6. The test arrangement shown in Fig. 4 provides for
a simple dynamic test of the SP9750 functions. When
the switch is in position 1, the input offset voltage is
nulled with the potentiometer, a condition detected by
observing the output to be at the mid-point of its range
(10 or 0 0). The latch must be 'Iow' for this measurement. The offset voltage can be measured with a high
impedance instrument. Positions 2, 3 and 4 provide
increasing amounts of bias to the reference input

corresponding to overdrives of 5mV, 10 mV, and
25 mV. For convenience of operation, the input
analogue signal is referred to ground, and the reference
input is set above ground, so that an input waveform
which is positive going and referred to ground is all that
is necessary. It should have an amplitude of (100 mV +
overdrive voltage) and should have less than 5%
overshoot. The risetime should be about 2 nS. Simple
circuit modifications and a negative going signal would
provide for inputs of opposite polarity. For accurate
timing, the path length l1 should be equal to l2 +l3
properiy terminated.
Static (DC) measurements can also be performed on
the same test arrangement.

APPLICATIONS
Although the SP9750 was aimed at a particular
system configuration it is sufficiently flexible to find
application in a variety of conversion methods. In an
ail-parallel A-D converter, the SP9750 is capable of
achieving sampling rates of up to 100 Megasamples per
second. This technique is usable up to 5-bit accuracy.
For higher bit accuracies, techniques such as the parallelseries method are required. Fig. 5 shows the schematic
diagram of an A-D converter system capable of giving
8-bit accuracy at sampling rates of up to 30 Megasamples per second. The SP9750 is used In two 4-bit
stages operating in the parallel-series-parallel mode.
The analogue current output settling time from the first
stage (an effective DAC facility) is dominated by the
settling time of the one comparator which has
the smallest overdrive. All other comparators have

longer to settle, since the preceding sample and hold
must be allowed to settle. For an 8-bit system, each
comparator in the first 4-bit conversion has a weighting
of 1/15 of full scale input. Therefore the settling band
of interest for -~ ;- l.S.B. is 2.9%. Typically the SP9750
settles to less than this, 1 %, in four nanoseconds
illustrating the possibility of converter construction at

The test circuit diagrnm, Fig. 4 indicates a method of

higher speeds, or higher accuracies

performing this test.
3. Due to the relatively low gain of the comparator in
the unlatched state, propagation measurements are
defined with a 25 mV overdrive. The relationship
between overdrive and delay is shown in Figs. 7a and
7b.
4. The gate input accepts an ECl drive. The outputs
0, to 04 are active when the gate input is at an ECl
'low' level, ( -1.75V) and are switched by the internal
circuitry. A 'high' gate input ( - 0.9 V) switches the
outputs to 'low', allowing the bussing of multiple

In order to achieve the optimum performance of this
device, care must be taken to ensure that good layout
practice is used, consistent with high frequency practice.
A ground plane construction should be used and all
leads should be designed to be microstrip transmission
lines. The device should be soldered directly into the
circuit board and the supplies decoupled with RF
capacitors as close to each device as possible. In
addition, to achieve the shortest possible settling time
for the analogue current output, it is essential to keep
the stray capacitance on Pin 9 (RsET) to a minimum.

423

DIFFERENCE
AMPLIFIER

ANALOGUE
INPUT

Fig. 5 Block diagram of a 4 x 4 bit parallel-series AID converter

ANALOGUE
INPUT

EACH BLOCK

REPRESENTS SP9750

Z
TO LOWER
LATCH INPUT
LEVELS
tALL COMPARATORS)

,

2

2

.

2

~
4 BIT WIRED 'Off
DECODING

Fig. 6 Block diagram of 4-bit LSS stage showing top six levels

424

ANALOGUE
CURRENT
OUTPUT

Fig. 7 Performance curves. Unless otherwise specified, standard conditions for a/l curves are TAMB = 25°C, Vee = 5.0V, VEE =-5.2V,
VREF~-8.0V.

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Fig. 7b Input to 00 output delay v. overdrive

Fig. 7a input to 10 output delay v. overdrive

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TEMPERATURE I'C)

Fig. 7h Minimum set-up time as a function of temperature

425

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Fig. 71 Supplv current variation with temperature

PACKAGE DETAILS
Dimensions are shown thus: mm (in)
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