1980_RCA_COS_MOS_Integrated_Circuits 1980 RCA COS MOS Integrated Circuits
User Manual: 1980_RCA_COS_MOS_Integrated_Circuits
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Solid
State
ROil
Solid
State
RCA COS/MOS
Integrated Circuits
This DATABOOK contains complete
technical information on RCA standard commercial COS/MOS integrated
circuits. It covers the full line of RCA
standard A- and B-series digital logic
circuits, and special-function circuits
(telecommunications and special interface and display driver circuits). An Index to Devices provides a complete
listing of types.
The DATABOOK is divided into nine
major sections. The first section includes classification and selection
charts, functional diagrams, and
photographs of available package options. This section is followed by a
discussion of general considerations
that should be taken into account in
the operation and application of
COS/MOS integrated circuits.
Three separate data sections provide
definitive ratings and characteristics
for (1) high-voltage B-series types, (2)
A-series types, (3) special-function
types.
Data pages for individual devices are
included as nearly as possible in alphanumerical sequence of type numbers.
Because some devices are grouped
together to show similarity of function
or data, individual type numbers may
be out of sequence. If you don't find
the type number you're looking for
where you expect it to be, check the Index to Devices.
'
The data sections are followed by a
Dimensional Outlines section, an Application Notes section, and a section
that lists RCA Sales Offices, Manufacturers' Representatives, and Authorized Distributors.
Table of Contents
Index to Devices. . . . .
Index to Application Notes.
Product Selection Guides. .
Product Classification Charts
Function Selection Charts .
Package and Ordering Information
Functional Diagrams. . . . . .
Industry-to-RCA Type Cross-Reference Guide.
General Operating and Application Considerations .
General Operating and Handling Considerations
A-Series COS/MaS Integrated Circuits
High-Voltage B-Series COS/MaS Integrated Circuits
COS/MaS Special Products. . . . . . . . . .
COS/MaS High-Voltage B-Series Integrated Circuits-Technical Data
COS/MaS A-Series Integrated Circuits-Technical Data . . .
COS/MaS Telecommunications, Display-Driver, and Interface
Circuits-Technical Data
Dimensional Outlines . . . . . . . . . . . . . .
Application Notes . . . . . . . . . . . . . . .
RCA Sales Offices, Manufacturers' Representatives; and
Authorized Distributors . . . . . . . . . . .
nail
Page
3
4
5
6
7
12
13
28
35
36
40
40
48
49
441
583
603
607 .
683
Solid IBrussels· Buenos Aires· Hamburg· Madrid· Mexico City· Milan
Montreal· Paris· Sao Paulo· Somerville NJ • Stockholm
State Sunbury-on·Thames
• Taipei· Tokyo
Infonnation furnished by RCA is believed to be accurate and reliable.
However, no responsibility is assumed by RCA for its use; nor for any
infringements of patents or other rights of third parties which may result
from its use. No license is granted' by implication or otherwise under any
patent or patent rights of RCA.
The device data shown for some types are indicated as preliminary or
objective. Preliminary data are intended for guidance purposes in
evaluating devices for equipment design. Such data are shown for types
currently being designed for inclusion in our standard line of commercially
available products. Objective data are intended for engineering evaluation
of types in the initial stages of design. The type designations and data are
subject to change, unless otherwise arranged. No obligations are assumed
for notice of change or future manufacture of these devices. For current
information on the status of preliminary or objective programs, please
contact your local RCA sales office.
Copyright 1980 by RCA Corporation
(All rights reserved under Pan-American Copyright Convention)
Trademark(s) ®Registered
Marca(s) Registrada(s).
Printed in USA 9-80
2
Index to Devices
This index does not include package
designation suffix letters for individual
type numbers; the various packages
available are shown in the data section.
Page
Data
Bulletin
File No.
Type No.
Page
Data
Bulletin
Fife No.
Type No.
Page
Data
Bulletin
File No.
CD4000A
CD4000B
CD4000UB
CD4001A
CD4001B
442
50
54
442
50
944
965
945
944
985
CD4025A
CD4025B
CD4025UB
CD4026A
CD4026B
442
50
54
492
116
944
965
945
916
1118
CD4053B
CD4054B
CD4055B
CD4056B
CD4057A
198
205
205
205
557
902
634
634
634
635
CD4536B
CD4555B
CD4556B
CD4565B
CD4724B
341
344
344
349
353
1245
856
658
1146
1111
CD4001UB
CD4002A
CD4002B
CD4002UB
CD4006A
54
442
50
54
445
945
944
965
945
920
CD4027A
CD4027B
CD4026A
CD4028B
CD4029A
496
124
499
126
502
941
942
937
1016
931
CD4059A
CD4060A
CD4060B
CD4062A
CD4063B
565
573
210
576
214
696
813
1120
816
805
CD22100
CD22101
CD22102
CD22104
CD22104A
564
569
589
593
593
1076
1039
1039
1259
1259
CD4006B
CD4007A
CD4007UB
CD4008A
CD4008B
58
446
62
451
66
1033
921
977
950
951
CD4029B
CD4030A
CD4030B
CD4031A
CD4031B
132
505
136
507
141
1028
932
1055
569
1073
CD4066A
CD4066B
CD4067B
CD4066B
CD4069UB
560
216
223
229
232
769
1114
909
609
804
CD22105
CD22105A
CD22659
CD40100B
CD40101B
594
594
595
357
362
1256
1256
1257
980
1000
CD4009A
CD4009UB
CD4010A
CD4010B
CD4011A
453
70
453
70
456
939
940
939
940
946
CD4032A
CD4032B
CD4033A
CD4033B
CD4034A
510
146
492
118
513
915
1081
918
1118
575
CD4070B
CD4071B
CD4072B
CD4073B
CD4075B
235
238
238
242
238
910
807
807
806
807
CD40102B
CD40103B
CD40104B
CD40105B
CD40106B
365
365
372
379
384
984
984
1220
1044
1017
CD4011B
CD4011UB
CD4012A
CD4012B
CD4012UB
74
78
456
74
78
986
947
946
986
947
CD4034B
CD4035A
CD4035B
CD4037A
CD4038A
150
517
156
520
510
1062
568
1101
576
915
CD4076B
CD4077B
CD4078B
CD4081B
CD4082B
246
235
250
242
242
903
910
810
806
806
CD40107B
CD40108B
CD40109B
CD40110B
CD40115
388
391
396
400
599
1015
1011
1018
1125
1075
CD4013A
CD4013B
CD4014A
CD4014B
CD4015A
459
82
462
86
464
935
936
922
1043
943
CD4038B
CD4040A
CD4040B
CD4041A
CD4041UB
146
522
114
525
161
1081
624
1063
572
934
CD4085B
CD4086B
CD4089B
CD4093B
CD4094B
253
257
261
266
270
811
812
1003
836
869
CD40116
CD40147B
CD40160B
CD40161B
CD40162B
601
405
408
408
408
1234
1117
1047
1047
1047
CD4015B
CD4016A
CD4016B
CD4017A
CD4017B
91
467
95
471
100
1024
952
953
927
1113
CD4042A
CD4042B
CD4043A
CD4043B
CD4044A
529
164
532
168
532
589
954
590
956
590
CD4095B
CD4096B
CD4097B
CD4098B
CD4099B
274
274
223
278
283
879
879
909
979
948
CD40163B
CD40174B
CD40181B
CD40182B
CD40192B
408
415
419
424
428
1047
1031
989
1008
993
CD4018A
CD4016B
CD4019A
CD4019B
CD4020A
475
105
478
110
460
929
1034
923
1045
928
CD4044B
CD4045A
CD4045B
CD4046A
CD4046B
166
535
172
536
176
956
614
1119
637
1099
CD4502B
CD4503B
CD4506B
CD4510B
CD4511B
287
290
293
297
302
1002
1224
1009
899
901
CD40193B
CD40194B
CD40206B
CD40257B
426
372
433
436
993
1220
1007
982
CD4020B
CD4021A
CD4021B
CD4022A
CD4022B
114
463
86
466
100
1063
933
1043
919
1113
CD4047A
CD4047B
CD4048A
CD4048B
CD4049A
543
162
549
169
554
623
1123
636
1124
599
CD4512B
CD4514B
CD4515B
CD4516B
CD4517B
307
310
310
297
314
1032
614
614
899
1146
CD4023A
CD4023B
CD4023UB
CD4024A
CD4024B
456
74
78
469
114
946
986
947
930
1063
CD4049UB
CD4050A
CD4050B
CD4051B
CD4052B
194
554
194
198
198
926
599
926
902
902
CD4516B
CD4520B
CD4527B
CD4532B
CD4536B
319
319
324
329
333
608
808
1006
676
1166
Type No.
Data
Bulletin
Page FileNo.
Type No.
___________________________________________________________________ 3
Index to Application Notes
Number
Till.
ICAN-1080 ...... "Dlgltal-to-An.log Conv.,.lon U.lng th. RCA-CD4007A COs/MOS IC" (Abstract)... .. .. .. .. ... .
ICAN-8088 ...... "Tlm.keeplng Adv.nc•• Through COS/MOS Technology" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICAN-8101 ...... "Th. RCA COS/MOS Ph •••-Locked Loop-A V.rsatll. Building Block lor Micro-Power Digital .nd
An.log Application." .. . .. .. .. . .. . .. .. .. . . .. . .. .. .. .. . . .. .. . .. .. . .. .. .. . .. .. . .. .. . .. .. . . . .. . ..
ICAN-8168 ...... "COS/MOS MSI Countar .nd Reglltar Dellgn .nd Appllc.tlonl" (Abstract) .....................
ICAN-6178 ...... "Nol.. Immunity 01 COS/MOS Integr.t.d-Clrcull Logic G.t.... (Abstr.ct) .............. ,. .......
ICAN-8210 ...... "A Typlc.1 D.ta-G.therlng .nd PrOCHllng Syst.m Ullng CD4000A-S.rlel COS/MOS P.rte"
(Abstr.ct) ............................................................... ; .. . .. . .. .. .. .. .. .. ..
ICAN-6230 ...... "Ullng th. CD4047A In COs/MOS Timing Appllcatlonl" ..............•........................
ICAN-6289 ...... "A COS/MOS PCM T.I.m.try and R.mote D.ta Acqullllion D.llgn" (Abltr.ct) .......•.........
ICAN-8315 ...... "COS/MOS Int.rlaclng Slmpllll.d" ........ .................... ..... ........... ................
ICAN-6348 ...... "Appllc.tlons olth. RCA-CD4083B COs/MOS SchmlH Trlgg.r" ....... , ....•.........•....... ,.
ICAN-8382 ... . .. "Using th. CD4520B to D.llgn Divide,. with Symmetrlc.1 Output." (Abltract) .................•
QCAN-6374 ... . .. "Th. COS/MOS CD4059A Progr.mmabl. Dlvld.-by-N Count.r In FM .nd Cltlz.nl-B.ndTr.nlC8l,.r Tun.,." (Abstract).. . . .. . . .. .. .. .. . . . .. .. .. . . . .. . . . .. . . . . .. . .. . .. . .. . .. .. . .. .. .. . .
ICAN-6488 ...... "A.table .nd MonOltable O.clll.to,. Using RCA COS/MOS Dlgltallnt.gral.d Clrcultl" . .... . .. ..
ICAN-6498 ...... "D.llgn 01 Flx.d .nd Programm.bl. Count.,. Ullng the RCA-CD4018A COS/MOS Pre••H.bl.
Dlvld. -by-UN" Count.r (Abstr.ct) .. .. . .. . .. .. . .. . . .. . . . . .. . . .. . .. . .. . . . . . . . .. .. . .. .. .. .. . • . .. .
ICAN-8525 ...... "Guld. to B.tt.r H.ndllng .nd Oper.tlon 01 CMOS Int.gr.t.d Clrcultl" . . . . . . . . . . . . . . . . . . . . . . . . .
ICAN-6532 ...... "Fundam.nt.l. 01 Te.tlng COS/MOS Int.grat.d Clrculls" ......................................
ICAN-8552 ...... "A Ba.lc S.I.cllon Guld. to DlglI.1 Count.,." .................................................
ICAN-8558 ...... "Und.,.t.ndlng Bull.red .nd Unbull.red CMOS Ch.ract.rlsllc." . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICAN-8563 ...... "Radl.llon R.slstanca 01 the COS/MOS CD4000A and CD4000B S.rI••" ........................
ICAN-8584 ...... "Appllc.llon 01 CD40107BE COS/MOS Du.1 NAND Bull.r".. .. .. .. . ........ ............ .. .. .. ..
ICAN-6572 ...... "COS/MOS EI.ctrostallc-Dlsch.rge Protecllon N.twork." . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICAN-8576 .. . . .. "Pow.r-Supply Con.ld.rallons lor COS/MOS D.vlc••" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICAN-8587 ...... "Nois. Immunity 01 COS/MOS B-S.rI•• Int.gr.t.d Circuit." . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICAN-6595 ...... "Int.rlaclng Analog and Digital Dlapl.YI with CMOS Intagrat.d .Clrcults... . . . . . . . . . . . . . . . . . . . . . . •
ICAN-6600 ...... "Arlthm.llc Arrays Ullng Stand.rd COS/MOS Building Blocks" (Abstract) ......................
ICAN-8801 ...... "Transmlllion .nd Multlpl.xlng 01 An.log or Dlglt.1 Signals Utilizing th. CD4018A Qu.d BII.t.ral
Switch" (Abltr.ct). .. . . . .. .. . .. .. . . . .. . .. . . . . . . . .. . . .. . . .. . . .. .. . . .. .. .. . .. .. .. .. . .. .. .. . . . . ..
ICAN-6602 ...... "Int.rlaclng COS/MOS with Oth.r Logic F.mlll.... (AbstracO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICAN-8718 ...... "Low-Pow.r Digital Frequ.ncy Synth.slz.,. Utilizing COS/MOS IC·... (Ab.tr.ct) ................
ICAN-6733 ...... "B.tt.ry-Pow.r.d Dlglt.I-DI.pl.y Clock/Tlm.r .nd M.t.rlng Appllc.tlons Utilizing th.
RCA-CD4028A .nd CD4033A Dec.de Count.r.-7-Segm.nt Output Types" (Abltract) ..........
ICAN-8739 .. . . .. "COS/MOS R.t. MultlplI.rs-V.rsatll. Circuit. lor Synth.slzlng Digital Function." (Abstr.ct) . . . .
ICAN-8883 ...... "Slmpllll.d D•• lgn of Astable RC Osclll.tors Using th. CD4060B or two CMOS Inv.rt.rs" .......
4 __
~
P.ge
882
808
814
682
882
682
818
882
625
828
682
682
631
682
637
640
649
852
657
859
862
664
887
675
882
882
882
682
882
682
881
____________________________________________________________________
Product Selection Guides
________________________ 5
Product Classification Chart
MULTIVIBRATORS
GATES
Single-Level
NOR/NAND
CD4000B
CD4000UB
CD4000A
CD4001B
CD4001UB
CD4001A
CD4002B
CD4002UB
CD4002A
CD4011B
CD4011UB
CD4011A
CD4012B
CD4012UB
CD4012A
CD4023B
CD4023UB
CD4023A
CD4025B
CD4025UB
CD4025A
CD406aB
CD4078B
CD40107B
Multi-Level
OR/AND
CD4071B
CD4072B
CD4073B
CD4075B
CD4081B
CD4082B
Multlfunctlon/AOI
Decoders/
Encoders
CD4007UB
CD4007A
CD4009UB
CD4009A
CD4010B
CD4010A
CD4041UB
CD4041A
CD4049UB
CD4049A
CD4050B
CD4050A
CD4069UB
CD4502B
CD4503B
CD40107B
CD4019B
CD4019A
CD4030B •.
CD4030A·
CD4037A
CD4048B
CD4048A
CD4070B.
CD4077B.
CD4085B
CD4086B
CD4028B
CD4028A
CD4514B
CD4515B
CD4532B
CD4555B"
CD4556B"
CD40147B
REGISTERS
Shift
Storage
CD4006B
CD4006A
CD4014B
CD4014A
CD4015B
CD4015A
CD4021B
CD4021A
CD4031B
CD4031A·
CD4034B·
CD4034A
CD4035B
CD4035A
CD4062A
CD4094B
CD4517B
CD40100B
CD40104B
CD40194B
.See
Comparators
COUNTERS
FIFO
Buffer
CD4076B
CD40105B
CD4099B
CD4724B
CD40108B.
CD40208B.
Binary
Ripple
CD4020B
CD4020A
CD4024B
CD4024A
CD4040B
CD4040A
CD4060B
CD4060A
TIMERS
CD4045B
CD4045A
CD4536B
.See
Multlport
Register
Synchronous
CD4008B
CD4008A
CD4030B +
CD4030A'+
CD4032B
CD4032A
CD4038B
CD4038A
CD4063B
CD4070B+
CD4077B+
CD4585B
ALU/Rate
Multipliers
CD4057A
CD4089B
CD4527B
CD40181B
CD40182B
+ See
Multllunctlon!AOI
Parity
Generator/
Checker
CD40101B
Schmitt
Trigger
CD4093B
CD40106B
"See
Demultiplexers
CD4013B
CD4013A
CD4027B
CD4027A
CD4042B
CD4042A
CD4043B
CD4043A
CD4044B
CD4044A
CD4076B""
CD4095B
CD4098B
CD4099B""
CD4508B
CD4724B""
C.D40174B
"See
Monostable
Storage
Registers
CD4016B t:.
CD4016A t:.
CD4019B
CD4019A
CD4051B
CD4052B
CD4053B
CD4066B t:.
CD4066At:.
CD4067B
CD4097B
CD4512B
CD4555B Ell
CD4556B Ell
CD40257B
CD4046B
CD4046A
CD40108B"
CD40208B"
CD4034.B"
CD4034A"
t:.See Ell See
Quad
Decoders!
Bilateral Encoders
Switch
"See
Storage
Register
With Counter
CD4026B
CD4026A
CD4033B
CD4033A
CD40110B
CD4047B
CD4047A
CD4098B
CD4538B
CD4016B+
CD4016A+
CD4066B+
CD4066A+
For
LCD"
Drive
INTERFACE
CIRCUITS
CD4009UB
CD4009A
CD4010B
CD4010A
CD4049UB
CD4049A
CD4050B
CD4050A
CD40107B
CD40109B
CD40115V
CD40116V
+See
Multiplexers
DISPLAY DRIVERS
Mulllport
Register
Astable/
Monostable
MUL TIPLEXERS/
PHASE- QUAD
DEMULTIPLEXERS LOCKED BILATERAL
LOOP
SWITCHES
Analog/Digital
Data Selectors
CD4017B
CD4017A
CD4018B
CD4018A
CD4022B
CD4022A
CD4029B
CD4029A
CD4059A
CD4510B
CD4516B
CD4518B
CD4520B
CD40102B
CD40103B
CD40160B
CD40161B
CD40162B
CD40163B
CD40192B
CD40193B
ARITHMETIC CIRCUITS
Adders/
Comparators
Flip-Flops/Latches
Buffers &
Inverters
For
LED ••
Drive
CD4054B
CD4055B
CD4056B
CD22104 V
CD22.104AV
CD22105 V
CD22105A V
CD4511B
"Liquid
Crystal
Display
•• L1ght
Emitting
Diode
TELECOMMUNICATION
CIRCUITS
Crosspoint
Switches
Tone
Generator
CD22100 V
CD22101 V
CD22102 V
CD22859 V
V Indicates types designed for special applications. Ratings and characteristics data for these types differ
in some aspects from the standardized data for A- and B-series types. Refer to RCA data bulletin on
6 ____
__ ____________________________________ ____________________
these types for specific differ.ences. Data bulletin file numbers are shown on functional diagrams.
~
~
~
Function Selection Chart
Function
I
Type No.
I
No. of
Pins
Function
Gates
Gates (cont'd)
NOR/NAND
Dual 4-input NOR
Multllunction/AOI (conl'd)
Dual 2-input NAND buffer/driver
CD4002B
CD4002UB
CD4002A
CD4012B
CD4012UB
CD4012A
CD4025B
CD4025UB
CD4025A
CD4023B
CD4023UB
CD4023A
CD4001B
CD4001UB
CD4001A
CD4011B
CD4011UB
CD4011A
CD4078B
CD4068B
CD4000B
CD4000UB
CD4000A
CD40107B
OR/AND
Dual 4-input OR
Dual 4-input AND
Triple 3-input OR
Triple 3-input AND
Quad 2-input OR
Quad 2-input AND
CD4072B
CD4082B
CD4075B
CD4073B
CD4071B
CD4081B
Dual 4-input NAND
Triple 3-input NOR
Triple 3-input NAND
Quad 2-input NOR
Quad-2 input NAND
8-input NOR/OR
8-input NAND/ AND
Dual 3-input NOR plus inverter
Buffers and Inverters
Dual complementary pair plus
inverter
CD4007UB
CD4007A
Hex inverter
CD4069UB
Hex inverter/buffer (3-state)
CD4502B
Hex buffer (3-state non-inverting)
CD4503B
Hex buffer/converter (inverting)
CD4009UB
CD4009A
Hex buffer/converter (inverting)
CD4049UB
CD4049A
Hex buffer / converter (non-inverting) CD4010B
CD4010A
Hex buffer/converter (non-inverting) CD4050B
CD4050A
Quad true/complement buffer
CD4041UB
CD4041A
CD40107B
Dual 2-input NAND buffer/driver
Multifunction/AOI
Triple AND-OR bi-phase pairs
Quad exclusive-OR
Quad exclusive-OR
Quad exclusive-NOR
CD4037A
CD4030B
CD4030A
CD4070B
CD4077B
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
8,14
14
14
14
14
14
14
14
14
14
16
16
16
16
16
16
16
16
16
16
14
14
8,14
14
14
14
14
14
Quad AND/OR Select
I
Type No.
I
No. of
Pins
CD4019B
CD4019A
16
16
CD4085B
14
CD4086B
14
CD4048B
CD4048A
16
16
CD4028B
CD4028A
CD4532B
16
16
16
CD40147B
16
CD4514B
24
CD4515B
24
CD4555B
16
CD4556B
16
CD4093B
CD40106B
14
14
CD40109B
CD4009UB
CD4009A
CD4049UB
CD4049A
CD4010B
CD4010A
CD4050B
CD4050A
CD40107B
16
16
16
16
16
16
16
16
16
8,14
CD40115 V
22
CD40116 V
22
CD4047B
CD4047A
CD4098B
CD4538B
14
14
16
16
CD4013B
CD4013A
Dual "J-K" with set/reset capability CD4027B
CD4027A
CD4095B
Gated "J-K" (non-inverting)
Gated "J-K" (inverting and noninverting)
CD4096B
14
14
16
16
14
Dual 2-wide, 2-input AND/OR
invert (AOI)
Expandable 4-wide, 2-input
AND/OR invert (AOI)
Multifunctional expandable 8-input
(3-state output)
Decoders/Encoders
BCD-to-decimal decoder
8-input priority encoder
10-line to 4-line
BCD priority encoder
4-bit latch/4-to-16 line decoder
(outputs high)
4-bit latch/4-to-16 line decoder
(outputs low)
Dual 1-of-4 decoder/demultiplexer
(outputs high)
Dual 1-of-4 decoder/demultiplexer
(outputs low)
~chmitt
Trigger
Quad 2-input NAND
Hex
Interface
Quad low-to-high voltage
Hex high·to-Iow voltage (inverting)
Hex high·to-Iow voltage (noninverting)
Dual 2-input NAND buffer/driver
8-bit bidirectional CMOS-to- TTL
level converter
8-bit bidirectional CMOS-to-TTL
level converter
Multivibrators
Monostable /astable
Dual monostable
Dual precision monostable
Flip-Flops
Dual "0" with set/reset capability
14
V Indicates types designed for special applications. Ratings and characteristics data for these types differ
in some aspects from the standardized data for A- and B-series types. Refer to RCA data bulletin on
these types for specific differences. Data bulletin file numbers are shown on functional diagrams.
7
Function Selection Chart
Function
I
Type No.
I
No.
of
Pins
Multivibrators (cont'd)
Flip-Flops
Hex "0"
4-bit "0" with 3-state outputs
Latches
Quad clocked "0"
Quad NOR R/S (3-state outputs)
Quad NAND R/S (3-state outputs)
Dual 4-bit
8-bit addressable
Registers
Shift Reglsters-Stalic
Dual 4-stage with serial input/
parallel output·
18-stage
64-stage
Dual 64-bit
8-stage with synchronous parallel
or serial input/serial output
8-stage with asynchronous parallel
input or synchronous serial
input/serial output
4-stage parallel-in/parallel-out with
J-K input and true/complement
,output
4-bit universal bidirectional
with 3-state outputs
4-bit universal bidirectional
with asynchronous master reset
8-stage bidi!'ectional parallel dr
serial input/parallel output
32-bit left/right
8-stage shift-and-store bus
Shift Registers-Dynamic
200-stage
Storage Registers
8-bit addressable latch
CD40174B
CD4076B
16
14
CD4042B
CD4042A
CD4043B
CD4043A
CD4044B
CD4044A
CD4508B
CD4099B
CD4724B
16
16
16
16
16
16
24
16
16
CD4015B
CD4015A
CD4006B
CD4006A
CD4031B
CD4031A
CD4517B
16
16
14
14
16
16
16
CD4014B
CD4014A
16
16
CD4021B
CD4021A
16
16
CD4035B
CD4035A
16
16
CD40104B
16
CD40194B
16
CD4034B
CD4034A
CD40100B
CD4094B
24
24
16
16
CD4062A
12
4-bit "0" -type with 3-state outputs
4 X 4 Multiport
4 X 4 Multiport
16
16
16
24
24
FIFO Buffer Registers
4-bit X 16 word
CD40105B
16
CD4024B
CD4024A
CD4040B
CD4040A
CD4020B
CD4020A
14
14
16
16
16
16
Counters
12-stage
14-stage·
8
I
Type No.
I
No. of
Pins
Counters (cont'd)
CD4099B
CD4724B
CD4076B
CD40108B
CD40208B
Binary Ripple
7-stage
Function
Binary Ripple
14-stage counter/divider and
oscillator
Timers
21-stage
Programmable
Synchronous
Decade counter/divider plus 10
decoded decimal outputs
Divide-by-8 counter/divider with
8 decimal outpu!s
Presettable divide-by-"N" counter,
fixed or programmable
Programmable-divide-by- "N"
counter
Presettable up/down counter,
binary or BCD-decade
Presettable 4-bit BCD up/down
counter
Presettable 4-bit binary up/down
counter
Presettable 2-decade BCD down
counter
Presettable 8-bit binary down
counter
Presettable 4-bit BCD up/down
counter
Presettable 4-bit binary up/down
counter
Dual BCD up counter
Dual binary up counter
Decade counter/asynchronous clear
Binary counter/asynchronous clear
Decade counter/synchronous clear
Binary counter/synchronous clear
CD4060B
CD4060A
16
16
CD4045B
CD4045A
CD4536B
14
14
16
CD4017B
CD4017A
16
16
CD4022B
CD4022A
16
16
CD4018B
CD4018A
16
16
CD4059A
24
CD4029B
'CD4029A
16
16
CD4510B
16
CD4516B
16
CD40102B
16
CD40103B
16
CD40192B
16
CD40193B
CD4518B
CD4520B
CD40160B
CD40161B
CD40162B
CD40163B
16
16
16
16
16
16
16
CD4026B
CD4026A
16
16
CD4033B
CD4033A
16
16
CD40110B
16
CD4054B
16
CD4055B
16
CD4056B
16
CD22104V
40
Display Drivers
With Counter
Decade counter/divider with 7segment display outputs and
display enable
Decade counter/divider with 7segment display outputs and
ripple blanking
Up/Down Counter-LatchDecoder-Driver
For Llquld-Crystal-Dlsplay Drive
. 4-segment display driver
BCD-to-7 -segment decoder /driver
with "display-frequency" output
BCD-to-7 -segment decoder/driver
with strobed-latch function
4-digit decotler/driver with
hexidecimal display
Function Selection Chart
Function
I
Type No.
I
No. of
Pins
For Llght-Emitting-Diode Drive
BCD-to-7 -segment latch decoder /
driver
J
Adders/Comparators
Triple serial adder, negative logic
16
16
16
16
14
14
14
14
BCD rate multiplier
Binary rate multiplier
Look-ahead-carry block
(:D40181B
CD4057A
CD4527B
CD4089B
CD40182B
24
28
16
16
16
Parity Generator/Checker
9-bit
CD40101B
14
Multiport Register
4 X 4
4 X 4
a X1
8X1
CD40108B
CD40208B
CD4034B
CD4034A
24
24
24
24
CD4016B
CD4016A
CD4066B
CD4066A
14
14
14
14
CD221 00. V
16
CD22101.V
24
CD221 02 V
24
CD22859V
16
CD22104A V
40
4-bit magnitude comparator
V
40
Quad exclusive-OR gate
CD22105A V
40
Quad exclusive-OR gate
Quad exclusive-NOR gate
CD4511B
16
CD4053B
CD4052B
CD4051B
CD4097B
CD4067B
CD4016B
CD4016A
CD4066B
CD4066A
16
16
16
24
24
14
14
14
14
CD4019B
CD4019A
16
16
CD4555B
16
CD4556B
CD40257B
CD4512B
16
16
16
CD4046B
CD4046A
16
16
CD22105
Quad bilateral switch
Digital (Data Selectors)
Quad AND/OR select
Dual l-of-4 decoder/demultiplexer
(outputs high)
Dual l-of-4 decoder/demultiplexer
(outputs low)
Quad 2-line-to-1-line
a-channel
Phase-Locked Loop
Micropower
Arithmetic Circuits
Adders/Comparators
4-bit full adder with parallel carry
out
Triple serial adder, positive logic
CD4008B
CD4008A
CD4032B
CD4032A
16
16
16
16
I
No. of
Pins
CD4038B
CD4038A
CD4063B
CD4585B
CD4030B
CD4030A
CD4070B
CD4077B
ALU/Rate Multipliers
4-bit arithmetic logic unit
Multiplexers/Demultiplexers
Analog
Triple 2-channel
Differential 4-channel
Single 8-channel
Differential 8-channel
Single 16-channel
Quad bilateral switch
Type No.
Arithmetic Circuits (Cont'd)
Display Drivers (cont'd)
For Liquid-Crystal-Display Drive
4-digit decoder/driver with
decimal ·display
4-digit decoder/driver with
hexidecimal display
4-digit decoder/driver with
decimal display
Function
Quad Bilateral Switches
For transmission or multiplexing of
analog or digital signals
Telecommunication Circuits
Crosspoint Switches
4 X 4 crosspoint switch with
control memory
4 X 4 X 2 crosspoint switch with
control memory
4 X 4 X 2 crosspoint switch with
control memory
Tone Generator
Dual-tone multifrequency
tone generator
V Indicates types designed for special applications. Ratings and characteristics' data for these types differ
in some aspects from the standardized data for A- and B-series types. Refer to RCA data bulletin on
these types for specific differences. Data bulletin file numbers are shown on functional diagrams.
9
COS/MOS Microprocessor, Memory, and
Timekeeping Circuits
In addition to the logic and special-function integrated
circuits listed in the preceding pages, RCA also offers a
comprehensive and expanding line of COS/MOS
microprocessOl, memory, and timekeeping integrated
circuits.
The microprocessor and memory circuits include centralprocessing units (CPU's), custom and 'standard read-only
memories (ROM's), programmable read-only memories
(PROM's), random-,access memories (RAM's), generalpurpose memories, system expanders, input! output
COS/MOS Microprocessor and Memory Products
No. of Pins
Microprocessors
COSMAC 8-Bit CPU
CDP I 802
COSMAC 8-Bit Microcomputer
CDPI804
Standard ROM's (Firmware)
UT4 Utility Program
CDPR512
Microterminal Controller
CDPR522
Fixed-Point Arithmetic
CDPR582
Custom ROM's (Mask Programmable)
512x8
CDP1831
512x8
CDP1832
1024 x 8
CDP1833
CDPI834
1024x8
EPROM's
CDPI8U42 256 x 8 UV Erasable
RAM's
4x8
CD4036A
CD4039A
4x8
256xl
CD4061A
CD4006IA 256xl
CD40114B 16x4
1024 x I
CDPI821
256x4
CDPI822
128 x8
CDPI823
32x8
CDPI824
1024x4
CDPI825
256x4
MWS5101
MWS5114 1024x4
System Expanders
4-Bit Bus Buffer (For Memory)
CDP1856
4-Bit Bus Buffer (For 110)
CDPI857
4-Bit Latch/Decoder (256 x 4
CDPI858
Memory)
4-Bit Latch/Decoder (lK x I
CDPI859
Memory)
4-Bit Latch/Decoder (IK x 4
CDPI866
Memory)
4-Bit Latch/Decoder (4K x I
CDPI867
Memory
4-Bit Latch/Decoder (IK x 4
CDPI868
Memory, Latched Chip
Enable)
General-Purpose I/O
CDP1851
Programmable I/O (20 Lines)
CDP1852
Byte-Wide 110 (8 Lines)
CDP1853
N Line Decoder
CDP1854A UART
CDP1855
Multiply-Divide Unit
40
40
24
24
24
24
24
24
24
24
24
24
16
16
16
16
22
24
18
18
22
18
16
16
16
16
18
18
18
40
24
16
40
28
No.o(Pins
General-Purpose I/O
4-Bit Bus Buffer (For Memory)
16
CDPI856
16
CDPI857
4-Bit Bus Buffer (For liD)
CDPI858
4-Bit Latch/Decoder (256 X 4
16
Memory)
4-Bit Latch/Decoder (I K x I
CDPI859
16
MemorY)
Programmable Frequency
CDPI863
Generator
16
4-Bit Latch/Decoder (I K x 4
CDP1866
Memory)
18
4-Bit Latch/Decoder (4K x I
CDPI867
18
Memory)
4-Bit Latch/Decoder (IKx4
CDPI868
Memory, Latched Chip
18
Enable)
High-Speed 8-Bit Input Port
CDPI872
22
(1873 Compatible)
High-Speed I of 8 Decoder
CDPI873
(8205 Pinout)
16
High-Speed 8-Bit Input Port
CDPI874
22
(1853 Compatible)
22
High-Speed 8-Bit Output Port
CDPI875
Special-Purpose I/O
CDPI861
Video Display Controller
CDPI862
Color Generator Controller
CDPI864
PAL Video Controller
VIS Address Plus Sound
CDPI869
Generator
CDPI870
VIS Color Video Generator
VIS Compatible Keyboard
CDPI871
Encoder
VIS Color Video Generator
CDPI876
(RGB Bondout)
COSMAC Microboard Computer Systems
Single-Board Computers
Memory Boards
110 Expansion Boards
Prototyping Systems
System Development Aids
COSMAC Development and Support Systems
Development, Prototyping and Evaluation Systems
System Support Components
System Support Software
System Support Modules
24
24
40
40
40
40
40
10 _______________________________________________________________________
COS/MOS Microprocessor, Memory, and
Timekeeping Circuits
(I/O) circuits, COS MAC microboard computer systems
and COS MAC development and support 'systems.
For descriptive information on RCA microprocessor and
memory circuits, refer to the RCA "COSMAC
Microprocessor Product Guide", MPG-108B; to the
RCA technical data bulletins on specific types; or to the
RCA DATABOOK "COS/ MOS Memories,
Microprocessors, and Support Systems", SSD-260.
The timekeeping circuits include standard "off-the-shelf'
circuits for watches and auto clocks. Plus a custom design
capability to tailor these products to meet specific
requirements. The watch products include LCD display
circuits from 3V, to 6 digits and from 5 to 6 functions with
additional features such as stopwatch and alarm. The
auto clocks are stepping-motor-drive clock circuits, 2-, 3-,
and 4-MHz crystal-operated.
For descriptive information on RCA timekeeping
circuits, refer to the RCA technical data bulletins on
specific types.
COS/MaS Timekeeping Products
Function
Timekeeping
Watches
3% Digit
5 function LCD watch with
stopwatch
4 Digit
6 function LCD watch with
alarm
6 Digit
6 function LCD watch with
stopwatch
6 function LCD watch with
alarm
Type No.
CD22003
No. of
Pins
Chip
CD22007V2
Chip
CD22008V1
Chip
CD22018
Chip
Function
Auto Clocks
Quartz analog auto clock
(O.5·Hz push·pull)
Quartz analog auto clock
(60-Hz)
Quartz analog auto clock
(30·Hz push-pull)
Type No.
No.of
Pins
CD22012
14
CD22014
8
CD22015
12
---------------------------------------------------------------------"
COS/MaS IC Packages
Packages
D Suffix
Ceramic Dual-In-Line Packages
Welded-8ea114,16,24,
and 28-lead Versions
F'Suffix
Frit-Seal Ceramic Dual-In-Line Packages
22, 40-Lead Side-Brazed Versions
14,16,and 24-lead Versions
E Suffix
Plastic Dual-In-Line Packages
MiniDIP
8,14,16,18,22,24,and 40-Iead Versions
T Suffix
12-Lead TO-5 Style Package
I
CD4024A and CD4062A only
Ordering Information
Most RCA COS/MaS integrated circuits are available in the
following package styles and are identified by the Suffix
Letters indicated below: dual-in-line ceramic, dual-in-line
frit-seal ceramic, dual-in·line plastic, and in chip form.
Some types are only available in one or two package
styles. The available package styles for any specific type
are given in the technical data for that type.
When ordering COS/MaS devices, it is important that the
appropriate suffix letter be affixed to the type number of
the device required. For example, a CD4016B in a dual-inline ceramic package will be identified as the CD4016BD.
Package
Dual·ln-Line Welded-Seal or
Side-Brazed Ceramic
Dual-In-Line Frit-Seal Ceramic
Dual-In-Line Plastic
TO-5 Style
Chip
H Suffix
COS/MaS Chip
Suffix
Letters
D
F
E
T
H
12 _____________________________________________________________________
Functional Diagrams
'4
'3
J=A+B
K=O+E+F
NC
•J=A+S+C+O
M=G+H
NC
A
A
VOO
VOO
0,
K
H
S
4
B
4
12 02t5
CLOCK 3
II °2+4
5
IOO3t4
H
02
G
5
C
M
H
L
VSS
"
C
G
03
0
F
7
6
04
Vss
7
K=E+F+G+H
L -_ _ _....J 6
NC
92CS-24762
Dual 3-lnput NOR Gate
Plus Inverter
C04001A
CD4001B
CD4001UB
(Page 442)
(Page 50)
(Page 54)
CD4000A
CD4000B
CD4000UB
Quad 4-lnput NOR Gate
(Page 442)
(Page 50)
(Page 54)
CD4002A
CD4002B
CD4002UB
A
0
5,
*.
CD4008A
CD400SB
(Page 448)
(Page 62)
A
H=B
r,e
J~5
0
K~E
L~F
J=A-S·C-o
A--'-t--:--,
VSS _8_
Voo= 16
NC
9c5S-4140R2
G~A
H~e
r~c
J~0
K~E
L~F
Voo= 16
~'3
92CS-21S07
Hex Buffer/Converter
Non-Inverting Type
(Page 453)
(Page 70)
(Page 453)
(Page 70)
CD4010A
CD4010B
,
VOo
'4
PAR.'N.
VOO
VOO
2345676
'3
S
CD4009A
CD4009UB
~
~
~
~
~
~
VCC-'-
Hex Buffer/Converter
Inverting Type
(Page 451)
(Page 66)
(Page 445)
(Page 56)
CD4006A
CD4006B
G~A
9?CS-l'5G77"2
4-Bit Full Adder with
Parallel Carry Out
Dual Complementary Pair
Plus Inverter
Vss
18-Stage Static Shift
Register
VCC _,_
NC' '3
(CARRY'NI
(Page 442)
(Page 50)
(Page 54)
~
~
~
~
~
~
Vss _B_
c,O'.....- - - - - - - J
VOO=14
CD4007A
C04007UB
92CS~ 2'!lOtl9RI
92CS-24756
Quad 2-lnput NOR Gate
K
SET,6
0, 5
S
H
CLOCK, 3
2
0,
C,
~~~:~
CONT.
K-+--.
'---t!.!-- M
RESET,
c
SET2 S
F
L
M=G-H
02 9
SER. "
'N·
CLOCK!Q
CLOCK2 "
+-_-,
0_..:6
Vss 7
4
E
RESET2l0
'---t=--E
Vss
7
K=E·F·G·H
B
NC
92C5-25047
92C5-25046
92CS-24763
Quad 2-lnput NAND Gate
CD4011 A
(Page 456)
CD4011B
(Page 74)
CD4011UB
(Page 78)
.92C'-24759
Dual 4-lnput NAND Gate
CD4012A
(Page 456)
CD4012B
(Page 74)
CD4012UB
(Page 78)
Dual "0" Flip-Flop with
Set/Reset Capability
CD4013A
(Page 459)
CD4013B
(Page 82)
S
VSS
a-Stage Synchronous Shift
Register with Parallel or
Serial I nput/Serial Output
CD4014A
(Page 462)
CD4014B
(Page 86)
___________________________________________________________________ 13
Functional Diagrams
YDD
7
DATA A
CLOCKA
RESET A
5
4
6
3
QIA
Q2A
Q4A
14
14
CLOCK 13
INHIBIT
0
4
"2"
ID
"4"
IN/OUT
SIG 0
"5"
"6"
c
w
c
6
"
OUTIIN
C
7
VSS
8
YSS
Dual 4-Stage Static Shift Register
with Serial InputlParaliel Output
CD4015A
(Page 464)
CD4015B
(Page 91)
DATA
RESET
"9"
15
(Page 324)
(Page 95)
Q4
13
vDD
0-:
::>
YSS
0
w
a:
......w
::>
'"
a5
8
Presettable Oivide-by-"N"
Counter Fixed or Programmable
Decade CounterlDivider w;th
10 Decoded Decimal Outputs
CD4017A
(Page 471)
CD4017B
(Page 100)
Quad Bi lateral Switch
Q3
II
V55
CD4016A
CD4016B
Q2
6
92C5-25074
92C5-21627
92C5-25048
4
DUT
'LI~;OUT
L--.o
QI
14
"
CARRY
SIG C
Q48
10
0
w
c
"e"
CONT
CLOCK
u
"7"
Q38
~~~m
-'
4
'"
~
0
Q2S
II
~
"3"
RESE:T 15
SIG B
IN/OUT
"I" 113" 1'5"
"("
CONT
QIS
12
RESETS
3
OUTIIN
Q3A
13
CLOCKs
CO NT
A
OUTIIN 2
YDD
~
"0"
CLOCK
10
DATAS
IN~t¥S
IS
SIG A
9
15
VDD
IN/OUT
16
CD4018A
CD4018B
(Page 475)
(Page 105)
PAR,IN,
I'
16
2345678
9
01
'"::>t-
04
4
84
A3
83
A2
82
AI
J
r
1203
3
4
5
6
13
12
14
15
I
:04'IA4Ko'+IB
o
...oa:
...u.w
:::>
'"~
~:=:~
CONT,
V55
CD4020
CD4020B
A-+---...,
14 ~DD
8 --'2=+-_ _---,
13
o
14
12 01
G
H
INPUT I
PULSES
" Q2
9 Q3
r
E
6 Q4
RESET
5 Qs
4
Q~
92C5- 24761
Triple 3-lnput NAND Gate
CD4023A
CD4023B
CD4023UB
(Page 456)
(page 74)
(Page 78)
(Page 483)
(Page 86)
(Page 489)
(Page 114)
"5"
w
0
"7"
14
YDD
S
13
(Page 486)
(Page 100)
VDD
16
G
CLOCK
D
H
2
CL~
E
I
12
,.
10
RESET
K
7
CD4025A
CD4025B
CD4025UB
(Page 442)
(Page 50)
(Page 54)
~
d
0
0
8
~
~
,
5 CARRY OUT
ENABLE
ENABLE
92CS- 24760
Triple 3-lnput NOR Gate
~
,
DISPLAY
DISPLAY
==---t=-- C
b
f
'----t'-'''-L
F
'l~
.
INHIBIT
OUT
IN
"
UNGATEO
·c·
SEGMENT
7
CD4024A
CD4024B
w
0
12
CD4022A
CD4022B
A
NC=8,IO,13
92CS-25051 R3 ' YSS
7-Stage Ripple-Carry
Binary CounterlDivider
0
0
Divide-by-S CounterlDivider with
8 Decoded Decimal Outputs
3 Q7
':::::=:---J-=-C
"4"
Synchronous Serial Inputl
Serial Output
0
'"....
II
CARRY
Q.
...
......a:
....::>
0
0
92CS-25073R~2----' OUT
0
L
F
...'"::>
...::>
"3"
Asynchronous Parallel or
CD4021A
CD4021B
(Page 480)
(Page 114)
VDD
.:::::>
7
10
Yoo= 16
YSs=8
8
YSS
8-Stage Static Shift Register
14-Stage Binary Ripple Counter
(Page 478)
(Page 110)
"2"
4
92C5-25047
V55
CD4019A
CD4019B
"I"
15
"6"
92C5-25036
Quad ANDIOR Select Gate
"0"
13
CLOCK~
014
RESET
2
14
SER. II
IN.
2 013
II
8
YSS
CLOCK
CLOCK
INHISIT
RESET
Vss
92CS.2~078RI
Decade CounterlDivider with 7Segment Display Outputs and
Display Enable
CD4026A
(Page 492)
CD4026B
(Page 118)
14 _____________________________________________________________________
Functional Diagrams
BUFFERED
'6
~~:!~Y~'O
INPUTS
"
°2
aCD
INPUTS
o
A
B
12 C
"
2 02
3
14
, .2
~
;~
6 7
7 4
9
~
a
'6 OUTPUTS
BUFFERED
""~
OCTAL
DECODED
~,uci:~~S
g~6rJ:CD
DECODED
OUTPUTS
(I OF 101
••
'4~
UP/DOWN '0
CLOCK
H
3
K
C
0
G
4
M
5
6
9
VSS
E
2 04
'5
@iiY
J'A(£)B
K'C(£)D
OUT
Vss
RESET2
VOD
A
6 0,
BINARY/
DECADE 9
14
8
L' E(£)F
M' G(£)H
92CS-I')I}.
9ZCS-I'7410RI
92CS-'7Ie7AI
vss
92CS -17190R3
Dual J-K Master-Slave
Flip-Flop with Set-Reset
Capability
CD4027A
CD4027B
Preseuable Up/Down Counter,
Binary or BCD-Decade
BCD-to-DBcimal Decoder
(Page 496)
(Page 124)
CD4028A
CD4028B
CD4029A
CD4029B
(Page 499)
(Page 128)
(Page 502)
(Page 132)
,.
VDD
A,..!l!_-r---'
DATAl
IN
MODE 10 CONTROL
CONT
LOGIC
RECIRC
DATA 2
IN
B,
64
'0
'2
6
SUM 2
RESET
SUM 3
DELAYED
CLOCK
OUT
VDO ',6
Vss =8
92CS
..
w
0
·
64-Stage Static Shift
Register
CD4031A
CD4031B
(Page 507)
(Page 141)
Triple Serial Adder
Positive Logic
CD4032A
CD4032B
(Page 510)
(Page 146)
•
LAMP
TEST
CARRY
5 OUT
RIPPLE
BLK
RIPPLE
BLK
'N
OUT
92CS-17663
Voo =16
190~9
AE
AlB
AIS
PIS
CL -1'-_ _-'
0
0
,.
VSS' 8
NC· 3,4,11,12,13,14
~
~
•~
",
•
" ~
STAGES DATA
OUT
CLOCK
INHIBIT
(Page 505)
(Page 138)
SI------,
CLOCK
INVERT I
Quad Exclusive-OR Gate
CD4030A
CD4030B
9CCS'Z9;;'Oo..~-='---'''''
Vss
Decade Counter/Divider
with· 7 -Segment Display
Outputs and Ripple Blanking
8-Stage Static Bidirectional
Parallel/Serial Input/Output
Bus Register
CD4033A
CD4033B
CD4034A
CD4034B
(Page 492)
(Page 118)
(Page 513)
(Page 150)
VDD
Voo -14
A,
Vee -I
SER.{J :
IN
K
,
'0
INPUT
A2
82
'NVERT 2
7
14 QIO
'2 09
12-STAGE
, RIPPLE
~
COUNTER
VOD al6
Vss =8
5
0,/0, at0203/03 0./0./
C2
-1
4-Stage Parallel InlParaliel
Out Shift Register with
J-K Serial Inputs and True/
Complement Outputs
CD4035A
CD4035B
(Page 517)
(Page 156)
-------L.!Q
AND/OR PAIR
6
r ---
13
09
4
D2
111
'"~
,..::>
0
07
:;]
06
05
0:
04
03
.~
::>
~
Q2
L---rr-------.F E2
TIC' OUT
92(S"9966RI
r---
0'2
15 01'
PULSES
TIC 2
RESE T
•
~
CLie. 6
PIS
'6
B,
'NVERT,
"
a'
RESET
------L!.D3
C3 ---iL _ _ _AND/OR
PAIR
"
___
_ _ _ ....J
E3
VOD =16
!l2tS-199'HiU
Triple ANDIOR Bi-Ph"e
Pair
CD4037A
(Page 520)
CD4038A
CD4038B
Vss
92CS·IT663
Triple Serial Adder
Negative Logic
(Page 510)
(Page 146)
9ZCS-29066RI
12-Stage Ripple-Carry Binary
Counter/Divider
CD4040A
CD4040B
(page 522)
(Page 114)
15
Functional Diagrams
40-----1
7()----+-1
13(}----+-1
-C
K
'~8
K·C
9
L-E
o
VSS·7
'~" M
VOO=14
M-O
CLOCK
5(}----.-1
12
N=D
N
92CS - 20034 RI
POLARITY
6 ( }--'---L--J
VOO~
Quad True/Complement
Buffer
CD4041A
CD4041UB
14(}----+-1
L
(Page 525)
(Page 161)
13
'2CS-20191
ENABLE
Vss
vsso-!-
(Page 529)
(Page 164)
NC
NC
ENABLE
92CS-20221RI
C04043A
CD4043B
B
Vss
Quad 3·State NOR R/S
Latch
Quad Clocked "0" Latch
CD4042A
CD4042B
8
92CS-20222
Quad 3-St.te NAND R/S
Latch
(Page 532)
(Page 168)
CD4044A
C04044B
(Page 532)
(Page 168)
PHASE COMP lOUT
2
R3
--1-,
CI
1---.....
LOW
I)-----....,~R
C2
T
4,5,6,9,10,11,12.13'
vss
NO CONNECTION
92C5-29107
Vss •
Micropower Phase-Locked Loop
21·Stage Counter
CD4045A
CD4045B
(Page 535)
(Page 172)
(Page 538)
(Page 176)
CD4046A
CD4046B
A~G'A
BINARV CONTROL INPUTS
'FUNCTION' CONTROL'
3·STATE
CONTROl
"
+ TRIGGER
12 RETJUGG(R
I
EXTERNAL
RESET
L _____ _
---.!
Low-Power Monostable/Astable
Multivibrator
CD4047A
CD4047B
(Page 543)
(Page 182)
B~H'ii
C~I.E
[:
DC
EXPAND
- TRIGGER
8
~~
92CS-29112
O~J-5
13
12
"
15
i [~ ~
J
OUTPUT
VSS·B
Voo"6
Multi-Function Expandable
8-lnpl" Gate
C04048A
CD4048B
F~L'F
VCc-'-
'"'----~
92CS~22249
E~K'E
(Page 549)
(Page 189)
vss _B_
NC -13
NC -16
92CS-27~06
Hex Buffer/Converter
'Inverting Type
CD4049A
CD4049UB
(Page 554)
(Page 194)
16 ______________________________________________________
~--
Functional Diagrams
A
B
e
0
F
~
~
~
~
~
~
G·A
IIX"
CHANNELS
IN/OUT
H'B
{~ \~
I"e
CHANNELS
IN/OUT
J"O
K"E
;
~
6
2
7
4
COMMON
OUT/IN
"y"
CHANNELS
IN/OUT
A
L·F
CONTROL
L
2
3
12
14
15
II
I
5
2
4
13
"x"
COMMON
OUT/IN
"y"
COMMON
OUT/IN
VOO"'6
CONTROL {
--'----'
{
rr
I
2
3
.
II 10 9 6 Voo "16
:
VSS' 8
VEE" 7
INH
VSS • 8
92CS - 26373
~IN~H~_ _ _~ VEE"7
Vce - , VSS _8_
92CS - 26372
92CS-2:1!o07
NC "16
Single S-Channel Analog
Multiplexer/Demultiplexer
Hex Buffer/Converter
Non-Inverting Type
CD4050A
(Page 554)
CD4050B
(Page 194)
IN/OUT {
ow.
12
a
13
b,
IN/OUT {
2
14
ax OR ay OUTIIN
I
15
b, OR by OUT/IN
{:C
CONTROL { -=~'-----'
IN/OUT
(Page 198)
CD4051 B
c>
5
,y-_.=:3'--;=::r:",,,--l
A
Differential 4-Channel Analog
Multiplexer/Demultiplexer
CD4052B
(Page 198)
ex OR cy OUTIIN
Voo" 16
VSS "8
vEE" 7
INH
92C5 - 22708Rl
4-Segment Liquid-Crystal
Display Driver
Triple 2-Channel
Multiplexer/Demultiplexer
CD4053B
VSS
CD4054B
(Page 198)
~VEE
7
(Page 205)
~voo
16
r ~-- -- - I
8
20
......ffi
i
'"
...>-'
...-'
[
5
2'
BCD
INPUTS
...Za:
22
7-
23
0 ......
7-SEG·
OUT·
... ,"0
<:>0
o ... u
u"'
...
STROBE
SEGMENT
OUTPUTS
I
DISPLAY FREQ. IN
"', 0
....
~o~o?!.
____ -.J
ALL It/PUTS PROTECTED BY
92CS- 20092RI
'--________
BCD-to-7-Segment Decoder/Driver
with "Display-Frequency" Output
Liquid-Crystal Display Driver
CD4055B
(Page 205)
I
COSIMOS PROTECTION NETWORK
BCD-to-7-Segment Decoder/Driver
with Strobed- Latch Function
Liquid-Crystal Display Driver
CD4056B
(Page 205)
17
Functional· Diagrams
,"""",{:.,
SELECT
,
C 6
'00'
SELECT- {'"
CO2
~
.
"
OVERFl.OW
OUTPUT
""
ROT.tITE-Z
4·Bit Arithmetic Logic Unit
C04057 A
(page 557)
tRo21
14·Stage Ripple·Carry
Binary Counter/Divider
and Oscillator
C04060A
(Page 573)
C04060B
(Page 210)
Programmable Divide·by·"N"
Counter
C04059A
(Page 565)
IN/OUT
o
RC
Q
REC~-'~-'_r-~
CASCADING
INPUTS
CL,O
CL20
AO
',~
A3
15
:~
WORo"A" {
13
1
U
'B 4
5 A >B
A' B 3
AcB 2
7 A<8
6
:;
Voo' 16
o
'B
WORO"B"{~~ :~
92CS- 24664
CONT
IN/OUT
IN/OUT
O~c.--..:..----J.~
I~~
,
SIG 0
N/OUT
'1-__--1
VSS'B
92CS-24S16RI
I
',I
I
150,.....J-----o7J
OUTIIN
SIG C
VOO'24
VSS"2
92CS- 24924RI
IN/OUT
200·Slage Dynamic
Shift Register
C04062A
(Page 576)
4·Bit Magnitude Comparator
C04063B
(Page 214)
Quad Bilateral Switch
C04066A
(Page 560)
C04066B
(Page 218)
16·Channel
Multiplexer/Demultiplexer
C040678
(Page 223)
18 ______________________________________________________________
~
___
Functional Diagrams
A~
B2
A~G'A
A
B
C
B~H'ii
C~I'C
G
0 6
VSS ,,7
VSS=7
92CS - 23874R3
92CS-23737R2
10 L
C
3 J
4 K
6
8
J.A(t)B
K'C(t)O
VOO"4
A
10 L
1'M
F~L'F
6 , S"NO CONNECTION
4 K
0
F 9
G 12
H 13
E~K'E
VO D -14
8
E 8
0~J.5
F
J
3
C5
M
L
H
'G~H
'I
+F
E
G
".
12
13
VSS'7
VOO"4 92C$- 24S66A2
Vss
92CS- 27685
a-Input NAND/AND Gate
CD4068B
Hex Inverter
(Page 229)
Quad Exclusive-OR Gate
(Page 232)
CD4069UB
Quad 2-lnput OR Gate
(Page 235)
CD4070B
CD4071 B
(Page 238)
Voo
Y OO
14
A I
A
B
C
0
E
F
G
H
8 2
C 8
5
9
o
I
J
3
6
4
6
H
12
10
G
13
E
~
o
II
I
II
12
9
B-=-II---I
A
E 4
10
c
9
3
4
10
12
H
G 13
L
L
Vss
92CS-27686
Vss
VSS
92.C5-27571
Dual 4-lnput OR Gate
CD4072B
92CS -27687
Triple 3-lnput OR Gate
Triple 3-lnput AND Gate
(Page 238)
OUTPUT
0lSA8LE
M
I
CD4075B
(Page 242)
CD4073B
N
2
A'
B2
J
4
K
A
C 5
o
3
(page 238)
6
C
0
E 8
F 9
G 12
II
H 13
j 'A(t)8
R.c(t)o
15
RESET
M
M'G(t)H
[ 'E(t)F
vss·a
VOO·16
92C5 - 2449 7R2
92C5 - 23877R4
92CS-24885RI
4-Bit D·Type Register
CD4076B
(Page 246)
Quad Exclusive-NOR Gate
CD4077B
(Page 235)
a-Input NOR/OR Gate
CD4078B
(Page 250)
___________________________________________________________________ 19
Functional Diagrams
INHI81:11~,O
81 2
3
C
INHIBI:~~~
8
A
10
II
F
G
13
B2 6
C2 8
02 9
K
H
4
E2
E'INHIBIT+AB+CO
LOGIC
HIGH
LOGICO'LOW
r.
9lCS-2'7!lB3
92CS - 27510
Quad 2-lnput AND Gate
CD4081B
EI
CI 12
01 13
0
(Page 242)
92CS-23890R2
Dual 2-Wide, 2-lnput
AND-OR-INVERT (AOn
Gate
CD4085B
(Page 253)
Dual 4-lnput AND Gate
CD4082B
(Page 242)
A-"""t....,....-,
H
B
BINARY RATE
G
K-+-.
LOGIC '" HIGH
LOGIC 0= LOW
VOO"4
ENA8LE/EXP~I-,-I_ _ _ _ _ _- - ,
J = INH
vss·a
92CS.2S004R,
R
2
(Page 261)
8 0
6
0
VOO'14
VSS '7
NC -I
Q
20 __________
~
Gated J-K Master-Slave
Flip-Flop, Non-Inverting
Inputs
CD4095B
(Page 274)
8
o6
92CS - 24427RI
(Page 270)
(Page 266)
Q
Q
R
2
RESET-------'
92C5 - 24430RI
(TERMINALS 4,5,6,7,14,13, 12,11,
RESPECTIVELY)
CD4094B
CD4093B
S
0
92C5 - 24564RI
Quad 2-lnput NAND
Schmitt Trigger
SET - - - - - - - ,
13
0
8-Stage Shift-and-Store
Bus Register
F
Binary Rate Multiplier
CD4089B
13
S
RESET
D-,,+--'
92CS-23880
SET
PARALLEL OUTPUTS 01-08
L
92CS- 2 38 rORL
Expandable 4-Wide, 2-lnput
AND-OR-INVERT (AOn
Gate
CD4086B
(Page 257)
K3
C
VOO'16
VSS' 7
NC '4
+ ENABLE + AB+CO+EF+GH
'---;"'-- II
Gated J-K Master-Slave
Flip-Flop, Inverting and
Non-Inverting Inputs
CD4096B
(Page 274)
_______________________________________________________
Functional Diagrams
VDD
2 RXCXO I
~
{
x
I
I
1 '-.'-.
I
I
I
I
y
7
'-------........
I
fou01N
-TR
RESET
tOUT/IN
VOo'16
·5S· a
p2
6
Q2
2
03
0'
05
9
II
13
14
06 15
Q3
04
05
Strobed Hex Inverter/Buffer
(Page 287)
6
PI
CLOCK
3 01
4
5 02
02A
03A
703
04 10
9 04
05 12
II 05
16.VOo a-v5S
12
02
13
14
3
2
03
13
VOo'I6
15
·55' a
UP/DOWN
CARRY IN
CARRY OUT
RESET
92C5-24824
alA
4- BIT
LATCH
3-STATE
OUTPUTS
a?A
aoA
RESET
gl~;rs~Tc+-------------,
OOB
aOB
alB
OIB
02B
.
06
03B
4-BIT
LATCH
3-STATE
OUTPUTS
a2B
a3B
S TROBE.,,-_ _...J
RESET L-_ _ _ _ _ _ __
92C5
92CS-32392RI
Hex Buffer
3-State Non-Inverting
(Page 290)
CD4503B
r
0
E
C
0
0
E
R
L
A
T
C
H
o 6
~
LE/STROBE
·S5,a
(Page 293)
7-SEGMENT
OUTPUTS
I
c2
21494~'
Dual 4-Bit Latch
CD4508B
[T
B I
04
(Page 283)
OIA
I
01
B-Bit Addressable Latch
CD4099B
STROBE
6
BCD
INPUTS
PRESET
ENABLE
07
92CS-2442!5RI
VOO
(Page 278)
OISABBLE 15
CD4502B
P4
03
,
OUTPUT c:::::::::::::;--~
DISABLEt
OOA
OOA
2
06 14
92CS-22921RI
P3
02
'203
13 04
'405
,. 06
2~253
Multivibrator
CD4098B
06
VoO'I6
V55 -a
P2
01
9 00
'0 01
II Q2
Dual Monostable
DISABLE
A
10
RX2
CX2
9ZCS-
(Page 223)
QI
Voo :16
Vss:8
RxCx 121
Differential B-Channel
Multiplexer/Demultiplexer
THREE-STATE
OUTPUT 4
DISABLE
12
INHIBIT
3
01
L
A
T
C
H
E
S
Q2
9
92CS-249BOR2
CD4097B
WRITE DISABLE
DATA
10 02
+TR
Voo '24
Vss =12
01
7 01
RESET
.;>--"'"o---J
I
6
MONO I
3
IN/OUT1:~-j·" t~,
IN/OUT
4
5
+TR
-TR
12 :
0
R
I
V
E
R
"
II c
)
10 d
9 •
15,
14 g
3-STATE
DISABLE
INHIBIT ------~,""lo
00
01-2
0
1
g~~~~1L
14 SELECT
OUTPUT
AOII
{ 8-12
VOO-16
vss· a
C-13
CD4!5128
4
at
,
02-3
CHANNEL 03-4
INPUTS
04-5
05-6
06-7
07-9
92C5- 2~OB3R2
VOD"I£;
BC D Presettab Ie Up/Down
Counter
CD4510B
(Page 297)
BCD-to-7-Segment
Latch Decoder Driver
CD4511B
(Page 302)
B-Channel Data Selector
CD4512B
(Page 307)
___________________________________________________________________ 21
Functional Diagrams
DATA I
DATA 2
3
DATA 3 21
A
B
LATCH C 4 TO 16
o DECODER
OATA4 22
PRESET
ENABLE
~2:.:3~======-_.J
P3
~:
CLOCK
CATA(OI)
WRITE
ENABLE
2
03
04
VOO'I6
VSS' 8
UP/DOWN
512
513
514
515
WE' 0-- QI6---032--~48---Q64
WE'I----017---033---049--HiZ
IOF 2 SHIFT REGISTERS. TERM. Not.
IN PARENTHESES ARE FOR 2 NO HALF.
VOO,I6
CAiiRYi'N
VSS'8
CARRY OUT
RESET
92CS·30371
92C:5·24824
92CS - 24597
3 alA
4 Q2A
5 a3A
Binary Presattable Up/Down
Counter
004516B
(Page 297)
Dual 64-Bit Shift Register
004517B
(Page 314)
BCD
RATE
SELECT
CLOCK
6 Q4A
INPUTS
~
I~ ~5
STROBE
i g 10 CASCADE
••
RATE
OUTPUTS
INHIBIT
tCARRYllN II
.;.10/.16
14
3
15
01
O~
13
P4
4-Bit Latch/4-to-16
Line Decoder
C04514B
(Page 310)
C04515B
(Page 310)
Output "High" on Select
Output "Low" on Select
CLOCK A
12
P2
17
20 SID
14
13
16
15
CLOCK
6
PI
19 511
STROBE
INHIBIT
I~ SO
10 51
8 52
7 53
6 54
5 55
4 56
18 57
S~TNT~
10 alB
12 Q2B
13 03B
• DUTY
• OUT
4
CLEAR I
1404B
R
VOo'l~
RESET B
15
VOO-16
YSS'8 .
92'CS-24~06AI
92CS-Z"91~IU
12CS-26!6ORI
VSS·'
Dual Up Counter
004518B
(Page 319)
BCD
004520B
(Page 319)
Binary
BCD Rate Multiplier
C04527B
8-Bit Priority Encoder
(Page 324)
(Page 329)
004532B
\bo
16
A 2
B
E
A
14
B
13
E
15
•
L......o.;;:4'-QO
5 01
6 Q2
7 Q3
12
II
I
9
00
01
02
03
92CS -22918RI
'-II~>-'II\J'V--.. VDD
INHIBIT
Yoo,I6
VSS'8
'ICS-IDaTl
Programmable Timer
004536B
(Page 333)
92C5-24253
Dual Precision Monostable
Multivibrator
(Page 341)
C04538B
Dual Binary-to-l-of-4
Decoder/Demultiplexer
Output "High" on Select
004555B
(Page 344)
22 ________________________________________________________________
Functional Diagrams
10
A 2
3
A
B
E
4
QO
5
iii
6 Oz
7Q!
14
12
/Xl
13
II
10
9
iii
15
WORO"A" f O
AI
A2
A3
7
2
f>B 4
A-B
A8
3 A'B
12 A-0.5 V). Reversal of
polarities will forward-bias and short
the structural and protection diode
between Voo and Vss.
* THESE
DIODES ARE INHERENTLY PART OF THE
MANUFACTURING PROCESS
(b) For improved B-series COS/MaS prod-
uct.
6. Large values of resistors in series with
Voo or Vss should be avoided; transient turn-on of input protection diodes can result from drops across
such resistors during switching.
(c) ForCD4049UB, CD4050B, andCD40109B
COS/MaS types.
Output Rules
01 ~ 25 V
D2:::!50V
A problem occasionally encountered in
handling and testing low-power semiconductor devices, including MaS and
small-geometry bipolar devices, has
been damage to gate oxide and/or p-n
junctions. Fig. 3 shows the gate-oxide
protection circuits used to protect COSt
MaS devices from static electricity damage. ICAN-6572 gives further information on protection circuits. Although
these circuits are included in all COSt
MaS devices, the handling precautions
in ICAN-6572 and ICAN-6525 should be
observed.
3. When COS/MaS circuits are driven
by TTL logic, a " pull-up" resistor
should be connected from the COSt
MaS input to 5 volts (further information is given in ICAN-6602).
IN/OUT
DIODE BREAKDOWN
Gate-Oxide Protection Network
2. All COS/MaS inputs should be term inated. An exception can be made in
the case of unbuffered NOR and
NAND gates (A-series and US types)
where terminating one of the series
inputs to the proper polarity will not
permit current flow caused by a floating input. Thus, tying low one of the
inputs of an unbuffered NAND gate,
or tying high one of the inputs of an
unbuffered NOR gate will satisfy this
requirement.
When COS/MaS inputs are wired to
edge card connectors with COSt
MaS drive coming from another PC
board, a shunt resistor in the range'of
100 kohms should be connected to
Voo or Vss, as applicable, in case the
inputs become unterminated with the
power supply on.
4. Voo should be equal to or greater than
Vee for COS/MaS buffers which have
two power supplies (except for the
CD40109B, and in particular, for CD4009 and CD4010 COS/MOS-to-TTL
"down"-conversion devices).
5. Power-source current capability
should be limited to as Iowa value as
reasonable to assure good logic operation.
The absolute-maximum input-current rating of ±10 mA, shown in the
published data, protects the device
against the possible occurence of an
induced Voo - Vss latch condition, or
damage to the input protection diodes. Latch-up conditions are explained in ICAN-6525.
.. THESE DIODES ARE INHERENTLY PART OF THE
MANUFACTURING PROCESS.
92CS-27967RI
(d) For COS/MaS transmission gates.
Fig. 3-Gate-oxide protection networks used in
RCA COS/MaS integrated circuits.
Input Signals and Ratings
1. Input signals should be maintained
within the power-supply voltage
range, Vss :5 V,:5 Voo. If the input signal exceeds the recommended inputsignal-swing range, the input current
1. The power dissipation in a COS/MaS
package should not exceed the rated
value for the ambient temperature
specified. The actual diSSipation
should be calculated when (a) shorting outputs directly to Voo or Vss, (b)
driving low-impedance loads, or (c)
directly driving the base of p-n-p or
n-p-n bi-polar transistor.
2. Output short circuits olten result from
testing errors or improper board assembly. Shorts on buffer outputs or
across power supplies greater than 5
volts can damage COS/MaS devices.
3. COS/MaS, like active pull-up TTL,
cannot be connected in the "wireOR" configuration because an "on"
PMOS and an "on" NMOS transistor
________________________________________________________________________ 37
General Operating and Application Considerations
4.
5.
6.
7.
could be directly shorted across the
power-supply rails. (Exception: CO40107B)
Paralleling inputs and outputs of
gates is recommended only when the
gates are within the same IC package.
Output loads should return to a voltage within the supply-voltage range
(Voo to Vss).
Large capacitive loads (greater than
5000 pF) on COS/MaS buffers or
high-current drivers act like short circuits and may over-dissipate output
transistors.
Output transistors may be over-dissipated by operating buffers as linear
amplifiers or using these types as
one-shot or astable multivibrators.
Noise margin is the difference between
the noise-immunity voltage (V,l or VIH)
and the output voltage Vo. Noise-margin
voltage is the maximum voltage that can
be impressed upon an input voltage V,N
(where V,N is the VOL or VOH voltage ofthe
preceding stage) at any (or all) logic I/O
terminals without upsetting the logic or
causing any output to exceed the output
voltage (Vo) conditions specified for Vll
and VIH ratings. Fig. 5 illustrates the
noise-margin concept in a simple system. Minimum noise margins for buffered B-series COS/MaS devices are 1,
2, and 2.5 volts, respectively, for supply
voltages of 5, 10, and 15 volts.
Noise Immunity and Noise Margin
The complementary structure of the inverter, common to all COS/MaS logic
devices, results in a near-ideal input-output transfer characteristic, with switching point midway (45% to 55%) between
the 0 and 1 output logic levels. The result
is high dc noise immunity.
Fig. 4 shows a typical transfer curve that
may be used to define the dc noise immunity of COS/MaS integrated circuits.
The noise-immunity voltage (V,l or V,H)
is the noise voltage at anyone input that
does not propagate through the system.
Minimum noise immunity for buffered Bseries COS/MaS devices is 30, 30, and
27 per cent, respectively for supply voltages Voo of 5,10, and 15 volts and 20 per
cent of Voo for all unbuffered gates. The
V,l and V,H specifications define the
maximum permissible additive noise
voltage at an input terminal when input
signals are within 50 millivolts ofthe supply rails.
10
VOU1IGHI
9
VIL(TVP)
-i
I
-----1-I
VOUT
VNML· VILIMAX,)-VO(LOWI
I
I
I
I
5
VNMH • Va (HIGH)- VtH (MIN.)
I
I
I
I
I
I
a
----t.-:-I
234
I
r-- V1HITYP1...,l
I
"OllOW)
-~
I
~
678
VIL(MAX.)
9
~
VIHIMINJ
V,N
Fig. 4- Typical transfer curve for a Inverting
gate at Voo = 10 V.
Fig. 5 - Noise margin example using inverters.
Of the two noise-limitation specifications (noise immunity and noise margin), RCA considers noise immunity to
be more practical for COS/MaS devices
because COS/MaS outputs are normally within 50 millivolts of supply rails.
Noise immunity increases as the input
pulse width becomes less than the propagation delay of ttie circuit. This condition is often described as ac noise immunity. (Further information on noise immunity is given in ICAN-6587).
Clock Rlse- and Fail-Time Requirements
Most COS/MaS clocked devices have
maximu m rise- and fall-time ratings (normally 5to 15 microseconds). With longer
rise or fall times, a device may not function properly because of data ripplethrough, false triggering problems, etc.
Some B-series COS/MOS counters have
Schmitt-trigger shaping circuits built into the clock circuit, removing the restriction for input rise or fall times. Long rise
and fall times on COS/MaS buffer-type
inputs cause increased power dissipation which may exceed device capability
for operating power-supply voltages
greater than 5 volts.
Parallel Clocking
Process variations leading to differences
In input threshold voltage among random device samples can cause loss of
data between certain synchronously
clocked sequential circuits, as shown in
Fig. 6. This problem can be avoided ifthe
maximum clock rise time (t..eL) for cascading any two CMOS sequential devices Is limited in accordance with the
following equations:
A Series Types
.
_ 0.8 Voo (v)
Maxlmumt,CL 1.25 (v) X tp(ns)
B Series Types
.
_ 0.8 Voo (v)
Maxlmumt..eL 1.15 (v) X tp(ns)
where t p = tpHl or tPlH (whichever is
smaller) for the unit A in Fig. 6 as specified on the device data sheet at the specified value of Voo and loading conditions.
Schmitt trigger circuits such as the CO4093B are an ideal solution to applications requiring wave-shaping.
CASCADING WITH SLOW CLOCK
CAN CAUSE ERROR
CL
C
0.7'100
~
I
L
QI
~
E
VOO
.. 3VOD
I
~
I'
~
~~!.
SWITCHING ...
~DD
o,----.-II~
\
- - - - -
PROPER
SWITCHING POINT"
....
' _ _0_,7_V.::00:.. ......
92CS-33024
Fig. 6 - Error effect that results from a slow
clock in cascaded circuits.
Three-State Logic
Three-state logiC can be easily implemented by use of a transmission gate in
the output circuit; this technique provides a solution to the wire-OR problem
in many cases.
Chip Assembly and Storage
RCA COS/MaS integrated circuits are
provided in chip form (H suffix) to allow
customer design of special and complex
circuits to suit individual needs. COS/
MaS chips are electrically identical to
and offer the features of their counterparts sealed in ceramic and plastic packages. The following paragraphs describe
mounting conSiderations, packaging,
shipping and storage criteria, handling
38 __________________________~----------------------------------
General Operating and Application Considerations
criteria, visual inspection criteria, testing
criteria, and bonding pad layout and dimensions for each chip.
Mounting Considerations. All COS/MaS
chips are non-gold backed and require
the' use of epoxy mounting. DuPont
No's. 6838 or 5504A conductive silver
paste or equivalent is recommended. In
any case the manufacturer's recommendations for storage and use should be
followed. If DuPont No., 6838 or 5504A
paste is used, the bond shoulq be cured
at temperatures between 185°C and
200° C for 75 minutes.
In COS/MOS circuits MOS-translstor pchannel substrates (n-type bulk material) are connected to Voe, therefore, when
chips are mounted and a conductive
paste Is used care must be taken to keep
the active substrate Isolated from ground
or other circuit elements.
Packing, Shipping, and Storage Criteria.
Solid-state chips, being small in size and
unencapsulated, are physically fragile
and small in physical size, and therefore,
require special handling considerations
as follows:
1. Chips must be stored under proper
conditions to insure that they are not
subjected to a moist and/or contaminated atmosphere that could alter
their electrical, physical, or mechanical characteristics. After the shipping
container is opened, the chip must be
stored under the following conditions:
A. Storage temperature, 40° C max.
B. Relative humidity, 50% max.
C. Clean, dust-free environment.
2. The user must exercise proper care
when handling chips to prevent even
the slightest physical damage to the
chip.
3. During mounting and lead bonding of
chips the user must use proper assembly techniques to obtain proper
electrical, thermal, and mechanical
performance.
4. After the chip has been mounted and
bonded, any necessary procedure
must be followed by the user to insure
that these non-hermetic chips are not
subjected to a moist and contaminated atmosphere which might cause the
development of electrical conductive
paths across the relatively small insulating surfaces. In addition, proper
consideration must be given to the
protection of these devices from
other harmful environments which
could conceivably affect thei r
performance and/or reliability.
Handling Criteria. The user should find
the following suggested precautions
helpful in handling COS/MaS chips.
Because of the extremely small size and
fragile nature of chips, the equipment
designer should exercise care in
handling these devices.
For I!dditional handling considerations
for COS/MaS devices, refer to ICAN6525, "Guide to Better Handling and Operation of CMOS Integrated Circuits."
1. Grounding
a. Bonders, pellet pick-up tools, table
tops, trim and form tools, sealing
equipment, and other equipment
used in chip handling should be
properly grounded.
b. The operator should be properly
grounded.
2. In-Process Handling
a. Assemblies or subassemblies of
chips should be transported and
stored in conductive carriers.
b. All external leads of the assemblies
or subassemblies should be shorted together.
3. Bonding Sequence
a. Connect Vee first to external connections, for example, terminal 14
of the CD4001AH.
b. Remaining functions may be connected to their external connections in any sequence.
4. Testing
a. Transport all assemblies of chips
in conductive carriers.
b. In testing chip assemblies or subassemblies, the operator should be
properly grounded.
Visual Inspection Criteria. All standard
commercial COS/MaS chips undergo a
visual inspection which is patterned after MIL-STD-883, Method 2010, Condition B with modifications reflecting
COS/MaS requirements.
'
Testing Criteria. COS/MaS chips are dc
electrically tested 100% in accordance
with the same standards prescribed for
RCA devices in standard packages.
Device Testing
RCA COS/MaS circuits are 100-percent
tested by circuit probe in the wafer stage
and are 100-percent tested again after
they have been packaged. DC tests of
RCA devices are performed at 5, 10, 15,
and 20 volts; functionality is checked at
2.8, 17, and 20 volts depending on family
(I.e., A or B series). Sample testing is
used to assure adherence to quality requirements and ac specifications.
Static tests, high-speed functional and
dc parametric tests, are performed at
wafer and package stages by means of a
Teradyne J283 test set. A Teradyne
S157CM test set and a Marcodata M D 154
test set are used in dynamic testing. Dynamic tests are performed with 15and 50
picofarad loads. Testing at 15 picofarads
is accomplished primarily by laboratory
"benc~-test" techniques; automatic testing at 15 picofarads is difficult because
of the high input capacitance (approximately 20 to 35 picofarads) of most automatic ac test sets.
Users should follow the sequence below
when testing COS/MaS devices:
1. Inst;!rt the device into the test socket.
2. Apply Vee.
3. Apply the input Signal.
4. Perform the test.
5. On completion of test, remove the input signal.
6. Turn off the power supply (Vee).
7. Remove the device from the test socket and insert it into a conductive carrier. COS/MaS devices under test must
not be exposed to electrostatic discharge or forward biasing of the intrinsic protective diodes shown in Fig.
3.
Detailed information on the techniques
employed in the testing of RCA COS/
MaS integrated circuits are described in
ICAN-6532 included in the Application
Notes section of this DATABOOK.
Device Mounting
Integrated circuits are normally supplied
with lead-tin plated leads to facilitate
soldering into circuit boards. In those
relatively few applications requiring
, welding of the device leads, rather than
spldering, the devices may be obtained
with nickel-plated Kovar leads .. ltshould
be recogn ized that this type of plating
will not provide complete protection
against lead corrosion in the presence of
high humidity and mechanical stress.
*MIL-M-38510, paragraph 3,5,6,1 (a), lead
material
________________~--------------------------__---------------------39
I.
General Operating and Application Considerations
In any method of mounting integrated
circuits which involves bending or form~
ing ofthe device leads, it is extremely important that the lead be supported and
clamped between the bend and the
package seal, and that bending be done
with care to avoid damage to lead plating. In no case should the radius of the
bend be less than the diameter of the
lead. It Is also extremely important that
the ends of bent leads be straight to assure proper insertion through the holes
in the printed-circuit board.
A-SERIES COS/MOS
INTEGRATED CIRCUITS
RCA CD4000A-series types have a maximum dc supply-voltage rating of -0.5 to
15 volts, and a recommended operating
supply-voltage range of 3 to 12 volts. The
major features of this series are as follows:
• Quiescent current specified to 15
volts
• 5-volt and 1o-volt parametric ratings
• Maximum input leakage of 1IJAat 15
volts over the full package operating-temperature range
• 1-volt noise margin (full package
temperature range)
Table I shows the maximum ratings and
the recommended operating supply-voltage range for RCA A-series COS/MaS
integrated circuits.
Static Electrical Characteristics
Table II shows the standard dc electrical
characteristics for A-series types. The
data sheet for each of these types contains the family characteristics shown in
Table I plus additional dccharacteristics
that are type-dependent.
Dynamic Electrical Characteristics
A-series dynamic, electrical characteristics are specified for individual types under the following conditions: Voo = 5 V
and 10V; TA =25°C (temperaturecoefficient is typically 0.3%/° C); CL = 15 pF; t,
, and tf of inputs = 20 ns.
HIGH-VOLTAGE B-SERIES
COS/MOS INTEGRATED
CIRCUITS
RCA-CD4000B-series types have a maximum dc supply-voltage rating of-0.5 to
20 volts, and a recommended operating
supply-voltage range of 3 to 18 volts. The
major features of this ser.ies are as follows:
• High-voltage (20-V) ratings
• 100% tested for quiescent current at
20 V
.
• 5-V, 10-V, and 15-V parametric ratings
• Standardized, symmetrical output
characteristics
• Maximum input current of 1IJA at 18
V over full~package-ternperature
range; 100 nA at 18 V and 25°C
• Noise margin (full package-temperature range) =
1VatVoo = 5V
2VatVoo = 10 V
2.5VatVoo = 15V
• Meets all requirements of JEDEC
Tentative Standard No. 13B, "Standard Specifications for Description of
'B' Series CMOS Devices
JEDEC Minimum Standard
Under the sponsorship of the Joint Electron Devices Engineering Council
(JEDEC) of the Electronic Industries Association (EIA), minimum industrial
standards have been established for the
Table 1- Maximum Ratings and Recommended Operating Conditions for A-series COS/MOS
Integrated Circuits
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, Voo (Voltages referenced to Vss terminal) ..•.••.•.••.• -0:5 to +15V
INPUT VOLTAGE RANGE, ALL INPUTS ....•......•..••.......••....•.•.••.•.•. -0.5 to liDO +0.5 V
POWER DISSIPATION PER PACKAGE (Po):
For TA = -40 to +60°C (Package Type E) .•.••..•....•.....•...•........•..........•.•.. 500 mW
For TA = +60 to +85°C (Package Type E) ••..•.•...............•...... Derate Linearly to 200 mW
For TA = -55 to +100°C (Package Types D, H) ................•......•..•..•............ 500 mW
For TA = +100 to +125°C (Package Types D, H) •.......•............. Derate Linearly to 100 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR:
For TA = Full package-temperature range (All package types) ..•........•..........•.... 100 mW
OPERATlNG"TEMPERATURE RANGE (TA):
Package Types D, H .••.....•.•............•..........•...•.•.•.•••.••••.•••••.. -55 to +125° C
Package Type E .•.........................••.....•..' .....•.......•....•.•...•... -40 to +85° C
STORAGE-TEMPERATURE RANGE TSTG) .......•....••...•........•.........•...••• -65 to 150°C
LEAD TEMPERATURE (During Soldering):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max.................. +265° C
RECOMMENDED OPERATING CONDITIONS
For maximum reilablllty, nominal operating conditions should be selected so that operaatlon Is always within the following ranges:
CHARACTERISTIC
Supply-Voltage Range (For TA = Full PackageTemperature Range)
LIMITS
Min.
Max.
3
12
UNITS
V
40 _____________________________________________________________________
General Operating and Application Considerations
Table II - A-Series Static Electrical Characteristics (Full Package Temperature Range)
LIMITS
CONDITIONS
SYMBOL
VOL
VOH
VIN
PARAMETER
VOLTS
MIN.
MAX.
VOLTS
MIN.
TYP.
MAX.
UNITS
5
10
-
5
10
-
0
0
0.05
0.05
V
V
Output High
0
0
-
-
5
10
4.95
9.95
5
10
-
-
V
V
5
10
3
2.25
4.5
-
V
V
1.4
2.8
5
10
2.25
4.5
-
3
-
V
V
4.2
9.0
-
-
5
10
3
2.25
4.5
-
V
V
-
-
0.8
1.0
5
10
3
2.25
4.5
-
V
V
Noise Margin
(Input Low)
-
4.5
9.0
-
5
10
1
1
-
V
V
Noise Margin
(Input High)
-
-
0.5
1.0
5
10
1
1
-
-
-
V
V
-
15
±10-s
±1
/1A
Quiescent Device
Leakage
-
-
-
Output Source and
Sink current
-
-
-
-
Noise Voltage
VNL
(551 Types) (Input Low)
Noise Voltage
VNH
(SSI Types) (Input High)
Noise Voltage
VNL
(MSI Types) (Input Low)
Noise Voltage
VNH
(MSI Types) (Input High)
VNMH
IILI
hH
IL
IONI
lop
VDD
Output Low
~oltage
~~Itage
VNML
Vo (volts)
Input Leakage
Low
-
3.6
7.2
-
1.5
1.5
1.5
1.5
-
-
5,10,15 See Data Sheets
5,10
See Data Sheets
JiA
mA
Note: Logic Level Inversion Assumed in Table II.
maximum ratil)gs, static and ac electrical characteristics of B-series CMOS integrated circuits. The JEDEC standard
(JEDEC Tentative Standard No. 13B)
defines B-series CMOS integrated circuits as a uniform family of both buffered
and unbuffered types that haVe an absolute dc supply-voltage rating of at least
18 volts.
The JEDEC minimum standard also includes in the B-series CMOS types that
have analog inputs or outputs and. inaddition. have maximum ratings and logical input and output parameters that
conform to B-series specifications
wherever applicable. These CMOS devices are also designated by the suffix
"B".
Buffered CMOS devices are types in
which the output "on" impedance is independent of any and all valid input logic
conditions, both preceding and present.
All such CMOS product are designated
by the suffix "B" following the basic type
number.
All B-series CMOS devices can directly
replace their A-series counterparts in
most applications. The UB types are
high-voltage versions of corresponding
A-series (unbuffered) types.
Unbuffered CMOS devices are types
that meet all B-series specifications except that the logical outputs are not buffered and the noise-immunity voltages.
V,L and V,H• are specified as 20 and 80 per
cent. respectively. of Voo for operation
from 5 or 10 volts. and 17 and 83 per cent.
respectively. of VDO for operation from 15
volts. All such CMOS product are designated by the suffix "UB".
Table III lists the JEDEC minimum
standards established for the maximum
ratings and recommended operating
conditions for B-series CMOS integrated circuits.
Table IV shows the JEDEC standards for
the static electrical characteristics of
CMOS B-series integrated circuits.
Standardized RCA Ratings
and Static Characteristics
RCA B-series COS/MOS integrated cir-
cuits meet or exceed the most stringent
requirements of the JEDEC B-series
specifications. Table V shows the standardized maximum ratings and recommended operating supply-voltage range
for RCA B-series COS/MOS integrated
circuits. The standardized static electrical characteristics for these devices are
shown in Table VI. As with the JEDEC
specifications. the RCA standardized
characteristics classifies the B-series
devices into three leakage (quiescentdevice-current) categories. Table VII
lists the RCA types in each category and
indicates types that. although they are
still B-series types. differ in one or more
static characteristics.
Tables V and VI show that. in a number of
important respects. RCA has established.
new performance standards for B-series
COS/MOS logic circuits:
1. Tight limits for all packages
RCA devices use the same set of limits for all package styles. The JEDEC
standard establishes two sets of limits
for most dc (static) parameters; a
___________________________________________________________________ 41
General Operating and Application 'Cor1siderations
Table IIi - JEDEC Minimum Standards for Maximum Ratings
and RecOmmended Operating Conditions for B-serles CMOS
Integrated Circuits'
Absolute MaxhTlUm Rlltlngs (Voltages
DC Supply Voltage
Vee
Input Voltage
V'N
DC Input Current
!,1Ii
(anyone input)
Storage-Temperature Range Ts
referenced to Vss):
-0.5 to +18
Vdc
Vdc
-0.5 to Vee +0.5
±10
mAdc
·C
-65 to +150
Recommended Operating Conditions:
DC Supply Voltage
Vee +3 to +15
Operating-Temperature Range. TA
Military~Range Devices
-55 to +125
Commercial-Range Devices
-40 to +85
Vdc
·C
·C
'Reprinted from JEDEC Tehtative Standard No. 13-B. "Standard
Specifications for Description of B-Series CMOS Devices."
Table IV - JEDEC Standard for Static Characteristics of a.Series CMOS Integrated Circuits'"
PARAMETER
100
TEMP.
RANGE
Quiescent
Device Current
Voo
(Vdc)
Mil
5
10
15
Comm
5
10
15
Mil
5
10
15
CONDITIONS
TLOW·
Min Max
VIN = Vss or VOO
Min
LIMITS
+2SoC
Tvp
Max
THIGH'·
Max
Min
0.25
0.5
1.0
0.25
0.5
1.0
7.5
15
30
1.0
2.0
4.0
1.0
2.0
4.0
7.5
15
30
1.0
2.0
4.0
1.0
2.0
4.0
GATES
BUFFERS.
FLlP·FLOPS
uAdc
All valid input
combinations
VIN = VSS or VOO
30
60
120
uAdc
Comm
5
10
15
Mil
5
10
15
Comm
5
10
15
All valid input
combinations
4
16
4
8
16
30
60
120
5
10
20
5
10
20
150
300
600
20
20
40
80
150
300
600
8
VIN = VSS or VOO
MSI
VOL
uAdc
Low-Level
VIL
High·Level
Output Voltage All
5
10
15·
VIN = VSS or VOO
jlol ERATURE ITAJ-25-C
GATE-TO-SOURCE VOl.TAGE IVGsJ--5V
d
~
-IO~
ffi
-15
-IOV
~
-20~
-15V
,
DRAIN-T~-SOURCE VOlTAGE (VOSJ-V
Fig. 7 - Typical output low (sink) current
characteristics.
DRA'N-T'D-SDUR'"
VOI..TAGE IVosl-V
Fig. B-Minimum output low (sink) current
characteristics.
Fig. 9 - Typical output high (source) current
characteristics.
DRAIN-TO-SOURCE VOl.TAGE IVosJ-V
-1:11
-10
-:II
AMBJENT TEW'ERATURE ITA)-ZS-C
GAlE-TO-SOURCE VOl.TAGE tVssl--:II
v
-IOV
-15 V
-100
-50
50
100
AMBIENT TEMPERATURE ITAJ--C
Fig. 10-Minimum output high (source) current characteristics.
Fig. 11- Variation of normalized output low
(sink) current 10L and output high (source)
current 10H with temperature.
15
5
'0
SUPPl.Y VOLTAGE (Vool-VOLTS
Fig. 12-Variation of normalized output low
(sink) current 10L and output high (source)
current 10H with supply voltage.
AMBIENT TEMPERATURE (tA)= 25°C
4
6
8
10
12
14
SUPPLY VOLTAGE (Vool-VOLTS
16
1.0AO CAPACITANCE
Fig. 13-Variation of low-to-high (ITLH) and
high to low (ITHL) transition time, and low-tohigh (tPLH) and high-to-Iow (tPHL) propagation
delay time with temperature.
B-Serles Dynamic (AC) Switching
Parameters
Table VIII defines the major COS/MOS
ac characteristics, with reference to the
waveforms shown in Figs. 16 through 19.
Test conditions of Voo, low capacitance
(Cc), and input conditions are given for
individual types in the published data.
Fig. 14-Variation of low-to-high (ITLH) and
high-to-/ow (trHc) transition time with
supply voltage.
Fig. 15-Variation of transition time ItTHL'
ItTLH' with load capacitance.
Outputs should be switching from 10% Voo to
90% Voo in accordance with device truth table.
Fig. 16- TranSition times and propagation
delay times, combination logic.
Fig. 17 - Clock-pulse rise and fall times and
pulse width.
47
General Operating and Application Considerations
Table VIII - Dynamic Electrical Characteristics - Definitions
Characteristic
Symbol
Limits
Max.
Min.
Propagation Delay:
Outputs going high to low
Outputs going low to high
tPHl
tPlH
X
X
Output Transition Time:
Outputs gOing high to low
Outputs going low to high
tTHL
tTLH
X
X
Pulse Width-Set, Reset, Preset
Enable, Disable, Strobe, Clock
tWl or tWH
X
Notes
1
Clock Input Frequency
fCl
X
Clock Input Rise and Fall Time
trCl, ttel
X
Set-Up Time
tsu
X
1
Hold Time
tH
X
1
Removal Time - Set, Reset, Preset-Enable
tREM
X
1
Three State Disable Delay Times:
High level to high impedance
High impedance to low level
Low level to high impedance
High impedance to high level
tPHZ
tPZl
tpLZ
tPZH
NOTE:
1,2
X
X
X
X
(1)
By placing a defining min. or max. in front of definition, the limits can change from min.
to max., or vice versa.
(2)
Clock input waveform should have a 50% duty cycle and be such as to cause the outputs
to be switching from 10% Voo to 90% Voo in accordance with the device truth table.
COS/MOS Special Products
RCA supplies a variety of special
COS/MaS products that have operating supply-voltage ranges and other
characteristics that differ from the
standardized data specifilld for A- and
B- series COS/MaS integrated circuits.
OUTPUT RL"I kG
OUTPUT
DISABLE
C,
50 ....
[VDO fo, 'PlZ GIld. lplL
.Vss tor 'PHZ orad IpZH
C&20069R4
CS-29514RI
Fig. 18- Three·state propagation delay wave
shapes and test circuit.
Fig. 19-5etup times, hold times, removal
time, and propagation delay times
for positive-edge triggered sequentiallogic circuits.
These special applications types include
crosspoint switches for use in telephone
and PBX systems, in studioaudioswitching applications, and as multisystem bus
interconnects; tone generators for use in
dual-tone telephone dialing systems; Interface circuits for level-shifting applications to interface CMOS logic levels with
different logic types; and display drivers
non-multiplexed, 4-digit, 7-segment
LCD types containing all the circuitry
necessary for driving conventional LCD
displays without the need for external
components.
48 ___________________________________________________________________
COS/MOS High-Voltage
B-Series Integrated Circuits
Technical Data
_ _ _ _ _ _ _ _ _ _ _ _ 49
I
CD4000B, CD4001 B, CD4002B, CD4025 B Types
COS/MOS NOR Gates
Features:
• Propagation delay time = 60 ns (typ.) at
CL=50pF,VOO=10V
• Buffered inputs and outputs
• Standardized symmetrical output characteristics
• 100% tested for maximum quiescent current at 20 V
• 5-V, 10-V, and 15-V parametric ratings
• Maximum input current of 1 p.A at 18 V
over full package-temperature range;
100 nA at 18 V and 25 0 C
• Noise margin (over full package temperature
range):
1 VatVoo=5 V
2 V at VOO = 10 V
2.5 Vat VOO = 15 V
High-Voltage Types (20-Volt Rating)
Dual 3 Input
plus Inverter - CD4000B
Quad 2 Input - CD4001 B
Dual 4 Input - CD4002B
Triple 3 Input - CD4025B
RCA-CD4000B, CD4001B, CD4002B, and
CD4025B NOR gates provide the system
designer with direct implementation of the
NOR function and supplement the existing
family of COS/MOS gates. All inputs and
outputs are buffered.
The CD4000B, CD4001B, CD4002B, and
CD4025B types are supplied in 14-lead
hermetic dual-in-line ceramic packages (D
and F suffixes), 14-lead dual-in-line plastic
packages (E suffix), 14-lead ceramic flat
packages (K suffix), and in chip form (H
suffix).
CD4000B
FUNCTIONAL DIAGRAM
• Meets all requirements of JEDEC Tentative
Standard No.13A, "Standard Specifications
for Oescription of "B" Series CMOS Devices"
STATIC ELECTRICAL CHARACTERISTICS
LIMITS AT INDICATED TEMPERATURES (OC)
Valuesat-55, +25, +125 Apply toD,F,H Packages
Values at -40,+25,+85 Apply to E Package
CONDITIONS
CHARACTERISTIC
Quiescent Device
Current,
IDD Max.
Output Low
(Sink) Current
10L Min.
Output High
(Source)
Current,
10H Min.
Output Voltage:
Lew-Level,
VOL Max.
Output Voltage:
High·Level,
VOH Min.
Input Low
Voltage,
VIL Max.
Input High
Voltage,
VIH Min.
1nput Current
liN Max.
50
+25
Vo
(V)
VIN
(V)
VDD
(V)
-55
-40
+85
+125
Min.
Typ.
Max.
-
0,5
5
0.25
0.25
7.5
7.5
-
0.01
0.25
-
0,10
0.5
0.5
15
15
0.01
0.5
1
30
30
0.01
5
0.64
1
5
0.61
-
150
0.42
150
0.36
0.51
0.02
1
1
5
-
1.5
1.1
0.9
1.3
2.6
-
4
2.8
-0.42
34
2.4
-0.36 -0.51
6.8
-1
-
-1.3
-1.15 -1.6
-3.2
-1.1
-2.8
-0.9
-2.4
-2.6
-6.8
-
0
0,05
0.05
0.05
-
-
0,15
10
15
-
0,20
20
0.4
0,5
5
0.5
0,10
0,15
10
1.5
4.6
2.5
9.5
13.5
-
0.5
0.5
0,10
0,15
15
5
1.6
4.2
5
-0.64 -0.61
-2
-1.8
10
15
-1.6
-4.2
-1.5
-4
0,5
5
0.05
-
0,10
0,15
10
15
0.05
0.05
-
0
-
5
4.95
10
15
4.95
9.95
14.95
9.95
14.95
0
5
10
15
-
-
0,5
0,10
0,15
0.5,4.5
-
5
1.5
1,9
-
1.5,13.5
0.5
-
3
4
-
10
15
5
1
-
10
15
0,18
18
-
1.5
-1.3
-3.4
-
3.5
3.5
7
7
11
to.1
±0.1
11
±1
±1
-
._J:A+B+C+O
14
V"
IJA
mA
K"~
1.5
3
4
±0.1
NC
CD4002B
FUNCTIONAL DIAGRAM
I.
V
V"
-
-
±1O-5
FUNCTIONAL DIAGRAM
UNITS
-
-
CD4001B
"
V
IJA
CD4025B
FUNCTIONAL DIAGRAM
CD4000B, CD4001B, CD4002B, CD4025B Types
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges:
LIMITS
CHARACTERISTIC
Supply·Voltage Range (For T A = Full Package
Temperature Range)
MIN.
MAX.
3
18
UNITS
V
MAXIMUM RATINGS. Absolute·Maximum Values:
DC SUPPLY·VOL TAGE RANGE. (V DOl
(Voltages referenced to VSS Terminal)
(NPUT VOLTAGE RANGE, ALL INPUTS
DC INPUT CURRENT, ANY ONE INPUT
POWER DISSIPATION PER PACKAGE (POl:
For TA " -40 to +60 0 C (PACKAGE TYPE El
For TA " +60 to +8S o C (PACKAGE TYPE El
I
I
INPUT VOLTAGE (VI) -
-0.5 to +20 V
-0.5
V
'0 VDD +0.5 V
±10mA
Fig. 1 -
.
.
.
..
..
Typical voltage transfer characteristics.
500 mW
Derate linearly at 12 mW/oC to 200 mW
.
.
.
..
..
SOOmW
Derate linearly at 12 mW/oC to 200 mW'
For T A = +100 to +1 25°C (PACKAGE TYPES D. F) '.
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA" FULL PACKAGE·TEMPERATURE RANGE (All Package Types)
100mW
OPERATING·TEMPERATURE RANGE (TA):
-55 to +12SoC
PACKAGE TYPES D. F. H
-40 to +8SoC
PACKAGE TYPE E
-65 to +150o C
STORAGE TEMPERATURE RANGE IT stg )
LEAD TEMPERATURE lOURING SOLDERING):
+26S0C
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max.
For TA = -55 to +100'C (PACKAGE TYPES D. F) .
DYNAMIC ELECTRICAL CHARACTERISTICS
At TA = 25'C;Input tr • tf~20ns,CL =50pF. RL =200H1.
10:1: AMBIENT TEMPERATURE (TA) -2S·C
2
"68
10
2
"68
102
2
"68
103
10"
INPUT FREQUENCY "11- kHz
TEST CONOITIONS
CHARACTER ISTIC
V OD
VOLTS
Propagation Delay Time.
5
10
15
tpHL. tPLH
5
10
15
Transition Time.
tTHL. tTLH
Input Capacitance. CI N
ALL TYPES
LIMITS
TYP.
Fig.2 - Typical power dissipation vs. frequency.
MAX,
125
60
45
100
50
40
250
120
90
200
100
80
5
7.5
Any Input
UNITS
ns
ns
pF
,
DRAIN-TO-SOURCE VOlTAGE {VDSI-V
Fig.3 - Typical output low (sink) current
characteristics.
a
5"21~
3(111
6UO)
4031
DD
VSS
*PROTECTED
ALL INPUTS ARE
BY
COSIMOS PROTECTION
NETWORK
lOGIC OIAGRAM
INVERTER AND I OF 2 GATES
7 (NUMBERS IN PARENTHESES ARE
VSS TERMINAL NUMBERS FOR SECOND GATE)
Fig.4 - Schematic and logic diagrams for CD4000B.
CRAIN-lO-SOURCE VOLTAGE {Vosl-V
Fig.5 - Minimum output low (sink)
current characteristics.
51
/------------------------------------------------------------------------------------------------CD4000B, CD4001 B, CD4002B, CD4025B Types
DRA1N-TO·SOURCE
1(8,6tI31~
I
1~.4.n)
J'
VOL,.t.GEI\Iosl-\'
2(9.15,12)
LOGIC DIAGRAM
(~"
R~
Ju "
y"
(9
*COS/MOS
ALL INPUTS ARE PROTECTED BY
PROTECTION NETWORK
IOF 4 GATES
(NUMBERS IN PARENTHESES
ARE TERMINAL NUMBERS
Fig.9 - Typical output high (source)
FOR OTHER GATES)
currBnt characteristics.
Fig.6 - Schematic and logic diagrams for CD4001B.
DRAIN-lO-SOURCE VOLTAGE IVDS)-V
2"2l~
3(11)
1(13)
4(101
5(9)
LOGIC DIAGRAM
g~
4*(10)
Fig. 10 - Minimum output high (source)
current characteristics.
*ALL INPUTS ARE PROTECTED BY
COSIMOS PROTECTION NETWORK
IOF 2 GATES (NUMBERS IN
PARENTHESES ARE TERMINAL
NUMBERS FOR SECOND GATE)
Fig.7 -
Schematic and logic diagrams for CD4002B.
''''"l~
4(~.12)
6
(9,101
!S(8,13)
LOGIC DIAGRAM
(2,121
.*
(8,131
Fig. 11 - Typical transition time vs. load
capacitance.
ROO
y .
* BYALLCOSIMOS
INPUTS ARE PROTECTED
PROTECTION
NETWORK
Fig.S -,. Schematic and logic diagrams for CD4025B.
Fig. 12 - Typical propagation delay time
VS. load capacitance.
52
CD4000B, CD4001B, CD4002B, CD4025B Types
Voo
~
v,"
'--
~i~~~:~~~~~~5
NOTE:
Fig. 13 -.: Input leakage current
test circuit.
A
,.
•
,.
,.
VOD
13
F
'0
9
K-O+E+F
S
H*A+B+C
Fig. 15 - Quiescent-device
current test circuit.
test circuit.
A
S
..lorn
,.•
TERMINAL ASSIGNMENTS (TOP VIEW)
,.
,.
VDO
13
K·m
C
'0
9
Vss
J-A+B+C+O
A
MaG+ii
L-E+F
'.
•
VDD
13
K.f+F+G+H
,.
"
NC
Vss
a
•
F
K-O+E+F
'0
9
,.
,.
NC
VDD
13
'0
VSS
L=G+H+I
.,)sA+B+C
C
9ZCS-24'147RI
Ne; NO CONNECTION
Ne= NO CONNECTION
CD4000B
,.
,.
G
D
92CS-Z-1]Q --
2-S~G~
I
,t:J-l.
---
__
z
~
-
-
-
-
CL
0
Dz+5
CL
cL
Q
CL~50pF I
___: CL : 15 pF
1 1
,
10
-------1
1-.
Ct..
D4~D
0 -~-2-;;G~----
,
."
10
.
, " ,
102
I I
I '
."
103
I
,
i
I
i
II
2
.69
10 4
CLOCK INPUT FREQUENCY (fCl)-
-4 S8
~Hl
Fig. 9 - Typical dyanamic power dissipation
as a function of clock frequency_
Cl
Ci
~
:
D3~nQ -?--;;;A~;---1J I
CL
",,0
--
.
~
CL
CL
2
0
~I038
CL
n
Jrp'"
~
,40~"~ ~V ~n'i~T1t
It.v
, = ~o·
", = ~
-i
i
~IO~
eo • -
IT. TO 14 MORE STAGES
~
.,,8=IENT TEMPE"lrrrri1'~)d;
Q
CL
~'~f fo- ~,:Il ~:,-~l
I
I
I
CL
CL
p
I
' I
92CM·29830A 1
,DETAILED LOGIC OF LATCH
n."O
I
l _________________
~
Fig. 6 - Logic diagram with detail of latch.
60 _______________________________________________________________________
CD40068 Types
INPUTS
o
Vss
100
')2:CS-2744'RI
Vss
Fig. 10- Dynamic power dissipation test
circuit.
Fig. 12 - Input voltage test circuit.
Fig. 11 - Quiescent device
current test circuit
40
50
60
70
INPUDS
VDO
VOO
NOTE·
~_
MEASURE INPUTS
SEQUENTIALLY,
TO BOTH VOO AND VSS
CONNECT ALL UNUSED
INPUTS TO EITHER
o ~
VSS
VOO OR VSS·
VSS
66-74
( 1.677-1·879)
Fig. 13 - Input current test circuit.
f - . - - - - - - - - - - - - ( " ' 2 ~~~~kII~-c;------------~
92 CM- 29744
Dimensions in paren theses are in millimeters and
are derived from the. basic inch dimensions as in·
dicated. Grid graduations are in mils (1(J3 inch).
The photographs and dimensions of each COS/MOS
chip represent a chip when it is part of the wafer.
When the wafer is cut into chips, the cleavage
angles are 57° instead of 90° with respect to the
face of the chip. Therefore, the isolated chip is
actually 7 mils (0.17 mm) larger in both dimensions.
Dimensions and pad layout for CD4006BH.
61
CD4007UB Types
COS/MOS
Dual Complementary
Pair Plus Inverter
High-Voltage Types (20-Volt Rating)
The RCA-CD4007U8 types are comprised of
three n-channel and three p-channel enhancement-type MOS transistors. The transistor
elements are accessible through the package
terminals to provide a convenient means for
Features:
tt4
• Standardized symmetrical output characteristics
• Medium Speed Operation -tpHL, tpLH = 30 ns (typ.)
at 10 V
JI~{1r"k
• 100% tested for quiescent current at 20 V
l~
• Meets all requirements of JEDEC Tentative
Standard No. 13A, "Standard Specifications
for Description of '8' Series CMOS Devices"
7
• Maximum input current of 1 I1A at 18 V
over full package-temperature range;
100 nA at 18 V and 25°C
theses indicate terminals that are connected
together to form the various configurations
listed.
The CD4007UBtypes are supplied in 14-lead
hermetic dual-in-line ceramic packages (0
and F suffixes). 14-lead dual-in-line plastic
packages (E suffix), 14-lead ceramic flat
packages (K suffix), and in chip lorm (H
suffix).
~
4
9
':I2CS- 25035
Terminal No.14 - VOO
Terminal NO.7 - VSS
constructing the various typical circuits as
shown in Fig. 2.
More complex functions are possible using
multiple packages. Numbers shown in paren-
~-Ll
1 1J
FUNCTIONAL DIAGRAM
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges:
LIMITS
CHARACTERISTIC
MIN.
Supply- Voltage Range
(For T A = Full Package
Temperature Range)
UNITS
MAX.
18
3
V
STATIC ELECTRICAL CHARACTERISTICS
Applications:
• Extremely high-input impedance amplifiers
• Shapers
• Inverters
Quiescent Deyice
Current,
IDD Max.
• Threshold detector
• Linear amplifiers
• Crystal oscillators
Output Low
(Sink) Current
IOL Min.
TERMINAL DIAGRAM
Top View
02 (P) SOURCE
Q2(P}ORAIN
Q2 GATES
Q2{N)DRAIN
QIGATES
a
SOURCE
Output High
(Source)
Current,
IOH Min.
VOO.a1602 8 Q3IP)
Ie
"
a2(NI SOURCE
VSS,QI& 02 Q3 (N)
SUSSTRATES QHNI
LIMITS AT INDICATED TEMPERATURES (OC)
Value. at -55, +25, +125 Apply to D,F,H Packages
Value. at -40, +25, +85 Apply to E Package
CONDITIONS
CHARACTERISTIC
10
SI.IBSTRATES,QI(P)ORAIN
QI(P) SOURCE
03 (N) DRAIN,Q3iP) SOURCE
Q3(P} DRAIN
03 GATES
Q3(NISOURCE
Vo
(V)
VIN VDD
(V)
(V)
-55
-40
+85
+125
Min.
+25
Typ.
Max.
-
a,s
5
0.25
0.25
7.5
7.5
-
0.01
0.25
0,10
10
0.5
0.5
15
15
0.01
0.5
-
0,15
15
1
30
150
30
-
0.01
0.02
1
5
-
0,20
20
5
1
5
150
-
0.4
a,s
5
0.64
0.61
0.42
0.36
0.51
1
-
0.5
0,10
10
1.6
1.5
1.1
0.9
1.3
2.6
-
1.5
4_6
0,15
15
2.4
34
a,s
5
2.8
-0.42
-0.36 -0.51
6.8
-1
2.5
9_5
D,S
5
-2
-1.8
-1.3
-1.15 -1.6
-3.2
-
0,10
10
-1.6
-1.5
-1.1
-0.9
-1.3
-2.6
13.5
0,15
15
-4.2
-4
-2.8
-2.4
-3.4
-6.8
4
4.2
-0.64 -0.61
-
D,S
5
0.05
-
0
0.05
-
10
15
0.05
0.05
-
a
a
0.05
-
0,10
0,15
Output Voltage:
High-Level,
VOH Min.
-
a,s
5
4.95
4.95
5
-
-
0,10
9.95
10
0,15
10
15
9.95
-
14.95
14.95
15
-
4.5
g
-
5
1
-
10
15
2
2.5
-
13.5
-
0.5
-
5
4
1
-
10
8
1.5
-
15
12.5
Input Low
Voltage,
VIL Max.
Input High
Voltage,
VIH Min.
I nput Current
liN Max.
0,18
18
±0.1
±0.1
±1
±1
0.05
-
1
-
2
-
-
4
-
2.5
-
8
-
-
12.5
-
-
-
±1O- 5
JlA
rnA
-
Output Voltage:
Lew-Level,
VOL Max.
~I{NIDRAIN
UNITS
±0.1
V
V
JlA
62--------------------------------------------------------------------
CD4007UB Types
MAXIMUM RATINGS, Absolute·Maximum Values:
DC SUPPLY·VOL TAGE RANGE. (V DD )
-0,5 to +20 V
(Voltages referenced to VSS Terminal)
INPUT VOLTAGE RANGE, ALL INPUTS
-0.5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT
±10mA
POWER DISSIPATION PER PACKAGE (POl:
For TA " -40 to +60 0 C (PACKAGE TYPE El . .
. . . . . . . ..
500 mW
Derate Linearly at 12 mW/oC to 200 mW
For T A" +60 to +85 0 C (PACKAGE TYPE El
. .
For TA " -55 to +100 0 C (PACKAGE TYPES D, F)
. . . . . . . ..
500mW
For T A" +100 to +125 0 C (PACKAGE TYPES D, Fl
Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA" FULL PACKAGE·TEMPERATURE RANGE (All Package Types)
100mW
OPERATING·TEMPERATURE RANGE (TAl:
PACKAGE TYPES 0, F, H
-55 to +12SoC
-40 to +8SoC
PACKAGE TYPE E
STORAGE TEMPERATURE RANGE (Tstgl
-65 to +1500 C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1132 inch! 1.59 ± 0.79 mm) from case for 105 max.
a) Triple Inverters
(14,2,11); (8,13);
(1,5); (7,4,9)
92CS-15~50
b) 3 ·Input NOR Gate
~~""12
10~
92CS-15349
(13,2); (1,11);
(12,5,8); (7,4,9)
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 250 C; Input t r , tf = 20 ns,
CL = 50 pF, RL = 200 Kn
CHARACTERISTIC
UNITS
VDD
Volts
Typ.
Max.
Propagation Delay Time:
tPHL,
tPLH
10
15
55
30
25
110
60
50
ns
lTHL,
lTLH
5
10
15
100
50
40
200
100
80
ns
10
15
pF
Transition Time
Input Capacitance
CIN
5
Any Input
~~"'12
c) 3·lnput NAND Gate
ALL TYPES
LIMITS
CONDITIONS
10~
(1,12,13); (2,14,11);
(4,8); (5,9)
d) Tree (Relay) Logic
OUT
12
"# ALL P- UNIT SUBSTRATES
ARE CONNECTED TO VDD
ALL N-UNIT SUBSTRATES
ARE CONNECTED TO Vss
92CS-15329
01
(13,12,5); (4,9,8);
A
(14,2); (1,11)
.+---+--OOUT
.
COS/MOS OUTPUT PROTECTION
NETWORK BETWEEN TERMINAL
NOS. 1,2,4,5,8,9,11,12,13
AND THE CORRESPONDING
DRAINS AND lOR SOURCES
~~~~~:L
01~0:
A
01· NfTO P WELL
OZ* ptro SUBSTRATE
RI= 1-5 KD
R2- IS-30n
~
B
OUT (VDD)=C ... AB
OUr (VSS)=CA+CB
:Jvss
92CM- 28632
vss
Fig. 1 - Detailed schematic diagram of CD4007UB showing input, output, and parasitic diodes.
Fig. 2 - Sample COS/MOS logic circuit arrangements
using type CD4001UB.
63
CD4007UB Types
e) High Sink-Current Driver
(6,3,10); (8.5, 12);
(11,14); 7.4,9)
(OPTIONAL Voo PUL.L-UP)
92CS-15330
INPUT \/OLTAG! IIII.I-V
9ZC!-111815
Fig. 3 - Typical vOltage-transfer characteristics
for NAND gate.
(6,3,10); (13,1,12);
(14,2,11); (7,9)
f) High Source-Current Driver
t--
1'ss
{OPTIONAL "'SSPULL-DOWN}
92CS-15327
h) Dual Bi-Directional Transmission Gating
g) High Sink - and Source-c.urrent .Driver
Voo
INPUT VOLTAGE (\Ix I-V
Fig. 4 - Typical voltage-transfer characteristics
for NOR gate.
(6,3,10); (14,2,11);
(7,4,9); 13,8,1,5,12)
Vss
92CS-t5341
(1,5,12); (2,9);
(11.4); (8,13,10);
(6,3)
92CS-15328
Fig. 2 - Sample COS/MOS logic circuit arrangements using type CD4001UB (Cont'd).
aRAIN-TO-SOURCE VOLfAGE (Vosl-V
Fig. 5 - Typical output low (sink)
current characteristics.
r8:~""'C
ii,
AMBIENT TEMPEMTlIE
15
a:
'Ta'-
2Sec
SUPPLY VI1.TAGE1"Do'-15
}12.S
~
10
i
r.'
~
10
,.
5
10
2.5
I
,
INPUT VOLTAGE IVI I-V
Fig. 6 - Minimum and maximum voltage-transfer
characteristics for inverter.
64~
1.5
10
12.5
15
INPUT VOLTAGE IVI:)-\I
ORAiN-1-o-"OU"CE VOLTAGE (VDsl-V
Ittts-UIHftl
Fig. 1 - Typical current and voltage-transfer
characteristics for inverter.
Fig. 8 - Minimum output low (sink)
current characteristics.
________________________________________________________________
CD4007UB Types
ORAIN-TO-SOURCE VOLTAGE IVOSJ-V
OD
VOO
INPU
V O ' NOTE
~
~:;~~:;I!~~~~S
TO BOTH Voo AND VSS'
CONN ECl ALI. UNUSED
EITHER
Vss
INPUTS TO
VOO OR VSS'
V55
Fig. 15 - Input current test circuit.
Fig. 9 - Typical output high (source)
current characteristics.
Fig. 13 - Typical transition time vs. load
capacitance.
:~UTO'·o_~
DRAIN-TO-SOURCE VOLTAGE IVOSI-V
NOTE:
TEST ANY ONE INPUT
VSS
WITH
~~~E~~~~TS AT
Fig. 16 - Input voltage test circuit.
o
V55
10'
1Q3
...
104
10'
10'
INPUT FREQUENCY IIi )-Hz
Fig. 10 - Minimum output high (source)
current characteristics.
100
Fig. 14 - Typical dissipation vs. frequency
characteristics.
Fig. i 7 - Quiescent device current test circuit.
r
~O
~
10
125-<:
•v
10
IS
INPUT VOI.TAG£ 1VII-V
"
Fig. 11 - Typical voltage-transfer characteristics
as a function of temperature.
DIMENSIONS AND PAD LAYOUT FOR CD4007UBH
Dimensions in parenthesfi Bf6 in millimeters and are
dsrived from the basic inch dimensions a. indicated.
Grid graduation. are in mil. (10-3 inch).
Fig. 12 - Typical propagation delay time vs.
load capacitance.
The photographs and.dimensions of each
COS/MaS chip represent a chip when it
;s part of the wafer. When the wafer is
cut into chips. the cleal/age angles are
57° instead of 90° with respect to the
face of the chip. Therefore, the isolated
chip is actually 7 mils (0. '7 mm) larger
in both dimensions.
65
CD4008B Types
COS/MOS 4-Bit Full Adder
With Parallel Carry Out
A4
High-Voltage Types (20-Volt Rating)
The RCA-CD4008B types consist of four
full adder stages with fast look ahead carry
provision from stage' to stage. Circuitry is
included to provide a fast "parallel-carry-out"
but to permit high-speed operation in arithmetic sections using several CD4008B's.
CD4008B inputs include the four sets of bits
to be added, Al to A4 and Bl to B4, in
addition to the "Carry I n" bit from a previous section. CD4008B outputs include the
four sum bits,S 1 to 54. I n addition to the
high speed "parallel·carry-out" which may be
utilized at a succeeding CD4008B section.
The CD4008B types are supplied in 16-lead
hermetic dual-in-line ceramic packages (D
and F suffixes), 16-lead dual-in-line plastic
packages (E suffix), 16-lead ceramic flat
packages (K suffix), and in chip form (H
suffix).
Features:
B3
A3
• 4 sum outputs plus parallel look-ahead carry-output
• High-speed operation - sum in-to-sum out, 160 ns typ;
carry in-to-carry out, 50 ns typo at VDD = 10 V,
Cl = 50 pF
• Standardized, symmetrical output characteristics
• 100% tested for quiescent current at 20 V
• Maximum input current of 1 IlA at 18 V
over full package-temperature range; 100
nA at 18 V and 250 C
• Noise margin (over full package temperature range):
1 Vat VOD = 5 V
2VatVOD=10V
2.5 Vat VOO = 15 V
• 5-V, 10-V, and 15-V parametric ratings
B2
A2
BI
AI
• Meets all requirements of JEOEC Tentative
Standard No. 13A, "Standard Specifications
for Description of 'B' Series CMOS Devices"
Applications:
13
"
10
Vss
9
TOP VIEW
CD4008B
TERMINAL ASSIGNMENT
*,
,,0'-t+1+4---r'"'-,
• Binary additionlarithmetic units
A2)( 5
"
(CARRY IN)
Quiescent Device
Current,
100 Max.
Output Low
(Sink} Current
IOLMin.
Output High
(Source}
Current,
IOH Min.
Output Voltage:
Low·Level,
VOL Max.
Output Voltage:
High·Level,
VOH Min.
Input Low
Voltage,
VIL Max.
Input High
Voltage,
VIH Min.
Input Current
liN Max.
Vo
(V}
-
'o'OD=16
LIMITS AT INDICATED TEMPERATURES (DC}
Values at -55,+25, +125 Apply to 0, F,H Packages
Values at -40, +25; +85 Apply to E Package
VIN VOD
(V}
(V}
-55
+85
-40
+125
Min.
+25
Typ.
0,5
5
5
5
150
150
-
0.04
5
10
20
10
20
300
600
300
600
-
0.04
0.04
10
-
10
15
20
-
0,20
20
100
100
3000
3000
-
0.08
100
0.4
0,5
5
0.64
0.61
0.42
0.36
0.51
1
-
0.5
0,10
10
1.6
1.5
1.1
0.9
1.3
2.6
-
5
5
9.5
0.5
0,5
0,10
4
4.2
-0.64 -0.61
-2
-1.8
10
-1.6
-1.5
13.5
0,15
15
-4.2
-4
-
0,5
5
0.05
-
0,10
0,15
0,5
10
15
5
0.05
0.05
-
0,10
-
0,15
0.5,4.5
1.5
4.6
2.5
1,9'
1.5,13.5
0,15
15
2.8
-0.42
-1.3
-1.1
-2.8
-
-0.36 -0.51
-1.15 -1.6
6.8
-1
-3.2
-
-0.9
-1.3
-2.6
-
-2.4
-3.4
-6.8
-
-
a
a
a
0.05
2.4
34
-
4.95
9.95
5
10
4.95
9.95
0.05
0.05
-
10
-
15
14.95
14.95
15
-
5
1.5
-
-
1.5
-
10
15
3
4
-
-
-
3
4
-
-
-
0.5,4.5
-
5
3.5
3.5
1,9
-
10
7
7
1.5,13.5
-
15
11
11
--
0,18
18
to.l
to.l
tl
tl
-
tl0- 5
V5S =8
'""ti
__
DD
vss
*" ALL INPUTS ARE
PROTECTED BY
COSI MOS PROTECTION
NETWORK
UNITS
Max.
0,10
0,15
"
SI
*7
" U".....- - - - '
STATIC ELECTRICAL CHARACTERISTICS
voo
B4
Co
54
53
52
51
CI
12
',0*"'"++t++~-r""'"
',0*"'"++I++~-L:::::J
AI
CHARACTERISTIC
I.
"
81 *6
CONOITIONS
,.
I.
92CS-27643
Fig. 1 - C040088 logic diagram.
JlA
TRUTH TABLE
rnA
Ai
Bi
Ci
Co
SUM
0
a
0
0
1
0
a
a
1
1
a
a
a
0
1
1
0
1
a
a
1
1
1
1
1
a
V
1
0
0
a
1
1
1
1
1
1
1
0
0
1
-
V
to.l
JlA
66 __________________________________________________________________
C040088 Types
RECOMMENDED OPERATING CONDITIONS at TA = 2fiDC, Except as Noted.
For maximum reliability, nominal operating conditions should be
selecred so that operation is always within the fol/owing ranges:
LIMITS
CHARACTERISTIC
MIN.
MAX.
3
18
Supply·Voltage Range (For
T A = Full Package Temp·
erature Range)
UNITS
V
LOAD CAPACITANCE {CLI- pF
MAXIMUM RATINGS, Absolute·Maximum Values:
DC SUPPL Y·VDL TAGE RANGE, (V DO)
-0.5 to +20 V
(Voltages referenced to VSS Terminal)
INPUT VOLTAGE RANGE, ALL INPUTS
-0.5 to VDD +0.5 V
±10mA
DC INPUT CURRENT, ANY ONE INPUT
POWER DISSIPATION PER PACKAGE (PDI:
For T A = -40 to +600 C (PACKAGE TYPE EI
....•... ,
500mW
Derate Linearly at 12 mW/oC to 200 mW
For TA = +60 to +85 0 C (PACKAGE TYPE EI
.
. . . . • . . .•
500mW
For TA = -55 to +1000 C (PACKAGE TYPES O,FI
Derate Linearly at 12 mW/oC to 200 mW
For T A = +100 to +125 0 C (PACKAGE TYPES 0, FI
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
100mW
FOR TA = FULL PACKAGE·TEMPERATURE RANGE (All Package Typesl
OPERATING-TEMPERATURE RANGE (TAl:
-55 to +1250 C
PACKAGE TYPES 0, F, H
-40 to +85 0 C
PACKAGE TYPE E .
-65 to +1500 C
STORAGE TEMPERATURE RANGE ITstgl
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ±0.79 mml from case for 10 s max.
Fig.3 -
Typical sum-in to sum-out propagation delay
time vs. load capacitance.
LOAD CAPACITANCE (CLI- pF
Fig.4 - Typical carry-in to carry-out propagation
delay time vs. load capacitance.
9-12{
A
99-12
50t 90+ 155
50
90
155
(el-Colt (Si-Co)+(CI-So)
LOAO CAPACITANCE (CL.I- pF
92CS-28306
} 55-8
90 + 155
(51-Co)HCi -50)0 90+ 155
Fig.5 - Typical carry-in to sum-out propagation delay
time vs. load capacitance.
(Si-So)
VSS
ALL SUMS SETrLEO AFTER 345
n.
92CS-33074
Fig.2- Typical propagation delay fora 16-bitadder (10 V operation).
LOAD CAPACITANCE {CLI- pF
Fig.6 - Typical sum·in to carry-out propagation delay
time vs. load capacitance.
_____________________________________________________________________ 67
CD4008B Types
DYNAMIC ELECTRICAL CHARACTERISTICS
At TA ~ 25'C; Input t r , tf~ 20ns, CL = 50pF, RL
CHARACTERISTIC
VDD
(V)
Propagation Delay Time:
tPHL, tPLH
Sum I n to Sum Out
Carry In to Sum Out
Sum I n to Carry Out
Carry I n to Carry Out
Transition Time:
tTHL, tTLH
Input Capacitance, CIN
DRAIN-TO~SOURCE VOLTAGE
LIMITS
ALL TYPES
TYP.
MAX.
5
10
15
400
160
115
800
320
230
5
10
15
5
10
15
5
10
15
5
10
15
370
155
115
200
90
65
100
50
40
100
50
40
5
740
310
230
400
180
130
200
100
80
200
1.00
80
7.5
-
IY!sl-V
=200kn
UNITS
ns
ns
Fig. 7 - Typical output high (source)
current characteristics.
ns
DRAIN-lO-SOURCE VOLTAGE (Vos)-V
ns
-1$
-10
AMSIENT TEMPERATURE !TA)'2,·C
.,
ns
..... ++ -IOV
pF
,.
J~E:::-fO
Fig.S -
Minimum output high (source)
current characteristics.
~
LOAD CAPACITANCE \CLlo"pF
- - - - CL o$OpF
,
,
DAAIN~TO-SOURCE
10
DRAIN-lO-SOURCE VOLTAGE (Vos)-V
VOLTAGE IVosl-V
Fig.9 - Typical output low (sink)
current characteristics.
Fig. to
-
Minimum output low (sink)
current characteristics.
INPUT
10'
lOS
10'
FREQUENCY If.) -kH,
Fig. 11 - Typical dissipation characteristics.
INPUTS
Voo
'OPUT.OOUTPUTS
'~
Voo
VOO .NOTE
INPDus
V'H
l
V~L
~
~:;~i:il~~~~~S
Vss
TO BOTH Voo AND Vss·
CONNECT ALL UNUSED
INPlITS TO EITHER
NOTE:
92CS-2144IRI
Fig. 72 -
Ou;escent;tevice~urrent
test circuit.
'Iss
1~N~"u~~OMaINATION
Fig. 13 - ''!put-voltage test c;r~uit.
68 ______________________________________________
VDO OR VSS·
Vss
Fig. 14 - Input current test circuit.
~-------------------
CD4008B Types
Dimensions in parentheses are in milli·
meters and are derived from the basic
inch dimensions as indicated.
graduations are in mils (10-3 inch).
Grid
The photographs and dimensions of each
COS/MOS chip represent a chip when it
is part of the wafer. When the wafer is
cut into chips, the cleavage angles are
57° instead of 90° with respect to the
face of the chip, Therefore. the isolated
chip is actually 7 mils (0.17 mm) larger
in both dimensions.
Dimensions and Pad Layout for CD4008BH
________~----------------------------------------69
CD4009UB, CD4010B Types
COS/MaS
Features:
Hex Buffers/Converters
• 100% tested for quiesce"t current at 20 V
• Maximum input current of 1 JlA at 18 V over full
package-temperature range: 100 nA at 18 V and 25 0 C
• 5-V, 10-V, and 15-V parametric ratings
High-Voltage Types (20-Volt Rating)
Inverting Type: CD4009UB
Non-Inverting Type: CD4010B
,.<-~-
8~H'8
Applications:
COS/MOS to DTL/TTL hex converter
COS/MOS current "sink" or "source"
driver
• COS/MOS high-to-Iow logic-level
converter
• Multiplexer - 1 to 6 or 6 to 1
The CD4049UB and CD4050B are preferred
hex buffer replacements for the CD4009UB
and CD4010B, respectively, in all applications except multiplexers. For applications
not requiring high sink current or voltage
conversion, the CD4069UB Hex Inverter is
recommended.
The CD4009UB and CD4010B types are
supplied in 16-lead hermetic dual-in-line
ceramic packages (D and F suffixes), 16lead dual-in-line plastic packages (E suffix),
16-lead ceramic flat packages (K suffix),
and in chip form (H suffix).
Vee
G:A
A
I.
•
H~B
I.
VDD
15
L=F
I.
F
13
Ne
••'!'
B
I-e
"
e
Vss
10
TOP VIEW
-
~,
-
~,,~
D~J'D
•
•
The RCA'CD4009UB and CD4010B Hex
Buffer/Converters may be used as COS/MaS
to TTL or DTL logic-level converters or
COS/MaS high-sink-current drivers.
~,~-,,--
C~"C
...•
vee
I.
J=D
9
0
IfOO~
F
VDD
L·F
F
Ne
.·E
E
"
"
c
10
V"
9
~,~
J·o
C~"C
~. ~ 'O~
92CS-244S2RI
O~J'o
Ne. NO CONNECTION
CD4010B
CD4009UB
l·F
'USS·-.t+-'
.~~
UNITS
I1A
,
.,
INPUT VOLTS IV1 1
Fig. 5 - Minimum and maximum voltage transfer
characteristics IVDD~51-CD4070B.
mA
V
Fig. 6 -Minimum and maximum voltage transfer
characteristics IVDD~701-CD40 70B.
V
4
8
INPUTVcc..TS(YI)
±0.1 ±0.1
±1
±1
-
±10-5 ±0.1
I1A
Fig. 7 - Minimum and maximum voltage transfer
characteristics IV DD~751-CD4070B.
______________________________________________________________________ 71
CD4009UB, CD4010B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA=25°C; Input tr, t,=20 ns,
CL=50pF, RL =200Kn
LIMITS
ALL PKGS
CONDITIONS
CHARACTER ISTIC
Voo
IV)
VI
IV)
VCC
IV)
UNIT
TYP.
MAX.
Propagation Delay Time:
5
5
5
70
140
10
10
10
40
80
10
10
5
35
70
15
15
15
30
60
15
15
5
30
60
5
5
5
100
200
10
10
10
50
100
10
10
5
50
100
15
15
15
35
70
15
15
5
35
70
5
5
5
30
60
10
10
10
20
40
10
10
5
15
30
15
15
15
15
30
15
15
5
10
20
5
5
5
65
130
10
10
10
35
70
10
10
5
30
70
15
15
15
25
50
15
15
5
20
40
5
5
5
150
350
10
10
10
75
150
15
15
15
55
110
Low-ta-High, tPLH
CD4009UB
CD4010B
High·ta-Low, tpHL
CD4009UB
CD4010B
Transition Time:
Low-to-High, trLH
ns
Fig. B - Typical voltage transfer characteristics
as a function of temperature-CD4010B.
ns
ns
DRAIN-TO-SOURCE VOL.TS (Vos'
ns
Fig. 9 - Typical output low (sink J
current characteristics.
AMBIENT TEMPERATURE ITA"25·C
5
5
5
35
70
10
10
10
20
40
15
15
15
15
. 30
CD4009UB
-
-
-
15
22.5
CD4010B
-
-
-
5
7.5
High-ta-Low, tTHL
ns
ns
'0
Input Capacitance, C1N
pF
'0
20
O'IAIN-TO-SOURCE VOL.TS NDSI
Fig. 10 - Minimum output low (sink)
current characteristics.
DRAIN-TO-SOURCE VOl.TAGE
(Vosl-V
9tCS-2765}
Fig. 11 - Typical output high (source)
current characteristics.
72 ________________________
Fig. 12 - Minimum output high (source)
current characteristics.
~
Fig. 13 - Typicallow-to-high propagation delay
time vs. load capacitance (CD4009UB).
___________________________________________
CD4009UB, CD4010B Types
:{p"GE,\"oO'_'!.I"
SlIPP\.."f
"o\..
10"
1-'
~ 20
0----1 )x:>--.........li.L......-_.......J
1{l3!
~
SET
oo
~
2{L2J
*ALL INPUTS ARE
PROTECTED BY
COS/MOS PROTECTION
V55
',"Sn,
CL ·50pF
NjN)oFfI/FF2 TERMINAL
ASSIGNMENTS
'" .
125'
~
r ~
;'"
~fJ
i
j
15
~
~
10
NETWORI(
92CM-27~8RI
Fig. 7 -
Logic diagram and truth table for CD40138
(one of two identical flip.flopsJ.
'0
.
15
SUPPLY \lOLTAGE (\1001-\1
20
9<'CS-2O;392R2
Fig. 8 - Typical maximum clock frequency vs.
supplV voltage.
___________________________________________________________________ 83
CD4013B Types
MAXIMUM RATINGS, Absolute-Maximum Values:
AMBIENT TEMPERATURE (TA):25:C
DC SUPPLY-VOLTAGE RANGE, (V DO)
-0.5 to +20 V
(Voltages referenced to VSS Terminal)
INPUT VOLTAGE RANGE. ALL INPUTS
-0.5 to VDD +0.5 V
DC INPUT CURRENT. ANY ONE INPUT
±lOmA
POWER DISSIPATION PER PACKAGE (PO):
0
For TA = -40 to +60 C (PACKAGE TYPE E)
. . . . . . . ..
500mW
For TA = +60 to +850 C (PACKAGE TYPE E)
.
Derate Linearly at 12 mW/oC to 200 mW
. . . . . . . ..
500 mW
For TA = -55 to +1000 C (PACKAGE TYPES D. F)
Derate Linearly at 12 mW/oC to 200 mW
For T A = +100 to +125 0 C (PACKAGE TYPES D. FI
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types)
100mW
OPERATING-TEMPERATURE RANGE (T A):
-55
to
+125 0 C
PACKAGE TYPES D. F. H . . . . .
PACKAGE TYPE E .
-40 to +85 0 C
STORAGE TEMPERATURE RANGE (Tstgl
-65 to + 150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mml from case for 10 s max.
INPUT tr =If = 20n$
~iiI02.BiI
~
~~:~~:~
LOAO CAPACITANCE
~ 10
"
INPUT FREQUENCY (i,I-Hz
Fig. 9 - Typical power dissipation
vs. frequency.
DYNAMIC ELECTRICAL CHARACTERISTICS
At TA = 2!f'C; Input t" tf= 20ns, CL = 50pF, RL = 200 kD.
TEST
CONDITIONS
LIMITS
rV DD
CHARACTERISTIC
Propagation Delay Time:
Clock to Q or Q Outputs
t pHl , tplH
Set to Q or Reset to Q tplH
-
Set to Q or Reset to Q tpHl
Transition Time tTHl· tTlH
Maximum Clock Input Frequency
Frequency # tCl
Minimum Clock Pulse Width
TEST CIRCUITS
W
MIN.
TYP.
MAX.
5
-
150
300
10
65
130
15
-
45
90
5
-
150
300
10
65
130
15
-
45
90
5
-
200
400
10
-
85
170
15
-
60
120
5
-
100
200
10
50
100
15
-
40
80
5
3.5
7
8
16
-
15
12
24
-
5
-
70
140
10
-
30
60
15
-
20
40
5
-
90
180
40
80
25
50
Minimum Data Setup Time ts
10
-
Clock Input Rise or Fall Time
10
t rCl, ttCl
Input Capacitance CIN
15
Any Input
20
40
10
20
7
15
15
-
-
-
-
4
Fig. 10 - Quiescent device current.
ns
ns
:~UTO"''"1
NOTE:
ns
ns
7.5
TEST ANY ONE INPUT,
WITH OTHER INPUTS AT
Voo OR Vss·
Fig. 11 - Input voltage.
ns
V~ ~NPu(Js
'00 :~:~U.E IN.PUrs
o ~
SEQUENTIALLY,
TO 90TH 1100 ANO IISS
CONNECT ALL UNUSED
INPUTS TO EITHER
IISS
""00 OR
""ss
Vss
/ls
1
5
Vss
ns
Vss
10
15
5
ns
MHz
Minimum Set or Reset Pulse
Width W
5
INPUTS
,
Vss
-
10
15
Voo
UNITS
(V)
Fig. 12 - Input current.
pF
#Input t r • tf = 5 ns.
84 _______________________________________________________________________
CD4013B Types
,I.
01
Oi
CLOCKI
RESET I
01
I.
""
"
'0
•
SET I
VSS
Voo
0'
0'
CLDCI( 2
RESET 2
02
5[T2
TOP VIEW
TERMINAL ASSIGNMENT
DIMENSIONS AND PAD LAYOUT FOR CD4013BH
55-63
(1.397-1.6001
54-62
".372-1.574)
92CM-
3097~
The photographs and dimensions of each COS/MOS
Dimensions in parentheses are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils f10- 3 inch).
chip represent a chip when it is part of the wafer.
When the wc:,fer is cut intoo chips, the cleavage
angles arc 57 Instead of 90 with respect to tIn.'
face of the chip. Therefore. the isolated chip is
actually 7 mils (0. 17 mm) larger in both dimensions.
______________________________________________
~
_____________________ 85
CD4014B, CD4021 B Types.
COS/MaS a-Stage
Static Shift Registers
High-Voltage Types (20-Volt Rating)
CD4014B:
Synchronous Parallel or
Serial Input/Serial Output
CD4021B:
Asynchronous Parallel Input or
Synchronous Serial Input/Serial Output
The RCA-CD4014B and CD4021 B series
types are S-stage parallel- or serial-input/serial output registers having common CLOCK
and PARAllEL/SERIAL CONTROL inputs,
a single SERIAL data input, and individual
parallel "JAM" inputs to each register stage.
Each register stage is a D-type, master-slave
flip-flop. In addition to an output from stage
S, "0" outputs are also available from stages
6 and 7. Parallel as well as serial entry is
made into the register synchronously with the
positive clock line transition in the CD4014B.
In the CD4021 B serial entry is synchronous
with the clock but parallel entry is asynchronous. In both types, entry is controlled
by the PARAllEL/SERIAL CONTROL input. When the PARAllEL/SERIAL CONTROL input is low, data is serially shifted
into the S-stage register synchronously with
the positive transition of the clock line. When
the PARAllEL/SERIAL CONTROL input
is high, data is jammed into the S-stage
register via the parallel input lines and synchronous with the positive transition of the
clock line. In the CD4021 B, the CLOCK
input of the internal stage is "forced" when
asynchronous parallel entry is made. Register
expansion using multiple packages is permitted.
The CD4014B and CD4021 B series types are
supplied in 16-lead hermetic dual-in-line
ceramic packages (0 and F suffixes), 16lead dual-in-line plastic packages (E suffix),
16-lead ceramic flat packages (K suffix). and
in chip form (H suffix).
PI·S
Q6
I. I,..
aB
PI-4
PI-3
PI-2
PI-I
v~s
45·
•
"
13
VDO
PI-7
PI-6
PI-5
12
07
"
SERIAL IN
10
CLOCK
PARALLEL/SERIAL
CONTROL
TOP VIEW
92C5-24456
TERMINAL DIAGRAM
C04014B, CD4021B
Features:
• Medium-speed operation ... 12 MHz (typ,) clock
rate at VDD-VSS =10 V
• Fully static operation
• 8 master-slave flip-flops plus output
;~:....!.
CONT
buffering and control gating
SER. II
• 100% tested for quiescent current at 20 V
, a,
'N
12 0,
• Maximum input current of 1 p.A at 18 V
ClOClC!!!
over full package-temperature range;
"
100 nA at 18 V and 250 C
• Noise margin (full package-temperature
range I = 1 Vat VOo =5 V
V55
2 Vat VDD = 10 V
2.5 Vat VDo = 15 V
CD4014B, CD4021B
• Standardized, symmetrical output characteristics
FUNCTIONAL DIAGRAM
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative
Standard No. 13A, "Standard Specifications
Applications:
for Description of 'B' Series CMOS Devices"
• Parallel input/serial output
data queueing
• Parallel to serial data conversion
• General-purpose register
,
.
RECOMMENDED OPERATING CONDITIONS AT TA = 250 C, Unless Otherwise Specified
For maximum reliability, nominal operating conditions should be selected so that operation
is always within the following ranges.
liMITS
CHARACTERISTIC
UNITS
VoD
(VI
Min.
Supply·Voltage Range (T A = Full
Package-Temperature Rangel
-
3
IS
5
10
15
ISO
SO
50
-
Clock Pulse Width, tw
-
3
6
S.5
15
15
15
Oock Frequency, fCl
Clock Rise and Fall Time,
trCl, tfCl
5
10
15
5
10
15
-
-
Max.
-
V
ns
MHz
IlS
Set·up Time, ts:
Serial Input
(ref. to ClI
5
10
15
120
SO
60
Parallel Inputs
C04014B
(ref. to ClI
5
10
15
SO
50
40
Parallel Inputs
C04021B
(ref. to P/SI
5
10
15
5
10
15
Parallel/Serial Pulse Width,
tw (CD4021 B)
5
10
15
50
30
20
.lS0
SO
60
160
SO
50
Parallel/Serial Removal Time,
tREM (CD4021 B)
5
10
15
2S0
140
100
Parallel/Serial Control
CD4014B
(ref. to ClI
-
ns
-
ns
-
ns
-
-
-
ns
ns
-
ns
86 __________________________________________________________________
CD4014B, CD4021 B Types
TRUTH TABLE - CD4014B
ER. PAA SER
'N CONTROL.
eL
./
./
./
./
../
../
[S
3
08
1.1 PI·n
,
0
1
X
X
x
x
x
00
NAL.I
,
,
,
,
x
0,
UNTER·
0
,
0
0
0
0
,
,
0
,
1
1
1
0
x x
0
an"
0
X
X
1
On"
X
X
0,
00
0
0
Ne
X" DON'T CARE CASE
NC : NO CHANGE
ps--+----~-'
VD
~
_____
* ALL
INPUTS ARE PROTECTED
BY COS/MQS PROTECTION
eL
92CM-28673RI
NETWORK.
Vss
Fig. 7 - Logic diagram for CD40748.
TRUTH TABLE - CD4021B
CL
n
rJ-
o
.
08
Q
;-4- i.:~' ' ' N-PU~TI-S-A-R-E-P-RO-T-Ee-T-E-O- '
Parallel!
Serial
Control
Q,
PI-'
PI·n
!Internal)
rr
'-
an
On-1
On,l
0,
00
NC
X" DON'T CARE CASE
eL
B'1 COS/Mas PROTECTION
Vss
Serial
Input
92CM-28674RI
NETWORK.
Fig. 2 - Logic diagram for CD40218.
______________________________________________________________ 87
CD4014B, CD4021 B Types
. MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE. (VDDI
-0.5 to +20 V
(Voltages referenced to VSS Terminal)
-0.5 to VDD +0.5 V
INPUT VOLTAGE RANGE. ALL INPUTS
±10mA
DC INPUT CURRENT. ANY ONE INPUT
POWER DISSIPATION PER PACKAGE (PDI:
. . . . . . . ..
sOOmW
For TA • -40 to +60 0 C (PACKAGE TYPE EI
Derate Linearly at 12 mW/oC to 200 mW
For TA • +60 to +85 0 C (PACKAGE TYPE EI
.
. . . . . . . ..
500mW
For TA -55 to +1000 C (PACKAGE TYPES D.FI
Derate Linearly at 12 mW/oC to 200 mW
For TAo +100 to +125 0 C (PACKAGE TYPES D. F I
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
100mW
FOR TA FULL PACKAGE·TEMPERATURE RANGE (All Package Typesl
OPERATING·TEMPERATURE RANGE IT AI:
-55 to +12soC
PACKAGE TYPES D. F. H
-40 to +8soC
PACKAGE TYPE E
-65 to +1500 C
STORAGE TEMPERATURE RANGE (Tstgl
LEAD TEMPERATURE (DURING SOLDERINGI:
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for lOs max.
0
0
DRAIN-TO-SOURCE VOLTAGE IVos!-\!
Fig. 3 - Typical output low (sink) current
characteristics.
STATIC ELECTRICAL CHARACTERISTICS
U
LIMITS AT INDICATED TEMPERATURES (oC)
CHARACTERISTIC
CONDITIONS
Vo
(V)
-
Quiescent
Device
Current,
100 Max.
Output Low
(Sink) Current
IOL Min.
Output High
(Source)
Current,
IOH Min.
Output Voltage:
Low·Level.
VOL Max.
Output
Voltage:
High-Level.
VOH Min.
Input Low
Voltage
VIL Max.
Input High
Voltage.
VIHMin.
Input Current
liN Max.
N
I
T
S
Values at -55. +25, +125 Apply to D.F.H Packages
Values at -40. +25. +85 Apply to E Package
+25
VIN VDD
(V)
(V) -55
+85
-40
+125
Typ.
Min.
Max.
0.04
600
-
3000
3000
-
0.61
0.42
0.36
0.51
1
1.6
1.5
1.1
0.9
1.3
2.6
4.2
4
2.B
2.4
3.4
6.B
":'0.42 -0.36 -0.51
-1.3 -1.15 -1.6
-3.2
150
150
10
300
300
20
600
100
0.64
10
15
0,5
5
5
-
0,10
10
10
-
0,15
15
20
-
0,20
20
100
0.4
0,5
5
0.5
0,10
1.5
0,15
5
4.6
0.5
5 -0.64 -0:61
2.5
0.5
5
-2
-1.B
0.04
10 jlA
0.04
20
O.OB
100
-1
-
9.5
0,10
10
-1.6
-1.5
-1.1
_0.9
-1.3
-2.6
0,15
15
-4.2
-4
-2.B
-2.4
-3.4
-6.B
-
0.5
5
0.05
-
0 0.05
-
0.10
10
0.05
-
0 0.05
-
0.15
15
0.05
-
0 0.05
-
0,5
5
4.95
4.95
5
-
-
0.10
10
9.95
9.95
10
-
-
14.95
0.15
15
14.95
15
-
-
5
1.5
-
-
1.5
1.9
-
10
3
-
-
3
1.5.13.5
-
15
4
-
-
4
0.5,4.5
-
5
3.5
1.9
1.5.13.5
-
10
7
7
-
-
15
11
11
-
O,lB
lB
-
±0.1
±0.1
±1
±1
-
DRAIN-TO-SOURCE
VOLTAGE.IVosl-v
V
Fig. 5 - Typical output high (source) current
characteristics.
DRAIN-lO-SOURCE VOlTAGE (VDSI-V
0.5,4.5
-
Fig. 4 - Minimum output low (sink) current
characteristics.
mft
13.5
3.5
D••"'-TCl-SOURCE VOLTAGE (V05I-V
5
V
-
±10- 5 ±0.1 jlA
Fig. 6 - Minimum output high (source) current
characteristics,
88 __________________________________________________________________
CD4014B, CD4021 B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA=25 0 C, Input t r ,tt=20 ns,
. CL =50 pF, RL =200 Kn
TEST
CONDITIONS
CHARACTERISTIC
Propagation Delay Time,
tpLH, tpHL
Transition Time,
tTHL, tTLH
VDD
(V)
5
10
15
5
10
15
LIMITS
UNITS
Min.
Typ.
Max.
160
80
60
320
160
120
ns
200
100
80
ns
-
100
50
40
-
-
Maximum Clock Input
Frequency, fCl
5
10
15
3
6
8.5
6
12
17
-
MHz
Minimum Clock Pulse
Width, tw
5
10
15
90
40
25
180
80
50
ns
Clock Rise and Fall Time,
trCl, tfCl *
5
10
15
-
-
-
15
15
15
J.i.s
Minimum Set-up Time. ts:
Serial Input
(ref. to CL)
5
10
15
-
60
40
30
120
80
60
ns
Parallel Inputs
CD4014B
(ref. to Cll
5
10
15
-
40
25
20
80
50
40
ns
Parallel Inputs
CD4021 B
(ref. to PIS)
5
10
15
-
25
15
10
50
30
20
ns
Parallel/Serial Umtrol
CD4014B
(ref. to Cl)
5
10
15
90
40
30
180
80
60
ns
-
0
0
0
ns
80
40
25
160
80
50
ns
140
70
50
280
140
100
ns
5
7.5
pF
Minimum Hold Time, tH:
Serial In, Parallel In,
Parallel/Serial Control
5
10
15
Minimum PIS Pulse Width,
5
10
15
tWH
(CD4021B)
Minimum PIS Removal Time,
tREM
CD4021 B (ref. to CL)
Average Input Capacitance. CI
5
10
15
Any Input
-
-
-
-
'ZCS-MS22
Fig. 1 - Typical transition time as a function of
load capacitance.
92.CS-29869
Fig. 8 - Typical propagation delay time as a
function of load capacitance.
Z
"811 10 '2
4 6810'2 '2
"68'032
"68,042
4 6 8 105
CLOCK INPUT FREQUENCY !teLl-kHz
,
SlCS-l98TI
Fig. 9 - Typical dynamic power dissipation
asa function of clock input frequency.
* If more than one unit is cascaded trCL should be made less than or equal to the sum of the transition
time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load.
SER. DATA
(1/4 fell
nf-------'
92C5-29871
Fig. 10 - Dynamic power dissipation test circuit.
________________________________________________________________ 89
CD4014B, CD4021 B Types
INPUTS
INPUTQVOO
OUTPUTS
Vss
'--
~
~
MEASURE INPUTS
• ---..y-
:t
Y~L.
1 N P U Voo
O S NOTE'
YDO
V,H
SEOUENTIALLY.
Vss
TO BOTH Voo AND Vss'
CONNECT ALL UNUSED
INPUTS TO EITHER
Voo OR VSS'
NOTE:
Vss
v..
~srN~~;~OMB'NATIC:W
VSS
Fig. 11 - Quiescent device
Fig. 13 - Input current test circuit.
Fig. 12 - Input voltage test circuit.
current test circuit.
80-88
(2.032-2.235)
I
f4---------=:,k~~957":14"")--------...;..~
The photographs and'dimensions of each COS/MOS
chip represent a chip when it is part of the wafer.
When the wafer is cut into chips, the cleavage angles
are 5;0 instead of 90D with respect to the face of
Dimensions and pad
la yout for CD40 14 BH
(CD4021 BH is identical)
92CM-2987Q
the chip. Therefore, the isolated chip is actually
Dimensions in parentheses are in millimeters and are
derived from the basic inch dimensions as indicated.
7 mils (0.17 mm) larger in both dimensions.
Grid graduations are. in mils (10- 3 inch).
90 ________________________________________________________________
CD4015B Types
,.
COS/MaS Dual 4-Stage
Static Shift Register Features:
VDD
OATA A
With Serial Input/Parallel Output
High-Voltage Types (20-Volt Rating)
The RCA-CD4015B consists of tINO identical,
independent, 4·stage serial·input/parallel·
output registers. Each register has indepen·
dent CLOCK and RESET inputs as well as
a single serial DATA input. "0" outputs are
available from each of the four stages on
both registers. All register stages are D-type,
master·slave flip·flops. The logic level present at the DATA input is transferred into
the first register stage and shifted over one
stage at each positive·going clock transition.
Resetting of all stages is accomplished by a
high level on the reset line. Register expansion to 8 stages using one CD4015B package,
or to more than 8 stages using additional
CD4015B's is possible.
The CD4015B-series types are supplied in
16-lead hermetic dual-in-line ceramic packages (0 and F suffixes), 16-lead dual-in-line
plastic package (E suffix), 16-lead ceramic
flat package (K suffix), and in chip form (H
suffix).
CLOCKA
• Medium speed operation ............ .
12 MHz (typ.) clock rate at VDD - Vss = 10 V
• Fully static operation
• 8 master-slave flip-flops plus input and output buffering
• 100% tested for quiescent current at 20 V
• 5-V, 10-V, and 15-V parametric ratings
• Standardized, symmetrical output characteristics
D'A
'0
D4A
DATAS
D"
CLOCK a
RESETs
·12
D'B
4
STAGE
D'B
D4B
• Maximum input current of 11lA at 18 V
over full package-temperature range;
100 nA at 18 V and 25°C
• Noise margin (full package-temperature
range) =
1VatVDD=5V
2 V at VDD = 10 V
2.5 Vat VDD = 15 V
Vss
CD4015B
FUNCTIONAL DIAGRAM
TERMINAL DIAGRAM
• Meets all requirements of JEDEC Tentative
Standard No. 13A, "Standard Specifications
for Description of 'B' Series CMOS Devices"
CLOCK B
04 B
03.
I.
2
3
oz.
Applications:
01.
RESET A
• Serial-input/parallel-output data queueing
• Serial to parallel data conversion
• General-purpose register
DATA A
Vss
I.
10
14
13
12
"
10
9
VDD
DATA B
RESET B
01.
02 B
03B
04'
CLOCK A
92CS·24457
CL
0
fo
f'
",,-X
*
RESETA
D'A
D'A
4
STAGE
a, ao
0
0".,
a.,
a,
Qn (NO CHANGEI
0
ALL INPUTS PROTECTED BY COSIMOS INPUT
PROTECTION NETWORK
'2CM~29383A2
x • OON'T CARE
CASE
Fig. 1 - Logic diagram (7 register).
________________________________________________________________________ 91
CD4015B Types
MAXIMUM
RATIN~S.
Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE.IVODI
-·0.5 to +20 V
(Voltages refer~nced 10 VSS Terminall
-0.5 to V DD +0.5 V
INPUT VOLTAGE RANGE. ALL INPUTS
±10mA
DC INPUT CURRENT. ANY ONE INPUT
POWER DISSIPATION PiR PACKAGE IPDI:
. . . . . . . ..
500mW
For T A = -40 10 +600 C (PACKAGE TYPE EI
Derate linearly at 12 mW/oC to 200 mW
For T A = +60 10 +85 ~ (PACKAGE TYPE EI. .
..
. . . . . .;
500mW
(PACKAGE TYPES O. FI
For T A = -55 to +100
Derale LInearly al 12 mWI C to 200 mW
For TA = +looto +125 C (PACKAGE TYPES D. FI
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
100mW
FOR T A = FULL PACKAGE-TEMPERATURE RANGE IAII Package Type,I
OPERATING-TEMPERATURE RANGE IT AI:
-5510 +l25°C
PACKAGE TYPES D. F. H
-40 to +85°C
PACKAGE TYPE E
-65 to +1500 C
STORAGE TEMPERATURE RANGE (Tugl
. . . . . . . "
LEtD TEMPERATURE (DURING SOLDERINGI:
. +265°C
rt distance 1/16 ± 1/32 inch 11.59 ± 0.79 mml from case for 10 s max.
!?
,
DRA.LN-TO-SOURCE VOLTAGE (Vosl-V
Fig. 2 - Typical output low (sink) current
characteristics.
RECOMMENDED OPERATING CONDITIONS at T A =250 C. Except as Noted. For maximum
reliability. nominal operating conditions should be selected so that operation is always within the
following ranges:
CHARACTERISTIC
VDD
(V)
liMITS
Min.
Supply-Voltage Range (For T A = Full PackageTemperature Range)
Clock Pulse Width.
Clock Rise and Fall Time.
tWCl
trCl. tfCl
3
5
10
15
5
10
15
180
80
50
-
18
V
-
-
ns
-
DRAIN-l'O-"OURCE VCl.TAGE
Fig. 3 - Minimum output low (sink) current
characteristics.
15
IlS
3
6
8.5
MHz
-
ns
DRAIN-lO-SOURCE VOLTAGE {Vos)-V
-
Clock Input Frequency.
fCl
5
10
15
Data Setup Time.
tsu
5
10
15
70
40
30
tWR
5
10
15
200
80
60
Reset Pulse Width.
UNITS
Max.
DC
...
.2CS-UsaOJll
Fig. 4 - Typicaloutput.high (source) current
characteristics.
DRAIN-lO-SOURCE VOLTAGE lVoSI-V
00
LOAD CAPACITANCE (CLI-pF
Fig. 5 - Minimum output high (source} curreht
characteristics.
92
Fig. 6 - Typical transition time as a function of
load capacitance.
00
IDO .
92Cs-2UT5
Fig. 7 - Typical propagation delay time a. a
tion of loadcapacitance.
func-
CD40158 Types
STATIC ELECTRICAL CHARACTERISTICS
CHARACTER·
ISTIC
Vo
(V!
Quiescent Device
Current,
IDO Max.
-
Output low
(Sink! Current
IOlMin.
0.4
0.5
1.5
4.6
2.5
9.5
13.5
Output High
(Source!
Current,
IOH Min.
Output Voltage:
Low·level,
VOL Max.
Output Voltage:
High·level,
VOH Min.
Input low
Voltage,
Vil Max.
Input High
Voltage,
VIH Min.
Input Current
liN Max.
LIMITS AT INDICATED TEMPERATURES (OC!
Values at -55, +25, +125 Apply to D,K,F ,H Packages
Values at -40, +25; +85 Apply to E Package
UNITS
+25
VIN VDD
+85
Typ.
Max.
+125 Min.
(V!
(V! -55 -40
150
5
5
150
0.04
5
5
0,5
300
0.04
10
10
300
10
0,10 10
Jl.A
20
600
20
0.04
20
0,15 15
600
O.OB
100
3000
20
100
3000
100
0,20
-
CONDITIONS
0,5,4.5
1,9
1.5,13.5
0.5,4.5
1,9
1.5,13.5
-
0,5
0,10
0,15
0,5
a,s
0,10
0.15
5
10
15
5
5
10
15
0.64
1.6
4.2
-0.64
-2
-1.6
-4.2
0.42
0.61
1.5
1.1
4
2.B
-0.61 -0.42
-1.B
-1.3
-1.5
-1.1
-4
-2.B
0,5
5
0,10
0,15
0,5
0,10
0,15
10
15
5
10
15
0.05
0.05
0.05
4.95
9.95
14.95
-
5
10
15
5
10
15
1.5
3
4
3.5
7
11
O,lB
18
-
-
±0.1
±0.1
±1
0.36
0.9
2.4
-0.36
-1.15
-0.9
-2.4
±1
-
0.51
1.3
34
-0.51
-1.6
-1.3
-3.4
1
2.6
6.8
-1
-3.2
-2.6
-6.B
-
a
0.05
0
0.05
0.05
4.95
9.95
14.95
5
10
15
a
-
-
3.5
7
-
11
-
-
-
-
-
-
rnA
V
1.5
3
4
V
-
-
±10- 5
±0.1
}J.A
Dimensions in pafen theses are in millimeters and
are derived from the basic inch dimensions as in85
2.159)
dicated. Grid graduations are in mils 00-3 inchJ.
The photographs and dimensions of each COS/MOS
chip represent a chip when it is part of the wafer.
When the wafer is cut into chips, the cleavage
angles are 57° instead of 90° with respect to the
face of the chip. Therefore, the isolated chip is
actually 7 mUs (0. 17 fflf!1) larger in both dimensions.
1--------(2.:~:~~16) -----------<--1
92CM-29678
Photograph of Chip Layout for CD40158.
___________________________________________________________________ 93
CD4015B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 2!f>C, Input t r , tf= 20ns, CL =50pF,
RL =200kn
TEST CONDITIONS
CHARACTERISTIC
VDD(V)
LIMITS
UNITS
Min. Typ. Max.
CLOCKED OPERATION
Propagation Delay Time;
TpHL, TplH
5
10
15
Transition Time;
tTHl' tTlH
5
10
15
Minimum Clock Pulse Width,
Clock Rise & Fall Time;
5
10
15
tWCl
5
10
15
trCL, tfCl'
Minimum Data Setup Time,
5
10
15
tsu
5
10
15
Maximum Clock Input Frequency, fCl
Input Capacitance, CI N
-
-.
-
Any Input
160 320
80 160
60 120
100 200
50 100
40 80
ns
90 180
40 80
25 50
- 15
15
15
2 " SiD 2
35
20
15
70
40
30
3
6
8.5
6
12
-
-
MHz
17
-
5
7.5
pF
Minimum Reset Pulse Width
tWR
-
5
10
15
5
10
15
"
1042
.. 6
92CS-29616
ILS
ns
DATAC
TpHl,
.. 68'032
Fig. 8 - Typical power dissipation as a function
of frequency.
RESET OPERATION
Propagation Delay Time,
.. "IOZ2
INPUT CLOCK FREQUENCY IfCLI- kHE
200 400
100 200
80 160
f~n
)
92ts-2ge?7
ns
100 200
40 80
30 60
Fig. 9 - Power dissipation test circuit.
* If more than one unit is cascaded trCL should be made less than or equal to the sum of the transition
time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load.
Voo
INPUTS
o
V55
'NPUTOVOO
OUTPUTS
V'H
~
'-
l
V~L
V~NP(JUT" ::::.._
o ~
SEQUENTIAUY,
TO 10TH YoD AND Yss.
CONNECT ALL UNUSED
INtUTS 10 EITHER
Voo QRVss ·
Vss
V'S
V55
NOTE:
TEST ANY CCIMBINATION
OF INPUTS
t2CS-2744IRI
Fig. 10 - Quiescent device current test
circuit.
Fig. 17 - Input voltage test circuit.
.
V55
Fig. 12 -Inputcurrent test circuit.
94 _____________________________________________________________________
CD4016B Types
COS/MOS Quad
Bilateral Switch
For Transmission or Multiplexing
of Analog or Digital Signals
Terminal Assignment
SIG A
IN
OUT
$IG
BO~~
,.
2
3
TOP VIEW
The RCA-CD4016B Series types are quad
bilateral switches intended for the transmission or multiplexing of analog or digital
signals. Each of the four independent bilateral switches has a single control signal
input which simultaneously biases both the
p and n device in a given switch on or off.
The CD4016 "S" Series types are supplied in
14-lead hermetic dual-in-line ceramic packages (D and F suffixes), 14-lead dual-in-line
plastic packages (E suffix), 14-lead ceramic
flat packages (K suffix), and in chip form (H
suffix).
Features:
I ,---,------",.
SU, A
CONTROL A
CONTROL 0
'N
OUT SIG 0
•
Vss
IN/OUT
VOO
"12
,."
CONTROL B
CONTROL C
High-Voltage Types (20-Volt Rating)
,.
OUT
'N
SIG C
92CS-244~8
Voo
CONTROL
vc·O<....'Wv........-l
Functional Diagram
Schematic diagram - 1 of 4 identical sections.
RECOMMENDED OPERATING CONDITIONS
For maximum reliability. nominal operating conditions should be selected so that
operation is always within the following range:
• 2O-Vdigital or ± 10-V peak-to-peak switching
LIMITS
UNITS
• 280-n typical on-state resistance for lS-V operation
CHARACTERISTIC
Min.
Max.
• Switch on-state resistance matched to within 10 n
typo over lS-V signal-input range
Supply Voltage Range (For T A = Full Package
18
V
3
• High on/off output-voltage ratio:
Temperature Range)
6SdBtyp.@fis=10kHz.RL=10kn
• High degree of linearity: <0.5% distortion
MAXIMUM ~ATINGS, Absolute·Maximum Values:
typo @fis = 1 kHz. Vis = S VPOp.
DC SUPPLY·VOLTAGE RANGE. IVDDI
VDO-VSS ;;>10 V. RL = 10 kn
-O.S to +20 V
(Voltages refer~nced to VSS Termlnall
• Extremely low off-state switch leakage
·0.5 to V DO +0.5 V
INPUT VOLTAGE RANGE. ALL INPUTS
resulting in very low offset current and
±10mA
DC INPUrCURRENT. ANY ONE INPUT IINCLUDING TRANSMISSION GATEI
high effective off-state resistance:
POWER DISSIPATION PoER PACKAGE (POl:
.
..
.
.
SOO
mW
100 pA typo @ VDD-VSS=18 V, TA=2So C·
For T A = -40 to +600 C (PACKAGE TYPE EI
Derate Linearly at 12 mW;oC to 200 mW
For T A = +60 to +8S ~ (PACKAGE TYPE EI
.
• Extremely high control input impedance
500mW
For TA = -55 to +100 C IPACKAGE TYPES D. FI
(control circuit isolated from signal circuit:
Derate Linearly at 12 mWI °C to 200 mW
For TA = +100 to +125°C IPACKAGE TYPES D. FI
1012 n typo
DEVICE DISSIPATION PER TRANSMISSION GATE
• Low crosstalk between switches:
100mW
FOR TA = FULL PACKAGE·TEMPERATURE RANGE (All Package Typesl
-SO dB typ_ @fis = 0.9 MHz, R L = 1 kn
OPERATING·TEMPERATURE RANGE IT AI:
-55 to + 12SoC
• Matched control-input to signal-output
PACKAGE TYPES D. F. H
-40 to +8S:C
capacitance :
PACKAGE TYPE E
-65 to +IS0 C
Reduces output signal transients
STORAGE TEMPERATURE RANGE IT" I
.
LEAD TEMPERATURE lOURING SOLD~RINGI:
• Frequency response. switch on = 40 MHz
+26SoC
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max.
(typ.)
• 100% tested for quiescent current at 20 V
• Maximum control input current of 1 /lA
at 18 V over full package temperature
range; 100 nA at 18 V at 250 C
• S-V. 10-V. and lS-V parametric ratings
App/ications:
• Analog signal switching/multiplexing
Signal gating
• Modulator
Squelch control
• Demodulator
Chopper
• Commutating switch
• Digital signal switching/multiplexing
• COS/MOS logic implementation
• Analog-tlHligital & digital-toanalog conversion
• Digital control of frequency. impedance.
phase. and analog-signal gain
,
INPUT SIGNAL VOLTS IVIS)
Fig. 1- Typ. on·state characteristics for 1 of 4
switches with VOO=+15 V, VSS=OIl.
INPUT SIGNAL VOLTS
""s.
,
92CS·27M1
Fig. 2- Typ. on-state characteristics for 1 of 4
switches with VOO=+10 V, VSS=O v.
________________________________________________________________________ 95
CD4016B Types
ELECTRICAL CHARACTERISTICS
Characteristic
LIMITS AT INDICATED
TEMPERATURE (oC)
Values at -55, +25, +125 Apply
to 0, F, H Packages
Values at -40, +25, +85 Apply to
E Package
Test Conditions
U
N
I
T
S
+25
VIN VOO
(V) (V) -55 -40 +85 +125 Typ. Max.
0,5
5
0.25 0.25 7.5 7.5 om 0.25
0,10 10
0.5 0.5
15
15 om
0.5
/loA
0,15 15
1
1 30
30 0.01
1
0,20 20
5
5 150 150 0.02
5
Quiescent Device
Current, I DO
INPUT StoNAL VOLTS IVISI
Fig. 3- Typ. on·state characteristics for 1 of 4
switches with VDO = +5 V, VSS = 0 v.
Signal Inputs (Vis) and Output (Vos)
On·State
Resistance, ron
Max.
VC=VOO
Vis=VOO or VSS
RL = 10kH
Returned Vis-4.75 to .5.75 V
to
VOO-VSS Vis=VOO or VSS
2
Vis=7.25 to 7.75 V
t.On·State
Resistance
Rl=10kH, VC=VOO
8etween Any
2 Switches, t.r on
Total Harmonic
Distortion,
THO
-3dB Cutoff
Frequency
(Switch on)
-5OdB Feed·
through
Frequency
(Switch off)
660
2000
15
360
370 520 600
-
15
775
790 1080 1230 -
5
-
-
600
-
400 n
850
-
15
-
-
-
-
-
10
-
-
-
-
5
-
h
15
-
-
-
-
0.4
-
%
VC- VOO=5V, VSS=-5V,
Vis(p.P) =5V (Sine wave
centered on 0 V) Rl=lkn,
-
-
-
-
40
-
~Hz
VC=VSS= -5V, ViS(p,pf5V
(Sine wave centered on V)
Rl =1 Ikn
-
-
-
-
1.25
-
~Hz
±1
±1
10-4 ±0.1 /loA
VC=VOO = 5 V, VSS= -5V, Vis(P'P)
= 5 V (Sine wave centered on 0 V)
RL =10 kn, fis= 1 kHz sine wave
-50 dB
Crosstalk
Frequency
VC(A)=VOO=+5V,
VC(B)=VSS=-5V,
Vis(A) = 5 V p.p '
!'iOn source
Rl = 1 kn
Propagation
Delay (Signal
I nput to Signal
Output) tpd
RL'" 200 kn
Vc = VlRff VSS= GNO.
CL =5 p
Vis = 10 V (Square
wave centered on 5 V
t r , tf = 20 ns
Output. COS
Feedthrough,
Cios
-
-
10
10
VC=OV
Input/Output
leakage Current Vis = 18V, Vos= OV;
(Switch off)
Vis=OV,
lis Max.
Vos= 18V
Capacitance:
Input. Cis
610 840 960
10 1870 1900 12380 2600
VOO = +5V
VC= VSS=-6V
18
±0.1 ±0.1
INPUT SIGNAL. VOLTS l\'isl
Fig. 4- Typ. on·state characteristics for 1 of 4
switches with VDO =+7.5 V, Vss=-7.5 V.
INPUT SIGNAL VOLTS (VIS)
Fig. 5- Typ. on·state characteristics for 1 of 4
switch.swith VDD =+5V, VSS --5V.
-
-
-
-
0.9
-
-
-
100
15
-
-
40
10
-
5
-
-
-
-
-
MHz
SUPPlY VOLTS: "DD- + 2.sV.Vss. -2.SY
AMBIENT T£~ATURE (Tala 25·C
~2
-
-
20
40 ns
15
30
4
4
0.2
-
i
I
L
i-,
X·
-,
-3
pF
Fig.
-2
V~~~
. ..
..
o
I
2.
3
INPUT 8IGHAL VOLTS tv.a)
6- Typ.
on·stat. Characteristics for 1 of 4
switches with VDD -+2.5 V, VSS=-2.5 V.
,
96 ________~/----------------------------------------------------
CD4016B Types
ELECTRICAL CHARACTERISTICS (cont'd)
LIMITS AT INDICATED
TEMPERATURE (oC)
Characteristic
U
N
Test Conditions
T
S
Control (V C)
lIisl< lOIlA
Control Input
Low Voltage,
VILe (Max.)
"'PUT 'IGIIAL VOLTS ('11,1
Vis = Vss, Vas = VDO
and
Vis = VOO. Vas = VSS
Control Input
High Voltage.
VIHC
5,10,
090904
15
.
.
.
See Fig. 1
04
.
5
3.5 (Min.)
10
7 (Min.)
15
11 (Min.)
0.7
V
SUf>Pl.Y VOLTS: Vco·.5, VsS·-5
V
Vis';; VOO
VOO-VSS=18V
VCC';; VOO - VSS
18
Crosstalk (Can,
trol I nput to
Signal Output)
Vc = 10 V (Sq. Wave)
t r • tf = 20 ns
RL = 10 kfl.
10
50
Turn·On
Propagation
Oelay
t r • tf = 20 ns
CL = 50 pF
RL = 1 kfl.
5
35
70
10
20
40 ns
15
15
30
Maximum
Control Input
Repetition Rate
Vis = VOD. VSS = GNO.
RL = 1 kfl. to gnd.
CL = 50 pF.
Vc = 10 V(Square
wave centered on 5 V)
t r • tf = 20 ns.
Vas = y, Vos@l kHz
10
10
±1
±10-5 ±0.1
p.A
Switch Input
.3"
i
~
,of-H+tt+-v.
I
-40°C
25°C*
25°Cl-
+85°C
+125°C
'to:s 2
•
~4
Fig. 8 - Typ. feedthru vs. frequency - switch
off.
MHz
7.5 jJ.F
Min.
2 OF" SWITCHES
0-'
Max.
0
5
0.25
-0.25
0.2
-0.2
0.2
-0.2
0.16
-0.16
0.12
-0.12
0.14
-0.14
4.6
10
10
0
10
0.62
-0.62
0.5
-0.5
0.5
-0.5
0.4
-0.4'
0.3
-0.3
0.35
-0.35
9.5
-
15
15
0
15
1.8
-l.S
1.4
-1.4
1.5
-1.5
1.2
-1.2
1
-1
1.1
-
1.5
-1.1
10 2 .. '.1022 "
INPUT SIGNAL fREQUENCY (II,) kHz
Switch Output
Vas (V)
lis (mA)
.6.
CI05t~lIIfU11EI'O'pI'
10_,2
5
5
* Plastic package
lC».DCAPACITANCE ICL!·CFIXTURE.CMETER°2.3.2.5·4:8pF
FlXTURE AND METER NULLED OUT
~
mV
5
Vis
(V) _55°C
!
~
Input
CapaCitance.
CIN
VDD
(V)
~NJ:c:.-G:tT~o\i~i~,~).5 Vp-p SINE WAVE (1.71 RMSI
3
~
Input Current.
liN (Max.)
0.1 ±0.1 ±1
Fig. 7':"" Typ. on-state characteristics asa function of
temp. for 1 of4switches with VDD=+S V.
VSS=-SV.
0.4
I
10
1032 .. "0"
102
INPUT SIGNAL FREQUENCY 1',.1- kHz
Fig. 9- Typical crosstalk between switch
circuits in the same package.
0.5
13.5
-
SUPPLY VOLTS: Vuo-"', YSS·-5
INPUTSIGNALYOLTSCYi.I·5Yp-p
C,os'O""
r--il---,
! 1......!
CO::::A~~~:;~5
.lOAD CJ,PACITANCE-CCFIX.·CMETER)- ~ft
u .... ••••'
Ceramic package
..,.
N
i
~
I
I I II
I
I
2J:-- LOAD RESISTANCE (RLI-IMa.
01
I
UtMS
~1~'
II
CL-
~~
_I.
.J
-'dB
~,.
"i!
:~~ro:I.~AOIO
OR fQUI:
T '\..T-+-
VC""uD
M
• ,. VO"METE::'I
,1. '°1°'1" ~]
.~
~~
~~
~,
.
,
I II NI
., "
"
00
INPUT SIGNAL FREQUENCY It••, MHZ
. Fig. 10- Determination of ron as a test condition for control input
high voltage (VIHd specification.
Fig. 11 - Typical frequency response
-switch on.
____________________________________________________________ 97
CD4016B Types
TYPICAL ON-STATE RESISTANCE CHARACTERISTICS, TA = 25°C
CHARAC·
SUPPL Y
TERISTIC' CONDITIONS
V DD
IVI
VSS
IVI
'on
+15
0
'on (max.!
+15
0
'on
+10
0
'on (max.!
+10
0
+ 5
0
'on
'on (max.!
+ 5
0
'on
'on (max.!
+7.5
-7.5
+7.5
-7.5
'on
+ 5
- 5
'on (max.!
+ 5
-
'on
+2.5
-2.5
+2.5
-2.5
'on (max.!
* Variation
Vc = +7.SV, VSS
CL=15 p F
=
=
200
+15
LOAD
CONDITIONS
RL - 10kSl
R = 100kSl
VALUE
VALUE
Vis
Vis
IVI
1m
IVI
1m
200
+15
180
ALL UNUSED TERMINALS
ARE CONNECTED TO VSS
+15
200
0
200
0
200
0
300
+11
300
+9.3
320
+9.2
+10
290
+10
250
+10
240
290
0
250
0
300
0
500
+7.4
560
+5.6
610
+5.5
860
+ 5
470
+ 5
450
+ 5
600
0
580
0
800
0
Uk
+4.2
7k
+2.9
33k
+2.7
200
+7.5
200
+7.5
180
+7.5
Fig. 12 - Off-state switch input or output
leakage current test circuit.
VD~f\... Vc·Voo
v"
-7.5
'0.25
200
280
-7.5
±25
180
400
-7.5
±0.25
260
+ 5
250
+ 5
240
+ 5
310
- 5
250
-5
240
-5
600
±D.25
580
±D.25
760
±0.25
liS = 1 KHl V'S = 5V pop
DISTORTION = 0.2 %
10
".
ALL UNUSED TERMINALS ARE
CONNECTED TO Vss
590
+2.5
450
+2.5
490
+2.5
720
-2.5
520
-2.5
520
-2.5
232k
±0.25
300k
±0.25
870k
±0.25
Fig. 13 - Test circuit for square·wave
response.
n.
SCALE. X ~ 0.2 msiDIV Y: 20 VIOIV
VOO" Vc = >2.5V. Vss ~ ·2.5V. RL" lOKH
CL = 15 pF
lIS" 1 KHz VIS= 5Vpp
DISTORTION'" 3 %
SCALE _ X : 0 2 ms/OlV Y '" 2.0 V/DIV
Vao ~ Vc = +5 V. Vss = 5 V. RL" 10Kn
CL=15pF
'IS" 1 KHz V'S, 5 v p P
DISTORTION = 0.4 "{,
-7.SV, RL = 10KD.
Voo
Ir,lf·20nl
200
290
from aperfect switch, ron = 0
SCALE: X = 0.2 mslDlV .. Y = 2.0 V!DIV'
VOO
5
RL - lkSl
VALUE
Vis
1m
IVI
92CS - 27614
92C5-27613
92CS-27612
Fig. 14 - Typical sine wave response of VOO
+1.5 V, VSS = -1.5 V.
SCALE
x""
Y
=
=
Fig. 16 - Typical sine wave response of VOO
+2.5 V, VSS = -2.5 V.
Fig. 15 - Typical sine wave response of VOO =
+5 V, VSS=-5 V.
100 nsiOIV
5.0 VIOl V
92C5-27615
SCALE
SCALE;
X" 100 ns.'DIV
V=5.0VOIV
Fig. 18 - Typical square wave response at VOD
VC=+10 V, Vss
= Gnd.
X ".l00~ns/DIV
Y"2V/OIV
92CS-Z7617
92CS-27616-
Fig. 17 - Typical square wave response at
VOO = Vc = +15 V, VSS = Gnd.
=
=
Fig. 19 - Typical square wave response at VOD
= VC=+5 V, Vss=Gnd.
98 ____________________________________________________________________
CD4016B Types
Voo
p
"'i~t_~l~~
-~~-;-
,
Vos WITH TEST UNIT
11 SWITCH OF C040l6A----...
PLuGGED IN TEST
,.
,
-
-:
.
I
v"
fiXTURE>
Vos FI)(TURE ALONE
TERM
ALL UNUSED TERMINALS
ARE CONNECTED TO
(NO UNIT
510 )OF SOCKET!
ALL UNUSED TERMINALS ARE
CONNECTED TO
!
\Iss
\Iss
Vc - IOV PER DIV
Vas' 0 '2V PER DIV
lOOns PEA DIV '
92C5-27618
fa)
Fig.21 - Propagation delay rime signal input
(V'S) to signal output (Vas).
fb}
Fig.20 - Crosstalk-control input to signal output.
MEASUftED ON 8OONTOH CAPN::ITAHCE
MIDGE MODEL 7!5A II Mlzi
VD~~VC
Ipl,s20ns
v"
Yc-- 5Y
VSS·-5Y
VDD··H~V
SWITCH THRESHOLD VOLTAGE IS DEFINED
AS THE VOLTAGE APPLIED TO A TRANSMISSION GATE CONTROL WHICH CAUSES
10 .. .0. OF TRANSMISSION GATE CURRENT.
ALL UNUSED TERMINALS ARE
CONNECTED TO \ISS
ALL UNJSED TERMINALS
ARE CONNECTED TO Yss
Fig. 22 - Max. control-input repetition rate.
VD~~Vc
Fig.23 - Switch threshold Voltage.
Fig.24 - Capacitance CIOS and COS.
Dimensions and pad layout for CD4016BH
VDO
tr,tfa20ns
VOO
ALL UNUSED TERMINALS ARE
CONNECTED TO VSS
~
_____
vc~~,u7·'I
IpZH
V
r/
10%
os
~RLtoVSS
l.. Vis 10 Voo
~ fPZLf--
V"~!RLIOVOO
10%
Vis to Vss
Fig.25 - Turn·On propagation delay·control input.
92CM-30918
Dimensions in parentheses are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10- 3 inch).
The photographs and dimensions of each
COS/MOS chip represent a chip when it
is part of the wafer. When the wafer is
cut into chips, the cleavage angles are
57° instead of 90° with respect to the
face of the chip. Therefore, the isolated
chip is actually 7 mils (0. 17 mm) larger
in both dimensions.
________________________________________________________________________ 99
CD4017B, CD4022B Typel
COS/MOS Counter/Dividers
High-Voltage Types (20-Volt Rating)
CD4017B-Decade Counter' with
10 Decoded Outputs
CD4022B-Octal Counter with
8 Decoded Outputs
The RCA-CD4017B and CD4022B are 5stage and 4-stage Johnson counters having
10 and 8 decoded outputs, respectively.
Inputs include a CLOCK, a RESET, and a
CLOCK INHIBIT signal. Schmitt trigger
action in the CLOCK input circuit provides
pulse shaping that allows unlimited clock
input pulse rise and fall times.
These counters are advanced one count at
the positive clock signal transition if the
CLOCK INHIBIT signal is low. Counter
advancement via the clock line is inhibited
when the CLOCK INHIBIT signal is high.
A high RESET signal clears the counter to
its zero count. Use of the Johnson counter
configuration pe,mits high-speed operation,
2-input decode-gating and spike-free decoded outputs; Anti-lock gating is provided,
thus assuring proper counting sequence. The
decoded outputs are normally low and go
high only at their respective decoded time
slot. Each decoded output remains high for
one full clock cycle. A CARRY-OUT signal
completes one cycle every 10 clock input
cycles in the CD4017B or every 8 clock
input cycles in the CD4022B and is used to
"0"
2
Features:
• Fully static operation
• Medium-speed operation ...
10 MHz (typ.) at VDD = 10 V
• Standardized, symmetrical output
characteristics
• 100% tested for quiescent current at 20 V
• .5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative
Standard No. 13A, "Standard Specifications
for Description of 'B' Series CMOS Devices"
CLOCK
10 "4"
RESET 15
-'
4
~
'"
"s"
0
•
"7"
"
"9"
0
~
"e"
1100=16
Vss=S
12
CARRY
OUT
CD4017B
Functional Diagram·
CLOCK
"0"
"
CLOCK
INHIBIT
13
","
"
"2"
RESET
"3"
UNITS
Min_
Clock Input Frequency, tCl
5
10
15
-
5_5
Clock Pulse Width, tw
5
10
16
200
gO
60
-
Clock Rise & Fall Time, trCl' tlCl
5
10
15
Supply-Voltage Range (For T A = Full PackageTemperature Rangel
3
Max.
18
"5"
1100=16
Vss:::8
12
CD4022B
Functional Diagram
I.
I.
I.
"
"
"
V,,,
T
Reset Pulse Width, tRW
5
10
15
260
110
60
5
10
15
400
280
150
-
RESET
CLOCK
CLOCK INHIBIT
CARRY OUT
9
10
9
TOP VIEW
CD4017B
TERMINAL DIAGRAM
MHz
ns
I.
,
ns
V,,
I.
I.
VDD
"
RESET
CL.OCK
"
CARRY OUT
12
CLOCK INHIBIT
"
10
9
NC
92CS_24464RI
ns
-
-
VDD
V
NC
230
100
70
"7"
CARRY
OUT
UNLIMITED
5
10
15
0
"6"
10
2
Clock Inhibit Setup Time, ts
w
0
2.5
5
0
u
12
LIMITS
VDD
(V)
~
"4" 0
RECOMMENDED OPERATING CONDITIONS
~
,.
"6"
For maximum reliability, nominal operating conditions should be selected so that operation
is always within the following ranges:
100 ________________________
"3"
'!IlCS-2S0T2R2
• Decade counter/decimal decode display
(CD4017B)
• Binary counter/decoder
• Frequency division
• Counter control/timers
• Divide-by-N counting
• For further application information,
see ICAN~6166 "COS/MOS MSI
Counter and Register. Design and
Applications"
ripple-clock the succeeding device in a multidevice counting chain.·
The CD4017B and CD4022B-series types are
supplied in 16-lead hermetic dual-in-line
ceramic packages (0 and F suffixes), 16lead dual-in-line plastic package (E suffix),
16-lead ceramic flat packages (K suffix), and
in chip form (H suffix).
Reset Removal Time, t rem
~
0
T
CLOCK 13
INHIBIT
Applications:
CHARACTERISTICS
"t"
"2"
14
TOP VIEW
NC - no connection
CD4022B
TERMINAL DIAGRAM
ns
________________________________________
CD4017B, CD4022B Types
CLOCK
INH~BIT
0'
~
____
~f)lL
________
D
en
D
Q3
D
____________________
~GI~
____
~
~
______________
____________-'f)lL___________________
Q4
______________
~GlL
_________________
________________f7IL_____________
____________________
--'ra>~
_____________
~==========~========~f7\~9~======~:;,
n%-.I4b~1
CARRY CUT
Fig. 2 - Tim;ng diagram for CD4017B.
'* ALL
INPUTS PROTECTED BY
COS/MOS PROTECTION NETWORK
92CL-2874!5R2
·CLOCK
INHIBIT
RESET ,"-_______________________________________
,---,L_______________
P~~I~~T ______________________
'0" -----cJ\L______________IOIL__________________ 1""OLI"
2'
'3"
~
rT
rTl
~L_____________ _
--------'"
--I3I
f3lL____________
--------~~~----------------~~~--------D
Q2
D
__________
03
~Is'~
________________
~~~
-----------~~
______
~
r," =====;===~m~,;=====::;:::==='--~~'
CARRt
Qui
Fig. 4 - Timing diagram for CD4022B.
6
"CLOCK
Vss
• ALL INPUTS PROTECTED BY
COS/MOS PROTECTION NETWORK
92CL-28746R2
Fig. 3 - Logic diagram for CD4022B.
_____________________________________________________________________ 101
CD4017B, CD4022B Types
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE. (VDDI
(Voltages refer&nced to VSS Terminal!
-0.5 to +20 V
INPUT VOLTAGE RANGE. ALL INPUTS
-0.5 to V DO +0.5 V
DC INPUT CURRENT. ANY ONE INPUT
±10mA
POWER DISSIPATION PoER PACKAGE (POl.
For T A = -40 to +60 C (PACKAGE TYPE EI
. .
'';
500mW
For T A = +60 to +85°C (PACKAGE TYPE EI
Derate Linearly at 12 mWI C to 200 mW
For T A = -55 to +100oC (PACKAGE TYPES D. FI
...
. . o.
500mW
For TA = +100to +125°C (PACKAGE TYPES D. FI
Derate Llnearlv at 12 mWf C to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE·TEMPERATURE RANGE (All Package Tvpesl
100mW
OPERATING-TEMPERATURE RANGE (TAl:
PACKAGE TYPES D. F. H
-55 to +125°C
PACKAGE TYPE E
-40 to +850 C
STORAGE TEMPERATURE RANGE (T" I
. .
-65 to + 150°C
LEAD TEMPERATURE (DURING SOLD~RINGI:
At distance 1/16 ± 1/32 Inch 11.59 ± 0.79 mm) from case for 10 s max.
+265°C
DRAIN-lO-SOURCE VOL.TAGE (VosI-V
Fig. 5- Typical output low (sinkl current
characteristics.
STATIC ELECTRICAL CHARACTERISTICS
CHARAC·
TERISTIC
CONDITIONS
Vo
(VI
Quiescent
Device
Current,
100 Max.
0.4
LIMITS AT INDICATED TEMPERATURES (OCI
I~
Values at -56, +26, +126 Apply to D,F ,H Packages
Values at -40, +25, +86 Apply to EPackage
+26
I
T
S
VIN VDD
(VI (VI -66
+86
-40
+126
0,5
5
5
5
150
150
-
0.04
10
10
10
300
300
-
0.04
10 /lA
0,15
15
20
20
600
600
-
0.9'4
20
0,20
20
100
100
3000
3000
-
0.08
100
0,5
5
0.64
0.61
0.42
0.36
0.51
1
1.1
0.9
1.3
2.6
2.8
2.4
3.4
6.8
-
-0.42 -0.36 -0.51
-1.3 -1.15 -1.6
-1
-
-3.2
-
0,10
10
1.6
1.5
0.15
15
4.2
4
4.6
0,5
5 -0.64 -0.61
2.5
0,5
5
-2
-1.8
9.5
0,10
10
-1.6
-1.5
-1.1
-0.9
-1.3
-2.6
13.5
0,15
15
-4.2
-4
-2.8
-2.4
-3.4
-6.8
5
mJ
-
0,5
5
0.05
10
0.05
-
0 0.05
0,10
VOL Max
-
0,15
15
0.05
-
0 0.05 V
Output
Voltage
High-Level
VOH Mill
-
Low-Le\.t:I,
Input low
Voltage
Vil Max.
Input High
Voltage,
VIHMin.
Input Current
liN Max.
0,5
5
4.95
4.95
5
-
10
9.95
15
10
15
-
0,15
9.95
14.95
5
1.5
3
-
15
4
-
0.5,4.5
-
5
3.5
1,9
1.5,13.5
-
10
7
7
15
11
11
-
1.5
10
LS,13.5
-
-
0,18
18
0.5,4.5
1,9
-
±0.1
±0.1
14.95
3.5
±1
±1
Fig. 7- Typical output high (source) current
characteristics.
0 0.05
0,10
-
-
DRAIN-lO-SOURCE VOL.TAGE IVosI-V
-
.-
Output Vo'tage.
(VosI-Y
Fig, 6- Minimum output low (sink) curront
characteristics.
0,10
Output low
(Sink) Current 0.5
IOl Min.
1.5
Output High·
(Source)
Current,
IOH Min.
DRAIN-lO-SOURCE VOI..TAGE
Max.
Typ.
Min.
3
4
V
-
±10- 5 ±0.1 /lA
Fig. 8- Minimum output high (sourco) current
characteristics.
102 ________________________________________________________________
CD4017B, CD4022B Types
DYNAMIC ELECTRICAL CHARACTERISTICS
At TA = 25°C, Input t r, tt = 20 ns, CL = 50 pF, RL = 200 kn.
CHARACTERISTIC
CONDITIONS
VDD(V)
LIMITS
UNITS
Min. Typ. Max.
CLOCKED OPERATION
-
5
10
15
Propagation Delay Time, tpHL' tpLH
Decode Out
_.
5
10
15
Carry Out
Transition Time, tTHL' tTLH
Carry Out or Decode Out Line
Maximum Clock Input Frequency, tCL
Minimum Clock Pulse Width, tw
Clock Rise or Fall Time, trCL, ttCL
*
5
10
15
-
5
10
15
2.5
5
5.5
5
10
15
-
5,10,15
Input Capacitance, CIN
-
Any Input
ns
300
125
80
600
250
160
100
50
40
200
100
80
ns
5
10
11
-
MHz
100 200
45
90
30
60
I
LOAD CAPACITANCE (Cll- pF
Fig. 10 - Typical transition time as a function
of load capacitance.
ns
UNLIMITED
-
5
10
15
Minimum Clock Inhibit
to Clock Setup Time, ts
325 650
135 270
85 170
115 230
50 100
35
70
ns
LOAD CAPACITANCE(CL) -
-
5
-
pF
265
115
85
530
230
170
ns
130 260
55 110
30
60
ns
200 400
140 280
75 150
ns
pF 92CS-3094!1
Fig. 11 - Typical propagation delay time as a
function of load capacitance (clock
to decode output).
RESET OPERATION
Propagation Delay Time, tpH L' tJ:'LH
Carry Out or Decode Out Li'nes
5
10
15
-
Minimum Reset Pulse Width, tw
5
10
15
Minimum Reset Removal Time
5
10
15
-
-
* Measured with respect to carry output line.
LOAD CAPACITANCE {CL1- pF
92CS-30946
Fig. 12 - Typical propagation delay time as a
function of load capacitance (clock
to carry·out).
CLOCK
10
AMBIENT TEMPERATURE
~L~g~ ~-r----------~------------------------------
r-\ ___________
RESET ___-+-_____________________...
DECODE 1-9
OUTPUT
- . , ~" I PRLH
92CS- 30948
10
DELAYS MEASURED BETWEEN 50 % LEVELS ON ALL WAVEFORMS
Fig. 9- Propagation delay, setup, and
hold time waveforms.
10
10 2
10 3
INPUT CLOCK FREQ (f el '-11HZ
104
10'
Fig. 13 - Typical dyanamic power disSipation as a
function of clock input frequency.
_______________________________________________________________________ 103
CD4017B, CD4022B Types
V~NPU(J'
'. :::~ "."
INPUT~
o
Vss
o ~
.
SEOUENTIALLY,
"ss
TO 90TH "DO ANOVSS
CONNECT ALL UNUSED
INPUTS TO EITHER
'100 OR 'ISS·
vss
92CS-21441Rr
Vss
Fig. 14 - Quiescent-cievice-
current testeifcuit
Fig. 15 - input-leakage current.
L. _ _ _ _ _ _ _ _ _ _ _ _ ...J
92CS-30949
nCS-30950
Fig. 18 - Dillideby Ncounter (N~ 10) with N
Fig. 17 - Dynamic power dissipation test circuit.
decoded au tputs.
Fig. 16 - Input-voltage test circuit.
When the Nth decoded output is reached
(Nth clock pulse) the S-R flip flop (con-·
structed from two NOR gates of the
CD40018) generates a reset pulse which
clears the CD40178 or CD40228 to its zero
count. At this time, if the Nth decoded output is greater than or equal to 6 in the CD40178 or 5 in the CD40228, the COUT line
goes high to clock the next CD40178 or CD40228 counter section. The "0" decoded
output also goes high at this time. Coincidence of the clock low and decoded "0"
output low resets the S-R flip flop to enable
the CD40178 or CD40228. If the Nth decoded output is less than 6 (CD40178) or 5
(CD40228), the COUT line will not go high
and, therefore, cannot be used. In this case
"0" decoded output may be used to perform
the clocking function for the next counter.
92CM-3095Z
CD40178H
CD4022BH
The photographs and dimensions of each COS/MOS
chip represent a chip when it is part of the wafer.
DimenSions m parentheses are in millimeters and
are derived from the basic inch dimensions as ;nd,'cated. Grid graduations are in mils (te1 3 inch).
When the w~fer is cut int~ chips. the cleavage
angles are 57 instead of 90 with respect to the
face of the chip. Therefore. the isolated chip ;s
actually 7 mUs (0. 11 mmJ la;ger in both dimensions.
104 ______________________________________________________________- - - - - -
CD4018B Types
COS/MOS Presettable
Divide-By-~N' Counter
High-Voltage Types (20-Volt Rating)
The RCA-CD4018B types consist of 5
Johnson-Counter stages, buffered Q outputs
from each stage, 'and counter preset control
gating. CLOCK, RESET, DATA, PRESET
ENABLE, and 5 individual JAM inputs are
provided. Divide by 10, 8, 6, 4, or 2 counter
configurations
can be implemented by
feeding the 05, 64, 03, 02, 01 signals,
respectively, back to the DATA input.
Divide-by-9, 7, 5, or 3 counter configurations can be implemented by the use of a
CD4011 B to gate the feedback connection
to the DATA input .. Divide-by functions
greater than 10 can be achieved by use of
multiple CD4018B units. The counter is
advanced one count at the positive clocksignal transition. Schmitt Trigger action on
the clock line permits unlimited clock rise
and fall times_ A high RESET signal clears
the counter to an all-zero condition. A high
PRESET-ENABLE signal allows information
on the JAM inputs to preset the counter.
Anti-lock gating is provided to assure the
proper counting sequence.
Features:
• Medium speed operation. _ . _ _ . 10 MHz (typ.) at
VDD-VSS=10V
• Fully static operation
• 100% tested for quiescent current at 20 V
• Standardized, symmetrical output characteristics
• 5-V, 10-V, and 15-V parametric ratings
• Maximum input current of 1 p.A at 18 V over full packagetemperature range; 100 nA at 18 V and 25°C
• Noise margin (full package-temperature
range) =
1 Vat VDD = 5 V
2 Vat VDD = 10 V
2.5 V at VDD = 15 V
• Meets all requirements of JEDEC Tentative
Standard No_ 13A, "Standard Specifications
for Description of 'B' Series CMOS Devices"
~:iiU
CLOCK
.
10
I.
02
DATA
RESET
iii
IS
6
0,
"
O.
~
0
w
~
w
~
~
"m
13 -
a.
Vss
FUNCTIONAL DIAGRAM
Applications:
• Fixed and programmable divide-by-l0~ 9, 8,
7, 6, 5,4, 3, 2 counters
• Fixed and programmable counters greater
than 10
TERMINAL DIAGRAM
Top View
DATA
JAMI
JAM 2
Q2
CiT
Q3
JAM3
Vss
The CD40l8B types are supplied in l6-lead
hermetic dual-in-line ceramic packages (D
and F suffixes), l6-lead dual-in-line plastic
packages (E suffix), l6-lead ceramic flat
packages (K suffix), and in chip form (H
suffix).
I.
2
16
IS
14
13
12
"
10
voo
RESET
• Programmable decade counters
• Divide-by-"N" counters/frequency
synthesizers
• Frequency division
• Counter control/timers
CLOCK
as
JAMS
ii4
PRESET ENABLE
JAM 4
92CS-24460
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (VDDI
(Voltages referenced to VSS Terminal) .
. -0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS .
-0.5 to V DD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT .
±10mA
POWER DISSIPATION PoER PACKAGE (POl:
For T A = -40 to +600 C (PACKAGE TYPE E). .
. . . . . . . ...
500mW
For T A = +60 to +85 9, (PACKAGE TYPE EI. .
Derate linearlv at 12 mW/oC to 200 mW
For T A = -55 to +100
(PACKAGE TYPES 0, FI
. . . . . . . ..
500mW
For TA = +100 to +125 C (PACKAGE TYPES 0, FI
Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR T A = FULL PACKAGE-TEMPERATURE RANGE (~II·paekage Types)
100mW
OPERATING-TEMPERATURE RANGE (T A):
PACKAGE TYPES 0, F, H
-55 to +1250 C
PACKAGE TYPE E
-40 to +85°C
STORAGE TEMPERATURE RANGE (T st )
. .
-65 to +150 0 C
LEAD TEMPERATURE (DURING SOLD~RING):
At distance 1116 ± 1132 inch (1.59 ± 0.79 mml from case for 10 s max.
f?
__________________________________________________________________ 105
CD4018B Types
RECOMMENDED OPERATING CONDITIONS at TA = 25°C, Unless Otherwise Specified
For maximum reliability, nominal operating conditions should be selected so that operation
is always within the following ranges.
CHARACTERISTIC
VOD
Min.
5
10
15
160
70
50
-
ns
JlS
Supply Voltage Range (at T A = Full Package·
Temperature Range)
3
Max.
UNITS
18
V
3
7
8.5
MHz
Clock Input Frequency,
fCl
Clock Pulse Width,
tw
5
10
15
Clock Rise & Fall Time,
trCl,tfCl
5
10
15
Unlimited
Data Input Set· Up Time,
ts
5
10
15
40
12
16
Data Input Hold Time,
tH
5
10
15
140
80
60
Preset or Reset Pulse Width,
tw
5
10
15
160
70
50
5
10
15
80
30
20
/
Preset or Reset Removal Time
-
-
-
ns
-
ns
-
ns
ns
Fig. 1 - Logic diagram.
BVDD
ON
Dvss
* ALL
INPUTS PROTECTED
BY COS/MaS INPUT
PROTECTION NETWORK
Fig. 2.- Detail of a typical stage.
106 __________________________________________________________________
CD4018B Types
STATIC ELECTRICAL CHARACTERISTICS
LIMITS AT INDICATED TEMPERATURES (OC)
CHARACCONDITIONS
Values at -55, +25, +125 Apply to D,F,H Packages
TERISTIC
Values at -40, +25, +85 Apply to E Package
+25
Vo
VIN VOD
(V)
(V) (VI -55
+85 +125
-40
Min. Typ. Max.
Quiescent
Device
Current,
100 Max.
-
0.5
5
5
5
150
150.
-
0.10
10
10
10
300
300
0.15
15
20
20
600
600
0.20
20
100
100
3000
3000
0.4
0.5
5
0.64
0.61
0.42
0.36
0.51
1
1.6
1.5
1.1
0.9
1.3
2.6
4.2
4
2.8
2.4
3.4
6.8
10
0.15
15
4.6
0.5
5
2.5
0.5
5
-2
-1.8
0.04
0.08
100
-1
-
-1.3 -1.15
-1.6
-3.2
-
-
-0.42 -0.36 -0.51
-0.64 -0.61
5
10 p,A
20
I
ORAIN-TO-SOURCE VOLTAGE(VOSI-V
Fig. 3 - Typical output low (sink) current
characteristics.
m~
9.5
0.10
10
-1.6
-1.5
-1.1
-0.9
-1.3
-2.6
13.5
0.15
15
-4.2
-4
-2.8
--2.4
-3.4
-6.8
-
0.5
5
0.05
10
0.05
-
0 0.05
0.10
0.15
15
0.05
-
0 0.05 V
Output Voltage:
Low-Level.
VOL Max.
Output
Voltage:
High·Level.
VOH Min.
Input High
Voltage.
VIHMin.
0.04
-
0.10
Input Low
Voltage
VIL Max.
0.04
-
Output Low
(Sink) Current 0.5
IOL Min.
1.5
Output High
(Source)
Current.
IOH Min.
-
U
N
I
T
S
0 0.05
-
0.5
5
4.95
4.95
5
-
-
0.10
10
9.95
9.95
10
-
0.15
15
14.95
14.95
15
-
-
1.5
-
4
0.5,4.5
-
5
1.5
-
1.9
-
10
3
1.5.13.5
-
15
4
-
0.5,4.5
-
5
3.5
3.5
1.9
1.5.13.5
-
10
7
7
-
15
11
11
0.18
18
Input Current
liN Max.
-
±0.1
±0.1
±1
±1
~'
E-IO-SOIJI'!:
±10- 5
-
ORA~N-TO-SOURCE
VOLTAGE
11051-1/
Fig. 4 - Minimum output low (sink) current
characteristics.
3
ORAIN-TO-SOURCE VOLTAGE
V
IVasl-v
I
±0.1 p,A
Fig. 5 - Typical output high (source) current
characteristics.
DRAIN-lO-SOURCE VOLTAGE !Vos]-I/
-I~
-:5
-10
AMBIENT TEMPERATURE ITAI-25·C
=
•• ,
rt:!
H
...
'm .... ,...!.:::.
H_. -t~tt::!
:-_.
+'::
•••
':::
l!!
_'0"
••••
to
•
lj'mi t :::'I[,'!
.... , till:
.. - , IHj"
~i' ; ':: "
.......
II
Fig. 6 - Minimum output high {source} current
characteristics.
LOAD
I
Fig. 7 - Tvpical transition time as a function of
load capacitance.
Fig. 8 - Typical propagation delay time as a
function of load capacitance
(CLOCK to OJ.
_____________________________________________________________________ 107
CD4018B Types
DYNAMIC ELECTRICAL CHARATERISTICS at TA
=25°C, Input tr,tt =20 ns,
Cl = 50 pF, Rl = 200 kn
TEST CONDITIONS
CHARACTERISTIC
VDD (VI
LIMITS
UNITS
Min.
Typ.
Max.
-
200
90
65
400
180
130
ns
100
50
40
200
100
80
ns
CLOCKED OPERATION
5
10
15
Propagat i on De Iay Ti me;
tplH' tpHl
Transition Time;
tTHl,tTlH
Maximum Clock Input
Frequency,
tCl
I
Minimum Clock Pulse Width,
tw
5
10
15
-
5
10
15
3
7
8.5
6
14
17
-
MHz
5
10
15
-
80
35
25
160
70
50
ns
5
10
15
Clock Rise & Fall Time;
trCL,ttCL
Unlimited
Minimum Data Input Set·Up
Time.
ts
5
10
15
-
Minimum Data Input Hold
Time,
tH
5
10
15
-
Average I nllUt Capacitance, CI
92e9-29849
IRESETto OJ.
lis
40
12
6
-
70
40
30
5
140
80
60
7.5
5
10
15
-
275
125
90
550
250
180
ns
5
10
15
-
-
80
35
25
160
70
50
ns
5
10
15
-
40
15
10
80
30
20
ns
Any Input
pF
9 - Typical propagation delay time as a
function of load capacitance
20
6
3
-
LOAD
Fig.
ns
2:
4 68 ro
2
468roz 2
1032
468r04 2
CLOCK FREQUENCY IfcLI- kHz
ns
o488r05
92CS-29852
Fig. 10 - Typical dynamic power dissipation
as a function of clock input
frequency.
pF
PRESET* OR RESET OPERATION
Propagation Delay Time;
Preset or Reset to 0:
tpLH, tpHL
Minimum Preset or Reset
Pulse Width,
tw
Minimum Preset or Reset
Removal Time
INPUTS
o
"ss
"ss
Fig. 11 - Quiescent device
current te,tcircuit
• At PRESET ENABLE or JAM Inputs.
"~.pu(J'
. . =~
Vss
92CS-2744IAI
"...
TO BOTH "DD AND 'Iss'
CONNECT ALL UNIJSD)·
..urS 10 EITHER
VooCIRVSS'
92CS-lta"
Fig. 12 - Input voltage test circuit.
Fig. 13 - Input current test circuit.
Fig. 14 - DynamiC power dissipation test circuit.
108 ____________________________________________________________________
CD40188 Types
("DATA" INPUT TIED TO
CLOCK
RESET
05
EXTERNAL CONNECTIONS FOR DIVIDE
BY 10, 9. 8, 7, 6, 5, 4, :3 OPERATION
FOR DECADE COUNTER CONFIGURATION I
rtrt r- f"\.. r-r-r-r- rt rL r- rt L rL f"\.. tt- L, L rt. L rt rt rV-
r-I\
rh
PRESET
DIVIDE BY 10
DIVIDE BY B
DIVIDE BY 6
DIVIDE BY 4
DIVIDE BY 2
DIVIDE BY 9
1/2 CQ401lB
I
i
I
i
DON'T CARE UNTIL
Jam)
I
I, II
r-r-
I
I
I
!
II
I
_
05
I
I
I
I-
1/2 CD4QII B
~
-3
,... I-- I--
-2
'-I-
Fig. 15 -
I
I
_
03
j-----------;
~
I
I
I
_
I
02
i
CONNECTED BACK TO "DATA"
(SKIPS "ALL-I'$" STATE)
I ___________ .JI
L
DIVIDE BY 3
1/2 C0401lB
"
I
(SKIPS "ALL-I's" STATE)
j __ -"/.?-,o.4-"!!~ __ ~
~
I
r
I
CONNECTED BACK TO "OATA"
DIVIDE BY 5
~ -f-
!
I
I
IL _ _ _ _ _ _ _ _ _ _ _ JI
i-'
!
,I
:-----------:
_
04
.,
i
CONNECTED BACK TO "DATA"
{SKIPS "ALL·I's" STATE I
DIVIDE BY 7
I
1-f-I
I
I
:
I
I
I ____________ JI
L
,
PRESET" GOEI HIGH I
I
I
I,
j-----------i
~
04
I
IL
CONNECTED BACK TO "DATA"
(SKIPS "ALL-I's" STATE)
_ _ _ _ _ _ _ _ _ _ ...JI
92CS-I707IR3
92SS-4148R2
Timing diagram.
Fig. 16 -
External connections for divide by 10,9,
8, 7, 5, 4, 3, 2 operation.
92CM-2985:5
Dimensions and pad layout for CD4018B,
The photographs and dimensions of each COS/MOS
DimenSions
parentheses are in millimeters and
are derived from the baSIC Inch dimensions as indicated. Grid graduations are In mils 00-- 3 inch).
In
chip represent a chip when it is part of the wafer.
When the w~f~r is cut int~ chips, the cleavage
angles are 51
Instead of 90
face of the chip.
with respect to the
Therefore, the isolated chip is
actually 7 mils (0. 17 mm) larger in both dimensions.
_____________________________________________________________________ 109
CD4019B Types
COS/MOS Quad
AND/OR Select Gate
High-Voltage Types (20-Volt Rating)
The RCA-CD4019B types consist of four
AND/OR select gate configurations, each
consisting of two 2-input AND gates driving
a single 2-input OR gate. Selection is accomplished by control bits Ka and Kb. In
addition to selection of either channel A or
channel B information, the control bits can
be applied simultaneously to accomplish
the logical A + B function.
The CD4019B types are supplied in 16-lead
hermetic dual-in-line ceramic packages (D
and F suffixes), 16-lead dual-in-line plastic
packages (E suffix), 16-lead ceramic flat
packages (K suffix), and in chip form (H
suffix).
Features:
• Medium-speed operation .....
... tpHL =tpLH = 60 ns (typ.) at CL =50 pF, V DD =10 V
• Standardized, symmetrical output characteristics
• 100% tested for quiescent current at 20 V
• 5·V, 10·V, and 15·V parametric ratings
• Meets all requirements of JEDEC Tentative Standard
No. 13A, "Standard Specifications for Description of 'B'
Series CMOS Devices"
• Maximum input current of 1 /lA at 18 V
over full package·temperature range; 100
nA at 18 V and 25 0 C
• Noise margin (full package·temperature
1 V at VDD = 5 V
range) =
2 V at VDD = 10 V
?5 Voi VDD = 15V
CD4019B
FUNCTIONAL DIAGRAM
App/ications:
MAXIMUM RATI NGS, Absolute-Maximum Values:
DC SUPPLY-VOL TAGE RANGE, (V DO!
(Voltages referenced to VSS Terminal)
-0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS
-0.5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT
±10mA
POWER DISSIPATION PER PACKAGE (PD!:
For TA = -40 to +60 0 C (PACKAGE TYPE E!
.
...
500 mW
.
For T A = +60 to +85 0 C (PACKAGE TYPE E!
Derate linearly at 12 mW/oC to 200 mW
For TA = -55 to +1000 C (PACKAGE TYPES D,F!
.
.
500mW
For TA = +100 to +125 0 C (PACKAGE TYPES D, F!
Derate linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types!
100mW
OPERATING-TEMPERATURE RANGE (TA!:
PACKAGE TYPES D, F. H
-55 to +125 0 c
PACKAGE TYPE E .
-40 to +85 0 C
STORAGE TEMPERATURE RANGE (T stg !
-65 to +1500 C
LEAD TEMPERATURE (DURING SOLDERING!:
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for lOs max.
+265 0 C
• AND·OR select gating
• Shift·right/shift·left registers
• True/complement selection
• AND/OR/Exclusive·OR selection
TERMINAL DIAGRAM
Top View
B'
A'
B'
A2
B2
AI
BI
I.
15
I.
13
12
Vss
"
10
9
VDD
A"
Kb
D4=A4Ka+B4Kb
D3-A3 Ko+ 83 Kb
D2~A2Ka+B2.Kb
Dt"AI Ka+BI Kb
Ko
92CS-24461
TRUTH TABLE
Voo
*
A,
Ka Kb An Bn On
1
1
0
0
0
1
1
1
1
0
0
1
1
0
1
1
1
0
X
X
X
0
0
1
1
1
1
X
X
1
0
X
0
1
0
1
1
0
1
0
0
0
1
1
1
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating
conditions should be selected so that operation
is always within the following ranges:
CHARACTERISTIC
VDD Min. Max. Units
(V)
Supply·Voltage Range
(For T A c Full Package
Temperature Range)
-
3
18
V
Fig. 1 - Schematic diagram for 1 of 4 identical stages.
110 __________________________________________________________________
CD4019B Types
STATIC ELECTRICAL CHARACTERISTICS
LIMITS AT INDICATED TEMPERATURES (DC)
U
Values at -55, +25, +125 Apply to D, F, H Packages
N
Values at -40, +25, +85 Apply to E Package
I
+25
T
VIN VDD
(V) (V) -55 -40
+85
+125 Min.
Typ.
Max. S
CONDITIONS
CHARAC·
TERISTIC
Quiescent
Device
Current, IDD
Max.
Output Low
(Sink)
Current
IOL Min.
Output High
(Source)
Current,
IOH Min.
Vo
(V)
-
0,10
5
10
2
1
2
0,15
0,20
15
20
4
20
0.4
0,5
5
0.5
0,10
1.5
0,15
4.6
2.5
0.5
0,5
9.5
0,10
13.5
0.15
-
0,5
-
0.10
0,15
0,5
1
30
30
60
-
0.02
0.02
-
4
20
60
120
600
120
600
0.64
0.61
0.42
0.36
10
1.6
1.5
1.1
0.9
1.3
2.6
15
4.2
4
2.8
2.4
3.4
6.8
-
0.02
0.04
-
1
2 Il A
4
20
DRAIN-TO-SOURCE VOlTAGE (VOSI-V
0.51
1
5 -0.64 -0.61 -0.42 -0.36 -0.51
-1
-2 -1.8 -1.3 -1.15 -1.6 -3.2
-1.6 -1.5 -1.1 -0.9 -1.3 -2.6
10
-4 -2.8 -2.4 -3.4 -6.8
-4.2
15
5
-
Fig. 2 - Typical output low (sink) current
characteristics.
-
rnA
·J:
e
I
I~
+i--GATE-TO-SOURCE VOLTAGE (VGS'·15V
ai
'25
10
;;
Output Voltage:
Low·Level,
VOL Max.
Output Voltage:
High·Level,
VOHMin.
Input Low
Voltage,
VILMax.
Input High
Voltage,
VIHMin.
Input Current
'IN Max.
0.05
-
15
0.05
0.05
0.5
0.10
0,15
5
10
15
4.95
9.95
14.95
4.95
9.95
14.95
-
5
10
1.5
1.5,13.5
-
0.5,4.5
1,9
-
1.5,13.5
-
0.5,4.5
1,9
-
5
10
0
-
0
0.05
0.05
-
-
-
1.5
3
-
15
4
-
-
3
4
5
10
3.5
7
3.5
-
7
-
-
15
11
11
-
0,18
18
±0.1
±1
±1
-
·
75 ,-
;~
t-
+
10V
g ,
V
-
5
10
15
±0.1
~
0.05
·,
~ 25
511
5
10
15
DRAIN-TO-SOURCE VOLTAGE IVosl-V
-
Fig. 3 - Minimum output low (sink) current
characteristics.
DRAIN-lO-SOURCE VOLTAGE (YosI-V
V
-
±10- 5 ±0.1
IlA
Fig. 4 - Typical output high (source) current
characteristics.
DRAIN-TO-SOURCE IiOLTAGE
IVOSI-V
LOAD CAPACITANCE
Fig. 5 - Minimum output high (source) current
characteristics.
Fig. 6 - Typical transition time as a function of
load capacitance.
-pF
Fig. 7 - Propagation delay time as a function
of load capacitance.
_____________________________________________________________________ 111
CD4019B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA =25o C.lnputtr.tt=20ns.CL =50pF.
RL =200 kn
LIMITS
TEST
CONDITIONS
CHARACTERISTIC
Min.
Typ.
Max.
5
10
15
-
300
120
100
ns
200
100
80
ns
-
150
60
50
100
50
40
All Aand B
Inputs
-
5
7.5
pF
Kaand Kb
Inputs
-
10
15
pF
Propagation Delay Time;
tpLH' tpHL
5
10
15
Transition Time;
tTHL. tTLH
Input Capacitance. CIN
n.
UNITS
VDD
(V)
.
I
2
INPUTS
INPUTO·
Veo
OUTPUTS
Vss
3
4
Fig. 8 - Typical dynamic power dissipation
as a function of input frequency.
Yc
INPUOS
Voo
:~:~~RE INPUTS
~ v~
o
VIL
.
-=-
0 ~
Va
.
SEQUENTIALLY,
TO BOTH VoD AND'Vss'
CONNECT ALL UNUSED
INPUTS TO EITHER
VDD DRVss '
NOTE:
V'S
92CS-29885
Fig. 10 - Quiescent device
Yss
UCS-274QZ
92C5-2744IRI
Vss
Fig. 9 - Dynamic power dissipation
test circuit.
-:.srN"~OM8IN.TI0iN
Fig. 11 - Input voltage test circuit.
Fig. 12 - Input current test circuit.
current test circuit.
TYPICAL APPLICATIONS
OUT
I
OUT
2
OUT
3
Fig. 13 - AND/OR select gating.
OUT
•
92CS-Z98H
Fig. 14 - "Shift leftlshift right" register.
112 ______________________~-----------------------------------------------
CD4019B Types
TYPICAL APPLICATIONS (CONT'O)
" 0',
rrfd,;i1, ~,
II
::
:1
JJ
CD4001B
: :
OR EQUIV.
::
::
II
I J
CD400f8
::
OR EQUIV.
::
'::
I
I I
C040018
::
OR EQUtV.
:
I
:
::II
!
J
S -2--' L:s--Z -' L~2--'
----- - ---- - ----- --,
OAII
II
~o ~'l!!!)} L-
r--
,
I
,
f
ce400Ts OR EOU/V.
,
(Kg)
,
L___ _
_
TRUE
__ J
COMPLEMENT
(Kb)
-++j:::+;::::=l:j::=t:;:=+1=~==++=t:::;-t- SELECT
SELECT
TRUTH TABLE
,[·1 ,[.1
OUT
,
,·0
,
OUT
OUT
OUT
OUT
OUT
2
92CS-Z'JB89
OUT
2
OUT
l
OUT
•
92C$-29888
Fig. 75 - AND/OR Exclusive·OR selector.
Fig. 16 - uTrue complement selector.
U
14---------;-:2:-.~:'.~
Dimensions and pad layout for CD4019BH
Dimensions in parentheses are in millimeters and
are derived from the basic inch dimensions as in·
dicated. Grid graduations are in mils (1cr 3 inch).
_"'_
The photographs and dimensions of each COS/MOS
chip represent a chip when it is part of the wafer.
When the wafer is cut into chips, the cleavage
angles are 57° instead of 90° with respect to the
face of the chip. Therefore, the isolatt!d chip ;s
actually 7 mils (0. 17 mm) larger in both dimensions.
113
CD4020B, CD4024B, CD4040B Types
COS/MOS Ripple-Carry
Binary Counter/Dividers
High-Voltage Types (20-Volt Rating)
CD4020B - 14 Stage
CD4024B - 7 Stage
CD4040B - 12 Stage
RCA-CD4020B, C04024B, and CD4040B
'are ripple-carry binary counters. All counter
stages are master-slave flip-flops. The state
of a counter advances one count on the
negative transition of each input pulse; a high
level on the RESET line resets the counter to
its all zeros state. Schmitt trigger action on
the input-pulse line permits unlimited rise
and fall times. All inputs and outputs
are buffered.
The CD4020B and CD4040B types are
supplied in 16·lead hermetic dual-in-line
ceramic packages (0 and F suffixes). 16-lead
dual-in-line plastic packages (E suffix), 16lead ceramic flat packages (K suffix), and in
chip form (H suffix).
Features:
Voo
• Medium-speed operation
• Fully static operation
• Buffered inputs and outputs
• 100% tested for quiescent current at 20 V
• Standardized, symmetrical output characteristics
• Fully static operation
• Common reset
.5-V, 10-V, and 15-V parametric ratings
• Maximum input current of 11lA at 18 V
over full package-temperature range;
100 nA at 18 V and 25°C
• Noise margin (over full package-tempera-
10
'"
01
INPUT
PULSES
a.
as
•
o
as
14-STAGE
13
RIPPLE
COUNTER
12 Q9
14 010
15 all
I
012
2
013
01'
'"
1~
0.
l~
0
0
'"
'"
~
~
~
~
m
~
,
RESET
92CS·25053R2
Vss
1 Vat VDD = 5 V
ture range):
00
07
CD4020B
FUNCTIONAL DIAGRAM
2 Vat VDD = 10 V
2_5 V at VDD = 15 V
• Meets all requirements of JEDEC Tentative
Standard No. 13A, "Standard Specifications
for Description of 'B' Series CMOS Devices"
V.O
Applications:
I.
• Control counters
• Timers
• Frequency dividers
• Time·delay circuits
12
INPUT I
PULSES
The C04024B types are supplied in 14-lead
hermetic dual-in-line ceramic packages (0
and F suffixes), 14-lead dual-in-line plastic
packages (E suffix), 14-lead ceramic flat
packages (K suffix), and in chip form (H
suffix).
7-STAGE
RIPPLE
COUNTER
RESET
0,
0,
O.
O.
a,
00
07
NC=8.IO.13
VSS
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (V DD )
--(l.5 to +20 V
(Voltages referenced to VSS Terminal)
INPUT VOLTAGE RANGE, ALL INPUTS
--(l.5 to VDD +0.5 V
±10mA
DC INPUT CURRENT, ANY ONE INPUT
POWER DISSIPATION PER PACKAGE (PD):
For TA -40 to +60 oC (PACKAGE TYPE E)
• . • • • . • .•
500mW
For TA = +60 to +850 C (PACKAGE TYPE E)
_
Derate Linearly at 12 mWtGC to 200 mW
For TA = -55 to +1000 C (PACKAGE TYPES D,F)
• • . • • • • ••
500mW
For T A = +100 to +125 0 C (PACKAGE TYPES 0, F)
Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types)
100mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPES 0, F, H
-55 10 +1250 C
PACKAGE TYPE E _
-40 to +85 0 C
-65 10 +1500 C
STORAGE TEMPERATURE RANGE (T.tg )
LEAD TEMPERATURE IDURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ±0_79 mm) from case for 10. max_
CD4024B
92CS-25051R4
FUNCTIONAL DIAGRAM
C
VD~
16
10
" 01
7 02
"03
INPUT
PULSES
'04
12-STAGE
RIPPLE
COUNTER
'05
206
407
13 Q8
TERMINAL ASSIGNMENTS
09
4 QIO
1!5 QII
11
CD4024B
CD4040B
Vss
012
013
01'
os
10
15
~
RESET
I.
VDO
13
I<
010
07
"
DB
12
os
II
0"
05
A.
NC
01
Q2
NC
05
07
12
D.
10
RESET
Vss
" "
I.
Vss
a'
NC
01
TOP..,IEW
TOP
10
a"
as
"
07
"
Q4
12
D.
11
"
02
v••
all
010
aB
0"
10
IIss
VIEW
NC- NO CONNECTION
01
TOP VIEW
92CS-24466RI
114
012
92CS-20747R2
~
'"
~
~
~
92CS-29066A2
CD4040B
v••
all
0
'"
I QI2
RESET
CD4020B
~
g
FUNCTIONAL DIAGRAM
CD4020B, CD4024B, CD4040B Types
RECOMMENDED OPERATING CONDITIONS at TA = 25°C. Unless Otherwise Specified
For maximum reliability, nominal operating conditions should be selected so that operation
is always within the following ranges:
CHARACTERISTIC
Max.
UNITS
18
V
3.5
8
12
MHz
VDD
Min.
fq,
5
10
15
-
Input-Pulse Width.
tw
5
10
15
140
60
40
-
ns
Input-Pulse Rise or Fall Time.
trq,' tfq,
5
10
15
Unlimited
Reset Pulse Width.
tw
5
10
15
200
80
60
-
ns
Reset Removal Time.
tREM
5
10
15
350
150
100
-
ns
Supply Voltage Range (at T A = Full PackageTemperature Range)
Input-Pulse Frequency.
3
0'
Fig. 4 - Detail of typical flip-flop stage.
!IS
I
I
DRAIN-TQ-SOURCE VOLTAGE ''10S)-V
Fig. 5 - Typical output low (sink) current
characteristics.
.
DD
~
__
INPUTS
PROTECTED BY
COS/MOS PROTECTION
NETWORK
01
014
Vss
Fig. 1 - Logic diagram for CD4020B.
DRAIN-lO-SOURCE VOLTAGE IVosl-V
DD
~
----
Fig. 6 - Minimum output low (sink) current
characteristics.
*INPUTS
PROTECTED BY
COS/MOS PROTECTION
NETWORK
01
07
Vss
DRAIN-lO-SOURCE VOLTAGE
~
l"osl-V
I
Fig. 2 - Logic diagram for CD4024B.
DD
___
* INPUTS
PROTECTED BY
COS/MOS PROTECTION
NETWORK
01
012
Vss
Fig. 3 - Logic diagram for CD4040B.
Fig. 7 - Typical output high (source) current
characteristics.
_______________________________________________________________________ 115
CD4020B, CD4024B, CD4040B Types
STATIC ELECTRICAL CHARACTERISTICS
CHARACTER·
ISTIC
Quiescent Device
Current,
IOD Max.
Output Low
(Sink) Current
IOlMin.
Output High
(Source)
Current,
IOH Min.
0.4
0.5
1.5
4.6
2.5
9.5
13.5
Output Voltage:
low·level,
VOL Max.
Output Voltage:
H igh·level,
VOH Min.
Input low
Voltage,
Vil Max.
Input High
Voltage,
VIH Min.
Input Current
liN Max.
DRAIN-YO-SOURCE VOL.TAGE
(VDsl-~
LIMITS AT INDICATED TEMPERATURES (OC)
Valu ...t-55, +25, +125 Apply to D,F,H Packages
CONDITIONS
V.lues at -40, +25; +85 Apply to E Package
UNITS
+25
Vo
VIN VDD
+125 Min.
Typ. Max.
+85
(V)
(V)
(V) -55 -40
D,S
0,10
0,15
0,20
5
10
15
20
5
10
20
100
5
10
20
100
150
300
600
3000
150
300
600
3000
D,S
0,10
0,15
0.5
0.5
0.10
0,15
5
10
15
5
5
10
15
0.64
1.6
4.2
-0.64
-2
-1.6
-4.2
0.61
1.5
4
-0.61
-1.8
-1.5
-4
0.42
0.36
0.9
2.4
-0.36
-1.15
-0.9
-2.4
1.1
2.8
-0.42
-1.3
-1.1
-2.8
0,5
5
0,10
0,15
0,5
0,10
0,15
10
15
5
10
15
0.05
0.05
0.05
4.95
9.95
14.95
5
10
15
5
10
15
1.5
3
4
3.5
7
11
0.5,4.5
1,9
1.5,13.5
0.5,4.5
1,9
1.5,13.5
0,18
18
0.04
0.04
0.04
0.08
0.51
1.3
34
-0.51
-1.6
-1.3
-3.4
4.95
9.95
14.95
5
10
20
100
1
2.6
6.8
-1
-3.2
-2.6
-6.8
jJA
rnA
0
0.05
0
0
5
10
15
0.05
0.05
1.5
3
4
3.5
characteristics.
V
V
Fig. 9 - Typical trsnsition time as a function of
11
±1
Fig. 8 - Minimum output high (source) current
load capacitance.
±10- 5
±0.1
IJA
Dimensions and Pad Layout for CD4024BH.
Dimensions and Pad Layout for CD4020BH. Dimensions and
pad layout for CD4040BH are identical.
Dimensions in parentheses are in millimeters and
afe derived from the basic inch dimensions as indicated. Grid graduations are in mils (10- 3 inch).
The photographs and dimensions of each COS/MOS
chip represent a chip when it is part of the wafer.
When the wafer is cut into chips. the cleavage
angles are 57° instead of 90° with respect to the
face of the chip. Therefore. the isolated chip is
actually 7 mils (0. 17 mm) larger in both dimensions.
116 ____________________________________________________________________
CD4020B, CD4024B, CD4040B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 250 C. Input t r • tf = 20 ns.
CL =50pF. RL = 200kn
LIMITS
CHARACTERISTIC
TEST
CONDITIONS
VDD
(V)
UNITS
Min.
Typ.
Max.
360
I nput·Pulse Operation
Propagation Delay Ti me. I/> to
01 Out; tpHL. tpLH
°n to On+ 1;
tpHL' tpLH
Transition Time.
tTHL' tTLH
5
-
180
10
-
80
160
15
65
130
5
-
100
200
10
-
40
80
15
-
30
60
5
-
100
200
10
..,.
50
100
40
80
140
15
-
70
10
30
60
15
-
20
40
5
Minimum Input·Pulse
Width. tw
r-210
r--;-s-
Input·Pulse Rise or Fall
Time. trl/>' ttl/>
Maximum Input·Pulse
Frequency. tl/>
LOAD CAPACITANCE lell-pF
ns
Fig. 10 - Typical propagation delay time as a
function of load capacitance
'to
ns
0 71.
10'2 AMBIENT TEMPERATURE ITA lo25"C
V
ns
Unlimited
IlS
5
3.5
7
-
10
8
16
-
15
12
24
-
-
5
7.5
5
-
140
280
10
-
60
120
50
100
100
40
200
80
30
60
5
-
175
350
10
-
75
150
15
-
50
100
Any Input
Input Capacitance. CI
ns
2.
MHz
468'02.
468'02.2
4 &810, 2.
468 10.2
INPUT PULSE FREQUENCY U",I- kHI
468. 05
92.C$-30157
Fig. 11 - Typical dynamic power dissipation as a
function of input pulse frequency for
pF
CD4020B.
Reset Operation
Propagation Delay
Time. tpHL
15
5
10
Minimum Reset Pulse
Width. tw
15
Reset Removal Time.
tREM
ns
ns
ns
Fig. 12 - Dynamic power dissipation test circuit
for CD4020B.
INPUTS
INPUO'
Voo
NOTE:
o
Vss
MEASURE INPUTS
SEQUENTIALLY,
TO BOTH Voo AND Vss'
CONNECT ALL UNUSEO
1NPUTS TO EITHER
v,,
VOO OR VSS'
92CS-21441AI
V,,
92eS-2UOIAI
Fig. 13 - Quiescent device
current test circuit.
Fig. 14 - Input voltage test circuits.
Fig. 15 - Input current test circuit.
____________________________________________________________________ 117
CD4026B, CD4033B Types
COS/MaS
Decade Counters/Dividers
"DO
tLOtl(
High-Voltage Types (20-Volt Rating)
With Decoded 7-Segment Display Outputs and:
Display Enable - CD4026B
Ripple Blank~ng - CD4033B
: :}!~
tLOCI(
.
...
T.
IMHIBIT
•
"
Features:
The RCA-CD4026B and CD4033B each consist of a 5'stage Johnson decade counter
and an output decoder which converts the
Johnson code to a 7·segment decoded out·
put for driving one stage in a numerical
display.
These devices are particularly advantageous
in display applications where low power
dissipation andlor low package count are
important.
Inputs common to both types are CLOCK,
RESET, & CLOCK INHIBIT; common
outputs are CARRY OUT and the seven
decoded outputs (a, b, c, d, e, f, g). Addi·
tional inputs and outputs for the CD4026B
include DISPLAY ENABLE input and
DISPLAY ENABLE and UNGATED "C·
SEGMENT" outputs. Signals peculiar to the
CD4033B are RIPPLE·BLANKING INPUT
AND LAMP TEST INPUT and a RIPPLE·
BLANKING OUTPUT.
A high RESET signal clears the decade
counter to its zero count. The counter is
advanced one count at the positive clock
signal transition if the CLOCK INHIBIT
signal is low. Counter advancement via the
clock line is inhibited when the CLOCK
INHIBITsignal is high. The CLOCK INHI·
BIT signal can be used as a· negative·edge
clock if the clock line is held high. Antilock
gating is provided on the JOHNSON counter,
thus assuring proper counting sequence. The
CAR RY·OUT (Cllll tl signal completes one
cycle every ten CLOCK INPUT cycles and
is used to clock the succeeding decade di·
rectly in. a multi·decade counting chain.
The seven decoded outputs (a,b, c, d, ll, f, g)
illuminate the proper segments in a seven
tI
"
RUET
8~
S CMR't'OUT
• Counter and 7·segment decoding in one package
• Easily interfaced with 7·segment display types
• Fully static counter operation: DC to 6 MHz (typ.)
at VDD=10 V
• Ideal for low·power displays
• Display enable output (CD4026B)
• "Ripple blanking" and lamp test (CD4033B)
• 100% tested for quiescent current at 20 V
• Stendardized, symmetrical output
characteristics
• 5-V, 10-V, and· 15·V parametric ratings
• Schmitt·triggered clock inputs
•. Meets all requirements of JEDEC Tentetive
Standard No. 13A, "Standard Specifications
for Description of 'B' Series CMOS DeviCes"
Applications
•
DISPLAY
..
DISPUT
EMABLE
ON
lNAILIE
OUT
Utl ....'£D·C·
SEGM'NT
Vss
I2CS-Z!1018AI
CD4026B
FUNCTIONAL DIAGRAM
CLOCK
12 •
~
0
.
" "til
"
RESET
:>
• .."""
CLOCIC
INHIBIT
• Decade counting 7-segment decimal
display
• Frequency division 7·segment decimal
displays
• Clocks, watches, timers
(e.g. +60, + 60, + 12 counter/display)
• Counter/display driver for meter
applications
I!!
l-
I> c
I.
LAMP
TEST
& CARRY
OUT
4
RIPPLE
BLK.
RIPPLE
BLIC.
OUT.
I.
Vso
CD4033B
FUNCTIONAL DIAGRAM
segment display device used for reptesenting
the decilnal numbers 0 to 9. The 7·segment
outputs go high on selection in the CD4033B;
in the CD4026B these outputs go high only
when the DISPLAY ENABLE IN is high.
TERMINAL DIAGRAMS
Top View
CLOCK
CI..OCK INHIBIT
DISPLAY ENABLE IN
DISPLAY ENABLE OUT
CARRY OUT
I.
••
,.I.
,.
I.
,
MAXIMUM RATINGS, Absolute·Maximum Values:
VDD
RESET
UNGATEO ~C· SEGMENT OUT
I.
"
10
Vss
9
DC SUPPLY·VOLTAGE RANGE. (VDDI
(Voltages referenced to VSS Terminal)
-0.510 '20 V
-0.510 VDD '0.5 V
±10mA
INPUT VOLTAGE RANGE. ALL INPUTS
DC INPUT CURRENT. ANY ONE INPUT
POWER DISSIPATION PER PACKAGE (POl:
For TA • -40 to '60 0 C (PACKAGE TYPE EI
. . . . . . . •.
500mW
For TA • '60 to 'S50C (PACKAGE TYPE EI
Derate Linearly at 12 mWflC to 200 mW
For TA • -55 to '1000 C (PACKAGE TYPES D.F I
. . . . . . . ..
500mW
For TA· '100 10 '125 0 C (PACKAGE TYPES O. F I
Derate Linearly at 12 mW/oC to 200 mW
OEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA • FULL PACKAGE·TEMPERATURE RA·NGE (All Package Types)
100mW
OPERATING·TEMPERATURE RANGE (TA):
PACKAGE TYPES D. F. H
-551o +125 0C
...... .
PACKAGE TYPE E.
-4010 +B5 0C
STORAGE TEMPERATURE RANGE (Tstg )
-65 10 + 150°C
LEAD TEMPERATURE (DURING SOLOERING):
At distance 1116 ± 1132 inch (1.59 ± 0.79 mml from case for"lD s max.
92CS-24469RI
CD4026B
Top View
CLOCK
CLOCK INHIBIT
RIPPLE BLANKING IN
RIPPLE BLANKING OUT
CARRY OUT
,
t
Vss
I.
•
,.
I.
,.
I.
VDD
RESET
LAMP TEST
"
"
10
9
92CS-2441~RI
CD4033B
118 ________________________________________________________________________
CD4026B, CD4033B Types
CD4026B
When the DISPLAY ENABLE IN is low the
seven decoded outputs are forced low regardless of the state of the counter. Activation of' the display only when required
results in significant power savings. This
system also facilitates implementation of
display·chara~ter multiplexing.
The CARRY OUT and UN GATED "C·
SEGMENT" signals are not gated by the
DISPLAY ENABLE and therefore are avail·
able continuously. This feature is are·
quirement in implementation of certain di·
vider functions such as divide·by·60 and
divide·by·12.
RECOMMENDED OPERATING CONDITIONS
For maximum reliability. nominal operating conditions should be selected so that operation is
always within the fol/owing ranges'
CHARACTERISTIC
LIMITS
VDD
(V)
MIN.
Supply.voltage Range (For TA = Full Package
Temperature Range)
Clock Input Frequency,
Clock Pulse Width,
fCL
tOCL
Clock Rise and Fall Time,
Clock Inhibit Set Up Time,
Reset Pulse Width,
t,.CL' ttCL
tsu
tw
Reset Removal Time
UNITS
MAX.
3
18
V
-
2.5
5.5
8
MHz
5
10
15
-
5
10
15
220
100
80
-
5
10
15
-
-
Unlimited
5
10
15
200
50
30
5
10
15
200
100
50
5
10
15
30
15
10
-
-
-
ns
-
-
STATIC ELECTRICAL CHARACTERISTICS
LIMITS AT INDICATED TEMPERATURES (OC)
Values at -55, +25, +125 Apply to D;F ,H Packages
Values at -40, +25, +85 Apply to E Package
UNITS
+25
VDD
Typ. Max.
+85
+125 Min.
(V) -55 -40
5
150
150
0.04
5
5
5
0.04
10
300
10
300
10
10
I'A
20
0.04
600
600
15
20
20
100
0.08
3000
3000
100
100
20
1
0.42
0.36 0.51
5
0.64 0.61
CONDITIONS
CHARACTER·
ISTIC
Vo
(V)
VIN
(V)
-
IDD Max.
-
0,5
0,10
0,15
0,20
Output Low
(Sink) Current
IOL Min.
0.4
0.5
0,5
0,10
1.5
4.6
0,15
0,5
2.5
9.5
13.5
-
0,5
0,10
0,15
0,5
5
0:05
-
-
0,10
0,15
0,5
0,10
Quiescent Device
Current,
Output High
(Source)
Current,
IOH Min.
Output Voltage:
Low·Level,
VOL Max.
Output Voltage:
High·Level,
VOH Min.
Input Low
Voltage,
VIL Max.
Input High
Voltage,
VIH Min.
Input Current
liN Max.
-
10
15
5
5
10
15
-
0,15
10
15
5
10
15
0.5,4.5
-
5
1,9
1.5,13.S
0.5,4.5
1,9
-
10
15
1.S,13.S
-
5
10
15
-
0,18
18
-
-
1.3
0.9
2.4
3.4
-0.36 -0.51
-1.15 -1.6
-0.9 -1.3
2.6
-
6.8
-1
-3.2
-2.6
-
-2.4
-3.4
-6.~
-
a
a
a
0.05
0.05
0.05
-
4.95
9.95
14.95
4.95
9.95
14.95
5
10
15
1.5
1.6
4.2
4
-0.64 -0.61
-2
-1.8
-1.6 -1.5
-4
-4.2
1.1
2.8
-0.42
-1.3
-1.1
-2.8
1.5
3
4
±0.1
±0.1
-
-
3.5
7
3.5
7
-
11
11
-
±1
±1
-
±10-5
-
rnA
-
0.05
0.05
V
1.5
3
4
-
V
±0.1
CD4033B
The CD4033B has provision's for automatic
blanking of the non·significant zeros in a
multi·digit decimal number which results in
an easily readable display consistent with
normal writing practice. For example, the
number 0050.0700 in an eight digit display
would be displayed as SO.07. Zero suppression on the integer side is obtained by connecting the RBI terminal of the CD4033B
associated with the most significant digit in
the display to a low-level voltage and can·
necting the RBO terminal of that stage to
the RBI terminal of the CD4033B in the
next·lower significant position in the display. This procedure is continued for each
succeeding CD4033B on the integer side of
the display.
On the fraction side of the display the RBI
of the CD4033B associated with the least
significant bit is connected to a low·level
voltage and the RBO of that CD4033B is
connected to the RBI terminal of the
CD4033B in the next' more·significant·bit
position. Again, this procedure is continued
for all CD4033B's on the fraction side of the
display.
I n a purely fractional number the zero
immediately preceding the decimal point can
be displayed by connecting the RBI of that
stage to a high level voltage linstead of to the
RBO of the next more·significant-stage).
For example:
optional zero -> 0.7346.
Likewise, the zero in a number such as 763.0
can be displayed by connecting the RBI of
the CD4033B associated with it to a highlevel'voltage.
Ripple blanking of non'significant zeros
provides an appreciable savings in display
power.
The CD4033B has a LAMP TEST input
which, when connected to a high·level volt·
age, overrides normal decoder operation and
enables a check to be made on possible
display malfunctions by putting the seven
outputs in the high state.
The CD4026B- and CD4033B-series types
are supplied in 16-lead hermetic dual-in-line
ceramic packages (D and F suffixes), 16lead dual-in-line plastic packages (E suffix),
16-lead ceramic flat packages (K suffix).
and in chip form (H suffix),
/lA
_______________________________________________________________________ 119
CD4026B, CD4033B Types
5
COUT
(CLOCK+10I
011121'
COUNT
CL
41"
017101' 01' 101"
RESET
CLOCK
INHIBIT
DISPLAV
.
ENABLE IN
DISPLAY
ENABLE OUT
.
CLOCK
*
CLOCK
D
CL
~'
~
•
INHIBIT 2
CARRY
OUT
UNGATED
"e· SEG.
*~~S:B~l
O'-------------..,---i >---~------_<1
IN
16
voca
GN00 8
It
ALL INPUTS PROTECTED
BY CDS/MOS INPUT
PROTECTION NETWORK
-n
4
~=~-;:t=~=d:~;=::f=~-:j
~
DISPLAY
ENABLE
OUT
Fig. 3 - CD40268 timing diagram.
CLOCK nn In
----
SEGMENT
DESIGNATIONS
VOO
r, nn In r, nn In r, n n n
~~i~--------~nL----------
Vss
f~rt
_________-.Jr----1L...._ _ _ _ __
R O I - - - - - - - - - - - - - - C_ _ _ __
Fig. 1 - CD40268 logic diagram.
COUT
(CLOCK-:-IOI----"L_ _---'r----'-_ _ _I " SEGMENT
DESIGNATIONS
'~----------------~LI<-
.00 ________________________________
..
~
012345618901845618912
92CS-29084
Fig. 4 - CD40338 timing diBgram.
*~
~
CLOCK
ff
.CLOCK
INHIBIT 2
CL
.
*RBIO'---------------L--"
16
VODO
ALL INPUTS PROTECTED
BY COS/MOS INPUT
GNDQa
PROTECTION NETWORK.
n
____
~
o
CL_=
RBO
_ Q
R
.
VOO
CL
CL
CL
-1...r>--
Ci:
Vss
Fig. 5 - Detail of typicBI flip-flop stage for both types.
Fig. 2 - CD40338 logic diagram.
DRAIN-TO-SOURCE VOLTAGE IVDSI-V
·DRAIN-TO-SOURCE VOlTAGE lVos)-V
Fig. 6 - Typical n-channel output low (sink)
current characteristics.
DRAIN-'"Q-',DU',CE VOLTAGE
Fig. 7 - Minimum
n~hannel
output low (sink)
current characteristics.
Fig. 8 - TypicBI p-channel output high (source)
current characteristics.
120 __________________________________________________________________
CD4026B, CD4033B Types
DRAIN-lO-SOURCE VOLTAGE (VoSl-V
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25"C, Input t" tf= 20 ns,
CL =50pF, RL =200kn
TEST
CONDITIONS
CHARACTERISTIC
LIMITS
UNITS
VDD
!VI Min. Typ. Max.
CLOCKED OPERATION
Propagation Delay Time;
Carry·Out Line
5
10
15
tpLH. tpHL
5
10
15
Decode Outlines
Transition Time;
tTHL' tTLH
Carry·Out Line
Maximum Clock Input Frequency, fCLA
Min. Clock Pulse Width.
tw
-
-
5
10
15
-
5
10
15
2.5
5.5
8
5
10
15
-
,
250 500
100 200
75 150
350 700
125 250
90 180
Fig. 9 - Minimum p-channe/ output high (source)
ns
AMBIENT TEMPERATURE (TAl- 25-C
100 200
50 100
25 50
-
5
11
16
current characteristics.
MHz
-
110 220
50 100
40 80
10V
20
Clock and Clock Inhibit Rise or Fall Time;
r2I ~~
trCL. tfCL
Average Input Capacitance. CIN
-
Any Input
40
60
LOAD CAPACITANCE ICL.l-pF
Unlimited
ns
80
'ZCS-31705
Fig. 10 - Typical propagation delay time as a
function of load capacitance for
decoded outputs.
-
5
7
-
275
120
80
300
125
90
550
240
160
pF
RESET OPERATION
Propagation Delay Time;
To Carry·Out Line.
To Decode Out Lines,
Min. Reset Pulse Width.
tpLH
tpHL. tpLH
tw
Min. Reset Removal Time
5
10
15
5
10
15
-
5
10
15
-
5
10
15
-
-
600
250
180
100 120
50 100
25 50
0
0
0
30
15
10
ns
LOAD CAPACITANCE (CLI-pF
Fig. 11 - Typical propagation delay time as a
function of load capacitance for
carry-out outputs.
.. Measured with respect to carry~ut line.
I
SUPPLY VOLTAGE IVool-V
92:CS-3I703
Fig. 12 - Typical maximum clock input-frequency
as a function of supply voltage.
______________________________________________________________ 121
CD4026B, CD4033B Types
VDD
TEST PEFORMED WITH
THE FOLLOWING SEQUENCE OF
"I"s AND "O"s AT EACH INPUT
51 52 53 54 55
o
o
0
I
0
0
o
0
I
0
o
I
I
I
0
0
* DISCONNECT
PIN 14
C040268
FOR
92CS-31706
<'
4 6~O
"
468'0 3 <'
-468'022
468,04 <'
4
CLOCK IN,,"UT-FREQUENCY ['elI-MHz
selo !:!
Fig. 15 - Quiescent device current.
92CS-31101
Fig. 13 - Typical power dissipation as a function
of clock input frequency.
ncs- 31702
Fig. 14 - Dynamic power dissipation test circuit
for CD4033B.
INTERFACING THE CD4026B AND CD4033B WITH COMMERCIALLY AVAILABLE
LIGHT EMITTING DIODE DISPLAYS
VDD
MONSANTO MAN 3
OR EQUIVALENT
(LOW POWER)
CD4026BI
CLOCK
INHIBIT
B
"DD
CD4033B
~
-
r
l
I
1
R
I
I
VDD:
~
"B
1
1
1
I
:
1
1
I
!.
A
+:
I
I,
1
I
I
I
CLOCK
DD
INHIBIT
Yoo
RESET
:
1
I
~
~~~~~oDP~g:
Yss
IB~O.4mA
IF 2: 12 mA/Seg.IIOOo;"OUTYCYCLE)
ILEO
WHERE VF: FORWARD DROP ACROSS DIODE
1
Voo OR Vss'
Pdc (MIN) 2: 30
VCE (SAT! ~ 0.5 V
R= VOO-VCElsOII-VFILEDI
92CS-3170B
20
MEASURE INPUTS
SEaUENTIALLY,
TO 80TH Voo ANO Vss'
CONNECT ALL UNUSED
INPUTS TO EITHER
o ~
1
G
1 N P UV
O S NOTE
~
1
I
I
L ____
WHERE Vp' INPUT PULSE
"F:
I
:
R=Vp-VSE-VF (LED)
ILEO
Fig. 16 - Input voltage.
'"AN,--l
:
G
VOO=::3,5V
IFRl5mA/SEGMENT
100% DUTY CYCLE
OR EOUIVALENT
OR. EQUIVALENT
A
7
SEGMENTS
RESET
92CS-27441RI
MONSANTO MAN I
1/7CA3082
Vss
92CS-31709
Fig. 17 - Input current.
60
I
88 -96
12.235 - 2.438)
0-
i
~(C)IOr~254)
104-112
12.642 - 2.8451
92C'3-31100RI
Dimensions and pad layout for CD40268.
DimenSIOns In parentheses are In millimeters and
are deflved from the baSIC Inch dimenSions as in·
dlcared. God graduations are In mils (10-- 3 inch).
.438)
Dimensions and pad fayout for CD4033B.
The photographs and dimensions of each COS/MOS
chip represent a chip when it is part of the wafer.
When the w~fer is cij t int~ chips, the cleavage
ang'es are 57 instead of 90 with respect to the
face of the chip. ,Therefore, the isolated chip is
actually 7 mils (0. 17 mm) larger in both dimensions.
122 _______________________________________________________________________
CD4026B, CD4033B Types
INTERFACING THE CD4026B AND CD4033B WITH COMMERCIALLY AVAILABLE
7·SEGMENT DISPLAY DEVICES*
(Refer to RCA Application Note ICAN·6733 for detailed interfacing information)
VT
!
VDD
IT
INCANDESCENT READOUTS
RCA Numill'OlJo DR2I1OI1 Srril."
CLOCK
CD402IBf
CD40338
INHIBIT
n:SE REQlIIREMF:STS:
\'1' :I.S-5\'
...." [
-=-
ASSUMED
VT
CD4OollU8
TRANSISTOR
CHARACTERISTICS
8dc (min,) i!:
-=-
VCE(SQI.l~
V,,
f
O.SY
YT=l.5 Y TO 6 V
: VOD '" BV (min.)
":"
vee" lOV (min.)
Vo"O" S 2~
IT =.mA 'Illin.)
2S
'8" ImA (min.)
CD4049UB
IT" 24mAfmin.)
~vcc "
lOY (min,)
Vo"O" S 0.6 V
PISl.ln:s l: VT
92CS~31710
LOW VOLTAGE VACUUM FLUORESCENT
READOUTS
1. Tung-Sol OIGIVAC S/G t Type DT1704A or DT1705C
2. Nippon Electric (NEC); Type DG12E or 1..0915
TUBE REQUIREMENTS: l00t0300pA/segment
at tube voltages of 12 V to 25 V depending on
required brightness Filament requirement 45 rnA
at 1.6 V, 8C or dc_
t (Trademark) Wagner Electric Co.
92C5-31711
_______________________________________________________________________ 123
CD4027B Types
COS/MOS Dual J-K
:e~:~~::~etcapability
Master-Slave Flip-Flop ·1· Static flip-flop operation -
retains state indefinitely
with clock level either "high" or "low"
High-Voltage Types (20-Volt Rating)
The RCA-CD4027B is a single monolithic
chip integrated circuit containing two identical complementary-symmetry J-K masterslave flip-f1ops_
Each flip-flop has provisions for individual J, K, Set, Reset, and
Clock input signals_
Buffered Q and Q
• Medium speed operation - 16 MHz (typ_) clock toggle
•
•
•
Maximum input current of 1 I1A at 18 V over
full package-temperature range; 100 nA at
18 V and 25 0 C
signals are provided as outputs. This inputoutput arrangement provides for compatible
'operation with the RCA,CD4013B dual Dtype fl ip-flop,
The CD4027B is useful in performing control, register, and toggle functions_ Logic
levels present at the J and K inputs along
with internal self-steering control the state
of each flip-flop; changes in the flip-flop
state are synchronous with the positivegoing transition of the clock pulse, Set and
reset functions are independent of the clock
and are initiated when a high level signal is
present at either the Set or Reset input,
rateat 10V
Standardized symmetrical output characteristics
100% tested for quiescent current at 20 V '
Noise margin (over full packagetemperature range):
1 Vat VDD ~ 5 V
2 Vat VDD ~ 10 V
2.5 Vat VDD ~ 15 V
• 5-V, 10·V, and 15·V parametric ratings
• Meets all requirements of JEDEC Tentative
Standard No. 13A, "Standard Specifications
for Description of 'B' Series CMOS Devices"
•
Functional Diagram
Applica tions:
•
Registers, counters, control circuits
The CD40278 types are supplied in 16-lead
hermetic dual-in-line ceramic packages (D
and F suffixes). 16-lead dual-in-line plastic
packages (E suffix) ,16-lead ceramic fiat
packages (K suffix). and in chip form (H
suffix)"
02
I.
2
ii2
MAXIMUM RATINGS. Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, IVDDI
. -0,5 ta +20 V
(Voltages refer~nced to VSS Terminal)
-0,5 ta V DD +0.5 V
INPUT VOLTAGE RANGE, ALL INPUTS
±10mA
DC INPUT CURRENT, ANY ONE INPUT
POWER DISSIPATION PoER PACKAGE IPDI:
,
.
'
,
,
,
,
"
500
mW
Far T A = -40 ta +600 C IPACKAGE TYPE EI
Derate Linearly at 12 mW/oC to 200 mW
Far T A ~ +60 ta +85 IPACKAGE TYPE EI, ,
, , , , ' , , .,
500 mW
Far T A = -55 ta +100 C IPACKAGETYPES 0, FI
Derate Linearly at 12 mW/ oC to 200 mW
Far T A = +100 ta +125°C IPACKAGE TYPES 0, FI
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR T A = FULL PACKAGE-TEMPERATURE RANGE IAII Package Types)
100mW
OPERATING-TEMPERATURE RANGE IT AI:
PACKAGE TYPES 0, F, H
-55 ta +125 0 C
PACKAGE TYPE E
-40 ta +85 0 C
-65 ta +150 0 C
STORAGE TEMPERATURE RANGE IT" I ' ,
LEAD TEMPERATURE lOURING SOLD~RINGI:
At distance 1/16 ± 1/32 inch 11.59 ± 0,79 mml fram case far lOs max,
eLOCt< 2
RESET 2
v
"01
J2
SET 2
.,
CLOCK I
RESETI
"
la
Vss
JI
SET I
TOP VIEW
92CS-2<1410
c;
*4(1210-+------1
01
13
12
.2
DD
I.
"
I.
TERMINAL ASSIGNMENT
)0---;---------------..,
*
PRESENT ST.\TE
INPUTS
OUTPUT
J
6 II 0 J ~--,---'--.-/
J
K
S
R
Q
NEXT STATE
OUTPUTS
CL&
Q
-a-
_NO CHANGE
lC
r;-lCro,rc-r-lH--'-+-------l
X
*
riDD
SET
7(9)0------1
CL
CL
t
3(13)~
*
C~OCK
f"....
t /'. . .
*AcLINM
PROTECTED BY
COS/MOS PROTECTION
NETWORK
Vss
Fig. 1 - Logic diagram and truth table for CD40278 (one of two identical J·K flip flops).
124
I
0
LOGIC I-HIGH LEVEL
lOGIC O'lOW LEVEL
92CM- 27551RI
CD40278 Types
RECOMMENDED OPERATING CONDITIONS at T A = 250 C, Except as Noted.
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges:
CHARACTERISTIC
VDD
(V)
Supply· Voltage Range
(For TA = Full Package Temperature Range)
Data Setup Time
ts
Clock Pulse Width
tw
Clock Input Frequency (Toggle Mode)
Clock Rise or Fall Time
LIMITS
All
Packages
Max.
Min.
fCl
trCl •. tfCl
Set or Reset Pulse Width
-
3
18
5
10
15
5
10
15
5
10
15
5
10
15
200
75
50
140
60
40
-
-
3.5
8
12
15
4
1
5
10
15
180
80
50
-
tw
UNITS
V
I
DRAIN-TO-SOURCE VOLTAGE (Vosl-V
ns
-
ns
-
dc
MHz
/.IS
ns
• If more than one unit is cascaded in a parallel clocked operation, trCl should be made less
than or equal to the sum of the fixed propagation delay time at 15 pF and the transition
time of the output driving stage for the estimated capacitive load.
DRAIN-lO-SOURCE VOL.TAGE IYosl-V
Fig.2 - Typical output low (sink)
current characteristics.
Fig.3 - Minimum output low (sink)
current characteristics.
DRAIN-fO-SOURCE VOLTAGE (Vos)-V
I
I
10 3
10~
10$
10 6
INPUT FREQUENCY(lII-Hz
• 'J2CS-Z4~ZO"3
Fig.4 - Typical output high (source)
Fig.5 - Minimum o'utput high (source)
current characteristics.
current characteristics.
V~NPU(JS
VDO :~:~U'E INPUTS
o ~
SEQUENTIALLY,
TO aoTH YDO AND Vss
CONNECT ALL UNUSm
Vss
INPUTS
VSS
11)
INPUTS
INPUTOVDOOUTPUTS
o
V55
V,H
'--
~
l
Y~L
EITHER
YooORVss ·
Fig.6 - Typical power dissipation vs. frequency.
Vss
NOTE:
TEST ANY ONE INPUT,
WITH OTHER INPUTS AT
Yoo OR Yss·
V55
'il2CS-2140IRI
Fig.7 - Input current test circuit.
Fig.8 - Input·voltage test circuit.
Fig.9 - Quiescent device current test circuit.
_____________________________________________________________________ 125
.CD4027B Types
STATIC ELECTRICAL CHARACTERISTICS
CHAAACTERISTIC
Quiescent
Device
Current
100 Max.
Output Low
(Sink)
Current,
CONDITIONS
Vo
(V)
VIN VDD
(V)
(V)
LIMITS AT INDICATED TEMPERATURES (OC)
Values at -55,+25,+125 AIIPly to D,F,H Plcgs.
Values at -40,+25,+85 Apply to E Plcgs.
UNITS
+25
Typ_ Max.
-55
+125 Min.
-40 +85
-
-
0,5
0,10
0.15
0,20
5
10
15
20
0.4
0.5
1.5
4.6
2.5
9.5
13.5
0,5
0,10
0,15
0,5
0.5
0,10
0,15
5
10
15
5
5
10
15
-
0,5
0,10
0,15
5
10
15
0.05
0.05
0.05
-
0
0
0
0.05
0.05
0.05
-
0,5
0,10
0,15
5
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5
10
15
-
Input Low
Voltage,
VIL Max.
0.5,4.5
1,9
1.5,13.5
-
5
10
15
1.5
3
4
-
1.5
3
4
Input High
Voltage,
0.5,4.5
1,9
1.5,13.5
-
-
5
10
15
3.5
7
11
3.5
7
11
-
-
0,18
18
'-OL Min.
Output High
(Source)
Current,
IOH Min.
Output Voltage:
Low-Level,
VOL Max.
Output Voltage:
High- Level,
VOH Min.
VIH Min.
Input
Current,
liN Max.
-
-
-
1
2
4
20
1
2
4
20
30
60
120
600
30
60
120
600
-
0.64 0.61
0.42 0.36 0.51
1.6
1.5
1.1
0.9
1.3
4.2
4
2.8
2.4
3.4
-0.64 -0.61 -0.42 -0.36 -0.51
-2 -1.8 -1.3 -1.15 -1.6
-1.6 -1.5 -1.1 -0.9 -1.3
-4.2
-4
-2.8 -2.4 -3.4
±0.1
±0.1
±1
±1
-
0.02
0.02
0.02
0.04
1
2
4
20
1
2.6
6.8
-1
-3.2
-2.6
-6_8
-
. -=-
IJA
rnA
-
-
V
V
-
±10-5 ±0.1
IJA
-
Dimensions in millimeters are derived from the basic inch dimensions
as indicBted. Grid graduations are in mils (10- 3 ).
The photographs and dimensions of each COS/MOS
chip represent a chip when it is part of the wafer.
When the wafer is cut into chips, the cleavage
angles are 57° instead of 90° with respect to the
face of the chip. Therefore, the isolated chip is
actually 7 mils (0. 17 mm) larger in both dimensions.
I
.-10
""to,IOI-O .•• 4)
1o>-------I •. OO.,:'~' ..I--------_t
Dimensions and Pad Layout for CD4027BH
_-1?M4
126 ________________________________________
~------------------------
CD4027B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at T A =250 C; Input t" tj'
CL = 50 pF, RL = 200 kn
CHARACTERISTIC
VDD
(V)
Propagation Delay Time:
Clock to Q or Q Outputs
5
10
15
5
10
15
5
10
15
5
10
15
tpHL. tPLH
Set to Q or Reset to Q tplH
Set to Q or Reset to Q tpHL
Transition Time
tTHL. tTLH
Maximum Clock Input
Frequency# (Toggle Mode)
fCl
Minimum Clock Pulse Width tw
Minimum Set or Reset Pulse
Width
tw
Minimum Data Setup Time ts
Clock Input Rise or Fall Time
trCL. ttCl
Input Capacitanoe
#
Input t,.
CI
tt = 5 ns.
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
=20 ns,
LIMITS
All Packages
Typ.
Min.
Max.
-
-
150
65
45
150
65
45
200
85
60
100
50
40
3.5
8
12
7
-
16
24
-
-
70
30
20
90
40
25
100
35
25
-
-
140
60
40
180
80
50
200
75
50
15
4
1
-
5
7.5
-
-
-
-
-
-
300
.130
90
300
130
90
400
170
120
200
100
80
UNITS
ns
ns
Fig. to
-
Tvpical propagation delay time vs.
load capacitance (CLOCK or SET
to 0, CLOCK or RESET to Q.
ns
ns
MHz
ns
Fig. 11 - Typical propagation delaY.lime vs.
load capacitance (SET to Q or
RESET to OJ.
ns
ns
AMBIENT TEMPERATURE (TA'- 2.5-C
t r ltf- 5nl
CL -SOpF
30
ps,
25
pF
10
5
10
15
SUPPLY VOLTAGE (VOOI-V
92CS-2639lR2
F;g.12- Typical maximum clock frequency vs.
supply voltage (toggle modeJ.
______________________________________________________________ 127
CD4028B Types
COS/MaS
BCD-to-Decimal Decoder
High-Voltage Types (20-Volt Rating)
The RCA-CD4028B, types are BCD·todecimal or binary·to·octal decoders consist·
ing of buffering on all 4 inputs, decoding·
logic gates, and' 10 output buffers, A BCD
code applied to the four inputs, A to D,
results in a high level at the selected one of
10 decimal decoded outputs. Similarly, a
3·bit binary code applied to inputs A through
C is decoded in octal code at output 0 to 7
if D = "0". High drive capability is provided
at all outputs to enhance de and dynamic
performance in high fan-out applications,
The CD4028B-Series types are supplied in
16-lead hermetic dual-in-line ceramic packages (D and F suffixes). 16-lead dual-in-line
plastic packages (E suffix), 16-lead ceramic
flat packages (K suffix), and in chip form (H
suffix),
Features:
• BCD-to-decimal decoding or binary-to-octal decoding
• High decoded output drive capability
• "Positive logic" inputs and outputs ....
.•... decoded outputs go high on selection
• Medium-speed operation ....
tpHL, tpLH = 80 ns (typ.) @ VDD = 10 V
• Standardized, symmetrical output characteristics
• 100% tested for quiescent current at 20 V
Voo
BuFFEREO
~~~B~::il.l·
BCD
'0
ii"
I
""" I
,~oc",
DECODED
~,u;:~~s
a:
III Ill> z_
1-0( 1->
W'
_0(
~o( )t'l'
-z IDa: ~
X xa:
'11,.ID .tCl W wCl <~
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
3
2
7
6
4
5
15
14
12
13
8
9
11
10
OUTPUT NUMBER
o
1 2 3 4 5 6 7 8 9101112131415
o0
0
1
2
3
4
5
6
7
8
9
0
3
4
1
2
3
4
1
2
9
5
6
7
8
9
5
6
8
7
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
101 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2 0 0 10000.000000000
00010 o 0 0 0 0 0 0 0 0 0 0
o 0'0 0 1 0 0 0 0 0 0 0 0 000
3 0 0 0 0 0 1 o 0 0 0 0 o 0 0 0 0
4 0 0 000 0 1 o 0 0 0 o 0 0 0 0
o 0 0 o 0 o 0 1 000 o 0 0 0 0
0 o 0 0 0 0 0 0 1 o 0 0 o 0 0 0
5 o 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
6 0 0 0 0 0 0 0 o 0 0 1 0 0 0 0 0
o 0 0 0 0 0 000 0 o 1 o 0 0 0
0 o 0 0 0 0 o 0 0 o 0 0 1 0 o 0
7 0 o 0 0 0 0 o 0 0 000 0 1 o 0
8 0 o 0 0 0 o 0 0 000 000 1 0
9 0 o 0 0 0 000 0 0 0 0 000 1
92CS-24UtR2
Fig. 6 - Minimum output high (source)
current characteristics.
101 AMBIENT TEMPERATUREITAI-25'"C
V~~NP(JUS :~:~URE INPUTS
IICS-2M12
Fig.
7 -.
vDO
o ~
SEQUENTIALLY,
Vss
Typical dynamic p~Wf!r dissipation as 8 function of input
frequency.
'
TO BOTH "'DO ANDVss·
CONNECT ALL UNUSED
INPUTS 10 EITHER
Voo ORVSS ·
Vss
TYPICAL APPLICATIONS
Fig. 9 - Input current test circuit.
INPUTS
Fig.
8 - Typical transition time as a
function of load capacitance.
INPUTOVIX)OUTPU.TS
V,H
'--
~
~
v~
VOD
NOTE
.~~SJN~~~~OMBINATION
Vss
.fig.
t1-
Input voltage test circuit.
OD
Fig. 13 - Code conversion circuit.
v
INPUTS
o
V55
Fig. 10 - Dynamic power dissipation
test circuit.
Fig. 12 - Ouiescent device current
test circuit.
The circuit shown in Fig.l3 converts any 4bit code to a decimal or hexadecimal code.
Table 2 shows a number of codes and the
decimal or hexadecimal number in these
codes which must be applied to the input
terminals of the CD40288 to select a particular output. For example: in order to get a
high on output No_ 8 the input must be
either an 8 expressed in 4-8it Binary code, a
15 expressed in 4-Bit Gray code, or a 5 expressed in Excess-3 code_
130 ____________________________________________________________________
CD4028B Types
8 ']
o
~
C
6
VT
--,{ '""" l
BCD
A(Trademark) Burroughs Corp.
Fig. 14 - Neon readout (Nixie Tube·) display application.
Fig. 15 - B-bit binary to 1-of-64 address decoder.
CD4028BH
DIMENSIONS AND PAD LAYOUT
The phorogrilphsiJlJddimelJS/ons
Dimensions in parentheses are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10- 3 inch).
(If
each COS/MOS
chip represeflt a chip when It is piHI of the wafer.
When the wi~fer is cut ;nt~ chips, the cleavage
iJngles are 57 instead of 90 with respect to the
face of the chip. Therefore, the isolated chip is
ilctuallv 7 mils (0, 17 mm) larger in both dimensions.
--------------------------------------------------------
'31
CD4029B Types
COS/MOS Presettable
Up/Down Counter
Binary or BCD-Decade
High-Voltage Types (20-Volt Rating)
The RCA-CD4029B consists of a four-stage
binary or BCD-decade up/down counter with
provisions for look-ahead carry in both
counting modes_ The inputs consist of a
single CLOCK, CARRY-IN (CLOCK ENABLE), BINARYIDECADE, UP/DOWN, PRESET ENABLE, and four individual JAM signals_ 01, 02, 03, 04 and a CARRY OUT
signal are provided as outputs_
A high PRESET ENABLE signal allows
information on the JAM INPUTS to preset
the counter to any state asynchronously with
the clock. A low on each JAM line, when the
PRESET-ENABLE signal is_high, resets the
counter to its zero count. The counter is
advanced one count at the positive transition
of the clock when the CARRY-IN and PRESET ENABLE signals are low. Advancement
is inhibited when the CARRY-IN or PRESET
ENABLE signals are high. The CARRY-OUT
signal is normally high and goes low when
the counter reaches its maximum count in
the UP mode or the minimum count in the
DOWN mode provided the CARRY-IN signal is low. The CARRY·IN signal in the low
state can thus be considered a CLOCK
EiiiA"BLE. The CARRY-IN terminal must be
connected to VSS when not in use.
Binary counting is accomplished when the
BINARY/DECADE input ishigh;the counter
counts in the decade mode when the BINARY/DECADE input is low. The counter
counts up when the UP/DOWN input is
high, and down when the UP/DOWN input
is low. MUltiple packages can be connected
in either a parallel-clocking or a rippleclocking arrangement as shown in Fig. 17.
Parallel clocking provides synchronous control and hence faster response lrom all
counting outputs. Ripple-clocking allows lor
longer clock input rise and fall times.
The CD4029B-series types are supplied in
IS-lead ceramic dual-in-line plastic packages (E suffix), IS-lead ceramic II at packages
(K suffix), and in chip form (H suffix).
CD4029B Terminal Diagram
·PRESET ENABLE
O.
JAM 4
JAMI
CARRY IN
01
CARRY OUT
Vss
I.
2
I.
15
14
13
12
"
10
Features:
• Medium-speed operation ___ 8 MHz (typ_)
@ CL = 50 pF and VDD-VSS = 10 V
• Multi-package parallel clocking for synchronous
high speed output response or ripple clocking
for slow clock input rise and fall times
• "Preset Enable" and individual "Jam" inputs provided
• Binary or decade up/down counting
• BCD outputs in decade mode
• 100% tested for quiescent current at 20 V
• 5-V, 10-V, and 15-V parametric ratings
• Standardized, symmetrical output characteristics
• Maximum input current of 1 JJ.A at 18 V
over full package-temperature range;
100 nA at 18 V and 25 0 C
• Noise margin (over full package-temperature range)
1 Vat VDD= 5 V
2VatVDD=10V
2_5VatVDD=15V
• Meets all requirements of JEDEC Tentative
Standard No_ 13A, "Standard Specifications
for Description of 'B' Series CMOS Devices"
• Programmable binary and decade
countinglfrequency synthesizers-BCD output
• Analog to digital and digital to
analog conversion
•
•
•
•
UplDown binary counting
Magnitude and sign generation
Up/Down decade counting
Difference counting
RECOMMENDED OPERATING CONDITIONS at TA = 25°C, Except as Noted_ For maximum
reliability, nominal operating conditions should be selected so that operation is always within the
following ranges:
CHARACTERISTIC
Supply-Voltage Range (For T A = Full PackageTemperature Range)
LIMITS
Min_
UNITS
Max.
3
18
5
10
15
SO
20
12
-
5
10
15
340
140
100
Clock Pulse Width, tw
5
10
15
180
90
60
Preset Enable Pulse Width, tw
5
10
15
130
70
50
Clock Input Frequency, fCL
5
10
15
-
5
10
15
-
Setup Time tSU:
Carry-In
UfD or B/D
Q2
UP/DOWN
92CS_24472R\
VDD
(V)
-
JAM 3
JAM 2
BINARYI DECADE
92CS-17!90R3
Applications:
Voo
eLOCt(
Q'
Vss
CD4029B
FUNCTIONAL DIAGRAM
Clock Rise and Fall Time, trCL, EfCL
V
-
ns
2
4
MHz
5.5
15
JJ.s
:132 ____________________________________________________________________
CD4029B Types
MAXIMUM RATINGS, Absolute·Maximum Values:
·
DC SUPPLY·VOL TAGE RANGE, (VDDI
(Voltages referenced to VSS Terminal)
-0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS
-0.5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT
±10mA
POWER DISSIPATION PER PACKAGE (Pol:
0
For TA = -40 to +60 C (PACKAGE TYPE EI
.
..
500 mW
For TA = +60 to +850 C IPACKAGE TYPE EI
.
Derate linearly at 12 mW/oC to 200 mW
For TA = -55 to +100 0 C (PACKAGE TYPES D,FI
. . ..
.
500 mW
For T A = +100 to +125 0 C (PACKAGE TYPES 0, F I.
Derate linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE·TEMPERATURE RANGE (All Package Type,I
100mW
OPERATlNG·TEMPERATURE RANGE ITAI:
-55 to +12S D C
PACKAGE TYPES 0, F, H
-40 to +8SoC
PACKAGE TYPE E .
-65 to +1S0oe
STORAGE TEMPERATURE RANGE (Tstgl
LEAD TEMPERATURE (DURING SOLDERINGI:
At distance 1/16 ± 1/32 inch 11.59 ± 0.79 mm) from case for lOs max.
E
I
~3oHf~+H~~~~~~~~~~EfEfffi
·
g
~
10
g ,
:;
10
15
DRAIN-l0-S0URCE VOLTAGE ("os)-v
Fig. 1 - Tvpical output low (sinkJ current
characteristics.
iUtlll nItlll
J '5[mlTlTilJ.Urrju}-l.AmT~".ltiLTum-_uslou\HRCE:: VOLTAGE {VGSJ-15V
~12.5
STATIC ELECTRICAL CHARACTERISTICS
u
LIMITS AT INDICATED TEMPERATURES (oCI
CHARAC·
TERISTIC
CONDITIONS
Vo
(VI
Quiescent
Device
Current,
100 Max,
Output Low
(Sinkl Current
IOL Min.
Output High
(Source)
Current,
IOH Min.
Output Voltage:
Low·Level,
VOL Max.
Output
Voltage:
High·Level,
VOH Min.
Input Low
Voltage
VIL Max.
Input High
Voltage,
VIH Min.
Input Current
liN Max,
N
I
T
S
Values at -55, +25, +125 Apply to O,F,H Packages
Values at -40, +25, +85 Apply to E Package
+25
V'N VOD
(VI
(VI -55
-40
+85
150
+125
150
-
0.04
300
300
10
600
-
0.04
600
0.04
20
3000
3000
-
O.OB
100
0.61
0.42
0.36
0.51
1
1.6
1.5
1.1
0.9
1.3
2.6
4.2
4
2.8
2.4
3.4
6.B
-
-1
-
-3.2
-
5
0,5
5
-
0,10
10
10
10
0,15
15
20
20
0,20
20
100
100
0.4
0,5
5
0.64
0.5
0,10
10
1.5
0,15
15
4.6
0,5
5 -0.64 -0.61
2.5
0,5
5
-2
-l.B
-1.3 -1.15
-1.6
-1.5
-4
-1.1
-0.9
-1.3
-2.6
-
-2.8
--2.4
-3.4
-6.8
-
5
-0.42 -0.36 -0.51
9.5
0,10
10
-1.6
0,15
15
-4.2
-
0,5
5
0.05
-
0 0.05
-
0,10
10
0.05
-
0 0.05
-
0,15
15
0.05
-
0 0.05
-
0,5
5
4.95
4.95
5
0,10
9.95
10
9.95
10
15
-
1.5
-
-
1.5
1,9
-
10
3
-
-
3
1.5,13.5
-
15
4
-
-
4
0.5,4.5
-
5
3.5
Fig. 3 - Typical output high (source) cu"ent
characteristics.
V
-10
1,9
1.5,13.5
-
10
-
15
O,lB
lB
V
-
3.5
-
7
7
-
-
11
11
-
-
-
15
DRAIN-TO-SOURCE VOLTAGE (Vos)-V
-15
14.95
±1
10
GATE-lO-SOURCE VOLTAGE (VGS'--5 V
5
±1
TIt
I1A
-
15
±0.1
25
DRAIN-lO-SOURCE VOLTAGE (Vos)-V
-
±0.1
~
5,
AM81ENT TEMP£RATURE (TA)'25 G C
0,15
-
,
DRAIN-TO-SOURCE VOLTAGE (VDS)-V
-
0.5,4.5
14.95
g
mJl
13.5
-
·
75
Fig. 2 - Minimum output low (sink) current
characteristics.
5
-
10
z
~
5
Max,
Typ.
Min.
a
±10- 5 ±0.1 I1A
Fig. 4 - Minimum output high (source) current
characteristics.
__________________________________________________________________
~1133
CD4029B Types
Fig. 5 - Typical transition time as a function of
load capacitance.
Vo
~*
eLOCi TE PE
ALL INPUTS ARE PROTECTED
BY COS/MOS INPUT PROTECTION
NETWORK
x
x
1..
0
x
X
1..
Vss
I
92CL.·28675R1
0
J
0
0
0
,xQ
, ,
,, 0
, 0
X
0
a
,
0
0
X
Q
X
Q
Ne
Ne
X-:-OON'T CARE
Fig. 9 - Logic diagram.
LOAD CAPACITANCE [CLI- pF
Fig. 6 - Typical propagation delay times as a
tion of load capacitance (a output).
func~
, ,
,
CLOCK (CL) I
CARRY IN
~I:
UP/DOWN
LOAD ~CIT"'NCE [CU- pF
92CS- 29720
Fig. 7 - Typical propagation delay time as II function of load capacitance (carry output}.
.
.
,
dI.
4
~
104
~
4
is
~J.
i •
DECADE
PRESET
ENABLE
"~ENT
r- TEMP£~nIT.~i~'.2'
-t"","- .I£~
r-
-
.1
4
,.
,, ,,
n,
,
'.',,
~.
,.
#.
~.,
Qil
, ,
Q31---:-'1
,r,,t.-
02'
c
2 •
,,
,
' ,
,ill,,
'" ,,
J21
,
"E:nTIffEE~#~¥#~
~,Q"'Y.
--t~"/> ~
.," ih'
;.,.•
r
;;
BINARYI
.. !L.!......L.J
I
I
c L ·'0 pP
CL -15 pF ___
I IIII
,0'
10
CLOCK F'R(QUENCY (Ia)-.HI
Fig. 8 - Typical powwr dissipation
of frequency.
liS II
..
I
CAARYOUT I
I
COUNT
I
I
,
1
,-
1
I
I
I
I
I
I
I
I
I
I
I
I 5 I 6 I 7 I 8 I 9 I /0 I 11 1 12 I 13
1
I
I
I
I
I
I
I
I
I
I
I
I
I
r
I
I
I
1
-I
,
,,
104
"CI-2.121
function
1
1
1
,,
176!51432
92CM-11192A2
Fig. 10 - Timing diagram-binary mode.
134 ____________________~----------------------------------------------
CD4029B Types
*
*
A------~--------------~
.------r-~--------------+_--_r--_,
92CS-1119SR2
Fig. //- Conversion of clock up, clock down
input signals to clock and up/down
input signals.
J=====~===t:O
CONTROL
LOGIC
INPUT
LEVEL
ACTION
BINARY COUNT
DECADE COUNT
BIN/DEC.
(BIOI
UP/DOWN
(U/D)
0"
The CD4029B CLOCK and UP/DOWN inputs
are used directly in most applications. In
applications where CLOCK UP and CLOCK
DOWN· inputs are provided. conversion to
the CD4029B CLOCK and UP/DOWN inputs
can easily be realized by use of the circuit
in Fig. 11.
UP COUNr
DOWN COUNT
CD4029B changes count on positive transitions of CLOCK UP or CLOCK DOWN
-inputs. For the gate configuration shown
below. when counting up the CLOCK DOWN
input must be maintained high and conversely
when counting down the CLOCK UP input
must be maintained high.
JAM IN
NO JAM
PRESET ENABLE
{PEl
NO COUNTER
ADVANCE AT pes.
CLDCK TRANSITION
CARRY IN ICII
(CLOCK ENABLE)
ADVANCE COUNTER
AT pos. CLOCK
TRANSITION
92CL-28615'U
Fig. 9 - Logic diagram (cont'd).
CLOCK (eL)
CARRY IN
C~I ~~::t=~=+~::+=i==f~=Lt==t=t~t=t==t=+~~1-~=t~
I
UP/DOWN
I
Ir--rI
I
BINARYI
I
DECADE
I
PRESET
I
ENABLE
I
I
,
~~~~--~~~~--~~~~--~~~~--~~~~--~~r-::
~+-~~-+~--7-+-~-7-+--~+-~~-+~--7-+-~-7~r-;-
I
I
OJ
I
I
02
I~
03
I
I
I
CARRY OUT
I
I
I
COUNT
I
I~
O.
i0
I
I
I
I
I : 2
I
I
I
3
4 : 5
I
I
,ui
I
I
I
I
I
: 8 : 9 : 8
I
I
I6 I7
I
I
J
I
I
l7
!
I
I
I
I
6 : 5
I
4
I
I
I
I
I
I
I
I
: I :
I
I
l 3 I2
I
I
I
a
Fig. 12 - Timing diagram-decade mode,
_______________________________________________________________________ 135
CD4029B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C. Input t r• tt = 20 nl.
Cl -60pF. Rl = 200 kSl
LIMITS
TEST CONDITIONS
CHARACTERISTIC
VDD!VI
Min.
5
10
15
-
!yp.
UNITS
Max.
Clocked Oparation
Propagation Delay Time: tpHl. tplH
a Output
5
10
15
Carry Output
250 500
120 240
90 180
280 560
130 260
95 190
Transition Time:
tTHl' tTlH
Outputs. Carry Output
-
Minimum Clock Pulse Width.
tw
5
10
15
trCl. ttCl ••
5
10
15
-
Clock Rise & Fall Time.
Minimum Setup Times,
Carry In
ts
.
5
10
15
5
10
15
8/0 or UID
5
10
15
Maximum Clock Input Frequency. tel
Input Capacitance,
CIN
Any Input
ns
100 200
50 100
40 80
5
10
15
a
92Cl-29722
Fig. 13 - Power dissipation test circuit.
-
-
-
-
-
90 180
45 90
30 60
-
15
15
15
30
-10
6
60
20
12
-
o
I's
Vss
ns
170 340
70 140
50 100
2
4
5.5
4
8
11
-
-
5
7.5
V55
nC5-21"OIRI
Fig. 14 - QuitlSCent-device current test circuit.
MHz
pF
Preset Enable
5
10
15
-
5
10
15
-
Minimum Preset Enable Pulse Width, tw
5
10
15
-
65 130
35 70
25 50
Minimum Preset Enable Removal
Time.
trem·
5
10
15
-
100 200
55 110
40 80
5
10
15
-
fs· ..• Carry In
5
10
15
-
Min, HOLD Time
tH··· Carry In
5
10
15
-
Propagation Delay Time: tpHl. tplH
a Outputs
Carry Output
-
-
-
235 470
100 200
80 160
320 640
145 290
105 210
'NPUTO·COOUTPUTS
V'H
~
'---
ns
:t
V~l
v"~
NOTE:
TEST ANY COMBINATION
OF INPUTS
92:CS-2:74'URI
Fig. 15 -Input voltBge test circuit.
Carry Input
Propagation Delay Time< tpHl. tplH
Carry Output
Min Set-Up Time
-
170 340
70 140
50 100
25
50
30
15
12
25
100 200
35
70
30 60
ns
ns
l
ns
~
Voo
INPUO
Vco S
~
NOTE.
~::~~:I~~~~~S
TO BOTH Voo ANO'lsS'
CONNECT All UNUSED
INPUTS TO EITHER
v'S
Veo OR Vss'
Vss
• From Up/Down, Binary/Decode. Carry In, or Preset Enable Control Inputs to Clock Edge.
**11 more than one unit is cascaded in the parallel clocked application, t,el should be made less than or
equal to the sum of the fixed propagation delay cit 15 pF and the transition time of the carry output
driving stage for the estimated capecitlve load. This measurement was mad. with a decouplina capacitor
1>11JFJ between VOO and VSS'
·.·From Carry In to Clock Edge
Fig.
'6 -
Input current test circuit.
136 __________________________________________________________________
CD4029B Types
UP/DOWN
>______,-__________________~·=~~R=A=LL=E=L=C=L=O:CK:'N:G=·--------~~----__________-1>
~:~m >------t--,------------------+--,-----------------+~~-----------
U.
CD402S
....
CL~~ >------1--~-----------------1--~----------------~--l-------------.
g~~~r>-----~--------------------~--------------------~---------------
UP/DOWN
>-----~__------------------~==========~--------~----------------.
~:~~~ >------t--.,-------------------+--.,....-----------------+~~-----------
cz .
•,0
CLOCK>_------f---+---------~~_/
BINARYI
DECADE
92CL-Z •• 76R1
====t::=======______-.JL--------------..
>______L ____~______
Ripple Clocking Mode:
The UplDown control can be changed at any count. The only restriction on changing
the Up/Down control is that the clock input to the first counting stage must be high.
* CARRY OUT lines at the 2nd. 3rd. etc., stages may have a negative-going glitch
pulse resulting from differential delays of different CD40298 IC's. These negativegoing glitches do not affect proper C04029B operation. However, if the CARRY OUT
signals are used to trigger other edge·sensitive logic devices, such as FF's or counters,
the CARRY OUT signals should be gated with the clock signal using a 2·input OR gate
such as C04071B.
For cascading counters operating in a fixed up·count or dawn·count mode. the OR
gates are not required between stages, and 00 is connected directly to the CL input of
the next stage with 5 grounded.
Fig. 17 - Cascading counter packages.
Dimensions and pad layout for CD4029B.
Dimensions in parentheses are in millimeters and
are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10- 3 inch).
The photographs and dimensions of each CaS/MOS
chip represent a chip when it is part of the wafer.
When the wafer is cut into chips. the cleavage
angles are 57° instead of 90° with respect to the
face of the chip. Therefore. the isolated chip is
actually 7 mils (0. 17 mm) larger;n both dimensions.
____________________________________________________________________ 137
CD4030B Types
COS/MOS
Quad Exclusive-OR Gate
High-Voltage Types (20-Volt Rating)
The RCA·CD4030B types consist of four if>,
dependent Exciusive·OR gates. The CD4030B
provides the system designer with a means
for direct implementation of the ExclusiveOR function.
The CD4030B types are supplied in 14-lead
hermetic dual-in-line ceramic packages (D
and F suffixes), 14-lead dual-in-line plastic
packages (E suffix), 14-lead ceramic flat
packages (K suffix), and in chip form (H
suffix).
Features:
• Medium-speed operation-tpH L, tpui = 65 ns (typ.) at
VDD = 10 V, CL = 50 pF
• 100% tested for quiescent current at 20 V
• Standardized, symmetrical output characteristics
• 5-V, 10-V, and 15-\{.paramet,ic ratings
• Maximum input current of 1 IlA at 18 V over full packagetemperature range; 100 nA at 18 V arid 25° C
• Noise margin (over full package·temperature
range):
1 Vat VDD= 5 V
2 Vat VDD = 10 V
2.5 Vat VDD = 15 V
• Meets all requirements of JEDEC Tentative
Standard No. 13A, "Standard Specifications
for Description of 'B' Series CMOS Devices"
Applications:
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE. (V DO)
. -0.5 to +20 V
(Voltages referenced to V 55 Terminal)
-0.5 to V DO +0.5 V
INPUT VOLTAGE RANGE, ALL INPUTS
±10mA
DC INPUT CURRENT, ANY ONE INPUT
POWER DISSIPATION PiR PACKAGE· (PO):
. . . . . . . ..
500mW
For T A = -40 to +600 C (PACKAGE TYPE E)
Derate Linearly at 12 mW/oC to 200 mW
For T A = +60 to +85 <;, (PACKAGE TYPE E) . .
. . . . . . . ..
500mW
For T A = -55 to +100 C IPACKAGE TYPES 0, F)
Derate linearly at 12 mW/oC to 200 mW
For TA = +100to +125°C IPACKAGE TYPES 0, F)
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR T A = FULL PACKAGE-TEMPERATURE RANGE (All Package Types)
100mW
OPERATING-TEMPERATURE RANGE ITA):
PACKAGE TYPES 0, F, H
-55 to +125:C
PACKAGE TYPE E
-40 to +85 C
STORAGE·TEMPERATURE RANGE ITstg ). . .
-65 to +150 0 C
LEAD TEMPERATURE (DURING SOLDERINGi:
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 ml)'l) from case for 10 s max.
RECOMMENDED OPERATING CONDITIONS
LIMITS
Supply-Voltage Range (For T A = Full Package
Temperature Range)
MIN,
MAX.
3
18
UNITS
92CS-:!OOSI
CD4030B
FUNCTIONAL DIAGRAM
Even and odd-parity generators and checkers
Logical comparators
Adderslsubtractors
General logic functions
TERMINAL DIAGRAM
Top View
A
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges:
CHARACTERISTIC
•
•
•
•
Vss _7
VOD-14
I
2
B
J. A(S B
K'C(SO
4
0
Vss
5
6
7
14
13
12
"
10
9
8
TOP VIEW
V
voo
H
G
M.G(SH
L·E(SF
F
E
92CS-24473RI
TRUTH TABLE FOR ONE OF
FOUR IDENTICAL GATES
*INPUTS P:::ECTED
~
__ v55
I
A
B
0
1
0
1
0
0
1
1
= HIGH
J
0
1
1
0
LEVEL
a = LOW LEVEL
V55
BY COS/MOS
PROTECTION NETWORK
Fig. 1 - Schematic diagram (1 of 4 identical
Vss
92CS-30052
gatesl.
138 _______________________________________________________________________
CD4030B Types
STATIC ELECTRICAL CHARACTERISTICS
LIMITS AT INDICATED TEMPERATURES (oCI
U
Values at -55, +25, +125 Apply to D, F, H Packages N
I
Values at -40, +25, +85 Apply to E Package
CONDITIONS
CHARAC·
TERISTIC
Vo
(VI
-
-40
+85
+125
Min.
+25
Typ.
0,10
10
2
2
60
60
0.15
15
4
4
120
120
-
0,20
20
20
20
600
600
-
0.4
0,5
5
0.64
0.61
0.42
0.36
0.51
0.5
0,10
10
1.6
1.5
1.1
0.9
1.3
2.6
1.5
0,15
15
4.2
4
2.8
2.4
3.4
6.8
4.6
0,5
2.5
0,5
9.5
0,10
5 -0.64 -0.61 -0.42 -0.36 -0.51
-1
-2 -1.B -1.3 -1.15 -1.6 -3.2
5
-1.6 -1.5 -1.1 -0.9 -1.3 -2.6
10
13.5
0,15
15
Quiescent
Device
Current,lDD
Max.
0,5
-
5
1
1
30
30
T
Max. S
i
GATE-TO-SOURCE VOLTAGE (VGS".5 II
25
~
~
~
20
10V
g
1
0.02
2 !J.A
4
0.04
20
-4.2
-4
-2.B
-2.4
1
10
-
mA
-3.4 -6.B
0,5
5
0.05
0.10
10
0.05
-
0
-
0.15
15
0.05
-
0
0.05
Output Voltage:
High·Level,
VOHMin.
-
5
4.95
4.95
5
-
0.5
0,10
10
9.95
9.95
10
-
0,15
15
14.95
14.95
15
-
Input Low
Voltage,
VILMax.
0.5,4.5
-
5
1.5
1.5
3
4
-
3
15
-
-
10
5
3.5
1,9
1.5,13.5
0.5,4.5
1,9
1.5,13.5
I npu t Cu rrent
liN Max.
-
10
7
7
15
11
11
0,18
18
-
3.5
±1
±0.1
-
±1
0.05
0.05
-
±0.1
(Vosl-V
Fig. 2 - Typical output low (sink) current
characteristics.
-
Output Voltage:
Low·Level,
VOL Max.
Input High
Voltage,
VIHMin.
I
~30
'- 15
0.02
0.02
E
DRAIN-TO-SOURCE VOLTAGE
Output Low
(Sink)
Current
IOLMin.
Output High
(Source)
Current,
IOH Min.
VIN VDD
(VI (VI -55
c
.".
V
5
10
15
CRAIN-TO-SOURCE VOLTAGE (11051-11
4
Fig. 3 - Minimum output low (sink) current
characteristics.
DRAIN-TO-SOURCE VOLTAGE (Vosl-V
I
V
-
±10-5 ±0.1 !J.A
Fig. 4 - Typical output high (source) current
characteristics.
DYNAMIC ELECTRICAL CHARACTERISTICS at T A
CL =50pF, RL = 200 Kn
=25°C; Input t r , tf =20 ns,
DRAIN-lO-SOURCE VOLTAGE (Vos)-V
-15
-10
-5
AMBIENT TEMPERATURE (TA" 25-C
CONDITIONS
CHARACTERISTIC
Propagation Delay Time,
Transition Time,
Input Capacitance,
tpLH, tpHL
tTHL' tTLH
CIN
LIMITS
VDD
(VI
Typ.
Max.
5
140
280
10
15
65
130
50
100
5
100
200
10
50
100
15
40
BO
5
7.5
Any Input
UNITS
ns
ns
pF
Fig. 5 - Minimum output high (source) current
characteristics.
____________________________________________________________________ 139
CD4030B Types
Voo
"PUTav""ouTPUTS
INPUTS
V,H
o
V55
'---
~
:r
V~L
Vss
NOT!.:
TiE:ST ANV COMBINAllON
OF'INPUTS
9ZCS-Z7441AI
Fig. 11 - Input·voltage test
V55
circuit.
92cs-n401RI
Fig. 10 - Quiescent-device current
test circuit.
Fig. 6 - Typical transition time as a function of
load capacitance.
Veo
'NPUO'.
Voo
~
!200t~+-
o
5g
~
SEQUENTlAL..LV.
Vss
TO BOTH Yoo AND Vss·
CONNECT ALL UNUSED
INPUTS TO EITHER
~
2i
NOTE
MEASURE INPUTS
V5S
100
Yoo OR Vss
,.V
III
20
IHil
40
60
92CS-300!lS
80
L.OAD CAPACITANCE (CLI-pF
100
92C5-30053
fig, 12 - Input-current test
circuit.
Fig. 13 - Dvnamic power dissipation test
circuit.
Fig. 7 - Typical propagation delay time as a function
of load capacitance.
AMBIENT TEMPERATURE fTA I- 25"'C
LOAD CAPACITANCE {CL~~!lO pF
!
-';,
~
i-"'"
~
~ i± S~ :---
100
!
!I
t
10
15
SUPPLY VOLTAGE 1Vool-V
Fig. 8 - Typical propagation delay time as a function
of supply voltage.
Dimensions and pad layout for CD4030BH.
Dimensions in parentheses are in millimeters and
are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10- 3 inchl.
t
_,2. ..
68 t
2
'" 5 I,
2.
'" ''', 2. 2
'" 68,
2.
'" 6
The photographs and dimensi0'ls of each COSMOS
chip represent a chip when it is parr of the wafer.
When the wafer is cut into chips. the cleallage
angles are 5'° instead of 90° with respect to the
face of the chip. Therefore. the isolated chip is
actuallv 7 mils (0. 17 rom) largB' in both dimensions.
',04
INPUT FREQUENCY (tIl-kH~
Fig. 9.- Typical dynamic power dissipation as a
function of input frequency.
140 _____________________________________________________________
CD4031 B Types
COS/MOS 64-Stage
Static Shift Register
High-Voltage Types (20-Volt Rating)
The RCA-CD4031 B is a static shift register
that contains 64 D-type, master-slave flipflop stages and one stage which is aD-type
master flip-flop only (referred to a.s a 1/2
stage).
The logic level present at the DATA input is
transferred into the first stage and shifted
one stage at each positive·going clock-transition. Maximum clock frequencies up to
12 Megahertz (typical) can be obtained. Because fully static operation is allowed, information can be permanently stored with the
clock line in either the low or high state. The
CD4031B has a MODE CONTROL input
that, when in the high state, allows operation
in the recirculating mode. The MODE CONTROL input can also be used to select between two separate data sources. Register
packages can be cascaded and the clock
lines driven directly for high-speed qperation.
Alternatively, a delayed clock output (CLD)
is provided that enables cascading register
packages while allowing reduced clock drive
fan-out and transition-time requirements. A
third cascading option makes use of the 0'
output from the 112 stage, which is available
on the next negative-going transition of the
clock after the 0 output occurs. This delayed
output, like the delayed clock CLD' is used
with clocks having slow rise and fall times.
The CD4031 8 types are supplied in 16-lead
hermetic dual-in-line ceramic packages (0
and F suffixes), 16-lead plastic dual-in-line
packages (E suffix), 16-lead ceramic flat
packages (K suffix), and in chip form (H
suffix).
Features:
• Fully staticoperatiori: DC to 12 MHz typo @ VDO-VSS
=15V
• Standard TTL drive capability on 0 output
• Recirculation capability
• Three cascading modes:
Direct clocking for high-speed operation
Delayed clocking for reduced clock drive requirements
Additional 1/2 stage for slow clocks
• 100% tested for quiescent current at 20 V
• Maximum input current of 1 JlA at 18 V
over full package-temperature range; 100 nA
at 18 V and 25 0 C
• Noise margin (over full package-temperature
range)
1 VatVOO=5V
2 V at VDD = 10 V
2.5 Vat VDD = 15 V
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative Standard No. 13A, "Standard Specifications for Description of'S' Series CMOS
Devices"
.4
STAGES DATA
OUT
•
DELAYED
CLOCK
V DO • 16
Vss
~
OUT
B
Ne·3,4,1I.12,13,14
FUNCTIONAL DIAGRAM
INPUT CONTROL CIRCUIT TRUTH TABLE
RECIRC.
DATA
Applications:
MODE
BIT INTO
STAGE I
1
X
0
1
0
X
0
0
X
1
1
1
X
0
1
0
• Serial shift registers
• Time delay circuits
TYPICAL STAGE TRUTH TABLE
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating
conditions should be selected so that
operation is always within the following ranges'
LIMITS
CHARACTERISTIC
Min.
Max. UNITS
Supply·Voltage Range
18
V
3
(For T A=Full Package·
Temperature Range I
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY·VOLTAGE RANGE.IVDDI
-0.5 to +20 V
(Voltages referenced to VSS Terminal)
INPUT VOLTAGE RANGE, ALL INPUTS
-0.5 to VDD +0.5 V
±lOmA
DC INPUT CURRENT. ANY ONE INPUT
POWER DISSIPATIO.N PER PACKAGE (PO):
0
..
......
500mW
For TA = -40 to +60 C (PACKAGE TYPE E)
Derate Linearly at 12 mW/oC to 200 mW
For T A = +60 to +850 C (PACKAGE TYPE E)
..
......
500mW
For TA= -55 to +1000 C IPACKAGE TYPES D.F)
Derate linearly at 12 mW/oC to 200 mW
For T.c.. = +100 to +125 0 C IPACKAGE TYPES 0, FI
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
100mW
FOR T A = FULL PACKAGE·TEMPERATURE RANGE IAII Package Types)
OPERATING·TEMPERATURE RANGE IT AI:
-55 to +12SoC
PACKAGE TYPES D. F, H
-40 to +85 0 C
PACKAGE TYPE E .
-65 to +1500 C
STORAGE TEMPERATURE RANGE ITstgi
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for las max.
0I0t8
CL
Dau + 1
0
J
0
..r
'-
1
x
1
NC
TRUTH TABLE FOR OUTPUT FROM Q'
(TERMINAL 51
Data + 64
Data + 64%
CL
\...
\...
0
1
0
1
.r
X
1 = HIGH LEVEL
X = DON'T CARE
NC
0 = LOW LEVEL
NC = NO CHANGE
I.
I."
RECIRCULATE
DATA IN 2
CLiN
"c{
"
0'
0
12
0
10
Vss
9
Voo
DATA IN I
}NC
MODE CONTROL
CLo
TOP VIEW
NC· NO CONNECTION
.TERMINAL ASSIGNMENT
____________________________________________________________________ 141
CD4031 B Types
STATIC ELECTRICAL CHARACTERISTICS
LIMITS AT INDICATED TEMPERATURES (OCI
Values at -55, +25, +125 Apply to D,F,H Packages
CONDITIONS
Values at -40, +25, +85, Apply to E Package
+25
Vo
VIN VDD
+85
(VI
(VI .~;-~5
+125
(VI
-40
Min.
Typ.
CHARACTERISTIC
-
0,5
0,10
0,15
0,20
5
10
15
20
0.4
0,5
0.5
1.5
0.4
0.5
1.5
0,10
0,15
0,5
0,10
0,15
5
10
15
Output High (Source)
4.6
Current. IOH Min.
2.5
9.5
13.5
0,5
0,5
0,10
0,15
0,5
0,10
0,15
Ouiescent Device
Current,
-
100 Max.
Output Low (Sinkl
Current IOL Min.
Q
Q,O',CLD
Q, Q, Q', CLD
-
Output Voltage:
-
Low-Level.
VOL Max.
Output Voltage:
High-level,
5
10
15
5
-0.64
2
-1.6
-4.2
-
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
0,18
18
±O.l
-
0.5,4.5
1,9
1.5, 13.5
VIL Max.
-
0.5.4.5
1,9
1.5,13.5
Input High
Voltage,
VIH Min.
TO
20
100
2.56
6.4
16.8
0.64
1.6
4.2
0.5
0,10
0,15
VOH Min,
Input Low
Voltage
'5
150
300
-
5
10
20
100
600
3000
15Q.
300
600
3000
2.44
1.68
1.44
2.04
6
16
4.4
11.2
0.42
3.6
9.6
0.36
0.9
2.4
5.2
13.6
0.51
1.3
3.4
-0.36
-1.15
-0.9
-2.4
-0.51
-1
-1.6
-1.3
-3.4
-3.2
-2.6
-6.8
0.61
1.5
4
'-'0.61
-1.B
-1.5
-4
1.1
-
2.8
-0.42
-1.3
-1.1
-2.8
0.05
0.05
0.05
4.95
9.95
14.95
1.5
3
4
3.5
7
11
0.04
0.04
0.04
0.08
-
4
10.4
27.2
1
2.6
6.:3
a
a
a
-
4.95
9.95
14.95
5
10
15
UNITS
Max.
5
10
20
100
pA
-
,
-
DRAIN-TO-SOURCE VOLTAGE !Vosl-V
Fig. 2 - Typical output low (,ink)
mA
0.05
0.05
0.05
V
-
-
-
1.5
-
3
4
3.5
7
11
--
-
±1O-5
±0.1
V
±O.l
±1
±1
-
OR.".··ro",ooI.C' IJOLTAGE (Vos}-V
Fig. 3 - Minimum output low (sink)
current characteristics (0 sink
current - 4X ordinate),
Input Current
liN Max.
current characteristics (0 sink
current = 4X ordinate).
pA
DRAIN-lO-SOURCE VOLTAGE (Vos}-V
-15
-10
-5
AMBIENT TEMPERATURE (TAJ-25·C
GATE-TO-SOURCE VOl.TAGE IVGS'o-5V
-of
~
-IO~
-15 ~
......
~
-IOV
.;:
...
-20~
Fig. 4 - Typical output high (source)
current characteristics.
ORAIN-TO-SOURCE VOl.TAGE (VOsJ-V
~
2
CLOCK
a
CL
9 CLo
fi
DD
--
.
.
* PROTECTED
AL.L. INPUTS ARE
BY
COSlMDS PROT'CTOO'
NETWORIC
V's
Fig. 1 - Logic diagram.
Fig. 5 - Minimum output high (source)
current characteristics.
142 ______________
~
_______________________________________________________
CD40318 Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA: 2!PC; Input t"t,: 20 ns,
CL:50pF,RL:200k0.
TEST CONDITIONS
CHARACTERISTIC
Typ.
5
10
15
5
10
15
-
250
110
90
190
80
65
500
220
180
380
160
130
100
50
40
200
100
80
ns
100
50
40
200
100
80
ns
50
25
20
100
50
40
ns
30
15
10
60
30
20
ns
60
30
20
ns
-
30
15
10
5
.10
15
-
120
50
40
240
100
80
ns
5
10
15
2
5
6
4
10
12
5
10
15
-
-
-
-
Clock to 0', tpHl' tplH;
Clock to 0, tpHl
Clock to ClD
Transition Time, tTHl' tTlH
(Any Output, except Q, tTHl)
-
Minimum Data Hold Time, tH
5
10
15
..
.
Clock Input Rise or Fall Time,
trCl, ttCl
Input Capacitance, CIN
(Any Input)
-
5
10
15
5
10
15
Maximum Clock Input Frequency,
-
Minimum Data Setup Time, ts
Minimum Clock Pulse Width, tw
-
5
10
15
5
10
15
tTHl
tCl
UNITS
Min.
Propagation Delay Time:
Clock to Q, tpHl' tplH;
Clock to 0, tplH
Q,
LIMITS
VDD(V)
-
-
-
-
-
5
Max.
ns
ns
040
60
LOAD CAPACITANCE eeL l-pF
100
Fig. 6 - Typical propagation delay time as a function
of load capacitance (see table).
'0
40
Fig.
ill
ill80
LOAD CAPACITANCE ICLr-pf
:2100
gOles- 30255
7 - Typical propagat;on delay t;me as a function
of load capacitance (see table),
-
-
eo
MHz
1000
1000
200
p.s
7.5
pF
*If more than one unit is cascaded in the parallel clocked application, trel should be made less than or
equal to the sum of the propagation delav at 50 pF and the transition time of the output driving stage.
""Maximum Clock Frequency for Cascaded Units;
a) Using Delaved Clock Feature in Recirculation Mode:
1
f max
=-
(n·l) CLO prop. delay + a prop. delay + set·up time
where n = number of packages
b) Not Using Delayed Clock:
92CS~24322
1
lmax
~ propagation delay + se"up time
Fig.
8 - Typ;cal transition time as a function of
load capacitance (except D, tTHL)'
143
CD4031 B Types
VDo
AMBIENT TEMPEAA~~RE .I~A 1·2~·C
y.
20
H~t
....
Iftllilil
40
'H-Ifttt-t--t-ttt
'0
60
80
'00
LOAD CAPACITANCE ICLI-pF
Fig. 9 - Tvpical transition time BS a function of
load capacitance (0, tTHL)'
2468
2458
2468
2
"68
10
100
II(
10k
CLOCK INPUT FREQUENCY (fcLI-kH:
2468
";;'" vss
Fig. 10 - Typical dynamic power di$$ipation as B
function of clock input frequency.
fCL
NOTE: P.G.I-fcLiP.G.2-.....-
Fig. 11 - Oynsmic power dissipation hlst circuit.
Voo
.
INPUTS
Vss
MODE CONTROL
Voo· RECIRCULATION
GND· NEW DATA
Fig. 12 - Cascading using direct clocking for high-speed operation
(see clock rise and fall time requirement J.
Fig. 13 - Ouiescent-devicecurrent test circuit.
Voo
Voo
INPUO
VDO S
'---Ii\-o ---v:..rCLOCK
DRIVER
NOTE
0
MEASURE INPUTS
SEQUENTIALLY.
TO BOTH Voo AND ¥Ss'
CONNECT ALL UMISED
Yss
INPUTS TO EITHER
DELAYED
CLOCK
TO CLOCK
*
NEW DATA
INTO FIRST
FOR RECIRCULATION MODE ONLY
FF TO DELAY DATA UNTIL
Voo CRYSS'
GNO. NEW DATA
FIRST REGISTER DELAYED CLOCKING
HAS OCCURRED.
REGISTER
VSS
MODE CONTROL: Voo =RECIRCULATION
9ZCS-29062R'
Fig. 15 - Input·leaksge current.
Fig. 14 - Cascading using delayed clocking for reduced clock drive requirements.
Voo
1
Q'
'NPUTOVCOOUTPUTS
'.~
v,.
1
Y~L
MODE CONTROL
Voo ~ RECIRCULATION
GNO = NEW DATA
92C5-29064
Vss
92CS-2744UII
Fig. 16 - Cascading using hBlf-clock-pulse delayed data output (0') to permit
use of slow rise and fall time clock inputs.
144
Ncn:~ ANY
CONIIINATION
OF'INPUTS
Fig. 17'- Input·voltage test circuit.
CD4031 B Types
91-99
(2.311- 2.515)
J
136-144
(3.454 - 3.658)
92CM-30259RI
.1
Dimensions and pad la your for CD4031 B.
DimensIons In pamntlleses afe In millimeters and
are dtmved from the basIc lOch dImenSions as indlcated. Grid graduiJtlons are III mils (10- 3 inch).
The phorographsanddimenslons of each COS/MOS
chip represent a chip when it IS part of the wafer.
When the w~fer is cut mt"o chips. the cleavage
angles afe 57 Instead of 90 with respect to the
face of the chip. Therefore, the'lsolated chip IS
actuallv 7 mils (0. 17 mm) larger in both dimenSions.
____________________________________________________________________ 145
CD4032B, CD4038B Types
COS/MOS
Triple Serial Adders
SUM I
I
High-Voltage Types (20-Volt Rating)
Features:
Positive Logic Adder - CD4032B
• Invert inputs Oh all adders for sum complementing
applications
dc to 10 MHz (typ.)
• Fully static operation.
@VDD=10V
• Single-phase clocking
• Standardized, symmetrical output characteristics
Negative Logic Adder - CD4038B
The RCA-CD40328 and CD40388 types
consist of three serial adder circuits with
common CLOCK and CARRY-RESET inputs. Each adder has provisions for two
serial DATA INPUT signals and an INVERT command signal. When the command signal is a logical "1 ", the sum is
complemented_ Data words enter the adder
with the least significant bit first; the sign
bit trails. The output is the MOD 2 sum of
the input bits plus the carry from the previous bit position. The carry is only added
at the positive-going clock transition for the
CD40328 or at the negative-going clock for
the CD40388, thus, for spike-free operation
the input data transitions should occur as
soon as possible after the triggering edge_
The CAR RY is reset to a logical "0" at the
end of each word by applying a logical "1"
signal to a CARRY-RESET input one-bitposition before the application of the first
bit of the next word.
The CD40328 and CD40388 types are supplied in 16-lead hermetic dual-in-line ceramic
packages (D and F suffixes), 16-lead dual-inline plastic packages (E suffix), 16-lead
ceramic flat packages (K suffix), and in chip
form (H suffix).
CD4032S, CD4038S
TERMINAL DIAGRAM
VDD
SUM 3
"
15
I.
INVERT 3
CLOCK
SUM2
"
"
INVERT2
12
CARRY RESET
INVERT 1
10
Vss
A'
B'
A2
B2
BI
AI
SUM I
TOP VIEW
92CS-24474RI
• 100% tested for quiescent current at 20 V
• 5-V, 10-V, and 15-V parametric ratings
• Maximum input current of 1 /1A at 18 V
over full package-temperature range;
100 nA at 18 V and 25°C
• Noise margin (over full package-temperature range)
1 Vat VDD = 5 V
2VatVDD=10V
2.5VatVDD=15V
• Meets all requirements of JEDEC Tentative
Standard No. 13A, "Standard Specifications
for Description of'S' Series CMOS Devices"
':I2C5-11663
CD4032B, CD4038B
FUNCTIONAL DIAGRAM
Applications:
•
•
•
•
•
Serial arithmetic units
Digital correlators
Digital datalink computers
Flight control computers
Digital servo control systems
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (V DD )
(Voltages refertmced to VSS Terminal)
. -0.5 to +20 V
INPUT VOLTAGE RANGE. ALL INPUTS
-0.5 to V DO +0.5 V
DC INPUT CURRENT, ANY ONE INPUT
±10mA
POWER DISSIPATION PjR PACKAGE (~):
For T A = -40 to +600 C (PACKAGE T PE E)
. . . . . . . ..
500mW
Derate linearly at 12 mW/oC to 200mW
For T A = +60 to +85 C (PACKAGE TYPE E). .
For T A = -55 to +1000 C (PACKAGE. TYPES 0, F)
..
........
500mW
0
For T A = +100 to +125 C (PACKAGE TYPES D, F)
Derate Linearly at 12 mWI eta 20.0. mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR T A = FULL PACKAGE-TEMPERATURE RANGE (All Package Types)
100mW
OPERATING-TEMPERATURE RANGE (T A):
PACKAGE TYPES 0, F, H
-55 to +125 0 C
PACKAGE TYPE E
-40 to +85°C
STORAGE TEMPERATURE RANGE (T,,)
. .
-65 to +1500 C
LEAD TEMPERATURE (DURING SOLD~RING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mml from case for 1(j s max.
RECOMMENDED OPERATING CONDITIONS at TA = 2SoC, Unless Otherwise Specified
For maximum reliability, nominal operating conditions should be selected so that operation
is always within the following ranges.
CHARACTERISTIC
VD D
Clock Input Frequency.
fCl
3
5
10
15
5
Clock Input Rise or Fall Time,
Data Input Set-Up Time.
Clock to A or 8 Inputs
146
Min.
Supply Voltage Range (at T A - Full Package-Temperature
Range)
trCl, tfCl
tsu
Max,
UNITS
18
V
-
2.5
-
5
7.5
-
10
15
-
5
10
15
200
80
60
500
500
500
MHz
/1s
-
-
ns
CD4032B, CD4038B Types
STATIC ELECTRICAL CHARACTERISTICS
IU
LIMITS AT INDICATED TEMPERATURES (OCI
CHARAC·
TERISTIC
CONDITIONS
Vo
(VI
+85
-40
5
0.04
10
600
0.04
20
3000
3000
-
O.OB
100
0.42
0.36
0.51
1
-
1.1
0.9
1.3
2.6
2.8
2.4
3.4
6.8
-0.42 -0.36 -0.51
-1.3 ':"1.15 -1.6
-3.2
-
150
150
-
0.10
10
10
10
300
300
-
0,15
15
20
20
600
-
0,20
20
100
100
0.4
0,5
5
0.64
0.61
1.5
0,15
15
4.2
4
4.6
0,5
2.5
0,5
5 -0.64 -0.61
-2 -1.8
5
-1
9.5
0.10
10
-1.6
-1.5
-1.1
-0.9
-1.3
-2.6
13.5
0.15
15
-4.2
-4
-2.8
-·2.4
-3.4
-6.8
-
0,5
5
-
0.10
10
-
0,15
15
5
Output Voltage:
Low·Level.
VOL Max.
-
Output
Voltage:
High·Level,
VOH Min.
Input High
Voltage.
VIHMin.
0.04
5
1.6
Max.
-
5
10
Typ.
Min.
5
0,10
Input Low
Voltage
VIL Max.
+125
0,5
Output Low
(Sinkl Current 0.5
IOL Min.
1.5
Output High
(Sourcel
Current.
IOH Min.
0.5
0.05
-
0 0.05
0.05
0 0.05
0.05
-
4.95
4.95
5
-
0 0.05
0.10
10
9.95
9.95
10
-
-
0.15
15
14.95
14.95
15
-
5
1.5
1,9
-
10
3
1.5.13.5
-
15
4
0.5,4.5
-
3
-
4 V
-
5
3.5
3.5
-
1,9
-
10
7
7
-
-
15
11
11
-
-
0,18
18
-
TO
] ADDERS
>-----0--
2 a3
±0.1
g_
±1
±1
CL
INVERT
CARRY
RESET
SUM
-
±10- 5 ±0.1 IlA
-l-+-++++t-+.-rH-tIITTi
Yoo
WORD I O.OlliIOOa+60
WORD 2 0.0110010. +50
0.1101110 •• 110
VSS
9ZCM-29082RI
±0.1
V
1.5
-
0.5,4.5
1.5.13.5
IlA
mt
-
Input Current
liN Max.
*
CLOCK =.'----i
+25
VIN VDD
(VI
(VI -55
-
Ouiescent
Device
Current,
IDD Max.
N
I
T
S
Values at -55, +25, +125 Apply to D,F,H Packages
Values at -40, +25, +85 Apply to E Package
* BY
ALL INPUTS ARE PROTECTED
COS/MOS PROTECTION
WORD3UOIIOII--37
WORD 41J.QQ.!..L!.Q.-3.Q.
1.0101001--87
Fig.2 - CD40328 timing diagram.
NETWORK
Fig. 1 - CD40328 logic diagram of one of three serial adders.
_____________________________________________________________________ 147
CD4032B, CD40388 Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C, Input tr , tf= 20 ns,
CL =50pF,RL = 200 kn
TEST CONDITIONS
VDD(V)
CHARACTERISTIC
Propagation Delay Time: tpHl, tplH
A,B, Carry Reset, or Invert Inputs to
Sum Outputs
Clock Input to Sum Outputs
LIMITS
UNITS
Min. Typ. Max.
5
10
15
-
260 520
120 240
90 180
ns
5
-
325 650
175 350
150 300
ns
100 200
50 100
40 80
ns
125 200
50 80
40 60
ns
10
15
-
5
Minimum Data Input Setup Time, tsu
.Clock to A or B Inputs
5
10
15
..,.
Maximum Clock Input Frequency, fCl
5
10
15
2.5
5
7.5
4.5
10
15
-
Clock Input Rise or Fall Time, trCL,tfCl *
5
10
15
-
-
500
500
500
Transition Time: tTHl, tTlH
10
15
Input Capacitance,
CIN
-
(Any Input)
5
~ 10
5
5'1
5
to
15
DRAIN-10-SOURCE VOL-TAGE (Vosl-V
Fig. 5 - Tvpical output Jow (sink) current
characteristics.
~
.,
1
~
MHz
7.5
and the fixed propagation delay of the output of the driving stage for the estimated capacitive load.
~12.s
a
GATE TO-SOURCE VOLTAGE {VGS,-15V
10
z
!!: 7.5
Ils
pF
* If more than one unit is cascaded t rCL should be made less than or equal to the sum of the transition time
"[i"oDER,------------------------;
~
..9
lOY
0
~ 25
ov
5
10
15
DRAIN-lO-SOURCE VOLTAGE (Vosl-V
Fig. 6 - Minimum output low (sink) current
characteristics.
DRAIN-lO-SOURCE VOLTAGE (Vos)-V
-15
-10
-5
AMBIENT TEMPERATURE (TA'"25·C
*.,
CLOC:"''-------
g--.
ho
ADDERS
J
VOO
~'""1rl/--'"---t_- 2&3
vss
Fig. 7 - Typical output high (source) current
92Chl-2:908l
* BYALLCOSIMOS
INPUTS ARE PROTECTED
PROTECTION
NETWORK
Fig. 3 - CD40388 logic diagram Df one of three serial adders.
characteristics.
DRAIN-lO-SOURCE VOlTAGE (VDS)-V
--=to
-10
',~,~~',~",~
CL
INVERT
CARRY
RESET
SUM
-1::t::t::t::t::t::t11:::!:::!:::!:::!:::!:i:t-J:::
WORD I 1.1000011 --61
WORD 2 1.100 II 01 =-51
1.0010000 '"-112
I
WORD 3 0.0100100 -+'6
WORD 4 0.0110001 -+49
0.IOIOI01·+8!S
Fig.4 - CD40388 timing diagram.
148
J
Fig. 8 - Minimum output high (source) current
characteristics.
CD4032B, CD4038B Types
AMeIE~T
TEMPERATURE (TA ,. 25"C
IDV
15V
20
40
60
LOAD CAPACITANCE (CLJ-pF
10
Fig. 9 - Typical transition time as a function of
load capacitance.
;>;
468102 l
4 68103 ~
68104 2.
4 6810~
CLOCK INPUT FREQUENCY (fCL)- kHz 9~CS-30~41
I
LOAD CAPACITANCE (CLI-,pf
Fig. 10 - Typical propagation delay times as a
function of load capacitance (A, B,
Fig. 11 - Typical dynamic power dissipation as a
function of clock input frequency.
carry reset or invert to SUM).
VDD
V~UTl1'roO~:'~:r
V 1L
~
'00"'
VSS
~
:00
NOTE·
=vss
Vss
TEST ANY COMBINATION
OF INPUTS
PO I- 'el
~:;uS~:il~~:~:s
I"""
TO BOT H Voo AND Vss
CONNECT ALL UNUSED
INPUTS TO EITHER
Voo ORV SS
Vss
P,G.2'*
Fig. 12 - Dynamic power dissipation test
circuit.
Fig. 13 -Input voltage test circuit.
Fig. 14 - Input current test circuit.
I NP UTS , - - - ' - - - - ,
o
vss
'00
Fig. 15 - Quiescent-device current test circuit.
Dimensions in parentheses are in millimeters and
are derived from the basic inch dimensions as indicated. Grid graduations are in mils (1(,3 inch).
The photographs and dimensions of each COS/MOS
chip represent a chip when it is part of the wafer.
When the wafer is cut into chips, the cleavage
angles are 57° instead of 90° with respect to' the
face of the chip. Therefore, the isolated chip is
actually 7 mils (0. 17 mm) larger in both dimensions.
Dimensions and pad layout for CD4032BH; dimensions and pad layout for
CD4038BH are identical.
__________________________________________________________________ 149
CD4034B Types
COS/MOS 8~Stage Static
Bidirectional Parallel/Serial
Input/Output Bus Register
51
.,-I---'
High-Voltage Types '20-Volt Rating)
AI.
AlS
PIS
C L - l_ _- '
The RCA-CD4034B is a static eight-stage
parallel-or serial-input parallel-output register _ It can be used to:
1) bidirectionally transfer parallel informa:
tion between two buses, 2) convett seriai
data to parallel form and direct the parallel
data to either of two buses, 3) store (recirculate) parallel data, or 4) accept parallel data
from either of two buses and convert that
data to serial form_ Inputs that control the
operations include a single-phase CLOCK
(Cl), A DATA ENABLE (AE), ASYNCHRONOUS/SYNCHRONOUS (A/S), A-BUS-TOB-BUS/B-BUS-TO-A-BUS (A/B), and PARAllEL/SERIAL (P/S)_
Data inputs include 16 bidirectional parallel
data lines of which the eight A data lines are
inputs (3-state outputs) and the B data lines
are outputs (inputs) depending on the signal
level on the A/B input_ In addition, an input
for SERIAL DATA is also provided_
All register stages are D-type master-slave,
flip-flops with separate master and slave
clock inputs generated internally to allow
synchronous or asynchronous data transfer
from master to slave_ Isolation from external
noise and the effects of loading is provided
by output buffering_
PARALLEL OPERATION
A high PIS input signal allows data transfer
into the register via the parallel data lines
synchronously with the positive transition
of the clock provided the A/S input is low_
If the AlS input is high the transfer is independent of the clock_ The direction of
data flow is controlled by the A/B input_
When this signal is high the A data lines are
inputs (and B data lines are outputs); a low
A/B signal reverses the direction of data flow_
The A"E input is an additional feature which
allows many registers to feed data to a
common bus_ The A DATA lines are enabled
only when this signal is high_
Data storage through recirculation of data in
each register stage is accomplished by making the A/B signal high and the AE signal
low_
App/ications:
• Parallel Input/Parallel Output,
Parallel Input/Serial Output,
Serial Input/Parallel Output,
Serial Input/Serial Output Register
• Shift right/shift left register
• Shift right/shift lett with parallel loading
• Address register
• Buffer register
• Bus system register with enable parallel
lines at bus side
• Double bus register system
• Up-Down Johnson or ring counter
• Pseudo-random code generators
• Sample and hold register (storage,
counting, diqllay)
• Frequency and phase comparator
SERIAL OPERATION
A low PIS signal allo~s serial data to transfer
into the register synchronously with the
positive transition of the clock_ The A/S input is internally disabled when the register is
in the serial mode (asynchronous serial operation is not allowed).
The serial data appears as output data on
either the B lines (when AlB is high) or the
A lines (when A/B is low and the AE signal
is high)_
Register expansion can be accomplished by
simply cascading CD4034B packages_
The CD40348 types are supplied in 24-lead
dual-in-line ceramic packages (D and F suffixes), 24-lead dual-in-line plastic packages
(E suffix), 24-lead ceramic flat packages (K
suffix), and in chip form (H suffix).
92CS-2910B
Functional Diagram
Features:
• Bidirectional parallel data input
• Parallel or serial inputs/parallel outputs
• Asynchronous or synchronous parallel
data loading
• Parallel data-input enable on "A" data
lines 13-state output)
• Data recirculation for register expansion
• Multipackage register expansion
• Fully static operation dc-to-l0 MHz (typ_)
at VDD =10 V
• Standardized, symmetrical output
characteristics
• 100% tested for quiescent current at 20 V
• S-V, 10-V, and lS-V parametric ratings
• Maximum input current of 1 /l-A at 18 V
over full package-temperature range;
100 nA at 18 V and 2So C
• Noise margin lover full package-temperature
range):
1 VatVDD=SV
2 V at VDD = 10 V
2_5 V at VDD = 15 V
• Meets all requirements of JEDEC Tentative
Standard No_ 13A, "Standard Specifications
for Description of '8' Series CMOS Devices"
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (V Dol
-0.5 to +20 V
(Voltages referenced to VSS Terminal)
INPUT VOLTAGE RANGE, ALL INPUTS
-0.5 to VDD +0.5 V
±10mA
DC INPUT CURRENT, ANY ONE INPUT
POWER DISSIPATION PER PACKAGE IPDI:
For T A = -40 to +600 C (PACKAGE TYPE E)
........ ,
500mW
For TA = +60 to +85 0 C IPACKAGE TYPE E)
_
Derate Linearly at 12 mW/oC to 200 mW
For TA = -55 to +1000 C (PACKAGE TYPES D,F)
.
...
500mW
Derate Linearly at 12 mW/oC to 200 mW
For T A = +100 to +125 0 C (PACKAGE TYPES 0, F I
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE-TEMPERATURE RANGE IAII Package Types)
100mW
OPERATING-TEMPERATURE RANGE ITAI:
-55 to +1250 C
PACKAGE TYPES 0, F, H
PACKAGE TYPE E _
-40 to +85 0 C
-65 to + 150°C
STORAGE TEMPERATURE RANGE IT stg )
LEAD TEMPERATURE lOURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mml from case for 10 s max.
150 ____________________________________________________________________
CD40348 Types
RECOMMENDED OPERATING CONDITIONS at T A = 25 0 C, Except as Noted.
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges:
LIMITS
Min.
Max.
VDD
(V)
CHARACTERISTIC
Supply·V.:>ltage Range (For T A = Full Package·
Temperature Range)
5
10
15
5
10
15
Data Setup Time, ts
Serial Data to Clock
Parallel Data to Clock
5
10
15
Clock Pulse Width, tw
3
18
160
60
40
50
30
20
350
140
80
-
de
2
5
Clock Input Rise or Fall Time, trCl, tfCl"
INPUTS
UNITS
ns
tpLH
t PHL'
Fig. 2 - Asynchronous operation propagation
delay time and transition time.
rVeo
----=-90%
-----50%
ns
MHz
OUTPUT
15
Jls
..
IS cascaded trCL should be made less than or equal to the sum of the transition time
" If
----50%
----10,.·0
OUTPUTS
ns
7
-
.l====J",==!...!- -.::~ _90"!.\!D
"B"OR"A"
DATA
V
-
5
10
15
5,10,15
Clock Input Frequency, fCl
"A"OR"B"
DATA
more than one Unit
and the fixed propagation delav of the output of the driving stage for the estimated capacitive load.
* SERIAL.
INPUT REFERS TO ANY OF THE "AnOR ~B" DATA INPUTS, "A"ENABLE,
INPUT, AlB, PIS, DR AlS INPUTS
*If-'SL.H AND tSHL ARE SET-UP TIMES
Fig. 3 - Synchronous operation propagation
delay times, transition times, and
set-up times.
ROO
Y .
* COSIMOS
INPUTS PROTECTED BY
PROTECTION
NETWORK
CLOCj(~
ENAABLE~
'" nrL======:::::C=:-L--
A/BjA/S
9"CS~,-9I09RI
"~
Fig.. 1 - Steering logic diagram.
FLIP-FLOP TRUTH TABLE
INPUTS
,.
OUTPUT
Q
ClM
.ClS
D
~
'\..
0
~
0
0
J
0
INVALID
CONDITION
J
\..
\..
J
X
..r
'-
..r
'J
"""-
1 = High level
nL.....__--'IlL._ _ _ _ _ _--'r-
St:g,- - - - - - -___--'r----L...:.
"
"
IUL
,,~
A4n
IUL
,,~
""L....._________
~IUL
"~
b
1
1
1
1
1
0= low Level
0
INVALID
r.ONDITION
X = Don't eare
,,1lL._ _ _ _ _ _ _ _ _ _--'IUL
,,~
r-ul.J
961
,,~
,,~
- - . - B DATA LINES ARE
OUTP~TS -----i-~~~A:SE
...
Fig. 4 - Timing diagram.
____________________________________________________________________ 151
CD40348 Types
STATIC ELECTRICAL CHARACTERISTICS
CHARAC·
TERISTIC
LIMITS AT INDICATED T.EMPERATURES (oCI :U
N
I
T
S
CONDITIONS
Vo
(VI
VIN VDD
(VI
(VI -55
-
Quiescent
Device
Current,
100 Max.
Values at -55. +25. +125 Apply to D.F.H Packages
Values at -40. +25. +85 Apply to E Package
+25
-40
+85
+125
Max.
Typ.
Min.
0,5
5
5
5
150
150
-
0.04
0,10
10
10
10
300
300
0.04
0.08
-
0,15
15
20
20
600
600
-
-
'0,20
20
100
100
3000
3000
-
0.4
0,5
5
0.64
0.61
0.42
0.36
0.51
0.04
1
Output Low
(Sink) Current 0.5
IOL Min.
1.5
0,10
10
1.6
1.5
1.1
0.9
1.3
2.6
0,15
15
4.2
4
2.8
2.4
3.4
6.8
4.6
0,5
5
2.5
0,5
5
-2
-1.8
9.5
0,10
10
-1.6
-1.5
-1.1
-0.9
-1.3. -2.6
13.5
0,15
15
-4.2
-4
-2.8
-2.4
-3.4
Output High
(Source)
Current,
IOH Min.
Output Voltage:
Low·Level,
VOL Max.
Output
Voltage:
High·Level,
VOH Min.
Input Low
Voltage
VIL Max.
-0.64 -0.61
-0.42 -0.36 -0.51
-1.3 -1.15
-1.6
-1
-3.2
-6.8
ORAIN-TO-SOURCE VOLTAGE IVosJ-V
-
Fig. 5 - Typical output low (sink)
current characteristics.
mJl
0,5
5
0.05
-
0
0.05
-
0,10
10
0.05
-
0
0.05
-
0,15
15
0.05
-
a
0.05
-
0,5
5
4.95
4.95
5
-
-
0,10
10
9.95
9.95
10
-
0,15
15
14.95
0.5,4.5
-
5
1.5
14.95
1.5
4
1,9
-
10
3
-
-
15
4
-
-
0.5,4.5
-
5
3.5
1,9
-
10
7
7
15
11
11
1.5,13.5
3.5
Input Current'
liN Max.
-
0,18
18
±0.1
±0.1
±1
±1
3-State
Output
Leakage
Current
lOUT Max.
0,18
0,18
18 ±O.4
±0.4
±12
±12
-
-
ORAIN-TO-SOURCE VOLTAGE
-
1.5,13.5
-
-
V
Fig. 6 - Minimum output low (sink)
15
-
* All inputs exce~
100
-
-
Input High
Voltage,
VIHMin.
5
10 p.A
20
current characteristics.
DRAIN-TO-SOURCE VOLTAGE (VosJ-V
3
V
-
-
±10- 5
±0.1 p.A
±10-4
±0.4 p.A
Fig. 7 - Typical output high (source)
current characteristics.
A and B Lines.
"25'
ERATU.
DRAIN-lO-SOURCE VOLTAGE IVpSI-V
L
Fig. 8 - Minimum output high (so::::;r21~2
current characteristics.
152 ______
~
Fig. 9 - Typical transition ~ime as B function
of load capacitance.
ACI
NeE
:L1-'
92C5-3015,
Fig. 10 - Typica' propagation delay time 8$ a
function of load capacitance (AlB)
parallel Data Input to BIA) parallel
Data Output, synchronous or
asynchronous] •
______________________________________________________----
CD4034B Types
ONE OF EIGHT SIAGES
r----~-------------------
I
I
I
K
1
0'
I
I
I
"6~0
:2
2 "61110 2 :2
4 61110l 2
468104 2
468 10$
CLOCK FREQUENCY ItcLI- kHz 92.CS-301$3
ROD
Fig. 12 - Typical dynamic power diSSipation
as a function of clock frequency.
Y
ss
PROTECTION NETWORK
ON SERIAL OATA INPUT
II
_
Voo
Q (TO NEXT STAGE DI
".
1_- __ ....: _____________________
_
92CM-Z9110RZ
Fig. 11 - Register stage logic diagram (1 of 8 stages).
13
12
14
TRUTH TABLE FOR REGISTER INPUT·LEVELS AND
RESULTING REGISTER OPERATION
=VSS
92CS-301$4
"A"
Enable PIS
a
a
a
a
a
1
AlB AlS
Operation'
a
x
Serial Mode; Synch. Serial Data Input, "A" Parallel Data Outputs
Disabled
1
X
Serial Mode; Synch. Serial Data
a
Parallel Mode; "B" Synch. Parallel Data Inputs., "A" Parallel Data
Outputs 0 isabled
a
Inp~t,
"B" Parallel Data Output
1
a
1
a
1
1
a
a
1
1
1
1
a
x
1
a
a
Paraliel Mode; "A" Parallel Data Inputs Disabled, "B" Parallel Data
Outputs, Asynch. Data Recirculation
Serial Mode; Synch. Serial Data Input, "A" Parallel Data Output
1
X
Serial Mode; Synch. Serial Data Input, "B" Parallel Data Output
1
1
a
a
1
1
a
1
Paraliel Mode; "B" Synch. Paraliel Data Input, "A" Paraliel Data.
Output
Parallel Mode; "B" Asynch. Parallel Data Input, "A" Parallel Data
Output
1
1
1
a
1
1
1
Paraliel Mode; "A" Synch. Parallel Data Input, "B" Parallel Data
Output
Parallel Mode; "A" Asynch. Parallel Data Input, "B" Parallel Data
Output
·Outputs change at posItive tranSition of clock In the serial mode and when the A/S controllOput IS "low "
in the parallel mode. During transfer from parallel to serial operation A/S should
remain low in order to prevent Os transfer into Flip Flops.
1
= HIGH
LEVEL
INPUTS
o
Parallel Mode; "B" Asynch. Parallel Data Inputs, "A" Parallel Datd
Outputs Disabled
Paraliel Mode; "A" Parallel Data Inputs Disabled, "B" Parallel Data
Outputs, SllOch. Data Recirculation
a
1
Fig., 73 - Dynamic power dissipation
test circuit.
0= LOW LEVEL
x
Vss
Fig. 14- Quiescent-device-current test circuit.
Voo,
VOO
I N P ( J U S NOTE'
~
MEASURE INPUTS
SEQUENTIALLY,
TO BOTH 1100 AND IISS'
CONNECT ALL UNUSED
INPUTS TO EITHER
VDO OR "SS,
o ~
Vss
Vss
= DON'T CARE
Fig. 15 - Input-current test circuit.
__________________________________________________________________ 153
CD4034B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 2!PC; Input tr,t,'; 20 ns,
CL =50pF RL =200kn
VDD
(V)
CHARACTERISTIC
Propagation Delay Time,
A(B) Parallel Data In to
B(A) Parallel Data Out
tpHl, tplH
3·State Propagation Delay Time,
AlB or AE to "A" OUT
tplZ, tpHZ'
tpZl' tpZH
5
10
15
tTHL, tTlH
5
10
15
Tr~nsition
Time,
Minimum Data Setup Time,
Serial Data to Clock
5
10
15
5
10
15
tsu
'NPUTOVDOOUTPUTS
LIMITS
Min. Typ. Max.
350
120
85
700
240
170
ns
200
80
60
400
160
120
ns
100
50
40
200
100
80
ns
-
80
30
20
160
60
40
ns
5
10
15
5
10
15
2
5
7
4
10
14
-
Maximum Clock Frequency,
5
10
15
-
-
125
50
35
250
100
70
ns
fCl
Minimum Clock Pulse Width,
tw
Maximum Clock Rise or Fall Time, trCl, tfCL *
Input Capacitance, (Any Input)
CIN
~
1
Vss
Fig.
16 -
NOTE:
TEST ANY COMBINATION
OF INPUTS
Input-voltage test circuit.
AppIicat!!JIIS
Minimum High·level Pulse Width, tw
AE, PIS, AIS
5
10
15
'---
V~L
-
Parallel Data to Clock
V'H
UNITS
25
15
10
50
30
20
ns
175
70
40
350
140
80
ns
Fig. 17 - 16·bit parallel in/parallel out,
parallel inr"erial out, serial in/
parljlliel out, serial in/serial out
register.
MHz
-
SERIAL
OATA
5,10,15
-
-
15
J.ls
-
-
5
7.5
pF
:*If more than one unit is cascaded, trCL should be made less than or equal to the sum of the transition time
1 and the fixed propagation delay of the output of the driving stage for the estimated capacitive load.
Fig. 18 - 16-bit serial in/gated parallel out
register.
DOUBLE - BUS SYSTEM
tENABLE INPUTS ON BOTH SIDES)
,------,
I
I
I
I
I
MEMORY
I
I
I
I
I
L
_____ -.J
r------,
I
I
~-------,
I
I
I
I
I
I
I
I
I
PERIPHERAL
Y REG
Z REG
UNIT
I
I
L ______ J
UNIT
C04034
C04034
The "A" enable (AE) and AlB signals control all
combinations of transfer between the registers
' ',u;'NLd~:~
and bus systems.
Fig. 19 - Single· and doublfJ·bus svstems.
154
ARITHMETIC
I
I
I
I
I
L _____ -.JI
CD40348 Types
.
SHIFT L.EFT OUTPUT
"A" ~NABL.E
SHIFT
L.EFTI
~rIFT
IGHT
SHIFT
~IGHT
NPUT
=
"
PIS
P-0
AE
,
rt~J~'4'JT
"A·PARAL.L.EL. DATA-l
L
8
REG '. ----'::
~
C04034
AlB
8
L-.....P/S
'"M'
"
f--C~~g3~
r-" AIS
I
......
8
~
AIS
PARALL.EL.
ENTRY
r1 rt rt ri rf 'HtM~~HT
SI
SI
CL.OCK
AE
I r1 r1
,
C~/B
,
8
~
~
SHIFT
L.EFT INPUT
AIS
"
Fig. 21 - N-stage shift register with fixed serial
output line.
AE
AE
VDD
L
AIS
PIS
REG. 3
CD4034
SAMPLE I HOLD
REG. 4
CD4034
VDD-L AIS
CC
M'
I __ A PARAL.LEL DATA __ B
~SI
~SI
PIS
AE
I _A PARAL.L.EL. OATA_ B
SERIAL DATA
CC
1_8 PARALLEL DATA-B
AlB
11111111
AIS
11111111
CLOCK
-
A "High" ("Low") on the shift Left/Shift
Right input allows serial data on the Shift
Left Input (Shift Right Input) to enter the
register on the positive transition of the
clock signal. A "high" on the "A" Enable
Input disables the "A" parallel cata lines on
Reg. 1 and 2 and enables the "A" data lines
on registers 3 and 4 and allows parallel data
Vaa
I_BPARAL.LEL OATA-B
into registers 1 and 2. Other logic schemes
may be used in place of registers 3 and 4 for
parallel loading.
When parallel inputs are not used Reg. 3 and
4 and associated logic are not required.
* Shift left input must be disabled during parallel
PIS
TO DISPLAY ETC
92CS-19214RI
Fig. 22 - Sample and hold register-serial/
parallel in-parallel out.
entry.
Fig. 20 - Shift right/shift left with parallel inputs.
"
2
""' I
"A· ENABLE
SERIAL INPUT
AlB
VSS
10
CLOCK
"12
TOP
"
"
VIEW
"
AIS
PIS
TERMINAL DIAGRAM
Dimensions in parentheses are in millimeters and
are derived from the basic inch dimensions as in·
dicated. Grid graduations are in mils (10- 3 inch).
The photographs and dimensions of each COS/MOS
cMp represent a chip when it is part of the wafer.
When tl]e w~fer is cut int~ chips, the cleavage
angles are 57 instead of 90 with respect to the
face of the chip_ Therefore, the isolated chip is
actually 7 mils (0. 17 mm) larger in both dimensions.
Dimensions and pad layout for CD4034BH.
____________________________________________________________________ 155
CD4035B Types
COS/MOS 4-Stage
Parallel In/Parallel Out
Shift Register
with J-K Serial Inputs and True/
Complement Outputs
High-Voltage Types (20-Volt Rating)
The RCA·CD4035B is a four-stage clocked
signal serial register with provision for synchronous PARALLEL inputs to each stage
and' SERIAL inputs to the first stage via
JK logic. Register stages 2. 3. and 4 are
coupled in a serial D flip·flop configuration
when the register is in the serial mode
(PARALLEL/SERIAL control lowl.
Parallel entry into each register stage is per·
mitted when the PARALLEL/SERIAL can·
trol is high.
In the parallel or serial mode information is
transferred on positive clock transitions.
When the TRUE/COMPLEMENT control is
high. the true contents of the register are
available at the output terminals. When the
TRUE/COMPLEMENT control is low. the
outputs are the complements of the data in
the register.
The TRUE/COMPLEMENT
control functions asynchronously with respect to the CLOCK·signal.
JK input logic is provided on the first stage
SERIAL input to minimize logic require-
Features:
•
•
•
•
•
•
•
•
•
•
•
4-Stage clocked shift operation
Synchronous parallel entry on all 4 stages
JK inputs on first stage
Asynchronous True/Complement control
on all outputs
Static flip-flop operation; Master-slave
configuration
Buffered inputs and outputs
High speed - 12 MHz (typ.l at VDD = 10 V
100% tested for quiescent current at 20 V
Standardized. symmetrical output
characteristics
5-V, 10-V. and 15-V parametric ratings
Meets all requirements of JEDEC Tentative
Standard No. 13A. "Standard Specifications
for Description of "B" Series CMOS
Devices"
PARAl.LEL IN
{".L
'KL
ER.
IN
~I'
101 2
111 3
1214\
CLKL
P/sL
4-STAGE REGISTER
TlcL
RESET
L
VOO"/6
Vss ~8
I'
,Ol/QI
15
1.'.4
1'3
OtQ2 0 3/03 Q4/Q4 f
TIC' OUT
92CS- 29054IU
FUNCTl.ONAL DIAGRAM
App/ications:
• Counters. Registers
Arithmetic-unit registers
Shift-left - shift right registe~s
Serial-to-parallel/parallel-to-serial
conversions
• Sequence generation
• Control circu its
• Code conversion
ments particularly in counting and sequence-
DRAIN·TO·SOURCE VOLTAGE IVosl-V
FI RST STAGE TRUTH TABLE
CL
generation applications.
With JK inputs
connected together. the first stage becomes
a D flip-flop. An asynchronous common
RESET is also provided.
...r
...r
The CD4035B types are supplied in IS-lead
hermetil: dual-in-line ceramic packages (D
and F suffixes). IS-lead dual-in-line plastic
packages (E suffix), IS-lead ceramic flat
packages (K suffix), and in chip form (H
suffix).
.r
tn_llINPUTS)
K
R
J
Fig. 1 - Typical output low (sink)
In (OUTPUTSl
On-I
an
0
x
x
0
a
I
0
0
I
J
x
0
a
I
0
I
0
a
On-I
...r
X
I
0
I
\....
X
X
a
On·1
X
X
X
I
X
0
On-I
current characteristics.
~gg~E
I
On-I
a
DRAIN-TO-SOURCE VOlTAGE IVDS)-V
Fig.
2 - Minimum output low (sink)
current characteristics.
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE. (VDDI
. -0.5 to +20 V
(Voltages referlmced to VSS Terminal)
-0.5 to VDD +O.S V
INPUT VOLTAGE RANGE. ALL INPUTS
±10mA
DC INPUT CURRENT. ANY ONE INPUT
POWER DISSIPATION P.,ER PACKAGE (POl:
. . . . . . . ..
SOOmW
For T A = -40 to +60. C (PACKAGE TYPE EI
Derate Linearlv at 12 mW/oC to 200 mW
For:rA = +60 to +85 ~ (PACKAGE TYPE EI. .
. . . . . . . ..
500mW
ForTA = -55 to +100
(PACKAGE. TYPES D. FI
Derate Linearlv at 12 mW/·C to 200 mW
For TA = +100 to +125 C (PACKAGE TYPES D. FI
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR T A = FULL PACKAGE-TEMPERATURE RANGE (All Package Tvpe.1
loomW
OPERATING·TEMPERATURE RANGE (TAl:
-55 to +125·C
PACKAGE TYPES D. F. H
PACKAGE TYPE E
-40 to +8S·C
-65 to +ISO·C
STORAGE TEMPERATURE RANGE (Tst I • .
LEAD TEMPERATURE (DURING SOLD~RINGI:
At distance 1/16 ± 1/32 inch 11.59 ± 0.79 mml from case for 10. max.
. +265°C
ORAIN-TO-SOUACE VOLTAGEIVos)-V
f
156
Fig.
3 - Typical output high (source)
curnlnt characteristics.
CD4035B Types
DRAIN-lO-SOURCE VOLTAGE
(Vosl-V
Ff
Y .
* BY
ALL INPUTS ARE PROTECTED
COS/MOS PROTECTION
NETWORK
Fig. 5 - Minimum output high (source)
current characteristics.
D
PIs-a-SERIAL MOOE
T/C-I-fRUE OUTPUTS
°
04/04
p
Q
:'p!
Q
r;:::-Ps
Pi~ps
"
CL~Ci
Typica' Stage Detail Logic
LOAD CAPACITANCE (CLI-pF
Fig. 4 - Logic diagram.
Fig. 6 - Typical transition time as a function of
load capacitance.
RECOMMENDED OPERATING CONDITIONS at TA = 2SD C, Except as Noted.
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges·
CHARACTERISTIC
VDD
(V)
LIMITS
MIN.
Supply·Voltage Range (For T A = Full
Package·Temperature Range)
Data Setup Time, tS:
J/K Lines
Parallel·ln Lines
3
5
10
15
5
10
15
5
Clock Pulse Width, tw
Clock Input Frequency, fCL
Clock Rise or Fall Time, trCL, tfCL:
Reset Pulse Width, tw
10
15
5
10
15
5
10
15
5
10
15
220
80
60
140
50
40
200
90
60
de
-
250
110
80
UNITS
MAX.
18
V
-
ns
LOAD
CAPACITANCE (ell - pF
92CS-30J62
Fig. 7 - Typical propagation delay times as a function of load capacitance (a output).
-
Ii
ns
-
-
ns
-
2
6
8
15
15
15
MHz
J.ls
-
ns
SUPPLY VOLTAGE (Voo)-V
gZeS-30)&"
Fig. 8 - Typical maximum clock mput frequency
as a function of supply voltage.
_____________________________________________________________ 157
CD40358 Types
STATIC ELECTRICAL CHARACTERISTICS
lotit AMBIENT TEMPERATURE ITA I- 25-C
U
LIMITS AT INDICATED TEMPERATURES (OC)
CHARAC·
TERISTIC
I
CONDITIONS
Vo
(V)
Quiescent
Device
Current,
IDD Max.
+25
VIN VDD
(V)
(V) -55
-
N
I
T
S
Values at -55, +25, +125 Apply to D,F ,H Packages
Values at -40, +25, +85 Apply to E Package
-40
+85
+125
Typ.
Min.
Max.
0,5
5
5
5
150
150
-
0.04
-
0,10
10
10
10
300
300
-
0.04
-
0,15
15
20
20
600
600
-
0.04
-
0,20
20
100
100
3000
3000
-
0.08
0.4
0,5
5
0.64
0.61
0.42
0.36
0.5
0,10
10
1.6
1.5
1.1
4.2
4
2.8
5
10 p.A
20
100
CLOCK INPUT FREQUENCY I feLI-IIH,
Output low
ISink) Current
IOlMin.
Output High
ISource)
Current,
IOH Min.
Output Voltage:
low-level,
VOL Max.
Input High
Voltage,
VIH Min.
Input Current
liN Max.
-
0.9
1.3
2.6
2.4
3.4
6.8
-
1.5
0,15
15
4.6
0,5
5
-1
-
2.5
0,5
5
-2
-1.8
-1.3 -1.15
-1.6
-3.2
-
-0.64 -0.61
-0.42 -0.36 -0.51
0,10
10
-·1.6
-1.5
-1.1
-0.9
-1.3
-2.6
-
0,15
15
-4.2
-4
-2.8
-2.4
-3.4
-6.8
-
-
0,5
5
0.05
-
0 0.05
0,10
10
0.05
-
0 0.05
0,15
15
0.05
.-
0 0.05
5
4.95
4.95
5
10
9.95
9.95
10
-
0,15
15
14.95
14.95
15
-
5
1.5
3
-
4
3
4
0.5,4.5
5
3.5
3.5
-
10
7
7
-
-
15
11
11
-
-
18
±0.1
±0.1
±1
-
±1
rf"'i'-<'-'
"
V
10
fpGI·~
-
10
15
0,18
13
12
92CS-30365
Fig. 10 - Dynamic power dissipation test circuit.
1,9
-
I.
1.5
..
1.5,13.5
1,9
1.5,13.5
I.
-
0,5
0,10
0.5,4.5
a
m~
9.5
-
92CS.30364
Fig. 9 - Typical dynamic power dissipation as
function of clock input frequency.
13.5
Output
Voltage:
High·level,
VOH Min.
Input low
Voltage
V il Max.
0.51
1
V
INPUTS
°
Vss
±10- 5 ±0.1 p.A
-
Fig. 11 - Ouiescent-device current test circuit.
LEFT/RIGHT
RIGHT
SHIFT
INPUT
Voo
CLOCK
1NPUO'
Voo
NOTE'
TRUE/COMPI.!.
~:~jiN~'~~~~:-S
?-@Vss
RESET
TO BOTH Voo ANO Vss'
CONNECT ALL UNUSED
INPUTS TO EITHER
4 J
3 j(
• CL
2 TIC
CD4035
• R
.
Voo OR VSS'
Vss
92CS-19974RI
92C$-2744IRI
Fig. 12 - Input-voltage test circuit.
Fig. 13 - Input-current test circuit.
Fig.
14 - Shift left/shift right register.
158 _________________________________________________________________
CD4035B Types
DYNAMIC ELECTRICAL CHARACTERISTICS
At TA = 25"C. Input tr • tf= 20ns. CL = 50pF, RL
)----.,....--0.15
CARRY
FORWARD
>-.,....---------0 '1-2
pl-3
=200 kG
TEST
CONDITIONS
CHARACTERISTICS
VDD
(V)
LIMITS
UNITS
Min.
Typ.
Max.
5
-
250
500
10
100
200
75
150
5
-
100
200
10
-
50
100
15
40
80
5
-
100
200
10
-
45
90
15
-
30
60
5,10,
15
-
-
15
5
110
5
-
10
-
25
50
15
-
20
40
CLOCKED OPERATION
Propagation Delay Time:
tpHl. tpLH
15
>----oPI-4
iUsing Couleur's Technique (B ID EC).... a
binary number (most significant bit. MSB)
first is shifted and processed. such that the
BCD equivalent is obtained when the last
binary bit is clocked into the register. The
CD4035B. with the correct conversion
logic. can also be used as a BCD·to·binary
converter.
Transition Time:
tTHl' tTlH
Minimum Clock Pulse Width. tw
Clock Rise or Fall Time. trCl. tfCL
*
Minimum Setup Time:
J/K Lines
"'The basic rule is: If a 4 or less is in a decade,
shift with the next clock pulse; if a 5 or greater
is in a decade, add 3 and then shift at the next
clock pulse. For more information refer to
"IRE TRANSACTIONS ON ELECTRONIC
COMPUTERS". Dec. 1958. Pages 313-316.
Fig. 75 - B/DEC logic.
10
15
Parallel·1 n·Lines
I nput Capacitance, CI N
ns
ns
IlS
220
40
80
30
60
70
140
ns
ns
-
5
2
4
10
6
12
15
8
16
Any Input
-
5
7.5
5
-
230
460
100
200
80
160
125
250
55
110
40
40
Maximum Clock Frequency, fCl
ns
MHz
pF
RESET OPERATION
Propagation Delay Time:
tpHl, tplH
10
15
5
10
Minimum Reset Pulse Width, tw
15
..
ns
ns
..
*If more than one Unit IS cascaded tTel should be made less than or equal to the sum of the transition
time and the fixed propagation delay of the output of the driving stage for the estimated capacitive
load.
Control::::: E'"
A
0
°2
B
03
C
°4
0
°1
A
°3
B
C
°4
0
1
1
1
1
1
1
0
0
1
o
0
1
1
0
1
1
0
1
0
1
6 0
1
9
0
0
1
3
12 0
o
1
0
1
0
1
o
6
1
1
0
9 1
0
1
0
13 1
1
1
2 0
0
0
4 0
1
0
11 1
1
0
1
o
o
0
7 1
B 0
1
1
1
0
1 1
o
0
0
14 0
1
1
1
0
3 1
0
1
1
1
12 0
0
1
0
B 0
1
7 1
1
0
0
Using B control line lEI two different state sequences can be generated.
For example; suppose the following two sequences are desired on
command (control line E)
0
1
2
5
10
4
Fig. 76(a} - Double sequence generator.
0
1
0
1
0
0
1
1
0
0
0
1
0
1
0
0
0
0
1
0
0
0
0
15
14
13
10
5
11
1
0
1
0
1
1
1
1
o
Fig. 76(b} - State sequences.
159
CD4035B Types
----L
9
PI-I
lot lit I.t
PI-2 Pl-3 Pl-4
,.----2.
6 CL
CLOCK
,...i
CARRY
C04035
I-
UNITS REGISTER
•
1
IQI
R
O.
0,
-fi'~
Ot litPl-3 I.tPl-4
J lPl-2
P[-I
C04035
,
TENS REGISTER
~F:/C
2 TIC
~
RESET
PIS
6 CL
J
L..1. K
INPUT
Voo
PIS
Q.
13
"
"
O.
0,
"
"
01
I
~]"co
UNITS
'----
PIS
PIS
CARRY
CARRY
BCD UNITS
(BIOEe LOGIC)
FORWARD
BCD TENS
(BIDEC LOGIC)
FIG.7
TO
UNITS
P!-3
PI-4
NEXT
~0[CADE
TO
FIG.1
PI-2
RE GISlER
~}co~s
TE
OU
OUT
'----
O.
13
PI-2
TO
TENS
REGISTER
PI-3
PI-.
Fig. 17 - Binary-to·BCD converter.
TERMINAL DIAGRAM
Top View
QI/GiI
TRUE/COW!:
R
J
RESET
~
PIS
Vas
••2
3
•s
re
.3
"13
'2
"
10
Voo
1I21G2
Q!l1I3
041G4
PI-'
PI-3
PI-2
PI-I
tICS-10M,,"
The photographs and dimensions represent
Dimensions and pad layout for CD40358H.
a chip when it ;s part of the wafer. When the
wafer is cut into chips; the CleavBfIIJ angles
are 57° instead of 90° with respect to the
Dimensions in parentheses are in millimeters and
are derived from the basic· inch dimensions as ;ndicated. Grid graduations are in mils (10- 3 inch).
face of the chip. Therefore. the ;solattKJ
chip is actually 7 mils (0.17 mmJ I.rger
in both dimensions.
160---------------------------------------------------------------
CD4041 US Types
COS/MOS Quad
True/Complement Buffer
High Voltage Types (20-Volt Rating)
The RCA-CD4041 US types are quad true/
complement buffers consisting of n- and
p-channel units having low channel resistance
and high current (sourcing and sinking)
capability. The CD4041 US is intended for
use as a buffer, line driver, or COS/MOSto-TTL driver_ I t can be used as an ultra-low
power resistor-network driver for A/D and
D/A conversion, as a transmission-line driver,
and in other applications where high noise
immunity and low-power dissipation-are primary design requirements_
The CD4041UB types are supplied in 14-lead
hermetic dual-in-line ceramic packages (D
and F suffixes), 14-lead dual-in-line plastic
packages (E suffix), 14-lead ceramic flat
packages (K suffix), and in chip form (H
suffix).
Features:
•
•
•
•
•
•
Balanced sink and source current; approximately 4 times
standard "B" drive
Equalized delay to true and complement outputs
100% tested for quiescent current at 20 V
Maximum input current of 1 p.A at 18 V over
full package temperature range; 100 nA at
18 V and 250 C
5-V, 10-V, and 15-V parametric ratings
Meets all requirements of JEDEC Tentative
Standard No_ 13A, "Standard Specifications
for Description of 'B' Series CMOS Devices"
B
6~'
Go<: 5
G
H
HoB
,
10~B K
•
•
•
•
•
High current source/sink driver
COS/MOS-to-DTL/TTL Converter Buffer
Display driver
MOS clock driver
Resistor network driver
(Ladder or weighted R)
•
•
Buffer'
Transmission line driver
L
E=A
F='A
I.
2
A
I.
"
12
G=B
4
H=1i
5
VOD
0
NsD
M=D
10
C
L=C
K-'
VSS
92CS-20155R1
DC SUPPLY-VOLTAGE RANGE, (V DD )
(Voltages referenced to VSS Terminal)
-0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS
-0_5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT
±10mA
POWER DISSIPATION PER PACKAGE (PO):
For TA • -40 to +60 o C (PACKAGE TYPE E)
. . . . . . . ..
500mW
For T A • +60 to +85 0 C (PACKAGE TYPE E)
.
Derate Linearly at 12 mW/oC to 200 mW
For TA • -55 to +100 oC (PACKAGE TYPES D,F)
. . . . . . . ..
500mW
ForTA· +100to +125 0 C (PACKAGE TYPES D, F)
Derate linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA • FULL PACKAGE-TEMPERATURE RANGE (All Package Types)
100mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPES 0, F, H
-55 to +125 0 C
PACKAGE TYPE E .
-40 to +85 0 C
STORAGE TEMPERATURE RANGE (Tstg )
-65 to + 1500 C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch 11.59 ± 0.79 mm) from case for 10 s max.
TOP VIEW
TERMINAL ASSIGNMENT
Voo
LIMITS
Max_
Min.
3
18
UNITS
LITAu.
tfljr
PUT
9 9
Yss
*ALL INPUTS PROTECTED
BY COS/MOS INPUT
PROTECTION NETWORK
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following range:
Supply-Voltage Range (For T A=Full PackageTemperature Range)
9
Applications:
MAXIMUM RATINGS, Absolute-Maximum Values:
CHARACTERISTIC
K-'
L=C
Vss
If1vo:3
...r--'-'
:r. 9
i P
il.
OOMPLEMENT
.., OU!!'UT
V5S
Fig.
t-
Schematic diagram 1 of 4 buffers.
V
DRAIN-lO-SOURCE VOLTAGE (VOSJ-V
70
GATE-lO-SOURCE VOLTAGE 'VGSI~15 V
~
E
I 60
1l
10V
!::::! 50
§
~ 40
a
~ 30
520
~
5
10
234567
DRAIN-lO-SOURCE VOLTAGE (Vosl-V
Fig.2 - Typical output low (sink) current
characteristics.
DRAIN-lO-SOURCE VOLTAGE (Vosl-V
Fig.3 - Minimum low (sink) current
characteristics.
Fig.4 - Typical output high (source) current
characteristics.
____________________________________________________________________ 161.
CD4041UB Types
STATIC ELECTRICAL CHARACTERISTICS
CHAAACTERISTIC
Quiescent
Device
Current
IDD Max.
Output Low
(Sink)
Current,
IOL Min.
Output High
(Source)
Current,
IOH Min.
CONDITIONS
Vo
VIN VDD
(VI
(VI
(VI
DRAIN-TO-SOURCE VOLTAGE (Vosl-V
LIMITS AT INDICATED TEMPERATURES (OCI
Values at -65,+25,+125 Apply to D, F,H Pkgs_
Values at -40,+25,+85 Apply to E Pkgs.
-65
-40
+85
+125
Min.
Typ.
Max.
-
0,5
0,10
0,15
0,20
5
10
15
20
1
2
4
20
1
2
4
20
30
60
120
600
30
60
120
600
-
0.02
0.02
0.02
0.04
1
2
4
20
0.4
0.5
1.5
4.6
2.5
9.5
13.5
0,5
0,10
0,15
0,5
0,5
0,10
0,15
5
10
15
5
5
10
15
2.1
6.25
24
2.1 .
-8.4
-6.25
-24
1.8
5.il
23
1.8
-6.7
-5.6
-23
1.44
4.5
17
1.44
-5.4
-4.5
-17
1.2
3.5
13
-1.2
-4.6
-3.5
-13
-
5
10
15
0.05
0.05
0.05
-
0
0
:....
3.2
1.6
10
5
38
19
-1.6 -3.2 ..
-6.4 -12.8
~10
-5
-19 -38
--
-
0,5
0,10
0,15
Output Voltage:
High· Level,
VOH Min.
-
0,5
0,10
0,15
5
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5
10
15
-
Input Low
Voltage,
VIL Max.
0.5,4.5
1,9
1.5,13.5
5
10
15
1
2
2.5
-
0.5,4.5
1,9
1.5,13.5
5
10
15
4
8
12.5
-
1
2
2.5
Input High
Voltage,
-
-
0,18
18
VIH Min.
Input
Current,
liN Max.
to.l
to.l
4
8
12.5
tl
tl
Il A
Fig.5 - Minimum output high (source)
current characteristics.
mA
-
Output Voltage:
Low· Level,
VOL Max.
-
UNITS
+25
-
a
0.05
0.05
0.05
-
-
-
.LOAD CAPACITANCE (ClJ-pF
Fig.6 - Typical propagation delay time
vs. load capacitance.
V
-
tl0-5 to.l
DYNAMIC ELECTRICAL CHARACTERISTICS at T A =250 C, Input tr,tt =20 ns,
CL = 50 pF, RL = 200 kn
v
m1l1H 1i11m
:::
i::H:tj:g ~?t
Il A
~~ll:~:::f
LOAD CAPACITANCE (Cll-pF
Fig. 7 - Typical transition time vs.
load capacitance.
CONDITIONS
CHARACTERISTIC
ALL TYPES
LIMITS
UNITS
VDD
Volts
Typ.
Max.
Propagation Delay Time:
tPHl,
tpLH
5
10
15
60
35
25
120
70
50
ns
lTHL.
lTLH
5
10
15
40
20
15
80
40
30
ns
15
22.5
pF
Transition Time
Input Capacitance
GIN
Any Input
INPUT VOLTAGE IVII-V
Fig.S - Minimum and maximum transfer
c'!aracteristics - true output.
162 _______________________________________________________________________
CD4041UB Types
1- -4
AMBIENT TEMPERATURE IT,.I- 2!!"C
2
INPUT 1,>I,020n'
!'ffi~~~~~
'NPUTOVCDOUTPUTS
V'H
'--
~
J
V~L
NOTE:
TEST MY ONE INPUT.
WITH OTHER INPUTS AT
VOO OR VSS·
VSS
z.s
I
INPUT VOLTAGE 1Vl!-V
tZtS-2140oiu
Fig.9 - Minimum and maximum transfer
characteristics - complement output.
1032
Fig. 13 - Input voltage test circuit.
4681042
468 10!!2 ... '1062
FREQUENCY II) HI
Fig. 11 - Typical power dissipation vs
frequency per output pair.
AMBIENT TEMPERATUREITA)-2!!"C
~it~;
,,"-
~ IO!!
ii
tt±~Y'
,,"-"
.fJ'
§
","'L'
,0
;1
(1'1
.',,"
,,~
Ft
~
~ 103
.....pit':
~
~
•
~
--t
,,J~~
,
.
INPUT RISE 8. FALL TIME-n,
Vss
CD
"
Fig. 10 - Typical power dissipation vs. input
rise & fall time per output pair.
TO BOTH VOO AND'lsS·
CONNECT ALL uNUSED
I..vTS TO EITHER
VSS
o·
VOO ORVSS '
Vss
Fig. 12 - Quiescent device current test circuit.
Fig. 14 - Input-leakage-current test circuit.
Dimensions and pad layout for the CD4041UBH
Dimensions in parentheses are in millimeters and are
derived from the basic inch dimensions as indicated
Grid graduations are in mils (10-3 inch).
The photographs and dimensions of each COS/MaS
chip represent a chip when it is part of the wafer.
When the wafer is cut into chips, the cleavage
angles are 57° instead of 90° with respect to the
face of the chip. Therefore, the isolated chip is
actually 7 mils (0. 17 mm) larger in both dimensions.
1--------- 12.06l:~:209) --------o-i
______________________________________
~
_____________________________ 163
CD4042B Types
COS/MOS
Quad Clocked
no"
latch
High-Voltage Types (20-Volt Rating)
The RCA-CD4042B types contain four latch
circuits, each strobed by a common clock.
Complementary buffered outputs are available from each circuit. The impedance of the
n- and p-channel output devices is balanced
and all outputs are electrically identical.
Information present at the data input is
transferred to outputs a and IT du ring the
CLOCK level which is programmed by the
POLARITY input. For POLARITY = 0 the
transfer occurs during the 0 CLOCK level
and for POLARITY = 1 the transfer occurs
. during the 1 CLOCK level. The outputs
follow the data input providing the CLOCK
and POLARITY levels defined above are
present. When a CLOCK transition occurs
(positive for POLARITY = 0 and negative
for POLARITY = 1) the information present
at the input during the CLOCK transition is
retained at the outputs until an opposite
CLOCK transition occurs_
The CD4042B types are supplied in lS-lead
hermetic dual-in-line ceramic packages (D
and F suffixes), lS-lead dual-in-line plastic
package (E suffix), lS-lead ceramic flat
package (K suffix), and in chip form (H
suffix).
lONE
I
or FOURLATC~ S t
CL
r
0,
L ___c,,- ___ ...J
-----l
!C0"NTROt.---p- -
c""~,,
."
':,
I
TG
I
..
EL
I
I
I
I
I
I
I
POLARtTY~P
6
I
v
L..'::.-I
L ________ ---"___ -'
g
OO *Au'INMS ARE
PROTECTED SY
COS/MOS PROTECTiON
NETWORK
J
1
FIg. 1
POLARITY
0
0
1
1
Clock polarity control
0 and Q outputs
Common clock
Low power TTL compatible
Standardized symmetrical output characteristics
100% tested for quiescent current at 20 V
Maximum input current of 1 /,-A at 18 V over
full package-temperature range; 100 nA at
18 V and 25 0 C
• 5-V, 10-V, and 15-V parametric ratings
• Noise margin (over full package
temperature range):
1 VatVDD -5 V
2 V at VDD = 10 V
2.5 V at VDD =15 V
• Meets all requirements of JEDEC Tentative
Standard No. 13A, "Standard Specifications
for Description of 'B' Series CMOS Devices"
D
LATCH
D
LATCH
truth table.
02
10
02
D,
13
03
D.
12
04
"
POLARITY
o-,,---+---L~
•
VDO~
VSS
92CS-20191
o!-
C04042B
FUNCTIONAL DIAGRAM
I.•
Q4
QI
•
POLARITY
D2
• Buffer storage
• Holding register
• General digital logic
I.
I•
3
4
DO
CLOCK
VDD
04
14
D4
13
I.
ii'!
"
•
ID
Vss
D3
Q3
Q2
Q2
TOP VIEW
92CS-201'MIRi
TERMINAL ASSIGNMENT
STATIC ELECTRICAL CHARACTERISTICS
CHARACTERISTIC
Ouiescellt
Device
Current
IDD Max.
Output Low
(Sink)
Current,
101 Min.
Output High
(Source)
Current,
IOH Min.
Output Voltage:
Low· Level,
VOL Max.
Output Voltage:
High· Level,
VOH Min.
VIL Max.
Input High
Voltage,
VIH Min.
Input
Current,
liN Max.
LIMITS AT INDICATED TEMPERATURES (OC)
Values at -55, +25, +125 Apply to D, F, H Pkgs.
CONDITIONS
Values at -40,+25,+85 Apply to E Pkgs.
UNITS
+25
Vo
VIN VDD
(V)
(V)
(V)
-55 -40 +85
Typ. Max.
+125 Min.
-
0,5
0,10
0,15
0,20
5
10
15
20
1
2
4
20
0.4
0.5
1.5
4.6
2.5
9.5
13.5
0,5
0,10
0,15
0,5
0,5
0,10
0,15
5
10
15
5
5
10
15
0.64
1.6
4.2
-0.64
-2
-1.6
-4.2
-
5
10
15
0.05
0.05
0.05
-
-
0,5
0,10
0,15
-
0,5
0,10
0,15
5
10
15
4.95
9.95
14.95
0.5,4.5
1,9
1.5,13.5
-
5
10
15
0.5,4.5
1,9
1.5,13.5
-
-
5
10
15
-
0,18
lB
-
±0.1
1
2
4
20
30
60
120
600
1
2
4
20
1
2.6
6.B
1
3.2
2.6
S.8
-
0
0
0
0.05
0.05
0.05
4.95
9.95
14.95
5
10
15
-
1.5
3
4
-
-
1.5
3
4
3.5
7
11
3.5
7
11
-
-
0.61 0.42
1.5
1.1
4
2.8
-0.61 0.42
1.8
1.3
-1.5 -1.1
-2.B
-4
±1
±0.1
~
30
60
120
SOO
-
0.02
0.02
0.02
0.04
-----164 ____________________________________________
Logic block dIagram and
01
D2
Applications:
Voltage,
a
0,
iii
Input Low
V55
CLOCK
0
D,
Features:
•
•
•
•
•
•
•
0.36 0.51
0.9
1.3
2.4
3.4
-0.36 0.51
1.15
1.6
-0.9
1.3
-2.4
3.4
±1
-
-
Il A
rnA
V
-
±10-5 ±0.1
V
IlA
____________________
CD4042B Types
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (V DD )
(Voltages referenced to VSS Terminal)
-0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS
-0.5 to VDD +0.5 V'
DC INPUT CURRENT, ANY ONE INPUT
±10mA
POWER DISSIPATION PER PACKAGE (PO):
o
For TA = -40 to +60 C (PACKAGE TYPE E)
• . . . . . . ..
500mW
For T A = +60 to +85 0 C (PACKAGE TYPE E)
. .
Derate Linearly at 12 mW/oC to 200 mW
For TA = -55 to +1000 C (PACKAGE TYPES 0, F)
. . . . • . . •.
500mW
For TA = +100 to +1250 C (PACKAGE TYPES D, F)
Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR T A = FULL PACKAGE-TEMPERATURE RANGE (All Package Types)
100mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPES 0, F, H
-55 to +125 0 C
PACKAGE TYPE E ,
-40 to +85 0 C
STORAGE TEMPERATURE RANGE (Tstg )
-65 to +150 0 C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1132 inch (1.59 ± 0.79 mm) from case for 10 s max.
,
DRAIN-lO-SOURCE VOL.TAGE
IVosl-V
Fig. 2 - Typical output low (sink) current
characteristics.
RECOMMENDED OPERATING CONDITIONS at TA = 25°C, Except as Noted.
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges:
CHARACTER ISTIC
VDD
(VI
SupplV-Voltage Range
(For TA=Full Package
Temperature Range)
Clock Pulse Width,
tw
Setup Time, ts
Hold Time, tH
Clock Rise or Fall
Time: t r , tf
LIMITS
ALL TYPES
Max,
Min.
UNITS
-
3
18
V
5
10
15
200
100
60
-
ns
5
10
15
5
10
15
50
30
25
120
60
50
5,10
15
-
I
ORAlIN-,"-',OURCE VOL.TAGE
IVos)-V
Fig. 3 - Minimum output low (sink) current
characteristics.
,
ns
DRA!N-TO-SOURCE VOLTAGE !Vos)-V
ns
-
Not rise or fall
time sensitive.
p.S
Fig. 4 - Typ;cal output high (source)
current characteristics.
DRAIN-lO-SOURCE VOLTAGE (Vos}-V
LOAD CAPACITANCE
Fig. 5 - Minimum output high (source)
current characteristics.
(eL.' -
LOAD CAPACITANCE CCLI -
j)F
Fig. 6 - Typical propagation delay time
load capacitance-data to Q.
VS.
pF
F;g. 7 - Typ;cal propagation delay time vs.
load capacitance-data to
a.
_____________________________________________________________________ 165
CD4042B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C; Input tr
,tr = 20 ns, CL = 50 pF,
RL=200Kn
CHARACTER ISTIC
. LIMITS
ALL TYPES
VDD
(V)
5
10
15
Max.
220
110
80
5
10
15
150
75
50
300
150
100
5
10
15
450
200
160
5
10
15
5
10
15
225
100
80
250
115
90
100
50
40
Minimum Clock
Pulse Width, tw
5
10
15
100
50
30
200
100
60
ns
Minimum Hold Time, tH
5
10
15
60
30
25
120
60
50
ns
Minimum Setup
Time,ts
5
10
15
0
0
0
50
30
25
ns
Propagation Delay
Time: tpHL' tpLH
Data In to Q
Data In to
a
Clock to Q
Clock to
a
Transition
Time: tyHL' tTLH
Clock Input Rise or Fall
Time: t r, tr
5,10
15
Input Capacitance, C, N
(Any Input)
-
ns
ns
LOAD CAPACITANCE {tll -
pF
F ;g. 8 - Typical propagation delay time
ns
500
230
180
200
100
80
Not rise or fall
time sensitive.
load capacitance-clock to
7.5
VI.
Q
ns
ns
LOAO CAPACITANCE lell -
J.IS
pF
Fig. 9 - 'Typical propagation delay time vs.
load capacitance-clock to
5,
10.
~.{
UNITS
Typ.
110
55
40
0.
pF
AMBIENT TEMPERATURE (TAJ· 2S'C
NOTE I
NOn: •
L.OAO CAPACITANCE
~
CL'I5pF
C -SOpf
10
I
10'
DATA
INPUT
104
lOll
INPUT FREQUENCY-HE
101
9lCS-309!lIIU
D
Fig. 10 - "Typical power dissipation ...
flTlquency.
Q
.
OOTPUT
Fig. " - Typical transition time VI. load
capacitance.
INPUTS
Vss
tpttL.tPLH
DTOQORfJ
tpHL,lPLH
CL TOOOAfJ
NOTES;
I. FOR POSITIVE CLOCK EDGE,INPUT DATA IS LATCHED WHEN
POLARITY IS LOW.
2. FOR NEGATIVE CLOCK EDGE, INPUT OATA IS lATCHED WHEN
POLARITY IS HIGH.
9ZCS·Z7630
Fig.
'2 -
Dynamic
test parameters.
DO
92CS-27.... IAI
Vss
Fig. 13 - Quiescent device current test circuit.
F;g.
'4 -Inputvoltagetestc;rcuit.
166 _____________________________________________________________________
CD4042B Types
Voo
1 N P U VDO
O S NOTE'
~
~~:~~:;I!~~~~S
Yss
TO BOTH Voo AND Vss·
CONNECT AL.L UNUSED
INPUTS TO EITHER
Voo OR VSS'
Vss
Fig. 15 -Input current test circuit.
Chip Photograph. Dimensions. and Pad Layout
59-67
1499-1 :>Oil
1 - - - - - - - 11 aJ~:~g321----"'l
Dimensions in parentheses are in millimeters and
are derived from the basic inch dimensions as in-
dicated. Grid graduations are in mils (10-- 3 inchJ.
The photographs and dimensions of each COS/MOS
chip represent a chip when it is part. of the wafer.
When the wafer is cut into chips, the cleavage
angles are 51° instead of 90° with respect to the
face of the chip, "Therefore. the isolated chip is
actually 7 mils (0. 17 mm) larger in both dimensions.
_______________________________________________________________________ 167
CD4043B, CD4044B Types
COS/MaS Quad 3-State
R/S Latches
High-Voltage Types (20-Volt Rating)
Quad NOR RIS Latch - CD4043B
Quad NAND RIS Latch - CD4044B
The RCA·CD4043B types are quad cross·
coupled 3'state COS/MOS NOR latches and
the CD4044B types are quad cross·coupled
3'state COS/MOS NAND latches. Each latch
has a separate Q output and individual SET
and RESET inputs. The Q outputs are controlled by a common ENABLE input. A
logic "I" or high on the ENABLE input
connects the latch states to the Q outputs.
A logic "0" or Iowan the ENAB LE input
disconnects the latch states from the Q
outputs, resulting in an open circuit condi·
tion on the Q outputs. The open circuit
feature allows common busing of the outputs.
The CD4043B and CD4044B types are supplied In 16-lead hermetic dual-in-line ceramic packages (D and F suffixesl. 16-lead
dual-in-line plastic packages (E suffix). 16lead ceramic flat packages (K suffix). and in
chip form (H suffix).
Features:
• 3-state outputs with common output
ENABLE
• Separate SET and RESET inputs for
each latch
• NOR and NAND configurations
• 5-V, 1 O-V, and 15-V parametric ratings .
• Standardized symmetrical output
characteristics
• 100% tested for quiescent current at 20 V
• Maximum input current of 1IJ.A at 18 V over
full package temperature range; 100 nA at
18 V and 25 0 C
.
• Noise margin (over full package temperature
rangel: 1 Vat VDD = 5 V
2 Vat VDD = 10 V
2.5 Vat VDD = 15 V
5,
R,
0,
5,
0,
R,
5,
0,
R,
S.
0.
R.
£NA8L.E
CD4043B
FUNCTIONAL DIAGRAM
• Meets all requirements of JEDEC Tentative
Standard No. 13A, "Standard Specifications
for Description of 'B' Series CMOS Devices"
Applications:
•
•
Holding register in multi-register system
Four· bits of independent storage with
output ENABLE
• Strobed register
• General digital logic
VDD
d
~2
S
E
.~E
E
04
9
~ -n~
C04Q43B
rd
lis
VeD
l
.
* ALL.
INPUTS PR:TECTEO
BY COS/MOS INPUT
PROTECTI.oN NETWORK
13
9
E
*5~:
I.
ao
RI
SI
ENABLE
,.
VDO
04
I.
R'
2
I.
13
54
NC
SI
NC
RI
53
R3
03
02
ENABLE
I.
"
52
R2
"
10
Vss
9
TOP VIEW
VDD
3
"13
54
R'
01
R3
53
12
6
"
10
Q3
02
Vss
TOP VIEW
92CS.24476RI
Ne'NO CONNECTION
CD40438
R2
52
I.
,.
'112CS·2"477RI
Ne· NO CONNECTION
TERMINAL ASSIGNMENTS
CD40448
Vss
CD40448
Fig. 1 - Logic diagrams.
MAXIMUM RATINGS, Absolute·Maximum Values:
DC SUPPLY·VOLTAGE RANGE. (VDD)
-0.5 to +20 V
(Voltages referenced to VSS Terminal)
-0.5 to VDO +0.6 V
INPUT VOLTAGE RANGE. ALL INPUTS
±lOmA
DC INPUT CURRENT. ANY ONE INPUT
POWER DISSIPATION PER PACKAGE (PO):
• . . • • • • •.
500mW
For T A = --40 to +60o C (PACKAGE TYPE E)
Derate Linearly at 12 mW/oC to 200 mW
• •
For T A = +60 to +850 C (PACKAGE TYPE E)
•
•
•
•
•
.
•
•
•
500mW
o
For TA = -55 to +100 C (PACKAGE TYPES O.F)
Derate Linearly at 12 mW/oC to 200 mW
For TA = +100 to +1250 C (PACKAGE TYPES D. F)
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
100mW
FOR TA = FULl: PACKAGE·TEMPERATURE RANGE (All Package Types)
OPERATI NG·TEMPERATUR E RANGE (TAl:
-55 to +1250 C
PACKAGE TYPES D. F. H
--40 to +850 C
PACKAGE TYPE E •
-65 to +150o C
STORAGE TEMPERATURE RANGE ITstg )
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ±0.79 mm) from case for lOs max.
Recommended Operating Conditions T A=25 0 C
For maximum reliability, nominal operating
conditions should be selected so that opera·
tion is always within the following ranges
Characteristic
Supply·Vollage Range
(T A = Full Package
Temperature Range)
SET or RESET
Pulse Width. tw
VOD Min. Max. lunits
(V)
-
3
18
5
10
15
160
80
40
-
V
ns
168 __________________________________________________________________
CD4043B, CD4044B Types
STATIC ELECTRICAL CHARACTERISTICS
CHARACTER·
ISTIC
Quiescent Device
Current,
100 Max.
Output Low
(Sink) Current
IOLMin.
Output High
(Source)
Current,
IOH Min.
Output Voltage:
Low·Level,
VOL Max.
Output Voltage:
High·Level,
VOH Min.
Input Low
Voltage,
VIL Max.
Input High
Voltage,
VIH Min.
Input Current
liN Max.
3·State Output
Leakage Current
lOUT Max.
LIMITS AT INDICATED TEMPERATURES (DC)
V.IUlllt-65,+25,+125 ApplytoD,F,H Package.
V.lull at -40, +25, +85 Apply to E Packllge
UNITS
+25
VIN VDD
Typ. Mix.
+125 Min.
+85
(V) (V) -55 -40
CONDITIONS
Vo
IV)
-
-
0,5
0,10
0,15
0,20
5
10
15
20
0.4
0.5
1.5
4.6
2.5
9.5
13.5
0,5
0,10
0,15
0,5
0,5
0,10
0,15
-
-
0.5,4.5
1,9
1.5,13.5
0.5,4.5
1,9
1.5,3.5
0,18
1
2
4
20
1
2
30
60
120
600
0,5
5
10
15
5
5
10
15
5
0,10
0,15
0,5
0,10
0,15
10
15
5
10
15
-
-
5
10
15
5
10
15
0,18
18
±0.1
±0.1
±1
0,18
18
±0.4
±0.4
±12
-
-
-
30
60
120
4
20
600
0.64 0.61
0.42
0.36
0.9
1.5
1.1
1.6
2.4
4.2
4
2.8
-0.64 -0.61 -0.42 -0.36
-2 -1.8 -1.3' -1.15
-0.9
-1.6 -1.5 -1.1
-4
-2.8
-2.4
-4.2
0.05
0.05
0.05
4.95
9.95
14.95
0.51
1.3
3.4
-0.51
-1.6
-1.3
-3.4
1
2
4
20
-
rnA
-
-
0
0.05
0
0
5
10
15
0.05
0.05
-
-
1.5
3
4
3.5
-
-
p.A
-
4.95
9.95
14.95
1.5
3
4
3.5
0.02
0.02
0.02
0.04
1
2.6
6.8
-1
-3.2
-2.6
-6.8
-
V
-
V
7
7
-
11
11
-
±1
-
±10-5
±0.1
}JA
±12
-
±10-4 ±0.4
}JA
-
DRAIN-lO-SOURCE .... OLTAGE l\'osl-V
It
Ii
I
DRAIN-lO-SOURCE VOLTAGE
tvos)-V
Fig. 2 - Typical output low (sink)
current characteristics.
CRAIN-lO-SOURCE VOLTAGE (Vosl-V
Fig. 3 - Minimum output low (sink)
current characteristics.
Fig. 4 - Typical output high (source)
current characteristics.
__________________________________________________________________ 169
CD4043B, CD4044B Types
DRAIN-TO-SOURCE VOLTAGE 1VOSI-V
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25° C; Input t r , tf= 20 ns,
CL =50pF, RL =200 Kn
CHARACTERISTIC
LIMITS
ALL TYPES
UNITS
VDD
(V)
TYP.
MAX.
Propagation Delay
Time: tpHL' tpLH
SET or RESET to Q
5
10
15
150
70
50
300
140
100
ns
3·State Propagation Delay
Time: ENABLE to Q
5
10
15
115
55
40
230
110
80
ns
5
10
15
90
50
35
180
100
70
ns
5
10
15
100
50
40
200
100
80
ns
Minimum
SET or RESET
Pulse Width, tw
5
10
15
80
40
20
160
80
40
ns
Input Capacitance,
(Any Input)
CIN
-
5
7.5
pF
tpHZ, tpZH
tpLZ. tpZL
Transition Time:
tTHL, tTLH
Fig. 5 - Minimum output high (source)
current characteristics.
TEST CIRCUITS
Fig. 6 - Typical transition time vs.
load capacitance.
106 AMBIENT TEMPERATURE (TA ,. 25°C
Voo
INPUTS
o
Vss
LOAD CAPACITANCE
CVl!!lpF
CL= 50pF
10
20
30
80
90
100
'0'
lOAD CAPACITANCE (CLI- pF
Fig. 7 - Typical propagation delay time
V~L
Fig. 9 - Quiescent device current.
YDO
Y
DO
'NPUOS
VIlI) NOTE
~
0
TO BOTH Voo AND VSS'
CONNECT AU. UNUSED
INPUfS TO EITHER
NOTE:
~~N~N~~OMBINATION
OUTPUT
MEASURE INPUTS
SEQUENTIALLY.
~
Vss
Yss
Voo OR VSS'
9ZCS-21441RL
Fig. 10 - Input voltage.
'0'
106
frequencv_
=Vss
10 5
INPUT FREOUENCY-Hz
Fig. 8 - Typical power dissipation vs.
vs. load capacitance-SET,
RESET to D, O.
V~UTQVIlI)OUTP~UT:
104
Voo
Fig. 11 - Input current.
Fig. 12- Switch bounce eliminator.
170 ____________________________________________________________________
CD4043B, CD4044B Types
.VDD
I.
TEST
"
"
IN
tpHZ Yoo VSS
15
ENABLE
IN
12
IN
II
iN
IKD
IDI-+t-"IVI..-{)
ENABLE
YSS
tpLZ Y ss
Y oo
Voo
IpZH Voo
YSS
VSS
t PZL Yss
Yoo
Yoo
z. HIGH
50"11.
.
50"11.
~
.
VSS
IMPEDANCE
Vss
Fig. 13 - ENABLE propagation delay time test circuit and waveforms.
CHIP PHOTOGRAPHS
DIMENSIONS AND PAD LAYOUTS
ENABLE A
0----------1---"
"
3 C04043
""
COiiiEI
ENABLE B
0----------1---"
1
DUTPUT
DATA
BUS
)
2/3 CO"'009
I.
,
3 C04043
10
"
15
.'C:I-IT1'.a
CD4043BH
3 C04043
10
"
+_-'
IS
COii)"'D
ENABLE
O~ _ _ _ _ _
RESET
Fig. 14 - Multiple bus storage.
Dimensions in parentheses are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10- 3 inch).
CD4044BH
The photographs and dimensions of each COS/MOS
chip represent a chip when it is part of the wafer.
When the wafer is cut into chips, the cleavage
angles are 57° instead of 90° with respect to the
face of the chip. Therefore, the isolated chip is
actually 7 mils (0. 17 mm) larger in both dimensions.
_____________________________________________________________________ 171
CD4045B Types
COS/MOS 21-St8ge Counter
High-Voltage Type~ (20-Volt Rating)
The RCA-C04045B is a timing circuit consisting of 21 counter stages, two output·
shaping flip·flops. two inverter output drivers,
and input inverters for use in a crystal oscil·
lator. The C04045B configuration provides
21 flip-flop counting stages, and two flip·
flops for shaping the output waveform for a
3.125% duty cycle. Push·pull operation is
provided by the inverter output drivers.
The first inverter is intended for use as a
crystal oscillator/amplifier. However, it may
be used as a normal logic inverter if desired.
A crystal oscillator circuit can be made less
sensitive to voltage·supply variations by the
use of source resistors. In this device, the
sources of the p and n transistors· have been
brought out to package terminals. If external
resistors are not required, the sources must
be shorted to their respective substrates (Sp
to VOO' Sn to VSS)' See Fig. 1. The first
inverter in conjunction with an outboard
inverter, such as 1/6 CD'I069, and RX' CX'
and RS can also be used to construct an
RC oscillator. The following data is supplied
as a guide iii the selection of values for RX'
RS, and Cx used in Fig. 11 :
1. RX max = 10 Mn with RS = 10 Mn
and Cx = 50 pF
2. Cx max = 25 /IF with RS = 560 kn
and RX = 50 kn
Features:
• Very low operating dissipation
<1 mW (typ.) @VOO = 5 V, fljJ =1 MHz
• Output drivers with sink or source capability
7 mA (typ.) @ VOO = 5 V
• Medium speed (typ.) . . • fljJ = 25 MHz @VOO = 10 V
• 100% tested for quiescent current at 20 V
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEOEC Tentative Standard
No. 13A, Standard Specifications for Oescripiton of
'8' Series CMOS Oevices"
4,5.6,9,10.11,1.2,13'
NO
CO~ECTIO'"
FUNCTIONAL DIAGRAM
MAXIMUM RATI NGS, Absolute·Maximum Values:
DC SUPPLY·VOLTAGE RANGE. (VOOI
(Voltages referenced to VSS Terminal)
-0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS
-0.5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT
±10mA
POWER DISSIPATION PER PACKAGE (Pol:
For TA • -40 to +60 0 C (PACKAGE TYPE E)
. . . . . . . ..
500mW
For T A • +60 to +850 C (PACKAGE TYPE E)
.
Derate Linearly at 12 mW/oC to 200 mW
For TA = -55 to +100o C (PACKAGE TYPES 0, FI
500mW
. . . . • . . ..
Derate Linearly at 12 mW/oC to 200 mW
For TA - +100 to +1250 C (PACKAGE TYPES 0, FI
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FO·R TA • FULL PACKAGE·TEMPERATURE RANGE (All Package Types)
100mW
OPERATING·TEMPERATURE RANGE (TAl:
PACKAGE TYPES 0, F, H
-55 to +1250 C
PACKAGE TYPE E .
-40 to +85 0 C
STORAGE TEMPERATURE RANGE (Tstgl
-65 to +1500 C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ±O.79 mm) from case for 10 5 max.
The C04045B types are supplied in l6-lead
dual-in-line ceramic packages (0 and F
suffixes). l6-lead dual-in-line plastic packages (E suffix), l6-lead ceramic flat packages
(K suffix), and in chip form (H suffix).
1·----------------------1
I
VDDI
r
I
I
Applications:
• Digital equipment in which ultra-low dissipation and/or operation using a battery
source is required.
• Accurate timing from a crystal oscillator
for timing applications such as wall clocks,
table clocks, automobile clocks, and digital
timing references in any circuit requiring
accurately timed outputs at various intervals in the counting sequence.
• Driving miniature synchronous motors,
stepping motors, or external bipolar transistors in push·pull fashion.
RS
I'
Vss
L
EXTERNAL
---.J
COMPONENTS
REFER TO APPLICATION NOT E
ICAN 6086 FOR THE CHOI CE OF
OSCILLATOR COMPONENT VALUES
AND TYPICAL OSCILLATOR CURRENTS
9ZCM-2910lR,
Fig. 7 - CD40458 and outboard components in a typical 21-stage counter application.
172 ___________________________________________________________________________________________________________________________________________
CD4045B Types
STATIC ELECTRICAL CHARACTERISTICS
CHARACTERISTIC
CONDITIONS
Vo
(V)
VIN VDD
(V) (V)
-55
-
0,5
5
0.10 10
0,15 15
0,20 20
0.4
0,5
5
Output Low (Sink)
0.5
0,10 10
Current IOL Min.
0,15 15
1.5
0,5
5
Output High (Source) 4.6
0,10 10
9.5
Current, IOH Min.
13.5 0,15 15
0.4,4.6 0,5
5
Pin 15 Output
0.5,9.5 0,10 10
Low and High
Current,IOL,IOH 1.5,13.5 0,15 15
0,5
5
Output Voltage:
0,10 10
Low-Level,
VOL Max.
0,15 15
Ouiescent Device
Current, IDD Max.
-
Output Voltage:
High-Level,
VOH Min.
Input Low
Voltage
VIL Max.
Input High
Voltage,
VIH Min.
Input Current
liN Max.
5
5
10
10
20
20
100
100
4.5
4.3
11.2 10.5
29.4
28
-4.5 -4.3
11.2 -10.5
29.4 -28
+85
+125
Min.
Typ.
150
150
0.04
5
300
0.04
300
10
A
600
600
0.04
20 /J
3000 3000
0.08 100
2.9
2.5
3.6
7
9.1
7.7
6.3
18
19.6 16.8
23.8
47
- mA
-2.9 -2.5 -3.6
-7
-7.7 -6.3
-9.1
-18
-19.6 -16.8 -23.8
-47
±0.1 +0.18
±0.2 ±0.3
- mA
±0.5
±1
0.05
0.05
0_05
0.05
0.05
0.05
-
-
-
-
V
4.95
9.95
14.95
-
5
10
15
5
10
15
1.5
3
4
3.5
7
11
0,18
18
-
U
N
I
T
Max. S
+25
-40
5
10
15
0,5
0,10
0,15
0.5,4.5 1,9
1.5,13.5
0.5,4.5
1,9
1.5,13.5
-
LIMITS AT INDICATED TEMPERATURES (OC)
Values at -55,+25,+125 Apply to D,F,H Packages
Values at -40,+25,+85, Apply to E Package
±0.1
±0.1
4.95
9.95
14.95
-
-
-
3.5
7
11
±1
1.5
3
4
-
V
-
±10-5 ±0.1 /J A
-
±1
-
5
10
15
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that operation is
always within the following ranges
LIMITS
VDD
(V)
Min.
Max,
Supply· Voltage Range (For T A = Full PackageTemperature Range)
-
3
18
V
5
10
15
-
Minimum Input-Pulse Width, tw
-
ns
-
100
50
40
5
10
15
5
12
15
-
MHz
CHARACTERISTIC
Maximum Input-Pulse Frequency,
(External Pulse SOurce)
fl/>
UNITS
_____________________________________________________________________ 173
CD4045B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at T A '" 25°C; Input t r • tf = 20 ns.
CL =50 pF. RL = 200 kn
TEST
CONDITIONS
CHARACTERISTIC
Propagation Delay Time:
+-j
LOW
1---.,~o-f-(9}-------1"'s
FIL.TER
C2
T
* BY
ALL INPU"TS ARE PROTECTED
COS/MOS PROTECTION
NETWORK
Vss
92C5-29172
Fig.' - COS/MaS phase-locked loop block diagram.
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (V Dol
1Voltages referenced to VSS Terminall
-0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS
-0.5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT
±10mA
POWER DISSIPATION PER PACKAGE (Pol:
o
For Til. = -40 to +60 C (PACKAGE TYPE EI
• . . . . . . ..
500mW
For Til. = +60 to +850 C (PACKAGE TYPE EI
.
Derate Linearly at 12 mW/oC to 200 mW
For TA = -55 to +100 0 C (PACKAGE TYPES D,F,I
. . . . . . . ..
500mW
For TA = +100 to +125 0 C (PACKAGE TYPES 0, F,I
Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE-TEMPERATURE RANGE IAIiPackage Typesl
100mW
OPERATING·TEMPERATURE RANGE (TAl:
PACKAGE TYPES 0, F, H
'-55 to +125 0 C
PACKAGE TYPE E .
-40 to +85 0 C
STORAGE TEMPERATURE RANGE (Tstgl
-65 to +150 0 C
LEAD TEMPERATURE (DURING SOLDERINGI:
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max.
176
&.
.3
c,
"
"•
Phase Comparators
The phase-comparator signal input (terminal
14) can be direct-coupled provided the signal
swing is within COS/MaS logic levels [logic
"0" ";;30% (VOO-Vssl. logic "1" ;;. 70%
(VOO-VSS)]. For smaller swings the signal
must be capacitively coupled to the selfbiasing amplifier at the signal input.
Phase comparator I is an· exciusive·OR net·
work; it operates analagously to an over-
driven balanced mixer. To maximize the lock
range, the signal- and comparator-input frequencies must have a 50% duty cycle. With
no signal or noise on the signal input, this
phase comparator has an average output
voltage equal to VOO/2. The low-pass filter
connected to the output of phase comparator
CD40468 Types
RECOMMENDED OPERATING CONDITIONS at T A = Full Package-Temperature Range
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges:
LIMITS
CHARACTERISTIC
UNITS
Min_
Max_
Supply-Voltage Range VCO Section:
As Fixed Oscillator
Phased-Lock-Loop Operation
3
5
18
18
Supply-Voltage Range Phase Comparator Section:
Comparators
VCO Operation
3
5
18
18
The selected external components must be
within the following ranges:
5 kn~ Rl, R2, RS~ 1 Mn
Cl ;;'100pF atV DD ;;'5 V;
Cl ;;. 50 pF at VD D ;;' 10 V
DESIGN INFORMATION
This information is a guide for approximating
the values of external components for the
CD4046A in a Phase-Lacked-Loop system_
Characteristics
Phase
Comparator
Used
Design Information
veo WITHOUT OFFSET
veo WITH OFFSET
R2=oo
veo Frequency
1
V
'-tzr[
to
--
t:c
''''
121L
2fc.
![?'
'I
I
'1i1N
'IoDI2
,-
-
supplies the averaged voltage to the veo
input, and causes the VCO to oscillate at the
center frequency Ifol.
The frequency range of input signals on
which the PLL will lock if it was initially
out of lock is defined as the frequency capture range 12f d.
The frequency range of input signals on
which the loop will stay locked if it was
initially in lock is defined as the frequency
lock range 12fU. The capture range is ~ the
lock range.
With phase comparator I the range of frequencies over which the PLL can acquire
lock Icapture range) is dependent on the
low-pass-filter characteristics, and can be
made as large as the lock range. Phase-comparator I enables a PLL system to remain
in lock in spite of high amounts of noise
in the input signal.
One characteristic of this type of phase comparator is that it may lock onto input frequencies that are close to harmonics of the
VCO center-frequency_ A second characteristic is that the phase angle between the
signal and the comparator input varies between 0 0 and 1800 , and is 900 at the center
frequency. Fig. 2 shows the typical, triangular, phase-to-output response characteristic
of phase-comparator I. Typical waveforms
for a COS/MaS phase-locked-loop employing phase comparator I in locked condition
of fa is shown in Fig. 3.
'bo'.
YDQ
veo INPUT VOL-TAGE
veo
VDD
~
INPUT VOLTAGE
12C1-ZOOIZItI
Voo
VOLTAGE
.
~
For No.Signallnput
Frequency Lock'
Range. 21L
2
1
Same as for No.1
veo will adjust to center frequency. fa
2
veo will adjust to lowest operating frequency. Imin
1
2
Range. 2 fC
1
Component
Selection
.,
9ZCS-Z0009
OUT
(11. (2)·
~
.,
I.
Phase Angle Between
1
Signal and .Comparator
2
Locks On Harmonic of
Center Frequency
lp"fL
2 Ie "'; -;:;-
OUT
Signal Input
Noise Rejecti~n
*C2
Yes
No
High
Low
.
(1) F. Gardner, "Phase-Lock Techniques" John Wiley and Sons. New York, 1966
(2) G. S. Moschytz, "Miniaturized Re Filters Using Phase-Locked Loop", BSTJ, May, 1965.
~
veo
I
INPUT (TERM.9)-LOW-PASS FILTER
OUTPUT
J1..I1S1..r-VOD
...............
-Vss
Fig.3 - Typical waveforms for COS/MOS phase·
locked loop employing. phase comparator
I in locked condition o('fo .
900 at center frequency (fo) approximating 0°
and 180 0 at ends of lock range (2 III
Always 00 in lock
__________________________
~
92CS-ZOOIORI
fC = fL
For further information, see
SIGNAL INPUT (TERM. 141
f~~:~~~~ :~~~~ 4)- ~
~~T~~.AW
For 2 Ie. see ReI. (2)
1
2
1
2
.
0
90·
180·
SIGNAL-TO- COMPARATOR
Fig.2 - Phase-comparator I characteristics
at low-pass filter output.
92CS-21iC)1
2
~
INPUTS PHASE OIFFERENCE
Same as lor No.1
t
Loop Filter
~
2 IL = lull veo Irequency range
2 IL = Imax-Imin
I.
Frequency Capture
§ Voal2
Phase-comparator II is an edge-controlled
digital memory network. It consists of four
flip-flop stages, control gating, and a threestate output circuit comprising p- and n-type
drivers having a common output node. When
the p-MOS or noMOS drivers are ON they
pull the output up to VDD or down to
VSS, respectively_ This type of phase comparator acts only on the positive edges of
the signal and comparator inputs. The duty
cycles of the signal and comparator inputs
are not important since positive transitions
________________________________________ 177
CD4046B Types
STATIC ELECTRICAL CHARACTERISTICS
Vo
(V)
LIMITS AT INDICATED TEMPERATURE (oC)
U
Values at -55, +25, +125 Apply to D,F ,H Package! N
I
Values at -40, +25, +85 Apply to E Package
T
+25
S
VIN VDD
(V)
(V)
-55 -40
+85 +125 Min_ Typ_ Max_
Output Low
(Sink) Current
IOL Min.
0.4
0.5
1.5
0,5
0,10
0,15
5
10
15
Output High
(Source)
Current,
IOH Min.
4.6
2.5
9.5
13.5
0,5
0,5
0,10
0.15
5
5
10
15
Output Voltage:
Low-Level,
Term. 4 0,5
driving 0,10
CMOS 0,15
5
10
15
0.05
0.05
0_05
0,5
e.g.
010
Term.3 0,15
5
10
15
4.95
9.95
14.95
CHARACTERISTIC
CONDITIONS
VCO Section
VOL Max.
Output
Voltage:
High-Level,
VOH Min.
Input Current
liN Max.
-
0_64
1.6
4.2
0.61
1.5
4
-0.64 -0.61
-2 -1.8
-1.6 -1.5
-4
-4.2
to.l
0.42
1.1
2.8
0.36
0.9
2.4
0.51
1.3
3.4
1
2.6
6.8
-0.42 -0.36 0.51
-1.3 -1.15 -1.6
-1.1 -0.9 -1.3
-2.8 -2.4 -3.4
-1
-3.2
-2.6
-6.8
-
4.95
9.95
14.95
tl
tl
10
15
-
mA
-
-
-
+10-5 ±0.1 Il A
-
0,18
18
0,5
0,10
0,15
0,20
5
10
15
20
0.1
0.5
1.5
4
-
0,5
0,10
0,15
0,20
5
10
15
20
20
40
80
160
Ouiput Low
(Sink) Current
IOL Min.
0.4
0.5
1.5
0,5
0,10
0,15
5
10
15
Output High
(Sourcel
Current
IOH Min.
4.6
0,5
0,5
0,10
0,15
5
5
10
15
-
5
10
1.5
3
-
-
-
-
-
15
4
-
-
5
10
15
3.5
3.5
7
7
-
11
11
-
-
-
0 0.05
0 0.05
0 0.05 V
5
-
-
to.l
-
Phase Comparator Section
-
Total Device
Current, I DD Max.
Term. 14 open,
Term.5=VDD
-
Term. 14 = VSS
or VDD' Term. 5
= VDD
-
2.5
9.5
13_5
DC-Coupled
Signal Input and
Comparator Input
Voliage Sensitivity 0.5,4.5
1,9
Low Level
1.5,13.5
VIL Max.
High Level
VIH Min.
0.5,4.5
1,9
1.5 13.5
control the PLL system utilizing this type
of comparator.
I f the signal-input frequency is higher than the comparator-input
frequency, the p-type output driver is maintained ON most of the time, and both the
nand p drivers OFF (3 state) the remainder
178
-
-
0.64
1.6
4.2
-
0.05
0.25
-
0.75
2
-
-
10
20
40
80
20
40
80
160
1
2.6
6.8
-1
-3.2
-2.6
-6.8
-
-
-
0.61
1.5
4
0.42
1.1
2.8
0.36
0_9
2.4
0.51
1.3
3.4
f-0.64 -0.61
-1.8
-2
-1.6 -1.5
-4
-4.2
-0.42
-1.3
-1.1
-2.8
0.36
1.15
-0.9
-2.4
0.51
-1.6
-1.3
-3.4
of the time_ If the signal-input frequency
is lower than the comparator-input frequency, the n-type output driver is maintained
ON most of the time, and both the nand
p drivers OFF (3 state) the remainder of
the time_ If the signal- and comparator-
0.1
0.5 mA
1.5
4
P-A
mA
-
1.5
3
4 V
-
-
input frequencies are the same, but the
signal input lags the comparator input in
phase, the n-type output driver is maintained ON for a time corresponding to the
phase difference_ If the signal- and comparator-input frequencies are the same, but
CD40468 Types
STATIC ELECTRICAL CHARACTERISTICS
LIMITS AT INDICATED TEMPERATURE (OCI
CHARACTERISTIC
U
CONDITIONS
Values at -55, +25, +125 Apply to D,F,H Packages N
I
Values at -40, +25, +85 Apply to E Package
T
+25
S
Vo
VIN VDD
(VI
(VI (VI -55 -40
+85 +125 Min_ Typ_ Max_
Phase Comparator Section (cont'dl
Input Current
liN Max.
(except Term.14)
3-State Leakage
Current,
lOUT Max.
0,18
0,18 18
±0.1
±0.1
±1
±1
-
±10- 5 ±0.1 IlA
0,18
±0.4
±0.4
±12
±12
-
±10- 4 ±0.4 !lA
18
ELECTRICAL CHARACTERISTICS at TA = 25°C
CHARACTERISTIC
TEST CONDITIONS
VDD
(VI
I
LIMITS
ALL TYPES
iUNITS
Min.
TVD. Max.
the comparator input lags the signal in phase,
the p-type output driver is maintained ON
for a time corresponding to the phase difference. Subsequently, the capacitor voltage
of the low-pass filter connected to this phase
comparator is adjusted until the signal and
comparator inputs are equal in both phase
and frequency. At this stable point both pand n-type output drivers remain OFF and
thus the phase comparator output becomes
an open circuit and holds the voltage on the
capacitor of the low-pass filter constant.
Moreover the signal at the "phase pulses"
output is a high level which can be used for
indicating a locked condition. Thus, for
phase comparator II, no phase difference
exists between signal and comparator input
over the full VCO frequency range. Moreover, the power dissipation due to the lowpass filter is reduced when this type of phase
comparator is used because both the p- and
n-type output drivers are OFF for most of
the signal input cycle. It should be noted
that the PLL lock range for this type of phase
comparator is equal to the capture range,
independent of the low-pass filter. With no
signal present at the signal input, the VCO
is adjusted to its lowest frequency for phase
comparator II. Fig. 10 shows typical waveforms for a COS/MOS PLL employing phase
comparator II in a locked condition.
VCO Section
Operating Power
Dissipation, P D
Maximum
Operating
Frequency f max
fo=10kHz
R2 = 00
C 1=50 pF
R2 = 00
VCOIWVDD
C1 = 50 pF
R2 = 00
VCOIWVDD
Center Frequency
(fol and Frequency
Range
(fmax-fmin)
R1 = 1 MU
VD D
VCOIN= -2-
R1 = 10 kU
R1 = 5 kU
Temperature Frequency
Stability:
No Frequency
Offset fMIN = 0
Frequency
Offset
fMIN l' 0
Output Duty
Cycle
Output Transi'tion
Times,
tTHL' tTLH
70 140
800 1600
3000 6000
-
5
10
15
0.3
0.6
0.8
0.6
1.2
1.6
5
10
15
0.5
1
1.4
0.8
1.4
2.4
IlW
AMBIENT TEMPERATURE {TAI-25·C
10'b-+-+d-_-+...:V:..CO:.:.N:.,.',.:VD::.O'_Z':"'.,z_,m..:..'_NH_'.,'T_'V.:S:.S-I
-
-
MHz
Programmable with external components R 1, R2, and C1
IO"~
See Design Information
VCOIN = 2.5 V ± 0.3V, R,=10 kU
Linearity
-
5
10
15
=5V ± 1 V,
-5 V ± 2.5 V,
=7.5V±1.5V,
= 7.5 V ± 5 V,
= 100kU
-400 kU
= 100kU
=1MU
5
-
1.7
-
-
0.5
4
0.5
7
-
5
10
15
-
±0.12
±0.04
±0.015
-
±0.09
±0.07
±0.03
-
-
-
-
-
-
5,10,15
-
50
-
100
50
40
5
10
15
-,
10"2
10- 1
TIMING CAPACITOR {Cl}-,.F
10
92CS-30347
Fig. 4 - Typical center frequency as a function of
ClandRlat V DD -5 V,10 V,and 1511.
%
-
f
:.
IO!!i
),----'~-"'~
~ I04'~---''''''''~
%fC
5
10
15
LO·3
veo
10
10
15
15
-
10"4
~
~
=
l!!
~
-
-
%
200
100
80
ns
lo3b--+----'
102')'--+--l---''~
,ob--+---+---+-=
10-5
10-4
10-3
veo TIMING
10-2
10-1
CAPACITOR (CIl-,.F
10
92CS-30353
Fig. 5 - Center frequency as B function of Ct and
R 1 fgr ambienJ temperatures of
-55
fio
125 C.
179
CD4046B Types
ELECTRICAL CHARACTERISTICS at TA = 25°C
CHARAC·
TERISTIC
TEST CONDITIONS
VDD
(V)
LIMITS
ALL TYPES
Min.
UNITS
Typ.
Max.
-
1.8
1.8
1.8
2.5
2.5
2.5
-
0.3
0.7
0.9-
-
%
IZ=50ILA
4.45
5.5
6.15
V
IZ= 1 mA
-
40
-
n
5
10
15
1
0.2
0_1
2
OA
-
Mn
0.2
-
5
10
15
-
VCO Section (cont'd)
Source· Follower
Output (Demodu·
lated Output):
Offset Voltage
(VCOIN-VDEM)
RS> 10kn
RS=100 kn
=300kn
=500kn
Linearity
Zener Diode
Voltage (V z)
Zener Dynamic
Resistance, R z
VCOIN = 2.5±0.3 V
=5±2.5V
= 7.5± 5 V
5
10
15
5
10
15
10V
--t~~~~"'F'S~s~
V
IOV
-+--N~~S~~
,V
10V
IO-~
10-4
veo
10-3
10
10-2.
10- 1
I
TIMING CAPACITOR ICII- ~F 92CS-3~46
Fig. 6 - Typical frequency offset as a function of
C1 and R2 for VDD = 5 V, 10 V, and
15 V_
Phase Comparator Section
Term. 111 (SIGNAL
IN) Input
Resistance
R14
AC Coupled
Signal Input
Voltage Sensitivity* (peakto-peak)
fiN = 100 kHz,
sine wave
Propagation Delay
Times, Terms_ 14
to 13: High to
Low Level, tpHL
5
10
15
5
10
15
Low to High
Level, tpLH
3-State Propagation
Delay Times,
Terms. 14 to 13:
High Level to
High Impedance,
5
10
15
-
-
-
-
180 360
330 660 mV
900 1800
225
100
65
450
200
130
ns
350
150
100
700
300
200
ns
225
100
95
450
200
190
ns
veo
TIMING CAPACITOR (Cll- "~2CS-3Ol52
Fig. 7 - Frequency offset as a function of
C1 and R2 fo~ambient !emperatures of -55 C to 125 C.
looa
z
.
?
,
,,
10
tpHZ
0.01
R2IRI
Low Level to
High Impedance,
,
tpLZ
Input Rise or Fall
Times, t r , tf
Comparator
Input, Term. 3
Signal Input,
Term. 14
Output Transition
Times, tTHL, tTLH
See Fig. 5 for Phase Compo "
output loading
5
10
15
-
285
130
95
570
260
190
ns
5
10
15
-
-
50
1
0.3
ILs
5
10
15
5
10
15
-
-
-
-
-
100
50
40
• For sine wave, the frequency must be greater than 10 kHz for Phase Comparator II.
-
-
500
20
2.5
200
100
80
92CS-303M
Fig. 8 - TVPical fMAX/fMINas a function of
R2IRI.
ILS
ns
10
10
AI -
k.Q
vr:s- !OM8
Fig. 9 - Typical VCO power dissipation at center
frequency as a function of R 1.
180 _______________________________________________________________
CD4046B Types
4
VD
PHASE COMPARATOR
OUTPUT tTERM.131
yeo
•
n
PHASE
COMPARATOR
OUTPUT
~-VDO
INPUT (TERM. 91 ~
LOW~PASS
-"._::~~
_.JI- - - +- - - - _
FILTER
20
ten
.
-VSS
OUTPUT
n
13
~-VOO
PHASE PULSE I TERM. II
: Kn
2 Ka
Vss
-YSS
NOTE: DASHED LINE IS AN OPEN.(;IRCUIT
92CS20011R2
CONDITION lard STATE)
Fig. I I - Phase comparator II
. Fig. 10 - Typical waveforms for COS/MaS phase·locked loop
employing phase comparator II in locked condition.
output loading circuit.
10
•• 0
•• I
•• 0
ID'
10
...
~
I
;; 10"
1
»
~;
~
~~1038
~
~
00
~...
~
I
of
15 11'02
2
..
68103
Z
,
""
RI-IcO
Fig. 13 - Typical source follower power
dissipation as a function of Rs.
VDD
"'r-
13
VOUT
Z k.o.
8 AMBIENT TEMPERATURE (TAl o 2S-CI
: VOD·IOV.VCOIN·~VtIV,R2.«I
I
vs.
OUTPUT CIRCUIT
~
~
,.../
2
~
:
......
,
"
• I
Fig. 12- Typical VCOpowerdissipation at fMIN
as a function of R2.
~
"'- ?v""
,
§~ 10
~ 10
10
~I,~",....
o~
.
9ZCS-30349
aOUl
·,
I~ ·
1f01.t-4GE
i~ lot r--
,
~_ IO"~
~
i~ao' ~.
~\o'DoJ",~
I
! ::~~N~O~::~~~~U~E (TAI'2S'~J
AMBIENT TEMPERATURE ITA) -2S'C
veo lN 'YoolZ, RI' Rt. aD
I
'of>
10'"
10'
R2-kil
,
... , ... , , ..
10
10 2
103
SIGNAL INPUT FREQUENCY (fINI- kHI
,
.
1-----+---+---1------1
108
pF
100 pF
CI.~O
l?:
~~
1000pF
,
II
r----+---~~~-t_~\f
, f(4V!+f(6VI ~
0 .....
104
I
'0' - - , - -
92CS-30350
Fig. 14 - AC-coupled signal input voltage as a
function of signal input frequency.
2
~::::J<':-_-::--"1
" -'(5VI
% LINEARITY = ~ X 100
~,..
0.01 pF
10'1
10-12
-4
68 1
2
-4
68 10
2
4 68102 2
4
68103
RI-kG
Fig. 15 - Typical VCO linearity as a function of
R1 and C1 at V DD = 10 V.
95-103
(2.413-2.6161
68
I
2
4
68
10
RI-kn
Fig. 16 - Typical VCO linearity as a function of
RI and C1 at V DD = 15 V.
Dimensions and pad layout for CD4046BH.
D,mens,ons in parentheses are In millimeters and
are derived from the basic inch dimensions as indicated. Grid graduations are in mils (Hr- 3 Inch).
85-93
92CM-30356
The photographs and dimensions represent a chip when it is part of the
wafer. When the wafer is cut intg
chips, the c/f§'vage angles are 57
instead of 90 with respect to the
face of the chip. Therefore, the isolated chip is actually 7 mils (0.17 mm)
larger in both dimensions.
____________________________________________________________________ 181
CD4047B Types
COS/MaS Low·Power
Monostable/Astable
Multivibrator
High Voltage Types (20·Volt Rating)
The RCA·CD4047B consists of a gatable
astable multivibrator with logic techni·
ques incorporated to permit positive or
negative edge·triggered monostable
multivibrator action with retriggering and
external counting options.
Inputs incluc!!L.±.lB!GGER, -TRIGGER,
ASTABLE, ASTABLE, RETRIGGER, and
EXTERNAL RESET. Buffered outputs are
a, a, and OSCILLATOR. In all modes of
operation, and external caP1!citor must be
connected between C·Timing and RC·
Common terminals, and an external
resistor must be connected between the
R·Timing and RC·Common terminals.
Astable operation is enabled by a high
level on the ASTABLE input or a low level
on the ASTABLE input, or both. ThJl.
period of the square wave at the a and a
Outputs in this mode of operation is a
function of the external components
employed. "True" input pulses on the
ASTABLE input or "Complement" pulses
on the ASTABLE input allow the circuit to
be used as a gatable multivibrator. The
OSCILLATOR output period will be half of
the
terminal output in the astable
mode. However, a 50% duty cycle is not
guaranteed at this output.
a
The CD4047B triggers in the monostable
mode when a positive·going edge occurs
on the + TRIGGER·input while the
-TRIGGER is held high. Input pulses
may be of any duration relative to the out·
put pulse.
If retrigger capability is desired, the
RETRIGGER input is pulsed. The retrig·
gerable mode of operation is limited to
positive·going edge. The CD4047B will
retrigger as long as the RETRIGGER·input
is hiqh, with or without transitions (See
Fig. 34).
An external countdown option can be im·
plemented by coupling "a" to an external
"N" counter and resetting the counter
with the trigger pulse. The counter output
pulse is fed back to the ASTABLE input
and has a duration equal to N times the
period of the multivibrator.
A high level on the EXTERNAL RESET in·
put assures no output pulse during an
"ON" power condition. This input can
also be activated to terminate the output
pulse at any time, for monostable opera·
tion, whenever VpD is applied, an internal
power-on reset circuit will clock the out·
put low within one output period (tM)'
a
The CD4047B-Series types are supplied in
14-lead hermetic d ual-i n-li ne cera mic packages (D and F suffixes), 14-lead dual-in-line
plastic packages (E suffix), 14-lead ceramic
flat packages (K suffix), and in chip form (H
suffix).
Features:
• Low power consumption: special COS/MaS
oscillator configuration
• Monostable (one·shot) or astable (free·running)
operation
• True and complemented buffered outputs
• Only one external Rand C required
• Buffered inputs
• 100% tested for quiescent current at 20 V
• Standardized, symml'trical output
characteristics
• S·V, 10'V, and 1S·V parametric ratings
'. Meets all requirements of JEDEC
Tentative Standard No. 13B,
"Standard Specifications for
Description of 'B'
Series CMOS Devices"
Monostable Multivibrator Features:
• Positive· or negative·edge trigger
• Output pulse width independent of
trigger pulse duration
• Retriggerable option for pulse width
expansion
• Internal power'on reset circuit
• Long pulse widths possible u~ing small
RC components by means of exter·
nal counter provision
• Fast recovery time essentially indepen·
dent of pulse width
• Pulse·width accuracy maintained at
duty cycles approaching 100%
Astable Multivibrator Features:
• Free·running 'or gat able operating
modes
• SO% duty cycle
C
R
R-C COMMON
ASTABLE
ASTABLE
-TRIGGER
Vss
TOP VIEW
92CS-2143'RI
Terminal Diagram
• Oscillator output availabfe
• Good astable frequency stability:
Frequency deviation:
= ± 2% + 0.03%/'C @ 100 kHz
±O.S% +0.01S%I"C @ 10kHz
(circuits "trimmed" to frequency
VDD = 10 V ± 10%)
=
Applications:
Digital equipment where low·power
dissipation and/or high noise immunity
are primary design requirements:
• En velope detection
• Frequency multiplication
• Frequency division
• Frequency discriminators
• Timing circuits
• Time·delayapplications
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so
that operation is always within the following ranges:
CHARACTERISTIC
Supply·Voltage Range (For T A - Full Package·Temperature
Ranqe)
LIMITS
MIN.
MAX.
UNITS
I
V
I
3
18
NOTE: IF AT 15 V OPERATION A 10 MQ RESISTOR IS USED THE OPERATING
TEMPERATURE SHOULD BE BETWEEN -25'e and 100'e
MAXIMUM RATINGS, Absolute·Maximum Values:
DC SUPPLY·VOLTAGE RANGE, (V DD)
(Voltage referenced to VSS Terminal) .......................,................ -0.5to +20V
INPUT VOLTAGE RANGE, ALL INPUTS ................................... -0.5toVDD +0.5V
DCINPUTCURRENT,ANYONEINPUT ............................................. ±10mA
POWER DISSIPATION PER PACKAGE (PO):
ForTA = -40to +60'C(PACKAGETYPEE) ....................................... 500mW
For TA + 60 to + 85'C (PACKAGE TYPE E) ............... Derate Linearly al 12 mW/'Clo 200 mW
ForT A = -5510 +100·C(PACKAGETYPESD,F) ................................... 500mW
ForTA = + 10010 + 125'C (PACKAGE TYPES D,F) ....... Derale Linearlyal 12mW/'Clo 200mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FORT A = FULL PACKAGE·TEMPERATURE RANGE (All Package Types) ............. : .100mW
OPERATING·TEMPERATURE RANGE (T A):
PACKAGETYPESD,F,H .................................................. -5510 + 125'C
PACKAGETYPEE ....................... " ............................... -4010 +85'C
STDRAGE TEMPERATURE RANGE (Tstg)' .................................... -6510 + 150'C
LEAD TEMPERATURE (DURING SOLDERING):
AI dislance 1116 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10s max ................... +265'C
182 ________________________________________________________
~
______
CD4047B Types
CD4047B FUNCTIONAL TERMINAL CONNECTIONS
NOTE: IN ALL CASES EXTERNAL RESISTOR BETWEEN TERMINALS 2 AND 3""
EXTERNAL CAPACITOR BETWEEN TERMINALS 1 AND 2""
TERMINAL CONNECTIONS
INPUT
TOVSS
TO
FUNCTION
TOVDD
Astable Multivibrator:
4,5,6,14
7,8,9,12
Free Running
4,6,14
7,8,9,12
.True Gating
Complement Gating
6,14
5,7,8,9,12'
Monostable Multivibrator:
Positive·Edge Trigger
4,14
5,6,7,9,12
Negative·Edge Trigger 4,8,14
5,7,9,12
5,6,7,8,9
Retriggerable
4,14
External Countdown
14
5,6,7,8,9,12
5
4
OUTPUT
PULSE
FROM
10,11,13 tA (10,11) = 4.40 RC
10,11,13 tA (13) = 2.20 RC#
10,11,13
10,11
10,11
10,11
10,11
8
6
12
.
OUTPUT PERIOD
OR
PULSE WIDTH
-
tM (10,11) =2.48 RC
... See Text.
# First positive Y, cycle pulse·width
= 2.48 RC, see Note On Page 10.
• Input Pulse to Reset of External Counting Chip External Counting Chip Output To Terminal 4
C-TlNING
I--R.;---I
/------+1--(113
COMMON
I
l--"===--+-~ ASTABLE
GATE
CONTROL
92CS-29071
Fig. l-CD4047B logic block diagram.
erc
RETRIGGER
RTC
ASTABLE
+TRIGGER
-TRIGGER
VD D
* INPUTS
PROTECTED BY ~
COS/MOS PROTECTION
--NETWORK
vss
DD
~
CAUTION- TERMINAL 31SMORE
** SPECIAL RC COMMON
PROTECTION NETWO::,"
SENSITIVE TO STATIC
ELECTRICAL DISCHARGE.
EXTRA HANDLING PRE-
C:Uo:',:~S ARE RECOMMENDED.
Vss
Fig. 2-CD4047B logic diagram.
- - - - - - - - - -_______________________________________________________ 183
CD4047B Types
DRAIN-lO-SOURCE VOLTAGE
(Yosl-V
~U
RI R2
FFI, FF3
¢
'12~S-~43~(!F14
Fig. 6- Typical output high (source) current
characteristics.
SQ
CL
C[
RQ
DRAIN-lO-SOURCE VOLTAGE (Vos)-V
-15
FF2, FF4
-10
-5
AMBIENT TEMPfRATURE [TAI-25·C
nCM-29040
Fig. 3-Detaillogic diagram for flip·flops FF1 and FF3 (a) and for flip·flops FF2 and FF4 (b).
-IOV
-15 V
Fig. 7-Minimum output high (source) ~~~~;;~;'
characteristics.
I
DRAIN-lO-SOURCE VOLTAGE (YoSI-V
DRAIN-lO-SOURCE VOLTAGE IYoS)-V
Fig. 4- Typfcal output low (sink) current
characteristics.
Fig. 5-Minimum output low (sink) current
characteristics.
STATIC ELECTRICAL CHARACTERISTICS
CHARAC·
TERIS·
TICS
liMITS AT INDICATED TEMPERATURES ("C)
Values at ·55,+25,+ 125 Apply to D,F,H Packages
Values at ·40, + 25, + 85 Apply to E Package
CONDITIONS
+25
Vo
(V)
VIN
(V)
VDD
(V)
-55
-40
+85
+125 Min.
Quiescent
Device Cur·
rent, 100
Max.
-
Output low
Low (Sink)
Current
IOlMin.
Output High
(Source)
Current,
IOH Min.
Output Voltage: Low·
Level VOL
Max.
0.4
0.5
0,5
0,10
0,15
0,20
0,5
0,10
5
10
15
20
5
10
1
2
4
20
0.64
1.6
1
2
4
20
0.61
1.5
30
60
120
600
0.42
1.1
30
60
120
600
0.36
0.9
1.5
0,15
15
4.2
4
2.8
2.4
4.6
2.5'
9.5
13.5
0,5
0,5
0,10
0,15
0,5
0,10
5
5
10
15
5
10
0,15
15
-
I
-0.64 -0.61 -0.42
-2 -1.8 -1.3
-1.6 -1.5 -1.1
-4.2 -4 -2.8
0.05
0.05
0.05
-0.36
-1.15
-0.9
-2.4
UNITS
Typ.
Max.
1
2
4
20
0.51
1.3
0.02
0.02
0.02
0.04
1
2.6
3.4
6.8
-
-0.51
1
-1.6 -3.2
-1.3 -2.6
-3.4 -6.8
0
0
-
0
LOAD
(CL.l-pF
Fig. 8- Typical propagation delay time as a
function of load capacitance (Astable,
Astable to Q. QJ.
"A
-
-
rnA
-
0.05
0.05
0.05
LOAD CAPACITANCE 1CL.I-pF
V
Fig. 9- Typical propagation delay time as a
function of load capacitance (+ or
- trigger to Q,
OJ.
184 _______________________________________________________________________
CD4047B Types
STATIC ELECTRICAL CHARACTERISTICS (CONTINUED)
CHARAC·
TERIS·
TICS
Output Volt·
age: High·
Level, VOH
Min.
LIMITS AT INDICATED TEMPERATURES ("C)
Values at ·55, +25,+125 Apply to D,F,H Packages
Values at ·40, + 25, + 85 Apply to E Package
+25
UNITS
VDD
(VI
-55/ -40 1+85 1+125 Min. Typ. Max.
CONDITIONS
Vo
(VI
VIN
-
0.5
010
0,15
-
Input Low 0.5,4.5
Voltage, VIL 1,9
Max.
1.5,13.5
(V)
5
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5
10
15
-
5
1.5
-
10
15
3
4
-
-
5
10
15
3.5
7
11
Input High 0.5,4.5
Voltage,
1.9
VIH Min. 1.5,13.5
Input Cur·
0,18
rent liN
Max.
-
18
±0.11 ±0.1
-
I I
±1
±1
V
1.5
3
4
-
3.5
7
11
-
-
-
V
-
-
Fig. 10-Typical transition time as a function
of load capacitance.
-
4 AMBIENT TEMPERATURE ITA )- 25·C
Cx· I ... F
3
±105 ±0.1
p.A
~
2
~
I
i
-I
,
!:l
~
~ -2
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C, Input tr , tf = 20 ns,
CL = 50pF, RL = 200kQ
VDD
CHARACTERISTICS
(VI
Propagation Delay Time:
Astable, Astable to Osc. Out
tpHL, tpLH
-
Astable, Astable to Q, Q
+ or - Trigger to Q, Q
Retrigger to Q, Q
External Reset to Q, Q
Transition Time:
Osc. Out, Q, Q
Minimum Input Pulse Width:
+ Trigger, - Trigger
tTHL, tTLH
tw
Reset
Retrigger
Input Rise and Fall Time:
All Inputs
tr,tl
Q or Q Deviation Irom 50%
Duty Factor
Input Capacitance,
CIN
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
Any
Input
Min.
-
-
-
-
-
-
-
LIMITS
Typ.
Max.
200
100
80
350
175
125
500
225
150
300
150
100
250
100
70
100
50
40
200
80
50
100
50
30
300
115
75
400
200
160
700
350
250
1000
450
300
600
300
200
500
200
140
200
100
80
400
160
100
200
100
60
600
230
150
Unlimited
-
-
±0.5
±0.5
+0.1
-
5
UNITS
-3
-.
o
6
8
10
12
14
SUPPLY VOL.TAGE IVool-V
16
18
20
Fig. II-Typical astable oscillator or Q, Q
period accuracy vs. supply voltage.
ns
SUPPLY VOLTAGE 'Vool-V
9~CS-32,,,i
-cr
Fig. 12-Typical astable oscillator or Q,
period accuracy vs. supply voltage.
p's
±1
±1
. ±0.5
%
7.7
pF
I
SUPPLY VOLTAGE IVooJ-V
Fig. 13- Typical astable oscillator or Q, Q
period accuracy vs. supply voltage.
__________________________________________________________________ 185
CD4047B Types
2
cx. O.OI ....F
R
"'5
AMBIENT TEMPERATURE ITA ) -
·c
Fig. 14"'- Typical astable oscillator or Q, Q
period accuracy vs. ambient temper·
ature (ultra-low frequency).
65
85
105
125
-2
-55
145
-roo
-35
AMBIENT TEMPERATURE (T A I-·C
kn
-15
25
45
65
85
105
125
145
AMBIENT TEMPERATURE (fA J_·C
Fig. 15-Typical astable oscillator or Q, Q
period accuracy vs. ambient temper'
ature (low frequency).
Fig. 16- Typical astable oscillator or Q, Q
period accuracy vs. ambient temper·
ature (medium frequency).
I
I
AMBIENT TEMPERATURE (TA)-·C
Fig. 17- Typical astabfe oscillator or Q, 0period accuracy vs. ambient temperature (high-frequency).
SUPPLY VOL.TAGE (Vool-V
Fig. 20- Typical output pulse-width variations
vs. supply voltage.
AMBIENT TEMPERATURE ITA )_·C
FIg. 18- Typical astable oscillator or Q,
period accuracy vs. ambient
temperature.
SUPPL.Y VOLTAGE (VOOI-V
Q
Fig. 19-Typical output pulse·width variations
vs. supply voltage.
I
SUPPLY VOLTAGE 1Voo)-V
Fig. 21- Typical output pulse-width
variations vs. supply voltage.
AMBIENT TEMPERATURE ITA)- ·C
Fig. 22- Typical output pulse·width variations
vs. ambient temperature.
§
'" Cx"IOOOpF.
2 SUPPL.Y VOLTAGE (Vool-ISV
~
g
tOkA
0 laMa
!;;[ -2
100 lin
100 kn
RX·'MO
10kn
~
> -.
~
~;
~
ir
-8
Ion
~
~
-10
°_12
-55
AMBI~~T
TEMPERATURE CTAI-·C
Fig. 23- Typical output pulse-width variations
vs. ambient temperature.
AMBIENT TEMPERATURE IT A )_·C
Fig. 24- Typical output·pulse-width variations
vs. ambient temperature.
IOMa
-35
-15
5.25456585
105
125
145
AMBIENT TEMPERATURE (TAI- ·C
Fig. 25- Typical output pulse-width variations
vs. ambient temperature.
186 __________________________________________________________________
CD4047B Types
IO~ ASTABLE MODE
L06
SUPPLY VOLTAGE IVOOI':'V
ASTABLE MOOE
SUPPLY VOLTAGIE 1VOOI'15V
,,'
,,'r--j---j---+---+--+-+---1
'0'
~'b-'
10
'0'
ASTABLE MOOE
SUPPLY VOLTAGE 1Vool'IO V
c..
/
'0'
0:0.'1'
11/
V
I/~~ r--
/
~~OO~
0.0\'1'
oO~
':/~
,
0
".t----j---+---+--+-+-~
"
c.. \
C:'
;/
,
"
,,'
,
,
.
,
10
.
Fig. 26- Typical power dissipation vs. output
frequency (V 00 = 5 Vi.
,
~tt
_c'./~
~
c'~
c'
,,'
,,'-F---+--+----=+-'----+-+--+----1
10
_10
10
La
QOR Q FREQUENCY If)-HE
_7"
0
,
,
,
10
10
10
10
CORQ FREQUENCY III-Hz
Fig. 27- Typical power dissipation vs. output
frequency (VOO = 10 Vi.
'.
Fig. 28-Typical power dissipation vs. output
Irequency (V00 = 15 Vi.
VDO
:~"'oo.~
INPUTS
o
Vss
Vss
NOTE:
VDD
~
MEASURE INPUTS
SEQUENTIALLY.
Vss
NOTE:
TEST ANY COMBINATION
OF INPUTS EXCEPT PIN 3
92CS·27441R1
L-----,_--'
Voo OR VSS'
Vss
92CS-27402
Vss
-22249
Functional Diagram
Features:
• Three·state output
a Many logic functions available inane package
• Standardized, symmetrical output
characteristics
• 100% tested for quiescent current at 20 V
• Maximum input current of lilA at 18 V
(full package·temperature range), 100 nA
at 18 V and 250 C
• Naise margin (full package·temperature
range) = 1 Vat VDD=5 V, 2 V at VDD
= 10 V, 2.5 Vat VDD=15 V
• 5·V, 10·V, and 15·V parametric ratings
• Meets all requirements of JEDEC Tentative
Standard No. 13A, "Standard Specifications
for Description of '8' Series CMOS Devices"
Applications:
NOR
A!y-
C
0
E
G
F
H
EXP
Ay A9OR
C
E
G
0
F
H
~
0
G
H
A~
C
E
G
ExP
EXP
ORlAND
AND
NAND
0
F
H
EXP
OR/NAND
ANO/OR
• Selection of up to 8 logic functions
• Digital control of logic
• General·purpose gating logic
- Decoding
- Encoding
ANOINOR
~~~~;~;Qy
Fig. 1 - Basic logic configurations.
J(OUTPuT)
Kd
I.,.
Voo
EXPAND
" ~}NPUTS
"
INPUTS~
"
12
10
9
K,
Vss
K,
K,
TOP VIEW
RECOMMENDED OPERATING CONDITIONS
i
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the fol/owing ranges:
LIMITS
CHARACTERISTIC
Supply·Voltage Range (For T A
Temperature Range)
= Full Package
MIN.
MAX.
3
18
TERMINAL ASSIGNMENT
UNITS
V
__________________________________________________________________ 189
CD4048B Types
K.
*KO
*Kb
*Kc
*Kd
t~~
r - - = - - - ' '. T.
ft fL
Voo
DRAIN-TO-SOURCE VOLTAGE (Vos)-V
Fig. a - Typical output low (sink)
current characteristics.
Fig. 2 - Logic diagram.
NOR
ORAIN-'·O-"OU'''' VOLTAGE
NAND
"~
12
"
Fig. 7 - Minimum output low (sink)
current characteristics.
14
••
i
I
DRAIN-lO-SOURCE VOLTAGE {Vos)-V
I
Ka-Kb-Kc:
0-0-0
ANO
OR
AND/NOR
AND lOR
OR lAND
OR/NAND
Fig. 3 -
Actua/~ircuit
logic configurations.
Fig. 8 - Typical output high (source)
current characteristics.
DRAIN-TO-SOURCE VOLTAGE IVosl-V
-15
-10
-5
AMBIENT TEMPERATURE ITA"25"C
APPLICATIONS OF EXPAND INPUT
.,
Voo
-IOV
J IOUTPUT)
·0
Voo
-15 V
12- INPUT OAIAND GATE
J.'
16-INPUT NOR GATE
A+B+C+O}" E+F+G+H)' IXI+1C2+X3+J(4)
Fig. 4 - 12·input ORlAND gate.
."
Fig. 9 - Minimum output high (source)
Fig. 5 - la·input NOR gate.
current characteristics.
190 ________________________________________________________________
~--
CD4048B Types
STATIC ELECTRICAL CHARACTERISTICS
AMBIENT TEMPERATURE lTAlo25"C
LIMITS AT INDICATED TEMPERATURES (OC)
Values at -55, +25, +125 Apply to D,IF,H Packages
Values at -40, +25, +85 Apply to E Package
+25
VDD
Typ.
+85
+125 Min.
Max.
(V) -55 -40
0.01
0.25
5
0.25 0.25
7.5
7.5
CONDITIONS
CHARACTER·
ISTIC
Quiescent Device
Current,
100 Max.
Output Low
(Sink) Current
IOL Min.
Output High
(Source)
Current,
IOH Min.
Output Voltage:
Low-Level,
Vo
(V)
-
0,5
_.
0,10
0,15
10
15
VIH Min.
0.01
0.01
0.5
1
-
0.02
0.51
1
2.6
5
-
5
5
5
0.64
0.61
0.42
0.5
0,10
1.6
1.5
1.1
1.5
0,15
10
15
4.6
5
2.5
9.5
13.5
0.5
0,5
5
4.2
4
-0.64 -0.61
-2
-1.8
0.10
0.15
10
15
-1.6
-4.2
-
0,5
5
-
0.10
10
15
5
10
15
4.95
9.95
14.95
4.95
9.95
14.95
-
5
1.5
-
-
1.5
1,9
1.5,13.5
-
10
3
-
-
15
4
-
-
0.5,4.5
1,9
-
5
3.5
3.5
-
3
4
-
-
7
-
-
-
10
15
7
1.5,13.5
11
11
-
-
Input Current
liN Max.
3·State Output
Current, lOUT
-
20
~.4.5
Voltage,
-
15
30
0,5
-
Input High
1 15
30
150
0,20
-
Voltage,
VIL Max.
0.5
1
-
-
Input Low
0:5
1
0.4
VOL Max.
Output Voltage:
High·Level.
VOH Min.
VIN
(V)
0,18
0.15
0.5
0.10
0,15
150
0.36
6.8
-1
-
-1.3
-1.1
-1.15 -1.6
-3.2
-
-0.9
-2.4
-304
-2.6
-6.8
-
-2.8
0.05
-
0
0.05
0.05
-
0
0.05
-
0
5
0.05
0.05
-1.5
-4
-1.3
10
15
0,18
18
±0.1
±0.1
±1
±1
-
±10- 5
0,18
18
±OA
±OA
±12
±12
-
±10- 4
200
/1 A
20
-
0.9
1.3
2.4
3.4
-0.36 -0.51
2.8
-0.42
UNITS
-
mA
""
GO
LOAO CAPACITANCE (CLI-pF
Fig. 10 - Typical propagation delay time
(logic inputs to output)
as a function of load capacitance.
-
V
-
-
V
±0.1
/1 A
±OA
/1 A
Fig. 11 - Typical transition time vs. load capacitance.
IMPLEMENTATION OF EXPAND INPUT FOR 9 OR MORE INPUTS
OUTPUT
FUNCTION
FUNCTION
NEEDED AT
EXPAND INPUT
OUTPUT BOOLEAN
EXPRESSION
NOR
OR
J-(A+B+C+D+E+F+G+HI+(EXP)
OR
OR
J=(A+B+C+D+E+F+G+H)+(EXP)
AND
NAND
J=(ABCDEFGH)'(EXP)
NAND
NAND
J=(ABCDEFGHI'(EXP)
OR/AND
NOR
J=(A+B+C+DI'(E+F+G+H)'(EXP)
OR/NAND
NOR
J=(A+B+C+D)'(E+F+G+H)'(EXP)
AND/NOR
AND
J-(ABCD)+(EFGH)+(EXP)
AND/OR
AND
J=(ABCDI+(EFGH)+(EXP)
NOTE:
Refer to FUNCTION
TRUTH TABLE for
connection of unused
inputs.
2
"6810 2
"6 ~02 2
"6 910~ 2
4 68104 2
INPUT FREOENCY IfIl-kH~
"6 ~o~
92CS-316.n
Fig. 12 - Typical power dissipation as a function of
input frequency.
Note: (EXPl designates the EXPAND function (Le., Xl+X2+' .. XN).
__________________________________________________________________
~19'
CD4048B Types
DYNAMIC CHARACTERISTICS at TA=250C, CL =50 pF, Input t r ,lf=20 ns,
R L=200 kG unless otherwise specified
CHARACTERISTIC
LIMITS
TEST CONDIT~
All Package Types
VDD
Typ.
Max.
V
5
10
15
5
10
15
Propagation Delay: tpHL,tpLH
Inputs to Output and
Ka to Output
300
150
120
600
300
240
450
170
110
280
100
80
Kc to Output
5
10
15
225
85
55
140
50
40
Expand Input to Output
5
10
15
190
90
65
380
180
130
5
10
15
80
35
25
160
70
50
5
10
15
100
50
40
200
100
80
Kb to Output
3-State Propagation Delay:
Kd to Output tpHZ,tpLZ
tpZH,tpZL
Transition Time: tTH L,tTLH
Input Capacitance: CI
RL=l kG
See Fig.21
Any Input
3·State Output Capacitance
5
7
5
10
UNITS
ns
pF
FUNCTION TRUTH TABLE
Voo
UNUSED
OUTPUT
BOOLEAN EXPRESSION Ka Kb Kc
INPUT'
FUNCTION
NOR
OR
OR/AND
OR/NAND
AND
NAND
AND/NOR
AND/OR
Kd=l
Fig. 13 - Dynamic power dissipation test circuit.
J-A+B+C+D+E+F+G+H
J=A+B+C+D+E+F+G+H
J= (A+B+C+D )o(E+F+G+H)
J (A+B+C+D)-(E+F+G+H)
J=ABCDEFGH
J=ABCDEFGH
J=ABCD+EFGH
J=ABCD+EFGH
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
Normal I nverter Action
Kd=O High Impedance Output
* See Figs. 1,2,3,4, and 5.
EXPAND Input=O
TEST CIRCUITS· STATIC MEASUREMENTS
INPUTS
o
Vss
92:CS-i!:744IRI
Fig. 14 - Quiescent device current
test circuit.
Fig. 15 - Input voltage test
circuit.
Fig. 16 - Input current test circuit.
192 ____________________________________________________________________
CD4048B Types
TEST CIRCUITS - DYNAMIC MEASUREMENTS
Voo
IS
OUTPUT
15
INPUT
"
13
INPUT~50%
-50%
INPUT
12
·S
"10
OUTPUT
OUTPUT
~=-~~~
'THL
Vss
Fig. 17 - Test circuit for tpHL'
tTHL' and tTLH (AND)
-t ~
~ I-tTLH
92CS-222.64
92cs-a1671
Fig. 18 - Waveforms for tpHL
and tpHL (AND).
Fig. 19 - Waveforms for tTHL
and tTLH (AND).
measurements.
SOp'
'lIS
Kd
15
14
4
(AND)
13
12
~----~""=
Voo
92CS-51674
92CS- 31669 Dvss
Fig. 21 - Waveforms for tpZL' tpZH'
tpLZ' and tpHZ lAND).
Fig. 20 - Test circuit for tpZL' tpZH' tpLZ'
and tpHZ lAND).
o
10
20
30
40
Dimensions and pad layout for CD4048BH.
Dimensions in parentheses are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch).
50
60
70
77
The photographs and dimensions of each COS/MOS
chip represent a chip when it ;s part of the wafer.
When the wafer ;s cut into chips, the cleavage
angles are 57° instead of 90° with respect to the
face of the chip. Therefore, the isolated chip is
actually 7 mils (0. 17 mm) larger;n both dimensions.
__________________________________________________________________ 193
CD4049UB, CD4050lB Types
COS/MOS
Hex Buffer/Converters Features:
High-Voltage Types (20-Volt Rating)
CD4049UB-1 nvertingType
CD4050B-Non-I'nverting Type
A
•
•
•
•
High sink current for driving 2 TTL loads
High-to-Iow level logic conversion
100% tested for quiescent current at 20 V
Maximum input current of 1p.A at 18 V over full packagetemperature range; 100 nA at 18 V and 2SoC
.5-,10-, and 15-volt parametric ratings
e
~
~
~
~
~
G·i
HoB
Ioe:
J·e
K;E
~~
-
F~L'F
Vee _,_
Vss _a_
Applications:
The RCA-CD4049UB and CD4050B are inverting and non-inverting hex buffers, respectively, and feature logic-level conversion using
only one supply voltage (VCC)- The inputsignal high level (VIH) can exceed the VCC
supply voltage when these devices are used
for logic-level conversions_ These devices are
intended for use as COS/MaS to DTL/TTL
converters and can drive directly two DTL/
TTL loads_ (VCC=5 V, VOL";; 0.4 V, and
IOL;;;' 3_2 mAo)
The CD4049UB and CD4050B are designated
as replacements for CD4009UB and CD401OB,
respectively _ Because the CD4049UB and
CD4050B require only one power supply,
they are preferred over the CD4009UB and
CD4010B and should be used in place of the
CD4009UBand CD4010B in all inverter, current driver, or logic-level conversion applications_ In these applications the CD4049UB
and CD4050B are pin compatible with the
CD4009UB and CD4010B respectively, and
can be substituted for these devices in existing
as well as in new designs_ Terminal No_ 16 is
not connected internallyon the CD4049U B or
CD40S0B, therefore, connection to this
terminal is of no consequence to circuit
operation_ For applications not requiring
high sink-current or voltage conversion, the
CD4069UB Hex Inverter is recommended_
The CD4049UB and CD40508 types are
supplied In 16-lead hermetic dual-in-line
ceramic packages (0 and F suffixes), 16lead dual-in-line plastic packages (E suffix),
16-lead ceramic flat packages (K suffix),
and in chip form (H sufflx)_
• COS/MaS to DTL/TTL hex converter
• COSIMOS current "sink" or "source"
driver
• COS/MaS high-to-Iow logic-level
converter
Ne 013
NC "16
CD4049UB
FUNCTIONAL DIAGRAM
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, IVccl
tVoltages referenced to VSS Terminal)
-{l_S to +20 V
-O.S to +20_5 V
INPUT VOLTAGE RANGE, ALL INPUTS
DC INPUT CURRENT, ANY ONE INPUT
±10mA
POWER DISSIPATION PER PACKAGE IPDI:
__
.
__
.
_
.
,
500mW
o
For TA = -40 to +60 C IPACKAGE TYPE EI
For TA - +60 to +850 C IPACKAGE TYPE EI
_
Derate Linearlv at 12 mW/oC to 200 mW
__ . _ _ __ . ,
500mW
For TA = -55 to +1000C IPACKAGE TYPES D. FI
0
For TA = +100 to +125 C IPACKAGE TYPES'D. FI
Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE-TEMPERATURE flANGE IAII Package Typesl
100mW
OPERATING-TEMPERATURE RANGE ITAI:
PACKAGE TYPES 0, F. H _ _ _ _ _ _ , . _ . _
-55 to +12SoC
PACKAGE TYPE E _ . _ _ _ _ _ _ _ _ _ _ _
-40 to +8SoC
STORAGE TEMPERATURE RANGE ITstgl
LEAD TEMPERATURE lOURING SOLDERINGI:
At distance 1/16 ± 1/32 inch 11.59 ± 0_79 mml from cas. for 10 s rna._
-65 to + 150°C
RECOMMENDED OPERATING CONDITIONS at TA=25 0 C, Except as Noted_
For maximum reliability. nominal operating condilions should be selected so that
operation is always within the following ranges:
LIMITS
Min_
Max_
CHARACTERISTIC
Supply-Voltage Range (VCC) (For T A=Full PackageTemperature Range)
Input Voltage Range (VIN)
UNITS
3
18
V
VCC
18
V
*The CD4049 and CD4050 have high-to-Iow-Ievel voltage conversion capability but Ilot
low-to-high-Ievel; therefore it is reco~mended that V IN ;;a= V CC·
A
~
B~
c~
D~
E~
F~
HoB
I·e
J;D
jl
~Tn
ta
R
~
IN
<·r
L"
Vee_'_
v's _B_
NC
Vee
G;A
~13
U
IN
N
'---4--~-4
Vss
= Vss
(.J
("
NC -IG
CD4050B
FUNCTIONAL DIAGRAM
Fig. l-aJ Schematic diagram of C04049UB, 1 of 6 identical units;
bl Schematic diagram of CD4050B, 1 of 6 identical units.
194 __________________________________________
~----------------------
CD4049UB, CD4050lB Types
STATIC ELECTRICAL CHARACTERISTICS
Limits At Indicated Temperatures (DC)
CHARACTERISTIC
CONDITIONS
Values at -55,+25,+125 Apply to D,F,H Pkgs.
Values at -40, +25, +85 Apply to £ Package
VIN VCC -55 -40
(V) (V)
+85
Quiescent
Device
Current, I DD
Max.
Output Low
(Sink)
Current
IOL Min.
Vo
(V)
0.4
0.4
0.5
1.5
0,5
0,10
0,15
0,20
0,5
0,5
0,10
0,15
5
10
15
20
4.5
5
10
15
1
2
4
20
3.3
4
10
26
1
2
4
20
3.1
3.8
9.6
25
30
60
120
600
2.1
2.9
6.6
20
30
60
120
600
1.8
2.4
5.6
18
Output High
(Source)
Current
IOH Min.
4.6
2.5
9.5
13.5
0,5
0,5
0,1(1
0,15
5
5
10
15
0.81
-2.6
-2.0
-5.2
-0.73
-2.4
-1.8
-4.8
-0.58
-1.9
-1.35
-3.5
-0.48
-1.55
-1.18
-3.1
Output Voltage:
Low-Level,
VOL Max.
-
5
10
15
0.05
0.05
0.05
-
-
0,5
0,10
0,15
-
0
0
0
Output Voltage:
High-Level,
VOH Min.
-
0,5
0,10
0,15
5
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5
10
15
-
4.5
9
13.5
-
5
10
15
1
2
-
-
-
2.5
-
-
1
2
2.5
5
10
15
1.5
3
4
-
-
1.5
3
4
4
8
12.5
4
8
12.5
-
-
3.5
7
11
3.5
7
11
-
-
Input Low
Voltage:
V IL Max.
CD4049UB
Input Low
Voltage:
VIL Max.
CD4050B
Input High
Voltage:
VIH Min.
CD4049UB
Input High
Voltage:
VIH Min.
CD4050B
Input Current,
liN Max.
+125
Min.
2.6
3.2
8
24
+25
Typ.
0.02
0.02
0.02
0.04
5.2
6.4
16
48
-0.65 -1.2
-2.1
-3.9
-1.65 -3.0
-4.3 -8.0
UNITS
Max.
1
2
4
20
-
pA
I
INPUT VOLTAGE I"J:'-V
Fig. 2-Minimum and maximum voltage
transferchsf8Cteristics for CD4049UB.
rnA
AMalENT TEMPERATURE
1T.t.,oz!!I-clf f tl f
SUPPLY VOLTAGE IVce'.5V
:::1111::
ffilHl!!l! iii! ....
-
0.05
0.05
0.05
IT ., ITfTT.!
!!~~tl!:
>1.~~~~,t1!~[ffi~r~~1:~::~:m~I~~~I~I:~::
m
....... rn I· ..
IIi.
ft
-_?
:!!I ::: Itit:; ::::
• '...
MINIMUM
•• -
1::: on
aXIMUM
••
I;:,;.:.
V
•
INPUT VOLTAGE CV11-V
0.5
1
1.5
-
-
-
Fig. 3-Minimum and maximum voltage
transfer characteristicr for CD4050B.
V
-
0.5
1
1.5
-
5
10
15
4.5
9
13.5
-
5
10
15
-
0,18
18
12:145&7
ORAIN-TO- SOURCE VOI.TAGE 1Vosl-V
92C5-27.1211'
±0.11 ±0.1
±1
±1
-8
-
±10-5
±0.1
pA
Fig. 4 - Typical output low (rink) current
characteristic$.
DRAIN-TO-souRCE: VOLTAGE 1Vosl-V
-7
--$
~
-4
-,
-2
-1
DRAIN-lO-SOURCE VOLTAGE IVDS)-V
92C,-274.,'1I
Fig. 5 - Minimum output low (sink) current
drain characteristics.
92:CS-l74I4RI
Fig. 6 - Typical output high (source) current
characteristics.
Fig. 1 - Minimum output high ($Duree) current
characteristicr.
__________________________________________________________________ 195
CD4049UB, CD4050B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA=250 C; Input t r ,tf=20 ns,
CL =50 pF, RL =200 kn
CHARACTERISTIC
CONDITIONS
VIN
Propagation Delay Time:
Low·to·High, tpLH
CD4049UB
CD4050B
High·to·Low, tpHL
CD4049UB
CD4050B
Transition Time:
Low·to·High, tTLH
High·to·Low, tTH L
Input Capacitance, CI N
CD4049UB
CD4050B
VCC
LIMITS
ALL PKGS.
Typ. Max.
5
10
10
15
15
5
10
10
15
15
5
10
10
15
15
5
10
10
15
15
5
10
15
5
10
15
5
10
5
15
5
5
10
5
15
5
5
10
5
15
5
5
10
5
15
5
5
10
15
5
10
15
60
32
45
25
45
70
40
45
30
40
32
20
15
15
10
55
22
50
15
50
80
40
30
30
20
15
120
65
90
50
90
140
80
90
60
80
65
40
30
30
20
110
55
100
30
100
1GO
80
GO
60
40
30
-
-
15
22.5
-
-
5
7.5
UNITS
ns
INPUT VOLTAGECVrl-V
Fig. 8 - TYPical voltage transfer characteristics as a function of temperature
for CD4049UB.
IlS
ns
Fig. 9 - Typical voltage transfer characteristics asa function of temperature for CD4050B.
..
IC":
pF
AMBIENT TEMPERATURE (TA 1- 2S·C
ftti;~
f--
t
..r
,:%}
.
. .r--Z
/-v5'0'
. .·v
. . 11--I.'''(111
.ft.'
2
~ ,0' J--t--~
1L..'7 /<,or,f
.00
. . '.t-f11
/
/
i--f-'.~ I/'~"-- ~.
~
~
~
2
L
•
foLcl7
~
2
LOAD CAPACITANCE ICL)io 50 rF
L
•
L
• e. 102
10
II ',03
~Hz
INPUT FREQUENCY
I I II
2
"
• • 104
92CS-29384
Fig. 10 - Typical power dissipation vs. frequency
~
~ lOIS AMBIENT TEMPERATURE eTA 1-25-C
!
~.
~
~
~
characteristics.
::, .M'"NT TEMP,""U", IT.
"2O'e
10!!
'cc
10"
INPUTS
D
Vss
10 3
100
.0'
'0
102
103
10 4
'55
INPUT fUSE AND FAL.l. TIME It, ,Itl-ft'
INPUT RISE AND FALL TIME 11,.tf l - u
92CS-204'OR2
Fig. 11 - Typicel POV'.'Sf dissipation vs. input
rise and fall times per inverter for
CD4049UB.
Fig. 12 - Typical power dissipation vs.
input rise and fall times per
Fig. 13 - Quiescent device current
rest circuit.
inverter for CD4050B.
196 _______________________________________________________________
CD4049UB, CD40S0B Types
COS/MOS 10 V LEVEL
TO OlLlTTL
51/ LEVEL
Vee 5 v
2
VCC
COS/MOS
v~UTQOUTP~
INPUTS
O· VIL
NOTE
VSS
TOOll/TTL
+IOVOV.TL
:L
V'L
OUTPUT
-I C04049
~IN~_ _ _
TERMINAL -
TEST ANY ONE INPUT,
WITH OTHER INPUTS AT
Vee OR VSS
3,5,7,9,II,ORI4
OUT TERMINAL -
2,4,6,10,12, OR 15
Vee
TERMINAL -
I
Vss
TERMINAL- 8
Fig. 15 -Input current test circuit.
Fig. 14 - Input voltage test circuit.
Fig. 16 - Logic-level conversion application.
60-68
(1524-1.7271
nCS-Z7'"
Dimensions in parentheses are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10- 3 inch).
Photograph of chip for CD4049UB. Dimensions
and pad layout for CD4050B are idenrical.
VCC
G'A
I.
2
A
H'ti
B
I'~
When the w~fer is cut intoo chips, the cleavage
angles are 57 instead of 90 with respect to the
face of the chip. Therefore, rhe isolated chip is
acrually 7 mils (0. 17 mm) larger in borh dimensions.
TERMINAL ASSIGNMENTS
16
NC
"
F
L~ F
"
"
NC
12
K't
"
J,l)
10
V55
The photographs and dimensions of each COS/MOS
chip represent a chip when it is part of the wafer.
9
NC' NO CONNECTION
CD4049UB
VCC
G~A
,4
I.
,
2
NC
"
"
12
NC
K'E
"
J'D
"
H'B
I,e
10
C
Vss
L'F
F
NC' NO CONNECTION
CD4050B
197
CD4051 B, CD4052B, CD4053B Types
COS/MOS Analog
Multiplexers/Demultiplexers·
J: =~.
ct11~~:~S J: =:
High-Voltages Types (20-Volt Rating)
CD4051B - Single a-Channel
CD4052B - Differential 4-Channel
CD4053B - Triple 2-Channel
RCA-C04051 B, C04052B, and C04053B
analog multiplexers/demultiplexers are digitally controlled analog switches having low
ON impedance and very low OFF leakage
current. Control of analog signals up to
20 V peak·to·peak can be achieved by digi·
tal signal amplitudes of 4.5 to 20 V (if
VOO-VSS = 3 V, a VOO,VEE of up to 13
V can be controlled; for VOO-VEE level
differences above 13 V, a VOO·VSS of at
least 4.5 V is required). For example, if
VOO=+4.5V, VSS=O, and VEE = -13.5 V,
analog signals from -13.5 V to +4.5 V can
be controlled by digital inputs of 0 to 5 V.
These multiplexer circuits dissipate extremely
low quiescent power over the full VOO·VSS
and VOO-VEE supply·voltage ranges, inde·
pendent of the logic state of the control
signals. When a logic "1" is present at the
inhibit input terminal all channels are off.
The C04051 B is a single 8·channel multiplexer having three binary control inputs, A,
B, and C, and an inhibit input. The three
binary signals select 1 of 8 channels to be
turned on, and connect one of the 8 inputs
to the output.
The C04052B is a differential 4-channel multi·
plexer having two binary control inputs, A
and B, and an inhibit input. The two binary
input signals select 1 of 4 pairs of channels
to be turned on and connect the analog in·
puts to the outputs.
The CD4053B is a triple 2-channel multi·
plexer having three separate digital control
inputs, A, B, and C, and an inhibit input.
Each control input selects one of a pair of
channels which are connected in a single·
pole double-throw configuration.
The C04051 B, C04052B, and C04053B are
supplied in 16-lead 'ceramic dual-in-line
packages (0 and F suffixes), 16-lead plastic
dual-in-line packages (E suffix), 16-lead
ceramic flat packages (K suffix), and in chip
form (H suffix).
16 _
C~:~~~;S
With Logic-Level Conversion
COM OUT/IN -
Applications:
-
Analog and digital multiplexing and demultiplexing
AID and 01A conversion
- Signal gating
-
INH_ 6
II-A
VEE _
Vss _
to -
7
8
•
B
.1- c
'J2CS·24482
INIOUT
- Wide range of digital and analog signal
levels: digital 3 to 20 V, analog to
20Vp_p
- Low ON resistance: 125 n (typ.) over 15
Vp_p signal·input range for VOO-VEE = 15 V
- High OFF resistance: channel leakage of
±100 pA (typ.) @VOO-VEE = 18 V
- Logic-level conversion for digital addressing
signals of 3 to 20 V (VOO-VSS = 3 to 20
V) to switch analog signals to 20 V pop
(VOO-VEE = 20 V); see introductory text
- Matched switch characteristics: RON =
5 n (typ.) for VOO-VEE = 15 V
- Very low quiescent power dissipation under
under all digital-control input and supply
conditions: 0.2 p.W (typ.) @ VOO-VSS =
VOO,VEE = 10V
I
13-0
12-3
* CHANNELS
Features:
Veo
"-'(
14 _
:5
CD4051B
Terminal Assignment
I.
Y~~:~LSJ~
COMMON-Y"OUT/IN
Y
,."
C~~~~~LS 1~
,N"
01
'0
VEE
Vss
Binary address decoding on chip
5-,10-, and 15-V parametric ratings
100% tested for quiescent current at 20 V
Maximum input current of 1 p.A at 18 V
over full package tamperature range;
100 nA at 18 Vand 25°C
I.,.I.
voo
~
I
X
C,~~~~~LS
COMMON·XMOUT/IN
~f X~:~~ELS
A
8
CD4O!i2B
Terminal Assignment
RECOMMENDED OPERATING CONDITIONS AT TA =250 C (Unless Otherwise Specified)
For maximum reliability, n~minal operating conditions should be selected so that operation
is always within the fol/owing ranges. Values shown apply to aI/ types except as noted.
CHARACTERISTIC
Supply-Voltage Range
(TA = Full Package·
Temp. Range)
Multiplexer Switch Input
Current Capability·
Output Load Resistance
VOO Min. Max. Uniu
*
-
-
3
18
V
-
25
100
-
mA
11
In certain applications, the external load·resistor
current may include both VOO and signal-line
components. To avoid drawing Voe current
when switch current flows into the transmission
gate inputs, the voltage drop across the bidirectional switch must not exceed 0.8 volt (calculated from RON values shown in ELECTRICAL
CHARACTERISTICS CHART). No VDD cur·
rent will flow through R L if the switch current
flows into terminal 3 on the C04051 ; terminals
3 and 130n the CD4052; terminals 4,14, and 15
on the CD4053.
t0, ••'.
,.,.I.
'""
01
10
INIOUT bl
OUT/IN CX arCY
INIOUTCX
VEE
,."
voo
OUTIIN blOrby
OUTIIN alOf01
:: liN/OUT
A
8
VSS
• When these devices are used as demultiplexers,
the "CHANNEL IN/OUT" terminals are the
outputs and the "COMMON OUT/IN" terminals
are the inputs.
92CS_24484
CD4053B
Ttlrminal Auignment
198 ________________________________________________________________
CD4051 B, CD4052B, CD4053B Types
MAXIMUM RATINGS, Absolute-Maximum Values:
a
DC SUPPLY-VOLTAGE RANGE, (VDD)
--{l.5 to +20 V
-0.5 to VDD +0.5 V
±10mA
(Voltages referenced to V S5 or VEE' whichever is more negative)
INPUT VOLTAGE RANGE, ALL INPUTS _
DC INPUT CURRENT, ANY ONE INPUT _
POWER DISSIPATION PER PACKAGE (PO):
. . . . • . . ..
For TA = -40 to +60 o C (PACKAGE TYPE E)
500mW
Derate linearly at 12 mW/oC to 200 mW
For T A = +60 to +850 C (PACKAGE TYPE E)
. .
For TA = -55 to +1000 C (PACKAGE TYPES D,F)
. . . . • . . ..
500mW
Derate Linearly at 12 mW/oC to 200 mW
For TA = +100 to +1250 C (PACKAGE TYPES 0, F)
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
100mW
FOR TA = FULL PACKAGE·TEMPERATURE RANGE (All Package Types)
OPERATING-TEMPERATURE RANGE ITA):
PACKAGE TYPES 0, F, H
-55 to +125 0 C
--40 to +8SoC
PACKAGE TYPE E .
STORAGE TEMPERATURE RANGE (Tstg )
-65 to +1500 C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 nim) from case for 105 max.
YDD
SUPPLY VOLTAGE (Vee - VEE)·
I
h AMBIENT TEMPERATURE i
t:(TA)o+125°C
,
g500
I'j
~400
~
z
300
~200
~
Ii
100
a
-4
-3
AMBIENT TEMPERATURE
(TA) - +125°C
5250
·
·
BINARY
0
C 9
INH 6
LOGIC
LEvEL
CONvERSION
·
i'J
~ 200
~
~ 150
z
3
TO
IOF8
DECODER
V
SUPP\.YVOLTAGE (VOO-VEE)-IOV
I 300
~
,
-2
-I
0
INPUT SIGNAL VOLTAGE IVls) -
Fig.4 - Typical channel ON resistance vs input
signal voltage (all types).
q
COMMON
OUT/IN
s v~.ulUn
600
Z
WITH
INHIBIT
~
100
~
50
-10
-7.5
-5
-2.5 0
2.5
7.5
INPUT SIGNAL VOLTAGE (Vi,)-V
10
92C$-2703J
Fig. 1 - Functional diagram of CD40518.
Fig.5 - Typical channel ON resistance vs. input
signal voltage (a/l typesl_
X CHANNELS IN/OUT
COMMON X
OUTIIN
A 10
*
6*
B 9
INH
*
BINARY
LOGIC
LEVEL
CONVERSION
B Vss
TO
J OF 4
DECODER
WITH
INHIBIT
COMMON Y
DUTIIN
INPUT SIGNAL VOLTAGE {Visl- V
92CS-21074RI
Y CHANNELS IN/OUT
Fig.6 - Typical channel ON resistance vs. input
signal voltage (all types).
Fig. 2 - Functional diagram of CD4052B.
IN/OUT
"I 300
~25O
~
u
~200
~
150
z
0'00
'.0
o
:t.:=r'DD
-10
~vss
Fig. 3 - Functional diagram of CD4053B.
-7.5
[lllll'IIP!
-5
-2.5
0
1 .•
2.'
INPUT SIGNAL VOLTAGE (Vi') - V
10
Fig.7 - Typical channel ON resistance vs. input
signal voltage (all types).
_______________________________________________________________________ 199
CD4051 B, CD4052B, CD4053B Types
ELECTRICAL CHARACTERISTICS
LIMITS at Indicated Tamperature (OCI
Valuesat-55,+25,+125,apply to D,F,H pkg
VEE Vss VDD Values at -40,+25,+85, apply to E pkgs
Vii
Units
(VI
(VI
(VI (VI
+25
-55 -40 +85 +125'
Min_ Typ.
Max.
SIGNAL INPUTS (Visl AND OUTPUTS (VOSI
CONDITIONS
CHARACTERISTIC
Quiescent Device
Current, I DO
Max.
5
10
15
20
On-State
Resistance
0';;; Vis';;; VDD
ron Max.
Change in OnState Resistance
(Between Any
Two Channelsl
lJ. ron
0
0
0
0
0
0
5
10
15
0
0
0
0
0
0
5
10
15
0
0
18
5
10
20
100
5
10
20
100
,800 850
310 330
200 210
-
-
150 150
300 300
600 600
3000 3000
1200 1300
520 550
300 320
-
-
-
-
0.04
0.04
0.04
0.08
-
470
180
125
-'
-
15
10
5
-
5
10
20
100
IJA
INPUT SIGNAL VOLTAGE (VLI' - VOLTS
1050
400
240
-
Fig.S - Typical ON chal'BClerl.tlc. for
I of S channels (C040S1SI.
n
n
OFF Channel
Leakage Current:
Any Channel
OFF Max.
All Cha~~els
OFF (Common
OUT/IN) Max.
±100·
-
±1000'
i'O.OI ±.100·
nA
10
lot
105
SWITCHING FREQUENCYCfl-kHz
Ca pacitance:
Input, Ci<
Output, Cos
~
CD4052
-5
~
-5
5
Feedthrough,
Cios
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Fig.S - Typical dynamic powsr di";pation
.... switching frequancy (C040S1 BI.
5
-
30
18
-
9
pF
-
I
AM_NT TEfll'VtATUR£ ITA)' 20"
ALTDINATINI"O· AND "I· MTTERH
LOAD CAPACITANCE 1tt-1-5O" ~
~
0.2
~
-
10"
.
W
Propagation Delay
Time (Signal I nput to Output
VDD RL= 200 kG 5
CL=50pF 10
tr,tf = 20 ns 15
i
-
..n.
-
-
-
-
-
-
30
15
10
60
30
20
ns
'0'
a
'0'
Ii
i
• Determined by minimum feasible leakage measurement for automatic testing.
~
loon 109
~
4
)/
10
10I
0
'HL
~
T.
SWITCHING 'REOWNCY III-kHz
"
I:
C04~2 ~ ...
1004 6
1/
CL"J6"
'0
CD402.
rill:'
-,/_ f .
~~
I
'"
V
~~ V.Y"·01.
I
'0'
'0'
Fig. 10 - Typical dynamic power di..ipation
.... switching fraqu.ncy (C040S2BI.
.
r
to .....IENT TEMPE:RATURE(T"I • 2,ee
PATTEn.
ALTERNATING "0- AND "."
LOAD CAPACllANet:
,ol5OlIf'/
I
!~
~
~
I
III
f-
IOJ~
:it'~
=;d".i'
:
l~~
~
.'
III -tij
L lJll.1il
"
·II~
Yeo • .. 5 Y
t!otT~IT
., ttt
C04053~'
~
I:
... c...
Q-------,
i
"
,F
'=l
10
.
,0'
10
SWlTOU... FR[QUENCYQ,-t;HI
.tcs-ttrzOlti
Fig. 11 - Typical dynamic powe, di8liPlltion
... switching fraquancy (C040S3BI.
200 ______________
~
vtE"-IOY
,.1
'01
The ADDRESS (digit8loControl inputsl8nd INHIBIT logiC levels ara:
"0" - VSS and "I" = VDD. The 8n810g sign81 (through the TGI may
swing from VEE to VDD.
I,)
'dl
.2eS-ZOOIiRI
Fig. 12 - TyplCllf bia. IIOftll/lfl"
_______________________________________________
CD4051B, CD4052B, CD4053B Types
ELECTRICAL CHARACTERISTICS (Cont'd)
LIMITS at Indlcatad Temperatura (OC)
CONDITIONS
Valullat -65,+26,+126,apply to D,F,H plcg
VEE Vss VDD Valul.at -40,+26,+85, apply to E' pk91
Vi.
(V)
(V)
(V) (V)
+26
-56 -40 +85 +126 1
Min. Typ.
Max.
CHARACTERISTIC
INPUT STATES
"ON" CHANNEL(S)
INHIBIT C B A
CD4061B
Units
CONTROL (ADDRESS or INHIBIT) Vc
Input Low
Voltage, VI L
Max.
Input High
Voltage, V I H
Min.
Input Current,
liN Max.
Propagation
Delay Time:
Address-to·
Signal OUT
(Channels ON
or OFF) See
Figs.14,15,18
Inhibit-toSignal OUT
(Channel turningON)
VIN = 0,18
5
10
15
5
10
15
18
-
1.5
3
4
3.5
3.5
7
7
-
11
to.l to.l
11
tl
tl
-
-
tl0-5
1.5
3
0
0
0
0
5
10
15
5
RL =10 kn, CL =50 pF
tr, t! = 20 ns
5
O
0
0
0
10
0
0
15
-10
0
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0 0 1
0 1 0
0 1 1
1 0 0
2
3
4
-
to.l
4
5
6
1
1 1 0
1 1 1
X X X
1
V
1
1 0
0
0
7
NONE
CD4052B
tJA
tr,t! = 20 ns, CL = 50 pF
0
0
0
-5
0 0
0
0
0
0
0
!
VEE=VSS
=VDD
RL =1 kn
thru
to VSS
1 kn
IIS< 2/JA
on all OFF
Channels
0
INHIBIT
B
A
0
0
0
0
0
1
0
1
0
0
1.
1
X
1
X
OX,Oy
lx,ly
2x,2y
3x,3y
NONE
CD4053B
360
160
120
225
720
320
240
450
INHIBIT
AorB
arC
0
0
0
1
1
X
ns
ax or bx or ex
ay or by or cy
NONE
X = Don't care
360
160
120
200
720
320
240
400
ns
200
70
130
450
210
160
300
ns
5
7.5
pF
Fig. 13- Truth tabl••.
RL =300n,CL -50 pF
tr,t! = 20 ns
Inhibit-toSignal OUT
(Channel turning OFF)
O
0
0
-10
0
0
0
0
Input
Capacitance, CIN
(Any Address
or Inhibit Input)
5
10
15
5
-
-
-
-
90
Fig.74 - Waveforms, channel being
turned ON (RL = 10k!ll.
TEST CIRCUITS
Voo
...-------1
, -_ _ _ _.,Voo
16
16
15
14
Fig.tS - Waveforms; channel being
rurned OFF (RL = 300 !II.
tOD
Fig. 16 - OFF channelloakago current - any channel OFF.
201
CD40518, CD40528, CD40538 Types
TEST CIRCUITS (Cont'd)
ELECTRICAL CHARACTERISTICS (Cont'd)
LIMITS
TEST CONDITIONS
CHARACTERISTIC
5-
Cutoff (-3-dB)
Frequency
Channel ON
(Sine Wave Input)
5
~
10
S-
1S
S-
30
Vas at Common OUT/IN CD40S2
2S
CD40S1
20
Vas at Any Channel
MHz
60
~
~
0.12
10
I. 10
CD40S3
1
Vas at Common OUT/IN CD40S2
VEE = VSS,
Vas
20 log Vis =-4OdB Vas at Any Channel
5-
-40-dB
Signal Crosstalk.
Frequency
10
1
VEE = VSS,
CD4051
%
I 10
r-_ _ _...... VOO
B
10
12
B
Between Any 2 Channels
3
Between Measured on Common
Sections
6
CD40S2
Channel
Only
10
16
MHz
Measured on Any
Vas
20 log = -4OdB Between
In Pin 2, Out Pin 14
Any 2
Vis
Sections
In Pin 1S, Out Pin 14
C040S3
Only
to Signal Crosstalk
~
C040S3
16
VEE = VSS,
fis = 1 kHz sine wave
-40-dB
Feedthrough
Frequency
(All Channels OFF)
Address·or·lnhibit·
1
Vas
20Iog-=-3dB
Vis
Total Harmonic
Distortion,
THD
10
VEE = VSS,
, ___-1 VOO
TYPICAL UNITS
VALUE
RL
(kn)
Vis Voo
(V) (V)
2.5
MHz
6
VOO
r---""""""""i
16
15
10#
I.
VEE=O,VSS=O, tr,tf
13
mV
6S
=20 ns, Vc = VDO
(Peak)
-Vss(Square Wave)
- Peak-to-peak voltage symmetrical about VOD - VEE
Fig. 17 - OFF channel leakage current - all
2
channels OFF.
# Both ends of channel
Voo
VOO
VO£fl...J
Vss CLOCK
IN
Vss
CD4051
CD4052
CQ4053
Fig. 18 - Propagation delay - address input to signal output.
Voo
Voo
16
IS
"13
12
10
9
t PHL AND tpLH
CD4051
Vss
Vss
Vss
tpHL AND lpLH
CD4052
Fig. 19 - Propagation delay - inhibit input to signal output.
t PHL AND lPLH
CD4053
92CS-21045
202 ____________________________________________________________________
CD4051B, CD4052B, CD4053B Types
TEST CIRCUITS (Cont'd)
Voo
Voo
I.
I>
I.
I.
I>
I.
13
13
12
92CS-30932
MEASURE c Z p.A ON ALL
·OFF" CHANNELS (I.;. CHANNEL 6)
92C5-30933
92C5-27047
MEASURE < 2 p.A ON ALL
"OFF" CHANNELS (e.Q CHANNEL by)
MEASURE < 2 jJ.A ON ALL
"OFF~ CHANNELS (II.; CHANNEL i l l
Fig.2T - Quiescent device current.
Fig. 20 - Input volrage test circuits (noise immunity).
KEITHLEY
VDD
160 DIGITAL
MULTIMETER
x-v
L-_ _~_ _ _ _-+-4PLOTTER
Vss
Vss
92C5-22716
CD4051
CD4053
ALL UNUSED INPUTS TO
Fig.22 - Channel ON resistance
EITHER Yoo OR vss.
measurement circuit.
NOTE:
MEASURE INPUTS
SEQUENTIALLY, TO BOTH
Voo AND Vss CONNECT
ALL UNUSED INPUTS TO
NOTE:
MEASURE INPUTS
SEQUENTIALLY, TO BOTH
voo AND vss CONNECT
92CS-27048
EITHER Yoo OR Vss.
Fig. 23 - Input current.
5V p-p
rv
COMMON
rv
92C5-27049
Fig.24 - FtHldthrough (./1 type.).
92CS-27050
Fig.25 - Crosstalk between any two channels (a/l types).
5 V p-p
rv
DIFFERENTIAL
SIGNALS
CD4062
CD4052
COMMUNICATIONS
LINK
DIFF.
DEMULTIPLEXING
MULTIPLEXING
92C$-270151
Fig.26 - Crosstalk between duals or triplets
(CD40528. CD40538i.
tzCS-2705Z
Fig.27 - Typical time-divi,ion application of the CD4052B.
_________________________________________________________________ 203
CD4051B, CD4052B, CD4053BTypes
SPECIAL CONSIDERATIONS
In applications where separate power sources
.e used to drive VOO and the signa! inputs,
the VOO current capability should exceed
Voo/RL (RL =effective external load). This
provision avoids permanent current flow or
clamp action on the VOO supply when power
is applied or removed from the C04051 B,
C04052B, or C04053B.
When switching from one address to another,
some of the ON periods of the channels of
the multiplexers will overlap momentarily,
which may be objectionable in certain applications. Also when a channel is turned
ON or OFF by an address input, there is a
momentary conductive path from the channel to VEE, which will dump some charge
from any capacitor connected to the input
or output of the channel. The inhibit input
turning ON a channel will similarly dump
some charge to VEE.
The amount of charge dumped is mostly
a function of the signal level above VEE.
Typically, at VOO,VEE = 10 V, a, 100 pF
n-
(1.956-
~---------C22~:~~~-------"
Dimensions and pad layout for CD4051BH.
capacitor connected to the input or output
of the channel will lose 3·4 % of its voltage at
the moment the channel turns ON or OFF.
This loss of voltage is essentially independent
of the address or inhibit signal transition
time, if the transition time is less than 1·2
J,ls. When the inhibit signal turns a channel
OFF, there is no charge dumping to VEE.
Rather, there is a slight rise in the channel
voltage level (65 mV typ.1 due to capacitive
coupling from inhibit input to channel input
or output. Address inputs also couple some
voltage steps onto the channel signal levels.
The photographs and dimensions of each COS/MOS
chip represent a chip when it is part of the wafer.
When the wafer is cut into chips, the cleavage
angles are 5(° instead of 90° with respect to the
face of the chip. Therefore, the isolated chip is
actuaJJy 7 mils (0. 17 mm) larger;n both dimensions.
Dimensions in parentheses are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid Graduations are in Mils (10- 3 inch).
71-85
(I 956 - 2 159J
o~-----,--------,_J
1-----------
(2
2~~=~8489) - - - - - - - - 1
Dimensions and pad layout for CD4052BH.
Dimensions and pad layout fo; CD4053BH.
204 _______________________________________________________________________
CD4054B, CD4055B, CD4056B Types
COS/MOS Liquid-Crystal
Display Drivers
High-Voltage Types (20-Volt Rating)
CD4054B - 4-Segment Display Driver
CD4055B - BCD to 7-Segment Decoder/Driver with
"Display-Frequency" Output
CD4056B - BCD to 7-Segment Decoder/Driver with
Strobed-Latch Function
The RCA CD4055B and CD4056B types are
single-digit BCD-to-7-segment decoder/driver
circuits that provide level-shifting functions
on the chip. This feature permits the BCD
input-signal swings (VDD to VSS) to be the
same as or different from the 7-segment
output-signal swings (VDD to VEE). For
example. the BCD input-signal swings (VDD
to VSS) may be as small as 0 to -3 V, whereas the output-display drive-signal swing (V DD
to VEE) may be as large as from 0 to -15V_
If VDO to VEE exceeds 15 V, VDDtoVSS
should be at least 4V (0 to -4V).
The 7 -segment outputs are controlled by
the DISPLAY-FREQUENCY (DF) input
which causes the selected segment outputs
to be low, high, or a square-wave output
(for liquid-crystal displays). When the DF
input is low the output segments will be
high when selected by the BCD inputs_
When the DF input is high, the output
segments will be low when selected by the
BCD inputs. When a square-wave is present
at the DF input, the selected segments will
have a square-wave output that is 1800 out
of phase with the DF input_ Those segments
which are not selected will have a squarewave output that is in phase with the input.
DF square-wave repetition rates for liquidcrystal displays usually range from 30 Hz
(well above flicker rate) to 200 Hz (well
below the upper limit of the liquid-crystal
frequency response). The CD4055B provides a level-shifted high-amplitude DF output which is required for driving thecommon
electrode in liquid-crystal displays_ The
CD4056B provides a strobed-latch function
at the BCD inputs. Decoding of all input
combinations on the CD4055B and CD4056B
provides displays of 0 to 9 as well as L, P,
H, A, -, and a blank position.
The CD4054B provides level shifting similar
to the C04055B and CD4056Bindependently
strobed latches, and common OF control on
4 signal lines_ The CD4054B is intended to'
provide drive-signal compatibility with the
CD4055B and C04056B 7-segment decoder
types f~r the decimal point, colon, polarity,
and similar display lines. A level-shifted
high-amplitude DF output can be obtained
from any CD4054B output line by connect-
Features:
• Operation of liquid crystals with COS/MaS
circuits provides ultra-low-power displays
Voo
• Equivalent ac output drive for liquidSTROBE
2
crystal displays - no external capacitor required
BCD \ ~~
• Voltage doubling across display, e_g_
INPUTS ~ 2 3
"12
2·
VDD - VEE = 18 V results in effective
DIS. FREQ.IN
36 V Pop drive across selected display
VEE
'0
Vss
9
segments
* 7-SEGMENT
• Low- or high-output level dc drive for
OUTPUTS
other types of displays
• On-chip logic-level conversion for different
input- and output-level swings
CD4056B
• Full decoding of all input combinations:
Terminal Assignment
0-9, L, H, P, A,-, and blank positions
• Strobed-latch function-CD4054B Series
and CD4056B Series
VDD
STROBE 4
I.
I.
• DISPLAY-FREQUENCY (OF) output
15
DISPLAY FREQ.IN
2
INO
for liquid-crystal common-line drive signalDUTO
3
STROBE 3
'0
CD4055B Series (CD4054B Series also:
OUT3
13
IN3
OUT2
see introductory text)
12
STROBE2
OUT I
• 100% tested for quiescent current at 20 V
" IN2
10
STROBE I
VEE
Vss
• Maximum input current of llJA at 18 V
INI
over full package temperature range;
100 nA at 18 V and 250 C
• Noise margin (over full package temperCD40548 Terminal Assignment
ature range):
1 VatVDD=5 V
2 V at VDD = 10 V
VDD
DISPLAY FREQ. OUT
2_5VatVDo=15V
"
2
• 5-V, 10-V, and 15-V parametric ratings
10
BCD
21
,.
,.
,."
1
:\
INPUTS
~~
~
20
Applications
•
•
•
•
•
•
•
•
General-purpose displays
Calculators and meters
Wall and table clocks
Industrial control panels
Portable lab instruments
Panel meters
Auto dashboard displays
Appliance control panels
ing the corresponding input and strobe lines
to a low and high level, respectively and
applying a square wave to DFIN; The
CD4054B may also be utilized for logic-level
"up conversion" or "down conversion". For
example, input-signal swings (VDD to VSS)
frum +5 to 0 V can be converted to outputsignal swings (VDD to VEE) of +5 to -5 V.
The level-shifted function on all three types
permits the use of different input- and output-signal swings. The input swings from a
low level of VSS to a high level of VDD while
the output swings from a low level of VEE to
the same high level of VOD- Thus, the input
and output swings can be selected independently of each other over a 3-to-18 V range.
VSS may be connected to VEE when no
level-shift function is reqyired_
For the CD4054B and CD4056B, data are
DISPLAY FREQ.IN
VE_
Vss
I.
"
'3
12
"
lD'
: IT_SEGMENT
c
OUTPUTS
b
92CS_24486
CD40558 Terminal Assignment
transferred from input to output by placing
a high voltage level at the strobe input. A
low voltage level at the strobe input latches
the data input and the corresponding output
segments remain selected (or non-selected)
while the strobe is low.
Whenever the level-shifting function is required, the CD4055B can be used by itself
to drive a liquid-crystal display (Fig.,16 and
Fig.201. The CD4056B, however, must be
used together with a CD4054B to provide
the common DF output (FigJ9). The capability of extending the voltage swing on the
negative end (this voltage cannot be extended
on the positive end) can be used to advantage
in the setup of Fig.l8. Fig_l17 is common
to all three types_
The C04054B-. C04055B-, and C040568series types are available in 16-lead ceramic
dual-in-line packages (Oand Fsufflxes), 16lead plastic packages (E suffix), 16-lead
ceramic flat packages (K suffix). and in chip
form (H suffix)_
205
CD4054B, CD4055B, CD4056B Types
LOAD CAPACITANCE (CL)- pF
ALL INPUTS PROTECTED BY
COS/MOS PROTECTION NETWORK
92CS-20090RZ
Fig.4 - Typical propagation delay time vs.
load capacitance for CD4D54B.
Fig. 1 - CD40548 functional diagram.
Fig.2 - CD40558 functional diagram.
LOAD CAPACITANCE (CL)- pF
Fig.5 - Typical propagation delay time vs. load
capacitance for CD4055 and CD4056B.
ALL ,tlPUTS PROTECTED BY
COS/MOS PROTECTION NETWORK
92CS-Z009IR2
Fig.3 - CD40568 functional diagram.
TRUTH TABLE FOR CD4055B and CD4056B
INPUT CODE
DISPLAV
OUTPUT STATE
CHARAC·
2'
2'
2'
2"
a
b
c
d
e
f
9
0
0
0
0
1
1"
1
1
1
1
0
0
0
0
1
0
1
1
0
0
0
0
0
0
1
0
1
1
0
1
1
0
1
0
0
1
1
1
1
1
1
0
0
1
0
1
0
0
0
1
1
0
0
1
1
0
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
TER
,,
,-
,,-
,,-
,,
,,
,
,,
,
,
,
,
,,
,,
,
0
1
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
1
1
1
0
1
0
0
0
0
1
1
1
0
1
0
1
1
0
1
1
0
1
1
1
,-,
,,
:-,,
1
1
0
0
1
1
0
0
1
1
1
1-'
1
1
0
1
1
1
1
0
1
1
1
, ,
,-,
1
1
1
0
0
0
0
0
0
0
1
-
1
1
1
1
0
0
0
0
0
0
0
,,-
LOAD CAPACITANCE{CL )-pF
92CS'Z849(1RI
Fig.6 - Typical transition time
load capacitance.
.,
.
~
~
lr
V,"
LOAD CAPACITANCE (eLl-50 pF
---
CL~15pF
10
BLANK
"
2:
4 6 10
2:
4 6 102 2:
4 6'03 2
4 6 104 2:
4 6 ,05
INPUT CLOCK FREQUENCY (feL)-kHz
Fig.7 - Typical input clock frequency vs.
power dissipation.
206
CD4054B, CD4055B, CD4056B Types
MAXIMUM RATINGS, Absolute·Maximum Values:
DC SUPPLY·VOLTAGE RANGE, (VDD)
-0.5 to +20 V
(Voltages referenced to VSS Terminal)
-0.5 to VDD +0.5 V
INPUT VOLTAGE RANGE, ALL INPUTS
±10rnA
DC INPUT CURRENT, ANY ONE INPUT
POWER DISSIPATION PER PACKAGE IPD):
. . . . . . • ..
500rnW
For T A = -40 to +60 0 C IPACKAGE TYPE E)
Derate linearly at 12 mWJoC to 200 mW
For TA = +60 to +850 C (PACKAGE TYPE E)
.
. . . . . . . ..
500rnW
For TA = -55 to +1000 C (PACKAGE TYPES D,F)
Derate Linearly at 12 mW/oC to 200 mW
For T A = +100 to +125 0 C (PACKAGE TYPES 0, F)
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
100rnW
FOR TA = FULL PACKAGE·TEMPERATURE RANGE (All Package Type,1
OPERATlNG·TEMPERATURE RANGE (TA):
-55 to +125 0 C
PACKAGE TYPES 0, F, H
-40 to +85 0 C
PACKAGE TYPE E .
-65 to +1500 C
STORAGE TEMPERATURE RANGE (Tstg )
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59
DRAIN-TO-SOURCE VOlTAGE IVDSI-V
Fig.8 - Typical n-channel output low (sink)
current characteristics.
± 0.79 mm) from case for lOs max.
STATIC ELECTRICAL CHARACTERISTICS
liMITS
CONDITIONS
Characteristic
VEE VSS
IV) IV)
a
a
a
a
a
a
a
Low Level. VOL
MAX.
a
a
a
a
a
High Level. VOH
MIN.
0
0
0
Quiescent Device
Current, IDO
MAX.
-5
Output Voltage:
Input Low
Voltage,
Vil MAX.·
0
0
0
···5
Input High
Voltage,
0
VIHMIN. 0
Output low
(Sink)
Current, IOl
Output High
(Source)
Current,lOH
Input Current,
liN
Vo VIN VDD
IV) IV) IV)
5
10
15
20
05
OlD
015
05
010
0,15
0
0
0
a
0.5,
0
4.5
1,9
0
01.5,13.5
0 U5,4.5
o I 1,9
o 1.5,13.5
5
0
0
-5
0
0
'0
0
4.5
0.5
1.5
4.5
a
~.5
a
0
13.5
0
a
a
-
Values at -SSO,+2s<', +12SOC Apply to D.F,H Packages
Values at -4fP. +2:;0. +8SoC Apply to E Package
_55° -40°
5
lD
20
100
+125° Min.
150
300
600
3000
-
+25 0 C
Typ. Max.
0.04
5
0.04 10
0.04 20
0.08 100
a
a
5
10
15
5
10
15
0.05
0.05
0.05
4.95
9.95
14.95
5
1.!>
3
4
3.5
7
11
3.5
7
11
0.92 0.67
0.92 0.67
3.4
2.4
·0.55 -0.35
-0.55 -0.35
-1.8
-1.2
1.6
0.55
0.8
1.6
0.55
0.8
5,B
2
2.9
-0.3 -0.45 -0.9
-0.3 -0.45 -0.9
-3
-1.1 -1.5
10
15
5
10
15
0,18
+85°
150
300
600
3000
5
10
15
5
10
15
0,98
0.98
3.6
-0.6
··0.6
-1.9
18
±0.1
±0.1
4.95
9.95
14.95
0
5
10
15
-
-
±1
±1
-
-
-
0.05
0.05
0.05
Units
I1A
DRAIN-TO-SOURCE VOLTAGE IlIosl-V
V
1.5
3
4
-
Fig.9 - Minimum n-channel output low (sink)
current characteristics.
DRAIN-TO-SOURCE VOLTAGE (VoSI-V
V
-
-
rnA
92CS·33194
-
±10- 5 ±0.1
Fig. 10 - Typical ~channel output high (source)
current characteristics.
I1A
JRAIN-'O-SOURCE VOLTAGE l\I051-V
I
voo
INPUTS
o
vss
vss
Fig. 11 - Qu;escent·dev;ce-current test circuit.
92CS·33193
92CS-274"IRI
Fig. 12 - Input-voltage test circuit.
Fig. 13 - Minimum p-channel output high
(source) current characteristics.
207
CD40548, CD40558, CD40568 Types
DYNAMIC ELECTRICAL CHARACTERISTICSatTA =2SoC,CL = SO pF, Inputt"tf = 20 ns,
RL = 200 kQ
CONDITIONS
CHARACTERISTIC
tpHL,tPLH
(Any Input to Any Output)
Transition Time, tTH L,tTLH
(Any Output)
Minimum Data Setup
Time, tS'
.
Minimum Strobe Pulse
Width, tw
I nput Capacitance, CI N
(Any Input)
~
ALL PACKAGE TYPES
CD40SS,CD40S6 UNITS
CD40S4
VEE VSS VDD
(V)
(V) (V)
NOTE
~i~~~:i,~~~~~S
.... S5
TO BOTH VDO ANO VS5
CONNECT ALL UNUSED
INPUTS TO EITHER
Typ. Max.
Typ. Max.
Propagation Delay Time,
DD
,NPDU5
V
'.100
LIMITS
Voo ORVSS'
V55
-5
0
0
0
0
0
5
10
15
400
340
250
800
680
500
650
575
375
1300
1150
750
ns
-5
0
0
0
0
0
5
10
15
100
100
75
200
200
150
100
100
75
200
200
150
ns
-5
0
0
0
5
10
15
110
50
35
220
100
70
110
50
35
220
100
70
ns
-5
0
0
0
0
0
5
10
15
110
50
35
220
100
70
110
50
35
220
100
70
ns
-
-
-
5
7.5
5
7.5
pF
Fig. 14 - Input-current test circuit.
---=
·50~.
DATA-I
STROBE
I
lr"1~201'ls.i
__ I '
~50%
IS
50%~
~
"
'--
Fig. 15 - Data setup time and strobe
pulse duration.
• CD4054 and CD4056 only.
RECOMMENDED OPERATING CONDITIONS atT A =2SoC (Unless otherwise specified)
For maximum reliability, nominal operating conditions should be selected so that operation
is always within the following ranges.
CHARACTERISTIC
VEE
(V)
VSS
(VI
VDD
(V)
LIMITS
Min.
Max.
3
18
UNITS
LEVELOm
SHIFTED
Supply Voltage Range:
(At T A= Full Package
Temperature Range)
DFOUT
V
DISPLAY
Setup Time (t s)-
-5
0
0
0
0
0
5
10
15
220
100
70
Strobe Pulse Width (tW)-
-5
0
0
0
0
0
5
10
15
220
100
70
-
DFOUT
I-- P
2:~"'~RNT
INPUT
ns
T~
1
I-- n
DISPLA'I'
ORIVER
SEGMENT
p~~~UQT)
(0 TOQ)
(HIGH-SELECT)
DFOUT
(.1
92CS- 20093RI
ns
-For CD4054 and CD4056 only.
-- VEEv0:u-uuuuuuuuuu-m
OFOUT
Vao
r-----'-.,
L
SEGMENT IN vEEJ
SEGMENT OUT
Voo
VEE
*
~
+(Voo-VEE~'
ov
-(VOo-VEE )
*:~~~Ti~N~OLL~~~~D~~~~~~iLS~~~~~N'f~~~FORM
LlaUID - CRYSTAL
COMMON ElECTRODE
Fig. 16 - Clock display: VDD
IF oFO UT IS
92CS-20094FlI
DFIN"DISPLAY-FREOUENCY INPUT
oFOUT.LEVEl-SHIFTEo DISPLAY· FREQUENCY OUTPUT
=0
92CS-20095RZ
V, VSS ~5 V,
VEE
= -15
Ibl
V, DF/N = 30 Hz square wave.
Fig. 17 - Display-driver circuit for one segment line
and waveforms.
208
CD4054B, CD4055B, CD4056B Types
No.4
ANAL.OG INPUTS C±5vl
I
STROBE
No· No. No.
2
3
4
O.P. o.p o.P
VOO·5V
I
ANALOG OUTPUTS
I:!. 5 V)
Fig.1S - Digital (0 to +5 V) to bidirectional analog
control (+5 to -5 V) level shifter.
Fig. 19 -
TypicaI3!&~igit
liquid-crystal display:
VDD=+5 V, VSS=O V, VEE=-10 V,
DFIN = 30 Hz square wave.
DF1N '
92C5- 20089 R2
3gVH~~g~~:~O~AVE.
OFOUT ;
gL~7~~- :~~~~i~8~
Fig.20 - Single-digit liquid-crystal display.
The photographs and dimensions of each COS/MOS
chip represent a chip when it is part of the wafer.
When the Wafer is cut into chips, the cleavage
angles are 57° instead of 90° with respect to the
face of the chip. Therefore, the isolated chip is
actually 7 mils (0. 17 mm) larger in both dimensions.
Dimensions in parentheses are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (ttr 3 inch).
Fig.21 - 'Conversion of uH" display to "F u display_
In addition to the letters L, H, P, and
A (See the truth table). five other letters
can be displayed through the use of simple
logic circuits preceding and following the
CD4055B or CD4056B devices. Fig.21 is an
example of a circuit that converts an "H"
display (code 1011) to an "F" display.
One condition that must be met is that
VEE=VSS. If VEE4VSS, the CD4054B must
be used to level shift in the appropriate places.
l)2CS-21Q61
92C5-27062
Dimensions and pad layout for CD4054BH.
In a similar manner the letters C, E, J, and
U can be displayed. These circuits can also
be used to drive LED displays provided the
exciusive·OR gates have sufficient output·
current drive.
The letters B, D, G, 1,0, and S may be rep·
resented by the codes for numbers 8, 0, 6,
I, 0, and 5, respectively, when there is pre·
knowledge that only letters are to be dis·
played.
Dimensions and pad layout for CD4055BH
Dimensions and pad layout for CD4056BH
________________________________________________________________
~
__ 209
CD4060B Types
COS/MOS 14-Stage RippleCarry Binary Counter/Divider
and Oscillator
o.
O'
06
07
High-Voltage Types (20-Volt Rating)
08
00
Features:
OlD
01'
•
•
•
•
•
•
•
12 MHz clock rate at 15 V
Common reset
FiJlly static operation
Buffered inputs and outputs
Schmitt trigger input-pulse line
100% tested for quiescent current at 20 V
Standardized, symmetrical output
characteristics
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEOEC Tentative
Standard No. 13B, "Standard Specifications for description of "B" Series CMOS
Devices"
The RCA-C04060B consists of an oscillator
section and 14 ripple-carry binary counter
stages_ The oscillator configuration allows
design of either RC or crystal oscillator
circuits_ A RESET input is provided which
resets the counter to the all-D's state and
disables the oscillator_ A high level on the
RESET line accomplishes the reset function.
All counter ,'itages are master-slave flip-flops.
The state of the counter is advanced one
step in binary order on the negative transition of .pIland .pO). All inputs and outputs
are fully buffered. Schmitt trigger action
on the input-pulse line permits unlimited
input-pulse rise and fall times.
The C040S0B-series types are supplied in
lS-lead hermeticdual-in-line ceramic packages 10 and F suffixes), lS-lead dual-in-line
plastic packages (E suffix), lS-lead ceramic
flat packages (K suffix), and in chip form (H
suffix).
FUNCTIONAL DIAGRAM
Oscillator Features:
Applications
•
•
•
•
Control counters
Timers
Frequency dividers
Time-delay circuits
Q41QI0
012,013
OD
- - -
ON EACH NEGATIVE-GOING TRANSITION
OF+IIANO+O)
,.
,.
•
014 3
• All active components on chip
• RC or crystal oscillator configuration
• RC oscillator frequency of 690 kHz
min. at 15 V
B
.. COUNTER ADVANCES ONE BINARY COUNT
013
I.
* BY COSIMOS PROTECTION
ALL INPUTS ARE PROTECTED
92CS-29072
NETWORK
92CM-Z9074RI
Fig. 2 - Detail of typical flip-flop stage.
Vss
Fig. 1 - Logic diagram.
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY·VOLTAGE RANGE. (VDDI
(Voltages referenced tD VSS Terminal)
INPUT VOLTAGE RANGE. ALL INPUTS
DC INPUT CURRENT. ANY ONE INPUT
POWER DISSIPATION PER PACKAGE (POlo
Fo' TA ' -40 to +60 o C (PACKAGE TYPE El
For TA '" +60 to +85 0 C (PACKAGE TYPE El
-0.5 to +20 V
-0.5 to VDD +0.5 V
±10mA
.
.
For TA = -55 to +100oC (PACKAGE TYPES D. F)
For TA = +100 to +1250 C (PACKAGE TYPES D. F)
. . . ...
500mW
Derate Linearly at 12 mW/oC to 200 mW
. .
500mW
Derate Linearly at 12 mW/oC to 200 mW
OEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA FULL PACKAGE·TEMPERATURE RANGE (All Package Types)
OPERATING-TEMPERATURE RANGE IT AI
PACKAGE TYPES D. F, H
PACKAGE TYPE E
STORAGE TEMPERATURE RANGE ITstgl
LEAD TEMPERATURE lOURING SOLDERINGI:
At distance 1/16 + 1/32 IIlch (1.59 + 0.79 mmJ from case for 10 s max.
100mW
-55 to +125°C
-40 to +8S o C
-65 to +1500 C
DRAIN-TO-SOURCE VOLTAGE (VOs!-Y
Fig. 3 - Typical n-channel output low (sink)
current characteristics.
210 ____________________________________________________________________
CD4060B Types
STATIC ELECTRICAL CHARACTERISTICS
U
LIMITS AT INDICATED TEMPERATURES (OC)
CHARACTERISTIC
CONDITIONS
Vo
(V)
Quiescent
Device
Current,
IDD Max.
Output Low
(Sink)Current*
IOL Min.
Output High
(Source)
Current*,
IOH Min.
Output Voltage:
Low·Level,
VOL Max.
Output
Voltage:
High-Level,
VOH Min.
Input Low
Voltage
VIL Max.
Input High
Voltage,
VIHMin.
Input Current
liN Max.
-
+25
VIN VDD
IV)
(V) -55
-40
+85
+125
Min_
Max.
Typ.
-
0,5
5
5
5
150
150
-
0,10
10
10
10
300
300
-
0,15
15
20
20
600
600
0,20
20
100
100
3000
3000
0.4
0,5
5
0.64
0.61
0.42
0.36
0.51
1
0.5
0,10
10
1.6
1.5
1.1
0.9
1.3
2.6
1.5
0,15
15
4.2
4
2.8
2.4
3.4
6.8
4.6
0.5
-0.42 -0.36 -0.51
-1
5 -0.64 -0.61
0.04
5
0.04
10
0.04
20
0.08
100
2.5
0,5
5
-2
-1.8
-1.3 -1.15
-1.6
-3.2
-
0,10
10
-1.6
-1.5
-1.1
-0.9
-1.3
-2.6
-
13.5
0,15
15
-4.2
-4
-2.8
-2.4
-3.4
-6.8
-
5
0.05
-
0 0.05
0.05
-
0 0.05
0,15
15
0.05
-
0 0.05 V
15
-
-
1.5
-
3
-
4
5
4.95
4.95
5
9.95
9.95
10
0,15
15
14.95
14.95
5
1.5
10
3
15
4
5
3.5
3.5
1,9
-
10
7
7
1.5,13.5
-
15
11
11
0,18
18
0.5,4.5
-
±0.1
±0.1
-
±1
-
±1
-
DRAIN-lO-SOURCE VOL.TAGE IVosl-V
mil
10
10
.5,13.5
current characteristics.
0,5
0,5
1,9
DRAIN-le-SOURCE VOL.TAGE (Vosl-V
Fig. 4 - Minimum n-channel output low (sink)
0.10
0,10
0.5,4.5
Il A
-
9.5
-
N
I
T
S
Values at -55, +25, +125 Apply to D,F,H Packages
Values at -40, +25, +85 Apply to E Package
Fig. 5 - Typical p-channel output high (source)
curren t characteristics.
DRAIN-lO-SOURCE VOLTAGE (Vosl-V
V
-
±10- 5 ±0.1 jlA
* Data not applicable to terminal 9 or 10.
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that operation is
always within the following ranges
CHARACTERISTIC
LIMITS
VDD
MIN.
Supply-Voltage Range (For T A = Full Package
Temperature Range)
-
3
18
Input-Pulse Frequency. ft/>I (External pulse source)
5
10
15
-
-
3.5
8
12
Reset Pulse Width, tw
5
10
15
120
60
40
-
trt/>· tft/>
V
-
-
r
~150
-
100
40
30
Input·Pulse Rise Time and Fall Time,
current characteristics.
MAX.
5
10
15
5
10
15
Input·Pulse Width, tw (f = 100 kHz)
Fig. 6 - Minimum p-channel output high (source)
UNITS
ns
t
~ 100
Unlimited
\ov
\ V
MHz
w
-
_
w
00
00
LOAD CAPAClTANCE {CL1-pF
ns
Fig. 7 - Typical propagation delay time {On to
as a function of load capacitance.
an +1J
211
CD4060B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at T A
= 25°C, Input tI , tf = 20 ns,
CL = 50 pF, RL = 200 kQ
CHARACTERISTIC
TEST
CONDITIONS
LIMITS
UNITS
VDO
(V)
MIN.
TYP.
MAX.
Input-Pulse Operation
Propagation De lay
Time.
468102 2
468 103 2
INPUT fRE~UENCY ('."II-IIHz
468 104
92C5-31251
Fig. 10 - Typical dynamic power dissipation as a
function of input frequency.
C XTAL: C I+C2+ eSTRAY
RC· ~~~~g~~tREaUENCY
RS.CURRENT LIMITING
92CS- 31253
92'CS-312'!54
Fig. 11 - Dynamic power dissipation test circuit.
Fig. 12 - Typical RC circuit.
Fig. 13 - Typical crystal circuit.
212 _______________________________________________________________________
<
CD4060B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C, Input tr,t, = 20 ns,
Cl = 50 pF, Rl = 200 k!l [cont'd)
INPUTS
liMITS
TEST
CONDITIONS
CHARACTERISTIC
o
UNITS
VDD
(V)
Min.
Typ.
Max.
5
10
15
18
20
21.1
21.5
23
24
25
26
27
Vss
RC Operation
Variation of Fre·
quency (Unit·to·Unit)
Cx = 200pF.
RS= 560 k!l.
RX = 50 k!l
Variation of Fre·
quency with voltage
change (Same Unit)
Cx = 200pF.
RS= 560 k!l.
RX = 50 k!l
RX max.
Cx = 10/lF
= 50/lF
= 10/lF
5
10
15
RX=500k!l
=300 k!l
=300 k!l
5
10
15
RX = 5k!l
Cx = 15 pF
10
15
Cx max.
Maximum Oscillator
Frequency'
Drive Current at
Pin 9 (For Oscillator
Design)
IOl
IOH
VSS
kHz
5V to 10 V
10Vto 15V
-
-
Fig. 14 - Quiescent device current.
2
1
20
20
10
M!l
-
-
-
-
/IF
-
-
1000
50
50
530
690
650
800
810
940
kHz
,.PUTQVDO
OUTPUTS
v,"
'-
~
:t
V~L
Vss
NOTE:
TEST ANY COMBINATION
OF INPUTS
Fig. 75 - Input voltage.
VO= 0.4 V
=0.5V
=1.5V
5
10
15
VO=4.6V
-9.5V
= 13.5V
5
10
15
-
-
-
0.36
0.8
3
-
-0.35
-0.8
-3
-
Voo
-
~
~::~~:';I!~~~~S
Vss
TO BOTH Voo ANO Vss·
CONNECT ALL UNUSED
mA
INP(JUS
VOO
NOTE.
INPUTS TO EITHER
• RC oscillator applications are not recommended at supply voltages below 7 V for RX = 50 kn.
Voo OR VSS·
VSS
Fig. 16 - Input current.
TERMINAL DIAGRAM
0'2
013
01.
OS
O'
07
O.
I.
2
•
Vss
IS
VOO
,.
010
08
O'
RESET
"
"
12
"
10
9
.1
+0
00
(TOP VIEW)
92CS-23761R2
DimenSions In parentheses afe in millimeters and
are derived from (he baSIC Inch dimensions as in·
dlcated. G"d graduations are in mils "(13 inch).
Thtl photographs and dimensions 'BPresent
chip when it is pan of the wafer. When the
w.fer·;s cut into chips, the cleavage angles
are 57° instead of 90° with respect to the
fBeIl of the chip. Therefore. the isolated
chip is IICtually 7 mils (0.77 mm) larger
in both dimen~ions.
II
92CM-31255
Dimensions and pad lavout for CD4060B.
213
CD4063B Types
COS/MOS 4-Bit Magnitude
Comparator
High Voltage Types (20-Volt Rating)
The RCA-CD4063B is a 4-bit magnitude comparator designed for use in computer and
logic applications that require the comparison
of two 4-bit words. This logic circuit detetmines whether one 4-bit word (Binary or
BCD) is "less than", "equal to", or "greater
than" a second 4-bit word.
The CD4063B has eight comparing inputs
(A3, B3, through AO, BO), three outputs (A
< B, A = B, A > B) and three cascading inputs
(A < B, A = B, A > B) that permit systems
designers to expand the comparator function
to B, 12, 16 . . . 4N bits. When a single
CD4063B is used, the cascading inputs are
connected as follows: (A < B) = low, (A = B)
= high, (A> B) = low.
For words longer than 4 bits, CD4063B devices may be cascaded by connecting the
outputs of the less·significant comparator to
the corresponding cascading inputs of the
more-significant comparator. Cascading inputs (A < B, A = B, and A > B) on the
least significant comparator are connected to
a low, a high, and a low level, respectively.
o
Features:
WORDA
• Expansion to 8, 12, 16_ ... 4N bit,s by cascading units
• Medium-speed operation:
compares two 4-bit words
hi 250 ns (typ.) at 10 V
• 100% tested for quiescent current at 20 V
" Standardized symmetrical output characteristics
.5-V, 10-V, and 15-V parametric ratings
CASCADING
A>8
Aae
ACB
92C$-24516
FUNCTIONAL DIAGRAM
B'
(AB)IN
CA>B1OUT
IA'81ouT
(AcB)OUT
I.
2
I.
I.
I.
13
12
"
10
"so
.
VDD
B.
A2
AI
81
/10
eo
(TOP VIEW)
Applications:
92CS-24!52~,
• Servo motor controls
RECOMMENDEO OPERATING CONDITIONS
For maximum reliability, nominal operating
conditions should be selected so that
operation is always within the following ranges:
LIMITS
CHARACTERISTIC Min_
Max. UNITS
Supply-Voltage Range
3
18
V
(For T A=Full Package·
Temperature Range)
.
WORDB 4
• Maximum input current of 1 p.A at 18 V
over full package temperature range;
100 nA at 18 V and 25°C
• Noise margin (full package temperature range)
range) = 1 V at VDD = 5 V
2 VatVDD = 10V
2.5 V at VOD = 15 V
• Meets all requirements of JEDEC Tentative
Standard No. 13A, "Standard Specifications
for Description of 'B' Series CMOS Devices"
The CD4063B types are supplied in 16-lead
hermetic dual-in-line ceramic packages (D
and F suffixes). 16-'lead dual-in-line plastic
package (E suffix), 16-lead ceramic flat
package (K suffix). and in chip form (H
suffix). This device is pin-compatible with
the standard 7485 TTL type.
A>9
A-S
INPUTS tACB
• Process controllers
TERMINAL ASSIGNMENT
MAXIMUM RATINGS, Absolute-Maximum Values:
OC SUPPLY-VOLTAGE RANGE, (V DO)
(Voltages referenced to VSS Terminal)
- B3
A3 = B3
X
A2> B2
A2 = B2
= B3
= B3
A3 = B3
A3 = B3
A3 = B3
A3 = B3
A3 = B3
A3 = B3
= B2
A2 = B2
A2 = B2
A2 = B2
A2 = B2
A2 = B2
A3< B3
X
A3
A3
A2
A2< B2
x = Don't Care
A1, Bl
AB
AB
X
X
X
X
X
X
X
X
X
X
X
a
a
a
a
I
1
X
= BO
AO = BO
AO = BO
a
a
a
1
1
1
0
a
a
a
a
a
a
a
a
1
AO< BO
X
X
X
X
1
X
X
1
a
a
a
a
a
AO, BO
X
X
X
X
X
AI> Bl
Al
i Al
Al
Al
Al
= Bl
= Bl
= Bl
= Bl
= Bl
OUTPUTS
CASCADING
AO>BO
AO
Al 8)IN~I-1
(A=BlIN 3
*
·3
'3
.2'2
!!2
~A
Vss
* BYALLTHE
INPUTS PROTECTED
COS/MOS PROTECTION
NETWORK
'2
~,
A,
.,
I
AI
I
I'
I
80
'0
I, ·0
'0
'l£:~~_._.
Fig. 4 - Minimum output low (sink)
current characteristics.
'
,
DRAIN-lO-SOURCE VOLTAGE (Vosl-V
______ .___I
1
92CL-30935
Fig. 2 - Logic diagram for CD4063B.
DYNAMIC ELECTRICAL CHARACTERISTICS
At TA = 25'C; Input tT, tf= 20ns, CL = 50pF, RL = 200kfl.
Fig.
TEST CONDITIONS
CHARACTERISTIC
VDD
Volts
ALL TYPES
LIMITS
Typ.
DRAIN-lO-SOURCE VOLTAGE tvosl-V
UNITS
Max.
5
10
15
625
250
175
1250
500
350
Cascading Inputs to
Outputs, tpH L, tp LH
5
10
15
500
200
140
1000
400
280
5
10
15
100
50
40
200
100
80
ns
5
7.5
pF
tTHL' tTLH
Input Capacitance, CIN
Any Input
Typical output high (source)
current characteristics.
Propagation Delay Time:
Comparing Inputs to
Outputs, tpH L, tpLH
Transition Time,
5-
ns
Fig.
6 - Minimum output high (source)
current characteristics.
216 __________________________________________________________________--
CD40638 Types
1
AMBIENT TEMPERATURE (T"I" 25"C
600
PPl.'f VOI-iME
\IIOD1.5~
~500
1400
f
1500
j~
12!l0
~
~
750
~
~
.00
~
10
ro
~
~
~
ro
~
U)AD CAPACITANCf;
I~ 1 -
250
0
~
..ql rlih I ,lllIPHl! Iii! :I!! :11;
..(Pi ,i! Ii! "ji i:!,. Hi ::q !ll
!jII
"
"
I!l
I;
I
I
Ii~
.
...
pf
:1
, i!
~
"
!
,.
!
;1
~
lE
o
1 AMBIENT TEMPERATURE (TAl- 25"C
.LOAD7'~I,T~NCE,(7LI~??Pf. .
:'!]
~ 1000
~
.,!:
I 'l!
''!.! J
ill
If
7.'
10
12.5
SUPPLY VOLTAGE 'VoDl-v
"
11.5
'0
ill
LOAD CAPACITANCE eell-pF
Fig. 7 - Typical propagation delay time
vs. load capacitance (Ucomparing
inputs" to outputs).
Fig. 8 -. Typical propagation delay ti';"e vs_ supply
voltage '''comparing inputs" to outputs).
VDD
I N P u Voo
Ds
~
:~:~~RE
Fig. 9 - Typical transition time vs. load capacitance.
INPUTS
SEQUENTIALLY,
TO BOTH VDO AND VSS'
CONNECT ALL UNUSED
lNPUTS TO EITHER
Voo ORVSS '
Vss
VSS
0.1 2
.. III
I ""102 ""10.11
INPUT FREQUENC'f{fJ-IIHI
""1012
0"
4181
Fig. 11 - Input current test circuit.
Fig. 10 - Typical power dissipation vs. frequency
(see Fig. 12 - dynamic power
dissipation test circuit).
Fig. 12 - Dvnamic power dissipation test circuit.
INPUTOVCO
OUTPUTS
V,H
~
'-
l
v~\.
Vss
HOTE:
TEST ANY COMBINATION
Of INPUTS
60-68
(1.524 -I. 727)
52CS-2744IRI
Fig. 13 - Input-voltage test circuit.
INPUTS
4-10
(0.102-0.254)
o
Vss
77-85
(1.956 -2.159)
92CS-24802
. Dimensions and pad layout for CD4063BH.
Dimensions in fJllflnthtJs. am in millimstsf'S and arB
dBrivsd from ths basic inch dimensions as indicatfld.
Vss
92e5-2740IlU
Fig. 14 - Ouiescent-device-current test circuit.
Grid graduation. are in mil. (10-3 inch).
The photographs and dimensions of each COS/MOS
chip represent a chip when it is part of the wafer.
When the wafer is cut into chips, the cleavage
angles are 57° instead of 90° with respect to the
face of the chip. Therefore, the isolated chip is
actuallv 7 mils (0. 17 mm) larger·in both dimensions.
__________________________________________________________________ 217
CD4066B Types
COS/MOS Quad Bilateral
Switch
For Transmission or Multiplexing of Analog or
Digital Signals
Features:
High-Voltage Types (20-Volt Rating)
• 1S-V digital or ±7_S-V peak-to-peak switching
The RCA-CD4066B is a quad bilateral switch
intended for the transmission or multiplexing of analog or digital signals. It is pin-forpin compatible with RCA-CD4016B, but
exhibits a much lower on-state resistance. In
addition, the on-state resistance is relatively
constant over the full input-signal range.
• 12Sn typical on-state resistance for 1S-Voperation
• Switch on-state resistance matched to within Snover
1S-V signal-input range
• On-state resistance flat over full peak-to-peak signal
range
• High on/off output-voltage ratio: 80 dB typ_ @
fis = 10kHz, R L = 1 kn
• High degree of linearity: 1 ~ !
,. O......I____..,.?......
1.lOuT
VOD"24
Vss
s
12
92CS- 24924RI
'N/~UT
Fig. 1 - CD4067 functional diagram.
Y
: I
{ I I
-r
'f................ '- I
+
I
{~-'--+-~--+--;.
I
-..........
I
'N/OUT
I
7
VOO ~24
CD4067 TRUTH "tABLE
Vss
Selected
Channel
A
B
C
0
Inh
X
X
0
0
1
X
0
0
0
X
0
0
0
1
0
0
0
None
0
0
1
1
1
0
0
0
0
0
0
0
0
3
4
S
6
I
0
0
0
0
0
1
1
0
0
0
0
0
8
9
10
11
I
I
I
I
1
1
1
0
0
0
0
12
13
14
15
0
1
0
I
1
0
0
0
I
I
current may· include both VOO and signal·1 ine
components. To avoid drawing V DO current when
switch current flows into the transmission gate
inputs, the voltage drop across the bidirectional
switch must not exceed 0.8 volt (calculated from
RON values shown in ELECTRICAL CHARAC·
TERISTICS CHART). No VOO current will flow
through RL if the switch current flows into
terminal 1 on the CD4067; terminals 1 and 17 on
0
I
1
the CD4097.
0
0
0
I
I
0
I
0
0
0
I
I
0
I
I
I
I
1
I
I
louillN
F"-"'-
';;:ro-l
92CS·24980R2
"12
Fig. 2-CD4097 functional diagram.
1
2
7
-..........
10U,'"N
CD4097
TRUTH TABLE
Selected
A
B
C
Inh
X
X
I
0
I
0
0
0
I
X
0
I
0
I
0
I
I
0
0
I
I
OIannel
None
0
0
0
0
0
OX,OY
IX,IY
2X,2Y
0
I
I
I
I
0
0
0
0
0
3X,3Y
4X,4Y
5X,5Y
6X,6Y
7X,7Y
_____________________________________________________________________ 223
CD4067B, CD4097B Types
ELECTRICAL CHARACTERISTICS
CHARACTERISTIC
LIMITS at Indicated Temperature (oC)
Values at -55,+25,+125,apply to D,H pkg
Values at -40,+25,+85,apply to E pkg
CONDITIONS
VSS
VDD -55
Vis
(V)
(V)
(V)
SIGNAL INPUTS (Vis) AND OUTPUTS (VOS)
5
10
15
20
Quiescent
Device Cur·
rent,lDD
Max.
-40
+85
+125
+25
Min.1 Typ.
5
10
20
100
5
10
20
100
150
300
600
3000
150
300
600
3000
Units
-
0.04
0.04
0.04
0.08
I Max_
5
10
20
100
Il A
INPUT SIGNAL VOl.TAGE IVlsl -
II
92CS-21326
ON-state Re
Fig. 3- Typical ON resistance vs. input signal
sistance
VSS';;
Visi;;;V OO
ron Max.
Change in
on·state
Resistance
(Between
Any Two
Channels)
b.ron
OFF Channel Leakage Current: Any
Channel
OFF Max.
or
All Channels OFF
(Common
OUT/IN)
Max.
Capacitance:
Input, Cis
Output,
Cos
CD4067
CD4097
Feed·
through,
Cios
Propaga·
tion Delay
Time (5ig'
nal Input
to Output
5
10
15
800
310
200
0
0
0
5
10
15
-
-
-
-
-
-
-
-
-
-
-
-
-
850
330
210
1200 1300
520
550
320
300
470
180
125
-
0
0
0
-
-
15
10
5
1050
400
240
-
voltage (all types).
!~
n
·10
-75
-5
-2.5
0
2.5
7.5
10
INPUT.SIGNAL VOLTAGE IVlsl-II
0
18
±100'
to.l
-
±1000'
±100'
nA
Fig. 4- Tvpical ON resistance vs. input signal
voltage fall types}.
-
-
-
-
-
5
"I
-
SUPPLY VOLTAGE IVoo -VS5) -"
z
~2:!50
.
>-
;;;H;
~
-5
5
-
-
-
-
-
-
55
35
-
-
-
-
-
-
-
-
0.2
:!
-
pF
VOO
.n.
CL ~50 pF
tr,tf~20 ns
5
10
15
-
-
-
-
--
-
-
-
-
60
30
-
10
20
AMBIENT TEMPERATURE
(TA)-+125·C
:::t
ii:l
::'!
••• : ...... ".
~ 100
30
15
tt!
~:iI
~
-
RL~200K.n
IT
2oo i: 1•
~ 150~:tt
I
v
300
50
+25-C
~ :~~!{.:
":1' :::: .::: ::~
:~.Ij=:; ~illi:':;
0
-10
-7.5
-5
-2.5
0
2.5
·Imll!ln
INPUT SIGNAL VOLTAGE (ViS I -
ns
7.5
10
V
92CS-27329
Fig. 5- Typical ON resistance vs. input signal
voltage (al/ types).
CONTROL (ADDRESS or INHIBIT) Vc
Input Low
Voltage,
V IL Max.
'Input High
Voltage,
VIH Min.
RL -1 Kn
to VSS
~VDD
IIS<2Il A
thru on all OFF
1 K£l
Channels
5
1.5
-
-
1.5
10
3
-
15
4
-
3
4
5
3.5
3.5
-
10
7
7
15
11
11
-
V
-
• Determined by minimum feasible leakage measurement for automatic testing.
Fig. 6- Typical ON resistance vs. input signal
voltage (all types).
224 ______________________________________________________________________
CD4067B, CD4097B Types
ELECTRICAL CHARACTERISTICS (Cont'd)
CHARAC-
TEST CIRCUITS
LIMITS at Indicated Temperature (OC)
Values at -55,+25,+125,apply to D,H pkg
Values at -40,+25,+85,apply to E pkg
CONDITIONS
TERISTIC
Vis
VSS
VDD
(V)
(V)
(V)
VIN=0,18V
18
-55
-40 +85
+125
Units
Voo
Voo
+25
Min. Typ.
2'
Max.
Vss
"
"
22
Input
Current,
liN Max.
Propagation
R L =lO K!l,C L c
Delay Time:
50 pF, t"tf=20 11>
Address or
Inhibit-toO
Signal OUT
0
(Channel
0
turning ON)
Address
01
Inhibit-toSignal OUT
±1
-
±10- 5
±0.1
turning
OFF)
20
V'"
Vss
-
-
-
-
325
650
-
-
-
-
-
135
270
-
-
-
-
-
95
190
5
-
10
15
0
5
-
-
-
-
-
220
440
0
10
-
-
-
-
c_
90
180
0
15
-
-
-
_c
-
65
130
-
-
-
-
-
5
Any Address or
Inhibit Input
MAXIMUM RATINGS, Absolute-Maximum
DC SUPPLY·VOL TAGE RANGE, (VDDI
ns
7.5
ns
pF
Values:
Fig. 7-0FF channel leakage current-any channel OFF.
-0.5 to +20 V
-0.5 to VOD +0.5 V
(Voltages referenced to VSS Terminal)
INPUT VOLTAGE RANGE, ALL INPUTS
DC INPUT CURRENT, ANY ONE INPUT
±10mA
POWER DISSIPATION PER PACKAGE (Pol:
For TA = -40 to +60 0 C (PACKAGE TYPE EI . .
. . . . . . . ..
500 mW
'.'
Derate Linearly at 12 mW/oC to 200 mW
For T A = +60 to +85 0 C (PACKAGE TYPE EI
For T A = -55 to +1000 C (PACKAGE TYPES 0, FI .
. . . . . . . ..
500 mW
For TA = +100 to +1250 C (PACKAGE TYPES 0, Fl.
De~ate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
- FOR TA = FULL PACKAGE·TEMPERATURE RANGE (All Package Typesl
100mW
OPERATING· TEMPERATURE RANGE (TAl:
PACKAGE TYPES 0, F, H
-55 to +125 0 C
-40 to +8SoC
PACKAGE TYPE E .
STORAGE TEMPERATURE RANGE (Tstgl
-65 to +150 0 C
LEAD TEMPERATURE (DURING SOLDERINGI:
At distance 1/16
I.,.
I.
I1A
RL=300 Il,C L =
50 pF, t ,-,tf=20 ns
(Channel
Input
Capacitance, CIN
±0.1 ±0.1 ±1
± 1/32
Voo
voo
24
0
Vss
"
22
21
20
voo
inch (1.59 ± 0.79 mm) from case for lOs max.
"
I.
"
Vss
Voo
Voo
"23
22
.
I.
"20
,
,
Fig. 8-lnput voltage-measure
(e.g.; channel 12).
<2 ,uA on all OFF channels
Fig. 9- OFF channel leakage current-all channels OFF.
_____________________________________________________________________ 225
CD4067B, CD4097B Types
ELECTRICAL CHARACTERISTICS (Cont'd)
TEST CIRCUITS (Cont'd)
Voo
TEST CONDITIONS
CHARACTERISTIC
Vis
(V)
VDD
(V)
RL
Cutoff
(-3-dB)
Frequency
Channel ON
(Sine Wave
Input)
5-
10
1
Total
Harmonic
Distortion,
THO
TYPICAL
VALUES
(KQ)
Vos
20 log -=-3 dB
Vis
Vas at Common OUT/IN
C04067
C04097
Vas at Any Channel
14
20
60
UNITS
,.
"
"
"'0
I.
I.
MHz
"
17
VIX>
2-
5
3-
10
S-
IS
0.3
10
0.2
0.12
%
lis = 1 kHz sine wave
510
1
-40·dB
Feedthrough
Vas
Frequency
(All Channels 20 log -=-40 dB
Vis
OFF
5Signal Crosstalk (Fre·
quencyat
-40 dB)
-
10
Vas at Common O}.lT/IN
C04067
C04097
20
12
Vos at Any Channel
8
Between Any 2 Channels'"
1
,.
MHz
"
"
"
I.
,0
1
Vas
20 log -=-40 dB
Vis
-
Address·or·
Inhibit·to·
Signal
Crosstalk
10
Voo
Between
Sections
C04097
Only
"
7
Measured on Common
10
Measured on Any
Channel
18
•
17
•
VIX>
MHz
10'
VSS=O, tr,tj=20 ns,
VC=VOO-VSS
(Square Wave)
Fig. 10- Quiescent device current.
mV
(Peak)
75
Voo-Vss
Peak-ta-peal< voltage symmetrical about - - - - .
2
... Worst case.
Both ends of channel.
•
•
"
21
20
I.
19
17
I.
I.
VOO
-IL-.:vss
92CS-27342RI
Voo
V2D
,.
vSS
2'
2'
•
5
"
20
I.
I.I.
"
17
Vo
10
voo
-IL-.:
92CS-2734IRI
Fig. 11- Turn-on and turn-off propagation delay-address select input to signal output
VS5
92CS-21343RI
Fig. 12- Turn-on and turn-off propagation de/ay-
(e.g. measured on channel OJ.
226 ________________________________________________
inhibit input to s;gnal output (e.g. measured
on channel 1J.
~------------------
CD4067B, CD4097B Types
~I
,~
~U7.~~~;:
TURN- ON TIME - -
Fig. 13-Channel ON resistance measurement circuit.
,•
y~ I~&)C~
Fig. 14-Propagation delay waveform channel
being turned ON (R L =10 Kf!. CL = 50 pFJ.
Fig_ 15-Propagation delay waveform, channel
being turned OFF (R L = 300 ll.
CL =50pFJ.
CHANNEL IN/OUT
::
~~)(~r ~ 9.~ ~
63
:
~
'
z
~IFJ (!6
18
19
I
2
2)l')l4Jl~l';il?\".~ls-_ ..
~
~
~ 8;2~,It
~
X OUll
9-
~
yY
!i
~~
m
*11
*14
BB:S--
~
iii
%
~
15
~
~
B-
~
0
->
i;T-
~
~
z
iii
B-~
COMM ON
17
B-
IN
~
~-
Vss"
Sf'
f*ALL INPUTS PROTECTED BY
COS/MOS PROTECTION NETWORK
Vss
Fig. 76-CD4067 Jogic diagram.
12
92CM-27328
Vss
VDO
E3f
--
Vss
'*ALL INPUTS PROTECTED BY
caS/Mos PROTECTION
NETWO~I(
92CM-27331
Fig. 17-CD4097/ogic diagram.
227
CD4067B, CD4097B Types
SPECIAL CONSIOERATIONS
In applications where separate power sources
are used to drive VOD and the signal inputs,
the VOD current capability should exceed
VDD/RL (RL =effective external load). This
provision avoids permanent current flow or
clamp action on the VDD supply when power
is applied or removed from the CD4067B or
CD4097B.
When switching from one address to another,
some of the ON periods of the channels of
the multiplexers will overlap momentarily,
which may be objectionable in certain applications. Also when a channel is turned on or
off by an address input, there is a momentary conductive path from the channel' to
VSS, which will dump some charge from any
capacitor connected to the input or output
of the channel. The inhibit input turning on
a channel will similarly dump some charge to
VSS·
The amount of charge dumped is mostly a
function of the signal level above VSS.
Typically, at VOD-VSS=10 V, a 100-pF
Dimensions and pad layout for CD40678H.
capacitor connected to the input or output
of the channel will lose 3-4% of its voltage at
the moment the channel turns on or off.
This loss of voltage is essentially independent
of the address or inhibit signal transition
time, if the transition time is less than 1-2 /15.
When the inhibit signal turns a channel off,
there is no charge dumping to VSS. Rather,
there is a slight rise in the channel voltage
level (65 mV typ.) due to capacitive coupling
from inhibit input to channel input or output.
Address inputs also couple some voltage
steps onto the channel signal levels.
In certain applications, the external load-
resistor current may include both VDD and
signal-line components. To avoid drawing
VDD current when switch current flows into
the transmission gate inputs, the voltage drop
across the bidirectional switch must not exceed 0.8 volt (calculated from RON values
shown in ELECTRICAL CHARACTERISTICS CHART). No VDD current will flow
through R L if the switch current flows into
terminal 1 on the CD4067B, terminals 1 and
17 on the CD4097 B.
Dimensions and pad layout for CD4097BH.
The photographs and dimensions of each COS/MOS
chip represent a chip when it is part of the wafer.
Dimensions in parentheses are in milNmeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10- 3 inch).
When the w~fer ;s cut into chips, the cleavage
angles are 57 instead of 90° with respect to the
face of the chip. Therefore. the isolated chip is
actually 7 mils (0.17 m"!) larger in boch dimensions.
228 __________________________________________________________
CD4068B Types
Features:
COS/MOS a-Input
NAND/AND Gate
High-Voltage Types (20-Volt Rating)
The RCA-CD4068B NAND/AND gate provides the system designer with direct implementation ofthe positive·logic a-input NAND
and AND functions and supplements the
existing family of COS/MOS gates.
The CD4068B types are supplied in 14-lead
dual-in-line ceramic packages (0 and Fsuffixes), 14-lead dual-in-line plastic packages
(E suffix). 14-lead ceramic flat packages (K
suffix), and in chip form (H suffix).
K-A-B·C·Q·E·F'G·H
A
,.
,
,.
voo
"
H
2
12
JzA·B·C·D·E ·f·G·H
• Medium-Speed Operation:
tpHL, tpLH = 75 ns hyp.) at VDD = 10 V
• Buffered inputs and outputs
• 5-V, 10-V, and 15-V parametric ratings
• Standardized symmetrical output characteristics
• 100% tested for quiescent current at 20 V
• Maximum input current of lilA at 18 V
over full package-temperature range;
100 nA at 18 V and 25 0 C
• Noise margin (over full package-temperature
range): 1 Vat VDD = 5 V
2 V at VDD = 10 V
2.5 Vat VDD = 15 V
• Meets all requirements of JEDEC Tentative
Standard No. 13A, "Standard Specifications
for Description of 'B' Series CMOS Devices"
Voo -14
Vss .7
6,8' NO CONNECTION
92CS-2lB]4R3
FUNCTIONAL DIAGRAM
RECOMMENDED
OPERATING CONDITIONS
For maximum reliability, nominal' operating
c,
conditions should be selected so that operation
is always within the following ranges:
.0 ,
G
'0
NC
9
CHARACTERISTIC
NC
vss
IMin. Max. Units
(TOP VIEW)
Supply· Voltage Range
(For T A = Full Package
3
Temperature Rangel
NCoNO CONNECTION
TERMINAL ASSIGNMENT
18
V
Fig. 1 - Logic diagram.
STATIC ELECTRICAL CHARACTERISTICS
CHARACTER·
ISTIC
Quiescent Device
Current,
100 Max.
Vo
(V!
-
Output Low
(Sink! Current
IOL Min.
Output High
(Source!
Current,
IOH Min.
0.4
0.5
1.5
4.6
2.5
9.5
13.5
Output Voltage:
-
Low-Level.
-
VOL Max.
Output Voltage:
High·Level.
VOH Min.
Input Low
Voltage,
VIL Max.
Input High
Voltage,
VIH Min.
Input Current
liN Max.
LIMITS AT INDICATED TEMPERATURES (OCI
Value. at-55, +25, +125 Apply to D,F ,H Packages
Values at -40, +25, +85 Apply to E Package
UNITS
+25
VDD
..,.55
+85
Typ.
-40
+125
Min.
Max.
(V!
0.Q1
5
0.25 0.25
7.5
7.5
0.25
0.Q1
10
0.5
0.5
15
15
0.5
IJA
15
1
30
0.01
1
1
30
20
5
5
5
0.02
150
150
0.64 0.61
0.42
0.36 0.51
1
5
1.1
0.9
1.3
2.6
1.5
10
1.6
34
2.4
15
4.2
4
2.8
6.8
rnA
-1
5
-0.64 -0.61 -0.42 -0.36 -0.51
-
CONDITIONS
-
-
0.5,4.5
1,9
1.5,13.5
0.5,4.5
1,9
1.5,13.5
VIN
(V!
0,5
0,10
0,15
0,20
0,5
0.10
0,15
0.5
0.5
0.10
0.15
0.5
-
5
10
15
5
-2
-1.6
-4.2
-1.3
-1.8
-1.5
-4
-1.1
-2.8
0.10
0.15
0.5
0.10
0.15
10
15
5
0.05
0.05
0.05
4.95
10
9.~5
15
14.95
-
1.5
3
-
5
10
15
5
10
'15
0,18
18
-
:0.1
~O.l
-3.2
-2.6
-6.8
-
-
0
0.05
-
0
0
5
0.05
0.05
10
-
-1.15 -1.6
-0.9 -1.3
-2.4 -3.4
4.95
9.95
14.95
-
-
4
-
3.5
7
11
3.5
7
11
:tl
:tl
-
15
-
I
DRAIN-TO-SOURCE .... OL.TAGE ( .... os)-V
Fig. 2 - Typical output low (sink) current
characteristics.
-
-
-
1.5
3
-
-
-
-
V
4
V
I
:t1O- 5
:to. 1
DRAIN-TO-SOURCE VOL.TAGE ('105)-'1
92CS-2·"9R'
IJA
Fig. 3 - Minimum output low (sink)
current characteristics.
229
CD4068B Types
MAXIMUM RATINGS,Absolute·Maximum Values:
DRAIN-lO-SOURCE VOLTAGE (Vosl-V
DC SUPPLY·VOLTAGE RANGE. (V OO '
(Voltages referenced to VSS Terminal)
-0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS
-0.5 to VOO +0.5 V
±10mA
DC INPUT CURRENT, ANY ONE INPUT
POWER DISSIPATION PER PACKAGE (POl:
For T A = -40 to +60o C (PACKAGE TYPE EI
. . . . . . . .•
500mW
Derate Linearly at 12 mW/oC to 200 mW
For TA = +60 to +850 C (PACKAGE TYPE EI
.
For TA = -55 to +1000 C (PACKAGE TYPES O,F,I
500mW
. . . . . . . •.
For TA = +100 to +125 0 C (PACKAGE TYPES 0, F,I
Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
100mW
FOR TA = FULL PACKAGE·TEMPERATURE RANGE (All Package Typesl
OPERATING· TEMPERATURE RANGE (TAl:
PACKAGE TYPES 0, F, H
-55 to +1250 C
PACKAGE TYPE E .
-40 to +850 C
STORAGE TEMPERATURE RANGE (Tstgl
-65 to +1500 C
LEAD TEMPERATURE (DURING SOLOERINGI:
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max.
DYNAMIC ELECTRICAL CHARACTERISTICS
At TA = 25'C; Input tr , tf= 20ns, C L = 50pF, RL
DRAIN-TO-SOURCE VOLTAGE (Vos)-V
= 200kH
TEST CONDITIONS
CHARACTERISTIC
V DD
VOLTS
5
10
15
5
10
15
Propagation Delay Time,
tPHL, tPlH
Transition Time,
ITHl,lTLH
Input Capacitance, CIN
"
..
ALL TYPES
LIMITS
UNITS
TYP.
MAX.
150
75
55
100
50
40
300
150
110
200
100
80
5
7.5
Any Input
ns
ns
Fig. 5;,... Minimum output high (;;'C~~z;,r2
cu"ent characteristics.
pF
INVERTERS
DETAIL OP"NVERTERI
VD•
£~1"
II
12
I. *
*
6
Yoo
"
3
Fig, 4 - Typical output high (source)
current characteristics.
VDD
Vss
~~.
LOAD CAPACITANCE ICLI-pF
J-o"
Fig.
of load capacitance.
~'
..
6 - Typical transition time as a function
V55
d:
OD
::r--o'
*
.
'g
..
Vss
* ALL
Fig, 7 - Schematic diagram.
230
INPUTS PROTECTED BY
COS/MOS PROTECTION
NETWORK
tZCM-2t094
Fig.
8 - Typical proPBgBtion delay time
as a function of load cap8citance.
CD4068B Types
10':
AM~IENT TEMPERATURE (TAl· 2~'C:
~
AMBIENT TEMPERATURE ITAI- 2!S-C
··
III I I. IV V
~.,fJ~
Ia'.
IE
o--1-H
&
B
C~I~C
D~J.5
E~K~E
F.1.L.{)oE-L' F
Yootl 4
VSS' 7
92CS-23H1R2
CD4069UB
FUNCTIONAL DIAGRAM
Applications:
• Logic inversion
• Pulse shaping
AMBIENT TEMPER"TUIIE IT ... I-Z5"(
• Oscillators
• High-input-impedance amplifiers
RECOMMENDED OPERATING CONDITIONS
For maximum reliability. nominal operating conditio,",,; should be selected so that
operation is always within the following ranges:
LIMITS
CHARACTERISTIC
Min.
Supply·Voltage Range (For
Temperature Rangel
TA~Full
Package
3
UNITS
Max.
18
V
INPUT VOL-rAGE (VI I-V
MAXIMUM RATINGS,Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (V DD )
-0.5 to +20 V
(Voltages referenced to VSS Terminal)
-0.5 to VDO +0.5 V
INPUT VOLTAGE RANGE, ALL INPUTS
±10mA
DC INPUT CURRENT, ANY ONE INPUT
POWER DISSIPATION PER PACKAGE (PO):
o
.
.
.
.
.
.
.
.
.
500mW
For T A = -40 to +60 C (PACKAGE TYPE E)
Derate Linearly at 12 mW/o.C to 200 mW
For T A = +60 to +850 C (PACKAGE TYPE E)
.
. . . . . . . ..
500mW
For TA = -55 to +lOOoC (PACKAGE TYPES O.F)
Derate Linearly at 12 mW/oC to 200 mW
For TA = +100 to +125 0 C (PACKAGE TYPES D. F)
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
100mW
FOR T A = FULL PACKAGE-TEMPERATURE RANGE (All Package Types)
OPERATING-TEMPERATURE RANGE (TA):
-55 to +1250 C
PACKAGE TYPES 0, F, H
--40 to +85 0 C
PACKAGE TYPE E .
-65 to +1500 C
STORAGE TEMPERATURE RANGE (T"9)
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1116 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max.
OYNAMIC ELECTRICAL CHARACTERISTICS at T A = 250 C; Input 1"
Fig. 1 - Minimum and maximum voltage
transfer characteristics.
12~·C -~
2.'
7.5
10
12.5
IS
INPVr VOLTAGE 1Vtl-V
20
Fig. 2 - Typical voltage transfer characteristics as a
function of temperature.
It = 20 ns,
CL =50pF,RL -200K11
l1.lI AMBIENT TEMP€RATURE ITA)- 25" C
CONDITIONS
CHARACTERISTIC
Propagation Delay Time;
Transition Time;
Input Capacitance;
tpLH' tpHL
tTHL, tTLH
CIN
ALL TYPES
LIMITS
VOD
V
Typ.
5
55
110
10
30
60
25
50
5
100
200
10
50
100
15
40
80
10
15
rTTlTTITITlTn n
SUPPLY VOLTAGE
+t-
rID·" '"
r.r:~t
IVooI.'S~
:
li!i
UNITS
>12.'
Max.
15
Any Input
IS
I
'I'
-10
ns
~
. .v
;"
~
2.'
ns
7.5
12.5
INPUT VOLTAGE IVI)-v
pF
IS
Fig. 3 - Typical current and voltage transfer
characteristics.
232 ____________________________________________________________________
CD4069UB Types
STATIC ELECTRICAL CHARACTERISTICS
CONDITIONS
CHARACTER·
ISTIC
VIN VDD
(V)
(V)
Vo
(V)
-
Quiescent Device
Current,
IDD Max.
-
0,5
0,10
0,15
0,20
5
10
15
20
0.4
0.5
1.5
4.6
2.5
9.5
13.5
0,5
0,10
0,15
0,5
0,5
0,10
0,15
5
10
15
5
5
10
15
-
5
5
-
10
15
10
15
5
10
15
4.5
1
-
1.5
-
5
10
15
5
10
15
0,18
18
-
Output Low
(Sink) Current
IOL Min.
Output High
(Source)
Current,
IOH Min.
Output Voltage:
Low·Level,
VOL Max.
Output Voltage:
High·Level,
VOH Min.
Input Low
Voltage,
VIL Max.
0
0
0
9
13.5
0.5
Input High
Voltage,
VIH Min.
Input Current
liN Max.
~,',R,~T~~,', I
LIMITS AT INDICATED TEMPERATURES (OC)
Values at -55, +25, +125 Apply to D,F,H Packages
Values at -40, +25, +85 Apply to E Package
+25
-55
-40
+85
0.25
0.5
1
5
0.25
0.5
1
5
7.5
15
30
150
0.64
1.6
4.2
-0.64
-2
-1.6
-4.2
0.61
0.42
1.5
1.1
4
2.8
-0.61 -0.42
-1.8
-1.3
-1.5
-1.1
-4
-2.8
+125
Min.
Typ.
Max.
7.5
15
30
150
-
0.Q1
0.Q1
0.25
0.5
1
5
0.36
0.9
2.4
-0.36
-1.15
-0.9
-2.4
0.51
1.3
34
-0.51
-1.6
-1.3
-3.4
1
2.6
6.8
-1
-3.2
-2.6
-6.8
-
0
0.05
0
0
5
10
15
0.05
0.05
0.05
0.05
0.05
4.95
9.95
14.95
4.95
9.95
14.95
1
-
-
2
2.5
4
8
-
-
-
-
4
12.5
±0.1
±0.1
0.01
0.02
±1
-
DRAIN-lO-SOURCE VOL.tAGE lVasl-V
I'·'''."'.
-
-
±O.l
JL-
a
V
~
I"
DRAIN-lO-SOURCE VOLTAGE (Vos)-V
9lCS·2oJI'"'
Fig. 5 - Min.imum output low (sink)
current characteristics.
V
."
A-~I-VDD
B- •
G"
u
'10
~~-..s~ ~v~Lt~G~~t';G's~:-5V
0
$. ~.,
T,
~ :f:j $lltl!::: :::~jE
.- ':: !fl. 11m J:, !. : ~
JlA
. -.................
G-i- 2
n U"
A
113.5,9,11,131
.,
DRAIN-lO-SOURCE VOL.TAGE IVosl-V
AMalEN T TEMPERATl.IRE ITA'o2'·C
:::: -10
d
n
-----AII'
".
I~
Voo
Voo
'~·"'·jj""U;i't
Ii
-
-
~."8.'
mA
-
-
'leo.
current characteristics.
-
1
2
2.5
I
Fig. 4 - Typical output low (sink)
-
-
J
4 K
F •
E •
H 12
"
M
C04071B
FUNCTIONAL DIAGRAM
• >
E
F 10
"
H 12
Vss
92CS-2:1686
LIMITS AT INDICATED TEMPERATURES (OC)
Value. at -55, +25, +125 Apply to D;F,H Package.
Values at -40, +25, +85 Apply to E Package
CONDITIONS
CHARACTERISTIC
Quiescent Device
Current,
100 Max.
Output Low
(Sink) Current
IOL Min.
Output High
(Source)
Current,
IOH Min.
Output Voltage:
Low·Level,
VOL Max.
Output Voltage:
High·Level,
VOH Min.
Input Low
Voltage,
VI!. Max.
Input High
Voltage,
VIH Min.
Input Current
liN Max.
238
Vo
(V)
VIN VDD
(V)
(V)
+25
-55
-40
+85
+125
0.25
0.25
7.5
-
0,5
0,10
0,15
0,20
5
10
15
20
0.4
0.5
1.5
4.6
2.5
9.5
13.5
-
D,S
0,10
0,15
0,5
5
10
15
5
5
10
15
0,5
5
-
0.10
0.15
0.5
0,10
0,15
10
15
5
10
15
0.05
0.05
0.05
4.95
9.95
14.95
-
5
10
15
5
10
15
1.5
3
4
3.5
7
11
0.18
18
-
0.5,4.5
1,9
1.5,13.5
4.5
9
13.5
0.5
0.10
0,15
-
0.5
1
15
0.5
1
30
5
5
150
0.64 0.61
0.42
1.6
1.5
1.1
4
2.8
4.2
-0.64 -0.61 -0.42
-2
-1.8
-1.3
-1.6 -1.5
-1.1
-4.2
-4
-2.8
±0.1
±0.1
Min.
Typ.
Max.
7.5
-
15
30
-
0.01
0.01
0.25
0.5
0.51
1.3
34
-0.51
-1.6
-1.3
-3.4
0.01
0.02
1
2.6
6.8
-1
-3.2
-2.6
-,6.8
1
5
-
-
-
0
0.05
-
0
0
5
10
15
0.05
0.05
-
1.5
3
4
150
0.36
0.9
2.4
-0.36
-1.15
-0.9
-2.4
-
-
4.95
9.95
14.95
-
3.5
7
11
±1
±1
-
±10- 5
CD4072B
FUNCTIONAL DIAGRAM
UNITS
p.A
•
J
-
-
rnA
10
92C5-21667
CD4075B
FUNCTIONAL DIAGRAM
V
-
±0.1
L
V
p.A
CD40718, CD40728, CD40758 Types
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (VDOI
(Voltages referenced to VSS Terminal)
-0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS
-0.5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT
±10mA
POWER DISSIPATION PER PACKAGE (Pol:
For T A = -40 to +60 0 C (PACKAGE TYPE EI
..
......
500mW
For T A = +60 to +85 0 C (PACKAGE TYPE EI
Derate Linearly at 12 mW/oC to 200 mW
For T A = -55 to +1000 C (PACKAGE TYPES O,FI
. . . . . . . ..
500mW
For TA =+100 to +125 0 C (PACKAGE TYPES D, FI
Derate linearly
12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE·TEMPERATURE RANGE (All Package Typesl
100mW
OPERATING·TEMPERATURE RANGE (TA):
PACKAGE TYPES 0, F, H
-55 to +125 0 C
PACKAGE TYPE E .
-40 to +85 0 C
STORAGE TEMPERATURE RANGE (Tstgl
-65 to +1500 C
LEAD TEMPERATURE (DURING SOLDERING):
At distance, 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 105 max.
SUPPLY VOLTAGEIV OO )oI5V
?'"
at
10
15
INPUT VOLTAGE {V1NJ-V
Fig. 1 - Tvpical voltage transfer
characteristics.
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25 D C, Input t r , tf = 20 ns,
and CL = 50 pF, RL =200 kQ
1
ALL TYPES
LIMITS
TEST CONDITIONS
CHARACTERISTIC
V DD
tpHL' tpLH
Transition Time,
tTHL, tTLH
Input Capacitance, CI N
MAX.
5
10
15
125
60
45
250
120
90
ns
5
10
15
100
50
40
200
100
80
ns
5
7.5
pF
-
Any Input
NETWORK
LOAD CAPACITANCE (CL)-pF
Fig. 2 - Typical propagation delay time
as a function of load capacitance
II
II
:g
* BY
ALL INPUTS ARE PROTECTED
COS I "lOS PROT EeT ION
}
100
TYP.
VOLTS
Propagation Delay Time,
"150
UNITS
OO
I
DRAIN-TO-SOURCE VOLTAGE {VDS)-V
- - --
V55
92CS ·29114'
Fig. 4 - Typical output low (sink) current
characteristics.
Fig. 3 - Schematic diagram for CD40718 (1 of 4 identical gates),
1(6'8"31~J
3(4,10,11)
A
2 (5,9,121
92C<;-29139
Fig. 5 -
Logic diagram for CD40718 (1 of 4 identical gates).
I
ORAIN- TO- SOURCE VOLTAGE
Fig. 6 - Minimum output low (sink) current
characteristics.
_______________________________________________________________________ 239
CD4071B, CD4072B, CD4075B Types
DRAIN-TO-SOURCE
1\Io51-V
tNY. I ·
Vss
g
DD
---
* BY
ALL INPUTS ARE PROTECTED
COS/MOS PROTECTION
Fig. 8 - Typical output high (source) current
characteristics.
NETWORK
Vss
.
DRAIN-IO-SOURCE VOLTAGE IVosC-V
,
Fig. 7 - Schematic diagram for CD40728 (1 of 2 identical gates).
1(131
Fig. 9 - Logic diagram for CD40728 (1 of 2 identical gates). ,
Fig. 10 - Minimum output high (source) current
characteristics.
8 (5'131:---t
2 (4.121'0-----''+-;
1 (3.111
c*)-~-+--_+..,
v,:
* BY
ALL INPUTS ARE PROTECTED
COS/MOS PROTECTION
g_
NETWORk
Fig. 12 -
vDO
Vss
lIZCM-29115
Fig. 11 - Schemotic diagram for CD40758 (1 of 3 identical gates).
.,..
··
:
,..·
!
i ·
AMBIENT TEaoFERATUR£ (T.,.2S-C
't
I
~
~
610'
I
.
.Ij,~-
~ ~ ;,;(.
CI()4.
~
Fig. 13 - Logic diagram for CD40758 (1 of 3 identical gates).
Typical transition time as a function
of load capacitance.
...~'1l:.
.d-LiL.
~
,
"
;C
h /'
VV"
iL."
·,
...
" , ... , ... , ...
I
CL·~pF
CL-15 pF-
10
10 2
INPUT FREQUENCY If I 1- IIHI
to5
'0'
Fig. 14 - Typical dyanamic power dissipation
as a function of frequency.
240 ____________________________________________________________________
CD40718, CD40728, CD40758 Types
TERMINAL ASSIGNMENTS (TOP VIEW)
INPUTS
o
J-A+B
I.
I.
3
I.
•
13
II
10
K-C+O
C
.. -A+EHC+O
VDD
H
G
.. -G+H
L-E+F
•
14
V DD
13
K-E+F+G+H
Vss
I.
•
CD40718
VOD
G
"II
10
Ie
Vss
I.
13
3
"II
F
E
0
Vss
I.
10
E
4881
DRAIN-lO-SOURCE VOLTAGE (YDSJ-V
Fig.1 - Typical output low 'sink)
current characteristics.
TERMINAL ASSIGNMENT
RECOMMENDED OPERATING CONDITIONS at TA = 25 0 C, Except as Noted.
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges:
CHARACTERISTIC
VDD
(V)
LIMITS
Max.
Min.
Supply·Voltage Range (For TA=Full PackageTemperature Rangel
Data Setup Time, ts
Clock Pulse Width, tw
Clock Input Frequency, tCl
Clock Input Rise or Fall Time, trCl,ttCl
Reset Pulse Width, tw
Data Input Disable Setup Time, ts
3
5
10
15
5
10
15
5
10
15
200
80
60
200
100
80
dc
-
5
10
15
-
5
10
15
5
10
15
120
50
40
180
100
70
UNITS
18
V
-
ns
ORAIN-TO-SOURCE WLTAGE (Vos)-V
-
Fig.2 - Minimum output low 'sink)
current characteristics.
-
-
ns
DRAIN-lO-SOURCE VOLTAGE{VosI-V
-
3
6
8
15
5
5
-
MHz
jJS
ns
-
-
ns
Fig.3 -
Typical output high 'source)
current characteristics.
246 ____________________________________________________________________
CD4076B Types
MAXIMUM RATINGS. Absolute-Maximum Values:
DRA.IN-lO-SOURCE VOLTAGE 1V051-\I
DC SUPPLY-VOLTAGE RANGE. IVODI
-0.5 to +20 V
(Voltages refer~nced to VSS Terminal)
-0.5 to VOO +0.5 V
INPUT VOLTAGE RANGE. All INPUTS
±10mA
DC INPUT CURRENT. ANY ONE INPUT
POWER DISSIPATION PoER PACKAGE IP D ):
. . . . . . . '';
500mW
For T A = --40 to +600 C IPACKAGE TYPE EI
Derate Ltnearly at 12 mWI C to 200 mW
For T A = +60 to +85 Ii, (PACKAGE TYPE EI
.
. . . . . . . '';
500mW
For T A = -55 to +100!; IPACKAGE TYPES D. FI
Derate LlnearJv at 12 mWI C to 200 mW
For TA = +100 to +125 C (PACKAGE TYPES D. FI
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
100mW
FOR T A = FUll PACKAGE-TEMPERATURE RANGE IAII Package Typesl
OPERATING·TEMPERATURE RANGE (TAl:
-55 to +125°C
PACKAGE TYPES O. F. H
-40 to +850 C
PACKAGE TYPE E
-65 to +1500 C
STORAGE TEMPERATURE RANGE IT st I
. .
lEAD TEMPERATURE (DURING SOlO~RINGI:
+265°C
At distance 1116 ± 1/32 inch 11.59 ± 0.79 mml from case for 10 sma •.
Fig.4 - Minimum output high (source)
current characteristics.
l:'I~'~~~,~~,ill~~
's
~~~~~[ ---1----1---'1
g
••••.•••••.•..•••.•...••..••••••••••.•..•••..••.....
"Iov: ;' ..
~
~
~
ij~j iiii :,j:
100 ... '"
: :~;!
.':: ::::
iii: iii: iii; iii:
jJuj"y ii::
::j: jjjj jjJj~i :::: "
f····'." ............................. ·••• ·.m ••••. Hi
RESET
2.0
o
40
60
80
100
LOAD CAPACITANCE ICL.)- pF
120
140
Fig.6 - Typical propagation delay time
OUTPUT
liS.
load capacitance {clock to
OJ.
(a)
OUTPUT " I
DISABLE {
N 2
CHAR.
'PHZ
I PlZ
I PZL
t PZH
~
AT Q
AT 0 ~
Voo
Vss
Vss
Voo
Vss
Voo
Voo
Vss
92CS-29299
(b)
Fig.5 - Functional waveforms for CD4076B.
Truth Table
Datalnpu,
Disable
Reset
I
0
0
0
0
0
0
0
LOAD CAPACITANCE ICLI-pF
Fig.7 -
Typical transition time vs.
load capacitance.
Data
Nllet
Stall
Output
a
Gl
G2
a
x
X
0
0
•x
X
x
x
1
X
X
x
1
x
a
a
a
0
0
I
1
0
0
0
0
X
X
X
x
x
x
a
a
CI~k
J""
-.r
J""
-.r
1
'-
NC
NC
NC
RESET 15>l--f::,_-----I~~=
NC
When lither Output Disable M or N IS high, the outputs are
disabled (high Impedance state), however sequential operation
01 the Ilrp·flops IS nOI affected.
t '" High Level
0:: low level
X
~
Don', Care
NC = No Change
*ALL INPUTS PROTECTED BY
COSINOS PROTECTION NETWORK
NC
9ZCS-Z4886RZ
Fig.8 - CD40768 logic diagram_
_____________________________________________________________________ 247
CD4076B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at T A =25°C. Input tr.tf = 20 nt.
Cl = 50 pF. Rl = 200 kn (Unless otherwise notedl
CHARACTERISTIC
Propagation Delay Time:
Clock to Q Output. tpHL. tpLH
Reset.
TEST CONDITIONS
LIMITS
VDD
V
Min. Typ. Max.
300 600
5
125 250
10
15
90 180
5
230 460
tpHL
3·State Output 1 or 0 to High
Impedance, tpHZ, tplZ
Rl=lkn
3·State High Impedance to 1
or 0 Output, tpZH' tpZl
Rl=lkn
Transition Time,
tTHL· tTLH
Maximum Clock Input F",qllt,ncy. tCl
0
-
Minimum Clock Pulse Width, tw
Maximum Clock Input Rise
or Fall Time,
trel, ttel
Minimum Reset Pulse With, tw
Minimum Data Setup Time, ts
Minimum Data Input Disable
Setup Time, ts
Inpu! Capacitance, CIN
VDO
.
INPUTS
Any Input
10
15
5
10
15
5
10
15
5
10
15
.-
100
75
150
75
60
150
75
60
100
50
40
3
6
8
5
10
15
15
5
5
-
5
10
15
5
10
15
5
' 10
15
-
-
..
60
25
20
100
40
30
90
50
35
5
..
-
...
..
..
..
..
-
200
150
300
150
120
300
150
120
ns
200
100
80
6 --12
16
100 200
50 100
40
80
5
10
15
5
10
15
UNITS
ns
MHz
0-
ns
-
-
lAS
-
120
50
40
200
80
60
180
100
70
7.5
ns
ns
ns
pF
r----'~-,
V~NPU(JS
VDO ::~~.E INPUTS
V55
o~
Vss
SEQUENTIALLY,
TO BOTH YOD AND Yss'
CONNECT AU. UNUSED
IfI'UI'l TO [ITNEA
Voo"'Vss'
V55
Fig. 11 - OuiesCflnt device current test circuit.
V55
QCS-Z"'4Utl
Fig. 12 -Inputvo/~ Intcircuit.
Fig. 13 - Input current test circuit.
248 _________________________________________________________________
CD4076B Types
STATIC ELECTRICAL CHARACTERISTICS
,.
LIMITS AT INDICATED TEMPERATURES (OCI
Value. at -55, +25, +125 Apply to D,:F ,H Packages
Value. at -40, +25, +85 Apply to E Package
UNITS
+25
VDD
+125
Min,
Typ.
+85
Max.
(VI -55 -40
5
5
150
150
5
5
0.04
0.04
10
10
10
10
300
300
IJA
15
20
20
600
600
0.04
20
0.08
100
20
100
100
3000 3000
-
I
MPERATUREITA)-Z5·C
LOAD CAPACITANCE (eLl-liOpF
CONDITIONS
CHARACTER·
ISTIC
Quiescent Device
Current,
100 Max.
Output Low
(Sinkl Current
IOLMin.
Output High
(Sourcel
Current,
IOH Min.
Output Voltage:
Low·Le~el,
VOL Max.
Output Voltage:
High.Level,
VOH Min.
Input Low
Voltage,
VIL Max.
Input High
Voltage,
VIH Min.
Input Current
liN Max.
Vo
(VI
-
VIN
(VI
-
0,5
0,10
0,15
0,20
0.4
0.5
1.5
4.6
2.5
9.5
13.5
0,5
0,10
0,15
0,5
0,5
0,10
0,15
10
15
5
5
10
15
-
0,5
5
0,10
0,15
0,5
0,10
0,15
10
15
5
10
15
0.05
0.05
0.05
4.95
9.95
14.95
-
1.5
3
4
3.5
7
11
-
-
-
0.5,4.5
-
5
1.5,13.5
0.5,4.5
1,9
-
1.5,13.5
-
5
10
15
5
10
15
-
0,18
18
1,9
-
0.64
0.61
1.5
1.6
4.2
4
-0.64 -0.61
-2
-1.8
-1.6 -1.5
-4
-4.2
to.l
to.l
0.42
1.1
2.8
-0.42
-1.3
-1.1
-2.8
±1
.0.36 0.51
0.9
1.3
2.4
34
-0.36' -0.51
-1.15 -1.6
-0.9 -1.3
-2.4 -3.4
-
10
15
20
Fig.9 - Typical maximum clock Input
frequency VI. supply voltaf/fl.
mA
-
0.05
-
0
0
5
10
15
0.05
0.05
-
V
-
-
-
-
-
1.5
3
4
3.5
7
-
-
11
-
-
-
11Q-5
±0.1
-
5
SUPPLY VOLTAGE fYDDI-V
92C5-2711llll
-
0
4.95
9.95
14.95
o
-
-
-
±1
1
2.6
6.8
-1
-3.2
-2.6
-6.8
V
-
10- 1
.
10
102
!O'
INPUT FREQUENCY (tI-IIHI
92C5-2711011
IJA
Fig. to - Typical dynamic power diuipation
VI. frequency.
3·State Output
Leakage Current
lOUT Max.
0,18
0,18
18
to.4
to.4
t12
t12
-
±10-4 to.4
IJA
Dimensions and pad layout for CD4076BH
Dimensions in PBfBnthBses are In millim,t.rs and are
derived from the basic inch dimensions as indluttld.
Grid graduations are ;n mils "0- 3 inch).
The photographs and dimensions of each COS/MaS
chip represent a chip when it is part of the wefer.
When the wafer is cut into chips, the cleava!JII
angles are 57° instead of 90° with respect to the
face of the chip. Therefore, the isolated chip i.
acrually 7 mils (0. 77 mm) larger in both dimensions•.
__________________________________________________________________ 249
CD4078B Types
Features:
COS/MOS a-Input
NOR/OR Gate
High-Voltage Types (20-Volt Rating)
The RCA·CD4078B NOR/OR Gate provides
the system designer with direct implementa·
tion of the positive·logic 8·input NOR and
OR functions and supplements the existing
family of COS/MOS gates.
The CD4078B types are supplied in 14-lead
dual-in-line ceramic packages (D and F suffixes), 14-lead dual-in-line plastic packages
(E suffix), 14-lead ceramic flat packages (K
suffix), and in chip form (H suffix).
• Medium·Speed Operation:
tpHL, tpLH = 75 ns (typ.) at VDD = 10 V
• Buffered inputs and output
• 5·V, 10·V, and 15-V parametric ratings
• Standardized symmetrical output characteristics
• 100% tested for quiescent current at 20 V
• Maximum input current of lilA at 18V
over full package·temperature range:
100 nA at 18 V and 25 0 C
• Noise margin (over full package-temperature
range):
1 Vat VDD = 5 V
2.5 Vat VDD = 15 V
2 V at VDD = 10 V
Yoo" 14
Vss = 7
nCS-23877fl4
• Meets all requirements of JEDEC Tentative
Standard No. 13A, "Standard Specifications
for Description of 'B' Series CMOS Devices"
FUNCTIONAL DIAGRAM
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPL Y·VOL TAGE RANGE, IV DO)
(Voltages referenced to VSS Terminal)
-0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS
-0.5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT
±10mA
POWER DISSIPATION PER PACKAGE IPD):
For TA = -40 to +60 o C IPACKAGE TYPE E)
.
.......
500mW
For T A = +60 to +85 0 C IPACKAGE TYPE E)
Derate Linearlv at 12 mW/oC to 200 mW
For TA = -55 to +lOOoC IPACKAGE TYPES D,F)
.
...
...
500mW
Derate Linearly at 12 mW/oC to 200 mW
For TA = +100 to +125 0 C IPACKAGE TYPES 0, F)
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE· TEMPERATURE RANGE IAII Package Types)
100mW
OPERATING·TEMPERATURE RANGE ITA):
PACKAGE TYPES 0, F, H
-55 to + 1250 c
-40 to +85 0 C
PACKAGE TYPE E .
STORAGE TEMPERATURE RANGE IT stg )
-65 to +1500 c
LEAD TEMPERATURE lOURING SOLDERING):
At distance-' /16
CRAIN-lO-SOURCE VOLTAGE (Vos)-V
Fig. 2 - Typical output low (sink) current
chatacteristics.
± 1/32 inch (1.59 ± 0.79 mm) from case for las max.
""IBIENT TEMPERATURE
RECOMMENDED
OPERATING CONDITIONS
For maximum reliability, nominal operating
conditions should be selected so that operation
is always within the following ranges:
CHARACTERISTIC
HA)~25·C
GATE-TO-SQURCE VOLTAGE (VGS,-15V
C 4
Min. Max. Units
Supply Voltage Range
(For T A Full Package
Temperature Rangel
3
18
V
92C$-29099
5
10
15
DRAIN-lO-SOURCE VOLTAGE (VOSI-V
Fig.
3 - Minimum output low (sink)
current characteristics.
DYNAMIC ELECTRICAL CHARACTERISTICS
AtTA = 25"C; Input t r , tf=20ns,C L =50pF,R L =200kl/
TEST CONDITIONS
CHARACTERISTIC
V DD
DRAIN-lQ-SOURCE VOLTAGE (vosl-V
ALL TYPES
LIMITS
TYP.
MAX.
VOLTS
Propagation Delay Time,
5
10
15
tpH L, tPLH
5
10
15
Transition Time,
tTHL, tTLH
Input Capacitance, CI N
Any Input
UNITS
--150
75
55
100
50
40
300
150
110
5
7.5
200
100
ns
ns
80
pF
Fig. 4 _ Typical output high (source) current
characteristics,
250 _________________________________________________________________
CD4078B Types
DRAIN-lO-SOURCE VOLTAGE (VOSI-V
STATIC ELECTRICAL CHARACTERISTICS
LIMITS AT INDICATED TEMPERATURES (oC)
Values at -55, +25, +125 Apply to D, F,H Packages
Values at -40, +25, +85 Apply to E Package
CONDITIONS
CHARACTER·
ISTIC
Quiescent Device
Current,
IDD Max.
Output Low
(Sink) Current
IOL Min.
Output High
(Source)
Current,
IOH Min.
Vo
(V)
VIN
(V)
+25
VDD
(V)
-55
-40
+85
+125
Min.
Typ.
Max.
-
0,5
5
0.25
0.25
7.5
7.5
0.25
0,10
0.5
0.5
15
15
0.01
0.5
-
0,15
10
15
-
0.01
-
1
30
30
-
0,20
20
150
150
-
0.01
0.Q2
1
5
0.4
0,5
5
5
0.64
1
5
0.61
0.42
0.36
0.51
1
0.5
0,10
10
1.6
1.5
1.1
0.9
2.6
2.8
-042
2.4
-0.36
1.3
34
-0.51
-1.6
-1.3
-3.4
1.5
0,15
15
4.6
D,S
5
2.5
9.5
13.5
0.5
0,10
0,15
4.2
4
-0.64 -0.61
5
-2
-1.8
-1.3
-1.15
10
15
-1.6
-4.2
-1.5
-4
-1.1
-2.8
-0.9
-24
rnA
-32
D,S
5
0.05
0
0.05
Lew-Level,
VOL Max.
-
0,10
10
0
-
15
5
005
0.05
Output Voltage:
0,15
0,5
0,10
0,15
0.05
0.05
Input Low
Voltage,
VIL Max.
Input High
Voltage,
VIH Min,
Input Current
liN Max.
0.5,4,5
1,9
1.5,13.5
0.5,4,5
1,9
1.5,13.5
-
10
15
4.95
0
5
9.95
14.95
10
15
-
-
1.5
3
4
5
3.5
7
3.5
11
11
-
-
;:10- 5
0,18
18
±0.1
±0.1
7
±1
"'1
V
1.5
5
10
15
10
15
Fig. 5 - Minimum output high (source)
current characteristics.
-2.6
-68
-
High-Level,
VOH Min.
pA
6.8
-I
Output Voltage:
4.95
9.95
14.95
UNITS
3
4
V
-
Fig. 6 - Typical transition. time as a
-
function of load capacitance.
-
zO.l
pA
DETAIL OF INVERTERS
VDO
Fig. 7 - Typical propagation delay time
as a function of load capacitance.
R
Yvss
VDD
VSS
Fig. 8 - Schematic diagram.
20
* ALL
25
INPUT VOLTAGE (VII- V
INPUTS PROTECTED BY
COSIMOS PROTECTION
NETWORK
92CL-29098
Fig.
9 -
Typical voltage transfer characteristics (NOR output).
251
CD4078B Types
.,
"': ~~T
~
Ie
~~
TEMPERATURE
:
~~I03~ :--CC:::6
4
".
:!i~
.,
•
/
/
l-ft.? "';~7z
t7
",,~v.
,t; / /
t
V'
INPUTS
o
fJ·V
Voo
Vss
1.(:"--: /
~
~ 102
!.~~
(lTI""l
':\.~~..),
10"8
6
!
10
.-
,
-
NOTE
MEASURE INPUTS
o ~
p-i-'"
~-
" 102 ,
10'
CONNECT ALL UNUSED
INPUTS TO EITHER
Voo OR VSS'
'55
10'
INPUl FREQUENCY 1111- kHz
Fig. 10 - Typical dynamic power dissipation
as a function of frequency.
SEQUENTIALLY,
TO BOTH VaD AND Vss'
Vss
CL .5O pF
i :Ct{15(F 1-[ B
f
. .
" 10 ,
INPu(J'
VDO
'-----'l' ~
//
'ss
Fig. 11 - Quiescent-device-current test circuit.
Fig. 12 - Input current test circuit.
'DO
.oK
A
INPUTQ'OO
OUTPUTS
I. .
•
(
13
"
"
V(H
(0
~
"'-0-..
v~
~
Ne
•
F
·E
Ne
Vss
CLOCK
TOP VIEW
• J-AtBtCtDtEtFfG+H
NOTE:
Vss
9
VDO
J_
H
~~S;N~~~~OMBINATION
A K-A+BtCtD+EtF+G+H
Ne- NO CONNECTION
9ZCS-2"~93R2
Fig. 13 - Input·voltage test circuit.
Fig. 14 - Dynamic power dissipation test circuit.
TERMINAL ASSIGNMENT
53-81
l~'
Dimensions and pad layout for CD4078BH.
Dimensions in parentheses are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduat;ons'are in mils (10-3 inch).
The photographs and dimensions of eo.. .J COS/MaS
chip represent a chip when it ;s part of the wafer.
When the wafer is cut into chips, the cleavage
angles are 570 instead of 900 with respect to the
face of the chip. Therefore, the ;solated chip is
actually 7 mils (0. 17 mr:n) larger in both dimensions.
252 ________________~--------------------------------------------------
CD4085B Types
COS/MOS Dual 2-Wide
2-lnput AND-OR-INVERT Gate
INHlal:II~,O
81 2
CI 12
3 EI
DI •
High-Voltage Types (20-Volt Rating)
INHlal:~~~
82 6
C2 8
D2 9
Features:
The RCA-CD4085 contains a pair of ANDOR-INVERT gates, each consisting of two
2-input AND gates driving a 3-input NOR
gate. Individual inhibit controls are provided
for both A-O-I gates.
• Medium-speed operation - tpH L = 90 ns;
tpLH = 125 ns (typ.) at 10 V
• Individual inhibit controls
• Standardized symmetrical output characteristics
.100% tested for quiescent current at 20 V
• Maximum input current of 1/lA at 18 V over full packagetemperatu re range; 100 nA at 18 V and 25° C
The CD40856 types are supplied in 14-lead
dual-in-line ceramic packages (0 and F
suffixes), 14-lead dual-in-line plastic packages (E suffix), 14-lead ceramic flat packages
(K suffix), and in chip form (H suffix).
VOO-14
Vss -7
4
E2
E·INHIBIT+AS+CD
LOGIC II HIGH
LOGIC 01 LOW
92eS-23690R2
FUNCTIONAL DIAGRAM
• Noise margin (over full packagetemperature range):
1 Vat VDD= 5 V
2 V at VDD = 10 V
2.5 Vat VDD = 15 V
• 5-V, 10-V, and 15·V parametric ratings
• Meets all requirements of JEDEC Tentative
Standard No. 13A, "Standard Specifications
for Description of '6' Series CMOS Devices"
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VDL TAGE RANGE, (VDDI
(Voltages referenced to VSS Terrnir:'1al)
-0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS
-0.5 to VDD +0.5 V
±10mA
DC INPUT CURRENT, ANY ONE INPUT
POWER DISSIPATION PER PACKAGE (PDI:
0
For T A = -40 to +60 C (PACKAGE TYPE EI
. . . . . . . ..
500 mW
Derate Linearly at 12 mW/oC to 200 mW
For T A = +60 to +85 0 C (PACKAGE TYPE EI
.
For TA = -55 to +1000 C (PACKAGE TYPES D,FI
. . . . . . . ..
500 mW
Derate Linearly at 12 mWjOC to 200 mW
For T A = +100 to +125 0 C (PACKAGE TYPES D, FI
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
100mW
FDR TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Typesl
OPERATING-TEMPERATURE RANGE (TA):
-55
to
+125 0 C
PACKAGE TYPES D, F, H
PACKAGE TYPE E .
-40 to +85 0 C
STORAGE TEMPERATURE RANGE (Tstg )
-65 to +1500 C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max.
INPUT VOLTAGE IYI)-V
Fig. 1 - Typical voltage Bnd current
transfer characteristics.
_ _ MAX
>
!
___ MIN
12.15
?:
!
>
10
1.!!
2.'
7.'
10
INPUT VOLTAGE IVII-V
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges:
LIMITS
CHARACTERISTIC
Min.
Supply·Voltage Range (For T A=Full Package·
Temperature Range)
AI
al
EI- INHI+AIBI+CIDI
Ez-iNH2+A2BZ+CZD2
A.
a.
Vss
3
I.
••
..
I.
""
• •
4
S
10
a
I
Max.
I
18
Fig. 2 -
Min. and max.
"UCS-llUI4
voltage transfer
characteristics,
UNITS
10
~
AMBLENT TEMPERATuRE ITA)· l'S"
V
Yeo
DI
CI
INHIBIT 2
INHIBIT I
D2
c.
lOP VIEW
92CS-UIURI
10°
10'
10 '
FREQUENCY IIl-lH'
'0'
'0'
Terminal Assignment
Fig. 3' ~ Typical power dissipation vs. frequency.
_________________________________________________________________ 253
CD4085B Types
STATIC ELECTRICAL CHARACTERISTICS
CHAAAC·
TERISTIC
Quiescent
Device
Current
100 Max.
Output Low
(Sink)
Current,
'-OL Min.
Output High
(Source)
Current,
IOH Min.
CONDITIONS
Vo
VIN VDD
(V)
(V)
(V)
-
LIMITS AT INDICATED TEMPERATURES (OC)
Values at -55,+25,+125 Apply to D, F,H Pkgs.
Values at -40,+25,+85 Apply to E Pkgs.
UNITS
+25
Typ. Max.
-55 -40 +85
+125 Min.
-
0,5
0,10
0,15
0,20
5
10
15
20
1
2
4
20
0.4
0.5
1.5
4.6
2.5
9.5
13.5
0,5
0,10
0,15
0,5
0,5
0,10
0,15
5
10
15
5
5
10
15
0.64
1.6
4.2
-0.64
-2
-1.6
-4.2
-
0,5
0,10
0,15
5
10
15
0.05
0.05
0.05
-
0,5
0,10
0,15
5
10
15
Input Low
Voltage,
VIL Max.
0.5,4.5
1,9
1.5,13.5
-
.Input High
Voltag~,
VIH Min.
Input
Current,
liN Max.
0.5,4.5
1,9
1.5,13.5
-
Output Volt·
age:
Low· Level,
VOL Max.
Output Volt·
age:
High· Level,
VOH Min.
1
2
4
20
1
2.6
6.8
-1
-3.2
-2.6
-6.8
i---=-
-
0
0
0
0.05
0.05
0.05
4.95
9.95
14.95
4.95
9.95
14.95
5
10
15
-
5
10
15
1.5
3
4
-
-
1.5
3
4
-
5
10
15
3.5
7
11
3.5
7
11
0,18
18
-
±0.1
30
60
120
600
30
60
120
600
-
0.02
0.02
0.02
0.04
-
1
2
4
20
0.61
0.42 0.36 0.51
1.5
1.1
0.9
1.3
4
2.8
2.4
3.4
-0.61 -0.42 -0.36 -0.51
-1.8 -1.3 -1.15 -1.6
-1.5 -1.1 -0.9 -1.3
-4
-2.8 -2.4 -3.4
±0.1
±1
±1
-
-
-
p.A
rnA
V
V
-
-
-
-
±10-5 ±0.1
p.A
A_lENT TEMPE.....TURE(TA'·Z5-C
I
LOAD CAPACITANCE ((1)-8Opf
1
1
'200
t
.~
~
Z ••
7.'
I.
12.!!
,.
17.5
,.
zo
III
SUPPLY YOLTAGEC'IDD1-V
LOAD CAPACiTANCE (Ct.)-,F
Fig. 4 - Typical data high-to-Iow level propagation
delay time VI, load capacitance.
LOAD CAPACITANCE
Ict. )-"
Fig. 5 - Typical data low-ta-high level propagation
delay time vs. load capacitance.
Fig. 6 - Typical data propagation delay time vs.
supply va/tage.
254 _______________________________________________________________________
CD4085B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 250 C; Input t r ,
CL ="50 pF, RL = 200
CONDITIONS
CHARACTERISTIC
Transition Time,
Input Capacitance,
UNITS
Typ.
Max.
450
5
225
10
90
180
15
65
130
5
310
620
10
125
250
ns
I
tpLH
Propagation Delay Time (Inhibit):
High·to·Low Level,
tpHL
Low-to-High Level,
LIMITS
VDD
V
Propagation Delay Time (Data):
High-to-Low Level,
tpHL
Low·to·High Level,
tt = 20 ns,
Kn
tpLH
tTHL' tTLH
CIN
15
90
180
5
150
300
10
60
120
15
40
80
5
250
500
10
100
200
15
70
140
5
100
200
10
50
100
15
40
80
5
7.5
Any Input
ns
DRAIN-lO-SOURCE VOLTAGE (Vos)-V
Fig. 7 - Typical output low (sink)
current characteristics.
ns
ns
ns
pF
DRAIN-lO-SOURCE VOLTAGE
Fig. 8 - Minimum output low (sink J
current characteristics.
DRAIN-lO-SOURCE VOLTAGE IVosl-V
DRAIN-lO-SOURCE VOLTAGE (Vosl-V
Fig. 10 - Typical output high (sourcel
current characteristics.
Fig. 11 - Minimum output high (source)
lIeS-MRI
Fig. 9 - Typical transition time vs. load
capacitance.
v,,
current characteristics.
INPUTS
o
INPUTQVOOOUTPUTS
V,H
'--"
4]
o
_
\IlL
'=
"ss
NOTE;
TEST ANY C0t.4BINATION
OF INPUTS
<;t2:C$-2144IAI
Fig. 12 - Quiescent device current test circuit.
Fig. 13 - Input voltage test circuit.
Fig. 14 - Input current test circuit.
____________________________________________________________________ 255
CD4085B Types
INHIBIT I
~~---------------------
VDO
AI
{jl!}"--+.----t-
81 2
*
CIQI!)-'-.......----t--'
DIQI~-----4--'
A2 ,
B2 6 •
. C2
(!.r=-......---+..J
VDO
D2 9 ·
"
,_ .,_,__..p;.::-f
rl
.
INHIBIT 2
STAND•• D COSIMOS
NETWORK
SS
Fig. 15 - CD4085 schematic diagram.
o
10
20
30
40
49
Dimensions in parentheses are in millimeters and are
56
1.422)
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10- 3 inch).
The photographs and dimensions of each
COS/MOS chip represent a chip when it
;s part of the wafer. When the wafer is
cut into chips, the cleavage angles are
57° instead of 90° with respect to the
face of the chip. Therefore, the isolated
chip is actually 7 mils (0. 17 mm) larger
in both dimensions.
92C5-32204
Dimensions and Pad Layout for CD4085BH.
256 __________________________________________________________________
CD4086B Types
COS/MOS Expandable 4-Wide
2-lnput AND-OR-INVERT Gate
High-Voltage Types (20-Volt Rating)
The RCA-CD40B6B contains one4-wide
2-input AND-OR-INVERT gate with an
INHIBIT!EXP input and an ENABLE!
EXP input. For a 4-wide A-O-I function
INHIBIT!EXP is tied to VSS and ENABLE!
EXP to VDD' See Fig.l0 and its associated
explanation for applications where a capability greater than 4-wide is required.
The CD4086B is supplied in 14-lead dual-inline ceramic packages (0 and F suffixes).
14-lead dual-in-line plastic packages (Esuffix). 14-leadceramic flat packages (K suffix),
and in chip form (H suffix).
Features:
•
•
•
•
•
•
•
•
Medium-speed operation - tPHL = 90 ns;
tpLH = 140 ns (typ_) at 10 V
INHIBIT and ENABLE inputs
Buffered outputs
100% tested for quiescent current at 20 V
Maximum input leakage current of 18 V
over full package-temperature range;
100 nA at 18 V and 250 C
Noise margin (over full package
termperature range):
1 VatVDD=5 V
2 V at VDD = 10 V
2,5 V at VDD = 15 V
Standardized, symmetrical output
characteristics
5-V, 1Q..V, and 15-V parametric ratings
lOGIC ,_ HIGH
LOGIC a_L.OW
\laD' 14
-"-==='--'
J .INH
Vss .7
NC·4
+ ENABL.E +AB+CO+EF +GH
FUNCTIONAL DIAGRAM
Voo
A
_ _8
"13
"
J:oINH+ENABlE+
AB+CD+EF+GH
Ne
E
• Meets all requirements of JEDEC Tentative
Standard No, 13A, "Standard Specifications
for Description of 'B' Series CMOS Devices"
0
12
•
S
"
ENABLE/EXP
10
INHIBIT/EXP
9
H
92C5· n869RI
Top View
TERMINAL ASSIGNMENT
MAXIMUM RATINGS,Absolute-Maximum Values:
ANBIEItT n.MPERATURE 1T.,1"2$"C
DC SUPPLY-VOLTAGE RANGE, NOD)
. ~.5to+20V
(Voltages referenced to VSS Terminal)
~.5 to VOD +0.5 V
INPUT VOLTAGE RANGE, ALL INPUTS
±10mA
DC INPUt CURRENT, ANY ONE INPUT
POWER DISSIPATION PER PACKAGE IPD):
• • • . • • • .•
500mW
For TA a -40 to +60o C IPACKAGE TYPE E)
Derate Linearly at 12 mWloC to 200 mW
For T A = +60 to +85 0C IPACKAGE TYPE E)
• •
. • • • • • • .•
500mW
For TA = -55 to +100?C IPACKAGE TYPES D,F)
Derate Linearly at 12 mWloC to 200 mW
ForTA = +100 to +1250C IPACKAGE TYPES 0, F)
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
l00mW
FOR T A = FULL PACKAGE-TEMPERATURE RANGE IAII Package Types)
OPERATING-TEMPERATURE RANGE ITA):
-55 to +125 0C
PACKAGE TYPES 0, F, H
-40 to+850C
PACKAGE TYPE E •
-65 to +1500C
STORAGE TEMPERATURE RANGE ITstg)
LEAD TEMPERATURE lOURING SOLDERING):
At distance 1/16 ± 1132 inch 11.59 ±0.79 mm) from case for lOs max.
i
~
~
"
,
!•
•
SUPPLY VOLTAGE
tVgoI"15
v
!ac'f,w,"'
'.Y,1j:j
1
.~,. "
I
!!
"'m:'
I
5V
v,.
III
..
5
••
,%D
~
.i
ft
,
IS
INPUT VOlTAGE. 1V.r.)-V
1ICI·llln
. Fig. ,
-I Typical ViJjtagtl and current transfer
characteristics,
"
_ _ _ MIN.
_ _ MAX.
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges:
LIMITS
CHARACTERISTIC
Supply-Voltage Range (ForTA = Full PackageTemperature Range)
MIN.
MAX,
3
1B
UNITS
INPUT VOLTAGE tV.r.I-V
V
_.......
Fig. 2 - Minimum and maximum voltage transfer
characteristics.
257
CD4086B Types
STATIC ELECTRICAL CHARACTERISTICS
CHARAC·
TERISTIC
CONDITIONS
Vo
V,N VDD
(V)
(V)
(V)
LIMITS AT INDICATED TEMPERATURES (OC)
Values at -55,+25,+125 Apply to D,F,H Pkgs.
Values at -40,+25,-165 Apply to E Pkgs.
UNITS
+25
Typ. Max.
-55 -40 -165
+125 Min.
Quiescent
Oevice
Current
IDO Max.
Output Low
(Sink)
Current,
IOl Min.
Output High
(Source)
Current,
IOH Min.
-
0,5
0,10
0,15
0,20
5
10
15
20
1
2
4
20
0.4
0.5
1.5
4.6
2.5
9.5
13.5
0,5
0,10
0,15
0,5
0,5
0,10
0,15
5
10
15
5
5
10
15
0.64
1.6
4.2
-0.64
-2
-1.6
-4.2
Output Volt·
age:
Low·Level,
VOL Max.
-
0,5
0,10
0,15
5
10
15
0.05
0.05
0.05
-
-
0,5
0,10
0,15
5
10
15
4.95
9.95
14.95
-
5
10
15
1.5
3
4
-
5
10
15
3.5
7
11
3.5
7
11
Output Volt·
age:
High· Level,
VOH Min.
30
60
120
600
1
2
4
20
30
60
120
600
-
0.02
0.02
0.02
0.04
1
2
4
20
1
2.6
6.8
-1
-3.2
-2.6
-6.8
-
r-=--
-
0
0
0
0.05
0.05
0.05
4.95
9.95
14.95
5
10
15
-
fJ.A
DRAIN-lO-SOURCE VOLTAGE (Yosl-V
-
Input Low
Voltage,
VIL Max.
0.5,4.5
1,9
1.5,13.5
Input High
Voltage,
V,H Min.
Input
Current,
"N Max.
0.5,4.5
1,9
1.5,13.5
-
-
0,18
-
18
iO.l
0.42 0.36 0.51
0.61
1.5
1.1
0.9
1.3
3.4
4
2.8
2.4
-0.61 -0.42 -0.36 -0.51
-1.8 -1.3 -1.15 -1.6
-1.5 -1.1 -0.9 -1.3
-4
-2.8 -2.4 -3.4
-
±1
±0.1
±1
-
Fig. 3 - Typical output low (sink)
'curren t characteristics.
mA
-
V
-
DRAIN-TO- SOURCE VOLTAGE
-
-
-
1.5
3
4
-
-
-
Fig. 4 -
Minimum output low (sink)
, current characteristics.
DRAIN-lO-SOURCE VOL.TAGE II/OSI-V
I
V
-
±10-5 ±0.1
fJ.A
Fig.5 -
Typical output high (source)
current characteristics.
DRAIN-lO-SOURCE VOLTAGE {VOS1-V
10
AMBIENT TEMPERATURE eTA J-
10°
nee
'0'
10'
10 2
FREQUENCY It 1- .Hz
'0'
Fig.S - Minimum output high (source)
Fig.S - Typical transition time VI. load capacitance.
I
258
Fig.7 - . Typical power dissipation
VB.
frequency.
current characteristics.
CD4086B Types
VDD
L.OAD CAPACITANCE 1Cll-pF
Fig. 11 -
Typical DA TA or ENABLE high-to·low
level propagation delay time vs. load
capacitance.
A".'~~T
! li'1'
, '1:,,:
.~.-c
TEMPERATURE
,,:' ' 1,'',!i!,
,,
:1::"
Vss
':".".1:' V:"~: '1:1:
":: ' ' I:' ~;; '::i ::': :
,""
"
I,'::':>
I....
'.;,,11/'.'.:;
H 9
*
LOAD CAPACITANCE/ell-pF
Fig. 12 -
ENABLE/EXP QlII!>-*"-----'VS"'S'-_ _ _ _ _ _ _--'
lNHIBIT/EXP(!!1~*"------------------..J
Typical DATA or ENABLE low·to·high
level propagation delay time vs. load
capacitance.
Vss
Fig. 9 - CD4086B schematic diagram.
AMBIENT TEMPERATURE tTAI-25·C
LOAD CAPACITANCE {CLI-50pF
INHIBIT/EXP Z , - - - - - - - - - ,
.,
AI
CI
IPLH
01
~
~
EI
7>0
.00
IPHL
FI
200
GI
HI
VD
ENAtlLEIEXP I
'"L_ _ _=;;:;;;;;""===~:;:~~~~:;:;;;:;:;:_--'
SUPPLY VOLTAGE tVoOI-V
JZ-AI Bltel 01 +EI FI +GI HI +A2 82.+C2 02+- E2 F2 +G2 HZ
Fig. 13 - Typical DATA or ENABLE propagation
delay time vs. supply Voltage.
Fig. 10 -
Two
CD40868~s
connected as an 8-wide 2-input A-O-I gate.
Fig. 10 above shows two CD4086's utilized
to obtain an 8-wide 2-input A.Q-I function.
The output (Jl) of one CD4086 is fed directly to the ENABLE/EXP2 line of the
second CD4086. In a similar fashion, any
NAND gate output can be fed directly into
the ENABLE/EXP input to obtain a 5-wide
A.Q-I function. In addition, any AND gate
output can be fed directly into the INHIBIT/EXP input with the same result.
____________________________________________________________________ 259
CD4086B Types
DYNAMIC ELECTRICAL CHARACTERISTICS
At TA = 25"C; Input t,., tf= 20ns, CL =50pF, RL = 200 kn
LIMITS
CONDITIONS
CHARACTERISTIC
V DD
(VI
TEST CI RCUITS
UNITS
TYP.
5
225
450
10
90
180
15
60
120
5
Low·to·High Level, tpLH
10
620
250
15
310
125
.90
5
150
300
10
15
60
40
120
Low·to·High Level,
tpLH(lNH)
Transition Time,
tTHL' tTLH
Input Capacitance CIN
o
Vss
Propagation Delay Time
(Data):
High·to·Low Level, tpHL
Propagation Delay Time
(Inhibit): High·to·Low
Level, tpHL(lNH)
I~PUTS
MAX.
ns
ns
180
Fig, 14 - Quiescent device current.
lis
80
5
250
500
10
100
200
15
70
140
5
100
200
10
50
100
15
40
80
Any Input
5
7.5
INPUTQVDOOUTPUTS
ns
VIH
ns
.
"'-V~L
~
:t
NOTE:
TEST ANY ONE INPUT,
WITH OTHER INPUTS AT
Yeo DRYSS'
Vss
pF
Fig. 15 - Input voltage.
V~NPUO'
... ~':.':,!:c': '
Vss
TO BOTH Yoo AND Yss'
CONNECT ALL UNUSED
INPlITS 10 EITHER
Yeo OR Yss '
Vss
nCS-Z140Z
Fig. 16 - Input leakage current.
Dimensions in Parentheses are in millimeters and are
der;"ed from the basic inch dimensions as indicated.
Grid graduations Bre in mils "q-3 inchJ.
The photographs and dimensions of each COS/MOS
chip represent a chip when it is part of the wafer.
When the wafer is cut into chips, the cleavage
angles are 57° instead of 90° with respect to the
face of the chip. Therefore, the isolated chip ;s
actuallv 7 mils (0. '7 rom) larger in both dimensions.
Dimensions and Pad Layout for the CD4086BH
260 ____________________________________________________________________
CD4089B Types
COS/MOS
Binary Rate Multiplier
High-Voltage Types (20-Volt Rating)
The RCA-CD4089B is a low-power 4-bit digital
rate multiplier ttiat provides an output pulse
rate that is the clock-input·pulse rate multiplied by 1/16· times the binary input. For
example. when the binary input number is
13. there will be 13 output pulses for every
16 input pulses. This device may be used in
conjunction with an upl down counter and
control logic used to perform arithmetic
operations (adds, subtract. divide, raise to a
power), solve algebraic and differential equations. generate natural logarithms and trigometric functions. AID and D/A conversions.
and frequency division.
For words of more than 4 bits. CD4089B
devices may be cascaded in two different
modes: an Add mode and a Multiply mode
(see Figs.14 and 15). In the Add mode some of
the gaps left by the more significant unit at
the count of 15 are filled in by the less
significant units. For example. when two
units are cascaded in the Add mode and
programmed to 11 and 13. respectively. the
more significant unit will have 11 output
pulses for every 16 input pulses and the
other unit will have 13 output pulses for every
256 input pulses for a total of
11 13
189
-+-
=--
16 256 256
In the Multiply mode the fraction programmed into the first rate multiplier is
multiplied by the fraction programmed into
the second multiplier. Thus the output rate
11
13 143
will be
-x-
--
16
256
16
Features:
•
•
•
•
•
•
Cascadable in mUltiples of 4-bits
Set to "15" input and "15" detect output
100% tested for quiescent current at 20 V
S-V, 10-V, and 15-V parametric ratings
Standardized. symmetrical output characteristics
Maximum input current of 1 /lA at 18 Vover
full package-temperature range; 100 nA at
18 Vand 25°C
• Noise margin (full package-temperature
range) =
1 VatVDD=5V
2 Vat VDD = 10 V
2.5 V at VDD = 15 V
BINARY RATE
'100*16
"ss'S
9ZCS-Z50001RI
FUNCTIONAL DIAGRAM
• Meets all requirements of JEDEC
Tentative Standard No_ 13A, "Standard
Specifications for Description of 'B'
Series CMOS Devices"
Applications:
,~
Numerical control
• Instrumentation
• Digital filtering
• Frequency synthesis
,
The CD4089B has an internal synchronous
4-bit counter which. together with one of the
four binary input bits. produces pulse trains
as shown in Fig. 2.
If more than one binary input bit is high. the
resulting pulse train is a combination of the
separate pulse trains as shown in Fig. 2.
DR,4.IN-TO-SOURCE VOLTAGE(VoS)-V
Fig. 1 - Typical output low (sink) current
characteristics.
AMSIENT TEMPE~~:~~~;ri'ifi;f~
III III
~"
<
The CD4089B types are supplied in 16-lead
ceramic dual-in-line packages (D and F suffixes), 16-lead dual-in-line plastic packages
(E suffix), IS-lead ceramic flat packages (K
suffix), and in chip form (H suffix).
~ 12.~
a
10"
+
:
p.
........
• + •
~
,.
Wi: t ,
~:!":t
:+!
+ GATE-TO-SOURCE VOLTAGE
:;
:j:
.:ilt::·
.. 10V
t:
IVGSI'I~V
I ••
..
~
10
I~
ORAIN-TO-SOURCE VOLTAGE (Vosl-V
Fig. 2 - Minimum output low (sink) currenr
characteristics.
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE. (V DOl
. -0.5 to +20 V
(Voltages refer~nced to VSS Terminal)
-0.5 to Vee +0.5 V
INPUT VOLTAGE RANGE. ALL INPUTS
±IOmA
DC INPUT CURRENT. ANY ONE INPUT
POWER DISSIPATION P.,ER PACKAGE (POl:
. . . . . . . ..
500mW
For T A ~ -40 to +60. C (PACKAGE TYPE EI
Derate Linearly at 12 mW/oC to 200 mW
For T A = +60 to +85 C (PACKAGE TYPE EI. .
.
.
.
.
.
.
.
.
.
500mW
For A = -55 to +100·of (PACKAGE. TYPES D. FI
Derate Linearly at 12 mW/oC to 200 mW
For TA = +100 to +125 C (PACKAGE TYPES D. FI
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
100mW
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Typesl
OPERATING-TEMPERATURE RANGE (TAl:
-55 to +125 0 C
PACKAGE TYPES D. F. H
-40 to +85 0 C
PACKAGE TYPE E
-65 to +150 oC
STORAGE TEMPERATURE RANGE (T .. I . .
LEAD TEMPERATURE (DURING SOLD~RINGI:
. +265°c
At distance 1/16 ± 1132 inch (1.59 ±0.79 mml from case for 105 max.
ORAIN-lO-SOURCE VOLlAGE 1Vosl-V
T
Fig. 3 - Typical output high (source) current
characteristics.
____________________________________________________________________ 261
CD4089B Types
RECOMMENDED OPERATING CONDITIONS at T A = 25°C, Except as Noted. For maxiinum
reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
CHARACTERISTIC
VDD
(V)
liMITS
Min.
Max.
Supply·Voltage Range (For TA = Full Package·
Temperature Range)
Set or Clear Pulse Width,
Clock Pulse Width,
Clock Frequency,
Clock Rise or Fall Time,
3
tw
5
10
15
160
90
60
tw
5
10
15
330
170
.100
fCl
5
10
15
trCl or tfCL
de
5,
10,15
-
Inhibit In Setup Time,
tsu
5
10
15
100
40
20
Inhibit In Removal Time,
tREM
5
10
15
240
130
110
Set Removal Time,
tREM
5
10
15
150
80
50
tREM
5
10
15
60
40
30
Clear Removal Time,
18
1.2
2.5
3.5
15
-
DRAIN-lO-SOURCE VOLTAGE (VosJ-V
I~~~I.E.N.~
.' .'...~'.".~' ~"..".
:'';OLT~G
UNITS
V
J
ns
!
ns
Fig. 5 - Minimum output high (source) current
characteristics.
MHz
IlS
ns
ns
LOAD CAPACITANCE (ClJ-pF
-
-
-
ns
Fig. 6. -
,Itl-"".
Typical propagation delay time as a
function of load capacitance (Clock
or Strobe to Out).
ns
LOAD CAPACITANCE ICL)- pF
Fig. 7 - Typical transition time BS B function
of load capacitance.
'0: AMB"NT TEMP'"iiil ITA '.~
·
'H
j
!". Ir!:I
.P •
i
I
f
Ii J ~
_.
'I"~
It I-co:
-tJ~
l}~~
. '.It
I,~
,.·• ... , . ,
i t Fe
/
103
.p {
H-
,
>-
~
*ALL INPUTS ARE PROTEcn:o
BY COS/MOS PROTECTION
NETWORK
4
ttCS·15OO7'AS
i
II
'10
<4
'102
CL·~,f
CL.~;PF
. ..
INPUT FREQUENCY It'N.-~HI
Fig.
Fig. 4 - Logic diagram.
---
I 1111 I
I
I 1111
.. "'052
""01
'1()5
'2CS-,u15!:1
8 - Typical dynamic power dissipation as a
function of input frequency_
Vss
262 __________________________________________________________________
___
CD4089B Types
VDD
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C;
Input t r • tf = 20 ns. CL = 50 pF. RL = 200 kH
TEST
CONDITIONS
CHARACTERISTIC
UNITS
r--
Propagation Delay Time. tpHL' tpLH
Clock to Out
LIMITS
VDD
V
Min.
Typ.
Max.
5
10
15
-
110
-
55
45
220
110
90
-
150
75
60
300
150
120
360
160
110
720
320
220
ns
250
100
75
500
200
150
ns
380
175
130
760
350
260
ns
300
125
90
600
250
180
ns
90
45
35
180
90
70
ns
160
75
55
320
150
110
330
150
110
660
300
220
200
100
80
-
Clock or Strobe to Out
5
10
15
Clock to Inhibit Out
High Level to Low Level
5.
10
15
-
Low Level to High Level
5
10
15
5
10
15
Clear to Out
5
10
15
C!ock to "9" or "15" Out
-
-
-
-
-
-
-
Inhibit In to Inhibit Out
5
10
15
-
Set to Out
5
10
15
Transition Time.
5
10
15
-
100
50
40
5
10
15
1.2
2.5
3.5
2.4
5
7
tTHL' tTLH
Maximum Clock Frequency, tCL
-
-
-
Minimum Clock Pulse Width, tw
5
10
15
-
Clock Rise or Fall Time,
trCL' ttCL
5
10
15
-
Minimum Set or Clear Pulse Width, tw
5
10
15
-
Minimum Inhibit-In Setup Time,
5
10
15
Minimum Inhibit In
Removal Time.
tsu
tREM
5
10
15
-
-
-
-
Fig. 9 - Dynamic power dissipation test circuit.
VDD
5
10
15
Cascade to Out
92CS-291!S1
ns
Fig. 10 - Quiescent device current test circuit.
DD
~
~:~~~N~'~~~~~S
--
TO 80TH Veo ANO Vss'
CONNECT ALL UNUSED
INPUTS TO EITHER
YDO ORYSS'
Vss
ns
Fig. 11 - Input-current test circuit.
ns
INPUTQVOO
OUTPUTS
V,H
15
15
15
!lS
80
45
30
160
90
60
ns
50
20
10
100
40
20
ns
120
65
55
240
130
110
ns
~
'--
MHz
ns
-
1NPUOS
V
NOTE
VDO
Vss
330
170
100
165
85
50
INPUTS , - - - ' - - ,
o
Vss
l
Y~L
Vss
NOTE:
TEST ANY COMBINATION
OF INPUTS
Fig. 12 - Input-voltage test circuit.
",S"our
I.
0
SETTo"15"
our
OUT
INHIBIT OUT
(CARRY)
vss
16
voo
15
14
4
13
CLEAR
5
12
7
8
10
CASCADE
INHIBIT IN
(CARRY)
STROBE
"
CLOCK
92CS-2~OO~RI
.
TOPVtEW
TERMINAL ASSIGNMENT
263
CD4089B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA =25°C (cont'd)
Input t r , If = 20 ns, CL =50 pF, RL = 200 kn
TEST
~ONDITIO~
LIMITS
VDD
V
Min. Typ.
CHARACTERISTIC
Minimum Set Removal Time,
5
10
15
Minimum Clear Removal Time, tREM
Input Capacitance,
CIN
-
5
10
15
tREM
-
Any Input
UNITS
Max.
75
40
25
150
80
50
ns
30
20
15
60
40
30
ns
5
7.5
pF
STATIC ELECTRICAL CHARACTERISTICS
LIMITS AT INDICATED TEMPERATURES (oCI
CHARAC·
CONDITIONS
Values at -55, +25, +125 Apply to D,F,H Packages
TERISTIC
Values at --40, +25, +85 Apply to E Package
+25
Vo
VIN VDD
(VI
(Vi (VI -55 -40
+85 +125 Min. Typ, Max.
Quiescent
Device
Current,
100 Max.
-
0,5
5
150
150
10
300
300
-
0.04
10
5
10
5
0,10
0.04
5
10
0,15
15
20
20
600
600
-
0.04
20
0,20
20
100
100
3000
3060
-
0.08
100
a,s
5
0.64
0.61
0.42
0.36
0.51
1
0,10
10
1.6
1.5
1.1
0.9
1.3
2.6
-
0,15
15
4.2
4
2.8
2.4
3.4
6.8
-
a,s
a,s
5
-0.42 -0.36 -0.51
-1.3 -1.15 -1.6
-1
2.5
-3.2
-
0.4
Output Low
(Sink) Current 0.5
IOL Min.
1.5
Output High
(Source)
Current,
IOH Min.
Output Voltage:
.Low·Level,
VOL Max.
Output
Voltage:
High·Level,
VOH Min.
Input Low
Voltage
VIL Max.
Input High
Voltage,
VIHMin.
Input Current
liN Max.
4.6
-0.64 -0.61
5
-2
-1.8
9.5
0,10
10
-1.6
-1.5
-1.1
-0.9
-1.3
-2.6
-
0,15
15
-4.2
-4
-2.8
-2.4
-3.4
-6.8
-
_.
a,s
5
0.05
-
0,10
10
0.05
-
-
0,15
15
0.05
4.95
5
10
9.95
9.95
10
14.95
0,5
5
-
0,10
-
0,15
15.
14.95
0.5,4.5
-
1.5
1,9
-
5
10
1.5,13.5
-
15
4
0.5,4.5
-
5
3.5
1,9
-
10
7
7
15
11
11
1.5,13.5
-
0,18
18
-
3
±0.1
±0.1
3.5
±1
±1
-
/loA
mJ!
a 0.05
a 0.05
a 0.05 V
4.95
,
N
I
T
S
-
13.5
-
u
15
-
-
1.5
-
-
3
4
V
-
-
±10- 5 ±0.1 /loA
264 ____________________________________________________________________
CD4089B Types
TRUTH TABLE
NOST SIGNIFICANT
INPUTS
C B A CLK INH
IN
o
o
DRM
c
10
0
9
M~G-H
L~ E""""="F
F
E
V"
Vss
'ssUCS-l740IRI
mult;v~brator.
Fig. 17 - Monostable multivibrator.
(TOP VIEwl
92CS-24835
Fig. 20 - Input current test circuit.
TERMINAL ASSIGNMENT
Dimensions in parentheses are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10- 3 inch).
The photographs and dimensions of each
COS/MaS chip represent a chip when it
is part of the wafer. When the wafer is
cut into chips, the cleavage angles are
57° instead of 90° with respect to the
face of the chip. Therefore, the isolated
chip is actually 7 mils (0.17 mm) larger
in both dimensions.
Dimensions and Pad Layout for CD4093BH
____________________________________________________________________ 269
CD4094B Types
COS/MOS
a-Stage Shift-and-Store
Features:
Bus Register
High·Voltage Types (20·Volt Rating)
The RCA-CD4094B is an 8-stage serial shift
register having a storage latch associated
with each stage for strobing data from the
serial input to parallel buffered 3-5tate outputs_ The parallel outputs may be connected
directly to common bus lines_ Data is shifted
on positive clock transitions_ The data in
each shift register stage is transferred to the
storage register when the STROBE input is
high_ Data in, the storage register appears at
the outputs whenever the OUTPUT -ENABLE
signal is high.
Two serial outputs are available for cascading a number of CD4094B devices. Data is
available at the Os serial output terminal on
positive clock edges to allow for high-speed
operation in cascaded systems in which the
clock rise time is fast. The same serial information, available at the O'S terminal on the
next negative clock edge, provides a means
for cascading CD4094B devices when the
clock rise time is slow.
The CD4094B types are supplied in 16-lead
hermetic dual-in-line ceramic packages (0
and F suffixes). 16-lead dual-in-line plastic
package (E suffix). 16-lead ceramic flat
package (K suffix), and in chip form (H
suffix).
• 3·state parallel outputs for connection to common bus
• Separate serial outputs synchronous to both positive
and negative clock edges for cascading
• Medium speed operation - 5 MHz at 10 V (typ.)
• Standardized, symmetrical output characteristics
• 100% tested for quiescent current at 20 V
• Maximum input current of 1 JlA at 18 V over full package·
temperature range; 100 nA at 18 V and 25°C
• Noise margin (full package temperature range):
1 Vat VDD = 5 V
2 V at VDD = 10 V
2.5 V at VDD = 15 V
.5-V, 10-V, and 15·V parametric ratings
• Meets all requirements of JEDEC Tentative
Standard No. 13A, "Standard Specifications
STROBE
for Description of 'B' Series CMOS Devices"
DATA
Applications:
• Serial-to-parallel data conversion
• Remote control holding register
• Dual·rank shift, hold, and bus applications
PARALLEL OUTPUTS QI-QS
ITERMINALS 4.5.6,7,14,13,12,11,
RESPECTIVELY)
fUNCTIONAL DIAGRAM
I.
2
IS
15
Voo
"
OS
07
08
D'S
Os
CLOCK
01
02
12
0'
0
10
"
Vss
9
TOP VIEW
OUTPUT ENABLE
os
nCS-l~642
Fig. 1 - Terminal assignment
MAXIMUM RATINGS,Absolute·Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (V DO}
-0.5 to +20 V
(Voltages referenced to VSS Terminal!
INPUT VOLTAGE RANGE, ALL INPUTS
-0.5 to VDD +0.5 V
±10mA
DC INPUT CURRENT, ANY ONE INPUT
POWER DISSIPATION PER PACKAGE (PO):
for TA = -40.to +&OoC (PACKAGE TYPE E)
. . • • • • • '.'
500mW
Derate Linearly at 12 mW/oC to 200 mW
for T A = +60 to +850 C (PACKAGE TYPE E)
.
. . . • . . . ••
500mW
For T A = -55 to +1oooC (PACKAGE TYPES D,f)
Derate Linearly at 12 mWloC to 200 mW
for TA = +100 to +1250 C (PACKAGE TYPES 0, f)
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
loomW
FOR TA = FULL PACKAGE·TEMPERATURE RANGE (All' Package Types)
OPERATING-TEMPERATURE RANGE (TA):
-55 to +1250 C
PACKAGE TYPES 0, f. H
-40 to +850 C
PACKAGE TYPE E .
-65 to +150o C
STORAGE TEMPERATURE RANGE (Tstg )
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1116 ± 1132 inch (1.59 ± 0.79 mm) from case for 10 s max.
SERIAL
OUT
SERIAL
OUT 9
Os
*F-i
,-f
STATE
8
v
55
*AL.L. INPUTS PROTECTED
BY COS/MOS
PROTECTION NETWORK
Fig. 3 - Timing diagram.
Fig. 2 - CD4094B Logic diagram.
270 _______________________________________________________________________
CD4094B Types
RECOMMENDED OPERATING CONDITIONS at TA = 25"C, Except as Noted.
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges:
(VI
ts
Clock Pulse Width. tw
Clock Input Rise or Fall time,
trCl, tfCL:*
Strobe Pulse Width, tw
MAX.
3
18
5
10
15
125
55
35
-
5
10
15
200
100
83
-
5
10
15
5
10
15
5
10
15
Clock Input Frequency, fCl
.r
UNITS
MIN.
Supply-Voltage Range (For TA=Full
Package-Temperature Range)
Data Setup Time.
CL"
liMITS
VDD
CHARACTERISTIC
TRUTH TABLE
V
-
1.25
2.5
3
15
dc
-
5
5
0
0
,
.f
,
.f
,
f
'- ,
Strobe
Parallel
Outputs
D...
Serial
Outputs
0,
ON
OS·
O·S
X
X
OC
OC
07
NC
X
X
OC
OC
NC
Q7
,
,
X
NC
NC
07
NC
0
0
ON·'
Q7
NC
,
1
°N·1
NC NC
Q7
NC
NC
07
0
1
1
Logic 1 == High
Logie 0 == low
... " Level Change
X '" Don't Care
NC = No Change
OC = Open Circuit
ns
• At the positive clock edge information in the 7th shift register
stage is transferred to the 8th register stage and the Os output.
ns
: ""TE-lu->UUH0
-'-FORC04095BK3~,
FORCD4096BK3~"
RESET
Fig. 12 - Clock pulse rise and fall time
waveforms.
~,~'----~~------------~-----------------"
~
CLOCK
I·
"Ct.
Voo
aIASIDIRECTIOMA!. LO.IMPEDANCE
WH[N CONTROL INPUT I IS "LOW'
AND CONTROL INPUT 2 IS 'HI6K'
DIAN OPEN CIRCUIT WHiEN CONTROL
INPUT I IS "HIGH 'AN~ CONTROt. INPUT
Z IS "lOW'
-ALL ,,",PUTS PROTECT[O 8Y
STANDARD COSIMOS
PROTECTION NETWORK
INPUTS , - - - ' - - - - - ,
'os
o
Vss
Fig_II - CD40958 and CD40968 logic diagram.
V55
Fig. 13 - Quiescent device current test
circuit.
276 ____________________________________________________________________
CD4095B, CD4096B Types
V~NPU(JS
Vco :~:~u., 'NPUTS
'NPUTOVCOOUTPUTS
V,.
'--
~
o ~
:r
V~
VSS
Vss
VOO
"s
SEQUENTIALLY,
\Iss
TO aoTH \100 AND "'ss
CONNECT Al.L UNUSED
INPUTS 10 [ITHEA
HOTE:
TEST ANY CONBINATI~
VSS
OF INPUTS
cLOCK0--f-----"'-j
Voo OR Vss
92CS-27441AI
Vss
Fig. 14 - Input voltage test circuit.
Fig. IS - Input leakage current test
circuit.
Fig. 16 - CD40958 connected in toggle
mode.
Vss
"
~~g5~
--.-------rr------r-r------ll
C040968
CLOCK
12 CL
R
2
Vss
Fig. 17 - C040968 connected as a "0"
type f1ip-f1op_
STATE
0
I
I
I
2
I
3
I
4
I
5
I
G
I ., I
e
I
9
I
0
I
I
CLOCI(~
,,~
STATE QA Oe Oc 00
00
0
,
0
,
,
0
o
,
,,
NOTE: PINS21013RE5fT6
o
,.~
SET,GOTOVSSON
ALL UNITS
----------~~
Fig. 18 - Synchronous binary divide-by·ten counter.
DIMENSIONS AND PAD LAYOUT FOR CD4095B AND CD4096B
TERMINAL ASSIGNMENTS
NC
,.
"
SET
JI
'2
CLOCK
J2
J3
10
RESET
2
VOD
"
"
K2
ii
K'
a
Vss
TOP VIEW
NC= NO CONNECTION
CD4095B
33-4'
(0.084
-0 1091
71-79
(l804-2006)
~
The photographs and dimensions of each COS/MOS
chip represent. a chip when it is part of the wafer.
When the wafer is cut into chips, the cleavage an·
gles are 5]0 instead of 90D with respect to the face
of the chip. Therefore, the isolated chip is actually
7 mils (0.17 mm) larger in both dimensions.
"
SET
JI
'2
CLOCK
'0
K2
NC
92C5-2.6389
CD4095BH
J2
CD4096BH
J3
Vss
Dimensions in paren theses are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10- 3 inch).
,.
RESET
"
"
,
•
VOD
iO
0
TOP VIEIiII
NC = NO CONNECTION
91C$-24479
CD4096B
277
CD4098B Types
COS/MOS Dual Monostable
Multivibrator
Features:
High-Voltage Types (20-Volt Rating)
The RCA-CD4098B dual monostable multivibrator provides stable retriggerable/resettable one-shot operation for any fixed·voltage timing application.
An external resistor (RX) and an external
capacitor (CX) control the timing for the
circuit. Adjustment of RX and Cx provides
a wide rallge of output pulse widths from the
o and 0 terminals. The time delay from
trigger input to output transition (trigger
propagation delay) and the time delay from
reset input to output transition (reset propagation delay) are independent of RX and
CX·
Leading·edge·triggering (+TR) and trailingedge-triggering (-TR) inputs are provided
for triggering from either edge of an input
pulse. An unused +TR input should be tied
to VSS. An unused - TR input should be tied
to VDD. A RESET (on low level) is provided
for immediate termination of the output
pulse or to prevent output pulses when power
is turned on. An unused RESET input should
be tied to VDD. However. if an entire section
of the CD4098S is not used. its RESET
should be tied to VSS. See Table I.
In normal operation the circuit triggers (extends the output pulse one period) on the
application of each new trigger pulse. For
operation in the non-retriggerable mode. Q is
connected to - TR when leading·edge triggering (+TR) is used or Q is connected to +TR
when trailing-edge triggering (-TR) is used.
The time period (T) for this multi vibrator can
be approximated by: TX=Y,RXCX for CX;;'
0.01 JJ.F. Time periods as a function of RX
for values of Cx and VDD are given in Fig. 8.
Values of T vary from unit to unit and as a
function of voltage, temperature, and RXCX.
The minimum value of external resistance.
RX. is 5 kn. The maximum value of external
capacitance, CX, is 100 JJ.F. Fig. 9 shows time
periods as a function of Cx for values of RX
and VDD.
The output pulse width has variations of
±2.5% typically. over the temperature range
of -55°C to 125°C for CX=1000 pF and
RX=100 kn.
For power supply variations of ±5%, the output pulse width has variations of ±0.5%
typically, for VDD=10 V and 15 V and ±1%
typically, for VDD=5 Vat CX=1000 pF and
RX=5 kn.
These types are supplied in IS-lead hermetic
dual-in-line ceramic packages (D and F
suffixes). IS-lead dual-in-line plastic package (E suffix), IS-lead ceramic flat package_
(K suffix), and in chip form (H suffix).
The CD40988 is similar to type MC14528.
·XI
r-Il-+-'l.M...... VDD
• Retriggerable/resettable capability
• Trigger and reset propagation delays
independent of RX. Cx
• Trigge'i!!g from leading or trailing edge
• 0 and 0 buffered outputs available
• Separate resets
• Wide range of output-pulse widths
• 100% tested for maximum quiescent
current at 20 V .
• Maximum input current of 1 JJ.A at
18 V over full package-temperature
range; 100 nA at 18 V and 25° C
• Noise margin (full package-temperature
rangel:
1 Vat VOD= 5 V
2 V at VOD=10 V
2.5 V at VOD=15 V
• 5-V •. 10-V. and 15-V parametric ratings
• Standardized ••ymmetrical output
characteri.tics
• Meet. all requirement. of JEDEC
Tentative Standard No. 13A. "Standard Specification. for De.cription of 'S'
Series CMOS Device ....
., iii
'-41"'-'lM~- VDD
ex.
Yss·a
92CS-242n
C04098B
Functional Diagram
C XI
RxCxUI
RESET (I)
+TR (II
-TR III
01
I.
,.
vDD
CX.
3
I.
13
I.
RESET (2)
I.
•
•
"
RX Cx l21
+TR (2)
-TRIZI
or
10
A.
vss
9
02
Applications:
TOP VIEW
• Pul.e delay and timing
• Pulse .haping
• A.table multivibrator
TERMINALS 1,8,15 ARE
ELECTRICALLY CONNECTED
INTERNALLY
92CS-24848RI
TERMINAL ASSIGNMENT
MAXIMUM RATI NGS, Absolute·Maximum Values:
DC SUPPLY·VOL TAGE RANGE. (VDDI
(Voltages referenced to VSS Terminall
-0.5 to +20 V
INPUT VOLTAGE RANGE. ALL INPUTS
·0.5 to VDO +0.5 V
DC INPUT CURRENT. ANY ONE INPUT
±10mA
POWER DISSIPATION PER PACKAGE (POl:
For TA = -40 to +60 0 C (PACKAGE TYPE EI
. . . . . . . ..
SOOmW
For T A = +60 to +850 C (PACKAGE TYPE E!
Derate Linearly a1 12 mW/oC 10200 mW
For TA = -55 to +1000 C (PACKAGE TYPES D.F I
. . . . . ..
.
SOOmW
For TA = +100 to +125 0 C (PACKAGE TYPES D. F 1.
Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE·TEMPERATURE RANGE (All Package Typosl
100mW
OPERATING·TEMPERATURE RANGE ITAI:
PACKAGE TYPES D. F. H
··55 to +12SoC
PACKAGE TYPE E
-40 to tBSOC
STORAGE TEMPERATURE RANGE (T stg !
·65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING!:
At distance 1/16 ± , /32 Inch (1.59
± 0.79
mm) from case for lOs max.
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected
so that operation is always within the following range.:
LIMITS
VDD
V
MIN.
MAX.
Supply-Voltage Range (For T A =
Full Package· Temperature
Range)
-
3
18
V
Trigger Pulse Width tW(TR)
5
10
15
140
SO
40
-
ns
Reset Pulse Width tWIRl
(This is a function of CX)
-
CHARACTERISTIC
Trigger Rise or Fall Time
tr(TR), tf(TR)
278
+T.
--TR
RESET
5·15
See
Dynamic Char.
Chart and
Fig. 19
-
100
UNITS
JJ.s
CD40988 Types
TABLE I
Ce4098B FUNCTIONAL TERMINAL CONNECTIONS
FUNCTION
Vee TO
TERM. NO.
VSSTO
TERM. NO.
INPUT PULSE
OTHER
TO TERM. NO. CONNECTIONS
MONO, MON0 2 MONO, MON0 2 MONO, MON0 2 MONO, MON0 2
Leading·Edge
Trigger!
Retriggerable
3,5
'1,13
4
12
Leading·Edge
Trigger!
Non·retriggerable
3
13
4
12
Trailing·Edge
Trigger!
Retriggerable
3
13
Trailing·Edge
Trigger!
Non·retriggerable
3
13
Unused Section
5
11
5·7
11-9
DRAIN-TD-SOURCE VOLTAGE (VOsJ-V
Fig. 1 - Typical output low (sink)
current characteristics.
12
4
3,4
5
11
5
11
4·6
12-10
12,13
"'OTES,
1. A RETRIGGERABLE ONE-SHOT MUL TIVIBRATOR HAS AN OUTPUT PULSE
WIDTH WHICH IS EXTENDED ONE FULL
TIME PERIOD ITXI AFTER APPLICATION
OF THE LAST TRIGGER PULSE.
2. A NON·RETRIGGERABLE ONE·SHOT
MULTIVIBRATOR HAS A TIME PERIOD
TX REFERENCED FROM THE APPLICATION OF THE FIRST TRIGGER PULSE.
The minimum time between
INPUT PULSE TRAIN
retriggering edges (or trigger
and ret rigger edges) is 40
per cent of (T X).
AETRIGGEAABLE MODE PULSE WIDTH
DRAIN-TO-SOURCE VOLTAGE (VosJ-V
--1
Fig. 2 - Minimum output low (sink)
curren t characteristics.
(+TR MODEl
NON·RETRIGGERABLE MODE PULSE
~
f----Tx~
WIOTH
I+TR MODE)
DRAIN-TO-SOURCE VOLTAGE (VosJ-V
I
Voo
.
3(131
RESET
Fig. 3 - Typical output high (source)
current characteristics.
16~VDD
L -_ _ _ _ _ _ _ _ _
---o::(~~laV~o-
DRAIN-TO-SOURCE VOLTAGE IVosJ-V
NOTE: SCHEMATIC SHOWN IS 1/2 OF TOTAL.
~~~~~~~ TA
: ~~6~~~ ::::=:~s
1,8,15 ARE EL.ECTRICAl.LY CONNECTED
·1 NTE RNALL Y.
*:~,!~~~g A::
COS/MOS ~ROTECTION
NETWORK
9lCM-27628RI
Vss
Fig. 4 - C040988 logic diagram.
Fig. 5 - Minimum output high (source)
current characteristics.
________________________________________________________________ 279
CD4098B Types
STATIC ELECTRICAL CHARACTERISTICS
CHARAC·
TERISTIC
Quiescent
Device
Current
IDD Max.
Output Low
(Sink I
Current,
IOL Min.
Output High
(Source)
Current,
IOH Min.
Output Volt·
age:
Low· Level,
VOL Max.
Output Volt·
age:
High·Level,
VOH Min.
Input Low
Voltage,
VIL Max.
CONDITIONS
Vo
VIN VDD
(VI
(VI (VI
-
LIMITS AT INDICATED TEMPERATURES (OCI
Values at -55,+25,+125 Apply to D,IF,H Pkgs.
Values at -40,+25,-185 Apply to E Pkgs.
UNITS
+25
-55 -40 -185 +125 Min.
Typ. Max.
-
0,5
0,10
0,15
0,20
5
10
15
20
1
2
4
20
0.4
0.5
1.5
4.6
2.5
9.5
13.5
0,5
0,10
0,15
0,5
0,5
0,10
0,15
5
10
15
5
5
10
15
0.64
1.6
4.2
-0.64
-2
-1.6
-4.2
-
0,5
0,10
0,15
5
10
15
0.05
0.05
0.05
-
-
0,5
0,10
0,15
5
10
15
4.95
9.95
14.95
4.95
9.95
14.95
0.5,4.5
1,9
1.5,13.5
-
5
10
15
1.5
3
4
5
10
15
3.5
7
11
-
-
-
0.5,4.5
Input High
1,9
Voltage,
1.5,13.5 VIH Min.
Input
0,18
Current,
liN Max.
Output
0,18
0,18
Leakage
lOUT Max.
1
2
4
20
30
60
120
600
30
60
120
600
-
-
0.42 0.36 0.51
0.61
0.9
1.3
1.5
1.1
4
2.4
3.4
2.8
-0.61 -0.42 -0.36 -0.51
-1.8 -1.3 -1.15 -1.6
-1.5 -1.1 -0.9 -1.3
-4
-2.8 -2.4 -3.4
0.02
0.02
0.02
0.04
1
2
4
20
1
2.6
6.8
- rnA
-1
t---=-3.2
-2.6
-6.8
0
0
0
0.05
0.05
0.05
5
10
15
-
-
-
1.5
3
4
3.5
7
11
-
-
-
/JA
LOAD CAPACITANCE (CL1-pF
9lCS-2.8735
Fig. 6 - Typical propagation delay time vs.
load capacitance. trigger into 0
out. (All values of CXand RX')
V
V
Fig. 7 - Transition time "s. load capacitance
for RX= 5 kfHOOOO kfland
18
±0.1
±0.1
±1
±1
-
±1O- 5 ±0.1
/J A
18
±0.4
±0.4
±12
±12
-
±10-4 ±0.4
/J A
CX = 75pF·70000pF.
~ lo"I--+--+-+--+---+-AiLl-.,i
110
11
I:
o.
PULSE WIDTH IPWI-,..
Fig. 8 - Typical external resistance vs.
pulse width.
Fig. 9 - Typical external capacitance vs.
pulse width.
0.'
10
2
.. 68102 2.
'" 68 10' 2.
..
68104 Z
EXTERNAL CAPACITANCE 1CxJ-pF
.. 681~
ucs-une
Fig. 10 - Typical minimum reset pulse width
VB. external capacitance.
280 _________________________________________________________________
CD4098B Types
DYNAMIC ELECTRICAL CHARACTERISTICS
TEST CIRCUITS
At TA = 25° C; Input t r,tf=20 ns, CL=50 pF, R L=200 krl.
TEST CONDITIONS
CHARACTERISTIC
RX (krl.)
Trigger Propagation Delay Time
+TR. -TRto 0, Q
5 to
10,000
tpHL, tpLH
Minimum Trigger Pulse Width,
tWH, tWL
Transition Time,
tTLH
tTHL
Reset Propagation Delay Time,
TpHL, TpLH
LIMITS
Typ.
Max.
250
125
100
500
250
200
5
10
15
5
10
15
70
30
20
100
50
40
140
60
40
200
100
80
100
50
40
150
75
65
200
100
80
300
150
130
Cx (pF) VDD (V)
5
;;>15
10
15
5 to
10,000
;;>15
5 to
10,000
;;>15
5 to
10,000
15 to
10,000
5 to
10,000
0.01 JlF
to
0.1 JlF
5
10
15
5
10
15
5 to
10,000
0.1 JlF
to
1 JlF
5
10
15
250
150
80
500
300
160
5 to
10,000
;;>15
5
10
15
225
125
75
450
250
150
15
5
10
15
100
40
30
200
80
60
1000
5
10
15
600
300
250
1200
600
500
0.1 JlF
5
10
15
25
15
10
-
5 to
15
-
10,000
5
10
15
Minimum Reset Pulse Width,
tWR
100
Trigger Rise or Fall Time
trlTR), tflTR)
-
Pulse Width Match
Between Circuits in
Same Package
10
Input Capacitance, CIN
UNITS
INPUTS
ns
ns
Fig. 12 - Ouiescent·device-current
test circuits.
ns
v,. 'NPUTOVCOOUTPUT'
ns
v,s
NOTE:
!lZCS-2744IAI
TEST ANY COMBINATION
OF INPUTS
Fig. 13 - Input·voltage test circuit.
ns
50
30
20
IJS
100
Jls
5
7.5
7.5
10
15
15
%
5
7.5
pF
1NPUO'
VOIl
NOTE
~
MEASURE INPUTS
0---0Vss
SEQUENTIALLY,
TO BOTH Yao ANDVss
CONNECT ALL UNUSED
INPUTS TO EITHER
Voo OR Vss
9lCS
TOlllllcullhl'.,.,... po_d'.'pIIllOnIPI
forllSltlMnlDO'1odutycyc":
P,OO" ' - ' po_ for lGCnr.dllly eye..
p
~
~
'--
v~
Yoo
Any Input
,.-_L-.....,
o
Vss
{~')Pl00Whlr' tm -_·lhDlpul.wtdth
U40l
Vss
Fig. 14 - Input leakage current test circuit.
r----j
TT
r-1
n
L---..J L
'r -lrlftltpulMplrtod --J
.·t·FOftm-600",•. 'T"1ooo"l, C)(-O.Ol"F.
VOO"SV
p' .. (,::)11)3 "W" BOO jlW 1_ dome!
Yeo" sy ----10\1---15Y--
2
,0'
z •
'~o Z
.. 61 102 2
• &1105
ONE-SHOT PULSE WIDTH
z ..
"to' 2
lineonp.phl '
4 611O~
("ml-,..
Fig. 11 - Average power dissipation vs. one·short pulse width.
_______________________________________________________________________ 281
CD4098B Types
APPLICATIONS
RXI
RX2
JL+ TR
VDD
INPUT PUl.SE
~
TIJIIIRXI eX!
~Tr-:+==f2~
OUTPUT PUlSE
---.--
TZRSRX:C)(2
ex !;O.OI",F
92CS·24256R2
Fig. 15 - Pulse delay.
s~u.-~ar-~t-----------------
__
100. TX VI. RX
RX
IOoIAvg.1
lmA
10kO
VDD;---
~~R.'( 0...J
RESET*~
*lOENSURER£START,APPLYRESET
(NEGATIVE PULSE) A"ER Veo
~~:P~~~:i~~[
HASA[ACHED
02
~
I'--Tx----l
--
IDD~--
I
~
O.05mA
TX
In +T21
3.8J'S
~
3.2,...
0.6 rnA
0.5.
~
SV
0.5.
2.SmA
SmA
VDO
~
10V
ot
15V
3._
10Mn
~
lmA
Note.
All V11lue ••retypcal.
cxrange: o.OOCn,..FIOO.1,..F.
92CIII.28MO
Fig. 16 - Astable multivibrator with restart after reset capability.
75-83
(1.905-2.108)
J
Dimensions and Pad Layout for CD4098BH
Dimensions in parentheses are in millimeters and
are derived from the basic inch dimensions as
indicated. Grid graduations are in mils (10- 3 inch).
282
The photograph and dimensions represent a chip
when it is part of the wafer. When the wafer is cut
into chips the cleavage angles are 5,0 instead of
goo with respect to the face of the chip. Therefore,
the isolated chip is actually 7 mils (0.17 mmJ
larger in both dimensions.
CD4099B Types
COS/MOS
a-Bit Addressable Latch
High-Voltage Types (20-Volt Rating)
The RCA-CD4099B 8-bit addressable latch
is a serial·input, parallel·output storage regis·
ter that can perfor!'1 a variety of fu nctions.
Data are inputted to a particular bit in the
latch when that bit is addressed (by means
of inputs AO, A1, A2) and when WRITE
DISABLE is at a low level. When WRITE
OISABLE is high, data entry is inhibited;
however, all 8 outputs can be continuously
read independent of WRITE DISABLE and
address inputs.
A master RESET input is available, which
resets all bits to a logic "0· level when RESET
and WRITE DISABLE are at a high level.
When RESET is at a high level, and WRITE
DISABLE is at a low level, the latch acts as
a 1-of-8 demultiplexer; the bit that is ad·
dressed has an active output which follows
the data input, while all unaddressed bits
are held to a logic "0" level.
The CD40998 types are supplied in l6-lead
hermetic ceramic dual-in-line packages (D
and F suffixes), l6-lead plastic dual-in-line·
packages (E suffix), l6-lead ceramic flat
packages (K suffix), and in chip form (H
suffix).
DATA
Features:
_
_
_
_
Serial data input
- Active parallel output
Storage register capability
- Master clear
Can function as demultiplexer
Standardized, symmetrical output characteristics
100% tested for quiescent current at 20 V
Maximum input current of 1 /lA at 18 V
(full package·temperature range), 100 nA
at 18 V and 25 0 C
- Noise margin (full package· temperature
range) = 1 Vat VDD = 5 V, 2 V at VDO
=10 V, 2,5 Vat VOD =15 V
- 5-V, 1Q.V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative
Standard No. 13A, "Standard Specifications
for Description of '8' Series CMOS Devices"
RESET
Functional Diagram
Applications:
.. Multi·line decoders
.. AID converters
MAXIMUM RATINGS, Absolute·Maximum Values:
DC SUPPLY·VOL TAGE RANGE, (VDDI
(Voltages referenced to VSS Terminal)
-0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS
-0.5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT
±10mA
POWER DISSIPATION PER PACKAGE (PO):
For T A = -40 to +60 0 C (PACKAGE TYPE E)
. . . . . ..
.
500mW
For T A = +60 to +85 0 C (PACKAGE TYPE E)
Derate Linearly at 12 mW/oC to 200 mW
For TA = -55 to +100 0 C (PACKAGE TYPES D,F)
. . . . . . ..
500 mW
Derate Linearly at 12 mW/oC to 200 mW
For T A = +100 to +125 0 C (PACKAGE TYPES 0, F)
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE·TEMPERATURE RANGE (All Package Types)
100mW
OPERATING·TEMPERATURE RANGE (TA):
PACKAGE TYPES 0, F, H
-55 to +125 0 C
-40 to +8SoC
PACKAGE TYPE E .
STORAGE TEMPERATURE RANGE (Tstgl
-65 to +1500 C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16
± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max.
a7
aD
.'"
AO~AO
v~.
.*
A4* . f'.-.
['........
WRITE
DISABLE~WD
,.
•
AO
A'
A'
Vss
A'~~
DATA~'D
RESET
DATA
WRITE
DISABLE
A'
1m
*
AI
A2~A2
* v- ~n
----'4
a3
Ai
,.
VOO
15
14
13
12
Q6
05
04
03
a.
7
10
01
a
•
ao
'-T=ep=V""E"W::--'92CS-240426
TERMINAL ASSIGNMENT
a4
A'
AI
Z'"
RESET~R
ADDRESS
WD
VDD
*PROTECTED
AU INPUTS ARE
BY
~
DATA---++1
,
DRAIN-TO-SQURCE vm:fAGE (VDsl-1/
COSIMOS PROTECTION
NETWORK
V••
Fig. 1 - Logic diagram of CD40998 and detail of 1 of Blatches.
Fig. 2 -
Typical output low (sink)
current characteristics.
--------------------------------------------------------------------283
CD40998 Types
R ECOMME NDE DOPE RA TI NG CONDITIONS at TA = 25" C (Unless otherwise specified)
For maximum reliability, nominal operating conditions should be selected so that operation
is always within the following ranges.,
CHARACTERISTIC
SEE
VDD
FIG. 15"
(V)
Supply Voltage Range:
(At T A = Full Package
LIMITS
MIN.
3
MAX.
UNITS
18
Data
Address
200
0
10
100
15
80
5
400
-
CD
10
200
-
15
125
-
5
150
-
10
75
-
15
50
5
100
-
10
50
-
15
35
-
5
150
-
10
75
-
15
50
-
0
Reset
Setup Time, ts
Data to WRITE DISABLE
Hoid Time, tH
Data to WRITE DISABLE
*
-
5
0
G
0
0
0
1
1
1
0
1
V
Temperature Range)
Minimum Pulse Width, tw
MODE SELECTION
ADDRESSED UNADDRESSED
WD R
LATCH
LATCH
WD
Follows Data
Holds Previous
State
Follows Data Reset to "0"
(Active High 8·Channel Demulti·
plexer)
Holds Previous State
Reset to "0" . Reset to "0"
I
f
= WRITE
DISABLE
R = RESET
ns
ns
Fig. 3 - Definition of WRITE DISABLE ON time.
ns
Circled numbers refer to times indicated on master timing diagram.
E
Note: In addition to the above characteristics, a WRITE DISABLE ON time (the time that WRITE
DISABLE is at a high level I must be observed during an address change for the total time that the
external ~ddress lines AO, A 1, and A2 are settling to a stable level, to prevent a wrong cell from
being addressed (see Fig, 3),
I
...5
15
GATE-TO-SOURCE VOLTAGE {VGSI-15 V
~12.5
8
10
10V
,v
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VOs)-V
Fig. 4 - Minimum output low (sink)
current characteristics.
START
CONVERSION
ORAIN-TO-SOURCE VOLTAGE (Vos)-V
-IS
-10
-5
AMBIENT TEMPERATURE (TA'-2S·C
GATE-TO-SOURCE VOLTAGE (VGS)'-SV
-S
-10
-IOV
-20
·20
*
-ISV
C04001
I ~~C~~SIV~Ctt~~LO-2A
'N~~~~
____________________________
~
Fig. 5 - , AID converter
284
92CL-27UI
Fig. 6 - Typic.' output high (sourcel
current characteristics.
-30
CD4099B Types
DRAI~-TO-SOURCE
STATIC ELECTRICAL CHARACTERISTICS
CHARACTER·
ISTIC
Quiescent Device
Current,
IDD Max.
Output Low
(Sink) Current
IOL Min.
Output High
(Source)
Current,
IOH Min.
0,5
0,10
5
10
1.5
4.6
0,15
0,5
15
5
2.5
9.5
13.5
0,5
0,10
0,15
5
10
15
Output Voltage:
-
0,5
5
Low-Level,
-
10
15
-
0,10
0.15
0,5
0,10
0,15
0.5,4,5
-
1,9
1,5,13.5
0,5,4.5
1,9
-
-
5
10
15
5
10
15
0,18
18
VOL Max.
Output Voltage:
High·Level,
VOH Min.
Input Low
Voltage,
VIL Max.
Input High
Voltage,
VIH Min.
Input Current
liN Max.
-
1.5,13.5
-
-
-
0.64
1.6
4.2
-0.64
-2
-1.6
-4.2
0.61
0.42
1.5
4
-0.61
-1.8
1.1
2.8
-0.42
-1.3
-1.5
-4
-1.1
-2.8
0.05
0.05
0.05
4.95
9.95
14.95
5
10
15
0.36
±0.1
0.51
1.3
0.9
2.4
34
-0.36 -0.51
-1.15 -1.6
-0.9 -1.3
2.4
3.4
-
4.95
9,95
14.95
1.5
3
4
-
3.5
3.5
7
7
11
±0.1
-!5
-10
LIMITS AT INDICATED TEMPERATURES (OC)
Values at -55, +25, +125 Apply to D,F ,H Packages
CONDITIONS
Values at -40, +25, +85 Apply to E Package
UNITS
+25
Vo
VIN VDD
+85
+125 Min.
Typ. Max.
(V)
(V) -55 -40
(V)
0.04
150
150
5
5
5
0,5
5
300
0.04
10
10
10
300
0,10 10
/1 A
0.04
20
20
20
600
600
0,15 15
0.08
100
100
3000 3000
100
0,20 20
0.4
0.5
VOLTAGE ('Ios)-V
±1
±1
1
2.6
6.8
-1
AMBIENT TE'-IPERATURE !TAI"25"C
GATE -TO-SOURCE VOLTAGE (\lGSI" -5 \I
lJlllt
-
mA
Fig. 7 - Minimum output high (source)
current characteristics.
-3.2
2.6
6.8
0
0.05
0
0
5
10
15
0.05
0.05
V
-
1.5
3
4
11
-
-
-
±1Q-5
±0.1
10205040
~
807080
90
LOAO CAPACITANCE (CL'-pF
V
Fig. 8 - Typical propagation delay time
(data to an) vs. load capacitance.
JlA
LOAO CAPACITANCE (CLI-pF
Fig. 9 - Typical transition time lIS. load
capacitance.
AMBIENT TEMPERATURE (fA "25-C
_ _ _ _ LOAD CAPACITANCE (CL",5pF
_ _ CL"50pF
I~!~,----~~~~~"~-t-----t----~
,
IOI~ ..::
CD4099BH
DIMENSIONS AND PAD LAYOUT
Dimensions in parentheses are in millimeters and
are derived (rom the basic inch dimensions as
indicated. Grid graduations are in mils (10- 3 inch).
,
The photographs and dimensions of each COS/MOS
chip represent a chip when it is part of the wafer.
When the wafer /:5 cut into chips, the cleavage
angles are 57° instead of 90° with respect to the
face of the chip. Therefore, the isolated chip ;s
actuallv 7 mils (0. 17 mm) larger in both dimensions.
00'
2
100
4 68
101
2
4
68
2
4 68
2
4 68
102
1 J
ADDRESS CYCLE TIME-.IIt
2
4
68
10 4
10'
Fig. TO - Typical dynamic power dissipation vs.
address cvcle time.
285
CD40998 Types
DYNAMIC ELECTRICAL CHARACTERISTICS at
Input tr- tf = 20 ns, R L = 200 Kn
TA =25" C, CL =5OpF,
INPUTS
o
CONDITIONS
SEE
VDD
(V)
FIG.15"
CHARACTERISTIC
Propagation Delay:
CD
Data to Output.
0)
tpLH·
IpHL
eD
Reset to Output,
MAX.
5
200
400
75
150
15
,50
100
5
200
400
WRITE DISABLE
to Output,
TYP.
10
tpLH·
tpHL
LIMITS
ALL PACKAGE TYPES
W
80
160
15
60
120
5
175
350
10
80
160
15
65
130
5
225
450
10
100
200
tpHL
15
75
150
Transition Time,
tTHL'
5
100
200
(Any Output)
tTLH
10
50
100
15
40
80
5
100
200
10
50
100
tpHL
Address to Output.
@
tpLH'
Minimum Pulse
CD
Width,tW
Data
@
Address
G)
Reset
15
40
80
5
200
400
10
100
200
15
65
125
5
75
150
10
40
75
15
25
50
5
50
100
10
25
50
Minimum Setup
(0
Time. IS
Data to WRITE DISABLE
15
20
35
5
75
150
10
40
75
Minimum Hold
G)
Time. tH
15
Data to WRITE DISABlE
Input Capacitance. CIN
.
.
Circled
numbers refer
Any Input
25
50
5
7,5
Vss
UNITS
V'!'I
Fig. 11 - Quiescent device current
test circuit.
n,
'NPUTOVCO
. OUTPUTS
V''-N
~
:t
V~L
NOTE;
~srN~~~~ClMBINATION
Vss
92CS-27441Rl
Fig. 12 n,
,
n,
Input voTfiJ/ie test circuit.
v~NPu(J'
'. ~7.".,"~
o ~
SEQUENTIALLY,
TO BOTH Voo AND Vss·
Vss
CONNECT ALL UNusm
INPUTS TO EITHER
Yoo OR VSS·
VSS
n,
n,
Fig. 13 - Input current test circuit.
AO
00
A'
A2
AI
A2
0'
Q2 II
A>
WD
DO.
CD4099
,
n,
2
"cO
AO
n,
S
pF
*
DO.
00
'A 0010
11
0011
'2
O.
DOl2
J3 0013
DATA
0'
CD4099 O.
0014
0015
06
07
0016
A'
A2
WD
7
1/6 C04069
0'
02
,.
"
,2C5-27675
=\'-----
DO'
'A DO.
DO'
03 12
04 13 DO'
05 14 006
Q6 I ' DO 7
008
07
OATA
DATA IN
to times indicated on master timing diagram .
AO,AI,A2
•
00
VDD
Fig. 14 - 1 of 16 decoder/demultiplexer.
1/4 C04016
a
,
INk
2
WRITE OlSABL.E
,
,
'---____--'F2L
RESET
/
"
/
Gl
00
/
X
IN/D\
,
/
0" ,--+---j--+--
O, _ _ _ _ _J
Fig. 15 -
286
Master timing diagram.
Fig. 16 ~ Muliiple selection decoding - 4 x 4
crosspoint switch.
CD4502B Types
COS/MOS Strobed Hex
Inverter /Buffer
High-Voltage Types (20-Volt Rating)
The RCA-CD4502B consists of six inverter/
buffers with 3-state outputs. A logic "'" on
the OUTPUT DISABLE input produces a
high-impedance state in all six outputs. This
feature permits common busing of the outputs, thus simplifying system design. A
Logic "'" on the INHIBIT input switches
all six outputs to logic "0" if the OUTPUT
DISABLE input is a logic "0". This device
is capable of driving two standard TTL loads,
which is equivalent to six times the JEDEC
"B"-series IOL standard.
The CD4502B types are supplied in 16-lead
hermetic dual-in-line ceramic packages (D
and F suffixes), 16-lead dual-in-line plastic
package (E suffix), 16-lead ceramic flat
package (K suffix). and in chip form (H
suffix). Thisdevice issimilartothe MC14502.
Features:
.2 TTL·load output drive capability
•
•
•
•
•
•
3-state outputs
Common output-disable control
Inhibit control
100% tested for quiescent current at 20 V
5-V, 10-V, and 15-V parametric ratings
Maximum input current of 1 /lA at 18 V over
full package-temperature range; 100 nA at
18 V and 25°C
• Meets all requirements of JEOEC Tentative
Standard No. 13A, "Standard Specifications
for Description of 'B' Series CMOS Devices"
• Noise margin (full package-temperature
rangel =
1 VatVDo=5 V
2 V at VDO = 10 V
2.5 Vat VOO = 15 V
THREE-STATE
OUTPUT
DISABLE
,.•
INHIBIT
3
0'
D' 6
O.
0'
,
03
04 10
04
03
os
0!5 13
06 ,S
14 Q6
VOO"16
VSS"e
FUNCTIONAL DIAGRAM
Applications:
•
3-state hex inverter for interfacing IC's
with data buses
• COS/MaS to TTL hex buffer
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VDLTAGE RANGE, (VDDI
(Voltages referenced to VSS Terminal)
-0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS
-0.5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT
±10mA
POWER DISSIPATION PER PACKAGE (Pol:
o
For T A = -40 to +60 C (PACKAGE TYPE El
. . . . . • . ..
500mW
Derate linearly at 12 mW/oC to 200 mW
For T A = +60 to +850 C (PACKAGE TYPE El
.
. . . . • • . ..
500mW
For TA = -55 to +1000 C (PACKAGE TYPES D,F)
For T A = +100 to +125 0 C (PACKAGE TYPES 0, F)
Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types)
100mW
OPERATING· TEMPERATURE RANGE (TAl:
PACKAGE TYPES 0, F, H
-55 to +1250 C
-40 to +850 C
PACKAGE TYPE E .
-65 to +1500 C
STORAGE TEMPERATURE RANGE (Tstgl
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1116 ± 1/32 inch (1.59 ± 0.79 mm) from case for lOs max.
GN;ER'EFV~FFERt';;I-
-- - - I
I
VOD
.><>-1--1""""'----_ _
,----+---t-'
3-:iTATE
OUTPUT
d :
Ho,
~
I
DISABLE INHIBIT On
Qn
0
0
0
1
0
0
1
0
0
1
x
0
1
X
X
Z
:
V55
1_- ___________ _
art.
Fig.2 - Typical output low (sink)
current characteristics_
TRUTH TABLE
I
DISABLE
>---f--
ORAIN-TO-SOURCE VOLTAGE IVOSI-V
logic 0 = Low
Z
= High
DRAIN-TO-SOURCE VOLTAGE IVDSI-V
Fig.3 - Minimum output low (sink)
current characteristics.
DRAIN-TO-SOURCE VOLTAGE lVoSJ-V
Impedance
X = Don't Care
TO 50 OTM!:.R
IN/ERlER/BUFFERS
Logic 1 = High
-II- ALL INPUTS AM[
vss
PROTECTED
BY COS I MOS PROTECT ION
NETWORK
92CM~29145
_
Fig. 1 - Logic diagram of 1 of 6 identical inverterlbuffers.
03
03
0'
3-STATE
OUTPUT DISABLE
,.• ..,.
OS
OS
'3
os
's
,.
0'
O.
O.
V55
voo
INHIBIT
II
os
'A
9
O.
04
TOP VIEW
TERMINAL ASSIGNMENT
Fig.4 - Typical output high (source)
current characteristics.
____________________________________________________________________ 287
CD4502B Types
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that operation is always within the following ranges:
LIMITS
CHARACTERISTIC
Min.
Max.
3
18
Supply·Voltage Range (For TA = FullPackage'
Temperature Rangel
DRAIN-lO-SOURCE VOLTAGE (Vos)-V
-15
AMBIENT TEMPEIlATURE
-10
(TAI·2~·C
-,
UNITS
fF.f. ,...
V
.- ....
,-
"'-15'V"
STATIC ELECTRICAL CHARACTERISTICS
-
LIMITS AT INDICATED TEMPERATURES (OCI
Values at -~5, +25, +125 Apply to 0, F ,H Packages
Values at -40, +25, +85 Apply to E Package
UililTS
+25
VIN VDD
+85
+125 Min.
Typ. Max.
(V) -55 -40
(V)
D,S
5
1
30
30
1
0.02
1
0,10 10
2
60
2
60
0.02
2
p.A
0,15 15
4
0.02
4
4
120
120
-
0,20
20
0.4
0,5
5
1.5
4.6
2.5
9.5
13.5
0,10
0,15
0,5
0,5
0,10
0,15
10
15
5
5
10
15
Output Voltage:
-
0,5
5
Low-Level,
-
-
0,10
0,15
0,5
0,10
0,15
10
15
5
10
15
0.5,4.5
-
1,9
1.5.13.5
-
5
10
15
5
T
CONDITIONS
CHARACTER·
ISTIC
Quiescent Device
Vo
(V)
-
Current,
IDD Max.
-
Output Low
(Sink) Current
IOL Min.
0.5
Output High
(Source)
Current,
IOH Min.
VOL Max.
-
Output Voltage:
High·Level,
VOH Min.
Input Low
Voltage,
VIL Max.
-
4.5
9
Input High
Voltage,
VIH Min.
13.5
Input Current
liN Max.
3-State Output
Leakage Current
-
20
600
600
3.66
2.52
9.6
9
24
25.2
-0.64 -0.61
-2
-1.8
-1.6 -1.5
-4.2
-4
6.6
16.8
-0.42
-1.3
-1.1
-2.8
2.16
5.4
14.4
-0.36
-1.15
-0.9
-2.4
20
3.84
0.05
0.05
0.05
4.95
9.95
14.95
3.06
6
15.6
-
40.8
-1
-3.2
-2.6
-6.8
-
-
0
0.05
-
0
0
5
10
15
0.05
0.05
-
-
-
1.5
3
4
3.5
-
7
11'
-
-
4.95
9.95
14.95
-
-
rnA
-
INPUT VOLTAGE IVI)-V
-
V
0,18
18
±0.1
±0.1
±1
±1
-
±10- 5
±0.1
p.A
0.18
18
±0.4
±0.4
±12
±12
-
±10-4
±0.4
p.A
-
Fig.6 - Typical voltage transfer
characteristics.
V
10
15
11
current characteristics.
20
-
7.8
20.4
-0.51
-1.6
-1.3
-3.4
-
1.5
3
4
3.5
7
0.04
Fig.5 - Minimum output high {source}
2
0,18
100
4 "
2 4
10'
•
102
2
4"
2
4 I.
10"
I~
2 4 ••
10 I
INPUT FREQUENCyltll-1IH1
lOUT Max.
Fig. 7 - Typical power dissipation as a
function of input frequency.
LOAD CAPACITANCE IC,..I-pf
LOAD CAPACITANCEICLI-pF
'2Cs-Z9t4e
Fig.S - Typical transition time as a function
of load capacitance.
Fig.9 - Typical propagation-delay time as a
function'of load capacitance.
Fig. 10 - Power-dissipation test circuit.
288 _________________________________________________________________
CD4502B Types
DYNAMIC ELECTRICAL CHARACTER ISTICS at T A = 25°C; Input t r, tf = 20 ns,
CL = 50 pF, RL = 200 Kr!
INPUTS
TEST CONDITIONS
CHARACTERISTIC
VDD
(V)
Data or Inhibit Delay Times:
High to Low, tpHL
Low to High, tpLH
Disable Delay Times:
Output High to High
Impedance, tPHZ
High·1 mpedance to Output
High, tPZH
See Fig. 14
Output Low to High
Impedance, tPLZ
LIMITS
TYP
MAX
5
10
15
5
10
15
5
10
15
135
60
40
190
65
60·
40
30
270
120
80
380
180
130
120
80
60
5
10
15
110
50
40
220
100
80
5
10
15
125
65 \
55
250
130
110
5
10
15
5
10
15
5
10
15
125
55
40
100
50
40
60
30
20
250
110
80
200
100
80
120
60
40
5
7.5
gO
,_L--,
o
Vss
UNITS
ns
Fig. 11 - Qu;escent·device-current
test circuit.
ns
gZCS-Z744IRI
High I mpedance to Output
Low, tpZL
Transition Times:
Low to High, tTLH
High to Low,tTH L
Any Input
I nput Capacitance, CI N
VDD
PULSE
GENERATOR
0'
VDD
0'
01
06
Fig. 12 - Input-voltage test circuit.
OD
"00
ns
INPu(
V J s NOTE
~
o
~
.
'Iss
.
pF
MEASURE INPUTS
SEQUENTIALLY,
TO BOTH '100 ANOVSS
CONNECT ALL UNUSED
INPUTS TO EITHER
'100 OR 'ISS'
Vss
Fig. 13 -Input leakage current test circuit.
06
DISABLE
D'
01
INHIBIT
0'
O.
D.
0'
••
Vss
TEST CONDITIONS
PIN15
POINT A
TEST
tpHZ
tPLZ
fPZl
tPZH
Vss
Voo
Voo
Vss
Vss
Voo
Voo
Vss
Fig. 14 - Disable delav times test circuit and waveforms.
Dimensions in parentheses are in millimeters and
Bre derived from the basic inch dimensions as
indicated. Grid graduations are in mils (10- 3 inch.)
The photograph and dimensions represen t a chip
when it is part of the wafer. When the wafer;s cut
into chips the cleavage angles are 570 instead of
gOO with respect to the face of the chip. ThtlfB'orB~
the isolated chip is acwa/ly 7 mil. (0.'7 mm}
'ZC:S-2IU'O
Dimensions and Pad Layout for CD4502BH
larger in both dimensions.
289
CD4503B Types
COs/MOS Hex Buffer
Features:
High-Voltage Types (20-Volt Rating)
3-State Non-Inverting Type
The RCA-C04503B is a hex noninverting
buffer with 3-state outputs having high sinkand source-current capability. Two disable
controls are provided, one of wh ich controls
four buffers and the other controls the
remaining two buffers. The C04503B types
are supplied in 16-lead hermetic dual-inline ceramic packages (0 and F suffixes),
16-lead dual-in-line plastic packages (E suffix), 16-lead ceramic flat packages (K suffix),
and in chip form (H suffix).
O'SAILE
1 TTL~oad output drive capability
2 output-disable controls
3-state outputs
Pin compatible with industry types MM80C97,
MC14S03, and 340097
• S-V, 10-V, and 1S-V parametric ratings
• Maximum input current of 1 p.A at 18 V over full
package-temperature range; 100nAat 18 V and 2S'C
• Meets all requirements of JEDEC
Tentative Standard No_ 13A, "Standard
Specifications· for Description of 'B'
Series CMOS Devices"
•
•
•
•
01
,J'-l===:::;!
2
'QI
o. •
O. 6
D4 10
D5 12
06 14
FUNCTIONAL DIAGRAM
. Applications:
• 3'state hex buffer for Interfacing IC's
with data buses
• COS/MOS to TTL hex buffer
D*
N
TRUTH TABLE
214,6,10,12,14)
,...-----1H
ON
OISAIB)
ON
0
I
X
0
0
I
HIGH Z
x•
0
I
(Vo~ -v
DON'T CARE
92C5-32734
Fig. 2-Typlcal n-channel outPUt I~w (sink)
current characteristics.
*ALL
INPUTS PROTECTED
BY COs/MOS PROTECTION
NETWORK
t2CM-5nn
Fig. 1-Logic diagram of 1 to 6 identical buffers.
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY·VOLTAGE RANGE, (VDD)
(Voltages referenced to VSS Terminal) ..... '................................... -0.5 to,. 20 V
INPUT VOLTAGE RANGE, ALL INPUTS ................................... -0.5to VDD '+-0.5 V
DC INPUT CURRENT, ANYONE INPUT ............................................. ±10mA
POWER DISSIPATION PER PACKAGE (PD):
ForTA
-40to +60'C(PACKAGETYPEE) ........................................ 500mW
ForTA
+60to + 85'C (PACKAGE TYPE E) ............. Derate Linearly at 12mWI'Ct0200mW
For TA = -55 to + 100'C (PACKAGE TYPES D, F) ................................... 500 mW
ForTA = + 100 to + 125'C(PACKAGETYPES D, F) ........ Derate Linearly at 12mWI'Cto 200mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
For TA = FULL PACKAGE-TERM PERATURE RANGE (All Package Types) ............... 100 mW
OPERATING·TEMPERATURE RANGE (T A):
PACKAGE TYPES D, F, H .................................................. -55to + 125'C
PACKAGETYPEE ......................................................... -40to +85'C
STORAGE TEMPERATURE RANGE (Tstg) ..................................... -65to + 150'C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1116 ± 1132 inch (1.59 ± 0.79mm) from case for 10 s max .................... + 265'C
=
=
Fig. 3-Minimum n-channel output low (Sink)
current characteristics.
0'
a'
,.
,.
DIS B
O.
13
06
a6
o.
0'
a,
12
O•.
'0
o.
DISA
Vss
'6
VDO
a.
a.
TOP VIEW
uel-SIlII!
TERMINAL ASSIGNMENT
290 ____________________________________________________________-----------
CD4503B Types
DRAIN-lO-SOURCE VOLTAGE IVDSI-V
STATIC ELECTRICAL CHARACTERISTICS
CHARAC·
TERISTIC
Quiescent
Device
Current,
100 Max.
Output
low
(Sink)
Current
IOlMin.
Output
High
(Source)
Current,
IOH Min.
Output
Voltage:
Low·
level,
VOL Max.
Output
Voltage:
High·
level,
VOH Min.
Input low
Voltage,
Vil Max.
Input
High
Voltage,
VIH Min.
Input
Current
liN Max.
3·State
Output
leakage
Current,
lOUT
Max.
LIMITS AT INDICATED TEMPERATURES (OC)
Values at -55, + 25, + 125 Apply to D,F,H Packages
Values at -40, + 25, + 85 Apply to E Package
CONDITIONS
+25
Typ.
MIX.
0.02
0.02
1
2
120
600
-
0.02
0.04
4
20
1.3
3.8
11.2
2.1
5.5
16.1
2.3
6.2
23
-
-1.9
-6.1
-3.7
-14.1
-
0
0.05
0.05
0.05
-
0
0
0.05
0.05
5
4.95
4.95
5
9.95
14.95
1.5
3
4
9.95
14.95
10
15
0.5,4.5
1,9
1.5,13.5
-
10
15
5
10
15
-
5
10
15
3.5
7
11
3.5
7
11
-
0,18
18
±0.1
0,18
0,18
18
±0.4 ±0.4
Vo
VIN
VDD
(V)
(V)
(V)
-55
-40
+85
-
0,5
0,10
5
10
1
2
1
2
30
60
30
60
-
0,15
0,20
15
20
4
20
4
20
120
600
0.4
0.5
1.5
0
0
0
5
10
15
2.6
6.5
19.2
2.5
6.4
18.9
1.4
3.9
11.4
4.6
2.5
9.5
13.5
5
5
10
15
5
5
10
15
-
0,5
5
0.05
0,10
0,15
10
15
0,5
0,10
0,15
+125 Min.
U
N
I
T
S
,..A
Fig. 4-Typical p·channel output high (source)
current characteristics.
DRAIN-TO-SOURCE VOLT••• ,Vo.'·-V
0.5,4.5
1,9
1.5,13.5
-
-1.2 -1.16 -0.7 -0.7 -1.02
-5.8 -5.7 -3.4 -3 -4.8
-3.1
3 -1.9 -1.8 -2.6
-8.2 -8 -4.9 -4.8 -6.8
±0.1
-
rnA
Fig. 5-Minlmum p.channe/'output high (source)
current characteristics.
-
1.5
3
4
-
-
-
V
V
-
±1
±1
-
± 10.5 ±0.1
±12
±12
-
±10·4 ±0.4
,..A
L.OAD CAPACITANCE teL. 1- pF
Sics-unll
Fig. 6- Typical propagation delay time as a
function of load capacitance.
RECOMMENDED OPERATING CONDITIONS
For maximum reliability. nominal operating conditions should be selected so
that operation is always within the following ranges:
CHARACTERISTIC
Supply·Voltage Range (For
Full Package·
TA
Temperature Range)
=
LIMITS
Min.
Max.
3
18
UNITS
"CS-32711t
V
Fig. 7- Typical transition time as a function
of load capacitance.
291
CD4503B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C; Input t r • tf
CL
50 pF. RL
200 kQ unless otherwise specified.
=
=
VDD
CHARACTERISTIC
M
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
Propagation Delay Time:
Low·to·Hlgh, tpLH
Hlgh·to·Low, tpHL
Transition Time:
Low·to·High, tTLH
High-to·Low, tTHL
3·State Propagation Delay Time:
tpHZ, tpZH
tpZL' tpLZ
,
..
z
V',
~ l'\j
.
4
2
~
V
t7k'
1-- c-
o
10
Fig. 10-QuiescenN/evice·current test circuit.
ns
ns
INPUTQVDO
OUTPUTS
V,H
ns
~
'--
:r
V~L'
NOTE:
TEST ANY COMBINATION
OF INPUTS
0
,
10
z
Fig. l1-lnput·voltage test cirCUit.
Ie
cL"15pF---C\.50pF--
4
·i'I·",·rH
6
10
12
.. .. , .. , .
,
92CS-2.744IRI
16 •
l/
1/
1/
V
,,
f5100•
ns
500"F
.~
V •.,· ~.
.iV
•
!;
ns
Vss
.~~V
4
E
50
30
25
35
20
13
70
30
25
90
40
35
ns
1/
~1OK8
z
17
150
70
50
110
50
35
90
45
35
70
40
25
140
60
50
180
80
70
Vss
AMBIENT TEMPERATURE (TAI*25·C
0
I
75
35
25
55
25
INPUTS
o
UNITS
VDD
~
'2
LIMITS
Typ.
Max.
20ns.
III
0
102
FREQUENCY If I-KHz
103
z
I.
Voo
II
14
MEASURE INPUTS
SEQUENTIALLY,
TO BOTH Voo AND Vss'
CONNECT ALL UNUSED
INPUTS TO EITHER
o ~
'10'
Fig. 8- Typical power dissipation as a function
of frequency.
1 N P U·00
O S NOTE'
~
Vss
92CS-32T41
Fig. 9....:.Dynamlc power dissipation test circuit.
Voo OR VSS'
Vss
Fig. 12-lnput current test circuit.
81
Dimensions and pad layout for CD45038H
DimenSions In paren theses are In m""meters and
are derived from the baSIC Inch d,menSIons
m·
dlcated. Grid graduallons are m mils 00- 3 Inch):
as
The photographs and dimensions represent
a chip when it is part of the wafer. When the
wafer is cut into chips, the cleavage angles
are 57° instead of 90° with respect to the
face of the chip. Therefore, the isolated
chip is actually 7 mils (0.17 mm) larger
in both dimensions.
292 __________________________________________________________________
CD4508B Types
COS/MaS Dual 4-Bit
Latch
High-Voltage Types (20-Volt Rating)
The RCA-CD450BB.dual 4-bit latch contains
two identical 4-bit latches with separate
STROBE, RESET, and OUTPUT DISABLE
controls. With the STROBE line in the high
state, the data on the "D" inputs appear at
the corresponding "0" outputs provided the
DISABLE line is in the low state. Changing
the STROBE line to the low state locks the
data into the latch. A high on the reset line
forces the outputs to a low level regardless of
the state of the STROBE input. The outputs
are forced to the high-impedance state for
bus line applications by a high level on the
DISABLE input.
The CD450BB types are supplied in the 24lead dual-in-line ceramic packages (D and F
suffixes), 24-lead dual-in-line plastic packages (E suffix). 24-lead ceramic flat packages (K suffix), and in chip form (H suffix).
The CD4508B is similar to industry type
MC14508.
Features:
• Two independent 4-bit latches
• Individual master reset for each 4-bit latch
• 3-state outputs with high-impedance state for bus
line applications
• Medium-speed operation: tpHL ~ tpLH ~ 70 ns
(typ.) at VDD ~ 10 V and CL ~ 50 pF
100% tested for quiescent current at 20 V
5-V, 10-V, and 15-V parametric ratings
Standardized, symmetrical output characteristics
Maximum input current of 1 IlA at 18 V
over full package-temperature range;
100 nA at 18 V and 25 0 C
• Noise margin (full package-temperature
range) ~
1 Vat VDD ~ 5 V
2 V at VDD ~ 10 V
2.5 Vat VDD ~ 15 V
• Meets all requirements of JEDEC Tentative Standard No.13A, "Standard Specifications for Description of 'B' Series
CMOS Devices"
Setup Time, tsu
Hold Time, tH
009
019
029
RESET ' -_ _ _ _ _ _.J
FUNCTIONAL DIAGRAM
I
-~
-:f30
z
~
GATE-lO-SOURCE VOLlAGE (VGSJ·15 V,.;
25
il
~
• Buffer storage
• Holding registers
• Data storage and multiplexing
3
~
;;
10
,
'0
DRAIN-lO-SOURCE VOLlAGE (VDS)-V
--{l.5 to +20 V
-0.5 to VDD +0.5 V
±10mA
RECOMMENDED OPERATING CONDITIONS at TA ~ 25 0 C, Except as Noted. For maximum
reliability, nominal operating conditions should be selected so that operation is always within the
following ranges:
Strobe Pulse Width, tWIst)
009
019
-
INPUT VOLTAGE RANGE, ALL INPUTS
DC INPUT CURRENT. ANY ONE INPUT
POWER DISSIPATION PER PACKAGE (Pol:
For TA = -40 to +60o C (PACKAGE TYPE EI
. . . . . . . ..
SOOmW
Derate Linearly at 12 mW/oC to 200 mW
For T A = +60 to +85 0 C (PACKAGE TYPE EI
o
. . . . . . . ..
For TA = -55 to +100 C (PACKAGE TYPES D,FI
500mW
Derate linearly at 12 mW/oC to 200 mW
For T A = +100 to +125 0 C (PACKAGE TYPES 0, FI
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types)
100mW
OPERATING·TEMPERATURE RANGE (TA):
PACKAGE TYPES 0, F, H
-55 to +12S o C
PACKAGE TYPE E •
-40 to +85 0 C
STORAGE TEMPERATURE RANGE (T stg )
-65 to +1500 C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch 11.59 ± 0.79 mm) from case for 10 s max,
Reset Pulse Width, tWIRl
RESET
OUTPUT
DlSABL
" 20
(Voltages referenced to VSS Terminal)
~
00.
01'
02.
03.
."
Applications:
DC SUPPLY-VOLTAGE RANGE. (VDDI
Supply·Voltage Range (For TA
Temperature Range)
DISABLE
DDA
DIA
02.
D3A
•
•
•
•
MAXIMUM RATI NGS, Absolute-Maximum Values:
VDD
(V)
CHARACTERISTIC
OUTPUT
Full Package-
LIMITS
Min.
Max.
3
18
5
10
15
200
140
100
-
5
10
15
140
80
70
5
10
15
5
10
15
50
30
20
0
0
0
Fig.2 - Typical output low (sink) current
characteristics.
,
DRAIN-lO-SOURCE VOLlAGE (VDS)-V
Fig.3 - Minimum output low (sink) current
characteristics.
UNITS
V
DRAIN-lO-SOURCE VOLTAGE (VDSJ-V
-
-
-
ns
-
Fig.4 - Typical output high (source) current
characteristics.
293
CD4508B Types
DRAIN-lO-SOURCE VOLTAGE (Vosl-V
STATIC ELECTRICAL CHARACTERISTICS
LIMITS AT INDICATED TEMPERATURES (OCI
VlluHI1-55, +25, +125 Apply to D,F ,H Pickage.
Valul' at -40, +25, +85 Apply to E Pickage
UNITS
+26
VIN VDD
Typ.
+125 Min.
+85
Max.
(VI -&5 -40
(VI
CONDITIONS
CHARACTERISTIC
Vo
(VI
-
Current,
10H Min.
0.42
0.61
1.5
1.1
4
2.8
-0.61 -0.42
-1.8
-1.3
-1.5
-1.1
-4
-2.8
0.36
0.9
2.4
-0.36
-1.15
-0.9
-2.4
0.51
1.3
34
-0.51
-1.6
-1.3
-3.4
1
2.6
6.8
-1
-3.2
-2.6
-6.B
-
-
0
0.05
0
0
5
10
15
0.05
0.05
1.5
3
4
3.5
-
7
7
-
11
11
-
-
±1
-
±10- 5
±0.1
"A
±12
-
±10-4 ±OA
"A
0,5
0,10
0,15
0,5
0,5
0,10
0,15
5
10
15
5
5
10
15
0.64
1.6
4.2
-0.64
-2
-1.6
-4.2
-
0,5
5
0,10
0,15
0,5
0,10
0,15
10
15
5
10
15
-
5
10
15
5
10
15
0,18
18
±0.1
±0.1
±1
0,18
18
±OA
±0.4
±12
0.5,4.5
1,9
1.5,13.5
0.5,4.5
1,9
1.5,13.5
Input Current
liN Max.
-
3-State Output
Leakage Current
lOUT Max.
5
10
20
100
0.4
0.5
1.5
4.6
2.5
9.5
13.5
Output Voltage:
High·Level,
VOH Min.
Input High
Voltage,
VIH Min.
0.04
0.04
0.04
0.08
5
10
20
100
Output Voltage:
Low-Level,
VOL Max.
Input Low
Voltage,
VIL Max.
-
5
10
15
20
IDD Max.
Output High
(Source)
150
300
600
3000
0,5
0,10
0,15
0,20
Current,
Output Low
(Sinkl Current
10L Min.
150
300
600
3000
-
Quiescent Device
0,18
-
5
10
20
100
0.05
0.05
0.05
4.95
9.95
14.95
-
1.5
3
4
3.5
-
- -
-
-
4.95
9.95
14.95
-
-
"
d
-
-
OUTPUT
V55:
RESET DISABLE STROBE
0
0
a
1
a
a
X
1
1
= HIGH
1
1
0
DINPUT
a OUTPUT
1
0
1
0
LATCHED
x
x
x
X
X
Z
LEVE L
a = LOW LEVEL
10
20
30
40
50
60
LOAD CAPACITANCE lell-pf
Fig.
6-
Typical propagation delay time as a func·
tion of load capacitance (strobe to data out).
I~ AMBIENT TEMPERATURE
*'LLIN~SS
PROTECTED BY
COS/MOS PROTECTION
NETWORK
0
x = DON'T CARE
102418,0,246'1022 4t18'032 4S8ut 2 461 ,0 5
INPUT FREQUENCY (f INJ- kHI
92CS-292!t5
Z = HIGH IMPEDANCE
Fig. 7 - Logic diagram (A-Sect;on), 1 of 4 identical/arches with
common output disable. reset. and strobe.
294
Fig. 5 - Typical transition time as a function of
load capacitance.
I
":~~~;.;,~_~________ J :~=r
0
V
I
risr
a
V
l
~
RESET-A
¥~
Fig. 4 - Minimum output high (source) current
characteristics.
'fu~11.9.'"
J
9
*
'o-------~----~----------,
*
mA
- TYPiCAL LArCH - I
VDD
4(6,s,IO)
Dn-A
-
"A
, Fig.
8-
Typical power dissipation as a function
of frequency.
CD4508B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25 0 C; Input t r , tf = 20 ns, CL = 50 pF,
R L = 200 kn, unless otherwise specified.
TEST
CONDITIONS
CHARACTERISTIC
Transition Time,
tTHL, tTLH
Minimum Reset Pulse Width,
tWIR)
Minimum Strobe Pulse Width, tWIst)
Minimum Setup Time,
tsu
Minimum Hold Time,
tH
Reset to Data Out
3·State Propagation Delay Times:
Output High to High Impedance,tpHZ
High Impedance to Output High, tPZH
Output Low to High Impedance, tpLZ
High Impedan·ce to Output Low, tpZL
'Wist)
100
50
40
200
100
80
5
10
15
5
100
70
50
70
40
35
25
15
10
0
0
0
130
70
50
105
60
45
90
50
40
200
140
100
140
80
70
50
30
20
0
0
0
260
140
100
210
120
90
180
100
80
5
10
15
5
10
15
90
50
35
180
100
70
90
50
35
180
100
70
5
10
15
5
10
15
90
50
35
90
50
35
5
180
100
70
180
100
70
7.5
10
Data In to Data Out
CIN
5
10
15
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
Propagation Delay Times: tPH L, tPLH
Strobe to Data Out
Input Capacitance,
LIMITS
Typ.
Max.
VDD
Any Input
-
UNITS
92CS-29296
Fig.9 - Power dissipation test circuit.
INPUTS
o
ns
Vss
Fig. 10 - Quiescent device
current test circuit.
pF
~
~~~8~E
Fig.t1 - Input voltage test circuit.
---j
-+______________-r________________
RESET--____
OUTPUT
DISABLE
t W(R
I
1
~
I
l.-
-J~~-------I
I
~.--~---------.---------------I~--~I-------
'PLH~I Iy.-________
l.-{
Qn OUTPUT ________{I
1
'TLHI f--
'PHL~ 1--1
L.- I
Y
oo
1 N P U VOO
OS
NOTE.
?@-
~::~~:~~~~~~s
\Iss
TO BOTH IJoo AND \Iss'
CONNECT ALL UNUSED
INPUTS TO EITHER
IISS
'
VooORVSS'
I
Fig. 13 -Input current test circuit.
Fig. 12 - Test waveforms.
____________________________________________________________________ 295
CD45088 Types
VDO
TEST AN.,.
OUTPUT
IliA
~o
1
50PF
CHAR.
mrmYeo
Vas
VSS
VDD
, PZL VSS
VDD
f PZH
Vss
'PHZ
9ileS-H2"
tpLZ
VDD
92CS-Z'Z99
Fig. 14 - Output disable test circuit and waveforms.
».===~===!===:;:::==+==::
CLOCK>
RESET
DATA BUS
~
SERIAL OATA
STROBE >-,~-++-+-+-r-t--j-f-f---
DISABLE
FUNC.TION
SEL.ECT
92CM-29300
Fig. 15 - Bus register. ,
,2CM-29301
Fig. 16 - Dual multiplexed bus register with
function select.
RESET A
I·
STROBE A
OUTPUT
DOA
OOA
• c.-tnca
.
2.
22
DISABLE A
21
VDO
0'8
D'8
20
OU
D08
DI A
OIA
"
18
018
DI8
DU
OOA
17
16
•
0 ..
10
15
.'A
"
"13
V••
10
008
008
OUTPUT
ISABLEB
STROBE B
ESETB
TOPYIEW
9ilCS-2T104
DmumSIOIIS 111 parentheses are In millimeters and
an' derived from the basic inch dimensions as indicated. God .9raduatlons are 111 mils (1(J3 inch).
The photographs and dimensions of each COS/MOS .
chip ,represent a chip when it is part of the wafer.
When the wafer is cut into chips,' the cleavage
angles are 57° instead of 90° with respect to the
face of the chip. Therefore. the isolated chip is
actuallv 7 mils (0. 17 mm) larger in both dimensions.
Dimensions and pad lavout for CD4508B.
296
TERMINAL ASSIGNMENT
CD4510B, CD4516B Types
COS/MOS Presettable
Up/Down Counters
High-Voltage Types (20-Volt Rating)
CD4510B - - - BCD Type
The CD4510B and CD4516B can be cascaded
in the ripple mode by connecting the CAR RYOUT to the clock of the next stage. If the
UP/DOWN input changes during a terminal
count, the CARRY-OUT must be gated with
the clock, and the UP/DOWN input must
change while the clock is high. This method
provides a clean clock signal to the subsequent counting stage. (See Fig. 15).
These devices are similar to types MC14510
and MC14516.
The CD4510B and CD4516B Series types
are supplied in 16-lead hermetic dual-inline ceramic packages (0 and F suffixes),
16-leaddual-in-line plastic packages (Esuffix). 16-lead ceramic flat packages(k suffix),
and in chip form (H suffix).
I.
"I.
13
"
"
10
9
CARRY OUT
Vss
01
12
02
,
13
0'
04
• Reset and Preset capability
If the CAR RY-I N input is held low, the
counter advances up or down on each
positive-going clock transition. Synchronous
cascading is accomplished by connecting all
clock inputs in parallel and connecting the
CAR RY-OUT of a less significant stage to
the CARRY-IN of a more significant stage.
I.
2
3
PI
• Synchronous internal carry propagation
The RCA-CD4510B Presettable BCD Up/Down
Counter and the CD4516 Presettable Binary
Up/Down Counter consist of four synchronously clocked D-type flip-flops (with a gating
structure to provide T-type flip-flop capability) connected as counters. These counters
can be cleared by a high level on the RESET
line, and can be preset to any binary number
present on the iam inputs by a high level on
the PRESET ENABLE line. The CD4510B
will count out of non-BCD counter states in a
maximum of two clock pulses in the up
mode, and a maximum of four clock pulses
in the down mode.
PRESET
PRESET
ENABLE
P2
CD4516B - - - Binary Type
ENABLE
O.
P.
PI
CARRY IN
01
Features:
• Medium-speed operation -fCl = 8 MHz typo at 10 V
Voo
CLOCK
03
P3
P2
02
UP/DOWN
RESET
(TOP VIEW)
CD451 DB, CD4516B
TERMINAL ASSIGNMENT
• 100% tested for quiescent current at 20 V
• 5-V, 10-V, and 15-V parametric ratings
• Standardized symmetrical output characteristics
• Maximum input current of 1 p.A at 18 V
over full package temperature range;
100 nA at 18 V and 25°C
• Noise margin (full package-temperature
range): 1 Vat VDD = 5 V
2VatVDD=10V
2.5VatVD D =15V
• Meets all requirements of JEDEC Tentative
Standard No. 13A, "Standard Specifications
for Description of 'B' Series CMOS Devices"
CLOCK
VOO"16
15
VSS'B
10
~
CARRY IN
RESET
CD451 DB, CD4516B
FUNCTIONAL DIAGRAM
92CS-24824
Applications:
• Up/Down difference counting
• Multistage synchronous counting
• Multistage ripple counting
• Synchronous frequency dividers
OPERATING CONDITIONS AT TA = 25°C, Unless Otherwise Specified
For maximum reliability, nominal operating conditions should be'selected so that operation
is always within the following ranges.
Characteristic
VDD
Min. Max. Units
5
' 10
15
150
75
60
5
10
15
-
5
10
15
5
10
15
5
10
15
150
80
60
-
-
15
5
5
Up-Down Setup Time, ts
5
10
15
360
160
110
Preset Enable or Reset Pulse Width, tw
5
10
15
220
100
75
3 18
Supply Voltage Range (At T A = Full Package-Temperature Range)'
Clock Pulse Width, tw
Clock Input Frequency, fCl
Preset Enable or Reset Removal Time-
Clock Rise and Fall Time, trCl, tfCl •
Carry-In Setup Time, ts
-
-
130
60
45
V
-
-
ns
-
2
4
5.5
MHz
ns
p.s
-
-
ns
-
ns
-
ns
-
-Time required after the falling edge of the reset or preset enable inputs before the rising edge
of the clock will trigger the counter (similar to setup time).
*If more than one unit is cascaded in the parallel clocked application, trCl should be made less
than or equal to the sum of the fixed propagation delay at 15 pF and the transition time olthe
carry output driving stage for the estimated capacitive load.
297
CD4510B, CD4516B Types
MAXIMUM, RATI NGS, Absolute·Maximum Values:
AMB'EN~ TEMPERATURE (,TA'*2:i*C
DC SUPPLY·VOL TAGE RANGE, (V DO)
-0.5 to +20 V
~Voltages referenced to VSS Terminal)
-{l.5 to VDD +0.5 V
INPUT VOLTAGE RANGE, ALL INPUTS
±10mA
DC INPUT CURRENT, ANY ONE INPUT
POWER DISSIPATION PER PACKAGE (PO):
0
........ ,
500mW
For T A = -40 to +60 C (PACKAGE TYPE E)
Derate Linearly at 12 mW/oC to 200 mW
For T A = +60 to +850 C (PACKAGE TYPE E)
,
. . . • . . . ..
500mW
For TA = -55 to +1000 C (PACKAGE TYPES D,F)
Derate Linearly at 12 mW/oC to 200 mW
For T A = +100 to +125 0 C (PACKAGE TYPES 0, F)
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
100mW
FOR TA = FULL PACKAGE·TEMPERATURE RANGE (All Package Types)
OPERATING·TEMPERATURE RANGE (TA):
-55
to
+1250C
PACKAGE TYPES 0, F, H
-40 to +85 0 C
PACKAGE TYPE E .
-65 to +1500 C
STORAGE TEMPERATURE RANGE (T;tg)
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ±O.79 mm) from case for 10 s max.
GATE-lO-SOURCE VOLTAGE (VGSI*15 V
,ov
g
~ 10
g~ ,
,v
5
10
15
DRAIN-TO-SOURCE VOLTAGE (Vosl-V
Fig. ~ - Typical output low (sink) current
characteristics.
AMBIENT TEMPERATURE
p,*
4
~R~OUTC7r-----------,
."'~~
PROTECTED BY
COS/MOS
I
DR,.IN·'m·"ou,,,, VOLTAGE (Vasl-V
Fig.2 - Minimum output low (sink) current
characterist;cs.
v...
DRAIN-lO-SOURCE VOLTAGE {Vosl-V
·~S
PROTECTION NETWORK.
-15
-10
-5
AMBIENT TEMPERATURE (TAI-25"C
H+H+tw,*",7'±""""
GATE-lO-SOURCE
VOLTAGE (VGS)=-5V
-5
•f
~
-IO~
~
-15 ~
-IOV
a
-20~
-ISV
Fig.3 - Logic Diagram for CD4510B.
Fig.4 - Typical output high (source) current
characteristics.
DRAIN-lO-SOURCE VOLTAGE (Vosl-V
.. '
:,'~:
"
'I~'~
,
'~H
1i::iI:m:L
I
:1;;:J:"i
000
LOAD CAPACITANCE ICLI-pF
If
~
0..
100
i--_·t-·-+,==Id...J-"l=l"""r:::P=bl---hP
i.·-,+:,Il-4--
50
'.J: ~_1:
w
o
..~J:~~
~
00
00
100
LOAD CAPACITANCE (CLl-pF
Fig. 7 - Typical propagation delay time vs.
Fig.5 - Minimum output high (source) current
characteristics.
Fig.6 - Typical transition time vs. load
capacitance.
load capacitance for clock-to-Q
outputs.
298 ________________________~------------------------------~--------
CD4510B, CD4516B Types
STATIC ELECTRICAL CHARACTERISTICS
LIMITS AT INDICATED TEMPERATURES (OC)
Valu •• at -55, +25, +125 Apply to D,F ,H Packa"".
Value. at -40, +25, +85 Apply to E Pickage
CONDITIONS
CHARACTER·
ISTIC
Quiescent Device
Current,
100 Max.
Output Low
(Sink) Current
IOLMin.
Output High
(Source)
Current,
IOH Min.
Output Voltage:
Low·Level,
VOL Max.
Output Voltage:
High.Level,
VOH Min.
Input Low
Voltage,
VIL Max.
Input High
Voltage,
VIH Min.
Input Current
liN Max.
Vo
(V)
0.4
0.5
1.5
4.6
2.5
9.5
13.5
-
-
0.5,4.5
VIN VDD
(V)
(V)
-40
+85
+125
Min.
5
10
20
100
150
300
600
3000
150
300
600
3000
-
0.42
0.36
0.9
2.4
-0.36
-1.15
-0.9
-2.4
0.51
1.3
3.4
-0.51
-1.6
-1.3
-3.4
0,5
0,10
0,15
0,20
5
10
15
20
5
10
20
100
0,5
0,10
0,15
0,5
0,5
0.10
0,15
5
10
15
5
5
10
15
0.64
0,5.
5
0,10
0,15
0,5
0,10
0,15
10'
-
1.5,13.5
-
-
0,18
18
-
0.61
1.5
1.6
4.2
4
-0.64 -0.61
-2
-1.8
-1.6 -1.5
-4
-4.2
1.1
2.8
-0.42
-1.3
-1.1
-2.8
0.05
0.05
0.05
4.95
9.95
14.95
15
5
10
15
5
10
15
5
10
15
1,9
1.5,13.5
0.5,4.5
1,9
-55
±0.1
±0.1
-
+25
Typ.
Max.
0.04
0.04
0.04
0.08
5
10
20
100
1
2.6
-
6.8
-1
-3.2
-2.6
-6.8
-
vs. supply voltage.
-
•
i
0.05
g
~ ••
-
3.5
-
7
7
-
11
11
-
±10- 5
±0.1
-
-
-
-
-
---CL-15pF
2
II
·,
~
~
if
10'
ill •
"'" •
-
1.5
3
4
CL :50 pF
10'
V
4
~.
I
II
I IIJ
+HI_~
J/-P ..p
...
~
~
#.
/
.,
i~
-l17
,
J.rX
10
V
2S-C
t ro lf·20ns
4
0.05
0.05
{TA1~
AMBIENT TEMPERATURE
10,
~
0
-
W
92CS·2T006
rnA
0
0
5
10
15
-
~
SUPPLY VOLTS-VOO
4.95
9.95
14.95
~
5
Fig.8 - Typical maximum clock input frequency
-
-
±1
p.A
-
1.5
3
4
3.5
±1
UNITS
0.1
.6. I
2
468'0 2. 4 6~02 2. 468 103
CLOCK INPUT FREQUENCY (fCL1- kHz
,
46.104
92CS·21007
Fig.9 - Typical dynamic power dissipation
vs. frequency.
p.A
INPUTS
o
vss
PRESET* I
ENABLEV1rr"1---'
Vss
~RRYOUT97~----------'
Fig. 1 t - Quiescent-device-current test circuit.
."'~
PROTECTED BY
v..s
COS/MOS
.;;)
PROTECTION NETWORK.
OD
VD D
INPUOS
V
~
NOTE:
~i~~~:i,!~~~~S
Vss
TO BOTH Voo AND VsS'
CONNECT ALL UNUSED
INPUTS 10 EITHER
Voo OR vss'
vss
Fig. 10 - Logic Diagram for CD4516B.
Fig. 12 -Input-current
test circuit
299
CD4510B, CD4516B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C. Cl = 50 pF.
Input t r• tf = 20 ns. Rl = 200 kQ
-
ConditVDD
(V)
INPUTQVDOOUTPUTS
,-.
~
Limits
ions
Characteristic
Min_
Typ_
V,H
Units
All Packages
J
V~L
Max_
Propagation Delay Time (tPHl. tplH):
NOTE:
-
5
10
15
Clock-to-Q Output (See Fig. 10)
Preset or Reset·to-Q Output
5
10
15
Clock-to-Carry Out
5
10
15
Carry-In-to-Carry Out
5
10
15
400
200
150
ns
210
105
80
420
210
160
ns
240
120
90
480
240
180
ns
125
60
50
250
120
100
ns
320
160
125
640
320
250
ns
-
100
50
40
200
100
80
ns
2
4
5.5
4
8
II
-
-
5
7_5
-
-
-
5
10
15
Preset or Reset-to-Carry Out
Transition Time (tTHl. tTlH) (See Fig. 9)
5
10
15
Max. Clock Input Frequency (fCl)
5
10
15
TEST ANY ONE INPUT,'
200
100
75
-
-
-
Input Capacitance (CIN)
Vss
WITH OTHER INPUTS AT
Voo ORVss'
Fig_ 13 - Input-voltage
test circuit.
l i20", .1f20",
50%
~
%VDD
~
VARIABLE
WIDTH
MHz
-
Fig. 14 -
pF
~ 'O"'V
Power-di~sipation
55
test circuit and
input waveform.
uw~>----~-----------------=;:=:~~==~-------.--------------.
=:~~~~
>-----+---.-----------------j--.---------------+......-----------+
C.1
RESET
C04510/16
>_----~--
C.O.
C.I.
CD4510/16
C.O
C. I",
C04510116
C.D.
...
________________------------------.4----__________
_+
~OO~>_----~----------------~~======~--------4r-------------+
~>-----+_~--------------__l--~--------------4-......-----------+
C: L9C K
>-----+--+----------'-1
RESET
>-____
.L-========::::Jt:=====:...:=__l._____________
RIPPLE CLOCKING MODE,
'T1£ UP/DOWN CONTROL CAN BE CHANGED AT ANY COUNT. THE ONLY RESTRICTION ON CHANGING
THE lF/DOWN CONTROL IS THAT TI£ CLOCK INPUT TO THE FIRST COUNTING STAGE MUST BE ·HIGH~
Fig. IS - Cascading counter packages.
300 ____________________________________________________________________
CD4510B, CD4516B Types
CLOCK
CARRY
"l..."l...
iN
r-r- r-rL r-r- !"Lit- "l..."l... l.:rt "l..."l... r-t-r-t- r.: r-r-r-r-
r-r-
UP/DOWN
RESET
PE
,
n_
L
CL CI
·X
r-
.I
X
X
X
X
,
10
f-- f-=f-- f-'-f-- f--
,- -
02
r- -
f-- r-'-- '-- 'c...
,
- - ~ f-- f-- -f::
o
,
IU
2
,
4
6
5
7
•
9
'-'
•
7
6
5
4
2
,
o
,
0
0
0
1
X
X
X
R ACTION
0 NO COUNT
0 COUNT UP
o COUNT DOWN
0 PRESET
1 RESET
20
40
50
60
70
80
90
100
'-
C-
F F=
04
PE
X
1
0
TRUTH TABLE
P4
'- r-f-- r- c...r-
U/D
x - DON"T CARE
r--;r---
P2
COUNT
1
0
0
.r
'-
-- 6
9
0
7
0
Fig. 16 - Timing Diagram for CD4510B.
CL.OCK
CARRY
iN
r- rL rL r- r- rL r- rL r-t- r-t r-t- rL r-t- rL r-t-r-tL
rL
r-t-r-t-r-t-
rL L
Ir
UP/DOWN
it- ;--
RESET
PE
h
h
P'
Voo
PZ
Vss
92CS-27031RI
P,
P4
0'
r-
02
= =
I--
~04
'-- 03
I--
;--
f-If-- Il-
-
-
I--
I-
-
f:: -
l-
CARRY OUT
COUNT
•
•
7
•
9
10
II
12
13
14
-
15
Dimensions and Pad Layout for CD4510BH.
I--
'--
- - 9
•
r-
r-
- f:: f-- --
I--
l-
f::
r-
I--
l - I-I'-- l - I-
II--
7
6
5
4
,
2
,
.r it- l o
0
15
Fig. 17- Timing diagram for CD4516B.
l
pARALLEL
DATA
OUTPUTS
ANALOG
DATA
INPUTS
CLOCK
PRESET
ENABLE:
This acquisition system can be operated in
the random access mode by jamming in
the channel number at the present inputs, or
in the sequential mode by clocking the
CD4516B.
Fig. 18 - Typical 16-channel, 1o-bit data aquisition system.
Dimensions and Pad Layout for CD4516BH.
The photographs and dimensions of each COS/MOS
chip represent a chip when it is part of the wafer.
When the wafer is cut into chips, the cleavage
ilngles are 57° instead of 90° with respect to the
face of the chip. Therefore, the isolated chip is
actually 7 mils (0. 17 mm) larger in both dimensions.
Dimensions in paren theses are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10- 3 inchJ.
_______________________________________________________________________ 301
CD4511B Types
COS/MOS BCD-to-7 -Segment
Latch Decoder Drivers
acD
T',
High-Voltage Types 120-Volt Rating)
B'·
l :,.~
DISPl.AY
..,
lZlW2131'1lsibI7ISI'11
c
92CS-2S087
C
H
o•
LE/i'f'Rm 5
The C04511Btypes are BCO-to-7-segment
latch decoder drivers constructed with COS/
MaS logic and n-p-n bipolar transistor output devices on a single monolithic structure.
These devices combine the low quiescent
power dissipation and high noise immunity
features of RCA COS/MaS with n·p·n bipolar output transistors capable of sourcing
up to 25 mAo This capability allows the
C04511B types to drive LED's and other
displays directly.
Lamp Test (IT), Blanking (i3C), and Latch
Enable or Strobe inputs are provided to test
the display, shut off orintensity-modulate it,
and store or strobe a BCD code, respectively.
Several different signals may be multiplexed
and displayed when external multiplexing
circuitry is used. The CD4511 B is supplied
in 16-lead hermetic dual-in-line ceramic
packages (0 and F suffixes), 16-lead dualin-line plastic packages (E suffix), 16-lead
ceramic flat packages (K suffix), andin chip
form (H suffix).
These devices are similar to the type
MC14511.
I.
I.
C
16
2
LT
I.
LEISTROBE
I."
at
D
Voo
"
•
Featur;es:
Vss ·8
IIOD"16
•
•
•
•
High-output-sourcing capability •.••••.. up to 25 mA
Input latches for BCD Code storage
Lamp Test and ~Ianking capability
7-segment outputs blanked for BCD input codes> 1001
• 100% tested for quiescent current at 20 V
• Max. input current of 1 pA at 18 V, over
full package-temperature range, 100 nA
at 18 V and 25°C
• 5-V, 1a-V, and 15-V parametric ratings
FUNCTIONAL DIAGRAM
Applications:
• Driving common-cathode LED displays
• Multiplexing with common-cathode LED
displays
• Driving incandescent displays
• Driving low-voltage fluorescent displays
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (V DD )
(Voltages referenced to Vss Terminal)
-(1.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS
-(1.5 to VOD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT
±lOmA
POWER DISSIPATION PER PACKAGE (PO):
o
For T A • -40 to +6O C (PACKAGE TYPE E) •
• • • • • • • ••
500mW
For T A • +60 to +85o C (PACKAGE TYPE E)
• •
Oerate Line.rly.t 12 mW/oC to 200 mW
For TA S -55 to +l000C (PACKAGE TYPES D,F)
• • • • • • • ••
500mW
Derate Linearly at 12 mW/oC to 200 mW
ForTA· +100 to +1250 C (PACKAGE TYPES 0, FJ
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA· FULL PACKAGE-TEMPERATURE RANGE (All Package Types)
100mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPES D. F. H
-55 to +1250C
-40 to+850C
PACKAGE TYPE E • • • • • • • • • • • • • • •
STORAGE TEMPERATURE RANGE (Tstg ) • • • • • • • •
-65 to +1500C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ±0.79 mm) from case for 10 s max.
10
V55
OPERATING CONDITIONS AT TA = 25°C Unless Otherwise Specified
TOP VIEW
92CS-25084RI
CD4511B
TERMINAL ASSIGNMENT
For maximum reliability, nominal operating conditions should be selected
so that operation is always' within the following ranges
VOD
Min.
Max.
Units
-
3
18
V
Set·Up Time (tsl
5
10
15
150
70
40
ns
ns
ns
Hold Time (tH?
5
10
15
0
0
0
Strobe Pulse Width (tW)
5
10
15
400
160
100
-
Characteristic
Supply· Voltage Range (TAl:
(Full Package-Temperature Rangel
302
ns
ns
ns
ns
ns
ns
CD4511B Types
STATIC ELECTRICAL CHARACTERISTICS
Conditions
Limits at Indicated Temperatures (OC)
V~lues
at -55, +25, +125 for D, F, H Packages
Values at -40, +25, +S5 for E Packages
Characteristic
IOH
V,N VDDI--:..:r=:..::.-=r:::C~:::"~~~;':':::::~:!"+"2"'5~---j Units
(mA)
(V)
Quiescent Device
Current: I DO
Max.
(V)
-55
-40
10
15
20
10
20
100
10
20
100
+S5
+125
300
600
3000
300
SOO
3000
Min.
Typ.
0.04
0.04
O.OS
Max.
10
20
100
I1A
Output Voltage:
0,5
0.05
0
0.05
Low· Level VOL 1-_1-_-t-;;o'-;,I-;ot-;I-;o'--t_ _ _ _ _o;;:.-;;0~5----+-=:...-+_~0;_~0~.0~5~ V
Max,
0,15 15
0.05
0
0.05
I
I
DRAIN-TO-SOURCE VOlTAGE IVos)-V
Fig. 1 - Typical output low (sink) current
characteristics.
I
0,5
4
4
4.2
4.2
4.1
4.55
High· Level Va H I--I---t-;;O,-;'1-;0t-;I-;0'--t--;:-9;.-t---;,;9;--t--f9f·2~t-:~9.~2:;--f--:9"::'-cl:-+-:-9;-,'5",5~_=--i V
Min.
0.1515
14
14
14.2
14.2
14.1
14.55
Input Low
Voltage, V, L
0.5,3.S
1,8.8
1.5
1.5
3
10
Max,r--t.l~.5~,1~3~.8~-~1~5~-----~4;-----~-=~+--=~+-~4~
0.5,3.8
3.5
3.5
f--~t.-;:-I:.;,8:;.:;:8:t-_+-l:.;0~_ _ _ _ _---C'-:-_ _ _ _--j_-I--+_-=---j:--=-Voltage, VI H
Min.
1.5,13.S
15
11
11
V
Input High
15
20
25
4.0
4.0
4.20
4.20
4.10
3.S0
3.80
3.90
3.50
3.90
3.50
3.90
3.55
3.40
3.55
3.40
3.40
3.10
9.0
9.0
9.20
9.20
9.10
8.S5
8.85
9.00
9.00
9.00
8.70
8.S0
8.70
8.60
8.40
8.40
8.S0
8.30
14.0
14.0
14.20
14.20
14.10
13.90
13.90
14.0
14.0
14.0
13.75
13.S5
13.75
13.65
13.50
13.50
13.70
13.50
Output Dnve
Voltage:
f-'1",0-+ _ _-+_-I
High Level VOH f-'1",5-+ _ _-+_-I 10
Min. 1-'=2",0-+_ _-+_-1
25
10
1-'=~7~~ +-~11
5
__
25
Output Low
(Sink) Current,
IOL
Min.
Input
0.5
1.5
0,10 10
0,15 15
18
I.S
4.2
1.5
1.1
0.9
4
2.8
2.4
±a.l
±a.l
±1
±1
1.3
3.4
AMBIENT 7EMPERATURE (TA )·2$·C
SO
75
LOAD' CAPACITANCE eeL )-pF
100
92.C5-27077
Fig, 2 - Typical data·to-output, low-to·high·level
propagation delay time as a function of
load capacitance.
V
14.55
14.30
14.20
14.10
13.95
13.80
V
2.S
6.8
25
V
9.55
9.25
9.15
9.05
8.90
8.75
r-__r-~0~.4~~0~,~5~~5-+~0~.6~4~~0.~S~I-+~0~·742~~0~.3~S~~0~.5~1~~1~-+__~
0,18 0,18
Current, lIN
4.55
4.25
4.10
3.95
3.75
3.55
V
~
~
75
LOAD CAPACITANCECCL l-pF
rnA
100
Fig. 3 - Typical data·to-output, high·to·low-Ievel
propagation delay time as a function of
load capacitance.
±10- 5 ±a.l
Max.
10
Z5
50
75
LOAD CAPACITANCECCL l-pF
Fig.
100
92CS-27079
4 - Typicallow-to-high-leve! transition time as
a function of load capacitance.
_____________________________________________________________________ 303
CD4511B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 2SoC. Input t r • tf = 20 ns.
CL = 50 pF. RL = 200 kn
CHARACTERISTIC
Test
Conditions
LIMITS
All Packages
UNITS
VDD
Volts
Min.
Typ.
Max.
Propagation Delay Time:
(Data)
High·to·Low Level. tpHL
5
10
15
-
520
210
150
1040
420
300
ns
Low·to·High Level. tpLH
5
10
15
-
660
260
180
1320
520
360
ns
350
175
125
700
350
250
ns
400
175
150
800
350
300
ns
15
-
5
10
15
-
-
250
125
85
500
250
170
ns
150
75
50
300
150
1()0
ns
40
30
ns
25
80
60
50
310
185
160
ns
-
(BL)
High·to·Low Level. tpHL
5
10
15
Low·to·High Level. tpLH
10
Propagation Delay Time:
5
Propagation DelayTime:
(LT)
High·to-Low Level. tpHL
5
10
15
-
Low-to-High Level, tTLH
5
10
15
-
High-to-Low Level, tTHL
5
10
15
-
125
75
65
Minimum Set-Up Time, ts
5
10
15
150
70
40
75
35
20
Minimum Hold Time, tH
5
10
15
0
0
0
-75
-35
-20
Strobe Pulse Width, tw
5
10
15
400
160
100
200
80
50
Low-to·High Level, tpLH
Transition Time:
-
-
LOAD CAPACITANCEICL)-pF
Fig.
92C$-27080
5 - Typical high-ta-Iow trtlnsition time as a .
function of load CBpacitance.
. AMBIENT TEMPERATURE eTA 1-25-C
o
os
SUPPLY VOLTAGE -OUTPUT DRIVE VOLTAGE I Yeo-VOM I-V
92C5-U081
Fig. 6 - Typical voltage drop (VDO to output) ...
outpUt soulCe current as a function of
supply.
ns
ns
ns
Iii'
Input Capacitance, CIN
304
-
5
7.5
pF
92.C5-21082
Fig. 7 - Typical dynamic power dissipation characteristics.
CD4511 B Types
.
TRUTH TABLE
Fig. 8 - Logic diagram.
INPUTS
r--L--,
a
INPUTS
VIH
o
Vss
'-
81
LT
0
B
A
b
,
d
X
X
0
X X X
X
1 I
I
I
x
0
1
X X X
X
o
o
0 0 0 0 Blank
0
1
1
0
0
0
0
11
1 1
1
1 0
0
1
1
0
0
0
1
o
1
1
a
0
0
a
I
0
1
1
0
0
1
0
1 1
0
1
1 0
1
~
0
1
1
0
0
1
1
11
1 1
o
0
1
3
0
1
1
0
1 0
0
o
1
o
0
1
1
0
1
1
0
1 0
1
1 0
1 1 0
1 1
5
0
1
1
0'
1
1
0
o
1 1
1
1
1
b
0
1
1
0
1
1
1
11
1
a
0
0
a
0
1
1
1
o
0
0
11
1 1
1
1 1
7
8
0
1
1
1
o
0
1
11
1
o
0
1 1
0
1
1
1
0
1
0
0
o
0
o
0
0
Blank
0
1
1
1
0
1
1
0
000
o
0
Blank
0
1
1
1
1 0
0
0
o
0 000
Blank
0
1
1
1
1 0
1
0
o
0 0 0 0 Blank
0
1
1
1
1
1
0
0
1
1
1
1
1
1
o
o
0 0 0 0 Blank
0
o
o
o
o
o
o
1
1
1
X
X X
X
C
0
1
0
0
1
f
9
Display
1
1
8
0 000
0
..,
'I
Blan~
*
I
*
*,Depends on BCD code previously
applied when LE = 0
X==Don'tCare
Note: Display is blank for all illegal input.codes (BCD> 1001).
vro
TEST CIRCUITS
.
LE
OUTPUTS
~
l
V~L
NOTE:
'ISS
Vss
(JVDO
Fig. 9 - Quiescent device current.
INPUTS
VDO
~~srN~~~OM8INATION
Fig. 70 - Input voltage.
J
92CS-2~08!l
NOTE:
?0-
~i;~~:;I~~~~~S
Vss
I, ,If -20nl
TO BOTH Voo AND VSS
CONNECT ALL UNUSED
INPUTS TO EITHER
'100 OR 'ISS'
V""
20", V-i==------V
W
Fig. 11 - Input current.
gO %
50%
r - - - - - - , Voo
LE
10%
VI-
r-- ---r-
Voo
t SU
90"IO
DATA
INPUTS
~
Soa
10%
_
t HOLD
MEASURE OUTPUT d FOR I PLH
MEASURE OUTPUT Q FOR IpHL
r
Fig. 12 - Data propagation delay.
. . 50%
V5S
FOR SETUP
VOO---,--
"
''''-"'''-0
~';.~tw~
VSS
92CS-27088RI
VOO
-12
= ·.::~r V··
50PF
o
=f
_ ___ -" _____ 0
20 ns
Vss
OO
92CS-27086RI
Fig. 13 - Dynamic power dissipation.
I, .', -20nl
92CS- 2S086RI
Fif}. 14 - Dynamic waveforms.
________________________________________________________________________ 305
CD4511B Types
LTIi VDD
APPLICATIONS
Interfacing with Various Displays
A -.:- -
~
c.J
-1('0'-_ _ _ _ _ _ _---.,
I~.----------,
D.J
I
:r.
I
E
I
DO
I
I
I
iss
=
l
92CS- 27091RI
A medium--brightness intensity display can be
obtained with "low-voltage fluorescent displays
I
I
I
I
,':-"'----.../ \
D~~tIJ
I
I
I
oLi
TO
-,
.LIi
v
r--------l
such as the Tung-Sol Digivac S/G**
~erles_
··Trademark Tung-Sol Division Wagner Electric Co.
Fig. 16 - Driving low-voltage fluorescent displays.
I
I
I
I
I
I
I
CD4511
__ J
I
I
L ______ _
I
LED 7-SEGMENT
DISPLAY
9ZCS- 27089RI
Duty Cycle = 100%
ISEG
= IDIODEAVG_ = 20 mA at Luminous Intensity/Segment = 250 microeandles
R= VOH-VDF
2 of 7 Segments Shown Connected
ISEG
Resistors R from V OD to Bach 7 ..egment driver
output are chosen to keep all Numitron segments
51 ightly on and warm.
Fig. l' - Driving incandescent displays (RCA
Numitron DR2000 series display.)_
Fig_ 15 - Driving common-cathode '-segment LED displays (example Hewlet-Packard 5082-7740)_
----,
A
,--.j
l.!!....:
c-l
I,
~
I.
o-...l
I
20
40
60
80
100
I
I
r.-
LE----i
voo
I
I
I
I
I
LiL~451~ rr.-,":+'V\RI'vf""1""-+-'I--i-~-f-i-Hr--+-H--'
I
£Os T"
I
v••
Multiplexing Scheme Showing 2 of 7 Segments Connected
92CM-27081RI
Transistors T 1-T4 IRCA-2N3053 or 2N2102) have Ie Max.rating >7xISEG
92CM-32873
Dimensions and pad layout for C045118 chip.
Duty Cycle = 25%
ISEG = [IDIODEAVGI x 4
R
= (V OH -
V DF - V CE )
ISEG
All unused inputs on CD4555
are connected to VOO or VSS.
Fig. 18 - Multiplexing with common-cathode 7-segment LED displays (example Hewlet-Packard 5082-7404
4 character display or 4 discrete Monosanto Man 3 displays).
306
The photographs and dimensions of each COS/MOS
chip represent a chip when it is part of the wafer.
When the w~f~r is cut intoo Ch!ps, the cleavage
angles are 57 Instead of 90 WIth respect to the
face of the ~hip. Therefore, the isolated chip is
actually 7 mils (0. 17 mm) larger in both dimensions.
Dimensions in parentheses are in millimeters and am
derived from the basic inch dimensions 85 indicated.
Grid graduation. are in mil. (10- 3 inch)_
CD4512B Types
COS/MOS 8-Channel
Data Selector
High-Voltage Types (20-Volt Rating)
The RCA-CD4512B is an 8-channel data
selector featuring a three-state output that
can interface directly with, and drive, data
lines of bus-oriented systems.
The CD4512B-series types are supplied in
16-lead hermetic dual-in-lineceramic packages (0 and F suffixes), 16-lead dual-in-line
plastic packages (E suffix), 16-lead ceramic
flat packages (K suffix), and in chip form (H
suffix).
Features:
• 3-state output
• Standardized, symmetrical output characteristics
.100% tested for quiescent current at 20 V
.5-V, 10-V, and 15-V parametric ratings
• Maximum input current of 1 p.A at 18 V over full packagetemperature range; 100 nA at 18 V and 2s"C
• Noise margin (over full package-temperature range):
1 VatVDD= 5V
2VatVDD=10V
2.5 Vat VDD = 15 V
OP~RATING
INHIBIT---~
10
,.
00-'
1
01-2
02-3
CHANNEL 03-4
INPUTS
D4-5
14 SELECT
OUTPUT
05-6
D6-7
~g~~i1L
D7-9
A-II
{ 8-12
VOD a l6
vss·,
C-13
CD4!5'!.
• Meets all requirements of JEDEC Tentative
Standard No. 13A, "Standard Specifications
for Description of 'B' Series CMOS Devices"
FUNCTIONAL DIAGRAM
Applications:
• Digital multiplexing
• Number-sequence generation
• Signal gating
RECOMMENDED
3-STATE DISABLE
DO
.01
2
D2.5
D3..
D4
5
D5.
0&
7
CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges:
LIMITS
CHARACTERISTIC
MIN.
MAX.
3
1B
Supply-Voltage Range (For T A = Full Package
Temperature Range)
vs.
UNITS
'1
15
14
13
12
II
10
".';TO;;;P....,V:::'EW;::.fl
VOO
3-STATE DISABLE
SEL. OUTPUT
C
8
A
INHIBIT
07
TERMINAL ASSIGNMENT
V
TRUTH TABLE
C 13
SEL. CONT.
*
voo
J
'
A
B
C
0
1
0
1
0
1
0
1
X
0
0
1
1
0
0
0
0
0
1
1
1
1
X
X
0
1
1
X
x
x
ELECT
OUTPUT
I = High Level
14
X = Don·t care
INH
0
0
0
0
0
3-STATE
SEL
DISABLE OUTPUT
0
0
0
0
0
0
0
0
0
0
0
1
0
X
1
DO
01
02
03
04
05
06
07
0
High Z
0= Low Level
.
1
vss
.
g"DD
* BY
ALL INPUTS ARE PROTECTED
CDS/MOS PROTECTION
NETWORK
Fig. 1 - Logic diagram.
LOAD CAPACITANCE (CL)-pF
Vss
Fig.
2 - Typical transition time as a function
of load caoacitance.
307
CD4512B Types
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (V DD )
. • -0.5 to +20 V
(Voltages referenced to VSS Terminal!
-0.5 to V DD +0.5 V
INPUT VOLTAGE RANGE, ALL INPUTS
±10mA
DC INPUT CURRENT, ANY ONE INPUT
POWER DISSIPATION PoER PACKAGE (P D ):
• . • . . _ . •.
500mW
For T A = -40 to +600 C (PACKAGE TYPE E)
Derate Linearly at 12 mW/oC to. 200 mW
For T A = +60 to +B5
(PACKAGE TYPE E) - . . • . . . . ..
500mW
For T A = -55 to +100
(PACKAGE TYPES D, F)
Derate Linearly at 12 mWt"C to 200 mW
For T A = +100 to +125 C (PACKAGE TYPES D, F)
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
100mW
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types)
OPERATING-TEMPERATURE RANGE (T A):
-55 to +125°C
PACKAGE TYPES D, F, H
-40 to +B5°C
PACKAGE TYPE E
-65 to +150oC
STORAGE TEMPERATURE RANGE (T,,)
_ .
LEAD TEMPERATURE (DURING SOLD~RING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max.
'i.
!?
STATIC ELECTRICAL CHARACTERISTICS
LIMITS AT INDICATED TEMPERATURES (OC)
CHARACCONDITIONS
Values at --55, +25, +125 Apply to D,F ,H Packages
TERISTIC
Values at -40, +25, +85 Apply to E Package
+25
Vo
VIN VDO
(V)
(V) (V) -55 -40
+85 +125 Min. Typ. Max.
Quiescent
Device
Current,
IDO Max.
-
0,5
5
5
5
150
150
-
0.04
0,10
10
10
10
300
300
0.04
-
0,15
15
20
20
600
600
-
0,20
20
100
100
3000
3000
-
0.64
0.61
0.42
0.36
0.04
0.08
0.4
Output Low
(Sink) Current 0.5
IOL Min.
1.5
0,5
5
0,10
10
1.6
1.5
1.1
0.9
1.3
2.6
0,15
15
4.2
4
2.8
2.4
3.4
6.8
4.6
0,5
5 -0.64 -0.61
2.5
0,5
5
-2
-1.8
-0.42 -0.36 -0.51
-1.3 -1.15 -1.6
-3.2
. Output High
(Source)
Current,
IOH Min.
Output Voltage:
Low-Level,
VOL Max.
Output
Voltage:
High-Level,
VOH Min.
Input Low.
Voltage
VIL Max.
Input High
Voltage,
VIHMin.
0.51
1
-1
5
10 p.A
20
100
current characteristics.
-
DRAIN-lO-SOURCE VOLTAGE IVosl-V
m.tl
0,10
10
. -1.6
-1.5
-1.1
-0.9
-1.3
-2.6
0,15
15
-4.2
-4
-2.8
-2.4
-3.4
-6.8
-
.0,5
5
0.05
-
0 0.05
0,10
10
0.05
-
0 0.05
0,15
15
0.05
-
-
0,5
5
4.95
4.95
0 0.05 V
5 -
-
0,10
10
10
15
9.95
14.95
9.95
0,15
14_95
15
1.5,13.5
0.5,4.5
1,9
1.5,13.5
-
5
3.5
3.5
-
10
7
7
-
-
15
11
11
-
5
1.5
10
3
15
4
-
Input Current
liN Max.
-
0,18
18
±0.1
±0.1
±1
±1
3-State
Output
Leakage
Current
lOUT Max.
0,18
0,18
18 ±O.4
±0.4
±12
±12
DRAIN-lO-SOURCE VOLTAGE IVOsl-V
Fig. 4 - Minimum output low (sink)
9.5
1,9
current characteristics.
U
N
I
T
S
13.5
0.5,4.5
I
ORAIN-TO-SOUACE VOI..TA.GE IVDS1-V
Fig. 3 - Typical output low (sink)
-
Fig. 5 - Typical output high (source)
current characteristics.
1.5
DRAIN-lO-SOURCE VOLTAGE (VoSl-V
3
4 V
-
±10- 5 ±0.1 p.A
-
-
±10-4 ±0.4 p.A
Fig. 6 - Minimum output high (source)
,
---
current characteristics.
308 _____________________________________________________________________
CD4512B Types
.,
DYNAMIC ELECTRICAL CHARACTERISTICS at TA =25°C, Input tr,tf = 20 ns,
CL = 50 pF, RL = 200 kU
TEST CONDITIONS
CHARACTERISTIC
Propagatio·n Delay Time, tpHL, tpLH
Inhibit to Output
"A" Select to Output
Data to Output
3·State Disable Delay Time:
tpZL' tpLZ' tpHZ' tpZH
Transition Time, tTH L, tTLH
LIMITS
1O:;': AMBIENT TEIIFERATURE (TA)'25"C
UNITS
VDD
(V)
Typ.
Max.
5
10
15
140
70
50
280
140
100
5
10
15
200
85
60
400
170
120
5
10
15
180
75
55
360
150
110
5
10
15
60
30
20
120
60
40
ns
5
10
15
100
50
40
200
100
80
ns
5
7.5
pF
Input Capacitance, CIN
(Any Input)
I
,
~
.
ill
~
q)'~
2
•
,
is
.,
102
10
2
..d1
"~
~'OUTPUTS
V,M
'-
~
:t
V~L
NOff:
Vss
~'TN~u~~ONaINATION
92CS-27441AI
Fig. 12 - Input voltage test circuit.
1 - - - - - - (I.9~~:~.,OBI--------I
- Dimensions and pad layout'''01- CD4512BH
_______________________________________________________________________ 309
CD4514B, CD4515B Types
COS/MOS 4-Bit Latch/4-to-16
Line Decoders
Features:
High-Voltage Types (20-Volt Rating)
CD4514B Output "High" on Select
CD4515B Output "Low" on Select
The RCA-CD4514B and -CD4515B consist
of a 4-bit strobed latch and a 4-to-16-line
decoder. The latches hold the last input data
presented prior to the strobe transition from
1 to O. Inhibit control allows all outputs to
be placed at 0(CD4514B) or 1(CD4515B)
regardless of the state of the data or strobe
inputs.
The decode truth table indicates all combinations of data inputs and appropriate selected outputs.
These devices are similar to industry types
MC14514 and MC14515.
The CD4514B and CD4515B types are
supplied in 24-lead hermetic dual-in-Iine
ceramic packages (0 and F suffixes), 24lead dual-in-line plastic packages (E suffix),
24-lead ceramic flat packages (K suffix),
and in chip form (H suffix).
•
•
•
•
VOO·24
VSS·12
I~ 50
10 51
.52
,"
6 54
5 S5
4 S6
Strobed input latch
Inhibit control
100% tested for quiescent current at 20 V
Maximum input current of 1 jJ.A. at 18 V
over full package-temperature range;
100 nA at 18 V and 250 C
Noise margin (over full package temperature range):
1 VatVDD = 5 V
2VatVDD=10V
2.5 Vat VDD = 15 V
• 5-V, 10-V, and 15-V parametric ratings
• Standardized, symmetrical output
characteristics.
• Meets all requirements of JEDEC Tentative
Standard No. 13A, "Standard Specifications
for Description of 'B' Series CMOS Devices"
18 ~
17 59
20 SIO
19 511
14 512
1:5 513
16 514
IS 51S
•
CD4514B, CD4515B
FUNCTIONAL DIAGRAM
Applications:
• Digital multiplexing
• Address decoding
• Hexadecimal/BCD decoding
• Program-coUnter decoding
• Control decoder
MAXIMUM RATINGS, Absolute-Maximum Values:
DRAIN-lO-SOURCE VOLTAGE (VDsl-V
DC SUPPLY-VOLTAGE RANGE,(V DD )
-0.5 to +20 V
-0.5 to VDD +0.5 V
±10mA
tVoltages referenced to VSS Terminal)
Fig. 1 - Typical output low (sink)
current characteristics.
INPUT VOLTAGE RANGE, ALL INPUTS
DC INPUT CURRENT, ANY ONE INPUT
POWER DISSIPATION PER PACKAGE (PO):
For TA = -40 to +60 o C (PACKAGE TYPE E)
. . . . . . . ..
500mW
Derate Linearly at 12 mW/oC to 200 mW
For T A = +60 to +850 C (PACKAGE TYPE E)
.
For T A = -55 to +1000 C (PACKAGE TYPES D,F)
500mW
. . . . . . . .,
Derate Linearly at 12 mW/oC to 200 mW
For TA = +100 to +125 0 C (PACKAGE TYPES 0, F)
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
100mW
FOR T A = FULL PACKAGE·TEMPERATURE RANGE (All Package Types)
OPERATING-TEMPERATURE RANGE (TA):
-55 to +125 0 C
PACKAGE TYPES 0, F,:H
-40 to +850 C
PACKAGE TYPE E .
-65 to +1500 C
STORAGE TEMPERATURE RANGE (Tstg )
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch 11.59 ±O.79 mm) from case for lOs max,
DRAIN-TO-SOURCE VOLTAGE (YoSI-V
RECOMMENDED OPERATING CONDITIONS at T A = 25°C, Except a. Noted.
For maximum reliability, nominal operating condition. should be seleCllld 10 that
operation I. alway. within the following ranges:
CHARACTERISTIC
VDD
(V)
Supply-Voltage Range (For T A = Full PackageTemperature Range)
LIMITS
Min.
Max.
3
18
-
Data Setup Time, ts
5
10
15
150
70
40
Strobe Pulse Width, tw
5
10
15
250
100
75
-
-
Fig. 2 - Minimum output low (,ink)
current characteri't;CI.
DRAIN-TO-SOURCE VOLTAGE (V05I-V
UNITS
V
ns
n.
Fig.
3 - Typical output high (source)
current characteristics.
310
CD4514B, CD4515B Types
STATIC ELECTRICAL CHARACTERISTICS
ORAIN-TO-SOIJACE VOLTAGE
-I~
CHARACTER·
ISTIC
Quiescent Device
Current,
100 Max.
liMITS AT INDICATED TEMPERATURES (OCI
Value,.'-55, +25, +125 Apply 10 D,F,H PIckage.
CONDITIONS
Value. al -40, +25, +85 Apply 10 E PIckage
+25
Vo
VIN VDD
+85
+125 Min.
Typ.
-40
Ma •.
(VI -55
(VI
(VI
-
0,5
5
5
5
150
150
-
0.04
5
-
0,10
0,15
10
10
-
600
-
0.04
0.04
10
20
300
600
300
15
10
20
20
0,20
20
100
100
3000
3000
-
O.OB
100
-
Output Low
(Sinkl Current
IOlMin.
0.4
0,5
5
0.64
0.61
0.42
0.36
0.51
1
-
0.5
1.5
0,10
10
1.6
1.1
0.9
1.3
2.6
-
0,15
15
1.5
4
Output High
(Sourcel
Current,
IOH Min.
4.6
0,5
0,5
5
5
0,10
0,15
10
15
2.5
9.5
13.5
4.2
-0.64 -0.61
-2
-1.8
-1.6 -1.5
-4
-4.2
2.8
-0.42
2.4
34
-0.36 -0.51
6.B
-1
-
-1.3
-1.15 -1.6
-0.9 -1.3
-2.4 -3.4
-3.2
-2.6
-6.8
-
-1.1
-2.8
-
0,5
5
0.05
-
0
0.05
Low-Level,
-
0,10
10
-
0
0.05
-
15
5
10
15
-
-
0,15
0,5
0,10
0,15
0.05
0.05
4.95
9.95
14.95
4.95
0
5
0.05
-
9.95
14.95
10
15
-
0.5.4.5
-
5
1.5
-
-
1.5
1.9
-
10
3
-
-
1.5,13.5
-
15
4
-
-
3
4
5
3.5
7
3.5
7
-
11
11
-
-
±10- 5
±0.1
Output Voltage:
High·Level.
VOH Min.
Input Low
Voltage,
VIL Max.
Input High
Voltage,
VIH Min.
Input Current
liN Max.
0.5,4.5
-
1,9
~
1.5,13.5
-
10
15
-
0,18
18
±0.1
±0.1
±1
±1
-
-~
II! I!II II II": .:. i!i!
-t. 111:·
nr-:: q:
Illdl:1:: I::: ::+
IJA
rnA
Fig. 4 - Minimum output high (source)
current characteristics.
-
Output Voltage:
VOL Max.
UNITS
tvos)-V
-10
-
V
V
Fig. 5 - Typical strobe or data propagation delay
time vs. load capacitance.
IJA
LOAD CAPACITANCE (CL}-pF
Fig. 6 - Typical inhibit propagation delay time
vs. load capacitance.
lOG AMBIENT TENPE~~TU.R!O ITAI. 25:~_
~
lOS--
I
'0'
'0'
CL'50pF_~
--CVI5pF-~
LOAD CAPACITANCE {CLI-pf"
2
46a
'0
2
4
G a l02
Z
4
6 alo~
2
4
6 ~04
FREQUENCY [fl-kHz
Fig. 7 -
Typicallow-to-high transition time vs.
load capacitance.
Fig. 8 - Typical strobe or data propagation delay
time vs. supply voltage.
Fig. 9 - Typical power dissipation vs. frequency.
____________________________________________________________________ 311
CD4514B, CD4515B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C; Input t r , tt
CL = 50pF, RL =200
Kn
TEST CONDITIONS
CHARACTERISTIC
- 20 nl,
.
Voo
UNITS
VDD
V
Typ.
Max.
5
10
15
485
185
135
970
370
270
5
10
15
250
110
85
500
220
170
Transition Time, tTLH. tTH L
5
10
15
100
50
40
200
100
80
Minimum Strobe Pulse Width, tw
5
10
15
125
50
40
250
100
75
ns
Minimum Data Setup Time, ts
5
10
15
75
35
20
150
70
40
ns
-
5
7.5
pF
Propagation Delay Time: tpHL' tpLH
Strobe or Data
Inhibit
Input Capacitance, CIN
Any Input
INPUTS
v55
LIMITS
V55
ns
Fig. 10 - Quiescent device current test circuit.
92CS-Z744IRI
fig. 71 - Input voltage test circuit.
V~NPU(JS
VDO ~~:~~.E INPUTS
o ~
Vss
lin
SEQUENTIALLY,
TO BOTH Yoo AND Vss'
A IfD
CONNECT ALL UNUSED
INPUI'S TO EITHER
ilel)
Veo OR Yss '
V55
A
a'lb
DA'A'
lieb
Fig. 12 - Input current test circuit.
... ico
Ileli
... IIcD
i ico
A
ico
i
ICD
·"
·•
,
54
so
s•
....
"5'
AerO
i
Ie 0
A
at
[!
135"
Aleo
INHIBIT 23o-·L>o-----~-------___,
1HUE INV[RTERS
USED ONLY 0..
C04!1I!1.
~
'ss
.. ALL INPUTS PROTECTEO BV
C05/MOS
PltOTECTION NETWORK
Fig.
312
!3 -
Logic diagram for CD45148 and CD45158.
CD4514B, CD4515B Types
DECODE TRUTH· TABLE (Strobe = 1)
INHIBIT
DECODER
INPUTS
D
C
B
SELECTED OUTPUT
CD4514B = Logic 1 (High)
A CD4515B = Logic 0 (Law)
STROBE
OATA I
I.
DATA 2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
1
0
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
1
X
X
X
x == Don't Care
0
1
1
0
1
0
1
50
51
52
53
0
1
0
1
54
55
56
57
0
1
0
1
58
59
510
511
0
1
DATA
1
All Output.
All Outputs
Logic 1 = high
V~---tr.lf
SI
52
SO
VSS
.r-\. ~O"4
----JI-- 'W ~'--::S-2"!I""Z
I.I.
I.
10
15
14
12
TOP VIEW
"
"
92C5-
STROBE
Fig.
VDD
INHIBIT
DATA 4
17
53
a2Qnl
_ _ _ _ ...J ~IS ~
512
513
514
515
0
X
57
5.
5'
54
2'
22
21
20
2.
OATA ;,
SlO
511
5.
5.
Sl4
515
512
51>
24~'"
CD4514B
CD4515B
14 - Waveforms for setup time and
TERMINAL ASSIGNMENT
strobe pulse width.
= 0, CD4514B
= I, CD4515B
Logic 0= low
101
Dimensions and Pad Layout for C045158 Chip
(Dimensions and pad layout for the CD45148 are ident(caIJ
Dimensions in parentheses am in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10- 3 inch).
The photographs and dimensions of each COS/MOS
chip represent a chip when it is parr of the wafer.
When the wafer ;s cut into chips, the cleavage
angles are 57° instead of 90° with respect to the
face of the chip. Therefore, the isolated chip is
actually 7 mils (0. 17 mm) larger in both dimensions.
____________________________________________~----------------------313
CD4517B Types
COS/MOS Dual 64·Stage
Static Shift Register
016 A
Q48 A
Features:
• Low quiescent current - 10 nA/pkg (typ.)
atVOO=5V
• Clock frequency 12 MHz (typ.) at
VOO= 10V
• Schmitt trigger clock inputs allow operation
with very slow clock rise and fall times
• Capable of driving two low-power TTL loads,
one low- power Schottky TTL load, or two
HTL loads
• Three-state outputs
• 100% tested for quiescent current at 20 V
.• Standardized, symmetrical output
characteristics
• 5-V, 10-V and 15-V parametric ratings
• Meets all requirements of JEOEC Tentative
Standard No.13A, "Standard Specifications
for Description of 'B' Series CMOS Devices"
I.
I.
VDD
12
WEB
CLB
Q64e
15
WE A
The RCA-CD4517B dual 64-stage static shift
register consists of two independent registers
each having a clock, data, and write enable
input and outputs accessible at taps following
the 16th, 32nd, 48th, and 64th stages. These
taps also serve as input points allowing data
to be inputted at the 17th, 33rd, and 49th
stages when the write enable input is a logic
1 and the clock goes through a low-to-high
transition. The truth table indicates how the
clock and write enable inputs control the
operation of the CD4517B. Inputs at the
intermediate taps allow entry of 64 bits into
the register with 16 clock pulses. The 3-state
outputs permit connection of this device to
an external bus.
The CD4517B is supplied in 16-lead hermetic
dual-in-line ceramic packages (0 and F
suffixes), l6-lead dual-in-line plastic packages (E suffix), l6-lead ceramic flat packages (K suffix), and in chip form (H suffix).
•
CL A
5
064 A
032 4 DA
13
"
10
• Scratch-pad memories
• General-purpose serial shift-register
appl ications
E~~.~-~_,-_,-~
Q488
WE· 0-- QI6---032---o48---064
WE- 1---·DI1---D33---D49--HiZ
IOF 2 SHIFT REGISTERS· TERM. Nos.
IN FMENTHESES ARE FOR 2 NO HALF.
VOO a l6
032 8
VSS·8
DB
vss
TOP VIEW
92CS-30371
92CS-31097
TERMINAL ASSIGNMENT
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY·VOLTAGE RANGE. IVDDI
-0.5 to +20 V
(Voltages referenced,to VSS Terminal)
INPUT VOLTAGE RANGE, ALL INPUTS
-0.5 to V DO +0.5 V
±10mA
DC INPUT CURRENT, ANY ONE INPUT
POWER DISSIPATION PoER PACKAGE (PO!:
For T A = -40 to +60 C (PACKAGE TYPE EI
.. '.' . . . '';
500mW
Derate Linearly at 12 mWI C to 200 mW
For T A = +60 to +85°~ (PACKAGE TYPE EI. .
500mW
For T A = -55 to +100 ~ (PACKAGE TYPES D. FI
Derate Linearly at 12 mW/C to 200 mW
For TA = +100 to +125 C (PACKAGE TYPES D. FI
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE·TEMPERATURE RANGE IAII Package Typesl
100mW
OPERATING·TEMPERATURE RANGE (TAl:
PACKAGE TYPES D. F. H
-55 to +12~:C
PACKAGE TYPE E
-40 to +85 C
STORAGE TEMPERATURE RANGE (Tstgl
.
-65 to +150 oC
LEAD TEMPERATURE (DURING SOLDERINGI
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max.
. +265°C
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that
.
operation is always within the fol/owing ranges:
LIMITS
CHARACTERISTIC
Supply·Voltage Range (For TA
Temperature Range)
=
MIN.
MAX.
3
18
Full Package
UNITS
V
TRUTH TABLE
Clock
0
0
1
1
--
~
-------
X = Don't Care
314
OO'A(DI!
WRITE
OISe
Applications:
• Time-delay circuits
ClOC.:~iIIZl.r------'
TERMINAL ASSIGNMENT
High-Voltage Types (20-Volt Rating)
Write
Enable
Data
Stage 16
Tap
Stage 32
Tap
Stage 48
Tap
Stage 64
Tap
0
1
0
1
0
1
0
1
X
X
X
X
Olin
Olin
X
X
016
032
048
064
Z
Z
Z
Z
016
032
048
064
Z
Z
Z
Z
016
D171n
016
032
033 In
032
048
049 In
048
064
Z
Z
Z
Z
Z = High Impedance
Z
064
CD4517B Types
CL--~------~----~------~----~----~~--~~-----,
CL
016
048
032
01
049
16 STAGES
16 STAGES
STAGE 16
OUTIIN TAP
STAGE 32
OUTIIN TAP
•
STAGE 48
OUTIIN TAP
STAGE 64
OUTIIN TAP
9~CM-3109BRI
Fig. 1-CD4517B functional block diagram (one half).
V55
A PROTECTED BY COS/Mes
PROTECTION NETWORK
~
V55
"* PROTECTION
PROTEe]ED BY COS/Mes
NETWORK
SAME AS
STAGES
16.32,48
EXCEPT
we:
WE
WE
WE
FOR Q-
92CL-32165
Fig. 2-CD4517B logic block diagram (one half).
eLK
WE
064
92CM-32763
Fig. 3-Dynamlc test waveforms.
_______________________________________________________________________ 315
CD4517B Types
STATIC ELECTRICAL CHARACTERISTICS
u
LIMITS AT INDICATED TEMPERATURES (oC)
CHARACTERISTIC
CONDITIONS
Vo
(V)
Quiescent
Device
Current,
100 Max.
Values at -55. +25, +125 Apply to D,F,H Packages
Values at -40, +25, +85 Apply to E Package
+25
VIN VDD
(V)
(V) -55
+85
-40
+125
Max.
Typ.
Min.
0.04
5
0.04
10
600
-
0.04
20
3000
3000
-
0.08
100
0.42
0.36
0.51
1
-
1.1
0.9
1.3
2.6
2.8
2.4
3.4
6.8
0.5
5
5
5
150
150
-
0,10
10
10
10
300
300
-
0,15
15
20
20
600
-
0.20
20
100
100
0.4
D,S
5
0.64
0.61
1.6
1.5
4.2
4
-
Output Low
(Sink) Current 0.5
IOL Min.
1.5
0,10
10
0.15
15
4.6
D,S
5
2.5
0,5
5
-2
-1.8
-1.3 -1.15
-1.6
-3.2
-
Output High
(Source)
Current,
IOH Min.
Output Voltage:
Low·Level,
VOL Max.
Output
Voltage:
High·Level,
VOH Min.
Input Low
Voltage
VIL Max.
Input High
Voltage,
VIHMin.
N
I
T
S
-0.64 -0.61
-0.42 -0.36 -0.51
-1
mJl
9.5
0,10
10
-1.6
-1.5
-1.1
-0.9
-1.3
-2.6
0,15
15
-4.2
-4
-2.8
-2.4
-3.4
-6.8
-
0,5
5
0.05
-
0
0.05
-
0,10
10
0.05
-
0
0.05
-
0,15
15
0.05
-
0
0.05
-
0,5
5
4.95
4.95
5
-
0,10
10
9.95
9.95
10
-
-
0,15
15
14.95
14.95
15
-
0.5,4.5
-
5
1.5
-
1.5
4
-
1,9
-
10
3
-
-
1.5,13.5
-
15
4
-
-
0.5,4.5
-
5
3.5
3.5
-
1,9
-
10
7
7
-
-
1.5,13.5
-
15
11
11
-
-
-
0,18
18
±0.1
±0.1
±1
±1
3·State
Output
Leakage
Current
lOUT Max.
0,18
0,18
18 ±O.4
±0.4
±12
±12
DRAIN-lO-SOURCE VOLTAGE {Vos)-V
Fig. 4-Typical n-channel output low (Sink)
current characteristics.
13.5
Input Current
liN Max.
IlA
V
DRAIN-lO-SOURCE VOLTAGE (VosJ-V
Fig. 5-Minimum n-channel output low (sink)
current characteristics.
3
ORAIN-lO-SOURCE VOLTAGE (VoSI-V
V
±10- 5 ±0.1 Il A
-
-
±10-4
±0.4 IlA
Fig. 6- Typical p-channel output high (source)
current characteristics.
ORAIN-lO-SOURCE VOLTAGE (Vos)-V
LOAD CAPACITANCE (CLJ-pF
Fig. 7-Minimum p-channel output high
(source) current characteristics.
Fig. 8-Typical propagation delay time as a
function of load capacitance.
Fig. 9- Typical transition tIme a a function
of load capacitance.
316 __________________________________________________________________- -
CD4517B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA
CL = 50pF. RL = 200kQ
TEST
CONDITIONS
CHARACTERISTIC
VOO (V)
Propagation Delay Time:
Cl to Bit 16 Tap
tpHL. tplH
3·State Output. WE to Bit
16 Tap tpHZ. tpLZ; tpZH.
tpZl (See Note)
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
Output Transition Time
tTHl. tTlH
Write Enable·to·Clock
Setup Time
Data·to·Clock
Setup Time. ts
=25°C; Input tr• tf=20ns.
Min.
LIMITS
UNITS
Typ. Max.
-100
-50
-30
-100
-60
-30
-
200
110
90
75
40
30
400
220
180
150
80
60
100
50
40
-50
-25
-15
-50
-30
-15
200
100
80
50
25
20
100
50
40
ns
100
50
25
200
100
50
ns
ns
-
5
10
15
Minimum Clock Pulse
Width. tw
5
10
15
-
90
40
25
180
80
50
Maximum Clock Input
Frequency. ICl
5
10
15
3
6
8
6
12
15
-
Maximum Clock Input Rise
or Fall Time. tlCl trCl
5
10
15
Input Capacitance CIN
Any Input
-
Fig. 10- Typical power dissipation as a
function of frequency.
ns
Data·to·Clock
Hold Time. tH
-
FREQUENCY If I KHz
ns
ns
5
10
15
-
ns
-
Write Enable·to·Clock
Release Time
-
ns
REPETITIVE WAVEFORM
fo
MHz
-
r--\
r-\
r - - \ , - Voo
c -J
'--J
LJ
"'---- Vss
~VDD
UNLIMITED
,..S
5
pF
D
(f-1/2 fol
--
Vss
92CS-3Z766
Fig. II-Dynamic power dissipation test
-
7.5
circuit and waveforms.
NOTE: Measured at the point of 10% change in output with an output load of 50 pF. Rl = 1 kQ to
VOO for tpZL. tpLZ and RL = 1 kQ to VSS for tpZH. tpHZ'
INPUTS
o
Vss
. INPUTOVOO
OUTPUTS
VIH
VDD
t
'
V~
•
NOTE:
~
vss
MEASURE INPUTS
SEQUENTIALLY I
TO BOTH Voo ANO Vss'
CONNECT ALL UNUSED
L-_,----' INPUTS TO EITHER
NOTE:
Vss
Vss
Fig. 12-Quiescent-device-current test circuit.
Voo OR VSS'
~~srNApNu~;OMBINAT1ON
92CS-Z 7441 R I
Fig. 13-lnput-voltage test circuit.
Vss
'J2CS-2740Z
Fig. 14-lnput current test circuit.
_________________________________________________________________________ 317
CD4517B Types
13.
Dimensions and pad layout for CD4517B.
Dimensions in parentheses are in millimeters
and are derived from the basic Inch dimensions as Indicated. Grid graduations are in
mils (1(J3 inch).
318
92CM-32762
The photographs and dimensions represent a
chip when it is part of the wafer. When the
wafer is cut into chips, the cleavage angles are
57" Instead of 90· with respect to the face of
the chip. Therefore, the Isolated chip is actually 7 mils (0.17 mm) larger in both dimensions.
CD4518B, CD4520B Types
COS/MOS Dual Up-Counters
High-Voltage Types (20-Volt Rating)
Features:
CD4518B Dual BCD Up-Counter
CD4520B Dual Binary Up-Counter
• Medium-speed operation 6-MHz typical clock frequency at 10 V
• Positive- or negative·edge triggering
• Synchronous internal carry propagation
The RCA·CD4518 Dual BCD Up·Counter
and CD4520 Dual Binary Up-Counter each
consist of two identical, internally synchro·
nous 4·stage counters. The counter stages are
D·type flip-flops having interchangeable
CLOCK and ENABLE lines for incrementing
on either the positive·going or negative·going
transition. For single·unit operation the
ENABLE input is maintained high and the
counter advances on each positive-going
transition of the CLOCK. The counters are
cleared by high levels on their RESET lines.
The counter can be cascaded in the ripple
mode by connecting Q4 to the enable input
of the subsequent counter while the CLOCK
input of the latter is held low.
The CD4518B and CD4520Btypes are supplied in 16-lead hermetic dual-in-line ceramic packages (D and F suffixes), 16-lead
dual-in-line plastic packages (E suffix). 16lead ceramic flat packages (K suffix), and in
chip form (H suffix).
• 100% tested for quiescent current at 20 V
• Maximum input current of 1 /JA at 18 V
over full package-temperature range;
100 nA at 18 V and 25°C
CD4518B, CD45208
• Noise margin(over full package-temperature
range): 1 Vat VDD = 5 V
2VatVDD=10V
FUNCTIONAL DIAGRAM
2.5 Vat VDD = 15 V
Applications:
• 5-V, 10-V, and 15-V parametric ratings
• Standardized, symmetrical output
characteristics
• Me~ts all requirements of JEDEC Tentative
Standard No. 13A, "Standard Specifications
for Description of 'B' Series CMOS Devices"
CLOCK
..r
'0
X
..r
1
MAXIMUM RATINGS,Absolute-Maximum Values:
X
DC SUPPLY·VOLTAGE RANGE, (V DO)
(Voltages referenced to VSS Terminal J
-o.S to +20 V
-0.5 to VDD +O.S V
±10mA
INPUT VOLTAGE RANGE, ALL INPUTS
DC INPUT CURRENT, ANY ONE INPUT
POWER DISSIPATION PER PACKAGE (PO):
For T A = -40 to +60o C (PACKAGE TYPE E)
. . • . . . . ••
SoomW
.
Derate Linearlv at 12 mW/oC to 200 mW
For T A = +60 to +850 C (PACKAGE TYPE EI
For T A = -55 to +1000C (PACKAGE TYPES D,F )
. . • . • • . ..
500mW
Derate Linearly at 12 mW/oC to 200 mW
For TA = +100 to +125 0 C (PACKAGE TYPES 0, F)
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types)
100mW
OPERATING-TEMPERATURE RANGE (TA):
-55 to +12SoC
PACKAGE TYPES 0, F, H
-40 to +8SoC
PACKAGE TYPE E .
STORAGE TEMPERATURE RANGE (Tstg )
-65 to +IS00C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 5 max.
• Multistage synchronous counting
• Multistage ripple counting
• Frequency dividers
TRUTH TABLE
ENABLE
RESET
1
0
Increment Counter
'-
0
Increment Counter
X
0
No Change
of
0
No Change
0
0
No Change
'X-
0
No Change
1
01 thru 04= 0
x ... Don't Car.
1
= High State
CLOCK A
ENABLE A
QIA
Q2A
Q3A
QOA
RESET A
V55
ACTION
I.
2
3
IS
Low State
15
vDO
RESET B
10
Qoa
13
12
7
B
o=
Q3B
Q2B
"
QIB
9
CLOCK 8
10
ENABLE B
(TOP VIEW)
92CS-24515
CD4518B, CD4520B
TERMINAL ASSIGNMENT
DRAIN-lO-SOURCE VOLTAGE (Vosl-Y
ORAIN-TO-SO'JRCE VOLTAGE ''o'oSI-V
Fig. 1 - Typical output low (sink) current
characteristics.
ORAIN- TO- SOURCE YDLTAGE
Fig. 2 - Minimum output low (sink) current
ch~racter;stics.
Fig. 3 - Typical output high (source) current
characteristics.
_______________________________________________________________ 319
CD4518B, CD4520.B Types
STATIC ELECTRICAL CHARACTERISTICS
CHARACTER·
ISTIC
Quiescent Device
Current,
100 Max.
Output Low
(Sink) Current
IOlMin.
Output High
tSource)
Current,
IOH Min.
Output Voltage:
low·level,
VOL Max.
Output Voltage:
High·level,
VOH Min.
Input low
Voltage,
Vil Max.
Input High
Voltage,
VIH Min.
Input Current
liN ~ax.
DRAIN-TO-SOURCE VOLTAGE IVOSI-V
LIMITS AT INDICATED TEMPERATURES (DC)
Value. It -55, +25, +125 Apply to D, F ,H Peckqn
CONDITIONS
Vllull .t -40, +25, +85 Apply to EPee.....
UNITS
+25
Vo
VIN VDD
Typ. Mix.
+125 Min.
+a5
(V)
(V)
(VI -55 -40
-
a,s
150
300
500
3000
-
0.42
1.1
2.8
-0.42
-1.3
1.1
-2.8
0.36
.0.9
2.4
-0.36
-1.15
0.9
-2.4
0.51
1.3
34
-0.51
-1.6
1.3
-3.4
-
5
10
15
20
5
10
20
100
0.4
0.5
1.5
4.6
2.5
9.5
13.5
-
0,5
0,10
0,15
0,5
5
10
15
'5
0.64
a,s
0,10
0,15
5
10
15
a,s
5
-
0,10
0,15
0,5
0,10
0,15
10
15
5
10
15
0.05
0.05
0.05
4.95
9.95
14.95
-
1.5,13.5
-
5
10
15
5
10
15
1.5
3
4
3.5
7
11
-
0,18
18
-
0.5,4.5
1,9
1.5,13.5
0.5,4.5
1,9
-
5
10
20
100
150
300
500.
3000
0,10
0,15
0,20
0.61
1.5
1.6
4
4.2
-0.64 -0.61
-2
-1.8
-1.6 -1.5
-4.2
-4
iO.l
±0.1
0.04
0.04
0.04
0.08
-
1
2.6
6.8
-1
-3.2
2.6
-6.8
-
a
a
a
4.95
9.95
14.95
5
10
15
-
-
-
-
-
±1
±1
5
10
20
100
I'A
-
-
rnA
Fig. 4 - Minimum output high (source) current
.
characteristics.
0.05
0.05
0.05
V
1.5
3
4
3.5
7
11
-
-
-
±10- 5
iO.l
-
20
30
V
40
50
60
70
80
LOAD CAPACITANCE ICLJ-pF
90
100
Fig. 5 - Typical propagation delay vs. load
capaCitance, clock or enable
to output.
IJ.A
LOAD CAPACITANCE (CLI-pF
Fig. 6 - Typical propagation delay time vs.
load capacitance, reset to output.
10
.,
SlJtl'PL.Y VOLTAGt 1VooJ-Y
LOAD CAPACITANCE ICL l-pF
0.1 I
.. " .
I
.. "10 I
.. "'012
.. "'051
.. "10"
FREQUENCY Itl- 11Hz
Fig. 7 - Typical transition time
capacitance.
'IS.
load
Fig.
8 - Typical maximum-clock-frequency
'IS. suppiV voltage.
Fig. 9 - Typical power dissipation
characteristics.
320 __________________________________________________________________
CD4518B, CD4520B Types
RECOMMENDED OPERATING CONDITIONS at TA = 250 C, Except as Noted.
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges:
CHARACTERISTIC
LIMITS
Min.
Max.
VDD
(V)
Supply·Voltage Range (For TA=Full Package·
Temperature Range)
Enable Pulse Width, tw
Clock Pulse Width, tw
Clock Input Frequency, ICl
Clock Rise or Fall Time, trCl or tlCl:
Reset Pulse Width, tw
3
de
-
UNITS
V
18
400
200
140
200
100
70
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
TEST CIRCUITS
Voo
-
ns
-
ns
Fig. 10 - Dynamic power dissipation.
1.5
3
4
15
5
5
MHz
IlS
-
250
110
80
ns
-
-
'NPUTOVDO
OUTPUTS
V'H
'--
~
J;
Y~
NOTE:
~~'JN~U~~OMBINATION
Vss
DYNAMIC ELECTRICAL CHARACTERISTICS at TA-25 0 C;
Inputt"tt-20 ns, CL ~50 pF, RL -200 Kn
CHARACTERISTIC
Propagation Delay Time, tpH l' tplH:
Clock or Enable to Output
Reset to Output
Transition Time, tTHl' tTlH
Maximum Clock Input Frequency. tCl
Minimum Clock Pulse Width, tw
5,10
15
5
10
15
5
10
15
Minimum Reset Pulse Width, tw
Minimum Enable Pulse Width, tw
Clock Input Rise or
Fall Time, trcl, tref
Fig. 11 - Input voltage.
TEST CONDITIONS
LIMITS
VOD
V
Min. Typ. Max.
5
- 280 560
10
- 115 230
15
80 160
5
- 330 650
10
- 130 225
15
90 170
5
- 100 200
10
- 50 100
15
- 40 80
1.5
3
5
10
3
6
15
4
8
100 200
5
50 100
10
15
35 70
Clock Rise or Fall Time, tr or tl:
Input Capacitance, CI N
92CS-27441RI
-
-
Any Input
5
10
15
-
-
15
5
125
55
40
200
100
70
5
250
110
80
400
200
140
7.5
-
15
5
5
UNITS
ns
INPUTS
r-~--'
o
Vss
ns
MHz
ns
Fig. 12 - QuiescentdevicecurrenttBstcircuir.
IlS
ns
ns
pF
IlS
Voo
1NPUOS
Voo
NOTE
~
~:~~::I!~~~S
Vss
TO 80TH VDO AND Yss'
CONNECT ALL UNUSED
INPUTS TO EITHER
V5S
Yoo OR VSS'
Fig. 13 - Input leakage-currenr test
oircuit.
____________________________________________________________________ 321
CD4518B, CD4520B Types
02
01
RESET
Fig. 14 - Oecade counter (C04518BJ logic diagram
for one of two identical counters.
VDD
.,. "'" ."",,..~
, .fiCOSIMOS PROTECTION
NETWORK
Vss
B;VS5
*
ALL INPUTS PROTECTED BY
Fig. 15 - Binary counter (CD4520Bi logic diagram
for one of two identical counters.
CDS/MOS PROTECTION
NETWORK
RESET
CLOCK
ENABLE
- ~~ti.~
RESET
O'
CD451B {
02
-
O'
O'
0'
C04520 {
Q2
-
.
, ••
MNtKn
5 •
7
•
9
II
12 13 14 1516 17 18
I
I-l~ ~~ ~~ ~~ I - -
o ,
••
•
5
•
7
8fL
t--
.
-
I-
, ••
5
•
7
•
ll-
9 10 II 12 13 14 15
o ,
f-
~
2fL
Fig. 16 - Timing diagrams for CD451BB and CD4520B.
t-
l-
O'
I
Q4
322 ________________~-------------------------------------------------
CD4518B, CD4520B Types
Fig. 17 - Ripple cascading of four counters with positive edge triggering.
*NOTE:
fOR SYNCHRONOUS CASCADING,THE CLOCK TRANSITION
TIME SHOULD BE MADE L.ESS THAN M EQUAL TO THE
SUN OF THE FIXED PROPAGATION DELAY AT i5pF AND
THE TRANSITION TIME OFTHE OUTPUT DRIVER STAGE
FOR THE ESTIMATED CAPACITATIVE L.OAD.
Fig.t8 - Synchronous cascading of four binary counters with negative edge triggering.
92
Dimensions and pad layout for CD4518BH chip.
Dimensions and pad layout for CD4520BH chip.
The photographs and dimensions of each
COS/MOS chip represent a chip when it
Dimensions in paren theses are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10- 3 inchJ.
is part of the wafer. When the wafer i$
cut into chips, the cleavage angles are
57° instead of 90° with respect to the
face of the chip. Therefore. the isolated
chip is actually 7 mils (0. 17 mm) larger
in both dimensions.
_______________________________________________________________________ 323
CD4527B Types
COS/MOS BCD Rate
Multiplier
High-Voltage Types (20-Volt Rating)
The RCA·CD4527B is a low·power 4·bit digi·
tal rate multiplier that provides an output·
pulse rate which is the clock·input·pulse rate
multiplied by 1/10 times the BCD input. For
example, when the BCD input is B, there will
be B output pulses for every 10 input pulses.
This device may be used to perform arith·
metic operations (add, subtract, divide, raise
to a power), solve algebraic and differential
equations, generate natural logarithms and
trigonometric functions, AID and DIA con·
version, and frequency division.
For fractional multipliers with more than one
digit, CD4527B devices may be cascaded in
two different modes: the Add mode and the
Multiply mode. (See Figs.12and15).ln the
Add mode,
Output Rate ~
(Clock Rate) [0.1 BCDl 0.01 BCD2
0.001 BCD3 + . . . .
+
+1
J
I n the Multiply mode, the fraction program·
med into the first rate multiplier is multiplied
by the fraction programmed into the second
one,
e.g.J!. x..i ~ ~ or 36 output
10 10 100
pulses for every 100 clock input pulses.
The CD4527B types are supplied in 16-lead
ceramic dual-in-line packages (D and F
suffixes), 16-lead dual-in-line plastic packages (E suffix), 16-lead ceramic flat packages (K suffix), and in chip form (H suffix).
Features:
•
•
•
•
•
Cascadable in multiples of 4-bits
Set to "9" input and "9" detect output
100% test for quiescent current at 20 V
5·V, 10·V, and 15-V parametric ratings
Standardized, symmetrical output
characteristics
• Maximum input current of 1 JlA at 18 V over
full package·temperature range; 100 nA at
18 V and 25°C
• Noise margin (full package·temperature
range) ~
1 VatVDD~ 5 V
2 Vat VDD ~ 10 V
2.5 Vat VDD ~ 15 V
• Meets all requirements of JEDEC Tentative
Standard No.13A, "Standard Specifications
for Description of 'B' Series CMOS Devices"
"9" OUT
C
0
I.
At distance 1/16 ± 1/32 inch (1.59 ±0.79 mm) from case for 10s max.
RECOMMENDED OPERATING CONDITIONS AT TA ~ 250 C, Except as Noted.
For maximum reliability, nominal operating conditions should be selected so that operation is
always within the following ranges:
Supply· Voltage Range (For T A
Temperature Range)
voo
IS
"
SET TO"9"
"13
OUT
12
OUT
"
INHIBIT OUT
10
(CARRYI
9
vss
=
Full Package·
LIMITS
Min.
Max.
3
18
-
UNITS
V
Set or Clear Pulse Width, tw
5
10
15
160
90
60
Clock Pulse Width, tw
5
10
15
330
170
100
-
5
10
15
dc
1.2
2.5
3.5
MHz
5,10,15
-
15
flS
5
10
15
100
40
20
-
ns
5
10
15
240
130
110
-
5
10
15
150
80
50
Clock Frequency, fCl
CLEAR
CASCADE
INHIBIT IN
Clock Rise or Fall Time, t rCl or tfCl
(CARRYI
STROBE
Inhibit In Setup Time, tsu
TOP VIEW
92CS-249,4
Inhibit In Removal Time, tREM
TERMINAL ASSIGNMENT
~et
Removal Time, tREM
-
ns
-
ns
-
-
ns
-
-
ns
-
5
60
ns
10
40
15
30
__________________________________________________________________
__
Clear Removal Time, tREM
324
VDD
(VI
•
CLOCK
FUNCTIONAL DIAGRAM
(Voltages referenced to VSS Terminal!
-0.510 +20 V
INPUT VOLTAGE RANGE, ALL INPUTS
-0.510 VDD +0.5 V
±10mA
DC INPUT CURRENT, ANY ONE INPUT
POWER DISSIPATION PER PACKAGE (PO):
0
For TA = -40 10 +60 C (PACKAGE TYPE E)
. . . . . . . ..
500 mW
Derate Linearly at 12 mW/oC to 200 mW
For T A = +6010 +850C (PACKAGE TYPE E) . .
For TA = -55 10 +1000C (PACKAGE TYPES 0, F) ,.
. . . '. . . . . .
500mW
Derate Linearly at 12 mW/oC to 200 mW
For T A = +10010 +125 0C (PACKAGE TYPES 0, F)
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE·TEMPERATURE RANGE (A" Package Typesl
100mW
OPERATING·TEMPERATURE RANGE (TA):
PACKAGE TYPES 0, F, H
-55 10 +125 0C
PACKAGE TYPE E .
"-40 10 +85 0 C
STORAGE TEMPERATURE RANGE (Tstg )
-65 10 +1500C
LEAD TEMPERATURE (DURING SOLDERING):
CHARACTERISTIC
Numerical control
Instrumentation
Digital filtering
Frequency synthesis
Vss'S
MAXIMUM RATINGS, Absolute·Maximum Values:
DC SUPPL Y·VOL TAGE RANGE, (V DO)
Applications:
•
•
•
•
Voo" IS
CD4527B Types
STATIC ELECTRICAL CHARACTERISTICS
CHARACTER·
ISTIC
Quiescent Device
Current,
IDD Max.
Output low
(Sink) Current
IOlMin.
Output High
(Source)
Current,
IOH Min.
Output Voltage:
low·level,
VOL Max.
Output Voltage:
High·level,
VOH Min.
Input low
Voltage,
Vil Max.
Input High
Voltage,
VIH Min.
Input Current
liN Max.
LIMITS AT INDICATED TEMPERATURES (DC)
Value.at-55, +25, +125 Apply to 0, F, H Packago.
Values at -40, +25, +85 Apply to E Plcklge
CONDITIONS
Vo
(V)
VIN VOD
(V)
(V)
+25
Typ.
Max.
0.04
0.04
0.04
0.08
5
10
20
100
1
2.6
-
6.8
-1
-3.2
-2.6
-6.8
-
-
0
0.05
0
0
5
10
15
0.05
0.05
-
-
3.5
-
1.5
3
4
7
-
-
±10- 5
±0.1
-55
-40
+85
+125
Min.
5
10
20
100
150
300
600
3000
150
-
10
15
20
5
10
20
100
300
600
3000
-
0.5
0,10
0.15
5
10
15
5
5
10
15
0.64
1.6
4.2
-0.64
-2
-1.6
-4.2
0.61
1.5
4
-0.61
-1.8
-1.5
-4
0.42
1.1
2.8
-0.42
-1.3
-1.1
-2.8
0.36
0.9
2.4
-0.36
-1.15
-0.9
-2.4
0,5
5
-
0,10
0,15
0,5
0,10
0,15
10
15
5
10
15
0.5,4.5
-
5
1,9
1.5,13.5
-
0.5,4.5
1,9
-
-
1.5,13.5
-
10
15
5
10
15
0,18
18
-
0,5
0,10
0,15
-
0,20
0.4
0.5
1.5
4.6
2.5
9.5
13.5
-
.-
-
0,5
0,10
0,15
0,5
-
5
0.05
0.05
0.05
4.95
9.95
14.95
4.95
9.95
14.95
1.5
3
4
3.5
7
11
to. 1 to. 1
0.51
1.3
34
-0.51
-1.6
-1.3
-3.4
-
11
±1
±1
-
-
-
UNITS
IJA
ORAIN-TO-SOURCE VOLTAGE IVDSI-V
-
-
Fig.' - Typical output low (sink)
current characteristics.
rnA
,..PEii;""'
V
-
-
-
II
,
V
DRAIN-lO-SOURCE VOLTAGE (I/Dsl-V
F;g.2 - Minimum output low (sink)
curren t characteristics.
IJA
Io'!"
DRAIN-lO-SOURCE VOLTAGE II/Psi-V
DRAIN-TO· SOURCE VOLTAGE IVosI-V
2
~
1'0'1
.e •
~
~
.
ffi
2
-"liF:r~
. 1J <,.pI" . .
- - ,'f/',I.'.,l.
~
.'
~.-
Q~
2
~ IO~
.~
.~
/
4
CL.-!50pF
CL·15pF - - -
2lela
:
2
'0
2
...
2
10
468
10 2
2468
2
10 3
... ...
2
10 4
lOS
INPUT FREQUENCY "IN)-kHl
92CS-2915!!1
Fig.3 - Typical output high (source)
Fig.4 - Minimum output high (source)
current characteristics.
current characteristics,
Fig.5 - Typical dynamic power dissipation as a
function of input frequency.
Va:>
INPOU
Voo S NOW
~
o ~
Vss
'
MEASURE INPUTS
SEQUENTIALLY,
TO BOTH VOD AND Vss·
CONNECT ALL UNUSED
INPUTS TO EITHER
VDO OR Vss·
Vss
LOAD CAPACITANCE ICL,I- pF
92CS-291!14
a
Fig. 6 - Typical propagation delay time as
function of load capacitance (Clock
or Strobe to Out).
Fig.7 - Typical transition time as a function of
Fig.8 - Input current test circuit.
load capacitance.
_____________________________________________________________________
325
CD45278 Types
DVNAMIC ELECTRICAL CHARACTERISTICS at T A =25°C:
Input t,.tt =20 ns. CL =50 pF. R L =200 kn
TEST CONDITIONS
CHARACTERISTIC
VDD
(V)
5
10
15
Propagation Delay Time. tPHL. tPLH
Clock to Out
5
10
15
Clock or Strobe to Out
5
10
15
Clock to Inhibit Out
High level to Low Level
5
10
15
Low level to High level
UNITS
Min.
Typ.
Max.
-
110
55
45
220
110
90
150
75
60
300
150
120
320
145
100
640
290
200
250
100
75
500
200
150
380
175
130
760
350
260
300
125
600
250
180
-
-
Clear to Out
5
10
15
-
Clock to "9" or "15" Out
5
10
15
-
Cascade to Out
5
10
15
-
Inhibit In to Inhibit Out
5
10
15
Set to Out
5
10
15
-
-
90
90
45
35
180
90
70
130
60
45
260
120
90
330
150
110
660
300
220
200
100
80
Fig.9 - Input voltage test circuit.
VOD
vco
INPUTS
ns
ns
Voo
ns
ns
-
Maximum Clock Frequency. feL
1.2
2.5
3.5
2.4
5
7
-
MHz
Minimum Clock Pulse Width, tw
5
10
15
165
85
50
330
170
100
ns
Clock Rise or Fall Time. trCL. tfCl
5
10
15
-
15
15
15
/J.S
Minimum Set or Clear Pulse Width, tw
5
10
15
-
80
45
30
160
90
60
Minimum Inhibit In Setup Time, tsu
5
10
15
50
20
10
100
40
20
120
65
55
240
130
110
75
40
25
150
80
50
-
-
30
20
15
60
40
30
ns
-
5
7.5
pF
tREM
Minimum Set Removal Time, tREM
5
10
15
Minimum Clear Removal Time, TREM
5
10
15
Input Capacitance, CIN
Any Input
-
-
Vss
Fig. to - Ouiercent device current test circuit.
5
10
15
5
10
15
Non;:
~N~~~0M8INAl1ON
92CS-Z144I1U
100
50
40
Minimum Inhibit In Removal Time,
~
=
.
ns
Transition Time. tTHl, tTlH
-
..........
V 1L
VSS
5
10
15
-
'NPUTOVCOOUTPUTS
V,.
LIMITS
'ZCS-UI157
Fig. 1 1 - Dynamic power di"ipation te,t circuit.
APPLICATIONS
MOST SIGNIFICANT
LEAST SIGNIFICANT
DIGIT
DIGIT
DRM (j)
A
DAIIIC!)
ns
--------......I
CLOCKQ-__
01234,6189012345,1890
ns
TIMING OIAGRAM SHOWING ONE OF FOUR OUTPUT
PULSES CONTRIBuTED BY DR" (J) TO OuTPUT FOR
I
EVERY 100 CLOCIC PULSES IN FOR PRESET No.94.
UCS·249,TRI
Fig. 12 - Two CD4527S's cascaded in the "Add"
mode with S PflIset number
326 _________________________________________________________________
CD4527B Types
'I4Q-_-{)_-{)~
*
_ _ _ _ _ _ _ _ _--'
STROBE
10
*
012345678901234
CASCADE
12
CLOCK
.,'9--[>--{:;--------------.
O.
n.n.nrmJlll1UUl
mLJ1JLJ1Jl...
~
\,cr--{~~~-----------------
o,~
."C?;;;;;;-l>~-{>;:===4==1=:J
INHIBIT IN
o.~
~
R2~
R'~
---u--u--un
OUTPUT (PIN 61
n
A ENABLED ---1~L.
8 ENll.BLED
C ENABLED
o
ENABLED
~
~
~
U
INIt. OUT
OUPUTIPIN61
(PRESET No· OF" 11
IPRESET No. OF 21
~
~
(PRESET No. Of 31
(PRESET No.QF4)
~
IPRESETNoQF5J
~
IPRESETNo. OF 61
~
I
*13
CLEAR
Fig. 13 - Logic diagram.
,
.,
IPRESET No· OF" 7)
(PRESET No. OF 81
'PRESET',·O'"
JUlfULJlJUUL1lI
~
I
9
OUTPUTS
V'H
=--
015
I
VIL
N
)
01 7
8
)
00 9
I
NOTE:
.....- - - - - - - - - 03'
08
TEST ANY ONE INPUT,
VSS
."'"
I
'~
~
02 6
WITH OTHER INPUTS AT
Voo ORVss·
)-"-+---GS'
07---...;.1
Fig. 13 - Input voltage test circuit.
I.
I
I
>,,'-1.___ 01'
)
)
OO---~OO
VOl)
)-"-1---- 00'
L -_ _ _ _ _ _ _ _ _ _ _ _
92CS-26369RI
'NPUOs
Voo
NOTE
~
Eol~
MEASURE INPUTS
SEQUENTIALLY.
Fig. 15 -
16~/evel
EO'
priority encoder.
TO BOTH Vao &NO VSS'
Vss
CONNECT ALL UNUSm
INPUTS TO EITHER
Voo ORVSS·
Vss
114 CD4011
0 9 - -........
Fig. 14 -Input current test circuit.
08
} -......- - - - - - 0 3 '
--+-1
07
1--1------02'
1----+:-:-:--:::-.,------ 01'
00'
DO
92CS-26370RI
TRUTH TABLE
Dimensions in parentheses are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch).
The photographs and dimensions of each COS/MOS
chip represent a chip when it is part of the wafer.
When the wafer ;s cut into chips, the clpavage
angles are 57° instead of 90° with respect to the
face of the chip. Therefore. the isolated chip is
actually 7 mils (0.17 mm) larger in both dimensions.
Dimensions and pad layout for CD4532BH.
332
Input
05 04
,09
08
07
06
1
0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
1
0
0
0
0
0
0
0
X
X
X
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
Output
03
02
01
00
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
0
0
0
X
X
X
X
1
0
0
0
x '" 0 on't Care
X
X
X
1
0
0
X
X
X
1
0
X
X
X
1
GS 03' 02' 01' DO'
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
.
O~to-9
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
Logic 0= Low
Logic 1 == High
Fig. 16 -
0
0
1
1
1
1
0
0
0
0
keyboard encoder.
,
CD4536B Types
COS/MaS Programmable Timer
CLOCK
INHIBIT
L]" l
High-Voltage Types (20-Volt Rating)
1
e.BYPA:S r '_4-'--'-'-_'..J..,"
The RCA-CD4536B is a programmable timer
consisting of 24 ripple-binary counter stages.
The salient feature of this device is its
flexibility. The device can count from 1 to
224 or the first a stages can be bypassed to
allow an output, selectable by a 4-bit code,
from anyone of the remaining 16 stages, It
can be driven by an external clock or an RC
oscillator that can be constructed using onchip components. Input IN1 serves as either
the external clock input or the input to the
on-chip RC oscillator. OUT1 and OUT2 are
connection terminals for the external RC
components. In addition, an on-chip monostable circuit is provided to allow a variable pulse width output. Various timing
functions can be achieved using combi-
A fast test mode is enabled by a logic 1 on
a-BYPASS, SET, and RESET. This mode
~~
Qjv»
OUT I RT
gUT2-J
cit
0 12
SET I
R£SET 2
13 DECODE
our
"
• On-chip RC oscillator provision
MONO IN
• Clock inhibit input
92CS-:317IB
Voo ·16
• Schmitt·trigger in clock line permits operation with very
Vss· 8
long rise and fall times
FUNCTIONAL DIAGRAM
• On·chip monostable output provision
• Typical fCl = 3 MHz at VDD = 10 V
• Test mode allows fast test sequence
• Set and reset inputs
• Capable of driving two low power TTL
loads, one lower·power Schottky load, or
two HTl loads over the rated temperature
RECOMMENDED OPERATING CONDITIONS
range
• Standardized, symmetrical output charac·
nations of these capabilities.
A logic 1 on the a-BYPASS input enables a
bypass of the first a siages and makes stage 9
the first counter stage of the last 16 stages,
Selection of 1 of 16 outputs is accomplished
by the decoder and the BCD inputs A, B, C
and D. MONO IN is the timing input for the
on-chip monostable oscillator, Grounding of
the MONO IN terminal through a resistor of
10K ohms or higher, disables the one-shot
circuit and connects the decoder directly to
the DECODE OUT terminal. A resistor to
VDD and a capacitor to ground from the
MONO IN terminal enables the one-shot circuit and controls its pulse width.
~t{: I~
Features:
.24 flip·flop stages - - counts from 2° to 224
• last 16 stages selectable by BCD select code
• Bypass input allows bypassing first 8 stages
teristics
• 100% tested for quiescent current at 20 V
• 5-V, 10·V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative
Standard No. 13A, "Standard Specifi·
cations for Description of 'B' Series
CMOS Devices"
For maximum reliability, nominal operating
conditions should be selected so that operation
is always within the following ranges:
LIMITS
CHARACTERISTIC
UNITS
Min. Max,
Supply·Voltage Range
(ForTA=Full
Package Temperature
Range)
3
18
V
divides the 24-stage counter into three a·stage
sections to facilitate a fast test sequence.
The CD45368 types are supplied in 16-lead
hermetic dual-in·line ceramic packages (D
and F suffixes), 16-lead dual-in-line plastic
packages (E suffix), 16-lead ceramic flat
packages (K suffix), and in chip form (H
suffix).
DECODE OUT SELECTION TABLE
DC B A
NUMBER OF STAGES IN
DIVIDER CHAIN
8-BYPASS=0 8-BYPASS= 1
MAXIMUM RATINGS, Absolute-Maximum Values:
OC SUPPLY·VOLTAGE RANGE, (Vaal
(Voltages referenced to VSS Terminal)
-0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS
-0.5 to VDD +0.5 V
OC INPUT CURRENT, ANY ONE INPUT
±10mA
POWER DISSIPATION PER PACKAGE (POl:
0
For T A = -40 to +60 C (P.ACKAGE TYPE EI
.......
500mW
For T A = +60 to +85 0 C (PACKAGE TYPE EI
Derate Linearly at 12 mW/oC to 200 mW
For TA = -55 to +lOO o C (PACKAGE TYPES D,FI
. . . . . .
500 mW
ForTA= +100to+12SoC (PACKAGE TYPES 0, F,l
Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Typesl
100mW
OPERATING·TEMPERATURE RANGE IT AI:
PACKAGE TYPES 0, F, H
-55 to +125°C
PACKAGE TYPE E
-40 to +85 0 C
STORAGE TEMPERATURE RANGE (Tstgl
-65 to +150o C
LEAD TEMPERATURE (DURING SOLDERINGI:
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mml from case for las max.
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
9
10
11
12
1
2
3
4
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
13
14
15
16
5
6
7
8
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
17
18
19
20
9
10
11
12
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
21
22
23
24
13
14
15
16
0= low Level
1 = High level
_________________________________________________________________ 333
CD4536B Types
STATIC ELECTRICAL CHARACTERISTICS
I
LIMITS AT INDICATED TEMPERATURES (oCI
CHARACTERISTIC
CONDITIONS
Vo
(VI
Quiescent
Device
Current,
100 Max.
VIN VDD
(VI -55
(VI
-40
+85
+125
Max.
Typ.
Min.
-
0'.5
5
5
5
-
0'.10'
10'
10'
10'
30'0'
30'0'
-
0'.0'4
0'.0'4
10'
-
0'.15
15
20'
20'
60'0'
60'0'
-
0'.04
20'
0'.20'
20'
10'0'
10'0'
30'0'0'
30'0'0'
-
0'.0'8
100
0'.4
0'.5
5
0'.64
0'.61
0'.42
0'.36
0'.51
1
-
150'
150'
Output Low
(Sink) Current 0'.5
IOL Min.
1.5
0'.10'
10'
1.6
1.5
1.1
0'.9
1.3
2.6
-
0'.15
15
4.2
4
2.8
2.4
3.4
6.8
-
4.6
0'.5
5 -0'.64 -0'.61
-1
2.5
0,5
5
-2
-1.8
Output High
(Source)
Current,
IOH Min.
Output Voltage:
Low·Level,
VOL Max.
Output
Voltage:
High-Level,
VOH Min.
Input Low
Voltage
VIL Max.
Input High
Voltage,
VIHMin.
Input Current
liN Max.
-1.3 -1.15
-1.6
-3.2
-
-0'.42 -0'.36 -0'.51
9.5
0,10
10'
-':6
-1.5
-1.1
-0'.9
-1.3
-2.6
-
13.5
0',15
15
-4.2
-4
-2.8
-2.4
-3.4
-6.8
-
-
0',5
5
0'.0'5
-
0',10'
10'
0'.0'5
-
0',15
15
-
0',5
-
5
0' 0'.0'5
5
4.95
4.95
5
0',10'
10'
9.95
9.95
10'
-
D,l~
15
14.95
14.95
15
-
5
1.5
-
1,9
-
10'
3
1.5,13.5
-
15
4
-
0'.5,4.5
-
5
3.5
10'
-
15
0',18
18
tD.l
tD.l
0' 0'.0'5
-
Fig. 3-Minimum output low (sink) current
4
-
7
7
11
11
-
-
-
I
I
DRAIN-TO-SDURCE VOLTAGE lV[)s)-V
characteriselcs.
3
-
tl
V
1.5
3.5
tl
eVosl-v
mj
0' 0'.0'5
-
DRAIN-lO-SOURCE VOLTAGE
characteristics.
0'.0'5
1,9
1.5,13.5
JlA
Fig. 2- Tvpical output low (sink) current
-
0'.5,4.5
U
N
I
T
S
Values at -55, +25, +125 Apply to 0, F ,H Packages
Values at -40, +25, +85 Apply to E Package
+25
tlD-5
DRAIN- TO-SOURCE VOLTAGE (VOSI-V
V
tD.l JlA
Fig. 4- Typical output high (source) current
characteristics.
ORAIN-TO-SOURCE VOLTAGE IVDS)-V
Fig. 1 - Functional block diagram.
Fig. 5-Minimum output high (source) current
characteristics.
334 __________________________________________________________________
CD4536B Types
*
CLOCK INH
7
A
....
INPUTS PROTECTED BY COS/MOS
PROTECTION NETWORK
92CL-31725
L-____________________________________ G
Fig.6 - Logic diagram for CD4536B [continued
on next page].
__________________________________________________________________ 335
CD4536B Types
DETAIL FOR
I
R_V~f~D~~ =1; R~~I
CLENCCLDIS FOR FF9 ANDff25)
DETAIL FOR
F'I, FF21 FFIO,FF9, FF25
ff.3_-_8_,_II_-_16_,'_1-_2_4____________
l-p
,
I
I
~~====t=~~1
-=-~_
~-v
_ ~
___ ~
~
~
ffl
A
'leFFI :AS SHOWN
BI------------------+-----4
i
II
FF2,IO
~
U
FF9
FF25
EXCEPT Q NOT BROUGHT OUT
FF9~SAME AS FFI EXCEPTQ IS BROUGHT OUT AND o,lI GO TO
TGf AND TG. RESP.
FF2;FFI0: DELETE rGI,TGf,AND INVfi FEED '0 TO OJ
DELETE CLEN ,CLOIS'
FF25:INV. AND INVd BECOME 2-INPUT NAND GATES, WITH
~~~~~o~"t~TfN~~.[,Eg~L'ilt:0l1n;;~u~
._-_._---
G,--~~~~~--------------~----------~
TO.
-----
92CL-31725
Fig.6 - Logic diagram for CD4536B [continued from previous page].
336 _________________________________________________________________
CD45368 Types
DYNAMIC ELECTRICAL CHARACTERISTICS, at TA = 25°C. Input t r• tf = 20 ns.
CL
50pF. RL= 200kQ
=
VDD
CHARACTERISTIC
Propagation Delay Times:
Clock to 01. 8-Bypass High
tPHL. tpLH
Clock to 01. a·Bypass Low
tpHL. tpLH
Clock to 016.
On to On+1.
Set to On.
Transition Time.
Min.
5
10
15
5
10
15
-
-
5
10
15
TpHLtPLH
-
-
5
10
15
tpHL. tpLH
5
10
15
tpLH
Reset to On.
(V)
5
10
15
tpHL
-
5
10
15
tTHL. tTLH
Minimum Pulse Widths:
Clock
-
5
10
15
Set
5
10
15
Reset
5
10
15
Minimum Set Recovery Time.
-
-
5
10
15
Minimum Reset Recovery Time.
5
10
15
5
10
15
Maximum Clock Pulse Input
Frequency.
fCL
Maximum Clock Pulse Input
Rise or Fall Time.
t r • tf
0.5
1.5
2.5
LIMITS
Typ. Max.
UNITS
1
0.5
0.35
2.5
o.a
0.6
2
1
0.7
5
1.6
1.2
"s
4
1.5
1
a
3
2
"s
150
75
50
300
125
80
300
150
100
ns
600
250
160
ns
3
1
0.75
6
2
1.5
"s
100
50
40
200
75
50
200
100
60
200
100
80
400
150
100
400
200
120
ns
3
1
0.75
6
2
1.5
fJS
2.5
1
0.6
5
2
1.6
7
3
2
3.5
1.5
1
1
3
5
"s
LOAD CAPACITANCE· (CLI-PF
IICS-327M
Fig. 7- Typical propagation delav time as a function
of/oad capacitance (CLOCK to
8·B YPASS high).
a"
ns
ns
LOAD CAPACITANCE ICI..)-pF
92CS-32769
Fig. 8- Typical propagation delay time as a function
of/oad capacitance (CLOCK to
8·BYPASS low).
a"
"s
"s
-
-
MHz
5.10.15
Unlimited
. 16
SET
RESET
IN I
OUT I
15
CLOCK INHIBIT
VSS
VDD
MONO IN
3
14
OSC INHIBIT
4
13
DECODE OUT
OUT 2
B -BYPASS
12
6
11
7
10
B
9
"s
~}
B
BINARY
SELECT
A
TOP VIEW
Terminal Assignment
92CS-31716
LOAD CAPACITANCE ICLI-pF
Fig. 9-Typical propagation delay lime as a
function of load capacitance (CLOCK
to 01& 8·BYPASS high).
_______________________________________________________________________ 337
CD4536B Types
AMBIENT TEMPERATURE (TAl. 25°C
' '"':
LOAD CAPACITANCE (CL.I-pF
102
Uet-U7n
SUPPLY VOLTAGE(VOOJ- V
'ZCS-327'71
Fig. 10-Typical propagation delay time as a
function of load capacitance (aN to
aN+1)'
2:
"6 BI03
2
" 6 ~04
2:
..
" . "0'
10'
EXTERNAL CAPACITANCE (Cxl- pF
Fig. 11-Typical RCoscillator frequency de·
viation as a function of supply
voltage.
EXTERNAL RESISTANCE (Rtc1-k.o
12CS-l277!
Fig. 12-Typical RC oscillator frequency devia·
tion as a function of time constant
resistance and capacitance.
"
SUPPLY VOLTAGE IVoolz5 V
RS·2Rlc
AMBIENT TEMPERATURE(TAI-·C
AMBIENT TEMPERATURE(TAJ -"C
Fig. 13-Typical RC oscillator frequency devia·
tion as a function of ambient temper'
ature (RS = 0).
"
SUPPLY VOLTAGE (Vool-IO II
12CS-3zn,
Fig. 14-Typical RC oscillator frequency deviation as a function of ambient
temperature (RS = 120 I2)
0001{.4)
0010(,8)
-+---......
_____Jr
_+_____..JJ'"C-=-:=-==-=-:L
lrL..
..JL NOTE,
SHADED PULSE REPRESENTS DECODE OUTPUT
IN MONOSTABLE MODE. IF AN OUTPUT PULSE
IS REQUIRED I FULL-COUNT-DOWN AFTER
REMOVAL OF RESET PULSE, SEE FIG. 31 FOR
R1L
USE OF CD4098B.
C:~E~
O~~~~~ n
CD4098St----------'
Fig_31 -CD45368 Timing Diagram.
L----.-2-CS-_-.2-7--.4
Fig.30 - Application showing use of
CD40988 and CD45368 to get
decode pulse 8 clock pulses
after Reset pulse.
Dimensions and pad layout for CD45368H.
Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions as ffdicated. Grid graduations are in
mils (10- inch).
The photographs and dimensions represent a
chip when It is part of the wafer. When the
wafer is cut into chips, the cleavage angles are
57· instead of 90· with respect to the face of
the chip. Therefore, the Isolated chip is actually 7 mils (0.17 mm) larger In both dimensions.
340
92CM-327B7
Prelimin~ry
CD4538B Types
Data
COS/MaS Dual Precision
Monostable Multivibrator
"XI
rlt-........I\II,f\r-- Voo
• 0,
High-Voltage Types (20-Volt Rating)
7
The RCA-C04538B dual precision
monostable multivibrator provides stable
retriggerable/resettable one-shot operation for any fixed-voltage timing application.
An external resistor (RX) and an external
capacitor (CX) control the timing and accuracy for the circuit. Adjustment of RX
and Cx provides a wide ranQl! of output
pulse widths from the Q and Q terminals.
The time delay from trigger input to output transition (trigger propagation delay)
and the time delay from reset input to output transition (reset propagation delay)
are independent of RX and CX. Precision
control of output pulse widths is achieved
through linear CMOS techniques.
Leading-edge-triggering (+ TR) and
trailing-edge-trlggering (- TR) inputs are
provided for triggering from either edge of
an input pulse. An unused + TR input
should be tied to VSS. An unused - TR input should be tied to Voo. A RESET (on
low level) is provided for immediate termination of the output pulse or to prevent
output pulses when power is turned on.
An unused RESET input should be tied to
VOO. However, if an entire section of the
C04538B is not used, its inputs must be
tied to either VOO or VSS. See Table I.
In normal operation the circuit triggers
(extends the output pulse one period) on
the application of each new trigger pulse.
Features:
• Retriggerablelresettable capability
• Trigger and reset propagation delays
independent of RX, Cx
• Triggering from leading or trailing edge
• Q and "0 buffered outputs available
• Separate resets
• Wide range of output-pulse widths
• Schmitt trigger input allows unlimited
rise and fall times on + TR and - TR inputs
• 100% tested for maximum quiescent
current at 20 V
For operation in the non-retrlggerable
mode, Q is connected to - TR when
leadlng-edge triggering (+ TR) is used or
Q is connected to + TR when traillngedge triggering (- TR) is used. The time
period (T) for this multivibrator can be
calculated by: T = RXCX.
The minimum value of external
resistance, RX, is 4 KQ. The maximum and
minimum values of external capacitance,
CX, are 100,..F and 5000 pF, respectively.
The C04S388 types are supplied in 16-lead
hermetic dual-in-line ceramic packages (0
and F suffixes), 16-lead dual-i n-line plastic
packages (E suffix), 16-lead ceramic flat
packages (K suffix), and in chip form (H
suffix).
The C04538B is similar to type MC14538
and is pin-for-pin compatible with the
C04098B.
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (VDD)
(Voltages referenced 10 VSS Terminal) ...................................... - 0.510 + 20 V
INPUT VOLTAGE RANGE,ALLINPUTS ................................... -0.510 VDD +0.5V
DCINPUTCURRENT,ANYONEINPUT ............................................. ±10mA
POWER DISSIPATION PER PACKAGE (PO):
ForTA= -4010 +60'C(PACKAGETYPEE) ....................................... 500mW
ForTA= +6010 +85'C(PACKAGETYPE E) ............ Derale LlnearlyaI12mW/'CI0200mW
ForTA= -5510 + l00'C (PACKAGE TYPES D,F) ................................... 500mW
ForTA= +10010 + 125'C (PACKAGE TYPES D,F) ....... Derale Llnearlyal12 MW/'Clo 200mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ................ 100 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGETYPESD,F,H ................................................. -5510 +125'C
PACKAGETYPEE ....................................................... -4010 +8S'C
STORAGE TEMPERATURE RANGE(Tslg) ..................................... -6510 + 150'C
LEAD TEMPERATURE (DURING SOLDERING):
AI dlslance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case lor IDs max ........ , ......... +265'C
OJ
'1t"......"V'>I\r- Voo
VOO-16
vss-e
CX2
CD4538B
RX2
92CS-242S3
Functional Diagram
• Maximum input current of 1 ,..A at
18 Voyer full package-temperature
range; 100 nA at 18 V and 25'C
• Noise margin (full package-temperature
1 Vat VOO
5 V
range):
2 Vat VOO= 10 V
2.5 Vat VOD= 15 V
• 5-V, 10-V, and 15-V parametric ratings
• Standardized, symmetrical output
characteristics
• Meets all requirements of JEOEC
Tentative Standard No. 13B, "Standard Specificatlqns for Oescription of 'B'
Series CMOS Devices."
Applications:
• Pulse delay and timing
• Pulse shaping
=
e Xi
RXC)(tll
RESET(t}
I.
2
+TR III
-TR (,II
01
I.
I.,.
13
12
"
or
10
Vss
Voo
ex>
RX Cx l21
RESETI21
+TR 12J
-TRill
02
ii2
TOP VIEW
TERMINALS 1,8,IS ARE
ELECTRICALLY CONNECTED
INTERNALLY
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected
so that operating Is always within the following ranges:
CHARACTERISTIC
VDD
V
Supply-Voltage Range (For T A =
Full
Package-Tempera! ure
Range)
-
LIMITS
MIN_
MAX,
5
18
TERMINAL ASSIGNMENT
UNITS
V
341
CD4538B Types
STATIC ELECTRICAL CHARACTERISTICS (Not Applicable to Pins 2 and 14)
CHARAC·
TERISTIC
-
LIMITS AT INDICATED TEMPERATURES (OC)
Values at - 55, + 25, + 125 Apply to D,F,H Pkgs.
UNITS
Values at -4O,+25,+85ADDI toEPIas.
VIN I"DD
+25
(V) (V) -55 -40 +85 +125 Min.
Typ.
Max.
0,5 5
5
5
150
150
0.04
5
0,10 10
10
10
300
300
0.04
10
,.A
0,15 15
20
20
600 600
0.04
20
0,20 20 100
100 3000 3000
0.08
100
0.4
0.5
1.5
05 5
0,10 10
0,15 15
CONDITIONS
Vo
(V)
Quiescent
Device
Current
100 Max.
Output Low
(Sink)
Current,
IOlMin.
Output High
(Source)
Current,
IOHMin.
Output Volt·
age:
Low·Level,
VOL Max.
Output Volt·
age:
Hlgh'Level,
VOH Min.
Input Low
Voltage,
Vil Max.
Input High
Voltage,
VIH Min.
Input
Current,
liN Max.
4.6
2.5
9.5
13.5
'
-
0,5
05
0,10
0,15
0.61
1.5
4
5 -0.64 -0.61
-2
5
-1.8
10 -1.6 -1.5
15 -4.2
-4
0.42
1.1
2.8
0.36
0.9
2.4
0.51
1.3
3.4
1
2.6
6.8
-0.42
-1.3
-1.1
-2.8
-0.36
-1.15
-0.9
-2.4
-0.51
-1.6
-1.3
-3.4
-1
-3.2
-2.6
6.8
-
0
0
0
0.05
0.05
0.05
5
10
15
-
-,
-
0,5 5
0,10 10
0,15 15
0.05
0.05
0.05 '
-
05 5
0,10 10
0,15 15
4.95
9.95
14.95
4.95
9.95
14.95
1.5
3
4
-
3.5
3.5
-
0.5,4.5
1,9
1.5,13.5
-
5
10
15
0.5,4.5
1,9
1.5,13.5
-
5
10
15
-
0,18 18
Fig. 1 -
342
0.64
1.6
4.2
±0.1
±O.l
7
7
11
11
±1
±1
-
Logic diagram (II. of device shown).
-
-
-
1.5
3
4
-
±10-5 ±0.1
rnA
V
V
,.A
CD4538B Types
DYNAMIC ELECTRICAL CHARACTERISTICS
At TA=25; Input t,.tf= 20 ns. CL=50pF
CHARACTERISTIC
Transition Time
tTLH.tTHL
Propagation Delay Time:
+ TRor - TRto aorO
tPLH.
tPHL
Reset to a or a
Minimum Input Pulse Width:
+ TR. - TR or Reset
tWH.
tWL
Output Pulse Width - a or a:
Cx =0.005 "F. RX=10 KQ
T
CX=0.1 "F. RX=100 KQ
CX=10"F. RX=100 KQ
Pulse Width Match between 100(T1- T2)
circuits in same package:
T1
CX=0.1 "F, RX= 100 KQ
TEST CONDITIONS
VOO (V)
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
LIMITS
Typ.
100
50
40
300
150
100
250
125
95
35
30
25
58
55
55
9.86
10
10.14
0.965
0.98
0.99
±1
±1
±1
UNITS
ns
"s
ms
s
%
TABLE I
CD4538B FUNCTIONAL TERMINAL CONNECTIONS
f'"U,NCTION
Le"ding-Edge
Trigger!
Retriggerable
Leading-Edge
'Trigger/Nonretriggerable
Trailing-Edge
Triggerl
Retrlggerable
Trailing-Edge
Trigger/Nonretriggerable
INPUT PULSE
OTHER
VODTO
VSSTO
TERM. NO.
TERM. NO.
TO TERM. NO.
CONNECTIONS
MON01 MON02 MON01 MON02 MON01 MON02 MON01 MON02
3,5
11. 13
4
12
3
13
4
12
3
13
5
11
3
13
5
11
4
NOTES:
1. Pi RETRIGGERABLE ONE·SHOT MULTI·
VIBRATOR HAS AN OUTPUT PULSE
WIDTH WHICH IS EXTENDED ONE FULL
TIME PERIOD (T) AFTER APPLICATION
OF THE LAST TRIGGER PULSE.
12
5-7
11-9
4-6
12-10
INPUT PULSE TRAIN
RETRIGGERABLE MODE PULSE
WIDTH (+ TR MODE)
...J
2. A NON·RETRIGGERABLE ONE·SHOT
MULTIVIBRATOR HAS A TIME PERIOD
NON·RETRIGGERABLE MODE
(T) REFERENCED FROM THE APPLI·
PULSE WIDTH
CATION OF THE FIRST TRIGGER PULSE. (+ TR MODE)
_______________________________________________________________________ 343
CD4555B, CD4556B Types
COS/MOS
Dual Binary to 1 of 4
Decoder/Demultiplexers
High-Voltage Types (20-Volt Rating)
CD4555B: Outputs High on Select
CD4556B: Outputs Low on Select
The RCA-CD4555B and CD4556B are dual
one-of-four decoders/demultiplexers. Each
decoder has two select inputs (A and B), an
Enable input (E), and four mutually exclusive outputs. On the CD4555B the outputs
are high on select; on the CD4556B the out·
puts are Iowan select.
When the Enable input is high, the outputs
of the CD4555B remain low and the output!
of the CD4556B remain high regardless of
the state of the select inputs A and B. The
CD4555B and CD4556B are similar to types
MC14555 and MC14556, respectively.
The CD4555B and CD4556B types are supplied in 16-lead hermetic dual-in-line ceramic packages (D and F suffixes), 16-lead
dual-in-line plastic packages (E suffix), 16lead ceramic flat packages (K suffix), and in
chip form (H suffix).
•
•
E
Features:
-
00
01
· 02
I
7 O.
12 00
Expandable with multiple packages
Standard, symmetrical output characteristics
100% tested for quiescent current at 20 V
Maximum input current of 1 p.A at 18 V over full
package tem perature range; 100 nA at 18 V and 25° C
II 01
10 02
9 O.
- Noise margin (full package·temperature
range): 1 Vat VDD = 5 V
2VatVDD=10V
2.5VatVDD=15V
- 5·V, 10-V, and 15·V parametric ratings
- Meets all requirements of JEDEC Tentative
Standard No. 13A, "Standard Specifications
for Description of '8' Series CMOS Devices"
CD4555B
FUNCTIONAL DIAGRAM
Applications:
- Decoding
- Code conversion
- Demultiplexing (using Enable input asa
data input)
- Memory chip·enable selection
- Function selection
E
I
IR>
Qi
12
II
10
Q2
9
03
•
Vss 92CS-22919AI
CD4556B
FUNCTIONAL DIAGRAM
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be $Sleeted
so that operation is always within the lol/owing ranges.
CHARACTERISTIC
Supply Voltage Range
(For T A = Full Package
Temp. Range)
V DO
MIN.
MAX.
UNITS
-
3
18
V
TERMINAL ASSIGNMENTS
I.
1120Ffl
or
I.
"
I.
. DUAL
Q2
Q3
or
10
9
lI2'
I5'l'
"
vss
MAXIMUM RATINGS,
Absolute-Maximum Values:
r}D
1120F
lSO'
"
"
DUAL
TOP VIEW
92CS-Z4943RI
DC SUPPLY·VOLTAGE RANGE, (VDDI
(Voltages referenced to VSS Terminal)
INPUT VOLTAGE RANGE, ALL INPUTS
DC INPUT CURRENT, ANY ONE INPUT
POWER DISSIPATION PER PACKAGE (POl:
For TA = -40 to +GOoC (PACKAGE TYPE EI
" . . . . . . .•
500mW
For T A = +60 to +85 0 C (PACKAGE TYPE EI
.
Derate Linearly at 12 mW/oC to 200 mW
For TAo -55 to +IOOoC (PACKAGE TYPES D.F .. I
. . . . . . . ,.
500mW
For TA = +100 to +125 0 C (PACKAGE TYPES D, F, I
Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE·TEMPERATURE RANGE (All Package Types)
l00mW
OPERATING·TEMPERATURE RANGE IT AI:
PACKAGE TYPES 0, F, ,H'
-55 to + 125°C
PACKAGE TYPE E . . . , . . . . . . . . . . .
-40 to +850 C
STORAGE TEMPERATURE RANGE (Tstgl
..... .
-65 to +1500 C
LEAD TEMPERATURE (DURING SOLDERINGI:
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 105 max.
344
CD4556B
...{l,5 to +20 V
...{l,5 to VDD +0.5 V
±10mA
t'
A
112 OF'
B
DUAL QO
01
02
O.
I.•
,.
I. !
"
13
4
•
"
"1
00
01
" O.
O.
10
Vss
lOP VIEW
9ZCS-Z4942RI
CD4555B
112 OF
DUAL
•
CD45558, CD45568 Types
STATIC ELECTRICAL CHARACTERISTICS.
CHARACTER·
ISTIC
, Vo
(V)
VIN
-
0,5
0,10
0.15
0.20
0.4
0.5
1.5
4.6
2.5
9.5
13.5
0,5
0,10
0,15
0,5
0,5
0.10
0.15
Quiescent Device
-
Current,
100 Max.
Output low
(Sink) Current
IOlMin.
Output High
(Source)
Current,
IOH Min.
LIMITS AT INDICATED TEMPERATURES (DC)
Value. at -55, +25, +125 Apply to D.. F,H Packages
Values at -40, +25, +85 Apply to E Package
UNITS
+25
VDD
+85
+125 Min.
Typ. Max.
(V) -55 -40
0.04
5
150
5
5
5
150
0.04
10
10
10
300
300
10
p.A
0.04
20
20
600
600
15
20
0.08
100
100
100
3000 3000
20
1
0.42
0.36 0.51
5
0.64 0.61
2.6
1.5
1.1
0.9
1.3
10
1.6
34
6.8
4
2.8
2.4
15
4.2
mA
-1
-0.64 -0.61 -0.42 -0.36 -0.51
5
-3.2
-2 -1.8
-1.3 -1.15 -1.6
5
-2.6
-1.1
-0.9 -1.3
10 -1.6 -1.5
-2.4 -3.4
-6.8
-2.8
15 -4.2 .-4
-
(VI
Output Voltage:
low·level,
VOL Max.
-
0,5
5
-
Output Voltage:
High·level,
VOH Min.
-
0,10
0,15
0,5
0,10
0,15
10.
15
5
10
15
0.5,4.5
1,9
1.5,13.5
0.5,4.5
1,9
1.5,13.5
-
5
10
15
5
10
15
0,18
18
Input low
Voltage,
Vil Max.
Input High,
Voltage,
VIH Min.
11
CONDITIONS
Input Current
liN Max.
0.05
0.05
0.05
4.95
9.95
14.95
±0.1
±0.1
-
a
0.05
-
0
a
4.95
9.95
14.95
5
10
15
0.05
0.05
-
-
-
1.5
3
-
4
1.5
3
4
3.5
3.5
7
-
-
7
11
11
-
-
-
±10- 5
±0.1
±1
±1
DYNAMIC ELECTRICAL CHARACTERISTICS at TA
,I
il
DRAIN-TO-SOURCE VOLTAGE IVOSI-V
Fig. 1 - Typical output low (sink) current
characteristics.
:RAlli'
.NT
I~
,'C
H!
!f. ,
v
Iii;
III
t
I~
II ..
ORAIN-TO-SOURCE VOL.TAGE (Vpsl-V
Fig. 2 - Minimum output low (sink) current
characteristics.
-
DRAIN-lO-SOURCE VOLTAGE (Vosl-V
p.A
=25" C; Input t,. tf =20 ns.
CL =50pF,RL =200Kn
TEST CONDITIONS
CHARACTERISTIC
ALL TYPES
LIMITS
UNITS
V DD
Fig. 3 - Typical output high (source) current
characteristics.
Volts
TYP,
MAX.
5
220
440
10
15
95
190
Any Output
70
140
E Input to Any
5
10
200
85
400
170
15
65
130
5
10
100
50
200
100
ns
15
40
5
80
7.5
pF
Propagation Delay Time, tpH L,
tpLH
A or B Input to
Output
Transition Time tTHL' tTLH
Input Capacitance C)N
Any Input
ns
DRAIN-tO-SOURCE VOLtAGE {VOSI-V
-I~
-10
-~
AMBIENT TEMPERATURE ITAI·2!!1·C
mil
ns
-tOY
••
f
i"
1 .....
H-;!
:t
!:
·0
Fig. 4 - Minimum output high (source) current
characteristics.
345
CD4555B, CD4556B Types
.
* ALL INPUTS PROTECTED
By COS/MOS
"~'", "'~""4
Vss
'2CS-2'4222RI
5 - C04556B logic diBgrtlm
Fig.
Fig.
(1 of 2 identical circuits).
6 - C04555B logic diagram
" of 2 identical circuits}.
TRUTH TABLE
INPUTS
OUTPUTS
ENABLE SELECT
CD4555B
E
B
A
0
0
0
0
0
1
0
0
03 02 01 00
0
0
0
1
OUTPUTS
CD4556B
03 02 01 00
1
1
0
1
1
1
1
0
0
1
0
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
0
0
0
1
1
1
1
X
X
0
0
0
0
1
1
1
1
X = DON'T CARE
=
LOGIC 1 HIGH
LOGIC 0= LOW
Fig. 1 - Typical propagation delay tima ... load
capecitance (A or B input to eny output).
,
SUPPLY VOLTAGE I VDoJ-VOl.TS
l.OID (ANCITANCE ICLI- pF
Fig. 8 - 'typIcal propagation delay time ... loed
capecitance (E input to any output).
Fig. 9 - Typical propagation delay time .....
supply voltage.
Fig. ,10':" Typical transition tima "./oed
..
capacitance.
VDD
.
INPUTS
Vss
,.PUTQVCOOUTPUT'
VOH
~
'--
J
V~L
NOTE:;
"I
2
4 "I~
2
.. "1022
.. ",10]2
.. 6'10"
Vss
Vss
.
~srN",N~~OMB'NAT1ON
INPUT FREQUENCY 'ti-kHz
92CS-2744IR'
Fig. 11 - Typical dynamic power diuipetion
111'. frequency.
.
346
Fig. 12 - Quiescent device current test
circuit.
Fig. 13 - Input voltage test circuit.
CD4555B, CD4556B Types
V~NPU(JS
Voo :~:~URE IN. PUTS
o ~
90%
---I--J::=::::lj,~-t--
50"1.
------j----JL------"L--
90~ ----t-~~=~
SEQUENTlAL.LY,
TO BOTH YOO ANO Y55'
Vss
____ V55
10%
===~~------+~~
90%
======~k-~------~JC
CONNECT ALL uNUSED
INPUTS TO EITHER
VSS
'0'00 OR Y55
90%
Fig. 74 - Input current test circuit.
'0%
10 ",.
--------~~==~~---
-----~~t_--~~
0'
10 .. ------~----''k__--~
===,jL-l-+---+--~,-
vss
I f ' I MHl. 50 "I. DUTY CYCLE
'1'1 MHz, 50"1. DUTY CYCLE
Fig. 16 - CD45568 8 input to Q3 output dynamic
Fig. 15 - CD45558 8 input to 03 output dynamic
signal waveforms.
signal waveforms.
90~ ----~---Jc=~t=--t------50 "I.
10 %
Voo
-'0'00
90'.
----+,f---------''Ir
INPUT
50%
----fr-+------:-J.--C''Ir
V55
I
APPLICATIONS
10 "'"
V55
[
INPUTS SELECT
90 "I.
====>l.-l----------hlc
50 "I. --------+'''k---------~I
Voo
OUTPUT
-------t----'j;.:=~~--l--- Vss
SELECT
INPUTS
0;
10"'.
QI
02
3
03
OUTPUTS
92CS- 24229
OUTPUTS
V55
t I -I MHz. 50
"I.
A
a a
a 1
1
a
DUTY CYCLE
1
Fig.
Fig. 18 - CD45568'if input to 03 output dynamic
GO
01
02
03
DATA
a
a
a
a
DATA
a
a
DATA
a
a
a
a
DATA
1
a
a
19 - l-of41me data demultiplexer usmg
CD4555B.
signal waveforms.
signal waveforms.
01
02
TRUTH TABLE
'0","
':tzcs- 2422~
Fig. 17 - CD45558 E input to 03 output dynamic
B
_
B
E
1/6 C040696
B
I I • I MHz, 50 "I. DUTY CYCLE
C04"S~0 a~
GA~"2
DATA
voo
90"1.
0'
10 %
Voo
50%------~~k_------~1
TRUTH TABLE
o OUTPUTS
INPUTS
00
C B A
QI
a
02
Q'
OUTPUTS
DECODER
INPUTS
Q'
Q'
00
or
a
1 2 3 4 5 6 7
0 a 1 a
0 0 1 0 1
0 1 0 0 a
0 1 1 0 0
1 0 0 0 0
1 0 1 0 a
1 1 0 a a
1 1 1 a a
a a a a a a
0 0 0
1 0 0
0 1 0
0 0 1
0 a a
0 0 0
a a a
0 0 0
0 0 0
a 0 0
0 0 0
1 0 a
0 1 a
0 a 1
Fig. 20 - 1-of.lJ decode, using CD4555B.
347
CD4555B, CD4556B Types
'RUTHTARI
OOU,....,,.
I....,.
DECODER
INPUTS
£ D
o 0
o 0
o 0
o 0
o 0
o 0
o 0
o 0
0 I
0 I
o I
0 I
0
0 I
0 I
C • A 0 I , 3 .. & • 7 •
o
o
o
0
I
I
I
I
o
o
0
, ,o
,
,
,
0
0
I
I
0
0
I
I
0
0
I
I
0
0
I
0
I
o
I
o
I
o
I
o
I
o
I
o
I
o
, XI X XI 0I
0
I 0
I
0 o
o 0
0 o
0 o
0 o
0 o
0 o
0 o
0 o
o 0
0 o
0 o
0 o
o
0
0
o
o
0
0
I
0
0
0
0
0
0
0
0
0
0
0
0
0
0
000000
000000
000000
100000
010000
00'000
a00100
000010
000001
000000
000000
000000
000000
000000
000000
o 0 Q 0 o 0 0
Q 0 0 0 o 0 0
13
0
0
0
0
0
0
0
0
0
0
0
0
0
10
0
0
0
0
0
0
0
0
0
0
I
0
0
0
0
tI
0
0
0
0
0
0
0
0
0
0
0
I
0
0
0
"
0
0
0
0
0
0
0
0
0
0
0
"0
0
0
0
0
0
0
0
0
0
0
0
0
0
,,
0
0
tI
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I
0
X-donIU"
Fig. 21 - 1-0(·16 decoder using CD45558 and
CD45568.
.a-Z4,ZZ
DIMENSIONS AND PAD LAYOUT FOR
CD4555BH. (Dimensions and pad layout for
CD45568H are identical).
Dimensions in parentheses are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mifs (10-3 inch),
The photographs and dimensions of each COS/MOS
chip represent a chip when it is part of the wafer.
When the wafer is cut into chips, the cleavage
angles are 57° instead of 90° with respect to the
face of the chip. Therefore. the isolated chip ;s
actually 7 mils (0. 17 mm) larger in both dimensions,
348 ________________________________________________________________
~
__
CD4585B Types
COS/MOS 4-Bit Magnitude
Comparator
..
AO
High Voltage Types (20-Volt Rating)
The RCA-CD4585B is a 4-bit magnitude comparator designed for use in computer and
logic applications that require the comparison
of two 4-bit words. This logic circuit determines whether one 4-bit word (Binary or
BCD) is "less than". "equal to". or "greater
than" a second 4-bit word.
The CD4585B has eight comparing inputs
(A3. B3. through AD. BO). three outputs (A
B) and three cascading inputs
(A < B. A = B. A> B) that permit systems
designers to expand the comparator function
to 8. 12. 16 ...... .4N bits. When a single
CD4585B is used. the cascading inputs are
connected as follows: (A < B) = low, (A = B)
= high. (A> B) = high.
Cascading these units for comparison of more
than 4 bits is accomplished as shown in
Fig. 13.
The CD4585B types are supplied in 16-lead
hermetic dual-in-Iine ceramic packages (D
and F suffixes), 16-lead dual-in-Iine plastic
packages (E suffix). 16-lead ceramic flat
packages (Ksuffix), and in chip form (H
suffix). This device is pin-compatible with
low-power TTL type 7485 and the CMOS
types MC14585 and 40085.
10
WORO"A- { A I
7
A3
15
13 A>8
A'B 4
Features:
CASCADING { A-a
INPUTS
- Expansion to 8.12.1S...... 4N bits by cascading units
- Medium-speed operation:
compares two 4-bit words
in 180 ns (typ.) at 10 V
- 100% tested for quiescent current at 20 V
- Standardized symmetrical output characteristics
- 5-V. 10-V. and 15-V parametric ratings
- Maximum input current of 1 f1A at 18 V
over full package temperature range;
100 nA at 18 V and 25°C
- Noise margin (full package temperature range)
range) =1 Vat VDD =5 V
2 V at VDD = 10 V
2.5 V at VDD = 15 V
_ Meets all requirements of JEDEC Tentative
Standard No. 13A. "Standard Specifications
for Description of 'S' Series CMOS Devices"
3 A-B
12 A 60
AO=60
AO=60
AO= 60
0
0
1
0
1
0
x
x
x
x
x
1
X
X
X
X
X
X
A3 = 63
A3 = 63
A3= 63
A2 =B2
A2 =B2
A2 =B2
A1 = 61
A1 = 61
A1 = 61
A3= 63
A3= 63
A3= 63
A3< 63
A2 = B2
A2 = 62
A2<62
A1 = 61
A1 <61
AOB
1
1
1
1
A1>61
A1 = 61
x
A=B
X
X
X
X
A2> 62
A2 = 62
A2= 62
X
A 63
A3= 63
A3= 63
A3 = 63
x
OUTPUTS
CASCADING
x
x
x
x
x
x
Logic 1 :::: High Level
AB
0
0
0
0
1
1
1
1
0
0
1
0
1
0
1
0
0
1
1
1
1
0
0
0
0
0
0
0
0
Logic 0 :::: Low Level
~ffVDO
~VSS
* INPUTS
PROTECTED BY
COSIMOS PROTECTION
NETWORK
IABIIN
(AcB)lN
(A-BItN
AI
•
•
16
V DD
I.
A3
B3
(A,.BIOUT
13
12
"
10
IAc.B}OUT
BO
AD
BI
V.s
TOP VIEW
92CS-31006
Dimensions and Pad Layout for CD4585BH
The photographs and dimensions represent
a chip when it is part of the wafer. ",urn the
Dimensions in parentheses are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils "0- 3 inch).
wafer is
are 57°
face of
chip is
cut into chips, the cleavage angles
instead of 90° with respect to the
the chip. Therefof'lJ. the isolared
actually 7 mils (0.17 mm) ISrgtJf
in both dimensions.
352 __________________________________________________________________
CD4724B Types
COS/MOS
8-Bit Addressable Latch
High-Voltage Types (20-Volt Rating)
Features:
The RCA-CD4724B 8-bit addressable latch
is a serial-input, parallel-output storage register that can perform a variety of fu nctions_
•
-
Data are inputted to a particular bit in the
latch when that bit is addressed (by means
of inputs AO, Al, A2) and when WRITE
DISABLE is at a low level. When WRITE
DISABLE is high, data entry is inhibited;
however, all 8 outputs can be continuously
read independent of WRITE DISABLE and
address inputs_
A master RESET input is available, which
resets all bits to a logic ·0· level when RESET
and WRITE DISABLE are at a high level.
When RESET is at a high level, and WRITE
DISABLE is at a low level, the latch acts as
a 1-of-8 demultiplexer; the bit that is addressed has an active output which follows
the data input, while all unaddressed bits
are held to a logic ·0' level.
The CD4724B types are supplied in l6-lead
hermetic ceramic.dual-in-line packages (D
and F suffixes), l6-lead plastic dual-in-line
packages (E suffix), l6-lead ceramic flat
packages (K suffix), and in chip form (H
suffix).
WRITE DISABLE
DATA----"'I
Serial data input
- Active parallel output
Storage register capability
- Master clear
Can function as demultiplexer
Standardized, symmetrical output characteristics
100% tested for quiescent current at 20 V
Maximum input current of 1IJA at 18 V
(full package-temperature range), 100 nA
at 18 V and 25 0 C
- Noise margin (full package-temperature
range) = 1 Vat VDD = 5 V, 2 Vat VDD
FUNCTIONAL DIAGRAM
= 10 V, 2_5 V at VDD = 15 V
- 5-V, 10-V, and 15-V parametric ratings
Applications:
- Meets all requirements of JEDEC Tentative
_ Multi-line decoders
Standard No_ 13A, "Standard Specifications
for Description of 'B' Series CMOS Devices"
- AID converters
MAXIMUM RATINGS, Absolute-Maximum Values:
OC SUPPLY-VOLTAGE RANGE. IVODI
-0.5 to +20 V
(Voltages referenced to VSS Terminal)
-0.5 to VDD +0.5 V
INPUT VOLTAGE RANGE, ALL INPUTS
±10mA
DC INPUT CURRENT, ANY ONE INPUT
POWER DISSIPATION PER PACKAGE IPD):
. . . . . . . ..
500mW
For TA = -40 to +60 o C (PACKAGE TYPE E)
Derate Linearly at 12 mW/oC to 200 mW
For T A = +60 to +85 0 C (PACKAGE TYPE E)
.
. . . . . . . ..
500mW
For TA = - 55 to +1000 C (PACKAGE TYPES D,FI
Derate Linearly at 12 mW/oC to 200 mW
For TA = +100 to +125 0 C (PACKAGE TYPES D, F)
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
100mW
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types)
OPERATING-TEMPERATURE RANGE (TAl:
-55 to +1250 C
PACKAGE TYPES D, F, H
-40 to +85 0 C
PACKAGE TYPE E .
-65 to +1500 C
STORAGE TEMPERATURE RANGE (Tstgl
LEAD TEMPERATURE (DURING SOLDERINGI:
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mml from case for 105 max.
QO
*
.
Ai
AO~AO
*
01
AI
AI~~
"
AI
Il*
n
A2~AZ
DATA6-{>o--{)o-- 0
IS
AI
IS
vDO
RESET
WRITE DISABLE
A2
I.
00
13
DATA
01
12
07
as
02
OZ
Al)
2
AD
a.
AI
10
a.
A.
Vss
O.
TOP VIEW
Ai
TERMINAL ASSIGNMENT
AI
06
AI
WRITE
DISABLE
WO
07
,.*
RESET
0---[:>0---[»-
R
ADDRESS
WO
OO
*PROTECTED
ALL INPUTS ARE
BV
~
COS/MOl PROTECTION
NETWORK
OATA
---+-+1
DRAIH-TO-SOURCE VOLTAGE (VDsI-V
Vss
Fig. 1- Logic diagram of C047248 and detail of , of Blatches.
Fig_
2- Tvpical output low 'sink)
current characteristiC£.
353
CD4724B Types
RECOMMENDED OPERATING CONDITIONS at TA = 25" C (Unl_ otherwisa $pfICifiedJ
For maximum reliability, nominal oparating conditions should be salacted 80 that oparation
is always within the following ranges.
CHARACTERISTIC
SEE
VDD
FIG. 15·
lVI,
Supply Voltage Range:
(At TA = Fu" Package
Temperature Range)
Pulse Width, tw
0
Data
Address
CD
0
Reset
Setup Time, ts
Data to WRITE DISABLE
Hold Time, tH
Data to WRITE DISABLE
0
G
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
LIMITS
MIN.
MAX.
3
18
200
100
80
400
200
125
150
75
50
100
-
50
-
35
150
75
50
-
UNITS
MODE SELECTION
ADDRESSED UNADDRESSED
WD R
LATCH
LATCH
0
0 Fo"ows Data Holds Previous
0
1 Fo"ows Data
V
1
1
State
Reset to ·0·
tctive High 8hannel
Demultiplexer)
Holds Previous State
0
1 Reset to ·0· I Reset to ·0·
R- RESET
WD = WRITE DISABLE
ns
-
-
92CS-Z7t7IRI
ns
Fig. 3- Definition of WRITE DISABLE ON time.
ns
• Circled numbers refer to times indicated on master timing diagram.
Note: In addition to the above characteristics, a WRITE DISABLE ON time (the time that WRITE
DISABLE is at a high level) must be observed ""ing an address change for the toteltime that the
external addre.. linas AO, A1, and A2 are satding to a stablelavel, to prevent a wrong cell from
beingad~""r-_d~.______________~~________________________________________- ,
""N-'ro-"eu"C' VOLTAGE IVos)-Y
Fig. 4- Minimum output loW' (,ink)
current charllCtllri,ticl.
START
CONVERSION
DRAIN-TO-SOURCE VOLTAGE IVosI-V
*
CD4001
• HYCDMP HC210SLD- 2R
OR EQUIYALENT
.N~~~~
______________________________
~
Fill.6 - Typical output high (sou,")
currtlnt ch"'lICI.8J'i.tit:s.
Fig. 5- AID conllflrter
354 _______________________________________________________________
CD4724B Types
STATIC ELECTRICAL CHARACTERISTICS
LIMITS AT INDICATED TEMPERATURES (OC)
Value. at -55, +25, +125 Apply to D,F ,H Package.
Value. at -40, +25, +85 Apply to E Package
CONDITIONS
CHARACTER·
ISTIC
Ouiescent Device
Current,
IDD Max.
Vo
(V)
-
Output Low
(Sink) Current
IOL Min.
Output High
(Source)
Current,
IOH Min.
Output Voltage:
Low·Level,
VOL Max.
Output Voltage:
High·Level.
VOH Min.
Input Low
Voltage,
VIL Max.
Input High
Voltage,
VIH Min.
Input Current
liN Max.
0.4
0.5
1.5
4.6
2.5
9.5
13.5
VIN VDD
(V)
(V)
+125
Min.
+25
Typ.
Max.
150
300
600
3000
150
300
600
3000
-
0.04
0.04
0.04
O.OB
5
10
20
100
0.42
0.36
0.51
1.1
2.B
-0.42
-1.3
-1.1
-2.B
0.9
2.4
-0.36
-1.15
-0.9
-2.4
1.3
34
-0.51
-1.6
-1.3
-3.4
1
2.6
6.B
-1
-3.2
-2.6
-6.B
5
10
20
5
10
20
20
100
100
0,5
0,10
0,15
0,5
0,5
0,10
0,15
5
0.64
10
15
5
5
10
15
0,5
5
0,10
0,15
10
15
5
10
15
0.5
0.10
0.15
0.5,4.5
-
1,9
-
1.5,13.5
-
0.5,4.5
1,9
-
-
+85
5
10
15
-
1.5,13.5
-40
0,5
0,10
0,15
0,20
-
-55
-
O.IB
0.61
1.5
1.6
4.2
4
-0.64 -0.61
-2
-1.B
-1.6 -1.5
-4.2
-4
5
10
15
5
10
15
lB
±0.1
±0.1
0.05
0.05
0.05
-
-
3
4
3.5
7
11
-
-
-
-
7
-
-
±10- 5
±0.1
-
current characteristics.
V
1.5
3
4
-
-
Fig.7 - Minimum ourput high (.ou,ce)
-
3.5
11
rnA
-
0
1.5
±1
-
0
0
5
10
15
4.95
9.95
14.95
±1
-
-
-
IJA
-
-
0.05
0.05
0.05
4.95
9.95
14.95
UNITS
10
10
00
V
Fig. 8 - Typical propagation delay time
(deta to an) ... load capacitance.
IJA
Fig. 9 -'Typical transition time w./oad
capacitance.
AMBIENT TEMPERATURE I fA 1-2$·C
_ _ _ _ LOAD CAPACITANCE CCLI-.5pF
_ _ _ CL-i50pF
112CM-30918
CD4724BH
DIMENSIONS AND PAD LAYOUT
Dimensions in parentheses are in millimeters and
are derived from the basic inch dimensions as
indicated. Grid graduations ate in mils (10- 3 inch).
The photographs and dimensions of each COS/MOS
chip represent a chip when it is part of the wafer.
When the wafer is cut into chips, the cleavage
angles are 57° instead of 90 0 with respect to the
face of the chip_ Therefore. the isolated chip is
actually 7 mils (0. 17 mm) larger in both dimensions.
IOI~I=.--+-
,
._-+
,0<>
.. 68
10D
10'
Z
.. 68
2
.. 6
102
a
I
..
1
68
.. 68
10"
10'
ADDRESS CYCLE TIME-III
Fig.
to -
Typical dynamic power dissipation
VI.
address cycle time.
355
CD4724B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25" C, CL = 50pF,
Input t r , tf= 2Ons, RL = 200 KG
CHARACTERISTIC
CONDITIONS
SEE
VDD
Fig.15·
Propagation Delay:
CD
Data to Output.
WRITE DISABLE
to Output,
M
TYP.
MAX.
5
200
400
10
75
150
15
50
100
5
200
400
10
80
160
15
60
120
tpLH·
tPHL
tPLH·
0
tpHL
LIMITS
ALL PACKAGE TYPES
5
175
350
10
80
160
15
65
130
5
225
450
10
100
200
tpHL
15
75
150
Transition Time,
tTHL'
5
100
200
(Any Output)
tTLH
10
50
100
15
40
80
5
100
200
10
50
100
15
40
80
5
200
400
10
100
200
15
65
125
5
75
150
10
40
75
15
25
50
@
Reset to Output,
tpHL
Address to Output.
tpLH'
,@
Minimum Pulse
0
Width,tw
Data
0
Address
@
Reset
5
Minimum Setup
@
Time, ts
Data to WRITE DISABLE
10
G)
Time,tH
INPUTS
UNITS
Vss
Fig. 11- QuielCflnt device current
test circuit.
ns
INPUTQVCOOUTPUTS
V,"
'--
~
~
VIOL
NOTE:
Vss
TEST ANY COMBINATION
OF INPUTS
9ZCS-274.IRI
Fig. 12-lnput voltage rest circuit.
ns
1NPUOS
Vco NOTE
Voo
~
ns
~::~~:;I~~~~~S
Vss
TO BOTH Voo AND Vss
CONNECT ALL. UNUSED
INPUTS TO EITHER
Voo OR VSS·
Vss
ns
Fig. 13- Input current test circuit.
AD
AO
00
AI
A.
14 WQ
01
a. o.
13 DATA
A'
••
AI
ns
A'
A.
DATA IN
100
25
50
15
20
35
5
75
150
10
40
75
15
25
50
5
7.5
Minimum Hold
Data to WRITE DISABLE
50
.
Vss
a.
CD4724B
06
07
ns
..
Any Input
7
00.
. 004
9
10
005
DO 0
" DO
"
7
DO 8
to
"00
ns
00
01
DO 10
a.
a.
a'
0011
0012
13 DATA
pF
DO
I AD
• AI
3 A2
14 WD
Input Capacitance, C, N
Q~
DO
DO.
I
5
* 116 CD4069
CD4724B Q5
00
07
Circled numbers refer to times indicated on master timing diagram .
R
10
"
12
9
0013
0014
0015
0016
15
VDD
Fig. 14- , of '6 decoder/demultiplexer.
y
IN/OUT
1/4 C04016
o
I
2
A.A.~----I.""
•
/
/
.,-----....
Fig. 15- """"" timing di.".",.
356
'G>.-
,
92CS·27677
/
IN/OUT
,
wo
\iii
Fig 16-: Multiple .election decoding . crosspoint switch.
4x 4
CD40100B Types
COS/MOS 32-Stage Static Left/Right Shift
Register
High-Voltage Types (20-Volt Rating)
The RCA-CD40100B is a 32·stage shift register containing 32 D-type master-slave flip·
flops.
The data present at the SHI FT·RIGHT INPUT
is transferred into the first register stage syn·
chronously with the positive CLOCK edge.
provided the LEFT/RIGHT CONTROL is at
a low level. the RECIRCULATE CONTROL
is at a high level, and the CLOCK INHIBIT
is low. If the LEFT/RIGHT CONTROL is at
a high level and the RECIRCULATE CON·
TROL is also high, data at the SHIFT·LEFT
INPUT is transferred into the 32nd register
stage synchronously with the positive CLOCK
transition. provided the CLOCK INHIBIT is
low. The state of the LEFT/RIGHT CONTROL, RECIRCULATE CONTROL, and
CLOCK INHIBIT should not be changed
when the CLOCK is high.
Data is shifted one stage left or one stage
right depending on the state of the LEFT/
RIGHT CONTROL, synchronously with the
positive CLOCK edge. Data clocked into the
first or 32nd register states is available at the
SHIFT-LEFT or SHIFT-RIGHT OUTPUT
respectively, on the next negative CLOCK
transition (see Data Transfer Table). No
shifting occurs on the positive CLOCK edge
if the 'CLOCK INHIBIT line is at a high
level. With the RECIRCULATE CONTROL
low, data in the 32nd stage is shifted into the
LEFT/RIGHT
CONTROL
IN
Features:
• Fully static operation
• Shift leftlShift right capability
• Multiple package cascading
• Recirculate capability
• LI FO or FI FO capability
• Standardized, symmetrical output
characteristics
• 100% tested for quiescent current at 20 V
• Maximum input current of 1 pA at 18 V
over full package·temperature range;
100 nA at 18 V and 25 0 C
• Noise margin (full package-temperature
range) =
1 Vat VOD= 5 V
2 V at VOO = 10 V
2.5 Vat VOO = 15 V
• 5-V, 10-V, and 15-V parametric rating's
• Meets all requirements of JEOEC Tentative
Standard No. 13A, "Standard Specifications
for Oescription of 'B' Series CMOS Devices"
13
SHIFT
"
CLOCK
3
CLOCK
INHIBIT
I.
SHIFT
RIGHT
12
RIGHT
OUT
SHIFT
LEFT
•
SHIFT 2
LEFT
6
OUT
'0100"16
NCo',5.7,
vss·a
IO.I~,15
RECIRCULATE
CONTROL
92C$-27561
FUNCTIONAL DIAGRAM
Applications:
•
•
•
Serial shift registers
Time delay circuits
Expandable N-bit data
(LI FO operation)
storage
stack
first stage when the LEFT/RIGHT CONTROL is low and from the 1 st stage to the
32nd stage when the LEFT/RIGHT CONTROL is high.
The CD40100B types are supplied in 16lead hermetic dual-in-lineceramic packages
(D and Fsuflixes), 16-lead dual-in-line plastic packages (E suffix), 16-lead ceramic Ilat
packages (K suffix), and in chip lorm (H
suffix).
DRAIN-lO-SOURCE VOLTAGE IVosl-V
Fig. 1 -!Typical output/ow (sink)
current,characteristics.
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE,IV DD )
~.5to+2OV
IVoltages referenced to VSS Terminal)
INPUT VOLTAGE RANGE, ALL INPUTS
-{I.5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT . .
±lOmA
POWER DISSIPATION PER PACKAGE IPD):
. . . . . . . ..
500mW
For TA = -40 to +60o C IPACKAGE TYPE E) .
Derate Linearly at 12 mW/oC to 200 mW
For TA a +60 to +850 C (PACKAGE TYPE E) . .
. . . . . . . '..
500mW
For TA· -55 to +1000 C IPACKAGE TYPES D,FI
Derate Linearly at 12 mW/oC to 200 mW
ForTA = +100 to +1250 C IPACKAGE TYPES D, FI
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
l00mW
FOR TA ='FULL PACKAGE-TEMPERATURE RANGE IAII Package Typesl'
OPERATING-TEMPERATURE RANGE ITAI:
":55 to +125 0 C
PACKAGE TYPES D, F, H
. . . _. . .
-40 to +850 C
PACKAGE TYPE E . . . . . . . . .
--ti5 to +1500 C
STORAGE TEMPERATURE RANGE ITstgl
LEAD TEMPERATURE IDURING SOLDERING):
At distance 1/16 ± 1/32 inch 11.59 ±0.79 mml from case for 10 s max.
ORAIN-TO-SOURCE VOLTAGE
Fig. 2 - Minimum output low (sink)
, current characteristics.
357
CD40100B Types
DRAIN-lO-SOURCE VOLTAGE (Vos)-V
-I!l
-10
-5
AMBIENT TEMPERATURE tTA'"Z5"C
CLoc~n
••
CLOCK INHIBIT
Cl
*>
11"
SHIFT LEFT
")0----0-
OUTPUT
LEFT/~'GT
Jill
1"
CONTROL
S
REC'R~U"If
*.
Fig. 5 - Typical output high (source)
current characteristics.
TE
CONTROL
DRAIN-lO-SOURCE VOL.TAGE (VOSI-V
R
-15
-10
-5
AMBIENT TEMPERATURE (TA)-25"C
Yoo
11
*ALLINF'UTS
" PROTECTED
Vss
BY COS/MaS PROTECTION
NETWORK
SHIFT LEFT
••
I"PUT
Fig. 6 - Minimum output high (source)
• DETAIL Of TYPICAL D·TYPE M-S FLIP-FLOP
current characteristics.
CL
Fig. 3 - Logic diagram.
LOAD CAPACITANCE ICLI-pF
Fig. 7 - Typical propagation delay time
(CLOCK to SHIFT LEFT/RIGHT J
as a function of load capacitance.
CLOCK
INPUT
t--' PL,.---j
_ _ _ _11
Ir
OUTPUT
Fig. 4 - Timing diagram defining setup, hold, and propagation delay times.
Fig. 8 - Typical transition time as a function
of load capacitance.
358
CD40100B Types
RECOM!'IIENDED OPERATING CONTITIONS at TA =250 C, Except as Noted.
For maximum reliability, nominal operating conditions should be selected so that operation
is always within the following ranges:
CHARACTERISTIC
LIMITS
VDD
(V)
Min.
Supply·Valtage Range (For T A = Fuli Package·
Temperature Range)
3
18
100
20
10
275
100
75
-
Data Setup Time, ts
5
10
15
Data Hold Time, tH
5
10
15
Clock Input Frequency, fCL
5
10
15
Clock Input Rise or Fall Time, trCL, tfCL
5
10
15
-
5
10
15
450
230
190
5
10
15
280
150
140
Clock Input Pulse Width:
Low Level, tWL
High Level, tWH
UNITS
Max.
V
-Cl·~OpF
-
dc
-
-_aCL."15pF
ns
I
2:
.. 8'102:
.. 68 10Z Z . . . 8 103 2 .. 68 104 2
. . . . 105
CLOCK INPUT FREQUENCY I 'eL.)-KHZ . t2CS-2Ut7
ns
Fig. 9 - Tvpical dynamic power dissipation
as a function of CLOCK frequency.
1
2.5
3
mHz
15
15
15
IlS
INPUTS
-
-
ns
-
ns
o
Vss
Vss
CONTROL TRUTH TABLE
LEFT/RIGHT
CONTROL
CLOCK
INHIBIT
RECIRCULATE
CONTROL
Fig. 10 - Quiescent-device--current test circuit.
INPUT BIT
ORIGIN
ACTION
1
0
1
Shift left
,1
0
0
Shift left
Stage 1
0
0
1
Shift right
Shift right input
0
0
0
Shift right
Stage 32
X
1
X
No shift
Shift left input
-
V~NP(JU'
" =~~
"ss
voo
•
TO BOTH
AND V5S'
CONNECT ALL. UNUSED
INPUTS TO EITHER
YOOORVSS'
Vss
DATA TRANSFER TABLE*
INITIAL STATE
DATA
INPUT
CLOCK
INHIBIT
CLOCK
INTERNAL
STAGE
0
0
X
X
0
0
1
0
X
X
0
X
1
0= Low level
1
= High
level
RESULTING STATE
LEVEL
CHANGE
INTERNAL
STAGE
OUTPUT
~
~
0
NC
a
NC
0
1
NC
1
~
~
NC
1
1
X
NC
NC
X = Don't care
* For Shift-Right Mode
Data Input = SHIFT·RIGHT INPUT (Term,'11
I nternal Stage = Stage' (0,1
Output = SHIFT·LEFT OUTPUT (Term. 4)
NC
Fig. 11 - Input-current lest circuit.
'"PUTOVceOUTPUTS
.........
~
V'H
:c
v~
= No change
For Shift·Left Mode
Data Input = SHIFT·LEFT INPUT (Term. 6)
Internal Stage = Slage 32 (032)
Output = SHI FT·RIGHT OUTPUT (Term. '2)
"55
NOTE:
TEST ANY COMBINATION
OF INPUTS
92CS-Z7441RI
Fig. 12 - Input· voltage test circuit.
359
CD40100B Types
STATIC ELECTRICAL CHARACTERISTICS
CHARACTER·
ISTIC
Quiescent Device
Current,
100 Max.
Output Low
(Sink) Current
IOLMin.
Output High
(Source)
Current,
IOH Min.
Output Voltage:
Low·Level.
VOL Max.
Output Voltage:
High·Level,
VOH Min.
Input Low
Voltage,
VIL Max.
Input High
Voltage,
VIH Min.
Input Current
liN Max.
LIMITS AT INDICATED TEMPERATURES (OC)
V"ues at -56, +25, +125 Apply to D,F ,H Packages
V.lue. at -40, +25; +85 Apply to E Package
CONDITIONS
Vo
(V)
0.4
0.5
1.5
4.6
2.5
9.5
13.5
-
0.5,4.5
1,9·
1.5,13.5
0.5,4.5
1,9
1.5,13.5
-
+25
VIN VDD
(V)
(V) -56
-40
+85
+125
Min.
Typ.
Max.
0,5
0,10
0,15
0,20
5
10
15
20
5
10
20
100
5
10
20
100
150
300
600
3000
150
300
500
3000
-
0.04
0.04
0.04
0.08
5
10
20
100
0.5
0,10
0,15
0,5
0,5
0,10
0.15
0,5
5
10
15
5
5
10
15
5
0.64
1.6
4.2
-0.64
-2
-1.6
-4.2
-
0,10
0,15
0,5
0,10
0,15
10
15
5
10
15
0.05
0.05
0.05
4.95
9.95
14.95
1
2.6
6.8
-1
-3.2
-2.6
-6.8
0
-
5
10
15
5
10
15
1.5
3
4
3.5
7
11
0,18
18
:to. 1
-
-
0.42
0.36 0.51
0.61
1.1
0.9
1.3
1.5
2.4
3.4
4
2.8
-0.61 -0.42 -0.36 -0.51
-1.8 -1.3 -1.15 -1.6
-0.9 -1.3
-1.5 -1.1
-4
-2.8
-2.4 -3.4
±0.1
-
4.95
9.95
14.95
-
±1
0.05
0.05
0.05
-
-
-
1.5
3
4
3.5
7
11
-
-
-
-
-
±10-:-5
rnA
-
0
0
5
10
15
-
p.A
-
-
-
±1
-
-
UNITS .
V
V
±D. 1
p.A
The photographs and dimensions of each
COS/MOS chip represent a chip when it
..,-"
12.210-2.4031
is part af the wafer. When the waflJr is
cut inco chips, the cleavage angles are
57° instead of 90° with respect to the
face of the chip. Therefore, the isolated
chip is actually 7 mils (0. 17 mm) larger
in both dimensions.
t---------r·~:~~ZIl---------I
NC.-......
Dimensions and pad layout for CD40100BH.
360
Dimensions in parentheses are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations arB in mils (70- 3 inch).
CD40100B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, Input t r, tf = 20 ns,
Cl =50pF,Rl = 200 kn
TEST CONDITIONS
CHARACTERISTIC
VDD
V
LIMITS
UNITS
Min. Typ. Max.
Propagation Delay Time:
Clock to Shift left/Right
Output,
tpLH' tpHL
5
10
15
360 720
165 330
115 230
ns
TransitionTime,
5
10
15
100
50
40
200
100
80
ns
Minimum Data Setup Time. ts
5
10
15
50
10
5
100
20
10
ns
Minimum Data Hold Time, tH
5
10
15
170
75
50
275
100
75
ns
tTHL' tTlH
5
Maximum Clock Input Frequency, tCl
10
15
Minimum Clock Input Pulse Width:
Low level, tWL
High level, tWH
Any Input
Input Capacitance, CI N
NC
CLOCK INHIBIT
I·
2
I.
15
CLOCK
SHIfT LEFT
our
NC
MHz
225 450
115 230
95 190
ns
5
10
15
140 280
75 150
70 140
ns
-
5
7.5
pF
VDD
NC
NC
LEFT/RIGHT CONTROL
12
SHIFT RIGHT
our
SHIFT RIGHT IN
SHIFT LEFT IN
NC
2
5
6
5
10
15
"
"
1
2.5
3
10
NC
RECIRCULATE CONTROL.
Vss
TOP VIEW
NC"NO CONNECTION
92:CS-21568
TERMINAL ASSIGNMENT
__________________________________________________________________ 361
CD40101 B Types
COS/MOS 9-Bit Parity
GeneratorIChecker
High-Voltage Types (20-Volt Rating)
The RCA-CD40101B is a. 9-bit (8 data bits
plus 1 parity bit) parity generator/checker.
It may be used to detect errors in data transmission or data retrieval. Odd and even
outputs facilitate odd or even parity generation and checking.
When used as a parity generator, a parity
bit is supplied along with the data to generate.
an even or odd parity output.
When used as a parity checker, the received
data bits and parity bits are compared for
correct parity. The even or odd outputs are
used to indicate an error in the received
data.
Word-length capability is expandable by
cascading. The CD401 01 B is also provided
with an inhibit control. If the inhibit control
is set at logical "1", the even and odd out·
puts go to a logical "0".
The C040101 B types are supplied in 14lead dual-in-line ceramic packages (0 and F
suffixes), 14-lead dual-in-Iine plastic packages (E suffix), 14-lead ceramic flat packages (K suffix). and in chip form (H suffix).
TERMINAL ASSIGNMENT
01
D.
O.
03
o.
000 OUT
Vss
,-
•
14
Veo
13
12
08
07
II
10
06
05
9
EVEN OUT_
e
INH
Features:
100% tested for maximum quiescent
current at 20 V
• Maximum input current of 1 /.LA at
18 V over full package-temperature
range; 100 nA at 18 V and 25 0 C
• Noise margin (f.ull package-temperature
range):
1 Vat VOD = 5 V
.
2VatVDD=10V
2.5 V at VDD = 15. V
• 5·V. 10-V. and 15-V parametric ratings
• Standardized, symmetrical output
characteristics
• Meets all requirements of JEDEC
Tentative Standard No.13A, "Standard
Specifications fBr Description of '8'
Series CMOS Devices."
•
FUNCTIONAL DIAGRAM
MAXIMUM RATINGS,Absolute-Maximum Values:
DC SUPPLY·VOLTAGE RANGE, (V Db)
(Voltages referenced to VSS Terminal)
-0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS
-0.5 to VDD +0.5 V
DC INPUT CURRENT. ANY ONE INPUT
±to mA
POWER DISSIPATION PEA PACKAGE (PO):
For TA = -40 to +60o C (PACKAGE TYPE E) .
. . • • . . • ..
SOOmW
For TA = +60 to +8SoC (P,--__--,_____+----,-__---lr--11-_---,
I
DRA'N-TQ-SOURCE VOLTAGE
Fig_ 4 -
lVosI-V
Typical output low (sink) current
characteristics.
~D
POSI
*ALL INPUTS PROTECTED BY
POS2
__ _
COS/MOS PROTECTION
NETWORK
DRAIN-TO-SOURCE VOL.TAGE 1\Io51-V
Vss
Fig. 5 - Minimum output low (sink)
Fig_ 1 - Logie diagram for the CD40 1058_
current characteristics.
380 ____________________________________________________________________
CD401058 Types,
STATIC ELECTRICAL CHARACTERISTICS
DRAIN- TO- SOURCE VOLTAGE IYOSI-V
U
N
I
T
S
LIMITS AT INDICATED TEMPERATURES (OC)
CHARACTERISTIC
CONDITIONS
Vo
(V)
Output Low
(Sinkl Current
IOL Min.
Output High
(Sourcel
Current,
IOH Min.
Output Voltage:
Low-Level,
VOL Max.
Output
Voltage:
High-Level,
VOH Min.
Input Low
Voltage
VIL Max.
+85
-40
+125
0,20
20
100
100
3000
3000
0.4
0,5
5
0.64
0.61
0.42
0.36
0.51
0.5
0,10
10
1.6
1.5
1.1
0.9
1.5
0,15
15
4.2
4
2.8
2.4
4.6
0,5
5
5
5
5
150
150
0,10
10
10
10
300
300
-
0,15
15
20
20
600
600
-
-0.64 -0.61
Max_
Typ_
Min_
-
0,5
-
0.04
5
0.04
10
0.04
20
0.08
100
1
-
1.3 .
2.6
3.4
6.8
-0.42 -0.36 -0.51
-1
-
2.5
0,5
5
-2
-1.8
-1.3 -1.15
-1.6
-3.2
-
9.5
0,10
10
-1.6
-1.5
-1.1
-0.9
-1.3
-2.6
-
-4.2
-4
-2.8
-·2.4
-3.4
-6.8
-
13.5
0,15
15
-
0,5
5
0.05
-
0,10
10
0_05
-
0,15
15
0.05
0
-
current characteristics.
DRAIN-lO-SOURCE VOLTAGE tVosl-V
mJl
0
0.05
-
5
4.95
4.95
5
10
9.95
9.95
10
-
-
0,15
15
14.95
14.95
15
-
0.5,4.5
-
5
1.5
-
10
3
15
4
-
5
3.5
3.5
-
1.5
1,9
-
7
7
-
-
11
11
-
-
0,18
18
±0.1
±0.1
±1
±1
3-State
Output
Leakage
Current
lOUT Max.
0,18
0,18
18 ±O.4
±0.4
±12
±12
-IS
Fig. 7 - Minimum output high (source)
current characteristics.
V
-
15
--
--15V
V
3
4
10
I nput Current
liN Max.
-,
-IOV
0.05
0,5
1,9
-10
0 0.05
0,10
1.5,13.5
-I~
AMBIENT TEMPERATURE (TAI-2'·C
-,
-
0.5,4.5
Il A
Fig. 6 - Typical output high (source)
-
1.5,13.5
Input High
Voltage,
VIHMin.
+25
VIN VDD
(V)
(V) -55
-
Quiescent
Device
Current,
IDD Max.
Values at -55, +25, +125 Apply to D,F,H Packages
Values at -40, +25, +85 Apply to E Package
±10- 5 ±0.1 IlA
-
-
±10-4 ±0.4 Il A
92tS-24322
.
Fig. 8 - Tvpical transition time as a function
of load capacitance.
10. AMBIENT TEMPERATUREITAI-25-C
I
z
~Io'a
~.
~o
:5~
IV
INPUTS , - - ' - - - ,
I<,~ ~~
A,..".~"'/
.,4.
2
!CA-IO·
~B
~
'"4""
~9 4
~s
1111 V
°
Vss
~Ov
:
-:Ii
/
4
2
~-Ia:
4
2
10'
I
.
1/
CL·SOpF
CL" 15 pF ____
/
4.8
1111 I 488
11
10 2 4 18102 2 4 88. 32 488 10.2
INPUT FREQUENCY Itl~- kHz
10
92c9-29904
Fig.
9 - Typical dynamic power diss;:
pation as a function of frequency.
Vss
92CS-21401RI
PULSE GEN. I ·'IN
PULSE
GEN.2.~
92e9-U903
Fig. 10 - Dynamic power dissipation
test circuit.
Fig. 11 - Ouiescent-device-current
test circuit.
381
CD401058 Types
DYNAMIC ELECTRICAL CHARACTERISilCS at T A = 25°C;
Input tr.tf = 20 ns. CL = 50 pF. RL = 200 kn
VDD(V)
Propagation Delay Time:
Shift·Out or Reset to Data·Out
Ready,
tpHL
5
10
15
Shift·ln to Data·ln Ready, tpHL
5
10
15
3-State Control to Data Out
tpZH' tpZL
5
10
15
tpHZ, tpLZ
5
10
15
5
10
15
Ripple-Through Delay Input to Output,
tpLH
-
-
-
Maximum Shift-In or Shift-Out Rate,
fl
5
10
15
1.5
3
4
Minimum Shift-In Pulse Width,
tWH
5
10
15
-
tTHL' tTLH
5
10
15
Minimum Shift-Out Pulse Width,
tWL
Maximum Shift-In or Shift-Out Rise
Time,
tr
5
10
15
Maximum Shift-In Fall Time,
tf
5
10
15
Maximum Shift-Out Fall Time,
tf
5
10
15
Minimum Data Setup Time,
tsu
5
10
15
Minimum Data Hold Time,
tH
5
10
15
tWL
5
10
15
Data-Out Ready Pulse Width, tWL
5
10
15
Minimum Master Reset Pulse Width,
tWH
5
10
15
Data-In Ready Pulse Width,
Input Capacitance
382
CIN
(Any Input)
-
'"
UNITS
V,H
'--
Min. Typ Max.
5
10
15
Transition Time,
IMPUTD
V
LIMITS
TEST CONDITIONS
CHARACTERISTIC
-
-
-
185 370
90 180
65 130
v~
140 280
60 120
40
80
ns
100 200
50 100
40
80
ns
2
1
0.7
Ils
3
6
8
Yoo
-
-
-
CONNECT ALL UNUSED
MHz
15
15
15
IlS
15
15
15
IlS
15
5
5
ILs
0
0
0
ns
150
120
~o~~~~
,e
16
Voo
OIR
2
15
SO
5I:3
14
OOR
0041300
01
~
12
01
02611Q2
03710Q3
V55
LB_ _
MR
--I.
TERMINAL ASSIGNMENT
ns
220 440
90 180
65 130
ns
100 200
45
90
30
60
ns
7.5
Fig. 13 - Input current test circuit.
ns
260 520
100 200
70 140
5
TO BOTH 'iDa AND'lss·
N'VTS 10 EITHER
VooORVSS'
175 350
75
60
SEOUENTIAl.LY.
Vss
V$S
ns
-
·MUSURE INPUTS
• ~
ns
180 360
80 160
50 100
-
I"PUO
v", S NOTE'
'---'i\--
ns
-
92CS-2l'4411t.
Fig. 12 - Input-voltage test circuit.
100 200
40
80
30
60
-
OF '"PUTS
.-
-
~
VSS
NOTE:
TEST ANY COMBINATICIN
ns
100 200
50 100
80
40
~
ns
160 320
65 130
45
90
4
2
1.4
OUTPUTS
.
pF
CD401058 Types
~
________________________nL----~--L..-T"""--
CUNKNOWN)
*ATVOO-5V-RIPPLE TIME FROM POSITION I TO POSITION 16 I
0
I
·AT Voo-5V-RIPPLE TIME FROM POSITION 16 TO POSITION I
I
92CS- 29233 RI
#DATA VALID goes,';hiUh level in Idnnce of the DATA OUT
bye maximum 0150 nsat Veo· 5 V. 25n.atVOD· 10V,
and 20 ns at Veo '" 15 V for CL • 50 pF and T A • 26OC.
Fig. 14 - Timing diagram for the CD40105B.
DATA OUT
READY
8 BIT
DATA
• 01'
DATA
DATA IN
READY
#pulse must be applied for cascaling by 16 N bits.
Fig. 75 - Expansion, B·bits·wide·by·16 N·birr/ong using CD40105.
The photographs and dimensions of each COS/MOS
chip represent a chip when it is part of the wafer.
When the wafer is cut into chips, the cleavage
angles are 57° instead of 90° with respect to the
face of the chip. Therefore. the isolated chip is
actuallv 7 mils (0. 17 mm) larger in both dimensions.
Dimensions. in parentheses are in millimeters and
are derived from the bas';c inch dimensions as indicated. Grid graduations are in mils 00-3 inch).
Dimension and pad layout for CD40105B.
383
CD40106B Types
Features:
COS/MOS Hex
Schmitt Triggers
High-Voltage Types (20-Volt Rating)
The RCA-CD40106B consists of six Schmitttrigger circuits. Each circuit functions as an
inverter with Schmitt-trigger action on the
input. The trigger switches at different points
for positive- and negative-going signals. The
difference between the positive-going voltage
IVP) and the negative-going voltage IVNI is
defined as hysteresis voltage (YH) Isee Fig.6).
The CD40106B types are supplied in 14lead hermeticdual-in-line ceramic packages
(0 and F suffixes), 14-lead dual-in-line plastic package (E suffix), 14-lead ceramic flat
package: (K suffix), and in chip form (H
suffix).
• Schmitt-trigger action with no external components
• Hysteresis voltage (tyP.) 0.9 V at VDD = 5 V, 2.3 V at
VDD = 10 V, and 3.5 V at VDD = 15 V
• Noise immunity greater than 50%
• No limit on input rise and fall times
• Standardized, symmetrical output characteristics
• 100% tested for quiescent current at 20 V
• Maximum input current of 1 /lA at 18 V over full
package-temperature range; 100 nA at 18 V and 25 0 C
'~.'i
.~H'i
C~.I..~
D~J.D
.~ ••!
F~L-1
• Low VDD to VSS current during slow
input ramp
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative
Standard No.13A, "Standard Specifications
for Description of 'B' Series CMOS Devices'~
VOO-M
VSS-7
FUNCTIONAL DIAGRAM
Applications:
•
•
•
•
Wave and pulse shapers
High-noise-environment systems
Monostable multivibrators
Astable multivibrators
•~
2(4. •
".10,12)
1(3",9,1,1')
Yo.
. . ALL
INPUTS
PROTECT
D
COS/MOS
PROTECTION
- E
--' s a
NETWORK.
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (VDDI
(Voltages referenced to VSS Terminall
-0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS
-0.5 to VDD +0.5 V
±10mA
DC INPUT CURRENT, ANY ONE INPUT
POWER DISSIPATION PER PACKAGE (Pol:
o
For TA: -40 to +60 C (PACKAGE TYPE El
. . . . . . . ..
500mW
For T A: +60 to +85 0 C (PACKAGE TYPE El
.
Derate Linearly at 12 mW/oC to 200 mW
. . . . • . . ..
500 mW
For TA: -55 to +1000 C IPACKAGE TYPES D,F,I
For TA: +100 to +125 0 C (PACKAGE TYPES D, F,l
Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA: FULL PACKAGE·TEMPERATURE RANGE (All Package Typesl
100mW
OPERATING·TEMPERATURE RANGE (TAl:
PACKAGE TYPES D, F, H
-55 to +1250 C
PACKAGE TYPE E .
-40 to +85 0 C
STORA.GE TEMPERATURE RANGE (Tstgl
-65 to +1500 C
LEAD TEMPERATURE IDURING SOLDERINGI:
At distance 1 /16 ~ 1/32 inch (1.59 ± 0.79 mm) from case for 105 max.
-~ "
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected
so that operation is always within the following ranges:
~
MIN.
MAX.
3
1S
Supply-Voltage Range I For T A .
Full Package·Temperature Rangel
10V
10
5 ,
LIMITS
CHARACTERISTIC
...
Fig. 1 - Logic diagram
(1 of 6 Schmitt trigge,.l.
UNITS
5
10
ORAI~-TO-SOURCE
15
VOLTAGE (VOSI-V
Fig.2 - Tvpical output low (sink)
current characteristics.
V
DYNAMIC ELECTRICAL CHARACTERISTICS
At TA = 2!PC,lnput t r , tf= 20n5, CL = 50pF, RL = 200kfl.
TEST CONDITIONS
CHARACTERISTIC
LIMITS
UNITS
VDD
(V)
TYP.
MAX.
tPHL,
tPLH
5
10
15
140
70
60
2S0
140
120
ns
tTHL
tTLH
5
10
15
100
50
40
200
100
SO
ns
5
7.5
pF
Propagation Delay Time:
Transition Time:
Input Capacitance, GIN
Any Input
5
10
15
ORAIN-TO-SOURCE VOLTAGE IVosl-v
Fig.3 - Minimum output low (sink)
current characteristics.
384 __________________________________________________________________
CD40106BTypes
DRAIN-lO-SOURCE VOLTAGE IVosl-V
-15
-10
-5
STATIC ElECTRICAL CHARACTERISTICS
AMBIENT TEMPERATURE (TA,025"C
H+I+fjW_~U..j.'U
LIMITS AT INDICATED TEMPERATURES IOC)
Values at -55,+25,+125 Apply to 0, F,H Packages
Values at -40,+25,+85 Apply to E Packages
CONDITIONS
CHARACTERISTIC
Quiescent Device
'Current, IDO
Max.
Positive Trigger
Threshold Voltage
Vp Min.
Vp Max.
Negative Trigger
Threshold Voltage
VN Min.
VN Max.
0.02
1
60
120
600
-
0.02
0.02
0.04
2
4
20
2.2
4.6
6.8
2.2
4.6
6.8
2.2
4.6
6.8
2.9
5.9
8.8
-
3.6
7.1
10.8
3.6
7.1
10.8
3.6
7.1
10.8
-
-
2.9
5.9
8.8
3.6
7.1
10.8
0.9
2.5
4
0.9
2.5
4
0.9
2.5'
4
0.9
2.5
4
0.9
2.5
4
1.9
3.9
5.8
-
5
10
15
2.8
5.2
7.4
2.8
5.2
7.4
2.8
5.2
7.4
2.8
5.2
7.4
-
-
1.9
3.9
5.8
2.8
5.2
7.4
5
10
15
0.3
1.2
1.6
0.3
1.2
1.6
0.3
1.2
1.6
0.3
1.2
1.6
0.3
1.2
1.6
0.9
2.3
3.5
-
5
10
15
1.6
3.4
5
1.6
3.4
5
1.6
3.4
5
1.6
3.4
5
-
-
0.9
2.3
3.5
1.6
3.4
5
0.64
1.6
4.2
0.61
1.5
4
0.42
1.1
2.8
0.36
0.9
2.4
0.51
1.3
3.4
1
2.6
6.8
-
VDD
IV)
-55
-40
+85
+125
Min.
-
0,5
0,10
0,15
0,20
5
1
1
30
30
10
15
20
2
4
20
2
4
20
60
120
600
5
10
15
2.2
4.6
6.8
2.2
4.6
6.8
5
10
15
3.6
7.1
10.8
5
10
15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VH Max.
Max.
VIN
IV)
Hysteresis Voltage
VH Min.
+25
Typ.
Vo
IV)
-
-
-
-
Output low (Sink)
Current,
IOl Min.
0.4 0,5
0.5 0,10
1.5 0,15
5
10
15
Output High
(Source)
4.6
2.5
9.5
13.5
0,5
0.5
0,10
0,15
5
5
10
15
Output Voltage
low-level,
VOL Max.
-
5
10
15
5
10
15
0.05
0.05
0.05
-
Output Voltage
High level,
VOH Min.
-
-
0
0
0
5
10
15
4.95
9.95
14.95
-
0,18
18
Current,
IOH Min.
Input Current,
liN Max.
-
-0.64 -0.61 -0.42 -0.36 -0.51 -1
-2 -1.8
-1.3 -1.15 -1.6 -3.2
-1.6 -1.5
-1.1
-0.9
-1.3 -2.6
-4.2
-4
-2.8 -2.4
-3.4 -6.8
±D. 1
V~.Vt"
1"._
__
v~~
v
-----_ _:
-
__.
L-r
£H
I
v:o~1
I
to.l
tl
1
§
S
UNITS
.•
tll
I
.t::~:
:
t..
/lA
~
-25~
t-
-30~
Hll
Fig.4 - Typical output high (source)
curren t characteristics.
DRAIN-lO-SOURCE VOLTAGE (VOSI-V
·\5
-10
·5
o·
V
-
-
---
V
Fig.5 - Minimum output high (source)
current characteristics.
rnA
-
4.95
9.95
14.95
5
10
15
-
-
10
V
0.05
0.05
0.05
tl
-5
-15
0
0
0
-
GATE-lO-SOURCE VOLTAGE (VGSJo-5V
tl0- 5 to.l
OUTPUT
CHARACTERISTIC
INPUT
CHARACTERISTIC
V
/lA
Fig.7 - Input and output characteristics.
J1J, .'., ,,"~,
~Vt"
vN
lip
Vo
V•• - - -
a) Definition of Vp, VN, VH
bJ Transfer characteristics of 1 of 6 gates
Fig.6 - Hysteresis definition, characteristics. and
tes~
set-up.
Fig.B - Typical current and voltage
transfer characteristics.
385
CD401068 Types
200 AM'''NT TEMPERATURE "A""'O: :: i~i:
b:ii ,~ ii' ~,ili~~"'H ~'~
.... :::' :::: "" I::: ':::
~
, II'
w
5
'~,"'r
~'
• 10
lJll
I'
''''PuT VO~TAGE WI I-v
Fig.9 - Typical voltage transfer characteristics
as a function of temperature.
I
20
IOV
!I
II
040
60
LOAD CAPACITANCE ICLI-pF
'::'
..
80
100
Fig, 10 - Tvpical propagation delay time as B
function of load capacitance.
AM81Efr1T TEMPERATuRE {TAI-2'S·C
INPUT ON TERMINALS 1,~,8.12 OR 2, 6,9,ll;
,
INPUJ~+_~'ED>_:O !,'~O.:~,
111111 :1:1
OTH,ER
~
ililt
€"
~
r
l.OAD CAPACITANCE (CL}-pF
Fig. It - Typical transition time as a function
of load capacitance.
..
I:: It! ..
g m; :
r"!!..- ... :: .::.:: ::::
H ~:n
10H-tt!:,Hiffi18ffi~1:*S!±H/:::i;~':.J:;<;~~I1+1HI='tlf1
c
~
.~g ,
j:
ti;;
~~
H
=:; ::::~ ~§
..
+1
,
10
~EJ It!: £~::?: ~;.:.! ~$
.
15
10
15
SUPPLY VOLTAGE IVDI)I-V
SUPPLY VOLTAGE (VODI-V
Fig. 13 - Typical trigger threshold voltage as a
function of supplV voltage,
Fig. 12 - Typical power dissipation per trigger
as a function of input frequency_
Fig. 14 - Typical per ceClt hysteresis as a function
of supply voltage.
APPLICATIONS
R
1/3C04007UB
'00
Vss
7SL--
-
-
~
Iii> C0401068
n..n:::
Yoo
VDDn
Vss
vSS
J:-t
•n
I'MI
rI-voo
CTI/6CD40106B
~
10 5
",
(
VVSS
'M~RCln VDD~~P)
'OOpF,"C~I,.F
fREQUENCY RANGE OF WAVE SHAPE
IS FROM DC TO I MHz
FOR THE RANGE Of R ANO C
GIVEN 5J.1' < 'M< Is
RISEANOFALLT'IoI[ 11,:,,1-"1
Fig. 15.- Typical power dissipation as a function
of rise and fall times.
L
!SOkn,"R~IMn
VSS
104
-1
2
Fig. 16 - Wave shapero
Fig. 17 - Monostable multivibrator.
Voo
INPUTS
r:r
116 C040r06B
C
T
Vss
t-'A--j
V
00
n r
Vs..-J
fA =RC In
o
V~ ~NP(Jus. ~~:~URE
Vss
L...J
Voo·
[tv~)(~:=~=)]
o ~
Vss
50kfi:SR:sIMQ
.
IOOpF5 C 51pF
FOR THE RANGE OF RAND C GIVEN
2,..$ < fA <045
Fig.f8 - Astable multivibrator.
Vss
Fig. 19 - Quiescent device current test circuit.
,NPUTS
SEQUENTIALLY,
TO 90TH VOO AND VSS'
CONNECT ALL UNUSED
INPUTS TO EITHER
VOO OR VSS'
VSS
Fig.20 - Input current test circuit.
386 _______________________________________________________________________
CD401068 Types
I.
A
G-A
"
""
8
Hoii
c
10
Voo
F
L-i=
I';
of
J
00
I'~
v,s
(TOP VIEWI
92CS·2942:6
Fig.21 - Dynamic power dissipation test circuit.
TERMINAL ASSIGNMENT
Dimensions in parentheses are ;n millimeters and
are derived from the basic inch dimensions as in·
dicated. Grid graduations are in mils 00- 3 inch).
The photographs and dimenslom of each COS/MOS
chip represent a chip when it is part of the wafer.
When the wi~fer is cut int00 chips, the cleavage
angles are, 57 inS read of 90 with respect to the
face of the chip. Therefore. rhe isolated chip is
acruallv 7 mils (0. 17 mm) larger in borh dimensions.
l - - -_ _~~-5.
1.498)
.1
Dimensions and Pad Layout for C040 I06BH
387
CD40107B Types
COS/MOS Dual 2-lnput
NAND Buffer/Driver
High-Voltage Type (20-Volt Rating)
The RCA-CD40107B is a dual 2-input NAND
buffer/driver containing two independent 2input NAND buffers with open-drain single
n-channel transistor outputs. This device
features a wired-OR capability and high
output sink current capability (136 rnA typ.
at VDD = 10 V, VDS = 1 V). The CD40107B
is supplied in the 8-lead dual-in-line plastic
(Mini-DIP) pack~ge (E suffix!. 14-lead hermetic frit-seal ceramic package (F suffix),
and in chip form (H suffix).
Features:
• 32 times standard B-Series output current
drive sinking capability - 136 rnA typo
@ VDD = 10 V, VDS = 1 V
• 100% tested for quiescent current at 20 V
• Maximum input current of 1 p.A at 18 V
over full package-temperature range;
100 nA at 18 V and 250 C
• 5-V, 10-V, and 15-V parametric ratings
• Noise margin, full package temperature
range, RL to VDD = 10 kn:
1 VatVDD = 5 V
2VatVDD=10V
2.5 V at VDD = 15 V
• Meets all requirements of JEDEC Tentative
Standard No.13A, "Standard Specifications
for Description of '8' Series CMOS Devices"
92CS-29434RI
FUNCTIONAL DIAGRAM
Applications
• Driving relays, lamps, LEOs
• Line driver
• Level shifter (up or down)
TRUTH TABLE
A B
C
0
1
0
1
0
0
1
1
l'
l'
l'
z#
z#
z#
0
*Requires external
pull-up resistor
'*
NOTE:NUM8ERS IN
I~~".N.'.
'~:.'.".A,' ~~.',
ill'1l'ilillillli Jl.
(RL) to VOO.
ALL INPUTS PROTECTED
BY COS/MOS
PROTECTION NETWORK
#Without pull-up
resistor (J.·state).
SQUARES FOR CD40107BF,
OTHERS FOR C040107BE.
Vss
92CS-29433fU
Fig. 1 - Schematic diagram of CD401 078 (one of 2 gates!
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE. (V OO )
(Voltages referenced to VSS Terminal)
. -0.5 to +20 V
INPUT VOLTAGE RANGE. ALL INPUTS
-0.5 to VOO +0.5 V
DC INPUT CURRENT, ANY ONE INPUT
±10mA
POWER DISSIPATION PER PACKAGE (PO):
For T A = -40 to +60:C (PACKAGE TYPE E)
500mW
. . . . . . . ..
For T A = +60 to +85 C (PACKAGE TYPE EI
Derate Linearly at 12 mW/oC to 200 mW
For T A = -55 to +1 OOoC (PACKAGE TYPE FI
. . . . . . . ..
500mW
For T A =+100 to +1250 C (PACKAGE TYPE F)
Derate Linearly at 12
to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types)
100mW
OPERATING-TEMPERATURE RANGE (T A):
.
PACKAGE TYPES F. H
-55 to +125 0 C
PACKAGE TYPE E
-40 to +850 C
STORAGE·TEMPERATURE RANGE (Tstg ) . •
-65 to +150oC
LEAO TEMPERATURE (OURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max.
,
DRAIN-TO-SOURCE VOLTAGE (Vos)-V
9ZCS-Z944"RI
Fig.2 - Typical output low (sink!
current characteristics.
mwtC
I~~~:·.~' ',~cC~~'lill !I·~?-I: I
.llil S
1
t
;" c::
;:::::;:
:::1
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected
so that operation is always within the following ranges:
CHARACTERISTIC
Supply-Voltage Range (For T A =
Full Package-Temperatu·rq Range)
LIMITS.
MIN.
MAX.
3
18
UNITS
V
I
ORAIN-TO-SOURCE VOLTAGE (VDS)-V
Fig.3 - Minimum output low (sink)
current characteristics.
388 ________________________________________________________________________
CD40107B Types
DYNAMIC ELECTRICAL CHARACTERI~:nCS atTA = 25 o C, CL = 50 pF ,Inpu_~tr,tt = 20 ns
TEST CONDITIONS
CHARACTERISTIC
VDD
Volts
Propagation Delay:
High·to·Low, tpHL
RL*=120n
RL*=120n
Low-to-High, tpLH
Transition Time:
RL*=120n
High-to-Low, tTHL
RL*=120n
Low-to-High, tTLH
LIMITS
UNITS
Typ.
Max.
5
10
15
100
45
ns
30
200
90
60
5
10
15
100
60
50
200
120
100
ns
5
10
50
20
100
40
15
10
20
5
50
10
35
25
100
70
15
l.OAD CAPACITANCE ICLI-pF
ns
50
Average Input Capacitance, CI N
Any Input
5
7.5
pF
Average Output Capacitance, COUT
Any Output
30
-
pF
*
Fig.4 - Typical transition time as a function of
load capacitance.
ns
RL is external pull-up resistor to VDD.
LOAD CAPACITANCE (CLI- pF
,2CS-29436F11
Fig.5 - Typical propagation delay time as a
STATIC ELECTRICAL CHARACTERISTICS
function of load capacitance.
LIMITS AT INDICATED TEMPERATURES (DC)
Values at -55, +25, +125 Apply to F,H Packages
Values at -40, +25, +85 Apply to E Package
UNITS
+25
VIN VDD
(V)
(V) -55 -40 +85 +125 Min. Typ. Max_
CONDITIONS
CHARACTERISTIC
Quiescent Device
Current
100 Max.
Output Low
(Sink) Current
IOL Min.
Vo
(V)
-
0,5
0,10
0,15
0,20
5
10
15
20
1
2
4
20
1
2
4
20
30
60
120
600
30
60
120
600
-
0.02
0.02
0.02
0.04
1
2
4
20
0.4
1
0.5
1
0.5
0,5
0.5
0,10
0,10
0,15
5
5
10
10
15
21
44
49
89
66
20
42
46
85
63
14
30
32
60
44
12
25
28
51
38
16
34
37
68
50
32
68
74
136
100
-
Output High
(Source)
Current
IOHMin.
: AMBIENT TEMPERATURE (TAl- lS-C
Il A
-
CL;50 pF
CL-15 pF1002
mA
46810, 2.
468102 2:
INPUT FREQUENCY
468103 2
If I I -
-
4 6~04 2
4 6~cfi
kHz
92CS-29438RI
Fig.6 - Typical power dissipation as a
function of input frequency.
No Internal Pull-Up Device
5
10
15
1.5
3
4
-
0.5,4.5
1,9
1.5,13.5
-
5
10
15
3.5
7
11
3.5
7
11
-
Input Current
liN Max.
-
0,18
18
±0.1
±0.1
±1
±1
-
Output Leakage
Current
10Z Max.
18
0,18
18
2
2
20
20
-
Input Low
Voltage
VIL Max."
4.5
9
13.5
Input High
Voltage
VIH Min."
" Measured with external pull·up resistor, RL = 10 kn to VDD.
-
1.5
3
4
Voo
-
V
±10-5
to.l
Il A
10.4
2
Il A
-
92C$-29435
Fig. 7 - Power-dissipation test circuit
for CD40101BE.
389
CD40107B Types
INPUTS
o
Vss
Fig.S - QuiescenN:levice
'current test circuit.
Veo
1NPOUS
Vco
NOTE'
~
MEASURE INPUTS
o ~
SEOUENTIALLV,
Vss
TO BOTH VDO ANO VSS'
CONNECT ALL UNUSED
.aes -11410111
NOTI: NUMiJ[ftl IN PADS fOR CD4010'11, HUMI[ftl
INPUTS TO EITHER
OUTIIOI CHIP fOR C04010Ylf,
Voo OR VSS'
Vss
Dimensions and Pad Layout for CD40107BH.
Dimensions in parentheses are in millimeters and
are derived (rom the basic inch dimensions as indicated. Grid graduations are in mils (10- 3 inch).
Fig. 9 - Input-current test
circuit.
The photographs and dimensions of each COS/MOS
chip represent a chip when it is part of the wafer.
When the wafer is cut into chips. the cleavage angles
are 570 . instead of 900 with respect to the face of
the chip. Therefore. the isolated chip ;s actually
1 'mils (0.17 mm} larger in both dimensions.
;:-..-
DD
Voo
v
NC
13
NC
2
7
0
A
12
NC
c-A-1i
3
6
E
D
4
5
_
Vss
I.
NC
B
Vss
D:o •n
+
V1L
OAO.
1;
V
INPUT00
VDO
OUTPUTS
V,H
10
•
F-O·E
TOP VIEW
TOP VIEW
CD4D1D7BF
CD4D107BE
TERMINAL ASSIGNMENTS
E
NOTE:
TEST ANY COMBINATION
OF INPUTS
92CS-2MII
Fig. to - Input·voltage
test circuit.
F-"if.E
NC
Special Considerations for C040107B
1. Limiting Capacitive Currents for CL >
500pF, VOO> 15 V.
For VOO> 15 V, and load capacitance
(eu from output to ground> 500 pF,
an external 25 n series limiting resistor
should be inserted between the output
terminal and CL. No external resistor is
necessary if CL < 500 pF or VOO <
15V.
2. Oriving Inductive Loads
When using the C040107B to drive in·
ductive loads, the load should be shunted
with a diode to prevent high voltages
from developing across the C040107B
output.
390 _____________________________________________________________________
CD40108B Types
COS/MOS 4 x 4 Multiport
Register
Features:
High·Voltage Types (20·Volt Rating)
The RCA·CD4010BB is a 4 x 4 multipart
register containing four 4·bit registers, write
address decoder, two separate read address
decoders, and two 3·state output buses.
When the ENABLE input is low, the cor·
responding output bus is switched, inde·
pendently of the clock, to a high·impedance
state, The high·impedance third state pro·
vides the outputs with the capability of being
connected to the bus lines in a bus·organized
system without the need for interface or
pull·up components.
When the WRITE ENABLE input is high,
all data input lines are latched on the positive
transition of the CLOCK and the data is
entered into the word selected by the write
address lines. When WR ITE ENABLE is low,
the CLOCK is inhibited and no new data is
entered. In either case, the contents of any
word may be accessed via the read address
lines. independent of the state of the CLOCK
input.
The CD4010BB types are supplied in
hermetic 24-lead dual-in-line ceramic
packages 10 and F suffixes), 24-lead dualin-line plastic packages IE suffix), 24-lead
ceramic flat packages IK suffix), and in chip
form IH suffix).
WRITE
ENABLE
• Four 4·bit registers
• One input and two output buses
• Unlimited expansion in bit and word
directions
• Data lines have latched inputs
• 3·state outputs
• Separate control of each bus, allowing
simultaneous independent reading of
any of four registers on Bus A and
Bus B and independent writing into
any of the four registers
• CD4010BB is pin·compatible with
industry type MC145BO
• Standardized, symmetrical output
characteristics
• 100% tested for quiescent current at 20 V
• Maximum input current of 1 /lA at 1B V
over full package·temperature range;
100 nA at 1B V and 250 C
• Noise margin lover full package·
temperature range):
1 VatVDD =5 V
2 Vat VDD = 10 V
2.5 V at VDD = 15 V
• 5·V, 10·V, and 15·V parametdc ratings
• Meets all requirements of JEDEC
Tentative Standard No. 13A, "Standard
Specifications for Description of 'B'
Series CMOS Devices"
-DATA
DO '0
{
DI
INPUTS
'-STATE A
. CO}
19
'!I
6
01
WOAD A
02 18
02
OUTPUT
o
7
C'
.
17
WRLTE I
READ 14
READ OA
23
01
WORD B
2
02
OUTPUT
, 0'
READ 18
READ
" 00}
os
3-STATEB
FUNCTIONAL DIAGRAM
WO WI ROA RIA ROB RIB
ENABLE B
Applications:
Fig. 1 - Block diagram.
• Scratch·pad memories
• Arithmetic units
• Data storage
AMBIENT TEMPERATURE {TA'-Z'·C
MAXIMUM RATINGS, Absolute·Maximum Values:
DC SUPPLYNOLTAGE RANGE, (VDDI
-0.5 to +20 V
(Voltages referenced to VSS Terminal)
-0.5 to VDD +0.5 V
INPUT VOLTAGE RANGE, ALL INPUTS
±lOmA
DC INPUT CURRENT, ANY ONE INPUT
POWER DIS~IPATION PER PACKAGE (Pol:
. . . . . . . ..
SOOmW
For TA = -40 to +60 0 C (PACKAGE TYPE EI
Derate linearly at 12 mW/oC to 200 mW
For TA = +60 to +850 C (PACKAGE TYPE EI
.
. . . . . . . ..
SOOmW
For TA = -55 to +1000 C (PACKAGE TYPES D,F)
Derate Linearly at 12 mW/oC to 200 mW
For T A = +100, to +12SoC (PACKAGE TYPES 0, F)
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
100mW
FOR TA = FULL PACKAGE·TEMPERATURE RANGE (All Package Tvpes)
OPERATING·TEMPERATURE RANGE (TAl:
-S5 to +12SoC
PACKAGE TYPES 0, F, H
-40 to +85 0 C
PACKAGE TYPE E .
-65 to +IS00C
STORAGE TEMPERATURE RANGE (Tstgl
LEAD TEMPERATURE lOURING SOLOERINGI:
At dist~nce 1/16
WRITE
ENABLE
I
0
lA
OA
lB
OB
A
B
on
anA
10
'V
10
15
DRAIN-lO-SOURCE VOLTAGE IVOSI-V
Fig. 2- Typical output low (sink I
current characteristics.
1
SI
S2
SI
S2
SI
S2
1
1
1
1
1
1
SI
S2
SI
S2
SI
S2
1
1
0
0
0
Z
Z
i<
x
x
x
x
x
x
0
0
X
~
1
Q
Q
0
1
1
Q
1
1
On 10
~
0
0
Q
0
1
1
Q
1
1
Word 0
X
.X
-_.
X
1--0
Q
1
1
1
X
X
X
X
X
X
X
1
1
x
ward 0
1
11()1.JltcfCd
oul
oul
Word 1 Word 2
Oul
Oul
Word 2 Word 1
uul
5
X
1 HIGH LEVEL. a lOW lEVE L. X DON"T CARE l= HHiH IMPfOANCE
51 andS2'l!te. IrJ '"pul SI"II'sol "lIh," I or a
lit!
WOld 1 Wmd2
out
~
II
°nB
~
X
~
5 ,
AMBIENT TEMPERATURE {TA,.25·C
WRITE WRITE READ READ READ READ ENABLE ENABLE·
~
x
lOV
g
± 1 i3~ inch (1.59 ± 0.79 mml from case for 10 s max.
TRUTH TABLE
CLOCK
GATE-lO-SOURCE VOLTAGE IV65'015 II
NC
NC
10
15
CRAIN-lO-SOURCE VOLTAGE (VOSI-V
Fig. 3- Minimum output Jow (sink)
current characteristics.
391
CD40108B Types
DRAIN-lO-SOURCE VOLTAGE IVosl-v
I
RECOMMENDED OPERATING CONDITIONS at TA = 250 C, Except as Noted.
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges:
VDD
(V)
CHARACTERISTIC
Supply Voltage Range
(For T A = Full Package
Temperature Range)
Set·Up Time:
Data to Clock, tS(D)
Write Enable to Clock,
tS(WE)
Write Address to Clock,
tS(WAI
Hold Time:
Data to Clock, tH(D)
Write Enable to Clock,
tH(WEI
Write Address to Clock,
tH(WA)
Clock Input Frequency,
feL
Clock Pulse Width,
CLor WE
tw
Clock Rise or Fall Time,
trCLor tfCL
LIMITS
MIN.
-
3
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
0
0
0
250
100
70
250
100
70
220
100
80
270
130
80
330
140
90
UNITS
MAX.
18
V
-
ns
-
ns
Fig. 5- Typical output high (sourcel
current characteristics.
-
-
DRAIN-lO-SOURCE VOLTAGE
-I!!
ns
-10
jVosl-v
-!I
0
ns
-
-
ns
ns
-
1.5
3.5
4.5
MHz
350
130
90
-
ns
15
5
-
-
Fig.
6- Minimum output high (source)
current characteristics.
tJ.S
5
LOAD CAPACITANCE IC\..I-pF
Fig.
7- Typical propagation delay
t,.':;S;;';19
function of load capacitance
reL or
WE to 01.
D,
WE
WA---r---------+-----f'-------~~''-~~-----------RA--_t.--~----~._~----------_t.----_+~~~
-=-::;:1
tPLH!::______
0,
-ll
tTLH
92Ctol-Z9221
Fig. 4- Timing diagram.
UCS-M,l'l
Fig. 8- Typical transition time as B function
of load capacitance.
392 _______________________________________________________________________
CD40108B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C; Input t"tf = 20 ns,
CL =50 pF, RL = 200kQ
CHARACTERISTIC
Propagation Delay Time:
tpHl' tplH
Clock or Write Enable to Q
Read or Write Address to Q
3·State Disable Delay Time:
tpZH. tpHZ
tpZl. tplZ
Output Transition Time:
tTHl' tTlH
Minimum Setup Time:
Data to Clock tS(D)
VDD
(V)
5
10
15
5
10
15
5
10
15
Maximum Clock Input Frequency.
fCl
Minimum Clock Pulse Width.
Clock or Write Enable
tW(Cl)
Write Address
tW(WAI
Average Input Capacitance.
(Any Input)
CI
-
-
ns
300
120
85
600
240
170
ns
100
50
40
200
100
80
ns
UNITS
5
10
15
-
100
50
40
200
100
80
ns
5
10
15
-
-95
-35
-20
0
0
0
ns
125
50
35
250
100
70
ns
125
50
35
-
250
100
70
ns
15
5
5
)ls
220
100
80
ns
-
-
5
10
15
-
110
50
40
5
-
135
270
10
15
-
65
40
130
80
5
10
15
-
165
70
45
330
140
90
ns
5
10
15
1.5
3.5
4.5
-
MHz
5
10
15
175
65
45
350
130
90
ns
5
10
15
-
150
75
45
300
150
90
ns
-
-
5
7.5
pF
-
3
7
9
o ~
SEQUENTIALLY,
TO BOTH VOD AND '-'55
CONNECT ALL UNUSED
INPUTS TO EITHER
-
-
DD
V~NPU(JS
V :~:~U' 'N.PUTS
'-'S5
5
10
15
-
,2tS-Z9ZI6
function of input frequency.
ns
-
INPUT FREQUEijCY Ull-kHZ
Fig. 9- Typical power dissipation as a
260
120
100
5
10
15
Write Address to Clock tH(WA)
-
-
720
280
200
130
60
50
Write Address to Clock tS(l.NA)
Write Enable to Clock tH(WE)
-
Max.
360
140
100
-
5
10
15
Minimum Hold Time:
Data to Clock tH(D)
-
LIMITS
Typ.
5
10
15
Write Enable to Clock tS(WE)
Clock Rise and Fall Time:
trCl. tfCl
Min.
Vss
Voo OR '-'S5
Fig. 10- Input leakage current
test· circuit.
.
ns
INPUTS
V55
Fig. 11- Ouiescent-device-current
test circuit.
INPurQVDOourpurs
---
V,H
~
:t
v~L
NOTE:
'-'55
TEST ANY COMBINATION
OF INPUTS
Fig. 12- Input-voltage test circuit.
_____________________________________________________________________ 393
CD40108B Types
STATIC ELECTRICAL CHARACTERISTICS
LIMITS AT INDICATED TEMPERATURES (DC)
Values at -55, +25, +125 Apply to D, F,H Packages
CONDITIONS
CHARACTER· 1-_ _.....,.._-,-_-1 Values at --40, +25, +85 Apply to E Packaga
ISTIC
Quiescent Device
Current.
100 Max.
UNITS
1----f-...!..-I--+--+-:-::-+-:::-::-::--+-:::-:-::-4---+-:,..,..,....t--:--1
/1 A
03.
Output Low
(Sink) Current
IOL Min.
,.
02.
3-STATE A
00.
rnA
Output High
(Source)
Current,
IOH Min.
,.,.
0' •
02.
D3.
WRITE I
Output Voltage:
Low·Level,
VOL Max.
,.
",.
'7
WRITE 0
READ 19
'0
READ DB
"
Vss
24
23
22
21
20
12
13
VDO
0'.
00.
3- STATE B
DO
0'
02
03
eLOCt(
WRITE ENABLE
REAO fA
READ OA
TOP VIEW
92C$-27697
V
TERMINAL ASSIGNMENT
Output Voltage:
High·Level,
VOH Min.
Input"Low
Voltage,
VIL Max.
V
Input High
Voltage,
VIH Min.
±10-5
±O.l
/1A
±10-4
±O.4
/1A
Dimensions in parentheses are in millimeters and are
derived from the basic inch" dimensions as indicated.
Grid graduations are in mils (10- 3 inchJ.
The photographs and dimensions of each COS/MOS
chip represent a chip when it is part of the wafer.
When the wafer is cut into chips, the cleavage angles
are 5]0 instead of 900 with respect to the face of
the chip. Therefore. the isolated chip is actually
7 mils (0.17 rom) larger in both dimensions.
-'34
92CS·29421
Dimensions and fad Lavout for CD40108BH
394 __________________________________________________________________
CD40108B Types
OOB
OIB
I
'''~
1:
*3-$TATE
B ENABLE
C
P
N
Q3B
r----------------- - - - - - - - - - - - - - - l
PIN 24: VOO
A
PIN 12 : VSS
ENABLE
C
Voo
I
d
i
~ OUT
PUT
q
w 0------+--
*
I
ALL INPUTS PROTECTED
BY COS/MOS INPUT
PROTECTION NETWORK
I
i
I
I
VS5
92CL-29422
1- DETAIL OF
LM.:M~R~C~'=_ _________ _
~~~T~~T~~
Fig. 13- Schematic diagram
P.G. I
PULSE GEN. 2
Jl.Jl.IlIL
I
______
J
92CL-29422
CL
P.G. 2~NABLE
ENAaL< ~VDD
INPlJT 50%
!SO,."
_Vss
tpL.Z
Q
~~
{IO%
CHAR TEST VOLTAGE tpHZ
tpHI
at 0
YOO
at Q
VSS
tpZH
'PL.Z
IpZL
V 0
VSS
VSS
VSS
VOO
VOO
Fig. 14- Output-enable-delay-times test
circuit and waveforms.
I
r:
L.!PZL
90% _Voo
P.G. I
VOL.
YOH
10% -Yss
PULSE GEN. 2
I--. pz "
PULSE GEN. I
92C"-29217
P,G.2
P.G.3
QnA,8~
PULSE GEN. 3
I-- REPETITIVE WAVEFORMs---l
92CN-2921BRI
Fig. 15- Power-dissipation test circuit
and waveforms.
395
CD40109B Types
COS/MOS Quad Low-to-High
Voltage Level Shifter Features:
• Independence of power supply sequence
consideratlons-VCC can exceed VDO, input
signals can exceed both VCC and VDD
• Up and down lavel-shifting capability
• Three-state outputs with separate enable controls
High-Voltage Types (20-Volt Rating)
The RCA-C040109B contains four low-tohigh-voltage level-shifting circuits. Each circuit will shift a low-voltage digital-logic
input signal (A, B, C, 0) with logical 1 = VCC
and logical 0 = VSS to a higher-voltage out·
put signal (E, F, G, H) with logical 1 = VOO
and logical 0 = VSS.
• Standardized, symmetrical output characteristics
• 100% tasted for quiescent current at 20 V
The RCA-C040109, unlike other low-to·
high level-shifting circu its, does not requ ire
the presence of the high-voltage supply
(VOO) before the application of either the
low·voltage supply (VccI or the input sig'
nals. There are no restrictions on the sequence of application of VOO, VCC, or the
input signals. In addition, there are no
restrictions on the relative magnitudes of
the supply voltages or input signals within
the device maximum ratings; VCC may
exceed VOO, and input signals may exceed
VCC and VOO. When operated in the mode
VCC > VOO, the C040109 will operate as
a high-to-Iow level-shifter.
MIN.
MAX.
3
18
Supply-Voltage Range (For T A =
Full Package-Temperature Range)
UNITS
V
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (VCC, VDD)
~.5to+20V
(Voltages referenced to VSS Terminal)
INPUT VOLTAGE RANGE. ALL INPUTS. .
~.5to+20V
±10mA
DC INPUT CURRENT. ANY ONE INPUT . .
POWER DISSIPATION PER PACKAGE (POl:
o
For T A = -40 to +60 C (PACKAGE TYPE EI
. . . . . . . •.
600mW
For TA = +60 to +85 0 C (PACKAGE TYPE EI
.
Derate Linearly at 12 mW/oC to 200 mW
For T A = -55 to +1000 C (PACKAGE TYPES D,F I
. . . . . • . ••
500mW
Derate Linearly at 12 mW/oC to 200 mW
For T A = +100 to +125 0 C (PACKAGE TYPES D. F)
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
loomW
FOR TA = FULL PACKAGE·TEMPERATURE RANGE (All Package Types)
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPES D. F. H
..... .
-55 to +1250 C
PACKAGE TYPE E . . . . . . . . . . . . . . .
-40" to +850 C
STORAGE TEMPERATURE RANGE (Tstgl . . . . . . • .
-65 to +160o C
LEAD TEMPERATURE (DURING SOLDERINGI:
At distance 1/16 ± 1/32 inch (1.59 ±0.79 mml from case for lOs max.
Applications:
Vee
V DD
VDD
J
TRUTH TABLE
INPUTS
ENABLE
A,B,C,D
A,B,C,D
1
1
0
OUTPUTS
~"",
9
VIS
E,F,G,H
0
1
Z
LOGIC 0 a LOW(VSS)
X - DON'T CARE
Z -HIGH (MPEDANCE
LOGIC 1 - VCC at INPUTS and VDD at OUTPUTS
396
LIMITS
CHARACTERISTIC
• High-or-Iow level-shifting with three-state
outputs for unidirectional or bidirectional
bussing
• Isolation of logic subsystems using separate power supplies from supply sequencing, supply loss and supply regulation
considerations
0
1
X
(1014 unlll'
RECOMMENDED OPERATING CONDITIONS
The C0401 09B-Series types are supplied in
16-lead ceramic dual-in-line packages (0
and F suffixes), 16-lead dual-in-line plastiC
packages (E suffix), 16-lead ceramic flat
packages (K suffix), and in chip form (H
suffix).
Low-to-high
level shift
FUNCTIONAL DIAGRAM
For maximum reliability, nominal optN'lIring condirions $hould btllIII«:trId
so that ope,."rion is IIIW11Y' within the following t'I/IIfI/IS:
The C040109 also features individual threestate output capability. A low level on any
of the separately enabled three-state output
controls produces a high-impedance state in
the corresponding output.
MODE
.2CI-I:I44.,
• Maximum input current of 1 /JA at 18 V
over full package-temperature range;.
100 nA at 18 V and 25 0 C
• Noise margin (full package-temperature
range)
= 1 Vat VCC = 5 V, VDD = 10 V
= 2 V at VCC = 10 V, VDD = 15 V
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative
Standard No. 13A, "Standard Specifications
for Description of 'B' Series CMOS Devices"
'ZCS-2t448
Fig. 1 - CD40I098 logic diogram (I of 4 un/ul.
CD40109B Types
STATIC ELECTRICAL CHARACTERISTICS
LIMITS AT INDICATED TEMPERATURES (DC)
Values at -55, +25, +125 Apply to D,.F,H Packages
Values at -40, +25, +85 Apply to E Package
UNITS
+25
VIN VDD
+85
+125 Min.
Typ.
Max.
(V)
(V) -55 -40
CONDITIONS
CHARACTERISTIC
Vo
(V)
Quiescent Device
Current,
IDD Max.
Output Low
(Sink) Current
IOLMin.
Output High
(Source)
Current,
IOH Min.
-
0,5
5
1
-
0,10
2
1
2
-
0,15
10
15
4
4
0,20
20
0.4
0,5
5
20
0.64
0.61
0.5
0,10
10
1.6
1.5
1.5
4.6
0,15
0,5
15
5
2.5
9.5
10
15
5
30
60
120
600 _
120
600
-
0.02
0.02
-
0.04
20
0.42
0.36
0.51
-
1.1
0.9
1.3
34
1
2.6
20
4
4.2
-0.64 -0.61
-2
-1.8
-1.6 -1.5
-4
-4.2
-
30
60
0.02
1
2
4
6.8
-1
-1.3
-1.1
-1.15 -1.6
-0.9 -1.3
-2.4 -3.4
-3.2
-2.6
-6.8
-
-
13.5
-
0,5
5
0.05
-
0
0.05
-
0,10
10
a
0.05
Output Voltage:
High-Level,
VOH Min.
-
15
5
-
0.05
0,15
0,5
10
15
4.95
9.95
5
10
-
0,10
0,15
0.05
0.05
4.95
9.95
14.95
0
-
14.95
15
-
I nput Current
liN Max.
0,18
18
±0.1
±0.1
±1
±1
-
±10- 5
±0.1
3-State Output
Leakage Current
lOUT Max.
0,18
18
±0.4
±0.4 .
±12
±12
-
±10-4
Input High
Voltage,
VIH Min.
-
V
-
IJA
DR"'N-TO'-""R" VOLTAGE tVosJ-V
Fig.3 - Minimum output low (sink)
Vo
(V)
Input Low
Voltage,
VIL Max.
current characteristics.
mA
-
Output Voltage:
Low·Level,
VOL Max.
-
Fig.2 - Typical output low (sink)
-
2.4
-0.36 -0.51
0,5
0,10
0,15
-
ORAtH-TO-SOURCE VOLTAGE (VDS)-V
-
2.8
-0.42
-2.8
IJA
1,9
±0.4
Il A
current characteristics.
Vec VDD
(V)
(V)
5
10
10
1.5, 13.5
1,9
1.5,13.5
5
10
10
15
15
1.5
3
-
-
1.5
-
3
3.5
3.5
-
7
7
-
V
-
Fig.4 - Typical output high (.ource).
DRAIN-lO-SOURCE VOLTAGE tVosl-V
L.OAD CAPACITANCE (CL1-p~2C'_ZB44.
Fig.S - Minimum output high (source)
current characteristics.
F;g.6 - Typical transition time as a function
of load capacitance.
Fig.7 - Typical high-to-Iow propagation delay time
as a function of load capacitance.
397
CD40109B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at T A
CL = 50 pF, RL = 200 kn
CHARACTERISTIC
Propagation Delay - Data Input
to Output:
SHIFTING
MODE
VCC
(VI
VDD
(VI
L-H
5
5
10
10
15
15
300
220
180
600
440
360
H-L
10
15
15
5
5
10
850
850
290
161)Q
1600
580
L-H
5
5
10
10
15
15
130
120
70
260
240
140
H-L
10
15
15
5
5
10
230
230
80
460
460
160
L-H
5
5
10
10
15
15
60
50
35
120
100
70
H-L
10
15
15
5
5
10
120
120
40
240
240
80
L-H
5
5
10
10
15
15
370
300
250
740
600
500
H-L
10
15
15
5
5
10
850
850
350
1600
1600
700
L-H
5
5
10
10
15
15
320
230
180
640
460
360
H-L
10
15
15
5
5
10
800
800
280
15')0
1500
560
L-H
5
5
10
10
15
15
100
80
40
200
160
80
H-L
10
15
15
5
5
10
120
120
40
240
240
80
L-H
5
5
10
10
15
15
50
40
40
100
80
80
H-L
10
15
15
5
5
10
100
100
50
200
200
100
Any Input
5
High·to·Low Level, tpHL
Low-to·High Level, tpLH
3·State Disable Delay:
Output High to High
Impedance, tpHZ
Output Low to High
Impedance, tpLZ
High Impedance to
Output High. tpZH
High Impedance to
Output Low, tpz L
Transition Time, tTHL, tTLH
Input Capacitance, CI
=25°C, Input t" It =20 ns,
LIMITS
Typ.
Max.
7.5
UNITS
ns
Fig.8 - Typicallaw·ro-high propagation delay time
as a function of load capacitance.
. ns
ns
7.5
10
12.5
15
SUPPLY VOLTAGE (Vool-V
ns
20
Fig.9 - Typical input switching as a function of
high·/evelsupply voltage.
ns
ns
SUPPLY VOLTAGE (vccJ-V
Fig. 10 - High-/evel.upply voltage
low-level supply voltage.
lIS.
ns
pF
Fig. l ' - Typical dynamic power dissipation as a
function of input frequency.
398.·_________________________________________________________________
CD40109B Types
TEST CIRCUITS
H". TIEST 'IOLT"GE
,
'PHZ
'PZL
IpZH
cc
55
•Vos
v••
v••
INPUTS
D
Vss
co
Fig. 13 - Qu;es::ent device current.
Fig. 12 - Output enable delay times test circuit and waveforms.
Vee
Voo
1NPUOS
Ve Vco
:~:~URE INPUTS
Vee
~
SEQUENTIALLY,
Vss
TO BOTH Voo AND Vss'
CONNECT ALL UNUSm
INPUTS 10 EITHER
Vee OR Vss'
NOTE:
TESf ANY COMBINATION
Vss
nCS-i.l4U
OF INPUTS
Fig. 14 - Input voltage.
Vee
ENABLE A
A
E
F
3
•
• ••
ENABLE B
Vss
I.I.I.
13
"
"9
10
Fig. 15 - input current.
Fig. 16 - Dynamic power dissipation te,t circuit.
Voo
ENABLE D
0
H
Ne
1
G
e
ENABLE C
TOP VIEW
CD40109B
TERMINAL ASSIGNMENT
72-80
1.829-2.032.
Dimensions in parentheses are in millimeters and
are derived from the basic inch dimensions as indicated. Grid graduations are in mils (1(J3 inch).
The photographs and dimensions of each COS/MOS
chip represent a chip when it is part of the wafer.
When the wafer is cut into chips, the cleavage
angles are 57° instead of 90° with respect to the
face of the chip. Therefore, the isolated chip is
actually 7 mils (0. 17 mm) larger in both dimensions.
Dimensions and pad layout for CD40 1098H.
399
CD40110B Types
Preliminary Data
COs/MOS Decade UpDown Counter/Decoder/
Latch/Driver
High-Voltage ·Type (20-V Rating) .
OISPLAY
101 11i'131&115161 118191
o
I
2
:3
4
5
6
7
8
9
S.: .
,
The RCA·C040110B Is a dual-clocked
up/down counter with a special precondl·
tlonlng circuit that allows the counter to
be clocked, via positive going Inputs, up
or down regardless of that state or timing
(within 100 ns typ.) of the other clock line.
The clock signal Is fed Into the control
logic and Johnson counter after It Is
preconditioned. The outputs of the
Johnson counter (which Include antl·lock
gating to avoid being locked at an Illegal
state) are fed Into a latch. This data can
be fed directly to the decoder through the
latch or can be strobed to hold a par·
tlcular count while the Johnson counter
continues to be clocked. The decoder
feeds a seven-segment bipolar output
driver which can source up to 25 mA to
drive LEOs and other displays such as
low-voltage fluorescent and Incandescent
lamps.
,
Voc a l6
Features:
vss·e
.. Separate clock-up and clock-clown lines
• Capable of driving common cathode LEOs and
other displays directly
• Allows cascading without any external circuitry
• 100% tested for quiescent current at 20 V
• Maximum Input current of 1 ,..A at
18 V over full package-tempera·
ture range; 100 nA at 18 V and 25°C
• Nolse-' margin (full package·
temperature range) =
1 Vat VDD = 5 V
2VatVDD = 10V
2.5 V at VDD = 15 V
• 5·V, 10·V and 15·V parametric
ratings
FUNCTIONAL DIAGRAM
92CS-3 1 375
MAXIMUM RATINGS, Absolute-Maximum Values:
Applications:
DC SUPPLY·VOLTAGE; RANGE, (VDD)
(Vollages referenced 10 VSS Terminal) . . . . . . . . . . .. . . . . . . . . . . .............. -0.510 +20 V
INPUT VOLTAGE RANGE, ALL INPUTS ........... , ....................... -0.510 VDD +0.5V
DC INPUT CURRENT, ANY ONE INPUT ............................................. ± 10 mA
POWER DISSIPATION PER PACKAGE (PO):
For TA = - 40 10 + 60·C (PACKAGE TYPE E) ...................................... 500 mW
For TA = + 60 10 + 85·C
(PACKAGE TYPE E) ................................. Derale Linearlyal 12 mW/·Clo 200 mW
ForTA = -5510 + 100·C (PACKAGE TYPES D,F) .................................. 500mW
For TA = + 10010 + 125·C
.
(PACKAGE TYPES D,F) .............................. Derale Linearly al 12 mW/·C 10 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE·TEMPERATURE RANGE
(All Package Types) ............................................................ 100 mW
OPERATING·TEMPERATURE RANGE (T A):
PACKAGE TYPES D,F,H ................................................. -5510 + 125·C
PACKAGE TYPE E ....................................................... - 40 10 + 85·C
STORAGE TEMPERATURE RANGE (T slg) ..................................... - 6510 + 150·C
LEAD TEMPERATURE (DURING SOLDERING):
AI dislance 1116 ± 1132 inch (1.59 ± 0.79 mm)
from case for 10 s max .......................................................... + 265·C
• Rate comparators
• General counting ,applications
where display Is desired
• Upldown counting appllcallons
where Input pulses are random
In nature
RECOMMENDED OPERATING CONDITIONS at TA = 25" C, Except as Noted.
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the fol/owing ranges'
A short duration negative-going pulse ap·
pears on the BORROW output when the
count changes from 0 to 9 or the CARRY
output when the count changes from 9 to
O. At the other times the BORROW and
CARRY output are a logic 1.
The CARRY and BORROW outputs can be
tied directly to the clock·up and clock·
down lines respectively of another
C040110B for easy cascading of several
counters.
The C040110B types are supplied in
16-lead dual-in·line ceramic packages (D
and F suffixes), and 16·lead dual·in-line
plastic package (E suffix).
CHARACTERISTIC
Supplv-Voltage RaJige
(For T A = Full Package
Temperature Range)
VDD
(V)
-
LIMITS
ALL TYPES
MIN.
3
UNITS
MAX.
18
V
400 _________________________________________________________________
CD40110B Types
STATIC ELECTRICAL CHARACTERISTICS
Limits at Indicated Temperatures (oC)
Conditions
Values at -55, +25, +125for D,F,H Package
Values at -40, +25, +85 for E Packages
Characteristic
IOH
(rnA)
Quescent Oevic
Current:
100 Max.
Output Voltage:
-
-
-
-
-
-
VOL Max.
High·level
-
Input low
-
Voltage,
-
-
0.5,3.8 1,B.8 1.5,13.8 0.5,3.B 1,8.8 1.5,13.8 -
0
10
25
0
10
25
0
10
25
(Sink) Current,
-
Input Current,
liN Max.
-
-
-
-
-
-
-
-
-
-
-
0.4 0,5
0.5 0,10
1.5 0,15
-
IOl Min.
-
-
-
Output low
15
5
10
15
-
-
-
-
Output Drive
Voltage
VOH Min.
0,15
0,5
0,10
0,15
-
-
-
Voltage,
VIH Min.
0,5
0,10
5
10
15
20
5
10
-
-
-
Vil Max.
Input High
VIN VDD
(V)
(V) -55 -40
-
-
Min.
!VI
-
low· level
VOH
Vo
-
S
Typ.
Max.
0.04
0.04
0.04
0.08
0
0
0
4.55
5
10 JJ.A
20
100
0.05
0.05 V
0.05
5
5 150
10 300
10
20
20 600
100 100 3000
0.05
0.05
0.05
150
300
600
3000
-
-
-
-
-
-
-
-
-
-
9.55
14.55
-
-
1.5
-
-
-
3
4
3.5
7
11
-
-
-
5
10
15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
3
4
3.5
7
11
5
10
15
5
5
5
10
10
10
15
15
15
+25
+85 +125 Min.
-
-
-
-
-
-
-
-
-
-
4.55
4.13
3.64
9.55
9.25
8.85
14.55
14.21
13.9
5 0.64 0.61 0.42 0.36 p.51
10
1.6 1.5
1.1 0.9 1.3
15 4.2
4
2.8 2.4 3.4
0,18 0,181 18 ±0.1 ±0.1
±1
±1
-
U
N
I
T
1
2.6
6.8
±10- 5
-
-
V
-
-
V
V
-
-
-
V
-
rnA
-
±0.1 JJ.A
CLOCK UP -.l~------,
CLOCK OOWN
RESET--I------...J
~TO"'OO~LE~E
..~ua.L·E-r_-----~
LATCH ENABLE
-t------~
92CS-29200RI
Fig. I-Functional diagram.
______________________
~
_______________________________________________ 401
CD40110B Types
Ti~Z
R
W
00
DC
o
'teLA
YCL8
y
CL C
"0"
y
CL D
z
TE
"0"
y
CL E
z
TE
~
R
W
W
DETAIL LOGIC
D
O L:
TE
R
=
TE
------~-
I------+.--ii
VOO
r-;::-CL
CL
CL~C[
OUTPUT
DRIVER
tn
~
..
(ALL 7 SEGMENTS)'
Fig. 2 - Logic diagram with f/ip4/op and output-driver details.
(cont'd next page).
~
L
Vo
25-50a
92CL-31384
Vas
402 __________________________________________________________________
CD40110B Types
t;
D.
0
r
B
DB
C
DC
•
E
A
B
DO
DE
A'
T
1:"
0
c
0
QA~ ...l'-... ""
Q~~BORROW
QO.~~
QE~CARRY
V
Fig.2 - Logic diagram with flip-flop and output-driver details (cont'd from previous page).
TERMINAL ASSIGNMENT
DISPLAY SEGMENTS
I
I.
7-SEGMENT { :
OUTPUTS
'I-Ib
·1
_Q
Ie
f
TOGGLE ENABLE
15
3
14
4
13
RESET
LATCH ENABLE
12
6
"
CLOCK DOWN
10
Vss
9
Voo
:.}'~."m
d
OUTPUTS
-
BORROW
CARRY
CLOCK UP
TOP VIEW
92CS-31376
9ZCS-31317
403
CD40110B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, Input t r, tf = 20 ns,
CL = 50 pF, RL = 200 kH
CHARACTERISTIC
Test
Conditions
LIMITS
All Packages
VDD
Volts
Typ.
UNITS
Clock Up/Clock Down
Minimum Pulse Width
5
10
15
85
35
15
ns
Maximum Frequency
5
10
15
2.5
5
8
MHz
Minimum CARRY Pulse Width
5
10
15
225
100
70
Minimum BORROW Pulse Width
5
10
15
260
110
80
5
10
15
750
285
200
Delay from Reset to first allowable Clock
5
10
15
300
125
75
Minimum Pulse Width
5
10
15
150
60
40
ns
Reset
Propagation Delay Time Reset to Clock
tpHL' tpLH
ns
TRUTH TABLE
CLOCK
UP·
~
X
CLOCK
DOWN*
X
--1
~~
LATCH
ENABLE
TOGGLE
ENABLE
RESET COUNTER
DISPLAY
0
0
0
Increments
by 1
0
0
0
Decrements
by 1
Follows
Counter
X
X
0
No Change
No Change
X
X
1
Goes to
00000
Follows
'Counter
(Display =
Follows
Counter
X
X
X
X~
X
1
0
Inhibited
X
1
0
0
Increments
by 1
Remains Fixed
1
0
0
Decrements
Remains Fixed
--.I
X
X :::: Do"n't care
~
1 :;;: High State
D')
Remains Fixed
by 1
0:;;:; Low State
• Typically 100 ns between dock·up and clock-down positive transitions are
required to ensure proper counting.
404 ______________________________________
~
____________________________
CD40147B Types
Features:
10-Line to 4-Line
BCD Priority Encoder
• Encodes 10·line to 4-line BCD
• Active low inputs and outputs
• Standardized, symmetrical output characteristics
.100% tested for quiescent current at 20 V
• 5-V, 10·V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative Standard
No. 13A, "Standard Specifications for Description of 'B'
Series CMOS Devices"
• Maximum input current of 1 /lA at 18 V over full
package-temperature range; 100 nA at 18 V and 250 C
• Noise margin Ifull package-temperature
range) =
1 V at VDD = 5 V
2 Vat VDD = 10 V
2.5 V at VDD = 15 V
High-Voltage Types (20-Volt Rating)
The RCA·CD40147B COS/MOS encoder features priority encoding of the inputs to ensure
that only the highest·order data line is en·
coded. Ten data input lines (0·9) are en·
coded to four·line (B.4,2,1) BCD. The highest
priority line is line 9. All four output lines are
logic 1 (VSS) when all input lines are logic O.
All inputs and outputs are buffered, and each
output can drive one TTL low·power Schottky
load. The CD40147B is functionally similar to
The CD40147B types are supplied in 16- I
lead ceramic dual-in-line packages (0 and F
suffixes). 16-lead dual-in-line plastic packages (E suffix), 16-lead ceramic flat packages (K suffix). and in chip form (H suffix).
i FUNCTiONALGAllNG--- - --I
0
I*®----{)---
I 1i
I9
I
I7_ 6
I '4
I
I ,--"'=M''F'.-/
A ,.
92CS-30~52
FUNCTIONAL DIAGRAM
• Keyboard encoding
• 10·line to BCD encoding
• Range selection
. RECOMMENDED OPERATI NG CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following range:
LIMITS
CHARACTERISTIC
:
Supply Voltage Range (For T A = Full Package
Temperature Range)
I
I
Min.
Max.
3
18
UNITS
V
TRUTH TABLE (Negative Logic)
I3
INPUTS
I
I
I
I
£rVOD
o
-~VSS
"7 '6
ii
92CM- 30956
COS/MOS PROTECTION NETWORK
AMBIENT
·
,
1
~15
3
4
5
6
7
8
9
b
C
B
A
0
0
0
1
X
0
0
0
1
X
X
X
0
0
0
0
1
X
0
0
0
0
0
1
X
X
0
0
0
0
0
0
1
X
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
X
X
1
0
0
0
0
1
1
1
1
1
0
0
1
1
X
X
0
0
0
0
0
0
0
0
0
1
0
0
0
0
X
X
X
0
0
0
0
0
0
0
0
1
X
0
X
X
X
X
0
0
X
X
X
X
X
X
X
__
...
Low Level
0
1
0
0
1
1
X
Don't Care
0
0
1
1
0
1
0
1
DRAIN-TO-SOURCE VOL.TAGE (VQsl-V
1
........
!: GATE-lO-SOURCE
10::: ::!: ::+ ...•
z
!!
75 h •
·
X
High Level
~
,
X
0
1
0
0
citt:I;:tjj:::
1:::;:-:
125 -+ .:...
g•
X
X
X
X
X
X
X
TEM~~H~~;t~11;25.C
a
...... ..
...
VOLTAGE (VGSI"SII
+ .. - ..
.. lOV"
,
~25~
5V
5
Fig. 2 - Typical output low (sink) current
2
o
Fig. 7 - CD407478 logic diagram.
ORAIN-TO-SOURCE VOLTAGE (VoSI-V
1
X
X
X
X
,
OUTPUTS
0
". 1
X
X
c X
X
D X
* INPUTS PROTECTED BY
characteristics.
" ,I
c "
Applications:
tl:1e TTL 54/74147 if pin 15 is tied low.
o*@)----\)-----
D "
10
15
ORAIN-TO-SOURCE VOL.TAGE IVosl-V
Fig. 3 - Minimum output low (sink) current
charar;teristics.
Fig. 4 - Typical output high (source) current
characteristics.
405
CD40147B Types
ORAIN-TO-SOURCE VOLTAGE (Vosl-V
MAXIMUM RATINGS. Absolute·Maximum Values:
-I'
DC SUPPLY·VDLTAGE RANGE, IVODI
-10
.,
AMBIENT TEW'ERATURE [TA'.25-C
··0.5 to +20 V
·0.5 to VOO +0.5 V
±10mA
(Voltages refertmced to VSS Terminal!
INPUT VOLTAGE RANGE, ALL INPUTS
DC INPUT CURRENT, ANY ONE INPUT
POWER DISSIPATION PoER PACKAGE IPOI:
..
..
500mW
For T A: -40 to +60 C IPACKAGE TYPE EI
Derate Linearly at 12 mW/C to 200 mW
For T A = +60 to +85°~ IPACKAGE TYPE EI
For T A = -55 to +100 C IPACKAGE TYPES 0, FI
.
.
. o.
500 mW
For T A: +100 to +125°C IPACKAGE TYPES 0, FI
Derate Llnearlv at 12 mWI eta 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA : FULL PACKAGE·TEMPERATURE RANGE IAII Package Types)
100mW
OPERATING·TEMPERATURE RANGE IT AI
PACKAGE TYPES 0, F, H
·:55 to + 125°C
PACKAGE TYPE E
-40 to +-SS:C
STORAGE TEMPERATURE RANGE IT" I
. .
-65 to +150 C
LEAD TEMPERATURE lOURING SOLO~RINGI:
At distance 1/16 ± 1/32 Inch (1.59 ± 0.79 mml from case for 10 s max,
+265°C
-.
-1011
.- ..
·0
+-~.
..
'-1"';+
.1
Fig. 5 - Minimum output high (source}current
STATIC ELECTRICAL CHARACTERISTICS
LIMITS AT INDICATED TEMPERATURES (oCI
U
Values at -55. +25. +125 Apply to D, F. H Packages N
Values at -40, +25, +85 Apply to E Package
CONDITIONS
CHARACTERISTIC
Vo
(VI
VIN VDD
(VI (VI -55
0.5
Quiescent
5
+85
-40
1
30
+125
Min.
30
+25
Typ,
Max,
T
S
0.02
Device
t--_ _-t0_•...,.I.,,0-t-l_0-t_---,-2+-_-:-2-t--:-::6:-:0-t--:-::6:-:0:-t-_---i_0_._02_+-_2-lIlA
Current. I DD
0.15 15
4
4
120
120
0.02
4
Max,
~--~~~~~~~~~~-=~---+~~~-4
0,20
Output Low
(Sink)
Current
IOL Min.
Output High
(Source)
Current.
IOH Min.
20
20
20
600
600
0.04
0.4
0.5
1.5
0,5
5
0.64
0.61
0.42
0,36
0.51
1
0.10
0.15
10
15
1.6
4.2
1.5
4
1.1
2.8
0.9
2.4
1.3
3.4
2.6
6.8
4.6
2.5
0.5
0,5
9.5
13.5
0,10
0,15
20
5 -0.64 -0.61 -0.42 -0.36 -0.51
-1
5
-2 -1.8 -1.3 -1.15 -1.6 -3.2
10
15
-1.6
-4.2
-1.5
-4
-1.1
-2.8
-0.9
-2.4
-1.3 -2.6
-3.4 -6.8
Output Voltage: t--_ _-t::-0_,.,,5-t-.,.,5-t-----,0:-.=c05::-----t---I1--0--t-0-.-05-j
Low·Level.
0,10 10
0.05
0
0,05
VOL Max.
0,15 15
0.05
0
0.05
~--------~---+--~~----------------+----r--~--~V
Output Voltage: f--_ _+0~..,,5+-.,.,5:-+-----,4:-.=-95::----+_:4:-.9::_:5:+--5.:......+--l
High·Level,
0,10 10
9.95
9.95
10
0,15
15
14.95
0.5,4.5
1.9
1.5,13.5
5
10
15
1.5
3
0.5,4.5
1,9
1.5,13.5
5
10
15
3.5
VOHMin.
Input Low
Voltage,
VIL Max.
~
Fig. 6 - Typical transition time as a function of
load capacitance.
14.95
LOAD CAPACITANCE (CL1-pF
.2CS.3(I.5S
Fig. 7 - Propagation delay time as a function
of load capacitance.
loS AMBIENT TEMPERATURE (TAl - 2'-
15
1.5
3
4
4
__----__+-__--~-+--~----------------+-__~--__~~V
Input High
Voltage,
VIHMin.
3.5
7
11
7
11
L-~-L~~IO-L~~I~OI~~~I~~~~~IO~.~.~~,~
I"UT FREQUENCY
I nput Current
IINMax.
0.18
18
;to. 1
±1
±10- 5 ±0.1 IlA
"IN'-
kHz
Fig. 8 - Typical dynamic power dissipation
as a function of input frequency.
406 ____________________________________________________________________
CD40147B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA =25°C, Input t r, tt =20 ns,
Cl =50 pF, Rl = 200 kn
LIMITS
All TYPES
TEST CONDITIONS
CHARACTERISTIC
VOO
UNITS
VDD
!VI
Propagation Delay Time,
tplH' tpHl
In·Phase Output
Any input to any
output
Out·ol·Phase Output
Transition Time, tTHl' tTlH
Max.
450
900
10
200
400
15
150
300
5
10
425
175
850
350
15
125
250
5
100
200
10
50
100
15
40
80
5
7.5
Any Input
Input Capacitance, Cl
.
Typ.
5
INPUTS
ns
92CS-30953
ns
Fig. 9 - Dynamic power dissipation
test circuit.
ns
pF
'NPUTOVOOOUTPUTS
Vss
V'H
V~.
~
V~NPU(J'
'. ::~".~
o ~
SEOUENTIALLY,
TO BOTH liDO AND Vss'
CONNECT ALL UNUSED
\Iss
INPUTS TO EITHER
NOTE:
Vss
Vss
liDO OR Vss'
~~'JN~'1,~~OMBINATION
Vss
IlZCS·2140IRI
Fig. 11 - Input voltage test circuit.
Fig. 10 - Ouiescent device
Fig. 12 - Input current test circuit.
current test circuit.
'6
Voo
,.
15
a
,.
13
"
'a
Vss
TOP VIEW
92CS·30957
CD40147B
TERMINAL
ASSIGNMENT
DimensIons In parentheses are in millimeters and
are derived from the basic inch dimensions as indicated. God graduations are in mils (10-- 3 inch).
The photographs and dimensIons of each COS/MOS
chip represent a chip when it is part of the wafer.
When the w~f~r is cut int~ Ch~ps. the cleavage
angles are 57 Instead of 90 with respect to the
face of the chip. Therefore, the isolated chip is
actually 7 mils (0.17 mm) larger in both dimensions.
92CM-30958
Dimensions and pad layout for CD40147BH
407
CD40160B, CD40161B, CD40162B, CD40163B Types
COS/MOS Synchronous Features:
Programmable 4-Bit
• Internal look-ahead for fast counting
• Carry output for cascading
Counters
• Synchronously programmable
• Clear asynchronous Input
(CD40160B, CD40161BI
• Clear synchronous input
CD40160B - Decade with Asynchronous
(CD40162B, CD40163BI
• Synchronous load control input
Clear
CD40161B - Binary with Asynchronous • Low-power TTL compatibility
• Standardized, symmetrical output
Clear
characteristics
CD40162B - Decade with Synchronous
.100% tested for quiescent current at 20 V
Clear
• Maximum input current of 1 JLA at 18 V
CD40163B - Bin~ry with Synchronous
over full package-temperature range;
Clear
100 nA at 18 V and 250 C
• Noise margin (over full package-temperaRCA-CD40160B, CD40161B. CD40162B.
ature rangel: 1 Vat VDD = 5 V
and CD40163B are 4-bit synchronous pro2VatVDD=10V
2_5VatVDD=15V
grammab(e counters. The CLEAR function
• 5-V, 10-V, and 15-V parametric ratings
ofthe CD40162B and CD40163B is synchro• Meets all requirements of JEDEC
nous and a low level at the CI:EA"Fi input sets
Tentative Standard No_ 13A, "Standard
all four outputs low on the next positive
Specifications for Description of 'B' Series
CLOCK edge. The CLEAR function of the
CMOS Devices"
CD40160B and CD40161B is asynchronous
and a low level at the CLEAR input sets all
duration approximately equal to the positive
four outputs low regardless of the state of
portion of the Q1 output. This positive
the CLOCK. LOAD, or ENABLE inputs. A
overflow carry pulse can be used to enable
low level at the LOAD input disables the
successive cascaded stages. Logic transitions
counter and causes the output to agree with
at the PE or TE inputs may occur when the
the setup data after the next CLOCK pulse
clock is either high or low.
regardless of the conditions of the ENABLE
The CD40l60B, CD40l6l B, CD40l62B, and
inputs.
CD40l63B types are supplied in l6-lead
hermetic dual-in-line ceramic packages (D
The carry look-ahead circuitry provides for
and F suffixes), 16-lead dual-in-line plastic
cascading counters for n-bit synchronous
packages (E suffix), l6-lead ceramic flat
applications without additional gating.lnstrupackages (K suffix), and in chip form (H
mental in accomplishing this function are
suffix).
two count-enable inputs and a carry output
The CD40160B through CD40163B types
(COUT). Counting is enabled when both PE
are functionally equivalent to and pin-comand TE inputs are high. The TE input is fed
patible with the TTL counter series 74160
forward to enable COUTo This enabled outthrough 74163 respectively.
put produces a positive output pulse with a
High-Voltage Types (20-Volt Rating)
P'
T'
10
CLEAR
"
13
01
02
LoAri
CLOCK
12
0'
PI
O.
.,
P2
P'
"
CARRY
OUT
VDD a l6
VSS·S
92CS-Z8&28R1
Functional Diagram
Applications:
• Programmable binary and decade counting
• Counter control/timers
• Frequency dividing
DRAIN-TO-SOURCE VOLTAGE {VDSI-V
Fig. 1- Typical output low 'sink}
current characteristics.
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE. (VDDI
. -0.5 to +20 V
(Voltages referenced to V S5 Terminal) . .
-0.5 to V DD +0.5 V
INPUT VOLTAGE RANGE. ALL INPUTS. .
±10mA
DC INPUT CURRENT. ANY ONE INPUT .
POWER DISSIPATION P.,ER PACKAGE (POl:
. . . . . . . •.
500mW
For T A = -40 to +60. C (PACKAGE TYPE E)
Derate Linearly at 12 mW/·C to 200 mW
For T A = +60 to +85
(PACKAGE TYPE E). •
.
•
.
.
.
.
.
•
.
500mW
For T A = -55 to +100
(PACKAGE TYPES D. FI
Derate Linearly at t2 mWloC to 200 mW
For TA = +100 to +125 C (PACKAGE TYPES D. FI
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
100mW
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types)
OPERATING-TEMPERATURE RANGE (TAl':
-55 to+125·C
PACKAGE TYPES D. F. H
-40 to +85°C
PACKAGE TYPE E
-65 to +150·C
STORAGE·TEMPERATURE RANGE (Tst ) . .
LEAD TEMPERATURE (DURING SOLD~RING):
. . • +265·C
At distBnee 1116 ± 1/32 inch (1.59 ± 0.79 mm) from eBse for 105 ma •.
ct,
!?
.RAIIN-Ttl-SOUReE VOLTAGE
Fig. 2- Minimum output low 'sink}
current characteristics.
408 _______________________________________________________________
CD40160B, .CD40161 B,CD40162B, CD40163B Types
...
C040160B AND C040162B BCD DECADE COUNTERS
...
...
...
*
8DD
* INPUTS
PROTECTED
BV' COS/MQS PROTECTioN
NETWORK
___ _
15 Cour
Vss
92CL·29224RI
Fig. 3- Logic diagrams for CD407608 and CD407628 8CD decade counters.
C0401618
C0401618 AND C0401638 BINARY COUNTERS
ASYNCHRONOUS CLEAR
*
•
P3
>--+--'---1
;>4-------'--!--=l==::j:;::=t=+~:t=t~
.
INPUTS PROTECTED
&1VDD
~~TC:~~DS PRDTECTION
__ _
Vss
92CL-29225RI
Fig. 4- Logie diagrams for CD407678 and CD407638 binary counters.
__________________________________________________________________ 409
CD40160B, CD40161B, CD40162B, CD40163B Types
RECOMMENDED OPERATING CONDITIONS at TA = 2SOC, Except as Noted
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges:
CHARACTERISTIC
VDD
(VI
Supply Voltage Range (Full T A = Full PackageTemperature Rangel
Setup Time: tsu
Data to Clock
LIMITS
MIN.
-
3
UNITS
MAX.
240
90
60
Load to Clock
5
10
15
240
90
60
PE or TE to Clock
5
10
15
340
140
100
Clear to Clock
,(CD40162B, CD40163B)
5
10
15
340
140
100
All Hold Times,
5
10
15
0
0
0
Clear Removal Time,
t rem
(CD40160B, CD40161 B)
5
10
15
200
100
70
Clear Pulse Width,
tWL
(CD40160B, CD40161BI
5
10
15
170
70
50
-
-
Clock Input Frequency,
5
10
15
-
2
5.5
-
8
5
10
15
170
70
50
-
5
10
15
-
200
70
15
Clock Pulse Width,
fCL
tw
Clock Rise or Fall Time, trCL or tfCL
-
V
18
-
5
10
15
tH
DRAIN-lO-SOURCE VOLTAGE IVos;}-V
-
ns
-
-
-
ns
Fig. 5- Typical output high (sourceJ
current characteristics,
ns
DRAIN-lO-SOURCE VOLTAGE {VOSI-V
-1~
-10
-~
AMBIENT TEMl'fRATUR£ ITAJ.25·C
GATE-TO-SOURCE VOLTAGE
I~S)'"
v
ns
-
-IOV
ns
-
ns
ns
-
-
9lCS-l.3l,Rl
Fig.
6- Minimum output high (source)
current characteristics.
MHz
ns
/.Is
ro
~
~
LOAD CAPACITANCE ICL,l-pF
~
~
92CS-29971
Fig. 7- Typical propagation delay time as a
function of load capacitance
(CLOCK to OJ.
TRUTH TABLE
CLO.CK
CLR
LOAD
PE
TE
1
0
X
X
PRESET
1
1
0
X
NC
1
1
X
0
NC
1
1
1
1
COUNT
0
X
X
X
RESET (CD40160B, CD40161BI
0
X
X
X
RESET (CD40162B, CD40163BI
1
X
X
X
NC (CD40162B, CD40163BI
..r
..r
...r
.r
.r
X
"\..
OPERATION
Fig.
8- TYPIcal tra,j~;tion time as a function
x • DON'T CARE
of load capacitanc~.
NC = NO CHANGE
410 __________________________________________________________________
1 • HIGH LEVEL
O-LOWLEVEL
CD40160B, CD40161 B, CD40162B, CD40163B Types
STATIC ELECTRICAL CHARACTERISTICS
liMITS AT INDICATED TEMPERATURES (DC)
CHARAC·
TERISTIC
CONDITIONS
Vo
(V)
-
Values at -55, +25, +125 Apply to D,F,H Packages
Values at -40, +25, +85 Apply to E Package
+25
VIN VDD
(V)
(V) -55
-40
+85
+125
Typ.
Min.
-
Max.
0,5
5
5
5
150
150
0,10
10
10
10
300
300
0,15
15
20
20
600
600
0,20
20
100
100
3000
3000
Output low
(Sink) Current 0.5
IOl Min.
1.5
0,5
5
0.64
0.61
0.42
0.36
0.51
1
-
0,10
10
1.6
1.5
1.1
0.9
1.3
2.6
-
0,15
15
4.2
4
2.8
2.4
3.4
6.8
4.6
0,5
5
-0.42 -0.36 -0.51
-1
2.5
0,5
9.5
0,10
13.5
-
-
Quiescent
Device
Current,
IDD Max.
0.4
Output High
(Source)
Current,
IOH Min.
Output Voltage:
low·level,
VOL Max.
Output
Voltage:
High-level,
VOH Min.
Input Low
Voltage
VIL Max.
Input High
Voltage,
VIHMin.
Input Current
liN Max.
-0.64 -0.61
u
N
I
T
S
0.04
5
0.04
10
0.04
20
0.08
100
IlA
- Fig. 9- Typical power alssipatlon as a
function of CLOCK frequency.
-1.8
-1.3 -1.15
-1.6
-3.2
10
-1.6
-1.5
-1.1
-0.9
-1.3
-2.6
0,15
15
-4.2
-4
-2.8
-2.4
-3.4
-6.8
0,5
5
0.05
-
0 0.05
0.10
10
0.05
-
0 0.05
0.15
15
0.05
-
0 0.05 V
0,5
5
4.95
4.95
5
-
-
0,10
10
9.95
9.95
10
-
0,15
15
14.95
14.95
15
-
0.5,4.5
-
5
1.5
-
-
5·
1,9
-
10
3
-
15
4
0.5,4.5
-
5
3.5
3.5
-
1,9
-
10
7
7
15
11
11
-
0,18
18
1.5,13.5
-
±0.1
±1
±0.1
-
±1
92CS-29972
Fig. 10- Dynamic power dissipation test
circuit.
1.5
1.5,13.5
-
Voo
m~
-2
3
4
V
-
INPUTS
o
"ss
±10-5 ±0.1 IlA
Fig_ 11- Quiescent-device-current test circuit.
V~NM(J" ~..::~
Yss
VSS
TO 10TH Voo AND Yss'
CCWIIN[CT ALL UNUSED
N'lII'S TO EITHER
YDOORVSS'
TERMINAL ASSIGNMENT
INPUTOVDOOUTPUTS
=-
VIH
C'CEi'ii
~
l
Vil
V'S
..
NOTE:
TEST ANY COMBINA.TION
OF INPUTS
9ZCS-Z744IRI
Fig. 12- Input-current test circuit.
PI
P' •
P' •
V5SPE
CLOCK
5
I.
I'.
I'"
15
10
9
voo
CARRY OUT
01
o.
O.
O•
TO
LOAD
TOP VIEW
92CS-29459
Fig. 13- Input-voltage test circuit.
________________________________________
~--------------------411
CD40160B, CD40161B, CD40162B, CD40163B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA
Input t r• tt = 20 ns. CL = 50 pF. RL = 200 kn
TEST
CONDITIONS
CHARACTERISTIC
VDD(V)
CLOCK OPERATION
5
Propagation Delay Time. tpHL,tpLH
10
Clock to
15
a
Clock to COUT
5
10
15
TE to COUT
5
10
15
Minimum Setup Time,
Data to Clock
5
10
15
tsu
Load to Clock
5
10
15
PE to TE to Clock
5
10
15
tH
5
10
15
tTHL,tTLH
5
10
15
=25°C;
LIMITS
ALL TYPES"
Min.
Typ.
Max.
-
UNITS
200
80
60
400
160
120
ns
-
225
95
70
450
190
140
ns
125
55
40
250
110
80
ns
120
45
30
240
90
60
ns
120
45
30
240
90
60
ns
170
70
50
340
140
100
ns
-
-
0
0
0
ns
100
50
40
200
100
80
ns
85
35
25
170
70
50
ns
-
Minimum Clock Pulse Width,
tw
5
10
15
-
Maximum Clock Frequency,
tCL
5
10
15
2
5.5
8
3
8.5
12
-
5
10
15
200
70
15
-
-
-
5
10
15
-
250
110
80
500
220
Minimum Setup Time,
tsu
(CD40162B, CD40163B)
Clear to Clock
5
10
15
-
170
70
50
340
140
100
ns
Minimum Hold Time,
tH
(CD40162B,CD40163B)
Clear to Clock
5
10
15
0
0
0
ns
Minimum Clear Removal Time, t rem
(CD40160B, CD40161B)
5
10
15
100
50
35
200
100
70
ns
Minimum Clear Pulse Width,
(CD40160B, CD40161B)
5
10
15
85
35
25
170
70
50
ns
Minimum Hold Time,
Transition Time,
Maximum Clock Rise or Fall Time,t
trCL, ttCL
CLEAR OPERATION
Propagation Delay Time,
tpHL
(CD40160B, CD40161B)
Clear to
a
..
tWL
-
-
-
-
-
-
-
MHz
-
lis
ns
ISO
412 ____________~----------------------------~------------------------
CD40160B, CD40161B, CD40162B, CD40163B Types
CLEAR(CD401608)~r.A::S:::YN::C::HR::O::NO""U::S-----------'----
--
1
CLEAR(CD401628)~r;S;;;YN",C,"H;;RO"'N;nou;;;s;---------------LOAD
~
OATA
'NPUTS
:
U
i
P'-.J
p2-.Jr-~ir--L_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
p,-.JI""--;--""1------------_ _ _ _ __
Lp4---~:----------------------r---,
CLOCK(CD40160BJ
CLOCK(CD40162Bl
,-l:---------+----iL-
ENABLES {PE
OUTPUTS
{:====~"------~
:
Q'--- -~:---------l-I-----I
1
1
Q4----~----+_I-----
n
III
I
CARRY OUT
°
I
I.
17
9
1
o!--~__:,____,,:-il--------·I
I II-·O-----,CO::;cU·CN"'T;----.....-tI.-..·-·-----:-:'N""H:::'B""T:-----I
..
CLEAR PRESET
92CL-29228RI
Fig. 14- Timing diagram for (:D40160B. CD4d162B.
C'U'AR (CD4016IBI--urA"'S;V;YN"'C"'HR"'O"'Nn.OU""S---,---------------
--
Ir.~~~".----------------
CLEA.R~CD40163BJ~ SYNCHRONOUS
LmIo
1
------f-,l-jl""------------------
"" J:-----i-----
'NPUTS
p,-.J
l'
N~r-~-~~___________________________
C'LOCI«CD40161
Bl------......,
CLOCK( CD4D 163 8)
I~~_ _ _ _- - ,
II
PE
ENABLES
'--__--'
1,..--:---------1--------,
{
OUTPUTS{:':=
=~--t.--""'i---'~ i
Q'----r~
1
i--+I- - - - - ,
Q4 -- -- _I--.J
CARRY OUT
1
'------+1-------------
1
rI
1
1
1
I
I
,..1·O-----,C-:-O-::UN:::T,-------I....
----tI-;;--r.I,.2-;;1,;;,-.,,44---to,.
CLEAR PRESET
'-----
,
1
.!-O--,---,2,-11---------.
j
I··-----:'."NHc:-'.:::'=-T--~
92CL-29229RI
Fig. 15- Timing diagram forCD40161B, CD40163B.
413
CD40160B, CD40161 B, CD40162B, CD40163B Types
f
0
CUt
10
20
30
40
50
60
70
BO
90
100
10.
B3
BO
CL
70
cc
60
50
CL
CL
40
30
ON
20
10
92.CM-29226
Fig. 16- Detail of flip·flops of CD401608 and CD401618 (asynchronous clear).
t:,
92CIII-29968
yC~
Dimensions and pad layout for CD40160BH. Dimensions and pad layout
for CD40161 BH,CD40162BH, and CD40163BH are identical.
Dimensions in parentheses are in millimeters and
are derived from the basic inch dimensions as in-
dicated. Grid graduations are in mils (10- 3 inch/.
The photographs and dimensions of each' CDS/MOS
chip represent a chip when it is part of the wafer.
When the w~f~r is cut ;nt~ Ch~ps. the cleavage
angles are 57 Instead of 90 with respect to the
face of the chip. Therefore, the isolated chip is
actuallv 7 mils (0. 17 mm) larger in both dimensions.
Fig. 17- Detail of flip·flops for CD401628 and CD401638 (synchronous clear).
LOAD------~~----------------~r_----------------~r_--------~.
ClOCK----~_i----------------~_i----------------~~----------~~
CiE'A'R
92CM-29969
Fig. 18 - Cascaded counter packages in the parallel-clocked mode.
~AO------~------------------~------------------~----------~
VOO
CLOCK
~------~------------------~-------------------+----------~
92CM-29970
Fig. 19 - Cascaded counter packages in the ripple-clocked mode.
414 _______________________________________________________________________
CD40174B Types
COS/MOS Hex 'D'-Type
Flip-Flop
High-Voltage Types !20-Volt Rating)
The RCA-C040174B consists of six identical
'O'-type flip-flops having independent DATA
inputs_ The CLOCK and CLEAR inputs are
common to all six units_ Data is transferred
to the Q outputs on the positive-going
transition of the clock pulse_ All six flip-flops
are simultaneously reset by a low level on
the CLEAR input_
The C040174B types are supplied in 16lead hermetic dual-in-line ceramic packages
(0 and F suffixes). 16-lead dual-in~line
plastic packages (E suffix). 16-lead ceramic
flat packages (K suffix). and in chip form (H
suffix).
Features:
• 5-V, 10-V, and 15-V parametric rating
• Standardized symmetrical output
characteristics
• 100% tested for quiescent CUffent at 20 V
• Maximum input current of llJ-A at 18 V
over full package-teml!erature range;
100nAat 18Vand25 C
• Noise margin (over full package-temperature
range):! lVatVDD= 5V
2 V at VDD = 10 V
2.5VatVDD=15V
• Meets all requirements of JEDEC Tentative
Standard No. 13A, "Standard Specifications
for Description of 'B' Series CMOS Devices"
MAXIMUM RATINGS,Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (VDDI
(Voltages referenced to VSS TerminaU
. • -0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS
-0.5 to V DD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT
±10mA
POWER DISSIPATION PoER PACKAGE (POl:
For T A = -40 to +60 C (PACKAGE TYPE E)
......•. _
500mW
For T A = +60 to +85°C (PACKAGE TYPE E) _ _
Derate Linearly at 12 mwtC to 200 mW
For T A = -55 to +100oC (PACKAGE TYPES 0, F)
. . • . . . . ..
500mW
For TA = +100 to +125°C (PACKAGE TYPES 0, F)
Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types)
100mW
OPERATING-TEMPERATURE RANGE (T A):
PACKAGE TYPES 0, F, H
_ _ _ _ _ _
-55 to +125:C
PACKAGE TYPE E
-40 to +85 C
STORAGE TEMPERATURE RANGE (TS!)
_ _
-65 to +150oC
LEAD TEMPERATURE (DURING SOLD~RING):
At distance 1116 ± 1132 inch (1.59 ± 0.79 mm) from case for 10 s max.
D~ 13
06 14
-I1---''-l''':':';',.:...J
CLOCIC--<-'
CCEiR~'---<>--_-'
vss-a
vOO"r6
FUNCTIONAL DIAGRAM
Applications:
• Shift Registers
• Buffer/Storage Registers
• Pattern Generators
TRUTH TABLE FOR 1 OF 6 FLIP-FLOPS
CLOCK
INPUTS
DATA
CLEAR
Q
~
0
1
0
~
1
1
1
~
X
1
NC
X
0
0
X
1 = High Level
0= Low Level
OUTPUT
X = Don't Care
NC = No Change
E:
~s
"AlL INPUTS CTERMS 1,3,4,6,9,
'1.13,141 PROTECTED BY COS/MOS
PROTECTION NETWORK
cc
CLK·~CL
Fig. 1 - Logic diagram (1 of 6 flip-flops).
Fig. 2- Typical transition time as a function
of load capacitance.
------------------------------------------~------------------------------
415
CD40174B Types
RECOMMENDED OPERATING CONDITIONS at T A = 25°C, Except as Noted.
For maximum reliability, nominal operating conditions should be selected so that operation is
always within the following ranges:
CHARACTERISTIC
IV)
Supply·Voltage Range (For T A = Full Package·
Temperature Range)
LIMITS
VDD
Min.
-
3
18
15
40
20
10
Data Hold Time, tH
5
10
15
80
40
30
-
-
Clock Input Frequency, tCl
5
10
15
Clock Input Rise or Fall Time, trCl,'ttCl
5
Data Setup Time, tsu
10
UNITS
Max.
V
ns
I
DRAIN~TO-SOURCE VOLTAGE
ns
characteristics.
dc
3.5
6
8
MHz
5
10
15
-
15
15
15
/.IS
Clock Input Pulse Width, tWl' tWH
5
10
15
130
60
40
Clear Pulse Width, tWl
5
10
15
100
50
40
5
10
15
0
0
0
-
Clear Removal Time, tREM
IVos}-V
Fig. 3- Typical output low (sink) current
ns
ns
I
DRA'N-leo-"DU"CE VOlTAGE IVos)-V
ns
Fig. 4- Minimum output low (sink) current
characteristics.
ORAIN-TO-SOURCE VOLTAGE (Vosl-V
I
Fig~
"2CS-Z"~20113
5- Typical output high (source) current
characteristics.
~RAIN-TO-SOURCE VOLTAGE
(Vos)-V
92CS-2ge3~
Dimensions and pad layout for CD40T 74BH.
Dimensions in parentheses are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduBtions are in mils (10- 3 inch).
The.photographs and dimensions of each COS/MOS
chip represent a chip when it ;s part of the wafer.
When the wafer is cut into chips, the cleavage
angles are 57° instead of 90° with respect to ·the
face of the ehip. Therefore, the isolated chip ;s
actuallv 7 mils (0. 17 mm} larger in both dimensions.
"ZCS-24~21112
Fig. 6- Minimum output high (source) cu"ent
characteristics.
416 __________________________________________________________________
CD40174B Types
STATIC ELECTRICAL CHARACTERISTICS
Vo
(V)
LIMITS AT INDICATED TEMPERATURES ('C)
U
Values at -55,+25, +125 Apply to D, F, H Packages N
Values at -40, +25, +85 Apply to E Package
I
+25
T
VIN VDD
(VI (VI -55 -40
+125 Min.
+85
Typ.
Max. S
-
0,5
0,10
0,15
0,20
Output Low
(Sink)
Current
IOL Min.
0.4
0.5
1.5
0,5
0,10
0,15
5
10
15
1
2.6
6.8
-
Output High
(Source)
Current,
IOH Min.
4.6
2.5
9.5
13.5
0,5
0,5
0,10
0,15
5 -0.64 -0.61 -0.42 -0.36 -0.51
-1
-2 -1.8 -1.3 -1.15 -1.6 -3.2
5·
10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6
-4 -2.8 -2.4 -3.4 -6.8
15 -4.2
-
-
5
10
15
0.05
0.05
0.05
-
0
-
0,5
0,10
0,15
-
0,5
0,10
0,15
5
10
15
4.95
9.95
14.95
4.95
9.95
14.95'
5
10
15
-
-
1.5
3
4
-
-
1.5
3
4
3.5
7
11
3.5
7
11
CONDITIONS
CHARAC·
TERISTIC
Quiescent
Device
Current, IDO
Max.
Output Voltage:
Low-Level,
VOL Max.
Output Voltage:
High-Level,
VOH Min.
5
10
15
20
Input Low
Voltage,
VILMax.
0.5,4.5
1,9
1.5,13.5
-
5
10
15
Input High
Voltage,
VIHMin.
0.5,4.5
1,9
1.5,13.5
-
5
10
15
0,18
18
1
2
4
20
1
2
4
20
120
600
30
60
120
600
0.64
1.6
4.2
0.61
1.5
4
0.42
1.1
2.8
0.36
0.9
2.4
30
60 -
0.51
1.3
3.4
0.02
0.02
0.02
0.04
0
-
-
-
1
2 p.A
4
20
0.05
0.05
0.05
I
4 68 10
2
4 68102 2
.. 68103
2
4 68'04
CLOCK INPUT FREQUENCY UCLI-kHI
Fig. 7- Typical dynamic power dissipation a~ a
function of CLOCK frequency.
mA
V
-
LOAO CAPACITANCE 1c".I-pF
-
Fig.
8- Typic.1 propagation 'delay time (CLOCK
to OUTPUT) a. a function of load
capacitance.
V
PULSE
GEN. 2
Input Current
'IN Max.
2
-
±0.1
±0.1
±1
±1
-
±10-5 ±0.1 p.A
-=- Vss
NOTE: PULSE GEN. I • 'IN
PULSE
Fig.
_ _ _ _ _ _ _ 10%
9-
GEN.2.~
Dynamic power dissipation test circuit.-
.
INPUTS
Vss
*(LHI OR (HLI OPTIONAL
Vco
CCEAR-
-501'-
o
92CS-20069R4
Fig. 10- Definition of .etup, hold, propagation delay,
and removal times.
Fig. 11 - Quiescent device current test circuit.
417
CD40174B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25'C;
Input t r• tf = 20 ns. CL = 50 pF. RL-... 200 kn
TEST
CONDITIONS
VDD(V)
CHARACTERISTIC
Clear to Output.
Transition Time.
Clear,
n'
100
50
40
200
100
80
ns
100
50
40
200
100
80
ns
-
65
30
20
130
60
40
ns
50
25
20
100
50
40
ns
-
20
10
0
40
20
10
n.
-
40
20
15
80
40
30
ns
5
10
15
3.5
6
8
7
12
16
-
5
10
15
15
15
15
-
-
-
tsu
5
10
15
Minimum Data Hold Time,
tH
5
10
15
SEQUENTIALLY,
TO BOTH Voo AND Vss'
-
-
-
5
10
15
-
'NPUTQVOO
OUTPUTS
~
'-
:r
YI~
CONNECT ALL UftUSEO
Vss
-
MHz
-
-
fJS
25
40
pF
5
7.5
-40
-15
-10
0
0
0
-
ns
TERMINAL ASSIGNMENT
V'H
INPUTS TO EITHER
YDO ORVSS '
Vss
-
-
Minimum Clear Removal
Time,
tREM
MEASURE INPUTS
-
5
10
15
tWl
Minimum Data Setup Time,
1NPUOS
Voo
NOTE'
-
5
10
15
All other
o ~
300
140
100
5
10
15
Input Capacitance, CIN
Clear
Vss
150
70
50
tTHl' tTlH
Maximum Clock Rise or Fall
Time, trCl, tfCl
~
-
5
10
15
Maximum Clock -Frequency. fCl
Voo
Max.
tpHL
Minimum Pulse Width.
Clock.
tWl, tWH
UNITS
Typ.
5
10
15
Propagation Delay Time
Clock to Output.
tpHL' tpLH
LIMITS
Min.
NOTE:
TEST ANY COMBINATION
Of'INPUTS
92CS-2T44IR(
,.,S
CCEifi
0'
0'
02
02
"13
D.
03
V5S
VDD
os
os
D.
12
Q'
"
Q4
10
D'
CUlCK
TOP VIEW
Fig. 12 - Input cu"ent test circuit.
Fig. 13 - Input voltage test circuit.
418 ____________________________________________________________________
CD401818 Types
COS/MaS 4-Bit
Arithmetic Logic Unit
High-Voltage Types (20-Volt Rating)
The RCA-CD401818 is a low-power four-bit
parallel arithmetic logic unit (ALU) capable
of providing 16 binary arithmetic operations
on two four-bit words and 16 logical functions of two Boolean variables. The mode
control input M selects logical (M = High I or
arithmetic (M = Low) operation. The four
select inputs (SO, 51, 52, and 53) select the
desired logical or arithmetic functibns,
which include AND, OR, NAND, NOR, and
exclusive-OR and-NOR in the logic mode,
and addition, subtraction, decrement, leftshift and straight transfer in the arithmetic
mode, according to the truth table. The
CD40181B operation may be interpreted
with either active-low or active·h igh data at
the A and B word inputs and the function
outputs F, by using the appropriate truth
table.
The CD40181B contains logic f.or full lookahead carry operation for fast carry generation using the carry·generate and carrypropagate outputs G and P for the four bits
of the CD40181B. Use of the CD40182B
look-ahead carry generator in conjunction
with multiple CD40181B'S permits highspeed arithmetic operations on long words.
A ripple carry output C n+4 is available for
use in systems where speed i~ not of primary
importance.
Also included in the CD40181B is a com·
parator output A = B, wh ich assumes a high
level whenever the two four-bit input words
A and B are equal and the device is in tile
subtract mode. In addition, relative magnitude information may be derived from the
carry-in input C n and ripple carry-out output Cn +4 by placing the unit in the subtract
mode and externally decoding using the
information in Table III.
The C040181.B types are supplied in 24lead hermetic ceramic dual-in-line packages (0 and F suffixes). 24-lead dual-in-line
plastic packages (E suffix). 24-lead ceramic
flat packages (K suffix). and in chip form (H
suffix).
Features:
•
•
•
•
•
•
•
•
Full look-ahead carry for speed operations on long words
Generates 16 logic functions of two Boolean variables
Generates 16 arithmetic functions of two 4·bit binary words
A = B comparator output available
Ripple-carry input and output available
Typical addition time 200 ns @ VDD = 10 V
Standardized, symmetrical output characteristics
100% tested for quiescent current at 20 V
• Maximum input current of 1 IlA at 18 V
over full package temperature range;
100 nA at 18 Vand 250 C
• Noise margin (full package temperature range)
= 1 Vat VDD = 5 V
=2VatVDD=10V
= 2.5 Vat VDD = 15V
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative
Standard No. 13A, "Standard Specifications
for Description of 'B' Series CMOS Devices"
t~
"'ODE
III
VOO'24
VSS"l!
(Activ..low datal
FUNCTIONAL OIAGRAM
1",
Applications:
WOfI0
A
• Parallel arithmetic units
• Process controllers
• Low-power minicomputers
AI
A2
ro}
FI
F2
23
21
OUTPUT
FUNCTION
"
A319
'O ,
{ BIB22022
WOAD
B
8318
CARRYINCn
1
MODE
M
CONTROL
8
"
15
'}
P
COO,
:~~~
OIlTPUTS
(Active-high data)
FUNCTIONAL DIAGRAM
MAXIMUM RAT. NGS, Absolure·Maximum Values:
OC SUPPLY·VOLTAGE RANGE. (VDD)
-0.5 to +20 V
{Voltages referenced to VSS Terminal}
-0.5 to VOD +0.5 V
INPUT VOLTAGE RANGE. ALL INPUTS
±10mA
DC INPUT CURRENT. ANY ONE INPUT
POWER DISSIPATION PER PACKAGE (PO):
. • . • . . • .•
500mW
For T A = -40 to +60o C (PACKAGE TYPE E)
Derate Linearly at 12 mW/oC to 200 mW
For T A = +60 to +850 C (PACKAGE TYPE EI
.
.
•.....
500mW
For TA ~ -55 to +1000 C (PACKAGE TYPES D) .
Derate Linearly at 12 mW/oC to 200 mW
For TA = +100 to +125 0 C (PACKAGE TYPES 0:)
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
100mW
FOR TA = FULL PACKAGE·TEMPERATURE RANGE (All Package Types)
OPERATING·TEMPERATUR.E RANGE ITA):
-55
to
+1250 C
PACKAGE TYPES D. F. H
-40 to +85 0 C
PACKAGE TYPE E .
-65 to +1500 C
STORAGE TEMPERATURE RANGE (TSlg )
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1116 ± 1/32 inch (1.59 ±O.79 mml from case for 10 s max.
The C040181 is similar to industry types
MC14581 and 74181.
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating
conditions should be selected so that
operation is always within the following ranges'
LIMITS UNITS
CHARACTERISTIC
Min. Max.
Supply· Voltage Range
(For T A=Full Package·
V
3
18
Temperature Range)
CARRY .'-1
CONT/tOL
11
I~
II
,
DRAIN-TO-SOURCE VOLTAGE IVosJ-V
Fig. 7 - Typical output low (sink)
current characteristics.
II
"".i'N-TO-SOUR", \'Ol.TAGE ICVDSJ-V
Fig. 2 - Minimum output low (sin;;s-~.31~RI
current Characteristics.
__________________________________________________________________ 419
CD40181 B Types
'I
~
.00 1.·.lENT 'MPERATUR,
I!
~ 400
20
LOAD CAPACITANCE ICLI-PF
Fig. 6 - Typical propagation delay time as a
function of load capacitance (for A
or B to F, logic mode).
Fig. 7 - Typical transition time as a function
: ·-----l:::>o--.....
..
I,::>O~----.JI.ALL INPUTS PROTECTED
*Cit 7
of load capacitance.
IY COSIMOS PROTECTION
NETWORK
Fig_
3-
CD407878 logic diagram (acriv&-/ow daral_
DRAIN-TO-SOURCE VOLTA.GE IVpsI-V
_"
_,n
I~~~',',•.', ,','~,'."u.,
I
II AMtNENT TEMPERATURE
ITAI·~·C
DRAIN-TO-SOURCE 'IOLTAGE IVDsl-V
-..
-10
'!E,",T :,',~,",~~.'
2:
2:
468
10
I
468
102
2468
2:
488
103
2:
48a
104
10'
INPUT FREQUENCY I 'IN 1- kHz
nts-I,,_
Fig. 8 - Typical dynamic dissipation as a function
of input frequency (see Fig. 11 - dynamic
power dissipat;on test circuit).
INPuTS , - ' - - - - ,
o
Vss
Fig. 4 - Typical output high (sourc;r-ZH20R'
current characteristics.
Fig. 5 - Minimum output high (source)
current characteristics.
Fig. 9 - Ou;escent-device-current test circuit.
420 _____________________________________________________________
CD40181 B Types
STATIC ELECTRICAL CHARACTERISTICS
LIMITS AT INDICATED TEMPERATURES (OC)
Vllull 11-55, +25, +125 Apply 10 0, f ,H PoCU"'"
Vllull II -40, +25, +85 Apply 10 E POCU ...
CONDITIONS
CHARACTER,
ISTIC
Vo
(V)
Quiescent Device
Current,
100 Max.
-
Output low
(Sink) Current
IOlMin.
0.4
0.5
1.5
4.6
2.5
9.5
13.5
Output High
(Source)
Current,
IOH Min.
Output Voltage:
low·level,
VOL Max.
-
Output Voltage:
High·level,
VOH Min.
-
-
-
Input low
Voltage,
Vil Max.
0.5,4.5
1,9
1.5,13.5
0.5,4.5
1,9
1.5,13.5
Input High
Voltage,
VIH Min.
Input Current
-
liN Max.
VIN VDD
(V)
(V)
D,S
0,10
0,15
0,20
D,S
0,10
0,15
D,S
D,S
0,10
0,15
D,S
0.51
1.3
34
-0.51
-1.6
-1.3
-3.4
1
2.6
6.8
-1
-3.2
-2.6
-6.8
-
Min.
5
10
15
20
5
10
20
100
5
10
20
100
150
300
600
3000
150
300
600
3000
-
5
10
15
5
5
10
15
5
0.64
1.6
4.2
-0.64
-2
-1.6
-4.2
0.61
1.5
4
-0.61
-1.8
-1.5
-4
0.42
1.1
2.8
-0.42
-1.3
0.36
0.9
2.4'
-0.36
-1.15
-0.9
-2.4
-1.1
-2.8
-
1.5
3
4
3.5
7
11
0,18
18
-
5
10
20
100
+125
5
10
15
5
10
15
0,10
0,15
-
-
0.04
0.04
0.04
0.08
+85
0.05
0.05
0.05
4.95
9.95
14.95
D,S
Mox.
~o
10
15
5
10
15
0,10
0,15
+25
Typ,
-55
±0.1
±0.1
-
-
±1
±1
HOTE:
CHARACTERISTIC
Propagation Delay Time: tpH L, tpLH
A or B to F (logic model,
A or 8 to G or P,
A or B to F, C n +4, or A = B,
Cnto F
Cn to Cn +4
~srNA,Nu~~CIM.INATION
Vss
I'A
Fig. 10 - Input-voltage test circuit.
rnA
0.05
-
-
-
-
-
-
1.5
3
4
-
V
-
-
-
-
±10- 5
±0.1
TEST CONDITIONS:
AD,AI, 42,43. SO, 53, M,en '" V OD
80,91,82,83-'IN
SI,52- VSS
V
(ALL OUTPUTS SWITCHING EXCEPT G I
Fig. 11 - Dynamic power dissipation test circuit.
I'A
Voo
DYNAMIC ELECTRICAL CHARACTERISTICS at T A =
Cl = 50 pF, Rl = 200 k.l1
J;
-
0.05
0.05
-
~
Y~
-
-
0
3.5
7
11
--...
V,H
-
0
0
5
10
15
4.95
9.95
14.95
,.purOVDOOUTPUTS
UNITS
1NPOUS
Voo
NOT'
~
MEASURE INPUTS
o
SEOUENTIAL..LV,
TO 80TH Vco ANDVss
~
Vss
250
C; Input t r , tf = 20 ns,
CONNECT ALL UNUSED
INPUTS TO EITHER
Voo OR Vss
VSS
LIMITS
UNITS
VDD
(VI
Typ.
5
10
15
400
160
120
800
320
240
ns
5
10
15
500
200
140
1000
400
280
ns
5
10
15
5
10
15
Transition Time: tTHL, tTlH
5
10
15
Input Capacitance, CIN (Any Inputl
-
320
135
100
200
100
70
Fig. 12 - Input current test circuit.
Max.
640
270
200
400
200
140
liD
Aii
2.
2'
22
53
ns
S2
SI
SO
Cn
M
ns
To
Fi
F2
VSS
100
50
40
200
100
80
ns
5
7.5
pF
21
20
19
18
17
ii2
ii3
i5
G
I.
'0
"12
VDD
Ai
iii
A2
,.
Cn+4
'5
P
I'
F3
A=8
92CS-27708
Top View
Terminal Assignment'
(Active-low Data)
421
CD40181 B Types
TABLE I
TRUTH TABLE
FUNCTION
SELECT
S3 S2 S1 SO
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
o
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
LOGIC
FUNCTION·
M=H
A
AB
A+B
Logic 1
~
B
A(±)!
A+B
AB
AG;)B
B
A + B
logic 0
AS
AB
A
INPUTStOUTPUT ACTIVE LOW
ARITHMETIC· FUNCTION
M=L
~-H
L
A minus 1
A
AB
ABminus 1
ABmlnus 1
As
minus 1
Zero
A plus (A +B) plus 1
A plus (A + Bi
AB plus (A +
AB plus (A + ""9) plus 1
A minus B minus 1
A minus B
(A + B) plus 1
A+B
A plus (A + B)
A plus (A + B) plus 1
A plus B
A plus B plus 1
AB plus (A + B)
AB plus (A + B) plus 1
A + B plus 1
A +B
A plus A
A plus A plus 1
A!!, plus A plus 1
A.!! plus A
ABplus A
AB plus A plus 1
A
A plus 1
en -
Bi
INPUTS/OUTPUTS ACTIVE HIGH
FUNCTION
SELECT
S3 S2 S1 SO
0
0
0
0
0
0
0
1
0
1
0
0
0
0
1
1
1
0
0
0
1
0
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
1
0
0
0
1
1
1
1
1
0
0
1 1 0
1
1
1
1
0
1
1
1
1
LOGIC
FUNCTION
M=H
A
A+B
AB
Logic 0
AS
B
A(t)B
AS
A+B
A(t)B
B
AB
LogiCL!
A+B
A+B
A
• Expressed as two's complement.
ARITHMETIC· FUNCTION
M= L
Cn - L
Cn - H
A
A plus 1
A+B
(A + .!!l plus 1
A+B
(A + B) plus 1
minus 1
Zero
A plus Alr
A plus AS plus 1
(A + B) plus AS
(A + B) plus AS plus 1
A minus B minus 1
A minus B
AS
ABminus 1
A plus AB
A plus AB plus 1
A plus B
A plus B plus 1
(A + B) plus AB
(A + tI) plus AB plus 1
ABmlnus 1
AB
Aplus A
A plus A plus 1
(A + B) plus A
(A + B) plus A plus 1
(A + B) plus A
(A + S) plus A plus 1
A minus 1
A
1 = HIGH LEVEL
Dimensions and pad layout for CD40 181 BH.
Dimensions in parentheses are in millimeters and
are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10- 3 inch).
The photographs and dimensions of each COS/MOS
chip represent a chip when it is part of the wafer.
Kflen the wafer;s cutintochips, the cleavage angles
are 570 instead of 9oo with respect to the facB of
the chip. Therefore, the isolated chip is actually
7 mils (0. 17 mm) (arger in both dimensions.
0= LOW LEVEL
422 _______________________________________________________________
CD40181 B Types
TABLE II
AC TEST SETUP REFERENCE (ACTIVE-LOW DATA)
TEST
DELAY TIMES
AC PATHS
INPUTS
DC DATA INPUTS
OUTPUTS
TOVSS
TOVDD
MODE*
SUMIN to SUMOUT
BO
Any F
Bl, B2, B3,
M,Cn
All A's
ADD
SUMIN to P
AO
P
Al,A2,A3,
M, Cn
All B's
ADD
SUMIN to G
BO
G
All A's
M,Cn
Bl,B2,B3
ADD
SUMIN to Cn+4
BO
Cn+4
AliA's,
M,C n
Bl, B2, B3
ADD
Cn toSUMOUT
Cn
Any F
AliA's,
M
All B's
ADD
Cn to Cn+4
Cn
Cn+4
All A's,
M
Alli'i's
ADD
SUMIN to A= B
BO
A=B
All A's,
Bl, B2, B3,
M
Cn
SUBTRACT
Any F
AliA's,
Cn
M
EXCLUSIVE
OR
All B's
SUMIN to SUMOUT
(Logic Model
• ADD Mode: 50,53 = VOO: 51, 52
= V 55 .
5UBTRACT Mode: SO, 53 = VSS: 51, 52
= VOO'
TABLE III
MAGNITUDE COMPARISON
ACTIVE - HIGH DATA
INPUT OUTPUT
Cn
Cn+4
1
1
MAGNITUDE
ACTIVE - LOW DATA
INPUT OUTPUT
Cn
Cn +4
MAGNITUDE
A";;B
0
0
A";;B
AB
0
1
A>B
0
0
A;;;'B
1
1
A;;;'B
1 = HIGH LEVEL
0= LOW LEVEL
423
CD40182B Types
COS/MOS Look-Ahead
Carry Generator
High-Voltage Types (20-Volt Rating)
The, RCA-C040182B is a high-speed lookahead carry generato; capable of anticipating
a carry across four binary adders or groups
of adders. The CD40182B is cascadable to
perform full look·ahead across n-bit adders,
Carry, propagate-carry, and generate·carry
functions are provided as enumerated in the
terminal designation below.
The C040182B, when used in conjunction
with the C040181 B arithmetic logic unit
(ALU), provides full high·speed look-ahead
carry capability for up to n-bit words. Each
C0401828 generates the look-ahead (anticipated carry) across a group of four ALU's.
In addition, otherCD40182B's may be employed to anticipate the carry across sections
of four look-ahead blocks up to n-bits. Carry
inputs and outputs of the C040181 8 are
active-high logic, and carry-generate (G) and
carry-propagate (P) outputs are active-low.
Therefore the inputs and outputs of the
C0401828 are compatible.
Features:
.-{..-., .
.
~
• Generates high-speed carry' across four adders
or adder groups'
• High-speed operations: '
tpHL = tpLH = 100 ns (typ.) @ VDD = 10 V
• Cascadable for fast carries over N bits
• Designed for use with CD40181B ALU
• 100% tested for quiescent current at 20 V
• 5-V. lo-V. and 15-V parametric ratings
.2
-
12
'n+"
Cn+Y
Ii! •
Cn+Z
{ .2PI
P1
10
YDO l 16
• Standardized. symmetrical output
characteristics
• Maximum input current of 1 p.A at 18 V
over full package-temperature range; 100
nA at 18 V and 25°C
• Noise margin (full package-temperature
lVatVDD=5V
range) =
2VatVDO=10V
2.5VatVDD=15V
• Meets all requirements of JEDEC Tentative Standard No. 13A, "Standard
Specifications for Description of 'B'
Series CMOS Devices"
vss-,
92CS·:?4826A,
FUNCTIONAL DIAGRAM
In
Pi
..
I·
GO
1'll
n
,..
1'1
,.
•
"
•
voo
Pz
iZ
c.
12
C,.+_
10
ent ,
G
Cn• r
VSS
TOP VIEW
Applications:
• High·speed parallel arithmetic units
• Multi-level look-ahead carry generation for
long word lengths
'J2CSI1&l4
TERMINAL ASSIGNMENT
The C040182B types are supplied in 16lead hermetic dual-in-line ceramic packages (0 and Fsuffixes), 16-leaddual-in-line
plastic packages (E suffix), 16-lead ceramic
flat packages (K suffix), and in chip form (H
suffix).
The C0401828 is similar to industry type
MC14582.
TERMINAL DESIGNATIONS
DESIGNATION
TERM.
GO,Gl,G2,G3 3,1,14,5
FUNCTION
Active-Low
Carry-Propagate
Inputs
--PO, PI, P2, P3
4,2,15,6
Cn
13
Cn+x,Cn+y •
Cn+ z
12.11,9
Active-H igh
Carry Outputs
10
Active-Low
Group
Carry-Generate
Output
7
Active·Low
Group
Carry-Propagate
Output
G
15
g
Active·Low
Carry-Generate
Inputs
* AU. INPUTS ARE
PROTECTED BY
Active-High
Carry Input
.
COSIMOS PROTECTION
,,(TWO"'"
OO
'Iss
Fig. 7 - C0407S28 logic diagram.
CD401828 Logic Equations:
Cn+x = GO + PO . C n
C n+y = Gl + PI ·GO + Pl· po. C n
C n+z = G2 + P2 . Gl + P2 ' PI . GO + P2 . PI . PO . C n
G = G3 + P3 . G2 + P3 . P2 . Gl
15 =153 • P2 . PI . PO
+ P3 . P2 . 151 . GO
424 ____________________________________________________________________
CD40182B Types
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges:
LIMITS
CHARACTERISTIC
MIN.
MAX.
3
18
Supply Voltage Range (For T A = Full
Package·Temperature Rangel
UNITS
V
MAXIMUM RATINGS, Absolute·Maximum Values:
DRAIN-TO-SOURCE VOLTAGE IVDS)-V
DC SUPPLY·VOLTAGE RANGE. (V DD )
0.5 to '20 V
(Voltages referenced to VSS Terminal)
0.5 to VDD '0.5 V
(NPUT VOLTAGE RANGE. ALL INPUTS
!10mA
DC INPUT CURRENT. ANY ONE INPUT
POWER DISSIPATION PER PACKAGE (PO):
.... ,
..
500mW
For T A = -401o +SOoC (PACKAGE TYPE E)
Derate LlIlcarly al 12 mW/oC to 200 mW
For TA = +60 to +85 0 C (PACKAGE TYPE E)
.
. , . . ..
.
500mW
For TA • -55 to +'OOoC (PACKAGE TYPES D.F)'
Derate Linearly at 12 mW/oC to 200 mW
For TA· +,00 to +'250 C (PACKAGE TYPES D. F I
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
100mW
FOR TA • FULL PACKAGE· TEMPERATURE RANGE (All Package Tvpe,)
OPERATING·TEMPERATURE RANGE (TAl:
5510 t12SoC
PACKAGE TYPES D. F. H
·40 to +85 0C
PACKAGE TYPE E .
65 to t 150°C
STORAGE TEMPERATURE RANGE ITstgl
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± D,79 mm) from case for 105 max.
Fig. 2 - Tvpical output low (sink)
current characteristics.
DRAIN-TO-SOURCE II'OLTAGE
Fig. 3 - Minimum output low (sink)
current characteristics.
STATIC ELECTRICAL CHARACTERISTICS
LIMITS AT INDICATED TEMPERATURES (OCI
Valu...t -55, +25, +125 Apply to D, F,H Package.
Value. at -40, +25, +85 Apply to E Package
CONDITIONS
CHARACTER·
ISTIC
Vo
-55
-40
+85
+125
Min.
Typ.
Max.
5
10
15
20
5
10
20
100
5
10
20
100
150
300
600
3000
150
300
600
3000
-
-
D,S
0,10
0,15
0,20
0.04
0.04
0.04
O.OB
5
10
20
100
0.4
0.5
1.5
4.6
2.5
9.5
13.5
D,S
0,10
0,15
0.5
D,S
0,10
0,15
5
10
15
5
5
10
15
0.64
1.6
4.2
-0.64
-2
-1.6
-4.2
0.61
1.5
4
-0.61
-1.B
-1.5
-4
0.42
1.1
2,B
-0.42
-1.3
-1.1
-2.B
0.36
0.9
2,4
-0.36
-1.15
-0.9
-2.4
1
2.6
-
M
Quiescent Device
Current,
100 Max.
Output low
(Sink) Current
IOlMin.
Output High
(Source)
Current,
IOH Min.
Output Voltage:
low·level.
VOL Max.
Output Voltage:
High·level.
VOH Min.
Input low
Voltage,
Vil Max.
Input High
Voltage,
VIH Min.
Input Current
liN Max.
VIN VDD
(V)
(V)
+25
-
-
-
0,5
5
-
0.10
0.15
D,S
0,10
0,15
10
15
5
10
15
0.5,4.5
-
1.9
1.5,13.5
0.5.4.5
1,9
-
5
10
15
5
10
15
1.5,13.5
-
-
0,18
lB
0.05
0.05
0.05
4.95
9.95
14.95
±0,1
0.51
1.3
34
-0.51
-1.6
-1.3
-3.4
-
-
0.05
0,05
0.05
-
-
1.5
3
4
-
3,5
7
7
11
11
-
-
DRAIN-TO-SOUACE VOLTAGf
IVosl-V
V
-
-
-
-
±IC- 5
±0.1
-
Fig. 4 - Typical output f,Jigh (source) .
current characteristics.
-
0
-
rnA
-
0
0
5
10
15
-
±1
-
-
-
±1
6.B
-1
-3.2
-2.6
-6.B
jJ.A
-
4.95
9.95
14.95
1.5
3
4
3.5
±0.1
-
DRAIN-TO-SOURCE VOLTAGE lVosI-V
UNITS
V
-
jJ.A
Fig. 5 - Minimum output high (source)
current characteristics.
425
CD40182B Types
DYNAMIC ELECTRICAL CHARACTERISTICS
At TA = 2rt>C; Input t" tf= 20ns, CL = 50pF, RL = 200kfl
LIMITS
VDD
CHARACTERISTIC
Propagation Delay Time:
,
tpHL' tpLH
P, G In to p. G Out and Carry Outs
Cn to Carry Outs
Transition Time: tTHL' tTLH
UNITS
(VI
Typ.
Max.
5
10
15
200
100
75
400
200
150
n,
5
10
15
240
120
90
480
240
180
ns
5
10
15
100
50
40
200
100
80
ns
5
7.5
pF
-
Input Cap,acitance CIN (Any Input)
Fig. 6 - Typical transition time
8S
a function of
load capacitance.
0",.,.
CL-!50pFCL-'!lpf' - - -
'I ill I
I
2
.
2
"" '102 I
... 1110 3 Z
. . . ..,.
INPUT FREQUENCY CFI)- .HI
Fig. 7 - Typical propagation delay time as a function
of load capacitance (P, G In to P. GOut
and Carry·Outs).
".'10
Fig. 8 - Typical power dissipation
input frequency_
INPUTS
Fig. 9 - Power dissipation test circuit.
as a function of
'OPUTQVeoOUTPUTS
V55
V'H
Voo
~
""----
v~
~
1NPUOS
Veo OOTE'
?0-
~~:~~:;I~~~~~S
Vss
TO BOTH Voo ANDYss'
CONNECT ALL UNUSED
NOTE:
00
Vss
INPUTS 10 EITHER
~SYN..,'t,~gCIMaINATION
Voo DRVss '
Vss
9lCS-274041RI
V55
Fig. 10 - Quiescent device current test circuit.
Fig. 12 -Input current test circuit.
Fig. " - Input voltage test circuit.
Applications
OUT
CARRY
!
LOOK-AHEAD
OUTPUTS
92CS-276Z6RI
Fig. 13 - 16-8i' 'wo-Ievellook-ahead ALU,
426 ______________________________________________________________
~--
CD40182B Types
Fig. '4 - 64·Bit full carry look ..head AI. U in 3 I••eli.
Fig. 15 - Combined rwo-Ievellook-ahead and ripple-carry ALU.
DIMENSIONS AND PAD LAYOUT FOR CD40182BH
1 - - - - - - - ,•..:::.•111------....,
Dimensions in parentheses are in millimeters and
are derived from the basic inch dimensions as
indicl!ted. Grid graduations srein mils (10- 3 inch).
The photographs and dimensions of each COS/MOS
chip represent a chip when it ;s part of the wafer.
When the wafer is cut into chips, the cleavage
angles are 57° instead of 90° with respect to the
face of the chip. Therefore. the isolated chip is
actually 7 mils (0. 77 mm) larger in both dimensions.
427
CD40192B, CD40193B Types
COS/MOS Presettable
Up/Down Counters
(Dual Clock With Reset)
High-Voltage Types (20-Volt Rating)
CD40192 - BCD Type
CD40193 - Binary Type
The RCA-CD40192B Presettable BCD Up/
Down Counter and the CD40193B Presettable Binary Up/Down Counter each consist
of 4 synchronously clocked, gated "0" type
flip-flops connected as a counter. The inputs
consist of 4 individual iam lines, a PRESET
ENABLE control, individual CLOCK UP
and CLOCK DOWN signals and a master RESET. Four buffered Q signal outputs as well
as CARRY and BORROW outputs for multiple-stage counting schemes are provided.
The counter is cleared so that all outputs are in a low state by a high on the R ESET line. A RESET is accomplished asynchro·
nously with the clock. Each output is
individually programmable asynchronously
with the clock to the level on the cor·
responding iam input when the PRESET
ENABLE control is low.
Features:
• Individual clock lines for counting up or counting down
PiiE""Sfi
ENABLE
• Synchronous high-speed carry and borrow propagation
delays for cascading
JI 15
• Asynchronous reset and preset capability
• Medium-speed operation-fCL = 8 MHz (typ.) @10 V
• 01
J2 1
2 02
J3 10
•7 O.
04
J4 9
13 BORROW
12CA'iiRY
CLOCK UP ,
• 5-V, 10-V, and 15-V parametric ratings
• Standardized, symmetrical output
characteristics
.100% tested for quiescent current at 20 V
• Maximum input current of 1 JlA at 18 V
over full package temperature range; 100
nA at 18 V and 25°C
• Noise margin over full package temperature
range:
1 Vat VDD = 5 V
2 V at VDD = 10 V
2.5 Vat VDD = 15 V
• Meets all requirements of JEDEC Tentative
Standard No. 13A, "Standard Specifications
for Description of 'B' Series CMOS Devices"
CLOCK DOWN 4
14
RESET
CD40192B, CD40193B
FUNCTIONAL DIAGRAM
92CS·27561AI
J2
02
0'
CLOCk DOWN
CLOCK UP
o.
Applications:
•
•
•
•
•
04
V..
Up/down difference counting
Multistage ripple counting
Synchronous frequency dividers
A/D and 0/A conversion
Programmable binary or BCD counting
,.
2
,.
'5
'4
13
'2
The CD401928 and CD401938 types are
supplied in 16-lead hermetic dual-in-line
ceramic packages (0 and F suffixes), lSlead dual-in-line plastic packages (E suffix),
16-lead ceramic flat packages (K suffix),
and in chip form (H suffix).
nm
PRESET ENABLE
'0
9
J'
J4
TOP VIEW
CD40192B, CD40193B
TERMINAL ASSIGNMENT
RESET
The counter counts up one count on the
positive clock edge of the CLOCK Lip sig·
nal provided the CLOCK DOWN line is high.
The counter counts down one count on the
positive clock edge of the CLOCK DOWN
signal provided the CLOCK UP line is high.
The CARRY and BORROW signals are high
when the counter is counting up or down.
The CARRY signal goes low one·half clock
cycle after the counter reaches its maximum
count in the count-up mode. The BORROW
signal goes low one-half clock cycle after
the counterreaches its minimum count in the
count-down mode. Cascading of multiple pack·
ages is easily accomplished without the need
for additional external circuitry by tying the
BORROW and CARRY outputs to the
CLOCK DOWN and CLOCK UP inputs,
respectively, of the succeeding counter
package.
Voo
J'
RESET
R4
54
CONTROL LOGIC I
•
SAME AS CONTROL LOGic I
* COS/MOS
ALL INPUTS PROTECTED BY
PROTECTION NETWORK
Fig. 1 -
C040192B logic diagram. (BCD).
428 ____________________________________________________________________
CD40192B, CD40193B Types
RESET
CLR I -~
_0
PE , -I--
?
,-
JIO
J20
R4
54
,
J30
J4 ,
-
-
o
1 -~ ~
ClK
UP 0
•
CONTROL lOGIC I
SAME AS CONTROL LOGIC I
ClK
l-
1
ON O
,
I-,--
I---
0' 0
020 -I--
,
I--
030
,
Q40
CARRY 1
o
BORROW
,
o
COUNT-+
78901210987
3 - CD401928 timing diagram.
Fig.
*
0
All INPUTS PROTECTED BY
COS/MOS PROTECTION NETWORK
-~
Fig.
-,
2 - CD401938 logic diagram (binary).
J20
I
I
J40
,------------------,
I~
I
I +-V +
I
I
I
CI
Cl
Cl'
I
0
,
,
-
01 0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
IL __________________ J I
I
ilNO
I
I
CI
I
UPO
Cl'
-
I
I
,
,
BORROW 0
I-
'--
I--
lI--
I---
I--
I--
COUNT-+
Fig.
~
I--
5-
0
13
141:' 0 I
2
1 0
I~
14 13
CD401938 timing diagram.
Fig. 4 - Internal logic of Flip-flop.
TRUTH TABLE
CLOCK
UP
CLOCK
DOWN
PRESET
ENABLE
RESET
ACTION
~
1
1
0
~
1
1
0
NO COUNT
0
COUNTDOWN
COUNT UP
1
~
1
1
'X
1
0
NO COUNT
0
0
PRESET
X
1
RESET
X
X
X
,
ORAIN-TO-SOURCE VOLTAGE (Vos)-V
Fig.
1 = HIGH LEVEL
0= LOW LEVEL
X = DON'T CARE
6-
Typical output low (sink)
current characteristics.
______________________________________________________________________ 429
CD401928, CD401938 Types
MAXIMUM RATI NGS, Absolute·Maximum Values:
DC SUPPLY·VDLTAGE RANGE. (V DOl
-0.5 to +20 V
(Voltages referenced to VSS Terminal)
INPUT VOLTAGE RANGE, ALL INPUTS
-O.S to VDD +O.S V
±10mA
DC INPUT CURRENT, ANY ONE INPUT
POWER DISSIPATION PER PACKAGE IPDI,
.
.
.
..
SOOmW
For TA : -40 to +60 o C (PACKAGE TYPE EI
Derate Linearly at 12 mW/oC to 200 mW
For T A: +60 to +BSoC (PACKAGE TYPE EI
. . . . . . . ..
For T A: -SS to +'OOoC (PACKAGE TYPES D,F I
SOOmW
Derate Linearly at 12 mW/oC to 200 mW
For T A: +,00 to +' 25°C IPACKAGE TYPES 0, F I
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA : FULL PACKAGE·TEMPERATURE RANGE (All Package Typesl
'OOmW
OPERATING·TEMPERATURE RANGE IT A"
-55 to +12SoC
PACKAGE TYPES 0, F, H
-40 to +8SoC
PACKAGE TYPE E
-65 to +150o C
STORAGE TEMPERATURE RANGE ITstgl
LEAD TEMPERATURE (DURING SOLDERINGI,
AI distance 1/16 ± 1/32 inch (1.59 ± 0.79 mmJ from case for lOs max.
DRAIN-lO-SOURCE VOLTAGE (.....05)-'.'
Fig. 7 -
Minimum output low (sink)
current characteristics.
DRAIN-TO-SOURCE VOLTAGE (VOsJ-V
RECOMMENDED OPERATING CONDITIONS at T A
= 25°C (unless otherwise specified)
For maximum reliability, nominal operating conditions should be selected so that operation is
always within the following ranges.
CHARACTERISTIC
VDD
(V)
LIMITS
Min.
Removal Time:
RESET or PE
5
10
15
80
40
30
Pulse Width:
RESET
5
10
15
480
300
260
-
PE
5
10
15
240
170
140
-
CLOCK
5
10
15
180
90
60
Clock Input Frequency
5
10
15
DC
Clock Rise & Fall Time
5
10
15
-
GATE-TO-SOURCE VOLTAGE (VGS)'-5V
UNITS
-
-
-~
Max.
Supply Voltage Range (For T A = Full Temp. Range)
3
-10
18
V
-
-
ns
-
ns
Fig. 8 - Typical output high (source)
current characteristics.
92.S
1·120~3
ORAIN-TO-SOURCE VOLTAGE (VPsJ-V
ns
-
ns
2
4
5.5
15
15
5
MHz
flS
Fig. 9 - Minimum output high (source)
current characteristics.
UCs-t4)t'"l
r--1WH"""""·WL - . ,
I
I
I
CLOCI(
I
RESET
PRESET ENABLE
I
*c=:::;:I=:::;;:===
I
,
I
,
..
~t"m
*RESET OR -PRESET
ENABLE
REMOVAL liME
92(5 - 27562RI
Fig. 10 -
Timing diagram defining trem "
Fig. 11 - Typical transition time as a
function of load capacitance.
430 ______________________________________________________________
~----
CD40192B, CD40193B Types
STATIC ELECTRICAL CHARACTERISTICS
LIMITS AT INDICATED TEMPERATURES (OC)
Values at -55, +25, +125 Apply to D, F ,H Packages
Values at --40, +25, +85 Apply to E Package
CONDITIONS
CHARACTER·
ISTIC
Vo
(V)
VIN VDD
(V)
(V)
-55
--40
+85
+125
Min.
+25
Typ.
-
D,S
5
5
5
150
150
-
0.04
5
-
0,10
10
20
300
-
0.04
10
0,15
10
20
300
-
10
15
600
600
~
0.04
20
-
0,20
20
100
100
3000
3000
-
0.08
100
Output Low
(Sink) Current
IOL Min.
0.4
0,5
5
0.64
0.61
0.42
.0.36
0.51
1
-
0.5
0,10
10
1.6
1.5
1.1
0.9
1.5
0,15
Output High
(Sourcel
Current,
IOH Min.
4.6
D,S
D,S
0,10
0,15
15
5
Quiescent Device
Current,
100 Max.
Output Voltage:
Low-Level,
VOL Max.
Output Voltage:
High·Level,
VOH Min.
Input Low
Voltage,
VIL Max.
Input High
Voltage,
VIH Min.
I nput Current
liN Max.
2.5
9.5
13.5
4.2
4
-0.64 -0.61
5
-2
10
15
-1.6
-4.2
-1.8
-1.5
-4
2.8
-0.42
-1.3
-1.1
-2.8
1.3
34
2.4
-0.36 -0.51
2.6
-
6.8
-1
-
-1.15 -1.6
-3.2
-
-0.9
-2.4
-1.3
-3.4
-2.6
-6.8
-
-
0,5
5
0.05
-
0
0.05
-
0,10
0.05
0.05
-
0
0
0.05
-
10
15
5
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5
10
15
0.05
-
-
0,15
D,S
0,10
0,15
0.5,4.5
-
5
1.5
-
-
1.5
1,9
-
10
-
-
1.5,13.5
0.5,4.5
1,9
-
15
3
4
-
-
-
5
3.5
7
-
-
1.5,13.5
-
10
15
3.5
7
3
4
-
11
11
-
-
-
0,18
18
-
-
±0.1
±0.1
±1
±1
-
UNITS
Max.
±10- 5
±0.1
/lA
~ 100
~
~
50
40
50
60
70
80
90
100
LOAD CAPACITANCE tel 1 - pF
Fig. 12 - Typical propagation delay time
as a function of load capacitance.
rnA
V
V
2:
"68
'0
2:
4 6 ~02 2
4 6 ~oJ 2:
4 6 ~04 2
4 6 ~o~
INPUT FREQUENCY (fINI-KHl
Fig. 13 - Dynamic power dissipation.
/lA
o
91
--'~-C:=~~il.
O- I-~
88-96
(2.235 - 2.4 38)
4-10
(0.102.. -0
.... 254)
111-119
.. ~--(2.819-3.022)
92CS-2B930RI
.1
The photographs and dimensions of each
Dimensions and pad layout for the CD40192BH
(dimensions and pad layout for the CD40193BH
are identical).
is part of the wafer. When the wafer is
Dimensions in parentheses are in millimeters and
are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10- 3 inch).
57 Instead of 90 with respect to the
face of the chip. Therefore, the isolaced
chip is actually 7 mils (0. 17 mm) larger
in both dimensions.
COS/MOS chip represent a chip when it
CU~
into chips, thg cleavage angles are
431
CD401928, CD401938 Types
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C
Input t r • ~
=20 ns. CL =50 pF. RL =200 kn
CHARACTERISTIC
LIMITS
VDD
(VI
5
10
15
Propagation Delay Time tpHL' tplH:
CLOCK UP or CLOCK DOWN to O. RESET to 0
UNITS
Min. Typ. Max.
-
ns
90
500
240
180
200
100
70
400
200
140
ns
320
160
120
ns
250
120
PEto 0
5
10
15
CLOCK UP to CAR RY. CLOCK DOWN to BaR ROW
5
10
15
-
160
80
60
5
10
15
-
300
150
110
600
300
220
ns
5
10
15
-
100
50
40
200
100
80
ns
5
10
15
-
40
20
15
80
40
30
ns
240
150
130
480
300
260
ns
120
85
70
240
170
140
ns
90
45
30
180
90
60
ns
4
8
11
-
MHz
RESETorPEtoBORROWorCARRY
Transition Time. tTH l. tTlH
Min. Removal Time. t rem
* RESET or PE
5
10
15
Min. Pulse Width. tw RESET
5
10
15
PE
5
10
15
CLOCK
-
-
-
-
Fig. 14 - Dynamic power dissipation test circuit.
92CS-21401RI
Fig. 15 - Ouiescent-dev;ce-current test circuit.
Fig. 16 - Input-lloitage test circuit.
Max. Clock Input Frequency. fCl
5
2
4
10
15 5.5
Clock Rise & Fall Time. t" tf
5
10
15
-
-
15
15
5
JlS
-
-
10
15
pF
5
7.5
pF
Input Capacitance. CIN:
RESET
V~NPU(J'
'. ;;';:::.;~~
Vss
All Other Inputs
III
INPUTS r---~-,
o
Vss
TO BOTH Vao ANO Vss"
CONNECT ALL. UNUSED.
INPUTS TO EITHER
Vao OR Vss'
Vss
The time required for RESET or PRESET ENABLE control to be removed before clocking (see timing
Fig. 77- Input current test circuit.
diagram, Fig. 10,.
JI J2 J3 J4
JI
J2 J3 J4
CLOCK U
~::i~------------~----------------------~
92C5-2756''''
Fig. 18,· cascaded counter packages.
432 __________________________________________________________________
CD40208B Types
COS/MaS 4 x 4 Multiport
Register
High-Voltage Types (20-Volt Rating)
The RCA-CD4020BB is a 4 x 4 multipart
register containing four 4-bit registers, write
address decoder, two separate read address
decoders, and two 3-state output buses.
When the ENABLE input is low, the corresponding output bus is switched, independently of the clock, to a high·impedance
state. The high-impedance third state provides the outputs with the capability of being
connected to the bus lines in a bus-organized
system without the need for interface or
pull-up components.
When the WRITE ENABLE input is high,
all data input lines are latched on the positive
transition of the CLOCK and the data is
entered into the word selected by the write
address lines. When WRITE ENABLE is low,
the CLOCK is inhibited and no new data is
entered. In either case, the contents of any
word may be accessed via the read address
lines independent of the state of the CLOCK
input.
The CD4020BB types are supplied in hermetic 24-lead dual-in-line ceramic packages
(D and F suffixes), 24-lead dual-in-line plastic packages (E suffix), 24-lead ceramic flat
packages (K suffix), and in chip form (H
suffix).
Features:
• Four 4-bit registers
• One input and two output buses
• Unlimited expansion in bit and word
directions
• Data lines have latched inputs
• 3-state outputs
• Separate control of each bus, allowing
simultaneous independent reading of
any of four registers on Bus A and
Bus B and independent writing into
any of the four registers
• Standardized, symmetrical output
characteristics
• 100% tested for quiescent current at 20 V
• Maximum input current of 1 /lA at 18 V
over full package-temperature range;
100 nA at 18 V and 25 0 C
• Noise margin (over full packagetemperature range):
1 Vat VDD = 5 V
2VatVOD=10V
2.5 Vat V DD = 15 V
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC
Tentative Standard No. 13A, "Standard
Specifications for Description of 'B'
Series CMOS Devices"
WRITE
ENABLE
OO
OATA
,NPUTS
~o
:
{ 01
0,18
o
.;
"}
01
11'0110 A
02
OUTPUT
, "
",
:: OO}
01
WOIIO!l
l
,
O~
OUTPUT
"
"'00'24
"'S5' 12
FUNCTIONAL OIAGRAM
Applications:
ENABLE
• Scratch-pad memories
• Arithmetic units
• Data storage
e
Fig. 1 - Block diagram.
TRUTH TABLE
CLOCK
2'
2'
22
ENABLE A
"
DO A
01 A
D2A
20
WRITE 0
"
I.
17
WRITE I
I.
DlA
READ DB
10
REAO IB
Vss
12
"
I.
13
VDD
018
51
52
SI
S2
51
52
1
1
1
1
1
1
51
52
51
52
51
S2
1
1
0
0
0
X
X
X
X
X
X
X
0
0
1
0
0
0
1
1
0
I
1
X
008
ENABLE 8
DO
01
°nB
1
~
I·
DnA
~
X
028
On
~
~
038
WRITE WRITE WRITE READ READ READ READ ENABLE ENABLE
ENABLE
1
lA
OA
lB
0
OB
A
B
------
X
Z
Z
On to
word 0
Word 1 Word 2
oul
oul
0
0
0
0
1
1
0
1
1
Word 0
not altered
Word 1 Word 2
oul
oul
X
X
X
1
0
0
1
1
1
X
X
X
X
X
X
X
X
1
,
Word 2 Word 1
oul
oul
X
NC
NC
1 - HIGH LEVEL. 0 LOW LEVEL. X
DON'T CARE, Z= HIGH IMPEOANCE
Sl and S2 rete' 10 "'PU! ~l.!1e\ of p,!hr, 10' a
02
0'
CL.OCK
WRITE ENABLE
READ IA
REAO OA
TOP VIEW
9ZCS-28550Rt
TERMINAL ASSIGNMENT
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY·VOL TAGE RANGE, (V OO )
(Voltages referenced to VSS Terminal)
-0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS
-0.5 to VDO +0.5 V
. OC INPUT CURRENT, ANY ONE INPUT
±10mA
POWER OISSIPATION PER PACKAGE (PO):
For TA = -40 to +60 0 C (PACKAGE TYPE E)
..
.....
500mW
For T A = +60 to +85 0 C (PACKAGE TYPE E)
Derate Linearly at 12 mW/oC to 200 mW
For TA = -55 to +100 0 C (PACKAGE TYPES O,F J
. ..
.....
500 mW
For T A = +,00 to +125 0 C IPACKAGE TYPES D, F J.
Derate Linearly at 12 mW/oC to 200 mW
DEVICE OISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types)
100mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPES 0, F, H
-55 to +125 0 C
PACKAGE TYPE E
-40 to +85 0 C
STORAGE TEMPERATURE RANGE (Tstgl
-65 to +1500 C
LEAD TEMPERATURE (DURING SOLOERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max.
433
CD402088 Types
r-----------------r--------------,
dVDD
PIN 24' Voo
PIN 12' Vss
I
A
I D
QA
I
I
ALL INPUTS PROTECTED
BY COSIMOS INPUT
PROTECTION NETWORK
IZCL-29222
I
Q8
I
I
I
L"':~R~C~~
I
I
I
I
~PUTI
Iw
, DETAIL OF'
I
~_ ...... OUT
I
I
*
ENABLE
_____ .______
h
'lVss
i
t
I
I
t
t DETAIL OF
I
L3:..S~T.:O~T~~ ______ --1
92CL-29222
Fig. 2 - Logic diagram.
D,
WE
WA--~--------+-----A-------~-/~~~---------.A---+.--~-----t.~~----------~--~+_~~O~---n'LQ,
Fig. 3 - Timing diagram.
434 ________~-----------------------------------------------------------------------------------
CD40208B Types
RECOMMENDED OPERATING CONDITIONS at TA = 250 C, Except as Noted.
For maximum reliability, nominal operating conditions should be eelected so that
operation is always within the fol/owing ranges:
LIMITS
CHARACTERISTIC
VDD
(V)
Supply Voltage Range
(For T A = Full Package
Temperature Range)
-
3
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
0
0
0
250
100
70
250
100
70
220
100
80
270
130
80
330
140
90
Set·Up Time:
Data \0 Clock, tS(D)
Write Enable to Clock,
tS(WE)
Write Address to Clock,
tS(WA)
Hold Time:
Data to Clock, tH(D)
Write Enable to Clock,
tH(WEI
Write Address to Clock,
tH(WA)
Clock Input Frequency,
tCl
Clock Pulse Width,
Clor WE
tw
Clock Rise or Fall Time,
trClor tt Cl
MIN.
MAX.
18
UNITS
V
-
ns
,
-
DRAIN-TO-SOURCE VOLTAGE (VQsl-V
-
-
Fig. 4 - Typical output low (sink J
current characteristics.
ns
-
-
I~~~'E.~C
ns
I;'
-
-
ns
350
130
90
;;;::;;:
,
:::
':';1
I:!!:i,:
Ill!
h-'
I;U:
HI Ii'
:'!1
;;;
§
-
-
TO-.~RCE
I" I"! ~:::j::::
I~
ns
~"
-
w
11",
-
-
:;n it:! :lI:!i
ittl ";;:nn :it:
ill! :11;::
:~~~~tm
ns
1.5
3.5
4.5
-
MHz
-
ns
,
DRAIN-TO-SDURCE VOLTAGE (Vos)-V
Fig. 5 - Minimum output low (sink)
current characteristics.
ORAIN-tO-SOURCE VOLTAGE
(Vosl-\I
-
-
15
5
5
-
-
J.Ls
Fig. 6 - Typical output high (source)
current characteristics.
DRAIN~TO-SOURC£
vOLTAGE (11051-\1
LOAD CAPACITANCE ICL)-pF
nCS-21219
Fig. 8 - Typical propagation delay time as a
Fig. 7 - Minimum output high (source)
current characteristics.
function of load capacitance (CL or
WE
0).
'a
Fig. 9 - Typical transition time as a function
of load capacitance.
435
CD40208B Types
"'% .... ENT TEMPERATURE 1T"'''l.~
STATIC ELECTRICAL CHARACTERISTICS
CHARACTER·
ISTIC
Quiescent Device
Current,
100 Max.
LIMITS AT INDICATED TEMPERATURES (OC)
Value. at -55, +25, +125 Apply to D,K,F ,H Package.
CONDITIONS
Values at -40, +25, +85 Apply to E Package
UNITS
+25
Vo
VIN VDD
Typ.
Min.
+125
Max.
-40
+85
-55
(V)
(V) (V)
-
0,5
0,10
0,15
0,20
-
Output low
(Sink) Current
IOl Min.
Output High
(Source)
Current,
IOH Min.
Output Voltage:
low-level,
VOL Max.
Output Voltage:
High-level,
VOH Min.
Input low
Voltage,
Vil Max.
Input High
Voltage,
VIH Min.
I nput Current
liN Max.
3-State Output
leakage Current
lOUT Max.
5
10
15
5
10
20
20
100
5
0.64
5
10
20
100
0.61
1.5
1.6
4.2
4
-0.64 -0.61
-2
-1.8
-1.6 -1.5
-4
-4.2
150
300
600
3000
150
300
600
3000
0.42
1.1
2.8
-0.42
-1.3
0.36
0.9
2.4
-0.36
-1.15
-0.9
-2.4
-
-
-
0.51
0.04
0.04
0.04
0.08
5
10
20
100
1
2.6
-
p.A
0,5
0,10
0,15
0,5
0.5
0,10
0.15
10
15
5
5
10
15
-
0,5
5
0,10
0,15
0,5
0.10
0,15
10
15
5
10
15
-
-
5
10
15
5
10
15
0,18
18
±0.1
±0.1
±1'
±1
-
±10- 5
±0.1
p.A
0,18
18
±0.4
±0.4
±12
±12
-
±10-4
±0.4
p.A
-
0.5,4.5
1,9
15,13.5
0.5,4_5
1,9
1.5,13.5
0.18
-1.1
-2.8
-
-
0
0
5
10
15
0.05
0.05
-
-
-
-
1.5
~
§
f-
•
I
I
/
:
~
-i.
,~~
r:t .
I:r
i-t;-hi,F
~L,t;
~
i.04.
~J
,}
f...;/
t
i21()l:.
·tT,
t
/
L
· .... .... t~ r-cl'ml-'-..
V
2
.. 68
24118
~.
,
INPUT FREQUENCY tlII-kHt
92CS-2!1216
Fig. 10 - Typical power dissipation as a
function of input frequency_
rnA
0.05
4.95
9.95
14.95
II
•
-
0
0.05
0.05
0.05
4.95
9.95
14.95
3
4
3.5
7
11
6.8
-1
-3.2
-2.6
-6.8
I
do
0.4
0.5
1.5
4.6
2.5
9.5
13.5
1.3
3.4
-0.51
-1.6
-1.3
-3.4
··
.
~IC)S.
-
-
-
1.5
3
4
3.5
7
-
-
11
-
-
V~NPU(JS ~~:~URE
V
VDO
o ~
•• PUTS
SEQUENTIALLY,
Vss
TO BOTH Yoo ANO Vss'
CONNECT ALL UNUSED
INPUTS TO EITHER
Voo OR VSS'
VSS
V
Fig. 11 - Input leakage current
test circuit.
INPUTS
o
Vss
140
co
Vss
Fig. 12 - Ou;escent-device-current
test circuit.
114-122
12."·'·0••
Dimensions and Pad Layout for CD40208BH
Dimensions in parentheses are in millimeters and aTe
derived from the basic inch dimensions as indicated.
Grid graduations arB in mils "0-3 inch).
The photographs and dimensions of each COS/MOS
chip represent a chip when it is part of the wafer .
. When the wafer is cut into chips, the cleavage angles
are 5,0 instead of 9rP with respect to the face of
the chip. Therefore, the isolated chip is actually
7 mils (0. 17 mm) larger in both dimensions .
..______ '21 -'54
~
(5.200-3.403)
92CM·29234
436 __________________________________________
~----------------------
CD40208B Types
DVNAMIC ELECTRICAL CHARACTERISTICS at TA
CL = 50 pF. RL = 200 kn
CHARACTERISTIC
Propagation Delay Time:
tpHL' tPLH
Clock or Write Enable to Q
Read or Write Address to Q
3·State Disable Delay Time:
tpZH. tpHZ
VDD
(VI
5
10
15
-
5
10
15
-
5
10
15
5
10
15
tpZL. tpLZ
5
10
15
Output Transition Time:
tTHL' tTLH
Minimum Setup Time:
Data to Clock tS(D)
5
10
15
Write Enable to Clock tS(WE)
Write Address to Clock tS(WA)
Clock Rise and Fall Time:
trCL. tt CL
5
10
15
5
10
15
5
10
15
Minimum Hold Time:
Data to Clock tH(D)
5
10
15
5
Write Enable to Clock tH(WE)
Write Address to Clock tH(WA)
Maximum Clock Input Frequency.
tCL
Minimum Clock Pulse Width.
Clock or Write Enable
tW(CLI
Wr ite Add ress
tW(WAI
Average Input Capacitance.
(Any Input)
CI
Min.
10
15
-
-
-
-
-
-
-
-
-
=25 0 C; Input t,.tt =20 ns.
LIMITS
Typ.
Max.
360
140
100
720
280
200
ns
300
120
85
600
240
170
ns
100
50
40
200
100
80
ns
130
60
50
260
120
100
ns
100
50
40
200
100
80
ns
-95
-35
-20
0
0
0
ns
125
50
35
250
100
70
ns
125
50
35
250
100
70
ns
-
15
5
5
110
50
40
220
100
80
135
270
65
40
130
80
165
70
45
330
140
90
UNITS
Y~
.
NOTE;
~'TN~~~~OW8INATION
Fig. 13 - Input-voltage test circuit.
Voo
,
TEST VOLTAGE
}JS
tpHZ
tpZH
'PLZ
lpZL
ns
".
01.
CHAR
VDO
VD
Vss
Vss
Vss
V
VOD
VDD
Fig. 14 - Output-enable-delav-times test
circuit and waveforms.
ns
-
5
10
15
1.5
3.5
4.5
5
10
15
175
65
45
350
130
90
5
10
15
-
,150
75
45
300
150
90
ns
-
-
5
7.5
pF
3
7
9
~
Yss
5
10
15
-
INPUTQVIlOOUTPUTS
-.......~
V,H
c~
ns
PULSE GEN. 2
-
-
PULSE GEN. I
MHz
PULSE GEN.:3
-
ns
P,G.I
P.G.2
P.G.3
QnA,B~
!--REPETITIVE WAVEFORMS--!
92CM-2921BRI
Fig. 15 - Power-dissipation test circuit
and waveforms.
437
CD40257B Types
COS/MOS
Quad 2-Line-to-1-Line
Data Selector/Multi
plexer
High-Voltage Types (20-Volt Rating)
The RCA-C040257B is a Data Selector/Multiplexer featuring three-state outputs which
can interface directly with and drive data
lines of bus-oriented systems.
The C0402578 types are supplied in 16lead hermeticdual-in-line ceramic packages
(0 and F suffixes). 16-lead dual-in-line plastic packages (E suffix), 16-lead ceramic flat
packages (K suffix), and in chip form (H
suffix).
Features:
• 3-state outputs
• Standardized, symmetrical output characteristics
• 100% tested for quiescent current at 20 V
• Maximum input current of 1 pA at 18 V
over full package-temperature range;
100 nA at 18 V and 250 C
• Noise margin (over full packagetemperature range):
1 Vat VOD = 5 V
2 Vat VDD = 10 V
2_5 Vat VDD = 15 V
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC
Tentative Standard No. 13A, "Standard
Specifications for Description of 'B'
Series CMOS Devices"
OUTPUT
OISABLE
.,
15
AI
01
.,
A'
A3
.3
0'
"
10
A4
IA
B4
13
03
12
INPUT
SELECT
OA
VOO'I6
vss·a
FUNCTIONAL DIAGRAM
Applications:
• Digital Multiplexing
• Shift-right/shift-Ieft registers
• Truelcomplement selection
MAXIMUM RATINGS, Aliso/ute-Maximum Values:
OCSUPPLYVOLTAGE RANGE.IVooi
(Voltaqp,> f!~h,t!'I:{Td 10 vss TI'rflllllill)
0.5 to +20 V
INPUT VOLTAGE RANGE. ALL INPUTS
0.5 to Voo +0,5 V
DC INPUT CURRENT, ANY ONE INPUT
±10 rnA
POWER DISSIPATION PER PACKAGE (Pol
For T A
40 to -GOoe (PACKAGE TYPE E)
500 mW
For T A
IGO t() 18S()C (PACKAGE TYPE E)
OpraH' Lllwarly at 12 mW/oC to 200 mW
For T A
5510 'lOO()e IPA'CKAGE TYPES D,F)
500 mW
For T A t 100 to • 12S()C IPACKAGE TYPES D, F)
DI'f----O
CL
V
ns
OUT
IF41hOR
51hSTAGE
TRUTH TABLE FOR SHIFT REGISTER STAGE
D
CL'
D.,
D
'-
0
,
x
\
J
,
I = HIGH
O' LOW
NC' NO CHANGE
X'DON'T CARE
... LEVEL CHANGE
NC
92CS-11887RI
Fig. 1 - Logic diagram and truth table
(one regi.te, .tagel.
• If mora than one unit is cascaded trCL should be made lass than or aqual to the sum of the transition time
and the fixed propagation delay of the output of the driving stage for the estimated capacitive load.
445
CD4006A Types
STATIC ELECTRICAL CHARACTERISTICS
Limits at Indicated Temperatures (oC)
Conditions
Characteristic
Quiescent Device
Current, IL Max.
D, F,H Package.
Va V'N Voo
(V) (V) (V)
_.
-
-
-
5
10
15
E Package
+25
+125
Typ. limit
0,01
0.5
30
0.01
1
60
0.5
25
1000
-55
0.5
1
25
-40
5
10
250
+25
+85
Limit
0.03
5
70
140
10
0.05
2.5
250 2500
Low-Level,
-
5
5
VOL
-
10
10
o Typ.; 0.05 Max.
o Typ.; 0.05 Max.
High Level,
-
0
0
5
10
4.95 Min.; 5 Typ.
9.95 Min.; 10 Typ.
4.2
-
5
1.5 Min.; 2.25 Typ.
10
3 Min.; 4.5 Typ.
5
10
1.5 Min.; 2.25 Typ.
3 Min.; 4.5 Typ.
4.5
-
5
1 Min.
'9
-
10
1 Min.
1 Min.
1 Min.
Output Voltage:
VOH
Noise Immunity:
Inputs Low,
VNL
9
0.8
1
Inputs High,
VNH
Noise Margin:
Inputs Low,
VNML
Inputs High,
VNMH
0.5
1
-
5
10
Output Drive
Current:
"-Channel
(Sink).
ION Min.
0.5
-
5
0.25
0.125 0.085 0.072
p.A
V
V
Fig. 2 - Typical propagation delay time
load capacitance.
VI.
AMBIENT TEMPERATURE tTA 'o25"C
TYPICAl TEMP£RATUR[ CO[FF!CIENT
FOR AlL VALUES OIF "'OD-O.S"'-C
V
0.25
0.06
0.048
,.
t++-.
40
p-Channel
ISource) :
'OPMin.
Input Leakage
,.
LOAO CAPACITANCE ICLI-,t
10
4.5
-
5
9.5
-
10
·0.25
0.5
Current,
"L."H
0.155
Units
Typ.
0.31
0.5
0.25 0.175
0.15
0.5
0.125
0.1
·0.125 ·0.15
·0.1
·0.07
·0.06
·0.15
·0.05
·0.04
·0.3
·0.2
·0.14
·0.12
·0.3
·0.1
·0.08
AnI,nT
15
±10- 5 Typ .• ±1 Max.
-
rnA
Fig. 3 - Typical transition time
cap3Citance.
VI.
load
p.A
VQD
r-1
I
[l~~----t-----4
-{»--(1,5,12);(2,9);
(11,4); (8,13,10);
(6,3)
'"
. h) Dual Bi-Directional Transmission Gating
g) High Sink- and Source-Current Driver
Fig. 14 - Sample COS/MaS logic circuit arrangements using type CD4007A.
VDO
VII)
,NPom
.~N.(JU'
.'DO ::~U.. 'N"'"
c ~
Yss
SEQUENTIALLY,
TO BCn'" Yoo MDYss
CONNECT ALL UNl.8ID
IfiPUl'S TDEITH'"
YDD CIt Yss·
.
'55
920-274<41
Fig. 15 - Noise-immunity test circuit.
Fig. 16 - Quiescent-device-currenttestcircuit
. Fig. 17 -Input-Ieakage-currenttestcircuit
450 __________________________________________________________________
CD4008A Types
COS/MOS 4-Bit Full Adder
Features:
With Parallel Carry Out
• 4 sum outputs plus parallel look-ahead carry-output
• Quiescent current specified to 15 V
• Maximum input leakage of 1 IJA. at 15 V
(full package-temperature range)
• 1-V. noise margin (full package-temperature
range)
Applications
The RCA-CD4008A types consist of four
full-adder stages with fast look-ahead carry
provision from stage to stage_ Circuitry is included to provide a fast "parallel-carry-out"
bit to permit high-speed operation in arithmetic sections using several CD4008A's.
CD4008A inputs include the four sets of bits
to be added, A 1 to A4 and B1 to B4, in addition to the "Carry In" bit from a previous
section. CD4008A outputs include the four
sum bits, Sl and S4, in addition to the highspeed "parallel·carry-out" which may be
utilized at a succeeding CD4008A section.
These types are supplied in l6-lead hermetic dual-in-line ceramic packages (D and
F suffixes). l6-lead dual-in-line plastic
packages (E suffix), l6-lead ceramic flat
packages (K suffix), and in chip form (H
suffix).
STATIC ELECTRICAL CHARACTERISTICS
• Binary addition/arithmetic units
MAXIMUM RATINGS, Absolute-Maximum Values:
STORAGE·TEMPERATURE RANGE (Tstgl . . • . . . . . . . • . . . . . . . . . . . . • . . . -65 to +150oC
OPERATING-TEMPERATURE RANGE (TAl:
PACKAGE TYPES D. F. H
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to +125 0 C
PACKAGE TYPE E . . . • . . . • • • • • . • . . . . . . . . . . . . . . . . . . . . . . . . -40 to +85 C
DCSUPPLY·VOLTAGE RANGE, (VODI
(Voltages referenced to VSS Terminal1: . . . . . . . . . . . . . . . ~ . . . . . . . . . . . . -0.5 to +15 V
POWER DISSIPATION PER PACKAGE (POl:
FOR TA = -40 to +60oC (PACKAGE TYPE EI
. . . . . • . . . . . . . • . . . . . . . . . . . 500 mW
FOR T A = +60 to +850 C (PACKAGE TYPE E I
. . . . • . Derate Linearly at 12 mW/oC to 200 mW
FOR TA = -55 to +100oC (PACKAGE TYPES D. F)
. . . . . • • . . . . . . • . . . . . • . • 500 mW
FOR T A = +100 to +125 0 C (PACKAGE TYPES D. Fl
. . . Derate Linearly at 12 mW/oC to 200 mW
OEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (ALL PACKAGE TYPESI . . . . . . . 100 mW
INPUT VOLTAGE RANGE, ALL INPUTS . • • . . . . . . . . . . . • • . . . . . . . . -0.5 to VDD +0.5 V
LEAD TEMPERATURE (DURING SOLDERINGI:
At distance 1/16 ± 1/32 inch 11,59 ±O.79 mm) from case for 105 max . . . . . . . . . . . . . . +26SoC
°
Limits at Indicated Temperatures (oC)
D,F,H Packages
E Package
Units
Characteristic
+25
Vo VIN VDD -55
+25
+125 -40
+85
IV) (V) IV)
Typ. Limit
TYIJ· Limit
5
5
0.3
5
300
50
0.5
50
700
Quiescent Device
10
10 0.5 10
600 500
1
100 1400 IJA.,
Current,l L Max.
15
50
1
50 2000 500
5
500 5000
Output Voltage:
0,5 5
o
Typ.; 0.05 Max.
Low-Level,
0,10 10
oTyp.; 0.05 Max.
VOL
V
High Level,
0,5 5
4.95 Min.; 5 Typ.
VOH
0,10 10
9.95 Min.; 10 Typ.
Noise Immunity: 4.2
5
1.5 Min.; 2.25 Typ.
'Inputs Low,
9
- 10
3 Min.; 4.5 Typ.
VNL
V
O.B 5
1.5 Min.; 2.25 Typ.
Inputs High,
VNH
1
- 10
3 Min.; 4.5 Typ.
Noise Margin;
4.5 5
1 Min.
Inputs Low,
VNML
9
- 10
1 Min.
V
Inputs High,
0.5 5
1 Min.
VNMH
1
1 Min.
- 10
Conditions
- - - -
Output Drive
Current:
n-Channel
(Sink),
ION Min.
p-Channel
(Source),
IDPMin.
Input Leakage
Current,
IlL, IIH Max.
• Carry Output
·
·
....
0.5
-
3
-
....
3
....
4.5
9.5
2
7
-
··
....
0.5
-
Any
Input
ASum Output
5
0.31 0.5 0.25 0.175 0.155
0.5
0.13
0.105
10
0.93 1.5 0.75
1.5
0.5
0.4
5
0.012 0.2 0,01 0.007 0.009 0.2 0.007 0_005
10
0.31 0.5 0.25 0.175 0.24
-0.31 -0.5 -0.25 -0.175 -0.155
-0.93 ·1.5 -0.75 ·0.53 ·0.6
-0.01 ·0.2 ·0.01 -0.007 -O.OOB
-0.IB5 ·0.3 -0.15 ·0.105 ·0.12
5
10
5
10
15
0.53
0.6
0.5
0.2
0.16
Characteristic
Min, Max. Units
Supply-Voltage Range
(TA= Full Package·
Temp. Range)
3
12
V
"0
~*15
'.
..*,
"
BI
IIS2~DD
"* 6
51
" (*~7+""'_ _--l':'::::'
--
*.
c,o'....- - - -....
(CARRY IN)
*PROTECTED
ALL INPUTS ARE
BY
Voo i' 16
VS5
=8
VSS
COSt MOS PROTECTION
NETWORK
92CS- 25017R2
Fig. 1 - CD4008A logic diagram.
TRUTH TABLE
mA
-0.5 -0.13 -0.105
·1.5 ·0.5 -0.4
-0.2 -0.007 ·0.005
·0.3 ·0.1 -0.08
±10-5 Typ.; ±1 Max.
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating
conditions should be selected so that opera·
tion is always within the following ranges_
AI
Bi
CI
Co
SUM
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
1
0
0
1
0
IJA.
1
0
1
0
0
0
1
1
1
1
0
1
0
1
1
1
0
1
451
CD4008A Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C; Input tr. tf= 20 ns. CL = 15 pF.
RL=200Kn
LIMITS
CHARACTERISTIC
VDD
(V)
Typ.
Max.
Typ.
Max.
Propagation Delay Time: tpHL' tpLH
Sum In to Sum Out
5
10
900
325
1300
500
900
325
2000
650
ns
Carry In to Sum Out
5
10
900
325
1300
500
900
325
2000
650
ns
Sum I n to Carry Out
5
10
320
120
600
200
320
120
ns
Carry I n to Carry Out
5
10
100
45
175
75
100
45
800
240
200
90
5
10
1250
550
2200
900
1250
550
2900
1100
ns
5
10
125
45
225
75
125
45
290
90
ns
-
10
-
10
-
pF
Transition Time: tTHL' tTLH
At Sum Outputs
At Carry Output
Input Capacitance. CI
(Any Input)
D.F.H
Packages
E
UNITS
Package
30
40
SO
so
.:::4''''
:-:-:-r:·....
LOAD CAPACITANCE ICLI-pF
Fig. 2 - Typical sum-in to carry out propagation
delay time 'IS, CL'
ns
Fig. 3 - Typical $um4n or carry-in to sum-out
propagation .dB~ay time VI. CL'
."
LOAD CAPACITANCE ICLI'ISpF
--Cl"50pF
102
101
"Ifif"UTFIIEOIIEffC'I'U.J-.Hr
20
SUPPLY VOLTS ('1100)
Fig. 4 - Typica' carry-in to carry.out propagation
delay time vs. CL'
YDO
Fig. 5 - Typical maximum propagation delay time
'Is. V DD for carry-in to carry-out.
8 13-16
:t
INPUTS
NOTE.
o
TEST ANY ONE IN?UT,
Yss
VSS
Fig. 6 - Typical dissipation characteristics.
.,,-,.{
yoo-:::.:urO"-.:.
V:L
Yco
,,'
WITH OTHER INPUTS AT
9ltS-laoo "00 OR Yss
..-,,{
}s._"
8 9-12
Fig. 8 - Noise immunity test circuit.
'L
v'"
v~.pu(Js
vDO :~::u.,
o ~
"SS
..-a{
8S-S
'.NPUTS
SEOUOHIAL.L.Y,
TO BOTH "DO AHOV!S
CONNECT AL.L. UNUSED
.'-4f
81-4
INP\lTS TO EITNER
"DOMVSS
Fig. 7 - Quiescent device current tIIst circuit.
452
v"
V55
Fig. 9 - Input leakage current rest circuit,
Fig. "0 - Typical connection for a 16·b;t adder.
CD4009A, CD4010A Types
COS/MOS
Hex Buffers/Converters
Inverting Type: CD4009A
Non-Inverting Type: CD4010A
The RCA-C04009A and CD4010A Hex
Buffer/Converters may be used as COS/MOS
to TTL or OTL logic-level converters or
COS/MOS high sink-current drivers_
The C04049A and C04050A are preferred
hex buffer replacements for the C04009A
and G04010A, respectively, in all applications except multiplexers_ For applications
not requiring high sink current or voltage
conversion, the C04069B Hex Inverter is
recommended.
1/1/'.,............
.,
0-......
IN
A
~.
8
~-
C
~.
H'B
I-e
, ~"
GATES
Vss
ALL INPUTS ARE PROTECTED BY
COS/MOS PROTECTION NETWORK
NCQ-!}
Vcco-J..
vsso-.!
VDOe-!!
r
oe-{>" -oM'£
' ~"
'U'·4'40Ill,
CD4009A
Features:
• Quiescent current specified to 15 V
• Maximum input leakage of 1 J.IA at 15 V
(full package-temperature range)
• High sink current for driving 2 TTL loads
• High-to-Iow level logic conversion
These types are supplied in 16-lead hermetic
dual-in-line ceramic packages (0 and F
suffixes), 16-lead dual-in-line plastic package (E suffix), 16-lead ceramic flat package
(K suffix), and in chip form (H suffix).
~
~
~
o
~
~
~
G.A
NC~
A
G-A
B
H-B
C
I_ C
E
veco--l
Ysso--!
F
\lDD~
J. D
Ie. E
L- F
.2SS·414ZR~
CD4010A
Fig. 7 - Logic diagrams.
' • •IENT
'ERATU", IT 1-""
Applications:
•
•
•
•
COS/MOS to DTL/TTL hex converter
COS/MOS current "sink" or "source" driver
COS/MOS high-ta-Iow logic-level converter
Multiplexer 1 to 6 or 6 to 1
"'ON'VCO ' "
RECOMMENDED OPERATING CONDITIONS at TA = 25°C, Except as Noted.
For maximum reliability, nominal operating conditions should be selectad SO that
operation is always within the following ranges:
LIMITS
CHARACTERISTIC
Supply-Voltage Range (For T A = Full PackageTemperature Range: VDD, VCC)
Input Voltage Range (VI)
UNITS
Min.
Max.
3
12
V
VCC'
12
V
Fig. 2 - Minimum & maximum voltage transfer
characteristics - CD4009A.
* The CD4009 and C04010 have high~to·low level voltage conversion capability but not low·to-high level,
therefore it is recommended that VOO ~ VI
;;> Vee.
4
•
INPUT VOLTS
•
tv"
10
Fig. 3 - Typical voltage transfer characteristics
as function of temp. - CD4009A.
,
.,
INPUT VOLTS Iyt I
Fig. 4 - Minimum & maximum voltage transfer
characteristics (VDD = 5) - CD4070A.
Fig. 5 - Minimum & maximum voltage transfer
characteristics (VDD = 70) - CD4010A.
Fig. 6 - Minimum & maximum voltage transfer
characteristics (VDD = 75) - CD4070A.,
453
CD4009A, CD4010A Types
STATIC ELECTRICAL CHARACTERISTICS
Limits at Indicatad Temperatures (oC)
Conditions
Vo VIN VCC·
+25
-55
(V) (V) (V)
Typ. Limit
- 5 0.3 0.01 0.3
Quiescent Device Current,1 L Max. - 10 0.5 0,01 0.5
Output Voltage:
Low· Level,
VOL
High Level
VOH
Noise Immunity:
Inputs Low,
VNL
CD4010A
Inputs High
VNH
All Types
Inputs Low,
VNL
CD4009A
Noise Margin:
Inputs Low,
VNML
CD4010A
-
0.02
10
3
5
Typ. Limit
0.03
3
0.05
5
100
50
0.5
5
oTyp.; 0.05 Max.
oTyp.; 0.05 Max.
-
0,5
0,10
5
10
4.95 Min.; 5 Typ.
9.95 Min.; 10 Typ.
3.6
-
5
1.5 Min.; 2.25 Typ.
50
Units
+85
42
70
IlA
500
V
--,
Fig. 7 - Typical voltage transfer characteristics
as a'function of temperature - CD4010A.
AMBIENT TEMPERATlIR'E (TA)- 2!1"C
~ 300 LOAD CAPilCITANC[ ICl)- l~pF
-
10
3 Min.; 4.5 Typ.
5
1.5 Min.; 2.25 Typ.
10
3 Min.; 4.5 Typ.
5
1 Min.; 1.5 Typ.
7.2
-
10
2 Min.; 3 Typ.
4.5
-
5
7.2
}'t'
;
mm
200
.PLASTIC PACKAGES ('PLHI-
1 Min.
-
10
1 Min.
0.5
5
1 Min.
1
-
10
1 Min.
0.4
-
5
0.5
-
10
4.6
-
5
Any Input
V
PLASTIC
9
2.5
9.5
I nput Leakage
Current,
IIL,IIH
10
20
30
10
3.6
P·Channel
(Source),
lOP Min.
15
-40
0,5
2.8
Output Drive
Current:
N·Channel
(Sink),
IDN Min.
-
Package
+25
+125
0,10
-
1.4
Inputs High,
VNMH
CD4010A
E
D, F,H Packages
Charactaristic
3.75
4
10
10
·0.31 ·0.5
15
10
I!>
SUPPLY VOLTS NOD' vee1
VDD - CD4010A.
V
2.1
3.6
8
5.6
9.6
·0.25 ·0.175 ·0.3
·0.9
·0.4
(lpHL)
Fig. 8 - Maximum propagation dt1lay time vs.
3
5 ·1.85 ·1.75 ·1.25
10 ·0.9 ·0.8 ·0.6
PAC~AGrS
4
3
2.4
10
8
6.4
mA
·0.5 ·0.25 ·0.2
·1.5 ·1.75 ·1.25 ·1
·0.72 ·0.8 ·0.6 ·0.48
±10- 5 Typ.; ±1 Max.
IlA
Fig.
'Vcc=Voo
9 - Typical n-channel drain characteristics,
,
LOAD CAF'ACITANCE (CL!-pF
DRAIN-YO-SOURCE VOLTS (Vos) 'ZCS-11e7'
Fig. 10 - Minimum n-channfll drain
charscteristics.
Fig. 11 - Typical high-to%~~w level propagation
dalay time VI, CL"
Fig. 12 - Typicallow-to-high level propagation
delay time VI. CL-
454 ____________________________________________________________________
CD4009A, CD4010A Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C; Input t r , tf = 20 ns, CL = 15 pF,
RL=200Kn
CONDITION
CHARACTER ISTIC
D,F,H
VDD
(V)
VI
(V)
LIMIT
VCC
(V)
Typ.
UNITS
Max.
Packages
Propagation Delay Time:
Low·to-High, tpLH
High-to-Low, tpHL
Transition Time:
Low-to-High, tTLH
High-to-Low, tTHL
Input Capacitance, CI
CD4009A
CD4010A
5
5
5
50.
80
10
10
10
25
55
10
10
5
15
30
5
5
5
15
55
10
10
10
10
30
10
10
5
10
25
5
5
5
80
125
10
10
10
50
100
5
5
5
20
45
10
10
10
16
40
-
-
-
15
5
-
5
5
5
50
100
ns
Fig. 13 - Typical high-to-Iow level propagation
delay time vs. CL (driving TTL, DTL).
ns
pF
E Package
Propagation Delay Time:
Low-to-high, tpLH
High-to-Low, tpHL
Transition Time:
Low-to-H igh, tp LH
High-to-Low, tTHL
Input Capacitance, CI
CD4009A
CD4010A
LOAD CAPACITANCE (CLI-pF
Fig.
10
10
10
25
70
10
10
5
15
40
5
5
5
15
70
10
10
10
10
40
10
10
5
10
35
5
5
5
80
160
10
10
10
50
120
5
5
5
20
60
10
10
10
16
50
-
-
-
15
-
-
5
-
14 -
92C5 Plln
Typicallow-to-high level propagation
delay time vs. CL (driving TTL, DTL)
ns
ns
pF
Fig. 15 - Typica' high-to-Iow le'l8/ transition tim.
Ys. CL"
0.'"''
11
II
. ~".
'
~
:
we
c:~ '. :~(:.';, ~~m\;,"1
... ,,:..,
,
~
;
,"~I
!~;;'1'
..
LOAD CAPACITANCE ICLI-pF
Fig. 16 - Typicallow-to-high level transition time
VI.
CL-
~
5~PPLY
VOLTSiVOO" veel
Fig. 17 - Maximum propagation delay time
V DO - CD4009A.
4 6 1 102
2
4
"Ib,
INPUT FREQuENCY Ct.l kHI
2
...,.
VI.
Fig. 18 - Typical dissipation characteristics.
455
CD4011A, CD4012A, CD40213A Types
COS/MOS NAND Gates
Features:
Quad 2 Input - CD4011A
Dual 4 Input - CD4012A
Triple 3 Input - CD4023A
The RCA-CD4011A, CD4012A, and CD4023A NAND gates provide the system
designer with direct implementation of the
NAND function and supplement the existing
family of COS/MaS gates_
These types are supplied in 14-lead hermetic dual-in-line ceramic packages (0 and
F suffixes). 14-lead dual-in-line plastic
packages (E sullix). 14-lead ceramic flat
packages (K suffix). and in chip form (H
suffix).
• Quiescent current specified to 15 V
• Maximum input leakage of t JJA at 16 V
(full package-temperature range I
• t-v noise margin (full package-temperature
rangel
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating
conditions should be selected sO that opera. tion is always within the following ranges:
92CS-24763
CD4011A
Min_ MIX. Units
Char_ristic
Supply Voltage Range
(over full package
3
12
V
temperature range)
MAXIMUM RATINGS,Abso/utll-Maximum VB/UBS:
d"g) ...........................
STORAGE· TEMPERATURE RANGE
-8510 +150oC
OPERATING·TEMPERATURE RANGE (TA):
PACKAGE TYPES O. F. H
. • • . . . • • • • • • • • • . . . . • • • • • • • • . • • • • . -5510 +125 C
PACKAGE TYPE E . . . • . . • • . . • . . . . . . . . • . • • . . . . • • • • • : .•••• -40 10 +8&oC
DC SUPPLY-VOLTAGE RANGE. (VOO)
(Vollagesreferenced 10 VSS Terminal): . . . . . . • . • • • . • • . • . . • . • • • . • • • • -0.& to +15 V
POWER DISSIPATION PER PACKAGE (PO):
FOR TA = -4010 +BOoC (PACKAGE TYPE E)
. . . . . . • . . . • • . • • • • • • • • • • • • 500 mW
FOR TA = +60'0 +850C (PACKAGE TYPE E)
..•••. Dera.. Linearly 01 12 mW/oC 10 200 mW
FOR TA = -55 to +IOOoC (PACKAGE TYPES D. F)
. • . • . • . . . . . • • • . . • • • • • • 500mW
FOR T A = +100'0 +125 0C (PACKAGE TYPES D. F)
.•• Derale Linearly 0.,2 mW/oC 10 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR T A = FULL PACKAGE·TEMPERATURE RANGE (ALL PACKAGE TYPES) .••..•• 100 mW
INPUT VOLTAGE RANGE. ALL INPUTS . • . . . • . . . . . . . . . . • . . . . • . • -0.510 VDD +0.5 V
LEAD TEMPERATURE (DURING SOLDERING):
A. distance 1/16 ±1/32 inch (1.59 ±0.79 mml from ca .. for 10. max . • . • • • . . • • • . • . +2650C
°
Ne
VSS T
••"[.";":i':ii
Ne
92CS-iM"!H
CD4012A
14YoD
92CS-Z"?61
CD4023AH
Fi,. 1 - Functional di6flnm •.
~
...
Ul
R
Voo
GATE.
DI
.
"s.
ALL. INPUTS ARE: PROTECTED BY
COS/MOS PROTECTIDN NETWORK.
92CS-2ZH7RI
Fig. 2 - Minimum & _imum lID/t/IgfI tr....fo,
chaf'llt:r.riltic.,
Fig_
3-
Typical IIQ/t/IgfI trllMfrlr thlH8Cterl.tic'
... function of temperllruIW.
I
INPUT VOLTS
IVII
.",ut VOLT' tvl'
9ZCS-I?"""
Fig. 4 - Typical multipl. input switching tIfInsfo,
chBrBCtllriltics for CD4012A.
456 ____________________
DRAIN- TO -SOURCE VOLTS (YDSI
9lCS-171!10
Fig. 5 - Typical curIWnt & IID/.
ch"'lICter;'tic,.
~
rr.".for
Fig. 6 - Typical n-chBnnel drain characteristics.·.
____________________________________________
CD4011 A, CD4012A, CD4023A Types
STATIC ELECTRICAL CHARACTERISTICS
..
O""",-TO-S0LA2 VOlTAGE 1VOSI-V
-10
Limits. IndiCIItIId TemperlltUre. (OC)
Condition.
E
0, F,H PlICk.",.
CheFlCtlrlstic
PlICk.",
Units
+25
+25
Vo VIN VDD -&&
+B&
+12& -40
(V) (V) (V)
Typ. Limit
Typ: Umit
15
3
0.5 0.005 0.5
& 0.0& 0.001 0.0&
Quiescent Device
30
0.005 5
6
&
10 0.1 0.001 0.1
Current, I L Max.
50
500
0.5
0.02
40
50
1&
2
2
Output Voltage:
Typ.; 0.05 Max.
0,5
&
Low· Level
VOL
Typ.; 0.05 Max.
0,10 10
- - - -
-
High Level,
VOH
Noise Immunity:
Inputs Low,
VNL
Inputs High.
VNH
Noise Margin:
Inputs Low.
VNML
Inputs High.
VNMH
Output Drive
Current:
N·Channel
(Sink)
ION Min.
3.6
7.2
1.4
2.8
4.5
9
0.5
1
&
-
IJA
GtoTt-TO-1iCUICI WUAG[ t
'·'!lV
"",-nee
.u.ENT 1UIN:1tATUM:
TYPICAL TlMII! COE"ICIENT AT ALL VALUES Of' VGs.~QS"'''-c
r-
V
4.95 Min.; 5 Typ.
9.95 Min.; 10 Typ.
Fig. 7 - Typical p-chann.' drain chersctllrl,ticl.
1.5 Min.; 2.25 Typ.
10
3 Min.; 4.5 Typ.
5
10
1.& Min.; 2.25 Typ.;
3 Min.; 4.5 Typ.
5
1 Min.
10
1 Min.
5
10
1 Min.
V
V
1 Min.
_N-'D-~""'"
0.6
0.5
CD4012A
0.5
0.5
Input Leakage
Current.
IIL.IIH
-
VDO
VOLTS
Fig. 8 - Minimum n-chsnn.' drain charsctBristics
CD4011A
CD4023A
P-Channel
(Source).
ioPMln.
All Types
&
10
-
,
-----'
_II!
OTHER
INPUTS GIIOUNDED
o
o
0,5
0,10
V~".,,:
-
-CD4011A & C04023A.
0.5
0.12. 0.095
0.6
0.25
0.2
0.06
0.06
0.31
10
0.62
0.6
0.5
5
0.16
0.25
0.12 0.085 0.072 0.25
10
0.31
0.6
0.2& 0.176 0.155
0.31 -0.5
-0.25 -0.175 -0.145
0.5
4.5
-
&
9.5
-
10 -0.75 -1.2
Any
Input
0.25 0.175 0.145
5
0.35
-0.4
-0.6
0.3
-0.35
-0.5 -0.12 0.095
-0.3
-1.2
-0.24
±lo-5 Typ.; ±1 Max.
15
mA
0.13 0.105
0.6
IJA
DRAIN -TO-SOURCE VOLTS (Yos'
Fig. 9 - Typical n-chann,/ drain characteristics.
,
OIIAiN - TO -SOURCE VOLTAGE IVoSl-V
~
su....,
'IOLTS'VDD . ,
I~
S
10
ZO
:so
40
50
eo
LOAD CAPACITANCE ICLI- pF
Fig. 10 - Minimum p-chennel drain
chafSCfflrinicl.
'JO
eo
IZCS-17""
Fig. 11 - Tvpicallow-to-high la'llll propagation
delay tlms ••• CL •
LOAD CANeITANCE CCL)-,F .lel-ITnl
Fig. 12 - Tvpical high-to-Iow IS'lllI propagation
delay tims ... CL - CD4011A, &
CD4023A.
457
CD4011 A, CD4012A, CD4023A Types
=25°C, CL =15 pF, Input !to, tf-20 nl,
DYNAMIC ELECTRICAL CHARACTERISTICS at TA
RL-200K!l
LIMITS
TEST
CONDITIONS
... 200
D,F,H
CHARACTERISTICS
E
Packages
VDD
Propagation Delay Time:
Low-to-High Level, tPLI-1
High-to-Low Level, tpH L
CD4011A and CD4023A
M
Typ.
Max.
Typ.
Max.
5
50
75
50
100
10
25
40
25
50
5
50
75
50
100
10
25
40
25
50
5
100
150
100
200
10
50
75
50
100
5
75
100
75
125
10
40
60
40
75
CD4012A
Transition Time:
Low-to-High Level, tTLH
High-to-Low Level, tTHL
CD4011 A and CD4023A
5
75
125
75
150
10
50
75
50
100
5
250
375
250
500
10
125
200
125
250
5
-
5
-
CD4012A
I nput Capacitance,. CI
Package
Any Input
UNITS
i
SUPPLY VOLTS
V
I- 5
ns
,0
LOAD CAPACITANCE (CLI-pF
Fig. 13 - Typical high·to-Iow level propagation
delay time vs. CL - CD4012A.
ns
ns
ns
..
ns
AMBIENT TEMpfRATUAEITA)' 2~'C
TYPICAL nMPERATURE COEFFICIENT
FOR ALL VALUES OF" VOO'O.3
,-.,"C
ns
10
so
20
40
50
60
LOAD CAp,t,CITANCE(CLI-pF"
Fig. 14 - Typicallow·to·high transition tim" vs.
pF
CL·
I .....I£NT TElllPEltATUM IT... 1· 25"C
I TYPICAL tEMPERATURE COEFFICIENT FOR
ALL YALUES OF Yoo • 0.5'" j"e
AMBIENT TEMPERATURE ITAI' 25'C
TYPICAL TEMPERATURE COEfFICIENT
FOIl: A,L.L. VALUES Of \'00 '0.3 "IIo/'C
seq
.
SUPPlY VOLTS IYOO'oS
• '00
~
'0
~ 200
• '0
I
30
'0
..
so
LOAD CAPACITANCE (CLI- pF
Fig.
LOAD CAPACITANCE ttll - pF"
Fig. 16 - Typical
15 - Typical high-to-Iow level transition
time vs. CL - CD4011A & CD4023A.
high-to%~~w
SUPPLY VOLTS (Vool
level transition time
Fig.. 17 - Minimum propagation
timB vs. VOD-
vs. CL - CD4012A.
.'ay
AMBIENT TEMPERATURE (TAl' 25 'C
1015
POWER DISSIPATION P'CVOOZf
+ PQUlESCENT
.
v~ ~NPu(Js :~:~U., 'NPUTS
INPUTS
Vss
SUPPLY VOLTSiV
~
::
VOO.VNH IMPUTavoo
OUTPUTS
1'15
10
Vss
'0'
SEOU[NTIALLY.
TO 80TH VOD AND "ss
~;~c:oAE~~~~[D
~E
LOAD CAPACITANCE lCL 1'I~pF"
CL'!>OpF"---
,0'
"'-.ig. 18 - Typical dissipation characteristics.
0 ~
"SS
=-
VNL
~
Voo
~
'-o
Fig. 19 - Quiescent device current
test circuit.
Vss
~~~
TEST ANY ONE INPUT,
WITH OlMER INPUTS AT
9lC'-17400
Veo OR
Vss
Vss·
Fig. 20 - Noise immunity
test circuit.
Fig_ 21 - Inputleak,age current
test CircUit.
458 __________________________________________________________________
CD4013A Types
Dual 'D'-Type Flip-Flop
The RCA-CD4013A consists of two identical,
independent data-type flip-flops. Each flipflop has independent data, set, reset, and
clock inputs, and Q and 0 outputs. These
devices can be used for shift register applications, and by connecting 0 output to the
data input,dor counter and toggle applications. The logic level present at the 0 input
is transferred to the Q output during the
positive-going transition of the clock pulse.
Setting or resetting is independent of the
clock and is accomplished by a high level
on the set (with low-level on reset) or reset
(with low-level on set) line, respectively.
These types are supplied in 14-lead hermetic dual-in-line ceramic packages (0 and
F suffixes), 14-lead dual-in-line plastic
packages (E suffix). 14-lead ceramic flat
packages (K suffix), and in chip form (H
suffix).
V55
MAXIMUM RATINGS, Absolute·Maximum Values:
CD4013A
FUNCTIONAL DIAGRAM
STORAGE·TEMPERATURE RANGE (Tstgl
OPERATING·TEMPERATURE RANGE (TAl,
PACKAGE TYPES O. F. H
PACKAGE TYPE: E:
........... .
OC SUPPLY·VOL TAGE RANGE. (VDDI
IVoltages referenced to VSS Terminal) ......•.......•.......
-55 to +125 0 C
-40 to +8SoC
-0.5 to +15 V
POWER DISSIPATION PER PACKAGE (PDI,
FOR T A = -40 to +60o C (PACKAGE TYPE E I
500mW
FOR TA = +60 to +85 0 C (PACKAGE TYPE E I
Derate Linearly at 12 mW/oC to 200 mW
FOR T A = -55 to +100 0 C (PACKAGE TYPES D. F I
FOR T A = +100 to +125 0 C (PACKAGE TYPES D. FI
500mW
..... Derate Linearlv at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE· TEMPERATURE RANGE (ALL PACKAGE TYPESI . .
INPUT VOLTAGE RANGE. ALL INPUTS.
LEAD TEMPERATURE (DURING SOLDERINGI,
At distance 1/16 ± 1/32 lOch 11.59 ± 0.79 mml from case for 10 s max.
100 mW
-0.5 to V DD +0.5 V
Features:
• Set-Reset capability
• Static flip-flop operation - retains state indefinitel~
with clock level either "high" or "low"
• Medium-speed operation - 10 MHz (typ_) clock
toggle rate at 10 V
• Quiescent current specified to 15 V
• Maximum input leakage of 1 p.A at 15 V
(full package-temperature range)
• 1-V noise margin (full package-temperature
range)
Applications:
• Registers, counters, control circuits
TIUTHU.IU
*·(O~Q'T---"""-------""'-----'
LOGIC
i
o. LOW
LOGIC I. HIGH
10
... LEVEL CHANGE
Ie. DON'T CARE
'HNI' FFt/Ff2 TERalNAL
ASSIGNMENTS
*4(~lo-------~~~--~
S
DD
~
RESET
BUFFERED OUTPUTS
1(13)
Fig.2 - Typical n-channe/ drain char.emf/st;at.
DRAIN - TO - SOURCE VOI..TS IVos'
• AU. INPUTS ARE
PROTECTEO BY
COS'MOS PROTECTION
I~
10
OIWN-TO-SOI..Ra: VOLTS l"osl ,ZCS-I7IOO
-IS
-10
-5
Vss
NETWORK
9ZSS-01'flZ'
-10 ~
.~
GATE - TO -
Fig. 1 - Logic diagram and truth table for CD4013A lone of two identical flip flops).
!
~:
~CE
1';':';' ....
VOlTS IVGS'o -IS
-t
"+rfH
g 1m :i~fUH#!lml}illilOO
.. MSI["IY TEMPERATURE ITA'. 2S"C
tyPICAL TEMPERAtURE COEFFICIENT FOR 10 "-0.3.,.
r
.
:
I·e
Fig.3 - Typical pachannel drain characteristics.
459
CD4013A Types
RECOMMENDED OPERATING CONDITIONS at TA = 250 C, Except as Noted:
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges liMITS
D,F,H
E
Package
Packages
Min.
Max.
Min.
Max.
CHARACTERISTIC
VDD
(V)
Supply·Voltage Range
(For TA = Full Package
Temperature Range)
-
Data Setup Ti me
ts
5
10
'3
12
3
12
40
20
-
50 .
25
tw
5
10
200
80
-
-
fCl
5
10
de
Clock Rise or Fall
Time
trCl·, tfCl
5
10
-
Set or Reset Pulse
Width
5
10
Clock Pulse Width
Clock Input
Frequency
UNITS
V
DflAIN-TO-SOLflCEVOLTSIVOSl
-
ns
-
500
100
2.5
7
dc
1
5
MHz
-
15
5
-
15
5
/.IS
250
100
-
500
125
-
-
Fig.4 - Minimum n-channel drain characteristics.
ns
-
ns
-
• If more than one unit is cascaded in a parallel clocked operation. trCl should
be made less than or equal to·the sum of the fixed propagation delay time at
15 pF and the transition time of the output driving stage for the estimated
capacitive load.
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25o C, Input t r, tt 20 ns,
Cl = 15 pF, Rl -200k.tl
Fig.5 - Minimum p-channel d,a;n characteristics.
g
liMITS
CHARACTERISTIC
VDD
(V)
Propagation Delay Time:
Clock to 0 or Q Outputs
D,F,H
Packages
Min. Typ.
Max.
-
150
75
300
110
175
75
300
110
175
75
300
-
5
10
-
75
50
125
70
5
10
2.5
7
4
10
-
tw
5
10
Minimum Set or Reset
Pulse Width,
tw
5
10
Minimum Data Setup
Time,
ts
5
10
-
Clock Rise or Fall Time
trCl. tfCl
5
10
-
Any
Input
-
5
10
-
E
Package
Min. Typ. Max.
-
UNITS
150
75
350
125
ns
175
75
350
125
ns
175
75
350
125
ns
-
75
50
150
75
ns
-
1
5
4
10
-
MHz
125
50
200
80
-
125
50
500
100
ns
125
50
250
100
-
125
50
500
125
ns
20
10
40
20
20
10
50
25
ns
-
15
5
-
-
-
15
5
/.Is
5
-
-
5
-
pF
-
tpHl, tplH
Set to 0 or Reset to 0
tPlH
5
10
Set to 0 or Reset to 0
tpHl
5
10
Transition Time,
ITHl,lTlH
Maximum Clock Input
Frequency,
fCl
Minimum Clock
Pulse Width,
Average Input
Capacitance,
460
CI
-
110
-
-
Fig.6 - Typical propagation delay time VI. CL'
AMlltlilT TEIIIPDtAT\IfI£ (TAI.u·e
TYPICAL TEWOtATURE COEFFICIENT FOR
ALL VALUES 0' VoooO.''lI.'-C
::::c
.
;
,
;
•
~.
::.::.~:
:::: .::.
o· .. ~~ .. ···~· ...... +
,.
Fig.7:.... Typical transition time
VI.
CL•
CD4013A Types
STATIC ELECTRICAL CHARACTERISTICS
Vo VIN VDD
(VI (VI (VI
Current,
IL Max. -
-
Quiescent Device
Output Voltage:
Low·Level,
VOL
High·Level
VOH
D, F,H Packages
+25
-55
E
+125
-40
Typ.
Limit
5
1
0.005
1
60
10
10
2
0.005
2
120
20
15
25
0.5
25
1000
250
Package
+25
Units
+85
Typ. Limit
0.01
10
20
0.02
2.5
250
~
~ 10
140
280
pA
2500
oTyp.; 0.05 Max.
o Typ.; 0.05 Max.
-
0.5
5
0.10 10
-
5
5 Typ.; 4.95 Min.
0.10 10
10 Typ.; 9.95 Min.
0.5
iI
Limits at I ndicated Temperatures (OCI
Conditions
Characteristic
10
",""LY VOLTSIVool
V
.,
20
Fig.S - Typical maximum clock input
frequency VS. VDO-
Noise Immunity:
4.2
Inputs Low,
VNL 9
-
10
2.25 Typ.; 1.5 Min.
4.5 Typ.; 3 Min.
Inputs High
0.8
-
5
2.25 Typ.; 1.5 Min.
1
-
10
VNH
Noise Margin:
Inputs Low.
4.5
VNML 9
Inputs High,
0.5
VNMH 1
Output Drive
Current:
0.5
N·Channel
0.5
(Sink)
IDN Min.
P·Channel
4.5
(Source)
9.5
IDPMin
I nput Leakage
Current,
IIL,IIH
5
4.5 Typ.;
V
3Min.
AMBIENT TEMPERAYURftT"I-Z5-c
INPUT Ir '., .ZO,..
-
5
1 Min.
-
10
1 Min.
-
5
1 Min.
-
10
1 Min.
-
5
0.65
1
0.5
0.35
0.35
1
0.3
0.24
10
1.25
2.5
1
0.75
0.72
2.5
0.6
0.5
V
~
10
,<>,
rnA
-
5
-0.31 -0.5 -0.25 -0.175 -0.17 -0.5 -0.14 -0.12
-
10
-0.8 -1.3 -0.65
Any
Input
15
-0.45
lOJ
10"
lOS
10.
,.'
INPUT FR£QUENCTif,I-Hz
Fig.9 - Typical dissipation characteristics.
-0.4 -1.3 -0.33 -0.27
±1 0- 5 Typ.; ±1 Max.
pA
VDO
VIX>
INPUTOVIX>
OUTPUTS
YOO·YNH
'--
~
~
Y~
.
1NPOUS
Veo
NOTE'
'---"?'--MEASURE INPUTS
Yoo
o~
SEOUENTIALLY,
TO BOTH YOO AND 'iss'
Vss
CONNECT ALL UNUSm
INPUTS 10 EITHER
YOO ORVSS '
NOTE:
TEST ANY ONE INPUT,
Vss
WITH OTHER INPUTS AT
Voo OR Yss'
INPUTS
Vss
Vss
9zes- 21400
Fig. 10 - Noise immunity test circuit.
Fig. 1 , - Input leakage test circuit.
Fig. 12 - Quiescent device-current test circuit.
461
CD4014A Types
COS/MOS 8-Stage
Static Shift Register
Synchronous Parallel or ,
Serial Input/Serial Output
RECOMMENDED OPERATING CONDITIONS at TA = 25u C. Except as Noted.
For maximum raliability, nominal operating conditions mould be selected so that
operation is always within the following ranges:
LIMITS
VDD
(V)
CHARACTERISTIC
Supply·Voltage Range (For TA= Full
Package·Temperature Range)
D.F.H
Packager
Min. Max.
E
Package
Min. Max.
UNITS
3
12
3
11
V
-
500
100
-
ns
--
B30
200
-
ns
Data Setup Time. ts
5
10
Clock Pulse Width, tw
5
10
350
BO
500
175
Clock Input Frequency, fCl
5
10
dc
dc
1
3
dc
dc
0.6
2.5
MHz
Clock Rise and Fall Time, trCL, ttCl'
5
10
-
-
15
5
-
15
5
/AS
-
..IS cascaded trCL should be made less than or equal to the sum of the transitIon
. . time and
* If more than one Unit
the fixed propagation delay of the output of the driving stage for the e~timated capacitive load.
STATIC ELECTRICAL CHARACTERISTICS
Limits at Indicated Temperature. (oC)
Conditions
D,F,H Pack. . .
E Pack.
Charactaristic
Vo VIN VDD
+25
+25
+125 -40
-55
!VI (V) (V)
Typ. Limit
Typ. Limit
50
5
0.5
5
300 50 0.5
5
Quiescent Device
10 10
1
10
600 100
1
100
Currant I L Max.
15 50
1
50
2000 600
5
600
Output Voltage:
oTyp.; 0.06 Max.
5
5
Low·Level,
10 10
oTyp:; 0.05 Max.
VOL
4.95 Min.; 6 Typ.
0
5
High Level
VOH
Noise Immunity:
Inputs Low,
VNL
Inputs High
VNH
Noise Margin:
Inputs Low,
VNML
Inputs High,
VNMH
Output Drive
Current:
n·Channel
(Sink),
ION Min.
- - - 0
4.2 9
O.B 1
4.6
9
0.6
1
0.6
0.6
p·Channel
(Source):
lOP Min.
Input Leakage
Currant,
IIL,IIH
4.6
9.5
-
10
700
1400
6000
1.5 Min.; 2.25 Typ.
10
3 Min.; 4.6 Typ.
6
10
1.6 Min.; 2.25 Typ.
3 Min.; 4.6 Typ.
5
1 Min.
10
6
10
1 Min.
1 Min.
1 Min.
V
0.16 0.3
0.12
V
V
0.OB5 0.072 0.3
0.26 0.175 0.12
The RCA-CD4014A types are B·stage parallel·
input/serial output registers having common
CLOCK and PARAllELISERIAL CON·
TROL INPUTS, a single SERIAL DATA
INPUT. and individual parallel "JAM" IN·
PUTS to each register stage. Each register
stage is a D·type, master-slave flip·flop. In
addition to an output from stage Ii, "a" out·
puts are also available from stages 6 and 7.
Parallel as well as serial entry is made into
the register synchronous \(1Iith the positive
clock line transition and under control of
the PARAlLEllSERIAL CONTROL input.
When the PARALLEL/SERIAL CONTROL
input is low. data is serially shifted into the
B·stage register synchronously with the positiva transition of the clock line. When the
PARALLELISERIAL CONTROL input is
high, data is Jammed into the 8-stage register
via the parallel input lines and synchronous
with the positive transition of the clock line.
Register expansion using multiple CD4014A
packages is permitted.
These types are supplied in IS-lead hermetic dual-in-line ceramic packages (0 and
F suffixes). IS-lead dual-in-line plastic
packages (E suffix). IS-lead ceramic flat
packages (K suffix). and in chip form (H
suffix).
CL'"
0.6
0.1
O.OB
0.31 0.5
5
·0.1 ·0.16 ·0.08 ·0.066 ·0.06 ·0.16 ·0.05 ·0.04
10
0.26 .0.44 ·0.20
mA
·0.14 ·0.12 ·0.44 ·0.1 ·0.08
±10- 6 Typ.; ±1 Max.
./
./
./
./
0.06 0.06
10
-Ar~Tlt5
IJA
9.96 Min.; 10 Typ.
5
5
Units
+85
CD4014A
FUNCTIONAL DIAGRAM
x
x
x
x
/" 0
./ ,
""
X
IJA
a,
SER. PAR SER 1101·1 PI·n
(INTER·
IN CONTROL
NALI
X
On
,
,
,
,
,
,
, , , ,
0
,
0
0
,
0
0
0
0
0
0
x x
0
X
X
,
On·,
X
X
X
a,
On
0
an"
NC
= DON'T CARE CASE
... = LEVEL CHANGE
NC : NO CHANGE
Fig. 1 - Troth
_Ie.
462 _______________________________________________________________________
CD4014A Types
Features:
• Medium speed operation .•... 5 MHz (typ.) clock
rate at VOO - VSS = 10 V
• Fully static operation
• 8 master·slave flip·flops plus output
buffering and control gating
• Quiescent current specified to 15 V
• Maximum input leakage current of 1 J.IA
at 15 V (full package·temperature range)
• l·V noise margin (full package·temper·
ature range)
App/ications:
• Synchronous parallel input/serial output
data queueing
• Parallel to serial data conversion
• General'purpose register
OYNAMIC ELECTRICAL CHARACTERISTICS atTA = 25°C.lnputtr.!t = 20 ns. CL = 15 pF.
RL
=200 k.n
10
.MIIENT TEMPERATURE IT,,'-2:1'C
ALTERNATING '0'
AND "j' PATTERN
t
•
10'
LIMITS
TEST
CONDITIONS
CHARACTER ISTIC
D.F.H
Packages
VDD Min.
(V)
Propagation Delay Time;
tPLH.tPHL
Transition Time;
ITHL. tTLH
Maximum Clock Input
Frequencv. fCL
Minimum Clock Pulse
Width.tW
Clock Rise & Fall Time;
trCL. t,cL'
Minimum Data Set Up
Time,ts
Average Input
Capacitance, CI
: '0'
£
Package
Typ. Max. Min.
5
-
300
750
10
100
225
5
-
150
300
10
-
75
UNITS
300
1000
100
300
150
400
125
-
75
150
5
1
2.5
-
0.6
2.5
-
10
3
5
-
2.5
5
-
5
-
200
500
200
830
10
100
175
100
200
5
-
15
-
15
-
5
100
500
50
100
10
-
-
5
-
100
350
10
-
50
80
-
Anv Input
-
5
5
-
-
0'1==
Typ. Max.
-
-
~
LOAD tAMCl'llLNC[
--Cl"OpF
ns
ns
(Cll·~pf
Fig. 2 - Typical dissipation characteristics.
MHz
ns
~
.
L
jJS
A
d ,
ns
'0
SlPPLY \/CLTSIVooi
Fig. 3 - Typical clock input frequency
5
-
vs. supply IIoltage .
pF
' ....EHT TE'UUATURE (TA1.0-C
TYPICAL TEMPERATURE COEFFICIENT FOR
ALL VALUES Of "OO.o.s ....
,·c
• If more than one unit is cascaded trCL should be made less than or equal to the sum of the transition time and
the fixed propagation delay of the output of the driving stage for the estimated capacitive load.
PARA.LLEL
INPUT _ 1
PI.]
PARAlLEL
SERIAL
CQNlROL
"
SERIAL
INPUT
10
20
eo
30
40
50
LOAD CAPACITANCE ICLI-pF
Fig. 4 - Typical propagation delBY time
V& load capacitance.
CLOCK
AMIIENT TEMPERATURE "AI- 25"'C
T'tPICAL TEMPERATURE COEFfiCIENT FOR
ALI- VALUES OF Voo·o.S .... ,·.:
I
j: 300
~
"
,.
,
200
:
~ 100
3040!!K)
60
LOAD CAPACITANCE leL I -
Fig. 6 - Typical transition time
capacitance.
Fig. 5 - Logic block diagram.
TO
pF 12CS-17101
liS.
load
463
CD4015A Types
COS/MOS Dual 4-Stage Static Shift Register
'"
With Serial Input/Parallel Output
'
DATA"
The RCA-CD4015A consists of two identical,
independent, 4-stage serial-input!paralleloutput registers. Each register has independent CLOCK and RESET inputs as well as
a single serial OAT A input. "0" outputs are
available from each of the four stages on
both registers. All register stages are D-type,
master-slave flip-flops. The logic level present at the DATA input is transferred into
the first register stage and shifted over one
stage at each positive-going clock transition.
Resetting of all stages is accomplished by a
high level on the reset line. Register expansion to 8 stages using om; CD4015A package,
or to more than 8 stages using additional
CD4015A's is possible.
CLOCIA
.
'"
lIun"
'"
'"
'"
'"
UTA,
'"
These types' are supplied in 16-lead hermetic dual-in-line ceramic packages (0 and
F suffixes), 16-lead dual-in-line plastic
packages (E suffix), 16-lead ceramic flat
packages (K suffix), and in chip form (H
suffix).
'"
CD4015A
FUNCTIONAL DIAGRAM
MAXIMUM RATINGS,Absolute-Maximum Values:
STORAGE.TEMPERATURE RANGE (TUgl . . . . . . . • . . . . . . . . . . • . . . . . • • •.
OPERATING·TEMPERATURE RANGE (T A ):
.......•.•............•.....•.•.• ,
PACKAGE TYPES D, F. H
.
PACKAGE TYPE E
-65 to +150'C
Features:
-55 to +125'C
-40 to +86'C
• Medium speed operation .... ___ . _ .. _
5 MHz (typ.) clock rate at VDD
- VSS= 10V
DC SUPPLY-VOLTAGE RANGE,IVDDI
(Voltagesre'erenced to Vss Terminal). . . . . . . . . . . . . . . • . • . . . • . . . . . . ..
POWER OISSIPATION PER PACKAGE (PDI
FOR T A = -40 to + 6O"c (PACKAGE TYPE E)
FOR TA = +60 to +85"C (PACKAGE TYPE E)
FOR TA
FOR TA
-0.5 to +15 V
.......•..............
500 mW
• . . . • . . . Derate Linearly at 12mWfC to 200 mW
= -55 to + l00'C (PACKAGE TYPES D, Fl.
= + 100 to +125'C (PACKAGE TYPES D, F)
..........••.•.•.•.
500 mW
..••Darate Linearly at 12 mWfC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (ALL PACKAGE TYPES). • . .
100 mW
INPUT VOLTAGE RANGE,ALL INPUTS • . • . . . . . • • . . • . . . • . . . . • • . . . . -0.5 to VDD +0.5 V
LEAD TEMPERATURE (DURING SO'LDERING):
+265'C
At distanea 1116 ± 1132 inch (1.59 ± 0.79 mml fr"m case for 10 sma • . . . . . • . . . . .
D,F, H·
PACKAGES
MIN.
Supply-Voltage Range (For T A = Full
Package-Temperature Range)
3
MAX.
E
PACKAGE
MIN.
12
3
• Quiescent current specified to 16 V
• Maximum input leakage current of 1 j.lA
at 15 V (full package-temperature
range)
.
• 1-V noise margin (full package-temperature range)
Applications:
TRUTH TABLE
LIMITS
VDD
(V)
plus output
• Serial-input!parallel-output data queueing
• Serial to parallel data convenion
• General-purpose register
RECOMMENDED OPERATING CONDITIONS at TA = 2!f'C, Except as Noted.
For maximum reliability; nominal operating conditions should be selected so that
operation is always within the following ranges:
CHARACTERISTIC
• Fully static operation
• 8 master-slave flip-flops
buffering
UNITS
Cl.... 0
R
Ql
Qn
fo
fl
0
0
Qn-1
0
1
0
Ql
Qn-1
Q n (N o CHANGE)
1
0
0
~ X
X
X
MAX.
V
12
.... = LEVEL CHANGE
X = DON'T CARE CASE
Data Setup Time, ts
5
10
350
BO
Clock Pulse Width, tw
5
10
500
175
Clock Input Frequency, fCl
5
10
dc
dc
Clock Rise and Fall Time, trCl, ttcl
5
10
Clock. Reset Pulse Width, tw
5
10
-
500
100
-
-
830
200
1
3
dc
dc
0.6
2.5
MHz
-
15
5
-
-
16
5
j.lS
500
175
-
830
200
-
ns
-
Fig. 1 - Truth I11b/e.
ns
-
ns
*If more than one unit is cascaded trCL should be made less than or equal to the sum of the transition time
and the fixed propagation delay of the output of the driving stage for the estimated capacitive load.
SlF'PLY YOI:-TlCVooI
Fig. 2 - TypiCtlI clod< input freqUBIICY
n. supply voltB!JB_
464 ______________________________________________
~
_______________
CD4015A Types
STATIC ELECTRICAL CHARACTERISTICS
CONDITIONS
CHARACTERISTICS
Vo
(V)
Quiescent Oe\lice
Current. IL Max.
Low Level.
VOL
-55
+25
TYP.
+125
LIMIT
-40
UNITS
+25
TYP. LIMIT
-
5
5
0.5
5
300
50
0.5
50
700
-
-
10
10
1
10
600
100
1
100
1400
15
50
1
50
2000
500
5
500
5000
-
5
5
-
10
10
JJA
o Typ.; 0.05 Max
o Typ.; 0.05 Max
LOAD
V
High level
V OH
Noise Immunity:
-
0
5
4.95 Min.; 5 Typ.
-
0
10
9.95 Min.; 10 Typ.
4.2
-
5
V NL
9
-
10
Inputs High
0.8
-
5
V NH
1
-
10
3 Min.; 4.5 Typ.
4.5
-
5
1 Min.
9
10
1 Min.
0.5
-
5
1 Min.
1
-
10
1 Min.
Inputs Low,
Inputs Low,
V NML
Inputs High,
V NMH
CAPACITA~CE
(CLI- pI'
Fig. 3. - Typical propagation'-deJay time
vs. load capacitance.
1.5 Min.; 2.25 Typ.
3 Min.; 4.5 Typ.
V
Noise Margin:
ALL VALUES OF VOO ·O.3'"4'"C
1
+85
-
Output Voltage:
V IN V DD
(V) (V)
PACKAGE
E
D, F, H PACKAGES
AMBIENT TEMPERATURE (T A J • Z'-C
TYPlCA.L TEMPERATURE COEFFICIENT FOR
I
LIMITS AT INDICATED TEMPERATURES (oC)
AMBIENT TEMPERATURE (TAl • 2~'C
TYPICAL TE"PERATURE COEFFICIENT FOR
..
~
1.5 Min.; 2.25 Typ.
IH
60q ALL VALUES OF '1 00 ' 0_3% I';:
,; 11
-;
::500
t!-:.
:400
: '1!
V
~ 200
I-
100
Output Drive
Current:
N-Channel
LOAD CAPACITANCE (CLl -
(Sink),
0.5
-
5
0.15
0.3
0.12
0.085
0.072 0.3
0.06
0.05
ION Min.
0.5
-
10
0.31
0.5
0.25
0.175
0.12
0.1
0.08
0.5
mA
P-Channel
(Source):
4.5
-
5
IDPMin.
9.5
-
10
Input leakage
-0.1
QF
Fig. 4:- Typical transition time vs
load capacitance.
-0.16 -0.08 -0.055 -0.06 -0.16 -0.05 -0.04
-0.25 -0.44 -0.20 -0.14 -0.12 -0.44 -0.1
-0.08
Any Input
Current,
IIL,IIH
-
1-115
JJA
±10- 5 Typ., ±1 Max.
0"
0"
0,.
--
LOo*.O CAPACITANCE (CLI'15QF
----Cl.5~~11IT
10
101
10
10
INPlJT CLOCK FREOIJENCI' (ICLl--tbuCS_I'fOtIlS
*
0.
Fig. 5 - Typical dissipation characteristic•.
ce.
'.*
0"
0"
4":
ce,
* ALL
Vss ~
INPUTS ARE
PROTECTED BY
COS/MOS PROTECTION
NETWORK
Fig. 6 - Logic diagram.
_______________________________________________________________________ 465
CD4015A Types
DYNAMIC ELECTRICAL CHARACTERISTICS
at TA = 25"C, Input tr, t,=20n8, CL = 15pF, RL = 200 kn
'NPUTOVOO
OUTPUTS
VOO-YNH
CHARACTERISTIC
LIMITS
TEST
CONDITIONS
~
(V)
D,F,H
PACKAGES
E
PACKAGE
UNITS
NOTI[:
Vss
Transition Time;
tTHL' tTLH
Minimum Clock Pulse
Width,'w
Clock Rise & Fall
Time; trCL, tpL'
Minimum Data SetupTime, ts
Maximum Clock
Input Frequency,
fCL
Average Input
Capacitance, CI
nSf ANY COMBINaTION
OF INPUTS
MIN. TYP. MAX. MIN. TYP. MAX.
9tt$-27441
CLOCKED OPERATION
Propagation Delay
Time;
TpLH' TpHL
_
~
=
'o -
VNl.
Fig_ 1 - NO/$e-immunity ""t circuit_
5
10
-
300
100
750
225
150
75
200
100
100
50
300
125
500
175
15
5
350
80
1
3
2.5
5
-
5
5
10
-.
5
10
-
5
10
5
10
5
10
5
10
5
10
-
-
-
300 1000
100
300
150
75
200
100
-
ns
-
100
50
400
150
830
200
15
5
500
100
-
0.6
2_5
2.5
5
-
MHz
-
-
5
-
pF
300
100
750
225
200
100
500
175
-
-
-
-
-
ns
Voo
ns
1NPUOS
Voo NOTE
'--tI"'- o~
MUSURE INPuTS
SEQUENnALLY,
Vss
TO BOTH Voo AND 'Iss
CQNNECT ALL UNUSm
...urs 10 EITNER
.
\fDa OR Yss
j.lS
Vss
ns
Fig_ 8 - Input-leakage-current "'st
circuit.
RESET OPERATION
Propagation Delay
Time,. TpHL
Minimuml
Reset Pulse Width
'w
300 1000
100 300
ns
200
100
ns
830
200
*If mora than one unit is' cascaded trCL should be made less than or equal to 1he sum of the transition time and
the fixed propagation delay of the output of the driving stage for the estlmeted capacitve load.
Test perfonned with the following
,ov
92CS 17909
sequence of ""s" and "0'5"
S,
S2
1
Test
0
Don't Test
0
0
Don't Test
1
0
0
0
Don't Te.t
Don't Test
1
0
Don't Test
0
0
1
0
Test
Don't Test
0
0
Test
1
0
S3
0
1
1
0
0
1
1
0
0
TERMINAL DIAGRAM
Top View
CLOCK B
D• •
03A
02A
0' A
,. I..
I.
DATA B
RESET 8
13
RESET A
"
DATA A
'0
v55
Voo
•
"
•
0'.
02.
03.
Q4A
CLOCK A
92CS-24457
Fig. 9 - Qu;e,c.nt4."ice-current
lelt circuit.
466 __________________________________________________________
~
______
CD4016A Types
COS/MOS Quad
Bilateral Switch
For Transmission or Multiplexing
of Analog or Digital Signals
The RCA·CD4016A Series types are quad
bilateral switches intended for the trans·
mission or multiplexing of analog or digital
signals. Each of the four independent bi·
lateral switches has a single control signal
input which simultaneously biases both the
p and n device in a given switch ON or OFF.
These types are supplied in 14-lead hermetic dual-in-line ceramic packages (0 and
F suffixes). 14-lead dual-in-line plastic
packages (E suffix). 14-lead ceramic flat
packages (K suffix). and in chip form (H
suffix).
Features:
- High degree of linearity: <0.5% distortion
typo @fis = 1 kHz, Vis = 5 Vp•p,
Voo-VSS ;;'10 V, RL = 10 k12
- Extremely low OFF switch leakage resulting in very low offset current and high ef·
fective OFF resistance:
100 pA typo @VDD-VSS= 10 V, TA = 25 0 c
- Extremely high control input impedance
(control circuit isolated from signal circuit:
1012 12 typo
- Low crosstalk between switches:
-50 dB typ. @fis=0.9 MHz, RL = 1 k12
- Matched control·input to signal·output
capacitance:
Reduces output signal transients
- Frequency response, switch ON = 40 MHz
(typ.)
- Quiescent current specified to 15 V
- M;lximum input leakage current of 1 p.A
at 15 V (full package·temperature range)
- 15-V digital or ± 7.5·V peak·to·peak switching
App/ications:
- 280-12 typical ON resistance for 15-V operation
- Analog signal switching/multiplexing
- Switch ON resistance matched to within· 1012
Signal gating
- Modulator
typo over 15·V signal·input range
Squelch control
_ Demodulator
- High ON/OFF output-voltage ratio:
Chopper
- Commutating switch
65 dB typo @ fis = 10 kHz, RL = 10 k12
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following range:
LIMITS
Min.
Max.
CHARACTERISTIC
Supply Voltage Range (For T A = Full Package
Temperature Range)
3
UNITS
12
IN/OUT
.!+-==c--..."
SIG A
FUNCTIONAL DIAGRAM
, CONTROL
VcO-"VV~""'--jr--,
Fig. 1-Schematic diagram - 1 of 4
identical sections.
- Digital signal switching/multiplexing
- COS/MOS logic implementation
- Analog·to-digital & digital·to·
analog conversion
- Digital control of frequency, impedance.
phase, and analog·signal gain
V
TYPICAL "ON" RESISTANCE CHARACTERISTICS
CHARAC·
SUPPLY
TERISTIC' CONDITIONS
vDD
IV)
VSS
(V)
a
RON
+15
RONimax.)
+15
0
RON
+10
0
RONimax.)
+10
0
RON
+ 5
RONimax.)
+ 5
0
RON
+7.5
-7.5
RONimax.)
+7.5
7.5
RON
+ 5
- 5
RONimax.)
+ 5
- 5
RON
+2.5
·2.5
RONimax.!
+2.5
-2.5
* Variation from.a
0
RL - lk!!
VALUE
Vis
IV)
(m
LOAD
CONDITIONS
RL = 10k!!
R..L - lOOk!!
VALUE
VALUE
Vis
Vis
(!!)
(V)
(!!)
(V)
+15'-
200
.,5
200
+15
180
200
a
200
a
200
a
320
+9.2
300
+11
300
+9.3
290
+10
250
+10
240
+10
290
0
250
a
300
0
500
+7.4
560
+5.6
610
+5.5
860
+ 5
470
+ 5
450
+ 5
600
a
580
0
800
0
Uk
+4.2
7k
+2.9
33k
+2.7
200
+7.5
200
+7.5
180
+7.5
200
290
7.5
'0.25
200
280
7.5
'25
180
400
·7.5
'0.25
+ 5
260
+ 5
250
+ 5
240
310
-
5
250
5
240
- 5
600
'0.25
580
'0.25
760
'0.25
590
+2.5
450
+2.5
490
+2.5
720
-2.5
520
·2.5
520
-2.5
232k
'0.25
300k
'0.25
870k
perfect switch. RON
'0.25
I
INPUT SIGNAL VOLTS Iv,sl
,:iCS-HIIO
Fig.2 - Typ. liON" characteristics for 1 of 4
switches with VOD '" +75 V, VSS = 0 V.
Fig.3 - Typ. nON" characteristics for 1 of 4
switches with VOD
= +70 V,
VSS
=0
V.
=on.
467
CD4016A Types
ELECTRICAL CHARACTERISTICS (All inputs. . . . . . . . . . . .
Recommended DC Supply Voltage (VDD-VSSI . . 3to 15 VI
Test Conditions
All Voltage Values
Characteristic
are in Volts
Limits
VOO
(V)
-4cPt. +250 C,+85 DC Apply to E
AM81ENT TEMPERATURE (TA' .
n"c
..
f.
i4
Values at -550 C,+25f'C.""250 C Apply to D,F ,H Packages
Values at
SUPPLY VOLTS,VOOo+!5;Vss·O
VSs<' VI'" VDDI
Package
Unit
+250 C
Typ.
Max.
-55°
_40°
+850
+1250
0.25
0.5
2
-
-
10
20
40
0.25
0.5
2
5
10
20
-
!YJ>!Max Typ/Max
!YJ>!Max
!YJ>!Max
120/360 130/370
120/360 130/370
130/775 1601790
130/600 150/610
130/600 150/610
32511870 37011900
120/360 130/370
120/360 130/370
150/775 180/790
130/600 150/610
130/600 150/610
300/1870 35011900
260/520
2601520
40011080
3401840
3401840
77012380
2601520
2601520
40011080
3401840
3401840
75012380
300/600
3001600
47011230
4001960
4001960
90012600
3001600
3001600
49011230
4001960
4001960
880/2600
200
200
280
250
250
580
200
200
300
250
250
560
660
660
2000
400
400
850
660
660
2000
~
~ 3
e~g 2
Quiescent Device
Current, I L max
(All switches ON
5
10
15
5
10
15
or all Switches
OFF)
O.F.H Pkgs:
E.Y Pkgs.
Signal Inputs (Vis) and Outputs (Vos)
VC=
VSS
Vis
VOO
RL = 10 kn+7.5
+7.5 -7.5 -7.5
iO.25
+5
+5
-5
-5
iO.25
ON Resistance.
+15
RON
+15
+0.25
0
+9.3
+10
+10
0
+0.25
+5.6
RL= 10knb.ON Resistance
Between Any
+7:5 -7.5 ±7.5
2 of 4 Switches
+5
-5
i5
/IRON
+5
Sine Wave
-5
-
-
-
0.25
0.5
2
0.25
0.5
2
INPUT SIGNAL VOLTS {V'S.
~A
Fig. 4 -
Typ. "ON u characteristics for 1 of 4
switches with VDD = +5 V, VSS = 0
v.
~A
400
400
850
\!
INPUT SIGNAL VOLTS tv,S'
Fig.5 - Typ. uON" characteristics for
switches with VDD
-
-
-
-
-
-
10
15
-
!!
-
-
-
-
0.4
-
%
-
-
-
-
40
-
MHi
= +7.5 V,
t of 4
VSS = -7.5 V.
5
P"I)&
Response
RL-l0kll
IDistortion)
fis
=
1 kHz
1~5
I
Frequency Response VOO=+b
VC=V SS=-5 p-p
Switch ON
(Sine-Wave
Input)
-
-
0.01
0.01
0.01
RL=lkl!
,
Vos
20Io91O
V;=
INPUT SIGNAL VOLTS (V'S)
-3d8
+5
-5
switches with VDD
pop
Feedthrough
Switch OFF
Input or Output
Leakage Current
Switch OFF
(Effective OFF
Resistance)
RV 1 kl!
20 10910 Vos
V'
_SOdS IS
-
=
t of 4
VSS = -5 V.
Fig.6 - Typ. ·'ON" characteristics for
-5
-
-
-
1.25
-
= +5 V,
MHz
SUPPLY VOLTS: Voo. + 2.5Y., Vss • -2.5V
AMIENT TENPERA11.R£ (TAJ· 2!5"C
Ve=
VDO VSS
+7.5 7.5
+5
-5
±7.5
i5
-
-
-
-
-
itOO
-
IOxl0- 3 ±125'"
pA
nA
;£-
,;v,.~~
,
'="
RL
o
I
2
3
INPUT SIGNAL VOlTS (VIS'
Fig.7 - Typ. "ON" characteristics for 1 of 4
switches with VDD = +2.5 V, VSS = -2.5 V.
468 __________________________________________________________________
CD4016A Types
ELECTRICAL CHARACTERISTICS
(Cont'd)
0
0
0
0
0
0
0
0
0
0
0
VSS';;; VI';;; VOO)
Recommended OC Supply Voltage (VOO-VSS) 0 03 to 15 V)
TIll Condition.
Characteristic
All Voluoge Values
are in Volts
VOO
IVI
Limiu
Valuesat-55"C,+25"C,+125"C Apply to D,F,H Packages
Values at -4d'C,+25"C, +85?C Apply to E Package
-55°
-400
-
-
+85°
+125°
-
-
Unit
+25o C
Typo
Max,
0.9
-
VCI A )"VOO=·5
Crosstalk Between
Any 2 of 4
Switches
If' -50 dB)
VCIB)=VSS=-5
VislAI ' 5 p.p
RL" kll
Vc:
Propagation
Delay (Signal
Input to
Signal Output) tpd
Capacitance :
Input,Cis
Output,Cos
Feedthrough,Cios
MHz
Vasl B)
20lagl0VislA) =
-50 dB
~JlO
INPUT SIGNAL VOLTS (VI,I
Fig.8 - Typ. nON n characteristics as a function of
temp. for t of 4 switches with VOO = +5 V,
VOO
5
VSS ' GNO
C L = 50 pF
Vis = 10 Sq.
Wave
tro tf = 20 ns
VSS=·5 V.
20
10
VOO'+5
VCC'VSS=-5
10
-
-
-
-
-
4
4
0.2
O.2min
O.5min
2.4max
1.5
50
25
ns
-
pF
2.7
V
ControllVel t
Switch Threshold
Voltage, VTH
Vis';;VOO,lis= 101JA O.7min
VOO·VSS= 15,1 0,5 2.9max
Input leakage
VOO
Vis~VDD
'15
VC-l0 ISq.Wave)
t r .tf=20 os VOO
RL'10k!! '10
Current, II L max
Crosstalk
(Control Input
to Signal Output)
Turn-On
Propagation Delay.
tp de
Maximum
Allowable Control
Input Repetition
Rate
VOO-VSs=10 VOO
5
Vc =10
ISee F ig.251 10
tr .tt=20 ns
CL "15 pF
RL' 1 k!!
-
-
-
! 10- 5 typ; ±1 max.
pA
-
-
-
-
50
-
-
-
-
-
20
10
40
20
IlS
-
-
-
-
10
-
MHz
-
-
-
-
5
-
pF
mV
Fig.9 - Typ. feedthru vs. frequency - switch
VOO'lO,
VSS'GNO
RL =1 kll,
CL=15pF
VCC,lOISq.Wave)
Ir,lf - 20n5
Av.lnput
Capacitance, CI
-
-
'" Limit determined by minimum feasible leakage current measurement for automatic testing .
.& Symmetrical about 0 volts.
• For all test conditions.
t All control inputs protected by COS/MaS protection network.
"DFF".
i
I~_
t
:r
INPUT SIGNAL FREQUENCY 11,,1- kHI
Fig.
to -
Typical crosstalk between switch
circuits in the same package.
VD~..r-\...vc-Voo
voo
',,'t- ZOn•
v"
10
.n
ALL UNUSED TERMINALS
ARE CONNECTED TO
Fig. 11 -' Typical switch frequency response
- switch uON u•
IIss
Fig. 12 - nOFFu switch input or output
leakage current test circuit.
ALL UNUSED TERMINALS ARE
CONNECTED TO Vss
Fig. 13 - Test circuit for square-wave
response.
469
CD4016A Types
SCALE: X'" 0.2 ms/DIV Y = 2.0 V101V
SCALE; X = 0.2 msiDIV y .. 2.0 V/DIV
Voo" vC" +7.5V, Vss" ·7.5V. RL" 10K!}
CL-15 p F
flS=lKHz V,s"SVp-p
DISTORTION c 0.2 %
.
-----\
~
\
\~
/
SCALE
Fig. 16 - Typical square wave response at
Fig. 15 - Typical sine WBve response of VDD
+2.5 V, VSS = -2.5 V.
··i~t"Cl~,
2 V DIV
VOO= Vc=+15 V, VssgGnd.
PLUGGED IN TEST
FIXTURE)
Vas FIXTURE A L O N E ' /
INO UNIT
TERM
5 TO J Of SOCKET!
Vc' IOV PER DIV
Vos - 0 2V PER DIV
I 1000sPERDIV
ALL UNUSED TERMINALS ARE
CONNECTED TO Vss
92C5-27&17
=
Vas WITH TEST UNIT
11 SWITCH OF CD4016A~
X, 100"s Drv
v-
92CS-27618
Ib)
la)
Fig. 17 - Typical square wzrw response.t VOO
= VC=+5 V, VSS· Gnd.
Fig. 78 - Crosstalk-control input to signal output.
SWITCH THRESHOLD YQLTAGE IS DEFINED
ALL UNUSED TERMINALS
ARE CONNECTED 10
AS THE YDLTAlE APPLIED 10 A TRANS-
'Iss
MISSION GATE CONTROL WHICH CAUSES
ID,.A OF TRANSMISSION GATE CUIIENT_
ALL UNUSED TERMINALS ARE
CONNECTED TO VSS
Fig. 19 - Propagation delay time signal input
(VISI to signal output (Vosl.
X - 100 IIi DIV
V-50VOIV
92CS-27615
92C5-27614
92C5-27612
Fig. 14 - Typical sine wave response of VDD =
+7.5 V, VSS = -7,5 V.
SCALE
VOO" VC" +2.5V. VS5" -2.SV. RL" 10Kn
CL'" 15pF
'IS" 1 KHz VIS = 5V pop
DISTORTION" 3 %
Fig.20 - Max. allowable control-input
repetition rate.
Fig.21- Switch threshold voltage.
MAXIMUM RATINGS, Absolute·Maximum Values:
STORAGE·TEMPERATURE RANGE (Tstgl
-66 to +1500 C
OPERATING·TEMPERATURE RANGE (TAl:
PACKAGE TYPES D. F. H
PACKAGE TYPE E
DCSUPPLY·VOLTAGE RANGE. (VDDI
-55 to +125 0 C
-40 to +85 0 C
ME'AlUftED ON BOONTON CAPACITANCE
illiDGE: MODEL TBA U ...IJ
-0.5 to +15 V
(Voltages referenced to V SS Termmal) .
POWER DISSIPATION PER PACKAGE (Po'
SOOmW
FOR T A = -40 to +600 C (PACKAGE TYPE E I
FOR TA = +60 to +85 0 C (PACKAGE TYPE E I
FOR T A= ~55 to +100 o C (PACKAGE TYPES D. F. )
FOR T A = +10010 +125 0 C (PACKAGE TYPESD. F.l.
Derate Lonearly at 12 mW/oC to 200 mW
Vc--5V
Vu--5V
'IDO-.5Y
500mW
Derate Lonearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE·TEMPERATURE RANGE (ALL PACKAGE TYPESI.
INPUT VOL TAGE RANGE. ALL INPUTS
LEAD TEMPERATURE (DURING SOLDERINGI:
At dIStance 1116 ± 1/32 ,nch (1.59 ± 0.79 mml from case for 10 s max.
ALL UMIIED TERlllNALI
ARE CONNECTED TO 'ISs
100 mW
-O.S to V DD +O.S V
Fig.22 - Capacitance CIOS and COS.
470 __________________________________________________________________
CD4017 A Types
COS/MOS De.cade
Counter/Divider
its zero count. Use of the Johnson decade
counter configuration permits high speed
operation, 2·input decimal decode gating,
and spike·free decoded outputs. Anti·lock
gating is provided, thus assuring proper
counting sequence. The 10 decoded outputs
are normally low and go high only at their
respective decimal time slot. Each decoded
output remains high for one full clock cycle.
A CARRY.QUT (COUT) signal completes
one cycle every 10 clock input cycles and is
used to clock the succeeding decade directly
in a multi-decade counting chain.
Plus 10 Decoded Decimal Outputs
The RCA-CD4017A consists of a 5·stage
Johnson decade counter and an output decoder which converts the Johnson binary
code to a decimal number. Inputs include a
CLOCK. a RESET, and a CLOCK INHIBIT
signal.
The decade counter is advanced one count at
the positive clock signal transition if the
CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited
when the clock INHIBIT signal is high. A
high reset signal clears the decade counter to
"0"
","
CLOCK: 14
CARRY
OUT
92CS·25072 R2
CD4017A
FUNCTIONAL DIAGRAM
Features:
• Synchronous decade counter plus 10 decoded outputs
• Fully static operation
• Medium speed operation ...
... 5 MHz !typ.) at VDD - VSS = 10 V
. . . • • . • • • . . • • • • . • • . . • • . . • • • -65to+150'C
OPERATING·TEMPERATURE RANGE (TA):
PACKAGE TYPE
-55 to +125'C
-40 to + 85'C
E
• Quiescent current specified to 15 V
• Maximum input leakage current of 1 JlA
at 15 V (full package-temperature range
range)
• 1-V noise margin (full package-temperature range)
DC SUPPLY·VOLTAGE RANGE (VDD)
(Voltages referenced to VSS Terminal) . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . ~.5 to +15 V
POWER DISSIPATION PER PACKAGE (PO):
FOR T A
=-40 to +60'C (PACKAGE TYPE
= +60 to +85'C (PACKAGE TYPE
FOR T A
= -55 to
FOR T A
E)
. • • . . . • . • . . • . . . . . . . . • . • • . 500mW
Ell
. . . . . . Derate Linearly at 12 mW;C to 200 mW
100'C (PACKAGE TYPES 0, F)
FOR TA = +100 to +125'C IPACKAGE TYPES 0, F.)
. . . . . . . . . . . . . . . . . . . . . . . 500mW
Applications:
... Derate Linearlv at 12 mWfC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR. TA
= FULL PACKAGE-TEMPERATURE RANGE
INPUT VOLTAGE RANGE, ALL INPUTS
10 "4"
"ss ~ 8
These types are supplied in l6-lead hermetic dual-in-line ceramic packages (D and
F suffixes). l6-lead dual-in-line plastic
packages (E suffix). l6-lead ceramic flat
packages (K suffix), and in chip form (H
suffix).
PACKAGE TYPES D. F, H
"3"
RESET I!!
\loo~ 16
MAXIMUM RATINGS, Absolute-Maximum Values:
STORAGE·TEMPERATURE RANGE (Tstg )
"2"
eLOCI( 13
INHIBIT
•
•
•
•
Decade counter/decimal decode display
Frequency division
Counter control/timers
Divide by N counting
N =2 - 10 with one CD4017A and one
one CD4001A
N> 10 with multiple CD4017A's
• For further application information, see
ICAN-6166 "COS/MaS MSI Counter
and Register Design & Applications"
(ALL PACKAGE TYPES) •.•.••• 100 mW
. • • . . • . • . . . . . . • . . . • . . . • • . -C.5 to VDD +0.5 V
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 105 max. . . . . . . . • • . • • •.
+265°C
CLOCK
CLOCK IN HIBIT
"0"
*ALl. INPUTS ARE
"I"
PROTECTED BY
COSIMOS PROTECTION
"1'
NETWORK
"]"
"'" ________
Tt •• IN ..... MO ,.GIID.¥SS
n:.......LND·I6·¥OD
~GI~
___________________
________________
"5"
----------jr,t~
"6"
______________
"7"
______________
"8"
__________________
"9"
jGl~
________________
~r,I~
___________
-'r,;~
___________
~::::::::::=t========~r;;~.~:::::::::;,
CARRY OUT
Fig. 1 - Logic diagram.
Fig. 2 - Timing diagram.
471
CD4017 A Types
STATIC ELECTRICAL CHARACTERISTICS
LIMITS AT INDICATED TEMPERATURES (oCI
CONDITIONS
CHARACTERISTICS
Quiescent Device
Current, IL Max.
Output Voltage:
Low· Level,
VOL
High Level
VOH
Noise Immunity:
Inputs Low,
Va
(VI
VIN
-
-
4.2
Inputs L~
VNML
9
Inputs High,
0.5
VNMH
1
+25
TYP.
LIMIT
+125
-40
LIMIT
0.5
50
700
0.3
5
300
50
10
10
0.5
10
600
100
1
100
1400
15
50
1
50
2000
500
5
500
5000
'----"i'-pA
VDD ORVSS·
10
o Typ.; 0.05 Max.
0
5
4.95 Min.; 5 Typ.
0
10
9.95 Min.; 10Typ.
-
IDN
Min
0.5
-
Decoded
4.5
-
Outputs
9.5
-
Cerry
Outputl
4.5
-
Carry
Output
0.5
0.6
5
VS5
V
lOP
9.5
Input Leakage
Current,
IIL.IIH
Fig. 10 - Input-leakage-current test circuit.
1.5 Min.; 2.25 Typ.
10
3 Min.: 4.5 Typ.
V
5
1.5 Min.; 2.25 Typ.
10
3 Min.; 4.5 Typ.
5
1 Min.
10
1 Min.
5
1 Min.
10
1 Min.
V
-
5
0.06
0.1
0.05
0.035
0.03
0.1
0.025
OUTPUTS
0.12
0.4
0.1
0.07
0.085
0.4
0.07
0.065
5
0.185
0.4
0.15
0.105
0.095
0.4
0.08
0.065
10
0.45
I
0.35
0.25
0.3
1
0.25
0.2
5
0.0375 -0.075 -0.03
10 f-o.12
5
10 f-o.45
15
-0.2
0.185 -0.4
-1
-..!:@
V:L
0.02
10
Tlnr
-
UTOVOO
I ••
P·Channel (Source)
Min
TO BOTH YoD AND Yss-
Vss
VOD-t0.5
MUSURE INPUTS
S[OIJ£NTIALLY.
o ~
CONNECT ALL UNUSED
N'UTS TO EITHER
Output Drive
Current:
N-<:hannel (Sink)
Decoded
Outputs
1 N P OVDO
U S NOTE'
VDO
5
10
-
+85"
TVP.
5
o Typ.; 0.05 Max.
-
0.8
-55
UNITS
E PACKAGE
+25
5
1
Inputs High
VDD
(VI
5
4.5
9
VNH
-
-
VNL
Noise Margin
(VI
D. F, H PACKAGES
,1:
NOTI:
Vss
mA
Fig. 11 - Noise-immunity test circuit.
-0.021 -0.018 -0.075 -O.ot5 -0.012
-0.1
-0.07
-0.085 -0.2
-0.07
-0.15
-0.1 Q!, 1-0.095 -0.4
-0.08
-0.066
-0.35
-0.25
-0.24
-0.20
-0.3
-1
±1cr 5 Typ .• ±1 Max.
-0.065
pA
When the Nth decoded output is reached
(Nth clock pulse) the S·R flip flop (con·
r-~--------~------------·~:~~6
structed from two NOR gates of the
I: CLOCI( N
CD4001A) generates a reset pulse which
clears the CD4017A to its zero count. At
this time, if the Nth decoded output is
+-,==__+--"-","",,,,,,==__+-.~~ENR~~~~:~T greater than or equal to 6, the CoUT line
goes high to clock the next CD4017A
counter section. The "0" decoded output
also goes high at this time. Coincidence of
the clock low and decoded "0" output low
resets the S·R flip flop to enable the
CD4017A. If the Nth decoded. output is
I
,
less than 6, the COUT line will not go high
L ___________________ J
92SS-4537R1
and, therefore, cannot be used. In this case
"0" decoded output may be used to perform
Fig. 12 - Divide by N counter IN .. lOJ with N
the clocking function for the next counter.
decododoutpulS.
~
,·CLOCK~N
472
~N~':JriOMIIN'TION
tZ:CS-2M4.
CD4017 A Types
RECOMMENDED OPERATING CONDITIONS at TA = 25·C, Except as Noted.
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges:
LIMITS
CHARACTER ISTIC
VDD
(VI
D, F,H
PACKAGES
MIN.
MAX.
E
PACKAGE
MIN.
UNITS
MAX.
LOAD CAPACITANCE ICLI- pF
Supply Voltage Range (For TA=Full
Package·Temperature Range)
3
12
3
12
V
Fig. 3 - Typical'prop8gation delay time
VI.
CL for decodod outputs.
-
830
250
-
1
3
dc
dc
0.6
2
MHz
-
15
15
-
15
15
JJ.s
5
10
500
165
-
-
830
250
-
ns
5
10
750
225
-
1000
275
-
500
200
Clock Pulse Width, tw
5
10
500
170
Clock Input Frequency, fCl
5
10
dc
dc
Clock Rise or Fall Time, trCl, tfCl
5
10
-
Reset Pulse Width, tw
Reset Removal Time
ts
-
700
300
5
10
Clock Inhibit
Setup Time,
-
ns
-
ns
LOAD CAPACITANCE cell -
ns
-
pF
Fig. 4 - Typical propagation delay time ... CL
for carry output.
n,,)_uec
AMIIEIIIY T£MPlRATlII'IE
TYPltAL TEMPERATURE COUFICIENT '0"
ALL VALUES Of "00.0.:5 ..
,·e
L
A
d,
.. ,.
t· :·
r•
10
Sl.FPLT VOLTSIYooI
Fig. 5 - Typ'c.' tTBn.itlon tim• ... CL for
d_dod outputs.
Fig. 6 - Typical transition time
1fS'.
CL for
15
Fig. 7 - Typical clock input frequency w. VOD.
carry output.
Test performed with the followIng
sequence of ",', and "O's" at Bach switCh •
•<>
I.f-!.!~ __ .,
'
Q;s IL ___________ .JI
DIVIDE BY 3
CD401lA
,----------i
1/2
-,
~
I
I
CONNECTED BACK TO -DATA(SKIPS "AL.L.-rs" STATE)
02 I
I
L __________ J
92CS-1707rR2
_
92SS-4148R2
,
,I
I
CONNECTED BACK TO ·DATA~
_
I
(SKIPS "AL.L.- r," STATE)
,
Fig. 2 - Timing diagram.
I
I
ill.
... 4 IL ___________ JI
-i-'
+-
CONNECTED BACK TO -DATA(SKIPS -ALL.-I"" STATE)
DIVIDE BY 1
1/2 CD401lA
DON'T CARE UNTIL "PRESET"" GOES HIGH
1-1-
REQUI REO
0,
~
Jam3
NO EXTERNAL
Fig. 3 - External connections for divide by 10,
9, 8, 7, 6, 5, 4, 3, 2 operation.
475
CD4018A Types
MAXIMUM RATINGS, Absolute-Maximum Values:
STORAGE-TEMPERATURE RANGE (Tstg ) . . . . . . . . . . . . . . . . . . . . . • . . • . . . .-65 to +150 oC
OPERATING·TEMPERATURE RANGE ( T A ) : '
0
PACKAGE TYPES D.F, H
. . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . •-55.0+125 0 C
PACKAGE TYPE E
. . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . -40'0 +85 C
DC SUPPLY-VOLTAGE RANGE. (VDD)
(Voltages referenced to VSS Terminal): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +16 V
POWER DISSIPATION PER PACKAGE (PD)
FOR TA= -40 to +60 DC (PACKAGE TYPE E)
. . . • . . . . • . . • . . . . . . . . . • • . • • • . 500 mW
FOR T A= +60'0 +85 DC (PACKAGE TYPE E)
. . . . . . . . .De,.'e Lineerly.t 12 mWIDC to 200 mW
FOR T A= -55 to +1 OODC (PACKAGE TYPES D. F) . . . . . . . . . . • • . • • • . • • . • . • • • 500 mW
FOR TA= +100'0 +125°C (PACKAGE TYPES D. F)
. . . • . De,••• Linee,ly.t 12 mW/oC'o:ZOO mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA= FULL PACKAGE·TEMPERATURE RANGE (ALL PACKAGE TYPES) . . . . • • • • . 100 mW
INPUT VOLTAGE RANGE. ALL INPUTS . . . • • . . • . . . . • . . . . . . • . . . . • . -0.5 to VDD +0.6 V
LEAD TEMPERATURE (DURING SOLDERING):
A. distance 1116 ± 1132 inch (1.59 ±0.79 mm) f,om case for 10 s max . . . . . . . . . . . . . . • . +265°C
LOAD C....... CtTAMeE
eeL.' -
pF
Fill- 4 - Typical propllfllltion dtllay time v••
'oad capacitance for decoded outputs.
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C, Input t r , tt = 20 n.,
CL = 15 pF, RL =200 ill
LIMITS
CHARACTERISTIC
TEST
CONDITIONS
VDD
(VI
E
D,F,H
Packsges
UNITS
Package
Min: Typ. Mm._ Min_ Typ. MaX_
CLOCKED OPERATION
Propagation Delay Time;
tpLH, tpHL
5
-
350
1000
-
350
1300
10
-
125
250
-
125
300
500
200
1200
400
-
500 1600
200 500
100
300
-
100
50
150
-
50
200
300
125
2.5
900
350
-
300
125
2.5
1200
450
Fig. 5 - Typical propagation delay tims VI,
To 05 Output
5
10
To Other Outputs
Transition Time;
tTHL,tTlH
To 05 Output
5
10
5
10
5
To Other Outputs
Maximum Clock Input
Frequency, fCl
10
5
Min. Clock Pulse Width,
tw
10
5
Clock Rise & Fall Time;
trCl, ttC l
-
1
3
-
5
200
100
-
-
-
0.6
-
2
5
200
170
15
-
100
-
-
350
830
250
15
175
75
300
-
-
5
-
350
1000
-
350
1300
-
125
250
-
125
300
-
1200
400
500
200
5
-
200
500
200
830
10
-
100
100
300
250
300
165
750
1000
100
225
-
1600
-
500
200
100
275
-
175
-
75
200
-
5
5
-
To 05 Output
10
To Other Outputs
5
10
M in. Preset or Reset
Pulse Width
.10
Any Input
ns
ns
I~t~
TYPICAL TEMPERATURE COEFFICIENT I'OR
ALL VALUES OF' Voo'O ,,.,,·e
I~. I:~,:::~h
I~
Il~~~;;:
MHz
15
700
10
5
Min. Data Input Set-Up
Time, t5
-
10IId capacitance for aS output.
ns
AMBIENT TEMPERATURE ITA) .25"C
500
15
500
Average Input
Capacitance, CI
LOAO CAPACITANCE ICL.'-pF
ns
II
30
LO~D
p.s
""
CAPACITANCE ICLI-pF
Fig. 6 - Typical transition time
VI.
load
capacitBnce for dt1Coded outputs.
ns
pF
PRESET* OR RESET OPERATION
Propagation Delay Time:
tplH' tpHl
tw
Min: Preset or Reset
Removal Time
5
10
ns
500
10
20
30
40
~o
10
'70
.0
LOAD CAPACITANCE 1CL.'- pF
ns
Fig. 7 - Typical trtm.ition tim. VI. 103d
capacItance for 06 output
• At PRESET ENABLE OR JAM Inputs.
476 __________________________________
~---------------------------
CD4018A Types
RECOMMENDED OPERATING CONDITIONS at TA =25 DC, Except as Notad.
For maximum reliability, nominal operating conditions should be salactad so that
operation is always within the following ranges:
liMITS
VDD
CHARACTERISTIC
E
Package
D,F,H
.!VI
Packsges
Supply·Voltage Range (For T A = Full
Package·Temperature Rangel
UNITS
Max.
Min.
Max.
3
12
3
12
V
500
200
700
300
-
ns
830
250
-
ns
5
10
500
170
-
Clock Input Frequency, fCl
5
10
de
de
1
3
de
de
0.6
2
MHz
Clock Rise and Fall Time, trCl, ttcL
5
10
-
15
15
-
15
15
p.s
Preset or Reset Pulse
Width, tw
5
500
830
10
165
5
10
750
225
-
-
5
10
Data Setup Time, ts
Clock Pulse Width, tw
Preset or Reset Removal Time
-
250
1000
275
-
! •
L
g
Min.
d ,
,.
....u 'oQ.TS(VooI
neS-ISlir
Fig. 8 - Typical maximum input clock
frequ.ncy ... supply voltage.
10
AMalEHT T[MPERATURE ITA!'Ol!!I'C
INPUT'r'I,'20n'
."
ns
LOAD CAPACITANCE ,CLI'I!lIIF
--CL"!lOpF
ns
-
10
10!
IOl
I'*'UTClOCI( FREQUENCY UCLI-Utz
10t2CS-17U9111
Fig. 9 - Typical di$Sipation charsctBristics
VDD'~PUlO"-~
STATIC ELECTRICAL CHARACTERISTICS
Characteristic
- -
Quiescent Device
Current IL Max.
Outpu, Voltage:
Low Level.
VOL
High Level
VOH
Noise Immunity.
Inputs Low,
VNL
Inputs High
VNH
Noise Margin:
Inputs Low,
VNML
InpulS High.
VNMH
Output Drive
Current:
"-Channel
(Sink)
ION Min.
p·Channei
(Source)
lOP Min.
Vo VIN VOO
(VI (VI (VI
Q5
u,.02
chC4
Q5
~1.~2
Q3.C4
-55
5
10
50
+25
Typ.
Limit
0.3
0.5
1
5
10
50
+125
-40
300
600
2000
50
100
500
-
-
5
10
15
5
5
o Typ.; 0.06 Max.
-
10
10
-
0
0
5
10
o Typ.; 0.05 Max.
4.95 Min.; 5 Typ.
9.95 Min.; 10 Typ.
4.2
-
5
1.5 Min.; 2.25 Typ.
9
0.8
1
-
10
5
10
3 Min.; 4.5 Typ.
1.5 Min.; 2.25 Typ.
3 Min.; 4.5 Typ.
-
4.5
-
5
9
0.5
1
0.5
0.5
-
10
0.5
0.5
4.5
9.5
4.5
9.5
I"put Leakage
Current.
'lL. "H Max.
E Pack.
D. F.H pack• •
-AT
-
-
-
-
-
0.18
0.4
0.45
1
0.06
0.1
0.25
0.4
5 ·0.185 ·0.4
10 ·0.45
·1
5 ·0.075 ·0.15
10 ·0.25 ·0.4
~T\5
0.6
1
5
60
100
500
Unlto
NOTE;
+86
700
1400
5000
Fig. 10 - Noise-immunity test circuit
IJA
5,
0.15
0.35
0.05
0.2
·0.15
·0.35
·0.06
·0.2
±10-5 Typ .• ±I Max.
Telt performed with
the following sequence
of "1's" and "0'1" at
each switch.
V
V
lMin.
1 Min.
1 Min.
0.105 0.095 0.4
0.3
1
0.25
0.035 0.03
0.1
0.4
0.14 0.18
·0.105 ·0.095 ·0.4
·0.25 ·0.3
·1
·0.04 ·0.035 ·0.15
·0.14 ·0.18 ·0.4
V
0.08
0.25
0.025
0.15
·0.08
·0.25
·0.03
·0.15
~SJN~NU;~ONIIN"TION
vSS
92CS-27441
1 Min.
5
10
5
10
5
10
+26
Typ. Limit
l
V:L
Limits.t Indlcatod T.mporotu... (oCI
Condition.
0.065
0.2
0.02
0.12
mA
·0.085
·0.2
·0.024
·0.12
IJA
5, 52 53 54 55 56 57
00000
1 1 1 0 0 1
1 0 I 0 1 1 1
0
0 0
0 0
0 1 0 0
.".
0
9lCS'11'J13AI
1 0 0
1 I 0
0 0 0
0 0 0
0 0 0 0 0 0 0
1 0 0 0 1 0 0
0 0 0 0 0 1 0
0 0 0 0 0 0 0
Fig. 11 - Quiescent-device-curfllnt trlst circuit.
Voo
·'D
?-0Vss
NOTE:
MEASURE INPUTS
SEQUENTIALLY,
TO 90TH "'DO AND Vss'
CONNECT ALL UNUSED
INPUTS TO EITHER
Voo CRVSS '
vss
1=.[g. 12 - InpuNeakage-current test circuit.
477
CD4019A Types
COS/MOS Quad AND/OR Select Gate
Features:
• Medium-speed operation, ••••
'" tpHL = tpLH 50 ns (typ.) at CL = 15 pF,
=
The RCA·CD40 19A types are comprised of
four AND/OR select gate configurations,
each consisting of two 2·input AND gates
driving a single 2·input OR gate. Selection
is accomplished by control bits Ka and Kb.
In addition to selection of either channel A
or channel B information, the control bits
can be applied simultaneously to accomplish
the logical A + B function.
VDD= 10V
• Quiescent current specified to 15 V
• Maximum input leakage current of 1 IJA
at 15 V (full peckage·temperature range)
• 1-V noise margin (full package·temper·
ature range)
Applications:
These types are supplied in 16-lead hermetic
dual-in-line ceramic packages (D and F
sufiixes), 16-lead dual-in-line plastic package (E suffix), 16-lead ceramic flat package
(K suffix), and in chip form (H suffix).
CD4019A
FUNCTIONAL DIAGRAM
• AND·OR select gating
• Shift·right/shift·left registers
• True/complement selection
• AND/OR/Exclusive·OR selection
MAXIMUM RATINGS, AbsolulB-Maximum Values:
STORAGE·TEMPERATURE RANGE IT stg ) . . . . . . . . . . . . . . . . . . . . . . . • . . .-65 to +1500 C
OPERATING· TEMPERATURE RANGE ITA):
PACKAGE TYPES 0, F. H . . . . . . . . . . • . • . . . • . . • . . • . . . . . . • . . . •-55 to +125 0 C
PACKAGE TYPE E . . . . . . . . . . . . . . . . . . . . . . . . . . • . . • . • . . . . . • -40 to +85oC
DC SUPPLY·VOLTAGE RANGE. IVDD)
(Voltages referenced to VSS Terminal): . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +15 V
POWER DISSIPATION PER PACKAGE IPD)
. . . . . . . . . • • • . . . . . . . . . • . . . 500 mW
FOR T A = -40 to +600 C IPACKAGE TYPE E)
FOR TA = +60 to +85 0 C IPACKAGE TYPE E I
. . . . . . Derate Linearly at 12 mW/oC to 200 mW
o
FOR TA = -55 to +100 C IPACKAGE TYPES 0, F)
. . • • . • . . . . . . . • • . • • . • • • 500mW
0
FOR TA = +100 to +125 C IPACKAGE TYPES D. F)
... Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE·TEMPERATURE RANGE IALL PACKAGE TYPES) . • . . . • . 100 mW
INPUT VOLTAGE RANGE. ALL INPUTS . • . . • • . . • • . • . . . . . . . • . . • • -0.5 to VDD +0.6 V
LEAD TEMPERATURE lOURING SOLDERING):
At distance 1116 ± 1132 inch 11.59 ±0.79 mm) from case for 10. max . • . • . . . . • . • • • • +2650 C
Fig. 2 - Typical propllfllltion ""'.y time v..
loed c_ltallCll.
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that
operation is alwavs within the following ranges:
LIMITS
CHARACTE R ISTIC
,Supply. Voltage Range (For TA = Full
Package·Temperature Range)
VDD
(VI
D,F,H
PackBgIII
Min.
Max.
3
12
E
PackllflB
Min. Max.
3
12
UNITS
'04050607010
LOAD CAPACITANCE teL1- pF
Voo
*
A,
o----t---,
Fig. 3 - Typical transition time vs. loed
capacitance.
AOD
:::
~~~lss
-ALL INPUTS ARE
I
PROTECTED BY
COS/MOS PROTECTION
. . . .L'I"'IOLTSCVDD'
NETWORK
Fig.
t-
Schematic diagram for 1 of 4 identicalltllgll8.
Fig. 4 -MBJCimumpropBf/lltion ""'ay tim. vs.
IUpply .oltBf/ll.
478 _______________________________________________________________
CD4019A Types
STATIC ELECTRICAL CHARACTERISTCS
~.
limits at Indica1lld Temperatures (oC)
E Package
D,F,H Pack/lf/lls
Units
Char8C1Briltic
Vo VIN VDD
+25
+25
+85
-55
+125 -40
(V) (VI (V)
Typ. limit
Typ. Limit
300
50
0.1
50 700
5
0.03
5
5
Ouiescent Device
600 100 9·2 100 1400 JlA
10
10 0.05 10
Current,l l Max.
500 5000
15
1
5
50
50 2000 500
."
Condition.
Output Voltage:
Low·Level,
VOL
High Level
VOH
Noise Immunity:
Inputs Low,
VNL
Inputs High
VNH
Noise Margin:
Inputs Low,
VNML
Inputs High,
VNMH
Output Drive
Current:
n·Channel
(Sink)
ION Min.
poChannel
(Source) :
lOP Min.
-
-
-
-
3.6
7.2
1.4
2.S
4.5
9
5
10
10
o Typ.; 0.05 Max.
o Typ.; 0.05 Max.
0
0
5.
10
4.95 Min.; 5 Typ.
9.95 Min.; 10 Typ.
5
1.5 Min.; 2.25 Typ.
3 Min.; 4.6 Typ.
1.5 Min.; 2.25 Typ.
3 Min.; 4.5 Typ.
1 Min.
1 Min.
1 Min.
0.5
-
5
0.5
-
10
9.5
Input Leakage
Current,
IlL, ilH
-AT
5
104
Fig. 5 - Typical dissipation characteristics.
V
-""
,.PUTS
,--..1_.,
1 Min.
6
10
5
10
ICLI'I~pF
(per output}.
6
10
-
4.5
V
10
0.5
1
LOAD CAPACITANCE
----CL·!lOpF
10'
10J
INPUT FREQUENCY "fl-Utl
5
-
'0'
V
0.6
0.9 0.45
0.3
0.37
0.9
1.5 0.75
0.55
O.S
1
0.3
1.5 0.65
0.23
Fig. 6 - Ou;escent-dev;c;e.current test circuit.
0.5
mA
·0.31 ·0.5 ·0.25 ·0.175 ·0.145 ·0.5 ·0.12 ·0.095
10 ·0.95 ·1.5 ·0.7
·0.5
·0.6
·1.5 ·0.5
INPUTOVOOOUTPUTS
·0.4
VOO-VNH
~r15
±10- 5 Typ .. ±1 Max.
/lA
'-
~
~
v~
NOTE:
TEST ANY ONE INPUT.
Vss
WITH OTHER INPUTS AT
9lCS-l14QO
VOD QRVss
DYNAMIC ELECTR ICAl CHARACTERISTICS at TA =25°C, Inputtr , tf =20 ns, Cl - 15 pF,
RL=2OOk!l
Fig. 7 - Noise-immunity test circuit.
LIMITS
CHARACTER ISTIC
TEST
CONDITIONS
VOD
M
D,F,H
Packages
Min.
E
Packllfl.
Typ. Max. Min.
Propagation Delay
Time;
tpLH, tpHL
-
100
225
10
50
100
Transition Time;
tTHL,fTLH
5
-
100
200
10
-
40
65
All A and B
Inputs
-
5
Ka and Kb
Inputs
-
12
Average Input
Capacitance, CI
5
UNITS
Typ. Max.
100
300
50
125
100
275
40
SO
-
-
5
-
pF
-
-
12
-
pF
ns
ns
Fig. 8 - Input·mskBf/B-curmnt lelt circuit.
479
CD4020A Types
COS/MOS
14-Stage Ripple-Carry
Binary Counter/Divider
The RCA-CD4020 consists of· a PU LSE
INPUT shaping circuit, RESET line driver
circuitry, and 14 ripple-carry binary counter
stages. Buffered outputs are externally available from stages 1 and 4 through 14. The
counter is reset to its ali-zeroes state by a
high level on the RESET inverter input line.
Each counter stage is a static master-slave
flip-flop. The counter is advanced one count
on the negative-going transition of each
INPUT PULSE.
I.
16
•
INPUT
PULSES
These types are supplied in 16-lead hermetic
dual-in-line ceramic packages (D and F
suffixes), 16-lead dual-in-line plastic package (E suffix), 16-lead ceramic flat package
(K suffix), and in chip form (H suffix).
01
7 0"
• o.
'4-STAOE
RIPPLE
COUNTER
•
•
13
12
01
07
01
Q9
14 QIO
1&
all
I 012
2 013
3 014
"
RESET
MAXIMUM RATINGS, Absolute-Maximum Values:
STORAGE-TEMPERATURE RANGE (Tstg ) _ .. _. _ ..... _ ... _ ........... _ ...... . -66 to +1500 C
OPERATING-TEMPERATURE RANGE (T A ):
PACKAGE TYPES 0, F, H
......... _. __ . _........ _........... __ ...... . -55 to +12SoC
PACKAGE TYPE E
-40 to +85 0 C
OC SUPPLY-VOLTAGE RANGE, (V DD )
(Voltages referenced to VSS Terminal) ......................................
RECOMMENDED OPERATING CONDITIONS at T A = 25 0 C, Except as Noted.
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges'
VDD
(V)
LIMITS
D,F,H
E
Packages
Package
Min.
Max.
Min.
Max.
Supply-Vo)tage Range (For TA = Full
Package-Temperature Rangel
UNITS
3
12
3
12
V
Input Pulse Width, tw
5
10
335
125
-
500
165
-
ns
Input Pulse Frequency, f",
5
10
de
de
1.5
4
de
de
1.5
4
MHz
Input Pulse Rise or Fall Time, tr""tf",
5
10
-
15
15
-
-
15
15
j.ls
Reset Pulse Width, tw
5
10
2500
475
-
3000
550
-
ns
-
Features:
• Medium speed operation .••
7 MHz (typ.) at VDD-VSS = 10 V
• Low output impedance
• Common reset
• Fully static operation
• Ouiescent current specified to 15 V
• Maximum input leakage current of 1 j.lA
at 15 V (full package-temperature range)
• I-V noise margin (full package-temperature
range)
Applications:
•
•
•
•
Frequency-dividing circuits
Time-delay circuits
Counter control
Counting functions
I.PUT
PlLSE
""'R
£t
.
*AIL INPUrS ARE
MOTECTED BV
..-.
COS/MOS PIIOTECTtCIN
nell-IIOI'''2
•
• Yss
• R. HIGH DOMINATES (RESETS ALL STAGES)
... ACTION OCCURS ON NEGATIVE GOING TRANSITION Of' INPUT
P\A.SE. COUNTER ADVANCES ONE .I'4ARY COUNT ON EACH
NEGATIVE ., TRANSITION (11,384 TOTAL alNMY COUNTSJ.
Fig. I-Logic diagram for 1 of 14 binary stages.
480
ac:s.1i053A2
-0.5 to +15 V
POWER DISSIPATION PER PACKAGE IPDI:
........ ___ ............ _. . .
SOO mW
FOR T A = -40 to +60o C (PACKAGE TYPE E)
FOR T A = +60 to +8SoC (PACKAGE TYPE E I
.. _.... _. Derate Linearlv at 12 mW/oC to 200 mW
FOR TA = -55 to +100 0 C (PACKAGE TYPES 0, F)
...... _... _'" _.........
SOO mW
FOR T A = +100 to +125 0 C (PACKAGE TYPES 0, F)
..... Der.te Linearlv at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (ALL PACKAGE TYPES) .. _.
l00mW
INPUT VOL TAGE RANGE, ALL INPUTS ...... _... _. __ . ___ .. __ . __ .. _...... -0.5 to V DD +0.5 V
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max, ......... .
CHARACTERISTIC
Vss
_ CD4020A
FUNCTIONAL DIAGRAM
CD4020A Types
..... IIDIT' TEIllPEJtAT1JItE IT"J. 2S-c
TYPICAL. T!.~""TVftI COD'fICIENT fOR 10 - ~ 0.:5" "C
I.
•
I
Fig. 3- Typical output n-channel drain characteristics.
NOTE: SUBSTRATES 10" "u•• ,. UNITS ARE COtilNECT(O TO YDD
SUBSTRATES fQfl"LL .... UNITS, UNLESS O'NE".11l SHOWN,ARE COJIIN[CTt:O TO OIIOUNO .
• SUBSTRATES fOR TNnl· ..• UNITS
COtIIN(CTID TO"UET LINE
""!
Fig. 2 - Schematic diagram of pulse shapers and 1 of 14 binary stages.
STATIC ELECTRICAL CHARACTERISTICS
Limits at Indicated Temperatures (OC)
Conditions
D,F,H Packages
E Package
llIaracteriltic
-55
+25
+125 -40
+25
Vo VIN VOO
(V) (V) (VI
Typ. Limit
Typ. Limit
Cluiescent
5
15
0.5
15
900
50
1
50
Device
25
100
100
1
25
10
1500
2
Current,
500
50
2.5
50
2000
500
5
- 15
ILMax.
Output
Voltage:
Low· Level , 5
5
o Typ.; 0.05 Max.
o Typ.; 0.05 Max.
10
10
VOL
High·Level,
VOH
Noise
Immunity:
Inputs Low,
VNL
Inputs High,
VNH
Noise
Margin:
Inputs Low,
VNML
Inputs High,
VNMH
Output
Drive Cur·
rent:
N·Channel
(Sink),
ION Min.
P·llIannel
(Source)
lOP Min.
Input
Leakage
Current,
IIL,IIH
-
0
0
-
+85
700
1400
5000
p.A
DRAIII~TO-SQ.RCE VOLTS !Vasl
S2CS.lfM2
Fig. 4-Minimum output n-channel drain characteristics.
.
DRAIN-TO-SOURCE YOUS !Vosl
-15
-10
-5
-.
V
4.95 Min.; 5 Typ.
9.95 Min.; 10 Typ.
5
10
Units
-I.
4.2
9
0.8
1
-
-
5
10
5
10
1.5 Min.; 2.25 Typ.
3 Min.; 4.5 Typ.
1.5 Min.; 2.25 Typ.
3 Min.; 4.5 Typ.
4.5
9
-
5
10
1 Min.
1 Min.
0.5
1
-
5
10
1 Min.
1 Min.
-
V
GATE-TO- SOURCE YOUS I Vosl--15
AMIIENT TEMP£RATURE IT,,1025·C
TYPICAL TEMPERATURE COEFFICIENT FOR 1 D • -0.:511. '·C
Fig. 5- Typical output p-channel drain charac·
teristics.
V
DRAIN-TO- saulteE VOLT' IYDI I
-""L
0.5
0.5
-
5
10
0.09
0.185
-
5
10
-0.11 -0.25 -0.09 -0.065 -0.09 -0.25 -0.06 -0.05
0.25 0.5
0.20 0.14
0.18
0.5
0.15 0.12
-
0.2
0.4
0.075 0.05
0.15 0.105
0.09
0.16
0.33
0.5
0.08
0.10
i
0.065
0.10
mA
4.5
9.5
-
Any Input
-1-1
15
±10-5 Typ., ±1 Max.
p.A
.1eI-1""
Fig. 6-Minimum output p-channel drain characteristics.
481
CD4020A Types
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25 0 C, Input tr,tt = 20 ns,
CL=15pF, RL200kQ
LIMITS
CHARACTERISTIC
TEST
CONDITIONS
VDD
(VI
E
Package
D,F,H
Packages
Min. Typ.
Max.
Min. Typ.
UNITS
Max.
Clocked Operation
.
Propagation Delay
Time,
5
10
-
450
150
600
225
-
450
150
650
250
ns
5
10
-
450
200
600
300
-
450
200
650
350
ns
Maximum Input Pulse
Frequency, f '"
5
10
1.5
4
2.5.
6
-
1.5
4
2.5
6
-
Minimum Input Pulse
Width, tw
5
10
-
200
70
335
125
-
-
200
70
500
165
ns
Input Pulse Rise &
Fall Time, tr""tf",
5
10
-
.-
-
-
-
-
15
15
-
-
15
15
Ils
Any Input
-
-
5
-
-
5
pF
5
10
-
2000
500
3000
-
775
-
tPLH, tpHL
Transition Time,
tTHL, tTLH
Average Input
Capacitance, CI
Reset Operation
Propagation Delay
Time,
Fig. 7- Typical propagation delay time vs. CL .
MHz
AMBIENT TEMPERATURE IT"I • 2$·C
.,"'"
I
~
TYPICAL T£MPEUTURE COEFFICIENT
FOR AL.L. VALUES OF
Voo' 0
3'Jo
,·e
,0
.
tpHL
2000 3500
500
300
"
ns
20
30
40
go
50
L(W) CAPACITANCE leLI-rtF
Minimum Reset Pulse
Width,
tw
-
5
10
1800
300
2500
475
-
1800 3000
550
300
Fig. 8- Typical transition time vs. CL -
ns
* Propagation delay is from input pulse to Q 1 output.
Voo
INPUTS
o
V55
LOAD CAPACITANCE ICLI'I:!pF
- - - - CL '~OpF
'0'
Fig. 9- Typical clock input frequency vs. VDO'
Vss
'0'
10)
10"
INPUT FREQUENC., Ufl-Hl
nCS-2140I
FiiJ. 10- Typical dissipation characteristics.
.INPUTOVOO
OUTPUTS
VOO-~
10·
.
~
o
_
VHL
Fig. 1,-Quiescent-device-current test circuit.
V~~NP(JUTVOO :~:~~"'NPUTS
o ~
SEQUENTIALLY,
Vss
TO BOTH YDD ANDYss-
CONNECT ALL &MUSED
...urs 10 EITHER
NOTE:
Vss
TEST ANY cowaiNATIc:4
OF INPUTS
Fig. 12-Noise-;mmunity test circuit.
VooOftYss.
Vss
Fig. 13-lnput-leskage-current test circuit.
482 __________________________________________________________________
CD4021 A Types
COS/MOS a-Stage Static Shift Register
Asynchronous Parallel Input/Serial Output,
Synchronous Serial Input/Serial Output
:::.2
Features:
CONT
• auiescent current specified to 15 V
• Maximum input leakage current of 1 J1A
at 15 V (full package-temperature range I
• 1-V noise margin (full package-temperature rangel
When the PARALLEL/SERIAL CONTROL
input is low, data are serially shifted into
the B-stage register synchronously with the
positive-going transition of the CLOCK
pulse.
When the PARALLEL/SERIAL CONTROL
input is high. data are jammed into the Bstage register via the parallel input lines asynchronously with the clock line.
Register expansion is possible using addi-
STATIC ELECTRICAL CHARACTERISTICS
CHARACTERISTICS
Quiescent Device
Current I L Max.
Output Voltage:
Low-Level,
Vo
V IN V DD
IVI
-
-
5
5
-
10
10
Co.
VOL
High Level
V OH
Noise Immunity;
Inputs Low,
V NL
4.2
9
5
10
50
1
UNITS
TYP. LIMIT
0.5
+85
5
300
50
50
700
600
100
1
100
1400
1
50
2000
500
5
500
5000
tional CD4021A packages_
These types are supplied in 16-lead hermetic
dual-in-line ceramic packages (D and F
suffixesl. 16-lead dual-in-line plastic package (E suffixl. 16-lead ceramic flat package
(K suffixl. and in chip form (H suffix).
• Parallel to serial data conversion
• Asynchronous parallel input/serial output
data queueing
• General purpose register
jJA
10
9.95 Min.; 10 Typ.
5
1.5 Min.; 2.25 Typ.
10
i,
~
'ill
, j
2
S
d
I
\ 3 Min.; 4.5 Typ.
10
3 Min.; 4.5 Typ.
5
1 Min.
9
-
10
1 Min.
0.5
-
5
1 Min.
10
1 Min.
5
10
Fig. 1 - Typical clock input frequency vs.
supply voltage.
V
AMIIENT TENPfRATURf ITA I • 2!!1 '"C
nPiCAL 'U:_ERATURE COEFFICIEHT FOR
ALL VALUES OF VDO • 0.' ,.,,·C
mHl!!Hl
Output Drive
Current:
mm!
PI,j.~: it:W;l.ln-m:::t!
I, +Jt~;~~oo
""~mTI I!!
N-Channel
(Sink I.
0.5
ION Min.
0.5
P·Channel
(Source I
4.5
lOP Min.
9.5
Input Leakage
Current,
IIL·IIH
I!!I
SlF'PLY VOI..TS1VOOI
V
1.5 Min.; 2.25 Typ.
:1::
fft !I~j
!:
.
~
V
~;: ::::
..... . . . . . .
LOAO CAPACITANCE ICL'-.!!I,F
...
~!!I
it
4.95 Min.; 5 typo
5
6
j
a Typ.; 0.05 Max.
a Typ.; 0.05 Max.
-
1
-40
10
1
Noise Margin:
Inputs High,
V NMH
0.5
+125
4.5
0.8
PACKAGE.
+25
TYP. LIMIT
-
Inputs High
V NH
Inputs Low,
V NML
5
-
Vss
C04021A
FUNCTIONAL OIAGRAM
AMBIENT TEMPERATI.R[ IT.. '-2!!1'"<: •••••••
15
10
a
a
E
+25
IVI
-
IVI
D, F, H PACKAGES
-55
ClOCK~
App/ications:
LIMITS AT INDICATED TEMPERATURES lOCI
CONDITIONS
SER. II
IN
• Asynchronous parallel or synchronous serial operation
under control of parallel/serial control-input
• Individual JAM inputs to each register stage
• Master-slave flip-flop register stages
• Fully static operation .... __ DC to 5 MHz
The RCA-CD4021A types are B-stage parallel or serial-inputlserial-output shift registers
having common CLOCK and PARALLEL!
SERIAL CONTROL inputs, a single SERIAL DATA input, and individual parallel
Jam inputs to each register stage. Each register stage is a D-type. master-slave flip-flop.
a outputs are avai lable from the sixth,
seventh. and eighth stages_
_Ar
-
-
5
0.15
0.3
0.12
0.085 0.072
0.3
0.06
0.05
10
0.31
0.5
0.25
0.175 0.12
0.5
0.1
0.08
5
10
~nr15
-0.1
-0.16 -0.08 -0.055 -0.06
-0.25 -0.44 -0.20 -0.14 -0.12
±10-5 Typ .. ± 1 Max.
rnA
~
-0.16 -0.05 -0.04
-0.44 -0.1
..mE ;g~
Ii!.
..
:~::
..
':'
I.::
:::: :::: I
.............
-0.08
"
Fig_ 2 -
7. . .
_1'1710'
Typical propBfllltion dB/ey tims VI_
load CllpacitanCtl.
483
CD4021 A Types
MAXIMUM RATINGS, Absolute-Maximum Values:
STORAGE-TEMPERATURE RANGE IT stgl
."SIENT TEMPERATURE ITA'. 25·C
T'l'PICA" TEMPERATUR[ COf"FFICIEHT FOR
ALL VALUES OF VDO' 0.3'" I ".:
____ . . • . . . . . . _ . . . . • . _ . • . • .• -65 to +150'C
OPERATING-TEMPERATURE RANGE (TA)\
PACKAGE TYPES 0, F, H
-65 to +125'C
PACKAGE TYPE E
. . . . . . . . . . • . _ . . . . • . _ .. __ . . . . . . . . . _ . . . . --40 to +B5'C
-f
,[400
DC SUPPLY-VOLTAGE RANGE, (VDDI
(Voltagesreferenced to VSS Terminail . . . • . . . • . . . . . . _ .•. _ .. _ ..•.•• _ • -0_5 to +15 V
POWER DISSIPATION PER PACKAGE (Pol
= -40 to +60'C (PACKAGE TYPE
EI
.•. _ .. _ . . . . . . . . . _ .• _ .•.•• 500mW
FOR T A = +60 to +85' C (PACKAGE TYPE E I
•• _ .. _ Derate Linearly at 12 mWfC to 200 mW
. . . _ ..•. _ . . . • . _ . . . . • • • . 500mW
FOR TA
FOR TA = -55 to +100'C (PACKAGE TYPES 0, F I
FOR TA
=+100 to +125'C (PACKAGE TYPES 0, FI
.. _ Derate Lineerly at 12 mWfC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
Fig. 3 - Typical transition time
load capacitance.
FOR t A = FULL PACKAGE-TEMPERATURE RANGE (ALL PACKAGE TYPESI .•.••.• 100 mW
INPUT VOLTAGE RANGE, ALL INPUTS •••••.•.• _ •.•.•••. _ ..• _ • _ -0.5 to VDD +0.5 V
LEAD TEMPERATURE (DURING SOLDERINGI:
Atdistancel/16± 1/32 inch (1.59 ± 0.79mml from case for 10. ma,_ ••. _ .•. _ .•• _ •.
PARALLEL
PI-iZ
INPUT~I
PARALLEL I
SERIAl.
Pl-3 PI-4
Pl-!!
PI-7
PI-6
VI.
+265'C
PI-B
7
CONTROL
CL
LOAD CAPACITANCE ICLI'I:lpF
----Cl'f>QpF
CLOCK
10*
Voo • TERMINAL 16
Fig. 4 - Typical dissipation
Vss" TERMINAl... e
chsracteristiCli.
a.
92CN -17141R3
Fig. 5 - Logic diagram.
R ECOMMENDED OPERATING CONDIT IONS at TA = 25' C, Except as Noted_
For maximum reliability, nominal operating conditions should be seleCted so that
operation is always within the following ranges:
TRUTH TABLE
CL 4
Serial
Parallell
Serial
Input
Control
Pl-l
PI·n
liMITS
01
(Internal)
On
X
X
t
0
0
0
0
X
X
1
0
1
0
1
X
X
1
1
0
1
0
X
X
1
1
1
1
1
~
0
0
0
X
X
X
0
On,1
X
1
on·1
X
X
01
On
1
'-4. LEVEL CHANGE
X
~,O CHANGE
0
CHARACTERISTIC
(VI
D,F. H
PACKAGES
MIN.
Supply-Voltage Range (For T A=Full
Package-Temperature Range)
X' DON'T CARE CASE
92CS-I7141 R3
VDD
3
MAX_
E
PACKAGE
MIN.
12
3
UNITS
MAX_
12
V
5
10
350
80
-
-
500
100
-
ns
Clock Pulse Width, 1W
5
10
500
175
-
830
200
-
ns
Clock I nput Frequency, fel
5'
10
de
de
1
3
de
de
0_6
2_5
MHz
Clock Rise and Fall Time, trCL, ttCl
5
10
-
15
5
-
15
5
!.IS
Data Setup Time,
ts
Fig. 6 - Truth table.
-
-
* If more than one unit is cascaded trCL should be made less than or equal to the sum of the tranlition time
and the fixed propagation delav of the outP.ut of the driving stage for the estimated capacitive load.
484
CD4021 A Types
DYNAMIC ELECTRICAL CHARACTERISTICS
at TA
=2fr1C, Input tr, tf= 20ns, CL = 15 pF, RL =200kU
'00-::::"'NPUTO'DO -!@
OUTPUTS
LIMITS
CHARACTERISTIC
TEST
CONDITIONS
VDD
(V)
Propagation Delay
Time:·
tPLH. tPHL
10
Transition Time;
trHL. trLH
Maximum Clock Input
Frequency. tCL
750
100
225
-
150
300
10
75
125
5
1
1000
300
300
-
150
400
75
150
-
-
0.6
200
830
100
200
-
15
5
2.5
-
5
200
500
100
175
-
15
-
-
5
-
-
100
350
-
100
500
50
80
-
50
100
Minimum Data Set
UpTime. 1$
10
10
5
5
~':'N~U~~OMIIIfATIC"
2.5
5
5
-
200
500
-
200
830
10
-
100
175
-
100
200
Any Input
-
5
-
-
5
-
Fig. 7 - Noise4mmunity test circuit.
ns
ns
MHz
3
10
Input Capacitance CI
300
5
Clock Rise & Fall
Time; trCL & ttCL'
Minimum High-Level
ParallellSerial
Control Pulse
Width tw
2.5
-
10
-
Minimum Clock Pulse
Width. tw
HOTE:
'Iss
300
5
UNITS
MIN. TYP. MAX. MIN. TYP. MAX.
-
5
.J;
V':L
E
PACKAGE
D. F. H
PACKAGES
Test performed wIth the following Mquenca
of "Ona's" lind .. Z.ro·....
S, S2 S3 S4 S5
o 0 , 0 0
, 0
"
, 0
0'
o , , , ,
ns
o ,
000
lIS
ns
ns
92C5o 1792CAI
pF
Fig. 8 - Quiescent device current test circuit.
*If more than one unit is cascaded trCL should be made Jess than or equal to the sum of the transition time
and the fixed propagation delay of the output of the driving stage for the estimated capacitive load.
·-From Clock or Parallel/Serial Control Input
-*
'"
.~NP(JUS
'00 :~:~U" 'NPUTS
o ~
SEQUENTIALLY,
TO acTH VDD AND 'iss
Vss
CONNECT ALL UNUSfD
INPUTS TO EITHER
VDD OR VSS
V55
PIS
D
Pl:
CL
Fig. 9 -!nput-leaksge-current
test circuit.
.,,
"q'
STAGES
~~~y8
D
Fig. 7a - One typical stage and its equivalent detailed circuit.
485
CD4022A Types
COS/MOS Divide-By-8
Counter/Divider
With 8 Decoded Outputs
The RCA-CD4022A types consist of a 4stage divide-by-8 Johnson counter, associate decode output gating and a CARRYOUT BIT. The counter is cleared to its zero
count by a high RESET signal. The counter.
is advanced on the positive ClOCK'signal
transition provided the CLOCK INHIBIT
signal is low.
Use of the Johnson divide-by·8 counter
configuration permits high·speed operation,
2·input decode gating, and spike-free decoder outputs. Anti·lock gating is provid,l!d,
thus assuring proper counting sequence. The
8 decode gating outputs are normally low
and go high only at their respective decoded
time slot. Each decode gate output remains
high for one full clock cycle. The CARRY·
OUT signal completes one cycle every 8
CLOCK· INPUT cycles and is used as a
ripple-carry signal to directly clock a suc·
ceeding counter package in a multi·package
counting system.
These types are supplied in l6-lead hermetic
dual-in-line ceramic packages (D and F
suffixes), l6-lead dual-in-line plastic package (E suffix), l6-lead ceramic flat package
(K suffix), and in chip form (H suffix).
MAXIMUM RATINGS, Absolute-Msximum Values:
STORAGE·TEMPERATURE RANGE (T,tg) , • • • . . . . . . • , . . . . • • , .•.•.••••.-65'0 +l50oC
OPERATING·TEMPERATURE RANGE (TAl:
°
PACKAGE TYPES 0, F, H
.. , • . . . • • • . • . • . . . , •• " . • . . • . • , .• , .•• -55'0 +1250C
PACKAGE TYPE E
. • . . . . • • • • . • . . . . , . . . . • • . . . • . , •.. , ..•.•• -40'0 +85 C
DC SUPPLY·VOLTAGE RANGE, (Vooi
(Vol.ogesrafaranced.o Vss Tarmlnal): .•• , . . • . • • • . , ..•. , •... , ...••• ,-0.5'0 +15 V
POWER DISSIPATION PER PACKAGE (Po)
FOR TA= -40'0 -tilQ°C (PACKAGE TYPE EI ., . . . . . . . • . • . • . . • • • , .•••.•• ,500mW
FOR T A= +60 to +850C (PACKAGE TYPE E I
" . . . ,., .oera.a LinHrly •• 12 mW'oC'o 200 mW
FOR TA= -55 to +loo oC (PACKAGE TYPES O. F)
, .•..•.••••.••• , ••• , .••• 5OOmW
FOR TA= +100'0 +1250C (PACKAGE TYPES 0, F J
••••• Oaro.a LinHrly at 12 mW'oC to 200 mW
OEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA= FULL PACKAGE·TEMPERATURE RANGE (ALL PACKAGE TYPESI , •.•.•..• 100 mW
INPUT VOLTAGE RANGE. ALL INPUTS • . • • • . . • • • • . . • . . • • . • , , , • , , -0.5'0 Voo +0.5 V
LEAD TEMPERATURE (DURING SOLOERINGI:
Atdistoncal/16±1/32 inch (1.59 ±0.79 mml from cosafor 10. mox ••• , • • . • . . • . . . • ,+265°C
RECOMMENDED OPERATING CONDITIONS at TA = 25°C, Except al Noted.
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges:
LIMITS
CHARACTERISTIC
VDD
(V)
Supply·Voltage Range (For TA = Full
Package· Temperature Range)
I
D,F,H
Packages
E
Packags
UNITS
Min.
Max.
Min.
Max.
3
12
3
12
V
Clock Inhibit
Setup Time, ts
5
10
175
75
-
-
175
75
--
ns
Clock Pulse Width, tw
5
10
500
170
-
830
250
-
ns
Clock Input Frequency, fCl
5
10
dc
dc
1
3
dc
dc
0.6
2
MHz
Clock Rise and Fall Time, trCl,ltCl
5
10
-
15
15
-
15
15
lAS
Reset Pulse Width
6
10
300
150
-
600
300
-
ns
Reset Removal Time
6
10
752
226
-
ns
486
--
1000
275
-
Features:
• Medium speed operation ...• 5 MHz (typ.) at
VDD - VSS= 10V
• Divide by N counting; N =2 to 8 with one
CD4022A plulone CD4001A package
• Quielcent current specified to 15 V
• Maximum input leakage current of 1 IJA
3t 15 V (full package-temperature range)
• 1-V noise margin (full package·temperature renge)
Applications:
• Binary counting/decoding
• Binary frequency division
• Binary counter control/timers
CD4022A Types
Ct.OCK
~~~
__________________________
Jr---1~
_________________
"0" ---ci\L.._ _ _ _ _ _-Jf'1i'\'--_ _ _ _ _ _ _ _ _1"OL-
"," ----In
---fT\
m~
"2"
"3" ______
~~L..
"4" _ _ _ _
"~.
_________..Jrr
~'__
________
_ _ _ _ __
0"'--_ _ ___
-J~
_____
_ _ _ _ _ __
_J~L..
nnL.._______
~nn
"6" _ _ _ _ _ _---'f6\
~
"7" :::::::::=\======~~~7;::::::::::::=\=======~~7
CaIJ!lY
r---Fig. 2 - Timing diagram.
AMBIENT T[MPERATURE ITA' • 25'C
TYPICAL TEMPERATURE COEFFICIENT FOR
i
VALuES OF Voo • 03... ,'e
}
-ALL INPUTS ARE PROTECTED BY
•
1250
:
1000
COSIMOS PROTECTION NETWORK
Fig. 1 - Logic diagram.
,~
LOAD CAPACITANCE cell-pF
Fig. 3 - Typical proPllflBtion dB/ay time VI.
load capacitance for dflCOded outputs.
STATIC.ELECTRICAL CHARACTERrSTICS
Lim... It 1...1..... Tompenotu. . (oCI
D,F,HP.:k_
E hcIc."
Condition.
Chor_ril1lc
Quiescent Device
Current IL Max.
Output Voltage:
Low Level
VOL
High Level
VOH
Noise Immunity:
Input. Low,
VNL
Input. High
VNH
Noise Margin:
Inpuu Low,
VNML
Input. High,
VNMH
Vo VIN VDD
-66
(VI (VI (VI
-
-
(Sink)
ION Min.
poChennel
(Source):
lOP Min.
Input Leakage
Currant,
IIL,IIH
-40
+26
TVD.
-
&
10
1&
&
&
10
10
oTyp.; 0.05 Max.
oTyp.; 0.05 Max.
0
0
&
10
4.95 Min.; &Typ.
9.95 Min.; 10 Typ.
&
10
&0
0.3
0.&
1
&
10
&0
300
&0
600
2000
100
600
0.&
1
5
-
&
1.& Min.; 2.25 Typ.
9
-
10
3 Min.; 4.5 Typ.
O.B -
&
10
1.& Min.; 2.2& Typ.
3 Min.; 4.& Typ.
1
4.5
9
0.5
1
Carry
Output
Decoded
Outpuu
Carry
Output
TVD. Umlt
+126
4.2
Output Drive Decoded 0.5
Current:
Outputs 0.5
n-Chlnnel
+26
0.&
0.5
4.5
9.5
4.&
9.6
-
-
-
- -1
5
1 Min.
10
1 Min.
5
10
1 Min.
1 Min.
5
10
5
10
&
10
0.062
0.12
0.185
0.37&
·0.038
.0.12
6 ·0.186
10 ·0.376
AT Input
'5
0.15
0.3
0.5
1
·0.075
.0.1&
·0.4
.o.B
0.03&
0.07
0.105
0.21
.0.021
·0.07
.0.16 ·0.106
.0.3 ·0.21
0.05
0.1
0.1&
0.3
.0.03
.0,1
0.03
0.06
0.09&
0.166
0.1&
0.3
0.5
1
.o.D1B ·0.07&
·0.06 .0,15
.0.09& ·0.4
·0.166 ·0.8
±lo-& Typ., ±1 Max.
Unlu
".•oo
~.
i8&
Umh
&0
100
500
700
1400
pA
&000
'0
V
Fig. 4 - Typical propagation delay time VI.
V
V
0.025
0.05
0.06
0.13
·0.01&
.0.05
.0.06
.0.13
0.02
0.04
0.085
0.105
mA
.0.012
·0.04
·0.06&
·0.105
pA
load capacitance for carry output.
AMIIENT TE..-otATUIIt: tT,t,l. 2'·C
T\?!CAl Tu.r:MTVRE CO["1CI[Iff fOR AL.L. VAUlES
OI1YDD·O.:S"I·~
IrT
,,'
20
40
60
L.OAD CAPACnANCE ICL.l-pF
80
Fig. 5 - Typical transition time VI. load
capacitanctJ for dfICoded outputs.
_______________________________________________________________________ 487
CD4022A Types
DYNAMIC ELECTRICAL CHARACTERISTICS It TA - 25°C, Input tr ,tr - 20 nl,
CL -15pF,RL-2OOkS'l
LIMITS
TEST
CONDITIONS
CHARACTERISTIC
VDD
(V)
E
D,F,H
PIICkll(/es
UNITS
PIICkllflll
Min. Typ. MIIX. Min. Typ. MIIX.
CLOCKED OPERATION
Propagation Delay Time:
5
tp~L'~LH
arry· ut Line
10
5
10
Decode Out Lines
Transition Time:
tTHl,tTlH
Carry·Out Line
5
10
5
10
5
10
Decode.out Lines
Min. Clock
Pulse Width, iw
Clock Rise and
Fall Time,
trCl, ttcl
Min. Clock Inhibit
Set·Up Time,
ts
Input Capacitance, CI
RESET OPERATION
Propagation Delay Time:
tPHl, tplH
Carry·Out Line
-
-
325 1300
250
125
400
200
1200
400
-
85
300
50
100
300
126
250
86
900
250
500
17U
-
-
300 1200
125 500
250 830
85 260
85
340
60
200
-
-
15
- -
16
6
176
350
175
700
10
75
160
76
300
2.6
5
5
-
0.6
2
-
-
2.6
6
6
-
10
Min. Reset Pulse
Width,tW
5
10
6
10
Min. Reset
Removal Time
6
10
-
-
900
-
300
1200
126
250
-
126
500
-
-
clIplICitIJnCII for ClIrTY output.
ns
ns
ns
ns
{JS
ns
Fig. 7 - Typic.1 clock input froqUBncy ...
.upply voltage.
MHz
-
300
500 1260
200 400
160 300
75
160
300 762
100 226
Fig. 6'- Typi.tIi trlJlJlltlon time ... 10«1
400 1600
200 800
15
1
3
ns
500
16
5
-
1000
125
-
5
10
Anv Input
Decode·Out Line
-
,
325
-
5
10
Max. Clock Input
Frequency, fCl'
-
500 2500
200 800
160 600
76 300
300 1!!!Ht
100 276
pF
10
•
AlllacNT TtMP£RATUM
IT"I'Z~'C
"PUT t r 'lf'20nl
i ...
ns
i
l
...
'0'
0'
ns
ns
LOAD CAPtlCtTANC[ ICLI'ISp'
--CL."!OjtF
ns
• Mea.ured with respect to carry output IIna
10
INPUT CLOCIC
IO Z
FREQUENCY
10'
'fCLI-Ub
10"
Fig. 8 - Typical dlulpation ch.roctari.ti.1.
VDD
VDO
INPUTS
o
Vss
. 10""'0'"
,VDD-~
OUTPUTS
-+, '
VNL
-
V~NPU(J'
'"=..::
Vss
TO BOTH Yoo AND'lss'
CONNECT ALL UNUSED
vss
V55
Fig. 9 - OuitJIC8nt-dtl'lictl-culTrlnt test circuit.
lNPurs 10 EITHER
VDOORYSS •
NOTE:
' Tar ANY COtMINATICIN
OF INPUTS
Fig. 10 - NO;$(J-;mmunity test clmuit.
V55
Fig.
l'
-lnpur-IHk. . .urront ta.t circuit
488 __________________________________________________________________
CD4024A Types
"DD
COS/MOS 7 -Stage Binary Counter
I.
With Buffered Reset
INPUT I
PULiE.
The RCA·CD4024A consists of an INPUT
PU lSE shaping circuit, RESET line driver
circuitry, and seven binary counter stages.
The counter is reset to "zero" by a high level
on the RESET input. Each counter stage is a
static master·slave flip·flop. The counter
state is advanced one count on the negative·
going transition of each INPUT PULSE.
",
*ALL INPUTS ARE
PROTECTED BY
COSINOS PROTECTION
NETWORI<
Fig. 1 - Functional diagram far C04024AD,
AE,AF,
These types are supplied in 14-lead hermetic
dual-in-line ceramic packages (D and F
suffixes), 14-lead dual-in-line plastic package (E suffix), 12-lead hermetic TO-S-style
package (T suffix) 14-lead ceramic flat packages (K suffix), and in chip form (H suffix).
V1 ·'IKI-2505IAI
'00
Applications:
• Frequency·dividing circuits
• .Time-delay circuits
• Counter control
• D/A counter and switch on one chip
.."
£\
"
00
RESET
*ALL. INPUTS ARE
PROTECTED BY
COS/MOS PROTECTION
NETWORK
Fig. 2 - Functional diagram
--
MAXIMUM RATINGS, AbsDlute-Maximum Values:
for CD4024A T.
",
Vss
STORAGE.TEMPERATURE RANGE (Tstgl . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65 ta +100°C
OPERATlNG·TEMPERATURE RANGE (TAl:
PACKAGE TYPES (D,F,T,HII. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55 ta +125 0 C
PACKAGE TYPE E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to +85 0 C
DC SUPPLY·VOLTAGE RANGE, (VDDI
(Vo(tages referenced to Vss Terminall: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 ta +15 V
POWER DISSIPATION PER PACKAGE (POl
FOR TA=-40ta+60oC (PACKAGE TYPE EI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW
FOR TA= +60 to +850 C (PACKAGE TYPE E I . . . . . . . . . Derate Linearly at 12 mW/oC to 200 mW
FOR TA=-55to +lOO oC (PACKAGE TYPES D,F,TI.. . . . . . . . . . . . . . . . . . . . . . . 500 mW
FOR TA= +100 to +1250 C (PACKAGE TYPES D,F,T I ..... Darate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA= FULL PACKAGE·TEMPERATURE RANGE (ALL PACKAGE TYPESI . . . . . . . . . 100 mW
INPUT VOLTAGE RANGE, ALL INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VDD +0.5 V
LEAD TEMPERATURE lOURING SOLDERINGI:
At distance 1/16 ±1132 inch 11.59 ±0.79 mml from case for 10 s max . . . . . . . . . . . . . . . . +265 0 C
RECOMMENDED OPERATING CONOITIONS at TA = 25°C, Except al Noted.
For maximum reliability, nominal operating conditions should be selectad 10 that
operation is alwayl within the following ranges.
Features:
• Medium·speed operation •.•.
•• 7·MHz (typ.) input pulse rate at
VOO -VSS= 10 V
• low high-and-Iow level output impedance
.• 700n and 500n (typ.), respectively at
VOO-VSS=10V
• Fully stetic operation
• Common reset
• Quiescent current specified to 15 V
• Maximum input leakage current of 1 J.IA
at 16 V (full package-temperature range)
• I-V noise margin (full package-temperature range)
LIMITS
CHARACTERISTIC
VOO
IV)
Supply·Voltage Range (For TA = Full
Package·Temperature Range)
D,F,T,H
Packages
Min.
Max.
E
Package
Min. Max.
3
12
3
5
10
330
125
-
-
500
165
5
10
de
de
1.5
4
de
de
Clock Rise or Fall Time, trCl, ttCl
5
10
15
15
Reset Pulse Width, tw
5
500
10
300
Clock Pulse Width,
tw
Clock Input Frequency, fCl
-
15
15
600
350
UNITS
12
V
-
ns
-
1
3
-
MHz
,
"",-TO-",,",,". """ 1Vosl
j.IS
Fig. 3 - Typical output n--channel drain
chSl1lCttlfi'tics.
ns
489
CD4024A Types
DRA'NoTQ-SOURCE VOLTS tvD"
STATIC ELECTRICAL CHARACTERISTICS
Limits lit IndiCllted TemparaturaslOC)
D.F. T.H. PsckBfIII8
E Psck8flll
Characterirtlc
+25
Vo VIN VOO
+25
-55
+125 -40
IV) !VI IV)
Typ. Limit
Typ. Limit
5
5
0.3
5
300
50
0.5 50
Quiescent Device
10 10 0.5 10 600
100
1 100
Current ,IL Max
15 50
1
50 2000 500
5
500
Output Voltage:
o Typ.; 0.05 Max.
5
5
Low·Level,
o Typ.; 0.05 Max.
10 10
VOL
Condition.
High Level,
VOH
Noise Immunity:
Inputs Low,
VNL
Inputs High,
VNH
Noise Margin:
Inputs Low,
VNML
Inputs High,
VNMH
Output Drive
Current:
n·Channel
ISinkl,
IDNMin.
p·Channel
ISourcel ,
IDPMin.
Input Leakage
Current,
IlL. IIH
- - - - 0
- 0
4.2 -
9
O.B
1
-
5
10
4.95 Min.; 5 Typ.
9.95 Min.; 10 Typ.
5
1.5 Min.; 2.25 Typ.
10
5
10
3 Min.; 4.5 Typ.
1.5 Min.; 2.25 Typ.
3 Min.; 4.5 Typ.
9
0.5
1
-
0.5
-
5
0.5
-
10 0.62
4.5
-
5
9.5
-
10 -0.45 -0.7 -0.35 -0.25
4.5
5
1 Min.
10
5
10
1 Min.
1 Min.
1 Min.
0.31
0.5 0.25 0.175
1
0.5
0.35
0.15
Units
+85
700
1400
5000
pA
V
Fig. 4 - Typical output p-channel drain
chSflJCteristicl.
V
V
0.5 0.12 0.095
0.31
1
0.25
0.2
Fig. 5 - Minimum output n-chsnnel df'llin
chsfactflri.tics.
mA
·0.19 ·0.3 ·0.15 ·0.105 ·0.145 -0.3 -0.12 -0.095
OR.lIN-TO-SOURCE VOLTS 1VOI J
~r~T15
-0.31
-0.7 ·0.25 -0.2
±10-5 Typ.; ±1 Max.
pA
O}
_
~uT5
10
2nd STAGE
0,
Fig.
6 - Minimum output p-channel drllin
chBf'llCteristic'.
• R. HIGHDOIIIMATE~I.EJEn"LLST"'GE5)
a~~E~~~:::=T~v:..~~gJ:,.A::~I:Ho:.:~~I~:,!L::AM51~tOH
1111 TOTAL
IJN"." COUNTS)
EOlIA liONS FOR STAGES Z TO 7
OZOUT • (OzHOr)(:I!R)
O]IIUT • (O]KOI KOz)(:"II)
0.0111 •
(O.)(OI)(Oz)(O])(~(ii)
0SOUT • (05)(01)/OZ)(0])(0.)(: )(li)
060UT • (11,)(01 KOz)(0])(0.)(05)(iKii)
01001' (07)(OI)(OZ)(o])(0.)(05)(0,)/:)(l1l
Fig. 7 - Logic block dillfl'lIITI (pulre shope'
and 1 binary itBgfl).
LOAD CAPACITANCE (CL)-pF
Fig.
ItCS.I1&IO
8 - Typic'" propB!JBtion delay time ••. CL •
490 __________________________________________________________________
CD4024A Types
DYNAMIC ELECTRICAL CHARACTERISTICS lit T A = 25°C. Input t,. tt = 20 nl.
CL
a
Alrl8EMT TEIIIPEltATURE: tT"I.2:I-C
15 pF. RL = 200 kSl
TYPICAl.. TnPERATLR£ COEFfICl[NT
FOR ALL \Illl.£S Of'
Voo.o., ... ,*c
LIMITS
TEST
CONDITIONS
CHARACTERISTIC
VDD
(V)
I/J
D.F.T.H
E
Packages
Min.
UNITS
PackSfIII
Typ. Max. Min.
Typ. Max.
INPUT OPERATION
5
Propagation Delay Tlme;tpLH. tPHL
10
5
Transition Time;
tTHL·tyLH
Maximum Pulse Input
Frequency. fr/J
10
5
10
5
Minimum Input Pulse
Width. tw
10
Input Pulse Rise &
Fall Time. trr/J.tfr/J
5
10
Average Input
Capacitance. CI
1.5
4
-
Any Input
175
350
-
175
400
80
125
80
150
175
225
-
175
250
80
2.5
125
-
80
2.5
150
7
200
330
140
125
-
-
15
-
10
-
5
-
-
-
1
3
-
7
200
500
140
165
-
ns
Fig. 9 -
ns
MHz
15
-
10
5
-
Typical transition time vs. CL -
ns
jJS
pF
LOAD
RESET OPERATION
c&Po\Cn..",c£
teL 1"~pF
--Cl'~OpF
-
Propagation Delay Time;
5
500
700
TpLH. TpHL
10
5
-
-
250
375
350
500
10
-
200
300
Minimum Reset Pulse
Width;tw
• Propagation delav tima is from input pulse to
-
500
800
250
375
400
600
200
350
IO~
10·
ns
lIILL_IIl
INPUT FR[OUENC'I' U.I-Hr
Fig. 10 -
'°6
,,'
Typical dissipation characteristics.
ns
Q 1 output.
v..
INPUTS
I
,.,..,.., VOLTSIVgoI
Fig. 11 -
Typica' input pU/511 ffllquency l's. V D[)-
NCS-Z1441
Fig. 12 -
OU;HClJnt-dtJII;ctH:Ufrent trlst
Fig. 13 -
circuit
Noise-immunity trlst circuit.
V~NPU(JS
vDO :~:~U.E IN.PU'S
o ~
SEOUENTlA'tt't,
TO BOTH Voo AND 'Iss
CONN Eel A LL UNUSED
Vss
INPUTS 10 EITHER
VSS
Fig. 74 -
Voo OR Vss
Input-'tlllkags";Uffllnt test circuit.
491
CD4026A, CD4033A Types
COS/MOS Decade Counters/Dividers
With Decoded 7-Segmllnt Display Outputs and:
Display Enable - CD4026A
Ripple Blanking - CD4033A
VDD
.
v..
12 ..
"}"·, ..g
Run
CD4026A
When the DISPLAY ENABLE IN is low the
seven decoded outputs are forced low reo
gardless of the state of the counter. Acti·
vation of the display only when required
results in significant power sevings. This
system also facil itates implementation of
display-character multiplexing.
The CARRY OUT and UNGATED"C·SEG·
MENT" signals are not gated by the DIS·
PLAY ENAB LE and therefore are available
continuously. This feature is a requiremeot
in implementation of certain divider functions such as divide·by·60 and divide-by-12.
CD4033A
The CD4033A has provisions for automatic
blanking of the non· significant zeros in a
492
multi-digit decimal number which results in
an easily readable display consistent with
normal writing practice. For example, the
number 0050.07000 in an eight digit display
would be displayed as 50.07. Zero suppreS:sion on the integer side is obtained by connecting the RBI terminal of the CD4033A
associated with the most significant digit in
the display to a low-level voltage and connecting the RBO terminal of that stage to
the RBI terminal of the CD4033A in the
next-lower significant position in the dis. play. This procedure is continued for each
succeeding CD4033A on the integer side of
the display.
On the fraction side of the display the RBI
of the CD4033A associated with the least
significant bit is connected to a low level
voltage and the' RBO of that CD4033A is
connected to the RBI terminal of the
CD4033A in the next more·significant-bit
position. Again, this procedure is continued
for all CD4033A's on the fraction side of the
display.
In a purely fractional number the zero
immediately preceding the decimal point can
be displayed by connecting the RBI of that
stage to a high level voltage(insteed of to the
RBO of the next more·significant-stage).
For Example: optional zero -+0.7346.
tikewise, the zero in a number such as 763.0
can be displayed by connecting the RBI of
the CD4033A associated with it to a highievel voltage.
Ripple blanking of non'significant zeros
provides an appreciable savings in display
power.
The CD4033A has a LAMP TEST input
which, when connected to a high-level volt· .
age, overrides normal decoder operation and
enables a check to be made on possible
display malfunctions by putting the seven
outputs in the high state.
~
CLOCK
"
" •°
CLOCK
INNIIIT
IS
The RCA-CD4026A and CD4033A each
consist of a 5-stage Johnson decade counter
and an output decoder which converts
the Johnson code to a 7-segment decoded
output for driving each stage in a numerical
display.
These devices are particularly advantageous
in display applications where low power
dissipation and/or low package count are
important.
Inputs common to both types are CLOCK,
RESET, & CLOCK INHIBIT; common
outputs are CAR RY OUT and the seven
decoded outputs (a, b, c, d, e, f, g). Additional inputs and outputs for the CD4026A
include DISPLAY ENABLE input and
DISPLAY ENABLE and UNGATED "CSEGMENT" outputs. Signals peculiar to the
CD4033 are RIPPLE-BLANKING INPUT
and LAMP TEST INPUT and a RIPPLE·
BLANKING OUTPUT.
A high RESET signal clears the decade
counter to its zero count. The counter is
advanced one count at the positive clock
signal transistion if the CLOCK INHIBIT
signal is low. Counter advancement via the
clock line is inhibited when the CLOCK INHIBIT signal is high. The CLOCK INHIBIT
signal can be used as a negative·edge clock
if the clock line is held high. Antilock gating
is provided on the Johnson counter, thus
assuring proper counting sequence. The CARRY·OUT '(Cout) signal completes one cycle
every ten CLOCK INPUT cycles and is used
to clock the succeeding decade· directly in a
multi-decade counting chain.
The seven decoded outputs (a, b, c, d, e, f, g)
illuminate the proper segments in a seven
segment display device used for representing
the decimal numbers 0 to 9. The 7·segment
outputs go high on selection in the
CD4033A; in the CD4026A theses outputs
go high only when the DISPLAY ENABLE
IN is high.
..
(LOCK
"
~
CLOCK
INHIBIT
•
RESET
"
•
LAMP
"
ENABLE
TEST
II
•
•
I
..
"
5 CARR't'OUT
DISPLAY
.
01S"1.'"
ENAILl
OUT
I.
UNGAl'lUI .(.
KGllnT
Vss
.ZCS·2S0""U
5
RIPPLE
BLK.
IN
&M-RY
RIPPLE
aLK.
OUT.
V••
CD4028A
CD4033A
FUNCTIONAL DIAGRAMS
Features:
• Counter and 7·segment decoding in one package
• Easily interfaced with 7·segment display typel
• Fully stetic counter operation: DC to 2.5 MHz
(typ.)
• Ideal fOr low·power displays
• Display Enable Output (CD4026A)
• "Ripple Blanking" and Lamp Test (CD4033A)
• Ouiescent current specified to 15 V
• Maximum input leakage current of
1 pA. at 15V (full package·temperature
range)
• 1·V noise margin (full package·tamper·
ature range)
Applications:
• Decade counting!7·segmant decimal
display
Frequency divisionn'segment decimal
displays
• Clock/watchas/timers
(e.g.';- 60,+ 50, ';-12 counter/display)
• Counter/display driver for meter
applications
•
These types are supplied in 16-lead hermetic
dual-in-line ceramic packages (0 and F
suffixes), 16-lead dual-in-line plastic pack·
age (Esuffix), 16-lead ceramic flat package
(K suffix), and in chip form (H suffix).
MAXIMUM RATINGS, Absolute-Maximum Values:
STORAGE·TEMPERATURE RANGE (Tstg ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65 to +150oC
OPERATlNG·TEMPERATURE RANGE (TA):
°
PACKAGE TYPES D, F. H . . . . . . . . . . . . . . . . . . . . ., . . . . . . . . . . . . . .-66 to +1250 C
PACKAGE TYPE E ... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to +85 C
DC SUPPLY·VOLTAGE RANGE. (VDD)
IVoltages referenced to Vss Terminel!: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +16 V
POWER DISSIPATION PER PACKAGE (PD)
FOR TA= -40 to +&ODC (PACKAGE TYPE E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW
FOR TA~ +&0 to +85 oC (PACKAGE TYPE E I . . . . . . . . . Dorate Lin..rly et 12 mW/oC to 200 mW
FOR TA- -55 to +100oC (PACKAGE TYPES D, Fl,
. . . . . . . . . . . . . . . . . . . . . . . . 500 mW
FOR TA= +100 to +1250 C IPACKAGE TYPES D, Fl
..... Derate Linearly It 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR T A= FULL PACKAGE·TEMPERATURE RANGE (ALL PACKAGE TYPES) . . . . . . . . . 100 mW
INPUT VOLTAGE RANGE, ALL INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VDD +0.5 V
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch 11.59 ±0.79 mm) from ..so for 10. max . • . . . . . . . . • . . . • . +286 oC
CD4026A, CD4033A Types
COUT
(CLOCK
COUNT
+ 10)
01'121'
CL
41"
RESET
CLOCK
INHIBIT
DISPLAY
b
E~:~~~:
ENA8LEOU~
t-~===~~==:j:===:t"-;:==~
f----+----+------,
UNGATED"C"
1,---<1>---"'-<:> SEGMENT
CL~Kl
~"'---lt=====L>-t!=ft~)
•
·c· SEG. rr:::=;-;::t==::::!====t=~-;~
*CLOCK
INHIBIT 2
*
IS
CARRYQUT
UNOATED
RE5ET"" ____, /"
*~~:~f~03------------I:>---~~----~
IN
16
a
VDDO
GND0 8
i:i:~ SEGMENT
f
ed
IE ALL INPUTS ARE PROTECTED BY
COS/ MOS PROTECTION NETWORK
tac.-I .....
DISPLAY
ENABLE
OUT
Fig. 2 - C04026A timing diBflrtlm.
CLOCK
D~.~~?!~TIONS
RESE'-,L_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CLOCK INHIBIT
nL_ _ _ _ __
LAlilP TEST
~~------
."
COlon IeLOCI
Fig. 1 - C04026A 1000ic dlagrsm.
SEGMENT
DESIGNATIONS
+ 101
.
flgi b
01-1 c
d
Fig. 4 - C04033A timing diBflram.
92S11-4471RS
DRAIN -TO-SOURCE VOL'IIYOO-VoHI
c
i:~
*
~=~ l:},1;'~~;:'T
I
CLOCK~"
fN~~~~152
IERESET
*
g
3
RBI 0 - - - - - - - - - - - - - < 1 . . . . - . /
VDD~
GNDOS
"-,,-----1:>;>0 RBO
*ALL INPUTS ARE PROTECTED4D
BY COS/MOS PROTECTION
__ _
NETWORK.
Vss
Fig. 3 - C04033A logiC diBgrom.
, Fig. 6 - Minimum and typiclll output p-chsnnsl
dtlcodtJd d",ln charBCtllrilticl " V 00-10
& 15V.
Fig. 5 - Minimum and typiclll output p-chsnnsl
decodsd drain chBractllrilticl. VOo-3.5
&5V.
Fig. 1- Typlclll output p-chonn.' dtlcodsd
dr.ln ChSrBCt&ri,tiC' 118. function
of tllmpeTllture.
Fig. B - Typical propagation delay tims
CL for docodod outpUI1i.
V$.
493
CD4026A, CD4033A Types
RECOMMENDED OPERATING CONDITIONS at TA = 25°C, Except as Noted.
For maximum rallability, nominal oparating conditionlshould be salectad 10 that
oparation is alwayl within the following rangel:
LIMITS
Voo
CHARACTERISTIC
IV)
Supply·Voltage Range (For TA = Full
Package·Temperatura Range)
Clock Inhibit
Setup Time, ts
Clock Pulse Width,
tw
Clock Input Frequency, tCL
Clock Risa or Fall Time, t,cL, ttcL
Reset Pulse Width,
tw
Reset Removal Time
D,F,H
PlICkBflllB
Min.! Max.
E
UNITS
PlICklllfllJ
Min. Max.
3
12
3
12
5
10
500
200'
700
300
5
10
330
170
-
-
5
10
5
10
oc' ',1.5
de
3
dc
dc
-
15
15
-
5
10
330
165
550
250
5
10
750
225
-
500
250
-
1
2
15
15
-
-
1000
275
-
V
p'
LOAO CAPACITANCE leL.1 -
ns
Fig. 9 - Tvpica' propagation delay time VB.
CL for corry output<.
ns
MHz
...... I[NT nMItERATURE IT" J -25-C
",ICAL TEMPERATURE COEffiCIENT ,0It
11500
p.s
ALL VALUES OF Voo·C'S"'·C
I
}
...
!-IOOO
ns
ns
"
STATIC ELECTRICAL CHARACTERISTICS
10
20
30
40
so
60
70
10
LOAD CAPACITANCE ICLI-pF
Limits.t Indicatad Temparatural (oC)
Conditions
Char_ristic
Cuiescent Device
Current IL Max.
Output Voltage:
Low-Level,
VOL
Vo Y,N VDD
(V) IV) IV)
-
- - 5
-
High Level.
VOH
Output Drive
Current
n-Channel
(Sink),
ION Min.
p-Channel
(Source),
lOP
Min.
Input Leakage
Current,
"L,"H
Decoded
Outputs
Carry
Output
Decoded
Outputs
Carry
Output
10
0
0
-
Noise Immunity:
Inputs Low,
VNL
Inputs High,
VNH
Noise Margin:
Inputs Low,
VNML
Inputs High,
VNMH
-
- -
5
10
16
50
100
600
0.5
1
5
1 Min.
5
10
5
10
5
10
5
10
5
10
- AT'nr
15
0.15
0.32
0.12
0.45
-0.21
-0.45
-0.12
-0.45
0.24 0.12
0.5 0.25
0.4 0.15
1
0.35
-0.28 -0.14
-0.6 -0_3
-0.4 -0.16
-1
-0.35
1 Min.
1 Min.
1 Min.
0.09 0.06
0.18 0.15
0.1 0.095
0.25
0.3
-0.1 -0.09
-0.22 -0.2
-0.1 -0.095
-0.25 -0.3
Fig. 10 - Typical transition time
decodod outpuu,
VB.
CL for
+85
700
1400
5000
jlA
V
3 Min.; 4.5 Typ.
1.5 Min.; 2.25 Typ.
3 Min.; 4.5 Typ.
5
60
100
600
Units
4.95 Min.; 5 Typ.
9.95 Min.; 10 Typ.
10
5
10
10
-
300
600
2000
1.5 Min.; 2.25 Typ.
-
6
10
60
5
-
-
0.3
0.5
1
-40
E PlICkaga
+25
Typ. Limit
o Typ.; 0.05 Max.
o Typ.; 0.05 Max.
5
9
-
5
10
60
10
6
10
4.5
0.5
1
0.5
0.5
0.5
0.5
4.5
9.5
4.5
9.5
D,F,H PlICklllfllJS
+25
+125
-55
Typ. Limit
V
V
0.24 0.06 0.05
0.5
0.12
0.1
0.4
0.08 0.06
1
0.25
0.2
·0.28 -0_07 -0_06
-0.6 -0.16 -0.13
-0.4 -0_08 -0.06
-1
-0.24 -0.2
±10-5 Typ., ± 1 Max.
mA
jlA
494 __________________________________________________________________
CD4026A, CD4033A Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C, Input t, ,t, = 20 nl, C L = 15 pF,
RL 2200k11
LIMITS
TEST
CONDITIONS
CHARACTERISTIC
Voo
(V)
E
D,F,H
Packages
Package/
UNITS
Min. Typ. Max. Min. Typ. Max.
CLOCKED OPERATION
5
Propagation Delay Time;
tPLH ,tPHl
Carry Out Line
-
350
1000
-
30
40
~o
60
LOAC CAPACITANCE IC l ) - pF
350 1300
ns
Decode Out Lines
Transition Time;
tTHl, tTlH
Carry Out Line
10
-
125
250
-
125
5
10
-
600
250
1700
500
-
600 2200
250 700
5
-
100
300
-
100
350
10
-
50
150
-
50
200
Maximum Clock Input
Frequency, tCl"
Min. Clock Pulse Width,
tw
Clock Rise & Fall Time;
trCl, ttCl
Min. Clock Inhibit Set
Up Time, ts
Average Input
Capacitance, CI
ns
~oo
!'lOO
~nn
-
11'00
125
350
-
125
450
5
1.5
2.5
-
1
2.5
-
10
3
5
-
2
5
-
5
-
200
330
200
500
10
-
100
170
100
250
-
-
-
175
75
15
15
500
200
175
75
15
15
700
300
5
-
-
5
-
5
10
5
10
Any Input
-
-
ns
MHz
ns
SUPPLY VOLTS (Vwl
JlS
Fig. 12 - Maximum input clock frequency vs.
VOO'
ns
pF
10
RESET OPERATION
Propagation Delay Time:
tPlH, tpHl
To Carry Out Line
5
10
5
10
5
10
5
10
Min. Reset Pulse Width
tw
Min. Reset Removal
Time
-
-
-
350
TOoo
125
250
550 1400
240 500
200 3JO
100 165
300 750
100 225
-
-
-
J60 1300
125
ns
1-
550 1900
240 600
200 500
100 250
300 1000
100 275
ns
ns
LQ-.D CAPIIIoI;ITAHCE
"'NL
M
I _, AND
".0."
AT EACH INPUT
5, 52 53 S4 5S
~
_
-
NOTE:
TEST ANYCONBINATION
104
10
102
lOS
INPUT CLOCI( FREQUENCY (tCLI- kHz
TEST P£fORM[O WITH THE FOLLOWINO
INPUTQVCOOUTPUTS
ICLI'I~pf
--CL'~OpF
ns
Fig. 13 - Typical dissipation charactrJristics.
SEQUENCE Of
"5S
tTAI·2~·C
300
.. Measured with respect to carry out line.
.
.....aIENT TEMPERATURE
INPUT'r'I,"ZOn,
To Decode Out Lines
VDD-~
(Of
ns
10
~
Decode Out Lines
Fig. 11 - Typical transition time vs. CL
corry output.
300
I
000
0
I
0
0
0
o
o
0
0
I
I
I
I
I
* DISCONNECT PIN 14
FOR
CD,~~s~IIOM.'
V~NPU(J'
... ;;";:,:.
TO BOTH liDO AHD Vss·
"SS
VSS
CONNECT ALL UHlIS[D
INPUTS TO EITHER
"00 atllSS ·
OF INPUTS
9ttS-27441
Fig. 14 - Noise immunity tBst circuit.
Fig. 15 - Quiescent-device-cUff'6nt test circuit.
Fig. 16 - ·Input-Ieakage-current test circuit.
495
CD4027 A Types
COS/MOS Dual J-K Master-Slave Flip-Flop
The RCA-CD4027A is a single monolithic
chip integrated circuit containing two identical complementary-symmetry J-K masterslave flip-flops. Each flip-flop has provisions
for individual J, K, Set, Reset, and Clock input signals. Buffered Q and
signals are
provided as outputs. This input-output arrangement provides for compatible operation with the RCA-CD4013A dual D-type
flip-flop.
a
The CD4027 A is useful in performing control; register, and toggle functions. logic
levels present at the J and K inputs along
with internal self-steering control the state
of each flip-flop; changes in the flip-flop
state are synchronous with the positive-going
transition of the clock pulse. Set and reset
functions are independent of the clock and
are initiated when a high level signal is present at either the Set or Reset input.
CD4027A
FUNCTIONAL DIAGRAM
MAXIMUM RATINGS,Absolute-Maximum Values:
STORAGE-TEMPERATURE RANGE IT51gl • • • • • . • • • • • • . • • • • • • • • • . • • . ..
-65 to +150"C
OPERATING-TEMPERATURE RANGE (TAl:
PACKAGE TYPES 0, F, H' ..•••..•.•••••••••••..••••.•••..••. -55 to +125°C
••••••••..••.••• , • • . • • • • • • • • • . • • • • • • • .• -40 to +s5"C
PACKAGE TYPE E
DC SUPPLY-VOLTAGE RANGE, (VDDI
(Voltagesreferenced to Vss TermineU: •••.•.•.•.••••••••..••••..•••• -0.5 to +15 V
POWER DISSIPATION PER PACKAGE (Pol:
FOR TA = -40 to +6Oo C (PACKAGE TYPE E)
• •• ••• ••• •. • •. •. •. ••••• •
500mW
FOR TA = +60 to +S5°C (PACKAGE TYPE~ EI
••••••• Derate Linearly at 12 mwfc to 200 mW
FOR T A --55to+l00"C (PACKAGETYPESD,FI •••••••..•••.•••••.•••
500mW
FOR TA = +100 to +125°C (PACKAGE TYPES 0, Fl •.•• Derate Linearly at 12 mwfC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR T A = FULL PACKAGE-TEMPERATURE RANGE (ALL PACKAGE TYPES!. • • • • •
100 mW
INPUT VOLTAGE RANGE, ALL INPUTS. • • • • • • • • • • • • • • • • • • • • • • . •• -0.5 to V DD +0.5 V
LEAD TEMPERATURE (DURING SOLDERINGI:
At distance 1/16 ± 1/32 inch 11.59 ± 0.79 mml from case for 10. max••••••••••••• ,
+265"C
RECOMMENDED OPERATING CONDITIONS at TA = 25'C, Except. Noted.
For maximum reliability, nominal operating conditions should be selected so that
operation is alwllYs within the fol/owing ranges.
VDD
(V)
D, F, If'
PACKAGES
E
PACKAGE
MIN.
MAX.
MIN.
3
12
3
Supply-Voltage Range (For TA = Full
Package-Temperature Range)
Data Setup Time, ts
5
10
150
50
Clock Pulse Width, tw
5
10
330
110
-
-
-
Features:
• Set-Reset capability
• Static flip-flop operation-retains state
indefinitely with clock level either
"high" or "low"
• Medium-speed operation-l0 MHz (typ.)
clock toggle rate at 10V
• Quiescent current specified to 15 V
• Maximum input leakage of 1 /-IA at 15 V
(full package-temperature range)
• I-V noise margin (full package-temperature range)
LIMITS
CHARACTERISTIC
These types are supplied in 16-lead hermetic
dual-in-line ceramic packages (0 and F
suffixes), 16-lead dual-in-line plastic package (E suffix), 16-lead ceramic!lat package
(K suffix), and in chip form (H suffix).
UNITS
Applications
•
Registers, counters, control circuits
MAX.
12
V
-
ns
200
75
-
500
165
-
-
ns
AMBIENT TEMPERATURE ITAl • 2S·C
TYPICAL TEMPERATURE COEF'ICIENT
30 fORID--o.:S"'·C
~
s:
B
Clock Input Frequency (Toggle
Mode) fCl
5
10
dc
Clock Rise or Fall Time, trCl,' tfCl
5
10
-
Set or Reset Pulse Width, tw
5
10
200
80
dc
1
3
MHz
15
5
-
15
5
/-IS
-
300
120
-
ns
1.5
4.5
-
"
10'
,
Fig. 1 - Typical n-channel drain characteristics.
*If more than one unit is cascaded in a parallel clocked operation, tpL should be made less than or equal to
the sum of the fixed propagation delay time at 15 pF and thp transition time of the output driving stage
for the estimated capacitive load.
496 __________________________________________________________________
CD4027A Types
DRAIN - TO - SOURCE VOlTS IVosl
-I~
STATIC ELECTRICAL CHARACTERISTICS
-~
-10
LIMITS AT INDICATED TEMPERATURES (oC)
CONDITIONS
CHARACTERISTICS
V IN VOO
(V) (V)
Vo
(V)
Quiescent Device
Current. IL Max.
Output Voltage:
Low Level,
VOL
High Level
V OH
Noise Immunity:
Inputs Low,
Noise Margin:
Inputs Low,
V NML
Inputs High,
V NMH
-55
TYP. LIMIT
0.005
1
60
10
0.01
10
140
2
120
20
0.05
20
280
15
25
0.5
25
1000
250
2.5
0.1
10
0.8
I
-
4.5
-
9
0.5
1
GATE - TO - SOURCE VOlTS lVoS' • - IS
p.A
250 2500
AMBIENT TEMPERATURE ITAJ" 2S"C
T\PICAL TEMPERATURE COEFFICIENT FOR IO"-O.S 'Yo'"C
o Typ.; C.OS Max
o Typ.; 0.05 Max
Fig. 3 - Ihf/;;::'i%~~~nel drain
5 Typ.; 4.95 Min.
5
O.lU 10
-
-I~ ~
TYP. LIMIT
0.005
0.5
•
+85
2
4.2
+25
1
5
-10 :
UNITS
-40
+125
5
0.5
9
Inputs High
V NH
+25
10
-
V NL
E PACKAGE
D. F. H PACKAGES
V
10Typ.; 9.95 Min.
2.25 Typ.; 1.5 Min.
5
10
4.5 Typ.; 3 Min.
5
10
2.25 Typ.; 1.5 Min.
AllBlENT TEMPERATURE ITA)" 25-C
TYPICAL TEMPERATURE COEFFICIENT FOR Io"-O.:S""-C
V
OATE - TO -SOURCE VOLTS IYOs)"15
4.5 Typ.; 3 Min.
5
1 Min.
10
1 Min.
5
1 Min.
10
, Min.
I '
V
Output Drive
Current:
N Channel
(Sink).
-
0.5
0.5
OAAIN -TO-SOUAa: VOLTS IVOS.
5
10
0.6! 1
1.2 2.5
-0.31 -0.5
0.5
1
0.35
0.75
1
2.5
0.35
0.72
0.3
0.6
0.24
0.5
ION Min.
P-Channel
rnA
4.5
-
5
9.5
-
10
(Source):
lOP Min.
Fig. 4 - Minimum n-channel drain
characteristics_
Input Leakage
Current,
-0.25 -O.I7E -0.17 ·0.5
-0.14 -0.12
I
-0.8
-1.3
r-------
-0.65 -0.45 -0.4
-1.3
-0.33 -0.27
-I'
-12'
CERAMIC PACKAGES
PLASTIC PACKAGES---
-10
m
.,
Any
Input
IIL·1IH
1
±10-5 ,Typ .• ±1 Max.
15
p.A
GATE - TO - sOtiitE VOLTS I
".~0IT~::::::::::::::::::::;:::::::::::::::::::::::::::t-
__-,
111'51
I" -III
AMBIENT TEMPERATURE ITAI- 2'"C
TYPICAL TEMPERATURE COEFfiCIENT
FOR I --O.:S"""C
_7.5
2ti""
"
0(, OV--'<-.-"
Ci.
•
CLOCK
DRAIN - TO - SOURCE VOLTS IVos'
Fig. 5 - Minimum p-channel drain
characteristics.
f'.....
CL
If'.....f
3(131~
~oo
*A~ :::t.
PRESENT SToto TE
INPUTS
J
5
R
I
X
0
0
)I
0
0
0
o
II
0
NEICT STATE
OUTPU
It
Q
o "
0
X
I
0
0
Ie
Ie
0
0
"
••
PROTECTED BY
COSIMOS PROTECTION
NETWORK
LOGIC I' HIGH LEVEL
LOGIC O' LOW LEVEL
x -
Fig. 2 -Logic diagram & truth table for CD4027A
(one of two identical J-K flip flops).
OON'TCl.llf
'0
00
eo
.0
LOAD C"p",CITANe£ ICLI-pF
Fig. 6 - Typical propagation delay
time vs. CLo
497
CD4027A Types
DYNAMIC ELECTRICAL CHARACTERISTICS
at 1A=25"C,lnputtr , t,=20ns,C L = 75pF, RL = 200 krl.
LIMITS
CHARACTERISTIC
D, F, H
PACKAGES
VDD
(VI
MIN. TYP.
Propagation Delay
Time: Clock to a
or Q Outputs
tPHL, tPLH
Set to
a or Reset to a,
tpLH
Set to
a or ,Reset to a,
tpHL
Transition Time
tTHL. tTLH
Maximum Clock Input
Frequency (Toggle
Mode)fCL
TYP.
MAX.
-
150
400
75
150
-
175
350
75
150
1
3
175
75
75
350
150
50
140
-
165
500
65
125
165
50
300
120
MAX. MIN.
5
-
200
400
10
-
100
200
5
-
175
225
10
2.5
110
5
10
-
175
75
225
5
10
-
75
110
125
50
70
5
10
1.5
4.5
-
3
8
UNITS
E
PACKAGE
-
3
8
ns
Fig.7 - Tvpical transition time
Vs.
CL.
ns
ns
250
ns
MHz
-
SUPPLY VOLTS (Yoo!
5
Minimum Clock Pulse
Width,tw
10
Minimum Set or
Reset Pulse Width,
5
10
-
165
50
80
-
70
150
-
70
200
25
50
-
25
75
15
-
330
110
65
125
200
Fig.S - Typical maximum clock input frequency
ns
VB. supplV voltage.
ns
.....ENT TfIlPEJiATURE IT""15-C
INPUT 'r'tf ·lOn.
tw
5
Minimum Data Setup
Time, ts
10
10
-
Any
Input
-
5
Clock Rise or Fall
Time, trCL' tfCL
Average Input
Capacitance, CI
-
5
5
'
-
-
-
ns
15
5
5
-
us
~ 10
pF
,0'
10'
10"
10 5
10'
INPUT FREDUENCY!t,)- HI
'0'
82CS·t18021t2
Fig.9 - Typical dissipation characteristics:
Voo
'NPUTOVOOouTPUTS
O
V :};-
NOT(
T[ST ANY ~[INPUT,
,
1
V~NPU(J'
.. =::::'
Vss
WITH ODIER INPUTS AT
INPUTS
TO BOTH Voo AND Yss'
CONNIECT ALL UNUSED
.
IWUTS 10 EITH[R
Voo CRVSS '
Vss
.
VSS
.
1,
Vss
Veo OAVss
Fig. 10 - Noise immunity test circuit.
Fig. 11 - Input leaksgs current test circuit.
Fig. 12 - Ouie$CfJnt device cummt test circuit.
498 __________________________________________________________________
CD4028A Types
COS/MOS
BCD-to-Decimal Decoder
VDD
o through
7 to go low. If unused, the 0
input must be connected to VSS. High drive
capability is provided at all outputs to en·
hance dc and dynamic performance in high
fan·out applications.
The RCA·CD4028A types are BCD·to·
decimal or binary·to·octal decoders consist·
ing of pulse·shaping circuits on all 4 inputs,
decoding·logic gates, and 10 output buffers.
A BCD code applied to the four inputs, A to
0, results in a high level at the selected one
of 10 decimal decoded outputs. Similarly, a
3·bit binary code applied to inputs A
through C is decoded in octal code at output
to 7. A high·level signal at the 0 input
inhibits octal decoding and causes outputs
"
B'D
INPUTS
12
~
,
.4
2
D
~J'~~S
;
6
~~~~J:~O
7
OECOO[O
7 •
OUTPUTS
9
"
OfCOCEO
:~
., '
C
'U'''''D
OCTAL
1
(,
LIOl'"IOI
VSS
These types are supplied in 16-lead hermetic
dual-in-line ceramic packages (0 and F
suffixes), 16-lead dual-in-line plastic package (E suffix), 16-lead ceramic flat package
(K suffix), and in chip form (H suffix).
o
. ~
o
1~=~~~'D •
CD4028A
FUNCTIONAL DIAGRAM
MAXIMUM RATINGS, Absolute·Maximum Values:
STORAGE·TEMPERATURE RANGE (Tstgl
•.•...•.•.......•...•..
-6S to +150'C
Features:
-6S to +12S'C
•
OPERATING·TEMPERATURE RANGE (TAl:
PACKAGE TYPES D, F,H
PACKAGE TYPE E
. . . . . -40 to +8S'C
DC SUPPLY·VOLTAGE RANGE, IVDD)
(Voltages references to VssTerminaU
. . . . . . . . . . . • • . . . . . . . . . . . . . . . . . -0.5 to +15 V
POWER DISSIPATION PER PACKAGE (PD):
FOR TA
= -40 to +60'C
(PACKAGE TYPE E I
. . • . . . • • . . . . . . . . . . . . . . . . • SOOmW
FOR TA = +60 to +8S'C (PACKAGE TYPE E I
. . . . . . Derate Linearly at 12 mWrC to 200 mW
__ __ __ __ __ __ __ __ __ __ __. SOO mW
FOR TA = -5S to +100'C (PACKAGE TYPES D, F)
FOR T A
= +100 to +12S'C
(PACKAGE TYPES D, F)
... Derate Linearly at 12 mWrC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA
= FULL PACKAGE·TEMPERATURE RANGE (ALL PACKAGE TYPES)
INPUTVOLTAGERANGE,ALL INPUTS
BCD·to-decimal decoding or binary·to-octal
decoding
• High decoded output drive capability •••
••. 8 mA (typ.) sink or source
D "Positive logic" inputs and outputs •..
•.• decoded outputs go high on selection
• Medium-speed operation •..
••. tTHL, tTLH = 30 ns (typ.) @VDD = 10 V
•
•
. • • . • . . 100 mW
. • . . • . . • . . . . • . . . . . . . . . . • . -{}.StoVDD+O.SV
•
LEAD TEMPERATURE (DUR ING SOLDER ING):
At distance 1116 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max, . . . . . . . : . . . . ..
+26SoC
Applications:
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges:
•
•
LIMITS
CHARACTERISTIC
VDD
(V)
Supply·Voltage Range (For T A=Full
Package·Temperature Range)
Quiescent current specified to 15 V
Maximum input leakage current of 1 /-lA
at 15 V (full package·temperature range)
1·V noise margin (full package·temper'
ature range)
•
E
PACKAGE
D, F,H
PACKAGES
MIN.
MAX.
MIN.
MAX,
3
12
3
12
Code conversion
Address decoding-memory selection
control
Indicator·tube decoder
UNITS
V
DRAIN-TO-SOURCE 'oQ.T51\/OSI
-I'
-10
-s
0
D
D
Fig. 1 - Typical output n-channel drain
characteristics.
Fig.
2 - Typical output p-channel drain
characteristics.
m
~
LOAD
~
~
00
~
CAMCITANCEICLI-p~
-
-
Fig. 3 - Typical propagation delay time
vs. CL.
499
CD4028A Types
TABLE I - TRUTH TABLE
DeB A 0 1 2 3 4 5 6 7 B 9
2
>--------o2
12*
co---+----\
£\
DD
--
0
0
1
1
o
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
1
0
0
0
o
o
0
0
0
0
0
1
o
o
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
o
o
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
o
0
0
1
0
0
o
o
o
0
0
0
0
0
1
o
0
0
0
0
0
0
0
0
0
1
1
1
0
o
I 1
I 1
o
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
o
o
o
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
o
0
1
0
1
0
1
o
o
0
0
0
0
0
0
1
1
0
0
0
o
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
*
**
* WHERE I HIGH LEVEL
0= LOW LEVEL
* * EXTRAORDINARY
=
*PROTECTED
AU. INPUTS ARE
BY
COS/YOS PROTECTION
STATES
NETWORK
vss
Fig. 4 - Logic diagram.
STATIC ELECTRICAL CHARACTERISTICS
LIMITS AT INOICATEO TEMPERATURES (oC)
CONDITIONS
0, F, H PACKAGES
CHARACTERISTIC
Vo
IV)
Quiescent Device
Current,ll Max.
High Level
VOH
Noise Immunity:
Inputs Low,
VNL
Inputs High
VNH
+25
125
+85
-40
TYP. LIMIT
TYP. LIMIT
-
5
5
5
300
50
5
-
-
10
10
1
10
600
100
10
100 1400
15
50
1
50
2000
500
10
500 5000
0.5
-
5
5
-
10
10
oTyp.; 0.05 Max.
oTyp.; 0.05 Max.
-
0
5
4.95 Min.;5 Typ.
0
10
9
-
10
0.8
-
5
42
700
"MBlEINT TEIlPE"ATUREIT",o2S-C
LOAD CAPACITANCECCL
V
5
1 Min.
VNML
9
-
10
1 Min.
Inputs High,
0.5
5
1 Min.
VNMH
1
-
10
1 Min.
3 Min.;4.5 Typ.
Fig. 6 - Maximum propagation delay time vs.
VDD·
V
VOO'IOV
~
10'
',·',S 20ft,
r~~~\JfSI
~~
0.5
-
5
0.75
1.2
0.6
0.45
0.35
1.2
0.3
0.25
0.5
-
10
1.5
2.4
1.2
0.9
0.7
2.4
0.6
0.5
4.5
-
5
-0.7
-0.9 -0.45 -0.32 -0.32 -0.9 f-o.22 -0.18
10
-1.4
-1.9 -0.95 -0.65 -0.65 -1.9 -0.48 -0.4
9
~~
r:
to"
~~
rnA
Inpul Leakage
500
Co (ALL OUTPUTSI • !I pI'
I
f
Output Drive
IIL,IIH
'0" ,,.
1.5 Min.; 2.25 Typ.
10
Current,
CL.
1.5 Min.; 2.25 Typ.
-
P·Channel
(Source),
lOP Min.
time~.
3 Min.; 4.5 Typ.
-
Current
N-Channel
(Sink),
ION Min.
Fig. 5 - Typical transition
I1A
9.95 Min.; 10Typ.
5
1
Inputs Low,
50
V
4.5
Noise Margin:
UNITS
E PACKAGE
-
Output Voltage:
Low·Level,
VOL
VIN VOO -55
(V) (V)
I
+25
IL~-"",,=+loj
- TI
- T '15
±10-' Typ., ±1 Max.
10 4
FREQUENCY lfl-tu
p.A
Fig. 7 - Dissipation vs. input frequency.
,...
CD4028A Types
DYNAMIC ELECTRICAL CHARACTERISTICS
at TA = 2SOC, Inputt" tf = 20 ns, CL = 75 pF, RL = 200 k£l.
LIMITS
TEST
CONDITIONS
,--VDD
CHARACTER ISTIC
(VI
Propagation Delay
Time;
tPLH, tPHL
Transition Time;
trHL. tTLH
D,F,H
PACKAGES
MIN. TYP. MAX. MIN.
700
100
290
60
300
75
-
30
150
-
-
5
-
10
-
100
180
5
-
60
150
30
-
5
Any Input
INPUTS
480
.. (Trademark) Burroughs Corp.
TYP. MAX.
250
-
250
UNITS
-
5
10
Average Input
Capacitance, CI
E
PACKAGE
ns
TRANSISTOR CHARACTERISTICS
l .......'thtt_I1Q.(UIQII '!>.OO!imA
ns
VrBRICEO
92CS-1129)R2
2:: rov
Fig. 9 - Neon readout (Nix.ie Tube")
display application.
pF
VDO
The circuit shown in Fig. 9 converts any 4·
bit code to a decimal or hexadecimal code.
Table 2 shows a number of codes and the
decimal or hexadecimal number in these
codes which must be applied to the input
terminals of the CD4028A to select a partic·
ular output. For example: in order to get a
high on output No. 8 the input must be
either an 8 expressed in 4·8it Binary code, a
15 expressed in 4·Bit Gray code, or a 5 ex·
pressed in Excess·3 code.
116 CD40698
92("5
INPUTS
Fig. 8 - Code conversion circuit.
Fig. 10 - Quiescent-device-current
test circuit.
TABLE II - CODE CONVERSION CHART
INPUT CODES
Hex8_
,Decimal
Decimal
INPUTS
CO>
en !II> z_
0:
w
I-
-O~ORI
CD4031A
FUNCTIONAL DIAGRAM
STORAGE-TEMPERATURE RANGE (Tstg ) . . . . . . . . . . . . . . . . . . . . . . . . . .
OPERATING·TEMPERATURE RANGE (TA):
PACKAGE TYPES 0, F. H
CLOCK2
3
5
100
10
200
5
2.5
10
I
MAX.
MIN.
12
-
MINIMUM~
E
PACKAGE
3
MAX.
12
100
-
200
'1.3
-
2.6
5
dc
0.8
de
0.4
10
de
2
de
1
5
-
2
-
2
10
1
UNITS
1
Fig. 1 -
V
DRAIN-TO-SCWACE VOLTS IVos'
Typical and minimum output n-channef
drain characteristics for Q output,
ORAIN-TO-SOURCE VOlTS'VOS'
-15
-10
-,
0
ns
Ils
MHz
J,tS
* If more than one unit is cascaded in the parallel clocked application, trCL should be made less than or equal
to the sum of the propagation delay at 15 pF and the transition time of the output driving stage.
°°
Fig. 2 - Typical output p-chsnneJ drain characterI isrics for Q output.
_________________________________________________________________ 507
CD4031A Types
STATIC ELECTRICAL CHARACTERISTICS
A~IENT
TEMPERATURE nAI·Z~·C
TYPICAL TEMPERATURE COEFFICENT FOR
ALL VALUES OF Voo' 0 l "10 ("C
LIMITS AT INDICATED TEMPERATURES (oC)
CONDITIONS
CHARACTERISTICS
Quiescent Device
Current, I L Max.
Output Voltage:
Low level,
-
-
VOL
5
5
10
E
0, F, H PACKAGES
Vo VIN Voo
-55
(V) (V) (V)
+25
TVP. LIMIT
600
50
1
50
700
10
0.5
10
10
25
1
25
1500 100
2
100
1400
15
50
1
50
2000 500
5
500
5000
4.95 Min.; 5 Typ.
9
-
10
Inputs High
VNH
0.8
-
5
1
-
10
3 Min.; 4.5 Typ.
Noise Margin:
4.5
-
5
1 Min.
9
10
1 Min.
0.5
-
5
1 Min.
1
-
10
1 Min.
0.4
-
Inputs Low,
VNML
Inputs High,
VNMH
Output Drive
Current:
N·Channel
(Sink),
Q
Q
ION Min.
I
CLO
p- Channel
(Source):
Q
lOP Min.
Q
CLO
2.6
1.3
0.91
1.6
2.6
1.3
1.05
4
4
3.2
5
8
3.2
5
8
0.18 0.09
0.06
0.05
0.18 0.045 0.037
0.5
10
0.24
0.4
0.2
0.14
,0.12
0.4
0.1
0.08
4.5
-
9.5
-
10
5
0.48
0.8
0.4
0.28
0.24
0.8
0.2
0.16
10
1.5
2.4
1.2
0.84
0.75
2.4
0.6
0.5
5
-0.4
-0.64 -0.32 -0.22 -0.20 -0.64 -0.16 -0.13
10
-0.85
-1.4
5
-0.11
-0.18 -0.09 -0.06 -0.05 -0.18 -0.045 0.037
10
-0.24
-0.4
-0.20 -0.14 -0.12 -0.4 -0.10
5
-0.48
-0.8
-0.40 -0.28 -0.24 -0.8 -0.20 -0.16
-1
-1.6
-0.80
Tlnr
15
-
:::i
.".
~g.
g"'"
.~
::7:~
~ 2oo'II~::~:~:~!~::;:E:~:~::t::i"~~±: :±:~:t::ct;f:~:8::
:,~
0.11
Input Leakage
Current,
IIL,IIH
V
5
9.5
.:':
;,uP!!:
10
4.5
-Il't'1::' ""'
or
AMBIENT TEMPE;R"ATURE ITAI'Z;OC
TYPICAL TEMPERATuRE COEFFICENT FO'"
ALL VALUES
VOO'Ol't"I"C
I
-
9.5
Typical propagation delay time vs, load
capacitance for data outputs.
!!1I!!!1I!l! :!~! i 11
!,ooltHWliiijj)ii: iii: :::;~
~ 400'l:i±l::!±l:±tfthl+t
¥.+~;ff~: :::: ::::
1.5 Min.; 2.25 Typ.
-
4.5
Fig. 3 -
V
0.5
0.5
'"
LOAD CAPACITANCEtCL1-pF
-L,.MO CAPACITANCE OF G~II!i,F
1.5 Min.; 2.25 Typ.
0.5
0.5
-LOAD CAPACITANCE OF 1)'15pF
3 Min.; 4.5 Typ.
4.5 1.6
,j,H.
'"
o·
p.A
V
9.95 Min.; 10 Typ.
5
I~
:tHltHl!! !!!!
5
4.2
. ... ,
'0
o·
60
10
Inputs Low.
VNL
..
o Typ.; 0.05 Ma.
o Typ,; 0.05 Ma.
0
Noise Immunity:
TVP. LIMIT
iff
o·
+85
-40
5
10
Iv~·~14
SlJPPI.:r VOl..TS
UNITS
+25
+125
0
High Level
VOH
PACKAGE
f I~
•
..
:.:: :::: ::::
•• '..
~ni
t • • ,~
2:
••••
""
"" .... :::: :::: .........
60
70
LOAD CAPACITANCE 1Cll-pF
Fig. 4 - Typical propagation delay 1fS. load capacitance for delayed clock output.
mA
-0.70 -0.49 -0.42 -1.4 -0.35 -0.29
-0.56
-0.5
0.08
-1.6 -0.40 -0.32
±10-5 Typ., ±1 Max.
p.A
lOAO CAPACITANCE ICLI-pF
.2CS_II?41
NOTE: fTILFOR Q OUTPtlT 15 StI;Mf'fCAIf1'LT LESS THAN tTLH
Fig. 5 - Typical transition time vs. load capacitance for data outputs.
MOO.
CONTROL;
E
RECIRCUL~A~TI~O~N- - t . . . . /
DATA
L
REtiRe.
.
MODE
BIT INTO
STAGE I
CL
Ci
Cl:t
£\
0
CLO
0
00
*ALL INPUTS ARE
PROTECTED BY
COS/MOS PROTECTION
NETWORK
l200~~~~~~~~~~~~~~:~
TYPICAL STAGE TRUTH TABLE
--
VSS
1
.
x
CL
...r
...r
\...
~
0+1
~
X· DeNT CARE
0
1
Input to Output is:
la)
Input 1 is "Low" and Control Input 2 is
"High"
NC
N.· NO CHANGE
X: DON'T CARE
A Bidirectional Short Circuit when Control
(b)
An Open Circuit when Control Input 1 is
~
='00
~
.
o
,.
LOAD CAPACITANCE tCL 1_ pF
"High" and Control Input 2 is "Low"
Fig, 7 - Logic diagram and truth tables.
Fig. 6 - Typical transition time VS. load capaci·
tance for delayed clock output.
508 _________________________________________________________________
CD4031 A Types
DYNAMIC ELECTRICAL CHARACTERISTICS
at TA=25 0 C, Input t r,tt=20 ns, CL =15 pF (unless otherwise specified), RL =200
TTPICAL TEMPERATuRE COEFFICENT FOR
ALL VALUES OF VOo.O '°Iol°C
CONDI~
D, F, H
IV)
MIN.
5
-
400
BOO
-
400
1600
j'"
10
_.
200
400
-
200
BOO
TYP.
MAX.
MIN. TYP.
g
,d ,
MAX.
~
Propagation Delay Time:
tpLH. tpHL
Clock to Data
Output Q& 0*
5
CL = 60pF 10
-
400
BOO
-
400
1600
-
200
400
-
200
BOO
ns
o
o
10
tTHL' tTLH
Q Output
5
-
75
150
-
75
10
-
30
60
-
30
120
5
-
300
600
-
300
1200
10
-
150
300
-
150
600
-
200
400
BOO
100
200
100
400
10
-
-
1
-
200
-
Minimum Data Set-Up
Time,ts
5
-
200
400
-
200
BOO
10
-
50
100
-
50
200
Maximum Clock Input
Frequency,lCl
5
O.B
2
-
0.4
2
-
10
2
4
-
1
4
-
5
-
50
100
-
50
100
10
-
100
200
-
100
250
5
-
1.25
2.5
1
-
eOutput
CL=60pF
5
10
5
Clock Rise and Fall Time;
trCL, tICL' ,
Minimum Data Hold
Time,tH
Minimum Clock Pulse
Width,tW
10
Average Input Capacitance, Cl Clock
2
-
0.5
-
60
-
5
AM81ENT TEMPERATURE ITA"2~'C
300
-
ns
2
-
1
1.3
I~
10
SUPPt..'I' \lOLlS 'Vool
Fig, 8 - Maximum clock input frequency vs.
supply voltage.
Transition Time;
CLD Output
'T"
UNITS
E
VDD
Clock toCLD
•
•
':[::;,
::::
t.:! ........
LIMITS
TEST
CHARACTERISTIC
mUm".!r:; ....
.:::
AM8IENTTEMPERATUREITAI'2~'C
kn
2.6
-
0.62
-
60
-
-
5
-
1.3
Ils
CLOCI( FREQUENCY (lCLI-HI
ns
Fig. 9 - Typical power dissipation vs. frequency.
MHz
INPUTOVOO
OUTPUTS
VOO'VNH
ns
~
'--
:t
V:L
p.s
HOTE:
TEST ANY ONE INPUT,
Vss
WITH OTHER INPUTS AT
9lCS-l1400
All Others
-
Voo ORVss·
pF
a:
. . Capacitive loading on output affects propagation delay of Q output. These limits apply for 0: load
Cl .. 15pF.
** If more than one unit is cascaded in the parallel clocked application, treL should be made less than or
equal to the sum of the propagation delay at 15 pF and the transition time of the output driving stage.
. . ** Maximum Clock Frequency for Cascaded Units;
Fig. 10 - Noise-immunity test circuit.
V~~"OUS
Voo :~:~U"
o ~
'NPuTS
SEQUENTIALLY,
TO BOTH VOoAHOVss
CONNECT ALL UNUSED
INPIJTS It)EITHER
Vss
a) Using Delayed Clock Feature -
"00 CRVSS
V55
f max = In-1) CLO prop. delay
+ Q prop. delay + set-up time where n = number of packages
Fig. 11 - Input-leakage-current test circuit.
bl Not Using Delayed Clock _ f
~
*ALl. INPUTS ARE
Vss
PROTECTED 8Y
COSI MOS PROTECTION
NETWORK
max
=
1
propagation delay + set-up time
*'
RECIRCULATION
IN
Fig. 12 - Functional diagram.
WITH SI AT GROUNO,CLOCK UNIT 64 TIMES
BY CONNECTING S2 TO PULSE GENERATOR
RETURN 52 TO GNO AND MEASURE LEAKAGE
CURRENT. REPEAT WITH 51 AT VDD
Fig. 13 - Ouiescent-device-current test circuit.
509
CD4032A, CD4038A Types
COS/MOS Triple Serial Adders
Features:
Positive Logic Adder - CD4032A
• Invert inputs on all adders for sum complementing
applications
• Fully static operation . . . . . . dc to 5 MHz (typ.)
• Buffered outputs
• Single-phase clocking
• Microwatt quiescent power dissipation . . . . 5/lW (typ.)
Negative Logic Adder - CD4038A
The RCA-CD4032A and CD4038A types
consist of three serial adder circuits with
common CLOCK and CARRY·RESET in·
puts. Each adder has two provisions for two
serial DATA INPUT signals and an INVERT
command signal. When the command signal
is a logical "1 ", the sum is complemented.
Data words enter the adder with the least
significant bit first; the sign bit trails. The
output is the MOD 2 sum of the input bits
plus the carry from the previous bit position.
The carry is only added at the positive-going
clock transition for the CD4032A or at the
negative-going clock for the CD4038A, thus,
for spike free operation the input data transitions should occur as soon as possible after
the triggering edge.
The CARRY is reset to a logical "0" at the
end of each word by applying a logical "1"
• Quiescent current specified to 15 V
• Maximum input leakage current of 1 /lA
at 15 V (full package-temperature range)
• 1-V noise margin (full package-temperature range)
signal to a CARRY·RESET input one bit·
position before the application of the first
bit of the next word. Figs. 2 and 4 show
definitive waveforms for all input and output
signals.
These types are supplied in 16-lead hermetic
dual-in-line ceramic packages (D and F
suffixes). 16-lead dual-in-line plastic package (E suffix), 16-lead ceramic flat packages
(K suffix). and in chip form (H suffix).
MAXIMUM RATINGS, Absolute·Maximum Values:
'2C5-17'"
FUNCTIONAL DIAGRAM
Applications:
• Serial arithmetic units
• Digital correlators
• Digital datalink computers
• Flight control computers
• Digital servo control systems
STORAGE·TEMPERATURE RANGE (Tstgl
OPERATINT GEMPERATURE RANGE (TAl:
~55 to +125°C
PACKAGE TYPES D. F. H
PACKAGE TYPE
-40 to +8SoC
E
DC SUPPLY-VOLTAGE RANGE. IVDDI
-0.5 to +15 V
(Voltages referenced to VSS Terminal)
POWER DISSIPATIDN PER PACKAGE (PDI
FOR TA
FOR T A
FOR TA
FOR T A
= -40 to +600 C (PACKAGE TYPE EI
= +60 to +85°C (PACKAGE TYPE E I
= -55 to +1000 C (PACKAGE TYPES D. FI
= +100 to +125°C (PACKAGE TYPES D. F)
500mW
Derate lmearlv at 12
mwtC to 200 mW
500 rhW
Derate linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR T A = FULL PACKAGE-TEMPERATURE RANGE (ALL PACKAGE TYPES)
100 mW
INPUT VOLTAGE RANGE. ALL INPUTS
0.5 to V DD '0.5 V
LEAD TEMPERATURE (DURING SOLDERINGI:
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mml from case for lOs max.
Fig. 1 -
RECOMMENDED OPERATING CONDITIONS at TA = 25°C, Except as Noted.
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges:
Typical propagation delay time vs. load
capacitance for A, 8, or INVERT inputs
to sum outputs.
LIMITS
CHARACTERISTIC
VDD
(V)
Supply·Voltage Range (For TA =
Full Package· Temperature Range)
D,F,H
Packages
E
Package
Min.
Min.
Max.
UNITS
Max.
3
12
3
12
V
Input Setup Time, ts
5
10
trCl
-
trCl
-
ns
Clock Input Frequency, fCl
5
10
dc
dc
1.5
3
dc
dc
2.5
5
Clock Rise or Fall Time, trCl, tfCl
5
10
-
510
-
15
15
-
15
15
MHz
/lS
Fig. 2 - Typica/.transition time vs.load capacitance
for sum outputs,
CD4032A, CD4038A Types
tt = 20 ns,
=15 pF, RL = 200 kS2
NlllEJlrT[MPERATUII[ (T,)025'(
INPUT Ir'ft-ZOn.
LOAD CAPACITANCE CCLlol!lpF
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C, Input t r,
CL
SUPPLY VOLTS eYOOI-',
LIMITS
CHARACTERISTIC
VDD
(V)
10
D, F, H
Packages
TEST CONDITIONS
UNITS
E
Package
Min. Typ. Max.
Min. Typ. Max.
Propagation Delay
Time;
,,-I-
tpLH' tpHL
A. B. or Invert
Inputs to Sum
Outputs
5
-
400
1100
-
400
1400
10
-
125
250
-
125
300
Clock Input
to Sum Outputs
5
-
800 2200
10
250
500
-
250
600
5
-
125
375
125
425
10
-
50
150
50
200
Transition Time;
tTHL' tTLH
(Sum Outputs)
Maximum Clock Input
5
1.5
Frequency, fCL
10
3
5
Clock Rise & Fall
Time;
trCL, tfCL··
5
-
10
-
-
-
-
Minimum Input Set Up
Time. tS·
-
2.5
-
1
800 2400
2.5
2
5
WORD
ns
MHz
-
15
-
15
trCL
-
-
-
-
WORD Z
RESET
SUM
IJS
WOAD I 0.0111100-+60
WORD 2 0.0110010· +50
WORD! 1.10110110-37
WORD 4 LlOOII 10--50
0.1101110"110
1.010100'*-81
Fig. 4 -
5
10
Average Input
Capacitance. CI
-
5
5
trCL
ns
-
pF
-rhis characteristic refers to the minimum time required for the A, B. or Reset I"puts to change state
following a positive c.1ock transition (CD4032A) or negative transition (CD4038A).
"If more than one unit is cascaded trCL should be made less than or equal to the sum of the transition
time and the fixed propagation delay of the output of the driving stage for the estimated capacitive
load.
WORD 3.WORO 4
-HH-I-J.-J.-+-+...fIIIIIIH
CAllRY
-
,+
CL
INVERT
-
15
15
Fig. 3 - Typical dissipation characteristics.
ns
CD4032A timing diagram.
CL
INVERT
-t-t-t-t-t-t-t-,
CARRY
QESET
SUM
WORD I 1.1000011 =-61
WQR02 1.1001101 :-51
1.0010000 "-lJ2
WORD 3 0.0100100 =+36
WORD 4 0.0110001 "+49
0.1010101 "+85
Fig. 5 - CD4038A timing diagram.
**AI==fIiiTDT-DE~if!'-;-~=====~-~-----r-~-=::
-->--C->-----~1'~
B,
'SUM
,1
*
..
5
CARRY
RESET
CLOCK
y>~~:>-
___~___
;»-,-j>-----t--
l !~DERS
* ALL
INPUTS ARE PROTECTED
BY COS/MOS PROTECTION
DD
20.
*ALL. INPUTS ARE PROTECTED
BY COSINOS PROTECTION
NETWORK
2.>
NETWORK
l~gDERS--
VSS
YSS
92CS' 1166 LAl.
Fig. 6 - C04032A logic diagram of one of three serial adders.
Fig. 7 - CD4038A logiC diagram of one of three
serial adders.
511
CD4032A, CD4038A Types
STATIC ELECTRICAL CHARACTERISTICS
Limits at Indicated Temperatures (oCI
Conditions
Characteristic
Vo
IV)
Quiescent Device
Current I L Max.
-
Output Voltage:
Low· Level
VOL
VIN VDD -55
(VI (VI
-
-
+25
+125
Units
+85
Typ. Limit
Typ. Limit
5
5
0.3
5
300
50
50
700
10
10
0.5
10
600
100
1
100
1400
15
50
1
50
2000
500
5
500
5000
5
5
-
10
10
o Typ.; 0.05 Max.
o Typ.; 0.05 Max.
-
0
5
4.95 Min.; 5 Typ.
-
0
10
9.95 Min.; 10 Typ.
Noise Immunity:
Inputs Low.
4.2
Package
+25
-40
-
High Level
VOH
-
5
VNL
9
-
10
Inputs High
0.8
-
5
VNH
1
-
10
Noise Margin;
Inputs Low.
E
0, F, H Packages
0.5
p.A
V
1.5 Min.; 2.25 Typ.
3 Min.; 4.5 Typ.
V
1.5 Min.; 2.25 Typ.
3 Min.; 4.5 Typ.
4.5
-
5
1 Min.
VNML
9
-
10
1 Min.
Inputs High.
0.5
5
1 Min.
VNMH
1
-
10
1 Min.
0.5
-
5
0.6
0.9
0.5
0.3
0.25
0.9
0.2
0.14
0.5
-
10
0.75
2.4
0.7
0.6
0.6
2.4
0.5
0.4
P·Channel
(Source).
4.5
-
IDP Min.
9.5
-
V
Output Drive
Current
N·Channel
(Sink).
IDN Min.
Input Leakage
-0.4 -0.15 -0.075 -0.14
-7.2 -0.55 -0.35
-0.3
-0.4 -0.1
-0.095
-1.2 -0.27 -0.22
Any Input
Current,
IIL.IIH
5 -0.21
10 -0.7
mA
-
-
p.A
±10- 5 Typ., ±1 Max.
15
INPUTS
o
Vss
IL
VD:~~~O~-~
Yoo
INP(J~VDD
~
NOTE:
MEASURE INPUTS
SEQUENTIALL.Y.
o ~
Vss
TO BOTH "'OD AND Vss'
CONNECT ALL UNUSED
INPUTS TO EITHER
9ZC$-Z7441
Fig',8 - Quiescent-device-current test circuit.
512
Vss
NOTE:
~N~~~ONBINATION
Fig. 9 - Noise-immunity test circuit.
Voo ORVsS '
Vss
92CS-2140l
Fig. 10 - Input-leakage-current test circuit.
CD4034A Types
COS/MOS a-Stage Static Bidirectional
Parallel/Serial Input/Output Bus Register
The RCA·CD4034A is a static eight·stage
parallel·or serial·input parallel·output regis·
ter. It can be used to:
1) bidirectionally transfer parallel informa·
tion between two buses, 2) convert serial
data to parallel form and direct the parallel
data to either of two buses, 3) store (recircu,
late) parallel data, or 4) accept parallel data
from either of two buses and convert that
data to serial form. Inputs that control the
operations include a single·phase CLOCK
(Cl), A DATA ENABLE (AE), ASYNCHRO·
NOUS/SYNCHRONOUS (A/S), A·BUS·TO·
B·BUS/2B·BUS·TO·A·BUS (A/B), and PAR·
AllEL/SERIAl (P/S).
Data inputs include 16 bidirectional parallel
data lines of which the eight A data lines are
inputs (outputs) and the B data lines are out·
puts (inputs) depending on the signal level
on the A/B input. In addition, an input for
SERIAL DATA is also provided.
All register stages are D·type master·slave
flip·flops with separate master and slave
clock inputs generated internally to allow
synchronous or asynchronous data transfer
from master to slave. Isolation from external
noise and the effects of loading is provided
by output buffering.
PARAllEL OPERATION
A high PIS input signal allows data transfer
into the register via the parallel data lines
synchronously with the positive transition
pf the clock provided the A/S input is low.
If the A/S input is high the transfer is in·
dependent of the clock. The direction of
data flow is controlled by the A/B input.
Whim this signal is high the A data lines are
inputs (and B data lines are outputs); a low
A/B signal reverses the direction of data flow.
The AE input is an additional feature which
allows many registers to feed data to a
common bus. The A DATA lines are enabled
only when this signal is high.
Data storage through recirculation of data in
each register stage is accomplished by mak·
ing the A/B signal high and the AE signal
low.
SERIAL OPERATION
A low PIS signal allows serial data to transfer
into the register synchronously with the
positive transition of the clock. The A/S in·
put is internally disabled when the register is
in the serial mode (asynchronous serial opera·
tion is not allowed).
* ENABLE
-A-
The serial data appears as output data on
either the B lines (when AlB is high) or the
A lines (when A/B is low and the AE signal
is high).
* AlB
*tft PIS
AlS
.. CLOCK
I
a
Register expansion can be accomplished by
simply cascading CD4034A packages.
DATA
92tS-ltZOZRI
Fig. 1 - Functional diagram.
The CD4034A-Series types are supplied in
24-lead hermetic dual-in-line ceramic packages (D suffix), 24-lead dual-in-line plastic
packages (E suffix), 24-lead ceramic flat
packages (K suffix), and in chip form (H
suffix).
~DD
fvss
*PROTECTED
ALL INPUTS ARE
BY
COSIMOS PROTEcnON
NETWORK
MAXIMUM RATINGS, Absolute·Maximum Values:
STORAGE·TEMPERATURE RANGE (T stg ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-6S to + IS0"C
OPERATlNG·TEMPERATURE RANGE (T A ):
PACKAGE TYPES D. H
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -SS to +12S"C
PACKAGE TYPE E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . _ . . . . . . -40 to +BS'C
DC SUPPLY·VOLTAGE RANGE. (VDDI
(Voltages referenced to VSS Terminal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +15 V
POWER DISSIPATION PER PACKAGE (PDI
FOR TA
= -40 to +60'C (PACKAGE TYPE
E). . . . . . . . . . . . . . . . . . . . . . . . . . .
SOO mW
FOR TA = +60 to +BS'C (PACKAGE TYPE E) . . . . . . . . . . . Derate Linearly at 12 mWI'C to 200 mW
FOR T A = -S5 to +1 OO"C (PACKAGE TYPES D)
........................
FOR TA - +100 to +12SoC (PACKAGE TYPES D)
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
SOO mW
. . . . . . Derate Linearly at 12 mWI'C to 200 mW
FOR TA = FULL PACKAGE·TEMPERATURE RANGE (ALL PACKAGE TYPES). . . . . .
100 mW
INPUT VOLTAGE RANGE. ALL INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . -O.S to V DD +O.S V
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 t 1/32 inch (I.S9 ± 0.79 mm) from case for lOs max. .. . . . . . . . . . ..
+26S'C
RECOMMENDED OPERATING CONDITIONS at TA = 25°C, Except as Noted.
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges:
LIMITS
CHARACTERISTIC
V DD
(V)
D,F,H
PACKAGES
MIN.
Supply·Voltage Range (For T A = Full
Package·Temperature Range)
3
MAX.
E
PACKAGE
MIN.
12
3
MAX.
5
10
500
200
-
500
200
Clock Pulse Width, tw
5
10
400
175
-
400
175
-
Clock Input Frequency, fCl
5
10
de
de
de
de
1.5
3
Clock Rise and Fall Time, trCl, tfCl'
5,10
-
15
-
V
12
Data Setup Time. ts
1.5
3
UNITS
-
ns
-
-
ns
MHz
15
/.Is
..
·U more than one unit is cascaded trCL should be made less than or equal to the sum of the transition time
and the fixed propagation delay of the output of the driving stage for the estimated capacitive Ic;aad.
513
CD4034A Types
Features:
Table I - Truth Table for Register Input-Levels and the Resulting Register Operation (L= Low
Level H =High Level X =Don't Carel
"A"
Enable PIS AlB A/S
L
L
L
X
L
L
H
X
L
H
L
L
l.
H
L
H
L
H
H
L
L
H
H
H
H
H
L
L
L
H
X
X
H
H
L
L
H
H
L
H
H
H
H
L
H
H
H
H
Operation"
Serial Mode; Synch_ Serial Data Input, "A" Parallel Data Outputs
Disabled
Serial Mode; Synch_ Serial Data Input, "B" Parallel Data Output
Parallel Mode; "B" Synch. Parallel Data Inputs, "A" Parallel Data
Outputs Disabled
Parallel Mode; "B" Asynch. Parallel Data Inputs, "A" Parallel Data
Outputs Disabled
Parallel Mode; "A" Parallel Data Inputs Disabled, "B" Parallel Data
Outputs, Synch. Data Recirculation
parallel Mode; "A" Parallel Data Inputs Disabled, "B" Parallel Data
Outputs, Asynch. Data Recirculation
Serial Mode; Synch. Serial Data Input, "A" Parallel Data Output
Serial Mode; Synch; Serial Data Input, "B" Parallel Data Output
Parallel Mode; "B" Syncn. Parallel Data Input, "A" Parallel Dilta
Output
Parallel Mode; "B" Asynch. Parallel Data Input, "A" Parallel Data
Output
Parallel Mode; "A" Synch. Parallel Data Input, "B" Parallel Data
Output
Parallel Mode; "A" Asynch. Parallel Data Input, "B" Parallel Data
Output
·Outputs change at positive transition of clock
In
the senal mode and when the A/S control input is "'ow"
in the par2lllel mode.
A.
"
• Bidirectional parallel data input
• Parallel or serial inputs/parallel outputs
• Asynchronous or synchronous
parallel data loading
• Parallel data-input enable on
"A" data lines
• Data recirculation for register expansion
• Multipackage register expansion
• Fully static operation DC-to-5 MHz (typ.1
At VDD-VSS = 10V
• Quiescent current specified to 15 V
• Maximum input leakage current of 1 p.A
at 15 V (full package-temperature
range)
• 1-V noise margi" (full package-temperature range I
Applications:
• Para.llel Input/Parallel Output,
Parallel InputlSerial Output,
Serial Input/Parallel Output,
Serial Input/Serial Output Register
• Shift right/shift left register
• Shift right/shift left with parallel loading
• Address register
• Buffer register
• Bus system register with enable parallel
lines at bus side
• Double bus register system
• Up-Down Johnson or ring counter
• Pseudo-random code generators
• Sample and hold register (storage, counting, display)
.
• Frequency and ph_ comparator
o.OO<~
6 STAGES
SAME AS STAG( L
E~~
",n..n======::::==~
w.j-=
L~,nL
______
~roL
____________
~r--
'~:L
~
"~
,f,2n
rL.IL
.,~
... n
... n
rLIL
~
1M
TG
TRUTH TABLE
o
OUT
INPUT TOOUTI'UT IS
AIIDlIIECTIOIIAL LOW IIiIPEDANa
IIHfHCOHTIIOLLNf'UT I IS "LOW"
tiN Cis 0
J
'\.
00)
AlClCOMTItOLIMPUT21S"HIG/I".
~J All OPEN CIRCWT WHEM COMTftOt.
.
FLIP-FLOP
•• TG.Tft»l!llI"IOMGATE~
l
"-
"PUT11S"IIGH","DCOHTlOlIMPUTA"""'~_
'0.
"\.
f
Q
,,~
00
00
,,~
o_
f
f
X Q
'\.
'\.
I
I
f
'\.
I
I
.
~
Logic diagram.
r-l..S1J
.~
L-
VSS
Fig. 2 -
514
.. INVALID CONDITlON
,,~
92CM·192ODR2
COS,Mas PROTECllON
NETWORK
... ,
.,~
XOON'r CA"E
1&1
Cis
*AU.INPUrS ARE
fIROTJCTED BY
rLIL
,,~
MnL_____________________rLIL
Fig. 3 -
B DAn. LINES ME OUTf'UTS
Timing diagram.
~'-J~i~:;-
CD4034A Types
STATIC ELECTRICAL CHARACTERISTICS
LIMITS AT INDICATED TEMPERATURES I'C)
CONDITIONS
CHARACTERISTICS
Quiescent Device
Current, IL Max.
Output Voltage:
Low Level,
VOL
High Level
VOH
Noise Immunity:
Inputs Low.
VNL
Inputs High
VNH
Noise Margin:
Inputs Low,
Vo V IN VDD
IV) IV) IV)
D, H PACKAGES
-55
.25
TYP, LIMIT
E PACKAGE
.,25
.25
-40
TYP. LIMIT
UNITS
.85
-
-
5
5
0.3
5
300
50
50
700
-
-
10
10
0.5
10
600
100
1.
100
1400
15
50
1
50
2000
500
5
500
5000
-
5
5
-
10
10
0.5
IJA
o Typ.; 0.05 Max
o Typ.; 0.05 Max
LOAD (APACITAI\IC[ICll-pf
V
-
0
5
4.95 Min.; 5 Typ.
-
0
10
9.95 Min.; 10 Typ.
9
-
10
0.8
-
5
1
-
10
3 Min.; 4.5 Typ.
4.2
Fig. 4 -
Typical propagation delay time
no. load capacitance.
1.5 Min.; 2.25 Typ.
5
3 Min.; 4.5 Typ.
V
1.5 Min.; 2.25 Typ.
4.5
-
5
1 Min.
VNML
9
-
10
1 Min.
Inputs High,
VNMH
0.5
5
1 Min.
1
-
10
1 Min.
Current:
N-Channel
ISink).
0.5
-
5
ION Min.
0.5
-
10
P·Channel
ISource):
4.5
lOP Min.
9.5
-
V
Output Drive
LOAD CAPACITANCE I(L1- pF
0.124 0.2
0.1
0.07
0.31
0.5
0.25
0.175 0.31
5 -0.075 -0.1
-0.05
0.124 0.2
0.1
0.07
0.5
0.25
0.175
0.035 ·0.075 -0.1
·0.05
0.035
Fig. 5 - Typical transition rime vs. load
capacitance.
rnA
Input Leakage
Current,
IIL,IIH
10 -0.188 -0.25 -0.125 0.088 0.188 -0.25 ·0.125 0.088
Any Input
± 10- 5 Typ., ± 1 Max.
-]-]15
IJA
SUPPLY VOLTS ""ODI
Fig. 6 - Typical clock input frequency vs.
supply Voltage.
Fig. 8 - Asynchronous operation propagation delay
time and transition time.
10
102
lOJ
10-
INPUT CLOCK fREQUENCY UCL1- _ttl 12<:5-1710.113
Fig. 7 - Typical dissipation
characteri$~;cs.
·,NPUT II[FER$ TO AHYOF THE "A"CJ'!"8"QATA ,IrIPuTS.'A'EJoiABl[.
.
SEIIIAI. ,,,,,PUT. Ala. PIS. 011 AI! INPUTS
··'SlHMOISHlAREsn·uPT,IrjIES
Fig. 9 - Clock pulse rise and fall timBS,
Fig. 10 - Synchronous operation propagation
dBlay timss, transition timBs, and set-up
times.
515
CD4034A Types
DYNAMIC ELECTRICAL CHARACTERISTICS
At TA = 2!f'C. Input tr• tf = 20ns. CL = 15 pF. RL = 2()(U,n
CHARACTERISTIC
5
10
5
10
5
10
5
10
Propagation Delav
Time; tpLH. tPHL
Transition Time;
tTHl,tTlH
Maximum Clock Input
Frequency, fCl
Clock Pulse Width.
tw
Min. High·level
AE. PIS. AIS
Pulse Width
5
10
Clock Rise& Fall Time
trCl, tfCl·
5
10
5
10
Data Set·Up Time.
, ts
AnV Input
*If more than one unit is cascaded
E
PACKAGE
D.H
PACKAGES
-VDD
(VI
Average Input
CapaCitance, CI
LIMITS
TEST
CONDITIONS
INPUTO'
VIX) OUTPUTS
UNIT
~
DD
V ':::'-
+
YN...
MIN.
1.5
3
-
-
TYP. MAX. MIN.
600
240
250
100
2.5
1200
480
750
300
5
200
100
-
240
85
-
-
250
100
-
5
-
400
175
480
195
15
15
500
200
-
-
-
1.5
3
-
TYP. MAX.
_
NOTE:
600
240
250
100
2.5
5
200
100
1200
480
750
300
400
175
240
480
85
195
-
15
15
500
200
-
-
-
250
100
-
5
-
TEST ANY ONE INPUT,
. Vss
ns
ns
WITH 01'HDt INPUTS AT
;2C5-21400 Vao ORVss'
Fig. 1 1 - Noise-immunity telt circuit.
MHz
ns
ns·
.
VDO
"ss
p.s
ns
pF
t,el should be made less than or equal to the sum of the transition time
"ss
Fig. '2 - Ou;escent-dev;ce-current test circuit.
and the fixed propagation delav of the output of the driving St8ge for the estimated capacitive load,
APPLICATIONS
V~NP(JUS :~:~U., INPUTS
"DO
o ~
S(QU[NTtALLY.
TO 10TH VOD AND V,S
Vss
CONNECT AU UNUSED
IfrPUTS TOEITH!"
Voo (l1li Vss
vss
CL>".~:::j======:::t:====::::
Fig. 14 - IS-Bltparllllel In/parslllliout. panllel
inlserlal out~ .risl in/paralle' out~ IIIr;II'
In/NrI.1 out "'I/I,ter.
Fig. 15 -' IS-Bit nrlelln/gated parallel out "'I/I,ter.
Fig. 13 - Inpuf.!eakage..current test c;,cu;t~
516 _______________________________________________________________
CD4035A Types
COS/MOS 4-Stage
Parallel In/Parallel Out
Shift Register
with J-K Serial Inputs and True/
Complement Outputs
Features:
• 4-Stage clocked shift operation
• Synchronous parallel entry on all 4 stages
• JR inputs on first stage
• Asynchronous True/Complement control
on all outputs
• Static flip-flop operation; Master-slave
configuration
• Reset control
• Buffered outputs
• Low power dissipation - 5p.W typ_ (ceramic)
• High speed - to 5 MHz
• Quiescent current specified to 15 V
• Maximum input leakage current of 1p.A
at 15 V (full package-temperature range)
• 1-V noise margin (full package-tamperBture range)
The RCA-CD4035A is a four-stage clocked
signal ·serial register with provision for
SYNCHRONOUS PARALLEL inputs to
each stage and SERIAL inputs to the first
stage via JK logic. Register stages 2, 3, and
4 are coupled in a serial 0 flip·flop config·
uration when the register is in the se'rial
mode (PARALLEL/SERIAL control low).
PARALlEL IN
f.L
Sf:'
Applications
When the TRUE/COMPLEMENT control is
high, the TRUE contents of the register are
available at the output terminals. When the
TRUE/COMPLEMENT control is low, the
outputs are the complements of the data in
the register. The TRUE/COMPLEMENT
control functions asynchronously with repect to the CLOCK signal.
JK input logic is provided on the first stage
SERIAL input to minimize logic requirements particularly in counting and sequencegeneration applications. With JK inputs
connected together, the first stage becomes
a 0 flip·flop. An asynchronous common
RESET is also provided.
These types are supplied in 16-lead hermelic
dual-in-line ceramic packages (O and F
suffixes), 16-lead dual-in-line plastic package (Esuffix), 16-lead ceramic flat packageq
(K suffix), and in chip form (H suffix) ..
1012
III'
1214\
RL
CLKL
. p/sL
CD4035A
4-STAGE REGISTER
TieL
• Counters, Registers
Arithmetic·unit registers
Shift left - shift right registers
Serial-to-parallel/parallel-to-serial conversions
• Sequence generation
• Control circuits
• Code conversion
L
voo·16
,.
RESET
Vss *8
I'
, O,/CI
I" I"
0,i0z 0]/03 Q4/04
TIC' OuT
'
'i2CS·""6R'
CD4035A
FUNCTIONAL DIAGRAM
MAXIMUM RATINGS, Absolute·Maximum Values:
STORAGE·TEMPERATURE RANGE (Tstgl • • . . . . • . • . . • . . . . • . • . • . . . . . . • -66 to +150oC
OPERATING·TEMPERATURE RANGE (TAl:
PACKAGE TYPES D, F, H
. . • . • . . . • . • . . • • . . • • . • • . • . • • • • . • . . . -55 to +125°C
. . . • . . . . . . . . • • . • • . • • . . • . . • • . • • . • . • • • . • • -40 to +85°C
PACKAGE TYPE E
DCSUPPLY·VOLTAGE RANGE,(VDDI
(Voltages referenced
to
VSS Terminal!: •..••.••••.••.•••••••••.....•• -0.5 to +15V
POWER DISSIPATION PER PACKAGE (PDI:
FOR T A ~ -40 to +60o C (PACKAGE TYPE E I
• • • • . • . • • . . . • • . • . • • . . • • . • • 500 mW
FOR T A = +60 to +8SoC (PACKAGE TYPE EI
•••.•.•• Derata Linearly at 12mWfC to 200 mW
FOR T A ~ -55 to +100oC (PACKAGE TYPES D, F l . . . . • . . • • • • • • • . • • . . • . .• 500 mW
FOR T A = +100 to +125°C (PACKAGE TYPES D, F l . • ..
Derate Linearly at 12mwfC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR T A = FULL PACKAGE·TEMPERATURE RANGE (ALL PACKAGE TYPESI. . • • • • .. 100mW
INPUT VOLTAGE RANGE, ALL INPUTS . • . . . • . • • . . • . • • . • • • . • • • • . • -0.5 to V DD +O.5V
LEAD TEMPERATURE (DURING SOLDERINGI:
At distance 1116 ± 1132 inch (1.59 ± 0.79 mml from case for 10 s max • . • • . • • . . • . • • . . +2650 C
RECOMMENOED OPERATING CONDITIONS at TA=250 C, except as noted.
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges:
Parallel entry via the 0 line of each reg·
ister stage is permitted only when the
PARALLEL/SERIAL control is high.
In the parallel or serial mode information
is transferred on positive clock transitions.
~I'
LIMITS
CHARACTER ISTIC
VOD
(V)
D,F,H
PACKAGES
MIN.
Supply Voltage Range (For T A: Full
Package·Temperature Range
3
MAX.
12
E
PACKAGE
MIN.
UNITS
MAX.
12
V
ns
500
100
-
500
250
-
ns
-
15
5
p.s
500
200
-
3
Data Setup Time, tS:
J/K Lines
5
10
500
200
Parallel·ln Lines
5
10
350
80
-
5
10
335
165
-
Clock Rise and Fan-Time, trCL,tfCL
5
10
-
Reset Pulse Duration, tw
5
10
400
175
Clock Pulse Width,
tw
15
5
-
750
250
-
ns
__________________________________________________________________·517
CD4035A Types
.
PARALLEL
PARALLEL
SERIAL
INPUT-I
CONTROLIP/S)
.'o--------1~---+~~--~+_--~~--~~--~r._~_r--~~__,
1
1
'00
a 300
~
:; zoo
~
f:
,.
..
100
rRUE/CQMPL.
'&2
Z03040~0601080
ITICI
LOAD CAPACITANCE (Cll-pF
PIS.C-SER'AL MODE
T/Co"
TRUE OUTPUTS
Fig. 2 - Typical propagation delay time vs.
load capacitance.
FIRST STAG[ TRUTH TABLE
'n_II I,.PU151
CL
J
J
F
'n(OUTPUTS)
a,
"On-'
J
0'
AMIIiENT nMPERATURE (Toll- 2~·C
TYPICAl. nMPERATURE COEFFICIENT FOR ALL VALUES
'
0
f 300
On-I
C~:C:ED: .g;:~~,~
}
V55
On-I
INPUT 100U1PU1 IS:
,I'" 810IR[CTlOIUoL. LOW IIilPEOANC[
WHEN CONTROL INPUT I IS LOW
Al.L. INPUTS PROTECTED BY
COS/MOS PROTECTION NETWORK
1
AND CONTROL INPUT 2 IS HIGH
b' AN OPEN CIRCUIT WH(N CONTI'IOL
INPUT I IS HIGH AND CONTROL.
INPUT Z 15 LOW
o
Fig. 1 - Logic block diagram.
•
STATIC ELECTRICAL CHARACTERISTICS
LIMITS AT INDICATED TEMPERATURES (DC)
CONDITIONS
CHARACTERISTICS
Vo V IN V Do
(V) (V) (V)
E
D, F, H PACKAGES
-55
+25
TYP.
LIMIT
+125
-40
~
+25
TYP. LIMIT
5
5
0.3
5
300
50
50
700
10
10
0.5
10
600
100
1
100
1400
- -
15
50
1
50
2000
500
5
500
5000
-
5
5
VOL
10
10
oTyp.; 0.05 Max
oTyp.; 0.05 Max
High Level
V OH
-
0
5
4.95 Min.; 5 Typ.
0
10
9.95 Min.; 10 Typ.
9
-
10
O.B
-
5
1
-
10
3 Min.; 4.5 Typ.
5
1 Min.
10
1 Min.
Current, IL Max.
Output Voltage:
Low Level,
Noise Immunity;
Inputs Low,
V NL
Inputs High
V NH
Noise Margin:
Inputs Low,
4.2
4.5
V NML
9
Inputs High,
V NMH ·
0.5
1
-
0.5
ro
~
~
fJA
3 Min.; 4.5 Typ.
V
1.5 Min.; 2.25 Typ.
-
5
1 Min.
10
1 Min.
Fi~
4 - Typical clock input frequency
VI.
supplV voltage.
V
0.5
-
5
0.62
1
0.5
0.35
0.43
1
0.35
0.24
0.5
10
1.55
2.5
1.25
0.B7
1.05
2.5
0.85
0.59
P-Channel
(Sourcel:
4.5
-
5
-0.31
-0.5
lOP Min.
9.5
-
10
IIL,IIH
•
1.5 Min.; 2.25 Typ.
5
ION Min.
Current,
~
V
Output Drive
Current:
N-Channel
(Sink),
Input Leakage
~
Fig. 3 - Typical transition time VI, load
capacitance.
+85
-
-
~
UNITS
-
Quiescent Device
•
LOAD CAPACITANCE (CLI-,F
PACKAGE
mA
I.1l&D tAMCl .... NCr: (CLI.,S,F
:T~nF5
-0.81 -1.3
-0.25 -0.17 -0.2
-0.5
-0.65 -0.45 -0.56 -0.31
±10-5 Typ., ±1 Max.
--CL"50,F
-0.18 -0.12
-0.45 -0.31
f.lA
Fig. 5 - Typical dynamic power dissipation
charac teristics.
518 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD4035A Types
DYNAMIC ELECTRICAL CHARACTERISTICS
= 250 C,
At TA
Input tr,tt
= 20 ns, CL = 15 pF, RL = 200 kn
LIMITS
CHARACTER ISTICS
E
PACKAGE
D, F,H
PACKAGES
TEST
CONDITIONS
UNITS
V DD
(V)
Min.
Typ.
Max.
Max.
Min.
Typ.
-
250
700
100
300
-
100
300
50
150
CLOCKED OPERATION
Propagation Delay
Time:
5
-
250
500
10
-
100
200
Transition Time:
5
200
10
-
100
t THL , tTLH
50
100
tpLH' tpHI-
Minimum Clock
Pulse Width, \v
5
Maximum Clock
Rise & Fall Time
t rCL' ttCL*
Minimum Setup Time:
-
J/K Lines
Maximum Clock
Frequency, tCL
Input Capacitance, C,
500
100
250
15
-
15
5
-
-
5
500
-
250
750
200
100
250
350
-
100
500
80
-
50
100
1
2.5
2
5
-
335
100
165
5
-
10
-
-
5
250
100
5
-
100
10
-
50
5
1.5
2.5
10
3
5
-
10
Parallel·ln Lines
200
-
200
-
10
-
-
5
250
500
700
200
-
250
100
100
300
-
200
400
-
200
500
-
100
175
-
100
200
-
5
10
-
5
10
Any Input
ns
ns
ns
jlS
ns
MHz
pF
RESET OPERATION
Propagation pelay
Time:
tpHL' tpLH
Minimum Reset Pulse
Width, \v
5
ns
ns
*If more than one unit is cascaded trCL should be made less than or equal to the sum of the transition time
and the fixed propagation delay of the output of the driving stage for the estimated capacitive load.
VOD-VNH
INPUTS
'HPUTOVCO
OUTPUT'
''VNOL
'HPUO'
vDO
Vco
:--0-
~
1
V55
NOT['
MUSUAI: INPUTS
SEQUENTIALLY,
VSS
TO BOTH VDO AND 'Iss'
CONNECT ALL UNUSED
NOTE:
vSS
TEST ANY CONIINATION
1NPUI'S TOEITH£R
Of'INPUTS
VDO OR VSS'
V55
Fig. 6 - Noise-immunity test circuit.
Fig. 7 - Ouiescent·device-current
test circuit.
Fig. 8 -Input-leakage-current
test circuit.
_________________________________________________________________ 519
CD4037 A Types
COS/MOS Triple AND/OR Bi-Phase Pairs
The RCA-CD4037 A consists of three ANDI
OR pairs driven by common control signals
A and B_
HRl DATA
CONTROL
Each circuit has a data input (C), and two output terminals (D and E) that provide outputs
in accordance with the truth table shown in
Fig_ 1. The circuit is useful for coding or decoding signals .for split-phase (Bi-phase) communication systems, magnetic recording, and
plated wire and core memory systems. A separate VCC terminal is provided to allow level
conversion to any voltage from 3 volts to V DD.
SIGNALS
D~~PHASE
MODULATED
sr----
OUTPUTS
--------~D2
rr --- _____
c~
ANa/OR PAIR
L----
COOl NG WAVEfORMS
PHASE
I"
.FE2
6("---- .L.--------,.!03
19
3-iL _ _ _ _AND
_ lOR
_ _PAIR
_ _ _ _ ..J"'""E3
MODULATED
DATA
CONTROL
SIGNALS
D~~PL~:~NTARY
These types are supplied in 14-lead hermetic
dual-ln-Iine ceramic packages (D and F
sufflxes),14-lead dual-in-Iine plastic package (E suffix), 14-lead ceramic flat package
(K suffix), and in chip form (H suffix).
E
OUTPUTS
DECODING WAVEFORMS
CD 4037A
FUNCTIONAL DIAGRAM
TRUTH TABLE
I NPUT OUTPUT
ABO
o
Fig. 1 - Coding and decoding waveforms.
E
0
C
RECOMMENDED OPERATING CONDITIONS_ For maximum reliability, nominal operating
conditions should be selected to that operation is always within the following ranges:
C
C
C
o
0
ALL INPlJTS ARE PAQTECTED BY
COS/MOS PROTECTION NETWORK
Features:
LIMITS
CHARACTERISTIC
0, F,H
VDD
(V)
E
PACKAGES
UNITS
PACKAGE
MIN_
MAX.
MIN.
MAX.
3
12
3
12
Supply-Voltage Range (For T A = Full
Package-Temperature Range)
• Outputs compatible with low-power TTL
systems.
• High sink and source current (1.6 rnA typ.)
capability at V DO =V CC =10V and
VDS =0.5 V.
• Microwatt quiescent power dissipation:
Po = 0.5 /JW/ceramic pkg- (typ.), Po =
2/JW/plasticpkg.(typ.) atVDD= 10V
V
CAUTION: VCC VOLTAGE LEVEL MUST BE EQUAL TO OR LESS POSITIVE THAN VDD
DYNAMIC ELECTRICAL CHARACTERISTICS
at TA = 25'C, Input tp tf= 20 ns, CL = 15 pF, RL = 200 kO
CHARACTERISTIC
LIMITS
TEST
CONDITIONS
0, F,H
r-VDD
(V)
Propagation Delay Time:
A and B Inputs
tpHL' tpLH
MIN_
TYP. . MAX. MIN.
5
-
225
450
10
-
75
150
5
250
500
75
150
225
450
tpHL
10
tpLH
5
-
10
-
90
180
80
C Inputs
Transition Time:
I
High-to-Low Level,
Applications:
E
PACKAGE
PACKAGES
5
-
40
10
-
15
30
5
10
-
75
-
60
150
120
-
5
• Quiescent current specified to 15 V
• Maximum input leakage current of 1 JJA at
15 V (full package-temperature range)
• l-V noise margin (full package-temperature
range)
UNITS
TYP . MAX_
-
325
650
100
200
-
350
700
-
ns
100
200
325
650
125
250
60
120
20
40
ns
100
90
200
180
ns
-
pF
•
Split-phase (Bi-Phase) communication systems.
• Disc, drum, and tape digital recording
systems.
• Plated wire and core memory systems.
• High-ta-Iow logic leVel converter_
ns
tTHL
Low-to-High Level,
tTLH
I nput Capacitance, CI
Any Input
-
5
'2CS~20079
Fig. 2 - Waveforms for measurement or-dynamic
characteristics.
520 __________________________________________________-------------
CD4037A Types
MAXIMUM RATINGS, Absolute-Maximum Values:
STORAGE-TEMPERATURE RANGE (T st9)
.•.••.•••••••••••.•••••.•
-65 to +150' C
too h...."=c=m.~m"r~,,,,,,..,,,,,,,,,,,,i
-55 to +125' C
-40 to +85' C
:. ISO
•
-0.5 to +15 V
g
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPES D. F, H
PACKAGE TYPE
~
•••••••••••••.•••••••••.••..•••
E
~
DC SUPPLY-VOLTAGE RANGE, (VDD)
~
(Voltages referenced to VSS Terminal) . • . • • • . • • • • • • • • • • • . • • • • • . . .
100
POWER DISSIPATION PER PACKAGE (PO):
FOR TA
FOR TA
FOR TA
FOR TA
= -40 to +60' C (PACKAGE TYPE El
• •
= +60 to +85' C (PACKAGE TYPE E)
••
= -55 to +100' C (PACKAGE TYPES 0, F)
= +100 to +125' C (PACKAGE TYPES D. F)
500 mW
•. • • • • . • • • • • • . .
Derate Linearly at 12 mW/" C to 200 mW
1..0AD CAPACITANCEICl.l-pF
500 mW
Derate Linearly at 12 mW/" C to 200 mW
•••••..••••••••
Fig. 3 - Tvpical transition time VI.
load capacitance,
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA
= FULL
100 mW
••••.••••••••••••.••••• -0.5 to VDO +0.5 V
PACKAGE-TEMPERATURE RANGE (ALL PACKAGE TYPES)
INPUT VOLTAGE RANGE, ALL INPUTS
LEAD TEMPERATURE (DURING SOLDERING):
+265' C
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max
STATIC ELECTRICAL CHARACTERISTICS
LIMITS AT INDICATED TEMPERATURES (OC)
CONDITIONS
CHARACTERISTICS
Quiescent Device
Current, I L" Max.
Output Voltage:
Low level,
VOL
High Level
V OH
Noise Immunity:
Inputs Low,
V NL
Vo V IN V DD
(VI (V) (VI
-
-
-
10 10
5
-55
+25
TYP.
LIMIT
PACKAGE
E
D,F, H PACKAGES
+125
-40
UNITS
+25
TYP. LIMIT
+85
5
5
0.03
5
300
50
0.1
50
700
10
10
0.05
10
600
100
0.2
100
1400
15
50
1
50
2000
500
5
500
5000
p.A
LOAD CAPACITANCE ICLI-pF
Fig. 4 - Typical transition time vs.
load capacitance.
o Typ.; 0.05 Ma.
oTyp.; 0.05 Ma.
5
V
-
0
-
0 10
4.95 Min.; 5 Typ.
5
9.95 Min.; 10 Typ.
4.2
-
5
9
-
10
0.8
5
1
-
10
3 Min.; 4.5 Typ.
4.5
-
5
1 Min.
0.5 1
-
10
1 Min.
5
I Min.
10
1 Min.
1.5 Min.; 2.25 Typ.
3 Min.; 4.5 Typ.
V
Inputs High
V NH
Noise Margin:
Inputs Low,
V NML
Inputs High.
V NMH
9
1.5 Min.; 2.25 Typ.
V
'00
LOAD CAPACITANCEICLI-pF
Fig. 5 - Typical propagation delay time vs.
load capacitance.
Output Drive
Current:
N~Channel
(Sink).
0.5
-
5
0.85
0.7
1.2
0.45
0.4
0.35
0.7
0.3
ION Min.
0.5
-
10
1.3
1.1
2
0.7
0.65
0.55
1.1
0.45
4.5
-
5
P·Channel
(Source):
lOP Min.
Input Leakage
Current,
IIL·IIH
9.5
-
~
10
-T ~T:5
-0.65 -0.55 -1
-0.9
-0.75 -1.6
-0.35 -0.35 -0.3
-0.45 -0.5
-0.4
rnA
,I
~
"
-0.55 -0.2
X
-0.75 -0.3
~
.0'
?
±1Q-5 Typ., ±1 M...
p.A
....1,0"-,-_....J,0"":'---',l,0''---,-J",.
IO-2L.._ _
For quiescent device current, noise immunity, and input leakage current test circuits see
"Ratings and Characteristics" at the beginning of the COSIMOS section.
INPUT FREQUENCY (f)-Hz
.PACKAGE CONTAINS 6 ANO-OR CIRCUITS
Fig. 6 - Typical dissipation characteristics.
521
CD4040A Types
COS/MaS 12-Stage
Ripple-Carry
Binary Counter/Divider
The RCA·CD4040A consists of an input·
pulse·shaping circuit and 12 ripple·carry
binary counter stages. Resetting the counter
to the all·O's state is accomplished by a
high·level on the reset line. A master·
slave flip-flop configuration is utilized for
each counter stage. The state of the counter
is advanced one step in binary order on the
negative-going transition of the input pulse.
All inputs and outputs are fully buffered.
These types are supplied in 16-lead hermetic
dual-in-I:ne ceramic packages .(0 and F
suffixes), 16-lead dual-in-line plastic package (E suffix). 16-lead ceramic flat package
(K suffix), and in chip form (H suffix).
A'as.
Features:
-
Medium-speed operation
. 5 MHz (typ.1 input pulse
rate at VOD - VSS = 10 V
Low output impedance .. 750 S1 (typ.) at VDD - VSS
=10 V and VDS =0.5 V
Common reset
- Fully static operation
All 12 buffered outputs available
Low-power TTL compatible
Quiescent current specified to 15 V.
Meximum input leakage current of 1 jJ.A
at 15 V (full package·temperature range)
1-V noise margin (full package-temper·
ature rangel
O.
,.
,.,.
0'0
13
08
,S
•
3
err
Q4
a
VDD
all
'2
ao
II
'0
R
A.
• a'•
"ss
9i2CS-20747RI
CD4040A
TERMINAL DIAGRAM
Applications:
-
Frequency-dividing circuits
Time-delay circuits - Control counters
RECOMMENDED OPERATING CONDITONS at TA = 2SOC, Except as Noted:
For maximum reliability, nominal operating conditions should ba selected so that operation is
always within the following ranges :
CHARACTERISTIC
VDD
(V)
Input·Pulse Frequency, f.p
Input-Pulse Rise or Fall Time, tr.p,tf.p
Reset Pulse Width, tw
,
UNITS
DRAIN - TO - SOURCE VOlTAGE (VOSI-V
t2C5-2IS,O
Fig.2 - Tvpical output n-channel
Supply Voltage Range (For T A = Full
PaCkage-Temperature Range)
Input Pulse Width, tw
LIMITS
E
D,F,H
Package
Packages
Min.
Max.
Min.
Max.
3
12
3
12
5
10
5
10
5
10
400
110
dc
dc
15
15
-
500
125
-
1.5
4
-
de
i5
15
5
10
1000
500
-
1250
600
-
1.5
4
~c
-
-
drain ctJaracteristics.
V
DAAIN:"TO-SOlJICE VOLTAGE (VDS1-V
ns
'v
MHz
-,
ps
ns
I
GATE-TO-SOi..RC£ VOlTAGE (
-10 ~
-1:1 V
I
~
AMBIENT TE .... EItATURE (TA'-Z:I·C
TYPICAL TEMP. COEFFICIENT AT ALL VALUES OF VGS·-a3%I·C
Fig.3 -
Typical output p-channel
drain characteristics.
4~
*PROTECTED
AU. '"PII1'5 ARE
BY
'}'NTOPUTS
2'"
STAGE
0,
NETWORK
12
"ss ••
• R-HIGH DOMINATES (RESETS ALL STAGES)
CDS/NOS PROTECTION 6ACTION OCCURS ON NEGATIVE GOING
BUFFERE~
VDD-16
TRANSITION OF INPUT PULSE. COUNTER
ADVANCES ONE BINARY COUNT ON EACH
NEGATIVE. TRANSITION (4096 TOTAL
BINARY COUNTS).
92CM-20748R3
Fig. 1 - Logic diagram of C04040A input pulse shapsr and 1 of 12 stages.
522
Fig.4 - . Functional diagram.
OUTPUTS
92CS-ZO!522
CD4040A Types
MAXIMUM RATINGS, Absolute·Maximum Values:
".ENT TEMPERATURE ITAI • U'C
STORAGE·TEMPERATURE RANGE (T stg )
.................................
OPERATING· TEMPERATURE RANGE (T A ):
-65 to +1500 C
..... ......................................
PACKAGE TYPES O. F. H
PACKAGE TYPE E
.. . . .. . . .. . . .. . .. .. .. .. . . .. .. ..
OCSUPPLY·VOLTAGE RANGE. (V OO )
-55 to +12S oC
-40 to +8So C
(Voltages referenced to VSS Terminal)......................................
-0.5 to +15 V
POWER DISSIPATION PER PACKAGE (PO):
FOR T A= -40 to +600 C (PACKAGE TYPE E)
FOR T A = +60 to +8S o C (PACKAGE TYPE E,)
,ov
Derate Linearly at 12 mW/oC to 200 mW
.................
SOOmW
..... Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE·TEMPERATURE RANGE (ALL PACKAGE TYPES) . . . . . . .
100 mW
INPUT VOLTAGE RANGE. ALL INPUTS. . . . . .
.................
-0.5'0 VOO +0.5 V
LEAD TEMPERATURE lOURING SOLDERING):
At distance 1/16 ± 1/32 inch 0,59 ± 0.79 mmJ from case for 105 max ......•..•....
Vo VIN VOO
(VI (VI (VI
Limits at Indicated Temperatures (OCI
Current,
IL Max. -
O,F,H Packages
--55
+25
E
+125
5
10
15
5
10
0
0
5
10
5
10
oTyp.; 0.05 Max.
oTyp.; 0.05 Max.
-
5
10
5
10
1.5 Min.; 2.25 Typ.
3 Min.; 4.5 Typ.
1.5 Min.; 2.25 Typ.
3 Min.; 4.5 Typ.
4.5
9
-
5
10
1 Min.
1 Min.
0.5
VNMH 1
-
5
10
1 Min.
1 Min.
-
5
10
-
5
10
Output Voltage:
Low-Level.
High·Level
VOH VOL
15
25
50
0.5
1
2.5
:s
.v
7.5
15
25
50
900
1500
2000
50
100
500
10
12.5
15
DRAIN - TO - SOURCE VOlTAGE IVDSI-i~C5'21~12
Fig.5 - Minimum output n-channel
drain characteristics.
DRAIN-1D-SDLIICE VOLTAGE h'DS}-V
'-lliV
.....BlENT TEMP[RATURE IT... ' ·25-C
tYPICAL TE"P. COEFFICIENT AT ALL VALUES OF \lciS.-o.3'1101-r.
Units
Package
+85
+25
-40
Typ. Limit
-
Quiescent Device
2!!
GATE-TO-SOUfIC£ YOLTAGt I
STATIC ELECTRICAL CHARACTERISTICS
Conditions
~ 3.75
500mW
FOR T A= -55 to +'OOoC (PACKAGE TYPES O. F)
FOR T A= +100 to +12S o C (PACKAGE TYPES O. F)
Characteristic
TYPlCA1. TEMP. COffFICIENT AT AL.L VALUES Of VGS' -03'1'-1'C
7.'
Typ.
Limit
1
2
5
50
100
500
700
1400
5000
Fig.6 - Minimpm output p--channel
drain characteristics.
IJ.A
V
4.95 Min.; 5 Typ.
9.95 Min:; 10 Typ.
Noise Immunity:
Inputs Low.
4.2
9
Inputs High.
0.8
VNH 1
VNL
Noise Margin:
Inputs Low,
VNML
-
V
LOAD CAPACITANCE lCL1-pF
Fig.l- Typical propagation delay time
load capacitance (per stage).
VI.
V
Inputs High.
Output Drive
Current:
N·Channel
0.5
(Sink),
ION Min. 0.5
P-Channel
(Sourcel:
4.5
lOP Min. 9.5
0.22
0.44
0.36
0.75
0.145 0.102
0.4
0.250
0.21
0.42
0.36
0.75
0.08
0.2
0.056
0.14
rnA
-0.15 -0.25 -0.1 -0.07 -0.15 -0.25 -0.06 -0.04
-0.03 -0.5 -0.25 -0.175 -0.29 -0.5 -0.15 -0.1
Input Leakage
Any Input
Current,
IIL.IIH
-
-
15
±10- 5 Typ., ±1 Max.
jJ.A
Fig.S - Typical transition time vs. load
capacitance.
523
CD4040A Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25 0 C, Input t r, tt = 20 ns,
CL = 15 pF, RL = 200 kG
10
AMI!1ENT TEMPERATURE ITAI-:!!!-C
rtt~
LIMITS
Test Conditions
Characteristic
~
(V)
Input·Pulse Operation
Propagation Delay
Time.
tPLH, tPHL·
D,F,H
Packages
E
Package
Min. Typ. Max.
Min. Typ. Max.
LOAD CAPACITANCE
--Cl'SOpF
5
10
-
450
225
900
450
-
450
225
950
475
ns
5
150
75
300
150
-
150
75
350
175
ns
1.5
4
2.5
-
MHz
200 500
75 125
Transition Time,
tTHL. tTLH
10
-
Maximum I nput·Pulse
Frequency, f",
5
10
1.5
4
2.5
-
6
-
-
200
75
400
110
-
15
7.5
-
-
Minimum Input·Pulse
Width, tw
Input·Pulse Rise &
Fall Time, t r",. tf"'.
Average Input
Capacitance, CI
Units
f=100 kHZ
5
10
5
-
10
-
-
-
5
Any Input
-
Reset Operation
Propagation Delay
Time, tPHL'
5
10
-
500 1000
250 500
Minimum Reset
Pulse Width. tw
5
10
-
500
250
• Measured from the 50% level of the negative
input pulse edge to the 50% level of either
the positive or negative edge of the 01 out·
put (pin 9); or measured from the negative edge of 01 through all outputs to
the positive or negative edge of the next
higher output.
1000
500
6
ns
-
/1S
-
5
-
pF
-
500
250
1250
600
ns
500
250
1250
600
ns
LOAD CAPACITANCE Ie )."
..
110
,.
l;I2CS-Z7$",,,,A'
Fig. 10 - Typical input-pu/ss frequency
vs. supply voltage.
o ~
I
SEQUENTIALLY,
TO BOT" VDO AND Vss
Co.(CT All UHUSm
INPU1'S 10 [ITH[A
"SS
Yooc.-vss ·
NOTE:
T£ST ANY ONE INPUT,
WITH OTHEA INPUTS AT
U(S-Z7.00
"DO ORYss
Fig. 11- Noise-immunity test circuit.
524
,.
SUPPLY VOLTSIVDDI
V~NPU(JS
v"" :~:~U.. INPUTS
~
V5S
-U·C
pF
IS
• Maximum input rise or fall time for functional operation.
• Measured from the positive edge of the reset pulse to the negative edge of any output
-(01 to 012).
IN.UTOV""OUT'UTS
":1,.
10"
~
INPUTS
'-
AMIIENT TEMPERATURE (TA
~
15
7.5
o
Vso
VDD~YNM
10!
INPUT FREQUENCY U.,I-kH,
Fig.9 - Typical dissipation characteristics.
-
-
102
(Cll'I~IIF
Vss
Fig. 12 - Quiescent*Cievice"'Current test circuit.
V55
Fig. 13 - Input-leakage-current test circuit.
CD4041A Types
COS/MOS Quad
True/Complement
Buffer
resistor-network driver for AID and D/A
conversion, as a transmission-line driver, and
in other applications where high noise immunity and low-power dissipation are primary design requirements.
A
E-A
ZF
F·;I;
•
The RCA-CD4041A types are quad truel
complement buffers consisting of n- and
p-channel units having low channel resistance
and hiQh current (sourcinR and sinking)capability_ The CD4041A is intended for use as
a buffer, line driver, or COS/MOS-to-TTL
driver. It can be used as an ultra-low power
'~I £
These types are supplied in 14-lead hermetic
dual-in-line ceramic packages (0 and F
suffixes), 14-lead dual-in-line plastic package (Esuffix), 14-lead ceramic flat package
(K suffix), and in chip form (H suffix).
G
'~4
G'.
H·ii
"H
MAXIMUM RATINGS, Absolute·Maximum Values:
STORAGE·TEMPERATURE RANGE (Tstgl
................................ .
OPERATING· TEMPERATURE RANGE ITAI:
.. , , , .. , . , , , , , , . , , , , , , , . , , . , , . , , , , ,
............................... .
-55 to +l25 oC
-40 to +8SoC
Vss Terminal) .•........................ '.' . . • . . • • • . .
-0.6 to +15 V
PACKAGE TYPES O. F, H
PACKAGE TYPE E
DC SUPPLY·VOL TAGE RANGE, (Vool.
(Voltages referenced to
POWER DISSIPATION PER PACKAGE (POl:
FOR T A = -40 to +600 C (PACKAGE TYPE E I
SOOmW
FOR T A = +60 to +8SoC (PACKAGE TYPE Ell
Derate Linearlv at 12 mW/oC to 200 mW
FOR T A = -55 to + 100°C (PACKAGE TYPES 0, F I
FOR T A= +100 to +125 0 C (PACKAGE TYPES 0, Fl
...........................
500mW
..... Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR T A = FULL PACKAGE·TEMPERATURE RANGE (ALL PACKAGE TYPESI . . . . . . .
100 mW
INPUT VOLTAGE RANGE, ALL INPUTS.
. . . . . . . . . . . . . ..
-O.S to V DD +0.5 V
LEAD TEMPERATURE (DURING SOLDERINGI:
.
At distance 1/16 ± 1/32 Inch (1.59 ± 0.79 mm I from case for lOs max. . ........... .
RECOMMENDED OPERATING CgNDITIONS
For maximum reliability, nominal operating oonditions should be selected so that
operation is always within the following range:
LIMITS
Min_
Max.
CHARACTERISTIC
Supply Voltage Range (For T A = Full Package
Temperature Range)
VDD
JD
•
NETWORK
12
V
JD
, !
vss
Quiescent current spacified to 15 V
Maximum input paakage of 1 IJA at 15 V
(full package-temperature range)
1·V noise margin (full package temperature
ranga)
Applications:
3
~S--0UTP\lT
* BYALLCOS/MOSPROTECTION
INPUTS PROTECTED
•
•
UNITS
~~TRU£
Vss
Features:
True Output
• High current source and sink capability
8 mA (typ.) @ VOS'= 0.5 V. VOO = 10 V
3.2 mA (typ,) @ VOS = 0_4 V, VOO = 5 V
(two TTL loads)
Complement Output
• Medium current source and sink capability
3_6 mA (typ.) @ VOS = 0.5 V, VOO" 10 V
1.6 mA (typ.) @ VOS" 0.5 V, VOO" 5 V
•
•
•
•
•
High current sourcelsink driver
COS/MOS-to-OTLrrTL converter
Display driver
MOS clock driver
Resistor network driver
(Ladder or weighted R)
•
•
Buffer
Transmission line driver
Vss
VDD
d
J
-------OOCOMPLEMENT
OUTPUT
i
V55
92CS-to055RI
Fig. I - CD4041 A schematic diagram _
_________________________________________________________ 525
CD4041 A Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 250 C and CL = 15 pF, RL = 200 kn
LIMITS
TEST
CONDIT~
CHARACTERISTIC
VDD
(Volts)
H igh-to-Low Level
tpHL
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
True
Output
Propagation Delay Time:
Comp_
Output
True
Low-to-H igh Level
Output
tpLH
Compo
Output
True
Transition Time:
High-to-Low Leve'
Output
tyHL
True
Output
Low-to-High Level
tyLH
Input Capacitance
Compo
Output
CI
Compo
Output
Any Input
D,F,H
Packages
E
Package
TYP. MAX.
UNITS
TYP. MAX.
65
40
55
30
75
45
45
25
20
13
40
25
20
13
35
25
115
75
100
45
125
75
100
40
40
25
60
40
40
25
55
40
65
40
55
30
75
45
45
25
20
13
40
25
20
;3
35
25
140
100
125
65
150
100
125
60
60
40
80
50
60
40
75
50
5
-
5
-
ns
ns
ns
Fig.S - Minimum output n~hannel drain charac-
ns
teristics -complement output.
ns
ns
ns
ns
pF
ORAIN:TO-SOUACE VOLTA.GE:IVOS1-V
Fig.9 - Minimum output p~hBnnel drain charac-
teristics - complement output.
Z.'
12.5
Fig. 10 - Minimum and maximum transfer charac-
teristics - true output.
IT.5
I:teS·ilOO45
ITA'- 25"'C
0
~
0
0
1-=
I--
0
10
80
90
(~l-PF
92CS-20047
Fig. 13 - Typical high-to-Iow IBvel trBn.ition
time VI. CL - complement output.
92CS-20046
Fig.tt - Minimum and maximum tranlfsr charac.
teristics - complement output.
AMBIENT TEMPERATURE
LOAD CAPACITANCE
zo
I'
..... UT VOLTAGE IV.I-V
INPUT VOLTAGEtvJI-V
10
J.
1,_.1
~"OO'. 5" __
, "O\.".;....-rs""~
b::::::
J:b - - l- t-
Fig. 12 - Typical transition time vs.
CL - truB output.
.
~IOO
I I
0
ao
90
92CS-20048
1«1
o-~
0
20- lIO 40 eo 60 70
LOAD CAPACITANCE ICLI-PF
c
o
1'00",'0'
L VV
'T· ..I· """';;.~/.
AMBIENT TEMPERATURE
=
I 1
IJoo" " " ' - -
I-
~
1--:1:
::.J.-Woo,-\5V
'0
..,
20
40
60 10
i..OAD CAPACITANCE (Ct.l-PF
""
80
90
92CS-20049
Fig. 14 - Typicallow-to-high level propagation
delay time VB. CL - truB output.
Fig. i5 - Typicallow-to-high levBI propagation
delay time VI. CL - cOmplement output.
526 ____________________________________________________________________
CD4041 A Types
STATIC ELECTRICAL CHARACTERISTICS
Limits at Indicated Temperatures (OC)
Conditions
Characteristic
Quiescent Device
Current, I L
Max.
Output Voltage:
Low·Level.
VOL
High·Level.
VOH
-40
Package
+85
+25
Typ. Limit
10
20
250
0.01
0.02
2.5
E
Vo
(V)
VIN
(V)
VDD
(V)
-
-
5
10
15
-
0.5
0.10
5
10
oTyp.: 0.05 Max.
oTyp.: 0.05 Max.
-
0.5
0.10
5
10
4.95 Min.: 5 Typ.
9.95 Min.: 10 Typ.
-
5
10
1.5 Min.: 2.25 Typ.
3 Min.: 4.5 Typ.
5
10
1.5 Min.: 2.25 Typ.
3 Min.: 4.5 Typ.
-
Noise Immunity:
3.6
Inputs Low.
7.2
VNL
Inputs High,
1.4
VNH 2.8
Noise Margin:
Inputs Low,
VNML
D, F ,H Packages
+25
+125
-55
Typ. Limit
4.5
9
I nputs High,
0.5
VNMH 1
-
-
-
-
1
2
25
0.005
0.005
0.25
1
2
25
60
120
1000
5
10
1 Min.
1 Min.
5
10
1 Min.
1 Min.
Output Drive
Current:
~
True
0.5
N·Channel
(Sink).
~ Camp.
ION Min. 0.5
5
10
5
10
P·Channel
~
True
9.5
(Source)
lOP Min. ~ Compo
9.5
5
10
5
10
Input Leakage
Current.
Any Input
IIL,IIH
15
2.1
6.25
1
2.5
3.2
10
1.6
4
1.6
5
0.8
2
1.2
3.5
0.55
1.4
1
3
0.5
1.2
10
140
20
280
250 2500
Units
IJA
V
Fig.2 - Typical output n-channel drain charac-
teristics - true output.
V
V
3.2
10
1.6
4
0.8
2.5
0.4
1
0.7
2.2
0.35
0.9
ORAIN-TQ-$OUR(£ YOt..TAGE ""OSI-V
rnA
-1.75
-5
-0.75
-2.25
-2.8
-8
-1.2
-3.6
'16.17'OR INPUT RISE AND fall.
*SE£TillE
LlMITATlotrIS
Fig.3 - Typical output p-channel drain cheracteristicl - true output.
-1.4 -1 -0.85 -2.8 -0.7 -0.6
-4 -2.8 -2.4
-8
-2 -1.8
-0.6 -0.4 -0.35 -1.2 -0.3 -0.27
-1.8 -1.25 -1.1 -3.6 -0.9 -0.8
±10- 5 Typ.: 1 Max.
jJ.A
.5EE F'1Cj.17 rOR INPUT RISE ANOFAI.!.
TIME L.IMITATIONS
Fig.4 - Typical output n-channel drain characteristics - complement output.
DRAlN-TO-SOURCE VOLTAGE ""OSI-\1
Fig.5 - Typical output p-channel drain charac-
teristics - compJeme'!t output.
........,..
Fig.6 - Minimum output n-channel drain charac-
teristics - true output.
QRAIN-TO-SOUACE va..TAGE {Vasl-V
Fig.7 - Minimum output p-channel drain characteristics - true output.
_________________________________________________________________ 527
CD4041A Types.
",.
.
.
Voo
Vss
;. .;.
:.e
..
...
Veo
..
..~"-
INPUTS
0
i~
Voo·s¥,'OIocnMl
;:
:.e
"
1032
4
104~'' ti
8105 2 '" 811)6 2
FREQUENCY Ifl HI
.. 68 107
Fig. 16 - Typical power dissipation
VI.
frtJquency per output pair.
VDD-VNH
'NPursOVDOOUTPUTS
---..
_
~
=
o
VNL
Fig. 17 - Typical power dissipation VI. input
rise & fall time per output pair.
V~NPU(J".
Vss
TO BOTH YDD
WITH
92ts-274oo
Fig. 19 - NO;IB immunity test
528
N'Ul'S TO EITHER
YDD ORVIS'
cmE:R INPUTS AT
VDD OR Vss'
circuit.
AN)"ss
taNNICT ALL UNUSED
NOTE:
TEST ANY ONE INPUT,
Vss
='::'
V55
Fig.20 - Input leakage current test circuit.
Fig.tS - Quiescent device current test circuit.
CD4042A Types
COS/MOS Quad Clocked
no"
Latch
D,
The RCA-CD4042A types contain four latch
and POLARITY levels defined above are
circuits, each strobed by a common clock.
present. When a CLOCK transition occurs
Complementary buffered outputs are availa(positive for POLARITY = 0 and negative
ble from each circuit. The impedance of the
for POLARITY = 1) the information present
n- and p-channel output devices is balanced
at the input during the CLOCK transition is
and all outputs are electrically identical.
retained at the outputs until an opposite
CLOCK transition occurs.
Information present at the data input is
transferred to outputs Q and Q during the
Thesetypes are supplied in 16-lead hermetic
CLOCK level which is programmed by the
dual-in-line ceramic packages (0 and F
suffixes), 16-lead dual-in-line plastic packPOLARITY input. For POLARITY = 0 the
age (E suffix). 16-lead ceramic flat package
transfer occurs during the 0 CLOCK level,
(K suffix), and in chip form (H suffix).
and for PO LAR ITY = 1 the transfer occu rs
during the 1 CLOCK level. The outputs
follow the data input providing the CLOCK
MAXIMUM RATINGS,Absolutl/-Maximum Values:
STORAGE-TEMPERATURE RANGE (Tstg ) . • • • . . . • • • • • • • • • • • . • . • • • . . .-65 to +1500 C
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPES 0, F, H
• . • • • . • . • • . • • . . • • • • • • . • • . _..•••••.-55 to +125 0 C
PACKAGE TYPE E .••.••••..•...•••.. , ••••.•••• , •••••• , •• -40 to +85 0 C
DC SUPPLY-VOLTAGE RANGE, (VDD)
(Voltages referenced to Vss Terminal!: • • . . . • . • • • • • • • • . • • , •..••• , •• -0.5 to +15 V
POWER DISSIPATION P';,R PACKAGE (PO):
FOR T A = -40 to +60 C (PACKAGE TYPE E)
.•••••.••••••.• , •.•.• , ••• 500 mW
FOR T A = +60 to +85°<;. (PACKAGE TYPE E )
•• , ••. Derate linearly at 12 mW/C to 200 mW
FOR TA = -55 to +100 C (PACKAGE TYPES 0, F)
. • • . • • . • • . • . • • • • , •...• 500 mW
0
FOR TA = +100 to +125 C (PACKAGE TYPES 0, P)
.•. Derate linearly at 12 mW/C to 200 mW
DEVICE DISSIPATIO['l PER OUTPUT TRANSISTOR
D,
D,
r---"'-O'O
D,
D.
t-Ur-~~O"
"D---IHr--''''--O
,.~~~"
CL.OCK
POLARITY
• 0::...........-1.....)
VDD~
Vsso!CD4042A
FUNCTIONAL DIAGRAM
Features:
• Clock polarity control
Q and Q outputs
• Common clock .
• Low power TTL compatible
• Quiescent current specified to 15 V
• Maximum input leakage of 1 JJA at 15 V
(full package-temperature range)
• 1-V noise margin (full package-temperature
range)
I!II
Applications:
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (ALL PACKAGE TYPES) ..••••• 100 mW
INPUT VOLTAGE RANGE, ALL INPUTS •••.••• , • • • • • • • . . . • • • • • . -0.5 to VDD +0.5 V
LEAD TEMPERATURE (DURING SOLDERING):
• Buffer storage
• Holding register
• General digital logic
At distance 1/16 ± 1/32 inch (1.59 ±0.79 mm) from case for 10 s max .••••••..•• , •• +2650 C
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C, Input tr ,tt = 20 ns, CL = 15 pF,
RL=200Kn
D,
D,
LIMITS
VOO
CHARACTERISTIC
Propagation De)ay
Time: tPHL, tPLH
Data In to Q
(V)
5
10
D,F,H
Packages
E
Package
UNITS
Typ,
Max,
Typ,
Max,
150
75
300
150
150
75
400
200
ns
5
10
250
100
500
200
250
100
600
250
5
10
300
125
600
250
300
125
750
300
5
10
400
175
800
350
400
175 '
1000
400
ns
Transition Time:
tTHL,lTLH
Minimum Clock
Pulse Width, tw
5
10
100
50
200
100
100
50
300
150
ns
5
10
175
60
250
120
175
60
350
175
ns
Minimum Hold
Time,tH
5
1'0
150
60
300
120
150
60
350
150
ns
Minimum Setup
Time,ts
5
10
0
0
50
30
0
0
50
30
ns
Minimum Clock Rise
or Fall Time: tr , tf
5
10
~ Not rise or fall time sensitive.
Input Capacitance, CI
(Any Input)
-
Data In to Q
Clock to Q
Clock to Q
5
-
5
-
0',
""0,
ns
ns
r"'iWf-J
I
I
I
I
p
"
I
I
POLARITY
cL
_
P
P
JJ.S
pF
d
I
I
I
~
, I
_
L _________
I
I
P___
....J
* AU. INPUTS ARE
PROTECTED BY
COS/NOS PROTECTION
NETWORK
fvss
CLOCK
0
-.r
1
"-
POLARITY
0
Q
0
LATCH
1
1
LATCH
0
0
Fig. 1 - Logic block diagram & truth table.
529
CD4042A Types
RECOMMENDED OPERATING CONDITIONS at TA = 25°C, Except as Noted.
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges:
AMBIENT TEMPERATURE ITA'· 2S·C
T'l'PICAl TEMPERATtJRECOEFFICIENT fOR ID~-O.3%/-C
!
VDD
CHARACTERISTIC
IV)
D,F,H
Packages
~
UNITS
E
Package
Min.
Max.
Min.
Max.
3
12
3
12
Supply·Voltage Range
(For T A = Full Package
Temperature Range)
-
Clock Pulse
Width,tw
5
10
350
175
Setup Time, 1:S
5
10
50
30
Hold Time, tH
5
10
350
150
Clock Rise or Fall
Time: t r, tf
5
10
2$
GATE-lO-SOURCE VOLTAGElVGSI-15V
{/
LIMITS
i
~
20
15
,ov
V
10
12.5
15
DRAIN-TO-SCIlJICE VOLTAGE tVoSI-V
-
250
120
-
-
ns
-
ns
-
Fig. 2 - Typical output n-channel drain
characteristics.
50
30
-
300
120
-
-
ns
Not rise"or fall time sensitive.
/J5
DRAIN-TO-SOLIICE VOlTAGE IVoSI-V
'OV
-10
I
-" il
GATE-TO-SOLRCE VOLTAGE: t
.0'5v
STATIC ELECTRICAL CHARACTERISTICS
Limits at Indicated Temperatures (oC)
Conditions
.lM8IENT TEMPERATURE I TA I • ZS·C
D,F,H Packages
E Package
+25
+251
+125 -40
+85
Typ. Limit
Typ·1 Limit
Characteristic
Units
Vo VIN VDD -55
IV) IV) (V)
Quiescent Device
Current, I L Max.
Output Voltage:
Low·level,
VOL
High level,
VOH
Noise Immunity:
Inputs Low,
VNL
Inputs High,
VNH
Noise Margin:
Inputs Low,
VNML
Inputs High,
VNMH
Output Drive
Current:
n·Channel
(Sink),
IDNMin.
p·Channel
(Source),
IDPMin.
Input leakage
Current,
IIL,IIH Max.
- - - - 0,5
- ~,10
- 0,5
5
10
15
4.2
1
2
25
0.005
O.OOS
0.25
1
2
25
60
10 0.01 10
120
20 0.02 20
1000 250 2.5 250
140
280
2500
10
o Typ.; 0.05 Max.
oTyp.; 0.05 Max.
5
4.95 Min.; 5 Typ.
kl,10
10
9.95 Min.; 10 Typ.
5
1.5 Min.; 2.25 Typ.
10
3 Min.; 4.5 Typ.
5
1.5 Min.; 2.25 Typ.
1
-
0.5
-
5
0.5
1
0.4
0.27
0.24
1
0.2
0.18
0.5
-
10
1.25
2
1
0.7
0.6
2
0.5
0.45
5
'0.45
·1
·0.35 ·0.25 ·0.2
·1
0.178 ·0.15
10 ·1.15
-2
-2
-0.45
9
0.8
1
4.5
9
0.5
4.5
9.5
-
Any
Input
5
10
Fig. 3 - Typical output p-channel drain
characteristics.
pA
M8£NT T£WIERATURE IT..,I. 25'"C
T'fPlCAL ThlPERATURf COEmCENT FOR:ro • - 0.3% ,-c,
"
V
,5V
'OV
V
1 Min.
5
10
1 Min.
,
7.'
}
}
t:tt
2.5
C0404ZAE
10
12.'
- --
"
DRAIN - TO - SOURCE VOLTAGE: IVosl
1 Min.
10
CD4042AO,ctl4042AIC,
CD4042Af
10V
2.5
3 Min.; 4.5 Typ.
5
.,.
•
TYPICAL TEMPERATURE COEF'FIQENT fOR ID"-O.''ItoI-C
Fig. 4 - Minimum n-channel drain characttlristics.
V
DRAIN - TO -SOURCE VOLTAGE IVosl-V
1 Min.
-15
-10
-5
AMBIENT TEMPERATURE (fAl. 25-C
TYPICAL TEMPERATURt: COEFFICIENT
FOR ID--O."."-c
IOV
GAT[-TO-SOUilC£ VOLTAGE I
15
/
-0.9
-0.6
-0.34
±lo-5 Typ.; 1 Max.
"1!lV
mA
}<.~.
-15
-0.4
---
pA
Fig~
}
CD4042AE
5 - Minimum p~hann81 drain characteristics.
530 __________________________________________________________________
CD4042A Types
NOTE I
CCgCK {
~
NOTE 2
'""I----F
Clo50pF---
Vss
Fig. 11 - Typical dissipation characteristics.
Fig. 12 - Quiescent device current test circuit.
Fig. 13 - Noise immunity test circuit.
V~~NPU(JS
VDO :~:~U.E 'NPUTS
o ~
SEQUENTlAL.LY,
\Iss
TO 90TH \100 AHOVss
CONNECT ALL. UNUSED
INPUfS 1'0 EITHER
Voo OR Yss'
IISS
FiG- 14 - Input leakage current test circuit.
531
CD4043A,· CD4044A Types
COS/MOS Quad 3-State
R/S Latches
", r'>-"'-......
"",
Quad NOR RIS Latch - CD4043A
Quad NAND RIS Latch - CD4044A
,
0,
5,
'2
'2
The RCA·CD4043A types are quad cross·
coupled 3'state COS/MOS NOR latches and
the CD4044A types are quad cross·coupled
3'state COS/MOS NAND latches. Each latch
has a separate Q output and individual SET
and RESET inputs. The Q outputs are can·
trolled· by a common ENABLE input. A log·
ic "1" or high on the ENABLE input can·
nects the latch states to the Q outputs. A
logic "0" or Iowan the ENABLE input
disconnects the latch states from the Q out·
puts, resulting in an open circuit condition
on the Q outputs. The open circuit feature
allows common busing of the outputs. The
logic operation of the latches is summarized
in the truth table shown in Fig. 1.
These types are supplied in 16-lead hermetic
dual-in-line ceramic packages (D and F
suffixes), 16-lead dual-in-line plastic package (E suffix), 16-lead ceramic flat packages
(K suffix), and in chip form (H suffix).
"
"
"".
o.
ENABLE
ENABLE
Nt
CD4044A
CD4043A
VS5
92CS-ZOiZ2!RI
FUNCTIONAL DIAGRAM
V55
92CS-20221
FUNCTIONAL DIAGRAM
Features:
Applications:
•
a·Level outputs with common
output ENABLE
• Separate SET and RESET inputs
for each latch
• NOR and NAND configurations
• Quiescent current specified to 15 V
•
Holding register in multi·
register system
• Four bits of independent
storage with output ENABLE
• Strobed register
• General digital logic
•
•
Maximum input leakage of 1 J.IA at 15 V
(full package-temperature range)
1-V noise margin (full package-temperature
range)
MAXIMUM RATINGS,Absolull1-Maximum Values:
C04043A- NOR
. STORAGE· TEMPERATURE RANGE (T,tg) . . . . . . . . • • • . . . . • • • . • • • • . . • .-65 to +150oC
OPERATING·TEMPERATURE RANGE (TA):
.
PACKAGE TYPES D. F. H . • . • . • . . . . • . . . . . • . • • . • • . . • . • . . . . • .-55 to +125 C
PACKAGE TYPE E . . • . • • • • . . . • • . • . . . • • • . • • . • . • • . • • . • . . • • . -40 to -+85 0 C
DC SUPPLY·VOLTAGE RANGE. (VDD)
(Voltagesreferenced to VSS Terminal): . • . . . . . . • • • . • . . . • . . • . • • • . . • . -0.5 to +15 V
POWER DISSIPATION PER PACKAGE (PD):
FOR TA: -40 to +60oC (PACKAGE TYPE E)
. . . • . • • . • • . • . • • • . • • • . • . • • 500 mW
FOR TA: +60 to -+85 0 C (PACKAGE TYPE E)
.•.••• Derate Linearly at 12 mW/C to 200 mW
o
FOR TA: -55 to +100 C (PACKAGE TYPES D. F)
. • . . . . . . . . . • • . . . • • • . . • 500 mW
FOR TA: +100 to +125 0 C (PACKAGE TYPES D. F)
... Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA: FULL PACKAGE·TEMPERATURE RANGE (ALL PACKAGE TYPES) . . • • . • . 100 mW
INPUT VOLTAGE RANGE. ALL INPUTS . • . . . • • . • . • • • • • • • • • • • • • • -0.5 to VDD +0.5 V
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ±0.79 mm) from case for 10 s max • . • . • • • . • • . . • . +265 oC
°
r
ONE OF foUR" L'ATCHESl
I
E
• I
"
I
I
I
I
3
.,
I
.
I
L _ _ _ _ _ _ .J
..
EN~~
,
x
a
o
oc'"
NC+
,
,
I
I
*OPEN CIRCUIT
0
I
~
A
02
+ NO CHANGE
IN
V••
••
R
GATES
01
A DOMINATED BY S- IINPUT
Vss
92CS';Z02U
ALL INPUTS ARE PROTECTED BY
COSfMOS PROTECTION NETWORk.
CD4044A-NAND
RECOMMENDED OPERATING CONDITIONS at T A = 25°C, Except as Noted.
For maximum reliability, nominal operating conditions should be selectad so that
operation is always within the following ranges:
r ONEOFFOURLATCH~l
I
, I
LIMITS
CHARACTERISTIC
VDD
(V)
Supply·Voltage Range
(For T A = Full Package
Temperature Range
-
Set or Reset Pulse
Width, tw
5
10
D,F,H
Packages
E
Package
UNITS
5,
Min.
Max.
Min.
Max.
3
12
3
12
200
100
-
225
110
-
•
V
EN~~
S
R
x
x
OC·
I
I
NC+
0'
ns
'0
o
E
Q
,
0
0
66
·OPEN CIRCUIT
-+ NO CHANGE
66 DOMINATED BY R-O INPUT
92CS-20212
Fig. 1 _. Logic diagrams end truth teble••
532 __________________________________________________________________
CD4043A, CD4044A Types
STATIC ELECTRICAL CHARACTERISTICS
Limits at Indicated Temperatures (oC)
E Package
Characteristic
Vo VIN VDD
+25
+25
IV) (V) IV) -55 Typ. Limit +125 -40 rryp· Limit
60
10 0.01 10
5
1 0.005
1
Quiescent Device
10
2 0.005 2
120 20 0.02 20
Current, I L Max.
- 15 25 0.25 25 1000 250 2.5 250
Output Voltage:
0,5 5
o Typ.; 0.05 Max.
Low·Level,
0,10 10
o Typ.; 0.05 Max.
VOL
4.95 Min.; 5 Typ.
High Level,
0,5 5
VOH
9.95 Min.; 10 Typ.
0,10 10
Noise Immunity:
4.2
5
1.5 Min.; 2.25 Typ.
Inputs Low,
3
Min.; 4.5 Typ.
. 9
VNL
- 10
5
1.5 Min.; 2.25 Typ.;
0.8 Inputs High,
VNH
3 Min.; 4.5 Typ.
10
1
Noise Margin:
4.5
5
1 Min.
Inputs Low,
1 Min.
9
- 10
VNML
Inputs High,
5
0.5
1 Min.
VNMH
1 Min.
10
1
Conditions
O,F,H Packages
- -
Units
+85
140
280
2500
f.IA
It
"h
~*ilt+-' ~ti+l fltliU
5
10
I~
DRAIN-fO-SOURCE vOLTAGE IV05)-\I
V
Fig.2 _ Typical output n-channel drain
characteristics.
ORAIN-TO-SOURCE VOLTAGE
-IS
-10
Ivos)-v
-:)
V
-
V
-
Output Drive
Current:
n·Channel
(Sink),
IDNMin.
p·Channel
(Source),
IDPMin.
Input Leakage
Current,
IIL,IIH
0.5
-
5
0.5
-
10 0.61
0.25
0.5
0.2
0.19 0.12 0.5
1
0.5
0.35
0:1
0.09
0.25
0.22
Fig. 3 - Typical output p-channel drain
4.5
9.5
Any
Input
1
0.3
5
·0.22 ·0.5 ·0.175 ·0.12 0.11 ·0.5 0.09 ·0.08
10
·0.5
·1
·0.4 ·0.28 0.24
mA
·0.2 ·0.18
·1
±10-5 Typ.; ±1 Max.
15
characteristics.
f.IA
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C; Input t r , tt = 20 ns, CL = 15 pF,
RL = 200 kn
LIMITS
VDD
CHARACTER ISTIC
O,F,H
E
Packages
Typ.
Max.
Propagation Delay
Time: tpHL, tpLH
SET or RESET to Q
5
10
175
75
350
175
175
75
400
200
ns
3-State Propagation Delay
Time: ENABLE to Q
tpHZ, tpZH
5
10
100
50
200
100
100
50
200
100
ns
5
10
80
40
160
80
80
40
160
80
ns
Transition Time:
tTHL·tpLH
5
10
100
50
200
100
100
50
250
125
ns
Minimum SET or RESET
Pulse Width. tw
5
10
80
40
200
100
80
40
225
110
ns
Average Input Capacitance. CI
(Any Input)
-
5
-
5
-
pF
tpLZ. tpZL
Package
Typ.
Max.
UNITS
IV)
Fig. 4 _ Minimum n-channel drain characteristics.
DRAIN-TO- SOURCE o.,tOLTAG£ lVosl-v
Fig. 5 - Minimum p-channel drain characteristics.
533
CD4043A, CD4044A Types
3~O
f3
AMBIENT TEMPERATURE ITAI'25'"C
~~:Ij~~ ~E:~~~~UR[ COEFFICIENT
J
f
:250
~
i
200
i~
"V
~
w
•
•
~
~
".
ro
~
ro
~
w
•
~
~
ro
~
10 2
e
~
~
LOAD CAPACITANC
CLoIS"
CL"!iO pF
10
10'
~
10·
IO!I
INPUT FREQUENCY-HI
LOAD CAPACITANCE leLI-pF
LOAD CAPACITANCE tCLI-pf
10'
"2CS-2ot20
92CI-2.0219
Fig. 8 - Typical diuipatlon charactllri't;cs.
Fig. 7 - TypicBl tran.itlon tlma ... CL'
Fig. 6 - Typical propagation dalay tima v.. CL•
INPUTS
NOTE:
"'P"OS
vDO
MUSURE: INPUTS
VDD
X
~
SEQUENTIALLY.
.
TO BOTH Voo AND 'Iss'
CONNECT ALL UNUSED
Vss
INPUfS TO EITNER
VDOCJIIVSS'
Vso
,1I:,-27.D,
Fig. 9 - Qui,scent device curmnt ten circuit.
_.[
VDD
TEST
,.
I.
"13
"
ENABLE
IN
iN IKD
10 f--+<~M.-o
"
IN
IN
A
IPHZ VDD Vss
v••
'PLZ V.. V D•
V. D
'PZH VDO Vso V ••
v••
' ..L VS5
z· HIGH
+-___9_..JICLo,5PF
Fig. 77 - Input laakage current te.t circuit.
Fig. 70 _ NoilS immunity lII.t circuit.
VD.
'MPEDANCE
0"
Uiii)"i
ENABLE
Ao---------+--l
r-----l
Vss
Bu'J!; -
ENABLE
10
;~ ·
•
12
~
COiOi
UN':'J:;.-&.VSS)
.11'3 Voo
POINT A ----r""'--
,
"
3 C04043
"
I
" L. _ _ _ _ _ JI
V5S
10
"
ENA8LE 8 0 - - - - - - - - - + - - '
.213 YDD
UN-Yss.m. YOD}
tpZL .....
Bu'J[1-·-·--\
Fig. 72 - ENABLE propagation daIsy tlma te.t circuit and we.. fo"" ..
APPLICATIONS
VDO
"
"
_
4
•
"
,.
I
_ ____ J I
LOAD C
ENABLE C
0-------.:---+--'
4
•
"
,
~
3 C04043
IMO
LOAD D
VoD
ENAILE
92CS-2020,RI
Fig. 73 - Switch bounca eliminator.
10
""
00----------+--'
RESET
Fig. 74 - Multiple bu. storaga.
534 __________________________________________________________________
CD4045A Types
COS/MOS 21-Stage Counter
The RCA·CD4045A is a timing circuit con·
sisting of 21 counter stages, two output·
shaping f1ip·flops, two inverter output
drivers, three 5.5·V zener diodes (providing
transient protection at 16.5 V), and input
inverters for use in a crystal oscillator. The
CD4045A configuration provides 21 flip·
flop counting stages, and two flip·flops for
shaping the output waveform for a 3.125%
duty cycle. Push·pull operation is provided
by the inverter output drivers.
The first inverter is intended for use as a
crystal oscillator/amplifier. However, it may
be used as a normal logic inverter if desired.
A crystal oscillator circuit can be made less
sensitive to voltage·supply variations by the
use of source resistors. In this device, the
sources of the p and n transistors have been
brought out to package terminals. If external
resistors are not required, the sources must
be shorted to their respective substrates (Sp
to V DO, Sn to VSS). See Fig. 3.
These types are supplied in 16-lead hermetic
dual-in-line ceramic packages (0 and F
suffixes), 16-lead dual-in-line plastic package (E suffix), 16-lead ceramic flat packages
(K suffix), and in chip form (H suffix).
App/ications:
• Digital equipment in which ultra·low
dissipation and/or operation using a
battery source are primary design
requirements.
• Accurate timing from a crystal
oscillator for timing applications
such as wall clocks, table clocks,
automobile clocks, and digital
timing references in any circuit
requiring accurately timed outputs
at various intervals in the counting
sequence.
• Driving miniature synchronous motors,
stepping motors, or external bipolar
transistors in push·pull fashion.
MAXIMUM RATINGS,Absolute·Maximum Values:
STORAGE.TEMPERATURE RANGE (T Slg ) . . • . , • . . . . . . . . . . . . • . . . . . , . . . . -65 to +150oC
OPERATING·TEMPERATURE RANGE (TA):
PACKAGE TYPES 0, F, H
••.. ' .•.... ' • • . • . . . . . . • . . . . . . . . . . . . . • -55 to +125:C
PACKAGE TYPE E
. . • • . . • . • . . . • . . • . . . . . . . . . . . . . . . . . . • • . . . -40 to +85 C
DC SUPPLY·VOLTAGE RANGE, (VDD)
(Voltages referenced to VSS TerminaU: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to +15 V
POWER
FOR
FOR
FOR
FOR
DISSIPATION PER PACKAGE (PO):
TA= -40 to +60 oC (PACKAGE TYPE E)
. . . • . . . . . . • . . . . . . . . . . . . • . . . . 500 mW
TA= +60 to +850 C (PACKAGE TYPE E 1 . . . . . . • . . Derate Linearly at 12 mWloC to 200 mW
TA= -55 to +100 oC (PACKAGE TYPES 0, FJ
. . . . . . • . • . . . . . . . . . . • . . . . 500 mW
TA= +100 to +125 0 C (PACKAGE TYPES 0, Fl
. . . . . Derate Linearly at 12 mWt"C to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA= FULL PACKAGE·TEMPERATURE RANGE (ALL PACKAGE TYPES) . . . . . . . . . 100 mW
INPUT VOLTAGE RANGE, ALL INPUTS . . . . • • . . . . . • • . . ' . . . . . . . . . . . -0.5 to VDD +0.5 V
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1116 ±1132 inch (1.59 ±0.79 mm) from case for 10 s max . . . . . . . . . . . , ... ,+265 0 C
VDO)
4,5,6,9,10,11,12,13=
NO CONNECTION
ncs - ~0943
Vs s
I.
CD4045A
FUNCTIONAL DIAGRAM
Features:
• Microwatt quiescent dissipation, . , , . ,
2.5 lIN (typ.) @ VDD = 5 V;
10 lIN (typ.) @ VDD = 10 V
• Very low operating dissipation .....•
1 mW (typ,);@VDD=5 V, f¢= 1 MHz
• Output drivers with sink or source
capability ..... .
7 mA (typ.) @VO= 0.5 V,
VDD = 5 V (sink)
5 mA (typ.) @VO=4.5V,
VDD = 5 V (source)
• Medium speed (typ.) .....
f¢= 5 MHz@VD D =5 V
f¢=10MHz@VDD=10V
• 16.5 V zener diode transient protectior.
on chip for automotive use
• Quiescent current specified to 15 V
• Maximum input leakage current of 1 J.LA
at 15 V (full package·temperature range)
• 1·V noise margin (full package·temper·
ature range)
RECOMMENDED OPERATING CONDITIONS at TA = 25°C, Except as Noted.
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges:
LIMITS
CHARACTERISTIC
VDD
(VI
Supply· Voltage Range (For T A=Full
Package·Temperature Range)
O,F.H
Packages
E
Package
Min,
Max.
Min,
Max,
3
12
3
12
V
-
-
ns
3.5
6.5
15
10
MHz
Input·Pulse Width, tw
5
10
115
60
-
140
75
Input·Pulse Frequency, f¢
5
10
5
10
dc
dc
4.4
8.5
15
10
dc
dc
Input·Pulse Rise or Fall Time, t r¢, ttI/J
UNITS
-
-
-
JJS
NOTE 1: To minimize power dissipation in the
zener diodes,
dissipation less
current-limiting
in series with
VOO>13 V.
and to ensure device
than 200 mW, a 150
resistor must be placed
the power supply for
NOTE 2: Observe power-supply
tions, VOO is terminal
terminal No. 14 (not
tively, a. in all other
16·lead devices).
n
terminal connecNo.3 and VSS is
16 and 8 respecCD4oo0A Series
535
CD4045A Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA
=25°C, Input tr ,tf =20 ns,
CL = 15 pF, RL = 200 k!2
LIMITS
CHARACTERISTIC
TEST
CONDITIONS
VDD
(V)
E
D,F,H
Packages
Min.
UNITS
Package
Typ. Max. Min. Typ. Max.
tPLH, tPHL
10
Transition Time:
tTHL, tTLH
10
-
5
4.4
10
B.5
10
-
6.5
10
-
5
-
100
115
100
140
50
60
-
50
75
-
-
15
10
-
-
-
15
10
J.IS
-
5
-
-
5
-
pF
Propagation Delay Time:
5
cp to y or y+d out
5
Maximum Input·Pulse
Frequency, f mcp
Minimum Input·Pulse
Width,tw
10
Input·Pulse Rise & Fall
Time; t,cp, tteJ>
Average Input
Capacitance, CI
5
10
Any Input
2.2
4.4
-
2.2
5.5
1.2
2.4
-
1.2
3.3
450
BOO
-
450
900
375
650
-
375
750
5
-
3.5
5
-
J.IS
-
ns
DRAIN-TO-SOURCE VOLTAGE {Vosl-V 92.CS-ZOe9r.RI
Fig. , - Typical output n-channel dlilin
characteristics.
MHz
ns
DRAIN TO SOURCE VOLTAGE tvosJ-V
92CS-Z0897RI
Fig. 2 - Minimum output n-channel drain
characteristc8.
ORAIN TO SOURCE VOLTAGE tvosl-V
2.097152
MH,
=
L
EXTERNAL - - '
COMPONENTS
'n
nCM-20en
Fig. 4 - Typical output p-channel drain
Fig. 3 - CD4045A and outboard component:< in a typical 21·stage counter application.
characteristics.
DRAIN TO SOURCE VOLTAGE IVDSl-V
10
PLASTIC PACICAGE__
AMBIENT TEMPERATURE ITA'o25°C
CERAMIC PACICAGlE-
IO~
10'
10'
INPUT fREQUENCY(f.)-Hz
92CS-20115AI
Fig. 5 - Minimum output p-channel drain
characteristics.
Fig. 6 - Typical dissipation VB input frequency
(21 countingstagesJ.
Fig. 7 - Typical zener diode characteristics.
536 ____________________________________________________________________
CD4045A Types
STATIC ELECTRICAL CHARACTERISTICS
Limits at Indicated Temperatures (DC)
D,F,H Packages
E Package
+25
+25
Vo VIN VOO -55
+85
+125 -40
(V) (VI (V)
Typ. Limit
Typ. Limit
Co'nditions
Characteristic
Quiescent Oevice
Current I L Max.
-
Output Voltage:
Low·Level,
VOl
High Level
VOH
Noise Immunity:
Inputs Low,
VNL
Inputs High
VNH
Noise Margin:
Inputs Low,
VNML
Inputs High,
VNMH
Output Orive
Current:
n·Channel
(Sink)
ION Min.
p-Channel
(Source):
lOP Min.
-
-
-
5
10
15
15
25
50
0.5
1
1
15
25
50
900 50
1500 100
2000 500
1
2
5
5
5
o Typ.; 0.05 Max.
10
10
o Typ.; 0.05 Max.
0
0
5
10
4.95 Min.; 5 Typ.
9.95 Min.; 10 Typ.
92C$-20955
-
5
1.5 Min.; 2.25 Typ.
-
10
3 Min.; 4.5 Typ.
0.8
-
1
1.5 Min.; 2.25 Typ.
3 Min.; 4.5 Typ.
4.5
-
5
10
9
-
IJ.A
SUPPL't' VOLTAGE [V001-Y
9
-
50 700
100 1400
500 5000
V
4.2
0.5
1
Units
Fig. 8 - Typical propagation delay Ie/>, to
y or y+d out) V$ VOO '
V
1 Min.
5
10
1 Min.
5
10
1 Min.
1 Min.
V
LOAD CAPACITANCE [CL1-pF
0.5
-
5
0.5
-
10
4.5
-
5
4.4
7
3.5
2.5
2.2
7
1.8
1.3
6.9
11
5.5
3.9
3.5
11
2.8
2
Fig. 9 - Typical transition time vs CL"
mA
-3.1 -5 -2.5 -1.8 -1.6 -5 -1.3 -0.9
-
Input Leakage
Current,
IIL,IIH
Zener Breakdown
Voltage, V(BR)Z
10 -5.6 -9 -4.5 -3.2 -2.8 -9 -2.3 -1.6
9.5
Any Input '
±10-5 Typ., ±1 Max.
15
- 1-
Min. 13.3 13.5
1-100,uA Typ.
16.5 -
-
Max. 17.8
-
18
13.7 13.3
-
-
18.2 17.8
-
IJ.A
13.5 13.6
16.5
-
-
-
18
18.1
V
SUPPLY VOLTAGE CVool-Y
Fig. 10 - Typical maximum input-pulse
frequency.
INPUTS
o
Vss
Voo
1NPUO'
Vco
NOTE'
~
MEASURE INPUTS
SEQUENTIALLY,
o ~
Vss
TO BOTH Voo AND Yss'
CONNECT ALL UNUSED
INPUTS TO EITHER
Voo OR Vss '
v,s
Vss
92CS-27441
Fig. 11 - Quie&-:ent-device-current
Fig. 12 - Noise-immunity test circuit.
Fig. 13 -lnput4eakage-current test circuit.
______________________________________________________
~
test circuit.
__________ 537
CD4046A Types
COS/MOS Micropower Phase-Locked Loop
The RCA-CD4046A COS/MOS Micropower
Phase-Locked Loop (PLL) consists of a lowpower, linear voltage-controlled oscillator
(VCO) and two different phase comparators
having a common signal-input amplifier and
a common comparator input. A 5.2-V zener
diode is provided for supply regulation if
necessary.
These types are supplied in 16-lead hermetic
dual-in-line ceramic packages (D and F
suffixes). 16-lead dual-in-line plastic package (E suffix), 16-lead ceramic flat package
(K suffix), and in chip form (H suffix).
VCO Section
The VCO requires one external capacitor Cl
and one or two external resistors (R 1 or R 1
and R2). Resistor Rl and capacitor Cl
determine the frequency range of the VCO
and resi£tor R2 enables the VCO to have a
frequency offset if required. The high input
impedance (l012n) of the VCO simplifies
the design of low-pass filters by permitting
the designer a wide choice of resistor-tocapacitor ratios. In order not to load the
low-pass filter, a source-follower output of
the VCO input voltage is provided at terminal
10 (DEMODULATED OUTPUT). If this
terminal is used, a load resistor (RS) of 10
kn or more should be connected from this
terminal to VSS. If unused this terminal
should be left open. The VCO can be connected either directly or through frequency
dividers to the comparator input of the
phase comparators. A full COS/MOS logic
swing is avai lable at the output of the VCO
and allows direct coupling to COS/MOS
frequency dividers such as the RCA-CD4024,
CD4018, CD4020, CD4022, CD4029, and
CD4059_ One or more CD4018 (Presettable Divide-by-N Counter) or CD4029 (Presettable Up/Down Counter), or CD4059A
(Programmable Divide-by-"N" Counter), together with the CD4046A (Phase-Locked
Loop) can be used to build a micropower
low-frequency synthesizer. A logic a on the
INHIBIT .input "enables" the VCO and the·
source follower, while a logic 1 "turns off"
both to minimize stand-by power consumption_
Phase Comparators
The phase-comparator signal input (terminal
14) can be direct-coupled provided the signal
swing is within COS/MOS logic levels [logic
"0" <;;30% (VDD-VSS), logic "1" ;;;. 70%
(VDD-VSS)]. For smaller swings the signal
must be capacitively coupled to the selfbiasing amplifier at the signal input.
Phase comparator I is an exclusive-OR network; it operates analagously to an overdriven balanced mixer. To maximize the lock
range, the signal- and comparator-input frequencies must have a 50% duty cycle. With
no signal or noise on the signal input, this
phase comparator has an average output
voltage equal to VDD/2. The low-pass filter
connected to the output of phase comparator
I supplies the averaged voltage to the VCO
input, and causes the VCO to oscillate at the
center frequency (fa).
The frequency range of input signals on
which the' PLL will lock if it was initially
538
Features:
• Very low power consumption:
70 JJ-W (typ,) at VCO fa = 10 kHz, VOO = 5 V
• Operating frequency range up to 1_2 MHz (typ.)
at VDD = 10 V
• Wide supply-voltage range: VOD - VSS = 5
to 15 V
• Low frequency drift: 0_06%/oC (typ.)
atVOO=10V
• Choice of two phase comparators:
1. Exclusive-OR network
2. Edge-controlled memory network with
phase-pulse output for lock indication
• High VCO linearity: 1% (typ.)
• VCO inhibit control for ON-OFF keying
and ultra-low standby power consumption
• Source.follower output of VCO control input
(Demod. output)
• Zener diode to assist supply regulation
• Quiescent current specified to 15 V
• Maximum input leakage current of 1 JJ-A
at 15 V (full package-temperature range)
Applications:
•
•
•
•
•
•
•
•
•
CI
-wr-,.,/T'
FM demodulator and modulator
Frequency synthesis and multiplication
Frequency discriminator
Data synchronization
Voltage-to-frequency conversion
Tone decoding
FSK - Modems
Signal conditioning
(See ICAN-6101) "RCA COS/MOS
Phase-Locked Loop - A Versatile
Building Block for Micropower
Digital and Analog Applications"
,.---.-+Voo
<:'N,.....""''':/'V-+:t:'"O., GATES
Vss
ALL INPUTS ARE PROTECTED BY
COS/MOS PROTECTION NETWORK.
Fig. 1 - COS/MaS phase-locked loop block diagram.
MAXIMUM RATINGS, Absolute-Maximum Values:
STORAGE-TEMPERATURE RANGE IT stg )
OPERATING·TEMPERATURE RANGE ITAI'
-65 to +150o C
PACKAGE TYPES D. F. H
PACKAGE TYPE E
DC SUPPLY-VOL TAGE RANGE. IV DD )
{Voltages referenced to VSS Terminal) ..............•....
-55 to +125 0 C
-40 to 'S50C
-0.510 +15 V
POWER DISSIPATION PER PACKAGE IPDI,
FOR T A' -40 to 'SOoC IPACKAGE TYPE·E I
500mW
E"l
Derate Linearly at 12 mW/oC to 200 mW
FOR T A ' '60 to 'S50C {PACKAGE TYPE
FOR T A ' -55 to
'100 0 C
(PACKAGE TYPES D. F)
FOR T A ' '100 to .125 0 C IPACKAGE TYPES D. F)
500mW
..... Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA • FULL PACKAGE·TEMPERATURE RANGE IALL PACKAGE TYPESI . .
INPUT VOLTAGE RANGE. ALL INPUTS.
LEAD TEMPERATURE IDURING SOLDERING),
At distance 1116 ± 1/32 Inch f1.59 ± 0.79 mm) from case for 105 max.
out of lock is defined as the frequency capture range (2fcl.
The frequency range of input signals on
which the loop will stay locked if it was
initially in lock is defined as the frequency
lock range (2fLl. The capture range is <;; the
lock range.
With phase comparator I the range of frequencies over which the PLL can acquire
lock (capture range) is dependent on the
low-pass-filter characteristics, and can be
made as large as the lock range. Phase-com-
100 mW
-0.5 to V DD +0.5 V
parator I enables a PLL system to remain
in lock in spite of high amounts of noise
in the input signal.
One characteristic of this type of phase comparator is that it may lock onto input frequencies that are close to harmonics of the
VCO center-frequency. A second characteristic is that the phase angle between the
signal and the comparator input varies between 0 0 and 1800 , and is 900 at the center
frequency. Fig. 2 shows the typical, triangular, phase-to-output response characteristic
CD4046A Types
1[2'
I
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that
oparation is always within the following range:
'i
;
'100
YOLTAGE
~
~
0
90-
LIMITS
Min_
Max_
CHARACTERISTIC
YoD/2
Supply Voltage Range (For TA = Full Package
Temperature Range
eo·
SIGNAI..-TO- COMPA.RATOR
INPUTS PHASE DFfER£NCE
UNITS
12
3
V
92(S-20009
Fig.2 - Phase-comparator I characteristics
at low-pass filter output.
of phase-comparator L Typical waveforms
for a COS/MOS phase-locked-loop employing phase comparator I in locked condition
of fa is shown in F ig_ 3_
ELECTRICAL CHARACTERISTICS at TA = 250 C
Limits
Test Conditions
Characteristic
Vo Vee
Volls Volls
All Package Types
e,E,F,H
Min_
I
Typ_
Max_
Units
Phase Comparator Section
SIGNAL INPUT (TERM. 14)
..rLSL
~~P~x~:~~~r41& ~
ITERM 51
~~':.rIr I
YCO INPUT 'TERM.91• LOW-PA.SS FILTER
OUTPUT
SlIl..f1..f"'"-VOD
VCO Operation
Operaling Supply Voltage. VDe-VSS
Total Quiescent Device Current,
Term. 14 Open
Comparators on Iv
-V'S
Term. 14 al VSS or Vee
92CS-2OCI1ORI
Fig_3 - TVPical waveforms for COS/MaS phaselocked loop employing phase comparator
I in locked condition of f 0-
Phase-comparator II is an edge-controlled
digital memory network_ It consists of four
flip-flop stages, control gating, and a threestate output circuit comprising p- and n-type
drivers having a common output node_ When
the p-MOS or noMOS drivers are ON they
pull the output up to VDD or down to
VSS, respectively_This type of phase comparator acts only on the positive edges of
the signal and comparator inputs_ The duty
cycles of the signal and comparator inputs
are not important since positive transitions
control the PLL system utilizing this type
of comparator_
If the signal-input frequency is higher than the comparator-input
frequency, the p-type output driver is maintained ON most of the time, and both the
nand p drivers OFF (3 state) the remainder
of the time_ If the signal-input frequency
is lower than the comparator-input frequency, the n-type output driver is maintained
ON most of the time, and both the nand
p drivers OFF (3 state) the remainder of
the time_ If the signal- and comparatorinput frequencies are the same, but the
signal input lags the comparator input in
phase, the n-type output driver is maintained ON for a time corresponding to the
phase difference_ If the signal- and comparator-input frequencies are the same, but
the comparator input lags the signal in phase,
the p-type output driver is maintained ON
for a time corresponding to the phase difference_ Subsequently, the capacitor voltage
of the low-pass filter connected to this phase
comparator is adjusted until the signal and
comparator inputs are equal in both phase
and frequency_ At this stable point both pand n-type output drivers remain OFF and
thus the phase comparator output becomes
an open circuit and holds the voltage on the
capacitor of the low-pass filter constant_
Term. 14 (SIGNAL IN)
Input Impedance,
25
55
-
200
410
Term. 5 at Vee
5
15
10
-
5
Terms_ 3 & 9 al Vss
25
15
-
50
60
500
-
(peak'lo-peak)
DC·Coupled Signal Input
and Comparator Input
Voltage Sensitivity
Low Level
-Vo
High Level
Volts
IDP
5
1
2
10
0.2
0.4
-
15
-
0.2
-
5
-
200
400
10
400
800
15
-
700
-
5
10
1.5
3
2_25
15
4.5
6.75
-
5
-
2.75
3_5
10
-
15
-
5.5
8.25
7
-
4.5
Phase Comparator
0.5
5
0.43
0.86
I & II Term. 2 & 13
0.5
10
1.3
2.5
-
0.5
5
0.23
0.47
-
0.5
10
0.7
1.4
-
Phase Comparator
4.5
5
-0.6
-
I & II Term. 2 & 13
9.5
4.5
10
-0.3
-0_9
-1.8
5
-0.08 -0.16
-
9.5
10
-0.25
15
-
Phase Pulses
p·Channel (Source),
16
5
See Fig.7
IDN
15
-
10
AC.Coupled Signal Input
Voltage Sensitivity'"
n·Channel (Sinkl.
-
3
Term. 15 open
Z14
Outj>ut Drive Current:
5
-
IL:
~
-
Phase Pulses
Inpul Leakage Curren I, IIL.IIH Max.
Any Inpul
-0.5
±10- 5
V
p.A
Mn
mV
V
rnA
±1
J.lA
'" For sine wave, the frequency must be greater than 1 kHz for Phase Comparator II.
SIGNAL INPUT ITEIIM. 141
veo OUTPUTITERM41.
COMPARATOR INPUT
(TER.. "
PHASE COMPARATOR D
OUTPUT (TERM. 131
veo INPUT
_~- - -e--- - - - _-"._~:::
•
ITERM. ').
• LOW-PASS FILTER
OUTPUT
PHASE PULSE ITERM. I J
11
NOTE: DASHED LINE IS AN OPEN-CIRCUIT CONDITION
R
-YOO
,-V'S
u-~::
92CS-20C)uRI
FigA - Tvpical waveforms for COS/MaS phase-locked loop
employing phase comparator II in locked condition.
539
CD4046A Types
ELECTRICAL CHARACTERISTICS at T A = 2So C
Limits
Test Conditions
Characteristic
Vo
Volu
VOO'
Volts
All Package Types
Uniu
D,E,F,H
Typ.
Min.
Max.
veo Section
Operating Supply Voltage
VOO-VSS
I
As fixed oscillator only
Phase-lock-loop operation
fa = 10 kHz
Operating Power
Dissipation,
Po
Maximum Operating
f max
Frequency.
R2=~
Rl =1 MSl
VOO
VeOIN=-2-
Rl = lOkSl
R2 =~
Cl=100pF
VCOIN = VOO
Cl = 50 pF
3
15
5
15
10
15
5
-
2400
0.25
0.5
10
0.6
1.2
15
-
1.5
5
70
600
-
V
"W
MHz
Center Frequency (fo) and
Frequency Range,
fmax-fmin
Linearity
Temperature-F requency
Stability·:
Programmable with external components R 1, R2, and Cl
See Design Information
High Level,
VOH
%/OCex_1_
f.VOO
Oriving COS/MOS·Type
Load (e.g. Term 3
;---
veo Output Transition
Vo
Volts
tTHL,lTLH
veo Output Drive
ION
p·Channel (Soureel,loP
Source-Follower Output
(Demodulated Outputl:
Offset Voltage
(VCOIN-VDEMI
Linearity
-
0.06-0.12
0.05-0.1
-
15
-
0.03-0.06
-
5,10,15
-
10 12
-
5.10,15
-
-
0.01
.
Phase Comparator Input)
Current:
n·Channel (Sinkl,
5
10
R2=~
VCO Output Duty Cycle
Times,
0.oi5-0.0
5
1%/ocex-f·VOO
RI
VOL
-
15
VCO Output Voltage
(Term 41
Low Level,
15
=7.5V±5V,Rl = I MSl
Input Resistance of
VCOIN (Term 9),
-
0.12-0.24
10
10
fMIN = 0
fMIN*O
1
5
= 5 V ± 2.5 V, Rl > 400 kSl
No Frequency Offset
Frequency Offset
-
VCOIN = 2.5 V ± 0.3 V, Rl > 10 kSl
II
1
0.04-0.08
-
5
4.99
-
-
10
9.99
-
-
%
%/oC
Sl
V
15
14.99
-
-
,
5,10.15
-
50
-
%
5
-
75
150
10
-
50
100
15
ns
40
0.5
0.5
5
0.43
10
1.3
0.86
2.6
-
4.5
5
-0.3
-0.6
-
9.5
10
-0.9
-1.8
-
5,10
-
1.5
2.2
15
-
1.5
-
-
0.1
-
%
RS> 10 kSl
RS>50kSl
1
VCOIN = 2.510.3 V
. = 5±2.5 V
= 7.5±5 V
5
10
15
'.
0.6
rnA
V
0.8
Zener Diode Voltage (V zl
1Z = 50 "A
4.5
5.2
6.1
V
Zener Dynamic
Resistance,
1Z= 1 rnA
-
100
-
Sl
•
..
RZ
.
.
Positive coefficient .
540
Moreover the signal at the "phase pulses"
output is a high level which can be used for
indicating a locked condition. Thus, for
phase comparator II, no phase difference
exists between signal and comparator input
over the full veo frequency range. More·
over, the power dissipation due to the low·
pass filter is reduced when this type of phase
comparator is used because both the p- and
n·type output drivers are OFF for most of
the signal input cycle, It should be noted
that the PLL lock range for this type of phase
comparator is equal to the capture range,
independent of the low-pass filter. With no
signal present at the signal input, the veo
is adjusted to its lowest frequency for phase
comparator II. Fig, 4 shows typical wave·
forms for a GOS/MOS PLL employing phase
comparator II in a locked condition.
CD4046A Types
10k.l1';;;Rl,R2,RS';;;1 M.I1
Cl ;;. 100 pF at VOO;;' 5 V;
Cl;;'50pFatVOO;;' lOV
DESIGN INFORMATION
This information is a guide for approximating
the values of external components for the
C04046A in a Phase-Locked-Loop system.
The selected external components must be
within the following ranges:
Characteristics
....SIENT TEMPERATURE ITA \·25·C
'MAl WHEN VCOIN'VDD,INHIBIT'\lSS
ININ WHENVCO IN 'YS5
In addition to the given design information
refer to Fig.5 for R l, R2, and Cl component
selections.
Phase
Comparator
Used
Deiign Information
VCO WITHOUT OFFSET
veo WITH OFFSET
R2=~
veo Frequency
,.,t1[
fa
1
--
Fig.5Ic) - Typical fmaxlfmin vs R2IRI.
'E
'WI
,12fl
rMIN
VODI2 YDO
yeo INPUT VOLTAGE
-
I
I
yeo
-
ZIl-
VDD
""0"
INPUT VOLTAOE
92eS-ZOO'ZItl
2
For No Signal ISlput
Frequency Lock
Same as for No.1
1
VCO will adjust to ceMer frequency. fa
2
VCO will adjust to lowest operating frequency, fmin
1
Range. 2 fL
2
2 fL = full VCO frequency range
4
e 10 1
6
2 fL = fmax-fmin
.,
Same as for No.1
,.
1
t
Loop Filter
Component
Selection
81()3
Fig,6(a) - Typical VCO power dissipation at center
frequency vs R 1•
OUT
(11. (2)
~
,. .,
Frequency Capture
Range. 2 fC
6
Z
AI-Kn
l~
2 fC "'"; -;;-
AMBIENT TEMPERATURE ITA1~25'C
.... CO I"'·Y55
OUT
For 2 fC, see Ref. (2)
lCl'50PF
",
",
~C2
50 pF
92CS-21901
Phase Angle Between
1
Signal and Comparator
2
,0'
,
50 pF
",
fC = fL
2
900
at center frequency (fa) approximating
and 1800 at ends of lock range (2 fL)
A Iways 00 in lock
00
&
BI01
R2.-~n
TYPICAL CENTER FREQUENCY
Fig.6(bJ - Typical VCO power dissipation at
'min vs R2.
UNIT-TO-UNIT VARIATION
.611'0-%
AMBIE"T TEMPERATURE IT A \. 25·C
VCOI"'\lOO'2, AI·R2·CI)
-,.,.....,.+--'"''""""-''O.,c-+ - - - - - 1
veo
Fig.5(a) - Typical center frequency Vi CI for
RI = 10 kn, and 1 Mn and fa --1/RI CI.
TIMING CAPACITOR
ICtl-~F
Fig.5(bJ - Typical frequency offset vs Cl for
R2 = 10 kn, 100 kn, and 1 Mn.
NOTE: Lower frequency values are obtainable if larger values of C1
than shown in Figs. 5(a) and 51b) are used.
Fig.6(c) - Typical source follower power dissipation
vs RS.
NOTE: To obtain approximate total power dissipation of PLL system for no-signal input
Po ITotall = Po Ifol + Po If MIN) + Po IRS) - Phase Comparator [
Po (Total) = Po (fMIN) - Phase Comparator II
541
CD4046A Types
DESIGN INFORMATION (Cont'd):
PM.
Cheracterlstlcs
Comparator
U.d
Driign Information
Locks On Harmonic 01
Center Frequency
1
Yes
2
No
Signal Input
Noise Rejection
1
2
High
Low
VCO WITHOUT OFFSET
VCO WITH OFFSET
R2=~
- Given: 10
- Use 10 with Fig.5a to
determine R 1 and C 1
- Given: 10 and IL
- Calculate fmin Irom
the equation
Imin = lo-IL
- Use Imin with Fig.5b
to determine R2 and C1
f max
- Calculate Imin
1
Irom the equation
Imax lo.j. IL
Imin =10 - IL
Imax
.
- Use fmin with
VCO
Component
Selection
Fig.5c to determine
ratio R 2/R 1 to obtain
R1
2
- Given: Imax
- Calculate 10 Irom
the equation
Imax
10 =-2-
- Given: 1m in & Imax
- Use Imin with Fig.5b
to determine R2 and C1
_ Calculate Imax
Imin
-Use 10 with F ig.5a to
determine R I and C1
Imax.
.
- Use Imin wIth Flg.5c
to determine
ratio R2/R 1 to
obtain RI
For further inlormation, see
(1) F. Gardner, "Phase·Lock Techniques" John Wiley and Sons, New York, 1966
(2) G. S. Moschytz, "Miniaturized RC Filters Using Phase·Locked Loop", BSTJ, May, 1965.
AM81ENT
~•
11.8
~
I.'
0
::: 1.4
112 f--
TEMP£ftATUft~ 1T~1 •• 2~·C _.1
,.,.
1..1.
..N81Et.IT TEMPERATURE !T.. }a25·C
VOO'IOV • VCOIN'5V!2.!lV • "2'CI)
SUPPLY VOlTAGE VOO.5V, '0-250 KHz
I
/
l,o~J ,", !
/ V
f
.lI
15V.IO~"O~HI
.
I.t:----+----jf--"""d>-"'-"'~
'/
I
-
I
I
,
f>
'1000
PEAl( -TO-PEAK SIGNAL INPUT VOlTAGE IVl1-mv
.I .
'0
68 10
________________________
2
'"
"102 2
"
.. 8'0'
ttl-KQ
Fig.7 - Typical lock range vs signal input amplitude.
~2
t~.==':i"'='
~lINU.RIT'f. fO-~17.5~1
Fig.S(al and (bl - Typical VCO linaa,ity ". R 7 and C7.
~
________________________
~
______________
CD404 7 A Types
COS/MOS Low-Power
Monostable/ Astable
Multivibrator
The RCA-CD4047 A consists of a gatable
astable multivibrator with logic techniques
incorporated to permit positive or negative
edge-triggered monostable multivibrator
action with retriggering and external counting options_
Inputs include +TRIGGER, -TRIGGER,
ASTABLE, ASTABLE, RETRIGGER, and
EXTERNAL RESET. Buffered outputs are
Q, Q, and OSCILLATOR. In all modes of
operation an external capacitor must be connected between C-Timing and RC-Common
terminals, and an external resistor must be
connected between the R-Timing and RCCommon terminals.
Astable operation is enabled by a high level
on the ASTABLE input. The period of the
square wave at the Q and Q Outputs in this
mode of operation is a function of the external components employed. "True" input
pulses on the ASTABLE input or "Complement" pulses on the ASTABLE input
allow the circuit to be used as a gatable
multivibrator. The OSCILLATOR output
period will be half of the Q terminal output
in the astable mode. However, a 50% duty
cycle is not guaranteed at this output.
In the monostable mode, positive-edge
triggering is accomplished by application of
a leading-edge pulse to the +TRIGGER
input and a low level to the -TRIGGER
input. For negative-edge triggering, a trailingedge pulse is applied to the -TRIGGER and
a high level is applied to the +TRIGGER.
Input pulses may be of any duration relative
to the output pulse. The multivibrator can
be retriggered (on the leading edge only) by
applying a common pulse to both the
RETRIGGER and +TRIGGER inputs. In
this mode the output pulse remains high as
long as the input pulse period is shorter than
the period determined by the RC components.
An external countdown option can be implemented by coupling "Q" to an external
"N" counter and resetting the counter with
the trigger pulse. The counter output pulse is
fed back to the ASTAB LE input and has a
duration equal to N times the period of the
multivibrator.
A high level on the EXTERNAL RESET
input assures no output pulse during an
"ON" power condition. This input can also
be activated to terminate the output pulse at
any time. In the monostable mode, a highlevel or power-on reset pulse, must be
applied to the EXTERNAL RESET whenever VDD is applied.
These types are supplied in 14-lead hermetic
dual-in-line ceramic packages (D and F
suffixes), 14-lead dual-in-line plastic package (E suffix), 14-lead ceramic flat package
(K suffix), and in chip form (H suffix).
Features:
•
Low power consumption: special
COS/MOS oscillator configuration
• Monostable (one-shot) or astable
(free-running) operation
• True and complemented buffered
outputs
• Only one external Rand C required
• Quiescent current specified to 15 V
• Maximum input leakage current of
1 p.A at 15 V (full package-temperature
range)
• 1-V noise margin (full package-temperature range)
.
Monostable Multivibrator Features:
• Positive- or negative-edge trigger
• Output pulse width independent of
trigger pulse duration
• Retriggerable option for pulse width
expansion
• Long pulse widths possible using small
RC components by means of external
counter provision
• Fast recovery time essentially independent
of pulse width
.
• Pulse-width accuracy maintained at duty
cycles approaching 100%
CD4047A
Terminal Diagram
Astable Multivibrator Features:
• Free-running or gatable operating modes
• 50% duty cycle
• Oscillator output available
• Good astable frequency stability:
Frequency deviation:
=±2% + 0.03%/o C @ 100 kHz
=±o.5% + 0.015%/oC @ 10 kHz
(circuits "trimmed" to frequency
VDD = 10 V ± 10%)
Applications:
Digital equipment where 'Iow-power dissipation andlor high noise immunity are primary
design requirements:
• Envelope detection
• Frequency multiplication
• Frequency division
• Frequency discriminators
• Timing circuits
• Time-delay applications
92CS-20026R2
Fig. 1 - r:;04047A logic block diagram.
MAXIMUM RATINGS, Absolute-Maximum Values:
STORAGE-TEMPERATURE RANGE (Tstg ) . • • • • . • • . . . . • . . • . . • • . . . . • • . . .-65 to +150 oC
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPES D. F. H
• • . • . . • • . • . . • . . . . . . . . • • . • . • • . • • • . • .-55to+1250C
PACKAGE TYPE E
. • • . • . • . • . • . . . • . • . . . . • • • . • : •••..••••••. -40 to +85 0C
DC SUPPLY-VOLTAGE RANGE. (VDD)
(Voltages referenced to VSS TerminaJ): . . • • . • • • • . • . . . . • . • . . • . . . . . • . . . -0.5 to +15 V
POWER DISSIPATION PER PACKAGE (PO)
FOR TA= -40 to +60 oC (PACKAGE TYPE E)
. . • • • . • . . • • • • • • . • • . . . . . . . . . . 500 mW
FOR TA= +60 to +8SoC (PACKAGE TYPE E I
. . . • . • . . • Derate Linearly at 12 mW/oC to 200 mW
FOR TA= -55 to +100 oC (PACKAGE TYPES D. F) . . . . . • . • . . . . • . • . • . . • • • . . . 500 mW
FOR TA= +100 to +125 0C (PACKAGE TYPES D. F)
. . . . . Derate Linearly at 12 mWtC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA= FULL PACKAGE-TEMPERATURE RANGE (ALL PACKAGE TYPES) . . . • . • . • • 100 mW
INPUT VOLTAGE RANGE, ALL INPUTS . • . . . • • . • . . • • • . • • . • . • . . • • • -0.5 to VDD +0.5 V
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ±1132 inch (1.59 ±0.79 mm) from case for 10 s max • . . . . . . . . . • . . . . . +265 0C
543
CD4047 A Types
RECOMMENDED OPERATING CONDITIONS at TA= 25°C, Except as Noted.
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges:
TEMPERATURE ITAI~2~·C
TEMPERATURE COEfFICIENT AT ALL VALUES
OF VG5·- 0 •3
i !'.T'b'"~CAL
~ ~
E
~ 40
D,F,H
Packages
VDD
Supply·Voltage Range (For TA=Full
Package· Temperature Range)
UNITS
E
Package
z
Max.
Min.
Max.
3
12
3
12
V
Ihput Pulse Width, tw
(Any Input)
5
10
1000
400
-
1300
600
-
ns
Trigger, Retrigger
Rise or Fall Time, tr ' tf
5
10
-
15
5
-
15
5
J.IS
-
:U
GATE-lO-SOURCE VOLTAGE !VGS.- 15 V
!30
Min.
-
,.,,'"C
~~
LIMITS
CHARACTERISTIC
10
.,
ORAIN-TO-SOURCE VOLTAGE 1VOS1-V
Fig. 2 - Typical output n-channel drain
characteristics for Q and 0" buffers.
AMBIENT TEMPERATUREITAJ'l!5'C
~
.
' .
TYPICAL TEMPERATURE COEFFICIENT AT ALL VALUES
''-+---+--+--\-1
11--,T,';1,v',,-'i'k0"~-·±:;
1=-1
~
-,--"L
ro~
Typ: VTR = 0.5 VOO tM = 2.48 RC
Min: VTR = 0.33 VCC tM =2.71 RC
Max. VTR = 0.67 VOC tM =2.48 RC
10
10. 4
!>
SUPPI.l' \IOLTAGE IVool-V
Fig. 24 - Typical
a· and If:pulse·width
Fig. 25 - Typical
{tM~ lOOms!.
'0'
a· and lJ pulse·width
value indicated.
MONOSTAlL.! MODE
MQHOSTABLE MODE
Note:
In the astable mode, the first positive half
cycle has a duration of TM; succeeding
durations are tA/2.
(AIIOo,.s.:!tIMSlml
"00'5,10'1
;
0·2
(BIIM:!'Oms
VDO':i,IOV
o
TeA
,.,
In addition to variations from unit to unit,
the monostable pulse width may vary as a
function of frequency with respect to VDO
and temperature. These variations are
presented in graphical form in Fig. 22 to 27
with 10 V as reference for voltage·variation
curves and 25°C as reference for temper·
ature·variation curves.
10'
accuracy vs Q and Qpulse width
for a variation of ± 10% from
accuracy VI supply 1I0ltage
Thus if ItM - 2.48 RC I is used, the maximum
variation will be (+9.3%, -0.0%).
10°
10'3
10- 2
10 I
OANDa-PULSE WIOTH--SECONDS
9ZCS-21430
+5
+25
It.
1~
a
60
+45
AMBIENT TEMPERATURE ITAI--C
Fig. 26 - Typical a and 0 pulse·width
accuracy
liS
Voo
IIF Kti
V
100 47 510
100 220 5,10
temperature
I
o
-55
·35
-15
+5
+25
+045
+65
+85
+105
+125
AMBIENT TEMPERATlJAE {TAI--C
Fig. 27 - Typical
Q
and Q pulse· width
accuracy range VI temperature.
(high frequBncy).
547
CD404 7 A Types
III. Retrigger Mode Operation
The C04047A can be used in the
retrigger mode to extend the outputpulse duration, or to compare the frequency of an input signal with that of
the internal oscillator. In the retrigger
mode the input pulse is applied to
terminals Band 12, and the output is
taken from terminal 10 or 11. As shown
in Fig. 2B, normal monostable action is
obtained when one retrigger pulse is
applied. Extended pulse duration is
obtained when more than one pulse is
applied. For two input pulses, tRE=tl'
+ tl + 2t2' For more than two pulses,
tRE (Q OUTPUT), terminates at some
variable time, to, after the termination
of the last retrigger pulse, to is variable
because tRE (Q OUTPUT) terminates
after the second positive edge of the
oscillator output appears at flip-flop 4
(see Fig. B).
IV. External Counter Option
Time tM can be extended by any amount with the use of external counting
circuitry. Advantages include digitally
controlled pulse duration, small timing
capacitors for long time periods, and
extremely fast recovery time. A typical
implementation is shown in Fig. 29.
The pulse duration at the output is
text = (N-l) (tA) + (tM + tA/2)
where t ext= pulse duration of the circuitry, and N is the number of counts
used.
V. Timing-Component Limitations
The capacitor used in the circuit should
be non-polarized and have low leakage(Le.
the parallel resistance of the capacitor
should be an order of magnitude greater.
than the external resistor used). There is
no upper or lower limit for either R or C
value to maintain oscillation.
However, in consideration of accuracy, C
must be much larger than the inherent
stray capacitance in the system (unless
this capacitance can be measured and
taken into account). R must be much
larger than the COS/MOS "ON" resistance in series with it, which typically is
hundreds of ohms. In addition, with
very large values of R, some short-term
instability with respect to time may be
noted.
The recommended values for these
components to maintain agreement with
previously calculated formulas without
trimming should be:
VI. Power Consumption
In the standby mode (Monostable or
Astable), power dissipation will be a
function of leakage current in the
circuit, as shown in the static electrical
characteristics. For dynamic operation,
the power needed to charge the external
tim ing capacitor C is given by the
following formulae:
10
ASTABLE MODE
SUPPLY VOLTAGE IVool-,1I
10"-1=--+--+--+-+-+--+---1
Astable Mode: P = 2CV 2f. (Output at
terminal No. 13)
P = 4CV 2f. (Output at
terminal Nos. 10 and 11)
10'
100
..:..10'
10 2
10 3
IO~
10'
Q OR Q FREQUENCY If 1 - HE
10'
Fig. 30 - Power dissipation va output
frequency IVDD = 5 Vi.
Monostable Mode:
(2.9CV 2 ) (Duty Cycle)
p =
T
10
ASTABLE MODE
SUPPLY VOLTAGE IVOO'-IOII
• IO'-I=--+--+--+-+--t--+--;
(Output at terminal
Nos. 10 and 11)
~
.
-I~'t--+--+--t--+--+~
~
~
~
,
10
;;
The circuit is designed so that most of
the total power is consumed in the
external components. In practice, the
lower the values of frequency and
voltage used, the closer the actual power
dissipation will be to the calculated
value.
Because the power dissipation does not
depend on R, a design for minimum
power dissipation would be a small
value of C. The value of R would
depend on the desired period (within
the limitations discussed above). See
Figs. 30-32 for typical power consumption in astable mode.
~
~lo21~~4-_~_~~-+--i-~r-~
10'
10'
10'
Fig~
10'
31 - Power diSSipation VS' output
frequency IVDD = 10 Vi.
~102'ic-~--t--+--i-~--r--L-~10~'~~1~~~_~1~0'~~10'~~10~'~~10~·~~'0r.'~~1~
92CS-200'30R2
OOR Q FREQUENCY UI-HI
UCS-21414
Fig. 32 - Power dissipation", output
Fig. 28 - Implementation of external
frequency IV DD = 15 Vi.
counter option.
JUUl:::==.-.1l.
7~
C ~ 100 pF, up to any practical value, for
astable modes;
C ~ 1000 pF, up to any practical value
for monostable modes.
92Cs-tOOH
Fig. 29 '- Retrigger-mode waveform ••
M8 ________________________
~
_________________________________
CD4048A Types
COS/MaS Multi-Function
Expandable 8-lnput Gate
The RCA- CD4048A is an 8-input gate
having four control inputs_ Three binary
control inputs - Ka, Kb, and Kc - provide
the implementation of eight different logic
functions_ These functions are OR, NOR,
AND, NAND, OR/AND, OR/NAND, AND/
OR, and AND/NOR.
an open circuit. This feature enables the
user to connect this device to a common
bus line.
These types are supplied in 16-lead hermetic
dual-in-line ceramic packages (D and F
suffixes), 16-lead dual-in-line plastic package (E suffix), 16-lead ceramic flat package
(K suffix), and in chip form (H suffix).
BINARY CONJROL. INPUTS
'FUNCTION CONTROL
In addition to the eight input lines, an
EXPAND input is provided that permits the
user to increase the number of inputs to one
CD4048A, (see Fig. 6). For example, two
CD4048A's can be cascaded to provide a
16-input multifunction gate. When the
EXPAND input is not used, it should be
connected to VSS.
A fourth control input -Kd - provides the
user with 3-state outputs. When control
input Kd is high the output is either a logic
1 or a logic 0 depending on the input states.
When control input Kd is low, the output is
i ~c KV
--Kia
1'-'.
b
10 7
9
3·STATE
CONTROL
2
INPUTS B - 13
C-12
D-II
EXPANO- .5
I
1'G-.-6
OU~PUT
INPUTS F - 5
H-'
VSS'8
MAXIMUM RATINGS, Absolute-Maximum Values:
"100- 16
92CS-22249
STORAGE-TEMPERATURE RANGE (Tstg ) • • • • • • . . • • . • • • • • • • . . • . • • • . . . .-65 to +150 oC
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPES 0, F, H
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55 to +125 C
PACKAGE TYPE E
" • • • • • • • • • • • • . • . . • • • • . • • • • • . . • . . • . • . . . -40 to +85 0 C
CD4048A
Functional Diagram
°
DC SUPPLY-VOLTAGE RANGE, (VDD)
(Voltages referenced to VSS Terminal): . • . • • . • . . . • . • . . . . . . • . . . . . . . . . . -0.5 to +15 V
POWER DISSIPATION PER PACKAGE (PO)
FOR TA=-40to+60oC (PACKAGE TYPE E) . . • • • • • . • . • . . • . • . . • . . • • . . . • . 500mW
FOR TA= +60 to +85 0 C (PACKAGE TYPE E)
. . • • • . • • . Derate Linearly at 12 mWloC to 200 mW
FOR TA= -55 to +100oC (PACKAGE TYPES 0, F)
. • . . • . • • . . • • • . • . . . • . . • . . • 500 mW
FOR TA= +100 to +1250 C (PACKAGE TYPES 0, F) ..•..•• Derate Linearly at 12 mWloC to 200 mW
DEVICE DISSIPA nON PER OUTPUT TRANSISTOR
FOR TA= FULL PACKAGE·TEMPERATURE RANGE (ALL PACKAGE TYPES) . • . • • • . . • 100 mW
INPUT VOLTAGE RANGE. ALL INPUTS . • • • • • • • • • • • • • • . . . • • • . • . . • -0.5 to VDO +0.5 V
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1116 ±1/32 inch (1.59 ±0.79 mm) from case for 10 s max . . . . • • . . . . . . . . . . +265 0 C
NOR
OR
A~ A~
C
E
C
D
F
D
E F
G H
EX'
G H
EX.
A!?-
AND
NAND
.
C
E
G
A~
C 0
E F
0
F
H
OR/NAND
• Medium-power TTL drive capability
• Three-state output
• High current source and sink capability
9 mA (typ_) @ VDS =0.5 V. VDO =10 V
• Many logic functions available in one
package
• Quiescent current specified to 15 V
• Maximum input leakage current of 1 jJA
at 15 V (full package-temperature range)
• 1-V noise m.argin (full packagetemperature range)
•
G H
EX.
EX'
ORlAND
Features:
AND/OR
AND/NOR
~~~;~;~
Applications:
• Selection of up to 8 logic functions
• Digital control of logic
• General-purpose gating logic
Decoding
- Encoding
Fig. 1 - Basic logic configurations.
M81ENT TEMPERATURE ITAl-25-C
TYPICAL TEMP. COEFFICIENT AT ALL VALUES OF
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges:
"'GS--Q~
GATE-TO-SOURCE VOLTAGE (Vasl-15V
LIMITS
10V
CHARACTERISTIC
V::>D
(V)
D,F,H
Packages
E
Package
UNITS
d
~ 40
~
:. 20
Min.
Max. Min_ Max.
,v
5
Supply-Voltage Range (For TA = Full
Package-Temperature Range)
10
15
DRAIN-TO-SOURCE" VOLTAGE IVDSJ-V
3
12
3
12
V
Fig. 2- Typ!cal output n-channel drain
characteristics.
549
CD4048A Types
AMBIENT TEMPERATURE ITAI 0 2S·C
STATIC ELECTRICAL CHARACTERISTICS
TYPICAL TEMP. COEFFICIENT AT ALL. ....LUES OF
""o·o., ..tee
C:D4041 ...0, AI(
CD4048AE
Limits at Indicated Temperatures (oC)
Conditions
GATE-lO-SOURCE VOl.TAGE IVas}-'5'"
D,F,H Packages
E
Package
Characteristic
Va
(V)
Quiescent Device
Current I L Max.
-
VIN Vee -5
(V) (V)
-
-
-
-
+25
1 p.005
10
2
15
25
+85
10
0.01
1
60
0.01
2
120 20 0.02
0.5
25 1000 250 2.5
..v
.0
Typ. Limit
Typ. Limit
5
40
Units
+25
125 -40
,ov
20
10
140
20
280
,0
JJA
250 2500
....,
,ov
.
DRAIN-YO-SOURCE VOLTAGE '\'o51-
Y
ttes-tU:MIIII
Fig. 3- Minimum output n-channel drain
Output Voltage:
Low Level,
VOL
High Level
VOH
-
5
5
o Typ.; 0.05 Max.
10
10
o Typ.; 0.05 Max.
0
5
4.95 Min.; 5 Typ.
-
0
10
9.95 Min.; 10 Typ.
characteristics
DRAIN-lO-SOURCE VOLTAGE 1Yosl-V
-IS
-10
-,
-.v
V
1
I
-40
-IOV
ii:
H
Noise Immunity:
Inputs Low,
VNL
-60 -
4.2
-
5
1.5 Min.; 2.25 Typ.
9
-
10
3 Min.; 4.5 Typ.
§
80
V
Inputs High
VNH
Noise Margin:
Inputs Low,
VNML
Inputs High,
VNMH
-
5
1.5 Min.; 2.25 Typ.
1
10
3 Min.; 4.5 Typ.
4.5
-
5
1 Min.
9
-
10
1 Min.
0.5
-
5
1 Min.
1
-
10
1 Min.
-
4.5
2
3.2
1.6
1.1
1.9
3.2
'1.6
1.3
-
10
5.6
9
4.5
3.1
5.4
9
4.5
3.7
0.8
•
z
_ _-'00:
~ TEMPERATURE IT... '.25·C
TYPICAL TEMP. COEFFlCfENT AT ALL. VALUES Of' y;;;; - 0.3 -,.t-c
V
DRAIN-to-SOURCE VOLTAGE lVosl-v
-10
.
-.v
AMB'ENT TEMPERATURE ITAI-25-C
TYPICAL TEMP. COEFFICIENT AT ALl.
VAWES OF VGS.-o.3
1
%/-e
I
;:
~
-'OY
GATE-TO-SOURCE VOLTAGE IVc;S)--'5V
mA
4.6
9.5
Input Leakage
Current,
IIL,IIH
-
5
CD4048AO,AIC
CD4048AE
-2 -3.2 -1.6 -1.1 -1.9 -3.2 -1.6 -1.3
......
Fig. 5- Minimum output p-channef drain
characteristics.
10 -5.6 -9 -4.5 -3.1 -3.8 -9 -3.15 -2.6
Any Input
-
-
15
3·State Output
Forced
Leakage Current (Output Disabled)
IOL,IOH
- 115
-I
± 10-5 Typ., ± 1 Max.
tJ,A
tJ,A
±10-4 Typ., ±2 Max.
INPUT FREQUENCY ttl) -H,
Fig. 6- Typical power dissipation as a
function of input frequency.
550
.I..
.zc."ao.....i
Fig. 4- Typical output p-channel drain
characteristics.
Output Drive
Current:
0.4
n·ChanneI(Sink)
ION Min.
0.5
p-channel
(Source),
lOP Min.
B
1"
GATE-TO-SDUACE.\IOLTAGE IYos'o-ISIi
CD4048A Types
DYNAMIC ELECTRICAL CHARACTERISTCS at TA
=25°C lind CL =15 pF'and 50 pF.
Typical Temperature Coefficient for all values of VDD = 0.3%fOC
AMalENT TEMPERATURE (T"I·2.5"C
RL = 200
kn
,"'"
TYPICAL TEMP. COEFFICIENT AT ALL VALUES OF VDO"o.3 %./-c
CL=15pF
TEST
CONDITIONS
CHARACTERISTIC
D,F,H
600
E
Package
Packages
UNITS
VDD
(Volts)
5
TYP.
MAX."
TYP.
MAX."
750
1300
750
1600
10
225
400
225
500
Transition Time:
High-to-Low Level tTHL
5
10
90
30
140
50
90
30
170
65
Low-to-H igh Level tTLH
5
10
130
40
250
60
130
40
5
300
75
Propagation Delay Time
tpHL
I nput Capacitance CI
Any Input
SuPPL.'" VOL.TAGE {VDo1·~V
.00
LIMITS
200
ns
ns
Fig. 7- Tvpical propagation delav time as a
function of load capacitance.
ns
pF
5
~
5
10
775
240
1350
430
775
240
1650
530
ns
5
10
105
40
170
70
105
40
200
85
ns
5
10
145
50
280
145
80
50
5
330
95
ns
-
pF
~
LOAO CAPACITANCE (CL!"pF
CL = 50 pF
Propagation Delay Time
tpLH·tpHL
Transition Time:
High-to-Low Level tTHL
Low-to-High Level tTLH
Input Capacitance (;1
Any Input
5
~
I~:
Ii
I!
I
* Max. Limits represent worst-case limits for worst·case modes of operation shown in Figs. 15.16, and 17.
LOAOCAPACITANCEICLI-pF
Fig_ 8- Typicallow-to-high level transition
time as a function of load capacitance.
.....SIENT TEMPERATURE (TAl'HoC
TYPICAL TEMP. COEFFICIENT AT ALL. VALUES OF VOO"o.3
"1./-c.
INPUTS
D
Vss
~
INPUTQVOO
OOITPUTS
.50
VOO-VNH
~ rOo
'--
~
~
v~
,Oy
"V
NOTE:
TEST ANY ONE INPUT,
WITH OTHER INPUTS AT
ll<100
"00 OR Vss
"SS
n~s-
LQAD CAPACITANCE 1Cll-pF
Fig. 10- Quiescent-dellice-current
Fig. 9- Typical high-to-Iow level transition
time as a function of load capacitance.
Fig. 11-
test circui~.
Noise-immunity
test circuit.
Voo
,.
Voo
.
1NPOUS
voo
NOTEo
~
V55
,.
~:~~~:i,!~~:rs
"
TO BOTH VDO AND Vss'
CONNECT ALL UNUSED
10
INPUTS TO EITHER
Voo OR "'ss'
INPUT~50".
I>
INPUT
O U T P U T H - ---90%
-
- --
12
'THL
--10%
'TLH
92CS-22265
9
V55
Fig. 12- Input-/eakage-current
test circuit.
Fig_ 13- tTHL' tTLif - ANO/NOR.
551
CD4048A Types
VDD
VDD
NOR
"~
.
OUTPUT _......... I
I' •• "'"
13
"
"..
j
I
INPUT
"
I>
"II
Ka-Kb-Kc:
0-0-0
10
•
12-INPUT ORlAND GATE
\Is.
J -I A+B+C+O)'( EH+G+H)· IXI+X2+X!i+X4J
AND
. Fig. 14(B} . 12·;nput ORlAND gate.
INP\lT~""
OUTPUT~%
OR FUNCTION
9ICS-ZIZ63
Fig. 15- tpLH - NAND.
OR
Vss
Vss
V55
16-INPUT NOR GATE
9ZCS-ZOZ41
~~-.....~,
Fig. 14(b} 16·input NOR gate.
Applications of Expand Input
NAND
AND/OR
FUNCTION
NEEDED AT
EXPAND INPUT
".•. ~
"I>
10
•
OUTPUT BOOLEAN
EXPRESSION
NOR
OR
J-(A+B+C+D+E+F+G+H)+(EXP)
OR
OR
J=(A+B+C+D+E+F+G+H)+(EXP)
AND
NAND
J=(ABCDEFGHHEXP)
NAND
NAND
J=(ABCDEFGH)·(m)
OR/AND
NOR
J=(A+B+C+D)'(E+F+G+H)'(EXP)
INPUT
"II
IMPLEMENTATION OF EXPAND INPUT FOR 9 OR MORE INPUTS
OUTPUT
FUNCTION
.
Vs.
INPUT~O'"
OUTPUT
~50%
-.J~A1L~ ~
9ZC5--22264
OR/NAND
NOR
J=(A+B+C+D)'(E+F+G+H)'(~)
AND/NOR
AND
J-(ABCO)+(EFGH)+(EXP)
AND/OR
AND
J=(ABCD)+(EFGH)+(EXP)
Fig. 16- tpHL - AND.
Note: IEXP) designates the EXPAND function 0 .•. , X1+X2+ ... XNI.
OR/NAND
AND/NOR
OR/AND
92CS-ZlIIiZ
Fig. 14(c) . ActuBI·cltfuit logic configurations.
Fig. 14- Expansion logic and truth reble.
552 __________________________________________________________________
CD4048A Types
K.
r--------B--.
C
I
3 CONFIGURATIONS
SAME AS FOR INPUT "A N
D~ _ _ _ _ _ _ _
..
'--"4~
-.J
VDD
EXP--~VVv-~~------------~------i
Kb
Vss
E-;--------~H--L
----, ________
~M~O::I:~RR:';~~~~A" _
,~
~-
Vss
gKb
Kb--r--------~b
---1
Kc
Kd---l
L
3 CONFIGURATIONS
SAME AS FOR "K~' INPUT
Kc
~~c
_ _ _ _ - - - --..J---L::::~:
Transmission Gata Definition
TG
=
Transmission Gate
Input to Output is:
a) A"bidirectionallow impedance when
control input 1 is low and control
2 is high.
b) An open circuit when control input 1
is high and control input 2 is low.
9ZCM-222~IRI
FUNCTION TRUTH TABLE
OUTPUT
UNUSED
BOOLEAN EXPRESSION Ka Kb Kc
INPUT*
FUNCTION
NOR
OR
J=A+B+C+D+E+F+G+H
J=A+B+C+D+E+F+G+H
ORlAND
J=(A+B+C+D}o(E+F+G+H)
OR/NAND J=(A+B+C+D)-(E+F+G+H)
AND
J=ABCDEFGH
NAND
J-.A,BCDEFGH
AND/NOR J-ABCD+EFGH
AND/OR
J=ABCD+EFGH
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
Kd=l Normal Inverter Action
Kd=O High Impedance Output
EXPAND Input=O
*See Figs. 1 and 7.
Fig. 17- logic diagram and truth table.
553
CD4049A, CD4050A Types
COS/MOS Hex Buffer/Converters
RECOMMENDED OPERATING CONDITIONS at TA=25 0 e, Except as Noted.
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges:
CD4049A-lnverting Type
CD4050A-Non-lnverting Type
The CD4049A and CD4050A are inverting
and non-inverting hex buffers, respectively,
and feature logic-level conversion using only
one supply voltage (Vcd- The input-signal
high level (VIH) can exceed the VCC supply
voltage when these devices are used for logiclevel conversions_ These devices are intended
for use as COS/MOS to DTL/TTL converters
and can drive directly two .DTL/TTL loads_
(VCC=5V, VOL;;'Oo4V,imd IDN;;'3_2mA.)
The CD4049A and CD4050A are designated
as replacements for CD4009A and CD4010A,
respectively. Because the CD4049A and
CD4050A require only one power supply,
they are preferred over the eD4009A and
CD4010A and should be used in place of the
CD4009A and CD4010A in all inverter, current driver, or logic-level conversion applications. In these appli.cations the CD4049A
and CD4050A are pin compatible with the
CD4009A and CD4010A respectively, and
can be substituted for these devices in
existing as well as in new designs. Terminal
No. 16 is not connected internally on the
CD4049A or CD4050A, therefore, connection
to this terminal is of no consequence to circuit operation. For applications not requiring high sink-current or voltage conversion, the CD4069 Hex Inverter is recommended.
These types are supplied in l6-lead hermetic
dual-in-line ceramic packages (D and F
suffixes), l6-lead dual-in-line plastic package (E suffix). l6-lead ceramic flat packages
(K suffix), and in chip form (H suffix).
Features:
•
•
•
•
High sink current for driving 2 TTL loads
High-te-Iow level logic conversion
Quiescerit current specified to 15 V
Maximum input leakage of 1 jJ.A at 15 V
(full package-temperature range)
App/ic;;Jtions:
• COS/MOS to DTL/TTL hex converter
• COS/MOS current "sink" or "source"
driver
• COS/MOS high-to-Iow logic-level
converter
GoA
A
~G~A
B
~H'B
B
e
~
~
A
~
I=e
D~ J·oE
,
K=E
~-
~L"
c~
D~
E~
F~
Vee _,_
Vee _,_
Vss - " -
Vss -"-
Ne =13
Ne -IS
CD4049A
H-B
roc
J=O
K=E
L=F'
Ne =13
Ne =16
CD4050A
Fig. 1 - Functional diagrams.
554
LIMITS
Max.
Min.
CHARACTERISTIC
Supply·Vollage Range (Vec) (For TA=Full Package·
Temperalule Range)
Input VoHage Range (VI)
,
UNITS
3
12
V
Vec
12
V
'The CD4049 and CD4050 have high-to-Iow-Ievel voltage conversion capability but not
low-to-high-Ievel; therefore it is recommended that VI .> Vee-
STATIC ELECTRICAL CHARACTERISTICS
Characteristic
c
Conditions
Vo
(V)
Quiescent
Device
Current,
ILMax.
-
Output
Voltage:
Low-Level,
VOL
High-Level,
-
-
-
VOH
Noise
Immunity:
Inputs Low, 3.6
VIN
(V)
-
Vce
(VI
5
Limits at I~dicated Temperatures (0C)
D.F,H Packages
E Package
-55
+25
+125 -40
+25
Typ. Limit
Typ. Limit
0.3
0.5
10
0.01
0.Q1
0.02
0.3
0.5
10
20
30
100
3
5
50
0.03
0.05
0.05
-
10
15
0,5
0, 10
0, 5
0,10
10
5
10
4.95 Min.; 5 Typ.
9.95 Min.; 10 Typ.
Ii
3
5
50
-
5
1.5 Min.; 2.25 Typ.
-
10
3 Min.; 4.5 Typ.
5
1.5 Min.; 2.25 Typ.
VNH
2.8
All Types
Inputs Low, 3.6
-
10
3 Min.; 4.5 Typ.
-
5
VNL
7.2
-
10
4.5
9
-
5
10
1 Min.
1 Min.
0.5
1
-
-
5
10
1 Min.
1 Min.
4.5
5
10
2.6
3.1
5.2
1.8
2.6
5.2
6
3
2.1
3.6
6
3
16
5.6
9.6
16
8
8
-1
-0.5 -0.35 -0.6 -1
-0.5
-2.5 -1.25 -0.9 -1.5 -2.5 -1.25
-2.5 -1.25 -0.9 -1.5 -2.5 -1.25
15
±10-5 Typ •• ±1 Max .
Iinput
Leakage
. Current,
IIL,IIH
Max.
0.4
0.4
0.5
4.5
2.5
9.5
-
-
-
-
Any Input
3.3
3.75
10
5 -0.62
5 -1.85
10 -1.85
42
70
500
o Typ.; 0.05 Max.
o Typ.; 0.05 Max.
VNL
7.2
CD4050A
Inputs High, 104
CD4049A
Noise
Margin:
Inputs Low,
VNML Min.
CD4050A
Inputs High,
VNMH Min.
C04050A
Output Drive
Current:
N-Channel
(Sink),
ION Min.
P-Channel
(Source),
lOP Min.
Units
+85
jJ.A
V
V
1 Min.; 1.5 Typ.
2 Min.; 3 Typ.
V
2.1
2.5
6.6
-0.4
-1
-1
mA
jJ.A
CD4049A, CD4050A Types
MAXIMUM RATINGS, Absolute·Maximum Values:
AMBIENT TEMPERATURE IT,,)-25·C
SUPPLY VOLTAGE (Vcc'.5 V
STORAGE·TEMPERATURE RANGE ITstgl
OPERATING· TEMPERATURE RANGE (TAl:
PACKAGE TYPES D. F. H
PACKAGE TYPE E
DCSUPPLY·VOLTAGE RANGE. (V CC)
IVoltages referenced to VSS Terminall ............................. ··.······
-55 to +12SoC
-40 to +BSoC
>
I •
?
-0.5 to +15 V
POWER DISSIPATION PER PACKAGE (POl:
FOR TAo -40 to +60 0 C (PACKAGE TYPE E I
SOOmW
FOR TAo +60 to +85 0 C (PACKAGE TYPE E I
Derate linearly at 1'2 mW/oC to 200 mW
500 mW
FOR TAo -55 to + 100°C (PACKAGE TYPES D. F·I
FOR TAo +100 to +125 0 C (PACKAGE TYPES D. F)
I
.. Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA FULL PACKAGE·TEMPERATURE RANGE (ALL PACKAGE TYPES)..
100 mW
0
INPUT VOLTAGE RANGE. ALL INPUTS
LEAD TEMPERATURE lOURING SOLDERING).
At distance 1/16 ± 1/32 Inch 11.59 ± 0.79 mm) fram case for lOs max.
-0.5 to V DD +0.5 V
2
3
INPUT VOLTAGE (":II-V
Fig. 2-Minimum and maximum voltage
transfer characteristics for
CD4049A.
AIIIBIENT TEMPERAnJRE ITAI.ZS·C
SUPPLY VOt..TAGE (Vcc'-! V
I
2
3
INPUT VOLTAGE ('1.11-11
INPUT VOLTAGE {".I'-V
Fig. 3-Minimum and maximum voltage
Fig. 4-Minimum and maximum voltage
Fig. 5-Minimum and maximum voltage
transfer characteristics for
transfer characteristics for
transfer characteristics for
CD4050A.
CD4049A.
CD4050A.
DRAIN-TO-SOURCE VOLTAGE 1Vosl-V
VOLTAGE lVII-V
INPUT VOLTAGE lVII-V
.'C,-104.4
nes-to... !
Fig. 6- Tvpical voltage transfer characteristics as a function of tempera-
ture for CD4049A.
Fig. 7- Typical voltage transfer characteristics as a function of tempera-
ture for CD4050A.
Fig. 8- Typical and minimum n-channel drain
characteristics as a function of gate-to-
source voltage IVGS) for CD4049A, CD4050A.
DRAIN-TO-5ClURCE VOLTAGE lVosI-V
Fig.
9- Typical and minimum p-channel drain
characteristics as a function of gate-to-
source voltage IVGS) for CD4049A,
CD4050A.
40
60
aD
I
LOAD CAPACITANCE ICLI-pF
Fig. 10- Typical high-to4ow level propagation delay
time vs. CL for CD4049A.
..
LOAD CAPACITANCE ICL)-pF
Fig. 11- Typical high-to%~~w level propagation delay
time VS. CL for CD4050A.
555
CD4049A, CD4050A Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA=250 C; Input t"tt=20 ns,
Cl=15 pF, Re200 kn
CHARACTERISTIC
Propagation Delay Time:
low-to-High. tpLH
CD4049A
ns
CD4050A
High-to-Low. tPHL
Fig_ 12-Typicallow-to-high level propagation delay
time vs. CL for CD4049A.
CD4049A
ns
CD4050A
Transition Time:
Low-to-High. tTlH
ns
Fig_ 13- Typicallow-to-high level propagation delay
time vs. CL for CD4050A.
92C9-20526
Fig. 15- Typical low-fa-high level transition time
vs_ CL for CD4049A. CD4050A.
Fig. 14- Typical hjgh~to·low Je~J transition time
vs_ CL for CD4049A, CD4050A.
v/
~
1 10'
~ IOliAM!B!"INT!T!'M:'I'RIATUiR'jIITA!"i"!'UI"I"jG.j"!"i"!RI'II
4
'0
I I III
"102
2
4.
I I
'Ib'
2
INPUT FREQUENCY 11.1 k~
4 ' '104
92CS-2OU7
Fig. 16- Typic,,' dissipation charaCteristics for
CD4049A, CD4050A.
101
10'
INPUT RISE AND FALL T'NE It, ,tt I •
10'
'''PUT RISE AND FALL TINE It,.tfl
92CS-204'OR
Fig. 18- Typical pO"".Ier dissipation ~'S. transition
time per inverter CD4050A.
vDO
Fig. 17-Typicalpowerdissipation VS. transition
time per inverter CD4049A.
a
INPUTS
V _y
DD ~H
---
V:L
VDO
OUTPUTS
avDO
INPUTS
4! "--/:"'\.+
Voo
=
-
0 ~
Yss
NOTE
MEASURE INPUTS
SEQUENTIALLY.
v:
INPUTS .--'------,
Vss
Fig. 19-Noise.immunity test circuit.
10)
92C$'20117
TO 10TH VDD AND",
CONNECT ALL UNUSED
...urs TO EITHER
Voo ORVss '
Fig_
.
(bJ Schematic diagram of CD4050A,
6 identical units.
Vss ncs-27402
Fig....20-4nput leakage current test circuit.
22 - (aJSchematic diagram of CD4049A. 1 of
6 identical units_
NOTE:
WITH OTHER INPUTS AT
'tlCS-274DO Yoo ORVss·
Vss
VSS
I.)
TEST ANV ONE INPUT,
Vss
IN
Fig.
1 of
21~uiescent device current test circuit.
556 ____________________________________________________________________
CD4057 A Types
COS/MaS LSI 4-Bit Arithmetic Logic Unit
The RCA-CD4057A is a low-power arithmetic logic unit (AlU) designed for use in lSI
computers_ An arithmetic system of virtually
any size can be constructed by wiring together a number of CD4057 A AlU's_ The
CD4057 A provides 4-bit arithmetic operations, time sharing of data terminals, and full
functional decoding for all control lines_ The
distributed control system of this device
provides great flexibility in system designs
by allowing hard-wired connection of N
units in 4N unique combinations_ Four
control I ines provide 16 instructions which
include Addition, Subtraction, Bidirectional
and Cycle Shifts, Up-Down Counting, AND,
OR, and Exclusive-OR logic operations_
Applications:
RIGHT SERIAL
DATA LINE
• Parallel Arithmetic Units
•
Process Controllers
• Remote Data Sets
• Graphic Display Terminals
FUNCTION
1-<"----'
SELECT -
t
TO
REGISTER
Voo' 26
Vss -25
detected and used to establish a conditional
operation_ Predetermined operation of the
CD4057A on a conditional basis allows
greater ALU flexibility_ Although especially
applicable as a parallel arithmetic unit, the
CD4057A also finds use in virtually any
application requiring one or more of its 16
basic instructions_ The CD4057 A is supplied
in a hermetically sealed 28-lead dual-in-line
ceramic package(CD4057AD).28-lead ceramic flat package (CD4057AK). and in chip
form (CD4057AH).
Two mode control lines allow the CD4057 A
to function as any 4-bit section of a larger
arithmetic unit by controlling the bidirectional serial transfer of data to adjacent
arithmetic arrays_ By means of three "Conditional Control" lines Overflow, All Zeros,
and Negative State conditions may be
MAXIMUM RATINGS, Absolute·Maximum Values:
STORAGE·TEMPERATURE RANGE IT stg )
-65 to +1500 C
OPERATlNG·TEMPERATURE RANGE ITA}'
PACKAGE TYPES O. H
-55 to +125 0 C
POWER DISSIPATION PER PACKAGE IPOI,
FOR T A = .-55 to +IOOuC IPACKAGE TYPES 0 I
500mW
FOR T A = + I 00 to + 125°C IPACKAGE TYPES D)
.. Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE-TEMPERATURE RANGE IALL PACKAGE TYPESI.....
INPUT VOLTAGE RANGE. ALL INPUTS
LEAD TEMPERATURE lOURING SOLDERING},
AI distance 1116 ± 1/32 Inch (1.59 ± 0.79 mmJ from case for 105 max.
100 mW
-0.5 to VOo +0.5 V
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges:
202~'RZ
Features:
•
•
LSI Complexity on a Single Chip
16-lnstruction Capability
-Add, Subtract, Count
:AND, OR, Exclusive-OR
-Right, Left, or Cyclic Shifts
• Bidirectional Data Busses
• Instruction Decoding on Chip
• Fully Static Operation
• Single-Phase Clocking
• Easily Expandable to 8, 12, 16,_
___ Bit Operation
Low Quiescent Device Dissipation __
____ 10 IJW (typ.)
-0.5 to +15 V
(Voltages referenced to VSS Terminal) ........... .
92CS -
Fig. 1 - Block diagram - C04057A.
•
oCSUPPLY·VOLTAGE RANGE. IV Oo }
INPUT/OUTPUT
•
•
Conditional-Operation Controls on Chip
Add Time (Data In-To Sum Out)
=375 ns (typ) at 10V
• Quiescent current specified to 15 V
• Maximum input leakage current of 1 J.IA
at 15 V (full package-temperature rangel
• l-V noise margin (full package-temperature
rangel
tpo 101 - COl'" 3 IpO leI - Col = 790 ns
I
013·16
CHARACTERISTIC
VDD
(V)
Min_
Max.
3
12
5
10
40
20
5
10
4590
1320
Clock Pulse Width, tw
5
10
1200
375
Clock -'nput Frequency, fCl
Count Mode
5
10
0_13
·0.46
5
10
0_33
1.4
-
5
10
-
Supply-Voltage Range (For T A = Full
Package-Temperature Range)
Setup Time, ts
DATA
OPCODE
Shift Mode
Clock Rise or Fall Time, trCl, tfCl
-
15
15
tpo ID[ - Col + 2 tpo leI - Col + tpo leI - Sol = 925
n$
513·16
LIMITS
UNITS
tpo 1°1- COl'" 21PD tel - Col'" 615 os
I
V
D!}.12
tpo
101 -
Co! + tpo leI - Colt tpo leI - Sol .. 750 ns
59-12
tpo (D[ - COl'" tpo lei - Col = 440 os
ns
05-8
IpO IDJ- Col + tpo leI - SOl" 575 ns
S~B
ns
fpO U)r - COl = 265 ns
I
01·4
tpolot-So'- 375nl
51·4
MHz
Vss
92C5-21875
jIS
Fig_ 2- Typical.peedchlUBcteri.ticsofa 16-bitALUat VOO -10 V.
557
CD4057 A, Types
STATIC ELECTRICAL CHARACTERISTICS
Limits at Indicated Temperatures (oC)
CONDITIONS
'CD40S7AD, CD40S7AH
CHARACTER ISTIC
UNITS
-SSoC
12SoC
25°C
Vo VIN VOD
(V) (V) (V) Min. Max Min. Typ. Max. Min. Max.
Ouiescent Device
Current IL
Output Voltage;
Low-Level.vOL
High Level, VOH
Noise Immunity
(All Inputs)
VNL, VNH
Noise Margin:
Inputs Low,
VNML
Inputs High,
VNMH
Output Drive Current:
ION, lOP
Zero Indicator
-
-
5
-
10
-
15
-
5
5
10
10
5
10
50
-
0.5
5
1
10
1
50
0
5
4.95 Min.; 5 Typ.
10
9.95 Min.; 10 Typ.
5
1
-
10
4.2
-
5
1.5 Min.; 2.25 Typ.
9
10
3'Min.; 4.5 Typ.
5
1 Min.
10
1 Min.
5
1 Min.
1
-
10
1 Min.
0.5
-
5
4.5
9
0.5
0.11
-
0.09 0.16
VI.
supply voltage for a typical CD4057A.
Fig. 4 - Transition time vs. load capacitance
for data outputs (D1-D4),
-
0.06
CLOCK PULSE RIS[ AND 'ALL TIMn
Yo.
p-channel
3
-
5
0.04
-
10
0.08
-
5
0.11
0.09 0.30
10
0_12
7
0.5
4.5
-
9.5
-
0.5
-
0.5
n-channel
0.5
p-channel
4.5
9.5
0.5
n-channel
0_5
p-channel
4.5
9.5
I nput Leakage
Current
IIL,IIH'
3 - Maximum counting frequency
V
0.12
All Other Outputs
Fig.
V
10
Overflow Indicator
V
1.5 Min.; 2.25 Typ.
-
p-channel
JJA
3 Min.; 4.5 Typ.
0.5
n-channel
300
2000
V
n-channel
Negative Indicator
150
o Typ.; 0.05 Max.
o Typ.; 0.05 Max.
0
0.8
-
-AT
5
0.07
10
0.12
5
0.25
10
0.37
5
0_08
-
10
0.12
-
-
5
0.11
10
0.06
5
0.02
10
0.06
~nT~5
0.10 0.16
-
0.07
0.03 0.06
-
0.02
-
0.07 0.13
-
O.OS
-
0.06
-
0.10 0.40
0.07
0.06 0.19
-
0.04
0_10 0.30
-
0.07
0.20 0.50
-
0.14
0.30 0_90
-
0.07 0.21
0.10 0.38
0.21
-
0.05
-
0.07
-
-
0.06
-
0.05 0.12
-
0_03
0.Q1
-
0.03
-
0.05 0.08
Fig_ 5 - Clock pulse rise and fall times,
-
0.09 0.10
0.02 0.05
L
rnA
Fig. 6 - Dat. .atup titTle.
~---VDD
VDD
HCS-2Jl74
± 10-5 Typ .• ± 1 Max.
/.!A
Fig. 7 - Datil hold time.
558 _________________________________________________________________
CD4057 A Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C and Cl = 15 pF. Rl =.200 kil.
trotf = 20 ns
Typical Temperature Coefficient at all values of VDD = 0.3%/oC
CHARACTERISTICS
Propagation Delay Time:
tplH,tpHL
DATA IN-toSUM OUT
CARRY IN-toSUM OUT
DATA IN-toCARRY OUT
CARRY IN-toCARRY OUT
Min.
Typ.
Max.
5
-
1430
3900
10
375
720
915
2550
10
-
310
840
5
-
950
2580
-
265
720
485
1320
175
480
1980
5400
750
2040
265
720
110
300
3700
10350
1650
4500
420
1140
5
10
5
10
10
5
10
Transition Time:
tTlH,tTHL
ZIOutput
5
10
5
10
5
Negative Indicator and
Overflow Indicator
10
All Other
Outputs
10
Minimum Clock Pulse
Width, tw
Clock Rise and Fall Time,
trCL,tfCl
Minimum Set Up Time: tSlH,tSHL
DATA
OPCODE
5
Count Mode
Shift Mode
Input Capacitance, CI
-
220
600
300
825
165
450
2775
475
1275
400
1200
10
125
375
5
-
-
15
10
20
40
10
20
1675
4590
485
1320
-
20
40
10
20
-
5
5
10
5
5
-
5
0.13
0.36
10
0.46
1.35
5
0.33
0.90
10
1.4
3.8
-
5
ANY INPUT
L
-
,----------,
ns
LEFT
~s:
DATA _
~
----XSyP;SS _--I
RIGHT
~
~~ ~
~~OATA
~
__________ J
LINE
BYPASS
r--------,
LEFT
;~RIGHT
DATA~~~OATA
~ _________ ~
L.INE
LINE
1000
10
Maximum Clock Frequency: fCl
-
r--------,
LEFT 0 :;~Mi"Et-<>...."v';s: ,RIGHT
~~J: :
: Ef'J:
LINE
-
10
Minimum Data Hold Time. tHlH' tHHl
-
The CD4057A arithmetic logic unit operates
in one of four possible modes. These modes
control the transfer of information, either
serial data or arithmetic operation carries, to
and from the serial-data lines. Fig. 8 shows
the manner in which the four modes control
the data on the serial-data lines.
UNITS
VDD
5
ZI Input
-toZIOutput
LIMITS
CD4057AD
TEST
CONDITIONS
LOGIC DESCRIPTION
OPERATIONAL MODES
BYPASS
~
92CS-202~2RI
Fig. 8 - Schematic of "Mode" concept.
ns
ns
ps
15
In MODE 0, data can enter or leave from
either the left or the right
serial-data line.
In MODE 1, data can enter or leave only on
the left serial-data line.
In MODE 2, data can enter or leave only
on the right serial-data line.
In MODE 3, serial data can neither enter
nor leave the register,regardless
of the nature of the operation.
Furthermore, the register is
by-passed electrically, i.e.,
there is an electrical bidirectional path between the right
and left seriafdata terminals.
The two input lines labeled Cl and C2 in
the terminal assignment diagram define one
of four possible modes shown in Table I.
Through the use of mode control, individual
arithmetic arrays can be cascaded to form
one large processor or many processors of
various lengths.
ns
TABLE I - MODE DEFINITION
ns
C2
Cl
MODE
ns
0
0
1
1
0
1
0
1
0
1
2
3
MHz
pF
Examples of how one "hard-wired"
combination of three ALU's can form (a) a
12-bit parallel processor, (b) one 8-bit and
one 4-bit parallel processor, or (c) three
4-bit parallel processors. merely by changes
in the modes of each ALCJ are shown in
Fig. 10.
559
CD4057 A Types
PARALLEL OATA
INIOUT LlfoES
,
ROTATE-'
ZI
IRol)
4
,,"UNCTION { :
SELECT
*
INPUT
•
,
t
6
d
7
CLOCK
INPUTS
A'
B
* {
CONDITIONAL
C
OVERFLOW
I/O
£3f
OVERFLOW
INO
ROTATE-Z
(Roll
OO
*ALL INPUTS PROTECTED BY
COStMOS PROTECTION NETWORK
vss
Fig. 9 - Simplified logic diagram.
Data-flow interruptions are shown by shaded
areas. With these three ALU's and the four
available modes. 61 more system combinatlons can be formed. If 4 ALU's are used.
44 combinations ('256) are possible. Fig. 11
shows a diagram of 4 CD4057A's interconnected to form a 16-bit parallel processor.
.~
b.~
abc
0 0 0
0 0 0
0 0
0 0
d
0
1
0
1
0
0 0
o
0
o
o
0
000
o
c.
92C5-20254
Fig. 10 -
"Mode" connections for parallel
0
010
o1 1
processor:
o
la} 72-bit unit,
Ib} one 8·blt and one 4-bit unit
Ie}
4-bit units.
o
three
NOTE: The BYPASS terminal of the "most
significant". CD4057 A is connected to the
bypass terminal of the "least significant"
CD4057 A. The bypass terminals on all other
CD4057A's are lett floating. This interconnection is' performed whenever more
than one CD4057 A are used to form a
processor_
II'JSTRUCTION REPERTOIRE
Four encoded lines are used to represent
16 instructions. Encoded instructions are as
follows:
0
o
1
NO-OP (Operational Inhibit)
AND
Count down
Count up
Subtract Stored number
from zero (SMZ)
Subtract from parallel data
lines (SM) (stored number from
parallel data lines)
Add (AD)
Subtract (SUB) (Parallel data
lines from stored number)
Set to all ones (SET)
Clear to all zeroes (CLEAR)
Exclusive-OR
OR
Input Data (From parallel
data lines)
Left shift
Right shift
Rotate (cycle) right
All instructions are executed on the positive
edge of the clock.
PARALLEL COMMANDS
a. CLEAR - sets register to zero.
b. SET -sets register to all ones.
c. OR -processes contents of register
with value on parallel-data lines in
a logical OR function.
d. AND -processes contents of register
with value on parallel-data lines in
a logical AN 0 function.
e. Exclusive-OR - processes contents
of register with data on parallel-data
lines in a logical Exclusive-OR function .
f. IN -loads data on parallel-data lines
into register:
g. DATA OUT CONTROL - unloads
contents of register-and overflow
flip-flop onto parallel data lines and
overflow I/O independent of all other
controls.
h. SUB:
In Mode 0, adds to the contents of
the register the one's com·
plement of the data on the
parallel-data lines. Carries
can enter on the right
serial data line and can
leave on the lett serial
data line. The overflow
indicator does not change
state.
In Mode 1, adds to the contents of the
register the two's complement of the data on the
parallel-data lines. Generated carries can leave on
the lett serial line. The
CARRY IN is set to zero.
The overflow indicator
does not change state.
In Mode 2, same as Mode 0, except
carries cannot-leave on the
right serial-data line.The
absence or presence of an
overflow is registered.
In Mode 3, same as Mode 1, except
carries cannot leave on the
lett serial-date line. The
absence or presence of an
overflow is registered.
i. COUNT UP:
In Mode 0, adds to the contents of the
register the data on the
right serial-data line and
permits any resulting carry
to leave on the lett serialdata line. No data enters
the parallel-data lines.
In Mode 1, internally adds a one to
the contents of the register
and permits any resulting
carry to leave on the lett
serial-data line. No data
enters or leaves the right
serial-data line.
In Mode 2, adds to the contents of the
register the data on the
right serial-data line. No
data enters or leaves the
lett serial-data line.
In Mode 3, internally adds a one to
the contents of the register
No data enters or leaves
the register on any serialdata or parallel·data line.
In all modes, with the
DATA OUT control high
560 _____________________________________________________________
CD405 7 A Types
RIGHT SERIAL
LEFT SERIAL
DATA LINE
(CARRY OUTI
DATA LINE
(CARRY IN)
ZERO INO
ZERO INO
ZERO INO
ZERO INO
BYPASS
BYPASS
BYPASS
BYPASS
R,I
R"
Ro2
R,2
R"
R"
R,2
R,2
•
L-+_+-__
Voo
• TERMINAL INTENTIONALLY LEFT FLOATING
Voo
VOO
VSS
UCS-20U9
Fig. 11 -
Connection for 16·bit arith/fletic logic unit.
the count is presented on
the parallel data lines (0104)_
i- COUNT OOWN:
In Mode 0, subtracts a one (2's complement form) from the contents of the register and
adds to this result the data
on the right serial-data line
and permits any resulting
carry to leave on the left
serial-data line. No data
enters on the parallel-data
lines.
In Mode 1, internally subtracts a one
from the contents of the
register and permits any
resulting carry to leave on
the left serial-data line. No
data enters or leaves the
right serial-data line.
In Mode 2, subtracts a one from the
contents of the register and
adds to this result the data
on the right serial-data line.
No data enters or leaves on
the left serial-data line.
In Mode 3, internally subtracts a one
from the contents of the
register. No data enters or
leaves on the serial-data
lines.
In all modes, with the OATA OUT control
high the count is presented on the parallel
data lines (01-04).
k. AOO(AO):
In Mode 0, adds the contents of the
register to the data on the
parallel-data lines and the
right serial-data line. Any
resulting carry can leave on
the left serial-data line. The
overflow indicator does not
change state.
In Mode 1, adds the contents of the
register to the data on the
parallel-data lines and allows
any resulting carry to leave
on the left serial-data line_
The right serial-data line is
open-circuited. The overflow indicator does not
change state. The CARRYIN is set to zero.
In Mode 2, adds the contents of the
register to the data on the
parallel data lines and the
right serial-data line. Any
overflow sets the overflow
indicator. The left serial·
data line is open-circuited.
The absence or presence of
an overflow is registered.
In Mode 3, adds contents of the register
to the data on the paralleldata lines. Any resulting
carry sets the overflow indicator. The two serial-data
lines are open circuited. The
absence or presence of an
overflow is registered. The
CARRY-IN is set to zero.
I. SM - same operation as AO except the
contents of the register are two's complemented during addition in Mode 1 and
Mode 3. In Mode 0 or Mode 2, the contents of the register are one's complemented and added to the data on the
right serial-data line and the paralleldata lines. Overflows occurring in Mode
1 or Mode 0 do not alter the overflow
indicator_The presence or absence of
overflows is registered on the overflow
indicator in Mode 2 or Mode 3.
m. SMZ:
In Mode 0, one's complements the
contents of the register
and adds the data on the
right serial-data line to the
contents of the register.
Any resulting carry can
leave on the left serialdata line. The overflow
indicator does not change
state.
In Mode 1, two's complements the
contents of the register
and permits any carry to
leave on the left serialdata line. No data can
enter the right serial-data
Iine. The overflow indicator does not change
state. The CARRY-IN is
set to zero.
In Mode 2, one's complements the
contents of the register
and adds the data on the
right serial-data Iine to the
contents of the register.
Carries cannot leave the
left serial data line. The
absence or presence of an
overflow alters the
overflow indicator.
In Mode 3, two's complements the
contents of the register.
Serial data can neither
the right serialenter
data Iine nor leave the
left serial-data line. The
overflow indicator is at
zero. The CARRY-IN is
set to zero.
n.
NO-OP - no operation takes place,
The clock input is inhibited and the state of all
registers and indicators
remains unchanged.
SERIAL-SHIFT OPERATIONS
a. ROTATE (cycle) RIGHT - This operation is internal. The contents of the
register shift to the right, cyclic fashion
with the leftmost stage accepting data
from the rightmost stage regardless of
the mode. Oata can leave the register
serially on the right data line only while
the register is in Mode 1 or Mode O.
Oata can enter the left data line serially
while the register is in Mode 1 or Mode
O. The Ro1 terminal of the "Most
Significant" C04057 A must be connected to the R02 terminal of the "Least
Significant" C04057 A. All other Ro 1
and R02 terminals must be left floating.
When only one C04057A is used, Ro1
must be connected to R02.
b. RIGHT SHIFT - The contents of the
register shift to the right and serial operations are as follows:
In Mode 0, data can enter serially on
the left data line, shift
through the register, and
leave on the .right data
line.
In Mode 1, data can enter serially on
the left data line. The
right data line effectively
is open - circuited.
In Mode 2, data can leave serially on
the right data line. The left
data line effectively is opencircuited. Vacant spaces are
filled with zeros.
In Mode 3, serial data can neither enter nor leave the register;
however, the contents sh ift
to the right and vacated
places are filled with zeros.
__________________________________________________________________ 561
CD4057 A Types
c.
In all modes, with the DATA OUT
control high the data is presented
on the parallel data lines (01·04).
,
LEFT SHIFT - The contents of the
register sh ift to the left and serial
operations are as follows;
In Mode 0, data can enter the right
data line, shift through the
register, and leave on the
left data line.
In Mode " data can leave serially on
the left data line. The right
data line effectively is
open-circuited. All vacant
positions are filled with
zeros.
In Mode 2, data can enter serially on
the right data line. The
left data line effectively is
open·circuited.
In Mode 3, data can neither enter nor
leave the register; however,
the contents shift to the
left, and vacated places
are filled with zeros.
In all modes, with the DATA OUT
control high the data is presented on
the parallel data lines (01·04).
0
Because the "DATA our' control instruction is independent of the other 16 instructions, care must be teken not to activate
this control when date are to be loaded into
the processor. This instruction should only
be activated when the procassor is executing
a NO-OP, any SHIFT, SMZ, COUNT UP or
DOWN, CLEAR, or SET.
If a data line, serial or parallel, is used as an
input and the logic state of that line is not
defined (Le., the line is an open circuit),then
the result of any operation using that line is
undefined.
a.,AR
SET
,.
NO CLEAR NO
OP.I--
L.TSHfn
f-
,
NO
'"
OF.'
,
,.
,.
RT SHIFT
S.
,.
NO
0'1'--
f-
'--I-
I-
r-
,I--
'-F I'--
,
,--
f----
I--
I--
1-1'-l-
r
r
I--
NO
IN
EXI:UJSIIIE. NO
"'I-- f-S!!- o.
-
I-I--
-
f--
0
...
-
I--
I-I'--
lL
,
C2
01\110 .-
DATA ,.
'---,
o
'---,C_
0
o'---,
L_
-DATA.-
- I'--
,C_
I-- ~-
p~
~-
R: w-
I-- ~-
'---,C_I-,
,
0
,
0
~..J
ZERO INo.
,
NEG. tHD
OVERFlOW
,
IL
1---
I--
,-- -
-L
- -L
[--'t_ ~'I'--I'-- 1--- ',-- H
- -L
I'-I'-- r-- -L_r-I-- -L
I'--
r--
1---
L
I-I'--
IIO
---
-
~ h
r h
r h
-,
r
,
01---. I'--
J.nLr
--- -
I
~-.
I'--
L
IND.
ovtRF~
I--
-
_.
.-
Lr lrL l.J Ln.. J" Lr U-
MOTES: RoI CONNECTED TO R02; IY-H.$S IS OPEN; ZI CONNECTED TO
'IOo.,,~
IN ttODE
s.
n
,-
--I I
-
-SOLID LINE ItEPlt£SENTS INPUT FROM EXTtRlOR SOURCE WHEN "DATa. OUT" IS LOW; DASHED LINE
REMESlNTS OUTPUT WHEN "MrA
ouT" IS HIGH.
Fig. 12 - Timing diagram.
NEGATIVE-NUMBER DETECTION
The NEG IND terminal of the CD4057A is
connected to the output of the flip-flop
that is in the most significant bit position.
A "'" on the NEG IND terminal indicates
a negative number is in the register. This
detection is also independent of modes_
INPUT II
- --
IM"UT c
INPUT cI
OPERATIONAL SEQUENCE FOR
ARITHMETIC ADD CYCLE
1.
2.
3.
4.
5.
Apply IN Instruction and Word A on
Parallel Data Lines (01,...04).
Apply CLOCK to load Word A into
the register.
Apply OP CODE Instruction and Word
B on Date Lines.
Apply CLOCK to load resulting
function of A and B into the register.
Apply "DATA OUT" control to
present result to Parallel Data Lines.
NOTE: Transitions of Step 2 and Step 3
may occur almost simultaneously; i.e.
separated by only one data-hold time.
562
ZERO DETECTION
The condition of "all zeros" is indicated
by a "1" on the Zero Indicator terminal
of the "Most Significant" CD4057A.
As shown in Fig. 11, terminal 21 of the
CD4057A containing the least significant
set of bits is connected to V DO' Zero
indication is independent of modes.
COMPLEMENTING NUMBERS
1. One's complement of number in ALU
register.
a) ALU must be in MODE 0 or MODE 2.
b) Zero on Rt. Data Line.
c) Execute an SMZ instruction.
(Continued)
"OATAOUT"
CLOCK
-
OATA 21t
-
;~
'--
n
h---L
~----
, --,L......
DATA .,.
,
-
---
-
CARA'I'M
OVERFLOW
LNOICATOR
NEGATIVE
LNOICATOft
-
t---- t---I--
Fig. 13 - Add cycle waveforms.
CD4057 A Types
2. One's complement of number to be
loaded into ALU register.
a) If zero indicator output is low,
execute a CLEAR instruction, and
make Rt. Data Line = o.
b) ALU must be in MODE 0 or MODE 2.
c) Execute an SUB instruction.
3. Two's complement of number in ALU
register.
a) ALU must be in MODE 1 or MODE 3.
b) Execute an SMZ instruction.
4. Two's complement of number to be
loaded into ALU register.
a) If zero indicator output is low,
execute a CLEAR instruction,
and make Rt. Data Line = O.
b) ALU must be in MODE 1 or MODE 3.
c) Execute an SUB instruction.
The following algorithms are given as a
general guideline to demonstrate some of
the capabilities of the CD4057 A.
MULTIPLICATION OF
TWO N-BIT NUMBERS
00 ... 0/00 .. 0
0 ... O/As • al' ..aN-l
I
Multiplier
0 ...OO/Bs .. bl' .. bN-l
I
Multiplicand
• As and Bs are sign bits
Multiplication Algorithm
1. Clear ALU to Zero
2. Store As
Bs in External Flip-Flop.
3. If As = 1, Complement Register 1.
4. If Bs = 1 , Complement Register 2.
5. Load Register 2 into ALU.
6. Do shift Left on ALU N Times
(N = number of bits).
7. Do N Times:
TABLE II - CONDITIONAL-INPUTS
TRUTH TABLE
Division Algorithm
Dividend
(1)
e
X
X
1
1
1
1
0
0
1
0
1
0
1
Yes
No
No
Yes
B
1
C
X = don't care
I
Divisor
e
Bs in External Flip-Flop.
1. Store As
2. If As =1, complement ALU 1 and ALU 2.
3. If Bs = 1, complement Register A.
4. Check for Divisor = 0
a) If Divisor = 0; stop, indicates
division by O.
b) If Divisor *0; continue.
5. Apply SUB instruction to ALU 1
and the contents of Register A to
ALU 1 data lines.
6. Put a zero on RT data line of ALU
2 and shift ALU 1 & ALU 2 left 1
bit.
7. Do "N" times.
(1) Apply a sub instruction to ALU 1
and the contents of Register A to
the ALU 1 data lines.
a) If Co = 1, then clock ALU 1, and
put a 1 on right data line of ALU 2,
b) If Co = 0, then do not clock, and put
a 0 on right data line of ALU 2.
(2) Shift left 1 bit .
8. If sign Flip Flop =1, complement
ALU 2.
9. Answer in ALU 2.
e
a) If MSB of ALU = 1
(Negative Indicator = High),
Then shift ALU left 1 bit;
add Register 1 to ALU.
b) If MSB of ALU = 0
(Negative Indicator = Low)
Then shift ALU left 1 bit.
Bs =1, then Complement
8. If As
ALU.
9. Answer in ALU.
0
OPERATION
PERMITTED
Yes
A
CONDITIONAL OPERATION
Inhibition of the clock pulse can be accomplished with a programmed NO-OP instruction or through conditional input terminals
A,B,and C.ln a system of many CD4057A's,
each CD4057 A can be made to automatically control its own operation or the
operation of any other CD4057 A in the
system in conjunction with the Overflow,
Zero, or Negative (Number) indicators.
Table II, the conditional inputs, truth
table, defines the interactions among A,B,
and C.
Two examples of how the conditional
operation can be used are as follows:
1) For the Multiplication Algorithm
A = 1, for step 7 (1)
A = 0, for step 7 (2)
B=l
C = negative Indicator
2) For the Division Algorithm
A = 1, for step 7 (1)
A = 0, for step 7 (2)
B=l
C = Co /left data line)
OVERFLOW DETECTION
The CD4057 A is capable of detecting and
indicating the presence or absence of an
arithmetic two's-complement overflow. A
two's-complement overflow is defined as
having occurred if the signs of the two initial
words are the same and the sign of the result
is different while performing a carry-generating instruction.
0.011
For example:
(+) 0.110
1.001
Overflows can be detected and indicated
only during operation in Mode 2 or Mode 3
and can occur for only four instructions
(AD, SMZ, SM, and SUB). If an overflow is
detected and stored in the overflow flip-flop,
anyone of the five instructions AD, SMZ,
SM, SUB, or IN can change the overflow
indicator.
When any of the three subtraction instructions is used, the sign bit of the data being
subtracted is complemented and this value
is used as one· of the two initial signs to
detect overflows. If an overflow has occurred, the final sign of the sum or difference is
one's complemented and stored in the mostsignificant-bit position of the register.
The overflow flip-flop is updated at the same
time the new result
is stored in the
CD4057 A. Whenever data on the paralleldata lines are loaded into the CD4057 A,
whatever is on the Overflow I/O line is
loaded into the overflow flip-flop. Also,
whenever data are dumped on the parallel
data Iines from the CD4057 A, the contents
of the overflow flip-flop are dumped 011 the
Overflow I/O line. Thus overflows may be
stored elsewhere and then fed into the
CD4057A at another time.
,_________________________________________________________________ 563
CD405 7 A Types
OPERATIONAL SEQUENCE
AND WAVEFORMS FOR
PROPAGATION-DELAY MEASUREMENTS
1.
2.
CARRY IN·to·CARRY OUT and CARRY
IN·to·SUM OUT
A.
B.
Apply Word A and IN instruction
Apply Clock to load word A into
register
C. Apply AD instruction
D. Apply Word B (data in)
E. Apply Clock to load result
(sum out)
F. Apply DATA OUT CONTROL
to look at result
'NPUTOVCO
OUTPUTS
A. Apply Word A and IN instruction
B. Apply Clock to load word A into
register
C. Apply AD instruction
D. Apply Word B
E. Apply CARRY IN (carry in)
F. Apply Clock to load result
(sum out)
G. Apply DATA OUT CONTROL
to look at result
DATA· IN·to·CAR RY OUT and DATA
IN·to·SUM OUT
VDO-YNH
.........
.
~
l
VNOL
NOTE:
Vss
~-.'-.
WITH OTHER INPUTS AT
92CS-27~OO "00 ORVss·
Fig. 15 - Noire-immunity
INPUTS
telt circuit.
r--L--,
o
Vss
ii
INPUT
b
INPUT c. _-+-+---'
INPut d
bATA OUT CXlNTROL
Vss
--+-t--t-+-+--+---
--1==+=:j:::::jII!'--1-
DATA OUT CONTROl.
--l-
DATA ,.
,
DATA
'-----
DATA 4·--+-+--I-~
-1==+===t111
Fig. 16 - Qu;est:8fIt·dsv;cs-current
test circuit
'·-i=t:==~
Voo
CLOCK
CARRY OUT
CD DArA IN
® CARRY OUT
Q)
o
-+-i--+-+I
SUM OUT
CD-@ OATA,. TO CARRY OUT
CD -@ DATA IN TO SUM OUT
t
INPOurVDO
~
CAlIA' OUT
SUM OUT
CD-@CoUIR't'INTOCARRYOUT
CD _@CAMYIN TO SUM OUT
F ;g. 17 - Input-1saka!Jt1'Current .
test circuit
Fig. 14(a} - DATA IN·to·CARRYOUTand
DATA IN·to-5UM OUT.
Fig. 14(b} - CARRY IN·to·CARRY OUT and
CARRY IN·to-5UM OUT.
TYPICAL APPLICATION
The CD4057A has been designed for use as a
parallel processor in flexible, programmable,
easily expandable, special or general purposa
computers, where minimization cif external
connections and data busing are primary
design goals. The block diagram of Fig. 1B
is an example of a computer that processes
8 bits in parallel.
C04034A
INPUT-OUTPUT
REGISTER
EXTERNAL
DATA
92CIIII-21112
Fig. 18 - Example of computer organ;zst;on using CD4057A.
564
CD4059A Types
COS/MOS Programmable
Divide-by-"N" Counter
CL
JI
Standard" A"-Series Types (3-to-15-Volt Rating)
RCA·CD4059 standard "A"-5eries types are
divide-by-N down·counters that can be pro·
grammed to divide an input frequency by
any number "N" from 3 to 15,999. The output signal is a pulse one clock·cycle wide
occurring at a rate equal to the input frequency divided by N. This single output has
TTL drive capability. The down·counter is
preset by means of 16 jam inputs.
The three Mode-Select Inputs Ka, Kb, and
Kc determine the modulus ("divide·by"
number) of the first and last counting sections in accordance with the truth table
shown in Table 1. Every time the first
(fastest) counting section goes through one
cycle, it reduces by 1 the number that has
been preset (jammed) into the three decades
af the intermediate counting section and into
the last counting section, which consists of
flip·flops that are not needed for operating
the first counting section. For example, in
the + 2 mode, only one flip-flop is needed
in the first counting section. Therefore
the last counting section has three flip·flops
that can be preset to a maximum count of
seven with a place value of thousands. If
+ 10 is desired for the first section, Ka is
set to 1, Kb to 1, and Kc to O. Jam Inputs
Jl,J2, J3, and J4 are used to preset the
first counting section and there is no last
counting section. The intermediate counting
section consists of three cascaded BCD decade (+ 10) counters presettable by means
of Jam Inputs J5 through J16.
The Mode-5elect Inputs permit frequencysynthesizer channel separations of 10, 12.5,
20, 25, or 50 parts. These inputs set the
maximum value of N at 9999 (when the
first counting section divides by 5 or 10) or
15,999 (when the first counting section
divides by 8, 4, or 2).
The three decades of the intermediate counting section can be preset to a binary 15 instead of a binary 9, while their place values
are still 1, 10, and 100, multiplied by the
number of the + N mode. For example, in
the + 8 mode, the number from which count·
ing·down begins can be preset to:
3rd decade:
2nd decade:
1st decade:
Last counting section
1500
150
15
1000
The total of these numbers (2665) times
8 equals 21,320. The first counting section
can be preset to 7. Therefore, 21,327 is the
maximum possible count in the + 8 mode.
The highest count of the various modes is
shown in the column entitled Extended
VDD
23
J2
Counter Range of Table 1. Control inputs
Kb and Kc can be used to initiate and lock
the counter in the "master preset" state.
In this condition the flip-flops in the counter
are preset in accordance with the jam inputs and the counter remains in that state
as long as Kb and Kc both remain low. The
counter begins to count down from the
preset state when a counting mode other
than the master preset mode is selected.
The counter should always be put in the
master preset mode before the +5 mode is
selected.
Whenever the master preset mode is used,
control signals Kb=O and Kc=O must be
applied for at least 3 full clock pulses.
After the Master Preset Mode inputs have
been changed to one of the + modes, the
next positive·going clock transition changes
an internal flip·flop so that the countdown
can begin at the second positiveiloing clock
transition. Thus, after an MP (Master Presetl
mode, there is always one extra count before
the output goes high. Fig.l illustrates a
total count of 3 (+ 8 mode). If the Master
Preset mode is started two clock cycles or
less before an output pulse, the output pulse
will appear at the time due. If the Master
Preset Mode is not used the counter jumps
back to the "JAM" count when the output
pulse appears.
J5
21
J6
J7
J3
20
I.
J8
JIS
18
JI5
17
J.
JIO
JI4
16
JII
JI3
15
JI2
VSS
II
14
Ka
13
Kb
l.12-:T:::O:::P-:V:::IE::W::-....J
92CS-22212RI
TERMINAL DIAGRAM
Operational and Performance Features:
• Synchronous Programmable + N Counter:
N =3 to 9999 or 15,999
• Presettable down-counter
• Fully static operation
• Mode-select control of initial decade
counting function (+ 10,8,5.4,2)
• T2L drive capability
• Master preset initialization
• Latchable + N output
• Quiescent current specified to 15 volts
• Max. input leakage current of 1 /lA at 15
volt5.•full package-temperature range
• 1 volt noise margin, full packagetemperature range
• 5-V and 10-V parametric ratings
Applications
•
•
•
A "1" on the Latch Enable input will cause
the counter output to remain high once an
output pulse occurs, and to remain in the
high state until the latch input returns to
"0". If the Latch Enable is "0", the output
pulse will remain high for only 1 cycle of
the clock·input signal.
22
J4
Kc
•
Fig. 1 - Total count of 3.
4
OUT
Communications digital frequency
synthesizers: VHF, UHF, FM, AM,etc.
Fixed or programmable frequency
division
"Time out" timer for con"sumer-appli-
cation industrial controls
Companion Application Note,ICAN-6374,
"Application of the COSIMOS CD4059A
Programmable Divide-by-N Counter in
FM and Citizens Band Transceiver
Digital· Tune!s"
The CD4059A series types are available in a
24-lead ceramic dual-in-line package. 24lead dual-in-line plastic package, 24-lead
ceramic flat package, and in chip form.
As illustrated in the sample applications, this
device is particularly advantageous in com·
munication digital frequency synthesis (VHF,
UHF, FM, AM, etc.) where programmable
divide~by-"N"
counters are an integral part
of the synthesizer phase·locked·loop sub·
system. The CD4059A can also be used to
perform the synthesizer "Fixed Divide·by-R"
counting function. It is also useful in general·
purpose counters for instrumentation func·
tions such as totalizers, production counters,
and "time out" timers.
565
CD4059A Types
MAXIMUM RATINGS, Absolute-Maximum Values.'
DC SUPPLY-VOLTAGE RANGE, V DD (Voltages referenced to VSS terminall
INPUT VOLTAGE RANGE, ALL INPUTS .
POWER DISSIPATION PER PACKAGE (PO):
For T A = -40 to +600 C (Package Type E)
For T A = +60 to +85 0 C (Package Type E) .
For T A = -55 to +100 0 C (Package Types D,H)
For TA = +100 to +1250 C (Package Types D,H)
DEVICE DISSIPATION PER OUTPUT TRANSISTOR:
-0.5 to +16 V
-0.5 to V DD +0.5 V
500mW
Derate Linearly to 200 mW
500mW
Derate Linearly to 100 mW
For T A = Full package·temperature range (All package types) .
100mW
OPERATING-TEMPERATURE RANGE ITA):
Package Types 0, H
Package Type E •
STORAGE-TEMPERATURE RANGE (TSTG) .
LEAD TEMPERATURE (During Soldering):
At distance 1/16 ± 1/32 inch (1.59 ±0.79 mm) from case for 10 s max.
-55 to +1250 C
-40'0 +850C
-65,0 150°C
OPERATING CONDITIONS AT T A = 25°C
(Unless otherwise specified)
For maximum reliability, nominal operating condit!ons should be selected so that operation is alwavs
within the following ranges.
Characteristic
VDD Min. Max. Units
SupplV Voltage
Range
3
12
V
(over full temprange)
Clock Pulse
5
200
ns
10
100
Width
Clock Input
5
1.5
MHz
Frequency
10
3
1:
~
STATIC ELECTRICAL CHARACTERISTICS
7
60
Characteristic
Vo VIN
(V) (V)
5
10
15
Quiescent Device
Current,
IL Max.
_400
+850 +1250
10
.20
10
20
700
200
300
400
-
-
-'
-
liS
AMBIENT TEMPERATURE'TA 1-25-C
200-~~STANT
!:!.
Lim~ts
!;;
Valuesat-5S"C,+2S"C, +12S"C Apply to 0, H Packages
Values at -400C,+25 0 C,+850 C Apply to E Packages
VOD
(V) _55 0
15
5
POWER LOCUS
Q
Conditions
5
10
Clock Input Rise
and Fall Time
-
-
t!40
Units
Min.
TYP.
Max_
-
0.02
0.02
10
20
500
-
~
Z 30
+250
i.:20
IJ.A
!~
10
GATE- TO- SOURCE
VOl-TAGE IVGs )- 5
v
2345678
Output Voltage:
Low Level,
VOL Max.
ORAIN-TO-SOURCE VOLTAGEIVosl-V
05
0,10
0,5
0,10
High Level,
VOH Min.
Noise Immunity:
Inputs Low,
"NL Min.
Inputs High,
VNH Min.
-
0.05
0.05
4.95
9.95
0
0
5
10
1.5
3
1
3
2.25
4.5
2.25
4.5
-
5
10
0.05
0.05
-
5
10
4.95
9.95
5
10
5
10
1.5
3
1.5
3
-
-
Fig.2 - Minimum output n-channel
dm;n characteristics.
V
lOy
1
! 60
I~V
AMBIENT TEMPERATURE'
Z
V
c
(fA 1-25-C'
!:!0- '0
200-mWCONSTANT
Z
~ 40
POWER LOCUS
§
u
Z30
Noise Margin:
Inputs Low,
VNML Min.
4.5
9
5
10
1
1
Inputs High;
VNMH Min.
0.5
1
5
10
1
1
"
!i
V
~
GATE-TO- SOURCE
VOl-TAGEIVOSI-5V
z
~ 10
1234567
Output Drive
DRAIN-TO-SOURCE VOLTAGEIVos)-V
Current:
N-Channel
(Sink)
ION Min.
0.4
0.5
5
10
2.5
5
P-Channel
(Source)
lOP Min.
2.5
4.6
9.5
5
5
10
-2
-0.5
-1.1
I nput Leakage
Current:·
IlL, 11H Max.
15
2.3
1.6
1.4
4.7
3.3
2.8
2
4
4
9
-1.B -1.3 -1.16 -1.6 -3.2
0.45
0.36 0.3
0.4 O.B
-1
-0.75 -0.65 -0.9 -1.B
±1
±10- 5
FiIJ-3 - Typical output n-ch.nnel
drain characteristics.
-
rnA
DRAIN-TO-SOURCE VOLTAGE 1'1051-'1
-10
.,
AMBIENT TEMPERATURE ITA '.25-C
±1
GATE-TO-SOURCE VOLTAGE 1'1651--''1
IJ.A
lOY
• Any Input
·15'1
FigA - . Minimum output p"l:hannel
drain characteristics.
566
CD4059A Types
DRAIN-TO-SOURCE VOLTAGE {Vasl-V
DYNAMIC ELECTRICAL CHARACTERISTlCSATTA = 25 0 C,CL =50 pF,lnputtr ,tf=20 ns,
RL =200 Itp.
-I
-!I
-10
AMBIENT TEMPERATURE (T A '-25-C
GATE-TO-SOURCE VOLTAGE (VGS"· 5
CONDITIONS
VDD
(V)
CHARACTERISTIC
Propagation Delay Time; tpH l' tplH
LIMITS
ALL PACKAGES
v
UNITS
Min_
Typ_
Max_
5
10
-
-
180
90
360
180
5
-
35
20
70
40
5
10
-
-
100
50
200
100
5
10
1.5
3
3
6
-
MHz
-
-
5
-
pF
200-mW CONSTANT
POWER LOCUS
ns
-15'1
Transition Time:
tTHl
tTLH
Maximum Clock Input Frequency, tCl
Average Input Capacitance,
(any input)
10
ns
Fig. 6 - Typical output p-channel
drain characteristics.
C,
AMBIENT TEMPERATURE (TA 1=25-C
::
PROGRAM JAM INPUTS (BCD!.
i~
Vss@voo
9
€>-
+tt~t
0
~
ro
~
~
~
~
ro
~
00
~
LOAD CAPACITANCE (CL,l-pF
Fig.7 - Typicallow-to-high propagation delay
time vs. load capacitance.
AMBIENT TEMPERATURE ITA )I025·C
'0
20
30
40
50
60
70
LOAD CAPACITANCE (CLJ-pF
60
90
100
92CM-22213RI
Fig.S - Typical high-to-Iow propagation delay
time vs. load capacitance.
ALL INPUTS (TERMS_1·-11, 13-221 PROTECTED
BY COS/MOS PROTECTION NETWORK
Fig.5 - Functional block diagram.
L.OAO CAPACITANCE ICL.J-pF
Fig.9 - Typicallow-to-high transition time
vs. load capacitance.
567
CD4059A Types
TABLE I
MODE
SELECT
INPUT
Ka Kb
FIRST COUNTING
SECTION
MODE
--Di:
Kc
vides
by:
w
~
~
~
~
ro
~
00
~
~
LOAD CAPACITANCE ICL)-pF
Fig. to - Typical high-to%~~w transition time
VB.
i
load capacitance.
~:-~EcNATp.:c~~~~~~:~.';a~·/5'
I
15
'
1
0
1
1
1
1
1
0
0
0
1
X
Can be
preset
to a
max
of:
LAST COUNTING
SECTION
vides
by:
Can be
preset
to a
max
of:
Jl
Jl,J2
8
4
3
Jl,J2,J3
Jl,J2,J3
J I,J2,J3,J4
2
Jam'"
inputs
used:
3
4
1
1
1
0
2
4
5#
1
8
10
7
9
0
0
MASTER PRESET
X : Don't Care
... Jl : Least significant bit.
MODE
--Di·
7
1
1
0
2
1
COUNTER
RANGE
DESIGN EXTENDED
Jam&
inputs
used:
Max.
Max.
J2,J3,J4
J3,J4
15,999
17,331
15,999
9,999
15,999
18,663
13,329
J4
J4
-
21,327
16,659
9,999
MASTER PRESET
-
-
#Operation in the +!imode (1st counting section) requires
going through the Master Preset mode prior to going into
the +5 mode. At power turn·on, kc must be a 10gic·"O"
for a period of 3 input clock pulses after VDD reaches
a minimum of 3 volts. See Fig. 21 for a suggested external
preset circuit.
J4: Most significant bit.
HOW TO PRESET THE CD4059A TO DESIRED + N
o
5
10
15
SUPPLY VOLTAGE 1Voo)-V
20
The value N is determined as follows:
N: [MODE"]
[1000 x Decade 5 Preset + 100X Decade 4
Preset·+ lOX Decade 3 Preset + 1X DeCade 2 Preset I + Decade 1 Preset
Fig. It - Typical max. clock frequency
vs. supply voltage.
MODE: First counting section divider (10, 8, 5, 4 or 2)
6 AMBIENT TEMPERATURE (T A "lS'e
,
4
~105
- .,
.:,
II
,.'0'"
~
~,o'
,...~
is
~ I
,0"
To calculate preset values for any N count, divide the N count by the Mode.
The resultant is the corresponding preset values of the 5th through 2nd
decade with the remainder being equal to the 1st decade value.
II
.!. I
4681
,(04
103
2
...
f
MODE SELECT = 5
169~ Preset Values
,II
INPUT FREQUENCY (I)-kHz
,s 184~9
Mode
Ka Kb Kc
1 0
1
N
Fig. 72 - Typical power dissipation vs.
input frequfmcy.
PROGRAM JAM INPUTS (BCD)
t
AMBIENT TEMPERATURE CTA 1- 2s'C
4 LOAD CAPACITANCE [ell-50pF
,
- .,
::'10 58
I
sJp~~~
J,LT~'
(Voo -IOV
o
i :
--
2
Ct: 103
~
2
I
•
,
'0'
.. , ..
V
10
2
4 6 B
103
2
N = 8479
No'
"-10,000
~
4 68
104
2
Fig. 73 - Typical power dissipation
clock input frequency.
1547 + 6
4.8
1(1
92CS-U'4!1
568
1
0
0
J13 J14 J15 J16
o
0
MODE SELECT: 8
B) N: 12382, Mode: 8
CLOCK INPUT FREQUENCY(fCLJ-KHz
VS'.
0
~
J9 Jl0 Jl1 J12
To verify the results use equation 1 :
N = 5 (1000X 1 + 100X6+ 10X9+ 1 X 5) +4
I 1111
To!
J5 J6 J7 J8
o
0
5V
~
6
~
Jl J2 J3 J4
•
104,
5
4
~
~
(1 )
8
I 12382
Ka Kb Kc
o 0 1
CD4059A Types
"CASCADING" VIA OTHER COUNTERS
PROGRAM JAM INPUTS
6
7
4
J5 J6 J7 J8
J9 Jl0 Jll J12
~
Jl J2 J3 J4
o
o
o
J13 J14 J15 J16
o
0
o
o
To verify:
N ~ 8 (1000 Xl + 100 X 5 + 10 X 4 + 1 X 7) + 6
N ~ 12382
MODE SELECT
C) N ~ 8479, Mode
~
10
Ka Kb Kc
1
0
0847 + 9
1018479
9
Jl
~
10
7
PROGRAM JAM INPUTS
4
~
J2 J3 J4
o 0 1
J5 J6 J7 J8
1
0
J9 Jl0 Jll J12
000
J13 J14 J15 J16
o 0 0
To Verify:
N ~ 10 (1000 X 0+ 100 X 8+ 10X4+ 1 X 7) + 9
N ~ 8479
DIGITAL PHASE-LOCKED LOOP (PLLI FOR FM BAND SYNTHESIZER
i
OUTPUT
9B.B to llB.6 MHz
---
10
VCO
H ....
Ik
+K
PRESCALER
2.41 to
2.965
MHz
CHANNEL
SELECT
In
+N
rpCOMP
COUNTER
CD4059A
5 kHz
R = 51.2
+A
XTAL
OSCILLATOR
COUNTER
CD4059A
Ir
1-
5 kHz
2.56 MHz
LOW·PASS
FILTER
I = In - I r
11 Calculating Min & Max "N" Values:
Output Freq. Range ITO) ~ 98.8 to 118.6 MHz
Channel Spacing Freq. (fel ~ 200 kHz
Division Factor (k) ~ 40
Reference Freq. (fr)
fkMax.
~
118.6 MHz
40
~
2.965 MHz; fkMin
fc
200
~ k~40
~
kHz
98.8 MHz
-4-0--
~
~
5 kHz
2.47 MHz
N~!g
fe
NMax ~
118.6 MHz
200 kHz ~ 593
NMin
98.8 MHz
200 kHz
494
2.56 MHz
5 kHz
R~---~512
Fig. 14 shows a BCD-switch compatible arrangement suitable for + 8 and + 5 modes,
which can be adapted, with slight changes,
to the other divide-by-modes. In order to be
able to preset to any number from three to
about 256,000, while preserving the BCD·
switch compatible character of the jam in·
puts, a rather complex cascading scheme is
required. Such a cascading scheme is neces·
sary because the CD4059A can never be pre·
set to a count less than 3 and logic is needed
to detect the condition that one of the num·
bers to be preset in the CD4059A is rather
small. In order to simplify the detection
logic, only that condition is detected where
the jam inputs to terminals 6, 7, and 9 would
be low during one count. If such a condition
is detected, and if at least 1 is expected to be
jammed into the MSB counter, the detection
logic removes one from the number to be
jammed into the MSB counter (with a place
value of 2000 times the divide·by·mode) and
jams the same 2000 into the CD4059A by
forcing terminals 6, 7, and 9 high.
The clock of the CD4013A may be driven
directly from the output of the CD4059A,
as shown by dashed option (1). or by the
inverted output of the CD4059A, option (2).
If option (2) is used the CD4029A cannot
count cycles shorter than 3. If option (1) is
used propagation delay problems may occur
at high counting speeds.
The general circuit in Fig.14 can be simpli·
fied considerably if the range of the cas·
caded counters does not have to start at a
very low value. Fig.15 shows an arrange·
ment in the + 4 mode, where the counting
range extends in a BCD·switch compatible
manner from 88,003 to 103,999. The arrangement shown in Fig.15 is easy to follow;
once during each cycle, the less significant
digits are jammed in (14,712 in this easel
and then 11,000 (4 x 2750) is jammed in
eight times in succession, by forcing jam inputs high or low, as required.
Numbers larger than the extended counter
range can also be produced by cascading
the CD4059A with some other counting
device. Fig.16 shows such an arrangement
where. only one fixed divide·by number is
desired which is close to three times the extended counter range as shown in the last
column of Table 1.. The dual flip·flop wired
to produce a + 3 count, can be replaced by
other counters such as the CD4029, CD4510,
CD4516,CD4017,ortheCD4022. In Fig.16
the + N subsystem is preset once to a number
smaller than the desired divide-by number.
This smaller number represents the less significant digits of the divide-by number. The
subsystem is then preset one or more times
to a round number (e.g. 1000, 2000) and
multiplied by the number of the divide-by
mode (+ 2 in the example of Fig.161. I t is
important that the second counting device
has an output that is high or low, as the
case may be, during only one of its counting
states.
569
CD4059A Types
21 + N
Count~r Configuration for UH F - 220 to 400 MHz
Channel Spacing: 50 kHz or 25 kHz
..
HL._~_4_
"10,
100 kHz
50/25 kHz
NMax
=
NMin =
400 MHz
25 kHz
10MHz
1 MHz
= 16,000
NMax
400 MHz
50 kHz
=
100 MHz
= 8,000
220 MHz
NMin = 50 kHz = 4,400
220 MHz
25 kHz = 8,800
31 + N Counter Configuration to VHF - 116 MHz
Channel Spacing = 12.5 kHz
~
., 8
12.5' kHz
H
H
"10
100 kHz
160 MHz
NMax
= 12.5 kHz
-IH
25.kHz
"10
80 MHz
NMax
H
100 kHz
= 25 kHz = 3,200
+ 10
1 MHz
H
1 MHz
12,800
41 + N Counter Configuration for VH F - 30 to 80 MHz
Channel Spacing: 25 kHz
4
--1L...-+_
"10
H
" 10
~-i
10 MHz
116 MHz
NMin
= 12.5 kHz = 9,300
51 + N Counter Configuration for AM - 995 to 2055 kHz
Channel Spacing = 10 kHz
"10
10MHz
30MHz
NMin = 25 kHz = 1200
--1
"10
10 kHz
H
+10
100 kHz
2055 kHz
NMax = . 10 kHz = 205
Fig. 14 - BCD switch~ompBtibJe +N system of the most general kind.
570
" 2
100 MHz
H
"10
1 MHz
CD4059A Types
Vss
Vss
VCO
Voo
I Voo
"nD
"no
Fig. 15 - Dividing by any number from 88.003 to 103.999.
VDD
2.
23
••
"
20
10
"
12
Fig.16- Division by 47,690 in +2 mode.
19
I.
17
I.
IS
I.
"
Fig. 17 - Quiescent device
current test circuit.
VDD
FCL
24
23
2.
21
l-CL
20
I.
I.
17
I.
10
"
IZ
..
"
I.
VDO
Fig. 19 - Power dissipation
Fig. IS - Noise immunity
test circuit.
test circuit
'all ..;. modes).
Fig.20 - Input leakage current test circuit.
571
CD4059A Types
*C,N
0---1 f--.__-+--'->,
0.02 TO
0.1 p.F
IN914
100 kl1
TO
I Mil
OR
EQUIVALENT
TO
C04059
CRI
PIN I
ICLOCK)
0.0001 p.F
TO
0.001 p.F
'-------+~~N C,~i~~
* DEPENDS
UPON 1100
VOLTAGE
For changing from any mode other than mode 5
(with power on). apply positive pulse to C'n. This
circuit automatically selects master preset mode
(K. = 0, Kc = 0) before going into the select conditions for mode 5 (K. = 1, K. = 0, K = 1). The
selection of C, and C2 is critical. C, is determined
by the VDD voltage--the lower VDD's need larger
C,'s. C2 must be 0.1 JlF or larger.
92C5-33102
Fig.21 - CD4059A mode 5 power on master preset circuit.
20
141-155
801r.1h.f:''-'--~''f'",""~~!...;,ib-+--;c;r.=iir'"7'''H 13734-3.931)
The photographs and dimensions represent
a chip when it is part of the wafer. When the
wafer is cut into chipsl the cleavage angles
are 57° instead of 90° with respect to the
face of the chip. Therefore, the isolated
chip is actually 7 mils (0. 17 mm) larger
in both dimensions.
.: ~:~ 8., ~ "'._"....,
1---------"(3.
Dimensions j,.. parentheses are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (1tr3 inch).
Dimensions and pad layout for CD4059AH.
572
CD4060A Types
COS/MOS 14-Stage Ripple-Carry
Binary Counter/Divider and Oscillator
The RCA·CD4060A consists of an oscillator
section and 14 ripple·carry binary counter
stages. The oscillator configuration allows
design of either RC or crystal oscillator
circuits. A RESET input is provided which
resets the counter to the all·O's state and
disables the oscillator. A high level on the
RESET line accomplishes the reset function.
All counter stages are master·slave flip·flops.
The state of the counter is advanced one
step in binary order on the negative transi·
tion of ¢I (¢O).AII inputs and outputs are
fully buffered.
These types are supplied in 16-lead hermetic
dual-in-line ceramic packages (0 and F
suffixes), 16-lead dual-in-line plastic package (E suffix). 16-lead ceramic flat packageu
(K suffix), and in chip form (H suffix).
Features:
•
•
•
•
•
•
4·MHz operating frequency (typ.) at VDD -VSS = 10 V
Common reset
Fully static operation
10 buffered outputs available
Quiescent current specified to 15 V
Maximum input leakage current of 1 pA
at 15 V (full package·temperature range)
• 1·V noise margin (full package·temper'
ature range)
CD4060A
FUNCTIONAL DIAGRAM
Oscillator Features:
• All active components on chip
• RC or crystal oscillator configuration
AMBIENT TEMPERATURE (TAl •
Z~·C
TYPICAL. TEMP. COEFFICIENT AT ALL VALUES OF VGS·-Q,3"1.I"C
Applications:
ATE-lO-SOURCE VOLTAGE (vG
l'l~v
• Timers
• Frequency dividers
MAXIMUM RATINGS, Absolute-Maximum Values:
STORAGE·TEMPERATURE RANGE (Tstg ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to +150 oC
OPERATING·TEMPERATURE RANGE (TA):
PACKAGE TYPES 0, F, H
. . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . •-55 to +125 0 C
PACKAGE TYPE E
. . . . • • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . -40 to +85 0 C
!i
1 ~
101l!i
l!i
CRAIN - TO - SOURCE VOLTAGE (VoSI-v
DC SUPPLY·VOL TAGE RANGE: IVDD)
(Voltages referenced to VSS Terminal): . . • . . . . . . . . . . . . . . . • . . . . . . . . . . . -0.5 to +15 V
POWER DISSIPATION PER PACKAGE (PO)
FOR TA=-40to+60oC (PACKAGE TYPE E)
. . . . . • • . . . . . . . . • . . . . . . . . • . . • 500mW
FOR TA= +60 to +85 0 C (PACKAGE TYPE' E)
. . . . . . . . .Derate Linearly at 12 mW/oC to 200 mW
o
FOR TA= -55 to +100 C (PACKAGE TYPES 0, F)
. . . . . . . . • . . . . • . . . . . . . . • . 500 mW
0
FOR TA= +100 to +125 C (PACKAGE TYPES 0, F)
. • . . . Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA= FULL PACKAGE·TEMPERATURE RANGE (ALL PACKAGE TYPES) . . • . . . . . . 100 mW
INPUT VOLTAGE RANGE, ALL INPUTS . . • . . . . . • . . . . • . . . . . . . . . . . . -0.5 to VDD +0.5 V
LEAD TEMPERATURE lOURING SOLDERING):
At distance 1/16 ± 1/32 inch 11.59 ±O.79 mm) from case for 105 max . . . . . ~. . . . . . . . . . . +26S oC
CHARACTERISTIC
3.1!i
Z.!i
1.~
10
!l.S
I~
Fig. 2 - Minimum n·channel drain characteristics.
Package
.,
DFiAIN-TO-SOLRCE VOLTAGE (Vosl-v
Max.
Min.
Max.
3
12
3
12
V
Supply·Voltage Range (For T A = Full
Package· Temperature Range)
Input·Pulse Width, tw
f= 100 kHz
5
10
400
110
-
500
125
-
ns
Input·Pulse Rise & Fall
Time, t r¢ , tf¢
5
10
-
15
1.5
-
15
1.5
fJS
Input·Pulse Frequency, f¢
5
10
-
1
-
3
-
0.9
2.15
MHz
5
10
1000
500
-
1250
600
-
ns
Reset Pulse Width, tw
a
z
~
UNITS
Min.
-
1·ISV
DRAIN - TO - SOURCE VOLTAGE IVosl-9~CS'~I~I~
E
Packages
ATE-TO-SOURCEVOLTAGEI'v:
~
LIMITS
D,F,H
AMBIENT TEMPERATURE ITAI- 2S'C
TYPICAl.. TEMP. COEffICIENT AT ALL VALUES Of VOS' ·0.3"t.I·C
'"
RECOMMENDED OPERATING CONDITIONS at TA = 25°C, Except as Noted.
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges:
VDD
(V)
Fig. 1 - Typical n·channel drain characteristics.
3
-10 _
GATE-TO-S~~ VOLTAGE (VG I'ISV
1
•
AMBIENT TOIPERATURE \TAl' 2~'C
TYPICAL TEMP COEfFICIENT AT ALL VALUES OF "GS··0.3"1oI'C
Fig. 3 - Typical p·channel drain characteristics.
573
CD4060A Types
STATIC ELECTRICAL CHARACTERISTICS
DA.lIN-TO-SClUAC[ VOLTAGE IVOSI-V
Limits at Indicated Temperatures (oCI
Conditions
D,F,H Packages
+25
Vo VIN VOO
-55
+125
(VI (VI (VI
Typ. Limit
Characteristic
Qu iescent Oev ice
Current I L Max.
-
-
Package
Units
+25
-40
+85
Typ. Limit
E
-
5
10
15
25
0.5
1
15
25
900
1500
50
100
1
2
-
15
50
2.5
50
2000
500
5
5
5
-
10
10
o Typ.; 0.05 Max.
o Typ.; 0.05 Max.
-
0
0
5
10
4.95 Min.; 5 Typ.
9.95 Min.; 10 Typ.
Noise Immunity:
Inputs Low,
VNL
Inputs High
VNH
4.2
-
5
1.5 Min.; 2.25 Typ.
9
10
3 Min.; 4.5 Typ.
0.8
-
1.5 Min.; 2.25 Typ.
10
-
5
10
3 Min.; 4.5 Typ.
Noise Margin:
Inputs Low.
VNML
Inputs High,
VNMH
4.5
-
5
1 Min.
9
-
10
1 Min.
0.5
1
-
5
10
1 Min.
1 Min.
0.5
-
5
0.5
-
10
4.5
-
5
9.5
-
10
Output Voltage:
Low Level,
VOL
High Level
VOH
Output Drive
Current:'
n·Channel
(Sink),
ION Min.
50 700
100 1400 p.A
500 5000
'0'
GATE -TO-Sot.RCE VOLTAGE I
'-':lV
-7.$
AMBIENT aMPERATURE ITA) -Z!I-t
TYPICAL TEMP. COEl"FICENT AT ALL VAUIES OF VGS.-o.,.,..,·c
V
Fig. 4 1- Minimum p-chsnnel drain characteristics.
V
V
LOAD CAPACITANCE (CLI- ,F
p·Channel
(Source),
lOP Min.
Input Leakage
Current,
IIL,IIH
0.22 0.36
0.18
0.125 0.21 0.36 0.18 0.15
0.44 0.75
0.36
0.25
0.42 0.75 0.36
0.3
Fig. 5 - Typical propBflBtion delay time VI. load
capscitanCIJ (1/>1 to 04 output).
mA
·0.15 ·0.25 ·0.125 ·0.085 ·0.145 ·0.25 .().125 -0.1
·0.3
_Ar~np~
·0.5
-0.25 -0.175 -0.29 -0.5 -0.25 -0.2
±10-5 Typ., ±1 Max.
/lA
* Data not applicable to Terminal 9 or 10
Fig. 6 j- Typical proPBflBtion delay time
V$.
load
capacitance (On to 0n+I)'
OUTPUT BUFFER,STAGES
~~~2-14
OSCIL~ATOR
;:,gu
I
:
)
~~~~~~H>-~
OJ
;j
STAGE I
• R"HIGH DOMINATES IRESETS ALL STAGES)
• COUNTER ADVANCES ONE BINARY COUNT
ON EACH NEGATIVE -GOING TRANSITION
OF ~II'ND ~O)
Fig. 7
574
INPUTS
TO 2nd
"£l
92CS-23763RI
VSS
INPUT PROTECTION
CIRCUIT ON ALL
INPUTS
J- Logic diagram of CD4060A oscillator, pulse shaper, and 1 of 14 counter stages.
AMIIENT nIFUATURE (T... I. H-C
"'"
:\.~"
}2!1O
~200
r
..,~
~ '00
•
~
~
lm~"'fm
I
f!!:.1
..I~
100 :
00
0
"
:
20
40
60
lOAD CAPACITANCE tel I - pF
80
HI
92CS-2~$!III
Fig. 8 - Typical output transition tims vs. load
capacitance.
CD4060A Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C. Input t r • tf = 20 ns.
CL = 15 pF. RL = 200
kn
LIMITS
TEST
CONDITIONS
CHARACTERISTIC
D,F,H
Packages
E
UNITS
Package
VDD
(V) Min. Typ. Max. Min. ,Typ. Max.
Input-Pulse Operation
10
Propagation Delay
Time. tfJl to 04 Out;
tpHL. tpLH
Propagation Delay
Time. an to 0n+l;
tpHL. tpLH
900
1800
-
900
1900
450
900
450
950
5
-
450
900
450
950
10
225
450
225
475
150
300
-
150
350
10
-
-
75
150
-
75
175
200
500
75
125
15
7.5
10
Transition Time,
tTHL.tTLH
5
Min. Input-Pulse
Width tw
f=100 kHz
Input-Pulse Rise & Fall
Time. trcp. tftfJ
Max. Input-Pulse
Frequency. ftfJ
Input Capacitance. CI
5
-
200
400
10
-
75
110
5
-
15
10
-
-
7.5
-
-
5
1
1.75
0.9
1.75
-
10
3
4
2.75
4
-
5
-
-
5
-
Any Input
Il5
SUPPLY VOLTAGE IVeo) -
-
5
ns
v
zo
Fig. 9 - Typical maximum-;nput-pulse frequency
v.s. supply voltage.
ns
ns
ns
p.s
~
MHz
pF
10
LOAD CAPACITANCE
- - - - Cl '~OpF
10 2
IO!
INPUT FREQUENC,\, "+I-kHZ
CCLI'I~pF
104
Fig. 10 - Typical dynamic power dissipation
characteristics.
Reset Operation
Propagation Delay
Time.tpHL
Minimum Reset
Pulse Width. tw
5
-
500 1000
1250
250
500
250
600
5
-
-
500
10
500
1000
-
500
1250
10
-
250
500
-
250
600
~
VDD-::::UTO'"
v~
VS5
Fig. 12 -
~
ns
V~NPU(J'
... ~;:
Vss
.
TEST PERFORMED
WITH UNIT IN ALL
Vss
.. 0· ... STATE AND
ALL "I's" STATE
AND INPUTS AT 10 V
AND GROUND
INPUTS
Fig. 11- Quiescent-device current test circuit.
TO 80TH Vco AND V5S·
COttNECT ALL UNUSED
INPUTS TO EITHER
NOTE:
TEST ANY ONE INPUT,
WITH OTHER INPUTS AT
92CS.21400 Voo ORVss·
Noise-immunity test circuit.
ns
VDO OR V5S·
Vss
F~g.
13 - Input-!eakage-current test circuit.
575
CD4062A Types
COS/MOS 200-Stage Dynamic Shift Register
MAXIMUM RATINGS. Absolute-Maximum Values:
STORAGE-TEMPERATURE RANGE (T,tg) ..•...••••• __ . . . . • • . . • . . .. -65 to +150° C
OPERATING-TEMPERATURE flANGE (TA):
PACKAGE TYPES: T, If.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -55 to +125° C
DC SUPPLY-VOLTAGE RANGE, (VDD)
(Voltages referenced to VSS Terminal): . . . . . . . . . . . . . . . . . . . . • .' . . . . . .. -0.5 to +15 V
POWER DISSIPATION PER PACKAGE (PO)
500mW
FOR TA = -55 to +100° C (PACKAGE TYPES Tl
FOR T A = +100 to +125' C (PACKAGE TYPES Tl. .. Derate Linearly at 12 mWf C to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (ALL PACKAGE TYPESI ....... 100 mW
INPUT VOLTAGE RANGE, ALL INPUTS . . . . . . . . . . • . . . . . . . . . . . . . . . -0.5 to VD D +0.5 V
LEAD TEMPERATURE (DURING SOLDERING):
+265' C
At distance 1116.1/32 inch (1.59 ± 0.79 mml from case for 10 s max.
,----STAGEt~
r-STAGE200~
CL(bl
__
OUTPUT
~BUFFER---"
CLIo)
'
~
fG
Q
TG
. '
~~
2
UlbJ
B'I' COSINOS
4(4)
PROTECTION NETWORK
4
"TERMINAL NUMBERS IN
PARENTHESES REFER TO
12-LEAO TO-5 STYlE
PACKAGE
CD4062A
CLlol
• TRANSMISSION GATE
INPUT TO OUTPUT IS
JI ALL INPUTS ARE PROTECTED
REt PRECIRe
2
(alA BIDIRECTIONAL L.OW IMPEDANCE·WHEN CONTROL INPUT
Is MLOWft AND CONTROL INPUT 2 IS 'HIGH"
11191·
V55
I-PHASE
CLOCK
C
LI
0-------+ CLZ
5151
CLOCK~M
MODE ~(lil
92C5-24664
CD4062A
FUNCTIONAL DIAGRAM
The RCA-CD4062A is a 200-stage dynamic
shift register with provision for either singleor two-phase clock input signals. Singlephase-clocked operation is intended for lowpower. low clock-line capacitance requirements. Si ngle·phase clocking is specified for
medium-speed operation « 1 M Hz) at supply voltages up to 10 volts. Clock input capacitance is extremely low « 5 pF), and
clock rise and fall times are non-critical. The
clock·mode signal (CM) must be low for
single-phase operation.
CM
The logic level present at the data input is
transferred into the first stage and shifted
one stage at each positive-going clock transition for single-phase operation. and at the
positive-going transition of Cll for two-phase
operation.
e.
The CD4062A-Series types are supplied in
l2-lead hermetic TO-5 packages (T suffix),
l6-lead ceramic flat packages (K suffix).
and in chip form (H suffix).
"ALL INPU"IS ARE PROTECTED
BY COS',",OS
PROTECTION NETWORK
4
CLIO
CL20
Two-phase clock-input signals may be used
for high-speed operation (up to 5 MHz) or to
further reduce clock rise and fall time requirements at low speeds. Two-phase operation is specified for supply voltages up to 15
volts. Clock input capacitance is only 50 pFI
phase. The clock-mode signal (CM) must be
high for two-phase operation. The singlephase·clock input has an internal pull-down
device which is activated when CM is high
and may be left unconnected in two-phase
operation.
CONTROL INPUT 2 IS "L.OW"
CL (b}'INTERNAL. CLOCK IN PHASE WITH elz
(INPUT TO
TERMINAL I)
CLOCI(
........-...--.-..-'
(b) AN OPEN CIRCUIT WHEN CONTROL INPUT I IS "HIGH" AND
CL (0)' INTERNAL. CLOCK IN PHASE WITH CL I
Fig. I - CD4062A logic block diagram.
2-~HASE 0-----+
RC
REC _
Features:
•
Minimum shift rates over full temperature range-
V55
Single-phase clock: 3 V';;; VOD';;; 10 V;
fmin = 10 kHz; _55° C';;; TA';;; +125° C
Cl lal • INTERNAL CLOCK IN PHASE WITH ell
CL (b) • INTERNAL CLOCK IN PHASE WITH CLZ
(fmin = 1 kHz up to TA ';;;7S0C)
.. TERMINAL NUI,lBERS IN
PARENTHESES REFER TO
12-LEAD TO-5 STYLE
PACI(AGE
r--
eM
Fig. 2 - Clock circuit logic diagram.
92CM-UTOOR2
Two-phase clock: 3 V .;;; VDD .;;; 15 V;
fmin = 10 kHz; _55° C';;; TA';;; +125° C
(f min=1 kHz up to TA';;;75°C)
576 __________________________________________________________________
CD4062A Types
RECOMMENDED OPERATING CONDITIONS at TA = 25' C, Except as Noted.
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges:
CHARACTERISTIC
LIMITS
VDD
(VI
.
Clock Input Frequency,
fCl
Clock Pulse Width, tw
MAX.
3
3
10
12
0.15
0.15
5
10
.
UNITS
MIN.
Supply·Voltage Range (For TA = Full
Package·Temperature Range):
Single. Phase Clock
Two·Phase Clock
5
10
250
500
Clock Rise or Fall Times,
trCL or tfCl'
5
10
-
Data Hold Time, tH'
5
10
150
50
Features (Cont'd):
V
500
1000
kHz
66.7 X 10'
66.7 X 10'
TEST CONDITIONS
ns
10
1
IlS
-
ns
LIMITS
r-:-:----1----,--,----1 UNITS
CHARACTERISTIC
VDD
V
Maximum Clock Input Frequency. tCl
5
TYP. MAX.
1.25
2.5-
2.5
5
•
•
•
•
Serial shift registers
Time-delay circuits
CRT refresh memory
Long serial memory
~---r---~----+---~MHz
10
Minimum Clock Input Frequency, tCL
MIN.
• Low power dissipation
0.3 mW/bit at 1 MHz and 10 V
0.04 mW/bit at 0.5 MHz and 5V
(alternating 1-0 data pattern)
• Data output TTL-DTL compatible
• Recirculating capability
• Delayed two-phase clock outputs available for cascading registers
• Asynchronous ripple-type presettable to
all l's or O's
• Ultra-Iow-power-dissipation standby operation
• Quiescent current specified to 15 V
• Maximum input leakage current of 1 IlA
at 15 V (full package-temperature range)
• 1-V noise margin (full package-temperaturerange)
5·
150
10
10
150
10
~----r---~----+----;
Hz
Clock Overlap Ti.:;m"'e'-_ _ _~
9f1'1o)
el2 - - J
\ -90%
. '--
L
Cl 1
tdl
-
ns
40
lf1'1o~r--
X-DATA SET-UP TIME
' ...
HIGH TO LOW
I----- td2
Y-OATA HOLD TIME
Z~DATA
SET -up TIME
LOW TO HIGH
Average Input Capacitance, C1
Cll. Cl2
92CS-22702RI
pF
50
-
250
500
Fig, 3 - Timing diagram-single1Jhase clock •.
Propagation Delays; tpH l' tplH
Cl 1 to Q
5
-
10
-
100
200
Cl 1 to Cl1D
5
-
250
500
Cl2 to Cl2D
10
-
100
200
5
-
150
300
10
-
50
100
--:----__------------------~------_t--~_t----~~_1~~ns
Minimum Data Setup Time,
tS~
... 1
r-----+-----+---~--~ns
D
5
-
-
0
10
-
-
0
1-----+-----+----1"--- ns
Clock Rise and Fall Times
trCll' Cl2
tfCll' Cl2
No Restrictions It
Clock Overlap Require'
ment Is Met
Q DELAYED 200 CLOCK PULSES
MIN tw(CL,l,lwICL2)-20ns
92CS-22103
Fig. 4 - Timing diagram-two-phas8 clock.
________________~----------------__-------------------------577
CD4062A Types
STATIC ELECTRICAL CHARACTERISTICS
AMBIENT TE'MPERATURE tTAI·ZS·C
TYPICAL TEMPERATURE COEFFICIENT IS -O.3"1""·C
AT ALL VALUES OF YGS
i'.1 .
LIMITS AT INDICATED
CONDITIONS
CHARACTERISTICS
12
-
-
10
25
15
50
-
5
5
-
10
10
'Oy
10
DRAIN-ro-souftCE VOlTAGE 1'1051-'1
o Typ.; 0.05 Max
oTyp.; 0.05 Max
Fig.
o output.
-
0
5
4.95 Min.; 5 Typ.
0
10
9.95 Min.; 10 Typ.
4.2
-
5
1.5 Min.; 2.25 Typ.
VNL
9
-
10
Inputs High
o.s
5
VNH
1
4.5
9
Inputs High,
V NMH
0.5
1
5- Typical n~hannel drain characterstics for
v
-
Noise Margin:
Inputs Low,
V NML
Ii
,y
p.A
High Level
-
t.VOL
l'lGslo,SV
5
VOH
Noise Immunity:
Inputs Low,
I
~ATE-TO-SOURC~ ~*
TYP. LIMIT
-
I
P
1"5:....---1+125
-55 1--+2
-
VOL
TEMPERATURES 1°C)
1--,--.---+....:....-,----....---1 UNITS
Vo V IN V DD
IV) IV) IV)
Output Voltage:
Low Level,
'I
ill::
DRAIN-TO-SOURCE VOLTSIVOSI
-5
-10
o
-5
°
·'0
3 Min.; 4.5 Typ.
V
1.5 Min.; 2.25 Typ.
10
3 Min.; 4.5 Typ.
-
5
1 Min.
-
10
1 Min.
5
1 Min.
10
1 Min.
.,.
AMBIENT TEMPERATURE I TAJo 25-C
TYPICAL TJ-MPERATURE COEFFICIENT
FOR ALL VALUES Of' '10 -·o.3%/ec:
V
Fig.
6-·
TYpical p-channel drain characteristics for
o output.
Output Drive
Current:
N·Channel
(Sink),
AMBIENT TEMPERATURE ITA ,- 2S"C
TYPICAL. TEMPERATURE COEFFICENT FOR
AU VALUES OF "OO'O.3""/"'C
IDNMin
Q
0.4
4.5
1.6
2.6
Output
0.5
10
5
s*
4
3.2
Cll0'
CL2D
P·Channel
(Source):
1.3
0.91
0.5
-
5
0.87
1.4
0.7
0.49
0.5
-
10
2.2
3.6
1.8
1.26
5
-0.31
-0.5
5
-0.93 -1.5
-0.75 -0.52
-0.87
-0.7
mA
r--;--+--+--+--r--~--i
.
10
4.5
Q
2.5
Output
9.5
IDPMin.
-
10
-1.4
ZO.
.
-0.25 -0.17
..
,.y
,
,.
..
90
Q
OUTPUT IS SIGNIFICANTLY LESS THAN ITLH
Fig. 7- Typical transition time VS'.
mA
eL for data outputs.
-0.49
-0.35 -0.24
-0.9
-0.63
Input Leakage
Current,
±10-5 Typ., ±1 Max.
IIL,IIH
* Maximum power dissipation rating
p.A
~ 200 mW.
.•
Fig.
LOAO CAPACITANCE lell-pF
8- Typical trl!nsition time
delayed clock ·outp'ut.
578
'00
'1~!;5-2"6S5
LOAD CAPACITANCE·iCL1-pF
NOTE Int.f"OR
tIS.
CL for
CD4062A Types
DYNAMIC CHARACTERISTICS AT TA =25· C. Vss =0 V. Cl =50 pF.lnput t r• tf
except trCl and tfCl
=20 ns.
Singla·Phase-Clock Operation: Clock Mode (CM) = low: 3 V ... VDD ... 10 V (See Figure 3)
TEST CONDITIONS
CHARACTERISTIC
VDD
V
Maximum Clock Input Frequency. fCl
tr. tf=20 ns
(50% Duty Cycle)
Minimum Clock Input Frequencv. fCl
(50% Duty Cycle)
.
MIN.
5
LIMITS
0.5
1
10
1
2
5
150
10
10
150
10
5
-
-
10
-
-
All Inputs Except
Cll and Cl2
-
Clock Rise and Fall Times"
trCl.tfCl
UNITS
TYP. MAX.
-
MHz
-
Hz
10
1
"
• '10.
,
" . 'IO!!
:t
...
8 10,
CLOCK 'REQUENCY "CLI- HI
Fig. 9- Typical pOwer dissipation vs. frequency.
lis
S'"GlE PHASE CLOCK
Average Input Capacitance. Cl
Propagation Delays:
5
CltoQ
Cl to CLIO
(50% Points)
~
CllD~
Cl to Cl2D (Positive Going)
C~
(50% Points
-
1000 2000
5
-
750 1500
10
-
300
5
-
500 1000
10
(Positive Going)
-
5
400
800
ns
600
I
10
-
200
400
5
-
450
900
10
-
175
350
Cl2D~
,0
-75
(50% Points)
Cl~
-2!
v
ANBIENT TUiIPERATURE
ns
/
Cl to Cl2D (Negative Going)
Cl~
Cl2D ~
(50% Points)
Transition Time: t TlH • tTHl
QDutput
CllD.CL2D
5
-
750 1500
10
-
300
600
200
5
-
100
10
-
50
100
5
-
200
400
100
200
5
-
10
-
10
";:EJ
ts
Cl
-
0
0
000
n,,)-·c
WIS.
ambient
temperature.
'00
'00
~
ns
INPUTS
Vss
Fig. 11- Quie.cent'fleonce-current
test circuit.
Voo
ns
3,5V OR 7V
1·50R3V -0
D
150
5
-aata Hold Time
:H~
-50
Fig. 70- Minimum shift frequency
Cl to CLIO (Negative Going) .
CLIO
TWO PHASE CLOCK
pF
10
I
-
-
150
ns
•• If more than one unit IS clISCoclad In slnglel'ha.. parallel clocked applicatIon. trCl should be made less than
or equal to the sum of the propagation delay at 15 pF. and the transition time of the output driving stage.
(See Figs. 5 and 7 for cascading options.)
... Use of clalayed clock permits highofPOOd logiC to preceda CD4062A register (s.. cascade register operation).
Fig. 12- Noi.e';mmuniry te.t
circuit.
Voo
92CS-22693
Fig. 13-lnpuHeakage-current
test circuit.
C04062AT
TERMINAL DIAGRAM
579
CD4066A Types
COS/MOS Quad Bilateral Switch
For Transmission or Multiplexing of Analog or Digital Signals
RCA C04066A is a quad bilateral switch
intended for the transmission or multiplexing of analog or digital signals. It is pin-forpin compatible with RCA-C04016, but exhibits a much lower ON resistance. In addition, the ON resistance is relatively constant
over the full input-signal range.
The CD4066A consists of four independent
bilateral switches. A single control signal is
required per switch. Both the p and the n
device in a given switch are biased ON or
OFF simultaneously by the control signal. As
shown in Fig. 1, the well of the n-channel
device on each switch is either tied to the
input when the switch is ON or to VSS when
the switch is OFF. This configuration eliminates the variation of the switch-transistor
threshold voltage with input signal, and thus
keeps the ON resistance low over the full
operating-signal range.
The advantages over single-channel switches
include peak input-signal voltage swings
equal to the full supply voltage, and more
constant ON impedance over the inputsignal range. For sample-and-hold applications, however, the C04016is recommended.
These types are supplied in 14-lead hermetic
dual-in-line ceramic packages (0 and F
sufflxesl. 14-lead dual-in-line plastic package (E suffix), 14-lead ceramic flat package
(K suffix), and in chip form (H suffix).
Features:
• 15-V digital or ± 7.5-V peak-to-peak switching
• 800 typical ON resistance for 15-V operation
• Switch ON resistance matched to within 5 0 over 15-V
signal-input range
• ON resistance flat over full peak-to-peak
signal range
• High ON/OFF output-voltage ratio: 65 dB
typ.@fis= 10 kHz, RL = 10 kO
• High degree of linearity: < 0.5% distorCD4066A
FUNCTIONAL DIAGRAM
tion typo @ fis = 1 kHz, Vis = 5 Vp _p,
VDD-VS~ 10 V, RL = 10 kO
• Extremely low OFF switch leakage resulting in very low offset current and high
effective 0 F F resistance: 10 pA typo @
VDD-VSS = 10 V, T = 25°C
• Extremely high control input impedance
(control circuit isolated from signal
circuit!: 10 12 0 typo
• Low crosstalk between switches: -50 dB
typ.@fis = 0.9 MHz, RL = 1 kO
NORMAL OPERATION
• Matched control-input to signal-output CONTROL-LINE BIASING:
SWITCH ON,Vc·t-"'OD
capacitance: Reduces output signal SWITCH OFF'~.vc~o"avss
VOO
transients
* ALL CONTROL INPUTS
• Frequency response, switch ON = 40 MHz
ARE PROTECTED BY
COSIMOS PROTECTION
(typ.)
NETWORK
• Quiescent current specified to 15-V
92CS-2162BR2
• Maximum control input leakage current
of l-IIA at 15-V (Full packagevSS
temperature range)
Fig. , - Schematic diagram of , of 4 identical
A
--
. switchessnd its assOciated control circuitry.
MAXIMUM RATINGS, Absolute-Maximum Values:
STORAGE TEMPERATURE RANGE ITstg ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to +125°C
OPERATING TEMPERATURE RANGE ITA':
SPECIAL CONSIDERATIONS - CD4066A
1. In applications where separate power
sources are used to drive VOO and the
signal inputs, the VDD current capability
should exceed VDO/R L (R L = effective
external load of the 4 C04066A bilateral
switchesl. This provision avoids any
permanent current flow or clamp action
on the VDD supply when power is applied
or removed from CD4066A.
2. In certain applications, the externalload·
resistor current may include both VDD
and signal-line components. To avoid
drawing VDD current when switch current flows into terminals 1, 4, 8, or 11,
the voltage drop across the bidirectional
switch. must not exceed 0.8 volt (calculated from RON values shownl.
PACKAGE TYPES 0, F, K, H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to +125°C
PACKAGE TYPE
E
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40 to +85°C
DC SUPPLY VOLTAGE RANGE, V DD
(Voltages referenced to V55) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +15 V
INPUT CURRENT ITRANSMISSION GATE INCL.) . . . . . . . . . . . . . , . . . . . . , . . . . . . . ±10 mA
POWER DISSIPATION PER PACKAGE:
FOR T A = -40 to +60°C (PACKAGE TYPE E I
"
FOR T A = +60 to +85" C (PACKAGE TYPE E)
Derate Linearly at 12
. . . . . . . . . . . . . . . . . . . . ','
500mW
mwroc ..... .
200mW
................... .
500mW
FOR T A = +100 to +125°C .IPACKAGE TYPES 0, F, K) Derate Linearly at 12 mWloC .. .
DEVICE DISSIPATION PER SECTION:
200mW
FOR T A =FULL PACKAGE·TEMPERATURE RANGE IALL PACKAGE TYPES) . . . . . .
100 mW
FOR TA = -55 to +100'C (PACKAGE TYPES 0, F, K)
ALL SIGNAL AND DIGITAL CONTROL INPUTS . . . . . . . . . . . ' . . . . . . . . . . . . VSS" V," V DD
LEAD TEMPERATURE lOURING SOLDERINGI:
At distance 1/16 ± 1/32 inch 11.59 ± 0.79 mm) from case for 10 s max.
+265°C
OPERATING CONDITIONS AT TA = 25°C
For ma~imum reliability, nominal operating conditions should be selected
so that operation is ~Iways within the following ranges
MIN,
MAX,
CHARACTERISTIC
VDD
UNITS
No VDD current will flow through RL
if the switch current flows into terminals
Supply Voltage Range
2,3,9, or 10.
3
12
V
(TA = Full Package Tempera3. Minimum bilateral switch output load
ture Range)
is 100 n.
580resistance
________________________________________________________________
__
-
CD4066A Types
App/ications:
• Analog signal switl:hing/multiplexing
Modulator
Signal gating
Squelch control
Demodulator
Chopper
Commutating switch
• Digital signal switching/Multiplexing
::1:\0
!2
• Transmission-gate logic implementation
• Analog-to-digital & digital-to-analog conversion
• Digital control of frequency, impedance,
phase, and analog-signal gain
AMBIENT TEMPERATURE
~ 300
I
ITAI-2~·C
SUPPLY VOLTAGE
Voo-Vssl- :IV
12~0
200
ELECTRICAL CHARACTERISTICS
0, F. H Packages
Values at -4(fC. +2SoC. +8SoC Apply to E
Package
4re in Volts
V DD
(VI
Ouiescent Device Current, I L max.
O,F, HPkgs.
Pkg.
_40 0
+850
-
5
10
0.25
-
0.5
-
15
2
10
15
o
-8
-
2.5
15
5
30
50
500
+125°
7.5
15
40
-
TYP.
MAX.
0.01
0.01
0.25
0.5
0.02
0.25
2
2.5
0.25
5
0.5
50
4
-2
0
2
4
SIGNAL VOLTAGE IV,,) - VOLTS
Fig. 2 (a) - Typical channel ON resistance VI. signal
voltage for three values of supply volt-
age (VDD-VSS)'
~A
~
~A
i§
350 SUPPLY VOLTAGE.
lV oo -VSSI.5V
AMBI NT EMPERATURE!
ITAI 0 12S-C
300
I
~250
SIGNAL INPUTS (Vi.1 AND OUTPUTS (Vo.1
z 200
~
~
VC=
VSS
VOO
-6
UNITS
+250
_55 0
5
E
,1"
Values at _55°C, +2SoC, +12SoC Apply to
AIJ Voltage Values
CHARACTERISTIC
I:lV
LIMITS
TEST
CONDITIDNS
Vis
I!SO
RL"" 10kn·
+7.5
-7.5 to
-7.5
+15
-5
+10
0
+2.5
-5 to
+5
Oto
+10
300
320
80
280
o
-8
+2.5
o to
0
400
450
520
550
120
500
3000
3500
5200
5500
270
5000
Fig. 2 (b) - Typical channel ON resistance vs. signal
voltage with supply volrage (VDDVSS)~5V.
.aON Resistance Between
Any 2 of 4 Switches,
to RO~
J.
-I
+15
+5
+10
0
+5 to
-5
0
~
0
5V
p.p
.
-5
RL = 10kn
5300
I
~2!50
.,
-
-
-
-
5
~200
~
n
-5
-
-
-
10
~
o
-
-
-
-
0.4
-
-8
-5
20 log 1a
VSs)~
-
-
-
-
40
-
i
I
+7.5
-7.5
+5
-5
VC(AI=VOO=+5
VCIBI=VSS= -5
RL = 1kn
rntlI
•
1 250 ~
-
-
-
1.25
-
MHz
±7.S
-
-
±5
-
-
(AI
5V
p.p
'----
20109,0 V os(BI =-5OdB
VjslA)
-
-
:to. 1
±100"
-
±O.l
±lOO·
:.
.,~
it
200
::1~
150
~
VC=
VSS
3:10 SUPPLY VOLTAGE tVoo-VSSl·15V
o 300
-
IOV.
MHz
-5 pop
~~::: -SOda
VI. signal
voltage with supply voltage (VOD-
Vis
VOO
-4
0
2:
4
SIGNAL VOL TAGE tv~,1 - VOLTS
Fig. 2 (c) - Typical channel ON resistance
RL - lkn
Feedthrough-Switch OFF
Between Any 2 of the 4
Switches (f at -50 dB)
-6
%
Vis
Crosstalk
50
-5 p.p
Vos
20 log, 0 - = -3dB
I
ITA'.'25·C
o 100
-
RL - lkn
+5
Input or Output Leakage Switch OFF (Effective
OFF Resistance)
AMBIENT TEMPERATURE
~ I~
Z
-
fjs::: 1kHz
+5
Frequency Response
Switch ON
(Sine·Wave Input)
I +15 to
to 0
-5
J.-I
+5
Sine Wave Response
(Distortion)
+7.5 to
-7.5
-7.5
or
SUPPLY VOLTAGE (Voo VSS I.l0V
::I
+5
Rl == 10kn·
+7.5
-4
-2
0
2:
4
SIGNAL VOLTAGE IV,"sl - VOLTS
n
-2.5 to
-2.5
-5
250
Oto
+15
0
ON Resistance, RON Max.
+5
220
+7.5
! ~ tit!!
ii:
r
+~
i
U;
" .t.:...,~
\.s.
Ft~·
i!
I
rt;]
m~
jl
l!!;
.:..c:
nA
-,o
o
2
4
SIGNAL VOLTAGE (Vis' - VOLTS
-
-
-
-
0.9
-
MHz
Fig. 2 (d) - Typical channel ON resistance vs. signal
voltage with supply voltage (VDDVssi ~ 15 V.
581
CD4066A Types
VDD
ELECTRICAL CHARACTERISTICS (Cont'd)
TEST
CONDITIONS
All VoItBgtI Va/UN
Are in Valrs
CHARACTERISTIC
I
V DD
Ivl
LIMITS
V.lues at -55"C, +2SoC. ""26°C Apply 10
0, F, H Packages
Values at
-4Cfc,
+2SoC. +SSoC Apply to E
Package
Propagation Delay (Signal
Input to Signal Output)
I--
Ipd
V OO
= 10
Capacitance:
Input,Cis
Output, Cos
VSS' GNO
7030A
-41)'
-
+85'
+1250
-
-
-
-
-
-
TYP.
MAX.
-
20
50
-
-
10
25
-
-
8
9rcs -22716
Fig. 3 - Channel ON resistance mSlJluremsntcircuit.
CL = 15pF
ns
V is = sq. wave
t r • tf= 20n5
(Input Signall
VOO = +5
VCC' Vss =-5
Feedthrough. C ios
H.P.
MOSELEY
+25'
-55'
VC·VDO
VOO
=5
X-Y
' -_ _....._ _ _--i>--jPLOTTER
UNITS
-
-
8
pF
0.5
CONTROL (VCI
Vis:S;;;V OD
Noise Immunity. VNL
2
'is' I(\:!A
Min.
2
2
2
2min
4.5
-
V
INPUT SIGNAL VOLTAGE 1Vi..1- VOLTS
StCS-23911'
Voo-VSS= 10
Fig. 4 - Typical ON characteristics for , of 4
channels.
Vis"VOD
Input Leakage Current. IlL
.,0- 6
"
VOO -VSS= 15
Max.
VC"V OO -VSS
~A
±1
= 10
~C= 10
Crosstalk
Control Input to
Signal Output
(sq. wave)
tre= t fc
RL = 10kn
R L =300kn
'" 20n5 V is <:10
Propagation Delay. tpdC
~
~ 'r--r--+--r+-r-~r-~~~~
VOO-VSS
-
-
-
-
50
-
mV
-
-
-
-
35
-
ns
-
-
-
-
10
-
MHz
-
-
-
-
5
-
pF
l'O:!F==l=~~~~~p~
CL = 15pF
VOO= 10, VSS=GNO
Maximum Allowable Control
R L =lkn,C L =15pF
Input Repetition Rate
Ivc = 10 (sq. wavel
SICS-lUI!.
,If= 20ns
Av. Input Capacitance, C,
Fig. 5 - Power dissipation per packago ....wi rthing
~EP
frequency.
Vc
• Umit determined by minimum feasible leakage measurement for automatic testing.
IJ. Symmetrical about 0 volts. • For all test conditions.
vc·vss
RATE
I r ·lf·20ns
vDO
Voa90~-1
20
n!:.l~~
Ciol
r----~~-----,
liDO • .. ~V :
: VCR -5V
I
I
I
I
MEASURED ON BOONTON
CAPACITANCE BRIDGE
MOCEI. 75A (I MHz)
TEST FIXTURE CAPACITANCE
NULLED OUT
+IO~
Vss
ALL UNUSED TERMINALS
ARE CONNECTED TO VSS.
lOO"-O
Vc
tr-If·20na
92C5-n9rg
Fig. 7 - OFF .wlrth Input or output leakago.
I
I
*COI
I
All UNUSED INPUTS ARE CONNECTED TO VSS.
?
92cs-n'le
t2es-2"Z'
Fig.
Fig. 6 - Capscitanr:;e t<circuit.
,q - Msxlmum allowable control input repeti'
tion ra&1.
g2eS-2S9!1
ALL UNUSED TERMINALS
ARE CONNECTED TO vss.
Fig. 9 - Cros.talk-control input to .Ignal output.
V~NP(J~" :. ."":.'
TO 10TH ¥aD AND Vss·
CONNECT ALL UNUSED
.....,., TO [ITttER
Vss
300n
VDO ORVSS·
ALL UNUSED INPUTS ARE .CONNECTED TO Vss·
,acS-2:59aORI
Fig. 8 - Propa(JIJtion dBlay time .ignsllnput (Vi'!
. to .ignal output IV
001.
582
Vss
ALL UNUSED TEF(MINALS AftE CONNECTED TO Vss.
12tS-'21!"
92CS-2S922RI
Fig. , , - Pr_tion dBlay tpLH- tpHL controlsignal output.
~~tS:~;.?:TROl
Fig.
'2 -
Input leekago current tnt clrcu, t.
COS/MOS Telecommunications, Display-Driver, and
Interface Circuits
Technical Data
_ _ _ _ _ _ _ _ _ _ _ _ _ 583
CD22100 Types
COS/MOS 4 x 4 Crosspoint
Switch with Control Memory
High-Voltage Types (20-Volt Rating)
The RCA-CD22100 combines a 4 x 4
array of crosspoints (transmission gates) with
a 4-line-to-16-line decoder and 16 latch circuits. Anyone of the sixteen transmission
gates (crosspoints) can be selected by applying the appropriate four line address. The
selected transmission gate can be turned on
or off by applying a logical one or zero,
respectively, to the data input and strobing
the strobe input to a logical one. Any number
of the transmission gates can be ON simul-
X2- I.
DATA I N - 2
by putting the strobe high and data-in low,
and then addressing all switches in
succession.
c-
VSS-
B
A-
Features:
Y1
13 ~)(4
12 r-X3
II r-Y4
10 r-Y3
7
91-XI
TOP
• Low ON resistance - 75 n typ_ at
VOO = 12V
• "Built-in" control latches
• Large analog signal capability - ± VOO/2
• 10-MHz switch bandwidth
• Matched switch characteristics
,c,RON =10n typo at VOO = 12 V
taneously. When the required operating
• High linearity - 0.5% distortion (typ_) at
power is applied to the CD22100, the states
of the 16 switches are indeterminate.
f =1 kHz, VIN = 5 V p _p ' VOO =10 V,
Therefore, all switches must be turned off
and RL = 1 kn
• Standard COSIMOS noise immunity
• 100% tested for maximum quiescent
current at 20 V
MAXIMUM RATINGS. Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (V pD )
(Voltages refer~nced to V SS Termonal) .
. -0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS .
-0.5 to V DD +0.5 V
DC INPUT CURRENT. ANY ONE INPUT* .
±10mA
POWER DISSIPATION PiR PACKAGE (PO):
For T A = -40 to +600 C (PACKAGE TYPE E)
. . . . . . . ..
500mW
For:r A = +60 to +85 ~ (PACKAGE TYPE E). .
Derate Linearly at 12 mW/o C to 200 mW
(PACKAGE. TYPES 0, F)
For TA = -55 to +100
500mW
. . . • . . . ..
For TA = +100 to +125 C (PACKAGE TYPES 0, F)
Derate Linearly at 12 mWi"C to 200 mW
DEVICE DISSIPATION PER TRANSMISSION GATE
FOR T A = FULL PACKAGE-TEMPERATURE RANGE (All Package Types)
100mW
OPERATING-TEMPERATURE RANGE ITA):
PACKAGE TYPES D. F. H
-55 to +125°C
PACKAGE TYPE E
-40 to +850 C
STORAGE TEMPERATURE RANGE ITS!)
. .
-65 to +1500 C
LEAD TEMPERATURE (DURING SOLD~RING):
At distance 1/16 ± 1/32 inch (1.59 ±0.79 mm) from case for 10 s max.
. +2650 C
* Maximum current through transmission gates (switches) = 25 rnA.
VIEW
92C5-2734'
Terminal
Assignment
ISUPPLY VOLTAGE
-".
'''-- !.SV
I~
I!.
I
'.-f.
I
!NPUT SIGNAL (Y"J-V
Fig.
f
STROBE
STROBE-
••
•
D-
B-
t6 r-VDD
"" r-Y2
3
,
9lCS-lottSl
2- ·Typical ON resistance as a function of
input signal voltage at VDO
2.SV.
C' -
V5S-
~v,v,,--sv
'TTttt" .",,-~::.~-_:".:
12"._._ T·_ ..":"PEo.TUO.:
O
II
I~
OATA
IN
. INPI 'SIGNALlV"
r-----~r_----~------~----OJ5
92CS-lozez
YI
Fig. 3- Typical ON resistance BS a function of
signsl voltage at VOO
~
-VSS=
r--+--~---+--~---+--...,..--t-<::>14
Y2
,--I-~r_-+--......,--j--"",,--+-oy:'
neS-10263
12
XI
)(2
Fig. 1 - Functional diagram.
584
x>
X4
"
92CM- 27346RI
Fig.
4 - Typical ON resistance as B function of
input signal voltage st VDO - - VS57_S II.
CD22100 Types
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected
so that operation is always within the following ranges:
LIMITS
CHARACTERISTIC
Supply·Voltage Range (For T A =
Full Package·Temperature Range)
MIN.
MAX.
3
18
UNITS
V
*,
INPUT SIClNA1.IVi ,I-Y
STROBE
160>----_
VDD
Fig. 5- Typical ON resistance as a
r---~----r------1----o"
VI
*.~
*.~
fUnfiPon of
input signal voltage at TA = 25 C.
TO OTHER DECODER
GATES/LATCHES
DETAIL OF LATCHES
*'~
"~:
. .:
"
Q
..
..~
INPUT VOLTAGE {Vi,I-V
Fig. 7 - Typical switch ON transfer charac-
teristics ( 1 of 16 switches).
X4"
OETAILOF TRANSMISSION GATES
.0>-----.
Vss
*
PROTECTED
INPUTS BY
COS/MOS PROTECTION
NETWORK
AMBIENT TEMPERATURE ITA). 215-C
SUPPLY VOLTAGE: "00-+5, IISS··!lV
~
£\VDD
INPITS~~~N!~:C~~:~; (:~~.!lV j"p-H+f-l-H-H
6
DATA-IN VOLTAGE (YOATA-IN1:+!lV
> 2!1 LOAD CAPACITANCE (CL.).I!5pF
!'
.!.
~;
~
Vss
I
Vss
I I III I
2
LOAD RESISTANCE
(RL'-"tln
Cics-O.4pf
I I :--'~-i
"is
til
SW
1.15
i 1~+-+11+-'i--r+r+-+-f~
o o.sf--I--H-++-l-f-tt+-+-l-t'lk'r-r"'i'TTl
Fig. 6- Schematic diagram.
Z
103
roZ
.04
4
$,
10'
10'
INPUT SIGNAL FREQUENY (t 1,1-IIHz
Sl2CS-30Z8'
TRUTH TABLE
Fig. 8 - Typical switch ON frequency response
characteristics.
Select
Address
Select
Address
o
AMBIENT TEMPERATURE ITA '-2S·C
SUPPL 'I' VOLTAGE lVoo 1-' 0 II
INPUT SIGNAL. VOLTAGE IV",-IQ Y pop I'ins wa"l
A
B
C
D
A
B
C
0
0
0
0
0
X1Yl
0
1
X1Y3
0
X2Yl
1
0
0
0
1
0
0
0
1
X2Y3
0
1
0
1
X3Y3
X4Yl
1
X4Y3
1
0
0
X1Y2
1
1
X1Y4
1
1
X2Y4
!l
0
0
X3Y2
1
0
1
0
0
0
1
1
0
0
0
0
X3Yl
1
0
1
0
0
0
1
1
X3Y4
u"o'Df-+-++tJ;;...,..,+t++-+-++++-+-++++-++-t-tl
X4Y2
1
1
1
X4Y4
1
1
1
1
1
1
X2Y2
1
0
0
1
1
-20
t~g ~rs~~+l~~Cl,C:8:~~tfF
-
.m
~-4oH-'i+tH-'i-++H--+-++H-j++VH-+1H
~T",
~60H--++tH-j-++H--+-++H74+++-H-+1H
§
~
~-8°H--++tH-j-++H"7i'9-tH-j+++-HH-1H
ii1
-120
0.1
-
2;
'"
6 8,
2 4 6810 2; 468102 2 468'032 4 68104
INPUT SIGNAL FREQUENCY Ifi,l- kHz 92CS-30267
Fig. 9 - Typical crosstalk between switches as a
function of signal frequency.
585
CD22100 Types
STATIC ELECTRICAL CHARACTERISTICS
LIMITS at Indicated Temperature ( C)
Values at -55,+25,+125,apply to D,F,H pkg
CHARACCONDITIONS
Values at -40,+25,+85,apply to E pkg
TERISTIC
VIN VDD -55 -40
(V) (V)
+25
Typ.
+85 +125
Min.
'01
AMBIENT TEMPERATURE ITA )-25·C
Units
Max.
CROSSPOINTS
-
Quiescent
Device Current,l DD
Max.
ON Resistance
RON Max.
liON Resistance,
lIRON
Any Switch
VIS=
Oto VOD
Between
any two
switches
OFF Switch
Leakage
All switches
Current
OFF
.IL Max.
-
-
5
10
15
20
5
10
20
100
5
10
20
100
150
300
600
3000
-
-
-
-
-
450 1000
135 145
1440 1625
205 230
12
15
100
70
110
75
155 175
110 125
5
10
12
15
-
-
-
-
-
5
10
-
-
150
300
600
3000
-
0.04
0.04
0.04
0.08
5
10
20
100
iJA
0.1
I
2
468'0 2
SWITCHING
4 68'022
4 68'04
92CS-30268
225
85
1250
180
75
65
135
95
35
20
18
15
-
n
Fig. 10 - Typical dynamic power dissipation as a
function of switching frequency.
VDO
n
,.
16
I.
13
12
0,18
18
±IOO
-
±lOOO
±100·
±1
"
nA
10
9
CONTROLS
92CS-30269
Input Low
Voltage
VIL Max.
OFF switch
IL <0.2IlA
Input High
Voltage,
VIH Min.
ON switch
see RON
characteristic
Input
Current,
liN Max.
4 68,032
FREQUENCY 1f,I-kHI
-
-
-
5
10
15
1.5
3
4
-
5
10
15
3.5
7
11
3.5
7
11
-
1.5
3
4
-
-
-
Fig. 11 - Quiescent current test circuit.
V
VOD
VDD
Any control
0,18 18
±0.1
±1
±0.1
±1
-
±10-5
±0.1
iJA
~
Vss
16
15
I.
NOTE
MEASURE INPUTS
SEQUENTIALLY TO
BOTH VDO AND Vss
CONNECT ALL UNUSED
INPUTS TO EITHER
13
12
• Determined by minimum feasible leakage measurement for automatic testing.
"
Voo OR V,S
10
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C
CONDITIONS
CHARACTERISTIC
92CS-30270
LIMITS
fis
kHz
RL
kn
Vis· VDD
(V)
(V)
-
10
5
10
15
UNITS
Fig. 12 - Input current test circuit.
Min. Typ. Max.
CROSSPOINTS
Propagation Delay Time, (Switch ON)
Signal Input to Output, tpHL' tpLH
5
10
15
-
60
30
20
ns
-
30
15
10
-
40
-
MHz
CL = 50pF;t r .tf=20ns
Frequency Response.
(Any Switch ON)
1
1
10
5
Sine wave input I
Vos
20 log - - = -3 dB
Vis
Sine Wave Response, (Distortion)
Feedthrough
(All Switches OFF)
·Peak-to-peak voltage symmetrical about
~.
12
1If-t-t--,
10
1
1
5
10
-
0.5
-
%
1.6
1
5
10
-
-80
-
dB
Sine wave input
V·
,.
•
,.OTE
CLOSE SWITCH S AFTER
92CS-30271
APPLYING VOD
Fig. 13 - Dynamic power dissipation test circuit.
2
586 __________________________________________________________________
CD22100 Types
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C
CONDITIONS
CHARACTERISTIC
fis
kHz
RL
kn
-
1
. LIMITS
Vis· VDD
(V) (V)
UNITS
Min. Typ. Max.
CROSSPOINTS (CONT'D)
Frequency for Signal Crosstalk
Attenuation of 40 dB
Attenuation of 110 dB
10
10
-
Sine wave input
1.5
0.1
-
'0
MHz
kHz
92C:5-30212
Vss
Capacitance,
Xn to Ground
Yn to Ground
Feedthrough
-
-
-
-
-
5·15
5-15
-
-
-
lB
30
0.4
-
-
pF
Fig. 14 - OFF switch input or output leakage
current test circuit.
-
ON
See
Fig.
CONTROLS
Propagation Delay Time:
Strobe to Output, tpZH
(Switch Turn·ON to High Level)
18
5
10
15
19
5
10
15
20
5
10
15
18
5
10
15
Data-In to Output, tpZL
(Turn-ON to Low Level)
19
5
10
15
Address to Output, tpHZ
(Turn-OFF)
20
5
10
15
RL=lkn,
CL=50pF,
tptf= 20ns
Data·ln to Output, tpZH
(Turn-On to High Level)
Address to Output, tpZH
(Turn-ON to High Level)
Propagation Delay Time:
Strobe to Output, tpH Z
(Switch Turn-OFF)
Minimum Setup Time,
Data-In to Strobe, Address, tsu
Minimum Hold Time,
Data-I n to Strobe, Address, tH
Maximum Switching Frequency, fqJ
RL=lkn,cL=50pF
t r, tf = 20 ns
Minimum Strobe Pulse Width. tw
-
Control Crosstalk.
Data·ln. Address. or Strobe to Output
10 110
• Peak-to-peak voltage svmmetrical s'bout V OO -
-2-
5
10
15
10
-
-
110 220
40 80
25 50
-
350 700
135 270
gO 180
-
-
-
-
0.6
1.6
2.5
-
-
-
-
Vi'~V"
300 600
125 250
80 160
'O"'y'OF
sw- ANY
STROBE •
210 420
110 220
100 200
300 600
120 240
90 180
75
-
5
7.5
DATA-I~
.YOD
92CS-3QZ75
Fig. 15 - Propagation delay time test circuit and
waveforms (signal input
to signal output,
switch ON).
CONTROLS
ns
'":r8r-~
435 870
210 14 20
160 320
95 190
25 50
15 30
180 360
110 220
35 70
1.2
3.2
5
-
CROSSPOINT
ns
165 330
85 170
70 140
Square wave input
tp tf=20ns
Any Control Input
Input Capacitance, CIN
5
10
15
5
10
15
5
10
15
-
SW -ANY CROSSPOINT
ns
ns
11L..J11L-Jr
....J
VDD CONTROL 0
50lnV-,
V"
_.om~--f·--~~-i~~~-92CY-30277
MHz
Fig.
/6-
Test circuit and waveforms for crosstalk
(control input to signal output).
ns
ON
mV
(peak)
Vi'~
"ol~
llkA
OFF
Ikof sw
II-00VO.
pF
sw- ANY CROSSPOINT
t2CS-S027'
Fig. 17 - Test circuit for crosstalk between switch
circuits in the same package.
________________________________________________________
~7
CD22100 Types
STROBE
DATA-IN
V,.
_
-J
CZH
"---410%"-
v..
SW • ANY CROSSPOINT
92CM-302.74
Fig. 18 - Propagation delay time test circuit and waveforms (strobe to signal
.
output, switch Turn-ON or Turn-OFF).
DATA IN
Vii
~
SW
-
VOl
I k'o
sw- ANY CROSSPOINT
STROBE -Voo
!iOpF
-=
92CM-3027!5
Fig. 19 - Propagation delay time test circuit and waveforms (data-in to signal output,
switch Turn-ON to high or low level).
VDD
ADDRESS-O
ADDRESS-'
ADDRESS
--+......1
VDD
DATA-IN
Vas I
SW-ANY CROSSPOINT
STROBE.- Vao
VDD
Vas 2
92CM-30276
Fig. 20 - Propagation delay time test circuit and waveforms (address to Signal output,
switch Turn·On or Turn·OFF).
Dimensions in parentheses are in millimeters and
"0-
are derived from the basic inch dimensions as in3 inchl.
dicated. Grid graduations are in mils
The photographs and dimensions of each COS/MOS
chip represent a chip when it ,is part of the wafer.
When the wafer is cut into chips, the cleavage
, angles are 57° instead of 90° with respect to the
face of the chip. Therefore, the isolated chip is
actuallv 7 mils (0.17 mm) larger in both dimensions.
Dimensions and pad layout for CD22 I OOH.
588 ____________________________________________________________________
Preliminary Data
COS/MOS 4 X 4 X 2
Crosspoint Switches
With Control Memory
The RCA·CD22101 arid CD22102 crosspoint
switches consist of 4 x 4 x 2 arravs of cross·
points (transmission gates!. 4·line to 16-line
decoders, and 16 latch circuits. Anv one of
the sixteen crosspoint pairs can be selected
by applying the appropriate four-line ad·
dress, and anv number of crosspoints can be
ON simultaneously. Corresponding cross·
points in each array are turned on and off
simultaneouslv, also.
In the CD22101, the selected crosspoint pair
can be turned on or off by applying a logical
ONE or ZERO, respectively, to the data in·
put, and applying a ONE to the strobe input. When the device is "powered up", the
states of the 16 switches are indeterminate. Therefore, all switches must be
turned off by putting the strobe high,
data-in low, and then addressing all
switches in succession.
CD221 01 , CD22102 Types
Features:
• Low ON resistance - 75 n typo at
VDD= 12V
• "Built-in" latched inputs
• Large analog signal capability ± VOO/2
• 10 MHz switch bandwidth
• Matched switch characteristics
lIRON = 8 n typo at VOD = 12 V
• High linearitv - 0.25% distortion {typ.} at
f = 1 kHz, VIN = 5 Vp _p , VOO - VSS = 10 V,
and RI = 1 kn
• Standard COS/MOS'noise immunity
The selected pair of cross points In tne
CD22102 is turned on by applving a logical
ONE to the Ka (set) input while a logical
ZERO is on the Kb input, and turned off by
applying a logical ONE to the Kb (reset)
input while a )ogical ZERO is on the Ka
input. In this respect, the control latches of
the CD22102 are similar to SET/RESET
flip·flops. Thev differ, however, in that the
simultaneous application of ONEs to the Ka
and Kb inputs turns off (resets) all crosspoints. All crosspoints in both devices must
be turned off as VDD is applied.
The CD22101 and CD22102 types are sup·
plied in 24·lead hermetic dual-in-line ceramic
packages (D and F suffixes), 24-lead dual·inline plastic packages (E suffix'), and in chip
form (H suffix).
C022101, C022102
FUnctional Diagram
Applications:
• Telephone svstems
• PBX
• Studio audio switching
• Multisystem bus interconnect
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (V DD )
(Voltages referenced to VSS Terminal)
-0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS.
-0.5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT·.
±10mA
POWER DISSIPATION PER PACKAGE (PD):
For TA = -40 to +600 C (PACKAGE TYPE E)
. . . . . . . ..
500mW
Derate Linearly at 12 mW/oC to 200 mW
For T A = +60 to +B5 0 C (PACKAGE TYPE E)
.
For TA = -55 to +1000 C (PACKAGE TYPES D,F)
. . . . . . • ..
500mW
For T A = +100 to +125 0 C (PACKAGE TYPES D, F)
Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
100mW
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types)
OPERATING-TEMPERATURE RANGE (TA):
.
-55 to +1250 C
PACKAGE TYPES D, F, H
-40 to +B5 0 C
PACKAGE TYPE E .
STORAGE TEMPERATURE RANGE (Tstg )
-65 to +1500 C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1132 inch (1.59 ± 0.79 mm) from case for lOs max .
•
C
X2'
YI'
Y2'
X4'
,,'
Y4'
Y,'
XI'
0
vss
I •
2
4
5
•
8
•
10
"
24
2'
22
21
20
I•
I.
17
I•
I.
14
12
TOP VIEW
"
Voo
A
X2
YI
Y2
X4
"
Y4
Y,
XI
DATA
STROBE
Top View
CD22101 Tert:ninal Diagram
• Maximum current through transmission pates (switches) = 25 rnA.
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that operation is alwavs within the following ranges'
• ,
C
X2'
YI'
I •
2
y2'
X4'
,,'
Y4'
CHARACTERISTIC
Supplv-Voltage Range (For TA = Full Package·
Temperature Range)
y,'
LIMITS
Min.
Max.
3
18
UNITS
XI'
0
V5S
10
"
24
2'
22
21
20
I.
18
17
I.
I.
14
12
TOP VIEW
V
"
voo
A
X2
YI
Y2
X4
"y,
Y4
XI
K,
K.
Top View
C022102 Terminal Diagram
589
CD221 01, CD22102 Types
[&2f~102
'Kit
21 VI
Ko \
20 Y2
SIGNALS
OUT (IN I
·
A
ADDRESS
·•
·
·
C
16 Y3
2.
17 '1'4
D
E
g
D
E
•5
D
IS
IS
e
*INPUTS
PROTECTED
BY COS/MOS
PROTECTION
NETWORK
---
4 VI'
,h>-t-,-t--r-++S,Y2'
SIGNALS
OUT (IN)
,h>-t-,-t--r-++•• Y"
,h>-t-,-t--r-+-+•• Y4 '
SIGNALS IN (OUT)
Fig. "I - Functional block diagram.
"
o~---_
'DO
.~
~
.~
.~
TO '!lOTHER
CD22io2
g....------
- .. -----.~
OETAIL OF TAAIoISIIiI'SSION GATES
.~..._-.Ff.T=f
, 0
NET_'
'ss
'ss
Fig. 2 - Logic diagram.
590 _____________________________________________________________
CD221 01, CD22102 Types
DECODER TRUTH TABLE
Address
B
A
0
0
1
0
1
0
1
1
0
0
0
1
1
0
1
1
Select
C
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
X1Yl
X2Yl
X3Yl
X4 Yl
X1Y2
X2Y2
X3Y2
X4Y2
Address
A
B
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
1
& Xl'Yl'
& X2'Yl'
& X3'Yl'
& X4' yl'
& Xl'Y2'
& X2'Y2'
& X3'Y2'
& X4'Y2'
Select
C
0
0
0
0
1
1
.1
1
0
1
1
1
1
1
1
1
1
X1Y3 &
X2Y3 &
X3Y3 &
X4Y3 &
Xl Y4 &
X2Y4 &
X3Y4 &
X4Y4 &
Xl'Y3'
X2'Y3'
X3'Y3'
X4'Y3'
Xl'Y4'
X2'Y4'
X3'Y4'
X4'Y4'.
CONTROL TRUTH TABLE FOR C022101
Function
Strobe
Data
Switch On
Address
A
B
1
1
C
1
0
1
1
1
15 (X4Y4) &
15' (X4'Y4')
Switch Off
1
1
1
1
1
0
15 (X4Y4) &
15' (X4'Y4')
No Change
X
X
X
X
0
X
X X X X
1
=High
Level; 0
= Low Level;
Select
X = Don't Care
CONTROL TRUTH TABLE FOR C022102
Function
Ka
Kb
Select
Switch On
Address
A
B
1
1
C
1
0
1
1
0
15 (X4Y4) &
15' (X4'Y4')
Switch Off
1
1
1
1
0
1
15 (X4Y4) &
15' (X4'Y4')
All Switches
Off
No Change
X
X
X
X
1
1
X
X
X
X
0
0
1
= High
Level; 0
= Low Level;
All
XXX X
X =Don't Care
591
CD22101, CD22102 Types
STATIC ELECTRICAL CHARACTERISTICS at T A = 2!i°C
TEST CONDITIONS
CHARACTERISTIC
Quiescent Device Current, I L
VDD
(V)
Switches OFF or ON
Cr osspoint:
OFF Leakage Current, I L
ON Resistance,RON
RL
I\ON Resistance, lIRON
lOkI!
Feedthrough Capacitance, CIOS
Channel Input or Output
Capacitance, CIS, COS
1
Feedthrough, Crosspoints OF F
UNITS
20
nA
100
pA
75
5
n
0.2
pF
30
pF
5
pF
0.4
%
-95
dB
n
12
Control I nput Capacitance, CI
Sine Wave Response (o.istortion)
TYPICAL
VALUE
j
fis" 1 kHz
RL c 10kU
fis
~
RL
1.6 kHz
~
1 k!!
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C
TEST CONDITIONS
CHARACTERISTIC
Propagation Delay Time:
Address or Strobe Inputs
To Output, tPHL, tPLH
Across Crosspoint,tPH L,tP LH
Minimum Strobe Pulse Width
592 ________________
~
VDD
(V)
RL
= 10 kH
CL = 50 pF
TYPICAL
VALUE
UNITS
f
200
ns
20
ns
+
80
ns
12
__________________________________________________
CD22104, CD22104A Types
Objective Data
COS/MOS
Four-Digit LCD
Decoder-Drivers
,"~'.m~ {
02
SEGMENT
OUTPUTS
12-V Rating
The RCA-CD22104 types are nonmultiplexed. four-digit. seven-segment.
IIquld-crystal display decoder-drivers_
The CD22104 types contain all the circuitry necessary to drive conventional
LCD displays (no external components requlred)_ Outputs are four sets of sevensegment driver signals and a backplane
driver signal. The backplane signal, derived from an on-board free-running
. oscillator, is common to all four digit
displays. These outputs combine to provide the zero dc components necessary
for long display life.
There are four data Inputs and four digit
select inputs. The four-bit binary input is
decoded by means of a PROM into sevensegment hexadecimal outputs for the
CD22104 and into decimal seven-segment
display outputs for the CD22104A. These
devices are pin-compatible with the InterslllCM72111PL and ICM7211AIPL, respectively.
D.
SEGMENT
OUTPUTS
20 2J2:f2~t~t~r25
A4 94 C4 04
Features
• 12- V supply-voltage rating
• No external components necessary
• 4-digit segment drive capability
• Backplane input/output allows
synchronization for cascading
devices to drive more digits
• Decodes multiplexed binary to
hexadecimal (CD22104) and decimal
(CD22104A) outputs
D.
SEGMENT
0'
SEGMENT
OUTPUTS
OUTPUTS
6'
42
n nl
I
7
WI""
DRIVER
ENB
.1JJ
_IJ 1
7 WIDE LATCH
Lll
35
7
8
9
10
34
33
32
31
30
29
28
27
2.
25
24
23
22
21
"
04 SE8~f~JT
DATA
DIGIT
SELECT
INPUTS
OSCILL.ATOR
INPUT
,
29
3'
,.
33
31
"
ENB
71 af 9f,01121 II
~21c_~JO_21E2klG2
7
WIDE
DRIVER
lJ.l
JJJ.l.l
1 WIDE LATCH
" ..T,.T.oi .i .i ,1
AI JJJEI JGI
n
7
WIDE
DRIVER
I I II L
..l.LW
ENB
7 WIOE LATCH
1111
I-
N
II J
'-'
,?
,:'
:i
'-:
c;-'
'3
S
,-
'j
;
-
4-10-7
0
::,-
D.
0
D.
01
.-
OSCILLATORJ------t:J----i BACKPLANE
.,..,28
I
DRIVER
.-,
r:
.:.
Ot:CODER
~
SEGMENT
OUTPUTS
Table I - Output Codes
Displl!y
Binary Input
HexadeCimal
DeCimal
B3 B2B1 BO
CD22104
CD22104A
01
SEGMENT
OUTPUTS
PROGRAMMABLE
ROM
~REJ6R~~~ING
DATA
INPUTS
CD22104, CD22104A
Terminal Asslgnmant
,
J
}
92CS-32933
""Ji
INPUTS
OIGIT
SELECT
INPUTS
TOP VIEW
(J
BO
BI
B.
B'
Vos
}
. i }..
SEGMENT
OUTPUTS
12
13
I.
15
I.
17
18
19
20
:3
'7
28
OUTPUTS
OSCILLATOR INPUT
The CD22104 types are supplied in the
40-lead dual-in-line plastic (E suffix)
package.
13' 14i ,~f ,J ~7i ~91'B1
7
WIDE
DRIVER
•
} SEGMENT
01
Applications
• Digital meters and calculators
• General-purpose displays
• Wall and table clocks
• Automobile dashboard displays
• Appliance control panels
E41F41.4 A31aJc31031E3 F3G3
7 WIDE LATCH
40
3.
38
37
3.
01 Voo {
SEGMENT
OUTPUTS
BACKPLANE
:>
0
,-,
'J
>:>
J
c
:,
;J
(BLANK/
,
BAC KPL.ANE
INPUT/OUTPUT
92CS-33050
ENB
DETECTOR
'66"
VDO
92CL-330
VSS
Fig. 1 - Block diagram of CD22104 and CD22104A.
593
CD22105, CD22105A Types
COS/MOS
Four-Digit LCD
Decoder-Drivers
Objective Data
Features
• 12- V supply-voltage rating
• No external components necessary
• 4-digit segment drive capability
• Backplane input/output allows
synchronization for cascading
devices to drive more digits
• Direct microprocessor interface
• Decodes binary into hexadecimal
(CD22105) and decimal (CD22105A)
outputs
12-V Rating
The RCA-CD22105 types are nonmultiplexed, four-digit, seven-segment,
liquid;crystal display decoder-drivers_
The CD22105 types contain all the circuitry necessary to drive conventional
liquid-crystal displays (no external components required). Outputs are four sets
of seven-segment driver signals and a
backplane driver signal. The backplane
Signal, derived from an on-board freerunning oscillator, is common to all four
digit displays. These outputs combine to
provide the zero dc components
necessary for long display life.
A four-bit data-input latch and a two-bit
select-code latch under the control of two
chip-select inputs permit interfacing with
a microprocessor. This device simplifies
designing a seven-segment display into a
microprocessor system, Without requiring
extensive ROM or CPU time for decoding
and display updating_ The four-bit binary
input is decoded by means of a PROM
into a seven-segment hexadecimal output
Applications
• Microprocessor-control/ed digital
meters and calculators
• General-purpose displays
• Microprocessor-control/ed automotive daShboard displays
• Microprocessor appliance control
panels
SEGMENT
OUTPUTS
OUTPUTS
20i 2~22f2~T2412J25 13 14i 15i lsi 17i 19i 18
.41F4b4 A3 eJc3lo3lE3 F3G3
.,
II
I
~I
7
WIDE
DRIVER
I I I I
I I I I
'7
DIGIT
~'-BI1§
02
SEGMENT
OUTPUTS
II
.. f
SEGMENT
OUTPUTS
•
A2
~
7i 8i
.i,oi "i "
Bz!cJozlEJF2
7
I
WIDE
DRIVER
I I I
37
AI
G2
611 ClI ollEI
FI GI
7
~
I
WIDE
DRIVER
I I I
I-
.
0
0
0
0
0
0
0
1
l'~
,"
1
0
1
0
0
0
1
Q
1
-':'
',--:
J
0
1
1
0
'j
0
1
1
1
1
0
0
0
oj
1
0
0
1
PROGRAMMABLE
ROM
1
0
;
0
'"
4-TO-7
DECODER
1
0
1
1
1
1
0
0
'-
1
1
0
1
oj
ENB
7 WIDE LATCH
I II
III
1
1
1
1
1
0
1
,-
,,
,-,
.J
li
,
,0
SE:ENT
OUTPUTS
'-'
e
:J
-'
'-:
'j
,'":
,=.
'-'0
.J
-
E
:-1
::,,-
':.J
-Jl ~ i ~
To
:::::: ]
(D) SUFFIX (JEDEC MO-001-AD)
j
------.
(D) SUFFIX (JEDEC MO-001-AEi
16-Lead Dual-In-Line Welded-Seal
Ceramic Package
'~""D",".UooW.""'"
Coram Ie Package
•
NOTES:
Refer to Rules for Dimensioning (JEDEC Publication No. 95)
for AXial lead Product Outlines.
1. When this device is supplied solder·dipped, the maximum lead
tt'lickness (narrow portion) will not exceed 0.013"(0.33 mm).
2. Leads within 0.005" (D.12 mm) radius of True Position (TP) at
gauge plane with maximum material condition and unit installed.
3. eA applies In zone L2 when unll installed.
4. a apphes 10 spread leads prior to Installation.
5. N IS the maximum quantity of lead positions.
SYMBOL
SYMBOL
A
Al
B
Bl
C
0
E
El
01
°A
L
L2.
a
N
N,
0,
S
INCHES
MIN.
MAX.
0.120
0.160
0.020
0.065
0.014
0.020
0.065
9·050
0.008
0.012
0.745
0.770
0.300
0.325
0.240
0.260
O.I00TP
0.300TP
0.125
0.150
0.000
0.030
00
160
14
0
0.050
0.085
0.065
0.090
NOTE
1
2
2.3
4
5
6
MILLIMETERS
MIN.
MAX.
3.05
4.06
0.51
1.65
0.35&
0.508
1.27
1.65
0.204
0.304
18.93
19.55
7.62
8.25
6.10
6.60
2.54 TP
7.62 TP
3.18
3.81
0.000
0.76
00
ISO
14
0
1.27
2.15
1.66
2.28
92SS-4411R2
6. N,IS the quantity of allowable rniningleads.
A
Al
B
Bl
C
0
E
El
INCHES
MIN.
MAX.
0.120
0.160
0.065
0.020
0.014
0.035
0.020
0.065
0.008
0.745
0.300
0.240
0.012
0.785
0.325
0.260
NOTE
1
MILLIMETERS
MIN.
MAX.
3.05
4.06
0.51
1.65
0.356
0.89
0.508
1.65
0.204
18.93
0.304
19.93
7.62
6.10
8.25
6.60
"I
O.I00TP
2
2.54 TP
"A
L
0.3OOTP
2,3
7.62TP
L2
0.125
0.000
a
0.150
0.030
15 0
0"
N
16
0
Nl
3.18
0.000
0"
4
5
6
3.81
0.76
I
150
16
0
01
0.050
0.085
1.27
2.15
S
0.015
0.060
0.39
1.52
92SS-4286R5
(D) SUFFIX (JEDEC MO-015-AH)
28-Lead Dual-In-Line Welded-Seal
Ceramic Package
(D) SUFFIX (JEDEC MO-015-AG)
24-Lead Dual-In-Line Welded-Seal
Ceramic Package
SYMBOL
A
Al
B
Bl
C
0
E
El
·1
.A
L
L2
NOTES:
Refer to Rules for Dimensioning (JEDEC Publication No. 951
for Axial Lead Product Outlines.
1. When this device is supplied solder·dipped, the maximum
lead thickness (narrow portion) will not exceed 0.013"
(0.33mml.
2. Leads within 0.005" (0.12 mm) radius of True Position
(TP) at gauge plane with maximum material condition
and unit installed.
3. eA applies in zone L2 when unit installed:
4. 0. applies to spread leads prior to installation.
5. N is the maximum quantity of lead positions.
6. N1 is the quantity of allowable missing leads.
DUAL·IN-LiNE SIDE·BRAZED CERAMIC
PACKAGES
a
N
Nl
01
S
MILLIMETERS
INCHES
NOTE
MIN. MAX.
MAX.
MIN.
0.090 0.200
0.020 0.070
0.Q15 0.020
0.045 0.055
0.008 0.012
1.15
1.22
0.600 O.S25
0.480 0.520
0.100 TP
O.SOOTP
0.100 0.180
0.000 0.030
()O
150
24
0
0.020 0.080
0.020 O.OSO
1. Leads within 0.005" (0.13 mm) radius of True
Position at maximum material condition.
2. Center to center of leads when formed parallel.
3. When this device is supplied solder dipped, the
maximum lead thickness (narrow portion) will not
.xceed 0.013" (0.33 mm).
604
2
2,3
4
5
6
(D) SUFFIX
40-Lead Dual-In-Line
Side-Brazed Ceramic Package
SYMBOL
INCHES
MIN.
NOTES:
1
2.29
5.08
1.78
0.51
0.381
0.508
1.143
1.397
0.204
0.304
29.21
30.98
15.24
15.87
12.20
13.20
2.54 TP
15.24 TP
2.54
4.57
0.00
0.76
()O
150
24
0
0.51
2.03
1.52
0.51
MIN.
MAX.
51.30
A
1.980 2.020
50.30
C
0.095 0.155
2.43
3.93
0
0.017 0.023
0.43
0.56
F
0.050 REF.
G
0.100 BSC
1.27 REF.
1
H
0.030 0.070
J
0.008 0.012
K
0.125 0.175_
l
M
0.580 0.620
70
-
P
0.025 0.050
N
40
3
2
A
Al
:1
C
D
INCHES
MILLIMETERS
NOTE
MIN. MAX.
MIN.
MAX.
0.090 0.200
2.29
5
0,070
0
2
0
1.77
g:gl~ li;:~55
~:~ I~:~~~
E
El
el
eA
0.600 0.625
0.485 0.515
C2
u. OUU I~:030
a
N
Nl
a1
S
u.n
I~
0.600 TP
,-D'
28
0
0.020 0.070
0.040 0.070
~::I
~:~~H
3g:~r 3~:~r
1
15.24
12.32
z
15.87
13.08
1~:~4 ~~
2,3
'0"
4
0.76
'Du
UU
5
28
0
6
0.51
1.02
1.77
1.77
92CM·20250R2
92CS-19948R4
NOTE MILLIMETERS
MAX.
SYMBOL
2.54BSC
0.76
1.78
0.20
0.30
3.18
4.45
14.74
15.74
70
0.,64
1.27
40
92CM 27029R2
(D) SUFFIX
22-Lead Dual-In-Lin ..
Side-Brazed Ceramic Package
SYMBOL
A
C
D
F
G
H
J
K
L
M
P
N
INellES
MIN.
MAX.
1.065 1.100
0.085 0.145
0.017 0.023
0.040 REF.
0.100 BSC
0.030 0.070
0.008 0.012
0.125 0.175
0.380 0.420
70
0.025 0.050
22
NOTE
1
1
3
2
MI IMI'TFRS
MIN.
MAX.
27.05
27.94
2.16
3.68
0.43
0.56
1.02 REF.
2.54 BSC)
0.76
1.78
0.20
0.30
3.18
4.45
9.65
10.67
70
0.64
1.27
22
92C8-25186R2
Dimensional Outlines (Cont'd)
Dual-In-Line Plastic and Frit-Seal Ceramic Par.kages
--rr=s-' ~ ------.
'j
~
~
•
UATIMGPlAtlEL
4
T.
A
~
""""" IL·· ,JL ~
...
c,
,:"' f-
(E) and (F) SUFFIXES (JEDEC MO-001-AC)
16-Lead Dual-In-Line Plastic or
Frit-Seal Ceramic Package
SYMBOL
A
Al
8
81
C
D
E
El
NOTES:
Refer to Rules for Dimensioning (JEDEC Publication No. 95)
for Axial Lead Product Outlines.
1. When this device IS supplied solder-dipped, the maximum lead
thickness (narrow portion) will not exceed 0.013" (0.33 mm).
2. leads within 0.005" (0,12 mml radius of True Position (TP)
at gauge plane with maximum material condition and unit
installed.
NOTE
MILLIMETERS
MIN.
3.94
MAX.
0.51
1.27
0.014
0.020
0.356
0
0.050
0.008
0.745
0.065
0.012
0.710
E
El
0.300
0.240
0.325
0.260
1.27
0.204
18.93
7.62
"I
0.100TP
"A
L
L2
a
N
Nl
01
S
0.300 TP
0.125
0.150
0.030
0.000
150
00
14
a
0.040
0.065
1
2
2.3
5.08
0.508
1.65
0.304
19.55
8.25
6.60
6.10
2.54 TP
7.62 TP
3.81
3.18
0.000
4
5
6
0.075
0.090
0.76
150
00
14
a
1.02
1,90
1.66
2.28
0.012
0.785
0.325
0.260
1
0.508
1.65
0.204
18.93
7.62
6.10
0.304
19.93
8.25
6.60
2
2.54 TP
0.300TP
2.3
7.62 TP
01
INCHES
MIN.
MAX.
0.200
0.155
0.020
0.050
0.008
0.745
0.300
0.240
0.356
0.89
O.I00TP
5. N is the maximum quantity of lead positions.
6. N 1 is the quantity of allowable missing leads.
A
Al
8
81
C
0.020
0.065
NOTE
"A
L
3. eA applies in zone L2 when unit installed.
4. a applies to spread leads prior to installation.
SYMBOL
0.014
0.035
SYMBOL
MILLIMETERS
MIN.
MAX.
3.94
5.08
1.27
0.51
"I
L2
a
N
N·l
(E) and (F) SUFFIXES (JEDEC MO-001-AB)
14-Lead Dual-In-Line Plastic or
Frit-Seal Ceramic Package
INCHES
MIN.
MAX.
0.155
0.200
0.050.
0.020
5
3.18
0.000
0.150
0.030
0.125
0.000
I
C1'
150
16
0
0.040
0.015
4
5
6
0.075
0.060
0"
3.81
0.76
I
150
16
0
1.02
1.90
0.39
1.52
92CM-I5967R4
(E) SUFFIX
22-Lead Dual-In-Line
Plastic Package
SYMBOL
A
A
B
8,
C
0
E
E
·1
"L
L?
a
N
N
01
S
'lilt'''''MAX.
MIN.
0.020
0.015
0.035
0.008
0.012
1.120
0.390 0.420
0.345 0.355
0.100 TP
0.400 TP
0.125 0.150
a 0.030
150
2°
22
a
0.055
0.Q15
NOTE
0.200
0.050
0.020
0.065
0.155
0.085
0.060
1
2
2.3
4
5
6
MILLIMETERS
MIN.
MAX.
3.94
.5.08
1.27
0.508
0.381
0.50B
0.89
1.65
0.204
2~:~~4
9.91
10.66
B.77
9.01
2.54 TP
10.16TP
3.18
3.Bl
0
0.762
20
150
22
a
1.40
0.381
2.15
1.27
92CS·30830
92SS·4296R3
(E) and (F) SUFFIXES (JEDEC MO-015-AA)
24-Lead Dual-In-Line Plastic or
Frit-Seal Ceramic Package
SYMBOL
A
Al
B
Bl
C
D
E
El
"I
NOTES:
Refer to Rules for Dimensioning (JEDEC Publication No. 951
for Axial lead Product Outlines.
1. When thiS device is supplied solder·dipped, the maximum lead
thickness (narrow portion) will nOI exceed 0.013",
2. Leads within O.OOS" (0.12 mm) radius of True Position (TP) at
guage plane with maKimum material condition and unit installed
3.
4.
5.
6.
eA applies In zone l2 when unit installed.
a applies to spread leads prior to installation.
N is the maximum quantity of lead positions.
N1 is the quantity of allowable missing leads.
"A
L
L2
a
N
Nl
01
S
(E) SUFFIX (JEDEC MO-001-AN)
S-Lead Dual-In-Line Plastic
(Mini-DIP) Package
INCHES
MILLIMETERS
NOTE
MIN. MAX.
MIN. MAX.
0.120 0.250
3.10 6.30.
0.020 0.070
0.51
1.77
0.D16 0.020
0.407 0.508
0.028 0.070
0.72
1.77
0.008 0.012
1
0.204 0.304
1.20 1.29
30.48 32.76
0.600 0.625
15.24 15.87
0.515 0.580
13.09 14.73
0.100 TP
2
2.54 TP
0.600 TP
15.24 TP
2.3
0.100 0.200
2.54 5.00
0.000 0.030
0.00 0.76
00
150
150
4
00
24
5
24
0
6
0
0.040 0.075
1.02 1.90
0.040 0.100
1.02 2.54
92CS26938R2
A
Al
8
81
C
INCHES
MIN. MAX.
0.155 0.200
0.020 0.050
NOTE
0.014 0.020
MILLIMETERS
MAX.
MIN.
5.08
3.94
0.508
1.27
1
O.OOB 0.012
0.370 Q.400
E
0.300 0.325
7.62
El
0.240 0.260
6.10
·1
0.100 TP
0.300 TP
0.125 0.150
0.000 0.030
N
Nl
8
0
01
S
0.040 0.D75
0.015 0.060
a
15
0.304
0.203
9.40
0
"A
L
L2
a
0.50B
1.65
0.356
0.889
0.035 0.065
10.16
8.25
6.60
2
2.54 TP
2.3
7.62 TP
3.81
0.762
3.18
0.000
o·
4
15·
8
5
6
a
1.90
1.52
1.02
0.381
92CS· 24026RI
(F) SUFFIX (JEDEC MO-001-AG)
16-Lead Dual-In-Line
Frit-Seal Ceramic Package
SYMBOL
A
Al
B
Bl
C
D
E
El
"I
"A
L
L2
a
N
Nl
01
S
INCHES
MILLIMETERS
MIN. MAX. NOTE MIN.
MAX.
0.165 0.210
4.20
5.33
0.015 0.045
0.381
1.14
0.D15 0.020
0.381
0.508
0.045 0.070
1.15
1.77
0.009 0.011
1
0.229
0.279
0.750 0.795
19.05
20.19
0.295 0.325
7.50
8.25
0.245 0.300
6.23
7.62
0.100 TP
2
2.54 TP
0.300 TP
2.3
7.62 TP
0.120 0.160
3.05
4.06
0.000 0.030
0.000
0.76
150
20
4
150
20
16
5
16
0
6
0
0.050 0.080
1.27
2.03
0.010 0.060
0.254
1.52
92CM·22284R 1
r
(E) SUFFIX
40-Lead Dual-In-Line
Plastic Package
SYMBOL
A
A
B
Bl
C
0
El
·1
a"
L
L2
a
N
Nl
°1
S
INC:HES
MILLIMETERS
MIN. MAX. NOTE MIN.
MAX.
0.120 0.250
3.10
6.30
0.51
0.020 0.070
1.77
0.016 0.020
0.407
0.508
0.028 0.070
0.72
1.77
0.204
0.008 0.012
1
0.304
2.000 2.090
50.80
53.09
14.73
0.515 0.580
13.09
2.54 TP
2
u.l10'P
15.24 TP
0.600 TP
2.3
0.100 0.200
2.54
5.00
0.00
0.000 0.030
0.76
0
0
0
0
15
4
0
150
40
40
5
0
6
0
2.41
0.065 0.095
1.66
0.040 0.100
1.02
2.54
92CS·30959
605
Dimensional Outlines (Cont'd)
TO·5 Style Package
Ceramic Flat Packs
(T) SUFFIX (JEDEC MO.006.AG)
12· Lead Metal Package
(K) SUFFIX (JEDEC MO·OO4-AF)
14-Lead
(K) SUFFIX (JEDEC MO·004-AG)
16-Lead
TERMINAL "N"
SYMBOL
A
B
C
- - ,
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H
L
N
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:
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I
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L2
L3
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MILLIMETERS
MIN. I MAX.
5.84 TP
0
0
4:19
4.70
0.407
0.482
3
0
0.407
0
0.533
NOTE
2
0
0.016
0
0.021
0.335
0.305
0.370
0.335
8.51
7.75
9.39
8.50
0.020
0.028
0.029
0.000
0.040
0.034
0.045
0.050
4
3
0.51
0.712
0.74
0.00
1.01
0.863
1.14
1.27
0.250
0.500
0.500
0.562
3
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12
1
6
5
S
2
I I I
6.4
12.7
12.7
14.27
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12
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A
B
C
.
INCHES
MIN._1 MAX.
I
0.008
0.100
0.015
0.019
0.003 I 0.006
0.050TP
1
E
H
L
N
0.200
0.300
0.600
1.000
Q
0.0051 0.050
0.000
0.050
0.300
0.400
S
Z
0.150
NOTE
1
1
2
.1. 0.350
14
3
4
4
MI LLIMETERS
MIN.
MAX.
0.21
2.54
_0.381
0.482
0.152
0.077
1.27TP
5.1
7.6
15.3
25.4
3.9 .l8.8
14
0.13
1.27
1.27
0.00
7.62
10.16
3, ¢B applias between L 1 end L2. ¢lB2 cpplial between L2
and 0.500" (12.10 mm) from.seating plana. Diameter is
uncontrolled in L, and bey~hd 0.500" (12.70 mm).
4. MlnUre from Max. I/.ID.
5. Nl is the quantity of allowable milling leads.
6. N is the maximum quantity of lead positions.
A
B
C
e
E
H
L
N
Q
S
Z
21
4
4
1
1
2
3
1
4
4
3.04
1.91
0.558
0.458
0.102
0.177
1.27TP
15.24
17.78
34.29
29.21
8.25
5.72
24
1.77
0.89
2.79
1.53
17.78
19.05
92CS-19949 A 2
SYM80L
NOTES:
1. Refer to JEDEC Publication No. 95 for Rules for
Dimensioning Peripheral Lead Outlines.
2. Leads within 0.005" (0.12 mm) radius of True
Position (TP) at maximum material condition.
3. N is the maximum quantity of lead positions.
4. Z and Z, determine a zone within which all body
and lead irregularities lie.
0.075 0.120
0.018 0.022
0.004 0.007
0.050 TP
0.600 0.700
1.150 1.350
0.225 0.325
24
0.035 0.070
0.060 0.110
0.700
0.750
MILLIMETERS
MAX.
MIN.
(K) SUFFIX
28·Lead
92SS-4300R3
1, R.fer to Rules for Dimensioning Axial Lead 'Product Outlines.
2. Leads at gauge plane within 0.007" (O.178mml radius of
True Position fTPI at maximum material condition.
!.
3
INCHES
NOTE
MIN.
MAX.
SYMBOL
SYMaaL
1
1
2
MILLIMETERS
MIN.
MAX.
0.21
2.54
0.381
0.482
0.077
0.152
1.27TP
5.1
7.6
15.3
25.4
3.9
B.8
16
0.13
1.27
0.00
0.63
7.62
10.16
(K) SUFFIX
24-Lead
z,
21
NOTES:
21
NOTE
92CS-17271R3
, -H-.
INCHES
MIN.
MAX.
0.230
0
0
0.165 0.185
0.016 0.019
-
-
92CS-19774
SYMBOL
Q
INCHES
MIN.
MAX.
0.008
0.100
0.D15
0.019
0.003
0.006
O.050TP
0.200
0.300
0.600
1.000
0.150 1 0.350
16
0.005
0.050
0.000
0.025
0.300
0.400
A
B
C
e
E
H
L
N
a
S
Z
21
INCHES
NOTE
MIN.
MAX.
0.075 0.120
0.018 0.022
0.004 0.007
0.050 TP
0.600 0.700
1.150 1.350
0.225 0.325
28
0.035 0.070
0.060
0
0.700
0.750
1
1
2
3
1
4
4
MILLIMETERS
MIN.
MAX.
3.04
1.91
0.458
0.558
0.102
0.177
1.27 TP
15.24
17.78
29.21
34.29
8.25
5.72
28
1.77
0.89
0
1.53
17.78
19.05
92CS-20972
606
Application Notes
_ _ _ _ _ _ _ _ _ _ _ _ 607
ICAN-6086
Timekeeping Advances
Through COS/MOS Technology
by S.S. Eaton
Most COS/MOS timing circuits consist of three basic
parts: an oscillator, or main timing standard; some digital
processing logic, usually in the form of frequency-dividing
circuits; and logic-circuit drivers for mechanical or electrical
output devices controlled by the digital processing logic. The
osciUator is perhaps the most important because the accuracy
of the total COS/MOS timing system is entirely dependent
upon the accuracy of the oscillator. This Note discusses basic
oscillator design considerations. practical COS/MOS oscil.
lator circuits, and some typical COS/MOS timing-circuit
applications.
Feedback-Circuit Configuration
A feedback circuit suitable for use with a parallelresonant oscillator circuit is shown in Fig. 4. This circuit,
known as a crystal pi network, is intended for use after an
amplifier that provides a lBO-degree phase shift. The pi
network is designed to provid~ the additional lBO-degree
phase shift reqUired for oscillation. The phase angle for this
type of feedbacK circuit is extremely sensitive to a change in
frequency, a .condition necessary for stable oscUlation. If the
equivalent resistance of the crystal were in fact zero (infinite
assure that the transistor sizes are large enough for the
particular supply voltage used and range of threshold voltages
expected. For any circuit. though, the sum of the threshold
voltages of the n· and p·channel transistors must always be
Jess than the supply voltage.
The oscillator amplifier governs, to a certain extent. the
selection of the components for the feedback network. The
amplifier current consumption is strongly dependent upon
the attenuation across the feedback network. As the
attenuation becomes greater, the signal at the amplifier input
becomes smaller, which, in tum, increases the amplifier
current consumption. Large voltage swings at the amplifier
input cause lillie currellt tu flow because the resistance of
either the n- or p·dtannel transistor is high during a large
portion of the cycle. On the hasis of power cunsiderations.
it is best to design the feedha~k network for a small ,JI1enuation.
BASIC OSCILLATOR DESIGN CONSIDERATIONS
A basic oscillator circuit consists of an amplifier and a
feedback section, as shown in Fig. 1. For oscillation to occur,
the gain. of the amplifier times the attenuation of the
feedback network must be greater than one. In addition, the
total phase shift through the amplifier and feedback network
must be equal to n times 360 degrees, where n is an integer.
These conditions imply that oscillations occur in any system
in which an amplified signal is returned in phase to the
amplifier input after being attenuated less than it was
originally amplified. In such a system, any noise present at
9ZCS-2050e
Fig. 2- Equivalent circuit for a Quartz crym/.
Table I - Typical Component Values for Common Cuts
of Quartz Oscillator Crystals
FREQUENCY
IGAIN.
(I)
32kHz
280 kHz
525kHz
2MHz
Cut
XYBar
OT·
OT
AT
Rslohms)
40K
t820
t400
82
25.9
12.7
0.52
tIHvI- '4800
92CS'2050!1
Fig. 1- Basic oscillator circuit
the amplifier input causes oscillation to build up at a rate
detennined by the loop gain, or afj product, of the over·all
circuit.
The frequency stability of an oscillator is primarily
dependent upon the phase-changing properties of the
feedback network. For high stability, quartz crystals and
tuning forks are commonly used as feedback network
ele~l1ents. The quartz crystal is the more popular because of
its higher Q or greater inherent frequency stability.
Selection of Crystal Operating Mode
Fig. 2 shows the equivalent circuit of 1\ quartz crystal,
and Table I lists typical component values of the elements
included in the equivalent circuit for different 'crystal cuts
and operating frequencies. The basic circuit can be resolved
into equivalent resistive (Re) and reactive (Xc) components.
Fig. 3 shows curves of these components as functions of
frequency for a typical 32.768-kHz crystal. Fig. 3(b) shows
two points at which the crystal appears purely resistive, (i.e.,
points at which Xc = 0). These points are defined as the
resonant (fr) and antiresonant (fa) frequencies. Seriesresonant oscillator circuits are designed to oscillate at or near
fro Parallel-resonant circuits oscillate between fr and fa,
depending upon the value of a parallel loading capacitor, as
discussed later. In contrast to series-resonant circuits, parallel
resonant·circuits work best with amplifiers that have high
input impedances. The parallel-resonant circuit, therefore, is
most applicable to crystal oscillators that employ COS!MOS
amplifiers. I
I
608
Ct (pF)
0.00491
0.0125
0.00724
0.Ot22
Co (pF)
2.85
5.62
3.44
4.27
Co /C1
580
450
475
350
Q
25000
25000
30000
80000
_10"
Q). a change in the phase angle of the feedback circuit would
not cause any change in oscillator frequency; the frequency,
therefore, would be insensitive to any phase change in the
amplifier. Though practical crystals allow only a slight
change in frequency for large variations in phase angle, the
amplifier phase angle should, to the extent possible, be made
independent of temperature and supply-voltage variations in
order to minimize the phase compensation required of the
feedback network. Any required phase compensation will, of
course, dictate a corresponding change in the frequency of
oscillation consistent with practical values of crystal Q. For
this reason, the equivalent resistance of the crystal should be
maintained as low as possible, and the amplifier should be
designed to roll off at frequencies greater than the crystal
frequency.
Oscillator Amplifier
Fig. S shows a COS/MOS amplifier circuit that may be
used to provide the amplification function in a crystal·
con trolled oscillator. The amplifier is biased so that the
output voltage VOUT is equal to the input voltage VIN or
typica1ly is equal to one-half the supply voltage VDD, (i.e.,
Your = YIN = YOO/2). Biasing is accomplished by means
of a resistor that has a value high enough to prevent loading
of the feedback network, yet that is low in comparison to
the amplifier input resistance. Resistor values of 10 to Soo
megohms will satisfy these criteria; however, lower values in
the order of IS megohms are generally u!ed to allow greater
input leakage without any severe change in bias point. The
gain of the amplifier varies with supply voltage, the size of
the n- and p-channel MOS transistors. and the sum of the
threshold voltages of the n- and p-channel transistors. When
an oscillator amplifier is designed to roll off at frequencies
greater than the crystal frequency. care must be taken to
,u_
+-1--+--+---+--+---+----11
:[1--
_Io~eli::::=::i==.- .
32.160
32.710
32.780
32.190
FREQUENCY-KHI
Ibl
Fig.3- Impedance characteristics of a quartz oscillator
crystal: (a) equillalent crystal resistance as a
function of frequency." (bl equillalent crystal
reactance as a function of frequency.
"
"
st
Fig. 4- Crystal pi·type feedback network.
V,N
.f
rl
P
VOUT
~vss
Fig. 5- COS/MOS amplifier.
ICAN-6086
Equivalent Crystal Resistance
The equivalent resistance Rs 01 the crystal should be
maintained as small as possible in order to obtain minimum
attenuation across the feedback network. For any given
circuil, the oscillator current always increases wilh a rise in
crystal resistance. This factor and stability considerations
provide strong arguments for the purchase of crystals that
have low series resistance, although the usual cost tradeoffs
prevail.
Crystal Load Capacitance
Another factor that influences the over-all power
consumption is the size of the pi-network capacitor at the
amplifier output. For minimum current consumplion, this
capacitor, obviously, should be kept small. This condition,
however, does not always imply high frequency stability. The
choice of the capacitor value first involves a determination of
the over·a11 crystal load capacilance. The phase angle of the
feedback network approaches 180 degrees when the crystal
equivalent reactive component Xe is equal to the reactance
(XCU of a capacitor placed in parallel with the crystal.
Fig. 4 shows that the effective capacitance across the crystal
consists of the two pi-network capacitors in series. If the
value of the equivalent reactance Xe at the crystal frequency,
as may be determined from Fig. 3(b), is equal to the value of
the crystal load capacitance CL' then the equivalent value
of the two series-connected pi·network capacitors can be
calculated from the following relationship:
Temperature Stability
Another important oscillator consideration is temperature stability. Most crystals have a negative parabolic
temperature coefficient. 2 Fig. 7 shows a typical curve "fthe
variation in crystal frequency as a function of temperaturp
The frequency of the total oscillator circuit also exhibits a
simih.ll temperature dependence. Temperature compensation
of the over-all oscillator circuit can be achieved by use of a
capacitor that has a positive parabolic temperature coefficient in the pi feedback network.3 For comparison, Fig. 7
also shows a typical resultant curve for the over·all circuit.
The temperature characteristics of a crystal are determined to a large extent by the crystal cut. Popular
low-frequency cuts include the NT and XV Bar. The XV Bar
is the more popular of the two types because it can be made
smaller for a given Q and is easier to trim. The disadvantage
of a slightly lower shock resistance of XV Bar crystals is
compensated by the superior aging chacteristics of this type.
The choice of the total equivalent load capacitance CL
"only fixes the series sum of the two pi-network capacitors.
The individual capacitors themselves can be found from the
following equations:
(2)
Cs = 4CI1(3 + 5fReCLl
(3)
The actual value of Cs used in the feedback circuit
should be about 3 picofarads less than the calculated value to
allow for the amplifier input capacitance. The value of the
amplifier output capacitor C1 should not nonnally be fixed.
A trimmer capacitor should be" placed in parallel with, or
used in place of, a fixed output capacitor to allow for
variations in stray capacitance and circuit components. The
mid-range value of the output capacitor combination should
be equal to the calculated value of CT.
Frequency-Trimming Capability
The required capacitance range for the osciUator trimmer
capacitor is determined by the variation in oscillation
frequency with a change in load capacitance. 2 The total
frequency-trimming range of a crystal-controlled oscillator
circuit is mainly a function of the crystal characteristics, or
more explicity,' is inversely proportional to the slope of the
crystal reactance curve, shown in Fig. 3(b). The slope of this
cUlVe is a function of the difference between the resonant
frequency fr and the antiresonant frequency fa. This
frequency difference, in tum, is a function of the crystal
capacitance ratio Co/C I, where Co and C I are the inherent
shunt and series capacitances, respectively, of the crystal
structure, as shown in Fig. 2. The slope of the reactance
curve is also a function of the total external crystal load
capacitance CL. As shown in Fig. 3(b). this slope decreases as
the equivalent reactance increases, (i.e., for smaller values of
the capacitance CU. Fig. 6 and Table II show trimming-range
data for a typical 32.768-kHz crystal that has a capacitance
ratio ColCI of 580. These data show that smaller values of
load capacitance result in greater trimming-range capability.
7- Effect of temperature on crystal frequency.
•
---....
V
.V
TURNOVER
TEMPERATURE
..
•
·3. -60
(I)
The value of the load capacitance CL, in general, is chosen
first, and the crystal manufacturer is required to cut the
crystal to oscillate at the desired frequency for the specified
value of load capacitance_
The choice of a load capacitance is important in terms of
over-all power consumption and frequency stability. Higher
values of CL generally improve frequency stability. but also
increase power dissipation. The timing industry presently
seems to have standardized on values of CL between 10 and
20 picofarads.
TEMPERATURE-·C
Fig.
~
..
~r
2.
2.
T,
RELATIVE TEMPERATURE _·C
6.
f.f
...
•
•
•
LOA 0 CAPACITANCE -pF
,I
Crystal Shock Resistance and Aging Rate
A prime concern of the timing industry today is that of
crystal shock resistance and aging. The aging of a crystal
results primarily from aging of the mounting material rather
Table II - Trimming Oa.. for a Typical 32-kHz
Quartz Oscillator Crystal
TRIM
LOAO CAPACITANCE, CL
5pF
11.5 pF
20pF
± 20 PPM
-0.45
+0.51
± 25 PPM
-.55
+.65
± 30 PPM
-0.66
+0.79
pi
pi
pi
-1.6
+2.0
-1.9
+2.6
-2.3
+3.3
pi
pi
pi
-3.7
+5.5
-4.5
+7.3
-5.2
+9.3
pi
pi
pi
32pF
-B.O
+14.7
-9.4
+20.5
-10.7
+27.9
pi
pi
X
·I
iI
-40
i
•
20
,., '"
4•
TEMPERATURE _·c
1
!,
!
i
.k{
,
I
.+-
60
00
I
Fig. 8- Frequency·temperature characteristics for various
crystal cuts: fa) XY-8ar and NT cu~' (b) A T cut.
than from aging of the quartz itself. The mounting material
enters into the crystal equivalent circuit, and the slowest
aging rate results when the mount consists of the least
ampunt of supporting material. This condition of course,
results in lower shock resistance, and an optimum trade-off
r::';f J:.e achieved. At present, 32-kHz crystals can be made
that can withstand a mechanical shock of about 1500 G's
applid for O.S millisecond and that have aging rates that
"sult in a frequency change of 2 to 5 parts per million for
the first" year and essentially no aging thereafter. Any
mechanical or thermal shock. however, will interrupt the
normal aging process. The aging rate of 2 to 5 parts per"
million presently appears acceptable to the timing industry,
although shock resistances of 3,000 to 5,000 G'sare desired.
This shock level corresponds approximately to the shock
experienced by dropping the crystal from a height of one
meter onto a hardwood floor.
PRACTICAL OSCILLATOR CIRCUITS
The basic amplifier. feedback-network, and crystal
considerations discussed in the preceding paragraphs can be
combined in the design of COS/MOS oscillator circuits. In
the circuits, the crystal selected has an equivalent resistance
Re of 50 kilohms and is cut to operate at a frequency of
32.768 kHz with a load capacitance CL of 10 picofarads. The
values of pi feedback-network capacitors CT and Cs can be
calculated by use of Eqs. (2) and (3) as CT. = 43 picofarads
and Cs = 13 picofarads. The value of the feedback-network
resistance R can be calculated as follows:
(3Xc
pi
,
i
typical 32·kHz crystal.
Crystal Dimensions
Size is also an important consideration in the design of
oscillator crystals. The length of quartz required for any
given cut is inversely proportional to the square root of
frequency. Dimensions for a typical packaged 32-kHz, XY
Bar crystal are 0.6 inch by 0.2 inch by 0.11 inch. The
smallest XV Bar crystals currently available have dimensions
in the order of 0.53 inch by 0.2 inch by 0.11 inch. A I·MHz
AT-cut crystal is significantly larger; however, dimensions
again decrease with frequency. Crystal manufacturers are
currently working to develop wristwatch-size AT-cut crystals
with the anticipation of circuit improvements that will allow
low~current operation at high frequencies.
!
,
Fig. 6- Frequency as a function of load capacitance for a
AT -cut crystals, when used at frequencies greater than I MHz,
are characterized by excellent temperature stability and
ruggedness. Temperature characteristics for this type of
crystal cut as well as for the XY Bar and NT types are shown
in Fig:B.
!
+ 0.27 !te) (Xc - O.B Re)
R=
16 Re
"'IMU
609
leAN-60S6
This value is the maximum value of resistance alluwd for a
minimum feedback-network attenuation of 0.75. a value
chosen on the basis of power and stability l,;'ollsid~r:JIi()ns.1
The cak'ulalct.l value of R includes any fixed resistance plus
the 3mplilicf output resistance. Because the output resistance
is often appreciable and varies wHh supply vuhagc. transistor
size, and threshold voltages, it is generally best to add
resistance experimentally until the desired power consumption 31lJ frequency stability are reached, The effect of this
resistance on uperating curren I and frequency stability can
be predicted from data given in Table III for the three
different COS/MOS crystal oscillator circuits shown in Fig. 9.
In each circuit. the pi-network capacitors IT and lS are 39
picofarads and 10 picofarads. respectively. These capacitances arc slightly less than the calculated values because of
stray and amplifier capacitances.
The circuit shown in Fig. 9(a) combines the amplifier and
feedback circuits shown in Fig. 4 and 5. Although theory
predicts that an increase in the values of the feedbacknetwork resistor R will result in increased frequency
stability. the circuit performance data given in Table III show
no significant improvement in this characteristic. This result
indicates that the circuit instability can be attributed almost
entirely to phase instabilities of the amplifier. This assumplion is verified by data taken from the circuits shown in
Figs.9(b) and 9{c) in which the required feedback-network
resistance is incorporated into the amplifier as a fixed value.
The resistors essentially fix the amplifier phase shift so that
greater stability results. As the data show. usc of these
resistors also results in a decrease in the total current
consumption. Because of the two fixed resistors,1he circuit
of Fig. 9(b) shows the least current consumption and also the
greatest stability.
require pulses al least every second. minute, and hour. The
ne..:esSity for frequency division becomes clear if o'ne
considers the wide variety of timing Intervals that may be
required for cerlain applications.
The basic frequency.dividing circuit, shown in Fig. II,
consists of a master-slave D-type flip.nop connected as a
binary counter stage. N stages may be cascaded with the final
output frequency equal to 2-N times the input frequency.
Division by integers other than powers of 2 can also be
accomplished by use of gating techniques. For example, a
dividc·by-60 counter implemerrted as shown in Fig. 12, can
be used to obtain minutes from seconds.
~i:i7N80'
'j..",""'r-'1----..._--l[
SILICON
GATE
A tuning-fork motor consists of two coils wired in series
and wound on either side of the fork. A subdivision of the
crystal frequency drives the coils which electromagnetically
vibrate the fork. The fork can be linked to an index wheel
that, in turn. can drive the hands of a watch.
Table III - Typical Oscillator Dati
Circuit
Voo
Cunwnt
R(m
(Volts)
(PA)
9(.1
lOOK
200K
9(bl
lOOK
150K
1.60
4.0
1.45
3.1
1.60
3.1
1.45
2.4
1.60
2.9
1.45
2.1
1.60
2.3
1.45
2.0
1.1
1.5
1.60
1.8
1.45.
1.6
1.1
9(el
F.-....,
Value of
200K
300K
Stability
VOO "1.45V
to1.8V
5.0
1.45
4.4
1.60
3.5
1.45
3.0
SILICON
GATE
Fig. 9-
2.6
2
2.6
0
.3
.2
.6
Typical COS/MOS crysra/·oscilfaror circuits.
V
2
V
segment of the display to assure long life. For this purpose, a
6()'Hz squ'are wave is applied to one input of each of seven
exclusive-OR gates. The logic state present at the other input
determines whether the segment will transmit or scatter light.
I
•
24681012141618202224
.5
AMPLIFIER FEEOBACK RESISTANCE
CRt I-MEGOHMS
'2CS-Z04U
Fig. 10- Oscillator frequency as a function of amplifier
feedback resistance.
As mentioned previously. Ihe amplifier feedback resistor
should not significantly load the crystal feedback network.
The resistor value at which loading begins. to occur can be
detennin~d from a curve of circuil operating frequency as a
function of feedback resistance. Fig. 10 shows such a curve
for Ihe circuit shown in Fig. --.f<>-"-';'IV--1~
~~~~Nr
.
! . o ,!~.
DECOOERI
~-f=~+==j[
~:=::)----+()o---'\~--t
L _______ ...J
COSIMOS T1MING-CIRCUIT APPLICATIONS
The choice of a readout device depends. of course, upon
the application involved and to a certain extent upon the
individual characteristics of the device itself. Special
considerations for readout devices are perhaps best treated in
a discussion of special requirements for three important
timing·circuit applications, namely, wristwatches. wall
clocks. and automobile clocks.
AVERAGE VOL.TAGE
ACROSS ANY SEGMENT
SEGMENT
I
Fig. 16- COS/MOS /iquftl.cty1tB1 driving cUr:uit.
611
ICAN-6086
Table VI - Life Data for Typical Baneries
Eveready
Type'
FROM
SEVENSEGMENT
DECODER
Life
(Oaysl
Mallory
Type'
Size
Type
915
M15F
AA
CarbonZinc
E91
MN1500
AA
Alkaline
200
935
M14F
C
CarbonZinc
385
150
E93
MN1400
C
Alkaline
575
950
M13F
0
CarbonZinc
800
E95
MN1300
0
Alkaline
1100
All life data assumes a continuous drain of 250 pA and an
end· of-life voltage of 1.1 V.
FRON"" N PLUS N DECODED OUTPUT
COUNTER
, Fig. 16- Multiplexing driving circuit for light-emitting diodes.
Mallory cells is shown in Table IV. Most of the cells listed
will last at least one year with a motor current of 10
microamperes and a total oscillator and divider current less
than 5 microamperes at an oscillator frequency of 32.768
kHz. The voltage for both types of cells is relatively constant
during the active life listed and falls off rapidly thereafter.
Typical end-oC-life voltages at 1.1 volts for mercury cells and
1.45 volts for silver-oxide cells. Either type of cell works
equally well with RCA silicon-gate COS!MOS circuits which
operate from supply voltages as low as 1~1 volts.
Wall Clocks
Size and power limitations for clocks are not as
restrictive as those for wristwatches. For this reason,
lower-cost, higher-frequency crystals may be used_ The
optimum range of crystal frequencies presently appears to be
from 131 kHz to 524 kHz_ All the osciUator considerations
given previously for operation at 32 kHz apply equally well
to this higher frequency range_ The oscillator circuit
configuration shown in Fig.9(b) is still the optimum type;
however, the value of the source resistors must be del;reased
to assure adequate gain at the higher frequencies. Source
resistors afe often best chosen experimentally by gradually
increasing the resistance until an output voltage swing of 30
to 70 per cent of the supply voltage VDD is reached. Data
taken from a typical 262-kHz oscillator circuit that employs
two lO-kilohm source resistors and a DT -cut, 262-kHzcrystal
are shown in Table V. The table also shows typical counter
current.
The most popular readout devices for clocks are
conventional-hand movements and liquid-crystal displays.
Continuously operating light-emitting-diode numerals can·
sume too much current even for long life of C- and D-size
batteries. In contrast. a typical RCA fou[-digit Iiquid-crystal
display having a O.4-inch-bY-0.6.inch numeral consumes only
100 microamperes of current with all segments energized.
Motors for driving the clock hands are typically of the
balance-wheel or continuous1y rotating synchronous types.
Sensitivity to vibration is usually not a restriction; hence, the
balance wheel motor can be successfully used in place of the
more expensive stepping motor. Clock motors typically
require about 300 to 450 microwatts of power, or average
currents of 200 to 300 microamperes at 1.5 volts.
These currents, together with the oscillator and counter
currents given in Table V. can now be compared with
typical battery capacities. Battery information extrapolated
from published Eveready data on popular AA-, Co, and D-size
cells is listed in Table V1.5 Most of the battery current is
consumed by the motor, and if a total current of 250
microamperes is assumed, the data show a carbon-Zinc C cell
as the minimum size battery required for one year of life.
Auto Clocks
Auto clock circuits are somewhat unique in that power
considerations are not nearly as restrictive as in other
portable applications. Although the low-power feature of
COS/MOS circuits is helpful, the main advantages obtained
Type
WH3
Voltage
Capacity
pAyn.
Heigh.
Un.)
Iin.1
1.35
25
0.208
0.455
0.455
1.55
19
0.210
W4
1.35
11
0.139
0.455
WSll
1.56
11
0.164
0.455
10Rl0l
(EXPI
0.190
0.610
1.35
36
10 L 19
(EXPI
1.55
27
0.190
0.610
W04
1.36
14
0.149
0.594
W05
1.36
23
0.110
1.003
612
Oscillator
Current
(pAl
Counter
Current
Product
VOO
(Voltsl
Silicon-Gate
1.IV
7
7
1.3V
_ 9.5
9
1.5V
11.5
10
1.6V
12.5
11
2.2V
21
10
3.0V
35
13
.
.,
,.
.,
(~AI
Freq.
Stability
(ppml
2.0 ppm
1.4
1.2
1.8
Diameter
WS 14
Type A
Table VII- Typical High-Frequency Data for
COS/MOS Oscillator and Counter
Circuits tLow-Voitage Product}
Freq.
(MHzI
Oscillator
Current
(mAl
5
1
12
1
VOD
(Volts)
Counter
Current
(mAl
Motor
Current
(mAl
0.28
0.125
1.3
0.275
5V
2-5mA
5
2
0.37
0.250
12
2
1.5
0.550
5
3
0.40
0.375
12
3
1.9
0.825
5
4
0.43
0.500
12
4
2.3
1.1
12V
5-10mA
5V
3·8mA
-12V
8·20mA
Table V - Typical Data for 262-kHz Oscillator
and Counter Circuits
Low-Voltage
.TablelV - Typical Data for Mallory Watch Cells
For minimum starting voltage. relatively small capacitors
shouJd be used in the pi-feedback network, and no source
resistors should be added to the amplifier. As indicated by
data taken on the circuit shown in Fig.9(b) and shown in
Table VII, low power can still be maintained even when the
source resistors are not used.
from the use of COS/MOS in automobile clocks, or in any
automotive application, are those of wide operating voltage
and temperature range and high noise immunity.
With little restriction on power. the choice of a crystal
depends mainly on cost. Crystals typically ~sed for automobile timing applications are AT-cut types that operate at
frequencies between I MHz and 4.2 MHz. The oscillator
considerations discussed earlier also apply to these frequen. cies; however, as the frequency increases, it becomes
increaSingly difficult to maintain a low start'ing v.oltage at a
low current. AI high frequenCies, the starting voltage and
current are inversely proportional and are controlled mainly
by the vaJues of the capacitors on the pi-type feedback
network and the size of the COS/MaS amplifier transistors.
The upper limit of the crystal frequency depends not so
much on power consumption as on the minimum supply
voltage aJlowed for circuit operation. The minimum auto·
mobile battery voltage is generally considered to be 5 volts;
however. the supply voltage for the timing circuit can be
considerably less than this value depending upon the design
of the transient protection circuit, as discussed later. Table
VIII lists minimum COS/MOS supply voltages for typical
oscillator circuits. The values shown permit design at two
temperatures. The lower temperature is often considered
adequate by auto companies' with the opinion that the
minimum battery voltage of 5 volts rarely, if ever. occurs at
high temperatures ..
The osclllator in a typical auto clock circuit is followed
by a number of frequency-dividing stages. the last stage of
which is frequently used to drive a motor. Long counter
chains are required because of the high oscillator frequency;
however, the power diSsipation of COS/MOS circuits is so
low th~t the number of stages is only restricted by chip size
limitations. Because COS/MOS circuits consume current only
during switching transitions, each counter stage averages
one-half the current of the previous stage. The first counter
stage, therefore, consumes as much current as all· of the
follOwing stages combined for a counter of infinite length.
Little difference, then, exists between the power consumption of a ten-stage or thirty-stage COS/MOS counter. Table
VII lists, in addition to the oscillator current, typical values
of counter current, as well as some typical ranges of peak and
average motor currents.
ICAN-SOBS
Current data. such as that shown in Table VII. are
necessary [or a proper design o[ the transient protection
circuit. an essential part of any automobile digital logic
system. Automobile manufacturers disagree on the maximum
amplitude and decay o[ transient voltage; however. values
often used are maximum transients of +120 volts and -90
volts, each decaying exponentially with a maximum time
constant of 45 milliseconds. Because standard COS/MaS
circuits are rated for a maximum supply of IS volts. a
protection circuit must be included between the battery and
the COS/MOS logic.
Table VIII - Minimum Operating Voltages for
COS/MOS Integr.l.od Cin:uits
Low·Voltage Product
Freq.
(MHzI
Silicon-Gate Product
1
2
3
4
1
2
3
4
2.9
3.1
3.5
4.0
1.6
2.0
2.6
3.0
3.0
3.3
4.0
5.0
1.8
2.6
3.4
4.0
Min.
Voltage
a.250C
Min.
Voltage
at 82°C
180°F
Fig. 17 shows a transient-voltage protection circuit that is
[requently used. The zener diode regulates the voltage supply
for the clock circuits. and the capacitor and series diode
prevent timing losses during negative transients. For minimum zener current during transients. the maximum value of
R should be based on the minimum circuit operating vo1tage
and the peak current drawn by the logic circuit and motor at
the minimum battery voltage_ The minimum zener breakdown voltage is then determined by subtraction o[ the
product of the minimum current drain at the normal baUery
voltage and the value of R just chosen [rom the battery
voltage. A zener breakdown greater than this voltage assures
that no unnecessary current will be drawn by the zener
during normal automobile operation.
In the design of a typical transient-voltage protection
circuit, it is assumed that the minimum battery voltage is 5
volts. that the minimum circuit operating vohage is 3.5 volts
at a crystal frequency of 3.145728 MHz. and that a peak.
current o[ 3 milliamperes is obtained at 5 volts. The value of
the resistance R is then found as (S - 3.5 + 0.7)/3~2S0
ohms. With a minimum current of 5 milliamperes at 12 volts.
the minimum zener voltage becomes 12 - 5(0.250) = 11_75
volts. For a +120-volt transient. the zener could then
consume a peak current of (120 - 11.8)/250 = 0.4 ampere.
For a maximum zener voltage of 13 volts. the dynamic
impedance of the zener must be less than (22V - 13V)/.4A =
22 ohms. Components chosen in this manner will provide
adequate protection for anticipated transients.
Both protection-circuit diodes can be integrated onto the
COS/MaS chip. When located as shown in Fig. 17. the series
diode need only have a breakdown rating of about 12 volts.
Zener diodes that have breakdown ratings o[ 4.5 to 6.0 volts
or any multiple thereof can also be integrated onto the
COS/MOS chip. The breakdown rating can also be increased
in O.7-volt steps by addition of forward-biased diodes in
series. Characteristics of two typical zener diodes integrated
in series are shown in Fig. 18. Fig. l8(a) shows the area
around the ·'knee" of the breakdown region. and Fig. 18(b)
shows the higher-current region useful for determining the
dynamic resistance. From the slope of the line, the typical
SUPPt.V
=
1100 •. TV.
Another important zener characteristic is dynamic
impedance. DUring a current surge. the voltage across the
zener must not rise to a damaging level. A vaJue of 22 volts
for the 45-millisecond time constant appears safe forstandard COS/MaS circuits.
2.
_-' OOY
I P~R
1- -
-I o;Y
---I
1-
I
_~
L_
_I
I
rL
-~
~
r-
~
_J
'0'
I I
1
L-
..1
i
rI-
I
L
1
1- -
I
1
II
I ,
J I
I
I
., PER
I
,
J
I
II- -
""
- -I
LL_
I- Fig. 17- Automobile transient-protection circuit
~
I
I
t
lo".r TO
~of
-...,
l-
"'~TERY
R
TIMING
CIRCtJIT
l
r
L_
--:_I l
!~
~
'v
- OIV
- I PER
=1
I o~v
-i
--I
- -II
- -I
J
1>,
- -I
_J
Fig. 18- OSICillograph tracings mowing characteristics of an
inre,ated zener diode: (a) low-current region,' (bl
high-current region.
dynamic resistance for two diodes is found to be 17.6 ohms
total. or 8.8 ohms per diode. The diodes are rated to
withstand a O.5-ampere surge current that' decays with an
80-millisecond time constant. The zener diode. then. is
compatible with present automobile protection requirements,
and integration of this component should represent a
considerable cost saving. especially- when integrated with the
series diode.
Other Applications
Although wristwatches and clocks of various types are
important applications of COS/MaS timing circuits. they are
certainly not the only timing applications which can benefit
from the unique features of COS/MaS logic. Applications
such as fuze timers. feeding systems, automatic sprinklers.
incubator timers, and other similar systems can be designed
from information provided on the oscillator and counter
with only the output device unique to the particular
application. Automobile applications for COS/MOS circuits
are almost endless. One can think of speed controllers. digital
speedometers, miles per gallon indicators. and perhaps even
estimated-time-of-arrival indicators that. on the basis of the
given total mileage, would update the time on it dynamic
basis [rom information provided by the speedometer.
odometer. and clock.
CONCLUSIONS
The primary advantage of electronic timing circuits over
conventional mechanical methods of timekeeping lies in the
greatly increased accuracy permitted by the highly stable
crystal-controlled oscillator circuit. Although crystal oscillator circuits have existed [or some time, their usefulness in
portable applications has been somewhat limited because of
the high current consumption required by the follOwing
digital logic. The advent of COS/MaS integrated circuits now
permits the design of complete low-power timing systems.
The impact of COS/MOS on timing applications is perhaps
equalled by the recent development of liqUid-crystal displays
and dC-la-de converters that allow low-power continuously
operating digital displays. Certainly. no great technological
barriers now exist for the use of electronic timing circuits in
a wide variety of applications. The search. no doubt, will
always continue for the ideal timekeeping deVice; however. it
should be apparent from the information presented that the
ideal timekeeping unit can now be more closeiy approached
than ever before.
REFERENCES
I. Eaton, S.S•• "Micropower Crystal-Controlted Oscillator
Design Using RCA COS/MOS Inverters," RCA Applica.
tion Note ICAN 6539, 1971.
2. "Frequency Control Devices." Catalog No. 670. Northern Enginnering Laboratories, Burlington, Wisconsin.
3. Yoda. H .• "Low Power Crystal Oscillator for Electronic
Wrist Watch," Mihon Dempa Kogyo Co .• Ltd .• Japan.
1971.
4_ Schindler, H.C .• "Liquid Crystal Dynamic Scattering for
Display Devices," RCA Publication PE·533, 1972.
5. Eveready Battery Applications Engineering Data. Union
Carbide Corp., 1971.
613
ICAN-6101
The RCA COS/MOS Phaae-Locked-Loop
A VeraatileBuilding Block for Micro- Power
Digital and Analog Applicationa
INTRODUCTION
Phase-Iocked.loops (PLL's). especially in monolithic
form, are finding significantly increased usage in signalprocessing and digital systems. FM demodulation, FSK
demodulation, tone decoding, frequency multiplication,
signal conditioning, clock synchronization, and frequency
'v
i
PLL described in this Note is the COS/MOS CD4046A.
which consumes only 600 microwatts of power at lO kHz, a
reduction in power consumption of 160 times when
compared to the 100 miIJiwatts required by similar monolithic bipolar PLL's. This power reduction has particular
significance for portable battery-operated equipment. This
Note discusses the basic fundamentals of phase-locked-loops,
and presents a detailed technical description of the COSI
MOS PLL as well as some of its applications.
TECHNICAL DESCRIPTION OF COS/MOS PLL
Fig. 2 shows a block diagram of the COS/MOS
eD4046A, which has been implemented on a single
monolithic integrated circuit. The PLL Structure consists of a
low-power, linear, voltage-controlled osclllator (VCO), and
two different phase comparators having a common signalinput amplifier and a common comparator input. A S.2-volt
zener is provided for supply regulation if necessary. The VCO
can be connected either directly or through frequency
dividers. to the comparator input of the phase comp-arators.
The low-p;:;:; nIter is implemented through external parts
because of the radical configuration changes from application
to application Uld because some of the components are
non-integrable. The eD4046A is supplied in a 16-lead,
dual·ln·llne. ceramic package (CD4046AD); a 16-lead. dual·
1n~1ne. plastic package (CD4046AE); or a 16-lcad flat·pack
(CD4046AK). [t is also available in chIp form (CD4046AH).
614
VOlTAGE
~
r
0
90
80
SIGNAL-TO- COMPARATOR
INPUTS PHASE Of"f"[RENCE
Fig. 4- f'haIe.compartltor / chonctMiltiCfl.t
/ow-ptns flltBr output.
Fig. 2- COSIMOS PLL block diB(ff'am.
Phase Comparaton
Most PLL systems utilize a balanced mixer composed of
weil-controlled analog amplifiers· for the phase-comparator
section. Analog amplifiers with well-controlled gain characteristics cannot easily be realized using COS/MaS technology. Hence. the COS/MOS design shown in Fig. 3
employs digital-type phase comparators. Both phase comparators are driven by a common-input amplifier configuration composed of a bias stage and four. inverting-amplifier
stages. The phase-comparator signal input (terminal 14) can
be direct-coupled provided the signal swing is within
COS/MOS logic levels [logic 0 .. 30% (VDD·VSS). logic
I ;;. 70% (VDD.YSS) J. For smaller input signal swings.
the signal must be capacitiveJy coupled to the self·hiasing
amplifier at the signal input to insure an over-driven digital
signal into the phase comparators.
Fig. 1- B/rxk diB(ff'Bm of PLL.
difference of the input signal and the veo. The error
voltage, Ve(t), is filtered and applied to the control inp~t of
the VCO; Vd(t) varies in a direction that reduces the
frequency difference between the veo and signal-input
frequency. When the input frequency is sufficiently close to
the veo frequency, the closed-loop nature of the PLL forces
the veo to lock in frequency with the signal input; i.e.,
when the PLL is in lock, the· veo frequency is identical to
the signal input except for a finite phase difference. The
range of frequencies over which the PLL can maintain this
locked condition is defined as the lock range of the system.
The lock range is always larger than the band of frequencies
over which the PLL can acquire a locked condition with the
signal input. This latter band of frequencies is defined as the
coprure range of the PLL system.
Yoo
~ Yool2
synthesis are some of the many applications of a PLL. The
REVIEW OF PLL FUNDAMENTALS
The basic phase-locked-loop system is shown in Fig. 1; it
consists of three parts: phase comparator,low-pass filter, and
voltage-controlled oscillator (VeO); all are connected to
form a closed-loop frequency-feedback system.
With DO signal input applied to the PLL system, the error.
voltage at the output of the phase comparator is zero. The
voltage, Vd(t), from the low-pass tilter is also zero, which
causes the veo to operate at a set frequency, fo, called the
center frequency. When an input signal is applied to the PLL,
the phase comparator compares the phase and frequency of
the signal input with the veo frequency and generates an
error voltage proportional to the phase and frequency
One characteristic of this type of phase comparator is
that it may lock onto input frequencies that are close to
harmonics of the veo center-frequency. A second characteristic is that the phase angle between the signal and the
comparator input varies between ()O and ISOO, and is 9oo at
the center frequency. Fig. 4 shows the typical, triangular,
phase-ta-output, response characteristic of phase-comparator
I. Typical waveforms for a COS/MOS phase·locked·loop
employing phase-comparator I in locked condition of fo is
shown in Fig. S.
Ph. .-comparator I is an exclusive~R network; it
operates analagously to an over-driven balanced mixer_ To
maximize the lock range, the signal and comparator input fre·
quencies must have SO-percent duty cycle. With no signal
or noise on the signal input, this phase comparator has
CCMPI.R,I,'OR
INPUT
Fig.
3-
Sdlem8tic of COSIMOS PLL phlllJeoCOmporator
IIICtlon.
an average output voltage equal to VDD/2. The low-pass
filter connected to the output of phase-compar;ator I supplies
the averaged voltage to the veo input, and causes the veo
to oscillate at the center frequenCy (fo)' With phase-comparator I, the range of frequencies over which the PLL can
acquire lock (capture range) is dependent on the low-pass-mter
characteristics, and can be made as large as the lock range.
Phase-comparator I enables a PLL system to remain In lock in
spite of high amuunts of noise in the lnput signal.
SIGNAL INPUT ITERM.141
r-L.rL..
f~:~1r8::~~~~41~ ~
rur..r".c~"rrW I
YeO INPUT 'TERN.91~
• LOW-PASS FILTER
OUTPUT
.JULSLj"--Yoo
...............
-vss
Fig. 5- TypiCB/ waveforms for COSIMOS phaselocked loop employing phBJe-COmparator I
in locked condition of f 0-
Phne-compilnrtor II is an cdge-controlled digital memory
network. It consists of four flip-flop stages, control gatina,
and a three-state output circuit comprising p and n driven
having a common. output node as shown in Fig. 3_ When the
p-MOS or noMOS drivers are ON, they pull the output up to
Von or down to V.sS .. respectively. This type of phase
comparator acts only on the positive edges of the signal·
and comparator-input signals. The duty cycles of the signal
and comparator inputs are not important since positive
transilions control the PLL system utilizing this type of
comparator. If the signal-input frequency is higher than the
comparator·input frequency, the p-MOS output driver is
maintained ON continuously. If the signal-input frequency is
lower than the comparator·input frequency, the noMOS
output driver is maintained ON continuously. If the signaland comparator-input frequencies are the same, but the
signal input lags the comparator input in phase, the noMOS
output driver is maintained ON for a time corresponding to the
phase difference. If the signal- and comparator-input fre·
quencies are the same, but the signal input leads the com·
parator input in phase, the p-MOS output driver is maintained
ON for time corresponding to the phase difference. Subsequently, the capacitor voltage ot" the low-pass filter connected to this type of phase comparator Is adjusted until the
signal and comparator input are equal in both phase and frequency. At this stable operating point, both p- and noMOS
~utput drivers remain OFF, and thus the phase-comparator
output becomes an open circuit and holds the voltage on the
capacitor of the low-pass filter constant_ Moreover, the signal
at the "phase pulses" output is at a high level, and can be used
for indicating a locked condition. Thus, for phase-comparator
11, no phase difference exists between signal and comparator
input over the full veo frequency range_ Moreover, the power
dissipation due to the low-pass filter is reduced when this
type of phase comparator is used because both the p. and nMOS output drivers are OFF for most of the signal·input
cycle. It should be noted that the PLL lock range for this
type of phase comparator is equal to the capture range,
independent of the low-pass filter. With no signal present at
the signal input, the veo is adjusted to its lowest frequency
for phase-comparator II. Fig. 6 shows typical waveforms for
a COS/MaS PLL employing phase-comparator II in a locked
condition.
ICAN-6101
SIGNAL INPUT ITERM 141
yeo OUTPUT ITERM 41'
eOt.lPARATOR INPUT
ITERM31
PHASE COMPARATOR II
OUTPUT ITERM 131
_.JL- - -
-R- - -
-
---tr Ir-~~~:
~",--VOO
-VSS
YCO INPUT ITERM 91-LOW-PASSF'ILTER
OUTPUT
PHASEPULSEITERMI)
~~~~~
NOTE, DASHED LINE IS AN OPEN-CIRCUIT CONDITION
Fig_6 - Typical waveforms for COS/MaS phase-locked loop
employing phase-comparator /I in locked condition.
Fig. 7 shows the state diagram for phase-comparator II;
each circle represents a state of the comparator. The number
at the top insicle each circle represents the state of the
comparator. while the logic state of the signal and
comparator inputs. represented by a 0 or a I. are given by
the left and right numbers. respectively. at the bot 10m of
each circle. The transitions from one slate to another result
from either a logic change on the signal input (I) or the
comparator input (e). A positive transition and a negative
transition- are shown by an arrow pointing up or down,
respectively. The state diagram assumes that only one
transition on either the signal input or the comparator input
occurs at any instant. States 3, 5, 9, and II represent the
condition at the output of phase-comparator (I when Ihe
p-MOS driver is ON, while states 2, 4, 10, and 12 determine
the condition when the noMOS driver is ON. States 1,6,7,
and 8 represent the condition when the output of phasecomparator II is in its high impedance state; i.e., both p- and
n-devices are OFF, and the phase-pulses output (terminal l)
is high. The condition at the phase-pulses output for all other
states is low.
As an example of how one may use the state diagram
shown in Fig. 7, consider the operation of phase-comparator
II in the locked condition shown in Fig. 6. The waveforms
shown in Fig. 6 are broken up into three sections: section I
corresponds to the condition in which the signal input leads
the comparator input in phase, while section II corresponds
to a finite phase difference_ Section III depicts the condition
when the comparator input leads the signal input in phase_
These three sections all correspond to a locked condition for
the eOS/MOS PLL; i.e., both signal- and comparator-input
signals are of the same "frequency but differ Slightly in phase.
Assume that both the signal inputs begin in the 0 state, and
that phase-comparator II is initially in its high-impedance
output condition (state 1), as shown in Figs. 7 and 6,
respectively. The signal input makes a positive transition
Following the example given for section I, the comparator
proceeds from state 2 to states 6 and 8 and then back to I.
The output of phase-comparator II for section 111 corresponds to the n-device being on for a time corresponding to the
phase difference between the signal and comparator inputs_
The state diagram of phase-comparatol II completely
describes all modes of operation of the comparator for any
input condition in a phase-locked-loop.
Voltage-Controlled Oscillator
Fig. 8 shows the schematic diagram of the voltage·
controlled oscillator (VeO). To assure low system-power
dissipation, it is desirable that the low-pass filter consume
little power. For example. in an Re filter. this requirement
dictates that a high-value R and a low-value e be utilized.
The veo input must not, however, load down or modify the
characteristics of the low-pass filter. Since the veo design
shown utilizes an n·MOS input configuration having practically infinite input resistance, a great degree of freedom is
a1lowed in selection of the low-pass filter components,
The VCO circuit shown in Fig. 8 operates as follows:
when the inhibit input is low, P3 is turned full ON,
effectively connecting the sources of P I and P2 1'0 VOD; and
gates I and ::! arc permitted to function as NOR-gate
flip-naps. Nt together with cxternal-resistor RI form a
source-follower configuration. As long as the resistance of R I
is at least an order of magnitude greater than ON resistance
of NI (greater than 10 kilohms). the current through RI is
linearly dependent on the veo input voltage. This current
flows through PI. which. together with P~. forms a
current-mirror network. Extcrnal resistor R:!. adds an
additional constant current through PI; this current offsets
the veo operating frequcncy for veo input ~ignals of 0
volts. In the current-mirror network. the I,;urrent of p~ is
effectively equal to the I,;urrent through PI independent uf
the drain voltage at P2_ (This condition is true provided P~ is
maintained in saturation; in the circuit shown. P2 is saturatcd
under all possible operating conditions and modes)_ The
set/reset flip-flop composcd of gates I ami:! turns ON either
P4 and N3. or P5 and N:!. One side of the external !.:apacilor
e I is. therefore. held at ground. while the other side is
charged by the constant !.:urrent supplied by P~. As soon as
e1 charges to the point at which the transfer point of
inverters I or 5 is reached. the nip-nap changcs state. The
In order not to load the low-pass filter, a source-follower
oupUI of the veo input voltage is provided (demodulated
output). If this output is used. a load resistor (Rs) of 10
kilohms nr more should be connected from this terminal to
ground. If unused, this terminal should be left open. A logic
o on the inhibi t inpu t enables the veo and the source
follower. while a logic I turns off both to minimize stand-by
pllwer consumption.
Performance Summary of COS/MOS PLL
The IlJ:lximulll ratings for the eD4046A COS/MaS PLL.
a~ well as its general operating-performance characteristics
arc nUllified in Table I. The veo and comparator
chara!.:lcrislics arc shown in Tables II and 111. respectively,
Table IV summarizes some useful formulas as a guide for
approximating the values of external components for the
CD4046A in a phase-locked-loop system. When using Table IV.
one should keep in mind that frequency values are in
kilohertz. resistance values are in kilohms, and capacitance
values are in microfarads. The selected external components
must be within the following ranges:
IOKn"R I ,Rl,R s ,,1 Mfl
C I '" 100pF,IYOO"'SY
C I ",SO pF al YOO'" lOY
In addition to the given design information, refer to Fig_ 9
for RI. R2,and el component selections. The use of Table [V
in designing a COS/MOS PLL system for some familiar applications is discussed below.
APPLICATIONS OF THE COS/MOS PLL
The COS/MaS phase·locked~loop is a versatile building
block suitable for a wide variety of applications, such as FM
dcmodulalor~. frequency synthesi7ers. split-phase
data
synchronization and decoding. and phase.locked-Ioop lock
detection.
FM Demodulation
When a phase-lOCked-loop is locked on an FM signal, the
voltage-controlled oscillator (VeO) tracks the instantaneous
frequency of that signal. The veo input voltage. which is the
filtered error voltage from the phase detector, corresponds to
the demodulated output. Fig. 11 shows the connections for
the COS/MOS CD4046A PLL as an FM demodulator. For
this example, an FM signal consisting of a IO-kilohertz carrier
frequency was modulated by a 4()()'Hz audio signaL The total
FM signal 70% IVoo - VSSI
AZ- -
Comparator Inpul l!:vr.ls !term. 31. "0" .. 30% (V OO - V5 S'
"I"
*' 70% (V OO -
E
'111.11
VSS'
'111M
Output Current Capability
Comparator I {term. 21 end ComparatOr II {term. 13):
"I" Dnve @
Vo .. 9.5
"0" 511lk @ Vo
V
ZIt
I
Voo
IIbO'2
Voo
2'L = 'uIlVCO,.equ.ncyrlnDe
1.4mA
2'L "'ml,,-Imi"
FreqYlncy C.plure
Phase-comparator I is used for this application because a PLL
system with a center frequency equal to the FM carrier
frequency is needed. Phase comparator I lends itself to this
application also because of irs high signal-input-noiserejection characteristics.
The formulas shown in Table IV for phase-comparator I
with R2 = 1;10 are used in the follOWing considerations. The
center frequency of the veo is designed to be equal to the
carrier frequency. 10kHz. The value of capacitor C 1. 500 pF.
was found by assuming an R 1 = 100 KG for a supply voltage
VOD= 5 volts.
These values determined the center frequency:
= 10kHz
Rlnge.2fe
Loop
1M
R5
OUT
111,121
4-
21e~;~
Fil!er
Compo",n'
Select'on
For2'c.s~Re'
PtlI.Angl.bel_n
Si,""I."dComperllor
teoo
s.,t.IlnputNoise
N.
High
AI;.cI'on
'0
-Given
- Use '0 with Fig.S. ro
dllterm,n.At.,.dCl
3 2
-Given:
'0 Iftdll
-ellcullle'mon'rom
Ih.tqUltlon
above capture frequency.
The total current drain at a supply voltage of 5 volts for
this FM..cIemodulator application is 132 microamperes for a 4
dB SIN-ratio on the signal input. and 90 microamperes for a
IOdB SIN ratio. The power consumption decreases because
the signal-input amplifier goes into saturation at higher input
levels.
- Given: 'max
-CatCUIlte'ofrom
Ih.equllIOft
'O·'~lI
'mon-'o-f\.
- Us. 'min Wllh Fig.9b
'....
lodeterminllR21ndCl
low·pass mter (R3 =100 kU,C2 =0.1 IlF) determine the
AllQY1Ioo,nlOCk
v..
CenlerFrequtncy
Rz·Cfl..= ±0.4 kHz
121
9(JO I' Cln'''' frequlncy lto '. ~O.lIl'Illin. 00 Ind
It Inch of lock rln.. 12'll
Locb on Hirmonici ot
The PLL was set for a capture-range of
to allow for the deviation of the carrier frequency due to the
audio signal. The components shown in Fig. 10 for the
vco in P1.1. systlm will ~uSl
IOlo_nopeorlt,ng'requenCV.'min
veo In PLL ,v.llm 1I\Ii1lldjust 10 Clnler fr!'qulncy.l o
.-D.SmA
"0" 5101( @V o - 0.5 V
_7r
'
1:E
-:-
t
1)'
ForNoSiptlnpUI
"1" Drlve@Vo"9.5V
fc ==.± .,1
-1-- "
2.6mA
Comparator II Phase Pulses (tp.rm.
fo
-
¥COWITHO,,.,
,.:., -- ----
__ _
VDffZ
-1.8mA
0.5 V
yeo WlntOUT OFFIIT
VCOWITH OFFIIT
¥CO WITHOUT O'FIlT
AI· -
veo
""""""",
SllKtion
-c:.Iculll.-;;;;;;-
- Use '0 wilh FIg.s.1O
dIIlermiMAllndCI
'rom l1'li equllion
'INJI 'o·'L
;;;·'O-'l
'"".
-u.r,;;;~1tI
FIg.fie 10 dllftmlnl
r8l10A2IA1 tOobtllin
.,
For furlhw Informltkln,"
F. o.dMr:""--loc:k TlChnlqu." John Willy Ind $Ont, Ntw York. I _
12' 0. S. Motdtya, ''MInilNrlHd AC Flltm lhin, .......Locked Loop", BSTJ,
m
u.v, 1186.
- Given'
'min.'",..
-Use 'rnjn wilh Fig.!5b
10 WMrll'lirNI R211'1dCl
'"".
-c.lcuI8l·'min
-U.~II'IF~
todlmmln.
rllioA2/A11G
otnllinR1
ICAN-6101
\/CC"
Phase-comparator II is used for this application because it
will not lock on hannonics of the signal-input reference
frequency (phase-comparator I does lock on harmonics).
Since the duty cycle of the output of the Divide-by·N
frequency divider is not SO percent, phase-comparator II
lends itself directly to this application.
Using the formulas for phase-comparator II shown in
Table IV, the veo is set up to COVer a range of 0 to 1.1 MHz.
The low-pass filter for this application is a two-pole, lag-lead
filter which enables faster locking for step changes in
frequency. Fig. 13 shows the waveforms during switching
between output frequencies of 3 and 903 kHz. The figure
shows that the transient going towards 3 kHz
the veo
control voltage is overdamped, while the transient to 903
kHz is underdamped. This condition could be improved by
changing the value of R3 in the low·pass filter by means of
adjustment of the switch-position hundreds in the Divideby-N counter.
SV
on
'~~~~:~~ OIlA''''
lOlA.
11 • '~2 .. A
~Oll
4 HI
~/"
h'90 .. 4 r OIi,OaBS'"
Fig. 10- FM demodulator.
Fig. 11 shows the perfonnance of the FM/demodulator
circuit of Fig. 10 at a 4 dB SIN-ratio. The demodulated
output is taken off the VeO.input source follower using a
resistor Rs (Rs = 100 ka).The demodulation gain for this
circuit is 250 mV1kHz.
0' "'".'OO"'AUO'O
TRANSMITTEC
~~r;E
C 5 V/cm
veo OUTPUT
10 V/em
'
m
SO m$/OIV
'0 v
-903
I fOUT
10 V .
-
vco
CONTROL
VOLTAGE
2V
Fig. 11- Volrage waveforms of FM demodulator.
Frequency Synthesizer
The PLL system can function as a frequency-selective
frequency multiplier by inserting a frequency divider into the
feedback loop between the veo output and the comparator
input. Fig. 12 shows a COSIMOS low-frequency synthesizer
with a programmable divider consisting of three decades. N,
the frequency-divider modulus, can vary from 3 to 999 in
steps of J. When the PLL system is in lock, the signal and
comparator inputs are at the same frequency and
f=NXlkHz
Therefore, the frequency range of this synthesizer is 3 to 999
kHz in I-kHz increments, which is programmable by the
switch position of the Divide·by-N counter.
Split-Phase Data Synchronization and Decoding
Fig.14 shows another application of eOS/MOS PLL,
split·phase data synchronization and decoding. A splitphase data signal consists of a series of binary digits that
occur at a periodic rate, as shown in waveform A in Fig. ]4,
The weight of each bit, 0 or I. is random, but the duration of
each bit, and therefore the periodic bit-rate, is essentially
constant. To detect and process the incoming signal, it is
necessary to have a clock that is synchronous with the
data-bit rate. This clock signal must be derived from the
incoming data Signal. Phase-lock techniques can be utilized to
recover the clock and the data. Timing information is
contained in the data transitions, which can be positive or
negative in direction, but both polarities have the same
meaning for timing recovery. The phase of the signal
determines the binary bit weight. A binary 0 or 1 is a positive
or negative transition, respectively. during a bit interval in
split-phase data signals.
0'
0
I
L I
0 1
..Il..JU"L...F
@~
I
Fig. 15- Lock-detection circuit.
phase-comparato~ ~II; the veo bandwidth is set up for an
fmin of 9.5 kHz and an fmax of 10.5 kHz. Therefore, the
PLL locks and unlocks on the I ~kHz and 20-kHz Signals,
respectively. When the PLL is in lock, the output of
phase-comparator I is low except for some very short pulses
that result from the inherent phase difference between the
signal and comparator inputs; the phase-pulses output
(terminal I) is high except for some very small pulses
resulting from the same phase difference. This low condition
of phase comparator I is detected by the lock-detection
circuit shown in Fig. 15. Fig. 16 shows the performance of
this circuit when the input signal is switched between 20 and
10 kHz. It can be seen that' after about five input cycles the
lock detection signal goes high.
©~
I
I
I
~
~
IL _________________
'0'
'0'
"l"tlLVltlE.81'-,,1
-'
12- l.ow-frequency synthesizer with threedecade programmable divider.
®~
,
,
Fig. 14- ISplit·phass datil synchronization and decoding.
H:,'~,~~!~"v"~
.
®~
I '-"I-'H-'l:'t-+'\-'H-'I't----'
I
Fig.
Phase-Locked-Loop Lock Detection
In some applications thai utilize a PLL, it is sometimes
necessary to have an output indication of when the PLL is in
lock. One of the simplest fonns of lock-condition indicator is·
a binary signal. For example. a 1 or a 0 output from a
lock-detection circuit would correspond to a locked or
unlocked condition, respectively. This signal could, in tum,
activate circuitry utilizing a locked PLL signal. This detection
could also be used in frequency-shift-keyed (FSK) dala
transmissions in which digital information is transmitted by
switching the input frequency between either of two discrete
input frequencies, one corresponding to a digital 1 and the
.
other to a digital O.
Fig. 15 shows a lock·detection scheme for the eOS/MOS
PLL. The signal input is switched between two discrete
frequencies of 20 kHz and 10kHz. The PLL system uses
Fig. 13- Frequency-synthesizer waveforms.
g~~g~~LATEO
0.1 Vlcm
into the clock input of FFI which divides the veo
frequency by two. During the ON intervals, the PLL tracks
the differentiated signal (B); during the OFF intervals the
PLL remembers the last frequency present and still provides
a clock output. The veo output is inverted and fed into the
clock input of FF2 whose data· input is the inverted output
of FFI. FF2 provides the necessary phase shift in·signal (C)
to obtain signal (D), the recovered clock signal from the
split.phase data transmission. The output of FF3, (E), is the
recovered binary infoTmation from the phase information
contained in the split-phase data. InHia] synchronization of
this PLL system is accomplished by a string of alternating O's
and l's that precede the data transmission.
--.....
"
•
,
~
i
I
I
. , 1 . -t - I
"
As shown in Fig. 14, the split-phase data-input (A) is first
differentiated to mark the locations of the data transitions.
The differentiated signal, (B), which is twice the bit rate, is
gated into the eOSIMOS PLL. Phase-comparator II in the
PLL is used because of its insensitivity to duty cycle on both
the signal and comparator inputs. The veo output is fed
I
VERT; 5 V/OIV
HORIZ I ms/OIV
I
~-'
.
L',
1veo OUTPUT
'
.~ ~~~~eTION
) OUTPUT
)-CONTROLVOLTAGE
GOVERNING SIGNAL
INPUT FREQUENCY
Fig. 16- Lock-detection-circuit waveforms.
617
ICAN-6230
Using the CD404 7 A in COS/MaS Timing Applications
by J. Paradise
Many applications exist today for COS/MOS multivibrators- both osci1lators and one·shats-in analog and digital
circuits. The requirements for these applications vary widely
in such parameters as voltage range, temperature stability.
power dissipation, drive capability, and external-component
cost. No design is optimum for all of the above considerations.
However, the RCA·CD4047A Monostable/Astable MuItivihator fulfills the needs of most applications in this timing
area. It can function as either an oscillator or one-shot with
many additional features, and will meet the power dissipation,
stability, and speed requirements ofmosl COS/MOS systems.
This Note compares some. simpler types of oscillator circuits
with the C04047 A in both theoretical and actual performance,
and provides application information on the C04047 A which
should prove useful to COS/MOScircuit and system designers.
~
~ 1.8,~--I----l--"":::::j:==~=::+:=--+---J.--A
~ t1'l--+-''''"-d---+-+-+---b.-'''''-+---./
:II
8
~~ "6'f-'",,".f'.,~+-+-+-+--+=-4-/-'--1
"
TRANSFER VOLTAGE (VTRI-PER CENT OF VDO
TRANSFER VOLTAGE !VTRI-PER CENT OF '100
COS/MOS OISCRETE RC OSCILLATOR
The simplest type of RC-oscillator is shown in Fig. I. It
consists of two inverters (which may be taken from standard
CfJ
®
A
(j)
R
C
Fig. 1 - Simp/sst COS/MaS RC oscillator.
RCA COS/MOS parts. i.e .• CD4OO7A. CD4001 A. CD4011 A.
etc.) and a single resistor and capacitor. The operating waveforms for this circuit are shown in Fig. 2.
The circuit operates as follows: depending on the output
levels of inverters A and B, at any instant C win be charging or
discharging through R. When the waveform at point (2) in the
circuit passes through the transfer voltage of inverter A, this
inverter will switch and cause inverter B to switch. Subsequently. the waveform at point (2) would be exponentially
(j)~
®VDD-~
~ ~ ~""
vsS-IV
Y
V
Fig. 3 - Discrete RC·oscillator time period as a function of transfer
tlolrage.
The above analysiS is valid only at low frequencies (Le., less
than 50kHz). As the multivibrator frequency approaches this
value, other considerations must be taken into account:
•
y
In this form it is easy to see that when K approaches zero, the
circuit and ,nsociated waveforms are eqUivalent to those of
Fig. A-.I. On the other hand. as K approaches infinity, the variation in period as a function of VOO is reduced to zero. This
result is shown in Fig. 5, where period as a function of trans-
1. The input protection circuit has a Vnn diode with a
finite resistance and capacitance; the diode will discharge at
the rate associated with this small time constant....
2. In the negative direction. there is a diode as well as a
series prot~tion resistor (1 to '3 kilohms); the time constant of
this diode is even longer than that of the VOO diode.
3. The propagation delay of the inverters used is added to
the time period during each charge and discharge cycle. Since
the delay is a function of VOD' small changes in Von at high
frequencies will cause the time period to vary.
4. There is a finite output impedance associated with'the
inverter which is in series with the external timing resistor.
Since this output impedance also changes with Von. at high
frequencies where the external resistor becomes small, the
multivibrator stability decreases with small variations in VOD'
The negative features of the input protection circuit can be
partially compensated for by the addition of a resistor, RS.in
series with the input protection circuit, as shown in Fig. 4.
Although the input inverter A is still clamped at one diode drop
above Von or one diode drop below VSS, the waveform at
point (4) is allowed to swing well above VOD and below VSS'
The larger swing reduces the dependency of transfer-voltage
variations upon stability;.the variable characteristics of the
input protection circuit and their effect upon stability are
greatly reduced. An analysiS of this circuit is presented in
Fig. 5 - DiscrettJ RC'ascillator time period as a function of transfer
voltage.
fer voltage is plotted for different value of VOO and K, and
Fig. 6, which shows period as a function of K for different
values of VOO' Variation in period with transfer voltage is
also reduced as K increases. This variation decreases from
10 per cent for K =0 to about 5 per cent as K gets large.
There are some obvious limitations in the value of RS that
can be used. Besides the disadvantages in this circuit if R is to
.•
I
,
l
,
.. 1
aVDD03~
t=Cr
~
f..-
Ii""
~I?"
......k:::
VTR o
.6~
,
¥
... ..." ... ... , ...
I
4 VDOo "v
CDNSTANT-k
Fig. 6 - DiscretB RC-o:scillator rims period as it function of constant. k.
be made adjustable, the user must be careful with component
layout, if RS is made very large, to take advantage of the improvement in stability. A time constant and phase shift is produced by RS and stray wiring and breadboard capacitance,
see Fig. 7. This shift creates a switching delay in the circuit which
changes the time period and, in addition, may cause spurious
oscillations and glitches in the muitivibrator circuit. A reasonable value for K would be anywhere from 2 to 10, with maximum and minimum values for RS determined by the above
considerations.
Fig. 2 - RC-oscillator operating watleforms.
increasing or decreasing with discontinuities equal in magnitude
to Von during the instant of switching. However. since
point (2) is protected by a standard input-protection circuit
common to COS/MOS devices, the waveform is clamped at one
diode voltage drop above VOO and below VSS' (Refer to waveforms in Figs. 2 and At). The calculations for the period of this
multivibrator circuit are shown in Appendix A; the final
equation for the period T is
Fig. 4 - RC'oscillator with the addnion of RS-
.92C5-22677
Fig. 7 - RC-o.scillator circuit with
T= -RC In(,-V..!T.!!R):...(:...VO",O,,-::-_VT",",Wc::..
(VOO+VO)2
(I)
where VTR is the switching or transfer point of the inverter,
and VD is the diode forward voltage drop.
Equation (1) shows that the period of the multivibrator, T,
is sensitive to changes in VOO. as illustrated by the graph of
time period, T, vs transfer voltage as a function of VOD in
Fig. 3. In addition to the strong dependence of actual time
period on the VDO chosen, the graph also illustrates that, for
a given Von. a full transfer voltage spread of 30 to 70 per cent
of VOO (unit-to-unit worst-case variations) yields a change in
time period of about 10 per cent from the nominalSO-per-cent
transfer-voltage percentage values.
618
sr~ay
capacitance.
Appendix B; the equation for the period. T, for this circuit is
shown in Eq. 2.
When
K=-t.
COSIMOS INTEGRATED RC OSCILLATORS
Tis:
The RCA·C04Q47 A is an integrated RC oscillator that
eliminates most of the disadvantages of the discrete circuits
previously discussed. The primary reason for this improved
performance is the special input-protection circuit which
. allows the capacitor charging waveform to swing above VOD
and below VSS without the need for an external resistor. This
cir~uit, shown in Fig. 8, has the same time period and stability
as the circuit in Fig. 4 for the case where the value of RS is
infinite. However, a resistor is eliminated, as well as the disadvantages of a time constant caused by the resistor.
ICAN-6230
COSiMOS INTEGRATEO ONE-SHOTS
There are two additional reasons for expected improvement
with the CD4047A. Fir~t, the transfer-voltage point of the
input inverter, A, is tested between 33 and 67 per cent ofVOD
instead of between 30 and 70 per cent; this narrower test range
improves stability by reducing unit-to-unit variations. In addition,large buffers are used for inverters D and E; this practice
The CD4047A, when used in the monostable mode, again
has several advantages over discrete designs. A high degree of
accuracy can be achieved with one time constant, and power
dissipation is lower than with discrete designs. Fig. 13 shows
that many functions can be achieved with the CD4047 A, including leading and trailing-edge triggering, and retriggering.
The pulse width, TM, is expressed below: its derivation is
given in Appen(fix E.
(VTR) (VOO) - VTR)
TM = -RC In (2 VOO)(2 VOO - VTR)
(6)
Fig. 14 is a graph of pulse width versus transfer voltage based
on the above equation.
The equations for monostable-mode power dissipation are
also derived in Appendix E. For a repetitive output on the
CD4047A,powerdissipationcan be expressed by the following
equation:
92C5-2261&
Fig. 8 - CD4047A oscillator sltCtion
reduces the effect of changes of device output impedance with
period stability. A derivation of period, T, for this circuit is
presented in the Appendix C; the final equation for T becomes:
2.875 CV002
(VTlV (VOO - VTlV
T = -RC In (VOO + VTR)(2 VOO _ VTR)
Pdiss=
(3)
0
SV/
102
4
2
103
&,
2
FREQUENCY
4
&
8104
(H~)
Fig. 10 - Comparison of Pdiss for discrets oscillator and C04047 with
theory.
CMOS OISCRETE ONE·SHOTS
Fig. 11 illustrates one of several simple monostable circuits
which can be employed in non-critical timing circuits.2 The
3VSVOOSl5V
.
0
\
~
\
.
II
---
c--\I
--
"
"
1/
- - ---
f\.
'l-
",.
1
1\
V
\
"
'"
"
J
"
TRANSfER VOLTAGE IIfrRI-P£A CENT Of' VDD
Fig.
..
l' - COS/MOS monost8ble circuit.
circuit pulse width is dependent upon the transfer voltage of
inverter B as time constant RC charges to VOO from VSS..The
pulse width is defined as
'"
(Voo-VTIV
T = -RC In (
VOO
)
(5)
Fig. 9 - CD4041 time period as a f.unction of transfer fIO/tage.
An additional advantage of the C04047 A is a reduction in
power dissipation as compared to the discrete multivibrators
discussed previously. Inverter A in Fig. 8 is designed with highimpedance components that limit power dissipation during the
time that the inverter operates in the middle of its transfer
region. Four additional inverters are used to gradually shift from
a very-high.impedance inverter at the input to a very-Iowimpedance driver in series with the external timing resistor.
Calculations for power dissipation and a comparison of Pdiss
for the CD4047A and a discrete oscillator are presented in
Appendix 0; the result is
Pdiss=2CV2 f
(4)
This equation specifies the power dissipated in the external
components only. At low frequencies, where most of the
power will be dissipated in R, power can be minimized by
using a small value of C, since the formula shows the power
is a function ofC and not R.
Additional power is consumed in the C04047 A chip as a
function of frequency. Fig. 10 shows curves for theoretical
minimum power dissipation, actual CD4047 A osciUator-po~er
dissipation, and discrete oscillator-power dissipation as a
function of frequency.
Fig. 12 shows the variation in pulse width as a function of
transfer voltage for this device.
There are several alternatives to the circuit shown in
Fig. 12.2 These alternatives have the advantage of greater
stability. but at the expense of two time constants required in
circuit and, in some cases, the addition of a diode.
.
I I
1 I ;
-, -+-i-
3V5VD\D51~V
,
,
.
-
i
P
l-::::::
,
"
/
I
I
61--- ---
..
(7)
USING THE CD4047A - SPECIAL CONSIOERATIONS
2
Figure 9 shows a graph of stability as a function of transfer
voltage based on this equation.
The graph of Fig. 9 shows a maximum variation of 5 per
cent between minimum (2.197 RC) and maximum (2.307 RC)
time periods. A va1~e of 2.25 RC yields a ± 2.5 per-cent variation. Typical values of period variations at high frequencies
and temperature extremes are included in the published data
for the CD4047 A.1
x (duty cycle)
TM
. .
/'
,/
/'
V
'"
.
"voo
TRANSI'U VOIaTAClE (YrR)-PER CENT Of'
..
'"
Fig. 12 - Simple ontNhot tim./HriodlU II function oftrlllJSfer fIOltl/gtI.
A number of circuit considerations are explained below
which will aid the user of the C04047 A.
A clamping circuit is provided on the chip to reduce the
recovery time (tr) that would normally exist in other monostable circuits; see Figs. 15 and 16. Fig. 17 shows a plot of
monostable-pulse-width stability as a function of duty cycle
for specific Rand C external components. Note that there is
no appreciable change in pulse width Until the duty cycle
approaches 100 per cent. A disadvantage to the clamping circuit is
that it introduces additional capacitance at the RC common
node (Fig. 16)., which may be noticeable for short pulse widths
in the monostable mode only. Some diffusion capacitance
present at the base of the n-p.n transistor is used to quickly
cnarge C to VOO after the one-shot cycle has terminated. This
capacitance is multiplied by the beta of the transistor, and is in
parallel with the external C during the time interval that the
transistorison(VoO - VBE -----_,
t-1RE--I
~
1
t-- 1RE --!
Fig. 20 - C04041A retrlpr-mode IWlfeformS'.
The circuit will work well even when the value of R approaches
or exceeds 1 megohm. For very low frequencies. where a large
value of capacitance is needed, the selection of the capacitor is
very important.
[t
must be nonpolarized because there is no
[efele'nce ground at either of the two pins to which C is COD-
* INPUTS
PROTECTED 8Y
STANDARD C05'toIOS
neeted. The capacitor parallel resistance (i.e., leakage) must
also be at least an order of magnitude higher than the external
R used. This criterion generally eliminates electrolytic ca·
pacitors and those made of materials which could produce
greater leakage current than that permitted for proper circuit
operation.
Because of the internal circuit construction, there is no
guarantee as to what de level will be present on the output at
pin 10 or I J when power is first turned on. If this condition
must be guaranteed, a system-power on pulse input to pin 9
can be made to assure that pin 10 will initially be at a low logic
level. The pulse can be generated from one of the circuits
shown in Fig. 21 .
RESISTOR- DIODE NETWORK
Vss
~
Vss
** CIACUIT
MODIFIED INPUT PROTECTION
TO PERMIT LARGER
EXTERNAL
RESET
INPUT-VOLTAGE SWINGS
Fig. 13 - CQ4047A logic diagram.
• , Voo
·
·
,
-'t--r--
·,
\
..
I~:J..
Vss
'"
"'!',..
--
.. ., . .~. .. . ..
Fig. 14 - C04041A Dn"-fhotpulss widthllSllluncrion oftransfervoltllf/ll.
,
·
·
,
·
··
,. .
,
·
14
···
,,
,,
..
,· .THE~1~EiRt'
. .. , .,.. . . ..
"'JOCk
--+"<-------,-----VDO --'---""------11.--=-:---
VTRWOD
VT.
-----=t---7,"'---+-
Vss
--------!r--;r--t----+---
"fA-VOO
-------''-'----1---+-
c
MUS. f--
R-Uk
-,
?
.1.~,
/
?
MEASURED
Fig. 15 - Cf)4D41A onlHhot RC wIIHfi:Jrm.
Fig. 21 - ClJ:4D41A POweMlp rtlftuircuirs.
Fig. 11 - CD4047A monostabl" IlCCU'JCY U II function a/duty eyeiB•
,
2Voo--,.--------------
,.
C'I~~
lI'IOUl
c
./
~!"I"
TO PIN 9
OF CD4047
A'lOCr
:----- ~~
I\
·, .. " . '" . '" . .
f\
...
·.
·
---
,
IV:II¥aoIII¥
h
.
Although the CD4047A data sheet calls for a minimum
input pulse duration of 200 nanoseconds at 10 volts and SOO
nanoseconds at 5 volts, shorter pulses (due to transients, etc.)
occur frequently in system applications where the CD4047 A is
used. Such narrow pulses may not be ignored by the CD4047 A,
but may instead cause Q to go high permanently or untU a reset
input occurs. The circuit shown in Fig. 22 eliminates this
problem by essentially ''lengthening'' the trigger pulse by
feeding back through RA"and CA a current pulse whm Q goes
from 0 to a 1. The particular values shown have been tried and
found to work well, even for extremely short input pulses
(less than 20 nanoseconds).
V,. 0-*--,-.,---1
11'4914
...,t.
THEO
~
c.t,PACITANCE-PICO'ARADS
'A
20pl'
10Ka
Fig. 22 - Input-pu'_ stretcher circuit.
Fig. 18 - C04041A /JUlie width til (I function 01 capacitanc".
APPLICATIONS
CDIFFUSION
:4=
I
"iF
FIg. 16 - CD4047A ciampinI/circuit.
~
I
r---
,
IM------!
Fig. 1S-CD4041Aone-shotDUtputlltpin 13.
NOISE OISCRIMINATOR
Fig. 23 illustrates an application of the CD4047 A in a noisediscriminator circuit. By adjusting the external time constant,
a pulse width narrower than that determined by the time
"constant will be rejected by the circuit. The output pulse will
620 ____________________________________________________________________
ICAN-6230
ENVELOPE DETECTOR
TIle CD4047 A can be used as an envelope detector by
.. ""
"..
VOUT-
""I"
.,1,,,,,,
"
,
FREQ.RAI\IGE
401'1 TO 1001'1
employing it in the retrigger mode, as shown in Fig. 32. The
time constant is selected so that the circuit will retrigger at the
---------
10 'JIOI"tI!iII
!100l's/OI"
1f4C04001
R·22.n
C '0.001
Fig. 28 - Low-pass filter-circuir waveforms.
follow the desired input, but the leading edge will be delayed
by the selected time constant. Fig. 24 shows typical waveforms
with the circuit in operation.
CD
INPUT
OUTPUT@
"OUT
~----
-
-
.-_.
- --
V,.
------- - -- --- -
Fig. 32 - Envelope·detector circuit.
TC04047· 50 I'S
Fig. 23 - Noise-discriminator circuit.
---~-
---------- - - -
500IOI/DIV
Fig. 24 - Noise.tJiscriminator circuit waveforms.
Fig. 29 - Low'pass-circuit walfeforms.
FREQUENCY DISCRIMINATOR
The C04047A can be used as a frequency-to-voltage converter, as shown in Fig. 25. A waveform of varying frequency is
applied to the +TRinput. The one-shot will produce a pulse of
constant width for each positive transition on the input. The
BANDPASS FILTER
Two CD4047 A low-pass filters can be employed to construct a bandpass filter,!Is illustrated by the circuit in Fig. 30.
The pass band is determined by the time constants of the two
fIlters. If the output of filter No.2 is delayed by Ct, the
CD4013A flip-flop will clock h~gh only when the cutoff frequency of filter No.2 has been exceeded; this point is illustrated in the timing diagram in Fig. 30. The Qoutput of the
CD40I3A is gated with the output of filter No. I to produce
'r- 2 0\H.
Fig. 25 - Frequency·discriminator circuit.
resultant pulse train is integrated to produce a waveform whose
amplitude is proportional to the input frequency. The waveforms of Fig. 26 were taken with the circuit in operation.
V,.
CD4047
Q OUT
1
\.
,
FREQ.RANGE
40 lOs TO 1m,
-
--
-
------------------
'"
" ~nnr~r'n~~~Ir1r~r;nr=
"OUT
10V/DI"~
~======~L..---.J~======
""" _ _ _ _ _--'nruUJ1'--_ _ _ __
I ms/DIV
CD40')
C·470pF
C-O.0022 "F
92CS-226~2
Fig. 30 - Bandpass filter Circuit and waveforms.
Fig. 26 - Frequency·discriminator-circuit waveforms.
LOW·PASS FILTER
A simple circuit using the CD4047 A as a low-pass filter is
shown in Fig. 27. The time constant chosen for the multivibrator will determine the upper cutoff frequency for the
filter. The circuit essentially compares the input frequency
the desired output. Typical operation of the circuit is shown in
Fig. 31, where the input frequency is swept through the pass
-band.
Fig. 27 - Low·pass filter circuit.
FREQUENCY
12 kHI
~
TCD4047 -1201'S
R -56k
C'IOOOpF
Fig. 33 - Enlfelope-detector-circuit waveforms.
PULSE GENERATOR
Several CD404 7 A units can be connected together to produce a general-purpose laboratory pulse generator, as shown in
Fig. 34. The circuit shown has variable-frequency and pulse·
width control, as weII' as gating and delayed sync capability.
Gating can be controlled from a high- or low-level input.
Automatic SO·per-cent duty-cycle capability is included, as
normal or inverted output.
CD4047A No.1 is connected as a gated, astable multivibrator, and, with the RC values shown, can produce overlapping ranges of frequencies from 2 Hz to I MHz. For free·
running operation, the Gate/Free-Run switch is closed, and
the Gate Level switch is placed in the high-level position.
Standby operation can be achieved with the Gate Level
switch ill the low·level position. When gating, the Gate/FreeRun switch is open, and the Gate Level switch is set to the
appropriate position. The gate signal is applied to the Gate In
jack.
CD4047A No.2 is triggered from the gated, astable multivibrator, and produces a narrow sync pulse which can trigger an
oscilloscope or generator. The sync pulse is obtained from the
Sync Out jaCk.
If a 50-per-cent duty cycle is desired, the Duty Cycle switch
is set in the 50-per-cent position, and the output is obtained
from CD4047 A No.1. The Signal Polarity ~witch determines
whether the Q and Qoutput is used.
CD4047A No.3 produces a variable, delayed (from I.S
microseconds to 250 milliseconds) output with respect to the
sync pulse when the Delay switch is in the IN position. This
one-shot is bypassed when the Delay switch is in the OUT
position (the inherent delay is approximately 400 nanoseconds).
CD4047A No.4 is a monostable multivibrator which receives trigger pulses from CD4047 A No. I or No.3. It can
produce overlapping ranges of pulse widths from 1.5 microseconds to 200 milliseconds with the values shown.
The signal output is buffered with the CD4041 A to
allow the pulse generator to drive any required load. The
circuit shown has the advantages of being compact, batterypowered. and COS/MOS compatible. In addition, it is capable
of being run from the same power supply as the device under
test to assure that the input levels are the same as VOD when
the power-supply voltage is varied.
MISCELLANEOUS APPLICATIONS
TFILTERI' 50 I'S
with its own reference, and produces an output which follows
the input for frequencies less than fcutoff. and a low output
for frequencies greater than fcutoff' Figs. 28 and 29 show
waveforms with the low-pass filter circuit in operation.
---- ----
5001'50/01"
TC04047 '501'&
R-22_
e-o.oOI
TCD4047A -50 ... ,
-
--
10"/DIV~
200l's/DIV
IOV/OIVtI!!!!I
V,. VOUT
IOV/DIV~
--
frequency of the input pulse burst . A dc level appears at the
output for the duration of the input pulse train. Fig. 33 shows
waveforms taken with the circuit in operation.
R '22.
C'IOOOpF
TFILTER 2'100,,&
R·47k
c· 1000pF
Fig. 31 - Band/NIss-filter-circuit waveforms.
The basic properties of good stability in the astable mode,
and stable pulse delay and width control in the monostable
mode, make the CD4047A a useful building block in many
systems, such as PMOS clock generation, audio tone gener-
621
ICAN-6230
afion~ semiconductor memory systems. semiconductor memory
exercisers, and general-purpose functional-testing systems. This
Application Note will serve as a guideline in incorporating the
CD4047 A in a system design.
REFERENCES
1. "CD4047A COSIMOS Low-Power Man_Ie/Astable
Multivibnltor," RCA Dala Bulletin, FHe No. 623
2. "Astable and Monollabl. Oscilla.... Using RCA COS/MOS
Oigltollntagrltod Circuits," by J. A. Dean and J. P. Rupley,
RCA Application Nole ICAN-6267
ACKNOWLEDGMENTS
The assistance of R. Vaccarella in the designing of some of
the application circuits shown and in obtaining laboratory
measurements used in plotting the curves shown in this Note is
acknowledged.
FI,. 34 - Puu.-,.".,.. circuit.
AppondlxACllculatlon of the Period of an Altllble Multtvi"tor Using. Single RC nma Constant
vpD+VO- - . - - - - - - - - - - - - - -
·00-+.......- - - - - - - - - - -
In Fig.A·I:
II: VTR' (VOO + VO) ••II/RC
VTR
11=-RClnvOO+VO
VTR'--'------"'t------...".,-
VOO-VTR
12= RCln VOO+VO
....
v••,-+----+~-----
Fig. A·' -
RClJ#i/~tor . .HIomI
And the period of an astable multivibrator using a single RC
time constant is:
fortIHtcin:uitafFIf. to
AppondlxB-
Analvs.. of Ciroult Shown In FIg. 4
Vpo+Vo
i'-.
vDO
i~
I
/i
I
I
I
I
I
I
I
I
In Fig. B·I:
I
Vi
I
VTR
liE-RClnVOO+VO
12: VOO - VTR C (VOO + VO). -12iRC
I
I--t"'~II~'8"""""'tZ---l
T
I
I'
II: VTR = (VOO + VO) e -II/RC
VOO-VTR
12" -RCln VOO+VO
F;fI.. B·' - RC Wlrtefonn for ". circuit of FIll- 4.
622 _______________________________________________________________
ICAN-6230
Eq. (B-1) is solved for V; the final voltage across the
capacitor is
V=Cle-KltA+~
(8-2)
KI
where C} = VTR = initial voltage across capacitor
RS+R
KI = RSRC
Fig. B·2 - Initisl conditions for solving period tAo
K2=
By inserting these values into Eq. (B·2) and setting the
final voltage across the capacitor. V, to VD. tA becomes
Circuit initial conditions are shown in Fig. B·2. In the
figure
dv V+VOO V+VOO-(VOO+VO)
-C dt= - R - - +
RS
(8-1)
_'_8__
RSRC ]
RS [VOO + VO]
[
tA = - RS + R In RS [VOO + VTR] + R [VTR - Vol
Insertion of these values into Eq. (B4). with
V= -VO yields
..!...
-v.~~vss
[
18 =
%
R
VOR-·RSVOO
RSRC
RSRr]
RS IVoo+Vol
RS + R In RS
I~ VDD
VTR} + R IVDD - VTR - Vol
C""_",,,
v••
Fig. B-3 - Initial conditiom tor solving period tB
The equations for tAt tB. and T can be simplified by
expressing RS as a multiple of R. Let
K =!§ and combining the expressions for tl and t2' The
Circuit initial conditions as shown in Fig. B·3. In the
figure
R
resulting expression for T is
dv VOO-V VO+V
C-=-----dt
R
RS
(8-3)
(VTR) (VOO - VTRl
T = -RC In --(V-')-O-+-V-O")2"'---
Solving Eq. (B-3) for V the final voltage across the
capacitor, yields
( K)
(8-4)
- i{:;l
K [VOO + VO]
RC In -K-'[-V"'O"'O-+-V-"T::"R:-]-+:-[V-T-R---V"":O]
where C2 = VTR - Von = initial voltage across capacitor
K}, K2 are same values as for above for tA-
Appendix CCalculation for Period of Astable Multivibrator Using Integrated Techniques
VOO+VTR-...------------r--
In Fig. C-I
tl: VTR = (VOO + VTR) e -tI/RC
VD.-l___~.-----------l___-
VTR-t---------'''r-----:7't--
vss-T------+--:r----+--
VTR
tl = RC In VOO +VTR
t2: VOO - VTR =(2 VOO - VTRle -t:zlRC
VOO-VTR
t2 = -RC In 2 VOO _ VTR
And the period of the astable multivibrator using integrated
techniques is
T = -RC In (VTR) (VOO - VTR)
(VOO + VTR) (2 VOO
VTR)
Fig. C-1- CD4047A RCoscillator waveform.
623
ICAN-6230
Appendix DPower Needed for Charge and Discharge of an External Capacitor During One Cycle
1
P= (f/2)
"OO-+"TR---.C----------
v,'---l---"...- - - - - 2C
=T
JT/2
lT/2
v" --1--------=-..--
CVdv
di
0
dl
(1.5 Vnn. -I/RC)
o
I - - - - T/2'-----1
(
2JT/2
4.5C V
=-...mL
T
RC
~C) (1.5 Vnn). -I/RC dl.
• -21/RCdl
0
92CS-tlU5
Fig. 0-' - Waveform for calculating power dissipation.
= _ ~2~!:.vnn 2 • -21/RC IT/2
Assume for this calculation that VTR = SO-per-cent VDD.
and that T = 2.2 Re. Since charge and discharge cycles are
symmetrical, the calculation can be performed by analyzing
a discharge cycle only. See Fig. 0-1.
T
0
Substituting T =2.2 RC
P=
_% (2.25) Vnn2 [. -2.2 -1] = 2.0fvnn2
v = 1.5 Vnn • -I/RC
~ =-
( k)(l.5 Vnn) (. -I/RC)
Appendix E-
Equations for Pulse Width TMof CD4047A in Monostable Mode
2"00--,------------
VDD-+---"""-------v" ---t------''''r----...,--vss-+----+---,,;L--f--
11: VTR = 2 Vnn. -ll/RC
VTR
11=-RCln-2Vnn
12: Vnn - VTR = (2 Vnn - VTRl. -12/RC
Vnn-VTR
12 = -RC ln 2 Vnn _ VTR
FIg. E·' - CD4041A RC WiTJlltlform. mQfJcutabie mode.
Note that the waveform in Fig. E·l is not symmetrical because
the timing capacitor is initially charged to VDD' In the
monostable mode, the circuit goes through one cycle only.
And the equation for the pulse width. TM. of a C04047 A in
the monostable mode is:
TM = 11 + 12 = -RC In;:(V:-,T,,,,R:;..)(V~n7:n_-_V..:.TR7:)""""7
(2 von) (2 Vnn - VTR)
Monostable Power Dissipation
To calculate the power dissipation for the circuit in the
monostable mode, refer to Fig. Eol. If it is assumed that
VTR = 5().p.r-c.nl Vnn. Fig. 14 shows lhal TM = 2.485 RC.
t2 is the ~me as,in the astable calculation, i.e., t2 = 1.10 RC
and PI2 = CV2ffor VTR = 50·per.:.nl Vnn. Thus, 11 in Ih.
monoslabl. mod. = 2.485 RC - 1.10 RC = 1.385 RC.
=~
TM
J
4Vdd2 (11
RC
o
J
.-21/ RC dl
CVdv
-dv
dl
Substiluting 11 = 1.385 RC
CVdv dl+ ..:.. CV2
dl
TM
wh.r. V = 2 Vnn. -I/RC and
-dv = dl
(1 )
- - (2 Vnn). -I/RC
RC
C
1.875 C Vdd 2
Pu = - - 2Vdd2 [. -2.77 -1] =_--:~C:TM
TM
P = PI! + PI2 = (1.875 + 1)
CVdd2
r;.;--
= 2.875
CVdd2
--:r;-
For a repetitive output from the CD4047 A
2.875 C Vdd 2
p=
TM
x duty cycle
624 ____________________________________________________________________
ICAN-6315
COS/MOS Interfacing Simplified
Table IV-Fanout of CD4049A and CD4050A Buffers to TTL
Buffer Fanout
by O. Blandford and A. Bishop
COS/MOS with its wide range of operating supply voltages,
low input current, and low power consumption, interfaces
easily with many electronic devices. In addition, COS/MOS
circuitry can easily be added to a system and can often be
operated from the existing power supply. Examples of praclicai
circuits for a wide variety of interfacing situations are given in
this Note; design constraints are included in each case.
Note that the C04000 Series type numbers are followed by
a suffix letter, A or B, which specifies the maximum operating
voltage for the device: A,3 to IS volts; B. 3 to 18 volts. The
outputs of all O·type devices are buffered and have the same
output drive current and equal source and sink capabilities.
Table I shows some characteristics of S·type .devices.
74
Minimum
Typical
essentially "capacitive", which means that many COS/MOSinputs
may be driven by a single TTL output. The actual number
depends on the frequency of operation.
In the COS/MaS to TTL interface, Fig. 3, the requirement
is to sink sufficient current in the low OUlput state at a maxi·
mum output voltage of 0.4 volt. Table III gives the current
sinking capability of some CD4000·series devices. Note that
all B·type devices have the same standard output drive and are
capable of sinking two low·power TTL loads, worst case. For
the higher power types of TTL, the CD4049A and C040S0A
buffers may be used. Table IV shows the minimum and typical
fanout for each TTL family. The buffer takes its power from
the 5-volt TTL supply and has an additional advantage in that
TTL Family
74H 74L 74LS
I
14
28
74S
14
+5 TO +15 V
Fig. 4- TTL to COSIMOS at a VDD greater than 5 volts.
Table I - Output Drive Current-B-Type Devices
Output
Drive
Current
Symbol
Sink
IoN
Source
lOP
VOO
Volt
Vo
Volt
BO, OK, OF. DH
-5SoC +2S oC +12SoC
Min.
Min.
Min.
DE
-40°C
Min.
+2S o C
+8S oC
Min.
Min.
10
0.4
0.5
0.5
I.I
0.4
0.9
0.3
0.65
0.45
1.0
0.4
0.9
10
4.6
2.5
9.5
-0.5
-2.0
-1.1
-0.4
-1.6
-0.9
-0.3
-1.I5
-0.65
-0.45
-1.8
-1.0
-0.4
-1.6
-0.9
5
0.36
0.75
-0.36
-1.3
-0.75
+2S oC
Typ.
Units
0.8
1.8
rnA
rnA
-0.8
-3.2
-1.8
mA
mA
mA
it can accept input voltage swings of 5 to 15 volts from the
COS/MOS to TTL
preceding COS/MaS system.
In interfacing ITL with COS/MOS with a common power
supply of between 4.5 and 5.5 volts, the guaranteed activepull-up TTL output voltage of 2.4 volts is lower than the
minimum COS/MOS input voltage required to guarantee
switching. 3.5 volts, Fig. I. This difference is overcome by the
use of an external resistor, RX in Fig. 2, which is also the reo
sistor to be used for open-collector-output TTL at a VOD of
5 volts. The minimum value of RX is fixed by the maximum
sink current, e.g., J.6 milliamperes for 74-series TTL, its
maximum value by IOH' the off leakage of the output ~ink
transistor. As shown in Table II. the values of RX between
1.5 and 4.7 kilohms are suitable for all the TTL families under
worst-case conditions. The COS/MOS input impedance is
COS/MaS
4.5 TO 55 V
Fig. 5-COS/MOS to HNIL to COS!MOS interlace.
COSIMOS to OTL
Fig. 3-COS/MOS to TTL interface.
To gain improvements in speed and noise immunity in a
system using a COS/MOS supply voltage greater than +5 volts,
high-voltage open-collector ITL circuits such as the 7416,
7417 or 7426 may be used, as shown in Fig. 4. The value of
the pull-up resistor RX will depend on the actual value of
VDD; at 10 volts, 39 kilohms would be SUitable.
The COS/MOS to DTL interface requires a buffer, such as
the CD4049A shown in Fig. 6, to sink the OTL input current
of 1.5 milliamperes at 0.4 volt. Fanout to OTL circuits depends
on the sink-current capability of the COS/MaS buffer used.
For the CD4049A and CD4050A, typical fanout is 3.
The DTL to COS/MaS interface requires no special consideration because the internal pull-up resistor in DTL circuits
and the extremely low input current of COS/MOS circuits
ensures a high logic level almost equal to the power·supply
voltage.
COSIMOSto HNIL
l.OGICO
OUTPUT
Fig. '-TTL to COSIMOSvoltage levels.
The wide operating-voltage range and low power consumption of COS/MaS circuitry enables it to operate from the
HNIL power supply. Most CD4000A circuits will drive the
HNIL input directly; for example, in Fig. 5, the C040818
output sinks the required 1.4 milliamperes at an output voltage.
typically Jess than 0.5 volt. The HNIL output·voltage levels,
0.8 volt and 10 volts, enable it to interface directly with the
COS/MOS input with good noise immunity.
Fig. 6-COS/MOS to OTL to COS!MOS interface.
4.5 TO 55 V
Table III-Minimum Current-Sinking Capability of COS/MOS Devices
COS/MOS
Type
Fig. 2- TTL to COS/MOS interfactl.
Tabla II-Values of RX for TTL-COSIMOS Interface
Characteristic
74
RX min. (ohms)
390
RX max. (kilohms) 4.7
748 74L 74LS 74S
270 l.5k 820 270
4.7 27
12
4.7
C04000A
CD4001A
CD4002A
CD4007A
CD4009A/49A
C040JOA/50A
C0401lA
CD4012A
CD404IA
CD4031A
CD4048A
CD4XXXB
Description
Dual 3-lnput NOR Gate Plus Inverter
Quad 2·Input NOR Gate
Dual 4-Input NOR Gate
Dual Complementary Pair Plus Inverter
Inverting Hex Buffer
Non-Inverting Hex Buffer
Quad 2·lnpu, NAND Gate
Dual 4-lnput NAND Gate
Quad True/Complement Buffer
64-Stage Static Shift Register
Expandable g-Input Gate
Any B-Type Device Output
Sink Current (rnA at 25°C
VO=0.4VoIt,VOO= 5 VoIt)
Ceramic
Plastic
0.4
0.4
0.4
0.6
3.0
3.0
0.2
0.1
0.4
0.3
0.3
0.3
0.3
3.0
3.0
0.1
0.05
0.2
J.3
J.3
1.6
0.4
1.6
0.4
625
ICAN-6315
COS/MOS to 10k Eel
COS/MOS and 10k EeL are not normally interfaced. but
they can be readily by using the )0124 and IOl2S devices
which are intended for conversion between EeL and TTL. This
interface requires that the COS/MOS device be operated at a
5-volt VOO_ as shown in Fig. 7. Where greater speed is
required of the COS/MOS system, it can be operated with
VDO at the Eel ground and VSS at -12 volts. In the latter
case. a IN914 diode clamps the COS/MOS output to VEE as
shown in Fig. 8, At supply voltages greater than 6 volts, a
COS/MOS buffer should not be used, as over-dissipation will
occur in the buffer.
INDUSTRIAL
CONTROL
SYSTEM
Vz·VDD
Fig. 13-ZentH' diode industrial control Interface.
f--------..jCE
...
+10 II
COS/MOS
SUPPLY
"
.
INDUSTRIAL
CONTROL
24-VOLT LOGIC
SYSTEM
Fig. to-COSMOS to n·channef dYlJ8mic·RAM inrllrfllce.
COs/MOS to PMOS
Fig. 1-1Ok EeL fa COS/MOSand COS/MOS to 10k-EeL interface.
ov
Silicon-gate PMOS static shift registers operating from
+5-yolt and -12-yolt supplies are directly compatible with a
system operating from the +5-volt supply with
VSS at zero volts. The only additional component required
is a clamp diode to VSS on the data output, as shown in Fig.
II, because the unloaded PMOS output voltage will go
negative in the low output state.
Fig. 14-COS/MOS to industri8l-control interlllC&
~COS/MOS
ov
The slow pulse edges typically found in an industrial
control system can be speeded up in the COS/MaS system by
Schmitt·trigger circuit, the CD4093B, Fig. 15(8). At 8
VDO of 5 volts, VH is typically 0.6 volt, Fig. IS(b).
8
-5.2 V
COSIMoo
SYSTEM
Fig. 8-COS/MDS at 12 volts to 10k-EeL intflrfscl/.
f----->iRECIRCULATE
1-----01."
to--.------jOUTI
OUT2
COs/MOS to NMOS
The increasing use of n-channel MOS memories means that
interfaces between COS/MaS and NMOS are now common.
In a system of lk memories, such as the type 2102, which
employ peripheral COS/MOS circuitry for address, read/write.
chip select and data handling, the COS/MOS circuitry can be
supplied from the S-volt power supply of the memory. Inputs
to the memory are then COS/MOS compatible, and direct
interface is permitted. The data output requires only a single
pull-up resistor, RX, as shown in Fig. 9, to ensure an
acceptable high-state output voltage.
ov
"V
ov
OUTPUT
WAVEFORM
F;g. , '-COS/MOS to PMOS static·shift-regisrer inrerlllCe.
COSIMOS to Industrial and Powar-Control Circuits
Industrial control systems employ greater logic swings
than IC logic systems, such as COS/MaS, to achieve high
noise immunity and to enable them to operate from readily
available high-voltage supplies and to interface with electromechanical equipment.
Fig. 12 shows a simple, resistive-divider circuit used to
interface a system with a 24-volt logic swing to COS/MOS;
the circuit could readily be modified for even higher voltage
swings. The capacitor filter enhances the excellent noise
AO TO A7
(TYPE 21021
!~T~~~IINPUTL_",vs=-s_..1
Fig. 15-(a) COSMOS Schmitt-trigger. (b) typical wallfllorms
lor Schmitt-trigger.
A high-power coil, such as the solenoid of a printer
hammer, which requires about 1 ampere at 70 vol ts, may be
driven from a COS/MaS system by using a Darlington
transistor as shown in Fig. 16. A typical vaJue of VBE for a
type 2N6385 transistor is I.5 volts at a collector current of
} ampere and a minimum gain of 1000, so that the output
source transistor of the CD4Q738 has to supply 1.5 milliamperes. The value of resistor R is chosen so that VOS is
. sufficient to guarantee this output current. Suitable values
of R for use with a B-type device are given in Fig. 16 for a
VOD -of 5, 10, and J 5 volts.
COS/NOS
SYSTEM
'v
1----oJ"
00
INDUSTRIAL
CONTRDL24 VOLT
LOGIC
II
SYSTEM
SOLENDID
"--,
Fig. 9-0irect interface betwllfln COS/MOS Bnd
B'k memory. rype2'02.
A 4k-bit, dynamic, n-channel RAM, such as the 2107 A,
has +12-volt and -S-volt supplies as well as the +S-volt Vee
supply. as shown in Fig. 10. The COS/MOS peripheral circuitry in this system is probably best operated from the + 12volt supply, ensuring good speed characteristics and noise
immunity. The 5·volt input signals to the memory are provided by CD4050A buffers powered by the 5·volt VCC
supply. The 12-vo1t-swing chip-enable signal is directly compatible with the 12-volt COS/MaS system. The data output
uses a single transistor to generate the required 12-voJt logic
swing; memories added to provide an increase in word
capacity are wire-OR'edat the data output pin of the memory.
HAMMEFI
I
I
Fig. 12-lndusrril1l control to COS/MOS interface.
I
I
immunity of the COSIMOS logic, and the two clamp diodes
ensure that the input signal voltage is between VDD and
V SS. An alternative circuit using a zener diode is shown in
Fig. 13.
A ~ngle-tramistor level-converter interfaces a COS/MOS
device. to ·an industrial control system, as shown in Fig. 14.
The transistor is driven directly from the COS/MOS device
output (Fig. 23 describes the method of calculating the
values of the resistors needed in Fig. 14).
I
~D:
Ik
IOV
4.7k
75
12N6385
I
8." L_~====~
.__ .J
Fig_ '6-COSMOS system drilling a printtH"·h8mmer sofenok!
With tt. aid of II Darlington tlilns;sror.
626 __________________________________________________________
~
________
ICAN-6315
Power-control SCR's and triacs may also be driven
directly by COS/MOS outputs. A sensitive·gate SCR, such as
the 10681, may be controlled directly by a COS/MOS gate,
such as the CD40698, and thus be able to control directly
2.5 amperes at reverse voltages up to 600 volts, as shown in
Fig. 21 shows a CA741·type op-amp operated between
VOO and VSS with a resistive divider on the non-inverting
op-amp ~nput.
NOR GATES
ORAIN-to-SOURCE VOL.TS (VDS'
-15
-10
-7.5
-,
-2.5
-,
J I~,
'~$
14
Fig. 17.
-12.5
Voo
I
Vas.
---'
OTHER GATE
INPUTS GROUNDED
-10
GATE ~ SOURCE VOLTS (\I:
I_ -15
AMBIENT TEMP(ffATURE (TA' ~ 25·C
TYPICAL TEMPERATURE COEFFICIENT FOR 10. - 0.3% I·C
Fig. 17-COSIMOS directly driving a sensitive-gate SCR.
SCR's and triaes with gate currents in the milliampere
region may be controlled by a buffer, such as the CD4049A.
This buffer could, in turn, be controlled by a COS/MaS
system or, as in Fig. 18, by an apia-coupler to provide
greater isolation.
,+
'~:'~lR____ '~k
I
I
L
OP!2-E..~f:!!...J
'-_~
COS(MOS Driving Displays
Digital systems now employ a great variety of digital
displays, so that their interface to COS/MaS is a common
requirement.
COS/MOS TO LED'S
I
I
TIL III
Fig. 24-CD400rA-typicai p-channel drain characteristics.
Fig. 2r-lnterface of ap-amp and COSIMOS with cammon ~uppJy rail.
--+
___
LED's may be driven directly from a COS/MaS buffer,
such as the CD40S0A shown in Fig. 22,3t 3 drive current of 15
milliamperes if a power supply of approximately 10 volts is
available.
Seven-segment LED displays connected in either common
anode or common cathode configurations may be driven at
supply voltages as low as +5 volts by the seven·transistor
R.
VOO-VOS-VSE' -VLEO
Ro"
I LEO
Fig. 25-COS/MOS driving a tr.Jn~istor with a common-carhodeconnected LED load.
Fig. r8-High·voIrafPJ logic to COS/MOS driving an SCR.
In cases where a single-gate output source or sink current
proves insufficient, it is possible to parallel the inputs and
outputs of gates on the same chip, as in Fig. 19. Gates not on
the same chip and buffer circuits should not be operated in
parallel as over-dissipation may result.
COS/MOS TO LCO
Seven·segment liquid-crystal displays may be driven directly
by COS/MaS circuits CD4054A, CD4055A or CD4056A, as
shown in Fig. 26. These circuits contain the internal levelshifting circuitry needed to convert the typically 5-volt input
logic-level swing to the 30·volt peak Be signal required to
drive the dvnamic·scattering LCD.
Fig. 22-COS/MOS buffer driving an LED.
Fig. 19-Pa'BJltJling inputt and outputs.
Interfacing Op·Amps to COS/MOS
arrays CA3081 and CA3082. Fig. 23 shows one of the seven
transistors of the CA30S1 with an LED load. The figure also
shows the method of calculating Rb and Rc. The base drive
current available depends on the CD4000A Series device used
and the values ofVOD and VOS' As shown in Fig. 24, the base
drive current increases with both VDO and VDS. Fig. 25
shows one of the seven transistors of the CA3082 driving a
common-cathode LED. The method of calculating the value of
emitter resistor Re is also shown in Fig. 25.
COS/MaS circuits may be connected directly to the out·
put of an op·amp operating between the normal ±15·volt
supply rails, as in Fig. 20, provided clamp diodes to Von and
VSS are used to ensure that the COS/MaS input voltage does
not go outside the range VS~o VDO, Resistor R3 limits the
op-amp output current should the op-amp output voltage tend
toward the negative rail.
LIQUID
CRYSTAL
DIGIT
R,
'DD
,
,
Fig. 26-Using the CD4055A to drive a liquid crystal.
1
1117 CA30SI
J
Vss
~o
\IOl.T
R < vDD(MINI - VOS(MAX)-VBE(MAX)
b-
Ic (MAXIIB(MINI
R,"
Fig. 2O-Spfit-rail ap-amp to COS/MOS intBrlace.
_'CO=-.-'-"".,E~'::;D:-,'c="~SA,-,Tl
Fig. 23-COSIMOS drilling a trBnsistor that has an LED load.
COS/MOS TO GAS-DISCHARGE OISPLAY
The popular seven·segment gas·discharge display requires
a cathode drive current that varies from segment to segment.
Manufacturers supply drivers which are COS/MaS compatible
at their inputs so that they can interface a COS/MOS system to
the gas·discharge display without additional circuitry.
REFERENCE
I. "COS/MOS Digital Integrated Circuits", RCA DATA BOOK
Series SSO-2038, 1975.
627
ICAN-6346
Figs.5 and 6 show measurements of voltage and energy
noise immunity for the Schrriitt trigger. Fig.5 shows, for
example, that for a Von of 5 volts, the noise immunity in each
Applications of the RCA~CD4093B
COS/MOS Schmitt Trigger
by D. J. Blandford
"""tEL
LOGIC "0"
OUTPUT
v.
vss
VOD
VN
Fig. 4 - Input and output charllCtBristics.
"rN
Vp
state exceeds the supply voltage (5 volts) for pulses shorter
than 200 nanoseconds. The energy noise inununity plotted
in Fig.6 against pulse Width. is the product of noise-pulse voltage, noise-pulse time, and the appropriate value of the output
drive current for the device under test. The units of energy are
nanojoules (10'"9 Joule). At each value of the s1,lpply voltage
the c1:'cve has a minimum value. Inspection of Fig.6 shows that
the value of the minimum energy noise immunity increases
with increasing VDO, and Occurs at a lower value of noisepulse Width.
Fig.2 - Transfer characteristic of the CD4093B.
Vo
VDD TVPICAL
SYMBOL VOLTS VOLTS VALUES UNITS
5
0.001
pA
IL
10
0.001
"A
LOW lEVEL
V
5
0
VOL
V
10
0
CHARACTERISTIC
QUIESCENT DEVICE CURRENT
HIGH lEVEL
NOISE IMMUNITY
VOH
VNL
VNH
OUTPUT DRIVE CURRENT SINK
SOURCE
ION
lOP
POSITIVE THRESHOLD VOLTAGE
Vp
NEGATIVE THRESHOLD VOLTAGE
Vn
HYSTERESIS VOLTAGE
Vh
PROPAGATION DELAY TIME
CL"'50pF
TRANSITION TIME
CL = 50 pF
Fig.I shows the functional diagram of the Schmitt trigger;
note that each input has the standard COS/MOS input protection network and that each output is double buffered.
~
,
* n
~I'IO,II)
* A.LL
INPUTS PROTECTED BY COS/MOS STANDARD
PROTECTION NETWORK
OUTPUT
REGION
VSSb=S'RE~G;S'O:sNcl:rl~"-J~~~~~
TABLE I
OUTPUT VOLTAGE
'?-.
Veo
.
tPHL.
tPLH
fTLH,
'THL
5
10
0
0
0 ..
0.5
4.6
2.5
9.5
5
10
5
10
5
10
5
10
5
5
10
5
10
5
10
5
10
5
10
5
5
10
2.6
5.2
3.0
6.5
V
V
0."
mA
mA
mA
mA
mA
18 LOW LEVEL
"
14
~
V
V
V
V
1."
-O.B
-1.8
-1.B
t
II
~
I
12
VOO ·15 V
"
10
~ •
I\\. VDD.I~V
6
"'-
4
,
V
V
V
V
V
2.6
5.2
2.0
3.5
0.6
1.7
190.
100
100
50
10
INPUT
VDDI~2Z~'O"'Gl02c:t., P.ZPiiiH-'E':/%/%/%/%/%
If now the input voltage is reduced, the output stays low
(VSS) until Vn is reached. At this point the output goes high
(VOO) and remains high as the input voltage is reduced to zero
(VSS). The hysteresis voltage is the difference between Vp and
Vn and is typically 0.6 volt for as-volt VOO and 2.0 volts for
a I O-volt VO~.
Static and Dynamic Electrical Characteristics at 25"C
115,8,12)
216,9,131
CD40938
COS/NOS
OUTPUT
This Note describes the characteristics and some typical
applications of the CD40938 COS/MOS quad two-input NAND
Schmitt Trigger. The C04093B may be used in al1 applications
in which the logical NAND function is required and, in addition,
in a whole range of timing, waveshaping, and interfacing applications in which the Schmitt Trigger action on the inputs
is utilized.
CHARACTERISTICS
The CD40938 consists of four Schmitt tciggers in a fourteenpin package. Each of the four devices is a two-input NAND
gate with Schmitt action on each input, yielding a typical
hysteresis voltage of 2.0 volts with a 1Q-volt supply without
the need for any external components. In addition, the
C040938 is compatible, pin for pin, with the popular
C04011A quad NAND gate, has the balanced and standardized output drive of the IS-volt COS/MOS "8" series types,
and has low propagation delay and very low power dissipation.
Table I summarizes these characteristics.
,eo
100
VOD-5V
~
.00
400
PULSE WIOTH-NANOSECONDS
V
n,
n,
,
=r--'00
600
18 HIGN LEVEl.
g
141C----f----t----f----t----t----12'C----f----t----f----t----t-----
~
IO'C--r-f----t----f----t----t--~
m
n,
n,
~
Fig.3 shows a graph of the typical hysteresis voltage
function of supply voltage VDD.
VH as a
Fig.4 shows the input/output characteristics of the CO40938; the output characteristic shown is the same for any
COS/MOS output, including the Schmitt trigger. The input
characteristic is unique to the Schmitt trigger and shows that,
when driven by another COS/MOS device, the Schmitt trigger
has more than SO-percent noise immunity in each state.
I
~
~~
•
\.
\
100
200
300
400
6eo
PULSE WIDTH-NANOSECONOS
Fig.S - Voltage noise immunity of the CD4093B.
Fig.1 - Functional dlagl'llm of the CD4093B. COS/MOS Schmitt tr;pr.
One of four Schmitt triggers is shown.
Fig.2 shows the transfer characteristic of the Schmitt
trigger. The general shape of this characteristic is the same
for all values of VDD, but the relative values of Vp ,Vn and
VH change with VDD as shown in the data sheet. As the input
voltage is increased from zero (VSS), the output remains high
(VDO) until Vp is reached. At this point the output goes low.
(VSS) and remains low as the input voltage is raised to VDD.
~
10
15
20
SUPPLY VOLTA.GE IVDO'-Y
Fig.3 - Typicsl perr:tlnt hystrJrelis .., IUPPJy voltage.
Another important property of the Schmitt trigger is
illustrated in Fig.?, which compares the supply current taken
by the CD4093B with lh.t of the C04011A. with a long rise·
and fall-tbne input. The power dissipated by the Schmitt
trigger is clearly much le·5s than that dissipated by the quad
NANO gate, so that th~ Schmitt trigger should be used in applications in which slow input edges are anticipated.
APPLICATIONS
_ The application of the C04093B COS/MOS Schmitt triuer
in situations which require the logical NAND function and in
timing, waveshaping, and interfacing applications in which the
Schmitt trigger action on the inputs is utilized are discussed
below.
628 _______________________________________________________________
ICAN-6346
~
90 LOW LEVEL
~~
70
/
g~ 60
~I
5"
~~
/
~~ 040
~!
VOO
td_=RClnv;;-
vco-IOY
V
Voo
@-~---C=f@
V
"00"5V
100
0
200
400
'00
'00
600
PUL.SE: WIDTH-NANOSECONDS
HIGH LEVEL.
~0
~i
.0
~I
/
~;
50
;~
40
/
~!
~g
30
/
L/
V'
I---
I
~
'100- 511
100
0
200
300
"" \
/
VOO"JDV
. /V
-
20
/
/
~
wx
~~
~.
Slow Edges - Slow edges aTe a common phenomenon in digital
systems; for example, at the output from a transducer, at the
end of a long line; or an output with large capacitive load, or
on the output of a filter. The Schmitt trigger is particularly
useful in generating a waveform with fast edges in these
applications, see Fig.9.
/"00015V
~i
g~
l'
C; Rt and R2 bias the input midway between Vn and Vp , the
input threshold voltages, to provide a square wave at the output.
10
1/4 C04D938
R®·u~
F;g.8 - Sine-Wi1Vt1 to square·wave converter.
V
~~ 20
8
VOO"15V
/
!~
i
By connecting one input to VOO, as in Fig.II, both edges
are delayed, because now, when input A goes low, output C
remains low until capacitor C discharges to Vn. At this time,
the output goes high. !d_ is given by:
I
~: eo
400
r--'00
600
Fig. 1 , - Delayed pulse.
\.
V-
Both edges may be separately delayed by connecting
different RC timing components to each input, as in Fig.12.
Now td+ and td_ are given by:
,
VOD
td. = R2C2 In VOO _ Vp
i\.
V
PULSE WIDTH-NANOSECONDS
Fig.6 - Energy noise immunity of the CD40938.
2ms/Division
Fig.9 - Sharpening up a slow edge.
~
(a) C04093BE,
-
Top vertical - 5V/Division
Lower vertical - 2mAIDivision
Horizontal
- D.2/Division
With an input. edge time of 1 second and an output transition time of 100 nanoseconds, the improvement in edge time
is a factor of 107 . With longer input edge times the improvement is even greater.
Timing - In general, timing circuits use external resistors and
capacitors to provide time constants. The advantage of the
CD4093B COS/MOS Schmitt trigger in these applicalions is
that the very high input impedance permits the designer to
use high values of timing resistance. Therefore, long delay
times may be produced with moderate values of capacitance,
and small, low-cost capacitors may be used for short and
medium time delays.
Edge Delays - In the circuit of Fig.) 0, the outpul falling edge
is delayed with respect to the input leading edge by a time td+
given by:
td.=RCln~
VDD-Vp
--
When the input goes high (Von) the capacitor charges up
towards Von through R. When input Breaches Vp, the out.
put goes low (VSS). As soon as jnput A goes low, the output
goes high.
t-"
~
. /~
tI'
......
CD40938 with th(l CD40'1A.
Waveshaping
Sine Wave to Square-Wava Converter - Fig.8 shows a typical
application of the Schn!itt trigger. the sine-wave to squarewave converter. The sine input is ac coupled by capacitor
VDO
rI
r@...J
L..--J
~~:
I
I
Voo~.
VDOXM
c Vp
@V,
®
I
vss
I
I
~
I
J
II
Fig.'O - Delay on leading edge.
I
I
I
~+
I
I
Itd_
I
I
I
Fig. 12 - Separate delay to each edge.
Edge Detector - Fig.13 shows a circuit that provides a short
negative-going output pulse for every positive-going edge at
the input. The input waveform is coupled to the input by
capacitor C; the pulse length depends, as before, on Rand
C. If a negative going edge detector is required, the circuit
of Fig.14 should be used.
®
U
~
114C0409' •
®
@
R
VOOSl-r
v"
®
I
I
II
II
-I
I I
J
~OOUlt-1
I
i
vss
1
-I J.-.Id+
I
I
I
~~~--ntT1--:
:I : I
Vos
v"
J
1
®V'~II
v,
I
Vss
I
C
Vn
C2
VOO
® voo~1
vp I
II
Fig.l - Power consumption with slow input edge,' a comparison of the
CI
@--j
®
1/4C040938
-4- -4-
®
-
(b) CD4011AE,
Top vertical - 5V/Division
Lower vertical - 2mA/Division
Horizontal
- 200ms/Division
@
RI
@~
2V/Division
~
v~~
tL=RIClln
C04093BE,
@
vp
I
VOO~
v,
I
~::lJilJ'
I
I
Vss
:
I I
I
I (
. Fig.13- RiJl'ng-edgedetector.
629
ICAN-6346
associated waveforms. Before power is applied, input and out·
VDD
C~T~L ®~.
®
®
;J;C R
put are at ground potential and capacitor C is discharged. On
power.on, the output goes high (VOD) and C charges through
R until Vp is reached; the output then goes low (VSS). C is
now discharged through R unti~ Vn is reached. The output
then goes high and charges C towards Vp through R. Thus
input A alternately swings between Vp and Vn as the output
goes high and low. One important advantage of this circuit
is that the oscillator is self·starting at power-on.
The osciUator period is given by:
T=Tl +T2
where
VDD-Vo
'I=Reln ~
aod
@
1 1 : 1
®
Vp
vn
Fig, 14 - FBlling-eti9fl detector.
Power-On Reset
A reset pulse is often required at power-on in a digital logic
system. This type of reset pulse is ideally provided by the circuit of Fig.15(a). Because of the high input impedance of the
Schmitt trigger,long reset pulse times may be achieved without
@
R2
@
®
92CS-25935RI
A range of astable oscillators may be easily constructed by
using the C040938. Fig.16 shows the basic circuit and its
VDD~"4CD4093e
®
l'
n
R
®
,
Fig. 16 - A,tabl. multivibrlltor.
I
Fig.
'7 -
ll~
01
~::rtn'
I
II
II
II
ON
I
(b)
~~
,~r
tal
II
1
lllk ....
~:
Vss
POWER....,I
(0)
1
FIg.fS - Gated .nable oscilkltor.
RI
Voo
Astable Oscillators
i
R2«RI
~c
Fig. 15 - Reset circuit; B comparison of the CD40938 with the CD4011/.
1
VDD~~DOD".®
the excess dissipation that results when both output devices are
on simultaneously. as in an ordinary gate device, Fig.l S(b).
,.)
I
1
:.vER
L
1
~:
v
:1
DN
T2, so that to get a I: I j mark.to-space ratio
the circuit of Fig.17(a) should be used. When the output is
low in the circuit of Fig. I 7, C is discharged through RI in parallel with R2, which shortens 72. IfR2 is:much smaller than RI,
short, negative-going pulses are produced, as in Fig.l7(b).
In general TI =F
VDD~
~:
I
I
I
I
:::r-uu-u'.
®
II
'2(:S-25937
Anable rncillator with controlled marlc-to-8plJr;e ratio.
In the circuit of Fig.18 the oscillator is gated by signal C
on the second input of the CD4093B. The oscillator output
is high while the gating signal is low; the' o,scillator then oscillates with the period T, given above, while the gating signal
is high.
Interfacing
The noise immunity of the COS/MOS NAND Schmitt
trigger is very high, typically greater than 50 percent ofVDD
in each state, as shown in Fig.4. Therefore, it is ideally
suited to circ~itry that requires a very high noise immunity.
Because of the hystereSiS built into the Schmitt trigger, it can
tolerate noise on a slow input edge without false switching at
the output, as shown in Fig.19. This noise performance permits the construction of an ideal interface from an industrial
environment to a COS/MOS logic system. as shown in Fig.20.
The CD4093B will function correctly under the most severe
conditions of input overvoltage and in spite of noise spikes of
up to hundreds of volts.. The input is kept between VSS and
VDD by DI and D2 with Rio typically 220 kilohm., as a
current-limiting resistor. Resistor R2 ties the logic input to
~
Uti
~VV
•. \'L1,
'I~
!'!llj
'lIA.
WII
[ILL IWl
II,,,,,
I'"
2V/Division
2ms/Division
Fig. 19 - RejllCtion of noig on slow input edl/lJ.
VDC
01
'NPUTF·
22011
02
TYPlfaL VALUE
* SAME
AS OTHER INPUT.
92CS-2!5939RI
Fig.20 - Indusrrial ..nlflronfMnt to COS/MOS In"rf~_
Vss should the interface input be open-circuited by the removal of a PC board from a system, for example. Capacitor
C 1, with R I, acts as a filter and enhances the noise-rejection
properties of the interface.
630 ____________________________________________________________________
ICAN-6466
Astable and Monostable Oscillators
Using RCA COS/MOS
Digital Integrated Circuits
by
D. V. DiMassimo &
A. R. Maslowski
CIRCUIT TECHNIQUES
COS/MaS integrated logic circuits are
being widely used in digital and other applications because of their high noise immunity,
extremely low power dissipation, and tolerance to wide variations in power-supply
voltages and operating temperatures. In addition, because their high input impedance
makes it possible to obtain large time
constants without the use of large capacitors,
COS/MaS gates can provide cost and size
reductions in multivibrator circuits'!
This Note describes several techniques
that may be used to compensate for the
normal threshold variation of MaS devices
in the design of stable multivibrator circuits
operating at frequencies up to 1 MHz. The
circuits shown can be formed by the use of
COS/MOS inverters or COS/MaS NAND or
NOR gates connected in an inverter configuration. NAND and NOR gates perform
the inverter function when all of the gate
inputs are tied together. This Note also
describes various applications for COS/MaS
multivibrator circuits: voltage-controlled oscillators, voltage-controlled pulse-width circuits, phase-locked voltage-controlled oscillators, frequency multipliers, and modulator/
demodulators (envelope detectors).
Astable Circuits
The circuits shown in Fig. I are those of
astable multi vibrators that use two COS/MaS
inverters (which may be taken from standard
RCA COS/MOS parts such as the CD4069B,
CD4007 A, CD4001, or CD4011). Fig. 2
shows the related waveforms. This simple circuit requires only two resistors and one capacitor and operates in the following manner.
Resistor RS' connected in series with the input
of the first inverter, limits the current
through the input protection circuit, Fig. 3.
In operation, the input to the first inverter
is clamped at one diode drop above VDD or
one diode drop below V SS. Depending on
the output levels of the two inverters, at any
instant C will be. either I charging or discharging through R. When the voltage at
point 2 in the circuit passes through the
transfer voltage level of the first inverter,
this inverter switches and causes the second
inverter to switch. The voltage at this point
Fig. 2 - RC-oscillator operating waveforms.
VDD
02
92C5·22811
92CS-27H6
Fig.
1 -
Vss
Astable multivibrator circuits that
Fig. 3 - Diode protection circuit.
employ two COS/MOS inverters.
2.' 0
•
.d~DO.3V}
Vo02 15V k
1 o~
203
~ 2.3
~)(
2.2
g
~
r?'~;DO"V}-
~~ ~
// ~VDD"ISV
VOO.IOV k=1
.~ ~
~ 2.2 0
A b7
~
~ r---...
w
"i= •
2.1
./
~
~
2.1 0
30
3~
-10
40
4$
eo
55
-
~
60
65
70
75
TRANSFER VOLTAGE (VTR)-PER CENT OF Voo
Fig. 4 - Discrete RC-oscillator time period as a function
2.
of transfer voltage.
•
.2
/"
2
o
VDOa:!t-
01
~
w
";::
.ere
..
.8 VDJ5V
,...-V
V
,
I:?
~
Voo
1:7
VTR-Z
.. , ." ." ..I, ...
~
0.001
~
f;::
,
0.01
,
,
0.1
I
10
,
100
CONSTANT-k
Fig. 5 - Discrete RC-oscillator time period as a function of constant, k.
631
ICAN-6466
is allowed to switch well above VOO and
below VSS because of Rs. The large swing
reduces the effects of variations in transition
voltage (VTR)' The variable characteristics of
the input protection circuit and their effect
on stability are greatly reduced because of
TABLE 1- FREOUENCY VARIATIONS OF ASTABLE MULTI·
VIBRATORS UNOER NORMAL CONOInONS
5
(VIR) (Voo . VTR)
I
2
3
4
KIVoo'Vol
- - - RCI, "":'''::':'-=-".,---:-:-::
(K+I)
KIVODTVTRI +IVTR vol
(K J
- - - RC I,
(K+I)
K IVoD + vol
....,-,-,.-=-=-=-:-....:::-----::-----::-:
KI2VOD VTR)+!VOO-VTR-Vol
4.08
3.92
4.76
4.07
4.42
5
(I)
CD4II8IIB
VOO"IOV VDD-16V
0.988
0.988
0.990
0.990
0.991
V...
VOO"IOV
IVI
YDD-&V
UNIT
NO.
(VOD+ VO)2
I
5.27
·5.19
5.58
5.26
5.25
I
2
3
4
The equation for the period, T, of the circuits in Fig. I is given by Eq. 1:2
(K
VOO"IOV
CVI
VOo"SV
NO.
Rs·
T"'-RCln
PERIODC ...I
vir.
UNIT
1.03
1.04
1.03
1.03
1.03
1.07
1.06
1.07
1.07
1.07
92C$-2737t
CD4001A
0.998
0.982
0.979
0.974
1.00
Q.986
1.01
0.962
0.981
0.965
1.00
0.990
1.01
0.962
0.991
V...
where K = Rs.
R
With the equation in this form it is easy
to see that as K approaches infinity the
variation in period as a function of VOO is
reduced to zero. This result is shown in
Fig. 4, where period as a function of transfer voltage is plotted for various values of
VOO and K, and in Fig. 5, which shows
CD4011A
UNIT
NO.
YDD-10V
CVI
VOO"&V
I
2
3
4
5
5.41
5.08
1.01
1.00
0.9900
0.983
0.996
5.76
·5.98
5.24
Fig. 7 - Astable multivibrator in which a NOR
or NAND gate is used as the first inverter
to permit gating of the multivibrator.
YDO-10V VDD-1ZV
VOO"IOV VOO"12V
1.02
1.03
1.00
0.996
1.00
1.03
1.04
1.01
1.01
1.00
Compensation For 50-Percent Duty Cycles
The variation in transfer voltage described
above affects the output-pulse duty cycle,
as shown in Fig. 8. A true square-wave pulse
is obtained only when the transfer voltage
occurs at the 50-percent point. However, the
duty cycle can be controlled if part oJ the
resistance in the RC time constant is shunted
rr-l rr-: rT-~ I
I L.lJ L.lJ Ll.J
as' 0.82M. R- 0.43 M.e· 910 pF. T- 25 C
temperature. Because the oscillators can
also tolerate changes in transfer characteristic
without frequency instability, they require
no thermal compensation. The frequency at
~55°C is extremely close to that at +12S o C.
period as a function of K for various values
of VOD' Variation in period with transfer
voltage is also reduced as K increases. This
variation decreases from 10 percent for
K = 0 to approximately 5 percent as K
becomes large.
There are some limitations on the value of
RS' It must not be made too large since a
time constant and phase shift is produced by
RS and stray wiring and breadboard capacitance. This shift creates a Switching delay in the circuit that changes the time
period and, in addition, may cause spurious
oscillations and glitches in the multivibrator
circuit. A reasonable value for K would be
anywhere from 2 to 10, with maximum and
minimum values for RS determined by the
above considerations.
Table I shows data measured when typical
units were employed in the circuits of
f":;\
\!.I
VOD+VD-~-....
___ Yt,·e7 "11oOF' YD
V~VD - - - . - -
..
..,I
--Yu.31 "110 OF' YD
...
92CS-27:s80
•
"•
Fig. B - Waveforms showing effects of tfBnsfer
voltage· on multivibrator frequency.
I
DRAIN SUPPLY
VOl.TAGE·+IDY
'0
..
~
~=-"·c
•
..
,
."- •
DC INPUT
Fig. 6 -
•
.
,
VO~TIoGE-Y
IZ
"
Jitter In Astable Circuits
Transfer charaCteristic as
of temperature.
8
function
Table II shows data measured on typical
units at temperature extremes. The astable
multivibrators shown in Fig. 1 can be gated
on and off by use of a NOR or NAND gate
as the first inverter, as shown in Fig. 7.
Fig. 1. Fig. 6 shows a typical transfer
~haracteristic as a function of temperature.
The curve shows that there is very little
change in characteristic from low to high
out with a diode, as shown in Fig. 9. Because adjustment of this diode shunt to
obtain a specific pulse duty factor .causes
the frequency of the circuit to vary, a
frequency control, R3' is added to compensate for this variation. It may also be
necessary to reverse the diode to obtain the
desired duty factor. The frequency of any of
the circuits shown can be made variable by
replacing the timing resistor with a potentiometer.
When using the astable circuits described
above with other equipment· and/or circuits
that require off-the-board connections, some
TABLE II - FREQUENCY VARIATIONS OF ASTABLE MULTIVIBRATORS AT TEMPERATURE EXTREMES
PERIOD
CD4IIaI8E
UN
NO.
3
VDD-I5V
=,,""C ...c
960
961
.96'
.96'
....
0.974
0.974
0.975
0.973
0.975
VDD"'0V
·s
ern"
CD4011AF
CD&001A'
VDD-1I5V
VDD-SV
VDD-lOV
VDD-12V
VDD-SV
VDD-10V
.....c 16"c .....c 16"c .....c ,25"c .....c ,25"c ....·c ,25"c ....·c ,25"c ....·c
no.,
0.997
.992
1.000
0....
1.011
1.011
1.010
1.011
1.009
1.-0.82 .., R-O.43 N,C- 910pF.
1.023
1.033
1.028
1.033
1.029
1.047
1.045
1.044
1.045
.....
0.930
0.926
0.914
0.914
0.930
0.92'
0.929
0.902
0.903
0.923
0.934
0.947
0.926
0.929
0.955
0.931
0.947
0.918
0.923
0.930
0.936
0.953
0.929
0.936
0....
0.943
0.956
0.920
0.935
0.938
0.937
0.931
0.925
0.933
0.934
0.9]7
0.934
0.927
0.931
0.933
0.'"
0.942
0....
0....
0.."
VDD-12V
1m"e
...·c
1moe
0.955
0....
0....
0.943
0.95S
0.958
0.951
0.958
0.950
0.962
0.960
0.956
0....
0.949
92CS'2738J
D.'"
Fig. 9 - Astable multivibrator in which a dutycycle control is added.
632 _____________________________________________________________
ICAN-6466
Tl' is approximately 1.4 times Rl Cl'
Unlike the astable circuit, which shows
little variation in frequency over the temperature range from _55°C to +125°C, the
monostable multivibrator shows some change
in time period; the variation is less than 10
jitter in the output waveform may be
encountered. This jitter is introduced into
the circuit by noise picked up by the
connecting cables and board capacitance
and stray wiring. This problem can be
corrected with the addition to the circuit
of an inverter, as shown in Fig. 10, that
isolates the frequency determining circuit
nodes from pickup by the output node. The
CD
92CS-21384
Fig. 12 - Compensated monostable multivibrator
circuit.
~PUT
~
inverter A, and the output of inverter B becomes low. Asi capacitor Clldischarges negatively, it charges through resistor Rita the
1/2CD40898
92C5-27382
Fig. 10 - Astable multivibrator circuit with
buffered output.
CD
output to the astable circuit is then taken
from the output of the added inverter.
Monostable Circuits
Fig. I I (a) shows a basic one-shot circuit
that uses a single RC time constant. 1bis
circuit operates well provided it is adjusted
to the COS/MaS unit used. If no adjustment
is made, the period T can vary from unit to
unit by -40 percent to +60 percent if the
transfer voltage varies by ±33 percent, as
shown by the waveforms in Fig. II (b).
The use of some resistance r, Fig. II, is
generally advisable to limit the current if
VOO is greater than 5 volts.
0Jl
® LJ'-;:~=
__ J;::::====
@
®
~-:-
-l
__ :
V,,-33%OFVDD
\-VARIATIDN IN
TIME PERIOD
(b)
\ 92("5-27383
Fig. 11 - Basic one-shot multivibrator circuit:
(a) circuit diagram, (b) waveforms.
Compensated Monostable Circuit
Fig. 12 shows a compensated monostable
multivibrator type of circuit that can be
triggered with a negative-going pulse (VOO
to ground). In the quiescent state, the output of inverter B is high. When a negativegoing pulse or spike is introduced into the
circuit, as shown in the waveforms of
Fig. 13, capacitor C1 becomes negatively
charged to ground and the output of inverter
A becomes high. Capacitor C2 then charges
to the value of VOO through diode 01 and
LOW
~
@
-'-------::==========1
~
Yt,·S:S,,-QFYOD
~--I---
-H-----,.l.:-------,
@
I
@
HIGHJl
@HIGH
LOW
511------
'2'---1
"Vt,·»"JI.OF YDD
- - - i : = T I : = : I j - '- - - - - -
I
TRANSFER VOLTAGE POINT-INVERTER A
92CS-2738!:\
Fig. 13 - Voltage waveforms for monos table
multivibrator circuit when a
negative-going trigger pulse is
applied.
value of VOO (waveform 2). The output of
inverter A remains high until the voltage
generated by the charging of CI is equal to
the transfer voltage of inverter A (Le., until
the waveform generated by the charging of
C I passes through the transfer-voltage curve
of inverter A); at that instant the output of
inverter A becomes low. Diode 01 temporarily prevents the discharge of capacitor C2,
which was charged -when inverter A was
high (waveform 3). Capacitor C2 then commences to discharge to ground through
resistor R2 (waveform 4). The output of
inverter B remains low until the voltage
genera ted by the discharge of C2 becomes
equal to the voltage at the voltage transfer
paint of inverter B (Le., until the waveform
genera ted by the discharge of C2 passes
through the transfer-voltage point of inverter
B); at that point the output returns to its
high state (waveform 5).
The advantage of using two inverters
fabricated on the same chip is that they
have similar transfer voltages. When two
equal RC time constants are used (R I CI =
R2C2), the effects of variations in transfer
voltage from device to device are effectively
cancelled out, as shown in Fig. 14. Eq. (I)
can be used to show that the maximum
variation in the time period T is less than
9 percent. The total time for one period,
Fig. 14 - Waveforms showing the cancelling effects
of transfer·voltage variations of the two
COS/MOS inverters when two equal time
constants are used.
percent. Table III shows data measured on
five units over the temperature range cited
above. At 25°C, the variation in the time
period T from unit to unit is very small,
usually less than 5 percent at a VOO of 10
volts.
The output from inverter B can be held
in the low or zero state as long as the
R2C2 time constant is reinforced by another
triggering pulse before the discharge waveform it generates passes through the transfervoltage point of inverter B.
Diode 02 in Fig. 12 is internal to the
COS/MaS circuit. As discussed for the
astable oscillator, it is part -of the input
protection circuit shown in Fig. 2, and
clamps the input at VOO'
Figs. IS and 16 show two variations of
the monostable circuit together with their
associated waveforms. The circuit of Fig. IS
triggers on the negative-going excursions of
the input pulse in the same manner as the
circuit of Fig. 12. The output pulse is
positive-going and is taken from the first
inverter. 1bis circuit does not need an
external diode. The circuit of Fig. 16 triggers
on the positive-going excursion of the input
pulse, and then locks back on itself until the
RC time constants complete their discharge.
The circuits of Figs. 15 and 16 cannot be
retriggered until they return to their quiescent
states.
Low Power Monostable Circuit - The
monostable circuits discussed thus far dissi-'
pate some power because one or both of the
inverters are on during the charging or discharging of the capacitor. 1bis power dissipation will be extremely low provided the
633
ICAN-6466
TABLE 111- FREQUENCY VARIATION OF MONOSTABLE MULTIVIBRATORS OPERATING AT THREE TEMPERATURES
PERIOO(m,1
UNIT
"NO.
1
2
3
4
5
-li6'c
0.40
0.38
0.40
0.36
0.42
0.30
0.34
0.32
0.35
,0.34
VOO-5V VOO-l0V VOO-15V VOO":SV VOO-l0V VIio-16V
0.74
0.76
0.75
0.74
0.76
0.41
0.40
0.40
0.42
0.41
PERIOO(."I
UNIT
NO.
1
2
3
~
5
--55"c
0.45
0.46
0.47
0.46
0.44
I
2
3
4
5
0.41
0.41
0.40
0.42
1.42
0.50
0.50
0.52
0.50
0.48
0.32
0.36
0.34
0.36
0.36
0.41
0.42
0.43
0.44
0,41
+125 C
Q
_55°C
0.50
0.50
0.54
0.53
0,51
0.46
0.46
0.49
0.47
0.46
"one-shot" pulse width is short compared to
the overall cycle time. Fig. 17 shows the
current waveform associated with the circuit
of Fig. 12. This waveform is very wide at
the base, and some current flows for approximately twice the time period.
®
L..---
~~
I
CD4001A
VDD-6V VOO"10V VOO-12V VOO-6V VOO"10V VOO- 12V
PERIOO(... I
UNIT
NO.
0.74
0.76
0.75
0.74
0.76
0.32
0.36
0.34
0.36
0.35
+26°C
VOO-6V VOO-l0V VOO-12V
0.39
0.40
0.40
0.42
0.40
+85"c
+25"c
VOO-SV VOO-l0V VOO- 1SV
0.73
0.74
0.76
0.76
0.75
CD4089BE
0.41
0.43
0.43
0.43
0.42
0.46
0,47
0,49
0.48
0.46
0.51
0.50
0.55
0.54
0.51
CD4011A
@~
~ - _ -,1./\
~
"'-----
2m. CURRENTO
92CI-2.7389
Fig. 17 - Current \"lBL'eforms for the diiJdiJ-comptJn-
sated multivibrator shown in Fig. 12.
Fig. 18(a) shows a circuit using the
CD4007 A. This device dissipates much less
'DO
+12SoC
+25°C
VOO"SV VOO"10V VOO" 12V VOO"SV VOO=10V VOO"12V VOO"SV VOO-l0V VOO"12V
0.58
0.55
0.56
0.55
0.56
0.53
0.50
0,52
0.52
0.50
0.49
0.45
0.44
0.46
0.46
0,57
0.54
0.55
0.56
0.57
0.52
0.50
0.51
0.52
0.51
0.48
0,44
0.44
0.46
0,46
o
Jn~
® --,
@
0,52
0.50
0.50
0.52
0.50
0.56
0.55
0.55
0.57
0.58
0.48
0.45
0.44
0.46
0.46
___________,
< ..... -~~.67".OF V~D
~
,,-33"4 Of VDD
OUTPUT
J"=T,---!
~~.~:~!~,~ ~~~
@---'!~
I
I
@ ~-------------
@
Jl
(a I CD4007A
I
I
I
®I~
~
i
.. . "VOLTA"'G't
Ibi
I.'
92CS-27387
Fig. 15 - Monostable multivibrator that is triggered by a negative-going input pulse:
lal circuit diagram, Ibl waveforms.
:
©j
@
o 11'--------
-t--TI --,r------@ --L--,--r--,
"
~~~~:~-------------
I
CD
''1'-___
'== =:1-- _~n'
T
Im., _ _ _ _ _ _ _
j
THRESHOLD
VOLTAGE
CURRENT
®
@~
,.,
,.,
,2CS.-27388
Fig. 16 - Monostable mult;vibrator that is triggered by 8 positive-going input pulse:
lal circuit diagram, Ibl waveforms. '
!
b!
9ZCS-27390
Fig. 18 - Low-power monostable multillibrator:
(a) circuit diagram, (b) waveform.
power than the other circuits shown but- is
not as stable; circuit operation is described by
the waveforms in Fig. 18(b). In the quiescent
state, ihe p-channel transistor of the first
inverter is biased off while the n-channel
transistor (which derives its control from the
output of the second inverter) is biased on.
Therefore, the output at C is low, and that
at D is high. Whenla negative-going pulse' is
introduced into the circuit through capacitor
Cl, the p-channel device is turned on.
634 _____________________________________________________________
ICAN-6466
Capacitor', C2 then charges to VOO' the
output at 0 becomes low, and the n-channel
device of the first inverter is turned off.
Capacitor Cli immediately begins to charge
to VOO through RI (waveform B). The
p.channel, transistor remains on, keeping
capacitor C2 charged to VOD until the voltage generated reaches the threshold voltage
level and turns the transistor off. The
n-channel transistor of the first inverter is
still off because the output of the second
inverter (waveform 0) is still low. When
the p.channel device of the first inverter
turns off, capacitor C2 begins to discharge
through resistor R2 (waveform C) to ground.
As C2 discharges, the voltage passes through
the threshold-voltage point of the second
p-channel transistor, and that transistor begins to turn on. The voltage then begins to
rise (waveform 0), and the n-channel device
of the first inverter turns on and provides a
second discharge path for capacitor C2' As a
result, the output waveform changes state
from low to high very rapidly to complete
the cycle.
The major advantage of the circuit of
Fig. 18 is its low power dissipation. Because
the circuit depends on the p-channel tran·
sistor threshold, the time period T varies
from unit to unit and with temperature
variations. Some compensation can be provided if the R2C2 time constant is made
approximately three times larger than the
RI CI time constant, as shown in Table IV.
TABLE IV - FREQUENCY VARIATIONS OF
MONOSTABLE MUL TIVIBRATORS WITH
TEMPERATURE WHEN R2C2 TIME CONSTANT IS LARGE COMPARED TO RICI
TABLE V - FREQUENCY VARIATIONS OF
MONOSTABLE MULTIVIBRATORS WITH TEMPERATURE WHEN C2 CONSISTS OF STRAY
CAPACITANCE ONLY
CD4007A
UNIT
NO.
I
2
3
4
PERIOO WITH VOO • 10 V
Im.1
-55'C
+25°C
125"C
0.121
0.110
0.120
0.103
0.125
0.115
0.124
0.105
0.129
O.IIB
0.127
O.IOB
APPLICATIONS
Voltage-Controlled Oscillators
Fig. 19 shows a circuit similar to the circuit in Fig. I. C is variable (by adjustment
of Cx) and R is variable (by adjustment of
VA)' The value of R varies from approximately I kilohm to 10 kilohms. These
limits are determined by the parallel combi-
frequency. IIf Rx is less than 10 kilohms,
there is a value of VA that will cause the
oscillator to cut off. Table VI lists values of
TABLE VI-PULSE WIDTH ASA FUNCTION OF VA
ANOVOO
'
PULSE WIOTH Il'
VA
VDO= 5V
VOO= 10V
VOO=12V
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
30
30
30
2B
26
26
28
2B
28
28
27
27
22
20
28
26
24
22
21
-
20
20
21
c= 0.OO15pF, Period = 55 ps
pulse width (B in Fig. 20(b» for various
values of VA and VOO' Fig. 20(b) shows the
waveform for the circuit described.
OUTPUT
C04007A
")0...........-
....
OUTPUT
NOTE:
INYlRTERS AND n- CHANNEL DEVICE ARE AVAILABLE IN
Ii -.GLE COS/MOS PACKAGE:
I-CD4007
TYPICAL VALUES:
RS
-rooto
R)( • 35ktl
C • 0.0005 - 0.0025 p.F
(.)
RI • 10 kA
ex • 0.001
Rs -IOOkO
O:s VAS Veo
- 0.004 ~F
.. USE PROPER SUFFIX TO DENOTE PACKAGE
REQUIRED - SEE APPENDIX.
92CS-22878RI
Fig. 19 - Voltage controlled oscillator.
92CS-22882Rl
(b)
Fig. 20(.} - Voltage controlled pulse·width
CD4007A
UNIT
NO.
PERIOD WITH VOD = 10 V (m,)
55C
25 C
I
0.740
0.759
2
0.740
0.754
125°C
0.779
0.760
3
0.730
0.735
0.735
4
0.750
0.750
0.759
RI = lOOK, RZ- 1M, r= 36K, C I =C2= 9JOpF
Current in the circuit of Fig. 18 can be
minimized by removing capacitor C2 so
that only stray capacitance is present at the
input of the second inverter. A comparison
of time-period variations under this condition
is shown in Table V. Again, the variations
from unit to unit are caused by differences
in p-channel transistor threshold.
nation of RI (i 0 kilohms) and the resistance
of the n-channel device, which varies from
I kilohm (Rem) to approximately 109 ohms
(RoFF)'
When VA = VSS, the n-channel device is
off and R = RoFF II RI, which is approximately equal to RI or 10 kilohms because
RoFF is very much greater than RI. When
VA = VOO' the n-channel device is fully
on and R = RoN II Rl or approximately
RoN, which is equal to I kilohm because
RoN is very much less than R I'
The center frequency of the oscillator is
varied by adjustment of Cx '
Voltage·Controlled Pulse-Width Circuits
Fig. 20(a) shows a further modification
of the circuit of Fig. I(a); in the modified
circuit the pulse width may be modulated
by varying VA, but only if Rx is sufficiently
high. As an example: if C = 0.0022 microfarads, Rx will be approximately 3S kilohms.
Lower values of Rx have an adverse effect on
circuit, (b) output waveform.
Phase-Locked Voltage-Controlled Oscillator
The voltage-controlled oscillator, VCO,
can be operated as a phase·locked oscillator
by the application of a frequency-controlled
voltage to the gate of the n-channel device.
Fig. 21 shows the block diagram of an FM
discriminator using the phase-locked VCO.
Block A is the same circuit of Fig. 19. The
output of the phase comparator is fed to the
gate of the n-channel device (VA)' If the
two inputs to the phase I comparator are
different, the change of VA causes the
output frequency of the VCO to change,
92CS-21391
Fig. 21 - VCO used in phase·locked loop.
635
ICAN-6466
Fig. 22. This change is divided by 2N and
fed back to the phase comparator.
'NPUTe-.
3
~
·
4
f
R
VDO-12Y
R.
~
VDO
PA~~~!o';?"NT.
~
--1.,---
FRED.
OUT
ModulationfDemodulation (Envelope
Detection)
OUTPUT
(.1
L
,-----,
(j) vssJ
VDD
,.1
'OOk
"ss
,.
,.
~
~
- - - -- - - - - -.'h'->'-J..~+'r-}-
V
I
i!l
a
~
•
I
•
!/
VDD
/
I
t
® YrR ---T"T·T"l"T"rr·r----------
.OOI5~F
Vss
/
/
If
2
10
20
/
VDD
@)
"ss
(
.,
References
92CS-27393
I. Further information on astable and monostable circuits using MSI devices may be
. found in RCA Application Note ICAN6230, "Using the C04047 in COS/MaS
Timing Applications'~ and in the RCA Data
Sheet for the C04098 Dual Monostable
Multivibrator.
(Note: COS/MaS Hex Buffers CD4009A
and Quad Buffer C04041 A are not recommended for use as multivibrators because
of very high power consumption in the
linear mode for long time constants. In
addition, the hex buffers have a large
imbalance between Isource and Isink
capability, which makes oscillator start-up
more unpredictable.)
Fig. 24 - la) Modulator circuit, Ib) waveforms.
40
,.,
1080100
FREQUENCY-lHI:
Fig. 22 - la) VCO, Ib) control voltage as a function
of output frequency.
(.1
Frequency Multipliers
Fig. 23(a) shows a frequency doubler. A
2N multiplier can be realized by cascading
this circuit with N·l other identical circuits.
The leading edge of the input signal, differentiated by Rl and Cl and applied to input
,
VDD
vss
Voo
•vss
Voo
3
R,
Vss
1-314 CD40llA
RI· R2· 10 k n
CI • C2 = 0.001 p,f
(.,
POINT IN
CIRCUIT
WAVEFORM
~
v
3.
· -y
..
(bI
L
2. For the derivation of this equation, see
RCA Application Note ICAN-6230, "Using
. the CD4047A in COS/MOS Timing Applications,"
92CS-2739.
Fig. 25 - la) liemodulator circuit, Ib) waveforms.
,.~
..
Pulse modulation may be accomplished
by use of the circuit shown in Fig. 24(a).
This circuit is another variation of Fig. 1.
Modulation or envelope detection of
pulse-modulation waves is performed by the
circuit shown in Fig. 25(a). The carrier burst
is inverted (by inverter A); its first negative
transition at point 2 turns on the diode (D)
to provide a charging path for C through the
n-channel resistance to ground. On the
positive transition of the signal (at point 2),
the diode is cut off and C discharges through
R. The discharge time constant (RC) is
much greater than the time of the burstsignal period. Point 3, therefore, never
reaches the switch point of inverter B until
the burst has ended .. The waveforms for 4
points in the circuit are shown in Fig. 25(b).
V-
No. I and the NAND gate, produces a pulse
at the output. The trailing edge of the input
pulse, after having been inverted, is differ·
entiated and applied to input No. 2 of the
NAND gate; it produces the second output
pulse from the NAND gate. The waveforms
for five points in the circuit are shown in
Fig. 23(b).
V
~
(0'
92CS-27392
Fig. 23 - (a) Frequency-doubler schematic,
Ib) waveforms.
636 ___________________________________________________________________
ICAN-6525
Guide to Better Handling and Operation
of CMOS Integrated Circuits
22M
-t
HIGHVOLTAGE
s~r 100~~I
by J. Flood and H. L. Pujol
r"'·
560
TO
o--"VV'v- DEVICE
CH-HUMAN BODY CAPACITANCE TO GROUND
Rs. BODY
SOURCE RESISTANCE
92CS-27968RI
This Note recommends specific handling
and operating practices that minimize the
probability of damage to CMOS integrated
circuits in the manufacturing operation and
the field environmen t.
A description of various gate.oxide net·
works that protect against electrostatic dis·
charge in both A·series and B·series RCA
COS/MOS product is provided. A practical
explanation of the SCR latch·up mechanism
and its associated failure mode is given. In
addition, operating procedures that help pre·
vent device malfunction are described.
01
INo-..-'VV'v---O--+...-"V\I'v+-I----+
CJD
-100 IlA
Voltage Breakdown Tests
Breakdown tests are performed on the n
and p channels of COS/MaS devices in a
manner similar to that of quiescent-Ieakagecurrent tests_ The purpose of the breakdown
test is to assure that channel breakdowns can
only occur at voltages above the maximum
guaranteed supply voltage; Table II gives
limits by series. Voltage breakdown test
circuits are shown in Fig. 17. With switch SI
in position I, the n devices are on and the p+to-n-substrate diodes are stressed. With switch
SI in position 2, the p devices are on and the
n+-to-p-well diodes are stressed.
Table II - Channel-Breakdown Limits
Max.
Test Voltage Curren t Limit
92CS- 26836
Fig. 16 - Intrinsic protection circuitry at each external
input of a CDS/MDS device_
CD4000A Series
15 V
C04000B Series
lOV
643
ICAN-6532
Note that in functional testing, the pass/fail
criteria for high and low out put states of the
device is a maximum of 500 millivolts
deviation from VOO and VSS.
Voo
n Substrate
Voo-+---,
p Channel
n Channel
VSS _
......_ _..J
pWell
Cbl
92CS- 28388
Noise Immunity
Noise immunity, VNL, VNH, is defined
as the maximum low·level input (VtU for
which an output logic. level does not change
state, and the minimum high·level input
(VIH) for which the output does not change
state.
The typical noise immunity of a COS/MaS
device is 45-percent of VOO; i.e., the input
voltage low and high levels will typically
change 45·percent of their values before the
output logic level ,·hanges. VtL is guaranteed
to be a maximum of 30 percent of Voo; VIH
is guaranteed to be a minimum of 70 percent ofVOO.
Cal
Noise Margin
Fig. 17 - Voltoge.IJreakdown test circuit.
Output-Voltage Levels
The output-voltage low (VoU and the
output-voltage high levels (V OH) of a
COS/MaS device approach VOO and VSS
within a few millivolts. Tests for VOL and
VOH are primarily bench-type static tests
performed as shown in Fig. 18. With switch
SI in position I, one n device is turned on
and the p devices are turned off. The voltage
output will be at VSS + 0.05 volt or VSS - 0
volt. With switch SI in position 2, all p
devices will be turned on and the n devices'
will be turned off. The voltage output will be
at VOO + 0 volt or VOO .- 0.05 volt.
Few automatic test sets have the resolu·
tion to measure an offset of SO millivolts
from the VDO and VSS supply with satis·
factory accuracy at reasonable test speeds.
Noise margin is the difference between a
device output voltage and VlL; i.e., the
magnitude of noise-margin voltage is that
noise voltage that may be added to any
COS/MaS input/output mode.
Noise margin and noise immunity are
guaranteed to meet data-sheet specifications
by the performance of input voltage tests, as
shown in Fig. 19. The input voltage test is
performe"d for each device as in functional
testing. VIL and VIH are applied according
to the device's truth table. The outputs are
monitored for an expected VNMH and
VNML state (voltage noise margin, voltage
noise margin low).
VNML=VOL-VIL
VNMH = VOH - VIH
VIL =VNL
VIH=VOO-VNH
Output Drive Current
Tests for output drive currents-ION (or
IOU, sink current, and lOp (or 10H), source
current-are conducted by means of the cir·
cuits shown in Figs. 20 and 11 .
Cal
92CS-26831
~VOL
---l ~
n Channal On
6
Vss
S1 In Position 1
51 in Position 2
Cbl
92CS-26838
Fig. 18 - rest of output voltage levels
(VOH and VOL' of a CD4001 A.
The purpose of the sink·current test, Fig.
20, is to determine the amount of current
that the output n device is capable of sinking
(with the n channel on) at a given output·
voltage level. Fig. 20(a) shows a C0400lAO
device whose VOO is equal to 10 volts and
whose voltage output is specified at 0.5 volt.
The amount of current that the output device can sink varies depending upon the
voltage drop across the device (VOS) for a
fixed VGS. n·channel drain characteristics are
shown in Fig. 20( c).
The purpose of the source·current test,
Fig. 21, is to determine the amount of
current that the p device is capable of
sourcing (with the p channel on) at a given
output-voltage level. Fig. 21(a) shows a
CD400lAO device whose VOO is equal to
10 volts and whose voltage output is specified
at 9.5 volts. Under these conditions, the
644 ____________________________________________________________________
ICAN-6532
[-
Inputs
Outputs
VILMax.
Connect For All
Functional States
~
COSIMOS
Device
Under Tesi
VIHMin.
92CS-28374
output dlive current will be a minimum of
0.25 milliampere. The amount of current
that the device can source varies depending
upon the voltage drop across the device
(VOS) for a fixed VGS. p-channel drain
characteristics are shown in Fig. 21 (c).
These current-voltage relationships can be
verified, theoretically, by the use of the
following equations.
In the triode region:
r
vos2l
2K'W
IO=-Q- LVOS(VGS-VTH)-2J0';;
Fig. 19 - Input-vo/rage4evel test arrangement.
VOS-4>-L
BUFFERED outpuTS
1113
92CS· 29244 R I
Fig. 2 - Detailed diagram 0/ master-.lave /lip-flop, the sequential memory element
counters including the CD4024.
0/ most static
____________________________________________________________________ 649
lCAN-6S52
"0"
"I"
CLOCI(
14
CLOCK 13
INHIBIT
RESET 15
•
"2"
10
~
.
0
"3"
"4"
"5"
~
"~
"6"
"7"
"e"
VOO=16
VSS =8
"
"9"
12
CARRY
OUT
92CS-25072R2
Fig. 3 - Functional and logic diagra"., for 5-,tage }ohnoon decade counter type CD4617.
Fig. 4.- Functional and logic diagrs"., for BCD counter type CD4518.
If it is assumed that the input
capacitance of the COS/MOS gate is small
compared to the output load capacitance.
it can be shown that the power consumption of the binary ripple counter is
not too different from that of the other
counters. With the CD4013 Quad 0 FlipFlop. shown functionally in Fig. 5. used as
the example and the dissipation
characteristics curves for this device in
Fig. 6. one can calculate the power
dissipation of a divide-by-sixteen binary
ripple counter and compare it to that
Johnson counter.
system IS actuaRy a divitle-by-two system.
The divide-by-sixteen counter would
require 06 = :z4J four flip-flops. At a
clock frequency of 4 MHz. aVo 0 of 10
volts. and an output capacitance of 15 pF.
this 4-stage network would ope~ate at the
fu\luwin!( frequl'ncies and. from Fig. 6.
di ...,il'att· the indicatt·(\ power:
ora
Sla!(e I
2 x lOll Hz
Sls!(e 2
I x lOll Hz
Sta!(e :J 0.:> x lOll Hz
Sta!(e 4 0.2:> x HIll Hz
The timing diagram given in Fig. 7
shows that each toggle flip-flop in a binary
Tnlall'ower :i.:i x J1):J.
650
Vss
p.w= 5.5 mW
Fig. 5 - Functional diagram of dual D
flip-flop type CD4013.
ICAN-6552
In a 12-bit system the binary counter is
by far the most com pact. In systems using
a larger number of bits this advantage is
even greater and is becoming increasingly
important as manufacturers develop MSI
and LSI devices. No longer is the constraint on a design the pellet size. but
rather the number of output pins the
design uses.
o
!i
~
10
.0'
10 5
.0 4
105
INPUT FREQUENCV(t.)-HI
106
'0'
Fig. 6 - Di&.ipation characteristics CUrtJe6·
for type CD4013.
For a Johnson counter. which operates
f.·eding back the inverted output of the
final stage. the number of stages utilizing
the CD40 I:J f1ip-flnp ne ..ded for a divideby-sixteen C()\lIlter is .. ight. The uutputs
art· changing at a rate uf
b~·
Each flip-flop at this frequency and at an
operating voltage of 10 volts and an output.
load of 15 pF would. from Fig. 6. dissipate
approximately 1.0 x 103 Ii W. The total
dissipation for the eight flip-flops.
therefore. would be 8 x 1.0 x 103 Ii W =
8.0mW.
In a system where the goal is a specific
output frequency and where the input
frequency is' variable. the binary ripple
counter is and has been the choice of many
designers. An excellent example is the
design technique usually used in digital
clocks and watches. An output of I Hz is
obtained by cOllllting down from a typical
4.194·MHz oscillator or a 32. 768-kHz
oscillator using the appropriate number of
binary stages.
Device Selection
Although the binary counter has advantages. it does have the handicap of
interfacing a non-binary world. It is
difficult to decode accurately a non-binary
count from a binary counter because a
complex decoding scheme is needed and
because the possibility of decoding spikes
is increased. As shown in Fig. 8. a binary
counter needs many external gates for
decoding purposes. In addition, to change
This comparison shows that the power
dissipation of these two systems is fairly
close in value and should not be the major
deciding factor as to which system to use
in a specific application.
04
DECODING COUNT
I
r-PouibielPike
V
;:'sed during
change from
D'Q~
eQunt 9 to
by
~f2·fO/2
10
a, falling
riling
92CS-29241
I
0.
03
a,
0,
'0
The most significant advantage of
binary counters is the amount of information which can be realized from a
given number. of bits. A comparison of a
binary 12-bit system with BCD and
Johnson counter 12-bit systems shows that
the binary system has 4096 separate
states. the BCD system has 1000 separate
stages. and the Johnson system has 24
separate states.
10000 - 1
11000
11100
11110
11111
01111
00111
00011
00001
-
2
3
4
5
6
7
8
9
Fig. 9 - External gate required by lohnson
counter; counting sequence requiring only
one bit change\at a time.
One disadvantage of both the binary
and the Johnson counters is the difficulty
of interfacing a decimal world. This
difficulty instigated the development of
the binary-coded decimal system. In the
BCD system. by grouping four bits into
each single decimal number. the actual
count becomes much easier for human
interface.
priorto~
Fig. 7 - Timing diagram for dillide-by-two
flip-flop.
Information Density
00000 - 0
QI
~ (.,
V
CLOCK~r-tJ'"l....rlJL fl ·'0
bit is changing at a time, as shown in Fig.
9. Decoding of the Johnson counter with
one inverter and one two-input gate can
always be accomplished by decoding a 1;0
or 0; I state between the two appropriate
outputs. In addition, because only one bit
is changing when the counter moves from
one count to the next, no decoding glitches
will develop from this decoding network.
Fig. 8 - Typical external gate required by;binary
counter for decoding; spike possibility caused by
non-simultaneous bit change, and, counting
sequence requiring simultaneous bit change.
from count 9 to count 10. two bits must
change simultaneously. Consequently, if
one bit changes prior to the second. a false
count of 8 or II could be decoded.
To avoid this kind of "glitch"
possibility the Johnson counter was
designed. In the Johnson counter only one
By way of summary. binary counters.
because of their high information density.
low power consumption. and relative
simplicity. are well suited for applications
such as industrial timers. watch or clock
operation. binary arithmetic systems. and
microprocessor systems.
J ohn.on countt'rs. because of their
decoding ease for any given count, are well
sliited for industrial controls. sequencers.
low
divide-by-n
decoding.
and
programmable divide-by-n counters.
BCD counters, because of their ease of
interface for human control, are well
suited for programmable divide-by-n
counters, counting systems for sevensegment readouts. industrial controls. and
frequency synthesis.
651
leAN-6558
Understanding Buffered and
Unbuffered CMOS Characteristics
by R_ E_ Funk
INTRODUCTION
Both buffered and unbuffered CMOS
B-series gates, inverters, and high-current IC
products are available from RCA; each product classification has application advantages
in appropriate logic-system designs. Recently,
many CMOS suppliers have been concentrating on promoting buffered B-series products with applications literature focusing
on the attributes and use of the buffered
types. This practice has left an imbalance in
the understanding and application of both
buffered and unbuffered gates and, in many
instances, customers are not using unbuffered
products when they are the best for the intended application. This Note narrows the
misunderstandings involved in this issue by
presenting and discussing the relative merits
of the buffered and unbuffered CMOS devices.
Background
Historically, most CMOS gates, inverters,
and high-current IC products were unbuffered,
and exhibited good logic-system performance, speed, noise immunity, and quasi-linear
characteristics in a wide variety of applications. As the scope of CMOS products
broadened and more manufacturers entered
the scene, buffered gate and inverter products
were brought out by RCA and others.
While RCA confined initial buffered products to new OR and AND functions,
other manufacturers introduced buffered
NOR and NAND gates having the same
generic 4000A'series designations as the
original widely·used unbuffered gates. Many
users were surprised by the non-interchangeability of the devices in applications where
speed, noise immunity, output impedance,
and linear gain-bandwidth characteristics were
critical. It is of immense benefit to CMOS
users to have available the definitions and
designations of both buffered and unbuffered
B-series CMOS devices as determined by the
JEDEC CMOS Standardizing Committee
under the cognizance of the JC40.2 JEDEC
Committee of EIA. The official "JEDEC
definitions are repeated below along with
detailed explanations and examples. Comparison of user-oriented characteristics and
the use of buffered and unbuffered gates are
also reviewed.
Definitions
Buffered CMOS-A CMOS device for which
the output on impedance is independent
of any and all valid input logic conditions,
both preceding and present, is said to have a
buffered output or to be a buffered CMOS
device. All such products are designated by
the suffix B.
Unbuffered CMOS-Products that meet Bseries specifications except that the logical
outputs are not buffered and the VIL and
VIH specifications are 20 percent and 80 percent of VDD, respectively, are marked with
the UB designation, such as lmciuamg,
not limited to):
but
4000UB
4025UB
400lUB
4007UB
4002UB
4009UB
401!UB
404!UB
4049UB
4012UB
4023UB
4069UB
The official JEDEC definitions are primarily applicable to gates, inverters, and
high-current (inverting) drivers such as the
specific UB types shown above. Non-inverting
gates and drivers as well as all MSI and LSI
B-types are by definition B types. There are
special analog I/O types that are also included as B types since they conform to all
B standards except that they have special
analog I/O circuitry. Examples of parts that
have no buffered or unbuffered significance
are:
4016B
4053B
4046B
4067B
4051B
4097B
4052B
4066B
4511B
4528B
RCA will make available both types of
CMOS gates. Logic examples of the buffered
and unbuffered 2-input NOR gate are shown
in Fig. I. Note that the buffered logic can be
implemented by either a 2-input NOR function followed by two inverters or by two
input inverters followed by the 2-input
NAND gate and an output buffer. RCA uses
the latter logic configuration, which has the
advantage of optimizing device noise immunity by negating the effect of stacked
devices at the input. This characteristic is
~PUT
~-V-v----
OR
~PUT
(0) BUFFERED-CD400IB
Ib) UNBUFFERED-CD400IUB
Fig. 1 - Example. of the buffered (CD4001 BJ and
unbuffered' (CD4001UBJ 2-input NOR gate.
especially significant for 3- or 4-input gates
where three or ·four PMOS or NMOS transistors are stacked in series at the input. In
this case, the inputs have an effective offset
in threshold and reduced input noise immunity.
Fig. 2 is a schematic representation of the
RCA buffered and unbuffered 2-input NOR
gates. The improved 4-diode-input gate-oxide
protection circuit is shown at the inputs.
JVoo
...
}a:.PUT
....
6Vss
(a) BUFFERED
r-+--....--..,-__ OUTPUT
Vss
Ib) UNBUFFERED
Fig. 2 - Schematic diagl1lms of the buffered and the
unbuffered 2-input NOR gate.
652 ________________________________________________________________
~~
leAN-6SS8
Examples
Examination of the dc performance characteristics of both the buffered and unbuffered
2-input NOR gate reveals the two electrical
characteristics, output impedance and noise
immunity, by which the types are differentiated by the JEDEC standard specifications:
Output Impedance
:2:,Buffered-Fig. 3 depicts the buffered
output stage and shows the MOS transistor as switched on with a channel
resistance R; R is the same value for the
n-switch closed or the p-switch closed.
+v
INPUTS
LOW
-A
~B
+y
A---I,
fR"
A--- .p
INPUTS
LOW
INPUTS
HIGH
R12
_A
_A
LOW
_B
HIGH
_B
B---
p
BJ-,R/2
'---y. 'y'
0~~~T
R/2
r--+-_.-:O:;.UTPUT
-y
........_
A--- n
-y
(0) I INPUT LOW, I INPUT HIGH
....._O..
UTPUT
8--- n
-y
(b) BOTH INPUTS LOW
(e) BOTH INPUTS HIGH
Fig. 4 - Variable output impedance of an unbuffered
2-input NOR gate. The resistors represent the
on impedance of a p- or n~hannel MOS tran-
sistor.
15
TA
a
25°C
~
10
Fig. 3 - Connsnt output impedance of a
buffered gate.
-Unbuffered-Fig. 4 depicts the unbuffered 2-input-gate p- and n-channel MOS
switches and appropriate on-channel
resistances. Note that the two stacked
p-channel switches are designed for an
on resistance of R/2. so that the output
impedance is R when both the logic
inputs are low, Fig. 4(b). In Fig. 4(a)
the. output impedance is R to the
negative supply terminal (usually ground)
for an input logic state of I, input high.
Fig. 4(c) shows the condition when the
unbuffered gate has an output impedance
of R/2 for both logic inputs high. Hence
the variable output impedance of the
unbuffered gate. For a 4-input gate, this
variable is R to R/4! The maximum
output resistance of RCA buffered or
unbuffered gates is R. Thus, minimum
10L and IOH specifications for buffered
and unbuffered gates are identical.
Noise Immunity
The second JEDEC-defined difference between the buffered and unbuffered CMOS
·gates (or inverters) is the difference in input
noise-immunity characteristics.
-Buffered-The buffered 2-input NOR
gate voltage-transfer characteristics Fig
5, are squared because of the gain of
t~ree CMOS stages from input to output.
FIg. 5 shows that noise voltage inputs of
±1.5 V at VDD = 5 V and ±4 V at
VDD = 15 V will have little discernible
5
VIN IBI,
a
V
VINala,
Nal
v
"I'
20
Fig. 5 - Voltage transfer characteristics of a buffered
2-input NOR gate (CD400781.
~ffect ?n the output voltage; i.e., noise
Immumty for all logic states is optimally
high as is noise margin: 1 volt at VDD =
5 V and 2.5 Vat VDD = 15 V.
-Unbuffered·-Fig. 6 shows the rounded
voltage-transfer characteristics of the
2-~nput unbuffered NOR gate. Also
eVIdent is the shift in the transfer curve
for the different logic input states. Compare these curves to those of Fig. 5 and
the effects of the non-buffered inputs
as well as the gain differences are evident.
Th.e ~ounde~ characteristics require a
nOlse-lmmumty specification of ±20%
of VDD at 5, 10 and 15 Vas well as a
reduced noise margin: 0.5 V at VDD =
5 V and 1.0 V at VDD = 15 V.
The above definitions use gate characteristics as illustrative of the JEDEC definitions for buffered and unbuffered characteristics relative to variable output impedance
and noise-immunity performance. Inverters
and high-current drivers may also be defined
as buffered (B) types or unbuffered (UB)
types by virtue of the squared or rounded
transfe~ characteristics of Figs. 3 and 4,
respectively. Even though both types have a
single NMOS and single PMOS output transistor, the rounded transfer characteristic of
the unbuffered inverters makes them UB
types by virtue of:
I. Reduced noise-immunity performance
where the 20% rating is applicable.
2. Varying output impedance as a function of input voltage change along the
rounded portion of the transfer curve.
COMPARISONS
Table I shows the qualitative comparisons
of user-oriented performance characteristics
of buffered and unbuffered CMOS gates,
inverters, or drivers. Table II is a quantitative
comparison of the key performance char'acteristics with explanations as follows:
Propagation. Delay- Delays shown are applicable to RCA 2-, 3-, and 4-input NOR and
NAND gates.
653
leAN-6558
7
I
r'\,
•
5
T."25OC
I
~
-
101-----1--\---+\-1-------11------1
3
VIN-182 VIN 2
vIN'
2
I
'- ~
15
20
(b)
Fig. 6 - Voltage transfer characteristics of an unbuffered
2-input NOR gate (CD4001 UBI with output voltagas
of 5 and 15 volts.
Table I-Comparison of Buffered and
Unbuffered Gate Characteristics
Characteristic
Propagation Oelay
Buffered
Unbuffered
Slow
Fast
Noise
Immunity/Margin Excellent
Good
Output Impedance
and Output Trans~
tion Time
Constant
Variable
ACGain
Low
High
Buffered Gates
Typical Propagation Delay
VOO = 5 V, CL = 50 pF
VOO= IOV
VOO= IS V
Noise Immunity
Noise Margin
Output Oscillatiim for Slow
Inputs
Yes
No
Input Capacitance
Low
High
Noise Immunity-Table III shows the detailed input-voltage data-sheet speCifications
for buffered and unbuffered gates. From
these test conditions the 'user-oriented noiseimmunity and noise-margin data of Table II
are derived. Also refer to Figs. 5 and 6 for
the voltage-transfer characteristics that illustrate the reason for the different input-voltage-specification requirements for buffered
and unbuffered devices.
Output Impedance-Refer to Figs. 3 and 4
and accompanying descriptions of the constant output impedance of buffered gates
and the variable output impedance of unbuffered gates. Note that both buffered and
unbuffered RCA 2-, 3- and 4-input gates are
designed to meet the same maximum output
impedance; output current ratings (IOL and
IOH) have the same minimum limit on RCA
data sheets.
Output Transition Time-The time required
for a CMOS output to transfer high or transfer
low is constant for buffered gates but varies
according to input logic states for unbuffered
gates. Output transition time varies as a
function of the driving source resistance of
654
Table "-Characteristics of Buffered and Unbuffered Gates
ISO ns
65 ns
50 ns
30% of VOO
at 5 and 10 V
27% at 15 V
IV
2V
2.5 V
VOO= 5 V
IOV
IS V
Typical Output Impedance
VOO=SV, VO=±O.4V
2-lnput Gate
3-lnput Gate
4-lnput Gate
Unbuffered Gates
60 ns
30 ns
25 ns
20% ofVOO
at 5,10, and 15 V
0.5 V
1.0 V
1.0 V
400 ohms
400 ohms
400 ohms
200-400 ohms
133-400 ohms
100-400 ohms
Typical Output Transition Time
VOO = 5 V, CL = 50 pF
(2-, 3-, 4-lnput Gates)
100 ns
50-100 ns
ACGain
AC Bandwidth
""68 dB
280kHz
VOO=IOV
VOO=IOV
Output Oscillation For
Slow Inputs
Susceptible
For tptf I ms
Typical Input Capacitance
Average
Peak
the output, which is state dependent as
indicated in Fig. 4, as well as the device
output capacitance, which is dependent on
both device size and input logic state. Because of variable output capacitance, outputtransition-time variations are not a linear
>
1-2 pF
2-4 pF
""23 dB
885 kHz
Not Susceptible
For tptf to 100 ms
2-3 pF
5-10 pF
function of output resistance. As Table II
shows, RCA 2-, 3- and 4-input unbuffered
gates exhibit a net 2-10-1 difference in output
transition time even though the output
resistance has a net 4-to-1 variation for the
4-input gate.
ICAN-6558
Table III-Input-Voltage Specifications
Characteristic
Vo
Limit
Min. Max.
VDD
Units
Input Voltage
Low (VId
4.5
5
1.5
Volts
9
10
3
B 13.5
15
4
UB 4.5
5
I
9
10
2
13.5
2.5
15
Inpht Voltage
High (VIH)
0.5
5
3.5
10
1
7
B 1.5
15
II
UB 0.5
5
4
10
8
I
15
1.5
12.5
Notes:
1. Noise-immunity voltage is the V1L or VIH Specification limit.
2. Noise-margin voltage is computed as follows:
Noise-Margin Voltage
=
AC Gain and Bandwidth-CMOS linear-mode
gain was measured for both the buffered and
unbuffered RCA 2-input NOR gate by means
of the test circuit of Fig. 7. Fig. 8 shows
typical linear-mode gain difference between
buffered and unbuffered RCA 2-input NOR
gates. While absolute performance depends on
device type (inverters; 2-, 3-, 4-input gates)
and test configurations, Fig. 8 defines the
VIL - (VDD-V O)
(VDD-VIH) - Va·
approximately 3-to-1 difference in Iinearmode performance between buffered and
unbuffered gates.
Output Oscillation for Slow Inputs-The high
linear-mode gain of buffered CMOS devices
can lead to undesirable oscillation at outputs
when input ramps are in excess of approximately I millisecond duration. Fig. 9 illus2-3 mY OF NOISE
ON RAMP
INPUT~
dB
METER
tr:.1 ml
(ALSO APPLICABLE TO tf:ll'l mil
I
I
I
I
TRANSITION
BEGINS
OUTPUT~
Fig. 7 - Linear-gain test circuit.
Fig.
68!----_=:,--"""+-..I'
280
VOO=15V
295
FREQUENCY-11Hz
lal TYPICAL CD400IB LINEAR GAIN
Fig.
8 - Typ;callinear-mode gain of buffered and
unbuffered 2-input NOR gate.
9 - Buffered output oscillation for a slow input.
trates this effect when approximately I to 2
millivolts of ac noise within the device bandwidth on the input signal are amplified
through the device and tend to develop a few
cycles of oscillation between the positive and
negative rails under 5-volt operation. In
contrast, unbuffered gates do not tend to
oscillate unless a noise voltage of 200 to 300
millivolts were present within the bandwidth
of the device. An input ramp of up to 100
milliseconds duration did not create oscillation in laboratory tests of RCA unbuffered
gates.
Input Capacitance-Figs. 10 and II show the
dynamic input capacitance of the RCA
buffered and unbuffered 2-input NOR gates,
respectively. The large MOS transistor geometry of the unbuffered. NOR gate is
responsible for the higher peak input capacitance (Miller effect) in the linear switching
range. The longer dwell in this linear region
also tends to broaden the Miller capacitance,
and therefore increases the effective average
input capacitance. Buffered gates and inverters
are rated at a maximum input capacitance of
I unit load (7.5 picofarads-JEDEC standard);
unbuffered gates and inverters are rated at 2
unit loads (15 picofarads maximum). Highcurrent unbuffered drivers, such as the CD4049UB, are rated at 3 unit loads (22.5
picofarads maximum).
Applications Guidance
Table IV summarizes preferred application
areas for both buffered and unbuffered RCA
B-series IC products. This information is based
on the buffered and unbuffered CMOS device
characteristics listed in Table II combined
with the author's experience and familiarity
with the application areas indicated. The
information given is general guidance to allow
the designer to key in on the specific
performance characteristics of either device
type. The data provided in this Note are
derived from RCA standardized Band UB
products whose circuit designs were implemented to match performance between UB
and B gate types as closely as possible. For
example, device sizes were selected to assure
matched output drive. In addition, the process and layout rules followed in Band UB
designs of RCA product are identical, as is
the use of improved gate-oxide protection
circuitry for Band UB product.
RCA Gate, Inverter, and Driver Products
Table V is a current list of SSI (small
scale integrated) Band UB products presently
in production by RCA. Refer to RCA product guides and the Databooks for detailed
product information)
References
I. COS/MOS Digital Integrated Circuits, Product Guide, COS-278E, 1976.
RCA Integrated Circuits, Databook, SSD210,1976.
__________________________________________________________________ 655
ICAN-6558
•
•
0
-
7
TA-25"C
•
•
4
•
~yIA'oY
\,
~l
I
TA-2S-C
VOO-SV
,OV
lOY
'OV
4
,
3
'0
'0
I
2
,
Fig. 10 - Input capacitance of a buffered 2·input
NOR gate (CD4001 B).
1
~ ~\.-
\..
'0
20
Fig. 11 - Input capacitance of an unbuffered 2-;npuf
NOR gate (CD4001 UBI.
Table IV-Applications of Buffered and Unbuffered CMOS Gates and Inverters
Application
Buffered
Preferred
Ultra·Low·Frequency Systems
Inputs 1 ms*
excluding Schmitt Triggers
Gate Applications Requiring
Constant Output Impedance
Such as D/ A R·2R Conversion
Preferred
Preferred
High·Freq., Moderate Gain,
Linear Amplification
Low·Freq .. High Gain,
Linear Amplification
Unbuffered
Preferred
High·Speed Systems
High·Noise Environments,
Low·Speed Systems
Preferred
Preferred
* Applies to gate,s of inverter designs of A~table or Monostable multivibrators
with T
> I millisecond.
Table V-RCA COS/MOS Buffered and
Unbuffered Gate, Inverter, and
Driver Types
Buffered
Unbuffered
CD4000B
CD4001B
CD4002B
CD4010B
CD4011B
CD4012B
CD4023B
CD402SB
CD40S0B
CD4068B
CD4071B
CD4072B
CD4073B
CD407SB
CD4078B
CD4081B
CD4082B
CD4000UB
CD400IUB
CD4002UB
CD4007UB
CD4009UB
CD40IIUB
CD40I2UB
CD4023UB
CD402SUB
CD404IUB
CD4049UB
CD4069UB
656 _________________________________________________________________
ICAN-6563
Radiation Resistance of the COS/MOS
CD4000A and CD4000B Series
by M. N. Vincoff
Complementary MOS (COS/MOS) inte·
grated circuits possess many advantages which
recommend their use in radiation·susceptible
space and military environments. Several of
the most significant of these advantages
are: ultra·low standby·power consumption,
high noise immunity, 1 extremely high pack.
aging density, and inherently high reliability:·3
These advantages, along with the improved
radiation resistance of the 1975 and 1976
RCA CD4000A and CD4000B series over the
previous CD4000 and CD4000A series described in earlier radiation studies,4 exhibif
the maturity reached by the MOS technology
since 1969.
A number of studies of the radiation
resistance of complementary MOS devices
by JPL, NASA, NRL and various companies
in the space industry have revealed two areas
of prime concern. 5 , 6 The first, permanent
radiation exposure, as experienced in a spacesatellite environment, causes a shift in thres·
hold or switching voltage, which could result
in increased leakage current, IL' The second.
transient radiation exposure, as experienced
in an atomic environment, causes the outputvoltage levels to respond to a pulse of
ionizing radiation; this effect could change
the state of the logic circuitry and require
resetting of that circuitry for proper equipment or system operation.
Permanent-Radiation Resistance
The CD4000 series was resistant to permanent radiation levels of 2 x I Q4 rads (approximately 10 12 e/cm 2) in 1971 and 1972.
In 1973, the RCA CD4000A-series devices
without special processing were found to be
resistant to radiation levels up to 2 x 105
rads (approximately 10 13 e/cm 2), as shown
in Fig. 1.4 In this figure the change in
SWitching voltage VS was plotted as a function of dose; the value of VS was calculated
from the average value of VTN and VTP for
the devices mentioned. In 1974 a minor
change was made to the process and the
radiation resistance was reduced to the
1971 - 1972 level. In late 1974 and early
1975 a JPL/NASA contract study resulted
in a second change to the process (gateoxide area); the change achieved a repeated
radiation-resistance level of I x 105 rads
(Si). This level of radiation resistance is
presently provided on Class A parts having a
"z" designation after the part number.
Veo a 10 VOL 15, DOSAGE
~ Co 60 GAMMA
I 1971, 72,14
2. 1973,1975
3 1976 SOME
OEVICE TYPES
SOURCE
I'
C04000 *
CD4000A I
SERIE/
,/
~
I
/
,I
CD4QOOA
i
8'j2
C040008
SERIES 2.
I;/\
2 ........... 2 ....
data in this Note as criteria. Test items to
be considered are radiation environment,
which will vary greatly depending on dosage
rate; time of exposure; amount of normal
shielding; distance of the device from the
radiation source; shielding afforded by the
atmosphere; power-supply voltage selection;
and switching cycles used during exposure.
For example, consider the effects of permanent radiation on two spacecraft in 90-degree
orbits at 600 and 1500 nautical miles from
the earth, respectively. The dose-depth is
determined as shown in the curves of Fig. 2.
/'2&::::::'3-3--3-2)(10 4
2xtO~
10'
10'
10'
10'
RADS(SII
10 10
lOti
t
I
I
10 12
lO"
10'''1
Ie/em!}
·POSITIVE BIAS APPLIED 100% OF THE TIME
92CS-Z2496Rt
Fig. 1 - Permanent radiation resistance of CD400().1
~
e
:: 10 4
:0
C04000A· and C04000B'series devices.
Product with this designation is tested on a
lot-sampling basis using a Gamacell·200
C9·60 radiation source. Latest radiation·
process improvements and resultant production studies indicate that some 1976
product exhibits radiation·resistance levels
up to and beyond I x 106 rads (Si). RCA
expects to have production CD4000A and B
series product available to I x 106 rads (Si)
in 1977.
The new radiation level of the CD4000A
and B series represents a Significant improvement over the previous CD4000A
series. In addition, with minimal shielding
(for example, 1/16-inch of aluminum) the
CD4000A or B series can be used in applications with levels of radiation up to 2 x 106
rads (approximately 10 14 e/cm 2).
Transient-Radiation Resistance
The resistance of the latest CD4000A and
B series (1975 and 1976) to transient
radiation is expected to be better than that
of the past CD4000A series, which should
withstand pulses of radiation in the range of
approximately 109 to 1010 rads/s. 7
Design Considerations
'The resistance of the CD4000A- and
B-series devices to either permanent- or
transient-radiation exposure can be increased
by providing either minimal shielding in the
equipment enclosure containing the devices
or by locating the devices deep within the
equipment. In any case, the action taken
will depend on the constraints dictated by
the radiation environment imposed by the
system or program. Each application must be
tested and the results analyzed with the
______________________________________
~
(a) 600-MllE, 90- ORBIT
(bl
I~OO-MILE,
90- ORBIT
Fig. 2 - Dose-depth curves for trapped electrons
and protons in spacecraft in orbit.
In these curves the dose in rads (AI)/day is
plotted as a function of the thickness of
spacecraft aluminum required to shield the
devices from trapped electrons and protons. 5
Conclusion
The RCA COS/MOS CD4000A and B
series exhibit improved radiation resistance
over the previous CD4000A series, and
operate well in many applications in which
permanent and transient radiation effects
are factors. When stringent radiation requirements are imposed, additional shielding
can be employed to increase the radiation
life of COS/MOS CD4000A- or B-series
devices to any desired level, i.e., to make
their radiation resistance equivalent to that
of bipolar devices. 6, 8
Reference
I. Eaton, ~.S., "Noise Immunity of RCA
COS/MOS Integrated Circuit Logic
Gates", RCA Application Note ICAN6166.
2. . Vincoff, M.N. and Schnable, G.L.,
"COS/MOS is a High-Reliability Technology", RCA Technical Publication
ST·6112.
3.
M.N. Vincoff and G.L. Schnable,
"Reliability of Complementary MOS
Integrated Circuits," IEEE Transitions
on Reliability, R-24, pp 255-259 (Oct.
1975).
_______________________ 657
ICAN-6583
4.
Ezzard, G., "Radiation Effects on
COS/MOS Devices", RCA Application
Note ICAN-6604 (covers CD4000
series).
5.
Device
Brucker, G.J., "COS/MOS
Sensitivity in Outer-Space Radiation
Environment", Report No. X72002,
Oct. 17, 1973, RCA Astro Electronics
Division.
6.
E. M. Reiss, "Radiation-Hardened
CMOS", for presentation at the 1976
Government Microcircuits Application
Conference.
7.
Dennehy, W.J., et aI., "Transient
Radiation Response in ComplementarySymmetry MOS Integrated Circuits",
RCA Technical Publication ST-4308.
8.
9.
Smith, J.M., and Murray, L.A., "Radiation Resistant COS/MOS Devices",
RCA Technical Publication ST-4723.
Poch, W.J., and Holmes-Siedle, A.G.,
"Permanent Radiation Effects in COS/
MOS Integrated Circuits", RCA Technical Publication ST -4174 (covers
CD4000 series).
658
10.
Schambeck, W., "Radiation Resistance
and Typical Applications of RCA COS/
MO"s Circuits in Spacecrafts", Telemetry Journal, June/July 1970 (covers
CD4000 series).
II.
Schambeck, W., "Effects of Ionizing
Radiation on Low-Threshold C-MOS
Integrated Circuits", DFVLR Institute
for Satellite Electronics, Oberpfaffenhofen, W. Germany, April 1972 (covers
CD4000A series).
12.
13
Danchencko, V., "Radiation Damage
in MOS Integrated Circuits, Part I",
Sept. 1971, Goodard Space Flight
Center, Report X-711-71-410 (covers
CD4000A series).
Poch, W.J., and Holmes-Siedle, A.G.,
"The Long-Term Effects of Radiation
on Complementary MOS Logic Net-'works", IEEE Transactions on Nuclear
Science NS-17 (6), Dec. 1970 (covers
CD4000 series).
.
14.
King, E.E., Nelson, G.P., and Hughes,
H.L., "The Effects of Ionizing Radiation on Various COS/MOS Integrated
Circuit Structures", IEEE Transactions
in Nuclear Science, No.6, pp. 264,
Dec. 1972, RCA Technical Publication
ST-6161.
IS
Peel, John L., et aI., "RadiationHardened Complementary MOS Using
Si02 Gate Insulators", IEEE Transactions on Nuclear Science, No.6,
pp. 271, Dec_ 1972.
16
Schlesier, K.M., et aI., "COS/MOS
Hardening Techniques", IEEE Transactions on Nuclear Science, No.6,
pp. 275, Dec_ 1972.
17.
E.M. Reiss and M.N. Vincoff, "Effects
of Variation of Gate Oxide Anneal
Temperature on Radiation Resistance
and· Reliability of CMOS Devices",
presented at the Conference onNuclear and Space Radiation Effects,
Humbolt State College, Arcata, California July 14-17, 1975, Conference
Summary, pp. 349-353 (i975).
ICAN-6564
Applications of CD40107BE
COS/MOS Dual NAND Buffer
by D. J. Blandford and G. l. Gimber
This Note describes the characteristics
of the COS/MOS dual NAND buffer, the
CD401078E, and the wide variety of practi·
cal applications in which this important
addition to the CD4000'series of COS/MOS
devices can be used.
CHARACTERISTICS
Fig. I shows the logic diagram of the
CD401078E, which consists of two 2·input
NAND buffers in an eight·pin plastic pack·
•• 0 - 1 \ . . ,
8.E~c.F
92C5-2U47
Fig. 1 - Logic diagram of the CD401078E
NAND buffer.
age; pin assignments are shown in Fig. 2.
The bar on the output line of the logic
diagram in Fig. I indicates that the output
2
7
00
0
C
3
6
E
"55
4
5
F
PIN I
w
~
~
10
PINZ
10V
PIN I
~...
Each input includes the standard COS/MOS
protection network, a 1.5 kilohm input
resistor and diodes to VDD and VSS' The
output device is a large n·channel transistor.
Typical transistor sink·currellt characteristics
are shown in Fig. 4 in which drain current,
IDN, is plotted against drain-to-source voltage.
VDS. for VGS = 5 V, 10 V and IS V (Le.,
VDD = 5 V. 10 V. and IS V). Note, for example, that for a VDS of I volt and a 10-volt
supply. the NAND buffer is capable of sinking typically 120 milliamperes. Applications
of this large current-sinking capability are
described below.
A pull-up resistor from the output (pins
3 or 5) to VDD enables the device to perform the logical NAND function, as shown
in the truth table, Fig. 3(b). Useable values
·O'V
8
PIH2
14
92C$-28348
Fig. 2 - Pin assignments of the CD401078E.
is open·drain, as shown in Fig. 3, the circuit
diagram and truth table for a single buffer.
DRAIN-lO-SOURCE VOLTAGE IYos)-V
Fig. 4 - Minimum output low (sink) current
characteristics of the CD40107BE.
~ 6;~--+---4-·44·~-~~---1----~--'
g
~
~
o
!IV
4
~_~.IN I
PIN 2
r---
2--
.681012
14
INPUT VOLTAGE 1Vr '-V01.TS
92CS-283SI
Fig. 5 - Transfer characteristics of the
CD40107BE showing sourcebias effect.
PRACTICAL APPLICATIONS
Practical applications of the CD401078
overlap with those of other devices in the
COS/MOS CD4000 series, for example, with
the logical NAND function of the CD40 II
and with the buffer function of the CD4041,
CD4049, and CD4050. However, the applications described in this Note are those for
which, until now, no COS/MOS NAND
buffer has had sufficient drive capability, in·
the hundred milliampere range.
In the first of these applications, Fig. 6,
two NAND buffers are each driving a 2.2watt, 12-volt incandescent lamp. The circuit is arranged as an astable oscillator with
its period of approximately two seconds
determined by the external capacitor and
resistors. In this and other similar applications the load is used as a pull-up from
the open-drain output to a power-supply
voltage greater than zero and equal to or
less than VDD'
,.0 O-""'V'v-~-4
•• E
o-......V'v-+-'
,.,
A
B
o
0
1
c*
,
o ,
1
1
1
0
(bl
*' REQUIRES
RESISTOR
EXTERNAL PULL-UP
TO "00
92C5-28350
Fig. 3 - (al Circuit diagram of the CD401078E,
(b) truth table for 1 of 2 gates.
of pull-up resistance lie between approximately 100 ohms and I megohm. Care should
be taken when choosing 3 pull-up resistor
or any other load not to exceed the maximum power dissipation of the deVice. Designers should refer to the device data sheet
for allowable dissipation limits over the
desired temperature range.
The three stages of gain from input to
output of the CD401078E, Fig. 3(a) result
in a very sharp transfer characteristic, Fig. 5,
near the ideal for a digital logic device.
More complete characteristics are given in
the CD401078 data shee!.!
10M
0,1,...
92(:5-28352
Fig. 6 - A 2.2-watt incandescent lamp-driver
circuit.
659
ICAN-6564
The same type of astable circuit is shown
in Fig. 7, but with a single load device, an
LED with a current limiting resistor of 150
ohms. The NAND buffer, as well as driving
the load, forms part of the astable circuit,
with one of its inputs used as an enable;
when this input is low, the LED is permanently off. The other half of the astable
oscillator utilizes a two-input NOR gate,
the CD400IAE, one input of which is used
as an inhibit. With the timing components
shown, the astable frequency is approximately 4 Hz.
IA
18
Ie
10
28
2A
2D
2C
LED'S HP5082-7904
I
I-
I I _I
4A 4C 8A Be
48 4D 88 80
VDO ·+IOV
CLOCK
IISS -OY
CD401'AE
Fig. 8 - Multiplexed LED circuit
INHIBIT ENABLE OUTPUT
0
I
0
I
OFF
0
0
OFF
I
I
OFF
ON
92CS -28353R I
Fig. 7- LED dri~er circuit
The NAND buffer is typically capable of
sinking 120 milliamperes at a VDS of 1 volt
wi th a IO-volt supply. It therefore meets the
typical requirements for the current-sinking
device at the cathode terminal of a commoncathode LED multiplexed display circuit,
Fig. 8. In this display circuit, data is
presented in the form of four BCD numbers
to be displayed on the four seven-segment
LED's; the clock input determines the multiplexing rate. The two D-type flip flops of the
CD40I3AE or BE are arranged as a two-stage
Johnson counter, the two Q outputs of
which select the da ta transferred by the
CD4052BE multiplexers to the CD451IBE
decoder-driver. The same Q outputs are
decoded by the four NAND buffers and
used to tum on the seven-segment displays
in the correct sequence. For example, when
Ql = I and Q2 = 0, both inputs of the
NAND buffer marked B in Fig. 8 are high,
and the buffer sinks current through the
diodes of the second seven-segment display
digit.
By using the two NAND buffers of a single
eight-pin DIP in parallel, it is possible to
interface directly from a COS/MOS system
to a heavy-duty load typified by. the computer peripheral-printer hammer solenoid of
Fig. 9. This type of solenoid typically requires 250 milliamperes to tum on which,
at a supply voltage, VDD, of 12 volts,
implies a VDS of approximately 0.6 volt.
To prevent excessive current flow through
the electrostatic-protection diodes to VDD
at the outputs of the NAND buffers,
in applications such as the one under discussion, the SWitching of inductive loads, the
protection diodes should be shunted with a
low-dynamic-impedance switching diode, such
as a lN4154.
In many systems where COS/MOS devices
are used for their wide operating-voltage
=cJJvO -r;l"~ =:.:'
['1
CONTROl [.
INPUTS\"
1/2 C0401078£
RELAY. 12
v
92CS-28356
Fig. 10:- Relay driller circuit.
common type of 12-volt relay, a two-pole
change-over type with a coil resistance of
185 ohms. Again, a IN4154 shunt diode
is advisable.
Fig. II shows a reversible 12-volt taperecorder motor driven by two NAND buffers
in a bridge circuit.· Two p-n-p transistors
provide an active pull-up to VDD.
SCR's and triacs typically require tens of
milliamperes of gate current, more than the
current capability of a standard COS/MOS
device o~tput. The NAND buffer, however,
is able to sink sufficient current, and in
22
IN4154
HAMMER
SOLEt.tOID
92CS-2835S
Fig. 9 - Solenoid driver circuit.
range and high noise immunity, and· particularly in industrial control applications, it is
important to be able to drive relays directly.
Fig. 10 shows a NAND buffer driving a
A
B
0
0
0
I
I
0
I
I
I
I
MOTOR FUNCTION
OFF
COUNTER CLOCKWISE
AS PREVIOUS STATE
CLOCKWISE
AS PREVIOUS STATE
92:CS-Z83S7
Fig. , 7 - Motor-controllercircuit.
660 __________________________________________________________________
ICAN-6564
Fig. 12 is seen driving a 2NS756 triac.
Ifisolation is required between the COS/MaS
L
+0
I"\J
v0 - . . - - - - - ,
112 CD40t07BE
v".o---------.....---o
92CS-28358
Fig. 12 - Direct dc drive interface of CD40101BE
with a triac.
and triac systems, the circuit of Fig. 13 is
used. In the figure, the NAND·buffer load
is the primary coil of a pulse transformer
T I, and when 5- to IO-microsecond pulses are
applied at a IOO-Hz repetition rate to the
COS/MaS input, sufficient current flows in
the transformer secondary to keep the triac,
a T2700D, turned on. The NAND-buffer
circuits make it possible for a COS/MaS
system to control several amperes of current
at line voltage.
Line driving is another application requiring large current pulses; Fig. 14 shows
two NAND buffers driving a twisted-pair
transmission line. Clock rates up to 8 MHz
are readily achieved by circuits driving five
meters of a 130-ohm line twisted at two
turns per inch.
One of the most important applications
for the open-drain NAND buffer is the
COS/MaS to TTL interface shown in Fig. 15.
The VDD pin of the CD40107BE is connected to the power supply of the COS/MaS
system, the external pull-up resistor to the
S-volt TTL supply. The values of the pull-up
resistor required and the number of loads
that may be driven are shown in the table
accompanying Fig. 15.
V~D
rl
112CD4D1D7.~
~
VDD'o--?~----------.
TWISTED
PAIR LINE
240 V
VCC
R
5
5
5
5
2.7K
1.2K
'0
50 HE
to
Zo -130
,.
LOADS
STDoT
STT
•
20
27
1'·
eo
,De
Fig. 15 - COS/MaS to TTL interface.
•5
••
OUTPUT
92CS-28359
'-5 TO 10 ,.,
F-,oo Hz
112 CD40107BE
TI- PULSE TRANSFORMER
Fig, 13 -Interface of CD40101BE with triac,
with CDS/MDS component and triac
isolated.
________________
YDO
DATA
INPUT
Fig.
~
= References
~~'~~.~~R ~',:~ =.':.~:m ';.~NGTH I. Preliminary Data Sheet for the CD401 07BE,
Z TURNS PER 'NCH.
COS/MaS Dual 2-Input NAND Buffer/
92C.-mGO
Driver, 1976; or RCA Databook, Series
74 - Line-driver circuit.
SSD-2IO,1976.
________________________________________________ 661
ICAN-6S72
mercury relay is used to switch the RC
source because such relays are fast and
free from arcing or bouncing effects.
Characterization of the various protection
networks is done in 12 diffl'rent combinations of inputs, outputs, and
COS/MOS Electrostatic-Discharge
Protection Networks
by H. L. Pujol
RCA's two families of CMOS
devices, the standard A series (3 to 15
voltsl and the high-voltage B series (3 to
20 volts I, are equipped with networks to
protect the gate oxide of the devices
against damage resulting from discharge
of electrostatic energy between any two
pins.
The gate input of a CMOS device is
equivalent to a small, low-leakage
capacitor (typically 5 picofarads I in
parallel with a very high resistance
(typically 1012 ohmsl. Because of this
extremely high intpedance which lends
itself to the buildup of electrostatic charge,
even a very low energy source (such as a
static charge I is capable of developing
voltages in the order of 80 volts, the
typical breakdown voltage of an MOS gate
oxide. In contrast with other semiconductor devices in which the breakdown
can be tested any number of tintes without
damage, the MOS gate oxide can be
shorted, and the device destroyed, as the
result of only one voltage excursion to the
breakdown lintit.
Protection Networks
Figs. 1 through 4 show the various
protection networks incorporated in all
COS/MOS product.
Standard Protection Networks
Fig. 1 shows the standard protection
network incorporated in all A-series and
some B-series devices. Input-diode D2 is a
22M
r""
560
TO
~DEVICE
01
INo-......\N'~-I
CH-HUMAN BODY CAPACITANCE TO GROUND
Rs- BODY SOURCE RESISTANCE
Fig.5 - Equivalent-bodv discharge network.
DI_ev
D2_5QV
A2ccRI
.. lHESE DIODES ARE INHERENTLY PART OF THE
MANUFACTURING PROCESS.
Fig.2 - Improved protection network.
01
01_ 25V
021'15DY
*THESE DIODES ARE INHERENTLY PART OF THE
MANUFACTURING PROCESS.
.
Fig.3 - Modified protection network.
lGATE
TABLE I - Worst-Case Capability of
Protective Networks
I
Protective Network
Worst·Case
'Capability
Standard
(inc!. C04049, C04050)
I kVto 2kV
OUTIIN
INIOUT
DIODE BREAKDOWN
Improved
01_ 25Y
D211t!50Y
* THESE DIODES ARE INHERENTLY PART OF
polarities. The combinations include all
combinations of any two of the following
pins: input, VDD, VSS, and output.
Evaluation of a protective network
begins with the charging of a 100picofarad capacitor through a 22-megohm
resistor and a mercury relay to the desired
voltage. The capacitor CH of Fig. 5 is
then discharged through the same mercury relay and a 560-ohm resistor into the
pins under test. Results of repetitive tests
are used to determine the worst-case
capability of the protective networks,
Table I.
THE
Transmission Gate
4kV
<800 V
MANUFACTURING PROCESS.
01
f-t-l~+-oOUT
OI_25V
D2 .. 5QV
*YHESE.DIODES ARE INHERENTLY PART OF THE
MANUFACTURING PROCESS.
Fig.1 - Standard protection network.
distributed resistor-diode network that
appears as two diodes to VDD.
Improved Protection Network
Fig. 2 shows the improved protection
network incorporated on all new B-series
devices as well as on all A-series Bconverted types.
662
Fig.4 - Transmission gate with intrinsic diodes
that protect against electrostatic discharge.
Other Protective Networks
Fig. 3 shows the modified protective
network for a CD4049/40SO buffer. The
input diode to VDD is not incorporated so
that the level-shifting function can occur.
Equivalent-Body Discharge Network
The protection networks described in
this Note are evaluated and characterized
by using the equivalent-body discharge
network of Fig. 5. As C is increased, the
amount of static energy dumped into the
CMOS device increases. As R is
decreased, the energy dissipated outside
the device is reduced, thereby increasing
the energy dissipated in the unit. A
Additional protection can be obtained
by adding external series resistors at
device inputs. The value of this resistance
should be approxintately 10 kilohms for
gate inputs and 1 kilohm for transmission
gilte inputs. In addition, zener diodes at
the output pins can clamp the voltage to a
safe level. The zener-voltage should not
exceed the absolute maximum rating of
the part. On-chip protection networks are
not used on transmission gates so that
their low "on" resistance can be maintained. The BOO-volt worst-case capability
shown in Table I is provided by the intrinsic diodes shown in Fig. 4.
The value of the input resistor on all
protection networks, except that used in
ICAN·6572
will exceed + VDD or fall below VSS, the
current through the input diodes should be
limited to 10 milliamperes or less to assure
safe operation)
Because of the presence of the integral protection network, the VDD
power supply must not be turned off while
a signal from a low-impedance pulse
generator is being applied at an input of a
COS/MOS circuit. Should the VDD
supply be turned off under such conditions, the VDD line would be essentially
grounded, and a positive voltage from the
pulse generator would be impressed across
the input diode to VDD' This voltage
could cause permanent damage to the
diode or burn out the VDD metallization.
If it is expected that any input excursion
transmission gates, can vary between 100
ohms and 2.5 kilohms because of circuitdesign differences. This resistance, in
conjunction with the capacitance of the
gate and the associated protective diodes,
integrates and clamps the device voltages
to a safe level. The diagrams of Figs. 6, 7,
and 8 demonstrate that the standard
protection networks prevent higher than
normal voltages from reaching the gate of
the MOS device. In addition, the low RC
time constant assures that circuit speed
remains unchanged in spite of the additional components.
Reference
For additional operating considerations see "Guide to Better
Handling and Operation of CMOS
Integrated Circuits," J. Flood, H. L.
Pujol, RCA Solid State Application
1.
NO,te ICAN-6525.
INPut
PI·I?-:_ _ _-AJ\h_ _ _ _
"\
.,--:-I__...~
1
1
VDO PIN
1
...L.
0,
'T c
I
vOX
:1
BREAK-
UNIT
DOWN t--~-----j
'----------~O GROUND PIN
INPUT
VOXIDE" val" 2S v
MAX
"'OXIDE" v02 FORwARD oS 1 V
MAX
ON CONDUCTION
BREAK·
DOWN
YDO PIN
n.TYPE UNIT
p·TYPE UNIT
INPUT PIN
1
~ J.
1.c
-r
1
1
YPE
ON
+,
0,
' ..._
"'OXIDE" VOl + VOl + p·TYPE UNIT
MAX
ON BREAK·
ON
.-nU,
....
1 _ _.....lL..._.....l
GROUNO PIN
DOWN
" I V. 25 v t 4 v" 30 v
VOXIOE: VOl : , V
p·TYPE UNIT
"'AX
92CS-28998
n-TYPE
Fig.6 - Circuits used to provide protection between input pin
and VDDpin.
ON
92CS-28999
U~IT
Fig.7 - Circuits used to provide protection between
input pin and ground pin.
,------/ V
,-----{ 1"- r-------,
VPEAK
f--------,
VPEAK
+
+
INPUT
PIN
C)--"'VV\i-T-14~~I--=~:=.!~ OUTPUT
ON
P'N
DI
°1
ON
BREAKDOWN
BREAK-
DOWN
Vox IDE = VOXIDE" VO, • VOl
MAX
MAX
BREAK·
DOWN
"·TYPE UNIT p·TYPE
~NrT
~
2S V. 1 V
MAX
ON
MAX
ON
= 26
v
~
BREAKOOWN.
OOWN
1 V + 25 V = 26 V
n·TYPE UNIT p·TYPE UNIT
92CS-28923
Fig.8 - Circuits used to provide protection between input pin and output pin.
_________________________________________________________________ 663
ICAN-6576
Power- Supply Considerations
for COS/MOS Devices
RCA COS/MOS Digital Integrated Circuits operate at
extremely low power dissipation levels. They function
reliably with high noise immunity over a wide operating~
voltage range, The RCA COS/MOS product line includes a
standard Une designed to operate with voltage supplies
from 5 to 15 volts and a low voltage ~A" series line
designed to operate from 3 to 15 volts. These properties
enable system designers to operate RCA COS/MOS
devices from unregulated, poorly-mtered supplies, or from
a wide variety of single- or multiple-cell battery sources.
This Note describes the salient features of COS/MOS
devices which permit operation from' Such a wide range
of power sources and provides the system designer with
the necessary information to pennit him to design the
most economical power source for his COS/MOS system.
This Note is applicable to both COS/MOS product lines
mentioned above.
. : -"
__
I
The operation of the p-type device is analogous to
that of the n-type, except that the carrien are holes, and
the applied voltage required to enhance the channel must
be negative rather than positive. (See Fig. 2b).
The gate electrode for a device of either polarity is
insulated from the body of the device; therefore, current
flows only from source to drain in the channel, never
from the gate into the channel.
DRAIN- TO-SOURCE VOLTS
"O
~
__
Vos
1 '
J
--~
VOS
'
Fig. 2b- Typical p-channel characteristics.
CHARACTERISTICS OF A BASIC COSIMOS
LOGIC INVERTER
Quiescent Device Dissipation.
The basic logic inverter (or gate) formed by use of
only a p- and an n-type device in series is Ihown
n-SUBSTRATE
In an n-type device, the majority carrien are electrons. A positive voltage on the gate is required to
enhance the conducting channel. For all gate voltages less
than a threshold value (V th). the conductivity of the
channel is negligible and the device is said to be cut-off.
For gate voltages greater than Vth, the channel is "enhanced", and current flow in .the channel will occur if a
suitable voltage is applied between the source and drain.
The resultant device characteristics are shown in Fig. 2a.
AMBIENT TEMPERATUftE ITA'.!O-C:
.. 1"00
TYPICAL TEMPERATURE COEfFICIENT
I~
g
I O:IG~·l"i-lrOI-jSOIUIRCIEIVOI.~TSI V~GSI' '}; ~·'!·~ ~!'~!·!~;_; !_/~j
_
~
IS
INPUTS GROUNDEO
'"
10
C040UAO,C0401lAE
C040U Ate, CD4025AO
C0402:3AE, CD40U.uc.
H
t+
__~ CD4012AD,CD401!AE,
-
t'
I
0,1'1'"
1 I
.,.. - J
I
14--,
I
OUTPUT
01: :
!..oo
I
~-~
I
I
I I
___n+-4_J
,-WELL
schematically in Fig. J. When the input lead is grounded
or otherwise connected to 0 volts (Io~ical "0"). the
n~device is cut-off, and the p-device is biased on. As a
result, there is a low-impedance path from the output to
VOD' and an open circuit to ground. The resultant
output,voltage is essentially VOD, or a logiC "J",
Similarly, when the input voltage is a logic ','1", or
VOD. then the n-channel device becomes a low impedance, while the p-channei device becomes an open circuit.
The resultant output becomes essentially zero volts (logic
·'0").
Note that one of the devices is always cut-off at
either logic extreme, and that no current flows into the
insulating gates. As a result, the inverter quiescent power
dissipation is negligible (equal to the product of VDO
times the leakage current).
A cross section of the COS/MOS inverter as it is
formed in an integrated circuit on an n-type substrate is
illustrated in Fig. 1. The sor.rce-drain diffusions and the
powell diffusion form parasitic diodes (in addition to the
desired transistors) at the basic inverter nodes, as shown
in Fig. 4. These parasitic elements are back-biased (across
the power supply) and contribute, in part, to the device
leakage current and thus' to the quiescent power
dissipation.
RCA's product line of COS/MOS devices consists of
circuits of varying complexity (i.e .• from the dual 4--input
logic gate that contain 16 MOS devices, to the more
complex 64-bit static shift registers that contain over
1000 devices). These devices occupy different amounts of
silicon area and are composed of varying numbers of
circuits formed from inverters. Consequently. each device
in the family exhibits a particular magnitude of leakage
current, depending upon the total effect of device count
and parasitic diode area. For example, some logic gates
are specified to operate with a typical power diSSipation
of S nW (Vno = 10V), but 7-stage counters or registers
are specified to operate with a typical power dissipation
of S~W (VDD= 10V). Published data includes both
typical device quiescent-current levels and maximum levels
(VOO = SV and Von = IOV). The maximum values are
rarely encountered in RCA devices.
Device - Switching Ch. .cteristics,
The input/output characteristics for the COS/MOS
inverter are shown in Fig. 5. As mentioned earlier the
signal extremes at the input and output are approximately zero volts (logic "0") and V DD (logic ' ....). The
switching point is shown to be typically 45 to 55% of
ihe magnitude of the power.supply voltage (regardless of
the magnitude of the power-supply voltage) over the
entire range from 3 to 15 volts (or 5 to 15 volts). Note
the negligible change in operating point from -S5CC to +
12SOC.
These excellent switching- characteristics permit COS/
MOS devices to be operated reliably over a wide range of
voltages, a property not found in other logic forms.
AC Dissipation Chlll1lctwistics.
During the transition from a logic '''On to a logic "1",
both devices are momentan1y on. This condition results
in a pulse of instantaneous current being drawn from the
power supply. The magnitude and duration of this
current depends upon the ronowing factors:
(a) the impedance: of the particular devices being used
in the inverter circuit
(b) the magnitude of the power-supply voltage
(c) the magnitude of the individual device threshold
voltages
(d) the input driver rise and fall times
,~
15 FOR IO°-o.3 "I"C
z
<
~.
•
"I~-SUBSTRATE
~.i-03
:
!Vas!
Enhancement-Mode Device Clwacteristics
Fig. 1- Cross'section of COSIMOS uansistor.
~
INPUT
I
Fig. 4- Basic inverter showing parasitic diodes.
REVIEW OF PERTINENT COSIMOS OEVICE
FUNOAMENTALS
The'MOS enhancement transistor is a majority-canier
device (See Fig. 1) in which the current in a conducting .
channel between two diffused electrodes (denoted as the
source and the drain) is controlled (enhanced) by a
voltage applied to a third terminal (the gate). which is
insulated from the source and drain.
J
VDD - -..,.
by H.L. Pujol
J
CD401!AI(
10
IS
DRAIN - TO -SOURCE VOLTS IVoSl
Fig. 2a- Typical n-channel charscfflristlcs.
VDO
i~~r
G1~IT
2.'
I!'-C:
2.5
7.S
10
12.S
15
INPUT VOLTS lVI'
FIg. 5- Typical COS/MOS transfer characteristics as a
Fig. 3- Basic COS/MOS I""."., (schematic).
function of temperature.
664 __________________________________________________________________
ICAN-6576
An additional component of current must also be
drawn from the power supply to charge and discharge the
internal parasitic node capacitances and the load capacitances seen at the output.
The device power dissipation which results from the
above current components is a frequency-dependent parameter. The more orten the circuit switches. the greater is
the resultant power dissipation. The heavier the capacitive
loading, the greater is the resultant power dissipation. The
power dissipation is not duty·cycle dependent. For all
intents and purposes it may be considered frequency
(repetition-rate) dependent.
Because the RCA COS/MaS product line ranges
widely in circuit complexity from device to device. the ac
device dissipations vary Widely from device to device. The
effect of capacitive loading on the individual devices also
varies. Figs. 6a and 6b show a family of curves for a
typical gate device and a typical MSI device. These
curves, from the published data for the individual devices.
illustrate how device power dissipation varies as a
fUnction of frequency. supply volrage and capacitive
loading.
AC Performance Characteristics.
During switching, the node capacitances, within a
given circuit and the load capacitances external to the
circuit, are charged and discharged through the p- or
n-type device conducting channel. As the magnitude of
VDD increases, the impedance of the conducting channel
decreases accordingly. This lower impedance results in a
shorter RC time constant (this non-linear property of
MOS devices can be observed from a close scrutiny of
the characteristic curves in Fig. 2). The result is that the
I
maximum switching frequency of a COS/MOS device increases with increasing supply voltage. (See Fig. 7a).
Fig. 7b shows curves of propagation delay as a function
of supply voltage for a typical gate device. However. the
the trade-off for low supply voltage (i.e., lower output current
to drive a load) is lower speed of operation.
The power dissipated during switching (if the load is
assumed to be capacitive) is equal to:
Co V50f (power is equal to energy per unit time]
where Co is the output and load capacitance. VOO is the
supply voltage. and f is the operating frequency in hertz. A
measure of this power dissipation as function of frequency can
be obtained from the model shown in Figs. 8a and 8b which
assumes step inputs and zero mode capacitance.
The average power for the square-wave input voltage
shown (repetition rate fa = lIto) is calculated as foHows:
to
J . .
For P with
SUPPLY'IOLTSIV
),15
LOAD CAPACITANCE IC L I'15pF
-~r !!I
104
':. K>.::::::;:4
I
105
CI..'50PF-:~
106
101
-r--. H-t--- .......:.........r-+
.-
--:--
~
:::
I, ,
10l
J. Add up aU typical package quiescent power dissipations
(as shown in the RCA COS/MaS published data).
Because quiescent power diSSipation is equal to the
product of quiescent device current times supply voltage, this parameter may also be obtained by adding aU
typical quiescent device currents, and multiplying the
sum by the supply voltage, VOD. Quiescent device
current is shown in the published data for supply voltages of 5 volts and 10 volts only.
In cases where the supply voltage is other than that
shown in the published data, the quiescent device current can be interpolated because this current varies
approximately linearly with voltage.
~ ,o.r-+-\
~
~
10
LOAD CAPACITANCE CCL)'15pF
----CL.5~~
104
10
102
IOl
INPUTCI..OCK FREOuENCY !lCLI-kHZ
Fig. 6- Typical power dissipation characteristics (a) Basic
gate power dissipation characteristics (b) MSI device
power dissipation characteristics.
i!
AM81ENT TEMPERATURE ITA I •
.1...
I.)
~J-ro
;!
~
~
C04021AD, CD402IAM
CD40%IAE
Fig. 8- Model for the evaluation of POWfIt' diaipsrlon
fa) Wavsfonns fb) Circuit.
2. Add up all dynamic power dissipations using
typical curves of dissipation per package as •
function of frequency shown in the published
data. In a fast-switching system, most of the
power dissipation is dynamic, therefore, quiescent
power dissipation may be neglected.
20
10
SUPPLY VOLTS
~
,
t voo I
The example below illustrates how these rules are
used to calculate total system power dissipation.
The system illustrated consists of ten 2-input NOR
gates, eleven inverters, one Ootype flip-flop. and
one 7-stage binary counter. The system operates
with • supply voltage of IOV at a frequency of
100 kHz, and has • load capacitance of 15 pF.
(See Table I)
Table I
dVo
(step inputs only),
AMBIENT TEMPERATURE ITAI .25·C~r ;
~
LOAD CAPACITANCE (CLI-IS pF
'3,'00
~
t
_.
200
t: ~; rW-- trt~:t:t t·
~! i1J~~¥t1n~t+t+t
.+l::Ji
':lI .1:.':..tli:~Jtl~.·!:.:!-~
'tli ':1: .trtt+~~~
t ·
II.
-~
~
J
C004000AD,CD4OO1Ao.CD4002AD
t~~~ ~~:~~::••::~~/D400lAKr
...
• . .- .........
.j.
~
?i
g
r
t PHL.}CD4000AE.C0400IAE
tpUt
C04002AE.cD4024AE ...
o
Thus, for a step input, the averase power dissipated is
directly related to the enOfJY required to change and dlscharge the circuit capacitance to the supply voItap, VOO.1t
should be noted that this power is independent of the dev!co
parameters. Although this equation was derived using an input
voltage with. rise time of zero, it has also been shown to be a
good approximation for circ:uitl where the input voltage rise
and faII times are small with respect to the repetition nte.
'pc
Ib)
4
Jf Ip(t)(VOO-·Voldt
'Nit) ='pCt) =Co Tt
, ['1J
u·c
6 LOAD CAPACITANCE tell- IS pF
~
to
P=..!..P-'N(t)V dt+..!..
to
a
to
a
Calculating System Power
The foregoing material presented fundamental reasons why
COS/MOS devices exhibit extremely low quiescent power.
Also presented were reasons why ac power dissipation increases with operating frequency and why it varies from
device to device.
.
For these reasons certain guidelines have been developed
to assist the deSigner in estimating system power. Total system power is equal to the sum of quiescent power and
dynamic power. Therefore, the two--step approach outlined
below can be used:
'0'
10
IS
20
Types
PQuiesc:ent
IlW
POynamic
....W
Gates
0.03
2
Inverters
0.01
2
O·type F/F
0.05
0.2
Counter
5
0.6
SUPPLY VOLTS (Voo )
P,- = Po + Po = 4.8mW (neg'ecting Pal
Fig. 7- Operating freqUtlncy and propagation delay as a
function of power-supply voltage (a) Maximum
guaranteed operatilJlJ frequency as a function of
power-supply voltage fbi Propagation delay as a
function of power-supply voltage for the basic
ga".
This example assumes that all devices are switching at
the clock-rate (100 kHz). Not alI of the logic circuits will
be switching states at this rate, thus, the total power
diSSipation wID be significantly lower than that stated in
the example.
____________________________________________________________________ 665
ICAN-6576
P-SUpply R.~""don Raquin_b.
The preceding discussion demonstrated that COS/MOS
_ees exhibit reliable switching properties over a wide
range of power....pply voltages. This fact implies that an
unregulated supply may be used with the provision that
(I) maximum voltage limits are not exceeded or
(2) system speed is no greater tban the speed which
This perf......... has been demonstrated in the
laboratory (100 Pis- 10). The amount of ripple on the
power supply is quite hish, yet the _ce function.
prol*ly.
Typicol Suppll.
Th. fonowing _
inIIicate some examples of
adequate IIlpplies for COS/MOS .ystoms.
can be supported by the COS/MOS devic.s operating at
the lowest val.. of the Von expected from the
lated supply.
unregu'
To establish the extent of th.regulation required, the
system designer must rust determine the maximum
operating frequeney required. Usually, the maximum
frequency of the system is limited by the .iIowest
responding devices in a logic chain; By ref.rence. to the
curve of frequeney as a function of· VDD and CL BiVen
in the published data for that deVice, a minimum VDD
wltage (required for proper operatlon)·can be det'1l··
mined. Any value above this VDI> (minimum) will
proYide ooceptable perfOrmance in the system. By selec·
tion of II nominal VDD half way between VDD (mini.
lnuni) and the 15·wlt maxiriJum rating ft.r COS/MOS
devices, the. designer can oslimnte the perCOl'tage regula.
•
tion .required for his system t~ ·perform adequately.
For example, the published data of the RCA
CD4OO4A 7-stege binary counter shows a curve (shown in
Fig. 9) of frequency ai a function of operating volta&e
for that device. For operation of this counter at 5 MHz,
with a loading capacitance of 15pF, the minimum operat·
ing VDD permitted for reliable operation is 10 volt., as
~-r--
~!IO.·
14
~
~
8
.\
6
1
r4!;..
4
...
2
,
0
I
i""""'
I
,
100
\
...
,'J.
1000
FREQUENCV-.Hr
F;g. 1G-Peak-to-peak ripple voltage as
B
1. Selection of Zener Diode and Resistor R
The amount of cunent that must be; maintained
through the diode (IcO is a function of the difference
betw.een,theWorst-caseaventgecu~nt required by the
COS/MOS systems and the current required by the
Zener diode for regulation based on its particular
breakdown characteri~tics.
The diode cunent (Id) and the worst-case average system current (lavg> determine'the value of,the resistor
(R) for a particular Zener regulating voltage.
2. Selection of Capacitance C
Before the proper' capacitance' can be selected the
foll~wing System requirements must be decided upon:
a. Peak charge requirement. This requirement is a functionofthe peak current and its pulse width. It must
be measured for the particular system speed and
load capacitance.
.........
"
The low current demand of the COS/MOS system
permits . an inexpensive but effective Zener diode
.
regulator.
Some of the design considetations are as foBows:
..
'0000
function of
frequency.
h. Permissible VOO minimum: As mentioned in previoussections, this minimum voltage will determine
the maximum operating speed of the COS/MOS
system. _
The size of the capacitor (e) may then be determined
(rom the fonowiog formula:
Q ; Ipt (charge; peak current
x pulse width)
shown on the curve.
Because the maximum VDD is IS volta, a haIf.way
voltege of 12.5 volts should be the nominal value used.
In this case, the maximum percentage regulation is 20%.
If the designer desires a nominal VDD closer to VDD
minimum, then better reBulation is required, (for example
in battery-operated equipment where a standard cell is
available).
D,
DC
HIGH
VOUAGE
SUPPLY
CCS/MOS
SYSTEM
Filtoring Requl_ts
Power....pply mteriDg requirements for cos/Mos
systems are minimal. Two factors account for this
situation: (I) the low quiescent powei dissipation.
involved, and (2) the fact that the peak value of the
ripple does not go below a minimum VDD (which
supports the ·required switclting frequency), so that the
COS/MOS logic performs satisfactorily.
AMBIENT TEMPERATURE ITA) a 25·C
LOAD CAI;t~CITANCE eel I ~ 15 pF
Fig. 12- Circuit for inrerftH:tl of COSMOS syrtem. to
high-vol_ supply.
Fig. 11- Battery standby for COSMOS systems.
This system is advantageous in cases where the dc
supply becomes open Dr short-circuited.
. With a low battery voltage the COS/MOS system will
continue to fUDttioD without interruption. In order to
drive this system the battery voltage and dc supply
voltage should relate as follows:
Vbattery = Vmin. + O.1V. (O.7V
Vmax.
>
Voc supply
>
lIt:I
Vmin.
one diode drop)
+
1.4V
AD. C04004AK C04004AT
..,
"
In the event the supply drops below V~., the
battery will forward bi.. diode D2 to form a closed·
circuit and the COS/MOS system will continue to
function properly through the battery.
20
SUPPLY VOl.TS IVDD l
-
.ZC:S-I7771
Fig. 9- Maximum frequency lIS 8 function of pOWfIr-.
supply voltage for the C04004 and CD4004A
666
High DC Source
For applications (especially in aircraft equipment)
where the supply voltage exoeed. the RCA COS/MOS
maximum rating of VDD' the circuit of Fig. 12 can be
used to reduce the high supply voltage to the normal
COS/MOS voltage range. This configuration uses a Zoner
diode, a resistor R and a capacitor C.
SUMMARY
This Note shows that RCA COS/MOS· devices offer many
advantages in the area of simplified power-supply requirements. The wide operating voltage range (3 to 15 volts or 5 to
IS volts) from a single ~pply, low power dissipation, and
high noise immunity pennit system designen to use less expensive, unregulated. power 'supplies. This wide voltage range
makes COS/MOS logic circuiu ideal for battery-operated
equipment because a better selection' of cells is feasible.
Another advantage is the direct compatibility of COS/MOS
devices with bipolar devices wliich eliminates exPensive and
power-consuming interface circuits. (See Ref. 1.)
COS/MOS transistOR show great pot.ntisl for use in
large array. bocause of the low power dissipation and
effective use of cltip ..... Th. relatively small Brea
consumed by COS/MOS circuits. .. well as the elimina·
tion of area and power-consumirlg nsiston, results in high
circuit.cJensity per unit-silicon......
The performaace features mentioned in this Note, as well
as the reduced co.t. inh.rent in IC technoloay make COS/
MOS circuits extremely attractive in many digital systems.
I. "Interfacing COS/MOS WITH OTHER LOGIC Families".
ICAN6602 by A. Havasy and M. Kutzin.
ICAN-6587
Noise Immunity of COS/MOS 8-Series Integrated Circuits
by T. Chesney
R. Funk
The
excellent
noise-immunity
characteristics of COS/MOS (compleme n ta ry-symmetry Imetal-oxidesemiconductor! digital IC's is a
paramount reason for their preferred and
successful use in high-noise automotive,
process-control, production-monitoring,
and
similar harsh-noise-prone applications. The introduction of the RCA
B-series COS/MOS devices furthers the
well-known noise immunity advantages of
the COS/MOS technology in two important ways:
1.
Improved noise-energy immunity
as a result of balanced lowimpedance output circuitry in all
RCA B-series COS/MaS devices.
2.
Standardized
(EIA-JEDEC
standards I dc noise-immunity and
noise-margin
ratings covering
buffered and unbuffered CMOSlogic types.
Included in this Note are brief
discussions of logic-system noise and
rejection concepts, COS/MOS dc/ac
noise-immunity specifications and
definitions, and dc/ac noise-immunity
performance data for several B-series
COS/MOS gates, inverters, and highcurrent drivers.
Logic-System Noise Concepts
Successful application of any digitallogic IC family requires consideration of
the following:
1.
Externally or internally generated
noise - both radiated and conducted.
2.
The
inherent
noise-immunity
capability of the logic family
selected.
3.
System noise-rejection measures.
Without coordination of these three
points, a system design may perform
unfavorably.
Consider first the various system or
environmental noise generating sources.
External system noise may include the
noise imposed upon a logic system by
electric motors, welders, rf transmitters,
x-ray machines, high-current solenoids or
relays, pulsed lasers, and circuit breakers.
All of the preceding emit EMI (electromagnetic interference), and many
produce power-line or ground-path noise
disturbance. External noise is characterized by randomly occurring highenergy transients that are not easily anticipated. Usually, this noise is coupled
electromagnetically or capacitively to
signal, supply, and ground lines. Internal
logic-system noise is usually generated on
logic-signal lines by capacitively coupled
crosstalk or by logic-switching current
surges on supply lines or ground lines. In
ultra-high-speed logic families such as
ECL, reflection noise resulting from an
impedance mismatch is also an internal
noise problem; but because of relatively
long output transition times of CMOS
devices (more than 10 nanoseconds),
reflection noise can be excluded from
further consideration.
Since botb external and internal noise
must be considered, logic systems must be
designed to survive in a medium to severe
noise environment, a fact that leads to the
second consideration, selection of an IC
logic family having noise-rejection
characteristics appropriate to the application. As is demonstrated below by
considerable data, B-se;ies COS/MOS
devices have good dc and ac and noiseenergy immunity characteristics. No
matter how good the noise-rejection
capability of a logic IC family, such as
COS/MOS, system design measures to
reduce noise entry into logic signal lines,
power supply lines, and the ground are
usually necessary to some extent. The
methods most commonly used to minimize
noise effects in COS/MaS logic systems
zener diode and a capacitor to
ground on each logic card or each
50 to 100 IC's. High-voltage supply
transients can usually be rejected
by this simple measure. Separate
lines should be used for logic
circuits and power switching
circuits.
2.
Ground-Line Noise - In a system
in which many high-current
switching components, such as
motors, relays, and SCR's are
involved, logic grounds should be
separated from high energy
component grounds. The logic
grounds should be returned to a
common point.
3. AC noise on system signal inputs
- 60 Hz is a commonly used
frequency reference. Raw ac power
lines should be isolated using a
transformer or optical coupler.
Zener-diode limiters are also effective. 60- Hz signals can be
shaped by using COS/MOS Schmitt-trigger circuits.
NOISE SPECIFICATIONS
COS/MaS noise immunity is
characterized by de specifications, ac
noise-immunity performance, and noiseenergy immunity performance. Each of
these characteristics is defined below and
supported by performance data.
DC Specifications
Table I shows the industry standardized
(JEDECI noise immunity and noise
margin ratings, VIL and VIH, for Bseries' devices. Note that separate
specifications have been established for B
I buffered I types and UB (unbuffered I
types. 1
are:
1.
Power-source line decoupling Good practice suggests use of a
small-value series resistor and
Two important noise characteristics can
be defined by using the VIL and VIH
ratings:
1.
Noise Immunity - The VIL and
667
ICAN-6587
2.
VIH limits are the device inputsignal noise-immunity ratings
which, as defined in Table II, are
30, 30, and 27 percent, respectively, of the 5, 10, and 15-volt
supply voltages for the B-series
types. Percentages are lower for
unbuffered gates, as shown in
Table II. The VIL and VIH
ratings define the maximum
permissible additive noise voltages
at an input terminal when input
signals are 50 millivolts off the
supply rails.
Noise Margin - The difference
between VIL and Vo or VIH and
Vo is the device noise-margin
voltage for the noninverting case.
Table II designates the Band UB
voltages.
Noise
noise·margin
margin voltage is defined aa that
noise voltage that can be impressed
upon VIN at any (or allliogic 110
terminals without upsetting the
logic or causing any output to
exceed the V0 ratings of Table I.
Of the two COS/MOS dc noise
definitions, immunity and margin, RCA
prefers the noise-immunity specification
as the more practical COS/MOS system
definition because CMOS outputs are
normally 50 millivolts off the rails.
POINT USED FOR
CAL~~~~TION OF ENmin'
tpmirl
COS/MOS ac noise immunity takes
into account both the device switching
threshold (dc noise immunity) and the
noise-pulse width. The latter is affected
primarily by the COS/MOS IC bandwidth, especially output transition times.
Fig. 1 shows the usual COS/MOS noisevoltage amplitude, Vt, as a function of
noise-pulse-width characteristic, tp'
Because noise pulses are narrow compared
with device output transition time, noisevoltage rejection is high. As the pulse
NOISE PULSE WIDTH Ctpl- 'IS
1/9
1.5/13.5
5
10
15
1.5
3
4
0.5/4.5
1/9
1.5113.5
5
10
15
1
2
2.5
5
10
15
3.5
7
11
5
10
15
8
Generic
ae
noise-immunity
immunity curves, such as those in Fig. I,
are applicable to:
Positive noise pulses on signal lines
in the 0 state.
Negative noise pulses on signal lines
in the 1 state.
Positive noise pulses on the ground
terminal.
Negative noise pulses on the positive
supply terminal.
Noise-Energy Immunity
Noise-energy immunity takes into
account the pulse width and the circuit
impedance at the point where the noise is
introduced. Noise-energy immunity, E ,
in nanojoules, is calculated as follows: .
4
12.5
Table II - B·Series Noise Immunity. and Noise Margin
Noise Immunity (%)
B·Series
UB-Series
Fig.
curve.
Curves of this type indicate the frequency
(as defined by noise-pulse characteristics)
at which the user has satisfactory dc noise
performance. The curves are especially
useful in calculating typical noise-energy
performance, a parameter that takes into
account the circuit impedance.
Test Conditions Input
Vo
VDD Voltage
(V)
(V)
(V)
Input High Voltage
VIHmin.
B types
0.5/4.5
1/9
1.5/13.5
UB types
0.5/4.5
1/9
1.5/13.5
VDD
I
AC Noise Immunity
Input Low Voltage
VIL max.
0.5/4.5
B types
UB types
>
€
However, designers familiar with TTL
may prefer to use the noise-margin voltage
for system analysis.
Table I - B·Series DC Noise Immunity and
Noise Margin (TA =25 0 C)
Characteristics
widths approach the IC bandwidth, the
curve flattens out at the device switchingthreshold voltage. AC noise-voltage
Noise·Margin Voltage (V)
B·Series
UB·Series
5
30
20
1
0.5
10
30
20
2
1
15
27
17
2.5
1
where EN is noise-energy immunity in
nanojoules, Vth is the device switchingvoltage threshold for a given noise-pulse
width, lp is the noise-voltage pulse width
in nanoseconds, and RO is the impedance
to ground in ohms at the point of noise
entry. RO is usually the output resistance
of the COS/MOS device.
By using values of V and t~ obtained
from the curve of Fig. I, the noise-energy
immunity curve of Fig. 2 is generated for a
668 _____________________________________________________________
ICAN-6587
given value of RO' A comparison of Figs.
1 and 2 shows that the minimum values of
CD40llUB
input NAND
CD4069UB
CD4049UB
The above list includes the most
commonly used COS/MOS gates, inverters, and buffered devices. The ac
noise-immunity characteristics of the
buffered NOR gate (CD4001BI reflect the
noise-immunity performance of buffered
CMOS products of all descriptions.
~
I
i?~
~ ENm"
~
---
:
L-~t~.m~i'~-----------'
NOISE PULSE WIDTH (tp,-ns
Fig. 2
Generic
immunity curve.
•
10
INPUT vOLTAGE tVIN'-V
noise-energy-
noise-energy immunity occur at an inputnoise pulse width for which the noisevoltage amplitude of Fig. 1 begins to
approach the dc noise-immunity or
threshold voltage of a device. The
minimum noise-energy immunity is the
basis for the calculations and comparisons
involving most IC families.
unbuffered quad 2gate,
hex inverter,
hex inverting buffer.
Fig. 4 CD400lUB voltage transfer
characteristic.
within
the
standard
JEDEC
specifications. The VIL and VIH values
for any typical COS/MOS device indicate
a typical de noise immunity close to 50
percent of the supply voltage, a
paramount advantage of CMOS logic
devices over TTL, ECL, PMOS, and
NMOS logic devices.
SIGNAL-LINE OR EXTERNAL
NOISE IMMUNITY
The following analysis was used to
determine the immunity of a COS/MOS
gate to noise on the input line at both the 0
(\ow-leveU and 1 (high-leveU logic states.
O-State Analysis
The signal-line noise immunity of
COS/MOS gates and inverters was
evaluated by means of the test circuit
shown in Fig. 6. The COS/MOS units
NOISE-IMMUNITY TEST DATA
DC Noise-Immunity Test Data
AC Noise-Immunity Test Data
CMOS dc noise-immunity performance
is obtained by plotting the voltage-transfer
characteristic of a CMOS gate, inverter,
or buffer. Figs. 3 and 4 show the voltagetransfer characteristics of the CD4001B, a
Fig. 5 shows the test circuit used in the
evaluation of the ac noise immunity of Bseries COS/MOS devices. The criterion
used is the triggering of a iypical
CD4013B flip-flop at the clock input. The
"i-----+__----t--------l
Fig. 6 Test circuit used to evaluate
signal-line noise immunity of COS/MOS
gates and inverters.
t
"!O~----_rt--+_---r--
----
p~~~ ~-o,*,,_F.-.J
~
!:;
Vss
J'L
V
g
i·~~--~--+_---r-------
g
Fig. 5 Test circuit used in the
evaluation of B-series COS/MOS devices.
,
10
15
INPUT VOLTAGE (VIN'-V
Fig. 3 CD4001B
characteristic.
voltage
transfer
buffered, quad 2-input NOR gate, and the
CD4001UB, an unbuffered version of the
same gate. Comparison of Figs. 3 and 4
and Table I indicates that the values of
VIL and VIH for these devices are well
circuit of Fig. 5 accounts for typical
CMOS loading factors and generally
reflects the ac noise performance of typical
B-series devices. The device types used in
the evaluation include the following:
CD400lUB
unbuffered quad 2input NOR gate,
CD4001B
buffered quad 2-input
2-input NOR gate,
tested were the CD400lUB, CD4001B,
CD40LlUB,
CD4049UB,
and
CD4069UB. Fig. 7 shows the results
obtained. The test circuit is designed to
measure the voltage required at the input
of the unit under test to trigger a CD4013
flip·flop.
During test, a positive-going noise pulse
i,s introduced into the signal line of the unit
under test. At some voltage level,
depending on the width of the puIse and
the gate thresholds, this pulse causes the
flip-flop to be clocked via the CD4001B
gate. This voltage level defines the permissible input range for a logical O.
________________________________________________________________
~669
ICAN-6587
Careful analysis of the ac noise curves of
Fig. 7(c) (for the CD4049UB) for O-state
si"rnal-Iine noise shows a voltage-pedestal
effect occurring at noise pulse widths
associated with the noise-threshold region
of the units under test. A comparison of
the voltage-transfer curves, of Fig. 8(c)
with the dynamic input capacitance curves
for the CD4049UB, Fig. 9, reveals that
this pedestal effect occurs in the same
region as the peak Miller input
capacitance, where the inverter is in its
maximum linear-gain region. Most 0- and
I-state noise-voltage characteristics curves
in this Note exhibit this pedestal effect to
some degree.
2Dr-------r-------r;;CD;;:;4~DO;;;,.;;-'
TAB 25-C
L-__-.~~---,~----~----~----.....
PULSEWIDTH-I'II
(a) CD4001B, CD4001UB
5
10~!5
INPUT VOLTAGE (VINI- VOLTS
I.
,.,,-t5'"C
C040111.8
"
"II
>
14<
.
(a) CD4001B
'a
I I. \
I
'00
~
Vm-IIV
lOY
zoo
PULSE WIDTH-.
...
TA-25-C
'Y
40 •
...
~ "~-----i-----.-r------'
g
I
>-
--- CD4Oe'UB
R'~--~-----+--~~----t---~
,
~:~"- ....
iii
a•
-
~5
W
INPUT VOLTAGE (VIN) - VOLTS
...
A dc analysis of the transfer characteristics of the components included in the
test setup can also be used to determine
the noise level required to clock the flip
flop. Fig. 8(a) shows that a signal of 4.15
volts is required at the input to the
CD4001B gate to produce an output of 4.5
volts at a supply voltage, VDD, of 10
volts. Fig. 8(b) shows that an input of 5.25
volts is required to trigger the CD4013
flip-flop at a supply voltage, VDD, of 10
volts. All measured values shown in Fig. 8
were obtained from measurements on
gates that have typical thresholdswitching characteristics.
670
~
0
•
10
20
"
Fig. 10 shows the test arrangement used
and Fig. 11 the results obtained from
noise-immunity measurements on the
COS/MOS logic gates and inverters
identified above when the input is high
and a negative-going pulse is superimposed on the signal line.
(b) CD4013B
w
TA = 25°
Results of O-state signal-line
noise-immunity tests.
I
15
(e) CD4049UB, CD4069UB
7
20
I-STATE ANALYSIS
!5
• _\~~--=1~====T=~~r~~~~-
Fig.
40
.if-----r--+I---t--t------
I.-~~~::::t:=~..~
zoo
~
u
I.V
Fig. 9 Dynamic input capacitance
curves for the CD4049UB. T A = 25°C.
==-~l==~f-------+'i5--Y__-;;'._"'Y'--l
PUL.SEWlOTH-ftI
60
10
~
14H------j------j- -CD404S11J8 ---1------1
~
IDV
INPUT VOLTAGE (VIN)-Y
~
i
"DOeSV
0
~
W)r-------.-------TCC..
D~~I3••__,
(b) CD4011 UB
>
.
~IO0
cl
•• _1""I • ' - t--
··
CD4049UB
120
"
10
CD4049UB
TA-2!5·C
'\
'\
PEAK MILLER INPUT
CAPACITANCE REGION
WHERE PEDESTAL
11]: ••
•
EFFECT OCCURS.
4.ISV
V
1/
'- ~
•
10
INPUT VOl.TAGE IYIN)- VOLTS
(e) CD4049UB
"
TA = 25°C.
Fig. 8 Transfer characteristics of
components used in the circuit of Fig. 6.
Fig. 10 Test circuit used to measure
noise immunity of COS/MOS logic gates
and inverters when the input is high and a
negative-going pulse is superimposed on
the signal line •
ICAN-6587
for simulating contact resistance and lead
length is used in the VDD line of the unit
under test. Without this resistance the test
unit will not react to the noise pulse.
GROUND-NOISE IMMUNITY
'00
PULSE WIOTH-ni
EQUIVALENT RESISTANCE,
REaU (ohms)
(.) CD4001B. CD4001UB
MINIMUM PULSE WIDTH*
(nanosecondsl
100
53.4
33
25
47.5
51.1
50
55.5
*VARIATION THE RESULT OF WAVE SHAPING
",--,---"C;;;D.;;;.';;;;LU"".,-----.,----~
"f-t-I_-+ __-I-TAOZ50C
--I---
\
"C+--t----t-----t----
zoo
I---
Fig. 12 Test circuit used to measure
the ability of test units to withstand a
negative-going noise pulse on the supply
line without a change in state.
Noise on the power line may be effectively reduced or eliminated by the use
of decoupling capacitors; however.
ground-line noise cannot be reduced so
easily and. therefore. is more objectionable. Fig. 14 shows the test circuit
used to measure the ground-line noise
immunity of COS/MOS gates and inverters; Fig. 15 shows curves of the results
obtained. Again. the units under test
would not react to the noise unless a 25ohm resistor or small inductor simulating
lead length or contact resistance were
placed to ground.
;'00
PULSEWIDTH-na
---=--~-=-t---iOv-
(b) CD4011UB
200
---~8:gn~'
:SOD
PULSEWIDTH-",
TA"25"C
I
(.) CD4001B. CD4001UB
C040llUB
_4-__-P~~.~H~.C~~--- __
>.2:,
-~t_-.---
--------t---.
r\"",
; 8
\
~. ---"-\
(c) CD4049UB. CD4069UB
--- ..-
--~~
t----I---- -
It should be noted that two power
supplies are used in the arrangement of
Fig. 12. An equivalent resistor or inductor
O.'~F
PULSE
.-rLGENERATOR
Fig. 14 Circuit used to
ground-line noise immunity.
measure
CROSSTALK NOISE IMMUNITY
PUL$£WLDTH-n
The test configuration shown in Fig. 12
measures the ability of test units to
withstand a negative-going noise pulse
superimposed on the supply line without a
change in state; Fig. 13 shows results of
tests. A pulse of sufficient amplitude
causes the output of the gate to decrease so
that. at some point. the CD40l3B flip-flop
is triggered from the rising voltage at the
output of the driving inverter stage.
r
~-
--
00.
Results of I-state signal-line
noise-immunity test.
P()WER-SUPPL Y NOISE IMMUNITY
ALL UNUSED INPUTS
TO VSS
I'r--'-.t====l==·~
-f---=-=r=~
'fA = 25°C.
Fig. 11
f
OR
2S11 500
,H
(b) CD4011UB
14
H
~~-
f--------l-.. -
---
CI)4049IJB
C04069UB
TA"ZS"C
--+---1
-+-.--1----- - - -
A test circuit used to evaluate crosstalk
is shown in Fig. 16. A noise pulse from a
pulse generator is coupled to the sIgnal
line of the gate or inverter through a
capacitor. The noise voltage necessary to
trigger the flip-flop is then measured for
different values of capacitance under high
and low input conditions. Fig. 17 shows
the effect of capacitance on the inputs of
the units under test.
2---r------f------f----~-----
zoo
300
PULSE WIDTH-ft$
(c) CD4049UB. CD4069UB
TA = 25°C.
Fig. 13
Power-line noise immunity;
The circuit shown in Fig. 18 more
closely approximates crosstalk caused by
adjacent signal lines. The response of the
test circuit to a noise pulse may be explained by analysis of the response of a
high-pass RC circuit to a ramp input of Vi
= ex t. where ex is the coefficient of
___________________________________________________________ 671
ICAN-6587
CD400IUB
---C04ooI8
1---+----+-----I-T..."25"C ; -
CD400fU8
j--+-+-r-r---t ___ ~~~B
t---
'p-SO-60 ..
,,'I---i-+--I----+---j--+----1
t
tl4
\\'
----
\1 r----
Lof--------"
PULSE WIDTH-II'
,L--"..
~-.200~-~>DO~-~400~-~
...
~~~
lal CD4001B, CD4001UB
~
T..."25"C
~
,
>
.,
.
CD40llU8
12
'L---,200~--.40~O--~OOO~-~~-~1000
COUPLING CAPACITANCE-
COUPLING CAPACITANCE-p'
C0400lUB
___ C04ooI8
"
·
_\\
.. "
· ----
VoD"15V
fp·30-B ..
I
p'
C0401lU'
VOO"'S'"
,,-10-15. r--
0
~
20
II ',,-'"
,
\
IS
'ov
200
PUlSE WIOTH - n
'00
\~
'0
5V
2
'00
\.:
It
VDO "15V
0'-..
0
tt
IS
\
\
"
--.....
••
Ibl CD4011UB
p'
000
CD4DIIUB
VOD"S ...
"........ r---
CD40llUB
VDO"IOV
".25-30l1li
r--
10
·•
12i-r--I-----j----t---+---j
IIO~
EaJl
i. ' :-400
600
COUPLING CAPACITANCE-pF
leI CD4049UB, CD4069UB
10
Fig. 15
Ground-line noise-immunity
measurements.
,.
>81
'v
•
...
=m~l\l\
I
Ip-SO"eo ..
j
~
a
~~
•
•
~V'L
100
100
>GO
400
000
000
COUPUlllc:Al'AeITANCI:-pF
Fig. 17
-
400
000
COOPLINI CAPACITANC£- "
200
)Vll.
'0
\\~,
a
•
--
"- r--
.A v, •
..
~
0
_-
t'~IO.~':vRI-
·· \""" ---
ALL UNUSED INPUTS
TO GROUND
....
--:~
\
\~
20
'laD-lOY
I,-IS-IO ..
\\.
• 1\1
• \ \\"
'0
f--
v'L
000
>DO
COUPUNG CAPACITANCE-pf
.0
.. ~
Voo-sv
v,.
-----
a
II
Fig. 16 Circuit for measuriug noise
voltage as a function of coupling
capacitance.
1"-
0
>DO
_CD404wa
___ C04019UI
I•• ~""
I "•
\['...
•
_ _ lOY
PULSE WIDTM -~.
..
\
\\
0
200
200
DOO
,
80.
400
000
COUPl.IN' CAPACITANCE -
200
aoo
200
400
600
COUPLING CAPACITANCE-,F
-
a
V'L
0
- v,.v"-
10
400
v,
a
...
AV~
-= !"E
-:::
~
100
COUPliNG CAPACITAHC£- p"
...
1000
Effect of coupling capacitance Ion the inputs
of the units under test ITA
25°C).
=
672 _______________________________________________________________
ICAN-6587
coupling and t -is rise time, 10 to 90 percent. The output voltage Vo may be
expressed by the following equation:
VO=llc--
tV>---
P~I__
I V/cm
==
=
I
Ir,"tf" IOnt
f= I MHz
,
r.
~
,
I!
EQUIV. OF 6 FEET OF
18.9 pF/ft..
- [i-e -t/2 Zo
II
Zin) C]
ONE WIRE
!56.1 pF/60 In
11.2 pFlfl. .
(3)
The results of this analysis may be applied
to the various crosstalk waveforms obtained_
vlN-la
o STATES
92CS- 29369
ROUND CABLE
ALL WIRES
94.7 pF/60 in.
VOO"IO V
Fig. 20 Circuit simulating a roundcable system.
!I!: :=
I
4V/cm
In Fig. 21, a sense line is placed between two adjacent driving lines (No. 22
gauge) of a 6-foot-long ribbon cable with a
capacitance of 16 picofarads per foot
(determined by measurement).
=
,.
I
I
,
II.::
,
Voo =15 V
tr=lf=IOns
f= IMHz
VIN"16
o STATES
I
I
I
!
IV/em
--
Fig. 22
system.
~
!'.ai!
I
Ie)
92CS-29368
Crosstalk in the round-cable
NOISE-ENERGY -IMMUNITY
PERFORMANCE DATA
Fig. 18 Circuit closely approximating
conditions for crosstalk on adjacent signal
lines.
z.
GATE
UNDER
TEST
~PUNG
T;oEF[ICIENT
lin
GATE
UNDER
TEST
V,N
Fig. 19 Equivalent circuit used in
crosstalk analysis of test configuration
shown in Fig. 18.
Crosstalk measurements that simulate
actual operation are made by use of the
test circuits shown in Figs. 20 and 21. The
"
muJ~'c...'mOF
10pF/l2l".
11'.''1'/111.
Fig. 21
Circuit simulating a ribboncable system.
The results of crosstalk are shown in the
photographs of Figs. 22 and 23 for round
cable and ribbon cable, respectively. The
crosstalk was insufficient to trigger the
CD4013B under all conditions of the
circuits of Figs. 20 and 21.
Table III shows computed values of
noise-energy immunity for the gate, inverter, and buffer types identified above.
Noise pulse width, t p ' and noise threshold
voltage, VT, data were obtained directly
from the I and 0 signal-input ac noiseimmunity test curves presented earlier in
this Note, Figs. 7 and II. Values of Ro are
typical output impedances for the
CD4001B driving gate used in obtaining
the curves. Fig. 24 is a plot of high- and
low-input state noise-energy immunity for'
the CD4001B gate as a function of input
pulse width. These curves show that noiseenergy immunity is high for noise bandwidths that exceed the speed capability of
the device, and a minimum of approximately 1.3 nanojoules where the
noise-pulse width (50 to 100 nanosecondsl
approximates the device output transition
time. Noise-threshold energy increases
steadily with greater pulse widths.
_______________________________________________________________ 673
ICAN-6587
Table I II - Typical Values:of Noise·Energy Immunity.
SUPPLY
VOLTAGE
TYPE
VDDIV)
NOISE
TYPICAL
NOISE
PULSE WIDTH THRESHOLD SIGNAL LINE
VOLTAGE
IMPEDANCE
VtIV )
RO lohms)
tp Ins)
LOW HIGH
CD4001UB
CD4001B
CD4011UB
CD4049UB
CD4049UB
TYPICAL
NOISE·ENERGY
IMMUNITY'
LOGIC STATE
LOW
HIGH
ENLlnJ) ENHlnJ)
LOW HIGH
ROL ROH
5
100
100
2.75
2.65
700
700
LOB
1.00
10
60
40
6.3
5.1
270
270
8.82
3.B5
15
40
40
9.0
7.0
190
190
17.05
10.32
5
10
160
80
150
40
2.58
6.2
2.85
5.6
700
270
700
270
1.52
11.40
1.74
4.65
12.Bl
15
40
40
9.6
7.B
190
190
19.40
5
100
140
3.0
2.67
700
700
1.29
1.43
10
40
80
5.0
5.45
270
270
3.70
B.80
15
60
40
6.9
9.1
190
190
15.03
17.43
5
60
120
2.0
2.9
700
700
0.343
1.44
·
··
·
~•
·
10
40
40
3.7
6.7
270
270
2.03
6.65
a
15
60
40
4.9
10.4
190
190
7.5B
22.77
5
150
150
2.75
2.60
700
700
1.62
1.45
10
60
6.4
5.2
270
270
9.10
6.01
15
40
60
60
8.7
8.0
190
190
15.94
20.21
Voo'" 5 V
f'-'f"'IOns
2V/em
I VIc
I
VIN"'
o
STATE
(ol
Voo.'OV
1100=10 V
t,a'f'" IOns
4V/cm
'r·tt-IOns
fw'MHz
4V/cm
flO IMHz
VIN'"
"'IN'"
D STATE
I STATE
IV/em
2V/cm
(el
92CS- 29366
::;:1,0
4V/cm
41//cm
4'
~' 11111
II
~
ffi •
=,
1111
i
Il·iii
:1 ,1
I
tr=tf=IOns
VDD"IS V
f= IMHz
VIN'"
I STATE
• 111
Iii
V OO ·1511
tr.'t-IOns
f·' MHz:
4V/cm
VIN"
o STATE
II
(.l
4v/cm • • • • •
(fl
Fig. 23
92CS- 29365
Crosstalk in the ribbon-cable system.
low-level ac noise-immunity for the
CONCLUSIONS
CD4049UB buffer is slightly lower
The noise·immunity test 'data
because of the lower effective input
demonstrates the high noise immunity of
threshold of the large NMOS transistor
COS/MOS dfgital integrated circuits.
used.
Typical ac noise· voltage immunity for an
or paramount interest is the good noiseunbuffered gate is 2 volts for a 5·volt
energy performance of approximately 1.3
supply, 5 volts for a 10-volt supply, and 7
nanojoules for B-series gates, which is
volts for a 15·volt supply. As expected, the
674
"'oooSV
r.. ·25"C
f--
VIN"LOW
V
l...----'"
,,\
V
I
f·'
I V fem
C040018
7
fr·tt·IOns
MHz
t= IMHz
VIN'"
I STATE
PULSE WItlTH It p) -III
I 00
--
----
V
200
PULSE WIOTH (tpl -
IN -HIGH
---
I---
lIOO
'"
Fig. 24, High- and low-input state
noise-energy immunity for the CD400IB
gate as a function of input pulse width.
TA.= 25°C.
comparable to the performance of bipolar
TTL gates at 5 volts despite their much
higher outJlut drive current. At operation
above 5 volts, the -noise-energy immunity
of COS/MOS devices ranges up to 20
nanojoules at 15 volts, far exceeding the
noise-energy immunity of TTL. This
improved noise immunity makes CMOS
logic devices far more economical to use in
high·noise automotive and industrial
control environments than TTL devices.
This noise-rejection capability exceeds
eveu that of bipolar high-threshold logic,
which has only approximately 5
nanojoules of noise-energy rejection in the
high logic-input state.
The good inherent noise immunity
provided by COS/MOS devices leads to
design economy, and complements the
accompanying benefits of COS/MOS:
low-cost, medium- to high-speed
operation, wide operating voltage range,
good temperature stability, wide selection
of SSI, MSI, and LSI device types, etc.
References
1.
"Understanding Buffered and
Unbuffered CMOS Characteristics,"
R.E. Funk, RCA Solid State
Application Note ICAN-6558.
2. "Noise Immunity of COS/MOS
Integrated Circuits," S.S. Eaton,
RCA Solid State Application Note
ICAN-6176. Discusses noise immunity of A-series devices.
3. "Designing Logic Circuits for High
Noise Immunity," Verell Boaen,
IEEE Spectrum, Jan. 1973.
4. JEDEC Standard for B-series
COS/MOS devices.
ICAN-6595
Interfacing Analog and Digital
Displays with CMOS Integrated Circuits
by J. E. Gillberg
Many forms of displays are available for
interfacing digital and analog information
from electronic circuits with the individual
end user. The display choice generally
takes into consideration not only technical
feasibility but also visual impact and often
aesthetic appeal. Until recently, the
analog display, primarily motors Iboth
synchronous and stepped with gears,
hands, or drums, has been the most widely
used. At present, however, new
developments are making the digital
display the more dominant method.
This Note describes some of the
COS/MOS integrated circuits most
suitable for interfacing the electronic
circuit and the display. In the case of
digital displays, it describes basic display
operation to help simplify the equipment
designer's task in selecting both the most
appropriate display and the most suitable
interfacing device.
Analog Display Drivers
Analog displays are usually driven from
either a synchronous motor or a stepper
motor. The synchronous motor receives an
incoming signal at a frequency of approximately 60 Hz and continuously
rotates at that frequency. The stepper
motor receives an incoming signal at about
0.5 to 2 Hz and rotates only during the
active pulse interval. The stepper motor
gives the effect of a non-continuous
movement of the motor or wheel.
One of the major users of digital circuits
with analog displays is the timekeeping
market. This market has continued to use
analog displays because of the many basic
advantages of the familiar clock or watch
face with moving hands. These advantages include low cost, high reliability,
simplified electronics, familiarity of
display mode, and low current drain.
A number of IC's are available for
interfacing the electronic clock circuitry
and the analog display. An excellent
example is the CD4045, a COS/MOS 21Stage Counter. As shown in Fig. I, this
device can be used in timing applications
not only to generate the crystal oscillator
output, but also, because of its output
current capability, to directly drive a
stepper motor. Fig. 2 gives curves
illustrating the current capabilities of the
CD4045.
One method of reducing the current
drain of a stepper motor is to terminate the
XTAL
~
2.097152 MHz
RF " 20 Mn TYP
CIN " 15 pF TYP
COUT " 30 pF TYP
fOUT " I HI:
---"-----"--
OUT~
92CS-29923
Fig. 1 - CD4045, COSI MOS 21-stage counter,
used to generate crystal oscillator output and to
drive stepper motor.
DRAIN TO SOURCE VClLTAGE IVosI-vI
I
DRAIN-lO-SOURCE VOLTAGE
tVcsl-v
Fig. 2 - Typical output n·channel and pchannel drain characteristics of the CD4045.
incoming pulse at the precise moment the
armature achieves enough momentum to
rotate to the next position without any
additional current. The Low-Voltage
COS/MOS Analog Timepiece Circuit
CD220l0E has the capability of detecting,
as shown in Fig. 3, when no additional
current is required by the motor. It
operates as follows. At the beginning of
the output pulse because the load is inductive no current will immediately flow
IV = L dildtl and the voltage at the
output will be at ground, as shown in Fig.
4 at to' After time, the current will begin
to flow into the pull-down n-channel
transistor of the CD220l0E. This current
Voo
Voo
ttEOTT~cRT
,---L-~/
MOTOR
r-t-"f------'
CD22010E
-=- Vss
92CS-29918
Fig. 3 - CD220lOE, a low-voltage COSIMOS
analog timepiece circuit. used to detect status
of stepper motor current.
U
'0
'I
I
I
I
'2
'
13
,
I
,
I
I
I
.... _-:
I
,
92CS-29922
Fig. 4 • Nominal output pulse of .tepper
motor.
flow raises the output voltage until the
motor begins to rotate and cause a back
electro-motive force thereby reducing the
voltage at the output. Once the motor has
achieved enough momentum to move on
its own inertia, however, any added
current again raises the output voltage.
The time interval from to to t3 in Fig. 4 is
the nominal output pulse. Time 1J indicates the end of an internal activation
period after which any rising edge on the
output will trigger internal circuitry to
terminate the pulse width, thus saving
battery current.
The battery-operated wall clock is one
of the major areas for analog displays
primarily because of the low-voltage 0.5
to 3.0 V typical) and low-current 160 A
typical) operation. A number of display
interface circuits are available for this
application. The most suitable depends
upon the type motor and the voltage being
used. Several of these circuits are
illustrated in Fig. 5. In Fig. 5Ic), the
capacitor CD increases the maximum
pulse or spike current supplied to the
675
ICAN-6595
'oJ
C022QI3E
IbJ
CD22010E
,
= 168 rnA
orIl
> 168/(3 rnA
=
Once VDD is established, a given VDS
can be taken from Fig. lib for current I I.
Therefore, R} = (VDS - 0.71/1}
kilohms
--.-
DIGIT
COMMON ANODE
!
7- SEGMENT DRIVER
I
DIGIT
-Veo
COM MON CATHODE
rL°RIVE
~
92CS-29916
Fig. 8 - Common cathode and common anode
light-emitting diode configurations.
677
ICAN-6595
C04011
,-----t---r--O STROBE
OUTPUT
ENABLE
MOST SIGNIFICANT
LEAST SIGNIFICANT
~)DlGIT
~
SEOUENCE
92C5-29914
CLOCK
Jl.I1.I1..J"1.
Fig. /0 - Use of CD4017. a counter/divider
having ten decoded outputs. to provide the
multiplexing digit signal.
SEVEN-SEGMENT
OUTPUT
,zeS-Z991'
optical filter in front of the LED. This
Fig. 9 - Interfacing of four-digit multiplexed
filter increases the contrast ratio of the
LED display and makes it easier to read in
LED di3play system with a four-digit inany ambient light.
formation storage device.
VOUT
voltage out of the CD4511B
AMBIENT TEMPERATUREfTA )-25-C
from Fig. 13 at the VDD being
used in the system
=
.,
C04017
VD
= voltage across LED segment for
I-oI-,--'V'I'v-----L
VCE
(a)
required brightness
= voltage across digit driver
transistor
92C5-29913
o
0.5
I
SUPPLY VOLTAGE -QUTPUTDRtVE VOLTAGE (VDO-VOH1-V
92C$-2?01l
In this example
GATE-TO-SOURCE VOLTAGE (YGS)-I&V
+
R2 =
'OV
5V
5
10
15
DRAIN-TO-SOURCE VOLTAGE (Vos)-V
(b)
Fig. 11 - Typical digit driving circuit and
m'nlmum output n-channel drain charactemtic used for calculating value' of resi3tor
RI.
Fig. 12 shows the segment and digit
drive. Resistor R~ is necessary to avoid
current "hogging' in the LED segments.
The value of R2 is calculated from the
curves in Fig. 13 showing output current
as a function of output voltage for the
CD4511B and from the infonnation
supplied wi'th the LED.
Let IS
678
= peak current in segment
VDD - (VOUT VD
24mA
+ VCEI
kilohms
If the value chosen for R 2 is too low.
uneven segment lighting can occur.
Resistor R2. therefore. should be as large
as possible.
One major drawback to the use of LED
displays is that the contrast ratio of the
display is very low in bright light. The
easiest means of correction is to place an
Voo
92CS-29912
Fig. 12 - Segment and digit drive circuit for
LED.
Fig. 13 - Typical voltage drop (VDD to outputl
vs. output source current as a function of
supply for the CD4S11.
Gas-Discharge Displays
Gas-discharge or cold-cathode displays
are available in both seven-segment and
one-of-ten decoded displays. The one-often decoded displays operate by energizing
one of a series of stacked cathodes each in
the shape of the numeral to be displayed.
This stacked arrangement causes some
viewing problems because the different
numbers appear to move in or out within
the display. A CD4028 BCD-to-decimal
decoder could be used for the one-of-tendecoding necessary for this type of device.
The seven-segment decoded gas-discharge
displays operate in a very similar manner
to the seven-segment LED displays
mentioned earlier.
One disadvantage of gas-discharge
displays is the high potential needed to
activate the display. Typically, a voltage
between 80 and 200 volts is necessary to
cause ionization of the enclosed gas. Once
ICAN-6595
r.±
RANSISTOR
SWITCH
~V:L
(-- --\ /-- --,
'--t-)
I, 1 )
\. ;-'-DRIVER
\
DRIVER
RI
lTR.NSISTOR
SWITCH
=
GAS OISCHARGE
OISPLAY
SERifS
SHUNT
92CS-29919
Fig. 14 - Basic series and shunt circuits for
multiplexing gao-discharge displays.
ionization takes place, the cathode glows a
dull red or orange-like color. In
multiplexing these devices, care must be
taken to make sure that segments
en~r~ed for one digit a.re completely
delODlzed before the next digit is activated.
. For m.ultiplexing gas-discharge
dIsplays, eIther the shunt or the series
method can be used. See Fig. 14. The
series method has the advantage of lower·
power dissipation, but it requires that the
switching transistor have higher voltage
and lower leakage than the shunt method
requires. Fig. 15 illustrates the
multiplexing Iif a one-oI-ten gas-discharge
display. Because of diode D I, the
oscillator using the CD4011 produces a
non-symmetrical output having an off
period long enough to assure that all
characters are deionized.
Fluorescent Displays
to 25 volts from anode to cathode is
typically used to accelerate electrons
emitted from the cathode. When the
cathode is activated, the current flow is
approximately 0.5 to 2 milliamperes
depending upon the type of display.
. The potentials of the anode, grid, and
fIlament are crucial in the operation of the
fluorescent display. The potential of the
filament in the fluorescent display must be
directly related to both the grid and anode
voltages because the filament is acting
both as a heater and as the cathode of the
display. The potential at which the
electrons are emitted from the cathode or
filament, therefore, is critical in determining whether or not those electrons are
accelerated toward the phosphor-coated
anode.
Advantages of fluorescent display
systems include low power, low cost, ease
?f multiplexing, and ease of interfacing to
mtegrated circuits. A disadvantage is that
they are more fragile than many other
forms of display because they reqoire an
evacuated envelope.
A typical circuit for driving a
fluorescent display is given in Fig. 16. The
display segments are connected to the
anodes of the display device and can be
driven directly from any COS/MOS HighVoltage B-Series Integrated Circuit at
about 20 volts. In many instances,
however, the control logic for the information being displayed is operating at a
voltage lower than the 20-volt display
supply. In these cases, the CD40109B
Quad Low-to-High Voltage Level Shifter
can be used to interface the device.
In a multiplexed system, the grid or
cathode of the fluorescent display device
operates in a manner equivalent to the
digit drive on LED devices. A typical grid
voltage value necessary to activate the
display is 10 volts. If a system is operating
below 10 volts, it may be necessary to shift
the voltage levels of both the segment and
the digit information.
The fluorescent display, like the LED,
is a seven-segment device. Its operation is
similar to that of a vacuum tube. The
major difference is that the anode of the
display has a phosphorescent coating
which when struck by an electron beam
emits blue-green light. Because this light
is of a very wide spectrum, it can be
filtered with little loss of display
brightness. A positive potential of ab~~:}~oL T.Gt-+---.....'W\r-
In an unmultiplexed system, the grid
voltage should always be enabled to allow
the display of the seven-segment information. An example of such a system is
given in Fig. 17. Because the grid voltage
is constant and not at the control of the
system, the only possible level shifting
necessary would be for the segment
display.
Unlike the LED display, the fluorescent
display quite often needs the level-shifting
capability of a transistor-inductor flyback
circuit to achieve the high potentials
necessary for operation. Fig. 18 gives
three typical up-converter circuits. The
circuit of Fig. 18(a 1 is pulsed by V IN thus
causing a current flow through L. This
change in current causes an increase in the
voltage across the inductor (VL = L·
di/dtl. The amount of current (ipeak
VDD/R21 is inversely proportional to the
value of R2. With R2 adjustable in value,
the output voltage can be increased by
lowering the value of R2 or decreased by
raising its value. Capacitor C2 filters the
voltage spikes caused by the input
frequency, and diode Dl keeps the
capacitor charged while the voltage spike
from L dil dt is low.
Fig. 18(bl differs from Fig. 18(alin that
it has a seM-contained RCL oscillator and
obtains its voltage increase by transformer
action. T~e oscillator formed by R o ' C,
and L drIves the n-p-n bipolar devices
forcing an ac signal across the transformer
input windings. Because the turns ratio of
the transformer from output to input is
greater than one, there is an increase in
output voltage. The transformer gives a
more precise increase in voltage than the
circuit in Fig. 18(al provides. Capacitor C
and diodes D and DZ clamp the voltage
VOUr to the ~reakdown voltage of DZ
and fIlter and ISOlate C from discharging
during the period of low output voltage
from the transformer.
=
Fig. 18(d is similar to Fig. l8(b 1 in the
transformer action, but its input is similar
FILAMENT
10M>
l
MULTIPLEXED
BCD
INPUTS
2 Mn
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I
,
I
INFO:~~TrON ElO'02. l~uB(SIT--;::;;;;:;;::;;t.~~~7=====J===~--'
10-BIT BUS
10-BIT BUS
92eS-Z99.'
I
I
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--n..
--1l....
--..J'"L
DIGIT
DRIVE
Fig. 15 - Series-type rrwltiplexing of a one-often gas-discharge display.
ZD-VOLT GRID OR CATHODE DRIVE
9ZCS-Z9910
16 - Typical circuit for driving
a fluorescent digital display.
___________________________________________________________ 679
ICAN-6595
C04013
BCD INPUTS
,
Voo "5 V
,,·n
n
i
i~-~ 1
RIO
1'0
;'70mA
V
FILAMENT
92eM- 29909
Fig. 17 - Example of unmultiplexed system for
driving a fluorescent display.
to that of Fig. 18(a) in that it is driven by
an external input.
Circuits similar to those in Fig. 18 can
be used to level-shift voltages for the gas-
discharge type of display discussed
previously. It is necessary, however, that
the transformer, capacitors, transistors,
and other components be rated to
withstand the 200-volt signals which may
be necessary to operate the gas-discharge
display and be capable of meeting the
higher power requirements.
CI
Your
TYPICAL
VALUES FOR
GUIDANCE
ONLY
(al
l
01
F~~ :~~~ ::" H,
01
Incandescent Displays
C2=O.02 p..F
RI =20kn
R2=O-1 kn
U = 3.4 mH
01 '" 2N2901 OR EQU1V.
or = IN914 OR EQUIV.
92CS~29908
Pulsed., single-transistorinductor flyback circuit.
~
'0
,~
I
y~f\
VSUPPLY
-VOUT
-
LII i
-
C
+
'--
C
92CS-2.990~
Fig. 19 - Circuit for interfacing a multiplexed
incandescent-type digital display.
,oz
~
(b I Transformer-type circuit with
ReL oscillator providing drive.
(c) Trans/ormer-type circuit
external drive.
DND
92CS-29907
9:i;h
9906
Fig. 18 - Typical up-converter circuits for
fluorescent digital displays.
One other display which has had wide
acceptance is the incandescent display. Its
low cost, high brightness, and ready
availability have lead to considerable use
of this display. Its disadvantages are its
high power dissipation and the high
amount of heat it generates. Typical
power requirements are 1.5 to 5 volts at 8
to 24 milliamperes.
Incandescent displays are available in
many sizes and colors. Multiplexing of the
digits is easily accomplished by pulsing
each segment for a given time period. The
wattage for an incandescent lamp at the
stated brightness remains constant
regardless of duty cycle or waveform
shape provided that the multiplexing rate
is faster than the thermal time constant of
the filament. When incandescent displays
are multiplexed, an increase in the forCing
voltage by an amount equal to the square
root of the number of multiplexed displays
will maintain the same brightness on each
display that it would have in a static
condition.
With incandescent displays, it is
recommended that diodes be used in series
with each segment to prevent erroneous
display indication through stray electrical
paths. Fig. 19 illustrates the interfacing of
a multiplexed incandescent display. In
this circuit, the CD4013 dual "D"-type
flip-flop combines with the CD4069
oscillator to generate the four pulse in-
tervals needed to multiplex four digits.
For a typical incandescent display
requiring 4.5 volts, the voltage necessary
for the four-digit display is 4 x 4.5 = 9
volts. The CD40107 dual NAND buffer/driver and the p-n-p transistor 40537
assure that sufficient current is generated
at this voltage. With a typical filament
segment current of 50 milliamperes, the
current sourced from transistor 40537 is 50
x 7 or 350 milliamperes. The minimum
beta of the 40537 is 20. Its base current,
therefore, is given by
IB1 = 350/20 = 17.5mA.
At VDD of 12 volts and lOUT of 17.5
mA, VOUT from the CD40107B is 0.11
volt. Then,
R1
= (11.3 - 0.11)/17.5 =
640 ohms.
For 50 milliamperes in each segment
of40
anda~
IB2 = 50/40 = 1.25mA
At VDD of 12 volts and lOUT of 1.25
mA, VOUT from the CD451lB is 11.4
volts. Then,
R2 = (l1.4 - 0.7)/1.25 = 8.56 kilohms.
These calculations depend upon the
current gain of each bipolar device and the
voltage necessary on the incandescent
display. As mentioned previously, the
diodes in series with each display segment
minimize the possibility of stray leakage
currents. Use of the blanking input of the
CD4511 assures that if the oscillator were
to cease to function for any reason, the
indexed digit and segments would not be
destroyed by the static voltage and current
applied to the display.
680 _________________________________________________________
leAN-6883
Simplified Design of Astable RC Oscillators
Using the CD4060B or Two CMOS Inverters
D. Rodman
Astable DeSign Approach
The most basic AC oscillator circuit Is
that shown In Ag. 1. The time period T for
one cycle of this oscillator Is given by the
equatlon: 1
T= -AC
rL
VOO-VTA
VTAJ
n
VOO
+In VOO
(1)
where:
R,
""'-~"--OUTPUT
nCS-32504
Fig. 2· An improved osclll.tor circuit made
by adding resistor Rs to the circuit of
Fig. 1.
Compensation for 50-Percent Duty Cycle
A true square-wave pulse Is obtained
only when the transfer voltage occurs at
the 50·percent point. If the transfer
voltage is at either 33 or 67 percent, the
duty cycle will not be 50 percent. The duty
cycle can be controlled, however, If part
of the resistance of the RC time constant
is shunted out with a diode, as shown In
Fig. 4.
.
c,;
The time period T for the circuit in Fig. 2
Is:1
T= _
VOO = supply voltage
VTA = transfer voltage
AxCx~n
L
By letting VTA = 0.5 VOO, equation 1 can
be simplified to:
T = - AC (In 0.5 + In 0.5)
T = 1.39AC
c,
R,
Application Notes are available that
deal with theoretical approaches to
OSCillator design; this Note stresses practical aspects of design and provides easyto-use algebraic equations that permit
values of A and C for a given oscillator frequency to be quickly determined.
VTA
VOO+VTR
J
VOO-VTA
+In---2 VOO - VTR
~_""-OUTPUT
(3)
92C5-32501
(2)
The problem with this circuit is that
transfer voltage can vary from 33 to 67
percent of VOO. Therefore, the maximum
variation In the time period, T, can be as
high as 9 percent, with a ± 33 percent
variation in transfer voltage from unit to
unit.
OUTPUT
Fig. 1 - The most basic RC oscillator circuit.
An Improvement to this basic circuit
can be made by adding reSistor As, as
shown In Fig. 2. The resistor makes the
frequency Independent of supply-voltage
variations and reduces the tlme'period
variations to less than 5 percent with
variations In transfer voltage.
As should be-10 times the value of Ax. If
As is made less than 10 Ax, the variation
in period T increases to about 10 percent
as the value of As epproaches zero.1 If As
Is made too large, a time constant and
phase shift Is produced by Rs and stray
wiring and breadboard capacitance. This
shift creates a switching delay In the circuit which changes the time period.
If VTR = 0.5 VOO, equation 3 can be
simplified to:
T
Fig. 4· Method of contrOlling the duty cycle
of the RC oscillator.
- RxCx (In % + In %)
T = 2.2 RxCx
(4)
Equation 4 will only be true in the
C04060B for values of R greater than 50
kllohms and for values of C greater than
1000 picofarads. At values of C less than
1000 picofarads, stray capecltance will
have a much greater effect on the entire
system.
It Is advised that a buffer circuit, Fig. 3,
be added to the Circuit of Fig. 2to prevent
the Jitter that would otherwise be Introduced Into the circuit by noise picked
up by connecting cables and by stray
wiring and breadboard capacitance. The
buffer circuit is not needed with the
C04060B since It has an Internal buffer
and Is Internally connected to a counter.
Because adjustment of this diode
shunt to obtain a specific pulse factor
causes the frequency of the circuit to
stray, a frequency control, R1, Is added.
This circuit Is not needed when using the
C04060B since It Is used In conjunction
with a counter. A 50-percent duty cycle
will be derived from the divider/counter
outputs.
References and Bibliography
1. "Astable and Monostable Oscillators
Using RCA COS/MaS Olgltal Integrated Circuits," RCA Solid State
Application Note ICAN-6466.
2. "COS/MaS 14-Stage Alpple-Carry
Binary CounterlOlvlder and
OSCillator," ACA Solid State Oata
Bulletin File Number 1120.
ex
R,
R,
OUTPUT
9ZCS-
32~05
Fig. 3· A buffer circuit used to Improve the
performance of the circuit of Fig. 2.
681
Abstracts of Other Application Notes
ICAN-6080 . . . . . . . . . . . . . . . 6 pages
Digital·ta-Analog Conversion Using the RCA·
CD-4007A COS/MaS IC
The use of the RCA-CD4007A COS/MaS
dual complementary pair plus inverter as a
digital-ta-analog (D/ A) switch is demonstrated.
The op-amp output stage for the digital-toanalog converter (DAC) uses COS/MaS and
bipolar transistor-array IC's. Resistance networks
for DAC's, the design of a voltage-follower
amplifier for single supply operation, and a
9-bit COS/MaS DAC are described.
ICAN-6166 . . . . . . . . . . . . . . . 16 pages
COS/MaS MSI Counter and Register Design
and Applications
.
. Logic and schematic diagrams for counter
and register types CD4006A, CD4014A,
CD40ISA, CD4018A, CD4020A, CD4021A,
CD4022A, and CD4024A are presented; circuit designs are outlined and device-design
trade-ofrs are discussed. Performance criteria
are summarized and applications by type are
outlined by means of logic or subsystems diagrams and waveforms photographs.
ICAN-6176 . . . . . . . . . . . , . . . . 8 pages
Noise Immunity of COS/MaS Integrated·Circuit
Logic Gates
The types of noise usually ,encountered in a
logic system are discussed and the noise immunity of a COS/MaS integrated-circuit logic·
gate test circuit in relation to system variables
is .evaluated. The evaluation is performed on a
circuH that includes a CD4000A dual 3-input
gate plus inverter and a CD4001A quad 2·input
gate connected in cascade to drive a CD4013A
flip-flop. Measurement of the voltage required
at various gate leads to switch the flip-flop
defines the noise immunity t!>reshold of the
gate circuits.
.
ICAN-6210 . . . . . . . . . . . . . . . 11 pages
A Typical Data·Gathering and Processing System Using CD4000A·Series COS/MaS Parts
This Note is developed in terms of a typical
system for process controls. The flexibility of
system design and common data-bus architecture made possible by the three-state outputs
and bidirectional input/outputs incorporated in
many COS/MaS circuits are stressed, as is the
~ase 01 system design for data handling in
mcrements of 4 bits made possible by the
CD4000A family. The implementation of the
system is shown in terms of the COS/MaS standard parts tha t can be used to perform the
desired system functions. Attention is focused
on the multiplicity of applications and the
scope of information processing that can be
covered by standard parts.
ICAN·6289 . . . . , . . . . . . . . . , 12 pages
A COS/MaS PCM Telemetry and Remote Data
Aci:lu isition Design
Descriptive background material on telemetry systems is given along with systems for
both immediate and remote data conversion
682
and transmission. Parts from the CD4000 family
are used to show how various sections of the
system may be realized, in the general case. The
exact configuration of any specific system will,
of course, depend on the unique requirements
of the application.
ICAN-6362 . . . . . . . . . . . . . . . 10 pages
Using the C04520B to Design 0 ividers with
Symmetrical Outputs
The general-purpose COS/MaS dual upcounter, the CD4520B, a counter that may lie
used in various counting and dividing app'lications is di.scussed. Dividers of the form N=2i' ± I
and N=21 ± I and described. Applications of
symmetrical dividers are also discussed.
ICAN-6374 . . . . . . . . . . . . . . . 8 pages
The COS/MaS CD4059A Programmable Divide·
by~N
Counter in. FM and Citizens-Sand-Trans-
ceiver Tuners
The frequency synthesis, capability of the
CD4059A programmable divide-by-N counter
is demonstrated in applications in an FM
digital tuner and in the digital tuner for a
citizens-band tranceiver., The digital approach
described in the paper allows desired frequeneles· to be selected by depressing numbered
buttons on a keyboard. By using the apprapriate basic circuitry along with a phase-Iockedloop circuit, the local oscillator of the receiver
is adjusted and locked to the proper frequency,
thus assuring proper station selection, Alternate
methods of station selection that enhance the
flexibility of the system are described.
ICAN-6498 . . . . . . . , . . . . . . . 6 pages
Design of Fixed and Programmable Counters
Using the RCA CD4018A COS/MaS Presettable
Divide·by·N Counter
The use of the CD4018A single-decade and
multidecade fixed and programmable divide-byN counters are described. System considerations
such as switch simplifications, components
minimization. and speed are also discussed.
ICAN-6600 . . . . . . . . . . . . . . . 6 pages
Arithmetic Arrays Using Standard COS/MaS
Building Blocks
The design of a COS/MaS arithmetic unit
capable of adding, subtracting, multiplying, and
dividing is described. The device is also able
to perform the logical functions of OR, AND
and the Exclusive OR of two 4-bit words. Three
4-bit registers are provided that permit either of
two words to perform a desired operation with
a third word. The system is confignred with
standard, commercially available COS/MaS
devices, which include registers, AND-OR select
gates, a full adder, and NOR and NAND gates.
ICAN-6601 . . . . . . . . . . . . . . . ~2 pages
Transmission and Multiplexing of Analog or
Digital Signals Utilizing the CD4016A Quad
Bilateral Switch'
The CD4016A quad bilateral switch is the
ideal semiconductor switch for use in switching
applications; it can be used for the transmission
of analog or digital signals with low distortion.
The Note discusses features of the device; operation of the COS/MaS switch; switch and logic
applications, including switch and logic functions; multiplexing/de multiplexing; digital control of signal gain, frequency, and impedance,
including resistor networks, and variable frequency can trol; digital-ta-analog conversion, including weighted resistor networks for the D/ A
converter, and all R-2R resistor ladder D/ A
converter; sample-and-hold applications; and
squelch control (level detection).
ICAN-6602 . . . . . . . . . . . . . . . 12 pages
Interfacing COS/MaS with Other Logic Families
The RCA CD4000A COS/MaS series circuits
operate from power-supplies of 3 to IS volts.
Thus, they can drive and be driven by a number of logic families, including all DTL and TTL
families, within certain conditions and limitations. This Note describes the conditions of
interface.
ICAN-6716 . . . . . . . . . . . . . . . IS pages
Low·Power Digital Frequency Synthesizers Utilizing COs/MaS IC's
A d.igital frequency synthesizer that employs
a digital phase-locked loop and other COS/MaS
circuits is described. Following a reveiw of
phase-locked-loop fundamentals, the use of
COS/MaS devices in FM receiver systhesizers
is discussed.
ICAN-6 73 3 . . . . . . . . . . . . , . . 16 pages
Battery·Powered Digital-Display Clock/Timer
and 'Metering Applications Utilizing the RCA
CD4026A and CD4033A Decode Counters 7 Segment Output Types
This. Note·· describes the CD4033A and
CD4026A and their use with various 7-segment
display units presently available. Interface
packages and methods are discussed to help the
the designer select the best system to meet his
demands. Also 'induded are battery-operated
systems for digital clocks and watches.
ICAN-6739 . . . . . . . . . . . . . . . 12 pages
COSIMOS Rate Multipliers - Versatile Circuits
for Synthesizing Digital Functions
COS/MaS rate multipliers, the CD4527B
and CD4089B, can be used as building blocks
to generate a· range of digital functions in
low-power systems where minimum package
count is desirable. The circuits may be employed in numerical control, instrumentation,
digital filtering, and frequency synthesis. When
used' with an up/down counter and control
logic, they can be used to perform such operations as multiplication, addition, subtraction,
generation· of algebraic equations and differential equations, integration, and to raise numbers to various powers. Symmetric rate multiplication, the problem of eliminating round-off
error in a directfrequency-synthesis application
in a common-carrier multiplex system is also
covered,
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R. A. E. Industrial Electronic.,
Ltd
3455 Gardner Court, Burnaby,
B.C. V5G 4J7
Tel: (604) 291-8866
Chile
Raylex Ing. Ind. Ltda.
Av Providencia 1244, 3Er Piso
"D", Casilla 13373, Santiago
Colombia
Mapp
Carrera 13 NRO 19~6
Apartado Aereo 15957, Bogota
Electronica Modema
Carrera 9A, NRO 19-52
Apartado Aereo 5361, Bogota
Jose E Marulanda Montoya
Carrera 10, NRO 15-39 Of. 701
Apartado Aereo 3697, Bogota
Costa Rica
AlmexS.A.
48, rue de l'Aubepine,
F - 92160 - Antony
Tel: (01) 666 2112
Greece
Semlcon Co
31, Vassileos Georgiou B'Street
Athens 516
Tel: 734.353
Guatemala
Electronica Guatemalteca
13 Calle 5-59, Zona I
Guatemala City - MAIL
ADDRESS: P.O. Box 514
Guatemala City, Guatemala
Tele-Equlpos, S.A.
lOA Calle 5-40, Zona I
Guatemala City - MAIL
ADDRESS: Apartado Postal
1798, Guatemala City,
Guatemala
Haiti
Societe Haitienne
D'Automobiles, S.A.
Post Office Box 428, PortAu-Prince
Holland
Inelco Nederland BV
Turfstekerstraat 63,
N - 1431 GD Aalsmeer
Tel: (02977) 2 88 55
Electroimpex, S.A.
Avenida 10, Calles 10 Y 12
San Jose
VekanoBV
Postbus 6115,
N - 5600 HC Eindhoven
Tel: (40) 81 09 75
Gallito Tecnico, S.A.
Av. 2 Calles 4 Y 6, San Jose
J. G. VaUdeperas, S.A.
Calle I, Avenidas 1-3, San Jose
Radio Parts, S.A.
2A. C. O. No. 319 Postalla
Dalia, San Salvador - MAIL
ADDRESS: P.O. Box 1262
San Salvador, EI Salvador
Telercas OY
P.O. Box 2,
SF - 01511 Vantaa 51
Tel: 90/821.655
Radio Equipements Antares
S.A.
9, rue Ernest Cognacq,
F - 9230 I - Levallois Perret
Tel: (01) 758 11 11
Tekelec Alrtronic S.A.
Cite des Bruyeres,
Rue Carle Vernet,
F - 92310 - Sevres
Tel: (01) 534.75.35
L. A. Varah, Ltd
2077 Alberta Street, Vancouver,
B.C. V5Y 1C4
Tel: (604) 873-3211
Teleradio Eletronica Ltda.
Rua Vergueiro, 3134 CEP04102 Sao Paulol SP
Tel: (011) 544-1245
V.A.M. Importacoes, Vendas E
Representacoes Ltda.
Rua Correa Dutra, 1264'
Andar, CEP-20.000 Rio de
Janeirol RJ .
Tel: (021) 225-5182
Dominican
Republic
Hamilton Avnet (Canada) Ltd
2670 Sabourin Street, St.
Laurent, Quebec H4S 1M2
Tel: (514) 331-0443
OrglU1izacao Distrlbuidora E
Representacoes Ltda.
Rua Vigario Tenorio, 105-Conj.
102/402, CEP-50.ooo
RecifelPE
Tel: (081) 224-2229
Saturno Brasilelro Importacao
Exportacao Ltda.
Rua Sacadura Cabral, 120, Sala
509, CEP-20.ooo Rio de
Janeiro/RJ
Tel: (021) 2434744
Cesco Electronics, Ltd.
24 Martin Ross Avenue
Downsview, Ontario M3J 2K9
Tel: (416) 661~220
Hamilton Avnet (Canada) Ltd
6291-19 Dorman Road
Mississauga, Ontario UV I H2
Tel: (416) 677-7432
Comereial Radio Lux Ltda.
Av. Alberto Bins, 533, CEP90.000 Portoalegrel RS
Tel: (051) 221..(i055
Panamericana Comerc:ial
Importadora Ltd••
Rua Aurora, 263, CEN11209
Sao Paulol SP
Tel: (011) 222-3211
Tage Olsen A/S
Ballerup Byvej 222, P.O. Box
225, DK - 2750 Ballerup
Tel: 02/65 81 11
Hamilton Avnet (Canada) Ltd
i735 Courtwood Cresent
Ottawa, Ontario K2C 3J9
Tel: (613) 226-1700
Bacher Elektronische Gerate
GmbH
Rotenmiihlgasse 26,
il20 Vienna
Tel: 0222/83 56 46~
Bahamas
Denmark
Electro Sonic, Inc.
1100 Gordon Baker Road
Willowdale, Ontario M2H 3B3
Tel: (416) 494-1666
Amtron Tyree
176 Botany Street, Waterloo,
N.S.W.2017
Austria
Cesco Electronics, Ltd.
4050 Jean Talon Street, West
Montreal, Quebec H4P IWI
Tel: (514) 735-5511
Honduras
Francisco J. Yones
3A Avenida S.O. 5, San Pedro
Sula, Honduras, Central
America
RCA Authorized Distributors
Hong Kong
Gibb Livingston & Co., Ltd.
Leigbton Centre, 77 Leighton
Road, P.O. Box 55
Iceland
Georg Amundason
P.O. Box 698,
Reykjavik
Tel: 81180
India
Italy
Photophone (Comel)
179/5 Second Cross
Bangalore 560-003
Eledra 3S SpA
Viale Elvezia 18,
1-20154 Milano
Tel: (02) 349751
Panama
Peru
Arven S.A.
PSJ Adan Mejia 103, OF. 33
Lima II
PhiHpplnes
Philippines Electronic
Industries, Inc.
P.O. Box 498, 3rd Floor, RCA
Global Bldg, 8755 Paseo De
Roxas, Makati Commercial
Center, Makatim Metro Manila
3110
Jermyn Distribution
Vestry Industrial Estate
Sevenoaks, Kent
Tel: Sevenoaks (0732) 50144
Silverstar Ltd.
Via dei Gracchi 20,
I - 20146 Milano
Tel: (02) 4996
Puerto Rico
Kelvinator Sales of Puerto
Rico, Inc.
P.O. Box BG, Rio Piedras,
Puerto Rico 00928
Singapore
Edward Eu & Co., Ltd
I Orchard Road, Singapore 9,
Republic of Singapore
Korea
Panwest Company, Ltd.
Room 312, Sam Duk Building
131, Da-Dong, Chung-Ku
Seoul, Republic of Korea
c.p.a. Box 3358
South Africa
Spain
Electronica Remberg. S.A.
deC.V.
Republica del Salvador No.
30-102, Mexico City I, D.F.
Mantenimiento E Instalaciones
InternacionaJes, S.A.
Calle 15 No. 79, Col. San Pedro
de Los Pinos, Mexico 18, D.F.
Mexicana de Bulbos, S.A.
Michoacan No. 30, Mexico II,
D.F.
Surinam
New Zealand
Amalgamated Wireless
(Australasia) N .Z. Ltd.
P.O. Box 50-248, Porirua
Nicaragua
Electronica Centroamericana,
S.A.
P.O. Box 3103, Managua
Comereial F. A. Mendieta, S.A.
Apartado Postal No. 1956
Paseo Tiscapa, Contiguo
Donde Estuvo, Embajada
Americana, Managua
Radio Centro
Reparto Serrano, Managua MAIL ADDRESS: P.O. Box
31, Managua, Nicaragua
Norway
Nadonal Elektro A/S
Ulvenveien 75, Okern Oslo 5
Tel: 02/22 19 00
Allied Electric (PTY) Ltd.
Components Division, P.O.
Box 6090, Dunswart 1508
Tel: (011) 892-1001
VSI Electronic (U.K.) Ltd.
Roydonbury Industrial Park
Horsecroft Road, Harlow
Essex CM19 5BY
Tel: (0279) 29666
(0279) 32947
U.S.
Alabama
Hamilton A vnet Electronics
4692 Commercial Drive, NW
Huntsville, AL 35805
Tel: (205) 837-7210
Arizona
Hamilton Avnet Electronics
505 South Madison Drive
Tempe, AZ 85281
Tel: (602) 894-9600
Electries Comercial Colominas
S.A.
Division Novolectric
Valencie 109-111
Barcelona II
Tel: (03) 253.20.07
Kirfalani's Ltd.
17- 7 Maagdenstreet, P.O. Box
251, Paramaribo
Surinam Electronics
Keizerstreet 206, ParamariboMAIL ADDRESS: P.O. Box
412, Paramaribo, Surinam
Ray tel, S.A.
Sullivan 47 Y 49, Mexico 4,
D.F.
EI Louvre, S.A.
Post Office Box 138, Curacao
Semicomps Northern Ltd.
East Bowmont Street, Kelso,
Roxburghshire, Scotland
Tel: Kelso (05732) 2366
Kierulff Electronics, Inc.
4134 East Wood Street
Phoenix, AZ 85040
Tel: (602) 2434101
Sisteco S.A.
Corcega 167,
Barcelona 36
Tel: (03) 321.73.47/92
(03) 322.42.05/52
Partes Electronicas, S.A.
Republica del Salvador 30-1
Mexico City
Netherland
Andlles
Macro Marketing Ltd.
396 Bath Road, Slough, Berks
Tel: Burnham (06286) 4422
Telectra Sari
Rua Rodrigo da Fonseca, 103
Lisbon I
Tel: 68.60.72-75
Portugal
Okura & Company Ltd.
3~ Ginza Nichome Chuo-Ku
Tokyo 104
Crellon Electronics Ltd.
380 Bath Road, Slough,
Berks, SLI 6JE
Tel: Burnham (06286) 4434
I.T.T. Electronic Services
Edinburgh Way, Harlow
Essex, CM20 2DE
Tel: Harlow (0279) 26777
LASI Elettronica SpA
Viale Lombardia 6, •
I - 20092 Cinisello Balsamo (MI)
Tel: (02) 61.20.441-5
Japan
U.K.
Tropelco, S.A.
Via Espana 20-18, Panama 7MAIL ADDRESS: P.O. Box
8465, Panama 7, Rep. of
Panama
IDAC Elettronica SpA
Via Turazza 32,
I - 35100 Pad ova
Tel: (049) 66.02.22
Mexico
Sistelcom, S.A.
Ave. Mexico y Ave. Ecuador
Edificio Albertina No.3
PanamaS
Sweden
Switzerland
Taiwan
Thailand
Turkey
Ferner Electronics AB
Snormakarvagen 35,
P.O. Box 125,
16126 BrommaStockholm
Tel: 08/80 25 40
Lagercrantz Elektronlk AB
Kanalvagen 5,
P.O. Box 48
19401 Upplands Vasby
Tel: 0760-861 20
Baerlocher A G
P.O. Box485.
CH -8021 Zurich
Tel: (01) 42.99.00
Hwa Sheng Electric Co., Ltd.
5th Floor Pong Lai Building
245 Min Chuan East Road
P.O. Box 55~79, Taipei
Anglo Thai Engineering Ltd.
P.O. Box 18, 137 Wireless Road
Bangkok
Teknim Company Ltd.
Riza Sah Pehlevi Caddesi 7
Kavaklidere Ankara
Tel: 27~8.00
W yle Distribution Group
8155 North 24th Avenue
Phoenix, AZ 85022
Tel: (602) 249-2232
California
Arrow Electronics, Inc.
720 Palomar Avenue
Sunnyvale, CA 94086
Tel: (408) 739-3011
A vnet Electronics
350 McCormick Avenue
Costa Mesa, CA 92626
Tel: (714) 754~051
Electronic Supply Corp.
2486 Third Street
Riverside, CA 92507
Tel: (714) 683-7300
Hamilton Avnet
1175 Bordeaux Drive
Sunnyvale, CA 94086
Tel: (408) 743-3300
Hamilton Avnet
4545 Viewridge Avenue
San Diego, CA 92123
Tel: (714) 279-2421
Hamilton Electro Sales
10912 W. Washington Blvd
Culver City, CA 90230
Tel: (213) 558-2020
KierullJ Electronics, Inc.
2585 Commerce Way
Los Angeles, CA 90040
Tel: (213) 725-0325
685
RCA Authorized Distributors
Arrow Electroni.s, In••
115 Palm Bay Road, NW
Building 200, Palm Bay, FL
32905
Tel: (3OS) 725-1480
Kierulff Electroni.s, In••
3969 E. Bayshore Road
Palo Alto, CA 94303
Tel: (415) 968-6292
Kierulff Electroni.s, In ••
8797 Balboa Avenue
San Diego, CA 92123
Tel: (714) 278-2112
G. S. Marshall Company
9674 Telstar Avenue
EI Monte, CA 91731
Tel: (213) 686~141
Marshall Industries
17321 Murphy Avenue
Irvine, CA 92714
Tel: (714) 556-6400
RPS Ele.troni.s, In•.
1501 South Hill Street
Los Angeles, CA 900 15
Tel: (213) 748-1271
S.hweber Ele.troni.s Corp.
17811 Gillette Avenue
Irvine, CA 92714
Tel: (714) 556-3880
S.hweber Electroni.s Corp.
3110 Patrick Henry Drive
Santa Clara, CA 95050
Tel: (408) 496~200
Wyle Distribution Group
124 Maryland Avenue
EI Segundo, CA 90245
Tel: (213) 322-3100
Illinois
Wyle Distribution Group
9529 Chesapeake Drive
San Diego, CA 92123
Tel: (714) 565-9171
~Ie Distribution Group
3 Bowers Avenue
Santa Clara, CA 95052
Tel: (408) 727-2500
Colorado
Klerulff Electroni... In••
10890 East 47th Avenue
Denver, CO 80239
Tel: (303) 371-6500
Connecti.ut
Florida
Pyttroni. Industries, In••
Baltimore! Washington
Industrial Pk, 8220 Wellmoor
Court, Savage, MD 20863
Tel: (301) 792~780
Hamilton A vuet Electronics
3197 Tech Drive, No.
St. Petersburg, FL 33702
Tel: (813) 576-3930
S.hweber Ele.troni•• Corp.
9218 Gaither Road
Gaithersburg, MD 20760
Tel: (301) 840-5900
Indiana
Hamilton Avnet Electronics
6700 1-85 Access Road, Suite
IE, Norcross, GA 30071
Tel: (404) 448~800
A. W. Mayer Co.
38 Border Street
West Newton, MA 02165
Tel: (617) 965-1111
Schweber Ele.tronl... In•.
4126 Pleasantdale Road
Atlanta, GA 30340
Tel: (404) 449-9170
S.hweber Ele.troni.s Corp.
25 Wiggins Avenue
Bedford, MA 01730
Tel: (617) 275-5100
Arrow Electronic.. In••
492 Lunt Avenue
Schaumburg, IL 60 193
Tel: (312) 893-9420
Sterling Electroni••, In••
411 Waverly Oaks Road
Waltham, MA 02154
Tel: (617) 894-6200
Hamilton Avnet Electronics
390 I North 25th Avenue
Schiller Park, IL 60 176
Tel: (312) 678-6310
Wilshire Electronl.sf
New Englaud, One Wilshire
Road, Burlington, MA 01803
Tel: (617) 272-3200
MI.higan
Arrow Ele.tronlcs, In••
3810 Varsity Drive
Ann Arbor, M148104
Tel: (313) 971-3220
S.hweber Electroni.s Corp.
1275 Brummel Avenue
Elk Grove Village, IL 60007
Tel: (312) 593-2740
Hamilton Avnet Electroni••
32487 Schoolcraft Road
Livonia, MI 48150
Tel: (313) 5224700
Seml.onductor Specialists, In•.
195 Spangler Avenue
Elmhurst, IL 60126
Tel: (312) 279-1000
RS Electroni.s, In••
34443 Schoolcraft Road
Livonia, MI 481 SO
Tel: (313) 525-1155
Graham Electroni•• Supply,
In••
133 S. Pennsylvania Street
Indianapolis, IN 46204
Tel: (317) 634-3202
S.bweber Ele.troni•• Corp.
33540 Schoolcraft Road
Livonia, MI 48150
Tel: (313) 525-3100
Iowa
Hamilton A vuet Electronics
Commerce Drive, Commerce
Park, Danbury, CT 06810
Tel: (203) 797-1100
Kansas
S.hweber Ele.tronl•• Corp.
Finance Drive, Commerce
Industrial Park, Danbury, CT
06810
Tel: (203) 792-3500
Hamilton A vuet Electronics
9219 Quivira Road
Overland Park, KS 66215
Tel: (913) 888-3900
Lonlsiana
Sterllnl Electronics, In••
4613 Fairfield Road
Metairie, LA 70002
Tel: (504) 887-7610
Maryland
Arrow Ele.troni... In••
480 I Benson Avenue
Baltimore, MD 21227
Tel: (301) 247-5200
Arrow Electronl... In••
1001 NW 62nd Street, Suite 108
Ft. Lauderdale, FL 33309
Tel: (305) 776-7790
Arrow Ele.troni••, In••
96D Commerce Way
Woburn, MA 01801
Tel: (617) 933-3130
Hamilton Avuet Electronics
50 Tower Office Park
Woburn, MA 01801
Tel: (617) 935-9700
Arrow Ele.tronlcs, In••
12 Beaumont Road
Wallingford, CT 06492
Tel: (203) 265-7741
o
M .....busetts
Arrow Ele.troni.s, In•.
2979 Pacific Drive
Norcross, GA 30071
Tel: (404) 449-3252
Newark Electroni.s
500 North Pulaski Road
Chicago, IL 60624
Tel: (312) 6384411
Hamilton Avnet Electroni••
8765 E. Orchard Rond, Suite
708, Englewood, CO 80111
Tel: (303) 740-1000
Wyle Distribution Group
6777 East 50th Avenue
Commerce City, CO 80022
Tel: (303) 287-9611
Hamilton Avnet Electronics
6800 NW 20th Avenue
Ft. Lauderdale, FL 33309
Tel: (3OS) 971-2900
S.hweher Ele.troni•• Corp.
2830 North 28th Terrace
Hollywood, FL 33020
Tel: (305) 927~511
Georgia
Hamnton Avnet Electronics
7255 Standard Drive
Hanover, MD 21076
Tel: (301) 796-5000
Minnesota
D ...o, In••
2500 16th Avenue, SW
Cedar Rapids, IA 52406
Tel: (319) 365-7551
Arrow Electroni••, In•.
5230 West 73rd Street
Edina, MN 55435
Tel: (612) 830-1800
Hamilton Avnet Electronics
7449 Cahill Road
Edina, MN 55435
Tel: (612) 941-3801
S.hweber Ele.troni•• Corp.
7422 Washington Avenue, So.
Eden Prairie, MN 55344
Tel: (612) 941-5280
Missouri
Hamilton Avne!' Electronl••
13743 Shoreline Court East
Earth City, MO 63045
Tel: (314) 344-1200
686 __________________________________________________________________
RCA Authorized Distributors
New Hampshire Arrow Electronics, Inc.
I Perimeter Drive
Manchester, NH 03103
Tel: (603) 668~968
Hamilton A>net Electronics
16 Corporate Circle
East Syracuse, NY 13057
Tel: (315) 437-2641
Oklahoma
Radio, Inc.
1000 S. Main Street
Tulsa, OK 74119
Tel: (918) 587-9123
New Jersey
Arrow Electronics, Inc.
Pleasant Valley Avenue
Moorestown, NJ 08057
Tel: (609) 235-1900
Milgray Electronics, Inc.
191 Hanse Avenue
Freeport, LI, NY 11520
Tel: (516) 546~000
Oregon
Arrow Electronics, Inc.
285 Midland Avenue
Saddlebrook, NJ 07662
Tel: (201) 797-5800
Rochester Radio Supply Co.
140 W. Main Street
Rochester, NY 14614
Tel: (716) 454-7800
Hamilton A>net Electronics
6024 SW Jean Road, Bldg B,
Suite J, Lake Oswego, OR
97034
Tel: (503) 635-8159
Pennsylvania
Hamilton A>net Electronics
10 Industrial Road
Fairfield, NJ 07006
Tel: (201) 575-3390
Schweber Electronics Corp.
2 Town Line Circle
Rochester, NY 14623
Tel: (716) 424-2222
Herbach & Rademan, Inc.
40 I East Erie Avenue
Philadelphia, PA 19134
Tel: (215) 426-1700
Hamilton A>net Electronics
I Keystone Avenue
Cherry Hill, NJ 08003
Tel: (609) 234-2133
Schweber Electronics Corp.
Jericho Turnpike
Westbury, LI, NY 11590
Tel: (516) 334-7474
Kierulff Electronics, Inc.
3 Edison Place
Fairfield, NJ 07006
(201) 935-2120
916 Main Street
Buffalo, NY 14202
Tel: (716) 884-3450
Reseo Electronics
Div. of Astrex, Inc., Airport &
Central H wys, Airport
Industrial Park, Pennsauken,
NJ 08110
Tel: (609) 6624000
New Mexico
Arrow Electronics, Inc.
2460 Alamo, SE
Albuquerque, NM 87106
Tel: (505) 2434566
Hamilton Avnet Electronics
2524 Baylor SE
Albuquerque, NM 87106
Tel: (505) 765-1500
New York
Arrow Electronics, Inc.
900 Broad Hollow Road
Route 110, Farmingdale, LI,
NY 11735
Tel: (516)
694~800
Arrow Electronics, Inc.
7705 Maltage Drive
Liverpool, NY 13008
Tel: (315) 652-1000
Arrow Electronics, Inc.
3000 South Winton Road
Rochester, NY 14623
Tel: (716) 275-0300
Hamilton A>net Electronics
5 Hub Drive
Melville, NY 11746
Tel: (516) 454~000
Hamilton Avnet Electronics
167 Clay Road
Rochester, NY 14623
Tel: (716) 442·7820
Texas
Arrow Electronics, Inc.
10700 Corporate Drive #100
Stafford, TX 77477
Tel: (713) 4914100
North Carolina Arrow Electronics, Inc.
938 Burke Street,
Winston-Salem, NC 27101
Tel: (919) 725-8711
Hamilton A>net Electronics
2401 Rutland Drive
Austin, TX 78758
Tel: (512) 837-8911
Hamilton A vnet Electronics
2803 Industrial Drive
Raleigh, NC 27609
Tel: (919) 829-8030
Hamilton A met Electronics
2111 West Walnut Hill Lane
Irving, TX 75002
Tel: (214) 6594100
Hammond Electronics of
Hamilton Avnet Electronics
3939 Ann Arbor Street
Houston, TX 77063
Tel: (712) 780-1771
Carolina
2923 Pacific Avenue
Greensboro, NC 27406
Tel: (919) 275~391
Ohio
Arrow Electronics, Inc.
13715 Gamma Road
Dallas, TX 75240
Tel: (214) 386-7500
Summit Distributors, Inc.
Schweber Electronics Corp.
18 Madison Road
Fairfield, NJ 07006
Tel: (201) 227-7880
Wilshire Electronics/NJ
IIII Paulison Avenue
Clifton, NJ 07015
Tel: (201) 340-1900
Schweber Electronics Corp.
101 Rock Road
Horsham, PA 19044
Tel: (215) 441-0600
Arrow Electronics, Inc.
10 Knollcrest Drive
Reading, OH 45237
Tel: (513) 761-5432
Schweber Electronics Corp.
4202 Beltway, Dallas, TX 75234
Tel: (214) 661-5010
Arrow Electronics, Inc.
6238 Cochran Road
Solon, OH 44139
Tel: (216) 248·3990
7420 Harwin Drive
Houston, TX 77036
Tel: (713) 784-3600
Schweber Electronics Corp.
Sterling Electronics, Inc.
2335A Kramer Lane, Suite A
Austin, TX 78758
Tel: (512) 836-1341
Arrow Electronics, Inc.
7620 McEwen Road
Centerville, OH 45459
Tel: (513) 435-5563
Hamilton Amet Electronics
4588 Emery Industrial Parkway
Cleveland, OH 44128
Tel: (216) 831-3500
Sterling Electronics, Inc.
11090 Stem mons Freeway
(Stemmons at Southwell)
Dallas, TX 75229
Tel: (214) 243-1600
Hamilton A>net Electronics
954 Senate Drive
Dayton, OH 45459
Tel: (513) 433-0610
Sterling Electronics, Inc.
4201 Southwest Freeway
Houston, TX 77027
Tel: (713) 627-9800
Hughes Peters, Inc.
481 East 11th Avenue
Columbus, OH 43211
Tel: (614) 294·5351
2874 Walnut Hill Lane
Dallas, TX 75229
Tel: (214) 358·2418
Trevino Electronics, Inc.
Schweber Electronics Corp.
23880 Commerce Park Road
Beachwood, OH 44122
Tel: (216) 464-2970
Utah
Hamilton A>net Electronics
1585 West 2100 South
Salt Lake City, UT 84119
Tel: (801) 972·2800
The Stolls Friedman Co.
2600 East River Road
Dayton, OH 45439
Tel: (513) 298-5555
Washington
Hamilton Avnet Electronics
14212 NE 21st Street
Bellevue, W A 98005
Tel: (206) 746·8750
687
RCA Authorized Distributors
Robert E. Priebe Company
2211 5th Avenue
Seattle, W A 98121
Tel: (206) 682-8242
Venezuela
Wyle Distribution Group
1750 132nd Avenue, NE
Bellevue, W A 98005
,Tel: (206) 453-8300
Wisconsin
West Indies
Da Costa and Musson Ltd.
Post Office Box 103, General
Post Office, Barbados
West Germany
AICred Neye Enatechnlk GmbH
Schillerstrasse 10,
2085 Quickborn
Tel: 04106/6121
Taylor Electric Company
1000 W, Donges Bay Road
Mequon, WI 53092
Tel: (414) 241-4321
Uruguay
u.s.
RTG E. Sprlngorum GmbH &; Co.
Bronnerstrasse 7,
4600 Dortmund I
Tel: 0231/5495·1
Tele·Cuba, S.A.
Av. Este 0, No. 164, Ferrenquin
a la Cruz, La Candelaria,
Caracas - MAIL ADDRESS:
Apartado 9520, Caracas,
Venezuela
Arrow Electronics, Inc.
430 West Rawson Avenue
Oak Creek, WI 53154
Tel: (414) 764-6600
Hamilton Avnet Electronics
2975 South Moorland Road
New Berlin, WI 53151
Tel: (414) 784-4510
Elkose GmbH
BahnhoCstrasse 44,
7141 Moglingen
Tel: 07141/487·1
Dina Radio, C.A.
Calle Madrid Entre Nueva
York y Carolina, Quinta Tana
Las Mercedes 107, CaracasMAIL ADDRESS: Apartado
Postal 60429, Chacao, Caracas,
Venezuela
Sasco GmbH
Hermann-Oberth·Strasse 16
8011 Putzbrunn
Tel: 089/46111
Spoerle Electronic KG
Otto·Hahn-Strasse 13,
6072 Dreieich
Tel: 06103/3041
Yugoslavia
Gustav Beck
Ellersdorfer Strasse 7.
8500 Nurnberg 15 .
Tel: 0911/34961-66
APSA
Av, Italia 4230, Montevideo
Avtotehna
P.O. Box 593,
Titova 36·XI LjUbljana 61000
Tel: 317044
RCA Manufacturers' Representatives
Arthur H. Baler Company
4940 Profit Way, Dayton, OH
45414
Tel: (513) 276-4128
Michigan
Arizona
Thom Luke Sales, Inc.
2940 North 67th Place, Suite B
Scottsdale, AZ 85251
Tel: (602) 941·1901
Nicon Associates
3835 West Eight Mile Road
Detroit, MI 48221
Tel: (313) 341·7688
Missouri
California
Bestronic.
(San Diego Area), 10150
Sorrento Valley Road, Suite
300, San Diego, CA 92121
Tel: (714) 452·5500
Kebco
75 Worthington Drive, Suite
101, Maryland Heights, MO
63043
Tel: (314) 576-4110/4111
Montana
Waugaman Associates, Inc.
4800 Van Gordon Street
Wheatridge, CO 80033
Tel: (303) 423·1020
R'Marketing
940 North 400 East, North Salt
Lake City, UT 84054
Tel: (801) 298·2631
Nevada
Delaware
Thomas Associates, Inc.
12 South Black Horse Pike
Bellmawr, NJ 08031
Tel: (609) 933·2600
(215) 627-8614
Thom Luke Sales, Inc.
(Clark County only), 2940
North 67th Place, Suite B
Scottsdale, AZ 85251
Tel: (602) 941·1901
New Jersey
Florida
G. F. Bohman Associates
130 North Park Avenue
Apopka, FL 32703
Tel: (305) 886·1882
Thomas Associates, Inc.
(Southern NJ), 12 South Black
Horse Pike, Bellmawr, NJ
08031
Tel: (609) 933·2600
(215) 627-6614
Tennessee
Georgia
Montgomery Marketing
Pineland Woods #303, 3640
Peachtree, Corner, West
Norcross, GA 30092
Tel: (404) 447-6124
New York
L·Mar Associates, Inc.
(Upstate NY), 4515 Culver
Road, Rochester, NY 14622
Tel: (716) 544·8000
Montgomery Marketing, Inc.
1212 Lane Drive, P.O. Box 520
Cary, NC 27511
Tel: (919) 467-6319
Utah
L·Mar Associates, Inc.
216 Tilden Drive, East
Syracuse, NY 13057
Tel: (315) 437·7779
R'Marketing
940 North 400 East, Suite B
North Salt Lake City, UT 84054
Tel: (801) 298·2631
Washington
L·Mar Associates, Inc.
921 North Rogers Avenue,
Endicott, NY 13760
Tel: (607) 748·1482
Western Technical Sales, Inc.
P.O. Box 3923, Bellevue, WA
98009
Tel: (206) 641·3900
West Virginia
North Carolina Montgomery Marketing, Inc.
1212 Lane Drive, P.O. Box 520
Cary, NC 27511
Tel: (919) 467-6319
Arthur H. Baier Company
67 Alpha Park, Cleveland, OH
44143
Tel: (216) 461·6161
Wisconsin
Arthur H. Baler Company
67 Alpha Park, Cleveland, OH
44143
Tel: (216) 461·6161
Key Enterprises
850 Elm Grove Road, Elm
Grove, WI 53122
Tel: (414) 784·3390
Wyoming
Waugaman Associates, Inc.
4800 Van Gordon Street
Wheatridge, CO 80033
Tel: (303) 423·1020
Colorado
idaho
Western Technical Sales, Inc.
(North of Boise), P.O. Box 3923
Bellevue, W A 98009
Tel: (206) 641·3900
R'Marketing
(East & South of Boise), 940
North 400 East, North Salt
Lake City, UT 84054
Tel: (801) 298·2631
Illinois
Kansas
688
Kebco
(Southern ILL Area), 75
Worthington Drive, Suite 101
Maryland Heights, MO 63043
Tel: (314) 576-4110/4111
Kebco
7070 West 107th Street, Suite
160, Overland Park, KS 66212
Tel: (913) 649·1051
Ohio
Oregon
Western Technical Sales, Inc.
2271 NW Cornell Road
Hillsboro, OR 97123
Tel: (S03) 640-4621
Pennsylvania
Arthur H. Baler Company
(Western PAl 67 Alpha Park
Cleveland, OH 44143
Tel: (216) 461-6161
Thomas Associates, Inc.
(Eastern PAl, 12 South Black
Horse Pike, Bellmawr, NJ
08031
Tel: (609) 933-2600
(21S) 627-6614
South Carolina Montgomery Marketing, Inc.
1212 Lane Drive, P.O. Box 520
Cary, NC 27511
Tel: (919) 467-6319
RCA Solid State is a leading supplier of high-reliability
integrated circuits to the military and aerospace community. Years of commitment, dedication, experience,
and know-how make possible shipment of hundreds of
thousands of quality high-reliability microcircuits annually.
RCA specialists fully understand the needs of component and systems engineers in the design of highreliability equipment, are thoroughly familiar with the
objective and requirements of MIL-STD-883 and MILM-38510, and work closely with governmental agencies
in the establishment of detailed specifications for highreliability microcircuits. Moreover, RCA Solid State provides complete facilities for processing and testing integrated circuits to these specifications. RCA Solid
State is justly proud of its many significant accomplishments with respect to the development, production and shipment of high-reliability integrated circuits, including:
MIL-M-38510 Class B requirements. Extensive inventories are maintained for rapid, off-the-shelf delivery.
RCA also offers high-reliability versions of standardproduct types that are processed and screened to
special customized specifications, especially for the
aerospace user and others who procure types to Class
S specifications.
RCA solid State maintains an extensive computer file
of customer specifications and has the methodology required to translate these customized specifications into
internal RCA standards and factory operating procedures. In addition to the de\ailed device specifications, the computer file lists the customer specification
number, any revision number, and the RCA custom
number assigned to a specific device type.
Radiation-Hardened High·Reliability IC's
First supplier of MIL-M-38510 to attain Class S
certification
First supplier of MIL-M-38510 COS/MOS integrated circuits
Leader in the production of radiation-resistant
microcircuits
Initiator of scanning-electron-microscope (SEM)
inspections in the production of high-reliability
microcircuits-in use at RCA since 1972
Initiator of ·MIL-STD-883, Condition A inspections-in use at RCA since 1972
RCA also offers radiation-hardened versions of highreliability (Class S or equivalent) CD4000- and CDP1800series COS/MOS integrated circuits. Radiation-hardened types, which are identified by addition of a "Z" or
"J" suffix to the device type number, are electrically and
mechanically identical to their prototype with. the exception that they are processed and screened to withstand a total gamma-radiation dosage of 10' rads(Si) for
Z-suffix types or 10· rads(Si) for J-suffix types.
Standard·Product High·Reliability IC's
RCA Solid State has complete custom-circuit capabilities for various COS/MOS and bipolar integrated-circuit
technologies. Custom circuits are offered whenever this
approach to integrated-circuit design is determined to
be economically feasible. Various custom-design
techniques have been developed to meet specific time
and volume requirements. RCA high-reliability custom
integrated circuits can be processed and screened to
MIL-STD-883 Class B specifications.
o
•
•
•
•
RCA offers high-reliability versions of virtually its entire
line of standard-product integrated circuits from the
CD4000 series of COS/MOS digital logic types, the
CDP1800 series of microprocessor and associated
memory and Input/output (I/O) types, and the CA3000
series of bipolar linear types. These integrated circuits
are processed and. screened to either MIL-STD-883 or
High·Reliability Custom IC's
"RCA High-Reliability Integrated Circuits," RIC-300, provides detailed
information on types available, controlled ratings and characteristics,
processing and screening schedules, and the reliability levels and classes to
which the types in each RCA high-reliability IC product series are supplied.
ROil State
Solid
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