1981_82_Memory_Databook 1981 82 Memory Databook
User Manual: 1981_82_Memory_Databook
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)lIALITY' RELIABILITY· TECHNOLOGY
MOTOROLA
SELECTOR
GUIDES
CROSS-REFERENCE
1
MOS Memories
RAM, EPROM, EEPROM, ROM
2
CMOS Memories
RAM, ROM
3
Bipolar Memories
TTL, MECL-RAM, PROM
4
Memory Boards
5
Mechanical Data
6
MOTOROLA
MEMORIES
Motorola has developed a very broad range of reliable MOS and bipolar
memories for virtually any digital data processing system application.
Complete specifications for the individual circuits are provided in the
form of data sheets. In addition, selector guides are included to simplify
the task of choosing the best combination of circuits for optimum
system architecture.
New Motorola memories are being introduced continually. For the latest
releases, and additional technical information or pricing, contact your
nearest authorized Motorola distributor or Motorola sales office.
The information in this book has been carefully checked; no responsibility, however, is assumed for inaccuracies. Furthermore, this information does not convey to the purchaser of microelectronic devices
any license under the patent rights of the manufacturer.
© MOTOROLA INC., 1980
"All Rights Reserved"
iii
MECL, EXORciser are trademarks of Motorola Inc.
iv
Table of Contents
Organization
Page
Alphanumeric Index ......................................................... vii
CHAPTER 1
Memories Selection Guide .................................................... 1-2
Memory Systems Board Selector Guide and Cross Reference .......................... 1-8
MOS Memory Cross-Reference ................................................ 1-9
CHAPTER 2
Dynamic RAMs
MCM4027A
MCM4116B
MCM4517
MCM6632
MCM6633
MCM6664
MCM6665
MCM6665L25
4K x 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
16K x 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
16K x 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
32K x 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
32K x 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 c34
64K x 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41
64K x 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49
64K x 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-56
Static RAMs
MCM2114,21L14
1 K x 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63
MCM2115A, 21L15A, 2125A, 21L25A 1 K x 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-68
MCM2115H,2125H
1Kx1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-74
MCM2147
4Kx1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-75
MCM2147H
4Kx1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-80
MCM2148
1Kx4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-81
1Kx4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-85
MCM2149
16Kx1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-86
MCM2167
2K x 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-87
MCM4016
MCM6641, 66L41
4K x 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-88
MCM6810, 68A10, 68B10
128 x 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-92
EPROMs
MCM2532, 25L32
MCM2708, 27A08
MCM2716 27L16
TMS2716, TMS27A16
MCM68708,68A708
MCM68732,68L732
MCM68764,68L764
MCM68766
4K x 8
1K x 8
2K x 8
2K x 8
1K x 8
4Kx8
8K x 8
8Kx8
EEPROMs
MCM2801
MCM2802
MCM2816
16x16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-141
32 x 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-206
2Kx8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-147
ROMs
MCM6670, 6674
MCM66700, 710, 714, 720, 730, 734,
740,750,751,760,770,780,790
MCM68A30A, 68B30A
MCM68A308,68B308
MCM68A316A
MCM68A316E
MCM68A332
MCM68A364,68B364
MCM68365
MCM68366
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-96
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-102
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-108
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-114
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-120
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-126
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-131
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-136
128x(7x5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-148
128x(7x9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-155
1 K x 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-169
1Kx8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-174
2K x 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-179
2Kx8 . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . 2-183
4Kx8 . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . 2-187
8Kx8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-191
8K x 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-196
8Kx8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-201
v
Table of Contents (Continued)
Page
Organization
CHAPTER 3
CMOS Memories
Static RAMs
MCM14505
MCM14537
MCM14552
MCM5101, 51 L01
MCM6508, 6518
MCM65116
MCM65147
MCM65148
64 x 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
256x1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
64x4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
256x4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
1 K x 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31
2K x 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35
4K x 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36
1 K x 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37
ROMs
MCM14524
MCM65516
CHAPTER 4
256x4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38
2K x 8 ..... ' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44
Bipolar Memories
TTL RAMs
1024 x 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
1024x 1 . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
MCM93415
MCM93425
TTL PROMs
MCM7680, 7681
MCM7684, 7685
1024x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
2Kx4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
MECL Memories
General Information ..................................................... 4-19
MECL RAMs
MCM10143
MCM10144,10544
MCM10145,10545
MCM 10146, 10546
MCM10147, 10547
MCM10148,10548
MCM1 0152, 10552
8 x 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
256x 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27
16 x 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29
1024x1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31
128 x 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33
64 x 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35
256x 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37
MECL PROMs
MCM10139,10539
MCM 10149, 10549
CHAPTER 5
32 x 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39
256x4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-43
Memory Subsystems
Board Level
MMS1102
MMS1122
MMS1132
MMS1117
MMS1119
MMS1128
MMS1170
MMS780
MMS8064
LSI-11 Compatible Add-In Memory (32K x 18) . . . . . . . . . . . . . . . . . 5-3
LSI-11, LSI-11/23 Compo Add-In Memory (32K x 16) ............ 5-5
LSI-11, LSI-11123 Compo Add-In Memory (1 28K x 16) ........... 5-7
PDP-11 Compatible (HEX SPC) Add-In Memory (64K x 18) ......... 5-9
PDP-11 (Modified or Extended Unibus) Compo Memory (128K x 18) .. 5-11
PDP-11 (Modified Unibus) Memory Compo (32K, 48K x 18) ....... 5-15
PDP-11170 Compatible Add-In Memory . . . . . . . . . . . . . . . . . . . . . 5-20
VAX-11/780 Compatible Add-In Memory . . . . . . . . . . . . . . . . . . . 5-22
Inter Multibus Compatible Memory . . . . . . . . . . . . . . . . . . . . . . . . 5-25
CHAPTER 6 - Mechanical Data . ......................................... 6-1
vi
Alphanumeric Index
D.~.
Page
Device
MCM10139 . . . . . . . . . . . . . . . . . . . . . 4-39
MCM10143 . . . . . . . . . . . . . . . . . . . . . 4-22
MCM10144 . . . . . . . . . . . . . . . . . . . . . 4-27
MCM10145 . . . . . . . . . . . . . . . . . . . . . 4-29
MCM10146 . . . . . . . . . . . . . . . . . . . . . 4-31
MCM10147 . . . . . . . . . . . . . . . . . . . . . 4-33
MCM10148 . . . . . . . . . . . . . . . . . . . . . 4-35
MCM10149 . . . . . . . . . . . . . . . . . . . . . 4-43
MCM10152 . . . . . . . . . . . . . . . . . . . . . 4-37
MCM10539 . . . . . . . . . . . . . . . . . . . . . 4-39
MCM10544 . . . . . . . . . . . . . . . . . . . . . 4-27
MCM10545 . . . . . . . . . . . . . . . . . . . . . 4-29
MCM 10546 . . . . . . . . . . . . . . . . . . . . . 4-31
MCM10547 ..................... 4-33
MCM10548 . . . . . . . . . . . . . . . . . . . . . 4-35
MCM10549 . . . . . . . . . . . . . . . . . . . . . 4-43
MCM10552 . . . . . . . . . . . . . . . . . . . . . 4-37
MCM14505 . . . . . . . . . . . . . . . . . . . . . . 3-3
MCM14524 . . . . . . . . . . . . . . . . . . . . . 3-38
MCM14537 . . . . . . . . . . . . . . . . . . . . . 3-12
MCM14552 . . . . . . . . . . . . . . . . . . . . . 3-20
MCM21L14 ..................... 2-63
MCM21 L 15A .................... 2-68
MCM21L25A .................... 2-68
MCM2114 . . . . . . . . . . . . . . . . . . . . . . 2-63
MCM2115A . . . . . . . . . . . . . . . . . . . . . 2-68
MCM2115H . . . . . . . . . . . . . . . . . . . . . 2-74
MCM2125A ..................... 2-68
MCM2125H . . . . . . . . . . . . . . . . . . . . . 2-74
MCM2147 . . . . . . . . . . . . . . . . . . . . . . 2-75
MCM2147H . . . . . . . . . . . . . . . . . . . . . 2-80
MCM2148 . . . . . . . . . . . . . . . . . . . . . . 2-81
MCM2149 . . . . . . . . . . . . . . . . . . . . . . 2-85
MCM2167 . . . . . . . . . . . . . . . . . . . . . . 2-86
MCM25L32 . . . . . . . . . . . . . . . . . . . . . 2-96
MCM2532 . . . . . . . . . . . . . . . . . . . . . . 2-96
MCM27A08 .................... 2-102
MCM27L16 .................... 2-108
MCM2708 . . . . . . . . . . . . . . . . . . . . . 2-102
MCM2716 . . . . . . . . . . . . . . . . . . . . . 2-108
MCM2801 . . . . . . . . . . . . . . . . . . . . . 2-141
MCM2802 . . . . . . . . . . . . . . . . . . . . . 2-206
MCM2816 . . . . . . . . . . . . . . . . . . . . . 2-147
MCM4016 . . . . . . . . . . . . . . . . . . . . . . 2-87
MCM2047A . . . . . . . . . . . . . . . . . . . . . . 2-3
MCM41168 . . . . . . . . . . . . . . . . . . . . . 2-13
MCM4517 . . . . . . . . . . . . . . . . . . . . . . 2-20
MCM51L01 . . . . . . . . . . . . . . . . . . . . . 3-27
MCM5101 . . . . . . . . . . . . . . . . . . . . . . 3-27
MCM6508 . . . . . . . . . . . . . . . . . . . . . . 3-31
MCM65116 . . . . . . . . . . . . . . . . . . . . . 3-35
MCM65147 . . . . . . . . . . . . . . . . . . . . . 3-36
MCM65148 . . . . . . . . . . . . . . . . . . . . . 3-37
MCM6518 . . . . . . . . . . . . . . . . . . . . . . 3-31
MCM65516 . . . . . . . . . . . . . . . . . . . . . 3-44
MCM66L41 .................... : 2-88
MCM6632 . . . . . . . . . . . . . . . . . . . . . . 2-26
MCM6633 ...................... 2-34
Page
MCM6641 . . . . . . . . . . . . . . . . . . . . . . 2-88
MCM6664 . . . . . . . . . . . . . . . . . . . . . . 2-41
MCM6665 . . . . . . . . . . . . . . . . . . . . . . 2-49
MCM6665L25 ................... 2-56
MCM6670 . . . . . . . . . . . . . . . . . . . . . 2-148
MCM66700 . . . . . . . . . . . . . . . . . . . . 2-155
MCM66710 . . . . . . . . . . . . . . . . . . . . 2-155
MCM66714 . . . . . . . . . . . . . . . . . . . . 2-155
MCM66720 .................... 2-155
MCM66730 .................... 2-155
MCM66734 .................... 2.-155
MCM6674 . . . . . . . . . . . . . . . . . . . . . 2-148
MCM66740 .................... 2-155
MCM66750 .................... 2-155
MCM66751 .................... 2-155
MCM66760 . . . . . . . . . . . . . . . . . . . . 2-155
MCM66770 . . . . . . . . . . . . . . . . . . . . 2-155
MCM66780 . . . . . . . . . . . . . . . . . . . . 2-155
MCM66790 .................... 2-155
MCM68A 10 . . . . . . . . . . . . . . . . . . . . . 2-92
MCM68A30A ................... 2-169
MCM68A308 ................... 2-174
MCM68A316A .................. 2-179
MCM68A316E .................. 2-183
MCM68A332 . . . . . . . . . . . . . . . . . . . 2-187
MCM68A364 ................... 2-191
MCM68A708 ................... 2-120
MCM68B 10 . . . . . . . . . . . . . . . . . . . . . 2-92
MCM68B30A ................... 2-169
MCM68B308 ................... 2-174
MCM68B364 ................... 2-191
MCM68L732 ................... 2-126
MCM68L764 . . . . . . . . . . . . . . . . . . . 2-131
MCM6810 . . . . . . . . . . . . . . . . . . . . . . 2-92
MCM68365 . . . . . . . . . . . . . . . . . . . . 2-196
MCM68366 .................... 2-201
MCM68708 .................... 2-120
MCM68732 .................... 2-126
MCM68764 .................... 2-131
MCM68766 .................... 2-136
MCM7680 . . . . . . . . . . . . . . . . . . . . . . 4-11
MCM7681 . . . . . . . . . . . . . . . . . . . . . . 4-11
MCM7684 . . . . . . . . . . . . . . . . . . . . . . 4-15
MCM7685 . . . . . . . . . . . . . . . . . . . . . . 4-15
MCM9341 5 . . . . . . . . . . . . . . . . . . . . . . 4-3
MCM93425 . . . . . . . . . . . . . . . . . . . . . . 4-7
MMS1102 . . . . . . . . . . . . . . . . . . . . . . . 5-3
MMS 111 7 . . . . . . . . . . . . . . . . . . . . . . . 5-9
MMS 111 9 . . . . . . . . . . . . . . . . . . . . . . 5-11
MMS1122 . . . . . . . . . . . . . . . . . . . . . . . 5-5
MMS 11 28 . . . . . . . . . . . . . . . . . . . . . . 5-1 5
MMS1132 . . . . . . . . . . . . . . . . . . . . . . . 5-7
MMS1170 . . . . . . . . . . . . . . . . . . . . . . 5-20
MMS780 . . . . . . . . . . . . . . . . . . . . . . . 5-22
MMS8064 . . . . . . . . . . . . . . . . . . . . . . 5-25
TMS27L16 . . . . . . . . . . . . . . . . . . . . . 2-114
TMS2716 . . . . . . . . . . . . . . . . . . . . . 2-114
vii
SELECTOR
GUIDES
CROSS-REFERENCE
1-1
MEMORIES SELECTION GUIDE
NOTES
Not all package options are listed.
Operating temperature ranges:
MOS - O°C to 70°C Selected MOS memories are offered in the following temperature
ranges:
-40°C to +85°C ("G" series)
- 55°C to + 125°C ("E" series)
ECl - Consult individual data sheets
TTL - Military - 55°C to + 125°C, Commercial OOC to 70°C
FOOTNOTES
1 Motorola's innovative pin # 1 refresh.
2 All MOS memory outputs are three-state except the open collector MCM2115A series.
3 Character generators include shifted and unshifted characters, ASCII, alphanumeric control,
math, Japanese, British, German, European and French symbols.
* To be introduced.
1-2
MEMORIES SELECTION GUIDE (continued)
RAMs
MOS DYNAMIC RAMs
Part Number
Access Time
Ins maxI
Power
Supplies
No. of Pins
MCM4027AC-2 . . . . . . . . . . . . . . .
MCM4027AC-3 . . . . . . . . . . . . . . .
MCM4027AC-4 . . . . . . . . . . . . . . .
150
200
250
+ 12, ± 5 V
+ 12, ± 5 V
+ 12, ± 5 V
16
16
16
+
+
+
+
16
16
16
16
16
16
16
Organization
4096 x 1
4096 x 1
4096 x 1
16384 x 1
16384 xl
16384 x 1
16384 xl
16384 xl
16384 x 1
16384 x 1
MCM411 6BC 1 5
MCM4116BC20
MCM4116BC25
MCM4116BC30
MCM4517C12 ·
MCM4517C15 ·
MCM4517C20 ·
· .............
· .............
· .............
· .............
..............
..............
..............
150
200
250
300
120
150
200
32768 xl
32768 x 1
32768 xl
32768 x 1
32768 x 1
32768 xl
MCM6632L 1 51
MCM6632L20 1
MCM6632L25 1
MCM6633L 15 ·
MCM6633L20 ·
MCM6633L25 ·
· .............
·.............
· .............
..............
..............
.. ... ... .. ....
150
200
250
150
200
250
+5V
+5V
+5V
+5V
+5V
+5V
16
16
16
16
16
16
65536 xl
65536 xl
65536 x 1
65536 xl
65536 x 1
65536 xl
MCM6664L 1 51
MCM6664L20 1
MCM6664L25 1
MCM6665L 15 ·
MCM6665L20 ·
MCM6665L25 ·
·. . . . . .... ....
·. ... ... . . ....
· .............
..............
..............
..............
150
200
250
150
200
250
+5V
+5V
+5V
+5V
+5V
+5V
16
16
16
16
16
16
Access Time
Ins maxI
Output
No. of Pins
12, ± 5
12, ± 5
12, ± 5
12, ± 5
+5V
+5V
+5 V
V
V
V
V
TTL BIPOLAR RAMs
Organization
Part Number
256 x 4
256 x 4
MCM93L412*
MCM93L422*
55
55
Open Collector
3·State
22
22
256x4
256x4
MCM93412 · ................
MCM93422 · . . . . . . . . . . . . . . . .
45
45
Open Collector
3·State
22
22
256 x 9
256x 9
MCM93478* ................
MCM93479* . . . . . . . . . . . . . . . .
60
60
Open Collector
3·State
24
24
1024 x 1
1024 x 1
MCM93415 · . . . . . . . . . . . . . . . .
MCM93425 · ................
45
45
Open Collector
3·State
16
16
See Notes on Page 1 - 2.
1-3
MEMORIES SELECTION GUIDE (continued)
MOS STATIC RAMs (+ 5 Voltsl
Part Number
Access Time
(ns max)
No. of Pins
MCM6810 . . . . . . . . . . . . . . . . . .
MCM68A10 . . . . . . . . . . . . . . . . .
MCM68B10 . . . . . . . . . . . . . . . .
450
360
250
24
24
24
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
MCM2114P20 . . . . . . . . . . . . . .
MCM2114P25 . . . . . . . . . . . . . .
MCM2114P30 . . . . . . . . . . . . . .
MCM2114P45 . . . . . . . . . . . . . .
MCM21 L 14P20 . . . . . . . . . . . . . .
MCM21 L 14P25 . . . . . . . . . . . . . .
MCM21L14P30 . . . . . . . . . . . . . .
MCM21 L 14P45 . . . . . . . . . . . . . .
.
.
.
.
.
.
.
.
200
250
300
450
200
250
300
450
18
18
18
18
18
18
18
18
1024 x
1024 x
1024 x
1024 x
1024 x
1024 x
1024 x
1024 x
1024 x
1024 x
MCM2115AC45 2 . . . . . . . . . . . .
MCM2115AC55 2 . . . . . . . . . . . .
MCM2115AC70 2 . . . . . . . . . . . .
MCM21L15AC45 1 . . . . . . . . . . .
MCM21 L 1 5AC70 2 . . . . . . . . . . .
MCM2125AC45 . . . . . . . . . . . . .
MCM2125AC55 . . . . . . . . . . . . .
MCM2125AC70 . . . . . . . . . . . . .
MCM21 L25AC45 . . . . . . . . . . . .
MCM21L25AC70 . . . . . . . . . . . .
.
.
.
.
.
.
.
.
.
.
45
55
70
45
70
45
55
70
45
70
16
16
16
16
16
16
16
16
16
16
Organization
128 x 8
128 x 8
128 x 8
1
1
1
1
1
1
1
1
1
1
4096 x 1
4096 x 1
4096 x 1
MCM2147C55
MCM2147C70
MCM2147C85
55
70
85
18
18
18
1024 x
1024 x
1024 x
1024 x
1024 x
1024 x
MCM2148C55*
MCM2148C70*
MCM2148C85*
MCM2149C55*
MCM2149C70*
MCM2149C8 5 *
55
70
85
55
70
85
18
18
18
18
18
18
Part Number
Access Time
(ns max)
No. of Pins
MCM5101P65 · ..............
MCM5101P80 · ..............
MCM51L01P45 . . . . . . . . . . . . . . .
MCM51 L01 P65 . . . . . . . . . . . . . . .
650
800
450
650
22
22
22
22
· ..............
· ..............
· ..............
· ..............
300
460
300
460
16
16
18
18
4
4
4
4
4
4
CMOS STATIC RAMs (+ 5 Voltsl
Organization
256
256
256
256
x4
x4
x4
x4
1024 x
1024 x
1024 x
1024 x
1
1
1
1
MCM6508C30
MCM6508C46
MCM6518C30
MCM6518C46
See Notes on Page 1 -2.
1-4
MEMORIES SELECTION GUIDE (continued)
Eel BIPOLAR RAMs
Organization
Part Number
Access Time
(ns max)
Output
No. of Pins
8x2
256 x 1
16 x 4
1024 x 1
1024 x 1
128 x 1
256 x 1
256 x 4
4096 x 1
4096 x 1
4096 x 1
1024 x 4
MCM10143 · ....... .........
MCM10144 · . . . . . . . . . . . . . . . .
MCM10145 · ................
MCM10146 · ................
MCM1 0146A * · . . . . . . . . . . . . . .
MCM1 0147
MCM10152 · ................
MCM10422 · ...... ..........
MCM10470 · ................
MCM1 0470A' · ..............
MCM 104 70B' (low power) . . . . . .
MCM10474 · ...............
15
26
15
29
15
15
15
15
35
20
35
25
ECloutput
ECl output
ECloutput
EC l output
ECloutput
ECloutput
ECloutput
ECloutput
ECloutput
ECloutput
ECloutput
ECloutput
24
16
16
16
16
16
16
24
18
18
18
24
Part Number
Access Time
(ns max)
Power
Supplies
No. of Pins
EPROMs
MOS EPROMs
Organization
1024 x
1024 x
1024 x
1024 x
8
8
8
8
MCM2708C · ................
MCM27A08C · ...............
MCM68708C · . . . . . . . . . . . . . . .
MCM68A708C · ..............
450
300
450
300
+
+
+
+
±5V
±5V
±5V
±5V
24
24
24
24
2048
2048
2048
2048
2048
2048
x
x
x
x
x
x
8
8
8
8
8
8
TMS2716C . . . . . . . . . . . . . . . . . .
TMS27A16C . . . . . . . . . . . . . . . . .
MCM2716C · ................
MCM2716C35 · ..............
MCM27l16C · ...............
MCM27l16C35 · .............
450
300
450
350
450
350
+ 12, ±5V
+ 12, ±5V
+5V
+5V
+5V
+5V
24
24
24
24
24
24
4096
4096
4096
4096
x
x
x
x
8
8
8
8
MCM2532C · . . . . . . . . . . . . . . . .
MCM2532C35 · ..............
MCM25l32C · ...............
MCM25l32C35 · . . . . . . . . . . . . .
450
350
450
350
+5V
+5V
+5 V
+5 V
24
24
24
24
8192 x 8
8192x8
8192x8
8192x8
8192 x 8
MCM68764C · ...............
MCM68764C35 · .............
MCM68l764C · . . . . . . . . . . . . . .
MCM68l764C35 .............
MCM68766C35 · .............
450
350
450
350
350
+5 V
+5V
+5V
+5V
+5V
24
24
24
24
24
Part Number
Access Time
Power
Supplies
No. of Pins
1O.us
10.us
0.45
+5V
+5 V
+5V
14
14
24
12,
12,
12,
12,
EEPROM
MOS EEPROM
Organization
16 x 16
32 x 32
2Kx 8
MCM2801
MCM2802
MCM2816
· .................
· .................
· .................
. See Notes on Page 1 - 2.
1- 5
MEMORIES SELECTION GUIDE (continued)
ROMs
MaS STATIC ROMs (+ 5 Volts)
Character Generators 3
Organization
Part Number
Access Time
(ns max)
No. of Pins
128 x (7 x 5)
128 x (7 x 5)
MCM6670P · ................
MCM6674P · ................
350
350
18
18
128 x (9 x
128 x (9 x
128 x (9 x
128 x (9 x
128 x (9 x
128 x (9 x
128.x (9 x
128 x (9 x
128 x (9 x
128 x (9 x
128 x (9 x
128 x (9 x
MCM66700P
MCM66710P
MCM66714P
MCM66720P
MCM66730P
MCM66734P
MCM66740P
MCM66750P
MCM66760P
MCM66770P
MCM66780P
MCM66790P
· . . . . . . . . . . '.' . . .
·.. ... ..........
· ...............
· ...............
· ...............
· ...............
·.. ... .. . . . . .. ..
·....... ........
· ...............
· ...............
· ...............
·...............
350
350
350
350
350
350
350
350
350
350
350
350
24
24
24
24
24
24
24
24
24
24
24
24
7)
7)
7)
7)
7)
7)
7)
7)
7)
7)
7)
7)
Binary ROMs 1+ 5 Volts)
Organization
Part Number
Access Time
(ns max)
No. of Pins
1024 x 8
1024 x 8
1024 x 8
MCM68A308P · ..............
MCM68A308P7 · .............
MCM688308P · ..............
350
350
250
24
24
24
2048 x 8
2048 x 8
2048 x 8
MCM68A316AP · . . . . . . . . . . . . .
MCM68A316EP · .............
MCM68A316P91 .............
350
350
350
24
24
24
4096 x 8
4096 x 8
MCM68A332P · ..............
MCM68A332P2 · .............
350
350
24
24
8192x8
8192x8
8192x8
8192x8
8192x8
8192x8
8192x8
8192x8
MCM68A364P ·
MCM68A364P3
MCM688364P ·
MCM68365P25
MCM68365P35
MCM68366P25
MCM68366P35
MCM68766C45
..............
· .............
.............
· .............
· .............
· .............
·.............
· .............
350
350
250
250
350
250
350
450
24
24
24
24
24
24
24
24
~
CMOS ROMs (+ 5 Volts)
Organization
Part Number
Access Time
(ns max)
No. of Pins
256 x 4
2048 x 8
2048 x 8
MCM14524 · ................
MCM65516C43 · . . . . . . . . . . . . .
MCM65516C55 · . . . . . . . . . . . . .
1200
430
550
16
18
18
See Notes on Page 1 - 2.
1-6
MEMORIES SELECTION GUIDE (continued)
PROMs
Eel PROMs
Organization
Part Number
Access Time
(ns max)
Output
No. of Pins
32 x 8
256 x 4
MCM10139 · . . . . . . . . . . . . . . . .
MCM10149 · ................
20
25
ECloutput
ECloutput
16
16
Part Number
Access Time
(ns max)
Output
No. of Pins
512 x 8
512x 8
MCM7640 · .................
MCM7641 · .................
70
70
Open Collector
3·State
24
24
1024 x 4
1024 x 4
MCM7642 · .................
MCM7643 · .................
70
70
Open Collector
3·State
18
18
1024 x 8
1024 x 8
MCM7680 · .................
MCM7681 · .................
70
70
Open Collector
3·State
24
24
2048x4
2048 x4
MCM7684* · ................
MCM7685* · ................
70
70
Open Collector
3·State
18
18
2048 x4
MCM7688* · ................
-
Open Collector
with Registers
20
2048x 4
MCM7689* · ................
-
3·State
with Registers
20
2048:-< 8
MCM76161* ................
70
3·Stete
24
TTL PROMs
Organization
See Notes on Page 1-2.
1- 7
Memory Systems Board Selector Guide and Cross Reference
DEC
COMPUTERS
MOrOROLA
PART NUMBER
MEMORY SIZE
81< ' 16
16K .. 16
• LSI 11
lSI 11.02
lSI 11,23
J2K " 16
64K " 16
i28K • 16
POP 11,03
(Q Bus Plus
SIOI)
16K '<
32K •
4f:\K ,
64K •
16K·
32K "
46K •
64K •
\MUOBUS
SPC 5101)
• PDP·11104
PDP 11134
POP·ll-'60
lMudbus
51011
• POP·lli04
poP·' 1/34
PDP·11160
(Mudbus
-'
I
ex>
~
I
PDP·11170
(Add· In)
,VAX 11/780
Memo
SUB·
~YSTE~ slOl1
CM5004616
CM5004632
MK 8005-03
MK BOOH2
MK B005-00
MONOLITHIC
SYSTEMS
PART NUMBER
DATARAM
PART NUMBER
PLESSEY
PART NUMBER
OR· 1155
DR-115S
DR·115S
PM·$V32AII03
M$C4601 16K· 16
NATIONAL
PART NUMBER
MSC4601 32K • 16
NS23P
MK BOOI-02
MK BOOI-Ol
MK B001-00
MK BOil 02_
MMS1117·~2PC
MMS1128P~016
32K • lB
48K • 18
64K " 18
96K, 18
MMS 1128P >< 032
MMS 1128P" 048
• MMS lI2BP" 064
tMMS112BP,,096
32K , lB
MMS1119P,032
18
18
18
18
18
PM-$V32A.l00
MSC4604 321< • 18
PM·$VJ2AP, 103
PM·$V3;>AP·102
PM·$v)2AP, 100
OR·115S
QA-l1JS
MMS1117· ·8
16
NS1L)4·16
N$11134-32
MSC3503
MSC3503
MSC3503
MSC3503
16K.
32' •
48' •
64K •
16
16
16
16
CM-503H32
eM-5034648
CM503HM
MK 6011·01
NS11!J4P·16
NSI L34P·32
MSCJ605 16K.
MSCJ605 32K •
MSC3605 48K :0
MSC360564K '
i8
18
18
18
MK 8011·00
NS1'.34P·16
NSl1·34P·32
MK 8011·02
MK B01 1·01
CM-503H32
MS11·LA
CM·5034·848
MSllL8
MK B012-00
MSC3606
DR·' 14$
DR-114S
DR·114$
DR·114S
OR·114S
OR·114S
OR 114S
QR·114S
MSL3606 32'. IB
MSCJ606 48K. 18
MSCJ606 128K • 18
16K, 1B
OR·114S
OR-114S
OR-114S
OR·114S
OR·114S
MSC3606
MSC3606
MSC3606
MSC3606
OR·114S
l)R·114S
DR·114S
DR·114S
MS11·LC
CM5034-832
CM-S034BM
MSll·LA
MS1'-I.B
MS1'-lC
MS11·LO
MMS1119P,,064
MMS1119P,,096
MMSI119P.128
MK 8012-03
NS1l134Q
~S' );34Q
NS1'i34Q
MK 8012·02
MK 8012·01
MK B012-00
32K·
6"·
96K·
128K •
IB
18
18
18
+ DEC. LSI-l1. PDp·1'. and VA"J..·111780 are
trademarks 01 Dlgrtal EQUipment Corp
PINCOMM IS a reglsterea trademark 01 Trendala
Standard MemOries
· PIIIICOMM
PINCOMM
PINCOMM
PINCOMM
PINCOMM
PINCOMM
PINCOMM
?INCOMM
P$
PS
PS
PS
PS
PS
PS
PS
94234 16
94234·j2
· PINCOMM
PINCOMM
PINCOMM
PINCOMM
PS
PS
PS
r'S
94134 32
9413464
· PINCOMM PS
PINCOMM PS
PM·S1164,10?
PM-S1164ilOl
PM·S 1164,100
94('34 16
IJ4i 34·3.'
PM·S 1164A, 102
PM·S11G4A1101
PM·S 1164AI100
PM·S IlL, 100
PM·SIIL,IOO
PM·S I ll/lOG
PM·Sl1LIIOO
PM-Sl1l,100
PM-S 11 L, 100
94134128
-MMS1119Px256
'MMS1119P ,512
- PINCOMM
70S
MMS " 70E 1064
I
MMS7BOAE1032
I
MS7BO-DA
IMB2101
MK 8016·01
I
I
NS 7BO
I
I
MSC 3610
I.
DR·I ?8S
I
I
t Populated With 32K RAMS
• Populated With 64K RAMS
)( "" 3 lor fast speed
x "'- 4 lor standard speed
PIPC· Parity .. Controller ehmmales Ihe need tor
DEC s 7850 controller
9412].:6
9411332
PM·$V32A,102
OR·l1S$
MSC4604 16K· 18
NS23P
MMSI117·~6
16K .. 18
STANOARO
MEMORIES
PART NUMBER
OR·II3S
MM$1117·
lB
CDC
PART NUMBER
oR-II3S
oR-113S
OR·115S
MK B005-14
MK 8005-12
MK 8005-10
CM 5004-B16
CM5004 Bl2
~ 2
MMSI117·~4
16
16
16
16
16
16
32K , 72
MSV11-EC
MSV11·EB
M$Vl '·Eo
MM$1102·34PC
32Kd9
I
M$Vl1·DD
MOSTEK
PART NUMBER
MMS1132
MMS1132
MMS1117· ·4PC
MMS1117··6PC
MMS1117· ,8PC
(,4K,,96K \(
12BK "
:?56K x
512K x
SIOI)
MSV11·BG
MSVll-DC
MMSll0nlPC
MMSll0n2PC
BK • 18
16K· IB
O~. 10.34.
35_ 40 45
50 55 60
MMSll02-31
MMS 1122N3032
MMSlli2N30)4
MMS 1132
INTEL
PART NUMBER
MMS1132
J2K ~ It!
64K '> 18
128K • 18
• pop 11,04
DEC
PART NUMBER
PINCDMM
7BOS
I
NOll IHIS ODCUMENI 15 INTENDED AS AN AID
10 OUR CUSTOMERS IN SELf CliNG IHE
PROPER ADO· IN
M~MORY
BOARO W[
RECOMMEND THAT THE OATASHEEI &
INTEL
MICROCOMPUTfRS
!-Isac S0110.
BO/20
86/12
, (MULTIBUSI
MDS Development
System
SYSTEM 80
+ISBC aO/l0.
80/20
t MOS Development
MEMORY
SIZE
MOTOROLA
PART
NUMBER
INTEL
PAR)
NUMBER
NATIONAL
PART
NUMBER
CHRISLIN
PART
NUMBER
16K,8
MMS8016
MMS8032
MMSB048
MMSB064
MMSB016P
MMS8032P
MMS804BP
MMS8064P
S8C
S8C
S8C
SBC
. 8LC
8LC
8LC
8LC
016
032
0'8
064
CI BOBO
CI BOBO
MMS80BIO-l
MMS80810
SBC 016
SBC 032
8LC 016
8LC 032
CI 80BO
CI BOBO
32K
4BK
64K
16K
32K
48K
64K
x
"
x
x
x
x
x
8
8
8
9
9
9
9
16K x 8
32K x 8
SYSTtrrlJQ
+ MUlTlBUS and rSSC are trademarks of INTEL Corp.
Ble is a trademark of NATIONAL SemI-conductorCorp
1
016
032
04B
064
J
t Compatible With limitations
rlCH~ICAL
MANUALS fOR THE
PARIICULAR BOARD 11'.1 OUESTION BE
USlD8EfORE INSIALLAIION
CI 80BO
J
-
THE OFFICIAL MOS MEMORY
CROSS·REFERENCE
From Motorola
Plrt Number
AMD
Am2708
Am2716
Am4044
Am9016
Am9114
Am91L14
Am9147
Am9208B
Am9217
Am9218
Am9232
AMI
52114
52114L
52147
54264
55101
S6508
56518
56810
S6830
s&l31A
S6831B
568332
FAIRCHILD
F16K
2114
F2708
F27081
2716
3508
F3516E
FM4027
F68B10
F88B308
F68708
FUJITSU
MB2147
MBM2716
MB4044
M88114
MB8116
MB8227
MB8308
MB8518H
.......,......'j'
I
L
R03-8316B
R03-9316B
R03-9332C
R03-9384B
Orglnl•• llon
o..crlpllon
Motoroll"
Accl•• Time
(n, MIX)
Number 01
Pin,
Power
Supplle,
Motoroll Pln·to·Pln
Rlpllcemlnt
1024 x 8 EPROM
2048 x 8 EPROM
4096 x 1 5RAM
16,384 x 1 DRAM
1024x45RAM
1024x45RAM
4096 x 1 5RAM
1024x85ROM
2048x85ROM
2048x85ROM
4096x85ROM
300·450
450
200-450
150·300
200·450
200·450
55-85
350
350
350
350
24
24
18
16
18
18
18
24
24
24
24
+12, :5V
+5V
+5V
+12, :5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
MCM2708
MCM2716
MCM66L41
MCM4116
MCM2114
MCM21L14
MCM2147
MCM68A308
MCM68A316A
MCM68A316E
MCM68A332
1024 x4 5RAM
1024x45RAM
4096 x 1 5RAM
8192x85ROM
256x45RAM
1024 x 1 5RAM
1024 x 1 5RAM
128x85RAM
1024x85ROM
2048x85ROM
2048x85ROM
4096x8 ROM
200·450
200·450
70·100
350
450-800
300·460
300·460
250·450
350
18
18
18
24
22
16
18
24
24
24
24
24
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
MCM2114
MCM21L14
MCM2147
MCM68A364
MCM5101
MCM6508
MCM6518
MCM6810
MCM68A30A
MCM68A316A
MCM68A316E
MCM68A332
16,384 x 1 DRAM
1024x45RAM
1024 x 8 EPROM
1024 x 8 EPROM
2048 x 8 EPROM
1024x85ROM
2048x85ROM
4096 x 1 DRAM
128x85RAM
1024x85ROM
1024x8 EPROM
150·300
200·450
450
300
450
350
350
120·250
250-450
250·350
450
16
18
24
24
24
24
24
16
24
24
24
+12,
+5V
+12,
+12,
+5V
+5V
+5V
+12,
+5V
+5V
+12,
4096 x 1 5RAM
2048 x 8 EPROM
4096 x 1 5RAM
1024x45RAM
16,384 x 1 DRAM
4096 x 1 DRAM
1024x85ROM
1024 x 8 EPROM
70·100
450
200·450
200-450
150-300
120·250
350
450
18
24
18
18
16
16
24
24
+5V
+5V
+5V
+5V
+12, :5V
+12, :5V
+5V
+12, :5V
MCM2147
MCM2718
MCM8841
MCM2114
MCM4116
MCM4027A
MCM88A308
MCM2708
2048 x
2048 x
4096 x
8092 x
350
350
24
24
24
24
+5V
+5V
+5V
+5V
MCM88A316A
MCM88A316E
MCM88A332
MCM88365-35
8
8
8
8
5ROM
5ROM
5ROM
5ROM
350
350
350
350
350
1-9
:5V
:5V
:5V
:5V
:5V
MCM4116
MCM2114
MCM2708
MCM27A08
MCM2716
MCM68A308
MCM68A316E
MCM4027A
MCM88Bl0
MCM88B308
MCM88708
Part Number
Organization
Deecrlptlon
~
Motorola'.
Acca.. Tlma
(na Max)
T
---~---------.
Number 01
Pin.
Power
Supplle.
Motorola Pln·to·Pln
Replacemenl
-
HARRIS
6501
6506
6514
6518
256)(4 SRAM
1024)( 1 SRAM
1024)(1 SRAM
1024)( 1 SRAM
450-800
300-460
200·450
300-460
22
16
18
18
+5V
+5V
+5V
+5V
MCM5101
MCM6506
MCM65114
MCM6518
HITACHI
HM4334P
HM435101
HM462316EP
HM462532
HM462708
HM462716
HM46332
HM46364
HM468Al0
HM46830
HM471/1
HM472114A
HM46016
HM4616
HM4647
HM4664
HM6116P
HM6147P
HM6146P
1024)(4 SRAM
256 )( 4 CMOS SRAM
2046)(8 SROM
4096 )( 8 EPROM
1024)( 8 EPROM
2048)(8
4(96)(8 SROM
8192)(8 SROM
128)(8 SRAM
1024)(8 SROM
16,364 )( 1 DRAM
1024)(1 SRAM
2048)( 8 EEPROM
16,364 )( 1 DRAM
4096)( 1 SRAM
65,536 )( 1 DRAM
2046)( 8 CMOS SRAM
4096)( 1 CMOS SRAM
1024)(4 CMOS SRAM
300·450
18
22
24
24
24
24
24
24
24
24
16
18
24
16
18
16
18
18
18
+5V
+5V
+5V
+5V
+5V
+5V
+5 V
+5V
+5V
+5V
+12, <:5 V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
MCM65114
MCM5101
MCM68A316E
MCM2532
MCM2708
MCM2716
MCM68A332
MCM68A364
MCM68Al0
MCM68A30A
MCM4116
MCM2114
MCM2816
MCM4517
MCM2147
MCM6665
MCM65116
MCM65147
MCM65148
INTEL
2114
2114L
2115A
2115AL
2115H
2117
2118
2125A
2125AL
2125H
2147
2147H
2146
2146H
2149H
2308
2316A
2316E
2332
2708
2708·1
2716
2716-1
2816
1024)(4 SRAM
1024)(4 SRAM
1024)( 1 SRAM
1024)( 1 SRAM
1024)(1 SRAM
16,364)( 1 DRAM
16,364 )( 1 DRAM
1024)( 1 SRAM
1024)(1 SRAM
1024)( 1 SRAM
4(96)(1 SRAM
4(96)( 1 SRAM
1024)(4 SRAM
1024)(4 SRAM
1024)(4 SRAM
1024)(8 SROM
2046)(8 SROM
2048)(8 SROM
4(96)(8 SROM
1024 )( 8 EPROM
1024)( 8 EPROM
2048)( 8 EPROM
2048 )( 8 EPROM
2046)( 8 EEPROM
200·450
200-450
45-70
45-70
20-35
150-300
100-200
45·70
45·70
20·35
55·100
35·55
70·85
45·55
45·55
350
350
350
350
450
350
450
350
350
18
18
16
16
16
16
16
16
16
16
18
18
18
18
18
24
24
24
24
24
24
24
24
24
+5V
+5V
+5V
+5V
+5V
+12, <:5 V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+12, <:5 V
+12, <:5 V
+5V
+5V
+5V
MCM2114
MCM21L14
MCM2115A
MCM21L15A
MCM2115H
MCM4116
MCM4517
MCM2125A
MCM21L25A
MCM2125H
MCM2147
MCM2147H
MCM2148
MCM2148H
MCM2149H
MCM68A308
MCM68A316A
MCM68A316E
MCM68A332
MCM2708
MCM27A08
MCM2716
MCM27A16
MCM2816
INTERSIL
2114 (IM2114)
IM2147
MK4027
IM6506
IM6518
IM7027
IM2114L
IM4116
IM7141
IM7141L
1024)(4 SRAM
4(96)( 1 SRAM
4(96)(1 DRAM
1024)(1 SRAM
1024)( 1 SRAM
4(96)( 1 DRAM
1024)(4 SRAM
16,364 )( 1 DRAM
4(96)(1 SRAM
4(96)( 1 SRAM
200-450
55-85
150-250
300-460
300·460
120-250
200-450
150·300
200-450
200-450
18
18
16
16
18
6
18
16
18
18
+5 V
+5V
+ 12, <:5V
+5V
+5V
+12, <:5 V
+5V
+12, <:5 V
+5V
+5V
MCM2114
MCM2147
MCM4027A
MCM6508
MCM6518
MCM4027A
MCM21L14
MCM4116
MCM6641
MCM66L41
ITT
ITT4027
ITT4116
4(96)(1 DRAM
16,384)( 1 DRAM
120-250
150-300
16
16
+ 12, <:5 V
+ 12, <:5 V
MCM4027A
MCM4116
450·600
350
450
450
450
350
350
350
350
150-300
200-450
350
100-200
55·85
150-200
120·200
55-70
55-65
1-10
--Part Number
MIC
MIC2316E
MIC2332
0'9anl2allon
Dncrtptlon
Motorola'.
Ace••• Tim.
(n. Maxi
Number 01
Pin.
Pow.r
Suppll••
Motorol. PIMo·Pln
Replacemenl
2048 x8 SROM
4096 x 8 SROM
350
350
24
24
+5V
+5V
MCM88A318E
MCM68A332
MOSTEK
MK2147
MK2716
MK4027
MK4116
MK4516
MK4164
MK30000
MK31000
MK32000
MK34000
MK36000
MK36000·4
4096 x 1 SRAM
2048 x 8 EPROM
4096 x 1 DRAM
16,384 x 1 DRAM
16,384 x 1 DRAM
65,536 x 1 DRAM
1024x8 SROM
2048x8SROM
4096x8 SROM
2048x8 SROM
8192x6 SROM
8192x8 SROM
70·100
450
150·250
150·300
120·200
150·250
350
350
350
350
350
250
18
24
16
16
16
16
24
24
24
24
24
24
+5V
+5V
+12, .,5 V
+ 12, .,5 V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
MCM2147
MCM2716
MCM4027A
MCM4116
MCM4516
MCM6884
MCM88A308
MCM88A318A
MCM88A332
MCM88A318E
MCM88A384
MCM88B384
NATIONAL
MM2114
MM2147
MM2708
MM2716
MM5235
MM5257
MM5257L
MM5290
1024x4 SRAM
4096 x 1 SRAM
1024 x 8 EPROM
2048 x 8 [PROM
8192x8 SROM
4096 x 1 SRAM
4096 x 1 SRAM
16,384 x 1 DRAM
200-450
55-85
450
450
350
200-450
200-450
150·300
16
18
24
24
24
18
18
16
+5V
+5V
+12, .,5 V
+5V
+5V
+5V
+5V
+ 12, .,5 V
MCM2114
MCM2147
MCM2708
MCM2716
MCM88A384
MCM8841
MCM88L41
MCM4116
4096 x 1 DRAM
16,384 x 1 DRAM
1024x4 SRAM
4096 x 1 SRAM
4096x8 ROM
2048 x 8 EPROM
4096 x 1 SRAM
256x4 SRAM
1024x1 SRAM
1024x4 SRAM
1024x8SROM
150-250
150·300
200·450
55-85
350
450
200·450
450-800
300-460
200-450
350
16
16
18
16
24
24
18
22
16
18
24
+12, .,5 V
+12, :1:5 V
+5V
+5V
+5V
+5V
+5V
+5V
+5 V
+5V
+5V
MCM4027A
MCM4116A
MCM21L14
MCM2147
MCM88A332
MCM2716
MCM88L41
MCM5101
MCM6508
MCM2114
MCM88A308
2048x8 SROM
350
24
+5V
MCM88A316A
350
450
450
350
24
24
24
24
+5V
+12, .,5V
+5V
+5V
MCM88A316E
MCM2708
MCM2716
MCM88A332
128x(7x91 SROM
128x(7x91 SROM
128x(7x9j SROM
128x(7x91 SROM
128x(7x91 SROM
128x(7x91SROM
350
350
350
350
350
350
24
24
24
24
24
24
+5V
+5V
+5V
+5V
+5V
+5V
MCM88700
MCM88710
MCM88720
MCM88730
MCM88740
MCM88750
1024x8 SROM
1024x8 SROM
128x(7x91 SROM
4096 x 1 DRAM
1024x4 SRAM
2048x8 SROM
4096x8SROM
8192x8 SROM
16,384 x 1 DRAM
1024 x 8 EPROM
2048 x 8 EPROM
4096 x 1 DRAM
256x4 SRAM
350
350
350
120·250
200-450
350
350
350
250-350
450
450
150·250
450-800
24
24
24
16
18
24
24
24
16
24
24
16
22
+5V
+5V
+5V
+12,
+5V
+5V
+5V
+5V
+12,
+12,
+5V
+12,
+5V
MCM88A308
MCM88A30A
MCM88700
MCM4027A
MCM21L14
MCM88A316E
MCM88A332
MCM88A384
MCM4116
MCM2708
MCM2716
MCM4027A
MCM5101
~-
NEc/EA
,PD414A
.PD416
,PD2114L
.PD2147
,PD2332
,PD2716
,PD4104
,PD5101
,PD6508
EA2114
EA230818308
,POor
EA2316A18316A
,POor
EA2318E18316E
EA2708
,PO or EA2716
EA8332
NITRON
NC6570
NC6571
NC6572
NC6573
NC6574
NC6575
SIGNETICS
2607
2608
2609
2880
2614
2618
2633
2664
2690
2708
2716
4027
5101
2048x8
1024x8
2048 x 8
4096x8
SROM
EPROM
EPROM
SROM
1-11
.,5 V
.,5 V
.,5V
.,5 V
Motorol.'.
Accaaa Tlma
(n, MI.)
Organl.allon
Deacrlptlon
Part Number
Number of
Pin,
Pow.r
Supplll'
Motorola Pln-Io-Pln
Rapllcamenl
SYNERTEK
SY2114
SY2147
SY2316A
SY2316B
SY2332
SY2716
SY5101
TEXAS INSTRUMENTS
TMS2114
TMS2147
TMS2516
TMS2532
TMS2708
TMS2716
TMS4016
TMS4044
TMS4116
TMS4164
TMS4732
TMS4764
1024 x4 SRAM
4096 x 1 SRAM
2048x8 SROM
2048x8 SROM
4096x8 ROM
2048 x 8 EPROM
256 x4 SRAM
200-450
55-85
350
350
350
450
450-800
18
18
24
24
24
24
22
+5V
+5V
+5V
+5V
+5V
+5V
+5V
MCM21L14
MCM2147
MCM88A318A
MCM88A316E
MCM88A332
MCM2716
MCM5101
1024)(4 SRAM
4096)( 1 SRAM
2048 )( 8 EPROM
4096 x 8 EPROM
1024 x 8 EPROM
2048 x 8 EPROM
2048x8 SRAM
4096 x 1 SRAM
16,384)( 1 DRAM
65,536 )( 1 DRAM
4096)(8 SROM
8192x8 SROM
200-450
55-85
450
350-450
450
450
200
200-450
150-300
150-250
350
350
18
18
24
24
24
24
24
18
16
16
24
24
+5V
+5V
+5V
+5V
+12, ±5V
+12,±5V
+5V
+5V
+ 12, ± 5 V
+5V
+5V
+5V
MCM2114
MCM2147
MCM2716
MCM2532
MCM2708
TMS2716
MCM4016
MCM8841
MCM4116
MCM6885
MCM88A332
MCM88365
18
18
24
+5V
+5V
+5V
MCM2114
MCM2147
MCM4016
TOSHIBA
!I
I
TMM314
TMM2147
TC5516P
Part
,
,
1024x4 SRAM
4096 x 1 SRAM
2048 x 6 SRAM
I
I
200-450
55-85
200
Number Guide _________________________________________
~_. ."
OMo;, ..
7'. -"".
Directly 8800
.'"~ 7'·~"
MCM21 L 14P45
7/\
Motorola MOS
Memory Prefix
Low Power
Version
r-\
MCM68A30A
Package Type
P _ Plastic
L = Side Braze
C = Cerdip Frit-Seal Ceramic
1-12
Motorola MOS
Memory Prefl.
Access Time Designator
No Letter - ,,450 ns
A= ,;350 ns
B= ,;250 ns
MOS Memories
RAM, EPROM, EEPROM, ROM
2-1
@
MOTOROLA
MCM4027A
MOS
4096-BIT DYNAMIC RANDOM ACCESS MEMORY
IN-CHANNEL. SILICON-GATE I
The MCM4027A is a 4096 x 1 bit high-speed dynamic Random
Access Memory_ It has smaller die size than the MCM4027 providing improved speed selections. The MCM4027 A is fabricated
using Motorola's highly reliable N-channel silicon-gate technology_
By multiplexing row and column address inputs, the MCM4027A
requires only six address lines and permits packaging in Motorola's
standard 16-pin dual-in-line packages. Complete address decoding is
done on chip with address latches incorporated.
All inputs are TTL compatible, and the output is 3-state TTL
compatible. The MCM4027 A incorporates a one-transistor cell
design and dynamic storage techniques, with each of the 64 row
addresses requiring a refresh cycle every 2.0 milliseconds.
4096-BIT DYNAMIC
RANDOM ACCESS
MEMORY
-
-
I
i
" , [ I ; . i ..
•
Maximum Access Time = 120
150
200
250
ns
ns
ns
ns
-
MCM4027 AC1
MCM4027 AC2
MCM4027AC3
MCM4027AC4
•
Maximum Read and Write Cycle Time =
320 ns - MCM4027 AC 1, C2
375 ns - MCM4027AC3, C4
•
Low Power Dissipation - 470 mW Max (Activei
27 mW Max (Standbyi
•
3-State Output for OR-Ties
C SUFFIX
f-AIT·SEAL CEAAMIC PACKAGE
CASE 620-00
PIN ASSIGNMENT
Ie
•
On-Chip Latches for Address, Chip Select, and Data In
•
Power Supply Pins on Package Corners for Optimum Layout
•
Industry Standard 16-Pin Package
•
Page-Mode Capability
•
Compatible with the Popular 21 04/MK4096/MCM6604
•
Second Source for MK4027
16
VSS
15
CAS
14
Dout
RAS
13
ES
AO
12
A3
A2
11
A4
A1
10
A5
VOO
9 VC'C
Ref
Function
TRUTH TABLE
Inputs
ms;s
CAS
L
L
Data Out
L
-+-----L +-L-
I-L
L
H
Valid data
L
~__
X
H
H
X-------'__X
L----_..L_----'-___
~.
H
~
High, L
Low, X
High Imp.
Input data
Full-operating
High Im"p,
High Imp. ---- -
-F~il--~P;~-a-ti-ng--- ly,-e-'--t------rOc:ecc'e"'leCCc"'teccd:;--cc'e"f,:-:ecc'hc-----j
r--v~1id ~r---~ ~d;ta--(cell)
7-f..--'·L H X [----Valid data~==L=~:-~~H-----+__--_x-__ " r-~-= :~~Iid da~~
Cycle Power
~
~
Previous
Interim
Present
---4---~-------~--------+----------+-~---
Valid
~_
Write cycle
d~t;- ----V;Od·-,-d--:.---'t-.-----+-----=R-e-d-u-ce-'----d-o-'--p-e~'_a-t~in_~g:~~_--:_Y~e-'~_--t;~_RAS;=_A;=_r_-o~n_I--:V:-_'-e~f_,-e_,~h_=__=__=__=__=_~...,
_Validd~ __ ~_-H_'g:~h__I_m---'p_.~+___H-i~9-h-l-m'--p-.-------r __S_t._n_d_b'--v_ _ _ _ _
data
_ _Valid
___
Yes
FUII-oper-a-ti-n-g~---t---:Y--:e-s------t-----:R:-e-a--:d-c-V-cl-e-------!
Valid data
Valid
data
__
____
_~
+__N_O_I-S_t_an_d_b~V_-O_u_t~P_u_t_d_i,_ab_l_ed---!
Standby
No__'________Standby-output
_ _'______ _ _---'---_
__
_valid
__
~
~_~
~
Don't Care
OS9464R1/11-78
2-3
MCM4027A
BLOCK DIAGRAM
Write
E
Clocks
RAS Clocks
I
I
1
i
Address
Clocks
p~1
l
t
CAS
Clocks
I
•
Chip Select
I nput Buffer
1
I
Data In
Buffer
~
Data Out
-----rl-
Address
Buffers
(61
Enable
Row
AO
--
Decoder
A2
At
Data
Reset
'----
t
A3
~ataln
~
AS
A4
I
Rowand
~
Out
Dummy Calls
Memory Array
.
64 Sense Refresh Amplifiers
Data In/Out Gating
(1-of·64)
Column
Buffer
-1 t
~
-
"01· 2
Data Bus
Select
I Memory Array I
I
I
I Dummy Cells
I
Column Decoder
(1-of-32)
t
r
r
-_.
OPERATING CHARACTERISTICS
ADDRESSING
DATA OUTPUT
The MCM4D27A has SIX address Inputs (AD-A5) and
two clock signals designated Row Address Strobe (!'!AS)
and Column Address Strobe (CAS), At the beginning of
a memory cycle, the six low order address bits AD through
A5 are strobed into the chip with RAS to select one of
the 64 rows. The row address strobe also initiates the tim·
ing that will enable the 64 column sense amplifiers. After
a specified hold time, the row address is removed and the
six high order address bits (A6-A 11) are placed on the
address pins. This address is then strobed into the chip
with CAS. Two of the 64 column sense amplifiers are
selected by A 1 through A5. A one of two data bus select
is accomplished by AD to complete the data selection.
The Chip Select (CS) is latched into the port along with
the column addresses.
In order to simplify the memory system designed and
reduce the total package count, the MCM4D27A contains
an input data latch and a buffered output data latch. The
state of the output latch and buffer at the end of a memo
ory cycle will depend on the type of memory cycle per·
formed and whether the chip is selected or unselected for
that memory cycle.
A chip will be unselected during a memory cycle if:
(1)
The ch ip receives both R AS and CAS signals,
but no Chip Select signal.
(2)
The chip receives a CAS signal but no tiAS
signal. With this condition, the chip will be
unselected regardless of the state of Chip
Select input.
If, during a read, write, or read·modify·write cycle,
2-4
MCM4027A
INPUT/OUTPUT LEVELS
the chip is unseleeted, the output buffer will be in the
high impedance state at the end of the memory cycle.
The output buffer will remain in the high impedance state
until the chip is selected for a memory cycle.
For a chip to be selected during a memory cycle, it
must receive the following signals: RAS, CAS, and Chip
Select. The state of the output latch and buffer of a
selected chip during the following type of memory cycles
would be:
(1)
All of the inputs to the MC1V!4027 A are TTL-compatible,
featuring high impedance and low capacitance (5 to 7 pF).
The three·state data output buffer is TTL-compatible and
has sufficient current sink capability (3.2 mAl to drive
two TTL loads. The output buffer also has a separate
VCC pin so that it can be powered from the same supply
as the logic being employed.
REFRESH
Read Cycle - On the negative edge of CAS,
the output buffer will unconditionally go to a
high impedance state. It will remain in this
state until access time. At this time, the out·
put latch and buffer will assume the logic
state of the data read from the selected cell.
This output state will be maintained until the
chip receives the next CAS signal.
(2)
Write Cycle - If the WE input is switched to a
logic 0 before the CAS transition, the output
latch and buffer will be switched to the state
of the data input at the end of the access time.
This logiC state will be maintained until the
chip receives the next CAS signal.
(3)
Read·ModifyWrite - Same as read cycle.
In order to maintain valid data, each of the 64 internal
rows of the MCM4027 A must be refreshed once every 2 ms_
Any cycle in which a FfAS signal occurs accomplishps a
refresh operation.
Any read, write, or read-modify-write
cycle will refresh an entire internally selected row_ However, if a write or read-modify-write cycle is used to perform a refresh cycle the chip must be deselected to prevent writing data into the selected cell. The memory can
also be refreshed by employing only the RAS cycle_ This
refresh mode will not shorten the refresh cycle time; however, the system standby power can be reduced by approximately 30%.
If the RAS only refresh cycles are employed for an extended length of time, the output buffer may eventually
lose data and assume the high impedance state. Applying
CAS to the chip will restore activity of the output buffer.
POWER DISSIPATION
DATA INPUT
Since the MCM4027A is a dynamic RAM, its power
drain will be extremely small during the time the chip is
unselected.
The power increases when the chip is selected and
most of this increase is encountered on the address
strobe edge. The circuitry of the MCM4027A is largely
Data to be written into a selected storage cell of the
memory chip is first stored in the on-chip data latch.
The gating of this latch is performed with a combination
of the WE and CAS signals. The last of these signals to
make a negative transition will strobe the data into the
latch_ If the WE input is switching to a logic 0 in the
beginning of a write cycle, the falling edge of CAS strobes
the data into the latch. The data setup and hold times
are then referenced to the negative edge of CAS.
If a read-modify-write cycle is being performed, the
WE input would not make its negative transistion until
after the CAS signal was enabled. Thus, the data would
not be strobed into the latch until the negative transistion
dynamic so power is not drawn during the whole time
the strobe is active. Thus the dynamic power is a function
of the operating frequency rather than the active duty
cycle.
In a memory system, the CAS signal must be supplied
to all the memory chips to ensure that the outputs of
the unselected chips are switched to the high impedance
state_ Those chips that do not receive a RAS signal will
not dissipate any power on the CAS edge except for that
required to turn off the chip outputs_ Thus, in order to
ensure minimum system power, the RAS signal should be
decoded so that only the chips to be selected receive a
RAS signal. If the RAS" signal is decoded, then the chip
select input of all the chips can be. set to a logic 0 state.
of Wf'.. The data setup and hold times would now be referenced to the negative edge of the WE signal. The only
other timing constraints for a write-type-cycle is that both
the CAS and WE signals remain in the logic 0 state for a
sufficient time to accomplish the permanent storage of
the data into the selected cell.
Circuit diagrams external to or containing Motorola products are Included as a means of Illustration only. Complete information
suffiCient for construction purposes may not be fully illustrated. Although the information herein has been carefully checked and IS believed
to be reliable, Motorola assumes no responsibility for inaccuracies. Information herp.1n does not convey to the purchaser any license under
the patent fights of Motorola or others.
The information contained herein is for guidance only, with no warranty of any type, expressed or Implied. Motorola reserves the nght
to make any changes to the Information and the product(s) to which the information applies and to discontinue manufacture of the
product(s) at any time
2-5
MCM4027A
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted.)
RECOMMENDED OPERATING CONDITIONS IReferenced
Parameter
to VSS" Ground I
Notes
Symbol
Min
Typ
Ma.
Unit
VDD
10.8
12.0
13.2
Vdc
2
VCC
VSS
5.0
VDD
Vdc
3
2
Supply Voltage
VSS
0
0
0
Vdc
VSS
-4.5
-5.0
-5.5
Vdc
2
Logic 1 Voltage, RAS, CAS, WRITE
VIHC
2.4
5.0
7.0
Vdc
2,4
Logic 1 Voltage, all inputs except RAS. CAS, WR ITE
VIH
2.2
5.0
7.0
Vdc
2,4
Logic 0 Voltage, all inputs
VIL
-1.0
0
0.8
Vdc
2.4
DC CHARACTERISTICS
IVDD
12 V '10% Vce
Characteristic
c
50 V '10% VSS
Average VOO Power Supply Current
Vee
Vas
-50 V '10% VSS = 0 V T A - 0 to 70 0 C.1 Notes 1, 5
Typ
Min
IDDl
Power Supply Current
Average
=
Symbol
Ma.
Units
Notes
35
mA
6
mA
7
ICC
Power Supply Current
ISS
250
~A
Standby VOO Power Supply Current
IDD2
2
mA
9
Average VOO Power Supply Current during
IDD3
25
mA
6
Input Leakage Current (any input)
IIiLI
10
~A
8
Output Lea kage Current
IOILi
10
~A
9.10
Output Logic 1 Voltage @ lout -'- -5 mA
VOH
Output Logic 0 Voltage @ 'out'" 3.2 mA
VOL
--
"RAS only" cycles
Vdc
2.4
Vdc
0.4
NOTES 1 through 11:
t. TA is specified for operation at frequencies totRC'?- tRc(minl.
Operation at higher cycle rates with reduced ambient temperatures
6. Current IS proportional to cycle rate.
1001 {maxI
is measured
at the cycle rate specified by tRc(minl.
and higher power disSipation IS permiSSible prOVided that all ac
7.
parameters are met.
data VCC is connected through a low Impedance (135
2. All voltages referenced to VSS.
Data Out. At all other times ICC consists of leakage currents only.
3. Output voltage Will swing from VSS to VCC when enabled,
with no output load. F or purposes of maintain 109 data 10 standby
8. All dev;ce pins at 0 volts except VSS which is at -5 volts and
mode, VCC may be reduced to VSS without affecting refresh
operations or data retention. However, the VOH(mlnl specifica·
9. Output is disabled (high-impedance) and RAS and CAS are
tion is not guaranteed in thiS mode.
measurement of thiS parameter.
the pin ul1der test which is at
both at a logic
4. Device speed IS not guaranteed at input voltages greater than
cycles
are
11.
requ Ired
after
power-up
volts.
1. Transient stabilization is required prior to
Effective capacitance is calculated from the equation:
c ==- t;V
6.0 with 6.V
= 3 volts.
(Full operating voltage and temperature range, periodically sampled rather than 100% tested) Note
Characteristic
Input Capacitance
typ) to
before proper
device operation is achieved. Any 8 cycles which perform refresh
are adequate for this purpose.
EFFECTIVE CAPACITANCE
+10
n
10.0V" VO u , " +10V.
TTL levels (0 to 5 v).
5. Several
ICC depends on output loading. During readout of high level
lAO-AS). D;n. CS
11
Symbof
Ma.
Unit
C;nIEFF)
5.0
pF
RAS, CAS, WRITE
10.0
Output Capacitance
CoutIEFF)
7.0
pF
ABSOLUTE MAXIMUM RATINGS (See Notes 1 and 2)
Rating
Voltage on Any Pin Relative to VBS-
Svmbol
V IO ' V out
Value
-0.5
'0 +20
Unit
Vdc
TA
o to +70
Storage Temperature Range
T stg
-65 to +150
°c
Output Current (Short CtrCUlt)
lout
50
mAdc
Operating Temperature Range
• (V •• - V ..
°c
> 4.5 V)
NOTE: Permanent deVice damage may occur of ABSOLUTE MAXIMUM RATINGS
ARE EXCEEDED. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages
for e)(tended periods of time could affect deVice reliability. VSS must be applied
prior to Vec and VOO. VBS must also be the last power supply switched off.
2-6
ThiS deVice contains CirCuitry to protect the
Inputs agamst damage due to high static voltages or electriC fields: however, It IS adVised that
normal precautions be taken to aVOid appllcatlon of any voltage hIgher than ma)(lmUm rated
voltages to tt-:IS high Impedance C!fCUlt
MCM4027A
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Read, Write, and Read-Modify-WriteCycles)
RECOMMENDED AC OPERATING CONDITIONS
IVDD"'2 v' '0%, vee' 5.0 v' '0%,
to 70 0 e) Notes " 5, '2,'B
'JBB
-5.0
v,
'0%, VSS
a V,
TA "0
P.rlmeter
Symbol
MCM.a27AC'
Min
M ••
Random Read or Write Cvcle Time
'AC
Read Write Cycle Time
Paae Mode Cvcle Time
AWC
PC
Access Time From Row Address SHobe
'RAe
120
Access Time From Column Address Strobe
'CAe
so
Output Buffer and Turn-Off Oelay
'OFF
'AP
Row Address Strobe Precharge Time
Row Address Strobe Pulse Width
'RAS
Aow Address Strobe Hold Time
'ASH
Column Address Strobe Pulse Width
Column Address Strobe Hold Time
'CAS
'CSH
Row to Column Strobe Lead Time
'ReO
Row Address Setup Time
'ASA
Row Address Hold Time
'RAH
C tumn AdOress Setup Time
'ASC
'CAH
Column Address Hold Time
Column Address Hold Time Referenced to ~
ChiD Select SetuD Time
ChiD Select Hold Time
Chip Select Hold T,me Referenced to
TranSition Time Rise and Fall
Read Command SetuD Time
Read Command Hold Time
Write Command Hold Time
Write Command Hold Time Referenced to
Write Command Pulse Width
Write Command to Row Strobe Lead Time
'csc
'CH
m
'CHA
'T
'ACS
IACH
m
Wnte Command to Column Strobe lead Time
Data In Setup Time
Data In Hold Time
Data In Hold Time Referenced to ~
Column to Row Strobe PrecharAe Time
Column Precharge Time
Refresh Period
Wnte Command Setup Time
~ to WIIITl' Del.,
RAS to wmTt Delay
Data Out Hold Time
NOTES 12
through
'AA
WCH
'WCA
'WP
'AWL
'CWL
'OS
'DH
'OHR
'CRP
'CP
'AFSH
'WCS
'CWO
'AWD
'DOH
MCM.a27AC2
Min
M ••
320
320
160
10,000
100
150
100
100
10,000
150
40
20
0
20
·10
45
95
50
45
95
3
0
0
45
95
45
50
50
0
45
95
0
60
35
a
40
80
40
50
50
0
40
80
0
60
200
135
50
2
120
200
135
135
200
25
0
25
0
60
110
10
65
55
3
0
0
55
3
0
0
75
ns
ns
ns
ns
85
ns
n<
ns
ns
ns
n<
ns
50
ns
,8
n<
ns
ns
160
55
70
70
0
55
75
85
85
0
75
120
160
ns
0
80
0
110
ns
2
17
ns
120
0
80
145
10
"
'4 '6
'5, '6
n.
160
50
ns
ns
·10
75
120
'3
,3
ns
10,000
160
·10
35
35
0
35
10
75
Not ..
ns
ns
250
'65
60
120
250
165
165
Unit.
ns
250
55
120
2
0
60
100
10
10,000
·10
·10
MCM.a27AC4
Min
M ..
375
375
2B5
225
'50
100
40
35
100
120
80
BO
120
15
0
15
5
40
BO
0
40
80
3
0
MCM.a27AC3
Min
M ••
375
375
320
320
'70
ns
ns
ns
ns
ns
ns
,.
19
ns
2
0-
90
175
10
ms
nc
n<
,n
ns
20
/IS
18.VIHc(min) or VIH(min) and VIL(max) are reference levels for
measuring timing of input signals. Also, transition times are
20:
12. AC measurements assume tT = 5 ns.
measured between VIHC or VIH and VIL.
13. The specifications for tRc(min) and tRwc(mln) are used only
to indicate cycle time at which proper operation over the full
temperature range (O°e .,,; T A ~ 70 0 e) is assured.
19. These parameters are referenced to CAS leading edge in
random write cycles and to WRITE leading edge in delayed write
or read-modify write cycles.
14.Assumes that tACO"'; tRCO(max).
100 pF,
20. twcs, tewD, and tAWD are not restrictive operating parameters. They are included In the data sheet as electrical characteriSltcs only: If twcs ~ twcs(minl. the cycle is an early write
cycle and Data Out will contain the data written into the selected
17.0peration within the tRCO(msx) limit Insures that tRAc(max)
can be met. tRCO(max) is specified as a reference point only~ If
cell. If tCWD ~ tcwo(min) and tRWD ~ tAWD(minl, the cycle is
a read-write cycle and Data Out will contain data read from the
tRCD is greater than the specified tRco(max) limit, then access
time is controlled exclusively by tCAC'
selected cell. If neither of the above sets of conditions is satisfied,
'the condition of Data Out (at access time) is indeterminate.
15. Assumes that tRCD ~ tACO (max).
16. Measured With a !oad CirCUit equivalent to 2 TTL loads and
2-7
MCM4027A
READ CYCLE TIMING
1+
1
,1---
; i--
AAS
V1HC
V IL
------1'1
'AC
"'-'AA .. -
IRSH----~----..
tCSH
I f.-.. --- tRCO---·
CAS
V,L
ADDRESSES
,
----I
:
i /'-------+---t---------.J i
i I
VIHC
-. -------+1
tAAS
.. -------tCAS -
:;
.r----
--.-~ 14----
•
tCAP
Yr
'--_+--_ _ _---.JI
V,H
V'C
I
1
II
'ACS-j.--.j
!
Dout
2-8
-.-J,
AC H
j
tAPi
1----
------1
MCM4027A
WRITE CYCLE TIMING
r-- -:
AAS
~-~--.-.
1
tAR
VI~~----------'~~__________________________________-J~
!
V
~---tR-C-D---------:-;t+~-"'C:;. ~;;f<<-.:;=:::~:-'-~R~:~SH. -~-~:.
t
te : :
~~~ -------ir-1i------'-----~~~______________~/..-'- - - - - - - - -
i
~ tAAH
tAsA---k--·...i~·
-.~ lAse--;'..., ;"tCAH'"
ADDRESSES
~',: ~ A:d~;" ~ ;~~,:s~ ~~«~'--IWCS i_________ ;... tWCH...j
....
"twp
..
V~H,~.~::>.L::..A-""_LLj<'~,----",--+-I-----t-r-_---4--"m~~~,~'I_L:~.A..-~~~,.
;,.L.'
L.- .
!'
..- tRWL
-
tWCR'
..,
;
r--.... -- --- ,. . -tOHA----;--·
:
cs
tcsc--r
f4--tCH
V~~L"'-"'~:-Jr1i.~,
~~.---.:7":~,\'
.
-i
t'~<>z=="""~Y
DO ut
Write
PAGE MOOE WRITE CYCLE
RAS
CAS
VIH Addresses V JL -
cOs
DOUT
Wnte
D,n
2-11
Row Addresses
s:
s:
Columns
A A A A A A
He.
5 4 3
L
3'
3F
3D
3C
3A
38
39
38
36
37
35
34
32
33
31
30
H
L
2'
2F
20
2C
2A
28
29
28
26
27
n
2 1 0
0
8
H
H
L
H m
L
H
H
L
L
L
L
H
H
L
L
L
H
H
L
H
L
H
L
L
H
L
L
H
H
L
L
H
H
L
H
L
H
L
L
H
L
H
L
H
H
l
L
H
H
L
H
L
H
£
L
L
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
'"
0
'"
um "m
u
o
u
~
0
u
m m
~
~
'"m u'"m
u
0
~
~
u
m
»
H
H
u
0
u
"
u
u
u
0
0
0
;;
u
'"m '"m
0
~
~
~ ~
0
U
0
U
0
o
0
o
~
o
u
0
u
8
0
'"o u'"0
o
u
~
0
u
0
~
'" u'"
u
o
~
0
~
~
0
u
0
~
'"m '"-
0
'"o 0'"
0
~
~
~
~
~
25
2'
22
23
21
20
~
....,
n
~
0
"
~
'"
L
L
L
L
H
H
H H
H
1F
10
1C
1A
18
19
18
16
N
~
H
~
III
:;
~
C
C
m
H
L
L
L
H
H
L
L
H
L
L
H
H
L
L
H H
L
H
L
17
15
14
12
13
"
~
~
L
H
11
~
10
OE
OF
00
H
L
L
L
H
H
L
L
H
H
L
m
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
L
L
H
L
L
H
H
H
L
L
H
H
L
L
~ ~
m m
~
0
~
0
~
~ ~
m m
~
~
~
'"m '"m
0
3
0
g
U
0
'"~ ;;'"
u
0
m
'"om '"m
0
U
g
0
U
~
o
u
~
~
~
'"o '"0
0
~
0
o 0
o 0
m m
0
U
'"oo 0'"0
rrxxrrIIrrXIrrrr
~
0
0"
3 •
, t
....
....
»
o
o
o
rrJ:rrrxxr~IxrrXI
~
0
0
0
~
~
~
'"om '"0m
»
"''''
»
"» "
......
»
~
0
"''''
0
~~
~
»
0
0
00
m
~
'"oo '"00
0
0
0
rrrIrrIxrrXIrrXI rrXIrrIIrrIIrrII
"'>
,,>
r r I I r r I I r r X I r r I I x x r r I I r r x x r r X I r r r r I r r r x x r r X I r r I I I I r r l : x r r I I r r X I r r WJ-
/
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;;;
r r X I r r I I r r x x r r r I r r I I r r : r I r r x x r r I X ::::IrrIIrrxxrrxxrr I I r r x x r r I I r r I x r r
~D
.
~
0
n
H H L a
H H
DC
OA
08
09
08
06
07
05
04
02
03
01
00
L 0
H ~
~ ~
rrIrrrIIIl:rrIl:rr r,IxrrIIxxrr::::Irr rrIIrrIIIxrrIIrr rrIIrrIIIxrrIIrr
i'oJJ-
Ir r I I I I r r r r I I X I r r r r I I I I r r r r I I I I r r r r X I I I r r r r I I I I r r r r I I I X r r r r I I I I r r
- J-
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Ig~~~S8~~ ~g~~a: 8~~Ia:g~~~~~~g g~ t:~~<:~Ic;::: ~~;; w~ ~ ;u;ri:~a; ~~~Ia;~ ~~; iii ~~;:;o ~~;;; ~ ~~I :=
n
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iii
~
MCM4116B
.,
,
16.384-BIT DYNAMIC RANDOM ACCESS MEMORY
MOS
The MCM4116B is a 16.384-bit. high-speed dynamic Random
Access Memory designed for high-performance. low-cost
applications in mainframe and buffer memories and peripheral
storage. OrganIZed as 16.384 one-bit words and fabricated using
Motorola's highly reliable N-channel double-polysilicon technology.
this device optimizes speed. power. and density tradeoffs.
By multiplexing row and column address inputs. the MCM4116B
requires only seven address Itnes and permits packaging in
Motorola's standard 16-pm dual in-line packages. This packaging
technique allows high system density and is compatible with widely
available automated test and insertion equipment. Complete
address decoding IS done on chip with address latches incorporated.
All inputs are TIL compatible. and the output is 3-state TIL
compatible. The data output of the MCM4116B is controlled by the
column address strobe and remains valid from access time until the
column address strobe returns to the high state. This·output scheme
allows higher degrees of system design flexibility such as common
input/output operation and two dimensional memory selection by
decoding both row address and column address strobes.
The MCM411 6B mcorporates a one-transistor cell design and
dynamic storage techniques. with each of the 128 row addresses
requiring a refresh cycle every 2 milliseconds.
•
IN-CHANNELl
16.384-BIT DYNAMIC
RANDOM ACCESS
MEMORY
P SUFFIX
PLASTIC PACKAGE
CASE 648
C SUFFIX
FRIT-SEAL CERAMIC PACKAGE
CASE 620
Flexible Timmg with Read-Moaify-Write. RAS·Only Refresh. and
Page-Mode Capability
•
Industry Standard 16-Pin Package
•
16.384 X 1 OrganIZation
PIN ASSIGNMENT
VBB
0
RAS 4
• All Inputs are Fully TIL Compatible
• Three·State Fully TIL-Compatible Output
•
Common 1/0 Capability When Using "Early Write" Mode
• On-Chip Latches for Addresses and Data In
• Low Power Dissipation -
ns
ns
ns
ns
-
MCM4116BP-15.
MCM4116BP-20.
MCM4116BP-25.
MCM4116BP-30.
BC-15
BC-20
BC-25
BC-30
Operating Temperature Range
Symbol
Value
Unit
Vin, Vout
-0.5 to +20
V
TA
o to +70
°c
°c
T stg
-65 to +150
Power Dissipation
Po
1.0
W
Data Out Current
lout
50
mA
Storage Temperature Range
13 A6
AO
,
A2
6
It
Al
I
10 pA5
VOO
8
9 PVCC
t2 pA3
pA4
. ... Address Inputs
. Column Address Strobe
.......................... Oata In
................ Dat. Out
Q ......
~.
. ... Row Address Strobe
W ......................... Read/Write Input
ABSOLUTE MAXIMUM RATINGS ISee Notel
Voltage on Any Pin Relative to VBB
CAS
14 Q
PIN NAMES
AD·A6 ..
CAS
0
Easy Upgrade from 16-Pin 4K RAMs
Rating
VSS
15
463 mW Active. 20 mW Standby(Max)
• Fast Access Time Options:150
200
250
300
•
2
W 3
±10% Tolerance on All Power Supplies
•
IeV"i6
NOTE Permanent deVice damage may occur if ABSOLUTE MAXIMUM RATINGS c:re exceeded. Functional operation should be restncted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could a1fect device reliability
VBB··
VCC·
VOO
VSS
. .Power I - 5 V)
.. Power
(+
5 Vl
.......... Powerl+12V)
...
Ground
This deVice contains circuitry to protect the
Inputs against damage due to high static volt-
ages or electric fields; however. it is advised that
normal precautions be taken to avoid application of any voltage higher than maximum rated
voltages to this high Impedance cirCUit.
D59006/10-79
2-13
MCM4116B
BLOCK DIAGRAM
4--- _ _
V OD
......... --- --vee
WRITE-------------------
......----VS$
'---VaB
r---r=~==;----
Data In
o
A6
--------------1
AS
--------------1
A4
--------------1
A2
--------------1
___D_u_m_m_y_C~._"~S______1
Memory Array
128 - Sense
Memory
Al
AO
Refresh AmlJS
--------------1
Array
Du~my Cells
64·Colum-ri -
Select Lin.es
COlumn Decoders
'·of·64
AO
DC OPERATING CONDITIONS AND CHARACTERISTICS
(F ull operating voltage and temperature range unless otherwise noted.!
RECOMMENDED OPERATING CONDITIONS
P.rameter
Supply Voltage
Not.
Symbol
Min
Typ
Ma.
Unit
VDO
10.8
12.0
13.2
V
1
VCC
4.5
5.0
5.5
V
1,2
VSS
0
0
0
V
1
VBB
-4.5
-5.0
-5.5
V
1
1
V,HC
2.4
V
V,H
2.4
-
7.0
Logic 1 Voltage, all inputs except RAS. CAS. WAITE
7.0
V
1
Logic 0 Voltage, all inputs
V,L
-1.0
..
0.8
V
1
Log.e 1 Volt., RAS, CAS, WRITE
DC CHARACTERISTICS
IVOO
12 V . 10% VCC
50 V
10%
Vas
Characteristic
A..,erag~
Vee
Symbol
VOO Power Supply Current
'001
Power Supply Current
Yee
0
·50 V . 10% VSS' 0 V TAO tu 70 C.I
ICC
Notes
M.n
Max
Units
-
35
rnA
4
-
rnA
5
"A
'BB1,3
-
200
Standby Vee Power Supply Current
'BB2
--
100
"A
Standby VOO Power Supply Current
'002
-
1.5
mA
6
Average VOO Power Supply Current dUring "RAS only" cycles
'003
-
'Z7
mA
4
Input Leakage Current (any Input)
'IILI
"A
'OILi
-
10
Output Leakage Current
10
"A
6.7
VOH
2.4
-
V
2
VOL
-
04
V
Aver~ge
Power Supply Current
Output Logic 1 Voltage
@
'out:: -5 rnA
Output LogiC 0 Voltage @ 'out::' 4.2 rnA
NOTES,
1
All voltages referenced to
2.
vss Vas
must be applied before and removed after other supply .... oltages
Output lIoltage Will SWing from VSS to
Vee
under open Circuit conditions. For purposes of maintaining dala ,n power "own mode, Vee
may be reduced to VSS Without affecting refresh operat.ons. VOH(minl spee,fication is not guaranteed
In
th·s
1110(18
3.
Several cycles are required after power·up before proper device operation IS achieved. Any 8 cycles WhICh perlorrll fefresh are adequate
4.
Current is proportional to cycle rate; maximum current
IS
measured at The fastest cycle rate
5
ICC depends upon output loading. The Vee supply is connected to the outr.,lut buffer only.
6.
OUlput is disabled (open-circuit) when
7
0 V G; V out "
CAPACITANCE
cAs is al a logiC
1
.. 5.5 V
-
-
If-I 0 MHz TA-25'C VCC-5
- V peltod.cally sampled ralher than 100% testedllSee Note 81
Parameter
Symbol
Typ
Max
Input Capacitance IAO-A5), Din
Cll
40
50
Inpul Capacttance~, CAS,WAITE
CI2
80
10
Output Capacitance (Ocutl
Co
50
70
2-14
Unit Notes
pF
9
pF
9
pF
7.9
IICM4116B
r:
AC OPERATING CONDITIONS AND CHARACTERISTICS (See Notes 3, 9,14)
READ, WRITE, AND READ-MODIFY-WRITE CYCLES
{VOO=12V -10% VCC=50V -10% Vee=-50V.,0% VSS=OV TA=O,070 u CI
MCM41168-16 MCM41168-20 MCM41168-26 MCM41188-30
Parameter
Random Read or Wnte Cycle Time
Symbol
Min
Max
Min
Max
Min
Mox
Min
Max
Units
'RC
375
375
-
410
-
480
-
ns
375
-
-
ns
300
ns
10,12
-
200
ns
11,12
60
0
60
ns
17
150
-
180
Read Write Cycle Time
'RWC
Access Time from Row Address Strobe
'RAC
Access Time from Column Address Strobe
'CAC
-
100
-
135
-
165
Output Buffer and Turn-off Delay
'OFF
0
50
0
50
0
'''lP
100
-
120
-
Row Address Strobe Precharge Time
375
150
515
200
660
250
ns
Row Address Strobe Pulse Width
'RAS
150
10,000
200
10,000
250
10,000
300
10,000
ns
Column Address Strobe Pulse Width
'CAS
100
10,000
135
10,000
165
10,000
200
10,000
ns
Row to Column Strobe Lead Time
'RCO
20
50
25
65
35
85 -
60
100
ns
Row Address Setup Time
'ASR
0
-
0
-
0
-
0
-
ns
,Row Address Hold Time
'RAH
20
Column Address Setup Time
'ASC
-10
-
-10
'CAH
45
-
55
'AR
95
-
120
-
160
200
-
'ns
Column Address Hold Time
-
-10
Column Address Hold Time
-
'T
3.0
35
3.0
50
3.0
50
3.0
50
ns
'RCS
0
-
0
0
-
ns
0
--
ns
iOQ
200
-
ns
160
-
0
120
-
55
-
75
-.
100
-
ns
75
-10.
Notes
35
ns
60
75
100
13
ns
ns
Referenced to A AS
Transition Time (Rise and Fall)
Aead Command Setup Time
Read Command Hold T,me
'RCH
0
-
0
Write Command Hold Time
'WCH
45
55
Write Command Hold Time
Referenced to RAS
'WCR
95
-
Write Command Pulse Width
-
0
75
'WP
45
Write Command to Row Strobe Lead Time
tAWL
60
Write Command to Column Strobe
Lead Time
'CWL
60
-
80
-
100
-
-
0
-
0
55
75
120
-
160
100
80
14
ns
ns
180
180
-
ns
0
-
os
15
100
ns
15
200
-
ns
-20
-
ns
200
2.0
ms
Data in Setup Time
'OS
0
Data in Hold Time
'OH
45
'DHR
95
Column to Row Strobe Precharge Time
'CRP
-20
-
-20
RAS Hold Time
'RSH
100
-
135
-
165
-
Refresh Period
'RFSH
-
2.0
-
2.0
-
2.Q
-
-
-20
-
-20
-
-20
-
ns
180
-
ns
16
280
-
ns
16
Data in Hold Time Referenced to RAS
WAITE Command Setup Time
'wcs
-20
CAS to WRITE Delay
'CWO
70
RAS '0 WR ITE Delay
'RWO
120
'CP
60
'PC
170
'CSH
150
CAS Precharge Time (Page mode cycle only)
Page Mode Cycle Time
CAS Hold T;me
95
160
80
225
200
-20
125
210
100
275
250
100
ns
ns
325
7
ns
300
-
ns
NOTES. (continued)
8.
,9.
Capacitance measured With a Boonton Meter or effective capacitance calculated from the equation
AC measurements assume tT
to. Assumes that tACO' tT
11.
~ssumes
that tRCO +, tT
.=
C
5.0 ns.
~ tACO (max).
:;t
tACO (max),
12. Measured with a load circuit equivalent to 2 TTL loads and 100 pF.
13.
14.
Operation within the tRCO (max) limit ensures that tRAC (max) can be met. tRCO (max) is specified as a reference point only; if tACO
is greater than the speCified tRCD (max) limit, then access time is controlled exclusively by tCAC.
VIHC (min) or VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transistion times are measured
between VIHC or VIH and VIL.
15. These parameters are referenced to CAS leading edge in random write cycles and to WRITE leading edge in delayed write or read-modify·
write cycles.
16. twCS. tcwo and t RWD are not restrictive operating parameters. They c:re included in the data sheet as electrical characteristics only-: If
twcs ~ twcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the
entire c'ycle; If tcwo ;---
MCM4517
PIN ASSIGNMENT COMPARISON
MCM4517
MCM4516
REFRESH
VSS
N/C
D
CAS
D
W
1.
W
Q
A6
RAS
AO
A3
AO
A2
A4
A2
A1
A5
4
6
A1
VCC
N/C
Vec
N/C'
VSS
D
15 -CAS
MCM6632
16
VSS
REFRESH
15
CAS
D
1.
16
VSS
15
CAS
14
Q
13
A6
14
Q
13
A6
W
RAS
12
A3
AO
12
A3
11
A4
A2
11
A4
10
A5
10
A5
9
A7
4
A1
N/C
Vee
REFRESH
VSS
N/C'
16
VSS
D
CAS
D
15
CAS
14
Q
A6
W
RAS
4
13
A6
A3
8
9
8
MCM6665
MCM6664
1.
W
3
14
Q
RAS
4
13
A6
12
A3
AO
A3
AO
5
12
11
A4
A2
A4
A2
6
11
A4
10
A5
A1
A5
A1
10
A5
9
A7
VCC
A7
VCC
9
A7
AO
A2
6
A1
VCC
8
W
Q
PIN VARIATIONS
Pin Number
MCM4116
MCM4616
MCM4617
MCM6632
MCM6663
MCM6664
MCM6666
1
VBBI-5 VI
REFRESH
NiC
REFRESH
N/C"
REFRESH
N/C"
e
VODI+ 12 VI
VCC
Vec
9
VCCI+5 VI
N/C
N/C
Vec
A7
VCC
A7
VCC
A7
VCC
A7
-'nternal pullup resistor should be left open or tied to
Vee
2-25
®
MOTOROLA
MCM6632
32.768-BIT DYNAMIC RAM
The MCM6632 is a 32,768 bit. high-speed. dynamic Random-Access
Memory. Organized as 32.768' one-bit words and fabricated using
HMOS high-performance N-channel silicon-gate technology. This new
breed of 5-volt only dynamic RAM combines high performance with low
cost and improved reliability.
By multiplexing row- and column-address inputs. the MCM6632 reqUires only eight address lines and permits packaging in standard 16-pin
dual-in-line packages. Complete ~ddress decoding is done on chip with
address latches incorporated. Data out is controlled by CAS allowing
for greater system flexibility.
All Inputs and outputs. Including clocks. are fully TTL compatible.
The MCM6632 incorporates a one-transistor cell design and dynamic
storage techniques. In addition to the RAS-only refresh mode. refresh
control function available on pin 1 provides automatic and self-refresh
modes
MOS
IN-CHANNEL. SILICON·GATEI
32,768-BIT
DYNAMIC RANDOM ACCESS
MEMORY
• OrganIZed as 32.768 Words of 1 Bit
• Single + 5 V Operation
• Fast 150 ns Operation
• Low Power DiSSipation
275 mW Maximum (Actlvel
30 mW Maximum (Standby)
•
•
•
•
•
L SUFFIX
CERAMIC PACKAGE
CASE 690
Three-State Data Output
Internal Latches for Address and Data Input
Early-Write Common I/O Capability
16K Compatible 12B-Cycle. 2 ms Refresh
Control on Pin·l for Automatic and Self Refresh
PIN ASSIGNMENT
REFRESH
•
•
•
•
CAS Controlled Output
Upward Pin Compatible from the 16K RAM IMCM4116)
One Half of the 64K RAM MCM6664
The Operating Half of the MCM6632 is Indicated by Device Marking:
MCM66320 Tie A7 CAS IA15) Low "0"
MCM66321 Tie A7 CAS IA15) High "1"
Clock
Amph~ler
A2
11
A4
Al
10
A5
9
A7
~
A2 ...
~
A3 . .
!
A4 ...
A5 ...
AS __
AO-A7
J
16.384 elt Memory
Array
,
~
~
~
§
16, 384· Sit Memory
Array
u
~
'0
~
-
l"
c
a
(i
11211 of 2561
Column Decoder
~
1/2 Cell
Logic
1/211 of 2561
Column Decoder
'"~
~
16,384- Bit Memory
Array
recha.rgt
Clock
Sense Ampllher
<{
~
0
~
16,384-8It Memory
Array
'"~
A7-"
f-
o
I-rn
RAS ..
CAS ..
VCC
~
i-REFRESH
g'
~Dala In, 0
E
g
~OutPut
Data. 0
V S
Refresh
Address Inpul
...[)~,:t~~~
I
I
.... Read/Write Input
Row Address Strobe
. Column Address Strobe
... Power 1+5 VI
.Ground
ThiS deVice contains circuitry to protect the inputs agarnst damage due to high static voltages
or electric fields; however, it is advised that normal precautions be taken to avoid application of
any voltage higher than maximum fated voltages
to this high-impedance circuit.
'0
-
W
I+-- ~
a
.=
Q
i-AAS
'" f--wnte. W
u
~a
8
PIN NAMES
"
l"
A3
AO
REFRESH
0
11
A6
-vss
Sense Amphfler
a
~
AO-..
AI . .
~
Q
R7i3
_vcc
Sense
~
W
Vee
BLOCK DIAGRAM
precha~gE
VSS
0
• RAS-only Refresh Mode
Sense Amphfler
L-....
DS9B26/!H1l
2-26
~'MCM6632'
ABSOLUTE MAXIMUM
RATINGS ISee Notel
---- -- _.
FIGURE I - OUTPUT LOAD
_..
Rating
Symbol
Value
Unit
~~ on_ ~n2:-"-~Aelatlve to V 55 lexcept Vee I
Yin. Vout
- 2 to + 7
V
.. 1 to + 7
V
Voltage on VCC Supply Aelatlve to VSS
~~eratlng
V m. Vout
TA
Temperature Range
Storage Temperature Range
Power DISSipation
-.
Data Out Current
._-_.
o to
+ 70
5V
970 II
'c
T5t9
-6510+150
·C
Po
10
W
lout
50
mA
.l
tOOpF o •
12kll
NOTE' Permanent deVIce damage may occur If ABSOLUTE MAXIMUM AATINGS are ex
ceeded. Functional operation should be restricted to RECOMMENDED OPERAT·
ING CONDITIONS. Exposure to hlghel than recommended voltages for extended
periods of time could affect deVice reliability
-Includes Jig Capacitance
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted.)
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
MCM6664·15, ·20
Symbol
Min
Typ
Ma.
Unit
Vr.r.
VSS
4.5
0
5.0
0
55
0
V-
I
V
I
Notes
Logic 1 Voltage, All Inputs
VIH
24
-
VCC+ 1
V
1
Logic 0 Voltage, All Inputs
VIL
- 2.0
-
0.8
V
1
Notes
DC CHARACTERISTICS
Characteristic
Symbol
Min
Ma.
Units
ICCI
50
mA
4
5
mA
5
40
mA
-
10
p.A
125
p.A
IOILi
-
10
p.A
Output Logic 1 Voltage @ !out = - 4 mA
VOH
2.4
-
V
-
Output Logic 0 Voltage @ lout = 4 mA
VOL
-
0.4
V
-
Vee Power Supply Current ItRC min,)
Standby
Vee
Power Supply Current
ICC2
VCC Power Supply Current Durong AAS Only Aefresh Cycles
ICC3
Input Leakage Current lany Inputllexcept AEFAESHIIVSS:5V,n :5VCCI
IIiLi
REFRESH Input Current IVF - VSSI
Output Leakage Current ICAS at logic 1, 0:5V out
IF
s5.51 ._-
CAPACITANCE If='1 0 MHz, TA=25'C VCC=5 V Peroodically Sampled Aather Than 100% Testedl
Symbol
Parameter
Typ
Ma.
Units
Notes
Input CapacItance IAO·AlI, Din
Cil
4
5
pF
7
Input Capacitance AAS, CAS, WRITE
CI2
8
10
pF
7
Output Capacitance 1D0uti ICAS = VIH to dIsable outputl
Co
5
7
pF
7
Units
Notes
8,9
8,9
AC OPERATING CONDITIONS AND CHARACTERISTICS
I See Notes 2, 3, 6, and Figure 11
IRead, Wrote, and Read·Modify-Wrote Cycles I
(Full Operating Voltage and Temperature Range Unless Otherwise Noted)
Parameter
Symbol
-
350
-
-
350
-
ns
ns
150
-
200
ns
10,12
75
-
110
ns
11, 12
30
0
40
ns
18
-
140
.-
ns
150
10000
200
10000
ns
75
10000
110
10000
ns
-
30
75
35
90
ns
13
Row Address Setup Time
tRCD
tASR
0
-
tRAH
25
-
0
Row Address Hold T,me
30
-
ns
ns
-
Column Address Setup Time
tASC
ns
-
55
155
-
ns
-
120
-
-
tCAH
0
45
0
Column Address Hold Time
ns
-
3
50
3
50
ns
6
Random Read or Wnte Cycle Time
,,'.
MCM6632-15 . MCM6632-20
Min
Min
Max
Ma.
tRC
300
300
-
Read Write Cycle Time
tRWC
Access Time from Row Address Strobe
tRAC
Access Time from Column Address Strobe
tCAC
Output Buffer and T urn-Off Delay
tOFF
0
Row Address Strobe Precharge Time
tRP
120
Row Address Strobe Pulse Width
tRAS
Column Address Strobe Pulse Width
tCAS
Row to Column Strobe Lead Time
Column Address Hold Time Referenced to RAS
tAR
tT
Transition Time (Rise and Faill
2-27
-
MCM6632
AC OPERATING CONDITIONS AND CHARACTERISTICS
ISee Notes 2, 3, 6 and FIgure 11
IRead, Write, and Read-Modify-Wnte Cycles I
{Full Operating Voltage and Temperature Range Unless Otherwise Notp.dl
Parameter
Symbol
MCM6632-15
MCM6632-20
Min
Ma.
Min
Ma.
-
0
-
ns
-
10
-
ns
14
35
-
ns
14
ns
ns
-
ns
15
ns
15
Read Command Setup Time
tRCS
0
Read Command Hold Time
tRCH
10
Read Command Hold T,me Referenced to RAS
tRRH
30
Write Command Hold Time
tWCH
45
twrR
Write Command Hold Time Relerenced to
RA"S
Write Command Pulse Width
Write Command to Row Strobe Lead Time
Write Command to ColtJmn
Data
In
St~obe
Lead Time
Setup Time
Data in Hold Time
Data in Hold Time Referenced to
R'AS
Column to Row Strobe Precharge Time
RAS Hold T,me
Refresh Period
WRiTE Command Setup
CAS to WlfiTE Delay
RAS to wmTt Delay
120
-
155
55
Units
ns
Notes
twp
45
-
55
tRWL
45
-
55
tCWL
45
55
tDS
0
t[)H
45
tDHR
120
tCRP
-10
tRSH
75
-
110
-
tRFSH
-
2.0
-
2.0
ms
-10
-
ns
16.
55
ns
16
ns
16
ns
450
3BO
-
0
55
155
-10
ns
ns
ns
-
ns
-
ns
tFBP
2000
tFBR
390
REFRESH Cycle T,me IAuto Pulse Model
tFC
330
-
ns
-
~ Pulse Penod IAuto Period Model
tFP
60
2000
60
2000
ns
-
REFRESH to ~ Setup Time IAuto Pulse Model
tFSR
3J
30
ns
REFRESH to RAS Delay T,me IAuto Pulse Model
tFRD
390
450
450
-
-
T,me
twcs
-10
tCWD
45
tRWD
125
CAS Hold Time
tCSH
·,50
~to~Delay
tRFD
0
mR'ESH
Penod I Battery Backup Model
REFRESH to ~ Precharge T,me IBattery Backup Model
~ Inactive Time
~ to ~Lead T,me
NOTES:
tFI
30
-
tFR
390
-
160
200
0
2000
30
ns
ns
ns
ns
ns
ns
1. All voltages referenced to VSS.
2. VIH min and VIL max are reference levels for measuring timing of input signals. Transition times are measured between V(H and
VIL·
3. An initial pause of 100 "s is required after power-up followed by any 8 AAS cycles before proper device operation guaranteed.
4. Current is a function of cycle rate and output loading; maximum current is measured at the fastest cycle rate with the output
open.
5. Output ,s disabled (open-clrcuitl and RAS and CAS are both at a logic 1.
6 The transition time specification applies for all input signals. In addition to meeting the tranSition rate specification, all Input signals must transmit between VIH and VIL (or between VIL and VIH) in a monotonic manner.
7. Capacitance measured with a Boonton Meter or effective capacitance calcula'l:ed from the equation: C = ~
8. The specifications for tAC (min), and tAWC (min) are used only to indicate cycle time at which proper operatton over the full temperature range 10·CsTAS70·CI is assured.
9. AC measurements assume tT = 5.0 ns.
10. Assumes that tRCD s tRCD I Maxi
11. Assumes that tRCD;': tRCD I Maxi
12. Measured with a current load equivalent to 2 TTL loads 1+200 ~A, - 4 mAl and 100 pF IVOH = 2.0 V, VOL = - 0.8 VI.
13. Operation within the tACO (max) limit ensures that tAAC {max} can be met. tACO (maxI is specified as a reference pOint only; if
tRCo is greater than the specified tACO (max) limit, then access time ,s controlled exclusively by tCAC.
14. Either tRRH or tRCH must be satisfied for a read cycle.
15. These parameters are referenced to CAS leading edge in random write cycles and to WRITE leading edge in delayed wnte or readmodify-write cycles.
16. twcs, leWD. and tRWo are not restrictive operating parameters. They are included In the data sheet as electrical characteriistics only: if twcs ~ twcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance)
throughout the entire cycle; if tCWD;': tCWD Imln) and tRWD;,:tRWD Imlnl, the cycle IS a read-write cycle and the data out will
contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at
access timel is indeterminate.
17. Addresses, data-in and WRITE are don't care. Data-out depends on the state of CAS. If CA:S remains low, the previous output
will remain ~alid. CAS is allowed to'make an active to inactive transition during the pin 11 refresh cycle. When CAS is brought
high, the output will assume a high-impedance state.
.
18. toff (max) defines the time at which the output achieves the open Circuit condition and is not referenced to output voltage levels.
2-28
:MCM6632
PIN ASSIGNMENT COMPARISON
MCM4516
VSS
N,C
0
15
CAS
W
14
Q
13
A6
AO
12
A3
A2
11
A1
10
Vec
9
1.
MCM6632
MCM4517
16
REFRESH
16
VSS
RHl'fESH
VSS
0
15
CAS
0
CAS
Vii
14
Q
RAS
13
A6
AO
12
A3
AO
A4
A2
11
A4
A2
A5
A1
10
A5
N/C
Vcc
9
VSS
REFRESH
CAS
0
W
1.
W
A6
1.
0
A3
A4
A5
N/C
Vcc
VSS
N/C
VSS
15
CAS
0
CAS
14
Q
W
13
A6
MCM6633
N/C
Q
A7
MCM6665
W
Q
RAS
A6
AO
A2
Q
RAS
4
A6
A3
AO
5
12
A3
AO
A4
A2
11
A4
A2
A4
A3
A1
10
A5
A1
10
A5
A1
A5
VCC
9
A7
VCC
9
A7
Vcc
A7
PIN VARIATIONS
---
Pin Number
MCM4116
MCM4616
1
Vaal-5 VI
8
9
VOOI + 12 VI
VCCI+5VI
MCM6664
REFRESH
N/C
REFRESH
N/C
VCC
A7
VCC
A7
VCC
A7
VCC
A7
MCM6632
REFRESH
N/C
VCC
N/C
VCC
N/C
On-Chip Refresh Featur",,1 Benefits
Reduce
Reduce
Reduce
Reduce
System
System
System
System
Refresh Controller Design Problem
Parts Count
Noise Increasing System Reliability
Power During Refresh
ORDERING INFORMATION
Pert Number
Description
S3)88d
Marking"
MCM6632L15
32K Dynamic
150
MCM66320L 15/MCM66321 L 15
MCM66320L 15
Random Access
150
MCM66320L15
MCM66321 L 15
Memory
150
MCM66321L15
MCM6632L20
Sidebraze
200
MCM66320L20/MCM66321 L20
MCM66320L20
Package "L"
200
200
MCM66320L20
MCM66321 L20
" MCM66320 = Tie A7 CAS IA151 Low "0"
MCM66321 = Tie A7 CAS IA 151 High "1"
2-29
MCM6665
MCM8663
MCM4517
MCM66321 L20
MCM6632
2-30
,1CM6632
SELF REFR~SH MODE (Blttary Backup)
(SEE NOTE 17)
: :~. . ,. . .,. ,. ". ,.n,- -tRFD-\~~-""~
I
ir-----------------------
VIH - - - - - - - - - - , , 1
AUTOMATIC PULSE REFRESH CYCLE (SEE NOTE 17) .
SINGLE PULSE
~tR-F-D--------~----------tFRD-----------------------~~
tF-SR------
~-------------------'FP------------------__..!
AUTOMATIC PULSE REFRESH CYCLE - MULTIPLE PULSE
(SEE NOTE 17)
VIH~~rlr----------~~r_-----------~
RAS-ONL Y REFRESH CYCLE
(Dotl-In Ind WRITE ar. Don't Car.,
CAS is HIGHI
VIH ........rv............
ADDRESSES,
AO-A6
2-31
MCM6632
READ-WRITE/READ-MODIFY-WRITE CYCLE
tRWC
RAS
V,H
tRAS
-I
~1~-----tAA----~"
V,L
tASH
tCSH
tCAS
m
V,H
V,L
V,H
Addresses
Address
~--------~--~I-tRWD--------------~~
L z3
'"f-...- - - - t c w D - - - - - - I I t o i
V,H
a
V,L
Vii
IData Outl VOH
VOL
I
~~:c
r
tOFF
Val,o
Data
_
VIH~14
tDS-rJ~
~
IHAI
o IDatalnl
vlL
2-32
.................
Valid
~nr,...,..,...,..,....,...,....,.....,......,
Date
~
MCM6632
MCM6664 Bil ADDRESS MAP
o
Row Address A7 A6 A5 A4 A3 A2 Al AO
Column Address A7 A6 AS A4 A3 A2 A 1 AO
Row
CoIumnAddreuee
H.,.
FE
Dec:
154
FF
255
Fe
FD
FA
FB
FB
'9
252
253
B2
BO
81
7D
~
~
~
~~
~§§~
88
04
03
02
01
~
~~
.......
~~
0-
0-
oo~~oo~
--------
--
0..- ..... 0 0 . . - . . - 0 0
----00
A2
AO
1
1
1
1
0
0
0
0
1
1
0
0
0
251
248
249
1
1
1
1
1
1
1
1
0
1
1
0
0
1
0
1
0
1
130
131
128
129
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
1
127
126
115
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
4
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
1
0
1
0
1
0
0
0
0
,
0
0
0
0
0
0
~8bBg8858
n
--
AS
1
1
1
1
1
1
1
1
2
00
~
M
1
1
1
1
1
1
1
··
·
···
···
···
·
~:::o8
0000
A3
1
1
1
1
1
1
1
1
··
···
·
7'
7E
~
AS
I
1
1
1
1
1
1
1
250
B3
00
A7
.3
Max
ns
-
ns
14
ns
14
rl~W~r~'t~e~C~o~m~m~an~d~H~o~ld~T?'~m~e~~~~~~~~__________________t-t~W~C~H~_t--~4~5:~I__----+-~~~_r---~--n~s_t-----_1
Write Command Hold Time Referenced to liAS
tWCR
120
155
ns
I
i,
Write Command Pulse WIdth
Wnte Command to A.ow Strobe Lead Time
tAWL
45
45
-
55
55
-
ns
ns
Wn!e Command to Column Strobe Lead Time
tCWL
45
-
55
-
ns
tDS
0
-
0
-
ns
15
'DH
45
-
~
-
ns
15
Data
In
twp
Setup T,me
Data In Hold Time
~D~a~ta__'n_H~o_l~d_T_im~e_R~e_fe_r~en_c_e~d_t_o_Ri>3.A~__________________________j __ ~tD~H~R__4_--12-:-0~~----4_--1575~~----I_-ns~-----_t
Column to Row Strobe Precharge Time
tCRP
-+__~tR~,S~H~ __
1--~~-,H~O~ld~T,:-lm=e_____________________________________
- 10
~
-
- 10
-
ns
-
110
-
ns
tRFSH
2.0
2.0
ms
Refresh Period
"'W"'R"'I"'f'"Ec-C""o::cm-"m=-=--a-ndc-::S,-e"'"tu-p--T:O-,c-m-e----------- --------------------·+--t"'w"----"C"-S'----+-----:-1::-0+---=-~+----:-10::--I--:O-"---,l--n-"s-'-----l---:1"6,------1
~~~A~t~07W~R~IT~E~D~e~la~y-·----___ ---------------------------__1--~tC~W~D__+_~4,,5~+_-.---~-,-:-::~~~----+--ns~---:1~6~
~~~~t~o-"W~R':-IT~E-"D~e':-Ia~y------_--------------.--------.----__---l__~tR~W~D'_____r-~12~5---l------j--~100,---l~---j--~ns~--"16~__l
~ Hold TIme
tCSH
150
-
CAPACITANCE If= 1.0 MHz, T A = 25°C, VCC= 5 V Periodically Sampled Rather Than 100% Testedl
Parametar
Symbol
Input Capacitance IAO-A71, D
Input Capacitance~,
CAS, wmTt
Dutput Capacitance {Ol {CAS = VIH to disable output!
200
-
ns
Typ
Ma.
Units
Notes
Cll
4
5
pF
7
CI2
8
10
pF
7
Co
5
7
pF
7
NOTES:
1
2
All voltages referenced to VSS.
VIH min and VIL max are reference levels for measuring timing of input signals. Transition times are measured between VIH and
VIL·
3. An initial pause of 100 its IS required after power-up followed by any 8 RAS cycles before proper device operation guaranteed.
Current IS a function of cycle rate and output loading; maximum current is measured at the fastest cycle rate with the output
ooen
5. Output IS dIsabled lopen-clrcuitl and RAS and CAS are both at a logic 1.
6. The transition time specification applies for all input signals. In addition to meeting the transition rate specification. all input signals must transmit between VIH and VIL (or between VIL and VIH) in a monotonic manner.
7. Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = ~
8.
The specifications for tRC (min). and tAwe (min) are used only to indicate cycle time at which proper operation over the full temperature range (Q°es T A:S 70 0 e) is assured.
AC measurements assume tT = 5.0 ns.
Assumes that tRCDStRCD Imaxl.
Assumes that tRCD" tRCD Imaxl.
Measured WIth a current load equivalent to 2 TTL loads {+ 200 ~A, -4 mAl and 100 p'F {VOH= 2.0 V, VOL = -0,8 VI
Operation WI~hln the tACO (maxi limit ensures that tRAC (max) can be met. tACO (max) IS specified as a reference point.only; if
tACO IS greater than the specified tRCD (maxi limit. then access time is controlled exclusively by tCAe.
14. Either tRRH or tRCH must be satisfied for a read cycle,
15 These parameters are referenced to CAS leading edge in random write cycles and to WAITE leading edge in delayed write or readmodify-write cycles.
16, twCS. teWD. and tRWD are not restrictive operating parameters. They are included in the data sheet as electrical characteriistics only: if twcs ~ twcs (minI. the cycle is an early write cycle and the data out pin will remain open circuit (high impedance)
throughout the entire cycle; If tCWD~ tCWD (minI and tRWD~tRWD Iminl. the cycle is a read-write cycle and the data out will
contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at
access tlmel IS Indeterminate.
.
17. toff (max) defines the time at which the output achieves the open circuit condition and is not referenced to output v~ltage levels.
g,
10.
11
12
13,
2-36
MCM6633
PIN ASSIGNMENT COMPARISON
MCM4517
Iml!rn1
VSS
N/C
16
VSS
mI!m
VSS
D
CAS
D
15
~
D
~
W
14
a
13
A6
W
m
A6
A2
Al
7
VCC
8
AO
12
A3
AO
A3
A2
11
A4
A2
A4
10
A5
10
A5
Al
N/C
VSS
Rtrn~
D
CAS
7
A5
N/C
VCC
16
VSS
N/C
16
VSS
D
15
CAS
D
15
CAS
W
14
a
W
14
a
13
A6
13
AS
12
A3
AO
12
A3
11
A4
A2
11
A4
10
A5
Al
10
A5
9
A7
VCC
9
A7
MCM6633
AO
A6
A4
VCC
4
m
A3
N/C
W
a
W
11
AO
RAS
1.
MCM6665
MCM6664
14
a
13
A6
12
A3
AO
A2
6
i1
A4
A2
Al
7
10
A5
Al
VCC
8
9
A7
VCC
6
8
A7
PIN VARIATIONS
Pin Number
MCM4116
MCM4516
MCM4517
MCM8632
MCM6663
MCM8664
1
8
9
VBB(-5 VI
REFRESH
N/C
REFRESH
N/C
REFRESH
N/C
VDD( + 12 VI
VCC
Vec
VCC(+5VI
N/C
N/C
VCC
A7
VCC
A7
Vee
A7
Vec
A7
MCM6666
ORDERING INSTRUCTIONS
PART NUMBER
DESCRIPTION
SPEED
MCM6633L15
MCM66330L 15
MCM66331L15
MCM6633L20
MCM66330L20
32K RAM
Sidebraze
Package
"L"
66330L 15/66331L15
150
66330115
150
200
MCM66331 L20
"MCM66330L20 ~ Tie A7 CAS (A151 Low"O"
MCM66331L20 ~ Tie A7 CAS (A151 High "1"
2-37
MARKING"
150
66331L15
66330L20/66331 L20
200
66330L20
200
66331L20
MCM6633
READ CYCLE TIMING
~----------~----'RC---------·----
--
~
~----------'RAS-------_i~
V,H
- - - - - . I 1OI1---~'AR-----4'~
RAS
V'L
1OIt---------'CSH~------_i~
__.al..---;--'RSH------il~
V,H
CAS
------:--:-----r---... 1OIt---'---'CAS---~~
,-+--11.--------""""""\1
V,L
Addresses
V,L
I
V,H
~
W
V,L
'CAC
'RAC
Q IData Ou,l VOH
'OFF
Va:ld
HIgh Z
Data
VOL
WRITE CYCLE TIMING
'RC
V,H
RAS
V,L
'RSH
'CSH
'CAS
V,H
CAS
V,L
'CAH
VIH
Addresses
V,L
V,H
W
V,L
tWCR
o lData In)
V,H
Vahd
Data
VIL
'DHR
Q lData Out!
VOH
High Z
VOL
2-38
MCM6633
RAS·O~L 'y REFRESH CYCLE
!Data-in and Write are Don t Care, CAS is HIGH)
~~------------IRC-----------------~~~
Aedresses.
AO·A6
READ-WRITE/READ·MODIFY-WRITE CYCLE
tRWC
tRAS
VIH
AA!.
~
~~__------tAR--------~
VIL
tRSH
tCSH
tCAS
VIHI
m
VIL
VIH
Address••
VIL
Address
~--------~--~I~tRWD--------------~~
I------ICWD----------t~
VIH
Vi
V"
a fData
Outi
VOH
VOL
I
o IData
101
2-39
MCM6633
MCM88IIIi BIT ADDRESS MA'P
Pin
e
o
Row Address A7 A6 A5 A4 A3 A2 A1 IW
Column Address A 7 A6 A5 A4 A3 A2 A 1 AO
Row
Column Add,....
H..
Do<
FE
FF
Fe
FD
FA
FB
FB
F9
254
255
252
253
250
251
248
249
··
··
··
0000
88
§§§~
W~
W
~
~~
~~
~~
N
0-
0-
--------
----
c
E
16.384-Bit Memory
,::
Array
0
a
a:
~
PrechorgE
Clock
AOl5
12pA3
A2[6
llpA4
Al17
lOpA5
"0
Sense Amplifier
-
9
A7
REFRESH.
AD-A7..
0..
"0
~
!
~
~
a
PIN NAMES
Sense Amplifier
0
~
A t.
~
@
14p
13p A6
Sense Amphtler
15p~
4
VCC [ 8
BLOCK DIAGRAM
Precha,fgE
lrii'-""i6p VSS
012
_i
-,4-'
Wrtte,W
Refresh
. Address Input
. ........ Data In
Q..
.. .................... Data Out
W.....
.. ....... Read/Wme Input
RAS..
.. .... Row Address Strobe
CAS ............... Column Address Strobe
Vce ........................ Power' + 5 VI
VSS .................................... Ground
... i
4-'Data In, 0
...
Output
Data,
a
T his device contains circuitry to protect the in-
puts against damage due to high static voltages
or electric fields; however, it is advised that nor·
mal precautions be taken to avoid application of
any voltage higher than maximum rated voltages
Sense Amplifier
-
to this high· impedance Circuit.
DS9B22/~OO
2-41
MCM6664
ABSOLUTE MAXIMUM RATINGS ISee Notel
FIGURE 1 Symbol
Valua
'Unit
Voltage on Any Pin Relative to VSS lexcept VCCI
Vin • Vout
- 2 to + 7
V
Voltage on VCC Supply Relallve to VSS
Yin. Yout
-110+7
V
o to
-6510+150
°c
°c
PD
1.0
W
lout
50
mA
Rating
-
--"---
Operatmg Temperature Range
TA
Storage Temperature Range
- - - - -- T sto
Power DISSipation
----.
Data Out Current
+ 70
OUTPUT LOAO
5V
970
n
----.--+0--...
Q-
....
100 pro
NOTE Permanent deVice damage may occur If ABSOLUTE MAXIMUM RATINGS are ex
ceeded. Functional operauon should be restricted to RECOMMENDED OPERAT1NG CONDITIONS Exposure to higher than recommended voltages for extended
peflods of time could affect deVice reliability
-Includes Jig Capacitance
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted_'
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
MCM6664-15. 20
-,--------;-:-;
LogiC 1 Voltage, All Inputs
LogiC 0 Voltage. All Inputs
DC CHARACTERISTICS
Symbol
Min
Typ
Max
Unit
Notes
VCC
VSS
4.5
0
5.0
0
5.5
0
V
V
1
1
VIH
2.4
V
1
- 2.0
-
VCC+ 1
VIL
0.8
V
1
Notes
-
Characteristic
Symbol
Min
Max
Units
r---v-CC Power Supply Current (tAC min.)
ICC1
50
mA
4
Standby V CC Power Supply Current
ICC2
5
mA
5
VCC Power Supply c:urrent DUring AAS Only Refresh Cycles
ICC3
-
40
mA
Input Leakage Current (any Input except REFRESH) (VSS ~ Vln:S VCC)
IIiLi
-
10
~A
IF
-
125
~A
IOILi
10
~A
VOH
2.4
-
V
-
0.4
V
-
Symbol
Typ
Max
Units
Notes
Cl1
4
5
pF
7
CI2
8
10
pF
7
Co
5
7
pF
7
~ Input Current IVF-VSSI
_.
Output Leakage Current (CAS at logiC 1, O:sVout:s5,~i
Output LogiC 1 Voltage @ lout =
Output LogiC
a Voltage @
-4
-
rnA
lout = 4 mA
VOL'
CAPACITANCE If ~ 1 0 MHz T A - 25'C VCC - 5 V Pe"odlcally Sampled Rather Than 100% Testedl
Parameter
Input Capacitance tAO-Ali. 0
Input Capacitance RAS. CAS. WRITE
Output Capacitance (01 (C"A!;
= VIH
.-
to disable output)
AC OPERATING CONDITIONS AND CHARACTERISTICS
ISee Notes 2. 3. 6 and Figure 11
IRead. Write. and Read-Modlfy-Wrlte Cyclesl
(Full Operatlnq Voltaqe and Temperature Range Unless O.therwlse Noted)
r--------------------- ---------Parameter
---r---.....,=OEi"
...
M ;M 1Cili4-15 MCM6664-20
. Symbol
....-;;=;;;-;-o;;;r--.-~---,
Min
Random Read or Wnte Cycle 11me
-
Read Write Cycle Tlm_e-:--;--c-_-=---c_______________ . ______ _
~~::: ~ ::: :~:: ~~:::~~:~e~~r;~~obe
Output Buffer and Turn·OIf Delay
.~
-
tRWC
Max
_ 300
c.'-'..-l-_
300
_-'-~~I--=-
Min
ns
_~
200
110
40
ns
ns
ns
140
120
tRAS
150
10000
200
10000
ns
Column Address Strobe Pulse Width
tCAS
75
10000
110
10000
ns
r.:
10. 12
11.12
18
ns
tRP
Row Address Strobe Pulse Width
Row to Column Strobe Lead Time
Row Address Setup Time
Notes
9
+-33'-:50bO,c-t-_-+_ns=--t--~88
. 9
_________ f--_-'-CA~ __;_-..2~___=;._
tOFF
0
30
0
Row Address Strobe Precharge TIme
Units
Max
tRCo
30
75
35
90
ns
13
--.. -.--.------ - - - . r-·-t:'-Ac'S'-'R'---+--;;O-t----t--,;;-+--~r--n-s-t----l
R;-O-w---=A"'d--:;d"re-'-ssC"7'HCCO "'ld-;:-T"',-m--"e---------- -- - -- - - - --- f-----:-'R"'A=H-f---;:2"'5-+- --if-"""+---t--ns'--+----l
--.-------------t---'='-'---I-----;:!-,C"o",lu::.m",n"-,-:A:,:dc::d.c:re::s.::.s..:S:.::e.::tu"p=::--:-TI,,,m.:.:e,-_ _ _ _ ._ --.- _
-- _ _ _
_t~A~,S,-,C~_+-_-::O:-t- __ +--::o-+-_-t_n_s-t_ _ _-I
r-
f--C"u",ll.::.,m",rc.'..:.A:,:d:.::d.c:re::s.:.s-'-H"o"'ld:....:.Tc.'m..,;e=--____ - - - - _
Column A"ddress Hold Time Referenced 10 RAS
TrarlSllion Time tRlse and Falll
-- _r-~6!::LtAR
-t'T
2-42
r- .~~.
120
-
-3-'
_-i~_n--,s'-t-_ _-I
ns
ns--+--=6--t
MCM6664
AC OPERATING CONDITIONS AND CHARACTERISTICS
(See Notes 2, 3, 6, and Figure 1)
(Read, Write, and Read-Modify-Write Cycles)
(Full Operating Voltage and Temperature Range Unless Otherwise Noted)
Parameter
Symbol
MCM6664-15
MCM6664·20
Min
Max
Min
Max
-
a
-
Read Command Setup Time
tRCS
a
Read Command Hold Time
tRCH
10
10
Units
Notes
os
-
ns
14
Read Command Hold Time Referenced to RAS
tRRH
30
-
15
..
ns
14
Write Command Hold Time
tWCH
45
55
..
ns
tWr:R
120
155
ns
55
-
155
-10
ns
-
ns
15
ns
15
-
ns
ns
110
-
-
2.0
ms
-
-10
-
ns
16
55
-
ns
16
160
ns
16
ns
3BO
-
60
2000
ns
30
-
ns
-
ns
-
ns
-
ns
-
~
45
-
Write Command to Row Strobe Lead Time
tRWL
45
-
55
Write Command to Column Strobe Lead Time
tCWL
45
55
Data in Setup Time
tDS
a
Data
tDH
45
Data In Hold Time Reterenced to ~
IDHR
120
Column to Row Strobe Precharge Time
tCRP
-10
RAS Hold Time
tRSH
75
-
Refresh Period
tRFSH
-
20
Write Command Hold T 1mB Referenced to
R"A!i
Write Command Pulse Width
In
Hold Time
wmTE Command
tW...GS.
-10
rn to WRITE Delay
tCWD
45
RAS to wmTt
tRWD
125
tCSH
150
tRFD
a
REFRESH Pertod IBattery Backup Model
tFBP
2000
REFRESH to ~ Precharge Time lBattery Backup Model
tFBR
390
REFRESH Cycle Time IAuto Pulse Model
tFC
330
-
I!EmSR
IFP
60
2000
-
Setup Time
Delay
CAS Hold Time
RA'S. to ~
Delay
Pulse Pertod IAuto Pertod Model
REFRESH to ~ Setup Time IAuio Pulse Model
IFSR
30
REFRESH to RAS Delay Time IAuto Pulse Model
IFRD
390
tFI
30
tFRL
390
~ Inactive Time
~ to AEmSHLead Time
NOTES·
55
a
200
a
2000
460
460
30
460
ns
ns
ns
ns
ns
ns
ns
All voltages reterenced Ie VSS.
VIH min and VIL max are reference levels for measuring timing of Input signals Transition times are measured between VIH and
VIL
3. An initial pause of 100 "s IS required after power-up followed by any 8 AAS cycles before proper device operation guaranteed
4. Current is a funr:tlon of cycle rate and output loading, maximum current IS measured at the fastest cycle rate with the output
open.
5 OutP~t IS disabled (open-circuit! and RAS and CAS are both at a logic 1
6. The tranSition time specification applies for all tnput signals. In addition to meeting the tranSition rate specification, all Input signals must transmit between VIH and VIL (or between VIL and VIH) In a monotoniC manner.
I~
7. Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation C = ~
8.
The speCifications for tAC (min), and tAWC (min) are used only to indicate cycle time at which proper operation over the futl temperature range (Q°C:s T A:S 70°C) is assured
9. AC measurements assume tT = 5.0 ns
10. Assumes thai tRCD"'IRCD IMaxl
11. Assumes that tRCD"'tRCD IMaxl
12. Measured with a current load equivalent to 2 TTL 1+ 200 ~A. - 4 mAl loads and 100 pF IVOH ~ 2.0 V. VOL ~ - 0.8 1/1.
13. Operation within the tACO (max) limn ensures that tAAC (max! can be met. tACO (max) IS specified as a reference pOint only; if
tACO is greater than the specified tACO (max) limit, then access time IS controlled exclusively by tCAe.
14. Either tRRH or tACH must be satisfied for a read cycle
15. These parameters are referenced to CAS leading edge In random write cycles and to WRITE leading edge m delayed write or readmodify-write cycles.
16. twcs, tCWD, and tAWD are not restnctive operating parameters. They are Included In the data sheet as electrical characteriistlcs only: if twcs2':: twcs (min!, the cycle is an early wnte cycle and the data out pm will remain open CirCUit Ihigh Impedance)
throughout the entire cycle: if tcwo~ tCWD (min) and tAWD~ tAWD Imlnl, the cycle IS a read-Write cycle and the data out Will
contain data read from the selected cell; .t neither of the above sets of condItions IS satisfied, the condItion of the data out (at
access time) IS Indeterminate.
17. Addresses, data-In and WAITE are don't care. Data-out depends on the stale of CAS If CAS remainS low, the prevIous output
will remam valid. CAS is allowed to make an active to inactive transition dunng the pm 11 refresh cycle When CAS IS brought
high, the output will assume a hIgh-Impedance siate
18. toff (max! defines the time at which the output achieves the open Circuit condition and IS not referenced to output voltage levels
2-43
MCM6664
PIN ASSIGNMENT COMPARISON
MCM4516
MCM6632
REFRESH
VSS
N/C
VSS
REFRESH
10
VSS
D
CAS
D
CAS
D
15
CAS
IN
14
a
RAS
13
A6
12
A3
IN
RAS
W
0
0
1'.6
A6
AO
A3
AO
A3
AO
A2
A4
A2
A4
A2
A1
A5
A1
A5
VCC
N/C
VCC
VSS
REFRESH
CAS
D
MCM6633
N/C
1.
D
IN
a
3
11
A4
A1
10
A5
N/C
VCC
9
A7
VSS
N/C
16
VSS
CAS
D
15
a
IN
14
CAS
a
13
A6
12
A3
MCM6664
1.
IN
A6
RAS
A6
RAS
5
A3
AO
A3
AO
A2
6
A4
A2
A4
A2
A1
7
A5
A1
A5
VCC
8
A7
VCC
A7
10
9
6
MCM6665
AO
RAS
1.
1.
4.
11
A4
A1
10
A5
VCC
9
A7
6
PIN VARIATIONS
Pin Number
MCM4116
MCM461e
MCM4617
MCM8632
MCM8883
MCM8864
1
VSSI-5 VI
REFRESH
N/C
REFRESH
N!C
REFRESH
8
VDDI+ 12 VI
VCC
VCC
9
VCCI+5 VI
N/C
N/C
VCC
A7
VCC
A7
VCC
A7
On-Chip Refresh Features! Benef~.
Reduce System Refresh Controller DeSign Problem
Reduce System Parts Count
Reduce System Noise Increasing System Reliability
Reduce System Power During Refresh
2-44
MCM6886
N/C
VCC
A7
MCM6664
,
READ CYCLE TIMING
'RC
'RAS
'AR
VIH
RAS
VIL
'CSH
'RSH-
CAS
'CAS
V'H
VIL
VIH
Addresses
VIL
IN
I
VIH
~
VIL
'CAC
'RAC
a lData Ouli
'OFF
VOH
Valid
Da'a
High Z
VOL
,
WRITE CYCLE TIMING
'RC
tRAS
VIH
~
'AR
RAS
VIL
I
tRSH
l - tRP- '
'CSH
CAS
tASR
VIH
Addresses
Vil
tRAH
r
~
l--1'ASC-l
~
Row
Address
VIH
:u,
VIH
I
,1/
tCWl
f-'WCf~
I
I
--II--
-
tRwL 1
I
~~
tDS~'DH
~
VIL
/
tCAH
Address
~tw
+-tWCR
~
V
Column
I
Vil
D IDa'a Inl
~
_ ~ 'l:JJI
twcs
IN
I
1\ \
Vil
t--'CR~
tCAS
I4---'RC
VIH
l\.-
Valid
tl
Data
~~:
tDHR
a IData Oull
VOH
---------------------------------Highl--------------------------------
VOL
2-45
MCM6664
SELF REFRESH MOOE (llettery Beckupl
(SEE NOTE 171
~~'-----------~
IFBR--J ......- - - - - - VIH----------~
AUTOMATIC PULSE REFRESH CYCLE - SINGLE PULSE
(SEE NOTE 171
VIH~~~-------------------------~
i+-----------tFRD------------+i
tRFD
~----------tFP----------~
AUTOMATIC PULSE REFRESH CYCLE - MULTIPLE PULSE
(SEE NOTE 171
! + -...... tFSR
RAS-ONL Y REFRESH CYCLE
(ON-In .nd WRITE ... Don't Ca ... CAl ia H(GHI
..-------IRC------~-~
VIH""".........." "
ADDRESSES,
A(}A6
2-46
MCM6664
REAO-WRITE/REAO-MOOIFY-WRITE CYCLE
...
-_
-_
-_
-_
--lR
C
-_
-_
-_
-_
-___
- - - - - - - - - - - - - -__
.._
_____-IRAS
_ _W
___
__
m
VIH
~~__------IAR
~
VIL
IRSH
ICSH
CAS
ICAS --------------.1
VIH
VIL
VIH
Addresses
VIL
VIH
W
VIL
L,-
o IData Inl
'I
2-47
MCM6664
MCM6664 BIT ADDRESS MAP
Row Address A 7 A6 AS A4 A3 A2 A 1 AO
Column Address A7 A6 A5 A4 A3 A2 Al .6.0
Column Add,","
Row
Hex
~
..
~if!
"'~
NN.
0-
0-
--------
AO
.1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
1
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
7F
127
126
125
0
0
0
1
1
1
1
1
1
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
··
··
·
···
···
04
03
02
01
3
2
1
0
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
0
0
0
0
~8b~8Z808
.a:><.O ......
c
~
16,384·811 Memory
Array
'0
recharg
Clock
D ..
'0
112 t 1 01 256)
Column Decoder
16,3i::\4·811 Memory
Array
0
~
-
PIN NAMES
....... Address Inpu1
oata In
.... Data Out
Read/Wllte Input
o •••••
. .... Row Address Strobe
.. Column Address Sirobe
.. Power 1+5 VI
... Ground
-+ Output
E
.=
'0
Sense Ampliller
AD-A7 ...
g I-i
a:
~
...
MCM6664 aVCC trace should go to pin II.
r-Sense
Sense Amplifier
'---
Data, 0
This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however,
it is advised that normal precautions be
taken to avoid application of any voltage
hrgher than maximum rated voltages to
this high-Impedance CirCUIt.
DS9824/9-8O
2-49
MCM6665
FIGURE I - OUTPUT LOAD
ABSOLUTE MAXIMUM RATINGS ISee Notel
Raling
Symbol
Velue
Unit
Voltage on Any Pin Relative to VSS (Except VCCI
Vin. Vout
-210+7
V
Voltage on VCC Supply Relatiye to VSS
Vin. Yout
- I to +7
V
Tst9
Po
-65 to +150
'c
Power Dissipation
1
W
Data Out Current
lout
50
rnA
Storage Temperature Range
5V
9700
Q------~~~--.
100 pF'
NOTE: Permanent deVice damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restncted to RECOMMENOED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
-Includes Jig Capacitance
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted.)
RECOMMENDED OPERATING CONDITIONS
Parlmeter
Symbol
Min
Typ
Max
Unit
NOI..
VCC
VCC
VSS
4.5
4}5
0
5.0
5.0
0
5.5
5.25
0
V
I
I
Logic I Voltage, All Inputs
VIH
2.4
-
VCC+l
V
I
Logic 0 Voltage, All Inputs
VIL
0.8
V
I
Supply Voltage
M CMS665L I 5/ M CMS665L20
M CMS665L I 5-5/ M CM6665L20-5
2.0
DC CHARACTERISTICS (Full Operating Voltage and Temperature Ranges Unless OtherWise Notedl
Symbol
Characteristic
VCC Power Supply Current (tRC min.1
ICCI
Standby VCC Power Supply Current
ICC2
VCC Power Supply Current During
I1AS
Only RefreSh Cycles
Min
Max
Unit.
Not..
-
50
mA
4
5
mA
5
40
mA
-
ICC3
IIiLi
-
10
~A
10
~A
Output Logic I Voltage @ lout - - 4 mA
10(L1
VOH
2.4
-
V
Output Logic 0 Voltage @ lout = 4 mA
VOL
-
0.4
V
Input Leak.age Current (any input) (0::5 Vin::5 5.5) (Except Pin 11
Output Leakage Current IOsV out s5.5HCAS at Logic II
AC OPERATING CONDITIONS AND CHARACTERISTICS
(See Notes 2, 3, 6, and Figure I I
(Read, Write, and Read-Modify-Wnte Cycles I
(Full Operating Voltage and Temperature Range Unless Otherwise Notedl
Parameter
Symbol
Random Read or Write Cycle Time
tRC
Read Write Cycle Time
Access Time from Row Address Strobe
tRwe
tRAC
Access Time from Column Address Strobe
tCAC
tOFF
Output Buffer and Turn-Off Delay
Row Address Strobe Precharge Time
Row Address Strobe Pulse Width
tRP
tRAS
Column Address Strobe Pulse Width
Row to Column Strobe Lead Time
tCAS
tRCD
Row Address Setup Time
tASR
Row Address Hold Time
Column Address Setup Time
tRAH
tASC
tCAH
tAR
tT
Column Address Hold Time
Column Address Hold Time Referenced to
rn
Transition Time (Rise and Falll
2-50
MCM6f1116. I 5
Min
Ma.
MCM6fIII6.20
Units
Min
Max
300
300
-
35Q
-
-
t50
350
-
--
ns
200
110
I\S
0
120
150
30
10000
10000
75
-
0
140
40
10000
10000
120
-
200
110
35
0
30
0
55
155
ns
ns
ns
3
50
:i
50
75
30
0
25
0
45
75
-
-
ns
ns
90
ns
ns
-
ns
-
ns
ns
ns
ns
ns
Not..
8,9
8,9
10, 12
11. 12
t7
13
-
6
UCM6665
AC OPERATING CONDITIONS AND CHARACTERISTICS
ISee Notes 2,3,6, and Figure II
(Read. Write, and Read-Modlfy-Wrlte Cycles)
(Full Operating Voltage and Temperature Range Uriless Otherwise NotedJ
Parameter
Symbol
Read Command Setup Time
Read Command Hold time
Read Command Hold Time Referenced to
i'fAS
Write Command Hold Time
Write Command Hold Time Referenced to RAS
-
Write Command Pulse Width
Write Command to Row Strobe Lead TIme
Wnte Command to Column Strobe Lead Time
Min
tRCS
0
-
ns
-
10
-
0
tRCH
10
--
ns
ns
14
14
ns
ns
-
ns
-
-
ns
-
-
ns
15
ns
15
ns
-
tRRH
30
tWCH
45
-
tWCA
120
-
55
155
twp
45
-
55
tAWL
45
45
-
55
Data In Hold Time Aeferenced to RAS
tDHR
0
45
. 120
Column to Row Strobe Precharge Time
'CAP
- 10
'RSH
tRFSH
lIAS
Hold Time
Refresh P-eflod
WAITE Command Setup Time
..-
CAS to WRITE Delay
IfAS to WRITE Delay
CAS' Hold Time
I-;--'---:--;;-
Input Capacitance 1t3;S,
Parameter
0
CAS', wmTE
OUlpul Capacitance 101 ICAS = VIH to disable output!
35
55
0
ns
-10
75
-
110
-
ns
-
2.0
-
2.0
twcs
tCWD
- 10
- 10
-
16
tRWD
125
ns
ns
16
16
tCSH
150
-
ms
ns
ns
-
45
CAPACITANCE if= 10 MHz TA=25'C VCC=5 V Periodically Sampled Rather Than 100% Tesledl
----
~~t Capacllance IAO-A71,
Ma.
-
tDH
- -
Units Notes
Ma.
tDS
Data in Hold Time
MCM6666-20
Min
tCWL
Dala In Selup Time
MCM6666-15
55
155
55
160
ns
-
200
Symbol
Typ
Ma.
Units
C'l
CI2
4
5
pF
7,
8
10
pF
7
Co
5
7
pF
7
Notes
NOTES:
I. All voltages referenced to VSS.
2 VIH min and VIL max are reference levels for measuring timing of input Signals. Transition times are measured between VIH and
VIL·
3. An initial pause of ·100 1'5 is required after power-up followed by any 8 RAS cycles before proper deVice operation guaranteed.
4. Current is a function .of cycle rate and output laading; maximum current is measured at the fastest cycle rate with the output
open.
5. Output is disabled lopen-circultl and RAS and CAS are both at a logic 1.
6 The transition time specificatian applies for all input signals. In addition t.o meeting th~ transitian rate specification, all.nput signals must transmit between VIH and VIL (or between VIL and VIH) in a manotonic manner.
Capacitance measured with a B.oonton Meter .or effective capacitance calculated from the equation. C = ~
8
9.
10.
11.
12
13.
14.
15.
16.
The specificati.ons for tAC (min), and tAWC (min) are used .only to indicate cycle time at which proper operation over the full temperature range (Q°C:sTAS70°C) is assured.
AC measurements assume tT = 5.0 ns.
Assumes that tACO" tRCD Imaxl.
Assvmes that tRCD'" tRCD Imaxl.
'Measured with a current load equivalent to 2 TTL loads 1+200 ~A, - 4 mAl and 100 pF (VOH = 2.0 V, VOL = - 0.8 VI
Operation within the tACO (max) limit ensures that tRAC (maxI can be met. tRCD Imax) is specified as a reference point only,
tACO is greater than the specified tRCD (max) limit. then access time is controlled exclusively by tCAC
Either tRAH or tACH must be satisfied for a read cycle.
These parameters are referenced to CAS leading edge in random write cycles and to"'W'Ai'IT leading edge in delayed write or readmadify-write cycles.
tWCS. tCWD, and tRWD are not restrictive operating parameters. They are included in the data sheet as electrical characten·
istics .only: if
~
Imln). the cycle is an early write cycle and the data out pin will rer::naln open cirCUIt (high impedance)
throughout the entire cycle; if tCWD~tCWD (min) and tRWD~ tRWD Imin), the cycle is a read-write cycle and the data out Will
contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the ·data out (at
access time) is indeterminate.
taff (max) defines the time at which the output achieves the open circuit canditlon and is not refp.renced to .output valtage levelS
twcs twcs
17.
2-51
MCM6665
PIN ASSIGNMENT COMPARISON
MCM4516
REFRESH
VSS
NIC
MCM4517
16
VSS
REFRESH
0
CAS
0
15
CAS
D
a
W
RAS 4
AO
W
A6
14
a
13
A6
RAS
1.
MCM6632
16
VSS
15
CAS
14
a
W
12
A3
AO
12
A3
AO
4
A6
A3
A2
6
11
A4
A2
11
A4
A2
6
A4
Al
7
10
A5
Al
10
A5
A1
7
A5
VCC
8
9
N/C
VCC
8
A7
16
VSS
N/C
0
8
9
N'C
VCC
16
VSS
REFRESH
0
15
CAS
0
15
CAS
W
14
a
W
14
a
RAS
13
A6
1.
MCM6633
NIC
1.
MCM6664
1.
MCM6665
W
RAS 4
A6
16
VSS
15
CAS
14
a
13
A6
A3
AD
5
12
A3
AO
A3
AO
5
12
A2
6
11
A4
A2
A4
A2
6
11
A4
A1
7
10
A5
A1
A5
A1
10
A5
VCC
8
9
A7
VCC
A7
VCC
9
A7
8
PIN VARIATIONS
Pin Number
1
8
9
MCM4118
VBBI-5 VI
Voot+ 12 VI
VcCt+5 VI
MCM4618
MCM4617
MCM8832
MCMeee3
MCMe884
RmIESH
N/C
rnlWSH
N/C
~
N/C
VCC
VCC
N/C
N/C
VCC
A7
VCC
A7
VCC
A7
VCC
A7
2-5?
MCMeeeI
.MCM6665
REAC CYCLE TIMING
tRC--tRAS
RAs
VIH
VIL
tAR
i
tRSH"
m
tCAS·
VIH
VIL
2-53
MCM6666
RAS·ONL Y REFRESH CYCLE
10.,.·,n and Wriii Ire Don" Cara. CAS il HIGH I
L.~'------------IAC------------------~
Addresses,
AO·AS
REAO·WRITEIREAO·MOOIFY·WRITE CYCLE
RAS
VIH
'RAS
IAWC
-!
'AA
, VIL
IRSH
'CSH
CAS
ICAS
VIH
VIL
Column
Addresses
VIL
Address
~---------T--~I-IRWD----------------~
j4
VIH
W
VIL
l-t
tCWD----....~
cAc ______
D lOata Inl
2-54
MCM6666
MCM8666 BIT ADDRESS MAP
Pm 8
D
Row Address A 7 A6 A5 A4 A3 A2 A 1 AO
Column Address A 7 A6 AS A4 A3 A2 A 1 AO
Cotumn Addreues
He.
Row
Dec
254
255
FE
FF
ilj:il
.'
etw~en VIH and
VIL
_
An .,llllal pause 01 100 "S IS rCllu'fed aller power up followed Py any 8 RAS cvc!es before I..HOPt'l dpvrc~! upercttron
4
5
6
open
Output IS disabled lopen cllcUlII and RAS alld CAS dlt! bOlt) dt d ~oylc 1
Ttle tranSition lime speclflcatlun applies tOI alllflput Signals In addltlOfI In Illt~t't,ny ttw IldliSttlllll Idlp SpP.t.:tfICHIllIn dlllnPlii SlY
nals must IranSrTtil between VIH and Vll (or between Vll and V'HI In (I IlIt)llO!lHlIC manner
Capacltanct; measured Wlttl a 8(lunllln Metel 01 efft=!cltve capaCltiillCf> calculated hum Itle equ.lII.)P C
9
10
11
12
13
14
lb
16
17
4l.i.Hrlnleed
Cllrrent 1<; a 'llllClllln 01 cyCle rate and output loadlllQ. maJ(lmum ClHIHll1 rR m~asured at the Ic:lSlest \'ycip fd:€, Witt) HlP dulpul
~
The speclftcallons flH tRC Imlnl, arId 'AWC hnml die used l)llly ttl IIldl t :;HP eycle tUlIt' at which propt!1 lJL1eration over ttle Ililltem
perature range 10"(:s T A:S 70"CI 15 assured
•
AC measurements assume t 1 =- 5 0 flS
Assumes thallRCDsIRCD (inax}
Assumes that tRCO~ tRCo (maxI
,
Measured with a currenl load eqUivalent 10 2 TTL loads 1+ 200 ~A ..- 4 mAl and 100 pF IVOH 2.0 V. VOL
0.8 VI.
Operation Within the IRCD (max; 1111111 ensures that !RAC (max! can be me! tReD lrnax) IS speClflp.d as a reference pOint only,
tRCD rS grealer than the speCified tRCD (maxllH"It, then access 11:lIP. IS <,ontlOlied exclUSively hy tCAC
E.ither tARH UI tACH must be satisfied fOI a lead cyclt-!
These pararnelf!1S ale retcrenr:ed 10 CAS leadllig edge JrtI,Hl(h l l1l wrlll! cyclt.!S arid tLl WRl1 E 11'iHlln\,} mlge If, dp.layed Wille or read·
modify wllte cycles
IWCS. tCWD, and lRWD are not reS!lIctlve Opcl!IC'> Dilly If 'wcs ~ twcs Imml, the cycle IS an early Wille c\,cle ,111(1 the dilla Ollt pin Will remalll Oppl) CIrCUit lhlgtl Impedancel
throughout tile tlnlHe cycl~, 'ItCWD~ tewD (nunl ..Uld tRWD~ tAWD (l1l1ftl. Ihe cycle IS a ledd write cycle 1nd Ihe data oul Will
contatn data lead hrlm Ihe selected cell, II ra!ttllet of Itle abo ....H ')I
0-
0-
--------
-----.-
•
. . . . ..
1
251
248
249
1
1
1
130
131
128
129
1
1
1
1
0
0
0
0
0
0
0
0
127
126
125
0
0
0
1
1
1
4
3
2
1
0
0
0
0
0
0
0
0
··•
··
···
···
··
u
00
250
1
1
1
1
1
1
1
1
··
·
···
83
c
E
253
1
1
1
1
252
80
81
A7 AI A3
0
0
0
1
1
,
1
1
1
1
,
A4 AS A:l AIJ A1
1
1
I
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
1
0
1
0
0
0
0
0
0
-00000000
000000000
·000000000
000000000
000000000
Data Stored - Dine Aoxe A,y
DIIUI
Stored
1
o
Invl3rted
True
True
Inverted
2-62
1
1
0
1
0
0----0000
o
0
0
00..-.-00--0
o
o
1
1
0
0
0
0 - - 0 0 __ 00
Column
Add...
A1
0
0
1
0
0
0
0
.CO\Dr-.\J")~N(",).-O
00
0
0
0
1
1
0
0
0
0
0
0
~8~~!aB58
-
1
1
1
1
0
0
a
1
0
1
"
'([5)
MCM2114
MCM21L14
MOTOROLA
MOS
4096-81T STATIC RANDOM ACCESS MEMORY
The MCM2114 is a 4096-bit random aCCeSS memory fabricated with
high density, high reliability N-channel silicon-gate technology, For ease
of use, the device operates from a single power supply, is directly compatible with TTL and DTL, and requires no clocks or refreshing because
of fully static operation, Data access IS particularly simple, since address
setup times are not required The output data has the same polaruy as
the Input data,
The MCM2114 is designed for memory applications where simple interfacing is the design oblectlve, The MCM2114 is assembled In 18-pln
dual-in-line packages with the industry standard pin-ouL A separate
chip select 1~llead allows easy seJectlon of an individual package when
the three-state outputs are OR-tied,
The MCM2114 senes has a maximum current of 100 mA, Low power
versions li,e" MCM21L 14 seriesl are available with a maximum current
of only 70 mA
• 1024 Words by 4-81t Organization
• Industry Standard 18-PIn ConfiguratIOn
IN-CHANNEL, SILICON-GATE I
4096-BIT,STATIC
RANDOM ACCESS
MEMORY
-
_.-<,,--'-.
• Single + 5 Volt Supply
• No Clock or Timing Strobe Required
.• ~
/
• Fully Static, Cycle Time = Access Time
• Maximum Access Time
MCM2114-20/MCM21 L 14-20200
MCM2114-25/MCM21L14-25 250
MCM2114-30/MCM21L 14-30 300
MCM2114-45/MCM21 L14-45450
• Fully TTL Compatible
..~,~
PLASTIC PACKAGE
CASE 701
r,]11 :
ns
ns
ns
ns
'"'AX
CERAMIC PACKAGE
CASE 680
• Common Data Input and Output
PIN ASSIGNMENT
• Three-State Outputs for OR-Ties
• Low Power Version Available
A6
[iiV1a
A5 2
BLOCK DtAGRAM
A9~1~5~_____{~:j------Vee
A4 ~3_______
A6
Vss -
Pin 18
Ping
"'-----1
A4
3
16 AS
A3
4
t5
AO
5
14 001
Al
6
13 002
A2
7
12
-S 8
11
004
10
W
VSS
17
A7-------1
16
AS --------1
Vee
17 A7
9
A9
003
14
oOt---~--I~r
I
PIN NAMES
002 _'",3_H-+-l
AOA9
Iii
S
004 _-++++-1
001,004
Vee
V~
'0
w---~_'
Address Input
Wnte Enable
ehlp Select
Data Input/Output
Power (+ 5 VI
Ground
AO Al A2 A3
059800/1 79
2-63
MCM2114-MCM21 L14
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating
Temperature Under Bias
Voltage on Any Pin With Respect to VSS
Valua
Unit
-10to +80
'C
-0.5 to + 7.0
V
5.0
mA
1.0
Watt
DC Dutput Currant
Power Dissipation
o to
Operating Temperature Range
+ 70
-65 to +150
Storage Temperature Range
This device contains circUItry to protect
the Inputs against damage due to high
static voltages or electric fields; nowever,
It IS advised that normal precautions be
taken tv avoid application of any voltage
higher than maximum rated voltages to
this high-Impedance Circuit
'c
'C
NOTE' Permanent devIce damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded. Funcllonal operation should be restncted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted.1
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Supply Voltage
•
LogIc 1 Voltage, All Inputs
LogIc 0 Voltage, All Inputs
Svmbol
Min
Typ
Max
Un,
VCC
VSS
4.75
0
5.0
0
5.25
0
V
6.0
V
08
V
-
VIH
2.0
VIL
-05
DC CHARACTERISTICS
Symbol
Parameter
MCM2114
·Min TVp
Max
ICC2
-
Output Low Current VOL = 0.4 V
IOL
21
Dutput HIgh Current VOH = 2.4 V
IOH
-
Input Load Current (All Input PinS, V ln = 0 to 5.5 Vl
III
1/0 Leakage Current (S = 2.4 V, VDO = 0.4 V to VCe!
ilLOI
Power Supply Current (V,n - 5.5 V, (DO - 0 mA, T A - 25'CI
ICCI
Power Supply Current (V ,n -5.5 V, IDO-O mA, TA=O'C)
NOTE: Duration not to exceed
MCM21L14
Typ Max
Min
-
100
-
-
-
2.1
60
' <. .
10
-
10
80
95
6.0
-1.4 -10
-
10
Unit
~A
10
~A
65
mA
70
mA
-
mA
-1.4 -1.0
mA
30 seconds
CAPACITANCE If = 1.0 MHz, TA = 25'C. perlodlcaliy sampled rather than 100% tested)
Characteristic
Input Capacitance IV In = 0 V)
InputlOutput CapaCItance (VDO = 0 V)
Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation
AC OPERATING CONDITIONS AND CHARACTERISTICS
IFuli operating voltage and temperature unless othelw,se noted.1
Input Pulse Levels
Input Rise and Fall Times.
08 Volt to 2.4 VailS
10 ns
Input and Output Timing Levels
Output Load
15 Volts
1 TTL Gate and CL = 100 pF
READ (NOTE 1) WRITE (NOTE 2) CYCLES
Parameter
Symbol
MCM2114-20
MCM21 L14·20
Min
Max
Address Valid to Address Don't Care
'AVAX
200
Address Valid to Output Valid
tAVOV
-
Chip Select Low to Data Valid
'SLOV
MCM2114-25
MCM21 L14-25
Min
Max
250
200
-
70
20
MCM2114·JO
MCM21 L14-JO
Max
Min
85
20
..
Unit
450
-
300
-
450
ns
100
-
120
ns
300
250
MCM2114·45
MCM21 L14-45
Min
Max
ns
20
20
ns
Chip Select Low to Output Don't Care
tSLOX
Chip Select High to Output High Z
tSHOZ
Address Don't Care to Output Hlg~l Z
tAXOZ
50
50
50
Write Low to Write High
tWLWH
120
135
Write High to Address Dan', Care
tWHAX
20
20
Write Low to Qutput High Z
'WLQZ
Data Valid to Wflte High
tDVWH
t20
130
150
200
ns
Write High to Data Don'T
tWHDX
0
0
0
0
ns
50
50'
NOTES 1. A Read occurs dunng the overlap 01 d low S" and (;I ~llgtl W
A Write occurs dUring the overlap 01 a low S and a low W
2-64
80
-
..
50
ns
150
200
ns
20
20
70
ns
ns
100
80
10
100
ns
:M2114-MCM21 L14
READ CYCLE TIMING
ilii HELD
HIGHI
~--------------'AVAX------------~"
~-----------'AVOV----------~"
Address
o
WRITE CYCLE TIMING INOTE 31
4
'AVAX
Address
\\\\\\\\\\\\\\' .\\ \)
w
o
rlllll; '17/7717777777;
1
'WLWH
'III-
\\\"Y
-
_'WHAX
'WLOZ
---
'WHDX
'DVWH
D
3. If the"S low tranSition occurs simultaneouSly with the W !ow lran51110n. the output buffers rem~ln In a hrgtHmpedance state.
WAVEFORMS
Waveform
Input
Qutp'··
Symbol
MUST
~
~
~
8~
VALID
CHANGE
fHOM,", TO L
WILL CHANGt
fHOMHTOL
CH~NGf
fHOM l '0 "
\)ON T CAHt
CHA""G~
~ROM
I
'0"
CHANGING
STAH
PffIMITTf.D
UNKNOWN
HIGH
tMPfOANn
F:;
r::
~.
WILL
ANY CHANGE
=:J--
t·
WILL Bf
VAt It)
2-65
MCM2114-MCM21 L14
TYPICAL CHARACTERISTICS
SUPPL Y CURR ENT v.rsus SUPPL Y VOLTAGE
80
=<
.§.
>-
!
=<
15
- -- -
10
-
~
~
65
...~
z
'"
-
~
~
4.75
5.0
VCC. SUPPL Y VOLT AGE (VOL TSI
5.25
7.0
I'-....
............
............
S5
o
20
40
TA. AMBIENT TEMPERATURE (OC)
OUTPUT SINK CURRENT versus OUTPUT VOL TAGE
1\
B.O
\
\
\
7.0
\
=<
5.0
1
4.0
'"
'"=>
I
:::I
~
:::I
3.0
E
2.0
5.0
u
'"z
\
\
\
\
~
>-
;;;
>- 4.0
~
0
-"
E
3.0
2.0
\
1.0
1.0
\
2.0
i
1.0
\.
o
30
4.0
VOH. OUTPUT VOLTAGE (VOLTSI
o
5.0
/
V
/
/
.§.
>z
-- - -
B
~
/
6.0
=<
:;
III
60
9.0 r - - -
6.0
'"
..........
60
5.5
8.0
0
........
~
OUTPUT SOURCE CURRENT ".rsus OUTPUT VOL TAGE
:::I
'"
50
4.5
~
..........
65
'"u=>
60
.§.
>~
............
....
>
~
............
70
.§.
~
'"
B
SUPPLY CURRENT versus AMBIENT TEMPERATURE
75
II
o
6.0
2-66
/
V
0.1
/
/
0.2
0.3
0.4
VOL. OUTPUT VOLTAGE (VOLTSI
0.5
0.6
MCM2114.MCM21 L14
,
TYPICAL ACCESS TIME versus TEMPERATURE
NORMALIZED ACCESS TIME versus TEMPERATURE
--
1.0
-7
-.-
/"
~
..
/V
~
0.85
"'"
Z
0.80
0
...... V
./
14
I
0.1 5
o
20
40
TA. TEMPERATURE (OCI
°v
........-
13 0
20
80
60
V
./
V
/
V
40
60
TA. TEMPERATURE (OCI
80
MCM2114/MCM21L14 BIT MAP
PIN 18
PIN 1
Vee
D
D
1008 1023 01(
1007
1023 ..
1007
D03 IPIN NO. 121
1008 1023 ..
1007
1008 1023 ..
1007
D04 IPIN NO. 111
1008
D02 (PIN NO. 131
DOl (PIN NO. 141
,
15
..
16
0 15
16
01(
16
0 15
0 15
01(
..
16
0
To determine the precise location on the die.of a word in memory. reassign address numbers to the address pins as
in the table below. The bit locations can then be determined directly from the bit map.
PIN NUMBER
~,
1
2
4
5
REASSIGNED
ADDRESS NUMBER
PIN NUMBER
A6
AS
A4
A3
AO
",
~'
2-67
--
L
160
./
0.90
.,."
j.
/
/
,.~ 0.95
~
17 0
REASSIGNED
ADDRESS NUMBER
6
Al
A2
15
16
17
A9
Ali
10
90
®
MCM2115A
MCM21L15A
MCM2125A
MCM21L25A
MOTOROLA
1024 x 1 STATIC RAM
MOS
The MCM2115A and MCM2125A families are high-speed, 1024 words
by one-bit, random-access memories fabricated using HMOS, highperformance N-channel silicon-gate technology. Both open collector
IMCM2115A) and three-state output IMCM2125A) are available. The
devices use fully static circuitry throughou.t and require no clocks or
timing strobes. Data out has the same polarity as the input data.
Access times are fully compatible with the industry-produced 1K
Bipolar RAMs, yet offer up to 50% reduction in power over their Bipolar
equivalents.
All inputs and output are directly TTL compatible. The chip select
allows easy selection of an individual device when outputs are OR-tied.
IN-CHANNEL, SILICON-GATE)
1024-BIT STATIC
RANDOM ACCESS
MEMORY
-
• Organized as ;024 Words of 1 Bit
• Single + 5 V Operation
• Maximum Access Time of 45 ns, 55 ns, and 70 ns available
16'
• Low Operating Power DiSSipation
• Pin Compatible to 93415A 12115A) and 93425A 12125A)
I
,:
Ii:
I
I'
1'
• TTL Inputs and Outputs
• Uncommitted Collector 12115A) and Three-State i2125A) Output
C SUFFIX
FAIT·SEAl
CEAAMIC PACKAGE
CASE 620,'06
BLOCK DIAGRAM
PIN ASSIGNMENT
s[rii'-'""i6 Pvcc
AO[2
15 pO
Al[ 3
14 ~W
A2
0
4
A3
A4
6
0
13 JA9
12
AS
11
A7
10
VSS 8
AOAI A2 A3 A4
A5 A6 A7 AS A9
PIN NAMES
TRUTH TABLE
S
Inputs
W
A6
A5
Output
2115A Family
Output
2125A Family
Q
Q
High Z
High Z
High Z
Data Out
H
X
X
H
L
L
L
L
L
L
H
H
X
H
H
Data Out
A
D.
Mode
Not Selected
Write "0"
o
S
VCC
VSS·
W
. Address
. Data Input
Data Output
Chip Select
+ 5 V Supply
. Ground
... Write Enable
Write"'"
Read
059819/5-8)
2-68
~CM2115A·MCM21L15A·MCM2125A·MCM21L25A
ABSOLUTE MAXIMUM RATINGS ISee Notel
Rating
Temperature Under Bias
Voltage on Any Pin With Respect to VSS
Value
Unit
-IOta +80
·C
-0.5 to + 7.0
Vdc
DC Output Current
20
mA
Power Dissipation
1.0
Watt
o to
Operating Temperature Range
Storage Temperature Range
NOTE:
This device contains circUitry to protect the inputs against damage due to high static voltages
or el~ctrlc fields; however, It IS advised that normal prtlcautlons be taken to aVOid application of
any voltage higher than maximum rated voltages
to this high-impedance circuit.
'c
+ 70
-65to +150
·C
Permanent damage may occur if ABSOLUTE MAXIMUM RATINGS
are exceeded. Functional operation should be restricted to RECOMMENDED OPERA TlNG CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could -affect device
reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted I
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Min
Typ
Max
Unit
Supply Voltage
VCC
VSS
4.75
0
5.0
0
5.25
0
V
Logic 1 Voltage, All Inputs
VIH
2.1
6
V
Logic 0 Voltage, All Inputs
VIL
-03
-
O.B
V
Parameter
DC OPERATING CHARACTERISTICS
Parameter
Symbol
Input Low Current (All Input PinS, Vrn =0 to 5.5 V)
IlL
Input High Current
IIH
Output Leakage Current (V out = 0.5/2.4 VI
IOL
Output Leakage Current IV out ~ 4.5 VI
Power Supply Current 15- VIL, Outputs Open T A - 25'CI
Output Low Voltage IIOL~7.0 mA, 2125A, 16 mA 2115AI
ICEX
ICC
VOL
Output High Voltage IIOH - - 4.0 mAl
VOH
Current Short Circuit to Ground
lOS
MCM2115A MCM21L15A MCM2125A MCM21125A
Unit
Min
Max
Min
Max
Min
Max
Min
Max
-
-40
40
-
-40
40
-40
40
-40
40
-
50
~A
100
-
-
-
~A
-
-
100
125
-
75
-
0.45
-
50
125
~A
-
~A
75
mA
0.45
-
0.45
-
0.45
V
-
2.4
-
2.4
-
V
-
-100
-
-100
mA
MCM2115A FAMILY AC OPERATING CONDITIONS AND CHARACTERISTICS, READ, WRITE CYCLES
ITA=Ot070'C VCC~50V ±5%1
Parameter
Symbol
MCM2115A-'15
MCM2115A·56
Min
Max
Min
Max
MCM2115A-70
Unit.
Min
Max
Chip Select Low Output Valid
tSLOV
5
30
5
35
5
ns
Chip Select High to Output Invalid
tSHOZ
-
30
-
35
Address Valid to Output Valid
tAVOV
-
45
-
55
-
40
40
70
ns
Address Valid to Output Invalid
tAVOX
10
-
10
-
10
-
ns
Write Low to Output Disable
tWLOZ
-
30
-
-
40
ns
Write High to Output Valid
tWHOV
0
30
0
0
45
ns
Write Low to Write High (Write Pulse Width)
tWLWH
30
-
40
50
-
ns
ns
D8ta Valid to Write Low
tDVWL
5
-
5
Write High to Data Don't Care IData Holdl
tWHDY.
5
-
5
35
35
-
Address Valid to Write Low IAddress Setup I
tAVVVL
5
5
-
15
Write High to Address Don't Care
tWHAX
5
5
_.
ns
tSLWL
5
5
-
ns
Write High to Chip Select High
tWHSH
5
-
5
-
5
Chip Select Low to Write Low
-
5
-
ns
Address Valid to Address Don't Care
tAVAX
45
-
55
-
70
ns
Chip Select Low to Chip Select High
tSLSH
-
45
-
55
-
70
ns
2-69
5
5
5
ns
ns
ns
MCM2115A-MCM21 L15A-MCM2125A-MCM21 L25A
,
MCM21Ll6A FAMILY AC OPERATING CONDITIONS AND CHARACTERISTICS, READ, WRITE CYCLES
IT A=O to 70·C VCC=50 V ±5%1
Pa.. meter
Symbol
c::hip Select Low to Output Valid
MCM21 L15A-<46 MCM21L15A-70
Unila
Min
Min
Max
Ma.
5
Chip Select High to Output Invalid
tSLaV
tSHQZ
-
Address Valid to Output Valid
tAVQV
-
Address Valid to Output Inva id
tAVQX
10
Write Low to Output Disable
tWLQZ
-
30
30
45
5
-
30
30
70
ns
ns
ns
ns
10
25
25
-
25
ns
0
25
ns
-
30
-
ns
-
Write High to Output Valid
tWHQV
0
Write Low to Write High (Write Pulse Width I
tWLWH
30
Data Valid to Write Low
tDVWL
0
Write High to Data Don't Care
tWHDX
5
Address Valid to Write Low (Address Setup I
tAVWL
5
Write High to Address Don't Care
tWHAX
5
Chip Select Low to Write Low
tSLWL
5
Write High to Chip Select High
tWHSH
5
Address Valid to Address Don't Care
tAVAX
-
45
Chip Select Low to Chip Select High
tSLSH
-
45
0
5
5
5
5
5
ns
ns
ns
ns
ns
70
ns
ns
70
ns
MCM2126A FAMILY AC OPERATING CONDITIONS AND CHARACTERISTICS, READ, WRITE CYCLES
(TA-Ot070·C
VCC=50V ±5%1
-
Pa.. meter
Symbol
MCM2125A-<46 MCM2125A-66 MCM2125A-70
Min
Ma.
Min
Ma.
Min
Ma.
ns
ns
ns
50
40
45
-
5
-
ns
5
-
ns
-
-
10
-
10
30
30
-
35
35
-
30
-
5
-
40
5
tWHDX
tAVWL
5
-
5
-
Write High to Address Don't Care
Chip Select Low to Write Low
Write High to Chip Select High
tWHAX
5
tSLWL
tWHSH
5
5
Address Valid to Address Don't Care
tAVAX
tSLSH
-
tSLQV
5
Chip Select High to Output High Z
tSHQZ
-
Address Valid to Output Valid
tAVQV
-
Address Valid to Output Invalid
tAVQX
10
Write Low to Output High Z
Write High to Output Valid
tWLOZ
-
tWHQV
0
Write Low to Write High (Write Pulse Width I
tWLWH
Data Valid to Write Low
tDVWL
Write High to Data Don't Care
Address Valid to Write Low (Address Setup I
Chip Select Low to Chip Select High
30
30
45
-
5
5
-
0
-
5
-
5
45
45
-
5
-
0
ns
ns
ns
ns
ns
15
5
Unila
40
40
70
-
5
35
35
55
Chip Select Low to Output Valid
5
-
5
-
ns
ns
-
70
ns
70
ns
-
5
55
55
ns
MCM21L25A FAMILY AC OPERATING CONDITIONS AND CHARACTERISTICS, READ, WRITE CYCLES
ITA=O to 70·C, VCC=5.0 V ±5%1
Pa .. meter
Symbol
Chip Select Low to Output Valid
MCM21 L2&A-<46 MCM21 L2&A-70
Unila
Min
Ma.
Min
Ma.
30
30
70
ns
10
-
ns
25
25
-
25
25
ns
n.
30
-
ns
5
5
-
tSLWL
5
Write High to Chip Select High
tWHSH
Address Valid to Address Don't Care
tAVAX
Chip Select Low to Chip Select High
tSLSH
5
tSLQV
tSHQZ
-
Address Valid to Output Valid
Address Valid to Output Invalid
tAVQV
-
tAVQX
10
Write Low to Output High Z
Write High to Output Valid
Write Low to Write High (Write Pulse Width I
tWLQZ
tWHQV
-
tWLWH
30
Data Valid to Write Low
tDVWL
0
Write High to Data Don't Care
tWHDX
5
Address Vahd to Write Low (Address Setup I
Write High to Address Don't Care
tAVWL
tWHAX
Chip Select Low to WritB Low
Chip Select High to Output High Z
2-70
0
30
30
45
-
5
0
0
5
-
ns
ns
ns
ns
-
ns
-
5
5
-
5
-
5
-
ns
ns
-
45
-
70
ns
45
-
70
ns
5
ns
MCM2115A-MCM21 L15A-MCM2125A-MCM21 L25A
CAPACITANCE 11=1.0 MHz, TA=25°C, periodically sampled rather than
100% tested.!
OUTPUT LOAD
Vce
Characteristic
Input Capacitance IVin = 0 VI
30011
Output Capacitance IVout=O VI
2115A
Capacitance measured with a Boonton Meter or effective capacitance calculated
0---+---4
from the equation: C=I"'tILW.
600
30 pF
Oncluding
scope and Jig I
2115A FAMILY
READ CYCLE TIMING 1
(~ Held Low, W Held High!
Address
Q IData Out)
READ CYCLE TIMING 2'
(W Held High!
-~~~~~~~~~----~;;;,;,~-----VOH
Previous Data Valid
Data Vahd
~------------------------------------------3.5V
Address~_ _ _ _._ _ _ _ _A_d_d_re_ss_v_al_id_ _ _ _ _ _ _ _ _ _ 0 V
[:_~""
t--J-IS-H-O-;-:: V
VOH
'\
Data Valid
~--------'
,0 IData Dull
-
VOL
WRITE CYCLE TIMING
Address~--·-----tAVAX"-!'-'"
5
~tSLWL 1
l--tAVWL-
IWHSH
1
I
, - - - - - - - - - - - 3.5 V
w
tDVWL
--1..:..-.-r-~
o IData Inl~
Dala Valtd
...j
IAII Time Measurements Referenced to 1 5 VI
2-71
-OV
MCM2115A-MCM21 L15A-MCM2125A-MCM21 L25A
OUTPUT LOAD
WAVEFORMS
Waveform
Svmbol
~
Input
Output
Must Be
Valid
Will Be
Valid
Change
From H to L
VCC
510
Q-.-_-~
2125A
Will Change
From H to L
30 pF
300
//////
Change
From L to H
Will Change
From L to H
OOOOOOOOC
Don't Care:
Any Change
Permitted
Changing
(Including
Scope and jIg I
State
Unk.nown
==>---
High
Impedance
212SA FAMILY
READ CYCLE TIMING 1
IS Held Low, W Held Highl
Address
o fOata Out!
READ CYCLE TIMING 2
(W Held High)
~g
Prev.ous
~,'_3.5V
tAVAX
.~
oata;-~A-~-~-V-----1---:~~~~~~~~~o~a~(a~~IC-a~-'1
,,' 0
- - - - - l -::>--------l
Memorv Array
64 Row
PIN NAMES
"SS=Pin9
AO-All
iN
t
64 Columns
0
Q
VCC·
VSS
11
....
.. Address Input
.Wnte Enable
....... Chip Enable
Data Input
Data Output
Power 1+5 VI
........... Ground
Q
TRUTH TABLE
E
W
x
Mado
Output
Power
Not Salee ted
High Z
Standby
L
L
Write
High Z
Active
L
H
Read
Data Out
Active
H
A3 A4 A5 A9 A1DAll
DS9B21 I li'
o IData OUII
Data Valid
READ CYCLE TIMING 2 13, 5)
iw HELD HIGHI
Address~________________________________A_d_d_re_s_s_v_a_li_d__________________~_____________________
j4-----------IELEH
-----------------CX)<~
Data Valid
I+-----+- tWHOV I4 , 51
o IData Out I
High Impedance
Data Undefined
NOTE:
1. If t goes high simultaneously with W high. the output remains in a high-impedance state
2. tWHAX is measured from the earlier of S or Vii going high to the end of the write cycle.
3. During this period. DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.
4. If S is low during this period, the DO pins are in the output state. Then the data input signals of opposite phase to the outputs must not
. be applied to them.
5.
Q is the same phase of write data of this write cycle.
WRITE CYCLE 2
IE CONTROLLED I
~-------------------------tAVAX----------------------------------.,
Address
Address Valid
-~~-------------------tELWH----------~----------_e~------------_+-------
1+-------''--------:------- IAVWH
----------------------~
~------tWLWH--------~~~~~r_~~~~
w
tDVWH
D lData In I
",,"'''-/V'l00<')(',
---_14--*
Data Valid
High Impedance
o IData Outl----------------------------------------------------------------------------------------
2-84
®
I
MCM2149
MOTOROLA
Product Preview
MOS
4aJS.BIT STATIC RANDOM ACCESS MEMORY
IN·CHANNEL. SI LlCON·GA TE I
The MCM2149 is a 4096-bit random access memory fabricated using
HMOS, high performance MOS technology. For ease.of use, the device
operates from a single power supply, is directly compatible with TTL
and requires no clocks or refreshing because of fully static operation.
Data access is particularly simple, since address setup times are not required. The output data has the same polarity as the input data.
The MCM2149 is designed for memory applications where simple interfacing is the design objective. The MCM2149 is assembled in 18-pin
dual-in-line packages with the industry standard pin-out. A separate
chip select (5) lead allows easy selection of an individual package when
the three-state outputs are OR-tied.
4096-BIT STATIC
RANDOM ACCESS
MEMORY
• 1024 Words by 4-Bit Organization
•
•
•
•
•
-
Power Dissipation - 140 mA Maximum (Active)
Fully TTL Compatible
Common Data Input and Output
Three-State Outputs for OR-Ties
Automatic Power Down Version Available - MCM2148
PIN ASSIGNMENT
A61~~vCC
BLOCK DIAGRAM
VCC = Pin 18
VSS'= Pin 9
A4~----~c=r---~
A5---A6-----I
A7 _1_7_ _ _-t
A8~----I
A9~
14
Dal--~~-I
Row
Select
L SUFFIX
CERAMIC PACKAGE
CASE 68).06
• Chip Select Access Time
MCM2149-70;30 ns Max.
MCM2149-B5;35 ns Max.
•
•
•
•
•
-~
C SUFFIX
FAIT·SEAl PACKAGE
CASE 726-m
HMOS Technology
Industry Standard 1B-Pin Configuration
Single + 5 Volt Supply
No Clock or Timihg Strobe Required
Maximum Access Time
MCM2149-70;70 ns Max.
MCM2149-B5;B5 ns Max.
Memory Arrav
64 Rows
64 Columns
A5[ 2
17
A4[ 3
16 A8
A3 4
15 A9
~A7
AD 5
14
001
Al 6
13
D02
A2 7
12 003
S
8
11 ~O04
VSS
9
10pW
PIN NAMES
AD-A9 ..
Vi
• • •
~..
D01·004
Vee
VSS
002 _1.:...3-..-1+-1
Address Input
Write Enable
Chip SeleCI
Data Input/Output
Power 1+5 V)
Ground
003 _12_,-+-+-+-1
004 ----H--H-+-i
Motorola reserves the right to make changes to
6
7
any product herein to improve" reliability, function or design. Motorola does not assume any
liability arising out of the application or use of
any product or circuit described herein; neither
does it convey any license under its patent rights
nor the rights of others.
4
AD A1 A2 A3
N P324/11-BO
2-85
®
MOTOROL.A
Product
MCM2167
Previe~
MOS
16,384-BIT STATIC RANDOM ACCESS MEMORY
IN-CHANNEL, SILICON-GATE)
The MCM2167 is a 16,384-bit static random access memory organized as 16,384 words by 1-bit using Motorola's N-channel silicon-gate
MOS technology. It uses a design approach which provides the simple
timing features associated with fully static memories and the reduced
standby power associated With semi-static and dynamic memories. This
means low standby power without the need for clocks, nor reduced
data rates due to cycle times that exceed access times.
~ controls the power-down feature. It is not a clock but rather a chip
select that affects power consumption. In less than a cycle time alter E
goes high, deselect mode, the part automatically reduces its power requirements and remains in this low-power standby mode as long as E
remains high. This feature results in sytem power savings as great as
85% in larger systems, where most devices are deselected. The
automatic powtlr-down feature causes no performance degradation.
The MCM2167 is in a 20 pin dual in-line package with the industry
standard pinout. It is TTL compatible in all respects. The data out has
the same polarity as the Input data. A data input and a separate threestate output provide flexibility and allow easy OR-ties.
• Fully Static Memory - No Clock or Timing Strobe Required
16,384-BIT STATIC
RANDOM ACCESS
MEMORY
•
•
•
•
•
L SUFFIX
CERAMIC PACKAGE
CASE 729-02
PIN ASSIGNMENT
Single + 5 V Supply
High Density 20 Pin Package
Automatic Power-Down
Directly TTL Compatible - All Inputs and Three-State Output
Separate Data Input and Output
• Access Time
MCM2167-55 MCM2167-70 MCM2167-85 MCM2167-1oo -
AO
VCC
Al
Al3,
A2
A12
All
55 ns max
A4
A10
70 ns max
85 ns max
100 ns max
A5
A9
G
A7
W
Vcc=Pin 20
Vss=Pin 10
•
•
E
Vss
BLOCK DIAGRAM
Row
Select
0
PIN NAMES
1\ch4'~l3,~..-------.--..-.. -... ~.A-d~dr-e-~~I-np-u~t
W..
E..
Memory Array
128 Rows
128 Columns
0..
G..
. ......... Write Enable
.. ..... Chip Enable
.. ....................... Data Input
.. ....................... Data Output
Vee ........................ Power 1+5 V)
V~S...
.. ...................... Ground
•
Column I/O Circuits
TRUTH TABLE
G
E
H
L
L
W
X
Mode
Not Selected
Output
High Z
Power
Standby
L
H
Write
High Z
Data Out
Active
Active
Read
--_ ..
W~9~~~------------
NP3.26/11-80
2-86
®
MCM4016
MOTOROLA
Produ.ct
Previe~
MOS
2048 x 8-BIT STATIC RANDOM ACCESS MEMORY
(N-CHANNEL, SILICON-GATE)
The MCM4016 is a 16,384-bit static Random Access Memory organized as 2048 words by a-bits, fabricated using Motorola's highperformance silicon-gate metal oxide semiconductor (HMOS)
technology. Its static design means that no refresh clocking circuitry is
needed and timing requirements are simplified. Access time is equal to
cycle time.
A chip select control is provided for controlling the flow of data in and
data out, and an output enable function is provided which eliminates
the need for external bus buffers.
The MCM4016 is in a 24-pin dual-in-line packa.ge with the industry
standard pinout and is pinout compatible with the industry standard
16K EPROM and 16K mask programmable ROM.
•
•
•
•
•
•
•
•
•
2048 Words by a-Bits Organization
HMOS Technology
Single + 5 V Supply
Fully Static: No Clock or Timing Strobe Required
Low Power Dissipation 35 mW Typical (Standby)
400 mW Tvpical (Active)
Maximum Access Time: MCM4016-20 - 200 ns
Fully TTL Compatible
Pinout Compatible with Industry Standard 2716 16K EPROM and
Mask Programmable ROM
Output Enable (;) Eliminates Need for Extern,,1 Bus Buffers
BLOCK DIAGRAM
AO
Al
A2
A3
A4
A5
A6
8
7
6
5
4
3
2
!!:::=
~
~
~
Row
Decoder
Pin 24= Vee
Pin 12=VSS
-.-.
.
Memory Matrix
128 x 128
,rhn
~"""~~,:;:,~
,~,~,
~~VI':;
~
ii' l
L
PIN ASSIGNMENTS
A7
A5
A9
A3
Iii
G
A2
Al0
t
AO
007
000
006
002
-.--
001 10
002-irOO!i+:
Input
Data
Control
~
Column Decoder
006-1H-007-<
~
I
IJ
t
A7
E
(;
W
.
Column 1/0
~
23
J zJ
22
z
AS
AS
ISU'
~
AlO
21
I
II I
• I I
I
• II I
Control
Loglr:
005
11
004
003
PIN NAMES
AO-A 10 ....................... Address Input
000-007..
. .. Oata Input/Output
G .............................. Output Enable
t
...................... ehip Select
Vii ............................. Write Enable
Vee· ........................ Power 1+ 5 VI
. ............... Ground
VSS..
•
·
J
18
20
Vee
A8
A6
V'ss
D~NJ~
g~~ F
~
LS'JFFIX
CERA~~~;~l~KAGE
CASE 623
001
~
~
v-
2048 x 8 BIT STATIC
RANDOM ACCESS MEMORY
Motorola reserves the right to make changes to
any product herein to improve reliability. function or design. Motorola does not assume any
liability arising out of the application or use of
any product or circuit descnbed herein; neither
does it convey any license under its patent rights
nor the rights of others
NP329/"-80
2-87
®
MCM6641
MCM66L41.
MOTOROLA
Advance Inforu.atlon
MOS
4096-BIT STATIC RANDOM ACCESS MEMORIES
IN·CHANNEL, SILlCON·GATEI
The MCM6641 series 4096 x l-bit Random Access Memory IS
fabricated with high density, high reliability N-channel silicon-gate
technology. For ease of use, the device operates from a single 5-volt
power supply, is directly compatible with TTL and DTL, and requires no
clocks or refreshing because of fully static operation. The fully static
operation allows chip selects to be tied low, further simplifying system
timing. Data access is particularly simple, since address setup times are
not reqUired. The output data has the same polarity as the data input.
The MCM6641 is designed for memory applications where simple interfacing is the design objective, and is assembled in 18-pin dual-m-jine
packages with the industry standard pin-outs.
4096-BIT STATIC
RANDOM ACCESS MEMORIES
• Single ± 10% + 5 V Supply
• Fully Static Operation - No Clock, Timing Strabe, Pre-Charge, or
Refresh Required
CASE 707·01
• Industry Standard 18-Pin Configuration
•
•
•
•
Fully TTL Compatible
Common Data Input and Output Capability
Three-State Outputs for OR- Tie Capability
Power Dissipation MCM6641 Less Than 550 mW IMaxirnuml
MCM66L41 Less Than 385 mW IMaxlmuml
.....
"
• Standby Power DiSSipation Less Than 125 mW ITypicali
PSUFFIX
.
PLASTIC PACKAGE
CASE 707·02
PIN ASSIGNMENT
• Plug-In Replacement For TMS4044
AO I.
Vee
Al
A6
MAXIMUM ACCESS TIME/MINIMUM CYCLE TIME
A7
MCM6641·20
MCM66L41-20
200 ns
MCM6641-30
MCM66L41-30
300 ns
MCM6641-25
MCM66L41·25
25"0 ns
MCM6641-45
MCM66L41-45
450 ns
15 A8
A5
o
7
w
14
A9
'3
AIO
12
A11
II
D
Vss,-_ _10~ S
BLOCK DIAGRAM
Ao------~~_f------,
A 1
PIN NAMES
~Vss
AO·A 11
----;::;C::J
----..f'l.---,
A2
AB _ _ _......, - - ,
A 7 ____
Row
$elecf
Memory Array
.Address Input
D
~VCC
Dala Inpel
.Data Output
o
5
64 Row
64 Columns
. Chip Select
Power Supply (+ 5 V)
Vee
~....,,--,
~s
A 6 - - - -......, - - ,
Ground
Write Enable
w
o
Data Input
D------i
ViI ----__,
TRUTH TABLE
,_~_
A3 A4
A~Al1Al0A9
S
W
D
Q
Mode
H
x
x
High Z
Not Selected
L
L
l
High Z
Wnte "0"
I
I
H
High Z
Write "1"
I
H
x
Oll1PlJl ;JOlla
Read
ADI475/2· 78
2-88
MCM6641-MCM66L41
ABSOLUTE MAXIMUM RATINGS (See Note I
Ratin,
Temperature Under Bias
Voltage on Any Pin With Respect to VSS
Value
Unit
-10 to +80
°c
inputs against damage due to high static voltages
-0.5 to + 7.0
Vdc
20
mA
or electric fields; however, it is advised that
normal precautions be taken to avoid applIcation of any voltage higher than maximum rated
1.0
Watt
o to +70
°c
°c
DC Output Current
Power Dissipation
Operating Temperature Range
Storage Temperature Range
Note:
-65 to + 150
This device contains circuitry to protect the
voltages to this high·impedance circuit.
Permanent dE'vlce damage may occur if ABSOLUTE MAXIMUM
RATINGS are exceeded. Functional operation should be restricted
to RECOMMENDED OPERATING CONDITIONS. Exposure to
higher than recommended voltages for extended periods of time could
affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperatur.e range unless otherwise noted)
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Symbol
Min
Typ
Max
Unit
VCC
VSS
4.5
0
5.0
0
5.5
0
V
VIH
2.0
-
6.0
V
VIL
-05
-
0.8
V
Supply Voltage
Logic 1 Voltage. All Inputs
-
Logic 0 Voltage. All Inputs
DC CHARACTERISTICS
Symbol
Parameter
-
Input Load Current IAII Input Pons, Vin = 0 10 5.5 VI
III
Output Leakage Current ICS - 2.4 V. V,n - 0.4 to VcO
MCM6641
Typ Max
Min
-
-
Output Low Voltage. 10L - 2.1 mA
VOL
-
Output High Voltage. 10H - 1.0 mA
VOH
2.4
Output Short Circuit Current
lOS'
-
ICC
..
-
-
80
100
0.15
0.4
-
10
~A
~A
55
70
mA
0.15
0.4
V
40
mA
2.4
40
Unit
10
10
IILOi
Power Supply Current IVCC = 5.5 V, lout =0 mAo T A = O'CI
10
MCM66L41
Min Typ Max
V
• Duration not to exceed 30 seconds
CAPACITANCE If= 1.0 MHz, TA=25'C. VCC=5.0 V. periodically sampled rathe, than 100% tested I
Characteristic
Input Capacitance 1Vin = 0 V)
Output Capacitance (V out = a V)
Capacitance measured With a Boonton Meter or effective
capaci~ance
calculated from the eQuatron: C = l.6. t /.6.V
STANDBY OPERATION·
(Typical Supply Values)
Device
Supply
Operating
Standby
MCM6641
VCC
+5 V
+2.4 V
225mW
MCM66L41
VCC
+5 V
+2.4 V
150mW
2-89
Max Standby Power
MCM6641-MCM66L41
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted)
Input Pulse Levels ................................ 0.6 Volt to 2.0 Volts
Input Rise and Fall Times..
. ... 10 ns
Input and Output Timing Levels..
Output Load..
. ..... 1.5 volts
. ...... 1 TTL Gate and CL = 100 pF
READ (NOTE 1), WRITE (NOTE 2) CYCLES
MCM6641-20
MCM66L41-20
Parameter
Read Cycle Time
MCM6641-25
MCM66L41-25
MCM6641-30
MCM6641-45
MCM66L41-30 MCM66 L41-45
Units
Svmbol
Min
Max
Min
Max
Min
Max
Min
Max
tAC
200
-
250
-
300
-
450
-
ns
tA
-
200
250
450
ns
ns
Chip Selection to Output Valid
tso
-
70
-
65
-
100
-
120
Chip Selection to Output Active
tsx
10
-
10
-
10
-
10
-
ns
Output 3-5ta1e From Deselection
tOTO
-
40
-
60
-
80
-
100
ns
Access Time
Output Hold From Address Change
50
50
50
50
ns
200
250
300
450
ns
tw
100
125
150
200
ns
'WA
a
0
a
0
'aHA
Write Cycle Time
. 'WC
Write Time
Write Release Time
Output 3-5tate From Write
'OTW
Data to Write Time Overlap
'OW
tOH
Data Hold From Write Time
300
100
·40
_.
-
125
60
-
a
0
80
150
a
-
ns
100
200
-
a
ns
ns
ns
READ CYCLE TIMING
(W HELD. HIGH)
tRC ---------~
~I__-------- 'A
-------il-l
Address
DOU,----------------------------~~~t=====~*-----------NOTES·
1 A Read occurs during the overlap of a low
S and a high W.
2. A Wnte occurs dunng the overlap of a low S and a low W.
3 If the S low tranSition occurs simultaneously with the Vii low transition, the output buff~rs remain
2-90
In
a high-Impedance state.
MCM6641·MCM66L41
WRITE CYCLE TIMING INote 31
'we
Addr...
~\\\\\\\
,\\ V. r-
~/IIIII
-
'w
'In
~
°out
'\
'\.~
-
tOTW
'WR
~
I--
,
2-91
--
'OH
~
'111111111I II
f--
®
MCM6810
1.0 MHz
MCM68A10
1,5 MHz
MCM68B10
2,0 MHz
MOTOROLA
MOS
128 X 8-BIT STATIC RANDOM ACCESS MEMORY
INCHANNEL, SILICON-GATEI
The MCM6810 is a byte-organized memory designed for use ii,
bus-organi zed systems. I t IS fabrrcated with N ·channel silicon ·gate
technology. For ease of use, the device operates from a SIngle power
supply, has cotTlpatibillty With TTL and DTL, and needs no
clocks or refreshing because of static operation.
The memory IS compatible With the M6SuO Microcomputer
Family,
providing random storage in byte ir:crements. Memory
expansion is provided through multrple Chi p Select Inputs.
•
Organized as 128 Bytes of B Bits
•
Static Operation
•
Bidirectional Three-State Data Input/Output
•
Six Chip Select Inputs (Four Active Low; Two Active High)
•
Single 5- Volt Power Supply
•
•
TTL Compatible
Maximum Access Time = 450 ns - MCM6Bl0
360 ns - MCM6BA 10
250 ns - MCM6BB10
128 X 8-BIT STATIC
RANDOM ACCESS
MEMORY
P SUFFIX
PLASTIC PACKAGE
CASE 709-02
~
L SUFFIX
CERAMIC PACKAGE
CASE 716-06
PIN ASSIGNMENT
'GNO
00
Vee
AO
Al
A2
ORDERING INFORMATION
Speed
Device
Temperature Range
1.0 MHz
MC6Bl0P, L
MC6Bl0CP, CL
MC6810BJCS
MC6810CJCS
to 70 0 C
-40 to +B5 0 C
-55 to +125 0 C
MC68Al0P, L
MC68Al0CP, CL
to + 70 0 C
-40 to +B5 0 C
MI L·STD-BB3B
MIL·STD·8B3C
1,5 MHz
2,0 MHz
MC6BB10P, L
03
A3
04
A4
06
A6
o
o
o to + 70 0 C
M6800MICROCOMPUTER FAMILY
BLOCK DIAGRAM
A5
07
R/W
eso
eS5
CSl
CS4
CS2
e53
MCM6810 - RANDOM ACCESS MEMORY
BLOCK DIAGRAM
r------,
Data
Bus
Memory Address
and Control
Address Data
Bus
Bus
05948717·78
2-92
MCM6810eMCM68A 10eMCM68B 10
MAXIMUM RATINGS
Symbol
Value
Vee
-0.3 to +7.0
Vdc
Input Voltage
Vin
-0.3 to + 7.0
Vdc
Operating Temperature Range
TA
TL to TH
o to 70
-40 to 85
-55to125
°e
Storage Temperature Range
T stg
-65 to +150
°e
Thermal Resistance
8JA
82.5
ue/w
Rating
Supply Voltage
ELECTRICAL CHARACTERISTICS
Unit
This device cont.",. circuitry to protlCt
the inputs again.t damage due to high
static voltage. or electric fields; howeyer,
it is advised that normal precautions b.
tak,n to avoid application of any voltage
higher than maximum ,attld voltages to
this high impedance circuit.
IVee = 5.0 V '5%. VSS = O. T A = TL to TH unless otherwise noted.1
Symbol
Min
Typ
M ..
Unit
lin
-
-
2.5
I'Ad<
'Output High Voltage
(lOH = -205 /'AI
VOH
2.4
-
Output Low Voltage
VOL
-
-
0.4
Vdc
ITSI
-
-
10
,uAdc
ICC
_.
-
80
100
mAdc
Cin
-
-
7.5
pF
Cout
-
-
12.5
pF
Characteristic
Input Current IAn. A/W. eS n • eSnl
IVin = 0 to 5.25 VI
Vdc
(lOL = 1.6 mAl
Output Leakage Current (Three-State)
les = 0.8 V or es = 2.0 V. V out = 0.4 V to 2.4 VI
Supply Current
IVee = 5.25 V. all other pins groundedl
1.0 MHz
1.5.2.0 MHz
Input Capacitance IAn. AIW. eS n • CSnl
IVin =0. TA = 25 0 e. f = 1.0 MHzl
Output Capacitance (On)
(V out = O. TA = 25 0 e. f = 1.0 MHz. eS0 = 01
RECOMMENDED DC OPERATING CONDITIONS
I
l I"put High Vo Itage
Parameter
I
Symbol
I
Min
2.0
I I nput Low Vo Itage
-0.3
I
I
Nom
I
I
I
I
BLOCK OIAGRAM
AO
A'
A2
A3
A4
A5
A6
CS5
CS4
eS3
23
22
2'
'8
3
4
5
6
1
8
11
~
20
'9
'5
'4
'3
CS2
'2
ES1
"
'0
eso
2-93
DO
Ot
02
03
04
05
06
01
M••
5.25
0.8
I
I
I
Unit
Vdc
Vdc
MCM6810-MCM68A l()eMCM68B 10
FIGURE 1 - AC TEST LOAD
5.0 V
AC TEST CONDITIONS
Condition
Value
0.8Vlo2.0V
Input Pulse Levels
Test Point o-~---1r--+.-+ MM06150
.. or Equiv
20 ns
Input Risp. and Fall Times
See Figure 1
Output Load
11.7 k
r MMD1000
or Equiv
-'ncludeli Jig Capacitance
AC OPERATING CONDITIONS AND CHARACTERISTICS
READ CYCLE (Vee
= 5.0 v
!
5%, VSS '" 0, TA '" TL to TH unless otherwise noted.)
MCM6810
Characteristic
Read Cycle Time
Access Time
MCM68Al0
MCM68Bl0
Symbol
Min
Max
Min
Max
Min
Max
leyelRI
450
-
360
-
250
-
-
360
450
tace
250
Address Setup Time
lAS
20
-
20
IAH
0
-
0
-
20
Address Hold Time
0
-
Data Ot!lay Time (Read)
IDDR
-
230
-
220
-
180
Read to Select Delay Time
IRCS
0
0
0
Data Hold frQ.m Address
IDHA
10
Output Hold Time
Data Hold from Read
I Read Hold from Chip Select
IH
10
IDHR
10
IRH
0
-
10
10
-
10
-
80
-
10
60
10
60
0
-
0
-
10
-
-
Unit
n.
no
n.
n.
n.
n.
n.
n.
no
no
READ CYCLE TIMING
~---------------lcvcIRI---------------~
1'4'--------tacc
Address
---------_~
2.0 V
0.8 V
cs
2.0 V
1'4----IDDR----~
0.8 V
A/iN
D8ta OlJt - - - - -
--------<:-
=
2.4 V
0.4 V
Date Valid
Don't Care
CS can be enabled for con.cutlva
read cycle. provided A/W remaln •• t V IH.
Note: CS end
2-94
M,CM6810eMCM68A 10eMCM68B 10
WRITE CYCLE 1VCC = 5.0 V, 5%, VSS = 0, TA = TL to TH unless otherwise noted.1
MCM6810
Characteristtc
Write Cycle Time
Addres~
Setup Time
MCM68A10
MCM68B10
Symbol
Min
- teyelWI
Max
Min
Max
Min
Max
Unit
450
-
360
-
250
-
ns
20
20
20
ns
Address Hold Time
'AS
tAH
0
0
0
Chip Select Pulse Width
tcs
300
250
ns
ns
Write to Chip Select Delay Time
twcs
0
-
0
-
Deta Setup Time (Write)
tDSW
190
80
-
60
tH
10
-
10
-
10
tWH
0
-
Input Hold Time
Write Hold Time from Chip Select
210
0
-
ns
n,
ns
WRITE CYCLE TIMING
~
2.0 V
Address==>¢:;a V
'AS
cs----------~~~~~~J
~'WCS
AiW~O.8V
Note
C$ and
Cs
can be enabled for r.onsecutlve write cycles
provided R/W is 5trobed to V I t-I before or coincident
with the Addresschange. and remains high for time tAS-
2-95
®
MCM2532
MCM25L32
MOTOROLA
4096 x 8-BIT UV ERASABLE PROM
MOS
The MCM2532/25L32 is a 32,768-bit Erasable and Electrically
Reprogrammable PROM designed for system debug usage and similar
applications requiring nonvolatile memory that could be reprogrammed
periodically. The transparent window in the package allows the memory
content to be er~d with ultraviolet light.
For ease of use, the device operates from a single power supply and
has static power-down mode. Pin-for-pin compatible mask programmable ROMs are available for large volume production runs of systems
initially using the MCM2532.
(N·CHANNEL, SILlCON·GATEI
4096 x 8-BIT
UV ERASABLE PROM
Single + 5 V Power Supply
Organized as 4096 Bytes of 8 Bits
Automatic Power-Down Mode (Standbyl
Fully Static Operation (No Clocksl
TTL Compatible During Both Read and Program
Maximum Access Time=450 ns MCM2532
350 ns MCM2532-35
250 ns MCM2532-25
• Pin Compatible with MCM68A332 Mask Programmable ROMs
•
•
•
•
•
•
CASE 623A-02
L SUFFIX CERAMIC PACKAGE
ALSO AVAILABLE - CASE 716
• Low Power Version
MCM25L32 Active - 50 mA Max
Standby - 10 mA Max
MCM25L32-25 Active - 70 mA
Standby - 15 mA
PIN ASSIGNMENT
A7
Vce
AS
A6
A5
A9
Vpp
MOTOROLA'S PIN·COMPATIBLE EPROM FAMILY
A3
E/Progr
A2
AlO
Al
All
AD
DOl
000
006
001
005
002
004
Vss
DQ3
MOTOROLA'S PIN·COMPATIBLE ROM FAMILY
32K
'PIN NAMES
A
DO
E/Progr
Address
Data Input/Output
Dual Function Enable
(Power-Down/Program Pulse)
• New Industry standard nomenclature
MCM..... 332
INDUSTRY STANDARD PINOUTS
DS9816/4-80
2-96
MCM2532-MCM25L32
ABSOLUTE MAXIMUM RATINGS
Rating
Value
Unit
-10to +80
-65 to + 125
·C
·C
·C
All Input/Output Voltages with
Respect to VSS
+6to-0.3
Vdc
Vpp Suppty Voltage With Respect to VSS
+28 to -0.3
Vdc
Temperature Under Bias
o to + 70
Operating Temperature Range
Storage Temperature
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken 10 avoid applicalion 01 any vollage
highar lhan maximum raled voltages 10 Ihis highimpedance circuit.
NOTE: Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded. FunCtional operation should be restTlcted to RECOMMENDED OPEAATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability
MODE SELECTION
Pin Number
9-11,
1l-17
Mode
DO
Read
12
20
21
24
VSS
EtProgr
Vpp
VCC
O.,a OUI VSS
High Z Vss
OUlput Disable
Standby
High Z
Vss
Program
Oalaln
VSS
Oala OUI VSS
High Z VSS
Program Verify
Program Inhibit
VIL
5V
Vee
VIH
51025 V
Vee
VIH
Pulsed
VIH to VIL
5V
Vee
VPPH
Vee
VIL
5V
Vee
VIH
VPPH
Vee
BLOCK DIAGRAM
Oala Input/Output DOO-007
FIGURE 1 - AC TEST LOAD
~
5.0 V
Tesl Point o-----jp--r-l_f--+
·,00
pF
Y Gating
AO-Al1
·Includes Jig Capacitance
Memory
Matrix
1256 x 1281
2-97
MMD6150
or Equiv.
MM07000
or EqUN.
MCM2532-MCM25L.32
CAPACITANCE If = 1.0 MHz, T = 25°C, periodically sampled rather than 100% tested.)
Characteristic
Input Capacitance IVin = 0 V)
Output Capacitance IV
= 0 VI
Capacitance measured witp a Boonton Meter or effective capacitance calculated from the equation: C=
l~f/~V.
DC OPERATING CONDITIONS AND CHARACTERISTICS
IFuily operating voltage and temperature range unless otherwise noted)
RECOMMENDED DC OPERATING CONDITIONS
Svrnbol
Min
Tw
Max
UnIt
MCM25L32/MCM2532
MCM2532-35/MCM2532-25
VCC
4.75
4.5
5.0
5.0
5.25
5.5
Vo<;
MCM25L32-35/MCM25L32-25
Vpp
VCC-0.6
2.2
-0.1
5.0
VCC+0.6
VCC+ 1.0
0.66
Parameter
Supply Voltage·
Input High Voltage
VIH
Input Low Voltage
VIL
-
Vo<;
Vo<;
RECOMMENDED DC OPERATING CHARACTERISTICS
Chlrllcterlollc
Address and E Input Sink Current
MCM2&32
Min Max
Symbol
Condition
Vin-5.25 V
lin
10
Vn"t~5.25 V
110
10
MCM2532
MCM2532-36
E=VIH
ICCl
-
VCC Standby Current· (Standby)
MCM2532-25
E=VIH
ICCl
-
25
V CC Supply Current· IActive)
MCM2532
MCM2532·3E
E=VIL
ICC2
-
100
MCM2532-25
E=VIL
ICC2
Ippt'
-
120
Output Leakage Current
VCC Supply Curro;nt· (Standby)
VCC Supply Current· (Active)
VJ>!> Sup.ply
Current·
Vpp~5.66
Output Low Voltage
V
IOL=2.1 mA
Output High Volta!!e
IOH-
VOL
VOH
4OO.A
25
MCM2&L32
UnIt·
Min Max
10 . .A
-
5.0
0.45
2.4
-
10
aA
10
mA
15
mA
50
mA
70
mA
5.0
inA
0.45
2.4
V
V
·VCC must be epplied simultaneously or prior to Vpp. VCC must also be switched oH simultaneously with or after Vpp. With Vpp connected
directly to VCC during the read operation, the supply current would be the sum of IPPl and ICC. The additional 0.6 V tolerance on Vpp makes
it possible to use a driver circuit for switching Vpp supply from VCC in Read mode to + 25 V for programming. Typical values are for
T A = 25°C and nominal supply voltages.
AC READ OPERATING CONDITIONS AND CHARACTERISTICS
IFull Operating Voltage and Temperature Range Unless Otherwise Noted)
Symbol
CNnctariIdc
Address Valid to Outout Valid (E/PrOar=V,,)
E 0 OutDut Valid
t to High Z Output
Data Hold from Address
.0.8 and 2.0 Volts
.. .. .... See Figure 1
Input and Output Timing Levels ..
Output Load ...
. 0.66 Voltand 2.2 Volts
........ 20ns
Input Pulse LeVels ...
Input Rise and Fall Times ...
(E = VIU
2-98
MCM2&32-2Ii
Min
Max
-
MCM2&32-36
Max
Min
MCM21i32
Min Max
UnIt
t.6.VOV
tFIOV
-
250
250
-
360
-
3EO
-
460
460
tEHOZ
0
100
100
0
100
ns
ns
tAXDX
0
-
0
0
-
0
-
ns
ns
MCM2532-MCM25L32
READ MODE TIMING DIAGRAMS IE ~ VILI
STANDBY MODE
A (Address)
Address Valid
Eft Progr)
Q
IData Outl
New Address Valid
\
Standby MoJe
/
-
~IEHQZ
!>-----High Z
Output Valid
Active Mode
- "'' ,C~-------->Output Valid
.
DC PROGRAMMING CONDITIONS AND CHARACTERISTICS
ITA=25°C±5°CI
RECOMMENDED PROGRAMMING OPERATION CONDITIONS
Symbol
Min
Nom
Max
VCC. VPPL
VpPH
4.75
24
5.0
25
5.25
26
Vde
VIH
VIL
2.2
-0.1
-
VCC+1
0.65
Vde
Vde
Parameter
Supply \loltage
Input High Voltage lor Data
InpOt Low Voltage for Data
-
Unit
'VCC must be applied simultaneously or prior to Vpp. VCC must also be switched off simultaneously with or after Vpp. The
device must not be inserted into or removed from a board with Vpp at + 25 V. Vpp must not exceed the + 26 V maximum
specifications.
PROGRAMMING OPERATION DC CHARACTERISTICS
Charlcterlltie
Address and EI Progr Input Sink Current
Condition
Symbol
Min
Typ
MIX
Unit
Vin = 5.25 V 10.45 V
III
-
-
1O
,.Ade
1O
mAde
VPP Supply Current IVpp = 25 V ± 1 VI
E/Progr = VIH
IPP1
-
VPP Programming Pulse Supply Current IVpp = 25 V ± 1 VI
t/l'rOQr = VIL
IPP2
-
ICC
-
VCC Supply Current - MCM2532
30
mAde
160
mAde
AC PROGRAMMING OPERATING CONDITIONS AND CHARACTERISTICS
Symbol
M"on
Address Setup Time
tAVEL
2.0
VPP Setup Time
Data Setup Time
tPHEL
tOVEL
2.0
Address Hold Time
tEHAX
Vpp to Enable Low Time
Data Hold Time
tpLEL
Characteriltie
tEHOZ
Unit
-
p.S
-
p.S
2.0
-
,.s
°
°
-
,.s
°
2.0
VPP Hold Time
Enable IPrograml Active Time
tEHPL
tELEH
l'
Enable IE/Progrl Pulse Transition Time
tTl PEl
tA. tF
5
0.5
VPP Aise and Fall Time from 5 to 25 V
MIX
55
2
-11 shorter than 45 ms (min) pulses are used, the same number of pulses should be applied after the specific data has been verified.
2-99
ns
ns
ns
ms
ns
,.s
MCM2532·MCM25L32
PROGRAMMING OPERATION TIMING DIAGRAM
.. I..
Program
VIH------""
A IAddressl
V I L - - - - - -J
Program
VenfY~
,.-"----
Address N Valid
t+---tEHAX----+j
VOHIVIH
o or a IDatal - - - - - - H , - z - - - - - - < I
Output Valid 1)---""",
VOLIVIL
VIH---------+------U
E/Progr
VIL
PROGRAMMING INSTRUCTIONS
After the completion of an ERASE operation, every bit in
the device is in the "1" state (represented by Output High!.
Data are entered by programming zeros (Output Low) into
the required bits. The words are addressed the same way as
in the READ operation. A programmed "0" can only be
changed to a "1" by ultraviolet light erasure.
To set the memory up for PROGRAM mode, the VPP input (pin 21) should be raised to + 25 V. The V CC supply
voltage is the same as for the READ operation. Programming
data is entered in a-bit words through the data out IDO} terminals while E/Progr is high. Only "O's" will be programmed
when "O's" and "1's" are entered in the data word.
After address and data setup, a 50 ms program pulse (VIH
to VIL) is applied to the E/Progr input . .A program pulse is
applied to each address location to be programmed. To
minimize programming time, a 2 ms pulse width is recommended. The maximum program pulse width is 55 ms;
therefore, programming must not be attempted with a dc
signal applied to the E/Progr input.
Multiple MCM2532s may be programmed in parallel with
the same data by connecting together like inputs and apply-
ing the program pulse to the f/l>r09r inputs. Different data
may be programmed into multiple MCM2532s connected in
parallel by using the PROGRAM INHIBLT mode. Except for
1he E/Progr pin, all like inputs may be common.
PROGRAM VERIFY for the MCM2532 is the read operation.
READ OPERATION
After access time, data is valid at the outputs in the READ
mode.
ERASING INSTRUCTIONS
The MCM2532/25L32 can be erased by exposure to high
intensity shortwave ultraviolet light, with a wave-length of
2537 angstroms. The recommended integrated dose (i.e.,
UV-intensity X exposure time) is 15 Ws/cm 2 As an example, using the "Model 30-000" UV-Eraser Turner Designs,
Mountain View, CA94043} the ERASE-time is 36 minutes.
The lamps should be used without shortwave filters and the
MCM2532/25L32 should be positioned about one inch away
from the UV-tubes.
2-100
MCM2532·MCM25L32
TIMING PARAMETER ABBREVIATIONS
TIMING LIMITS
The table of timir\g values shows either a minimum or a
m'aximum limit for each parameter. Input requirements are
specified from the external system point of view. Thus, address setup time is shown as a minimum since the system
must supply at least that much time (even though most
devices do not require it!. On the other hand, responses from
the memory are specified from the device point of view.
Thus, the access time IS shown as a maximum since th·e
device never provides data later than that time.
t X X X X
signal name. from. Whi.Ch i.nterval i.S defined ~
transition direction for first signal
signal name to which Interval IS defined
transition direction for second signal
III
The transition definitions used In this data sheet are:
H = transition to high
L = transition to low
V = transition to valid
X = transition to invalid or don't care
Z = transition to off (high impedance)
WAVEFORMS
Waveform
Symbol
Input
Output
Must Be
Wilt Be
Valid
Valid
Change
From H 10 L
Will Change
From H 10 L
~
Change
From L tc H
Will Change
From L to H
NlllN
Don't Care
Any Change
Permitted
Changing
~
==>-
State
Unknown
High
Impedance
2-101
®
MCM2708
MCM27A08
MOTOROLA
1024 X
a ERASABLE
PROM
MOS
The MCM270B/27AOB is an B192-bit Erasable and Electrically
Reprogrammable PROM designed for system debug usage and
similar applications requiring nonvolatile memory that could be
reprogrammed periodically. The transparent window on the package
allows the memory content to be erased with ultraviolet light.
Pin-for-pin m"sk-programmable ROMs are available for large volume
production runs of systems initially using the MCM270BI27AOB.
•
Organized as 1024 Bytes of 8 Bits
•
Static Operation
•
Standard Power Supplies of +12 V, +5 V and - 5 V
•
Maximum Access Time
= 300
ns 450 ns -
(N-CHANNEL, SILICON-GATE)
1024 X a-BIT
UV ERASABLE PROM
MCM27A08
MCM2708
•
Low Power Dissipation
•
Chip-Select Input for Memory Expansion
•
TTL Compatibl~
•
Three-State Outputs
•
Pin Equivalent to the 2708
•
Pin-for-Pin Compatible to MCM65308, MCM68308 or 2308
Mask-Programmable ROMs
FRIT·SEAL CERAMIC PACKAGE
CASE 623A-02
CERAMIC PACKAGE
CASE 716-07
PIN CONNECTION DURING READ OR PROGRAM
Mode
,Pin Number
9-11,13-17
12
18
19
20
21
24
Read
Dout
VSS
VSS
VDD
VIL
VBB
Vec
Program
Din
VSS
Pulsed
VIHW
VBB
VCC
r
VDD
PIN ASSIGNMENT
VIHP
Vee
--
AS
ABSOLUTE MAXIMUM RATINGS (11
Rlting
A9
Value
Unit
Opt-fating Temperature
'Oto+70
Storage Temperature
-65 to +125
°c
°c
VOO with Respect to Vee
+20 to -0.3
Vdc
VOO
VCe and VSS with Respect to VaB
+ 15 to -0.3
Vdc
PROGR.
All Input or Output Voltages with Respect to Vee during Read
+15to-0.3
Vdc
+20 to -0.3
Vdc
CSIWE Input with Respect to
Vee during Programming
~ram .'np~_t with Respect to Vee
Power Dissipation
+35 to -0.3
Vdc
1.8
Watts
Note 1:
Permanent device damage may occur if
ABSOLUTE MAXIMUM RATINGS .re
VSB
CS/WE
07
DO
06
01
05
02
04
VSS
exceeded. Functional
op~ration should
be restricted to RECOMMENDED OP·
ERATING CONDITIONS. Exposur. to
higher than recommended voltages for
extended periods of time could affect
device reliabilitv.
OS9440 R2/1-79
2-102
MCM2708-MCM27A08
BLOCK DIAGRAM
DC READ OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted.)
RECOMMENDED DC READ OPERATING CONDITIONS
Paramet.r
SupplV Voltage
Symbol
Min
Nom
MIx
VCC
4.75
5.0
5.25
Vdc
VOO
11.4
12
12.6
Vdc
-5.0.
Unit
VBB
-5.25
-4.75
Vdc
Input High Voltage
VIH
3.0
-
VCC + 1.0
Vdc
Input Low Voltage
Vil
VSS
-
0.65
Vdc
Symbol
READ OPERATION DC CHARACTERISTICS
Charlcteristic
Address and CS Input Sink Current
Output Leakage Current
VOO Supply Current
VCC Supply Current
V BB Supply Current
J
I
(Note 21
I
Max
Unit
lin
Min
-
Typ
= Vil
Vout = 5.25 V. CS/WE = 5 V
1
10
,.A
IlO
-
1
10
,.A
Worst-Case Supply Currents
100
.-
50
65
mA
All Inputs High
ICC
Condition
Yin - 5.25 V or Yin
CS/WE
= 5.0 V. TA
' OoC
IBB
.
-
6
10
mA
30
45
mA
0.45
V
800
VOL
-
OU1Put High Voltage
IOH - -100,.A
VOH1
3.7
Out·put High Voltage
IOH - -1.0 mA
VOH2
2.4
-
Po
-
-
Output Low Voltage
Power Dissipation
IOl = 1.6 mA
(Note 21
TA = 70°C
V
-
V
mW
Not. 2:
The total power dissipation is specified at 800 mW. It is not calculable by summing the various ~urrent (100. ICC. and Ise) multiplied by
their respective Yoltages, since current paths exist between the various power supplies and VSS. The IOO( ICC. and
used to determine power supply capacity only.
•
VBB must be applied prior to Vee and VOO. VaB must. also be the last power supply switched off.
2-103
lea currents should
be
MCM27oa-MCM27Aoa
AC READ OPERATING CONDITIONS AND CHARACTERISTICS
(Fu" operating voltage and temperature range u·nless otherwise noted.)
(A" timing with tr = tf = 20 ns, Load per Note 3)
MCM2708
MCM27A08
Symbol
Char.cteristic
Min
Tyi'
Max
Min
Typ
Max
Unit
220
300
-
280
450
ns
60
120
-
60
120
ns
-
-
0
-
-
ns
120
0
120
n.
Addre.. to Output Delay
tAO
Chip Select to Output Delay
tco
-
Data Hold from Address
tDHA
0
Data Hold from Deselection
tDHD
0
CAPACITANCE (periodically sampled r8ther than 100% tested)
Characteristic
Input Capacitance
Condition
Symbol
Typ
Max
Unit
Vin ; 0 V. TA ; 25°C
Cin
4.0
6.0
pF
V out ; 0 V. TA; 25°C
Cout
8.0
12
pF
(f; 1.0 MHz)
Output Capacit8.nce
(f; 1.0 MHz)
Noto 3:
Output Load; 1 TTL Gate and CL ; 100 pF (Include. Jig Capacitance)
Timing Measurement Reference Levels;
Inputs:
0.8 V and 2.8 V
Outputs: 0.8 V and 2.4 V
AC TE8T LOAD
5_0 v
RL=2.2k
Test Poont
00---00 and 300 to 7M are to be pro·
grammed. All other bits are "don't care". The
program pulse width is 0.5 ms. The minimum
number of program loops
,
N
= 100
= 200 .
0.5
One
program loop consists of words 0 to 1023. The
data entered into the "don't care" bits should be
all 15.
3. Same requirements as example 2, but the EPROM is
now to be updated to include data for words S50
to SSO. The minimum number of program loops is
the same as in the previous example, N = 200. One
program loop consists of words 0 to 1023. The data
entered into the "don't care" bits should be all 15.
Addresses 0 to 200 and 300 to 100 must be reo
programmed with their original data pattern.
ERASING INSTRUCTIONS
The' MCM270S/27 AOS can be erased by exposure to
high intensity shortwave ultraviolet light, with a wave·
length of 2537 A. The recommended integrated dose (i.e.,
UV·intensity x exposure time) is 12.5 Ws/cm 2. As an
example, using the "Model 30·000" UV·Eraser (Turner
Designs, Mountain View, CA94043) the ERASE·time is
30 minutes. The lamps should be used without shortwave
filters and the MCM270S/27AOS should be positioned
about one inch away from the UV·tubes.
2-107
®
MCM2716
MCM27L16
MOTOROLA
2048 x 8-BIT UV ERASABLE PROM
MOS
(N-CHANNEL, SILICON-GATEI
The MCM2716127L 16 is a 16,384-bit Erasable and Electrically
Reprogrammable PROM designed for system debug usage and similar
applications requiring nonvolatile memory that could be reprogrammed
periodically. The transparent lid on the package allows the memory content to be erased with ultraviolet light.
For ease of use, the device operates from a single power supply and
has a static power-down mode. Pin-for-pin mask programmable ROMs
are available for large volume production runs of systems initially using
the MCM2716127L 16.
•
•
•
•
Single 5 V Power Supply
Automatic Power-down Mode (Standbyl
Organized as 2048 Bytes of B Bits
Low Power Version 27L 16/27L 16-35 Active 50 mA Max
Standby 10 mA Max
27L 16-25 Active 70 mA Max
Standby 15 mA Max
2048x8-BIT
UV ERASABLE PROM
L SUFFIX CERAMIC PACKAGE
ALSO AVAILABLE - CASE 7t8
• TTL Compatible During Read and Program
• Maximum Access Time =450 ns MCM2716
350 ns MCM2716-35
250 ns MCM2716-25
PIN ASSIGNMENT
• Pin Equivalant to Intel's 2716
• Pin Compatible to MCM68A316E
• Output Enable Active Level is ·User Selectable
A7
MOTOROLA'S PIN-COMPATlILE EPROM FAMILY
121(
.....,
..•.,
11K
-
Vce
A6
AS
A5
AS
A4
Vpp
A3
G
A2
AtO
At
E/Progr
AO
007
000
006
Oat
005
002
004
VSS
003
MOTOROLA'S PIN-COMPATIILE ROM FAMILY
AI
• Pin NIIfn8I
..
'" "
...",'---_
.....-
A.
.. Address
DO .... Data Input/Output
E/Progr .... Chip Enable/Program
G .... Output Enable
• New Industry standard nomenclature
INDUSTRY STANDARD PINOUTS
OS9817/ 4-80
2-108
MCM2716-MCM27L 16
ABSOLUTE MAXIMUM RATINGS
R8IIng
Temperature Under Bias
Operating Temperature Range
Storage Temperature
All Input or Output Voltages with Respect to VSS
Vpp Supply Voltage with Respect to VSS
Vllue
Unit
-10 to +80
o to + 70
-65 to +125
+6 to -0.3
+28 to -0.3
·C
·C
·C
Vdc
This device contains circuitry to protect the inputs
against damage due to high static voltages or alec!ric fields; however, it is advised that normal precautions be taken to avoid application of any voltage
higher than maximum rated voltages to this highimpedance circuit.
Vdc
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
MODE SELECTION
PIn Number
&-11,
Mode
13-17
Read
DO
12
VSS
18
E/Progr
VIL
Don't Car,
21
Vpp
VCC
VCC
Data Out
VSS
Output Disable
High Z
VSS
Standby
High Z
VSS
Program
Data In
VSS
Program Verify
Data Out
VSS
VIL
Program Inhibit
High Z
VSS
VIL
VIH
VIH
Pulsed
VIL to VIH
VIL
Vce'
VIH
Don't Care
Vcc'
Vce
Vee'
VCC
VIH
VIHP
Vce
VIL
VIHP
VIHP
VCC
VCC
'In the Read Mode if VPP~VIH, then G (active lowl
VpP:sVIL, then G lactive highl
BLOCK DIAGRAM
Data Input/Output D~DQ7
~
FIGURE 1 - AC TEST LOAD
6.0V
E/Progr
~
TestP~nto-~--~--i4t--i
• loci pF
Y Gating
AO-Al0
'Includes Jig Capacitance
Memory
Matrix
(128)( 1281
2-109
24
20
G·
MMD6160
or Equiv.
MMD7000
or Equiv.
MCM2716-MCM27L16
CAPACITANCE If= 1.0 MHz. T = 25°C. periodically sampled rather than 100% testedl
Ch.r.cteri8tic
Input Capacitance (V ,n = 0 VI
Output Capacitance (Vout-O VI
~
Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C =
Il.v·
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted)
P.-
RECOMMENDED DC OPERATING CONDITIONS
-.---
Symbol
MCM27L 161MCM2716
Supply Voltage·
MCM27L 16-351 MCM27L 16-251 MCM2716·351 MCM2716·25
VCC
Vpp
Input High Voltage
VIH
Input Low Voltage
VIL
Min
Nom
Mex
4.75
4.5
VCC-0.6
5.0
5.0
5.0
5.25
5.5
VCC+0.6
2.0
-0.1
-
-
VCC+ 1.0
O.B
Unit
Vdc
Vdc
Vdc
RECOMMENDED DC OPERATING CHARACTERISTICS
Condition
Ch.racteristic
Address. G and EI Progr Input Sink Current
Output Leakage Current
VCC Supply Current (Standbyl 2716/2716-35
VCC Supply Current (Standbyl 2716-25
VCC Supply Current (Activel 2716i2716-35
VCC Supply Current (Activel 2716-25
Symbol
MCM2718
Typ
Mex
Unlte
Min
Typ
Mex
10
,.A
10
,.A
Vin=5.25 V
'in
-
Vo~t-5.25 V
G=50 V
ILO
-
-
10
10
-
-
ICCl
-
-
25
-
-
10
mA
ICCl
-
-
25
-
-
15
mA
ICC2
-
-
100
-
-
50
mA
ICC2
-
-
120
-
-
70
mA
IpPl
-
5.0
mA
EI P!.ogr= VIH
G=VIL
E'!P~gr-VIH
G/VIL
(Outputs Open I G=EIProgr=
VIL
G - E/Progr(Outputs Openl
VIL
Vpp=5.B5 V
Output Low Voltage
IOL=2.1 mA
VOL
-
Output High Voltage
IOH-
IDJ,.A
VOH
. 2.4
'Vpp Supply Current·
MCM27L18
Min
-
5.0
0.45
-
0.45
2.4
V
V
·VCC must be applied Simultaneously or prior to Vpp. Vce must olso be switched off Simultaneously With or alter Vpp. With Vpp connected
directly to VCC during the read operation. the supply current would then be the sum of IPPl and ICC. The additional 0.6 V tolerance on Vpp
makes it possible to use a driver circuit for switching the Vpp supply pin from VCC in Read mode to ± 25 V for programming. Typical values a,.
for T A = 25°C and nominal supply voltages.
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage ond temperature range unless otherwise notedl
Input Pulse Levels ..
Input Rise and Fall Times.
Characteristic
Address Valid to Output Valid
EI Progr to Output Valid
Output Enable to Output Valid
EI Progr to Hi-Z Output
Output Disable to Hi-Z Output
Data Hold from Address
. .0.8 Volt and 2.2 Volts
..20ns
Input and Output Timing Levels .......... 2.0 and 0.8 Volts
Output Load ..
. ....................... See Figure 1
Condition
Symbol
EI Progr = G = VIL
tAVOV
INote 21
lELOV
E/Progr= VIL
-
MCM2718-25 ~CM2718-3I MCMZ718
Unite
Min Max Min Mex Min Mex
-
350
350
150
-
100
0
0
100
0
0
-
0
250
250
tGLOV
-
tEHOZ
0
r/Progr- VIL
tGHOZ
EI Progr= G=VIL
tAXDX
2-110
450
450
150
-
100
0
100
100
0
100
-
0
-
150
ns
Jl'CM2716eMCM27L 16
READ MODE TIMING DIAGRAMS (EI Progr= VILI
Output Valid
STANDBY MODE IOutput Enable = VILI
Standby Mode 1E"/Progr=VIHI
A IAddressl
Active Mode
tELQV INote 21
o IData Out!
Output Valid
NOTE 2: tELQV is referenced to !"/Progr or stable address, whichever occurs last.
DC PROGRAMMING CONDITIONS AND CHARACTERISTICS
ITA=25°C±5°CI
RECOMMENDED PROGRAMMING OPERATING CONDITIONS
Unit
Symbol
Min
Nom
Max
Supply Voltage
VCC
VPP
4.75
24
5.0
5.25
25
26
Input High Voltage for Data
VIH
2.2
-
Input Low Voltage for Data
VIL
-0.1
-
VCC + 1
0.8
Cond~ion
Symbol
Min
Typ
Ma.
Un~
Yin = 5.25 V 10.45 V
III
-
-
10
"Ade
mAde
Parameter
Vde
Vde
Vde
PROGRAMMING OPERATION DC CHARACTERISTICS
Characteriotic
Address, G and E/Progr Input Sink Current
VPP Supply Current IVpp = 25 V ± 1 VI
E/Progr= VIL
IPPl
-.
VPP Programming Pulse Supply Current IVpp = 25 V ± 1 VI
EI Progr= VIH
IPP2
-
-
30
mAde
-
ICC
-
-
160
mAde
Symbol
Min
Max
Unit
tAVEH
2.0
VCC Supply Current IOutputs Openl
10
AC PROGRAMMING OPERATING CONDITIONS AND CHARACTERISTICS
Characteriotic
tELAX
2.0
Output Enable Hold Time
tELGL
2.0
Data Hold Time
tELOZ
2.0
VPP Setup Time
tPHEH
0
Vpp to Enable Low Time
tELPL
0
-
Output Disable to High Z Output
Output Enable to Valid Data IE/Progr- VILt
tGHQZ
0
150
tGLQV
-
150
ns
1·
5
55
-
ms
Program Pulse Rise Time
tEHEL
tpR
Program Pulse Fall Time
tPF
5
-
ns
Address Setup Time
2.0
-- r.!9.1-W 2.0
. _ - - - ~H
Output Enable High to Program Pulse
Data Setup Time
Address Hold Time
Program Pulse Width
-If shorter than 45 ms (min) pulses are used, the same number of pulses should be applied after the specific data has been verified.
2-111
"s
"s
"S
"s
"s
"s
ns
ns
ns
ns
MCM2716eMCM27L16
PROGRAMMING OPERATION TIMING
OIA~RAM
Program
A IAddressl
Program Verily
Address N Valid
t+----tELAX----~
G IOutput
Enablel
o or a 10atai
tGHEH
.tOVEH
..--.;;;..;.;---tEHEL
E/Progr
tPR
(t
r-tPHEH
ELPL
PROGRAMMING INSTRUCTIONS
After the completion of an ERASE operation, every bit in
the device is in th!l "1" state Irepresented by Output Highl.
Data are entered by programming zeros IOutput Low) into
the required bits. The words are addressed the same way as
in the READ operation. A programmed "0" can only be
changed to a "1" by ultraviolet light erasure.
To set the memory up for Program Mode, the Vpp input
IPin 21) should be raised to + 25 V. The Vee supply voltage
is the same as for the Read operation and G is at VIH. Programming data is entered in S-bit words through the data out,
100) terminals. Only "O's" will be programmed when "O's"
and "1's" are entered in the S-bit data word.
After address and data setup, a program pulse IVIL to
VIH) 'is applied to the EiProgr input. A program pulse is applied to each address location to be programmed. To
minimize programming time, a 2 ms pulse width is recommended. The maximum program pulse width is 55 ms;
therefore, programmi!lg must not be attempted with a dc
signal applied to the E/Progr input.
Multiple MCM2716s may be programmed in parallel by
connecting together like inputs and applying the program
pulse to the EI Progr inputs. Different data may be programmed into multiple MCM2716s connected in parallel by using
the PROGRAM INHIBIT mode. Except lor the E/Progr pin,
all like inputs !including Output Enable) may be common,
2-112
The PROGRAM VERIFY mode with Vpp at 25 V is used to
determine that all programmed bits were correctly programmed.
READ OPERATION
After access time, data is valid at the outputs in the READ
mode, With stable system addresses, effectively faster access time can be obtained by gating the data onto the bus
with Output Enable.
The Standby mode is available to reduce active power
dissipation. The outputs are in the high impedance state
when the E/Progr input pin is high IVIH) independent of the
Output Enable input.
ERASING INSTRUCTIONS
The MCM2716127L 16 can be erased by exposure to high
intensity shortwave ultraviolet light, with a wavelength of
2537 angstroms. The recommended integrated dose li.e.,
UV-intensity X exposure time) is 15 Ws/cm 2. As an example, using the "Model 30-000" UV-Eraser ITurner Designs,
Mountain View, CA 94043) the ERASE-time is 36 minutes.
The lamps should be used without shortwave filters and the
MCM2716/MCM27L 16 should be positioned about one inch
away from the UV-tubes.
MCM2716-MCM27L 16
TIMING PARAMETER ABBREVIATIONS
TIMING LIMITS
The table of timing values shows either a minimum or a
maximum limit for each parameter. l!'\Put requirements are
specified from the external system point of view. Thus, address setup time is shown as a minimum since the system
must supply at least that much time (even though most
devices do not require it). On the other hand, responses from
the memory are specified from the device point of view.
Thus, the access time is shown as a maximum since the
device never provides data later than that time.
t X X X X
signal name from which interval is defined ----1
transition direction for first signal
signal name to which interval is defined
transition direction for second signal
III
The transition definitions used in this data sheet are:
H = transition to high
L = transition to low
V = transition to valid
X = transition to invalid or don't care
Z = transition to off (high impedance I
WAVEFORMS
Input
Output
Must Be
Valid
Will Be
Valid
~
Change
From H to L
Will Change
From H to L
Jlll7
Change
From L to H
Will Change
From L to H
lYlll'&
Don't Care:
Any Change
Permitted
Changing
Waveform
Symbol
State
Unknown
High
Impedance
=:)-
2-113
®
TM52716
TM527A16
MOTOROLA
MOS
2048 X 8 ERASABLE PROM
The TMS2716 and TMS27A16 are 16,384-bit Erasable and
Electrically Reprogrammable PROMs designed for system debug
usage and similar applications requiring nonvolatile memory that
could be reprogrammed periodically _The transparent window on the
package allows the memory content to be erased with ultraviolet
light. The TMS2716 is pin compatible with 2708 EPROMs, allowing
easy memory size doubling.
•
IN-CHANNEL, SILICON-GATEI
2048 X 8-BIT
UV ERASABLE PROM
Organized as 2048 Bytes of 8 Bits
•
Fully Static Operation (No Clocks, No Refreshl
•
Standard Power Supplies of + 12 V, + 5 V, and - 5 V
•
Maximum Access Time = 300 ns - TMS27A 16
450 ns - TMS2716
•
Chip-Select Input for Memory Expansion
•
TTL Compatible - No Pull-up Resistors Required
•
Three-State Outputs for OR-Tie Capability
•
The TMS2716 is Pin Compatible to MCM2708 and
MCM68708 EPROMs
.
fRIT·SEAL PACKAGE
CAS E 623A-02
CERAMIC PACKAGE
CASE ·716-07
PIN ASSIGNMENT
BLOCK DIAGRAM
Data Input/Output
A7
000-007
A6
A5
A4
A3
A2
Al
Y Gating
DOl
D02
VSS
AO-Al0
PIN NAMES
AO-AID
Memory Matrix
(128 X 128)
DOO-DOl
.Address Inputs
Data Input (Program or
VOD
Output (Read)
. Program Enable
Chop Select
Program Pulse
- 5 V Power Supplv
+ 5 V Power SupplV
+ 12 V Power SupplV
VSS
... Ground
(EI.
~
(Progrl
VBB
VCC·
059618 Rll1-19
2-114
TMS2716eTMS27A 16
ABSOLUTE MAXIMUM RATINGS (1)
Value
Unit
o to + 70
°e
. -65 to + 125
°e
+20 to -0.3
V
+ 15 to -0.3
V
+15to-0.3
V
Rating
Operating Temperature
Storage Temperature
VOO with Respect to
Vas
Vee and VSS with Respect to Vas
All Input or Output Voltage with Respect to
IE) 'nput with Respect to
Vas
Program 'nput with Respect to
Vee
During Read
During Programming
+20 to -0.3
V
Vas
+35 to -0.3
V
1.8
Watts
Power Dissipation
PIN CONNECTION OURING
REAO OR PROGRAM
Pin Number
Mod.
9-11,
13-17
18
24
Read
D out
V'L or
Vee
Program
Din
VIH
Pulsed
VIHW
VIHP
NOTE 1: Permanent device damage may occur it ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
DC READ OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted)
RECOMMENDED DC READ OPERATING CONDITIONS
Svmbol
Min
Nom
Max
Unit
TMS2716
Vee
Voo
Vee
4.75
11.4
-5.25
5.0
12
-5.0
5.25
12.6
-4.75
V
V
V
TMS27A16
Vee
VOO
Vee
4.5
10.8
-5.5
5.0
12
-5.0
5.5
13.2
-4.5
V
V
V
Parameter
Supplv Voltage
Input High Voltage
VIH
2.2
-
Vee+ 1.0
V
Input Low Voltage
VIL
VSS
-
0.65
V
Condition
Svmbol
Min
TVp
Max
Unit
Vin = VCCmax or Vin "" VIL
lin
-
1
10
~A
ILO
-
1
10
~A
-
65
mA
-
12
mA
-
45
mA
VOL
-
READ OPERATING DC CHARACTERISTICS
Characteristic
Address Input Sink Current
Output Leakage Current
V out :; Vee max and S = 5 V
V DO Supply Current
Worst-Case Supply Currents
·100
Vee Supply Current
All Inputs High
lee
Vee Supply Current
(E)=5DV,TA=00e
Output Low Voltage
IOL = 1.6mA
lee
Output High Voltage
IOH = -100
~A
VOHI
3.7
-
Output High Voltage
IOH--l.0mA
VOH2
2.4
-
0.45
V
-
V
V
Vas must be applied prior to Vee and VOO- VBB must also be the last power supply SWItched off.
CAPACITANCE (periodically sampled rather than 100% tested)
Characteristic
Input Capacitance
Condition
Symbol
TVp
Max
Unit
Vin =OV, TA = 25 0 e
Gin
4.0
6.0
pF
V out =0 V, TA = 25 0 e
C out
8.0
12
pF
If = 1.0 MHz)
Output Capacitance
If = 1.0 MHz)
2-115
TMS2716eTMS27A16
AC READ OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperatUie range unless otherwise noted)
(All timing with tr ~ tf ~ 20 ns, Load ~er Note 2)
TMS2716
Characteristic
Symbol
Min
TMS27A16
Ma.
Min
Ma.
Unit
Addless to Output Delay
'AVOV
450
300
ns
Chip Select to Output Delay
'SLOV
120
120
ns
Data Hold from Address
'AXOZ
10
Data Hold hom Deselect ion
'SHOZ
10
-
120
NOTE 2: Output Load'" 1 TTL Gate and CL = 100 pF (Includes Jig Capacitance)
Timing Measurement Reference Levels - Inputs: 0.8 V and 2.8 V
Outputs: 0.8 V and 2.4 V
TIMING PARAMETER ABBREVIATIONS
10
.
10
120
ns·
ns
AC TEST LOAD
TIMING LIMITS
t X X X X
m'".. ", "'m", --'
transition direction for first signal
Sign.al name .'''m w"m"
III
signal name to which interval is def;ned
transition direction for second signal-
The table of timing values shows eithel a minimum or
a maximum limit for each parameter. Input requirements
are specified from the external system point of view.
Thus, address setup time
IS
shown as a minimum since the
system must supply at least that much time (even though
most devices do not require itl. On the other hand,
The transition definitions used in this data sheet are"
H ~ transition to high
responses from the memory are specified from the device
L =- transition to low
point of "iew. Thus, the access time is shown as a maximum since the deVice never provides data later than
V =- transition to valid
lhat time.
X
=
transition to invalid or don't care
Z
~
transition to off (high impedance)
READ OPERATION TIMING DIAGRAM
Address Valid
Chip Select,S
Data Out, Q
High Z
2-116
TMS2716e TMS27A 16
DC PROGRAMMING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted)
RECOMMENDED PROGRAMMING OPERATING CONDITIONS
Symbol
Min
Nom
Max
Unit
Supply Voltage - TMS2716 and TMS27A16
VCC
VOO
Vaa
4.75
11.4
-5.25
5.0
12
-5.0
5.25
12.6
-4.75
Vdc
Vdc
Vde
Input High Voltage for Data
VIHO
3.8
-
VCC+ I
Vdc
Input Low Voltage for Data
VILO
Vss
_.
0.65
Vdc
Input High Voltage for Addresses
VIHA
3.B
-
VCC + I
Vde
Input Low Voltage for Addresses
VILA
-
0.4
Vde
Program Enable tE) Input High Voltage (Note 3)
VIHW
VSS
11.4
12
12.6
Vdc
Program Enable (E) Input Low Voltage (Note 3)
VILW'VCC
.4.75
5.0
5.25
Vde
Program Pulse Input High Voltage (Note 3)
VIHP
25
27
Vde
Program Pulse Input Low Voltage (Note 4)
VILP
VSS
-
1.0
Vde
Parameter
NOTE 3: Referenced to VSS·
NOTE 4: VIHP - VILP = 25 V min.
PROGRAMMING OPERATION DC CHARACTERISTICS
Characteristic
Address Input Sink Current
Condition
Yin = 5.25 V
Symbol
Min
Typ
Max
Unit
ILl
-
-
10
,!JAde
3.0
mAde
20
mAde
-
65
mAde
15
mAde
-
45
mAde
Program Pulse Source Current
IIPL
-
Program Pulse Sink Current
IIPH
-
VOO Supply Current
Worst-Case Supply Currents
100
Vec Supply Current
All InpufS High
lEI =5V. TA =OoC
ICC
Vas Supply current
laa
-
AC PROGRAMMING OPERATING CONDLTIONS AND CHARACTERISTICS
(Full operating voltage and temperature unless otherwise noted)
Symbol
Min
Max
Address Setup Time
tAVPH
10
IE) Setup Time
tEHPH
10
-
Oat8 Setup Time
tOVPH
10
Addres. Hold Time
tpLAX
1.0
IE) Hold Time
tPLEL
0.5
Characteristic
Unit
/"
/"
/"
-
/"
".
Data Hold Time
tpLOX
1.0
Program to Read Delay
tELQV
-
10
/"
Program Pulse Width
tPHPL
0.1
1.0
m.
".
/"
Program Pulse Rise Time
tPR
0.5
2.0
Program Pulse Fall Time
tPF
0.5
2.0
2-117
/"
TMS2716-TMS27 A 16
PROGRAMMING. OPERATION- TIMING DIAGRAM
1 - - - - - - - - - - - - - 1 of N Program Loops
------------o+-~.-
READ (After N
Program
Loops)
Program
Enable, (E)
tpLEL
Note 5
teHPH
VtHA
Address
a
VILA
tAVPH
tPLAX ----..
V1HD
D.t. Out
Valid
Data Out,
VILD
tPLDX
tOVPH
tPR
IPF
tPHPL
VtHP - -
--
Program
PuisI!', P
V, LP--------------J
NOTE 5: This Program Enable tranistion must occur after the Program Pulse transition and before the Address Transition.
WAVEFORM DEFINITIONS
W,n.form
Input
Waveform
Output
Symbol
MUST BE
~
-Z!l7
Input
Output
Symbol
WII.L 6E
VAUf)
VALID
CHANG(
WILL CHANGE:.
FHOMHTOL
FROM H TO L
CHAr-IGI:.
WILL CHANGE
~H()ML10H
FROM L TO H
~
=:J-
2-118
DON
r
CARE
ANY CHANGE
PERMITTED
CHANGING
STATE
UNKNOWN
HIGH
IMPEDANCE
TMS2716eTMS27A 16
PROGRAMMING INSTRUCTIONS
EXAMPLE FOR PROGRAMMING
Always use the TPtotal = N X tPHPL ;;;. 100 ms
relationship.
1. All 16,384 bits should be programmed with a 0.2 ms
program pulse width.
The minimum number of program loops:
After the completion of an ERASE operation, every bit
in the device is in the "1" state (represented by Output
High). Data are entered by programming zeros (Out·
put Low) into the required bits. The words are addressed
the same way as in the READ operation. A programmed
"0" can only be changed to a "1" by ultraviolet light
N = TPtotal
tPHPL
erasure.
To set the memory up for programming mode, the
VCC(E) input (Pin 24) should be raised to + 12 V. Programming data is entered in 8-bit words through the data
output terminals (000 to 007).
The VDD and Vaa supply voltages are the same as for
the READ operation.
After address and data setup, one program pulse per
address is applied to the program input. A program loop is
a full pass through all addresses. Total programming timel
address, TPtotal = N X tPHPL ;;;. 100 ms. The required
number of program loops (N) is a function of the program
pulse width (tPHPL) where: 0.1 ms" tpHPL " 1.0 ms;
correspondingly, N is: 100 " N " 1000. There must be
N successive loops through all 2048 addresses. It is not
permitted to apply more than one program pulse in
succession to the same address (i.e., N program pulses to
an address and then change to the next address to be
programmed). At the end of a program sequence the
Program Enable (E) falling edge transition must occur
before the first address transition, when changing from
a PROGRAM to a READ cycle. The program pin should
be pulled down to V I LP with an active device, because
this pin sources a small amount of current (lIPL) when
(E) is at VIHW (12 V) and the program pulse is at VILP.
= 100 ms
= 500.
0.2 ms
One program loop consists of words 0 to 2047.
2. Words 0 to 200 and 300 to 700 are to be programmed. All other bits are "don't care". The program
pulse width is 0.5 ms. The minimum number of program
loops, N = 100/0.5 = 200. One program loop consists of
words 0 to 2047. The data entered into the "don't care"
bits should be ali 1s.
3. Same requirements as example 2, but the EPROM is
now to be updated to include data for words 850 to 880.
The minimum number of program loops is the same as in
the previous example, N = 200. One program loop consists
of words 0 to 2047. The data entered into the "don't
care" bits should be ali 1s. Addresses 0 to 200 and
300 to .700 must be reprogrammed with their original
data pattern.
ERASING INSTRUCTIONS
The TMS2716127A16 can be erased by exposure to
high intensity shortwave ultraviolet light, with a wave·
length of 253711.. The recommended integrated dose (i.e.,
UV·intensity X exposure time) is 12.5 Ws/cm 2. As an
example, using the "Model 30·000" UV·Eraser (Turner
Designs, Mountain View, CA 94043) the ERASE·time is
30 minutes. The lamps should be used without shortwave
filters and the TMS2716/27A 16 should be positioned
about one inch. away from the UV·tubes.
2-119
®
MCM68708
MCM68A708
MOTOROLA
1024 X
a ERASABLE
MOS
PROM
The MCM6B70B/6BA708 is a 8192-bit Erasable and Electrically
Aeprogrammable PAOM designed for system debug usage and
similar applications requiring nonvolatile memory that could be
reprogrammed periodically. The transparent window on the package
allows the memory content to be erased with ultraviolet light.
Pin-far-pin mask-programmable AOMs are available for large volume
production runs of systems initially using the MCM6870B/68A708.
•
IN-CHANNEL, SILICON-GATE)
1024 X a-BIT
UV ERASABLE PROM
Organized as 1024 Bytes of 8 Bits
•
Fully Static Operation
•
Standard Power Supplies of + 12 V, +5 V and - 5 V
•
Maximum Access Time ~ 300 ns 450 ns -
MCM68A708
MCM6870B
•
Low Power Dissipation
•
Chip-Select Input for Memory Expansion
•
TTL Compatible
• Three-State Outputs
•
•
•
PIN ASSIGNMENT
Pin Equivalent to the 2708
A7[~~VCC
Pin-for-Pin Compatible to MCM6530B, MCM6830B or 2308
Mask-Programmable A OMs
Bus Compatible to the M6800 Family
PIN CONNECTION OURING READ OR PROGRAM
Mode
12
Read
D out
Program
Din
18
19
VSS
VSS
VDD
VSS
Pulsed
VDD
20
21
24
VIL
VBB
Vee
VIHW
VBB
Vec
23 ~A8
A5[ 3
22 PA9
A4[ 4
21 PV88
A3[ 5
20
CS/Wf
A2[ 6
19
VDD
Al[ I
18
PROGR.
AO[ 8
17
D7
DO[ 9
16
D6
Dl[ 10
15
D5
D2[ 11
14
D4
VSS[ 12
13
D3
Pin Number
9-11,13-17
A6[ 2
VIHP
I
Me6BOQ
MIcroprocessor
I
MCM68708/68A708 READ ONLY
MEMORY BLOCK DIAGRAM
M6800 MICROCOMPUTER FAMILY
BLOCK OIAGRAM
--
--
MCM6B70B
~~8A708
EPROM
Memory
MatriX
----1
>-------1
Random
Acte'!is
Memory
Interface
Adapter
(1024 x 8)
I
-
i
I
Data
Buffers
~
Data Bus
-
Selection
and Control
~
Address
Bus
Interface
Adapter
Modem
I
Mema,J A"" .. "
Data
Bus
and Control
DS9439 Rl/l·79
2-120
MCM68708-MCM68A708
BLOCK DIAGRAM
Data Output
00--D7
ABSOLUTE MAXIMUM RATINGS'
Unit
Valuo
Rating
Storage Temperature
-65 to +125
°c
vc
VDD with Respect to VBB
+20 to -0.3
Vdc
VCC and VSS with Respect to VBB
+15 to -0.3
Vdc
All Input or Output Voltages with
Respect to Vee during Read
CS/WE Input with Respoct to VBB
+15 to -0.3
Vdc
+20 to -0.3
Vdc
o to
Operating Temperature
>70
during Programming
Program Input with Respect to VSS
+35 to -0.3
Vdc
1.8
Watts
Power Dissipation
Not.l:
Permanent device damage may occur if ABSOLUTE MAXIMUM
RATINGS sre exceeded. Functional operation should be restricted
to RECOMMENDED OPERATING CONDITIONS. Exposure to
higher than recommended voltages for . extended periods of time
could affect device reliabilitv.
DC READ OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted.)
RECOMMENDED DC READ OPERATING CONDITIONS
Parameter
Symbol
Min
Nom
Max
Unit
VCC
4.75
5.0
5.25
Vdc
VDD
11.4
12
12.6
Vdc
-5.25
-5.0
-4.75
Vdc
Input High Voltage
VBB.
VIH
VSS +2.0
Vdc
Input Low Voltage
VIL
VSS -0.3
-
VCC
VSS +0.8
Symbol
Min
Tvp
Mox
Unit
lin
-
1
-
1
10
10
Supply Voltage
Vdc
READ OPERATION DC CHARACTERISTICS
Charaeteristic
Condition
Address and CS Input Sink Current
Vin· 5.25 V or Vin - VIL
Output Leakage Current
V out • 5.25 V, CS/WE· 5 V
ILO
Worst-Case Supply Currents
100
All Inputs High
ICC
CS/WE· 5.0 V, TA· OOC
IBB
IOL ·1.6 mA
VOL
-
IOH· -100 "A
VOH
VSS +2.4
VOO Supply Current
VCC Supplv Current
VBB Supply Current
Output Low Voltage
j
J
(Note 2)
I
Output High Voltage
Power Dissipation
(Note 2)
TA·700 C
Po
-
50
6
65
10
30
45
-
VSS +0.4
-
800
-
"A
"A
mA
mA
mA
V
V
mW
Not. 2:
The total power dissipation is specified at 800 mW. It is not calculable by summing the various currents 1100. 'cc. and 'se) multiplied by
their respective voltages. since current paths exist between the various power supplies and VSS. The 100. ICC. and 'ee currents should be
used to determine power supply capacity only.
Vss must be applied prior to Vec and VOO. VBS must aiso be the last power supply switched off.
2-121
MCM68708-MCM68A708
AC READ OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted.)
(All timing with tr = tf = 20 ns, Load per Note 3)
MCM68A708
Characteristic
Min
Typ
Max
Min
Typ
Max
Unit
tAO
-
220
300
-
280
450
-
60
120
-
60
120
-
120
-
120
ns
n.
n.
n.
Address to Output Delay
Chip
Selec~
to Output Delay
Data Hold from Address
Data Hold from Deselection
MCM68708
Symbol
'CO
tDHA
10
.tDHD
10
10
10
CAPACITANCE (periodicaliV sampled ,ather than 100% tested)
Charecteristic
Input Capacitanc.e
(f
Condition
Vin
=0
= 25°C
V, TA
Symbol
Typ
Max
Unit
Cin
4.0
6.0
pF
Cout
8.0
12
pF
= 1.0 MHz)
Output Capacitance
(f = 1.0 MHz)
V out
=0
V, TA
= 25°C
Noto 3:
Output Load = 1 TTL Gate and CL = 100 pF (Includes Jig Capacitance)
Timing Measurement Reference Levels:
.
Inputs:
0.8 V and 2.8 V
Outputs: 0.8 V and 2.4 V
AC TEST LOAD
-M--"
Test Point o--<~-.....
100 pF • ;::~
24 k
MMD6150
or Equiv
MM07000
or Equiv
• Includes Jig Capacitance
READ OPERATION TIMING DIAGRAM
Address
2-122
MCM68708-MCM68A708
DC PROGRAMMING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted.)
RECOMMENDED PROGRAMMING OPERATING CONDITIONS
Paramlter
Supply Voltage
Unit
Symbol
Min
Nom
Max
VCC
4.75
5.0
5.25
Vde
VDD
11.4
12
12.6
Vde
VSS
-5.25
-5.0
-4.75
Vde
Input High Voltage for All Addresses and Data
VIH
3.0
-
VCC + 1.0
Vde
Input Low Voltage (except Program)
VIL
0.65
Vde
VIHW
VSS
11,4
12
12.6
Vde
Program Pulle Input High Voltage (Note 4)
VIHP
25
-
27
Vde
Program Pulse Input Low Voltage (Noie 5)
VILP
VSS
-
1.0
Vde
Symbol
Typ
Max
Unit
-
10
"Ade
3.0
mAde
20
mAde
50
65
mAde
CSIWE Input High Voltage
(Note 4)
NoM 4: Referenced to VSS.
Noto 6: VIHP - VILP = 25 V min.
PROGRAMMING OPERATION DC CHARACTERISTICS
Charlcteriltic
Program Pulse Source Current
IIPL
Program Pulse Sink Current
IIPH
Min
-
Worst-Case Supply Currents
100
-
VCC Supply Current
All Inputs High
ICC
-
6
10
mAde
Vas SuPPly current
CS/WE = 5 V. TA
las
-
30
45
mAde
Condition
Addres. and CSIWE Input Sink Current
VDD Supply Current
Vin = 5.25 V
ILl
=.Ooc
AC PROGRAMMING OPE~ATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature unless otherwise noted.)
Symbol
Min
Max
Unit
Address Setup Time
Characteristic
tAS
10
-
CSIWE Setup Time
-
".
tcss
10
Data Setup Time
tDS
10
".
".
",
".
Address Hold Time
tAH
1.0
-
CSIWE Hold Time
tCH
0.5
-
Dota Hold Time
tDH
1.0
Chip Deselect to Ouptut Float Delay
tDF
0
120
tDPR
-
10
",
Program to Read Delay
".
n.
Program Pulse Width
tpw
0.1
1.0
m.
,.rogram Pulse Rise Time
tPR
0.6
2.0
Program Pulse Fall Time
".
tpF
0.5
2.0
2-123
".
MCM68708·MCM68A708
PROGRAMMING OPERATION TIMING DIAGRAM
1 - - - - - - - - - - - - - 1 of N Program Loops
-------------<--!->--
READ-(After N
Program
Loops)
CS/WE
tCH
NoteS
VIH
Address 0
Address 0
VIL
tAH~
'AS
tAO
(Read)
VIH
Data Out
Valid
Data
VIL
'DH
'OS
'PR
'PW
'OH'PF
'OPR
VIHP
Program
Pulse
VIL------....J
Note 6: The CS/WE transistion must occur after the Program Pulse transition and before the Address Transistion.
2-124
MCM68708·MCM68A708
PROGRAMMING INSTRUCTIONS
After the completion of an ERASE operation, every
.bit in the device is in the "I" state (represented by
Output High). Data are entered by programming zeros
(Output Low) into the required bits. The words are
addressed the same way as in the READ operation. A
programmed "0" can only be changed to a "I i, by ultra·
violet light erasure.
To set the memory up for programming mode, the
CS/WE input (Pin 20) should be raised to +12 V. Pro·
gramming data is entered in 8·bit words through the
data output terminals (DO to 07).
Logic levels for the data lines and addresses and the
supply voltages (Vee, VOO, Vaa) are the same as for the
READ operation.
After address and data setup on8' program pulse per
address is applied to the program input (Pin 18). A pro·
gram loop is a full pass through all addresses. Total
programming time, Tptotal = N x tpw .. 100 ms. The
required number of program loops (N) is a function of the
program pulse width (tpwi. where:· 0.1 ms .;; tpw .;;
1.0ms; correspondingly N is: 100';; N .;; 1000., There
must be N successive loops through all 1024 addresses. It
is not permitted to apply more than one program pulse in
succession to the same address (i.e., N program pulses to
an address and then change to the next address to be pro·
grammed). At the end of a program sequence the eSIWE
falling edge transition must occur before the first address
transition, when changing from a PROGRAM to a READ
cycle. The program pin (Pin 18) should be pulled down
to V ILP with an active device, becaus~his pin sources a
small amount of current (IIPL) when eSIWE is at VIHW
, (12 V) and the program pulse is at V I LP'
EXAMPLES FOR PROGRAMMING
Always use the TPtotal = N x tPW" 100 ms relationship.
1. All 8092 bits should be programmed with a 0.2 ms
program pulse width.
The minimum number of program loops:
N = TPtotal
tpw
= 100 ms = 500.
0.2 ms
One program loop
consists of words 0 to 1023.
2. Words 0 to 200 and 300 to 700 are to be pro·
grammed. All other bits are "don't care". The
program pulse width is 0.5 ms. The minimum
100
number of program loops, N = Q.5 = 200. One
program loop consists of words 0 to 1023. The
data entered into the "don't care" bits should be
all 1s.
3. Same requirements as example 2, but the EPROM is
now to be updated to include data for words 850
to 880. The minimum number of program loops is
the same as in the previous example, N = 200. One
program loop consists of words 0 to 1023. The data
entered into the "don't care" bits should be all 1s.
Addresses 0 to 200 and 300 to 700 must be reo
programmed with their original data pattern.
ERASING INSTRUCTIONS
The MCM68708/68A708 can be erased by exposure to
high intensity shortwave ultraviolet light, with a wave·
length of 2537 A. The recommended integrated dose (i.e.,
UV·intensity x exposure time) is 12.5 Ws/cm 2. As an
example, using the "Model 30·000" UV·Eraser (Turner
Designs, Mountain View, CA 94043) the ERASE·time is
30 minutes. The lamps should be used without shortwave
filters and the MCM68708/68A 708 should be positioned
about one inch away from the UV·tubes.
2-125
®
MCM68732
MCM68L732
MOTOROLA
4096 x 80BIT UV ERASABLE PROM
The MCM68732/68L732 is a 32,768-bit Erasable and Electrically
Reprogrammable PROM designed for system debug usage and similar
applications requiring nonvolatile memory that could be reprogrammed
periodically, or for replacing 32K ROMs for fast turnaround time. The
transparent window on the package allows the memory content to be
erased with ultraviolet light.
For ease of use, the device operates from a single power supply and
has a static power-down mode. Pin-for-pin compatible mask programmable ROMs are available for large volume production runs of systems
initially using the MCM68732/68L732.
MOS
IN-CHANNEL. SILICON-GATE)
4096xB-BIT
UV ERASABLE PROGRAMMABLE
READ ONLY MEMORY
• Single + 5 V Power Supply
• Automatic Power-down Mode (Standby) with Chip Enable
•
•
•
•
Organized as 4096 Bytes of 8 Bits
Low Power Dissipation
Fully TTL Compatible
Maximum AcCess Time = 450 ns MCM68732
350 ns MCM68732-35
• Standard 24-Pln DIP for EPROM Upgradability
• Pin Compatible to MCM68A332 Mask Programmable ROM
• AR Selects the Operational 32K Portion of the Die
MCM68732-1 AR = 1 = HIGH
MCM68732-0 AR = 0= LOW
• Pin Compatible With the MCM2532 32K EPROM in the Read Mode
L SUFFIX SIOEBRAZE CERAMIC PACKAGE
ALSO AVAILABLE - CASE 718
• Low Power Version
MCM68L732 Active 60 mA Maximum
Standby 15 mA Maximum
MCM68L732-35 Active 100 mA Maximum
Standby 25 mA Maximum
PIN ASSIGNMENT
A7
MOTOROLA'S PIN-COMPATIBLE EPROM FAMILY
12K
11K
....
VCC
A6
AS
A5
A9
A4
AA
A3
ENpp
A2
Al0
AI
Al
All
AI
AO
DQ7
000
006
'.
MC_784
001
005
002
004
VSS
003
MOTOROLA'S PIN-COMPATIBLE 110M FAMILY
.......,
....
••
14K
12K
'Pin Names
•
eM
•
GO
Me_liE
A .... Address
AA .... Address Aeference
DO .... Data Input/Output
ENpp .
. Chip Enable/Program
• New industry standard
no~er}cI8ture
INDUSTRY STANDARD PINOUTS
059814 Rl/10-80
2-126
MCM68732-MCM68L732
ABSOLUTE MAXIMUM RATINGS (11
Rating
Temperature Under Bias
Value
Unit
-10 to +80
·C
o to
Operating Temperature Range
+ 70
·C
-65to +125
·C
All Input or Output Voltages with Respect to VSS
+6to-0.3
Vdc
Vpp Supply Voltage with Respect to VSS
+28 to -0.3
Vdc
Storage Temperature
This device contains cirCUitry to protect the inputs
against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage
higher than maximum rated voltages to this highimpedance cirt;uit.
NOTE- Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages tor extended
periods of time could affec.t device reliability
MODE SELECTION
Pin Number
&-11,
13-17,
DO
Mode
Read
12
20
24
VSS
ElVpp
VCC
Data out
VSS
VIL
VCC
High Z
VSS
VIH
VCC
Standby
High Z
VSS
Data in
VSS
VIH
usea
VILP to VIHP
VCC
Program
Output Disable
VCC _
VCC
BLOCK DIAGRAM
Data Input/Output
VSS_
DOO-D07
~
FIGURE 1 - AC TEST LOAD
ElVpp
5.0 V
~M{
Test Point o--~.---'-.-~.I--~
Y Gating
·100pF
Memory
Matrix
A5-Al1 { /
AR
CAPACITANCE If ~ 1.0 MHz. T
r-------Input Capacitance (V ln =
a VI
·Includes Jig Capacitance
~ 25°e. peflodlcally sampled rather ttlan 100% lested.)
___,___
Typ Ma. Unit
-+-"1==+'-!!'+==--+-"=-1
Symbol
C~~~~s_ti_c_________________._ _ _
E::;x::..ce"'p:_t..;t,,/::;V."-P."-P_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-+ Crn
Input Capacitance E/Vpp_________ ._. ____ _
Output Cap<3citance (Vout =
MMD6t50
or EQuiv.
MMD7000
or EQuiv.
a VI
4.0
6.0
pF
100
e ,n
60
pF
------- ---- ----- --- .- --.------+---:--"'---+-::-::--+--,-:---+'----1
Cout
Capacitance measured with a Boonton Meter or effective (;apacltance calculated from
2-127
th~
equatIOn
e~
tt,,,It.V
8.0
12
pF
MCM68732-MCM68L732
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise nO'ed)
RECOMMENDED DC OPERATIN9 CONDITIONS
Parameter
Symbol
Min
Nom
Ma.
VCC
4.75
4.5
5.0
5.0
5.25
5.5
V
Input High Voltage
VIH
2.0
VCC+ 1.0
V
Input Low Voltage
VIL
-0.1
-
0.8
V
MCM68L732/MCM68732
MCM68L732-35/MCM68732-35
Supply Voltage
Unit
RECOMMENDED DC OPERATING CHARACTERISTICS
Characteristic
Condition
--
Ma.
Min
Typ
Ma.
lin
-
10
ILO
10
-
10
~A
ElVpp~O.4
IEL
IEH~ IPL
-
-
10
Vout-5.25 V
-
100
-
-
100
/loA
400
-
25
-
/loA
rnA
25
0.45
-
-
2.4
-
400
-
ElVpp~
V
2.4
VCC Supply Current (Standbyl MCM68732
ElVpp- VIH
ICCl
VCC Supply Current IStandbyl MCM68732-35
ElVpp ~ VIH
VCC Supply Current IActive! MCM6873210utputs Open!
ElVpp- V!L
ICCH- ICC2
-
VCC Supply Current (Active! MCM68732-35 (Outputs Openl
rlVpp~VIL
ICC2
-
Output Low Voltage
lOL~2.1
VOL
-
VOH
2.4
lOH~
Output High Voltage
Units
Typ
Vin~5.25
ElVpp Input Sink Current
MCM68L732
MCM68732
Min
Address Input Sink Current
Output Leakage Current
Symbol
rnA
-400 p.A
-
120
160
15
~A
25
60
mA
100
rnA
0.45
V
-
V
rnA
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted)
Input Pulse Levels ..
Input Rise and Fall Times.
Input Timing Levels ..
.................. 0.8 Volt and 2.2 Volts
. .................................. 20ns
.1.0 Volt and 2 Volts
Output Timing Levels ..
Output Load.
Characteristic
Address Valid to Output Valid
Condition
Symbol
E~VIL
tAVOV
-
E to Output Valid
Eto HI-Z Output
Data Hold from Address
-------
. .... 0.8 Volt and 2 Volts
. See Figure 1
E
=
VIL
MCM6873235
MCM68732
Ma.
350
Min
-
0
100
0
-
Ma.
tELOV
Min
-
tEHOZ
tAXDX
350
READ MODE TIMING DIAGRAM
Address Valid
A (Addressl
ElVpp
a (Output!
High Z
---....;;..----{
High Z
Data Valid
2-128
Units
450
ns
450
ns
0
100
ns
0
-
ns
MCM68732-MCM68L732
DC PROGRAMMING CONDITIONS AND CHARACTERISTICS
IT A = 25 i,5°CI
RECOMMENDED PROGRAMMING OPERATING CONDITIONS
Parameter
Symbol
Min
Nom
Max
Unit
Supply Voltage
VCC
4.75
5,0
5,25
V
Input High Voltage for All Addresses and Data
VIH
2,2
Input Low Voltage for All Addresses and Data
VIL
-0,1
-
VCC ,.. 1
0,8
V
V
V
Program Pulse Input High Voltage
VIHP
24
25
Program Pulse Input Low Voltage
VILP
2,0
VCC
26
6,0
V
Symbol
Min
Typ
Max
Unit
III
-
10
p.A
IPH
-
30
400
mA
-
-
-
-
160
mA
PROGRAMMING OPERATION DC CHARACTERISTICS
Condition
Characteristic
Address Input Sink Current
Vpp Program Pulse Supply Current IVpp
Vpp Supply Current IVpp
Y,n
=
= 5,25 V
"
-
25 V ± 1 VI
= 2.4 VI
-
VCC Supply Current IVpp = 5,0 VI
IPL
=
ICC
IEH
p.A
AC PROGRAMMING OPERATING CONDITIONS AND CHARACTERISTICS
Symbol
Min
Max
Address Setup Time
Cna ..cterillic
tAVPH
2,0
Data Setup Time
tDVPH
2,0
Chip Enable to Valid Data
tELOV
450
Chip Disable to Data In
tEHDV
2.0
-
Unit
p.s
Program Pulse Width
tPHPL
tPR
1.9
2.1
ms
,Program Pulse Rise Time
0.5
2,0
~s
Program Pulse Fall Time
tpF
0.5
2,0
p's
p.S
p.S
ns
Cumulative Programming Time Per Word12
ms
tcp
50
Block mode programming must be used. Block mode programming IS defined as one program pulse applied to each of the 4096 address locations in sequence. Multiple blocks are used to accumulate programming time Itepl.
PROGRAMMING OPERATION TIMING DIAGRAM
A (Addressl
D or 0 IDatal
ElVpp
2-129
MCM68732-MCM68L732
PROGRAMMING INSTRUCTIONS
READ OPERATION
After access time, data is valid at the outputs in the Read
mode. A single input (ElVppl enables the-.9utputs and puts
the chip in active or standby mode. With ElVpp = "0" the
outputs are enabled and the chip is in active mode; with
ElVpp = "'" the outputs are three-stated and the chip is in
standby mode. During standby mode, the power dissipation
is reduced.
Multiple MCM68732s may share a common data bus with
like outputs OR-tied together. In this configuration the
ElVpp input should be high on all unselected MCM68732s to
prevent data contention.
After the completion of an ERASE operation, every bit in
the device is in the "'" state (represented by Output Highl.
Data are entered by programming zeros (Output Lowl into
the required bits. The words are addressed the same way as
in the READ operation. A programmed "0" can only be
changed to a "'" by ultraviolet light erasure.
To set the memory up for Program Mode, the ElVpp input
I Pin 201 should be between + 2.0 and + 6.0 V, which will
three-state the outputs and allow data to be setup on the DO
terminals. The V CC voltage is the same as for the Read
operation. Only "O's" will be programmed when "O's" and
""s" are entered in the a-bit data word.
After address and data setup, 25-volt programming pulse
(VIH to VIHPI is applied to the ElVpp input. A program
pulse is applied to each address location to be programmed.
The maximum program pulse width is 2 ms and the maximum program pulse amplitude is 26 V.
Multiple MCM68732s may be programmed in parallel by
connecting like inputs and applying the program pulse to the
E/Vpp inputs. Different data may be programmed into multiple MCM68732s connected in parallel by selectively applying
the programming pulse only to the MCM68732s to be programmed.
ERASING INSTRUCTIONS
The M CM68732 can be erased by exposure to high intensity shortwave ultraviolet light, with a wavelength of 2537
angstroms. The recommended integrated dose (i.e., UVintensity X exposure timel is '5 Ws/cm 2 As an example, using the "Model 30-000" UV-Eraser (Turner Designs, Mountain View, CA 940431 the ERASE-time is 36 minutes. The
lamps should be used without shortwave filters and the
MCM68732 should be positioned about one inch away from
the UV-tubes.
TIMING PARAMETER ABBREVIATIONS
TIMING LIMITS
t X X X X
Slgn.al name. from. which Interval is defined ---...J
transition direcllon for first signal
Signal name to which interval is defined
tranSition direction for second signal
The table of timing values shows either a minimum or a
maximum limit for each parameter. Input requirements are
specified from the external system point of view. Thus, address setup time is shown as a minimum since the system
must supply at least that much time (even though most
devices do not require it). On the other hand, responses from
the memory are specified from the device point of view.
Thus, the access time is shown as a maximum since the
device never provides data later than that time.
III
The transition definitions used in this data sheet are'
H = transition to high
L = transition to low
V = transition to valid
X = transition to invalid or don't care
Z = trans Ilion to off (high impedancel
Waveform
WAVEFORMS
Input
Output
Sym\>Ol
Valid
Will Be
Valid
. Change
Will Change
Must Be
~
From H to L
From H to L
~
Change
From L to H
Will Change
From L to H
Don't Care:
Changing:
llllm
Any Change
State
Permitted
Unknown
==>-
High
Impedance
2-130
®
MCM68764
MCM68L764
MOTOROLA
MOS
8192 x 8-BIT UV ERASABLE PROM
IN-CHANNEL, SILICON-GATE)
8192x8-BIT
UV ERASABLE
PROGRAMMABLE READ
ONLY MEMORY
The MCM68764/68L764 is a 65,536-bit Erasable and Electrically
Reprogrammable PROM designed for system debug usage and similar
applications requiring nonvolatile memory that could be reprogrammed
periodically, or for replacing 64K ROMs for fast turnaround time. The
transparent window on the package allows the memory content to be
erased with ultraviolet light.
For ease of use, the device operates from a single power supply and
has a static power-down mode. Pin· for-pin mask programmable ROMs
are available for large volume production runs of systems initially using
the MCM68764/68L764.
Single + 5 V Power Supply
Automatic Power-down Mode IStandby) with Chip Enable
Organized as 8192 Bytes of 8 Bits
Low Power Dissipation
Fully TTL Compatible
Maximum Access Time ~ 450 ns MCM68764
350 ns MCM68764-35
• Standard 24-Pin DIP for EPROM Upgradability
• Pin Compatible to MCM68A364 Mask Programmable ROM
•
•
•
•
•
•
C SUFFIX
FAIT-SEAL CEAAMIC PACKAGE
CASE 623A-Q2
24
L SUFFIX CERAMIC PACKAGE
ALSO AVAILABLE - CASE 716-07
• Low Power Version
MCM68L764 Active 60 mA Maximum
Standby 15 mA Maximum
MCM68L764-35 Active 100 mA Maximum
Standby 25 mA Maximum
PIN ASSIGNMENT
Vee
A8
A9
MOTOROLA'S PIN-COMPATIBLE EPROM FAMILY
A12
32K
EIVpp
AIO
Al1
DQ7
006
005
004
MOTOROLA'S PIN-COMPATlBLE ROM FAMILY
32K
Vss
11K
,
,"
.
...
eM
MCM8lA311E
·Pin Names
A .
DO
ElVpp .
INDUSTRY STANDARD PINOUTS .
DQ3
. Address
. Data Input/Output
~/Program
• New Industry standard nomenclature
DS98t5 Rl/9-al
2-131
MCM68764·MCM68L764
ABSOLUTE MAXIMUM RATINGS ISee Notel
Rlting
Vllul
Temperature Under Bias
-10to +60
o to
Operating Temperature Range
Unit
·C
·C
+ 70
-65 to +125
·C
All Input or Output Voltages with Respect to VSS
+610-0.3
VPP Supply Voltage with Respect to VSS
+2810 -0.3
Vdc
Vdc
Storage Temperature
This devIce contains circuitry to protect the inputs
against damage due to high static voltages or electnc fields; however .. it is adVised that normal precautions be taken to avoid application of any voltage
higher than maximum rated voltages to this highimpedance circuit,
NOTE: Permanenl device damage may occur If ABSOLUTE MAXIMUM RA liNGS are exceeded. Functional operation should be restncted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability,
MODE SELECTION
I
Pin Number
~",
ElVpp
24
Vee
Read
Data out
VSS
VIL
VCC
Output Disable
High-Z
VSS
VIH
Vce
Standby
High-Z
VSS
Vee
Program
Data in
VSS
VIH
Pulsed
VILP to VIHP
13-17,
Mode
00
Vce _
..-ss_
12
VSS
20
Vee
BLOCK DIAGRAM
Data Input/Output DOO-D07
/~
FIGURE 1 - AC TEST LOAD
ElVpp
5.0 V
Test Point 0--~-~-"1----1
Y Gating
'100 pF
Memory
Matrix
'Includes Jig Capacitance
2-132
MMD6150
or Equiv.
MMD7000
or Equiv.
~M68764·MCM68L764
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature Tange unless otherwise noted)
" RECOMMENDED DC OPERATING CONDITIONS
Symbol
Peremeter
Input High Voltage
VIH
Min
4.75
4"5
2.0
Input Low Voltage
VIL
-0.1
MCM68L7641 MCM68764
MCM68764-35/MCM68L764-35
Supply Voltage
RECOMMENDED DC OPERATING CHARACTERISTICS
---
VCC
---"-_.
Condition
Characteristic
-Address Input Sink Current
-"
Vin~5.25
V
Vout -5.25 V
Output Leakage Current
tlVpp Input Sink Current
Symbol
lin
-
ElVpp=O.4
IEL
IEH= IpL
VCC Supply Current IStandbyl MCM68764
ElVpp- VIH
ICCI
VCC Supply Current IStandbyl MCM68764-35
ElVpp- VIH
ICCI
VCC Supply Current IActivel MCM68764 IOutputs Open}
ElVpp=VIL
ICC2
VCC Supply Current IActive} MCM68764-35 IOutputs Open}
ElVpp=VIL
ICC2
Output Low Voltage
Output High Voltage
IOL=2"1 mA
VOL
VOH
IOH= -4OO,.A
Me.
Unit
5.25
5.5
Vdc
-
VCC + 1.0
Vdc
-
-
2.4
-
Vdc
. 0"8
MCM88784
Min Typ Me.
ILO
ElVpp=2.4
Nom
5.0
5.0
10
10
100
400
25
25
120
leo
MCM88L764
Unite
Min Typ Me.
-
0.45
-
-
2.4
-
-
-
10
10
100
"A
,.A
,.A
400 , ,.A
15
mA
mA
25
eo mA
100
mA
-
0.45
V
-
-
V
Symbol
Typ
Ma.
Cin
4.0
6.0
100
12
Unit
pF
pF
pF
CAPACITANCE If = 1 0 MHz TA - 25'C periodically sampled rather than 100% tested I
Characteristic
Input Capacitance IV on = 0 VI Except ElVpp
InputCapacotance ElVpp
Output Capacitance IVout=O VI
Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C
=
Cin
eo
Cout
8.0
14t
I1V·
READ MODE TIMING DIAGRAM
Address Valid
A IAddressl
ElVpp
tEHOZ
tAvov/tELOV
Hogh-Z
o IOutputl---------<
Hogh-Z
Data Valid
2-133
MCM68764-MCM68L764
AC OPERATING CONDITIONS AND CHARACTERISTICS
. (Full operating voltage and temperature range unless otherwise notedl
Input Pulse Levels .......................... 0.8 Volt and 2.2 Volts
.. ............................. 20 ns
Input Rise and Fall Times..
Input Timing Levels.
. ................. 1.0 and 2 Volts
Output Timing Levels
Output Load.
Characteristic
Condition
Address Valid to Output Valid
E = VIL
Symbol
MCM68784MCM1111784
36
UniI8
Min Ma. Min Me.
-
tELQV
-
tEHOZ
E - VIL
tAXDX
E to Output Valid
E to Hi-Z Output
Data Hold from Address
........ 0.8 Volt and 2 Volts.
.. ...... See Figure 1
tAVOV
-
450
ns
450
ns
0
350
350
100
0
100
ns
0
-
0
-
ns
DC PROGRAMMING CONDITIONS AND CHARACTERISTICS
lTA=25± 5°CI
RECOMMENDED PROGRAMMING OPERATING CONDITIONS
Symbol
Min
Nom
Ma.
Unit
Supply Voitage
Vee
4.75
5.0
5.25
V
Input High Voltage for All Addresses and Data
VIH
2.2
-
V
Input Low Voltage for All Addresses and Data
Vil
-0.1
-
VCC + 1
0.8
Program Pulse Input High Voltage
VIHP
24
25
26
V
Program Pulse Input Low Voltage
VILP
2.0
VCC
6.0
V
Symbol
Min
Typ
MI.
Unit
III
-
-
10
,.A
mA
PerImeter
PROGRAMMING OPERATION DC CHARACTERISTICS
Cherect.-IeIIc
Condltlon
Address Input Sink Current
Yin
z
5.25 V
-
Vpp Program Pulse Supply Currant IVpp - 25 V ± 1 VI
Vpp Supply Current IVpp - 2.4 VI
-
VCC Supply Currant IVpp-6.0 VI
IPH
IPL - IEH
ICC
-
V
30
400
,.A
mA
160
AC PROGRAMMING OPERATING CONDITIONS AND CHARACTERISTICS
S'fII1bo1
Min
Ma.
2.0
-
Deta Setup Time
tAVPH
tDVPH
2.0
-
,.S
Chip Enable to Valid Data
tELOV
-
ns
Chip Disable to Data In
tEHDV
tpHPL
tpA
450
2.0
-
1.9
2.1
I's
ms
0.5
2.0
,.s
0.5
2.0
~
Ch"lctlrtlllc
Address Setup Time
Program Pulse Width
Program Pulse Rise Time
Program Pulse Fall Time
tPF
tc:p
Unit
,.,
Cumulative Programming Time Per Word·
12
50
m•
• Block mode programming must be used. Block mode programming IS defined as one program pulse applied to each of the 8,192 address locations In sequence. Multiple blocks are used to accumulate programming time hCp).
2-134
MCM68764-MCM68L764
PROGRAMMING OPERATION TIMING DIAGRAM
Address 0
A (Address)
o or
Data Out
IData)
Q
ENpp
tELQV
tDVPH
PROGRAMMING INSTRUCTIONS
READ OPERATION
After the completion of an ERASE operation, every bit in
the device is in the "'" state (represented by Output High!.
Data are entered by programming zeros (Output Low! into
the required bits. The words are addressed the same way as
in the READ operation. A programmed "0" can only be
changed to a "'" by ultraviolet light erasure.
To set the memory up for Program Mode, the ElVpp input
(Pin 2O! should be between +2.0 and +6.0 V, which will
three-state the outputs and allow data to be setup on the DO
terminals. The V CC voltage is the same as for the Read
operation. Only "O's" will be programmed when "O's" and
""s" are entered in the 8-bit data word.
After ,address and data setup, 25-volt programming pulse
(VIH to VIHP) is applied to the ElVpp input. The program
pulse width is 2 ms and the maximum program pulse
amplitude is 26 V.
Multiple MCM68764s may be programmed in parallel by
connecting like inputs and applying the program pulse to the
ElVpp inputs. Different data may be programmed into multiple MCM68764s connected in parallel by selectively applying
the programming pulse only to the MCM68764s to be programmed.
.
'2-135
After access time, data is valid at the outputs in the Read
mode. A single input (ElVpp! enables the outputs and puts
the chip in active or standby mode. With Eivpp= "0" the
outputs are enabled and the chip is in active mode; with
ElVpp= "'" the outputs are three-stated and the chip is in
standby mode. During standby mode, the power dissipation
is reduced.
Multiple MCM68764s may share a common data bus with
like outputs OR-tied together. In this configuration, only one
ElVpp input should be low and no other device outputs
should be active on the same bus. This will prevent data contention on the bus.
ERASING INSTRUCTIONS
The M CM68764 can be erased by exposure to high intenSIty shortwave ultraviolet light, with a wavelength of 2537
angstroms. The recommended integrated dose (i.e., UVintensity X exposure time! is '5 Ws/cm 2 As an example, using the "Model 30-000" UV-Eraser (Turner Designs, Mountain View, CA 94043! the ERASE-time is 36 minutes. The
lamps should be used without shortwave filters and the
MCM68764 should be pOSitioned about one inch away from
the UV-tubes.
®
MOTOROLA
MCM68766
Advance InforIDation
MOS
8192 x 8-BIT UV ERASABLE PROM
IN-CHANNEL, SILICON-GA TEl
The MC68766 is a 66,536-bit Erasable and Electrically Reprogrammabie PROM designed for system debug usage and similar applications
requiring nonvolatile memory that could be reprogrammed periodically,
or for replacing 64K ROMs for fast turnaround time. The transparent
window on the package allows the memory content to be erased with
ultraviolet light.
For ease of use, the device operates from a single power supply that
has an output enable control and is pin-for-pin compatible with the
MCM68366 mask programmable ROMs, which are available for large
volume production runs of systems initially using the MCM68766.
8192 x 8-BIT
UV ERASABLE
PROGRAMMABLE READ ONLY
MEMORY
• Single + 5 V Power Supply
• Organized as 8192 8ytes of 8 Bits
• Fully TTL Compatible
• Maximum Access Time =450 ns MCM68766
350 ns MCM68766-35
• Standard 24-Pin DIP for EPROM Upgradability
• Pin Compatible to MCM68366 Mask Programmable ROM
• Power Dissipation - 160 mA Maximum
FAIT-SEAL CERAMIC PACKAGE
CASE 623A02
L SUFFIX CERAMIC PACKAGE
ALSO AVAILABLE - CASE 71~
PIN ASSIGNMENT
Vce
MOTOROLA'S PIN-COMPATIBLE EPROM FAMILY
AS
A9
AI2
GIVpp
AIO
All
DOl
006
DOl
005
Vss
003
004
MOTOROLA'S PIN-COMPATIBLE ROM FAMILY
32K
11K
·Pin Names
A
DO
ITlVpp
Address
...... Data Input/Output
Output Enable/ Program
• New tndustry standard nomenclature
INDUSTRY STANDARD PINOUTS
ADI843/9-80
2-136
.MCM68766
ABSOLUTE MAXIMUM RATINGS
Rating
Temperature Under Bias
Value
Unit
-1010 -I:1l)
·e
o to
+ 70
-6610 +125
·e
·e
Allinpul or Output Voltages with Respect to VSS
+6 to -0.3
Vdc
Vpp Supply Vollage with Respecl to VSS
+2810 -0.3
Vdc
Operating Temperature Range
Storage Temperature
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage
higher than maximum rsted voltages to this highimpedance circuit.
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
penods of time could affect device reliability.
MODE SELECTION
Pin Number
9-11,
13-17,
DO
Mode
.,
Read
Output Disable
Program
12
20
24
VSS
~/VPP
Vee
Data Out
High-Z
Vss
VIL
Vee
VSS
Vee
Data In
VSS
VIH
Pulsed
VILP to VIHP
BLOCK DIAGRAM
Vee - - .
Vss _
Dala InputlOutput
DOO-D07
~.
FIGURE 1 - AC TEST LOAD
~lVpp
5.0 V
Test Point
o--'--""--1I1111t--+
Y Gating
°100 pF
Memory
Matrix
°lncludes Jig Capacitance
2-137
MM061!iO
or Equiv.
MMD7
MMD6150
or EQuiv
, MM07000
1 TTL Gate and CL - 30 pF
or Equiv
AC CHARACTERISTICS
Characteristic
Symbol
Min
Max
Unit
Icye
350
-
ns
tacelA)
-
350
ns
-
350
ns
150
ns
Cycle Time
Address Access Time
Row Select Access Time
t,ccIRS)
Chip Select to Outf1ut Delay
teo
TIMING DIAGRAM
..
teye
tacdA)
Address
~
I
I
RS
CS
~
2.0 V
0.8 V
~
face( RS)
2.0 V
0.8 V
Y
K
2.0 V
0.8 V
teo
2.0 V
0.8 V
.IS<
2.4 V
04 V
Data Out
~:...
Don't Car.
2-150
. Data Valid
X
X,(X
'V'
MCM667OeMCM6674
CUSTOM PROGRAMMING FOR MCM6670
as VOH; the dots left blank will be at VOL. RO is always
programmed to be blank (VoU. (Blank formats appear at
the end of this data sheet for your convenience; they are
not to be submitted to Motorola, however.)
2. Convert the characters to hexadecimal coding treat·
ing dots as ones and blanks as zeros, and enter this infor·
mation in the blocks to the right of the character font
format. The information for 04 must be a hex one or
zero, and is entered in the left block. The information for
03 thru DO is entered in the right block, with 03 the
most significant bit for the hex coding, and DO the
least significant.
3. Transfer the hexadecimal figures either to punched
cards (Figure 3) or to paper tape (Figurp 5).
4. Transmit this data to Motorola, along with the
customer name, customer part number and revision, and
an indication that the source device is the MCM6670.
By the programming of a single photomask, the cus·
tamer may specify the content of the MCM6670. En·
coding of the photomask is done with the aid of a com·
puter to provide quick, efficient implementation of the
custom bit pattern while reducing the cost of implemen·
tation.
Information for the custom memory content may be
sent to Motorola in the following forms, in order of
preference:
1. Hexadecimal coding using IBM Punch Cards (Fig,
ures 3 and 4).
2. Hexadecimal coding using ASCII Paper Tape Punch
(Figure 5).
Programming of the MCM6670 can be achieved by
using the following sequence:
,. Create the 128 characters in a 5 x 7 font using
the format shown in Figure ,. Note that information at
output 04 appears in column one, 03 in column two,
thru DO information in column five. The dots filled in
and programmed as a logic "'" will appear at the outputs
5. Information should be submitted on an organiza·
tional data form such as that shown in Figure 2.
FtGURE 1 - CHARACTER FORMAT
Character Numbe(tV.J1P/I!~gIAlPClr)
ROW SELECT
TRUTH TABLE
RS3
0
0
0
0
,,
,,
RS2
RS'
,
, ,
,, ,,
0
,0
0
0
0
0
MSB
LSB
Character NumberC@lOfII€1< IA/PrJTJ
HEX
MSB
LSB
00
I F
I 0
I 0
OUTPUT
RO
R'
R2
R3
0
A4
AS
0
R6
R7
HEX
04 03
DO
I C
I 0
I 0
I F
FIGURE 2 - FORMAT FOR PROGRAMMING GENERAL OPTIONS
ORGANIZATIONAL DATA
MCM6670 MOS READ ONLY MEMORY
Customer:
Motorola Use Only:
Company ___________________________________
Quote ________________________
Part No.
Originator ____________________
Phone No. _ _ _ _ _ _ _ _ _ _ _ _ ___
Chip·Select Options:
CS
Part No.:
Speclf. No.:
Active High
Active Low
1
o
D
D
2-151
No·Connect
D
MCM6670eMCM6674
FIGURE 3 - CARD PUNCH FORMAT
Columns
1·9
Blank
10·25 Hex coding for first character
26
Slash (I)
27·42 Hex coding for second character
Slash (I)
43
44·59 Hex coding for third character
60
Slash (I)
61· 76 Hex coding for fourth character
77·7B Blank
79·BO Card number (starting 01; thru 32)
Column lOon the first card contains either a zero or
a one to program D4 of row RO for the first character.
Column 11 contains the hex character for D3 thru DO.
Columns 12 and 13 contain the information to program
Rl. The entire first character is coded in columns 10 thru
25. Each card contains the coding for four characters;
32 cards are required to program the entire 128 characters.
The characters must be programmed in sequence from
the first character to the last in order to establish proper
addressing for the part. Figure 3 provides an illustration of
the correct format.
FIGURE 4 - EXAMPLE OF CARD PUNCH FORMAT
(First 12 Charactors of MCM6670P41
I
08000000011000000000000111110001010101010111110101010101000111101010101010008011
IrJt!""l'II"'J~I~~II~~Mn»nMn.n
• • • ~UUM • • n • • ~~UUM~"U""~~gUMBM~MHAhUQM"MVU"~nnnHn~n • • •
11111111111111111111111111111111111111111111111111111111111111111111111111111111
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2,2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 222 2 2 2
33133133331333333]]] 11131313 3 33 313333313 3 331333333313333133 3 3131113113] 3 31331131
44444444444444444444444444444444444444444444441414141414144444444444444444444444
5555555555555555555\\55555555555555555555555555555555555555555555555555555555555
111116111111111111166"'11111111111111116111116161111111611161666166666111111111
11111111111111111111 J 1 J 111111111111111111111111111111111111111111111111111111111
111111111111111111111111111111111111111111111111111111111111 i 8 8 81111111111111111
9119999999999991999919199199991999991999999999999999999999S3l9999~~ge99999999191
12)4,,".~nUOMn.".~.~nnMn.V
• LON ,- •
5' ANDARO fORM
••• ~UUM»~n.nqn04J~~UUq"~~I~':~~MS'~:
"!.
··!.~~nn~n.".N
•
FIGURE 5 - PAPER,TAPE FORMAT
Frames
Leader
Blank Tape
Allowed for customer use (M ..;;; 64)
1 to M
M + 1, M + 2
CR; LF (Carriage Return; Line Feed)
M T 3 to M + 66 First line of pattern information
(64 hex figures per line)
M +67, M +68 CR;LF
M + 69 to
Remaining 31 lines of hex figures,
M + 2114
each line ,followed by a Carriage Re·
turn and Line Feed
Blank Tape
Frames 1 to M are left to the customer for internal
identification, where M";;; 64, Any combination of alpha·
numerics may be used. This information is terminated
with a Carriage Return and Line Feed, delineating the
start of data entry, (Note that the tape cannot begin with
a CR and/or LF, or the customer identification will be
assumed to be programming data.!
• Frame M + 3 contains a zero or a one to program D4
of row RO for the first character. Frame M + 4 contains
the hex character for D3 thru DO, completing the pro·
gramming information for RO. Frames M + 5 and M + 6
contain the information to program R 1. The entire first
character is coded in Frames M + 3 thru M + 18. Four
complete characters are programmed with each line. A
total of 32 lines program all 128 characters (32 x 4).
The characters must be programmed in sequence from the
first character to the last in order to establish proper
addressing for the part.
2-152
MCM667OeMCM6674
The formats below are given for your convenience in preparing character information for MCM6670 programming. THESE
FORMATS ARE NOT TO BE USED TO TRANSMIT THE INFORMATION TO MOTOROLA. Refer to the Custom Pro·
gramming instructions for detailed procedures.
Character Number _ __
MSB
LSB
HEX
1I0oloOOO
111010000
112 010000
0 0
Character Number _ __
MSB
LSB
Character Number _ _ _ _
HEX
MSB
LSB
HEX
1160ioooo
117010000
0403
DO
MSB
0403
LSB
HEX
MSB
0403
MSB
LSB
Character Number _ __
MSB
HEX
0403
LSB
HEX
Character Num,",er _ __
MSB
0403
DO
Character Number _ _ _
MSB
Character Number _ __
DO
Character Number _ __
LSB
HEX
000
000
000
000
000
000
lieD DOD
117 00000
0403
DO
tJ 0
MSB
LSB
HEX
11000000 o
Rloo000
R200000
R300000
R400000
RS 00000
R60 DOD
117 00000
0403
DO
::B,iBBBB
115 00000
Character Number _ __
Character Number _ __
LSB
0403
MSB
DO
LSB
HEX
Character Number _ __
MSB
HEX
DO .
0403
2-153
LSB
DO
Character Number _ __
MSB
LSB
HFX
RO 0'0000 0
Rloo0oo
R200000
RJooooo
R400000
R500000
R60 000
R700000
04 OJ
DO
ROD DOD 0 0
R100000
R200000
113 00000
R400000
RSOOOoO
RGO DOD
R700000
0403
DO
DO
LSB
HEX
Character Number _ _ _ _
HEX
Character Number _ _ _
MSB
LSB
HEX
0
0
Character Number _ __
LSB
HEX
11000000
Rlooooo
R20 000
RJOoDoo
R40 000
R500000
R60 DOD
R700000
0403
DO
MSB
00
Character Number . _ __
MSB
LSB
HEX
RO 00000
Rlooooo
R200000
RJooODo
1'1 4 00000
R500000
R60 000
R7.ooooo
DO
0403
0 0
MCM667OeMCM6674
FIGURE 6 - MCM6674 PATTERN
2-154
®
MCM66700 MCM66710
MCM66714 MCM66720
MCM66730 MCM66734
MCM66740 MCM66750
MCM66751 MCM66760
MCM66770 MCM66780
MCM66790
MOTOROLA
8192·BIT READ ONLY MEMORIES
ROW SELECT CHARACTER GENERATORS
The MCM66700 is a mask·programmable 8192·blt horizontal·scan
(row select) character generator. It contains 128 characters in
a 7 X 9 matrix, and has the capabilit·, of shifting certain characters
that normally extend below the baseline such as i. y, g, p, and
q. Circuitry is supplied internally to effectively lower the whole
matrix for this type of character-a feature previously requiring
external circuitry.
MOS
A seven-bit address· code is used to select one of the 128 available
characters. Each character is defined as a specific combination of
IN· CHANNEL, SILICON-GATE)
logic Is and Os stored in a 7 X 9 matrix. When a specific four-bit
binary row select code is applied, a word of seven parallel bits appears
at the output. The rows can be sequentially selected, providing
a nine·word sequence of seven parallel bits per word for each
character selected by the address inputs. As the row select inputs
are sequentially addressed, the devices will automatically place
the 7 X 9 character in one of two preprogrammed positions on
the 16-row matrix, with the positions defined by the four row
select inputs. Rows that are not part of the character are
automatically blanked.
The devices listed are preprogrammed versions of the MCM66700.
They contain various sets of characters to meet the requirements
of diverse applications. The complete patterns of these devices
are contained in this data sheet.
8K READ ONL Y MEMORIES
HORIZONTAL·SCAN
CHARACTER GENERATORS
WITH SHIFTED CHARACTERS
C SUFFIX
FAIT-SEAL CEAAMIC PACKAGE
CASE 623-04
• Fully Static Operation
• Fully TTL Compatible with Three·State Outputs
• CMOS and MPU Compatible, Single ± 10% 5 Volt Supply
• Shifted Character Capability
(Except MCM66720, MCM66730, and MCM66734)
• Maximum Access Time = 350 ns
• 4 Programmable Chip Selects (0, 1, or X)
• Pin-far-Pin Replacement for the MCM6570,
Including All Standard Patterns
A2 120A3 110A4 90A5
AS
Decode
SO40-
Aow
1
Output
Buffers
-
j
j
Matrix
Shift
Control
Matrix
(128)
H
I
Matrix
S.lect
CASE7~
PIN ASSIGNMENT
AS3
AS2
~1904
eS4
AS1
03
A6
ASO
f---o 1S 02
05
f---o7
~
I
I'
Vce
f---o 6
r--
P SUFFIX
PLASTIC PACKAGE
f---o 20 06
Decode
(8064)
Blank;n.
BLOCK
DIAGRAM.
24
f---o 5
Memory
Matrix
Address
jJ
,
-
-
f---
AO 150A1 160-
~'
05
01
02
f--<> 17 DO
lL~:Ocs~4
21~)226 236246
Vcc=Pin2
ASO AS 1 AS2 AS3
VSS = Pin 13
D6
D4
DO
A1
eS1
AO
A3
eS2
A2
VSS
OS9516/S-78
2-155
MCM66700 Series
ABSOLUTE MAXIMUM RATINGS
(See Note I, Voltages Referenced to Vss)
Rating
Supply Voltages
Symbol
Valua
Unit
Vee
-0.3 to 7.0
-0.3 to 7.0
o to +70
-55 to +125
Vdc
Input Voltage
Vin
Operating Temperature Range
TA
T stg
Storage Temperature Range
Vde
DC
ue
NOTE 1: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher-than-recommended voltages for
extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted)
RECOMMENDED DC OPERATING CONDITIONS
(Referenced to VSS)
Symbol
Min
Nom
Max
Unit
Supply Voltage
Vec
5.0
5.5
Vde
Input Logic "'" Voltage
VIH
-
VCC
Vde
Input Logic "0" Voltage
Vil
4.5
2.0
-0.3
0.8
Vde
Symbol
Min
Typ
Max
Unit
IIH
-
-
2.5
!JAde
Output low Voltage (Blank)
(lOl = 1.6 mAde)
VOL
0
-
0.4
Vde
Output High Voltage (Dati
(lOH = -205 !JAde)
VOH
2.4
ICC
Po
-
-
BO
mAde
200
440
mW
ein
-
4.0
7.0'
pF
C out
-
4.0
7.0
pF
P.remet.r
DC CHARACTERISTICS
Characteristic
Input Leakage Current
(VIH
= 5.5 Vdc, VCC = 4.5 Vdc)
Power SupplV Current
Power Dissipation
CAPACITANCE
(Periodically sampled rather than
Input Capacitanc.
If - 1.0 MHz)
Output Capacitance
(f
= 1.0 MHz)
Vde
100% tested)
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that
norm. precaution, be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
2-156
MCM66700 Series
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted)
ACTEST LOAD
5.0 V
R L =2.5k
MMD6150
or Equiv
AC TEST CONDITIONS
130 pF
Condition
Value
Input Pulse Levels
11.7 k
.... 07000
or Equi'lt'
0.8 V to 2.0 V
Input Rise and Fall Times
20 ns
Output Load
1 TTL Gate and Cl ; 130pF
AC CHARACTERISTICS
Characteristic
Address Access Time
Row Select Access Time
Chip Select to Output Delay
Symbol
TVp
Max
Unit
tacclA)
250
350
ns
tacclRS)
250
350
ns
tco
100
150
ns
TIMING DIAGRAM
)4-------------- tacc (A) ----------------1..... 1
2.0 V
Address
0.8 V
\4------------ tace( AS) - - - - - - - - - - - - -..- 1
2.0 V
0.8 V
RS
2.0 V
CS
tco------------~
CS
0.8 V
2.4 V
0.4 V
O.t. Out
~
; Oon't Ca'.
2-157
Data Valid
MCM66700 Series
MEMORY OPERATION !Using Positive logic)
Most positive level = 1, most negative level = O.
Addr...
To select one of the 128 characters, apply the appro·
priate binary code to the Address inputs (AO through A6).
can be programmed to occupy 'either of the two positions
in a 7 X 16 matrix. (Shifted characters are not available
on MCM66720, MCM66730, or MCM66734.)
RowSalect
To select one of the rows of the addressed character
to appear at the seven output lines, apply the appropriate
binary code to the Row Select inputs (RSO through RS3).
Output
For these devices, an output dot is defined as a logic 1
level. and an output blank is defined as a logic 0 level.
Programmable Chip Select
The MCM66700 has four Chip Select inputs that can
be programmed with a 1,0, or don't care (not connected).
A dan'; care must always be the highest chip select pin or
pins. All standard patterns have Don't Care Chip Selectexcept MCM66751.
Shifted Characters
These devices have the capability of displaying charac·
ters that descend below the bottom line (such as lowercase
letters i. y, g, p, and q). Internal circuitry effectively drops
the whole matrix for this type of character. Any character
DISPLAY FORMAT
Figure 1 shows the relationship between the logic
levels at the row select inputs and the character row at
the outputs. The MCM66700 allows the user to locate the
basic 7 X 9 font anywhere in the 7 X 16 array. In addition,
a shifted font can be placed anywhere in the same 7 X 16
array. For example, the basic MCM66710 font is
established in rows R14 through R6. All other rows are
automatically blanked. The shifted font is established in
rows R 11 through R3, with all other rows blanked. Thus,
while anyone character is contained in a 7 X 9 array, the
MCM66710 requires a 7 X 12 array on the CRT screen to
contain both normal and descending characters. Other
uses of the shift option may require as much as the full
7 X 16 array, or as Iittle as the basic 7 X 9 array (when
no shifting occurs, as in the MCM66720).
The MCM66700 can be programmed to be scanned
either from bottom to top or from top to bottom. This is
achieved through the option of assigning row numbers in
ascending or descending count, as long as both the basic
font and the shifted font are the same. For example, an
up counter will scan the MCM66710 from bottom to top,
whereas an up counter will scan the MCM66714 from top
to bottom (see Figures 7 and 8 for row designation).
FIGURE 1 - ROW SELECT INPUT CODE AND SAMPLE CHARACTERS FOR MCM66710 AND MCM66720
ROW SELECT
TRUTH TABLE
RS3
RS2
RSl
MCM66710
RSO
OUTPUT
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
RO
Rl
R2
R3
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
R4
RS
R6
R7
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
RS
R9
Rl0
Rll
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
R12
R13
R14
R15
MCM66720
ROW
NO.
0000000
•••••• 0
.00000.
.00000.
.00000.
••••••0
.000000
.000000
.000000
.000000
0000000
0000000
0000000
0000000
0000000
0000000
06
R1S
R14
R13
R12
Rll
Rl0
R9
RS
R7
R6
RS
R4
R3
R2
Rl
RO
DO
2-158
ROW
NO.
0000000
0000000
0000000
0000000
=~~~~~B
.0000.0
.0000.0
• • 000.0
.0 • • • 00
.000000
.000000
.000000
0000000
0000000
0000000
06
DO
RO 0000000
Rl .0 ••• 00
R2 • • 000.0
R3 .0000.0
• • • • • • 0 R4 • • 000.0
.000000 RS .0 • • • 00
.000000 R6 .000000
.000000 R7 .000000
.000000 RS .000000
06
DO
06
DO
••••••0
.00000.
.00000.
.00000.
MCM66700 Series
CUSTOM PROGRAMMING FOR MCM66700
By the programming of a single photomask, the custom·
er may sPlICify the content of the MCM66700. Encoding
of the photomask is done with the aid of a computer to
provide quick, efficient implementation of the custom bit
pattern while reducing the cost of implementation.
Information for the custom memory content may
be sent to· Motorola in the· following forms, in order
of preference:·
1. Hexadecimal coding using IBM Punch Cards
(Figures 3 and 4)
2. Hexadecimal coding using ASCII Paper. Tape Punch
(Figure 5)
they are not to be submitted to Motorola, however.)
2. Indicate· which characters are shifted by filling
in the extra square (dot) in the top row, at the left
(column S).
3. Convert the characters to hexadecimal coding
treating dots as 15 and blanks as Os, and enter this infor·
mation in the blocks to the right of the character font
format. High order bits are at the left, in columns Sand
03. For the bottom eight rows, the bit in Column S must
be 0, so these locations have been omitted. For the top
row, the bit in Column S will be 0 for an unshifted
character, and 1 for a shifted character.
4. Transfer the hexadecimal figures either to punched
cards (Figure 3) or to paper tape (Figure 5).
Programming of the MCM66700 can be achieved by
using the follow sequence:
1. Create the 128 characters in a 7 X 9 font using the
format shown in Figure 2. Note that information at
output 06 appears in column one, 05 in column two,
through DO information in column seven. The ·dots filled
in and programmed as a logic 1 will appear at the outputs
as VOH;thedotsleft blank will be at VOL. (Blank formats
appear at the end of this data sheet for your convenience;
5. Assign row numbers to the unshifted font. These
must be nine sequential numbers (values 0 through 15)
assigned consecutively to the rows. The shifted font is
similarly placed in any position in the 16 rows.
6. Provide, in writing, the information indicated in
Figure 6 (a copy of Figure 10 may be used for this pur·
pose). Submit this information to Motorola together
with the punched cards or paper tape.
FIGURE 2 - CHARACTER FORMAT
Character Number
(eu'!oHIIt.Iv,.".)
MS8
f R'"R,.
II.
I._
R
,
R II
~Ii
RI.
R.
R,
i R.
R 7
LSB HEX
00000000
0000000
DOD DODD
0000000
DIDIII DoolID
1100 110110
1100 011100
l1li00 110110 'I A
DIDID oODIID a ,
S
06
O. 03
DO
Charachtr Number(CtfK!!II&( ",,,,,)
::
I R.
RII
~
R7
R'
MSB
LSB
l1li 01111111111100
0111000110
0l1li11l1li1100
0l1li000110
0111000110
0l1lil1lil1lil1li00
OliO DODD
OliO 0000
11000000
DO
FIGURE 3 - CARD PUNCH FORMAT
Column,
1 - 10
11
12 - 29
30
31 -48
49
50-67
68
69 - 76
77 -78
79 -80
81ank
Asterisk (*)
Hex coding for first character
Slash (I)
Hex coding for second character
Slash (I)
Hex coding for third character
Slash (I)
Blank
Card number (starting 01; through 43)
Blank
Column 12 on the first card contains the hexadecimal
equivalent of column Sand 06 through 04 for the top row of the
first character. Column 13 contains 03 through DO. Columns 14
and 15 contain the information for the next row. The entire first
character is coded in columns 12 through 29. Each card contains
the coding for three characters. 43 cards are required to program the
entire 128 characters, the last card containing only two characters.
The characters must be programmed in sequence from the first
character to the last in order to establish proper addressing for the
part. As an example, the first nine characters of the MCM66710
are correctly coded and punched in Figure 4.
-NOTE: Motorola can accept magnetic tape and truth table formats. For further information contact your local Motorol. ules repreuntltive.
2-159
MCM66700 Series
FIGURE 4 - EXAMPLE OF CARD PUNCH FORMAT
(Fi ..t 9 Choroct'" of MCM66710)
""::-('?C c .=-' ,":: 1? ~?'- ?f'.= !"? ,"r' 1
,
??~
,:' ':-r;:
1:
~?' 1 ?'."~
.-' f ;-, " ,......
J ;"'". " oJ ,. ,1" ,f.: -;'\
'"-.'
II
I
I
IODODDDDDDDIIIIIIIIDDDDDODODOloODOCDOOODODDlololloloo~oooooololololloooooooolODD
1 I II II
l.t~I'IIII~1~11·'~1Inl,nn~nAII~nW1IJ'"U"~IJ~ftqltUII~11"'!I'"~\'\I~~~~!:~WM"~II~""I',)~~,·
I 1 1 1 1 1 1 11 11 11 1 1 1 11 1 111111 111111 1 1 1 1 1 1 1 1 1 1 I 11 1 1 1 111 1 1111111111 I 1 1 1 I 111 jill 1 1 1 111 1
2222222 22 2 2 2222222222 2 212121111111111111221111211111111111111111111111;', 11111111
3111111111111111131111 II 13311111111111111111111111111111111 3 1111111 I
j
JIll J 111111
•••••••••• 14444444.4414111444.4.444444444444441444444444144444444444444444444444
1111111111111111111111111111111111111111111
j j
111111111 J II}; 5 1111 5 5 11111111111511
1656 616 6 656 6 6 6 6 6 6 6 66 6 6 6 66 6 6 6 6 6 E 6 6 6 6 6 6 6 66 66! 6 6 6 6 6 6 6 616 66 E ~ 6 6 6 6 6 6 6 b 6 6 6 6 6 6 6 6 6 6 6 6' 66
11111111111111111111111111111111111111111111111111111111111111111111111111111 7 7 7
"
, 1'1111' hl8 8 8 8111 8 811111111111111111111111111111111 8111
II III ,
81 '881111111118 I
199" 9991!9 9 9 99 99 9!9 9 9 9999 9 9 99 9 9 9 9 9 99 9 9 99 9 9 99 99 9 9 9 9919 9 9 999 9 99 9 9 9 9 ~ 919 9 9 9 9 9 9 9 9 9 9
I I I I I I I I I "" 1/ _'" II '1 01 LI ";: " ,,', l' /1 I; I' II It M II!: lJ;')I" I' 1111 •• II 01.1" II" II q 11101 I'I_',', \1 II
1
SUNO""O FC'I1li !lOll
~Ill
1111 '" il I: U
~
I) 141 11\" I'I 'I,', II:,:! ' In
FIGURE 5 - PAPER TAPE FORMAT
Frames
Leader
1 to M
M+l,M+2
M + 3 to M + 66
M + 67, M + 68
M + 69 to M + 2378
start of data entrv. (Note that the tape cannot begin
with a CR and/or LF, or the customer identification will
be assumed to be programming data.)
Frame M + 3 contai ns the hexadecimal equivalent of
column Sand D6 thru D4 for the top row of the first
character. Frame M + 4 contains D3 thru DO. Frames
M + 5 and M + 6 program the second row of the first
character. Frames M + 3 to M + 66 comprise the first line
of the printout. The line is terminated with a CR and
LF.
Blank Tape
Allowed for customer use (M ';;64)
CR; LF (Carriage Return; Line
Feed)
First line of pattern information
(64 hex figures per line)
CR; LF
Remaining 35 lines of hex figures,
each line followed by a Carriage
Return and Line Feed
The remaining 35 lines of data are punched in sequence
using the same format, each line terminated with a CR
and LF. The total 36 lines of data contain 36 x 64 or
2304 hex figures. Since 18 hex figures are' required to
program each 7 x 9 character, the full 128 (2304 -0- 18)
characters are programmed.
Blank Tape
Frames 1 to M are left to the customer for internal
identification, where M .;; 64. Anv combination of alpha·
numerics mav be used. This information is terminated
with a Carriage Return and Line Feed, delineating the
FIGURE 6 - FORMAT FOR ORGANIZATIONAL DATA
ORGANIZATIONAL DATA
MCM66700 MOS READ ONLY MEMORY
Customer
Customer Part No.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Rev.
Row Number for top row of non-shifted font
Row Number for bottom row of non-shIfted font
Row Number for top row of shifted font
Programmable Chip Select information: 1 "" Active High
CS1_ CS2 _
0
= Active
CS3_ CS4_
2-160
Low
X = Don't Care (Not Connected)
MCM66700 Series
FIGURE 1 - MCM66110 PATTERN
FIGURE B - MCM66114 PATTERN
- - - - - - - - - - - - _ .....,--------------,-.
1000
_ ..--!~1___ ... ~!~ __ .!.o~~_~__ ..
2-161
'101
MCM66700 Series
FIGURE 9 - MCM66734 .PATTERN"
FIGURE 10 - MCM66120 PATTERN"
2-162
MCM66700 Series
FIGURE 11 - MCM66730 PATTERN··
FIGURE 12 - MCM66740 PATTERN
2-163
MCM66700 Series
FIGURE 13 - MCM66750 PATTERN
MCM66751 - Same as MCM66750 except CSI = O. CS2 = O. CS3 = X. and CS4 = X.
FIGURE 14 - MCM66760 PATTERN
2-164
MCIVJ66700 Series
FIGURE 15 - MCM66770 PATTERN
...
···......·.·..... .......
.
.......
·
··.......
..
·
.....
.
··................··.....
..
...•...
...
-
"
e"
.
"
•
•
'
.
··.··. .....
f ..... ·· ..
··.......
....
·
··..:. .....:'.:::!··.· .
i
: ••••• : 1
:
:I
.,
1[.;.
':' ::1 -I:
.... I:.
.....··· . .•...I:I...
..'.,..'... ..
--f •
....
,
I
:
·......
·
.... ·..·.....
....
·
·
.
.....
·.....··. ..· ." ··....
I " •••
,
-~-
~--
-----L....!!.-•.
...
:.--
-
'
---------------'
FIGURE 16 - MCM66780 PATTERN
. '. t:~:~~~~u:~
!5··.··: i.
II
: I ••• :.
.
i'·, i i·' '.!! 51'
1----1....:..F==+-=----+:.:
..:.:·:.:..:.:·c:.·+'·: ·cc·..
:.:cc·=-t· ---" . .~_I·~~_~~,t-•••
•••
• ••
t-
',I
II
•
':
·::···.1 ....::.' •......
.:
,"rr'
__ .+~~_~!~.
I
••••• '
:
i :"ill 5"i ill: iii": i :5.····· ~ iii ·..···i:
, I :- ' . I I I
II
,I
II
II
:
I, II _:
.•. ••. ... !:·_-t -
••••••••
'
••
~-
,.
~.'.'
'
:
••
··r·: ~ ....
I
I•••••• ~
1-'"
.'
t-I
.:.:. ~ ':- _. t••••
~
:
,
i '.
.'
~
.:.
+-.: •• ··4
•
:.
: : •• ,. i:
••
:~-~--T-
I
1 •••••••••••••••••
:
::.' . i! .::
:••••• I:
1 : : :...
••
i :
I
••
I
....' •
' :
1
:
'.
.:
..:
I:··:!
:
: ••
!: ••••
•
• ••••
• ••••
!! : i
!
:
i
.
!
_ ••••• _l'•• :
1 : ••••• :
:-+.
I:
I:
••
i.... ..... ........:._..-.-:1=_' _ ....:1:' -:-r:-
: : I·.
r---1...:,r====-t.::..:",..,.-=-t:.:":.:':.:":.=...
..
.1 •
• • ••
••: 1
I
:
"j'
••
I
••••••••
:
:...
:
:
1
·1··········
·1·
••••• i •• : I
•• : ••••••
I
i ...... ' ...~~~:t.I..:..:........ :.-.~-.~~l. ; ,_.j :_·_·~~~l_~~~!~~ 1"
1----18f-=::.::=.,-t....::.:=='--t:::
••:.::.:::••:.::.=+1-=-=.... ••••• •• ••••• •••••••
••••
!•
II:
i": i i
1Ii·····1
••••
-+ .. ~
- ..~-~.- -t~·-~-·-~··+: ,--c,,=+,=:::c=t"==1
•• I·.l:~i :!
i
: ! .·~:~!l1i ···i···! .i: I·······:
!:
! ••••••• !
:.'
1'.1:
r---1-=-r-:,=:-t--=----+--::::=,-i-'-:~=: +'·~·-:.·.~,i~." .~ •• ····~·.~l.-- ----to! --~~ --+ ... ~.....!. : •••••••••••
••••••• 1
.;;.
:
••••
i:··i···~··· .··1: ••: , .:. ::.
!
:
.;........
:.1I
:: . :. I· •. ! ,.....
1
:
:
~
-:1'';;;;···:
! •••••
..-
. :i·
:.: li~.~·JI~~· ·.. ! I.··
f -.~r
+=C=-+ ___?_'~:+I;;;-.:fl
i.... ·
1
•••••
•••••• ':' -. I •
j
•
L-f'!~l--:~.)\-+ :..~~
L---'====..c:..:=:..:.L==---'-=:.::.:--'-_::..
. L.='- - -'-:.~. .•.:~.)._.J i;~~i~D~~~:~'A:::ll: :;.~ : .~.=:_L=': -:.: :.L:= .L.: .-c =.L:=_'_'_L. : .:. =_"
-_._----_._-- - - - - - - - - - - - - - _ . _ - - '
2-165
MCM66700 Series
FIGURE 17 - MCM86710 PATTERN
2-166
MCM66700 Series
MCM66700 Seri.
Pin Allignment
MCM6570 Seri.
MCM66700 Equivalent
MCM6571
MCM6571A
MCM6572
MCM6573
MCM6573A
MCM6574
MCM6575
MCM6576
MCM6577
MCM6578
MCM6579
MCM66710
MCM66714
MCM66720
MCM66730
MCM66734
MCM66740
MCM66750
MCM66760
MCM66770
MCM66780
MCM667110
MCM6670 Seri.
Pin A.ignment
,.
Delcription
"
"
ASCII, shifted
,.
ASCII, shifted
ASCII
Japenese
Japenese
'.
Math Svmbols
Alphanumeric Control
British, shifted
German, shifted
French. sh ifted
European,lhi!ted
"-,....c:._-,=,
APPLICATIONS INFORMATION
One important appl itation for the MCM66700 series is
in CRT display systems (Figure 18). A set of buffer shift
registers or random access memories applies a 7·bit
character code. to the input of the character generator,
which then supplies one row of the character according
to the count at the four row select inputs. As each row
is available, it is put into the TTL MC7495 shift registers.
The parallel information in these shift registers is clocked
serially out to the Z·axis where it modulates the raster
to form the character.
The MCM66700 series require one power supply of
+ 5.0 volts. When powering this device from laboratory
or system power supplies, it is important that the Absolute
Maximum Ratings not be exceeded or device failure
can result. Sor"e power supplies exhibit spikes or glitches
on their outputs when the ac power is switched on and off.
FIGURE 18 - CRT DISPLAY APPLICATION USING MCM66710
MC7495
~6
9
8
~
3
~
Cho,ec,o, \
~l
~
~
~
0---2.
~
~
AO
DO
17
4
7
Al
01
A2
02
A3
03
A4
04
A5
05
A6
06
RSO RS 1 RS2RS3
21 22 23 2.
5
18
~
6
19
5
~
Count.,.
Cl
C2
2-167
ao
~
al
~
a2
~
MC
Cl
C2
Opo
OPI
OP2
OP3
a3~
MC7495
1 Os
6
MC
9
Cl
8
C2
2
Opo
3
OPI
4
OP2
5
OP3
Pr...t
Control
Os
ao~
al
~
a2
~
10
a3
Z Axil
Input
MCM66700 Series
The formats below are given for your convenience in preparing character information for MCM66700 programming.
THESE FORMATS ARE NOT TO BE USED TO TRANSMIT THE INFORMATION TO MOTOROLA. Refer to the Custom
Programming instructions for detailed procedures.
LSB
MSB
R
R
R
R
R
R
R
R
R
HEX
0000 000
000 0000
000 000
000 0000
000 0000
000 0000
000 000
000 0000
000 0000
5
06
0403
MSB
R
R
R
R
R
R
R
R
R
R
R
R
A
R
A
R
A
00
LSB
000
DOD DODO
R
A
R
R
R
R
A
R
5
000 0000
000 0000
000 0000
DOD 000
000 ODD
000 DODO
0000
ODD
04 03
00
06
R
R
R
R
R
R
R
R
R
00
A
R
R
R
LSB
HEX
R
R
R
R
R
R
R
R
0000
000
04 03
00
R
5
HEX
R
06
0000
000
DOD 0000
R
'ODD DOD
R
R
R
R
R
R
R
5
000 000
000 000
000 0000
000 000
000 0000
0000
ODD
0403
00
06
2-168
0403
00
LSB
HEX
0000 0000
DOD 0000
000 0000
000 0000
000 0000
000 0000
000 000
000 DODO
000
DODO
04 03
00
5 06
Character Number
LSB
MSB
A
06
MSB
R
DOD DODO
DOD 000
000 DODD
R
HEX
Character Number _
0000 0000
000 0000
000 0000
000 0000
000 0000
R
LSB
0000 000
000 0000
000 0000
000 0000
000 0000
000 0000
000 000
000 0000
000 0000
5
Character Number
LSB
0000
0403
MSB
R
06
MSB
06
MSB
Character Number
HEX
Character Number
R
HEX
0000 000
000 0000
000 0000
000 000
000 0000
000 0000
000 000
000 0000
000 0000
5
0000 0000
000 0000
000 0000
000 0000
000 0000
000 0000
000 000
000 DODD
0000
000
0403
00
5
LSB
MSB
Character Number
R
Character Number
Character Number
Character Number
HEX
MSB
R
R
R
R
A
R
R
R
A
LSB
0000 0000
000 0000
000 0000
000 0000
000 0000
000 0000
000 000
000 0000
0000
000
0403
00
5
06
HEX
®
MCM68A30A
MCM68B30A
MOTOROLA
MOS
1024 X 8-BIT READ ONLY MEMORY
IN{;HANNEL, SILICON-GATE)
The MCM68A30A/MCM68B30A are mask-programmable byteorganized memories designed for use in bus-organized systems_
They are fabricated with N-channel silicon-gate technology. For
1024 X 8-BIT
READ ONLY MEMORY
ease ot use. the device operates \rom a s''''g\e power supp\y, has
compatibility with TTL and DTL, and needs no clocks or
refreshing because of static operation.
I
The memory is compatible with the M6800 Microcomputer
Family, providing read only storage in byte increments. Memory
expansion is provided through multiple Chip Select inputs. The
active level of the Chip Select inputs and the memory content are
defined by the customer.
•
Organized as 1024 Bytes of 8 Bits
•
Static Operation
•
Three·State Data Output
•
Four Chip Select Inputs (Programmable)
,\,:,
~
,
_
.
\
.
, ' '
~...
•
Single ±10% 5-Volt Power Supply
TTL Compatible
•
Maximum Access Time
PLASTIC PACKAGE
CASE 709-02
PIN ASSIGNMENT
= 350
ns - MCM68A30A
250 ns - MCM68B30A
GND~~AO
ABSOLUTE MAXIMUM RATINGS IS •• Not. 11
Symbol
Value
Unit
VCC
-0.3 to +7.0
Vdc
Supply Voltage
I nput Voltage
V,n
Operating Temperature Range
Storage Temperature Range
NOTE 1
CEAAMIC PACKAGE
CASE 623-04
P SUFFIX
•
Rating
CSUFFIX
,,~' FAIT-SEAL
-0.3 to +70
o to
TA
Tst9
+70
-65 to +150
Vdc
°c
°c
Permanent deVice ddmage may occur If ABSOLUTE MAXIMUM RATiNGS are ex
ceeded. Functional operation should be restrICted to RECOMMENDED OPERAT
ING CONDITIONS. Exposure to higher than recommended voltages tor extended
23~Al
22 ~A2
DO
2
01
3
02
4
21 pA3
03£ 5
20 'A4
04[ 6
19
~A5
05[ 7
18
~A6
06[ 8
17 pA7
07[ 9
16 pA8
eSl[lO
15pA9
~CS4
CS2[ 11
14
Vee[ 12
13 peS3
periods of time could offect deVice rehabdlty.
MCM68A30A/MCM68BJOA READ ONLY
MEMORY BLOCK DIAGRAM
M6800 MICROCOMPUTER FAMIL Y
BLOCK 01AGRAM
Memory
Matrix
11024 X 8)
Address
Data
Bus
Bus
Data
Buffars
Data Bus
Memory Address
and Control
OS9456 RI/6-78
2-169
MCM68A30A·MCM68B30A
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operatmg voltage and temperature range unless other\o.'lllse noted_)
RECOMMENDED DC OPERATING CONDITIONS
P.rameter
Symbol
Min
Nom
Max
Unit
Supply Voltage
VCC
4.5
50
5.5
Vdc
Input High Voltage
VIH
2.0
-
5.5
Vdc
I nput Low Voltage
VIL
-0.3
-
0.8
Vdc
DC CHARACTERISTICS
Symbol
Min
Typ
Max
Unit
Input Current
IVin ~ 0'0 5.5VI
I,n
-
-
2.5
J.l.Adc
Output High Voltage
VOH
2.4
-
-
Vdc
VOL
-
-
0.4
Vdc
ILO
-
-
10
/.JAde
ICC
--
-
130
mAde
Characteristic
(IOH = -205"AI
Output Low Voltage
IIOL ~ 1.6 mAl
Output Leakage Current (ThreE ·State)
(CS = 0.8 Vor
Cs = 2.0 V, V OUI =0.4 V 10 2.4 VI
Supply Current
IVCC ~ 5.5 V, TA = DoC)
CAPACITANCE
If - 1.0 MHz, T A ~ 25°C. periodically sampled
rather than 100% tested'!
CMr.cteristic
Unit
Symbol
MIX
I nput Capacitance
Cin
7.5
pF
Output Capacitance
Cout
12.5
pF
This device contains circuitry to protect the
Inputs against damage due to high static voltages
or electric fields; hO\l\ever. it is advised that
nor mal precautions be taken to avoid applicat ion
of any voltage higher than maximum rlted voltages to this high·impedance circuit.
BLOCK DIAGRAM
AO
Al
A2
A3
A4
AS'
A6
A7
AS
A9
24
23
22
21
20
19
18
17
16
15
CS1'
CS2'
CS3'
CS4'
10
11
13
14
2
3
4
5
6
Add,ess
Oecode
7
S
9
Vee
• Active level defined by the customer.
= Pin
00
01
02
03
04
05
06
07
12
Gnd'" Pin ;-
2-170
MCM68A30A-MCM68B30A
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature unless otherwise noted.)
(All timing with tr
='
tf = 20 ns, Load of Figure 1)
MCM68A30AL
MCM68B30AL
Symbol
Min
Max
Min
Max
Unit
Cycle Time
teye
350
-
250
-
ns
Access Time
Chip Select to Output Delay
tace
350
250
ns
150
125
ns
Characteristic
-
'CO
Data Hold from Address
'DHA
10
-
10
-
ns
Data Hold from Desetection
'DHD
10
150
10
125
ns
FIGURE 1 - AC TEST LOAD
5.0 V
Telt Point
O-""'---1~--+"-"
130 pF·
11.7 k
MM06150
or Equi ....
~, MM01000
,
or Equiv
• Includes Jig Capacitance
TIMING DIAGRAM
teye
tace
Address
CS
~
2.0 V
~
ir-0.8 V
2.0 V
XXXAX
0.8 V
'CD
2.0 V
0.8 V
"XX
_tOHO~
_tOHA
2.4 V
0.4 V
Data OUt
2-171
XX
MCM68A30A-MCM68B30A
CUSTOM PROGRAMMING
By the programming of a single photomask for the
FIGURE 2 - BINARY TO HEXAOECIMAL CONVERSION
MCM68A30A/MCM68B30A. the customer may specify
the content of the memory and the method of enabling
the outputs.
Information
on
the
MCM68A30A/MCM68B30A
general
should
options
be
of
submitted
B,nary
Data
0
0
0
0
0
0
the
0
0
on
0
0
0
an Organizational Data form such as that shown in Figure
1
0
,
,
Information for custom memory content may be sent
In
,
,
,
0
0
3. ("No Connect" must always be the highest order Chip
Select PII1(sl.1
to Motorola
preference I:
Hexadecimal
Character
one of four forms (shown in order of
,
1
1. Paper tape 'output of the Motowla M6800 Software.
,
,
1
2. Hexadecimal coding uSing IBM Punch Cards.
3. EPROM (MCM2708, MCM27A08, or MCM687081.
,
0
,
,
,
0
2
3
0
0
0
4
,
,
0
5
6
1
7
0
0
0
0
0
0
1
9
9
1
0
A
0
1
1
B
,
0
0
0
c
1
0
1
,
,
1
,
,
0
1
1
0
,
E
F
4. Hand·punched paper tape (Figure 31.
PAPER TAPE
IBM PUNCH CARDS
Included In the software packages developed for the
M6800 Microcomputer Family IS the ability to produce
a paper tape output for computerized mask generation.
The hexadecimal equivalent (from Figure 21 may be
placed on 80 column IBM punch cards as follows:
The assembler directives are used to control allocation
of memory, to assign values for stored data, and for
controlling the assembly process. The paper tape must
specify the full 1024 bytes.
2-172
Step
Column
1
12
Byte "0" Hexadecimal equivalent for
outputs 07 thru 04 (07 ~ M.S.B.I
2
13
Byte "0" Hexadecimal equivalent for
outputs 03 thru DO (03 ~ M.S.B.I
3
14·75
4
77-80
Alternate steps 1 and 2 for consecutive
bytes.
Card number (starting 00011
MCM68A30A-MCM68B30A
FIGURE 3 - HAND·PUNCHED PAPER TAPE FORMII-
r---------------------------------______________________________ o
Frames
Leader
1 to M
M+l,M+2
M+3toM+66
M+67,M+68
M + 69 to M + 2112
Blank Tape
Allowed for customer use (M';;; 64)
CR; LF (Carriage Return; Line
Feed)
First line of pattern information
(64 hex figures per line)
CR;LF
Remaining 31 lines of hex figures,
each line followed bV a Carriage
Return and Line Feed
Blank Tape
Frames 1 to M are left to the customer for internal
identification, where M .;;; 64. Any combination of alpha·
numerics mav be used. This information is terminated
with a Carriage Return and Line Feed, delineating the
start of data entrv. (Note that the tape cannot begin
with a CR and lor LF, o~ the customer identification will
be assumed to be programming data.)
Option A (1024 x 8)
Frame M + 3 contains the hexadecimal equivalent of
~
.• ,.--------------------,
bits 07 thru 04 of bvte O. Frame M + 4 contains bits
03 thru DO. These two hex figures together program bvte
O. Likewise, frames M + 5 and M + 6 program bvte I,
while M + 7 and M + 8 program bvte 2. Frames M + 3 to
M + 66 comprise the first line of the printout and program,
in sequence, the first 32 bvtes of storage. The line is
terminated with a CR and LF.
Option B (2048 x 4)
Frame M + 3 contains the hexadecimal equivalent
of bvte 0, bits 03 thru DO. Frame M + 4 contains bvte I,
frame M + 5 byte 2, and so on. Frames M + 3 to M + 66
sequentially program bytes 0 to 31 (the first 32 bytes).
The line is terminated with a CR and LF.
Bot!! Options
The remaining 31 lines of data are punched in sequence
using the same format, each line terminated with a CR
and LF. The total 32 lines of data contain 32 x 64 or
2048 characters. Since each character programs 4 bits of
information, a full 8192 bits are programmed.
As an example, a printout of the punched tape for
Figure 13 would read as shown in Figure 10 (a CR and
LF is implicit at the end of each line!.
FIGURE 4 - FORMAT FOR PROGRAMMING GENERAL OPTIONS
ORGANIZATIONAL DATA
MCM68A30A/68B30A MOS READ ONLY MEMORY
Motorola Use Only:
Customer:
Quote: __________________________
Company
Part No.
Part No.: ________________________
Or iginator _____________________________________
Specif. No.: ____________________
Phone No. ___________________________
Ch ip Select Options:
Active
High
CSI
CS2
CS3
CS4
0
0
0
0
2-173
Active
Low
0
0
0
0
No Connect
"Don't Care"
0
0
0
0
®
MCM68A308
MCM68B308
MOTOROLA
MOS
1024 X a-BIT READ ONL Y MEMORY
The MCM6SA30S/MCM6SS30S is a mask-programmable byteorganized memory designed for use in bus-organized systems_ It is
fabricated with N-channel silicon-gate technology_ For ease of use,
the device operates from a single power supply, has compatibility
with TTL and DTL, and needs no clocks or refreshing because
of static operation.
The memory is compatible with the M6S00 Microcomputer
Family, providing read only storage in byte increments. Memory
expansion is provided through multiple Chip Select inputs. The
active level of the Chip Select inputs and the memory content
are defined by the customer.
• Organized as 1024 Bytes of S Bits
• Sta.tic Operation
• Three-State Data Output
• Mask-Programmable Chip Selects for
Simplified Memory Expansion
• Single ± 10% 5-Volt Power Supply
• TTL Compatible
• Maximum Access Time = 350 ns - MCM68A30S
250 ns - MCM68B30S
• 350 mW Typical Power Dissipation
IN-CHANNEL, SILICON-GATE)
1024 X a-BIT
READ ONLY MEMORY
e SUFFIX
FAIT·SEAL CEAAMIC PACKAGE
CASE 623-04
P SUFFIX
PLASTIC PACKAGE
CASE 709-02
PIN ASSIGNMENT
MOTOROLA'S PlN-COMPATIBLE EPROM FAMILY
32K
'IK
.. ,
,
.. C....7M
MOTOROLA'S PIN-COMPATIBLE ROM FAMILY
.J
32K
DOS
A7
Vee
A6
A8
A5
AS
A4
S3
A3
S1
A2
S4
A1
S2
AO
Q7
00
06
01
05
02
04
Vss
03
PIN NAMES
Address Inputs
AD -A9
S1
S4
00 07
Vee
INDUSTRY STANDARD PINOUTS
VSS
o
Chip Selects
Data OutPut
I
5 V Power Supply
GrOIJn(l
DS9601 16-78
2-174
MCM68A308e MCM688308
DC OPERATING CONDITIONS AND CHARACTERISTICS
.(Full operating voltage and temperature range unlp.ss otherWise noted)
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Min
Typ
Mmc
Unit
Supply Voltage
VCC
5.0
VIH
5.5
5.5
Vdc
Input High Voltage
Input Low Voltage
VIL
4.5
2.0
-0.3
O.S
Vdc
Parameter
-
Vdc
DC CHARACTERISTICS
Symbol
Min
M ••
Unit
Input Current
(V in = 0 to 5.5 VI
I,n
-
2.5
IJAdc
Output High Voltage
(lOH • -205 ~AI
VOH
2.4
-
Vdc
Output Low Voltage
VOL
-
0.4
Vdc
ILO
10
}.lArtc
ICC
130
mAde
Characteristic
(lad.. =
1.6
mAl
Output Leakage Current (Three-State)
(S = OB V or
5 = 2.0 V. VO"t = 0.4 V
to
2.4
VI
'Supplv Current
. (VCC =
5.5
V, TA = OOCI
ABSOLUTE MAXIMUM RATINGS
Rating
(See Note
11
Symbol
Value
Unit
VCC
-0.310+7.0
Vdc
-0.3
Vrtc
Supply Voltage
Input Voltage
Vin
Operating Temperature Range
TA
Storage Temperature Range
T stg
!o + 7.0
o to
-65
°c
°c
+ 70
to·,
150
NOTE 1: Permanent device damage may occur
M6800 MIC ROCOMPUTE R F AMI L V
BLOCK DIAGRAM
if ABSOLUTE MAXIMUM RATINGS .re
exceeded. Functional operation should be
r.stricted to RECOMMENDED OPERATING
CONO.ITIONS. Exposure to higher than recommended 1I0itages for e)(tended periods of time
could affect device reliability.
AO
A1
A2
A3
A4
AS
A6
A7
A8
A9
BLOCK
DIAGRAM
St'
52'
53'
S4'
•
Addr...
O.t.
Bu.
Bu.
9
I
00
ro 01
6
11
02
13 03
14 04
15 as
16 06
17 07
Address
4
3
Decode
t
23
22
20
18
21
19
Vee ", Pin 24
VSS'= Pin 12
Active level defined by the u ..'.
2-175
MCM68A308-MCM68B308
AC OPERATING CONDITIONS AND CHARACTERISTICS'
(Full operating voltage and temperature unlesc; otherwise noted.
All timing with tr = tf = 20 ns, Load of Figure 1)
MCM6BB308
MCM6BA30B
Symbol
Min
Max
Min
Max
Unit
Cycle Time
teye
350
-
250
-
ns
Access Time
tace
350
-
250
ns
Chip Select to Output Delay
tso
-
150
-
150
ns
Data Hold from Address
tDHA
10
Data Hold from Deselection
tDHD
10
Characteristic
ns
10
150
CAPACITANCE
10
ns
150
This device contains circuitry to protect
(f == 2.0 MHz, TA = 25°C. periodically sampled rather than 100% tested)
Symbol
M..
Unit
Input Capacitance
Gin
7.5
pF
Output Capacitance
C out
12.5
pF
Characteristic
the inputs against damage due to high static
voltages or electric fields; however, 'it is
advised that normal precautions be taken
to avoid application of any \/oltage higher
than
max.imum
rated
'Jo\tages
to
th,'
high·impedance circuit.
FIGURE 1 - AC TEST LOAD
5:0
v
f'L = 2.5k
T elf Po int
t----+
o--.....----.---1r----i'.........--t
Unit
,
MMD6150
Of
E Quiv
MM07000
Of E~uiv
MCM68A316A
TIMING DIAGRAM
-\
- - tCYC
_I
tace
Addres
i
.~1.0.8 V
P¢
2.0 V
O.8~ ~
2.0 V
.xXXx.;y<)<,
'SO
s .)<,
2.0 V
L
0.8 V
XX
r-- tH
XS«;XXXX
=1
~tDHA
Data Out
2.4 V
X
0.4 V
2-181
~
MCM68A316A
CUSTOM PROGRAMMING
FIGURE 2 - BINARY TO HEXADECIMAL CONVERSION
By the programming of a single photomask for the
MCM68316A, the customer may specify the content of
the memory and the method of enabling the outputs.
Binary
HexadeCimal
Character
Data
Information
on
the
general
options of the
MCM68A316A should be submitted on an Organizational
Data form such as that shown in Figure 3.
Information for custom memory content may be sent
to Motorola in one of four forms (shown in order of
preference) :
0
0
0
0
0
0
0
1
1
0
0
1
0
0
0
1
1
2
3
0
1
0
0
4
0
0
0
1
0
1
5
1
1
0
6
1
1
1
7
1
0
0
0
0
0
8
9
1
1
0
1
1
A
1
0
0
0
1. Paper tape output of the Motorola M6800 Software.
1
B
2. Hexadecimal coding using IBM Punch Cards.
1
1
1
C
1
0
0
0
1
1
D
3. EPROM (TMS2716 or M'cM2716).
1
1
1
0
E
4. Hand·punched paper tape.
1
1
1
1
F
IBM PUNCH CARDS
PAPER TAPE
Included in the software packages developed for the
M6800 Microcomputer Family is the ability to produce a
paper tape output for computerized mask generation. The
assembler directives are used to control allocation of
memory. to assign values for stored data. and for control·
ling the assembly process. The paper tape must specify the
The hexadecimal equivalent (from Figure 2) may be
placed on 80 column IBM punch cards as follows:,
Step
Column
1
12
Byte "0·· Hexadecimal equivalent for
outputs 07 thru 04 (07 ~ M.S.B.)
2
13
3
14 - 75
Byte "0" Hexadecimal equivalent for
outputs 03 thru 00 (03 ~ M.S.B.)
Alternate steps 1 and 2 for consecutive
bytes.
4
77-80·
full 2048 bytes.
Card number (starting 0001)
Total number of cards (64)
FIGURE J - FORMAT FOR PROGRAMMING GENERAL OPTIONS
ORGANIZATIONAL DATA
MCM68AJ16A MOS READ ONLY MEMORY
Customer:
Motorola Use Only:
Company
Quote
Part No.
Part No .. _ _ _ _ _ _ _ _ _ _ _ __
Originator
Speci!. No ..
Phone No
Chip Select:
*Oon't Care
Active High
51
S2
S3
Active Low
(No Connect)
D
D
D
D
o
o
o
o
-A don't care must always bP. the
2-182
D
hl~lhest
order Chip Select(sl.
®
MCM68A316E
MOTOROLA
MOS
2048 X 8 BIT READ ONLY MEMORY
IN~HANNEL.SILICON-GATEI
The MCM68A316E is a r1Iask-programmable byte-organized
memory designed for use in bus-organizKt systems. It is fabricated
with N-channel silicon-gate technology. For ease of use. the device
operates from a single power supply. has compatibility with TTL and
o TL. and needs no clocks or refeshing because of static operation.
The memory is compatible with the M6800 Microcomputer
Family. providing read only storage in byte increments. Memory
expansion is provided through multipl, Chip Select inputs.. The
active level of the Chip Select inputs and the memory content
are defined by the user.
•
Fully Static Operation
•
Three-State Data Output
•
Mask-Programmable Chip Selects for
Simplified Memory Expansion
•
Single ± 10% 5·Volt Power Supply
•
TTL Compatible
•
Maximum Access Time
•
Plug-in Compatible with 2316E
•
Pin Compatible with 2708 and TMS27.6 EPROMs
2048 X 8 BIT
READ ONLY MEMORY
C SUFFIX
FRIT -SEAL CERAMIC PACKAGE
CASE~
= 350 ns
P SUFFIX
PLASTIC PACKAGE
CASE 7\)9.{)2
PIN ASSIGNMENT
MOTOROLA'S PlN-COIIPAnBLI IfIIIOII FAMILY
all
-..
all
-
MOTOROLA'S PlN-COMPAnBLr ROM FAMILY
11K
PIN NAMES
AO-A10.
INDUSTRY STANDARD IIiINours
.. Addrenlnpuft
51-53
· Chip Selects
00-07
· Date Output
VCC
· + 5 V Power Supply
Vss
. Ground
DS9IiOO/&-78
2-183
MCM68A316E
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted)
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
VCC
4.5
5.0
5.5
Vdc
Input High Voltage
VIH
2.0
5.5
Vdc
Input Low Voltage
VIL
-0.3
-
0.8
Vdc
DC CHARACTERISTICS
Symbol
Min
Max
Unit
Input Current
(Vin = 0 to 5.5 VI
lin
-
2.5
/JAde
Output High Voltage
VOH
2.4
-
Vdc
VOL
-
0.4
Vdc
ILO
-
10
,uAdc
ICC
-
130
mAde
Characteristic
(lOH = -205 ,.AI
Output Low Voltage
(IOL = 1.6mAI
-Output Leakage CUOCo'lt ,I hree-State)
5 = 2.0 v, V out = 0.4
(S = 0.8 V or
V to 2.4 VI
Supply Current
(VCC = 5.5 V, TA = OOCI
ABSOLUTE MAXIMUM RATINGS (See Note 11
Rating
Symbol
Value
Unit
VCC
-0.3 to +7.0
Vdc
Input Voltage
Vin
-0.3 to +7.0
Vdc
Operating Temperature Range
Storage Temperature Range
TA
o to +70
T stg
-65 to +150
°c
°c
Supply Voltage
NOTE1: Permanent device damage may occur If ABSOLUTE MAX IMUM RATINGS are
exceeded. Functional
operation
should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages
for extended periods of time could affect device reliability.
,,======,------------,
CAPACITANCE
(f:: 2.0 MHz, TA = 25°C, periodically sampled rather than 100% tested)
I
J
Characteristic
t Input Capacitance
I Output Capacitance
I
I
Symbol
Max
Unit
Cin
C out
7.5
pF
12.5
pF
M6800 MICROCOMPUTER FAMILY
BLOCK DIAGRAM
Addr ... Data
Bu.
Bu.
BLOCK
DIAGRAM
AO
Al
A2
"3
A.
A5
A6
A'
A8
A9
Ala
8
7
9
10
11
13
6
4
3
2
00
01
02
03
,. o.
Address
Decode
15 05
16 06
17 07
23
22
19
51'
52'
53'
Vee
Gnd
Active level defined by the us.r.
2-184
Pin 24
Pin 12
MCM68A316E
FIGURE l-AC TEST LOAD
SO V
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature unless otherwise noted.
All timing with tr :: tf 20 ns, Load of Figure 1)
::0
T est Po In t o---+---<~-I"--+
,
130 pF'
11.7 k
~,
M M 0 6 1 50
or EQuiv
MMD1000
or E qUI ...
Characteristic
Max
-
Unit
-
350
ns
150
ns
10
-
ns
10
150
ns
Symbol
Min
Cycle Time
tcye
350
Access Time
tace
Chip Select to Output Delay
ISO
Data Hold from Address
'DHA
IH
Data Hold from Deselection
ns
"Includes JIg CapacItance
TIMING DIAGRAM
This device contains circuitry to
protect the inputs against damage
'cvc--
due to high static voltages or electric fields; however, it is advised
that normal precautions be taken
to avoid
------------1I
- - . - - - - - - - - lace - - - -.. - -
,It------
Address
application of any vol-
tage higher than maximum rated
voltages to this high-impedance
circuit.
- - ISO
2-185
-.------<~
MCM68A316E
CUSTOM PROGRAMMING
FIGURE
By the programming of a single photomask for the
MCM68A316E, the customer may specify the content of
the memory and the method of enabling the outputs.
a - BINARY TO HEXADECIMAL CONVERSION
Binary,
Hexadecimal
'(;haracter
Oa'i
0
0
0
0
Information
on the general
options of the
MCM68A316E should be submitted on an Organizational
Data form such as that shown in Figure 3. ("No·Connect"
must always be the highest order Chip Select(s).)
0
0
1
,
1
0
1
1
1
0
2
0
1
1
J
1
0
0
,
,
,
,
4
0
,
0
6
0
0
0
0
0
0
,
,
,
,
,
1
1. Paper tape output of the Motorola M6800 Software.
2. Hexadecimal coding using IBM Punch Cards.
3. EPROM (T~S2716 or MCM2716).
0
0
1
0
0
Information for custom memory content may be sent
to Motorola in one of three forms (shown in order of
preference) :
0
0
0
,
0
5
1
1
,
8
9
A
8
0
0
1
1
,
0
0
0
,
c
,
,
0
,
E
F
1
,
0
IBM PUNCH CARDS
PAPER TAPE
Included in the software packages developed for the
M6800 Microcomputer Family is the ability to produce a
paper tape output for computerized mask generation. The
assembler directives are used to control allocation of
memory, to assign values for stored data, and for control·
ling the assembly process. The paper tape must specify the
full 2048 bytes.
The he.a~ecimal equivalent (from Figure 21 may be
placed on
column· IBM punch cards as follows:
eo
Step
Column
1
12
2
13
3
14-75
4
77-~
Byte "0" Hexadecimal equivalent for
outputs 07 thru 04 (07 = M.S.B.I
Byte "0" Hexadecimal equivalent for
outputs 03 thru 00 (03 = M.S.B.)
Alternate steps 1 and 2 for consecutive
bytes.
Card number (starting 00011
Total number of cards (64)
FIGURE 3 - FORMAT FOR PROGRAMMING GENERAL OPTIONS
ORGANIZATIONAL DATA
MCM68A316E MOS READ ONL Y MEMORY
Customer:
Motorola Use Only:
Company -------------------------------------
Ouote: _________________________
Part No.
Part "10.: ______________________
Originator ________________________
Phone No. ________________
Chip Select:
SI
S2
S3
Specif. No.:
Active
High
Active
Low
No
Connect
0
0
0
0
0
0
D
0
2-186
D
®
MCM68A332
MOTOROLA
MOS
4096 X a-BIT READ ONL Y MEMORY
The
MCM68A332
is
a
mask-programmable
byte-organized
INCHANNEL,SILICON-GATEI
memory designed for use in bus-organized systems. It is fabricated
with N-channel silicon-gate technology_ For ease of use, the device
operates from a single power supply, has compatibility with TTL and
DTL, and needs no clocks or refreshing because of static operation_
The memory
IS
4096 X a-BIT
READ ONL YMEMORY
compatible with the M6800 Microcomputer
Family, providing read only storage in byte increments. Memory
expansion
IS
provided through multiple Chip Select inputs_ The
C SUFFIX
FAIT-SEAL CEAAMIC PACKAGE
CASE 623-04
active level of the Chip Select Inputs and the memory content
are defined by the user.
•
Fully Static Operation
•
Three-State Data Output for OR-Ties
•
Mask-Prog,ammable Chip Selects for Simplified Memory
Expansion
•
Single ± 10% 5-Volt Power Supply
•
Fully TTL Compatible
•
MaXimum Access Time
•
Directly Compatible with 4732
= 350
ns
•
Pin Compatible with 2708 and 2716 EPROMs
•
Preprogrammed MCM68A332-2 Available
P SUFFIX
PLASTIC PACKAGE
CASE 709-02
-
PIN ASSIGNMENT
MOTOROLA'S PIN-COMPATIBLE EPROM FAMILY
..r
Vee
AS
A9
21
52
S1
A10
MOTOROLA'S PIN-COMPATIBLE ROM FAMILY
32K
18
All
17
Q7
16
as
15
Q5
14
04
13
03
PIN NAMES
.,
. . Address Inputs
AQ··A"
MCMN"332
S .
. Programmable
Chip Selects
aO-07
Vee.
INDUSTRY STANDARD PINOUTS
Vss
. Data OutPut
.. + 5 V Power SupplV
. Ground
OS961917-78
2-187
MCM68A332
AO
A1
A2
A3
A4
AS
A6
A7
AS
A9
Al0
A11
BLOCK
DIAGRAM
9
10
11
13
7
6
5
•
,.
Address
2
1
23
22
51·
52·
d3
04
15 05
16 06
17 07
Decode
3
00
01
02
20
21
Vee = Pin 24
VSS'" Pin 12
Active 18'1181 defined bV the u .. er.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operallng voltage and temperature range unless otherWise noted)
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Symbol
Min
TVp
Max
Unit
Vee
4.5
5.0
5.5
Vdc
Input High Voltage
VIH
2.0
-
55
Vdc
Input Low VOltage
VIL
-0.3
0.8
Vdc
Supply Voltage (\ICC must he
applied
at least 100
IJS belore ploper deVIL! operailorll~
achIeved)
DC CHARACTERISTICS
Symbol
Min
Max
Unit
Input Current
(V ,n -" 0 to 5.5 V!
1m
-
25
/JAde
Output High Voltage
VOH
2.4
VOL
-
0.4
Vdc
-
10
/-lAde
-
80
mAde
Characteristic
(IOH
c
Output Low Voltage
"0L
1.6 mAl
Outnut Leakage Current (Three-Slattd
(S
0.8 v Qr' S ~ 2.0 V, v ou t : Q4Vto2.4Vi
ILO
Supr1y Current
lee
IVee
Vdc
-205 "AI
1
5.5 v. TA - oOel
ABSOLUTE MAXIMUM RATINGS (S.e Note 11
Symbol
Value
Unit
Vee
-0.3 to +7.0
Vdr.
Innut Voltage
V,n
-0.3 to + 7.0
Vdc
OperJtrnq Temperature RtatlC voltages or electric flelns; however, It IS advised
that normal precautions he taken
to aVOId applIcation of any voltage higher than maximum rated
voltages to thiS high-Impedance
CirCUIt.
De
°e
NOTE 1 Permanent device cJamaqe may occur If ABSOLUTE MAXIMUM RATINGS are
exceeded.
Functional
operation
should
be
restrlcteu to RI;COrylMENDED
OPERATING CONDITIONS. Exposure to hllJher than recommended voltages
for eXTended periods of tIme could affect device reliab,lity.
CAPACITANCE
(f =
1.0 MHz, TA = 25°C. periodically sampled rather than 100% tested)
Characteristic
Symbol
Input Capacitance
Output Capacitance
Cout
M6800 MICROCOMPUTER EAMILY
-BLOCK DIAGRAM
2-188
Addrass
Data
Bus
Bus
MCM68A332
FIGURE 1 - AC TEST LOAD
5.0 V
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operat!ng voltage and tempel."Jture unless otherWise noted.
All timlnq with tr :: tf
Test Point o-.....---1~---+~.-. MMD6150
or equivalent
r
, 1.7 k
130 pF·
.. MMD7000
.. or equivalent
t-
= 20
ns, Load of Figure 1l
Svmbol
Min
teye
350
Ma.
--
Unit
Cycle Time
Access Time
tace
-
350
ns
Chip Select to Output Delay
'50
150
ns
Characteristic
Data Hold from Address
Data Hold from Deselect_on
'DHA
10
'H
10
ns
ns
150
ns
-Includes jig capacitance
TIMING DIAGRAM
__---------tcvc_--------~
~~2.0V=======:::j=~~
~--------tacc------~·~I
Address, A
~
Chip Select, S
2.0 V
Ch;p Select,S
0.8 V
'50------1
Output,
a -----~----------~(~5L.~~t------J)~-----Waveform
Waveform
Waveform
Symbol
0.4 V
Input
Output
MUST BE
WILL BE
VALID
VALID
Symbol
Input
~ ~~yN~TH~~EE
PERMITTED
2-189
Output
CHANGING.
STATE
UNKNOWN
Svmbol
~
Input
Output
HIGH
IMPEDANCE
MCM68A332
MCM68A332 CUSTOM PROGRAMMING
FIGURE 2 - BINARY TO HEXADECIMAL CONVERSION
By the pl"ogrammlng of a single photomask. for the
MCM68A332, the customer may specify the content of the
memory and the method of enabling the outputs.
Information on the general oPtions of the MCM68A332
0
0
0
0
0
0
0
0
1
should be submitted on an Organizational Data form such as that
shown in Figure 3. (A "No-Connect" or "Don't Care" must always
be the highe~t order Chip Select!s)')
..
Information for custom memory content may be sent to
MOlorola in one 01 four forms Ishown in order of preference):
1. IBM Punch Cards:
1
1
1
1
1
1
A. Hexadecimal Format
B. Intel F armat
C. Binary Negstive-Postive Format
2. EPROMs-two 16K (MCM2716 or TMS27161 or four
BK IMCM27081
3. Paper tape output of the Motorola M6800 software
4. Hand punched paper tape
The hexadecimal equivalent Ifrom Figure 21 may be placed on
80 column IBM. punch cards as foilows:
12
Bytl! "0" Hexadecimal equivalent for outputs
07 through 04 107 • M.S.B.I
2
13
Byte
"a ..
Hexadecimal equivalent for outputs
03 through 00 (03 • M.S.B.I
4
5
14-75
77-79
0
1
0
t
1
0
t
1
2
3
1
1
1
1
0
0
0
4
1
1
1
0
5
6
0
0
0
0
0
0
0
1
0
t
t
1
0
0
0
1
0
t
t
7
B
9
A
B
C
0
E
F
1
1
The -2 standard ROM pattern contains sine-lookup and arctanlookup tables.
Locations 0000 through 2001 contain the sine: valu8$. The
sine's first quadrant is divided into 1000 parts with sine values
corresponding to these angles stored in the ROM. Sin 1112 is
included and is rounded to 0.9999.
The arctan values contain angles in radians corresponding to
the arc tangents of 0 through 1 in steps of 0.001 and are contained
in locations 2048 through 4049.
Locations 2002 through 2047 and 4050 through 4095 are
zero filled.
All values are represented in absolute decimal format with four
digit precision. They are stored in BCD format with the two most
significant digits in the lower byte and the two least significant
digits in the upper byte. The decimal point is assumed to be to
the left of the most significant digit.
IBM PUNCH CARDS, HEXADECIMAL FORMAT
Column
0
0
PRE·PROGRAMMED MCM68A332P2, MCM68A332C2
Included in the software packages developed for the M6800
Microcomputer Family is the ability to produce a paper tape
output for computerized mask generation. The assembler directives are used to control.allocation of memory. to assign values for
stored data. and for controlling the assembly process. The paper
tape must specify the full 4096 bytes.
1
0
0
0
0
1
1
1
1
1
PAPER TAPE
Stop
Hexadecimal
Character
Binary Data
Alternate steps 1 and 2 for consecutive bytes.
Card number Istarting 001).
Total number of cards must equal 128.
ExamplP.: Sin 110~0
~I
• 0.0016 decimal
Address _ _ _ _ _ _..:C;;:o.:.:nt:::e:::n;;:ts:0002
0003
0000
0001
0000
0110
FIGURE 3 - FORMAT FOR PROGRAMMING GENERAL OPTIONS
ORGANIZATIONAL DATA
MCM68A332 MOS READ ONLY MEMORY
Customer:
Motorola Use Only
Company _________________________________
Ouote ____________________________
Part No. ________________________________
Part No. ___________________________
Origimitor _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Phone No. __________________________
Chip Select Options:
Sl
S2
Specif. No.
Active High
Active Low
o
o
o
o
2-190
No·Connect
o
o
®
MCM68A364
MCM68B364
MOTOROLA
MOS
8192 X 8-BIT READ ONLY MEMORY
The MCM68A364/MCM68B364 is a mask-p(ogrammable byteorganized memory designed for use in bus-organized systems. It is
. fabricated with N-channel silicon-gate technology. For ease of use,
the device operates from a single power supply, and has
compatibility with TTl. The addresses are latched with the Chip Enable
input - no external latches reQuired.
The memory is compatible with the M6800 Microcomputer
Family. providing read only storage in byte increments. The Chip
Enable input deselects the output and puts the chip in a power-llown
mode.
• Automatic Power Down
• Low Power Dissipation -
(N-CHANNEL. SILICON-GATE)
8192 X 8-BIT
READ ONLY MEMORY
L SUFFIX
CERAMIC PACKAGE
CASE 716-06
150 mW active (typical)
35 mW standby (typical)
• Single ±10% 5-Volt Power Supply
• High Output Drive Capability (2 TIL Loads)
• Three-State Data Output for OR-Ties
• TIL Compatible
• Maximum Access Time -
P SUFFIX
PLASTIC PACKAGE
CASE 709-02
250 ns - MCM68B364
350 ns - MCM68A364
• Pin Compatible with 8K - MCM68A308. 16K - MCM68A316E.
and 32K - MCM68A332 Mask-Programmable ROMs
• Pin Compatible with 24-pin 64K EPROM MCM68764
MOTOROLA'S PINoCOMPATIILE EPROM FAMILY
12K
PIN ASSIGNMENT
Vee
A7
A6
AS
A5
A9
A4
A12
A3
A2
AlO
A1
All
AO
07
00
Q6
01
05
02
Q4
VSS
03
MOTOROLA'S PINoCOMPATIILE ROM FAMILY
PIN NAMES
12K
AD
A12
E
aD 07
Address
Chip Enable
Data Output
Vee·
+ 5 V Power Supply
vss
Ground
This device contair.s Circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however,
It IS advised that normal precautions be
taken to avoid application of any voltage
higher than maximum rated voltages to
INDUSTRY STANDARD PINOUTS
this high-impedance circuit.
0598)617-79
2-191
MCM68A364-MCM688364
BLOCK
DIAGRAM
AO
Al
A2
A3
A4
AS
A6
A7
A8
A9
Al0
All
A12
8
6
5
4
9 DO
10 01
02
13 03
14 04
15 05
16 06
17 07
11
Address
Decode
1
23
22
19
18
21
E 20
Vee
= Pin
24
VSS '-' Pin 12
ABSOLUTE MAXIMUM RATINGS (See note)
Rating
Symbol
Value
Unit
VCC
-0.5 to +7.0
Vdc
Yin
-0.5 to + 7.0
Vdc
Supply Voltage
Input Voltage
Operating Temperature Range
TA
T stg .
Storage Temperature Range
o to
+ 70
-65 to + 150
'c
'c
NOTE: Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended vollages lor extended penods of time could
affect device reliability
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operatmg voltage and temperature range unless otherwise noted.)
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Symbol
Min
Nom
Max
Unit
Vce
4.5
5.0
5:5
Vdc
(Vee must be applied at least lOOps before proper device
operation is achieved)
Input High Voltage
V,H
20
_.
55
Vdc
Input Low Voltage
V,L
-0.5
-
08
Vdc
SymbQI
Min
Typ
Max
Unit
iin
-10
-
10
/JAdc
Output High Voltage IIOH ~ -220 /JAI
VOH
2.4
-
-
Output Low Voltage IIOL ~ 32mAI
VOL
-
-
0.4
Vdc
Output Leakage Current (Three-State)
IE = 2.0 V. Vout = 0 V to 55 VI
ILO
-
10
/JAdc
Supply Current - Active(MinImum Cycle Rate)
ICC
-
25
40
mAdc
Supply Current IE =V,HI
IS8
-
7
10
mAde
RECOMMENDED OPERATING CHARACTERISTICS
Characteristic
Input Current IV,n ' 0 to 55 VI
Standby
-Current is proportIonal to cycle rate
CA~ACITANCE (f~ 1.0 MHz, TA ~ 25'C, periodically sampled rather than 100% teSled)
Characteristic
Input CapacItance
Output Capacitance
2-192
-10
Vdc
MCM68A364·MCM68B364
AC OPERATING CONDITIONS AND CHARACTERISTICS
Read Cycle
RECOMMENDED OPERATING CONDITIONS
(TA = 0 10 70"C Vee = 5 0 V '10% All liming wllh I, = If = 20 ns load'of Flgu,e 1)
MCM688364
MCM68A364
Symbol
Min
Ma.
Min
Ma.
Unit
Chip Enable Low to Chip Enable Low of Next Cycle (Cycle Time)
IELEL
375
_.
450
--
ns
Chip Enable Low to Chip Enable High
IELEH
250
_.
300
_.
ns
Chip Enable Low to Output Valid (Access)
IELOV
-
250
-
300
ns
Chip Enable High to Oulpul High Z (Off Time)
IEHOZ
-
60
-
75
r,')
Chip Enable Low 10 Address Don'l Care (Hold)
IELAX
60
-
75
-
ns
Parameter
Address Valid to Chip Enable Low (Address Setup)
IAVEL
0
-
0
-
ns
Chip Enable Precharge Time
IEHEL
125
-
150
-
ns
TIMING DIAGRAM
IELEL
CHIP ENABLE. ~
VIHVILIELEH
ADDRESS. A
IELQV
VOHDATA OUTPUT. Q
1
VALID
High Z
VOL-
High Z
FIGURE 1 - AC TEST LOAD
WAVEFORMS
Waveform
RL
= 12
'OO'' p
or Equiv
10.9 k
1
Output
MUST BE
WILL BE
VALID
VALID
~
CHANGE
f-ROM H TO L
WilL CHAr~C.E
FHOM H TO l
.PlZZ7
CHANGE
WILL CHANGE
FF-lQMLTOH
I'AOMLTQH
L>ON"T eMU
ANY CHANGE
CHANGING
PEHMITTED
UNKNOWN
k
T esl POlnl O--"'!~""'--f4f---+ MMD6150
1
Input
Svmbol
5.0 V
MMD7000
or EQuiv
~
=r-
-'ncludes Jig Capacitance
2-193
STATE
HIGH
IMPEDANCE
MCM68A364-MCM688364
CUSTOM PROGRAMMING
TIMING PARAMETER ABBREVIATIONS
x XXX
"'",' ",m"
M"'" " """W ~
transition direction for first signal
'0. .",," ;
By the programming of a Single photomask for the
MCM68A364/MCM68B364, the customer may specify the
contents of the memory.
Information for custom memory content may be sent to
Motorola in one of two forms (shown in order of preference):
1. Magnetic Tape - 9 TraCk, 800 bpi, odd parity written
in EBCDIC character code. Motorola's R.O.M.S. format.
2. EPROMs
one 64K (MCM68764), two 32K
(MCM2532), four 16K IMCM2716 or TMS2716), or
eight 8K IMCM27081.
3. IBM Punch Cards
A. Hexadecimal Format
B. INTEL Hexadecimal Format
III
signal name to which interval is defined
transition direction for second signal
The transition definitions used in this data sheet are:
H = transition to high
L = transition to low
V = transition to valid
X = transition to invalid or don't care
Z = transition to off (high impedance)
IBM PUNCH CARDS. HEXADECIMAL
FORMAT
TIMING LIMITS
The table of timing values shows either a minimum or
a maximum limit for each parameter. Input requirements
~
are specified from the external system point of view.
Thus, address setup time is shown as a minimum since the
system must supply at least that much time leven though
most devices do not require it). On the other hand,
responses from the memory are specified from the device
point of view. Thus, the access time is shown as a maximum since the device never provides data later than
that time.
1
2
3
4
5
The hexadecimal equivalent Ifrom Figure 2) may be
placed on 80 column IBM punch cards as follows:
Column
12
Byte "0" Hexadecimal equivalent for outputs 07 through 04 (07= M.S.B.I
13
Byte "0" Hexadecimal equivalent for outputs 03 through 00 (03= M.S.B.I
14-75 Alternate steps 1 and 2 for consecutive
bytes
77-79 Card number (starting 001)
Total number of cards must equal 256
FIGURE 2 - BINARY TO HEXADECIMAL CONVERSION
B,narv
Hexadecimal
Character
Data
0
0
0
0
0
0
0
1
1
0
0
1
0
2
0
0
0
0
1
1
1
0
0
0
J
4
1
1
5
0
1
1
0
6
0
1
1
1
7
1
0
0
0
8
1
0
0
1
9
1
0
1
0
A
1
0
1
1
B
C
1
0
1
0
0
1
1
0
1
0
1
1
1
0
1
1
1
1
E
F
2-194
MCM68A364e MCM68B364
M6800 MICROCOMPUTER FAMILY
BLOCK DIAGRAM
READ ONLY MEMORY
BLOCK DIAGRAM
MCM68A364
MCM686364
. .- .....I - - - - i
Read Only
Memory
Memory
Matrix
(8192 X 8)
Interface
Adapte,
Interface
Adapter
Add,..,
Data
BUI
Bus
Memory Addr •••
and Control
PRE-PROGRAMMED MCM68A364P3/l3
The -3 standard ROM pattern contains log (base 10)
and antilog (base 10) lookup tables for the 64K ROM.
locations 0000 through 3599 contain log base 10
values. The arguments for the log table range from 1.00
through 9.99 incrementing in steps of 1/100. Each log
value. IS
b.ented hy ,In eight-digit decimal number
with decimal P' '11: assumed to be to the left of the mostsigniiicant digit.
A~!ilog (base 10) are stored in locations 4096 through
80'15. Th~' ,uments range from .000 through .999
i!,crementing ,n steps of 1/1000. Each antilog value is
represented by an eight-digit decimal number with
decimal point assumed to be to the right of the mostsignificant digit.
locations 3600 through 4095 and 8096 through
8191 are zero filled.
"'1"
All values are represented in absolute decimal format
with eight digit precision. They are stored in BCD format
with the two most significant digits in the lower byte and
the remaining six digits in the three consecutive
locations.
Example:
log10 (1.01) = .00432137 decimal
Address
4
5
6
7
Contents
0000
0100
0010
0011
2-195
0000
0011
0001
0111
®
MOTOROL.A
MeM68365
Advance InforInation
MOl
8192 ~ 8-BIT READ ONLY MEMORY
IN·CHANNEL, SILICON-GATEI
The MCM68365 IS a mask-programmable byte-organized memory
designed for use in bus-organized systems. It is fabricated With
N-channel silicon-gate technology. For ease of use, the device operates
from a single power supply, has compatibility with TTL, and needs no
clocks or refreshing because of static operation.
The memory is compatible with the M6800 Microcomputer Family,
providing read only storage in byte increments. The active level of the
Chip Enable input and the memory content is defined by the user. The
Chip Enable input deselects the output and puts the chip in a powerdown mode.
8192x8-BIT
READ ONLY MEMORY
• Fully Static Operation
• Automatic Power Down
• Low Power Dissipation - 225 mW Active !Typical)
30 mW Standby ITypical)
•
•
•
•
Single ± 10% 5-Volt Power Supply
High Output Drive Capability 12 TTL Loadsl
Three-State Data Output for OR-Ties
Mask Programmable Chip Enable
• TTL Compatible
• Maximum Access Time - 250 ns - MCM68365-25
350 ns - MCM68365-35
e SUFFIX
P SUFFIX
FRIT-SEAL
CERAMIC PACKAGE
CASE 623
PLASTIC PACKAGE
CASE 709
PIN ASSIGNMENT
• Pin Compatible with 8K - MCM68A308, 16K - MCM68A316E,
and 32K - MCM68A332 Mask-Programmable ROMs
Vee
AS
A9
AI2
MOTOROLA'S PIN·COMPATIBLE EPROM FAMILY
E
UK
AIO
All
Q7
06
05
04
03
MOTOROLA'S PIN-COMPATIBLE ROM FAMILY
'""
UK
PIN NAMES
AO-A I 2 ..... Address
E ..... Chip Enable
00-Q7 ..... Data Output
Vee ..... + 5 V Power Supply
Vss ...... Ground
This device contains Circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, It is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this high im-
INDUSTRY STANDARD PINOUTS
pedance circuit
ADI844/9-80
2-196
MCM68365
BLOCK DIAGRAM
AO
Al
A2
A3
AO
AS
A6
A7
AS
A9
Al0
All
A12
'T
----..
--.... '0
__- . 1 6
DO
01
D2
03
DO
05
06
__ -.17
07
9
6
11
s-
3 Stale
Address
Outf'"/ut
Decode
Buffers
2 --
---.13
-----.'4
-----..15
23
22
19
18 --
21
20
Vcc=Pm 24
VSS = P,n 12
• Active level defined bv the user
ABSOLUTE MAXIMUM RATINGS ISee Notel
Rating
Value
Vce
V,n
-0_3 to + 7_0
V
03 to + 7
V
TA
to + 70
-65 to + 150
Input Voltage
Operating Temperature Range
Storage Temperature Range
Note:
Unit
Symbol
Supply Voltage
°
T stg
°
'c
'c
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
RECOMMENDED OPERATING CONDITIONS Exposure to higher than recommended voltages for extended pertods of time could affect device reliability
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted)
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
(Vee must be applied at least 100 pS before proper deVice operation IS achieved)
Input High Voltage
nput Low Voltage
RECOMMENDED OPERATING CHARACTERISTICS
Characteristic
Symbol
Min
Nom
Max
Unit
VCC
45
5_0
5_5
V
VIH
VIL
2_0
0_3
5_5
0_8
V
Symbol
Min
Typ
Max
Unit
lin
-
-
10
pA
Output High Voltage IIOH - - 205 pAl
VOH
2.4
-
V
Output Low Voltage IIOL - 3_2 mAl
VOL
0.4
V
ILO
pA
45
10
80
mA
6.0
15
mA
Input Current (V ln - 0 to 5.5 Vl
a"tput Leakage Current IThree-Statei It~ 2
°
V, Vout - 0.4 V to 2.4 VI
Supply Current
Active IVCC'-55 V, TA-O'CI
ICC
Supply Current -
Standby IVCC - 5_5 V, T A - O'C, E - VIHi
IS8
CAPACITANCE
If ='.0 MHz, T A
= 25°C,
periodically sampled rather than 100% tested)
Characteristic
Input Capacitance
utput Capacitance
2-197
-
MCM68366
AC OPERATING CONDITIONS AND CHARACTERISTICS
Read Cycle
RECOMMENDED OPERATING CONDITIONS
IT A =0 to 70·C, V CC =5.0 V ± 10%. All timing with tr =tf = 10 ns, load of Figure 11
p.,.-
Symbol
Address Valid to Address Don't Care ICycle Time when Chip Enable is held Active)
Chip Enable Low to Chip Enable High
Address Valid to Output Valid IAccessl
Chip Enable Low to Output Valid IAccessl
Address Valid to Output Invalid
: Chip Enable Low to Output Invalid
Chip Enable High to Output High-Z
, (;hlp Selection to Power Up Time
. Chip Deselection to Power Down Time
Address Valid to Chip Enable Low IAddress Setup I
READ CYCLE TIMING 1
IE Held Low)
~ tAVQ~~-
MCM8II366-25
Min
MIx
tAVAX
250
tELEH
tAVQV
tELQV
tAVQX
tELQX
tEHQZ
tpu
tpD
250
-
350
350
-
-
250
-
100
tAVEL
0
-
10
10
0
0
0
350
250
10
10
0
0
-
70
-
------
Q IData
__
350
80
120
-
l-----~:~
__----------------tAVAX
Address
MCM8II366-36
Min
MIx
-il~-l1
Outl_-_-_-_-_-_-_-_-!::P:-r~e~v-:'i~o-~U-s~JD~a;ta~V;a~h~·-:'d~~~~~l~~~~~~~t:~~~~~~~~~~~~~~~D~a-t;aCv;a~li~d--------~-_-_-_-___-VOH
VOL
READ CYCLE TIMING 2
Address
~
_tAVEL
Address Valid
-I
tELEH
tELQV
-tELQX
Q IData
VCC
Supply
Current
~~
-
tEHQZr-
Outl-------:--HI-Z~
........'"""'.,..........!'-----....;;.D.;...at'-a-V-a-lld-----j>-HI-Z.
:~:
_____~ _~"- t=_________----l
___
VOH
VOL
t_PD_t
TIMING PARAMETER ABBREVIATIONS
t X X X X
"'~' ~.
''Om .m,,,, '0_' ...'o"'..J
transition direction lor lirst signa)
III
signal name to which interval is delined
transition direction for second Signal
The transition definitions used in this data sheet are:
H = transition to high
L = tranSition to low
V = transition to valid
X = transition to invalid or don't care
Z = transition to off Ihigh impedance)
TIMING LIMITS
The table of timing values shows either a minimum or a
maximum limit for each parameter. Input requirements are
specified from the external system point of view. Thus, address setup time is shown as a minimum since the system
must supply at least that much time leven though most
devices do not require itl. On the other hand, responses from
the memory are specified from the device pOint of view.
Thus, the access time is shown as a maximum since the
device never provides data later than that time.
2-198
MCM68366
READ ONLY MEMORY BLOCK DIAGRAM
MCM68365
Read Onlv
Memorv
Memory
Matrix
t8192x81
Data Bus
,
,,.'
Memory Address
and Control
Address Data
Bus
Bus
PRE-PROGRAMMED MCM68366f'3S-3/C3S-3,
MCM68366P2S-3/C26-3
The - 3 standard ROM pattern contains log tbase 101 and
antilog (base 10) lookup tables for the 64K ROM.
. Locations 0000 through 3599 contain log base 10 values.
The arguments for the log table range from 1.00 through
9.99 incrementing in steps of 1/100. Each log value is
representer1 by an eight-digit decimal number with decimal
paint assumed to be to the left of the most-significant digit.
Antilog (base 101 are stored in locations 4096 through
8)95. The arguments range from .000 through .999 incrementing in steps of 1/1000. Each antilog value is
represented by an eight-digit decimal number with decimal
point assumed to be to the right of the most-significant digit.
Locations 3600 through 4095 and 8196 through B191 are
zero filled.
All values are represented in absolute decimal format with
eight digit precision. TheV are stored in BCD format with the
two most significant digits in the lower byte and the remaining six digits in the three consecutive locations .
Example: 10910(1.011 = 0.00432137 decimal
Address
4
5
6
7
2-199
Contents
0000
0000
0011
0100
0010
0001
0011
0111
MCM68365
CUSTOM PROGRAMMING
Information for custom memory content may be sent to
Motorola in one of two forms (shown in order of preference):
By the programming of a single photomask for the
MCM68365, the customer may specify the content of the
memory and the method of enabling the outputs.
Information on the general options of the MCM68365
should be submitted on an Organizational Data form such as
that shown in Figure 2.
1. Magnetic Tape
9 track, BOO bpi, odd parity written in EBCDIC character code. Motorola R.O.M.S. format.
2. EPROMs - four 16K (MCM2716, or TMS2716, or eight
8K (MCM27081, one 64K or two 32Kl
FIGURE 2 - FORMAT FOR PROGRAMMING GENERAL OPTIONS
ORGANIZATIONAL DATA
MCM68385 MOS READ ONLY MEMORY
Customer:
Company ____________________________________
Part No. ____________________________________
Motorola Use Only:
Quote: _____________________
Part No: _____________________
Originator ___________________________________
Speci!. No: __________________
Phone No. __________
Enable Options:
Active High Active Low
Chip Enable
D
2-200
0
®
MOTOROLA
MCM68366
Advance InforIllation
MOS
8192 x 8-BIT READ ONLY MEMORY
IN-CHANNEL, SILICON-GATE)
The MCM68366 is a mask-programmable byte-organized memory
designed for use in bus-organized systems It IS fabricated with
N-channel silicon-gate technology. For ease of use, the device operates
from a single power supply, has compatibility with TTL and DTL. and
needs no clocks or refreshing because of static operation
The memory is compatible with the M6800 Microcomputer Family,
providing read only storage In byte Increments. The active level of the
Output Enable input and the memory content IS defined by the user
The Output Enable Input deselects the output.
• Fully Static Operation
• Fast Data Valid Time for High Speed Microprocessors
8192x 8-BIT
READ ONLY MEMORY
~~)
.
2~tnUL~.
,
• Low Power Dissipation - 225 mW Active ITYPlca11
" P SUFFIX
C SUFFIX
• Single ± 10% 5-Volt Power Supply
• High Output Drive Capability 12 TTL Loads)
FRIT·SEAL
CERAMIC PACKAGE
CASE 623
• Three-State Data Output for DR-Ties
t·
IL D
24
PLASTIC PACKAGE
CASE 700
• Mask Programmable Output Enable
• TTL Compatible
• Maximum Access Time -
\20 ns from Output Enable
250 ns from Address - MCM68366-25
350 ns from Address - MCM68368-35
• Pin Compatible with 8K and 32K -
MaSk-Programmable ROMs
• Pin Compatible with MCM68766 64K EPROM
PIN ASSIGNMENT
A7[~~VCC
A6[ 2
22
A9
4
21
A12
A4
MOTOROLA'S PIN·COMPATIBLE EPROM FAMILY
MOTOROLA'S PIN·COMPATIBLE ROM FAMILY
32K
11K
23 JAS
A5[ 3
A31 5
20
G
,A2[ 6
19
A10
All 7
IS
All
AO[ 8
17
Q7
001 9
16~06
011 10
15 P05
021 I'
14P04
Vssl 12
13~03
PIN NAMES
AO-A12. .... Address
G. .. . Output Enable
OO-Q7 ..... Data Output
Vee ..... + 5 V Power Supply.
VSS ...... Ground
AI
This deVIce contains circuitry to protect the
inputs against ,damage due to high static
voltages or electric fields; however, it is advised that normal precautions be taKen to
avoid application of any voltage higher than
maximum rated voltages to this high impedance circuit.
INDUSTRY STANDARD PINOUTS
ADI842/9-8Q
2-201
MCM68366
BLOCK DIAGRAM
AO
Al
A2
A3
AO
A5
A6
A7
A8
A9
Al0
All
A12
9
10
11
13
10
15
16
Address
Deco(1e
I
17
23
DO
01
D2
·03
DO
05
06
07
n
19
18
21
'(l" 20
VCC= Pin 24
YSS = Pin 12
• Active Level Defined by the User
ABSOLUTE MAXIMUM RATINGS ISee Note 11
Symbol
Rating
Supply Voltage
VCC
Y' n
Input Voltage
Operating Temperature Range
Value
Unit
0.3to +7.0
Vdc
-0.3 to + 7.0
Vdc
o to
TA
Tstg
+ 70
'c
Storage Temperature Range
-65 to + 150
'c
NOTE 1. Permanent deVice damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restflcted to
RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and tem~rature range unless otherwise noted)
RECOMMENDED OPERATING CONDITIONS
Perimeter
Supply Voltage
IVee must be applied at least l00,.s before proper device operation is achieved}
Input High Voltage
Input Low Voltage
Symbol
Min
Nom
Max
Unlt
VCC
4.5
5.0
5.5
Vdc
V,~
2.0
-0.3
-
VIL
-
5.5
0.8
Vdc
Symbol
Min
Typ
lin
-
-
Max
10
RECOMMENDED OPERATING CHARACTERISTICS
Ch.r.cteriatic
Input Current IVin = 0 to 5.5 V}
Output High Voltage (fOH = - 206,.A)
Output Low Voltage IIOL = 3.2 mA}
Output Leakage Current IThree-StateIIG=2.0V. Vou ,=O.4 V to 2.4 VI
Supply Current IV CC = 5.5 V. TA = O'C}
CAPACITANCE
If = 1.0 MHz. TA = 25'C. periodically sampled rather than l00,*, tested}
Input Capacitance
Output Capacitance
2-202
VOH
VOL
2.4
1_0
-
ICC
-
45
-
Unit
"Adc
Ydc
0.4
Vdc
10
"Adc
mAdc
80
MCM68366
AC OPERATING CONDITIONS AND CHARACTERISTICS
Read Cycle
RECOMMENDED OPERATING CONDITIONS
IT A = 0 '0 70'C vcc = 5 0 V +
- 10% All timing with 'r = 'I = 10 ns load 01 Figure 11
Symbol
Parameter
t
Address Valid '0 Address Don', Care
MCM68366-25
MCM68366-35
Min
Ma.
Min
Unil
Ma.
'AVAX
250
-
350
-
liS
Address Valid '0 Ou,pu' Valid IAccessl
'AVOV
-
250
-
350
ns
Output Enable Low to Output Valid (Access)
-
120
10
10
-
Output Enable High to Output Hlgh-Z
'GHZO
0
70
10
0
120
-
ns
10
Outpu, Enable Low to Ovtput Invalid
'GLQV
'AVOX
'r.L()X
80
ns
Address Valid to Outpu, Enable Low IAddress Setup)
tAVOL
0
-
0
-
ns
(Cycle Time when Output Enable
IS
Held Active)
Address Valid to Output Invalid
§
READ CYCLE TIMING 1
~
.-----------------tAvAX
'1<3 Held Low)
Address
----------
tAVQ~~------~·~1
ns
ns
VIH
VIL
Dal. Valid
o IData OUtl====!p~re~v;,o;u~sJD~a~t.~V~.~I~id~=:~~~~~=======~!!!~~======
VOL
VOH
READ CYCLE TIMING 2
~
r---tAVGL
Address~yX~(X'~()~('X~X~
...~-I-----------:A...,d~dr-e-ss...,V~a~lid~------------ VIH
~L
'I
G
----------..J
I,....-----VIH
VIL
GLQV
~
~tGLOX
hn~~nm------~-~~-~
VOH
Q mata Outi ---------------HI-Z
_
Data Valid
I
)-HI-Z- VOL
2-203
_
IGHOZr-
MCM68366
FIGURE 1 - AC TEST LOAD
WAVEFORMS
Waveform
Svmbol
MlJ!)!
i:3e
Will Be
Vahd
\~~\\~
milli
YIIIIt!
Will Change
From H It) L
Change
From L 10 H
'NIII Ct1angp
From L to H
Dan't Care
Any Change
:-:hanglfHJ
Permitted
L.;nknowl'
t-
' ' ',:'" tJ
VCllrd
f-rom H 10 l
Change
00 V
Output
Input
RL = 1 2>
MMD6150
Ir
or EQuiv
II I k
,Ir
MMD700G
or EQurv
-=
"Includes Jig Capacitance
Slale
Hlytl
Imp~darlce
READ ONLY MEMORY BLOCK DIAGRAM
MCM68366
Read Only
Memory
Memory
Matrix
18192 x 81
Address
Bus
.-
Memory Address
and Control
Data
Bus
PRE-PROGRAMMED MCM68366P35-3/C35-3.
MCM68366P2!>-31 C2!>-3
The - 3 standard ROM pattern contains log (base 10) and
antilog (base 101 lookup tables for the 64K ROM.
Locations'oooo through 3599 contain log base 10 values.
The arguments for the log table range from 1.00 through
9.99 incrementing in steps of 1/100. Each log value is
represented by an eight-digit decimal number with decimal
point assumed to' be to the left of the most-significant digit.
Anlilog (base 10) are stored in locations 4096 through
8095. The arguments range from 0.000 through 0.999 incrementing in steps of 1/1000. Each antilog value is
represented by an eight-digit decimal number with decimal
point assumed to be to the right of the most-significant digit.
Data Bus
Locations 3600 through 4095 and 8096 through 8191 are
zero filled.
All values are represented ir, absolute decimal format with
eight digit precision. They are stored in BCD format with the
two most significant digits in the lower byte and the remaining six digits in the three consecutive locations.
Example: 1091O (1.011 ~ .00432137 decimal
Address
0000-
0000
5
0100
0010
0011
0011
0001
0111
6
7
2-204
Contents
4
MCM68366
CUSTOM PROGRAMMING
Information for custom memory content may be sent to
Motorola in one of two forms Ishown in order of preferencel:
By the programming of a single photomask for the
MCM68366, the customer may specify the co~tent of the
memory and the method of enabling the outputs.
1. Magnetic Tape
9 track, 800 bpI, odd panty written in EBCDIC character Code. Motorola's R.O.M.S. format.
2. EPROMs - one 64K IMCM68764, MCM687661, two
32K IMCM25321, four 16K IMCM2716, or TMS27161,
or eight 8K IMCM27081.
Information on the general options of the MCM68366
should be submitted on an Organizational Data form such as
that shown in Figure 3.
FIGURE 3 - FORMAT FOR PROGRAMMING GENERAL OPTIONS
ORGANIZATIONAL OATA
MCM68386 MOS REAO ONLY MEMORY
Customer"
Company ____________________________________
Motorola Use Only
Part No .-'"__________________________________
Onglnator ____________________________________
Enable Options·
AL:tlve High Active Low
0
2-205
Part No: ___________________
Specll. No:
Phone No. ___________________________
Output Enable
Quote ______________________
D
(ill
MOTOROLA
~ SCn'1iconductors
MCM2802
Advance Infonnation
.. ,',..... ,."._...
MOS
-_._---------.,
32 X 32 BIT SERIAL ELECTRICALLY ERASABLE PROM
The MCM2802 is a 1 K-bit serial Electrically Erasable PROM designed
for applications requiring both non-volatile memory and in·system
information updates. In digital tuning systems, it provides storage
for up to 32 channels. It has ,external control of timing functions
and serial format for data and address.
IN·CHANNEL, SILICON GATE)
32 X 32 BIT
ELECTRICALLY ERASABLE PROM
,.-
- Single 5V supply in Read mode
_ 5V and 25V supply for Erase and Program
- In·System Program/Erase Capability
I
- O·100kHz clock rate
.
LSUFFIX
_ Floating gate process
CERAMIC PACKAGE
CASE 632.1)6
PSUFFIX
- Expandable to 16K·bit systems
PLASTIC PACKAGE ALSO AVAILABLE
CASE 646.OS
- Word and Array erasable
-----------------'-----------,
FIGURE 1 - BLOCK DIAGRAM
~-----
---
PIN ASSSIGNMENT
T2-
-n
1ft:
AO/61
V,P
C.
C1
Vss
Cl
C2
* For normal operation, hardwired to
vss.
PIN NAMES
VPC. . . . . . . . . Program Voltage Control
ADO. Address Input + Data Input/Output
T1. T2 . . . . . . . . . . . . . Margin Testing
Cl, C2, C3, C4 . . . . . Chip Address 1 to 4
CL . . . . . . . . . . . . . . . . . . . . Clock
RE .................... Reset
AO/DA. . . . . . . .. Shift Register Select
This device contains circuitry to protect the
inputs against dlWTlage due to high static
voltages or electric fields; however, it is
advised that normal precautions be taksn to
avoid application of any voltage higher than
maximum rated vottages to this high
impedance circuit.
This
IS
advance information and specifications are subject to change without notice.
2·206
MCM 2802
ABSOLUTE MAXIMUM RATINGS (Voltages referred to Vss)
Symbol
Min
Max
Unit
DC Supply Voltage
V DD
-0.5
8
Vdc
Programming Voltage
Vpp
-0.5
28
Vdc
Input Voltage
VIN
-0.5
8
Vdc
VP Control Output
VPC
-0.5
28
Vdc
Operattng Temperature Range
TA
-40
85
·C
TSTC
-56
150
·C
Reting
Storage Temperature Range
NOTE - Permanent device damage may occur if ABSOLUTE MAXIMUM
RATINGS are exceeded. Functional operation should be restricted to
RECOMMENDED OPERATING CONDITIONS. Exposure to high ... than
recommended voltages for extended periods of time could affaet device
raliability.
SWITCHING CHARACTERISTICS ITA = 0 ... 70 DC; Voo = 5V ± 10 %; Vp = 24.5V ± 1.5 V
Pin
Symbol
P.remeter
Fig No
Min
tER
Erase time
100
twR
Write time
10
CL
FCL
Clock Frequency FCL = lIT CL
CL
tCLH
Clock High Leyel Hold Time
2
4
CL
tCLL
Clock Low LeYel Hold Time
2
4
CL
tCLRF
Clock Fall Time and Rise Time
2
AD/DA
tAD/DA
Register Control to Clock
Delay Tim. except for tREAD
2
1
tREAD
After READ opcode only
3
2
I/O
tDSUP
tDH
I/O
tDOUTS
tDQUTP
0
Caut
Oat. In Set-Up
2,3
2
2,3
0.1
3
Data Out Parallel Ooley
3
Output Capocitanoo (V out -0 V)
ms
US
US
".
100
".
US
US
1
3
12
2-207
kHz
US
1
Data In Hold
Unit
m.
100
2
Data Out Serial Delay
Max
US
US
pF
MCM 2802
DC CHARACTERISTICS ITA
= 0 ... 70·C;
Ch_
VOO = 5V ± 10%; Vp = 24.5V ± 1.5 V
MOl<
Unit
Vpp
Supply Current
Ipp
3
mA
VOO
Supply Current
100
20
mA
1/0
Tri..... lnputl
V OH =2.4V
10H
-0.1
Output
VOL =0.5V
10L
1.6
Tristate
liN
10
,.A
liN
10
,.A
Pin
Allinputl
Except 1/0
VPC
AllinPUti
Symbol
Condhlon
Input Leakage
VP Control I
VON = IV
ION
Pull down device
OFF .....
V MAX
VOFF = VP
10FF.
Input Low Vol_
V IL
Input High Voltage
V IH
r-------
Min
mA
mA
mA
0.7
Vpp
10
,.A
0.8
V
2.4
V
~-,-=- :u""-G·R~:~-H---,-CL-"·-~---------...,I
-.- - - - - - -
C O CK
---/
H~~~~..f
l--~~
f----
I
i
I
AOCI (II)
AOIDA
______-+__~x~_4--+-~------_++_-
i
.--~~~~~~~~~~~~
FIGURE 3 - READOUT T I M I N G S - - - - - - - - - - - -.......j
tREAD
CLOCK
AOO
__--__----~~~----~_1~====~~~T~.======~D<
ADOR+READ COOl " .. ) IN
AD IDA
DATA OUT
BiTt
'-----
\~+-------~H-------
2-208
- - - - - - - - - - -.. - -
~~~~0-Ah--Cr:/t==
I I
~ptJ---"""'----
CLOCK
~
ADO
DO
~
AD/5i.
OP COO<
DECODING
•
L
STBY
~ I PIS
D1
DZ
1\ I
(
H
l
H
I
I,
~"
~
\1
II
t
ST8Y
)
~
f
/
READ OUT
/
,
RfADOUT
D31
,
------~I~---~I/
C
DlI
i
/
(FORCED)
II
-.--.-.-
(fORCm)
STaY
,
(DECtXJED)
II
l
q
U
/I
H
•
':-l
~
FIGURE 4 - READOUT SEQUENCE
------------------1
"
32
12
"
CLOCK
ADO
AD{Di.
OP CODE
DECOD1NG
,
,;
STaY
(fORCED)
f
STaY
-----,
WR1Tt
'I
(fORCED)
f--
L--
ERASE
T ER
~
ST8Y
(FORaDI
f-
T WR
-!
-I
---- FIGURE 5 - WRITE SEQUENCE _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--J
MCM 2802
FUNCTIONAL DESCRIPTION
The circuit accepts 12 bits of Address/Op code in the
address register and 32 bits of data in the data register
(see figure 1: Block diagraml.
Addre../Op code format (figure 11
The four shifted bits C1 to C4 are used as chip select
word in multichip systems. The chip address is defined by
hardwiring the C1 to C4 pins. These bits are adjacent to
the address field, so that no software modification is reo
quired in a program designed for a multi·1 K memory appli·
cation.
The five following A 1 to A5 bits select one of the word
addresses. The last 3 bits 01 to 03 control the operating
modes.
Function
Read
Word ErasE!
01
02
03
o
o
o
0
Block Erase
Write
Standby
___J ·
Read operation (figure 41
:m~ I
11 The ADDRESS/OP CODE is loaded. The address
selecting the word to be read and the op code bits being
the READ code.
21 The AD/M is switched to the data mode, thus
initiating the parallel transfer from the core to the shift
register. First bit of data is present at the output.
31 As soon as the first of the 31 data out clock pulses is
applied, the parallel transfer is stopped and data is
shifted at the output. Data is recirculated in the data
register.
41
The output buffer is turned on only, when READ is
internally decoded, AD/DA is low and chip is selected by
C1 and C4. Otherwise it is in the high impedance state.
41 The AD/DA line is switched low again for a t =
tWRITE, during which the selected word is programmed.
51 At the end of the WR ITE operation it is recommended
to load op code STANDBY and to return input AD/DA to
the low state.
Erase
Both BLOCK ERASE and. WORD ERASE are provided
and are controlled by the op code. Vpp has to be applied
for BLOCK ERASE, WORD ERASE and for WRITE. For
all other conditions it can be switched off to high
impedance or VDD or VSS.
Standby
When AD/DA is high, the instruction decoder is disabled
and hence STANDBY is forced. By shifting the STANDBY
op code into the address register, STANDBY will be reo
cognized independently of the state of AD/DA.
Clock
The active high clock is only used for shifting data and
addresses. This shift occurs on the clock falling edge.
Chip selection
The ADDRESS/DATA line can be used as a chip select in
a system having other serial I/O devices. DATA and
CLOCK lines being shared the non-volatile memory is
only activated when the AD/DA line is low .. Shifting
information to the data register has no effect to the core
while the chip is deselected.
In a multi·memory arrangement, all the lines including
ADDRESS/DATA, CLOCK and DATA, are shared, with
the exception of C1 to C4 which are hardwired to VDO or
VSS, thus defining the circuit address. All Vp control
outputs of the memory circuits can be combined in a
wired OR configuration.
Data protection
Addresses and data are clocked in and out with the falling
edge of block.
Writing (figure 51
11 ADDRESS/OP CODE is shifted in, the op code being
either BLOCK ERASE or WORD ERASE.
21 Switching the ADiOA line low for t = tERASE
initiates the erase process. During this period of time,
a data word can be shifted into the data register.
31 Then the WRITE code and the same address is loaded
to the address register.
When Vpp is turned off, data stored in the array is always
protected. A Vpp control output is provided for switching
the Vpp supply. It consists of a pull down device to VSS.
This device is turned on only when: VDD is present, a
WRITE or ERASE code has been loaded in the address
register and AD/DA is low.
Schematics for this exte. nal Vpp control are proposed in
figure 6.
Reset
Vpp and VDD may be turned on or off in any sequence
without disturbing data in the NVM array. During power·
up, the op code is preset to the standby mode. The
RESET input can be connected to the system RESET.
2-210
MCM 2802
r---------------- FIGURE 6 -
Vpp CONTROL AND MULTICHIP SETUP -
vPP-......- _
10kA
41kA
J
R2
vpcl
VPP
.s
vpcl
VPP
N
N
V
CL
ADQ
AD/DA
I
...
0
IS
u
U
E
1
VPP
N
0
E
vpp
vpcl
...
v,ki'
•
E
2
I
'--------------_._------_. ----- -
1.
3
I
I
""-
- - - ..
2·211
_-----
'R11
25V
CMOS Memories
RAM, ROM
3-1
®
MCM14S0S
MOTOROLA
CMOS LSI
64-BIT STATIC RANDOM ACCESS MEMORY
I LOW·POWER COMPLEMENTARY MOSt
The MCM14505 64-bit random access memory is fully decoded
on the chip and organized as 64 one-bit words (64 X 1)_ Medium
speed operation and micro power supply requirements make this
device useful for scratch pad or buffer memory applications where
power must be conserved or where battery operation is required.
When used with a battery backup. the MCM 14505 can be utilized
as an alterable read-only memory, allowing the battery to retain information in the memory when the system is powered down, and
allowing the battery to charge wh~n power is applied_ The micropower requirements of this memory allow quiescent battery operation
for great lengths of time without significant discharging.
•
64-BIT (64 X 1) STATIC
RANDOM ACCESS MEMORY
Quiescent Current = 50 nA/package typical @ 5 Vdc
•
Noise Immunity = 45% of VDD typical
•
Supply Voltage Range
•
Single ReadlWrite Control Line
•
Wired·OR Output Capability
Expansion
=
3_0 Vdc to 18 Vdc
= 180 ns typical
(3-State Output)
at VDD
Write Cycle Time = 275 ns typical at VDD = 10 Vdc
CASE 632
CASE 646
"""'' 11SUffIX
= 10 Vdc
Access Time
•
P SUFFIX
PLASTIC PACKAGE
OROERING INFORMATION
for Memory
•
L SUFFIX
CERAMIC PACKAGE
L
P
A
•
Fully 8uffered Low Capacitance Inputs
•
Capable of Driving Two Low·power TTL Loads, One Low-power
Schottky TTL Load or Two HTL Loads Over the Rated Temperature Range
C
Denote,
Ceramic Package
PlastiC Package
Extended Operating
Tamperatur. Ranga
Limited Operating
Temperatur. Range
MAXIMUM RA TI NGS (Voltages referenced to Vss)
Symbol
Value
Unit
VOO
-05to+18
Vdc
Input Voltage, AU Inputs
Vin
-0.5 to VOO + 0.5
Vdc
DC Current Drain per Pin
I
10
mAde
TA
-55 to +125
-40 to +85
°c
Rating
DC SupplV Voltage
Operating Temperature Range - AL Device
C LlCP Device
Storage Temperature Range
T stg
-65 to +150
°c
BLOCK DIAGRAM
Add .... { : ;
Inputs
A3
~
4
10 Data Out
A411
AS 12
Data In 13
This device contains circuitry to protect the inputs against damage due to high
static voltages or electric fields; however, it is advised that normal precautions be
taken to avoid application of any voltage higher than maximum rated voltages to
this high impedance circuit. For proper operation it is recommended that Vin and
V out be constrained to the range VSS';;; (Vin or V out )';;; VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VOOI.
3-3
Strobe S
CE 16
CE28
R/W 9
Voo -; Pin 14
VSS"'Pln7
MCM14505
ELECTRICAL CHARACTERISTICS
Chafacterlstlc
Output VIJltaqe
V,n
"0" Level
Vee
Vdc
VOL
~O
VOH
Oar VOO
NOise Immunity u
I V out
I YOU!
I YOU!
10 Vdel
1 5 Voe}
VNH
Output Onve Current (AI. DeVice)
Source
IVOH 2.5 Vdc}
4.6 Vdcl
95 Vdcl
04 Vdcl
Sink
'OL
0.5 Vdc)
~
Thi h·
Min
Typ
Max
-
a
a
a
005
005
0.05
4.95
995
1495
5.0
10
15
005
0.05
0.05
50
10
15
495
995
1495
5.0
10
15
15
3.0
4.5
15
3.0
4.5
2.25
4.50
675
50
10
15
14
2.9
4.4
15
3.0
4.5
225
4.50
6.75
5 a
50
10
15
-1.2
-0 25
-0.62
-18
-
-10
-0.2
-05
-15
-17
-0.36
-0.9
-35
50
10
15
0.3
0.9
2.2
..
0.25
0.75
1.7
0.35
1.2
4.5
5.0
5 a
10
15
-1.0
-02
-05
- 1.4
·08
-0 16
-0.4
-1.2
-1.7
-036
-0.9
-3.5
5.0
10
15
0.2
0.6
3.9
0.15
0.5
0.7S
0.35
1.2
4.5
..
Min
495
9.95
14.95
Max
Unit
0.05
0.05
005
Vdc
-
Vdc
Vdc
1.5 Vdcl
Output Drive Current (CUep DeVice)
(VOH 2.5 Vdel
(VOH 46 Vdcl
(VOH ·9.5 Vdcl
(VOH" 135 Vdcl
Source
IVOL • 0.4 Vdcl
(VOL - 0.5 Vdcl
IVOL • 15 Vdcl
Sink
-
14
2.9
4.4
-
15
3.0
4.5
-
..
-0.7
-014
-0.35
-
0.18
0.50
12
-1.1
'OL
-
0.1
0.4
0.6
I,n
15
'0 1
'0 00001
'0 1
I,n
15
.1.0
.0 00001
t
C,n
-
QUiescent Current (CLlep DeVice)
'00
100
(Per Package)
Total Supply Current·· 't
(DynamiC plus QUiescent,
Pel Package)
ICL 50 pF on all outputs, _II
buffers sWltchmg)
Three-State Leakage Current
(AL DeVice)
Three-State Leakaqe Current
(CLlCP DeVice)
'T
mAde
mAde
-0.6
-0.12
-0.3
-1.0
-
Input Current (CUep DeVice)
QUiescent Currenl (AL Oevlce)
(Per Package)
-
IOH
Input Current (AL DevICe)
Input Capacitance
(V,n 01
Vdc
mAde
'OH
(VOH -,13.5 Vdcl
IVOL
(VOL
(VOL
Max
VNL
0.8 Vdc!
I YOU! ",- 0.8 Velc)
I YOU! . 1.0 Vdcl
I V out ' 1,5 Vde)
IVOH
IVOH
2SoC
T ,ow •
Min
10
15
VOO or 0
"'" Level
V,n
Symbol
50
7.5
0.050
50
10
15
5 a
10
20
a 100
0150
50
10
20
50
10
15
50
lOa
200
0.050
a 100
0150
50
lOa
200
50
10
15
'T
'T
'T
'TL
15
,0 1
'TL
15
±1 0
11.28 "A/kHzl I
12.56 "A/kHzl I
13.85 "A/kHzl I
·Tlow == -5SoC for AL Device, -40 0 C for CLlCP Device.
Thigh == +125 0 C for AL Device, +8S o C for CLlCP Device
#Noise immunity specified for worst-case input combination.
tTo calculate total supply current at loads other than 50 pF.
iTlell = iT'50 pFJ t 1 x 10- 3 ICl -Sal VOOI
where: IT is in jJA (per package), CL in pF, VDO in.Vdc, and f in kHz is input frequency_
··The formulas given are for the typical characteristics only at 25°C.
3-4
-
1.0
t
t
t
..
mAde
_.
.10
/-lAde
·14
IJAdc
pF
..
..
-
150
300
600
pAdc
375
750
1 SOD
/JAde
/JAdc
100
iDD
100
. 000001
± 0.1
,3.0
/JAdc
'0 00001
, 1.0
± 7.5
pAdc
MCM14505
SWITCHING CHARACTERISTICS·
ICL
= 50 pF
TA
=
Output Rise Time
'TLH
'TLH
'TLH
=
=
=
25 0 CI
Symbol
Characteristic
12.43 ns/pFI CL + 58.5 n,
11.08 ns/pFI CL + 36 n,
10.72 ns/pFI CL + 39 ns
Output Fall Time
Propagation Delay Time
Read Access Time
=
=
=
Typ
Mox
5.0
10
15
-
-
180
90
75
360
180
150
5.0
10
15
-
160
80
65
320
160
130
Strobe Down Time
ns
ns
5.0
10
15
-
455
210
130
750
400
300
5.0
10
15
500
125
95
100
50
75
-
5.0
10
15
300
120
90
-100
-40
-25
-
5.0
10
15
200
75
55
70
25
20
-
5.0
10
15
270
60
45
90
20
15
-
5.0
10
15
400
100
75
80
25
11
-
5.0
10
15
75
25
20
15
10
5.0
-
5.0
10
15
50
15
10
0
0
0
-
5.0
10
15
0
0
0
-25
-10
5.0
10
15
0
0
0
5.0
10
30
-
5.0
10
15
-
500
200
150
750
400
300
5.0
10
15
-
440
275
200
700
550
415
5.0
10
15
-
200
80
60
600
200
150
-
ns
'WL
---
i
--
Write Setup Time
I
Address Release Time
ns
'sulWI
I
ns
'sulAI
I
-
ns
treHR)
I
i
Data Hold Time
ns
'hlDl
I
I
I
Read Release Time
i
1
Read Cycle Time
'cyclAI
Write Cycle Time
ns
-90
ns
'rellW)
iI
--
-
',ellA)
I
Write Release Time
Output Disable Delay
(10% Output Change into 1.0
ns
'sulD)
Aead Setup Time
ns
'su
Data Setup Time
n.
ns
'cyclWI
ns
tdis
kn
Load)
The formula IS for the typical characteristics only.
I
3-5
Unit
ns
'acclAI
11.4 ns/pFI CL + 385 ns
110.7 ns/pF) CL + 175 ns
10.5 ns/pFI CL + 105 ns
~etupTime
Min
'THL
'THL =12.16ns/pFI CL +52n,
'THL = 10.96 ns/pFI CL + 32 n,
'THL = 10.69 ns/pFI CL + 33 ns
'acclAI
'acclAI
'acclAI
VOO
'TLH
MCM14505
FIGURE 1 - READ CYCLE TIMING DIAGRAM
50%
Strobe
tWHmin
=:
tcyc(A) mSK tWlmin
Nots. The read/write input can be maintained at a logical " ' "
(high voltage) during a read cycle.
tacc(RI
Data Output -o:::-u,-p-u-,-'\.
"0"
f-
_
/
tdis -
r--"-'-"--lo._---:----,-----VOH
I".. Ou'pu'
Disabled
"0"
Oat.
Valtd
V
Disabled
r-
FIGURE 2 - WRITE CYCLE TIMING DIAGRAM
tWHmin == tcyc(W) max -tWL min
50%
'WH
Strobe
Note The read/write input can be maintained at a logic "0"
(low voltage) durIng a write cycle. If the read/write
mput IS mamtalned at 8 logic "0" whtle the strobe IS
8 logic"''', then the output data will be d isab led (high
impedance) during the wr.te cycle.
Data In
--------w--------Y
_ _ _ _ _ _ _5_0__
~~_ _ _ _ _ _ _ _ __
FIGURE J - MAXIMUM STROBE PULSE WIDTH
versus TEMPERATURE
FIGURE 4 - TYPICAL READ ACCESS TIME
yersus LOAD CAPACITANCE
100~~~~~~~~~~~~~~~~~~~~~
~ -~ ----F-':=-r-:.--4'=----r--
~
10 - -
--~
-~O
--r=:
--r-----
50Vdc
!
600
~
400
r.
25°C
r--'--
1
";::
"
r
T··--
800
VOD
~
D
~
~ 200
~
':1.0 Vdc
L
10 Vdc
15 Vdc
0
-60
20
20
60
100
140
0
TA. AMBIENT TEMPERATURE IUCI
20
40
60
CL. LOAD CAPACITANCE (pfl
3-6
80
100
MCM14505
FIGURE 5 - TYPICAL OUTPUT SOURCE
CAPABILITY '''5U5 TEMPERATURE
FIGURE 6 - TYPICAL OUTPUT SINK
CAPABILITY yo"U5 TEMPERATURE
_uI_. ___IU I
Voo-,
Vlnput
0----
_._--
----l ~
300 '"
1 0 k.HI
Notes
, Cycle R IW to ground and then to V DO
prIor to measurement to Insure turn
on of the device under test
2
For the P-channel characteristiCS.
3
For the N-channel characteristiCS,
VOS'
VOS
4
IS
VO H
VOO'
,o~
measured directly
For the drain current, 10 - 100 Amp
1";,
v,,,
---_._-,_."--(al TA
55 u C
'25 u C
It;) TA 112SUC
(h) TA
;;C
5
·t
10
..j t
I
z
tt
~
t
., 0
Voo
I
. rf'
50 Vdc
h
1
tJ
z
"
~
u
Z
tt
'""
"
0
~
~
~
"
~
~
0
~
0
l__
BO
a
(iI)
+-.+--+~
"
0
TA . -55°C
lb)TA - +25 uC
(ellA '125 0 C
·10
10
10
·B 0
vos. ORAIN
VO I T AGE IVtlc)
Vos. ORAIN VOl TAGE (Vile!
3-7
MCM14505
FIGURE 7 - FUNCTIONAL CIRCUIT DIAGRAM
Oat. In
BasIc Memorv Cell
3-8
MCM14505
OPERATING CHARACTERISTICS
In considering the operation of the MCM14505 CMOS memory.
row IS In the low state, and the unselected 15 rows retain their
logiC "1" level due to the row capacitance that exists when the row
decoder Inhibit gates are disabled. ThIs capaCItive storage mechanism requires a maximum strobe Width (see Figure 3) equal to the
lunctlon reverse bias RC time constant. When the strobe IS returned
to a logiC "0" the rows are forced to VDO by the row decoder
inhibit gates (pullup deVices!. Similarly the column read/write
inhibit gates (pulldown deVIces) force the column lines to a logiC
"0" state.
Two column lines are associated With each memory cell In order
to write IOta the cell. The write selection drivers are enabled when
the R/W line IS a logiC "0" and the strobe line IS a logiC "1" The
input data IS written Into the column selected by the column
decoder. For Instance, If a "1" IS to be written In the memory cell
associated WIth row 1 and column 1, then row 1 would be enabled
(logic "0") while column 1b is forced high and column la is forced
low by the wrtte selection drivers. If a logic "0·' is to be written
IOto the cell, then column 1a IS forced high and lb is forced low.
The data that IS retamed 10 the memory cell is the data that was
present on the data Input pin at the moment the strobe goes low
when R/W IS low, or when R/W goes high when the strobe IS high.
refer to the functional CirCUit diagram of Figure 7 and timing
diagrams shown in Figures 1 and 2 The basIc memory cell IS a
cross.roupled flip-flop consisting of two Inverter gates and two
P-channel devices for read/write control. The push-pull cell provides
high speed as well as low power
Durmg a read cycle, when the strobe line IS high the write
selection dnvers are disabled and the data from the selected row
IS
available on columns lb, 2b, 3b, and 4b. The A4 and AS address
bits are decoded to select output data from one of the four columns.
The output data is available on the data output pin only when the
strobe and read/wnte lines are high simultaneously and after the
read access time, tacdR!, has occurred (see Figure ll. Note that
the output IS mitla"y disabled and always goes to the logiC "0" state
(low voltage) before data 15 valid. The output IS In the hlghImpedance state (disabled) when the strobe line or the R /W line is
in the low state. The memory IS strobed for reading or writing only
when the strobe, CE 1, and CE2 are high simultaneously. The R/W
line can be a dc voltage dUring a read or Write cycle and need not
be pulsed, as shown In the timing diagrams. For this case the RfW
line should be a logiC "1" (high! for reading and a logiC "0" for
WrttlOg.
When the strobe line IS high, the column read/wrtte Inhibit
gates and the row decoder Inhibit gates are disabled, the selected
APPLICATIONS INFORMATION
Figure 8 shows a 256·\NOrd by n-blt statiC R AM memory system
The outputs of four MCM14505 deVices are tied together to form
256 words by 1 bit. Additional bits are attained by paralleling the
tnputs in groups of four. Memortes of larger words can be attained
by decoding the most significant bits of the address and ANDing
them with the strobe Input.
Fan-In and fan-out of the memory IS limited only by speed
requirements. The extremely low Input and output leakage current
(100 nA maximum) keep the output voltage levels from changtng
Signif,cantly as more outputs are tied together. With the output
levels independent of fan-out, most of the power supply range IS
available as logic swing, regardless of the number of units wired
together. As a result, high nOise immunity is marntatned under
all conditions.
Power dissipation IS 0.1 JJW per bit at a 1.0-k Hz rate for a
5.0-\,I()lt power supply, while the static power dissipation IS 2.0 nW
per bit. ThiS low power allows non-volatile information storage
when the memory is powered by a small standby battery.
Figure 9 shows an optional standby power supply CtrCUlt tor
making a CMOS memory "non-volatile". When the usual power
fails, a battery is used to sustain operation or maintain stored
information. While normal power supply voltage is present, the
battery is trickle
t=c>
,
G
2
3
H
4
"
,2
6
-=-
MCM14505
64·Bit
Ram
'Or--
8
5
~ t- 9
'3
Dat8 In
,
~BOOut
2
3
4
"
MCM14505
6
8
Ram
12
Dynamic
64-Bit
'0 r--
5
StrOb:...s---L..
~
r-~
9
,3
,
2
3
4
"
"12
6
8
Aead/Write
~
I I I I II II
I I II I II I
I I I 1111 I
I II III I I
I I
I I
I I
I I
I
I
I
I
MCM145Q5
64-Bit
Ram
'0 r--
5
9
,3
I
I
I
I
Expand Verticallv For n·Bits
Circuit diagrams ul111Zlng Motorola products are Included as a means
of Illustrating typical semiconductor applications. conseQuentlV.
cQr"Iplete 'nforrr.ation suffrClent for construction purposes is not
necessarily given
The Information has been t;aretu1ly checked and
.5 believed to be entirely reliable
However, no re$pons,b,llty IS
assumed for Inaccuracies. Furthermore, such Information does not
convey to the purchaser of the semiconductor devices descrtbed any
Itcense under the patent rights of Motorola Inc or others
3-10
MCM14505
FIGURE 9 - STAND BY
BATTERY CIRCUIT
FIGURE 11 - CMOS·TO·TTL INTERFACE
FOR VOO • 5.0 V
FIGURE 10 - TTL TO CMOS INTERFACE
Vee
Von "'- 5.0 V
2.0 k
r--~~-----o V DD
470
TO TTL
IF.O.· 1)
R
x>--1.0
,000001
Con
-
100
mAde
pAdc
-",Adc
50
75
_.
pF
100
200
1800
.uAdc
50
10
15
100
0.5
100
200
400
1.0
1.5
200
400
Per Package)
50 pF on all outputs, all
50
10
IT
IT
IT
15
-,14
0.5
10
1.5
IT
-
mAde
·1.0
100
200
400
100
-
10
50
10
15
(Per Package)
Total SupplV Current"' t
(DynamiC plus QUiescent.
-
2.4
~
!per Package)
Vdc
-
0.36
09
15
QUiescent Current (CLlCP Oevu:;e)
-
-0.3
-1.0
Ion
QUiescent Current (AL DeVice)
-
-1.1
Input Current tAL DeVice)
Input Capacitance
(V ln
01
1.4
2.9
4.4
mAde
IVOH 095 VdcJ
IVOH 0 135 Vdcl
Sink
-
IOH
IVOH 0 4.6 Vdcl
= 1.5
50
10
15
-
TVp
mAde
IVOL 0 1.5 VdcJ
Output Dnve Current (ClICP Devlcel
Source
IVOH 02.5 Vdcl
IVOL
Thi h·
Min
IOH
0
IVOL 0 0.4 Vdcl
IVOL = 0.5 Vdcl
25°C
M ••
Vdc
VNH
Output Drive Current (AL Device)
IVOH
25 Vdcl
Source
IVOH - 4.6 Vdcl
IVOH 0 9.5 VdcJ
(VOH ~ 135 Vdcl
0
.
VNL
SI
I YOU! . 0.8 Vdc)
I .v out "- 1 0 Vdc}
I YOU! . '.5 Vdc)
IVOL 04 Vdcl
IVOL 0 0.5 Vdcl
Tlow
Min
!
3600
7200
400
1800
3600
--
}JAde
7200
}-lAde
(146 /JA/kHz) I + 100
!2 91 .uA/kHz) t + 100
!4 37 .uA/kHz) t + 100
ICL
buffers SWitching}
Three·State Leakage Current
(AL DeVice)
In
15
,0 1
·000001
,0.1
,30
/.lAdc
Three·State Leakage Current
In
15
!10
. a 00001
:!:
1,0
, 7.5
.uAdc
!CLlCP DeVice)
-Tlow . -55°C for AL DeVice, -40°C for CLlCP DeVice
Thigh ~ +125 0 C for AL DeVice. +85 0 C for CLlCP DeVice
".Noise Immunity sp~Clfled for worst·case Input combination
NOise Margin lor b01h "1" and "0" level" 1.0 Vdc min @ VOO
. 5,0 Vdc
20 Vdc mm @ VOO
10 Vdc
2.5 Vdc mln@ Voo
15 Vdc
tTo calculate total supply current at loads other than 50 pF
ITICLI
where
ITI50pFI' 1.10- 3 IC L -501 VDDI
IT IS In.uA (per package), CL m pF, VOO ,n Vdc, and fin kHz
IS
--The formulas given are for the tYPical characteristiCS only at 2SoC
3-13
mput frequency
MCM14537
SWITCHING CHARACTERISTICS·
ICL
=
50 pF TA
=
250 C)
Ch.r.cteriltic
Figur.
Symbol
3
tTLH
Output Rise Time
tTLH = 13.0 ns/pF) CL + 30 ns
tTLH = 11.5 ns/pF) CL + 15 ns
tTLH = ILl ns/pF) CL + 10 ns
Output Fall Time
tTHL = 11.5 ns/pF) CL + 25 ns
tTHL = 10.75 ns/pF) CL + 12.5 n.
tTHL = 10.55 n./pF) CL + 9.5 ns
Read Access Time from ST or CE2
tace = 11.4 ns/pF) CL + 2480 ns
tace = 10.7 n./pF) CL + 690 ns
tace = 10.5 ns/pf) CL + 393 ns
Output Enable Delay from eEl or CE2
3
Typ
5.0
10
15
-
180
90
65
5.0
10
15
-
100
50
40
5.0
10
15
400
150
115
2500
700
400
5.0
10
15
70
25
20
300
100
70
5.0
10
15
1800
600
450
ns
ns
t acC7 (CE n )
4,5,6,7
tsulA)
-. -4:5,6~7- .-;;;(~)--
;~
I
,
I
tsulD)
ns
6000
2000
1500
ns
900
300
225
600
200
140'-
ns
I -
1400
I
t ::.-- - n;--
480
-.-- ___ ~L_ f_~;--~~--I
---------- .. - ---7---
200
100
80
l:rT-2:0t'--r~-' 1--,;-;-
thID)·5.0··
Data Setup Time
Unit
360
180
130
taeclR)
5,6
H~ld Time f-;-om An to sf;;-,CE2 .-. -----. -.
Min
tTHL
4,5
Setup Time from An to 5T or CE2
- - r---- 1--Max
VOO
~
1
5.0
3600
1200
i=---+,--ns----1
10
15
1800
1350
600,
420
~~
720
:~
24=o----t------1---n-s---1
240
180
80
55
-
~==~~~~--T---------------~,---'7--t-~th-I~W=E~)-i-~5~.~0-i-~1'~5o--r-!5ci---+-1 ----~I-n-s-~
Write Enable Hold
ime
r-;,W;:rC;it':Oe"1E":nc::abi':'li::et(~o%_
;i
,~J
-1--1
''---f--.
----._-'-W-L-(-W-I--------,-Cy-;-(r--W-I--------'-;:--(A-I- - _ -
Strobe or
eE1 or CE2
1ST, CEI, CE21
The Strobe, eE1 and CE2 may be utilized to control a write cycle,
however, during changes of address either Strobe or CE2 must
be in the logical " ' " state (high level).
2
oeta input logic level is don't care during the indicated intervals.
3
Data input logic level must remain fixed.
4
Write Enable may be maintained as a logical "0" during the write cycle.
S
All input rise and fall times are 20 ns.
3-17
Vaa
VOL
MCM14537
LOGIC/BLOCK DIAGRAM
3 State Enable
tHigh AeslstanCE! State)
ST
±----L=rr--
I
A7J-----=f··
:::!
I
u_
A3
J;':~ ~~
-~
L
I
AO
0--1--------1
II
16.16.1
~~
I
A2D--i-----------1
AI
l
l::===__
I=<~_
-
M:~'~~V
10f16~M
=---=-3
J
Decoder
O---':---L__ -~:-~~~
i-----Set
~~:~~t
Q
~-~Re,et
L ____ ._~I
I
L __
FUNCTION
Address changing
sf
WE
D,n
°out
X
X
R'A
X
X
X
R
0
0
X
X
R'4
X
X
X
X
R
" ' " disables write cycle
and D out
X
X
X
A
The chip
C-El
CE2
X
X
VCllld
X
Adc:Jress changing
X
not valid
C out <..hsabled In
high reSistance state
X
COMMENTS
00.lJ.l will t)e active If t-E; aoc:l
GE2
"0" cmd WE
C'E2· "1"
",",
fully disabies Internal
log": and output.
Changing address ,n this mode
may result
III
altered data
GEl
IS
tully disabled.
WE
X
X
X
0
X
R
"0" enables IIIIrl11119 Into
memory If CE i, CE2, and
ST
Dour enatJled
actIVe state
If
111
"0"
S:,..-
",", the output stores
0
0
X
X
A
0
0
0
X
A
The output reads the present
contents that are addressed.
0
X
R
The addressed location '5 read
,nto outpUT latch With OIJtput In
the "R" state.
Read addressed
memory lo,atlon
mto output latch.
X
X
Disable reading
from memory
X
X
Wnte Into memory
0
0
X
X
R
X
X
RIA
0
0
A
R
X
X
X
1
X
X
X
X
X
X
X
X
X
X
X
X
1
X
Write disabled
and reads the prevIous data
frorn or wrItten into ",erTlory.
Address changing can take
place In this condition.
Om is written .nto memory
and into the output latch
WE - "1" IS a read enable.
R
WE ~ "0" IS a write enable.
R
RIA
RIA
R' High resistance state at D out
A
An active level of either VSS or VO D
AiA
An R or A condition dependmg on the don't care conditiOn
X
Don't ClIre condition (must be In th ...· "1" or "0" state)
1
0
A high level at VDD
A low level ilt VSS
3-18
MCM14537
TYPICAL APPLICATION FOR SERIAL WORDS UTILIZING BUS TECHNIOUES
T word
T wor{lllywi
t,H.{(ST)' in·l) t acu C£.l)
3 8
~s
tor a 32 bit senal wurd <11 VOO
10 V
Typical 1024)( 1 RAM Utill}',ng Four MCM14537's
Typical Low Power 1024 x 1 RAM UtiliZing Four MCM14537's.
3-19
®
MCM14552
MOTOROLA
CMOS LSI
256-BIT STATIC RANDOM ACCESS MEMORY
ILOW-POWER COMPLEMENTARY MOSI
The MCM14552 is a static random access memory (RAM) organ·
ized in a 64 x 4 bit pattern. The three chip enable inputs can be used
as extensions of the six address inputs, creating 9·bit address scheme.
Eight MCM14552 devices may be used to comprise a 2048·bit memo
ory (512 x 4) without additional address decoding.
The mode control (M) is used to change the control logic charac·
teristic of the circuit. For example, with M high, the J·state input
(T) fully controls the J·state characteristic of the output. With M
low, the output J·state characteristic is controlled by chip enable
inputs (CEl, write enable input (WE) and T.
The memory is designed so that dc signals may operate the memo
ory, with no maximum pulse width restrictions.
Medium speed, micropower operation, and control flexibility
make the device useful in scratch pad or buffer applications where
battery operation or high noise immunity are required.
256-BIT (64 X 4) STATIC
RANDOM ACCESS MEMORY
L SUFFIX
•
Quiescent Current
•
Noise Immunity = 45% of VDD typical
=
50 !lA/package typical @ 5 Vdc
CERAMIC PACKAGE
CASE 623
•
J·state Output Capability for Memory Expansion
•
Output Data Latch Eliminates Need for Storage Buffer
= 10 Vdc
•
Access Time = 700 ns typical @ VDD
•
Fully Decoded and Buffered
•
Supply Voltage Range
•
Capable of Driving Two Low·power TTL Loads, One Low·power
Schottky TTL Load or Two HTL Loads Over the Rated Temper·
ature Range
= J.O Vdc
to 18 Vdc
P SUFFIX
r'" .
PLASTIC PACKAGE
CASE 709
ORDERING INFORMATION
MOM'"''
NOTE: Pin 20(LE)) must be connected to VSS
L
L
P
A
e
MAXIMUM RATINGS (Voltage, referenced to vssl
Rating
Unit
Symbol
Value
VOO
-0.5 to +,8
Vdc
Input Voltage, AU Inputs
V ,n
Vdc
DC Current Drain per Pin
I
-0.5 to VOO + 0.5
,0
DC Supply Voltage
Operating Temperature Range ~ AL Device
CLlCP DeVice
TA
Storage Temperature Range
T 5t9
PIN ASSIGNMENT
mAde
-55 to +125
-40 to +85
°c
-65 to +,50
°c
•
M
VDD
2'
ST
eEl
23
D out 0
Ce2
22
Din 0
Ce3
21
IE
T
20
D out 1
Din 1
18
Din 2
A'
17
°out2
static voltages or electric fields... however, It is advised that normal precautions be
taken to avoid application of any voltage higher than ma:Klmum rated voltages
to this high Impedance CIrcuit
For proper operatIon it is recommended that
V ,n and Vout be constraIned to the range VSS ~ (V IO or Voutl ~ VOO
Unused Inputs must always be tied to an appropriate logic voltage level (e.g., either
3-20
19
A5
This device contains circuitry to protect the inputs against damage due to high
VSS or \/00·
O.".~
CeramIc Package
PlastIc Package
Extended OperatIng
Temperatufe Range
LImIted Operating
Temperature Range
D out 3
A3
t6
10
Din 3
A2
15
11
WE
A1
,.
12
VSS
AO
13
MCM14552
ELECTRICAL CHARACTERISTICS
Symbol
CharacteristiC
Output Voltaqe
V,n
Vao
V,n
Oar VOO
Or
Voo
Vdc
"0" Level
VOL
50
10
15
"1" Level
VOH
50
10
0
15
"0" Level
Input VOltage '/
IVo
IVo
IVa
·
9.0 or 1 0 Vde)
135 Of 1.5 Vdcl
TVp
Max
Min
Max
Unit
0.05
0.05
005
-
0
0
0
0.05
005
005
-
0.05
0.05
0.05
Vde
495
995
14.95
150r 13.5Vdc)
15
3.0
40
.-
550
825
-
3.5
70
11.0
-
-0.7
-014
-035
-
-11
225
450
6 75
1.5
3.0
40
35
/0
110
215
35
1.0
11.0
-1.2
--1.0
-1.7
50
10
IVOH
13.5 Vde)
15
-025
-0.62
-18
-
-0.2
-05
-1.5
-036
-09
-3.5
5.0
10
15
0.64
1.6
42
-
051
13
34
088
225
88
50
50
·08
-016
-1 7
15
-10
-02
-05
-1.4
5.0
10
052
13
0.44
11
15
36
IOl
IVOl
IVOl
0.5 Vde)
IOl
'.5 Vdc}
Inpul Current (AL DeVice)
I,n
15
Input Current (CLlCP Devlcel
I,n
15
Input CilpaclInnce
01
(V,n
C,n
QUIescent CUlfent (AL DevH.:p.)
100
(Pel PiJ<.:kaqe)
-
50
50
10
15
20
50
10
15
50
100
200
t
IT
50
10
IDynamlc plus QUiescenT.
Per PockiJlje)
1Cl
3.0
• 01
·10
'UI)
(Per Pilckaqe)
Tolal Supply CurrenT"
-04
-12
10
QUiescent CurrenT lel 'CP Devlcel
0.36
0.9
2.4
-
-
mAde
mAde
10
Sink
Vde
-
10H
(VOH 4.6 Vdc)
(VOH - 9.5 Vdc)
135 Vecl
(VOH
04 Vacl
_.
-
mAde
50
46 Vdcl
95 Vdc)
(VOL
1.5
3.0
4.0
10H
IVOH
IVOH
Output Orlve Current (CL/CP Devlcel
25 Vdcl
Source
(VOH
Vde
995
14.95
Vde
5.0
10
15
Sink
4.95
50
10
15
VIH
0.5 or 4 5 Veld
1.0 or 9 0 Vdc}
IVOl 04 Vdel
(Val . 0 5 Velcl
15 Vdcl
(VOL
Thi h-
Min
495
9.95
1495
5.0
10
15
Output Drive Current (Al Devlcel
2.5 Vdd
Source
IVOH
25°C
Max
Vil
4.5 or 0 5 Vdc)
.. ," Level
IVO
IVO
IVa
T 10w
Min
-
088
225
8.8
0.36
09
2.4
--
--
• 000001
-01
• 000001
'10
50
7.5
0050
0100
0150
50
10
20
300
600
0050
0100
50
100
200
375
750
1500
0150
IT
IT
IT
15
-036
-09
--35
-0.6
-0 12
-0.3
-1 0
mAde
'10
j...!Adc
'14.0
.uAdc
pF
150
(1.98 j..IA/kHl) I • IOD
}.lAde
.uAde
.uAdc
13.96 .uA/kH,) I + 100
(5.86 /.IA/kH,1 I • 100
50 pF no all OuTpUTS, <:lll
huffers sWilch,nq)
Three,STatf! Le<'lkaqe CurrenT
ITL
15
· 01
· 0 f)0001
·01
·30
/-lAde
ITL
15
.10
·000001
'1 ()
• 7.5
/-JAdc
(AL DeVice)
Three,SlaTe LC;Jkaqe CurrenT
(CUep Dev,u)
'T low
·55 0 C IOf AL DeVice. -40(JC lor CLlCP Oevlce
Th,qh
1125 0 C for AL DeVice, 185°C for CLlCP DeVice
""NOise Irnmutuly spp-uhed fOf wor!,l-case Input cornlHnilTHJn
NOise ~arqln for bOTh "1" and "0" level
10 Vdt: min (,,) VOO
'50 Vdc
20 Vdc min ('.') VDO
10 Vrlc
25 Vdc min ~!l VOD
15 Vdc
tTo calculate TOlal supply currenT aT loads other Than 50 pF
ITICL)
ITI50 pr) i 4 J( 10-- 3 ICL -50) VOOf
where- IT IS In j.JA Iper PiJckaqe). C L In pF, VOO,n Vdc, and lin kH/lS InpuT frequency
• ·The formulas (Jlven are fOr The tvprc..al characteristics only at 25°C
3-21
MCM14552
SWITCHING CHARACTERISTICS'
ICL" 50 pF, T A" 25 0 CI
~:~;~m:S/PF~:~:~::~~=~-=-~~~~-~r-fi~¥i!~i S:T~~~II~V::'I
tTLH"ll,5ns/pFICL+25ns
tTLH" 11.1 ns/pFI CL + 10 ns
. __ ._ ..__
Output Fall Time
._-1 .... --.--.. -, -1--c-tT- H- L
tTHL" 11.5 ns/pFI CL + 25 ns
tTHL" 10,75 ns/pFI CL + 12,5 ns
tTHL" 10.55 ns/pFI CL + 9.5 ns
Read Cycle Time
" 2
I
._~..
-rl-
I
tcyciR I
i
I Strobe to
1,3
Ad~;~-;-H~d T~e
I
I
tsufA-Sf)
L
I
I
I
l'
i
J-- 2006 - L
t
I
i
. _
~~ J-
100
50
I
40
i
5.0
10
15
1500
450
350
~__
200
100
80
6000
i
t.., _
ns
i
~
ns
-'~;;O -~ ::~~- ~-~sj
~~~- ~ -~~-~
L_
500
-
I
150
_
i
120
ns
I
150
100
75
2,4
tsu(A-eEI
5.0
10
15
1800
600
450
600
200
150
ns
2,4
thiCE-AI
5.0
10
15
450
300
225
150
100
75
ns
Wh"en Reading
1,2
tWLlRI
5.0
10
15
1800
450
350
450
150
100
When Writing
3,4
tWLIWI
5.0
10
15
3600
1800
1350
1200
600
400
-100
-40
-30
Address to Chip Enable Serup Time
I Chip l~;bi~ to Addres~ -H~ld Time
I
I
I
~-=-=~"'"
Strobe or Chip Enable Pulse Width
180
5.0
10
15
f-----
I
I
thIST·AI
I
I Strobe or Ch~E'~~ife Puls~"Wtd'th
15
5.0
90
_+,' ___ ..s5_-+ __
1,3
I
i
5.0
10
;C~C~~I-~ - ~~
f-----=----- --Address to Strobe Setup Time
I
TI__ '~JI ..
I
-- 3 4 -1--
Write Cycle Time
f ~"----r ~::=r::: -I Un~it
10
I
IR";;d" Setup -T'i~e
t~u(R)
f
5.0
15
a
a
ttdAI
5.0
10
15
540
240
180
180
60
45
tw(D)
5.0
1800
600
450
600
200
150
600
150
120
200
50
30
I
10
Read Hold Time
I
f-::-.. - ---
I Data Setup Time
3,4
I
10
I
i- - -.. _-
I Data Hold Time
Y
15
3,4
thllli
I
5.0
10
L_
15
-+-
-':;-s_1
I
~~: -j
:J
i
ns
l
J
I
{contmul-!dl
*The formula given IS for the tYPical characteristics only
3-22
MCM14552
---------,
Ie L
C
50 pF, T A
2SoC) /continued)
T- ~~~~~~~-
F igu re
3,4
I
tsu (WE)
r.w
""-r"";,=e='En~a"'51~e:-:-Ho-'-Id-'-;:T;-m-e- - - - - - - .--.. --- .;- - 3, 4
i
~;d A~~~;~ TIme fr~m-S'~~rob~-'
1
1,3
_
I tacc(A·STI
!
L.
t-
VDD
!
-!
Min
-t-
Typ
5.0
10
15
720
240
180
240
80
55
5.0
10
15
150
60
45
50
20
15
'-----T-!
-
i
ns
I
I
!
I
I
I
ns
----~
5.0
10
15
2000
700
350
6000
2100
1600
5.0
2100
6300
10
15
750
400
2250
1700
5.0
10
15
400
200
150
1200
600
450
ns
5.0
10
15
400
160
120
ns
;
1200
480
360
5.0
10
15
500
200
150
;
1500
:
600
450
I
I
ns
2
ktpu; Enable!Dosabie Delay tram Chop Enable-;'r
\
2,4
tRICE),
tRIW{\
Wr'ite-Enable
r
'Ftiiiie-S,ite Enable/DISable Output Delay
i
[:h~ OutputPropaga"on
Delay
i
--J
--'=-'- _ _ _ ._
/ Read Access T,me from Chip Enable
iI
!
--<
I
• ----.-r---
_1
ns
_1
The formula given IS for the tYPical characteristIcs only.
Din Din Din Din
T
LOGIC DIAGRAM
6
c;>
c;>
M
WE
ST
10
c;>
19
1
-~20¢
-1
"
eEl 23
I
CE222
CE3 21
A5 180
3 to B
00
A4 17
Oecnder
Al
14~
3 00ut 0
01
5
02
02
7 0 out2
03
03
9
01
Memory
A2 15 0
GO
64)( 4
A3 160-----
3 to 8
D out '
Latches
Array
Decoder
AO 13 0
Pin 24
VOO
VSS
3-23
~
Pin 12
1
.. t .___M~~ __ +-_~~.'-
Gout 3
I
MCM14552
FIGURE 1 - READ CYCLE WAVEFORMS UTILIZING STROBE TO ACCESS MEMORY
Add,"" _ _ _
------
~f-
_-I
--'CVdRI--------
t---
',u
(A
51)
th(A
1 5O%_________
ST;-t==
Vaa
VSS
i
- - - - - Vaa
50%
r----- -I
Vss
tWURI __ _
, - - - - - - - - - - Vaa
I
tsu(A)
50%
-~
------i
- - - - - - - - VSS
-----Vaa
La tt': hEriabTe
/
' \ 50%
I'
--------~------------~
--..j 'actlRSTI f----
Data Out
VSS
------1 tee
----------~Xl
90%
_ _ _ _ _ _ _ _ _ _ _ _--'_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~
,~O~%~_
tTLH tTHL
c'r 1, C[2, CE:3 and T are
Notes
WE.
~:
low, M
IS
----1
VOL
50%VO
H
~
high
may t)e held high during the complete rea(~ cvcle
FIGURE 2 - READ CYCLE WAVEFORMS UTILIZING CHIP ENABLE TO ACCESS MEMORY
Ad<:~~'~
Cf;TpTnable
-f
'cvc(RI -
-------I
i---t:--t-(A-t;-E-~-(R-I---------'*~5-0-%-------- ~::
-1-------
<:-E-I
-1------\ '"
1!
'"c(R
\~
C:'_I
____--___
--_-_v:s:
-
Voo
Vss
Data Out
Notes
Unused
c''E. ST,
M and
f are low and WE IS high
High ,,,,penance output state occurs when any
and M
IS
low, or when
T
CE
IS high
The output displays data from the prevIous state
'WUR)
. 'ar:c(R CElrna)('
3-24
IS high
MCM14552
FIGURE 3 - WRITE CYCLE WAVEFORMS UTILIZING STROBE
4===---
Add, ... _ _ _ _ _
'cyclWl
---
~
thIA·ST)
-=1'-________ ~::
, - - - - - - " - - - - - - - - VDD
Vss
r----t------
VDD
Write Enable
---~Vss
,-----j------
VDD
Data In
--4--.....,*~-------E= ~::
Data Out
VOL
Notes:
1 _. CEl, CE2, CE3 and T are maintained at the logical "0" level.
2 -- M is maintained at the logical" 1" level.
3 - The output displays the
c~ntents of the prevIOus state
4 - The output displavs the contents of the presently addressed location as in 8
read modify write cycle
5 - The output displays the data that was written mto addressed location.
FIGURE 4 - WRITE CYCLE WAVEFORM UTILIZING CHIP ENABLE
f-------tcVC(W)----~1
-~*50%
VDD
VSS
,r-----VDD
50%
- - - - - - VSS
Write Enable
Oat. In
r - - - - - - - - - t - - - - - - - VDD
-----+-------t---~'I~-J''---------+_------VSS
r----VOH
Data Out
Note.:
1 - High impedance output state occurs when
is low, for M and
2 - Unused
CE' •. Sf.
T
CE
'----VOL
il high or when WE
maintained in the low state.
M and
T
are maintained at the logica' "0" level.
3-25
MCM14552
TRUTH TABLE
~~~F~""~'."~O~"____+-~C~'~'4-CCE~'~~C~E~J-t~~+-~L~E~~M~+-_S~T~~~W~E-t~D~,"-t~D~O~"'Y-C---~c~O~m~~~"~"---[l"Ul w ,lIl'eaCl 1yp,j')1i
CE
n T
0' " ~'.
0 "nrl
WF.
1
n
1 ,1n,1 T
~"-'''-''-''-L-''-'''-O'-''O)----+-~-~--~~-~:C,--+~~+-----~~'+-~--i-~-+~~+-~-t-D-Oo-,,-w-"'-h-,--;,-:,~-,-,'~i--()-,!"-----
13
0:-;:---------1
,5
[")illa
TRUTH TABLE
ConTrOl
004
Output
Mode
Hlgh·L Not Selected
Hlgh-Z Not Selected
Hlgh-Z Output Disabled
18
X
DO
AS
A6
Hlgh·Z Write
x
A 7
X
DOUI
Read
DS982B/9~80
3-27
MCM5101-MCM51 LOl
MAXIMUM RATINGS (Voltages referenced to Vss Pin 81
Rating
Symbol
Valua
Unit
Vcc
Vrn
- 0.510 + 70
V
DC Supply Voltage
Voltage on Any Pin
Operating Temperature Range
Storage Temperature Range
V
-0310 VCC+0.3
o to
lA
+ 70
'c
-65to + 150
lstQ
This device contains circuitry to protect the in~
puts against damage due to high static voltages
or electric fields; however, it IS advised that normal precautions be taken to avoid application of
any voltage higher than maximum rated voltages
to this high-Impedance Circuit
'c
NOTE' Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded, Functional operation should be restrrcted to RECOMMENDED OPERATING CONOITIOr~S Exposure to higher than recommended voltages tor extended
periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operatmg voitage and temperature range unless otherwise noted)
RECOMMENDED OPERATING CONDITIONS
~PIY VOltage~
s~~rl ~i~
Paramater
::~
~;~
Unit
V
~i-L-o-g-iC-1--V-o-'ta-9-e-,~A-II-I-n-pu-t-s-----------------------------------------+---v~,~H~-r~2~.2--t--------rV~C-C--+~0~.3+---V~~
I
Logic 0 Voltage, All Inputs
VIL
-0.3
-
0.65
V
DC CHRACTERISTICS
Symbol
Characteristic
MCM51 L01-45
MCM51 L01-65
Min Typlll
Max
Input Current
lin 121
-
Input High Voltage
VIH
V,L
2.2
-0
VOH
24
-
VOL
-
-
Input Low Voltage
Output High Voltage IIOH
~
- 1.0 mAl
Output Low Voltage IIOL ~ 2.0 mAl
Output Leakage Current
ICEl
~
ILOl21
22 V, VOL ~O V to VCCI
-
5.0
-
-
MCM5101-80
Min l yp l1J
2.4
-
-
-
04
0.4
--
-
± 10
-
-
± 10
-
-
Vce -t- 03 22
-03
065
24
VCC + 0.3 2.2
-03
0.65
Unit
Max
5.0
-
-
--
-
Max
-
nA
VCC + O.
0.65
V
V
-
V
0.4
:!:
V
~A
2.0
-- - - ' - - -
Operating Current
IVin~VCC,
5.0
MCM5101-65
Min l yp l1J
except CE1,,065 V,
'CC1
--
9.0
22
-
9.0
22
-
11
25
ICC2
-
13
27
-
13
27
--
15
30
mA
ICCL 121141
-
-
10
-
-
200
-
-
500
~A
Min
2.0
0
tRC t,!
Typl1l
Max
-
-
Unit
V
0.14
10
~A
0.70
200
~A
-
-
ns
i
I
ns
I
,
mA
outputs open)
Operating Current
IVrn~2.2
V, Except CE1,,0.65 V,
outputs open)
Standby Current
ICE2,,0.2 V,
Vrn~O
V or VCCI
Characteristic
Input Capacitance (Vin = 0 VI
Output Capacitance {V OUl = 0 VI
LOW VICC DATA R ETENTION CHARACTERISTICS IExeluding MCM5101-801
Parameter
Test Conditions
I
V CC for Data Retention
MCM51 LOl-45, -65 Data Retention Current
MCM5101-65 Data Retention Current
CE2,,0.2 V
I
I
Symbol
VDR
VDR~2.0
V
ICCDRl
VDR~20V
ICCDR2
tCDR
IR
Chip Deselect to Data Retention Time
Operation Recover Time
Notes
,. Typical values are T A = 25°C and nominal supply voltage
2 Current through all inputs and outputs included In ICCL measurement
3 tRC ~ Read Cycle Time
4. Low current state is for CE2 = 0 only
3-28
J
i
J
MCM5101-MCM51 L01
TYPICAL ICCDR vs TEMPERATURE
lOW VCC DATA RETENTION WAVEFORM
r
vee ~ 0 v
eE2 02 v
Supply
Voltage
I 11
(Vee)
v ,n
lOY
;;
tCDR --.,
=
~i
V,H
"u
Chip Enable 0.2 V'\.,,=========
(CE::2)
0 V
III
-
11 01
11
10
lU
JO
1(1
rU-.1PtRATlJRE
\11
611
/11
(IJ[)
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature unless otherwise noted)
+ 0 65 V to 2 2 V
Input Pulse Levels
Input Rise and Fall Times
READ CYCLE
Outpulload
1 TTL Gate and CL = 100 pF
Timing Measurement Refelence Level
1~V
20 ns
----------------------Symbol
Parameter
__________ ______
1---,M,,-~c_:,_5-~rl.;::_;;'::_-:,_~-+-M.M:_;;-~'=~-5T~-,~.~1._:-~c_~-_t-__._M.,C-:M~5:;-0..'o::-80_,,__1 ~~
Min
Max
Min'-j.__::MC'a-:x, _+_.M,-"in"---jl---'M:.:a=x~_j.--::=_+--"-=_+---
-
ns
ns
800
ns
800
400
------t---tC02---5OO--=- -700-t----+~=-+-n·-s--i
850
OUlPUI O>sabl;U;-O~tP~t-----------'aD
-~-- ~250- 350
ns
450
'OF
0
130-(j--r--'50 -0- -c2:-::00
c:---t---n-s- - j
Data Output 10 Hlgh-Z State
Read Cycle
Access T,me
Ch,p Enable (CEll to Outpul
Ch,p Enable (CE21 ,O-Out,;-~,-----------
__ ...'R_~ ~50
-~----'CO'
450
650
650
600
800
---
o--~-~~~o--t--~--~
----------------;:--;--;--;cc----
PrevIous Rea?_~ata _V~wlth Respect to Ad?_~~~han~_.=t__ ~~_~ _
0
f---- ----;;;;-PrevIous Read Data Valid with Respect 10 Chip Enable
tOH2
0
- - -------- - - - ---'----'------''----"----'-----'---'-----
o
3-29
MCM5101-MCM51 L01
READ CYCLE TIMING
r-
I
Address
'RC
------------1
,,,nJE
--+--t('eo, I
__{Iy--I
L..-
IOH2-~
CE2
I
r-=r--==:t
'C02
-t
~---
00
ICommon 1/0)11)
Data
OUI
------I
'oo
'OF
IA
~.>-~.-- ~i
....
It\
-----------------~~~---------Data OiJl Valid
WRITE CYCLE TIMING
,
--- 'we -
1-+
Address ---------'*'--1.___-__-__--_-__-__
r--
'eWl
---------J
---I-~t=
-,
,
l-------I~;r
i
1
CE2
------.J
I
4
i
---...,
I
'eW2
~------------------~--------~---
00
(CC)mrr1[)n I/Oll.;O
'OS
'OH
---
Data In Siable
lAW
RiW
1 ~~r-I
lOW -
________________
,
~--
'WP
Notes
1 00 may bE':: lied low for separdte 1;0 opefallor~
2 During the write cycle. 00 IS "hlgh" for common \/0 ard "don', care" for separate I/O operation
3-30
®
MCM6508
MCM6518
MOTOROLA
1024 x 1 BIT STATIC RANDOM ACCESS MEMORY
The MCM6508 and MCM6518 are fully static 1024 x 1 RAMs
fabricated uSing CMOS silicon gate technology. They offer low power
operation from a single + 5 V supply with data retention to 2.0 V. The
16·pln MCM6508 has a single active low chip enable. The MCM6518 has
two select lines, In additIOn to the chip enable. Both part types latch ad·
dresses with COIP enable The MCM6518 IS especially suitable for
multiplexed bus microprocessors like the MC146805
• Low Standby and Operating Power
•
Single ± 10% 5 V Supply
•
Data Retention \0 2.0 V
•
Fast Access Time
•
Address Lalches
CMOS
(COMPLEMENTARY MOSI
1024 X 1 BIT STATIC
RANDOM ACCESS MEMORY
-'I
•
three State Outputs
•
Fully TTL Compatible Inputs/OulPUIS
.
•
Fully Slatlc Operation
•
Dlreci Replacement For
HarriS HM650SIHM6518
Inlersll IM6508/1M6518
L
"-
C SUFFIX
FRIT SEAL CERAMIC PACKAGE
CASE 620·06
~~ ~
c'"""
Type Number
Package Typical Current
Suffixes
2V
5V
MCM6508·751 MCM65t825
CrP
oI
MCM650830 / MCM65tS30
C/P
I
~A
MCM650S46/MCM651S 46
C/P
1.A
~A
oI
Maximum
Access Time
T emperatu re
Range
250 ns
010 70'C
I ~A
300 ns
1.A
460 ns
o 10
o 10
~A
fRIT SEAL CERAMIC PACKA!1{{ffO
CASE 726·02
Operating
PIN ASSIGNMENTS
70'C
70'C
'E
MCM650B AND MCM651B
FUNCTIONAL BLOCK DIAGRAM
16 VCC
1.
AO
t5
D
Al
14
W
A2
4
A3
t2
AS
A4
"10
A7
Q
MCM650S
13 A9
A6
I.
A5
Vss
MCM651S
IS
S2
t6
D
15
W
14 A9
13
0
Vss
:rJ--
I
.fo' MCM6508
L-E__S_1_s-_2_a_'e_._"_'''_''_'',_'_OO___________________A_O_A__'_A_2_A_3_A_4______
~
VCC
t7
AS
12
A7
11
A6
10 A5
ThiS deVice contains circuitry 10 protect the m
putS against damage due f0 hlQh static voltages
or electriC fields, however. It IS adVised that nor
mal precautions be taken to avoid applications of
any voltage higher than maximum rated voltages
to thiS high· Impedance CirCUit
DS9B29/1()'80
3-31
MCM6508·MCM6518
ABSOLUTE MAXIMUM RATINGS ISee Notel
Note Permanent device damage may occur If ABSOLUTE: MAXIMUM RATINGS are exceeded Functional operation should be restricted to
RECOMMENDED OPERATING CONDITIONS Exposure to higher than recommended voltages for extended periods of lime
could affect device rehablillY
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise notedl
RECOMMENDED DC OPERATING CONDITIONS
Note
1 TYPICdl valuf-!s ,ire TA
2~"C
rind nominal
~l'lJpl\- vOI:aqt~
Max
HO
12 Il
3-32
MCM6508e MCM6518
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range u'lless otherWise noted)
Output Load
0_8 V to VCC - 2_0 V
20 ns
Input Pulse Levels
Input Rise and Fall Times
, - - - - - - - - - - - - - - - - - - - - - - - - - , - - - - - -Svmbol
Parameter
Read or Write Cycle Time
tELEL
tELEH
tEHEL
E;;ai)i;P';I-se Width, Low
Enable Pulse Width, High
Enable Access T1me
Address Setup
~s-,-H-,-o-,-Id-;--------
----------
~Ot~-------------------
Data Hold
1 TTL Gate and CL = 50 pF
Timing Measurement Reference Level
- - - - - - - - - - - - - - - - - -- ------
MCM6S08-25
MCM6S08-30
MCM6S08-46
~
MCM6518-25 +-M
..Ci':M_65T--l"8-~30'___t____,,Mri:C:_M__,65-'-IT8i:-46_::_1 Units
Min
Max
Min
Max
Min
Max
---- 450- - - - r-i3Qns
350
----- 1---460
ns
300
250
100
150
270
ns
I
,1~~i
tWHDX
15V
-0
-1 E,~: Jt~ l
-
0
r -
0--
1
:-----;;~
-
--
~lseWidih
-- -----~==_=_-_-_==_=__=_--==_=__=__=_-_-_--t-:tWLWH-,----;)Or--f-l~-~~O~--~~
Wnle Enable 10 Outpul Disable
tWLOZ
160
- , 180
- ! 285 I ns
Output Dlsable--i6508-0-nlYi------- -------tEHOZ
-160
--=; --i8() - 285
ns
Output Disable 16518 Dnlyl
--------f-r.;S"'H=O"'Z+--- -----,00285
ns
WriteDiSable to OutputEnabie-----------------+-::tW"'-':H'c:O"'X'+160
!-- 180
285
ns
----=--+---,so -
Output En~~!e_l?5OBJ5:riiil--:-_-=':'__
~nalJle-16518-0nlyl _________
tELOX~ I - - _ -----;6() - - --I80-r------::tSLQX
tWLSH
tSLWH
Select to Wnte Pulse Setup
Pulse Hold
seleCtto Wnte
Enable to Write Pulse Setup
~-----------
160
28~_+
ns
r-180-+- - -285 i ---;,~
r-------.=-- -fio
ns
160
160
--27"'0-+----+----,n=-=s:----1
tWLEH
130
160
270
ns
- - - - - - - - - - - - ---'\ELWf:!- ----;-'j() ---~-f---;-§O -~---2"'7"0c--i------+-ns--1
--
Enab:e to Write Pulse Hold
130
130
_ _ _ _ _ _ _ _ _ _ _ _ L-____
_~
_ _L __ _
~~_~
READ CYCLE
~----~--------------IELEL--------------------~
A
E
---~---JI'~-~'~-------~----1
~--------====~*-~----------IELEH--------------~====~IE~H~f~l~==~
-----'1
IWLQZ
o
Q
PrevIous data
I$HOZ
ST
~------~---------------P------------------------LL------------"me Rele,ence _ _
-+-t-11-----+-t---+-f---+-1--+t-+---t2
Time
Reference
-1
0
1
2
3
4
5
r-
~
w
H
H
X
X
H
H
'-L
L
J
H
'--
3
4
TRUTH TABLE
Output
'nputs
L
L
L
H
H
H
X
X
H
A
X
V
X
X
X
X
V
D
X
X
X
X
X
X
X
Notes:
Q
Z
Z
X
V
V
Z
Z
Function
DIsabled
Ao(jress Latched
Output Enabled
OIJtpul Valid
Output Latched
Disabled (Same As 11
Next CYClf~ (Samp As 01
1 MCM6518 selected Dilly II both ~ and ~ are low and deselected 11 either
high ~ and ~ are connected to ton MCM6508
2 The address WithIn the memory WIll change only on failing t
3-33
Sf or 52
's
5
MCM6508-MCM6518
WRITE CYCLE
~'FLAX
A
F'EHfL
~....
;
I
w
~
--
J
'll EH
~
-- -!FlWH~~~"'"
..... IAVEL
Nt·)([
LEHEL_
I4---- I'WLWH
)(
VoIl,(! D,Ha
~!DVWH
IWHQX
I
H !I"
-=1
'AVE,
Vdl,d
J
ISlWH
~
IWLSt-I
/(
-tt---+-t
-+-t--+t---+t-+-to
,
,,,,, R"',,,,'''''----+-t
2
3
4
TRUTH TABLE
Inputs
Time
Reference
I
I
1
I
7
1
W
A
0
Q
H
X
X
X
X
l
X
X
X
Z
Z
Z
Z
Z
Addrf'SS Lolched
Wrl!p Mode
Data Wrillpn
Z
Drsablf':j (Sarn\'-' A.s
Z
Nt.,,;! Cycie (Sarnt-' As 0)
l
Iz
4
;,
Nntp.s
r\1
~
'l
0
I
~1
f,', ~ H
Output
~
",-', ,
l
J
X
X
X
l
X
X
X
i Ih'~1
V
X
X
X
X
V
V
X
X
X
V
S1
011111
S7
3-34
,11,'
;I'~'"
<111(j
Function
Disabled
Wrill-' COflipletpu
{1\'~("f'( To't!
I', ,:I't'l
"
S1 ,1/ S7.<,
5
®
MOTOROLA
MCM65116
Product Previe,",
CMOS
2048 x 8-BIT STATIC RANDOM ACCESS MEMORY
The MCM65116 IS a 16,384-bil SIalic Random Access Memory
organIZed as 2048 words by B-bilS, fabrlcaled uSing Motorola's highperformance silicon-gale complemenlary melal oxide semiconductor
IHCMOS) technology. II uses a design approach which provides the
simple timing features associated With fully static memOries and the
reduced power associated wilh CMOS memories. This means low
slandby power wlthOUI Ihe need for clocks, nor reduced dala rales due
10 cycle limes Ihat exceed access time
Chip Enable lEI controls Ihe power-down fealure. II is nol a clock bUI
ralher a chip conlrollhataffecls power consumpllon. In less than a cycle
time after chip enable lEI goes high, Ihe part automatically reduces its
power requirements and remams in this low-power slandby as long as
Ihe chip enable lEI remains high. The automatic power-down feature
causes no performance degradallon.
The MCM65116 IS m a 24-pln dual-m-line package With the Industry
standard pinout and is pinout compatible With the industry standard
16K EPROM/ROM.
• 2048 Words by 8-BIt OrganIZation
ICOMPLEMENTARY MOSI
2,048xB BIT
STATIC RANDOM
ACCESS MEMORY
~
-
I
- .
,II,
.
I
.'
LSUFFIX
CERAMIC PACKAGE
CASE 716
I
~.
n~t I~;FR'TSEALC ~ :~,I~
',r
' ' ! .':
I' ..
t
CASE 623
PACKAGE
• HCMOS Technology
• Single + 5 V Supply
• Fully Static: No Clock or Timing Strobe Required
PIN ASSIGNMENTS
• Industry Slandard 24-Pln Package
• Maximum Access Time
MCM65116-12
120 ns
MCM65116-15 - 150 flS
MCM65116-20
200 ns
•
13
2:l
VCC
AS
A9
Vi
G
Power DIssipation
80 mA Maximum (Actlvel
15 mA Maximum IStandbyl
A10
• Fully TTL Compallble
• Automatic Power-Down
• Pinout Compatible With Industry Standard 2716 16K EPROM and Mask
Programmable ROM
E
Al
007
006
001
004
BLOCK DIAGRAM
13
VSS
003
PIN NAMES
AO-AlO
OOO-OO?
W
G
t
Vce
VSS
Address Input
Data Input/Output
. Write Enable
Output Enable
. Chip Enable
.Power 1+ 5VI
_..
,Ground
Motorola reserves the nght to mak.e changes to
any product herein to Improve reliability, function or design Motorola does not assume any
liabIlity arisIng out of the applIcatIon or use of
any product or Circuit descnbed herein; neither
does It convey any license under ItS patent fights
nor the flghts of others
NP330/1 HlO
3-35
®
MOTOROLA
MCM65147
'----_____P_r_o_d_"_Ct Prev ie""
______
J
CMOS
I.COMPLIMENTARY MOSt
4096-BIT STATIC RANDOM ACCESS MEMORY
The MCM65147 IS a 4096-bll static Random Access Memory orga
nlled as 4096 words by l-blt, fabricated uSing Motorola's high perfor·
mance CMOS Silicon gate technology IHCMOSI It uses a design ap·
proach which provides the simple timing features associated with fully
static memo"es and the reduced power associated with CMOS
memories. This means low power without the need for clocks, nor
reduced data rates due to cycle times that exceed access times
Chip enable tE) controls the power·down feature_ It IS not a clock,
but rather a chip control that affects power consumption. Arter Egoes
high, Initiating deselect mode, the part automatically reduces Its power
requirements and remams In this low-power standby mode as long as E
remains high
The MCM65147 IS In an 18·prn dualln·lllle package With the Industry
standard pinout It IS TTL compatible In all resrects The dalo <)ut has
the same polarity as the Input data. A data Input and a separate three
state output prOVide flexibility and allow easy OR ties
•
Single + 5 V Supply
•
Fully Static Memory - No Clock or Timing Strobe Requlled
•
Automatic Power Down
•
Low Power DisSipation
75 mW TYPical IActlvel
500 I'W TYPical (Stand~yl
•
Directly TTL Compatible -
-~::-~~
-,
~
r<:
..•.. ---
• .
LSUFFIX
CERAMIC PACKAGE
' C A S E 680
'oJ '
,RIT
I
SEALCC~~:~:~
CASE
PACKAGE
no
,rl'"I((~ll
.
i
_i.__1 _:_ _ _..J
~-------PINASSIGNMENTS
AO ; •
Vee
Al
A6
A2
A7
A4
A9
0
All
All Inputs and Output
•
Separate Data Input and Three·State Output
•
Equal Access and Cycle Time
•
Maximum Access Time
MCM65147-55= 55 ns
MCM65147-70= 70 ns
•
4,096 X 1 BIT
STATIC RANDOM
ACCESS MEMORY
A8
___J
High Density 18-Pln Package
AlO
D
E
VSS
BLOCK DIAGRAM
Aoo---{X::::=JAt
o----a==:J
A2 c>-----Ci\:::=::J
~"O
o
A3 o-----1~===l a:
A4o----DC=j
Vcc=P,nt8
VSS = Pin 9
;;;
0
il
o
Memory Matrix
~'::0 A t l_~-=~N_N_~MEs. __ -Address
I
Chip Enable
Data In
IE
0
~~
64x64
pow::t~;~~ J
ec
A5~-~~===L__~
VSS
.
---------_.
Ground
-~-
----
DO----
Motorola reserves the nght 10 make changes to dny product
herein 10 'fTlpruve rellab!lity. funCllt)(', or deSign Motorol""
does not assume (lny liability anSlI1g out (11 the application O!
A6A7 A8 A9AlOA1t
use of any
p~odUCl
or CIrCUli described herein, neither does
II convey <'Iny license undtll ,IS Di:llf>n\ (lghTS nor the rights of
alhp.f:';
NP328/tl-80
3-36
®
MOTOROLA
MCM65148
Product Prev ie,""
CMOS
4096-BIT STATIC RANDOM ACCESS MEMORY
(COMPLEMENTARY MOS)
The MCM65148 IS a 4096-blt Random Access Memory organized as
1024 words by 4-blts, fabricated uSing Motorola's high-performance
silicon-gate complementary metal oXide semiconductor IHCMOS)
technology. For ease of use, the device operates from a single power
supply, IS directly compatible with TTL and reqUires no clocks or
refreshmg because of Its fully statiC design. Data access IS pa'llcularly
simple, Since address setup times arp not required. The output data has
the same polarity as the input data
The MCM65148 IS designed for memory applications where simple Interfacing IS the design obJective. The MCM65148 is assembled in an
18-pin dual-m-line package wllh the mdustry standard pmout A chip
enable (E) lead allows easy selection of an individual package when the
three-state outputs are OR-tied.
•
4096-BIT STATIC
RANDOM ACCESS MEMORY
~"~lll ) S[~c
~
II "'>'"
FLR"
'A(,AGE
:"ASf ;26
1024 Words by 4-811 Organization
• HCMOS Technology
• Single + 5 V Supply
• No Clock or Timing Strobe Required
• Industry Standard 18-Pln Conflgurallon
• Maximum Access Time
MCM65148-70 - 70 ns
MCM65148-85 - 85 ns
•
Automatic Power Down
•
Power DiSSipation
200 mW TYPical (Activel
100 ~W TYPical (Standby)
PIN ASSIGNMENT
I\b
f"Ti\-Ti'B
• Fully TTL Compatible
00
11
A·
• Common Data (nputs and Outputs
• Three-State Outputs for OR- Ties
A4
Ib
A8
,
A][ -,
All
Al
A2
BLOCK DIAGRAM
Vcc
P'I; 18
vss
Pill
r
9
\Iss
AO A9
W
E
001 004
VCC
VSS
lJOI
.,
V('l
'0 A9
14
lJO'
"
11
DO:?
I
'2
UO~~
11
D04
'0
W
H
Address Input
\.'V~I!e
Enab:p.
Chip Selec1
Data Inpul, Output
Powerl+'5VI
Ground
Motorola reserves the right to make changes to
any product herein to Improve reliability, 'unction or design, Motorola does not assume any
liability arising out of the application or use of
any product or Circuit described herein; neither
does It convey any license under Its patent rights
nor the nghts of others
NP331/1 t-80
3-37
@
MOTOROLA
CMOS LSI
1024-81T READ ONLY MEMORY
ILOWPOWER COMPLEMENTARY MOSI
The MCM 14524 is a complementary MaS mask programmable
Read Only Memory IROMI. TillS deVice IS ordered as a factory spe·
cial with its unique nattern specified by the user
This ROM is organized in a 256 x 4,ult pattern. The contents of
a specified address 1< AD, A 1, A2, A3, A4, A5, A6, A7 >1 will
appear at the four data outputs lBO, B 1, B2, B31 following the
negative going edge of the clock. When the clock goes high, the data
1024-81T
(256 X 4)
READ ONLY MEMORY
_. . 1_.
present at the output will be latched. The mf~mory Enable may be
taken low (lsynchronously, forcing the oatd outputs low and reset·
ting the output latches. This device finds dpplicdtioll wherever low
power or high noise immunity is a deSign consiueration.
•
J,Iii - ,
~,ode Protection on All Inputs
,,"
,l
45~" of VDD tYPical
•
Noise Immunity
•
Quiescent Current
•
Single Supply Operation - Either PositIVe or Negative
•
Memory Enable Allows Expansion
10 nA/package tYPical @ 5 Vdc
.
.l \
\ . :
" ~
L SUFFIX
P SUFFIX
CERAMIC PACKAGE
PLASTIC PACKAGE
CASE 620
CASE: 648
ORDERING INFORMATION
•
Output Latches Provide a Useful Storage Register
•
Supply Voltage Range
•
Capable of Driving Two Low power TTL Loads, One Low power
Schottky TTL Load to Two HTL Loads Over the Rated Temper·
c
. . .'
l
3.0 Vdc to 18 Vdc
MC14xxx
ature Range
I
_J
SU~f':e,:~,~~f::".ge
~
P
J\
PlaSllt Package
f: I,1 t"
"v'.
: :' ~:,:" ::-=-,=~i-~,=,_~[-"_,_._- - - f-:- -'~- '.~- :)'
""'11)'_""0'"
-----
OLl'
, ' 1·.'1111'
II
i
--'~-
1I0}fdgl'~
1',,'
H"
'~--~~~--,-
-.-- ..
~--.,--
or VOOI
.__________ L_.~~~i
I),,,.• ·."
1
"
.1
"
1 !
I
.,
"
:..:
" II>
• T low
Thlqh
~50C lOt AL D~v'CI:
howt~vl"f.
It IS
advised that
to ,h'$ high Ifllpr.'dt1nl..'i' nrCI/I(
appropr. I i< Add""'> I
OUTPUT DATA
BINARY TO HEXADECIMAL CONVERSION TABLE
LATCHES
0
X
x
1
BO
I
0
I
0
I
0
0
Care
t
'Ind,cates Cl,)nrents 01 spectf,erj Address
w;11 ap~)ear
BINARY
WORD
CARD
DESIRED CHARACTER
at outputs as stated above
(J
()
fT'lt~\flod$
Two
may be us..,d to transnllt the custom
m~!mory
~:i)ttefn to Motorola
0
(1
()
)
U
i
I
')
1
()
METHOD '" PuNCHED COMPUTER CARDS
A b:llarv
be punched
U 0
0 1
I)
1
~
._----.J
i
I
;:,-'_':~'j t~!·CIIr:.·,' ,-t;t:I'.''::;\!llt
1:1 ·"li1'-:i;'.~c;
f'H all 2SG words)
';';"':Itp(
In . ,;IlW~I(.dl
per card are punched
of I~ach de~lr.'d Qlltput nlay
ciJrds (tour cards <.Ire rt'qulred
()
Iword numberl order
li\ COitH'flf',S
12··thru 75
USlIlg
the
I
64 ...... ords
BH1dry
L'
()
I
:
1.1
{)
to
tabie. Columm 77 and 78 are used
to nurnber thp card:>, which IllU'3t OI! H' fllimerical ordpr Please
use characters as ~hOW,l In the tabli~ wh\~fl pdllr:hllig computer cards
Hexadecimal
U
converSion
ROM SAMPLE WORD PROGRAMMING FOR PUNCHED CARD
SAMPLE WORD
OUTPUTS
ADDRESS INPUTS
WORD
NUMBER
Al
[)
1
2
J
I
A6
';0
A4
AJ
A2
AI
a
a
a
o
a
a
a
a
a
0
a
o
o
0
1
0
a
a
{)
AO
o
B3
I
o
o
o
1
o
B2
o
B1
I
C.l\RD
BO
CHARACTER
o
J
J
o
o
l
Shown In colurnns
,.12
,
150ncard
below
I
I
I
A
0
Card
N°_I
WORD NUMBER
000
00000000000100111111111111111111111111111111111111111111111111111111111111101
JI JI j,
€: "
I
I
I
I
I
I
I I
I II II II Ij II 1~ II 'I II I' JIll ~')) 'I l~ II 11 11 "
)1 II )1 JJ J. )1 jl
II II "() II I I " I; II It ~ I' 1/ II II II )I Ii II ~. 10~' '.'
.1 ",: 61., II
~ 'I :1
'j
'I ;1 'I ., II
11 I I 1111 I 111 I I 1 1 1 1 I 1 I 1 1 I 1 1 1 1 111 1 1 1 1 1 I 1 1 1 I 1 I I 1 I I I I I I I I I I 1 I I I I I I I I I I 1 I I I I I I I I I III I
22222222222222222222222222211111111221211121111111212112222211111111111211111111
3 3 3 33 3 3 3 3 3 3 3 . . 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 J 3 J 3 J 31 J 3 J 3 J J 3 3 3
444 44 44 4 44 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 44444444444444444444444444444444444444
5555555555555555555555555555555555555555555555555555555555555555555555;555555555
6 6 6 66 6 66 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 G6 6 6 6 6 6 6 6 G6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 G6 6 6 6 6 6 6 6
11111111111111 1111 11 111 11111 1 11 111111 11 1 1 11 ).1 1111 ) 1 ) ) ) ) ) 1 ) ) ) 1 ) 1 ) ) ) 11 ) ) I 1 ) ) ) ) ) ) ) )
I I 8 . . . . . . I I 8 8 B8 B B B8 8 8 8 8 8 8 8 8 I 8 8 8 a 8 8 8 8 B8 B, B B8 8 8 8 8 8 6 8 8 8 6 S 8 6 8 8 8 8 B8 B B 8 8 8 8 8 8 ! 8 B8 8 B8 8 8 8
9999999999999999999999999999999999999999999999999999g939999999999999999999999999
I I
GLOI!l
~0
,
.1 'I
I ' I I, : \ ' I . I ,. "
,~ II II ; I '. ", : i ,! II "
II : I II !) : I 1\ "
.' il !i I~ II I; I, 10 .', Ii I' Ii 11 )~ ;, I, I' "
;
3-42
~. 'I .'
MCM14524
METHOD B: TRUTH TABLE
For customers who do not have access to punch cards, Motorola
will accept Truth Tables. When filling out the table, use the 0 to F
hexideClmal character in column "e".
CUSTOM PROGRAM for the MCM14524 Read Only Memory
WORD
0
1
2
3
4
C
WORD
51
52
53
54
55
5
6
7
56
57
8
9
10
11
12
13
14
15
16
17
18
59
60
61
62
63
64
65
66
67
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
58
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
C
WORD
C
WORD
C
WORD
102
103
104
105
106
153
154
155
156
157
204
107
108
109
158
159
209
210
160
161
162
211
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
205
206
207
208
163
164
165
166
167
168
169
170
171
212
213
214
215
216
217
218
219
220
221
222
172
173
174
223
224
225
175
176
177
178
179
180
181
182
183
226
227
184
185
228
229
230
231
232
233
234
135
136
137
186
187
188
235
236
237
238
239
138
139
140
141
189
190
191
192
240
241
242
243
142
143
144
145
146
193
194
195
196
197
147
148
149
150
151
152
198
199
200
201
202
203
244
245
246
247
248
249
250
251
252
253
254
255
3-43
C
@
MOTOROLA
MCM65516
Advance InforIllation
CMOS
ICOMPLEMENTARY MOSI
2048 x 8 BIT READ ONLY MEMORY
The MCM65516 IS a complementary MOS mask programmable byte
organized read only memory {ROMI The MCM65516 IS organized as
2048 bytes of 8 OltS, designed lor use In muitlplex bus systems It IS
fabrrcated uSing Motorola's Sl:,con gate CMOS technology, which of
fers low-power operation from a single 50 volt supply
The memory IS compatible with CMOS microprocessors that share
address and data lines Compatibility IS enhanced by pins 13, 14, 16,
and 17 which give the user the versatility of selecting the active levels of
each. Pin 17 allows the user to choose active high, aCTive low or a third
option of programmrng which IS termed the "MOTEL" mode If this
mode IS selected by the user, it provides direct compatibility with either
the Motorola MCl46805E2 or Intel 8085 type microprocessor serres, In
the MOTEL operation the ROM can accept either polarrty Signal on the
data strobe Input as long as the Signal toggles dunng the cycle, This
unique operational f~ature makes the ROM an extremely versatile part.
2048 X 8 BIT
MULTIPLEXED BUS
READ ONLY MEMORY
'?~~~~f{ffr7
\ j'J ~ :
~
L SUFFIX
CERAMIC PACKAGE
CASf 68006
• 2K x 8 CMOS ROM
• 3 to 6 Volt Supply
•
Access Time
430 ns {5 VI MCM65516-43
550 ns {5 VI MCM65516-55
•
Low Power'Dlsslpatlon
30 rnA Maximum (Actlve l
50 I'A Maximum (Standbyl
•
Multiplex Bus Dllectly Compatible Wltl1 All CMOS Microprocessors
iMCl46805E2, NSC8001
PIN ASSIGNMENTS
AUO
~~vcc
AOI
A02
3
17
pc,'
t6
pl
•
Prns 13, 14, 16, and 17 are Mask Programmable
•
MOTEL Mask Optron Also Insures Dllect Compatibility with NMOS
Microprocessors Like MC6803, MC6801, 8085, and 8086
A04[ 5
14
•
Standard 18 Prn Package
;.\05
13
E
A06
12
AIO
AQ)
1t
A8
VSS
10 A8
AQ3[ 4
AOO,AOl
BLOCK DIAGRAM
15 pM
PS
E
Sf
G
PIN NAMES
AGO-A07
A8,A 10
M .
E
S
G
M---
S
Ad(jress/Dala Output
. Address
Multiplex Address Strobe
Ch,p Enable
Chip Select
.Data Strobe ,Output Enable)
Disables
Output Buffers
E, E Llrnlt
Power O:sslpal'on
ThiS device contains CirCUiTry tu protect
ROM Array
the Inputs agamst. damage due to high
sla11(, voltages Of electflc fields, however,
1128x 1281
It 15 advised that normal preCi::Iul10ns be
taken to aVOid application of any VOltage
higher ttlan maXilllum rated voltages 10
Ibis rllgh-lmpeda11ce ClfCUI;
ADI854/9-80
3-44
MCM65516
ABSOLUTE MAXIMUM RATINGS ISee Notel
Rating
Symbol
Supply Voltage
Value
o 3 tu--
Vcc
Input Voltage
Vm
Operating Temperature Range
TA
Storage Temperature Range
Unit
+
70
-- 0 3 to + 7 0
o 10
+ JO
V
"e
-65 to +150
TstQ
V
'c
NOTE Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exc:eeded FlJnctlonal operation should be restncted to
RECOMMENDED OPERATING CONDITIONS Exposure to higher than recommended voltages for extended periods uf time could al·
feet device reliability
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherWise noted)
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Nom
Max
Unit
Vce
45
50
55
V
Input High Voltage
VIH
VCC - 2 0
5.5
V
Input Low Voltage
VIL
-- 03
--
08
V
Supply Voltage
IV CC must be applied al least 100 J,L~ before proper device operation
IS
achieved)
RECOMMENDED OPERATING CHARACTERISTICS
Characteristic
MCM66616-43
Symbol
MCM66616-55
Unit
Test Condition
Min
Max
Min
VOH
Vce- OAV
-
Vec-04 V
VOL
-
0_4
-
OA
V
Supply Current (Operattng)
ICC1
-
30
-
30
rnA
CL - 130 pF, V," - VIH to VIL
tcyc= 1.0 ~s
Supply Current IDC Actlvel
ICC2
-
100
-
100
~A
Vin - Vee to GND
Standby Current
IIS6
75
~A
V,n - VCC to GND
- 10
+10
~A
-10
+ 10
~A
Output High Voltage
Max
v
Source Current - 1,6 mA
Output Low Voltage
Sink Current + 1.6 mA
Input Leakage
Output Leakage
CAPACITANCE
50
lin
-10
IOL
-10
+ 10
+ 10
(f= 1 0 MHz, TA-=25 vC periodically sampled rather than 100% tested)
I
I
Characteristic
I Input Capacitance
Symbol
I
C,n
If--:cO-'u-=tp':'u-=t-=c:::a:'':p':'ac-=,t-a:'':n':'ce-,------------~-----------------------111-- Cout
I Max I Unit
I :, I
I 1251
of
pF
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherWise noted I
READ CYCLE
CL = 130 pF
MCM66616-43
Symbol
Parameter
MCM66616-s6
Address Strobe Access Time
tMLDV
Min
-
Read Cycle Time
tMHMH
580
-
725
Multiplex Address Strobe High to Multiplex Address Strobe Low (Pulse Width)
tMHML
150
175
Data Strobe Low to Multiplex Address Strobe Low
'GLML
50
--
Multiplex Address Strobe Low to Data Strobe High
tMLGH
100
160
Address Valid to Multiplex Address Strobe Low
tAVML
50
50
Chip Select Low to Multiplex Address Strobe Low
Multiplex Address Strobe Low to Chip Select High
Chip Enable Low/High to Multiplex Address Strobe Low
Multiplex Address Strobe Low to Address Don't Care
50
- - ~.l.ML
-
tMLSH
50
tELML
tEHML
50
50
Max
430
-
- ---
Min
~
50
ns
-
ns
-~
ns
--
ns
ns
ns
~-
~
ns
50
50
ns
50
80
tGHDV
175
200
Data Strobe Low to Hlgh-Z
tGL.DL
Data Strobe High to Address Don't Care
tGHDX
3-45
550
80
Data Strobe High to Da1a Valid
160
-~
Unit
Max
50
tMLAX
2 0 - r-----
.--
20
--
ns
ns
100- ~
-
ns
MCM65516
~-------I
READ CYCLE TIMING
IMHMH (Redd Cycle
,
!.---I
'''Hi'.':
llfTl£:)
-------------+{
---.j
!
'/ -,
A8
:,~,
Ail'
AGO :0 AQ1
V,H
V'L
~~l8~~~~:8§8~~>< I'---+-J >--------<'X>
Dor'~
Care
~-~---!MLDV------~~
FUNCTIONAL DESCRIPTION
of address strobe. Address strobe has a mrnlmum pulse
Width requirement since the Circuit is internally pr8charged
dunng this time and IS setup for the next cycle on the trading
edge of address strobe. Access time IS measured from the
negative edge of address strobe
The part IS eqUipped With a data strobe Input IGI which
controls the output of data onto the bus Irnes after the addresses are off the bus. The data strobe has three potential
modes of operation which are programmable With the ROM
array. The first mode IS termed the MOTEL mode of operation. In thiS mode, the Circuit can work With either the
Motorola or Intel type microprocessor series. The difference
between the two senes for a ROM peripheral IS only the
polarity of the data strobe signal. Therefore, In the MOTEL
mode the ROM recognrzes the state of the data strobe signal
at the trailing edge of address strobe Irequ"es a setup and
hold tlmel, latches the state Into the CIrcuit after address
strobe, and !Urns on !he data outputs when an opposite
polarity signal appears on the data strobe Input. In this manner the data strobe input can work With either polarity Signal
but that Signal must toggle dUring a cycle to output data on
the bus Irnes. If the data strobe remains at a d.c level the
outputs Will remain off. The data strobe Input has two other
programmable modes of operation and those are the standard static select modes Ihlgh or lowl where a d.c. Input not
synchronous With the address strobe will turn the outputs on
or off
The chip enable and chip select Inputs are all programmable with the ROM array to either a high or low select. The
chip select acts as an additional address and is latched on the
address strobe trailing edge. On deselect the chip select
merely turns off the output drivers acting as an output
disable, It does not power down the chip The chip enable rnputs, however, do put the chip rn a power down standby
mode but they are not latched With address strobe and must
be maintained ,n a d.c. state for a full cycle,
The 2K x 8 bll CMOS ROM IMCM655161 shares address
and data lines and, therefore, IS compatible with the malority
of CMOS microprocessors In the Industry The package size
IS reduced from 24 pinS for standard NMOS ROMs to 18 pins
because of the multiplexed bus approach The savings In
package size and external bus I!nes adds up to tighter board
packing density which IS handy for battery powered hand
carned CMOS systems ThiS ROM IS designed with the intention of having very low active as weI' as standby currents
The active power dlsslpallon of 15C mW fat VCC = 5 V
freq = 1 MHzl and standby power of 25C ~W lat VCC = 5 VI
add up to low power for battery operatIon, The tYPIcal access time 01 the ROM IS 200 ns making It acceptable for
operation With today's eXisting CMOS microprocessors
An example of thiS operation IS shown 1/' Figure 1 Shown
IS a tYPical connection with either the Motorola MC146805E2
CMOS microprocessor IM6BOO serres) or !he Na!lonal
NSCBOO which IS an 8085 or ZOO based system The main difference between ttle systems IS ttlal Ihe dala s\robe IDSI on
the MCl46805E2 and ttle read bar IRDI on the 8085 both
control the output of data from n'8 ROM but are of OPPosite
polarity The Motorola 2K x 8 ROM can accept either polanty
Signal on the data strobe Input as long as the signa! toggles
dUfing the cycle ThiS IS termed the MOTEL mode of operation ThiS unique operational feature makes the ROM an extremely versatile pan Further operational features are explamed In t~le foiioWlflg section
Operational Features
In order to operate In a multiplexed bus sytem the ROM
latches, for one cycle, the address and chip select Input tnformation on the trading edge of address strobe IMI so the
address Signals can be taken off the bus
Since they are latChed, the address and chip select Signals
have a setup and hold time referenced to the negative edqe
3-46
MCM65516
FIGURE 1
TYPICAL MINIMUM SYSTEM - MOTOROLA
lAO
LI
Microprocessor
MCl46805E2
High Order Address Bus 151
Bus Control Signals (3)
TYPICAL SYSTEM - NATIONAL
v
C
~
~ ~~
r01
Xl
_BREO
X2
~,..----~
....,+-~--+-J
RESET
A8- A15
A12 A13
NSCaoo
I
ADO-AD?
_
~
t-__--,
4 - - BACK
_WAIT
Man~set
INTA
INT
K;==
ALE
RDt----i
_NMI
,---~A
WR
_~B
IO/"Mt-----I
_RSTC
RFSH
CLKt----i
SO _
_
_1'5
A13
/I
t-----"..-----.---r---.--......-----.).
~r~~_+~--~~~~------_
-
Sl_
RESET OUTI----i
1!
u
>
z
co
r--
VV
A8-A 10 AOO-AQ7
VCCGND-
,
M
G
2K x 8 ROM
MCM65516
3-47
E
, 1
S
CE
~ToIN
I
ADOAD7
~
I@
I~
4:
Muxed RAM
To OUT
PA
PB
of:3~
I:::;
-
a:
PC
MCM65516
CUSTOM PROGRAMMING
InformatIon for custom memory content may be sent to
Motorola In one of two forms (shown In order of preferencel:
By the programming of a single photomask for the
MCM65516 the customer may specify the content of the
memory and the method of enabling the outputs, or selection of the "MOTEL" optIOn IPm 171.
Information on the general options of the MCM65516
should be submitted on an OrganIZational Data form such as
that shown m the below figure
1 Magnetic Tape
9 track, 800 bPI, odd panty written In EBCDIC character code Motorola's R.O.M.S format.
2 EPROMs
One 16K IMCM2716, or TMS27161
FORMAT FOR PROGRAMMING GENERAL OPTIONS
ORGANIZATIONAL DATA MOS READ ONLY MEMORY
Customer"
Company ___________________________________
Motorola Use Only
Part No ___________________________________
Originator ___________________________________
Ouote. _____________________________
Part No
Speci/. No .. _________________________
Phone No ---------------------------
Programmable Pin Options
13
ACllve
Low
14
15
17
u
[J
[J
[]
[j
MOTEL 0
3-48
Bipolar Memories
TTL, MECL-RAM, PROM
4-1
@ MOTOROLA
MCM93415
1024-BIT RANDOM ACCESS MEMORY
The MCM93415
TTL
1024 X 1 BIT
RANDOM ACCESS MEMORY
a 1024-bit Read/Write RAM organIZed 1024
IS
wOlds by 1 bIt.
The MCM93415 IS deSIgned for butler control storage and hIgh
performance main memory applications, and has a typical access
tIme of 35 ns.
The
MCM93415
has
full
decodIng
on-chip,
separate
data
Input and uatd output lines, anrl an active low chip select. The
deVIce
IS
fully
compatIble
With
standard
F SUFFIX
DTL anrl TTL logiC
CfRAMIC PACKAGE .....
families dnd features drl uncommitted collector output for ease
•
Uncommitted Coi(ector Output
•
TTL Inputs and Output
•
Non-Inverting Data Output
•
High Speed
Access Time - 35 ns TYPical
Chip Select·
~.
_
.'
16!
15 no TYrlcal
•
Power Dissipation Decred58s \.vlth Increasmg Temperature
•
Power DISSIIJatlon 0.5 mW!Bit TYPical
•
Olganlled 1024 Words X 1 Bit
_.~
__ ~. _..
_r_-_;~:_~'_:::<._
--."
CASE 6 5 0 . r :
of memory expdnSlon
1
f
,f
:
'
I"
:
D SUFFIX
CERAMIC PACKAGE
CASE 620
-
..
BLOCK DIAGRAM
P SUFFIX
PLASTIC PACKAGE
CASE 648
Sense Amp
and
Write Drivers
PIN ASSIGNMENT
16
Wor(J
Drivers
I.
15
32 X 32
Array
14
WE
13
12
c-s
"
10
15
D,n
1 of 32
1 of 32
Decoder
Decoder
PiQ Designation
CS
AD - A9
13
AO
A 1 A2 A3 A4 A5 A6 A 7 AS
A9
Address Inputs
Write Enable
Vee - Pin 16
Gnd . Pin 8
Data Input
D out
4-3
Chip Select
Data OutPut
MCM93415
FUNCTIONAL DESCRIPTION
The MCM93415 is a fully decoded 1024-blt Random Access
Memory organized 1024 ......ords by one bit. Bit selection IS
achieved by means of a 1 O·blt address, AD to A9.
The Chip Select input provides for memory array expanSion.
RL
IS In
kit
FO "" number of TTL Unit Loads lUll driven
ICEX "'- Memory Output Leakage Current
VOH -= RequlTeu Output High Level at Output Node
system performance
The read and write operations are controlled by the state of
(WE.
VCCIMIIl)-VOH
nllCEXJ + FOIO.041
number of Wired-OR outputs tied together
For large memories, the fast chip select access time permits the
decoding of Chip Select (Cs) from the address Without affecting
the active low Write Enable
VCCIM,nJ
IOL - FOll.6J
IOL
Pin 14). With WE held low and
c
Output Low Curnmt
the chip selected, .t~ data at Din IS written Into the addressed
toeatlon. To read, WE IS held high and the chip selected. Data 111
The minimum RL value
the specified locatron IS presented at DouT and IS non-HlVerted
abtllty. The maximum RL value
at VOH. One Unit Load
OR applications. In any application an external pull·up reSistor of
d
hlyh at the output when
1<;
determined by the output and
input leakage current which must bf~ supplied to hold the output
Uncommitted collector outputs are provided 10 allow Wired
AL value must be used to provide
limited by output current slnkmg
IS
c-
40 p.A Hlgh/I.G rnA low
It IS
off. Any RL value Within the range specified below rTlily be used
ABSOLUTE MAXIMUM RATINGS (Note II
TRUTH TABLE
Inputs
Storage Temperature
Ceramic Package ID and F Suffixi
- 55°C 10 + 165°C
PlastiC Package IP SuffiX)
- 5S0C 10 + 125°C
Open
Operating Junction Temperature, T J
Ceramic Package (0 and F SuffiX)
165°C
125°C
PlastiC Package (P SuffiX)
- O. 5 V to + 7.0 V
V CC Pin Potential to Ground Pin
Output
C$
WE
Om
Collector
Mode
H
X
X
H
Not Selected
L
L
L
H
Write ·'0"
L
L
H
H
Wnte "1"
L
H
X
DOll!
Read
-0.5Vto-+55V
Input Voltage (dc)
Voltage Applied to Outputs (Output High)
H '- High Voltage
-0.5 V to 15.5 V
L .= Low Voltaqe Level
120 rnA
Output Current (dc) (Output Low)
U~vel
X
Don't Care (High
01
Low)
-12 rnA to 15.0 rnA
Input Current Idc)
NOTE 1: DeVice damage may occur If ABSOLUTE MAXIMUM RATINGS .H(~ e)(Ct~eded
GUARANTEED OPERATING RANGES (Note 2)
Supply Voltage (Vee)
Part Number
Min
MCM934150C, PC
4.75 V
MCM93415FM, DM
4.50 V
I
I
I
Nom
5.0 V
5.0 V
I
Ambient Temperature (T A)
Max
I 5.25 V
I 5.50 V
DoC 10
- 55 0 C 10
75()C
t
t
125 0 C
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operatIng voltage and temperature range unless otherWise noted)
Limits
Symbol
Characteristic
Min
Max
Unit
0.45
Vdc
Conditions
VCC ~ Mm,IOl ' 16mA
VOL
Output low Voltage
VIH
Input High Voltage
VIL
Input Low Voltage
0.8
IlL
Input low Current
-400
.uAdc
Vec"" Max, V ln
0.4 V
IIH
Input High Current
40
}JAdc
Vce~: Mux, V tn
·4.5 V
1.0
mAdc
VCC·- Max, V,n·- 5.25 V
ICEX
Output Leakage Current
100
}.lAdc
VCD
Input Olode Clamp Voltage
-1.5
Vdc
ICC
Power Supply Current
130
mAdc
155
mAdc
T A - ODC
170
mAdc
TA"" Mill
2.1
4-4
Vdc
Guaranteed Input High Voltage for All Inputs
Vdc
Guaranteed Inpui Low Voltilge for All Inputs
VCC ., Max, V out -45V
VCC
~
Max, lin
~
-10 rnA
I
TA - Max
l
I
VCC
-=
Max,
All Inputs Grounded
MCM93415
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature unless otherwise noted)
AC TEST LOAD AND WAVEFORM
Input Pulses
Loading Condition
All Input Pulses
>-.--<
3
,,--------,.,
5~VD~;I
_
300 H
- -- - --
--~~ - - 90:
: :
Gnd':'"......,
,.......10n$
,
MCM93415
3~ ~
30 pF
Capacitance
60012
--:-r:1~10ns
( Inclucllng
0
: I
__
Gnd-:- ---4
1--10n5
',-----
~I,
-1~ _
- - - -- - - -
"' v_p ~)~" _ _ _ _ _ _ _
Scope and Jig}
0
~\-_'OI'
1- _ _ _ _ _ _ _ _
--10%
-90%
I'~10ns
~
MCM93415DC. PC MCM93415DM.FM
Symbol
Characteristic (Notes 2. 3)
READ MODE
Min
Ma.
Ma.
Min
Unit
Conditions
ns
DELAY TIMES
tACS
Chip Select Time
35
45
See Test Circuit
tRCS
Chip Select Recovery Time
35
50
and Waveforms
'AA
Address Access T'me
45
60
WRITE MODE::
ns
DE LA Y TIMES
'W5
Write Disable Time
35
45
'WR
Write Recovery Time
40
50
See Test Circuit
and Waveforms
ns
INPUT TIMING REQUIREMENTS
30
40
See Test Circuit
'WSO
Data Setup T irne Prior to Write
5
5
and Waveforms
tWHO
Data Hold TIme After WrIte
5
5
10
15
10
10
'W
Write Pulse Width (to guarantee write)
tWSA
Adclrcss S€tup TIme (at
tWHA
Address Hold Time
tw
Min}
twscs
Chip Select Setup Time
5
5
tWHCS
Chip Select Hold TIme
5
5
READ OPERATION TIMING DIAGRAM
Propagation Delay from Address Inputs
Propagation Delay from Chip Select
AO-Ag--y
Addre~,-_ _ _ _ _ _ _ __
I
~~~at Output - - - - . . . : . . . . - - ,
I
1 A C5
\'---i----,r
Dout
Data Output
I
-----t-----i
(All Time Measurements Referenced to 1.5 V)
4-5
MCM93415
WRITE CYCLE TIMING
cs
Chip Select
'\
r
I
I
~~d':'~'_n_p_u_"___....:__-J~
~~a
~
)f(. .---t-[____
l:i
Input
_ _ _ _- I -_ _+--J
1---,\
W-E
Write Enable
D~ut
I
I
I
tW---Ijg I
'WHol
I
'---tWHA---I
ItWSD~
I
I
I
I
I
~tWHCS~
I
111
f--tWSA.......,.j
i
Data OutPut
t----twscs---l
______________________
-+I__- J
\1
II
I
~
______________
I
I
tws -+--------I
r------t-- tw A
(All Time Measurements Referenced to 1 5 V)
NOTE 2
DC and AC Specifications I,mlts guaranteed with 500 linear feet per minute blown air Contact your Motorola Sales Representative
d extended temperature or moddled operating conditions are deSired
1/ JA
(Junction to Ambient)
Package
Blown
D Suffix
50 0 CIW
85 0 CIW
15 0 CIW
F Suffix
55 0 CIW
90 0 CIW
15 0 CIW
P Suffix
65 0 CIW
100 0 CIW
25 0 CIW
Still
/J JC (Junction to Case)
NOTE 3. The AC limits are guaranteed to be the worst case bit In the memory
4-6
®
MCM93425
MOTOROLA
1024-BIT RANDOM ACCESS MEMORY
The MCM93425 is a 1024-bit Read/Write RAM, organized 1024
TTL
words by 1 bit.
The MCM93425 IS designed for high performance main memory
and control storage applications and has a typical address time of
35 ns_
1024 X 1 BIT
RANDOM ACCESS MEMORY
The MCM93425 has full decoding on-chip, separate data input
and data output lines, and an active low-chip select and write enable.
The device is fully compatible with standard DTL and TTL logic
families. A three-state output is provided to drive bus-organized
systems and/or highly capacitive loads.
F SUFFIX
CERAMIC PACKAGE
CASE 650
Three-State Output
•
•
TTL Inputs and Output
•
Non-Inverting Data Output
•
High Speed Access Time - 35 ns Typical
_
Chip Select - 15 ns TYPical
'. I
•
Power Dissipation - 0_5 mW/Bit Typical
•
Power DISsipation Decreases With IncreaSing Temperature
.
.r,
r I : .' ,.
,'
D SUFFIX
CERAMIC PACKAGE
CASE 670
IfIIIIIIe~ ~
,.rmyn
BLOCK DIAGRAM
P SUFFIX
PLASTIC PACKAGE
Sense Amp
CASE 648
and
Write Drivers
PIN ASSIGNMENT
Word
Drivers
32 X 32
Array
1.
16
WE
15
14
13
CS
12
11
6
15
D,n
, of 32
Decoder
10
1 of 32
Decoder
9
Pin Description
13
AO
A 1 A2 A3 A4 A5 A6 A 7 AS
Vee"= Pin 16
cs
God'" Pin 8
AO·A9
Address I nputt;
WE
Write Enable
Din
Data Input
D out
Data Output
A9
NOTE: Logic driving sense amp/write dr .... ers depicts
negative-onlV' write used on C4m
4-7
Chip Select
MCM93425
FUNCTIONAL DESCRIPTION
The MCM93425 IS a fully decoded 1024-blt Random Access
lOW, the data at Din IS written Into the addressed !oeatlon. To
Cs
Memory organized 1024 words by one bit. Word selection IS
achieved by mF!ans of a 1 O-blt address, AD -- A9
The Chip Select
Input provides for memory array expan-
location IS presented at 00UI and IS non-Inverted.
Sion. For large memories, the fast chip select tlrne permits the
speeds
decoding
Imped othl-'rWI')" n()tl~cl)
r--
UnIts
CondLtLon!.
V"c -
Vee
Mill, IOL . 16 mA
-VI-I;;'---
'OH
IOH
- 10 J mA, Vce
5') mA
Vrle
Vee
f------jf----:------::-----,,-,---=-:--------------- loft
Output Current (High Z)
Output High Voltage
I MeM9J42S0C~-PCI MCM934:?~FM, DM
24
Vri<
---7~
-
---
I--V-e-D-+-'-n-p-ut-D-,a-d-e-e-'a-m-p-V-,.L"-til-4~-------~-f--"-·--·--· -~'l-S'
ICC
Power Supply Current
- - - - - - --- - - --'130
---- -iSS
TA
iliArle
-t----:,c'A"-----:u""::e-+1
rn-A"--''',--;
_-.2~
4-8
M<.IX,
1111
MilK
___
MI(l
I
Vce
5UV
5'\
10 InA
--------+
M •• x,
AI: InplJt'>
(,rl)lJnd,~d
--~---------~
MCM93425
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature unless otherwise noted)
AC TEST LOAD AND WAVEFORMS
Input Pulses
Loading Conditions
All Input Pulses
:t~-
~
• - i - -
1 - - - - - - - -\--90%
- - - - -:-\
1 I
I
-=_ 1-"-'0 n,
----1
1--'0 n,
::3---------{
_____
30 pF
J.:>~p_~~\
----::!:""""
I
'0%
--/~-90%
I
I
t----' a n,
-= ~
Load B
Load A
-'0%
I
1
--i 1--' a n,
MCM93425DC. PC MCM93425DM. FM
Characteristic (Notes 2, 4)
Symbol
READ MODE
DELAY TIMES
Min
Max
Max
Min
Units
Conditions
n,
tACS
Chip Select Time
35
45
See Test CirCUit
1ZACS
Chip Select to High Z
35
50
and Waveforms
tAA
Address Access Time
45
60
n,
WRITE MODE
DE LA Y TIMES
tzws
Write Disable to High Z
35
45
tWR
Write Recoverv Time
40
50
See Test CirCUit
and Waveforms
n,
INPUT TIMING REQUIREMENTS
tw
Write Pulse Width (to guarantee write)
30
40
See Test CirCUit
tWSD
Data Setup Time Prior to Write
5
5
<=====
------i
MCM93425
WRITE CYCLE TIMING
CS
Chip Select
AO
A9
-5
D,n
Data Input
¥r--+--f
~!
i t ~~-~ 1---+-1
; , ILJLi
-+---
WF."
Write Endi.lc
TWSO
-..J ~-
t-- - -twscs
~A-..I
~ __
-
tWHCS
H.";,h"Z - -, - \
Load A
D out
Data Output
-· . .1
Load B
I
lWHD~
-...J
~- tWSA
I
tWR
J
High Z _ _ _ _
____
~_-_ _ __
(All ahove measurements referencp. to 1 5 VI
WRITE ENABLE TO HIGH Z DELAY
&V
WE
Write Enable
00ut
TZWS----1
Data Output "0" Level
~_ _ _ _
05 V High Z
5 pF
. " " Level
0.5 V
°out
High Z
'-----
Data Output
Load C
Propagation Delay from Chip Select to High Z
CS
1'5V
Chip Select
~tZRCS
°out
Data 0 u tp_u...;I_·..:;·O_"_L::.;e...;v.:.el~--'I
,---0 5 V High Z
. " " Level
0.5 V
°out
' - _ _ _ _ High Z
Data Output
(All
tzxxx parameters are measured at a delta of 0.5 V from the logic level and using Load C)
NOTE 2: DC and AC specifications limits guaranteed with 500 linear feet per minute blown 81r. Contact your Motorola Sales Representative
if extended temperature or modified operating conditions are desired.
(J JA
(Junction to Ambientt
Package
Blown
Still
9 JC (Junction to Case)
D Suffix
50 0 C/W
85 0 CiW
15 0 C/W
F Suffix
55 0 C/W
90 0 C/W
15 0 C/W
P Suffix
65 0 C/W
1000 C/W
25 0 C/W
NOTE 3: Out~ut shorr circuit conditions must not exceed 1 second duration
NOTE 4 The maximum address access time IS guaranteed to be the worst case bit in the memory.
4-10
®
MCM7680
MCM7681
MOTOROLA
MIll
8192-BIT PROGRAMMABLE READ ONLY MEMORY
The MCM7680!81 together with the MCM7620!21, MCM7640/43
8192-BIT PROGRAMMABLE
READ ONLY MEMORIES
comprise a complete, compatible family having common dc electrical characteristics and identical programming requirements. They
are fully decoded, high-speed, field-programmable ROMs and are
available
In
MCM7680 - 1024 X 8 - Open-Collector
MCM7681 - 1024 X 8 - Three-State
commonly used organizations, with both open-collector
and three-state outputs_ All bits are manufactured stOring a logical
"1" (outputs high), and can be selectively programmed for logical "0"
(outputs low).
The f,eld·programmable PROM can be custom-programmed to
any pattern using a simple programming procedure Schottky bipolar
circuitry provides fast access time, and features temperature and
voltage compensation to minimize access time variations.
Pinouts are compatible to industry-standard PROMs and ROMs.
In addition, the MCM7680 and 81 are pin compatible replacement
for the 512 X 8 with pin 2 connected as A9 on the 1024 X 8.
I n addition to the conventional storage array, extra test rows and
columns are included to assure high programmability, and guarantee
CE RAMie PACKAGE
parametric and ac performance. Fuses in these test rows and columns
CASE 623
are blown prior to shipment.
•
Common de Electrical Characteristics and
•
Simple, High-Speed Programming Procedure
(0.1 seconu per 1024 8its, Typical)
•
Expandable - Open-Collector or Three-State
Outputs and Chip Enable Inputs
•
Inputs and Outputs TTL-Compatible
Low Input Current - 250 /lA Logic "0",40 /lA Logic "1"
Full Output Drive - 16 mA Sink, 2_0 mA Source
•
Fast Access Time - Guaranteed for Worst-Case
N2 Sequencing, Over Commercial and Military
•
Pin-Compatible with Industry-Standard PROMs and ROMs
Programming Procedure
PIN ASSIGNMENT
24
Temperature Ranges
23
22
4
ABSOLUTE MAXIMUM RATINGS ISee Note)
Rating
21
20
Symbol
Value
Unit
VCC
+ 70
Vdc
V,"
+5.5
Vdc
VOH
+7.0
Vdc
ICC
650
mAde
10
Input Current
I,"
-20
mAde
11
14
Output Sink Current
10
100
mAde
12
13
SUpply Voltage (opf>rattng)
Input Voltage
Output Voltage (operating)
Supply Current
18
8
TA
Storage Temperature Range
T stg
-55to+150
TJ
+175
-55 to 'i'"125
o to +70
°c
°c
.,.
NOTE' Permanent device damage may occur ,I ABSOLUTE MAXIMUM RATINGS
Functional operation should be restricted to RECOMMENDED
exceeded
OPERATING CONDITIONS
Exposure to higher than recommended . . ortages
for extended periods 01 time could allect devIce reliabilttv. (While programmrng,
follow the programming speCifications.)
4-11
17
16
°c
Operating Temperature Range
MCM76xxDM
MCM76xxDC
Maximum Junction Temperature
19
15
MCM7680, MCM7681
DC OPERATING CONDITIONS AND CHARACTERISTICS
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Symbol
Supply Voltage
Min
Nom
Max
4.50
4.75
5.0
5.0
5.50
5.25
Unit
Vdc
Vee
MCM76)(xOM
MCM76xxDC
Input High Voltage
V,H
2.0
-
.-
Vdc
Input Low Voltage
V,l
-
-
0.8
Vdc
DC CHARACTERISTICS
Three-State
Output
Open·Collector
Output
Symbol
'RA. 'RE
Parameter
Test Conditions
Address/Enable
"1"
V,H
Vee Max
Min
Input Current
"0"
V,l
045 V
Output Voltage
"1"
10H
"0"
'Ol
-2.0 mAo Vee" Vee M,n
-+16 mA, Vee
Vee Min
10HE
'OlE
Output DIsabled
Current
"1"
"0"
VOH. Vee Vee Max
'0.3V.Vec Vee Max
VOL
10H
Output Leakage
"1"
VOH.Vec
VCl
Input Clamp Voltage
lOS
Output Short
ICC
Power Supply Curren!
CirCUIt
I,n
Current
(f - 1.0 MHz, T A
Max
Unit
40
}JAde
-0.1
-0.25
mAde
3.4
0.35
0.45
Vdc
100
N/A
100
-100
.uAde
100
N/A
}JAde
-1.5
-1.5
Vdc
70
mAde
150
170
mAde
Min
TVp
-0.1
0.35
-
Vee Max
-10 mA
Vec Vee Max, Vout 0.0 V
One Output Only for 1 s Max
-0.25
-
N/A
N/A
2.4
0.45
N/A
Velc
15
,uAdc
VCC - VCC Max
MeM7680iMCM7681 DC
MCM7680iMCM7681DM
CAPACITANCE
Max
40
VOH
VOL
'FA.'FE
Tvp
All Inputs Grounded
110
110
110
150
170
110
mAde
25°C, perlodicilily sampled rather than 100% tested.)
Characteristic
Input Capacitance
Output Capacitance
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature unless otherWise noted)
o to
+70 0 C
-55 to +125 0 C
Symbol
TVp
Max
TVp
Max
Unit
Address to Output Access Time
tAA
45
70
45
85
ns
Chip Enable Access Time
tEA
30
40
30
00
Characteristic
ns
MCM7680/81
Ae TEST lOAD
TIMING DIAGRAM
'
Address
1.5 V
~
--------3.0 V
_, . - - : - , - - - - - - 0 0 V
'AA ~
__
Oulpul
',.5
v*
1.5V
cs ~
._.,-_ __
CS
I
tEA-.
"0" Oulpul
•
r--
'.5 V \
Vee
o
E-
~
3 OV
.
1.5V
t.
.-1
0.0 V
i--. tEA
Fv
Test Point 0 ..,.-.
30"Fo
-~-
300
--t---o
0)(
~600
-~
-Includes Jig CSfJacitance
4-12
MCM7680, MCM7681
PROGRAMMING
his own programmer to satisfy the sepcifications described
The PROMs are manufactured with all bits/outputs
Logical "1" (Output High).
in Table 1. or buy any of the commercially available pro·
Any desired bit/output can
grammers which meet these specifications. These PROMs
be programmed to a Logical "0" (Output Low) by follow·
ing the simple procedure shown below. One may build
can be programmed automatically or by the manual pro·
PROGRAMMING PROCEDURE
1. Address the PROM with the binary address of the
while the Vee input is raised to VpH by applying
output enable pulses to each output which is to be
selected word to be programmed.
cedure shown below.
programmed.
Address inputs
The output enable pulses must be
separated by a minimum interval of td'
are TTL·compatible. An open circuit should not be
used to address the PROM.
2. Disa':!: the chip by applying Inputs highs (VIH) to
7. Lower Vee to 4.5 Volts following a delay of td
from the last programming enable pulse applied to
an output.
the es Inputs. es Inputs must remain at VIH for
program and verify. The chip select is TTL·compatible.
8. Enable
the PROM for verification by applying a
logic "0" IVILI to the es Inputs.
9. If any bit does not verify as programmed. repeat
An open circuit should not be used to disable the
chip.
3. Disable the ~ro"rammlng circuitry by applying an
Output Voltage Di,able of less than VOPD to the
output of the PROM. The output may be left open
to achieve the disable.
4. Raise Vee to VpH with rise time equal to t r .
5. After a delay equal to or greater than td. apply a
pulse with amplitude of VOPE and duration of tp to
the output selected for programming. Note that the
Steps 2 through 8 until the bit has received a total
of 1.0 ms of programmi~g time. Bits which do not
program within 1.0 ms may be considered programming rejects.
Multiple pulses of durations
shorter than 1.0 ms may be used to enhance programming speed.
10. Repeat Steps 1 through 9 for all other bits to be
programmed In the PROM.
PROM is supplied with fuses intact generating an
11. Programming rejects returned to the factory must
output high.
Programming a fuse will cause the
output to go low In the verify mode.
be accompanied by data giving address with desired
and actual output data of a location in which a
programming failure has occurred.
6. Other bits in the same word may be programmed
TABLE 1
PROGRAMMING SPECIFICATIONS
Symbol
Parameter
VIH
VIL
Address Input
VPH
VPL
Programming/Verify
ICCp
Programming Voltage Current Limit
Voltage(1 )
Voltage to
Vee
Min
TVp
Max
Unit
2.4
0.0
11.75
4.5
5.0
0.4
5.0
V
12.0
4.5
0.8
12.25
5.5
650
V
V
V
600
600
'r
I
1
I
I
10
10
~s
If
Programming (Vee)
Voltage Rise and
Fall Time
td
Programming Delay
10
10
100
~s
Ip
Programming Pulse Width
100
1000
~s
DC
Programming Duty Cycle
-
50
90
%
10.0
4.5
10.5
5.0
11.0
5.5
V
Output Voltage Enable Current
2
4
10
mA
Case Temperature
-
25
75
°c
mA
~s
Output Voltage
VOPE
VOPD
lOPE
TC
Enable
Disablel21
(1) Address and chip select should not be left open for V I H.
(2) Disable condition will be met with output open circuit.
4-13
V
MCM7680, MCM7681
FIGURE 1 - TYPICAL PROGRAMMING WAVEFORMS
Vee
Data-'
DolO 2 _ _ _ _ _ _ _ _ _ _ _..J
DOloN _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---l
4-14
®
[
MCM7684
MCM7685
MOTOROLA
]
Advance InforIllation
MTTL
8192-BIT PROGRAMMABLE READ ONLY MEMORY
The MCM7684/85 together with the MCM7620/21/40/41 142/431
8192-BIT PROGRAMMABLE
READ ONLY MEMORIES
80/81 comprise a complete, compatible family having common dc
electrical characteristics and identical programming requirements.
They are fully decoded, high-speed, field-programmable ROMs
and are available in commonly used organizations, with both opencollector and three-state outputs. All bits are manufactured storing
a logical "1" (outputs high!. and can be selectively programmed
for logical "0" (outputs low).
The field·programmable PROM can be custom-programmed
to any pattern using a simple programming procedure. Schottky
MCM7684 - 2048 X 4 - Open-Collector
MCM7685 - 2048 X 4 - Three-State
bipolar circuitry provides fast access time, and features temperature
and voltage compensation to minimize access time variations.
Pinouts are compatible to industry-standard PROMs and ROMs.
In addition, the MCM7684 and 85 are pin compatible replacement
for the 1024 X 4 with pin 8 connected as A 10 on the 2048 X 4.
In addition to the conventional storage array, extra test rows and
o SUFFIX
columns are included to assure high programmability, and guarantee
CERAMIC PACKAGE
parametric and ac performance. Fuses in these test rows and columns
CASE 726
are blown prior to shipment.
•
Common de Electrical Characteristics and
Programming Procedure
•
Simple, High-Speed Programming Procedure
•
Expandab!e - Open-Collector or Three-State
Outputs and Chip Enable Input
•
Inputs and Outputs TTL-Compatible
Low Input Current - 250 J.1A Logic "0",40 J.1A Logic "1"
•
Fast Access Time - Guaranteed for Worst-Case
N2 Sequencing, Over Commercial and Military
•
Pin·Compatible with Industry-Standard PROMs and ROMs
10.1 second per 1024 Bits, Typicall
PIN ASSIGNMENT
Full Output Drive - 16 mA Sink, 2.0 mA Source
Temperature Ranges
18
17
16
4
15
6
13
ABSOLUTE MAXIMUM RATINGS ISee Notel
Supply Voltage
14
Rating
Symbol
Value
Unit
{op~ratlngl
VCC
+ 7.0
Vdc
V,n
+5.5
Vdc
VOH
+7.0
Vdc
'CC
I,n
650
mAde
-20
mAdc
'0
100
mAdc
Input Voltage
Output Voltage (operating I
Supply Current
Input Current
Output Sink Current
Operating Temperature Range
MCM76xxDM
-55to+125
o to .. 70
T stg
-55 to +150
TJ
+175
Maximum Junction Temperature
°c
uc
.,e
"
NOTE' Permanent device damage may occur
ABSOLUTE MAXIMUM RATINGS
exceeded
Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS
Exposure to higher than recommended voltages
for extended periods of time could affect device reliability. (While programming,
follow the programming speCIfications.)
ThiS" advance Information and speclflc.atlons are subJec.t to change withOut notice
4-15
11
10
°c
TA
MCM76xxDC
Storage Temperature Range
12
B
MCM7684, MCM7685
DC OPERATING CONDITIONS AND CHARACTERISTICS
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Min
Nom
Ma.
4.50
4.75
5.0
5.0
5.50
5.25
VIH
2.0
Vdc
-
-
-
VIL
0.8
Vdc
Symbol
Supply Voltage
MCM76xxOM
MCM76xxOC
VCC
Input High Voltage
Input Low Voltage
Unit
Vdc
DC CHARACTERISTICS
{Over Recommended Operating Temperature Rangel
Symbol
Open-Collector
Output
Parameter
Test Conditions
Three-State
Output
Min
Typ
Max
Min
Typ
Max
Unit
-
-
40
--
40
.uAdc
-0.1
-0.25
mAde
3.4
0.35
0.45
Vdc
Vdc
100
-100
}JAde
.uAdc
N/A
.uAdc
IRA, IRE
IFA,IFE
Address/Enable
"1··
Input Current
·'0·'
VIH
VIL
-0.1
-0.25
-
VOH
VOL
Output Voltage
"1"
"0"
IOH - -2.0 mA, VCC M;n
10L +16 mA, Vce M,n
N/A
-
-
2.4
-
0.35
0.45
-
10HZ
10LZ
Output DIsabled
Current
·'1"
·'0"
VOH. VCC Max
VOL - +0.3 V. VCC Max
-
VOH. Vcc Mox
-
100
N/A
·'1"
-
100
.-
- 1.5
-
-
-1.5
Vdc
N/A
-
N/A
15
-
70
mAde
-
80
80
120
140
-
80
80
120
140
mAde
-
0
0
VCC Max
U.45 V
0
10H
Output Leakage
VIC
Input Clamp Voltage
lin-- 1OmA
lOS
Output Short Circuit Current
Vee Max, Vout - 0.0 V
One Output Only for 1 5 Max
ICC
Power Supply Current
VCC Max
MCM7684/MCM7685 DC
MCM7684/MCM7685 OM
CAPACITANCE If
=
All Inputs Grounded
-
-
-
mAde
1.0 MHz, TA = 25°C. per;od,cally sampled rather than 100% tested.1
Characteristic
Input Capacitance
Output Capacitance
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature unless otherWise noted)
o to
+70o C
-55 to +125 0 C
Svmbol
Typ
Max
Typ
Ma.
Unit
Address to Output Access Time
tAA
45
70
45
85
ns
Chip Enable Access Time
tEA
15
25
15
30
ns
Characteristic
AC TEST LOAD
TIMING DIAGRAM
tJ:
Vee
'
Address
~
1.5 V
*
--------3.0 V
' .--,.-,------O.OV
'AA__
Ou,pu'
'1.5 V
cs~
1.5V
~3.0V
1.5V
oo
1...
. . , -_ __
CS
I-It
tEA-I
r--...-I
·'0" Ou'put
1.5 V ,
r--
O.OV
tEA
Fv
Input t,. tf
<
Test Point
30pF-
.
Ox
600
5.0 ns
-Includes Jig Capacitanee
4-16
MCM7684, MCM7685
PROGRAMMING
his own programmer to satisfy the sepcifications described
The PROMs are manufactured with all bits/outputs
Logical "1" (Output High).
In Table 1. or buy any of the commercially available pro-
Any desired bit/output can
grammers which meet these specifications. These PROMs
be programmed to a Logical "0" (Output Low) by follow·
can be programmed automatically or by the manual pro-
ing the simple procedure shown below.
cedure shown below.
One may build
PROGRAMMING PROCEDURE
while the Vee input is raised to V PH by applying
output enable pulses to each output which is to be
1. Address the PROM with the binary address of the
programmed.
selected word to be programmed. Address inputs
are TTL·compatible. An open circuit should not be
used to address the PROM.
The output enable pulses must be
separated by 0 minimum interval of td'
the es input. The chip select is TTL-compatible.
7. Lower Vee to 4.5 Volts following a delay of td
from the last programming enable pulse applied to
an output.
An open circuit should not be used to disable the
8. Enable the PROM for verification by applying a
2. Disable the chip by applying an input high (VIH) to
logic "0" (VIL) to the es inputs.
chip.
9. If any bit does not verify as programmed. repeat
3. Disable the programming circuitry by applying an
Steps 2 through B until the bit has received a total
Output Voltage Di5able of less than VOPD to the
output of the PROM. The output may be left open
of 1.0 ms of programming time.
4. Raise Vee to VpH with rise time equal to t r ·
5. Alter a delay equal to or greater than td' apply a
gramming speed.
pulse with amplitude of VOPE and duration of tp to
the output selected for programming.
10. Repeat Steps 1 through 9 for all other bits to be
Note that the
programmed in the PROM.
PROM is supplied with fuses intact generating an
output high.
Bits which do not
program withi n 1.0 ms may be considered programming rejects.
Multiple pulses of durations
shorter than 1.0 ms may be used to enhance pro-
to achieve the disable.
11. Programming rejects returned to the factory must
Programming a fuse will cause the
be accompanied by data giving address with desired
output to go low in the verify mode.
and actual output data of a location in which a
programming failure has occurred.
6. Other bits in the same word may be programmed
TABLE 1
PROGRAMMING SPECIFICATIONS
Symbol
Min
Typ
Ma.
Unit
VIH
VIL
Address Input
2.4
5.0
5.0
V
Voltagel1 I
0.0
0.4
0.8
V
VPH
VPL
Programming/Verify
11.75
12.0
12.25
V
4.5
4.5
5.5
V
600
600
650
mA
1
1
1
1
10
10
1"
10
10
lOa
1"
ICCp
tr
tf
Parameter
Voltage to
Vee
Programming Voltage Current L,mit
Programming (Vee)
Voltage Rise and.
Fall Time
1"
td
Programming Derav
tp
Programming Pulse Width
100
.-
Programming Duty Cycle
-
50
1000
90
1"
DC
Enable
10.0
10.5
11.0
V
Disable(2)
4.5
5.0
5.5
V
Output Voltage Enable Current
2
4
10
mA
Case Temperature
-
25
75
°c
%
Output Voltage
VOPE
VOPD
lOPE
TC
(1) Address and chIp select should not be left open for VIH.
(21 Disable condition will be met with output open circuit.
4-17
MCM7684, MCM7685
FIGURE 1 - TYPICAL PROGRAMMING WAVEFORMS
cs _____--I
VpH----
Vee
Data- 1
Oata-2
--------------1
Data N
-------------------1
4-18
MECL MEMORIES
GENERAL INFORMATION
Complete information is available in the M EC L Data Book. Contact your sales representative or authorized
distributor for information.
TABLE 1 - LIMITS BEYOND WHICH DEVICE LIFE MAY BE IMPAIRED
Characteristic
Supply Voltage
Input Voltage IV CC - 0)
Output Source Current -
Symbol
Rating
Unit
VEE
-8.0 to 0
V
o to
Yin
Continuous
50
lout
Surge
Junction Ternperature - Ceramic PackageG)
Storage Temperature
V
mA
100
165
TJ
Piastic Package
CD
VEE
°c
150
T stg
- 55 to + 150
°c
Maximum TJ may be exceeded I " 250 0 C) for short periods of time (';; 240 hours) without significant
reduction in device life.
TABLE 2 - LIMITS BEYOND WHICH PERFORMANCE MAY BE DEGRADED
Characteristic
Supply Voltage (V cc
Output Drive -
~
O)@
MCM10l00 Series
Symbol
Rating
VEE
-4.94 to - 5.46
V
-
50Hto-2.0V
n
MCM 1 0500 Series
Operating Temperature Range@)
100
n
to -2.0 V
°c
TA
o to
MCM10l00 Series
75
-55 to + 125
MCMl 0500 Series
Functionality only. Data sheet limits are specified for --5.19 to -5.21 V.
With airflow;;' 500 Ifpm.
4-19
Unit
MECL MEMORI ES (continued)
TABLE 3 - DC TEST PARAMETERS
Each MECL 10,000 series device has l!een designed to meet the dc specifications shown in the test table, after
thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board
and transverse airflow greater than 500 linear feet per minute is maintained. VEE
OoC
-SSoC
Forcing
Function
=-
5.2 V ± 0.01 0 V.
7SoC
2SoC
Parameter MCM10S00* MCM10100** MCM10100- MCM10S00* MCM10100**
12SoC
MCM10S00*
vlHmax = VOHmax
-0.880
-0.840
- 0.81 0
-0.780
-- O. 720
-0.630
VOHmin
-1.080
-1.000
-0.960
-0.930
-0.900
-0.825
VOHAmin
-1.100
-1.020
-0.980
-0.950
-0.920
-0.845
VIHAmin
-1.255
-1.145
-1.105
- 1.105
-1.045
-1.000
VILAmin
-1.510
-1.490
-1.475
-1.4 75
-1.450
-1.400
- 1 .635
-1.645
-1.630
-1 .600
-1.605
-1.525
VOLAmax
-1.655
-1.665
-1.650
-1.620
-1.625
-1.545
VOLmin
IINLmin
-1.920
-1.870
-1.850
-1.850
-1.830
--1.820
0.5
0.5
0.5
0.5
0.3
0.3
VOLAmin
VILmin
VILmin
r
'Drlvlng 100 n to -2.0 V .
• 'Driving 50 n to -2.0 V.
Vee
=0
Gnd
1~ __ -,
°
~--.-
I
0
I
I
I
I
I
I
-l--l
I
I
INPUT LEVELS
CS' CS2 CS3
"0
'A7
"
A]
I
I
0
I
o----!I
tr
A"
All timing measurements referenced to 50% of input levels
A7
I
I
I
I
CL -;;;:
I
I
oeley should be derated 30 ps/pF for capacitive loed up to 50 pF
I
I
I
2.0nstyp.
°out --;-
A6
I
I
I
If
A4
I
Din
WE
I
5,0 pF (including jig lind stray capacitance)
-2.0 V
I
I
I
I
FIGURE 1 - SWITCHING TIME TEST CIRCUIT
4-20
MECL MEMORIES (continued)
FIGURE 2 -- CHIP SELECT ACCESS TIME WAVEFORM
Chip Select
cs
50%
FIGURE 3 - ADD.RESS ACCESS TIME WAVEFORM
._--j
Dout
____________________
~~r5-0-o/.-0-------------------
FIGURE 4 - SETUP AND HOLD WAVEFORMS (WRITE MODEl
Address
50%
50%
D out
~-----tWSA----~
tws
4-21
@
MCM10143
MOTOROLA
8 X 2 MULTIPORT REGISTER
FILE (RAM)
8 x 2 MULTIPORT REGISTER FILE
(RAM)
The MCM10143 is an 8 word b." 2 bit multipart register file
(RAM) capable of reading two locations and writing one location simultaneously. Two sets of eight latches are used for data
storage in this LSI circuit.
WRITE
The word to be Wrlttell IS selected by "ddrt,s,,'s AO . A2. Each bit
of the word has a separal!' Writ" elldbl" to Jllow more flexibility In
system design. A write occurs on the
Data
IS
POSltIVl:
trdn...,ltlon of the clock
enabled by having the write elldbles Jt a low level when the
clock makes the transition. To inhit)lt d bit frorn
t}(~lIlg
L SUFFIX
written, the
CERAMIC PACKAGE
CASE 623
bit enable must be at a high level whell the clock qoes low and not
change until the clock gues high. Operatlull of ttw clock and the bit
I~
enables can ue reversed. While the clock
low d
pO~ltlve
transition of
the bit enable will WrlW that tllt Illtu the add"'55 ",t.,ct"d t)y AO-A2.
READ
When the clock is hl9h Jny twu
\Vord~ rndY t){~ rPdcl
out simulta
neausly, as selected by add""ses 80 B2 alld Co C2. Including the
word written during the prewdlf'g half l?lol?k "yci<' When the clock
goes low the addressed rtilt<..l is stored III tht: ')lrJ\lI:~, Ll.'vel changes on
PIN ASSIGNMENT
the redd ,.HJdress Ijnt~s hJvt~ no effl~ct Ull ttll' output IHn!! the cluck
again goes high. Read uut is accumrllSl",d at dny tllne by enabling
output gates (BO B 1), (CO C 1)
tpd
Clock to Data out
(R cad So lected)
pk~1
2
C~
OB,
r~
OBO
OCt
r~·
R'E B
OCo
•
lOr" (typ)
(typ
110
6
I
8
luadl
c;
'MOOE
INPUT
LJ 0
II E~
[) ,
I
11
()U TPu T
HEllUBo
OBt
()(;o
DC,
or
Re .•HJ
Ii
\fI.'''O!
I"H
tI
~I
I
i
Hea(l
"Note
-,'\I01P
CI()<.'" u ....
("r~<,t'q\Je"l
;111'1 lh''''''jt,
T,,,!h
AU 1'.. 2, BO H2. d,,,r LO C:.! .1'" d I .,..:
~(,
1,,1,',·
',.j
ItlrO"4hUCll T at,I,·
Do,. ,
Cdr~
4-22
H
H
12
BO
~,
vcc
veel
AEc
1-,-.'
L~
Bt
C2
WE1
Co
wfo
C,
2'
~ 23
- .,
22
2t
.
,
-.~
20
19
Clock
[
'0 L
TRUTH TABLE
1----'-"-+-.-.-C-'O-'k-'W-t'-o'-W-E-,'
.-f Vcco
L~ B2
Read ErlatJie to Ddta out 28 r]> (typ)
(Clock high. Add""ses 1",?Selltj
610 mW
[
5 ns (tYI'I
Address to Data out
(Clock Hrgh)
Po
,
::-:J
.--
18
t7
16
-1
DO
A,
~
-]
15
,
D,
AO
rj
1.
,
13
[-1
.
'LV~E
A2
-1
J
MCM10143
BLOCK DIAGRAM
4
REB
,--
6
Read
Decoder
B
7
v
5
I----<
f---~
~
9
t--
10
~
Clock
Multiplexer
Bbit 1
Write
Amplifier
Bit 0
~
L~
r+
Multiplexer
B-bit 0
-
~
r-- I--
t-
Slave
B-bit 1
Slave
B-bit 0
f--
.....
....
f-----
Output
Gate
B-bit 1
2
- - 0 aB,
Output
Gate
B-bit 0
3
~
aBO
8 x1
Master Latches
Bit 0
14
Write
Decoder
A
15
13
8
WE,
~
11
01
Write
Amplifier
Bit 1
IL.,
~
...
0
17
16
18
.1 "., ~
l
f--
8 x 1
Master Latches
Bit 1
Multiptexer
C-bit 1
~
r-- r-
Slave
C-bit 1
~
r-
22
I
QC1
J
r-----
Dec;der
l
Output
Gate
Cblt 1
L....,
L-....,
Multi
plexer
~
Cbit 0
f----
20
Slave
r-- I--
C-bit 0
~
--
0
4-23
Output
Gate
Cblt 0
L-- _ _
~ aco
MCM10143
ELECTRICAL CHARACTERISTICS
oOC
Characteristics
Power Supply Drain Current
Input Current
Pins 10, 11, 19
All other pins
Switching Times Q)
Read Mode
Address Input
Read Enable
Data
Setup
Address
Hold
Address
+25 0 C
+75 0 C
Symbol
Min
Max
Min
Typ
Max
Min
Max
Unit
IE
-
150
-
118
150
-
150
mAde
-
245
200
-
-
-
-
245
200
-
245
200
/JAde
linH
-
ns
15.3
5.3
7.3
4.5
1.2
2.0
10
3.5
5.0
-
-
8.5
5.5
thold(Clock -8 +)
-
-
-1.5
tsetup(WE -Clock +)
tsetup(WE +Clock-)
tsetup(A -Clock +)
-
-
-
-
-
-
tRE-OB+
tClock+08-
4.0
1.1
1.7
tsetup (8 -Clock -)
ts ±- 08 ±
14.5
5.0
7.0
4.5
1.2
2.0
15.5
5.5
7.6
-
-
-
-4.5
-
-
-
7.0
1.0
8.0
5.0
4.0
-2.0
5.0
2.0
-
-
-
2.5
-2.0
-3.0
-2.0
Write Mode
Setup
Write Enable
Address
Data
Hold
Write Enable
Address
Data
Write Pulse Width
Rise Time, Fall Time
(20% to 80%)
tsetuo(D -Clock +)
-
-
-
-
-
-
PWWE
-
5.5
1.0
1.0
1.0
-
8.0
t r , tf
1.1
4.2
1.1
thold(Clock +WE +)
thold(Cloek +WE-)
thold(Clock + A +)
thold(Clock+D+)
G)AC timing figures do not show all the necessary presetting conditions.
4-24
-
-
-
-
-
-
-
-
-
-
-
5.0
-
-
-
2.5
4.0
1 .1
4.5
MCM10143
READ TIMING DIAGRAMS
FIGURE 1
FIGURE 2
FIGURE 3
FIGUR.E 4
4-25
MCM10143
(
WRITE TIMING DIAGRAM
(nab's ~tup
WE _ _ _ _ _ ~-----
r
t
tup
{
•
CIO;".k
FIGURE 5
Enable Hold
FIGURE 6
WE
Clock
Disable
WE
FIGURE 7
Clock
Pulse Width
FIGURE B
Clock
WE
--, > > 'se'up
Address
1---, »'hold
I ~--- - ----
--==1-----
'---------------+-------~-h-:-Id
A -----.,-
-----+--------,
0-- -
+-__-'1\_ - - - - - - - -
- - - - _ I ' -_ _
Clock _ _ _ _ _ _ _ _ _ _ _J
4-26
FIGURE 9
®
MCM10144/MCM10544
MOTOROLA
256 X 1-BIT RANDOM
ACCESS MEMORY
The
X
MCM10144/10544
1bit
RAM.
Bit
is
selection
a
256
word
is achieved
by
means of an 8·bit address AO through A7.
The active-low chip
expansion
up
to
select
2048 words.
allows memory
The fast ch ip
select access time allows memory expansion
without affecting system performance.
The operating mode of the RAM (CS inputs
low) is controlled by the WE input. With WE
low the chip is in the write mode-the output
AO
Al
A2
A3
A4
WE
is low and the data present at Din is stored
at the selected address. With WE high the chip
is
3
in
the
selected
4
read
mode-the data state
memory
location
at the
is presented
non-
inverted at D out '
9
~
•
Typical Address Access Time
•
Typical Ch ip Select Access Time ~ 4.0 ns
•
50
kn
17 ns
Input Pulldown Resistors on Chip
Select
A5
A6
•
Power 0 issipation (470 mW typ @ 25 0 C)
•
Pin·forPin Replacement for Fl0410
Decreases with Increasing Temperature
A7
TRUTH TABLE
MODE
INPUT
OUTPUT
cs·
WE
D,"
Dout
Write "0"
L
L
L
L
Write " ' "
L
L
H
L
R.. d
L
H
if>
a
16
Diubled
H
if>
L
15
PIN ASSIGNMENT
14
¢ '" Don't Care
13
12
11
F SUFFIX
CERAMIC PACKAGE
CASE 650
4-27
10
MCM10144/MCM10544
ELECTRICAL CHARACTERISTICS
OOC
-55 0 C
Characteristic
Symbol
+25 0 C
+75 0 C
+125 0 C
Min Max Min Max Min Max Min Max Min Max
Unit
Power Supply Drain Current
lEE
-
140
-
135
-
130
-
125
-
125
mAdc
Input Current High
linH
-
375
-
220
-
220
-
220
-
220
}.lAdc
-55°C and +125 0 C test values apply to MC105xx devices only.
SWITCHING CHARACTERISTICS (Note 1)
Characteristics
Read Mode
Chip Select Access Time
Chip Select Recovery Time
Address Access Time
Write Mode·
Write Pulse Width
Data Setup Time Prior to Write
Data Hold Time After Write
Address Setup Time Prior to Write
Address Hold Time After Write
Chip Select Setup Time Prior to
Write
Chip Select Hold Time After Write
Write Disable Time
Write Recovery Time
Rise and Fall Time
Symbol
NOTES:
MCM10544
TA=Oto
+ 75 0 C,
TA = -55 to
+125 0 C,
VEE =
-5.2 Vdc
± 5%
VEE =
-5.2 Vdc
± 5%
Min
Max
Min
Max
tACS
tRCS
tAA
2.0
2.0
7.0
10
10
26
2.0
2.0
7.0
10
10
26
tw
25
2.0
-
25
2.0
2.0
8.0
0.0
2.0
-
-
2.0
2.5
2.5
10
10
-
tWSD
tWHD
tWSA
tWHA
tWSCS
2.0
8.0
2.0
2.0
-
tWHCS
tws
tWR
2.0
2.5
2.5
10
10
-
-
Cin
C out
Conditions
ns
Measured from 50% of
input to 50% of output.
See Note 2.
ns
tWSA = 8.0 ns
Measured at 50% of
input to 50% of output.
tw = 25 ns.
ns
Measured between 20%
and 80% points.
pF
Measured with a pulse
technique.
-
1.5
1.5
7.0
5.0
1.5
1.5
7.0
5.0
-
5.0
8.0
-
5.0
8.0
-
Unit
-
t r , tf
Address to Output
CS or WE to Output
Capacitance
Input Capacitance
Output Capacitance
MCM10144
1. Test circuit characteristics: RT ~ 50 n, MCM10144; 100 n, MCM10544. CL';; 5.0 pF (including jig
and stray capacitance). Delay should be derated 30 ps/pF for capacitive load up to 50 pF.
2. The maximum Address Access Time is guaranteed to be the Worst-Case Bit in the Memory.
3. For proper use of MECL Memories in a system environment, consult MECL System Design
Handbook.
4-28
@ MOTOROLA
00
0'
MCM10145/MCM10545
16 X 4-BIT REGISTER FILE
(RAM)
cs
OJ
The MCM10145/10545 isa 16 word X 4-bit
RAM.
Bit selection
is achieved by means of
a 4-bit address AO through A3.
The active·low chip
expansion
up
to
32
select allows memory
words.
The
chip
fast
select access time allows memory expansion
without affecting system performance.
The operating mode of the RAM (CS input
low) is controlled by the WE input. With WE
low the chip is in the write mode-the output
is low and the data present at Dn is stored at
the selected address. With WE high
is
in
the
selected
AI
mode-the
memory
inverted at
A3
read
location
data
the ch ip
state
at the
is presented
non-
an.
=
•
Typical Address Access Time
•
Typical Chip Select Access Time
•
50 kl1 Pulldown Resistors on All Inputs
Power Dissipation (470 mW typ @ 25 0 C)
•
10· ns
=
4.5 ns
Decreases with Increasing Temperature
Wf
PIN ASSIGNMENT
16
15
TRUTH TABLE
14
MODE
INPUT
cs
WE
OUTPUT
On
13
On
12
Write "0"
11
Write "1"
H
R.ad
Oilabled
L SUFFIX
H
H
~
~
~
10
a
~ '" Don't Care.
CERAMIC PACKAGE
CASE 620
FIGURE 1 - CHIP ENABLE STROBE MODE
A
----'1'- _ _ _ _ _ _ _ _ _ JI'-___
jo4--_+__
Don
---.....,1-"
F SUFFIX
CERAMIC PACKAGE
CASE 650
4-29
tCHA
MCM10145/MCM10545
ELECTRICAL CHARACTERISTICS
OOC
-55°C
Characteri~tic
Symbol
Power Supply Drarn Current
lEE
Input Current High
linH
+75 0 C
+25 0 C
+ 125°C
Min Max Min Max Min Max Min Max Min Max
-
Unit
135
-
130
-
125
_.
120
-
120
mAde
375
-
220
-
220
-
220
-
220
/lAde
55°C and +125 0 C test values apply to MC105xx devices only.
SWITCHING CHARACTERISTICS (Note 1)
MCM10145
TA
Characteristics
Read Mode
Chip Select Access Time
Chip Select Recovery Time
Address Access Time
Write Mode
Write Pulse Width
Data Setup Time Prior to Write
Data Hold Time After Write
Address Setup Time Prior to Write
Address Hold Time After Write
Chip Select Setup Time Prior to
Write
Chip Select Hold Time After Write
Write Disable Time
Write Recovery Time
Chip Enable Strobe Mode
Data Setup Prior to Chip Select
Write Enable Setup Prior to
Chip Select
Address Setup Prior to Chip Select
Data Hold Time After Chip Select
Write Enable Hold Time After
Chip Select
~ddress Hold Time After Chip
Select
Chip Select Minimum Pulse Width
Rise and Fall Time
Address to Output
CS to Output
Capacitance
Input Capacitance
Output Capacitance
NOTES:
Symbol
~
0 to
MCM10545
TA~-55to
+75 0 C,
+125 0 C,
VEE ~
-5.2 Vdc
5%
VEE ~
-5.2 Vdc
5%
Min
Max
Min
Max
tACS
tRCS
tAA
2.0
2.0
4.0
8.0
8.0
15
2.0
2.0
4.0
10
10
18
tw
-
-
tWSCS
0
--
8.0
0
4.0
5.0
3.0
5.0
-
tWSD
tWHD
tWSA
tWHA
8.0
0
3.0
5.0
1.0
tWHCS
tws
tWR
0
2.0
2.0
8.0
8.0
tCSD
tcsw
0
0
tCSA
tCHD
tCHW
0
2.0
0
tCHA
tcs
-
-
0
2.0
2.0
Unit
Conditions
ns
Measured from 50% of
input to 50% of output.
See Note 2.
ns
tWSA ~ 5 ns
Measured at 50% of
input to 50% of output.
tw ~ 8 ns.
ns
Guaranteed but not
tested on standard
product. See Figure 1.
-
10
10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4.0
-
-
-
18
-
.-
-
1.5
1.5
7.0
5.0
1.5
1.5
7.0
5.0
6.0
8.0
-
6.0
8.0
ns
t r , tf
pF
Cin
C out
-
-
Measured between 20%
and 80% points.
Measured with a pulse
technique.
1. Test circuit characteristics: RT ~ 50 l', MCM10145; 100 n, MCM10545. CL ~ 5.0 pF (including jig
and Stray Capacitance). Delay should be derated 30 ps/pF for capacitive loads up to 50 pF.
2. The maximum Address Access Time is guaranteed to be the worst-case bit in the memory.
3. For proper use of MECL Memories in a system environment, consult MECL System Design Handbook.
4-30
®
MCM1 0146/MCM1 0546
MOTOROLA
1024 X 1-BIT RANDOM
ACCESS MEMORY
The MCM10146/10546 is a 1024 X 1-bit
RAM. Bit selection is achieved by means of
a 10-bit address, AO to A9.
The active-low chip select is provided for
memory expansion up to 2048 words.
The operating mode of the RAM (CS input
low) is controlled by the WE input. With WE
low, the chip is in the write mode, the output,
D out . is low and
.
AO
~
i;
A1
A2
we
"C
0
~
A3
A4
..
"C
4
N
6
the data state present at
Din is stored at the selected address_ With WE
high, the chip is in the read mode and the data
!:'
15
L
A6
A7
A8
•
Pin-for-Pin Compatible with the 10415
•
Power Dissipation (520 mW typ @ 25 0 C)
•
Typical Address Access of 24 ns
•
Typical Chip Select Access of 4.0 ns
•
50
Decreases with I ncreasing Temperature
12
A5
stored at the selected memory location will be
non-inverted at D out - (See Truth
Table_)
presented
A9
kn
Pulldown Resistor on Chip Select
Input
PIN ASSIGNMENT
TRUTH TABLE
MOOE
INPUT
WE
CS
16
OUTPUT
O,n
15
°out
Write
'0"
I.
L
L
L
Write
'1'
L
L
H
L
R.ad
L
H
Q
DI5abied
H
¢
0
L
14
13
4
c> ""
12
11
10
9
Don"t Care
_LSUFFIX
CERAMIC PACKAGE
CERAMIC PACKAGE
CASE 620
CASE 65003
4-31
MCM 10146/MCM 10546
ELECTRICAL CHARACTERISTICS
OOC
-55°C
+25 0 C
+75 0 C
+ 125°C
Characteristic
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Power Supply Drain Current
lEE
-
155
150
-
145
-
125
-
125
mAdc
-
375
-
220
-
220
-
220
-
220
/JAdc
Input Current High
linH
Logic "0" Output Voltage
VOL
-1.970 -1.655 -1.920 -1.665 -1.900 -1.650 -1.880 -1.625 -1.870 -1.545
Vdc
NOTE: -55°C and +125 0 C test values apply to MCM105XX only.
SWITCHING CHARACTERISTICS (Note 1)
Symbol
Characteristics
MCM10146
MCM10546
TA ~ 0 to
+75 0 C.
VEE = -5.2 Vd.
• 5%
TA~-55to
Min
Max
+125 0 C.
VEE ~ -5.2 Vd •
• 5%
Min
Max
Read Mode
ns
Chip Select Access Time
tACS
tRCS
tAA
2.0
2.0
8.0
7.0
7.0
29
2.0
2.0
8.0
8.0
8.0
40
tw
25
-
25
-
tWSD
tWHD
tWSA
tWHA
tWSCS
5.0
5.0
8.0
2.0
5.0
-
5.0
5.0
10
8.0
5.0
-
tWHCS
tws
tWR
5.0
2.8
2.8
7.0
7.0
5.0
2.8
2.8
12
12
~or~ toOutput
1.5
4.0
1.5
4.0
Address to Output
1.5
8.0
1.5
8.0
Cin
-
-
C out
-
5.0
8.0
5.0
8.0
Chip Select Recovery Time
Address Access Time
Write Mode
Write Pulse Width
(To guarantee writing)
Data Setup Time Prior to Write
Data Hold Time After Write
Address Setup Time Prior to Write
Address Hold Time After Write
Chip Select Setup Time Prior to
I
Write
Chip Select Hold Time After Write'
Write Disable Time
Write Recovery Time
Rise and Fall Time
-
-
Output Capacitance
NOTES:
ns
tWSA = 8.0 ns.
Measured at 50% of input
to 50% of output.
tw = 25 ns
ns
Measured between 20% and
80% points.
pF
Measured with a pulse
-
-
-
tr.tf
-
Conditions
Measured at 50% of input
to 50% of output.
See Note 2.
-
Capacitance
I nput Capac ita nee
Unit
technique.
1. Test Circuit characteristics: RT = 50 n. MCM10146; 100 n. MCM10546. CL" 5.0 pf including Jig and stray capacitance.
For Capacitance Loading" 50 pF. delay should be derated by 30 ps/pF.
2. The maximum Address Access Time is guaranteed to be the Worst-Case Bit in the Memory.
3. For proper use of MECl Memories in a system environment, consult MECl System Design Handbook.
4-32
®
MOTOROLA
MCM10147/MCM10547
128 X 1-BIT
RANDOM ACCESS MEMORY
X
The M CM 1 047/10547 is a fast 128-word
l-bit RAM. 8it selection is achieved by
means of a 7-bit address, AO through A6.
The
active-low
chip
selects and fast chip
select access time allow easy memory expansion
up to 512 words without affecting system
performance.
The operating mode (CS inputs low) is
controlled by the WE input. With WE low the
chip is in the write mode-the output is low and
AO
WE
A1
the data present at D in is stored at the selected
address. With WE high the chip is in the read
mode-the data state at the selected memory
A2
location is presented non-inverted at D out '
A3
A4
AS
•
Typical Address Access Time of 10 ns
•
Typical Chip Select Access Time of 4.0 ns
•
50 kS1 Input Pulldown Resistors
on All Inputs
•
Power Dissipation (420 mW typ @ 25 0 C)
Decreases with Increasing Temperature
•
SimiiartoFl0405
A6
PIN ASSIGNMENT
TRUTH TABLE
vee1
AO
A1
vCC2
16
Dout
15
CS1
A2
A3
BC=
14
WE
D,n
A5
A6
VEE
NC
11
~" _LSUFFIX
CERAMIC PACKAGE
CASE 620
4-33
Dout
WE
Don
L
L
L
L
L
L
H
L
R . .d
L
H
~
a
QIs.abled
H
.p
.p
L
··0··
Write "1"
12
OUTPUT
cs·
Write
13
A4
INPUT
MODE
¢J::: Don't C.r •.
CERAMIC PACKAGE
CASE 650
MCM10147/MCM10547
ELECTRICAL CHARACTERISTICS
OOC
-55°C
Characteristic
Symbol
+25 0 C
+75 0 C
+125 0 C
Min Max Min Max Min Max Min Max Min Max
Unit
Power Supply Drain Current
lEE
-
115
-
105
-
100
--
95
-
95
mAde
Input Current High
linH
-
375
-
220
-
220
-
220
-
220
,uAdc
5S0C and -+125 0 C test values apply to MC105xx devices only_
SWITCHING CHARACTERISTICS (Note 1)
Characteristics
Symbol
MCM10147
MCM10547
T A - 0 to + 75°C.
VEE = -5.2 Vdc ,5%
T A - -55 to + 125°C.
VEE = -5.2 Vdc ,5%
Min
Max
Read Mode
Min
···
'ACS
'ACS
tAA
2.0
2.0
5.0
B.O
tw
tWSD
tWHD
tWSA
tWHA
tWSCS
tWHCS
tws
tWA
8.0
1.0
3.0
4.0
3.0
1.0
1.0
2.0
2.0
-
8.0
8.0
Rise and Fall Time
tr,tf
1.5
5.0
·
Capacitance
I nput Capacitance
Output Capacitance
Cin
-
Cout
.-
5.0
8.0
-
Chip Select Access Time
Chip Select Recovery Time
Address Access Time
8.0
15
Write Mode
Write Pulse Width
Data Setup Time Prror to Write
Data Hold Time After Write
Address Setup Time Prior to Write
Address Hold Time After Write
Chip Select Setup Time Prior to Write
Chip Select Hold Time After Write
Write Disable Time
Write Recovery Time
NOTES:
1. Test Circuit charactemtlcs: AT: 50
···
ns
···
··
MCM10547.
Measured from 50% of
input to 50% of output.
See Note 2.
ns
tWSA - 4.0 ns
Measured at 50% of input
to 50% of output.
tw = 8.0 ns.
-
-
Conditions
Unit
-
-
n. MCM10147; 100 n.
Max
-
-
··
·
··
ns
Measured between 20% and
80% points.
pF
Measured with a pulse
technique.
CL '" 5.0 pF (including JIg and stray capacitance).
Delay should be derated 30 ps/pF for capacitive load up to 50 pF_
2. The maximum Address Access Time is guaranteed to be the Worst-Case Bit in the Memory.
3. For proper use of MECL Memories in a system environment, consult MECL System Design Handbook.
"To be determined; contact your Motorola representative tor up-to-date Information.
4-34
®
MCM1 0148/MCM1 0548
MOTOROLA
°OUT
CSl
CS2
I
I
14
1'1
64 X 1-8\1'
RANDOM ACCESS MEMORY
The MCM10148/10548 is a fast 64 word X
bit RAM. Bit selection is achieved by means
I"
l)"ta OlJ1
ChllJ
Buffer
Selert
of a 6 bit address, AO through A5,
The
active low
chip
selects and
fast chip
seleCT access tllnc allow easy memory expansion
up to 256 warns without affecting system
perforfnance
Tile
Sen!ioe
2 c-
AD
Al
A2
--~
l,
B X B
___6_
Menlory Cell
Array
--1
I
__ 1
,
L_
Bit Address Buffer!
1/8 Decoder
L,_ --io,1
I
A3
A4
operCJtmg
mode
(CS
inputs
low)
Ta
r
J
lI l
chip
1
.
-g; 1,2
-.
J3
«CD
e~
the write rnode---the output is low
IS In
and the data present at Om
WE
I
selected
If)
<; ;;
Din
0
address
the read rnode
memory
\i'FE
With
is stored at the
high
the
chip
location
presented
IS
non inverted
at D out .
j
•
Typical Address Access Time of 10 ns
•
Typical Chip Select Access Time of 4.0 ns
•
50 kU Input Pullclown Resistors
•
Power DISSipation (420 mW typ @ 25 0
on A II Inputs
AS
Ci
PIN ASSIGNMENT
~
'1
-..../·1
Veel
' . AD
Vee2
00ut
~ ___._J
TRUTH TABLE
16
~_-..J'~
L:-:j
Al
[-:-=~
CS1
~ L":':'~1
CS2
WEh,2
A2
N C r..:.=J1 1
3
4
6
1
C::j
c.:-~
A3
MODE
I
N Cr]l.
Din
AS
~13
r=~-::-Jl0
I
Be_tEE __~}--:J 9
INPUT
WE
D,n
°out
L
Wrote
D
L
L
L
Write
1
L
L
H
L
L
H
cJ>
Q
c:>
cJ>
L
DI~abled
L SUFFIX
OUTPUT
CS·
Read
.. cs
~
CSl
+
H
CS2
+ CS3
CJ
c
Don·t Care
CERAMIC PACKAGE
CASE 620
~~~SUFFIX
~RA~IC
PACKAGE
CASE 650
4-35
is
the data state at the selected
Decreases with Increasing Temperature
1 ' ...
is
controlled l)y the W-E Input. With WE low the
A'Tlp11f'e r
MCM10148/MCM10548
ELECTRICAL CHARACTERISTICS
-55°C
Characteristic
Symbol
OoC
+7SoC
+ 25°C
+ 12SoC
MiniMax MmlMax MiniMax MiniMax MiniMax
Power Supply Drain Current
lEE
.. 1 '15
1105
Input Current High
l,nH
- 1375
1 220
. I 95
1 100
1 220
1 220
Unit
..
1 95
mAde
..
1220
JJAdc
·5S0C and +12SoC test values apply to MC105xx devlc~s only
SWITCHING CHARACTERISTICS (Note 1)
Characteristics
Symbol
MCM10148
MCM10548
TA '" 0 to + 15°C.
VEE = -5.2 Vdc • 5%
TA - -55 10 + 12S0C.
VEE = -5.2 Vdc • 5%
Min
Max
Min
Max
Read Mode
Unit
os
Chip Select Access Time
Chip Select Recovery Time
Address Access Time
'ACS
'RCS
'AA
-
75
75
-
15
.-
Input to 50% of output.
See Note 2.
.
Wnte Mode
os
Write Pulse Width
Data Setup Time Prior to Write
Data Hold Time After Write
Address Setup Time Prior to Write
Address Hold Time After Write
Chip Select Setup Time Prior to Write
Chip Select Hold Time After Write
Write Disable Time
Write Recovery Time
Rise and Fall Time
'WHA
tWSCS
'WHCS
tws
tWR
8.0
3.0
2.0
5.0
3.0
3.0
0
2.0
20
7.5
7.5
tr.tf
1.5
5.0
tw
tWSD
'WHD
tWSA
-
-
Conditions
Measured from 50% of
tWSA :. 5.0 ns
Measured at 50% of Input
to 50% of output.
tw ~ 8.0 ns.
.
os
Measured between 20%
and 80% points.
Capacitance
I nput Capacitance
Output Capacitance
NOTES:
pF
Cin
C out
-
5.0.
8.0
-
,. Test CirCUit characteristiCS: AT'" 50 H, MCM10148; 100 H,MCM10548.
CL"'" 5.0 pF (Including Jig and stray capacitance)
Delay should be derated 30 ps/pF for capaCitive load up to 50 pF.
2
The maximum Address Access Time
IS
guaranteed to be the Worst·Case Bit In the Memory.
3. For proper u!>e of MECL Memories In a system envuonme.'lt, consult MECL System Design Handbook.
-To be determined; contact your Motorola representative tor up·to·date Information.
4-36
Measured with a pulse
technique.
®
MCM1 0152/MCM1 0552
MOTOROLA
256 X 1-BIT
RANDOM ACCESS MEMORY
TheMCM10152/10552 isa256·word X 1·bit
RAM.
Bit selection
by means of
is achieved
an 8·bit address AO through A 7.
The active-low chip select allows memory
expansion
up to 2048 words. The fast chip
select access time allows memory expansion
without affecting system performance.
The operating mode of the RAM (CS inputs
low) is controlled by the WE input. With WE
.
AO
'"5 Iii
alu
A1
4
•
UN
"
a
Olsabled
H
L
CSl
+
CS2
+ CS3
D out
(j) '" Don't Care
10
CERAMIC PACKAGE
CERAMIC PACKAGE
CASE 620
CASE 650
4-37
MCM 10152/MCM 10552
ELECTRICAL CHARACTERISTICS
r----------------------,------.----.-----.----.----.---T --55°C
OoC
+ 2SoC
+ 7SoC
+ 125°C i
CharacterIstic
Symbol
Min Max Min Max Min Max Min Max Mm Md)(
IE:E:.
140
135
130
125
17.~)
I
I
Ufllt
:nA(1(
--1,~---'375---~2~2~0~--~2~2~0+---~2~2~0~-~2~.2~O~-"-A~,-"~
In~ul CUIII~ll1 Hlqh
--------------5SoC and +12SoC test values apply to MC105xx devices only.
SWITCHING CHARACTERISTICS (Note 1)
----- - - - - - - -
--.-----.--~-,-:-:-:-::-::--.---------:~:-.,..,--:=----,-----.---------,
MCM10152
MCM10552
TA =0 to +75 0 C,
TA - -55to +125 0 C,
VEE
Characteristics
= -5_2
Symbol
Mm
lACS
20
20
70
Rcad Mode
Chip Select Ace" ...... Tltlw
Chip S'~I'~ct Recnvel y TIfTll~
Add! t~SS ACCI!sS T lm.~
"lC5
'AA
Vdc
Max
Oatil S(!tup T IInl!
'w
PI 1<)1
(I) Will,·
'WSD
Chin Sell!CI Huld T rnw Afl!'1 Wille
'WHCS
'ws
75
AllI~1 Wrltl'
W/I!(~ DrS.!!>[!! TlflH~
Write Hcc(}very
'W5A
tWHJ\
Max
5%
Unit
Conditions
75
Input 10 50",,,
75
S!'c N')\I: 2
1"
--------1-----------;;-;--
to
I)' ()ulnut
50 ns
-'V'JSA
tw
'wscs
A(i(irpss Hold TIrTH:'
tW~H)
Vdc
MI~()surf'd CIt
Chip St!lcct Setup Time Pllnr t() Wille
Will!'
= -5_2
Min
10
2_0
70
~) 0
J 0
20
20
Diltil HrJld TIITW AfH:r
Address Setup TIfTH' Prior to WIII('
VEE
- - - - - r----·-~--'----+---I-M-c-"-ilS-·U-'-1-~(-,- -!-'-()-n-'C:5C:O-<~
WrltP Modp
Wllte PUISf! Width
5%
50o~,
50", 1)1 IrlPUl
of nut nut
10 ns
TIlTH:
R,s" "n,' GilT""e ---------Capacitance
Input C.lPilcltance
Output Capacltanc£!
NOTES
-- r
---S::'--- ---- 'c-=~-C
50
pF
Mp.
AJ 1:1
A4
14
CS I!) ------------------------~~t_--._~--~~--~_+--_._4--_.~~_1~~~
:I
[)J
[)4
4-39
[)]
02
0,
DO
MCM10139/MCM10539
ELECTRICAL CHARACTERISTICS
+25 o C
-DOC
-SSoC
+12S0C
+7SoC
Characteristic
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
MIx
Unit
Power Supply Drain Current
lEE
-
160
-
150
-
145
140
-
160
mAde
Input Current High
linH
-
450
-
265
-
265
-
265
-
265
"Adc
Logic "0" Output Voltage
MCM10139
MCM10539
VOL
Vdc
-2.010 -1.665 -1.990 -1.650 -1.970 -1.625
-2.060 -1.655
-1.990 -1.620
-1.960 -1.545
-
SWITCHING CHARACTERISTICS (Note 1)
MCM10139
MCM10539
(VEE· -5.2 Vdc ± 5 %;
TA· -SSoC to +12SoC)
Chl,ect.,inic
Symbol
(VEE· -5.2 Vdc ± 5%;
TA'. OOC to +75 0 C)
Chip Select Access Time
Chip Select Recovery Time
Address Access Time
tACS
tRCS
tAA
15 ns Max
15 ns Max
20 ns Max
Rise and Fall Time
t r • tf
3.0 ns Typ
Input Capacitance
Output Capacitance
Cin
Caut
5.0 pF Max
B.O pF Max
NOTES'
1.
Test circuit characteristics' AT = 50
n,
··
··
·
·
MCM 10139; 100
n,
Conditions
Measured from 50% of input to 50%
of output. See Note 2
Measured between 20% and BO% points.
Measured with a pulse technique.
MCM10539. CL ~ 5.0 pF including jig and stray capacitance.
For Capacitance Loadmg ~50 pF. delav should be derated by 30 ps/pF.
2. The maximum Address Access Time is guaranteed to be the Worst-Case Bit in the Memory.
3.
For proper use at MECL Memories In a system environment, consult MECL System Design Handbook.
-To be determined; contact your Motorola representative for up·to·date information.
4-40
MCM 10139/MCM 10539
FIGURE 1 - MANUAL PROGRAMMING CIRCUIT
+6.B V 0.0 V
Program
-0.8 V
1
+'5 V
3 k
Verify
--,
(Momentary)
Address
'" "
I
I
-c___....---------1
Decoder
A410---Ll=_
CS13~_-tJ
F SUFFIX
r)
CERAMIC PACKAGE
"
D3
CASE 650
4-43
12
D2
1.
15
D'
DO
MCM10149/MCM10549
ELECTRICAL CHARACTERISTICS
OOC
55°C
+25 0 C
+75 0 C
+125 0 C
Min Max Min Max Min Max Min Max Min Max
Symbol
Characteristic
Power Supply Drain Current
lEE
140
I nput Current High
IlnH
450
135
_.
-
265
130
125
265
265
.-
Unit
125
mAde
1 265
J...IAdc
5S0C and -t12SoC test values apply to MC1Q5xk devices only.
SWITCHING CHARACTERISTICS (Note 1)
MCM10149
MCM10549
T A = 0 to + 75°C,
VEE = -5.2 Vdc . 5%
TA - -55 to +125 0 C,
VEE = -5.2 Vdc . 5%
Symbol
Characteristics
Max
Min
Max
Min
Read Mode
Chip Select Access Time
Chip Select Recovery Time
Address Access Time
Rise and Fall Time
Capacitance
Input Capacitance
Output Capacitance
NOTES:
1. Test
Circuli
tACS
tRCS
tAA
2.0
2.0
7.0
10
10
25
t(,tf
1.5
7.0
Unit
ns
··
·
·
.
See Note 1.
ns
-
5.0
8.0
5.0
8.0
-
Measured between 20%
and 80% points.
pF
-
Cin
C out
Conditions
Measured from 50% of
Input to 50% of output.
Measured with a pulse
technique.
characterIStics. RT - 50 n, MCM10149, 100 n, MCM10549.
CL ~ 5.0 pF (including jig and stray capacitance)
Delay should be derated 30 ps/pF for capacitive load up to 50 pF
2. The maximum Address Access Time is guaranteed to be the Worst-Case Bit in the Memory.
3.
For proper use of MECL Memones In a system environment, consult MECL System Design Handbook.
4. VCP = VCC =- Gnd for normal operation.
·To be determined; contact your Motorola representative for up·to-date information.
t
PROGRAMMING THE MCM10149
During programming of the MCM10149, input
pins
7,
9,
and
Coincident
10 are addressed with standard
With,
or at some delay after the
V CP pulse has reached its 100% level, the desired
M EC L 10K logic levels. However, during program·
bit to be fused can be selected. This is done by
ming input
pins 2, 3, 4, 5, and 6 are addressed
taking the corresonding output pin to a voltage
with 0 V .;; VIH .;; + 0.25 V and VEE';; V IL .;;
-3.0 V. It should be stressed that this deviation
from standard input levels is required only during
of + 2.85 V ± 5%. It is to be noted that only one bit
outputs should remain terminated through their
the programming mode. During normal operation,
standard MECL 10,000 input levels must be used.
50 ohm
load resistor (100 ohm for MCM 1 0549)
to
V.
With these requirements met, and with VCP
is to be fused at a time. The other three unselected
=
-2.0
Current into the selected output is
5 rnA maximum.
VCC = 0 V and VEE = - 5.2 V ± 5%, the address
is set up. After a minimum of 100 ns delay, VCP
the
(pin 1)
is
sourced out of the chip select pin 13. The 0% to
voltage
VCP
ramped up to + 12 V
0.5 V
:I.
(total
is now 17.2 V, + 12 V
to VEE
After the bit select pulse has been applied to
-
appropriate
100%
rise
output,
the
fusing
current
is
time of this current pulse should be
[-5.2 vJ). The rise time of this VCP voltage
pulse should be in the 1 -lOlls range, while its
250 ns max. Its pulse width should be greater than
100 IlS. Pulse magnitude is 50 mA ± 5.0 mAo The
pulse width (t w l) should be greater than 100 Ils
but less than 1 ms. The V CP supply current at + 12
voltage clamp
be-6.0V.
V
will be approximately 525 mA while current
After
drain from V CC will be approximately 175 mAo A
supplies.
The
current
limit
on
the
this
current
source
is
to
the fusing current source has returned
a
rnA, the bit select pulse is returned to it initial
level, i.e., the output is returned through its load
current limit should therefore be set on both of
these
on
VCP
to -2.0 V. Thereafter,
VCP is returned to 0 V.
supply should be set at 700 mA while the V CC sup·
Strobing of the outputs to determine success in
ply should be limited to 250 mAo
programming
It should be
noted that the VEE supply must be capable of
sink ing
VCP
the combined
supplies
while
current
of
maintaining
the
a
Vee
voltage
should
Occur
no
sooner
and
maming bits are programmed in a similar fashion.
of
-5.2 V ± 5%.
t
NOTE:
than
100 ns after VCP has returned to 0 V. The re-
For devices that program incorrectly, return serialized units with individual truth tables.
Non compliance voids warranty.
4-44
MCM 10 149/MCM 10549
PROGRAMMING SPECIFICATIONS
The
following
timing
diagrams
and
fusing
Definitions and values of timing symbols are
information represent programming specifications
as follows.
for the M CM 10149.
Vee - Pin 16 - a v
VEE
Pjn 8
-5.2 V 1:5%
Symbol
+12 V
~'05V
~ L~ ~
------J
:
iHf
trl-..l
'wl
~---
1+_·,25~~V
I
Selected OutPut Open
Pln(11
12 140rlSt
I ~
iI
0 V
I
Rise Time,
Programming Voltage
twl
Pulse Width,
Programming Voltage
tOl
Delay Time,
Programming Voltage
I
t02
'Ol'-j ,
50 rnA
;;. 100 JJ.s
<
1 ms
;;'0
tw2
Pulse Width, Bit Select
;;. 100 JJ.s
t02
Delay Time, Bit Select
;;'0
Pulse to Programming
+5mA
Chip Select Pin 13
Value
;;. 1 JJ.s
Pulse to Bit
Select Pu Ise
I
tw2
Definition
trl
0 mA---+-'
Voltage Pulse
t03
Delay Time, Bit Select
;;. 1 JJ.s
Pulse to Programming
Current Pulse
tr3
The timing diagram is shown for programming
All addressing must be done 100 ns prior to the
tw3
a
250 ns max
Pulse Width,
;;. 100 JJ.s
Programming
beginning of the VCP pulse, i.e., VCP =
V.
Likewise, strobing of the outputs to determine
success in programn1ing should occur no sooner
Current Pulse
t04
a
than 100 ns after V CP returns to
V.
Note that the fusing current is defined
Rise Time, Programming
Current Pulse
one bit. Note that only one bit is blown at a time.
Delay Time,
Programming Current
as
Pulse to Bit
a positive current out of the chip select, pin 13.
A programming duty cycle of ~ 15% is to be
Select Pulse
observed.
4-45
;;. 1 JJ.s
MCM10149/MCM10549
MANUAL PROGRAMMING CIRCUIT
+5 V
+5 V
12k
0.005
r
1
Verify
116 MC7406
0.05
"F
8.2 k
"F
J"2OL
"s
Delav
r--'--~-,
Q
680~
1/2
MC8602
Enable
Q
Current
Pulse
1/2
MC8602
Cp
Q
Program
+5V
Enable
+5 V
~
lN914
--5.2 V
(-6 V Ciampi
Curren t Sro_u_r_c_e...._ _""'~---_ _ _--,
510
510
lN914
or Equiv.
100
-5.2 V
·12 V
+5 V
+12.5V
r-----..---O+5 V
, - - -.....- - , Lim it
1/4
150
1.0
MC7438
240
1/4 MC7438
180
180 H. 1/2 W
lN914
51!!,1/2W
+5 V o--'\M~..----II*----.-----.
"0"
CS
7
"O--~----o----I A 7
1.0 k
-5.2 V
11
D3 f--<>----....- - - - O ' "
680
-S.2 V
5
~-~>----O--;A6
1.0 k
-5.2 V
1.0 k
-S.2 V
6
AS
12
10
D2
A4
1.0 k
-5.2 V
9
A3
1.0 k
-5.2 V
680
-S.2 V
MCM101491
10549
14
Dl
3
680
-5_2 V
A2
1.0 k
-S.2 V
2
"0---.-----<>--1 A
1.0 k
-S.2 V
4
1
C
Rotary SW
15
DO f--<>----+----O
680
-5.2 V
1.0 k
-5.2 V
16
4-46
Memory Boards
5-1
@
MOTOROLA
MMSll02
Advance Information
ADD-ON MEMORY CARD FOR THE LSI-11 FAMILY
The MMS11 02 is a dual height (5.187" x 8.94") add-on memory card for the LSI-11 family of computers.
It is compatible with the LSI-11/2 and LSI-11 processors as weH as the PDP 11 V03 computer systems. It
incorporates byte parity storage as well as generation and detection logic.
Specification Highlights
INTERFACE
LSI-11, "Q" Bus-Plus.
CAPACITY
8K words
PARITY
Optional on-board storage, generation and detection logic for both upper and lower byte.
Parity option does not degrade access times. ,
SPEED
The MMS 11 02-3X has a read access time under 300 ns. Read access time is defined here
as the time from receipt of SYNC H to the transmission of RPL Y H, assuming that the
SYNC H to DIN H time is no greater than 160 ns.
x
16 bits, 16K words
x
16 bits, 32K words
x
1 6 bits.
ADDRESSING
Switch-selectable, to start on any 4K word boundary between 0 and 128K.
110 PAGE USE
Three switches allow anyone of the lowest three kilowords of the 110 page to be used
as ReadlWrite memory.
BATIERY BACKUP Jumper selectable; allows the MMS1102 to be operated from a separate uninterrupted
power source (+5 BBU and + 12 BBU).
REFRESH
Implemented internal to the MMS1102 and totally transparent to the system.
5-3
MMS1102
MMS1102-XX ORDERING INFORMATION
Storllge Capacity
Part Number
(With Parity and Controller)
Part Number
(No Parity)
16 Kilobytes
MMSll02-31PC
MMSll02-31
32 Kilobytes
MMSll02-32PC
MMSll02-32
64 Kilobytes
MMSll02-34PC
MMSll02-34
MMS1102-3X -
AC
OP~RATING
CHARACTERISTICS
Writ. Ace••• (n.)
Reed Acce .. (n.)
Wor.t C..e
Typical
Worat C...
Typical
Ace••• Time-
250
300
125
175
Cycle Time-·
470
500
350
400
A.fntlh Latency···
175
400
175
400
-As measured from receipt of RSYNC H to transmission of TRPLY H.
··This is the reciprocal of the maximum continuous transfer rate. assuming no refresh interference.
···Occurs approximately once every 16 microseconds.
MMS1102 POWER REQUIREMENTS
Curr.nt Requirement. (mA)
Active
Standby
Nominal Vohllge
Min
Max
Typical
725
925'
.5 VDC (Total)
4.75
5.25
Wor.t
Cao.
Wor.t
Ca ••
Input Pin.
775
1000'
850
1100'
AA2. BA2
AD2. BD2
Typical
800
1000'
.12 VDC
11.40
12.60
100
150
250
400
.5 VDC (BBU)
4.75
5.25
400
500
450
550
AV1"
.12 VDC (BBU)
11.40
12.60
100
150
250
400
AS1'"
·Parity version only_
··In svstems without battery backup this voltage is obtained from the regular +5 V rail via an on~board jumper.
···The +12 V supply requirement can be met via an on-board jumper from the regular +12 V rail.
MMS1102 BACKPLANE CONNECTOR PIN ASSIGNMENT
A
Row
Pin
A
B
C
0
E
F
H
J
K
L
M
N
P
R
S
T
U
V
B
1
Side
2
-
+5 V
BDCOK H
-
-
BAD16 L"
BAD17 L
GND
.12 V
aDOUT L
BRPLY L
-
-
GND
},
-
-
BDIN L
BSYNC L
BWlBT L
GND
},
BIAKI L } '"
BIAKO L
GND
BBS7 L
-
BREF L
.12 V BBU
GND
BDMGI L } '"
BDMGO L
-
-
GND
-
BDAL 0 L
BDAL 1 L
.5 V
GND
-
.5 V BBU
2
1
-
-
*Must be hardwired on backplane or damage to MOS devices may result.
"Or PRTYER or PRTYCK .
••• Hardwired on MMS 11 02.
5-4
.5 V
GND
.12 V
BDAL 2 L
BDAL 3 L
BDAL
BDAL
BDAL
BDAL
BDAL
BDAL
4
5
6
7
8
9
L
L
L
L
L
L
BDAL
BDAL
BDAL
BDAL
BDAL
BDAL
10
11
12
13
14
15
L
L
L
L
L
L
®
MOTOROLA
MMSl122
J
Product Previe"",
---------_
..
_---
- - - - - - - -
-.--~-------------------
ADD-IN MEMORY CARD FOR THE LSI-ll FAMILY
The MMS1122 IS a dual height 15.19" x B94") add-on memory card for the LSI 11 family of computers It IS compatible with
LSI-11, LSI-11/2, and LSI-1L23 processors as well as PDP l1V03" computer systems It utilIZes MCM4132L 32K RAM
moduies
FEATURES
• Capacity of 32K Words, Each 16- Bits Long
•
•
•
•
•
•
Effective Capacity IS SWitch Selectable at any 1K Word Increment
AddreSSing IS SWitch Selectable to Start on Any 1K Word Boundarv
From 0 10 127K
Reild Access Time of 300 ns Imax.)
Cycle Time 500 ns Imax )
Refresh Implemented Internal to the Card ITransparentto the
System) On-Board Jumpers Permit SynchronIZation of Refresh If
Desired.
r
Relresh and~
Address
Memory Array
Mult;plexer
Jumper Selectable Battery Backup ProvIsions Allow Use of Separate
Power Source
• LSI-11 IO-Bus and O-Bus Plusl Interface Compatible
User Option
SWltches/
Jumpers
MMSl122N3032
BaSIC Pan
l=r~
No Panty
Number
Speed
(300 ns Access)
Invalid
tAH
25
-
Address Setup Time - A <0:21> Valid to MSYN I
tAS
75
-
ns
1
Processor Handshake Time - SSYN I to MSYN t
tPH
-
0
ns
I, 2
Data Hold Time IWrite CycleiDATOI - MSYNI to 0 <015> Invalid
tDHW
40
1
tDSW
15
--
ns
Data Setup Time IWnte CycieiDATOI - 0 <0:15> Valid to MSYNI
ns
1
NOTES' 1. AU timing is referenced at card edge. Operation
refresh arbitration.
IS
assumed to be
a properly term mated backplane, with memory not busy and no
In
2. Assumes handshaking occurs Immediately.
AC OPERATING CHARACTERISTICS IO'CsTAS70'CI
Characterhrtica
MMS1119X3XXX
Min Typ Ma.
Symbol
MMS1119X4XXX
Typ Ma.
Min
Unit
Note
360
-
440
425
-
ns
1
tRACC
3ro
-
330
360
-
380
430
ns
1
Data Hold Time - Read IDA Til
Cycle MSYN t to Data Invalid
tDH
70
-
-
70
-
-
ns
1
Data Setup Time - Read IDA Til
Cycle 0<0:15> Valid to SSYNI
tDS
0
-
-
0
-
-
ns
1
Memory Handshake Time - Read IDATII
or Write IDATOI Cycle MSYN t to SSYN'
tMH
-
-
75
-
-
75
ns
1
Write Access Time - MSYN I 10 SSYN'
tWACC
-
125
165
-
125
165
ns
1
Cycle Time - Write IDATOI Cycle
tWCYC
340
-
-
440
-
-
ns
1
Cycle Time - Read IDA Til Cycle
tRCYC
Read Access Time - MSYN I to SSYN I
NOTES: 1. All timing IS referenced at card edge. Operation is assumed to be In a properly terminated backplane, with memory not busy and no
refresh arbitration.
2. Assumes handshaking occurs Immediately.
WRITE CYCLE TIMING
Bus A <0:21 >
Bus 0 <0:16>
Bus MSYN L
----.:....::~-+----1-,(----'i
Bus SSYN L
tDH
t-----tWCYC---~
READ CYCLE TIMING
r:
Bus A <0:21 >
)[
Bus C <0:1 >
--......X
AS
tRACC
tAH
~
-
tPHBus MSYN L
~
-tMH
Bus SSYN L
tDS
Bus 0 <0:15> L
tRCYC
5-13
-
-tDt:j
MMS1119
TIMING
The MMS111S is fully compatible with the PDP-11
Modified and Extended UNIBUS protocol and timing. limits
are specified In the AC Conditions/Characteristics Tables in
conlunction with the DATI/DATO waveforms.
BUS INTERFACE
The M M S 11 1S is provided with a switch to select the type
of Bus to be used. With this switch closed, the Interface IS to
en Extended UNIBUS backplane 122 bit address!. The
memory operates with a Modified UNIBUS system 118 bit
addressl with this switch open.
STARTING ADDRESS
The MMS1 119 utilizes a set of switches to allow the starting address to be selected at any 4K boundary. This feature
is available regardless of the Bus Interface or Memory
Capacity option chosen. In cases where the sum of the starting address and the memory capacity exceeds the host
machine addressing capability, the capability is automatically
reduced. INo wraparound to starting address locations occurS.1
REFRESH
The storage cells in the MMS111S are implemented with
dynamic MOS RAM's. The charge stored in the cells must be
refreshed every 2 milliseconds, requiring a single refresh cycle to be initiated approximately once every 16 M Seconds.
The latency induced to bus cycles concurrent with refresh
cycles is no greater than the specified minimum cycle time
for the MMS111S version chosen.
The MMS' 11S contains circuitry to automatically refresh
the memory cells. An option is also provided to allow the
User to control the refresh externally. In this case, the
Refresh Latency will be no greater than the refresh cycle time
defined by the external cirCUitry. Note that any external
refresh circuitry must conform to the requirements previously mentioned, i.e., each cell refreshed at a 2 millisecond rate
and a refresh cycle time not less than the minimum Read Cycle time.
I/O PAGE SIZE
When the MMS111S is located in high memory, the User
may select part of the I/O page as Read/Write memory. This
is implemented via three switches, resulting in optional I/O
page sizes of 2K, 4K, or 8K words.
PARITY OPTIONS
The MMS11 1SPXXXX contains parity control cirCUitry
which is fully compatible with the DEC parity module. This
circuitry does not degrade access or cycle times, and the
Parity Control Status Register ICSRI address can be switch
selected to any standard pre-assigned bus address. 1772100a
thru 772136a for Modified UNIBUS, 1772100a thru 1772136a
for Extended UNIBUS. In any case, the CSR occupies a
single two-byte address spacel. The on-board parity circuitry
does not impose any additional bus loading on the system.
The MMS1'1SPXXXX can also be used in systems which
utilize the DEC Parity Module. The User selects this mode of
operation by opening a switch Iprovided on the MMS 11 19PI
prior to installation of the memory. The parity generation and
detection circuitry of the MMS111SP is fully compatible with
the DEC Parity Module.
The MMS1 11SNXXXX version IS available for those
systems not requiring parity. This product is supplied as a
16-bit word memory with the Internal/ External Parity Control
switch open I Externall.
AVAILABLE OPTIONS
The MMS" 1S features a variety of options, allowing its
configuration into a wide range of applications. Several of
these options are installed at the factory, witt> most of these
specified by the part number as shown in the "Ordering Information" on Page 1. Others are chosen by the User prior to
installation of the product.
MEMORY CAPACITY
The MMS1 11S utilizes either 16K or 64K RAM components to allow optional storage capacities of 64K, 96K,
128K, 256K, or 512K Words. As noted on Page 1 10rdering
Informationl, the last three digits of the full part number
identifies the total memory capacity In K Words.
1/0 SIGNAL DESCRIPTION
Signal
Type
Daacription
A<0:21 >
Input
Address lines to select memory locations AO selects byte in DATOB
0<0:15>
Bidir.
Data lines used to communicate with Master
C<0:1>
Input
Control lines to specify type of cycle
MSYN
Input
Timing control from Master. Used to start cycle
SSYN
Output
IN IT
Input
System Reset
DClO
Input
Power monitoring
Timing control used to notify Master that cycle is complete
PB
Output
P<0:1>
Bidir.
Data Parity Bits
PAR DET
Input
Indicates external parity module
INT SSYN
Output
Signal to Master that parity error has occurred
IS In
use
Slave Sync used with external parity module only
NOTE: All Signals are low assertion level.
5-14
®
MOTOROLA
MMS1128
Advance InforIllation
'PDP-ll MODIFIED UNIBUS' COMPATIBLE MEMORY SYSTEM
• Uses 16K, 32K, or 64K Dynamic RAM Chips
• Available in 32K, 48K, 64K, 96K, and 128K Word
Capacities
• Read Access Time Typically 300 ns (Measured (nslde
Buffers)
• Cycle Times as Low as 460 ns Typical
• Two Speed Options Available
• Worst-Case AC Limits Specified at Card Edge
• On-Board Parity and Parity Controller Standard
• Also Available Without Parity
• Starting Address Conflgurable at any 4K Boundary
• Automatic Internal Refresh
• Provisions for External Refresh Control
• Battery Backup Capability Standard
• Single 5-Volt Power Supply Required for 64K, 96K, 128K,
Word Versions
ORDERING INFORMATION
Z1 Zo
--rOption
BasIc Product
Parity + Controller
Desl.9nat:on
No Parity··
I
I
I
I
L y 1 head Access I
I
I
3
4
I
I
300 ns I typl
350 ns I,ypl
I
I
1
Z2
Z1
Zo
0
0
0
0
3
2
1
•• Available on special order
NOTE K
5-15
Capacl~;32 K Words
4
8
48 K Words
6
4
64 K Words
9
6
96 K Words
2
8
128 K Words
1024, Word = 16 Bits WIO, 18 Bits With Panty
MMS1128
I/O SIGNAL DESCRIPTION
Signal
Typa
A <0:17>
Input
0<015>
Bidirectional
C <01>
MSYN
Input
Control lines to specify type of cycle
Input
Timing control
SSYN
Output
INIT
Input
System Aeset
OCLO
PB
Input
Power monltonng
Description
Address lInes to select memory locations AO selects byte
In
DATOS.
Data lines used to communicate with Master
~rom
Master. Used to start cycle
Timing control used to notify Master that cycle is complete.
Output
Signal to Master that parity error has occurred
P <0:1>
PAA OET
Bidirectional
INT SSYN
Output
Input
Data Parity Bits
Indicates extend parity module In use.
Slave Sync used WIth external parity module only
NOTE: All signals are low assertion level
ABSOLUTE MAXIMUM RATINGS
Rating
Lim~
Symbol
voo
Supply Voltage IAelatlve to Groundl
Input Voltage (Any input relative to GNOJ
NOTES: 1. Permanent damage may occur If Absolute MaXimum Ratrngs are exceeded.
Recommended Operating Conditions.
2. Permanent damage may also occur if VOO
IS
Min
Max
-0.3
20.0
VCC
-0.3
7.0
VBB
- 20.0
0.3
Vn
-OJ
5.5
UnM
Vdc
Vdc
Functional operatIon shall be restncted to
applied for more than one second while VBB is outside its Recommended Operating
Aange.
ENVIRONMENTAL RATINGS
Rating
Operating Temperature
Storage Temperature
Relative Humidity (Without Condensation)
Symbol
Limit
Un~
TA
o to 55
Tstg
AH
-40 to +B5
'c
'c
o to 90
%
RECOMMENDED DC OPERATION CONDITIONS
Parameter
Symbol
Lim~
Min
Max
Un~
Note
Supply Voltage
- Nominal + 15 V or nominal + 12 V, pon AAI
VOO
- Nominal + 5 V, pins AA2, BA2, CA2
VCC
VCC/BBU
- Nomrnal + 5 V BBU, pin BOI
- Nominal - 15 V or nominal - 12 V, pm AS 1
NOTES. 1. + 15 V or + 12 V
IS
VBB
lumper selectable on all modules populated With 16K AAMs.
1,3
14.50
16.50
11.40
12.60
4.15
4.15
5.25
5.25
~
-7.00
-20.00
3:"4
Vdc
-----;-
2 Pins AA2, BA2, and CA2 are connected together on the MMSl128.
These voltages must be present on cards populated With 16K RAMs if Battery Back Up IS required. Only VCC/BBU need be
present for cards populated With 32K or 64K RAMs.
4. VOO and VBB not reqUired for cards populated with 32K or 64K RAMs.
5-16
MMS1128
WRITE CYCLE TIMING (DATOI
tAS-...._---twACC - - -.....
Bus A <0:17> L
BusC <0:1> L
Bus D <0:15> L
Bus MSYN L
Bus SSYN L
~---------twCYC--------~~
READ CYCLE TIMING (DATil
tAH ......
_tAS
Bus A <0:'7> L
'/;:
BusO<0:1>L
'//
f-
tRACC
:1///////
-
Bus MSYN L
'L/IIII~
~tPH
f-tMH
J
Bus SSYN L
t DS
Bus D <0:15> L
tACYC
5-17
-1
. . ~tDH:1
MMS1128
DC OPERATING CHARACTERISTICS (0° < T A < 55°C)
Capacity
(K Wo,dal
Characteristic
Mode
Symbol
Min
Limit
Typ
Ma.
Units
Notes
Adc
1, 2
1
Supply Current
32,48
Active
100
0.25
0.50
32,48
Standby
100
0.16
030
- Nominal + 5 V Supply
32,48
ActfStby
ICC
120
150
Adc
-
Nominal + 5 V BBU
32,48
BBU
ICC
0.55
0.80
Adc
1
-
Nominal + 5 V Supply
64,96, 128
64,96, 128
Act/Stby
ICC
1.60
2.25
Adc
1
BBU
ICC
0.80
115
Adc
1
32,48
All
IBB
12
20
mAde
1, 2
Vdc
IIH
15
Any Input, VIL =0.4 Vdc
IlL
- Nominal + 15 V or + 12 V Supply BBU
- Nominal + 5 V BBU
- Nominal - 15 V or - 12 V Supply BBU
Logic "1" Input Current - Any Input, VIH
Logic "0" Input Current Logic"'" Output Current V Bus ~ 4.0 Vdc
~4.0
Any Output,
Logic "0" Output Voltage - Any Output,
IOL ~50 mAdc
Any Input
Input Threshold Voltage
High Logic State
Input Threshold Voltage - Any Input low LOQic State
50
~Adc
3
-16
mAdc
3
VOH
20
100
~Adc
3
VOL
0.4
0.70
Vdc
3
VILH
1.80
2.25
2.50
Vdc
VIHl
1.05
1.30
1.55
Vdc
NOTES· ,. Active Mode = Memory accesses at maximum continuous rates; Standby Mode = Internal Refresh Cycles only; Battery Back Up
(SBUI = Standby Mode With + 5 V applied only through Pin 801
2. + 15 VI + 12 V and - 15 VI -12 V supplies not reqUIred for products populated with 64K RAMs
3. Negative Sign = Current out of pin. MinIMax limits refer to absolute values of current
AC OPERATING CONDITIONS
Parameter
Symbol
Umil
Min Max
50
Address Hold Time - MSYN to A<017> Invalid
tAH
Address Setup Time - A < 0: 17 > Valid to M SYN
tAS
tpH
75
tDHW
40
Processor Handshake Time -
SSYN to MSYN
Data Hold Time IWrote Cycle/DATO)
Data Setup Time IWrote Cycle/OATOI NOTES:
MSYN to 0 <0:15> Invalid
0
Unit
Note
ns
1
ns
1
ns
1, 2
ns
1
<015> Valod to MSYN
All timing IS referenced at card edge Operation
no refresh arbitration
1:3
15
ns
1
tosw
assumed to be In a properly terminated backplane, With memory not busy and
2. Assumes handshaking occurs Immediately
AC OPERATING CHARACTERISTICS (O°C < T A < WCI
Cycle Time -
Read (DATil Cycle
Read Access Time Data Hold Time -
MSYN to SSYN
Read (DATil Cycle MSYN to Data Invalid
Data Setup Time - Read IDATII
Cycle 0 <0:15> Valod to SSYN
Memory Handshake Time - Read IDATII or
Write IDATO) Cycle - MSYN to SSYN
Write Access Time - MSYN to SSYN
Min
IS
MMS1128X4XXX
Typ Me.
Min
Unit
Note
tRCYC
460
515
510
565
ns
1
tRACC
330
300
3BO
430
os
1
70
ns
1
ros
2
75
ns
1
165
ns
1
70
tDH
tDS
0
tMH
25
tWCYC
assumed to be
Timing is referenced Inside Bus Onvers.
5-18
0
75
125
tWACC
Cycle Time - Write IDATOI Cycle
NOTES. 1. All timing IS referenced at card edge OperatIon
no refresh arbitration
MMSI128X3XXX
Typ Max
Symbol
Chirecteriatici
In
165
25
125
1
ns
325
340
425
440
a properly terminated backplane, with memory not busy and
MMS1128
TIMING
the last three digits of the full part number Identifies the total
memory capaCIty in K Words.
The MMS 1128 IS fully compatible with the PDP-11
Modified UNIBUS protocol and timing. Limits are specified
in the A.C. ConditlOnslCharactenstlcs Tables In conlunction
with the DATIIDATD waveforms.
STARTING ADDRESS
The MMS 1128 utilizes a set of SWitches to allow the startIng address to be selected at any 4K boundary. ThiS feature
IS available regardless of the Memory Capacity option
chosen. In cases where the sum of the starting address and
the memory capaCIty exceeds the host machine addreSSing
capability, the capability is automatically reduced INa
wraparound to starting address location occurs. I
REFRESH
The storage cells in the MMSl128 are Implemented with
dynamic MDS RAM's. The charge stored in the cells must be
refreshed every 2 milliseconds, requiring a single refresh cycle to be Initiated approximately once every 16 milliseconds.
The latency induced to bus cycles concurred with refresh
cycles IS no greater than the specified minimum cycle time
for the M M S 1128 version chosen.
The M M S 1128 contains circuitry to automatically refresh
the memory cells. An option is also provided to allow the
User to control the refresh externally. In thiS case, the
Refresh Latency will be no greater than the refresh cycle time
defined by the external circuilry. Note that any external
1/0 PAGE SIZE
When the MMS2118 IS located In high memory, the User
may select part of the 1/0 page as ReadlWrlte memory ThiS
IS Implemented via three switches, resulting In optional 1/0
page sizes of 2K, 4K, or 8K words.
PARITY OPTIONS
The MMS2118PXXXX contains parity control circuitry
which is fully compatible With the DEC parity module. ThiS
circuitry does. not degrade access or cycle times, and the
Parity Control Status Register (CSRI address can be SWitch
selected to any standard pre-aSSigned bus address. (772100s
through 7721368.1 In any case, the CSR occupies a Single
two-byte address space. The on-board parity circuitry does
not impose any additional bus loading on the system.
The MMSl128PXXXX can also be used in systems which
utilize the DEC Parity Module. The User selects this mode of
operation by inserting a lumper pnor to installation of the
memory. The parity generation and detection circuitry of the
MMSl128P IS fully compatible With the DEC Parity Module.
The MMSl128PXXXX version is available for those
systems not requiring panty. ThiS product IS supplied as a
16-bit word memory with the Internal! External Parity Control
switch open IExternali
refresh circuitry must conform to the requirements prevIous-
ly mentioned, i.e., each cell refreshed at a 2 millisecond rate
and a refresh cycle time not less than the minimum Read Cycle time.
AVAILABLE OPTIONS
The MMS1128 features a variety of optIOns, allowing its
configuration Into a wide range of applications. Several of
these options are installed at the factory, with most of these
specified by the part number as shown in the "Ordering InformatIOn" on Page 1. Others are chosen by the User pnor to
installation of the product.
MEMORY CAPACITY
The MMSl128 utilizes 16K, 32K, or 64K RAM components
to allow optional storage capacities of 32K, 48K, 64K, 96K,
or 128K Words. As noted on Page 1 (Ordering InformatlOnl,
5-19
@
MOTOROLA
MMSl170
Product Pre v Ie,",
MEMORY ARRAY CARD FOR PDP*-11170
The MMS1170 is a dynamic memory array system
specifically designed for use In PDP-11170 minicomputers
from Digital Equipment Corporation. The array has a capacity of 64K double words 1256K bytesl using 16K RAM chips.
It is hardware and software compatible with the PDP-11170
memory controller module and DEC diagnostics.
The MMS1170 is designed to occupy a single hex slot of
the DEC MK-11 Memory System chassis. It features an On
Line/Off line switch Iwith an LED indicator) to facilitate
trouble-shooting. A separate LED indicates when battery
backup voltage is available via the backplane connector.
All RAMs used on the MMS1170 are socketed. Two spare
16K x 1 RAMs are provided on the board. The product is fully burned-in and covered by the Motorola Memory System
One-Year limited Warranty.
ORDERING INFORMATION
r
ECC
BasIc Part No
NOTE Double Word
·PDP 15
~
Speed Option
32 Date and 7 ECC Bits
a trademark of Digital EQUipment Corporation
5-20
5"8164 x 1024 Double Words)
MMS1170
ENVIRONMENTAL RATINGS
Symbol
Rating
Operating Temperature
TA
Storage Temperature
T St9
RH
Relative Humidity (Without Condensatton)
limit
o to
Units
+ 50
'C
-40 to +00
'C
o to 00
%
PHYSICAL DIMENSIONS
Dimen8ton
Width
HeIght
PC Board Thickness
Clearance ReQuired (Component Side)Clearance Required (Solder Sidel-
Millimeters
Inches
39.85
22225
0.142
0.952
0.254
15.688
8.75
0.056
0.375
0.10
-Measured from surface of PC Board
POWER REQUIREMENTS
Maximum Current Requirements
Operating Standby Battery Backup
Input Voltage
+12 B
+5V
-12 B
+5 VB
1.5
0.4
0.04
0.9
0.25
0.35
002
0.8
0.25
0
0.02
0.8
Un~.
Adc
Adc
Adc
Adc
AC OPERATING CHARACTERISTICS
Nominal··
650
680
320
70
Characteristic
Cvcle Time Access Time -
Read
Write
Read
Write
Un~
ns
ns
··The actual response times are determined by DEC MK-l1 Memory System Controller design. Nominal values shown are for reference only.
5-21
®
MOTOROLA
MMS780
Advance InforIllation
MEMORY ARRAY CARD FOR VAX-11 1700·
The MMS780 is a dynamic memory array system specifically designed for use in VAX-11 1780 minicomputers
from Digital Equipment Corporation. The array has a capacity of 32K words 1256K Bytesl using 16K RAM chips. It
is fully compatible with the VAX-111780 memory controller module.
;' M~
~ foooj ~
~'IIII'l) ~
~. . . .
,1.· [.
....
....:::..
"" ~'fjf][~ eM .,~
.l1li i ' . ""
.
...
~
~ ~. ~.
,..
-
R2
~
••
1""'
II
'11
l~
ORDERING INFORMATION
MM S780AE1032
BaSIC~
iii
ECs~eed IOP1IDn
I
SIZe IK Words I
Note K = 1024
Word = 64 Data + 8 ECC Bits
·VAX is a trademark. of Digital Equipment Corporation
5-22
MMS780
ENVIRONMENTAL RATINGS
Symbol
Rating
Operating Temperature
TA
Storage Temperature
Tst9
RH
Relative Humidity (Without Condensation)
Limit
o to
Unita
-4Oto +!Kl
·C
·C
o to 90
%
+56
PHYSICAL DIMENSIONS
Width
MHlimetera
39.85
Height
:Jl.48
12.0
PC Board Thickness
0.142
0.056
Clearance Required (Component Side'-
0.952
0.375
Clearance Required (Solder Side)-
0.254
0.10
Dimension
Inchee
15.688
• Measured from surface of PC Board
POWER REOUIREMENTS
+ 12 V
Maximum Current Requirementa
Unita
Standby Battery Backup
1.5
0.25
0.25
Adc
+5 V
-5V
0.04
0.6
0.02
0
0.02
Adc
Adc
+ 5 V Battery
0.9
0.8
0.8
Adc
Input Voltage
Operating
0.7
AC OPERATING CHARACTERISTICS
Characteristic
Nominal··
5:J)
Cycle Time - Read. Refresh, or Init.
- Readl Modify IWrite
1100
Access Time - Read
- Write
250
750
Unita
ns
ns
• -The actual response times are determined by VAX-111780 Memory Subsystem Controller design. Nominal values shown are tor reference
only
OPERATING PRINCIPLES
The MSM780 is based on 16K x 1 dynamic RAMs arranged
in two banks, each containing 72 chips. The 72-bit word thus
formed is subdivided into two 32-bit long words (Upper and
Lower! and eight ECC bits. All memory array accesses correspond to a Read from, or write to, the selected 72-bit
word. (All 8, 16, and 32 bit memory operations are
transformed into 72 bit accesses by the memory controller. J
The memory array selection is accomplished via address
lines (ADR19:ADR16J and four select signals at the Memory
Subsystem Backplane This Backplane has 16 slots
dedicated for memory array cards, with the select signals
uniquely specified for each slot. This arrangement eliminates
the need for special lumpers and address switches. The
MMS780 is merely inserted in the next available backplane
slot. A total of 4 Megabytes of memory can be accomodated
by one Memory Subsystem.
5-23
USAGE RECOMMENDATIONS
The MMS780 is recommended for use with any
VAX-ll/780 memory subsystem set up for operation with
the DEC M8210 array card. It is hardware and software compatible with the VAX-11/780, including DEC diagnostics
which allOW failure isolation at the chip level. The MMS780 is
also compatible with DEC battery backup proviSions.
INTERFACE
The VAX-11/780 computer system is normally configured
with either one or two memory subsystems, as shown in
Figure 1. The normal interface signals ut;lized within each
subsystem are depicted in Figure 2. The MMS780 Array
Module functions in any slot of either subsystem, with no
modifications required.
MMS780
FIGURE 1 - NORMAL VAX-ll/780 MEMORY CONFIGURATION
VAX-111780
CPU
Cache Memory
Synchronous Backplane Interconnect
4,"
....
,r.
:
I
'OJ ,7
_----,
,,
r--~--'
2-16
Memory
:
I
I
I
Memory
Controller
Array Cards
roC::::::::'i
,
I
I
:
,
~
•
Optional
Memory
Controller
"I
,: ," '---~ ' M 0-16
{
~
I' :I :I •I
emory,.
! I~AI-A
L
_____ _ J-I
. " ,.. __ ,,'1 Array Cards
'~i'
______ J
'
I
IMMS7801
IMMS7801
FIGURE 2 -
,.'------, I
I I :
rt------,
MEMORY SUBSYSTEM INTERFACE
.---M
E
M
Memory
I-------~~
Slot Select < SLOT03:SLOToo>
y
I - - - - - - -____
Memory
o
Controller
Board Select Addr.
)
V
Base Chip Addr.' ' )
~----~~
/
V
ECC Bits < C07:Coo>
T
E
M
C
K
-)
~
' - -_ _ _--J
~
E
~L----EC-C--Bi-ts-<--C-07-:C-oo-->----~~
I( .
'---
~
V
A
Data ' )
_ _ _-l~
Control Signals" 181
N
~
V
~_
L
A
N
»
V
P
V
~
Base Chip Addresses < ADAI2:ADAOI
~
V
Control Signals" 181
Extended Addresses'
S
I~
V
~
Data ' \
/
L-_ _ _--J
'Extended Addresses are labeled ADA13, ADACS, and ADA EXT. During normal operation, they correspond to > ADAI5:ADAI3<
··Control signals are: Read. Column Address Strobe (CAS), Row Address Strobe (RAS). Multiplexer Control, Refresh Cycle, Bus Select, Bus Output Enable. and Initiate.
5-24
®
MMS8064(P)
MMS8048(P)
MMS8032(P)
MMS8016(P)
MOTOROLA
Advance Information
SBC-COMPATIBLE MEMORY SYSTEMS
The MMSBOXX family of memory systems is designed
for use with the Intel SBC BO Series computers. System
BO microcomputers. MDS systems. and the 16-blt SBC
B6/12. The modules employ 16K dynamic RAM's
mounted on a single 6 3/4" X 12" PC board along with
timing, control. and bus interface logic. Eight models are
available. all having the same access and cycle times All
electrictfl connections are made via two edge connectors
•
Pin. Function. and Form-Factor Compatible with
MULTIBUS' Systems
•
Even/Odd Bank Address Allows 16-Bit or B-Blt
Operation
• Addresses Selectable
•
20 Address Lines -
In
Independent BK Blocks
Operates in 1 M Byte System
•
Handles Early or Late Inhibits
•
Operates in Delayed Write. Advance Write. and Read
Modes
•
Battery Backup Capability through use of Memory
-Protect Signal on P2 Connector
•
On-Board Refresh Control Circuitry
•
Programmable Advanced Acknowledge (AACK/)
Signal
• On-board VBB Generation (-5 V) Allows Operation
from 12 V. +5 V. and -12 V. -10 V. or -5 V Supplies
•
Cycle Times of 700 ns (Read. Delayed. Write) and
1240 ns (Advanced Write)
• Available In 16K. 32K. 4BK. and 64K Byte
Configurations
PHYSICAL CHARACTERISTICS
ORDERING INFORMATION
No Parity
MMS8064
Parity
Capacity
Charlcteristic
limit
MMS8064P
64K Bytes
Width
3048 cm (12 00 Inches)
MMS8048
MMS8048P
48K Bytes
Depth
17 15 em (6 75 Inches)
MMS8032
MMS8032P
32K Bytes
Thickness
t 27 em (0 50 Inches)
MMS8016
MMS80t6P
16K Bytes
Weight
397 grams (140 ounces)
'Trademark of Intel. Inc
5-25
MMS8064(p)eMMS8048(p)eMMS8032(p)eMMS8016(P)
AC OPERATING CONDITIONS
limit
Parameter
Read or Delayed Write Cycle
Advanced Write Cycle
Cycle Time
Address Setup Time
Address Hold Time
Symbol
Min
Unit.
Notel
tCYC
tCYC'AI
700
1240
ns
1.2
1.2.3
Address Valid to MADC/' or MWAC/I
tAS
50
ns
MADCII or MWRC/I to Address Invalid
tAH
0
ns
Data Valid to MWACI j
tDSW
-100
ns
Write Data Setup Time (Delayed Write)
Write Data Oelay Ti me
(Advanced Write)
MWACI I to Data Invalid
Byte High Enable Setup Time
Byte High Enable Hold Time
tDHW
0
ns
!)S1
!)S2
10
-50
ns
Early Inhibit
Inhibit Setup Time
INHII Valid to MADC/j or MWAC/I
Late Inhibit Option Installed
MADC/I or MWACI j to INHI Invalid
tlH
100
ns
BHENI Valid to MRDCI j or MWACI I
tBS
50
ns
MADC/' or MWACII to BHENI Invalid
tBH
0
ns
15
iJs
< 475
Memory Protect Setup Time
MPAO/j to VCC
Vdc
tMPS
Memory Protect Hold Time
VCC ? 4 75 Vdc to MPRO/I
tMPH
0
tAl
12.7
Refresh Interval
NOTES
ns
500
tDDAW
Write Data Hold Time
Inhibit Hold Time
Me.
3
ns
15.6
ms
Typ
Max
Units
Notes
400
450
ns
1.3
1) Add Refresh Delay Time (TRO) to these parameters when Asynchronous Refresh occurs
2) Add 40 ns (Typ), 50 ns (Max) to these parameters If Late Inhibit Option is Installed
3) Applicable only if Advanced Write Cycle option IS installed
AC OPERATING CHARACTERISTICS (O"C <- TA <- 55'C)
Limit
Symbol
Parameter
MADCI j to Data Valid
tAce
Aead Data Valid to XACKI j
tDSA
0
XACKI I to Data Invalid
tDHA
0
MADC/I or MWTC/j to AACK/I
tAAK
-
MADC/j or MWTC/j to XACK/j
tACK
Read Access Time
Read Data Setup Time
Aead Data Hold Time
Advance Acknowledge
Delay Time
Transfer Acknowledge
Delay Time
Acknowledge Turn-Off Time
Panty Error Setup Time
Parity Error Hold Time
1)
2)
3)
4)
5)
ns
-
MADC/I or MWTC/I to AACK/I or
XACK/I
tTD
15
PAA EAAI Valid to XACK/j
tps
0
XACKI j to PAR EAAI Invalid
tPH
50
65
ns
-
ns
1.4.5
50
ns
1.2
55
ns
ns
ns
ns
550
tDA
Refresh Delay Time
NOTES
Min
Add 40 ns (Typ). 50 ns (Max) to these parameters If Late Inhibit option IS Installed.
Add 450 ns (Typ), 500 ns (Max) to these parameters for Advanced Write Cycle operations.
Add Refresh Delay Time (tAD) to these parameters when Asynchronous Refresh occurs
See Advance Acknowledge options table for Delay Time
Advance Acknowledge IS delayed until Transfer Acknowledge Time If Asynchronous Refresh occurs
ADVANCE ACKNOWLEDGE OPTIONS
The MMS8060 Series can be programmed 10
prOVide an ADV ACK Delay (tAAKI of 10010
450 ns. Available options are as noted In table
at right_ Selection IS made via installation of a
smgle jumper between two terminals of a 16
pm DIP socket. (Jumper between pinS 8 & 9 -lOOns Typ. between 1 &. 16 - '50 ns. etc)
Option Selected
Limit
8-9
1 -16
7-10
2-16
3-14
6-12
4-13
6-11
Units
Min
70
120
165
215
260
310
360
400
ns
Typ
100
150
200
250
300
350
400
450
ns
Ma.
125
175
230
285
335
400
450
500
ns
5-26
MMS8064(p)eMMS8048(p)eMMS8032(p)eMMS8016(P)
ABSOLUTE MAXIMUM RATINGS
limit
Symbol
Min
Max
Units
Nominal .,-5 Vdc
Vee
-03
+70
Vde
Nominal + 12 vdc
VDD
-03
+150
Vde
VBB
·03
+03
-70
-15.0
Vde
Vde
VtN
-03
+55
Vdc
Rating
Power Supply Voltage
(Measured at Connector
P 1 or P2 With Respect
to GND)
Nominal ·5 Vdc (Negative voltage regulator disabled)
Nominal -'0 Vdc or -12 Vdc (Negative
r---
vQlt~ge
regulator enabled)
Input Voltage. Any Input (Measured at Pl or P2 Conn With Respect to GNO)
NOTES
1) Permanent damage may occur If Absolute Ma)(lmum Ratings are exceeded Functional operation should be restncted to
Recommended Operating Conditions
2) Permanent damage may also occur If VOO
IS
applied for more than one second while Ves
IS
outside
Its
Recommended
Operating Range
ENVIRONMENTAL RATINGS
Limit
Rating
Symbol
Min
Ma.
+55
+85
Unit
TA
90
%
Storage Temperature
T9tg
0
-40
Relative Humidity (Without Condensation)
R.H
0
Symbol
Min
Ma.
Units
Nominal +5 Vdc
Vee
475
5.25
Vde
Nominal .,2 Vdc
VDD
114
12.6
Vde
Nominal ·5 Vdc (Negative voltage regulator disabled)
Nominal -'0 Vdc or -'2 Vdc (Negative voltage regulator enabled)
VBB
-475
-95
-5.25
-126
Vde
Operating Temperature
°C
°C
RECOMMENDED DC OPERATING CONDITIONS
Limit
Condition
Supply Voltage
Logic Zero Input Voltage, Any Input
Vil
-03
+08
Vde
Logic One, Input Voltage, Any Input
VtH
+20
+525
Vde
Max
Units
DC OPERATING CHARACTERISTICS (O"C <
- TA < 55°C)
limit
Parameter
Symbol
Min
Typ
Supply Current
Nominal +5 Vdc
ICC
3.0
Ade
(Normal Mode)
Nominal + 12 Vdc
IDD
260
mAde
Nominal -5 Vdc (Negative voltage regulator disable.d)
Nominal -'0 Vdc or -12 Vdc (Negative voltage regulator enabled)
IBB
14
30
mAde
mAde
Supply Current
Nominal +5 Vdc
ICC
11
Ade
(Battery Backup Mode)
Nominal +'2 Vdc
IDD
90
mAde
Nommal -5 Vdc (Negative voltage regulator disabled)
Nominal -10 Vde or -12 Vdc {Negative voltage regulator enabled}
IBB
72
14
mAde
mAde
logic One Input Current
(Vee = 4.75 Vde, VIH = 2.4 Vde
DATO/-DATFI
All Other Inputs
IIH
250
40
/JAde
/JAde
Logic Zero Input Current
(Vee = 5.25 Vde_ Vil = 0.4 Vde)
DATOI-DATF:
An Other Inputs
III
-600
-400
/JAde
/JAde
All Outputs
Logic One Output Voltage
(Vee = 475 Vde, IOH = -5 mAde)
All Outputs
Logic Zero Output VoltagE:
(Vee = 4.75 Vde, IOl = 48 mAde)
5-27
VOH
1---:-:-VOL
24
Vde
0.5
Vde
MMS8064(p)eMMS8048(p)eMMS8032(p)eMMS8016(P)
BASIC CYCLE TIMING
'CYC
Address
MWRC/ ________________
~
or
MRDCI
AACKI
XACKI
INHII
BHENI
/
MRDCI
DATA
XACK
~~-----
PARERR------------------
DELAYED WRITE CYCLE TIMING
MWRCI
r--'DSW)~--::1
DATA-------~
r-""W
p->-----------
ADVANCED WRITE CYCLE TIMING
~I
j
\
DATA _________
~~!_.~~~=~~=~~=~=-_'-D~D~A~W~~=~==~=-_~=-_~=-~~!-----------------'-D-H--W~ ~
5-28
MMS8064(p)eMMS8048(p)eMMS8032(p)eMMS8016(P)
P1 CONNECTOR PIN ASSIGNMENTS
Signal Name
Symbol
Pin No.
Signal Name
Symbol
Pin No.
Signal Name
Ground
Ground
VSS
VSS
VSS
VSS
VDD
Vee
Vee
Vee
Vee
VBB
VBBl
VBB2
XACKI
1. 2
11.12
75. 76
85. 86
7.8
3. 4
5.6.
81.82
1:13. 1:14
9.10
77.78
79. 80
23
Address Lme 0
Address Line 1
ADROI
ADR1/
ADR2I
ADR31
ADR4/
ADR5/
ADR61
ADR7/
ADRI:I!
ADR9!
ADRAI
ADRBI
ADRCI
ADRDI
ADREI
ADRFI
ADR101
ADR111
ADR121
ADR131
57
58
55
56
53
54
51
52
49
50
47
48
45
46
43
44
28
30
32
34
Memory Read
Command
Ground
Ground
+12 V Supply
+5 V Supply
+5 V Supply
+5 V Supply
+5 V Supply
-5 V Supply
-10 V Supply
-12 V Supply
Transfer
Acknowledge
AAeKI
25
Command
Inhibit
INH11
24
8yte H;gh
BHENI
27
Advance
Acknowledge
Enable
Address line 2
Address
Address
Address
Address
Address
Address
Address
Address
Address
Line
Line
LIne
Line
Lme
line
LI ne
Li ne
Li ne
Li ne
Line
Line
3
4
5
6
7
B
9
A
B
C
0
E
Address
Address
Address
Address
Address
Une
Line
Lme
Line
Line
F
10
11
12
13
Address
Address
Address
Memorv Write
Symbol
Pin No.
MRDCI
MWTCI
19
20
DATO/
DATlI
DAT2/
DAT31
DAT4/
DAT51
DAT6!
DAnl
DAT81
DAT91
DATAl
DATBI
DATCI
DATD,
DATEI
DAlF/
73
74
71
Command
Data
Data
Data
Data
Data
Data
Data
Lme
Line
Lme
Line
Line
Lme
Line
0
1
2
3
4
5
6
Data line 7
Data
Data
Data
Data
Data
Data
Data
Data
Line
Une
Lme
Line
Line
Une
Lme
Lme
8
9
A
8
C
0
E
F
72
69
70
67
68
65
66
63
64
61
62
59
60
NOTE: Pins not listed are not connected to Memory System circuitry
P2 CONNECTOR PIN ASSIGNMENTS
Signal Name
Memory Protect
Parity Error
Test Point - Advanced Write
Test Point - Refresh Clock
Test Po;nt - Parity 0 & 1
Symbol
Pin No.
MPROI
PAR ERRI
Tp·ADVW
TP·REFCLK
Tp·PART 0 & 1
20
29
38
40
42
Symbol
Pin No.
lP·PARl2 & 3
VSS
Vee (BAn)
VDD(BAn)
VBe (8An)
44
1.2
3. 4
Signal Name
Test Po;nt - Par;ty 2 & 3
Ground
+5 V (Battery)
+12 V (Battery)
-5 V (8attery)
9.10
NOTE' PinS not listed are not connected to Memory System cirCUitry
MMS80XX SYSTEM
Description
Signal (Pl)
ADRO/·ADRF/
Lower Order Address used to select 1 location out of 64K· block
ADR10·ADR·131
High Order Addresss used to select one 64K block out of 1024K
DATOI·DAn/
Data signals for 8-bit mode or lower byte of data signals for' 6-bit mode
DAT8/·DATFI
High order byte data signals for 16-blt mode
AACKI
(Programmable - 8 timing selections) Advanced Acknowledgement Signal from Memory Card in response to
MWTCI or MRDC
XACKI
Acknowledgement Signa: from Memory Card Indicating that Data Transfer has occurred
MRDCI
Signal to Memory Card requesting to read RAM memory
MWTc/
Signal to Memory Card requesting to write data into RAM memory
INH11
Signal disabling response of the Memory card to MWTC/ and MRDel
BHENI
Signal used to enable the 16-bit mode of operation
Description
Signal (P2)
MPROI
Signal used to enable the transfer from normal voltages to battery back-up voltages by disabling all cirCUits except
refresh. Can also be used separately from battery back-up to do same thing
PAR ERRI
Signal used to indicate a Parity Error
Tp·ADVW
Test Point Signal used to select Advanced Write Mode
Tp·REF C/K
Test Point Signal used to clock refresh flip-flop externally (used only for evaluation purposes)
Tp·PART 0 AND 1
Test Point Signal used to force a Parity Error on Reading Banks 0 or 1
TP·PART 2 AND 3
Test Point Signal used to force a Parity Error on Reading Banks 2 or 3
·K = 1024 Bytes
5-29
MMS8Q64(p)eMMS8048(p)eMMS8032(p)eMMS8016(P)
GENERAL DESCRIPTION
series allows the user to select an Advance-Acknowledge
Delay Time of 100 to 450 ns (in 50 ns Increments) This
facilitates tailoring of the memory response time to the
system speed.
An Inhibit Input is provided With the MMSBOXX series
to allow the Bus Master to turn off the memory for certain
operations. In general, the system activates this signal
prior to a Memory Read (MRDC/) or Write IMWRC/)
command. In certain types of systems, however, the
Inhibit signal arrives after the Read/Write command. A
lumper option is provided with the MMSBOXX Series,
allowing the Inhibit input to respond to a "Late Inhibit"
signal. This option should be Installed only if the system
requires it, since It slows the Memory System response by
approximately 50 ns.
Most SBC systems utilize a "Delayed Write" command
wherein the Data is available coincident With activation of
MWRC/. Some systems, however, utilize an "Advanced
Write" technique, with the data becoming valid some 500
ns after the Write Command. A jumper option is provided
with the MMS80XX series to allow operation In the Write
Cycle. Transfer Acknowledge (XACK/) is inhlbiied during
the dummy cycle, but Advance Acknowledge (AACK/)
occurs if programmed to do so. XACKI then occurs during
the actual Write Cycle unless the system has responded
to the AACKI signal. (In this case, system response to the
AACKI Signal is defined as a deactivation of the MWRCI
Input). Selection of the "Advanced Write" option does not
affect Read Cycle operations.
In general, SBC backplanes provide -5 volts at pins 9
and 10 of connector Pl. Some systems. however, provide
only -10 volts at pins 77 and 78 and/or -12 volts of pins
79 and BO. The MMS80XX Series contain an on-board
negative 5 volt regulator to allow operation with such
systems.
The MSM80XX series is designed for operation with
SBC/BlC 80 Series Single-Board Computers (including
the SBC 86/12 16-bit computer). System 80 Series
Microcomputers. and Intel MDS Systems The four
configurations are plug-In replacements for
Intel/National SBC/BlC 016. 032. 048. 064 memory
cards.
OPTIONS
The MMS80XX series is available in foUl population
options. Each of these configurations can be obtained
with or without parity. (See Ordering Information on Page
1.) In addition to the population and parity options,
provisions are made to allow the user to configure the
memory card to meet system requirements. The primary
user options are Address Selection. AdvanceAcknowledge Response time. Early/late Inhibit optIOns,
Advanced/ Delayed Write selection. and -5 Vdc
derivation.
Address Selection options allow the user to locate the
memory card in anyone of sixteen memory segfflents with each of these segments defined as a 64K memory
space. If the MMS8064 IS chosen, the memory system
responds to all addresses within the selected memory
segment. When depopulated modules (8016/80321
8048) are used, address selection for ,ndependent 8K
Byte blocks is provided. The MMS8048. for example, can
be configured to respond to 6 of the eight 8K blocks In the
chosen segment.
Advance Acknowledge is utilIZed to prevent initiation of
unnecessary processor "Walt" states. (In effect, the
signal indicates that the memory transfer will be
completed during the current cycle). The MMS80XX
5-30
Mechanical Data
6-1
MECHANICAL DATA
The packaging availabil ity for each device is indicated on the individual data sheets. Dimensions
for the packages are given in this section.
-----------14-PIN PACKAGES-----------
g.
FRIT·SEAL CERAMIC PACKAGE
CASE 632
8~
7~
I
-ll--o J
F
MILLIMETERS
MIN
MAX
19.05 19.94
6.10
7.49
B
C
5.08
D
0.38
0.58
1.40
1.77
F
2.54 esc
G
1.91
H
2.29
0.20
0.38
J
5.08
K
3.18
L
7.62 esc
150
M
N
0.51
1.02
INCHES
MIN
MAX
0.750 0.785
0.240 0.295
0.200
0.015 0.023
0.055 0.070
0.100 esc
0.075 0.090
0.008 0.015
0.125 0.200
0.300 esc
150
0.020 0.040
DIM
A
-
NOTES:
1. ALL RULES AND NOTES ASSOCIATED
WITH MD·OOI AA OUTLINE SHALL APPLY.
2. DIMENSION "L" TO CENTER OF LEADS
WHEN FORMED PARALLEL.
3. OIMENSION "A" ANO "8" (632·061 DO
NOT INCLUOE GLASS RUN·OUT.
4. LEADS WITHIN 0.25 mm (0.010) OIA
OF TRUE POSITION AT SEATING PLANE
AND MAXIMUM MATERIAL CONDITION.
CASE 632·06
PLASTIC PACKAGE
CASE 646
.
HI-
"
....j G ~
MILLIMETERS
DIM MIN
MAX
A
18.16 19.56
6.10
6.60
B
4.06
5.08
C
0.38
0.53
0
F
1.02
1.78
G
.548SC
1.32
2.41
H
0.38
J
0.20
K
.92
3.43
1.628SC
L
100
M
00
0.51
1.02
N
INCHES
MIN
MAX
0.115 0170
0.240 0.260
0.160 0.200
0.015 0.021
0.040 0.010
0.10 8S(
0.052 0.095
0.008 0.015
.115 0.135
0.3008SC
100
0°
0.020 0.040
CASE 646-05
6-3
NOTES:
1. LEADS WITHIN 0.13 mm
(0.005) RADIUS OF TRUE
POSITION AT SEATING
PLANE AT MAXIMUM
MATERIAL CONOITION.
2. OIMENSION "L" TO
CENTER OF LEAOS
WHEN FORMED
PARALLEL.
3. OIMENSION "8" OOES NOT
INCLUOE MOLO FLASH.
4. ROUNDED CORNERS OPTIONAL.
MECHANICAL DATA (Continued)
- - - - - - - - - - 16-PIN PACKAGES
FRIT-SEAL CERAMIC PACKAGE
CASE 620
"0 '\
1
,
B
•
~
, - A
'[
C
J_i1
DIM
A
B
C
0
~L ~FL lSEATlNG
F
G
H
PLANE
J
K
1. LEADS WITHIN 0.13 mm (0.005) RADIUS
OF TRUE POSITION AT SEATING PLANE
AT MAXIMUM MATERIAL CONOITION.
2. PACKAGE INDEX: NOTCH IN LEAD
NOTCH IN CERAMIC OR INK OOT.
3. OIM "L"TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIM "A" AND "B" DO NOT INCLUDE
GLASS RUN·OUT
5. DIM "F" MAY NARROW TO 0.76 mm
(0.030) WHERE THE LEAD ENTERS
THE CERAMIC BODY.
L
M
N
MILLIMETERS
MIN
MAX
19.05 19.94
7.49
6.10
5.08
0.38
0.53
1.78
1.40
2.54 BSC
1.14
0.51
0.30
0.20
5.08
3.18
7.62 BSC
150
0.51
1.02
INCHES
MIN
MAX
0.750 0.785
0.240 0.295
0.200
0.015 0.021
0.055 0.070
0.100 BSC
0.020 0.045
0.008 0.012
0.125 0.200
0.300 BSC
15 0
0.020 0.040
CASE 62CHJ6
PLASTIC PACKAGE
CASE 648
oi;:::::::P
~
-l
_
P
~ F__
lA
'\ CONFIG
OPTIONAL LEAD
(1.8.9.& 16)
I
..j
NOTE 5
DIM
A
8
C
0
f
G
H
J
"
L
M
N
MILLIMETERS
INCHES
MAX
MIN
MAX
MIN
lB.BO 21.34 0.740 0.840
6.10
6.60
0.240 0.260
5.0B
0.160 0.200
4.06
0.3B
0.53
0.015 0.021
1.02
0.040 0.070
1.78
2.54 Bse
O.l00BSC
0.38
2.41
0.015 0.095
0.20
0.38 _",008 0.015
0.115 0.135
3.43
t."
0.300 BSC
7.62 BSC
00
0
100
10
0"
0.51
1.02
0.020 0.040
CASE 648-05
6-4
NOTES:
1. LEADS WITHIN 0.13 mm
(0.005) RADIUS Of TRUE
POSITION AT SEATING
PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION "L" TO
CENTER OF LEADS
WHEN FORMED
PARALLEL.
3. OIMENSION "B" DOES NOT
INCLUDE MOLD FLASH.
4. "F" DIMENSION IS FOR FULL
LEADS. "HALF" LEADS ARE
OPTIONAL AT LEAO POSITIONS
1,8,9,and 161.
5 ROUNDED CORNERS OPTIONAL.
MECHANICAL DATA (Continued)
- - - - - - - - - 1 6 - P I N PACKAGES (Continued) - - - - - - - - CERAMIC PACKAGE
CASE 660
I 9
(
t
8 I
MILLIMETERS
DIM MIN
MAX
A
9.40 10.16
1.24
8
6.22
C
2.03
1.52
0.41
0.48
0
0.15
0.08
1.21 Bse
0.89
H
0.64
9.40
K
6.l5
18.92
t-~
0.51
R
0.38
r+-
NOTES:
1. LEAD NO. 110ENTIFIEO BY TAB
ON LEAD OR DOT ON COVER.
2. LEAOS WITHIN O.ll mm 10.DOS)
TOTAL OF TRUE POSITION AT
MAXIMUM MATERIAL CONDITION.
INCHES
MIN
MAX
0.310 0.400
0.245 0.285
0060 0.080
0.016 0.019
o.ool 0.006
0.050 Bse
0.025 0.035
0.250 0.310
0.145
0.020
- 0.015
CASE 6fiO.03
CERAMIC PACKAGE
CASE fB)
NOTES:
I. A AND ·8· ARE DATUMS.
2. T IS SEATING PLANE
3. POSITIONAL TOLERANCE FOR LEADS (D).
['![i'O:25 (o.ololel Tl A@IBf!)1
DIM
A
8
C
0
F
G
H
J
K
L
M
MILLIMETERS
MIN
MAX
20.07 20.57
1.11
7.62
2.67
4.19
038
0.53
0.76
1.52
2.54 8se
0.76
1.18
020 _L 0.30
3.1B
5.0B
7.628SC
100
.!l ~1l,3B L L~l
INCHES
MIN
MAX
0.190 0.810
0.280 0.300
0.105 0.165
0.015 0021
0.030 0.060
01008SC
0.030 0.010
0.008 0.012
0.125 0.200
0.300 BSC
100
0.015.J 0.D60
CASE 600-13
6-5
4. DIMENSION L TO CENTER OF LEAOS
WHEN FORMED PARAllEL.
5. DIMENSIONING AND TOLERANCING
PER ANSI YI4.5. 1973.
6.690·11 AND 690·12 OBSOLETE.
NEW STANDARD 690·13.
MECHANICAL DATA (Continued)
- - - - - - - - - - 1 8 - P I N PACKAGES ••- - - - - - - - - CERAMIC PACKAGE
CASE 600
NOTES;
1. LEAOS WITHIN 0.13 mm (0.005) RAO OF
TRUE POSITION AT SEATING PLANE AT
MAXIMUM MATERIAL CONOITION.
2. OIMENSION "L" TO CENTER OF LEAOS
WHEN FORMEO PARALLEL.
MILLIMETERS
DIM MIN
MAX
A 22.48 23.24
B
7.16
7.57
C- 3.18
4.27
D
0.38
0.58
F
0.76
1.40
G
2.54 SSC
H
1.02
1.52
J
0.20
0.30
K
2.68
4.44
L
7.37
7.87
M
100
N
0.38
1.40
INCHES
MIN
MAX
0.885 0.915
0.282 0.298
0.125 0.168
0.015 0.023
0.030 0.055
0.100 8SC
0.040 0.060
0.008 0.012
0.105 0.175
0.290 0.310
100
0.015 0.055
CASE flOO.06
PLASTIC PACKAGE
CASE 701-01
NOTES'
1 LEAOSWITHINO.13mm
. (0.005) RADIUM OF TRUE
POSHION AT SEATING
PLANE AT MAXIMUM
MATERIAL CONDITION
101M "G")
2. OIMENSION "L" TO CENTER
OFLEAOSWHENFORMEO
PARALLEL.
MILLIMETERS
DIM MIN
MAX
A 23.11 23.88
8 6.10
6.60
C 4.06
4.57
0
0.38
051
F 1.02
1.52
2.54 SSC
G
H 1.32
1.83
J
0.30
0.20
K 2.92
3.43
7.37
7.87
L
00
M
100
N
0.51
1.02
INCHES
MIN
MAX
0.910 0.940
0.240 0.260
0.160 0.180
0.015 0.020
0.040 0.060
0.100 8SC
0.052 0.072
0.008 0.012
0.115 0.135
0.290 0.310
10·
00
0.020 0.040
CASE 701-01
6-6
MECHANICAL DATA (Continued)
- - - - - - - - - l8-PIN PACKAGES (Continued)
PLASTIC PACKAGE
CASE 707
r~ :::::::~
I.
A
II
•
1
I
JW\NVvV~lf}~
iJF
i
.~
Hf--
I
G I--
iLl
A
1 --I
. ~·-M
---H--D
SEATlNGPlA"
1
J-\\--
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (01.
SHALL BE WITHIN 0.25mmI0.Ol0) AT
MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE ANO
EACH OTHER.
2 DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
3. DIMENSION B OOES NOT INCLUOE
MOLD FLASH.
MILLIMETERS
MAX
DIM MIN
A 22.22 23.24
6.60
6.10
B
3.94
4.57
C
0.36
0.56
0
1.27
1.78
F
2.54 BSC
G
1.52
H
1.02
0.20
0.30
J
K
3.43
2.92
7.62 BS
l
QO
150
M
0.51
1.02
N
INCHES
MIN
MAX
0.875 0.915
0.240 0.260
0.155 0.180
0.014 0.022
0.050 0.070
0.100 BSC
0.040 0.060
0.008 0.012
0.115 0.135
O. 00 BSC
QO
150
0.020 0.040
CASE 707-02
FRIT SEAL CERAMIC PACKAGE
CASE 726
.-i
I
B
~~n=r~~---.=I~
.,
jG~
L~J
F~
I
-f
A~
r~1
J~II
U
I [
H
i
I
r-r--'T
-11--0
\
L-
SE.ATlNG PLANE
DIM
NOTES:
1. LEADS, TRUE POSITIONED
WITHIN 0.25 mm (0.0101 DIA.
AT SEATING PLANE, AT
MAXIMUM MATERIAL
CONDITION.
2. DIM "L" TO CENTER OF
LEADS WHEN FORMED
PARALLEl.
3. DIM "A" & '·S"INCLUDES
MENISCUS.
A
B
C
0
F
G
H
J
K
l
M
N
MILLIMETERS
MIN
MAX
23.11
7.75
4.06
0.51
1.52
2.~4 BSC
1.40
0.30
0.20
4.44
7.37
B.OO
15 0
00
0.51
1.27
22.35
7.11
0.41
1.27
INCHES
MAX
MIN
0.910
0.305
0.160
0.016 0.020
0.050 0.060
0.100BSC
0.8BO
0.2BO
U.O~~
0.008
-
0.290
00
0.020
CASE 726-02
6-7
0.012
0.175
5
150
0.050
u.
MECHANICAL DATA (Continued)
- - - - - - - - - 1 8 - P I N PACKAGES (Continued) - - - - - - - -
[C::J] ,
~-----~A.}-
CERAMIC PACKAGE
CASE 749
~
I
I
H C
~
,
DIM
A
B
C
0
F
-I.
!
I
--, G r-
G
H
J
NOTES:
1. OIMENSIONOO IS DATUM.
2. POSITIONAL TOLERANCE FOR LEADS:
K
L
N
P
\-4>1025(0010) e1T1Mil\
3. ill IS SEATING PLANE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5, 1973.
MILLIMETERS
MIN
MAX
22.61 23.11
7.24
7.75
8.64
0.36
0.61
0.89
1.40
2.548SC
3.30
0.23
0.30
2.92
7.37
7.87
0.64
1.14
9.14
INCHES
MIN
MAX
0.890 0.910
0.285 0.305
0.340
0.014 0,024
0.035 0.055
0.1008SC
0130
0.009 0.012
0.115
0,290 0.310
0.025 0.045
0,360
CASE 749-01
- - - - - - - - - - 2O-PIN P A C K A G E - - - - - - - - - CERAMIC PACKAGE
CASE 729
~'
~I-II-!/-W-
J,~LIii
H,
D
Ili
SEATING"'"
~G
DIM
A
B
C
I
=q
l-j
,
0
F
G
K
H
J
K
L
M
N
NOTE:
1. LEADS WITHIN 0.13 mm (0.005)
RADIUS OF TRUE POSITION AT
SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF
LEADS WHEN FORMED
PARALLEL
MILLIMETERS
MAX
MIN
24.64 25,91
8,13
7.06
2.79
4.70
0.51
0.38
1.14
1.40
2.54 8SC
0.89
1.52
0.20
O.JU
4.57
3.18
7.62 BSC
00
100
0.51
1.52
INCHES
MAX
MIN
0.970 1.020
0.278 0.320
0,110 0.185
0.015 0.020
0.045 0.055
8SC
0.100
0035 0.060
10.008 10.012
0.125 0.180
BSC
0.300
a
IOU
0.020
0.060
CASE 729-02
6-8
MECHANICAL DATA (Continued)
- - - - - - - - - - 22-PIN P A C K A G E S - - - - - - - - - PLASTIC PACKAGE
CASE 708
" " '"-""4
1
I
B
VV'v~
L
A
N C
Ol...M
- H -
-
G -
-- F
_
-- 0
M
J --
NOTES
2156
864
C
394
2iiji
9.14
5.08
'0.56
f+Hf ~~~~~~~
G-r--··
H
J
POSITIONAL TOLERANCE OF LEADS 101.
SHALL BE WITHIN 0.25111111100101 AT
MAXIMUM MATERIAL CONDITION. IN
RELAllON TO SEATING PLANE AND
EACH OTHE R
3.
A
B
~
K
MILLIMETERS
_~IN._. MAX
~-+.~~~~~~~~~~~
M
N
DIMENSION L fa CENTER OF LEADS
WHEN FORMED PARALLEL
DIMENSION B ODES NOT INCLUDE
MOLD FLASH
0.51
CASE 7a3-04
FRIT-SEAL CERAMIC PACKAGE
CASE 736
A
r - MIi-LIMETERS
I
DIM
N C
I
A
I
r-~
K
..... H,-
-G·---F
- ..-
0
SEATING
PLANE
I
__ M
Ii
J -1'-
r+
H
•
NOTES
T. LEADS TRUE POSITIONED
WITHIN 0.25 mm (0.010) OIA AT
SEATING PLANE AT MAXIMUM
MATERIAL CONOITlOfIl (DIM "0")
2 DlM "L" TO CENTER OF LEADS
WHEN FO RMEO PARALLEL.
L
Ilf
•
r---MiN26.80
9.14
MAX
27.£11
9.91
5.46
3.81
038 053
1.21 1.65
2.54 Bse
0.51
1.27
.0)0 O.
2.54 4.32
9.91 10.41
.
15
0.25 0.89
mCHE-SMAX
MI.
I.OSS 1.095
0.360 0.390
0.150 0.215
0.015
CASE 736-01
6-9
0.021
0.050 0.1165
0.100 esc
0.020 0.050
O.
0.012
0.100 0.170
0.390 0.410
15
0.010 0.035
MECHANICAL DATA (Continued)
- - - - - - - - - - - 24-PIN PACKAGES - - - - - - - - - - FRIT-SEAL CERAMIC PACKAGE
CASE 623
[~~~~~~~~]
A
I-
"
-I
,..- SEATING PLANE
~'TI
t
~{~~j
D
NJ I .' '.
I· :,
--i G ~--
-11-
KJ
-,
1--
L
M
---~\ .
J_.-I-
DIM
A
B
C
0
F
G
J
NOTES:
1. OIM "L" TO CENTER OF
LEAOS WHEN FORMEO
PARALLEL
2. LEAOSWITHINO.13mm
(O.OOS) RADIUS OF TRUE
POSITION AT SEATING
PLANE AT MAXIMUM
MATERIAL CONDITION.
(WHEN FORMED PARALLEL)
K
L
M
N
MILLIMETERS
MIN
MAX
INCH[S
MIN
MAX
31.24 32.77
12.70 IS.49
4.06
S.S9
0.41
O.SI
1.27
I.S2
2.S4 BSC
0.20
0.30
4.06
2.29
IS.24 BSC
ISO
00
1.27
O.SI
1.230 1.290
O.SOO 0.610
0.160 0.220
0.016 a.020
O.OSO 0.060
0.100BSC
0.008 0.012
0.090 0.160
0600 BSC
ISO
00
0.020 O.OSO
CASE 623--04
FRIT-SEAL CERAM)C PACKAGE
CASE 623A
MILLIMETERS
MIN
MAX
31.24 32.77
12.70 IS.49
4.06
S.84
0.41
O.SI
1.27
I.S2
2.S4
BSC
G
J
0.20
0.30
2.29
4.06
K
IS.24 Bse
l
0
M
150
0
N
O.SI
1.27
DIM
A
B
C
D
F
NOTES:
1 DIM "L" TO CENTER OF
LEADS WHEN FORMEO
PARALLEL
2. LEADS WITHIN 0.13 mm
1O.00S) RADIUS OF TRUE
POSITION AT SEATING PLANE
AT MAXIMUM MATERIAL
CONDITION. (WHEN FORMED
PARALLEL).
INCHES
MIN
MAXJ
1.230
0.610
O.SoO
0.160 0.230
0.016 0.020
O.OSO 0.060
0.100 BSC
O.OOB 0.012
0.090 0.160
0.600 BSC
00 J. ISO
0.020 O.OSO
CASE 623A-02
6-10
~
MECHANICAL DATA (Continued)
- - - - - - - - - 2 4 - - P I N PACKAGES (Continued)--------..
PLASTIC PACKAGE
CASE 700
B
~,:,
,
L
,~
L ' .._.liI
,
i
','
·-JH~
-1GI--
:
._!
F
-
DIM
A
iK
Ii
_L.
0 'SfJl,II~G
B
C
0
NOTES:
I POSITIONAL TOLERANCE OF LEADS (0),
SHALL BE WITHIN 0.25 mm (0.010) AT
MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND
EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
3. DIMENSION 8 ODES NOT INCLUDE MOLD
FLASH.
F
G
H
J
K
L
M
N
MILLIMETERS
MIN
MAX
31.37 32.13
13.72 14.22
3.94
5.08
0.56
0.36
1.52
1.02
2.54 8SC
1.65
2.03
0.20
0.38
2.92
3.43
15.24 8SC
15°
0"
0.51
1.02
INCHES
MIN
MAX
1.235 1.265
0.540 0.560
0.155 0.200
0.014 0.022
0.040 0.060
0.100 8SC
0.065 0.080
0.008 0.015
0.115 0.135
0.600 SSC
15°
0°
0.020 0.040
CASE 709-02
CERAMIC PACKAGE
CASE 716
NOTE:
I. LEADS TRUE POSITIONED WITHIN
0.25f"m (0.010) DIA (AT SEATING
PLANEI AT MAXIMUM MATERIAL
CONDITION.
2. DIM T'TO CENTER OF LEADS
WHEN FORMED PARALLEL
, 1- L-i
:NjFl,
-1>-
J
M
.e
MILLIMETERS
MIN
MAX
27.64 30.99
14.94 15.34
4.32
2.67
0.38
0.53
0.76
1.40
2.54 8SC
178
I---'J:!--- ~0.20
0.30
4.19
~
15.49
~.
M
10°
~ .!I!?- 1.52
DIM
A
8
C
D
F
G
r-{i~9
y
INCHES
MIN
MAX
1.088 1.220
0.588 0.604
0.105
~
0.015 0.021
0.030 0.055
a 100 8S
0.030 JL070
0.008 ..,M,1
0.100 0.165
0.590 0.610
10°
0.040 0.060
CASE 716-06
6-11
MECHANICAL DATA (Continued)
- - - - - - - - - 24-PIN PACKAGES (Continued)------_ __
CERAMIC PACKAGE
CASE 716
"I
"j
~------~---==-~
I----A----..!
H -
Wttffiffm
-
SI~"frlc;.~l ... JtI ,J
--- 0
G-
-
- - J
M
NOTE:
1. LEADS TRUE POSITIONED WITHIN
0.25mm (0.010) DIA (AT SEATING
PLANE) AT MAXIMUM MATERIAL
CONDITION.
2. DIM "L" TO CENTER OF LEADS
WHEN FORMEO PARALLEl.
DIM
A
8
C
0
F
G
H
J
K
L
M
N
MILLIMETERS
INCHES
MIN
MAX
MIN
MAX
27.64 30.99 1088 1.220
14.73 15.34 0.580 0.604
3.18
5.08
0.125 0.200
0.38
0.53
0.015 0.021
0.76
140 0.030 0.055
2.54 SSC
0.1 08SC
0.16
178
0.030 . O.OlD..
0.20
0.30
0.008 O. 12
2.54
4.57
0.100 0.180
14.99 15.49 0.590 0.610
10 0
100 ,
102
152
0.040 0.060
CASE 716-07
6-12
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