1981_HLN062_8_16_bit_Multi Chip_Microcomputer 1981 HLN062 8 16 Bit Multi Chip Microcomputer
User Manual: 1981_HLN062_8_16_bit_Multi-Chip_Microcomputer
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8/16 BIT
MULTI-CHIP
MICROCOMPUTER
DATA BOOK
.HITACHI
TABLE OF CONTENTS
Quality and Reliability Commitment .............................................................. 3
Hitachi Microprocessor/Peripheral Cross Reference ............................................... 4
New Hitachi Microprocessor Numbering System .................................................. 5
HD6800, HD68AOO, HD68800
MPU (Micro Processing Unit) ................................................•............... 6
HD6802
MPU (Microprocessor with Clock and RAM) ................................................. 37
HD6809, HD68A09, HD68809
MPU (Micro Processing Unit) ............................................................... 48
HD6821 , HD68A21, HD68821
PIA (Peripheral Interface Adapter) ........................................................... 77
HD6840, HD68A40, HD68840
PTM (Programmable Timer Module) ......................................................... 97
HD6843S, HD68A43S
FDC (Floppy Disk Controller) .............................................................. 110
H 06844, H D68A44
DMAC (Direct Memory Access Controller) .................................................. 143
H D6845S, H D68A45S, H D68845S
CRTC (CRT Controller) .................................................................... 160
HD6846
COM80 (Combination ROM 110 Timer) .................................................... 190
HD6850, HD68A50
ACIA (Asynchronous Communication Interface Adapter) .................................... 211
HD6852, HD68A52
SSDA (Synchronous Serial Data Adapter) ................................................... 211
HD46508, HD46508-1
ADU (Analog Data Acquisition Unit)-Preliminary ........................................... 234
HD68000
MPU (Micro Processing Unit)-Preliminary . ................................................. 253
APPENDiX ...................................................................................... .
Package Information ........................................................................... 296
HMCS6800 Family Instructions ............................. " ................. , ................ 298
Memories ..................................................................................... 303
Linear IC & Interface Circuits .................................................................. 306
TTL HD74/HD74S/HD74LS Series ............... '" ........................... , ................ 308
Quality and Reliability
An Unprecedented Commitment to
Quality and Reliability . . .
As quality and reliability become increasingly important
concerns, Hitachi continues to improve its efforts to
provide the best possible product. The experience gained
in shipping millions of microprocessors and peripheral
LSls for critical and demanding automotive and industrial
applications is reflected in every product we sell. Each
unit shipped receives 100% dynamic high-temperature
burn-in, a quality assurance effort unparalleled in the
semiconductor industry, and another reason why Hitachi
is the Symbol of Semiconductor Quality, Worldwide.
QUALITY ASSURANCE FLOW FOR ASSEMBLY AND TEST
(all microprocessor and microcomputer products):
REMARKS
QC CRITERIA
INSPECTION LEVEL
PROCESS
1
Dicing
-
-
-
2
Chip Visual
100%
Visual
100x
3
Lot Acceptance
AOL=0.25%*
Visual
100x
4
Die Attachment
-
-
Au-Si
5
Patrol Inspection
OncelDay/Machine
Visual
-
6
Wire Bonding
-
-
AI Ultrasonic
7
Patrol Inspection
OncelDay/Machine
Visual
Once/Week/Machine
Bond Dimension
Bond Strength
8
Visual Inspection
100%
Visual
9
Lot Acceptance
AOL=0.25%*
Visual
20x
10
Seal
-
-
A-Sn Alloy
'11
Temperature Cycle
100%
-
-55°C -25°C ·150°C
10 Cycles
12
Hermeticity
100%
Fine and Gross
Hermetic Packages
Only
20x
13
Plating
Tin (Sn)
Lead Trim
-
-
14
-
-
15
Visual Inspection
100%
Visual
16
Lot Acceptance
AOL=0.25%
Visual
17
Burn-in
100%
-
Dynamic Ta = 125°C
18
Electrical Test
100%
DC, AC, Functional
Ta =70°C
19
Marking
-
-
20
Electrical
100%
DC
21
Visual Inspection
100%
External Visual
22
Lot Acceptance
AOL=0.25%*
Electrical
AOL=0.65%
External Visual
*Combined DC, AC and functional.
3
HITACHI MICROPROCESSOR/PERIPHERAL CROSS REFERENCE
Hitachi is in the process of converting many microprocessor part numbers to "industry standard"
generic part numbers. A complete list showing both
the "old" and "new" part numbers is shown in
figure 1. The use of industry standard part numbers
will greatly simplify the interface between Hitachi
and our customers.
Beginning JULY 1, 1981, all orders should be
entered using the "new" part numbers only.
Note that during the conversion process, product
shipped by Hitachi will be marked 1 of 2 ways (see
figure 2).
Description
16/32 bit microprocessing unit, 8 mhz .............
16/32 bit microprocessing unit, 6 mhz .............
16/32 bit microprocessing unit, 4 mhz .............
8/16 bit microprocessing unit, 1mhz ...............
8/16 bit microprocessing unit, 1.5mhz .............
8/16 bit microprocessing unit, 2mhz ...............
8 bit microprocessing unit, 1mhz ..................
8 bit microprocessing unit, 1.5mhz ................
8 bit microprocessing unit, 2mhz ..................
8 bit microprocessing unit, 1mhz ..................
with clock and 128 bytes RAM
8 bit microprocessing unit, 1mhz ..................
with clock and 256 bytes RAM
128 x 8 static RAM, 450ns access time .............
128 x 8 static RAM, 360ns access time .............
Peripheral interface adapter, 1mhz ................
Peripheral interface adapter, 1.5mhz ...............
Peripheral interface adapter, 2mhz ................
Programmable timer module, 1mhz ................
Programmable timer module, 1.5mhz ..............
Programmable timer module, 2mhz ................
Floppy disk controller, 1mhz ......................
Floppy disk controller, 1.5mhz ....................
8 bit DMA controller, 1mhz ........................
8 bit DMA controller, 1.5mhz ......................
8 bit DMA controller, 2mhz ........................
CRT controller, 1mhz .............................
CRT controller, 1.5mhz ...........................
CRT controller, 2mhz .............................
CRT controller (enhanced), 1 mhz .................
CRT controller (enhanced), 1.5mhz ................
CRT controller (enhanced), 2mhz .................
ROM, I/O, Timer combo, 1mhz ....................
Asynchronous comm interface, 1mhz ........... : ..
Asynchronous comm interface, 1.5mhz ............
Synchronous comm interface, 1mhz ...............
Synchronous comm interface, 1.5mhz .............
Analog data acquisition unit, 1mhz ................
Analog data acquisition unit, 1.5mhz ..............
Analog data acquisition unit, 1mhz (enhanced) .....
Analog data acquisition unit, 1.5mhz (enhanced) ...
1) marked with the "old" Hitachi part number ...
or
2) marked with a dual number ("old" and "new")
At the completion of the conversion (approximately
JANUARY 1, 1982) all product will be shipped with
the dual marking (2 above).
If this conversion plan poses problems, or you have
any questions, please contact Hitachi Microprocessor Marketing.
"old"
HITACHI
number
---------------
"new"
HITACHI
number
MOTOROLA
number
HD6809P
HD68A09P
HD68B09P
HD46800DP
HD468AOOP
HD468BOOP
HD46802SP
HD68000-8
HD68000-6
HD68000-4
HD6809P
HD68A09P
HD68B09P
HD6800P
HD68AOOP
HD68BOOP
HD6802SP
MC68000L
MC68000L6
MC68000L4
MC6809P
MC68A09P
MC68B09P
MC6800P
MC68AOOP
MC68BOOP
MC6802P
------
HD6802WP
------
HM46810P
HM468A10P
HD46821P
HD468A21P
HD468B21P
HD6810P
HD68A10P
HD6821P
HD68A21P
HD68B21P
HD6840P
HD68A40P
HD68B40P
HD6843SP
HD68A43SP
HD6844P
HD68A44P
HD68B44P
HD6845RP
HD68A45RP
HD68B45RP
HD6845SP
H068A45SP
HD68B45SP
HD6846P
HD6850P
HD68A50P
HD6852P
HD68A52P
HD46508P
HD46508P-1
HD46508PA
HD46508PA-1
MC6810P
MC68A10P
MC6821P
MC68A21P
MC68B21P
MC6840P
MC68A40P
MC68B40P
MC6843P
MC68A43P
MC6844P
MC68A44P
MC68B44P
MC6845P
MC68A45P
MC68B45P
----------------
HD46503SP
HD46503SP-1
HD46504RP
HD46504RP-1
HD46504RP-2
HD46505RP
HD46505RP-1
HD46505RP-2
HD46505SP
HD46505SP-1
HD46505SP-2
------
HD46850P
HD468A50P
HD46852P
HD468A52P
HD46508P
HD46508P-1
HD46508PA
HD46508PA-1
Figure 1. Hitachi Microprocessor/Peripheral Cross Reference
4
------
----------MC6846P
MC6850P
MC68A50P
MC6852P
MC68A52P
---------------------
NEW HITACHI MICROPROCESSOR NUMBERING SYSTEM
(a)
Present marking
~ []JDB
BD~BBDBSB
(]~B~ISI
(b)
New marking
~ []JDB
BD~BBDBSB
(]~B~ISI
BDB8~BSB
Figure 2.
5
HDSBOO, HDSBAOO, HDSBBOO---MPU (Micro Processing Unit)
The HD6800 is a monolithic 8-bit microprocessor forming
the central control function for Hitachi's HMCS6800 family.
Compatible with TTL, the HD6800 as with all HMCS6800
system parts, requires only one 5V power supply, and no external TTL devices for bus interface. The HD68AOO and
HD68BOO are high speed versions.
The HD6800 is capable of addressing 65K bytes of memory with its 16-bit address lines. The 8-bit data bus is bi-directional as well as 3-state, making direct memory addressing and
multiprocessing applications realizable.
• FEATURES
• Versatile 72 Instruction - Variable Length (1-3 Byte)
• Seven Addressing Modes - Direct, Relative, Immediate,
Indexed, Extended, Implied and Accumulator
• Variable Length Stack
• Vectored Restart
• Maskable Interrupt
• Separate Non-Maskable Interrupt - Internal Registers Saved
in Stack
• Six Internal Registers - Two Accumulators, Index Register,
Program Counter, Stack Pointer and Condition Code Register
• Direct Memory Accessing (DMA) and Multiple Processor
Capability
• Clock Rates as High as 2.0 MHz (HD6800
1 MHz,
HD68AOO ... 1.5 MHz, HD68BOO ... 2.0 MHz)
• Halt and Single Instruction Execution Capability
• Compatible with MC6800, MC68AOO and MC68BOO
HD6800P, HD68AOOP, HD68BOOP
(DP-40)
• PIN ARRANGEMENT
• BLOCK DIAGRAM
RES
TSC
NC
1>2
DBE
NC
R/W
D.
D,
D,
D,
D,
DBE 36
SA
7
D,
VMA
5
Au
Am 34
A"
A"
(Top View)
26
0.1
27
O.
28
01
29
04
30
OJ
31
O2
32
0l
33
Do
6
HD6800, HD68AOO, HD68BOO - - - - - - - - - - - - - •
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Supply Voltage
Item
Vee *
-0.3 - +7.0
V
Input Voltage
V in *
-0.3 - +7.0
V
Operating Temperature
Topr
T stg
- 20 - + 75
°c
- 55 - +150
°c
Storage Temperature
Unit
* With respect to Vss (SYSTEM GNO)
(NOTE) Permanent LSI damage may occur if maximum rating are exceeded. Normal operation should be under recommended operating conditions.
If these conditions are exceeded, it could affect reliability of LSI.
•
RECOMMENDED OPERATING CONDITION
Item
Supply Voltage
Input Voltage
Symbol
min
Vee *
V ,L *
4.75
-
2.0
-20
Topr
max
5
-0.3
V ,H *
Operating Temperature
typ
25
Unit
5.25
V
0.8
V
Vee
75
°c
V
* With respect to Vss (SYSTEM GNO)
•
•
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (Vee = 5V ± 5%, Vss = OV, Ta = -20-+75°C, unless otherwise noted.)
Item
min
typ*
Input "High" Voltage
Logic**
V ,H
Vss + 2.0
-
Vee
Input "Low" Voltage
Logic**
V ,L
Vss - 0.3
Vss + 0.8
V
Clock Input "High" Voltage
¢1, ¢2
V ,He
V ce - 0.6
Vee + 0.3
V
Clock Input "Low" Voltage
¢1, ¢2
V,Le
IOH
= -205pA
Vss + 2.4
-
IOH
= -145pA
Vss + 2.4
IOH
= -100pA
Vss + 2.4
VOL
IOL
= 1.6mA
lin
V in = 0-5.25V,
All other pins are connected
to GND
0 0 -0 7
Output "High" Voltage
A o-A 15 , R/W
VMA
V OH
BA
Qutput"Low" Voltage
Logic***
Input Leakage Current
Three-State (Off-state)
Input Current
Test Condition
Symbol
¢1,¢2
0 0 -0 7
A o-A 15 , R/W
Power Dissipation
I TS1
Vss - 0.3
V in = 0.4 - 2.4V
Po
Logic***
Input Capacitance
0 0 -0 7
¢1
Cin
Vin = OV, Ta
f = 1 MHz
= 25°C,
¢2
Output Capacitance
A o-A 15 , R/W
VMA BA
Cout
V in = OV, Ta
f = 1 MHz
* Ta = 25°C, Vee = 5V
** All inputs except 4>1 and 1/>2
*** All inputs except 4>1 ,1/>2 and 0 0-0 7
7
max
Unit
V
Vss + 0.4
V
-
V
-
-
V
-
-
V
-
-
-
1.0
2.5
-
-
100
pA
-
2.0
10
pA
pA
W
Vss + 0.4
-
-
100
-
0.5
1.0
-
-
V
pA
6.5
10
pF
10
12.5
pF
25
35
pF
45
70
pF
12
pF
v
= 25 C,
HD6800, HD68AOO, HD68BOO - - - - - - - - - - - - - •. AC CHARACTERISTICS
1. TIMING CHARACTERISTICS OF CLOCK PULSE CPI and
Symbol
Item
cpz
HD6800
typ
max
Test
Condition
min
Fig.10
1.000
Fig. 10
400
Rise and Fall Times CPI, cpz
Delay Time (Clock Internal)
t r , tf
Fig. 10
tct
Fig. 10
-
-
Clock "High" Level Time
tUT
Fig. 10
900
-
Frequency of Operation
f
Cycle Time
tcyC
Clock Pulse Width
I CPI, cpz
PWCH1. PWCH 2
I
0.1
min
HD68AOO
typ
max
min
HD68800
typ
max
--
2.0
-
10
0.1
-
10 0.666
-
230
-
100
-
-
100
-
4,500
-
-
4,500
-
-
440
-
1.0
4,500
-
600
1.5
0.1
10 0.500
4,500
180
Unit
MHz
4,500
/J.s
ns
-
100
ns
-
4,500
--
-
ns
ns
2 READ/WRITE CHARACTERISTICS
Item
Address Delay
Time
Symbol
Test
Condition
HD6800
typ
min
max
min
HD68AOO
typ
max
min
HD68BOO
typ
max
Unit
C=90pF
tA01
Fig.11,
Fig. 12
-
-
270
-
-
180
-
-
150
ns
C=30pF
tAo2
Fig. 11,
Fig. 12
-
-
250
-
-
165
-
-
135
ns
tOSR
Fig. 11
100
-
-
60
-
-
40
-
-
ns
tacc
Fig. 11
-
-
530
-
-
360
-
-
250
ns
10
Data Setup Time (Read)
Peripheral Read Access Time
tacc = tUT - (tAD + tOSR )
Input Data Hold Time
tH
Fig. 11
10
-
-
Fig. 12
20
-
20
-
10
tH
-
-
Output Data Hold Time
-
20
-
-
ns
Address Hold Time
(Address, R/W, VMA)
tAH
Fig. 11,
Fig. 12
10
-
-
10
-
-
10
-
-
ns
Enable "High" Time for DBE
Input
tEH
Fig. 12
450
-
-
280
-
-
220
-
-
ns
Data Delay Time (Write)
toow
Fig. 12
-
-
225
-
-
200
-
-
160
ns
Data Bus Enable Down Time
(During CPI Up Time)
tOBE
Fig. 12
150
-
-
120
-
-
75
-
-
ns
Data Bus Enable Delay Time
tOBEO
Fig. 12
300
-
-
250
-
-
180
-
-
ns
Data Bus Enable
Rise and Fall Times
tOBEr
tOBEf
Fig. 12
-
-
25
-
-
25
-
-
25
ns
ns
Processor Control Setup Time
tpcs
200
-
-
140
-
-
110
-
-
ns
Processor Control
Rise and Fall Times
tpcr
tpCf
-
-
100
-
-
100
-
-
100
ns
Bus Available Delay Time (BA)
tBA
-
165
270
-
ns
-
-
135
-
-
-
tTso
-
250
Three-State Delay Time
220
ns
270
5.0V
Test Point
C = 130pF for 0 0 -0 7
= 90pF for Ao -AI s. R/W. and VMA
= 30pF for BA
R= 11kn for 0 0 -0 7
= 16kn for Ao-A ls ' R/W and VMA
= 24kn for BA
C includes Stray Capacitance.
All diodes are 152074<9.
o-.......--+--W-....
c
Figure 1 Bus Timing Test Load
D
-
HD6800, HD68AOO, HD68BOO - - - - - - - - - - - - - The Last Instruction Cycle
'"
BA
Figure 2 Timing of HALT and BA
Halt Cycle
I nstruction Cycle
·1-
ct>1
BA
O.4V
Figure 3 Timing of HALT and BA
MPU Reset
-I-
MPU Restart Sequence
\'---__1VCC -06V\'---_---'r
Vee - O.6V
RES
VMA
2.4V
Figure 4 RES and MPU Restart Sequence
HD6800, HD68AOO, HD68BOO - - - - - - - - - - - - - WAIT Cycle or
The Last Instruction Cycle
Interrupt Sequence
\"---_--.-11
\'-_---Jr
VCC-O.6V
(When WAIT Cycle)
BA
Figure 5 IRQ and NMI Interrupt Timing
..
.
I
The last execution cycle of
WAI instruction (#9)
...I
WAIT Cycle
\'-__§;:C~.6VL
_tpcr
BA
Figure 6 WAI Instruction and BA Timing
PWCHt (4.5Ils max)
Figure 7 TSC Input and MPU Output
HD6800, HD68AOO, HD68BOO - - - - - - - - - - - - •
MPU REGISTERS
The MPU provides several registers in Fig. 8, which is available for use by the programmer.
Each register is described below.
•
StackPomter{LJ
Stack Pointer (HI
Incrementer
(H)
Program Counter (Hl
Incrementer(U
Program Counter (Ll
Index Register (H)
Index Register (IX)
The index register is a two byte register that is used to store
data or a sixteen bit memory address for the Indexed mode of
memory addressing.
•
(Ll Ao -A~
Temporary Register
Stack Pointer (SP)
The stack pointer is a two byte register that contains the
address of the next available location in an external push-down/
pop-up stack. This stack is normally a random access Read/
Write memory that may have any location (address) that is convenient. In those applications that require storage of information in the stack when power is lost, the stack must be nonvolatile.
•
Address Bus
Program Counter (PC)
The program counter is a two byte (16-bit) register that
points to the current program address.
•
Address Bus
(H) A~ -A '5
Index Register (L1
Accumulators (ACCA, ACCB)
The MPU contains two 8-bit accumulators that are used to
hold operands and results from an arithmetic logic unit (ALV).
Data Bus
0,,-0,
0
7
I
ACCA
I
ACCB
I
I
I
I
I
I
•
Accumulator B
Index Register
•
0
15
PC
MPU SIGNAL DESCRIPTION
Proper operations of the MPU requires that certain control
and timing signals (Fig. 9) be provided to accomplish specific
functions. The functions of pins are explained in this section.
0
IX
Clock (2 2)
I
Two pins are used to provide the clock signals. A two-phase
non-{)veriapping clock is provided as shown in Fig. 10.
Program Counter
0
15
I
Figure 9 Internal Block Diagram of MPU
0
7
15
I Accumulator A
SP
.......------tcyc------~
Stack Pointer
ri>l
-
Carry (From Bit 7)
Overflow
VIHC
vav
ri>2
Zero
VI LC
V IHC
VILC
Vav
Negative
Interrupt Mask
' - - - - - - Half Carry
(From Bit 3)
-------.J(
= vcc - O.6V
= Vss+O.4V
= Vss + O.6V
(min.)
(max.)
Figure 10 Clock Timing Waveform
Figure 8 Programming Model of the Microprocessing
Unit
•
•
Address Bus (Ao "'A 1 5 )
Sixteen pins are used for the address bus. The outputs are
three-state bus drivers capable of driving one standard TTL load
and 90pF. When the output is turned off, it is essentially anopen circuit. This permits the MPU to be used in DMA applications. Putting TSC in its high state forces the Address bus to go
into the three-state mode .
Condition Code Register (CCR)
The condition code register indicates the results of an Arithmetic Logic Unit operation: Negative (N), Zero (Z), Overflow
(V), Carry from bit 7 (C), and half carry from bit 3(H). These
bits of the Condition Code Register are used as testable conditions for the conditional branch instructions. Bit 4 is the
interrupt mask bit (I). The unused bits of the Condition Code
Register (b6 and b7) are "1". The detail block diagram of the
microprossing unit is shown in Fig. 9.
•
Data Bus (0 0 "'0 7 )
Eight pins are used for the data bus. It is bidirectional,
transferring data to and from the memory and peripheral
devices. It also has three-state output buffers capable of driving
one standard TTL load and 130pF. Data Bus is placed in the
three-state mode when DBE is "Low."
11
HD6800, HD68AOO, HD68BOO ------------~
~-----------------------tcyc------------------------~
CPI
Address~~~~~~~~~~------------------------------------t1~~~
From
MPU
---"'--------------tacc--------+Data From
Memory or
Peripherals
2.0V --::~I--~======~~
-------------------------------O~.8~V~~~~~~~~
~~ Indeterminate period
Figure 11 Read from Memory or Peripherals
Start of Cycle
1/>1
Address
FromMPU~~~~~~~-~~r_--__----4_--------------------------11r__
2.4V
Data
From MPU
---t:=~~-;;;.;j-------+--------------------"tt""""'~
-----I-I-------------I~~~-:-:=~~-'--,_~-----D-a-ta-V-a-li-d---~_-~~
~tD~::r
~"03 Indeterminate period
Figure 12 Write to Memory of Peripherals
12
HD6800, HD68AOO, HD68BOO - - - - - - - - - - - - • Data Bus Enable (DBE)
This input is the three-state control signal for the MPU data
bus and will enable the bus drivers when in the "High" state;will
make the bus driver off when in the "Low" state. This input is
TTL compatible; however in normal operation, it would be
driven by 2 cycles. The RES pulse can be completely
asynchronous with the MPU system clock and will be recognized during ct>2 if setu~e tPCS is met .
•
•
Interrupt Request (IRQ)
This level sensitive input requests that an interrupt sequence
be generated within the machine. The processor will wait until
it completes the current instruction that is being executed
before it recognizes the request. If the interrupt mask bit in the
Condition Code Register is not set, the machine will begin an
interrupt sequence. The Index Register, Program Counter,
Accumulators, and Condition Code Register are stored away on
the stack.
Next the MPU will respond to the interrupt request by
setting the interrupt mask bit "1" so that no further interrupts may occur. At the end of the cycle, a 16-bit address will
be loaded that points to a vectoring address which is located in
memory locations FFF8 and FFF9. An address loaded at these
locations causes the MPU to branch to an interrupt routine in
memory. Interrupt timing is shown in Fig. 14.
The HALT line must be in the "High" state for interrupts
to be serviced. Interrupts will be latched internally while HALT
is "Low". The IRQ has a high impedance pullup device internal
to the chip; however a 3kn external resistor to Vee should be
used for wire-OR and optimum control of interrupts.
I
Cycle
#1
I #2 I
Cycle
Cycle
#3
I #4 I
Cycle
Cycle
#5
I
Cycle
#6
I
Non-Maskable Interrupt (NMI) and Wait for Interrupt (WAI)
The MPU is capable of handling two types of interrupts:
maskable (IRQ) as described earlier, and non-maskable (NMI).
IRQ is maskable by the interrupt mask in the Condition Code
Register while NMI is not maskable. The handling of these interrupts by the MPU is the same except that each has its own
vector address. The behavior of the MPU when interrupted is
shown in Fig. 14 which details the MPU response to an interrupt
while the MPU is executing the control program. The interrupt
shown could be either lRQ or NMI and can be asynchronous
with respect to ct>2. The interrupt is shown going "Low" at
time tpcs in cycle #1 which precedes the first cycle of an instruction (OP code fetch). This instruction is not executed but
instead the Program Counter (PC), Index Register (IX),
Accumulators (ACCX), and the Condition Code Register (CCR)
are pushed onto the stack.
The Interrupt Mask bit is set to prevent further interrupts.
The address of the interrupt service routine is then fetched from
FFFC, FFFD for an NMI interrupt and from FFF8, FFF9 for
an IRa interrupt. Upon completion of the interrupt service
routine, the execution of RTI will pull the PC, IX, ACCX, and
CCR off of the stack; the Interrupt Mask bit is restored to its
condition prior to interrupts. Fig. 15 is a similar interrupt sequence, except in this case, a WAIT instruction has been executed in preparation for the interrupt. This technique speeds
up the MPU's response to the interrupt because the stacking of
Cycle
#7
I
Cycle
#8
I #9 I #10 I #11 I #12 I #13 I #14 I #15 I
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Address
Bus
IRQ or
NMI
1M
Data
Bus
Inst (x)
R/W
PCO-PC7 PC8-
\~
IXO-IX7 IX8-
ACCA
ACCB
New PCB-PCIS New PCO-PC7 First Inst of
Address
Address Interrupt Routine
CCR
PC15
IX15
____________________________________
JI
.VMA
Figure 14 Interrupt Timing
I
I
I
I
Cycle Cycle CYCle) Cycle CYcle) Cycle ICycle Cyclel Cycle
#2
#3
#4
#5
#6
#7
#8
#9
I #1
Address
Bus
R/W
I Wait Cycl e ICYCle)
Cycle ICYcie I Cycle ICycle ICyclel
# n #n+1 #n+2 #n+3 #n+4 #n+5
Cycle
2
4
7
3
5
9
6
8
#1
Jl
X
X
X
X
X
X
X
X
Instruction
SPlnl SPin-II SPln-21 SPln-31 SPln-41 SPin-51 SPln-SI
n+3
n In+1 n+2
7..
X
_ _ FFF8-FFF9- New PC
Address
VMA
I
1M
fRO or
"
NMI
Data
Bus
Cycle
n+4 #n+5
(NOTE)
I
X
X
Wait
Inst
X
X
A.
X
X
A.
- I I--tpcs (2oons)
X
PCO-PC7 P~~~5IXO-IX7 1~~;5 ACCA ACCB CCR
1>3~~g~~
f
(NOTE) Midrange waveform indicates high impedance state.
Figure 15 WAI Instruction Timing
14
,
First Inst.
ot Interrupt
Routine
.r
lI.
X
New PCB-PCI 5 New pca-pc
Address
Address
HD6800, HD68AOO, HD68BOO - - - - - - - - - - - - -
the PC, IX, ACCX, and the CCR is already done.
While the MPU is waiting for the interrupt, Bus Available will
go "High" indicating the following states of the control lines:
VMA is "Low", and the Address Bus, R/W and Data Bus are all
in the high impedance state. After the interrupt occurs, it is
serviced as previously described.
•
Table 1 Memory Map for Interrupt Vectors
Vector
•
Description
MS
FFFE
LS
FFFF
FFFC
FFFD
FFFA
FFFB
Software Interrupt
FFF8
FFF9
Interrupt Request
Restart
Non·maskable Interrupt
Three State Control (TSC)
When the Three State Control (TSC) line is "High" level, the
Address Bus and the R/W line are placed in a high impedance
State. VMA and BA are forced "Low" when TSC = "High" to
prevent false reads or writes on any device enabled by VMA.
It is necessary to delay program execution while TSC is held
"High". This is done by insuring that no transitions of ¢l (or
¢2) occur during this period. (Logic levels of the clocks are
irrelevant so long as they do not change.)
Since the MPU is a dynamic device, the ¢I clock can be
stopped for a maximum time PWCH1 without destroying data
within the MPU. TSC then can be used in a short Direct Memory Access (DMA) application.
Fig. 16 shows the effect of TSC on the MPU. The Address
Bus and R/W line will reach the high impedance state at tTS D
(three-state delay), with VMA being forced "Low". In this
example, the Data Bus is also in the high impedance state while
¢2 is being held "Low" since DBE=¢2' At this point in time, a
DMA transfer could occur on cycles #3 and #4. When TSC is
returned "Low," the MPU address and R/W lines return to the
bus. Because it is too late in cycle #5 to access memory, this
cycle is dead and used for synchronization. Program execution
resumes in cycle #6.
Cycle
#1
#2
I
#3
#4
Halt (HALT)
When this input is in the "Low" state, all activity in the
machine will be halted. This input is level sensitive.
The HALT line provides an input to the MPU to allow control or program execution by an outside source. If HALT is
"High", the MPU will execute the instructions; if it is "Low",
the MPU will go to a halted or idle mode. A response signal,
Bus Available (BA) provides an indication of the current MPU
status. When BA is "Low", the MPU is in the process of executing the control program; if BA is "High", the MPU has halted
and all internal activity has stopped.
When BA is "High", the Address Bus, Data Bus, and R/W line
will be in a high impedance state, effectively removing the
MPU from the system bus. VMA is forced "Low" so that the
floating system bus will not activate any device on the bus that
is enabled by VMA.
While the MPU is halted, all program activity is stopped, and
if either an NMI or IRQ interrupt occurs, it will be latched into
the MPU and acted on as soon as the MPU is taken out of the
halted mode. If a RES command occurs while the MPU is
halted, the following states occur: VMA = "Low", BA = "Low",
Data Bus = high impedance, R/W = "High" (read state), and
the Address Bus will contain address FFFE as long as RES is
"Low". As soon as the HALT line goes "High", the MPU will
go to locations FFFE and FFFF for the address of the reset
routine.
Fig. 18 shows the timing relationships involved when halting
the MPU. The instruction illustrated is a one byte, 2 cycle instruction such as CLRA. When HALT goes "Low", the MPU
will halt after completing execution of the current instruction.
The transition of HALT must occur tpcs before the trailing edge
of ¢l of the last cycle of an instruction (point A of Fig. 18).
HALT must not go "Low" any time later than the minimum
tpcs specified.
Refer to Figure 18 for program flow for Interrupts.
•
Valid Memory Address (VMA)
This output indicates to peripheral devices that there is a
valid address on the address bus. In normal operation, this signal
should be utilized for enabling peripheral interfaces such as the
PIA and ACIA. This signal is not three-state. One standard TTL
load and 90pF may be directly driven by this active "High"
signal.
#5
I
#6
System
CPl
MPUCPl
Address
Bus
R/W
VMA
CPz
Data
Bus
DBE
TSC
Figure 16 TSC Control Timing
15
HD6800, HD68AOO, HD68BOO - - - - - - - - - - - - -
>---y-.
IRQ
Ignored
#1
~
2
#3- 9
y
(FFFC) Fetch
IM=1
Reset ( ~RMd~
#11
#10
#11
(FFF8) Fetch
IM=1
Reset
(~R~~
#12
JUMP
FFFC/O
#13
Figure 17 MPU Interrupt Flow Chart
16
#13
HD6800, HD68AOO, HD68BOO - - - - - - - - - - - - -
II
jl nstruction nstruction
Fetch
Execution
...
Set the data direction register to "00"
Initialize the control register
Load the contents of the peripheral
interface register into the accumulator
CRA
•
DORA •
CLR
CLR
LOAA
STAA
#$04
•
CRA
LOAA
PIRA
CLR
LOAA
STAA
~~:B}.
Clear the DDRA access bit of the control register to "0".
Clear all bits of the dada direction register.
Set DDRA access bit of the control register to "1" to allow
to access the peripheral interface register.
Set the data direction register to "FF"
Initialize the control register
Store the data in the accumulator into
output register
LOAA
STAA
CRA
•
Set DDRB access bit of the control register to "0".
Set all bits of the data direction--register to "FF".
~:::: }. Set DDRB access bit of the control register to "1" to allow to
access the peripheral interface register.
I
I
I
LOAA
STAA
I
DATA} •
PIRB
87
Write the data into the peripheral interface register.
HD6821, HD68A21, HD68821
• ReadlWrite Operating Using Control Lines
Read/write request from peripherals shall be put into the
control lines as an interrupt signal, and then MPU reads or
writes after detecting interrupt request.
The following case is that Port A is used and that the rising
edge of CAl indicates the request for read from peripherals.
Set the data direction register to "00"
CLR
CLR
CRA •
DORA.
LDAA #$06
Initialize the control register
Load the contents of the control register
into the accumulator
STAA CRA
•
Set the OORA access bit to "0".
Set all bits of the data direction register to "0".
Program the rising edge of CAl to be active. IRQA is masked
and OORA access bit is set to 1.
LOOP LDAA CRA }
•
BPL LOOP
Check whether the read request comes from peripherals
or not.
No
Load the contents of the peripherel
interface register into the accumulator
• Load the data from the peripheral interface register into the
accumulator. CRA flag is reset after this read operation.
LDAA PIRA
To read the peripheral data, the data is directly transfered to
the data buses 0 0 -0, through PAo-PA, or PBo-PB, and
they are not latched in the PIA. If necessary, the data should be
held in the external latch until MPU completes reading it.
When initializing the control register, interrupt flag bit
(CRA7, CRA6, CRB7, CRB6) cannot be written from MPU. If
necessary the interrupt flag must be reset by dummy read of
Peripheral Register A and B.
Write operation using the interrupt signal is as follows. In
this caseJ!.port is used and interrupt request is input to CB I .
And the IRQ flag is set at the rising edge of CB 1 •
88
HD6821, HD68A21, HD68B21 - - - - - - - - - - - - CLA
LOAA
Set the data direction register to "FF"
STAA
Initialize the control register
LOOP
CAB
•
Set DDRB access bit to "0"
#$FF }
OOA B
•
Set all bits of DDRB to output" I".
LOA A
#$06
STAA
CAB
• Program the rising edge of CB I to be active. IRQB is masked
and DDRB access bit is set to "I".
LOAA
CAB
Load the contents of the control
register into the accumulator
BPL
LOOP
Load the contents of the output
register in the accumulator
LOAA
PIAB
• Reset the CRB7 flag by the dummy read of the
peripheral interface register.
STAB
PIAB
•
• Check whether the write request comes from peripherals
or not.
No
Store the contents of the accumulator
into the output register
Store the data of the accumulator B to the peripheral
interface register.
(3) CRA7 flag is set and CA2 becomes "High" (CA2 automatically becomes "High" by the interrupt CAl). This
indicates the peripheral to maintain the current data and
not to transfer the next data.
(4) MPU accepts the read request by IRQA hardware interrupt
or CRA read. Then MPU reads the peripheral register A.
(5) CA2 goes "Low" on the following edge of read Enable
pulse. This informs that the peripheral can set the next data
to port A.
Interrupt request flag bits (CRA7, CRA6, CRB7 and CRB6)
cannot be written and they cannot be also reset by write
operation to the peripheral interface register. So dummy read of
peripheral interface register is needed to reset the flags.
To accept the next interrupt, it is essential to reset indirectly
the interrupt flag by dummy read of peripheral interface
register.
Software poling method mentioned above requires MPU to.
continuously monitor the control register to detect the read/
write request from peripherals. So other programs cannot run at
the same time. To avoid this problem, hardware interrupt may
when the
be used. The MPU is interrupted by IlUIA or
read/write request is occurred from peripherals and then MPU
analyzes cause of the interrupt request during interrupt processing.
• Handshake Mode
The functions of CRA and CRB are similar but not identical
in the hand-shake modes. Port A is used for read hand-shake
operation and Port B is used for write hand-shake mode.
CAl and CB I are used for interrupt input requests and CA 2
and CB2 are control outputs (answer) in hand-shake mode.
Fig. 16, Fig. 17 and Fig. 18 show the timing of hand-shake
mode.
CRB5 = "I", CRB4 = "0" and CRB3 = "0"
(1) A peripheral device requests MPU to write the data by using
CB I input. CB2 output remains "High" until MPU write
data to the peripheral interface register.
(2) CRB7 flag is set and MPU accepts the write request.
(3) MPU reads the peripheral interface register to reset CRB7
(dummy read).
(4) Then MPU write data to the peripheral interface register.
The data is output to port B through the output register.
(5) CB2 automatically becomes "Low" to tell the peripheral
that new data is on port B.
(6) The peripheral read the data on Port B peripheral data lines
and set CB I to "Low" to tell MPU that the data on the
peripheral data lines has been taken and that next data can
be written to the peripheral interface register.
mmr
< Read Hand-shake Mode>
CRA5=" 1", CRA4="0" and CRA3="0"
(1) A peripheral device puts the 8-bit data on the peripheral
CRA5 = "I", CRA4 = "0" and CRA3 = "I"
CRB5 = "I", CRB4 = "0" and CRB3 = "I"
This mode is shown in Figure 16, Figure 19 and Figure 20.
data lines after the control output CA2 goes "Low".
(2) !he peripheral requests MPU to read the data by using CAl
mput.
89
HD6821, HD68A21, HD68B21
Timing
CRAS CRA4 CRA3
E
R/W
CS·RS. ·RS o
/ / / /r----'
READ Request
t::
o
Q..
CRA7
o
o
The
o
1~:.::...:.;.::~ooooTJ
chan~e
of PAo-PA71
is not allowed. I
I
PA o -PA7\ are
Busy
I
I
allowed to ,be set.
Next PA o -PA are allowed to setr'~_ _ _ __
7
CA 2
Ready
Ready
I
~
________
~-J
Timing
CRBS CRB4 CRB3
E
R/W
PB o -PB _ _ _ _ _ _ _ _ _--<..
7
WRITE Request
CB'~///
dummy Read
Reset
CRB7
o
o
".
..
~-------~----~---~
UU2
o
PB o -PB 7 data is old.
,.....'----~B-us-y----... PB o -PB 7 data is new.
Ready
Figure 16 Timing of Hand-shake Mode and Pulse Mode
90
HD6821. HD68A21. HD68B21 - - - - - - - - - - - - -
Goes "High" on
transition of CAl
(I RQA 1 Flag bit set)
Goes "Low" when data on
"A" side has been read by
MPU after falling edge
of enable signal
pAl
~_~--------~ff
_CA_2____
L
Enable Signal (E)
Handshaking with peripheral on 'A' side
Data
PIRA
CAl
Peripheral
PIA
CA 2
7
I
0
CRA
x
0
II
0
0
0
Peripheral Says:
Here's new data
(Sets eRA7)
Figure 17 Bits 5,4, 3 of eRA = 100 (Hand-shake Mode)
91
HD6821, HD68A21, HD68B21 - - - - - - - - - - - - -
Goes "Low" on first
positive edge of enable
Goes "High" or transition
ocfBC2Bl
(lRa~Blfl.'.
~
bi.t.se.t.)_ _ _ _ _ _ _-4,',L: _ _ _ _ _ _ _ _ _
r
:!~~:~ ~fa~: :~~h~~.~"
side. (STA A PIRB)
(
L
Enable
signal
(E)
Handshaking with peripheral on 'B' side
Data
~/
I
I
PIRB
CBI
...
PIA
CB 2
~
I I I I I I I I I ~~
CRB
7
x
0
1
0
Peripheral
...
0
0
1
0
1
Says. Here s new data
(STA A PIRB)
;/
Peripheral
Request for data
Figure 18 Bits 5, 4, 3 of eRB = 100 (Hand-shake Mode)
92
HD6821, HD68A21, HD68B21
C~
Normally
"High"
Goes "Low" after a "Read a side
data" Instruction (LOA)
(Negative transition of E)
Goes "High" on
the negative
edge of the
next E pulse
after a
"Read a
side data"
Instruction
(LOA)
Enable
signal ( E ) - - - - '
Pulse mode
Pulse output on 'A' side
Oata
.Jr
I
If
I
PIRA
PIA
CRA
7
I
x
Peripheral
CA 2
0
1 0 1 1 1 0 11 1 1 1 x 1 x
I
Pu., initi""'''' ",.. It
of reading 'A' side
(LOA A PIRA)
~
A
Figure 19 Bits 5,4,3 of eRA = 101 (Pulse Mode)
Q3
Dol, ..R'..... by MPU
HD6821, HD68A21, HD68B21
CB 2 Normally
"High"
Goes "High" on the
next positive E
pulse after A
"write B
side data"
instruction
(STA)
Goes "Low" on the positive
transition of the first
E pu Ise after a "write B
side data" instruction
(STA)
Enable
signal
(E)
1 ..______. .
Pulse mode
Pulse output on 'B' side
Data
~
tl
I
PIRB
I
Peripheral
PIA
7
CRB
CB 2
0
I x 1 0 1 1 10 11 1 1 1 x 1 x I
Pulse initiated as a result
of writing into 'B' side
(STA A PIRB)
...
_
Xow" "
P'''''''''''
at port
for peripheral
Figure 20 Bits 5,4,3 of CRB=101 (Pulse Mode)
94
HD6821. HD68A21. HD68821 - - - - - - - - - - - - •
• SUMMARY OF CONTROL REGISTERS CRA AND CRB
Control registers CRA and CRB have total control of CAl,
CA 2 , CB I , and CB 2 lines. The status of eight bits of the control
registers may be read into the MPU. However, the MPU can only
write into Bit 0 through Bit 5 (6 bits), since Bit 6 and Bit 7 are
set only by CAl, CA 2 , CB I , or CB 2 •
When all the outputs of given PIA port are to be active "Low"
(True~ 0.4 volts), the following procedure should be used.
a)
b)
c)
d)
e)
• Addressing PIAs
Before addressing PIAs, the data direction (DDR) must first
be loaded with the bit pattern that defines how each line is to
function, i.e., as an input or an output. A logic "I" in the data
direction register defines the corresponding line as an output
while a logic "0" defines the corresponding line as an input.
Since the DDR and the peripheral interface resister have the same
address, the control register bit 2 determines which register is
being addressed. If Bit 2 in the control register is a logic "0",
then the DDR is addressed. If Bit 2 in the control register is a
logic "1", the peripheral interface register is addressed. Therefore, it is essential that the DDR be loaded first before setting
Bit 2 of the control register.
1.
2.
3.
4.
S.
6.
7.
(DORA, PIRA)
(CRA)
(DDRB, PIRB)
(CRB)
LOA A #%11110000
STAA
PIAIAD
LOA A #% 11111111
STA A
PIAIBD
LOA A #0/000000100
STAA
PIA lAC
STAA
PIAIBC
(4 outputs, 4 inputs)
(Loads A DDR)
(All outputs)
(Loads BOOR)
(Sets Bit 2)
(Bit 2 set in A control register)
(Bit 2 set in B control register)
1.
2.
3.
4.
S.
6.
7.
8.
#$ F004
PIA lAD
#$FF04
PIAIBD
All Is in peripheral interface register
Clear Bit 2
All 1s in data direction register
00 100 III ~ control register
Interchanging RSo And RS 1
Some system applications may require movement of 16 bits
of data to or from the "outside world" via two PIA ports (A
side + B side). When this is the case it is an advantage to
interconnect RS 1 and RS o as follows.
RS o to Al (Address Line AI)
RS 1 to AO (Address Line AO)
This will place the peripheral interface registers and control
registers side by side in the memory map as follows.
Table
PIA lAD
PIAIBD
PIAIAC
PIAIBC
The program shown in the previous section can be accomplished using the Index Register.
LOX
STX
WX
STX
Set Bit 2 in PIAIBC (control register)
•
PIA Programming Via The Index Register
1.
2.
3.
4.
LOA A#4
STA A PIAIBC
LOA B#$FF
STA B PIAIBD
CLRPIAIBC
STA B PIAIBD
LOA A #$27
STA A PIAIBC
The above procedure is required in order to avoid outputs
going "Low", to the active "Low" TRUE STATE, when allIs
are stored to the data direction register as would be the case if
the normal configuration procedure were followed.
Statement 2 addresses the DDR, since the control register
(Bit 2) has not been loaded. Statements 6 and 7 load the control
registers with Bit 2 set, so addressing PIAIAD or PIAIBD
accesses the peripheral interface register.
•
Set Bit 2 in the control register.
Store all Is ($FF) in the peripheral interface register.
Clear Bit 2 in the control register.
Store allIs ($FF) in the data direction register.
Store control word (Bit 2 = I) in control register.
The B side of PIAl is set up to have all active low outputs.
CB 1 and CB 2 are set up to allow interrupts in the HANDSHAKE MODE and CB 1 will respond to positive edges
("Low"-to-"High" transitions). Assume reset conditions. Addresses are set up and equated to the same labels as previous
example.
Given a PIA with an address of 4004, 4005, 4006, and 4007.
4004 is the address of the A side peripheral interface register.
4005 is the address of the A side control register. 4006 is the
address of the B side peripheral interface register. 4007 is the
address of the B side control register. On the A side, Bits 0, 1, 2,
and 3 will be defined as inputs, while Bits 4, 5, 6, and 7 will be
used as outputs. On the B side, all lines will be used as outputs.
PIA lAD = 4004
PIAIAC =4005
PIA I BD =4006
PIAIBC =4007
Active Low Outputs
Example Address
$4004
$4005
$4006
$4007
(DORA, PIRA)
(DDRB, PIRB)
(CRA)
(CRB)
$FO-+PIA lAD .;$04-+PIA I AC
The index register or stackpointer may be used to move the
16-bit data in two 8-bit bytes with one instruction. As an
example:
LDX PIAIAD
PIA lAD -++ IXl-r.: PIA IBD ~ IXL
$FF-+PIA I BD ;$04-+PIA 1BC
•
PIA - After Reset
When the RES (Reset Line) has been held "Low" for a
minimum of one microsecond, all registers in the PIA will be
cleared.
Because of the reset conditions, the PIA has been defined as
Using the index register in this example has saved six bytes of
program memory as compared to the program shown in the
previous section.
95
HD6821, HD68A21, HD68821 - - - - - - - - - - - - -
• SUMMARY OF CA2-CB2 PROGRAMMING
Bits 5, 4, and 3 of the control registers are used to program
the operation of CA2-CB2.
follows.
1. All I/O lines to the "outside world" have been defined as
inputs.
2. CAl, CA2 , CB,. , and CB2 have been defmed as interrupt
input lines that are negative edge sensitive.
3. All the interrupts on the control lines are masked. Setting of
interrupt flag bits will not cause m'OA or 'MOB to go "Low".
b5
CA,-CB,
Input ~
Mode
• SUMMARY OF CAl-CB l PROGRAMMING
Bits 1 and 0 of the respective control registers are used to
program the interrupt input contr.ollines CAl and CB l .
b1
bO
o
o
o
1
1
1
o
b1
bO
CA2 -CB 2
Output ~
Mode
b3
b4
I
[g0 g:=:
1(+)
0
1(+)
W
1
1
1
o
1
o
1
(Mask) CA2 -CB2 Input Mode
(Allow) b4 = Edge (0 = -, 1 = +)
(Mask) b3 = Mask (0 = Mask,
(Allow)
1 = Allow)
o - Handshake Mode
0
0
1 - Pulse Mode
~ } b3 Following Mode
1
1
~ Edge (0 = -, 1 = +)
= Mask (0 = Mask, 1 = Allow)
1
Note that this is the same logic as Bits 4 and 3 for CA2-CB2
when CA2-CB2 are programmed as inputs.
..
..
1/0 As Follow:
Control Lines:
CAl - Positive Edge, Allow Interrupt
CAt - Pulse Mode
CBI - Negetive Edge, Mask Interrupt
CB t - Hand Shake Mode
Assume Reset Condition
PIA1AD
PIA1AC
PIA1BD
PIA1BC
......
.....p
"A"
...
.
......
.
-..
....-
-
....
~------------
PIA Confiauration Solytion
LDA A #$BC
10111100
STA A PIA1AD
1/0 to DDRA
LDA A #$FF
11111111
STA A PIA1BD
1/0 to DDRB
LDA A #$2F
00101111
To "A" Control
STA A PIA1AC
LDA A #$24
00100100
STA A PiAi8C
To "8" Controi
..-
.
-..
···
·
"B"
.
--..
I------.~ PB o
Figure 21 PIA Configuration Problem
96
HDS840, HDS8A40, HDS8B40---PTM (Programmable Timer Module)
The HD6840 is a programmable subsystem component of the
HMCS6800 family designed to provide variable system time intervals.
The HD6840 has three 16-bit binary counters, three corresponding control registers and a status register. These counters are under
software control and may be used to cause system interrupts and/or
generate output signals. The HD6840 may be utilized for such tasks
as frequency measurements, event counting, interval measuring and
similar tasks. The device may be used for square wave generation,
gated delay signals, single pulses of controlled duration, and pulse
width modulation as well as system interrupts.
• FEATURES
•
Operates from a Single 5 Volts Power Supply
• Fully TTL Compatible
• Single System Clock Required (E)
• Selectable Prescaler on Timer 3 Capable of 4 MHz for
the HD6840, 6 MHz for the HD68A40 and
8 MHz for the HD68840
• Programmable Interrupts (I RQ) Output to MPU
• Readable Down Counter Indicates Counts to Go to Time-Out
• Selectable Gating for Frequency or Pulse-Width Comparison
HD6840P, HD68A40P, HD68840P
• RES Input
• Three Asynchronous External Clock and Gate/Trigger
Inputs Internally Synchronized
• Three Maskable Outputs
•
(DP-28)
• PIN ARRANGEMENT
BLOCK DIAGRAM
E
(SvstemrP,)
E
CSt
CSo
(Top View)
rt
Vss
1 1
Vee
RES
G,
c.
0,
13; C,
0,
G,
Co
0,
97
HD8840, HD88A40, HD88B40 - - - - - - - - - - - - - -
•
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Value
Input Voltage
Vee *
V in *
Operating Temperature
Topr
- 20-+ 75
Tstll
- 55-+150
Supply Voltage
Storage Temperature
Unit
-0.3-+7.0
V
-0.3-+7.0
V
°c
°c
* With respect to Vss (SYSTEM GND)
[NOTE) Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating
conditions. If these conditions are exceeded, it could affect reliability of LSI.
•
RECOMMENDED OPERATING CONDITIONS
Item
Symbol
min
typ
max
Unit
Supply Voltage
Vee *
4.75
5
5.25
V
Input Voltage
V 1L *
-0.3
-
0.8
V
V 1H *
2.0
-
- 20
25
Vee
75
°c
Operating"Temperature
Topr
V
* With respect to Vss (SYSTEM GND)
•
ELECTRICAL CHARACTERISTICS
•
DC CHARACTERISTICS (Vee = 5V ± 5%, Vss = OV, Ta = -20 - +75°C, unless othMWise noted.)
Item
Symbol
Test Condition
typ*
max
Unit
Vee
V
-2.5
-
- 10
min
Input "High" Voltage
V 1H
2.0
Input "Low" Voltage
V 1L
-0.3
Input Leakage Current
lin
V in = 0 - 5.25V (Except Do ..... 0 7 )
Three-State Input Current
(off-state)
I TS1
V in = 0.4 - 2.4V
Vee = 5.25V (Do - 0 7 )
Output "High" Voltage
V OH
Output "Low" Voltage
VOL
Output Leakage Current
(off-state)
I LOH
Power Dissipation
Pn
Input Capacitance
Output Capacitance
* Ta
0.8
V
2.5
J.l.A
-
10
J.l.A
2.4
-
-
V
I LOAD = 1.6 mA (Do - 0 7 )
I LOAD = 3.2 mA (0 1 - 0 3 , IRQ)
-
-
0.4
V
V OH = 2.4V (I RQ)
-
-
10
J.l.A
-
330
550
I LOAD = -205 J.l.A (Do - 0 7 )
I LOA D = -200 J.l.A (Other Outputs)
Cin
V in = OV
Ta = 25°C
f = 1 MHz
Do - 0 7
-
-
12.5
Other Input
-
-
7.5
Cout
V in = OV
Ta = 25°C
f = 1 MHz
IRQ
-
-
5.0
0 1 , O2 , 0 3
= 2SoC, vee = S.OV
98
10
mW
pF
pF
HD6840, HD68A40, HD68B40 - - - - - - - - - - - - - •
AC CHARACTERISTICS (Vee = 5V ± 5%, Vss = OV, Ta = -20 '" +75°C, unless otherwise noted.)
1. MPU READ TIMING
Symbol
Item
Test
Condition
HD6840
min
HD68A40
min
typ
10
0.666
-
10
0.5
-
10
4.5
0.280
-
4.5
0.22
-
4.5
-
-
-
IlS
IlS
IlS
25
ns
0.45
Enable "Low" Pulse Width
PWEL
0.43
-
-
0.280
Enable Rise and Fall Time
tEp tEf
-
-
25
-
Address Set Up Time
tAS
160
-
-
140
Data Delay Time
tOOR
-
-
320
-
Data Hold Time
tH
10
-
-
10
Address Hold Time
tAH
t ACC
10
-
-
10
Data Access Time
1.0
Fig. 1
-
Unit
max
tcycE
PW EH
Enable Cycle Time
Enable "High" Pulse Width
HD68B40
typ
-
480
max
min
-
0.21
25
-
-
70
220
-
typ
-
ns
-
-
180
ns
10
-
-
ns
10
-
-
ns
250
ns
-
360
max
2. MPU WR ITE TIMING
Item
Symbol
HD6840
Test
Condition
min
typ
HD68A40
max
max
-
10
0.5
-
10
IlS
4.5
0.22
-
4.5
IlS
-
-
IlS
25
ns
-
ns
-
Enable Cycle Time
tcycE
1.0
-
10
0.666
0.45
0.280
Enable Rise and Fall Time
t Ep tEf
-
Address Set Up Time
tAS
160
-
4.5
Enable "Low" Pulse Width
PWEH
PW EL
Data Set Up Time
tosw
195
Fig. 2
Data Hold Time
tH
10
Address Hold Time
tAH
10
-
Unit
typ
Enable "High" Pulse Width
0.43
HD68B40
min
min
typ
-
0.280
0.21
-
-
-
25
25
-
-
140
-
-
70
-
-
-
60
-
80
10
-
10
-
-
10
-
-
10
-
max
ns
ns
ns
3. TIMING OF PTM SIGNAL
Symbol
Item
Input Rise and Fall Times
C, G. RES
-
0.5"
j.ls
teveE+tsu+tHo
-
teyeE + tsu +t H0
-
tcveE+tSU+tHO
-
ns
teveE + tsu +t H0
-
teveE+tsu+tHo
-
teyeE +tsu +t H0
-
ns
200
-
120
-
75
-
200
-
120
-
75
-
PWH
Fig. 4
( Asynchronous )
Mode
C, G, RES
tsu
Fig. 5
( Synchronous )
Mode
tHO
Fig.5
( SynChrOnOUS)
Mode
PW L ,
PWH
(ASynChrOnOUS)
Mode
.
C, G, RES
Output Delay Time
CJ ("'8 Pre·
scaler Model
O. -
OJ
TTL
teo
MOS
tem
CMOS
Interrupt Release Time
*
Ir•
Unit
max
0.666"
C,G
Input Pulse Width
HD68B40
min
-
Input "High" Pulse Width
("'8 Pre·
scaler Model
max
1.0"
PWL
CJ
HD68A40
min
-
C,G,REs
Input Hold Time
max
Fig. 3, Fig. 4
Input "Low" Pulse Width
C, ("'8 Pre·
scaler Model
min
t r , tf
Fig. 3
( Asynchronous )
Mode
Input Setup Time
HD6840
Test.Condition
t cmos
tlR
Fig. 6
ns
50
-
50
-
50
-
50
-
50
-
50
-
ns
125
-
84
-
62.5
-
ns
VoH =2.4V,
Load B
-
700
-
460
-
340
ns
VOH=2.4V.
Load 0
-
450
-
450
-
340
ns
VOH=0. 7xV cC.
Load D
-
2.0
-
1.35
-
1.0
!1S
-
1.2
-
0.9
-
0.7
!1S
Fig. 7
tf ~ leveE
99
HD6840, HD68A40, HD68B40 - - - - - - - - - - - - -
E
RS,
CS,
RtW
Data Bus
Figure 1 Bus Read Timing
(Read Information from PTM)
Figure 2
Bus Write Timing
(Write Information into PTM)
~-c;
G;-G;
RES
Figure 3
Input Pulse Width "Low"
Figure 4
Input Pulse Width "High"
~2DV
\~tcmos*
~ -C;,G.-G;
RES
*
Figure 5
E
r
IRQ
OBV
r--lIR=*
,
,
2.4V
______________- J
Figure 7
VOH(CMOS)
Figure 6 Output Delay
Input Setup and Hold Times
I RQ Release Time
100
= 0.7 x vcc
HD6840, HD68A40, HD68B40 - - - - - - - - - - - - - -
Load B
(0 1 .0 2 .0 3 )
(TTL Load)
S.OV
Load A
(Do - 0,)
5.0V
---..----i.._-.
Test Point
Test Point O-....
All diodes are
IS2074@.
130 pF
o-....---..---I'e--.
40 pF
12 kn
Adjust RL
so that IOL = 3.2 rnA
then test VOL
All diodes are
= 152074
®.
Load C
d
(IRQ Only)
°
5.0V
Ton Po;",
Load
(0 1 .0 2 .0 3 )
(CMOS Load)
(MOS)
1.3 k!1
100pF
Test Point
I
1
30PF
1
Figure 8
Bus Timing Test Loads
MPU to control the PTM. VMA should be utilized in conjunction with an MPU address line into a Chip Select of
the PTM.
The three timers in the H06840 may be independently
programmed to operate in modes which fit a wide variety
of applications. The device is fully bus compatible with
HMCS6800 system and is accessed by load and store
operations from the MPU in much the same manner as a
memory device. In a typical application, a Timer will be
loaded by first storing two bytes of data into an associated Counter Latch. This data is then transferred into
the counter via a Counter Initialization cycle. The counter
decrements on each subsequent clock period which may
be an external clock or Enable (System cf>2) until one of
several predetermi-ned conditions causes it to halt or recycle. The timers are thus programmable, cyclic in nature,
controllable by external inputs or the MPU program, and
accessible by the MPU at any time.
•
Bidirectional Data (Do '" 0 7 )
The bidirectional data lines (0 0 "'0 7 ) allow the transfer
of data between the MPU and PTM. The data bus output
drivers are three-state devices which remain in the highimpedance (off) state except when the MPU performs a
PTM read operation (ReadlWrite and Enable lines "High"
and PTM Chip Selects activated).
• Chip Select (CS o , CSt)
These two signals are used to activate the Data Bus interface and allow transfer of data from the PTM. With CS;;
= "Low" and CSt = "High", the device is selected and
data transfer will occur.
•
PTM INTERFACE SIGNALS FOR MPU
The Programmable Timer Module (PTM) interfaces to
the HMCS6800 Bus with an eight-bit bidirectional data
bus, two Chip Select lines, a ReadlWrite line, an Enable
(System cf>2) line, an Interrupt Request line, an external
Reset line, and three Register Select lines. These signals, in
conjunction with the H06800 VMA output, permit the
•
ReadlWrite (R/W)
This signal is generated by the MPU to control the direction of data transfer on the Data Bus. With the PTM
selected, a "Low" state on the PTM R/W line enables the
input buffers and data is transferred from the MPU to the
101
HD6840, HD68A40, HD68840 - - - - - - - - - - - - an additional Enable period is required if setup times are
not met. The RES input must be stable "High"/"Low"
for the minimum time stated in the AC Characteristics.
Recognition of a "Low" level at this input by the PTM
causes the following action to occur:
a. All counter latches are preset to their maximal
count values.
b. All Control Register bits are cleared with the exception of CR 10 (internal reset bit) which is set.
c. All counters are preset to the contents of the latches.
d. All counter outputs are reset and all counter clocks
are disabled.
e. All Status Register bits (interrupt flags) are cleared.
PTM on the trailing edge of the Enable (System <1>2 ) signal.
Alternately, (under the same conditions) RiW = "High"
and Enable "High" allows data in the PTM to be read by
the MPU.
• Enable (E)
This signal synchronizes data transfer between the
MPU and the PTM. It also performs an equivalent synchronization function on the external clock, reset, and
gate inputs of the PTM.
•
Interrupt Request (J RQ)
The active "Low" Interrupt Request signal is normally
tied directly (or through priority interrupt circuitry) to
the TROinput of the MPU. This is an "open drain" output
(no load device on the chip) which permits other similar
interrupt request lines to be tied together in a wire-OR
configuration.
The I RQ line is activated if, and only if, the Composite
Interrupt Flag (Bit 7 of the Internal Status Register) is
asserted. The conditions under which the I RQ line is activated are discussed in conjunction with the Status
Register.
•
Register Select Lines (RS o , RS 1 , RS 2 )
These inputs are used in conjunction with the R/W line
to select the internal registers, counters and latches as
shown in Table 1.
It has been previously stated that the PTM is accessed
via MPU Load and Store operations in much the same
manner as a memory device. The instructions available
with the HMCS6800 family of MPUs which perform
operations directly on memory should not be used when
the PTM is accessed. These instructions actually fetch a
byte from memory, perform an operation, then restore it
to the same address location. Since the PTM used the R/iN
line as an additional register select input, the modified
data may not be restored to the same register if these
instructions are used.
•
External Reset (RES)
A "Low" level at this input is clocked into the PTM by
the Enable (System <1>2) input. Two Enable pulses are
required to synchronize and process the signal. The PTM
then recognizes the active "Low" or inactive "High" on
the third Enable pulse. If the RES signal is asynchronous,
Table 1 Register Selection
Register
*
Select Inputs
Operations
R/W
= "Low"
= "High"
RS,
RS!
RS.
L
L
L
= "0"
CR20 = "1"
L
L
H
Write Control Register #2
Read Status Register
L
H
L
Write MSB Buffer Register
Read Timer #1 Counter
CR20
Write Control Register #3
Write Control Register #1
R/W
No Operation
L
H
H
Write Timer #1 Latches
Read LSB Buffer Register
H
L
L
Write MSB Buffer Register
Read Timer #2 Counter
H
L
H
Write Timer #2 Latches
Read LSB Buffer Register
H
H
L
Write MSB Buffer Register
Read Timer #3 Counter
H
H
H
Write Timer #3 Latches
Read LSB Buffer Register
* L; "Low"level. H; "High" level
the limit Imposed by Enable (System ¢2) Setup, and Hold
time.
The external clock inputs are clocked in by Enable
(System ¢2) pulses. Three Enable periods are used to
synchronize and process the external clock. The fourth
Enable pulse decrements the internal counter. This does
not affect the input frequency, it merely creates a delay
between a clock input transition and internal recognition
of that transition by the PTM. All references to C inputs
in this document relate to internal recognition of the
input transition. Note that a clock "High" or "Low" level
which does not meet setup and hold time specifications
may require an additional Enable pulse for recognition.
•
PTM ASYNCHRONOUS INPUT/OUTPUT SIGNALS
Each of the three timers within the PTM has external
clock and gate inputs as well as a counter output line. The
inputs are high impedance, TTL compatible lines and
outputs are capable of driving two standard TTL loads.
Clock Inputs (~ , C2 , C 3 )
Input pins Ct , C2 , and C3 will accept asynchronous TTL
voltage level signals to decrement Timers 1, 2, and 3,
respectively. The "High" and "Low" levels of the external
clocks must each be stable for at least one system clock
period plus the sum of the setup and hold times for the
inputs. The asynchronous clock rate can vary from de to
•
102
HD6840, HD68A40, HD68B40 - - - - - - - - - - - - dent of the -=-8 prescaler selection.
When observing recurring events, a lack of synchronization will result in "jitter" being observed on the output of
the PTM when using asynchronous clocks and gate input
signals. There are two types of jitter. "System jitter" is
the result of the input signals being out of synchronization with the Enable (System Counter Time Out
Single Shot Mode: Gate t or Reset Causes Counter Initialization
Pulse Width Comparison Mode: Interrupt If Gate
Interrupt Flag Masked (fAll)
Interrupt Flag Enabled (IRQ)
Timer Output Masked
"1" Timer Output Enable
(NOTE) Reset is Hardware or Software Reset (RES
= "Low" or CR10 = "1 ").
105
L-J is> Counter Time Out
HD6840, HD68A40, HD68B40 - - - - - - - - - - - - condition (RES = "Low" or CR10 = "1") is recognized. It
can also occur - depending on Timer Mode - with a
Write Timer Latches command or recognition of a negative transition of the Gate input.
Counter recycling or re-initialization occurs when a
negative transition of the clock input is recognized after
the counter has reached an all-zero state. In this case, data
is transferred from the Latches to the Counter.
and 5 of the corresponding control register. Assuming that
the timer output is enabled (CRX7 = "1 "), either a square
wave or a variable duty cycle waveform will be generated
at the Timer Output, OX. The type of output is selected
via Control Register Bit 2.
Either a Timer Reset (CR 10 = "1" or External RES
= "Low") condition or internal recognition of a negative
transition of the Gate input results in Counter Initialization. A Write Timer Latches command can be selected as
a Counter Initialization signal by clearing CRX4 .
The counter is enabled by an absence of a Timer Reset
condition and a "Low" level at the Gate input. The
counter will then decrement on the first clock signal
recognized during or after the counter initialization cycle.
It continues to decrement on each clock signal so long as
G remains "Low" and no reset condition exists. A
Counter Time Out (the first clock after all counter bits
= "0") results in the Individual Interrupt Flag being set
and re-initialization of the counter.
A special condition exists for the dual 8-bit mode
(CRX2 = "1") if L = "0". In this case, the counter will
revert to a mode similar to the single 16-bit mode, except
Time Out occurs after M+l clock pulses. The output, if
enabled, goes "Low" during the Counter Initialization
cycle and reverses state at each Time Out. The counter
remains cyclical (is re-initialized at each Time Out) and
the Individual Interrupt Flag is set when Time Out occurs.
If M = L = "0", the internal counters do not change, but
the output toggles at a rate of 1/2 the clock frequency.
In the dual 8-bit mode (CRX2 = "1") [Refer to the
example in Fig. 9] the MSB decrements once for every
full countdown of the LSB + 1. When the LSB = "0", the
•
TIMER OPERATING MODES
The HD6840 has been designed to operate effectively
in a wide variety of applications. This is accomplished
by using three bits of each control register (CRX3, CRX4,
and CRX5) to defined different operating modes of the
Timers. These modes are outlined in Table 4.
Table 4 Operating Modes
Control Register
CRX3
CRX4
CRX5
Timer Operating Mode
0
0
Continuous
0
*
*
1
Single-Shot
1
0
Frequency Comparison
1
1
*
*
Pulse Width Comparison
* Defines Additional Timer Functions.
In addition to the four timer modes in Table 4, the
remaining control register bit is used to modify counter
initialization and enabling or interrupt conditions.
•
Continuous Operating Mode (Table 5)
Any of the timers in the PTM may be programmed to
operate in a continuous mode by writing "O"s into bits 3
Table 5 Continuous Operating Modes
CONTINUOUS MODE
(CRX3 = "0", CRX5 = "a")
Control Register
CRX2
CRX4
0
-
G~
0
0
1
1
0
1
Initialization/Output Waveforms
Counter Initialization
I
1
-
G~+W+R
*Timer Output (OX) (CRX7 = "1")
1N + lJ(Tl--j--IN +lI1TITIN + 1)ITl1
I
-
G~+R
-
G~+W+R
-
G~+R
= Negative transition of Gate
rI
to
I
I
TO
TO
I-VoH
I
VOL
TO
f-- IL + 111M + lilT) -r--IL + 111M + ll1Tl---l
V
~-OH
--i
I
to
I Ll IT)
f-TO
--l
VOL
I L)IT)
r--
TO
input.
W = Write Timer Latches Command.
R = Timer Reset (CRlC
= "1" or
External RES = "Low")
N = 16-Bit Number in Counter Latch.
L
= 8-Bit Number in LSB Counter Latch.
M = 8·Bit Number in MSB Counter Latch.
T
= Clock Input Negative Transitions to Counter.
to = Counter Initialization Cycle.
TO= Counter Time Out (All Zero Condition).
* All time intervals shown above assume the Gate (3) and Clock (C) signals are synchronized to Enable
(System cf>2 ) with the specified setup and hold time requirements.
106
I
HD6840, HD68A40, HD68840 - - - - - - - - - - - - *Time
Out
Example: Contents of MSB = 03 = M
Contents of LSB = 04 = L
t
M(L + 1) + 1
Algebraic Expression
03(04 + 1) + 1 =
16 Enables
-------fl,------
2.4 V
- - - - - + ' 1 - - - - 0.4 V
Counter Output
E
(System
4>2 )
:
I
I
I
I
I
I
I
I
1 + L - - - I....~---- 1 + L --~.~I._-1+L ~
I
5 Enable
5 Enable
I
5 Enable
Pulses
Pulses
Pulses
~
I
4 Enable
Pulses
I
_l+L-
:
5 Enable
Pulses
I
I
I
(M+il(~~+1l
,:
I
I
I
I
:.--..,
*
I
I
**
t
~
I
**
I
~
-.!
I
I
!
**
*
Algebraic Expression
(04 + 1) (03 + 1) = 20 Enable or
External Clock Pulses
(M + 1) (L + 1) = Period
M(L + 1) + 1 = "Low" portion of period
L = Pulse width
* Preset LSB and MSB to Respective Latches on the negative transition of the E.
** Preset LSB to LSB Latches and Decrement MSB by one on the negative transition of the E.
Figure 9 Timer Output Waveform Example
(Continuous Dual 8-Bit Mode using Internal Enable)
ble are shown in Table 6.
As indicated in Table 6, the internal counting mechanism remains cyclical in the Single-Shot Mode. Each
Time Out of the counter results in the setting of an
Individual Interrupt Flag and re-initialization of the
counter.
The second major difference between the Single-Shot
and Continuous modes is that the internal counter enable
is not dependent on the Gate input level remaining in the
"Low" state for the Single-Shot mode.
Another special condition is introduced in the SingleShot mode. If L = M = "0" (Dual 8-bit) or N = "0" (Single
16-bitl, the output goes "Low" on the first clock received
during or after Counter Initialization. The output remains
"Low" until the Operating Mode is changed or nonzero
data is written into the Counter Latches. Time Outs continue to occur at the end of each clock period.
The three differences between Single-Shot and Continuous Timer Modes can be summarized as attributes of
the Single-Shot mode:
1. Output is enabled for only one pulse until it is
reinitialized.
2. Counter Enable is independent of Gate.
3. L = M = "0" or N = "0" disables output.
Aside from these differences, the two modes are identical.
MSB is unchanged; on the next clock pulse the LSB is
reset to the count in the LSB Latches and the MSB is
decremented by 1 (one). The output, if enabled, remains
"Low" during and after initialization and will remain
"Low" until the counter MSB is all "O"s. The output will
go "High" at the beginning of the next clock pulse. The
output remains "High" until both the LSB and MSB of
the counter are all "O"s. At the beginning of the next
clock pulse the defined Time Out (TO) will occur and the
output will go "Low". In the normal 16-bit mode the
period of the output of the example in Fig. 9 would span
1546 clock pulses as opposed to the 20 clock pulses using
the Dual 8-bit-mode.
The discussion of the Continuous Mode has assumed
that the application requires an output signal. It should be
noted that the Timer operates in the same manner with
the output disabled (CRX7 = "0"). A Read Timer
Counter command is valid regardless of the state of CRX7.
•
Single-8hot Timer Mode
This mode is identical to the Continuous Mode with
three exceptions. The first of these is obvious from the
name - the output returns to a "Low" level after the
initial Time Out and remains "Low" until another
Counter Initialization cycle occurs. The waveforms availa-
107
HD6840, HD68A40, HD68840 - - - - - - - - - - - - •
tion cycle, an Individual Interrupt Flag is set. The counter
is disabled, and a Counter Initialization cycle cannot begin
until the interrupt flag is cleared and a negative transition
on "IT is detected.
Frequency Comparison or Period Measurement Mode
(CRX3
="1", CRX4 ="0")
The Frequency Comparison Mode with CRX5 = "1" is
straightforward. If Time Out occurs prior to the first negative transition of the Gate input after a Counter Initializa-
Table 6 Single-Shot Operating Modes
Single-Shot Mode
(CRX3
="0", CRX7 = "1". CRX5 = "1")
Initialization/Output Waveforms
Control Register
CRX2
CRX4
Counter Initialization
0
0
G~+W+R
0
1
G~+R
1
0
G~+W+R
1
1
G~+R
II
r'
Timer Output (OX)
(N+1 )(T) ~(N+1 )(T)
I--(N)(T)
~
I
to
TO
L+lI1M+l) 1T);",'j::L+lI1M+l)
--j(L)(T)
to
/ lTO
1
ITll
TO
TO
Symbols are as defined in Table 5 .
•
Time Interval Modes
The Time Interval Modes are provided for those applications which require more flexibility of interrupt generation and Counter Initialization. Individual Interrupt Flags
are set in these modes as a function of both Counter Time
Out and transitions of the Gate input. Counter Initialization is also affected by Interrupt Flag status.
The counter does operate in either Single 16-bit or
Dual 8-bit modes as programmed by CRX2. Other
features of the Time Interval Modes are outlined in Table
If CRX5 = "0", as shown in Table 7 and Table 8, an
interrupt is generated if Gate input returns "Low" prior
to a Time Out. If Counter Time-Out occurs first, the
counter is recycled and continues to decrement. A bit is
set within the timer on the initial Time Out which precludes further individual interrupt generation until a new
Counter Initialization cycle has been completed. When
this internal bit is set, a negative transition of the Gate
input starts a new Counter Initialization cycle. (The
condition of G,j..·T·TO is satisfied, since a Time Out has
occurred and no individual Interrupt has been generated.)
7.
Table 7 Time Interval Modes
CRX3 = "1"
CRX4
CRX5
Application
0
0
Frequency Comparison
Interrupt Generated if Gate Input Period (1/F) is less
than Counter Time Out (TO)
0
1
Frequency Comparison
Interrupt Generated if Gate Input Period (1 IF) is greater
than Counter Time Out (TO)
1
0
Pulse Width Comparison
Interrupt Generated if Gate Input "Down Time" is less
than Counter Time Out (TO)
1
1
Pulse Width Comparison
Interrupt Generated if Gate Input "Down Time" is greater
than Counter Time Out (TO)
Condition for Setting Individual Interrupt Flag
Any of the timers within the PTM may be programmed
to compare the period of a pulse (giving the frequency
after calculations) at the Gate input with the time period
required for Counter Time-Out. A negative transition of
the Gate input enables the counter and starts a Counter
Initialization cycle - provided that other conditions as
noted in Table 8 are satisfied. The counter decrements
on each clock signal recognized during or after Counter
Initialization until an Interrupt is generated, a Write Timer
Latches command is issued, or a Timer Reset condition
occurs. It can be seen from Table 8 that an interrupt con-
dition will be generated if CRX5="0" and the period of
the pulse (single pulse or measured separately repetitive
pulses) at the Gate input is less than the Counter Time
Out period. If CRX5 = "1", an interrupt is generated if
the reverse is true.
Assume now with CRX5 = "1" that a Counter Initialization has occurred and that the Gate input has returned
"Low" prior to Counter Time Out. Since there is no
Individual Interrupt Flag generated, this automatically
starts a new Counter Initialization Cycle. The process
will continue with frequency comparison being performed
108
HD6840, HD68A40, HD68B40 - - - - - - - - - - - - _
on each Gate input cycle until the mode is changed, or
a cycle is determined to be above the predetermined limit.
•
the time period required for Counter Time Out. With
CRX5 = "1", the interrupt is generated when the reverse
condition is true .
As can be seen in Table 9, a positive transition of the
Gate input disables the counter. With CRX5 = "0", it is
therefore possible to directly obtain the width of any
pulse causing an interrupt. Similar data for other Time
Interval Modes and conditions can be obtained, if two
sections of the PTM are dedicated to the purpose.
Pulse Width Comparison Mode (CRX3 = "1", CRX4
= "1")
This mode is similar to the Frequency Comparison
Mode except for a positive, rather than negative, transition of the Gate input terminates the count. With CRX5=
"0", an Individual Interrupt Flag will be generated if the
"Low" level pulse applied to the Gate input is less than
Table 8 Frequency Comparison Mode
CRX3 = "''', CRX4 = "0"
Control Reg
BitS (CRXS)
Counter
Initialization
Counter Enable
Flip-Flop Set (CE)
Counter Enable
Flip-Flop Reset (CE)
Interrupt Flag
Set (I)
0
G~·T·(CE+TO)+R
G~,w·R·T
W+R+I
G~
1
G~:j"+R
G~'W'R'I
W+R+I
TO Before
Before TO
G~
I represents the interrupt for a given timer.
Table 9 Pulse Width Comparison Mode
CRX3 = "''', CRX4 = "'"
Control Reg
BitS (CRXS)
Counter
Initialization
Counter Enable
Flip-Flop Set (CE)
Counter Enable
Flip-Flop Reset (CE)
Interrupt Flag
Set (I)
0
G~'I+R
G~;W'R'I
W+R+I+G
Gt Before TO
1
G~·T+R
IX!
OJ
(/)
D•
IX!
Os
o.
::>
STRB
(8)
I~
ITEMPORARY
COUNTER
II
I
II III
J
lCT
e»
w
~
FI
<{
lOX
<{
0
0,
TRZ
WPT
EFIA
ROY
CS
Iuw
RS,
~o
RS,
R/W
E
Bo
lnl
.J.J
ffi~
1-2
(/)0
_u
HoR
Hlo
WGT
..
(!)
w
VFOC
WoT
a:
oCK
ROT
Figure 13 Block Diagram ofthe FDC
.
ca
l-
RS o
:::t
C
:::t
C
ca
..
~
w
(I)
HD6843S, HD68A43S
operations is stored in the LTAR by the bus interface.
• GENERAL DESCRIPTION
The HD6843SP FDC consists of four primary sections; the
Register, Serializing. Bus Interface, and Control sections. The
following explanation of these sections can be followed in the
block diagram of Figure 13.
• Serializing Section
The serializing section handles the serial-to-parallel and
parallel-to-serial conversions for Read/Write operations as well
as CRC generation/checking and the generation/detection of the
clock pattern. The Data Output Shift Register (DOSR), Data
Input Shift Register (DISR) , CRe Generator/Checker, and
Clock Shift Register (CSR) comprise the serializing section of
the FOC.
• Register Section
The register section consists of twelve user accessible registers
used for controlling a floppy disk drive. All twelve are
connected by the internal data bus to allow the processor access
to them.
• Bus Interface
The Bus Interface section provides the timing and control
logic that allows the FDC to operate with the 6800 bus, and is
comprised of the Data Buffers. Request Control, and the
Register Select circuitry.
Data Output Register (DOR)
The DOR is an 8-bit register which holds the data to be
written onto the disk. The information is stored here by the bus
interface.
Data Input Register (DIR)
The data words read from the disk are stored in the 8-bit
DIR until read by the bus interface.
• Control
The internal timing and control signals which sequence the
FDC are derived from the macro instructions by the control
section.
Current Track Address Register (CTAR)
CTAR is a 8-bit register containing the address of the track
over which the R/W head is currently positioned.
• HD6843SP PIN DESCRIPTION
• Power Pins
Vee: +5 volt (±5%) power input.
Vss: Power Supply Ground.
Command Register (CMR)
The macro commands are written to the 8-bit CMR to begin
their execution.
• Bus Pins
Interrupt Status Register (lSR)
The four bits of the ISR represent the four conditions that
can cause an interrupt to occur.
Reset (RES) Input
The RES input is used to initialize the FOC. When RES
becomes "Low", the state of the outputs is defined by the table
below:
Set-Up Register (SUR)
Variable Seek and Settling times are programmed by the
SUR: Four bits are used to program the track to track seek time
and four bits are used to program the head settling time for the
floppy disk drive used with the FOC.
Output
FIR
WGT
HDR
STP
Status Register A (STRA)
The eight bits of STRA are used to indicate the state of the
floppy disk interface.
Sector Address Register (SAR)
SAR contains the five bit sector address associated with the
current data transfer.
State of Output
"Low"
"Low"
"Low"
"Low"
Output
HLD
TxRQ
IRQ
WDT
State of Output
"Low"
"Low"
"High"
"Low"
Registers which are affected by RES are shown in Table 7.
Status Register B (STRB)
The eight error flags of STRB are used to signify error
conditions detected by the FDC or generated by the floppy disk
drive.
Interrupt Request (I RQ) Output
The IRQ line is an open drain output that becomes a "Low"
level (logic "O") when the FDC requests an interrupt. Interrupt
requests are controlled by the interrupt enables in CMR
(Command Register) with the function causing the interrupt
shown in ISR (Interrupt Status Register).
General Count Register (GCR)
The seven bits of GCR contain the destination track address
when a SEK (seek) macro command is being executed. If a
multi-sector Read or Write macro command is being executed,
GCR contains the number of sectors to be read or written.
Data Bus O-Data Bus 7 (Do -0 7 ) Bidirectional
The 8 bidirectional data lines allow the transfer of data
between the FOC and the controlling system. The output
buffers are three-state drivers that are enabled when the FDC is
transferring data to the data bus.
CRC Control Register (CCR)
The two bits of the CCR are used to enable the CRC and
shift the CRC for the Free Format Commands.
Enable (E) Input
The E input to the FDC causes data transfers to occur
between the FDC and the system controlling the FDC
Logical Track Address Register (LTAR)
The seven bit track address used for read and write
119
HD6843S, HD68A43S - - - - - - - - - - - - - -
(HMCS6800 MPU, OMA Controller, etc.) E must be a logic "1"
("High" level) for any transfer to be enabled on 0 0 ......0,. The E
input is normally connected to system (/)2 •
Chip Select (CS) Input
The CS input in conjunction with the E input, is used to
enable data transfers on 0 0 ...... 0,. E must be a "High" level and
CS must be a "Low" level (logic "0") to enable the transfer.
The TxAK input being a "High" level (logic "1 ") performs a
similar function as CS being a "Low" level.
causes the FDC to neglect the state of RSo...... RS2 causing thl
FDC to select the DOR (Data Output Register) or DIR (Dat~
Input Register) to the data bus (00-0,) as shown in Table 2
CS = "0" and TxAK = "I" cannot be permitted at the samE
time.
Table 2 Register Selection for DMA Transfers
TxAK
RSo-R~
CS
RIW
Register
Selected
ReadlWrite (RJW) Input
1
1
DOR
1
x
x
1
The R/W input is issued by the system controlling the FDC
(HMCS6800 MPU, OMA Controller, etc.) to signify if a read or
write operation is to be performed on the FDC. When TxAK is a
"Low" level, R/W is used in conjunction with CS and RSO ...... RS 2
to determine which register is accessed by the bus as shown in
Table 1. When TxAK is a "High" level, R/W is used to select
either the OOR or DIR to the data bus (see description of
TxAK input).
1
0
DIR
This mode of operation is normally used for DMA (Direct
Memory Access) transfer with the FDC.
When TxAK is a "Low" level the registers are selected by CS,
R/W and RSo-RS2 as shown in Table 1.
Register Select O...... Register Select 2 (RSo...... RS2 ) Input
•
RS o-RS 2 , in conjunction with the R/W input, are used
to select one of the user accessible registers in the FDC as
shown in Table I.
Bus Direction (BD) Output
The BD output is provided to control external bidirectional
buffers on the data bus (Oo-D,) as shown in Figure 14. Its
polarity is shown by Table 3.
Transfer Request (TxRQ) Output
TxRQ is used in the OMA mode to request a data transfer
Table 3 Bus Direction (BD) States
from the DMAC. TxRQ is a "High" level if the FDC is in the
DMA mode (CMR bit 5 is set) when a data transfer request
occurs (STRA bit 0 is set). It is reset to a "Low" level (logic
"0") when TxAK becomes a "High" level (logic "1"). Data
transfer errors will occur if TxAK does not reset TxRQ before
the next data transfer is required.
TxAK
CS
BD
1
0
0
1
1
0
RIW
0
RIW
(Operation of BO as defined by this chart allows the FOe to function
Transfer Acknowledge (TxAK) Input
with the DMA Controller H D6844P.)
TxAK is generated by the system controlling the FDC
(HMCS6800 MPU, DMA Controller, etc.) and is a response to a
TxRQ issued by the FDC. A "High" level (logic "I") on TxAK
Table 1 Address Codes for User Accessible Registers
TxAK
CS
RS2
RS.
RSo
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
R/W
0
1
0
0
1
1/0
,.
v
1
Registers
DOR (Data Output Register)
01 R (Data Input Register)
CTAR (Current Track Address Register)
CMR (Command Register;
1
ISR (Interrupt Status Register)
0
SUR (Set Up Register)
1
STRA (Status Regiser A)
0
SAR (Sector Address Register)
1
STRB (Status Register B)
0
0
1
0
0
0
0
0
0
1
0
1
0
GCR (General Count Register)
0--_._-----
1
1
0
CCR (CRC Control Register)
0
1
1
1
0
0
120
LTAR (Logical Track Address Register)
HD6843S, HD68A43S - - - - - - - - - - - - - -
,----------,
Din
MPU
I
+-~~--~--~--~
,
~~---+-~-+--
FOe
Rout,
,
,
,
,I
I
I
I _________ _
L
HDST26
Enable
Figure 14
•
Bus Buffer Control
B is read.
I/O and Control Pins
Head load (HlO) Output
HLD is used to notify the disk drive that the RfW head
should be loaded (placed in contact with the media). When the
FDC is ready for the head to load, HLD is a "High" level (logic
"1 "). A "Low" level (logic "0") HLD indicates the head should
be unloaded.
File Inoperable (FI) Input
FI is an input to the FDC from the drive. A "High" level
indicates the drive is in an inoperable state. Its current state can
be examined by reading bit 5 of Status Register B (STRB).
Step (STP) Output
The STP output, in conjunction with HDR, is used to control
head movement. A 32 IlS wide positive (logic "1") pulse is
generated on STP, to move the R/W head one track in the
direction defined by the HDR output. The period of the STP
signal is programmable by the SUR (Set-Up Register). The
number of pulses generated on STP is the difference between
the contents of the CTAR (Current Track Address Register),
and the GCR (General Count Register) which contains the track
address to which the head is to be moved.
Head Direction (HOR) Output
The HDR signal controls the direction of head movement. A
"High" level (logic "1") signifies the head should step to the
inside (toward the hub) of the disk. A "Low" level (logic "0")
indicates the direction of head movement should be to the
outside of the disk.
Track Zero (TRZ) Input
The TRZ input is reflected by bit 3 of STRA (Status Register
A). The TRZ input must be a "High" level (logic "I") when the
R/W head of the drive is positioned over track zero. A logic" 1"
on this input inhibits step pulses during a Seek Track Zero
command.
Index (lOX) Input
The index input is received from the floppy disk drive and is
used to sense the index hole in the disk media. The IDX signal is
used to initialize the intemalFDC timing. The state of the lOX
input is reflected by bit 6 of Status Register A (STRA). A
"High" level (logic "1") is to indicate the index hole is under the
index sensor. The index input is used to count the number of
disk revolutions while searching for the address 10 field (see
description of STRB bit 3).
Ready (ROY) Input
The ready input is received from the disk drive and can be
read as bit 2 of STRA (Status ReJtister A). A "Hidt" level (logic
"1") indicates the drive is ready and allows the FDC to operate
the drive.
low Current Track (lCT) Output
The LCT signal is used to control the level of write current
used by the disk. drive. LCT is a "Low" level (logic "0") when
the write head is positioned over tracks 0~43. If it is over tracks
44-76, LCT is a "High" level (logic "1 "). LCT is determined
from the contents of the Current Track Address Register
(CTAR).
Write Protect (WPT) Input
WPT is an input indicating when the media is Write
Protected. A "High" level during an FDC write operation results
in a Write Error (STRB bit 6) but the FDC continues to perform
the write function. The state of the WPT input can be read by
examining bit 4 of the Status Register A (STRA).
Write Gate (WGT) Output
When a write operation is being performed, WGT is a logic
"I" ("High" level). For a read operation, WGT is a "Low" level
(logic "0").
File Inoperable Reset (FIR) Output
FIR is an output from the FDC to the floppy disk drive to
reset it from an inoperable status. If the FI input is a "High"
level, a pulse, of which width almost equals to E pulse "Low"
width, is generated on the FIR output whenever Status Register
121
Clock (ClK) Input
The CLK input is used to generate various timing sequences
internal to the FDC. The head settling, seek time, step pulse
width and write data pulse width, etc., are generated from the
CLK input signal. The CLK is 1 MHz frequency and the duty is
50%.
HD8843S, HD88A43S - - - - - - - - - - - - - • Data Pins
Data Clock (OCK) Input
OCK is used to clock data from the drive into the FOC. It is
generated from the read data received from the drive.
Clock
f = Frequency of the ClK Input. To insure IBM3740
compatibility the clock frequency must be 1 MHz.
Read Data (ROT) Input
RDT is the serial data input from the drive. The data stream
includes both the clock and data bits.
Figure 15 WDT Output Timing
Write Data (WOT) Output
WDT is the double frequency modulated data output from
the FOC. The time between clock bits is 4/f where f is the
frequency of the clock input. The pulse width for both clock
and data is I/f (see Figure 15). For the normal clock frequency
of I MHz the clock period is 4 IlS, the clock pulse width is. 1 IlS
and the data pulse width is I IlS. Figure 15 shows the
relationship between the WDT output and the frequency of the
eLK inputs.
• FORMAT
The format used by the HD6843SP, shown in Figure 18,
compatible with the soft sector format of the IBM3740.
• MACRO COMMAND SET
The macro command set shown in Table 4 is discussed in th
following paragraphs.
Variable Frequency Oscillator Control (VFOC) Output
VFOC is used as a sync signal during system diagnostics.
Waveforms are shown in Figure 16.
SSR, RCR, MSR Command
lOX
DiSk~~
~~-,O--'
_ _G"S_....iI.;.Gl....i1
"High"
GJ
!----~
Data
10
WGT
VFOC
2 bits
2 bit.
SSW, SWO, MSWCommand
o;'k~
WGT
lOX
G.
IG'~~-'-O-
"rl ~ ~ ~'bvm
G I"--o-a-ta--',
~--------------~
G.
10
~--------
In FFW Command, VFOC becomes "High" when WGT is at "High" level.
In FFR Command, VFOC remains "High".
Figure 16 Variable Frequency Oscillator Control Waveform
(Relation Between WGT and VFOC)
122
G3
HD6843S, HD68A43S
SSW, SWD and MSW commands (Single Sector Write, Single Sector Write with Delet Data Mark, and Multi-Sector Write)
~b,
WGT--~
C
D
C
C
D
---~
WDT
(1) 1.0 jJS (typ)
0.7 jJS (min)
1.3 jJS (max)
(2) 0 jJS (min)
0.3 jJS (max)
Figure 17 Write Data versus Write Gate Timing
Index
...-II1.o..--------------fHI------------rL
Gap 1
Gap 2
Track
Format
Preamble
46 Bytes
r=::-l
(Post-Index)
32 Bytes
~
o
Index
Address Mark
Data = FC
Clock = D7
ID
A~~~~ss
Sector
Format
Data = FE
Clock = C7
Sector 2
'sector
l'
Sector 25
'sectorJ IJ
Gap 3
(lD Gap)
1 7 Bytes
8:=v:=H~ ~,-Address ID Field
Data
6 Bytes
Address Mark
Data=FB or F8
1 - Track Address
Clock = C7
2 - 00 Byte
3 - Sector Address
4 - 00 Byte
5- CRC
6-CRC
~ector 2~
s!ctor 2 6 U
Gas 5
274 Bytes
(Pre-Index Gap)
Gap 4
(Data Gap)
33 Bytes
____--" I~~
Data
128 Bytes
CRC
2 Bytes
Next 10
Address Mark
Figure 18 Soft Sector Format
Table 4 Macro Command Set
CMR Bits
Macro Command
1
2
3
4
5
6
7
8
9
10
STZ
SEK
SSR
S9N
RCR
9ND
MSW
MSR
FFW
FFR
Seek Track Zero
Seek
Single Sector Read
Single Sector Write
Read CRC
Single Sector Write with Delete Data Mark
Multi Sector Write
Multi Sector Read
Free Format Write
Free Format Read
123
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
1
1
1
0
0
1
1
1
1
1
1
0
0
1
0
1
0
1
0
1
1
0
1
0
1
1
0
0
1
1
0
0
1
1
Hex
Code
2
3
4
5
6
7
I
D
C
B
A
HD6843S, HD68A43S
•
Seek Track Zero (STZ)
•
The STZ command causes the R/W head to be released from
the surface of the disk (HLD is reset) and positioned above
track 00. The FDC issues step pulses on the STP output until
the TRZ input becomes a "High" level or until 82 pulses have
been sent to the drive. When the TRZ input becomes "High",
the step pulses are inhibited on the STP output but the FDC
remains busy until ail 82 have been generated internally.
If the TRZ input remains "Low" (logic "0") after all 82
pulses have been generated, the seek error flag (STRB bit 4) is
set.
After all 82 pulses have been generated, the head is loaded
(HLD becomes a "High"). After the settling time specified in
the SUR has expired, the Seek Command End flag is set (ISR
bit 1), Busy STRA7 is reset, CTAR and GCR are cleared. The
head remains in contact with the disk. A command such as
RCR (Read CRC) may be issued following a STZ if the head
must be released.
•
t}
Thil Operetion II Conducted in Perellel
with ell Other Operationl.
Seek (SEK)
The SEK command is used to position the R/W head over the
track on which a Read/Write operation is to be performed. The
contents of the GCR are taken as the destination address and
the content of the CTAR is the source address; therefore, the
number of pulses (N) on the STP output are given by:
N = I(CTAR) - (GCR)I
HDR is a "High" for (GCR) > (CTAR) otherwise it is a "Low".
When a SEK command is issued, Busy is set, the head is
raised from the disk, HDR is set as described above, and N
number of pulses appear on the STP output. After the last step
pulse is used, the head is placed in contact with the disk. Once
the head settling time has expired, the Seek Command End flag
(ISR bit 1) is set, Busy is reset, and the contents of the GCR are
transferred to the CTAR.
•
Address Search Operation
The flow chart of Figure 20 shows the operation of
address search operation.
Set Treck NOI Equal
'r--t--"'IiiO£~5~~~
Set RWCE IISR Bit 01
SloreICMR
TreckBil51
AdG-...
InDIR
SINGLE SECTOR READ/WRITE COMMANDS
The single sector Read/Write commands (SSR, RCR, SSW,
and SWD) are used to Read/Write data from a single 128 byte
sector on the disk. As shown in Figure 19 these types of
instructions can be divided into two sections. The first section,
which is common to all instructions, is the address search
operation, while the second sec:tion is unique to the requirements of each instruction.
Figure 20 Operational Flow of the Address Search Sequenc
•
Single Sector Read (SSR)
The single sector read command follows the address searc.
procedure as defined in the previous flowchart. If the search i
successful, status sense request is set and the operatio
continues as described by the flowchart of Figure 21 .
•
Read CRC (RCR)
The RCR command is used to verify that correct data wa
written on a disk. The operation is the same as for the SS]
Figure 19 Basic Single Sector Command Flow Chart
124
HD6843S, HD68A43S
Set Data Address
Mark Undetected
(STAB Bit2)
Set RWCE
IISR Bit 0)
Set CRC Error
(STRB Bit 1)
Set RWCE
IISR Bit(l)
Figure 21 Operational Flow of the SSR Command
125
HDI843S, HD68A43S
• Single Sector Write with Delete Data Mark (SWD)
The operation flow of SWD is exactly like that of SSW. F<
SWO, the data pattern of the Data Address Mark becomes F
instead of FB. The clock pattern remains C7.
command with the exception that the data transfer request
(STRA bit 0) is not set. The Status Sense Request interrupt can
be disabled by using the DMA flag of CMR.
• Single Sector Write (SSW)
Single sector write is used to write 128 bytes of data on the
disk. After the command is issued, the address search is
performed. The remainder of the instruction's operation is
shown.in Figure 22.
• Multi-Sector Commands (MSRIMSW)
MSR is used for sequential reading of one or more sector
If S sectors are to be read, S - 1 must be written into.the GC
before the command is issued.
Write the
Data
AddreaMark
(Cloc:k -C7,
Oate. FB)
Figure 22 Operational Flow of the SSW Command
126
HD6843S, HD68A43S
•
The basic operation for the MSR and MSW is the same as
that for the SSR and SSW respectively. The basic operation
begins with an address search operation, which is followed by a
single sector read or write operation. This completes the
operation on the first sector. The SAR is incremented, the GCR
is decremented, and if no overflow is detected from the GCR
(i.e., GCR become negative) the sequence is repeated until S
number of sectors are read or written.
The completion of an MSR or MSW is like that of an SSR or
SSW command. First RWCE is set and Busy is reset, after the
settling time has expired, the head is released.
If a delete data mark is detected during an MSR command,
STRA bit 1 (Delete Data Mark Detected) remains set throughout the commands operation.
When a multi-sector instruction is issued, the sum of the SAR
and GCR must be less than 27. If SAR + GCR > 26, an address
error (STRB bit 3 set) will occur after the contents of SAR
becomes greater than 26.
•
•
When one of the four write macro commands (SSW, SWD,
MSW, and FFW) is executed, the information contained in the
DOR is loaded into the DOSR, and is shifted out on the WDT
line using a double frequency (FM) format.
•
Data Input Register (DIR); Hex address 0, read only
One of the three read macro commands (SSR, MSR, FFR)
executed, will cause the information on the RDT input to be
clocked into the DISR. When 8 clock pulses have occurred, the
8 bits of information in the DISR are transferred to the DIR
where it can be read by the bus interface.
Free Format Write (FFW)
The FFW has two modes of operation which are selected by
FWF (Free Format Write Flag) which is dat,a bit 4 of the CMR.
When FWF = "0", the data bits of the DOR are written directly to the disk without first writing the preamble, address
mark, etc. The contents of the DOR are FM modulated with a
clock pattern of all ones.
If FWF = "1" the odd bits of the OOR are used as clock bits
and even bits are used for data bits. In this mode, the DOSR
clock is twice a normal write operation and one byte of DOR is
one nibble (four bits of data) on the disk.
The two modes of the FFW command allow formatting a
disk with either the IBM3470 format or a user defined format.
After the FFW command is loaded into the CMR, WGT
becomes a "High" level, the contents of DOR are transferred to
the DOSR, data transfer request (STRA bit 0) is set, and the
serial bit pattern is shifted out on the WDT line. Therefore, OOR
must be loaded before the FFW command is issued. Data from
the DOR is continually transferred to the DOSR and 'shifted out
on WDT until the CMR has been written with an all zero
pattern. When CMR becomes zero, WGT becomes a "Low"
level, but RWCE is not set and the R/W head is left in contact
with the disk.
REGISTER DEFINITIONS
• Current Track Address (CTAR); Hex address 1 , read/write
Bit 7
I Bit 6 I Bit 5 I Bit 4 I Bit 31 Bit 2 TBit 1 TBit a
Track Address of Current Head position
The address of the track over which the R/W head is
currently positioned is contained in the CTAR. At the end of a
SEK command, the contents of the GCR are transferred to the
CTAR. CT AR is cleared at the completion of a STZ command.
CTAR is a read/write register so that the head position can be
updated when several drives are connected to one FDC. Bit 7 is
read as a "0".
• Command Register (CMR); Hex address 2, write only
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3*1 Bit 2* 1 Bit 1 * 1 Bit 0*
Function
Interrupt
Mask
ISR3
Interrupt
Mask
DMA
Flag
FWF
Macro Command
*Bit 0 - 3 are clt:ared by RES.
The commands that control the FDC are loaded into the
lower four bits of the CMR. Information that controls the data
transfer mode and interrupt conditions are loaded into bits four
through seven.
Free Format Read (FFR)
FFR is used to btput all data (including Address marks) from
a disk. Once the FFR command is set into the CMR, the head is
loaded and after the settling time has expired the serial data
from the FDC is brought into the DISR. After 8 bits have
accumulated, it is transferred to the DIR and Data Transfer
Request (STRA bit 0) is set.
This operation continues until a zero pattern is stored in the
CMR, terminating the FFR command. As in the case of the
FFW command, RWCE is not set and the head remains in
contact with the disk.
The first data that enters the DISR is not necessarily the first
bit of a data word since the head may be lowered at any place
on the disk. To prevent the FDC from remaining unsynchronized to the data, the FFR command will synchronize
to an ID address mark (FE) or a Data Address mark (FB or F8)
or an Index Address Mark (FC).
Bit Q-Bit 3: Macro Command
The Macro Command to be executed by the FDC is written
to bits 0--3.
Bit 4: Free Format Write Flag (FWF)
If a Free Format Write command is issued, the state of bit 4
of the CMR determines what clock source will be used. The
FWF is defined in the FFW (Free Format Write) command
explanation.
Bit 5: DMA Flag
If bit 5 is a "1" the FDC is in the DMA mode. -Bit 5 being a
"1" inhibits setting of Status Sense Request (lSR bit 2) thereby
preventing its associated interrupt. A logic" 1" DMA flag also
enables the TxRQ output allowing it to request DMA transfers
when the Data Transfer Request flag (STRA bit 0) is set.
A logic "0" DMA flag indicates the program controlled I/O
(PC I/O) mode.
127
~
"Command End
Command Set
HLO
HOR
LCT
----
GCR, CTAR; ch!ar
I
-----
----,
Settling
time
-----
-----,
-----
STP
--
......
I\)
co
TRZ
ROY
STRA7
(Busy)
1
-min,Ons
2
3
z
l
321-15
.~seek time
!'1•
n-1
'1
I•
n~l
:\
Seek time
c
.
G)
CIt
82
w
!IJ
H : i n , 21-15
z
c
I
G)
"'"
~
,
---'
II
ISR'
(Seek Command End)
• STP output is masked when TRZ becomes "High", But if TRZ falls to "Low" again before 82 pulse outputs are all provided,
STP output become available again from that time point,
•• When ROY i,; "Low" with Command Set, the execution is postponed until ROY becomes "High",
Figure 23 Timing Sequence of STZ Command
t
en
,.
GCR Set
""
I
Command End
Command Set
~~eek--r--Se~tling_
time
time
CTAR Determined
HLD
---_\
~
I
---HDR
LCT
---- ==~~~:-_t(
--- -------
--- -------1.
min.L
Ons
-"
I\)
STP
1
CD
*
RDY
STRA7
(Busy)
"1"
Seek---l
time
2
l}- ~
-r
"High" GCRL 44
"Low" GCRS; 43
f----min.32I.1s
ISRl
~
Co)
!IJ
n
J:
C
G)
;
,
II
"-Time for calculation
of relative address
Max lms.
* When RDY is "Low" with Command Set, the execution is postponed until RDY becomes "High".
Figure 24 Timing Sequence of SEK Command
J:
C
G)
C»
(Difference between
GCR and CTAR)
-IJ
(Seek Co
mand End)
"High"; toward the hub
"Low" ; away from the hub
\
~
Co)
tn
LTARSAR
Set Set
===
......
Co)
o
~\
A
=t.-S".';n.~
Command End
(Address Error)
r---se~ling_1
tIme
tIme
~~,...J
lOX
STRA7
(Busy)
"
I
Command Set
HLO
Next Command Set
Start Address Search
~Y...I
J
"-
ISRO
(R/We )mmand End)
ROT Va lid
Unless a new command
is issued during the
settling time after
Command End, HLO
becomes" Low",
Unless the address is detected
before the c k revolves three
times after I Immand Set, it
results in Cc mmand End with
Address Err
Il: 0=1
STF 3 =1
:::t
C
G)
:
Co)
!R
:::t
C
'(
\
* If HLO has already been "High" when the command is set, the FOC starts the address search immediately,
When ROY is "Low" with Command Set, the FOC waits for the execution until ROY becomes "High",
Figure 25 Timing Sequence of SSR, SSW, RCR, SWO, MSR, MSW Command
(Relation with HLO and lOX)
E
en
Co)
ID
I-
Data from
the diskette
FF
00
00
00
00
00
00
IDAM Track
00
Sector
r--------------.--
I
---~----,
---
\~~
'\
CD
-----,----,
---.---
-I
----.--
I
Reset
1 \ \
® ------------------------------.J·~~s-;;;--------~:t------ ------
,
Sector
Equal
@
......
c.l
......
FF
_______ _'l.® _______ ____ _
Reset
Track
Equal
CRC I FF
CRC
-,
Check Timing
of Data
IDAM
detection
00
.. I
ID CRC
"0"
@
\
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~-----------
Compare with
LTAR
Compare with
SAR
------
Track
Not Equal
Sector
Not Equal
Command End
~ _:i~ ~~:E.:.r~ ~r_w~t~~rack Not Equal ®
I
ISRO
,
@
@
ISR2 set by address
detection
In the case of Track Not Equal, ® is not set and ,if CRC equals to the one calculated by FDC, STRAS is set.
In the case of Sector Not Equal, c:v is not set and CD & ® are reset to search the next IDAM.
In the case of CRC Error, @ is not set and CD,® & @are reset. (ISRO: Set, STRB1: Set, STRB3: Set)
When CD, ®. @, & @) are all set,ISR2 is Set. These four signals are reset with Command End.
When @ is "1 ", go to the data transfer routine.
Figure 26 Internal Timing Sequence of Address Search Routine
:z:
c
Co)
(R/W Command End)
(1i)
".,
Co)
!b
~
".,
..\
(Sense Request)
00
Q)
I
ISR2
:z:
c
Q)
en
-I
Data from
the diskette
IDCRC
"0"
Read Data
Valid
STRAO (Data
Set Pulse
~
:RC
FF
FF
Data
or
DAM
F~+- I~ PDAM
GAP ----
(Da
N
STRB2
IDA
+==
FF
CRC
FF
I·
STRAl
(DO
" detected)
I
I.
,
'------------ --------------_\
Reset with Co
\
(t
~rf
m ¥R
n n
11
11\
fl
I
n
~
It
~
of RCR,
ated to
nerated
%
oG)
:
Transfer
Coo)
!II
32 bytes
,,------------
undetected)
(R/W
ISR2
(Sense Reque
CRC
Command End with DAM'Undetected
Transfer Error!
ISRO
(CR
127th 128th
Data Data
/
ansfer Request)
I
Error)
I
:ommand End)
STRBl
3rd
Data
I
Read
DIR
STRBO
2nd
Data
~
STRAQ
....
W
1st
Data
%
~----- ------------~-l
r---~l
;-.,---------
M Undetected
Error
~-------------I
Command End with DAM Undetected
~
I.
A
-
I
ISR l'lead
Unless DAM(FB) or DDAM(FS) is detected within 32 bytes after 10 field has been detected,STRB2 is set to end the command.
Figure 27 Data Transfer Timing of SSR, RCR Command
is 'FS'.
"if DAM
o
G)
;
t
(I)
Data
-10-
FF
FF
CRC
Data from
the diskette
-11 bytes
IDCRC
1st
Data
2nd
Data
127th
Data
_1
DOR---.DOSR
Transfer
(,.)
Writing
on DOR
Write Data
~
U
~
,
FF
FF
\
J:
C
G)
CD
~
Co)
!I»
J:
C
G)
Transfer Error
~
~
Co)
en
ISRO
(R/WComman :I End)
_If
CRC
-ru
~tl J1
rutl
It .-J
rr
STRBO
(Data Transfer Error)
ISR2
(Sense Request)
CRC
T
-)
STRAO
(Data Transfer Request)
12Sth
Data
I
6 bytes
WGT
(,.)
00
I
"0"
......
00
DAM*
or
DDAM
Command End
\
A'"
ISR Read
* As Data Address Mark, SSW command writes 'FB' and SWD command writes 'FS',
Figure 28 Data Transfer Timing of SSW, SWD Command
Sector
Co mmandSet
~
FOC
Operation
I
J~
10 I GAP
Addre!;5
Search
I
I
Sector
GAP
Data
101 GAP
Address
Search
Data Transfer
I
1
Data
Sector
~,
10 I GAP 1 Data
Address
Search
Data Transfer
Command End
GAP
I
Data Transfer
J:
I
C
0)
.....
1
GCR- 1
SAR+1
GCR decremen t
SAR increment
Co)
~
·ISRO
(R/W Comma ,rI
\
CO
1
r--------------,------------1_
,----
L
~n"'l
GCR- 1
SAR+1
GCR-1
SAR+1
-- --------- J
c:
(GCR)=O
Address Search and Data Transfer in each sector is the same as those of SSR or SSW command.
When Address Error occurs. it results in Command End. If an error relating to Data Transfer occurs,
Error flag is set. But the command continues to be executed to shift into the next sector.
Figure 29 Timing Sequence of MSR, MSW Command
!b
J:
~-..,.
Command End with Address Error
~
Co)
C
Command End
0)
~
~
Co)
en
Set "00" Command into CMR
Command Set
HLD
Se.ttling
tIme
I
~'~------------------------------------------1
WGT
1st
Data
DOSR
2nd
Data
~
C
m
CO
~
.....
Co)
01
w
DOR -+ DOSR
Transfer
'\.---,.,I\..--...I"--J'----I"--J ' - - - ' ' - - - '
!.n
~
c
m
~
STRAO
(Data Transfer Request)
~
w
en
Writing on
DOR
DOR
1st Data
2nd
Data
• The first one-byte data must be set into DOR before Command Set.
• If H LD has already been "High" when the command is set, WGT becomes "High" immediately.
• When '00' command is set into CMR, an interrupt of Command End is not generated.
Figure 30 Timing Sequence of FFW Command
Command Set
___
~
.
Set "00" oommand 'nto CMR
--------------------+---------
Irl
Settling time
Read Data _ _ _ _ _ _ _ _ _ _ _ _....J
Valid
DSR
%
C
1st
Data
0)
at
~
Co)
.....
(0)
DISR ..... DIR
Transfer
- - - - . - - - - - - - - -......'~'+__I~""'_r__I'_r___''_+__'
m
!P
%
C
0)
;
DIR
~
Co)
tJ)
Reading out
ofDIR
--------------------------~
STRAO
(Data Transfer Request)
If HLD has already been "High" when the command is set, Read operation starts immediately without waiting for the settling time.
When "00" command is set into CMR, an interrupt of Command End is not generated.
Figure 31 Timing Sequence of FFR Command
HD6843S, HD68A43S
Bit 6: ISR31nterrupt Mask
CMR bit 6 (ISR3 Mask) is used to control the operation of
ISR bit 3. A logic "1" in CMR bit 6 inhibits output of STRBOR·Interrupt signal to
If CMR bit 6 (ISR3 Mask) and
CMR bit 7 are "0" STRB-OR·Interrupt signal will be output to
iRQ.
times. For MSR and MSW commands, it is set for each sector.
In the PC I/O mode, an interrupt occurs when Status Sense
Request becomes a logic" 1". In the DMA mode, (DMA flag of
CMR is set) Status Sense Request is unchanged and does not
generate an interrupt when the address ID field has been
verified.
Bit 7: Function Interrupt Mask
When CMR bit 7 is a logic "1" all interrupts are inhibited.
Bit 3: STRB-OR
STRB·OR is an "OR" of all of the bits of Status Register B.
mo.
STRB·OR =STRBO + STRBI + STRB2 + STRB3 +
STRB4 + STRB5 + STRB6 + STRB7
STRB·OR-Interrupt =STRBI + STRB2 + STRB3 +
STRB4 + STRB5 + STRB6 + STRB7
Table 5
Causes
of
Interrupt
Command Register Masks
That Affect Interrupts
CMR7
CMR6
(Function
Interrupt (lSR3 Mask)
Mask)
CMR5
(DMA Flag)
STRB-OR-Interrupt signal causes IRQ. STRB-OR is read
by Read ISR. STRBO (Data Transfer Error) sets ISR Bit 3 but
does not cause Interrupt.
ISRO, ISRl, and ISR2 are cleared when the Interrupt Status
Register is read, but ISR3 is cleared only after Status Register B
has been read except when FI input is "High".
ISRO
(Read write
Command End)
M
X
X
ISR1
(Seek Command
End)
M
X
X
ISR2
(Status Sense
Request)
M
X
M
ISR3
(STRB-ORInterrupt)
M
M
The SUR is not affected by a reset operation; therefore, once
it is initialized, the information remains until power is removed
from the FDC.
X
Bit 0 '" Bit 3: Head Settling Time
The. head settling time is used to generate a delay after the
head is placed in contact with the disk. This allows the head to
stop bouncing before any operations are performed. The delay
is programmed by bits 0-3 and is specified by the equation:
x = No effect
M = Bits that are used as masks
• Interrupt Status Register (lSR); Hex address 2, read only
Bit 71Bit 61Bit 51 Bit 4 Bit 3
Not Used
(Read as "0")
STRB
·OR
Bit 2*
Bit 1*
Bit 0*
Seek
Status
Read Write
Sense Command Command
End
Request
End
=
4096
f
•B
B =Number contained in bits 0-3 of SUR
f =Frequency of ClK input
For IBM3740 compatibility f = 1 MHz and the timing range
is 4.096 ms for a "0001" to 61.44 ms for a "1111". A "0000"
code prevents Settling Time complete from being set and the
FDC must be Reset.
• Cleared by REs
Bit 0: Read Write Command End (RWCE)
When an SSR, RCR, SSW, SWO, MSR or MSW Macro
Command has completed execution, bit 0 becomes set (logic
"1 "). If the function interrupts are enabled (bit 7 of CMR is a
logic "0"), the conclusion of a Macro Command's execution will
cause an interrupt.
Bit 4 '" Bit 7: Track to Track Seek Time
The frequency of STP is detennined by bit 4- bit 7 of SUR
as shown below.
Bit 1: Seek Command End (SCE)
Seek Command End is set on SEK and STZ commands to
indicate the head has been loaded and the settling time specified
in SUR has expired. Since RWCE is not set for the SEK or STZ
command, SCE can be used as an interrupt to signify the SEK
or STZ command has fmished. SCE is not set for any of the
R/W commands.
Bit 2: Status Sense Request
For an SSR, SSW, SWO, MSR, or MSW Command, Status
Sense Request indicates that the specified address ID field has
been detected and verified by a CRC check. This is used as an
early indication that data transfers will occur after 18 more byte
Delay
II------A 1024 _ _ _ _--..11
~3f2f-
ufl~
f
________
~~
A = Number specified in bits 4-7 of SUR.
f = Frequency of elK input.
137
For IBM compatible operation, f is 1 MHz. This results in an
STP pulse width of 32 J.LS and an STP interval of 1.024 ms for a
"0001" to 15.36 ms for a "1111".
HD6843S, HD68A43S
• Status Register A (STRA); Hex address 3, read only
Bit 7*
Busy
*
Bit 5* Bit 4
Bit6
Index
Clear~
Track
Not
Equal
Write
Protect
Bit 3
Track
Zero
Bit 2
Bit 1 *
Drive
Ready
Delete
Data
Mark
Detected
of STRB bit 3) during the address search phase of a non-free
format read/write command.
Bit 0*
Data
Transfer
Request
Bit 7: Busy
When Busy is a logic "1", the FDC is executing a command
and no new commands can be issued. Busy should be confirmed
to be "0" before reading ISR or. STRB as well as issuing a
command.
by RES
• Sector Address Register (SAR); Hex address 4, write only
Bit 0: Data Transfer Request
For a write operation (SSW, SWD, MSW, FFW) the transfer
request bit indicates that the DOR is ready to accept the next
data word to be written on the disk. If data is not written into
the DOR before the last data bit in the DOSR is shifted out to
the WDT line; the data transfer error bit (bit 0 of STRB) will be
set. After a write command has been issued, the first transfer
request occurs simultaneously with the Status Sense Request.
For a write operation, transfer request is reset after the DOR
haS been written from the data bus.
During a read operation (SSR, MSR, FFR) the transfer
request bit signifies data from the DISR has been transferred to
the DIR. The DIR must be read before the DISR is full again or
the data transfer error bit (bit 0 of STRB) will be set. For read
operations, transfer request is reset by a read of the DIR.
Bit 1: Delete Data Mark Detected
A Single Sector Read operation that detects a delete data
code (F8) instead of a general data code (FB) as a Data Address
Mark will set the'Delete Data Mark Detected bit. For the MSR
command, bit 1 is set the first time an "F8" code is found and
remains set throughout the execution of the command. Bit 1 is
reset whenever an SSR, SSW, SWD, MSR, MSW, or RCR
command is issued.
Bit 2: Drive Ready
The Drive Ready bit indicates the state of the Ready input
from the floppy disk drive. If a command is issued with Ready
at logic "0", its execution will be inhibited until Ready becomes
a logic "I". If ready becomes a "0.:' during the execution of a
command the Hard Error Flag (STRB bit 7) is set.
Bit 3: Track Zero
The state of the Track Zero input from the floppy disk drive
is reflected in this bit of STRA. A logic" 1" on the Track Zero
input inhibits step pulses during an STZ command.
Bit 4: Write Protect
The Write Protect input from the floppy disk drive is
reflected by bit 4 of STRA. A "High" level (logic" 1") on the
WPT input during the execution of any write command results
in a write error (bit 6 of STRB set).
* Cleared by RES
Before a data transfer macro command (SSW, SWD, SSR,
RCR, MSW, MSR) is issued, the address of the sector on which
the operation is to be performed must be written into the SAR.
The address in the sector address byte of an Address ID field of
the disk is compared with the contents of the SAR. During an
MSW or MSR command, the SAR is incremented after each
sector is read or written. When execution is complete, the SAR
contains the address of the last sector on which an operation
was performed plus one.
• Status Register B(STRB); Hex address 4, read only
Bit 7* 'Bit 6*
Hard
Error
Bit 5
Bit 4 *
File
Write Inoper- Seek
Error
Error
able
Bit 3*
Bit 2* Bit 1 *
Sector Data
Address Mark
Unde- Undetected tected
CRC
Error
Bit 0*
Data
Transfer
Error
* Cleared by RES
The bits of the STRB represent possible error conditions that
may occur during execution of macro commands. Whenever
STRB is reset, ISR bit 3 is also reset.
Bit 0: Data Transfer Error
Data Transfer Error indicates an underflow or overflow of
data. If a Write operation is being performed, it signifies that
data was not presented to the DOR before the DOSR became
empty. In this case, the current contents of the DOR are transferred to the DOSR and the write operation continues. The
data transfer error temains set until STRB is read, and the data
transfer request remains set until data is written into the DOR.
The operation of the CRC is unchanged.
For read commands, a data transfer error indicates that data
in the DIR was not read before the next data word from the
disk was transferred to the DIR. The read operation contimH~8
until sufficient data has been read from the disk to satisfy the
requirements of the command (I28 bytes for SSR). The error
indication remains set until STRB is read, and the transfer
request remains set until data is read from the DIR.
Bit 5: Track Not Equal
If the track address read from the address ID field does not
Bit 1: CRC Error
coincide with the address in the LTAR in spite ofCRC matching
the one calculated by FDC, the Track Not Equal bit is set.
A CE.C error occurs when the CRC read from the disk does
not match that calculated by the FDC on the data it reads from
Track Not Equal applies to all non-free format read/write comthe disk. A CRC error can occur in two different situations;
mands, and is reset after -a non-free format read/write comchecking the address ID field, checking the data field.
mand is issued.
If the CRC error occurs during the check of an address ID
Bit 6: Index
. The. state ~f the index input appears in bit 6 .of STRA. !he
field, Sector Address Undetected (STRB bit 3) will also be
mdex mput IS used to count the number of disk revolutIOns
indicated (see Table 6). A CRC error of a data field is indicated
while the FOe is looking for the address ID field (see operation 138 by a CRC Error and no Sector Address Undetected.
HD6843S, HD68A43S
The GCR contains the destination track address for the R/W
head on an SEK Macro Command. The contents of the GCR are
transferred to the CTAR at the end of the SEK Command. For
multi-sector read or write operations (MSR, MSW), the GCR
contains the number of sectors to be read minus one. During the
MSR or MSW execution the GCR is decremented after each
sector is read or written_
Bit 2: Data Mark Undetected
If a valid data mark is not detected in the data block of a
sector, it is indicated by a Data Mark Undetected error.
Bit 3: Sector Address Undetected
The Sector Address Undetected bit can be set on two conditions; not finding the sector address and a CRC error on an
address ID field.
If the disk makes three revolutions during an address search
operation and the sector address specified in the sector address
register is not found in any of the address ID fields, a Sector
Address Undetected condition is indicated.
A CRC error that occurs on an address ID field will set bit 3
also_ Table 6 shows how bits 1 and 3 are related.
• CRC Control Register (CCR) ; Hex address 6, write only
Bit 7
CRC Error
(STRB1)
0
0
0
1
No Error
Sector Address not Detected
1
1
0
CRC Error on a Data Field
1
CRC Error on Address 10 Field
Bit 1: Shift CRC
Bit 1 is valid only for the FFW command. After setting, it
takes effect on the next transfer of data from DOR to DOSR
(see Figure 33)_ Setting Shift CRC terminates the CRC
calculation and causes the CRC calculated on all the data
written into DOR up to the setting of bit 1, to be shifted out
the WDT output. The CRC calculation will not include any data
written to DOR after Shift CRe is set.
Bit 5: File Inoperable
The state of the File Inoperable input appears in bit 5. If the
File Inoperable input is a "High" level, a pulse of width equals
to Enable pulse width PWEL is issued on the FIR output when
STRB is read. FI is not latched but the input is gated to the bus
when STRB is read.
•
Not
Used
General Count Register (GCR); Hex address 5, write only
61
Bit
51
Bit
41
Bit 31 Bit 2 1 Bit 1 1 Bit 0
Bit
Bit
61 Bit 51 Bit 41 Bit 3 I Bit 2 I Bit 1 1 Bit 0
7 Bit Logical Track Address
When a read or write macro command (SSW, SWD, SSR,
RCR, MSW, MSR) is issued, the address of the track on which
the operation is to be performed must be written into the
LTAR. The address in the track address byte of an Address ID
field of the disk is compared with the contents of the LTAR.
The contents of LTAR are not affected by the execution of any
of the commands.
Bit 7: Hard Error
If the Ready input becomes a "Low" level during the operation of a command (Busy is set), a Hard Error indication will
result.
7 Bit Count for Track Number on SE K Command
and Sector Count for MSR or MSW Command
LTAR (Logical Track Address); Hex address 7, write only
Bit 7
Bit 6: Write Error
If the WPT input becomes a "High" level (logic "1") during
the execution of a write command the Write Error bit is set.
Not
Used
Bit 1 Bit 0
Shift CRC
CRC Enable
Bit 0: CRC Enable
During an FFW command, CRC Enable is set by software
and CRC generation takes effect on the next transfer of data
from DOR to DOSR (see figure 32). The CRC generation
continues until Shift CRC (CCR bit 1) is set.
For an FFR command, CRC Enable is set by software and
CRC generation takes effect on the next data read from DIR.
The calculation continues for all data bytes read from DIR until
CRC Enable is reset. The bytes read previous to resetting CRC
Enable are considered the CRC information bytes and the CRC
check is made against them.
Condition
Bit 7
51 Bit 41 Bit 3 I Bit 2
The CCR information is used only in the free format
commands; for all other commands this register is masked and
has no function.
Bit 4: Seek Error
An STZ (Seek Track Zero) command that never receives a
track zero indication on the track zero input will result in a
Seek Error (see description of STZ command).
•
Bit
Not Used
Table 6 Relationship of CRC Error and
Sector Address Undetected
Sector
Address
Undetected
(STRB3)
I Bit 61
139
HD6843S, HD68A43S
CRC
Enable
Reset
(CCRO=O)
CRC
Enable
Set
(CCRO=1)
DCK (Data
Clock Input)
Load Signal
from DISR
to DIR
DTR
CRC Enable_...-oif-_ _......"
(CCRO)
CAC
valid
DISR
DIR
CRC Calculation includes Data Byte 1 through Data Byte n.
Figure 32 CCR Control Register Timing for an FFR Command (READ)
Shift
CCR Set
(CCRO=1)
Write (CCR1=1)
Byte n
to DOR
(Data n)
CCR Enable Set
(CCRO=1)
(CCR1=O)
Shift
Clock
Load signal
from DOR
to DOSR
STRAO
(DTR)
CCRO
(CRC Enable)
CCR1
(Shift CRC)
CRCvaiid
DOR
DOSR
WDT
Output
Data 2
The CRC Calculation includes Data Byte 1 through Data Byte n-1.
Figure 33 CCR Control Register Timing for an FFW Command (WRITE)
140
Write Byte
n+2 to DOR
(Data n+2)
CCR Set
(CCRO=O)
(CCR1=O)
HD6843S, HD68A43S
Table 7 Programming Reference Data
Table 7 is a summary of the information in the data sheet and can be used as a reference when programming the HD6843S
Registers
CMR
Hex
Address
2
R/W
Mode
WO
Data Bits
Bit 7
Function
Interrupt
Mask
Bit 7
ISR
STRA
STRB
2
3
4
Bit6
ISR3
Interrupt
Mask
I
Bit6
Bit 4
DMA
Flag
FWF
Bit 5
I
Bit 7 *
Bit6
Busy
Index
RD
Bit 7 *
Bit 6 *
Hard
Error
Write
Error
Bit 5 *
Track
Not
Equal
Bit 5
File
Inoperable
Bit 3 *
141
Bit 2 *
STRB
-OR
Bit 4
Bit 3
Bit2
Write
Protect
Track
Zero
Drive
Ready
Bit4 *
Seek
Error
I
Bit 1 *
I
Bit 0 *
Macro Command
Bit 3
Bit3 *
Bit2 *
Sector
Data
Address
Mark
Undetected Undetected
* Cleared by RES
RO - Read Only
WO - Write Only
R/W - Read/Write
I
Bit 2 *
Status
Sense
Request
Bit4
Not Used
RO
RO
I
Bit 5
Bit 1 *
Bit 0 *
Read Write
Seek
Command Command
End
End
Bit 1 *
Delete
Data Mark
Detected
Bit 0 *
Data
Transfer
Request
Bit 1 *
Bit 0 *
CRC
Error
Data
Transfer
Error
HD6843S, HD68A43S
MACRO COMMANDS
Hex Code
Instruction
Hex Code
Instruction
2
3
STZ
SEK
SSR
SSW
RCR
SWD
A
FFR
FFW
MSR
MSW
4
5
6
7
B
C
D
Table 8 Error Condition, Command Execution, Interrupt, and Head Control
Flag
Set Condition
Track Not
Equal
STRA5
Track information of I D field
is not equal to the content of
LTAR.
Data
Transfer
Error
STRBO
Overrun or underflow during
the data transfer
Reading of STR B
SSR, MSR, SSW,
SWD, MSW, FFR
FFW
Read/Write command continues to be executed.
CRC
Error
STRB1
CRC Error on ID field or Date
field
Reading of STRB
SSR, RCR, MSR,
SSW, SWD, MSW
(FFR)
The execution of a command Request
is interrupted and R/W
(lSRO,
Command End USRO) is set. ISR3)
Unchanged"
Data Mark
Undetected
STRB2
DAM or DDAM is undetected
within 32 bytes after ID field
has been detected.
Reading of STRB
SSR, RCR, MSR
The execution of a command Request
is interrupted and R/W
(lSRO,
Command End (lSRO) is set. ISR3)
Unchanged··
Sector
Address
Undetected
STRB3
(1) Sector Address of ID
field is not equal to the
content of SAR.
(2) CRC Error on ID field
Reading of STRB
SSR, RCR, MSR
after Busy (STRA7)
SSW, SWD, MSW
is reset.
The execution of a command Request
is interrupted and R/W
((SRO,
Command End ((SRO) is set. ISR3)
Unchanged
(Head remains
loaded after
settling time
has expired.)
Seek Error
STRB4
TRZ signal semains "Low" level
though eighty-two STP pulse
outputs are prcvided in STZ
command.
Reading of STRB
STZ
The execution of a command
Request
is interrupted and Seek
Command End (lSR1) is set. (lSR1,
ISR3)
Unchanged
STRB5
A "High" level input of FI
terminal is reflected.
FI signal of the
FDD is reset when
"High" pulse output is provided by
reading of STRB
atFI="1".
All commands
The execution of a command
is interrupted. If it is a
Read/Write command, ISRO
is set. If it is a seek command,
ISR1 is set.
Reading of STRB
STRB6
Write operation (WGT="High")
is performed when the input of
WPT terminal is "High" level.
SSW, SWD, MSW
FFW
The execution of a command Request
is interrupted and R/W
((SRO,
Command End ((SRO) is set. ISR3)
All commands
The execution of a command
is interrupted. If it is a Read/
Write command, ISRO is set.
If it is a seek command, ISR1
is set.
Error
File
Inoperable
Write
Error
Reset Condition
Command
Issuing of SSR,RCR,
MSR, SSW, SWD or SSR,RCR,MSR
SSW, SWD, MSW
MSW Command
Command Execution
Interrupt Head Control
The execution of a command
Request
is interrupted and R/W
(lSRO)
Command End (lSRO) is set.
Unchanged**
No
Unchanged**
interrupt
Unload the
Request
head imediatel
((SRO or (HLD="Low")
ISR1,
SetWGT to
ISR3)
"Low"
Unload the
head imediatel y
(HLD="Low"
Set WGTto
"Low"
-
Hard Error
STRB7
Not Ready
during the
idling
STRA2
RDY input signal becomes
"Low" level during the execution of a command (Busy="1".)
-
Reading of STRB
-
-
* These errors except STRB5 and STRA2 are reset by RES inputs.
** Head is unloaded if the new command is not issued during the settling time after ReadlWrite command ends.
142
-
--_..
_._-
Unload the
Request head imediatel y
(lSRO or (HLD="Low")
ISR1,
Set WGT to
ISR3)
" Low"
Unload the
No
head imediatel y
interrupt (HLD="Low")
HDS844P,HDS8A44P
DMAC {Direct Memory Access Controller}
The HD6844P Direct Memory Access Controller (DMAC)
performs the function of transferring data directly between
memory and peripheral device controllers. It controls the
address and data buses in place of the MPU in bus organized
systems such as the HMCS6800 Microprocessor System.
The bus interface of the HD6844P includes select, read/
write, interrupt, transfer request/grant, and bus interface logic
to allow the data transfer over an 8-bit bidirectional data bus.
The functional configuration of the DMAC is programmed via
the data bus. The internal structure provides for control and
handling of four individual channels, each of which is separately
configured. Programmable control registers provide control for
the transfer location and length, individual channel control and
transfer mode configuration, priority of servicing, data chaining,
and interrupt control. Status and control lines provide control
to the peripheral controllers.
The mode of transfer for each channel can be programmed as
cycle-stealing or a burst transfer mode.
Typical applications would be with the Floppy Disk Controller (FDC), etc .•
HD6844P, HD68A44P
• FEATURES
• Four DMA Channels, Each Having a 16-Bit Address
Register and a 16-Bit Byte Count Register
• 1 M Byte/Sec (HD6844P), 1.5 M Byte/Sec (HD68A44P)
Maximum Data Transfer Rate
(DP·40)
• Selection of Fixed or Rotating Priority Service Control
• Separate Control Bits for Each Channel
• PIN ARRANGEMENT
• Data Chain Function
• Address Increment or Decrement Update
• Programmable Interrupts and DMA End to Peripheral
Controllers
•
DGRNT
i5'RciT
DRQH
Compatible with MC6844
• BLOCK DIAGRAM
T~Ra,
T~RQ,
Address/Control and Interrupt
D.
0,
0,
D.
0,
0,
0,
(Top View)
Data
Bus
143
HD6844P, HD68A44P - - - - - - - - - - - - - - • ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
Supply Voltage
Vee *
-0.3 - +7.0
V
Input Voltage
Yin *
-0.3 -+7.0
Operating Temperature
Topr
-20 -+75
°c
Storage Temperature
TS1g,
-55-+150
°c
Item
• With respect to
(NOTE)
V
Vss (SYSTEM GND)
Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be
under recommended operating conditions. If these conditions are exceeded, it could affect
reliability of LSI.
• RECOMMENDED OPERATING CONDITIONS
Item
Symbol
min
typ
max
Unit
Power Supply Voltage
Vee *
V 1L *
4.75
5
5.25
V
-0.3
-
0.8
V
V 1H *
2.0
-
V
Topr
-20
25
Vee
75
Input Voltage
Operating Temperature
• With respect to
°c
Vss (SYSTEM GND)
• ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (Vcc=SV±5%, Vss=OV, Ta=-20-+7SoC, unless otherwise noted.)
min
typ*
max
Unit
Input "High" Voltage
V 1H
2.0
-
Input "Low" Voltage
V 1L
-0.3
-
Vee
0.8
V
Symbol
Item
Test Condition
V
I nput Leakage Current
TxRQo-3, ~2 OMA,
RES,OGRNT
lin
Vin=Q-S.2SV
-
-
2.S
IJA
Three-State (off state)
Leakage Current
Ao-A lS , 0 0 -0 7 , R/W
I TS1
V ln =0.4-2.4V
-10
-
10
IJA
IOH=-205IJA
2.4
-
2.4
-
-
IOH=-1451JA
IOH=-10{)IJA
2.4
-
VOL
IOL =1.6mA
-
less
Vin::!(JV, Fig. 10
0 0 -0 7
Output "High" Voltage
A o-A 15 , R/W
V OH
All Other Outputs
Output "Low" Voltage
Source Current
CS/TxAKB
Po
Power Dissipation
~20MA
Input Capacitance
0 0 -0 7 , CS, Ao-~,
R/W
TvC"_
_
''''''~U'''''''''3,
Cin
cce
Vin=OV, Ta=25°C
f=1.0MHz
..... ..."
OGRNT
Output Capacitance
Cout
Vin=OV, T.";'25°C, f=1MHz
• V ee =5.0V, T.=25"c
144
-
V
-
-
0.4
V
-
10
16
rnA
500
1000
mW
-
20
-
-
12.5
-
-
10
-
-
12
pF
pF
HD6844P, HD68A44P - - - - - - - - - - - - - - • AC CHARACTERISTICS (Load Condition Fig. 9)
1.
CLOCK TIMING
Item
lP2 DMA Cycle Time
lP2DMA Pulse Width
I
"High" Level
"Low" Level
lP2DMA Rise and Fall Time
2.
Symbol
Test Condition
1'.cy c
PWI/>H
Fig. 2
Fig. 2
HD6844P
min
HD68A44P
min
typ
max
Unit
typ
max
1,000
-
-
-
ns
-
-
666
450
280
-
ns
25
ns
PWI/>L
Fig. 2
400
-
-
230
-
1(pr,\pt
Fig. 2
-
-
25
-
-
ns
DMA TIMING (Load Condition Fig. 9)
Item
Symbol
TxROSetup Time
HD6844P
HD68A44P
min
typ
max
min
typ
t TOS1
120
-
-
120
-
-
lP2DMA Falling
Edge
t TOS2
210
-
-
210
-
-
t TOH1
20
-
-
10
-
-
tTOH2
20
-
-
10
-
-
155
-
-
125
-
-
10
10
-
-
-
-
270
-
-
180
30
-
-
20
-
-
35
35
-
-
Rising
Edge
lP2 DMA Falling
Edge
Unit
max
lP2DMA Rising
Edge
lP2 DMA
TxRO Hold Time
Test Condition
ns
Fig. 3
ns
DGRNT Setup Time
DGRNT
tOGS
DGRNT Hold Time
DGRNT
tOGH
Address Output
Delay Time
Ao-A 1S , R/W,
TxSTB
tAD
Fig. 6
Address Output
Hold Time
tAHO
Fig. 6
TxSTB
Address Three-State
Delay Time
Ao-A lS , R/W
tATSO
Fig. 7
-
-
270
-
-
270
Address Three-State
Recovery Time
Ao-A 1S , R/W
t ATSR
Fig. 7
-
-
270
-
-
270
ns
Delay Time
DROH,DROT
tooo
Fig. 5
-
-
375
-
-
250
ns
lP2DMA Rising
Edge
tTK01
Fig. 5
-
-
400
-
-
310
DG RNT Rising
Edge
tTK02
Fig. 8
-
-
190
-
-
160
lP2DMA Falling
Edge
tOE01
Fig.6
-
-
300
-
-
250
DGRNT Rising
Edge
tO Eo2
Fig. 8
-
-
190
-
-
160
Ao-A 1S , R/W
TxAK Delay Time
I RO/DEND Delay
Time
3.
Fig. 4
ns
ns
ns
ns
ns
ns
BUS TIMING
1) READ TIMING
Symbol
Item
Address Setup Time
Ao-~,R/W,CS
t AS
Address Input Hold
Time
Data Delay Time
A o-A 4 , R/w,CS
tAHI
D o-D 7
tOOR
Data Access Time
Do -D 7
tACC
Data Output Hold
Time
D o-D 7
tOHR
T-est Condition
Fig. 2
145
min
HD68A44P
HD6844P
typ max
min
typ
max
140
-
10
-
-
Unit
140
-
-
10
-
-
-
-
320
-
ns
-
-
220
460
360
ns
10
-
-
10
-
-
ns
I
ns
I
ns
HD6844P, HD68A44P - - - - - - - - - - - - - - 2) WRITE TIMING
Item
Symbol
Ao-~,R/W,~
tAS
min
140
tAHI
10
Address Setup Time
Address Input Hold
Time
Ao-A4,R/W,CS
Data Setup Time
0 0 -0 7
tosw
Data Input Hold
Time
0 0 -0 7
tOHW
csrrxAKB
Fig. 2
H068A44P
typ max
-
195
-
10
-
min
140
H06844P
typ
max
-
-
ns
Unit
-
10
-
-
ns
-
80
-
ns
-
10
-
-
ns
2 ----t--,r"'+I
00
28
01
27
O2
26
03
25
04
24
Os
23
06
22
07
21
32 TxRClo
OGRNT 38
Request,
Grant,
Timing
39
Control
q,2 0MA
Test Condition
40
~
I·
Transfer
Requestl
Acknow·
ledge
31
TxRQ.
30
TxR~
29 TxRQ 3
35 TxAKA
~34 Tx5TB
1~·--v-s-s-=-p-in-1------""
~
Voo=Pin20
Figure 1 Expanded Block Diagram
146
HD6844P, HD68A44P - - - - - - - - - - - - - - -
~-------------------tcyc~------------------~
r------ PW~H --------+t~f r--------PWc/>L ------~
!/>lOMA
2.0V
2.0V
Ao-A" (Input)
R/W (Input)
CS (Input)
tOOR
tOHR
~------tACC------~
2.4V
DO -0, (Output)
(Read Operation)
OAV
DO -0, (Input) _
(Write Operation)
Figure 2 ReadlWrite Sequence
!/>2 0MA
Figure 3 Timing of TxRQ Input
147
HD6844P, HD68A44P - - - - - - - - - - - - - - Set Up Timing
~ __________ J2.0V
'0:.-1
---------- ---------
1/1 2 DMA
2.0V
DGRNT
Hold Timing
DGRNT
Figure 4 Timing of DGRNT Input
toaD
2.4V
O.4V
2.4V
TxAKA
CslTxAKB (Output)
O.4V
Figure 5 Timing of DROH, DROT, TxAK Outputs
148
HD6844P, HD68A44P - - - - - - - - - - - - - - -
4>2DMA
2.4V
A,-A~5 (Output)
R W (uutput)
iXSTB
x
O.4V
t DED
2.4V
O.4V
-------------------
--------------------------
Figure 6 Timing of Address and IRQ/DEND Outputs
Recovery Time of Address Three-state
4>2 DMA (or DGRNTI
2.4V
O.4V
Delay Time of Address Three-state
Ao-A,s
R/W
tAHO
Figure 7 Timing of Address Three-state
149
HD6844P, HD68A44P - - - - - - - - - - - - - - -
DGRNT
CS/TxAKB (Output)
0.4V
.OE021 24V
/1 .
-IRQ/DEND
--------------------~
Figure 8 Timing of Synchronous OGRNT Output
5.0V
2.4kn
Test terminal
0 0 -0,
......-",--~
Test terminal o---~-
Ao -A 15 • R/W
CS/TxAKB
All other outputs
01
C
0 1 -0 4
:
C
130 pF
90pF
50 pF
30pF
1S2074(8)
Figure 9 load Circuit
r-- ----- --- ------------------,
,
HD6844P
I
Vee
~~ON
TxAKBoutput
I
I
~s
•
~
'" 1-
I
I
,I
,I
,
"0"
•
OFF
D.C. Ammeter
Vss
TxAK ENABLE
,
I,
Vss
CSinput
I
I ____________ .... _____________ JI
L
Figure 10 Source Current Measurement Circuit for CS/TxAKB Terminal
150
R
11 kil
16 kil
24kil
24 k!2
HD6844P, HD68A44P - - - - - - - - - - - - - - • DEVICE OPERATION
The DMAC has fifteen addressable registers, eight of them
are sixteen bits in length. Each channel has a separate Address
Register and a Byte Count Register, each of which is sixteen
bits. There are also four Channel Control Registers. The three
General Control Registers common to all four channels are the
Priority Control Register, the Interrupt Control Register, and
the Data Chain Register.
To prepare a channel for DMA, the Address Registers must
be loaded with the starting memory address and the Byte Count
Register loaded with the number of bytes to be transferred. The
bits in the Channel Control Register establish the direction of
the transfer, the mode, and the address increment or decrement
after each cycle. Each channel can be set for one of three
transfer modes: Three-State Control (TSC) Steal, Halt Steal, or
Halt Burst. Two read-only status bits in the Channel Control
Register indicate when the channel is busy transferring data and
when the DMA transfer is completed.
The Priority Control Register enables the transfer requests
from the peripheral controllers and establishes either a fIxed
priority or rotating priority scheme of servicing these requests.
When the DMA transfer for a channel is complete (the Byte
Count Register is zero), a DMA End signal is directed to the
peripheral controller and an IRQ goes to the MPU. Enabling of
these interrupts is done in the interrupt Control Register. The
IRQ flag bit is read from this register.
Chaining of data transfers is controlled by the Data Chain
Register. When enabled, the contents of the Address and Byte
Count Registers for channel #3 are put into the registers of the
channel selected for chaining when its Byte Count Register
becomes zero. This allows for repetitively reading or writing a
block of memory.
During the DMA mode, the DMAC controls the address bus
and data bus for the system as well as providing the R/W
line and a signal to be used as VMA. When a peripheral
device controller desires a DMA transfer, it is requested by a
Transfer Request. Assuming this request is enabled and meets
the test of highest priority, the DMAC will issue a DMA
Request. When the DMAC receives the DMA Grant, it gives a
Transfer Acknowledge to the peripheral device controller, at
which time the data is transferred. When the channel's Byte
Count Register equals zero, the transfer is complete and a DMA
tma is given to the peripheral device controller, and an IRQ is
given to the MPU.
• Initialization
During a power-on sequence, the DMAC is reset via the RES
input. All registers, with the exception of the Address and Byte
Count Registers, are- set to a logic "0" state. This disables all
requests and the Data Chain function while masking all
interrupts. The Address, Byte Count, and Channel Control
Registers must be programmed before the respective transfer
request bit is enabled in the Priority Control Register.
• Transfer Modes
There are three ways in which a DMA transfer may be done.
The one used is determined by the data transfer rate required,
the number of channels attached, and the hardware complexity
allowable. Refer to Figures 11 through 13.
Two of the modes, TSC Steal and Halt Steal, are done by
cycle-stealing from the MPU. The Three-State Con~SC)
Steal mode is initiated by the DMAC bringing the DRQT line
"Low". This line goes to the system clock driver which returns a
"High" on DGRNT on the rising edge of the system 2
DO-D?
f-..-t\
v
~
:~ 3.3kn
t--
IRQ
~
-
VMA
BA
~
R/W
4>.
~
-H~LT
..
r-v
+5V
R/W (RAM)
t--
4>2 MPU
tP.MPU
-
tP2 TTL
CLOCK
GENERATOR LOGIC
~
(CPGJ
~~
:s
'"
CD
S
CI)
DGRNT
1
1"0
is
DRQH
0
"t:l
«
IRQ
Decoder
I
A
Ao-A4
y
As-A. s
5
I
['
11
~
-
t--
1"
H
A
DO-D?
8
TxSTB
TxRQo
II.
0 0 -0 7
---{>
I--
TxAK
~
~
TxRQ
t--
R/W
RES
Vee
HD6843SP
(FDC)
E
r-v ..
"
HD6844P
(DMAC)
A
R/W
CS
I--
r--.
II
~
A
CS/TxAKB
~
K.v
Floppy Disk
Drive
Decoder
VSS
tP2DMA
~
I--
II II I I I I
Figure 17 Example of DMA System Structure (1) (minimum)
158
HD6844P, HD68A44P - - - - - - - - - - -_ _ __
DB
0 0 -0,
..
A
...
4>.
~
1/>2
IRO
BA
I
I
~
VMA
TSC
I
~
"
RIW
.----..
iRO
~
A o-A 15
HD6800
(MPU)
HAL:T
t
~
~
VMA
R/W
AB
~
III
I-
DB
.
HM4681 0
RAM
AB
"
4>MEM
~
MEMORY
HN46B30
ROM
~
etc.
READY
r--
REFRESH REO
REF GRNT
I....-
4>.MPU
I/>MEM
I--
L..--
4>2 MPU
MRDY
t--
RRO
t--
CLOCK G~NERATOR
LOGIC
RGRNT
I--
OGRNT I-- t-~
ORO
t
~
K>
t--
r0o-
i'~
en
~
l!Io- u
--{>or--"cl....-
----. A
Vss
~
:E
DR'QH
6ROT
L:=J
·I~
:s
I
L..-
~
t---
~ ~~
DGRNT
r--
~
r--v
c=J
0
~
trQ:
r-r--
OMAENO
TxAK
R/W
H074155
0
b
TxAK
#0-3
-CJ~:
CS
V
R/W
tP20MA
I
~r
III~
"'
~
- r----
I--
r--
DB
etc.
E
I
* Open Collector
Figure 18 Example of DMA System Structure (2) (maximum)
159
I/O
,
DEVICE
H06843S
CONTROLLER
(FOC)
TxRO
:D-
t--
CS
#2
#3
I
HDS845S,HDS8A45S,
HDS8B45S
CRTC (CRT Controller)
The CRTC is a LSI controller which is designed to provide an
interface for microcomputers to raster scan type CRT displays.
The CRTC belongs to the HMCS6800 LSI Family and has full
compatibility with MPU in both data lines and control lines. Its
primary function is to generate timing signal which is necessary
for raster scan type CRT display according to the specification
programmed by MPU. The CRTC is also designed as a
programmable controller, so applicable to wide·range CRT
display from small low.functioning character display up to
raster type full graphic display as well as large high·functioning
limited graphic display.
•
•
FEATURES
Number of Displayed Characters on the Screen, Vertical
Dot Format of One Character, Horizontal and Vertical
Sync Signal, Display Timing Signal are Programmable
HD6845SP, HD68A45SP, HD68B46SP
• 3.7 MHz High Speed Display Operation
•
•
•
•
•
•
•
Line Buffer-less Refreshing
14-bit Refresh Memory Address Output (16k Words
max. Access)
Programmable Interlace/Non-interlace Scan Mode
Built-in Cursor Control Function
Programmable Cursor Height and its Blink
Built-in Light Pen Detection Function
Paging and Scrolling Capability
•
•
TTL Compatible
Single +5V Power Supply
•
Upward compatible with MC6845
•
•
PIN ARRANGEMENT
Vss
g;-
VSYNC
mg
HSYNC
LPSTS
RA,
RA,
MA,
MA,
MA,
SYSTEM BLOCK DIAGRAM
RA,
RAJ
MA,
I---~-----r------- ~8u1
RA.
MA.
D,
MA,
D,
MA.l
HD6845S
0,
D.
D.
D.
0,
MA.
MAIO 4
MAli 1
G
D,
MA,
MA.
a-
MAlt 1
MA u 17
RS
DIi!lPTMG~
E
R/W
CUDISP~
vccli--..._ _ _ _ _...r- CLK
(Top View)
•
D'''T''''
I
ORDERING INFORMATION
CUOI"
HaVNe
VSYNC
LPSTB
CRTC
~:t
HD6845SP
160
Bus Timing
CRT Display
Timing
1.0 MHz
HD68A45SP
1.5 MHz
HD68B45SP
2.0 MHz
3.7 MHz max.
HD6845S, HD68A45S, HD68845S
•
ABSOLUTE MAXIMUM RATINGS
Item
Supply Voltage
Input Voltage
Operating Temperature
Symbol
Value
Vee *
Vin *
-0.3 - +7.0
V
-0.3 - +7.0
- 20- + 75
V
°c
- 55- +150
°c
Topr
Tstg
Storage Temperature
Unit
•
With respect to Vss (SYSTEM GND)
[NOTE] Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating
conditions. If these conditions are exceeded, it could affect reliability of LSI •
•
RECOMMENDED OPERATING CONDITIONS
Item
Supply Voltage
Input Voltage
I
min
typ
max
Vee *
V 1L *
4.75
5
5.25
V
-0.3
-
0.8
V
Vee
75
V
°c
V 1H *
Topr
Operating Temperature
•
Symbol
2.0.
- 20
25
Unit
With respect to Vss (SYSTEM GND)
ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (Vee = 5V ± 5%, Vss =OV, Ta = -20-+75°C, unless otherwise noted.)
min
typ
max
Unit
Input "High" Voltage
Item
V 1H
2.0
Input "Low" Voltage
V 1L
-0.3
-
Vee
0.8
V
Input Leakage Current
2.5
p.A
- 10
-
10
p.A
2.4
-
-
V
-
-
0.4
V
Symbol
Test Condition
=0 -
5.25V (Except 0 0 -0,)
I in
Vin
Three-State Input Current
(off-state)
ITS1
V in = 0.4 - 2.4V
Vee = 5.25V (0 0 - 0,)
Output "High" Voltage
V OH
Output "Low" Voltage
VOL
Input Capacitance
Cin
Output Capacitance
Power Dissipation
Cout
I LOAD
= -205 p.A (0 0 -
0,)
I LOAD = -100 p.A (Other Outputs)
ILOAD = 1.6 mA
V in =0
Ta = 25°C
f = 1.0 MHz
Vin
Do - 0,
Other Inputs
=OV, Ta = 25°C, f = 1.0 MHz
Po
161
-2.5
V
12.5
pF
10.0
pF
-
-
10.0
pF
-
600
1000
mW
HD6845S, HD68A45S, HD68B45S
•
AC CHARACTERISTICS (Vee = 5V ±5%, Vss
=OV, Ta =-20-+75°C, unless otherwise noted.)
1. TIMING OF CRTC SIGNAL
min
typ
max
Clock Cycle Time
tCycc
270
-
-
ns
Clock "High" Pulse Width
PWCH
130
-
ns
Clock "Low" Pulse Width
PWCL
130
Rise and Fall Time for Clock Input
20
ns
Memory Address Delay Time
tCr, tCf
t MAO
-
-
Raster Address Delay Time
tAAO
DISPTMG Delay Time
tOTo
CUDISP Delay Time
tcoo
Horizontal Sync Delay Time
tHso
Vertical Sync Delay Time
Symbol
Item
Light Pen ~trobe Pulse Width
tvso
PW LPH
Light Pen Strobe
t LPo1
Uncertain Time of Acceptance
t LPo2
Test Condition
-
-
-
Fig. 1
-
-
-
Fig. 2
Unit
ns
160
ns
160
ns
250
ns
250
ns
200
ns
250
ns
60
-
-
ns
-
-
70
ns
-
-
0
ns
2. MPU READ TIMING
Item
Symbol
Test
Condition
HD6845SP
min
HD68A45SP
max
min
typ
max
min
-
-
0.666
-
0.280
-
-
0.22
Enable Cycle Time
ttycE
Enable "High" Pulse Width
PW EH
0.45
Enable "Low" Pulse Width
PWEL
0.40
Enable Rise and Fall Time
Address Set Up Time
tEr, tEf
t AS
Data Delay Time
too A
-
-
Data Hold Time
tH
-
-
-
1.0
-
-
-
140
320
10
10
-
460
-
-
typ
max
min
140
Address Hold Time
tAH
10
10
Data Access Time
tAcc
-
0.280
25
Fig. 3
HD68B45SP
typ
0.5
0.21
-
typ
max
-
-
Unit
(J.s
-
25
fJ.S
ns
-
ns
fJ.S
-
70
-
220
-
-
180
ns
-
10
-
ns
10
-
-
ns
360
-
-
250
ns
HD68A45SP
typ
max
min
25
3. MPU WRITE TIMING
Item
Symbol
Test
Condition
HD6845SP
min
tCYc:C
PW EH
0.45
-
-
0.666
Enable "High" Pulse Width
Enable "Low" Pulse Width
PW EL
0.40
-
-
0.280
Enable Rise and Fall Time
tEr, tEf
25
-
-
25
-
Address Set Up Time
tAs
140
-
-
tosw
195
-
140
Data Set Up Time
80
-
Data Hold Time
tH
10
-
10
-
Address Hold Time
tAH
10
-
10
-
-
Enable Cycle Time
1.0
Fig. 4
-
162
-
0.280
-
-
HD68B45SP
typ
max
Unit
0.5
-
-
(J.s
0.22
-
(J.s
25
ns
70
-
60
-
-
ns
10
-
-
ns
10
-
-
ns
0.21
(J.s
ns
HD6845S, HD68A45S, HD68B45S
2.0V
PW CL
2.0V
O.8V
PWCH
tCr
2.4V
MAo-MAt3----------------------~~----J
2.4V
RAo-RA.
-------------------------+-----'
2.4V
DISPTMG ________________________
~------J
tOTO
2.4V
CUDISP
teDD
tCDD
2.4V
HSYNC
VSYNC
tHSD
tVSD
lPSTB __________
~~~2-.0-V----------P-W--LP-H---------~~------------------------This Figure shows the relation in time between
ClK signal and each output signals. Output
sequence is shown in Figs. 9 - 15.
Figure 1 Time Chart of the CRTC
163
HD6845S, HD68A45S, HD68B45S
elK _ _--J
M+2
M
lPSTB
\_-
-------10-11
_________~~-------J"--~--------------~I~----------~L
2.0V
lPSTB
~
When LPSTB rises in this period,)
Refresh Memorv Address "M+2"
is set into the light pen register.
tLPD1, tLPD2: lPSTB's uncertain time of acceptance.
Figure 2 LPSTB Input Timing & Refresh Memory Address that is set into the light pen register.
~-----------t~e
2.0V
E
-----~~--.l1
cs----..
RIW,RS---....I
00-07-________________
~
Figure 3 Read Sequence
164
HD6845S, HD68A45S, HD68B45S
1-------tc:vcE - - - - - - - . t
E
tEr
tosw
CS
R/W
RS (Address
Register)
2.0V
O.8V
RS
(Control Register)
Figure 4 Write Sequence
Linear address generator generates refresh memory address MAo
-MA I3 to be used for refreshing the screen. By these address
signals, refresh memory is accessed periodically. As 14 refresh
memory address signals are prepared, 16k words max are
accessible. Moreover, the use of start address register enables
paging and scrolling. Light pen detection circuit detects light
pen position on the screen. When light pen strobe signal is
received, light pen register memorizes linear address generated
by linear address generator in order to memorize where light
pen is on the screen. Cursor control circuit controls the position
of cursor, its height, and its blink.
• SYSTEM DESCRIPTION
The CRTC is a LSI which is connected with MPU and CRT
display device to control CRT display. The CRTC consists of
internal register group, horizontal and vertical timing circuits,
linear address generator, cursor control circuit, and light pen
detection circuit. Horizontal and vertical timing circuit generate
RAo ....~, DISPTMG, HSYNC, and VSYNC. RAo ....~ are
raster address signals and used as input signals for Character
Generator. DISPTMG, HSYNC, and VSYNC signals are received
by video control circuit. This horizontal and vertical timing
circuit consists of internal counter and comparator circuit.
165
HD6845S, HD68A45S, HD68B45S
Vee vss
t t
l
Horizontal Displayed
Register
elK -4--..--.1
Horizontal Total
Register
Horizontal Sync
Position Register
HSYNC
Sync
Width Register
Maximum Raster
Address Register
Vertical Displayed
Register
Vertical Total
Register
Vertical Total Adjust
Register
DISPTMG
Vertical Sync
Position Register
Start Address
Register
Cursor Start
Raster Register
CUDISP
Cursor End
Raster Register
Cursor Register
VSYNC
Interlace & Skew
Register
LPSTB . ~~--------------~~~==========~~~~~~
____
MA" -MA"
Figure 5 Internal Block Diagram of the CRTC
166
_.J
HD6845S, HD68A45S, HD68B45S
• FUNCTION OF SIGNAL liNE
• Interface Signals to CRT Display Device
Character Clock (ClK)
The CRTC provides 13 interface signals to MPU and 25
interface signals to CRT display.
CLK is a standard clock input signal which defmes character
timing for the CRTC display operation. This signal is normally
derived from the external high-speed dot timing logic .
• Interface Signals to MPU
Bi-directional Data Bus (0 0 -0,)
Bi-directional data bus(Do-D,) are used for data transfer
between the CRTC and MPU. The data bus outputs are 3-state
buffers and remain in the high-impedance state except when
MPU performs a CRTC read operation.
Horizontal Sync (HSYNC)
HSYNC is an active "High" level signal which provides
horizontal synchronization for display device.
Vertical Sync (VSYNC)
Read/Write (R/W)
R/W signal controls the direction of data transfer between
the CRTC and MPU. When R/W is at "High" level, data of
CRTC is transfered to MPU. When R/W is at "Low" level, data
of MPU is transfered to CRTC.
VSYNC is an active "High" level signal which provides vertical synchronization for display device.
Display Timing (DISPTMG)
DISPrMG is an active "High" level signal which defines the
display period in horizontal and vertical raster scanning. It is
necessary to enable video signal only when DISPTMG is at
"High" level.
Chip Select (CS)
Chip Select signal (CS) is used to address the CRTC. When
CS is at "Low" level, it enables R/W operation to CRTC internal
registers. Normally this signal is derived from decoded address
signal of MPU under the condition that VMA signal of MPU is at
"High" level.
Refresh Memory Address (MA o-MA 13 )
MAo-MA 13 are refresh memory address signals which are
used to access to refresh memory in order to refresh the CRT
screen periodically. These outputs enables 16k words max.
refresh memory access. So, for instance, these are applicable up
to 2000 characters/screen and 8-page system.
Register Select (RS)
Register Select signal (RS) is used to select the address
register and 18 control registers of the CRTC. When RS is at
"Low" level, the address register is selected and when RS is at
"High" level, control registers are selected. This signal is
normally a derivative of the lowest bit (AO) of MPU address bus.
Raster Address (RAo-RA4 )
RAo -RA4 are raster address signals which are used to select
the raster of the character generator or graphic pattern
generator etc.
En~le(E)
Enable signal (E) is used as strobe signal in MPU R/W
operation with the CRTC internal registers. This signal is
normally a derivative of the HMCS6800 System ~2 clock.
Cursor ·Display (CUDISP)
CUDISP is an active "High" level video signal which is used
to display the cursor on the CRT screen. This output is inhibited while DISPI'MG is at "Low" level. Normally this output
is mixed with video signal and provided to the CRT display
device.
Reset (RES)
Reset s.P (RES) is an input signal used to reset the CRTC.
When RES is at "Low" level, it forces the CRTC into the
following status.
1) All the counters in the CRTC are cleared and the device
stops the display operation.
2) All the outputs go down to "Low" level.
3) Control registers in the CRTC are not affected and remain
unchanged.
This signal is. different from other HMCS6800 family LSls in the
following functions and has restrictions for usage.
1) RES signal has capability of reset function only when
LPSTB is at "Low" level.
2) The CRTC starts the display operation immediately after
RES signal goes "High".
light_Pen Strobe (lPSTB)
LPSTB is an active "High" level input signal which accepts
strobe pulse detected by the light pen and control circuit. When
this signal is activated, the refresh memory .address (MAo '"
MA 13 ) which are shown in Fig. 2 are stored in the 14-bit light
pen ,egister. The stored refresh memory address need to be
corrected in software, taking the delay time of the display
device, light pen, and light pen control circuits into account.
167
HD6845S, HD68A45S, HD68B45S
•
REGISTER DESCRIPTION
Table 1 Internal Registers Assignment
Register
Register Name
Program Unit
READ
WR ITE 1--,----,----,------,..---.,----.---.---
#
0
AR
Address Register
0
RO
Horizontal Total •
0
R1
0
R2
X
0
Character
X
0
Horizontal Displayed
Character
X
0
Horizontal Sync·
Position
Character
X
0
X
0
0
R3
Sync Width
Vertical-Raster,
HorizontalCharacter
0
R4
Vertical Total •
Line
X
0
0
R5
Vertical Total Adjust
Raster
X
0
0
R6
Vertical Displayed
Line
X
0
0
R7
Vertical Sync •
Position
Line
X
0
0
RS
Interlace & Skew
X
0
0
R9
Maximum Raster
Address
Raster
X
0
0
R10
Cursor Start Raster
Raster
X
0
0
R11
Cursor End Raster
Raster
X
0
0
R12
Start Address(H)
0
0
0
R13
Start Address( L)
0
0
0
R14
CursorlH)
0
0
0
R15
Cursor (L)
0
0
0
R16
Light Pen(H)
0
X
0
R17
Light Pen( L)
0
X
[NOTE) 1. The Registers marked *: (Written Value) = (Specified Value) - 1
2. Written Value of R9 is mentioned below.
1) Non-interlace Mode }
(Written Value Nr) = (Specified Value) - 1
Interlace Sync Mode
2) Interlace Sync & Video Mode
(Written Value Nr) = (Specified Value) - 2
and C1 specify skew of CUDISP output signal.
3.
DO and D1 specify skew of DISPTMG output signal.
When Sis "1", V specifies video mode. S specifies the Interlace Sync Mode.
4. S specifies the cursor blink. P specifies the cursor blink period.
5. wvO-wv3 specify the pulse width of Vertical Sync Signal.
whO-wh3 specify the pulse width of Horizontal Sync Signal.
6. RO is ordinally programmed to be odd number in interlace mode.
7. 0; Yes, x; No
eo
168
wv3
wv2
wv1
wvO
wh3
wh2
wh1
V
whO
S
HD6845S, HD68A45S, HD68B45S
• Address Register (AR)
Table 2 Pulse Width of Vertical Sync Signal
This is a S-bit register used to select 18 internal control
registers (RQ-R17). Its contents are the address of one of 18
internal control registers. Programming the data from 18 to 31
produces no results. Access to RQ-RI7 requires, first of all, to
write the address of corresponding control register into this
register. When RS and 'CS are at "Low" level, this register is
selected.
•
VSW
Horizontal Total Register (RO)
This is a register used to program total number of horizontal
characters per line including the retrace period. The data is 8-bit
and its value should be programmed according to the specification of the CRT. When M is total number of characters, (M-I)
shall be programmed to this register. When programming for
interlace mode, M must be even.
•
Horizontal Displayed Register (R 1)
This is a register used to program the number of horizontal
displayed characters pet line. Data is 8·bit and any number that
is smaller than that of horizontal total characters can be
programmed.
• Horizontal Sync Position Register (R2)
This is a register used to program horizontal sync position as
multiples of the character clock period. Data is 8·bit and any
number that is lower than the horizontal total number can be
programmed. When H is character number of horizontal Sync
Position, (H.1) shall be programmed to this register. When programmed value of this register is increased, the display position
on the CRT screen is shifted to the left. When programmed
value is decreased, the position is shifted to the right. Therefore,
the optimum horizontal position can be determined by this
value.
Pulse Width
27
26
25
24
0
0
0
0
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
0
1
0
1
5
0
1
1
0
6
16H
0
1
1
1
7
1
0
0
0
1
1
0
0
0
1
1
0
8
9
1
0
1
1
11
1
1
0
0
12
1
1
0
1
13
1
1
1
0
14
1
1
1
1
15
10
H; Raster period
Table 3 Pulse Width of Horizontal Sync Signal
HSW
23
• Sync Width Register (R3)
This is a register used to program the horizontal sync pulse
width and the vertical sync pulse width. The horizontal sync
pulse width is programmed in the lower 4-bit as multiples of the
character clock period. "0" cannot be programmed. The
vertical sync pulse width is programmed in higher 4·bit as
multiples of the raster period. When "0" is programmed in
higher 4-bit, 16 raster period (16H) is specified.
• Vertical Total Register (R4)
This is a register used to program total number of lines per
frame including vertical retrace period. The data is within 7·bit
and its value should be programmed according to the specifica·
tion of the CRTC. When N is total number of lines, (N-I) shall
be programmed to this register.
22
21
2°
Pulse Width
- (Note)
0
0
0
0
0
0
0
1
1 CH
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
0
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
0
0
0
1
0
0
1
8
9
1
0
1
0
10
1
0
1
1
11
1
1
0
0
12
• Vertical Total Adjust Register (RS)
1
1
0
1
13
This is a register used to program the optimum number to
adjust total number of rasters per field. This register enables to
decide the number of vertical deflection frequency more
strictly.
1
1
1
0
14
1
1
1
1
15
CH; Character clock period
(Note) HSW = "0" cannot be used.
• Vertical Displayed Register (R6)
This is a register used to program the number of displayed
character rows on the CRT screen. Data is 7-bit and any number
that is smaller than that of vertical total characters can be
programmed.
169
HD6845S, HD68A45S, HD68B45S
•
Skew function is used to delay the output timing c
CUDISP and DISPTMG signals in LSI for the time to acce
refresh memory, character generator or pattern generato
and to make the same phase with serial video signal.
Vertical Sync Position Register (R7)
This is a register used to program the vertical sync position
on the screen as multiples of the horizontal character line period. Data is 7-bit and any number that is equal to or less than
vertical total characters can be programmed. When V is character number of vertical sync position, (V-I) shall be programmed
to this register. When programmed value of this register is increased, the display position is shifted up. When programmed
value is decreased, the position is shifted down. Therefore, the
optimum vertical position may be determined by this value.
• Maximum Raster Address Register (R9)
This is a register used to program maximum raster addrel
within 5-bit. This register dermes total number of rasters pc
character including space. This register is programmed as fo:
lQws.
Non-interlace Mode, I nterlace Sync Mode
•
When total number of rasters is RN, (RN-l) shall b
programmed.
Interlace and Skew Register (Ra)
This is a register used to program raster scan mode and skew
(delay) of CUDISP signal and DISPTMG signal.
I nterlace Sync & Video Mode
When total number of rasters isRN, (RN-2) shall b
programmed.
Interlace Mode Program Bit (V, S)
Raster scan mode is programmed in the V, S bit.
This manual dermes total number of rasters in non-intedac
mode, interlace sync mode and interlace sync & video mode l
follows:
Table 4 Interlace Mode (2 1 , 2°)
v
o
o
1
o
S
o
Raster Scan Mode
Non-interlace Mode
0-----
} Non-interlace Mode
1----2-----
Interlace Sync Mode
Interlace Sync & Video Mode
Total Number of Rasters 5
Programmed Value Nr = 4
(The same as displayed
total number of rasters
I
4-----
Raster Address
In the non-interlace mode, the rasters of even number
field and odd number field are scanned duplicatedly. In the
interlace sync mode, the rasters of odd number field are
scanned in the middle of even number field. Then it is
controlled to display the same character pattern in two
fields. In the interlace sync and video mode, the raster scan
method is the same as the interlace sync mode, but it is
controlled to display different character pattern in two field.
I nterlace Sync Mode
0 - - - - - - Total Number of Rasters 5
-------------- 0 Programmed Value Nr =4
1----In the interlace sync mode, ,
-------------- 1
2----total number of rasters in
-------------- 2
both the even and odd fields
3------------------ 3
is ten. On programming,
4
----( the half of it is dermed as
-------------- 4
total number of rasters.
)
Raster Address
Skew Program Bit (C1, CO, 01, DO)
These are used to program the skew (delay) of CUDISP
signal and DISPTMG signal.
Skew of these two kinds of signals are programmed
separately.
I nterlace Sync & Video Mode
o
Total Number of Rasters 5
=3
------------ 3
(Total number of rasters )
4
displayed in the even field
Raster Address
and the odd field.
2 - - - - - - - - - - - - 1 Programmed Value Nr
Table 5 DISPTMG Skew Bit (2 7 ,26 )
01
DO
0
0
0
• Cursor Start Raster Register (R10)
01 SPTMG Signal
This is a register used to program the cursor start raste
address by lower 5-bit (2° -24) and the cursor display mode b~
higher 2-bit (25 , 26).
Non-skew
1
One-character skew
0
Two-character skew
Table 7 Cursor Display Mode (26 , 2 5 )
Non-output
Table 6 Cursor Skew Bit (25 • 24)
C1
CO
0
0
0
B
P
Cursor Display Mode
0
0
Non-blink
0
1
Cursor Non-display
0
Blink, 16 Field Period
Non-skew
Blink, 32 Field Period
Non-skew
1
One-character skew
0
Two-character skew
Blink Period
light
Non-output
.
16 or 32 Field Period
170
dark
HD6845S, HD68A45S, HD68B45S
• Cursor End Raster Register (R 11)
This is register used to program the cursor end raster address.
6) 2 ~Nr ~30
7) 3 ~ Nht (Except non-interlace mode)
5 ~ Nht (Non-interlace mode only)
• Start Address Register (R12, R13)
These are used to program the first address of refresh
memory to read out.
Paging and scrolling is easily performed using this register.
This register can be read but the higher 2-bit (2 6 ,2 7) ofR12 are
always "0".
*
In the interlace mode, pulse width is changed ±Jfz raster time when
vertical sync signal extends over two fields.
Notes for Use
The method of directly using the value programmed in the
internal register of LSI for controlling the CRT is adopted.
Consequently, the display may flicker on the screen when the
contents of the registers are changed from bus side asyncronously with the display operation.
Cursor Register
Writin~ into this register at frequent intervals for moving the
cursor should be performed during horizontal and vertical
retrace period.
Start Address Register
Writing into the start address register at frequent intervals for
scrolling and paging should be performed during horizontal and
vertical display period.
It is desirable to avoid programming other registers during
display operation.
• Cursor Register (R14, R15)
These two read/write registers stores the cursor location. The
higher 2-bit (2 6 , 27) of R 14 are always "0".
• Light Pen Register (R16, R17)
These read only registers are used to catch the detection
address of the light pen. The higher 2-bit (2 6 , 27) of R16 are
always "0". Its value needs to be corrected by software because
there is time delay from address output of the CRTC to signal
input LPSTB pin of the CRTC in the process that raster is lit
after address output and light pen detects it. Moreover, delay
time shown in Fig. 2 needs to be taken into account.
Restriction on Programming Internal Register
1) o
'0
Horizontal
Retrace
Period
al
>
ca
Q.
0
B
of:
QI
]
>~
'0
RM Access + CG Access + tMAD
1
tCH
2
RM Access
3
RM
+ CG Access + tMAD ~ tCH > RM
Access + tMAD ~ tCH > RM Access
C1
CO
01
DO
0
1
0
0
0
Fig. 18
0
0
Fig. 19
1
0
1
0
Fig. 17
Access
+ tMAD
Interlace & Skew Register
Bit Programming
tCH :. CHCP Period; tMAD: MA Delay
F1
CUDISP
CHCP·N - _ - - I
F2
DISPTMG
CRTC
Refresh
MA
CG
RA
ClK
CHCP·P
L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ I DOT COUNTER ....--+---1
Figure 18 Display Control Unit (2)
F1
~-C~U~D~I~S-P---------------_iD Q~---------,
CHCP·N-_.......... T
DISPTMG
CRTC
MA
P
Refresh
Memory
1==:::>1-15
RA
ClK
L-----------------~C~H~C~P~~~DOTCOUNTER·....--4-~
Figure 19 Display Control Unit (For high·speed display operation) (3)
180
1
HD6845S, HD68A45S, HD68B45S
CHCP-P
MA
DISPTMG
---1----\-'
CUDISP
----~----~--~+-----------~-----'
F2 -Q
F1-Q
VIDEO
\
CRT Display
•••••••
Figure 20 Time Chart of Display Control Unit (1)
CHCP-P
----,
-
-
MA
X
0
~
X
1
DISPTMG
y--_. ----1
CUDISP
I-- one-Character~
Skew
"
\""
Fl-Q
'IIlllll!f.
RMOUT
LATCH (1)
CGOUT
0
~
'I1l7llli.
0
VIDEO
CRT Disp lay
2
X
~
I"""""-~ 1 " " " " " - -r--
" •••••••
V
3
X
4
~
'Illlllll!!.
-
4
X
3
2
"--r--1
X
\
tllll7lJI..
-
1
- - "-~- X
X 0
J_X_
-
YllllllJI
1
X
3
r---- ~----'-\
'\
F2-Q
2
-
, " " " , , - -"--
i:2 ~X-2.
Figure 21 Time Chart of Display Control Unit (2)
X
1"""""-
HD6845S, HD68A45S, HD68B45S
VIDEO
\
CRT Display
•••• ••
Figure 23 Time Chart of Display Unit (3)
• HOW TO DECIDE PARAMETERS SET ON THE CRTC
(Nvt + 1) (Nr + 2) + 2Nadj
Rt =
2
•
How to Decide Parameters Based on Specification of CRT
Display Unit (Monitor)
Number of Horizontal Total Characters
Horizontal deflection frequency fh is given by specification
Rt =(Nvt + l)(Nr + 2) + 2Nadj +1 ............. (b)
2
of CRT display unit. Number of horizontal total characters is
determined by the following equation.
fh
=
............. (a)
(a) is applied when both total numbers of vertical characters
(Nvt + 1) and that of rasters in a line (Nr + 2) are odd.
(b) is applied when total number of rasters (Nr + 2) is even, or
when (Nr + 2) is odd and total number of vertical characters
(Nvt + 1) is even.
where,
Rt
Number of Total Rasters per frame
(Including retrace period)
Nvt
Programmed Value of Vertical Total
Register (R4)
Nr
Programmed Value of Maximum Raster
Address Register (R9)
Nad~
Programmed Value of Vertical Total Adjust
Register (R5)
I
tc (Nht + 1)
where,
tc : Cycle Time of CLK (Character Clock)
Nht : Programmed Value of Horizontal Total Register
(RO)
Number of Vertical Total Characters
Vertical deflection frequency is given by specification of
CRT display unit. Number of vertical Total characters is
determined by the following equation.
1) Non-interlace Mode
Rt (Nvt + 1) (Nr + 1) + Nadj
2) Interlace Sync Mode
Rt = (Nvt + 1) (Nr + 1) + Nadj + 0.5
3) Interlace Sync & Video Mode -
=
Horizontal Sync Pulse Width
Horizontal sync pulse width is programmed to low order
4-bit of horizontal sync width register (R3) in unit of horizontal
character time. Programmed value can be selected within from 1
to 15.
182
HD6845S, HD68A45S, HD68B45S
Horizontal Sync Position
Vertical Sync Position
As shown in Fig. 24, horizontal sync position is nonnally
selected to be in the middle of horizontal blank period. But
there are some cases where its optimum sync position is not
located in the middle of horizontal blank period according to
specification of CRT. Therefore, horizontal sync position
should be detennined by specification of CRT. Horizontal sync
pulse position is programmed in unit of horizontal character
time.
As shown in Fig. 25, vertical sync position is nonnally·
selected to be in the middle of vertical blank period. But there
are some cases where its optimum sync position is not located in
the middle of vertical blank period according to specification of
CRT. Therefore, vertical sync position should be detennined by
specification of CRT. Vertical sync pulse position is programmed to vertical sync position register (R 7) in unit of line
period.
I"
DISPTMG
"I
lH
• How to Decide Parameters Based on Screen Format
Dot Number of Characters (Horizontal)
"
LI - Horizontal -+HOrjZO"t81~ Horizontal ~
r--- Video Period
BI.n~
Video Period
-.J
Dot number of characters (horizontal) is detennined by
character font and character space. An example is shown in Fig.
26. More strictly, dot number of characters (horizontal) N is
determined by external N-counter. Character space is set by
means shown in Fig. 27.
-,nl_ _ _ _ _ _- - -
HSVNC.n~---_ _ _ _
Figure 24 Time Chart of HSYNC
Dot Number of Characters (Vertical)
Vertical Sync Pulse Width
Vertical Sync Pulse Width is programmed to high order 4-bit
of vertical sync pulse width register (R3) in unit of raster
period. Programmed value can be selected within from 1 to 16.
Dot number of characters (vertical) is detennined by
characters font and line space. An example is shown in Fig. 26.
Dot number of characters (vertical) is programmed to maximwn
raster address (register R9) of CRTC. When Nr is programmed
t,___
f-- Vertical
----I""'.~ Vertical __
Vertical
--I
I
Video Period
Blank
Video Period
I
OISPTMG--.J
I I U"'--I-----,&...I_ _ _.......Ii-......_I---4J~
I.
.1
1 Frame
VSYNC------------------------~n~-------------------------Figure 25 Time Chart of VSYNC
Don Number of
Character Fo nt
,HOd,O,'" Ch"'''''Oh aracter
L
"-.
•
•
•
• •
I
S~ace
•• • • •
•
•
•
•
•••••••
•
•
•
•
•
•
•
•
•• • • • •
•
•
•
•
•
•
•••••
•
•
Dot Number of
Vertical Characters
(Number of Rasters)
j
Line
Space
(
Dot Number of Horizontal Characters
Dot Number of Vertical Characters
7X9 Character generator is used.
Figure 26 Dot Number of Horizontal and Vertical Characters
183
10
13
HD6845S, HD68A45S, HD68845S
Character Font
\
•••••
•
•
•
•
•
•
••••
•
•
•
•
•
•
•••••
..0 ....0"
"0"
I I
I
I
Seria I Data
Shift Register
Figure 27 How to Make Character Space
Horizontal Deflection Period (th)
Horizontal Display Period
_I
=
*
Horizontal Retrace Period
I
'
'['
Number of Horizontal Displayed Characters
tc
~
Horizontal Display Period
Horizontal Character Time =
-----------:-::-c:---Number of Horizontal Displayed Characters
Figure 28 Number of Horizontal Displayed Characters
value of R9, dot number of characters (vertical) is (Nr+l).
Number of Horizontal Displayed Characters
Number of horizontal displayed characters is programmed to
horizontal displayed register (Rl) of the CRTC. Programmed
value is based on screen format. Horizontal display period,
which is given by specification of horizontal deflection frequencyand horizontal retrace period of CRT display unit,
determines horizontal character time, being divided by number
of horizontal displayed characters. Moreover, its cycle time and
access time which are necessary for CRT display system are
determined by horizontal character time.
Number of Vertical Displayed Characters
cal retrace period and the relation between number of vertical
displayed character and total number of rasters on a screen is
as mentioned above, CRT which is suitable for desired screen
format should be selected.
For optimum screen format, it is necessary to adjust number
of rasters per line, number of vertical displayed characters, and
total adjust raster (Nadj) within specification of vertical
deflection frequency.
Scan Mode
The CRTC can program three-scan modes shown in Table 11
to interlace mode register (R8). An example of character display
in each scan mode is shown in Fig. 7.
N umber of vertical displayed characters is programmed to
vertical displayed register (R6). Programmed value is based on
screen format. As specification of vertical deflection frequency
of CRT determines number of total rasters (Rt) including verti184
HD6845S, HD68A45S, HD68B45S
Cursor Display Method
Table 11 Program of Scan Mode
21
2°
0
0
1
0
0
1
1
1
Fine Display of Characters
Cursor start raster register and cursor end raster register
(RIO, Rll) enable programming the display modes shown in
Table 7 and display patterns shown in Fig. 8. Therefore, it is
possible to change the method of cursor display dynamically
according to the system conditions as well as to realize the
cursor display that meets the system requirements.
& Figures
Start Address
Main Usage
Scan Mode
Non-interlace
Interlace Sync
Interlace Sync
& Video
Normal Display of Characters
& Figures
& Figures Without Using
Start address resisters (RI2, R13) give an offset to the
address of refresh memory to read out. This enables paging and
scrolling easily.
High-resolution CRT
Cursor Register
Display of Many Characters
Cursor registers (RI4, R1S) enable programming the cursor
display position on the screen. As for cursor address, it is not X,
Y address but linear address that is programmed.
[NOTE] In the interlace mode, the number of times per
sec. in raster scanning on one spot on the screen
is half as many as that in non-interlace mode.
Therefore, when persistence of luminescence is
short, flickering may happen. It is necessary to
select optimum scan mode for the system, taking
characteristics of CRT, raster scan speed, and
number of displayed characters and figures into
account.
•
EXAMPLES OF APPLIED CIRCUIT OF THE CRTC
Fig. 30 shows an example of application of the CRTC to
monochrome character display. Its specification is shown in
Table 12. Moreover, specification of CRT display unit is shown
in Table 13 and initializing values for the CRTC are shown in
Table 14.
Table 12 Specification of Applied Circuit
Item
Specification
Character Format
5 x 7 Dot
Character Space
Horizontal: 3 Dot Vertical : 5 Dot
One Character Time
1 J,LS
Number of Displayed Characters
40 characters x 16 lines = 640 characters
Access Method to Refresh Memory
Snychronous Method (DISPTMG Read)
Refresh Memory
1 kB
Address Map
Refresh
Memory
CRTC
Address
Register
CRTC
Control
Register
2 15 214 :2 13 212 211 2 10 2 9
28
27
26
25
24
23
22
21
2°
0
0
0
0
0
0
*
*
*
*
*
*
*
*
*
*
0
0
0
1
0
0
x
x
x
x
x
x
x
x
x
0
0
0
0
1
0
0
x
x
x
x
x
x
x
x
x
1
x ... don't care,
Synchronization Method
* ... 0 or 1
HVSYNC Method
Table 13 Specification of Character Display
Item
Specification
Scan Mode
Non-interlace
Horizontal Deflection Frequency
15.625 kHz
Vertical Deflection Frequency
60.1 Hz
Dot Frequency
8MHz
Character Dot (Horizontal x Vertical)
8 x 12 (Character Font 5 x 9)
Number of Displayed Characters (Row x Line)
40x 16
HSYNCWidth
4J,Ls
VSYNCWidth
3H
Cursor Display
Raster 9 ....... 10, Blink 16 Field Period
Paging, Scrolling·
Not used
185
HD6845S, HD68A45S, HD68B45S
Table 14 Initializing Values for Character Display
Register
Symbol
Name
RO
Horizontal Total
Nht
3F
R1
R2
R3
Horizontal Displayed
Nhd
28
(40)
Horizontal Sync Position
Nhsp
34
(52)
Sync Width
Nvsw, Nhsw
34
R4
Vertical Total
Nvt
14
(20)
RS
R6
Vertical Total Adjust
08
( 8)
Vertical Displayed
Nadj
Nvd
10
(16)
R7
Vertical Sync Position
Nvsp
13
(19)
RS
R9
R10
Interlace & Skew
(63)
00
Nr
Maximum Raster Address
OB
(11 )
Cursor Start Raster
B, P, NCSTART
49
R11
Cursor End Raster
NCEND
OA
(10)
R12
R13
Start Address (H)
00
( 0)
Start Address (L)
00
( 0)
R14
Cursor (H)
00
( 0)
R15
Cursor (L)
00
( 0)
tc
1 IJS
10123456710123466,1012345671
~1111111
!
~
B
Initializing Value
Hex (Decimal)
\
Cursor
Figure 29 Non-interlace Display (Example)
186
fiE
.fTTL
~
VMA Au
A..
Au Au
A"
:"
\.11 i i t i i
r
-
O~D.D.D
1~
ri;;;1 rJ;;~
~
I,--
Vee
~~1
II L=1!,
L
~E
~
~!I!!!~
~
;:6
HD74LSOO
I d'
......
iiiC
s
•
".
H~.14.LS1~~.
RMAft-RMA~
~•
+-+--.--\0,
::1 E-+---+----------,
~:
o.
ru
0,
0,
0,
o.
~i~;1
r
..... ~
0)
o
Uk.1 ..
CIt
$0
::E:
C
..
G)
.Vee
rrl
;
"7
L..-----,..,--Jkt-Rttf¥hh.
Vee
MelJ
HD74021
s
CI7ITITl
~·"G'
-mT
, I
[[2,.;.. ..
CIt
$0
::E:
CGA,-CGA,
C
I
..
G)
CIt
III
CIt
en
~
i
~
VIDEO~
H07486
I'
)D...------- HVSYNC·P
R, :510
os;
~~t I~',! aRz
::E:
C
G)
CIt
t:
......
0:0.0.0'
,I' .zJf-----W
Figure 30 Example of Applied Circuit of the CRTC (Monochrome Character Display)
HD6845S, HD68A45S, HD68B45S
Differences between the HD6845R (Motorola MC6845 Compatible) and the HD6845S (Enhanced)
No.
HD8845R
Functlona' Difference
HD8845S
Character line address
Interlace
Sync
Programming
Methoti
&
num~r of
0
vertical
characters
1---------------
Video Mode
Display
Character line address
~_B_C_ -
- - - - - - - - --
Programming
unit for
number of
vertical
characters
2--------------3--------------4---------------
Number of
raster per
character
line
o
ABC
} Programming
1 ______________
unit for
2
number of
43 _______________
~~:~~~~ers
5 ________________
6 _ _ _ _ _ _ _ _ _ _ _ __
7 _______________
8 _ _ _ _ _ _ _ _ _ _ _ __
9 _______________
In HD6845R. number of characters is vertically
programmed in units of two lines. as illustrated
above. (Number of vertical total characters.
Number of vertical displayed characters.
Vertical Sync Position)
In HD6845S. number of characters is vertically
programmed in unit of one line. as illustrated
above. (Number of vertical total characters.
Number of vertical displayed characters.
Vertical Sync Position)
Example of above figure ...
Example of above figure ...
Programmed number into Vertical Displayed
Register = 5
Programmed number into Vertical Displayed
Register = 10
Both even number and odd number can be
specified.
Character
Character!
line address
Only even number can be specified.
~ ~i~~~~~~~~~I~ {r\
,--------------<}
2 -t-e--e--o-- O--l ~
4
-t---------g--3
o
2
Number of raster
Ch,,,,,.,
0
line address
6 -t---------8"-5
--E)--e--e--G-----7
8---------------9
------
Number of raster = 10 scanline (specified)
However. number which is programmed into
register is calculated as follows.
Programmed number (Nr)
= (Number specified) - 1
4
--G---~~=~~-::
_! _________ ~- t
:dJdrss
3
eeeee
--E)-----------E)-- 5
: =!=========~= :
0
::E~~:t: :{ ,
: =~=~~=~==== :~
~ =t=========1=
~}
-"2"---------t4
eeeee
6
~ =;=~==~==~=~=
~J
_! _________
--E)-----------E)-- 2
3
5
9
~- 4
e
e
--E)-----------E)-- 6
e e e
e
--------------- 8
When number of raster
per character line
is EVEN
When number of raster
per character line
is ODD.
Number of raster
= 10 scan line
(specified)
Number of raster
'" 9 scan line
(specified)
However. number which is programmed into
register is calculated as follows.
Programmed number (NR)
= (Number specified) - 2
Cursor
Display
Cursor is displayed in both EVEN field
and ODD field.
Cursor is displayed in either EVEN field
or ODD field.
0-----2
4
6
--9-9--Ei--9-0--
0------
1 ~ EVEN number
--------------- 3
eeeee
--9-9--Ei--9-0-- 5--+- EVEN number
--------------- 7
8------
0--------------------
--------------- 1
e e e e e -+- EVEN number
-t-t=g-1-t6 -t-t=g-1-t- ~ EVEN number
--------------- 7
2
4
3
8-----O---~--
--------------- 1
2 ------
1
2 --G--&--e--G---E)-- 3 ~ ODD number
4 --G--&--e--G---E)-- 5 ~ ODD number
6-------------------- 7
4 -t-t~-1-t- 3 ~ ODD number
6 --G--e--e--o---E)-- 5 ~ ODD number
--------------- 7
8-----0------
8 ------
2
--9-0--0--9-'9--
1~ EVEN number
--G--e--e--G---E)-- 3
4 -!-~~--S.-!- 5-+ ODD number
6 -------------------- 7
8
188
0
5
1
HD8845S, HD68A45S, HD68B45S
No.
Functional DIHerence
HD6845R
Fixed at 16 raster scan cycle
Vertical Sync
2
HD6645S
(16H)
Programmable (1 -16 raster scan cycle)
Pulse Width
r-Fixed at 16
scan cycle
(VSYNC output)
VS~
R3
V~
R3
I I I I I I I I
I
Not used
SKEW Function
high order
4 bits of R3
I
~
3
~specified by ~
~
I
I I I I
IWV31wV21WV11wvOi
~~
~
Vertical Sync Horizontal Sync
Width
Width
Horizontal Sync Width
Not included
SKEW capability is included in DISPTMG.
CUDISP signals.
Attached byte
~
R8
R8
I I
I
I I I Ivisl
I C, ICo ID, IDo I
'-.,-' ' - . , - '
~
I I I I
V
S
CUDISP DISPTMG
Not used
Example of DISPTMG output
~
Not skewed
_ ~ One character skew
_~ Two character skew
1 character time
2 character time
H
4
Start Address Register
5
RESET Signal (RES)
Write Only
MAD
RAo
M'3 Output {
N
N
Read or Write
~A4 Output
-----Synchronous reset
MAo - MA" 0",.", }
RAo
N
RA4 Output
___ - Asynchronous reset
Other Outputs--------Asynchronous reset
Other Outputs
Output signals of MAD MA,3. RAo RA 4•
synchronized with CLK "LOW' level. go to
"LOW" level. after RES has gone to "LOW."
Other outputs go to "LOW" immediately after
RES has gone to "LOW" level.
N
N
Output signals of MAo ~ MA,3. RAo RA4 and
others go to "LOW" level immediately after
RES has gone to "LOW" level.
N
AC Characteristic Differences between HD6845R (Motorola MC6845 Compatible) and HD6845S (Enhanced)
No.
Characteristic Difference
Symbol
1
Clock Cycle Time
tcyce
min.
HD46505R
typo
max.
HD46505S
min.
typo
max.
-
-
330
-
-
270
Unit
ns
2
Clock Pulse Width "High"
PWCH
150
-
-
130
-
-
ns
3
Clock Pulse Width "Low"
PWCL
150
-
-
130
-
-
ns
4
Rise and Fall Time for Clock Input
-
-
15
-
20
ns
-
-
250
-
-
200
ns
-
60
-
-
ns
80
-
70
ns
-
10
-
-
0
ns
5
Horizontal Sync Delay Time
6
Light Pan Strobe Pulse Width
7
Light Pan Strobe.
Uncertain Time of Acceptance
T cR , TeF
THSD
PWLPH
80
-
TLPDl
T LPD2
189
HDS84&
COMBO (Combination ROM 1/0 Timer)
The HD6846 combination chip provides the means, in
conjunction with the HD6802, to develop a basic 2-chip
microcomputer system. The H06846 consists of 2048 bytes of
mask-programmable ROM, an 8-bit bidirectional data port with
control lines, and a 16-bit programmable timer-counter.
This device is capable of interfacing with the HD6802 (basic
H06800, clock and 128 bytes of RAM) as well as the
H06800 if desired. No external logic is required to interface
with most peripheral devices.
•
•
•
FEATURES
2048 8-Bit Bytes of Mask-Programmable ROM
8-Bit Bidirectional Data Port for Parallel Interface plus
Two Control Lines
•
•
Programmable Interval Timer-Counter Functions
Programmable liD Peripheral Data, Control and Direction Registers
•
Compatible with the Complete HMCS6800 Microcomputer Product Family
•
•
TTL-Compatible Data and Peripheral Lines
Single 5-Volt Power Supply
•
Compatible with MC6846
(DP-40)
• TYPICAL MICROCOMPUTER
Vee
CTO
Coun.rlTimer I/O { CTG
CTC
p.
P,
P,
ParaUell/O
Control
Vee
$landb'( Vee
Vee
• PI N AR RANG EMENT
A,
1o-L---+--4iiEs
r - - -.....--tiRa
A.
1-----1VMA
1-----1E
1-----1RIW
REs
P,
p.
P,
p.
Vee
A..
iiiQ
H06802
cpI
(CPU)
CP,
Ao
1V_ _oov"I O. - O ,
A,
A,
{C::
A,
CP,
Vee
P,
40 pins
P,
P,
... Vss
P,
P,
This is. block diegram of e typical cost effactive microcomputer. The MPU is
the center of the microcomputer system and is shOW'n in I minimum system inter·
facing with e ROM combination chip. It is not intended that this system be limited to
this function but thet it be expandable with other perts in the HMCS6800 Microcomputer family.
P,
P,
Po
(Top View)
190
-------------------------------------HD6846------------------------------------• RECOMMENDED OPERATING CONDITIONS
• ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Value
Unit
~
V
Input Voltage
Vee *
Vin *
-0.3~
Operating Temperature
Topr
-20
~
Storage Temperature
Tstg
-55
~
Supply Voltage
-0.3
+7.0
+7.0
Item
Symbol
min
typ
max Unit
Vee *
4.75
5.0
5.25
V
VIL *
-0.3
-
0.8
V
Vee
75
°c
Supply Voltage
+75
V
°c
Input Voltage
+150
°c
Operating Temperature
* With respect to Vss (SYSTEM GND)
(NOTE) Permanent LSI damage may occur if maximum
ratings are exceeded. Normal operation should
be under recommended operating conditions. If
these conditions are exceeded, it could affect
reliability of LSI.
VIH *
2.0
-
Topr
-20
25
* With respect to VSS (SYSTEM GND)
• ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (Vcc=5.0V±5%, VSS=OV, Ta=-2~+75°C, unless otherwise noted.)
Symbol
Item
Test Condition
min. typo
max. Unit
Input "High" Voltage
All Inputs
V IH
2.0
-
Input "Low" Voltage
All Inputs
VIL
-0.3
-
Vee
0.8
Vee -0.5
Vee
+0.5
Vee -0.5
Vee
+0.5
Input "High" Level
Clock Overshoot/Undershoot
Input Leakage Current
Input "Low" Level
R/W, RES, CSo ,
CSt, CPt, CTG,
CTC, E, Ao~A10
Do~D7' PO~P7'
Three-State (Off State)
I nput Current
CP 2
Output "High" Voltage
CP 2 ,
Vos
PO~P7
Output "Low" Voltage
Output "High" Current
(Sourcing)
Output "High" Current
(Sourcing)
(the current for driving other than
TTL, e.g., Darlington Base)
Output "Low" Current
(Sinking)
Output Leakage Current
(Off State)
-
-
10
pA
IOH = -205pA
2.4
V
' 2.4
-
-
IOH = -200pA
-
V
IOH = -200pA
2.4
-
-
V
VOL
loi.. = 1.6mA
-
-
004
V
0.4
V
-
pA
5.25V
IOL = 3.2mA
VOH = 204V
VOH = 204V
200
-
IOH
VOH = 1.5V
-1.0
-
1.6
IOL
VOL = O.4y
3.2
-
-
mA
IRQ
ILOH
VOH = 2.4V
-
-
10
pA
20
pF
Vee = OV
-
mW
Cin
Cin
-
800
E
12.5
pF
Do~D7
IOH
CTO, CP 2 ,
CP 2 ,
PO~P7
PO~P7
Do~D7
Other Outputs
-
Power Dissipation
Po
Do~D7
PO~P7'
Capacitance
pA
Vin = 0.4 ~ 2.4V
Do~D7
Other Outputs
2.5
ITSI
CTO
V
-
Vin = 0
VOH
V
-
~
lin
Do~D7
V
CP 2 , CTO
205
pA
-10 mA
Gout
Cin
Vin = OV
-
-
10
pF
Ta = 25°C
-
-
7.5
pF
RES, CSo , CSt,
CPt, Ef'G
Cin
f = 1 MHz
-
-
10
pF
IRQ
Cout
-
-
7.5
pF
Ao~A10,
R/W
191
V
-----------------------------------HD6846----------------------------------• AC CHARACTERISTICS (Vcc=5.0V±5%, VSS=OV, Ta=-20'"'-'+75°C, unless otherwise noted.)
1. BUS TIMING
min
typ
Enable Cycle Time
Item
Symbol
teyeE
Test Condition
1.0
Enable Pulse Width, "Low"
PWEL
430
-
Enable Pulse Width, "High"
PWEH
430
Address Set Up Time
tAS
140
Data Delay Time
tOOR
Data Hold Time
tH
Address Hold Time
tAH
10
Enable Rise and Fall Time
tEf,tEr
195
Data Set Up Time
tosw
Reset "Low" Time
tRL
Interrupt Release Time
tlR
Fig. 1
10
2
Fig. 2
-
max
10
4500
4500
Unit
#J.S
ns
ns
-
ns
320
ns
-
ns
25
ns
ns
-
ns
-
p.s
1.6
p.s
2. PALLAREL PERIPHERAL I/O LINE TIMING
Symbol
Test Condition
min
typ
max
Peripheral Data Setup Time
tposu
Fig.3
200
-
ns
Rise and Fall Times CPt. CP 2
tpr, tpf
Fig. 5
-
-
1.0
-
#J.S
p.s
Fig.4
20
-
-
ns
-
1.0
p.s
-
2.0
p.s
1.0
p.s
ns
-
-
typ
max
Unit
Item
Delay Time E to CP 2 Fall
tCP2
Delay Time I/O Data CP 2 Fall
toc
Delay Time E to CP 2 Rise
tRS1
Delay Time CPt to CP 2 Rise
tRS2
Fig.5
-
Peripheral Data Delay
tpow
Fig.4
-
Peripheral Data Setup Time for Latch
tpsu
Peripheral Data Hold Time for Latch
tpDH
Fig.9
100
15
1.0
Unit
ns
3. TIMER/COUNTER LINE TIMING
Item
Symbol
CTC, CTG Rise and Fall Time
tCr. tCf
CTC, CTG Pulse Width, "High" (Asynchronous Mode)
tpWH
CTC, CTG Pulse Width, "Low" (Asychronous Mode)
tpWL
CTC, CTG Setup Time (Synchronous Mode)
tsu
CTC, CTG Hold Time (Synchronous Mode)
thd
CTO Delay Time
tCTO
192
Test Condition
Fig. 6
Fig. 7
Fig. 8
min
-
-
100
ns
~~58
-
-
ns
~~~
-
-
ns
200
-
ns
50
-
-
ns
-
-
1.0
#J.S
-------------------------------HD6846--------------------------------
E
E
R/W
Ao~Alo
CP 2
CS o , CS 1
(Output)
Figure 5 CP 2 (Output) Delay Time
Do~D7
(Read)
-------
COM BO..... MPU
Do ~D7 (Write)
------
MPU-->COMBO
Figure 1 Bus ReadlWrite Timing
Figure 6 CTG, CTC Pulse Width
E
\'---
E
t'R---F~'
2.4V
IRQ
--------------~
Figure 2 I RQ Release Time
Figure 7 CTG, CTC Setup Time and Hold Time
~.OV
p.-p, -------
E
E
~~:~p:~su--~--,--------------!2.0V
_tiov
\~
'I--tCTO~~
~
2.4V
CTO_________
Figure 3 Peripheral Data Set Up Time
~O~.4~V~_____
Figure B CTO Delay Time
E
PO~P7
(Output) _ _ _ _--' 1\--1-___
tpSUJ..-----~tpDH
2.0V
CP 2
O.8V
(Output)
Figure 4 Peripheral Data and CP 2 (Output) Delay Time
Figure 9 Peripheral Port Latch Setup and
Hold Time
193
------------------------------------HD6846-----------------------------------The timer/counter control register allows control of th
interrupt enable, output enable, selection of an internal 0
external clock source, a -:- 8 prescaler, and operating mode
Input pin CTC (counter-timer clock) will accept an asytl
chronous clock pulse to decrement the internal register for th,
counter-timer. If the divide-by-8 prescaler is used, the maximun
clock rate can be four times the master clock f~ency with aJ
absolute maximum of 4 MHz. Gate input (CTG) accepts aJ
asynchronous TIL-compatible Signal which may be used as
trigger or gating function to the counter-timer. A counter-time
output (CTO) is also available and is under software contra
being dependent on the timer control register, the gate input
and the clock source.
LOA~B
S.OV
ITImI
LOAD A
10,-0" CTO,
CP" P,-P,I
I.Skll
Test Point
Test POint
l~'
•
C - 13()pF for 0,-0,
3()pF forCTO,CP"P,-P,
Parallel I/O Port
The parallel bidirectional I/O port has functional operationa
characteristics similar to the B port on the HD6821 PIA. Thi:
includes 8 bidirectional data lines and two handshake contra
signals. The control and operation of these lines are completel;
software programmable.
The interrupt input (CP I) will set the interrupt flag CSRI 0
the composite status register. The peripheral control (CP 2 ) rna;
be programmed to act as an interrupt input (set CSR2) or as :
peripheral control output.
R-ll kfl forD,-D,
12kll forCTO,CP"Po-P,
RL - 2.4 kll for 0 0 -0,
1.2 kll for CTO, CP" P,-P,
All diode. ara IS2074@ .
Figure 10 BusTiming Test Loads
p.
P,
P,
P,
• GENERAL DESCRIPTION
The HD6846 combination chip may be partitioned into
three functional operating sections: programmed storage, timercounter functions, and a parallel I/O port.
•
P,
p.
P,
CP,
Programmed Storage
CP,
es o
es,
The mask-programmable ROM section is similar to other
ROM products of the HMCS6800 family. The ROM is organized
in a 2048 by 8-bit array to provide read only storage for a
minimum microcomputer system. Two mask-programmable
chip selects are available for user deflnition.
Address inputs Ao '" A IO allow any of the 2048 bytes of
ROM to be uniquely addressed. Bidirection~ data lines (Do '"
D,) allow the transfer of data between the MPU and the HD
6846.
•
p.
Do
0,
0,
0,
D.
0,
0,
0,
Vee
Ao
A,
A,
A,
A.
A,
A,
A,
A,
A,
Vss
A"
Timer-Counter Functions
Under software control this 16-bit binary counter may be
programmed to count events, measure frequencies, time intervals, or similar tasks. Internal registers associated with the I/O
functions may be selected with Ao, A I and A 2 • It may also be
used for square wave generation, single pulses of controlled
duration, and gated signals. Interrupts may be generated from a
number of conditions selectable by software programming.
194
Figure 11 Combination ROM I/O Timer (COMBO)
Basic Block Diagram
-----------------------------------HD6846-----------------------------------
CP,
CP,
fRO Buffer
&
Status Register
Peripheral
Data
Register
Po
P,
P,
P,
P,
P,
P,
....--P,
Figure 12 Parallel I/O Port Block Diagram
Figure 13 Timer/Counter Block Diagram
•
• SIGNAL DESCRIPTION
•
Bus Interface
The HD6846 interfaces to the HMCS6800 Bus via an eight
bit bidirectional data bus, two Chip Select lines, a Read/Write
line, and eleven address lines. These signals, in conjunction with
the HMCS6800 VMA output, permit the MPU to control the
HD6846.
•
•
Bidirectional Data Bus (Do ~D7 )
•
Read/Write (R/W)
This signal is generated by the MPU and is used to control
the direction of data transfer on the bidirectional data pins. A
"Low" level on the R/W input enables the HD6846 input
buffers and data is transferred to the circuit during the E pulse
when the part has been selected. A "High" level on the R/W
input enables the output buffers and data is transferred to the
MPU during E when the part is selected.
Chip Select (CS o , CSt)
The CS o and CS 1 inputs are used to select the ROM or I/O
timer of the HD6846. They are mask programmed to be active
"High" or active "Low" as chosen by the user.
•
Enable (E)
This. signal synchronizes data transfer between the MPU and
the HD6846. It also performs an equivalent synchronization
function on the external clock, reset, and gate inputs of the
HD6846 Timer section.
The bidirectional data lines (Do ~ D 7 ) allow the transfer of
data between the MPU and the HD6846: The data bus output
drivers are three-state devices which remain in the highimpe¢mce (Off) state except when the MPU performs an
HD6846 register or ROM read (R/W = 1 and I/O Registers or
ROM selected).
•
Reset (RES)
The active "Low" state of the RES input is used to initialize
all register bits in the I/O section of the device to their proper
values. (See the section on Initialization for Reset conditions for
timer and peripheral registers.)
•
Interrupt Request (I RQ)
The active "Low" IRQ output acts to interrupt the MPU
through logic included on the HD6846. This output utilizes an
open drain configuration and permits other interrupt request
outputs from other circuits to be connected in a wire-OR
configuration.
Address Inputs (Ao ~ A 1 0 )
The Address Inputs allow any of the 2048 bytes of ROM to
be uniquely selected when the circuit is operating in the ROM
mode. In the I/O-Timer mode, address inputs Ao , AI, and A2
select the proper I/O Register, while A3 through A I 0 (together
with CS o and CSd can be used as additional qualifiers in the
I/O Select circuitry. (See the section on I/O-Timer Select for
additional details.)
•
Peripheral Data (PO~P7)
The peripheral data lines can be individually programmed as
either inputs or outputs via the Data Direction Register. When
programmed as outputs, these lines will drive two standard TTL
195
-----------------------------------HD6846----------------------------------loads (3.2 rnA). They are also capable of sourcing up to 1.0 rnA
.
at 1.5 Volts (Logic" 1" output.)
When programmed as inputs, the output drivers associated
with these lines enter a three-state (high impedance) mode.
Since there is no internal pull-up for these lines, they represent
a maximum 1OIlA load to the circuitry driving them regardless of logic state.
A logic zero at the RES input forces the peripheral data lines
to the input configuration by clearing the Data Direction
Register. This allows the system designer to preclude the
possibility of having a peripheral data output connected to an
external driver output during power-up sequence.
•
Interrupt Input (CP l
CTC inputs in this document relate to internal recognition 01
the input tranSition. Note that a clock transition which does n01
meet setup and hold time specifications may require all
additional Enable pulse for recognition.
When observing recurring events, a lack of synchronization
will result in either "System jitter" or "Input jitter" being
observed on the output of the HD6846 when using an
asynchronous clock and gate input signal. "System jitter" is the
result of the input signals being out of synchronization with
Enable, permitting signals with marginal set-up and hold time to
be recognized by either the bit time nearest the input transition
or subsequent bit time. "Input jitter" can be as great at the time
between the negative going transitions of the input signal plus
the system jitter if the first transition is recognized during one
system cycle, and not recognized the next cycle or vice-versa.
)
Peripheral input line CP 1 is an input-only that sets the
Interrupt Flags of the Composite Status register. The active
transition for this signal is programmed by the peripheral
control register for the parallel port. CP 1 may also act as a
strobe for the peripheral data register when it is used as an input
latch. Details for programming CP I are in the section on the
parallel peripheral port.
•
Gate Inputs (CTG)
Peripheral Control line CP 2 may be programmed to act as an
Interrupt input or Peripheral Control output. As an input, this
line has high impedance and is compatible with standard TTL
voltage levels. As an output, it is also TTL compatible and may
be used as a source of 1 rnA at 1.5 V to directly drive the base
of a Darlington transistor switch. This line is programmed by
the Peripheral Control Register.
The input pin CTG accepts an asynchronous TTL-compatible
signal which is used as a trigger or a clock gating function to the
Timer. The gating input is clocked into the HD6846 by the
Enable signal in the same manner as the previously discussed
clock inputs. That is, a CTG transition is recognized on the
fourth Enable pulse (provided setup and hold time requirement!
are met), and the "High" or "Low" levels of the CTG inpu1
must be stable for at least one system cloc~riod plus the sum
of setup and hold times. All references to CTG tra~sition in thi!
document relate to internal recognition of the input transition.
The CTG input of the timer directly affects the internal
16-bit counter. The operation of CTG is therefore independen1
of the + 8 prescaler selection.
•
•
FUNCTIONAL SELECT CIRCUITRY
•
I/O-Timer Select Circuitry
•
Peripheral Control (CP 2 )
Counter Timer Output (CTO)
The Counter Timer Output is software programmable by
selected bits in the timer/counter control register. The mode of
operation is dependent on the Timer control register, the gate
input, and the clock source. The output is TTL compatible.
•
CS o and CS 1 are user programmable. Any of the four binar}
combinations of CSo and CSl can be used to select the ROM,
Likewise, any other combination can be used to select thE
I/O-Timer. In addition, several address lines are used ru
qualifiers for the I/O-Timer. Specifically, A3 = A4 '= As =
logical "0". A6 can be programmed to a "1", "0", or don't care,
A, = As = A9 = AlO = don't care or one line only may be
programmed to a logical "1". Figure 14 outlines in diagram
matic form the available chip select options.
External Clock Input (CTC)
Input pin eTC will accept asynchronous TTL voltage level
signals to be used as a clock to decrement the Timer. The "High"
and "Low" levels of the external clock must be stable for at
least one system clock period plus the sum of the setup and
hold times for the inputs. The asynchronous clock rate can vary
from dc to the limit imposed by System E, setup, and hold
times.
The external clock input is clocked in by Enable pulses.
Three Enable periods are used to synchronize and process the
external clock. The fourth Enable pulse decrements the internal
counter. This does not affect the input frequency; it merely
creates a delay between a clock input transition and internal
recognition of that transition by the HD6846. All references to
•
Internal Addressing
Seven I/O Register locations within the HD6846 are
accessible to the MPU data bus. Selection of these registers i!
controlled by Ao , AI, and A2 (as shown in Table 1) provided
the I/O timer is selected. The combination status register i!
Read-only; all other Registers are Read and Write.
Input
E
ill Input
Recog.
Input
Output
~
,...---------1:1-......- - - '
either
here
.----\ I
I
or Here
196
J~
1-----1
--.J ____ J
~i~y~~
Jitter
-------------------------------------HD6846-------------------------------------
~--.. I/O·TIMER
SELECT
A 10
A9
As
0----0
0----0
A,
Q---{)
Figure 14 I/O-Timer Select Circuitry
combination of the chip select inputs.
Table 1 Internal Register Addresses
REGISTER SELECTED
Az
At
Ao
ROM Select
Combination Status Register
Peripheral Control Register
Data Direction Register
Peripheral Data Register
Combination Status Register
Timer Control Register
Timer MSB Register
Timer LSB Register
ROM Address
0
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
0
The active levels of CS o and CSt for ROM and I/O select are
a user programmable option. Either CS o or CSl may be programmed active "High" or active "Low", but different codes
must be used for ROM or I/O select. CSo and CSl are mask
programmed simultaneously with the ROM pattern. The ROM
Select Circuitry is shown in Figure 15.
x
x
x
1
1
1
1
Initialization
When the RES input has accepted. a "Low" signal, all
registers are initialized to the reset state. The data direction and
peripheral data registers are cleared. The Peripheral Control
Register is cleared except for bit 7 (the RES bit). This forces the
parallel port to the input mode with Interrupts disabled. To
remove the RES condition from the parallel port, a "0" must be
written into the Peripheral Control Register bit 7 (PCR7).
The counter latches are preset to their maximal count, the
Timer control register bits are reset to zero except for Bit 0
(TCRO is set), the counter output is cleared, and the counter
clock disabled. This state forces the timer counter to remain in
an inactive state. The combination status register is cleared of all
interrupt flags. During timer initialization, the reset bit (CCRO)
must be cleared.
Figure 15 ROM Select Circuitry
•
TIMER OPERATION
The Timer may be programmed to operate in modes which
fit a wide variety of applications. The device is fully bus
compatible with the HMCS6800 system, and is accessed by
Load and Store operations from the MPU.
In a typical application, the timer will be loaded by storing
two bytes of data into the counter latch. This data is then
transferred into the counter during a Counter Initialization
cycle. The counter decrements on each subsequent clock cycle
(which may be Enable or an external clock) until one of several
predetermined conditions causes it to halt or recycle. Thus the
timer is programmable, cyclic in nature, controllable by external
inputs or MPU program, and accessible to the MPU at any time.
ROM
The Mask Programmable ROM section is similar in operation
to other ROM products of the HMCS6800 Microprocessor
family. The ROM is organized as 2048 words of 8-bits to
provide read-only storage for a minimum microcomputer
system. The ROM is active when selected by the unique
197
-----------------------------------HD6846----------------------------------•
Counter Latch Initialization
The Timer consists of a 16-bit addressable counter and two
8-bit addressable latches. The function of the latches is to store
a binary equivalent of the desired count value minus one.
Counter initialization results in the transfer of the latch
contents of the counter. It should be noted that data transfer to
the counters is always accomplished via the latches. Thus, the
counter latches may be accurately described as a 16-bit
"counter initialization data" storage register.
In some modes of operation, the initialization of the latches
will cause simultaneous counter initialization (i.e. immediate
transfer of the new latch data into the counters). It is, therefore,
necessary to insure that all-16-bit of the latches are updated
simultaneously. Since the HD6846 data bus is 8-bit wide, a
temporary register (MSB Buffer Register) is provided for in the
Most Significant Byte of the desired latch data. This is a
"write-only" register selected via address lines Ao, A I , and A2 .
Data is transferred directly from the data bus to the MSB Buffer
when the chip is selected, R/W is "Low", and the timer MSB
register is selected (Ao = "0", Al =A2 = "1 ").
The lower 8-bit of the counter latch can also be referred to as
a "write-only" register. Data Bus information will be transferred
directly to the LSB of a counter latch when the chip is selected,
R/W is "Low" and the Timer LSB Register is selected (Ao =Al
= A2 = "1 "). Data from the MSB Buffet will automatically be
transferred into the Most Significant Byte of the counter latches
simultaneously with the transfer of the Data Bus information to
the Least Significant Byte of the Counter Latch. For brevity,
the conditions for this operation will be referred to henceforth
as a "Write Timer Latches Command."
The HD6846 has been designed to allow transfer of two
bytes of data into the counter latches from any source, provided
the MSB is transferred first. In many applications, the source of
data will be an HMCS6800 MPU. It should therefore be noted
that the 16-bit store operations of the HMCS6800 family
microprocessors (STS and STX) transfer data in the order
required by the HD6846. A Store Index Register instruction,
for example, results in the MSB of the index register being
transferred to the selected address, then the LSB of the index
register being written into the next higher location. Thus, either
the index register or stack pointer may be transferred direct]
into a selected counter latch with a single instruction.
A logic zero at the RES input also initializes the countc
latches. All latches will assume maximum count (65,535
values. It is important to note that an internal reset (Bit zero (
the Timer/Control Register Set) has no effect on the countc
latches.
• Counter Initialization
Counter Initialization is defined as the transfer of data frol
the latches to the counter with attendant clearing of th
Individual Interrupt Flag associated with the counter. Count~
Initialization always occurs when a reset condition (exterm
RES = "0" or TCRO = "1") is recognized. It can also occ\:
(dependent on The Timer Mode) with a Write Timer Latch~
command or recognition of a negative transition of the CT4
input.
Counter recycling or reinitialization occurs when a cloc
input is recognized after the counter has reached an all-zer
state. In this case, data is transferred from the Latches to th
Counter, but the Interrupt Flag is unaffected.
•
Timer Control Register
The Timer Control register (see Table 2) in the HD6846 il
used to modify timer operation to suit a variety of application:
The Timer Control Register has a unique address space (Ao'
"1, Al = "0", A2 = "J ") and therefore may be written into a
any time. The least sigruficant bit of the Control Register is use
as an Internal Reset bit. When this bit is a logic zero, all timel
are allowed to operate in the modes prescribed by the rernainin
bits of the timer control register.
Writing" 1" into Timer Control Register Bit 0 (TCRO) cause
the counter to be preset with the conents of the counter latchel
all counter clocks are disabled, and the timer output an
interrupt flag (Status Register) are reset. The Counter Latch an
Timer/Control Register are undisturbed by an Internal Rese
and may be written into regardless of the state of TCRO.
Timer Control Register Bit 1 (TCRl) is used to select th
clock source. When TCRI = "0", the external clock input CT4
is selected, and when TCRI ="1 ", the timer uses Enable.
Table 2 Format for Timer/Counter Control Register
CONTROL
REGISTER
BIT
STATE
TCRO
0
TCRl
0
BIT DEFINITION
Internal Reset
Timer in Preset State
1
Clock Source
0
1
TCR3
TCR4
TCR5
TCR6
TCR7
x
x
x
0
Timer uses External Clock (CTC)
Timer uses ¢J2 System Clock
1
TCR2
STATE DEFINITION
Timer Enabled
+8 Prescaler
Enabler
Operating Mode
Selection
Clock is not Prescaled
Clock is prescaled by +8 Counter
See Table 3
1
Timer Interrupt
Enable
I RQ Enabled from Timer
I RQ Masked from Timer
0
Timer Output Enable
Counter Output (CTO) Set "LOW"
Counter Output Enabled
1
198
------------------------------------- HD6846------------------------------------Table 3 Counter/Timer Operation Modes
Mode
TCR3 TCR4 TCR5
Continuous
Mode
0
0
0
Cascaded Single
Shot Mode
Normal Single
Shot Mode
Frequency Com·
parison Mode
Pulse Width
Comparison
Mode
Counter
Initialization
"CI"
Counter Enable
"CE"
Interrupt Flag
Counter Clock
"CC"
Set
Clear
(G=Low)' R
CE' C
TO
RS-RT orCI
(G=Low) • R
CE' C
TO
RS-RT or CI
G.j.. +W+R
1
0
0
0
0
1
G.j.. +W+R
R
CE'C
TO
RS-RT or CI
0
1
1
G.j.. +R
R
CE' C
TO
RS-RT or CI
1
0
0
1
0
1
1
1
1
1
G
t
+R
CE set=G .j..·W· R·T
CE reset=W+R+1
CE' C
G.j.. before RS-RTorCI
orW
TO
G.j..·T+R
CE set=G.j..·W·'R·T
CE reset=W+R+1
CE' C
G.j.. before
TO
RS-RT orCI
orW
0
G.j..·T+R
CE set=G.j..·W· R' T·G
CE reset=W+R+I+(G=High)
CE' C
Gt before
TO
RS-RT or CI
orW
1
G .j..·I+R
CE set=G.j.. 'W' R·T·G
CE reset=W+R+I+(G=High)
CE' C
Gt
RS-RT or CI
orW
CE+TOF·CE)·G.j...j
+R
R = External RES or Internal Reset TCRO
W = Write Timer Latch
I = I~rupt Flag
before
TO
TO = Counter Time Out
~=CTG
C = Clock selected in the internal register
G .j, = Negative transition of CTG signal
G t = Positive transistion of CTG signal
RS-RT = Read Operation of Timer Counter after the read of Status Register
(Normal operation to clear the interrupt)
CI = Counter Initialization (I nternal Signal)
TOF = Time Out Flag (Set by a'TO, Reset by CIl
Timer Control Register Bit 2 (TCR2) enables the -:- 8
prescaler (TCR2 = "1 "). In this mode, the clock frequency is
divided by eight before being applied to the counter. When
TCR2 ="0" Enable is applied directly to the counter.
TCR3, 4, 5 select the Timer Operating Mode, and are
discussed in the next section.
Timer Control Register Bit 6 (TCR6) is used to mask or
enable the Timer Interrupt Request. When TCR6 = ''0'', the
Interrupt Flag is masked from the timer. When TCR6 = "1", the
Interrupt Flag is enabled into Bit 7 of the Composite Status
Register (Composite IRQ Bit), which appears on the IRQ
output pin.
Timer Control Register Bit Seven (TCR7) has a special
function when the timer is in the Cascaded Sinl!1e Shot mode.
(This function is explained in detail in the section describing the
mode.) In all other modes, TCR7 merely acts as an output
enable bit. If TCR7 = "0", the Counter Timer Output (' :TO) is
forced "Low". Writing a logic one into TCR7 enables C1 O.
•
CONTINUOUS MODE
(TCR3=O, TCR7=1, TCR5=O)
~~~~'i~~
TCR4
0
1
INITIALIZATION/OUTPUT WAVEFORMS
Counter
Initialization
~.j, +W+R
G.j..+R
CTO
Ie-'N+' J m-'I~'N+ll m~ I~IN+' J
II
r
I
TO*
TO*
I
to
'T1
~H
VOL
TO*
~ .j, = Negative Transition CTG Input.
W = Write Timer Latches Command.
R = Timer Reset (TCRO=1 or External REs=O)
N = 16 Bit Number in Counter Latch.
T = Period of Clock Input to Counter.
to = Counter Initialization Cycle.
TO = Counter Time Out (All Zero Condition,)
* Point at which an interrupt may occur.
Timer Operating Modes
The HD6846 has been designed to operate effectively in a
wide variety of applications. This is accomplished by using three
bits of the control register (TCR3, TCR4, and TCRS) to define
different operating modes of the Timer, outlined in Table 3.
•
Table 4 Continuous Operating Modes
Continuous Operating Mode (TCR3 = 0, TCR5 = 0)
The timer may be programmed to operate in a continuous
counting mode by writing zeros into bits 3 and 5 of the timer
control register. Assuming that the timer output is enabled
(TCR7 = "1 "), a square wave will be generated at the Timer
Output CTO (See Table 4).
Either a Timer Reset (TCRO = "I" or External RES = "0")
condition or internal recognition of a negative transition of the
CTG input results in Counter Initialization. A Write Timer
Latches command can be selected as a Counter Initialization
Signal by clearing TCR4.
The discussion of the Continuous Mode has assumed the
application requires an output signal. It should be noted the
Timer operates in the same manner with the output disabled
(TCR7 = "0"). A Read Timer Counter command is valid
regardless of the state of TCR7.
199
------------------------------------HD6846-----------------------------------•
•
Normal Single-8hot Timer Mode (TCR3 = 0, TCR4 = 1,
TCR5 =1)
Cascaded Single-shot Mode (TCR3=0, TCR4=0, TCRS=l)
This mode is identical to the single-shot mode with two
exceptions. First, the output waveform does not return to a
"Low" level and remain "Low" after timeout. Instead, the output level remains at its initialized level until it is re-programmed
and changed by timeout. The output level may be changed at
any timeout or may have any number of timeouts between
changes.
The second difference is the method used to change the
output level. Timer Control Register Bit 7 (TCR7) has a special
function in this mode. The timer output (CTO) is equal to
TCR7 clocked by timeout. At every timeout, the content of
TCR7 is clocked to and held at the CTO output. Thus, output
pulses of length greater than one timer cycle can be generated
by cascading timer cycles and counting timeouts with a software
program (See Figure 16).
An interrupt is generated at each timeout. To cascade timer
cycles, the MPU would need an interrupt routine to: 1) count
each timeout and determine when to change TCR7: 2) write
into TCR7 the state corresponding to the next desired state of
the output waveform (only necessary during the last timer cycle
before the output is to change state): and 3) clear the interrupt
flag by reading the combination status register followed by
Read Timer MSB. It is also possible, if desired, to change the
length of the timer cycle by reinitializing the timer latches. This
allows more flexibility for obtaining desired times.
1bis mode is identical to the Continuous Mode with two
exceptions. The first of these is obvious from the name - the
output returns to a "Low" level after the initial Time Out and
remains "Low" until another Counter Initialization cycle occurs.
The output waveform (CTO) is shown in Figure 16.
As indicated in Figure 16, the internal counting mechanism
remains cyclical in the Single-Shot Mode. Each Time Out of the
counter results in the setting of an Individual Interrupt Flag and
re-initialization of the counter.
The second major difference between the Single-Shot and
Continuous modes is that the internal counter enable is not
dependent on the CTG input level remaining in the "Low" state
for the Single-Shot mode. Aside from these differences, the two
modes are identical.
to
CTO
(N +')
(A) NORMAL SINGLE-SHOT MODE OUTPUT WAVEFORM
TCR7 = Output
After Timeout
•
Time Interval Modes (TCR3 = 1)
The Time Interval Modes are provided for applications
requiring more flexibility of interrupt generation and Counter
Initialization. The Interrupt Flag is set in these modes as a
function of both Counter Time Out and transitions of the CTG
input. Counter Initialization is also affected by Interrupt Flag
status. The output signal is not defined in any of these modes.
Other features of the Time Interval Modes are Outlined in Table
5.
eTO
(B) CASCADED SINGLE-SHOT MODE OUTPUT WAVEFORM
, = Write a "'" into TCR7
0= Write a "0" into TCR7
*Point at which an interrupt may occur.
•
(NOTE) All time intervals shown above assume the Gate (CTG)
and Clock (CTC) signals are synchronized to Enable with the
specified setup and hold time requirements.
Frequency Comparison Mode (TCR3 = 1, TCR4 = 0)
The timer within the HD6846 may be programmed to
compare the perio~ a pulse (giving the frequency after
calculations) at the CTG input with the time period required for
Counter Time Out. A negative transition of the CTG input
enables the counter and starts a Counter Initialization cycle provided that other conditions as noted in Table 3 are satisfied.
The counter decrements on each clock signal recognized during
or after Counter Initialization until an Interrupt is generated, a
Figure 16 Single-Shot Modes
Table 5 Time Interval Modes
TCR3 = 1
APPLICATION
CONDITION FOR SETTING INDIVIDUAL INTERRUPT FLAG
0
Frequency
Comparison
Interrupt Generated if CTG Input Period (1 IF)
is Less Than Counter TimeOut (TO).
0
1
Frequency
Comparison
Interrupt Generated if CTG Input Period (1 IF)
is Greater Than Counter Time Out (TO).
1
0
Pulse Width
Comparison
Interrupt Generated if CTG Input "Down Time"
is Less Than Counter Time Out (TO).
1
1
Pulse Width
Comparison
Interrupt Generated if CTG Input "Down Time"
is Greater Than Counter Time Out (TO).
TCR4
TCRS
0
200
------------------------------------HD6846-----------------------------------clearing CSRI and CSR2 are detailed in a later section. The
Timer Interrupt Flag (CSRO) is cleared under the following
conditions:
1) Timer Reset - Internal Reset Bit (TCRO) = "1" or External
RES = "0".
2) Any Counter Initialization condition.
3) A Write Timer Latches command if Time Interval modes
(TCR3 ="1") are being used.
4) A Read Timer Counter command, provided this is preceded
by a Read Composite Status Register while CSRO is set. This
latter condition prevents misSing an Interrupt Request
generated after reading the Status Register and prior to
reading the counter.
The remaining bits of the Composite Status Register
(CSR3"'CSR6) are unused. They default to a logic zero when
read.
Write Timer Latches command is issued, or a Timer Reset
condition occurs. It can be seen from Table 3 that an interrupt
condition will be generated if TCR5 ="0" and the period of the
pulse (single pulse or measured separately repetative pulses) at
the CTG input is less than the Counter Time Out period. If
TCR5 ="1", an interrupt is generated if the reverse is true.
Assume now with TCR5 = "1" that a Counter Initialization
has occurred and that the CTG input has returned "Low" prior
to Counter Time Out. Since there is no Individual Interrupt Flag
generated, this automatically starts a new Counter Initialization
Cycle. The process will continue with frequency comparison
being performed on each CTG input cycle until the mode is
changed, or a cycle is determined to be above the predetermined
limit.
Pulse Width Comparison Mode (TCR3 = 1, TCR4 = 1)
This mode is similar to the Frequency Comparison Mode
except for the limiting factor being a positive, rather than
negative, transition of the CTG input. With TCR5 = "0", an
Individual Interr2!£!. Flag will be generated if the zero level pulse
applied to the CTG input is less than the time period required
for Counter Time Out. With TCR5 = "1", the interrupt is
generated when the reverse condition is true.
As can be seen in Table 3, a positive transition of the CTG
input disables the counter. With TCR5 = "0", it is therefore
possible to directly obtain the width of any pulse causing an
interrupt.
•
•
Composite Status Register
The Composite Status Register (CSR) is a read-only register
which is shared by the Timer and the Peripheral Data Port of
the HD6846. Three individual interrupt flags in -the register-are
set directly via the appropriate conditions in the timer or
peripheral port. The composite interrupt flag - and the IRQ
Output - respond to these individual interrupts only if
corresponding enable bits are set in the appropriate Control
Registers. (See Figure 17.) The sequence of assertion is not
detected. Setting TCR6 while CSRO is "High" will cause CSR7
to be set, for example.
The Composite Interrupt Flag (CSR7) is clear only if all
enabled Individual Interrupt Flags are clear. The conditions for
•
1/0 OPERATION
•
Parallel Peripheral Port
The peripheral port of the HD6846 contains 8 Peripher~
Data lines (Po-P,), two Peripheral Control lines (CPt and CP l ),
a Data Direction Register, a Peripheral Data Register, and a
Peripheral Control Register. The port also directly affects two
bits (CSRI and CSR2) of the Composite Status Register.
The Peripheral Port is similar to the "B" side of a PIA
(HD46821) with the following exceptions:
1) All registers are directly accessible in the HD6846 Data
Direction and Peripheral Data in the HD6821 are located at
the same address, with Bit Two of the Control Register used
for register sele~ti9n.
_
__
2) Peripheral Control Register Bit Two (PRC2) of the HD6846
is used to select an optional input latch function. This option
is not available with HD6821 PIA's.
3) Interrupt Flags are located in the HD6846 composite status
register rather than Bits 6 and 7 of the Control Register as
used in the HD6821.
4) Interrupt Flags are cleared in the HD6821 by reading data
from the Peripheral Data Register. HD6846 Interrupt Flags
are cleared by either reading or writing to the Peripheral Data
Register - provided that this sequence is followed a) Flag
Set, b) Read Composite Status Register, c) Read/Write
Peripheral Data Register is followed.
IRQ
(NOTE) Bits CSR3 - CSR6 are not used.
Figure 17 Composite Status Register & Associated Logic
201
------------------------------------HD6846-----------------------------------5) Bit 6 of the HD6846 Peripheral Control Register is not
used. Bit 7 (PeR7) is an Internal Reset Bit not available on
the HD6821.
6) The Peripheral Data lines (and CP2 ) of the HD6846 features
internal current limiting which allows them to directly drive
the base of Darlington NPN transistors.
•
Data Direction Register
The MPU can write directly to this eight-bit register to
configure the Peripheral Data lines as either inputs or outputs.
A particular bit within the register (DDRn) is used to control
the corresponding Peripheral Data line (Pn). With DDRn = "0",
Pn becomes an input; if DDRn = "1", Pn is an output. As an
example, writing Hex $OF into the Data Direction Register
results in Po thru P 3 becoming outputs and P 4 thru P 7 being
inputs. Hex $55 in the Data Direction Register results in alternate outputs and inputs at the parallel port.
•
Peripheral Port Reset (PCR7)
Bit 7 of the Peripheral Control Register (PeR7) may be uSed
to initialize the peripheral section of the HD6846. When this
bit is set "High", the' peripheral data register, the peripheral data
direction register, and the interrupt flags associated with the
peripheral port (CSR1 & CSR2) are all cleared. Other bits in the
peripheral control register are not affected by PCR7. _
PeR7 is set by either a logic zero at the External RES input
or under program control by writing a "1" into' the location. In
any case, PeR7 may be cleared only by writing a zero into the
location while RES is "High". The bit must be cleared to activate the port.
•
Control of CPI Peripheral Control Line
CPI may be used an interrupt reguest to the HD6846, as a
strobe to allow latching of input data" or both. In any case, the
input can be programmed to be activated by either a positive or
negative transition of the signal. Thes options are selected via
Control Register Bits PCRO, RCR1 & PCR2.
Control Register Bit 0 (PCRO) is used to enable the interrupt
transfer circuitry of the HD6846. Regardless of the state of
PCRO, and active transition of CPI causes the Composite Status
Register Bit One (CSR1) to be set. if PCRO ="1", this interrupt
will be reflected in the Composite Interrupt Flag (CSR7), and
thus at the IRQ output. CSR1 is cleared by a Peripheral Port
Reset condition or by either reading or writing to the peripheral
data register after the Composite Status Register is read. The
latter alternative is conditional - CSR1 must have been a logic
one when the Composite Status Register was lart read. This precludes inadvertent clearing of interrupt flags generated between
the time the Status Register is read and the manipulation of
peripheral data.
Control Register Bit One (PeRl) is used to select the edge
which activates. CP I. When PCRI = "0", CP I is active on
negative transitions ("High" to "Low"). "Low" to "High"
transitions are sensed by CP I when PCR1 ="1".
•
Peripheral Data Register
This eight-bit register is used for transferring data between
the peripheral data port and the MPU. Any bit corresponding to
an output line will be used to drive the output buffer associated
with that line. Data in these output bits is normally provided by
an MPU Write function. (Input bits - those associated with
input lines - are unchanged by a Write Command.) Any input
bit will reflect the state of the associated input line if the input
latch function is deselected. If the Control Register is programmed to provide input latching, the input bit will retain the
state at the time CP I was activated until the Peripheral Data
Register is read by the MPU.
•
Peripheral Control Register
This eight-bit register is used to control the reset function as
well as for selection of optional functions of the two peripheral
control lines (CP I and CP2 ). The Peripheral Control Register
functions are outlined in Table 6.
Table 6 Peripheral Control Register Format (Expanded)
l
PCR7
I
PCR6
I
PCR5
I
PCR4
I
PCR3
PCR2
I
PCR1
I 0=
CP2 DIRECTION CONTROL
CP2 Is INPUT
l
I
o=
NORMAL OPERATION
1 = RESET CONDITION (CLEARS PERIPHERAL
DATA & DATA DIRECTION REG + CSR1 & CSR2)
l
CP
I
=
I
ACTIVE EDGE SELECT
(.J.) EDGE
POSITIVE (t) EDGE
o =2 NEGATIVE
1
PCR4
I
II
PCR3
I
1
1 = CPt INT. ENABLED
o=
~--------------------------
I
I
CPt ACTIVE EDGE SELECT
NEGATIVE (.J.) EDGE
1 = POSITIVE (t) EDGE
RESET (SET BY EXT. RES = 0 OR WRITING
ONE INTO LOCATION; CLEARED BY
WRITING ZERO TO THIS LOCATION)
CP2 IS INPUT(PCR5 = 0)
PCRO
I 0=
CPI INT. ENABLE
CPI INT. MASKED
1 = CP2 Is OUTPUT
I
I
I
I
CP2 INT. ENABLEj
CP2 INT. MASKED
1 = CP z INT. ENABLED
o=
202
PCR3
0
0
0
1
1
I
CPI INPUT LATCH CONTROL
0= INPUT DATA NOT LATCHED
1 = INPUT DATA LATCHED ON ACTIVE CPI
PCR4
OOR 1
CP2 IS OUTPUT (PCR5 = 1)
INTERRUPT ACKNOWLEDGE
INPUT/OUTPUT ACKNOWLEDGE
PROGRAMMABLE OUTPUT
(CP 2 REFLECTS DATA
WRITTEN INTO PCR3)
I
I
------------------------------------HD6846-----------------------------------In addition to its use as an interrupt input, CP 1 can be used
as a strobe to capture input data in an internal latch. This option
is selected by writing a one into Peripheral Control Register Bit
Two (PCR2). In operating, the data at the pins designated by
the Data Direction Register as inputs will be captured by an
active transition of CP 1. An MPU Read of the Peripheral Data
Register will result in the captured data being transferred to the
MPU - and it also releases the latch to allow capture of new
data. Note that successive active transitions with no Read
Peripheral Data Command between does not update the input
latch. Also, it should be noted that use of the input latch
function (which can be deselected by writing a zero into PCR2)
has no effect on output data. It also does not affect Interrupt
function of CP 1 •
•
manner as those lines selected as outputs by the Data Direction
Register.
The handshaking mode (PCRS = "1", PCR4 = "0") allows
CP 2 to perform one of two functions as selected by PCR3. With
PCR3 = "I", CP2 will go "Low" on the first Enable positive
transition after a Read or Write to the Peripheral Data Register.
This Input/Output Acknowledge signal is released (returns
"High") on the next positive transition of the Enable signal.
In the Interrupt Acknowledge mode (PCRS = "1", PCR4 =
PCR3 = "0"), CP 2 is set when CSRI is set by an active
transition of CP 1. It is released (goes "Low") on the first
positive transition of Enable after CSRI has been cleared via an
MPU Read or Write to the Peripheral Data Register. (Note that
the previously described conditions for clearing CSRI still
apply.)
Control of CP2 Peripheral Control Line
•
CP z may be used as an input by writing a zero into PCRS. In
this configuration, CP 2 becomes a dual of CP 1 in regard to
generation of interrupts. An active transition (as selected by
PCR4) causes Bit Two of the Composite Status Register to be
set. PCR3 is then used to select whether the CP 2 transition is to
cause CSR7 to be set - and thereby cause IRQ to go "Low".
CP2 has no effect on the input latch function of the HD6846.
Writing a one into PCRS causes CP 2 to function as an
output. PCR4 then determines whether CP 2 is to be used in a
handshake or programmable output mode. With PCR4 = "1",
CP 2 will merely reflect the data written into PCR3. Since this
can readily be changed under program control, this mode allows
CP 2 to be a programmable output line in much the same
Restart Sequence
A typical restart sequence for the HD6846 will include
initialization of both the Peripheral Control & Data Direction
Registers of the parallel port. It is necessary to set up the
Peripheral Control Register first, since PCR7 = "0" is a
condition for writing data into the Data Direction Register. (A
logic zero at the external RES input automatically sets PCR7.)
•
Summary
The HD6846 has several optional modes of operation which
allow it to be used in a variety of applications. The following
tables are provided for reference in selecting these modes.
Table 7 HD6846 Internal
Register Addresses
R/W
A2
Al
Ao
REGISTER SELECTED
R
R/W
R/W
R/W
R
R/W
R/W
R/W
R
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
x
x
x
Combination Status Register
Peripheral Control Register
Data Direction Register
Peripheral Data Register
Combination Status Register
Timer Control Register
Timer MSB Register
Timer LSB Register
ROM Address
0
1
0
1
Table 8 Composite Status Register
CSR7
I
I
CSR3-CSR6 NOT USED DEFAULT
TO ZERO WHEN READ
I
COMPOSITE INTERRUPT FLAG
0= NO ENABLED INTERRUPT FLAG SET
1 = ONE OR MORE ENABLED INTERRUPT FLAGS SET*
CSR2
I
CSR1
I
CSRO
j
I
I
I 0=
CP, INTERRUPT FLAG III TIMER INTERRUPT FLAG I
o = NO INT REQ.
NO INT REQ
1 = INT REQUESTED
1 = INT REQUESTED
INVERSE OF THIS BIT APPEARS AT IRQ OUTPUT
CPI
*STATUS OF THIS BIT CAN BE EXPRESSED AS:
CSR7 = CSRO· TCR6 + CSR1· PCRO + CSR2· PCR3
I
203
INTERRUPT
NO INT REQ.
1 = INT REQUESTED
o=
I
------------------------------------HD6846-----------------------------------Table 9 Timer Control Register
I
TCR7
J
TCR6
TCR5
I
I
TCR3
TCR4
I
TCR2
l
IINTERRUPUT ENABLE
o = IRQ MASKED
1 = IRQ ENABLED
I
TCR1
TCRO
J
INTERNAL RESET
0= TIMER ENABLED
1 = INT REQUESTED
I
I oCLOCK
SOURCE
= EXTERNAL CLOCK (CTC)
TIMER OUTPUT ENABLE
OUTPUT DISABLED (LOW)
1 = OUTPUT ENABLED
o=
1 = INTERNAL CLOCK (41 2 )
--------------------------
I
FOR CASCADED SINGLE-SHOT
OUTPUT GOES LOW AT TIME OUT
1 = OUTPUT GOES HIGH AT TIME OUT
o=
+ 8 PRESCALE ENABLE
o = CLOCK NOT PRESCALED
1 = CLOCK PRESCALED (+ 8)
TCR3
TCR4
TCR5
0
0
0
CONTINUOUS
CTG'(' + W + R
TO
0
0
1
CASCADED SINGLE SHOT
CTG.(, + W + R
TO
0
1
0
CONTINUOUS
CTG .(, + R
TO
0
1
1
NORMAL SINGLE SHOT
CTG .(, + R
TO
1
0
0
1
0
1
1
1
0
1
1
1
R
W
TO
CE
TIME OPERATING MODE
COUNTER INITIALIZATION
FREQUENCY COMPARISON
PULSE WIDTH COMPARISON
CTG .(,.
r· (CE + TOF·CE) + R
'('·1 + R
CTG '('·1 + R
CTG'(' . 1 + R
CTG
= RESET CONDITION
= WRITE TIMER LATCHES
= COUNTER TIME OUT
= COUNTER ENABLE
•
I
INTERRUPT FLAG SET
CTG .(, BEFORE TO
TO
BEFORE CTG
CTG t BEFORE TO
TO
BEFORE CTG t
CTG'(' = NEG TRANSISTION OF PIN 17
CTGt = POS TRANSITION OF PIN 17
1 = INTERRUPT FLAG (CSRO) = 0
Table 10 Peripheral Control Register
l
I
PCR7
I
PCR6
I
PCR5
I
PCR4
I
PCR3
J
PCR2
I
I oCP=z CP
DIRECTION CONTROL
Is INPUT
PCR1
I
z
1 = CPz Is OUTPUT
RESET (SET BY EXT. RES = 0 OR WRITING
ONE INTO LOCATION; CLEARED BY
WRITING ZERO TO THIS LOCATION)
I
I
PCRO
I
I
CPt INT. ENABLE
CPt INT. MASKED
1 = CPt INT. ENABLED
o=
CP1 ACTIVE EDGE SELECT
0= NEGATIVE (.(,) EDGE
1 = POSITIVE (t) EDGE
1-------- - - - - - - - - - - - - - - - - - - - - - - 0= NORMAL OPERATION
1 = RESET CONDITION (CLEARS PERIPHERAL
DATA & DATA DIRECTION REG + CSR1 & CSR2)
I
I
I
CPz' IS INPUT (PCR5 = 0)
I
I
j
PCR4
I
CP ACTIVE EDGE SELECT
(.(,) EDGE
1 = POSITIVE (t) EDGE
o =z NEGATIVE
PCR3
I
I
I
CP 2 INT. ENABLE
CP z INT. MASKED
1 = CP z INT. ENABLED
o=
I
204
I
CPt INPUT LATCH CONTROL
INPUT DATA NOT LATCHED
1 = INPUT DATA LATCHED ON ACTIVE CPt
o=
PCR4
0
PCR3
0
0
1
1
OOR 1
I
CP z IS OUTPUT (PCR5 = 1)
INTERRUPT ACKNOWLEDGE
INPUT/OUTPUT ACKNOWLEDGE
PROGRAMMABLE OUTPUT
(CP z REFLECTS DATA
WRITTEN INTO PCR3)
------------------------------------HD6846-----------------------------------• CUSTOM PROGRAMMING
shown in Figure 18 and Figure 19.
Information for custom memory content may be sent to
IDTACHI in one of two forms (shown in order of preference):
1) Paper tape output of the HMCS6800 Load Module Format
or of the BNPF Format
2) Hexadecimal coding using IBM Punch Cards
By the programming of a single photomask for the
HD6846, the customer may specify the content of the
memory and the method of enabling the outputs.
Information on the general options of the HD6846 should
be submitted on an Organizational Data form such as that
ORGANIZATIONAL DATA
HD46846 COMBINATION ROM-I/O-TIMER
Customer:
Hitachi Use Only:
Company
Part No.
Quote:
Originator
Part No.:
Specif. No.:
Phone No.
Enable Options: (ROM ENABLE MUST DIFFER FROM I/O-TIMER)
CHECK ONE COLUMN ONLY
1
CS o
cS l
0
DD
DO
ROM SECTION
1
1
I/O-TIMER SELECT
0
0 0
D D
A 10
A6
1
0
x
DDD
x'
1
x
x
x
1
x
x
x=
x
x
x
1
x
NOT USED
A?
x
x
X
x
1
I
DATE
SECTION
ENGINEER
TYPE NO. OF ROM
CUSTOMERS PIN (if you need)
I I I I I I I I I I I I
DATA FORMAT
2.
HMCS6S00 load module format
BNPF format
total bytes of data (decimal)
coding media
01.
paper tape
02.
1MB SO column card
initial ROM address (decimal)
parity (for paper tape)
01. even
o
2. odd
0
3. none
total number of cards
designed
for HITACHI reference only
ref. No.
~
mask ROM No.
approved
processed data
approved data
Figure 19
Confirmation sheet of specification for HD6846 series ROM
205,
OSO.SV
Ag
Figure 18 Format for Programming General Options
1.
x
Aa
I/O-TIMER SECTION
COMPANY
~2.0V
x
------------------------------------HD6846-----------------------------------• PAPER TAPE
1) Anyone inch width tape usually available in market can be
used but tape in black color is recommended.
2) Both leader and trailer have more than 600 frames.
(Example)
ooooooooooooooooooooooooooooooooo~oooooo
trailer
more than
600 frames
data
leader
more than
600 frames
3) One me data of each chip shall be contained in one reel of
paper tape. One me data shall not be divided into more than
two reels.
4) Parity
Parity shall be indicated in "Confirmation sheet of specifica·
tion". Parity forms are grouped;
(1) With parity
EVEN or ODD
(2) Without parity
5) 8·bit ASCII code shall be used.
contents
column
Free format of data column
1 to 71
72
Blank
Sequential card number, not free format.
Least significant digit of decimal sequential
number is located in column 80.
No alphabet letters.
Any sequential number more than 1 can be used •
73 to 80
• CARD
,1) Use IBM 80 column card.
2) Use EBCDIC code.
3) Card format is as follows;
4) Total number of cards shall be written in "Confirmation
sheet of specification".
• DATA FORMAT
•
HMCS6800 LOAD MODULE FORMAT
This is object format obtained from HMCS6800 assembler.
1) 8·bit code is divided into upper and lower 4 bits and
transformed into hexadecimal number.
(Example) Binary number if 11000010 is transformed as follows.
lower
upper
0, 0 6
1
\
1
Os
D.
03
O2
0 1 Do
0
0
,0
1
1
.
I
bit weight
(corresponding to
ROM output)
0
I
6
C
2) Load module structure of paper tape is shown as an example.
<'~"
50
51
51
206
1((
5,
51
------------------------------------HD6846-----------------------------------SO is the header record, Sl is data record and S9 is end of me
record. Each data record corresponds to each ROM data as
shown below. Continuous memory address shall be devided into
several records due to limitation of maximum frame number (70
frames = 35 bytes) in one record.
SO, Sl or S9 is distinguished by CC following start of the
record S.
ROM
51
Address
51
51
51
}
""."NUUSI
00
(CR)
OA
(LF)
00
00
00
frame
00
S: start of the
53
record
CC: type of
CC
1
-
I--
70 frames
max
Byte oount Hexa Oicimal
(2 frames = 1 byte)
Start address
of data in this
record
I--
-
)
I--
-
}""
I--
-
Check
sum
I
.
I--
-
v---Check sum is complement of 1 for sum of each S-bit.
207
}
-
I--
Byte
count
record
(0.10r9)
}""
HD6846
3) Example of load module format
1
2
3
4
5
6
7
8
9
10
frame
start of record
type of record
byte count
start address of
data in this
record
data
data
data
n
check
sum
CC=30
header
record
53
30
30
36
30
30
30
30
34
38
34
34
35
32
32
42
S
0
06
0000
48-H
44-0
52-R
28
(check sum)
CC=31
data
record
53
31
31
36
31
31
30
30
39
38
30
32
6a
38
Check sum of header record above is complement of 1 of (06
+ 00 + 00 + 48 + 44 + 52)16 i.e., 2B.
The start address of data record is incremented for each one
byte data, then is compared to the next address in data record
and is checked to be sequential or not.
When it is not sequential, hexadecimal 00 is ftlled as data for
that address automatically.
A example of type out of paper tape in HMCS6800 load
module format is shown below.
header record ... SOO6000048445228
data record ...... Sl13F0007EF5587EF7897EF AA 77EF9C07EF9C4 7E24
data record ...... S 112FO lOFA657EFA887EFAA07EF9OC7EFA24 7E06
.
end of file record .... S9030000FC
S
16
1100
98
CC=39
end of file
record
53
S
39
9
30
03
33
30
30
0000
30
30
46
FC (check sum)
43
02
A8
(check sum)
4) Four types of data of ROM code are able to be processed. In
any case, header record before data record is needed and so
as end of ftle record after data record.
(a) No vacancy in ROM
Data record is filled with full ROM record of one chip.
Therefore address is sequential. Initial ROM address in "Conftrmation sheet of speciftcation" is O.
(b) .Vacancy in former part of ROM
Desired initial address shall be filled in initial ROM address
column in "Conftrmation sheet of speciftcation". Data of 00 are
filled automatically for vacant address.
(c) Vacancy in the middle of ROM
Data of 00 are filled in for vacant address. Initial ROM
address for data I is 0 and desired initial address for data II shall
be descnbed in "Conftrmation sheet of speciftcation".
(d) Vacancy in later part of ROM
When end of ftle record is read out, data of 00 are filled in
thereafter.
ROM
vacancy
(filled with 00)
vacency
(filled with 00)
(a)
(c)
(b)
208
(d)
------------------------------------HD6846-----------------------------------(Example) Paper tape whose data record is S1141920B6FC .....
000
o
00
0
0
00000
0
0
OOOOOOOOOOOOOOOOOOO~OOOOO~~O~~~~~~OOOOOOOOOOOOOOOOOOOO000
o
00000000
0000000
o
5
0
0
0
0000
0
00000
00000
000
00000 0
2BFF44
14906C466
• BNPF format
1) Each word is expressed as BNPF slice which begins word
opening mark B, has 8 character bit contents shown by P or
Nand fmishes with end mark F.
(E xam p Ie) OF in hexadecimal code is expressed as shown below (paper tape).
00000
0000
0
0
00000000000000 0 0000000000000000000
0000
0000
0000000000
o
bit weight
2) Any contents between F of the fIrst slice and B of next slice
are disregarded.
3) Bit pattern (BNPF) slice for all ROM address shall be
indicated. Initial ROM address in "ConfIrmation sheet of
specification" is, therefore always 0 for BNPF.
B
shows beginning of the word
N
shows 0 of one bit data
P
shows 1 of one bit data
F
shows end of the word
Note 1) X can be used expect for P and N for indication of
word contents of BNPF slice. This X means that bit
can be either P or N (don't care). X shall be
determined by HITACHI for testing and shall be
Note 2)
Note 3)
209
informed to the customer in confIrmation table.
Expression of B*nF can be used for indicating that
the same contents of foregoing slice are applicable
from this word to following n words.
For example, when B*4F is indicated at 10th word
position, the contents of 9th word are repeated for
10, 11, 12 and 13th word.
(Content of X is not always repeated even in this
case.)
n is grater than 1 and less than fInal address of ROM.
When vacancy of ROM exists, combination of Note
I) and Note 2) is usefull.
-----------------------------------HD6846----------------------------------Customer
HITACHI
ROM code
Customers PIN
chip select &
other information
Choice
of Media
"Organizational Data"
"Specification Confirmation Sheet"
"ROM code"
or
same as
input
medium
information
Customer's
responsibilitY
HITACHI's
responsibi lity
Mask
making
report
Figure 20 Flow chart of Mask ROM Development
210
HD&850, H D & 8 A 5 0 - - - - - - - - ACIA (Asynchronous Communication Interface Adapter)
The HD6850 Asynchronous Communications Interface
Adapter provides the data formatting and control to interface
serial asynchronous data communications information to bus
organized systems such as the HMCS6800 Microprocessing Unit.
The bus interface of the HD6850 includes select, enable,
read/write, interrupt and bus interface logic to allow data
transfer over an 8-bit bi-directional data bus. The parallel data
of the bus system is serially transmitted and received by the
asynchronous data interface, with proper formatting and error
checking.
The functional configuration of the ACIA is programmed via
the data bus during system initialization. A programmable
Control Register provides variable word lengths, clock division
ratios, transm'it control, receive control, and interrupt control.
For peripheral or modem operation three control lines are
provided.
•
•
•
•
•
•
•
FEATURES
Serial/Parallel Conversion of Data
Eight and Nine·bit Transmission
Insertion and Deleting of Start and Stop Bit
Optional Even and Odd Parity
Parity, Overrun and Framing Error Checking
Peripheral/Modem Control Functions (Clear to Send
CTS, Request to Send RTS, Data Carier Detect DCD)
•
Optional
H D6850P, H D68A50P
(DP-24)
+ 1, + 16, and + 64 Clock Modes
•
• Up to 500kbps Transmission
• Programmable Control Register
• N-channel Silicon Gate Process
• Compatible with MC6850 and MC68A50
•
PIN· ARRANGEMENT
BLOCK DIAGRAM
Tx ClK 4
E
14
13
8
1---+ 6
~o
Tx
Data
11
24 CTS
D.
0,
0,
03
D.
Os
0,
0,
22
21
20
19
18
17
16
15
7
5
I--t-- 2
Rx elK
IRQ
~--......- - - - - 23 DCD
3
-----------1
RTS
(Top View)
Rx Data
?11
-------------------------------HD6850, HD68A50------------------------------• ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
Supply Voltage
Vee *
-0.3 - +7.0
V
Inpu'l: Voltage
Vin *
-0.3 - +7.0
Operating Temperature
Topr
Tstg
-20- +75
°c
-55 - +150
°c
Item
Storage Temperature
V
* With respect to Vss (SYSTEM GND)
(NOTE)
Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be
under recommended operating conditions. If these conditions are exceeded, it could affect reliability of LSI.
• RECOMMENDED OPERATING CONDITIONS
Symbol
Vee *
Item
Supply Voltage
min
typ
max
Unit
4.75
5
5.25
V
Input Voltage
V 1L *
V 1H *
-0.3
-
0.8
V
2.0
-
V
Operating Temperature
Topr
-20
25
Vee
75
°c
* With respect to Vss (SYSTEM GND)
• ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (Vcc=5V±5%, VSS=OV, Ta=-2o-+75°C, unless otherwise noted.)
Item
Symbol
Input "High" Voltage
All Inputs
Input "Low" Voltage
All Inputs
VIH
V 1L
Input Leakage Current
RAN,CSo,CS1,CSz,E
lin
0 0 ""0 7
ITS1
Three-State (Off State)
Input Current
0 0 -0 7
Output "High" Voltage
V OH
TxOata, RTS
min
typ*
max
Unit
2.0
-0.3
-
Vee
0.8
V
V in =o-5.25V
-
-
2.5
JlA
Vin =0.4-2.4V
-
-
10
JlA
IOH=-205JlA, Enable
Pulse Width ~ 25Jls
2.4
-
-
IOH=-100llA, Enable
Pulse Width ~ 25Jls
2.4
-
-
Test Condition
V
V
Output "Low" Voltage
All outputs
VOL
IOL =1.6mA,Enable
Pulse Width ~ 25Jls
-
-
0.4
V
Output Leakage Current
(Off State)
IRQ
I LOH
VoH =2.4V
-
-
10
JlA
300
525
mW
-
-
12.5
Power Oissipation
Po
0 0 -0 7
Input Capacitance
Output Capacitance
E, TxCLK, RxCLK,
RAN, RS, RxOata, CS o ,
CS 1, CS 2 , ~ OCO
RTS", TxOata
IRQ
Cin
Vin=OV, Ta =25°C,
f=1.0MHz
-
-
7.5
Cout
Vin=OV, Ta=25°C,
f=1.0MHz
-
-
5.0
212
10
pF
pF
--------------------------------HD6850, HD68A50------------------·-------------•
AC CHARACTERISTICS
1. TIMING OF DATA TRANSMISSION
Minimum Clock Pulse Width
Test
Condition
Symbol
Item
PW CL
PW CH
+16, +64 Modes
+16, +64 Modes
min
typ
-
500
-
800
-
1.0
Fig. 1
600
Fig. 2
600
max
Unit
-
ns
ns
t TOO
Fig.3
-
Receive Data Setup Time
+ 1 Mode
t ROSU
Fig.4
500
Receive Data Hold Time
+ 1 Mode
tROH
Fig. 5
500
-
-
ns
tlR
Fig. 6
-
1.2
J..Ls
tRTS
Fig. 6
-
-
1.0
J..Ls
-
1.0*
J..Ls
Clock Frequency
+1 Mode
fc
+16, +64 Modes
Clock-to-Data Delay for Transmitter
IRQ Release Time
RTS Delay Time
Rise Time and Fall Time
t r , tf
Except E
kHz
J..Ls
ns
-
* 1.0 IlS or 10% of the pulse width, whichever is smaller.
2. BUS TIMING CHARACTERISTICS
1) READ
Item
Symbol
Test
Condition
HD6850
min
typ
max
min
HD68A50
typ
max
Unit
Enable Cycle Time
t cycE
Fig.7
1.0
0.666
J..Ls
Fig. 7
0.45
25
0.28
-
-
PW EH
-
-
Enable "High" Pulse Width
25
J..Ls
Enable "Low" Pulse Width
PW EL
Fig.7
0.43
-
-
0.28
-
-
J..Ls
tAS
Fig.7
140
-
-
140
-
-
ns
320
-
ns
10
10
-
ns
-
-
220
-
25
-
-
25
ns
max
min
HD68A50
typ
max
Unit
Setup Time, Address and R/W valid
to Enable positive transition
Data Delay Time
tOOR
Fig.7
-
Data Hold Time
tH
Fig. 7'
10
Address Hold Time
tAH
Fig. 7
10
-
Rise and Fall Time for Enable
Input
tEr,tEf
Fig. 7
-
-
Symbol
Test
Condition
ns
2) WRITE
Item
min
HD6850
typ
tcycE
PW EH
Fig.8
1.0
-
-
0.666
-
-
J..Ls
Enable "High" Pulse Width
Fig.8
0.45
-
25
0.28
-
25
J..Ls
Enable Cycle Time
Enable "Low" Pulse Width
PW EL
Fig.8
0.43
-
-
0.28
-
-
J..Ls
Setup Time, Address and R/W
valid to Enable positive transition
tAS
Fig.8
140
-
-
140
-
-
ns
Data Setup Time
-
80
10
-
-
ns
10
ns
-
-
25
ns
tosw
Fig.8
195
Data Hold Time
tH
Fig. 8
10
-
Address Hold Time
tAH
Fig.8
10
-
-
Rise and Fall Time for Enable
Input
t Er, tEf
Fig.8
-
-
25
213
ns
------------------------------HD6850, HD68A50------------------------------
Tx elK
or
Rx elK
or
Rx elK
Figure 2 Clock Pulse Width, "High" State
Figure 1 Clock Pulse Width, " Low" State
tTDD~
Tx Data
__________-J.
2.4V
~.-~O~.4~V---------
Figure 4 Receive Data Setup Time (+1 Mode)
Figure 3 Transmit Data Output Delay
tlR-----1-
______J___
Figure 5 Receive Data Hold Time (+1 Mode)
22 . 44VV
Figure 6 RTS Delay and I RQ Release Time
Enable
RS, CS, R/W
Data Bus
Figure 7 Bus Read Timing Characteristics
(Read information from ACIA)
214
-------------------------------HD6850, HD68A50-------------------------------
Enable
Data Bus
Figure 8 Bus Write Timing Characteristics
(Write information into ACIA)
Load B
Load A
5.0V (Vee)
(Do -0 7 , RTS. Tx Data)
ORQ Only)
RL=2.4kn
Test point
Test Point O-~"""-""--1
C
~
5'OV
3kn
r~F
R
C = 130pF for 0 0 -0 7
= 30pF for RTS and Tx Data
All diodes are 1S2074 ® or Equiv.
R=11knforD o-D 7
= 24kn for RTS and Tx Data
Figure 9 Bus Timing Test Loads
START
BIT
06
Do
t----------CHARACTER TIME @ 10 CPS (11 BITS)
100 msec
Figure 10 110 Baud Serial ASCII Data Timing
215
PARITY
BIT
STOP STOP
BIT BIT
----------.-j
--------------------------------HD6850, HD68A50--------------------------------
START
BIT
PARITY STOP
BIT
BIT
Do
t--------CHARACTER TIME @ 15 & 30 CPS (10 BITS)--------1-f
(SEE TABLE BELOW)
BAUD RATE
150
300
15
30
BIT TIME (msecl
6.67
3.33
CHARACTER TIME (msec)
66.7
33.3
CHARACTERSfflEC
BIT TIME
=
_---'S=E=C'------_
BAUD RATE
Figure 11 150 & 300 Baud Serial ASCII Data Timing
MARK
I
I
START
I
D6
PARITY
STOP
STOP
NEXT
CHAR.
SPACE
Figure 12 Send a 7 Bit ASCII Char. "H" Even Parity
- 2 Stop Bits H = 48 16 = 10010002
• ACIA OPERATION
• Master Reset
• DATA OF ACIA
HD6850 is an interface adapter which controls transmission
and reception of Asynchronous serial data. Some examples of
serial data are shown in Figs. 10 - 12.
•
The master reset (CRO, CRt) should be set during system
initialization to insure the reset condition and prepare for
programming the ACIA functional configuration when the
communications channel is required. Control bits CR5 and CR6
should also be programmed to define the state of RTS whenever
master reset is utilized. After master resetting the ACIA, the
programmable Control Register can be set for a number of
options such as variable clock divider ratios, variable word
length, one or two stop bits, parity (even, odd, or none), etc.
INTERNAL STRUCTURE OF ACIA
HD6850(ACIA) provides the following; 8-bit Bi-directional
Data Buses (Do-D 7 ), Receive Data Input (Rx Data), Transmit
Data Output (Tx Data), three Chip Selects (CSo ,CS I ,CS;),
Register Select Input (RS), Two Control Input (Read/Write
(R/W), Enable(E», Interrupt Request Output(IRQ), Clear-toSend (rn) to control the modem, Request-to-Send (RTS),
Data Carrier Detect(DCD) and Clock Inputs(Tx CLK, Rx CLK)
used for synchronization of received and transmitted data. This
ACIA also provides four registers; Status Register, Control
Register, Receive Register and Transmit Register.
24-pin dual-in-line type package is used for the ACIA. Internal Structure of ACIA is illustrated in Fig. 13.
216
--------------------------------HD6850, HD68A50-------------------------------ACIA
r - - - - - - - - - - - - - - - - - - - - - - - - - - - - - --.,
--i
(~;to)
y+C5~ ~
I
TRANSMIT DATA REGISTER (TOR)
WRITE ONLY /
i
:w.,,,,
0, /
D.'
0./ 0./ 0./ 0, / 0./ 0./
}.~.~JJ/
JJ
SERIAL DATA OUT
T. Da.. ;
i
LINES (PARALLEL
TO SERIAL CONVERTER)
DATA
LINES
TO
OR
FROM
MPU
READ ONLY
CONTROL REGISTER (CR)
:
ifI r----r---l---r-- -r-rr-r
I
I
I
I
WRITE
ONLY
I
R.CLK
I
I
READ
ONLY
I
01
D:a
OJ
D.
Os
06
IRQ
UPT
INTjiu
TRANSMIT
CLOCK
I
-r-
I
0,
I
RECEIVE DATA REGISTER (RDR)
R/W
E
~~:;
ENABLE
r
RS
CTS
L_
~~g~~VE
R. Da ..
SERIAL DATA IN
Do
TxCLK
MPU
CS.
CS.
cs,
DcD
i~;:L ~
(AO)
REGISTER
~~%~M
~~~~T
CHIP SELECT
FROM MPU
~I~~~ESS
MPU
ADDRESS
LINE
RTS
J
~~:~EST
MODEM
DATA
g~~:6~R
FROM
MODEM
Figure 13 Internal Structure of ACIA
• Transmit
A typical transmitting sequence consists of reading the ACIA
Status Register .either as a result of an interrupt or in the
ACIA's tum in a polling sequence. A character may be written
into the Transmit Data Register if the status read operation has
indicated that the Transmit Data Register is empty. This
character is transferred to a Shift Register where it is serialized
and transmitted from the Transmit Data output preceded by a
start bit and followed by one or two stop bits. Internal parity
(odd or even) can be optionally added to the character and will
occur between the last data bit and the flrst stop bit. After the
flrst character is written in the Data Register, the Status
Register can be read again to check for a Transmit Data Register
Empty condition and current peripheral status. If the register is
empty, another character can be loaded for transmission even
though the flrst character is in the process of being transmitted
(because of double buffering). The second character will be
automatically transferred into the Shift Register when the flrst
character transmission is completed. This sequence continues
until all the characters have been transmitted .
the detection of the leading mark-space transition of the start
bit. False start bit delection capability insures that a full half bit
of a start bit has been received before the internal clock is
synchronized to the bit time. As a character is being received,
parity (odd or even) will be checked and the error indication
will be available in the Status Register along with framing error,
overrun error, and Receive Data Register full. In a typical
receiving sequence, the Status Register is read to determine if a
character has been received from a peripheral. If the Receiver
Data Register is full, the character is placed on the 8-bit ACIA
bus when a Read Data command is received from the MPU.
When parity has been selected for an 8-bit word (7 bits plus
parity), the receiver strip the parity bit (07="0") so that data
alone is transferred to the MPU. This feature reduces MPU
programming. The Status Register can continue to be read again
to determine when another character is available in the Receive
Data Register. The receiver is also double buffered so that a
characttr can be read from the data register as another character
is being received in the Shift register. The above sequence continues until all characters have been received.
• Receive
Data is received from a peripheral by means of the Receive
Data input. A divide-by-one clock ratio is provided for an
externally sync~ronized clock (to its data) while the divide-by16 and 64 ratios are provided for internal synchronization. Bit
synchronization in the divide-by-16 and 64 modes is initiated by
• ACIA INTERNAL REGISTERS
The ACIA provides four registers; Transmit Data Register
(TDR), Receive Data Register(RDR), Control Register(CR) and
Status Register(SR). The content of each of the registers is
summarized in Table 1.
217
-------------------------------HD6850, HD68A50------------------------------Table 1 Definition of ACIA Register Contents
Buffer
Address
Data Bus
*
**
***
****
****
RS=1 • R/W=O
RS=1 • R/W=1
RS=O· R/W=O
RS=O· R/W=1
Transmit Data
Register
Receiver Data
Register
Control Register
Status Register
(Write Only)
(Read Only)
(Read Only)
0
Data Bit 0*
Data Bit 0
1
Data Bit 1
Data Bit 1
Counter Divide
Select ·(CR1)
Tx Data Reg. Empty
(TORE)
2
Data Bit 2
Data Bit 2
Word Select 1
(CR2)
Data Carrier Detect
(DCD)
3
Data Bit 3
Data Bit 3
Word Select 2
(CR3)
Clear to Send
(CTS)
4
Data Bit 4
Data Bit 4
Word Select 3
(CR4)
Framing Error
(FE)
5
Data Bit 5
Data Bit 5
Tx Control 1
(CR5)
Overrun
(OVRN)
6
Data Bit 6
Data Bit 6
Parity Error
(PE)
7
Data Bit 7***
Data Bit 7**
Tx Control 2
(CR6)
Rx Interrupt Enable
(CR7)
Rx Data Reg. Full
(RDRF)
Interrupt Request
(IRQ)
Leading bit = LSB = Bit 0
Data bit will be zero in 7-bit plus parity modes.
Data bit is "don't care" in 7-bit plus parity modes.
1 ... "High" level,O ... "Low" level
interrupt enables, and the Request-to-Send (RTS) peripheral/
modem control output.
•
Transmit Data Register (TOR)
Data is written in the Transmit Data Register during the
negative transition of the enable (E) when the ACIAhas been
addressed and RS· R/W is selected. Writing data into the
register causes the Transmit Data Register Empty bit in the
Status Register to go "0". Data can then be transmitted. If the
transmitter is idling and no character is being transmitted, then
the transfer will take place within one bit time of the trailing
edge of the Write command. If a character is being transmitted,
the new data character will commence as soon as the previous
character is complete. The transfer of data causes the Transmit
Data Register Empty (TDRE) bit to indicate empty.
Counter Divide Select Bits (CRO and CR 1)
The Counter Divide Select Bits (CRO and CR1) determine
the divide ratios utilized in both the transmitter and receiver
section of the ACIA. Additionally, these bits are used to provide
a master reset for the ACIA which clears the Status Register
(except for external conditions on CTS and DCD) and initializes
both the receiver and transmitter. Master reset does not affect
other Control Register bits. Note that after power-on or a power
fail/restart, these bits must be set "1" to reset the ACIA. Mter
resetting, the clock divide ratio may be selected. These counter
select bits provide for the following clock divide ratios:
•
Receive Data Register (RDR)
Data is automatically transferred to the empty Receive Data
Register (RDR) from the receiver deserializer (a shift register)
upon receiving a complete character. This event causes the
Receive Data Register Full bit (RDRF) on the status buffer to
go "1" (full). Data may then be read through the bus by addressing the ACIA and R/W "High" when the ACIA is enabled.
The non-destructive read cycle causes the RDRF bit to be
cleared to empty although the data is retained in the RDR. The
status is maintained by RDRF as to whether or not the data
is current. When the Receive Data Register is full, the automatic
transfer of data from the Receiver Shift Register to the Data
Register is inhibited and the RDR contents remain valid with its
current status stored in the Status Register.
•
(Write Only)
Counter Divide
Select (CRO)
Table 2 Function of Counter Devide Select Bit
CR1
CRO
0
0
0
Function
+1
+16
0
+64
Master Reset
Word Select Bits (CR2, CR3, and CR4)
- The Word Select bits are used to select word length, parity,
and the number of stop bits. The encoding format is as follows:
Control Register
The ACIA Control Register consists of eight bits of writeonly buffer that are selected when RS and R/W are "Low". This
register controls the functon of the receiver, transmitter,
218
------------------------------ HD6850,
HD68A50------~----------------------
• Status Register
Table 3 Function of Word Select Bit
Information on the status of the ACIA is available to the
MPU by reading the ACIA Status Register. This read-only
register is selected when RS is "Low" and R/W is "High".
Information stored in this register indicates the status of the
Transmit Data Register, the Receive Data Register and error
logic, and the peripheral/modem status inputs of the ACIA.
CR4
CR3
CR2
a
a
a
a
a
a
0
7 Bits + Even Parity + 2 Stop Bits
1
7 Bits + Odd Parity + 2 Stop Bits
1
a
7 Bits + Even Parity + 1 Stop Bit
1
1
7 Bits + Odd Parity + 1 Stop Bit
Receive Data Register Full (RDRF), Bit 0
1
a
8 Bits + 2 Stop Bits
1
a
a
1
8 Bits + 1 Stop Bit
1
1
a
8 Bits + Even Parity + 1 Stop Bit
1
1
1
8 Bits + Odd Parity + 1 Stop Bit
RDRF indicates that received data has been transferred to
the Receive Data Register. RDRF is cleared after an MPU read
of the Receive Data Register or by a master reset. The cleared or
empty state indicates that the contents of the Receive Data
Register are not current. Data Carrier Detect (OCD) being
"High" also causes RDRF to indicate empty.
Function
Word length, Parity Select, and Stop Bit changes are not
buffered and therefore become effective immediately.
Transmitter Control Bits (CR5 and CR6)
Two Transmitter Control bits provide for the control of
the interrupt from the Transmit Data Register Empty condition,
the Request-to-Send (RTS) output, and the transmission of a
Break level (space). The following encoding format is used:
Table 4 Function of Transmitter Control-Bit
eR6
CR5
o
a
RTS = "Low", Transmitting Interrupt Disabled.
1
RTS = "Low", Transmitting Interrupt Enabled.
a
RTS = "High", Transmitting Interrupt
o
Function
Disabled.
Transmitting Interrupt Disabled.
Receive Interrupt Enable Bit (CR7)
. The following interrupts will be enabled by a "1" in bit
position 7 of the Control Register (CR7): Receive Data
Register Full, Overrun, or a "Low" to "High" transistion on the
Data Carrier Detect (DCD) signal line.
RIE
Internal RoRF Flog
OVAN Flag
[
OeD Flag
Data Carrier Detect (DCD), Bit 2
The DCD bit will be "1" when the DCD input from a modem
has gone "High" to indicate that a carrier is not present. This bit
going" 1" causes an Interrupt Request to be generated when the
Receive Interrupt Enable is set. It remains" 1" after the DCD
input is returned "Low" until cleared by first reading the Status
Register and then the Data Register or until a master reset
occurs. If the DCD input remains "High" after read status and
read data or master reset has occurred, the interrupt is cleared,
the DCD status bit remains" 1" and will follow the DCD input.
The CTS bit indicates the state of the CTS input from a
modem. A "Low" CTS indicates that there is a CTS from the
modem. In the "High state, the Transmit Data Register Empty
bit is inhibited and the CTS status bit will be "1". Master reset
does not affect the Clear-to-Send Status bit.
the Transmit Data Output.
Receiver
The Transmit Data Register Empty bit being set "1"
indicates that the Transmit Data Register contents have been
transferred and that new data may be entered. The "0" state
indicates that the register is full and that transmission of a new
character has not begun since the last write data command.
Clear-to-Send (CTS), Bit 3
RTS = " Low", Transmits a Break level on
RoRF Flag
Transmit Data Register Empty (TDRE), Bit 1
Framing Error (FE), Bit 4
FE indicates that the received character is improperly framed
by a start and a stop bit and is detected by the absence of the
1st stop bit. This error indicates a synchronization error, faulty
transmission, or a break condition. The FE flag is set or reset
during the receive data transfer time. Therefore, this error
indicator is present throughout the time that the associated
character is available.
Receiver Overrun (OVRN), Bit 5
Overrun is an error flag that indicates that one or more
characters in the data stream were lost. That is, a character or a
number of characters were received but not read from the
Receive Data Register (RDR) prior to subsequent characters
being received. The overrun condition begins at the midpoint of
the last bit of the second character received in succession
without a read of the RDR having occurred. The overrun does
not occur in the Status Register until the valid character prior to
Overrun has been read. The RDRF bit remains set until the
Overrun is reset. Character synchronization is maintained during
the Overrun condition. The Overrun indication is reset after the
reading of data from the Receive Data Register or by a Master
Reset.
_ _ __
Internal TORE Flag
Transmitter
[
CTs Input
TORE Flag
Fig. 14 I RQ Internal Circuit
219
-------------------------------HD6850, HD68A50------------------------------Parity Error (PE), Bit 6
Clock Inputs
The PE flag indicates that the number of "1 "s (highs) in the
character does not agree with the preselected odd or even
parity. Odd parity is defined to be when the total number of
ones is odd. The parity error indication will be present as long as
the data character is in the RDR. If no parity is selected, then
both the transmitter parity generator output and the receiver
parity check results are inhibited.
Separate high impedance TTL compatible inputs are provided for clocking of transmitted and received data. Clock
frequencies of 1, 16 or 64 times the data rate may be selected.
Transmit Clock (Tx CLK)
The Tx CLK input is used for the clocking of transmitted
data. The transmitter initiates data on the negative transition of
the clock.
Interrupt Request (IRQ), Bit 7
The IRQ bit indicates the state of the IRQ output, Any
interrupt condition with its applicable enable will be-indicated
in this status bit. Anytime the IRQ output is "Low" the- IRQ bit
will be "1" to indicate the interrupt or service request status.
IRQ is cleared by a read operation to the Receive Data Register
or a write operation to the Transmit Data Register.
Receive Clock (Rx CLK)
The Rx CLK input is used for synchronization of received
data. (In the -:- 1 mode, the clock and data must be
synchronized externally.) The receiver samples the data on the
positive transition of the clock.
• Serial Input/Output Lines
• SIGNAL FUNCTIONS
•
Receive Data (Rx Data)
The Rx Data line is a high impedance TTL compatible input
Interface Signal for MPU
through which data is received in a serial format. Synchronization with a clock for detection of data is accomplished internally when clock rates of 16 or 64 times the bit rate are used. Data
rates are in the range of 0 to 500 kbps when external
synchronization is utilized.
Bi-Directional Data Bus (0 0 "'0 7 )
The bi-directional data bus (Do "'D 7 ) allow for data transfer
between the ACIA and the MPU. The data bus output drivers
are three-state devices that remain in the high impedance (off)
state except when the MPU performs an ACIA read operation.
Transmit Data (Tx Data)
Enable (E)
The Tx Data output line transfers serial data to a modem or
other peripheral. Data rates in the range of 0 to 500 kbps when
external synchronization is utilized.
The Enable signal, E, is a high impedance TTL compatible
input that enables the bus input/output data buffers and clocks
data to and from the ACIA. This signal will normally be a
derivative of the HMCS6800 ¢2 Clock.
Modem Control
The ACIA includes several functions that permit limited
control of a peripheral or modem. The functions included are
CTS, RTS and DCD.
ReadlWrite (RIW)
The R/W line is a high impedance input that is TTL
compatible and is used to control the direction of data flow
through the ACIA's input/output data bus interface. When R/W
is "High" (MPU Read cycle), ACIA output drivers are turned on
and a selected register is read. When it is "Low", the ACIA
output drivers are turned off and the MPU writes into a selected
register. Therefore, the R/W signal is used to select read-only or
write-only registers within the ACIA.
Clear-to-Send (CTS)
This high impedance TTL compatible input provides automatic control of the transmitting end of a communications link
via the modem CTS active "Low" output by inhibiting the
Transmit Data Register Empty (TDRE) status bit.
Chip Select (eS o , CS 1 , CS 2 )
Request-to-Send (RTS)
These three high impedance TTL compatible input lines are
used to address the ACIA. The ACIA is selected when CSo and
CS 1 are "High" and CS2 is "Low". Transfers of data to and
from the ACIA are then performed under the control of the
Enable signal, Read/Write, and Register Select.
The RTS output enables the MPU to control a peripheral or
modem via the data bus. The RTS output corresponds to the
state of the Control Register bits CR5 and CR6. When CR6=O
or both CR5 and CR6=1, the RTS output is "Low" (the active
state). This output can also be used for Data Terminal Ready
(OTR).
Register Select (RS)
The RS line is a high impedance input that is TTL
compatible. A "High" level is used to select the Transmit/
Receive Data Registers and a "Low" level the Control/Status
Registers. The R/W signal line is used in conjunction with
Register Select to select the read-only or write-only register in
each register pair.
Data Carrier Detect (DCD)
This high impedance TTL compatible input provides automatic control, such as in the receiving end of a communications
link by means of a modem DeD output. The DCD input inhibits
and initializes the receiver section of the ACIA wheri "High". A
"Low" to "High" transition of the DCD initiates an interrupt to
the MPU to indicate the occurrence of a loss of carrier when the
Receive Interrupt Enable bit is set.
Interrupt Request (IRQ)
IRQ is a TTL compatible, open-drain (no internal- pullup),
active "Low" output that is used to interrupt the MPU. The
IRQ output remains "Low" as long as the cause of the interrupt
is present and the appropriate interrupt enable within the ACIA
is set.
220
HD6852,HD68A52
SSDA (Synchronous Serial Data Adapter)
The HD6852 Synchronous Serial Data Adapter provides a
bi-directional serial interface for synchronous data information
interchange. It contains interface logic for simultaneously
transmitting and receiving standard synchronous communications characters in bus organized systems such as the
HMCS6800 Microprocessor systems.
The bus interface of the HD6852 includes select, enable,
read/write, interrupt, and bus interface logic to allow data
transfer over an 8-bit bi-directional data bus. The parallel data
of the bus system is serially transmitted and received by the
synchronous data interface with synchronization, fill character,
insertion/deletion, and. error checking. The functional configuration of the SSDA is programmed via the data bus during
system initialization.
Programmable control registers provide control for variable
word length, transmit control, receive control, synchronization
control and interrupt CO!ltrol. Status, timing and control lines
provide peripheral or modem control.
Typical applications include data communications terminals,
floppy'disk controllers, cassette or cartridge tape controllers and
numerical control systems.
• FEATURES
• Programmable Interrupts from Transmitter, Receiver,
and Error Detection Logic
• Character Synchronization on One or Two Sync Codes
• External Synchronization Available for Parallel·Serial
Operation
• Programmable Sync Code Register
• Up to 600kbps Transmitter
• Peripheral/Modem Control Functions
• Three Bytes of FIFO Buffering on Both Transmit and
Receive
• 6, 7, or 8 Bit Data Transmission
• Optional Even and Odd Parity
• Parity, Overrun, and Underflow Status
•
Compatible with MC6852 and MC68A52
•
BLOCK
CS
10
0,
17
D.
16
0,
15
REi
9
HD6852P, HD68A52P
(DP-24)
• PIN ARRANGEMENT
DIAGRAM
6
TxOata
24
ill
23
DCO
7
iFiQ
2
Rx Data
3
Rx elK
5
SM/iS'fR
(Top View)
-------------------------------HD6852, HD68A52------------------------------•
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Value
Unit
-0.3- +7.0
V
Input Voltage
Vee *
Yin *
-0.3 - +7.0
Operating Temperature
Topr
- 20 - + 75
V
°c
Storage Temperature
T stg
-55 - +150
°c
Supply Voltage
* With respect to Vss (SYSTEM GND)
(NOTE) Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating
conditions. If these conditions are exceeded, it could affect reliability of LSI.
•
RECOMMENDED OPERATING CONDITIONS
Item
Symbol
min
typ
max
Unit
Supply Voltage
Vee *
V 1L *
V 1H *
4.75
5
5.25
V
-0.3
-
ToP!'
- 20
Input Voltage
Operating Temperature
2.0
25
0.8
V
Vee
75
V
°c
* With respect to Vss (SYSTEM GND)
•
ELECTRICAL CHARACTERISTICS
•
DC CHARACTERISTICS (Vee = 5V ± 5%, Vss = OV, Ta = -20-+75°C, unless otherwise noted.)
min
typ*
Input "High" Voltage
All Input
VIH
-
2.0
-
-
V
Input "Low" Voltage
All Input
VIL
-
-
-
0.8
V
2.4
-
-
V
2.4
-
-
V
-
-
0.4
V
-
-
2.5
~A
-
-
10
~A
-
-
10
~A
-
300
525
-
-
12.5
-
-
7.5
-
-
10
-
5.0
Item
Symbol
Do-D 7
Output "High" Voltage
Tx Data
DTR,TUF
Output "Low" Voltage
All Output
V OH
V OH
VOL
Test Condition
IOH = -205 ~A,
PW EH , PWEL~ 25~s
IOH = -100~A,
PW EH , PWEL~25~s
IOL = 1.6 mA,
PW EH , PWEL~25~s
max
Unit
TxCLK, RxCLK,
Input Leakage Current
Rx Data, E,
RES, RS, R/W
lin
Yin = 0 - 5.25V
CS, DCD, CTS
Three·State Input Current
(Off State)
Output Leakage Current
(Off State)
Do- D7
ITS1
IRO
I LOH
Power Dissipation
Yin = 0.4 ..... 2.4V,
Vee = 5.25V
V OH = 2.4V
Po
Do ..... D7
RxData, RxCLK,
Input Capacitance
TxCLK, RES,
CS, RS, R/W, E,
Cin
Yin = OV,
Ta = 25°C
f = 1 MHz
mW
pF
DCD,CTS
Output Capacitance
* Ta
TxData, DTR, TUF,
IRO
Cout
Yin =OV, Ta=25°C
f = 1 MHz
= 25"C, vee = 5V
222
pF
-------------------------------HD6852, HD68A52------------------------------•
AC CHARACTERISTICS
Vp
"0" -+ pea
VAin < Vp
VAin: Analog Input
Voltage to be
compared
Vp : Programmed Voltage
x = Do not care
* = See Table 6
[NOTE] CD bit and ST bit are effective in every case.
(R4)
Status & AID Data Register (H) (R2)
This register is a 7 -bit read only register that is used to
store the upper 2-bit data (C8, C9), data weight (DW), data
overscale (OV), programmable comparator output (PCO),
busy (BSY) and interrupt request(IRQ).
(C8, C9)
These bits store upper 2-bit data mea(Upper bit data) sured by 10 bit length conversion.
BSY bit
(Busy)
This bit indicates that the ADU is now
under conversion.
IRQ bit
(Interrupt
Request)
This bit is set when the AID conversion
has completed and cleared by reading
the R3.
AID Data Register (L) (R3)
DWbit
(Data weight)
This register is an 8-bit read-only register that is used to
store the lower 8 bits data of lO-bit conversion or full 8 bits
data of the 8-bit conversion.
This bit indicates data weight when
Auto range-switching mode is selected.
This bit is set or reset when the conversion has completed. The conditions
are shown in following Table.
In this mode GAINSEL output also goes
"High" or "Low" on the same condition shown in Table 5.
Other status of DW bit is shown in
Table 6.
PC Data Register (R4)
This register is an 8-bit write-only register prepared for
Programmable Voltage comparison. Stored data is converted
to digital voltage, and compared with analog input to be
measured. The result of comparison is set into PCO bit.
Table 5 Data Weight (OW) Set or Reset Condition
~
Set
Mode
("1")
Reset
("0")
Auto Range-Switching (x2)
VA"In
410
< 1024
_
.
VREF ()
+
410
VAin> 1024 • V REF (+)
Auto Range-Switching (x4)
V "
Am
< 1024
206 • V
REF(+)
V " > 206 • V
Aln
1024
REF(+)
VAin
: Analog Input Voltage to be measured
VREF(+) : Voltage Applied to REF(+)
READ READ
Reg. 2 Reg. 3
WRITE WRITE
,Reg. ~ Reg: I
I
I
I
,
I
I
,
I
I
I
I
,
,
I
I
I
,
~
~
I
:
I
i:
'
_ I':
R~~.CS,,~
--~
I
i ~.:.:~;n;H:~;tmmm~~~~~~~~~~~~~~~~~~~~~.~~~~~~~~~~~~~~
~~
mOl
\
g~;~t~lro~
(Rl)
j ) .I I. I.
K
%
C
~
CD
CIt
o
ClK
!»
I\)
~
m.~
g~~I~erslor
~~~06ut
~~
lSB(20
)
.
~
L
H
I II
1 Conversion end
===~------------------------~I:l==~:
Status & AID
~:;~ Register
(H)~
AID Data
.~~",~~
(l)
7;~;ster
28
~)
BSy _ _ _ _ _.......
IRQ
MSB(29)
WdW~
Figure 13 AID Conversion Timing Chart (Basic Sequence)
%
C
~
CD
CIt
o
CD
.!..
HD46508, HD46508-1 - - - - - - - - - - - - - - • AID Conversion and PC sequence
(1'c:yc=1tL s)
10 bits AID Conversion
1)
Basic Sequence
SC =
( ST = "0"
GS= "0"
Conversion Start
Conversion End
"0")
2°
(LSB)
2) Basic Sequence
(When overscale
is detected)
Overscale check Cycle
(Analog Input is compared with V REF (+).)
3)
Expanded Sequence
"0")
SC =
( ST = "1"
GS= "0"
MSB cycle is expanded to compensate external amplifier's settling delay.
4)
Auto RangeSwitching Control
Sequence
SC = "0"
ST = "0"
GS = "1"
GO= "0"
(G1 = "1")
or
~---- Auto
Range- switching cycle
(Analog Input is compared with 1/2 V REF (+) or 1/4 V REF (+)
at this cycle)
( GO = "1")
G1 = "0"
5)
Auto Rangea) Analog Input < 1/2 V REF (+) or 1/4 V REF (+)
Switching & Expansion
Control
.-----~ "GAINSEL" goes "High"
Sequence
SC = "0"
ST = "1"
GS = "1" 1"",,a.u.;~~~~~L:.:.:=':'+-_--+_---.JL-_...L._--L_---.JL-_..L._--L_--.JL.:.:=.:..J
GO= "0"
(G1="1")
or
b) Analog Input> 1/2V REF (+) or 1/4VREF (+)
6) Sample & Hold
Control Sequence
(
~~: ::~::)
GS
GO
G1
= "1"
= "0"
= "0"
247
HD46508, HD46508-1
7) Programmable
Gain Control
Sequence
(
"GAINSEL" always goes "High"
~~: ::~::)
GS= "1"
GO= "1"
Gl = "1"
8) Programmable
Gain & Expansion
Control Sequence
=
"0")
SC = "1"
ST
GS= "1"
( GO= "1"
Gl ="1"
8 Bit AID Conversion
1) Basic Sequence
~~: ::~::)
( GS=
"0"
Additional conversion cycle
for rounding the LSB - 1 Bit .
./.
2) Expanded Sequence
"1")
SC =
( ST = "1"
GS= "0"
Programmable Voltage Comparison
~
~
1) Basic Sequence
"1")
PC =
(. ST = "0"
2) Expanded Sequence
(
"1")
PC =
ST = "1"
• HOW TO USE THE ADU
•
1) Auto Range-Switching (Auto Gain) Control
2) Programmable Gain control
3) Sample & Hold control
GAINSEL output is controlled by Mode Select bit (GO,
G 1) when GAINSEL enable bit (GS) is "1".
Functions of GAINSEL
The ADU is equipped with programmable GAINSEL output signal. By using GAINSEL output and external circuit,
the ADU is able to implement following control.
Table 6 GAINSEL Control
OW
GS
Gl
GO
0
x
x
"Low"
Normal Use (GAINSEL is not used)
0
1
1
0
0
0
"High"
Sample & Hold control
0
1
1
0
*
*
Auto Range Switching x 2 control
**
**
1
1
"High"
1
•
1
GAINSEL
Control Mode
Auto Range Switching x 4 control
Programmable Gain control
GAINSEL goes "High" or "Low" according to the condition shown in Table 5.
See, Table 5.
248
1
HD46508, HD46508-1
• Additional Circuits for GAINSEL Use
x1, x4 Auto/Pragrammable Gain
+8V
Voo
HD10466 OR Eav
r
I
20k
I
I
I
I
I
I
I
L'
COMMON
GAIN
SEL
Vss
REF (-)
COMPIN
ADU
Figure 14 Pre-amplifier Circuit
(x1, x4 Auto-Range Switching)
OV
x1 Sample & Hold
+8V
HA 17902 __---4t--~
0
DATA
11 ............ 1
NOT OVERSCALE
1
11 ............ 1
OVERSCALE
NOTE
Figure 16 Overscale Check Flow
HD14066
OR EDV.
r------------------I
2 n -1
Cl
,
1101
,
8
101 1
I
(/)
UJ
...J
COMMON
Vss
GAINSEL
REF(-)
~
COMPIN
(!)
ADU
,
011'
I-
010'
I
I
001,
c..
I-
::::>
o
: overseale area
I of t~e ADU
,I
I
I
,
,,
,I
100,
I
(5
::::>
ideal transition
111:
I
I
,
I
I
Figure 15 Sample & Hold Circuit
8/8 oversea Ie
refers voltage
•
~WV\jt.-v\MIWM~.".."'lNlr+'I/IA.,.....VVv......_'\I\I\r_+-_.
~
Cll<
-0
@
I
I-@
It"---
~~
l~
"""
'<>'
r--
'----
I'-- ~
~----
~-----!
>@-o
@)..
.@..
-@.
r-~
I-~
~.lJDS
Read Cye Ie
lOS. ODS Write CyeIe
~----
~
'C'
~J@~
~@
~
~f®--t
~r-
lI- I - -
~IL@
I--®"
,.
,....
~
~----
~
~---
~@
18
I-@":"'"
R/W Read Cye Ie
~1-
R/WWritl CyeIe
~3-
Date Out
ISla
11
Asynchronous Inpu ts
Note
, HALT. RES IInput
r-------@-=1
+-- ...
~
I--
~
M@
1-------------------R ______________________
~
I--
~
"'"
Date in---- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~
[NOTE)
1>------
- r-------
~
~
K------------- --------~
..
~--~---
r-@-'"
I
(f)-
...@-
"""
"""
J
~
"'"
Aill
.J
"'" ]
J---
1. Setup time for the asynchronous inputs BERR, ~. SR, DTACK, IPLo -IPL • and VPA guarantees
2
their recognition at the next falling edge of the clock.
2. Waveform measurements for all inputs and outputs are specified at: logic high'" 2.0 volts, logic low" 0.8 ,,"olts
Figure 5 AC Electrical Waveforms
258
These waveforms should only be referenced in regard to the edge-to-edge measurement of the timing specifications. They are not
intended as a functional description of the input and output signals. Refer to other functional descriptions and their related diagrams
for device operation.
Strobes
and R/W - - - - - - - - - - - - - - - - - - - - ___ - . I
I~
@
~I
BR
BGACK
~
1--L
@
CO
1m
1
t
I
@I~
t
~
@
i
1-
CLK
[NOTE] 1. Setup time for the asynchronous inputs BERR, BGACK, BR, DTACK, IPLo -IPL 2 , and VPA guarantees
their recognition at the next falling edge of the clock.
2. Waveform measurements for all inputs and outputs are specified at: logic high = 2.0 volts, logic low = 0.8
Figure 6
AC Electrical Waveforms - Bus Arbitration
~olts
J:
c
en
CIC»
Q
Q
Q
-----------------------------------H068000----------------------------------
The following paragraphs describe the data organization and
addressing capabilities of the HD68000.
The data types supported by the HD68000 are: bit data,
integer data of 8, 16, or 32-bit, 32-bit addresses and binary
coded decimal data. Each of these data types is put in memory,
as shown in Figure 8.
• OPERAND SIZE
•
Operand sizes are defined as follows: a byte equals 8-bits, a
word equals 16-bit, and a long word equals 32-bit. The operand
size for each instruction is either explicity encoded in the
instruction or implicity defined by the instruction operation.
All explicit instructions support byte, word or long word
operands. Implicit instructions support some subset of all three
sizes.
Instructions for the HD68000 contain two kinds of information: the type of function to be performed, and the location of
the operand(s) on which to perform that function. The methods
used to locate (address) the operand(s) are explained in the
following paragraphs.
Instructions specify an operand location in one of three
ways:
Register Specification - the number of the register is
given in the register field of the instruction.
Effective Address - use of the different effective address
modes.
Implicit Reference - the definition of certain instructions
implies the use of specific registers.
• DATA ORGANIZATION AND ADDRESSING CAPABILITIES
•
DATA ORGANIZATION IN REGISTERS
The eight data registers support data operands of 1, 8,16, or
32-bit. The seven address registers together with the active stack
pointer support address operands of 32-bit.
•
ADDRESSING
DATA REGISTERS
Each data register is 32-bit wide. Byte operands occupy the
low order 8·bit, word operands the low order 16·bit, and long
word operands the entire 32-bit. The least significant bit is
addressed as bit zero; the most significant bit is addressed as bit
31.
When a data register is used as either a source or destination
operand, only the appropriate low-order portion is changed; the
remaining high-order portion is neither used nor changed.
•
• ADDRESS REGISTERS
•
Each address register and the stack pointer is 32-bit wide and
holds a full 32-bit address. Address registers do not support byte
sized operands. Therefore, when an address register is used as a
source operand, either the low order word or the entire long
word operand is used depending upon the operation size. When
an address register is used as the destination operand, the entire
register is affected regardless of the operation size. If the
operation size is word, any other operands are sign extended to
32-bit before the operation is performed.
The HD68000 separates memory references into two classes:
program references, and data references. Program references, as
the name implies, are references to that section of memory that
contains the program being executed. Data references refer to
that section of memory that contains data. Generally, operand
reads are from the data space. All operand writes are to the data
space.
•
•
DATA ORGANIZATION IN MEMORY
14
13
12
11
Byte 000000
Byte 000002
10
9
PROGRAM/DATA REFERENCES
REGISTER SPECIFICATION
The register field within an instruction specifies the register
to be used. Other fields within the instruction specify whether
the register selected is an address or data register and how the
register is to be used.
Bytes are individually addressable with the high order byte
having an even address the same as the word, as shown in Figure
7. The low order byte has an odd address that is one count
higher than the word address. Instructions and multibyte data
are accessed only on word (even byte) boundaries. If a long
word datum is located at address n (n even), then the second
word of that datum is located at address n + 2.
15
INSTRUCTION FORMAT
Instructions are from one to five words in length, as shown in
Figure 9. The length of the instruction and the operation to be
performed is specified by the first word of the instruction which
is called the operation word. The remaining words further
specify the operands. These words are either immediate
operands or extensions to the effective address mode specified
in the operation word.
7
8
Word 000000
I
6
5
4
3
0
Byte 000001
I
Byte 000003
··
Byte FFFFFE
1
Word 000002
•
•
•
Word FFFFFE
1
2
J
~
Byte FFFFFF
Figure 7 Word Organization In Memory
260
HD68000
7
6
Bit Data
1 Byte = a-Bit
2
4
3
5
0
Integer Data
1 Byte = a-Bit
15
14
13
12
11
10
9
6
a
4
5
3
2
0
2
0
Byte 1
Byte 0
LSBI
IMS'
Byte 2
Byte 3
= 16-Bit
1 Word
14
15
13
12
11
9
10
6
a
4
5
3
Word 0
IMS'
LSBI
Word 1
Word 2
1 Long Word
14
15
MSB
---
13
11
12
10
9
= 32-Bit
7
a
6
4
5
0
2
3
High Order
Long Word 0- -
- -
-
- -
- -
-
- - - - Low Order
- -
-
-
-
--- ---- -- -- - -- -
- -
-
- - - - -
-
-
-
-
-
-
-
-
-
-
- - -LSB
---LongWord1---- -
-Long Word 2- - - - -
-
-
- -
-
--- -
- - -
-
-
-- --- --
-
-
-
-
-
- -
Addresses
1 Address = 32-Bit
15
MSB
- -
14
13
12
11
10
a
9
7
5
6
4
o
2
3
High Order
-
Address 0- -
-
-
-
-
-
-
-
-
- - - - Low Order
-
-
-
-
-
-
-
- -
-
-
- - - -LSB
-- -
Address 1_ - - - - - _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- ___ Address2. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
MSB = Most Significant Bit
LSB = Least Significant Bit
15
MSD
MSD
LSD
14
13
12
11
Decimal Data
2 Binary Coded Decimal Digits = 1-Byte
10
4
7
6
9
5
a
BCD 0
BCD 1
BCD 4
BCD 5
LSD
2
1
BCD 3
BCD 6
BCD 7
= Most Significant Digit
= Least Significant Digit
Figure 8 Data Organization in Memory
261
3
BCD 2
0
------------------------------------ HD68000----------------------------------• EFFECTIVE ADDRESS
Most instructions specify the location of an operand by using
the effective address field in the operation word. For example,
Figure 10 shows the general fonnat of the single effective
address instruction operation word. The effective address is
composed of two 3-bit fields: the mode field, and the register
field. The value in the mode field selects the different address
modes. The register field contains the number of a register.
The effective address field may require additional infonnation to fully specify the operand. This additional infonnation,
called the effective address extension, is contained in the
following word or words and is considered part of the
instruction, as shown in Figure 9. The effective address modes
are grouped into three categories: register direct, memory
addressing, and special.
REGISTER DIRECT MODES
These effective addressing modes specify that the operand is
in one of the 16 multifunction registers.
Data Register Direct
The operand is in the data register specified by the effective
address register field.
Address Register Direct
The operand is in the address register specified by the
effective address register field.
MEMORY ADDRESS MODES
These effective addressing modes specify that the operand is
in memory and provide the specific address of the operand.
Address Register Indirect
The address of the operand is in the address register specified
by the register field. The reference is classified as a data
reference with the exception of the jump and jump to
subroutine instructions.
15
14
13
12
11
Address Register Indirect With Postincement
The address of the operand is in the address register specified
by the register field. After the operand address is used, it is
incremented by one, two, or four depending upon whether the
size of the operand is byte, word, or long word. If the address
register is the stack pointer and the operand size is byte, the
address is incremented by two rather than one to keep the stack
pointer on a word boundary. The reference is classified as a data
reference.
Address Register Indirect With Predecrement
The address of the operand is in the address register specified
by the register field. Before the operand address is used, it is
decremented by one, two, or four depending upon whether the
operand size is byte, word, or long word. If the address register
is the stack pointer and the operand size is byte, the address is
decremented by two rather than one to keep the stack pointer
on a word boundary. The reference is classified as a data
reference.
Address Register Indirect With Displacement
This address mode requires one word of extension. The
address of the operand is the sum of the address in the address
register and the sign-extended 16-bit displacement integer in the
extension word. The reference is classified as a data reference
with the exception of the jump and jump to subroutine
instructions.
Address Register Indirect With Index
This address mode requires one word of extension. The
address of the operand is the sum of the address in the address
register, the signextended displacement integer in the low order
eight bits of the extension word, and the contents of the index
register. The reference is classified as a data reference with the
exception of the jump and jump to subroutine instructions.
10
7
6
5
9
8
Operation Word
(First Word Specifies Operation and Modes)
2
3
4
1
0
Immediate Operand
(If Any. One or Two Words)
Source Effective Address Extension
(If Any. One or Two Words)
Destination Effective Address Extension
(If Any. One or Two Words)
Figure 9 Instruction Format
5
4
3
2
Effective Address
Mode
Register
Fig 10 Single· Effective-Address Instruction Operation Word General Format
262
o
HD68000---------------------------------Table 4 Effective Address Encoding Summary
SPECIAL ADDRESS MODES
The special address modes use the effective address register
field to specify the special addressing mode instead of a register
number.
Mode
Register
Data Register Direct
000
register number
Address Register Direct
001
register number
Absolute Short Address
Address Register Indirect
010
register number
Address Register Indirect with
Posti ncrement
011
register number
Address Register Indirect with
Predecrement
100
register number
Address Register Indirect with
Displacement
101
register number
Absolute Long Address
Address Register Indirect with Index
110
register number
This address mode requires two words of extension. The
address of the operand is developed by the concatenation of the
extension words. The high-order part of the address is the first
extension word; the low-order part of the address is the second
extension word. The reference is classified as a data reference
with the exception of the jump and jump to subroutine
instructions.
Absolute Short
111
000
Absolute Long
111
001
Program Counter with Displacement
111
010
Program Counter with Index
111
011
Immediate or Status Register
111
100
Addressing Mode
This address mode requires one word of extension. The
address of the operand is the extension word. The 16-bit address
is sign extended before it is used. The reference is classified as a
data reference with the exception of the jump and jump to
subroutine instructions.
Table 5 Implicit Instruction Reference Summary
Program Counter With Displacement
This address mode requires one word of extension. The
address of the operand is the sum of the address in the program
counter and the sign-extended 16-bit displacement integer in the
extension word. The value in the program counter is the address
of the extension word. The reference is classified as a program
reference.
Instruction
Implied
Register (s)
Branch Conditional (Bee), Branch Always (BRA)
PC
Branch to Subroutine (BSR)
PC,SP
Check Register against Bounds (CH K)
SSP, SR
Test Condition, Decrement and Branch (DBee)
PC
"-~--.-
Program Counter With Index
This address mode requires one word of extension. The
address is the sum of the address in the program counter, the
sign-extended displacement integer in the lower eight bits of the
extension word, and the contents of the index register. The
value in the program counter is the address of the extension
word. This reference is classified as a program reference.
Immediate Data
This address mode requires either one or two words of
extension depending on the size of the operation.
Byte operation - operand is low order byte of extension
word
Word operation - operand is extension word
Long word operl!-tion - operand is in the two extension
words, high-order 16 bits are in the first extension
word, low-order 16 bits are in the second extension
word.
--
,
-' ...
-
-_._------..- - -
Signed Divide (DIVS)
SSP,SR
Unsigned Divide (DIVU)
SSP,SR
Jump (JMP)
PC
Jump to Subroutine (JSR)
PC,SP
Link and Allocate (LINK)
SP
Move Condition Codes (MOVE CCR)
SR
Move Status Register (MOVE SRI
SR
Move User Stack Pointer (MOVE USP)
USP
Push Effective Address (PEA)
SP
Return from Exceotion (RTE)
PC, SP,SR
Return and Restore Condition Codes IRTR)
PC, SP,SR
Return from Subroutine (RTS)
PC,SP
Trap (TRAP)
SSP,SR
Trap on Overflow (TRAPV)
SSP,SR
Unlink (UNLK)
SP
Condition Codes or Status Register
•
A selected set of instructions may reference the status
register by means of the effective address field. These are:
AND! toCCR
AND! toSR
EORI toCCR
EORI to SR
ORI to CCR
ORI to SR
Some instructions make implicit reference to the program
counter (PC), the system stack pointer (SP), the supervisor stack
pointer (SSP), the user stack pointer (USP), or the status
register (SR). Table 5 provides a list of these instructions and
the registers implied.
•
IMPLICIT REFERENCE
SYSTEM STACK
The system stack is used implicitly by many instructions;
user stacks and queues may be created and maintained through
the addressing modes. Address register seven (A 7) is the system
EFFECTIVE ADDRESS ENCODING SUMMARY
Table 4 is Ii summary of the effective addressing modes
stack pointet (SP). The system stack pointer is either the
discussed in the previous paragraphs.
supervisor stack pOinter (SSP) or the user stack pointer (USP),
depending on the state of the S-bit in th~ status registar. If the
S-bit indicates supervisor state, SSP is the active system stack
263 pointer, and the USP cannot be referenced as an address
------------------------------------ HD68000----------------------------------register. If the S-bit indicates user state, the USP is the active
system stack pointer, and the SSP cannot be referenced. Each
system stack fills from high memory to low memory.
•
•
INSTRUCTION SET SUMMARY
The following paragraphs contain an overview of the form
and structure of the HD68000 instruction set. The instructions
form a set of tools that include all the machine functions to
perform the following operations:
Data Movement
Integer Arithmetic
Logical
Shift and Rotate
Bit Manipulation
Binary Coded Decimal
Program Control
System Control
The complete range of instruction capabilities combined with
the flexible addressing modes described previously provide a
very flexible base for program development.
•
INTEGER ARITHMETIC OPERATIONS
The arithmetic operations include the four basic operations
of add (ADD), subtract (SUB), multiply (MUL), and divide
(DIY) as well as arithmetic compare (CMP), clear (CLR), and
negate (NEG). The add and subtract instructions are available
for both address and data operations, with data operations
accepting all operand sizes. Address operations are limited to
legal address size operands (16 or 32 bits). Data, address, and
memory compare operations are also available. The clear and
negate instructions may be used on all sizes of data operands.
The mUltiply and divide operations are available for signed
and unsigned operands using word multiply to produce a long
word product, and a long word dividend with word divisor to
produce a word quotient with a word remainder.
Multiprecision and mixed size arithmetic can be accomplished using a set of extended instructions. These instructions
are: add extended (ADDX), subtract extended (SUBX), sign
extend (EXT), and negate binary with extend (NEG X).
A test operand (TST) instruction that will set the condition
codes as a result of a compare of the operand with zero is also
available. Test and set (T AS) is a synchronization instruction
useful in multiprocessor systems. Table 7 is a summary of the
integer arithmetic operations.
DATA MOVEMENT OPERATIONS
The basic method of data acquisition (transfer and storage) is
provided by the move (MOVE) instruction. The move instruction and the effective addressing modes allow both address and
data manipulation. Data move instructions allow byte, word,
and long word operands to be transferred from memory to
memory, memory to register, register to memory, and register
to register. Address move instructions allow word and long word
operand transfer and ensure that only legal address manipulations are executed. In addition to the general move instruction
there are several special data movement instructions: move
multiple registers (MOVEM), move peripheral data (MOVEP),
exchange registers (EXG), load effective address (LEA), push
effective address (PEA), link stack (LINK), unlink stack
(UNLK), and move quick (MOVEQ). Table 6 is a summary of
the data movement operations.
Table 7 Integer Arithmetic Operations
Instruction
Operand Size
16,32
ADD X
8,16,32
16,32
Ox + Dy + X -+ Ox
Ax@- + Ay@ -+X-+ Ax@
CLR
8,16,32
0-+ EA
8,16,32
On (EA)
Ax@
An -
ADD
CMP
16,32
Table 6 Data Movement Operations
Instruction
Operation
Operand Size
Operation
On + (EA) -+ On
(EA) + On -+ EA
(EA) + #Xxx -+ EA
An + (EA) -+ An
8,16,32
(EA)
- #xxx
+ - Ay@+
(EA)
DIVS
32+ 16
On/lEA) -+ On
DIVU
32+ 16
Dn/(EA) -+ On
EXT
8-+ 16
16- 32
MULS
16 M 16 - 32
(Dn)s -+ Dn 16
(On) 16 - Dn 32
On IE (EA) -+ On
EXG
32
Rx.-. Ry
LEA
32
EA -+ An
LINK
-
An-+ SP@SP-+ An
SP + d -+ SP
MULU
16_ 16 - 32
On IE (EAl .... On
NEG
8,16,32
o -.(EA) .... EA
NEGX
8,16,32
0- (EA) - X - EA
8,16,32
On lEA)
lEA)
An -
MOVE
8,16,32
(EA)s-+ EAd
MOVEM
16,32
(EA) -+ An, On
An, On -+ EA
MOVEP
16,32
(EA) -+ On
On -+ EA
MOVEQ
8
#xxx ...... On
PEA
32
EA ...... SP@-
SWAP
32
Dn[31 :16) ...... Dn[15:0)
-
An -+ SP
SP@ + ...... An
UNLK
[NOTES)
SUB
16,32
8,16,32
Dx-Dy -X .... Ox
Ax@ - - Ay@ - - X .... Ax@
TAS
8
lEA) - 0, 1 -+ EA [7)
TST
8,16,32
lEA) -0
SUBX
[NOTE]
s = source
d = destination
[ ) = bit numbers
@ - = indirect with predecrement
@ + = indirect with postincrement
264
(EA) - On
- On -+ EA
- #xxx -+ EA
(EA) - An
[
) = bit number
-----------------------------------HD68000---------------------------------•
LOGICAL OPERATIONS
•
Logical operation instructions AND, OR, EOR, and NOT are
available for all sizes of integer data operands. A similar set of
immediate instructions (AN 01 , ORI, and EORI) prcvide these
logical operations with all sizes of immediate data. Table 8 is a
summary of the logical operations.
BIT MANIPULATION OPERATIONS
Bit manipulation operations are accomplished using the
following instructions: bit test (BTST), bit test and set (BSET),
bit test and clear (BCLR), and bit test and change (BCHG).
Table 10 is a summary of the bit manipulation operations. (Bit
2 of the status register is Z.)
Table 10 Bit Manipulation Operations
Table 8 Logical Operations
Instruction
Operand Size
Instruction
Operation
8.16.32
OR
8.16.32
Dn v (EA) -+ On
(EA) v Dn -+ EA
(EA) v #xxx -+ EA
EOR
8.16.32
(EA)EIl Dy -+ EA
(EA) Ell #xxx -+ EA
NOT
8.16.32
- (EA) -+ EA
AND
Operand Size
Operation
8.32
- bit of (EA)
BSET
8.32
- bit of (EA) -+ Z
1 -+ bit of EA
BClR
8.32
- bit of (EA) -+ Z
0-+ bit of EA
BCHG
8.32
- bit of (EA) -+ Z
- bit of (EA) -+ bit of EA
BTST
Dn,,(EA)-+ Dn
(EA)" Dn -+ EA
(EA)" #Xxx -+ EA
-+
Z
[NOTE) - = invert
•
•
BINARY CODED DECIMAL OPERATIONS
Multiprecision arithmetic operations on binary coded decimal numbers are accomplished using the following instructions:
add decimal with extend (ABCD), subtract decimal with extend
(SBCD), and negate decimal with extend (NBCD). Table 11 is a
summ ary of the binary coded decimal operations.
SHIFT AND ROTATE OPERATIONS
Shift operations in both directions are provided by the
arithmetic instructions ASR and ASL and logical shift instructions LSR and LSL. The rotate instructions (with and without
extend) available are ROXR, ROXL, ROR, and ROL. All shift
and rotate operations can be performed in either registers or
memory. Register shifts and rotates support all operand sizes
and allow a shift count specified in the instruction of one to
eight bits, or 0 to 63 specified in a data register.
Memory shifts and rotates are for word operands only and
allow only single-bit shifts or rotates.
Table 9 is a summary of the shift and rotate operations.
Table 11 Binary Coded Decimal Operations
Instruction
Operand Size
Operation
ABCD
8
Dx lO + Dy,o + X -+ Dx
Ax@ -10 + Ay@ -10 + X -+ Ax@
SBCD
8
Dx 10 - DYlo - X -+ Dx
Ax@ - 10 - Ay@ - 10- X
NBCD
8
0- (EA)IO - X
-+
--+
Ax@
EA
Table 9 Shift and Rotate Operations
Instruction
Operand Size
ASl
8.16.32
~.
ASR
8.16.32
lSl
8.16.32
~
§£H-
lSR
8.16.32
0--1
ROl
8.16.32
~
ROR
8.16.32
ROXl
8.16.32
ROXR
8.16.32
•
Operation
.
q
coY.
l.j
X
H
1-
.
0
~
1-
PROGRAM CONTROL OPERATIONS
Program control operations are accomplished using a series of
conditional and unconditional branch instructors and return
instructions. These instructions are summarized in Table 12 .
The conditional instructions provide setting and branching
for the following conditions:
CC
carry clear
LS - low or same
LT - less than
CS
carry set
EQ
equal
MI - minus
F
never true
NE - not equal
PL - plus
GE - greater or equal
always true
GT - greater than
T
no overflow
VC
HI - high
overflow
VS
LE - less or equal
0
.~
I::J
.~
j..fxl-J
.~
•
SYSTEM CONTROL OPERATIONS
System control operations are accomplished by using privileged instructions, trap generating instructions, and instructions
that use or modify the status register. These instructions are
summarized in Table 13.
265
----------------------------------HD68000--------------------------------Table 12 Program Control Operations
Operation
Instruction
Conditional
Bee
Branch conditionally (14 conditions)
8- and 16-bit displacement
Test condition, decrement, and branch
16-bit displacement
Set byte conditionally (16 conditions)
DBee
Sec
Unconditional
B'RA
Branch always
8- and 16-bit displacement
Branch to subroutine
8- and 16-bit displacement
Jump
Jump to subroutine
BSR
JMP
JSR
Returns
RTR
RTS
HD68000
icroprocesso
Processor {
Status
HMCS6800{
Peripheral
Control
System {
Control
Return and restore condition codes
Return from subroutine
E
VMA
-PBERR
RES
Bus
Control
BR
BG
}
Bus
Arbitration
Control
~
}
HALT
Interrupt
Control
Figure 11 Input and Output Signals
Table 13 System Control Operations
Instruction
DATA BUS (Do THROUGH 0 15 )
This 16-bit, bidirectional, three-state bus is the general
purpose data path. It can transfer and accept data in either word
or byte length. During an interrupt acknowledge cycle, the
external device supplies the vector number on data lines
Operation
Privileged
RESET
RTE
STOP
ORI to SR
MOVE USP
ANDI to SR
EORI to SR
MOVE EAto SR
Reset external devices
Return from exception
Stop program execution
Logical OR to status register
Move user stack pointer
Logical AND to status register
Logical EOR to status register
Load new status register
Trap Generating
TRAP
TRAPV
CHK
Trap
Trap on overflow
Check register against bounds
Status Register
ANDI to CCR
EORI to CCR
MOVE EA to CCR
ORI to CCR
MOVE SR to EA
Logical AND to condition codes
Logical EOR to condition codes
Load new condition codes
Logical OR to condition codes
Store status register
Do"'D7'
ASYNCHRONOUS BUS CONTROL
Asynchronous data transfers are handled using the following
control signals: address strobe, read/write, upper and lower data
strobes, and data transfer acknowledge. These signals are
explained in the following paragraphs.
Address Strobe (AS)
This signal indicates that there is a valid address on the
address bus.
ReadIWrite (RIW)
This signal defmes the data bus transfer as a read or write
cycle. The R/W signal also works in conjunction with the upper
and lower data strobes as explained in the following paragraph.
Upper And Lower Data Strobes (UDS, LOS)
These signals control the data on the data bus, as shown in
Table 14. When the R/W line is "High", the processor will read
from the data bus as indicated. When the R/W line is "Low", the
processor will write to the data bus as shown.
• SIGNAL AND BUS OPERATION DESCRIPTION
The following paragraphs contain a brief description of the
input and output signals. A discussion of bus operation during
the various machine cycles and operations is also given.
Data Transfer Acknowledge (DTACK)
This input indicates that the data transfer is completed.
When the processor recognizes DTACK during a read cycle, data
is latched and the bus cycle terminated. When DTACK is
recognized during a write cycle, the bus cycle is terminated.
• SIGNAL DESCRIPTION
The input and output signals can be functionally organized
into the groups shown in Figure 11. The following paragraphs
provide a brief description of the signals and also a reference (if
applicable) to other paragraphs that contain more detail about
the function being performed.
BUS ARBITRATION CONTROL
These three signals form a bus arbitration circuit to determine which device will be the bus master device.
ADDRESS BUS (AI THROUGH A 23 )
This 23-bit, unidirectional, three-state bus is capable of
addressing 8 megawords of data. I t provides the address for bus
?peration during all cycles except interrupt cycles. During
mterrupt cycles, address lines AI. A2 , and Aj provide information about what level interrupt is being serviced while address
lines A4 through A23 are all set to a logic high.
Bus Request (BR)
This input is wire ORed with all other devices that could be
bus masters. This input indicates to the processor that some
other device desires to become the bus master.
266
HD68000 - - - - - - - - - - - - - - - - Reset (RES)
Table 14 Data Strobe Control of Data Bus
R/W
UOS
LOS
High
High
-
Low
Low
High
High
Low
High
Low
High
High
Low
Low
Low
High
Low
Low
Low
High
Low
DB~D1S
No valid data
No valid data
Valid data bits
Valid data bits
8~15
No valid data
Valid data bits
8-15
Valid data bits
0~7
Valid data bits
0~7
No valid data
Valid data bits
8-15
0-7
Valid data bits
Valid data bits
0-7*
0-7
Valid data bits
Valid data bits
Halt (HALT)
When this bidirectional line is driven by an external device, it
will cause the processor to stop at the completion of the current
bus cycle. When the processor has been halted using this input,
all control signals are inactive and all three-state lines are put in
their high-impedance state. Refer to BUS ERROR AND HAL T
OPERATION paragraph for additional information about the
interaction between the halt and bus error signals.
When the processor has stopped executing instructions, such
as in a double bus fault condition, the halt line is driven by the
processor to indicate to external devices that the processor has
stopped.
8~15*
8-15
.. are a result of current
* These conditions
This bidirectional signal line acts to reset (initiate a system
initialization sequence) the processor in response to an external
reset signal. An internally generated reset (result of a RESET
instruction) causes all external devices to be reset and the
internal state of the processor is not affected. A total system
reset (processor and external devices) is the result of external
halt and reset signals applied at the same time. Refer to RESET
OPERATION paragraph for additional information about reset
operation.
DO~07
Implementation and may
not appear on future devices.
Bus Grant (BG)
This output indicates to all other potential bus master
devices that the processor will release bus control at the end of
the current bus cycle.
HMCS6800 PERIPHERAL CONTROL
These control signals are used to allow the interfacing of
synchronous HMCS6800 peripheral devices with the asynchronous HD68000. These signals are explained in the following
paragraphs.
Bus Grant Acknowledge (BGACK)
This input indicates that some other device has become the
bus master. This signal cannot be asserted until the following
four conditions are met:
1. a bus grant has been received
2. address strobe is inactive which indicates that the microprocessor is not using the bus
3. data transfer acknowledge is inactive which indicates that
either memory or the peripherals are not using the bus.
4. bus grant acknowledge is inactive which indicates that no
other device is still claiming bus mastership.
Enable (E)
This signal is the standard enable signal common to all
HMCS6800 type peripheral devices. The period for this output
is ten HD68000 clock periods (six clocks "Low", four clocks
"High").
Valid Peripheral Address (VPA)
INTERRUPT CONTROL UPl oI IPl l , IPl 2 )
These input pins indicate the encoded priority level of the
device requesting an interrupt. Level seven is the highest priority
while level zero indicates that no interrupts are requested. The
least significant bit is given in IPLo and the most significant bit
is contained in IPL2 •
This input indicates that the device or region addressed is a
HMCS 6800 family device and that data transfer should be
synchronized with the enable (E) signal. This input also
indicates that the processor should use automatic vectoring for
an interrupt. Refer to INTERFACE WITH HMCS6800
PERIPHERALS.
SYSTEM CONTROL
Valid Memory Address (VMA)
The system control inputs are used to either reset or halt the
processor and to indicate to the processor that bus. errors have
occurred. The three system control inputs are explained in the
following paragraphs.
This output is used to indicate to HMCS6800 peripheral
devices that there is a valid address on the address bus and the
processor is synchronized to enable. This signal only responds to
a valid peripheral address (VPA) input which indicates that the
peripheral is a HMCS6800 family device.
Bus Error (BERR)
This input informs the processor that there is a problem with
the cycle currently being executed. Problems may be a result of:
1. nonresponding devices
2. interrupt vector num ber acquisition failure
3. illegal access request as determined by a memory management unit
4. other application dependent errors.
The bus error signal interacts with the halt signal to
determine if exception processing should be performed or the
current bus cycle should be retried.
Refer to BUS ERROR AND HALT OPERATION paragraph
for additional information about the interaction of the bus error
and halt signals.
PROCESSOR STATUS (FC o , FC 1I FC 2 )
These function code outputs indicate the state (user or
supervisor) and the cycle type currently being executed, as
shown in Table 15. The information indicated by the function
code outputs is valid whenever address strobe (AS) is active.
CLOCK (ClK)
The clock input is a TTL compatible signal that is internally
buffered for development of the internal clocks needed by the
processor. The clock input shall be a constant frequency.
267
----------------------------------- HD68000----------------------------------
Table 16 is a summary of all the signals discussed in the
previous paragraphs.
The address and data buses are separate parallel buses used to
transfer data using an asynchronous bus structure. In all cycles,
the bus master assumes responsibility for deskewing all signals it
issues at both the start and end of a cycle. In addition, the bus
master is responsible for deskewing the acknowledge and data
signals from the slave device.
The following paragraphs explain the read, write, and
read-modify-write cycles. The indivisible read-modify-write
cycle is the method used by the HD68000 for interlocked
multiprocessor communications.
[NOTE] The terms assertion and negation will be used extensively. This is done to avoid confusion when
dealing with a mixture of "active-low" and "activehigh" signals. The term assert or assertion is used to
indicate that a signal is active or true independent of
whether that voltage is "Low" or "High". The term
negate or negation is used to indicate that a signal is
inactive or false .
•
Read Cycle
Table 15 Function Code Outputs
FC 2
FC!
FC o
Cycle Type
Low
Low
Low
(Underfined, Reserved)
Low
Low
High
User Data
Low
High
Low
User Program
Low
High
High
(Undefined, Reserved)
High
Low
Low
(Undefined, Reserved)
High
Low
High
Supervisor Data
High
High
Low
Supervisor Program
High
High
High
Interrupt Acknowledge
SIGNAL SUMMARY
BUS OPERATION
The following paragraphs explain control signal and bus
operation during data transfer operations, but arbitration, bus
error and halt conditions, and reset operation.
DATA TRANSFER OPERATIONS
Transfer of data between devices involves the following
leads:
Address Bus Al through A23
Data Bus Do through 015
Control Signals
During a read cycle, the processor receives data from
memory or a peripheral device. The processor reads bytes of
data in all cases. If the instruction specifies a word (or double
word) operation. the processor reads both bytes. When the
instruction specifies byte operation, the processor uses an
internal AO bit to determine which byte to read and then issues
the data strobe required for that byte. For byte operations,
when the AO bit equals zero, the upper data strobe is issued.
When the AO bit equals one, the lower data strobe is issued.
When the data is received, the processor correctly positions it
Table 16 Signal Summary
Mnemonic
Input/Output
Active State
Three State
Address Bus
A I -A23
Output
High
Yes
Data Bus
0 0 -0 15
Input/Output
High
Yes
Address Strobe
AS
Output
Low
Yes
Rm
Output
Read-High
Write-Low
Yes
Yes
Signal Name
ReadlWrite
Upper and Lower Data Strobes
UDS, LOS
Output
Low
Data Transfer Acknowledge
DTACK
Input
Low
No
Bu.s Request
BR
Input
Low
No
Bus Grant
BG
Output
Low
No
Bus Grant Acknowledge
BGACK
Input
Low
No
Interrupt Priority Level
IPL o , IPL I , IPL2
Input
Low
No
Input
Low
Low
No
No*
Bus Error
BERR
Reset
RES
Input/Output
Halt
HALT
Input/Output
Low.
No*
Enable
E
Output
High
No
Valid Memory Address
VMA
Output
Low
Yes
Valid Peripheral Address
VPA
Input
Low
No
Output
High
Yes
Function Code Output
FCo , FC I , FC 2
Clock
ClK
Input
High
No
Power Input
Vee
Vss
Input
-
-
Ground
Input
* Open dram
268
-
HD68000--------------------------------internally.
A word read cycle flow chart is given in Figure 12. A byte
read cycle flow chart is given in Figure 13. Read cycle timing is
given in Figure 14 and Figure 15 details word and byte read
cycle operation.
3)
4)
5)
Address Device
Set R/W to Read
Place Address on AI - A'3
Pillce FUl'lction Code on FC o - FC,
Assert A,oj-!ress Strobe (AS)
Assert Up'.r Data Strobe (UDS) and Lower
Data Strobe (LOS)
I
t
1)
2)
3)
1) Decode Address
2) Place Data on Do - 0 7 or De - 015
(based on UDS or ~)
3) Assert Data Transfer Acknowledge (DTACK)
Decode Address
Place Data on Do - 015
Assert Data Transfer Acknowledge (DiACK)
Acquire Data
1) Latch Data
2) Negate ODS or [l)S"
3) Negate AS
V
Acquire Data
3)
Latch Data
Negate 015S and
Negate ~
I
t
I
1)
2)
SLAVE
Address pevice
1) Set R/W to Read
2) Place Address on AI - A23
3) Place Function Code on FC o - FC,
4) Assert Address Strobe (AS)
5) Assert Upper Data Strobe (UDS) or Lower
Data Strobe (LOS) (based on Ao )
SLAVE
BU,; MASTER
1)
2)
BUS MASTER
a>s
Terminate Cycle
1) Remove Data from Do - 0 7 or De - 0 1 ,
2) Negate of ACK
Terminate Cycle
1)
2)
I
Remove Data from Do - 015
Negate of ACK
Start Next Cycle
Figure 13 Byte Read Cycle Flow Chart
Start Next Cycle
Figure 12 Word Read Cycle Flow Chart
>-<
AS
\
I
ODS
\
I
05S
\
I
H
R/W
\
OTACK
0 8 -0 15
0
0-°7
FCo -FC 2
<
:::::>--<
I--- ----
<
-Read - - - -
I
>
)
H
>-
>-<
I
\
\
\
I
\
I
\
<
<
+- ------
Write - - - -
H
>r-
\
rr-
\
I
I
>
)
H
\
\
(
(
-+- -------
Figure 14 Read and Write Cycle Timing Diagram
269
Slow Read - - - - - -
r
>>>~
* Internal Signal Only
~
- - - Word Read - -
+ --
-Odd Byte Read - -
+ --
Even Byte Read - -
~
Figure 15 Word and Byte Read Cycle Timing Diagram
Write Cycle
SLAVE
BUS MASTER
During a write cycle, the processor sends data to memory or
a peripheral device. The processor writes bytes of data in all
cases. If the instruction specifies a word operation, the
processor writes both bytes. When the instruction specifies a
byte operation, the processor. uses an internal AO bit to
determine which byte to write and then issues the data strobe
required for that byte. For byte operations, when the AO bit
equals zero, the upper data strobe is issued. When the AO bit
equals one, the lower data strobe is issued. A word write cycle
flow chart is given in Figure 16. A byte write cycle flow chart is
given in Figure 17. Write cycle timing is given in Figure 14 and
Figure 18 details word and byte write cycle operation.
Address Device
1) Place Address on AI -A l3
2)
3)
4)
5)
6)
Place Function Code on FC o - FC,
Assert Address Strobe (AS)
Set R/W to Write
Place Data on Do-DIS
Assert Upper Data Strobe (UDS) and
Lower Data Strobe (LDS)
1) Decode Address
2) Store Data on 0 0 -0 15
3) Assert Data Transfer Acknowledge
(DTACK)
Read-Modify-Write Cycle
The read-modify-write cycle performs a read, modifies the
data in the arithmetic-logic unit, and writes the data back to the
same address. In the HD68000 this cycle is indivisible in that
the address strobe is asserted throughout the entire cycle. The
test and set (TAS) instruction uses this cycle to provide meaningful communication between processors in a mUltiple processor
environment. This instruction is the only instruction that uses
the read-modify-write cycles and since the test and set instruction only operates on bytes, all read-modify-write cycles are
byte operations. A read-modify-write cycle flow chart is given in
Figure 19 and a timing diagram is given in Figure 20.
I
Terminate 01put Transfer
1) Negate ~ and iJ)S
2) Negate AS
3) Remove Data from Do -0 15
4) Set R/W to ~ead
I
BUS ARBITRATION
Bus arbitration is a technique used by master-type devices to
request, be granted, and acknowledge bus mastership. In its
simplest form, it consists of:
1. Asserting a bus mastership request.
2. Receiving a grant that the bus is available at the end of the
current cycle.
3. Acknowledging that mastership has been assumed.
Figure 21 is a flow chart showing the detail involved in a
request from a single device. Figure 22 is a timing diagram for
the same operations. This technique allows processing of bus
requests during data transfer cycles.
270
Terminate Cycle
1) Negate OT ACK
t
I
Start Next Cycle
Figure 16 Word Write Cycle Flow Chart
------------------------------------H068000----------------------------------BUS MASTER
1)
2)
3)
4)
5)
6)
SLAVE
Address Device
Place Address on AI -A 23
Place Function Code on FC o -FC 2
Assert Address Strobe (AS)
Set R/W to Write
Place Data on Do - 0, or 0 8 - DIS (according to Ao)
Assert Upper Data Strobe (UDS) or Lower
Data Strobe (LOS) (based on Ao)
~
Input Data
1) Decode Address
2) Store Data on Do -0, if LOS is asserted.
Store Data on 0 8 -0 1 S if UDS is asserted.
3) Assert Data Transfer Acknowledge
~
1)
2)
3)
4)
Terminate Output Transfer
Negate UDS and LOS
Negate AS
Remove Data from Do -0, or 0 8 -DIS
Set R/W to Read
~
Terminate Cycle
1) Negate DTACK
I
Start Next Cycle
Figure 17 Byte Write Cycle Flow Chart
H
H
)
)
H
H
A0 *
AS~
UDS
LOS
~./\
DTACK
D'-DIS
0 0 -0,
FCo -FC 2
=:::>--<
::::>-<
I
I
\
\
I
I
\
f\
I
\
)
(
)
(
\
H
)-<
* Internal Signal Only
~
I
\
- - - - Word Write - - -
-+- ---
f\
I
<
>
\
r
r>
>
<
>
--+- ---
Even Byte Write - -
Figure 18 Word and Byte Write Cycle Timing Diagram
271
r
\
H
Odd Byte Write - -
r
\
)
~
------------------------------------H068000-----------------------------------
SLAVE
BUS MASTER
1)
2)
3)
4)
Address Device
Place Address on Al -Au
Set R/W to Read
Assert Address Strobe (AS)
Assert Upper Data Strobe (UDS) or Lower
Data Strobe (U>S)
t
Input Data
1) Decode Address
2) Place Data on Do -0 7 or DB -DIS
3) Assert Data Transfer Acknowledge
(DTACK)
Acquire Data
1) Latch Data
2) Negate ODS or ~
3) Start Data Modification
I
J
Terminate Cycle
1) Remove Data from Do -0 7 or 0 8 -0 15
2) Negate l5i"Aa<
I
t
Start Output Transfer
'
1) Set R/W to Write
2) Place Data on Do -0 7 or 0 8 -0 15
3) Assert Upper Data Strobe (D'DS) or Lower
Data Strobe (LOS)
I
J
Input Data
1) Store Data on Do -0 7 or Os -0 15
2) Assert Data Transfer Acknowledge
,
1)
2)
3)
4)
(DTACK)
Terminate Output Transfer
Negate UDS or LOS
Negate AS'
Remove Data from Do -0 7 or 0, -0 15
Set R/W to ReadLI_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- ,
l
Terminate Cycle
1)
Negate~
I
Start Next Cycle
Figure 19 Read-Modify-Write Cycle Flow Chart
272
-------------------------------------HD68000------------------------------------
\
I
\
UDSor LOS
\
R/W
DTACK
\
I
Os-D,s
<
(
>
>
0 0 -0 7
I
I
\
\
<
(
rr-
>->>-C
FC o -FC,-=>--<
~ - - - - - - - - - - -Indivisible Cycle- - - - - - - - - - ~
Figure 20 Read-Modify-Write Cycle Timing Diagram
The timing diagram shows that the bus request is negated at
the time that an acknowledge is asserted. This type of operation
would be true for a system consisting of the processor and one
device capable of bus mastership. In systems having a number of
devices capable of bus mastership, the bus request line from
each device is wire ORed to the processor. In this system, it is
easy to see that there could be more than one bus request being
made. The timing diagram shows that the bus grant signal is
negated a few clock cycles after the transition of the acknowledge (BGACK) signal.
However, if the bus requests are still pending, the processor
will assert another bus grant within a few clock cycles after it
was negated. This additional assertion of bus grant allows
external arbitration circuitry to select the next bus master
before the current bus master has completed its requirements.
The following paragraphs provide additional information about
the three steps in the arbitration process.
REQUESTING DEVICE
PROCESSOR
Request the Bus
1) Assert Bus Request (BR)
I
t
Grant Bus Arbitration
1) Assert Bus Grant (BG)
t
1)
2)
3)
4)
t
Acknowledge Bus Mastership
External arbitration determines next bus
master
Next bus master waits for current cycle to
complete
Next bus master asserts Bus Grant
Acknowledge (BGACK) to become new
master
Bus master negates BR
I
Terminate Arbitration
1) Negate BG (and wait for BGACK to be negated)
t
Operate as Bus Master
1) Perform Data Transfers (Read and Write
cycles) according to the same rules the
procassor uses.
t
Release Bus Mastership
1) Negate BGACK
Requesting the Bus
External devices capable of becoming bus masters request the
bus by asserting the bus request (BR) signal. This is a wire ORed
signal (although it need not be constructed from open collector
devices) that indicates to the processor that some external
device requires control of the external bus. The processor is
effectively at a lower bus priority level than the external device
and will relinquish the bus after it has completed the last bus
cycle it has started.
When no acknowledge is received before the bus request
signal goes inactive, the processor will continue processing when
it detects that the bus request is inactive. This allows ordinary
processing to continue if the arbitration circuitry responded to
noise inadvertently.
Receiving the Bus Grant
Re·Arbitrate or Resume Processor Operation
Figure 21 Bus Arbitration Cycle Flow-Chart
The processor asserts bus grant (BG) as soon as possible.
Normally this is immediately after internal synchronization. The
only exception to this occurs when the processor has made an
internal decision to execute the next bus cycle but has not
progressed far enough into the cycle to have asserted the address
strobe (AS) signal. In this case, bus grant will not be asserted
until one clock after address strobe is asserted to indicate to
273
------------------------~---------
HD68000----------------------------------
CLK
UDS
LOS
R/W----DTACK
\
BGACK
-----~\====~~I
_------------~\====~-I
\~____________
\~------I
Processor - -
¥
- - DMA Device-
-+ ----
Processor- - - - -
-+- ---
-DMA Device- - -
Figure 22 Bus Arbitration Cycle Timing Diagram
bus error signal. When a bus error signal is received, the
processor has two options: initiate a bus error exception
sequence or try running the bus cycle again.
external devices that a bus cycle is being executed.
The bus grant signal may be routed through a daisy-chained
network or through a specific priority-encoded network. The
processor is not affected by the external method of arbitration
as long as the protocol is obeyed.
Exception Sequence
Acknowledgement of Mastership
Upon receiving a bus grant, the requesting device waits until
address strobe, data transfer acknowledge, and bus grant
acknowledge are negated before issuing its own BGACK. The
negation of the address strobe indicates that the previous master
has completed its cycle, the negation of bus grant acknowledge
indicates that the previous master has released the bus. (While
address strobe is asserted no device is allowed to "break into" a
cycle.) The negation of data transfer acknowledge indicates the
previous slave has terminated its connection to the previous
master. Note that in some applications data transfer acknowledge might not enter into this function. General purpose devices
would then be connected such that they were only dependent
on address strobe. When bus grant acknowledge is issued the
device is bus master until it negates bus grant acknowledge. Bus
grant acknowledge should not be negated until after the bus
cycle(s) is (are) completed. Bus mastership is terminated at the
negation of bus grant acknowledge.
The bus request from the granted device should be dropped
when bus grant acknowledge is asserted. If bus request is still
asserted after bus grant acknowledge is negated, the processor
performs another arbitration sequence and issues another bus
grant. Note that the processor does not perform any external
bus cycles before it re-asserts bus grant.
BUS ERROR AND HALT OPERATION
In a bus architecture that requires a handshake from an
external device, the possibility exists that the handshake might
not occur. Since different systems will require a different
maximum response time, a bus error input is provided. External
circuitry must be used to determine the duration between
address strobe and data transfer acknowledge before issuing a
274
The bus error exception sequence is entered when the
processor receives a bus error signal and the halt pin is inactive.
Figure 23 is a timing diagram for the exception sequence. The
sequence is composed of the following elements:
1. Stacking the program counter and status register
2. Stacking the error information
3. Reading the bus error vector table entry
4. Executing the bus error handler routine
The stacking of the program counter and the status register is
the same as if an interrupt had occurred. Several additional
items are stacked when a bus error occurs. These items are used
to determine the nature of the error and correct it, if possible.
The bus error vector is vector number two located at address
$000008. The processor loads the new program counter from
this location. A software bus error handler routine is then
executed by the processor. Refer to EXCEPTION PROCESSING for additional information.
Rs-Running the Bus Cycle
When the processor receives a bus error signal and the halt
pin is being driven by an external device, the processor enters
the re-run sequence. Figure 24 is a timing diagram for re-running
the bus cycle.
The processor completes the bus cycle, then puts the address,
data and function code output lines in the high-impedance state.
The processor remains "halted," and will not run another bus
cycle until the halt signal is removed by external logic. Then the
processor will re-run the previous bus cycle using the same
address, the same function codes, the same data (for a write
operation), and the same controls. The bus error signal should
be removed before the halt signal is removed.
-------------------------------------HD68000-----------------------------------elK
\~------------------------------~//
,~-------
uos------~\
~----
__ ,
~
~----~\
---------
·r.-------~
I
'''''____
~
RM
OTACR--------------------------------------------------~ ~
\
oa-Ols----S{~~~~~~~~~~~~~~. .-_;:====
0
0 -0,
FC o -FC 2
~
:::>-<
~======
(
~
\
HALT
..
fE-1 nltlate
Read
+-
- - Response Failure- -
-+
'~----~=======
~,-----------------C
·
-1-..... E- Initiate
Bus Error Detection +yele
Termlnates..,....,-- - - Bus
-.- - rror Stacking
Figure 23 Bus Error Timing Diagram
eLK
)
I
I
I
\
ODS"
\
\
lOS
(
\
\
I
I
\
I
R/W
\
oTACK
oa-o,s
(
0 0 -0,
(
Fe o -FC 2
BERR
HALT
::J-<
)
(
>
(
)
\
\
~ - - - - - Read- - - -
<
/
+- --
I
------;-Halt - - - - - - - - -
-+--
Figure 24 Re-Run Bus Cycle Timing Information
275
---Rerun- - - -
r-
}-
>->-C
~
HD68000--------------------------------[NOTE] The processor will not re-run a read-modify-write
cycle. This restriction is made to guarantee that the
entire cycle runs correctly and that the write operation of a Test-and-Set operation is performed without
ever releasing AS.
processor is honoring the halt request, bus arbitration performs
as usual. That is, halting has no effect on bus arbitration. It is
the bus arbitration function that removes the control signals
from the buso
The halt function and the hardware trace capability allow the
hardware debugger to trace single bus cycles or single instructions at a time. These processor capabilities, along with a
software debugging package, give total debugging flexibility.
Halt Operation with No Bus Error
The halt input signal to the HD68000 performs a Halt/Run/
Single-Step function in a similar fashion to the HMCS6800 halt
function. The halt and run modes are somewhat self explanatory in that when the halt signal is constantly active the
processor "halts" (does nothing) and when the halt signal is
constantly jnactive the processor "runs" (does something).
The single-step mode is derived from correctly timed
transitions on the halt signal input. It forces the processor to
execute a single bus cycle by entering the "run" mode until the
processor starts a bus cycle then changing to the "halt" mode.
Thus, the single-step mode allows the user to proceed through
(and therefore debug) processor operations one bus cycle at a
time.
Figure 25 details the timing required for correct single-step
operations. Some care must be exercised to avoid harmful
interactions between the bus error signal and the halt pin when
using the single cycle mode as a debugging tool. This is also true
of interactions between the halt and reset lines since these can
reset the machine.
When the processor completes a bus cycle after recognizing
that the halt signal is active, most three-state signals are put in
the high-impedance state. These include:
1. address lines
2. data lines
3. function code lines
This is required for correct performance of the re-run bus
cycle operation.
Note that when the processor honors a request to halt, the
function codes are put in the high-impedance state (their buffer
characteristics are the same as the address buffers). While the
uos
urs
R/W
\
I
\
\
I
DTACK
\
(
0 0 -0 7
(
:::>-<
~-
RESET OPERATION
The reset signal is a bidirectional signal that allows either the
processor or an external signal to reset the system. Figure 26 is a
timing diagram for reset operations. Both the halt and the reset
I
/
\
I
r-
\
)
(
>
(
<
)
- - -Read- - - - -
\
\
I
\
HALT
When a bus error exception occurs, the processor will
attempt to stack several words containing information about the
state of the machine. If a bus error exception occurs during the
stacking operation, there have been two bus errors in a row.
This is commonly referred to as a double bus fault. When a
double bus fault occurs, the processor will halt. Once a bus error
exception has occurred, any bus error exception occurring
before the execution of the next instruction constitutes a
double bus fault.
Note that a bus cycle which is re-run does not constitute a
bus error exception, and does not contribute to a double bus
fault. Note also that this means that as long as the external
hardware requests it, the processor will continue to re-run the
same bus cycle.
The bus error pin also has an effect on processor operation
after the processor receives an external reset input. The
processor reads the vector table after a reset to determine the
address to start program execution. If a bus error occurs while
reading the vector table (or at any time before the first
instruction is executed), the processor reacts as if a double bus
fault has occurred and it halts. Only an external reset will start a
halted processor.
I
0 8 -0 15
FC o -FC 2
Double Bus Faults
+ -------
I
Halt - - - - - -
+ -----
Figure 25 Halt Signal Timing Characteristics
276
Read - - - -
>->->-<=
~
------------------------------------HD68000----------------------------------ClK
Plus 5 Volts
Vee
RES
1
HALT
1
t
~
>
100
Milliseconds~,....---------------
I
t<4
Bus Cycles
(2)
(3)
[NOTES]
(1) Internal start-uptime (4) PC High read in here
Bus State Unknown:
(2) SSP High read in here (5) PC low read in here
(3) SSP low read in here (6) First instruction fetched here.
All Control Signal Inactive.
Data Bus in Read Mode:
(4)
(5)
(6)
'#:I::I::X
>---<
Figure 26 Reset Operation Timing Diagram
lines must be applied to ensure' total reset of the processor.
When the reset and halt lines are driven by an external
device, it is recognized as an entire system reset, including the
processor. The processor responds by reading the reset vector
table entry (vector number zero, address $000000) and loads it
into the supervisor stack pointer (SSP). Vector table entry
number one at address $000004 is read next and loaded into the
program counter. The processor initializes the status register to
an interrupt level of seven. No other registers are affected by the
reset sequence.
When a RESET sequence is executed, the processor drives
the reset pin for 124 clock pulses. In this case, the processor is
trying to reset the rest of the system. Therefore, there is no
effect on the internal state of the processor. All of the
processor's internal registers and the status register are unaffected by the execution of a RESET instruction. All external
devices connected to the reset line. should be reset at the
completion of the RESET instruction.
When Vee is initially applied to the processor, an external
reset must be applied to the reset pin for 100 milliseconds.
•
interrupt, by a bus error, or by a reset. Exception processing is
designed to provide an efficient context switch so that the
processor may handle unusual conditions.
The halted processing state is an indication of catastrophic
hardware failure. For example, if during the exception processing of a bus error another bus error occurs, the processor
assumes that the system is unusable and halts. Only an external
reset can restart a halted processor. Note that a processor in the
stopped state is not in the halted state, nor vice versa.
•
EXCEPTION PROCESSING
The following paragraphs describe the actions of the HD68000
which are outside the normal processing associated with the
execution of instructions. The functions of the bits in the
supervisor portion of the status register are covered: the
supervisor/user bit, the trace enable bit, and the processor
interrupt priority mask. Finally, the sequence of memory
references and actions taken by the processor on exception
conditions is detailed.
•
PRIVILEGE STATES
The processor operates in one of two states of privilege: the
"user" state or the "supervisor" state. The privilege state
determines which operations are legal, is used by the external
memory management device to control and translate accesses,
and is used to choose between the supervisor stack pointer and
the user stack pointer in instruction references.
The privilege state is a mechanism for providing security in a
computer system. Programs should access only their own code
and data areas, and ought to be restricted from accessing
information which they do not need and must not modify.
The privilege mechanism provides security by allowing most
programs to execute in user state. In this state, the accesses are
controlled, and the effects on other parts of the system are
limited. The operating system executes in the supervisor state,
has access to all resources, and performs the overhead tasks for
the user state programs.
SUPERVISOR STATE
The supervisor state is the higher state of privilege. For
instruction execution, the supervisor state is determined by the
S-bit of the status register; if the S-bit is asserted (high), the
processor is in the supervisor state. All instructions can be
executed in the supervisor state. The bus cycles generated by
instructions executed in the supervisor state are classified as
supervisor references. While the processor is in the supervisor
privilege state, those instructions which use either the system
stack pointer implicitly or address register seven explicitly
access the supervisor stack pointer.
All exception processing is done in the supervisor state,
regardless of the setting of the S-bit. The bus cycles generated
during exception processing are classified as supervisor references. All stacking operations during exception processing use
the supervisor stack pointer.
PROCESSING STATES
The HD68000 is always one of three processing states:
normal, exception, or halted. The normal processing states is
that associated with instruction execution; the memory references are to fetch instructions and operands, and to store
results. A special case of the normal state is the stopped state
which the processor enters when a STOP instruction is
executed. In this state, no further memory references are made.
The exception processing state is associated with interrupts,
trap instructions, tracing and other exceptional conditions. The
exception may be internally generated by an instruction or by
an usual condition arising during the execution of an instruction. Externally, exception processing can be forced by an
277
-----------------------------------HD68000---------------------------------USER STATE
Table 17 Reference Classification
The user state is the lower state of privilege. For instruction
execution, the user state is determined by the S-bit of the status
register; if the S-bit is negated (low), the processor is executing
instructions in the user state.
Most instructions execute the same in user state as in the
supervisor state. However, some instructions which have important system effects are made privileged. User programs are
not permitted to execute the STOP instruction, or the RESET
instruction. To ensure that a user program cannot enter the
supervisor state except in a controlled manner, the instructions
which modify the whole status register are privileged. To aid in
debugging programs which are to be used as operating systems,
the move to user stack pointer (MOVE USP) and move from
user stack pointer (MOVE from USP) instructions are also
privileged.
The bus cycles generated by an instruction executed in user
state are classified as user state references. This allows an
external memory management device to translate the address
and to control access to protected portions of the address space.
While the processor is in the user privilege state, those
instructions which use either the system stack pointer implicity,
or address register seven explicity, access the user stack pointer.
Function Code Output
FCo
FC2
FC!
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Reference Class
(Unassigned)
User Data
User Program
(Unassigned)
(Unassigned)
Supervisor Data
Supervisor Program
Interrupt Acknowledge
processing of an exception occurs in four steps, with variations
for different exception causes. During the first step, a temporary copy of the status register is made, and the status register
is set for exception processing. In the second step the exception
vector is determined, and the third step is the saving of the
current processor context In the fourth step a new context is
obtained, and the processor switches to instruction processing.
PRIVILEGE STATE CHANGES
EXCEPTION VECTORS
Once the processor is in the user state and executing
instructions, only exception processing can change the privilege
state. During exception processing, the current setting of the
S-bit of the status register is saved and the S-bit is asserted,
putting the processing in the supervisor state. Therefore, when
instruction execution resumes at the address specified to process
the exception, the processor is in the supervisor privilege state.
Exception vectors are memory locations from which the
processor fetches the address of a routine which will handle that
exception. All exception vectors are two words in length (Figure
27), except for the reset vector, which is four words. All
exception vectors lie in the supervisor data space, except for the
reset vector which is in the supervisor program space. A vector
number is an eight-bit number which, when multiplied by four,
gives the address of an exception vector. Vector numbers are
generated internally or externally, depending on the cause of
the exception. In the case of interrupts, during the interrupt
acknowledge bus cycle, a peripheral provides an 8-bit vector
number (Figure 28) to the processor on data bus lines DO
through 07. The processor translates the vector number into a
full 24-bit address, as shown in Figure 29. The memory layout
for exception vectors is given in Table 18.
As shown in Table 18, the memory layout is 512 words long
(1024 bytes). It starts at address 0 and proceeds through address
1023. This provides 255 unique vectors; some of these are
REFERENCE CLASSIFICATION
When the processor makes a reference, it classifies the kind
of reference being made, using the encoding on the three
function code output lines. This allows external translation of
addresses, control of access, and differentiation of special
processor states, such as interrupt acknowledge. Table 17 lists
the classification of references.
•
EXCEPTION PROCESSING
Before discussing the details of interrupts, traps, and tracing,
a general description of exception processing is in order. The
Word 0
New Program Counter (High)
Word 1
New Program Counter (Low)
Figure 27 Exception Vector Format
Ignored
Iv, Iv·1 v, Iv·1 v, Iv, Iv, Iv·1
Where: V 7 is the MSB of the Vector Number
Vo is the LSB of the Vector Number
Figure 28 Peripheral Vector Number Format
278
------------------------------------H068000-----------------------------------
All Zeroes
Figure 29 Address Translated from 8-Bit Vector Number
Table 18 Exception Vector Assignment
Vector
Number(s)
Address
Assignment
Space
Dec
Hex
0
0
000
SP
Reset: Initial SSP
-
4
004
SP
Reset: Initial PC
2
8
008
SO
Bus Error
3
12
OOC
SO
Address Error
4
16
010
SO
Illegal Instruction
5
20
014
SO
Zero Divide
6
24
018
SO
CHK Instruction
7
28
01C
SO
TRAPV Instruction
8
32
020
SO
Privilege Violation
9
36
024
SO
Trace
10
40
028
SO
Line 1010 Emulator
11
44
02C
SO
Line 1111 Emulator
12*
48
030
SO
(Unassigned, reserved)
(Unassigned, reserved)
13*
52
034
SO
14*
56
038
SO
(Unassigned, reserved)
15
60
03C
SO
Unitialized Interrupt Vector
SO
(Unassigned, reserved)
SO
Spurious Interrupt
16-23*
24
64
04C
95
05F
96
060
----
._-"----
-
25
100
064
SO
Level 1 Interrupt Autovector
26
104
068
SO
Level 2 Interrupt Autovector
27
108
06C
SO
Level 3 Interrupt Autovector
28
112
070
SO
Level 4 Interrupt Autovector
29
116
074
SO
Level 5 Interrupt Autovector
30
120
078
SO
Level 6 Interrupt Autovector
31
124
07C
SO
Level 7 Interrupt 'Autovector
32-47
128
080
SO
TRAP Instruction Vectors
191
08F
48-63*
192
OCO
SO
(Unassigned, reserved)
255
OFF
64-255
256
100
SO
User Interrupt Vectors
1023
3FF
-
-
* Vector numbers 12, 13, 14, 16 through 23 and 48 through 63 are reserved for future enhancements by Hitachi_ No user peripheral devices should be
assigned these numbers.
279
------------------------------------HD68000----------------------------------reserved for TRAPS and other system functions. Of the 255,
there are 192 reserved for user interrupt vectors. However, there
is no protection on the first 64 entries, so user interrupt vectors
may overlap at the discretion of the systems designer.
KINDS OF EXCEPTIONS
Exceptions can be generated by either internal or external
causes. The externally generated exceptions are the interrupts
and the bus error and reset requests. The interrupts are requests
from peripheral devices for processor action while the bus error
and reset inputs are used for access control and processor
restart. The internally generated exceptions come from instructions, or from address errors or tracing. The trap (TRAP), trap
on overflow (TRAPV), check register against bounds (CHK) and
divide (DIV) instructions all can generate exceptions as part of
their instruction execution. In addition, illegal instructions,
word fetches from odd addresses and privilege violations cause
exceptions. Tracing behaves like a very high priority, internally
generated interrupt after each instruction execution.
EXCEPTION PROCESSING SEQUENCE
Exception processing occurs in four identifiable steps. In the
first step, an internal copy is made of the status register. After
the copy is made, the S-bit is asserted, putting the processor
into the supervisor privilege state. Also, the T-bit is negated
which will allow the exception handler to execute unhindered
by tracing. For the reset and interrupt exceptions, the interrupt
priority mask is also updated.
In the second step, the vector number of the exception is
determined. For interrupts, the vector number is obtained by a
processor fetch, classified as an interrupt acknowledge. For all
other exceptions, internal logic provides the vector number.
This vector number is then used to generate the address of the
exception vector.
The third step is to save the current processor status, except
for the reset exception. The current program counter value and
the saved copy of the status register are stacked using the
supervisor stack pointer. The program counter value stacked
usually points to the next unexecuted instruction, however for
bus error and address error, the value stacked for the program
counter is unpredictable, and may be incremented from the
address of the instruction which caused the error. Additional
information derming the current context is stacked for the bus
error and address error exceptions.
The last step is the same for all exceptions. The new program
counter value is fetched from the exception vector. The
processor then resumes instruction execution. The instruction at
the address given in the exception vector is fetched, and normal
instruction decoding and execution is started.
MU LTIPLE EXCEPTIONS
These paragraphs describe the processing which occurs when
mUltiple exceptions arise simultaneously. Exceptions can be
grouped according to their occurrence and priority. The Group
o exceptions are reset, bus error, and address error. These
exceptions cause the instruction currently being executed to be
aborted, and the exception processing to commence at the next
minor cycle of the processor. The Group 1 exceptions are trace
and interrupt, as well as the privilege violations and illegal
instructions. These exceptions allow the current instruction to
execute to completion, but preempt the execution of the next
instruction by forcing exception processing to occur (privilege
violations and illegal instructions are detected when they are the
next instruction to be executed). The Group 2 exceptions occur
as part of the normal processing of instructions. The TRAP,
TRAPV, CHK, and zero divide exceptions are in this group. For
these exceptions, the normal execution of an instruction may
lead to exception processing.
Group 0 exceptions have highest priority, while Group 2
exceptions have lowest priority. Within Group 0, reset has
highest priority, followed by bus error and then address error.
Within Group I, trace has priority over external interrupts,
which in turn takes priority over illegal instruction and privilege
violation. Since only one instruction can be executed at a time,
there is no priority relation within Group 2.
The priority relation between two exceptions determines
which is taken, or taken first, if the conditions for both arise
simultaneously. Therefore, if a bus error occurs during a TRAP
instruction, the bus error takes precedence, and the TRAP
instruction processing is aborted. In another example, if an
interrupt request occurs during the execution of an instruction
while the T-bit is asserted, the trace exception has priority, and
is processed first. Before instruction processing resumes, however, the interrupt exception is also processed, and instruction
processing commences finally in the interrupt handler routine.
A summary of exception grouping and priority is given in Table
19.
Table 19 Exception Grouping and Priority
Group
Exception
Reset
0
Bus Error
Address Error
Processing
Exception processing begins at
the next minor cycle
Trace
1
Interrupt
Exception processing begins
II/egal
before the next instruction
Privilege
TRAP, TRAPV,
2
CHK,
Zero Divide
•
Exception processing is started
by normal instruction execution
EXCEPTION PROCESSING DETAILED DISCUSSION
Exceptions have a number of sources, and each exception has
processing which is peculiar to it. The following paragraphs
detail the sources of exceptions, how each arises, and how each
is processed.
RESET
The reset input provides the highest exception level. The
processing of the reset signal is designed for system initiation,
and recovery from catastrophic failure. Any processing in
progress at the time of the reset is aborted and cannot be
recovered. The processor is forced into the supervisor state, and
the trace state is forced off. The processor interrupt priority
mask is set at level seven. The vector number is internally
generated to reference the reset exception vector at location 0
in the supervisor program space. Because no assumptions can be
made about the validity of register contents, in particular the
supervisor stack pointer, neither the program counter nor the
status register is saved. The address contained in the first two
words of the reset exception vector is fetched as the initial
supervisor stack pointer, and the address in the last two words
2800f the reset exception vector is fetched as the initial program
------------------------------------H068000----------------------------------counter. Finally, instruction execution is started at the address
in the program counter. The power-up/restart code should be
pointed to by the initial program counter.
The RESET instruction does not cause loading of the reset
vector, but does assert the reset line to reset external devices.
This allows the software to reset the system to a known state
and then continue processing with the next instruction.
proceeds with the usual exception processing, saving the
program counter and status register on the supervisor stack. The
saved value of the program counter is the address of the
instruction which would have been executed had the interrupt
not been present. The content of the interrupt vector whose
vector number was previously obtained is fetched and loaded
into the program counter, and normal instruction execution
commences in the interrupt handling routine. A flow chart for
the interrupt acknowledge sequence is given in Figure 30; a
timing diagram is given in Figure 31.
INTERRUPTS
Seven levels of interrupt priorities are provided. Devices may
be chained externally within interrupt priority levels, allowing
an unlimited number of peripheral devices to interrupt the
processor. Interrupt priority levels are numbered from one to
seven, level seven being the highest priority. The status register
contains a three bit mask which indicates the current processor
priority, and interrupts are inhibited for all priority levels less
than or equal to the current processor priority.
An interrupt request is made to the processor by encoding
the interrupt request level on the interrupt request.lines; a zero
indicates no interrupt request. Interrupt requests arriving at the
processor do not force immediate exception processing, but are
made pending. Pending interrupts are detected between instruc·
tion executions. If the priority of the pending interrupt is lower
than or equal to the current processor priority, execution
continues with the next instruction and the interrupt exception
processing is postponed. (The recognition of level seven is
slightly different, as explained in a following paragraph.)
If the priority of the pending interrupt is greater than the
current processor priority, the exception processing sequence is
started. First a copy of the status register is saved, and the
priVilege state is set to supervisor, tracing is suppressed, and the
processor priority level is set to the level of the interrupt being
acknowledged. The processor fetches the vector number from
the interrupting device, classifying the reference as an interrupt
acknowledge and displaying the level number of the interrupt
being acknowledged on the address bus. If external logic
requests an automatic vectoring, the processor internally generates a vector number which is determined by the interrupt level
number. If external logic indicates a bus error, the interrupt is
taken to be spurious, and the generated vector number
references the spurious interrupt vector. The processor then
PROCESSOR
INTERRUPTING DEVICE
Request Interrupt
t
Grant Interrupt
1) Compare interrupt level in status register
and wait for current instruction to complete
2) Place interrupt level on AI • A 2 • A3
3) Set R/W to read
4) Set function code to interrupt acknowledge
5) Assert address strobe (AS)
6) Assert lower data strobe (LOS)
I
.
2) Assert data transfer acknowledge (OTACK)
I
+
Acquire Vector Number
1) Latch vector number
2) Negate LOS
3) Negate AS
1) Negate
t
I
I
I
\
\
UOS
ms
\
R/W
\
OTACK
(
(
OS-015
0 0 -0,
FC o -FC 2
IPLo -IPL 2
::>-<
.
Figure 30 Interrupt Acknowledge Sequence Flow Chart
\
\
\
I
)
)
}-J
\
r=---
-Read Cycle- - -
-+- --
of ACK
Start Interrupt Processing
H
AS
f
PrOVide Vector Number
1) Place vector number of Do -0 7
-Vector Number Acquisition - -
4
Figure 31 Interrupt Acknowledge Sequence Timing Diagram
281
-----------------------------------HD68000---------------------------------TRACING
Priority level seven is a special case. Level seven interrupts
cannot be inhibited by the interrupt priority mask, thus
providing a "non-maskable interrupt" capability. An interrupt is
generated each time the interrupt request level changes from
some lower level to level seven. Note that a level seven interrupt
may still be caused by the level comparison if the request level is
a seven and the processor priority is set to a lower level by an
instruction.
To aid in program development, the HD68000 includes a
facility to allow instruction by instruction tracing. In the trace
state,. after each instruction is executed an exception is forced,
allowing a debugging program to monitor the execution of the
program under test.
The trace facility uses the T-bit in the supervisor portion of
the status register. If the T-bit is negated (oft), tracing is
disabled, and instruction execution proceeds from instruction to
instruction as normal. If the T-bit is asserted (on) at the
beginning of the execution of an instruction, a trace exception
will be generated after the execution of that instruction is
completed. If the instruction is not executed, either because an
interrupt is taken, or the instruction is illegal or privileged, the
trace exception does not occur. The trace exception also does
not occur if the instruction is aborted by a reset, bus error, or
address error exception. If the instruction is indeed executed
and an interrupt is pending on completion, the trace exception
is processed before the interrupt exception. If, during the
execution of the instruction, an exception is forced by that
instruction, the forced exception is processed before the trace
exception.
As an extreme illustration of the above rules, consider the
arrival of an interrupt during the execution of a TRAP
instruction while tracing is enabled. First the trap exception is
processed, then the trace exception, and finally the interrupt
exception. Instruction execution resumes in the interrupt
handler routine.
INSTRUCTION TRAPS
Traps are exceptions caused by instructions. They arise either
from processor recognition of abnormal conditions during
instruction execution, or from use of instructions whose normal
behavior is trapping.
Some instructions are used specifically to generate traps. The
TRAP instruction always forces an exception, and is useful for
implementing system calls for user programs. The TRAPV and
CHK instructions force an exception if the user program detects
a runtime error, which may be an arithmetic overflow or a
subscript out of bounds.
The signed divide (DNS) and unsigned divide (DNU)
instructions will force an exception if a division operation is
attempted with a divisor of zero.
I LLEGAL AND UNIMPLEMENTED INSTRUCTIONS
Illegal instruction is the term used to refer to any of the
word bit patterns which are not the bit pattern of the first word
of a legal instruction. During instruction execution, if such an
instruction is fetched, an illegal instruction exception occurs.
Word patterns with bits 15 through 12 equaling 10 10 or
1111 are distinguished as unimplemented instructions and
separate exception vectors are given to these patterns to perm it
efficient emulation. This facility allows the operating system to
detect program errors, or to emulate unimplemented instructions in software.
BUS ERROR
Bus error exceptions occur when the external logic requests
that a bus error be processed by an exception. The current bus
cycle which the processor is making is then aborted. Whether
the processor was doing instruction or exception processing,
that processing is terminated, and the processor immediately
begins exception processing.
Exception processing for bus error follows the usual sequence of steps. The status register is copied, the supervisor
state is entered, and the trace state is turned off. The vector
number is generated to refer to the bus error vector. Since the
processor was not between instructions when the bus error
exception request was made, the context, additional information is saved on the supervisor stack. The program counter and
the copy of the status register are of course saved .. The value
PRIVILEGE VIOLATIONS
In order to provide system security, various instructions are
privileged. An attempt to execute one of the privileged
instructions while in the user state will cause an exception. The
privileged instructions are:
STOP
AND (word) Immediate to SR
RESET
EOR (word) Immediate to SR
RTE
OR (word) Immediate to SR
MOVE to SR
MOVE USP
15
14
13
12
11
10
8
9
7
6
5
4
3
Lower Address
2
o
Function Code
- -
High
'Access Address- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - _.
Low
Instruction Register
Status Register
High
~ - - Program Counter - - - - -
- - - - - - - - - - - - - - -- - -- - - - - - - - - - - Low
R/W (read/write): write = 0, read = 1, I/N (instruction/not); instruction = 0, not
Figure 32 Supervisor Stack Order
282
=1
-----------------------------------HD68000---------------------------------saved for the program counter is advanced by some amount,
two to ten bytes beyond the address of the first word of the
instruction which made the reference causing the bus error. If
the bus error occurred during the fetch of the next instruction,
the saved program counter has a value in the vicinity of the
current instruction, even if the current instruction is a branch, a
jump, or a return instruction. Besides the usual infonnation, the
processor saves its internal copy of the first word of the
instruction being processed, and the address which was being
accessed by the aborted bus cycle. Specific infonnation about
the access is also saved: whether it was a read or a write,
whether the processor was processing an instruction or not, and
the classification displayed on the function code outputs when
the bus error occurred. The processor is processing an instruction if it is in the nonnal state or processing a Group 2
exception; th.e processor is not processing an instruction if it is
processing a Group 0 or a Group 1 exception. Figure 32
illustrates how this infonnation is organized on the supervisor
stack. Although this information is not sufficient in general to
effect full recovery from the bus error, it does allow software
diagnosis. Finally, the processor commences instruction processing at the address contained in the vector. It is the responsibility
of the error handler routine to clean up the stack and detennine
where to continue execution.
If a bus error occurs during the exception processing for a
bus error, address error, or reset, the processor is halted, and all
processing ceases. This simplifies the detection of catastrophic
system failure, since the processor removes itself from the
system rather than destroy all memory contents. Only the
RESET pin can restart a halted processor.
PROCESSOR
t
Define HMCS 6800 Cycle
1) External hardware asserts Vaidl Peripheral
Address (VPA)
t
Synchronize With Enable
1) The processor monitors Enable (E) until it is
low (Phase 1 )
2) The processor asserts Valid Memory Address
(VMA)
,
Transfer Data
1) The. per.ipheral waits until E is active and then
transfers the data
+
Terminate Cycle
1) The processor waits until E goes low.
(On a Read cycle the data is latched as
E goes low internally)
2) The processor negates VMA
3) The processor negates~, Ol5S, and Ci5S
•
Start Next Cycle
ADDRESS ERROR
Figure 33 HMCS6800 Interfacing Flow Chart
Address error exceptions occur when the processor attempts
to access a word or a long word operand or an instruction at an
odd address. The effect is much like an internally generated bus
error, so that the bus cycle is aborted, and the processor ceases
whatever processing it is currently doing and begins exception
processing. After exception processing commences, the sequence is the same as the for bus error including the
information that is stacked, except that the vector number
refers to the address error vector instead. Likewise, if an address
error occurs during the exception processing for a bus error,
address error, or reset, the processor is halted.
•
SLAVE
Initiate Cycle
1) The processor starts a normal Read or
Write cycle
•
DATA TRANSFER OPERATION
Three signals on the processor provide the HMCS6800
interface. They are: enable (E), valid memory address (VMA),
and valid peripheral address (VPA). Enable corresponds to the E
or <
X
>-<
AS~
1\
UOS~
lOS~
""
R/W
OTACK~
°S-015
0 0 -0 7
FC o -FC 2
E
VISA
VMA
(
--<:::)
--<:::)
X
C
X
\
>--<
>--<
I
\
~ Normal ~
(""'"" - Cvde - ~ - - -HMCS6800 Peripheral Read Cycle- - -
r
K
L
\
---1-..
r
r
....J
-r HMCS6800 Peripheral Write Cycle i
Figure 34 HMCS6800 Cycle Operation
284
X
>>-
>-<
1\
I
\
I
I
I
HD68000 ClK
periPhera~,
*
70 ns
Type B
140 ns
Type A
140 ns
Std
HMCS6800*
150 ns~ Type B
180 ns
Type A
270 ns
.Std
HMCS6800 VMA, R/W
E
HMCS6800 E Clock Freq.
t=
...-----
~
~
!E-- 10 ns HMCS6800*
A
1.0MHz
Std
Perir-heral *
~ 10 ns Peripheral *
~ ~ 10 ns HMCS6800·
TypeB~180ns~
Type
A
220 ns
HMCS6800 R"'" D...
Std
r
.",.homl
I) r - - - -
320 "'
10",
--$#//$
Type B
Type A
Std
(X)
B
1.5 MHz
'f(///~/1
HMCS6800 Address
I\)
Type
2.0 MHz
~peri~~e~:3'* I
SO ns
195 ns
~~
HMCS6S00 Write Data
)~_ _ _ _ _ _ __
01
%
C
G)
HD6S000 Address
>--@"&'»)o----------
AS
VPA
II!!I
~
HD68000 (S MHz)
j.E-200ns~
VMA
~
Write Data
HD68000 ClK
* Times are expressed for different device clock frequencies.
Figure 35 HD68000 to HMCS6800 Peripheral Timing Diagram
CD
o
o
o
-----------------------------------H068000----------------------------------
AS
UOS
LOS
Rm--~===---~======================~~
OTACK'---I
08-015~~----------------------------------------0-0 ----<:::::>~----------------------------------------FC o -FC
}-I
'-C
0
7
2 )-(
O
IPL -IPL
2
~,~::::::::::;---------------~::::::::~~----
L-
E
VPA~~~~~__~_-_~_\==========\-----------~
\ - _ _ _ _ _ _1r--
VMA
_1- - - - ---r- - - I- -Normal
Cycle
_I
- - - - Autovector Operation - - - - - - -----,
Figure 36 Autovector Operation Timing Diagram
Memory If an effective address mode may be used to refer to
memory operands, it is considered a memory addressing effective address mode.
Alterable If an effective address mode may be used to refer to
alterable (write able) operands, it is considered an
alterable addressing effective address mode.
Control If an effective address mode may be used to refer to
memory operands without an associated size, it is
considered a control addressing effective address
mode.
Table 20 shows the various categories to which each of the
effective address modes belong. Table 21 is the instruction set
summary.
The status register addressing mode is not permitted unless it
is explicitly mentioned as a legal addressing mode.
These categories may be combined, so that additional, more
restrictive, classifications may be defined. For example, the
instruction descriptions use such classifications as alterable
memory or data alterable. The former refers to those addressing
modes which are both alterable and memory addresses, and the
Table 20 Effective Addressing Mode Categories
Effective
Address
Register
Data
Memory
Control
Alterable
000
001
010
011
100
101
110
111
111
Register number
X
-
Register number
-
-
-
X
Register number
X
X
X
X
Register number
X
X
-
X
Register number
X
X
-
X
Register number
X
X
X
X
000
001
X
X
X
X
X
X
X
X
111
111
111
010
X
X
X
-
all
X
X
X
100
X
X
-
-
Modes
Dn
An
An@
An@+
An@An@(d)
An@ (d, ix)
xxx. W
xxx. L
PC@(d)
PC@ (d, ix)
#xxx
Addressing Categories
Mode
X
Register number
286
------------------------------------ HD68000----------------------------------Table 21 Instruction Set
Condition Codes
N Z V C
* U * U *
Operation
Description
Mnemonic
X
(Destination)lO + (Source) 10 ~ Destination
(Destination) + (Source) ~ Destination
(Destination) + (Source) ~ Destination
*
*
*
*
*
-
-
-
-
-
Add Extended
(Destination) + Immediate Data ~ Destination
(Destination) + Immediate Data ~ Destination
(Destination) + (Source) + X ~ Destination
*
*
*
*
*
*
(Destination A (Source)
0
0
0
0
*
*
*
*
*
*
*
*
*
*
AND Logical
*
*
*
*
*
*
-
-
-
Add Decimal with Extend
Add Binary
ABCD
ADD
ADDA
Add Address
ADDI
ADDQ
Add Immediate
Add Quick
ADDX
AND
ANDI
AND Immediate
(Destination) A Immediate Data ~ Destination
-
ASL,ASR
Arithmetic Shift
(Destination) Shifted by ~ Destination
Bee
Branch Conditionally
If CC then PC + d
BCHG
Test a Bit and Change
BCLR
Test a Bit and Clear
BRA
Branch Always
~
~
-
Destination
PC
*
-
-
-
-
*
-
-
-
-
*
-
-
-
-
-
-
-
-
-
*
-
-
--
~«bit
BSET
BSR
BTST
CHK
CLR
CMP
CMPA
CMPI
CMPM
DBee
DIVS
DIVU
EOR
number» OF Destination ~ Z
«bit number» OF Destination ~
OF Destination
~ «bit number» OF Destination ~ Z
o~ OF Destination
PC + d ~ PC
*
~
~«bit
number» OF Destination ~ Z
1 ~ OF Destination
PC ~ SP@ -; PC + d ~ PC
Test Bit and Set
Branch to Subroutine
Test a Bit
Check Register against Bound
Clear an Operand
Compare
Compare Address
Compare Immediate
Compare Memory
Test Condition,
Decrement and Branch
Signed Divide
-
~«bit
number» OF Destination ~ Z
If Dn <0 or Dn> «ea» then TRAP
o ~ Destination
(Destination) - (Source)
(Destination) - (Source)
(Destination) - Immediate Data
(Destination) - (Source)
If
~
CC then Dn -1
~
Dn; if Dn =f -1 then PC + d
(Destination)/(Source)
~
Destination
PC
-
*
*
*
*
*
*
*
*
-
-
-
-
-
-
*
*
*
*
*
*
*
*
*
0
(Destination) @ Immediate Data ~ Destination
-
EXG
EXT
Exchange Register
Rx~Ry
Sign Extend
(Destination) Sign-extended
Jump
Jump to Subroutine
Destination ~ PC
PC ~ SP@ -; Destination ~ PC
-
Load Effective Address
*
0
0
-
-
-
-
- -
*
*
0
*
Destination
-
*
*
0
0
CCR
*
*
*
*
*
SR
*
*
*
*
*
MOVE
Move Data from Source to
Destination
(Source)
~
MOVE to
CCR
Move to Condition Code
(Source)
~
MOVE to
SR
Move to the Status Register
(Source)
~
1
- - -
*
-
(Destination) Shifted by ~ Destination
= Unaffected
0
*
Logical Shift
-
0
0
-
Link and Allocate
= Undefined
0
-
LSL, LSR
U
-
l'
-
LINK
0'" Cleared
-
0
-
Destination ~ An
An ~ SP@ -; SP ~ An; SP + d
* = Affected
U
0
1
Exclusive OR Immediate
JSR
LEA
U
*
*
*
*
EORI
JMP
*
*
*
*
*
*
(Destination)/(Source) ~ Destination
(Destination) @ (Source) ~ Destination
Destination
-
0
Unsigned Divide
Exclusive OR Logical
~
-
U
0
~
-
= Set
287
~
SP
-
HD88000-------------------------------Table 21 Instruction Set (Cont.)
MOVE
from SR
MOVE USP
MOVE.A
Move User Stack Pointer
Move Address
USP ~ An; An ~ USP
(Source) ~ Destination
Registers ~ Destination
(Source) ~ Registers
(Source) ~ Destination
Immediate Data -+ Destination
(Destination) * (Source) ~ Destination
(Destination) * (Source) ~ Destination
o- (Destination) 10 - X ~ Destination
0- (Destination) ~ Destination
0- (Destination) - X ~ Destination
MOVEP
MOVEQ
MULS
MULU
NBCD
NEG
NEGX
NOP
NOT
OR
ORI
PEA
RESET
ROL, ROR
ROXL,
ROXR
RTE
Move Peripheral Data
Move Quick
Signed Multiply
Unsigned Multiply
Negate Decimal with Extend
Negate
Negate with Extend
No Operation
Logical Complement
Inclusive OR Logical
Inclusive OR Immediate
Push Effective Address
Reset External Devices
Rotate (Without Extend)
See
STOP
SUB
SUBA
SUBI
SUBQ
SUBX
&NAP
TAS
TRAP
TRAPV
TST
UNLK
Condition Codes
X N Z V C
-
SR
Move Multiple Registers
RTS
SBCD
~
Move from the Status Register
MOVEM
RTR
Operation
Description
Mnemonic
Destination
'" (Destination) ~ Destination
(Destination) v (Source) ~ Destination
(Destination) v Immediate Data -+ Destination
Destination ~ SP@ -
- - - -
- - - - - - - - - - - - - - - - -
*
*
*
*
*
*
U
*
*
*
*
*
*
*
*
0
0
0
U
*
*
0
0
0
*
*
*
- - - - - * * 0 0
-
*
*
0
0
(Destination) Rotated by -+ Destination
- * * 0 0
- - - - - - - - - * * 0 *
Rotate with Extend
(Destination) Rotated by ~ Destination
*
*
*
0
*
Return from Exception
Return and Restore Condition
Codes
Return from Subroutine
Subtract Decimal with Extend
Set According to Condition
Load Status Register and Stop
Subtract Binary
Subtract Address
Subtract Immediate
Subtract Quick
Subtract with Extend
Swap Register Halves
Test and Set and Operand
Trap
Trap on Overflow
Test an Operand
Unlink
SP@ +-+ SR; SP@ +~ PC
*
*
*
*
*
SP@ +~ CC;
*
*
*
*
*
*
U
*
U
*
-
SP@+~
PC
SP@+~PC
(Destinationho - (Sourceho - X -+ Destination
If CC then 1's -+ Destination else O's -+ Destination
Immediate Data ~ SR; STOP
(Destination) - (Source) ~ Destination
(Destination) - (Source) -+ Destination
(Destination) - Immediate Data -+Destination
(Destination) - Immediate Data -+ Destination
(Destination) - (Source) - X -+ Destination
Register [31 :16] ~ Register [15:0]
(Destination) Tested -+ CC; 1 ~ [7] OF Destination
PC ~ SSP@- ; SR ~ SSP@-; (Vector) ~ PC
If V then TRAP
(Destination) Tested ~ CC
An ~ SP; SP@+-+ An
] .. Bit number
288
- - - - *
*
*
*
-
- -
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
*
*
*
*
*
*
*
*
0 0
0 0
- - - - - - - - - * * 0 0
- - - - -
------------------------------------- HD68000-----------------------------------In Table 25, the headings have the following meanings: An =
address register operand, Dn = data register operand, ea = an
operand specified by an effective address, and M = memory
effective address operand.
latter refers to addressing modes which are both data and
alterable.
•
INSTRUCTION EXECUTION TIMES
The following paragraphs contain listings of the instruction
execution times in terms of external clock (eLK) periods. In
this timing data, it is assumed that the memory cycle time is no
greater than four periods of the external processor clock input,
which prevents the insertion of wait states in the bus cycle. The
number of bus read and write cycle for each instruction is also
included with the timing data. This data is enclosed in
parenthesis following the execution periods and is shown as:
(R/W) where R is the number of read cycles and W is the
number of write cycles.
[NOTE] The number of periods includes instruction fetch and
all applicable operand fetches and stores.
•
•
EFFECTIVE ADDRESS OPERAND CALCULATION
TIMING
•
•
SHIFT/ROTATE INSTRUCTION CLOCK PERIODS
Table 28 indicates the number of clock periods for the shift
and rotate instructions. The number of bus read and write
cycles is shown in parenthesis as: (R/W). The number of clock
periods plus the number of read and write cycles must be added
to those of the effective address calculation where indicated.
MOVE INSTRUCTION CLOCK PERIODS
Table 23 and 24 indicate the number of clock periods for the
move instruction. This data includes instruction fetch, operand
reads, and operand writes. The number of bus read and write
cycles is shown in parenthesis as: (R/W).
•
•
SINGLE OPERAND INSTRUCTION CLOCK PERIODS
Table 27 indicates the number of clock periods for the single
operand instructions. The number of bus read and write cycles
is shown in parenthesis as: (R/W). The number of clock periods
plus the number of read and write cycles must be added to
those of the effective address calculation where indicated.
Table 22 lists the number of clock periods required to
compute an instruction's effective address. It includes fetching
of any extension words, the address computation, and fetching
of the memory operand. The number of bus read and write
cycles is shown in parenthesis as (R/W). Note there are no write
cycles involved in processing the effective address.
•
IMMEDIATE INSTRUCTION CLOCK PERIODS
The number of clock periods shown in Table 26 includes the
time to fetch immediate operands, perform the operations, store
the results, and read the next operation. The number of bus
read and write cycles is shown in parenthesis as: (R/W). The
number of clock periods plus the number of read and write
cycles must be added to those of the effective address
calculation where indicated.
In Table 26, the headings have the following meanings: # =
immediate operand, Dn = data register operand, M = memory
operand, and SR =status register.
BIT MANIPULATION INSTRUCTION CLOCK PERIODS
Table 29 indicates the number of clock periods required for
the bit manipulation instructions. The number of bus read and
write cycles is shown in parenthesis as: (R/W). The'number of
clock periods plus the number of read and write cycles must be
added to those of the effective address calculation where
indicated.
STANDARD INSTRUCTION CLOCK PERIODS
The number of clock periods shown in Table 25 indicates the
time required to perform the operations, store the results, and
read the next instruction. The number of bus read and write
cycle is shown in parenthesis as: (R/W). The number of clock
periods plus the number of read and write cycles must be added
to those of the effective address calculation where indicated.
Table 22 Effective Address Calculation Timing
Byte, Word
Addressing Mode
Long
Register
Dn
Data Register Direct
0(0/0)
0(0/0)
An
Address Register Direct
0(0/0)
0(0/0)
An@
Address Register Indirect
4 (1/0)
An@+
Address Register Indirect with Postincrement
4 (1/0)
8 (2/0)
8 (2/0)
An@-
Address Register Indirect with Predecrement
6 (1/0)
10 (2/0)
An@(d)
Address Register Indirect with Displacement
8 (2/0)
12 (3/0)
Memory
An@ (d, ix)*
Address Register Indirect with Index
10 (2/0)
14 (3/0)
xxx. W
Absoiute Short
8 (2/0)
12 (3/0)
xxx. L
Absolute Long
12 (3/0)
16 (4/0)
PC@(d)
Program Counter with Displacement
8 (2/0)
12 (3/0)
PC@ (d, ix)*
Program Counter with Index
10 (2/0)
14 (3/0)
#xxx
Immediate
4 (1/0)
8 (2/0)
* The size of the Index register hx) does not affect execution time.
289
-----------------------------------HD68000---------------------------------Table 23 Move Byte and Word Instruction Clock Periods
Destination
Source
On
An
An@
An@+
An@-
An@(d)
On
4 (1/0)
4«1/0)
9 (1/1)
9 (1/1)
13 (211)
An
An@
4 (1/0)
4 (1/0)
9 (1/1)
9 (1/1)
.9 (111)
9 (1/1)
8 (2/0)
8 (2/0)
13 (2/1)
13 (2/1)
13 (2/1)
An@(d,ix)* xxx.W
xxx.L
15 (2/1)
13 (211)
13 (2/1)
15 (2/1)
13 (2/1)
17 (311)
17 (3/1)
19 (3/1)
17 (3/1)
21 (4/1)
17 (311)
An@+
8 (2/0)
8 (2/0)
13 (2/1)
13 (2/1)
13(2/1)
17 (311)
19 (3/1)
17 (3/1)
21 (411)
An@-
10 (2/0)
10 (2/0)
15 (2/1)
15 (2/1)
15 (3/1)
19 (3/1)
21 (3/1)
19 (3/1)
23 (411)
An@(d)
12 (3/0)
12 (3/0)
17 (3/1)
17 (3/1)
17(3/1)
21 (4/1)
23 (4/1)
21 (4/1)
25 (5/1)
An@ (d, ix)*
14 (3/0)
14 (3/0)
19 (3/1)
19 (3/1)
19(3/1)
23 (4/1)
25 (4/1)
23 (4/1)
27 (511)
xxx.W
12 (3/0)
12 (3/0)
17 (3/1)
17 (3/1)
17 (3/1)
21 (4/1)
23 (4/1)
21 (4/1)
25 (5/1)
xxx. L
16 (4/0)
16 (4/0)
21 (4/1)
21 (4/1)
21 (4/1)
25 (511)
27 (5/1)
25 (5/1)
29 (611)
PC@(d)
12 (3/0)
14 (3/0)
12 (3/0)
14 (3/0)
17 (3/1)
17 (3/1)
19 (3/1)
17 (3/1)
21 (4/1)
23 (411)
21 (4/1)
25 (5/1)
19 (3/1)
19 (3/1)
23 (4/1)
25 (4/1)
23 (4/1)
27 (5/1)
8 (2/0)
8 (2/0)
13 (2/1)
13 (2/1)
13 (211)
17 (311)
19 (3/1)
17 (3/1)
21 (4/1)
PC@ (d, ix)*
#Xxx
• The size of the index register (ix) does not affect execution time.
Table 24 Move Long Instruction Clock Periods
Source
On
Destination
On
4 (1/0)
An
4 (1/0)
An@
An@+
An@-
An@(d)
14 (1/2)
14 (1/2)
16 (1/2)
18 (2/2)
20 (2/2)
An@(d,ix)* xxx.W
18 (2/2)
xxx.L
22 (3/2)
An
An@
4 (1/0)
4 (1/0)
14 (1/2)
14 (1/2)
16 (1/2)
18 (2/2)
20 (2/2)
18 (2/2)
22 (3/2)
12 (3/0)
12 (3/0)
22 (3/2)
22 (3/2)
22 (3/2)
26 (4/2)
28 (4/2)
26 (4/2)
30 (5/2)
An@+
12 (3/0)
12 (3/0)
22 (3/2)
22 (3/2)
22 (3/2)
26 (4/2)
28 (4/2)
26 (4/2)
30 (5/2)
An@An@(d)
14 (3/0)
14 (3/0).
24 (3/2)
24 (312)
24 (3/2)
28 (4/2)
30 (4/2)
28 (4/2)
32 (5/2)
16 (4/0)
16 (4/0)
26 (4/2)
26 (4/2)
26 (4/2)
30 (5/2)
32 (5/2)
30 (5/2)
34 (6/2)
An@ (d, ix)*
18 (4/0)
18 (4/0)
28 (4/2)
28 (4/2)
28 (4/2)
32 (5/2)
34 (5/2)
32 (5/2)
36 (6/2)
xxx.W
16 (4/0)
16 (4/0)
26 (4/2)
26 (4/2)
26 (4/2)
30 (5/2)
32 (5/2)
30 (5/2)
34 (6/2)
xxx. L
20 (5/0)
20 (5/0)
30 (5/2)
30 (5/2)
30 (5/2)
34 (6/2)
36 (6/2)
34 (6/2)
38 (7/2)
PC@(d)
16 (4/0)
16 (4/0)
26 (4/2)
26 (4/2)
26 (4/2)
30 (5/2)
32 (5/2)
30 (5/2)
34 (6/2)
PC@ (d, ix)*
18 (4/0)
18 (4/0)
28 (4/2)
28 (412)
28 (4/2)
32 (5/2)
34 (5/2)
32 (5/2)
36 (6/2)
#xxx
12 (3/0)
12 (3/0)
22 (3/2)
22 (3/2)
22- (3/2)
26 (4/2)
28 (4/2)
26 (4/2)
30 (5/2)
• The size of the index register (ix) does not affect execution time.
290
HD68000---------------------------------Table 25 Standard Instruction Clock Periods
Instruction
ADD
op, An
8 (1/0)+
4 (1/0)+
6 (1/0)+**
6 (1/0)+**
Long
CMP
-
Byte, Word
6 (1/0)+
4 (1/0)+
Long
6 (1/0)+
6 (1/0)+
-
DIVS
DIVU
EOR
4 (1/0)+
Long
Byte, Word
AND
op , Dn
Size
Byte, Word
6 (1/0)+**
-
158 (1/0)+*
-
140 (1/0)+*
op Dn,
9(1/1)+
14 (1/2)+
9 (1/1)+
14 (1/2)+
-
Byte, Word
-
4 (1/0)***
9 (1/1)+
Long
-
8 (1/0)***
14 (112)+
MULS
-
-
70 (1/0)+*
-
MULU
-
-
70 (1/0)+*
-
-
4 (1/0)+
8 (1/0)+
4 (1/0)+
6 (1/0)+**
6 (1/0)+**
Byte, Word
OR
Long
Byte, Word
SUB
Long
6 (1/0)+**
9(1/1)+
14 (1/2)+
9 (1/1)+
14 (112)+
+
Add effective address calculation time
Indicates maximum value
Total of 8 clock periods for instruction if the effective address is register direct
*** Only available effective address mode is data register direct.
Table 26 Immediate Instruction Clock Periods
Instruction
ADDI
ADDQ
ANDI
CMPI
EORI
MOVEQ
ORI
SUBI
SUBQ
+
Size
op #, Dn
op#, M
op #, SR
Byte, Word
8 (2/0)
13(2/1)+
-
Long
16 (3/0)
22 (3/2)+
-
Byte, Word
4 (1/0)
9 (1/1)+
-
Long
8 (1/0)
14 (1/2)+
-
Byte, Word
8 (2/0)
13 (2/1)+
20 (3/0)
Long
16 (3/0)
22 (3/2)+
-
Byte, Word
8 (2/0)
8 (2/0)+
-
Long
14 (3/0)
12 (3/0)+
-
Byte, Word
8 (2/0)
13 (2/1)+
20 (3/0)
Long
16 (3/0)
22 (3/2)+
-
Long
4 (1/0)
-
-
Byte, Word
8 (2/0)
13 (2/1)+
20 (3/0)
Long
16 (3/0)
22 (312)+
Byte, Word
8 (2/0)
13(2/1)+
-
Long
16 (3/0)
22 (3/2)+
Byte, Word
4 (1/0)
9 (1/1)+
-
Long
8 (1/0)
14(1/2)+
-
Add effective address calculation time
291
------------~--------------------
HD68000---------------------------------
Table 27 Single Operand Instruction Clock Periods
Instruction
CLR
NBCD
NEG
NEGX
NOT
See
TAS
TST
+
Memory
Size
Register
Byte, Word
4 (1/0)
9 (1/1)+
Long
6 (1/0)
14 (1/2)+
Byte
6 (1/0)
9 (1/1)+
Byte, Word
4 (1/0)
9 (111)+
Long
6 (1/0)
14 (1/2)+
Byte, Word
4 (1/0)
Long
6 (1/0)
9 (1/1)+
14 (1/2)+
Byte, Word
4 (1/0)
9 (111)+
Long
6 (1/0)
14 (1/2)+
Byte, False
4 (1/0)
9 (1/1)+
Byte, True
6 (1/0)
9(111)+
Byte
4 (1/0)
11 (1/1)+
Byte, Word
4 (1/0)
4 (1/0)+
Long
4 (1/0)
4 (1/0)+
Add effective address calculation time.
Table 28 Shift/Rotate Instruction Clock Periods
Instruction
ASR,ASL
LSR, LSL
ROR, ROL
ROXR, ROXL
Memory
Size
Register
Byte, Word
6 + 2n (1/0)
Long
8 + 2n (1/0)
-
Byte, Word
6 + 2n (1/0)
9 (1/1)+
9 (1/1)+
Long
8 + 2n (1/0)
-
Byte, Word
6 + 2n (1/0)
9 (1/1)+
Long
8 + 2n (1/0)
-
Byte, Word
6 + 2n (1/0)
9 (1/1)+
Long
8 + 2n (1/0)
-
Table 29 Bit Manipulation Instruction Clock Periods
Instruction
BCHG
BCL~
BSET
BTST
+
Size
Byte
Long
Byte
Long
Byte
Long
Byte
Long
Dynamic
Register
Static
Memory
-
9(1/1)+
-
8 (1/0)*
-
9 (1/1)+
-
10 (1/0) *
-
9 (1/1)+
-
8 (1/0)*
-
4 (1/0)+
-
6 (1/0)
Add effective address calculation time
Indicates maximum value
292
Register
12 (2/0)*
14 (2/0)*
12 (2/0)*
10 (2/0)
Memory
13 (2/1)+
13 (2/1)+
13 (2/1)+
8 (2/0)+
-
------------------------------------HD68000----------------------------------•
CONDITIONAL INSTRUCTION CLOCK PERIODS
•
Table 30 indicates the number of clock periods required for
the conditional instructions. The number of bus read and write
cycles is indicated in parenthesis as: (R/W). The number of
clock periods plus the number of read and write cycles must be
added to those of the effective address calculation where
indicated.
•
MULTI-PRECISION INSTRUCTION CLOCK PERIODS
Table 32 indicates the number of clock periods for the
multi-precision instructions. The number of clock periods
includes the time to fetch both operands, perfonn the operations, store the results, and read the next instructions. The
number of read and write cycles is shown in parenthesis as:
(R/w).
In Table 32, the headings have the following meanings: Dn =
data register operand and M = memory operand.
JMP, JSR, LEA, PEA, MOVEM INSTRUCTION CLOCK
PERIODS
Table 31 indicates the number of clock periods required for
the jump, jump to subroutine, load effective address, push
effective address, and move multiple registers instructions. The
number of bus read and write cycles is shown in parenthesis as:
(R/W).
•
MISCELLANEOUS INSTRUCTION CLOCK PERIODS
Table 33 indicates the number of clock periods for the
following miscellaneous instructions. The number of bus read
and write cycles is shown in parenthesis as: (R/W). The number
of clock periods plus the number of read and write cycles must
be added to those of the effective address calculation where
indicated.
Table 30 Conditional Instruction Clock Periods
Instruction
Bee
BRA
BSR
Trap or Branch
Not Taken
Byte
10 (1/0)
8 (1/0)
Word
10 (1/0)
12 (2/0)
Byte
10 (1/0)
Word
10 (1/0)
-
Byte
20 (212)
Word
20 (2/2)
-
-
12 (2/0)
10 (2/0)
14 (3/0)
CC true
DBee
CC false
CHK
-
TRAP
TRAPV
+
Trap or Branch
Taken
Displacement
43 (5/3)+*
8 (1/0)+
-
37 (4/3)
37 (5/3)
4 (1/0)
Add effective address calculation time
Indicates maximum value
Table 31 JMP, JSR, LEA, PEA, MOVEM Instruction Clock Periods
Instruction
JMP
JSR
LEA
PEA
Size
-
An@+
An@-
An@(d)
An@(d,ix)*
xxx. W
xxx.L
PC@(d)
8 (2/0)
An@
-
-
10 (2/0)
14 (3/0)
10 (2/0)
12 (3/0)
10 (2/0)
14 (3/0)
18 (2/2)
-
-
20 (2/2)
24 (2/2)
20 (2/2)
22 (3/2)
20 (2/2)
24 (2/2)
4 (1/0)
-
-
8 (2/0)
12 (3/0)
8 (2/0)
12 (2/0)
18 (2/2)
12 (2/0)
22 (212)
8 (2/0)
-
18 (2/2)
22 (3/2)
18 (2/2)
22 (2/2)
16 + 4n
(4+n/0)
18 + 4n
(4+n/0)
16 + 4n
(4+n/0)
20 +4n
(5+n/0)
16 + 4n
(4+n/0)
18 +4n
(4+n/0)
16 + 8n
(4+2n/0)
18 + 8n
(4+2n/0)
16 + 8n
(4+2n/0)
20 + 8n
(6+2n/0)
16 + 8n
(4+2n/0)
18 + 8n
(4+2n/0)
8+ 5n
(2/n)
12 + 5n
(3/n)
14 + 5n
(3/n)
12 + 5n
(3/n)
16 + 5n
(4/n)
-
-
-
-
8 + 10n
(2/2n)
12+10n
(3/2n)
14 + 10n
(3I2n)
12+10n
(3I2n)
16+10n
(4/2n)
-
-
14 (1/2)
12 + 4n
(3+n/0)
12 + 8n
(3+2n/0)
MOVEM
Word
M--. R
Long
MOVEM
Word
8 + 5n
(2/n)
Long
8 + 10n
(2I2n)
R~M
12 + 4n
(3+n/0)
12 + 8n
(3+2n/0)
-
-
n is the number of registers to move
* is the size of the index register Ox) does not affect the instruction's execution time.
293
PC@(d,ix)*
HD68000--------------------------------Table 32 Multi-Precision Instruction Clock Periods
ADDX
opM, M
Size
op On, On
Byte, Word
4 (1/0)
19 (3/1)
Long
8 (1/0)
32 (5/2)
Instruction
Byte, Word
-
12 (3/0)
long
-
20 (5/0)
Byte, Word
4 (1/0)
19 (3/1)
Long
8 (1/0)
32 (5/2)
ABCD
Byte
6 (1/0)
19 (3/1)
SBeD
Byte
6 (1/0)
19 (3/1)
CMPM
SUBX
Table 33 Miscellaneous Instruction Clock Periods
Instruction
Size
MOVE from SR
-
6 (1/0)
9 (1/1)+
MOVE to CCR
-
12 (2/0)
12(2/0)+
12 (2/0)
12 (2/0)+
Word
-
MOVE to SR
MOVEP
Long
Register
Memory
Register -+ Memory
-
-
-
28 (2/4)
24 (6/0)
-
-
-
Word
4 (1/0)
-
Long
4 (1/0)
18 (2/2)
4 (1/0)
-
4 (1/0)
-
4 (1/0)
132 (1/0)
-
-
RESET
-
RTE
-
20 (5/0)
-
-
RTR
20 (5/0)
-
-
SWAP
-
4 (1/0)
-
-
UNLK
-
12 (3/0)
-
-
LINK
MOVE from USP
MOVE to USP
NOP
RTS
STOP
+
16 (4/0)
4 (0/0)
16 (4/0)
6 (1/0)
EXT
-
...
18 (2/2)
-
EXG
Memory -+ Register
-
-
-
Add effectIve address calculatIon tIme
Table 34 Exception Processing Clock Periods
• EXCEPTION PROCESSING CLOCK PERIODS
Table 34 indicates the number of clock periods for exception
processing. The number of clock periods includes the time for
all stacking, the vector fetch, and the fetch of the first
instruction of the handler routine. The number of bus read and
write cycles is shown in parenthesis as: (R/W).
Exception
Address Error
Periods
57 (417)
Bus Error
57 (417)
Interrupt
47 (5/3)*
I "egal Instruction
37 (4/3)
Privileged Instruction
37 (4/3)
Trace
37 (4/3)
* The interrupt acknowledge bus cycle is assumed to take four external
clock periods.
HITACHI reserves the right to make changes to any products herein to improve functioning or design. Although
the information in this document has been carefully reviewed and is believed to be reliable, HITACHI does not
assume any liability arising out of the application or use of any product or circuit described herein, neither does
it convey any license under its patent rights nor the rights of others.
294
[ APPENDIX
295
I
PACKAGE INFORMATION
Packages are classified into 3 types; dual-in-line plastic, dualinline ceramic (glass-sealed) and dual-in-line ceramic (with lid),
according to the quality of material used for packaging.
Package*
Function
Type
Pin No.
HD6800
HD68AOO
Micro Processing Unit
40
Microprocessor with Clock and RAM
40
8/16 Bit Micro Processing Unit
40
Peripheral Interface Adapter
40
Programmable Timer Module
40
Asynchronous Communications Interface Adapter
24
Synchronous Serial Data Adapter
24
Combination ROM I/O Timer
40
Floppy Disk Controller
40
Direct Memory Access Controller
40
CRT Controller
40
HD68BOO
HD6802S
HD6809
HD68A09
HD68B09
HD6821
HD68A21
HD68B21
C**
G
P
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
HD6840
HD68A40
HD68B40
HD6850
HD68A50
HD6852
HD68A52
HD6846
HD6843S
HD68A43S
HD6844
HD68A44
HD46508-1
0
0
0
0
0
0
0
0
HD68B45
HD46508
0
0
HD6845
HD68A45
0
Analog Data Acquisition Unit
40
16/32 Bit Microprocessor
64
O-std.
16 Bit Direct Memory Access Controller
64
O-std.
HD68000-4
HD68000-6
HD68000-S
HD6S450-4
HD68450-6
HD68450-S
* The package codes of C, G and P are applied to the package materials as follows.
C; Ceramic with Lid
G; Glass - Sealed Ceramic
P; Plastic
** Special Order Only
296
•
DUAL-IN-LINE CERAMIC (with Lid)
DC-40
DC-24
II~i~
(Dimensions in mm)
•
(Dimensions in mm)
DUAL-IN-LINE CERAMIC (Glass-sealed)
DG-16
DG-16A
~I
ft
O'~\5°
•
0.20-0.38
(Dimensions in mm)
(Dimensions in mm)
DUAL-IN-LlNE PLASTIC
DP-24
DP-16
(Dimensions in mm)
(Dimensions in mm)
DP-28
DP-40
'I~
;
:
,~
~
(Dimensions in mm)
"".A ",.~~~ --- -
,,,m.
297
(Dimensions in mm)
HMCS6800 FAMILY INSTRUCTIONS
• ACCUMULATOR AND MEMORY OPERATIONS
HD6800
HD6802
Operations
Add
Mnemonic
A+M-+A
ADDB
B+M-+B
Add Double
ADDD
A:B + M:M+1--+ A:B
Add Accumulators
ABA
A + B -+A
Add with Carry
ADCA
A+M+C-+A
ADCB
B+M+C-+B
SUBA
A -M-+A
SUBB
B - M -+ B
SUBD
A:B - M:M+1 -+ A:B
SBA
A - B-+ A
SBCA
A - M - C ..... M
SBCB
B - M - C -+ M
Multiply
MUl
A x B-+ A:B
Decimal Adjust A
DAA
Decimal Adjust Accumulator
Subtract Double
Subtract with
Carry
Increment
Decrement
Clear
Compare
Compare Double
CompXgcumulators
Test Zero or
Minus
And
o
o
000 0
o 0 0 0
0 0 0
0 0 0
o
0
o
o
o
o
0 0 0
0 0 0
0 0 0
0 0 0
000 0
o
0
000 0
0 0
o
o
0 0 0
000 0
o
INC
M+ 1-+ M
A + 1 -+ A
o
INCB
B + 1 -+ B
o
0
o 0
000 0
o
o
M -1-+ M
A -1-+ A
o
o
DECB
B -1 -+ B
o
o
ClR
0 -+ M
ClRA
0 -+ A
o
o
ClRB
0 -+ B
o
o
CMPA
A - MOO 0
CMPB
B-M
0
o
0
0
o
0
000
o
o
o
o
0
0 0 0 0
0000
o
o
o
0
0
0 0
o
o
o
0
0 0
0
0 0 0 0 0
00000
~------~----------------------+-~~-+~--~+-~-+~--~+-~~-+~--~+--b-+~--~+-~~--
CMPD
A:B-M:M+1
CBA
TST
A-B
TSTA
A -00
TSTB
B -00
ANDA
A·M-A
0
o
M -00
o
0
o 0
0
o
o
o
o
o
0 0 0
00000
000
00000
o
000
o 0 0 0
o 00 0
o
ORAB
ORB
B+M-+B
Exclusive Or
EORA
A® M-+ A
o
o
o
o
o
o
000 0
Complement 1's
COM
EORB
COMA
o
A-+A
NEG
00 -M-+M
o
0
0 0
0
0
0 0
0 0
o
0
COMB
o
o
o
o
o
0 0
0
0
0
0
0 000
000 0
o
o
o
0
000 0
0
o
o
o
NEGA
OO-A-+A
o
OO-B-B
o
Bit Test
BITA
A·M
BITB
B·M
Bit Clear
BClR n
0-+ M· Bit (n)
01
Bit Set
BSET n
1 -+ M • Bit (n)
o
SEX
Sign Extend B into A
000
0 0 0
0 0
o
NEGB
o
o
0
o 0 000
o
o
0
o
0
000 0
o 0 0 0
o
o
o 0 0 0
0 0 0
000 0
o
o
o 0 0 0
o 0 0 0
0 0 0
000
0 0 0 0
o
o
A+M-+A
(Negate)
0 000
0 000
o
ORAA
ORA
Complement.2's
o
o
0
o
o
DEC
0
0000
0
o
o
0
DECA
o
0
o
o
o
o
00000
000
o
000 0
o 0 0 0
000 0
00000
00000
o 0 000
o 0 0 0 0
o 0 0 0
o
o
o
o
o
o
o
000
0 0 0
o 0 0 0 0
00000
000 0
0 0
o
INCA
ANDB
Or
HD6809
HD6805
Boolean/Arithmetic
Operation
ADDA
Subtract
HD6801
HD6803
o
o
o
0 0 0
o
o
0
0
0 0
0 0
0
0
o
298
(to be continued)
H06801
H06803
H06800
H06802
Operations
Load
Mnemonic
LDAA
LDA
LOAB
LDB
LDD
Store
Transfer
STAA
STA
M-+A
000 0
M-+B
000 0
M:M+1 -+ A:B
o
0
0
0
o
0
0
0
o
A-+M
000
STAB
5TB
B-+M
000
5TD
A:B-+M:M+1
TFR
Register 1 -+ Register 2
TAB
A-+B
TBA
B -+A
00000
00000
00000
000
000
o
0
0
0
000
000 0
000
o
0
0
0
o
o
o
o
o
o
EXG
Register 1 --> Register 2
Push Data
P5HA
A --> Ms 5 -1 --> 5
o
o
P5HB
B -->Ms 5-1-->5
o
o
P5H5
Registers ..... Ms 5 - n --> 5
P5HU
Registers --> Mu U - n ..... U
PULA
Ms ..... A
5 + 1 --> 5
PULB
Ms--> B
5 + 1 --> 5
PUL5
Ms -+ Registers
PULU
Mu ..... Registers U + n ..... U
5hift Left
Arithmetic
000
000 0
Exchange
Pull Data
HD6809
H06805
Booleanl
Arithmetic Operation
o
o
o
o
o
o
o
5 + n ..... 5
o
A5L
ASLA
A5LB
A5LD
5hift Right
Arithmetic
o
A5R
I
L5B
ASRB
5hift Right
Logical
o
L5RA
0 .....
_--ll-JI-->
M5B
L5B
1-1.......
1
LSRB
ROL
ROLA
ROLB
Rotate Right
o
0
o
0
000 0
COO
L5R
L5RD
Rotate Left
0
I-->D~~1-+0~+-~-+~O+-~-+-r+0-r1-+4~-r~O+-
A5RA
M
A
B
lCo '
0
o
0
0
o
0
o
0
0
0
Dt---;r-t-+-+-~-t--+--r-t---1--+-~+-~f----t-+-+-°-t--+--r-t---1--+-+~-+C~+-+-1-~-+-+~--~+-+-O~-+-+~~--~+-1-~-+-+~--~+--
-I'----L-.I_-----'"I-JIJ
C MSB
LSB
0
0
0
0
0
0
0
0
0
0
~-+--r-+--O0 +--t-+-r~+O--+-~+-I--+~O---+-+-+--t--+--+--+-O+-0
0
ROR
RORA
RORB
299
• JUMP AND BRANCH INSTRUCTIONS
H06800
H06802
Operations
Mnemonic
Branch Test
H06801
HD6803
HD6805
IU
w
UJ
UJ
H06809
w
> a I>
> a I>
a Ia Iu x a w
u x a
u x a
u x a
UJ W W
UJ W UJ Z
UJ UJ UJ Z
UJ W W Z ...J
...J
...J
~ a: 0 ~ I-~...J ~
~ a: a I- a.. ~ ~ a: a I- a.. ~ ~ a: 0 I- a..
x
w
UJ
UJ
x
x
UJ
~ Ci ~ UJ ~ a: ~ 15 ~ UJ ~ a: ~ a ~ w ~ a: ~ 15 ~ ~ ~~ ~ a:
~
Branch if Carry
Clear
BCC
Branch if Carry
Set
BCS
Branch
if = Zero
SEQ
Branch if Not
Equal Zero
BNE
C=O
0
0
0
C=1
0
0
0
0
0
LBCS
Z=O
0
0
0
0
Z'IO
0
0
0
0
N®V=O
0
0
0
Z + (N ® V) =0
0
0
0
N ® V = 1
0
0
LBEQ
0
LBNE
Branch
if ~ Zero
BGE
Branch
if> Zero
BGT
Branch
if < Zero
BLT
Branch
if ~ Zero
BLE
Branch
if Higher
BHI
Branch
if Lower or Same
BLS
Branch
if Plus
BPL
Branch
if Minus
BMI
Branch
if overflow Clear
BVC
Branch
if Overflow Set
BVS
0
LBGE
0
LBGT
0
0
0
LBLT
Z + (N ® V) = 1
0
0
0
LBLE
0
C+Z=O
0
0
0
0
0
LBHI
C+Z=1
0
0
0
0
0
LBLS
N=O
0
0
0
0
N=1
0
0
0
0
V=O
0
0
0
V= 1
0
0
0
LBPL
0
LBMI
0
LBVC
0
LBVS
0
Branch if Half
Carry Clear
BHCC
H=O
0
Branch if Half
Carry Set
BHCS
H= 1
0
Branch if Interrup
Mask Clear
BMC
1=0
0
Branch if Interrupt
Mask Set
BMS
1=1
0
Branch if Interrupt
Line High
BIH
INT= 1
0
Branch if Interrupt
Line Low
BIL
INT =0
0
0
I
Branch if Bit n of
MClear
BRCLR n
M (n) =0
Branch if Bit n of
M Set
BRSET n
M (n) = 1
Branch Always
0
0
LBCC
0
BRA
0
0
0
0
LBRA
Branch Never
0
BRN
0
0
0
0
0
LBRN
Branch to
Subroutine
BSR
Jump
JMP
0
0
0
LBSR
0
0
0
0
0
0
0
0
0
0
0
0
(to be continued)
300
HD6800
HD6802
Operations
Mnemonic
HD680'
HD6803
HD6805
HD6809
Branch Test
Jump to
Subroutine
JSR
Return from
Subroutine
RTS
o
o
o
o
No Operation
NOP
o
o
o
o
o
o
o
o
o
o
o
o
Software
Interrupt
o
SWI
000
000
0
o
000 0
SWI2
SWI3
Return from
Interrupt
RTI
o
Wait
WAI
o
Synchronize to
Interrupt
•
o
CWAI
o
SYNC
o
INDEX REGISTER AND STACK POINTER INSTRUCTIONS
HD6800
HD6802
Operations
HD680'
HD6803
HD6809
HD6805
Boolean/
Arithmetic Operation
Mnemonic
+, . . .
Increment
INX
x
X
o
o
Decrement
DEX
X-1 ..... X
o
o
o
o
o
o
ADD with B
ABX
B+X ..... X
Clear
CLRX
0 .... X
o
Negate
Complement 1 '5
NEGX
OO-X ..... X
o
COMX
ASLX
FF - X ..... X
o
Shift Left
Arithmetic
Shift Right
Arithmetic
Shift Right Logical
ASRX
o
~'''',s'''''BI,---_...,...IL~...,i,SBI4 9
o
LSRX
o
Rotate Left
ROLX
o
Rotate Right
RORX
o
Test
TSTX
X -00
Compare
CPX
CMPX
X -M:M+1
Load
Store
Load effective
Address
CMPY
Y - M:M+1
LDX
M:M+1 ..... X
LDY
M:M+1 ..... Y
STX
X ..... M:M+1
STY
Y ..... M:M+1
LEAX
Effective address ..... X
LEAY
Effective address .... Y
Push
PSHX
X ..... Ms
Pull
PULX
Ms .... X
o
000 0
000 0
000 0
000 0
000 0
000 0
00000
00000
000
000
000
o
o
0
0
0 0
0 0
o 0
0 0
0 0
o
0 0
0
o
o
o
o
Ito be continued)
301
Transfer X, A
Transfer X, S
A-+X
X -+A
TSX
S-+ X
0
0
0
TXS
X-+S
0
0
Increment
INS
S+1-+S
0
0
0
0
Decrement
DES
S-1-+S
Reset
RSP
$7F -+ S
Compare
CMPS
S - M: M+1
0
0
0
0
0
CMPU
U -M: M+1
0
0
0
0
0
LDS
M: M+1 ..... S
0
0
0
0
0
LDU
M : M+1 -+ U
0
0
0
0
0
STS
S -+ M :M*-1
0
0
0
0
STU
U-+ M : M+1
0
0
0
LEAS
Effective Address -+ S
0
LEAU
Effective Address -+ U
0
Load
Store
Load effective
Address
•
0
TAX
TXA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CONDITION CODE REGISTER INSTRUCTIONS
HD6800
HD6802
Operations
w
Boolean Operation
Mnemonic
ICl U
w w
~
~
Clear Carry
HD6801
HD6803
a:::
Cl
Z
w ICl
X
>
X
Cl ~
...J
el.
~
ICl U 'X Cl
W W W Z
~ a::: Cl IX
w
w ~ a::: ~
0
HD6805
w
>
...J
el.
~ w ~
~
w
HD6809
W
~
a::: ~
W
a:::
Cl
W Z
Cl IX
X
Cl ~
>
CLC
O-+C
0
0
CLI
0-+1
0
0
0
Clear InterruptMask
CLV
O-+V
0
0
0
Set Carry
SEC
1-+C
0
0
0
SEI
1 -+ I
0
0
0
SEV
1-+V
0
0
TAP
A -> CC
0
0
CC-+ A
0
0
TPA
And CC
Or CC
CC· imm-> CC
0
ORCC
CC+imm-> CC
0
S
U
+
+
$
I\lI
Ms
Mu
CC
Accumulator A
Accumulator B
Index Register
Index Register (6809 only)
Stack Pointer
User Stack Pointer (6809 only)
Transfer into
Arithmetic Plus
Arithmetic Minus
Boolean AND
Boolean Inclusive OR
Boolean Exclusive OR
Connection Area
Complement of M
Stack area pointed by S.
Stack area pointed by U.
Condition Code Register
H
Half Carry from 3 bit
Interrupt Mask
Negative
Zero
Overflow
Carry Bit from 7 bit
Most Signification bit
Least Signification bit
Immediate
Direct
Indexed
N
Z
V
C
MSB
LSB
IMMED
DIRECT
INDEX
Ext~nded
EXTND
EXT INDIRECT Extended indirect
Inplied (Inherent. Accumulator)
IMPL
Relative
RELATIVE
302
U
Cl
w
W
~ ~~~
ANDCC
LEGEND
A
B
X
y
W
0
Set InterruptMask
Set Overflow
~
Cl I- X
W U
W
>
~
~ a::: Cl ~ I-~...J
w
w
w ~ a::: ~ 0 ~
a:::
...J
el.
Clear Interrupt Mask
Transfer A. CC
I-
W
Cl IU
MEMORIES
•
MOS MEMORI ES
• SELECTION GUIDE TO MOS RAMs
Mode
Total
Bit
Type No.
Process
Organization
(word xbit)
HM472114A-1
HM472114A-2
HM472114-3
NMOS
1024 x4
HM472114-4
HM4334-3
HM4334-4
CMOS
1024x 4
CMOS
1024 x 4
HM6148
4k-bit
HM6148-6
HM6148L
HM6148L-6
200
300
300
450
450
300
460
450
640
70
70
85
85
70
70
HM6147
70
70
HM6147-3
55
55
70
70
CMOS
4096 x 1
55
55
120
120
HM6116-3
150
150
HM6116-4
200
200
120
120
HM6116L-2
CMOS
2048 x8
HM6116L-3
150
150
HM6116L-4
200
200
HM4716A-1
HM4716A-2
HM4716A-3
NMOS
16384 x 1
HM4716A-4
HM4816
64k-bit
200
85
HM6116-2
Dynamic
150
640
4096'>< 1
HM6147L-3
16k-bit
150
450
CMOS
HM6147L
16k-bit
Cycle
Time
(ns)
min.
85
HM4315
Static
Access
Time
(ns)
max.
NMOS
HM4864-2*
HM4864-3*
NMOS
16384 x 1
65536 x 1
120
320
150
320
200
375
250
410
100
200
150
270
200
335
Supply
Voltage
Power
Dissipation
(V)
(mW)
+5
200
Package * *
Pin No_
C
Crossreference
G
P
• •
18
+5
20
18
+5
200
18
+5
20
18
75
+5
18
180
+5
24
160
+12,
+5,
350
16
-5
+5
250
16
+5
170
16
•
•
•
• •
• •
• •
•
•
•
•
•
•
•
• •
• •
•
•
•
•
•
•
•
•
• •
• •
• •
• •
2114L-2
2114L-3
2114L-4
HM-6514
2148
2148-6
2147
2147-3
MK4116-2
MK4116-3
MK4116-4
• SELECTION GUIDE TO MOS ROMs
Program
Mask
UV Erasable &
Electrically
Electrically Erasable
& Programmable
Total
Bit
Type No.
Process
Organization
(word x bit)
Access
Time
(ns)
max.
Supply
Voltage
(V)
Power
Dissipation
(mW)
Package * *
Pin No.
16k-bit
HN462316E
2048 x 8
350
350
24
32k-bit
HN46332
4096 x 8
350
250
24
64k-bit
HN48364
16k-bit
HN462716
32k-bit
16k-bit
HN462532
HN462732
HN48016
NMOS
8192 x8
350
2048 x8
450
4096 x8
2048)( 8
* Preliminary
** The package codes of C, G, and P are applied to the package materials as follows.
C : Ceramic with Lid, G: Glass-sealed Ceramic, P: Plastic
303
225
24
310
24
450
450
24
350
160
24
+5
C
G
Crossreference
P
·•
• •
•
•
2316E
•
2716
TMS2532
2732
•
• BIPOLAR MEMORIES
• SELECTION GUIDE TO BIPOLAR RAMs
Level
Total
Bit
256-bit
Type No.
Organization
(word xbit)
Output
HM2106
15
1.8
HM10414*
256x1
10
Open
Emitter
1024 x 1
10
HM2504
HM2504-1
TTL
55
45
HM2510-1
1k-bit
HM251 0-2
24
0.5
16
0.8
16
0.2
18
F10410
•
F10414
•
F10422
•
F1oo422
•
•
•
F10415A
1.8
16
+5
0.5
16
70
45
F10415
F10470
•
•
•
•
•
93411
93411A
93415
•
•
35
3-State
HM2511-1
P
•
•
70
45
1024x 1
HM2511
•
15
Open
Collector
HM2510
0.8
G
•
16
-5.2
25
256 x 1
C
Crossreference
•
8
4096 x 1
Pin No.
35
20
HM2112-1
HM10470-1*
-4.5
25
HM2112
HM10470*
10
2.8
Package**
2.8
10
256x4
HM2110-1
HM2110-2
-5.2
8
HM2110
256-bit
(V)
1.8
HM100422*
4k-bit
max.
Power
Dissipation
(mW/bit)
35
HM10422*
1k-bit
Supply
Voltage
HM2105
HM10414-1 *
ECL
Access
Time
(ns)
0.5
16
Power
Dissipation
(mW/bit)
Pin No.
500
18
600
18
93415A
•
93425
SELECTION GUIDE TO BIPOLAR PROM
Level
Total
Bit
4k:t>it
Type No.
HN25044
HN25045
HN25084*
TTL
8k-bit
HN25085*
HN25088*
HN25089*
Organization
(word x bit)
1024 x4
2048 x 4
1024x 8
Output
OIC
3-S
OIC
3-S
OIC
3-5
Access
Time
(ns)
max.
Supply
Voltage
(V)
50
60
+5
60
* Preliminary
** The package codes of C, G, and P are applied to the package materials as follows.
C : Ceramic with Lid, G : Glass-sealed Ceramic, P: Plastic
304
600
Package** .
24
C
Crossreference
G
P
•
•
•
82S137
•
825180
•
•
82S136
82S184
82S185
82S181
•
OUTLINE
,
I OP-16 I
~
I OG-16
I
I OG-24A ,
•
I OP-24 ,
IOP-181
I OG-16A
I
I OG-18
I
I OG-24 ,
I OG-24B
I
, OC-16
I
I DC-24C
,
APPLICABLE ICs
Dp·16
HM4716Ap·1, HM4716AP·2, HM4716AP·3, HM4716AP·4
DP·18
HM472114AP·1, HM472114AP·2, HM472114P·3, HM472114P-4, HM4334P·3, HM4334p·4, HM6148P,
HM6148P·6, HM6148LP, HM6148LP·6, HM4315P, HM6147P, HM6147p·3, HM6147LP, HM6147Lp·3
Dp·24
HM6116P·2, HM6116p·3, HM6116p·4, HM6116LP·2, HM6116LP·3, HM6116LP·4, HN462316EP, HN46332P,
HN48364P, HN48016P
DG·16
HM2105, HM2106, HM10414, HM10414·1, HM2504, HM2504·1
DG·16A
HM4716A·1, HM4716A·2, HM4716A·3, HM4716A-4, HM2110, HM2110·1, HM2110·2, HM2112, HM2112·1,
HM2510, HM2510·1, HM2510·2, HM2511, HM2511·1
DG-18
HM472114A-1, HM472114A-2, HM472114·3, HM472114·4, HM6147, HM6147·3, HM10470, HM10470·1,
HN25044, HN25045, HN25084, HN25085
DG-24
HN25088, HN25089
DG·24A
HM10422, HM100422
DG-24B
HN462716G
DC-16
HM4816, HM4864·2, HM4864-3
DC-24C
HN462716, HN462532, HN462732
305
LINEAR IC & INTERFACE CIRCUITS
•
LINEAR les
Type No.
Functions
General Purpose
HAl774l
High Speed
HAl77l5
Operational
Amplifiers
Package Code
M
P
DP-14
HA17904
Voltage
Comparators
DG·14
DP·8
~A7l5C
NS LM1458
~A747C
NS LM2904
HA17301
DP·14
DG·14
Motorola MC3301
DP·14
DG·14
NS LM2902
HA18l3
DP·8
DP·8
DG-8
HA17903
DP·8
DG-8
Fixed
~A741C
Fairchild
HA17902
HA18l2
Dual
Cross·reference
Fairchild
Fairchild
DG-8
Single
Variable
Regulators
DG-8
Universal
HAl807
Quad.
Voltage
GS
DG-8
DP·8
HAl7747
Quad.
G
T-l00
HA17458
Dual
PS
DP·8
NS LM2903
DG·14
HA1790l
DG·14
NS LM2901
DG·14
Fairchild
~A 723C
T·220AB
Fairchild
~A7805C
HA17806
T-220AB
Fairchild
~A7806C
HA17807
T-220AB
8V,lA
HA17808
T·220AB
Fairchild
~A7808C
l2V,lA
HA178l2
T·220AB
Fairchild
~A 78l2C
l5V,lA
HA178l5
T·220AB
Fairchild
~A78l5C
l8V,lA
HA178l8
T-220AB
Fairchild ~A78l8C
2-37V, l50mA
HA17723
5V,lA
HA17805
6V,lA
7V,lA
DP·14
24V,lA
HA17824
T·220AB
Fairchild
~A7824C
5V,O.5A
HA178M05
T·220AB
Fairchild
~A78M05C
6V,O.5A
HA178M06
T·220AB
Fairchild
~A78M06C
7V,O.5A
HA178M07
T·220AB
8V,O.5A
HA178M08
T-220AB
Fairchild
~A78M08C
l2V,O.5A
HA178M12
T·220AB
Fairchild
~A78M12C
l5V,O.5A
HA178M15
T·220AB
Fairchild
~A78M15C
~A78M18C
l8V,O.5A
HA178M18
T·220AB
Fairchild
20V,O.5A
HA178M20
T·220AB
Fairchild
~A 78M20C
24V,O.5A
HA178M24
T·220AB
Fairchild
~A78M24C
Switching Regulator Controller
HA17524
DP·16
AID, D/A
8·bit Double Integral Type AID
HA16613
DP·28
Converters
8-bit D/A
HA17408
Differential Video Amp.
HAl7733
5 Transistor Arrays
HA1127
Precision Timers
HA17555
DP·8
Monostable Multivibrators
HA1607
DP·8
DP·16
DG·16
Silicon General SG3524
DG·16
AMD AM1408
DG·14
RCA CA3045
T·100
Fairchild
Other
Micromotor Speed Controller
HA16503
DP-14
Function
Light·measu rement Amp_
for Camera
HA16506
DP·14
HA16564
DP·14
Coin Sensor
HA16603
DP·16
Electric Leakage Breaker
HA16604
SP-8
Burner Controller
HA16605W
DP·20
306
DG-8
~A733C
Signetics NE555
•
INTERFACE CIRCUITS
Dual
Driver
Quad.
Dual
Dual NAND + NPN Transistor
•
DG-14
Texas SN75109
DP-14
DG-14
Texas SN75110
DG-16
HD75188
DP-14
DG-14
Texas SN75188
HD75107A
DP-14
DG-14
Texas SN75107A
HD75108A
DP-14
DG-14
Texas SN75108A
DG-16
DG-16
HD75154
DP-16
DG-16
HD75189
DP-14
DG-14
Texas SN75189
HD75450A
DP-14
DG-14
Texas SN75450A
HD75451A
DP-8
DG-8
Texas SN75451A
HD75452
DP-8
DG-8
Texas SN75452
Dual OR
HD75453
DP-8
DG-8
Texas SN75453
Dual NOR
HD75454
DP-8
DG-8
Texas SN75454
Texas SN7524
Dual Sense Amplifier
HD1902
DG-16
Quad. TTL-MaS Clock Driver
HD2912
DG-16
Quad. TTL-MaS Clock Driver
HD2916
DG-16A
Quad. ECl-TTl Driver
HD2923
DG-16A
HD2919
Printer Driver
DP-16
OUTLINE
[DP-161
I DG-14
I T-1 00
I
Texas SN75154
Dual AND
IC
Memory
Other
DP-14
HD75110
Dual NAND
Core Memory
Memory
Suport
Cross-reference
HD75109
HD2915
Quad.
Peripheral
Driver
G
HD2905
Triple
Receiver
P
HD2904
Triple
Line Driver!
Receiver
Package Code
Type
Functions
I
I DG-16
I
l!-220AB I
307
I DG-16A
I
TTLHD74/HD74S/HD74LS SERIES
•
•
PERFORMANCE (per gate)
HD74
Series
HD74S
Series
HD74LS
Series
Propagation
Delay Time
10ns
3ns
10ns
Power
Dissipation
10mW
20mW
2mW
Speed-Power
Product
100pJ
6,DpJ
20pJ
Performance
MAIN CHARACTERISTICS (Ta
~
Parameter
VOL (lOL max.)
V OH
(loH=-400,uA)
V IL
=-20 -- +7SoC)
HD74 Series
min.
max.
HD74S Series
HD74LS Series
min.
min.
max.
0.5V
-
O.4V
-
2.4V
-
2.7V
-
-
max.
0.5V
2.7V
-
-
O.BV
-
O.BV
-
O.BV
V IH
2V
-
2V
-
2V
-
IlL
IIH (VII..pmin.)
-
-1.6mA
-
-2mA
-
-0.4mA
40,uA
50,uA
20,uA
• SELECTION GUIDE
• NAND/NOR/AND/OR GATES
HD74 Series
Function
Quad. 2-input Positive
Quad. 2-input Positive
Quad. 2-input Positive
Quad. 2-input Positive
Hex Inverters
NAND Gates
NAND Gates (with Open Collector Output)
NOR Gates
NAND Gates (with Open Collector Output)
00
01
02
03
04
HD74S Series
HD74LS Series
02
03
04
00
01
02
03
04
05
00
-
Hex Inverters (with Open Collector Output)
Hex Inverter Buffers/Drivers (with Open Collector High-voltage Output)
Hex Buffers/Drivers (with Open Collector High-voltage Output)
Quad. 2-input Positive AND Gates
Quad. 2-input Positive AND Gates (with Open Collector Output)
05
06
07
OB
09
05
Triple 3-input Positive NAND Gates
Triple 3-input Positive AND Gates
Triple 3-input Positive NAND Gates (with Open Collector Output)
Dual 4-input Schmitt NAND Gates
Hex Schmitt-trigger Inverters
10
10
11
12
-
-
-
-
-
08
09
-
-
10
11
12
13
14
-
15
15
16
17
-
-
20
20
-
-
20
21
Dual 4-input Positive NAND Gates (with Open Collector Output)
Expandable Dual 4-input Positive NOR Gates (with Strobe)
Dual 4-input Positive NOR Gates
Quad. 2-input High-voltage Interface NAND Gates
Triple 3-input Positive NOR Gates
22
23
25
26
27
22
22
-
-
8-input Positive NAND Gate
Quad. 2-input Positive OR Gates
Quad. 2-input Positive NAND Buffers
Quad. 2-input Positive NAND Buffers (with Open Collector Output)
Dual 4-input Positive NAND Buffers
30
32
37
38
40
40
30
32
37
38
40
125
126
132
-
125A
126A
132
-
133
134
-
Triple 3-input Positive AND Gates (with Open Collector Output)
Hex Inverter Buffers/Drivers (with Open Collector High-voltage Output)
Hex Buffers/Drivers (with Open Collector High-voltage Output)
Dual 4-input Positive NAND Gates
Dual 4-input Positive AND Gates
Quad. Bus Buffer Gates with 3-state Output (Inverting)
Quad. Bus Buffer Gates with 3-state Output (Noninverting)
Quad. 2-input Positive NAND Schmitt Triggers
13-input Positive NAND Gate
12-input Positive NAND Gate (with 3-state Out.)
12
13
14
-
-
26
27
(to be continued)
308
Function
Dual 4-input Positive NAND Line Drivers
Octal Bus Transceivers (with Noninverted 3-state Output)
Hex Bus Buffers/Drivers (with 3-state Output)
Hex Bus Buffers/Drivers (with 3-state Output)
Hex Bus Buffers/Drivers (with 3-state Output)
Hex Bus Buffers/Drivers (with 3-state Output)
•
-
140
-
-
-
245
365A
366A
367A
368A
H D74S Series
HD74LS Series
HD74LS Series
-
-
AND-OR-INVERT GATES
Function
HD74 Series
i
I
50
51
53
54
-
-
-
51
-
-
-
-
54
55
-
64
65
-
-
EXPANDER
Function
HD74 Series
Dual 4-input Expanders
•
HD74S Series
-
Expandable Dual2-wide 2-input AND-DR-INVERT Gates
Dual 2-wide 2-inpl.!t AND-DR-INVERT Gates
Expandable 4-wide 2-input AND-DR-INVERT Gate
4-wide 2-input AND-DR-INVERT Gate
2-wide 4-input AND-DR-INVERT Gate
4-2-3-2-input AND-DR-INVERT Gate
4-2-3-2-input AND-DR-INVERT Gate (with Open Collector Output)
•
HD74 Series
HD74S Series
HD74LS Series
60
FLIP FLOPS
HD74 Series
Function
J-K Master-Slave Flip Flop (AND Inputs)
Dual J-K Flip Flops
Dual D-type Edge-triggered Flip Flops
Dual J-K Flip Flops (with PR and CLR)
Dual J-K Flip Flops (with PR, Common CLR, and
72
73
74
76
HD74S Series
74
-
HD74LS Series
I
-
73
74A
76
78
-
-
Dual J-K Flip Flops
Dual J-K Positive Edge-triggered Flip Flops (With PR and CLR)
Dual J-K Negative-edge-triggered Flip Flops (with PR and CLR)
Dual J-K Negative-edge-triggered Flip Flops (with PRj
Dual J-K Negative-edge-triggered Flip Flops (with PR, Common CLR,
and Common CK)
107
-
Monostable Mu Itivibrator
Retriggerable Monostable Multivibrator
Dual Retriggerable Monostable Multivibrators
Hex D-type Flip Flops (with CLR)
Quad, D-type Flip Flops (with CLR)
Dual Monostable Multivibrators (with Schmitt Trigger)
121
-
-
-
-
123
174
175
221
174
175
-
122
123
174
175
221
HD74 Series
HD74S Series
HD74LS Series
-
90
92
93
Comm~n
CK)
-
112
113
114
-
107
109A
112
113
114
• COUNTERS
Function
Decade Counter
Divide-by-Twelve Counter
4-bit Binary Counter
Presettable Decade Counter/Latch
4-bit Binary Counter/Latch
90A
92A
93A
176
177
Synchronous Decade Counter
Synchronous 4-bit Binary Counter
Fully Synchronous Decade Counter
160
161
162
309
-
-
-
-
-
160
161
162
-
-
Fully Synchronolls 4-bit Binary Counter
Synchronous Decade Decimal Rate Multiplier
Synchronous Decade Up/Down Counter
163
167
190
Synchronous 4-bit Binary Up/Down Counter
Synchronous Decade Up/Down Counter
Synchronous 4-bit Binary Up/Down Counter
Decade Counter
4-bit Binary Counter
191
192
193
290
293
163
I
I
i
--1
=-J
I
Dual 4-bit Decade Counters
Dual 4-bit Binary Counters
Dual 4-bit Decade Counters
Synchronous Decade Up/Down Counter
Synchronous 4-bit Binary Up/Down Counter
•
HD74LS Series
HD74S Series
HD74 Series
Function
I
190
191
192
193
290
293
390
393
490
668
669
4-BIT, 5-BIT SHIFT/STORAGE REGISTERS
HD74 Series
Function
4-bit Right-Shift, Left-Shift Register
5-bit Shift Register (Dual Parallel-in, Parallel-out)
4-bit D-type Register (with 3-state Output)
4-bit Parallel-in, Parallel-out Bidirectional Shift Register
4-bit Parallel-in, Parallel-out Shift Register (J-K Inputs for First Stage)
4-bit Right-shift, Left-shift Register
HD74LS Series
HD74S Series
95A
96
173
194
195
-
-
-
95B
96
173
194A
195A
295B
-
• a-BIT SHIFT REGISTERS
HD74 Series
Function
8-bit Shift Register
8-bit Parallel-out Shift Register
Parallel-load 8-bit Shift Register
8-bit Parallel-in, Parallel-out Bidirectional Shift Register
8-bit Parallel-in, Parallel-out Shift Register (J-K Inputs for First Stage)
8-bit Universal Shift/Storage Register
91A
164
166
198
199
HD74S Series
HD74LS Series
-
91
164
166
-
-
HD74 Series
HD74S Series
147
148
-
-
-
148
299
• ENCODERS
Function
10-line-to-4-line Priority Encoder
8-line-t~-3-line Priority Encoder
HD74LS Series
• DECODERS/DEMULTIPLEXERS
HD74 Series
Function
BCD-to-Decimal Decoder
Excess 3-to-Decimal Decoder
Excess 3-Gray-to-Decimal Decoder
3-to-8-line Decoder
Dual 2-to-4-line Decoders/Demultiplexers
42A
43A
44A
4-line-to-16-line Decoder/Demultiplexer
Dual 2-line-to-4-line Decoders/Demultiplexers
Dual 2~line-to-4-line Decoders/Demultiplexers (With Open
Collector Output)
4-line-to-16-line Decoder/Demultiplexer (wi,th Open Collector Output)
310
HD74LS Series
HD74S Series
-
42
-
-
-
-
154
155
-
138
139
-
154
155
156
159
156
-
I
(to be continued)
• DECODERS/LAMP DRIVERS/BUFFERS
HD74 Series
Function
BCD-to-Decimal Decoder/Driver (with 30V Out.)
BCD-to-Decimal Decoder/Driver (with 15V Out.)
BCD-to-Seven Segment Decoder/Driver (with 30V Output)
BCD-to-Seven Segment Decoder/Driver (with 15V Output)
BCD-to·Seven Segment Decoder
BCD-to-Seven Segment Decoder
BCD-to-Decimal Decoder/Driver (with 60V Out.)
BCD-to-Seven Segment Decoder/Driver (with 15V Output)
BCD-to-Seven Segment Decoder/Driver
BCD-to-Seven Segment Decoder/Driver
•
HD74S Series
HD74LS Series
45
145
46A
47A
-
-
-
-
-
49
-
2".7
248
249
141
145
47
48
-
-
-
HD74 Series
HD74S Series
HD74LS Series
75
-
75
279
-
-
-
/
LATCHES
Function
Quad. Bistable Latches
4-bit Bistable Latch
Quad. S-R Latches
8-bit Addressable Latch
4-bit Bistable Latch
-
77
279
259
375
• RANDOM ACCESS MEMORIES (less than 256-bit)
HD74 Series
Function
64-bit Random Access Memory (16w by 4b)
HD74S Series
HD74LS Series
HD74S Series
HD74LS Series
89
• ARITHMETIC ELEMENTS
HD74 Series
Function
4-bit Binary Full Adder
4-bit Magnitude Comparator
Quad. 2-input Exclusive-OR Gates
Quad. Exclusive-OR/NOR Gates
Quad. 2-input Exclusive-OR Gates (with Open Collector Output)
8-bit Odd/Even Parity Generator/Checker
4-bit Arithmetic Logic Unit/Function Generator
Look-Ahead Carry Generator (for ALU)
Dual Carry Save Full Adders
Quad. 2-input Exclusive-NOR Gates (with Open Collector Output)
9-bit Odd/Even Parity Generator/Checker
4-bit Binary Full Adder (with Fast Carry)
Quad. 2-input Exclusive-OR Gates
83A
85
86
136
86
135
-
83A
85
86
136
180
-
-
-
181
182
181
182
H183
-
-
-
-
266
-
280
283
-
-
-
280
283
386
(to be continued)
311
• DATA SELECTORS/MULTIPLEXERS
Function
HD74 Series
HD74S Series
HD74LS Series
-
151
157
151
152
153
157
-
158
251
257
258
-
158
251
253
257
258
298
HD74 Series
HD74S Series
HD74LS Series
-
-
-
-
240
241
244
16-bit Data Selector/Multiplexer
8-bit Data Selector/Multiplexer (with Strobe)
8-bit Data Selector/Multiplexer
DuaI4-line-to-1-line Data Selectors/Multiplexers
Quad. 2~line-to-1-line Data Selectors/Multiplexers
150
151A
153
157
Quad. 2-line-to-1-line Data Selectors/Multiplexers
8-bit Data Selector/Multiplexer (with Strobe and 3-state Output)
Dual 4-line-to-1-line Data Selectors/Multiplexers (with 3-state Output)
Quad. 2-line-to-1-line Data Selectors/Multiplexers (with 3-state Output)
Quad. 2-line-to-1-line Data Selectors/Multiplexers (with 3-state Output)
Quad. 2-input Multiplexers (with Storage)
251
-
• MICROPROCESSOR SUPPORT FUNCTIONS
Function
Octal Buffers/Line Drivers/Line Receivers (Inverted 3-state Output)
Octal Buffers/Line Drivers/Line Receivers (Noninverted 3-state Output)
Octal Buffers/Line Drivers/Line Receivers (Inverted 3-state Output)
-
• OUTLINE
IDP-161
I DG-16 I
I DG-16A
I
312
I DG-20 I
,'
.
. . ~ REGIONAL O·FFI'CES
For furth~r information, contact your Regional Sales Office:
Eastern
Westerr
9700 Re~da Blvd. ••
1
Suite 208
Northridge, CA 91324
(213) 70l-p606
j
Central
6200 Savoy Drive, Suite 704
Houston, TX 77036
(713) 974-0534
TWX 910-881-7043
594 Marrett Road, Suite 22
Lexington, MA 02173
(617) 861-1642
TWX 710-326-1413
"
~ !tac~ ~me!a~2!:!r
1800 Bering Drive, San Jose, CA 95112
!nd Ie Sales and Sewice Division
(408).292-6404 .
. Symbol of Semiconductor Quolity, Worldwide
PIlIt-JTFn 1"-1 II ~ A
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