1981_Harris_Digital_Data_Book_Bipolar_CMOS_Volume_2 1981 Harris Digital Data Book Bipolar CMOS Volume 2

User Manual: 1981_Harris_Digital_Data_Book_Bipolar_CMOS_Volume_2

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BIPOLAR
CMOS

OJ
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en

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•

PRODUCTS DIVISION
A DIVISION OF HARRIS CORPORATION

Volume 2

1981

Volume 2

$2.95

HARRIS
Digital Data Book

Harris Semiconductor Digital Products represent stateof-the-art in density and high speed performance.
HARRIS expertise in design and processing offers
the user the most reliable product available in a wide
choice of formats, options, and package types. With
continuing research and development and the introduction of new products, Harris will provide its customers with the most advanced technology.
This book describes Harris Semiconductor Products
Division's complete line of digital products and includes
a complete set of product specifications and data
sheets. Also included are sections on reliability, programming, and packaging.
Please fill out the registration card at the back of this
book and return it to us so we may keep you informed
of our latest new product developments over the next
year.
If you need more information on these and other
HAR RIS products, please contact the nearest HAR R IS
sales office listed in the back of this data book.

Harris Semiconductor's products are sold by description only.
HARRIS reserves the right to make changes in circuit design,
specifications and other information at any time without prior
notice. Accordingly, the reader is cautioned to verify that data
sheets and other information in this publication are current
before placing orders. Information contained in application notes
is intended soley for general guidance; use of the information for
user's specific application is at user's risk. Reference to products
of other manufacurers are solely for convenience of comparison
and do not imply total equivalency of design, performance,
or otherwise.

Printed In USA

General Information
Alpha-Numeric Index of
Total HARRIS Product
Devices by Families
Data Sheet Classifications
IC Handling Procedure
HARRIS Memory Selection Guide
Bipolar PROM Cross Reference Guide
Users' Guide to MOS Static RAMs

(1-1)
(1-4)
(1-5)
(1-6)
(1-7)
(1-8)
(1-9)

Bipolar Memory
CMOS Memory
CMOS Interface
CMOS Microprocessor
Microprocessor Support Systems
HARRIS Reliability & Quality
Ordering & Packaging

o ice

Information

HARRIS ·Sales Locations

iii

•

••
•
•--

Ell
Ell

Ell
III

Total HARRIS Product Index
CATALOG PAGE NUMBER
ANALOG
HA-909/911
HA-1600/02/05
HA-1610/15
HA-1620/25
HA-2400/04/05
HA-2420/25
HA-2500/02/05
HA-2507 /17 /27
HA-2510/12/15
HA-2520/22/25
HA-2530/35
HA-2600/02/05
HA-2607/27
HA-2620/22/25
HA-2630/35
HA-2640/45
HA-2650/55
HA-2700/04/05
HA-2720/25
HA-2730/35
HA-2900/04/05
HA-4602/05
HA-4622/25
HA-4741
HA-4900/05
HA-4920/25
HA-4950
HA-51 00/05
HA-5110/15
HA-5130/35
HA-5160
HA-5190/95
HC-55516/32
HC-55536
HD-0165
HD-4702
HD-6101

Low Noise Operational Amplifier
Precision 10V Reference
Precision 10V Reference
Precision 5V Reference
Programmable Analog Module
Sample/Hold
High Slew Rate Amplifier
High Slew Rate Amplifier
High Slew Rate Amplifier
High Slew Rate Amplifier
High Slew Rate Wideband Inverting Amplifier
High Impedance Amplifier
High Impedance Amplifier
High Impedance Wideband Amplifier
Unity Volt Gain Current Amplifier
High Voltage Operational Amplifier
Dual High Performance Operational Amplifier
General Purpose Amplifier
Wide Range Programmable Operational Amplifier
Wide Range Dual Programmable Operational Amplifier
Chopper Stabilized Operational Amplifier
High Performance Quad Operational Amplifier
Wideband Quad Op Amp
Quad 471 Operational Amplifier
Precision Quad Comparator
High Speed Quad Comparator
Precision High Speed Comparator
JFET Input Wideband Operational Amplifier
JFET Input Wideband Operational Amplifier
Precision Operational Amplifier
High Slew Rate JFET Operational Amplifier
Fast Settling Operational Amplifier
16kHz CVSD
Decode Version Only
16 Line Keyboard Encoder
Programmable Bit Rate Generator
Parallel Interface Element

HD-6402
HD-6408
HD-6409
HD-6431
HD-6432
HD-6433
HD-6434
HD-6435
HD-6436
HD-6440
HD-6495
HD-6600
HD-15530

Universal Asynchronous Receiver/Transmitter
Asynchronous Serial Manchester Adapter (ASMA)
CMOS Manchester Encoder-Decoder (MED)
CMOS Hex Latching Bus Driver
CMOS Hex Bi-directional Bus Driver
CMOS Quad Bus Separator/Driver
CMOS Octal Resettable Latch
CMOS Hex Resettable Latch
CMOS Octal Bus BufferlDriver
CMOS Latch Decoder Driver
CMOS Hex Bus Driver
Quad Power Strobe
Manchester Encoder-Decoder

1-1

DIGITAL

2-6
4-2
4-6
1-14
2-10
4-9
2-14
2-18
2-20
2-24
2-28
2-32
2-36
2-38
2-42
2-46
2-50
2-54
2-58
2-64
2-70
2-74
2-81
2-87
2-91
2-9B
2-103
2-108
2-114
1-15
1-16
2-120
5-2
1-24
5-7
4-3
5-29
4-7
4-12
4-17
4-28
4-31
4-34
4-37
4-40
4-43
4-46
4-50
2-4
4-53

CATALOG PAGE NUMBER
ANALOG

HD-15531
HI-200
HI-201
H 1-300/301/302/303
H 1-304/305/306/307
H 1-381/384/387/390
HI-506/507
HI-506A/507A
HI-508/509
H 1-508A/509A
HI-516
HI-518
HI-562
HI-1800
HI-1818A/28A
HI-1840
HI-5040
HI-5041
HI-5042
HI-5043
HI-5044
HI-5045
HI-5046
HI-5046A
HI-5047
HI-5047A
HI-5048
HI-5049
HI-5050
HI-5051
HI-5610
HI-5900
HI-5901
HM-104
HM-168
HM-186
HM-198
HM-410
HM-6100
HM-6322
HM-6501
HM-6503
HM-6504
HM-6505
HM-6508
HM-6512
HM-6513
HM-6514
HM-6515
HM-6516
HM-6518
HM-6551
HM-6561

Manchester Encoder-Decoder
Dual SPST CMOS Switch
Quad SPST CMOS Switch
Dual SPST CMOS Switch
Dual SPST CMOS Switch
Dual SPST CMOS Switch
Single Ended 16 Channel CMOS MUX
Single Ended 16 Channel Overvoltage Protected
Single 8 Channel CMOS MUX
Single Ended 8 Channel Overvoltage Protected
16 Channel/Differential 8 Channel CMOS Hi-Speed MUX
8 Channel/Differential 4 Channel CMOS Hi-Speed MUX
12 Bit D/A Converter
Dual DPDT Switch
8 Channel Dual 4 Channel Multiplexer
16 Channel MUX-High Z
SPSTSwitch
Dual SPST Switch
SPDT Switch
Dual SPDT Switch
DPST Switch
Dual DPST Switch
DPDT Switch
DPDT Switch
4PST Switch
4PST Switch
Dual SPST Switch
Dual DPST Switch
SPDT Switch
Dual SPDT Switch
10 Bit Hi-Speed D/A Converter
Differential DAS Front End
Single Ended DAS Front End
lOx 4 50ns Diode Matrix
6 x 8 50ns Diode Matrix
8 x 6 50ns Diode Matrix
9 x 8 50ns Diode Matrix
4 x 10 50ns Diode Matrix
12 Bit Static CMOS Microprocessor
1024 x 12 CMOS ROM
256 x 4 CMOS RAM
2048 x 1 CMOS RAM
4096 x 1· CMOS RAM
4096 x 1 CMOS RAM
1024 x 1 CMOS RAM
64 x 12 CMOS RAM
512 x 4 CMOS RAM
1024 x 4 CMOS RAM
1024 x 8 CMOS RAM
2048 x 8 CMOS RAM
1024 x 1 CMOS RAM
256 x 4 CMOS RAM
256 x 4 CMOS RAM

*Data Sheet Only

1-2

DIGITAL

4-60
3-4
3-10
1-18
1-19
1-20
3-28
3-34

*
3-40
3-46
3-49
4-13
3-16
3-52
3-56
3-20
3-20
3-20
3-20
3-20
3-20
3-20
3-20
3-20
3-20
3-20
3-20
3-20
3-20
4-22
4-35

*
2-7
2-7
2-7
2-7
2-7
5-7
3-4
3-10
3-16
3-22
3-30
3-36
3-42
3-48
3-54
3-62
3-66
3-70
3-76
3-82

CATALOG PAGE NUMBER
ANALOG
HM-6562
HM-6564
HM-6611
HM-6641
HM-6661
HM-6716
HM-6758
HM-7602/03
HM-7608
HM-7610/11
HM-7610A/11A
HM-7620/21
HM-7620Al21A
HM-7640/41
HM-7640A/41A
HM-7642/43
HM-7642A/43A
HM-7642P/43P
HM-7644
HM-7647R
HM-7648/49
HM-7680/81
HM-7680A/81A
HM-7680R/81 R
HM-7680RP/81 RP
HM-7684/85
HM-7684P/85P
HM-7616
HM-76160/161
JAN-512
HB-61000
HB-61001

256 x 4 CMOS RAM
8192 x 8 CMOS RAM
256 x 4 CMOS PROM
512 x 8 CMOS PROM
256 x 4 CMOS PROM
2048 x 8 CMOS EPROM
1024 x 8 CMOS EPROM
32 x 8 Bit Generic PROM
1024 x 8 Bit Generic PROM
256 x 4 Bit Generic PROM
256 x 4 Bit Generic PROM-45ns
512 x 4 Bit Generic PROM
512 x 4 Bit Generic PROM-50ns
512 x 8 Bit Generic PROM
512 x 8 Bit Generic PROM -50ns
1024x 4 Bit Generic PROM
1024 x 4 Bit Generic PROM-50ns
1024 x 4 BIT Generic PROM - Power Down
1024 x 4 Bit Generic PROM-Active Pullup
512 x 8 Bit Generic PROM-Latched Outputs
512 x 8 Bit Generic PROM
1024 x 8 Bit Generic PROM
1024 x 8 Bit Generic PROM-50ns
1024 x 8 Bit Generic PROM-Latched Outputs
1024 x 8 Bit Generic PROM-Powerdown with Latched Outputs
2048 x 4 Bit Generic PROM
2048 x 4 Bit Generic PROM - Power Down
2048 x 8 Bit Generic PROM
2048 x 8 Bit Generic PROM
M38510/2010BJB PROM
Micro-12 HM-6100 Evaluation Board
Micro-12, 4K x 12 Memory Board

1-3

DIGITAL
3-88
3-94
3-104
3-110
3-115
3-121
3-122
2-11
2-50
2-14
2-17
2-20
2-23
2-26
2-29
2-32
2-35
2-38
2-41
2-44
2-47
2-53
2-56
2-59
2-65
2-69
2-72
2-75
2-78
2-81
6-4
6-8

III

•

Devices by Families
Bipolar PROMs
JAN 0512
HM-7602/03
HM-7610/11
HM-7610A/11A
HM-7616
HM-76160/161
HM-7620/21
HM-7620A/21A
HM-7640/41
HM-7640A/41A
HM-7642/43
HM-7642A/43A
HM-7642P/43P
HM-7644
HM-7647R
HM-7648/49
HM-7608
HM-7680/81
HM-7680A/81A
HM-7680R/81 R
HM-7680P/81P
HM-7680RP/81 RP
HM-7684/85
HM-7684P/85P
CMOS Bus Drivers
HD-6431
HD-6432
HD-6433
HD-6434
HD-6435
HD-6436
HD-6440
HD-6495
MIL-STD-1553
Support Circuits
HD-15530
HD-15531
p.P
HM-6100
HD-6101

CMOS RAMs

Page
2-81
2-11
2-14
2-17
2-75
2-78
2-20
2-23
2-26
2-29
2-32
2-35
2-38
2-41
2-44
2-47
2-50
2-53
2-56
2-59
2-62
2-65
2-69
2-72

HM-6501
HM-6503
HM-6504
HM-6505
HM-6508
HM-6512
HM-6513
HM-6514
HM-6515
HM-6516
HM-6518
HM-6551
HM-6561
HM-6562
HM-6564
CMOS Interface
HD-4702
HD-6402
HD-6408
HD-6409
CMOS PROMs
HM-6611
HM-6641
HM-6661
HM-6716
HM-6758

Page
4-28
4-31
4-34
4-37
4-40
4-43
4-46
4-50

CMOS ROMs
HM-6322
Quad Power Strobe
HD-6600

Page

Diode Matrices

4-53
4-60

HM-0104
HM-0168
HM-0186
HM-0198
HM-0410

Page
5-7
5-29

1-4

Page
3-10
3-16
3-22
3-30
3-36
3-42
3-48
3-54
3-62
3-66
3-70
3-76
3-82
3-88
3-94
Page
4-3
4-7
4-12
4-17
Page
3-104
3-110
3-115
3-121
3-122
Page
3-4
Page
2-4
Page
2-7
2-7
2-7
2-7
2-7

Data Sheet Classifications
CLASSIFICATION

Pl1Ivi,w
DATA
SHEET

Advanc,
Information

DISCLAIMERS

PRODUCT STAGE

Formative or
Design

This document contains the design specifications
for product under development. Specifications
may be changed in any manner without notice.

Sampling or
Pre-Production

This is advanced information, and specifications
are subject to change without notice.

First Production

Supplementary data may be published at a
later date.

DATA SHEET

Preliminary
DATA SHEET

Harris reserves the right to make changes at any~
time without notice, in order to improve design
and supply the best product possible.

1-5

•

I. C. Handling Procedures
charge. It is evident, therefore, that proper handling procedures or rules should be adopted.

Harris I.C. processes producetircuits more
rugged than similar ones.
However, no semiconductor is immune from damage resulting from
the sudden application of many thousands of volts
of static electricity. While the phenomenon of
catastrophic failure of devices containing MOS
transistors or capacitors is well known, even bipolar circuits can be damaged by static discharge,
with altered electrical properties and diminished
reliability.
None of the common I.C. internal
protection networks operate quickly enough to
positively prevent damage.

Elimination or reduction of static charge can be
accomplished as follows:
• Use conductive work stations. Metallic or
conductive plastic* tops on work benches
connected to ground help eliminate static
build-up.
• Ground all handling equipment.
• Ground all handling personnel with a conductive bracelet through 1-M ohm to ground.
The 1-M ohm resistor will prevent electroshock
injury to personnel .

It is suggested that all semiconductors be handled,
tested, and installed using standard "MOS handling
techniques" of proper grounding of personnel and
equipment. Parts and subassemblies should not be
in contact with untreated plastic bags or wrapping
material. High impedance I.C. inputs wired to a
P.C. connector should have a path to ground
on the card.

• Smocks, clothing, and especially shoes of
certain insulating materials (notably nylon)
should not be worn in areas where devices are
handled. These materials, highly dielectric in
nature, will hold, or aid, in the generation of
a static change. Where they cannot be eliminated natural materials such as cotton etc.
should be used to minimize charge generation
capacity.

HANDLING RULES
Since the introduction of integrated circuits with
MOS structures and high quality junctions, a safe
and effective means of handling these devices has
been of primary importance. One method employed to protect gate oxide structures is to incorporate input protection diodes directly on the
monolithic chip. However, there is no completely
foolproof system of chip input protection in existance in the industry. In addition most compensation networks in linear circuits are located at
high impedance nodes, where protection networks
would disturb normal circuit operation. If static
discharge occurs at sufficient magnitude (2kV or
morel. some damage or degradation will usually
occur. It has been found that handling equipment
and personnel can generate static potentials in
excess of 10KV in a low humidity environment;
thus it becomes necessary for additional measures
to be implemented to eliminate or reduce static

• Control relative humidity to as high as a
level as practical. (RH 50%).
• Ionized air blowers reduce charge build-up
in areas where grounding is not possible or
desirable.
• Devices should be in conductive carriers during
all phases of transport. Leads may be shorted
by tubular metallic carriers, conductive foam
or foil.
• In automated handling equipment, the belts,
chutes, or other surfaces should be of conducting material. If this is not possible, ionized
air blowers may be a good alternative.

* Supplier 3M Company "Velostat"

1-6

HARRIS Memory Selection Guide
NUMBER
WORDS

...------.

•

4
BYTE SIZE

1-7

Bipolar PROM Cross Reference
AMD
AM 27 LS08
AM 27S08
AM 29750
AM 27S18
AM 27LS09
AM 27S09
AM 29751
AM 27S19
AM 27LS100
AM 27810
AM 29760
AM 27LS20
AM 27LSll
AM27811
AM 29761
AM 27L821
AM 27812
AM 29770
AM 27813
AM 29771

HARRIS
7602

INTEL
3601
3621
3602/02A
3622/22A
3604/04A
3604L
3624/24A
3605
3625
3608
3628

HARRIS
7610/10A
7611/11A
7620/20A
7621/21A
7640/41 A

MOTOROLA
MCM5303A
MCM7640
MCM7641
MCM7642
MCM7643
MCM2708

HARRIS
JAN 0512
7640/40A
7641/41A
7642
7643
7608

RAYTHEON
29660
29662
29661
29663
29611
29613
29620
29622
29624
29625
29621
29623
29625
29627
29630
29632
29631
29633
29634
29635
29636
29637

HARRIS
7610/10A

7603

7610/10A

FAIRCHILD
93417
93427
93436
93446
93438
93448
93452
93453
93450
93451
rERSIL

7611/11A

5
5
5

HARRIS
7610/10A
7611/11A
7620/20A
7620/21 A
7640/40A
7641/41 A
7642
7643
7680
7681

FUJITSU
MB7056
MB7051
MB7057
MB7052
MB7058
MB7053
MB7059
MB7054
MB7060
MB7055

HARRI5
7602
7603
7610/10A
7611/11A
7620/20A
7620/21 A
7642
7643
7680
7681

ARRIS
161
761
76' 'lOA
16'
IA

NMI
6330
6331
6300
6301
6305
6306
6348
6340
6349
6341
6352
6353
63BO
6381
6385
63100
63101

HARRIS
7602
7603
7610/10A
7611/11A
7620/20A
7621/21A
7648
7640/40A
7649
7641/41 A
7642
7643
76BO
7681
7608
7684
7685

NEC
PB403
/.IPB405
/.IPB425
j!PB406
UPB426
UPB40B
/.IPB428
/.IPB427

HARRIS
7610 lOA
7640/40A
7641/41A
7642
7643
7680
76B1
7608

TEXA5IN5T.
7451BB/188A
7452BB
74186
745387
7¢S287
745473
745475
745472
745474
748477
748476

HARRIS
7602
7603
JAN 0512
7610/10A
7611/11A
7648
764040A
7649
7641/41A
7642
7643

7620/20A

7621/21A

A
IA

7641/41 A
7642
7643
7680
7681

7611/11A
7620/20A
7648
7640/40A
7649
7641/41 A
7680
7681
7608

NATIONAL
DM8577

HARRIS
7602

DM74:
DM74: 17
DM7¢ 13
DM8:
15
DM74: 12
DMS:
16
DM7¢ 12
DM74,573
DM8: ,229

7Ul0
71

DM27LS06

76U!!

SIGNETICS
82823
828123
82827
825126
825129
828130
825131
825146
825140
825147
828141
825136
825137
825180
825181
8252708
825184
825185
825190
828191

HARRIS
7602
7603
7610/10A

OA
IA

i48
i40/40A
>49
i41/41A
>42
7U¢3
7UBe

1-8

7611/11A
7620/20A
7621/21A
7648
7640/40A
7649
7641/41A
7642
7643
7680
7681
7608
7684
7685
76160
76161

Users' Guide to MOS Static RAMs
II:

en
SIZE &
ORGANIZATION TYPE PINS
64x 12 CMOS

It:
~

:I:

:>
Q

i0(

6512
6508

6508

6518

...'"l-

:>
"-

l:
V

I-

...w

I-

8401

...iii
II:

w
l-

2'"
o~
~~
~'"

6512
6508

6608

6518

...w

I-

iii

J!!
i

"I-w

l3~

CMOS
18

lKx 1

266 x 4

NMOS

9102

16
18

6662
6561

6501

22
22
16

6551

4102

2112

22
2K
2Kx 1

CMOS
NMOS
CMOS
2K
512x4 NMOS
4K

CMOS

4Kx 1

NMOS

2111

2112
9111
2101
9101

18
18
18
18

6603

6504
6505

4256

2101

0(-

1-"-

"'j:

'"2

;;:
0

v
II:

Qz
::::i~

"iii

6508
5001
1821

443

6518
74C930
2125 2102 2102
2125
2115

2102
2125

5040
5101
1822

5101
510l

145101

2112

4C92O
6551
2112

2111

4111

2112
2606
2111

2101

4101

2101

6551
9112

0
j:

"I-w

II:

5lb!

'"Q

5102

6508

5508

2102

2102
4033

5101

2112

4043

2111
,2112
2101

4042

...8
N

74C921
6652

435101 5101

5101

NMOS

6561

CMOS

0
I0

I-v

'"j:
V

6518

2102
2125

4015
4025

II:

...

7001
6508
6508 74C929

1902

16
lK

...0
0(

5007
5501
5101

4112

4039

6513
2113
6504
6505

4316
6147

8404

6504

6504
6847

2147

2141
2147

4104
2147

6514

444

5104

20
9146
9147

NMOS
20

8K
lK x8

CMOS
NMOS

24
24

6615

16K

CMOS

6516

NMOS

4104
2147

2147

2613

2147
4044

315D

4046

2114

6514

2114

4804

472114 2114
6148 2148

2148

6514

21C14 58981

6848
2148

2114
2148

2148
2114

445
2114

5114
5115
2114

2114

2614

2114

5047
314A

4046

4047
2142

2141
2142

2142

5614

5114

9130
9131

2Kx8

2141
2147

6148
4334

CMOS
9124
9135
9114
9148

6147
4847

4200
8414

6514

20
18
lK x4

4104
4200

2147

9140

4017
2147

4118
4801

8118

---

""D
421-3

""D
446

6116

5516
2128

4802

4016

2016

4104
6104

2-1

Product Index

PAGE
HD-6600
HM-0168
HM-0186
HM-0410
HM-0104
HM-0198
HM-7602/03
HM-7610/11
HM-7610A/11A
HM-7620/21
HM-7620A/21A
HM-7640/41
HM-7640A/41A
HM-7642/43
HM-7642A/43A
HM-7642P/43P
HM-7644
HM-7647R
HM-7648/49
HM-7608
HM-7680/81
HM-7680Al81A
HM-7680R/81 R
HM-7680P/81P
HM-7680RP/81 RP
HM-7684/85
HM-7684P/85P
HM-7616
HM-76160/161
JAN-0512

Quad Power Strobe
6 x 8 Monolithic Diode Matrices
8 x 6 Monolithic Diode Matrices
4 x 10 Monolithic Diode Matrices
10 x 4 Monolithic Diode Matrices
9 x 8 Monolithic Diode Matrices
32x8PROM
256 x 4 PROM
256 x 4 PROM
512 x 4 PROM
512 x 4 PROM
512 x 8 PROM
512 x 8 PROM
1K x 4 PROM
1K x 4 PROM
1K x 4 PROM
1K x 4 PROM
512 x 8 PROM
512 x 8 PROM
1K x 8 PROM
1K x 8 PROM
1K x 8 PROM
1K x 8 PROM
1K x 8 PROM
1K x 8 PROM
2K x 4 PROM
2K x 4 PROM
2K x 8 PROM
2K x 8 PROM
512 Bit PROM
MI L/M3851 0/201 01

PROM Programming
Programmer Evaluation
Data Entry Formats for HARRIS Custom Programming

2-4
2-7
2-7
2-7
2-7
2-7
2-11
2-14
2-17
2-20
2-23
2-26
2-29
2-32
2-35
2-38
2-41
2-44
2-47
2-50
2-53
2-56
2-59
2-62
2-65
2-69

2-72
2-75
2-78
2-81
2-86
2-89
2-90

ABSOLUTE MAXIMUM RATINGS

As with all semiconductors, stresses listed under "Absolute Maximum Ratings" may
be applied to devices (one at a time) without resulting in permanent damage. This
is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed under "Electrical
Characteristics" are the only conditions recommended for satisfactory operation.

2-2

Harris Generic Programmable
Read Only Memories

In 1970, Harris offered the industry's first Bipolar programmable read only memory, and
has been a leader in the field of Bipolar PROMs from 1970 to date. Harris PROMs are
manufactured using the Bipolar Junction Isolation process with reliability proven nickelchromium fusible links. Harris has had experience with nickel chromium since 1964 when
it was first used for high reliability military circuits because of its high stability characteristics. Harris has been manufacturing nickel-chromium fuse links since 1970 when the first
PROM was manufactured, and has become the industry's most extensive programmable
read only memory concept. This history has been a factor in giving Harris PROMs the industry's high programming yield and a proven level of quality and reliability.
We now employ a shallow diffused self-aligned emitter aperture process combined with
two-level aluminum interconnect. This state of the art process technology has been
deployed to produce large format devices with the high speed and versatility required
by the industry.
Today Harris offers a family of programmable read only memories which we call the
Generic PROMs or GPROMs. They have the following characteristics:
•

Coherent part numbering scheme, the 76xxx series.

•

Identical programming procedure for all GPROMs.

•

All parameters are guaranteed over full temperature and voltage.

•

The GPROM family comprises a complete range of formats.

JAN QUALI FI ED PROMS
The Harris Semiconductor Bipolar manufacturing line has received certification for processing JAN product. There are five QPL I qualified PROMs. Five additional HARRIS
PROMs have been granted QPL II listing pending QPL I approval and may be shipped as
JAN qualified product. Additional HARRIS PROMs are at various stages of qualification
and the status of each at press time is listed below. As the status of these products will
change rapidly, we suggest that you contact the nearest Harris Representative or Harris
Sales Office for current status.
HARRIS PART#
JAN 0512
HM1-7610
HM1-7611
HMl-7620
HMl-7621
HMl-7642
HM1-7643
HM1-7644
HM1-7602
HM1-7603
HMl-7640
HMl-7641

SLASH SHEET
MI L-M-38510/20101
MI L-M-38510/20301
MI L-M-3851 0/20302
MIL-M-38510/20401
MIL-M-38510/20402
M I L-M-3851O/20601
MIL-M-38510/20602
MIL -M-3851 0/20603
MIL-M-38510/20701
MIL-M-38510/20702
MIL-M-38510/20801
MI L-M-3851 0/20802

2-3

STATUS
BJB
BEB
BEB
BEB
BEB
BVB
BVB
BE B
BEB
BEB
BJB
BJB

QPL
QPL
QPL
QPL
QPL
QPL
QPL
QPL
QPL
QPL
QPL
QPL

•

SEMICONDUCTOR
HARR1S
PRODUCTS DIVISION

HD-6600

A DtVISION OF HARRIS CORPORATION

QUAD POWER STROBE

FEBRUARY 7978

Features
•

HIGH DRIVE CURRENT-200mA

•

HIGH SPEED SOns TYPICAL

•

TTL COMPATIBLE INPUTS

•

DIELECTRIC ISOLATION

•

QUAD MONOLITHIC CONSTRUCTION

•

POWER SUPPLY FLEXIBILITY

•

LOW POWER:
STANDBY-30mW/CIRCUIT

logic Diagram
NC

VCC3

ACTIVE-95mW/CI RCUIT
4

Description

VCC2

GND

Circuit Diagram
,.....----...- - - - 0

VCC2

._--DVCC3

~-Ml---------+---------'----OOUTPUT

INPUT

0---+"

~---------~----------------------~--~OGND

2-4

The H D-6600 Quad Power Strobe is constructed with Harris Dielectric
Isolation Bipolar Monolithic Process. The design incorporates power
supply flexibility with TTL compatible inputs and high current outputs.
This circuit is intended for use in power switched PROM arrays .

(ONE OF FOUR IDENTICAL STROBES)

VCCI

Specifications HD-6600
ABSOLUTE MAXIMUM RATINGS
Power Supply Voltage VCC1
VCC2
VCC3
Input Voltage VIN
Storage Temperature TSTG
Output Current I L
Power Dissipation at 25 0 C

+8 VDC
+18 VDC
+18 VDC
-0.5 VDC to +5.5 VDC
-65 0 C to +150 o C
-200m A
1000mW
(Derate 9mW!OC Above 60 0 C)

RECOI\I;MENDED OPERATING CONDITIONS
Power Supplies:

TA = -55 0 C to +125 0 C HD1-6600-2
T A = OOC to + 750 C H D 1-6600-5

ELECTRICAL CHARACTERISTICS

SYMBOL

PARAMETER

IIR

5 VDC ± 10%
12VDC±15%
5 VDC±20%

VCC1
VCC2
VCC3

MIN.

TYP.

Input Current

MAX.

UNITS

J.lA
mA

-1.6

"F
V,H

Input Threshold

V,L

Voltage

2.0

4.75

VOH

TEST CONDITIONS
V,N = 2.4 VDC
V,N =0.4VDC

4.85

VCC1 = 5.0 VDC

1.0

VCC1 = 5.0 VDC

'L = 500J.lA DC

6.0

VCC1 = 5.5 VDC

V,N = 2.4 VDC

VCC1 = 5.5 VDC

Output Voltage

D.C.

V,N = 0.4 VDC

(Note 1)
VOL
ICC1
ICC2

VCC1 = 5.5 VDC

VCC1 = 4.5 VDC

0.8

VCC2 = 12.0 VDC
VCC3 = 5.0 VDC

Supply Current

V,N = 0.4 VDC

'L = -150mA DC

'L =-150mA DC

(Note 2)
ICC2

VCC1 = 5.5 VDC
V,N = 2.4 VDC

SYMBOL

A.C.

PARAMETER

TYP.

MAX.

UNITS

'L = 0

CONDITIONS TA = 25 0 C

tON

Turn On Delay

VCC1 = 5.0 VDC

tOFF

Turn Off Delay

VCC2 = 12 VDC

Rise Time

RL = 33rl

Fall Time

CL = 620 pF

VCC3 = 5.0 VDC

NOTES

(1) One strobe enabled.

(2)

All strobes enabled.

Switching Time Definitions
INPUT

/,----,-----3VDC

tR·~

~t()FF

----OVDC

OUTPUT

VOL

III

2-5

•

Typical Characteristics

TYPICAL OUTPUT VOLTAGE vs.

TYPICAL OUTPUT VOL TAGE ...
LOAD CURRENT AND NUMBER OF STROBES ENABLED

VCC3 SUPPLY VOLTAGE
6.0,-~---r-----r----'-------:I

5.0

NUMBER OF STROBES

----i

TA-250C
VCC,-5VDC
VCC2-'2VDC
VCCl-5VDC

5.75

5.5

TA - 250C
VCC, =5VDC
VCC2-'2VDC

ONE STROBE

5.25

..
:>

< 4.85

5.0r-----+

S 4.75

:I:

4.8

4.5r------:;I1"'":;~fC--+----+_---___i

4.15

120

'00

140

160

180

200

5.0

TA = 250C

VCC2= '2VDC
VCCl= 5 VDC
RL-33(2

....
4. 9

>
.~

4.8

120

TA=250 C
VCC, =5VDC
VCC2=,2VDC
VCCl-5VDC

100

Rt:

I""'"

-20

+25

+40

+60

+15

+'00

-V

14. 7

-:i3S'f
toFF

-55 -40

6.0

TYPICAL DELAY tOFF AND tF v••
LOAD CAPACITANCE

vcc, =5VDC

5.75

VCC3 in Volts

TYPICAL OUTPUT VOL TAGE ...
AMBIENT TEMPERATURE

5.5

5.25

5.0

4.75

IL inmA

+125

200

400

600

800

1000

1200

1400

'600

1800

CL in pF

TAinOC

TYPICAL DELAY ...
AMBIENT TEMPERATURE

TYPICAL DELAY tON AND tR ...
LOAD CAPACITANCE

'20
VCC, =5VDC
VCC2-'2VDC
VCCl-5VDC
RL =33(2
CL =62OpF

'00
80
<

.. " ,.

---- ---

...... ..... ~--- ;:.:::.- ~
-

tOFF

---

TA - 250C
VCC, =5VDC
VCC2= '2VDC
VCCl-5VDC
RL=33n

'20
'00

~
'iI

;

o
-55 -40

-20

+25

+40

+60

+75

+100

200

+126

TA in oc

400

600

800

000

CL in pF

2-6

'200

'400

'800

800

HARRIS

MONOLITHIC DIODE

SEMICONDUCTOR
PRODUCTS DIVISION
A DIVISION OF HARRIS CORPORATION

MATRICES
Description

Features

Designed with the CMOS circuit engineer in mind, these
versatile diode matrices allow the application of logically
powerful programmable solutions to low power CMOS
system appl ications.

•

FIELD PROGRAMMABLE

•

CMOS COMPATIBLE

•

ZERO POWER DISSIPATION

•

FAST SWITCHING

•

fiVE POPULAR ORGANIZATIONS

These devices incorporate an advanced dielectric isolation
process to eliminate the need for power supply pins and
allow parasitic free operation.
Programming is accomplished by cleanly vaporizing a fusible link by application of a brief high voltage pulse to
a selected array element. This operation open circuits
a row to column orring diode eliminating their former
interaction.

Monolithic Structure

ROW
CONNECTION

--_I:'
SILICON
DIOXIDE

DIELECTRIC
LAVER
"P"TVPE
SILICON

Fusible link System

METALIZED
INTERCONNECT
LINE

DISCONNECTED
DIODE

INTACT
LINK
FUSED
LINK
CONNECTED
DIODE

" .... '"

.....

U 1 II L

2-7

•

Monolithic Diode Matrices
HM-0198
COLUMN CONNECTION PIN NO.

HM-0168 6 x 8

DIODE MATRICES

HM-0186 8 x 6

DIODE MATRICES

4~~~~~~~~~~~~

HM-0410 4 x 10 DIODE MATRICES

HM-0104 10 x 4 DIODE MATRICES
HM-0198 9x 8

5~~~~~~~~~~~~

~ 6~~~~~~~~~~~~
~

~ 7~~~~~~24~~~

DIODE MATRICES

~ H~~~~~~~~~~~~
~ 13~-}~~~~~~~~~~
14~-}~~~~~~~~~~

HM-0104

HM-0168

COLUMN CONNECTION PIN NO.

8
FUSIBLE

LINKS

COLUMN CONNECTION PIN NO.

4~~~~~~~

5~~~~~~~

12 10

~ 6~~~~~~~

fil

9~~~~~~~

~ 10o-+'4-~..:zr..f-""-

II:

HM-0410

HM-0186

COLUMN CONNECTION PIN NO.

17148139
COLUMN CONNECTION PIN NO.

11~-}~~~~.4:~~!I.4~~~~~~~~~

CUSTOM PATTERNS
When ordering a matrix with a custom pattern: Send a paper tape, or copy a matrix pattern and circle out those diodes
to be removed from the matrix. Another method to clearly identify a pattern is to callout respective anode and
cathode for each diode to be removed, by package pin number.

2-8

Specifications Diode Matrices
ABSOLUTE MAXIMUM RATINGS

Forward Current

100mA

Surge Current (100J.ls Max.)

200mA

Total Ckt. Dissipation (Still Air)

450mW

Storage Temperature (Ambient)

-65 0 C to

+1500 C

Maximum Ratings are limiting values above which permanent damage may occur.

ELECTRICAL CHARACTERISTICS

ITA
SYMBOL

PARAMETER

HM-OXXX-5

HM-OXXX-2
HM-DXXX-8

OOC to + 75°C

-55OC to +125OC

MIN

MAX

Forward Voltage

Reverse Breakdown Voltage

UNITS

1.5

V
V

IF
IF

IBV

IF = 10mA to IR = 10mA
Recovery to 1mA

trr

Reverse Recovery Time

Crosspoi nt Capacitance (1)

100

(1) Guaranteed but not 100% tested.
(2) Cc OC_1
_
VBIAS

TYPICAL PERFORMANCE CURVES
VOLTAGE Vf

'c-i.k"

WORST
DlODE@260C

"' WORST
DIODE I) -550C

CURRENT-mA

I ,/

o.5

0.3

o. 2
O. 1

0.2

I I
I I
2SOC..L, /-ssoc

0.4

= 20mA
= 1mA
= 100J.lA

250C

250 C

CONDITIONS

MAX

1.5
0.9

i
BVR

MIN

D••

0 .•

VOLTS

2-9

1.0

1.2

=5V; f = lMHz (2)

•

Programming

Use a simple supply capable of driving a 27 ohm resistor (carbon) with a clean transition from 0 to 24-30 volts in less
than 5OOlls, for at least 10ms. The diode to be disconnected is selected by setting the row and column switches 52
and 53 respectively as required. When switch 51 is depressed, programming current is provided to column contacts
in the matrix. This current opens the fusible link, in series with the selected diode. The peak fusing current required
to open a fusible lil1k is approximately 750 milliamperes. As the temperature of the fuse is raised, the aluminum
begins to melt. This melting continues until the fuse link separates. The cohesive forces of the melting aluminum
retracts the remaining portions of the metal, thereby preventing formation of loose aluminum residues. The melting
temperature of aluminum (approximately 6500 C) will not affect the passivating layer of silicon dioxide, whose melting
temperature is about 13500 C. Test verification is obtained by an indicator lamp or LED placed in series with the
column and row switches through the verify contacts of 51 to give electrical indication of the condition of each diode
in the matrix before and after fusing.
Caution: Programming is limited to one fuse at a time.

SIMPLE PROGRAMMER

PROGRAMMER TEST CONFIGURATION

SI DPDT MOMENTARV
82 17 POS, 1 POLE
S3ROTARV

01 Oz - 2N1613
INDICATOR LIGHT, LED

•

26 50 100 200
MICROSECONDS-

"Max TRISE = 500llsec
NOTE: The 27 ohm resistor is only used for oscilloscope
measurements of the Power Supply Characteristics
becaues it represents a typical unprogrammed
fuse/diode.

MATRIX UNDER TEST

2-10

HM-7602/03

HARRIS
SEMICONDUCTOR
PRODUCTS DIVISION

32 x 8 PROM

A DIVISION OF HARRIS CORPORATION

HM-7602 - Open Collector Outputs
HM-7603 - "Three State" Outputs

Pinouts

Features

TOP VIEW - DIP
•

50ns MAXIMUM ADDRESS ACCESS TIME

•

"THREE STATE" OR OPEN COLLECTOR OUTPUTS

°1

•

SIMPLE HIGH SPEED PROGRAMMING PROCEDURE ONE PULSE/BIT.
ASSURES FAST PROGRAMMING AND SUPERIOR RELIABILITY.

°2

FAST ACCESS TIME - GUARANTEED FOR WORST CASE N2 SEQUENCING OVER COMMERCIAL AND MILITARY TEMPERATURE AND VOLTAGE RANGES.

INDUSTRY'S HIGHEST PROGRAMMING YIELD

•

VCC

GND

OS,

Description
TOP VIEW - FLATPACK

The HM-7602/03 is a fully decoded high speed Schottky TTL 256/Bit
Field Programmable ROM in a 32 word by 8 bit/word format with open
collector (HM-7602) or "Three State" (HM-7603) outputs. These PROMs
are available in a 16 pin D.I.P. (ceramic or epoxy) and a 16 pin flatpack.
All bits are manufactured storing a logical "1" (Positive Logic) and can be
selectively programmed for a logical "0" in anyone bit position.
Nickel-chromium fuse technology is used on this and all other Harris
Bipolar PROMs.

01
°2
03
04
05
06
07
GND

1
2
3
4
5
6
8

The HM-7602/03 contains test rows which are in addition to the storage
array to assure high programmability and guarantee parametric and A.C.
performance. The fuses in these test rows are blown prior to shipment.
There is one chip enable input on the HM-7602/03.
the chip.

CE low enables

Functional Diagram

PIN NAMES
AO-A4
01 -OS
~

Address Inputs
Data Outputs
Chip Enable Inputs

logic Symbol

Aoll0}
Allll}

32.8

A21l2}

MEMORY ARRAY

A3113}
A41l4}

CEI15}

116} -vcc
18} =GND

16
15
14
13
12
11
10
9

IS}

(7)

(5)

(4)

(3)

2-11

VCC

CE
A4
A3
A2
Al
AO
08

•

Specifications HM-7602/03
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
-650 C to +1500 C
Operating Temperature (Ambient) -550 C to +1250 C
Maximum Junction Temperature
+1750 C

Output or Supply Voltage (Operating) -0.3 to +7.0V
Address/Enable I nput Voltage
5.5V
-20mA
Address/Enable Input Current
100mA
Output Sink Current

CAUTION: Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress only rating and functional operetion of the device at these or at any other conditions above those indicated in the operational
sections of this specification is not implied. (While programming, follow the programming specifications.)

D.C. ELECTRICAL CHARACTERISTICS (Operating)

PARAMETER

SYMBOL

MIN

HM-7602/03-5 (VCC = 5.0V ±5%, TA = ODC to +750 C)
HM-7602/03-2 (VCC = 5.0V ±10%, TA = -550 C to +1250 C)
Typical measurements are at T A = 250 C, VCC = +5V

TYP

MAX

UNITS

TEST CONDITIONS

IIH
III

Address/Enable
I nput Current

"I"
"0"

-50.0

+40
-250

IJA
IJA

VIH = VCC Max.
Vil = 0.45V

VIH
Vil

Input Threshold
Voltage

"I"

2.0

1.5
1.5

"0"

0.8

V
V

VCC=VCCMin
VCC = VCC Max.

VOH
VOL

Output Voltage

"I"

2.4'

3.2"
0-.35

0.45

V
V

lOt-( = -2.0I11A, VCC = VCC Min.
101"::" +lsniA, Vec = VCC Min.

10HE
10lE

Output Disable
Current

IJA
IJA

"0"

"I"

+100
-100

"0"

VOH; vee;: = Vee Max.
Val = 0.3V,'Vce = VCC Max.

VCl

Input Clamp Voltage

Output Short Circuit
Current

-15"

-1.2

lOS

--100'

VCC = VCC Max., VOUT = O.OV
One Output Only for a Max.
of! Secon!-T.S.

TEA

~
~I
I
I

A. C. TEST LOAD
VCC

OJ'~~ Ox o--~~-.....-O TEST POINT

soon

• Includeo jig " probe

total capacitance

2-22

VIL

I
I

•

TEA

lI
I

HM-7620A/21A

HARRIS
SEMICONDUCTOR
PRODUCTS DIVISION

HIGH SPEED 512

A DIVISION OF HARRIS CORPORATtON

x 4 PROM

HM-7620A - Open Collector Outputs
HM-7621A - "Three State" Outputs

Features

Pinouts

•

50ns MAXIMUM ADDRESS ACCESS TIME

•

"THREE STATE" OR OPEN COLLECTOR OUTPUTS

•

SIMPLE, HIGH SPEED PROGRAMMING PROCEDURE USING SINGLE
PULSES, ASSURES FAST PROGRAMMING AND SUPERIOR
RELIABILITY.

TOP VIEW - DIP

•

INPUTS AND OUTPUTS TTL COMPATIBLE

•

FAST ACCESS TIME - GUARANTEED FOR WORST CASE N2 SEQUENCING OVER COMMERCIAL AND MILITARY TEMPERATURE AND VOLTAGE RANGES.

•
•

vee

A.4

GND

INDUSTRY'S HIGHEST PROGRAMMING YIELD
PIN COMPATIBLE WITH INDUSTRY STANDARD PROM's AND ROM's.

Description
The HM"7620A/21A are fully decoded high speed Schottky TTL 2048Bit Field Programmable ROM's in a 512 word by 4 bit/word format with
open collector (HM-7620A) or "three state" (HM-7621A) outputs.
These PROMs are available in 16 pin D.I.P. (ceramic or epoxy) and a
16 pin flatpack.
All bits are manufactured storing a logical "1" (positive logic) and can be
selectively programmed for a logical "0" in any bit position.
The HM-7620A/21A contain test rows and columns which are in addition
to the storage array to assure high programmability and guarantee parametric and A.C. performance. The fuses in these test rows and columns
are blown prior to shipment.

TOP VIEW - FLATPACK

A6
A5
A4
A3
AO
A,
A2

4
5

7
S

GNO

Vee

16
15
14
13
12
11
10
9

1
2

A7
AS

CE
0,
°2
03
04

PIN NAMES

This PROM is intended for use in state of the art high speed logic systems.
Nickel-chromium fuse technology is used on these and all other Harris
Bipolar PROMs.

Ao-Aa
~

01-04

Functional Diagram

Address Inputs
Chip Enable Input
Data Outputs

Logic Symbol

A.4AsAeA1Aa

VCC"(,·,

(3' (2'

GND- (8)

(II 115' (,.,

CE
Ao

ROW

32 . . .
MEMORY

DECODER

ARRAY

ONE OF 32

A,
A2
A3
A4
As
AS
A7
A8

eel

.,.'9'

1101

(111
0,

t121
0,

2-23

0,
02
03
04

•

Specifications HM-7620AIHM-7621A
ABSOLUTE MAXIMUM RATINGS
Output or Supply Voltage (Operating) -0.3 to +7 .OV
Address/Enable Input Voltage
5.5V
Address/Enable Input Current
-20mA
Output Sink Current
l00mA

Storage Temperature
-650 C to +1500 C
Operating Temperature (.A,mbient) -550 C to +125 0 C
+175 0 C
Maximum Junction Temperature

CAUTION: Stresses above thoSe listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress only rating and functional operation of the device at these or at any other conditions above those indicated in the operational
sections of this specification is not implied. (While programming. follow the programming specifications.)

D.C. ELECTRICAL CHARACTERISTICS (Operating) HM-7620A/21A-5 (VCC = 5.0V 15%. TA = ooC to +750 C)
HM-7620A/21A-2 (VCC = 5.0V ±10%. TA = -550 C to +125 0 C)
Typical measurements are at TA = 250 C. VCC = +5V

SYMBOL

PARAMETER

MIN

TYP

MAX

UNITS

-50.0

+40
-250

fJA
fJA

VIH = VCC Max.
Vll= 0.45V

1.5
1.5

0.8

V
V

VCC = VCC Min.
VCC = VCC Max.

3.2"
0.35

0.45

V
V

10H = -2.0mA. VCC = VCC Min.
10l = +16mA. VCC = VCC Min.

IIH
III

Addresslenable
Input Current

"1"
"0"

VIH
Vil

Input Threshold
Voltage

"1"
"0"

2.0

VOH
VOL

Output
Voltage

"1"
"0"

2.4*

10HE
10lE

Output Disable
Current

"1"
"0"

VCl

I nput Clamp Voltage

lOS

Output Short Circuit
Current

ICC

Power Supply Current

+40
-40*

-15·

TEST CONOITIONS

VOH. VCC = VCC Max.
VOL = 0.3V. VCC = VCC Max.

fJA
fJA

-1.2

-100·

VOUT= O.OV
One Output Only for a Max.
of 1 Second

130

VCC = VCC Max. All Inputs
Grounded

liN = -18mA

'''Three State" only
NOTE: Positive current defined as into device terminals.

A.C. ELECTRICAL CHARACTERISTICS (Operating)

HM-7620A/21A -2
5V ±10%
-550 C to + 1250C

HM-7620Al21A - 5
5V±5%
OOC to+ 750C
PARAMETER

SYMBOL
TAA

Address Access Time

TEA

Chip Enable Access Time

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

A.C. limits guaranteed for worst case N2 sequencing with maximum test frequency of 5MHz.

CAPACITANCE: TA = 250 C (NOTE: Sampled and guaranteed - but not 100% tested.)

SYMBOL
CINA. CINCE
COUT

MAXIMUM

UNITS

TEST CONDITIONS

Input Capacitance

VCC = 5V. VIN = 2.0V. f = 1MHz

Output Capacitance

VCC = 5V. VOUT= 2.0V. f = 1MHz

PARAMETER

2-24

SWITCHING TIME DEFINITIONS

CE'-----....

ADDR~ES_-_-_-_-_-_-_-_-_-_-~~J~'~1.~5V~-----------VIH
VIL

OUTPUTS

____-+ __

TAA

,------- VOH
1.5V
VOL

_-----VIH
1.5V
-------VIL

OUTPUTS-------t----i<~____l_--~

T.S.

A.C. TEST LOAD

PROM
OUTPUT

0xO----3

(141

(151

2-29

(161
07

(171

Specifications HM-7640A141A
ABSOLUTE MAXIMUM RATINGS
Output or Supply Voltage (Operating) -0.3 to +7.0V
Address/Enable Input Voltage
5.5V
-20m A
Address/Enable Input Current
Output Sink Current
100mA
CAUTION:

Storage Temperature
-65 0 C to +1500 C
Operating Temperature (Ambient) -55 0 C to +125 0 C
Maximum Junction Temperature
+175 0 C

Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device.

These

are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational
sections of this specification is not implied. (While programming. follow the programming specifications.)

D.C. ELECTRICAL CHARACTERISTICS (Operating)

•

HM-7640A/41A-5 (VCC = 5.0V ± 5%, T A = DoC to +75 0 C)
HM-7640A/41A-2 (VCC = 5.0V± 10%, TA = -550 C to +1250 C)
Typical measurements are at T A = 25 0 C, VCC = +5V

SYMBOL

PARAMETER

MIN

TYP

MAX

UNITS

TEST CONDITIONS

IIH
IlL

Address/Enable "1"
Input Current
"0"

-50.0

+40
-250

I1A
I1A

VIH
VIL

Input Threshold "1"
Voltage
"0"

2.0

1.5
1.5

0.8

V
V

VOH
VOL

Output
Voltage

2.4*

3.2'
0.35

0.45

= Vec Max.
=0.45V
Vee = vee Min.
Vee = vee Max.
10H = -2.0mA, Vee = Vee Min.
10l = +16mA, Vee =Vee Min.

10HE
10LE

Output Disable "1"
Current
"0"

"1"
"0"

Vel

Input Clamp Voltage

105

Output Short Circuit

-15"

VIH
VIL

V
V

+40

VOH, Vee = Vee Max.
VOL = 0.3V, Vee = Vee Max.

I1A
I1A

-40'

V
mA

VOUT = O.OV, One Output at a
Time for a Max. of 1 Second

170

Vee =Vee Max., All Inputs
Grounded.

liN

Current

ICC

Power Supply Current

= -18mA

-1.2
-100'

125

NOTE: Positive current defined as into device terminals.

'''Three State" only

A.C. ELECTRICAL CHARACTERISTICS (Operating)

HM-7640Al41A
SV ±10%
-SSOC to + 12SoC

HM-7640A/41A
5V±5%
ooc to +7SOC
SYMBOL

PARAMETER

TAA

Address Access Time

TEA

Chip Enable Access Time

MIN

TYP

MAX
50

MIN

TYP

MAX

UNITS

A.C. limits guaranteed for worst case N2 sequencing with maximum test frequency of SMHz.

CAPACITANCE: T A = 250 C
SYMBOL
elNA, elNeE
eOUT

(NOTE: Sampled and guaranteed - but not 100% tested.)

MAXIMUM

UNITS

I nput Capacitance

Vee = 5V, VIN

Output Capacitance

Vee

PARAMETER

2-30

TEST CONDITIONS

= 2.0V, f = 1MHz

= 5V, VOUT = 2.0V. f = 1MHz

SWITCHING TIME DEFINITIONS

ADDRESSES ~~1_.5_V_ _ _ _ _

VIH
VIL

Ce, 8& CE2

: _---_ :

CE3&CE4':

I
I

l :i

-+!____~

-i
:

TAA

! k,.--""""'!f-.. . .>.--

OUTPUTS

DUTPUTS ___

---l

I--

TEA

A.C. TEST LOAD

Vee

PROM
OUTPUT

~ IH

CHIP ENABLES = = * 1 . 5 V

----.-<> TEST POINT

Ox 0----.....

60011

3OpF·

• Includes jig & probe

total capacitance

2-31

f-- --i
I
I

I
I

TEA

I
I

VIL

T.S.

HARRIS

HM-7642/43

SEMICONDUCTOR
PRODUCTS DIVISION

1K x 4 PROM

A DIVISION OF HARAIS CORPORATION

HM-7642 - Open Collector Outputs
HM-7643 - "Three State" Outputs

Features

Pinouts
TOP VIEW - DIP

•

60ns MAXIMUM ADDRESS ACCESS TIME

•

"THREE STATE" OR OPEN COLLECTOR OUTPUTS AND TWO CHIP
ENABLE INPUTS.

•

SIMPLE HIGH SPEED PROGRAMMING PROCEDURE - ONE PULSE/BIT.
ASSURES FAST PROGRAMMING AND SUPERIOR RELIABILITY.

•

FAST ACCESS TIME - GUARANTEED FOR WORST CASE N2 SEQUENCING OVER COMMERCIAL AND MILITARY TEMPERATURE AND VOLTAGE RANGES.
INDUSTRY'S HIGHEST PROGRAMMING YIELD

Description
The HM-7642/43 are fully decoded high speed Schottky TTL 4096Bit Field Programmable ROMs in a 1 K word by 4 Bit/word format with
open collector (HM-7642) or "Three State" (HM-7643) outputs. These
PROMs are avaliable in an 18 pin DIP (ceramic or epoxy) and an 18 pin
flatpack.
All bits are manufactured storing a logical "1" (positive logic) and can be
selectively programmed for a logical "0" in any bit position.
Nickel-chromium fuse technology is used on this and all other Harris
Bipolar PROMs.
The HM-7642/43 contains test rows and columns which are in addition
to the storage array to assure high programmability and guarantee parametric and A.C. performance. The fuses in these test rows and columns
are blown prior to shipment.
There are two chip enable inputs on the HM-7642/43. CEl and CE2
low enables the chip.

Functional Diagram

CEl
GND

CE2

TOP VIEW - FLATPACK

As~~~~~__~~~~~vCC
A5~

A4
A3
Ao
A,
A2

AS
Ag
0,
02
03

eE,

GND

CE2

PIN NAMES
AO-A9

01 -04
CEl,CE2

Address Inputs
Data Outputs
Chip Enable Inputs

Logic Symbol
A4

AS A6 A7 AS

(3)

(2)

(,) ('7) ('6) (15)

A.(S)
A, (6)
A2(?)
A3(4)

(t8) = Vee
(9)=GND

vcc

03(12)

02('3)

2-32

0,(14)

Specifications HM-1642143
ABSOLUTE MAXIMUM RATINGS

Storage Temperature
-65 0 C to +150 o C
Operating Temperature (Ambient) -55 0 C to +1250 C
+175 0 C
Maximum Junction Temperature

Output or Supply Voltage (Operating) -0.3 to +7.0V
5.5V
Address/Enable Input Voltage
-20mA
Address/Enable Input Current
Output Sink Current
100mA

CAUTION: Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress only rating and functional operation of the device at these or at any other conditions above those indicated in the operational
sections of this specification is not implied. (While programming, follow the programming specifications.)

D.C. ELECTRICAL CHARACTERISTICS (Operating)

PARAMETER

SYMBOL

MIN

IIH
III

Address/Enable
I nput Current

"1"
"0"

VIH
Vil

I nput Threshold
Volt.ge

VOH
VOL

Output Voltage

10HE
10lE

Output Disable
Current

HM-7642/43-5 (VCC; 5.0V ±5%, TA; ooC to +75 0 C)
HM-7642/43-2 (VCC ; 5.0V ±1 0%, T A; -550C to +1250 C)
Typical measurements are at T A; 250 C, VCC; +5V

TYP

MAX

UNITS
VIH
Vil

= Vee Max.
= 0.45V

Vec
VCC

= VCC Min
= VCC Max.

0.45

V
V

10H = -2.0mA, VCC = VCC Min.
10l = +16mA, VCC = VCC Min.

+100
-100

J.1A
J.1A

+40
-250

J.1A

-50.0

"1"
"0"

2.0

1.5
1.5

0.8

"1"
"0"

2.4'

3.2'
0.35

"1"
"0"

TEST CONDITIONS

J.1A.

VOH, VCC = VCC Max.
VOL = 0.3V, VCC = VCC Max.

Vel

Input Clamp Voltage

-1.2

lOS

Output Short Circuit
Current

-15'

-100'

Vec = Vce Max., VOUT = O.OV
One Output Only for a Max.
of 1 Second.

ICC

Power Supply Current

100

140

Vec = Vee Max. All Inputs
Grounded

liN

= -18mA

NOTE: Positive current defined as into device terminals
• "Three State" only

A.C. ELECTRICAL CHARACTERISTICS (Operating)
HM-7642/43
5V±10%
-55 0 C to + 12So e

HM-7642/43
SV±S%
ooe to +75 0 e
SYMBOL

PARAMETER

TAA

Address Access Time

TEA

Chip Enable Access Time

UNITS

MIN

TYP

MAX

MIN

TYP

MAX

A.C. limits guaranteed for worst case N2 sequencing with maximum test frequency of 5MHz.

CAPACITANCE: TA; 25 0 C
SYMBOL
CINA,CINCE
COUT

PARAMETER

TEST CONDITIONS

MAXIMUM

UNITS

Input Capacitance

VCC

Output Capacitance

Vec

2-33

= 5V, VIN = 2.0V, f = 1 MHz
= 5V, VOUT = 2.0V, f = 1MHz

SWITCHING TIME DEFINITIONS

ADDRESSES

VIH
: -------vIL

~"--- ~
,

!
,,

,
,,

OUTPUTS----+!----~VOH
-I

-----J.E.

CE18r CE2
:
CHIP ENABLE~.5V

1.5V

TAA

!
,,

OUTPUTS----~i--~-,
:

VOL

K','

--i TEA f--

I-

Vee

C~--...- - -...--O TEST POINT

600n

30pF*

* Includes jig

& probe

total capacitance

•

2-34

,
,

,,
,
,

>!--T.S.

--I TEA
I

A. C. TEST LOAD

PROM
OUTPUT

V
'i.5V
IH
----VIL

l,
I

HARRIS

HM-7642A/43A

SEMICONDUCTOR
PRODUCTS DIVISION

HIGH SPEED 1K x 4 PROM

A DIVISION OF HARRIS CORPORATION

HM-7642A - Open Collector Outputs
H M-7643A - "Three State" Outputs

Features
•
•
•
•

•

Pinout

SOns MAXIMUM ADDRESS ACCESS TIME.
"THREE STATE" OR OPEN COLLECTOR OUTPUTS AND TWO CHIP
ENABLE INPUTS
SIMPLE HIGH SPEED PROGRAMMING PROCEDURE ONE PULSE/BIT.
ASSURES FAST PROGRAMMING AND SUPERIOR RELIABILITY.
FAST ACCESS TIME - GUARANTEED FOR WORST CASE N2 SEQUENCING OVER COMMERCIAL AND MILITARY TEMPERATURE AND VOLTAGE RANGES.
INDUSTRY'S HIGHEST PROGRAMMING YIELD.

TOP VIEW-DIP
A6

Description
The HM-7642A/43A are fully decoded high speed Schottky TTL 4096Bit Field Programmable ROMs in a 1 K words by 4 Bit/word format with
open coliector(HM-7642A) or "Three State" (HM-7643A) outputs. These
PROM's are available in an la-pin DIP (ceramic or epoxy) and an la-pin
flat pack.

Vce

CE,

GND

CE2

All bits are manufactured storing a logical "1" (positive logic) and can be
selectively programmed for a logical "0" in any bit position.
TOP VIEW-FLAT PACK

Nickel-chromium fuse technology is used on this and all other Harris
Bipolar PROMs.
The HM-7642A/43A contains test rows and columns which are in addition to the storage array to assure high programmability and guarantee
parametrics and A.C. performance. The fuses in these test rows and
columns are blown prior to shipment.
There are two chip enable inputs on the HM-7642A/43A. CEl and CE2
low enables the chip.

Vce

A6
A5

A7
AS
Ag

A4
A3
AO

GEl

02
03
04

GND

GE2

Al
A2

Functional Diagram

PIN NAMES
AO-Ag
0,-04

CE"

CHIP ENABLE INPUTS

Logic Symbol

4096 BIT
MEMORY ARRAY

NOTE: Phvsical bit
positions for columns
are as follows:

64 TRANSMISSION GATES

CE 2

ADDRESS INPUTS
DATA OUTPUTS

02,04
01,03

= (0
=

~151

(15. 0

~141

( I = PIN NUMBERS
(lSI = Vee
(91 = GND

2-35

GE,
GE2
AO
A,
A2
A3
A4
A5
A6
A7
AS
Ag

0,
02
03
04

Specifications HM-7642A/43A
ABSOLUTE MAXIMUM RATINGS

Output or Supply Voltage (Operating)

-0.3 to +7.0V

Address/Enable I nput Voltage

Storage Temperature
Operating Temperature (Ambient)

5.5V

Address/Enable Input Current

-20mA

Output Sink Current

100mA

Maximum Junction Temperature

-65 0 C to +150 0 C
-55 0 C to +125 0 C
+175 0 C

CAUTION: Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational
sections of this specification is not implied. (While programming, follow tl}e programming specifications.)

HM-7642A/43A-5 vcc ~ 5.0V ±S%, TA ~ ooc to +750 C)
HM-7642A/43A-2 VCC ~ 5.0V ±1O%, T A ~ -55 0 C to +1250 C)

D.C. ELECTRICAL CHARACTERISTICS (Operating)

Typical Measurements are at T A ~ 25 0 C, VCC; +5V

SYMBOL

PARAMETER

MIN

TYP

MAX

UNITS

IIH
III

Address/Enable "1"
Input Current
"0"

-50.0

+40
-250

JiA
JiA

VIH = Vce Max.
Vil = 0.45V

VIH
Vil

Input Threshold "1"
Voltage
"0"

2.0
-

1.5
1.5

0.8

V
V

Vee = vee Min.
Vee = vee Max.

VOH
VOL

Output
Voltage

2.4*

3.2*
0.35

0.50

V
V

10H = -2.0mA, Vee = Vee Min.
10l = +16mA, Vee = vee Min.

10HE
10lE

Output Disable "1"
Current
"0"

"1"
"0"

+40
-40*

TEST CONDITIONS

VOH, Vee = vee Max.
VOL = 0.3V, Vee = vee Max.

JiA
JiA

Vel

Input Clamp Voltage

-1.2

lOS

Output Short Circuit
Current

-15*

-100*

VOUT = O.OV, One Output at a
Time for a Max. of 1 Second

ICC

Power Supply Current

100

140

vee = vee Max., All Inputs
Grounded.

liN = -18mA

NOTE: Positive current defined as into device terminals.
*"Three State" only

A.C. ELECTRICAL CHARACTERISTICS (Operating)

HM-7642A/43A
5V±5%
OOC to +75 0e
PARAMETER

SYMBOL

MIN

TYP

HM-7642A143A
5V ±10%
-550C to + 1250C

MAX

MIN

TYP

MAX

UNITS

TAA

Address Access Time

TEA

Chip Enable Access Time

A.C. limits guaranteed for worst case N2 sequencing with maximum test frequency of 5MHz.

CAPACITANCE: T A ~ 250 C

SYMBOL
eINA, elNeE
eOUT

(NOTE: Sampled and guaranteed - but not 100% tested.l

MAXIMUM

UNITS

Input Capacitance

PARAMETER

Vee = 5V, VIN

Output Capacitance

Vee = 5V, VOUT = 2.0V, f = 1MHz

2-36

TEST CONDITIONS

= 2.0V. f = 1MHz

SWITCHING TIME DEFINITIONS
,

VIH

ADDRESSES ~1.5V

~---VIH

, --------VIL

~------'t'

I',

I
I

~VOH

TAA

:;
I

OUTPUTS----1!---t(k,,_ _ _...

,
I
,, -

--l TEA f I
"I
A.C. TEST LOAD

Vee

PROM
OUTPUT Ox

---VIL

I~-J~ T.S.

OUTPUTS_ _~'I-_ _ _~ VOL

-I

1.5V

o---....-_~-o TEST POINT
3OpF*

* Includes jig & probe
total capacitance

2-37

--I
"I

TEA

I-I

HM-7642P/43P

HARRIS
SEMICONDUCTOR
PRODUCTS DIVISION

POWER DOWN 1K x 4 PROM

A DIVISION OF HARRIS CORPORATION

HM-7642P - Open Collector Outputs
HM-7643P - "Three State" Outputs

Advance Information

Features
•
•

•
•
•

Pinout

50ns MAXIMUM ADDRESS ACCESS TIME,
"THREE STATE" OR OPEN COLLECTOR OUTPUTS, A POWER DOWN
INPUT, AND A CHIP ENABLE INPUT.
SIMPLE HIGH SPEED PROGRAMMING PROCEDURE - ONE PULSE/BIT.
ASSURES FAST PROGRAMMING AND SUPERIOR RELIABILITY.
FAST ACCESS TIME FOR WORST CASE N2 SEQUENCING OVER COMMERCIAL AND MILITARY TEMPERATURE AND VOLTAGE RANGES.
INDUSTRY'S HIGHEST PROGRAMMING YIELD.

TOP VIEW - DIP

Description
The HM-7642P/43P are fully decoded high speed SchottkyTTL 4096-Bit
Field Programmable ROMs in a 1 K words by 4 bit/word format with open
collector (HM-7642P) or "Three State" (HM-7643P) outputs. These
PROM s are available in an 18-pin DIP (ceramic or epoxy) and an 18-pin
flat pack.

VCC

GND

All bits are manufactured storing a logical "1" (positive logic) and can be
selectively programmed for a logical "0" in any bit position.
Nickel-chromium fuse technology is used on this and all other Harris
Bipolar PROMs.

The HM-7642P/43P contains test rows and columns which are in addition to the storage array to assure high programmability and guarantee
parametrics and A.C. performance. The fuses in these test rows and columns are blown prior to shipment.
There is a power down input on the HM-7642P/43P which is similar to a
chip enable. The chip can be enabled or disabled using the power down
input where a powered down chip dissipates 25% of nominal power and
the outputs go to a high impedance state. The chip is powered up
when PDl is low.

TOP VIEW - FLAT PACK

02
03
04

GNO

PIN NAMES
AO-Ag
01 -04
PO
CE

.---'--Jr---, .. . . - - - - - - - - -......

A7
AS
Ag
0,

AO
A,

There is also the conventional chip enable input on this device,CE low and
PDl low enables the device.

Functional Diagram

vcc

AS
AS
A4
A3

ADDRESS INPUTS
DATA OUTPUTS
POWER DOWN INPUT
CHIP ENABLE INPUT

logic Symbol
4011 BIT
MEMORY ARRAY

...

NOTE: Physical bit
positions for columns
are as follows:
84 TRANSMISStON GATES

0,,03
02,04

= (15, 0 - 1 4 )
= (0-15)

( ) :::: Pin Numbers

= Vee
= GND

(18)
(9)

CE
AO
A,
A2

A3
A4

41s
AS
A7
AS
Ag

2-38

0,
02
03
04

Specifications HM-7642P143P
ABSOLUTE MAXIMUM RATINGS

Storage Temperature
-65 0 C to +150 0 C
Operating Temperature (Ambient) -55 0 C to +125 0 C
+175 0 C
Maximum Junction Temperature

Output or Supply Voltage (Operating) -0.3 to +7.0V
Address/Enable Input Voltage
5.5V
Address/Enable I nput Current
-20mA
100mA
Output Sink Current
CAUTION:

Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device.

These

D.C. ELECTRICAL CHARACTERISTICS (Operating)

HM-7642P/43P-5 (VCC = 5.0V i5%, TA = DoC to +75 0 C)
HM-7642P/43P-2 (VCC = 5.0V ±10%, T A = -55 0 C to +125 0 C)
Typical Measurements are at T A = 25 0 C, VCC = +5V

SYMBOL

PARAMETER

MIN

TYP

MAX

UNITS

IIH
IlL

Address/Enable "1"
"0"
Input Current

-50.0

+40
-250

J1A
J1A

VIH = Vee Max.
VI L = 0.45V

VIH
VIL

Input Threshold "1"
"0"
Voltage

2.0

1.5
1.5

0.8

V
V

Vee = VCC Min.
Vec = Vce Max.

VOH
VOL

Output
Voltage

"1"
"0"

3.2*
0.35

0.50

V
V

10H = -2.0mA, Vce = Vee Min.
10L = +16mA, VCC = vce Min.

10HE
IDLE

Output Disable
Current

"1"
"0"

2.4"

+40
-40'

TEST CONDITIONS

VOH, VCC = VCC Max.
VOL = 0.3V, VCC = Vce Max.

J1A
J1A

VCL

Input Clamp Voltage

-1.2

IDS

Output Short Circuit
Current

-15*

-100*

VOUT = O.OV, One Output at a
Time lor a Max. 01 1 Second

ICC

Power Supply Current

100

140

vee = VCC Max., All Inputs
Grounded.

ICCPD

Power Supply Current
During Power Down

Vec = VCC Max., All Inputs
Ground Except Pin 10.

liN = -18mA

NOTE: Positive current defined as into device terminals.
*"Three State" only

A.C. ELECTRICAL CHARACTERISTICS (Operating)

PARAMETER

SYMBOL

HM-7642P/43P-S

HM-7642P/43P-2

SV.:!:.S%
OOC to +75 0 C

-SSOC to + 12So C

SV.:!:.10%

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

200

TAA

Address Access Time

TDA

Chip Disable Access Time

TpU

Chip Power-Up Access Time

100

ISO

A.C. limits guaranteed for worst case N2 sequencing with maximum test frequency of 5MHz.

CAPACITANCE: T A = 25 0 C (NOTE: Sampled and guaranteed - but not 100% tested.)
SYMBOL
CINA, CINCE
COUT

PARAMETER

MAXIMUM

UNITS

I nput Capacitance

Vec = 5V, VIN = 2.0V, 1= lMHz

Output Capacitance

Vce = 5V, VOUT = 2.0V, I

2-39

TEST CONDITIONS

lMHz

SWITCHING TIME DEFINITIONS
I

ADDRESSES

~ 1.5V
I

CE & PO
CHIP ENABLES

VIH

~--------------VIL

I
I

TAA

I
I

~VOH

-I

OUTPUTS

VIH

.... 1.5V
----VIL

I
I

OUTPUTS

1
I

VOL

-I

TEA ,I-TpU

A.C. TEST LOAD
VCC

PROM
OUTPUT Ox O - - -....- -....~:> TEST POINT
30pF*

GOOn

* Includes Jig
and Probe Total

Capacitance

2-40

I
I

I
I
I

)t-T.S.

--I
I
I

'rOA

lI
I

HARRIS

HM-7644

SEMICONDUCTOR
PRODUCTS DIVISION

A DIVISION Of HARRIS CORPORATION

4 PROM

Active Pull-up Outputs

Pinouts

Features

TOP VIEW - DIP

•

60ns MAXIMUM ADDRESS ACCESS TIME

•

ACTIVE PULL-UP OUTPUTS

•

SIMPLE HIGH SPEED PROGRAMMING PROCEDURE ONE PULSE/BIT.
ASSURES FAST PROGRAMMING AND SUPERIOR RELIABILITY

•

FAST ACCESS TIME - GUARANTEED FOR WORST CASE N2 SEQUENCING OVER COMMERCIAL AND MILITARY TEMPERATURE AND VOLTAGE RANGES.

•

INDUSTRY'S HIGHEST PROGRAMMING YIELD

•

LOW PIN COUNT FOR MAXIMUM DENSITY

Vcc

GND

Description
TOP VIEW - FLATPACK

The HM-7644 is a fully decoded high speed Schottky TTL 4096-Bit
Field Programmable ROM in a 1 K word by 4 bit/word format with active
pull-up outputs. This PROM is available in a 16 pin DIP (ceramic or
epoxy) and a 16 pin flatpack.
All bits are manufactured storing a logical '"1'" (positive logic) and can be
selectively programmed for a logical '"0'" in any bit position.
Nickel-chromium fuse technology is used on this and all other Harris
Bipolar PROMs.
The HM-7644 contains test rows and columns which are in addition to
the storage array to assure high programmability and guarantee parametric and A.C. performance. The fuses in these test rows and columns
are blown prior to shipment.

3
AS
14
Ag
A3
4
13
AO
5
01
12
6
A1
11
02
10
A2
03
9
GND --__'8-________-'-----04

PIN NAMES

AO - A9
01 - 04

Address Inputs
Data Outputs

Logic Symbol

Functional Diagram
A4

131

AS A7

AS Ag

121 1.1 1.51 11411131

AD lSI
A.lal
A, 171
A.IOI

1.61- V ee
181-GND

A6 ----~~------~~-----VCC
16
A5
A7
15

0,(12)

0.1.01

2-41

Specifications HM-7644
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
-65 0 C to +150 o e
Operating Temperature (Ambient) -550 C to +125 0 e
Maximum Junction Temperature
+175 0 e

Output or Supply Voltage (Operating) -0.3 to +7.0V
Address/Enable Input Voltage
5.5V
Address/Enable Input Current
-20mA
Output Sink Current
100mA

CAUTION: Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress only rating and functional operation of the device at these or at any other conditions above those indicated in the operational
sections of this speciflca.tion is not implied. (While programming; follow the programming specifications.)

D.C. ELECTRICAL CHARACTERISTICS (Operating)

PARAMETER

SYMBOL

HM-7644-5 (Vee = 5.0V ±5%, T A = ooe to +750 e)
HM-7644-2 (Vce = 5.0V ±10%, TA = -55 0 e to +125 0 e)
Typical measurements are at T A = 250 e, Vce = +5V

MIN

TYP

MAX

UNITS

-50.0

+40
-250

JJA
JJA

VIH = VCC Max.
Vil = 0.45V

1.5
1.5

0.8

V
V

Vec = Vce Min
Vee = vee Max.

3.2
0.35

0.45

V
V

IOH = -2.0mA, Vee = vee Min.
IOL = +16mA, Vec = Vce Min.

IIH
III

Address/Enable
Input Current

"1"
"0"

VIH
VIL

Input Threshold
Voltage

"1"
"0"

2.0

VOH
Val

Output Voltage

"1"
"0"

2.4

TEST CONDITIONS

VCl

Input Clamp Voltage

-1.2

lOS

Output Short Circuit

-15

-100

VCC = Vee Max., VOUT = O.OV
One Output Only lor a Max.
011 Second.

100

140

Vee = vee Max. All Inputs
Grounded

liN'" -18mA

Current

Power Supply Current

ICC

NOTE: Positive current defined as into device terminals

A.C. ELECTRICAL CHARACTERISTICS (Operating)
HM-7644-2
5V ±10%
-55 0 C to + 1250 C

HM-7644-5
5V±5%
ooe to +75 O C
PARAMETER

SYMBOL

Address Access Time

TAA

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

A.C. limits guaranteed for worst case N2 sequencing with maximum test frequency of 5MHz.

CAPACITANCE: T A = 25 0 C
SYMBOL
CINA,elNC E
eOUT

MAXIMUM

UNITS

Input Capacitance

VCC = 5V, VIN = 2.0V, I = lMHz

Output Capacitance

Vce = 5V, VOUT = 2.0V, 1= 1MHz

PARAMETER

2-42

TEST CONDITIONS

SWITCHING TIME DEFINITIONS

VIH

1.5V

ADDRESSES

VIL

VOH

OUTPUTS

VOL
TAA

A. C. TEST LOAD

Vee

OJ':"~~

Ox o----<~-_-O TEST POINT

30pF*

600n

Includes Jig & probe

total capacitance

2-43

•

LATCHED OUTPUT
512 x 8 PROM

Features

Pinout

HARRIS

HM-7647R

SEMICONDUCTOR
PRODUCTS DIVISION
A. DIVISION OF HARRIS CORPORATION

•
•
•

SOns MAXIMUM ADDRESS ACCESS TIME
"THREE STATE" OUTPUTS WITH TWO CHIP ENABLE INPUTS
SIMPLE HIGH SPEED PROGRAMMING PROCEDURE - ONE PULSE/BIT.
ASSURES FAST PROGRAMMING AND SUPERIOR RELIABILITY.

•

FAST ACCESS TIME - GUARANTEED FOR WORST CASE N2 SEQUENCING
OVER COMMERCIAL AND MILITARY TEMPERATURE AND VOLTAGE
RANGES.

•
•

INDUSTRY'S HIGHEST PROGRAMMING YIELD
PIN COMPATIBLE WITH THE 82S115

•
•

LATCHED OUTPUTS
INPUT LOADING IS - 100PA MAXIMUM

TOP VIEW - D.I.P.
VCC
A2
A,
AO

Description
The HM-7647R is a fully decoded high speed Schottlky TTL 4096-Bit
Field Programmable ROM in a 512 word by 8 bit/word format and is
available in a 24 pin D.I.P. (ceramic or epoxy) and a 24 pin flatpack.

A7
AS
0,

CE,
CE2
STR

03
04

07
Os
Os
NC

NC
GND

All bits are manufactured storing a logical '.,.' (positive logic) and can be
selectively programmed for a logical "0" in any position. The HM-7647R
has "Three State" outputs.
Nickel-chromium fuse technology is used on this and all other Harris
Bipolar PROMs.

•

TOP VIEW - FLATPACK

The pinout is it:entical to the 82S115 PROM.

A3
A4

The HM-7647R contains test rows and columns which are in addition to
the storage array to assure high programmability and guarantee parametric
and A.C. performance. The fuses in these test rows and columns are
blown prior to shipment.

There are two chip enable inputs on the HM-7647R. CEl low and CE2
high enables the chip.
HM-7647R is operated in the Transparent Read Mode by holding the
strobe input high throughout the read operation. This is the normal read
mode where the two chip enable inputs will control the outputs.
In Latched Read Mode, bringing the strobe input low will latch the outputs and chip enable inputs. If the device is disabled when the strobe
input goes low the outputs will be latched in the high impedance state. If
the device is in the latched mode the strobe input must be brought high to
allow the outputs to respond to new address or chip enable conditions.

===ji'rr===

~
AS

~,
CE2

0,
02
03
04

STR
08
07
06

NC
GND

05
NC

PIN NAMES
AO-AS
01-0S
-CE2
STR

eel

Functional Diagram

Address Inputs
Data Outputs
Chip Enable Inputs
Latch Input

Logic Symbol

CE,
CE2
STR
AO
A,
A2
A3
A4
AS
AS
A7
AS

2-44

vcc
A2

0,
02
03
04
Os
Os
07
Os

Specifications HM-7647R
ABSOLUTE MAXIMUM RATINGS
Output or Supply Voltage (Operating)

-0.3 to +7.0V

Address/Enable Input Voltage

5.5V

Address/Enable Input Current

-20mA

Output Sink Current

100mA

Storage Temperature
Operating Temperature (Ambient)
Maximum Junction Temperature

-65 0 C to :,-1500 C
-55 0 C to +125 0 C
+1750 C

CAUTION: Stresses above those listed under the "Absolute Maximum R;,Jtings'" may cause permanent damage to the device. This is a
stress only rating and functional operation of the device at these or at any other conditions above those indicated in the operational
sections of this specification is not implied. (While programming, follow the programming specifications.)

D.C. ELECTRICAL CHARACTERISTICS (Operating)

SYMBOL

PARAMETER
Address/Enable

IIH
III

Input Current

"1"
"0"

VIH
Vil

Input Threshold
Voltage "0"

VOH
VOL
IOHE
10lE

MIN

HM·7647R-5 (VCC = 5.0V 2:5%, TA = ooC to +75 0 C)
HM-7647R-2 (VCC = 5.0V 2:10%, TA =-55 0 C to +125 0 C)
Typical measurements are at T A = 250 C, VCC = +5V

TYP

MAX

VIH ~ VCC Max.
Vil = 0.45V

V
V

VCC = Vce Min.
Vee = Vce Max.

0.50

V
V

10H = -2.0mA, VCC = VCC Min.
10l = +16mA, VCC = VCC Min.

+40
-40

f.1A
f.1A

-50

"1"
"0"

2.0

1.5
1.5

0.85

Output "1"
Voltage "0"

"1"
"0"

2.7(21

3.3
0.35

Output Disable
Current "0"

"1"
"0"

TEST CONDITIONS

f.1A
f.1A

+25
_100(1)

UNITS

VOH, VCC = Vce Max.
VOL = 0.3V, VCC = VCC Max.

VCl

Input Clamp Voltage

Output Short Circuit
Current

-20

-1.2

lOS

-70

VOUT=O.OV
One Output Only for a Max.
011 Second

ICC

Power Supply Current

135

185

VCC = Vce Max. All Inputs
Grounded

liN = -18mA

..
*Posltive current defined as Into device terminals.
NOTE(l):
NOTE(2):

Ill=-150f.1Alor-2
VOH = 2.4V lor -2

A.C. ELECTRICAL CHARACTERISTICS (Operating)

HM-7647R-5
5V:!:5%
Ooc to +750C
SYMBOL

HM-7647R-2
5V:!: 10%
-550C to +125 0C

PARAMETER

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

TAA
TEA

Address Access Time
Chip Enable Access Time

40
30

60
40

50
40

80
50

ns
ns

TADH
TCDH
TSW
TSl
TDl
TCDS

Address Hold Time
Chip Enable Hold Time
Strobe Pulse Width
Strobe Latch Time
Strobe Delatch Time
Chip Enable Set-Up Time

0
10
30
60
40

-10

-10
0
15
45
-

15
35
-

0
10
40
80
50

ns
ns
ns
ns
ns
ns

40
-

TEST CONDIT.

Transparent

latched

A.C. limits guaranteed for worst case N2 sequencing with maximum test frequency of 5MHz.

CAPACITANCE: T A = 25 0 C

SYMBOL
CINA, CINCE
COUT

(NOTE: Sampled and guaranteed - but not 100% tested.!

PARAMETER

Input Capacitance
Output Capacitance

MAXIMUM

UNITS

TEST CONDITIONS

VCC = 5V, VIN = 2.0V, I = 1MHz

VCC = 5V, VOUT = 2.0V, I = lMHz

2-45

•

SWITCHING TIME DEFINITIONS (TRANSPARENT MODE)

ADDRESSES _ _ _ _ _.r
-i ~ 1.5V

OUTPUTS

____-+ __- J
TAA

VIH

CE1

,..---VIH

VIL

CE2

.....- - - V I L

OUTPUTS

T.S.

VOH

VOL

NOTE: Strobe input must remain high throughout read cycle while in transparent mode.

SWITCHING TIME DEFINITIONS (LATCHED MODE)

ADORESS____

---------------~I~--------VIH
1.5V

J(1.5V

VIL

~TCDS--~·I-·--TADH~

+-__--, I~:----_;_----------..
CHIP ENAB~:2_---+II---.JX 1.5V
I
*-1 ~.5V
r--TSW-++I·~--TCOH---~.-t....-TCD--1
CE1 _ _ _ _

~~.1

STROBE----!I.:::::::1-:-:.J:..
_____

""""'

'-1_.5_V_ _ _ _ _ _. .V

A.C. TEST LOAD

PROM OUTPUT Ox o--~~--"'--.--

: '--___:.>-_J

I
I

~ TEA

r-- ---[

TEA

T.S.

;

A.C. TEST LOAD

PROM
OUTPUT

Ox o---t---.-O TEST POINT
30pF*

• Includes Jig

and Probe Total
Capacitance

•

2-49

HARRIS
SEMICONDUCTOR
PRODUCTS DIVISION

HM-7608

A DIVISION OF HARRIS CORPORATION

Features

8 PROM

Pinouts

•

10nl MAXIMUM ADDRESS ACCESS TIME

•

"THREE STATE" OUTPUTS WITH A CHIP ENABLE INPUT

•

SIMPLE, HIGH SPEED PROGRAMMING PROCEDURE - ONE PULSEI
BIT. ASSURES FAST PROGRAMMING AND SUPERIOR RELIABILITY.

•

FAST ACCESS TIME - GUARANTEED FOR WORST CASE N2 SEQUENCING OVER COMMERCIAL AND MILITARY TEMPERATURE AND VOLTAGE RANGES.

•

INDUSTRY'S HIGHEST PROGRAMMING YIELD

'N.I.C:
N.I.C:

•

PIN COMPATIBLE WITH THE 2108 WITH:
ONLY ONE 5 VOLT SUPPLY

TOPVIEW- DIP

vee
A8

08
0,
08

SUPERIOR ACCESS TIME

FASTER PROGRAMMING TIME

Description
The HM-760B is a fully decoded high speed Schottky TTL B192-Bit
Field Programmable ROM in a 1 K word by B bit/word format and is
available in a 24 pin D.I.P. (ceramic or Elpoxy) and a 24 pin flat pack.
All bits are manufactured storing a logical" 1" (Positive Logic) and can be
selectively programmed for a logical "0" in any bit position, the HM-760B
has "Three State" outputs.

•

Nickel-chromium fuse technology is used on this and all other Harris
Bipolar PROMs.
The HM-760B contains test rows and columns which are in addition to the
storage array to assure high programmability and guarantee parametric
and A.C. performance. The fuses in these test rows and columns are
blown prior to shipment.

TOP VIEW - FLATPACK

A7===1r'rr===vcc
A6

NJ~

A2
A,

02
03

06
05
04

GNO
PIN NAMES
AO-Ag

0, -08

There is a chip enable input on the HM-760B where CE low enables
the device.

Functional Diagram

N.I.C:
N.I.C:

AO
0,

This PROM is a plug in replacement for the 270B where the VSS pin on
the 270B becomes GND on the HM-760B. The VBB, VDD, and program
pins on the 270B are all N.C. on the HM-760B.

Address Inputs
Data Outputs
Chip Enable Input

·No Internal Connect

logic Symbol

8192
MEMORY ARRAY

NOTE: PHYSICAL BIT POSITIONS
FOR COLUMNS ARE AS FOLLOWS:

0,.03. 05. 07_{O __1SI
°2.04. OS. as ...-.(15, 0-14)

CE
AO

A,
A2
A3
A4

A.
A3

128 TRANSIMISSION GATES

AS
A7

A,
AD

( ) = Pin Numbers

(24): VCC

(12) = GND
(21) = N.1.C.
(19) = N.I.C.
(1S) = N.1.C.

2-50

•

0,
°2
03
°4
°5

Os
°7

Specifications HM·7608
ABSOLUTE MAXIMUM RATINGS
Output or Supply Voltage (Operating)

-0.3 to +7.0V

Address/Enable Input Voltage

Storage Temperature

5.5V

Operating Temperature (Ambient)

Address/Enable Input Current

-20mA

Output Sink Current

100mA

Maximum Junction Temperature

-65 0 C to +1500 C
-55 0 e to +125 0 e
+175 0 C

CAUTION: Stresses above those listed under the "Absolute Maximum Ratings may cause permanent damage to the device, This is a
stress onlv rating and functional operation of the device at these or at any other conditions above those indicated in the operational
N

sections of this specification is not implied. (While programming, follow the programming specifications.)

HM-7608-5 (VCC = 5.0V i5%, TA = OoC to +75 0 C)
HM-7608-2 (Vce = 5.0V ±1O%, TA = -550 C to +125 0 C)
Typical measu;ements are at T A = 250 e, Vce = +5V

D.C. ELECTRICAL CHARACTERISTICS (Operating)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

IIH
IlL

Address/enable

"1"
"0"

Input Current

-50.0

+40
-100

Il A
Il A

VIH
Vil

I nput Threshold
Voltage

"1"
"0"

2.0

1.5
1.5

0.8

V
V

VOH
VOL

Output
Voltage

"1"
"0"

2.4
-

3.2
0.35

0.5

V
V

10HE
10lE

Output Disable
Current

"1"
"0"

+40
-40

Il A
Il A

Vel

Input Clamp Voltage

-1.2

lOS

Output Short Circuit
Current

-15

-25

-100

Power Supply Current

ICC

TEST CONDITIONS
VIH = Vce Max.
Vil = 0.45V

= Vee Min.
= Vee Max.
10H = -2.0mA, Vee = Vee Min.
10l = +16mA, Vce = Vee Min.
VOH, Vee = Vee Max.
VOL = 0.3V, Vee = Vee Max.
liN = -18mA
VOUT = O.OV
Vee
Vee

One Output Only for a Max.
of 1 Second
130

170

Vee = Vee Max. All Inputs
Grounded

NOTE: Positive current defined as into device terminals.

A.C. ELECTRICAL CHARACTERISTICS (Operating)

HM-7608-5

HM-7608-2
5V ±10%
-550C to + 1250C

5V.±5%

ooe to + 75 0 e
PARAMETER

SYMBOL

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

TAA

Address Access Time

TEA

Chip Enable Access Time

A.C. limits guaranteed for worst case N2 sequencing with maximum test frequency of 5MHz.

CAPACITANCE: T A

SYMBOL
eINA,e'NeE
eOUT

= 25 0 C

(NOTE: Sampled and guaranteed - but not 100% tested.!

PARAMETER

MAXIMUM

UNITS

Input Capacitance

Vee

Output Capacitance

Vee

2-51

TEST CONDITIONS

= 5V, VIN = 2.0V, f = lMHz
= 5V, VOUT = 2.0V, f = lMHz

SWITCHING TIME DEFINITIONS
CE, _ _"",""
CHIP ENABLE

~----""",I_-------VIH

ADDRESSES

-i ~1.5V

-----./

OUTPUTS

Ir-:::-:----VIH
1.5V

p.-----./-r------ VIL

VIL

,....---VOH

-----+-_./
TAA

OUTPUTS----f--1<======t===)

'0<

A.C. TEST LOAD

PROM
OUTPUT

Ox o--~,--"",~O TEST POINT
30pF*

* Includes Jig
and Probe Total

Capacitance

2-52

T.S.

HARRIS

HM-7680/81

SEMICONDUCTOR
PRODUCTS DIVISION

1K x 8 PROM

A DIVISION OF HARRIS CORPORATION

HM-7680 - Open Collector Outputs
HM-7681 - "Three State" Outputs

Pinouts

Features
•

70ns MAXIMUM ADDRESS ACCESS TIME

•

"THREE STATE" OR OPEN COLLECTOR OUTPUTS AND FOUR CHIP
ENABLE INPUTS

•

SIMPLE HIGH SPEED PROGRAMMING PROCEDURE ONE PULSE/BIT.
ASSURES FAST PROGRAMMING AND SUPERIOR RELIABILITY.

•

TOP VIEW-DIP

FAST ACCESS TIME - GUARANTEED FOR WORST CASE N2 SEQUENCING OVER COMMERCIAL AND MILITARY TEMPERATURE AND VOLTAGE RANGES.
INDUSTRY'S HIGHEST PROGRAMMING YIELD

Description
The HM-7680/81 is a fully decoded high speed Schottky TTL 8192/Bit
Field Programmable ROM in a 1 K word by 8 bit/word format with open
collector (HM-7680) or "Three State" (HM-7681) outputs.
These
PROM's are available in a 24 pin D.I.P. (ceramic or epoxy) and a 24 pin
flat pack.
All bits are manufactured storing a logical "1" (Positive Logic) and can be
selectively programmed for a logical "0" in anyone bit position.
Nickel-chromium fuse technology is used on this and all other Harris
Bipolar PROMs.
The HM-7680/81 contains test rows and columns which are in addition
to the storage array to assure high programmability and guarantee parametric and A.C. performance. The fuses in these test rows and columns
are blown prior to shipment.
There are four chip enable inputs on the HM-7680/81. CE1, CE2 low,
and CE3, CE4 high enables the chip.

Functional Diagram
63r------------------------,

1 OF 64
ROW
DECODE

NOTE: PHYSICAL BIT POSITiONS
FOR COLUMNS ARE AS FOLLOWS:
0,.0,,05. 0 7-(0-151
°2.°4. <>e. 08_115.0_14)

8192 BIT
MEMORY
ARRAY

Vcc
AS

CEI

IT2

CE3

CE4

GND

TOP VIEW - FLATPACK
AS
A7
AS
A4
A3
A2
AI
AO
01
02
03
GND

AS
~~~~~JJ~~~~ VCC
Ag
ITI
CE2
CE3
CE4

Os
~

Os
Os
04

PIN NAMES
AO - A9 Address Inputs
01 - 08 Data Outputs
GE1, CE2, CE3, CE4 Chip Enable Inputs

Logic Symbol

AS
Ag

12S TRANSMISSION GATES

1 OF 16
COLUMN
DECODE

(

) = Pin Numbers

(24) = Vee
(12)= GND

•

Specifications HM-7680/81
ABSOLUTE MAXIMUM RATINGS
Output or Supply Voltage (Operating)

-0.3 to +7 .av

Address/Enable Input Voltage

Storage Temperature
Operating Temperature (Ambient)

5.5V

Address/Enable Input Current

-20mA

Output Sink Current

100mA

Maximum Junction Temperature

-65 0 C to +150 o C
-55 0 C to +125 0 C
+1750 C

D.C. ELECTRICAL CHARACTERISTICS (Operating)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

-SO.O

+40
-2S0

J..LA
J..LA

VIH = VCC Max.
Vil = O.4SV

1.S
l.S

0.8

V
V

Vec = Vec Min.
Vec = Vec Max.

3.2"
0.3S

O.SO

V
V

IOH = -2.0mA, Vee = Vee Min.
IOl = +16mA, VCC = Vce Min.

+40
-40'

J..LA
J..LA

IIH
IlL

Addresslenable
Input Current

"1"
"0"

VIH
Vil

Input Threshold
Voltage

"1"
"0"

2.0

VOH
VOL

Output
Voltage

"1"
"0"

2.4 •
-

10HE
10lE

Output Disable

"1"
"0"

Current

HM-7680/81-5 (VCC = 5.0V :!5%, TA = aoc to +75 0 C)
HM-7680/81-2 (VCC = 5.0V ±10%, TA = -55 0 C to +125 0 C)
Typical measurements are at T A = 25 0 C, VCC = +5V

TEST CONDITIONS

VOH, Vce = VCC Max.
Val = 0.3V, vcc = VCC Max.

VCl

Input Clamp Voltage

-1.2

105

Output Short Circuit
Current

-lS"

-100"

VOUT = O.OV
One Output Only for a Max.
of 1 Second

ICC

Power Supply Current

130

170

VCC = VCC Max. All Inputs
Grounded

liN = -18mA

NOTE: Positive current defined as into device terminals.

* "Three State" only

A.C. ELECTRICAL CHARACTERISTICS (Operating)

HM-7680/81-S
SV±S%
ooe to + 750C
PARAMETER

SYMBOL

MIN

TYP

HM-7680/81-2
sv ±10%
-550C to + 1250C
MAX

MIN

TYP

MAX

UNITS

TAA

Address Access Time

TEA

Chip Enable Access Time

A.C. limits guaranteed for worst case N2 sequencing with maximum test frequency of 5MHz.

CAPACITANCE: T A = 25 0 C (NOTE: Sampled and guaranteed - but not 100% tested'!

SYMBOL

PARAMETER

MAXIMUM

UNITS

TEST CONDITIONS

elNA, CINCE

I nput Capacitance

VCC = 5V, VIN = 2.0V, f = lMHz

COUT

Output Capacitance

VCC=5V,VOUT=2.0V,f=

2-54

lMH~

SWITCHING TIME DEFINITIONS

- - - - - " I .....- - - - - - - - v I H
ADDRESSES _ _ _ _ _ _./7 ~1.5V
VIL

CE1. CE2 _ _--,. ~-----,. , - - - - VIH
CHIP ENABLES
1.5V
V
CE38 r;==== vcc
AS
Ag
~,

CE2
CE3

A1
AO

0,
02

GNO

STR
~

PIN NAMES

AO - A9
08
GEL GE2. CE3
STR

a' -

Address Inputs
Data Outputs
Chip Enable Inputs
Strobe

logic Symbol

Functional Diagram
NOTE: Pl"lysical bit positions
for columns are as follows:

°°2,04.°6.
1.°3.°5.°7-(0-15)
08-I1S, 0_14)

.1N8JT
MEMORV
ARRAY

...................
(

) = Pin Numbers

(24) '" Vee
(12) = GND

2-59

•

Specifications HM-7680R/81R
ABSOLUTE MAXIMUM RATINGS
Output or Supply Voltage (Operating) -0.3 to +7.0V

Storage Temperature

Address/Enable Input Voltage

Operating Temperature (Ambient)

5.5V

Address/Enable Input Current

-20mA

Output Sink Current

100mA

Maximum Junction Temperature

-650 C to + 1500 C
-55 0 C to +1250C
+1750 C

D.C. ELECTRICAL CHARACTERISTICS (Operating)

HM-7680R/81 R-5 (Vec = 5.0V :!s%, TA = DoC to +75 0 C)
HM-7680R/81 R-2 (Vec 5.0V :r10%, T A
-55 0 C to +125 0 C)
Typical measurements are at T A = 25 0 C, Vce = +5V

SYMBOL

•

PARAMETER

"TYP

MIN

IIH
IlL

AddressfEnable
I nput Current

'I"
"0"

VIH
VIL

Input Threshold
Voltage

VOH
VOL
10HE
10LE

MAX

UNITS

+40

JJ.A
JJ.A

VIH = VCC Max.
VIL= 0.45V

V
V

VCC = VCC Min.
VCC = VCC Max.
10H = -2.OmA, VCC = VCC Min.
10L= +16mA, VCC = VCC Min.

-50.0

-250

"I"
"0"

2.0

1.5
1.5

0.8

Output
Voltage

"I"
"0"

2.4*

3.2"
0.35

0.50

V
V

Output Disable
Current

"I"
"0"

+40
-40"

JJ.A
JJ.A

TEST CONDITIONS

VOH, VCC - VCC Max.
VOL = 0.3V, VCC = VCC Max.

VCL

I nput Clamp Voltage

-1.2

lOS

Output Short Circuit
Current

-"5'

-25

-100'

VOUT- O.OV
One Output Only for a Max.
of 1 Second

ICC

Power Supply Current

130

170

VCC = VCC Max. All Inputs
Grounded

liN - -18mA

NOTE: Positive current defined as into device terminals.
'''Three State" only

A.C. ELECTRICAL CHARACTERISTICS (Operating)

HM-7680Rf81R-5
5V±5%
OOC to+75OC

HM-7680Rf81 R-2
5V±10%
-55OC to +125oC

SYMBOL

PARAMETER

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

TAA
TEA

Address Access Time
Chip Enable Access Time

45
30

70
40

90
50

ns
ns

Latched or
Transparent

TADH
TCDH
TSW
TSL
TDL
TCDS

Address Hold Time
Chip Enable Hold Time
Strobe Pulse Width
Strobe Latch Time
Strobe Delatch Time
Chip Enable Set-Up Time

0
10
30
70

-10
0
10
40

ns
ns
ns
ns
ns
ns

Latched Only

0
10
40
90

TEST CONDIT.

A.C. limits guaranteed for worst case N2 sequencing with maximum test frequency of 5MHz.

CAPACITANCE: T A = 250 e

SYMBOL

(NOTE: Sampled and guaranteed - but not 100% tested.1

MAXIMUM

UNITS

TEST CONDITIONS

CINA,CINCE

Input Capacitance

PARAMETER

VCC = 5V, VIN = 2.0V, f = IMHz

COUT

Output Capacitance

VCC = 5V, VOUT = 2.0V, f = lMHz

2-60

SWITCHING TIME DEFINITIONS (Transparent M~del

VIH

---_./

-i ~1.5V

AIHHNSSES

OUTPUTS

1.5V

VIL

-----t---./
TAA

VOH

I~V

VIL

T.S.

OUTPUTS

VOL

VIH

TEA

NOTE: Strobe Input must remain high throughoul read cycle while in transparent mode.

SWITCHING TIME DEFINITIONS (Latched Model

ADDRESSES ~ 1(,.5V

~ i{1.5V

--/

I---TCDS
CE,. CE2
CHIP ENAB LES
CE3

TADH-

1.5V~1(

~1.5V

r-TSW
1.5V

STROBE

TCD--

TCDH

------.
",,,1.5V

1.5V

TSL

;1( 1.SV

OUTPUTS

TAA

A.C. TEST LOAD

PROM
OUTPUT

.....--o TEST POINT

oxo--~~-

600n

30pF*

* Includes

Jig

and Probe Total
Capacitance

2-61

1.5

TDL
......

t-T.S.

•

HARRIS

HM-7680P/81P

SEMICONOUCTOR
PRODUCTS DIVISION

POWER DOWN 1K x 8 PROM

A DIVISION OF HARRIS CORPORATION

HM-7680P - Open Collector Outputs
HM-7681P - "Three State" Outputs

Preliminary
Features

Pinouts

•

70nsMAXIMUM ADDRESS ACCESS TIME

•

"THREE STATE" OR OPEN COLLECTOR OUTPUTS AND FOUR POWER
DOWN INPUTS.

•

SIMPLE HIGH SPEED PROGRAMMING PROCEDURE - ONE PULSE/BIT.
ASSURES FAST PROGRAMMING AND SUPERIOR RELIABILITY.

•

FAST ACCESS TIME - FOR WORST CASE N2 SEQUENCING OVER COMMERCIAL AND MILITARY TEMPERATURE VOLTAGE RANGES.
INDUSTRY'S HIGHEST PROGRAMMING YIELD.

Description
The HM-7680P/81 P is a fully decoded high speed Schottky TTL 8192Bit Field Programmable ROM in a 1 K word by 8 bit/word format with
open collector (HM-7680P) or "three state" (HM-7681P) outputs. These
PROM's are available in a 24 pin D.I.P. (ceramic or epoxy) and a 24 pin
flatpack.
All bits are manufactured storing a logical "1" (positive logic) and can be
selectively programmed for a logical "0" in any bit position.
Nickel-chromium fuse technology is used on this and all other Harris
Bipolar PROMs.

•

TOP VIEW - DIP

VCC

AS
Ag

A5
A4

PO,

PD2

l'D3

j5Jj4

GND

TOP VIEW-FLATPACK

The HM-7680P/81P contains test rows and columns which are in addition
to the storage array to assure high programmability and guarantee parametric and A.C. performance. The fuses in these test rows and columns
are blown prior to shipment .
There are four power down inputs on the HM-7680P/81 P which are
similar to chip enables. The chip is enabled or disabled using the power
down inputs where a disabled chip dissipates 30% of nominal power and
the outputs go to a high impedance state. The chip is powered up (enabled) when PDl and PD2 are low and PD3 and PD4 are high.

Functional Diagram
PIN NAMES
AO - Ag Address Inputs
0, - Os Address Outputs
PO,. PD2. PD3. PD 4 Power Down Input.

8192 BIT

MEMORY
ARRAY

( I· Pin Numbers
(24)' Vee
(12)"GND
NOTE: PhVlicaI Bit Positions
For Column. At. As Follows:

0,.03,. 0S. 07 -0 -15
°2. 0 4-°6.0&-15,0-14

128 TRANSMISSION GATES

2-62

Logic Symbol

Specifications 76SDP/SIP
ABSOLUTE MAXIMUM RATINGS

Output or Supply Voltage (Operating)

-0.3 to +7.0V

Address/Enable I nput Voltage

Storage Temperature
Operating Temperature (Ambient)

5.5V

Address/Enable Input Current

-20mA

Output Sink Current

100mA

-65 0 C to +150 0 C
-550C to +125 0 C

+ 1750 C

Maximum Junction Temperature

D.C. ELECTRICAL CHARACTERISTICS (Operating)

HM-7680P/81P-5 (VCC; 5.0V

± 5%, TA = ooC to +750 C)

HM-7680P/81P-2 (VCC; 5.0V

± 10%, TA; -55 0 C to +125 0 C)

Typical measurements are at T A; 25 0 C, VCC; +5V

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

-50.0

+40
-250

JJA
JJA

1.5
1.5

0.8

V
V

3.2"
0.35

0.50

V
V

+40
-40"

JJA
JJA

IIH
IlL

Address/Enable
Input Current

"1"
"0"

VIH
VIL

Input Threshold
Voltage

"1"
"0"

2.0

VOH
VOL

Output
Voltage

"I"
"0"

2.4"

10HE
IOLE

Output Disable
Current

"I"
"0"

VeL

Input Clamp Voltage

lOS

Output Short Circuit
Current

ICC

Power SupplV Current

ICCPD

Power SupplV Current
au ring Power Down

TEST CONOITIONS
VIH = Vee Max.
VIL = 0.45V

= vee Min.
= Vee Max.
10H = -2.0mA, Vee = Vee Min.
10L = +16mA, Vce =Vee Min.
VOH, Vec = VCC Max.
VOL =0.3V, Vec = Vee Max.
Vee
Vee

-1.2

-100"

VOUT = O.OV, One Output at a
Time for a Max. of 1 Second

130

170

Vee = Vec Max., All Inputs
Grounded.

Vec = Vee Max., All Inputs
Grounded.

-IS"

liN = -18mA

NOTE: Positive current defined as into device terminals.
'''Three State" on IV

A.C. ELECTRICAL CHARACTERISTICS (Operating)

HM-7680P/81P-S
SV±S%
OOC to +7s oe
SYMBOL
TAA
TpD
TpU

PARAMETER

Address Access Time
Chip Power-Down
Access Time
Chip Power-Up Access Time

HM-7680P/81P-2
SV±10%
-S50C to + 12SoC

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

100

150

200

A.C. limits guaranteed for worst case N2 sequencing with maximum test frequency of 5MHz.
CAPACITANCE: T A = 25 0 C (NOTE: Sampled and guaranteed - but not 100% tested.)

SYMBOL
CINA, CINCE
eOUT

MAXIMUM

UNITS

Input Capacitance

PARAMETER

Output Capacitance

2-63

TEST CONDITIONS

= 5V, VIN =2.0V, f = 1MHz
Vee = 5V, VOUT =2.0V. f = 1MHz
Vec

•

SWITCHING TIME DEFINITIONS

---

PO,. PDa
- - , - - - -... I ...- - - - - - - - V I H
VIL

...----VIH

POWER DOWNS

ADDRESSES_~_ _-./-:: ~'.'v

'----VIL

jij)3. PD4

/'""_ _ _ VOH

+-__./

OUTPUTS_ _ _ _ _

TAA

'·5V

VOL

OUTPUTS---T--t'-_ _-L_~

A.C. TEST LOAD

PROM
OUTPUT

Ox o--~~-_-o TEST POINT

30pF*
-'ncludes Jig
and Probe Total
Capacitance

•

2-64

T.S.

HARRIS

HM-7680RP/81RP

SEMICONDUCTOR
PRODUCTS DIVISION

POWER DOWN 1K x 8 PROM

A DIVISION OF HARRIS CORPORATION

Preliminary

HM-7680RP - Open Collector Outputs
HM-7681RP - "Three State" Outputs

Features

Pinouts

•
•

70n5 MAXIMUM ADDRESS ACCESS TIME.
"THREE STATE" OR OPEN COLLECTOR OUTPUTS AND TWO CHIP ENABLE
INPUTS.

TOP VIEW-DIP

•

SIMPLE HIGH SPEED PROGRAMMING PROCEDURE - ONE PULSE/BIT. ASSURES
FAST PROGRAMMING AND SUPERIOR RELIABILITY.

VCC

•

FAST ACCESS TIME - GUARANTEED FOR WORST CASE N2 SEQUENCING OVER
COMMERCIAL AND MILITARY TEMPERATURE AND VOLTAGE RANGES.

A6
AS

•

INDUSTRY'S HIGHEST PROGRAMMING YIELD.

eE,

•
•

LATCHED OUTPUTS.
A POWER DOWN INPUT ALLOWING 70% REDUCTION IN NOMINAL POWER DISSIPATION.

A2
A,

Description
The HM-7680RP/81 RP are fully decoded high speed Schottky TTL 8192-8it
Field Programmable ROMs in a 1 K words by 8 bit/word format with open collector
(HM-7680RP) or "Three State" (HM-7681 RP) outputs. These PROMs are available in a 24 pin DIP (ceramic or epoxy) and a 24 pin flatpack.
All bits are manufactured storing a logical "1" (positive logic) and can be selectively
programmed for a logical "0" in any bit position.
Nickel-chromium fuse technology is used on these and all other Harris Bipolar
PROMs.
The HM-7680RP/81 RP contains test rows and columns which are in addition to
the storage array to assure high programmability and guarantee parametrics and
A.C. performance. The fuses in these test rows and columns are blown prior to
shipment.

CE2

PO
STR

0,
02
03

°7
Os
Os

GNO

°4

TOP VIEW-FLATPACK

There are two chip enable inputs on the HM-7680RP/81 RP. CEt and CE2 low
enables the device.
There is also a power down input on this device. A powered down device has 70%
reduction in nominal power dissipation if the outputs are not latched and 50% reduction in nominal power if the outputs are latched.
The HM-7680RP/81 RP is operated in the Transparent Read Mode by holding the
the strobe input high and the PD input high throughout the read operation. This is
the normal read mode where the two chip enables and the power down inputs will
control the outputs.
In Latched Read Mode, bringing the strobe input low will latch the outputs and
the chip enable inputs. However, the power down input is independent of the latch
function and can be changed while in the latched mode. If the device is disabled
when the strobe input goes low, the outputs will be latched in the high impedance
state. If the device is in the latched mode, the strobe input must be brought high to
allow the outputs to respond to new address or chip enable conditions.
The following is a summary of the functional dependencies of the operating modes:
1.

Chip enabled, transparent, powered up - normal mode where the power down
input is effectively a chip enable with the ICC reduction function.

Chip enabled, latched, power up - this is normal latched mode where the outputs remain latched regardless of address and chip enable switching.

Chip enabled, latched, power down - this is the powered down latched mode
where the output data remains latched while power is reduced to 50% of its
nominal value. If the latch strobe changes state while in this mode, the outputs
will go to a high impedance state and power will reduce to 30% of nominal
power. This is because the PD input becomes an effective chip enable in the
Transparent Mode.

Chip disabled, transparent, power down - this is the normal powered down
mode where the outputs are in a high impedance state and the power is reduced to 30% of the nominal power.

On the following page is a table to clarify the operational interdependencies.

2-65

PIN NAMES
AO-A9 Address Inputs

0,-08 Data Outputs
CE"

CE2

Chip Enable Inputs

Power Down Input

STR Strobe Input

logic Symbol

TRUTH TABLE for HM-7680RP/81RP

STR

CE2

CE1

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

OUTPUTS

ICC

Latched Data
Latched "Th ree State"
Latched "Three State"
Latched :'Three State"
Unlatched "Three State"
Unlatched "Three State"
. Unlatched "Three State"
Unlatched "Three State"
Latched Data
Latched "Three State"
Latched "Three State"
Latched "Three State"
Unlatched Data
Unlatched "Three State"
Unlatched "Three State"
Unlatched "Three State"

85m A
85mA
85mA
85mA
SOmA
SOmA
SOmA
SOmA
170mA
170mA
170mA
170mA
170mA
170mA
170mA
170mA

Assume that the sequence of transitions is: 1) Chip Enables, 2) STR, 3)
and the initial state is Unlatched Data ..

Functional Diagram

•

8192 BIT
MEMORY
ARRAY

•
•
•
A9

NOTE: Phy.ical Bit Position.
for Column. ar. a. Follows:
01.03.05.07- 0-15
02.04. Os. 08-15.0-14

••

•

•••
128 TRANSMISSION GATES

OUTPUT BUFFERS

2-66

Specifications HM-7680RP181RP
ABSOLUTE MAXIMUM RATINGS
-650 C to +150 0 C
Storage Temperature
Operating Temperature (Ambient) -55 0C to +1250C
Maximum Junction Temperature
+1750 C

Output or Supply Voltage (Operating) -0.3 to +7.0V
Address/Enable Input Voltage
5.5V
-20mA
Address/Enable Input Current
Output Sink Current
100mA

D.C. ELECTRICAL CHARACTERISTICS

HM-7680RP/81 RP-5 (VCC ~ 5.0V ± 5%, TA ~ ooC to +75 0 C)
HM-7680RP/81 RP-2 (VCC ~ 5.0V ± 10%, T A ~ -55 0 C to +125 0 C)
Typical meaSUrtlments are at T A ~ 25 0 C, VCC ~ +5V

(Operating)

PARAMETER

MIN

TYP

MAX

UNITS

Input Current

"1"
"0"

-50.0

+40
-250

J1A
J1A

Input Threshold
Voltage

"1"
"0"

2.0

1.5
1.5

0.8

V
V

VCC
VCC

VOH
VOL

Output
Voltage

"1"
"0"

2.4*
-

3.2*
0.3S

0.50

V
V

10H = -2.0mA, VCC = VCC Min.
10l = +16mA, VCC = VCC Min.

10HE
10lE

Output Disable
Current

"1"
"0"

+40
-40*

J1A
J1A

SYMBOL
IIH
IlL

Address/Enable

VIH
Vil

TEST CONDITIONS
VIH = VCC Max.
Vll=0.45V

= VCC Min.
= VCC Max.

VOH, VCC = VCC Max,
VOL = 0.3V, VCC = VCC Max.

VCl

Input Clamp Voltage

-1.2

lOS

Output Short Circuit
Current

-lS*

-2.S

-100*

VOUT =O.OV, One Output at a
Time lor a Max. 01 1 Second

ICC

Power Supply Current

120

170

VCC = VCC Max .. All Inputs
Grounded.

ICCPD

Power Supply Current
During Power Down

VCC = VCC Max., All Inputs
Grounded.

ICClPD

Power Supply Current
During Latched Power
Down

VCC = VCC Max., All Inputs
Grounded.

liN = -18mA

NOTE: Positive current defined as into device terminals.
* "Three State" only

A.C. ELECTRICAL CHARACTERISTICS (Operating)
HM-7680RP/81 RP-5
SV'± 5%
aoc to +75 0 C

HM-7680RP/81 RP-2
5V'± 10%
-550C to + 1250C

SYMBOL

PARAMETER

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

TAA
TDA
TEA
TpU

Add ress Access Time
Chip Disable Access Time
Chip Enable Access Time
Chip Power-Up Access Time

SO
30
30
100

70
40
40
150

90
50
50
200

ns
ns
ns
ns

Latched or
Transparent

ns
ns
ns
ns
ns
ns

Latched Only

TADH
TCDH
TSW
TSL
TDL
TCDS

Address Hold Time
Chip Enable Hold Time
Strobe Pulse Width
Strobe Latch Time
Strobe Delatch Time
Chip Enable Set-Up Time

0
10
30
70

-10

10
40

10
40
90

-10
0
10
40

TESTCOND.

A.C. limits guaranteed for worst case N2 sequencing with maximum test frequency of 5MHz.

CAPACITANCE: T A
SYMBOL
CINA, CINCE
COUT

25 0 C (NOTE: Sampled and guaranteed - but not 100% tested.)
MAXIMUM

UNITS

Input Capacitance

VCC = 5V, VIN = 2.0V, I

Output Capacitance

VCC

PARAMETER

2-67

TEST CONDITIONS

= SV,

= 1MHz

VOUT = 2.0V, I = lMHz

•

SWITCHING TIME DEFINITIONS (Transparent Model

VIH

- - - , - - - - " I . r - - - - - - - - VIH
ADDRESSES _ _ _ _ _/-; ~1.5V
VIL

1.5V
VIL

_---VOH
OUTPUTS

OUTPUTS

------+----'

VOL

----+---1(.

'---+-../

TEA. TpU

TAA

TDA

NOTE: Strobe input must remain high throughout read cycle while in transparent mode.

SWITCHING TIME DEFINITIONS (Latched Model

ADDRESS ~

----

--, 1.5V

1.5V

---------

TADH-

-TCDS
CE1.CE2

..,

CHIP ENA BLES

1.5V

jifj

r-TSW
1.5V

STROBE

•

------

1.5V

TSL
OUTPUTS

K.1.5V

---.

TDL

......
./

TAA

A.C. TEST LOAD

PROM
OUTPUT

TCD--

TCDH

0xo---.....--.-o TEST POINT
600n

30pF*

* I neludes Jig
and Probe Total
Capacitance

2-68

1.5

T.S.

HM-7684/85

HARRIS

2K x 4 PROM

SEMICONDUCTOR
PRODUCTS DIVISION
A DIVISION OF HARRIS CORPORATION

HM-7684 - Open Collector Outputs
HM-7685 - "Three State" Outputs

Features

Pinouts

•

70nsMAXIMUM ADDRESS ACCESS TIME

•

"THREE STATE" OR OPEN COLLECTOR OUTPUTS AND A CHIP ENABLE
INPUT
A6

•

SIMPLE HIGH SPEED PROGRAMMING PROCEDURE - ONE PULSE/BIT
ASSURES FAST PROGRAMMING AND SUPERIOR RELIABILITY

VCC

FAST ACCESS TIME - GUARANTEED FOR WORST CASE N2 SEQUENCING OVER COMMERCIAL AND MILITARY TEMPERATURE AND VOLTAGE RANGES

•

TOP VIEW - DIP

INDUSTRY'S HIGHEST PROGRAMMING YIELD

Description
The HM-7684/85 are a fully decoded high speed Schottky TTL 8192Bit Field Programmable ROM in a 2K word by a 4 bit/word format with
open collector (HM-7684) or "Three State" (HM-7685) outputs. These
PROMs are available in an 18 pin DIP (ceramic or epoxy) and an 18 pin
flatpack.
All bits are manufactured storing a logical "1 "(positive logic) and can be
selectively programmed for a logical "0" in any bit position.

04
CE

GND

TOP VIEW - FLATPACK

Nickel-chromium fuse technology is used on this and all other Harris
Bipolar PROMs.

•

The HM-7684/85 contains test rows and columns which are in addition
to the storage array to assure high programmability and guarantee parametrics and A.C. performance. The fuses in these test rows and columns
are blown prior to shipment.
There is a chip enable on the HM-7684/85.

CE low enables the chip.
PIN NAMES

Functional Diagram

AO - A 10 Address Inputs
01 - 04 Data Outputs
CE Chip Enable Input

AS
8192 BIT

MEMORY
ARRAY

logic Symbol

( I '" Pin Numben
(18) = Vee

(9)

GND

128 TRANSMISSION GATES

2-69

Specifications HM-7684/85
ABSOLUTE MAXIMUM RATINGS

Output or Supply Voltage (Operating)

Storage Temperature

-0.3 to +7.0V

Address/Enable Input Voltage

Operating Temperature (Ambient)

5.5V

Address/Enable Input Current

-20mA

Output Si nk Current

100mA

Maximum Junction Temperature

-65 0 C to +150 0 C
-55 0 C to +125 0 C
+175 0 C

CAUTION: Stresses above those listed under the "Absolute Maximum RatingsO may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational
sections of this specification is not implied. (While programming, follow the programming specifications.)

D.C. ELECTRICAL CHARACTERISTICS (Operating)

HM-7684/85-5 (VCC = 5.0V
HM-7684/85-2 (VCC = 5.0V

± 5%, T A = ooC to +75 0 C)
± 10%, TA = -55 0 C to +125 0 C)

Typical measurements are at T A = 250 C, VCC = +5V

SYMBOL

PARAMETER

MIN

TYP

MAX

UNITS

IIH
IlL

Address/Enable "1"
I nput Current
"0"

-50.0

+40
-250

JiA
JiA

VIH
VIL

Input Threshold "1"
Voltage
"0"

2.0
-

1.5
1.5

0.8

V
V

VCC
Vee

VOH
VOL

Output
Voltage

2.4"
-

3.2*
0.35

0.50

10HE
10LE

Output Disable "1"
Current
"0"

"1"
"0"

TEST CONDITIONS

= Vce Min.
= Vee Max.
IOH = -2.0mA, Vee = Vee Min.
10L = +16mA, Vee = Vee Min.

V
V

+40
-40'

VOH, Vec = VCC Max.
VOL = 0.3V, VCC = VCC Max.

JiA
JiA

VCL

Input Clamp Voltage

-1.2

lOS

Output Short Circuit

-15*

-100*

liN

= -18mA

VOUT

Current

ICC

= VCC Max.
= 0.45V

= O.OV, One Output at a

Time for a Max. of 1 Second

Power Supply Current

170

120

VCC = VCC Max., All Inputs
Grounded.

NOTE: Positive current defined as into device terminals.
*"Three State" only

A.C. ELECTRICAL CHARACTERISTICS (Operating)

HM-7684/8S-S
SV!S%
ODC to +7SoC
PARAMETER

HM-7684/8S-2
SV! 10%
-SSoC to + 12SoC

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

TAA

Address Access Time

TEA

Chip Enable Access Time

SYMBOL

A.e. limits guaranteed for worst case N2 sequencing with maximum test frequency of 5MHz.

CAPACITANCE: T A = 250 C

SYMBOL
CINA, CINCE
COUT

(NOTE: Sampled and guaranteed - but not 100% tested,)

MAXIMUM

UNITS

Input Capacitance

PARAMETER

Vce

= 5V,

Output Capacitance

VCC

= 5V, VOUT = 2.0V, f = 1MHz

2-70

TEST CONDITIONS
VIN

= 2.0V, f = 1MHz

SWITCHING TIME DEFINITIONS

Ce
ADDRESSES

VIH

--: ~1.5V

CHIP ENABLE

VIL

OUTPUTS
TAA

VOH

OUTPUTS

_---VIH
1.5V
............... VIL

T.S.

VOL

A.C. TEST LOAD

Vcc
PROM
OUTPUT

-_-0 TEST POINT

Ox 0 - - -....

600n

3OpF*

* I neludes Jig
and Probe Total

Capacitance

III

2-71

HM-7684P/85P

HARRIS
SEMICONDUCTOR
"RODUCTS DIVISION

POWER DOWN 2K x 4 PROM

A DtVISION OF HARRIS CORPORATION

HM-7684P - Open Collector Outputs
HM-7685P - "Three State" Outputs

Preliminary

Pinouts

Featur.l!.s
•

70ns'MAXIMUM ADDRESS ACCESS TIME

•

"THREE STATE" OR OPEN COLLECTOR OUTPUTS AND A POWER DOWN
INPUT

•

SIMPLE HIGH SPEED PROGRAMMING PROCEDURi: - ONE PULSE/BIT
ASSURES FAST PROGRAMMING AND SUPERIOR RI!LIABILITY

TOP VIEW - DIP
A6

Vce

•

FAST ACCESS TIME - GJARANTEED FOR WORST CASE N2 SEQUENCING OVER COMMERCIAL AND MILITARY TEMP. AND VOLT. RANGES

•

INDUSTRY'S HIGHEST PROGRAMMING YIELD

Description
The HM-7684P/85P are fully decoded high speed Schottky TTL 8192Bit Field Programmable ROMs in, a 2K words by 4 bit/word format with
open collector (HM-7684P) or "Three State" (HM-7685P) outputs. These
PROMs are available in an 18 pin DIP (ceramic or epoxy) and an 18 pin
flatpack.
All bits are manufactured .storing a logical "1" (positive logic) and can be
selectively programmed for a logical "0" in any bit position.
Nickel-chromium fuse technology is used on this and all other Harris
Bipolar PROMs.

AlO

GND

TOP VIEW - FLATPACK

The HM-7684P/85P contains test rows and columns which are in addition
to the storage array to assure high programmability and guarantee parametrics and A.C. performance. The fuses in these test rows and columns
are blown prior to shipment.
There is a power down input on the HM-7684P/85P which is similar to a
chip enable. The chip is enabled or disabled using the power down input
where a disabled' chip dissipates 30% of nominal power and the outputs go
to a high impedance state. The chip is powered up (enabled) Wh!lf\ POl
is low.

Functional Diagram
~r-------------------------;

PIN NAMES
AO - A1 0
01 - 04
PO

Address Inputs
Data Outputs
Power Down Input

8192 BIT

MEMORY
ARRAY
A6

Logic Symbol
'A5

( ) = Pin Numbers
(18) = Vee

191- GND

12B TRANSMISSION GATES

A,
AD

2-72

Specifications 7684P/85P
ABSOLUTE MAXIMUM RATINGS

Output or Supply Voltage (Operating)

-0.3 to +7.0V

Address/Enable Input Voltage

Storage Temperature

Address/Enable Input Current

-20m A

Output Sink Current

100mA

CAUTION:

Operating Temperature. (Ambient)

5.5V

Maximum Junction Temperature

-65 0 C to +150 0 C
-55 0 C to +125 0 C
+175 0 C

Stresses above those listed under the NAbsolute Maximum Ratings" may cause permanent damage to the device.

These

are stress onlv ratings and functional operation of the device at these or at any other conditions above those indicated in the operational
sections of this specification is not implied. (While programming, follow the programming specifications.)

D.C. ELECTRICAL CHARACTERISTICS (Operating)

HM-7684P/85P-5 (VCC = 5.0V
HM-7684P/85P-2 (VCC 5.0V

± 5%,

TA = ooC to +750 C)
-55 0 C to +125 0 C)

± 10%, TA =

Typical measurements are at T A = 25 0 C, VCC = +5V

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

TEST CONDITIONS

IIH
III

Address/Enable
I nput Current

"1"
"0"

-50.0

+40
-250

IJA
IJA

VIH
Vil

Input Threshold
Voltage

"1"
"0"

2.0
-

1.5
1.5

0.8

V
V

VCC
VCC

VOH
Val

Output
Voltage

"1"
"0"

2.4*
-

3.2*
0.35

0.50

IOHE
IOlE

Output Disable

"1"
"0"

Current

VCl

I nput Clamp Voltage

lOS

Output Short Circuit
Current

ICC

Power Supply Current

ICCPD

Power Supply Current

= VCC Min.
= Vce Max.
10H = -2.0mA, Vce = VCC Min.
10l = +16mA, VCC = VCC Min.

V
V

+40
-40*

= VCC Max.
= 0.45V

VOH, VCC = Vec Max.
Val = 0.3V, Vec = VCC Max.

JlA

IJA

= -18mA

-1.2

-lOa"

VOUT = O.OV, One Output at a
Time for a Max. of 1 Second

120

170

VCC = VCC Max., All Inputs
Grounded.

VCC = Vce Max., All Inputs
Grounded.

-15"

liN

During Power Down

NOTE: Positive current defined as into device terminals.

*"Three State" only

A.C. ELECTRICAL CHARACTERISTICS (Operating)

HM-7684P/85P-5
5V±5%
OOC to +750 C
SYMBOL

PARAMETER
Address Access Time
Chip Power Down
Access Time
Chip Power-Up Access Time

TAA
TpD
TpU

HM-7684P/85P-2
5V.± 10%
-550 C to + 1250 C

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

100

150

200

A.C. limits guaranteed for worst case N2 sequencing with maximum test frequency of 5MHz.

CAPACITANCE: T A

SYMBOL
CINA, CINCE
COUT

= 250 C

(NOTE: Sampled and guaranteed - but not 100% tested.l

MAXIMUM

UNITS

Input Capacitance

PARAMETER

Vec

= 5V, VIN = 2.0V, f = lMHz

Output Capacitance

Vec

2-73

TEST CONDITIONS

5V, VOUT

= 2.0V, f = lMHz

•

SWITCHING TIME DEFINITIONS

__________

____-----------VIH

AOORESSES __________,,"""' ~1.5V

OUTPUTS

-----------t-----"
TAA

PO----_
POWEROOWN

VIL

/-----VOH
15V

OUTPUTS------~----K

VO,

A.C. TEST LOAD

Vee

PROM
OUTPUT

..--_-0

Ox 0 - -.......

TEST POINT

30pF*

* Includes Jig
and Probe Total
Capacitance

•

2-74

T.S.

HARRIS

HM-7616

SEMICONDUCTOR
PRODUCTS DIVISION
A DIVISION OF HARRIS CORPORATION

Features

8 PROM

Pinout
TOP VIEW - DIP

•

80ns MAXIMUM ADDRESS ACCESS -ri;,lE

•

"THREE STATE" OUTPUTS AND A CHIP ENABLE INPUT

•

SIMPLE HIGH SPEED PROGRAMMING PROCEDURE TYPICAL

•

FAST ACCESS TIME - GUARANTEED FOR WORST CASE N2 SEQUENCING OVER COMMERCIAL AND MILITARY TEMPERATURE AND VOLTAGE RANGES

•

INDUSTRY'S HIGHEST PROGRAMMING YIELD

•

PIN COMPATIBLE WITH THE 2716

ONE PULSE/BIT

VCC

A4
CE

A1
AO
01

Description

02
03

HM-7616 is a fully decoded high speed Schottky TTL, 16,384 bit Field
Programmable ROM in a 2K word by 8 bit/word format with "Three
State" outputs. This PROM is available in a 24 pin DIP.

All bits are manufactured storing a logical "1" (Positive Logic) and can be
selectively programmed for a logical "0" in any bit position.

logic Symbol

The Nickel-chromium fuse technology used is the same as all other Harris
Bipolar PROMs and the JAN approved MIL-M-38510 PROMs.
The HM-7616 contains test rows and columns which are in addition to
the storage array to assure high programmability and guarantee parametrics and A.C. performance. The fuses in these test rows and columns
are blown prior to shipmen't.

III

There is a chip enable input on the HM-7616. CE low enables the device.

Functional Diagram
(19) (22)(23)( 1J(2) (3) (4)
A10 AgAS A7A6 As A4

128 x 64

128

1of128

MEMORY
ARRAY

x 64

ROW

MEMORY

DECODER

ARRAY

L - - -_ _..J127L,-_-,-_r--r_-,-_,.-....,._...,..---J

124) = vcc
(12) = GND
(21) = N.C,
I1S) = N.C.

2-75

Specifications HM-1616
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
-65 0e to +1500e
Operating Temperature (Ambient) -'55 0 C to +125 0 e
Maximum Junction Temperature
+175 0 e

Output or Supply Voltage (Operating) -0.3 to +7 .OV
Address/Enable Input Voltage
5.5V
Address/Enable Input Current
-20mA
Output Sink Current
100mA

D.C. ELECTRICAL CHARACTERISTICS (Operating)

HM-7616-5 (Vec = 5.0V ±5%, TA = OoC to +75 0 e)
HM-7616-2 (Vec = 5.0V ±10%, TA = -55 0 e to +125 0e)
Typical Measurements are at T A = 25 0e, Vec = +5V

SYMBOL

PARAMETER

MIN

TYP

MAX

UNITS

IIH
III

Address/Enable "1"
Input Current
"0"

-50.0

+40
-250

IJA
jlA

VIH
Vil

Input Threshold "1"
Voltage
"0"

2.0

1.5
1.5

0.8

V
V

VOH
VOL

Output
Voltage

"1"
"0"

2.4*

3.2
0.35

0.50

V
V

10HE
10LE

Output Disable
Current

"1"
"0"

+40
-40*

jlA
jlA

TEST CONDITIONS
VIH = VCC Max.
Vil = 0,45V

= VCC Min.
= VCC Max.
10H = -2.0mA, VCC = VCC Min.
10l = +16mA, VCC = VCC Min.

VCC
VCC

VOH, VCC = VCC Max.
VOL = 0.3V, VCC = VCC Max.

VCl

Input Clamp Voltage

-t.2

lOS

Output Short Circuit
Current

-15

-100

VOUT = O.OV, One Output at a
Time for a Max. of 1 Second

ICC

Power Supply Current

180

VCC = VCC Max., All Inputs
Grounded.

liN

= -18mA

NOTE: Positive current defined as into device terminals.

A.C. ELECTRICAL CHARACTERISTICS (Operating)

HM-7616-2
5V ±10%
-550C to + 1250C

HM-7616-5
5V±5%
ooc to +750C
MIN

TYP

MIN

TYP

MAX

UNITS

TAA

Address Access Time

TEA

Chip Enable Access Time

PARAMETER

SYMBOL

MAX

A.C. limits guaranteed for worst case N2 sequencing with maximum test frequency of 5MHz.

CAPACITANCE: T A = 25 0 e
SYMBOL
CINA,CINCE
COUT

(NOTE: Sampled and guaranteed - but not 100% tested.)

PARAMETER

Input Capacitance
Output Capacitance

MAXIMUM

UNITS

VCC = 5V, VIN

VCC

2-76

TEST CONDITIONS

= 5V,

= 2.0V, f = lMHz

VOUT

= 2.0V, f

= lMHz

SWITCHING TIME DEFINITIONS

,
ADDRESSES ==¥_l_.S_V_ _ _ _ _ _

~::

CE _____~2.:~ ---VIL

-j.l,!____~VOH

-I

TAA

i
I

"K,.

OUTPUTS----+!---1<-

OUTPUTS ___

~VIH

- - - - '..L....

VOL

::
I

--1 TEA f- --l
::
~

f--~

)i-' T.S.
TEA

i-~

tr,tf

< 5ns

A.C. TEST LOAD

Vce
30011

PROM
OUTPUT

Ox o---"'-~~-O TEST POINT

600n

3OpF*

• Includes jig & probe

total capacitance

•

2-77

HM-76160/161

HARRIS
SEMICONOUCTOR
PROOUCTS OIVISION

A DIVISION OF HARRIS CORPORATION

8 PROMS

HM-76161 - "Three State" Outputs
HM-76160 - Open Collector Outputs

Features

Pinout

•

BOns MAXIMUM ADDRESS ACCESS TIME

•
•

"THREE STATE" OR OPEN COLLECTOR OUTPUTS AND THREE CHIP
ENABLE INPUTS

•

SIMPLE HIGH SPEED PROGRAMMING PROCEDURE - ONE PULSE/BIT
TYPICAL

•

FAST ACCESS TIME - GUARANTEED FOR WORST CASE N2 SEQUENCING OVER COMMERCIAL AND MILITARY TEMPERATURE AND VOLTAGE RANGES

•

INDUSTRY'S HIGHEST PROGRAMMING YIELD

TOP VIEW - 0 I P
Vce

Aa
Ag
AlO
A3

CEI

CE3

CE2

Description

The HM-76160/161 are fully decoded high speed Schottky TTL 16.384
bit Field Programmable ROMs in a 2K word by 8 bit/word format with
open collector (HM-76l60) or "Three State" (HM-76161) outputs.
These PROMs are available in a 24 pin DIP.

Logic Symbol

All bits are manufactured storing a logical "1" (Positive Logic) and can be
selectively programmed for a logical "0" in any bit position.
The nickel-chromium fuse technology used is the same as all other Harris
8ipolar PROMs and the JAN approved MIL-M-38510 PROMs.
The HM-76160/161 contain test rows and columns which are in addition
to the storage array to assure high programmability and guarantee parametrics and A.C. performance. The fuses in these test rows and columns
are blown prior to shipment.
There are three chip enable inputs on the HM-76160/16l.
CE2 high. and CE3 high.enables the device.

CEl low.

Functional Diagram
(21 )(22)(23)(1 1(2) (3) (4)

A10 AgA8 A7A6A5A4

128 x 64
MEMORY
ARRAY

101128

ROW
DECODER

.L-________~·127Lr__~_,--~--~~--~_,--~

(24)' Vce
(12)-GND

2-78

Specifications HM-16160/161
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
-65 0e to +1500 e
Operating Temperature (Ambient) -55 0e to +1250 e
Maximum Junction Temperature
+1750e

Output or Supply Voltage (Operating) -0.3 to +7.0V
Address/Enable Input Voltage
5.5V
Address/Enable Input Current
-20mA
100mA
Output Sink Current

HM-76160/161-5 (Vee = 5.0V ±5%, TA = ooe to +75 0 e)
HM-76160/161-2 (Vee = 5.0V :tl0%, TA = -55 0e to +1250 e)
Typical Measurements are at TA = 25 0 e, Vee = +5V

D.C. ELECTRICAL CHARACTERISTICS (Operating)

SYMBOL

PARAMETER

MIN

TYP

MAX

UNITS

IIH
IlL

Address/Enable "1"
"0"
Input Current

-50.0

+40
-250

IJ.A
IJ.A

VIH
VIL

I nput Threshold "1"
Voltage
"0"

2.0

1.5
1.5

0.8

V
V

VCC
VCC

VOH
VOL

Output
Voltage

3.2*
0.35

0.50

V
V

10HE
10LE

Current

+40
-40*

IJ.A
IJ.A

-1.2

-15*

-100*

VOUT = O.OV, One Output at a
Time for a Max. of 1 Second

180

VCC = VCC Max., All Inputs
Grounded.

"1"
"0"

2.4*
-

Output Disable "1"
"0"

VCL

Input Clamp Voltage

lOS

Output Short Circuit
Current

ICC

Power Supply Current

TEST CONDITIONS

= VCC Max.
= 0.45V

= VCC Min.
= VCC Max.
10H = -2.0mA, VCC = VCC Min.
10L = +16mA, VCC = VCC Min.

VOH, VCC = VCC Max.
VOL = 0.3V, VCC = VCC Max.
liN

= -18mA

NOTE: Positive current defined as into device terminals.
*"Three State" only

A.C. ELECTRICAL CHARACTERISTICS (Operating)

HM-76160/161-S
SV±S%
DoC to +7S oC
SYMBOL

PARAMETER

HM-76160/161-2
SV ±10%
-SSoC to + 12So C

MIN

TYP

MAX

MIN

TYP

MAX

TAA

Address Access Time

TEA

Chip Enable Access Time

UNITS

A.C. limits guaranteed for worst case N2 sequencing with maximum test frequency of SMHz.

CAPACITANCE: T A
SYMBOL
CINA, CINCE
COUT

25 0 e (NOTE: Sampled and guaranteed - but not 100% tested.)
MAXIMUM

UNITS

Input Capacitance

PARAMETER

VCC

= 5V, VIN = 2.0V, f = lMHz

Output Capacitance

VCC

= SV, VOUT = 2.0V. f = lMHz

2-79

TEST CONDITIONS

SWITCHING TIME DEFINITIONS

CEl==*:_ _ _ _ _~l VIH
1.SV
1.SV
I
'IlL

ADDRESSES

~_l_.S_V_ _ _ _ _ ~::

CE2. eE3

-+I!___~VOH
~ VOL

OUTPUTS _ _

-I
I
I

--J

k"--~!""--">!-

OUTPUTS

TAA

: :

TEA

I
I

t,. tf

A.C. TEST LOAD

Vee

PROM
OUTPUT

0---.--.....--<>

TEST POINT

30pF*

* Includes jig & probe
total capacitance

•

2-80

T.S.

I- -l TEA I< Sn.

JAN-OS12

HARRIS
SEMICONDUCTOR
PRODUCTS DIVISION

512 BIT, BIPOLAR PROM
MIL/M38510/20101

A DIVISION OF HARRIS CORPORATION

Features

Pinout

•

FIELD PROGRAMMABLE

•

64 WORDS/S BITS PER WORD

•

FULLY DECODED

•

DTL/TTL COMPATIBLE

•

TOP VIEW - D.LP.

55n. ACCESS TIME

Description
The JAN-0512 is a field programmable 64 word by 8 bit PROM. In an
unprogrammed memory, all "Memory Elements" are short circuits so that
logical "zeros" appear at each output bit position for any address input.
"Electronic Programming" involves the alteration of specific "Memory
Elements" to create logical "ones" in selected bit positions. This alteration is irreversible and cannot be accomplished under normal operating
conditions.

N.C.

VCC

N.C.

IC"

"Must be left open circuit

Block Diagram
OUTPUT BUFFERS

r=----------Al

ADDRESS
MEMORY
ELEMENTS
&
DECODING
MATRIX
AS

ENABLE

-Ie - Internal Connection must be left open

NOTE: For operational condition. return pins
11, 13, and 23 to svstam ground.

2-81

Specifications JAN-0512
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range
Input Voltage Range
Storage Temperature Range
Lead Temperature (Soldering 10 Seconds)
Thermal Resistance, Junction-to-Case
Output Supply Voltage
Output Sink Current
Maximum Power Oissipation, Po
Maximum Junction Temperature, TJ

-0.5 VOC to 7.0 VOC
-1.5 VOC at -12mA to 5.5VOC
-65 0 C to + 1500 C
300 0 C
JC' Case J = 30 oC/w
-0.5VOC to 7.0VDC
+30mA
575mWdc
1750 C

RECOMMENDED OPERATING CONDITIONS
Supply Voltage
Minimum High Level Input Voltage
Maximum Low Level Input Voltage
Normalized Fanout (Each Output)
Ambient Operating Temperature Range

4.75 VOC Min. to 5.25VDC Maximum
2.OVOC
0.8V OC
6 Maximum (10mA)
-550 C to +1250 C

ELECTRICAL CHARACTERISTICS
The electrical characteristics are as specified in the table and apply over the full recommended ambient operating temperature range, unless otherwise specified.
LIMITS
SYMBOL

TEST

MIN

MAX

UNITS

TEST CONDITIONS

VOL

Low Level Output Voltage

0.45

Volts

VCC -4.75V
VIN =2.0V
IOL = 10mA

VIC

Input Clamp Voltage

-1.5

Volts

VCC = 4.75V
liN = -12mA
TA = 25 0 C

100

P.A

VCC = 5.25V
VOH = 2.8V
VIN = 0.8V

200

P.A

VCC = 5.25V
VOH = 5.25V
VIN = 0.8V

P.A

VCC = 5.25V
VIN = 2.4V;

100

P.A

VCC = 5.25V
VIN = 5.25;(1)

-1.6

VCC = 5.25V
VIN =0.4V;@

100

VCC = 5.25V
VIN =0

140

ICEXI
Maximum Collector Cut-Off
Current

ICEX2

IIHI
High Level Input Current
IIH2
ilL

Low Level Input Current

ICC

Supply Current

tPHL
tPLH

-0.2

Propagation Delay Time
High-to-Low Level Logic
Propagation Delay Time

Low-to-High Level Logic
NOTES:

1. When testing one E input. apply 5.25V to the other.
2. When testing one E input, apply GND to the other.

2-82

VCC = 5.0V
CL = 30pF Min.
Rl =470n ±5%

Switching Time Test Circuits

+5.0V

INPUT

5.0V

VCC

A1
A2
PULSE
GENERATOR
PRR

=1MHz -

20%

SEE

NOTE 2

D.U.T.

E1
E2

;,1"~~_1_0_ns

_ _ _ _ _V_
2.7V

"_"S_ - - - 3.0V ±. O.1V

INPUT

1\.:::..:..:._ _ _ _ _ OV
,-----VOH

OUTPUT

,--------+--..- - - - - - VOH
1.5V

tpHL

IL
f--

VOL

NOTES:

1. Pins 12 and 14 shall be left open.
2. The applicable test table should be selected from the altered item drawing.

3. C1 = O.5J.lF±10%; R1 =50n ±S%; R2=470n±S%; R3=lkn±S%;
CL = 30pF including jig and probe capacitance.

2-83

•

Characteristic Curves

OUTPUT CHARACTERISTICS

OUTPUT CURRENT

VS.

TEMPERATURE

40
VCC-5V

VCC-5V
36

;( 30

;(

..
I-

/)!/ ~~

a:
a: 20

:;,

~ .. ~~/

~4.75V

-55

..,'"
~a:

o
26

-66

126

.....'"

CL -3OpF

";I

a:
a:

>
...

125

VCC-5V

IOL = IOmA
VCC

:;,
-

Transition Definitions:
H=
L=
V=
X=
Z=

Transition
Transition
Transition
Transition
Transition

to
to
to
to
to

High
Low
Valid
Invalid or Don't Care
Off (High Impedance)

3-3

HIGH
IMPEDANCE

HARRIS

H.M-6322

SEMICONDUCTOR
PRODUCTS DIVISION

CMOS ROM

A DIVISION OF HARRIS CORPORATION

1024 Word x 12 Bit
Pinout

Features

TOP VIEW-DIP
•

HM-6100COMPATIBLE
500 ILW

•

LOW POWER STANDBY

•

HIGHSPEED

•

STATIC OPERATION

•

lB PIN PACKAGE FOR HIGH DENSITY

DXO

•

ON CHIP ADDRESS REGISTER

DXl

E
G

DX2
DX3
DX4

Description

GND

The HM-6322 is a high speed, low power, silicon gate CMOS Static ROM,
organized 1024 words by 12 bits, with multiplexed data and address lines.
The XS output pin is a mask programmable, external select line used to
activate an external device, usually RAM. Signal polarities and functions
are specified for direct compatibility with the HM-6100.

PIN NAMES
OX

E -

Address Input
and Data Out
Chip Enable

G XS -

logic Symbol
DXO
DXl
DX2
DX3
DX4
DX5
DX6
DX7
DX8
DX9
DX10
DXll
XS

Operation
Address and data out are multiplexed on the 12 DX lines (DXO - DX11).
The address is latched into the on chip register by the falling edge ofE.
Data out becomes valid when E, G and G are all in the enabled state. The
XS pin becomes valid a propagation delay after an appropriate address is
presented to the address register.
GND

Functional Diagram

r------ -1'oFl;-o-----l
x

(DXO-DXl1)

I
I

12 BIT
(A2-AB)
ADDRESS 1-"'-::":::"':"::':-1
REGISTER

128 x B
ARRAY

¥P
¥
L
A

I
I

~~I-T-O-D+X
I LINES

_...I

G
DXO.DXO.VCC
DX1~,VCC

DX2,uX2.VCC
DX3.DX3.VCC
DX4,l5X4.vcc
DX5.I»«i.VCC
PROGRAMMABLE
RAM SELECT

CAUTION: These devices are sensitive to electrostatic discharge.
Users should follow Ie Handling Procedures specified on pg. 1-6.

3-4

Output Enable
Output Enable
External Select

'OBC = OUTPUT
BUFFER CONTROL

Specifications HM-6322-21-9
ABSOLUTE MAXIMUM RATINGS

-0.3V to +8.0V

Supply Voltage (Vee - GND)
Applied Input or Output Voltage
Storage Temperature Range
Operating Temperature Range
Industrial -9
Military -2

ELECTRICAL CHARACTERISTICS

D.C.

vee = 5.0V

GND -0.3 to vee +0.3V
-650 e to +1500 e
-40 0e to +850 e
-550e to +125 0e

± 10%

SYMBOL

PARAMETER

MIN

VIH

Logical "1" Input Voltage

3.0

VIL

Logical "0" Input Voltage

IlL

Input Leakage

-1.0

VOH

Logical "1" Output Voltage

3.5

VOL

Logical "0" Output Voltage

Output Leakage

ICCSB

Standby Supply Current

ICCOP

Operating Current

CI
CIO

TYP

MAX

UNITS

TEST CONDITIONS

-1.0

CD
1nput Capacitance ®
I/O Capacitance ®

1.1

+1.0

IJ.A

OV5;VIN5;vcc

lOUT = -2.0mA

0.4

10UT= 2.0mA
ov5;vo5;vcc

1.0

IJ.A

100

IJ.A

VI=OorVCC

f=lMHz,IO=O

5.0

7.0

VI = VCC or GND

6.0

10.0

See Switching Waveforms page 6.
INDUSTRIAL
SYMBOL

A.C.

PARAMETER

MIN

MILITARY

MAX

MIN

MAX

UNITS

TELQV

Access Time from E

350

400

TGHQV

Output Enable Time

160

180

TGLQZ

Output Disable Time

180

TEHEL

Strobe Pos. Pulse Width

TELEL

Cycle Time

TAVEL

160
80

430

490

Address Set-Up Time

TELAX

Address Hold Time

TELXSV

Propagation to XS

110

TEST CONDITIONS
VCC = 5± 10%

ns
125

NOTES:

CD Operating Supply Current (ICCOP) is proportional to operating frequency, example typical ICCOP = 3mA/MHz.
®
®

Capacitance sampled and guaranteed - not 100% tested.
A.C. test conditions: Inputs- TRise = TFal1 = 20ns; Outputs - CLoad = 5OpF. All timing measurements
at 1.5V reference level.

3-5

Specifications HM-6322C-9
ABSOLUTE MAXIMUM RATINGS

Supply Voltage (vee - GND)
Applied Input or Output Voltage
Storage Temperature Range
Operating Temperature Range

vee = 5.0V ± 10%

ELECTRICAL CHARACTERISTICS

D.C.

SYMBOL

PARAMETER

MIN

VIH

Logical "1" Input Voltage

3.0

VIL

Logical "0" I nput Voltage

ilL

I nput Leakage

-10

VOH

Logical "1" Output Voltage

3.5

VOL

Logical "0" Output Voltage

Output Leakage
Standby Supply Current

Iceop

Operating Current

TYP

MAX

UNITS

TEST CONDITIONS

-10

ICCSS

CIO

III

-0.3V to +8.0V
GND -0.3 to vee +0.3V
-650 e to +150oe
-40 oe to +85 0 e

®
®

O.S

+10

f.1A
V

0.4

10UT= 1.0mA

Ov~vo~vee

OV~VIN~VeC
lOUT = -1.0mA

f.1A

500

f.1A

VI = 0 or vec

rnA

f=lMHz,IO=O
VI = vec or GND

Input Capacitance

5.0

7.0

I/O Capacitance

6.0

10.0

See Switching Waveforms page 6.
INDUSTRIAL
SYMBOL

A.C.

PARAMETER

MIN

MAX

UNITS

TELQV

Access Time from

500

TGHQV

Output Enable Time

250

TGLQZ

Output 0 isable Time

250

TEHEL

Strobe Pos. Pu Ise Width

250

TELEL

Cycle Time

750

TAVEL

Address Set-Up Time

TELAX

Address Hold Time

100

TELXSV

Propagation to XS

TEST CONDITIONS
VCC = 5

± 10%

ns
200

NOTES:

Operating Supply Current (lCCOP) is proportional to operating frequency, example typical lecop = 3mA/MHz.

® Capacitance sampled and guaranteed - not 100% tested.
® A.C. test conditions: Inputs - TRise = TFall = 20ns; Outputs - CLoad = 50pF.
at 1.5V reference level.

3-6

All timing measurements

Custom ROM Programming
characters identifying the customer and the pattern number.
Next are 2 characters designating true or false for inputs
DXOand DX1 tochips select gate A (see Functional Diagram)
and 6 characters designating true, false or don't care for
inputs DXO, DX1, DX2, DX3, DX4 and DX5 to the RAM
select gate B (see Functional Diagram). Next is one character
(H or L), designating aBC as active high or active low (column 16). Column 17 is for designating XS as active high or
active low (H or L). The header ends with a rubout.

HM-6322 programming information is generated from
the PAL III Symbolic Assembler, (in conjunction with the
DEC PDP/8 Type System) as a "second pass" binary tape.
A separate tape is required for each 1024 word ROM pattern. A header is added to the front of each tape giving
customer 10, chip select and XS programming information.
The header consists of 16 ASCII characters generated from
a standard teletype. Channel 8 is always punched. The
header begins with a rubout followed by 6 alphanumeric

CHANNELS

87654

COLUMN - 1
2

3
4
5
6
7

8
9
10
11
12
13
14

15
16
17
18

CHARACTER

o
o
o

••••• 0 • ••
••
.0

RUBOUT
H

••
••
••

0
••
O.

S
D
J

5
3
T

•

.0.
••

••• ••

•

COMMENTS

•

••

•• • o0 •• •
••
0 ••
••
O ••
••
o ••
••
o ••
••
o ••
••
••
••
••••• 0 •••

·0·
.0.

}
}
}
}

BEGIN HEADER
3 CHARACTER CUSTOMER ID
(A-Z. 0-91 ARE ALLOWABLE

3 CHARACTER CUSTOMER PATTERN ID
(A-Z, 0-91 ARE ALLOWABLE
DXO CHIP SELECT PROGRAMMING
DX1
DXO
DX1

F
F

SPROCKET HOLES

}

DX2

TRUE, F

FALSE

EXTERNAL SELECT (XSI
GATE PROGRAMMING
T ~ TRUE, F ~ FALSE, V

DX3

V
V

DX4

L
L

OBC }
XS

RUBOUT

END OF HEADER

DON'T CARE

DX5

* ACTIVE LEVEL

H ~ ACTIVE HIGH
L ~ ACTIVE LOW

0
0

•
•
•

0
0

PAL III symbolic assembler "second pass" output is of this form.
Channel 8 only punches indicate a leader or trailer. An address is

•

•••
)...-..

LEADER

0
0

•

designated by a punch in Channel 7. 12 bits of data are represented

SET LOCATION

by two adjacent volumns.

TO (020018
SET LOCATION

(6-11 in the second column.

TO (600018

A A A 0 B B B
C C COD D B

TYPICAL OCTAL
NUMBER ABC D

The set to location (020018 is an automatic output of the PAL III
Symbolic Assembler and can be disregarded. Set to location (600018

f'"--"" X

•
••

DXO-DX5 are represented by channels

(6-11 in the first column. DX6-DX11 are represented by channels

X X 0 X X

is an example of user defined ROM data location and is most

CHECK SUM

commonly used.

XXXOXXX

o
o
o
o

TRAILER

SPROCKET HOLES
*See Functional Diagram

3-7

Ell

Custom ROM Programming (Continued)
HEADER BLOCK:

4096 words or as narrow as 64 words and positioned any
where in the 4K field.

The header block defines the customer and pattern identification code and the ROM control function programming
information (columns 2-7). The control functions are chip
select programming, external select (XS) active area and
polarity, ROM output buffer control (aBC). The chip select programming information provided in column 8 and 9
of the header block addresses the ROM, which responds in
1 K blocks (e.g. 0000-102410 - 0000-17778).

Gate C is a programmable inverter used to determine the
polarity of XS in the active window.
Gate D is a programmable inverter used in combination
with Gates A and B to control the output buffer enable line.
Gate D is normally programmed as an inverter. This serves
to disable Gate A and the ROM output buffers anytime that
XS is active.

The external select (XS) active area is defined in columns
10-15, it can be an area as small as 64 words or as wide as
4096 in 64 word blocks. The polarity of XS in the active
state is defined in column 17 (H for active high and L
for active low).

In special case applications, there may be a need to have
some of the area assigned to ROM also assigned to RAM,
or it may be desired to have XS in the active state while
the ROM outputs are enabled. An example of this would
be a system designed to have the lower 1 K block of memory
(0000-1777 octal) allocated to ROM. However, it may be
necessary to have a small amount of read-write memory
for temporary storage. In this case the ROM control logic
would be programmed to enable the output buffers for
th is 1 K block except for the area that was assigned to RAM.
In this example aBC (column 16) would be specified low
which would disable the output buffers when XS is active.
The chip select gate (A) would be programmed to respond
to addresses having DXO, DX1 low and XS decode gate (B)
programmed to respond to the addresses dedicated to RAM.

Column 16 is used to specify the state of aBC (output
buffer control line), H for high, L for low. The output
buffer control line in conjunction with the programmable
chip select gate determines when the output buffers are
enabled. Typically, the output buffers would be disabled
when XS is in the active state and XS deactivated when the
output buffers are enabled. In this instance aBC would be
programmed low by specifying an L in column 17 of the
header.
PROGRAMMABLE GATE DEFINITIONS:
Gate A is the programmable chip select bit programmed to
define the 1 K address block out of a 4K field that the ROM
responds to. The possibilities are (0000-17778); (200037778); (4000-57778); (6000-77778).
_

MATRIX PATTERN CODE:
The pattern code is a standard DEC PDP/8 binary code tape.
It is made up of a leader (channel 8 punch), a starting address, 1024 words of binary data, check sum and a trailer
(channel 8 punch).

Gate B is used to program the address window for which
external select is active. This window can be as wide as

----------Switching Waveforms
~--------------------TELEL----------------~

G--_ _ _ _ _ _-+_____J
I----~

*"C"

G • has the same timing as G and

is inverted

3-8

A Typical Microprocessor System
DXIO-111
10 - 255)

r - - f-E

f-G

HM~100

MICROPROCESSOR

~ DXD

G
OX11
DX10

f - ox,

ox.
ox.

OX7
OX6
DX5

~ OX2
OX3
' - - OX4

~GND
LXMAR

+vy

+Vr

+V~
vee

A3
A2

vee
A4

A'
AD
AS
A6
A7

s;
003
OQ2
OQ,
OQD

r!:-

~
3

A3
A2
A'
AD
AS
A6
A7

vee
A4

+Vj
f-

003~
DQ2~
D01 ..;....
DOO 7

A3
A2
A'
AD
A6
A6
A7

vee
A4

s;
OQ3
DQ2
DQ,
OQD

_
E
I~~NO
52~ Iff~NO 52l fl~ND 52

MEMSEL

++0-

;!t

XTe

HM-6322
1024 x 12
ROM
ADDRESS SPACE
(3072 - 4095)10

HM-6561
256 x 4
RAM

HM-6661
256 x 4
RAM

ADDRESS SPACE (0000 - 0255) 10

•

3-9

HARRIS

HM-6501

SEMICONDUCTOR
PRODUCTS DIVISION
A DIVISION OF HARRIS CORPORATION

256 x 4 CMOS RAM

NOT RECOMMENDED FOR NEW DESIGNS - SEE HM-6551

Features
•

Pinout

LOW STANDBY POWER

TOP VIEW

50J.LW MAX
20mW/MHz MAX

vee

•

LOW OPERATING POWER

•
•
•
•

FAST ACCESS TIME
DATA RETENTION VOLTAGE
TTL COMPATIBLE IN/OUT
HIGH OUTPUT DRIVE - 1 TTL LOAD

•
•

HIGH NOISE IMMUNITY
ON CHIP ADDRESS REGISTERS

•
•

•

THREE STATE OUTPUTS
EASY MICROPROCESSOR INTERFACING
LATCHED OUTPUTS

•

MILITARY AND INDUSTRIAL TEMPERATURE RANGES

220nsec MAX
2.0 VOLTS MIN

E
G

s
Q3

D3
Q2

D2
"1.._ _ _r"

A -ADDRESS INPUT
ENABLE
W-WRITE ENABLE
G -OUTPUT ENABLE

S - CHIP SELECT
D- DATA INPUT
Q- DATA OUTPUT

E - CH IP

Description
The HM-6501 is a 256 by 4 static CMOS RAM fabricated using selfaligned silicon gate technology. Synchronous circuit design techniques are
employed to achieve high performance and low power operation.

logic Symbol
E vee W

On chip latches are provided for address and data outputs allowing efficient interfacing with microprocessor systems. The data output buffers
can be forced to a high impedance state for use in expanded memory
arrays.

AD
Al
A2
A3
A4
AS
A6
A7

The HM-6501 is a fully static RAM and may be maintained in any state
for an indefinite period of time. Data retention supply voltage and supply
current are guaranteed over temperature.

00
00

01
Q1

02
02
03
03

S GNO

~------~-----,

Functional Diagram
AOo---r--,
A10-----j
AS 0------1
A6:0----t

GATED
ROW
DECODER

32 x 32

MATRIX

A7'o---L....,.,..--.J
G

DO.()-----I

>-----------,
A

010-----I>A4--------------r1

00
0

GATED
COLUMN
DECODER

AND DATA

DATA

INPUT/OUTPUT

0
020-----I(;~---------~---~~,_-_r~~~--_r.-~~
030---., ;:.,.________...J

ALL LINES POSITIVE LOGIC - ACTIVE HIGH

wo---q

THREE STATE BUFFERS:
A HIGH-OUTPUT ACTIVE

Eo----q~--~r_------r_r_~

DATA LATCHES:
LHIGH __ 0= 0
o LATCHES ON FALLING EDGE OF L
A2 A3 A4

G~~------------~
CAUTION: These devices are sensitive to electrostatic discharge.
Users should follow IC Handling Procedures specified on pg. 1- 6.

ADDRESS LATCHES:
LATCH ON RISING EDGE OF L
GATED DECODERS:
GATE ON RISING EDGE OF G

3-10

Specifications HM-6501B-2IHM-6501B-9

ABSOLUTE MAXIMUM RATINGS

OPERATING RANGE

Supply Voltage - (Vee - GND)

-O.3V to +8.0V

Applied Input or Output Voltage

(GND -O.3V)
to (Vee +O.3V)

Operating Supply Voltage -vee
Military (-2)
Industrial (-9)
Operating Temperature
Military (-2)
Industrial (-9)

-65 0C to +1500e

Storage Temperature

4.5V to 5.5V
4.5V to 5.5V

-55 0 e to +125 0 C
-40oC to +85 0 C

ELECTRICAL CHARACTERISTICS
TEMP. & vcc =
OPERATING
RANGE
SYMBOL

D.C.

PARAMETER

ICCSB

Standby Supply Current

ICCOP

Operating Supply Current

ICCDR

Data Retention Supply Current

--OQ

ALL LINES ACTIVE HIGH - POSITIVE LOGIC
THREE STATE BUFFERS:

A HIGH-OUTPUT ACTIVE
CONTROL AND DATA LATCHES:
LLOW-Q- 0

a LATCHES ON RISING EDGE OF L

ADDRESS LATCHES:
LATCH ON RISING EDGE OF L
GATED DECODERS:

GATE ON RISING EDGE OF G
A3 A4 AS A10 AS

CAUTION: These devices are sensitive to electrostatic discharge.
Users should follow IC Handling Procedures specified on pg. 1-6.

3-16

Specifications HM-6503-9

ABSOLUTE MAXIMUM RATINGS

PPERATING RANGE

Supply Voltage - (vee -GND)

-O.3V to +8.0V

Operating Supply Voltage

Input or Output Voltage Applied

(GND -O.3V)
to (Vee +O.3V)

Industrial (-9)

Storage Temperature

4.5V to 5.5V

Operating Temperature

-65 0 e to +1500 e

-40 0 e to +85 0 e

Industrial (-9)

ELECTRICAL CHARACTERISTICS
TEMP. & veeOPERATING
RANGE

ICCSB

Standby Supplv Current

ICCOP

Operating Supply Current (2)

ICCOR

Data Retention Supply Current

VCCOR

Data Retention Supply Voltage

2.0

Input leakage Current

-1.0

10Z

Output Leakage Current

VIL

Input Low Voltage

D.C.

MIN

PARAMETER

SYMBOL

VIH

Input High Voltage

VOL

OutPUt Low Voltage

VOH

Output High Voltage

Input CapacitanceCD

TEMP- 250 e

10.0

S.O

2.4

10: 1.SmA

VI = vee or GNO

•

/= lMHz
vo=vee or GNO

TELOV

Chip Enable Access Time

350

200

TAVOV

Address Access Time

370

200

TELOX

Ch ip Enable Output Enable

100

@
@
@

100

Time

TEHOZ

Chip Enable Output Disable
Time

TELEH

Chip Ena~e Pulse Negative
Width

350

200

TEHEL

Chip Enable Pulse Positive

150

100

@
@
@
@
@
@
@

Width

A.C.

NOTES:

1.
2.
3.
4.

TAVEL

Address Setup Time

TELAX

Address Hold Time

lWLWH

Write Enable Pulse Width

100

lWLEH

Write Enable Pulse Setup Time

250

100

lWLEL

Early Write Pulse Setup Time

-10

lWHEL

WrIte Enable Read
Setup Time

-10

TELWH

Early Write Pulse Hold Time

100

TOVWL

Data Setup Time

TDVEL

Early Write Data Setup Time

lWLOX

Data Hold Time

100

TELOX

Early Write Data Hold Time

100

TOVWL

Data Valid to Write Time

TELEL

Read or Write Cycle Time

500

300

@
@
@
@
@
@
@

All devices tested at worst case limits. Room temp., 5 volt data provided for information - not guaranteed.
Operating Supply Current (ICCOP) is proportional to Operating Frequency. Example: Typical ICCOP = 5mA/MHz.
Capacitance sampled and guaranteed - not 100% tested.
AC Test Conditions: Inputs - TR ISE = TFALL = 20nsec; Outputs - CLOAO = 50pF. All timing
measurements at 1.5V reference level.

3-18

Read Cycle

TELEL
TEHEL

TELEH

E
TEHQZ
VALID DATA OUTPUT

HIGH

TIME
REFERENCE

t t

-I

TRUTH TABLE
INPUTS

TIME
REFERENCE

-1

X
H

"\.

2
3
4

L
H

FUNCTION

OUTPUT
A

Z
Z

MEMORY DISABLED
CYCLE BEGINS. ADDRESSES ARE LATCHED

OUTPUT ENABLED
DUTPUTVALID

V
X

X
H

X
V

V
V

Z
Z

READ ACCOMPLISHED
PREPARE FOR NEXT CYCLE !SAME AS-II
CYCLE ENDS. NEXT CYCLE BEGINS (SAME AS 01

The address information is latched in the on chip registers
on the falling edge of E (T ~ 0). Minimum address set up
and hold time requirements must be met. After the required hold time, the addresses may change state without
affecting device operation. During time (T ~ 1) the output

becomes enabled but data is not valid until during time
(T ~ 2). Vii must remain high until after ,time (T ~ 2).
After the output data has been read, E rrlay return high
(T ~ 3). This will disable the output buffer and ready the
RAM for the next memory cycle (T ~ 4).

Early Write Cycle

TELEL
TELEH

II
W~~~~~---+----~~~~~~~~~~~~~~~~~~~~~~~~~--4----

-l

TDVEl

----l

TELOX-j

DATA VALID

T_O_V_EL-,-_
NEXT DATA

HIGH-l

REF~'~EENCE -----..,tl-----+-------------------------1I---------------------1tl--tI------+----I

TRUTH TABLE
TIME

INPUTS
A

-1

X
X
V

REFERENCE

2
3

OUTPUT

FUNCTION

X
V

Z
Z
Z
Z
Z

PREPARE FOR NEXT CYCLE (SAME AS-1I

CYCLE ENDS, NEXT CYCLE BEGINS (SAME AS 0)

X
X
X
V

The early write cycle is the only cycle where the output is
guaranteed not to oecome active. On the falling edge of
E (T ~ 0)' the addresses, the write signal, and the data
input are latched in on chip registers. The logic value of Vii
at the time E falls deterl1')ines the state of the output buffer
for that cycle. Since W is low in the early write cycle the
output buffer is latched into the high impedance state and

MEMORY DISABLED
CYCLE BEGINS, ADDRESSES ARE LATCHED
WRITE IN PROGRESS INTERNALl Y

WRITE COMPLETED

will remain in that state until E returns high (T ~ 2). For
this cycle, the data input is latched by E going low; therefore data set up and hold times should be referenced to E.
When E (T ~ 2) returns to the high state the output buffer
disables and all signals are unlatched. The device is now
ready for the next cycle.

3-19

Read Modify Write Cycle

TIME
REFERENCE

t
-1

TRUTH TABLE
TIME
REFERENCE

-1
0
1
2
3
4

5
6
7

INPUTS
A

X
H
H
H

"'L
L
L
L

"'X

.r x
H

....

X
H

X
V

OUTPUT

X
X
X
X
V
X

Z
Z

x x

X
V
V
V
V

X
V

Z
Z

X
X
X
X

X
X

The read modify write cycle begins as all other cycles on
the falling edge of E (T .; 0). The W line should be high at
(T = 0) in order to latch the output buffers in the active
state. During (T = 1) the output will be active but not valid
until (T = 2). On the falling edge of the W (T = 3) the data
present at the output and input are latched. The W signal

FUNCTION

MEMORY DISABLED
CYCLE BEGINS. ADDRESS ARE LATCHED
OUTPUT ENABLED
OUTPUT VALID. READ AND MODIFY TIME
WRITE BEGINS. DATA IS LATCHED
WRITE IN PROGRESS INTERNALLY
WRITE COMPLETED
PREPARE FOR NEXT CYCLE (SAME AS -1)
CYCLE ENDS. NEXT CYCLE BEGINS (SAME AS 0)

also latches itself on its low going edge. All input signals
excluding E have been latched and have no further effect
on the RAM. The rising edge of E (T = 5) completes the
write portion of the cycle and unlatches all inputs and the
output. The output goes to a high impedance and the RAM
is ready for the next cycle.

1- - - - - - - - - - - - - - - - - - - - - -

Late Write Cycle

REFER~~~~ ----+---+-----+---~----+----Il---tt---1t-----

3-20

TIME
REFERENCE

-I

0
I

X
X
V
X
X
X
X

Z
Z

L
L

X
V
X
X
X
X
V

INPUTS

2
3

H
H

4
5

OUTPUT
FUNCTION
MEMORY DISABLED
CYCLE BEGINS, ADDRESSES ARE LATCHED
WRITE BEGINS, DATA IS LATCHED
WRITE IN PROGRESS INTERNALLY

X
X
X

WRITE COMPLETED
PREPARE FOR NEXT OYCLE (SAME AS-1)

Z
Z

CYCLE ENDS, NEXT CYCLE BEGINS (SAME AS 0)

The late write cycle is a cross between the early write
cycle and the read-modify-write cycle.
Recall that in the early write the output is guaranteed to
remain high impedance, and in the read-modify-write
the output is guaranteed valid at access time. The late

write is between these two cases. With th is cycle the output
may become active, and may become valid data, or may
remain active but undefined. Valid data is written into the
RAM if data set up, data hold, write setup and write pulse
widths are observed.

NOTES:
In the above descriptions the numbers in parenthesis (T = X) refer to the respective timing diagrams.
The numbers are located on the time reference line below each diagram. The timing diagrams shown
are only examples and are not the only valid method of operation.

Suggestions For 6503 Memory Array Design
The HM-6503 is a device that can be used to good advantage in systems which are offered with choices of memory
array size. With one common memory board layout the
designer can easily offer two different array sizes. This is
accomplished by using the conveniently similiar pinouts of
the HM-6503 (2K by 1) and the HM-6504 (4K by 1). For
example, a 16K word by 8 bit array using HM-6503s and a
32K word by 8 bit array using HM-6504s can be easily implemented on the same printed circuit card. The circuit
diagram suggests one implementation requiring only one
jumper wire for 16K or 32K word selection. This single
jumper wire also allows the 16K array to utilize the HM-

TO RAM

PIN 14

HD-644D
CMOS

I OF B
LATCHED
DECODER
DRIVER

B
WORO
ENABLE
LINES

L,7'I~,--------=~~RESSES

____6_5_0_3_H__
o_rt_h_e_H_M
__
-6_5_0_3_L_v_e_rs_io_n_.________________________________________________________________

low Voltage Data Retention
HARRIS CMOS RAMs are designed with battery backup in mind. Data retention voltage and supply current are
guaranteed over temperature. The following rules insure data retention:

Chip Enable eEl must be held high during data retention; within VCC + 0.3V to VCC - 0.3V.

On RAMs which have selects or output enables (e.g. S, (iI, one of the selects or output enables should be
held in the deselected state to keep the RAM outputs high impedance, minimizing power dissipation.

All other inputs should be held either high (at CMOS VCCI or at ground to minimize ICCDR.

Inputs which are to be held high (e.g.

E I must be kept between VCC + 0.3V and 70% of VCC during the

power up and power down transitions.

The RAM can begin operation one TEHEL after VCC reaches the minimum operating voltage (4.5 voltsl.
DATA RETENTION TIMING

-----..1-=--- DATA RETENTION MODE ----00-1 ...- - - - - - vce 22.DV

VCC±D.3V

3-21

~IIiII=

•

HARRIS

HM-6504

SEMICONDUCTOR
PRODUCTS DIVISION
A DIVISION OF HARRIS CORPORATION

4096 x 1 CMOS RAM
Pinout

Features

•
•
•
•
•

LOW POWER STANDBY

TOPVIEW

250/lWMAX.

LOW POWER OPERATION

35mW/MHz MAX.

EXTREMELY LOW SPEED POWER PRODUCT
@2.0VMIN.

DATA RETENTION

vee

TTL COMPATIBLE INPUT/OUTPUT

•

THREE-STATE OUTPUT

•
•
•
•
•
•

STANDARD JEDEC PINOUT

Al0

200nsac MAX.

FAST ACCESS TIME
MILITARY TEMPERATURE RANGE
INDUSTRIAL TEMPERATURE RANGE

All

GND

18 PIN PACKAGE FOR HIGH DENSITY
ON CHIP ADDRESS REGISTER

Logic Symbol

Description

vee

The HM-6504 is a 4096 x 1 static CMOS RAM fabricated using self
aligned silicon gate technology. The device utilizes synchronous circuitry
to achieve high performance and low power operation.
On chip latches are provided for addresses, data input and data output
allowing efficient interfacing with microprocessor systems. The data
output can be forced to a high impedance for use in expanded memory
arrays.
The HM-6504 is a fully static RAM and may be maintained in any state
for an indefinite period of time.
Data retention supply voltage and supply current are guaranteed over
temperature.

AO
Al
A2
A3
A4

A5
A6
A7

A7
A6

- Address Input
E - Chip Enable

iN - Write Enable
o - Data Input

Data Output

AO
Al

LATCHED
ADDRESS

GATED
ROW

64,64
MATRIX

>--00
A

ALL LINES ACTIVE HIGH - POSITIVE lOGIC
THREE STATE BUFFERS;

A HIGH-OUTPUT ACTIVE
CONTROL AND DATA LATCHES:
LLOW-Q-O
Q LATCHES ON RISING EDGE OF l
ADDRESS LATCHES:

LATCH ON RISING EDGE OF L
GATED DECODERS:

GATE ON RISING EDGE OF G
A3 A4A5A11A10A9

CAUTION: These devices are sensitive to electrostatic discharge.
Users should follow IC Handling Procedures specified on pg. 1-6.

3-22

A8
A9
AIO
A11

Functional Diagram
AB

GND

HM-6504B-2IHM-6504B-D
ABSOLUTE MAXIMUM RATINGS

OPERATING RANGE

Supply Voltage - (vee -- GND)

-O.3V to +8.0V

Input or Output Voltage Applied

(GND -O.3V)
to (Vee +O.3V)

Operating Supply Voltage
Military (-2)
Industrial (-9)

-65 0 e to +150o e

Storage Temperature

4.5V to 5.5V
4.5V to 5.5V

Operating Temperature
Military (-2)
Industrial (-9)

-55 0 e to +1250 e
-40 o e to +85 0 e

ELECTRICAL CHARACTERISTICS
TEMP. & VCC=
OPERATING
RANGE
PARAMETER

SYMBOL

D.C.

MIN

ICCSB

Standby Supply Current

ICCOP

Operating Supply Current@

ICCDR

Data Retention Supply Current

VCCDR

Data Retention Supply Voltage

2.0

TEMP = 250 CG)
VCC= 5.0V
TEST
CONDITIONS

MAX

TYPICAL

UNITS

1.0

Il A

10 =0
VI = VCC or GND

rnA

f=1MHz.IO=0
VI = VCC or GND

0.1

Il A

10
VI

1.4

Input Leakage Current

-1.0

+1.0

0.0

IlA

GNDSVISVCf

10Z

Output Leakage Current

-1.0

+1.0

0.0

IlA

GNDSVO SVCC

Vil

Input Low Voltage

-0.3
VCC
-2.0

0.8
VCC
+0.3
0.4

2.0

VIH

Input High Voltage

Val

Output Low Voltage

VOH

Output High Voltage

Input capacitance@)

2.0

0.25

4.0

8.0

5.0

f = lMHz
VI = vec or GND

Output CapacitanceG)

10.0

6.0

f = lMHz

TElOV

Chip Enable Access Time

200

150

TAVOV

Address Access Time

220

150

2.4

TElOX

Chip Enable Output Enable
Time

TEHOZ

Chip Enable Output Disable

TElEH

Chip Enable Pulse Negative

200

150

Time
Width

A.C.

= 0 VCC = 2.0
= vec or GND

TEHEl

Chip Enable Pulse Positive
Width

TAVEL

Address Setup Time

TElAX

Address Hold Time

TWlWH

Write Enable Pulse Width

TWlEH

Write Enable Pulse Setup Time

150

100

TWlEl

Early Write Pulse Setup Time

-10

TWHEl

Write Enable Read Mode
Setup Time

-10

TElWH

Early Write Pulse Hold Time

TDVWl

Data Setup Time

TDVEl

Early Write Data Setup Time

TWlDX

Data Hold Time

TElDX

Early Write Data Hold Time

TOVWl

Data Valid to Write Time

TElEl

Read or Write Cycle Time

290

210

= 2.0mA
= -LOrnA

vee or

GND

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

All devices tested at worst case limits. Room Temp., 5V data provided for information - not guaranteed.
Operating Supply Current (ICCOP) is proportional to Operating Frequency. Ex: TypicaliCCOP = 5mA/MHz.
Capacitance sampled and guaranteed - not 100% tested.
AC test conditions: Inputs - TRISE = TFALL = 20ns; Output - CLOAD = 50pF. All timing measured at
1 .5 V reference level.

3-23

Specifications HM-6504-2IHM-6504-D

ABSOLUTE MAXIMUM RATINGS

OPERATING RANGE

Supply Voltage - (vee -GND)

-0.3'11 to +8.0V

Input or Output Voltage Applied

(GND -0.3V)
to (Vee +0.3V)

Storage Temperature

Operating Supply Voltage
Military (-2)
Industrial (-9)

4.5V to 5.5V
4.5V to 5.5V

Operating Temperature
Military (-2)
Industrial (-9)

-650 e to +1500 e

-55 0 e to +125 0 e
-40 0 e to +85 0 C

ElECTR ICAl CHARACTE RISTICS
TEMP. & VCC=
OPERATING
RANGE
SYMBOL
leeSB

D.C.

MIN

Standby Supply Current

leeop

Operating Supply Current®

leeDR

Data Retention Supply Current

VCeDR

Data Retention Supply Voltage

TYPICAL

UNITS

1.0

p.A

10=0
VI = vee or GND

f=lMHz.IO=O
VI = vee or GND

0.1

p.A

10 = 0, vee = 2.0
VI = vee or GND

1.4

2.0
.-1.0

+1.0

0.0

p.A

GND~VI~Vee

Output Leakage Current

-1.0

+1.0

0.0

p.A

GND~VO~Vee

VIL

Input Low Voltage

-0.3

2.0

vee
-2.0

0.8
vee
+0.3
0.4

Input Leakage Current

VIH

Input High Voltage

VOL

Output Low Voltage

2.0

0.25

VOH

Output High Voltage

4.0

Input Capacitance®

10 = -1.0mA

8.0

5.0

f = lMHz
VI = vee or GND

Output Capacitance@

10.0

6.0

f~ lMHz
VO = vee or GND

2.4

TELOV

Chip Enable Access Time

300

170

TAVOV

Address Access Time

320

170

TELOX

Chip Enable Output Enable
Time

100

TEHOZ

Chip Enable Output Disable

100

ns
ns

Time
TELEH

Chip Enable Pulse Negative

300

170

TEHEL

Chip Enable Pulse Positive
Width

120

TAVEL

Address Setup Time

Width

A.C.

NOTES:

1.
2.
3.
4.

TEST
CONDITIONS

MAX

10Z

lEI

PARAMETER

TEMP = 250 CG)
VCC= 5.0V

TELAX

Address Hold Time

TWLWH

Write Enable Pulse Width

TWLEH

Write Enable Pulse Setup Time

200

130

TWLEL

Early Write Pulse Setup Time

-10

TWHEL

Write Enable Read Mode
Setup Time

-10

TELWH

Early Write Pulse Hold Time

TDVWL

Data Setup Time

TDVEL

Early Write Data Setup Time

TWLDX

Data Hold Time

TELDX

Early Write Data Hold Time

TOVWL

Data Valid to Write Time

TELEL

Read or Write Cycle Time

420

240

10 = 2.0mA

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

All devices tested at worst case limits. Room temp., 5 volt data provided for information - not guaranteed.
Operating Supply Current (lCCOP) is proportional to Operating Frequency. Example: Typical ICCOP = 5mA/MHz.
Capacitance sampled and guaranteed - not 100% tested.
AC Test Conditions: Inputs - TRISE = TFALL = 20nsec; Outputs - CLOAD = 50pF. All timing
measurements at 1.5V reference level.

3-24

Specifications HM-6504C-D
ABSOLUTE MAXIMUM RATINGS

OPERATING RANGE

Supply Voltage - (Vee -GND)

-O.3V to +8.0V

Input or Output Voltage Applied

(GND -O.3V)
to (Vee +O.3V)

Operating Supply Voltage
Industrial (-9)
Operating Temperature
Industrial (-9)

-65 oe to +1500 e

Storage Temperature

4.5V to 5.5V

-40 0 e to +85 0 e

ELECTRICAL CHARACTERISTICS

TEMP. & VCC=
OPERATING
RANGE
SYMBOL

D.C.

PARAMETER

MIN

ICeSB

Standby Supply Current

ICCOP

Operating Supply current®

ICCDR

Data Retention Supply Current

VeCDR

Data Retention Supply Voltage

2.0

TEMP = 250 CG)
VCC= 5.0V
TEST
CONDITIONS

MAX

TYPICAL

UNITS

100

Il A

10 = a
VI = vee or GND

rnA

f= lMHz, 10=0
VI = vce or GND
VI =

Il A

1.4

10 = a vce = 2.0V

vee or uNO

Input Leakage Current

-1.0

+1.0

0.0

IlA

GND~VI~Vee

IOZ

Output Leakage Current

-1.0

+1.0

0.0

IlA

GND~VO~Vee

VIL

Input Low Voltage

-0.3
vee
-2.0

0.8
vee
+0.3
0.4

2.0

VIH

Input High Voltage

VOL

Output Low Voltage

VOH

Output High Voltage

Input Capacitance@)

2.0

0.25

4.0

10 = -LOrnA

8.0

5.0

f'" lMHz

Output Capacitance®

10.0

6.0

f = lMHz
vo = vee or GND

2.4

10 = 2.0mA

VI = vee or GND

TELOV

Chip Enable Access Time

300

170

TAVOV

Address Access Time

320

170

TELOX

Chip Enable Output Enable
Time

100

TEHOZ

Chip Enable Output Disable

100

Time

A.C.

NOTES:

TELEH

Chip Enable Pulse Negative
Width

300

170

TEHEL

Chip Enable Pulse Positive
Width

120

TAVEL

Address Setup Time

TELAX

Address Hold Time

TWLWH

Write Enable Pulse Width

TWLEH

Write Enable Pulse Setup Time

200

130

TWLEL

Early Write Pulse Setup Time

-10

TWHEL

Write Enable Read Mode
Setup Time

-10

TELWH

Early Write Pulse Hold Time

TDVWL

Data Setup Time

TDVEL

Early Write Data Setup Time

TWLDX

Data Hold Time

TELDX

Early Write Data Hold Time

TOVWL

Dat] Valid to Write Time

TELEL

Read or Write Cycle Time

420

240

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

All devices tested at worst case limits. Room temp., 5 volt data provided for information - not guaranteed.

Operating Supply Current (lCCOP) is proportional to Operating Frequency. Example: Typical ICCOP = 5mA/MHz.

Capacitance sampled and guaranteed - not 100% tested.

AC Test Conditions: Inputs - TRISE = TFALL = 20nsec; Outputs - CLOAO = 50pF. All timing

measurements at 1.5V reference level.

3-25

III

Specifications HM-6504-5
ABSOLUTE MAXIMUM RATINGS

OPERATING RANGE

Supply Voltage - (VCC - GND)

-O.3V to +8.0V

Input or Output Voltage Applied

(GND -O.3V)
to (GND +O.3V)

Storage Temperature

-650 C to +150oC

Operating Supply Voltage
Commercial

4.5V to 5.5V

Operating Temperature
Commercial

ooC to +75 0 C

ELECTRICAL CHARACTERISTICS
TEMP. & vccOPERATING
RANGE
SYMBOL

MIN

leeSB

Standby Supply Current

Iceop

Operating Supply Current

leeDR

Data Retention Supply Current

VCCDR

Data Retention Supply Voltage

D.C.

PARAMETER

10Z

TEMP = 25 0 C (j)
vcc= 5.0V
TEST
CONDITIONS

MAX

TYPICAL

UNITS

500

10 =0
VI = vee or GND

f = lMHz. 10 = 0
VI = vee or GND

500

vee = 2.0, 10 = 0
VI = vee or GND

1.4

Input Leakage Current

-10.0

2.0
+10.0

±O.5

/JA

GND:SVI :Svee

Output Leakage Current

-10.0

+10.0

±0.5

GND:SV0:SVee

VIL

Input Low Voltage

-0.3

0.8

2.0

VIH

Input High Voltage

vee
-2.0

vee
+0.3

2.0

VOL

Output Low Voltage

0.4

0.25

VOH

Output High Voltage

4.0

= -0.4mA

Input Capacitance@)

5.0

2.4
8.0

1.6mA

= lMHz
= vee or GND
f = lMHz
va '" vee or GND
f

III

Output Capacitance@)

10.0

6.0

100

0)
0)
0)

100

350

200

150

100

0)
0)
0)
0)
0)
0)

TELOV

Chip Enable Access Time

350

200

TAVQV

Address Access Time

370

200

TELQX

Chip Enable Output Enable

TEHQZ

Chip Enable Output Disable

TELEH

Chip Enable Pulse Negative
Width

TEHEL

Chip Enable Pulse Positive
Width

TAVEL

Address Setup Time

TELAX

Address Hold Time

TWLWH

WI ite Enable Pulse Width

100

TWLEH

Write Enable Pulse Setup Time

250

100

TWLEL

Early Write Pulse Setup Time

-10

TWHEL

Write Enable Read
Setup Time

-10

TELWH

Early Write Pulse Hold Time

100

TDVWL

Data Setup Time

Time

A.C.

NOTES:

TDVEL

Early Write Data Setup Time

TWLDX

Data Hold Time

100

TELDX

Early Write Data Hold Time

100

TQVWL

Data Valid to Write Time

TELEL

Read or Write Cycle Time

500

300

ns
ns

0)
0)
0)
0)
0)

All devices tested at worst case limits, Room temp., 5 volt data provided for information - not guaranteed.

Operating Supply Current (lCCOP) is proportional to Operating Frequency. Example: Typical ICCOP = 5mA/MHz.

Capacitance sampled and guaranteed - not 100% tested.

AC Test Conditions: Inputs - TRISE = TFALL = 20nooc; Outputs - CLOAO = 50pF. All timing

measurements at 1.5V reference level.

3-26

Read Cycle
A
TELEL
TEHEL

TELEH

r
TEHQZ
VALID DATA OUTPUT

HIGH

TIME
REFERENCE

t t

-I

TRUTH TABLE
TIME
REFERENCE

-1
0
1

"'-

H
L
L

2
3

..r
H

4
5

INPUTS

OUTPUT
0

X
H
H
H
H
X
H

X
V

Z
Z

V
V
Z
Z

x
X
V

FUNCTION

MEMORY DISABLED
CYCLE BEGINS. ADDRESSES ARE LATCHED
OUTPUT ENABLED
OUTPUT VALID
READ ACCOMPLISHED
PREPARE FOR NEXT CYCLE (SAME AS-II
CYCLE ENOS. NEXT CYCLE BEGINS (SAME AS 01

The address information is latched in the on chip registers
on the falling edge of E (T = 0). Minimum address set Up
and hold time requirements must be met. After the required hold time, the addresses may change state without
affecting device operation. During time (T = 1) the output

becomes enabled but data is not valid until during time
(T = 2). iN must remain high until after time (T = 2)_
After the output data has been read, E may return high
(T = 3). This will disable the output buffer and ready the
RAM for the next memory cycle (T = 4).

Early Write Cycle

A~~~~~
TELEL

TELEH

HIGH-Z

REF~I~E~CE----+t---;-------------+-----------tt-tt----+-1

TRUTH TABLE
TIME

REFERENCE

INPUTS
iN
A

X
X
X
V

X
X

Z
Z
Z
Z
Z
Z

-1
0
1

"'-

..r

X
L
X
X

H
L

OUTPUT

X
V

FUNCTION

MEMORY DISABLED
CYCLE BEGINS. ADDRESSES ARE LATCHED
WRITE IN PROGRESS INTERNALL Y

WRITE COMPLETED
PREPARE FOR NEXT CYCLE (SAME AS -1)
CYCLE ENDS. NEXT CYCLE BEGIN& (SAME AS 01

The early write cycle is the only cycle where the output is
guaranteed not to become active. On the falling edge of
~ (T = 0), the addresses, the write signal, and the data
input are latched in on chip registers. The logic value of iN
at the time E falls determines the state of the output buffer
for that cycle_ Since W is low when ~ falls, the output buffer is latched into the high impedance state and

3-27

will remain in that state until ~ returns high (T = 2). For
this cycle, the data input is latched by E going low; therefore data set up and hold times should be referenced to E_
When E (T = 2) returns to the high state the output buffer
disables and all signals are unlatched. The device is now
ready for the next cycle_

•

ReBd Modify Write Cycle

TIME
REFERENCE

-I

TRUTH TABLE
TIME
REFERENCE

INPUTS
A

-I

0
I

"'-

X
H
H
H

2
3
4
5

L
L
L
L

.r x

X
H

X
V
X
X
X
X

OUTPUT

0
X
X
X
X
V
X

x x

X
V
V
V
V

X
V

Z.
Z

X
X

FUNCTION

The read modify write cycle begins as all other cycles
on the falling edge of E IT= 0). The W line should be
high at IT = 0) in 'order to latch the butput buffers in the
active state. During IT = 1) the output will be active but
not valid until IT = 2). On the falling edge of i:h~ WIT = 3)
the data present at the output and input are latched. The

MEMORY OISABLED
CYCLE BEGINS. ADDRESS ARE LATCHED
OUTPUT ENABLED
OUTPUT VALID. READ AND MODIFY TIME
WRITE BEGINS. DATA IS LATCHED
WRITE IN PROGRESS INTERNALLY
WRITE COMPLETED
PREPARE FOR NEXT CYCLE (SAME AS -II
CYCLE ENDS. NEXT CYCLE BEGINS (SAME AS 01

W signal also latches itself on its low going edge. All input
signals excluding E have been latched and have no further
effect on the RAM. The rising edge of E IT = 5) completes
the write portion of the cycle and unlatches all inputs and
output. The output goes to a high impedance and the
RAM is ready for the next cycle .

late Write Cycle

Q _ _ _..;H.;.;.'G;;;H;.;Z;...._ _ _ _ __

TIME
REFERENCE

t t -t t - ----+--+---+----+--+--+--1
-I

3-28

TIME
REFERENCE

INPUTS

X
H

MEMORY DISABLED

V
X
X
X
X
V

X
V
X
X
X
X

Z
X
X

CYCLE BEGINS, ADDRESSES ARE LATCHED
WRITE BEGINS, DATA IS LATCHED

L
L

OUTPUT

E Vii

3
4

J
H

H
X

FUNCTION

X
Z

WRITE IN PROGRESS INTERNALLY
WRITE COMPLETED
PREPARE FOR NEXT OYCLE (SAME AS -1)

CYCLE l=NDS, NEXT CYCLE BEGINS (SAME AS 0)

write is between these two cases. With this cycle the output
may become active, and may become valid data, or may
remain active but undefined. Valid data is written into the
RAM if data set up, data hold, write setup and write pulse
widths are observed.

NOTES:
In the above descriptions the numbers in parenthesis (T = n) refer to the respective timing diagrams.
The numbers are located on the time reference line below each diagram. The timing diagrams shown
are only examples and are not the only valid method of operation.

Low Voltage Data Retention

HAR R IS CMOS RAMs are designed with battery backup in mind. Data retention voltage and supply current are
guaranteed over temperature. The following rules insure data retention:
1.

Chip Enable (E) must be held high during data retention; within VCC + 0.3V to VCC - 0.3V.

On RAMs which have selects or output enables (e.g. S. Gl. one of the selects or output enables should be
held in the deselected state to keep the RAM outputs high impedance, minimizing power dissipation.

All other inputs should be held either high (at CMOS VCC) or at ground to minimize ICCDR.

Inputs which are to be held high (e.g.
power up and power down transitions.

The RAM can begin operation one TEHEL after VCC reaches the minimum operating voltage (4.5 volts).

must be kept between VCC + 0.3V and 70% of VCC during the

DATA RETENTION TIMING

- - - - -... t-....- - - - -

DATA RETENTION MODE

vee ~2.0V

vee ± O.3V

3-29

------l_------

Ell

1&1

HARRIS

HM-6505

SEMICONDUCTOR
PRODUCTS DIVISION
A DIVISION OF HARRIS CORPORATION

4096 x 1 CMOS RAM

Advance Information

Features

Pinout

•

TOP VIEW

•
•

•
•
•
•
•
•

LOW POWER STANDBY

250J.,lWMAX.

LOW POWER OPERATION

35mW/MHz MAX.

VCC

200nsMAX.

2.0VMIN.

FAST ACCESS TIME
DATA RETENTION

EXTREMELY LOW SPEED POWER PRODUCT

TTL COMPATIBLE INPUT/OUTPUT

EASY MICROPROCESSOR INTERFACING

Al0

MILITARY AND INDUSTRIAL TEMPERATURE RANGES

All
(l

18 PIN PACKAGE FOR HIGH DENSITY

GNO

Description
TN

A Address Input
DQ Data In/Out
E Chip Enable

The HM-6505 is a 4096 x 1 CMOS RAM fabricated using selfaligned silicon gate technology.
Synchronous circuit design
techniques are employed to achieve high performance and low
power operation.

Write Enable
Output Enable

logic Symbol

On chip address latches are provided to allow efficient interfacing with microprocessor systems. The common data in/out
can be forced to a high impedance state for use in expanded
memory arrays.

EVCCGW

AO
Al
A2
A3

A4
A5
A6
A7

The HM-6505 is a fully static RAM and may be maintained in
any state for an indefinite period of time.

Data retention supply voltage and supply current specifications
are guaranteed over temperature.

Al0
All

GND

Functional Diagram
AS
A7

64x64
MATRIX

AO
AI

ALL LINES ACTIVE HIGH POSITIVE LOGIC

THREE STATE BUFFERS:
A HIGH -OUTPUT ACTIVE
ADDRESS REGISTERS:
LATCH ON RISING EDGE OF L
GATED DECODERS:
GATE ON RISING EDGE OF G

A3 A4 AS'A11A10A9

CAUTION: These devices are sensitive to electrostatic discharge.
Users should follow IC Handling Procedures specified on pg. 1- 6.

3-30

Specifications HM-6505B-2IHM-6505B-9
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (vee - GND)
Input or Output Voltage Applied

Storage Temperature

OPERATING RANGE
-0.3 to 8.0V

Operating Supply Voltage
Military (-2)
Industrial (-9)

(GND -0.3V)
to (Vee +0.3V)

4.5V to 5.5V
4.5V to 5.5V

Operating Temperature
Military (-2)
Industrial (-9)

-650 e to 1500 e

-550 e to +1250 e
-40 0 e to +850 e

ELECTRICAL CHARACTERISTICS
TEMP& vcc =
OPERATING
RANGE
PARAMETER

SYMBOL

D.C.

MIN

TEMP = 25 0 C
VCC =5.0V

MAX

TYPICAL

UNITS

TEST CONDITIONS

1.0

IJA

10 =0
VI = VCC or GND

f = 1MHz, 10 = 0
VI = VCC or GND

0.5

IJA

10 = 0, VCC = 2.0
VI = VCC or GND

ICCSB

Standby Supply Current

ICCOP

Operating Supply Current

ICCDR

Data Retention Supply Current

VCCDR

Data Retention Supply Voltage

2.0

1.4

Input Leakage Current

-1.0

+1.0

0.0

IJA

GND~VI~VCC

IIOZ

Input/Output Leakage Current

-1.0

+1.0

0.0

iJA

GND .:SVIO~ VCC

VIL

Input Low Voltage

-0.3

O.B

2.0

VCC -2.0

VCC +0.3

2.0

0.4

0.25

10 = 2.0mA

4.0

VIH

Input High Voltage

VOL

Output Low Voltage

VOH

Output High Voltage

Input Capacitance@

B.O

5.0

10 = -1.0mA
VI = VCC or GND

Input/Output Capacitance@

10.0

6.0

f= 1MHz
VIO = VCC or GND

CIO

2.4

f= 1MHz

A.C.

TELQV

Chip Enable Access Time

200

130

TAVQV

Address Access Time

220

130

TELQX

Chip Enable Output Enable Time

TEHQZ

Chip Enable Output Disable Time

TGLQV

Output Enable Output Enable Time

TGHQZ

Output Enable Output Disable Time

TWLQZ

Write Enable Output Disable Time

TELEH

Chip Enable Pulse Negative Width

200

130

TEHEL

Chip Enable Pulse Positive Width

TAVEL

Address Set Up Time

TELAX

Address Hold Time

TWLWH

Write Enable Pulse Width

100

TWLEH

Write Enable Pulse Set Up Time

100

TELWH

Write Enable Pulse Hold Time

200

130

TDVWH

Data Set Up Time

100

TWHDZ

Data Hold Time

TWLDV

Write Data Delay Time

TELEL

Read or Write Cycle Time

290

180

@
@
@
@
@
@
@)
@)
@
@)
@)
@)
@)
@)
@
@
@
@

NOTES:

~
~

All devices tested at worst case limits. Room temp., 5 volt data provided for information-not guaranteed.
Operating Supply Current (ICCOP) is proportional to Operating Frequency, Example: Typical

ICCOP

SmA/MHz.

Capacitance sampled and guaranteed-not 100% tested.
AC test conditions: Inputs-TRISE
, .5V reference level.

= TFALL

== 20nsec; Output-C load == 50pF. All timing measured at

3-31

Specifications HM-6505-2IHM-6505-9
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (vee - GND)

OPERATING RANGE
-0.3 to 8.0V

Input or Output Voltage Applied

(GND-0.3V)
to (Vee +0.3V)

Storage Temperature

-650 e to 1500 e

Operating Supply Voltage
Military (-2)
Industrial (-9)
Operating Temperature
Military (-2)
Industrial (-9)

4.5V to 5.5V
4.5V to 5.5V
-550 e to +125 0 e
-40 0 e to +85 0 e

ELECTRICAL CHARACTERISTICS
TEMP & vcc =
OPERATING
RANGE
PARAMETER

SYMBOL

D.C.

ICCSB

Standby Supply Current

ICCOP

Operating Supply Current

Data Retention Supply Current

VCCDR

Data Retention Supply Voltage

MAX

TYPICAL

UNITS

TEST CONDITIONS

1.0

/.LA

10 =0
VI = VCC or GND

f = 1MHz, 10 = 0
VI = VCC or GND

0.5

/.LA

10 = 0, VCC = 2.0
VI = VCC or GND

1.4

I nput Leakage Current

-1.0

+1.0

0.0

/.LA

GND~VISVCC

IIOZ

I nput/Output Leakage Current

-1.0

+1.0

0.0

GND~VI0:S.VCC

VIL

Input Low Voltage

-0.3

0.8

2.0

/.LA
V

VCC -2.0

VCC+0.3

2.0

0.4

0.25

4.0

10 =-1.0mA

2.0

VIH

Input High Voltage

VOL

Output Low Voltage

VOH

Output High Voltage

Input Capacitance@

8.0

5.0

VI = VCC or GND
f= 1MHz

Input/Output Capacitance@

10.0

6.0

VIO = VCC or GND
f = 1MHz

CIO

A.C.

ICCDR

MIN

TEMP = 250 C
VCC= 5.0V

2.4

10 = 2.0mA

@
@
@
@
@
@

TELOV

Chip Enable Access Time

300

170

TAVOV

Address Access Time

320

170

TELOX

Chip Enable Output Enable Time

100

TEHOZ

Ch ip Enable Output Disable Time

100

TGLOV

Output Enable Output Enable Time

100

TGHOZ

Output Enable Output Disable Time

100

TWLOZ

Write Enable Output Disable Time

100

TELEH

Chip Enable Pulse Negative Width

300

170

@)
@)

TEHEL

Chip Enable Pulse Positive Width

120

TAVEL

Address Set Up Time

TELAX

Address Hold Time

TWLWH

Write Enable Pulse Width

120

TWLEH

Write Enable Pulse Set Up Time

120

TELWH

Write Enable Pulse Hold Time

300

160

TDVWH

Data Set Up Time

120

TWHDZ

Data Hold Time

TWLDV
TELEL

Write Data Delay Time
Read or Write Cycle Time

100
420

50
240

ns
ns

20
20

@)
@)
@)
@)

NOTES:

All devices tested at worst case limits. Room temp., 5 volt data provided for Information-not guaranteed.
Operating Supply Current (lCCOP) Is proportional to Operating Frequencv. Example: Typical

Capacitance sampled and guaranteed-not 100% tested.
AC test conditions: Inputs-TRISE >= TFALL::; 20nsec; Output-C load = 50pF. All timing measured at
1.5V reference level.

ICCOP = 5mA/MHz.

3-32

Specifications HM-6505-5
ABSOLUTE MAXIMUM RATINGS

OPERATING RANGE

Supply Voltage (VCC - GND)

-O.3V to +8.0V

Input or Output Voltage Applied

(GND -O.3V)
to (VCC +O.3V)

Storage Temperature

Operating Supply Voltage
Commercial

4.5V to 5.5V

Operating Temperature
Commercial

OOC to +75 0 C

-650 C to +150 0 C

ELECTRICAL CHARACTERISTICS
TEMP& VCC=
OPERATING
RANGE
PARAMETER

SYMBOL
ICeSB

Standby Supply Current

ICCOP

Operating Supply Current

MIN

(!)
TEMP = 250C
VCC = 5.0V

MAX

TYPICAL

UNITS

TEST CONDITIONS

500

100

p.A

10 = 0
VI = VCC or GND

f = lMHz, 10 = 0

500

J.lA

VI = VCC or GND

D.C.

ICCDR

Data Retention Supply Current

VCCDR

Data Retention Supply Voltage

1.4

Input Leakage Current

-10.0

+10.0

± 0.5

p.A

GND$;VIS,VCC

IIOZ

Input/Output Leakage Current

-10.0

+10.0

±0.5

GND$; VIO$;VCC

VIL

Input Low Voltage

-0.3

0.8

2.0

J.lA
V

VCC -2.0

VCC+0.3

2.0

0.4

0.25

4.0

10 = -O.4mA

VIH

Input High Voltage

VOL

Output Low Voltage

VOH

Output High Voltage

CI
CIO

A.C.

2.0

10 = 0, VCC = 2.0
VI = VCC or GND

2.4

10 = 1.6mA

Input Capacitance@

8.0

5.0

VI = VCC or GND
f= lMHz

I nput/Output Capacitance@

10.0

6.0

VIO = VCC or GND
f= lMHz

TELQV

Chip Enable Access Time

350

200

TAVQV

Address Access Time

370

200

@
@

TELQX

Chip Enable Output Enable Time

100

@
@
@

TEHQZ

Chip Enable Output Disable Time

TGLQV

Output Enable Output Enable Time

TGHQZ

Output Enable Output Disable Time

100

TWLQZ

Write Enable Output Disable Time

100

TELEH

Chip Enable Pulse Negative Width

350

200

TEHEL

Chip Enable Pulse Positive Width

150

100

TAVEL

Address Set Up Time

TELAX

Address Hold Time

TWLWH

Write Enable Pulse Width

150

100

@
@
@

TWLEH

Write Enable Pulse Set Up Time

150

100

TELWH

Write Enable Pulse Hold Time

350

180

TDVWH

Data Set Up Time

150

100

@
@
@

TWHDZ

Data Hold Time

TWLDV

Write Data Delay Time

100

@
@
@
@

TELEL

Read or Write Cycle Time

500

320

NOTES:

All devices tested at worst case limits. Room temp., 5 volt data provided for Information-not guaranteed.
Operating Supply Current (lCCOP) is proportional to Operating Frequency, Example: Typical

@
@)

ICCOP = 5mA/MHz.
Capacitance sampled and guaranteed-not 100% tested.
AC test conditions: Inputs-TRISE = TFALL = 20nsec; Qutput-C load
1.5V reference level.

3-33

= 50pF. All timing measured at

Read Cycle

W--4---~~---4-------------+------+----------------

REFER:~~:---------1I'----+--------t-------f---+----+----+----1

TRUTH TABLE
INPUTS

TIME
REFERENCE

-1

L
L

MEMORY DISABLED
CYCLE BEGINS, ADDRESSES ARE LATCHED
OUTPUT ENABLED

X
X
X

Z
Z
X

L
L
f
H

H
H
H
H

X
X

V
V
Z

PREPARE FOR NeXT CYCLE (SAME AS -1)

CYCLE ENOS, NEXT CYCLE BEGINS (SAME AS OJ

2
3

FUNCTION

OUTPUT VALID
READ ACCOMPLISHED

(T = 2). W must remain high throughout the read cycle.
After the data has been read,
may return high (T = 3).
This will force the output buffers into a high impedance
mode at time (T = 4). G is used to disable the output
buffers when in a logical "1" state ( T = -1, 0, 3, 4, 5).
After (T = 4) time, the memory is ready for the next cycle.

The address information is latched in the on chip registers by the falling edge of 1: (T = 0)' minimum address
set up and hold time requirements must be met. After
the required hold time, the addresses may change state
without affecting device operation. During time (T = 1).
the outputs become enabled but data is not valid until time

-r

Write Cycle

",l

. ~;;;;~<»>:'~

III

TELEL

-----t-:

TAVEL

NEXT ADD

'I
T.HEL ~--I

)'
w
TELWH

TOVWH

lWHDX

I VALID DATA IN !

G HIGH
TIME
REFERENce

I
-1

TRUTH TABLE
TIME

REFERENCE

-1

L
L
f
H

2
3
4
5

INPUTS

X
X

H
H
H
H
H
H
H

X
X
X
V
X
X
X

L
f
H

X
X

X
X
X

X
V

FUNCTION
MEMORY DISABLED
CYCLE BEGINS, ADDRESSeS ARE LATCHED
WRITE PERIOD BEGINS
DATA IN IS WRITTEN
WA ITE COMPLETED

PREPARE FDA NEXT CYCLE {SAME AS-1/
CYCLE ENDS, NEXT CYCLE BEGINS (SAME AS 0)

to the E rising edge. The write operation is terminated by
the first rising edge of IN (T = 2) or E (T = 3). After the
minimum E high time (TEHELl, the next. cycle may
begin.
If a series of consecutive write cycles are to be
performed, the W line may be held low until all desired
locations have been written.
In this case, data setup
and hold times must be referenced to the rising edge of E.

The write cycle is initiated on the falling edge of E (T = 0),
which latches the address information in the on chip
If a write cycle is to be performed where the
registers.
output is not to become active, G' can beheld high (inactive).
TDVWH and TWHDX must be met for proper
device operation regardless of G. If E and IT fall before W
falls (read mode), a possible bus conflict may exist.
If
E rises before IN rises, reference data setup and hold times

3-34

Read Modify Write Cycle

G----~

REFER:~::---+--+-----1---+----+------1---1--~-~--TRUTH TABLE
TIME
REFERENCE.
-1
0
1

2
3
4
5
6
7

INPUTS

DATA I/O

"\.

H
H
H
L
f
H

H
H
L
L
H
H
H
H
H

Z
Z

L
L
L
L
f
H

"\.

v
X
X
X
X

x
X
V

FUNCTION
MEMORY DISABLED
CYCLE BEGINS, ADDRESSES ARE LATCHED
READ MODE, OUTPUT ENABLED (W = HIGH, G = LOW)
READ MODE, OUTPUT VALID
WRITE MODE, OUTPUT HIGH Z
WAITE MODE, DATA IS WRITTEN
WRITE COMPLETED
PREPARE FOR NEXT CYCLE (SAME AS -1)
CYCLE ENOS, NEXT CYCLE BEGINS (SAME AS OJ

x
V

Z
V

Z
Z
Z

W may return high. The information just written may now

If the pulse width ofW is relatively short in relation to that
of E, a combination read write cycle may be performed.
If W remains high for the first part of the cycle, the output
will become active during time (T ; 1) provided G is
low.
Data out will be valid during time (T = 2). After
the data is read, W can go low. After minimum TWLWH,

be read or E may return high, disabling the output buffer
and preparing the device for the next cycle. Any number
or sequence of read-write operations may be performed
while E is low providing all timing requirements are met.

NOTES:
In the above descriptions, the numbers in parentheses (T=n), refer to the respective timing diagrams. The numbers
are located on the time reference line below each diagram. The timing diagrams shown are only examples and are
not the only valid method of operation.

Chip Enable (E) must be held high during data retention; within vee + 0.3V to vec - 0.3V.

On RAMs which have selects or output enables (e.g. S, ~'l, one of the selects or output enables should be
held in the deselected state to keep the RAM outputs high impedance, minimizing power dissipation.

All other inputs should be held either high (at CMOS VCe) or at ground to minimize ICeDR.

Inputs which are to be held high (e.g.
power up and power down transitions.

The RAM can begin operation one TEHEL after VCC reaches the minimum operating voltage (4.5 volts!.

must be kept between vee + 0.3V and 70% of vce during the

DATA RETENTION TIMING

-----...1""'. . . . .- - - - DATA RETENTION MODE - - - - - 1 / " - - - - - VCC~2.0V

VCC±O.3V

3-35

HARRIS

HM-6508

SEMICONDUCTOR
PRODUCTS DIVISION

1024 x 1 CMOS RAM

Features

•

•
•
•

•
•
•
•
•

Pinout

LOW STANDBY POWER
LOW OPERATING POWER
FAST ACCESS TIME
DATA RETENTION VOLTAGE
TTL COMPATIBLE IN/OUT
HIGH OUTPUT DRIVE - 2 TTL LOADS
HIGH NOISE IMMUNITY
ON CHIP ADDRESS REGISTER
MILITARY TEMPERATURE RANGE
INDUSTRIAL TEMPERATURE RANGE
THREE-STATE OUTPUTS
16 PIN PACKAGE FOR HIGH DENSITY

TOP VIEW

50llWMAX
20mW/MHz MAX
180n58c MAX
2.0 VOLTS MIN

Description

A - Address Input
Chip Enable

E-

Data Input

Q -

Data Output

W - Write Enable

The HM-6508 is a 1024 by 1 static CMOS RAM fabricated using selfaligned silicon gate technology. Synchronous circuit design techniques are
employed to achieve high performance and low power operation.

logic Symbol
E +vccW

On chip latches are provided for address allowing efficient interfacing with
microprocessor systems. The data output buffers can be forced to a high
impedance state for use in expanded memory arrays.

AO
AI

A2
AJ
A4
A5
A6
A7
AS
A9

The HM-6508 is a fully static RAM and may be maintained in any state
for an indefinite period of time. Data retention supply voltage and supply
current are guaranteed over temperature.

o
Q

IIIII________________________________________________~____________

-_-_G_N_D_________ .

Functional Diagram
AS
A6
A7

AS
A9

32x 32
MATRIX

Do-------t
G

GATED
COLUMN
DECODER
AND DATA 1/0

w
L

LATCHED
ADDRESS
REGISTER

AO AI A2 A3 A4

CAUTION: These devices are sensitive to electrostatic discharge.
Users should follow IC Handling Procedures specified on pg. 1- 6.

3-36

ALL LINES POSITIVE LOGIC - ACTIVE HIGH
THREE STATE BUFFERS:
A HIGH-OUTPUT ACTIVE
ADDRESS REGISTER AND DECODERS:
LATCH ON RISING EDGE OF L
GATE ON RISING EDGE OF G

Specifications HM-65088-2IHM-65088-9
ABSOLUTE MAXIMUM RATINGS

OPERATING RANGE

Supply Voltage - (vee -GND)

-O.3V to +8.0V

Input or Output Voltage Applied

(GND -O.3V)
to (Vee +O.3V)

Operating Supply Voltage -vee
Military (-2)
Industrial (-9)
Operating Temperature
Military (-2)
Industrial (-9)

-650 e to +150o e

Storage Temperature

4.5V to 5.5V
4.5V to5.5V

-55 0 e to +125 0 e
-400e to +85 0 e

ELECTRICAL CHARACTERISTICS

TEMP. & VCC =
OPERATING
RANGE
SYMBOL

D.C.

A.C.

PARAMETER

MIN

MAX

TEMP. = 250 C
VCC= 5.0V
TYPICAL

-- OXO
OXI
>-- OX2
!-- OX3
' - - OX4
GNO

.......-

li
OXll
OX10
OX9
OX8
OX7
OX6
OX6

L~
es
vee

LXMAR
MEMSEl
XTe

3-46

STR
AOR
OXO
OXI
OX2
OX3
OX4
GNO

MSEL
OXll
OX10
OX9
OX8
OX7
OX6
OX6

~
CS
VCCSTR
AOR
OXO
OXI
OX2
OX3
OX4
-GNO

MSEL c-OXll ~
OX10
OX9
OX8
OX7

r-r-r-r-oxe r-OX5 r--

low Voltage Data Retention

HAR R IS CMOS RAMs are designed with battery backup in mind. Data retention voltage and supply current are
guaranteed over temperature. The following rules insure data retention:
1.

Chip Enable (~) must be held high during data retention; within VCC + 0.3V to VCC - 0.3V.

On RAMs which have selects or output enables (e.g. S,
one of the selects or output enables should be
held in the deselected state to keep the RAM outputs high impedance, minimizing power dissipation.

All other inputs should be held either high (at CMOS VCC) or at ground to minimize ICCDR.

Inputs which are to be held high (e.g.
power up and power down transitions.

The RAM can begin operation one TEHEL after VCC reaches the minimum operating voltage (4.5 volts).

en,

must be kept between VCC + 0.3V and 70% of VCC during the

DATA RETENTION TIMING

- - - -.......1"""1----- DATA RETENTION MODE ----~ , . . . - - - - - vee

~2.0V

vee±O.3V

III

3-47

lEI

HARRIS

HM-6513

SEMICONDUCTOR
PRODUCTS DIVISION
A DIVISION OF HARRIS CORPORATION

512 x 4 CMOS RAM

Features

•

•
•

•

•
•

•
•
•

•
•

Pinout

LOW POWER STANOBY

250IlWMAX.

LOW POWER OPERATION

TOP VIEW

35mWIMHz MAX.

DATA RETENTION

@2.0VMIN.

TTL COMPATIBILITY INPUT/OUTPUT

vce

COMMON DATA IN/OUT

A7
AS

THREE STATE OUTPUTS
FAST ACCESS TIME

300nsec MAX.

INDUSTRIAL OR COMMERCIAL TEMPERATURE RANGE
1B PIN PACKAGE FOR HIGH DENSITY
ON CHIP ADDRESS REGISTER
PINOUT ALLOWS UPGRADE TO

HM~514

DOO
DOl

D02

D03

Vii

Description

Logic Symbol

The HM-6513 is a 512 x 4 static CMOS RAM fabricated using self aligned
silicon gate technology. The device utilizes synchronous circuitry to
achieve high performance and low power operation.

E vee Vii

On chip latches are provided for the addresses allowing efficient interfacing with microprocessor systems. The data output can be forced to a high
impedance state for use in expanded memory systems.

AO
Al
A2
A3
A4
A5
A6
A7
AS

The HM-6513 is a fully static RAM and may be maintained in any state
for an indefinite period of time. Data retention supply voltage and supply
current are guaranteed over temperature.
The HM-6513 is supplied in two versions, the HM-6513H and the HM6513L. The H or L is used to designate the logic level to be connected
to the Y input. If a HM-6513H is procured the user must connect the
input to VCC in the system. If a HM-6513L is used the Y input must be
connected to system ground.

Functional Diagram

Al
AO

DOO
DOl
D02
D03

A-Address Input
E -Chip Enable

W-Write Enable
DQ -Data In/Out
Y -Hard Wired Input

A7
A6

GATED

DECODER

ROW

64x32
MATRIX

A4
A3

GATED COLUMN
DECODER
AND DATA

INPUT/OUTPUT

D<:::::

AOO=====><~_ _ _ _ _ _A_O_O_RE_SS_V_A_Ll_O_ _ _ _ _ _ _

low Voltage Data Retention
HAR R IS CMOS RAMs are designed with battery backup in mind. Data retention voltage and supply current are
guaranteed over temperature. The following rules insure data retention:'
1.

Chip Enable (~) must be held high during data retention; within VCC + 0.3V to VCC - 0.3V.

On RAMs which have selects or output enables (e.g. S,
one of the selects or output enables should be
held in the deselected state to keep the RAM outputs high impedance, minimizing power dissipation.

All other inputs should be held either high (at CMOS VCC) or at ground to minimize ICCDR.

Inputs which are to be held high (e.g.
power up and power down transitions.

The RAM can begin operation one TEHEL after VCC reaches the minimum operating voltage (4.5 volts).

en,

E) must be kept between VCC + 0.3V and 70% of VCC during the

DATA RETENTION TIMING

_ _ _ _ _.1-0------ DATA RETENTION MODE - - - - . - ; ~-----Vee~2.0V

--'1///

vee ± O.3V

3-61

•

HARRIS
SEMICONDUCTOR
PRODUCTS DIVISION

HM-6515

A DiVISION OF HAAAIS CORPORATION

Advance Information

1K x 8 CMOS RAM

Features

•

•
•
•
•
•
•
•
•
•

•

Pinout
SmWMAX.

LOW POWER STANDBY
LOW POWER OPERATION

TOP VIEW

SOmW/MHz MAX.

FAST ACCESS

240nsMAX.

INDUSTRY STANDARD PINOUT
SINGLE SUPPL Y

5 VOLT VCC

A4
A3

TTL COMPATIBLE
STATIC MEMORY CELLS

A'
OQ7

2 STD. TTL LOADS

HIGH OUTPUT DRIVE

OOB

ON CHIP ADDRESS LATCHES

DOS
004

00'

EASY MICROPROCESSOR INTERFACING
GNO

WIDE TEMPERATURE RANGE

Description

The HM-6515 is a CMOS 1024 x 8 Static Random Access Memory. Extremely
low power operation is achieved by the use of complementary MaS design techniques. This low power is further enhanced by the use of synchronous circuit
techniques that keep the active (operating) power low, and also give fast access
times. The pinout of the HM-6515 is the popular 24 pin, 8 bit wide standard
which allows easy memory board layouts, flexible enough to accomodate a variety of PROMs, RAMs, EPROMs and ROMs.

G
W

The HM-6515 is ideally suited for use in microprocessor based systems. The
byte wide organization simplifies the memory array design, and keeps operating
power down to a minimum because only one device is enabled at a time. The
address latches allow very simple interfacing to recent generation microprocessors
which employ a multiplexed address/data bus, such as the 8085. The convenient output enable control also simplifies multiplexed bus interfacing by allowing the data outputs to be controlled independent of the chip enable.

W
G

E
Y

003

Address Input
Data Input/Output
Chip Enable
Output Enable
Write Enable
Hard Wired Input

logic Symbol
+VCC

•

000

A'
A2
A3

DO'
002
003
004
DOS
OOB

A'
AS
A6
A7
AS
A9
Y

The HM-6515 is supplied in two versions, the HM-6515H and the HM-6515L.
The H or L is used to' designate the logic level to be connected to the Y input.
If an HM-6515H is procured the user must connect the Y input to VCC in the
system. If an HM-6515L is used the Y input must be connected to system GND.

":"

Functional Diflgram
AO
All

AS
AS

1i
ALL LINES POSITIVE LOGIC ACTIVE HIGH

THREE STATE BUFFERS:
A HIGH - - OUTPUT ACTIVE
ADDRESs LATCHES AND GATED
DECODERS:
LATCH ON RISIrJG EDGE OF L
GATE ON RISING EDGE OF G

CAUTION: These devices are sensitive to electrostatic discharge.
Users should follow IC Handling Procedures specified on pg. 1-6.

3-62

Specifications HM-6515-9
ABSOLUTE MAXIMUM RATINGS
Supply Voltage

-vee

OPERATING RANGE
+8.0V

Input or Output Voltage Applied

Operating Supply Voltage
Industrial (-9)

GND -O.3V
to vee +O.3V

4.5V to 5.5V

Operating Temperature Ranges:
-40 o e to +85 0 e

Industrial (-9)
-65 0 e to +150 oe

Storage Temperature

Input Rise/Fall Time

$,10J.ls

ELECTRICAL CHARACTERISTICS
TEMP. 8< VCC =
OPERATING RANGE
SYMBOL

D.C.

MIN

VCC=5.0V

TEST

MAX

TYP

UNITS

CONDITIONS

1.0

0.10

10=0
VI = VCC or GND

10.0

7.0

f=lMHz,IO=O
VI = VCC or GND

500

0.05

J.lA

10 = 0, VCC = 2.0
VI = VCC or GND

ICCSB

Standby Supply Current

ICCOP

Operating Supply Current

ICCDR

Data Retention Supply Current

VCCDR

Data Retention Supply Voltage

2.0

Input Leakage Current

-1.0

+1.0

0.0

J.lA

GND :5VI :5vcc

IIOZ

I nput/Output Leakage Current

-1.0

+1.0

0.0

J.lA

GND :5 VIO:5 VCC

VIL

Input Low Voltage

-0.3

0.8

2.0

VCC -2.0

VCC +0.3

2.0

0.40

0.35

4.0

10 = -1.0mA

8.0

5.0

VI = VCC or GND
f = lMHz

10.0

7.0

VIO= VCCorGND
f = lMHz

VIH

Input High Voltage

VOL

Output Low Voltage

VOH

Output High Voltage

CI
CIO

A.C.

PARAMETER

TEMP. = 25 0 C

Input Capacitance

2.4

Input/Output Capacitance

TELQV

Chip Enable Access Time

240

130

TAVQV

Address Access Time

250

130

TELQX

Chip Enable Output Enable Time

100

TWLQZ

Write Enable Output Disable Time

100

TEHQZ

Chip Enable Output Disable Time

100

TGLQV

Output Enable Output Enable Time

100

TGHQZ

Output Enable Output Disable Time

100

TELEH

Chip Enable Pulse Negative Width

240

130

TEHEL

Chip Enable Pulse Positive Width

150

TAVEL

Address Setup Time

TELAX

Address Hold Time

ns
ns

TWLWH

Write Enable Pulse Width

100

TWLEH

Write Enable Pulse Setup Time

100

TELWH

Write Enable Pulse Hold Time

240

130

TDVWH

Data Setup Time

100

TWHDZ

Data Hold Time

TWHEL

Write Enable Read Setup Time

TQVWL

Data Valid to Write Time

TWLDV

Write Data Delay Time

100

TELEL

Read or Write Cycle Time

390

200

10 = 3.2mA

@)
@)
@)
@)
@)
@)
@)
@)
@)
@)
@)
@)
@)
@)
@)
@)
@)
@)
@)
@)

NOTES:

---00
A

ALL LINES POSITIVE LOGIC - ACTIVE HIGH

Vi
A

LATCHED
ADDRESS
REGISTER

AO Al A2 A3 A4

CAUTION: These devices are sensitive to electrostatic discharge.
Usors should follow IC Handling Procedures specified on PQ. 1-6.

3-70

THREE STATE BUFFERS:
A HIGH ~OUTPUT ACTIVE
DATA LATCH:
L HIGH ~ D= 0
D LATCHES ON RISING EDGE OF L
ADDRESS REGISTERS AND DECODERS:
LATCH ON RISING EDGE OF L
GATE ON RISING EDGE OF G

Specifications HM-6518B-2IHM-6518B-9

ABSOLUTE MAXIMUM RATINGS

OPERATING RANGE

Supply Voltage - (Vee -GND)

-O.3V to +8.0V

Input or Output Voltage Applied

(GND -O.3V)
to (Vee +O.3V)

Storage Temperature

Operating Supply Voltage -vee
Military (-2)
Industrial (-9)
Operating Temperature
Military (-2)
Industrial (-9)

-65 0 C to +150 0 C

4.5V to 5.5V
4.5V to 5.5V

-55 0 C to +1250 C
-400 C to +850 C

ELECTRICAL CHARACTERISTICS

TEMP. & VCC =
OPERATING
RANGE
SYMBOL

MAX

TYPICAL

TES~

UNITS

CONDIT ONS

Standby Supply Current

0.1

f.1A

10= 0
VI = VCC or GND

ICCOP

Operating Supply Current (?)

1.5

f = 1 MHz, 10 = 0
VI = vqc or GND

ICCDR

Data Retention Supply Current

0.01

f.1A

VCC =2.0, 10 = 0
VI = VCC or GND

1.4

Input Leakage Current

-1.0

+1.0

0.0

f.1A

GND ~ VI ~ VCC

IOZ

Output Leakage Current

-1.0

+1.0

0.0

f.1A

GND ~VO~ VCC

VIL

Input Low Voltage

-0.3

0.8

2.0

VCC -2.0

VCC +0.3

2.0

0.4

0.2

= 3.2mA

4.5

= -O.4mA

Data Retention Supply Voltage

2.0

VIH

Input High Voltage

VOL

Output Low Voltage

VOH

Output High Voltage

Input Capacitance@

VI = VCC or GND
f = 1MHz

Output Capacitance@

VO= VCC or GND
f = 1MHz

180

100

180

120

40
40

@)
@)
@)
@)
@)
@)
@)
@)
@)
@)
@)
@)
@)
@)
@)
@
@)

TELQV

A.C.

MIN

11(

VALID

TEtH

~EHEL

..I'

'--

TWLEH

TELWH

TEHEL---';:

TELEH

TWLWH

~DVWH_

;JI(

. t=.,TWHDX

VALID DATA

HlaHZ
TSLWH

TWLSH

AEFEA:~~~ -----------!I-------l-------------+-----------ll-----+-------l--------l---,
TRUTH TABLE
TIME
REFERENCE
-1
0
1

INPUTS
W §(I) A

FUNCTION

Z
Z
Z
Z
Z
Z
Z

MEMORY DISABLED
CYCLE BEGINS, ADDRESSES ARE LATCHED
WRITE MODE HAS BEGUN
DATA IS WRITTEN
WRITE COMPLETED
PREPARE FOR NEXT CYCLE (SAME AS -1)
CYCLE ENDS, NEXT CYCLE BEGINS (SAME AS 0)

-...... x x
L L L
L.f L
.fX X
H X X
'-X X

2
3
4
5

NOTES:

--r<.

ii
il

CAUTION: These devices are sensitive to electrostatic discharge.
Users should follow IC Handling Procedures specified on pg. 1- 6.

3-82

DOl

002
003

ALL LINES POSITIVE LOGIC - ACTIVE HIGH

000

The HM-6561 is pin for pin replaceable with the HM-8661, a 256 x 4
CMOS PROM. This allows a single memory board design with any organization of RAM and PROMs .

.5'0-----1
.,'0-----1

Write Enable
DQ - Data In/Out

logic Symbol

Functional Diagram

W-

Specifications HM-6561B-2IHM-6561B-9
ABSOLUTE MAXIMUM RATINGS

OPERATING RANGE

Supply Voltage - (Vee - GND)

-O.3V to +8.0V

Input or Output Voltage Applied

(GND -O.3V)
to (Vee +O.3V)

Storage Temperature

Operating Supply Voltage -vee
Military (-2)
Industrial (-9)
Operating Temperature
Military (-2)
Industrial (-9)

-650 e to +150 0 e

4.5V to 5.5V
4.5V to 5.5V

-55 0 e to +125 0 e
-40 0 e to +850 e

ELECTRICAL CHARACTERISTICS
TEMP. & vcc =
OPERATING
RANGE
SYMBOL

D.C.

MIN

MAX

TYPICAL

UNITS

TEST
CONDITIONS

ICCSS

Standby Supply Current

0.1

IJ.A

10=0
VI = VCC or GND

ICCOP

Operating Supply Current@

1.5

f = 1MHz, 10 = 0
VI = VCC or GND

ICCDR

Data Retention Supply Current

0.01

IJ.A

VCC = 2.0, 10 = 0
VI=VCCorGND

VCCDR

Data Retention Supply Voltage

2.0

104

Input Leakage Current

-1.0

+1.0

0.0

IJ.A

GND ~ VI ~ VCC

IIOZ

Input/Output Leakage Current

-1.0

+1.0

0.0

GND ~VIO~ VCC

VIL

Input Low Voltage

-0.3

0.8

2.0

IJ.A
V

VCC -2.0

VCC +0.3

2.0

0.4

0.2

=1.6mA

4.5

= -Oo4mA

VIH

Input High Voltage

VOL

Output Low Voltage

VOH

Output High Voltage

Input Capacitance@

VI = VCC or GND
f = 1MHz

Input/Output Capacitance@

VIO = VCC or GND
f = 1MHz

220
220
120
120
120

120
110

ns
ns
ns

CIO

TELOV
TAVOV
TSLOX
TWLOZ
TSHOZ
TELEH
TEHEL
TAVEL
TELAX

A.C.

PARAMETER

TEMP. = 250 C
VCC =5.0V

TDVWH
TWHDX
TWLDV
TWLSH
TWLEH
TSLWH
TELWH
TWLWH
TWLSL
TSHWH
TELEL

NOTES:

Ch ip Enable Access Time
Address Access Time
Chip Select Output Enable Time
Write Enable Output Disable Time
Chip Select Output Disable Time
Chip Enable Pulse Negative Width
Chip Enable Pulse Positive Width
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Write Data Delay Time
Chip Select Write Pulse Setup Time
Chip Enable Write Pulse Setup Time
Chip Select Write Pulse Hold Time
Chip Enable Write Pulse Hold Time
Write Enable Pulse Width
Early Output High Z Time
Late Output High Z Time
Read or Write Cycle Time

2.4

220
100
0
40

50
50
50
120
50
-10

60
60

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

60
-10

ns
ns

-10
170

ns
ns

20
50
0
50
60
60

100
0
120
120
120
120
120
120
0
0
320

@)
@)
@)
@)
@)
@)
@)
@)
@)
@)
@)
@)
@)
@)
@)
@)
@)
@)
@)
@)

All devices tested at worst case limits. Room temp., 5 volt data provided for information - not guaranteed.
Operating Supply Current (lCCOP) is proportional to Operating Frequency. Example: Typical ICCOP = 1.5mA/MHz.
Capacitance sampled and guaranteed - not 100% tested.
AC Test Conditions: Inputs - TRISE = TFALL = 20nsec; Outputs - CLOAD = 50pF. All timing

measurements at 1 .5V reference level.

3-83

•

Specifications HM-6561-2IHM-6561-9
ABSOLUTE MAXIMUM RATINGS

OPERATING RANGE

Supply Voltage -(vee - GND)

-O.3V to +8.0V

Input or Output Voltage Applied

(GND -O.3V)
to (Vee +O.3V)

Operating Supply Voltage -vee
Military (-2)
Industrial (-9)
Operating Temperature
Military (-2)
Industrial (-9)

-650 e to +150 oe

Storage Temperature

4.5V to 5.5V
4.5V to 5.5V

-550e to +1250 e
-4ooe to +85 0 e

ELECTRICAL CHARACTERISTICS
TEMP. & vcc =
OPERATING
RANGE
SYMBOL

D.C.

A.C.

TEST
CONDITIONS

MAX

TYPICAL

UNITS

0.1

Il A

10=0
VI = VCC or GND

1.5

f = 1 MHz, 10 = 0

0.01

Il A

ICCSB

Standby Supply Current

ICCOP

Operating Supply Current

ICCDR

Data Retention Supply Current

VCCDR

Data Retention Supply Voltage

2.0

1.4

I nput Leakage Current

-1.0

+1.0

0.0

JlA

GND ~VI ~ VCC

IIOZ

Input/Output Leakage Current

-1.0

+1.0

0.0

GND ~ VIO ~ VCC

VIL

Input Low Voltage

-0.3

0.8

2.0

JlA
V

VCC -2.0

VCC+0.3

2.0

0.4

0.2

=1.6mA

4.5

= -O.4mA

•

MIN

PARAMETER

TEMP. = 25 0 cCD
VCC= 5.0V

o---+-t-------Q

PC>--------~LJ----~
00

IPROGRAMMING ONL VI

CAUTION: These devices are sensitive to electrostatic discharge.
Users should follow Ie Handling Procedures specified on pg. 1- 6.

3-104

00
01
02

Specifications HM-6611-2IHM-6611-9

ABSOLUTE MAXIMUM RATINGS

OPERATING RANGE

Supply Voltage (vee - GND)

-O.3V to +8.0V

Input or Output Voltage Applied

(GND -O.3V)
to (Vee +O.3V)

Storage Temperature

Operating Supply Voltage -vee
Military (-2)
Industrial (-9)
Operating Temperature
Military (-2)
Industrial (-9)

-65 0 C to +1500 C

4.5V to 5.5V
4.5V to 5.5V

-55 0 C to +125 0 C
-400 C to +85 0 e

ELECTRICAL CHARACTERISTICS

TEMP. & vcc =
OPERATING
RANGE
SYMBOL
ICCSB

Standby Supply Current

ICCEN

Enabled Supply Current

D.C.

Input leakage Current

MIN

TYPICAL

UNITS

100

IlA

VI = VCC or GND
S=VCC

VI = VCC or GND
S=GND,IO =0

-1.0

+1.0

0.0

IlA

GND'::;:VI'::;:VCC

±0.1

IlA

GND~VO~VCC

@
@

10Z

Output leakage Current

-1.0

+1.0

Input low Voltage

-0.3

0.8

2.0

VIH

Input High Voltage

VCC2.0

VCC+
0.3

2.0

VOL

Output low Voltage

0.4

0.3

VOH

Output High Voltage

2.4

@@)

I nput Capacitance

@@)

4.0

10 = -1.0mA

5.0

VI = VCC or GND
f = 1 MHz

10.0

6.0

VO = VCC or GND
f = 1MHz

Output Capacitance

TAVQV

Address Access Time

450

300

TSlQV

Ch ip Select Access Time

500

350

150

TSlQX

Chip Select Output Enable Time
Chip Select Output Disable Time

10 = 2.0mA

B.O

TSHQZ

TEST
CONDITIONS

MAX

Vll

A.C.

PARAMETER

= 25 0 C<:D
vcc= 5.0V

TEMP.

®
®
®
®

NOTES:

All devices tested at worst case limits.

ICCEN is proportional to the number of unblown fuses per word addressed. If all four fuses in the word addressed are
blown ICCEN ~ ICCSB.

Except

Room temperature 5 volt data provided for information - not guaranteed.

Program Enable is used only during programming and its characteristics are accounted for in the program-

ming specifications.

Capacitance is sampled and guaranteed, but not 100% tested.

AC test conditions:

Inputs - TRISE = TFAll = 20nsec; Outputs - ClOAD = 50pF; Timing measured at 1.5V

reference level.

3-105

•

Specifications

HM-6611~5

OPERATING RANGE

ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC - GND)

-O.3V to +8.0V

Input or Output Voltage Applied

Operating Supply Voltage -VCC
Commercial

4.5 to 5.5V

(GND -O.3V)
to (Vee +O.3V)

Storage Temperature

Operating Temperature
Commercial

ooC to 75 0 C

-65 0 C to +150 0 C

ELECTRICAL CHARACTERISTICS

TEMP. & vcc =
OPERATING
RANGE
SYMBOL
ICCSB

Standby Supply Current

ICCEN

Enabled Supply Current

lEI
A.C.

@
@

TEST
CONDITIONS

MAX

TYPICAL

UNITS

1.0

0.2

VI = VCC or GNO
s= VCC

VI = VCC or GNO
S= GNO,IO = 0

-5.0

+5.0

±0.5

JlA

GNO~VI~VCC

-10.0

+10.0

±0.5

JlA

GNO~VO";VCC

Input Low Voltage

-0.3

O.B

2.0

VIH

Input High Voltage

VCC 2.0

VCC+
0.3

2.0

VOL

Output Low Voltage

0.4

0.3

VOH

Output High Voltage

Input Leakage Current

D.C.

MIN

PARAMETER

TEMP. = 25 0 C
VCC= 5.0V

10Z

Output Leakage Current

VIL

2.4

10 = 1.0mA

4.0

10 =-0.5mA

8.0

5.0

VI = VCC or GNO
1= 1MHz

10.0

6.0

va = VCC or GNO
1= 1MHz

Address Access Time

650

400

TSLQV

Chip Select Access Time

800

500

TSLQX

Chip Select Output Enable Time

200

TSHQZ

Chip Select Output Oisable Time

200

@@)

Input Capacitance

Output Capacitance

TAVQV

@@)

®
®
®
®

NOTES:

OIC

VALID DATA

TRUTH TABLE
INPUTS
S
A

OUTPUT
FUNCTION

DEVICE DESELECTED, OUTPUT
HIGH IMPEDANCE
DEVICE SELECTED, DATA OUTPUT
VALID FOR ADDRESS PRESENT

The timing waveforms shown describe only one possible
method of operation. The device will output valid data
corresponding to the address input one chip select access
time (TSLOV) after it is selected. If the device is already
selected and the address is changed to a new val id address
the corresponding data will be available at the outputs no

later than one address access time (TAVOV) later. Thus,
this device can be selected each time a data word is desired,
or it can be left selected to access a number of data words.
If the system data bus allows, the device may be permanently selected for ease of use.

Programming
BACKGROUND INFORMATION
The HM-6611 is a 256 x 4 eM as Programmable ReadOnly Memory. It is programmed by the controlled application of programming pulses to selected memory cells.
These pulses permanently alter the logic state of the memory cell. The memory array is manufactured with each
cell set to the high or "1" logic state. The user may select
any memory cell and permanently change its logic state
to a "0" or low by programming.
Programming is accomplished by addressing the word to be
programmed, applying the programming pulses, and verifying the data programmed. The verification is performed
at high voltage (Vee) during the programming sequence,
and at low voltage after all programming is completed.

logic levels (VOH

70% vee, VOL

Address buffers able to maintain high state voltages
of ~ 70% of vee at both high and low vee, * and low
state voltages 5 20% vee at both high and low vee.

Timing and control logic suitable to sequence the
required functions.
*Never allow any input to rise more than 0.3 volts
above vee.

PROGRAMMING PROCEDURE:
OVERALL:
1.

Address and program word.

Verify data output at high vee (10.5V

Programming power supply is a negative 20.0V supply
(:!:1.0V), switchable between -20V, OV, +3.5V, and
+10.5V. This supply must be able to deliver 400 mA
average, and lA peak currents at -20V. Less than 1mA
output current is required at OV, +3.5V, and at +10.5V.
The slew rate between +10.5V and -20V must be controlled within 1 0011 sec to 40011 sec.
Data output load devices (switchable) capable of
sinking 10mA from the output pin without rising
more than 0.6 volts above ground. Open collector.
open drain or discrete devices with resistive pullups of 4.7K
47K is the recommended implementation.

20% vee).

PROGRAMMING SYSTEM CHARACTERISTICS:
Power source for the device to be programmed (Vee)
variable from +3.0 to +11.0 volts, current capability
of 500mA averag·e and 1 amp dynamic currents.

Data output sensing devices capable of sensing valid

3-107

± .5V)

If device fails to verify, repeat program - verify
sequence (reject device as defective after 8 programming attempts at anyone word).

If device passes verify, repeat programming sequence twice more then return to step 1 to program the next word.

If device passes verify at the last location to be
programmed continue to step 3.

Lower vee to 3.5 ± 0.5V and verify each location in
the matrix.
a.

If any location fails to verify, reject the device
as defective.

If all locations pass verify, the part is properly
programmed.

•

PROGRAMMING SEQUENCE FLOW CHART
3.

Initiate the P supply falling edge.

After the P supply has crossed zero (ground) going negative, enable the data output load devices of each output pin that is to be programmed (to become a low or
"0" logic state).

Disable the data output load 4 milliseconds (± 1msec)
after it was enabled (TQLQH).

The data output load devices must be disabled before
the P supply is allowed to cross zero (ground) on
its rising edge.

Invert AO for 500 nanoseconds, then return AO to its
original logic state.

Wait 500 nanoseconds or more (TPHQV).

Compare the output data with the desired data.
a.

If anyone bit fails to verify, program again starting at step 3. After 8 programming attempts at
anyone location, reject the device as defective. It
is acceptable to repulse all desired bits if anyone
bit does not program.

If all four bits verify, program the word twice
more (steps 3 thru 8 twice). Then return to step
1 to address the program the next word.

After steps 1 thru 9 are completed for each word to be
programmed:
10. Lower all inputs to ground.
11. Lower

vee to +3.5 volts ± .5 volts.
vec. *

12. Raise j5 to

13. Setup the address of the word to be verified. (High or
"1" or VIH inputs must be > 2.35 and < vee +0.3
volts). *

14. Wait 1 microsecond.
15. Compare the output data with the desired data.

PROGRAMMING STEPS:
INITIALIZE:

vce

~ +10.5V
p~vee

S ~ GND

± .5V

(not used during programming)

If any bit fails to verify, reject the device as
defective.

If all four bits verify, return to step 13 to verify
the next word.

Setup the address of the word to be programmed.

After steps 13 thru 15 are completed for each word in the
matrix, the device has been properly programmed.

Wait 500 nanoseconds or more (TAVPL).

* Never allow any input to rise more than 0.3 volts above

PROGRAM CYCLE TIMING TABLE

SYMBOL

PARAMETER

TAVPL

Address to Program Setup Time

TPLQL

Program Enable to Data Time

TAVQV

Address to Output Valid

TQLQH

Data Low Pulse Width

TQHPH

Data High to Program Disable Time

TAXAX

AO Inverted Time

TPHQV

Program Disable to Read Time

TPHAV

Program Disable to Address Invert (AO)

3-108

MIN

500
100
500
3.0
100
500
500
0

MAX

UNITS
ns
/-Is
ns

5.0

ms
/-Is
ns
ns
ns

vee.

PROGRAMMING CYCLE
VCC = 10.5V ± .5V
TAXAX

+10.5V

AO
GND
NEXT ADDRESS

+10.5V

AN
GND
+10.5V

------i

-20V

,~~~~~~~~[f~----~~~2~~~r----+--

DATA OUTPUT PIN NOT
GND..., TO BE PROGRAMMED

+10.5V

LOW VOLTAGE VERIFY CYCLE

vee = 3.5V ± O.5V
+3.5-----,
A PREVIOUS ADD
GND

NEXT ADDRESS

I------l/Ls---f-+3.5-------------"""'-

a
PREVIOUS DATA
GND--------------/

Y--l..J......- - - - - - - - - - -

EXAMPLE PROGRAMMING CIRCUIT

+VCC

INVERTAO

AO-S

4.7K

AO
A1
A2

DATA

A3
A4

:S R :S 47K

OPEN
COLLECTOR
DRIVERS

VCC

HM-6611

TO BE
Q2 ~-~~~I--~ ~---PROGRAMMED

A5
A6

D-

"::"

......-H--\

8:="""
D-

......-----DESIRED
DATA
L--------------PCONTROL

3-109

HARRIS

HM-6641

SEMICONDUCTOR
PRODUCTS DIVISION
A DIVISION OF HARRIS CORPORATION

512 x 8 CMOS PROM

Advance Information
Features

•
•
•
•

•
•
•
•
•
•
•

LOW POWE R STANDBY
LOW POWER OPERATION

Pinout
TOf'VIEW

500~WMAX.

vee

50mW/MHz MAX.

FAST ACCESS TIME

200nsMAX.

lIT
~

FIELD PROGRAMMABLE

A3
A2

POL YSILICON FUSE LINKS

1:"

TTL COMPATIBLE IN/OUT

Q1
Q6

POPULAR PINOUT LIKE BIPOLAR 7641

THREE STATE OUTPUTS

Q'
GNO '--_ _.r Q3

ADDRESS LATCHES INCLUDED ON CHIP

A Address Input

EASY MICROPROCESSOR INTERFACING

Q Data Output

WIDE TEMPERATURE RANGES

E
G

Chip Enable
Output Enable
P Program Enable
(P = Gnd. except when
programming)

Description
The HM-6641 is a 512 x 8 CMOS polysilicon fuse link Programmable Read
Only Memory in the popular 24 pin, byte wide pinout. Synchronous circuit
design techniques combine with CMOS processing to give this device high
speed performance with very low power dissipation.

•

logic Symbol

On chip address latches are provided, allowing easy interfacing with recent
generation microprocessors that use multiplexed address/data bus structures,
such as the 8085. The output enable controls, both active low and active
high, further simplify microprocessor system interfacing by allowing output
data bus control independent of the chip enable control. The data output
latches allow the use of the HM-6641 in high speed pipelined architecture
systems, and also in synchronous logic replacemant functions.

p----------4"9'-mtQZ"v:<...z...;. <. ;~'" :-.: . ,:-.: . ,:-.:" "':>

REf~:Ee,.CE------'1---11-----+----I----tl-----+t-_it~,

TRUTH TABLE
TIME
REFERENCE
-1
0
1

INPUTS
E

...

X
V
X
X

H
L
L

2
3

..r

...

L
L
L
H
X

x
X
V

(SAME AS-1)

NOTE:

The HM-6661 Read Cycle is initiated
of E. This signal latches the input
chip registers. Minimum
must be met. After the
lines may change state
In order to read the output
The output data will be vali.~t"'l.,d!lll.

has output data latches that are controlled
On the rising edge of E the present data is latched
remains latched until E falls. Either or both Sl or S2
may be used to force the output buffers into a high im- .
pedance state.

Programming
BACKGROUND INFORMATION
The HM-6661 is a 256 x 4 CMOS Programmable ReadOnly Memory. It is programmed by the controlled application of programming pulses to selected memory cells.
These pulses permanently alter the logic state of the memory cell. The memory array is manufactured with each
cell set to the high or "1" logic state. The user may select
any memory cell and permanently change its logic state
to a "0" or low by programming.

output current is required at OV,+3.5V, and at +10.5V.
The slew rate between +10.5V and -20V must be controlled within 100j.l sec to 400llsec.
3.

Programming is accomplished by addressing the word to be
programmed, applying the programming pulses, and verifying the data programmed. The verification is performed
at high voltage (VCC) during the programming sequence,
and at low voltage after all programming is completed.

Data output load devices (switchable) capable of
sinking 10mA from the output pin without rising
more than 0.6 volts above ground. Open collector,
open drain or discrete devices with resistive pullups of 4.7K to 47K is the recommended implementation.

Data output sensing devices capable of sensing valid
logic levels (VOH ~ 70% VCC, VOL 5 20% VCC).

Address buffers able to maintain high state voltages
of ~ 70% of VCC at both high and low VCC, * and low
state voltages ~ 20% VCC at both high and low VCC.

Timing and control logic suitable to sequence the
required functions.

PROGRAMMING SYSTEM CHARACTERISTICS:
1.

Power source for the device to be programmed (VCC)
variable from +3.0 to +11.0 volts, current capability
of 500mA average and 1 amp dynamic currents.

Programming power supply is a negative 20.0V supply
(±1.0V), switchable between -20V, OV, +3.5V, and
+10,5V. This supply must be able to deliver 400 mA
average, and 1A peak currents at -20V. Less than 1 mA

*Never allow any input to rise more than 0.3 volts
above VCC.

3-118

PROGRAMMING PROCEDURE:
a. If anyone bit which was programmed fails to verify
as a low or VO L, program again starti ng at step 5.
After 8 programming attempts at anyone location
reject the device as defective. It is acceptable to repulse (TOLOH) all bits within a word if any bits do
not program.

OVERALL:
1.

Address and program word.

Verify data output at high vee (10.5V± .5V)

If device fails to verify repeat program - verify
sequence (reject device as defective after 8 programming attempts at anyone word).

If device passes verify repeat programming sequence twice more then return to step 1 to program the next word.

If device passes verify at the last location to be
programmed continue to step 3.

Lower vee to 3.5
the matrix.

± 0.5V

If any location fails to verify reject the device
as defective.

If all locations pass verify the part is properly
programmed.

PROGRAMMING STEPS:

12. Lower all inputs to ground.
13. Lower vee
+3.5 volts :!.:.0.5 volts.
Ie fp) to vee.'
14. Raise pr am~n
Set
the ad
the word to be verified. (High
'1" i n $ .
>2.35V and

NOTES:

.)
SYNC SE LECT actuates a Command sync for an input high
and Data sync for an input low.
SEND DATA is an active high output which enables the
external source of serial data.
SEND CLOCK IN is 2X the Encoder data rate.
ENCODER CLOCK is the input to the 6:1 divider.
Positive supply pin.

4-14

Encoder Operation
The Encoder requires a single clock with a frequency of
twice the desired data rate appl ied at the SClock input. An
auxiliary divide by six counter is provided on chip which
can be utilized to produce thl! SClock by dividing the
DClock.

During these sixteen periods the data should be clocked
into the SDlnput with every high-to-Iow transition of the
ESC @ - @). After the sync and Manchester II encoded
data are transmitted through the BOO and BZO tJutputs,
the Encoder adds on an additional bit which is the (odd)
At any time a low on Oi will
parity for that word
force both bipolar outputs to a high state but will not
affect the Encoder in any other way.

®.

The Encoder's cycle begins when EE is high during a falling
edge of ESC
This cycle lasts for one word length or
twenty ESC periods. At the next low-to-high transition of
the ESC, a high at SS input actuates a Command sync
or a low will produce a Data sync for that word
When
the Encoder is ready to accept data, the SD output will go
high and remain high for sixteen ESC periods @ - @) .

CD.

To abort th'e Encoder transmission a positive pulse must
be applied at MR. Any time after or during this pulse,
a low-to-high transition on SCI clears the internal counters
an initializes the Encoder for a new word.

®.

TIMING

!0!'!'!'!4!_!0!7!

!'.!'.!17!'.!'.!!!
~

SCI
ESC

--1

;rJ/J//AVALnll'//////l////dDO~1~~~.V//I/l//M

~~--------------~I

jjffij

IwU?////U/tOON.TCAR.I/!/U/!//ULb{ VU////u////I7u//J

_____________

tw///I//I/I/u/ll//////////////4
f

-----""T.

III

Decoder Operation
The Decoder requires a single clock with a frequency of
12 times the desired data rate applied at the DClock input.
The Manchester II coded data can be presented to the
Decoder in one of two ways. The Bo.l and BZI inputs
will accept data from a differential output comparator.
The UDI input can only accept non inverted Manchester II
coded data (e.g. from BZO of an Encoder).

The decoded data available at SDO is in a N RZ format.
The DSC is provided so that the decoded bits can get
shifted into an external register on every low-to-high
-@ .
transition for this clock

After all sixteen decoded bits have been transmitted@the
data is checked for odd parity. A high on VW output @)
indicates a successful reception of a word without any
Manchester or parity errors. At this time the Decoder is
looking for a new sync character to start another output
sequence.

The Decoder is free running and continuously monitors
its data input lines for a valid sync character and two valid
Manchester data bits to start an output cycle. When a
the type of sync is indicated
valid sync is recognized
by the CDS output. If the sync character was a command,
this output will go high
and remain high for sixteen
DSC periods @ , otherwise it will remain low. The TD
output will go high and remain high
@ while the
Decoder is transmitting the decoded data through SDO.

CD '
®

At any time in the above sequence a high input on DR
during a low-to-high transition of DSC will abort transmission and initialize the Decoder to start looking for
a new sync character.

®-

4-15

•

TIMING

10I'IZI

1-1·l

l'l

1,.1"1,.1,.1

DSC

BOI
." _-'-"":":';::::""L..
TO _ _ _ _ _ _ _ _ _ _......1

CDS _ _ _ _ _ _ _ _ _ _

L__

--1I:_:_:_:_:_:_:_:_:_:_:_:_:_-j~1 ~-----------------L--

Encoder Timing

rEId

-.J

ESC
SD _ _ _ _ _ _ _-Jr==~

___________

SC~
rEO

BOoORBZc5

Decoder Timing
NOTE: UI = O. FOR NEXT DIAGRAMS

~BITPERIOD
.01

BITPERIOD~

BIT PERIOD

r---

.FT D,::rJ//II//l7//l/j////Il//7///A
I•
I

ll- T03

T02

-l I- T03

F"TD,.f/l/j/l7////I/7/111////II/I//A
I
TD'
'1

DSC -----,
CDS

~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

TD~Fr--~------------------

COMMAND SYNC

PD,OW/ffbft//J////ff////////.1

BOI
I

T02

' ..... T03

:::;:rr- T03

1 TD'

B2I -FTD,>W/////I//////i////ift///IA
1

r---

DATA SYNC

BOI J"OTD,::t/lj/Zl

~>-TD3
B2I ~
W/f////////D
I-- TD4 - I - - TOS
---lI

ONE

TOS

ZERD

J
;r-:v.~'-TD3
0"'"'D'Jl
-----i-- TD.

I=TDi0f///7fl1///1/l7//A
I

ONE

S------L-____~r---

DSC---"~~_ _ _
TDB-tL-t:==
CDS---rl~=-

_ _ _ _ _ _ _ _ _ _ _ _ _ _ __

TO~
vw

I
D~~L__~~~~I===-----~

NOTE: BOI

UIJ.
1

TDZ
COMMAND SYNC

UIJ.
I
I

TD'
DATA SYNC

0; BZI

1 FOR NEXT DIAGRAMS

TD'

. Viff//ff//A

TD'

. VIff////I/A

TD.
~~~==~=====J~====~f=====~T~D;.======~I~'~T~D4~~~
T~~

UI J==TD4

ONE

ZERO

ONE

lONE

4-16

_____

~r---

T~S~~~_ _ _ _ _ _ _ _ _ ____

HARRIS

HD-6409

SEMICONDUCTOR
PRODUCTS DIVISION
A DIVISION OF HARRIS CORPORATION

CMOS Manchester
Encoder-Decoder (MED)
Features

Pinout
TOP VIEW

•

CONVERTER OR REPEATER MODE

•

INDEPENDENT MANCHESTER ENCODER AND DECODER OPERATION

•

ONE MEGABIT/SEC DATA RATE

BZI

•

LOW BIT ERROR RATE

BOI

BOO

•

DIGITAL PLL CLOCK RECOVERY

UDI

BZO

•

ON CHIP OSCILLATOR

VCC

SO/CDS

SDO

•

SINGLE POWER SUPPLY

•

LOW OPERATING POWER: 25mW AT 5 VOLTS

•

FULL INDUSTRIAL TEMPERATURE RANGE

•

20 PIN PACKAGE

Description
The HD-6409 Manchester Encoder-Decoder (M ED) is a high speed, low
power device manufactured using self-aligned silicon gate technology. The
device is for use in serial data communication, and can be operated in
either of two modes. In the converter mode, the MED converts Non
Return to Zero code (N RZ) into Manchester code and decodes Manchester
code into Non Return to Zero code. For serial data communication,
Manchester code does not have some of the deficiencies inherent in Non
Return to Zero code. For instance, use of the MED on a serial line eliminates DC components, provides clock recovery, and gives a relatively high
degree of noise immunity. Because the M ED converts the most commonly
used code (NRZ) to Manchester code, the advantages of using Manchester
code are easily realized in a serial data link.
In the Repeater mode, the MED accepts Manchester code input and
reconstructs it with a recovered clock. This is to minimize the effects of
noise on a serial data link. A digital phase lock loop generates the recovered clock. A maximum data rate of lMHz requires only 25mW of power.
Manchester code is used in magnetic tape recording and in fiber optic
communication, and generally is used where data accuracy is imperative.

ECLK

SRST

CTS

NVM

DCLK

RST

GND

Logic SymbolOx
Ix

55
Co
SO-CDS
ECLK

BOO
BZO
CTS

MS
RST
BOI
BZI
UDI

SDO
DCLK

i'JiiM
SRST

DECODER

Functional Diagram
NvM
BO'
Bli
UD'

BOO

BZo
C'fi

iAif
SD-COS

~~~~____________________________________-'~LK

L-~~-t-------------------------------------'OCL'

eo_---

0.5 x CR x tc
CR x tc

tc -10

50
(5 x fc)
(5 x fel

ns
ns
ns
ns
ns
ns
l/s
l/s

CL = 20pF for Co,
50pF otherwise

CONVERTER MODE

•

ENCODER SECTION
tCEl
tCE2
tCE3
tCE4
tCE5

SO Setup Time
SD Hold Time
SO to BZO Prop Delay
CTS Low to ECLK, BOO,
BZO Enabled
CTS High to ECLK,BoO,
BZO Disabled

ns
ns
DBP@
tc

3
0.5

40
1.S

DBP@
ns
DBP@

CL = SOpF

0.5

1.5

DBP@

CL = 50pF

40
70
3

DBP@)
ns
ns
DBP@

70
0

DECODER SECTION
tCDl
tCD2
tCD3
tcD4

UDI to SDO, NVM
DCLK to SDO, NVM
RS'FLow to DCLK, SDO, SRST,
iiiViiiiLow
RS'i' High to DCLK, SDO NVM
Enable

2.5

REPEATER MODE
tRl
tR2
tR3
tR4

UDI to BOO, BZO
ECLK to 'BZO
ECLK to SRSi'
UDI to SDO,N'i7iiii

2.S

NOT~3~S: CR _ Clock Rate, either 16X or 32X the data rate.
•

tc = l/fc
DBP - Data Bit Period, i.e. for CR = 16X, one DBP = 16 clock cycles
Guaranteed and sampled but not 100% tested.

4-20

Converter Mode
ENCODER OPERATION

"0" bits followed by a Command sync pulse. (i) A Command sync pulse is a three bit wide pulse with the first 1Y,
bits high followed by 1'1:. bits low. @ Serial NRZ data is
clocked into the encoder at SO/COS on the high to low
transition of ECLK during the command sync pulse. The
NRZ data received is encoded into Manchester II data and
transmitted out on BOO and BZO following the Command sync pulse. @) Following the synchronization sequence, input data is encoded and transmitted out continuously without parity check or word framing. Manchester
data out is inverted.

The encoder uses free running clocks at 1X and 2X the data
rate derived from the system clock IX for internal timing.
CTS is used to control the encoder outputs, ECLK, BOO and
BZO. A free running 1X ECLK is transmitted out of the
encoder to drive the external circuits which supply the
NRZ data to the MEO at pin SO/COS.
A low on CTS enables encoder outputs ECLK, BOO and
BZO, while a high on CTS forces BZO. BOO high and holds
ECLK low. When CTS goes from high to low CD , a synchronization sequence is transmitted out on BOO and BZO.
A synchronization sequence consists of eight Manchester

ECLK

,
4---+-----------------~nuru:

I-O.----EIGHT ..0·... --~.~.OCOMMAND
~.Y:;;;N;;;C=-to

~ SYNCHRONIZATION SEQUENCE ~

DECODER OPERATION

There is a three bit delay between UOI, BOI or BZI input
and the decoded NRZ data transmitted out of SOO.

The decoder requires a single clock with a frequency
16X or 32X the desired data rate. The rate is selected on
the speed select with SS low producing a 16X clock and
high a 32X clock. For long data links the 32X mode should
be used as this permits a wider timing jitter margin. The internal operation of the decoder utilizes a free running clock
synchronized with incoming data for its clocking.

Control of the decoder outputs is provided by the RST
pin. When RST is low, SOO, OCLK and NVM are forced
low. When RST is high, SOO is transmitted out synchronously with the recovered clock DCLK. The NVM output remains low after a low to high transition on I1S'f until
a valid sync pattern is received.

The Manchester II encoded data can be presented to the
decoder in either of two ways. The Bipolar One and Bipolar Zero inputs will accept data from differential inputs
such as a comparator sensed transformer coupled bus. The
Unipolar Data input can only accept noninverted Manchester II encoded data, i.e. Bipolar Zero Out of an encoder.
The decoder continuously monitors this Manchester data
for a valid sync pattern. Note that while the MEO encoder
section can generate only a Command sync pattern, the decoder can recognize either a Command or Oata sync pattern.
A Oata sync is a logically inverted C.ommand sync.

The decoded data at SOO is in NRZ format. OCLK is provided so that the decoded bits can be shifted into an external register on every low to high transition of this clock.
Three bit periods after an inval id Manchester bit is received
on UOI, or BOI and BZI, NVM goes low synchronously
with the questionable data output on SOO. Further, the
decoder does not reestablish proper data decoding until
another sync pattern is recognized.

DeLK

UO'

SOD
RST

4-21

•

Repeater Mode
A low on CTS enables ECLK, BOO, and i3'Z0. In contrast
to the converter mode, a transition on CTS does not initiate
a synchronization sequence of eight O's and a Command
sync. The repeater mode does recognize a Command or
Data sync pulse. SD/CDS is an output which reflects the
state of the most recent sync pulse received, with high indicating a Command sync and low indicating a Data sync.

Manchester II data can be presented to the repeater in either
of two ways. The inputs Bipolar One In and Bipolar Zero
In will accept data from differential inputs such as a comparator or sensed transformer coupled bus. The input Unipolar Data In accepts only non-inverted Manchester II
coded data. The decoder requires a single clock with a
frequency 16X or 32X the desired data rate. This clock
is selected to l6X with Speed Select low and 32X with
Speed Select high. For long data links the 32X mode should
be used as this permits a wider timing jitter margin.

When RST is low, the outputs SDO, DCLK, and NVM are
low, and SRSi' is set low. SRST remains low after RST
goes high and is not reset until a sync pulse and two valid
manchester bits are received with the reset bit low. With
RST high, N RZ Data is transmitted out of Serial Data Out
synchronously with the lX DCLK.

The inputs UDI, or BOI, BZI are delayed approximately
1/2 bit period and repeated as outputs BOO and BZO.
The 2X ECLK is transmitted out of the repeater synchronously with BOO and BZO.

INPUT

COUNT!
DCLK

I-.-SYNCPULS~---I
,
,
UOI

BZO

BOO

RST

---,

SRST

'-------Switching Waveforms
NOTE: UDI" 0, FOA NEXT DIAGRAMS

I---BITPERIOO

BITPERIOO

BOI-tTl~
I-

BITPERIOO---l

r--

-I ~ T3
~Tl~

BZII

I-oTl~

COMMAND SYNC
BOIl
BZI

j:~T3
Tl~=========

~T3

, TZ

DATA SYNC

BOI~Tl~Tl~ ~

BZI~~ ~~~~~T3
t--

T4 -

ONE

-I-

ONE

T4----i

.1 •

1
.~

·1·

COMMAND SYNC

I
UOIJ.
I

ZERO

NOTE: BOI" 0; BZI- 1 FOR NEXT DIAGRAMS

UOIJ.

-j.

TZ
DATA SYNC

T.
~~~~~======~~====~F=====~T~.~======tl~'~T~4~~~
~==L-

U O I F = T4

ONE

ZERO

4-22

ONE

lONE

~O%
,

ALL OUTPUTS EXCEPT Ox

'0%7:

_____....;;;J,

he, BZI, BOI,UDI

ts-..J

~'6

---.

90%

CL -l00pF far CO
CL • 60pF for.1I ather outputs

~,~~---------

r--

f\,0%

_ ____--',,;;,O%;;.JI :

,,
----a

,,--,

~t7

,~~----------~

Encoder Timing

ECLK

----:---1
'CE,
I
I
SDICDS

I
I

_'CE2--.J
I

I
I

I
50%

BZO~_

,
I

I-

tcE3

~O%
I

________________________- J

BOO,

azo

_______________. - J

~tcE5-:

"'-tcE4.--j

EeLK,

/-"

~'"O,,~.

_____________

!JU

Decoder Timing
UDI
MANCHESTER '1'

MANCHESTER '0'

DCLK

SDD

"BINARY '1'

4-23

BINARY '0'

III

OXI

~40%

I~----------------~

------: tCD3 : -

--:

~,"o%

DCLK,SDO.
SRST,NVM

_____________

'CD4 ' - -

__________

. .,5:"~_+_',_r_-_-_-_-_ - - - - ---

Repeater Timing
UDI

SRST

MANCHESTER '0'

MANCHESTER '"

MANCHESTER '0'

MANCHESTER '"

MANCHESTER '0'

t---'R3---1
~~___________________________________________

I•

'R4

\ ....._ - - -

S D O _

MANCHESTER CODE

used when data is in a biphase format. For Manchester
" code, a logic "1" is defined as a bit period containing
a high to low transition at the middle of a bit period.
Manchester I code is not decoded properly by the H D6409. Manchester II code is also known as Biphase-L code.

In contrast to N RZ code, which represents binary code
as a static level throughout a bit period, Manchester code
is based upon a level transition at the middle of a bit
period. For serial data transmission this mid bit transition
affords Manchester code several advantages over N RZ code.
One is the elimination of the DC component NRZ code
produces when a long consecutive string of zeroes or ones
is transm itted. Single sideband or phase modulation networks require additional circuitry to use DC signals. Secondly, the transition can be used to recover the clock
from the Manchester data, allowing the synchronization of
the transmitted data with the receiver clock to occur
every bit period rather than every word frame. This improves the bit error rate.

Because Manchester code contains both the data and the
clock, it has a different frequency range than N RZ code.
The frequency range for NRZ code is from DC to fc/2
(fc-clock frequency), with constant unchanging logical
values producing a low frequency of 0 and alternating
logical values producing an upper frequency of fc/2. In
contrast, the low frequency for Manchester code, obtained
when the logical values of data alternates, is fc/2, while
the high frequency represented by unchanging logical
values, if f c .

The Manchester " code, Bipolar Zero and. Bipolar One,
as shown in the figure below, are logical complements

BIT PERIOD

I
BINARVCODE

NON RETURN

TOZERO

BIPOLAR ZERO

I
BIPOLAR ONE

JTLI1..LJLn

'
hJ.sLrtlj-lJ
I

,I
I

I '

4-24

External Clock Mode

__________________ TCYC __________________,",.I1
1

~TR~

1:~------TeL------~'

~~.-----------------,.~

1_.~_____ TeH ______~.~:

--ITF I _

PARAMETER

MIN

TCYC
TCH
TCL
TR

62
20
20

MAX

UNITS

50
*
50
*

ns
ns
ns
ns
ns
ns
ns

CONDITIONS

Ie" 3.3MHz
Ie :>3.3MHz
Ie " 3.3MHz
Ie :>3.3MHz

III
Crystal Oscillator Mode

lC Oscillator Mode

r------.------1

Cl ;;; 20pF

e1 ·32pF
Crysul + Stray
Xl· AT CUT PARALLEL

co = 5pF

co •

RESONANCE

FUND~

AMENTAL MODE
RI (TYPI ·30n
R1 -15Mfl

I---.....----l o.
e1

e1
Co

4-25

CMOS Bus Driver Family
HD-6431 CMOS HEX LATCHING BUS DRIVER
TRUTH TABLE
FEATURES

CONTROL
INPUTS

FUNCTIONAL DIAGRAM

DATA PORT
STATUS

• SINGLE POWER SUPPLY

• HIGH NOISE IMMUNITY

HI-Z·

• INDUSTRIAL
GRADES

HI-Z

AND

MILITARY

• DRIVE CAPACITY .•. • 300pF
• SOURCE CURRENT . . . . 4mA

• Data is latched to the value
of the last input

• SINK CURRENT . . . . . . . 6mA

X .. Don'teare
HI-Z .. High Impedance

• PROPAGATION DELAY: 65nsBC
@5V

+ '"

Transition from High
to Low Level

HD-6432 CMOS HEX BI-DIRECTIONAL BUS DRIVER
FUNCTIONAL DIAGRAM
TRUTH TABLE
FEATURES
•

INPUTS

•

INDUSTRIAL
GRADES

MILITARY

•

DRIVE CAPACITY .•. . 300pF

H
H

L
L

H
H
X

0
0

L
L
H

L
L

X
X

H
H

L
H

•

EAB EAB E BA EaA

HIGH NOISE IMMUNITY
AND

OATAPQRT
STATUS

CONTROL

• SINGLE POWER SUPPLY

I
I
I
0
I
0
ISOLATED

ISOLATED
ISOLATED
ISOLATED
NOT
ALLOWED

•

SOURCE CURRENT .••• 4mA

•

SINK CURRENT. • • . • •. 6mA

•

PROPAGATION DELAY:
@5V

I " Input, 0" Output, X" Don't Care

45nsec

HD-6433 CMOS QUAD BUS SEPARATOR/DRIVER
TRUTH TABLE

FEATURES

III

FUNCTIONAL DIAGRAM

• SINGLE POWER SUPPLY

CONTROL
INPUTS

FUNCTION

DRIVE CAPACITY . . . . 300pF

• SOURCE CURRENT .••. 4mA

ISOLATED

•

HIGH NOISE IMMUNITY

•

INDUSTRIAL
GRADES

•

AND

MILITARY

•

~INK

•

PROPAGATION DELAY:
@5V

CURRENT . . • . . • • 6mA
40nsec

t ... Input, 0- Output,
D:;;;; Disconnected

HD-6434 CMOS OCTAL RESETTABLE LATCHED BUS DRIVER
TRUTH TABLE
FEATURES

CONTROL INPUTS
Rl

• SINGLE POWER SUPPLY

DATA

HI-Z

MILITARY

• DRIVE CAPACITY . . .• 300pF

• HIGH NOISE IMMUNITY
• INDUSTRIAL
GRADES

AND

• SOURCE CURRENT .••. 6mA
• SINK CURRENT . • . . . • • 9mA
• PROPAGATION DELAY:
@5V

45nsec

X,= Don', Care HI-Z High Impedance
l"Low
H-High
• Data IS latched to the val of the last input

t -

Transition from a Low to High level

4-26

FUNCTIONAL DIAGRAM

CMOS Bus Driver Family
HD-6435 CMOS HEX RESETTABLE LATCHED BUS DRIVER
TRUTH TABLE
FUNCTIONAL DIAGRAM

FEATURES

CON'rROL INPUTS
R1

• SINGLE POWER SUPPLY

• HIGH NOISE IMMUNITY

• INDUSTRIAL
GRADES

AND

MILITARY

• DRIVE CAPACITY .

300pF

• SOURCE CURRENT

. 6mA

• SINK CURRENT . . • . • . . 9mA
• PROPAGATION DELAY:
@5V

HI-Z

•

x- Don't Care

45nsec

DATA
L2

HI-Z. High Impedance

L=-low
H=High
• Data is latched to the valueo! the last input

t =

Transition from a Lo ..... to High level

HD-6436 CMOS OCTAL BUS BUFFER/DRIVER

CONTROL

• SINGLE POWER SUPPLY
AND

INPUT

OUTPUT

• HIGH NOISE IMMUNITY
• INDUSTRIAL
GRADES

FUNCTIONAL DIAGRAM

TRUTH TABLE

FEATURES

MILITARY

• DRIVE CAPACITY .

. 300pF

• SOURCE CURRENT

.. 6mA

HI-Z

X
X

HI-Z

• SINK CURRENT .' .••.•• 9mA
• PROPAGATION DELAY:
@5V

L = Low, H

45nsec

HI-Z

= High

= Don't Care

= High Impedance

HD-6440 CMOS LATCHED 3 TO 8 LINE DECODER-DRIVER
TRUTH TABLE

FEATURES
•

. G1G203 rILl!

A2AtAO

• SINGLE POWER SUPPLY
• HIGH NOISE IMMUNITY
• INDUSTRIAL AND MILITARY
GRADES
•
•
•
•

FUNCTIONAL DIAGRAM

HIGH SPEED DECODING FOR
MEMORY ARRAYS

DRIVE CAPACITY •. . 200pF
SOURCE CURRENT • .. 2 mA
SINK CURRENT. . .. . 2.4 mA
PROPAGATION DELAY. 65nsec
@5V

YOY1YZY3Y4YSY6Y7 FUNCTION

H H H H H H H H
HHHHHHHH
HHHHHHHH
LHHHHHHH
H

L H

H H H H H

HHLHHHHf-/
HHHlHHHH
L

L H

L l

L H

HHHHLHHH

L H

HHHHHLHH
HHHHHHLH
H

" "
" "

VOY1 Y 2Y3Y4Y5 Y 6 Y 7

YOYtY2Y3Y4Y5Y6Y7

L'" Low,
Y n · Data

H - High,
IS

latched to the

x - Don'\ Care
villu~of

the last Input

HD-6495 CMOS HEX BUS DRIVER
FUNCTIONAL DIAGRAM

FEATURES

TRUTH TABLE

• SINGLE POWER SUPPLY
• INDUSTRIAL
GRADES

AND

INPUT

OUTPUT

X
X
X

HI-Z

CONTROL

• HIGH NOISE IMMUNITY
MILITARY

• DRIVE CAPACITY .

300pF

• SOURCE CURRENT

• 4mA

• SINK CURRENT ..•

• 6mA

• PROPAGATION DELAY:
@5V

35nsec

Don't Care HI-Z

HI-Z
HI-Z

= High Impedance

4-27

HARRIS

HD-6431

SEMICONDUCTOR
PRODUCTS DIVISION

CMOS HEX
LATCHING BUS DRIVER

Features

Pinout
TOP VIEW

•

SINGLE POWER SUPPLY

•

HIGH NOISE IMMUNITY

•
•
•
•

INDUSTRIAL AND MILITARY GRADES

•

DRIVE CAPACITY

300pF

SOURCE CURRENT

4mA

SINK ·CURRENT

6mA

PROPAGATION DELAY

75nsecMAX.

GND

Truth Table

Description
The HD-6431 is a self-aligned silicon gate CMOS Latching Three-State
Bus Driver. This circuit consists of 6 non-inverting latching drivers with

CONTROL
INPUTS

H
H
L
L
L

L
H

separate input and output. A high on the strobe line L allows data to go
through the latches and a transition to low latches the data. A high on
the Three-State control

VCC

E forces

the buffers to the high impedance mode

without disturbing the latched data.

New data may be latched in while

the buffers are in the high impedance mode.
Outputs guaranteed valid at VCC 2.0V for Battery Backup Applications.

H
H

DATA PORT
STATUS
A

X
X
X
L

HI-Z'
HI-Z

L
H

• Data IS latched to the value
of the la'St input
X = Don't Care
HI-Z = High Impedance
~ = T~~:il~.~ from High to

ID--------------~----~
Functional Diagram

(2)
1A

1y 2A

CAUTION: These devices are sensitive to electrostatic discharge.
Users should follow IC Handling Procedures specified on pg. 1-6.

4-28,

Specifications HD-6431

ABSOLUTE MAXIMUM RATINGS
+8.0V

Supply Voltage
Input or Output Voltage Applied

vee +0.3V
-65 0 e to +150 0 e

GND -0.3V to

Storage Temperature Range
Operating Temperature Range

-400 e to +85 0 e

Industrial HD-6431-9
Military

HD-6431-2

-55 0 e to +125 0 e
+4 to +7V

Operating Voltage Range

ELECTRICAL CHARACTERISTICS
Vee = 5.0V ± 10%; T A = Industrial or Military
PARAMETER

MIN

V,H

Logical "1" Input Voltage

70% VCC

V,L

Logical "0" I nput Voltage

',L

I nput Leakage

SYMBOL

VOH

MAX

TEST CONDITIONS

V
20% VCC

1.0

fJ.A
V

-1.0

Logical "1" Output Voltage

UNITS

VCC -0.4

OV~VIN~VCC
10H = -4.0mA,
E= Low

D.C.

VOL

Logical "0" Output Voltage

0.4

10L =6.0mA
E= Low

Output Leakage

-1.0

1.0

fJ.A

OV~VO~VCC,
E = High

ICC

Supply Current

fJ.A

C,N

Input Capacitance*

V,N = VCC or GND,
VCC = 5.5V
V,N = OV; TA = 25 0 C;
f = lMHz

Output Capacitance *

V,N = OV; TA = 25 0 C;
f = lMHz

• Guaranteed and sampled, but not 100% tested.

VCC= 5.0V

SYMBOL

A.C.

PARAMETER

MIN

Vee = 5.0V

±10%

TA = Indus. or Mil.

25 0 C

MAX

MIN

MAX

UNITS

tpD

Propagation Delay

tEN

Enable Time

tDiS

Disable Time

tSET

Input Setup Time

Input Hold Time
Pulse Width

tHOLD
tpw

.ns

Output Rise Time

Output Fall Time

NOTE

~---------

50%

EBA EAB

EBA

EAB

50%

All inputs have tR, tF ~ 20ns.

OUTPUT TEST CIRCUIT
FOR PROPAGATION OELAYS

OUTPUT TEST CIRCUIT
FOR THREE-STATE DELAYS

DECOUPLING CAPACITORS

The Transient current required to charge the load capacitance is given by IT ; C
change state at the same time and that
CL ; 300pF

~dt is constant;

IT; (6) (300 x 10- 12 ) 5.0 x 0.8
100 x 10- 9

dv
dt

. Assuming that all outputs may

IT ;/ECL) (VCC x 80%\ ego [tR; lOOns
V
tR or tF ')

VCC; 5.0V

each

72mA.] This current spike may cause a large negative voltage

spike on VCC, which if it becomes a diode drop less than any input, may cause the device to latch up. It is recommended that a 0.1 II F ceramic disk decoupling capacitor be placed between VCC and GND at each device to filter
out this noise.

II
PROPAGATION DELAYS

1.8

B/A

_________
50%

9O'i

:1-----

~O%

AlB

'po

12'"

J--tF

tpo

1.6

1.2'
1.16
1.08

1.'

~
1.00
tpo 1300pF) 0.92

1.2
tR.tF
1.0
tR, tF 13OOpF) 0.8

0.84

0.6

90%
0.2

tR---l

h~--r--.---r----'-

o 50 100

200

300 400
CllpF)
FIGURE 1

500

50 100

200

300 400
CllpF)
FIGURE 2

500

fore 55 x 0.84 or 46nsec. To obtain the rise and fall times
check the A.C. specs for the rise and fall times at 4.5V and
1250 C to obtain a worst case rise time of 110nsec. Use
Figure 2 to find it's degradation multiple to be 0.65. The
adjusted rise time is, therefore, 110 x 0.65 or 72nsec. To
obtain the standard 50% to 50% propagation delay, add the
adjusted propagation delay to half of the adjusted rise time
to get a propagation delay of 82nsec. The rise time was
used here because it is always the worst case.

The above example will illustrate the calculation of a more
useful propagation delay. The system on this example uses
a 5 volt supply with a tolerance of ± 10%, an ambient temperature of as high as 1250 C, and a calculated load capacitance of 150pF. This application requires the HD-6432-2.
The table of A.C. specs shows the tPD at 4.5V and 1250 C
. is 55nsec. Use the graph in Figure 1 to get the degradation
multiple for 150pF. The number shown is 0.84. The adjusted propagation delay, to the 10% or 90% point, is there-

4-33

HARRIS

HD-6433

SEMICONDUCTOR
PRODUCTS DIVISION
A DIVISION OF HARRIS CORPORATION

CMOS QUAD BUS
SEPARATOR/DRIVER
Pinout

Features

•
•

SINGLE POWER SUPPLY

•

INOUSTRIAL AND MILITARY GRADES

•

DRIVE CAPACITY

•
•
•

SOURCE CURRENT

TOP VIEW

HIGH NOISE IMMUNITY

300pF
4mA
SmA

SINK CURRENT

50nsec MAX.

PROPAGATION DELAY

Description
Troth Table
The HD-6433 is a self-aligned silicon gate CMOS bus separator/driver.
CONTROL

This circuit consists of 8 drivers organized as 4 pairs of bus separators

Outputs guaranteed valid at VCC 2.0V for Battery Backup Applications.

(15)

4A
(14)

4B
(13)

3A
(11)

(12)

3B
(10)

1O-..;(.;.;71~EB

(1)

(2)

(3)

(5)

(4)

CAUTION: These devices are sensitive to electrostatic discharge.
Users should follow IC Handling Procedures specified on pg. 1-S.

4-34

(S)

ISOLATED

= Input, 0 = Output,
o = 0 isconnected

Functional Diagram
4y

FUNCTION

INPUTS

which allow a unidirectional input bus and a unidirectional output bus to
be interfaced with a bi-di rectional bus.

Specifications HD-6433
ABSOLUTE MAXIMUM RATINGS
+8.0V

Supply Voltage

GND -0.3V to vee +0.3V

Input or Output Voltage Applied

-65 0 e to +150 0 e

Storage Temperature Range
Operating Temperature Range

-40 0 e to +85 0 e

Industrial H D-6433-9
Military HD-6433-2

-55 0 e to +125 0 e

Operating Voltage Range

+4 to +7V

ELECTRICAL CHARACTERISTICS
Vee

= 5.0V ± 10%; TA = Industrial

SYMBOL

or Military

PARAMETER

MIN

VIH

Logical "I" Input Voltage

70% Vee

V,L

Logical "0" Input Voltage

',L

I nput Leakage

VOH
VOL
10

MAX

1.0

PA
V

OV$VIN$VCC
lOH = -4.0mA

lOL =6.0mA

1.0

VCC -0.4

Logical "0" Output Voltage
Output Leakage

TEST CONDITIONS

V
20% Vec

-1.0

Logical "I" Output Voltage

UNITS

-1.0

D.C.

Ov$VO$VCC
EA = EB = High

ICC

Supply Current

C'N

V,N = VCC or GND,
VCC = 5.5V

I "put Capacitance *

V,N = OV; TA = 25 0 C;
f = lMHz

C'IO

I/O Capacitance·

V,N = OV; TA = 25 0 C;
f = lMHz

Output Capacitance *

V,N = OV;TA = 25 0 C;
f= lMHz

• Guaranteed and sampled, but not 100% tested.

eL = 300pF
Vee = 5.0V

'====:...,_+-_____,

iiiiiiiiii

.--.1....-.1-.,

UNIPOLAR
DATA IN
BIPOLAR

BIPOLAR
BIPOLAR
ZERO OUT

DECODER

CLOCK

SERIAL
DATA IN
ENCODER
SHIFT
CLOCK

SERIAL
DATA OUT

VALID
WORD

~:!~~>''----------...Jr__t:::~-+-.....::9+~~~DER

,.
DATA

COMMANDIOATA
SYNC

ZERQIN

SEND

TAKE DATA

ONE IN
BIPOLAR

ONE OUT

CLOCK

20
SYNC

SELECT

ENCODER
ENABLE

CAUTION: These devices are sensitive to electrostatic discharge.
Users should follow IC Handling Procedures specified on pg. 1- 6.

4-53

•

Specifications HO-15530
ABSOLUTE MAXIMUM RATINGS

Supply Voltage

+7.0V

Input or Output Voltage Applied

GND -O.3V to Vee + O.3V

Storage Temperature Range

-65 0 e to +150 0 e

Operating Temperature Range
-40 0 e to +85 0 e

Industrial HD-15530-9
Military HD-15530-2

ELECTRICAL CHARACTERISTICS
SYMBOL

D.C.

vee

= 5.0V is%

PARAMETER

= Industrial

MINIMUM

VIH
VIL
VIHC
VILC
ilL
VOH
VOL
ICCSB

Logical "1" Input Voltage
Logical "a" Input Voltage
Logical "I" Input Voltage (Clock)
Logical "a" Input Voltage (Clock)
Input Leakage
Logical "I" Output Voltage
Logical "a" Output Voltage
Supply Current Standby

ICCOp

Supply Current Operating"

CIN
CO

-55 0 e to +125 0 e

TYPICAL

or Military
MAXIMUM

0.5

S.O

10.0

5.0
S.O

7.0
10.0

pF
pF

20% VCC
VCC -0.5
GND +0.5
+1.0

-1.0

204
004

Input Capacitance*

Output Capacitance*

UNITS
V
V
V
V
f..IA
V
V
mA

70% VCC

TEST CONDITIONS

OV ~ VIN ~ VCC
IOH =-3mA
IOL = 1.SmA
VIN = VCC = 5.25V
Outputs Open
VCC = 5.25V,
1= lMHz

"Guaranteed and sampled but not 100% tested.

ENCODER TIMING vee

A.C.

FEC
FESC
TECR
TECF
FED
TMR
TEl
TE2
TE3
TE4
TE5
TE6
TE7
TES
TE9

A.C.

= 5.0V ±5%

Decoder Reset Setup Time
Master Reset Pulse Width
Bipolar Data Pulse Width
Sync Transition Span
One Zero Overlap

or Military

150
125
75
75
90
SO
55
150

Serial Data Hold
Enable Setup
Enable Pulse Width
Sync Setup
Sync Pulse Width
Send Data Delay
Bipolar Output Delay

Decoder Clock Frequency
Decoder Clock Rise Time
Decoder Clock Fall Time
Data Rate
Decoder Reset Pulse Width

= Industrial

15
2.5
S
S
1.25

Serial Data Setup

DECODER TIMING Vee
FDC
TDCR
TDCF
FDD
TOR
TORS
TMR
TDI
TD2
TD3
TD4
TD5
TD6
TD7
TDS
TD9
TOlD
TD11

= 5.0V ±5%

Encoder Clock Frequency
Send Clock Frequency
Encoder Clock Rise Time
Encoder Clock Fall Time
Data Rate
Master Reset Pulse Width
Shilt Clock Delay

50
130

= Industrial

8
S
1.25
150
75
150
TDC +10
lSTDC
TDC -10
6TDC
12TDC
40
50
SO
90
110
90

Sync Delay (ON)
Take Data Delay (ON)
Serial Data Out Delay
Sync Delay (OFF)
Take Data Delay (OFF)
Valid Word Delay

-'--------'
~:~~~R~~~~>-'2"-2--------'
MAsTERr"----------'
RESET

SELECT

CAUTION: These devices are sensitive to electrostatic discharge.
Users should follow Ie Handling Procedures specified on pg. 1-6.

DATA SYNC

SERIAL DATA OUT

4-60

VALID WORD
·PARITY
SELECT

+----+-!:4- ~~g~~ER

SHIFT

TAKE DATA,'

Mll-STO-1553A
The 1553A standard defines a time division multiplexed
data bus for application within aircraft. The bus is defined
to be bipolar, and encoded in a Manchester II format, so
no DC component appears on the bus. This allows transformer coupling and excellent isolation among systems and
their environment.

BUS

The HD-15531 supports the full bipolar configuration,
assuming a bus driver configuration similar to that in
Figure 1. Bipolar inputs from the bus, like Figure 2,
are also accommodated.
The signaling format in MIL-STD-1553A is specified on
the assumption that the network of 32 or fewer terminals
are controlled by a central control unit by means of Command Words, and Data. Terminals respond with Status
Words, and Data. Each word is preceded by a synchronizing pulse, and followed by parity bit, occupying a total
of 20 J.1. sec. The word formats are shown in Figure 4.
The special abbreviations are as follows:
P

Parity, which is defined to be odd, taken
across all 17 bits.

R/T

Receive on logical zero, transmit on ONE.

Message Error if logical 1.

Terminal Flag, if set, calls for controller
to request self-test data.

FIGURE 1 - Simplified MIL-STD-1553 Driver

"'"
"0"

FIGURE 2 - Simplified MIL-STD-1553 Receiver

The paragraphs above are intended only to suggest the
content of MI L-STD-1553A, and do not completely
describe its bus requirements, timing or protocols.

COMMAND
SYNC

III

I -------f-------COMMAND WORD (FROM CONTROLLER TO TERMINAL)

DATA
SYNC

q=j

I -------f--------

SYNC

~E~~otE~~oJ_n~~~
LOGICAL ONE DATA

LOGICAL ZERO DATA

5
TERMINAL
ADDRESS

I, I

SUBADDRESS
R/T
!MODE

5
DATA WORD
COUNT

I' I
I I
p

DATA WORD (SENT EITHER DIRECTION)

~~_ _ _ _ _ _ _ _'6__________41~11

l=
I

SYNC

DATA WORD

STATUS WORD (FROM TERMINAL TO CONTROLLER)

FIGURE 3 - MIL-STD-1553 Character Formats

FIGURE 4 - MIL-STD-1553 Word Formats

NOTE: This page is a summary of MI L-STD-1553A and is not intended to describe the operation of the HD-15531.

4-61

Ip I

•

Specifications HD-15531
ABSOLUTE MAXUMUM RATINGS

Supply Voltage

+7.0V

Input or Output Voltage Applied

GND -O.3V to vee +O.3V

Storage Temperature Range

-65 0 e to +150 0 e

Operating Temperature Range
-40 0 e to +85 0 e

Industrial HD-15531-9
Military HD-15531-2

-55 0 e to +125 0 e

ELECTRICAL CHARACTERISTICS Vee = 5.0V ±S% TA = Industrial or Military

D.C.

MINIMUM

PARAMETER

SYMBOL
VIH
VIL
VIHC
VILC
ilL
VOH
VOL
ICCSB

Logical "1" Input Voltage
Logical "0" Input Voltage
Logical "1" Input Voltage (Clock)
Logical "0" Input Voltage (Clock)
I nput Leakage
Logical "1" Output Voltage
Logical "0" Output Voltage
Supply Current Standby

ICCOp
CIN
Co

TYPICAL

MAXIMUM

UNITS

0.5

0,4
2.0

V
V
V
V
P.A
V
V
mA

Supply Current Operating"

S.O

10.0

Input Capacitance*
Output Capacitance*

5.0
S.O

7.0
10.0

pF
pF

70% VCC
20% VCC
VCC -0.5
GND +0.5
+1.0

-1.0
2,4

TEST CONDITIONS

OV ~ VIN ~ VCC
IOH =-3mA
IOL = 1.SmA
VIN = VCC = 5.25V
Outputs Open
VCC = 5.25V.
f = 15MHz

"Guaranteed and sampled but not 100% tested.
ENCODER TIMING

A.C.

FEC
FESC
TECR
TECF
FED
TMR
TE1
TE2
TE3
TE4
TE5
TE6
TE7
TES
TE9

Encoder Clock Frequency
Send Clock Frequency
Encoder Clock Rise Time
Encoder Clock Fall Time
Data Rate
Master Reset Pulse Width
Shift Clock Delay
Serial Data Setup
Serial Data Hold
Enable Setup
Enable Pulse Width
Sync Setup
Sync Pulse Width
Send Data Delay
Bipolar Output Delay

15
2.5
S
S
1.25
150
125
75
75
90
SO
55
150
50
130

MHz
MHz
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

CL - 50pF

MHz
MHz
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

CL - 50pF

DECODER TIMING

A.C.

FDC
FDS
TDCR
TDCF
FDD
TOR
TORS
TMR
TD1
TD2
TD3
TD4
TD5
TD6
TD7
TD8
TD9
TDlO
TD11
TD12
TD13

Decoder Clock Frequency
Decoder Synchronous Clock
Decoder Clock Rise Time
Decoder Clock Fall Time
Data Rate
Decoder Reset Pulse Width
Decoder Reset Setup Time
Master Reset Pulse Width
Bipolar Data Pulse Width
Sync Transition Span
One Zero Overlap
Short Data Transition Span
Long Data Transition Span
Sync Delay (ON)
Take Data Delay (ON)
Serial Data Out Delay
Sync Delay (OF F)
Take Data Delay (OFF)
Valid Word Delay
Synchronous Clock To Shift Clock Delay
Synchronous Data Setup
NOTE

15
2.5
S
S
1.25
150
75
150
TDC +10
18TDC
TDC -10
6TDC
12TDC
110
110
80
110
110
110
75
30

(j): 15TDC +10 = [15 (Decoder Clock Period)] +10ns TDC = Decoder Clock Period =_1_
These parameters are guaranteed but not 100% tested.

4-62

FDC

Pin Assignments
DESCRIPTION

NAME

SECTION

1
2

Both
Decoder

VCC
VALID WORD

Output high indicates receipt of a valid word.

Decoder

TAKE DATA'

A continuous, free running signal provided for host timing or data

4
5
6

Decoder

TAKE DATA
SERIAL DATA OUT
SYNCHRONOUS DATA

Output is high during receipt of data after identification of a sync pulse

Decoder
Decoder

Decoder

SYNCHRONOUS DATA SELECT

In high state allows the synchronous data to enter the character identification logic.

Decoder

SYNCHRONOUS CLOCK

Decoder

DECODER CLOCK

Positive supply pin.

handling. When data is present on the bus, this signal will be
synchronized to the incoming data and will be identical to take data.
Delivers received data in correct NRZ format.
I nput presents Manchester data directly to character identification

logic. SYNCHRONOUS DATA SELECT must be held high to use
this input. If not used this pin should be held high.

Input provides externally synchronized clock to the decoder.

This input should be tied high when not in use.
Input drives the transition finder, and the synchronizer which in

turn suppl ies the clock to the balance of the decoder.
10

Decoder

SYNCHRONOUS CLOCK SELECT

Decoder

BIPOLAR ZERO IN

Decoder

BIPOLAR ONE IN

Decoder

UNIPOLAR DATA IN

In high state directs the SYNCHRONOUS CLOCK to control the decoder
character identification logic. A low state selects the DECODER CLOCK
A high input should be applied when the bus is in its negative state.
This pin must be held high when the unipolar input is used.
A high input should be applied when the bus is in its positive state.
This pin must be held low when the unipolar input is used.
With pin 11 high and pin 12 low, this pin enters unipolar data into

Decoder

DECODER SHIFT CLOCK

Output which delivers a frequency (DECODER CLOCK -;. 12),

Decoder

TRANSITION SELECT

A high input to this pin causes the transition finder to synchronize on
every transition of input data. A low input causes the transition finder
to synchronize only on mid-bit transitions.

16
17

Decoder

N.C.
COMMAND SYNC

Decoder

DECODER PARITY SELECT

An input for parity sense, calling for even parity with input high and

Decoder

DECODER RESET

odd parity with input low.
A high input to this pin during a rising edge of DECODER SHIFT

the transition finder circuit. If not used this input must be held low.
synchronized by the recovered serial data stream.

Blank

Not connected.

Output of a high from this pin occurs during output of decoded data
which was preceded by a Command (or Status) synchronizing character

CLOCK resets the decoder bit counting logic to a condition ready
for a new word.

Both

COUNT Co

21
22
23
24
25

Both
Both
Both

GROUND
MASTER RESET
COUNTC2
60UT
BIPOLAR ZERO OUT

Encoder
Encoder

One of five binary inputs which establish the total bit count to be
encoded or decoded.
Supply pin.
A high on this pin clears 2: 1 counters in both the encoder and decoder.
See pin 20.
Output from 6: 1 divider which is driven by the ENCODER CLOCK.
An active low output designed to drive the zero or negative sense of
a bipolar line driver.

Encoder

OUTPUT INHIBIT
BIPOLAR ONE OUT

A Iowan this pin forces pin 25 and 27 high, the inactive states.

Encoder

SERIAL DATA IN

Encoder

ENCODER ENABLE

Accepts a serial data stream at a data rate equal to ENCODER SHIFT
CLOCK.
A high on this pin initiates the encode cycle. (Subject to the preceeding cycle being complete.)

Encoder

SYNC SELECT

Actuates a Command sync for an input high and Data sync for an
input low.
Sets transmit parity odd for a high input, even for a low input.

26
27

Encoder

An active low output designed to drive the one or positive sense of
a bipolar line driver.

Encoder

ENCODER PARITY SELECT

32
33

Encoder

SEND DATA

Is an active high output which enables the external source of serial data

Encoder

SEND CLOCK IN
ENCODER SHIFT CLOCK

Clock input at a frequency equal to the data rate X2.
Output for shifting data into the Encoder. This shift clock shifts data

35
36
37

Blank
Both

on a low-to-high transition.

Encoder
Decoder

N.C.
COUNT C3
ENCODER CLOCK
DATA SYNC

Not connected.

See pin 20.
Input to the 6: 1 divider.
Output of a high from this pin occurs during output of decoded data
which was preceded by a Data synchronizing character.

39
40

Both
Both

COUNT C4
COUNT C1

See pin 20.
See pin 20.

4-63

III

Encoder Operation
to accept data, the SEND DATA output will go high for
K ENCODER SHIFT CLOCK periods
During these
K periods the data should be clocked into the SERIAL
DATA input with every low-to-high transition of the
ENCODER SHIFT CLOCK
@. After the sync and
Manchester II encoded data are transmitted through the
BIPOLAR ONE and BIPOLAR ZERO outputs, the Encoder
adds on an additional bit with is the parity for that word
At any time a low on OUTPUT INHIBIT input will
force both bipolar outputs to a high state but will not
affect the Encoder in any other way.

The Encoder requires a single clock with a frequency of
twice the desired data rate applied at the SEND CLOCK
input. An auxiliary divide by six counter is provided on
chip which can be utilized to produce the SEND CLOCK
by dividing the DECODER CLOCK. The frame length is
set by programming the COUNT inputs. Parity is selected
by programming ENCODER PARITY SELECT high for
odd parity or low for even parity.

®.

®-

®.

The Encoder's cycle begins when ENCODER ENABLE is
high during a falling edge of ENCODER SHI FT CLOCK
This cycle lasts for one word length or K + 4 ENCODER SHIFT CLOCK periods, where K is the number of
bits to be sent. At the next low-to-high transition of the
ENCODER SHIFT CLOCK, a high at SYNC SELECT
input actuates a Command sync or a low will produce a
Data sync for that word @. When the Encoder is ready

CD.

TIMING

ENCODER SHIFT CLOCK

To abort the Encoder transmission a positive pulse must
be applied at MASTER RESET. Any time after or during
this pulse, a low-to-high transition on SEND CLOCK
clears the internal counters and initializes the Encoder for
a new word.

1'1'1'1,1-1'1'1'11·"'1·"1··,1·-'1·1 I 1
,Jl.JUlfUlI1JUU
,IL...n..JLIlSU
~~M

'.C.D'.'.AS" ---.J
SY.C","CT

WMVALlD!W'h0%~.N;rH~'~~
I

~/ffffi
I

1
...._ _ _ __

l"BIT4T8IT;T;iT2T;IT~};:;';--~

l~~~I.~'!~I!!!~I!'.::!.f~~!.~

•

Decoder Operation
To operate the Decoder asynchronously requires a single
clock with a frequency of 12 times the desired data rate
applied at the DECODER CLOCK input. To operate the
Decoder synchronously requires a SYNCHRONOUS
CLOCK at a frequency 2 times the data rate which is
synchronized with the data at every high-to-Iow transition
applied to the SYNCHRONOUS DATA input. The Manchester II coded data can be presented to the Decoder
asynchronously in one of two ways. The BIPOLAR ONE
and BIPOLAR ZERO inputs will accept data from a comparator sensed transformer coupled bus as specified in
Military Spec 1553. The UNIPOLAR DATA input can
only accept noninverted Manchester 11 coded data. (e.g.
from BIPOLAR ZERO OUT on an Encoder).

bits to be received. If the sync character was a data sync
the DATA SYNC output will go high. The TAKE DATA
output will go high and remain high @ while the
Decoder is transmitting the decoded data through SERIAL
DATA OUT. The decoded data available at SERIAL
DATA OUT is in NRZ format. The DECODER SHIFT
CLOCK is provided so that the decoded bits can get shifted
into an external register on every low-to-high transition of
this clock@-@.

After all K decoded bits have been transmitted
the
data is checked for parity. A high input on DECODER
PARITY SELECT will set the Decoder to check for even
parity or a low. input will set the Decoder to check for odd
parity. A high on VALID WORD output
indicates
a successful reception of a word without any Manchester
or parity errors. At this time the Decoder is looking for
a new sync character to start another output sequence.

The Decoder is free running and continuously monitors its
data input lines for a valid sync character and two valid
Manchester data bits to start an output cycle. When a valid
sync is recognized
the type of sync is indicated by a
high level at either COMMAND SYNC or DATA SYNC
output. If the sync character was a command sync the
COMMAND SYNC output will go high @and remain high
for K SH IFT CLOCK periods
where K is the number of

CD '

At any time in the above sequence a high input on DECODER RESET during a low-to-high transition of DECODER SHIFT CLOCK will abort transmission and initialize the Decoder to start looking for a new sync character.

®,

4-64

I' I

1 ' 1 • 1 ' 1 • 1 7 1 • 1 1N-' 1"-2 I N_' 1 Nil

1 1

'LIlrLfl.SU1mlJ

SYNCHRONOUS CLOCK

________________--i--------~r

~f-------------.~

_________---'1_ mm ___ m_~

!nn_n_m nn ____m L -

_________--'I _____ u _______ ~ ;__
"""DATADU'

_________________

L-

W/#/7/h'NN.j0.
AC$.O or l
AC >0 and

= 1 or both.
l = O.
= 1 or both.
l = O.

= 1 or both.
l = O.

When writing an actual program, it is useful to think in terms of the FORTRAN relational operators - .lT., .EO., etc.when trying to compare numbers. The following method along with Table 3 - 3 will provide this.
ClA Cll
TAD B
CMl CMA lAC
TADA
Test ClA

/ Initialize AC and Link
/Fetch 2nd number
/Create "-B" (AC & l act like a 13 bit accumulator)
/Fetch 1st number
fUse instructions from Table 3 - 3 to provide test
/The ClA is optional to provide a clear AC after test
/Branch to FAil routine if test failed
/Test passed, continue with program

JMP FAil

TABLE 3 - 3
SIGNED
COMPARE

UNSIGNED
COMPARE

SKIP IF
A. NE. B
A. LT. B
A. LEo B
A. EO.B
A.GE.B
A.GT.B

SNA
SMA
SMA SZA
SZA
SPA
SPA SAN

SNA
SNl
SNl SZA
SZA
SZl
SZl SNA

GROUP 3 MICROINSTRUCTIONS
Figure 8 shows the instruction format of group 3 microinstructions which requires bits 3 and 11 to contain a 1. Bits 4,
5 or 7 may be set to indicate a specific group 3 microinstruction. If more than one of the bits is set, the instruction is
a microprogrammed combination of group 3 microinstructions following the logical sequence listed in Figure 8.
0
I

2
I

I ClA IMOA I *

I
logical
1 2 3 -

MOL I *
*Don't care

Sequences:
ClA
MOA, MOL
NOP

FIGURE 8 - Group 3 Microinstruction Format

5-20

TABLE 4

MNEMONIC

OCTAL
CODE

LOGICAL
SEQUENCE

NUMBER
OF
STATES

NOP

7401

NO OPERATION - See group 1 microinstructions.

CLA

7600

CLEAR ACCUMULATOR

MOA

7501

MQ REGISTER INTO ACCUMULATOR - The content of the MO
is logical OR'ed with the content of the AC and the result is loaded
into the AC. The original content of the AC is lost but the original
content of the MO is retained. This instruction provides the programmer with an inclusive OR operation.

MOL

7421

MO REGISTER LOAD - The content of the AC is loaded into the
MO, the AC is cleared and the original content of the MO is lost.
This is similar to a DCA instruction.

ACL

7701

1,2

CLEAR ACCUMULATOR AND LOAD MO REGISTER INTO
ACCUMULATOR - This is equivalent to a microprogrammed combination of CLA and MOA. It is similar to the two instruction
combination of CLA and TAD.

CAM

7621

1,2

CLEAR ACCUMULATOR AND MO REGISTER - The content of
the AC and MO are loaded with binary O's. This is equivalent to a
microprogram combination of CLA and MOL.

SWP

7521

SWAP ACCUMULATOR AND MO REGISTER - The content of
the AC and MO are interchanged by accomplishing a microprogrammed combination of MQA and MOL.

CLA SWP

7721

1,2

CLEAR ACCUMULATOR AND SWAP ACCUMULATOR AND
MO REGISTER - The content of the AC is cleared. The content
of the MO is loaded into the AC and the MO is cleared.

OPERATION

Input Output Transfer Instructions (lOT)
The input/output transfer instructions, which have an OPCODE of 6a are used to initiate the operation of peripheral
devices and to transfer data between peripherals and the HM-6100. Three types of data transfer may be used to receive
or transmit information between the HM-6100 and one or more peripheral I/O devices. PROGRAMMED DATA
TRANSFER provides a straightforward means of communicating with relatively slow I/O devices, such as Teletypes,
cassettes, card readers and CRT displays. INTERRUPT TRANSFERS use the interrupt system to service several peripheral devices simultaneously, on an intermittent basis, permitting computational operations to be performed concurrently with the data I/O operations. Both Programmed Data Transfers and Program Interrupt Transfers use the accumulator as a buffer, or storage area, for all data transfers. Since data may be transferred only between the accumulator
and the peripheral, only one 12 bit word at a time may be transferred. D I R ECT MEMORY ACCESS, DMA, Transfers
variable-size blocks of data between high-speed peripherals and the memory with minimum of program control required by the HM-6100.
lOT INSTRUCTION FORMAT
The Input/Output Transfer instruction format is represented in Figure 9.
0

USER DEFINABLE BITS

Basic lOT Instruction: 6XXX a
0

2
0

DEVICE SELECTION
PDP-B/E Format: 6NNXa
FIGURE 9 -lOT Instruction Format

5-21

CONTROL

•

The first three bits, 0 - 2, are always set to 6a (110) to specify an lOT instruction. The next 9 bits, 3 - 11, are user definable and can provide a minimal implementation when each bit controls one operation. When following PDP-8/E
format, the next six bits, 3 - 8, contain the device selection code that determines the specific I/O device for which the
lOT instruction is intended and, therefore, permit interface with up to 64 I/O devices. The last three bits, 9 - 11, contain the operation specification code that determines the specific operation to be performed. The nature of this operation for any given lOT instruction depends entirely upon i:he circuitry designed into the I/O device interface.

PROGRAMMED DATA TRANSFER
Programmed Data Transfer is the easiest, simplest, most convenient and most common means of performing data I/O.
For microprocessor applications, it may also be the most cost effective approach. The data transfer begins when the
HM-6100 fetches an instruction from the memory and recognizes that the current instruction is an lOT @. This is
referred to an IFETCH and consists of five (5) internal states. The HM-6100 sequences the lOT instruction through a
2-cycle execute phase referred to as IOTA and 10TB. Bits 0 - 11 of the lOT instruction are available on DXO - 11 at
IOTA /\ LXMAR @. These bits must be latched in an external address register. DEVSEL is active low to enalbe data
transfers between the HM-6100 and the peripheral device @)& @. Input-Output Instruction Timing~ shown i~
ure 10. The selected peripheral device communicates with the HM-6100 through 4 control lines - CO, Cl, C2 and SKP.
In the HM-6100 the type of data transfer, during an lOT instruction, is specified by the peripheral device(s) byasserting the control lines as shown in Tables 5-1 and 5-2.
The control line SKP, when low during an lOT, causes the HM-6100 to skip the next sequential instruction. This feature is used to sense the status of various signals in the device interface. The .CO, Cl, and C2 lines are treated independently of the SKP line. In the case of a RELATIVE or ABSOLUTE JUMP, the skip operation is performed after the
jump. The input signals to the HM-6100,DXO - 11, CO, Cl, C2 and SKP, are sampled during IOTA on the rising edge
of time state 3 @. The data from the HM-6100 is available to the device during DEVSEL /\ XTC @. The 10TB
cycle is internal to the HM-6100 to perform the operations requested during IOTA. Both IOTA and 10TB consists of
six (6) internal states.

1-1__

---IFETCH ----o.JI·-_O-------IOTA -----~·-tl · - - - - - I O T B - - - - - · - I I

osc OUT
T-5TATES

DXIO-lll~~--------_<~~CJC:J0~)::)_--------~c:mE)--------------------------~
IFETCH

LXMAR~__________________~r1~

XTA ______

~r___1~

______________

____________________~--------------------------~r

~r---1~

____________________

~r___1~

________________

r--IL______________r-----~______________~--~

XTB~

MEMsEL ----,
I

L-J~~----------------------~--

DEVSEL

__
sg.~

-_-_-_-_-_-_-_-_-_-_-_-_-1
I

1-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-__
I

WAiT-_-_-L--J'.-,-_-_-_-_-_- _-L--l\--_-_-_-_-L..1\..- :_-_-_-_-_-_-_- _-_-_-_-

I
) to exit the
mode. When in the Alternate Mode, the ten
numeral keys, the decimal point key, and the
ENTER key transmit unique escape codes for
custom assignment by the user. In either
mode, there are also three blank unassigned
keypad keys for user definition. Cursor
control keys complete the keypad's function.

An auxiliary keypad extends the keyboard's
capabil ities. The keypad has 19 keys. There
are two modes in which the keypad can
operate, Normal and Alternate. When in the
Normal Mode, the ten numeral keys and the
decimal point key, respond like the numeral
keys and decimal point key on the main key-

6-13

PROCESSOR
The overall organization of DECstation":78 is shown in the Figure below. An LSI (large scale
integration) version of the powerful PDP-8 minicomputer contained on a 15 3/4" x 11 7/8"
printed circuit board is mounted inside of DECstation-78's video display unit. This is the processor for the system. It includes a 12-bit CPU with memory extension control, 16,384 words
(32 bytes) of Random Access Memory, complete peripheral interfacing, internal bootstrap
facilities, and a 1DDHz real-time clock. The CPU has the same powerful instruction set as the
PDP-8A. Cycle time is approximately 3.6 microseconds.
Three general purpose processor registers are provided:
• PC. The 12-bit program counter points to the location from which
the next instruction will be fetched.
• AC, L. The 12-bit accumulator and its 1-bit carry extension, the
Link, form the register where all arithemtic calculations take place.
• MQ. The 12-bit Multiplier Quotient register serves as a temporary
storage register.
Memory
Main memory is 12-bits by 16K words of Random Access NMOS Memory organized as
4 fields of 4K words each. Each field consists of 32 pages of 128 words.
An on-board ROM permits several important features to be included. These are:
• Automatic self-test procedure.
Processor status display.
• Terminal emulation mode, which alilows DECstation-78 to be used
as a stand alone computer terminal without independent processing
capability.
• Internal disk bootstrap.
Preselection of baud rates on primary communications port .

•
6-14

Instructions
There are two basic groups of instructions: memory reference and microinstructions. 1\1emory reference instructions require an operand; microinstructions do not. The DECstation-78
processor features indirect addressing capability up to 4K and 8 auto-index registers. Three
groups of operate microinstructions perform a variety of program operations without any
need for reference to memory location. Groups 1 and 2 allow the programmer to manipulate
and/or test the data that is located in the accumulator or link. Group 3 operate instructions
allow the programmer to manipulate the MQ register. Many of these operate microinstructions may be combined by the experienced programmer in order to use the DECstation-78
processor more efficiently.
Input/Output (lOT) instructions are used to control the operation of the computer's interrupt system and clock and to make all exchanges of data to the system display, keyboard,
and externally connected peripherals.
I nterface Ports
There are six interface ports for DECstation-78: a parallel port, a disk interface port, a
electronic program injection port and three asynchronous serial ports.
Parallel I/O Port - is for printers and custom interfacing. It provides bi-directional 12-bit
transfers at rates up to 15K words per second.
Serial Line Unit-1 (SLU-1) - connects the central processor to the display subsystem internally and is not externally accessible. The two other asynchronous serial EIA RS-232C
interface ports are suitable for primary and secondary communications applications, terminals, and the attachment of a variety of devices. These ports (SLU-2 and SLU-3) features
16 program selectable baud rates ranging from 50 to 19,200 baud and programmable loopback for maintenance. One port, SLU-3, provides programmable parity generation and
overrun detection, variable width stop-bit selection and programmable character length.
The other port, SLU-2, is equipped for full modem control.
Disk Interface Port - allows connection between the DECstation-78 processor and two
independent dual drive disk units (RX78). It provides both 8- and 12-bit data formats for
maximum flexibility.
MR78 Electronic Program Injection Port - allows the mounting of an external Read Only
Memory program capsule. The M R78 provides high speed loading under control of a preprogrammed ROM unit. Loading is automatically initiated when the DECstation-78 START
button is pressed.

6-15

•

RX78 FLOPPY DISK DRIVE
The RX78 Floppy Disk System is an inexpensive mass storage subsystem, I/O and random
access file device characterized by speed and reliability. Either one or two compact, self-contained units may be interfaced with the processor via a high-speed data port on the external
connector panel.
Track-to-track moves require six milliseconds for the move plus twenty milliseconds for settling
time if the head is loaded for a read or write. The rotational speed of the diskette is 360-rpm,
with an average latency time of 83 milliseconds. The total average access time is only 263
milliseconds.
The RX78 Floppy Disk System uses I BM-standard diskettes - thin, flexible oxide-coated disks
about the size of a 45-rpm phonograph record. The disk is recorded only on one side and is
permanently contained in an 8-inch square flexible protective envelope. The diskette contains
77 tracks with 26 sectors per track. Each sector can store 256 8-bit bytes or 128 12-bit words
for a total formatted capacity of 512,512 bytes or 256,256 words. The diskette is a portable,
convenient storage, interchange and software distribution medium which allows DECstation-78
users to store large amounts of data in a small space.
PRINTERS
For local on-site output, the LA78 DECprinter-1 1.80-cps line printer is recommended. This
printer interfaces via a parallel port on DECstation-78. For word processing applications, the
LQP78 letter quality printer is available.

III

6-16

Support Softvvare

Harris supports its microprocessor-based systems through an extensive variety of proven PDP-8
software. For the DECstation-78, there are three major operating system packages available.
These are: the OS/78 operating system that is included in the price of the basic DECstation-78
package; an optional commercial operating system, COS-310, for small business applications;
and a word processing system, WPS-8, for documentation and other text editing needs. For
real-time multitasking, RTS/8 can also be added.
In addition to these basic software support packages, Harris can provide the user application
software for linking the DECstation-78 to a hardware development system, such as the MICRO12. Harris also has a software package to link the DECstation-78 to a Data I/O Model 9 PROM
Programmer. PAL-8 based cross assemblers for the popular 8-bit microprocessors can be obtained from various sources, thus increasing the functionality of the DECstation-78. The user
also has access to the extensive DECUS library of PDP-8 programs which in many cases can
reduce development efforts.
MUL TILANGUAGE OPERATING SYSTEM OS/78
OS/78 provides DECstation-78 users with power and flexibility in both interactive and batch
programming environments. OS/78 is based on DIGITAL's proven OS/8 and offers many features previously available only on larger computer systems. OS/78 maximizes utilization of
DECstation-78 main memory because the resident portion of the operating system requires
only 256 words of memory. Non-resident portions of the system are swapped into memory
from the RX78 floppy disk automatically as required.
OS/78 is easy to use and provides the development programmer with a complete, logical interface
to program and file structures. All data files and executable programs are stored in one or
more floppy disks where they may be accessed for loading, modification or execution by simple
keyboard commands.
OS/78 incorporates Commercial BASIC and FORTRAN IV and provides a comprehensive set of
software tools and utility programs that help make DECstation-78 an excellent program development and calculations tool in the single-user environment. These include EDIT, PAL8, CREF,
ODT and BATCH PROCESSI NG, among others.

6-17

•

EDIT - is a line-oriented text editor that allows the user to enter and modify ASCII files.
It supports commands to list, insert, delete, change and move text as well as to search for
character strings.
PAL 8 - is a two-pass language assembler that provides the programmer with the capability
of coding directly in machine-oriented symbolic instructions. Its features include: 1) conditional assembly which enables a single source file to produce different binaries for different
purposes; 2) paginated listings, page headings and page numbering to improve program
documentation; and 3) a symbol table which lists all program labels and their memory
location or value.
CREF (Cross-Reference Utility Program) - aids the programmer in writing, debugging and
maintaining assembly language programs by providing the ability to pinpoint all references to
a particular symbol. CREF provides an alphabetical cross-reference table for PAL8 assembly
listings and numbers each line in the listing. Program symbols and literals are printed alphabetically along with the numbers of the lines that reference to them. Optional two-pass
operations doubles the number of symbols that can be accommodated in a program.
BITMAP - is anOS/78 utility used to construct a table, or map, showing the memory
locations used by a given binary file. BITMAP will accept any absolute binary file as input
and route its output to any supported I/O device.
ODT (Octal Debugging Technique) - is invisibly co-resident with the user program so that
there is no need to allocate more than 3 words in each 4K field for a debugging package
during development. Breakpoints can be set anywhere in a program to allow the programmer
to trace the execution of his program. Whenever program execution is suspended, ODT
provides the capability to examine and optionally modify memory locations or registers.
Specified areas of memory may be searched by means of ODT's binary memory search
mechanism.
OS/78's Batch Processing utility - allows lengthy sequences of commands or frequently
used programs to be run automatically on DECstation-78.
OS/78 BASIC - is high level, easily learned programming language compatible with Dartmouth BASIC. It uses simple English words, abbreviations and familar mathematical symbols
to specify operations. BASIC can be used for executing large data processing tasks as well
as performing quick, one-time calculations.
BASIC consists of an editor, compiler, and a runtime system, all three supporting BASIC's
dual functions as an interactive program development tool and a system for interactive and
batch execution. The BASIC instruction set includes powerful, yet simply learned commands
which allow novices to do useful programming in a relatively short time. Extended operations and functions, such as program chaining and string operations, allow the more experienced programmer to perform intricate manipulations or express a problem efficiently
and concisely.
REAL- TIME MULTITASKING RTS/8
RTS/8 allows DECstation-78 to handle many tasks simultaneously by making use of the otherwise idle processor cycles that occur periodically during a programs execution. A user-defined
priority list allows the most important jobs to be processed first. As a result, programs in execution can, if necessary, be temporarily suspended and removed from memory (swapped out) to
make room for a higher priority job.
By using RTS/8, the programmer is able to take advantage of a set of software modules that
will interface with his hardware, thereby freeing him to concentrate on his own programs and
greatly reduce development time. Note: RTS/8 must have OS/78 software as the operating
system.

6-18

WORD PROCESSING SOFTWARE WPS-8
Word Station 78 is a complete word processing and visual text editing package for use in both
stand alone and shared-logic environments. It can be added to the DECstation-78 and includes
proven turnkey word processing software. Options include the LOP 78 letter quality printer
and a Communications/Optical Character Reader interface which permits the word station to
communicate over various grades of communications facilities with host computers or other word
stations.
WS78 is powerful yet inexpensive enough to be used as a free-standing word processing system
with its own processing capability, local storage and printers. The software is conveniently
stored on the system floppy disk. Additonal space on the system floppy disk is reserved for a
boilerplate library and a shorthand dictionary. "Shorthand" expressions might be names, addresses, titles, technical words or other standard short units of text that an organization uses
repeatedly. These expressions may be stored on floppy disk, recalled with a few keystrokes and
automatically inserted into the current text, thereby saving hours of retyping and increasing
operator productivity. More than one hundred full pages of typing in as many as 200 separate
files may be stored on a document diskette.
Because all the "programming" is in the software, DIGITAL word stations can be used by anyone
for productive work after only a day's familiarization with the equipment. A typical standalone application, for example, might involve the use a a Word Station 78 in a development
facility for the production of reports, documents and correspondence.
Word Station 78 Features:
Software Features:
•
•
•
•
•
•
•
•
•
•
•

"Cue card" prompting of commands via visual display.
Prestored rulers for margin, printer spacing and tabbing control.
Format information stored with each document.
Variety of printer output for mailing labels, envelopes, letterhead,
technical manuals, etc.
Simultaneous printing and editing.
Justified margins.
Underlined and overstruck printout.
Time and date indexing of documents.
Mailing list generation.
Form letter merge.
Insertion of boilerplate material.

Full Editing Features:
• Bi-directional search capabilities.
• Block move ("cut and paste").
• Editing done by grammatical entities - character,
word, tab, column, sentence, line, paragraph, or page.
• Decimal point alignment.
• Swap of transposed characters.
• Manual or automatic pagination.

6-19

•

COMMERCIAL OPERATING SYSTEM COS-3l0
System Software
DIGITAL's Commercial Operating System (COS-310) is a self-contained, disk-resident
operating system for small to medium-sized commercial applications. System features
include:
• A comprehensive business programming language, DIGITAL's
Business-Oriented Language (DIBOLl.
• Numerous utilities to simplify program development and create,
update, sort/merge and back-up data files.
• Sequential or random file accessing from disk storage.
• User file directories.
• A large system message library.
• Multivolume file support.
• Batch and interactive data processing.
Applications Flexibility
One of the most important characteristics designed and built into DEC COS-310 is flex-ibility - flexibility that lets 310 tackle a wide range of data processing problems and produce
solutions quickly, efficiently, and economically. COS-310's flexibility is shown in its many
uses:
• A stand-alone computer system.
• A remote job entry station.
• A "brilliant" terminal functioning as a satellite to a central
computer system but having its own totally independent power.
COS-310 also services a wide range of users. Small companies can use COS-310 as their
total processing system to perform payroll and other necessary accounting functions. Larger
companies can use several DECstation-78's with COS-310 to decentralize their data processing by placing a DECstation-78 at each branch office to handle remote job entry while
providing complete formatting and batch processing capabilities on a local level. Banks,
insurance companies, manufacturers, warehousing operations - these are just a few of the
many users who can profit from the cost-effective performance of COS-310. Standard
applications programs are available from DEC as well as from numerous software firms.
The System for Small Companies
In small companies, COS-310 can be used in many applications areas - from order entry
and inventory control to accounts payable, accounts receivable, and payroll. It can maintain
credit files and information on outstanding orders, accept order entry information keyed
in at the video terminal, print the packing tickets, update the inventory file, and generate
invoices. COS-310 can also be used to report on back orders and future orders, to describe
the company's overall sales picture, to keep track of salesmen's commissions, and to perform
sales analysis and related processing tasks.
COS-310 can provide small companies with immediate information when it is needed, not
sometime later when the "crisis" has passed. Customers are happier because their orders
can be filled faster and more accurately. They receive up-to-date billing information and
account statements with no delays - a benefit that means a good cash flow back from
customers who want to maintain their credit ratings and/or discounts. Special discounts
are easily handled by the system with each customer's account reflecting information that is
unique to that company. Customer orders for the future can be entered into COS-31 0 and
automatically processed at the exact time they were requested.

6-20

Support Literature

HARRIS DATA BOOKS
Digital Data Book
Analog Data Book

HARRIS MANUALS
Harris Microprocessor Systems Design Manual
MICRO-12 User's Manual

DEC MANUAL
Introduction to Programming

DEC SYSTEM MANUALS
DECstation User's Guide
DECstation Technical Manual
OS/78 User's Manual
RTS-8 User's Manual
Word Processing System Reference Manual
COS-310 System Reference Manual

NOTES:

Data Books are available from Harris sales representatives and distributors.

Manuals can be purchased from Harris Semiconductor, Melbourne, Fla. (see
order form in back of this Data Book.
DEC Systems Manuals are available from DIGITAL Equipment Corporation.

6-21

Introduction to DECUSTM

OVERVIEW
Since the HM-6100 microprocessor was designed to recognize the instruction set of the Digital
Equipment Corporation (DIGITAL) TM PDP-8/E TM minicomputer, most programs written
for the PDP-8 family are also usable with the HM-6100. The Digital Equipment Computer
Users Society (DECUS) provides the vehicle through which HM-6100 and PDP-8 users can
exchange ideas, information and user written programs. Harris Semiconductor supports the
HM-6100 through participation in the 12-Bit Special Interest Group of DECUS.

HISTORY
DECUS was established in 1961 to " ... advance the effcient use of DIGITAL computers.
It is a voluntary, not-for-profit users group, supported in part by Digital Equipment Corporation·"1

ACTIVITIES
Symposia
The symposia, which are held throughout the year, provide a forum for users to meet with
each other and with DIGITAL management. The papers and presentations are published as
DECUS Proceedings shortly after each symposium and provide a permanent record of the
meetings activities.
Special Interest Groups (SIGs)
The SIGs promote the interchange of specialized information through the pubilication of
newsletters and the coordination of symposia sessions. At the symposiums they sponser
business meetings, tutorials, and workshops which fulfill the two-fold purpose of fostering
communication among users and between users and DIGITAL. User submitted articles,
minutes of local meetings, and letters comprise the major portion of the newseltters. Suggestions, hints, bug fixes, program plans, or questions of a non-commercial nature are suitable material for SIG newsletters.
The 12-Bit Special Interest Group is the vehicle through which users interested in 12-Bit
hardware and software can share their ideas. Focus on user interest in HM-6100 related
material (such as the DECstation-78) is provided by the MICRO-8 Working Group within
the 12-Bit SIG. Various application notes, and hardware and software suggestions are covered
in the MICRO-8 section of the 12-Bit SIG newsletter and at the symposia.

Program Library
One of the services performed by DECUS is the maintainence of a large library of programs
for DIG ITA L computers. The D ECUS PDP-8 Program Library Catalog lists over 1200
assembly language and FOCAL TM programs organized into 17 categories. Included are text
editors, assemblers, debuggers, high-level languages (BASIC, FOCAL, ALGOL, SNOBOL,
LISP, etc.), operating systems, input/output device handlers, mathematical packages, and
various other types of application software.

6-22

MEMBERSHIP

Associate
An individual who wishes to join DECUS is eligible for an Associate (non-voting) membership if he has" ... a bonifide interest in DECUS .. ."1' Associate Members receive DECUSCOPE, the Society's Newsletter, automatically. They may receive other DECUS material,
such as the 12-Bit SIG Newsletter and the PDP-8 Library Catalog, on request.
Installation
An organization, institution, or individual that has purchased, leased, or has on order a
computer manufactured by Digital Equipment Corporation (such as a DECstation-78) is
elgible for Installation Membership in DECUS.

TM Trademark Digital Equipment Corporation, Maynard, Ma. 01784
1 DECUS Membership Brochure

6-23

7-1

Reliability & Quality Contents

Introduction, Quality Control, Reliability

7-3

Section 1. CMOS Reliability/Quality Enhancement

7-5

Section 2. Fusing Mechanism of Nickel-Chromium Thin Film Links

7-11

Microscopic Observations of Fuses
Section 3. Reliability Screening Programs

7-23
7-28

Hi-Rei Program

7-28

Dash 8 Program

7-29

Section 4. Burn-In Circuit Diagrams

7-2

7-40

Harris Reliability & Quality
Introduction
The Product Assurance Department at Harris Semiconductor Products Division is responsible for assuring that the quality and reliability of all products shipped to customers meet
their requirements. During all phases of product fabrication, there are many independent
visual and electrical checks performed by Product Assurance personnel.
Prior to shipment, a final inspection is performed at Quality Assurance Plant Clearance to
insure that all requirements of the purchase order and customer specifications are met.
The following military documents provide the foundation for HARRIS Product Assurance
Program.
MI L-M-38510D
MI L-Q-9858A
MI L-STD-883B
NASA Publication 200-3
MI L-C-45662A
MI L-I-4508A

"General Specification of Microcircuits"
"Quality Program Requirements"
"Test Methods and Procedures for Microelectronics"
"Inspection System Provisions"
"Calibration System Requirements"
"Inspection System Requirements"

The Harris Semiconductor Reliability and Quality Manual, which is available upon request,
describes the total function and policies of the organization to assure product reliability and
quality. All customers are encouraged to visit the Harris Semiconductor facilities and survey
the deployment of the Product Assurance function.

Duality Control
All critical processing of digital products is subject to rigid manufacturing and quality
control processing.
Built-in quality assures that Harris products have an excellent reliabitlity record.
Diffusion and ion implantation processing is subject to oxide thickness controls, penetration evaluations, resistivity measurement and inspection gates for visual defects. To insure
process stability, diffusion furnaces, metallization and passivation equipment is subject
to frequent qualifications via C-V plotting techniques. CV techniques insure CMOS stability as they provide a very sensitive measure of the concentration of ionic species.
Thin film controls insure specified interconnect and passivation thicknesses. In the case
of bipolar memory circuits, the NiCr fuse processing is very carefully monitored via
Consistent and controlled execution of the HAR R IS
resistivity and geometry controls.
nichrome processing has led to very reliable PROMS of high programmability.
Other in-line process controls include:
•
•
•
•
•
•
•
•
•
•

Critical controls on all raw materials used in device processing and assembly
I n line SEM inspections
Specified consistent compositions of thin film source materials
Continual environmental monitoring for humidity, particle counts and temperatures
Controls on oxide and metallization thicknesses
Doping concentration and profiles
Pre and post etch inspections
Mask production inspection gates to control defect densities
Ion penetrations
Prescribed calibration intervals and preventative maintenance of all
processing equipment
• Total specification documentation and rigid change control procedures

7-3

•

Harris maintains a well equipped Analytical Services Dept. which is managed by Quality
Control. This area consists of a microscopy laboratory and a complete wet chemical analysis facility.
The microscopy lab includes a Scanning electron microscope with energy
dispersive X-ray analysis capability, electron microprobe, Scanning Auger with ESCA
attachment, SIMS and all sample preparation equipment.
Equipment also includes atomic absorption and optical emission spectrocopy, UV visible
and infra red and a profilometer.
This laboratory has the capability to do quantitative
and qualitative analyses of all semiconductor materials. This on-site facility assures Harris
built-in quality and reliability.

Reliability
The reliability approach at Harris Semiconductor is based on designing in reliability rather
than testing for reliability only. The latter is applied to confirm that sound design with quality
and reliability based ground rules are observed and correctly executed in a new product design.
Reliability engineering becomes involved as early as concept review of new products and
continues to remain involved through design and layout reviews. At these critical development points of a new design, basic reliability oriented layout guidelines are invoked to
insure an all-around reliable design. This concept is reflected by the Harris reliability
requirement procedures which encompass mandatory first run product evaluation. This
is done at not only the circuit level, but also at the process technology and package level.
Reliability engineering approval is required before new product designs are released to
manufacturing.
Tests at both maximum rated and accelerated stress levels are performed. Acceleration is
important to determine how and at what stress level a new design would fail. From this
information, necessary design changes can be implemented to insure a wider and safer
margin between the maximum rated stress condition and the device's stress limitation.
The notably low failure rates for the Bipolar and CMOS Memory products are a direct result
of the application of this reliability concept. For the PROM circuits, the high standards
for reliability and quality; have yielded the industry'S high programmability yields. Our
demonstrated expertise in N iCr fusing has resulted in observed failure rates which are less
than equivalently complex TTL LSI circuits. For example, derating according to the arrhenius reaction rate (1.0eV activation energy) gives a failure rate of 0.0002%/1000 hours
or 2 F ITs at +500 C ambient for programmed bipolar PROMs. For the 65XX CMOS Memory
products the +50 0 C derated failure rate is 0.0001%/1000 hours or 1 F IT (based on 1.2 e.V).
The excellent reliability peformance is further exemplified by our customers. Analysis of
parts returned to Harris indicates the following results. For the CMOS Memory products,
the returns constiture 0.2% of the total volume sh ipped, wh ile for the Bipolar Memory products this figure is 1.5%. This number includes all programmability rejects for the PROMs .
The accompanying charts illustrates the distribution of categories for why devices are returned. Note that 60-70% of these returned are devices that were not defective when they
were shipped.
These units failed due to electrostatic damage (ESDI. electrical overstress
(EOS). or were good devices which were incorrectly identified as board or system level
failures. The latter category is defined as invalid returns and represents 30-40% of the
total number of returned units.

7-4

40
PERCENTAGE
OF RETURNS
30

'---1

iiii

..""

I
4

CUSTOMER INDUCED PROBLEMS: 66%
1. INVALID RETURNS
2. EOS/ESD

56%
1%

OBSERVED FAILURE MODES: 34%
3. ASSEMBLY
4. TEST ESCAPES
5. PROCESSING FLAWS

1%
10%
24%

RETURNED UNITS
SHIPPED

EQUAL~1.5%

OF TOTAL PARTS

CMOS FAILURE CATEGORIES
(TYPICAL REPRESENTATION)

CUSTOMER INDUCED PROBLEMS:
OF RETURNED UNITS
1.
INVALID RETURNS
CUSTOMER PROGRAMMING
2.
PROBLEMS
3.
BLOWN BOND WIRES (REVERSE INSERTION)
4.
EOS, VCC SPIKES

PERCENTAGE
OF RETURNS

OBSERVED
5.
6.
7.
234

61%
27%
26%
5%
3%

FAILURES MODES:
PROCESSING FLAWS
ASSEMBLY
TEST ESCAPES

28%
8%
3%

7
RETURNED UNITS
PARTS SHIPPED

BIPOLAR FAILURE CATEGORIES

EQUAL

1.5%

OF TOTAL

(TYPICAL REPRESENTATION)

Section 1.

CMOS Reliability/Quality Enhancement

To ensure a totally reliable product and system, the design engineer needs to understand
In addition, a clear understanding
the capabilities and limitations of CMOS product.
of the techniques employed to improve reliability is essential for High Reliability system
goals. The following describes the necessary tools to enhance CMOS reliability.
DESIGNING OUT FAILURE MODES
Static Charge
Since the introduction of MOS, manufacturers have searched for effective and safe ways
of handling this voltage sensitive device. High input impedance of CMOS, coupled with
gate-oxide breakdown characteristics, result in susceptibility to electrostatic charge damage.

7-5

•

Figure 1 shows ~ cross-section of a silicon gate MOS structure. Note the very thin oxide
layer ( ~ 1000A)* present under the gate material. Actual breakdown voltage for this
insulating layer ranges from 70V to 100V.
Handling equipment and personnel, by simply moving, can generate in excess of 10kV of
static potential in a low humidity environment. Thus, static voltages, in magnitudes sufficient to damage delicate MOS input gate structures, are generated in most handling environments.
A failure occurs when a voltage of sufficient magnitude is applied across the gate oxide
causing it to breakdown and destruct. Molten material then flows into the void creating a
short from the gate to the underlying silicon. Such shorts occur either at a discontinuity
in doping concentration, or at a defect site in the thin oxide. If no problems appear in the
oxide, breakdown would most likely occur at gate/source, or gate/drain intersection coincidence due to the doping concentration gradient.
Noncatastrophic degradation may result due to overstressing a CMOS input. Sometimes
an input may be damaged, but not shorted. Most of these failures relate to damage of the
protection network, not the gate, and show up as increased input leakage.

FIGURE 1 - Silicon-gate PFET structure cross-section shows the
heavily doped source and drain regions. They are separated by a narrow
gap over which lies a thin-gate oxide and gate material.

Voltage Limiting Input Protection
During the evolution of monolithic MOS, manufacturers developed various protection
mechanisms that are an integral part of the circuit. However, several of these earlier techniques have been replaced by improved methods now in use. The object of most of these
schemes is to prevent damage to input-gate structures by limiting applied voltages.
Recent CMOS designs employ a dual-diode concept in their input protection networks.
Figure 2 illustrates such a protection circuit.
One characteristic of junction-isolated CMOS protection circuits is the ~ 20011 current
limiting resistor. Cross sectional area of the metallization leading to the resistor, and the
area of the resistor are, therefore, designed to absorb discharge energy without sustaining
permanent damage. This dual-diode protection has proved very effective and is the most
commonly used method in production today.
HARRIS INPUT GATE PROTECTION
To protect input device gates against destructive overstress by static electricity accumulating
during handling and insertion of CMOS products, Harris provides a protection circuit on all
inputs. The general configuration of this protection circuit is shown in Figure 2.
Both diodes to the VDD and VSS lines have breakdown voltages averaging between 35 and
40 volts. Excessive static charge accumulated on the input pin is thus effectively discharged
through these diodes which limit the voltage applied from gate to drain and source. The
200 ohm resistor provides current limiting during discharge. Depending on the polarity of
the input static charge and on which of the supply pins are grounded, the protective diodes
may either conduct in the forward direction or breakdown in the reverse direction .

•,..& (Angstrom = ,o-8cm)

7-6

In order to test this concept, step stress tests have been performed at Harris using an approximate equivalent circuit to simulate the static charge encountered in handling operations.
The equivalent circuit consists of a 100pF capacitor in series with a 1.5K ohm resistor
and is considered the rough equivalent of a human body. Step stressing takes the form of
charging the capacitor to a given voltage and then discharging it into an input pin of the
CMOS device under test according to the sequence given in MI L-M-3851 O.
Stress Voltage

Cumulative Failures

500
700
1000
1500
1700
1800

o
o
o
1

3
4

These results indicate that the input protection used for Harris CMOS products provides
adequate protection against static electricity based on the limits specified in MI L-M38510.
There are two trade-ofts to consider when fabricating an input protection scheme, namely
effectiveness of the overvoltage protection and performance of the overall circuit. It is
obvious that increasing the series resistance and capacitance at an input limits current and
this, in turn, increases the input protection's ability to absorb the shock of a static discharge. However, such an approach to protection can have a significant effect on circuit
speed and input leakage. The input protection selected must therefore provide a useful
performance level and adequate static-charge protection.
Commonly used MOS-input protection circuits all have basic characteristics that limit
their effectiveness. The zener diodes, or forward-biased pn-junctions, employed have
finite turn-on times too long to be effective for fast rise-time conditions. A static discharge of 1.5kV into a MOS input may bring the gate past its breakdown level before the
protection diodes or zener becomes conductive.
Actual turn-on times of zeners and pn-diodes are difficult to determine. It is estimated
that they are a few nanoseconds and a few tens of picoseconds, respectively. A low-impedance static source can easily produce rise times equal to or faster than these turn-on
times. Obviously the input time constant required to delay buildup of voltage at the gate
must be much higher for zener diodes or other schemes having longer turn-on times.
~200n

POLYSILICON
RESISTOR

Voo

NNOTE: FOR CMOS, Voo IS MOST
POSITIVE; Vss IS MOST
NEGATIVE.

P+
INPUT

Q--.IV'_+-i
200

FIGURE 2 - Junction isolated dual-diode protection networks are most
commonly used in today's CMOS circuits.

7-7

•

Consider an example. Figure 3 shows a test circuit that simulates the discharge of a 1.5kV
static charge into a CMOS input. Body capacitance and resistance of the average person
is represented by a 100pF capacitor through 1.5kO. Switch A is initially closed, charging
100pF to 1.5kV with switch B open. Switch A is opened, then B is closed, starting the
discharge. With the 1.5KO x 5pF time constant to limit the charge rate at the DUT input,
it would take approximately 350psec to charge to 70V above VDD. Diode turn-on time
is much shorter than 350psec, hence the gate node would be clamped before any damage
could be sustained.
There is no completely foolproof system of chip-input protection presently in production.
If static discharge is of high enough magnitude, or of sufficiently short rise-time, some
damage or degradation may occur. It is evident, therefore, that proper handling procedures
should be adopted at all times.
VDD

I
I

1.5Kf2

0--<>:

1.5kV~~

I
I
I
CHH"N'......--.

100PF

Vss

TEST SETUP

4pF

Vss

I
.
I DEVICE UNDER TEST

FIGURE 3 .,.. Input protection network test setup illustrates how diode
clamping prevents excessive voltages from damaging the CMOS device.

HANDLING RULES
Elimination or reduction of static charge can be accomplished as follows:
• Use conductive work stations. Metallic or conductive plastic* tops on work benches
connected to ground help eliminate static build-up.
• Ground all handling equipment.
• Ground all handling personnel with a conductive bracelet through 1MO
The 1MO resistor will prevent injury.

to ground.

• Smocks, clothing, and especially shoes of certain insulating materials (notably nylon)
should not be worn in areas where devices are handled. These materials, highly dielectric in nature, will hold or aid in the generation of a static charge.
• Control relative humidity to as high a level as practical.
helps bleed away any static charge as it collects.

A higher level of humidity

• Ionized air blowers reduce charge build-up in areas where grounding is not possible
or desirable .
• Devices should be in conductive carrriers during all phases of transport. Leads may be
shorted by tubular metallic carriers, conductive foam or foil.
• In automated handling equipment, the belts, chutes, or other surfaces the leads contact
should be of a conducting nature. If this is not possible, ionized air blowers may be a
good alternative.
THE FORWARD-BIAS PHENOMENON
Monolithic CMOS integrated circuits employ a single-crystal silicon wafer into which
FET sources and drains are implanted. For complex functions many thousands of transistors may be required and each must be electrically isolated for proper operation.

·Supplier: 3M Company "Velostat".

7-8

Junction techniques are commonly used to provide the required isolation - each switching
node operating reverse-biased to its respective substrate material. Additionally, as previously mentioned, protection diodes are provided to prevent static-charge related damage
where inputs interface to package pins. Forward-biasing any of these junctions with or
without power applied may result in malfunction, parametric degradation, or damage
to the circuit.

Before proceeding, it should be pointed out that junction isolation, in the classical sense,
is not implemented in the CMOS structure. Although commonly called junction isolation,
the CMOS technique varies substantially from that used in bipolar TTL (Figure 4).

N-EPITAXIAL
LAYER
P+ ISOLATION DIFFUSION

P-WELL FOR
N-CHANNEL TRANSISTORS
VSS

NO EPITAXIAL LAYER
P CHANNEL TRANSISTORS
ARE DIFFUSED DIRECTLY
INTO THE N-SUBSTRATE

CMOS "JUNCTION ISOLATION"

FIGURE 4 - Junction isolation for bipolar and CMOS differ considerably. CMOS utilizes a simpler technique that takes advantage of its less
complex processing.

ELECTROMIGRATION AND FUSING
An aluminum metallization system is used for on-chip interconnect and wire bonding of
most CMOS integrated circuits. On-chip metallization means a very pure grade of aluminum
deposited on the surface of a silicon wafer. A subsequent metal etch defines the interconnect pattern.
This on-chip metallization can be subject to two primary current density related failure
modes, electromigration and fusing.
Electromigration results from displacement of metal atoms due to high current densities.
Displacement of atoms creates physical holes in the metal structure that enlarge with time,
eventually causing an open circuit. Current density levels for which circuit life is not
impaired are subjects of considerable debate. One figure, generally considered to be ultrasafe, is 105A/cm 2 .
Considerably higher current densities, on the order of 106 - 108 A/cm 2, are required to
cause fusing. For a 0.3 mil wide 40 J.l. inch thick aluminum line and a fuse current density
of 107 A/cm 2, 775mA will cause fusing. Current levels of this magnitude are not generated
during normal CMOS operation.
Could a high-energy static discharge into a CMOS input or output cause fusing? Yes,
but such a failure would most likely occur due to heavily forward-biasing an input or
output through a low impedance.

7-9

•

High currents resulting from an excessive forward-bias can cause severe overheating localized to the area of a junction. Damage to the silicon, overlying oxide and metallization
can result.
BIPOLAR PARASITICS
Care must always be exercised not to forward-bias junctions from input or output pads.
A complex and potential defect phenomenon is the interaction of a npn/pnp combination a la SCR (Figure 5). Forward-biasing the base-emitter junction of either bipolar
component can cause the pair to latch up if ,8npn x ,8pnp ~ 1. The resultant low impedance between supply pins can cause fusing of me.tallization or over-dissipation of the chip.
Figure 5 shows how an SCR might be formed. The p+ diffusion labeled INPUT is connected
to aluminum metallization and bonded to a package pin. Biasing this point positive with
respect to VDD supplies base drive to the pnp through R2. Although gain of these lateral
devices is normally very low, sufficient collector current may be generated to forwardbias and supply substantial base current to the vertical npn parasitic. Once the pair has
been activated, each member provides the base current required to sustain the other. A
latched condition will be maintained until power is removed or circuit damage disables
further operation.
EMITTER (PNP)
INPUT

Voo

R2
LATERAL
(PNP)
VERTICAL
(NPN)

COLLECTOR
(NPN)

Voo

Vss

FIGURE 5 - Improper biasing can latch-up this SeR configuration. A
p+ guard ring is commonly used to kill lateral pnp action. This ring is
diffused into the surface at the junction of p- and n- silicon.

DESIGN RULES EQUALLY IMPORTANT AS HANDLING RULES
A system using CMOS devices must have reliability designed in. No amount of testing can
guarantee long term reliability when poor design practices are evident.
• Never apply signals to a CMOS circuit before power has been turned on (to prevent
latch-up)
• Supply filter capacitance should be distributed such that some filtering is in close
proximity to the supply pins of each package. Testing has shown 0.01 /-I F/package to be
effective in filtering noise generated by most CMOS functions.
• CMOS signal lines are terminated at the driving end by a relatively high impedance when
operating at the low end of the supply voltage range. This high-impedance termination
results in vulnerability to high-energy or high-frequency noise generated by bipolar or
other non-CMOS components. Such noise must be held down to manageable levels on
both CMOS power and signal lines.
• Where CMOS must interface between logic frames or between different equipments,
ground differences must be controlled in order to maintain operation within absolute
maximum ratings.

7-10

• Capacitance on a CMOS input or output will result in a forward-bias condition when
power is turned off. This capacitance must discharge through forward-biased input or
output to substrate junctions as the bus voltage collapses. Excessive capacitance (thousands of pF) should be avoided as discharging the stored energy may generate excessive
current densities during power-down.
• Where forward-biasing is inevitable, current limiting should be provided. Current should
not be permitted to exceed 1mA on any package pin excluding supply pins.
All CMOS is susceptible to damage due to electrical overstress. It is the user's responsibility to follow a few simple rules in order to minimize device losses.
He should first select a source for the CMOS device that employs an effective input protecttion scheme. This will allow a greater margin of safety at all levels of device handling since
the devices will not be quite so prone to static charge damage. Next, he should apply a
sound set of handling and design rules. At minimum, this will eliminate electrical stressing
or hold it to manageable levels.
With an effective on-chip protection scheme, good handling procedures and sound design,
users should not lose any CMOS devices to electrical overstress.
The total reliability data base to date for SAJI process related CMOS products is represented
as follows:
OPERATING LIFE TEST RESULTS
NO.OF
DEVICES

DEVICE-HOURS
DEVICE-HOURS

NO.OF
FAILURES

OBSERVED
FAILURE RATE

DERATED TO
50°C (1)

2,332

2,634,304

0.68%/1 K HOU RS
OR 6800 FITs

0.0003%/1 K HOU RS
OR 3 FITs

0.07%/1 K HOU RS
OR 700 FITs

0.00003%/1 K HOURS
ORO.3FITs

POST 168 HOURS

(1) Derating is based on activation energy of 1.2eV.
Above data reflects dynamic operating life at VDD=5.5V, fO=lMHz
@ T A=+1250 C using unburned in product.
1 FIT (failure unit)=l failure in 109 device-hours.

Section 2. Fusing Mechanism of Nickel-Chromium Thin Film Links

Nickel-chromium fusible link programmable read-only memories, PROMs have been developed and utilized since their inception during the early 1970's 1. The physical mechanism of fusing these links has been generally described as melting,2 but with the advent of
a successful transmission electron microscopy technique 3 ~ has detailed information on the
structure of the programmed fuse gap become available. These observations, coupled with
electrical and thermodynamic characterization of the fusing event, have led to a clearer
understanding of this phenomenon with concurrent definition of programming conditions
for reliable operation of programmed PROMs.

7-11

•

SOME RELEVANT GENERAL PROPERTIES OF NICKEL-CHROMIUM
Fundamental to the mechanism of NiCr .fusing are those physical properties that make
it an excellent registor material from processing, design and applications perspective. It
is no accident of history that NiCr is widely used for resistors on solid state devices.
To begin with, NiCr is a resistive material comprised of two transition metals-nickel
and chromium. In transition metals, the outer electron shells contain only one or two
electrons and some of the conduction electrons must come from inner shells. The inner
shell conduction electrons are shielded by the outer shell resulting in a high scattering and
trapping site density. Thus, transition metals are inherently less conductive than normal
metals 4 • In the case of NiCr, an alloy effect 4 occurs to further enhance electron
scattering. The result is that the resistance of the alloy is much higher than the arithmetic
average of its two components 5 as illustrated in Figure 1 * *.
The resistivity of NiCr makes it well suited for small geometry thin film resistors that
are size compatible with high density fuse design requirements. Due to its high resistivity
the thickness of NiCr that is necessary to achieve a typical fuse resistance of 300 ohms
is an advantageous property for a fuse, as will be described later. There is also the elimination of step coverage problems where the metallization (aluminum) contacts the NiCr.
A consequence of the extensive electron scattering in NiCr is a short mean free path of
the conduction electrons. For example, the mean free path in gold is 380A 6 compared to
an estimated 40A for NiCr. As a consequence, films greater than 100A thick have bulk
resistivity properties (i.e., surface effects are not dominant). As Figure 2 shows, surface
scattering effects which reduce conduction are absent by the time the resistor film is greater
than 1OOA 7 in thickness. The practical ramification of this property is reproducibility in
the fabrication process. Because there is no dependence on surface effects to achieve the
desired sheet resistivity, thin film resistors may be produced with excellent tolerance and
stabilityB.
The short mean free path is also relevant to describing the fusing mechanism, discussed in
the Mass Transport Models section.
NiCr is a material that forms a self-limiting oxide skin. That is, the oxide of NiCr is known
to be a coherent spinel 9 ,10 , see Figure 3. It is postulated that in the course of processing
NiCr resistors, this thin spinel sheath will form around the NiCr to a thickness of ~ 20A.
This sheath serves to stabilize the resistors and is partly responsible for the excellent thermal stability (absence of::::::: R(T) effects) of NiCr 11. This spinel may also be a factor in the
fusing pehnomenon.

MICROSTRUCTURE OF A PROGRAMMED NICKEL-CHROMIUM FUSE
The technique of using transmission electron microscopy (TEM) to examine programmed
fuse gaps was developed by Dr. Kinsey Jones at C.S. Draper Labs 3 ,12 . It is the only technique which mutually satisfies the requirements of sufficient resolution to analyze the gap
and not destroy in sample preparation the structure to be analyzed. It is this latter point
that has severely limited the utility of the scanning electron microscope (SEM) in endeavors
to analyze programmed NiCr fuses. In depassivating devices, necessary with the SEM,
microstructural details of the fuse gap are destroyed. Many interpretations of the fusing
phenomenon based on SEM results have been erroneous or misleading because what was
seen was an artifact of sample preparation.
Figure 4 illustrates schematically the utilization of transmission electron microscopy for
fuse gap analysis. Of course, besides direct structure observation, comp'osition of various
phases may be ascertained by electron probing.
•
The microstructure of a programmed fuse gap in a PROM circuit via TEM is shown in
Figure 5. The relevance of those programming conditions will be discussed further in
following sections, but Figure 5 is representative of the gap created in a NiCr fuse under
programming power conditions specified 13 for PROM's.

7-12

The TEM micro photograph indicates the elemental distribution found by microprobing.
The following observations are made:
a.

The visual appearance indicates that the neck of the fuse was in the molten state
during programming.

Mass transport of the nickel and chromium from the gap region has occurred.

There is asymmetry to the melted NiCr distribution. That is, there is more
densified NiCr on what was the cathode (negative) side of the fuse which
suggests the molten NiCr moved in a direction opposite to electron flow during
programming.

d. The gray phase (region C) of the gap which comprises the insulative separation of
the two sides of the fuse is devoid of nickel and composed of oxides of silicon and
chromium 14. The typical separation is 0.6-1.0 microns. The resistance across the
gap is > 10 megohms and it will not break down, electrically or structurally to
voltages in excess of 100 volts.
e.

The white spots, dark spots and filaments are described by the fluid dynamics of a
disintegrating liquid sheet 12. Briefly, that model describes how minute discontinuities in a liquid sheet, perterbate into larger holes and finally into droplets and
filaments because of surface tension effects. The structure looks similar to a "frozen
splash".

MASS TRANSPORTMODELS
In the previous section, it has been demonstrated that programmed NiCr fuses melt
and that mass transport takes place. But what is the mechanism, the driving force for mass
transport? Table 1 lists the possibilities.
Table 1
(1) Electromigration (Huntington & Grone 15): Mass flux occurs under the influence
of high current flow because electron collisions with atoms of the conducting
medium provide a net motion vector in the direction of electron flow.
(2) Thermal gradient (Soret 16): In the presence of a thermal differential, material
will diffuse from the high temperature to the low temperature region.
(3) Concentration gradient (Fick 17 ): In an imbalanced distribution of concentration,
mass will diffuse from regions of higher concentration to lower concentration.
(4) Field enhanced ionic mobility (Eyring and Jost 18): Molten metals will ionize,
lose electrons and become cations. In the presence of an electric field, they will
be driven towards the cathode.
Considering each possible mechanism in turn:
(1) Electromigration - On the surface, this seems a most logical explanation for programming. It is known that the current densities in a fuse neck at programming
are very high ( rv 5 x 107 amps/cm 2 ) and it could be postulated that this electron
flux sweeps the nickel and chromium from the gap. But empirical data and theoretical considerations show this not to be the case.
a.

TEM of the fuse gap indicates the molten. NiCr has moved
opposite to electron flow.

in a direction

b. Theoretical calculations of the kinetic energy of conduction electrons in
NiCr demonstrate that because the mean free path is short and the lattice
binding energy is high (transition metals typically have high melting points),
the electrons have insufficient energy to impart the mobility to the nickel and
chromium atoms necessary for electromigration in the direction of electron
flow.

7-13

•

However, general treatments of electromigration theory 15, 24 identify two forces
acting on atoms of the conducting medium. One is the aforementioned electron
momentum ("electron wind"). in the direction of electron flow. The other is the
electrostatic force from the applied electric field that causes ions of the conducting
material to move opposite to the direction of electron flow. See mechanism (4).
Obviously, the joule heating that leads to melting the fuse is coming from electron
interaction with the NiCr film. There is no incongruity with the fact that this
is not leading to electromigration such as observed in aluminum. Because the mean
free path is short, the energy exchanged per collision is small. But because electron
scattering is a dominant factor in resistive materials, the frequency of collisions is
high. Thus, thermal energy (lattice vibration) is added to the metal atoms. The
electron collisions increase the amplitude of the atomic vibration and increase the
temperature. This is why NiCr is an efficient material for converting electrical
energy into thermal energy (toaster effect).
(2) Thermal Gradient - From an analysis of heat flow in a fuse, it has been shown
(see th~ Transient Heat Flow Analysis section), Figure 6, that the temperature
profile across a fuse neck is flat. The gradient occurs at the neck-to-fuse body
interface. But the programmed gap occurs in a region where there is no temperature
gradient. Further, this model would predict a symmetric distribution of mass,
post-programming which is not observed. Temperature gradient does not cause
the mass transport.
(3) Concentration Gradient - It has been shown in unprogrammed fuses that no concentration gradient exists. Laterally in the fuse film this is borne out by the TEM/
probe analysis. That is, no nickel or chromium concentration variations are observed across an unprogrammed fuse. Vertically (distribution of nickel, chromium
through a cross section of the resistor) it has been shown 20 , from sputter etching
Auger analysis that the nickel and chromium are distributed uniformly through
the film (no concentration layering effects).
Because there is no concentration gradient initially, this is ruled out as a starting
mechanism for fusing.
(4) Field Enhanced Ionic Mobility - Eyring and Jost 18 have observed that liquids have
a fixed ratio between their energy as a liquid and the energy required for vaporization, see Figure 7. Stated simply, the principal is, the more cohesive the liquid,
the more energy is required to transform it to the gaseous phase, and the ratio is
a constant. This rule held for all types of liquids (gases, solvents, organics, etc.)
except metals. But by accounting for ionization of molten metals and the subsequent reduction in atomic radii, see Table II, they found that metals obeyed the
liquid:gas constant energy ratio. In other words, molten metals are ionic.
It follows then that these positive ions (they have given up outer shell electrons)
will move in the presence of an electric field (from the programming pulse) toward
the negative terminal, opposite to the direction of electron flow. This is consistent
with the TEM observations and with some investigations of electromigration. For
example, Wever 25 observed in copper above 9500 C, that mass flux was toward
the cathode.
In summary, NiCr fuses program as follows:
A programming pulse of sufficient
power is applied across the fuse. Power dissipation in the fuse neck heats this
region into the molten state and the nickel and chromium atoms become ionized.
They move toward the negative side of the fuse and the liquid film begins to diintegrate.
The film becomes electrically discontinuous and rapidly returns to the
solid state, the final structure resembling a frozen splash described by fluid dynamics. The fuse gap consists of insulative oxides of silicon and chrome, with
resistance >10 megohms.
Footnote: Arguments have also been advanced that oxidation is the mechanism of fus;ing 19, If this were so, the probe data,
which discerns elemental presence, would not show nickel and chromium depletion in the gap region, i. e., mass
transport, per se, would not have occured. 8ecause the TEM data clearly indicates mass transport, attention is
focused here on identifying the driving force for that mass transport.

7-14

TRANSIENT HEAT FLOW ANALYSIS
The previous discussions dealt with the fusing event postfacto, describing the microscopic
material structure created by programming. The dynamics of the fusing event can also
be characterized. By modeling the fuse structure and its environment in terms of classical
heat flow, the connection between electrical and material behavior of fuses can be established.
A computer thermal analysis program called "TH EROS" 21 was used to calculate the dynamic temperature effects in a PROM-fuse structure as a function of applied power density.
This computer program can thermally model a multicomponent structure and calculate
the temperature as a function of time for given power dissipation conditions. The program
takes into account temperature dependent thermal properties of the various materials and
models a 2-dimensional multimaterial, multigeometrical structure into a RC circuit network
that can be analyzed by sophisticated transient circuit analysis programs. This approach is
convenient because the differential equations that describe heat flow problems have the
same form as differential equations for RC circuit networks. For example, specific heat
is analogous to capacitance, thermal conductivity is analogous to the inverse of resistance,
temperature is analogous to voltage and heat flow is analogous to current. By way of the
"THEROS" heat flow to electrical analog program, the sophistication available with present
circuit analysis programs can be utilized to solve complex heat flow problems without
consuming hours of computer time and without the errors prevalent in more simplified
calculations. For the heat flow model to be truly representative of the actual device, the
immediate environment of the fuse must be completely accounted for. For example,
the passivating oxide layer on top of the fuse will affect the heat flow and the subsequent
structure of the programmed fuse. Programming a fuse without the passivating oxide 22
will result in a different structure than occurs in an actual PROM circuit.
The term "power density" is defined as the amount of power that is dissipated in the fuse
neck region divided by the area of the fuse neck (watts/miI 2 ), see Figure 8. The concept
of defining power density as power per unit surface area is applicable to thin film heat
flow problems where the heat is dissipated through a surface. (The concept is analogous to
defining current density as current per cross sectional area). Figure 9 shows a plot of the
computer results giving the temperature in the center of the NiCr fuse that would
be achieved if a constant power were applied for a time t. The curves show that the fuse
can easily reach the melt temperature of NiCr 23 within microseconds for power densities > 2.5 watts/mil 2 .
Figure 10 is a plot of the intercept of the time to reach the melt temperature (1450 0 C) vs.
the power density. This theoretical prediction of the power density versus time to reach the
melt temperatures compares well with experimental data on time to fuse. The data in
Figure 10 was taken from test vehicle fuses, processed identically to circuit fuses, but
free of interfacing circuitry. This allowed precise characterization of fuse-pulse interactions. The data matches for long fusing time but deviates for short fusing time. This
difference can be accounted for by considering the definition of "time to fuse". The
experimental data points represent total time to fuse which includes rise time of the programming pulse, time for the fuse to heat to sufficient temperature, and time of the actual
fusing event. For example, Figure 11 shows a typical current trace for a fuse programmed
under constant voltage conditions. The trace shows a fixed rise time, tr (about 100 nanoseconds for this data), a response time, tm, for the NiCr to reach the melt temperature,
and a time for the fuse neck to enter the melt phase and program, tf. Plotting the time
defined as tm shows excellent correlation with the theoretical prediction of the time to
reach melt temperature. The difference between the theoretical prediction to reach melt
and the actual time to fuse agrees with the measured values of tr + tf. Figure 10, therefore,
shows that fusing follows a heat flow dependence that requires the NiCr to achieve
melt. Proper PROM design necessitates taking into account thermal factors that affect the
heat flow conditions in the neighborhood of the fuse. Concentrating power by optimum
fuse geometry and ensuring sufficient power to the fuse will achieve fast, uniform programming.

7-15

•

For power density conditions below the programming threshold level, the fuse temperature
as a function of power density into a fuse for a sustained pulse (t --- Q) ) is shown in Figure
12. There is good agreement of the computer model with experimental data. The experimental data was derived from measuring the fuse resistance (at reduced current, avoiding
12R heating) of an externally heated fuse and comparing that to the power necessary to
generate the same resistance at an ambient temperature of 25 0 C. The agreement between
model and experimental data is a further indication that the heat flow analysis is correctly
projecting the temperature in the fuse.
It is also relevant to note the low power density on a fuse in the read mode, 5% of the
threshold power density to melt the NiCr fuse. Test vehicle fuses were stressed at
1 watt/mil2 which is 65% of the fusing threshold level and equivalent to a fuse temperature
of BOOoC. No failure occured after 4000 hours of continuous operation. Thus, the designed power density for PROM operation in the read mode avoids the occurence of unprogrammed fuses becoming open.
In summary, the power density vs. time to program curve, Figure 10, agrees with the heat
flow model and implies a single mechanism, melting for both fast and slow fusing. High
power fusing (fast blow) approaches adiabatic heating conditions and therefore gives a large
melted region and wide gap. Restricted power programming (slow blow) allows much of the
heat to diffuse away taking longer for the fuse to reach melt.
MARGINALLY PROGRAMMED FUSE
By grossly violating recommended programming procedures for fuses, it is possible to
create a marginal fuse gap that may be subject to reverting state ("growback"). This anomaly was induced in a test vehicle fuse by restricting the power input to a value on the t
-+0> asymptote ( rv 1.5 watts I mil2 ) of the power density vs. time to fuse curve (Ref.
previous section, Figure 10). Under these conditions, a fuse was induced to program,
become electrically discontinuous, after 5 minutes of sustained power. This effect, programming under an anomalously reduced power, was not found to be reproducible. Many
fuses at this power would not program after days.
This deliberately improperly programmed fuse was subsequently subjected to a slowly
applied DC voltage ramp under current limited conditions (10M resistor in series). At 12
volts, the fuse resistance dropped to rv 5000 ohms. The TEM photograph of this fuse is
shown in Figure 13. It is obvious from this photograph that the reduced power condition
has resulted in a fuse that has marginally programmed. That is, the gap created after programming is very narrow (approximately a few hundred angstroms) and subject to a voltage
breakdown effect.
Fuses programmed per the recommended power levels will program rapidly with a wide
gap as illustrated in the Mass Transport Models section. These fuses can be subjected to
more that 100 volts and will undergo no change in electrical or physical condition.
As indicated in Figure 13, if a restricted amount of power is applied to a fuse, it is possible
to create a very narrow gap. Under the presence of high voltage and extreme current
limiting, it is then possible to force a voltage breakdown across the gap. It is postulated
that this voltage discharge results in the establishment of a low conductivity relink at one or
a few points of closest approach in the marginally blown gap. This specific structure could
not be confirmed with the TEM study because even the TEM did not have resolution to
examine microstructure at < 300 angstroms.
This mechanism of marginal programming is precluded from occuring in an actual PROM
circuit because the programming specification, specifically the power and pulse widths,
have been established to only generate well blown, wide gap fuses. That is, if the power
actually reaching a fuse is lower than that required to blow the fuse properly, the fuse
will not program in the time allotted for the programming pulse. The device, therefore,
becomes a programming reject (won't program) and is scrapped.

7-16

In summary, the observation that a NiCr fuse can be marginally programmed has no connection with the reliability of the PROM circuit.
Recall, to generate this anomaly, a
power density four times less than the designed value and a program time rv 108 times
longer than the maximum specified programming time was required. Further, a voltage
'"'-'10 times higher than the maximum that would be seen in an actual PROM, (with current
limiting) was required to cause the relink.
Obviously, these observations and conclusions are based on NiCr fuses, PROM design, and
Contentions by others that a specific fuse
control procedures as deployed by Harris.
material, NiCr or something else, is more or less reliable must be interpreted in perspective of the manufacturer's technology and not necessarily be construed as being generally
representative.
LIFE TEST RESULTS
Life testing data of programmed PROMs has been accumulated for several years of production. The data in Table III summarizes those results. The total sample base represents
a multiplicity of designs and configurations (0512, HPROM series 2nd state-of-the art
GPROMs). These samples were selected from unburned in production runs that had passed
the standard final test program and were programmed to data sheet programming procedure.
The I ife test conditions are representative of typical applications (except for elevated temperature). The results indicate that the level of reliability of these PROM circuits is equivalent
to circuits of similar complexity that do not utilize fusible links.
SUMMARY
(1) Conduction electrons in NiCr have a short mean-free path. This maximizes 12R heating
and precludes electromigration in the direction of electron flow as a fusing mechanism.
(2) Transmission electron microscopy is the only effective analytical tool to characterize
the programmed fuse gap structure.
(3) NiCr fuses program by molten metal (nickel, chrome), ions moving in the presence
of an electric field. The final structure resembles a frozen splash and is described by
fluid dynamics.
(4) Thermal analysis coupled with empirical programmed fuse data indicate a threshold
power density for fusing. If this power density is exceeded, which can be assured if
the programming time utilized is as specified, the fuse gap will be wide and reliable.
If this power density threshold is only matched, it is possible to create a marginal
fuse.
(5) Life test results indicate programmed PROM reliability is equivalent to devices of the
same complexity that do not utilize fusible links.

REFERENCES
1. Press Release, Harris Semiconductor, May 4 1970
2. MO,R. S. and Gilbert, D. J., J. Etectrochem. Soc., 120,
7 pp. 100-1003, (1973).
3. Jones, K. W., Plasma Etching as Applied to Failure
Analysis, 12 Annual PrOt:eedings IEEE, Reliability Physics

Symposium, pp. 43-47.1975.
4. 2iman, J, M., Electron and Phonons -

Transport Phenomena in Solids, Q)(ford Press, 1972.
L., Thin

15. Huntington, H. B., and Grone, A. J., Phys. Chem. Solids,
20,76 (196l).
16. Soret, Ch., Arch. de {Geneve, 3, 48 {18791.
17. Fick, A., Pogg. Ann, 95, 59 (18851.

The Theory of

5, Coles, B. R., PhY5. Soc., B, 65, 221.
6. Chopra, K.

14. Kenny, G. B., Fusing Mechanism of Nichrome Resistors
in PROM devices, M. S. Thesis, MIT, June, 1975.

Film Phenomena, McGraw-Hili,

1969.
7. Nagata, M. et aI., Proc. Elec. Compo Conf" 1969.
8. l. Holland, "Thin Film Microelectronics". p. 17-19,
Chapman and Hall, Ltd., {1966J.

9. Nat. Bur. of Standards Publ. 296, Ed. by Wachtmon,
J. B., et aI., p. 125, (19681.
10. Wells, A. F. "Structural Inorganic Chemistry", P. 379,
Oxford Press (1950).
11. Philofsky, E. et al., Observations on the Reliability of
NrCr Res:stors, 8th Annual Proceedings IEEE, Reliability
PhYsics Symposium, pp. 191-199, 1970.
12 Jones, K. W., et aI., Fusing Mechansim of Nichrome
Resistor Links in PROM Devices, 14th Annual Proceedings IEEE, Reliability Physics Symposium, 1976.

18. Jost, W., Diffusion in Solids, Liguids, Gases, p. 470,
Academic Press (19601.
19. Franklin, P. and Burgess, D., Reliability Aspects of
Nichrome Fusible Link PROM's, 12th Annual Proceedings
IEEE, Reliability Physics Symposium, pp. 82-86, 1974.

20. Davidson, J. L.,

PROM Reliability. Presentation at
NEPCON, Boston, Mass., October 1974.

21. Rossiter, T. J., THEROS, A Computer Program for
Heat Flow Analysis, RADC Technical Report - 74-113,
1974.
22. Advertisement, Fairchild Semiconductor, "ELECTRONICS", p. 39, July 24, 1975.
23. Bechtoldt, C. J. and Vacher, H. C., Trans AI ME Va.
221, p. 14, (19611.
24. O'Heurle, F. M., Proc. IEEE, 59,10 (Oct. 1971).
25. Wever, H., Z. Elektrochem., 60, p. 1170 (1956).

13. Harris Integrated Circuits Data Book, pp. Me-28-55,
August, 1975.

7-17

•

CONDUCTION PROPERTIES OF NiCr

OXIDATION OF NiCr

eNICKEl AND CHROMIUM ARE TRANSITION METALS.

• NiCr FORMS SELF LIMITING SKIN OXIDE

elNNER SHELL ELECTRONS CONoutr,oUTER SHELL SHIELDS. HIGHER RESISTANCE.

• SPINEL

eALLOY EFFECT ENHANCES SHIELDING/RESISTIVITY.

150

DiffUSION
COEFFICIENT

__ x
120

(".Ucm)

THICKNESS~20.&

• PROMOTES RESISTOR STABILITY

ci/

Cr in

IREF.AI

r'\

/
/

O-REF.A

0- REF. 8
X - REF. C

T lOCI

SPINEL GENERAL
FORM (REF. B)

AB204

INIC'2041

100%

WEIGHT %

METALLIC

A - Handbook 01 Chemistry and PhYSICS.
B - Thin Film Technology. A. W. Berry, et. al
C - Japanese Metal Material Handbook, Y Yamamoto, et. al.

Ref. A ~ "Mass Transport in Oxides," NBS Publ. 296, (1968),
Ref. B - A. F. Wells, "Structural Inorganic Chemistry", Oxford Press (1950),

Figure 1

Figure 3

FILM VS. BULK PROPERTIES

SCANNING TRANSMISSION ELECTRON
MICROSCOPY ANALYSIS OF FUSES

• SHORT MEAN FREE PATH LENGTH OF ELECTRONS

• BULK RESISTIVITY IN THIN fiLM.

• GooO FILM REPRODUCIBILITY

I I

P, FILM RESISTIVITY
Pb BULK RESISTIVITY

NiCr

1\ (ref.

(ref.

....

-- - ----- --- -10

_ ••

o in NiCr2'J4

'\)

o(cm2)
SEC

NiCr2~

Ni in Ntcr~4 -----

100

'-.

---- --- --500

200

FILM THICKNESS f

DETECTOR

1000

A - M. Nagata, et. aI., Proc. Elee, Comp. Conf., 1969,
B - K. L. Chopra, Thin Film Phenomena,

McGra""'~Hill,

1969.

Figure 2

Figure 4

7-18

STEM PROGRAMMED FUSE
PROGRAMMING CONDITIONS:
POWER'" 150 mW.

TIME TO Fuse", 2

~SEC.

• Liquified gases
Other liquids
n Alcohols

>.;;;

§
;

....,

10
.l E of vaporization

Fig. 11-24. Empirical relation between free energy of activation in liquids, .IF, and
energy of evaporation, olE, Rosevaere. Powell and Eyring,

TABLE II

Corrected ratio of energy of vaporization and activation for viscous flow
)It'tal

POINT MICROPROBE ANAL VSIS

)Oil.

A-NiCr

I--

B - MEL TEO NiCr
C - Si02, CHROMIUM OXIDE
o -Si02
E - DENSIFIED NiCr
F - FIELD OXIDE (Si02)

GA' REGION

\
,

~;,~~~1lY

NOTE: (AI "FROZEN SPLASH" EFFECT
PROGRAMMING HAS MELTED
NiCr IN' GAP REGION.
(8) MASS TRANSPORT IN GAP.
Ie) MASS ASYMMETRY TO NEGTIVE TERMINAl.

Zn
Cd

,,cr--o---o-

--o---o.~

PROBl

K
Ag

--l

Hg
Hg
Sn
Sn

""0---0- - -0'

--0---0--\
'().oo_

AverASf'

temp. cc.
500
480
1400
850
750
800
700
250
600

600
1000

.1 Eoop keal. .JE•.,..,.kcal.

23 .•
19.0
60.7
26.5
22.5
3•. 1
.2.6
13.6
12.3
15.3
14.5

1.45
1.13
•• 82
3.09
1.65

1.13
2.80
0.65
0.615
I. ••

1.70

.JErap
~

.J E NP ( ' ' ' " ) '
.JEl'llf ;:;;;;;;;

16.1
16.7
12.5
8.6
13.5
30.3
15.9
20.8
22.2
10.6
8.6

2.52
3 .• 1
3.79
2.10
3.96
2.53
•• 97
2.37
3."
••07
3.30

,--0---0---0-

,--a

From "Diffusion in Solids, liquids, Gases", W.•Iost.

Figure 5

Figure 7

TEMPERATURE PROFILE IN FUSE NECK
FROM HEAT FLOW MODEL

POWER DENSITY IN FUSE NECK REGION

FUSE
STRUCTURE

POST
PROGRAMMING

POWER DENSITY = (21 p./Jw)
a·w)
1.0
TEMPERATURE
PROFilE DURING
PROGRAMMING

0.9

( T1 - T. )
1ma)!. - Ta

0,8

0.7

P.L/w =
1

\
\

P, =

0 .•

0.5

L.w=

Figure 6

RESISTANCE OF THE
FUSE NECK (OHMS)

LENGTH OF FUSE
NECK

SHEET RESISTIVITY OF
NICHROME (OHMS/Sa)

WIDTH OF FUSE NECK

PROGRAMMING
CURRENT ( ( = VF/RF)

AREA OF FUSE NECK
(MIL.2)

Figure 8

7-19

•

DYNAMIC HEATING OF NiCr FUSE
VS.
POWER DENSITY
3500

3000

2500

2000

"''"::>
~

ffi"

1500

2.5

1000

1.6

MelT TEMPERATURE Of NiC,

500

100

1000

10,00

TIME (",SEC)

Figure 9
POWER DENSITY VS. TIME TO FUSE
(t, + t,l

I-IJ/'

TYPICAL CURRENT TRACE
OF PROGRAMMING PULSE
tf::::500ns

~~
a: a:

sa
a:

NiCr IN MELT PHASE

II
I
I

Ii---tm --IIItf

t f .. RISE TIME

tm ... TIME FOR NiC, TO REACH
MELT

t, '" TIME FOR NiC, TO PROGRAM

•

COMPUTER PREDICTION Of TIME
FOR NiCr TO REACH MELT (lm)
. . . . EXPERIMENTAL RESUL T8 OF TOTAL
TIME TO FUSE {t, + tm + tpl (t, ~ lOOns)
EXPERIMENTAL RESULTS OF TIME TO
iii

MELT Itml

100

1000
TIME (PSI

Figure 10

7-20

10,000

100,000

1 SEC.

PROGRAMMING PULSE CHARACTERISTICS

I
....2
w

a:
a:
::>
u

TIME (50Ons/cm)

tr = RISE TIME OF PROGRAMMING PULSE
1m =

TIME FOR NiC, TO REACH MELT

If =

TIME OF THE FUSING EVENT (IONIC MASS TRANSPORT)

Figure 11

MAXIMUM FUSE TEMPERATURE VS. POWER DENSITY

",I
/1
I

103

...

IPROGRAMMING I
MODE

~
ili...

";:.
:>

102

x
-MODEL

-x- EXPERIMENTAL DATA
@ NICHROME MELT TEMPERATURE

t--

READ MODE--1

'O'.~O,~--~--L-~~~~.,L---~--~~~~~~,----~--~~~~~,O
POWER DENSITY (WATTS/Mll2,

Figure 12

7-21

•

MARGINALL Y PROGRAMMED TEST VEHICLE FUSE
PROGRAMMING CONDITIONS:
POWER DENSITY = I.SWATTS/MIL2
TIME TO FUSE = 300 SEC.

FORCED RELINK OF MARGINALLY PROGRAMMED TEST FUSE

10M!!

SLOW RAMP
D.C.

AT 12 VOLTS.
RF DROPPED TO::eSKU

PROGRAMMED
TEST VEHICLE
FUSE

Figure 13
OPERATING LIFE TEST RESULTS
#DEVICES
ALL PROM TYPES

7681

#DEVICE-HRS. #FAILURES
5(3) (5)

15,439.914

DERATED
to 50(S)oC
(TYPICAL
IN USE)

LIFE TEST & BURN-IN SCHEMATIC

ACTUAL
FAILURE RATE

FAILURE RATE
@60%C. L. (1)

0.03%/K H RS(4)
OR 300 FITs
(MTTF - 3.3 x 106
HRS)

0.04%/K HRS(4)
OR 400 FITs
(MTTF - 2.5 x 106
HRS)

0.0002%/K HRS
OR 2 FITs

O.00026%/K H RS
OR 2.S FITs

lFIT (FAILURE UNITI = 1 FAILURE IN 109 DEVICE-HOURS

VCC

(11

C.L. (CONFIDENCE LEVELl

(21

FUSE MATRIX: 50% PROGRAMMED
RANDOM PATTERN AS PER PRESCRIBED
PROGRAMMING PROCEDURE.

(31

NON-FUSE RELATED FAILURES

(41

SAME OR BETTER THAN MSI FAILURE
RATES (REF. MDFR 1273-ROME AIR
DEVELOPMENT CENTERI

(51

16B-HOUR NOTED FAILURES.

(61

1.0eV ACTIVATION ENERGY

30o.Q :120%

031-----'

TA =+12SoC
VCC =S.SV
1KHz = 1M = 210=411 = 812 = .•..

Table III

7-22

Microscopic Observations of Fuses

Beauty is in the eye of the beholder. When the eye is attached to a microscope, beauty
can take strange forms. Nowhere is this more evident than when the realm of blown fuses
in PROMs is entered. This paper will "shed some light" on the misinformation which
has been generated regarding the nature of NiCr fuse gaps as viewed by different microscopic techniques.
WHAT YOU SEE OPTICALLY
Using a light microscope to examine fuse structures is a futile exercise because the wavelength of visible light is within an order of magnitude of the total fuse dimensions. The
microstructure of the fusing process reaction zone contains formations that are smaller
than a wavelength of light. In addition, the overlying passivation acts like an aberrant lens
and distorts the image which is visible. The most that can be reliably ascertained regarding
the nature of a fuse with optical microscopy is whether the fuse is physically present or
absent.
Photo 1* illustrates this physical phenomenon. The photograph is of photoresist after exposure to ultraviolet light and normal developing solutions. The ridges in the vertical
portion of the photoresist are produced by the standing wave that is present due to reflection of the U.V. light from the oxidized silicon during resist exposure. As can be seen,
the ridge pattern has a wavelength A of the incident light ( A = 3650nm), the index of
refraction of the photoresist is n = 1.58; thus, for visible light on the order of A = 5000nm,
less than ten wavelengths are needed to span the fuse neck region.
WHAT THE SCANNING ELECTRON MICROSCOPE SHOWS
The SEM is a useful analytical tool for many applications. This is amply demonstrated by
Photo 1 that showed us the standing wave pattern in photoresist.
The SEM does have limitations in observing fuses, however. For one, it cannot "see"
through the passivation layer on top of the fuse.
This necessitates the removal of the
glassivation and hence, physical and chemical alteration of the fuse gap microstructure.
In addition, the results after depassivation are misleading. A SEM of a depassivated typical
programmed NiCr fuse is shown in Photo 2. Photo 3 is a typical programmed polysilicon
fuse as deployed in the CMOS PROM.
Previous observers have never reached satisfactory explanations for the fusing phenomena
based on SEM photographic evidence. The important facts to consider here are that for
both fuses, an electrical discontinuity has been achieved through programming. In both
cases, the observer is hard pressed to determine how this was achieved, for his eyes tell
him that both fuses appear physically connected in various areas. Electrically, we know
this is not the case.
This brings us to the crucial observation that the SEM cannot distinguish between electrical conductors and electrical insulators. This is readily confirmed by observing the lack
of differentiation afforded in the SEM view of the adjacent aluminum interconnect (an
excellent conductor) and the underlying silicon dioxide (an excellent insulator). Since both
of the above fuses ilre electrically discontinuous, some portion of their makeup is insulative,
but the Scanning Electron Microscope gives us no clues as to the integrity of the insulator .

• Photos found on pages 7-25 thru 7-27.

7-23

•

TRANSMISSION ELECTRON MICROSCOPY ANALYSIS OF FUSES'
A fresh approach in fuse analysis has been developed to view a fuse without disturbing
the conditions present at the time of programming. Basically, the technique uses a thinned
specimen PROM with the fuses sandwiched between the two normal glass sheets found on
the PROM (the passivation above and thermal oxide below) with the underlying silicon
substrate etched away as shown in Photo 4. Now standard high resolution bright and
dark field TEM (Transmission Electron Microscopy) analytical techniques are available.
Photo 4 is a TEM photograph of a typical programmed NiCr fuse. Now we can see which
regions of the blown fuse are conductive metal and which are not. The well-defined darkened regions are metallic while the overlying gray, which is all that was seen by SEM,
has proven by electron diffraction analysis to be a stable insulating oxide compound with
crystalline order that resembles a NiCr204 spinel. The surrounding region of high transmission are characteristic of the undisturbed passivation and underlying thermal Si02.
Therefore, Transmission Electron Microscopy has the capability of determining the true
chemistry of programmed NiCr fuses .

•
7-24

PHOTO 1A

•
PHOTO 1B

7-25

SEM Photographs of Programmed Fuses

PHOTO 2A

PHOTO 3A

PHOTO 2B

PHOT03B

7-26

PHOTO 4

7-27

Section 3.

Reliability Screening Programs

Reliability Screening Programs
Facility Qualification
Harris is closely attuned to the requirements of military quality and reliability manufacturing programs. Our facilities and its quality plan is well accepted at all major companies.
In addition, we have JAN qualification in the Bipolar Memory area and have JAN qualifications in process on CMOS Memory and Analog products.
MIL-STD-883B-Class B (Dash 8)
As a special service to users of Hi-Rei products Harris makes instantly available high reliability on many of our product lines. Simply by adding its postscript -8 to appropriate
Harris part numbers "off the shelf" delivery can be obtained of products screened to M I LSTD-883B Method 5004 Class B.

Hi-ReI Program
To meet our commitment to CMOS growth, Harris has introduced the Hi-Rei Dash 8 program. This program is designed to meet the needs of the customer seeking enhancef;l quality
and reliability by additional screening steps.
This program is designed for:
• Customers using a current reliability add-on program.
•

For the individual seeking a trade-off between additional cost and improved reliability
and quality through screening - Harris gives a broad selection from Class B flow to
burn-in only.

The Harris Hi-Rei Program is a comprehensive program aimed at serving the various needs
of many customers. With the increasing need for improved IC systems mean time to failure
performance, the Hi-Rei program assures high quality and reliability of CMOS circuits.
Harris CMOS devices' have been produced for over 6 years in modern state of the art manufacturing facilities. Our implemented second and third generation mask designs with the
experience of well-controlled processes, results in standard products with built-in reliability.
Coupling Harris CMOS with a Hi-Rei Program will result in an enhanced combinations
for quality and reliability.
User Benefits
• Eliminates user screening programs

• Provides uncomplicated incoming inspection
• Reduces infant mortality and board rework

• Reduces field failures and unnecessary maintenance costs
Quality
In theory, parts tested 100 percent should upon receipt at the user's site be 100 percent
good. Due to volume production there may exist a small percentage of parts
which escape 100 percent tests. The AQL or L TPD outgoing sampling plans at Harris
have been very successful in stopping the DOA's (Dead on Arrival). For the user with complex systems using large quantities of products, a quality enhancement can be tailored into
your specific Hi-Rei Program by choosing tightened sampling plans. The tightened quality
test plan ensures close maintenance of the improved quality level throu'gh careful product
segregation and retesting.

7-28

Reliability
Experience and perfected process controls have built reliability into a standard Harris
CMOS product. Reliability cannot be tested into a part. Quality level may be improved
by retesting and tighter sampling plans. However, reliability is improved by proper design
and observance of sound ground rules, controlled processes and finally by stress testing
to confirm claimed reliability performance. The Hi-Rei program offers a varied mix of
stress tests to compress time and weed out devices subject to infant mortality. The equivalent early life failures are removed by the various screens such as temperature cycling,
stabilization bake, burn-in and high temperature functional testing. Some or all of these
stress tests will remove early failures and thus improve overall system reliability.

Dash 8 Program -

MIL-STD-883B;!Off-the-Shelf Delivery; MIL-STD-883/MIL-M-38510,

INTRODUCTION
Statement of Scope
This section establishes the detail requirements for HARRIS circuits screened and tested
under the Product Assurance Program.
The Harris DASH 8 Devices pass the screening requirements of the latest issue of MILSTD-883B, Method 5004, Class B, and the requirements as specified in this document.
Included in this section are the quality standards and screening methods for commercial
parts which must perform reliably in the field.
Applicable Documents
The following Military documents form a part of this section to the extent referenced
herein and provide the foundation for Harris Products Assurance Program.
MIL-M-38510
MI L-Q-9858A

"General Specification for Microcircuits"
"Quality Program Requirements"

MI L-STD-833B

"Test Methods and Procedures for Microelectronics"

NASA Publication 200-3

"Inspection System Provisions"

Harris maintains a Product Assurance Program (PAP) using MIL-M-38510 as a guide.
Harris Product Assurance Program assures compliance with the requirements and quality
standards of control drawings and the requirements of this specification.
The DASH 8 Program will also be found useful by those Harris customers who must generate their own procurement specifications.
Use of the enclosed Harris Standard Test
Tables, Test Parameters, and Burn-In as described in Section 4 will aid in reducing specification negotiation time.
PRODUCT ASSURANCE AT HARRIS
Our Product Assurance Department strives to assure that the quality and reliability of
products shipped to customers is of a high level and consistent with customer requirements.
During product processing, there are several independent visual and electrical
checks performed by Reliability and Quality Assurance personnel.
Prior to shipment, a final inspection is performed at Quality Assurance Plant Clearance
to insure that all requirements of the purchase order and customer specifications are met.
The system and procedures used and implemented are in accordance with MI L-M-38510,
MIL-Q-9858A, MI L-STD-883 B, MIL-C-45662 and MIL-I-45208.
The Harris Semiconductor Products Division Reliability and Quality Manual, which is available upon request, describes the total function and policies of the organization to assure
product reliability and quality.

7-29

•

HARRIS SEMICONDUCTOR DASH 8 PRODUCT FLOW
MIL-M-38510/MI~-STD-883, METHOD 5004 CLASS B
100% SCREENING PROCEDURE

SCREEN

MIL-STD-883 METHOD/COND.

Internal Visual

2010 Condo B.

Stabilization Bake

1008 Condo C (24 hrs. minimum)

Temperature Cycling

1010 Condo C

Constant Acceleration

2001 Condo E; Y1 plane

Seal:

® Fine

1014 Condo A or B
1014 Condo C

@ Gross

NOTE:

Initial Electrical

Harris Specifications

Burn-In Test

1015,160 hrs. @ 1250C (or equivalent) (Burn-In circuits enclosed)

Final Electrical
100% go-no-go

Tested at Worst Case Operating
Conditions

External Visual

2009 Sample Inspection

Lot Acceptance

Table I, Group A Elect. Tests

Group A, Subgroup 1,2,3, & 9 for Bipolar-Table 1, Subgroup 2 & 10 for CMOS.

Traceability:

All devices are assigned date code identification that provides traceability
back to the inspection lot.

Branding:

All devices are branded with the HX-XXXX-8 and EIA date code.

Aged Products:

Product that has been held for more than 24 months will be reinspected
to group A inspection requirements prior to shipment.

Additional
Requ irements:

Attributes data on Group A Lot Acceptance will be supplied upon request.

Generic data from Harris' Reliability Add-On Program is available upon request. The objective
of Harris Reliability Add-On Program is to provide a continuous life and environmental
monitor for all products· families in manufacturing. This program provides life test performance results to fullfill reliability data requirements and to verify package integrity. The
Reliability Add-On Program is supplemental to customer funded Lot Qualification.
For customers desiring Lot Qualification, Harris Semiconductor will perform Group A, B, C
and 0 inspections to M I L-STD-883, Method 5005 as defined herein for an additional charge.

7-30

Standard Products Screening and
I nspection Procedure
PRODUCT CATEGORIES
MIL
1M)

COMM
IC)

EPOXY
IE)

Incoming Material
Silicon and Chemical Procurement.

O.C. Incoming Inspection. Materials
are Inspected for Conformance to
Specified Requirements.

Manufacturing Wafer Fabrication

Manufacturing, Wafer Electrical
Probe (100%)

Manufacturing, Wafer Scribe,
Break (100%)

Manufacturing Dice Screen (100%)

OA Dice Inspection Control

Preform Procurement
Package Procurement
Leadframe Procurement
Epoxy Compound Procurement

X
X

N/A
N/A

O.C. Preform Inspection
O.C. Package lr1spection
O.C. Leadframe Inspection

X
X

Manufacturing Package Clean

N/A

Manufacturing Die Mounting

OPER. SEQ.

M
C
E

OPER. DESCRIPTION

M
C
E

• DIH20 & Gas Monitor
• SEM Process Control
• Wafer Process Control

7-31

X
X
X
X

N/A
N/A

•

M
C
E

QA Die Mount Control
(continuous sampling)
• Visual Die Inspection

Bond Wire Procurement

Q.C. Wire Inspection (receiving)

Manufacturing Wire Bonding

X
AI

X
Au

QA Bond Control (continuous
sampling)
• Visual Die & Bond Inspection
• Wire and Pull Test

MS883
Method
2010
Condo
Aor B

MS883
Method
2010
HS
Mod.
Condo
B

MS883
Method
2010
Condo
Aor B

MS883
Method
2010
HS
Mod.
Condo
B

Preseal Bake Per MS-883,
Method 1008, Condo C

8 hr.

4 hr.

Package Lid Procurement

N/A

Package Lid Inspection

N/A

Package Lid Clean

N/A

Package Seal/Encapsulation

QA Package Seal/Encapsulated
Control (continuous sampling)

Manufactu ri ng Pre-Seal Screen
(100%)

QA Pre-Seal Inspection
Lot Acceptance

M
C
E

•

M
C

M
C
E

7-32

Stabilization Bake
MS-883, Method 1008, Condo C.

24 hr.

8 hr.

N/A

Centrifuge, MS-883, Method 1010,
(Vl) Plane 30 KG's min.

100%

N/A

Fine Leak, MS-883, Method 1014

100%

N/A

100%

N/A

Frame Removal & Loading Units
In Carriers/Sticks

Final OA Lot Inspection, MS-883
Method 1014
• Fine & Gross Leak
• Visual/Mechanical Inspection

Group A Initial Tests
Table 1

Brand Device Type/Date Code
Serialize, If Applicable

N/A

Burn-In (100%)' MS-883,
Method 1015

Classes
A/B
Products

N/A

Group A Final Test 1.
(Worst Case Oper. Cond.)

N/A

OA Acceptance Elec. Testing
• Visual/Mechanical Method
2009 Lot Sampling

Brand Devices Type/Date Code

N/A

Temperature Cycle, MS-883,
Method 1010, Condo C,

Gross Leak, MS-883, Method 1014

M
C
E

C
E

C
E
M
C
E

Controlled Inventory

7-33

•

M
C
E

NOTE:

Package for Shipment

Quality Conformance Inspection
Group B/C/D Testing, MS-883,
Method 5005, Periodically or by
Customer P.O. Request

QA Plant Clearance
• Final Visual of Marking and
Physical Quantity, Conformation
of Product py Inspection or
Sample Test

Ship to Customer

1. Group A, Subgroup 1,2,3, & 9 for Bipolar-Table 1, Subgroup 2 & 10 for CMOS.

Harris Semiconductor Dash 8 Product Flo\N for
CMOS Module Products
I.

LEADLESS CHIP CARRIER 100%, SCREENING PROCEDURE -MIL M-38510/
MIL-STD-883, METHOD 5004 CLASS B

MIL-STD-883 METHOD/COND.
& HARRIS SPECS.

SCREEN
1.
2.
3.
4.
5.

Internal Visual
Stabilization Bake
Temperature Cycling
Constant Acceleration
Seal:
A-Fine
B-Gross

2010 Condo
lOBO Condo
1010 Condo
2001 Condo

1014 Condo A or B
1024 Condo C2
HA R R I S Specifications
1015, 160 Hrs. @ +1250 C
(or Equiv.)
Test at worst case
Operating Conditions
2009, Sample Inspection
Table I, Group A Electrical
Tests S. G:S 2 & 10

I nitial Electrical
Burn-In Test

Final Electrical 100%
Go-No-Go
9. External Visual
10. Q. A. Lot Acceptance

NOTE:

B
C (24 Hrs. Min.)
C
E. YI Plane

Group A, Subgroup 1,2,3, & 9 for Bipolar-Table 1,
Subgroup 2 & 10 for CMOS

7-34

II.

MODULE PRODUCT 100% SCREENING PROCEDURE/HARRIS SPECIFICATION.

MI L-STD-883 METHOD/COND.
& HARRIS SPECS.

SCREEN
Substrate & Capacitor Visual/
Mechanical O.A. Tests
2. Substrate & Capacitor
O.A. Electrical Tests
3. Module Assembly
4. Temperature Cycling
5. Serialization
6. Visual Inspection
7. Final Electrical 100%
Go-No-Go
8. Brand
9. Visual Inspection
10. O. A. Lot Acceptance
1.

HAR R IS Specifications
HAR R IS Specifications
HARRIS Specifications
1010.2 (5 Cycles)

HARRIS Specifications
+250 C DC Tests

-a. A. Monitor
-

HARRIS Semiconductor
HAR R IS Semiconductor

HARRIS Commercial Grade Products
This product is processed on the same wafer fabrication lines, to the same thorough
specification and rigid controls as HI-Rei parts. At wafer electrical probe the product may
be categorized for electrical performance, such as temperature range of operation or maximum output (see specific product data sheet for grading details) by utilizing multiple
colored inks. Defective die are inked with red ink, but, for example, die meeting the
commercial temperature range electrical specifications may be inked with green ink.
The die are then visually inspected and sorted after die separation to a modified Class B
visual criteria. They are then assembled in packages on a controlled assembly line. The ink
used to categorize product performance, such as the green ink, might not be removed from
the commercial grade die. This ink has been chemically characterized as inert and reliability verification confirms there is no effect on performance or operating life of the
parts.
Harris invites any interested customer to review our assembly flow and facilities for information, quality survey, or certification.

7-35

Table I -

Group A Electrical Tests 1.

SUBGROUP 2.

DASH 8& 2
LTPD*
MIL-PRODUCT

LTPD*
COMM. PRODUCT

Subgroup 4
Dynamic Tests at 25 0 C

Subgroup 5
Functional Tests at 250 C

Subgroup 1
Static Test at 250 C
Subgroup 2
Static Test at Maximum Rated
Operating Temperature
Subgroup 3
Static Tests at Minimum Rated
Operating Temperature

Subgroup 6
Functional Tests at Maximum and
Minimum Rated Operating
Temperatures
Subgroup 7
Switching Tests at 25 0 C

1. The specific parameters to be included for tests in each subgroup shall be as specified in the applicable
procurement document or specification sheet. Where no parameters have been identified in a particular
subgroup or test within a subgroup, no Group A testing is required for that"subgroup or test to satisfy

Group A requirements.

•

2. A single sample may be used for all subgroup testing. Where the required size exceeds the lot size, 100%
inspection shall be allowed.
3. Group A, Subgroup 1,2,3, & 9 for Bipolar-Table 1, Subgroup 2 & 10 for CMOS .

7-36

Table II -

Group B Tests (Lot Related)1.
MIL-STD-883

TEST

METHOD

LTPD*

CONDITION

Subgroup 1
Physical Dimensions

2016

2 Devices
(No Failures)

2015

4 Devices
(No Failures)

Subgroup 2
Resistance to Solvents

Subgroup 3
Solderability 3

±. 100 C

2003

Soldering Temperature of 260

2014

Failure Criteria from Design and
Construction Requirements of Applicable
Procurement Document.

2011

(1) Test Condition Cor D
(2) Test Condition Cor D
(3) Test Condition H

Subgroup 4
Internal Visual and
Mechanical

1 Device
(No Failures)

Subgroup 5
Bond Strength 2
(1) Thermocompression
(2) Ultrasonic or Wedge
(3) Beam Lead

NOTES:
1.

Electrical reject devices from the same inspection lot may be used for all subgroups when end point measurements are not required.

Test samples for bond strength may, at the manufacturer's option unless otherwise specified be randomly
selected immediately following internal visual (precap) inspection specified in method 5004. prior to sealing.

All devices submitted for solderability test must have been through the temperature!time exposure specified
for burn-in. The L TPD for solderabilitY test applies to the number of leads inspected except in no case shall

Generic data from Harris Reliability Add-On Program in the form of ReliabilitY Bulletins are available upon

less than 3 devices be used to provide the number of leads required.

request.
* Reference Note - Table 1 *

7-37

•

Table III -

Group C (Die Related Tests)

MI L-STD-883
TEST

METHOD

CONDITION

LTPD*

Subgroup 1
Operating Life Test

1005

End Point Electrical
Parameters

Test Condition to be specified (1000 Hrs)

Table I - Subgroup 1

Subgroup 2
Temperature Cycling

1010

Test Condition C

Constant Acceleration

2001

Test Condition E
Yl Axis

Seal

1014

As Applicable

(a) Fine
(b) Gross 2.
Visual Examination

End Point Electrical
Parameters

Table I - Subgroup 1

NOTES:
1.

Visual examination shall be in accordance with method 1010.

When fluorocarbon gross leak testing is utilized, test condition C2 shall apply as minimum.

Generic data from Harris Reliability Add-On Program in the form of Reliability Bulletins are available
upon request ..

* Reference Note -

Table 1

7-38

Table IV -

Group 0 (Package Related Tests)

MI L-STD-883B
METHOD

TEST

CONDITION

LTPD*

Subgroup 1
Physical Dimensions

2016

Su bgrou p 2 4.
2004
1014

Test Condition B2 (Lead Fatigue)
As Applicable

Thermal Shock

1011

Temperature Cycling
Moisture Resistance
Seal
(a) Fine
(b) Gross 6.
Visual Examination
End Point Electrical
Parameters

1010
1004
1014

Test Condition B as a Minimum,
15 Cycles Minimum.
Test Condition C, 100 Cycles Minimum
Omit Initial/Conditioning and Vibration
As Applicable

Lead Integrity
Seal
(a) Fine
(b) Gross 6.
Su bgrou p 3 1.

Table I - Subgroup 1

Su bgrou p 4 1.
Mechanical Shock
Vibration Variable Frequency
Constant Acceleration
Seal
(a) Fine
(b) Gross 6.
Visual Examination
End Point Electrical
Parameters

2002
2007
2001
1014

Test Condition B
Test Condition A
Test Condition E
As Applicable

Table I - Subgroup 1

Su bgroup 54.
Salt Atmosphere
Seal
(a) Fine
(b) Gross
Visual Examination

1009
1014

Test Condition A
As Appl icable

NOTES:

Devices used in subgroup 3, "Thermal and Moisture Resistance" may be used in subgroup 4, "Mechanica'''.

Visual examination shall be in accordance with method 1 004.

Visual examination shall be performed in accordance with method 2007 for evidence of defects or damage
to case, leads, or seals resulting from testing (not fixturing). Such damages shall constitute a failure.

Electrical reject devices from that same inspection lot may be used for samples.

Visual examination shall be in accordance with method 1009.

When fluorocarbon gross leak testing is utilized, test condition C2 shall apply as minimum.

Generic data from Harris ReliabilitY Add-On Program in the form of Reliability Bulletins are available
upon request.

Reference Note - Table 1

7-39

•

Section 4.

Burn-In Circuit Diagrams

MIL-STD-883B, method 1015.2, paragraph 1, states, "The Burn-In test in performed
for the purpose of screening or eliminating marginal devices, those with inherent defects
or defects resulting from manufacturing aberrations which cause time and stress dependent
failures.
In the absence of Burn-In, these defective devices would be expected to result
in infant mortality or early lifetime failures under use conditions. Therefore, it is the intent
of this screen to stress microcircuits at or above maximum rated operating conditions or
to apply equivalent screening conditions which will reveal time and stress dependent failure
modes with equal or greater sensitivity without impairing long term reliability of the BurnIn surviving microcircuits.
Typically a dynamic type of Burn-In is preferred at Harris because of its worst case
conditions. Static Burn-In is applied only where there is a specific customer requirement.
Capability exists for +1250C through +1500C Burn-In usually at HARRIS option. This
enables higher throughput of devices by performing, for an example, a +1500 C, aO-hour
Burn-In which is equivalent to the standard +125 0C, 160-hour cycle.
Actual Burn-In circuits are available on request through Harris field sales office and may
include a variety of schematics, due to the differences in Burn-In oven systems, all of
which are functionally equivalent with regard to the Burn-In objectives .

•
7-40

8-1

Component Ordering Information

PREFIX:

B - 2

6514

H - Harris

PART NUMBER:
OXXX
Diode

FAMILY:

61XX

63XX
64XX
"65XX
66XX
67XX
76XX

A - Analog

C - Communications
o - Digital
I - Interface
M - Memory

TEMPERATURE:
Mat~ices

Microprocessor
CMOS Interface

cMOS RAMs
-

CMOS PROMs
CMOS EPROMs
Bipolar PROMs

VERSION*

Chip Form

CMOS

1 - Ceramic
3 -

6 - 100% 250C Probe
8 - Dash 8 Program
Mil. Std. 8838
g, - -40 oC to +850 C

CMOS ROMs

PACKAGE CODE:

o -

2 - -550Cto+1250C
5 - DOC to +750C

4 - Leadle's Carrier
5 - Substrate and leadless assemby
9 -

10 Volt version

A
B
C

Epoxy

High speed - Low power

Commercial grade
Standard product

Blank

FlatPack

BIPOLAR

* All

A
P
R
RP

versions may not be applicable to every product.
Checic. data sheet,

Redesign - Two level metal
Power Down version

Latched outputs

Latched outputs with
Power Down option

Blank

Standard parts

System Ordering Information

PR~F~X~ar)J
FAMILY:
B - Board & Systems
Z - Documentation

61000

PART NUMBER:

61XXX - Systems

OPTION:

61000-1 - Basic system with 256
words memory

61000-4 - Basic system with 1024
words memory & parallel
I/O port

61001-1 - 4096 word CMOS memory
61001-2 - 2048 word CMOS memory

PACKAGE CODE:
o - Systems

HARRIS DASH 8 PROGRAM
As a service to users of High Rei products, Harris makes readily available via the high reliability DASH 8 program many products from our product lines. Parts screened to MI LSTD-883 Method 5004 Class B are simply branded with the postscript "-8" to the appropriate Harris part numbers, in effect, offering "off the self" delivery. For details concerning
this special Harris program for High Rei users, see the Dash 8 section of this Data Book.
NOTE: At the time of this printing, a new industry Standard Method for production of
Class Band C microcircuits was being defined by JEDEC. Harris intends to implement this
new standard procedure. The procedure embodies all relevant device screening sections of
Mil. Spec. 8838 and 38510D, and is quite similar to our current Dash 8 program. Please
consult your Harris representative if you are interested in procuring parts to this standard
specification.
SPECIAL ORDERS
For best availability and price, it is urged that standard "Product Code" devices be specified,
which are available worldwide from authorized distributors. Where enhanced reliability is
needed, note standard "Dash 8" screening described in this Data Book. Harris application
engineers may be consulted for advice about suitability of a part for a given application.
If additional electrical parameter guarantees or reliability screening are absolutely required,
a Request for Quotation and Source Control Drawing should be submitted through the local
Harris Sales Office or Sales Representative. Many electrical parameters cannot be economically tested, but can be assured through design analysis, characterization, or correlation
with other parameters which have been tested to specification limits. These parameters are
labeled "sampled and guaranteed but not 100% tested".
Harris reserves the right to decline to quote, or to request modification to special screening
requirements.

8-2

Selection Guide

PRODUCT

CERDIP

EPOXY

LEADLESStt

CERPACKtt

Diode Matrices
HM-0104
HM-0168
HM-0186
HM-0198
HM-0410

9H
9H
9H
8e
9H

4U
4U
4U
4U

I nterface Products
HD-4702
HD-6402
HD-6408
HD-6409
HD-6431
HD-6432
HD-6433
HD-6434
HD-6435
HD-6436
HD-6440
HD-6495
HD-15530
HD-15531

4Z
5H
4K
4L
4Z
4N
4Z
4K
4L
4L
4N
4Z
4K
5H

3L
3J
3F
3N
3L
3D
3L
3F
3N
3N
3D
3L

LA
LG
LG
LA
LA
LA
LG
LG
LG
LA
LA
LG
LG

Bipolar Memory
HD-6600
HM-7602
HM-7603
HM-7608
HM-7610
HM-7610A
HM-7611
HM-7611A
HM-7616
HM-7620
HM-7620A
HM-7621
HM-7621A
HM-7640
HM-7640A
HM-7641
HM-7641A
HM-7642
HM-7642A
HM-7642P
HM-7643
HM-7643A
HM-7643P
HM-7644

4D
4Z
4Z
4K
4Z
4Z
4Z
4Z
4K
4Z
4Z
4Z
4Z
4K
4K
4K
4K
4N
4N
4N
4N
4N
4N
4P

3L
3L
3F
3K
3L
3K
3L
3K
3K
3K
3K
3F
3F
3F
31=
3D
3D
3D
3D
3D
3D
3K

88
88
8F
88
88
88
88
8L
88
88
88
88
8F
8F
8F
BF
8e
8e
8e
8e
8e
8e
Be

*These package numbers to be used in product ordering. Other numbers shown in Selection Guide and drawings
are internal package numbers.

ttContact factory for latest availability of devices in these packages.

8-3

Selection Guide
(Continued)

PRODUCT
HM-7647R
HM-7648
HM-7649
HM-7680
HM-7680A
HM-7680R
HM-7680P
HM-7680RP
HM-768l
HM-7681A
HM-7681 R
HM-7681P
HM-7681RP
HM-7684
HM-7684P
HM-7685
HM-7685P
HM-76l60
HM-76161
JAN-0512

CERDIP

EPOXY

LEADLESStt

CERPACKtt

4K
4L
4L
4K
4K
4K
4K
4K
4K
4K
4K
4K
4K
5E
5E
5E
5E
5F
5F
4K

3F
3N
3N
3F
3F
3F
3F
3F
3F
3F
3F
3F
3F
3D
3D
3D
3D

4N
4M
5E
5E
5E
4P
4N
5E
5E
5F
5F
4N
4M
4N
4P

3D
3E
3T
LB
LB
3T
LB
3T
3K
3D
LA
3T
LB
3T
LB
3F
3F
LG
LA
3D
3E
3D
LA
3K
Leadless Array Package MA

8F
8D
8D
8F
8F
8F
8F
8F
8F
8F
8F
8F
8F
8H
8H
8H
8H
8L
8L

CMOS Memory
HM-6322
HM-6501
HM-6503
HM-6504
HM-6505
HM-6508
HM-6512
HM-6513
HM-6514
HM-6515
HM-6516
HM-6518
HM-6551
HM~6561

HM-6562
HM-6564
HM-661l
HM-6641
HM-6661
HM-6716
HM-6758

5C
5F
4N
5J
5J

8E
8H
8H
8H
8B
8C
8H
8C
8E
8C
8B
8B

LA
LG
LG

Mi croprocessor
HM-6l00
HD-610l

•

5H
5H

3H
3J

LG
LG

*These package numbers to be used in product ordering. Other numbers shown in Selection Guide and drawings
are internal package numbers .

ttContact factory for latest availability of devices in these packages.

NOTE FOR PACKAGE DRAWINGS ON FOLLOWING PAGES:

1.
2.
3.

All dimensions in inches; millimeters are shown in parentheses.
All dimensions i.Ol0 (±o.25mm) unless otherwise shown.
Internal package codes are shown in black squares.

8-4

Package Dimensions

11111

18 LEAD EPOXY DIP

III

22 LEAD EPOXY DIP

,300
(162)

.255!.OIO
(6.48.t.254)

(.46l±.076\

0.52\

III

24 LEAD EPOXY DIP

(::::::::::J~."
(3115+'2541
• -.

600/15.24)

,015TYP,

.DIU.D03

.IOOTYI'.

.06HYI'.

(.457±.078)

12.M)

(1.52)

(.162)

,600

r-U.9ITYP.l

.020 TYI'.

13.BU
.1211

~~i

40 LEAD EPOXY DIP

8:::::::::::Et~02';" TOPV".
I
III
~
I.51J'
'52,32',25"

125+010~.005

(3.171

l1li11

2.USOf,OID

?~II
r
!

.125 MIN.
,OIO±.DOZ

13.16MIN.l

0.52 TVP.)

.100TVI'.
/Z.S4TVPJ

l.254.t.051l

115.241 !(.Of,BEND

.150i.OD5

~3'''',''71:

I
,

!,oI'OD2TVP,tF+1
(.254 i.51 TV!'.)
-.

-- --

,OI8t003TVI'.
(.46:t016TYPJ

I""'"

OO·15e

1111

16 LEAD EPOXY DIP

20 LEAD EPOXY DIP

"~~~::::::::~

I[
W\,II
.020 TVI'.

1.1140*.010

(28.42 +.254)

TOPV' ..
.140:1:,005
/3.58t.127)

----1

Y'300G.

Jco~mp ~ J t2~:;0;,~
,nAI\T\'!

[

,1\1\1\1\

.I~;.:'r

I ",,",003 ".'00TYP~f-- (.46*,078)
TVP
(2.54/

.018:!; .003
(4.57±.076)

,IDOlYI'.

,OliaTYP,

,OlOt,D02

12.54)

(1.52)

1.254±.O5ll
1)0·150

8-5

OFBfND
(/.621

III

14 LEAD EPOXY DIP

III

14 LEAD CERDIP

E:::: ::[0.
7&"'"

IP:::~:~~
'''~_'.~'''.

,,;':,"

,,,,~~_"":'M~~I'12n
MIN.
(3.11)

•

.., I-:

.oIU.003 .IOOTYI'.
1.4S1±.OlS)
(2.54)

I '-----JO

:TIl

.~ " , .

IT,~~

00-1611

.01D! .00'

.0&0 TVI'.
IU2)

(.254±.061)

1111

-H...

24 LEAD CERDIP

[:::::::::J

1t'6T"' ' '~

""~i~l
"~t
I -j I- -11-_'II"
~ 138'-1.52'-1
oL

O
.
I.
220 MAX

132.771

.DSOTYP,
(1.62)

.160~O

-.,-

-11-

,018:1:,003
(.4Bi.07B)

22 LEAD CERDIP

J !it~1

::~

f4.06~4

12.541

I::~;:'~--\\-

95&:t015

1;''';'81'

~.220

.015-.080

.0181.003
\.4S7±.01&)

.540+.020

.2541

.100
TVI'.

[:::::::r"·

IS.59' .
1--,13.,...,,-1
-L
I
I

1." MAlt

,160t·

20 LEAD CERDIP

•

.080 TVP.
U.521

11111

-I.,,,f-{2.UI

f:~~:~~)

1 - 1- - , : : , : : : : : : ,

·I·,~:.,~x ~':'i:rf~

I~~~gl'
T
---l
-1~-

~ ~

,018:1:,003
1.4St.07S}

.080lYl'.
/1.521

~-1.,~

.IUOTYI'.
12.541

00.160

'-\\,010:1:.003
(.254:1:.076)

8-6

"''',~''''

1Jt---;,......---f\\

-I00.150

,::~:::'-\\--

TYP.

18 LEAD CERDIP

[::::::r'

ffi ."".'"
18~~ ~
l

11111

16 LEAD CERDIP

[:::::::1

14 LEAD CERDIP

~
~

TOPVIE.
!4'~~'

.715t,OI5

1----1'9.691.3811:

MAX

,,,,,,,,,~

~11.49~.254)

1-.77D··15-1
'::.'
~~~
14""mm~85MAX'
I .oj~WW I .•15!.06. -I I_ ~~:
119.56~.3811

.295:!:.OI

~mwm-WP1·
L

.ISOt,DID
f4.06:t.254)

.01St,003
(11.461:.08)

'015_060
1,:381-i.521

11fl

~IDoryp~

.080
0.52)

~
00-150

.3100.87J1,255!.OlQ'r

.066

i T t - (,381-1.521
12.541

(.457!:.1I16) (1.52)

•

16 LEAD CERDIP

.Ilin.!

: : : : : : :
.115+.015

I:~~VIE' 1_ .""""
14.6&1

h •." •.
' 'o'••,~M~X
1:

2541

(;r.~~1--I I-

1111::

-1I-~ ~

.OI8.!..ODl.060
L457:!:..n76) 11.52)
TVP

-j

I-

lDOryp.
(2.54)

00 _150

..·
II

40 LEAD CERDIP

f~~~::::::::::::::

_I'

>-i

2.06.t.020

'"
~(1S49) L

.2~~~;x~1

OIP.OOl

DaD TYP.

(.46 i ,016)

!I.521

.100 TVP. D81-1.521

L254±.076t

18 LEAD CERPACK

~IN

ONE 10ENT

PIN ONE 10ENTIFY

.0181:.002
HYP.I

.335*,010 SO.

-.-l

1.285 1:.015

f----12:~103 t±'~~~1l -

OS •
11271

II ---1f-

J9.18.t.2541 +J724t.3811-

-------i

J2.2!11
.041

oost.002

•

0IB!.002
1046':0051

.090 MAX.

1O·'Jr~

005!002

285t015
-r- 1l.24t381l

j-.

950 ~ .020
124.13!.0511

(1191

10.13!.O.OSI

+====~~~===--~
8-7

.010t.003

J2.&41

JO.46.:!:.0.0§1

530±0Isl'-

~~±. : J~;5" ~~

-11-

.0101.003
(.254:!:.016)

TOPVIEW

I ,...

(;~~:~~I~---.L l"'''''81l

16 LEAD CERPACK

TOPVEIW

L254!:.016)

•

.215+.010

~14.1m

2541-

Olot,OOl
lO.25t.08J

12.54\

TOPVIEW

090 MAX.
12.291

20 LEAD CERPACK

TOP VIEW

?~:

1011

L}:

".,,"

(24I!.tS08)

/" PINONEIDENT

~:L .,,".•

(l.19)

tl21 ! 0.05)

(REF.!

~ '~~7!':~:~~'

.9S0t.02D
(24.1310.51/

.047
11.191

24 LEAD CERPACK

18 LEAD CERPACK

TOPVIEW

TOP VIEW

,e;;-

r-PINONEIDENT.

1111

.510 t .010
112.95t.2541

'24

~
I

OS,
(1271

I
,

018+ 002

TVP~
.

""-'DO"

12 13

TVP-

1111'

--I f-

-9Sn±02012413±0511

..r

.__ ..

.385 t ,OHISQ.
t9.78 t .2S41

'+'

.9S0!.020
124.13!0.5U

0
0

018:!:. 002 I
HI.46!Q,05),

,;::::~.--J t ~:r11.191

.041
ILl!!)
REF

+===1C==::JIE~l..~1

L
1-

005t.002
10.13 ! 0.05)

.0471l.1SIREF'l

05 ±.0021.127±O,051

.090 MAX.
(2.291

11.24*.38_') ~

~:t"
.,B5'."'--IT

r--

090 MAX.
(229)

.041

.OOS!.OO2

TOP VIEW

I ' -I

- - 1918t254) ---'724t380-- OIB:!:. 002
(457!0051
950! 0211
•
(TVP)

22 LEAD CERPACK

rPINONEIDENT.

"'''IOS.

22 LEAD CERPACK

TOPVIEW

24 LEAD CERPACK

ToPVIEW

rP1N ONE IDENT.

.S10t.OlO
112.95 t .2641

.510t,010

.OI8:!:..DD2
iO.46tDOS)

-L

!L-__ .. ~~"9:::',::_-=·3811~:,:;041
r--1~385±.OI~I_f--1·285::t.015

124.13:!:.O.S1!

··
···•

111."!'.1541

11112

,PIN ONE IOENT.

..n..

121

.005:!:..OO2
IG.THO.OS)

--11.0911 MAX.

[2.291

L-_. -

.018+.002
1O.46!OOSI

1213

.3"'.'''_~h.185±.'~5 T

" .. 18t.2541~

t7.24±.38U

950!.020

'"1.191
REF.

.005!.002

-(24.13!0.51J-~---

.041
(1.19)

l~o","======~~~~~~=======:~=RE~F.
.- :
:

t=~:E=~:~~~
i

8-8

c
c
c
c

c
c

c
o

--1+1.090 MAX.
(2.291

14 LEAD FLATPACK

1111

18 LEAD LEADLESS CHIP CARRIER

TOP VIEW

J l:j
I

(l5~1

O(l5

Sr~G~7

.2ast,010
117.2410.2sll

!: '1r"0-1 :1250.:1:005

3S0 t .OIO

(1.1BIMAX

}05!C'.0=02=,,=.,=, =,=.05='~c=:5="
=5:====:=L~.025(0.641 REF.

-f
J'251

250 t
2S0 i 01Sj 018+001
Jl271
-(B35.t1271--(B35i"3811
1048!OOJI
' " - - - 7 S 0 ! 0 2 0 !190S!OSII---

.045.t.OI011!1.14.t0.25)

TOPVIEW

40 LEAD LEADLESS CHIP CARRIER

BOTTOM VIEW

40 LEAD 64K RAM MEMORY MODULE

TOP VIEW

)

+015.

r""01"Q~

.065.:1:.010

11.65'.2541

01
TOPV1EW

S1DEVIEW

.040
(1.021

Ff====~~~==~~~--'

.060
11.521

NOTCH ANGLE

~;:~02'

T tS 1)

TYPICAL LEAOLESS

CARRJERPACKAGE•

.040
(1.021

NO.1 LEAD

IDENTIFIER

BOTTOM VIEW

.010t,003
.254:1;.0761

•
8-9

9-1

Dice Ordering Information

GENERAL INFORMATION
Harris Memory Products are available in chip form to the hybrid micro circuit designer.
The standard chips are DC electrically tested at +250C to the data sheet limits for the
commercial device and are 100% visually inspected to MIL-STD-883, Method 2010, Condition B criteria. Packaging for shipment consists of waffle pack carriers plus an anti-static
cushioning strip for extra protection.
The hybrid industry has rapidly become more diversified and stringent in its requirements
for integrated circuits. To meet these demands Harris has several options additional to
standard chip processing available upon request at extra cost. For more information consult
the nearest Harris Sales Office.
CHIP ORDERING INFORMATION
Standard and special chip sales are direct factory order only. The minimum order on all
sales is $250.00 per line item. Contact the local Harris Sales Office for pricing and delivery
on special chip requirements.
MECHANICAL INFORMATION
Dimensions:

All chip dimensions nominal with a tolerance of ±.003". Maximum chip
thickness is .023".

Bonding Pads:

Minimum bonding pad size is .004" x .004" unless otherwise specified.

ELECTRICAL INFORMATION
CMOS:

Die substrate must be electrically connected to vce through conductive
die attach, to assure proper electrical operating characteristics.

Bipolar:

Die substrate can be electrically connected to ground, or can be left open,
but cannot be connected to vee.

PRODUCT CODE EXAMPLE

6508

H M 0

PREFI"J
H (Harris)

MODEL NUMBER

FAMILY:
M = Memory
D = Digital

TEMPERATURE:
6 = 25 0 C Probe'
0= Chip Form

*Contact Harris for
availability of -2
(-550C to +125 0 C)

dice.

9-2

Dice Geometry Index

Product

Drawing No.

HD-4702
HD-6101
HD-6402
HD-6408
HD-6409
HD-6431
HD-6433
HD-6432
HD-6434
HD-6435
HD-6436
HD-6440

1
2
3
4
5
6
6
7
8
9
10
11

HD-6495
HD-6600
HM-0104
HM-0168
HM-0186
HM-0198
HM-0410
HM-6100
HM-6322
HM-6501
HM-6503
HM-6504
HM-6505
HM-6508
HM-6512
HM-6513
HM-6514
HM-6515
HM-6516
HM-6518
HM-6551

Product

Drawing No.

HM-6561
HM-6562
HM-6611
HM-6641
HM-6661
HM-7602
HM-7603
HM-7608
HM-7680/80A/80R/80P/80RP
HM-7681/81A/81 R/81P/81 RP
HM-7610
HM-7611
HM-7610A
HM-7611A
HM-76160
HM-76161
HM-7620
HM-7621
HM-7620A
HM-7621A
HM-7640
HM-7641
HM-7642
HM-7643
HM-7644
HM-7642A
HM-7642P
HM-7643A
HM-7643P
HM-7647R
HM-7648
HM-7649

12
13
14
15
16
17
18
19
20
21
21
22
23
24
25,
25
26
26
27
28

29
30
31
32
33
34
34
35
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
42
43
43
43
43
44
44
44

9-3

HD-4702

HD-6101

119
MILS

100
MILS

1 - - - - - - - 1 3 0 MILS - - - - - - 1
f - - - - - - 97 MILS - - - - - - I

HD6402

HD-6408
PIN ONE

I
118

MILS

195
MILS

1-------115 MILS------I

\ - - - - - - 1 5 5 MILS

9-4

-----I

HD-6409

II·

ONE

HD-6431, HD-6433, HD-6495

107
MILS

1 - - - - - - 9 4 MILS - - - - - I

HD-6432

•

HD-6434

87
MILS
PII\I..-'Z'iil'"

ONE

1 - - - - - - 100 MILS - - - - - I

1 - - - - - - 94 MILS - - - - - I

•

III

HD-6435

HD.:.s436
PIN ONE

~----

III

MILS

r------

100 MILS - - , - - - - - - 1

100 MILS - - - - - - - I

HD-6440

t-------

88
MILS

9-6

-------1

III

HD-6600
PIN TWO

77
IMILS

1 - - - - - - - 1 0 9 MILS - - - - - ;

III

HM-0104

PIN
ONE

HM-0168

T
: :

~ 42 MILS

PIN
ON E

HM-0186

ONE~
•

•

= =1

---i

~41 MILS---1

III

HM-0198

wsls!s!;!-::.
T
r.::SSSSSSS'::lll
"-':'£££££££3
-:£i'Eri£i£..- 1

~3.5MILS~

HM-0410

MILS

1 - - - - 7 2 MILS

f---

9-7

47 MILS

-----1

•

·HM-6100

HM-6322

200
MILS

151
MILS

ONE

1-------219 MILS------i

~---- 137 MILS

.II

.HM-6503, HM-6504

HM-6501
NONE

198
MILS

1 - - - - - - - 1 3 2 MILS - - - - - - - - I

'I1 - - - - - - - 1 5 5 MILS - - - - - - - 1
, NOTE: OCTAGONAL PADS ARE NOT FOR BONDING.

9-8

III

HM-6505

HM-6508
PIN ONE

PIN ONE

150
MILS

1 - - - - - - 1 3 0 MILS - - - - - - I

1
1 - - - - - - 1 5 5 MILS

NOTE: OCTAGONAL PADS ARE NOT FOR BONDING.

HM-6512

HM-6513, HM-6514

PIN ONE

201
MILS

1 - - - - - - - 133 MILS - - - - - - I

1-------- 155 MI LS

NOTE: OCTAGONAL PADS ARE NOT FOR BONDING.

9-9

•

III

HM-6515, HM-6516

•

HM-6518

PIN ONE

262
MILS

1 - - - - - - 1 3 0 MILS - - - - - /

1 - - - - - - 207 M I L S - - - - - - l

HM-6551

HM-6561
. PIN ONE

1 - - - - - - - 1 3 2 MILS - - - - - /

1 - - - - - - 132 MILS - - - - - - 1

9-10

III

HM-6611
HM-6562

PIN ONE

182
MILS

1 - - - - - - - 1 3 2 MILS - - - - -

III

HM-6641

HM-6661

197

MILS

•
1 - - - - - 1 3 0 MILS------1

9-11

HM-7602, HM-7603

HM-7608, HM-7680/80A/80R/80P/80RP,
HM-7681/81A/81 R/81P/81 RP

I
166

MILS

1 - - - - - - - 1 7 3 MILS - - - - - - \

t - - - - - - 8 4 MILS - - - - - I

III

HM-7610, HM-7611

III

HM-7610A, HM-7611A
PIN ONE

1 - - - - - - 9 8 MILS - - - - - - I

9-12

III

HM-76160. HM-76161

HM-7620. HM-7621

233
MILS

1----107 MI LS - - - - I

133 - - - - ;
I - - - - MILS

HM-7620A. HM-7621A

III

HM-7640. HM-7641

II
1 - - - - - - 1 5 0 MI LS - - - - - - - 1

1 - - - - - 9 8 MILS - - - - - I

9-13

HM-7642, HM-7643, HM-7644

188

166

MILS

1-----

130MILS ---~

HM-7642A, HM-7642P, HM,:,7643A
HM-7643P
. ,

HM-7647R, HM-7648,
HM-7649
PIN ONE
(HM-7647R)

III
1 - - - - - 1 3 5 MILS----l

9-14

109 MILS - - - - I

OEM Sales Offices
NORTHEASTERN REGION
Suite 301
117 Worcester Street
Wellesley Hill, MA 02181
(617) 237-5430
Suite 273
555 Broadhollow Road
Melville, L.I., N.Y. 11747
(516) 249-4500
SOUTHEASTERN REGION
Suite 115
2020 W. McNab Road
Ft. Lauderdale, FL 33309
(305) 971-3200

Suite 325
650 Swedesford Road
Wayne, PA 19087
(215) 687-6680
CENTRAL REGION
17120 Dallas Parkway
Dallas, TX 75248
(214) 934-4237
Suite 206
5250 Far Hills Avenue
Kettering, OH 45429
(513) 433-5770
6400 Schafer Court
Suite 300
Rosemont, Illinois 60018
(312)692-4960

WESTERN REGION
Suite 227

21243 Ventura Boulevard
Woodland Hills, CA 91364
(213) 992-0686
Suite 320
1503 South Coast Drive
Costa Mesa, CA 92626
(714) 540-2176
Suite 300
625 Ell is Street
Mountain View, CA 94043
(415) 964-6443
33919 9th Avenue South
Federal Way, WA 98003
(206) 838-4878

International Sales

Europe
HEADQUARTERS

WEST GERMANY

DENMARK

Harris S.A.
Harris Semiconductor European
Headquarters, C/O Harris S.A.
6 Av Charles de Gaulle, Hall A
F-78510 Le Chesnay
Tel:
954-90-77
TWX: 842696514 F

Harris GmbH
Harris Semiconductor Div.
Einsteinstrasse 127
D-8 Munich 80
Tel:
089-47-30-47
TWX: 524126 HARMU D

Ditz Schweitzer A.S.
Vallensbaekvej 41
DK-2600 Glostrup
Tel:
02-453044
TWX: 33257 SCHWEI DK

EUROPEAN DISTRIBUTORS

Finn Metric OY
Ahertajantie 6 D/PL 35
SF-02101 Espoo 10
Finland
Tel:
460844
TWX: 122018

SALES OFFICES
AUSTRIA
ENGLAND
Harris Systems Ltd.
Harris Semiconductor Div.
P.O. Box 27, 145 Farnham Rd.
Slough SL 1 4XD
Tel:
(Slough) 34666
TWX: 848174 HARRIS G
FRANCE
Harris S.A.
Harris Semiconductor
6 Avenue Charles de Gaulle, Hall A
F-78510 Le Chesnay
Tel:
954-90-77
TWX: 842696514 HARRIS P

Kontron GmbH
Industriestrasse B 13
2345 Brunn am Gebirge
Tel:
02236/86631
TWX: 79337 KONIN A
BELGIUM
Betea S.A.
775 Chausee de Louvain
B-1140 Brussels
Tel:
02-7368050
TWX: 23188 BETEA B

10-1

FINLAND

FRANCE
Almex S.A.
48 rue de l'Aubepine
F-92160 Antony
Tel:
666-21-12
TWX: 250067 ALMEX
A2M
18 Avenue Dutartre
F-78150 Le Chesnay
Tel:
955-32-49
TWX: 698376 AMM

EUROPEAN DISTRIBUTORS
(Continued)

Spetelec
Tour Europa-III
94532 Rungis Cedex
Tel:
6865665
TWX: 250801 THAI
GERMANY
Alfred Neye-Enatechnik GmbH
Sch i II erstrasse 14
2085 Quickborn b. Hamburg
041066121
Tel:
TWX: 02-13590 ENA D
Kontron Elektronik GmbH
Breslauer Str. 2
D-8057 Eching b. Munich
089319011
Tel:
TWX: 0522122 KONEL D
Jermyn GmbH
Schulstrasse 36
D-6277 Camberg-Wurges
Tel:
(06434) 6005
TWX: 484426 JERM D
ITALY
Erie Elettronica SpA
Via Melchiorre Gioia 66
1-20125 Milano
(2) 6884833/4/5
Tel:
TWX: 36385 ERIE MIL
Lasi Elettronica
Via Ie Lombardia, 6
1-20092 Cinisello Balsamo
Tel:
(2) 9273578
TWX: 37612 LASI MIL
NETHERLANDS
Techmation Electronics B.V.
Nieuwe Meerdijk, 31
P.O. Box 31
NL-1170 AA Badhoevedorp
Tel:
02968-6451
TWX: 18612 TELCO NL
NORWAY
EGA A.S.
Ulvenveien 75
P.O. Box 53
Oekern, N-oslo 5
Tel:
+472221900
TWX: 11 265A EGA N
SPAIN & PORTUGAL
Unitronics S.A.
Princesa No.1
Torre de Madrid
Planta 12-0fficina 9
Madrid, Spain
Tel:
2425204
TLX: 22596 UTRON
SWEDEN

SWITZERLAND
Stolz A.G.
Taefernstrasse 15
CH 5405 Baden-Daettwil
Tel:
0568401 51
. TWX: 54070 STLZ CH
UNITED KINGDOM & IRELAND

India
American Components Inc.
For Sujata Sales and Exports Ltd.
3350 Scott Blvd., Bldg. 15
Santa Clara, CA, U.S.A. 95051
Tel:
(408) 727-2440
TLX: 352073 EL COMP SNTA

Macro Marketi ng Ltd.
396 Bath Road
Slough, Berks, U.K.
Tel:
(06286) 4422
TWX: 847945 APEX G
Hy-Comp Ltd.
7, Shield Road
(Ashford Industrial Est.)
Ashford, Middlesex
TW151AV
Tel:
0784246273
TWX: 923802 HY COMP G
Jermyn Holdings Ltd.
Vestry Estate
Sevenoaks, Kent, U.K.
Tel:
073250144
TWX: 95142 JERMYN G
Memec Ltd.
Thame Park Ind. Estate
Thame, Oxon OX9, 3RS, U.K.
Tel:
084421 3146
TWX: 837508 MEMEC G
Phoenix Electronics Ltd.
Western Buildings
Vere Road
Kirkmuirhill, Lanksh.
ML11 9RP, Scotland
Tel:
055589-2393
TWX: 777404 FENIX G

Far East
OEM SALES OFFICE
JAPAN
Harris Semiconductor Inc.
Far East Branch
Suzuya Bldg., 2F
8-1 Shinsen-cho
Shibuya-ku, Tokyo 150
Tel:
03-476-5581
TWX: J 26525 HARRISFE

FAR EAST DISTRIBUTORS
AUSTRALIA
CEMA (Distrb.) Pty. Ltd.
21 Chandos Street
Crows Nest, N.S.w. 2065
Tel:
439-4655
TWX: A22846 CEMA AA

A B Betoma
Box 3005
S-171 03 Solna 3
08-820280
Tel:
TWX: 19389 BETOMA S

10-2

HOME OFFICE
P.O. Box 883
Melbourne, FL 32901
Tel:
(305) 724-7000
TWX: 510-959-6259

Harris Technology:

Your competitive edge.

Innovative technology from Harris can be translated into technical advantages for your product
or a more competitive and cost effective means of solving your customer's needs. Over the
years Harris has pioneered in developing sophisticated processes such as dielectric isolation (DI),
and is known for expertise in thin-film technology, dielectrically isolated high voltage CMOS,
and its unique self-aligned silicon gate CMoS process which yields ICs with superior speed/
power/density characteristics.
These state-of-the-art processes have spawned a wide family of analog and digital devices
which offer designers higher performance and raise the level of system reliability. Advanced
linear products include the first monolithic 12-bit D/A converter, high performance operational
amplifiers, and the most complete family of CMOS and bipolar analog switches. Digital products include a complete range of bipolar PROMs from 256 to 8K bits, CMOS memories, and a
CMOS 12-bit microprocessor.
Let Harris technology go to work for you and supply that elusive competitive edge ... that extra
something to help you meet the challenge of competition and succeed.

Harris offers:
ANALOG

DIGITAL

Operational Amplifiers
Quad Comparators
Switches
Multiplexers
Sample and Hold
D/ A Converters
AID Converters
Precision Voltage References
Delta Modulators (CVSD)
Keyboard Encoders
Line Drivers/Receivers

Bipolar PROMs
CMOS RAMs, ROMs, PROMs
Microprocessors
CMOS LSI Logic

III
10-3

HARRIS
SEMICONDUCTOR
PRODUCTS DIVISION
A DIVISION OF HARRIS CORPORATION

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1981_Harris_Digital_Data_Book_Bipolar_CMOS_Volume_2 1981 Harris Digital Data Book Bipolar CMOS Volume 2

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